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.triton/dump/0bb244fe116b8bad2e3be6ce32964a26/triton_.llir

@@ -0,0 +1,366 @@
+; ModuleID = 'LLVMDialectModule'
+source_filename = "LLVMDialectModule"
+
+@global_smem = external addrspace(3) global [0 x i8]
+@.str = private unnamed_addr constant [11 x i8] c"__CUDA_FTZ\00", align 1
+
+define void @triton__0d1d2d3d4d5d6d7d8de9de(ptr addrspace(1) %0, ptr addrspace(1) %1, ptr addrspace(1) %2, ptr addrspace(1) %3, ptr addrspace(1) %4, ptr addrspace(1) %5, ptr addrspace(1) %6, ptr addrspace(1) %7, i32 %8, i32 %9) local_unnamed_addr !dbg !7 {
+  %11 = tail call i32 @llvm.nvvm.read.ptx.sreg.tid.x(), !dbg !10
+  %12 = and i32 %11, 31, !dbg !10
+  %13 = lshr i32 %11, 5, !dbg !10
+  %14 = and i32 %13, 1, !dbg !10
+  %urem = shl i32 %11, 2, !dbg !10
+  %15 = and i32 %urem, 252, !dbg !10
+  %16 = tail call i32 asm "mov.u32 $0, %ctaid.x;", "=r"() #6, !dbg !11
+  %17 = shl i32 %16, 8, !dbg !12
+  %18 = or i32 %17, %15, !dbg !13
+  %19 = sext i32 %18 to i64, !dbg !14
+  %20 = getelementptr float, ptr addrspace(1) %0, i64 %19, !dbg !14
+  %21 = tail call { i32, i32, i32, i32 } asm sideeffect "mov.u32 $0, 0x0;\0A\09mov.u32 $1, 0x0;\0A\09mov.u32 $2, 0x0;\0A\09mov.u32 $3, 0x0;\0A\09@$5 ld.global.v4.b32 { $0, $1, $2, $3 }, [ $4 + 0 ];\0A\09@!$7 mov.u32 $0, $6;\0A\09@!$9 mov.u32 $1, $8;\0A\09@!$11 mov.u32 $2, $10;\0A\09@!$13 mov.u32 $3, $12;", "=r,=r,=r,=r,l,b,r,b,r,b,r,b,r,b"(ptr addrspace(1) %20, i1 true, i32 0, i1 true, i32 0, i1 true, i32 0, i1 true, i32 0, i1 true) #6, !dbg !15
+  %22 = extractvalue { i32, i32, i32, i32 } %21, 0, !dbg !15
+  %23 = extractvalue { i32, i32, i32, i32 } %21, 1, !dbg !15
+  %24 = extractvalue { i32, i32, i32, i32 } %21, 2, !dbg !15
+  %25 = extractvalue { i32, i32, i32, i32 } %21, 3, !dbg !15
+  %26 = bitcast i32 %22 to float, !dbg !15
+  %27 = bitcast i32 %23 to float, !dbg !15
+  %28 = bitcast i32 %24 to float, !dbg !15
+  %29 = bitcast i32 %25 to float, !dbg !15
+  %30 = getelementptr i16, ptr addrspace(1) %1, i64 %19, !dbg !16
+  %31 = tail call { i32, i32 } asm sideeffect "mov.u32 $0, 0x0;\0A\09mov.u32 $1, 0x0;\0A\09@$3 ld.global.v2.b32 { $0, $1 }, [ $2 + 0 ];\0A\09@!$5 mov.u32 $0, $4;\0A\09@!$7 mov.u32 $1, $6;", "=r,=r,l,b,r,b,r,b"(ptr addrspace(1) %30, i1 true, i32 0, i1 true, i32 0, i1 true) #6, !dbg !17
+  %32 = extractvalue { i32, i32 } %31, 0, !dbg !17
+  %33 = extractvalue { i32, i32 } %31, 1, !dbg !17
+  %34 = trunc i32 %32 to i16, !dbg !17
+  %extelt.offset = lshr i32 %32, 16, !dbg !17
+  %35 = trunc i32 %extelt.offset to i16, !dbg !17
+  %36 = trunc i32 %33 to i16, !dbg !17
+  %extelt.offset1 = lshr i32 %33, 16, !dbg !17
+  %37 = trunc i32 %extelt.offset1 to i16, !dbg !17
+  %38 = tail call float asm "cvt.f32.bf16 $0, $1;", "=r,h"(i16 %34) #6, !dbg !18
+  %39 = tail call float asm "cvt.f32.bf16 $0, $1;", "=r,h"(i16 %35) #6, !dbg !18
+  %40 = tail call float asm "cvt.f32.bf16 $0, $1;", "=r,h"(i16 %36) #6, !dbg !18
+  %41 = tail call float asm "cvt.f32.bf16 $0, $1;", "=r,h"(i16 %37) #6, !dbg !18
+  %42 = getelementptr i16, ptr addrspace(1) %2, i64 %19, !dbg !19
+  %43 = tail call { i32, i32 } asm sideeffect "mov.u32 $0, 0x0;\0A\09mov.u32 $1, 0x0;\0A\09@$3 ld.global.v2.b32 { $0, $1 }, [ $2 + 0 ];\0A\09@!$5 mov.u32 $0, $4;\0A\09@!$7 mov.u32 $1, $6;", "=r,=r,l,b,r,b,r,b"(ptr addrspace(1) %42, i1 true, i32 0, i1 true, i32 0, i1 true) #6, !dbg !20
+  %44 = extractvalue { i32, i32 } %43, 0, !dbg !20
+  %45 = extractvalue { i32, i32 } %43, 1, !dbg !20
+  %46 = trunc i32 %44 to i16, !dbg !20
+  %extelt.offset2 = lshr i32 %44, 16, !dbg !20
+  %47 = trunc i32 %extelt.offset2 to i16, !dbg !20
+  %48 = trunc i32 %45 to i16, !dbg !20
+  %extelt.offset3 = lshr i32 %45, 16, !dbg !20
+  %49 = trunc i32 %extelt.offset3 to i16, !dbg !20
+  %50 = tail call float asm "cvt.f32.bf16 $0, $1;", "=r,h"(i16 %46) #6, !dbg !21
+  %51 = tail call float asm "cvt.f32.bf16 $0, $1;", "=r,h"(i16 %47) #6, !dbg !21
+  %52 = tail call float asm "cvt.f32.bf16 $0, $1;", "=r,h"(i16 %48) #6, !dbg !21
+  %53 = tail call float asm "cvt.f32.bf16 $0, $1;", "=r,h"(i16 %49) #6, !dbg !21
+  %54 = getelementptr i16, ptr addrspace(1) %3, i64 %19, !dbg !22
+  %55 = tail call { i32, i32 } asm sideeffect "mov.u32 $0, 0x0;\0A\09mov.u32 $1, 0x0;\0A\09@$3 ld.global.v2.b32 { $0, $1 }, [ $2 + 0 ];\0A\09@!$5 mov.u32 $0, $4;\0A\09@!$7 mov.u32 $1, $6;", "=r,=r,l,b,r,b,r,b"(ptr addrspace(1) %54, i1 true, i32 0, i1 true, i32 0, i1 true) #6, !dbg !23
+  %56 = extractvalue { i32, i32 } %55, 0, !dbg !23
+  %57 = extractvalue { i32, i32 } %55, 1, !dbg !23
+  %58 = trunc i32 %56 to i16, !dbg !23
+  %extelt.offset4 = lshr i32 %56, 16, !dbg !23
+  %59 = trunc i32 %extelt.offset4 to i16, !dbg !23
+  %60 = trunc i32 %57 to i16, !dbg !23
+  %extelt.offset5 = lshr i32 %57, 16, !dbg !23
+  %61 = trunc i32 %extelt.offset5 to i16, !dbg !23
+  %62 = tail call float asm "cvt.f32.bf16 $0, $1;", "=r,h"(i16 %58) #6, !dbg !24
+  %63 = tail call float asm "cvt.f32.bf16 $0, $1;", "=r,h"(i16 %59) #6, !dbg !24
+  %64 = tail call float asm "cvt.f32.bf16 $0, $1;", "=r,h"(i16 %60) #6, !dbg !24
+  %65 = tail call float asm "cvt.f32.bf16 $0, $1;", "=r,h"(i16 %61) #6, !dbg !24
+  %66 = getelementptr i16, ptr addrspace(1) %4, i64 %19, !dbg !25
+  %67 = tail call { i32, i32 } asm sideeffect "mov.u32 $0, 0x0;\0A\09mov.u32 $1, 0x0;\0A\09@$3 ld.global.v2.b32 { $0, $1 }, [ $2 + 0 ];\0A\09@!$5 mov.u32 $0, $4;\0A\09@!$7 mov.u32 $1, $6;", "=r,=r,l,b,r,b,r,b"(ptr addrspace(1) %66, i1 true, i32 0, i1 true, i32 0, i1 true) #6, !dbg !26
+  %68 = extractvalue { i32, i32 } %67, 0, !dbg !26
+  %69 = extractvalue { i32, i32 } %67, 1, !dbg !26
+  %70 = trunc i32 %68 to i16, !dbg !26
+  %extelt.offset6 = lshr i32 %68, 16, !dbg !26
+  %71 = trunc i32 %extelt.offset6 to i16, !dbg !26
+  %72 = trunc i32 %69 to i16, !dbg !26
+  %extelt.offset7 = lshr i32 %69, 16, !dbg !26
+  %73 = trunc i32 %extelt.offset7 to i16, !dbg !26
+  %74 = tail call float asm "cvt.f32.bf16 $0, $1;", "=r,h"(i16 %70) #6, !dbg !27
+  %75 = tail call float asm "cvt.f32.bf16 $0, $1;", "=r,h"(i16 %71) #6, !dbg !27
+  %76 = tail call float asm "cvt.f32.bf16 $0, $1;", "=r,h"(i16 %72) #6, !dbg !27
+  %77 = tail call float asm "cvt.f32.bf16 $0, $1;", "=r,h"(i16 %73) #6, !dbg !27
+  %78 = zext nneg i32 %15 to i64, !dbg !28
+  %79 = getelementptr float, ptr addrspace(1) %5, i64 %78, !dbg !28
+  %80 = tail call { i32, i32, i32, i32 } asm sideeffect "mov.u32 $0, 0x0;\0A\09mov.u32 $1, 0x0;\0A\09mov.u32 $2, 0x0;\0A\09mov.u32 $3, 0x0;\0A\09@$5 ld.global.L1::evict_last.v4.b32 { $0, $1, $2, $3 }, [ $4 + 0 ];\0A\09@!$7 mov.u32 $0, $6;\0A\09@!$9 mov.u32 $1, $8;\0A\09@!$11 mov.u32 $2, $10;\0A\09@!$13 mov.u32 $3, $12;", "=r,=r,=r,=r,l,b,r,b,r,b,r,b,r,b"(ptr addrspace(1) %79, i1 true, i32 0, i1 true, i32 0, i1 true, i32 0, i1 true, i32 0, i1 true) #6, !dbg !29
+  %81 = fadd float %38, %26, !dbg !30
+  %82 = fadd float %39, %27, !dbg !30
+  %83 = fadd float %40, %28, !dbg !30
+  %84 = fadd float %81, %50, !dbg !31
+  %85 = fadd float %82, %51, !dbg !31
+  %86 = fadd float %83, %52, !dbg !31
+  %87 = fadd float %85, %63, !dbg !32
+  %88 = fadd float %86, %64, !dbg !32
+  %89 = fadd float %87, %75, !dbg !33
+  %90 = fadd float %88, %76, !dbg !33
+  %91 = insertelement <2 x float> poison, float %84, i64 0, !dbg !32
+  %92 = insertelement <2 x float> %91, float %41, i64 1, !dbg !32
+  %93 = insertelement <2 x float> poison, float %62, i64 0, !dbg !32
+  %94 = insertelement <2 x float> %93, float %29, i64 1, !dbg !32
+  %95 = fadd <2 x float> %92, %94, !dbg !32
+  %96 = insertelement <2 x float> poison, float %74, i64 0, !dbg !33
+  %97 = insertelement <2 x float> %96, float %53, i64 1, !dbg !33
+  %98 = fadd <2 x float> %95, %97, !dbg !33
+  %99 = insertelement <2 x float> poison, float %89, i64 0, !dbg !34
+  %100 = insertelement <2 x float> %99, float %65, i64 1, !dbg !34
+  %101 = fadd <2 x float> %98, %100, !dbg !34
+  %102 = insertelement <2 x float> poison, float %90, i64 0, !dbg !34
+  %103 = insertelement <2 x float> %102, float %77, i64 1, !dbg !34
+  %104 = fadd <2 x float> %101, %103, !dbg !34
+  %105 = extractelement <2 x float> %104, i64 0, !dbg !34
+  %106 = extractelement <2 x float> %104, i64 1, !dbg !34
+  %107 = fadd float %105, %106, !dbg !34
+  %108 = bitcast float %107 to i32, !dbg !40
+  %109 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %108, i32 16, i32 31), !dbg !40
+  %110 = bitcast i32 %109 to float, !dbg !40
+  %111 = fadd float %107, %110, !dbg !34
+  %112 = bitcast float %111 to i32, !dbg !40
+  %113 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %112, i32 8, i32 31), !dbg !40
+  %114 = bitcast i32 %113 to float, !dbg !40
+  %115 = fadd float %111, %114, !dbg !34
+  %116 = bitcast float %115 to i32, !dbg !40
+  %117 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %116, i32 4, i32 31), !dbg !40
+  %118 = bitcast i32 %117 to float, !dbg !40
+  %119 = fadd float %115, %118, !dbg !34
+  %120 = bitcast float %119 to i32, !dbg !40
+  %121 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %120, i32 2, i32 31), !dbg !40
+  %122 = bitcast i32 %121 to float, !dbg !40
+  %123 = fadd float %119, %122, !dbg !34
+  %124 = bitcast float %123 to i32, !dbg !40
+  %125 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %124, i32 1, i32 31), !dbg !40
+  %126 = bitcast i32 %125 to float, !dbg !40
+  %127 = fadd float %123, %126, !dbg !34
+  %128 = icmp eq i32 %12, 0, !dbg !40
+  %129 = zext nneg i32 %14 to i64, !dbg !40
+  %130 = getelementptr float, ptr addrspace(3) @global_smem, i64 %129, !dbg !40
+  tail call void asm sideeffect "@$2 st.shared.b32 [ $0 + 0 ], $1;", "r,r,b"(ptr addrspace(3) %130, float %127, i1 %128) #6, !dbg !40
+  tail call void @llvm.nvvm.barrier0(), !dbg !40
+  %131 = icmp slt i32 %11, 2, !dbg !40
+  %132 = sext i32 %11 to i64, !dbg !40
+  %133 = getelementptr float, ptr addrspace(3) @global_smem, i64 %132, !dbg !40
+  %134 = tail call float asm sideeffect "@$2 ld.shared.b32 $0, [ $1 + 0 ];", "=r,r,b"(ptr addrspace(3) %133, i1 %131) #6, !dbg !40
+  %135 = bitcast float %134 to i32, !dbg !40
+  %136 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %135, i32 1, i32 31), !dbg !40
+  %137 = bitcast i32 %136 to float, !dbg !40
+  %138 = fadd float %134, %137, !dbg !34
+  %139 = and i32 %11, 1, !dbg !40
+  %140 = icmp eq i32 %139, 0, !dbg !40
+  %141 = and i1 %131, %140, !dbg !40
+  tail call void asm sideeffect "@$2 st.shared.b32 [ $0 + 0 ], $1;", "r,r,b"(ptr addrspace(3) %133, float %138, i1 %141) #6, !dbg !40
+  tail call void @llvm.nvvm.barrier0(), !dbg !40
+  %142 = load float, ptr addrspace(3) @global_smem, align 4, !dbg !40
+  %143 = fadd float %142, 0.000000e+00, !dbg !42
+  %144 = tail call float asm "div.full.f32 $0, $1, $2;", "=r,r,r"(float %143, float 2.560000e+02) #6, !dbg !46
+  %145 = extractelement <2 x float> %98, i64 0, !dbg !47
+  %146 = fsub float %145, %144, !dbg !47
+  %147 = fsub float %89, %144, !dbg !47
+  %148 = fsub float %90, %144, !dbg !47
+  %149 = fsub float %106, %144, !dbg !47
+  %150 = fmul float %146, %146, !dbg !48
+  %151 = fmul float %147, %147, !dbg !48
+  %152 = fmul float %148, %148, !dbg !48
+  %153 = fmul float %149, %149, !dbg !48
+  tail call void @llvm.nvvm.barrier0(), !dbg !49
+  %154 = fadd float %150, %151, !dbg !51
+  %155 = fadd float %152, %154, !dbg !51
+  %156 = fadd float %153, %155, !dbg !51
+  %157 = bitcast float %156 to i32, !dbg !49
+  %158 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %157, i32 16, i32 31), !dbg !49
+  %159 = bitcast i32 %158 to float, !dbg !49
+  %160 = fadd float %156, %159, !dbg !51
+  %161 = bitcast float %160 to i32, !dbg !49
+  %162 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %161, i32 8, i32 31), !dbg !49
+  %163 = bitcast i32 %162 to float, !dbg !49
+  %164 = fadd float %160, %163, !dbg !51
+  %165 = bitcast float %164 to i32, !dbg !49
+  %166 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %165, i32 4, i32 31), !dbg !49
+  %167 = bitcast i32 %166 to float, !dbg !49
+  %168 = fadd float %164, %167, !dbg !51
+  %169 = bitcast float %168 to i32, !dbg !49
+  %170 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %169, i32 2, i32 31), !dbg !49
+  %171 = bitcast i32 %170 to float, !dbg !49
+  %172 = fadd float %168, %171, !dbg !51
+  %173 = bitcast float %172 to i32, !dbg !49
+  %174 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %173, i32 1, i32 31), !dbg !49
+  %175 = bitcast i32 %174 to float, !dbg !49
+  %176 = fadd float %172, %175, !dbg !51
+  tail call void asm sideeffect "@$2 st.shared.b32 [ $0 + 0 ], $1;", "r,r,b"(ptr addrspace(3) %130, float %176, i1 %128) #6, !dbg !49
+  tail call void @llvm.nvvm.barrier0(), !dbg !49
+  %177 = tail call float asm sideeffect "@$2 ld.shared.b32 $0, [ $1 + 0 ];", "=r,r,b"(ptr addrspace(3) %133, i1 %131) #6, !dbg !49
+  %178 = bitcast float %177 to i32, !dbg !49
+  %179 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %178, i32 1, i32 31), !dbg !49
+  %180 = bitcast i32 %179 to float, !dbg !49
+  %181 = fadd float %177, %180, !dbg !51
+  tail call void asm sideeffect "@$2 st.shared.b32 [ $0 + 0 ], $1;", "r,r,b"(ptr addrspace(3) %133, float %181, i1 %141) #6, !dbg !49
+  tail call void @llvm.nvvm.barrier0(), !dbg !49
+  %182 = load float, ptr addrspace(3) @global_smem, align 4, !dbg !49
+  %183 = fadd float %182, 0.000000e+00, !dbg !54
+  %184 = tail call float asm "div.full.f32 $0, $1, $2;", "=r,r,r"(float %183, float 2.560000e+02) #6, !dbg !56
+  %185 = fadd float %184, 0x3EE4F8B580000000, !dbg !57
+  %186 = tail call i32 @__nvvm_reflect(ptr nonnull @.str) #6, !dbg !58
+  %.not.i = icmp eq i32 %186, 0, !dbg !58
+  br i1 %.not.i, label %189, label %187, !dbg !58
+
+187:                                              ; preds = %10
+  %188 = tail call float @llvm.nvvm.rsqrt.approx.ftz.f(float %185), !dbg !58
+  br label %__nv_rsqrtf.exit, !dbg !58
+
+189:                                              ; preds = %10
+  %190 = tail call float @llvm.nvvm.rsqrt.approx.f(float %185), !dbg !58
+  br label %__nv_rsqrtf.exit, !dbg !58
+
+__nv_rsqrtf.exit:                                 ; preds = %187, %189
+  %.0.i = phi float [ %188, %187 ], [ %190, %189 ], !dbg !58
+  %191 = extractvalue { i32, i32, i32, i32 } %80, 3, !dbg !29
+  %192 = bitcast i32 %191 to float, !dbg !29
+  %193 = extractvalue { i32, i32, i32, i32 } %80, 2, !dbg !29
+  %194 = bitcast i32 %193 to float, !dbg !29
+  %195 = extractvalue { i32, i32, i32, i32 } %80, 1, !dbg !29
+  %196 = bitcast i32 %195 to float, !dbg !29
+  %197 = extractvalue { i32, i32, i32, i32 } %80, 0, !dbg !29
+  %198 = bitcast i32 %197 to float, !dbg !29
+  %199 = fmul float %146, %.0.i, !dbg !59
+  %200 = fmul float %147, %.0.i, !dbg !59
+  %201 = fmul float %148, %.0.i, !dbg !59
+  %202 = fmul float %149, %.0.i, !dbg !59
+  %203 = fmul float %199, %198, !dbg !60
+  %204 = fmul float %200, %196, !dbg !60
+  %205 = fmul float %201, %194, !dbg !60
+  %206 = fmul float %202, %192, !dbg !60
+  %207 = getelementptr float, ptr addrspace(1) %6, i64 %19, !dbg !61
+  %208 = bitcast float %145 to i32, !dbg !62
+  %209 = bitcast float %89 to i32, !dbg !62
+  %210 = bitcast float %90 to i32, !dbg !62
+  %211 = bitcast float %106 to i32, !dbg !62
+  tail call void asm sideeffect "@$5 st.global.v4.b32 [ $4 + 0 ], { $0, $1, $2, $3 };", "r,r,r,r,l,b"(i32 %208, i32 %209, i32 %210, i32 %211, ptr addrspace(1) %207, i1 true) #6, !dbg !62
+  %212 = getelementptr i16, ptr addrspace(1) %7, i64 %19, !dbg !63
+  %213 = tail call i16 asm "cvt.rn.bf16.f32 $0, $1;", "=h,r"(float %203) #6, !dbg !64
+  %214 = tail call i16 asm "cvt.rn.bf16.f32 $0, $1;", "=h,r"(float %204) #6, !dbg !64
+  %215 = tail call i16 asm "cvt.rn.bf16.f32 $0, $1;", "=h,r"(float %205) #6, !dbg !64
+  %216 = tail call i16 asm "cvt.rn.bf16.f32 $0, $1;", "=h,r"(float %206) #6, !dbg !64
+  %217 = insertelement <2 x i16> undef, i16 %213, i64 0, !dbg !64
+  %218 = insertelement <2 x i16> %217, i16 %214, i64 1, !dbg !64
+  %219 = bitcast <2 x i16> %218 to i32, !dbg !64
+  %220 = insertelement <2 x i16> undef, i16 %215, i64 0, !dbg !64
+  %221 = insertelement <2 x i16> %220, i16 %216, i64 1, !dbg !64
+  %222 = bitcast <2 x i16> %221 to i32, !dbg !64
+  tail call void asm sideeffect "@$3 st.global.v2.b32 [ $2 + 0 ], { $0, $1 };", "r,r,l,b"(i32 %219, i32 %222, ptr addrspace(1) %212, i1 true) #6, !dbg !64
+  ret void, !dbg !65
+}
+
+; Function Attrs: mustprogress nocallback nofree nosync nounwind speculatable willreturn memory(none)
+declare noundef i32 @llvm.nvvm.read.ptx.sreg.tid.x() #0
+
+; Function Attrs: convergent nocallback nounwind memory(inaccessiblemem: readwrite)
+declare i32 @llvm.nvvm.shfl.sync.bfly.i32(i32, i32, i32, i32) #1
+
+; Function Attrs: convergent nocallback nounwind
+declare void @llvm.nvvm.barrier0() #2
+
+; Function Attrs: alwaysinline nounwind
+define float @__nv_rsqrtf(float %x) local_unnamed_addr #3 {
+  %1 = tail call i32 @__nvvm_reflect(ptr nonnull @.str) #6
+  %.not = icmp eq i32 %1, 0
+  br i1 %.not, label %4, label %2
+
+2:                                                ; preds = %0
+  %3 = tail call float @llvm.nvvm.rsqrt.approx.ftz.f(float %x)
+  br label %6
+
+4:                                                ; preds = %0
+  %5 = tail call float @llvm.nvvm.rsqrt.approx.f(float %x)
+  br label %6
+
+6:                                                ; preds = %4, %2
+  %.0 = phi float [ %3, %2 ], [ %5, %4 ]
+  ret float %.0
+}
+
+declare i32 @__nvvm_reflect(ptr) local_unnamed_addr #4
+
+; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(none)
+declare float @llvm.nvvm.rsqrt.approx.ftz.f(float) #5
+
+; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(none)
+declare float @llvm.nvvm.rsqrt.approx.f(float) #5
+
+attributes #0 = { mustprogress nocallback nofree nosync nounwind speculatable willreturn memory(none) }
+attributes #1 = { convergent nocallback nounwind memory(inaccessiblemem: readwrite) }
+attributes #2 = { convergent nocallback nounwind }
+attributes #3 = { alwaysinline nounwind "disable-tail-calls"="false" "frame-pointer"="all" "less-precise-fpmad"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #4 = { "disable-tail-calls"="false" "frame-pointer"="all" "less-precise-fpmad"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #5 = { mustprogress nocallback nofree nosync nounwind willreturn memory(none) }
+attributes #6 = { nounwind }
+
+!llvm.module.flags = !{!0, !1}
+!llvm.dbg.cu = !{!2}
+!nvvm.annotations = !{!4, !5, !5, !4}
+!llvm.ident = !{!6}
+
+!0 = !{i32 2, !"Debug Info Version", i32 3}
+!1 = !{i32 4, !"nvvm-reflect-ftz", i32 1}
+!2 = distinct !DICompileUnit(language: DW_LANG_C, file: !3, producer: "triton", isOptimized: true, runtimeVersion: 0, emissionKind: FullDebug)
+!3 = !DIFile(filename: "cybxnh26qvsbmxmvdr54vaav2ezk2qxu7562fhhsn4lvyvqgoglw.py", directory: "/tmp/torchinductor_root/yb")
+!4 = !{ptr @triton__0d1d2d3d4d5d6d7d8de9de, !"kernel", i32 1}
+!5 = !{ptr @triton__0d1d2d3d4d5d6d7d8de9de, !"maxntidx", i32 64}
+!6 = !{!"clang version 3.8.0 (tags/RELEASE_380/final)"}
+!7 = distinct !DISubprogram(name: "triton__0d1d2d3d4d5d6d7d8de9de", linkageName: "triton__0d1d2d3d4d5d6d7d8de9de", scope: !3, file: !3, line: 18, type: !8, scopeLine: 18, spFlags: DISPFlagDefinition | DISPFlagOptimized, unit: !2)
+!8 = !DISubroutineType(cc: DW_CC_normal, types: !9)
+!9 = !{}
+!10 = !DILocation(line: 26, column: 26, scope: !7)
+!11 = !DILocation(line: 23, column: 28, scope: !7)
+!12 = !DILocation(line: 30, column: 40, scope: !7)
+!13 = !DILocation(line: 30, column: 36, scope: !7)
+!14 = !DILocation(line: 30, column: 30, scope: !7)
+!15 = !DILocation(line: 30, column: 46, scope: !7)
+!16 = !DILocation(line: 31, column: 30, scope: !7)
+!17 = !DILocation(line: 31, column: 46, scope: !7)
+!18 = !DILocation(line: 31, column: 67, scope: !7)
+!19 = !DILocation(line: 32, column: 30, scope: !7)
+!20 = !DILocation(line: 32, column: 46, scope: !7)
+!21 = !DILocation(line: 32, column: 67, scope: !7)
+!22 = !DILocation(line: 33, column: 30, scope: !7)
+!23 = !DILocation(line: 33, column: 46, scope: !7)
+!24 = !DILocation(line: 33, column: 67, scope: !7)
+!25 = !DILocation(line: 34, column: 31, scope: !7)
+!26 = !DILocation(line: 34, column: 47, scope: !7)
+!27 = !DILocation(line: 34, column: 68, scope: !7)
+!28 = !DILocation(line: 35, column: 31, scope: !7)
+!29 = !DILocation(line: 35, column: 36, scope: !7)
+!30 = !DILocation(line: 37, column: 18, scope: !7)
+!31 = !DILocation(line: 39, column: 18, scope: !7)
+!32 = !DILocation(line: 41, column: 18, scope: !7)
+!33 = !DILocation(line: 43, column: 19, scope: !7)
+!34 = !DILocation(line: 233, column: 15, scope: !35, inlinedAt: !38)
+!35 = distinct !DILexicalBlockFile(scope: !37, file: !36, discriminator: 0)
+!36 = !DIFile(filename: "standard.py", directory: "/usr/local/lib/python3.10/dist-packages/triton/language")
+!37 = distinct !DILexicalBlockFile(scope: !7, file: !36, discriminator: 0)
+!38 = !DILocation(line: 243, column: 36, scope: !35, inlinedAt: !39)
+!39 = !DILocation(line: 48, column: 59, scope: !35)
+!40 = !DILocation(line: 243, column: 36, scope: !37, inlinedAt: !41)
+!41 = !DILocation(line: 48, column: 59, scope: !37)
+!42 = !DILocation(line: 8, column: 15, scope: !43, inlinedAt: !45)
+!43 = distinct !DILexicalBlockFile(scope: !7, file: !44, discriminator: 0)
+!44 = !DIFile(filename: "triton_helpers.py", directory: "/usr/local/lib/python3.10/dist-packages/torch/_inductor")
+!45 = !DILocation(line: 48, column: 45, scope: !43)
+!46 = !DILocation(line: 51, column: 20, scope: !7)
+!47 = !DILocation(line: 52, column: 20, scope: !7)
+!48 = !DILocation(line: 53, column: 20, scope: !7)
+!49 = !DILocation(line: 243, column: 36, scope: !37, inlinedAt: !50)
+!50 = !DILocation(line: 56, column: 59, scope: !37)
+!51 = !DILocation(line: 233, column: 15, scope: !35, inlinedAt: !52)
+!52 = !DILocation(line: 243, column: 36, scope: !35, inlinedAt: !53)
+!53 = !DILocation(line: 56, column: 59, scope: !35)
+!54 = !DILocation(line: 8, column: 15, scope: !43, inlinedAt: !55)
+!55 = !DILocation(line: 56, column: 45, scope: !43)
+!56 = !DILocation(line: 59, column: 20, scope: !7)
+!57 = !DILocation(line: 61, column: 20, scope: !7)
+!58 = !DILocation(line: 62, column: 26, scope: !7)
+!59 = !DILocation(line: 63, column: 20, scope: !7)
+!60 = !DILocation(line: 64, column: 20, scope: !7)
+!61 = !DILocation(line: 66, column: 25, scope: !7)
+!62 = !DILocation(line: 66, column: 48, scope: !7)
+!63 = !DILocation(line: 67, column: 25, scope: !7)
+!64 = !DILocation(line: 67, column: 48, scope: !7)
+!65 = !DILocation(line: 67, column: 4, scope: !7)

.triton/dump/0bb244fe116b8bad2e3be6ce32964a26/triton_.ptx

@@ -0,0 +1,807 @@
+//
+// Generated by LLVM NVPTX Back-End
+//
+
+.version 8.2
+.target sm_89
+.address_size 64
+
+	// .globl	triton__0d1d2d3d4d5d6d7d8de9de
+.extern .shared .align 1 .b8 global_smem[];
+.global .align 1 .b8 _$_str[11] = {95, 95, 67, 85, 68, 65, 95, 70, 84, 90, 0};
+
+.visible .entry triton__0d1d2d3d4d5d6d7d8de9de(
+	.param .u64 triton__0d1d2d3d4d5d6d7d8de9de_param_0,
+	.param .u64 triton__0d1d2d3d4d5d6d7d8de9de_param_1,
+	.param .u64 triton__0d1d2d3d4d5d6d7d8de9de_param_2,
+	.param .u64 triton__0d1d2d3d4d5d6d7d8de9de_param_3,
+	.param .u64 triton__0d1d2d3d4d5d6d7d8de9de_param_4,
+	.param .u64 triton__0d1d2d3d4d5d6d7d8de9de_param_5,
+	.param .u64 triton__0d1d2d3d4d5d6d7d8de9de_param_6,
+	.param .u64 triton__0d1d2d3d4d5d6d7d8de9de_param_7,
+	.param .u32 triton__0d1d2d3d4d5d6d7d8de9de_param_8,
+	.param .u32 triton__0d1d2d3d4d5d6d7d8de9de_param_9
+)
+.maxntid 64, 1, 1
+{
+	.reg .pred 	%p<33>;
+	.reg .b16 	%rs<21>;
+	.reg .b32 	%r<112>;
+	.reg .f32 	%f<94>;
+	.reg .b64 	%rd<20>;
+	.loc	1 18 0
+$L__func_begin0:
+	.loc	1 18 0
+
+	ld.param.u64 	%rd9, [triton__0d1d2d3d4d5d6d7d8de9de_param_0];
+	ld.param.u64 	%rd10, [triton__0d1d2d3d4d5d6d7d8de9de_param_1];
+$L__tmp0:
+	.loc	1 26 26
+	mov.u32 	%r78, %tid.x;
+	and.b32  	%r79, %r78, 31;
+	ld.param.u64 	%rd11, [triton__0d1d2d3d4d5d6d7d8de9de_param_2];
+	ld.param.u64 	%rd12, [triton__0d1d2d3d4d5d6d7d8de9de_param_3];
+	ld.param.u64 	%rd13, [triton__0d1d2d3d4d5d6d7d8de9de_param_4];
+	shl.b32 	%r80, %r78, 2;
+	ld.param.u64 	%rd14, [triton__0d1d2d3d4d5d6d7d8de9de_param_5];
+	and.b32  	%r81, %r80, 252;
+	ld.param.u64 	%rd15, [triton__0d1d2d3d4d5d6d7d8de9de_param_6];
+	ld.param.u64 	%rd16, [triton__0d1d2d3d4d5d6d7d8de9de_param_7];
+	.loc	1 23 28
+	mov.u32 %r1, %ctaid.x;
+	.loc	1 30 40
+	shl.b32 	%r82, %r1, 8;
+	.loc	1 30 36
+	or.b32  	%r83, %r82, %r81;
+	.loc	1 30 30
+	mul.wide.s32 	%rd17, %r83, 4;
+	add.s64 	%rd1, %rd9, %rd17;
+	mov.b32 	%r6, 0;
+	mov.pred 	%p1, -1;
+	.loc	1 30 46
+	mov.u32 %r2, 0x0;
+	mov.u32 %r3, 0x0;
+	mov.u32 %r4, 0x0;
+	mov.u32 %r5, 0x0;
+	@%p1 ld.global.v4.b32 { %r2, %r3, %r4, %r5 }, [ %rd1 + 0 ];
+	@!%p1 mov.u32 %r2, %r6;
+	@!%p1 mov.u32 %r3, %r6;
+	@!%p1 mov.u32 %r4, %r6;
+	@!%p1 mov.u32 %r5, %r6;
+	mov.b32 	%f1, %r2;
+	mov.b32 	%f2, %r3;
+	mov.b32 	%f3, %r4;
+	mov.b32 	%f4, %r5;
+	.loc	1 31 30
+	mul.wide.s32 	%rd18, %r83, 2;
+	add.s64 	%rd2, %rd10, %rd18;
+	.loc	1 31 46
+	mov.u32 %r10, 0x0;
+	mov.u32 %r11, 0x0;
+	@%p1 ld.global.v2.b32 { %r10, %r11 }, [ %rd2 + 0 ];
+	@!%p1 mov.u32 %r10, %r6;
+	@!%p1 mov.u32 %r11, %r6;
+	cvt.u16.u32 	%rs1, %r10;
+	{ .reg .b16 tmp; mov.b32 {tmp, %rs2}, %r10; }
+	cvt.u16.u32 	%rs3, %r11;
+	{ .reg .b16 tmp; mov.b32 {tmp, %rs4}, %r11; }
+	.loc	1 31 67
+	cvt.f32.bf16 %r14, %rs1;
+	mov.b32 	%f5, %r14;
+	cvt.f32.bf16 %r15, %rs2;
+	mov.b32 	%f6, %r15;
+	cvt.f32.bf16 %r16, %rs3;
+	mov.b32 	%f7, %r16;
+	cvt.f32.bf16 %r17, %rs4;
+	mov.b32 	%f8, %r17;
+	.loc	1 32 30
+	add.s64 	%rd3, %rd11, %rd18;
+	.loc	1 32 46
+	mov.u32 %r18, 0x0;
+	mov.u32 %r19, 0x0;
+	@%p1 ld.global.v2.b32 { %r18, %r19 }, [ %rd3 + 0 ];
+	@!%p1 mov.u32 %r18, %r6;
+	@!%p1 mov.u32 %r19, %r6;
+	cvt.u16.u32 	%rs5, %r18;
+	{ .reg .b16 tmp; mov.b32 {tmp, %rs6}, %r18; }
+	cvt.u16.u32 	%rs7, %r19;
+	{ .reg .b16 tmp; mov.b32 {tmp, %rs8}, %r19; }
+	.loc	1 32 67
+	cvt.f32.bf16 %r22, %rs5;
+	mov.b32 	%f9, %r22;
+	cvt.f32.bf16 %r23, %rs6;
+	mov.b32 	%f10, %r23;
+	cvt.f32.bf16 %r24, %rs7;
+	mov.b32 	%f11, %r24;
+	cvt.f32.bf16 %r25, %rs8;
+	mov.b32 	%f12, %r25;
+	.loc	1 33 30
+	add.s64 	%rd4, %rd12, %rd18;
+	.loc	1 33 46
+	mov.u32 %r26, 0x0;
+	mov.u32 %r27, 0x0;
+	@%p1 ld.global.v2.b32 { %r26, %r27 }, [ %rd4 + 0 ];
+	@!%p1 mov.u32 %r26, %r6;
+	@!%p1 mov.u32 %r27, %r6;
+	cvt.u16.u32 	%rs9, %r26;
+	{ .reg .b16 tmp; mov.b32 {tmp, %rs10}, %r26; }
+	cvt.u16.u32 	%rs11, %r27;
+	{ .reg .b16 tmp; mov.b32 {tmp, %rs12}, %r27; }
+	.loc	1 33 67
+	cvt.f32.bf16 %r30, %rs9;
+	mov.b32 	%f13, %r30;
+	cvt.f32.bf16 %r31, %rs10;
+	mov.b32 	%f14, %r31;
+	cvt.f32.bf16 %r32, %rs11;
+	mov.b32 	%f15, %r32;
+	cvt.f32.bf16 %r33, %rs12;
+	mov.b32 	%f16, %r33;
+	.loc	1 34 31
+	add.s64 	%rd5, %rd13, %rd18;
+	.loc	1 34 47
+	mov.u32 %r34, 0x0;
+	mov.u32 %r35, 0x0;
+	@%p1 ld.global.v2.b32 { %r34, %r35 }, [ %rd5 + 0 ];
+	@!%p1 mov.u32 %r34, %r6;
+	@!%p1 mov.u32 %r35, %r6;
+	cvt.u16.u32 	%rs13, %r34;
+	{ .reg .b16 tmp; mov.b32 {tmp, %rs14}, %r34; }
+	cvt.u16.u32 	%rs15, %r35;
+	{ .reg .b16 tmp; mov.b32 {tmp, %rs16}, %r35; }
+	.loc	1 34 68
+	cvt.f32.bf16 %r38, %rs13;
+	mov.b32 	%f17, %r38;
+	cvt.f32.bf16 %r39, %rs14;
+	mov.b32 	%f18, %r39;
+	cvt.f32.bf16 %r40, %rs15;
+	mov.b32 	%f19, %r40;
+	cvt.f32.bf16 %r41, %rs16;
+	mov.b32 	%f20, %r41;
+	.loc	1 35 31
+	mul.wide.u32 	%rd19, %r81, 4;
+	add.s64 	%rd6, %rd14, %rd19;
+	.loc	1 35 36
+	mov.u32 %r42, 0x0;
+	mov.u32 %r43, 0x0;
+	mov.u32 %r44, 0x0;
+	mov.u32 %r45, 0x0;
+	@%p1 ld.global.L1::evict_last.v4.b32 { %r42, %r43, %r44, %r45 }, [ %rd6 + 0 ];
+	@!%p1 mov.u32 %r42, %r6;
+	@!%p1 mov.u32 %r43, %r6;
+	@!%p1 mov.u32 %r44, %r6;
+	@!%p1 mov.u32 %r45, %r6;
+	.loc	1 37 18
+	add.f32 	%f21, %f5, %f1;
+	add.f32 	%f22, %f6, %f2;
+	add.f32 	%f23, %f7, %f3;
+	.loc	1 39 18
+	add.f32 	%f24, %f21, %f9;
+	add.f32 	%f25, %f22, %f10;
+	add.f32 	%f26, %f23, %f11;
+	.loc	1 41 18
+	add.f32 	%f27, %f25, %f14;
+	add.f32 	%f28, %f26, %f15;
+	.loc	1 43 19
+	add.f32 	%f29, %f27, %f18;
+	add.f32 	%f30, %f28, %f19;
+	.loc	1 41 18
+	add.f32 	%f31, %f24, %f13;
+	add.f32 	%f32, %f8, %f4;
+	.loc	1 43 19
+	add.f32 	%f33, %f32, %f12;
+	add.f32 	%f34, %f31, %f17;
+$L__tmp1:
+	.loc	2 233 15
+	add.f32 	%f35, %f34, %f29;
+	add.f32 	%f36, %f33, %f16;
+	add.f32 	%f37, %f35, %f30;
+	add.f32 	%f38, %f36, %f20;
+	mov.b32 	%r71, %f38;
+	add.f32 	%f39, %f37, %f38;
+$L__tmp2:
+	.loc	2 243 36
+	mov.b32 	%r84, %f39;
+	shfl.sync.bfly.b32	%r85, %r84, 16, 31, -1;
+	mov.b32 	%f40, %r85;
+$L__tmp3:
+	.loc	2 233 15
+	add.f32 	%f41, %f39, %f40;
+$L__tmp4:
+	.loc	2 243 36
+	mov.b32 	%r86, %f41;
+	shfl.sync.bfly.b32	%r87, %r86, 8, 31, -1;
+	mov.b32 	%f42, %r87;
+$L__tmp5:
+	.loc	2 233 15
+	add.f32 	%f43, %f41, %f42;
+$L__tmp6:
+	.loc	2 243 36
+	mov.b32 	%r88, %f43;
+	shfl.sync.bfly.b32	%r89, %r88, 4, 31, -1;
+	mov.b32 	%f44, %r89;
+$L__tmp7:
+	.loc	2 233 15
+	add.f32 	%f45, %f43, %f44;
+$L__tmp8:
+	.loc	2 243 36
+	mov.b32 	%r90, %f45;
+	shfl.sync.bfly.b32	%r91, %r90, 2, 31, -1;
+	mov.b32 	%f46, %r91;
+$L__tmp9:
+	.loc	2 233 15
+	add.f32 	%f47, %f45, %f46;
+$L__tmp10:
+	.loc	2 243 36
+	mov.b32 	%r92, %f47;
+	shfl.sync.bfly.b32	%r93, %r92, 1, 31, -1;
+	mov.b32 	%f48, %r93;
+$L__tmp11:
+	.loc	2 233 15
+	add.f32 	%f49, %f47, %f48;
+$L__tmp12:
+	.loc	2 243 36
+	setp.eq.s32 	%p23, %r79, 0;
+	shr.u32 	%r94, %r78, 3;
+	and.b32  	%r95, %r94, 4;
+	mov.u32 	%r96, global_smem;
+	add.s32 	%r50, %r96, %r95;
+	mov.b32 	%r51, %f49;
+	@%p23 st.shared.b32 [ %r50 + 0 ], %r51;
+	bar.sync 	0;
+	setp.lt.s32 	%p24, %r78, 2;
+	add.s32 	%r53, %r96, %r80;
+	@%p24 ld.shared.b32 %r52, [ %r53 + 0 ];
+	mov.b32 	%f50, %r52;
+	shfl.sync.bfly.b32	%r97, %r52, 1, 31, -1;
+	mov.b32 	%f51, %r97;
+$L__tmp13:
+	.loc	2 233 15
+	add.f32 	%f52, %f50, %f51;
+$L__tmp14:
+	.loc	2 243 36
+	and.b32  	%r98, %r78, 1;
+	setp.eq.b32 	%p31, %r98, 1;
+	not.pred 	%p32, %p31;
+	and.pred  	%p25, %p24, %p32;
+	mov.b32 	%r55, %f52;
+	@%p25 st.shared.b32 [ %r53 + 0 ], %r55;
+	bar.sync 	0;
+	ld.shared.f32 	%f53, [global_smem];
+$L__tmp15:
+	.loc	3 8 15
+	add.f32 	%f54, %f53, 0f00000000;
+$L__tmp16:
+	.loc	1 51 20
+	mov.b32 	%r57, %f54;
+	mov.b32 	%r58, 1132462080;
+	div.full.f32 %r56, %r57, %r58;
+	mov.b32 	%f55, %r56;
+	.loc	1 52 20
+	sub.f32 	%f56, %f34, %f55;
+	sub.f32 	%f57, %f29, %f55;
+	sub.f32 	%f58, %f30, %f55;
+	sub.f32 	%f59, %f38, %f55;
+	.loc	1 53 20
+	mul.f32 	%f60, %f57, %f57;
+$L__tmp17:
+	.loc	2 243 36
+	bar.sync 	0;
+$L__tmp18:
+	.loc	2 233 15
+	fma.rn.f32 	%f61, %f56, %f56, %f60;
+	fma.rn.f32 	%f62, %f58, %f58, %f61;
+	fma.rn.f32 	%f63, %f59, %f59, %f62;
+$L__tmp19:
+	.loc	2 243 36
+	mov.b32 	%r99, %f63;
+	shfl.sync.bfly.b32	%r100, %r99, 16, 31, -1;
+	mov.b32 	%f64, %r100;
+$L__tmp20:
+	.loc	2 233 15
+	add.f32 	%f65, %f63, %f64;
+$L__tmp21:
+	.loc	2 243 36
+	mov.b32 	%r101, %f65;
+	shfl.sync.bfly.b32	%r102, %r101, 8, 31, -1;
+	mov.b32 	%f66, %r102;
+$L__tmp22:
+	.loc	2 233 15
+	add.f32 	%f67, %f65, %f66;
+$L__tmp23:
+	.loc	2 243 36
+	mov.b32 	%r103, %f67;
+	shfl.sync.bfly.b32	%r104, %r103, 4, 31, -1;
+	mov.b32 	%f68, %r104;
+$L__tmp24:
+	.loc	2 233 15
+	add.f32 	%f69, %f67, %f68;
+$L__tmp25:
+	.loc	2 243 36
+	mov.b32 	%r105, %f69;
+	shfl.sync.bfly.b32	%r106, %r105, 2, 31, -1;
+	mov.b32 	%f70, %r106;
+$L__tmp26:
+	.loc	2 233 15
+	add.f32 	%f71, %f69, %f70;
+$L__tmp27:
+	.loc	2 243 36
+	mov.b32 	%r107, %f71;
+	shfl.sync.bfly.b32	%r108, %r107, 1, 31, -1;
+	mov.b32 	%f72, %r108;
+$L__tmp28:
+	.loc	2 233 15
+	add.f32 	%f73, %f71, %f72;
+$L__tmp29:
+	.loc	2 243 36
+	mov.b32 	%r60, %f73;
+	@%p23 st.shared.b32 [ %r50 + 0 ], %r60;
+	bar.sync 	0;
+	@%p24 ld.shared.b32 %r61, [ %r53 + 0 ];
+	mov.b32 	%f74, %r61;
+	shfl.sync.bfly.b32	%r109, %r61, 1, 31, -1;
+	mov.b32 	%f75, %r109;
+$L__tmp30:
+	.loc	2 233 15
+	add.f32 	%f76, %f74, %f75;
+$L__tmp31:
+	.loc	2 243 36
+	mov.b32 	%r64, %f76;
+	@%p25 st.shared.b32 [ %r53 + 0 ], %r64;
+	bar.sync 	0;
+	ld.shared.f32 	%f77, [global_smem];
+$L__tmp32:
+	.loc	3 8 15
+	add.f32 	%f78, %f77, 0f00000000;
+$L__tmp33:
+	.loc	1 59 20
+	mov.b32 	%r66, %f78;
+	div.full.f32 %r65, %r66, %r58;
+	mov.b32 	%f79, %r65;
+	.loc	1 61 20
+	add.f32 	%f80, %f79, 0f3727C5AC;
+	.loc	1 62 26
+	rsqrt.approx.ftz.f32 	%f81, %f80;
+	.loc	1 35 36
+	mov.b32 	%f82, %r45;
+	mov.b32 	%f83, %r44;
+	mov.b32 	%f84, %r43;
+	mov.b32 	%f85, %r42;
+	.loc	1 63 20
+	mul.f32 	%f86, %f56, %f81;
+	mul.f32 	%f87, %f57, %f81;
+	mul.f32 	%f88, %f58, %f81;
+	mul.f32 	%f89, %f59, %f81;
+	.loc	1 64 20
+	mul.f32 	%f90, %f86, %f85;
+	mul.f32 	%f91, %f87, %f84;
+	mul.f32 	%f92, %f88, %f83;
+	mul.f32 	%f93, %f89, %f82;
+	.loc	1 66 25
+	add.s64 	%rd7, %rd15, %rd17;
+	.loc	1 66 48
+	mov.b32 	%r68, %f34;
+	mov.b32 	%r69, %f29;
+	mov.b32 	%r70, %f30;
+	@%p1 st.global.v4.b32 [ %rd7 + 0 ], { %r68, %r69, %r70, %r71 };
+	.loc	1 67 25
+	add.s64 	%rd8, %rd16, %rd18;
+	.loc	1 67 48
+	mov.b32 	%r72, %f90;
+	cvt.rn.bf16.f32 %rs17, %r72;
+	mov.b32 	%r73, %f91;
+	cvt.rn.bf16.f32 %rs18, %r73;
+	mov.b32 	%r74, %f92;
+	cvt.rn.bf16.f32 %rs19, %r74;
+	mov.b32 	%r75, %f93;
+	cvt.rn.bf16.f32 %rs20, %r75;
+	mov.b32 	%r110, {%rs17, %rs18};
+	mov.b32 	%r111, {%rs19, %rs20};
+	@%p1 st.global.v2.b32 [ %rd8 + 0 ], { %r110, %r111 };
+	.loc	1 67 4
+	ret;
+$L__tmp34:
+$L__func_end0:
+
+}
+	// .globl	__nv_rsqrtf
+.visible .func  (.param .b32 func_retval0) __nv_rsqrtf(
+	.param .b32 __nv_rsqrtf_param_0
+)
+{
+	.reg .f32 	%f<3>;
+$L__func_begin1:
+
+	ld.param.f32 	%f1, [__nv_rsqrtf_param_0];
+	rsqrt.approx.ftz.f32 	%f2, %f1;
+	st.param.f32 	[func_retval0+0], %f2;
+	ret;
+$L__func_end1:
+
+}
+	.file	1 "/tmp/torchinductor_root/yb/cybxnh26qvsbmxmvdr54vaav2ezk2qxu7562fhhsn4lvyvqgoglw.py"
+	.file	2 "/usr/local/lib/python3.10/dist-packages/triton/language/standard.py"
+	.file	3 "/usr/local/lib/python3.10/dist-packages/torch/_inductor/triton_helpers.py"
+	.section	.debug_abbrev
+	{
+.b8 1
+.b8 17
+.b8 1
+.b8 37
+.b8 8
+.b8 19
+.b8 5
+.b8 3
+.b8 8
+.b8 16
+.b8 6
+.b8 27
+.b8 8
+.b8 180
+.b8 66
+.b8 12
+.b8 17
+.b8 1
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+.b8 1
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+.b8 1
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+.b8 1
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+.b8 10
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+.b8 0
+.b8 0
+.b8 4
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+.b8 1
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+.b8 0
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+.b8 5
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+.b8 0
+.b8 49
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+.b8 1
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+.b8 1
+.b8 88
+.b8 11
+.b8 89
+.b8 11
+.b8 87
+.b8 11
+.b8 0
+.b8 0
+.b8 0
+	}
+	.section	.debug_info
+	{
+.b32 407
+.b8 2
+.b8 0
+.b32 .debug_abbrev
+.b8 8
+.b8 1
+.b8 116
+.b8 114
+.b8 105
+.b8 116
+.b8 111
+.b8 110
+.b8 0
+.b8 2
+.b8 0
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+.b8 107
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+.b8 113
+.b8 103
+.b8 111
+.b8 103
+.b8 108
+.b8 119
+.b8 46
+.b8 112
+.b8 121
+.b8 0
+.b32 .debug_line
+.b8 47
+.b8 116
+.b8 109
+.b8 112
+.b8 47
+.b8 116
+.b8 111
+.b8 114
+.b8 99
+.b8 104
+.b8 105
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+.b8 99
+.b8 116
+.b8 111
+.b8 114
+.b8 95
+.b8 114
+.b8 111
+.b8 111
+.b8 116
+.b8 47
+.b8 121
+.b8 98
+.b8 0
+.b8 1
+.b64 $L__func_begin0
+.b64 $L__func_end0
+.b8 2
+.b8 116
+.b8 114
+.b8 105
+.b8 116
+.b8 111
+.b8 110
+.b8 95
+.b8 95
+.b8 48
+.b8 100
+.b8 49
+.b8 100
+.b8 50
+.b8 100
+.b8 51
+.b8 100
+.b8 52
+.b8 100
+.b8 53
+.b8 100
+.b8 54
+.b8 100
+.b8 55
+.b8 100
+.b8 56
+.b8 100
+.b8 101
+.b8 57
+.b8 100
+.b8 101
+.b8 0
+.b8 116
+.b8 114
+.b8 105
+.b8 116
+.b8 111
+.b8 110
+.b8 95
+.b8 95
+.b8 48
+.b8 100
+.b8 49
+.b8 100
+.b8 50
+.b8 100
+.b8 51
+.b8 100
+.b8 52
+.b8 100
+.b8 53
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+.b8 54
+.b8 100
+.b8 55
+.b8 100
+.b8 56
+.b8 100
+.b8 101
+.b8 57
+.b8 100
+.b8 101
+.b8 0
+.b8 1
+.b8 18
+.b8 1
+.b8 1
+.b8 3
+.b64 $L__func_begin0
+.b64 $L__func_end0
+.b8 1
+.b8 156
+.b32 125
+.b8 4
+.b32 125
+.b64 $L__tmp1
+.b64 $L__tmp14
+.b8 2
+.b8 48
+.b8 59
+.b8 5
+.b32 125
+.b64 $L__tmp1
+.b64 $L__tmp14
+.b8 2
+.b8 243
+.b8 36
+.b8 0
+.b8 5
+.b32 125
+.b64 $L__tmp2
+.b64 $L__tmp15
+.b8 2
+.b8 48
+.b8 59
+.b8 5
+.b32 125
+.b64 $L__tmp15
+.b64 $L__tmp16
+.b8 3
+.b8 48
+.b8 45
+.b8 5
+.b32 125
+.b64 $L__tmp17
+.b64 $L__tmp32
+.b8 2
+.b8 56
+.b8 59
+.b8 4
+.b32 125
+.b64 $L__tmp18
+.b64 $L__tmp31
+.b8 2
+.b8 56
+.b8 59
+.b8 5
+.b32 125
+.b64 $L__tmp18
+.b64 $L__tmp31
+.b8 2
+.b8 243
+.b8 36
+.b8 0
+.b8 5
+.b32 125
+.b64 $L__tmp32
+.b64 $L__tmp33
+.b8 3
+.b8 56
+.b8 45
+.b8 0
+.b8 0
+	}
+	.section	.debug_pubnames
+	{
+.b32 $L__pubNames_end0-$L__pubNames_start0
+$L__pubNames_start0:
+.b8 2
+.b8 0
+.b32 .debug_info
+.b32 411
+.b32 125
+.b8 116
+.b8 114
+.b8 105
+.b8 116
+.b8 111
+.b8 110
+.b8 95
+.b8 95
+.b8 48
+.b8 100
+.b8 49
+.b8 100
+.b8 50
+.b8 100
+.b8 51
+.b8 100
+.b8 52
+.b8 100
+.b8 53
+.b8 100
+.b8 54
+.b8 100
+.b8 55
+.b8 100
+.b8 56
+.b8 100
+.b8 101
+.b8 57
+.b8 100
+.b8 101
+.b8 0
+.b32 0
+$L__pubNames_end0:
+	}
+	.section	.debug_pubtypes
+	{
+.b32 $L__pubTypes_end0-$L__pubTypes_start0
+$L__pubTypes_start0:
+.b8 2
+.b8 0
+.b32 .debug_info
+.b32 411
+.b32 0
+$L__pubTypes_end0:
+	}
+	.section	.debug_loc	{	}

.triton/dump/0bb244fe116b8bad2e3be6ce32964a26/triton_.ttgir

@@ -0,0 +1,76 @@
+#blocked = #triton_gpu.blocked<{sizePerThread = [4], threadsPerWarp = [32], warpsPerCTA = [2], order = [0], CTAsPerCGA = [1], CTASplitNum = [1], CTAOrder = [0]}>
+module attributes {"triton_gpu.compute-capability" = 89 : i32, "triton_gpu.num-ctas" = 1 : i32, "triton_gpu.num-warps" = 2 : i32, "triton_gpu.threads-per-warp" = 32 : i32} {
+  tt.func public @triton__0d1d2d3d4d5d6d7d8de9de(%arg0: !tt.ptr<f32, 1> {tt.divisibility = 16 : i32}, %arg1: !tt.ptr<bf16, 1> {tt.divisibility = 16 : i32}, %arg2: !tt.ptr<bf16, 1> {tt.divisibility = 16 : i32}, %arg3: !tt.ptr<bf16, 1> {tt.divisibility = 16 : i32}, %arg4: !tt.ptr<bf16, 1> {tt.divisibility = 16 : i32}, %arg5: !tt.ptr<f32, 1> {tt.divisibility = 16 : i32}, %arg6: !tt.ptr<f32, 1> {tt.divisibility = 16 : i32}, %arg7: !tt.ptr<bf16, 1> {tt.divisibility = 16 : i32}, %arg8: i32 {tt.divisibility = 16 : i32, tt.max_divisibility = 16 : i32}, %arg9: i32 {tt.divisibility = 16 : i32, tt.max_divisibility = 16 : i32}) attributes {noinline = false} {
+    %cst = arith.constant dense<256> : tensor<256xi32, #blocked>
+    %cst_0 = arith.constant 9.99999974E-6 : f32
+    %cst_1 = arith.constant 2.560000e+02 : f32
+    %cst_2 = arith.constant 0.000000e+00 : f32
+    %c256_i32 = arith.constant 256 : i32
+    %cst_3 = arith.constant dense<0.000000e+00> : tensor<256xf32, #blocked>
+    %cst_4 = arith.constant dense<0.000000e+00> : tensor<256xbf16, #blocked>
+    %0 = tt.get_program_id x : i32
+    %1 = tt.make_range {end = 256 : i32, start = 0 : i32} : tensor<256xi32, #blocked>
+    %2 = arith.cmpi slt, %1, %cst : tensor<256xi32, #blocked>
+    %3 = arith.muli %0, %c256_i32 : i32
+    %4 = tt.splat %3 : (i32) -> tensor<256xi32, #blocked>
+    %5 = arith.addi %1, %4 : tensor<256xi32, #blocked>
+    %6 = tt.splat %arg0 : (!tt.ptr<f32, 1>) -> tensor<256x!tt.ptr<f32, 1>, #blocked>
+    %7 = tt.addptr %6, %5 : tensor<256x!tt.ptr<f32, 1>, #blocked>, tensor<256xi32, #blocked>
+    %8 = tt.load %7, %2, %cst_3 {cache = 1 : i32, evict = 1 : i32, isVolatile = false} : tensor<256xf32, #blocked>
+    %9 = tt.splat %arg1 : (!tt.ptr<bf16, 1>) -> tensor<256x!tt.ptr<bf16, 1>, #blocked>
+    %10 = tt.addptr %9, %5 : tensor<256x!tt.ptr<bf16, 1>, #blocked>, tensor<256xi32, #blocked>
+    %11 = tt.load %10, %2, %cst_4 {cache = 1 : i32, evict = 1 : i32, isVolatile = false} : tensor<256xbf16, #blocked>
+    %12 = arith.extf %11 : tensor<256xbf16, #blocked> to tensor<256xf32, #blocked>
+    %13 = tt.splat %arg2 : (!tt.ptr<bf16, 1>) -> tensor<256x!tt.ptr<bf16, 1>, #blocked>
+    %14 = tt.addptr %13, %5 : tensor<256x!tt.ptr<bf16, 1>, #blocked>, tensor<256xi32, #blocked>
+    %15 = tt.load %14, %2, %cst_4 {cache = 1 : i32, evict = 1 : i32, isVolatile = false} : tensor<256xbf16, #blocked>
+    %16 = arith.extf %15 : tensor<256xbf16, #blocked> to tensor<256xf32, #blocked>
+    %17 = tt.splat %arg3 : (!tt.ptr<bf16, 1>) -> tensor<256x!tt.ptr<bf16, 1>, #blocked>
+    %18 = tt.addptr %17, %5 : tensor<256x!tt.ptr<bf16, 1>, #blocked>, tensor<256xi32, #blocked>
+    %19 = tt.load %18, %2, %cst_4 {cache = 1 : i32, evict = 1 : i32, isVolatile = false} : tensor<256xbf16, #blocked>
+    %20 = arith.extf %19 : tensor<256xbf16, #blocked> to tensor<256xf32, #blocked>
+    %21 = tt.splat %arg4 : (!tt.ptr<bf16, 1>) -> tensor<256x!tt.ptr<bf16, 1>, #blocked>
+    %22 = tt.addptr %21, %5 : tensor<256x!tt.ptr<bf16, 1>, #blocked>, tensor<256xi32, #blocked>
+    %23 = tt.load %22, %2, %cst_4 {cache = 1 : i32, evict = 1 : i32, isVolatile = false} : tensor<256xbf16, #blocked>
+    %24 = arith.extf %23 : tensor<256xbf16, #blocked> to tensor<256xf32, #blocked>
+    %25 = tt.splat %arg5 : (!tt.ptr<f32, 1>) -> tensor<256x!tt.ptr<f32, 1>, #blocked>
+    %26 = tt.addptr %25, %1 : tensor<256x!tt.ptr<f32, 1>, #blocked>, tensor<256xi32, #blocked>
+    %27 = tt.load %26, %2, %cst_3 {cache = 1 : i32, evict = 3 : i32, isVolatile = false} : tensor<256xf32, #blocked>
+    %28 = arith.addf %8, %12 : tensor<256xf32, #blocked>
+    %29 = arith.addf %28, %16 : tensor<256xf32, #blocked>
+    %30 = arith.addf %29, %20 : tensor<256xf32, #blocked>
+    %31 = arith.addf %30, %24 : tensor<256xf32, #blocked>
+    %32 = arith.select %2, %31, %cst_3 : tensor<256xi1, #blocked>, tensor<256xf32, #blocked>
+    %33 = "tt.reduce"(%32) <{axis = 0 : i32}> ({
+    ^bb0(%arg10: f32, %arg11: f32):
+      %53 = arith.addf %arg10, %arg11 : f32
+      tt.reduce.return %53 : f32
+    }) : (tensor<256xf32, #blocked>) -> f32
+    %34 = arith.addf %33, %cst_2 : f32
+    %35 = arith.divf %34, %cst_1 : f32
+    %36 = tt.splat %35 : (f32) -> tensor<256xf32, #blocked>
+    %37 = arith.subf %31, %36 : tensor<256xf32, #blocked>
+    %38 = arith.mulf %37, %37 : tensor<256xf32, #blocked>
+    %39 = arith.select %2, %38, %cst_3 : tensor<256xi1, #blocked>, tensor<256xf32, #blocked>
+    %40 = "tt.reduce"(%39) <{axis = 0 : i32}> ({
+    ^bb0(%arg10: f32, %arg11: f32):
+      %53 = arith.addf %arg10, %arg11 : f32
+      tt.reduce.return %53 : f32
+    }) : (tensor<256xf32, #blocked>) -> f32
+    %41 = arith.addf %40, %cst_2 : f32
+    %42 = arith.divf %41, %cst_1 : f32
+    %43 = arith.addf %42, %cst_0 : f32
+    %44 = tt.extern_elementwise %43 {libname = "libdevice", libpath = "/usr/local/lib/python3.10/dist-packages/triton/language/../third_party/cuda/lib/libdevice.10.bc", pure = true, symbol = "__nv_rsqrtf"} : (f32) -> f32
+    %45 = tt.splat %44 : (f32) -> tensor<256xf32, #blocked>
+    %46 = arith.mulf %37, %45 : tensor<256xf32, #blocked>
+    %47 = arith.mulf %46, %27 : tensor<256xf32, #blocked>
+    %48 = tt.splat %arg6 : (!tt.ptr<f32, 1>) -> tensor<256x!tt.ptr<f32, 1>, #blocked>
+    %49 = tt.addptr %48, %5 : tensor<256x!tt.ptr<f32, 1>, #blocked>, tensor<256xi32, #blocked>
+    tt.store %49, %31, %2 {cache = 1 : i32, evict = 1 : i32} : tensor<256xf32, #blocked>
+    %50 = tt.splat %arg7 : (!tt.ptr<bf16, 1>) -> tensor<256x!tt.ptr<bf16, 1>, #blocked>
+    %51 = tt.addptr %50, %5 : tensor<256x!tt.ptr<bf16, 1>, #blocked>, tensor<256xi32, #blocked>
+    %52 = arith.truncf %47 : tensor<256xf32, #blocked> to tensor<256xbf16, #blocked>
+    tt.store %51, %52, %2 {cache = 1 : i32, evict = 1 : i32} : tensor<256xbf16, #blocked>
+    tt.return
+  }
+}

.triton/dump/0bbf368bb6fbbd0528742f708246d167/triton_.ttir

@@ -0,0 +1,57 @@
+module {
+  tt.func public @triton__0d1d2d3d4de5de(%arg0: !tt.ptr<f32, 1> {tt.divisibility = 16 : i32}, %arg1: !tt.ptr<bf16, 1> {tt.divisibility = 16 : i32}, %arg2: !tt.ptr<f32, 1> {tt.divisibility = 16 : i32}, %arg3: !tt.ptr<bf16, 1> {tt.divisibility = 16 : i32}, %arg4: i32 {tt.divisibility = 16 : i32, tt.max_divisibility = 16 : i32}, %arg5: i32 {tt.divisibility = 16 : i32, tt.max_divisibility = 16 : i32}) attributes {noinline = false} {
+    %c256_i32 = arith.constant 256 : i32
+    %cst = arith.constant dense<0.000000e+00> : tensor<256xbf16>
+    %cst_0 = arith.constant 0.000000e+00 : f32
+    %cst_1 = arith.constant 2.560000e+02 : f32
+    %cst_2 = arith.constant 9.99999974E-6 : f32
+    %cst_3 = arith.constant dense<0.000000e+00> : tensor<256xf32>
+    %cst_4 = arith.constant dense<256> : tensor<256xi32>
+    %0 = tt.get_program_id x : i32
+    %1 = tt.make_range {end = 256 : i32, start = 0 : i32} : tensor<256xi32>
+    %2 = arith.cmpi slt, %1, %cst_4 : tensor<256xi32>
+    %3 = arith.muli %0, %c256_i32 : i32
+    %4 = tt.splat %3 : (i32) -> tensor<256xi32>
+    %5 = arith.addi %1, %4 : tensor<256xi32>
+    %6 = tt.splat %arg0 : (!tt.ptr<f32, 1>) -> tensor<256x!tt.ptr<f32, 1>>
+    %7 = tt.addptr %6, %5 : tensor<256x!tt.ptr<f32, 1>>, tensor<256xi32>
+    %8 = tt.load %7, %2, %cst_3 {cache = 1 : i32, evict = 1 : i32, isVolatile = false} : tensor<256xf32>
+    %9 = tt.splat %arg1 : (!tt.ptr<bf16, 1>) -> tensor<256x!tt.ptr<bf16, 1>>
+    %10 = tt.addptr %9, %5 : tensor<256x!tt.ptr<bf16, 1>>, tensor<256xi32>
+    %11 = tt.load %10, %2, %cst {cache = 1 : i32, evict = 1 : i32, isVolatile = false} : tensor<256xbf16>
+    %12 = arith.extf %11 : tensor<256xbf16> to tensor<256xf32>
+    %13 = tt.splat %arg2 : (!tt.ptr<f32, 1>) -> tensor<256x!tt.ptr<f32, 1>>
+    %14 = tt.addptr %13, %1 : tensor<256x!tt.ptr<f32, 1>>, tensor<256xi32>
+    %15 = tt.load %14, %2, %cst_3 {cache = 1 : i32, evict = 3 : i32, isVolatile = false} : tensor<256xf32>
+    %16 = arith.addf %8, %12 : tensor<256xf32>
+    %17 = arith.select %2, %16, %cst_3 : tensor<256xi1>, tensor<256xf32>
+    %18 = "tt.reduce"(%17) <{axis = 0 : i32}> ({
+    ^bb0(%arg6: f32, %arg7: f32):
+      %36 = arith.addf %arg6, %arg7 : f32
+      tt.reduce.return %36 : f32
+    }) : (tensor<256xf32>) -> f32
+    %19 = arith.addf %18, %cst_0 : f32
+    %20 = arith.divf %19, %cst_1 : f32
+    %21 = tt.splat %20 : (f32) -> tensor<256xf32>
+    %22 = arith.subf %16, %21 : tensor<256xf32>
+    %23 = arith.mulf %22, %22 : tensor<256xf32>
+    %24 = arith.select %2, %23, %cst_3 : tensor<256xi1>, tensor<256xf32>
+    %25 = "tt.reduce"(%24) <{axis = 0 : i32}> ({
+    ^bb0(%arg6: f32, %arg7: f32):
+      %36 = arith.addf %arg6, %arg7 : f32
+      tt.reduce.return %36 : f32
+    }) : (tensor<256xf32>) -> f32
+    %26 = arith.addf %25, %cst_0 : f32
+    %27 = arith.divf %26, %cst_1 : f32
+    %28 = arith.addf %27, %cst_2 : f32
+    %29 = tt.extern_elementwise %28 {libname = "libdevice", libpath = "/usr/local/lib/python3.10/dist-packages/triton/language/../third_party/cuda/lib/libdevice.10.bc", pure = true, symbol = "__nv_rsqrtf"} : (f32) -> f32
+    %30 = tt.splat %29 : (f32) -> tensor<256xf32>
+    %31 = arith.mulf %22, %30 : tensor<256xf32>
+    %32 = arith.mulf %31, %15 : tensor<256xf32>
+    %33 = tt.splat %arg3 : (!tt.ptr<bf16, 1>) -> tensor<256x!tt.ptr<bf16, 1>>
+    %34 = tt.addptr %33, %5 : tensor<256x!tt.ptr<bf16, 1>>, tensor<256xi32>
+    %35 = arith.truncf %32 : tensor<256xf32> to tensor<256xbf16>
+    tt.store %34, %35, %2 {cache = 1 : i32, evict = 1 : i32} : tensor<256xbf16>
+    tt.return
+  }
+}

.triton/dump/10ca9c2c168e8529fb752d28f80c40a5/triton_.ptx

@@ -0,0 +1,764 @@
+//
+// Generated by LLVM NVPTX Back-End
+//
+
+.version 8.2
+.target sm_89
+.address_size 64
+
+	// .globl	triton__0d1de
+.global .align 1 .b8 _$_str[11] = {95, 95, 67, 85, 68, 65, 95, 70, 84, 90, 0};
+
+.visible .entry triton__0d1de(
+	.param .u64 triton__0d1de_param_0,
+	.param .u32 triton__0d1de_param_1
+)
+.maxntid 128, 1, 1
+{
+	.reg .pred 	%p<27>;
+	.reg .b16 	%rs<17>;
+	.reg .b32 	%r<67>;
+	.reg .f32 	%f<431>;
+	.reg .b64 	%rd<6>;
+	.loc	1 18 0
+$L__func_begin0:
+	.loc	1 18 0
+
+	ld.param.u64 	%rd3, [triton__0d1de_param_0];
+$L__tmp0:
+	.loc	1 21 36
+	mov.u32 	%r14, %tid.x;
+	shl.b32 	%r15, %r14, 3;
+	and.b32  	%r16, %r15, 1016;
+	.loc	1 20 28
+	mov.u32 %r1, %ctaid.x;
+	.loc	1 20 33
+	shl.b32 	%r17, %r1, 10;
+	.loc	1 21 23
+	or.b32  	%r18, %r17, %r16;
+	.loc	1 24 34
+	mul.wide.s32 	%rd4, %r18, 2;
+	add.s64 	%rd5, %rd3, %rd4;
+	mov.pred 	%p1, -1;
+	.loc	1 24 39
+	mov.u32 %r2, 0x0;
+	mov.u32 %r3, 0x0;
+	mov.u32 %r4, 0x0;
+	mov.u32 %r5, 0x0;
+	@%p1 ld.global.v4.b32 { %r2, %r3, %r4, %r5 }, [ %rd5 + 0 ];
+	cvt.u16.u32 	%rs1, %r2;
+	{ .reg .b16 tmp; mov.b32 {tmp, %rs2}, %r2; }
+	cvt.u16.u32 	%rs3, %r3;
+	.loc	1 24 48
+	cvt.f32.bf16 %r6, %rs1;
+	mov.b32 	%f1, %r6;
+	cvt.f32.bf16 %r7, %rs2;
+	mov.b32 	%f2, %r7;
+	.loc	1 29 18
+	mul.f32 	%f9, %f1, 0f3F3504F3;
+	.loc	1 30 23
+	abs.ftz.f32 	%f17, %f9;
+	setp.ge.f32 	%p2, %f17, 0f3F8060FE;
+	mov.f32 	%f365, 0f3789CA3C;
+	mov.f32 	%f364, 0fB9F560B9;
+	mov.f32 	%f363, 0f3BAC840B;
+	mov.f32 	%f362, 0fBD0C8162;
+	mov.f32 	%f361, 0f3E1CF906;
+	mov.f32 	%f360, 0f3F6A937E;
+	mov.f32 	%f359, 0f3F20D842;
+	mov.f32 	%f366, %f17;
+	@%p2 bra 	$L__BB0_2;
+	.loc	1 0 23
+	mov.f32 	%f365, 0f38B1E96A;
+	mov.f32 	%f364, 0fBA574D20;
+	mov.f32 	%f363, 0f3BAAD5EA;
+	mov.f32 	%f362, 0fBCDC1BE7;
+	mov.f32 	%f361, 0f3DE718AF;
+	mov.f32 	%f360, 0fBEC093AC;
+	mov.f32 	%f359, 0f3E0375D3;
+	.loc	1 30 23
+	mul.f32 	%f366, %f9, %f9;
+$L__BB0_2:
+	.loc	1 0 0
+	cvt.f32.bf16 %r8, %rs3;
+	mul.f32 	%f10, %f2, 0f3F3504F3;
+	.loc	1 30 23
+	setp.ltu.f32 	%p3, %f17, 0f3F8060FE;
+	fma.rn.ftz.f32 	%f135, %f365, %f366, %f364;
+	fma.rn.ftz.f32 	%f136, %f135, %f366, %f363;
+	fma.rn.ftz.f32 	%f137, %f136, %f366, %f362;
+	fma.rn.ftz.f32 	%f138, %f137, %f366, %f361;
+	fma.rn.ftz.f32 	%f139, %f138, %f366, %f360;
+	fma.rn.ftz.f32 	%f140, %f139, %f366, %f359;
+	neg.f32 	%f141, %f366;
+	selp.f32 	%f142, %f141, %f9, %p2;
+	fma.rn.ftz.f32 	%f367, %f140, %f142, %f142;
+	mov.f32 	%f358, 0f3F800000;
+	@%p3 bra 	$L__BB0_4;
+	ex2.approx.ftz.f32 	%f143, %f367;
+	sub.f32 	%f145, %f358, %f143;
+	mov.b32 	%r19, %f145;
+	mov.b32 	%r20, %f9;
+	and.b32  	%r21, %r20, -2147483648;
+	or.b32  	%r22, %r21, %r19;
+	mov.b32 	%f367, %r22;
+$L__BB0_4:
+	.loc	1 0 0
+	{ .reg .b16 tmp; mov.b32 {tmp, %rs4}, %r3; }
+	mov.b32 	%f3, %r8;
+	.loc	1 30 23
+	abs.ftz.f32 	%f30, %f10;
+	setp.ge.f32 	%p5, %f30, 0f3F8060FE;
+	mov.f32 	%f374, 0f3789CA3C;
+	mov.f32 	%f373, 0fB9F560B9;
+	mov.f32 	%f372, 0f3BAC840B;
+	mov.f32 	%f371, 0fBD0C8162;
+	mov.f32 	%f370, 0f3E1CF906;
+	mov.f32 	%f369, 0f3F6A937E;
+	mov.f32 	%f368, 0f3F20D842;
+	mov.f32 	%f375, %f30;
+	@%p5 bra 	$L__BB0_6;
+	mul.f32 	%f375, %f10, %f10;
+	mov.f32 	%f374, 0f38B1E96A;
+	mov.f32 	%f373, 0fBA574D20;
+	mov.f32 	%f372, 0f3BAAD5EA;
+	mov.f32 	%f371, 0fBCDC1BE7;
+	mov.f32 	%f370, 0f3DE718AF;
+	mov.f32 	%f369, 0fBEC093AC;
+	mov.f32 	%f368, 0f3E0375D3;
+$L__BB0_6:
+	.loc	1 0 0
+	cvt.f32.bf16 %r9, %rs4;
+	mul.f32 	%f11, %f3, 0f3F3504F3;
+	.loc	1 30 23
+	setp.ltu.f32 	%p6, %f30, 0f3F8060FE;
+	fma.rn.ftz.f32 	%f160, %f374, %f375, %f373;
+	fma.rn.ftz.f32 	%f161, %f160, %f375, %f372;
+	fma.rn.ftz.f32 	%f162, %f161, %f375, %f371;
+	fma.rn.ftz.f32 	%f163, %f162, %f375, %f370;
+	fma.rn.ftz.f32 	%f164, %f163, %f375, %f369;
+	fma.rn.ftz.f32 	%f165, %f164, %f375, %f368;
+	neg.f32 	%f166, %f375;
+	selp.f32 	%f167, %f166, %f10, %p5;
+	fma.rn.ftz.f32 	%f376, %f165, %f167, %f167;
+	@%p6 bra 	$L__BB0_8;
+	ex2.approx.ftz.f32 	%f168, %f376;
+	sub.f32 	%f170, %f358, %f168;
+	mov.b32 	%r23, %f170;
+	mov.b32 	%r24, %f10;
+	and.b32  	%r25, %r24, -2147483648;
+	or.b32  	%r26, %r25, %r23;
+	mov.b32 	%f376, %r26;
+$L__BB0_8:
+	.loc	1 0 0
+	cvt.u16.u32 	%rs5, %r4;
+	mov.b32 	%f4, %r9;
+	.loc	1 30 23
+	abs.ftz.f32 	%f43, %f11;
+	setp.ge.f32 	%p8, %f43, 0f3F8060FE;
+	mov.f32 	%f383, 0f3789CA3C;
+	mov.f32 	%f382, 0fB9F560B9;
+	mov.f32 	%f381, 0f3BAC840B;
+	mov.f32 	%f380, 0fBD0C8162;
+	mov.f32 	%f379, 0f3E1CF906;
+	mov.f32 	%f378, 0f3F6A937E;
+	mov.f32 	%f377, 0f3F20D842;
+	mov.f32 	%f384, %f43;
+	@%p8 bra 	$L__BB0_10;
+	mul.f32 	%f384, %f11, %f11;
+	mov.f32 	%f383, 0f38B1E96A;
+	mov.f32 	%f382, 0fBA574D20;
+	mov.f32 	%f381, 0f3BAAD5EA;
+	mov.f32 	%f380, 0fBCDC1BE7;
+	mov.f32 	%f379, 0f3DE718AF;
+	mov.f32 	%f378, 0fBEC093AC;
+	mov.f32 	%f377, 0f3E0375D3;
+$L__BB0_10:
+	.loc	1 0 0
+	cvt.f32.bf16 %r10, %rs5;
+	mul.f32 	%f12, %f4, 0f3F3504F3;
+	.loc	1 30 23
+	setp.ltu.f32 	%p9, %f43, 0f3F8060FE;
+	fma.rn.ftz.f32 	%f185, %f383, %f384, %f382;
+	fma.rn.ftz.f32 	%f186, %f185, %f384, %f381;
+	fma.rn.ftz.f32 	%f187, %f186, %f384, %f380;
+	fma.rn.ftz.f32 	%f188, %f187, %f384, %f379;
+	fma.rn.ftz.f32 	%f189, %f188, %f384, %f378;
+	fma.rn.ftz.f32 	%f190, %f189, %f384, %f377;
+	neg.f32 	%f191, %f384;
+	selp.f32 	%f192, %f191, %f11, %p8;
+	fma.rn.ftz.f32 	%f385, %f190, %f192, %f192;
+	@%p9 bra 	$L__BB0_12;
+	ex2.approx.ftz.f32 	%f193, %f385;
+	sub.f32 	%f195, %f358, %f193;
+	mov.b32 	%r27, %f195;
+	mov.b32 	%r28, %f11;
+	and.b32  	%r29, %r28, -2147483648;
+	or.b32  	%r30, %r29, %r27;
+	mov.b32 	%f385, %r30;
+$L__BB0_12:
+	.loc	1 0 0
+	{ .reg .b16 tmp; mov.b32 {tmp, %rs6}, %r4; }
+	mov.b32 	%f5, %r10;
+	.loc	1 30 23
+	abs.ftz.f32 	%f56, %f12;
+	setp.ge.f32 	%p11, %f56, 0f3F8060FE;
+	mov.f32 	%f392, 0f3789CA3C;
+	mov.f32 	%f391, 0fB9F560B9;
+	mov.f32 	%f390, 0f3BAC840B;
+	mov.f32 	%f389, 0fBD0C8162;
+	mov.f32 	%f388, 0f3E1CF906;
+	mov.f32 	%f387, 0f3F6A937E;
+	mov.f32 	%f386, 0f3F20D842;
+	mov.f32 	%f393, %f56;
+	@%p11 bra 	$L__BB0_14;
+	mul.f32 	%f393, %f12, %f12;
+	mov.f32 	%f392, 0f38B1E96A;
+	mov.f32 	%f391, 0fBA574D20;
+	mov.f32 	%f390, 0f3BAAD5EA;
+	mov.f32 	%f389, 0fBCDC1BE7;
+	mov.f32 	%f388, 0f3DE718AF;
+	mov.f32 	%f387, 0fBEC093AC;
+	mov.f32 	%f386, 0f3E0375D3;
+$L__BB0_14:
+	.loc	1 0 0
+	cvt.f32.bf16 %r11, %rs6;
+	mul.f32 	%f13, %f5, 0f3F3504F3;
+	.loc	1 30 23
+	setp.ltu.f32 	%p12, %f56, 0f3F8060FE;
+	fma.rn.ftz.f32 	%f210, %f392, %f393, %f391;
+	fma.rn.ftz.f32 	%f211, %f210, %f393, %f390;
+	fma.rn.ftz.f32 	%f212, %f211, %f393, %f389;
+	fma.rn.ftz.f32 	%f213, %f212, %f393, %f388;
+	fma.rn.ftz.f32 	%f214, %f213, %f393, %f387;
+	fma.rn.ftz.f32 	%f215, %f214, %f393, %f386;
+	neg.f32 	%f216, %f393;
+	selp.f32 	%f217, %f216, %f12, %p11;
+	fma.rn.ftz.f32 	%f394, %f215, %f217, %f217;
+	@%p12 bra 	$L__BB0_16;
+	ex2.approx.ftz.f32 	%f218, %f394;
+	sub.f32 	%f220, %f358, %f218;
+	mov.b32 	%r31, %f220;
+	mov.b32 	%r32, %f12;
+	and.b32  	%r33, %r32, -2147483648;
+	or.b32  	%r34, %r33, %r31;
+	mov.b32 	%f394, %r34;
+$L__BB0_16:
+	.loc	1 0 0
+	cvt.u16.u32 	%rs7, %r5;
+	mov.b32 	%f6, %r11;
+	.loc	1 30 23
+	abs.ftz.f32 	%f69, %f13;
+	setp.ge.f32 	%p14, %f69, 0f3F8060FE;
+	mov.f32 	%f401, 0f3789CA3C;
+	mov.f32 	%f400, 0fB9F560B9;
+	mov.f32 	%f399, 0f3BAC840B;
+	mov.f32 	%f398, 0fBD0C8162;
+	mov.f32 	%f397, 0f3E1CF906;
+	mov.f32 	%f396, 0f3F6A937E;
+	mov.f32 	%f395, 0f3F20D842;
+	mov.f32 	%f402, %f69;
+	@%p14 bra 	$L__BB0_18;
+	mul.f32 	%f402, %f13, %f13;
+	mov.f32 	%f401, 0f38B1E96A;
+	mov.f32 	%f400, 0fBA574D20;
+	mov.f32 	%f399, 0f3BAAD5EA;
+	mov.f32 	%f398, 0fBCDC1BE7;
+	mov.f32 	%f397, 0f3DE718AF;
+	mov.f32 	%f396, 0fBEC093AC;
+	mov.f32 	%f395, 0f3E0375D3;
+$L__BB0_18:
+	.loc	1 0 0
+	cvt.f32.bf16 %r12, %rs7;
+	mul.f32 	%f14, %f6, 0f3F3504F3;
+	.loc	1 30 23
+	setp.ltu.f32 	%p15, %f69, 0f3F8060FE;
+	fma.rn.ftz.f32 	%f235, %f401, %f402, %f400;
+	fma.rn.ftz.f32 	%f236, %f235, %f402, %f399;
+	fma.rn.ftz.f32 	%f237, %f236, %f402, %f398;
+	fma.rn.ftz.f32 	%f238, %f237, %f402, %f397;
+	fma.rn.ftz.f32 	%f239, %f238, %f402, %f396;
+	fma.rn.ftz.f32 	%f240, %f239, %f402, %f395;
+	neg.f32 	%f241, %f402;
+	selp.f32 	%f242, %f241, %f13, %p14;
+	fma.rn.ftz.f32 	%f403, %f240, %f242, %f242;
+	@%p15 bra 	$L__BB0_20;
+	ex2.approx.ftz.f32 	%f243, %f403;
+	sub.f32 	%f245, %f358, %f243;
+	mov.b32 	%r35, %f245;
+	mov.b32 	%r36, %f13;
+	and.b32  	%r37, %r36, -2147483648;
+	or.b32  	%r38, %r37, %r35;
+	mov.b32 	%f403, %r38;
+$L__BB0_20:
+	.loc	1 0 0
+	{ .reg .b16 tmp; mov.b32 {tmp, %rs8}, %r5; }
+	mov.b32 	%f7, %r12;
+	.loc	1 30 23
+	abs.ftz.f32 	%f82, %f14;
+	setp.ge.f32 	%p17, %f82, 0f3F8060FE;
+	mov.f32 	%f410, 0f3789CA3C;
+	mov.f32 	%f409, 0fB9F560B9;
+	mov.f32 	%f408, 0f3BAC840B;
+	mov.f32 	%f407, 0fBD0C8162;
+	mov.f32 	%f406, 0f3E1CF906;
+	mov.f32 	%f405, 0f3F6A937E;
+	mov.f32 	%f404, 0f3F20D842;
+	mov.f32 	%f411, %f82;
+	@%p17 bra 	$L__BB0_22;
+	mul.f32 	%f411, %f14, %f14;
+	mov.f32 	%f410, 0f38B1E96A;
+	mov.f32 	%f409, 0fBA574D20;
+	mov.f32 	%f408, 0f3BAAD5EA;
+	mov.f32 	%f407, 0fBCDC1BE7;
+	mov.f32 	%f406, 0f3DE718AF;
+	mov.f32 	%f405, 0fBEC093AC;
+	mov.f32 	%f404, 0f3E0375D3;
+$L__BB0_22:
+	.loc	1 0 0
+	cvt.f32.bf16 %r13, %rs8;
+	mul.f32 	%f15, %f7, 0f3F3504F3;
+	.loc	1 30 23
+	setp.ltu.f32 	%p18, %f82, 0f3F8060FE;
+	fma.rn.ftz.f32 	%f260, %f410, %f411, %f409;
+	fma.rn.ftz.f32 	%f261, %f260, %f411, %f408;
+	fma.rn.ftz.f32 	%f262, %f261, %f411, %f407;
+	fma.rn.ftz.f32 	%f263, %f262, %f411, %f406;
+	fma.rn.ftz.f32 	%f264, %f263, %f411, %f405;
+	fma.rn.ftz.f32 	%f265, %f264, %f411, %f404;
+	neg.f32 	%f266, %f411;
+	selp.f32 	%f267, %f266, %f14, %p17;
+	fma.rn.ftz.f32 	%f412, %f265, %f267, %f267;
+	@%p18 bra 	$L__BB0_24;
+	ex2.approx.ftz.f32 	%f268, %f412;
+	sub.f32 	%f270, %f358, %f268;
+	mov.b32 	%r39, %f270;
+	mov.b32 	%r40, %f14;
+	and.b32  	%r41, %r40, -2147483648;
+	or.b32  	%r42, %r41, %r39;
+	mov.b32 	%f412, %r42;
+$L__BB0_24:
+	.loc	1 0 0
+	mov.b32 	%f8, %r13;
+	.loc	1 30 23
+	abs.ftz.f32 	%f95, %f15;
+	setp.ge.f32 	%p20, %f95, 0f3F8060FE;
+	mov.f32 	%f419, 0f3789CA3C;
+	mov.f32 	%f418, 0fB9F560B9;
+	mov.f32 	%f417, 0f3BAC840B;
+	mov.f32 	%f416, 0fBD0C8162;
+	mov.f32 	%f415, 0f3E1CF906;
+	mov.f32 	%f414, 0f3F6A937E;
+	mov.f32 	%f413, 0f3F20D842;
+	mov.f32 	%f420, %f95;
+	@%p20 bra 	$L__BB0_26;
+	mul.f32 	%f420, %f15, %f15;
+	mov.f32 	%f419, 0f38B1E96A;
+	mov.f32 	%f418, 0fBA574D20;
+	mov.f32 	%f417, 0f3BAAD5EA;
+	mov.f32 	%f416, 0fBCDC1BE7;
+	mov.f32 	%f415, 0f3DE718AF;
+	mov.f32 	%f414, 0fBEC093AC;
+	mov.f32 	%f413, 0f3E0375D3;
+$L__BB0_26:
+	.loc	1 0 0
+	mul.f32 	%f16, %f8, 0f3F3504F3;
+	.loc	1 30 23
+	setp.ltu.f32 	%p21, %f95, 0f3F8060FE;
+	fma.rn.ftz.f32 	%f285, %f419, %f420, %f418;
+	fma.rn.ftz.f32 	%f286, %f285, %f420, %f417;
+	fma.rn.ftz.f32 	%f287, %f286, %f420, %f416;
+	fma.rn.ftz.f32 	%f288, %f287, %f420, %f415;
+	fma.rn.ftz.f32 	%f289, %f288, %f420, %f414;
+	fma.rn.ftz.f32 	%f290, %f289, %f420, %f413;
+	neg.f32 	%f291, %f420;
+	selp.f32 	%f292, %f291, %f15, %p20;
+	fma.rn.ftz.f32 	%f421, %f290, %f292, %f292;
+	@%p21 bra 	$L__BB0_28;
+	ex2.approx.ftz.f32 	%f293, %f421;
+	sub.f32 	%f295, %f358, %f293;
+	mov.b32 	%r43, %f295;
+	mov.b32 	%r44, %f15;
+	and.b32  	%r45, %r44, -2147483648;
+	or.b32  	%r46, %r45, %r43;
+	mov.b32 	%f421, %r46;
+$L__BB0_28:
+	abs.ftz.f32 	%f108, %f16;
+	setp.ge.f32 	%p23, %f108, 0f3F8060FE;
+	mov.f32 	%f428, 0f3789CA3C;
+	mov.f32 	%f427, 0fB9F560B9;
+	mov.f32 	%f426, 0f3BAC840B;
+	mov.f32 	%f425, 0fBD0C8162;
+	mov.f32 	%f424, 0f3E1CF906;
+	mov.f32 	%f423, 0f3F6A937E;
+	mov.f32 	%f422, 0f3F20D842;
+	mov.f32 	%f429, %f108;
+	@%p23 bra 	$L__BB0_30;
+	mul.f32 	%f429, %f16, %f16;
+	mov.f32 	%f428, 0f38B1E96A;
+	mov.f32 	%f427, 0fBA574D20;
+	mov.f32 	%f426, 0f3BAAD5EA;
+	mov.f32 	%f425, 0fBCDC1BE7;
+	mov.f32 	%f424, 0f3DE718AF;
+	mov.f32 	%f423, 0fBEC093AC;
+	mov.f32 	%f422, 0f3E0375D3;
+$L__BB0_30:
+	setp.ltu.f32 	%p24, %f108, 0f3F8060FE;
+	fma.rn.ftz.f32 	%f310, %f428, %f429, %f427;
+	fma.rn.ftz.f32 	%f311, %f310, %f429, %f426;
+	fma.rn.ftz.f32 	%f312, %f311, %f429, %f425;
+	fma.rn.ftz.f32 	%f313, %f312, %f429, %f424;
+	fma.rn.ftz.f32 	%f314, %f313, %f429, %f423;
+	fma.rn.ftz.f32 	%f315, %f314, %f429, %f422;
+	neg.f32 	%f316, %f429;
+	selp.f32 	%f317, %f316, %f16, %p23;
+	fma.rn.ftz.f32 	%f430, %f315, %f317, %f317;
+	@%p24 bra 	$L__BB0_32;
+	ex2.approx.ftz.f32 	%f318, %f430;
+	sub.f32 	%f320, %f358, %f318;
+	mov.b32 	%r47, %f320;
+	mov.b32 	%r48, %f16;
+	and.b32  	%r49, %r48, -2147483648;
+	or.b32  	%r50, %r49, %r47;
+	mov.b32 	%f430, %r50;
+$L__BB0_32:
+	.loc	1 27 18
+	mul.f32 	%f321, %f8, 0f3F000000;
+	mul.f32 	%f322, %f7, 0f3F000000;
+	mul.f32 	%f323, %f6, 0f3F000000;
+	mul.f32 	%f324, %f5, 0f3F000000;
+	mul.f32 	%f325, %f4, 0f3F000000;
+	mul.f32 	%f326, %f3, 0f3F000000;
+	mul.f32 	%f327, %f2, 0f3F000000;
+	mul.f32 	%f328, %f1, 0f3F000000;
+	.loc	1 32 18
+	add.f32 	%f329, %f367, 0f3F800000;
+	add.f32 	%f330, %f376, 0f3F800000;
+	add.f32 	%f331, %f385, 0f3F800000;
+	add.f32 	%f332, %f394, 0f3F800000;
+	add.f32 	%f333, %f403, 0f3F800000;
+	add.f32 	%f334, %f412, 0f3F800000;
+	add.f32 	%f335, %f421, 0f3F800000;
+	add.f32 	%f336, %f430, 0f3F800000;
+	.loc	1 33 18
+	mul.f32 	%f337, %f328, %f329;
+	mul.f32 	%f338, %f327, %f330;
+	mul.f32 	%f339, %f326, %f331;
+	mul.f32 	%f340, %f325, %f332;
+	mul.f32 	%f341, %f324, %f333;
+	mul.f32 	%f342, %f323, %f334;
+	mul.f32 	%f343, %f322, %f335;
+	mul.f32 	%f344, %f321, %f336;
+	.loc	1 35 40
+	mov.b32 	%r51, %f337;
+	cvt.rn.bf16.f32 %rs9, %r51;
+	mov.b32 	%r52, %f338;
+	cvt.rn.bf16.f32 %rs10, %r52;
+	mov.b32 	%r53, %f339;
+	cvt.rn.bf16.f32 %rs11, %r53;
+	mov.b32 	%r54, %f340;
+	cvt.rn.bf16.f32 %rs12, %r54;
+	mov.b32 	%r55, %f341;
+	cvt.rn.bf16.f32 %rs13, %r55;
+	mov.b32 	%r56, %f342;
+	cvt.rn.bf16.f32 %rs14, %r56;
+	mov.b32 	%r57, %f343;
+	cvt.rn.bf16.f32 %rs15, %r57;
+	mov.b32 	%r58, %f344;
+	cvt.rn.bf16.f32 %rs16, %r58;
+	mov.b32 	%r63, {%rs9, %rs10};
+	mov.b32 	%r64, {%rs11, %rs12};
+	mov.b32 	%r65, {%rs13, %rs14};
+	mov.b32 	%r66, {%rs15, %rs16};
+	@%p1 st.global.v4.b32 [ %rd5 + 0 ], { %r63, %r64, %r65, %r66 };
+	.loc	1 35 4
+	ret;
+$L__tmp1:
+$L__func_end0:
+
+}
+	// .globl	__nv_erff
+.visible .func  (.param .b32 func_retval0) __nv_erff(
+	.param .b32 __nv_erff_param_0
+)
+{
+	.reg .pred 	%p<4>;
+	.reg .b32 	%r<5>;
+	.reg .f32 	%f<49>;
+$L__func_begin1:
+
+	ld.param.f32 	%f14, [__nv_erff_param_0];
+	abs.ftz.f32 	%f1, %f14;
+	setp.ge.f32 	%p1, %f1, 0f3F8060FE;
+	mov.f32 	%f46, 0f3789CA3C;
+	mov.f32 	%f45, 0fB9F560B9;
+	mov.f32 	%f44, 0f3BAC840B;
+	mov.f32 	%f43, 0fBD0C8162;
+	mov.f32 	%f42, 0f3E1CF906;
+	mov.f32 	%f41, 0f3F6A937E;
+	mov.f32 	%f40, 0f3F20D842;
+	mov.f32 	%f47, %f1;
+	@%p1 bra 	$L__BB1_2;
+	mul.f32 	%f47, %f14, %f14;
+	mov.f32 	%f46, 0f38B1E96A;
+	mov.f32 	%f45, 0fBA574D20;
+	mov.f32 	%f44, 0f3BAAD5EA;
+	mov.f32 	%f43, 0fBCDC1BE7;
+	mov.f32 	%f42, 0f3DE718AF;
+	mov.f32 	%f41, 0fBEC093AC;
+	mov.f32 	%f40, 0f3E0375D3;
+$L__BB1_2:
+	setp.ltu.f32 	%p2, %f1, 0f3F8060FE;
+	fma.rn.ftz.f32 	%f29, %f46, %f47, %f45;
+	fma.rn.ftz.f32 	%f30, %f29, %f47, %f44;
+	fma.rn.ftz.f32 	%f31, %f30, %f47, %f43;
+	fma.rn.ftz.f32 	%f32, %f31, %f47, %f42;
+	fma.rn.ftz.f32 	%f33, %f32, %f47, %f41;
+	fma.rn.ftz.f32 	%f34, %f33, %f47, %f40;
+	neg.f32 	%f35, %f47;
+	selp.f32 	%f36, %f35, %f14, %p1;
+	fma.rn.ftz.f32 	%f48, %f34, %f36, %f36;
+	@%p2 bra 	$L__BB1_4;
+	ex2.approx.ftz.f32 	%f37, %f48;
+	mov.f32 	%f38, 0f3F800000;
+	sub.f32 	%f39, %f38, %f37;
+	mov.b32 	%r1, %f39;
+	mov.b32 	%r2, %f14;
+	and.b32  	%r3, %r2, -2147483648;
+	or.b32  	%r4, %r3, %r1;
+	mov.b32 	%f48, %r4;
+$L__BB1_4:
+	st.param.f32 	[func_retval0+0], %f48;
+	ret;
+$L__func_end1:
+
+}
+	.file	1 "/tmp/torchinductor_root/af/cafucwnmq4o436kwzkmrinerrnocxll7q6wsadcl726g6cradipo.py"
+	.section	.debug_abbrev
+	{
+.b8 1
+.b8 17
+.b8 1
+.b8 37
+.b8 8
+.b8 19
+.b8 5
+.b8 3
+.b8 8
+.b8 16
+.b8 6
+.b8 27
+.b8 8
+.b8 180
+.b8 66
+.b8 12
+.b8 17
+.b8 1
+.b8 18
+.b8 1
+.b8 0
+.b8 0
+.b8 2
+.b8 46
+.b8 0
+.b8 17
+.b8 1
+.b8 18
+.b8 1
+.b8 64
+.b8 10
+.b8 135
+.b8 64
+.b8 8
+.b8 3
+.b8 8
+.b8 58
+.b8 11
+.b8 59
+.b8 11
+.b8 63
+.b8 12
+.b8 0
+.b8 0
+.b8 0
+	}
+	.section	.debug_info
+	{
+.b32 172
+.b8 2
+.b8 0
+.b32 .debug_abbrev
+.b8 8
+.b8 1
+.b8 116
+.b8 114
+.b8 105
+.b8 116
+.b8 111
+.b8 110
+.b8 0
+.b8 2
+.b8 0
+.b8 99
+.b8 97
+.b8 102
+.b8 117
+.b8 99
+.b8 119
+.b8 110
+.b8 109
+.b8 113
+.b8 52
+.b8 111
+.b8 52
+.b8 51
+.b8 54
+.b8 107
+.b8 119
+.b8 122
+.b8 107
+.b8 109
+.b8 114
+.b8 105
+.b8 110
+.b8 101
+.b8 114
+.b8 114
+.b8 110
+.b8 111
+.b8 99
+.b8 120
+.b8 108
+.b8 108
+.b8 55
+.b8 113
+.b8 54
+.b8 119
+.b8 115
+.b8 97
+.b8 100
+.b8 99
+.b8 108
+.b8 55
+.b8 50
+.b8 54
+.b8 103
+.b8 54
+.b8 99
+.b8 114
+.b8 97
+.b8 100
+.b8 105
+.b8 112
+.b8 111
+.b8 46
+.b8 112
+.b8 121
+.b8 0
+.b32 .debug_line
+.b8 47
+.b8 116
+.b8 109
+.b8 112
+.b8 47
+.b8 116
+.b8 111
+.b8 114
+.b8 99
+.b8 104
+.b8 105
+.b8 110
+.b8 100
+.b8 117
+.b8 99
+.b8 116
+.b8 111
+.b8 114
+.b8 95
+.b8 114
+.b8 111
+.b8 111
+.b8 116
+.b8 47
+.b8 97
+.b8 102
+.b8 0
+.b8 1
+.b64 $L__func_begin0
+.b64 $L__func_end0
+.b8 2
+.b64 $L__func_begin0
+.b64 $L__func_end0
+.b8 1
+.b8 156
+.b8 116
+.b8 114
+.b8 105
+.b8 116
+.b8 111
+.b8 110
+.b8 95
+.b8 95
+.b8 48
+.b8 100
+.b8 49
+.b8 100
+.b8 101
+.b8 0
+.b8 116
+.b8 114
+.b8 105
+.b8 116
+.b8 111
+.b8 110
+.b8 95
+.b8 95
+.b8 48
+.b8 100
+.b8 49
+.b8 100
+.b8 101
+.b8 0
+.b8 1
+.b8 18
+.b8 1
+.b8 0
+	}
+	.section	.debug_pubnames
+	{
+.b32 $L__pubNames_end0-$L__pubNames_start0
+$L__pubNames_start0:
+.b8 2
+.b8 0
+.b32 .debug_info
+.b32 176
+.b32 125
+.b8 116
+.b8 114
+.b8 105
+.b8 116
+.b8 111
+.b8 110
+.b8 95
+.b8 95
+.b8 48
+.b8 100
+.b8 49
+.b8 100
+.b8 101
+.b8 0
+.b32 0
+$L__pubNames_end0:
+	}
+	.section	.debug_pubtypes
+	{
+.b32 $L__pubTypes_end0-$L__pubTypes_start0
+$L__pubTypes_start0:
+.b8 2
+.b8 0
+.b32 .debug_info
+.b32 176
+.b32 0
+$L__pubTypes_end0:
+	}
+	.section	.debug_loc	{	}

.triton/dump/10ca9c2c168e8529fb752d28f80c40a5/triton_.ttgir

@@ -0,0 +1,26 @@
+#blocked = #triton_gpu.blocked<{sizePerThread = [8], threadsPerWarp = [32], warpsPerCTA = [4], order = [0], CTAsPerCGA = [1], CTASplitNum = [1], CTAOrder = [0]}>
+module attributes {"triton_gpu.compute-capability" = 89 : i32, "triton_gpu.num-ctas" = 1 : i32, "triton_gpu.num-warps" = 4 : i32, "triton_gpu.threads-per-warp" = 32 : i32} {
+  tt.func public @triton__0d1de(%arg0: !tt.ptr<bf16, 1> {tt.divisibility = 16 : i32}, %arg1: i32 {tt.divisibility = 16 : i32, tt.max_divisibility = 16 : i32}) attributes {noinline = false} {
+    %cst = arith.constant dense<1.000000e+00> : tensor<1024xf32, #blocked>
+    %cst_0 = arith.constant dense<0.707106769> : tensor<1024xf32, #blocked>
+    %cst_1 = arith.constant dense<5.000000e-01> : tensor<1024xf32, #blocked>
+    %c1024_i32 = arith.constant 1024 : i32
+    %0 = tt.get_program_id x : i32
+    %1 = arith.muli %0, %c1024_i32 : i32
+    %2 = tt.make_range {end = 1024 : i32, start = 0 : i32} : tensor<1024xi32, #blocked>
+    %3 = tt.splat %1 : (i32) -> tensor<1024xi32, #blocked>
+    %4 = arith.addi %3, %2 : tensor<1024xi32, #blocked>
+    %5 = tt.splat %arg0 : (!tt.ptr<bf16, 1>) -> tensor<1024x!tt.ptr<bf16, 1>, #blocked>
+    %6 = tt.addptr %5, %4 : tensor<1024x!tt.ptr<bf16, 1>, #blocked>, tensor<1024xi32, #blocked>
+    %7 = tt.load %6 {cache = 1 : i32, evict = 1 : i32, isVolatile = false} : tensor<1024xbf16, #blocked>
+    %8 = arith.extf %7 : tensor<1024xbf16, #blocked> to tensor<1024xf32, #blocked>
+    %9 = arith.mulf %8, %cst_1 : tensor<1024xf32, #blocked>
+    %10 = arith.mulf %8, %cst_0 : tensor<1024xf32, #blocked>
+    %11 = tt.extern_elementwise %10 {libname = "libdevice", libpath = "/usr/local/lib/python3.10/dist-packages/triton/language/../third_party/cuda/lib/libdevice.10.bc", pure = true, symbol = "__nv_erff"} : (tensor<1024xf32, #blocked>) -> tensor<1024xf32, #blocked>
+    %12 = arith.addf %11, %cst : tensor<1024xf32, #blocked>
+    %13 = arith.mulf %9, %12 : tensor<1024xf32, #blocked>
+    %14 = arith.truncf %13 : tensor<1024xf32, #blocked> to tensor<1024xbf16, #blocked>
+    tt.store %6, %14 {cache = 1 : i32, evict = 1 : i32} : tensor<1024xbf16, #blocked>
+    tt.return
+  }
+}

.triton/dump/10ca9c2c168e8529fb752d28f80c40a5/triton_.ttir

@@ -0,0 +1,25 @@
+module {
+  tt.func public @triton__0d1de(%arg0: !tt.ptr<bf16, 1> {tt.divisibility = 16 : i32}, %arg1: i32 {tt.divisibility = 16 : i32, tt.max_divisibility = 16 : i32}) attributes {noinline = false} {
+    %cst = arith.constant dense<1.000000e+00> : tensor<1024xf32>
+    %cst_0 = arith.constant dense<0.707106769> : tensor<1024xf32>
+    %cst_1 = arith.constant dense<5.000000e-01> : tensor<1024xf32>
+    %c1024_i32 = arith.constant 1024 : i32
+    %0 = tt.get_program_id x : i32
+    %1 = arith.muli %0, %c1024_i32 : i32
+    %2 = tt.make_range {end = 1024 : i32, start = 0 : i32} : tensor<1024xi32>
+    %3 = tt.splat %1 : (i32) -> tensor<1024xi32>
+    %4 = arith.addi %3, %2 : tensor<1024xi32>
+    %5 = tt.splat %arg0 : (!tt.ptr<bf16, 1>) -> tensor<1024x!tt.ptr<bf16, 1>>
+    %6 = tt.addptr %5, %4 : tensor<1024x!tt.ptr<bf16, 1>>, tensor<1024xi32>
+    %7 = tt.load %6 {cache = 1 : i32, evict = 1 : i32, isVolatile = false} : tensor<1024xbf16>
+    %8 = arith.extf %7 : tensor<1024xbf16> to tensor<1024xf32>
+    %9 = arith.mulf %8, %cst_1 : tensor<1024xf32>
+    %10 = arith.mulf %8, %cst_0 : tensor<1024xf32>
+    %11 = tt.extern_elementwise %10 {libname = "libdevice", libpath = "/usr/local/lib/python3.10/dist-packages/triton/language/../third_party/cuda/lib/libdevice.10.bc", pure = true, symbol = "__nv_erff"} : (tensor<1024xf32>) -> tensor<1024xf32>
+    %12 = arith.addf %11, %cst : tensor<1024xf32>
+    %13 = arith.mulf %9, %12 : tensor<1024xf32>
+    %14 = arith.truncf %13 : tensor<1024xf32> to tensor<1024xbf16>
+    tt.store %6, %14 {cache = 1 : i32, evict = 1 : i32} : tensor<1024xbf16>
+    tt.return
+  }
+}

.triton/dump/127102ca642eeddf1a14ce3904d9fabf/triton_.llir

@@ -0,0 +1,290 @@
+; ModuleID = 'LLVMDialectModule'
+source_filename = "LLVMDialectModule"
+
+@global_smem = external addrspace(3) global [0 x i8]
+
+define void @triton__0d1d2d3de4e(ptr addrspace(1) %0, ptr addrspace(1) %1, ptr addrspace(1) %2, i32 %3, i32 %4) local_unnamed_addr !dbg !5 {
+  %6 = tail call i32 @llvm.nvvm.read.ptx.sreg.tid.x(), !dbg !8
+  %7 = and i32 %6, 31, !dbg !8
+  %8 = lshr i32 %6, 5, !dbg !8
+  %9 = and i32 %6, 7, !dbg !8
+  %10 = shl nuw nsw i32 %9, 2, !dbg !8
+  %11 = and i32 %8, 7, !dbg !9
+  %12 = lshr i32 %7, 3, !dbg !9
+  %13 = shl nuw nsw i32 %11, 2, !dbg !9
+  %14 = or i32 %13, %12, !dbg !9
+  %15 = or i32 %14, 96, !dbg !9
+  %16 = or i32 %10, 1, !dbg !10
+  %17 = or i32 %10, 2, !dbg !10
+  %18 = or i32 %10, 3, !dbg !10
+  %19 = tail call i32 asm "mov.u32 $0, %ctaid.x;", "=r"() #3, !dbg !14
+  %20 = shl i32 %19, 5, !dbg !15
+  %21 = or i32 %20, %10, !dbg !16
+  %22 = or i32 %20, %7, !dbg !16
+  %23 = icmp ult i32 %15, 120, !dbg !17
+  %24 = shl nuw nsw i32 %14, 17, !dbg !18
+  %25 = or i32 %24, 4194304, !dbg !18
+  %26 = or i32 %24, 8388608, !dbg !18
+  %27 = shl nuw nsw i32 %15, 17, !dbg !18
+  %28 = add i32 %21, %24, !dbg !19
+  %29 = add i32 %25, %21, !dbg !19
+  %30 = add i32 %26, %21, !dbg !19
+  %31 = add i32 %21, %27, !dbg !19
+  %32 = sext i32 %28 to i64, !dbg !20
+  %33 = getelementptr float, ptr addrspace(1) %0, i64 %32, !dbg !20
+  %34 = sext i32 %29 to i64, !dbg !20
+  %35 = getelementptr float, ptr addrspace(1) %0, i64 %34, !dbg !20
+  %36 = sext i32 %30 to i64, !dbg !20
+  %37 = getelementptr float, ptr addrspace(1) %0, i64 %36, !dbg !20
+  %38 = sext i32 %31 to i64, !dbg !20
+  %39 = getelementptr float, ptr addrspace(1) %0, i64 %38, !dbg !20
+  %40 = tail call { i32, i32, i32, i32 } asm sideeffect "mov.u32 $0, 0x0;\0A\09mov.u32 $1, 0x0;\0A\09mov.u32 $2, 0x0;\0A\09mov.u32 $3, 0x0;\0A\09@$5 ld.global.L1::evict_first.v4.b32 { $0, $1, $2, $3 }, [ $4 + 0 ];\0A\09@!$7 mov.u32 $0, $6;\0A\09@!$9 mov.u32 $1, $8;\0A\09@!$11 mov.u32 $2, $10;\0A\09@!$13 mov.u32 $3, $12;", "=r,=r,=r,=r,l,b,r,b,r,b,r,b,r,b"(ptr addrspace(1) %33, i1 true, i32 0, i1 true, i32 0, i1 true, i32 0, i1 true, i32 0, i1 true) #3, !dbg !21
+  %41 = extractvalue { i32, i32, i32, i32 } %40, 0, !dbg !21
+  %42 = extractvalue { i32, i32, i32, i32 } %40, 1, !dbg !21
+  %43 = extractvalue { i32, i32, i32, i32 } %40, 2, !dbg !21
+  %44 = extractvalue { i32, i32, i32, i32 } %40, 3, !dbg !21
+  %45 = bitcast i32 %41 to float, !dbg !21
+  %46 = bitcast i32 %42 to float, !dbg !21
+  %47 = bitcast i32 %43 to float, !dbg !21
+  %48 = bitcast i32 %44 to float, !dbg !21
+  %49 = tail call { i32, i32, i32, i32 } asm sideeffect "mov.u32 $0, 0x0;\0A\09mov.u32 $1, 0x0;\0A\09mov.u32 $2, 0x0;\0A\09mov.u32 $3, 0x0;\0A\09@$5 ld.global.L1::evict_first.v4.b32 { $0, $1, $2, $3 }, [ $4 + 0 ];\0A\09@!$7 mov.u32 $0, $6;\0A\09@!$9 mov.u32 $1, $8;\0A\09@!$11 mov.u32 $2, $10;\0A\09@!$13 mov.u32 $3, $12;", "=r,=r,=r,=r,l,b,r,b,r,b,r,b,r,b"(ptr addrspace(1) %35, i1 true, i32 0, i1 true, i32 0, i1 true, i32 0, i1 true, i32 0, i1 true) #3, !dbg !21
+  %50 = extractvalue { i32, i32, i32, i32 } %49, 0, !dbg !21
+  %51 = extractvalue { i32, i32, i32, i32 } %49, 1, !dbg !21
+  %52 = extractvalue { i32, i32, i32, i32 } %49, 2, !dbg !21
+  %53 = extractvalue { i32, i32, i32, i32 } %49, 3, !dbg !21
+  %54 = bitcast i32 %50 to float, !dbg !21
+  %55 = bitcast i32 %51 to float, !dbg !21
+  %56 = bitcast i32 %52 to float, !dbg !21
+  %57 = bitcast i32 %53 to float, !dbg !21
+  %58 = tail call { i32, i32, i32, i32 } asm sideeffect "mov.u32 $0, 0x0;\0A\09mov.u32 $1, 0x0;\0A\09mov.u32 $2, 0x0;\0A\09mov.u32 $3, 0x0;\0A\09@$5 ld.global.L1::evict_first.v4.b32 { $0, $1, $2, $3 }, [ $4 + 0 ];\0A\09@!$7 mov.u32 $0, $6;\0A\09@!$9 mov.u32 $1, $8;\0A\09@!$11 mov.u32 $2, $10;\0A\09@!$13 mov.u32 $3, $12;", "=r,=r,=r,=r,l,b,r,b,r,b,r,b,r,b"(ptr addrspace(1) %37, i1 true, i32 0, i1 true, i32 0, i1 true, i32 0, i1 true, i32 0, i1 true) #3, !dbg !21
+  %59 = extractvalue { i32, i32, i32, i32 } %58, 0, !dbg !21
+  %60 = extractvalue { i32, i32, i32, i32 } %58, 1, !dbg !21
+  %61 = extractvalue { i32, i32, i32, i32 } %58, 2, !dbg !21
+  %62 = extractvalue { i32, i32, i32, i32 } %58, 3, !dbg !21
+  %63 = bitcast i32 %59 to float, !dbg !21
+  %64 = bitcast i32 %60 to float, !dbg !21
+  %65 = bitcast i32 %61 to float, !dbg !21
+  %66 = bitcast i32 %62 to float, !dbg !21
+  %67 = tail call { i32, i32, i32, i32 } asm sideeffect "mov.u32 $0, 0x0;\0A\09mov.u32 $1, 0x0;\0A\09mov.u32 $2, 0x0;\0A\09mov.u32 $3, 0x0;\0A\09@$5 ld.global.L1::evict_first.v4.b32 { $0, $1, $2, $3 }, [ $4 + 0 ];\0A\09@!$7 mov.u32 $0, $6;\0A\09@!$9 mov.u32 $1, $8;\0A\09@!$11 mov.u32 $2, $10;\0A\09@!$13 mov.u32 $3, $12;", "=r,=r,=r,=r,l,b,r,b,r,b,r,b,r,b"(ptr addrspace(1) %39, i1 %23, i32 0, i1 %23, i32 0, i1 %23, i32 0, i1 %23, i32 0, i1 %23) #3, !dbg !21
+  %68 = extractvalue { i32, i32, i32, i32 } %67, 0, !dbg !21
+  %69 = extractvalue { i32, i32, i32, i32 } %67, 1, !dbg !21
+  %70 = extractvalue { i32, i32, i32, i32 } %67, 2, !dbg !21
+  %71 = extractvalue { i32, i32, i32, i32 } %67, 3, !dbg !21
+  %72 = bitcast i32 %68 to float, !dbg !21
+  %73 = bitcast i32 %69 to float, !dbg !21
+  %74 = bitcast i32 %70 to float, !dbg !21
+  %75 = bitcast i32 %71 to float, !dbg !21
+  %76 = fadd float %45, 0.000000e+00, !dbg !22
+  %77 = fadd float %46, 0.000000e+00, !dbg !22
+  %78 = fadd float %47, 0.000000e+00, !dbg !22
+  %79 = fadd float %48, 0.000000e+00, !dbg !22
+  %80 = fadd float %54, 0.000000e+00, !dbg !22
+  %81 = fadd float %55, 0.000000e+00, !dbg !22
+  %82 = fadd float %56, 0.000000e+00, !dbg !22
+  %83 = fadd float %57, 0.000000e+00, !dbg !22
+  %84 = fadd float %63, 0.000000e+00, !dbg !22
+  %85 = fadd float %64, 0.000000e+00, !dbg !22
+  %86 = fadd float %65, 0.000000e+00, !dbg !22
+  %87 = fadd float %66, 0.000000e+00, !dbg !22
+  %88 = fadd float %72, 0.000000e+00, !dbg !22
+  %89 = fadd float %73, 0.000000e+00, !dbg !22
+  %90 = fadd float %74, 0.000000e+00, !dbg !22
+  %91 = fadd float %75, 0.000000e+00, !dbg !22
+  %92 = select i1 %23, float %88, float 0.000000e+00, !dbg !23
+  %93 = select i1 %23, float %89, float 0.000000e+00, !dbg !23
+  %94 = select i1 %23, float %90, float 0.000000e+00, !dbg !23
+  %95 = select i1 %23, float %91, float 0.000000e+00, !dbg !23
+  %96 = fadd float %76, %80, !dbg !24
+  %97 = fadd float %77, %81, !dbg !24
+  %98 = fadd float %78, %82, !dbg !24
+  %99 = fadd float %79, %83, !dbg !24
+  %100 = fadd float %96, %84, !dbg !24
+  %101 = fadd float %97, %85, !dbg !24
+  %102 = fadd float %98, %86, !dbg !24
+  %103 = fadd float %99, %87, !dbg !24
+  %104 = fadd float %100, %92, !dbg !24
+  %105 = fadd float %101, %93, !dbg !24
+  %106 = fadd float %102, %94, !dbg !24
+  %107 = fadd float %103, %95, !dbg !24
+  %108 = bitcast float %104 to i32, !dbg !10
+  %109 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %108, i32 16, i32 31), !dbg !10
+  %110 = bitcast i32 %109 to float, !dbg !10
+  %111 = fadd float %104, %110, !dbg !24
+  %112 = bitcast float %111 to i32, !dbg !10
+  %113 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %112, i32 8, i32 31), !dbg !10
+  %114 = bitcast i32 %113 to float, !dbg !10
+  %115 = fadd float %111, %114, !dbg !24
+  %116 = bitcast float %105 to i32, !dbg !10
+  %117 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %116, i32 16, i32 31), !dbg !10
+  %118 = bitcast i32 %117 to float, !dbg !10
+  %119 = fadd float %105, %118, !dbg !24
+  %120 = bitcast float %119 to i32, !dbg !10
+  %121 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %120, i32 8, i32 31), !dbg !10
+  %122 = bitcast i32 %121 to float, !dbg !10
+  %123 = fadd float %119, %122, !dbg !24
+  %124 = bitcast float %106 to i32, !dbg !10
+  %125 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %124, i32 16, i32 31), !dbg !10
+  %126 = bitcast i32 %125 to float, !dbg !10
+  %127 = fadd float %106, %126, !dbg !24
+  %128 = bitcast float %127 to i32, !dbg !10
+  %129 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %128, i32 8, i32 31), !dbg !10
+  %130 = bitcast i32 %129 to float, !dbg !10
+  %131 = fadd float %127, %130, !dbg !24
+  %132 = bitcast float %107 to i32, !dbg !10
+  %133 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %132, i32 16, i32 31), !dbg !10
+  %134 = bitcast i32 %133 to float, !dbg !10
+  %135 = fadd float %107, %134, !dbg !24
+  %136 = bitcast float %135 to i32, !dbg !10
+  %137 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %136, i32 8, i32 31), !dbg !10
+  %138 = bitcast i32 %137 to float, !dbg !10
+  %139 = fadd float %135, %138, !dbg !24
+  %140 = icmp ult i32 %7, 8, !dbg !10
+  %141 = shl nuw nsw i32 %9, 5, !dbg !10
+  %142 = or i32 %141, %11, !dbg !10
+  %143 = zext nneg i32 %142 to i64, !dbg !10
+  %144 = getelementptr float, ptr addrspace(3) @global_smem, i64 %143, !dbg !10
+  tail call void asm sideeffect "@$2 st.shared.b32 [ $0 + 0 ], $1;", "r,r,b"(ptr addrspace(3) %144, float %115, i1 %140) #3, !dbg !10
+  %145 = shl nuw nsw i32 %16, 3, !dbg !10
+  %146 = or i32 %145, %11, !dbg !10
+  %147 = zext nneg i32 %146 to i64, !dbg !10
+  %148 = getelementptr float, ptr addrspace(3) @global_smem, i64 %147, !dbg !10
+  tail call void asm sideeffect "@$2 st.shared.b32 [ $0 + 0 ], $1;", "r,r,b"(ptr addrspace(3) %148, float %123, i1 %140) #3, !dbg !10
+  %149 = shl nuw nsw i32 %17, 3, !dbg !10
+  %150 = or i32 %149, %11, !dbg !10
+  %151 = zext nneg i32 %150 to i64, !dbg !10
+  %152 = getelementptr float, ptr addrspace(3) @global_smem, i64 %151, !dbg !10
+  tail call void asm sideeffect "@$2 st.shared.b32 [ $0 + 0 ], $1;", "r,r,b"(ptr addrspace(3) %152, float %131, i1 %140) #3, !dbg !10
+  %153 = shl nuw nsw i32 %18, 3, !dbg !10
+  %154 = or i32 %153, %11, !dbg !10
+  %155 = zext nneg i32 %154 to i64, !dbg !10
+  %156 = getelementptr float, ptr addrspace(3) @global_smem, i64 %155, !dbg !10
+  tail call void asm sideeffect "@$2 st.shared.b32 [ $0 + 0 ], $1;", "r,r,b"(ptr addrspace(3) %156, float %139, i1 %140) #3, !dbg !10
+  tail call void @llvm.nvvm.barrier0(), !dbg !10
+  %157 = icmp slt i32 %6, 256, !dbg !10
+  %158 = sext i32 %6 to i64, !dbg !10
+  %159 = getelementptr float, ptr addrspace(3) @global_smem, i64 %158, !dbg !10
+  %160 = tail call float asm sideeffect "@$2 ld.shared.b32 $0, [ $1 + 0 ];", "=r,r,b"(ptr addrspace(3) %159, i1 %157) #3, !dbg !10
+  %161 = bitcast float %160 to i32, !dbg !10
+  %162 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %161, i32 4, i32 31), !dbg !10
+  %163 = bitcast i32 %162 to float, !dbg !10
+  %164 = fadd float %160, %163, !dbg !24
+  %165 = bitcast float %164 to i32, !dbg !10
+  %166 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %165, i32 2, i32 31), !dbg !10
+  %167 = bitcast i32 %166 to float, !dbg !10
+  %168 = fadd float %164, %167, !dbg !24
+  %169 = bitcast float %168 to i32, !dbg !10
+  %170 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %169, i32 1, i32 31), !dbg !10
+  %171 = bitcast i32 %170 to float, !dbg !10
+  %172 = fadd float %168, %171, !dbg !24
+  %173 = icmp eq i32 %9, 0, !dbg !10
+  %174 = and i1 %157, %173, !dbg !10
+  tail call void asm sideeffect "@$2 st.shared.b32 [ $0 + 0 ], $1;", "r,r,b"(ptr addrspace(3) %159, float %172, i1 %174) #3, !dbg !10
+  tail call void @llvm.nvvm.barrier0(), !dbg !10
+  %175 = zext nneg i32 %141 to i64, !dbg !10
+  %176 = getelementptr float, ptr addrspace(3) @global_smem, i64 %175, !dbg !10
+  %177 = load float, ptr addrspace(3) %176, align 4, !dbg !10
+  %178 = zext nneg i32 %145 to i64, !dbg !10
+  %179 = getelementptr float, ptr addrspace(3) @global_smem, i64 %178, !dbg !10
+  %180 = load float, ptr addrspace(3) %179, align 4, !dbg !10
+  %181 = zext nneg i32 %149 to i64, !dbg !10
+  %182 = getelementptr float, ptr addrspace(3) @global_smem, i64 %181, !dbg !10
+  %183 = load float, ptr addrspace(3) %182, align 4, !dbg !10
+  %184 = zext nneg i32 %153 to i64, !dbg !10
+  %185 = getelementptr float, ptr addrspace(3) @global_smem, i64 %184, !dbg !10
+  %186 = load float, ptr addrspace(3) %185, align 4, !dbg !10
+  tail call void @llvm.nvvm.barrier0(), !dbg !28
+  %187 = zext nneg i32 %10 to i64, !dbg !28
+  %188 = getelementptr float, ptr addrspace(3) @global_smem, i64 %187, !dbg !28
+  %189 = insertelement <1 x float> undef, float %177, i64 0, !dbg !28
+  store <1 x float> %189, ptr addrspace(3) %188, align 4, !dbg !28
+  %190 = zext nneg i32 %16 to i64, !dbg !28
+  %191 = getelementptr float, ptr addrspace(3) @global_smem, i64 %190, !dbg !28
+  %192 = insertelement <1 x float> undef, float %180, i64 0, !dbg !28
+  store <1 x float> %192, ptr addrspace(3) %191, align 4, !dbg !28
+  %193 = zext nneg i32 %17 to i64, !dbg !28
+  %194 = getelementptr float, ptr addrspace(3) @global_smem, i64 %193, !dbg !28
+  %195 = insertelement <1 x float> undef, float %183, i64 0, !dbg !28
+  store <1 x float> %195, ptr addrspace(3) %194, align 4, !dbg !28
+  %196 = zext nneg i32 %18 to i64, !dbg !28
+  %197 = getelementptr float, ptr addrspace(3) @global_smem, i64 %196, !dbg !28
+  %198 = insertelement <1 x float> undef, float %186, i64 0, !dbg !28
+  store <1 x float> %198, ptr addrspace(3) %197, align 4, !dbg !28
+  tail call void @llvm.nvvm.barrier0(), !dbg !28
+  %199 = zext nneg i32 %7 to i64, !dbg !28
+  %200 = getelementptr float, ptr addrspace(3) @global_smem, i64 %199, !dbg !28
+  %201 = load <1 x float>, ptr addrspace(3) %200, align 4, !dbg !28
+  %.frozen = freeze i32 %22
+  %202 = sdiv i32 %.frozen, 256, !dbg !29
+  %203 = mul i32 %202, 256
+  %.decomposed = sub i32 %.frozen, %203
+  %204 = sext i32 %202 to i64, !dbg !30
+  %205 = getelementptr i64, ptr addrspace(1) %1, i64 %204, !dbg !30
+  %206 = tail call i64 asm sideeffect "mov.u64 $0, 0x0;\0A\09@$2 ld.global.L1::evict_last.b64 { $0 }, [ $1 + 0 ];", "=l,l,b"(ptr addrspace(1) %205, i1 true) #3, !dbg !31
+  %207 = lshr i64 %206, 54, !dbg !32
+  %208 = and i64 %207, 512, !dbg !32
+  %209 = add i64 %208, %206, !dbg !32
+  %210 = shl i64 %209, 8, !dbg !33
+  %211 = sext i32 %.decomposed to i64, !dbg !34
+  %212 = getelementptr float, ptr addrspace(1) %2, i64 %210, !dbg !35
+  %213 = getelementptr float, ptr addrspace(1) %212, i64 %211, !dbg !35
+  %214 = icmp eq i32 %11, 0, !dbg !36
+  %215 = tail call float asm sideeffect "mov.u32 $0, 0x0;\0A\09@$3 atom.global.gpu.acq_rel.add.f32 $0, [ $1 + 0 ], $2;", "=r,l,r,b"(ptr addrspace(1) %213, <1 x float> %201, i1 %214) #3, !dbg !36
+  ret void, !dbg !37
+}
+
+; Function Attrs: mustprogress nocallback nofree nosync nounwind speculatable willreturn memory(none)
+declare noundef i32 @llvm.nvvm.read.ptx.sreg.tid.x() #0
+
+; Function Attrs: convergent nocallback nounwind memory(inaccessiblemem: readwrite)
+declare i32 @llvm.nvvm.shfl.sync.bfly.i32(i32, i32, i32, i32) #1
+
+; Function Attrs: convergent nocallback nounwind
+declare void @llvm.nvvm.barrier0() #2
+
+attributes #0 = { mustprogress nocallback nofree nosync nounwind speculatable willreturn memory(none) }
+attributes #1 = { convergent nocallback nounwind memory(inaccessiblemem: readwrite) }
+attributes #2 = { convergent nocallback nounwind }
+attributes #3 = { nounwind }
+
+!llvm.module.flags = !{!0}
+!llvm.dbg.cu = !{!1}
+!nvvm.annotations = !{!3, !4, !4, !3}
+
+!0 = !{i32 2, !"Debug Info Version", i32 3}
+!1 = distinct !DICompileUnit(language: DW_LANG_C, file: !2, producer: "triton", isOptimized: true, runtimeVersion: 0, emissionKind: FullDebug)
+!2 = !DIFile(filename: "c6ik5vx7p22fpk4dcvh55zimw4t5nr5zn2b7inujxjauxshljumm.py", directory: "/tmp/torchinductor_root/6i")
+!3 = !{ptr @triton__0d1d2d3de4e, !"kernel", i32 1}
+!4 = !{ptr @triton__0d1d2d3de4e, !"maxntidx", i32 256}
+!5 = distinct !DISubprogram(name: "triton__0d1d2d3de4e", linkageName: "triton__0d1d2d3de4e", scope: !2, file: !2, line: 18, type: !6, scopeLine: 18, spFlags: DISPFlagDefinition | DISPFlagOptimized, unit: !1)
+!6 = !DISubroutineType(cc: DW_CC_normal, types: !7)
+!7 = !{}
+!8 = !DILocation(line: 22, column: 44, scope: !5)
+!9 = !DILocation(line: 24, column: 33, scope: !5)
+!10 = !DILocation(line: 243, column: 36, scope: !11, inlinedAt: !13)
+!11 = distinct !DILexicalBlockFile(scope: !5, file: !12, discriminator: 0)
+!12 = !DIFile(filename: "standard.py", directory: "/usr/local/lib/python3.10/dist-packages/triton/language")
+!13 = !DILocation(line: 35, column: 25, scope: !11)
+!14 = !DILocation(line: 21, column: 28, scope: !5)
+!15 = !DILocation(line: 21, column: 33, scope: !5)
+!16 = !DILocation(line: 22, column: 23, scope: !5)
+!17 = !DILocation(line: 29, column: 25, scope: !5)
+!18 = !DILocation(line: 31, column: 47, scope: !5)
+!19 = !DILocation(line: 31, column: 40, scope: !5)
+!20 = !DILocation(line: 31, column: 34, scope: !5)
+!21 = !DILocation(line: 31, column: 53, scope: !5)
+!22 = !DILocation(line: 33, column: 23, scope: !5)
+!23 = !DILocation(line: 34, column: 38, scope: !5)
+!24 = !DILocation(line: 233, column: 15, scope: !25, inlinedAt: !26)
+!25 = distinct !DILexicalBlockFile(scope: !11, file: !12, discriminator: 0)
+!26 = !DILocation(line: 243, column: 36, scope: !25, inlinedAt: !27)
+!27 = !DILocation(line: 35, column: 25, scope: !25)
+!28 = !DILocation(line: 35, column: 28, scope: !5)
+!29 = !DILocation(line: 36, column: 20, scope: !5)
+!30 = !DILocation(line: 38, column: 30, scope: !5)
+!31 = !DILocation(line: 38, column: 35, scope: !5)
+!32 = !DILocation(line: 41, column: 32, scope: !5)
+!33 = !DILocation(line: 45, column: 40, scope: !5)
+!34 = !DILocation(line: 45, column: 36, scope: !5)
+!35 = !DILocation(line: 45, column: 30, scope: !5)
+!36 = !DILocation(line: 45, column: 55, scope: !5)
+!37 = !DILocation(line: 45, column: 4, scope: !5)

.triton/dump/127102ca642eeddf1a14ce3904d9fabf/triton_.ptx

@@ -0,0 +1,653 @@
+//
+// Generated by LLVM NVPTX Back-End
+//
+
+.version 8.2
+.target sm_89
+.address_size 64
+
+	// .globl	triton__0d1d2d3de4e
+.extern .shared .align 1 .b8 global_smem[];
+
+.visible .entry triton__0d1d2d3de4e(
+	.param .u64 triton__0d1d2d3de4e_param_0,
+	.param .u64 triton__0d1d2d3de4e_param_1,
+	.param .u64 triton__0d1d2d3de4e_param_2,
+	.param .u32 triton__0d1d2d3de4e_param_3,
+	.param .u32 triton__0d1d2d3de4e_param_4
+)
+.maxntid 256, 1, 1
+{
+	.reg .pred 	%p<30>;
+	.reg .b32 	%r<112>;
+	.reg .f32 	%f<76>;
+	.reg .b64 	%rd<22>;
+	.loc	1 18 0
+$L__func_begin0:
+	.loc	1 18 0
+
+	ld.param.u64 	%rd8, [triton__0d1d2d3de4e_param_0];
+	ld.param.u64 	%rd9, [triton__0d1d2d3de4e_param_1];
+$L__tmp0:
+	.loc	1 22 44
+	mov.u32 	%r48, %tid.x;
+	and.b32  	%r49, %r48, 31;
+	ld.param.u64 	%rd10, [triton__0d1d2d3de4e_param_2];
+	and.b32  	%r50, %r48, 7;
+	shl.b32 	%r51, %r50, 2;
+	.loc	1 24 33
+	bfe.u32 	%r52, %r48, 5, 3;
+	bfe.u32 	%r53, %r48, 3, 2;
+	shl.b32 	%r54, %r52, 2;
+	or.b32  	%r55, %r54, %r53;
+	or.b32  	%r56, %r55, 96;
+	.loc	1 21 28
+	mov.u32 %r1, %ctaid.x;
+	.loc	1 21 33
+	shl.b32 	%r57, %r1, 5;
+	.loc	1 22 23
+	or.b32  	%r58, %r57, %r51;
+	or.b32  	%r59, %r57, %r49;
+	.loc	1 29 25
+	setp.lt.u32 	%p16, %r56, 120;
+	.loc	1 31 47
+	shl.b32 	%r60, %r55, 17;
+	shl.b32 	%r61, %r56, 17;
+	.loc	1 31 40
+	add.s32 	%r62, %r58, %r60;
+	add.s32 	%r63, %r62, 4194304;
+	add.s32 	%r64, %r62, 8388608;
+	add.s32 	%r65, %r58, %r61;
+	.loc	1 31 34
+	mul.wide.s32 	%rd11, %r62, 4;
+	add.s64 	%rd1, %rd8, %rd11;
+	mul.wide.s32 	%rd12, %r63, 4;
+	add.s64 	%rd2, %rd8, %rd12;
+	mul.wide.s32 	%rd13, %r64, 4;
+	add.s64 	%rd3, %rd8, %rd13;
+	mul.wide.s32 	%rd14, %r65, 4;
+	add.s64 	%rd4, %rd8, %rd14;
+	mov.b32 	%r6, 0;
+	mov.pred 	%p1, -1;
+	.loc	1 31 53
+	mov.u32 %r2, 0x0;
+	mov.u32 %r3, 0x0;
+	mov.u32 %r4, 0x0;
+	mov.u32 %r5, 0x0;
+	@%p1 ld.global.L1::evict_first.v4.b32 { %r2, %r3, %r4, %r5 }, [ %rd1 + 0 ];
+	@!%p1 mov.u32 %r2, %r6;
+	@!%p1 mov.u32 %r3, %r6;
+	@!%p1 mov.u32 %r4, %r6;
+	@!%p1 mov.u32 %r5, %r6;
+	mov.b32 	%f1, %r2;
+	mov.b32 	%f2, %r3;
+	mov.b32 	%f3, %r4;
+	mov.b32 	%f4, %r5;
+	mov.u32 %r10, 0x0;
+	mov.u32 %r11, 0x0;
+	mov.u32 %r12, 0x0;
+	mov.u32 %r13, 0x0;
+	@%p1 ld.global.L1::evict_first.v4.b32 { %r10, %r11, %r12, %r13 }, [ %rd2 + 0 ];
+	@!%p1 mov.u32 %r10, %r6;
+	@!%p1 mov.u32 %r11, %r6;
+	@!%p1 mov.u32 %r12, %r6;
+	@!%p1 mov.u32 %r13, %r6;
+	mov.b32 	%f5, %r10;
+	mov.b32 	%f6, %r11;
+	mov.b32 	%f7, %r12;
+	mov.b32 	%f8, %r13;
+	mov.u32 %r18, 0x0;
+	mov.u32 %r19, 0x0;
+	mov.u32 %r20, 0x0;
+	mov.u32 %r21, 0x0;
+	@%p1 ld.global.L1::evict_first.v4.b32 { %r18, %r19, %r20, %r21 }, [ %rd3 + 0 ];
+	@!%p1 mov.u32 %r18, %r6;
+	@!%p1 mov.u32 %r19, %r6;
+	@!%p1 mov.u32 %r20, %r6;
+	@!%p1 mov.u32 %r21, %r6;
+	mov.b32 	%f9, %r18;
+	mov.b32 	%f10, %r19;
+	mov.b32 	%f11, %r20;
+	mov.b32 	%f12, %r21;
+	mov.u32 %r26, 0x0;
+	mov.u32 %r27, 0x0;
+	mov.u32 %r28, 0x0;
+	mov.u32 %r29, 0x0;
+	@%p16 ld.global.L1::evict_first.v4.b32 { %r26, %r27, %r28, %r29 }, [ %rd4 + 0 ];
+	@!%p16 mov.u32 %r26, %r6;
+	@!%p16 mov.u32 %r27, %r6;
+	@!%p16 mov.u32 %r28, %r6;
+	@!%p16 mov.u32 %r29, %r6;
+	mov.b32 	%f13, %r26;
+	mov.b32 	%f14, %r27;
+	mov.b32 	%f15, %r28;
+	mov.b32 	%f16, %r29;
+	.loc	1 33 23
+	add.f32 	%f17, %f1, 0f00000000;
+	add.f32 	%f18, %f2, 0f00000000;
+	add.f32 	%f19, %f3, 0f00000000;
+	add.f32 	%f20, %f4, 0f00000000;
+	add.f32 	%f21, %f5, 0f00000000;
+	add.f32 	%f22, %f6, 0f00000000;
+	add.f32 	%f23, %f7, 0f00000000;
+	add.f32 	%f24, %f8, 0f00000000;
+	add.f32 	%f25, %f9, 0f00000000;
+	add.f32 	%f26, %f10, 0f00000000;
+	add.f32 	%f27, %f11, 0f00000000;
+	add.f32 	%f28, %f12, 0f00000000;
+	add.f32 	%f29, %f13, 0f00000000;
+	add.f32 	%f30, %f14, 0f00000000;
+	add.f32 	%f31, %f15, 0f00000000;
+	add.f32 	%f32, %f16, 0f00000000;
+	.loc	1 34 38
+	selp.f32 	%f33, %f29, 0f00000000, %p16;
+	selp.f32 	%f34, %f30, 0f00000000, %p16;
+	selp.f32 	%f35, %f31, 0f00000000, %p16;
+	selp.f32 	%f36, %f32, 0f00000000, %p16;
+$L__tmp1:
+	.loc	2 233 15
+	add.f32 	%f37, %f17, %f21;
+	add.f32 	%f38, %f18, %f22;
+	add.f32 	%f39, %f19, %f23;
+	add.f32 	%f40, %f20, %f24;
+	add.f32 	%f41, %f37, %f25;
+	add.f32 	%f42, %f38, %f26;
+	add.f32 	%f43, %f39, %f27;
+	add.f32 	%f44, %f40, %f28;
+	add.f32 	%f45, %f41, %f33;
+	add.f32 	%f46, %f42, %f34;
+	add.f32 	%f47, %f43, %f35;
+	add.f32 	%f48, %f44, %f36;
+$L__tmp2:
+	.loc	2 243 36
+	mov.b32 	%r66, %f45;
+	shfl.sync.bfly.b32	%r67, %r66, 16, 31, -1;
+	mov.b32 	%f49, %r67;
+$L__tmp3:
+	.loc	2 233 15
+	add.f32 	%f50, %f45, %f49;
+$L__tmp4:
+	.loc	2 243 36
+	mov.b32 	%r68, %f50;
+	shfl.sync.bfly.b32	%r69, %r68, 8, 31, -1;
+	mov.b32 	%f51, %r69;
+$L__tmp5:
+	.loc	2 233 15
+	add.f32 	%f52, %f50, %f51;
+$L__tmp6:
+	.loc	2 243 36
+	mov.b32 	%r70, %f46;
+	shfl.sync.bfly.b32	%r71, %r70, 16, 31, -1;
+	mov.b32 	%f53, %r71;
+$L__tmp7:
+	.loc	2 233 15
+	add.f32 	%f54, %f46, %f53;
+$L__tmp8:
+	.loc	2 243 36
+	mov.b32 	%r72, %f54;
+	shfl.sync.bfly.b32	%r73, %r72, 8, 31, -1;
+	mov.b32 	%f55, %r73;
+$L__tmp9:
+	.loc	2 233 15
+	add.f32 	%f56, %f54, %f55;
+$L__tmp10:
+	.loc	2 243 36
+	mov.b32 	%r74, %f47;
+	shfl.sync.bfly.b32	%r75, %r74, 16, 31, -1;
+	mov.b32 	%f57, %r75;
+$L__tmp11:
+	.loc	2 233 15
+	add.f32 	%f58, %f47, %f57;
+$L__tmp12:
+	.loc	2 243 36
+	mov.b32 	%r76, %f58;
+	shfl.sync.bfly.b32	%r77, %r76, 8, 31, -1;
+	mov.b32 	%f59, %r77;
+$L__tmp13:
+	.loc	2 233 15
+	add.f32 	%f60, %f58, %f59;
+$L__tmp14:
+	.loc	2 243 36
+	mov.b32 	%r78, %f48;
+	shfl.sync.bfly.b32	%r79, %r78, 16, 31, -1;
+	mov.b32 	%f61, %r79;
+$L__tmp15:
+	.loc	2 233 15
+	add.f32 	%f62, %f48, %f61;
+$L__tmp16:
+	.loc	2 243 36
+	mov.b32 	%r80, %f62;
+	shfl.sync.bfly.b32	%r81, %r80, 8, 31, -1;
+	mov.b32 	%f63, %r81;
+$L__tmp17:
+	.loc	2 233 15
+	add.f32 	%f64, %f62, %f63;
+$L__tmp18:
+	.loc	2 243 36
+	setp.lt.u32 	%p21, %r49, 8;
+	shl.b32 	%r82, %r50, 7;
+	or.b32  	%r83, %r82, %r54;
+	mov.u32 	%r84, global_smem;
+	add.s32 	%r34, %r84, %r83;
+	mov.b32 	%r35, %f52;
+	@%p21 st.shared.b32 [ %r34 + 0 ], %r35;
+	or.b32  	%r85, %r82, 32;
+	or.b32  	%r86, %r85, %r54;
+	add.s32 	%r36, %r84, %r86;
+	mov.b32 	%r37, %f56;
+	@%p21 st.shared.b32 [ %r36 + 0 ], %r37;
+	or.b32  	%r87, %r82, 64;
+	or.b32  	%r88, %r87, %r54;
+	add.s32 	%r38, %r84, %r88;
+	mov.b32 	%r39, %f60;
+	@%p21 st.shared.b32 [ %r38 + 0 ], %r39;
+	or.b32  	%r89, %r82, 96;
+	or.b32  	%r90, %r89, %r54;
+	add.s32 	%r40, %r84, %r90;
+	mov.b32 	%r41, %f64;
+	@%p21 st.shared.b32 [ %r40 + 0 ], %r41;
+	bar.sync 	0;
+	setp.lt.s32 	%p25, %r48, 256;
+	shl.b32 	%r91, %r48, 2;
+	add.s32 	%r43, %r84, %r91;
+	@%p25 ld.shared.b32 %r42, [ %r43 + 0 ];
+	mov.b32 	%f65, %r42;
+	shfl.sync.bfly.b32	%r92, %r42, 4, 31, -1;
+	mov.b32 	%f66, %r92;
+$L__tmp19:
+	.loc	2 233 15
+	add.f32 	%f67, %f65, %f66;
+$L__tmp20:
+	.loc	2 243 36
+	mov.b32 	%r93, %f67;
+	shfl.sync.bfly.b32	%r94, %r93, 2, 31, -1;
+	mov.b32 	%f68, %r94;
+$L__tmp21:
+	.loc	2 233 15
+	add.f32 	%f69, %f67, %f68;
+$L__tmp22:
+	.loc	2 243 36
+	mov.b32 	%r95, %f69;
+	shfl.sync.bfly.b32	%r96, %r95, 1, 31, -1;
+	mov.b32 	%f70, %r96;
+$L__tmp23:
+	.loc	2 233 15
+	add.f32 	%f71, %f69, %f70;
+$L__tmp24:
+	.loc	2 243 36
+	setp.eq.s32 	%p29, %r50, 0;
+	and.pred  	%p26, %p25, %p29;
+	mov.b32 	%r45, %f71;
+	@%p26 st.shared.b32 [ %r43 + 0 ], %r45;
+	bar.sync 	0;
+	add.s32 	%r97, %r84, %r82;
+	ld.shared.f32 	%f72, [%r97];
+	add.s32 	%r98, %r84, %r85;
+	ld.shared.f32 	%f73, [%r98];
+	add.s32 	%r99, %r84, %r87;
+	ld.shared.f32 	%f74, [%r99];
+	add.s32 	%r100, %r84, %r89;
+	ld.shared.f32 	%f75, [%r100];
+$L__tmp25:
+	.loc	1 35 28
+	bar.sync 	0;
+	shl.b32 	%r101, %r50, 4;
+	add.s32 	%r102, %r84, %r101;
+	st.shared.f32 	[%r102], %f72;
+	st.shared.f32 	[%r102+4], %f73;
+	st.shared.f32 	[%r102+8], %f74;
+	st.shared.f32 	[%r102+12], %f75;
+	bar.sync 	0;
+	shl.b32 	%r103, %r49, 2;
+	add.s32 	%r104, %r84, %r103;
+	.loc	1 36 20
+	shr.s32 	%r106, %r59, 31;
+	shr.u32 	%r107, %r106, 24;
+	add.s32 	%r108, %r59, %r107;
+	shr.s32 	%r109, %r108, 8;
+	and.b32  	%r110, %r108, -256;
+	sub.s32 	%r111, %r59, %r110;
+	.loc	1 38 30
+	mul.wide.s32 	%rd15, %r109, 8;
+	add.s64 	%rd6, %rd9, %rd15;
+	.loc	1 45 55
+	ld.shared.u32 	%r47, [%r104];
+	.loc	1 38 35
+	mov.u64 %rd5, 0x0;
+	@%p1 ld.global.L1::evict_last.b64 { %rd5 }, [ %rd6 + 0 ];
+	.loc	1 41 32
+	shr.u64 	%rd16, %rd5, 54;
+	and.b64  	%rd17, %rd16, 512;
+	add.s64 	%rd18, %rd17, %rd5;
+	.loc	1 45 30
+	shl.b64 	%rd19, %rd18, 10;
+	add.s64 	%rd20, %rd10, %rd19;
+	mul.wide.s32 	%rd21, %r111, 4;
+	add.s64 	%rd7, %rd20, %rd21;
+	.loc	1 45 55
+	setp.eq.s32 	%p28, %r52, 0;
+	mov.u32 %r46, 0x0;
+	@%p28 atom.global.gpu.acq_rel.add.f32 %r46, [ %rd7 + 0 ], %r47;
+	.loc	1 45 4
+	ret;
+$L__tmp26:
+$L__func_end0:
+
+}
+	.file	1 "/tmp/torchinductor_root/6i/c6ik5vx7p22fpk4dcvh55zimw4t5nr5zn2b7inujxjauxshljumm.py"
+	.file	2 "/usr/local/lib/python3.10/dist-packages/triton/language/standard.py"
+	.section	.debug_abbrev
+	{
+.b8 1
+.b8 17
+.b8 1
+.b8 37
+.b8 8
+.b8 19
+.b8 5
+.b8 3
+.b8 8
+.b8 16
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+.b8 27
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+.b8 0
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+.b8 4
+.b8 29
+.b8 1
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+.b8 0
+.b8 0
+.b8 5
+.b8 29
+.b8 0
+.b8 49
+.b8 19
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+.b8 1
+.b8 18
+.b8 1
+.b8 88
+.b8 11
+.b8 89
+.b8 11
+.b8 87
+.b8 11
+.b8 0
+.b8 0
+.b8 0
+	}
+	.section	.debug_info
+	{
+.b32 264
+.b8 2
+.b8 0
+.b32 .debug_abbrev
+.b8 8
+.b8 1
+.b8 116
+.b8 114
+.b8 105
+.b8 116
+.b8 111
+.b8 110
+.b8 0
+.b8 2
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+.b8 117
+.b8 109
+.b8 109
+.b8 46
+.b8 112
+.b8 121
+.b8 0
+.b32 .debug_line
+.b8 47
+.b8 116
+.b8 109
+.b8 112
+.b8 47
+.b8 116
+.b8 111
+.b8 114
+.b8 99
+.b8 104
+.b8 105
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+.b8 100
+.b8 117
+.b8 99
+.b8 116
+.b8 111
+.b8 114
+.b8 95
+.b8 114
+.b8 111
+.b8 111
+.b8 116
+.b8 47
+.b8 54
+.b8 105
+.b8 0
+.b8 1
+.b64 $L__func_begin0
+.b64 $L__func_end0
+.b8 2
+.b8 116
+.b8 114
+.b8 105
+.b8 116
+.b8 111
+.b8 110
+.b8 95
+.b8 95
+.b8 48
+.b8 100
+.b8 49
+.b8 100
+.b8 50
+.b8 100
+.b8 51
+.b8 100
+.b8 101
+.b8 52
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+.b8 0
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+.b8 114
+.b8 105
+.b8 116
+.b8 111
+.b8 110
+.b8 95
+.b8 95
+.b8 48
+.b8 100
+.b8 49
+.b8 100
+.b8 50
+.b8 100
+.b8 51
+.b8 100
+.b8 101
+.b8 52
+.b8 101
+.b8 0
+.b8 1
+.b8 18
+.b8 1
+.b8 1
+.b8 3
+.b64 $L__func_begin0
+.b64 $L__func_end0
+.b8 1
+.b8 156
+.b32 125
+.b8 4
+.b32 125
+.b64 $L__tmp1
+.b64 $L__tmp24
+.b8 2
+.b8 35
+.b8 25
+.b8 5
+.b32 125
+.b64 $L__tmp1
+.b64 $L__tmp24
+.b8 2
+.b8 243
+.b8 36
+.b8 0
+.b8 5
+.b32 125
+.b64 $L__tmp2
+.b64 $L__tmp25
+.b8 2
+.b8 35
+.b8 25
+.b8 0
+.b8 0
+	}
+	.section	.debug_pubnames
+	{
+.b32 $L__pubNames_end0-$L__pubNames_start0
+$L__pubNames_start0:
+.b8 2
+.b8 0
+.b32 .debug_info
+.b32 268
+.b32 125
+.b8 116
+.b8 114
+.b8 105
+.b8 116
+.b8 111
+.b8 110
+.b8 95
+.b8 95
+.b8 48
+.b8 100
+.b8 49
+.b8 100
+.b8 50
+.b8 100
+.b8 51
+.b8 100
+.b8 101
+.b8 52
+.b8 101
+.b8 0
+.b32 0
+$L__pubNames_end0:
+	}
+	.section	.debug_pubtypes
+	{
+.b32 $L__pubTypes_end0-$L__pubTypes_start0
+$L__pubTypes_start0:
+.b8 2
+.b8 0
+.b32 .debug_info
+.b32 268
+.b32 0
+$L__pubTypes_end0:
+	}
+	.section	.debug_loc	{	}

.triton/dump/127102ca642eeddf1a14ce3904d9fabf/triton_.ttgir

@@ -0,0 +1,60 @@
+#blocked = #triton_gpu.blocked<{sizePerThread = [1, 1], threadsPerWarp = [32, 1], warpsPerCTA = [1, 8], order = [0, 1], CTAsPerCGA = [1, 1], CTASplitNum = [1, 1], CTAOrder = [1, 0]}>
+#blocked1 = #triton_gpu.blocked<{sizePerThread = [4, 1], threadsPerWarp = [8, 4], warpsPerCTA = [1, 8], order = [0, 1], CTAsPerCGA = [1, 1], CTASplitNum = [1, 1], CTAOrder = [1, 0]}>
+module attributes {"triton_gpu.compute-capability" = 89 : i32, "triton_gpu.num-ctas" = 1 : i32, "triton_gpu.num-warps" = 8 : i32, "triton_gpu.threads-per-warp" = 32 : i32} {
+  tt.func public @triton__0d1d2d3de4e(%arg0: !tt.ptr<f32, 1> {tt.divisibility = 16 : i32}, %arg1: !tt.ptr<i64, 1> {tt.divisibility = 16 : i32}, %arg2: !tt.ptr<f32, 1> {tt.divisibility = 16 : i32}, %arg3: i32 {tt.divisibility = 16 : i32, tt.max_divisibility = 16 : i32}, %arg4: i32 {tt.max_divisibility = 8 : i32}) attributes {noinline = false} {
+    %cst = arith.constant dense<256> : tensor<32x1xi64, #blocked>
+    %cst_0 = arith.constant dense<0> : tensor<32x1xi64, #blocked>
+    %cst_1 = arith.constant dense<512> : tensor<32x1xi64, #blocked>
+    %cst_2 = arith.constant dense<256> : tensor<32x1xi32, #blocked>
+    %cst_3 = arith.constant dense<131072> : tensor<1x128xi32, #blocked1>
+    %cst_4 = arith.constant dense<120> : tensor<1x128xi32, #blocked1>
+    %cst_5 = arith.constant dense<0.000000e+00> : tensor<32x128xf32, #blocked1>
+    %cst_6 = arith.constant dense<true> : tensor<32x1xi1, #blocked>
+    %c32_i32 = arith.constant 32 : i32
+    %0 = tt.get_program_id x : i32
+    %1 = arith.muli %0, %c32_i32 : i32
+    %2 = tt.make_range {end = 32 : i32, start = 0 : i32} : tensor<32xi32, #triton_gpu.slice<{dim = 1, parent = #blocked1}>>
+    %3 = tt.make_range {end = 32 : i32, start = 0 : i32} : tensor<32xi32, #triton_gpu.slice<{dim = 1, parent = #blocked}>>
+    %4 = tt.expand_dims %2 {axis = 1 : i32} : (tensor<32xi32, #triton_gpu.slice<{dim = 1, parent = #blocked1}>>) -> tensor<32x1xi32, #blocked1>
+    %5 = tt.expand_dims %3 {axis = 1 : i32} : (tensor<32xi32, #triton_gpu.slice<{dim = 1, parent = #blocked}>>) -> tensor<32x1xi32, #blocked>
+    %6 = tt.splat %1 : (i32) -> tensor<32x1xi32, #blocked1>
+    %7 = tt.splat %1 : (i32) -> tensor<32x1xi32, #blocked>
+    %8 = arith.addi %6, %4 : tensor<32x1xi32, #blocked1>
+    %9 = arith.addi %7, %5 : tensor<32x1xi32, #blocked>
+    %10 = tt.make_range {end = 128 : i32, start = 0 : i32} : tensor<128xi32, #triton_gpu.slice<{dim = 0, parent = #blocked1}>>
+    %11 = tt.expand_dims %10 {axis = 0 : i32} : (tensor<128xi32, #triton_gpu.slice<{dim = 0, parent = #blocked1}>>) -> tensor<1x128xi32, #blocked1>
+    %12 = arith.cmpi slt, %11, %cst_4 : tensor<1x128xi32, #blocked1>
+    %13 = arith.muli %11, %cst_3 : tensor<1x128xi32, #blocked1>
+    %14 = tt.broadcast %8 : (tensor<32x1xi32, #blocked1>) -> tensor<32x128xi32, #blocked1>
+    %15 = tt.broadcast %13 : (tensor<1x128xi32, #blocked1>) -> tensor<32x128xi32, #blocked1>
+    %16 = arith.addi %14, %15 : tensor<32x128xi32, #blocked1>
+    %17 = tt.splat %arg0 : (!tt.ptr<f32, 1>) -> tensor<32x128x!tt.ptr<f32, 1>, #blocked1>
+    %18 = tt.addptr %17, %16 : tensor<32x128x!tt.ptr<f32, 1>, #blocked1>, tensor<32x128xi32, #blocked1>
+    %19 = tt.broadcast %12 : (tensor<1x128xi1, #blocked1>) -> tensor<32x128xi1, #blocked1>
+    %20 = tt.load %18, %19, %cst_5 {cache = 1 : i32, evict = 2 : i32, isVolatile = false} : tensor<32x128xf32, #blocked1>
+    %21 = arith.addf %20, %cst_5 : tensor<32x128xf32, #blocked1>
+    %22 = arith.select %19, %21, %cst_5 : tensor<32x128xi1, #blocked1>, tensor<32x128xf32, #blocked1>
+    %23 = "tt.reduce"(%22) <{axis = 1 : i32}> ({
+    ^bb0(%arg5: f32, %arg6: f32):
+      %40 = arith.addf %arg5, %arg6 : f32
+      tt.reduce.return %40 : f32
+    }) : (tensor<32x128xf32, #blocked1>) -> tensor<32xf32, #triton_gpu.slice<{dim = 1, parent = #blocked1}>>
+    %24 = triton_gpu.convert_layout %23 : (tensor<32xf32, #triton_gpu.slice<{dim = 1, parent = #blocked1}>>) -> tensor<32xf32, #triton_gpu.slice<{dim = 1, parent = #blocked}>>
+    %25 = tt.expand_dims %24 {axis = 1 : i32} : (tensor<32xf32, #triton_gpu.slice<{dim = 1, parent = #blocked}>>) -> tensor<32x1xf32, #blocked>
+    %26 = arith.divsi %9, %cst_2 : tensor<32x1xi32, #blocked>
+    %27 = arith.remsi %9, %cst_2 : tensor<32x1xi32, #blocked>
+    %28 = tt.splat %arg1 : (!tt.ptr<i64, 1>) -> tensor<32x1x!tt.ptr<i64, 1>, #blocked>
+    %29 = tt.addptr %28, %26 : tensor<32x1x!tt.ptr<i64, 1>, #blocked>, tensor<32x1xi32, #blocked>
+    %30 = tt.load %29 {cache = 1 : i32, evict = 3 : i32, isVolatile = false} : tensor<32x1xi64, #blocked>
+    %31 = arith.addi %30, %cst_1 : tensor<32x1xi64, #blocked>
+    %32 = arith.cmpi slt, %30, %cst_0 : tensor<32x1xi64, #blocked>
+    %33 = arith.select %32, %31, %30 : tensor<32x1xi1, #blocked>, tensor<32x1xi64, #blocked>
+    %34 = arith.muli %33, %cst : tensor<32x1xi64, #blocked>
+    %35 = arith.extsi %27 : tensor<32x1xi32, #blocked> to tensor<32x1xi64, #blocked>
+    %36 = arith.addi %35, %34 : tensor<32x1xi64, #blocked>
+    %37 = tt.splat %arg2 : (!tt.ptr<f32, 1>) -> tensor<32x1x!tt.ptr<f32, 1>, #blocked>
+    %38 = tt.addptr %37, %36 : tensor<32x1x!tt.ptr<f32, 1>, #blocked>, tensor<32x1xi64, #blocked>
+    %39 = "tt.atomic_rmw"(%38, %25, %cst_6) <{atomic_rmw_op = 5 : i32, scope = 1 : i32, sem = 4 : i32}> : (tensor<32x1x!tt.ptr<f32, 1>, #blocked>, tensor<32x1xf32, #blocked>, tensor<32x1xi1, #blocked>) -> tensor<32x1xf32, #blocked>
+    tt.return
+  }
+}

.triton/dump/127102ca642eeddf1a14ce3904d9fabf/triton_.ttir

@@ -0,0 +1,53 @@
+module {
+  tt.func public @triton__0d1d2d3de4e(%arg0: !tt.ptr<f32, 1> {tt.divisibility = 16 : i32}, %arg1: !tt.ptr<i64, 1> {tt.divisibility = 16 : i32}, %arg2: !tt.ptr<f32, 1> {tt.divisibility = 16 : i32}, %arg3: i32 {tt.divisibility = 16 : i32, tt.max_divisibility = 16 : i32}, %arg4: i32 {tt.max_divisibility = 8 : i32}) attributes {noinline = false} {
+    %cst = arith.constant dense<256> : tensor<32x1xi64>
+    %cst_0 = arith.constant dense<0> : tensor<32x1xi64>
+    %cst_1 = arith.constant dense<512> : tensor<32x1xi64>
+    %cst_2 = arith.constant dense<true> : tensor<32x1xi1>
+    %cst_3 = arith.constant dense<256> : tensor<32x1xi32>
+    %cst_4 = arith.constant dense<131072> : tensor<1x128xi32>
+    %cst_5 = arith.constant dense<120> : tensor<1x128xi32>
+    %cst_6 = arith.constant dense<0.000000e+00> : tensor<32x128xf32>
+    %c32_i32 = arith.constant 32 : i32
+    %0 = tt.get_program_id x : i32
+    %1 = arith.muli %0, %c32_i32 : i32
+    %2 = tt.make_range {end = 32 : i32, start = 0 : i32} : tensor<32xi32>
+    %3 = tt.expand_dims %2 {axis = 1 : i32} : (tensor<32xi32>) -> tensor<32x1xi32>
+    %4 = tt.splat %1 : (i32) -> tensor<32x1xi32>
+    %5 = arith.addi %4, %3 : tensor<32x1xi32>
+    %6 = tt.make_range {end = 128 : i32, start = 0 : i32} : tensor<128xi32>
+    %7 = tt.expand_dims %6 {axis = 0 : i32} : (tensor<128xi32>) -> tensor<1x128xi32>
+    %8 = arith.cmpi slt, %7, %cst_5 : tensor<1x128xi32>
+    %9 = arith.muli %7, %cst_4 : tensor<1x128xi32>
+    %10 = tt.broadcast %5 : (tensor<32x1xi32>) -> tensor<32x128xi32>
+    %11 = tt.broadcast %9 : (tensor<1x128xi32>) -> tensor<32x128xi32>
+    %12 = arith.addi %10, %11 : tensor<32x128xi32>
+    %13 = tt.splat %arg0 : (!tt.ptr<f32, 1>) -> tensor<32x128x!tt.ptr<f32, 1>>
+    %14 = tt.addptr %13, %12 : tensor<32x128x!tt.ptr<f32, 1>>, tensor<32x128xi32>
+    %15 = tt.broadcast %8 : (tensor<1x128xi1>) -> tensor<32x128xi1>
+    %16 = tt.load %14, %15, %cst_6 {cache = 1 : i32, evict = 2 : i32, isVolatile = false} : tensor<32x128xf32>
+    %17 = arith.addf %16, %cst_6 : tensor<32x128xf32>
+    %18 = arith.select %15, %17, %cst_6 : tensor<32x128xi1>, tensor<32x128xf32>
+    %19 = "tt.reduce"(%18) <{axis = 1 : i32}> ({
+    ^bb0(%arg5: f32, %arg6: f32):
+      %35 = arith.addf %arg5, %arg6 : f32
+      tt.reduce.return %35 : f32
+    }) : (tensor<32x128xf32>) -> tensor<32xf32>
+    %20 = tt.expand_dims %19 {axis = 1 : i32} : (tensor<32xf32>) -> tensor<32x1xf32>
+    %21 = arith.divsi %5, %cst_3 : tensor<32x1xi32>
+    %22 = arith.remsi %5, %cst_3 : tensor<32x1xi32>
+    %23 = tt.splat %arg1 : (!tt.ptr<i64, 1>) -> tensor<32x1x!tt.ptr<i64, 1>>
+    %24 = tt.addptr %23, %21 : tensor<32x1x!tt.ptr<i64, 1>>, tensor<32x1xi32>
+    %25 = tt.load %24 {cache = 1 : i32, evict = 3 : i32, isVolatile = false} : tensor<32x1xi64>
+    %26 = arith.addi %25, %cst_1 : tensor<32x1xi64>
+    %27 = arith.cmpi slt, %25, %cst_0 : tensor<32x1xi64>
+    %28 = arith.select %27, %26, %25 : tensor<32x1xi1>, tensor<32x1xi64>
+    %29 = arith.muli %28, %cst : tensor<32x1xi64>
+    %30 = arith.extsi %22 : tensor<32x1xi32> to tensor<32x1xi64>
+    %31 = arith.addi %30, %29 : tensor<32x1xi64>
+    %32 = tt.splat %arg2 : (!tt.ptr<f32, 1>) -> tensor<32x1x!tt.ptr<f32, 1>>
+    %33 = tt.addptr %32, %31 : tensor<32x1x!tt.ptr<f32, 1>>, tensor<32x1xi64>
+    %34 = "tt.atomic_rmw"(%33, %20, %cst_2) <{atomic_rmw_op = 5 : i32, scope = 1 : i32, sem = 4 : i32}> : (tensor<32x1x!tt.ptr<f32, 1>>, tensor<32x1xf32>, tensor<32x1xi1>) -> tensor<32x1xf32>
+    tt.return
+  }
+}

.triton/dump/15fa39c568de5a2b912a7bda93a479b3/triton_.ttgir

@@ -0,0 +1,24 @@
+#blocked = #triton_gpu.blocked<{sizePerThread = [8], threadsPerWarp = [32], warpsPerCTA = [4], order = [0], CTAsPerCGA = [1], CTASplitNum = [1], CTAOrder = [0]}>
+#blocked1 = #triton_gpu.blocked<{sizePerThread = [4], threadsPerWarp = [32], warpsPerCTA = [4], order = [0], CTAsPerCGA = [1], CTASplitNum = [1], CTAOrder = [0]}>
+module attributes {"triton_gpu.compute-capability" = 89 : i32, "triton_gpu.num-ctas" = 1 : i32, "triton_gpu.num-warps" = 4 : i32, "triton_gpu.threads-per-warp" = 32 : i32} {
+  tt.func public @triton__0d1d2de(%arg0: !tt.ptr<bf16, 1> {tt.divisibility = 16 : i32}, %arg1: !tt.ptr<f32, 1> {tt.divisibility = 16 : i32}, %arg2: i32 {tt.divisibility = 16 : i32, tt.max_divisibility = 16 : i32}) attributes {noinline = false} {
+    %c1024_i32 = arith.constant 1024 : i32
+    %0 = tt.get_program_id x : i32
+    %1 = arith.muli %0, %c1024_i32 : i32
+    %2 = tt.make_range {end = 1024 : i32, start = 0 : i32} : tensor<1024xi32, #blocked>
+    %3 = tt.make_range {end = 1024 : i32, start = 0 : i32} : tensor<1024xi32, #blocked1>
+    %4 = tt.splat %1 : (i32) -> tensor<1024xi32, #blocked>
+    %5 = tt.splat %1 : (i32) -> tensor<1024xi32, #blocked1>
+    %6 = arith.addi %4, %2 : tensor<1024xi32, #blocked>
+    %7 = arith.addi %5, %3 : tensor<1024xi32, #blocked1>
+    %8 = tt.splat %arg0 : (!tt.ptr<bf16, 1>) -> tensor<1024x!tt.ptr<bf16, 1>, #blocked>
+    %9 = tt.addptr %8, %6 : tensor<1024x!tt.ptr<bf16, 1>, #blocked>, tensor<1024xi32, #blocked>
+    %10 = tt.load %9 {cache = 1 : i32, evict = 1 : i32, isVolatile = false} : tensor<1024xbf16, #blocked>
+    %11 = triton_gpu.convert_layout %10 : (tensor<1024xbf16, #blocked>) -> tensor<1024xbf16, #blocked1>
+    %12 = arith.extf %11 : tensor<1024xbf16, #blocked1> to tensor<1024xf32, #blocked1>
+    %13 = tt.splat %arg1 : (!tt.ptr<f32, 1>) -> tensor<1024x!tt.ptr<f32, 1>, #blocked1>
+    %14 = tt.addptr %13, %7 : tensor<1024x!tt.ptr<f32, 1>, #blocked1>, tensor<1024xi32, #blocked1>
+    tt.store %14, %12 {cache = 1 : i32, evict = 1 : i32} : tensor<1024xf32, #blocked1>
+    tt.return
+  }
+}

.triton/dump/1c188b233fcb854770e6a3cf1802c844/triton_.ttgir

@@ -0,0 +1,63 @@
+#blocked = #triton_gpu.blocked<{sizePerThread = [4, 1], threadsPerWarp = [16, 2], warpsPerCTA = [1, 4], order = [0, 1], CTAsPerCGA = [1, 1], CTASplitNum = [1, 1], CTAOrder = [1, 0]}>
+#blocked1 = #triton_gpu.blocked<{sizePerThread = [1, 1], threadsPerWarp = [32, 1], warpsPerCTA = [2, 2], order = [0, 1], CTAsPerCGA = [1, 1], CTASplitNum = [1, 1], CTAOrder = [1, 0]}>
+module attributes {"triton_gpu.compute-capability" = 89 : i32, "triton_gpu.num-ctas" = 1 : i32, "triton_gpu.num-warps" = 4 : i32, "triton_gpu.threads-per-warp" = 32 : i32} {
+  tt.func public @triton__0d1d2d3de4de(%arg0: !tt.ptr<f32, 1> {tt.divisibility = 16 : i32}, %arg1: !tt.ptr<f32, 1> {tt.divisibility = 16 : i32}, %arg2: !tt.ptr<f32, 1> {tt.divisibility = 16 : i32}, %arg3: i32 {tt.divisibility = 16 : i32, tt.max_divisibility = 16 : i32}, %arg4: i32 {tt.divisibility = 16 : i32, tt.max_divisibility = 16 : i32}) attributes {noinline = false} {
+    %cst = arith.constant dense<256> : tensor<64x1xi32, #blocked>
+    %cst_0 = arith.constant dense<32768> : tensor<64x1xi32, #blocked>
+    %cst_1 = arith.constant dense<256> : tensor<1x8xi32, #blocked>
+    %cst_2 = arith.constant dense<128> : tensor<1x8xi32, #blocked>
+    %c0_i32 = arith.constant 0 : i32
+    %c128_i32 = arith.constant 128 : i32
+    %c8_i32 = arith.constant 8 : i32
+    %cst_3 = arith.constant dense<0.000000e+00> : tensor<64x8xf32, #blocked>
+    %c64_i32 = arith.constant 64 : i32
+    %0 = tt.get_program_id x : i32
+    %1 = arith.muli %0, %c64_i32 : i32
+    %2 = tt.make_range {end = 64 : i32, start = 0 : i32} : tensor<64xi32, #triton_gpu.slice<{dim = 1, parent = #blocked}>>
+    %3 = tt.make_range {end = 64 : i32, start = 0 : i32} : tensor<64xi32, #triton_gpu.slice<{dim = 1, parent = #blocked1}>>
+    %4 = tt.expand_dims %2 {axis = 1 : i32} : (tensor<64xi32, #triton_gpu.slice<{dim = 1, parent = #blocked}>>) -> tensor<64x1xi32, #blocked>
+    %5 = tt.expand_dims %3 {axis = 1 : i32} : (tensor<64xi32, #triton_gpu.slice<{dim = 1, parent = #blocked1}>>) -> tensor<64x1xi32, #blocked1>
+    %6 = tt.splat %1 : (i32) -> tensor<64x1xi32, #blocked>
+    %7 = tt.splat %1 : (i32) -> tensor<64x1xi32, #blocked1>
+    %8 = arith.addi %6, %4 : tensor<64x1xi32, #blocked>
+    %9 = arith.addi %7, %5 : tensor<64x1xi32, #blocked1>
+    %10 = tt.make_range {end = 8 : i32, start = 0 : i32} : tensor<8xi32, #triton_gpu.slice<{dim = 0, parent = #blocked}>>
+    %11 = tt.expand_dims %10 {axis = 0 : i32} : (tensor<8xi32, #triton_gpu.slice<{dim = 0, parent = #blocked}>>) -> tensor<1x8xi32, #blocked>
+    %12 = arith.remsi %8, %cst : tensor<64x1xi32, #blocked>
+    %13 = arith.divsi %8, %cst : tensor<64x1xi32, #blocked>
+    %14 = tt.broadcast %12 : (tensor<64x1xi32, #blocked>) -> tensor<64x8xi32, #blocked>
+    %15 = arith.muli %13, %cst_0 : tensor<64x1xi32, #blocked>
+    %16 = tt.broadcast %15 : (tensor<64x1xi32, #blocked>) -> tensor<64x8xi32, #blocked>
+    %17 = tt.splat %arg0 : (!tt.ptr<f32, 1>) -> tensor<64x8x!tt.ptr<f32, 1>, #blocked>
+    %18 = tt.splat %arg1 : (!tt.ptr<f32, 1>) -> tensor<64x8x!tt.ptr<f32, 1>, #blocked>
+    %19 = scf.for %arg5 = %c0_i32 to %c128_i32 step %c8_i32 iter_args(%arg6 = %cst_3) -> (tensor<64x8xf32, #blocked>)  : i32 {
+      %25 = tt.splat %arg5 : (i32) -> tensor<1x8xi32, #blocked>
+      %26 = arith.addi %25, %11 : tensor<1x8xi32, #blocked>
+      %27 = arith.cmpi slt, %26, %cst_2 : tensor<1x8xi32, #blocked>
+      %28 = arith.muli %26, %cst_1 : tensor<1x8xi32, #blocked>
+      %29 = tt.broadcast %28 : (tensor<1x8xi32, #blocked>) -> tensor<64x8xi32, #blocked>
+      %30 = arith.addi %14, %29 : tensor<64x8xi32, #blocked>
+      %31 = arith.addi %30, %16 : tensor<64x8xi32, #blocked>
+      %32 = tt.addptr %17, %31 : tensor<64x8x!tt.ptr<f32, 1>, #blocked>, tensor<64x8xi32, #blocked>
+      %33 = tt.broadcast %27 : (tensor<1x8xi1, #blocked>) -> tensor<64x8xi1, #blocked>
+      %34 = tt.load %32, %33, %cst_3 {cache = 1 : i32, evict = 2 : i32, isVolatile = false} : tensor<64x8xf32, #blocked>
+      %35 = tt.addptr %18, %31 : tensor<64x8x!tt.ptr<f32, 1>, #blocked>, tensor<64x8xi32, #blocked>
+      %36 = tt.load %35, %33, %cst_3 {cache = 1 : i32, evict = 2 : i32, isVolatile = false} : tensor<64x8xf32, #blocked>
+      %37 = arith.mulf %34, %36 : tensor<64x8xf32, #blocked>
+      %38 = arith.addf %arg6, %37 : tensor<64x8xf32, #blocked>
+      %39 = arith.select %33, %38, %arg6 : tensor<64x8xi1, #blocked>, tensor<64x8xf32, #blocked>
+      scf.yield %39 : tensor<64x8xf32, #blocked>
+    }
+    %20 = "tt.reduce"(%19) <{axis = 1 : i32}> ({
+    ^bb0(%arg5: f32, %arg6: f32):
+      %25 = arith.addf %arg5, %arg6 : f32
+      tt.reduce.return %25 : f32
+    }) : (tensor<64x8xf32, #blocked>) -> tensor<64xf32, #triton_gpu.slice<{dim = 1, parent = #blocked}>>
+    %21 = triton_gpu.convert_layout %20 : (tensor<64xf32, #triton_gpu.slice<{dim = 1, parent = #blocked}>>) -> tensor<64xf32, #triton_gpu.slice<{dim = 1, parent = #blocked1}>>
+    %22 = tt.expand_dims %21 {axis = 1 : i32} : (tensor<64xf32, #triton_gpu.slice<{dim = 1, parent = #blocked1}>>) -> tensor<64x1xf32, #blocked1>
+    %23 = tt.splat %arg2 : (!tt.ptr<f32, 1>) -> tensor<64x1x!tt.ptr<f32, 1>, #blocked1>
+    %24 = tt.addptr %23, %9 : tensor<64x1x!tt.ptr<f32, 1>, #blocked1>, tensor<64x1xi32, #blocked1>
+    tt.store %24, %22 {cache = 1 : i32, evict = 1 : i32} : tensor<64x1xf32, #blocked1>
+    tt.return
+  }
+}

.triton/dump/284d053ae6736ef59b97361c588791fb/triton_.ptx

@@ -0,0 +1,577 @@
+//
+// Generated by LLVM NVPTX Back-End
+//
+
+.version 8.2
+.target sm_89
+.address_size 64
+
+	// .globl	triton__0d1d2d3de4de
+.extern .shared .align 1 .b8 global_smem[];
+
+.visible .entry triton__0d1d2d3de4de(
+	.param .u64 triton__0d1d2d3de4de_param_0,
+	.param .u64 triton__0d1d2d3de4de_param_1,
+	.param .u64 triton__0d1d2d3de4de_param_2,
+	.param .u32 triton__0d1d2d3de4de_param_3,
+	.param .u32 triton__0d1d2d3de4de_param_4
+)
+.maxntid 128, 1, 1
+{
+	.reg .pred 	%p<20>;
+	.reg .b16 	%rs<5>;
+	.reg .b32 	%r<98>;
+	.reg .f32 	%f<47>;
+	.reg .b64 	%rd<10>;
+	.loc	1 18 0
+$L__func_begin0:
+	.loc	1 18 0
+
+	ld.param.u64 	%rd3, [triton__0d1d2d3de4de_param_2];
+	ld.param.u64 	%rd2, [triton__0d1d2d3de4de_param_1];
+	ld.param.u64 	%rd1, [triton__0d1d2d3de4de_param_0];
+$L__tmp0:
+	.loc	1 22 44
+	mov.u32 	%r1, %tid.x;
+	and.b32  	%r2, %r1, 31;
+	shl.b32 	%r13, %r1, 2;
+	and.b32  	%r3, %r13, 60;
+	.loc	1 24 33
+	bfe.u32 	%r4, %r1, 5, 2;
+	.loc	1 21 28
+	mov.u32 %r11, %ctaid.x;
+	.loc	1 21 33
+	shl.b32 	%r5, %r11, 6;
+	.loc	1 22 23
+	or.b32  	%r14, %r5, %r3;
+	.loc	1 26 20
+	shr.s32 	%r16, %r14, 31;
+	shr.u32 	%r17, %r16, 24;
+	add.s32 	%r18, %r14, %r17;
+	shr.s32 	%r19, %r18, 8;
+	.loc	1 29 36
+	mad.lo.s32 	%r20, %r19, 32512, %r14;
+	shl.b32 	%r21, %r4, 9;
+	add.s32 	%r22, %r20, %r21;
+	shl.b32 	%r23, %r1, 4;
+	and.b32  	%r24, %r23, 256;
+	add.s32 	%r96, %r22, %r24;
+	mov.f32 	%f43, 0f00000000;
+	mov.b32 	%r97, -8;
+	mov.pred 	%p1, -1;
+	mov.f32 	%f44, %f43;
+	mov.f32 	%f45, %f43;
+	mov.f32 	%f46, %f43;
+$L__BB0_1:
+	.loc	1 33 34
+	mul.wide.s32 	%rd6, %r96, 2;
+	add.s64 	%rd4, %rd1, %rd6;
+	mov.b32 	%r27, 0;
+	.loc	1 33 63
+	mov.u32 %r25, 0x0;
+	mov.u32 %r26, 0x0;
+	@%p1 ld.global.L1::evict_first.v2.b32 { %r25, %r26 }, [ %rd4 + 0 ];
+	@!%p1 mov.u32 %r25, %r27;
+	@!%p1 mov.u32 %r26, %r27;
+	cvt.u16.u32 	%rs1, %r25;
+	{ .reg .b16 tmp; mov.b32 {tmp, %rs2}, %r25; }
+	cvt.u16.u32 	%rs3, %r26;
+	{ .reg .b16 tmp; mov.b32 {tmp, %rs4}, %r26; }
+	.loc	1 33 115
+	cvt.f32.bf16 %r29, %rs1;
+	mov.b32 	%f13, %r29;
+	cvt.f32.bf16 %r30, %rs2;
+	mov.b32 	%f14, %r30;
+	cvt.f32.bf16 %r31, %rs3;
+	mov.b32 	%f15, %r31;
+	cvt.f32.bf16 %r32, %rs4;
+	mov.b32 	%f16, %r32;
+	.loc	1 34 34
+	mul.wide.s32 	%rd7, %r96, 4;
+	add.s64 	%rd5, %rd2, %rd7;
+	.loc	1 34 63
+	mov.u32 %r33, 0x0;
+	mov.u32 %r34, 0x0;
+	mov.u32 %r35, 0x0;
+	mov.u32 %r36, 0x0;
+	@%p1 ld.global.L1::evict_first.v4.b32 { %r33, %r34, %r35, %r36 }, [ %rd5 + 0 ];
+	@!%p1 mov.u32 %r33, %r27;
+	@!%p1 mov.u32 %r34, %r27;
+	@!%p1 mov.u32 %r35, %r27;
+	@!%p1 mov.u32 %r36, %r27;
+	mov.b32 	%f17, %r33;
+	mov.b32 	%f18, %r34;
+	mov.b32 	%f19, %r35;
+	mov.b32 	%f20, %r36;
+	.loc	1 39 38
+	fma.rn.f32 	%f46, %f16, %f20, %f46;
+	fma.rn.f32 	%f45, %f15, %f19, %f45;
+	fma.rn.f32 	%f44, %f14, %f18, %f44;
+	fma.rn.f32 	%f43, %f13, %f17, %f43;
+	.loc	1 29 36
+	add.s32 	%r97, %r97, 8;
+	add.s32 	%r96, %r96, 2048;
+	setp.lt.u32 	%p9, %r97, 120;
+	@%p9 bra 	$L__BB0_1;
+	.loc	1 22 44
+	and.b32  	%r58, %r1, 63;
+	.loc	1 22 23
+	or.b32  	%r59, %r5, %r58;
+$L__tmp1:
+	.loc	2 243 36
+	mov.b32 	%r60, %f43;
+	shfl.sync.bfly.b32	%r61, %r60, 16, 31, -1;
+	mov.b32 	%f21, %r61;
+$L__tmp2:
+	.loc	2 233 15
+	add.f32 	%f22, %f43, %f21;
+$L__tmp3:
+	.loc	2 243 36
+	mov.b32 	%r62, %f44;
+	shfl.sync.bfly.b32	%r63, %r62, 16, 31, -1;
+	mov.b32 	%f23, %r63;
+$L__tmp4:
+	.loc	2 233 15
+	add.f32 	%f24, %f44, %f23;
+$L__tmp5:
+	.loc	2 243 36
+	mov.b32 	%r64, %f45;
+	shfl.sync.bfly.b32	%r65, %r64, 16, 31, -1;
+	mov.b32 	%f25, %r65;
+$L__tmp6:
+	.loc	2 233 15
+	add.f32 	%f26, %f45, %f25;
+$L__tmp7:
+	.loc	2 243 36
+	mov.b32 	%r66, %f46;
+	shfl.sync.bfly.b32	%r67, %r66, 16, 31, -1;
+	mov.b32 	%f27, %r67;
+$L__tmp8:
+	.loc	2 233 15
+	add.f32 	%f28, %f46, %f27;
+$L__tmp9:
+	.loc	2 243 36
+	setp.lt.u32 	%p10, %r2, 16;
+	shl.b32 	%r68, %r3, 2;
+	or.b32  	%r69, %r68, %r4;
+	shl.b32 	%r70, %r69, 2;
+	mov.u32 	%r71, global_smem;
+	add.s32 	%r41, %r71, %r70;
+	mov.b32 	%r42, %f22;
+	@%p10 st.shared.b32 [ %r41 + 0 ], %r42;
+	shl.b32 	%r72, %r4, 2;
+	shl.b32 	%r73, %r3, 4;
+	or.b32  	%r74, %r73, 16;
+	or.b32  	%r75, %r74, %r72;
+	add.s32 	%r43, %r71, %r75;
+	mov.b32 	%r44, %f24;
+	@%p10 st.shared.b32 [ %r43 + 0 ], %r44;
+	or.b32  	%r76, %r73, 32;
+	or.b32  	%r77, %r76, %r72;
+	add.s32 	%r45, %r71, %r77;
+	mov.b32 	%r46, %f26;
+	@%p10 st.shared.b32 [ %r45 + 0 ], %r46;
+	or.b32  	%r78, %r73, 48;
+	or.b32  	%r79, %r78, %r72;
+	add.s32 	%r47, %r71, %r79;
+	mov.b32 	%r48, %f28;
+	@%p10 st.shared.b32 [ %r47 + 0 ], %r48;
+	bar.sync 	0;
+	setp.lt.s32 	%p14, %r1, 256;
+	add.s32 	%r50, %r71, %r13;
+	@%p14 ld.shared.b32 %r49, [ %r50 + 0 ];
+	mov.b32 	%f29, %r49;
+	shfl.sync.bfly.b32	%r81, %r49, 2, 31, -1;
+	mov.b32 	%f30, %r81;
+$L__tmp10:
+	.loc	2 233 15
+	add.f32 	%f31, %f29, %f30;
+$L__tmp11:
+	.loc	2 243 36
+	mov.b32 	%r82, %f31;
+	shfl.sync.bfly.b32	%r83, %r82, 1, 31, -1;
+	mov.b32 	%f32, %r83;
+$L__tmp12:
+	.loc	2 233 15
+	add.f32 	%f33, %f31, %f32;
+$L__tmp13:
+	.loc	2 243 36
+	and.b32  	%r84, %r1, 3;
+	setp.eq.s32 	%p19, %r84, 0;
+	and.pred  	%p15, %p14, %p19;
+	mov.b32 	%r52, %f33;
+	@%p15 st.shared.b32 [ %r50 + 0 ], %r52;
+	add.s32 	%r54, %r50, 512;
+	@%p14 ld.shared.b32 %r53, [ %r54 + 0 ];
+	mov.b32 	%f34, %r53;
+	shfl.sync.bfly.b32	%r85, %r53, 2, 31, -1;
+	mov.b32 	%f35, %r85;
+$L__tmp14:
+	.loc	2 233 15
+	add.f32 	%f36, %f34, %f35;
+$L__tmp15:
+	.loc	2 243 36
+	mov.b32 	%r86, %f36;
+	shfl.sync.bfly.b32	%r87, %r86, 1, 31, -1;
+	mov.b32 	%f37, %r87;
+$L__tmp16:
+	.loc	2 233 15
+	add.f32 	%f38, %f36, %f37;
+$L__tmp17:
+	.loc	2 243 36
+	mov.b32 	%r56, %f38;
+	@%p15 st.shared.b32 [ %r54 + 0 ], %r56;
+	bar.sync 	0;
+	add.s32 	%r88, %r71, %r73;
+	ld.shared.f32 	%f39, [%r88];
+	add.s32 	%r89, %r71, %r74;
+	ld.shared.f32 	%f40, [%r89];
+	add.s32 	%r90, %r71, %r76;
+	ld.shared.f32 	%f41, [%r90];
+	add.s32 	%r91, %r71, %r78;
+	ld.shared.f32 	%f42, [%r91];
+$L__tmp18:
+	.loc	1 40 28
+	bar.sync 	0;
+	add.s32 	%r92, %r71, %r68;
+	st.shared.f32 	[%r92], %f39;
+	st.shared.f32 	[%r92+4], %f40;
+	st.shared.f32 	[%r92+8], %f41;
+	st.shared.f32 	[%r92+12], %f42;
+	bar.sync 	0;
+	shl.b32 	%r93, %r58, 2;
+	add.s32 	%r94, %r71, %r93;
+	ld.shared.u32 	%r57, [%r94];
+	.loc	1 41 25
+	mul.wide.s32 	%rd9, %r59, 4;
+	add.s64 	%rd8, %rd3, %rd9;
+	.loc	1 41 36
+	and.b32  	%r95, %r1, 64;
+	setp.eq.s32 	%p18, %r95, 0;
+	@%p18 st.global.b32 [ %rd8 + 0 ], { %r57 };
+	.loc	1 41 4
+	ret;
+$L__tmp19:
+$L__func_end0:
+
+}
+	.file	1 "/tmp/torchinductor_root/sj/csjd7mlrjujd4uwze5tkg7ptteagpihgt5ztatfqchprcrax22ls.py"
+	.file	2 "/usr/local/lib/python3.10/dist-packages/triton/language/standard.py"
+	.section	.debug_abbrev
+	{
+.b8 1
+.b8 17
+.b8 1
+.b8 37
+.b8 8
+.b8 19
+.b8 5
+.b8 3
+.b8 8
+.b8 16
+.b8 6
+.b8 27
+.b8 8
+.b8 180
+.b8 66
+.b8 12
+.b8 17
+.b8 1
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+.b8 1
+.b8 0
+.b8 0
+.b8 2
+.b8 46
+.b8 0
+.b8 135
+.b8 64
+.b8 8
+.b8 3
+.b8 8
+.b8 58
+.b8 11
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+.b8 11
+.b8 63
+.b8 12
+.b8 32
+.b8 11
+.b8 0
+.b8 0
+.b8 3
+.b8 46
+.b8 1
+.b8 17
+.b8 1
+.b8 18
+.b8 1
+.b8 64
+.b8 10
+.b8 49
+.b8 19
+.b8 0
+.b8 0
+.b8 4
+.b8 29
+.b8 0
+.b8 49
+.b8 19
+.b8 17
+.b8 1
+.b8 18
+.b8 1
+.b8 88
+.b8 11
+.b8 89
+.b8 11
+.b8 87
+.b8 11
+.b8 0
+.b8 0
+.b8 5
+.b8 29
+.b8 1
+.b8 49
+.b8 19
+.b8 17
+.b8 1
+.b8 18
+.b8 1
+.b8 88
+.b8 11
+.b8 89
+.b8 11
+.b8 87
+.b8 11
+.b8 0
+.b8 0
+.b8 0
+	}
+	.section	.debug_info
+	{
+.b32 266
+.b8 2
+.b8 0
+.b32 .debug_abbrev
+.b8 8
+.b8 1
+.b8 116
+.b8 114
+.b8 105
+.b8 116
+.b8 111
+.b8 110
+.b8 0
+.b8 2
+.b8 0
+.b8 99
+.b8 115
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+.b8 100
+.b8 55
+.b8 109
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+.b8 114
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+.b8 117
+.b8 106
+.b8 100
+.b8 52
+.b8 117
+.b8 119
+.b8 122
+.b8 101
+.b8 53
+.b8 116
+.b8 107
+.b8 103
+.b8 55
+.b8 112
+.b8 116
+.b8 116
+.b8 101
+.b8 97
+.b8 103
+.b8 112
+.b8 105
+.b8 104
+.b8 103
+.b8 116
+.b8 53
+.b8 122
+.b8 116
+.b8 97
+.b8 116
+.b8 102
+.b8 113
+.b8 99
+.b8 104
+.b8 112
+.b8 114
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+.b8 114
+.b8 97
+.b8 120
+.b8 50
+.b8 50
+.b8 108
+.b8 115
+.b8 46
+.b8 112
+.b8 121
+.b8 0
+.b32 .debug_line
+.b8 47
+.b8 116
+.b8 109
+.b8 112
+.b8 47
+.b8 116
+.b8 111
+.b8 114
+.b8 99
+.b8 104
+.b8 105
+.b8 110
+.b8 100
+.b8 117
+.b8 99
+.b8 116
+.b8 111
+.b8 114
+.b8 95
+.b8 114
+.b8 111
+.b8 111
+.b8 116
+.b8 47
+.b8 115
+.b8 106
+.b8 0
+.b8 1
+.b64 $L__func_begin0
+.b64 $L__func_end0
+.b8 2
+.b8 116
+.b8 114
+.b8 105
+.b8 116
+.b8 111
+.b8 110
+.b8 95
+.b8 95
+.b8 48
+.b8 100
+.b8 49
+.b8 100
+.b8 50
+.b8 100
+.b8 51
+.b8 100
+.b8 101
+.b8 52
+.b8 100
+.b8 101
+.b8 0
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+.b8 105
+.b8 116
+.b8 111
+.b8 110
+.b8 95
+.b8 95
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+.b8 100
+.b8 49
+.b8 100
+.b8 50
+.b8 100
+.b8 51
+.b8 100
+.b8 101
+.b8 52
+.b8 100
+.b8 101
+.b8 0
+.b8 1
+.b8 18
+.b8 1
+.b8 1
+.b8 3
+.b64 $L__func_begin0
+.b64 $L__func_end0
+.b8 1
+.b8 156
+.b32 125
+.b8 4
+.b32 125
+.b64 $L__tmp1
+.b64 $L__tmp18
+.b8 2
+.b8 40
+.b8 25
+.b8 5
+.b32 125
+.b64 $L__tmp2
+.b64 $L__tmp17
+.b8 2
+.b8 40
+.b8 25
+.b8 4
+.b32 125
+.b64 $L__tmp2
+.b64 $L__tmp17
+.b8 2
+.b8 243
+.b8 36
+.b8 0
+.b8 0
+.b8 0
+	}
+	.section	.debug_pubnames
+	{
+.b32 $L__pubNames_end0-$L__pubNames_start0
+$L__pubNames_start0:
+.b8 2
+.b8 0
+.b32 .debug_info
+.b32 270
+.b32 125
+.b8 116
+.b8 114
+.b8 105
+.b8 116
+.b8 111
+.b8 110
+.b8 95
+.b8 95
+.b8 48
+.b8 100
+.b8 49
+.b8 100
+.b8 50
+.b8 100
+.b8 51
+.b8 100
+.b8 101
+.b8 52
+.b8 100
+.b8 101
+.b8 0
+.b32 0
+$L__pubNames_end0:
+	}
+	.section	.debug_pubtypes
+	{
+.b32 $L__pubTypes_end0-$L__pubTypes_start0
+$L__pubTypes_start0:
+.b8 2
+.b8 0
+.b32 .debug_info
+.b32 270
+.b32 0
+$L__pubTypes_end0:
+	}
+	.section	.debug_loc	{	}

.triton/dump/284d053ae6736ef59b97361c588791fb/triton_.ttgir

@@ -0,0 +1,65 @@
+#blocked = #triton_gpu.blocked<{sizePerThread = [4, 1], threadsPerWarp = [16, 2], warpsPerCTA = [1, 4], order = [0, 1], CTAsPerCGA = [1, 1], CTASplitNum = [1, 1], CTAOrder = [1, 0]}>
+#blocked1 = #triton_gpu.blocked<{sizePerThread = [1, 1], threadsPerWarp = [32, 1], warpsPerCTA = [2, 2], order = [0, 1], CTAsPerCGA = [1, 1], CTASplitNum = [1, 1], CTAOrder = [1, 0]}>
+module attributes {"triton_gpu.compute-capability" = 89 : i32, "triton_gpu.num-ctas" = 1 : i32, "triton_gpu.num-warps" = 4 : i32, "triton_gpu.threads-per-warp" = 32 : i32} {
+  tt.func public @triton__0d1d2d3de4de(%arg0: !tt.ptr<bf16, 1> {tt.divisibility = 16 : i32}, %arg1: !tt.ptr<f32, 1> {tt.divisibility = 16 : i32}, %arg2: !tt.ptr<f32, 1> {tt.divisibility = 16 : i32}, %arg3: i32 {tt.divisibility = 16 : i32, tt.max_divisibility = 16 : i32}, %arg4: i32 {tt.divisibility = 16 : i32, tt.max_divisibility = 16 : i32}) attributes {noinline = false} {
+    %cst = arith.constant dense<256> : tensor<64x1xi32, #blocked>
+    %cst_0 = arith.constant dense<32768> : tensor<64x1xi32, #blocked>
+    %cst_1 = arith.constant dense<256> : tensor<1x8xi32, #blocked>
+    %cst_2 = arith.constant dense<128> : tensor<1x8xi32, #blocked>
+    %c0_i32 = arith.constant 0 : i32
+    %c128_i32 = arith.constant 128 : i32
+    %c8_i32 = arith.constant 8 : i32
+    %cst_3 = arith.constant dense<0.000000e+00> : tensor<64x8xf32, #blocked>
+    %cst_4 = arith.constant dense<0.000000e+00> : tensor<64x8xbf16, #blocked>
+    %c64_i32 = arith.constant 64 : i32
+    %0 = tt.get_program_id x : i32
+    %1 = arith.muli %0, %c64_i32 : i32
+    %2 = tt.make_range {end = 64 : i32, start = 0 : i32} : tensor<64xi32, #triton_gpu.slice<{dim = 1, parent = #blocked}>>
+    %3 = tt.make_range {end = 64 : i32, start = 0 : i32} : tensor<64xi32, #triton_gpu.slice<{dim = 1, parent = #blocked1}>>
+    %4 = tt.expand_dims %2 {axis = 1 : i32} : (tensor<64xi32, #triton_gpu.slice<{dim = 1, parent = #blocked}>>) -> tensor<64x1xi32, #blocked>
+    %5 = tt.expand_dims %3 {axis = 1 : i32} : (tensor<64xi32, #triton_gpu.slice<{dim = 1, parent = #blocked1}>>) -> tensor<64x1xi32, #blocked1>
+    %6 = tt.splat %1 : (i32) -> tensor<64x1xi32, #blocked>
+    %7 = tt.splat %1 : (i32) -> tensor<64x1xi32, #blocked1>
+    %8 = arith.addi %6, %4 : tensor<64x1xi32, #blocked>
+    %9 = arith.addi %7, %5 : tensor<64x1xi32, #blocked1>
+    %10 = tt.make_range {end = 8 : i32, start = 0 : i32} : tensor<8xi32, #triton_gpu.slice<{dim = 0, parent = #blocked}>>
+    %11 = tt.expand_dims %10 {axis = 0 : i32} : (tensor<8xi32, #triton_gpu.slice<{dim = 0, parent = #blocked}>>) -> tensor<1x8xi32, #blocked>
+    %12 = arith.remsi %8, %cst : tensor<64x1xi32, #blocked>
+    %13 = arith.divsi %8, %cst : tensor<64x1xi32, #blocked>
+    %14 = tt.broadcast %12 : (tensor<64x1xi32, #blocked>) -> tensor<64x8xi32, #blocked>
+    %15 = arith.muli %13, %cst_0 : tensor<64x1xi32, #blocked>
+    %16 = tt.broadcast %15 : (tensor<64x1xi32, #blocked>) -> tensor<64x8xi32, #blocked>
+    %17 = tt.splat %arg0 : (!tt.ptr<bf16, 1>) -> tensor<64x8x!tt.ptr<bf16, 1>, #blocked>
+    %18 = tt.splat %arg1 : (!tt.ptr<f32, 1>) -> tensor<64x8x!tt.ptr<f32, 1>, #blocked>
+    %19 = scf.for %arg5 = %c0_i32 to %c128_i32 step %c8_i32 iter_args(%arg6 = %cst_3) -> (tensor<64x8xf32, #blocked>)  : i32 {
+      %25 = tt.splat %arg5 : (i32) -> tensor<1x8xi32, #blocked>
+      %26 = arith.addi %25, %11 : tensor<1x8xi32, #blocked>
+      %27 = arith.cmpi slt, %26, %cst_2 : tensor<1x8xi32, #blocked>
+      %28 = arith.muli %26, %cst_1 : tensor<1x8xi32, #blocked>
+      %29 = tt.broadcast %28 : (tensor<1x8xi32, #blocked>) -> tensor<64x8xi32, #blocked>
+      %30 = arith.addi %14, %29 : tensor<64x8xi32, #blocked>
+      %31 = arith.addi %30, %16 : tensor<64x8xi32, #blocked>
+      %32 = tt.addptr %17, %31 : tensor<64x8x!tt.ptr<bf16, 1>, #blocked>, tensor<64x8xi32, #blocked>
+      %33 = tt.broadcast %27 : (tensor<1x8xi1, #blocked>) -> tensor<64x8xi1, #blocked>
+      %34 = tt.load %32, %33, %cst_4 {cache = 1 : i32, evict = 2 : i32, isVolatile = false} : tensor<64x8xbf16, #blocked>
+      %35 = arith.extf %34 : tensor<64x8xbf16, #blocked> to tensor<64x8xf32, #blocked>
+      %36 = tt.addptr %18, %31 : tensor<64x8x!tt.ptr<f32, 1>, #blocked>, tensor<64x8xi32, #blocked>
+      %37 = tt.load %36, %33, %cst_3 {cache = 1 : i32, evict = 2 : i32, isVolatile = false} : tensor<64x8xf32, #blocked>
+      %38 = arith.mulf %35, %37 : tensor<64x8xf32, #blocked>
+      %39 = arith.addf %arg6, %38 : tensor<64x8xf32, #blocked>
+      %40 = arith.select %33, %39, %arg6 : tensor<64x8xi1, #blocked>, tensor<64x8xf32, #blocked>
+      scf.yield %40 : tensor<64x8xf32, #blocked>
+    }
+    %20 = "tt.reduce"(%19) <{axis = 1 : i32}> ({
+    ^bb0(%arg5: f32, %arg6: f32):
+      %25 = arith.addf %arg5, %arg6 : f32
+      tt.reduce.return %25 : f32
+    }) : (tensor<64x8xf32, #blocked>) -> tensor<64xf32, #triton_gpu.slice<{dim = 1, parent = #blocked}>>
+    %21 = triton_gpu.convert_layout %20 : (tensor<64xf32, #triton_gpu.slice<{dim = 1, parent = #blocked}>>) -> tensor<64xf32, #triton_gpu.slice<{dim = 1, parent = #blocked1}>>
+    %22 = tt.expand_dims %21 {axis = 1 : i32} : (tensor<64xf32, #triton_gpu.slice<{dim = 1, parent = #blocked1}>>) -> tensor<64x1xf32, #blocked1>
+    %23 = tt.splat %arg2 : (!tt.ptr<f32, 1>) -> tensor<64x1x!tt.ptr<f32, 1>, #blocked1>
+    %24 = tt.addptr %23, %9 : tensor<64x1x!tt.ptr<f32, 1>, #blocked1>, tensor<64x1xi32, #blocked1>
+    tt.store %24, %22 {cache = 1 : i32, evict = 1 : i32} : tensor<64x1xf32, #blocked1>
+    tt.return
+  }
+}

.triton/dump/3791d630ba27aad5e647360045d2f1b5/triton_.ptx

@@ -0,0 +1,743 @@
+//
+// Generated by LLVM NVPTX Back-End
+//
+
+.version 8.2
+.target sm_89
+.address_size 64
+
+	// .globl	triton__0d1d2d3d4d5d6d7de8de
+.extern .shared .align 1 .b8 global_smem[];
+
+.visible .entry triton__0d1d2d3d4d5d6d7de8de(
+	.param .u64 triton__0d1d2d3d4d5d6d7de8de_param_0,
+	.param .u64 triton__0d1d2d3d4d5d6d7de8de_param_1,
+	.param .u64 triton__0d1d2d3d4d5d6d7de8de_param_2,
+	.param .u64 triton__0d1d2d3d4d5d6d7de8de_param_3,
+	.param .u64 triton__0d1d2d3d4d5d6d7de8de_param_4,
+	.param .u64 triton__0d1d2d3d4d5d6d7de8de_param_5,
+	.param .u64 triton__0d1d2d3d4d5d6d7de8de_param_6,
+	.param .u32 triton__0d1d2d3d4d5d6d7de8de_param_7,
+	.param .u32 triton__0d1d2d3d4d5d6d7de8de_param_8
+)
+.maxntid 64, 1, 1
+{
+	.reg .pred 	%p<37>;
+	.reg .b16 	%rs<9>;
+	.reg .b32 	%r<110>;
+	.reg .f32 	%f<86>;
+	.reg .b64 	%rd<26>;
+	.loc	1 18 0
+$L__func_begin0:
+	.loc	1 18 0
+
+	ld.param.u64 	%rd15, [triton__0d1d2d3d4d5d6d7de8de_param_0];
+	ld.param.u64 	%rd16, [triton__0d1d2d3d4d5d6d7de8de_param_1];
+$L__tmp0:
+	.loc	1 26 26
+	mov.u32 	%r76, %tid.x;
+	and.b32  	%r77, %r76, 31;
+	ld.param.u64 	%rd17, [triton__0d1d2d3d4d5d6d7de8de_param_2];
+	ld.param.u64 	%rd18, [triton__0d1d2d3d4d5d6d7de8de_param_3];
+	ld.param.u64 	%rd19, [triton__0d1d2d3d4d5d6d7de8de_param_4];
+	shl.b32 	%r78, %r76, 2;
+	ld.param.u64 	%rd20, [triton__0d1d2d3d4d5d6d7de8de_param_5];
+	and.b32  	%r79, %r78, 252;
+	ld.param.u64 	%rd21, [triton__0d1d2d3d4d5d6d7de8de_param_6];
+	.loc	1 23 28
+	mov.u32 %r1, %ctaid.x;
+	.loc	1 30 40
+	shl.b32 	%r80, %r1, 8;
+	.loc	1 30 36
+	or.b32  	%r81, %r80, %r79;
+	.loc	1 30 30
+	mul.wide.s32 	%rd22, %r81, 2;
+	add.s64 	%rd1, %rd16, %rd22;
+	mov.b32 	%r4, 0;
+	mov.pred 	%p1, -1;
+	.loc	1 30 46
+	mov.u32 %r2, 0x0;
+	mov.u32 %r3, 0x0;
+	@%p1 ld.global.v2.b32 { %r2, %r3 }, [ %rd1 + 0 ];
+	@!%p1 mov.u32 %r2, %r4;
+	@!%p1 mov.u32 %r3, %r4;
+	cvt.u16.u32 	%rs1, %r2;
+	{ .reg .b16 tmp; mov.b32 {tmp, %rs2}, %r2; }
+	cvt.u16.u32 	%rs3, %r3;
+	{ .reg .b16 tmp; mov.b32 {tmp, %rs4}, %r3; }
+	.loc	1 30 67
+	cvt.f32.bf16 %r6, %rs1;
+	mov.b32 	%f1, %r6;
+	cvt.f32.bf16 %r7, %rs2;
+	mov.b32 	%f2, %r7;
+	cvt.f32.bf16 %r8, %rs3;
+	mov.b32 	%f3, %r8;
+	cvt.f32.bf16 %r9, %rs4;
+	mov.b32 	%f4, %r9;
+	.loc	1 31 30
+	mul.wide.u32 	%rd23, %r79, 4;
+	add.s64 	%rd2, %rd17, %rd23;
+	.loc	1 31 35
+	mov.u32 %r10, 0x0;
+	mov.u32 %r11, 0x0;
+	mov.u32 %r12, 0x0;
+	mov.u32 %r13, 0x0;
+	@%p1 ld.global.L1::evict_last.v4.b32 { %r10, %r11, %r12, %r13 }, [ %rd2 + 0 ];
+	@!%p1 mov.u32 %r10, %r4;
+	@!%p1 mov.u32 %r11, %r4;
+	@!%p1 mov.u32 %r12, %r4;
+	@!%p1 mov.u32 %r13, %r4;
+	mov.b32 	%f5, %r10;
+	mov.b32 	%f6, %r11;
+	mov.b32 	%f7, %r12;
+	mov.b32 	%f8, %r13;
+	.loc	1 32 30
+	mul.wide.s32 	%rd24, %r81, 4;
+	add.s64 	%rd3, %rd18, %rd24;
+	.loc	1 32 46
+	mov.u32 %r18, 0x0;
+	mov.u32 %r19, 0x0;
+	mov.u32 %r20, 0x0;
+	mov.u32 %r21, 0x0;
+	@%p1 ld.global.v4.b32 { %r18, %r19, %r20, %r21 }, [ %rd3 + 0 ];
+	@!%p1 mov.u32 %r18, %r4;
+	@!%p1 mov.u32 %r19, %r4;
+	@!%p1 mov.u32 %r20, %r4;
+	@!%p1 mov.u32 %r21, %r4;
+	mov.b32 	%f9, %r18;
+	mov.b32 	%f10, %r19;
+	mov.b32 	%f11, %r20;
+	mov.b32 	%f12, %r21;
+	.loc	1 33 30
+	mul.wide.s32 	%rd25, %r1, 4;
+	add.s64 	%rd4, %rd19, %rd25;
+	.loc	1 33 35
+	mov.u32 %r26, 0x0;
+	@%p1 ld.global.L1::evict_last.b32 { %r26 }, [ %rd4 + 0 ];
+	mov.b32 	%f13, %r26;
+	mov.u32 %r27, 0x0;
+	@%p1 ld.global.L1::evict_last.b32 { %r27 }, [ %rd4 + 0 ];
+	mov.u32 %r28, 0x0;
+	@%p1 ld.global.L1::evict_last.b32 { %r28 }, [ %rd4 + 0 ];
+	mov.u32 %r29, 0x0;
+	@%p1 ld.global.L1::evict_last.b32 { %r29 }, [ %rd4 + 0 ];
+	.loc	1 34 31
+	add.s64 	%rd8, %rd20, %rd25;
+	.loc	1 34 36
+	mov.u32 %r55, 0x0;
+	@%p1 ld.global.L1::evict_last.b32 { %r55 }, [ %rd8 + 0 ];
+	mov.b32 	%f14, %r55;
+	mov.u32 %r31, 0x0;
+	@%p1 ld.global.L1::evict_last.b32 { %r31 }, [ %rd8 + 0 ];
+	mov.u32 %r32, 0x0;
+	@%p1 ld.global.L1::evict_last.b32 { %r32 }, [ %rd8 + 0 ];
+	mov.u32 %r33, 0x0;
+	@%p1 ld.global.L1::evict_last.b32 { %r33 }, [ %rd8 + 0 ];
+	.loc	1 35 35
+	add.s64 	%rd12, %rd15, %rd24;
+	.loc	1 35 51
+	mov.u32 %r34, 0x0;
+	mov.u32 %r35, 0x0;
+	mov.u32 %r36, 0x0;
+	mov.u32 %r37, 0x0;
+	@%p1 ld.global.v4.b32 { %r34, %r35, %r36, %r37 }, [ %rd12 + 0 ];
+	@!%p1 mov.u32 %r34, %r4;
+	@!%p1 mov.u32 %r35, %r4;
+	@!%p1 mov.u32 %r36, %r4;
+	@!%p1 mov.u32 %r37, %r4;
+	mov.b32 	%f15, %r34;
+	mov.b32 	%f16, %r35;
+	mov.b32 	%f17, %r36;
+	mov.b32 	%f18, %r37;
+	.loc	1 37 18
+	mul.f32 	%f19, %f1, %f5;
+	mul.f32 	%f20, %f2, %f6;
+	mul.f32 	%f21, %f3, %f7;
+	mul.f32 	%f22, %f4, %f8;
+$L__tmp1:
+	.loc	2 233 15
+	fma.rn.f32 	%f23, %f1, %f5, %f20;
+	fma.rn.f32 	%f24, %f3, %f7, %f23;
+	fma.rn.f32 	%f25, %f4, %f8, %f24;
+$L__tmp2:
+	.loc	2 243 36
+	mov.b32 	%r82, %f25;
+	shfl.sync.bfly.b32	%r83, %r82, 16, 31, -1;
+	mov.b32 	%f26, %r83;
+$L__tmp3:
+	.loc	2 233 15
+	add.f32 	%f27, %f25, %f26;
+$L__tmp4:
+	.loc	2 243 36
+	mov.b32 	%r84, %f27;
+	shfl.sync.bfly.b32	%r85, %r84, 8, 31, -1;
+	mov.b32 	%f28, %r85;
+$L__tmp5:
+	.loc	2 233 15
+	add.f32 	%f29, %f27, %f28;
+$L__tmp6:
+	.loc	2 243 36
+	mov.b32 	%r86, %f29;
+	shfl.sync.bfly.b32	%r87, %r86, 4, 31, -1;
+	mov.b32 	%f30, %r87;
+$L__tmp7:
+	.loc	2 233 15
+	add.f32 	%f31, %f29, %f30;
+$L__tmp8:
+	.loc	2 243 36
+	mov.b32 	%r88, %f31;
+	shfl.sync.bfly.b32	%r89, %r88, 2, 31, -1;
+	mov.b32 	%f32, %r89;
+$L__tmp9:
+	.loc	2 233 15
+	add.f32 	%f33, %f31, %f32;
+$L__tmp10:
+	.loc	2 243 36
+	mov.b32 	%r90, %f33;
+	shfl.sync.bfly.b32	%r91, %r90, 1, 31, -1;
+	mov.b32 	%f34, %r91;
+$L__tmp11:
+	.loc	2 233 15
+	add.f32 	%f35, %f33, %f34;
+$L__tmp12:
+	.loc	2 243 36
+	setp.eq.s32 	%p27, %r77, 0;
+	shr.u32 	%r92, %r76, 3;
+	and.b32  	%r93, %r92, 4;
+	mov.u32 	%r94, global_smem;
+	add.s32 	%r42, %r94, %r93;
+	mov.b32 	%r43, %f35;
+	@%p27 st.shared.b32 [ %r42 + 0 ], %r43;
+	bar.sync 	0;
+	setp.lt.s32 	%p28, %r76, 2;
+	add.s32 	%r45, %r94, %r78;
+	@%p28 ld.shared.b32 %r44, [ %r45 + 0 ];
+	mov.b32 	%f36, %r44;
+	shfl.sync.bfly.b32	%r95, %r44, 1, 31, -1;
+	mov.b32 	%f37, %r95;
+$L__tmp13:
+	.loc	2 233 15
+	add.f32 	%f38, %f36, %f37;
+$L__tmp14:
+	.loc	2 243 36
+	and.b32  	%r96, %r76, 1;
+	setp.eq.b32 	%p35, %r96, 1;
+	not.pred 	%p36, %p35;
+	and.pred  	%p29, %p28, %p36;
+	mov.b32 	%r47, %f38;
+	@%p29 st.shared.b32 [ %r45 + 0 ], %r47;
+	bar.sync 	0;
+	ld.shared.f32 	%f39, [global_smem];
+$L__tmp15:
+	.loc	3 8 15
+	add.f32 	%f40, %f39, 0f00000000;
+$L__tmp16:
+	.loc	1 41 19
+	sub.f32 	%f41, %f9, %f13;
+	sub.f32 	%f42, %f10, %f13;
+	sub.f32 	%f43, %f11, %f13;
+	sub.f32 	%f44, %f12, %f13;
+	.loc	1 42 20
+	mul.f32 	%f45, %f41, %f14;
+	mul.f32 	%f46, %f42, %f14;
+	mul.f32 	%f47, %f43, %f14;
+	mul.f32 	%f48, %f44, %f14;
+	.loc	1 43 19
+	mul.f32 	%f49, %f20, %f46;
+$L__tmp17:
+	.loc	2 243 36
+	bar.sync 	0;
+$L__tmp18:
+	.loc	2 233 15
+	fma.rn.f32 	%f50, %f19, %f45, %f49;
+	fma.rn.f32 	%f51, %f21, %f47, %f50;
+	fma.rn.f32 	%f52, %f22, %f48, %f51;
+$L__tmp19:
+	.loc	2 243 36
+	mov.b32 	%r97, %f52;
+	shfl.sync.bfly.b32	%r98, %r97, 16, 31, -1;
+	mov.b32 	%f53, %r98;
+$L__tmp20:
+	.loc	2 233 15
+	add.f32 	%f54, %f52, %f53;
+$L__tmp21:
+	.loc	2 243 36
+	mov.b32 	%r99, %f54;
+	shfl.sync.bfly.b32	%r100, %r99, 8, 31, -1;
+	mov.b32 	%f55, %r100;
+$L__tmp22:
+	.loc	2 233 15
+	add.f32 	%f56, %f54, %f55;
+$L__tmp23:
+	.loc	2 243 36
+	mov.b32 	%r101, %f56;
+	shfl.sync.bfly.b32	%r102, %r101, 4, 31, -1;
+	mov.b32 	%f57, %r102;
+$L__tmp24:
+	.loc	2 233 15
+	add.f32 	%f58, %f56, %f57;
+$L__tmp25:
+	.loc	2 243 36
+	mov.b32 	%r103, %f58;
+	shfl.sync.bfly.b32	%r104, %r103, 2, 31, -1;
+	mov.b32 	%f59, %r104;
+$L__tmp26:
+	.loc	2 233 15
+	add.f32 	%f60, %f58, %f59;
+$L__tmp27:
+	.loc	2 243 36
+	mov.b32 	%r105, %f60;
+	shfl.sync.bfly.b32	%r106, %r105, 1, 31, -1;
+	mov.b32 	%f61, %r106;
+$L__tmp28:
+	.loc	2 233 15
+	add.f32 	%f62, %f60, %f61;
+$L__tmp29:
+	.loc	2 243 36
+	mov.b32 	%r49, %f62;
+	@%p27 st.shared.b32 [ %r42 + 0 ], %r49;
+	bar.sync 	0;
+	@%p28 ld.shared.b32 %r50, [ %r45 + 0 ];
+	mov.b32 	%f63, %r50;
+	shfl.sync.bfly.b32	%r107, %r50, 1, 31, -1;
+	mov.b32 	%f64, %r107;
+$L__tmp30:
+	.loc	2 233 15
+	add.f32 	%f65, %f63, %f64;
+$L__tmp31:
+	.loc	2 243 36
+	mov.b32 	%r53, %f65;
+	@%p29 st.shared.b32 [ %r45 + 0 ], %r53;
+	bar.sync 	0;
+	ld.shared.f32 	%f66, [global_smem];
+$L__tmp32:
+	.loc	3 8 15
+	add.f32 	%f67, %f66, 0f00000000;
+	mov.b32 	%r56, 1132462080;
+$L__tmp33:
+	.loc	1 48 20
+	div.full.f32 %r54, %r55, %r56;
+	mov.b32 	%f68, %r54;
+	.loc	1 50 20
+	neg.f32 	%f69, %f40;
+	fma.rn.f32 	%f70, %f19, 0f43800000, %f69;
+	fma.rn.f32 	%f71, %f20, 0f43800000, %f69;
+	fma.rn.f32 	%f72, %f21, 0f43800000, %f69;
+	fma.rn.f32 	%f73, %f22, 0f43800000, %f69;
+	.loc	1 52 20
+	neg.f32 	%f74, %f45;
+	fma.rn.f32 	%f75, %f74, %f67, %f70;
+	neg.f32 	%f76, %f46;
+	fma.rn.f32 	%f77, %f76, %f67, %f71;
+	neg.f32 	%f78, %f47;
+	fma.rn.f32 	%f79, %f78, %f67, %f72;
+	neg.f32 	%f80, %f48;
+	fma.rn.f32 	%f81, %f80, %f67, %f73;
+	.loc	1 54 20
+	fma.rn.f32 	%f82, %f68, %f75, %f15;
+	fma.rn.f32 	%f83, %f68, %f77, %f16;
+	fma.rn.f32 	%f84, %f68, %f79, %f17;
+	fma.rn.f32 	%f85, %f68, %f81, %f18;
+	.loc	1 56 51
+	mov.b32 	%r66, %f82;
+	mov.b32 	%r67, %f83;
+	mov.b32 	%r68, %f84;
+	mov.b32 	%r69, %f85;
+	@%p1 st.global.v4.b32 [ %rd12 + 0 ], { %r66, %r67, %r68, %r69 };
+	.loc	1 57 25
+	add.s64 	%rd14, %rd21, %rd22;
+	.loc	1 57 48
+	cvt.rn.bf16.f32 %rs5, %r66;
+	cvt.rn.bf16.f32 %rs6, %r67;
+	cvt.rn.bf16.f32 %rs7, %r68;
+	cvt.rn.bf16.f32 %rs8, %r69;
+	mov.b32 	%r108, {%rs5, %rs6};
+	mov.b32 	%r109, {%rs7, %rs8};
+	@%p1 st.global.v2.b32 [ %rd14 + 0 ], { %r108, %r109 };
+	.loc	1 57 4
+	ret;
+$L__tmp34:
+$L__func_end0:
+
+}
+	.file	1 "/tmp/torchinductor_root/sn/csned4hyxpgwu5ttubs3r7uxkjq5yfl3zh6c2sozobtkek2uzfcv.py"
+	.file	2 "/usr/local/lib/python3.10/dist-packages/triton/language/standard.py"
+	.file	3 "/usr/local/lib/python3.10/dist-packages/torch/_inductor/triton_helpers.py"
+	.section	.debug_abbrev
+	{
+.b8 1
+.b8 17
+.b8 1
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+.b8 89
+.b8 11
+.b8 87
+.b8 11
+.b8 0
+.b8 0
+.b8 0
+	}
+	.section	.debug_info
+	{
+.b32 403
+.b8 2
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+.b32 .debug_abbrev
+.b8 8
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+.b8 0
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+.b64 $L__func_end0
+.b8 2
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+.b64 $L__func_begin0
+.b64 $L__func_end0
+.b8 1
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+.b32 125
+.b8 4
+.b32 125
+.b64 $L__tmp1
+.b64 $L__tmp14
+.b8 2
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+.b64 $L__tmp14
+.b8 2
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+.b64 $L__tmp2
+.b64 $L__tmp15
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+.b64 $L__tmp16
+.b8 3
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+.b64 $L__tmp17
+.b64 $L__tmp32
+.b8 2
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+.b64 $L__tmp18
+.b64 $L__tmp31
+.b8 2
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+.b64 $L__tmp31
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+.b32 125
+.b64 $L__tmp32
+.b64 $L__tmp33
+.b8 3
+.b8 46
+.b8 45
+.b8 0
+.b8 0
+	}
+	.section	.debug_pubnames
+	{
+.b32 $L__pubNames_end0-$L__pubNames_start0
+$L__pubNames_start0:
+.b8 2
+.b8 0
+.b32 .debug_info
+.b32 407
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+.b8 100
+.b8 101
+.b8 56
+.b8 100
+.b8 101
+.b8 0
+.b32 0
+$L__pubNames_end0:
+	}
+	.section	.debug_pubtypes
+	{
+.b32 $L__pubTypes_end0-$L__pubTypes_start0
+$L__pubTypes_start0:
+.b8 2
+.b8 0
+.b32 .debug_info
+.b32 407
+.b32 0
+$L__pubTypes_end0:
+	}
+	.section	.debug_loc	{	}

.triton/dump/3791d630ba27aad5e647360045d2f1b5/triton_.ttir

@@ -0,0 +1,72 @@
+module {
+  tt.func public @triton__0d1d2d3d4d5d6d7de8de(%arg0: !tt.ptr<f32, 1> {tt.divisibility = 16 : i32}, %arg1: !tt.ptr<bf16, 1> {tt.divisibility = 16 : i32}, %arg2: !tt.ptr<f32, 1> {tt.divisibility = 16 : i32}, %arg3: !tt.ptr<f32, 1> {tt.divisibility = 16 : i32}, %arg4: !tt.ptr<f32, 1> {tt.divisibility = 16 : i32}, %arg5: !tt.ptr<f32, 1> {tt.divisibility = 16 : i32}, %arg6: !tt.ptr<bf16, 1> {tt.divisibility = 16 : i32}, %arg7: i32 {tt.divisibility = 16 : i32, tt.max_divisibility = 16 : i32}, %arg8: i32 {tt.divisibility = 16 : i32, tt.max_divisibility = 16 : i32}) attributes {noinline = false} {
+    %c256_i32 = arith.constant 256 : i32
+    %cst = arith.constant dense<0.000000e+00> : tensor<256xbf16>
+    %cst_0 = arith.constant 0.000000e+00 : f32
+    %cst_1 = arith.constant dense<0.000000e+00> : tensor<256xf32>
+    %cst_2 = arith.constant dense<2.560000e+02> : tensor<256xf32>
+    %cst_3 = arith.constant dense<2.560000e+02> : tensor<1xf32>
+    %cst_4 = arith.constant dense<256> : tensor<256xi32>
+    %0 = tt.get_program_id x : i32
+    %1 = tt.make_range {end = 256 : i32, start = 0 : i32} : tensor<256xi32>
+    %2 = arith.cmpi slt, %1, %cst_4 : tensor<256xi32>
+    %3 = arith.muli %0, %c256_i32 : i32
+    %4 = tt.splat %3 : (i32) -> tensor<256xi32>
+    %5 = arith.addi %1, %4 : tensor<256xi32>
+    %6 = tt.splat %arg1 : (!tt.ptr<bf16, 1>) -> tensor<256x!tt.ptr<bf16, 1>>
+    %7 = tt.addptr %6, %5 : tensor<256x!tt.ptr<bf16, 1>>, tensor<256xi32>
+    %8 = tt.load %7, %2, %cst {cache = 1 : i32, evict = 1 : i32, isVolatile = false} : tensor<256xbf16>
+    %9 = arith.extf %8 : tensor<256xbf16> to tensor<256xf32>
+    %10 = tt.splat %arg2 : (!tt.ptr<f32, 1>) -> tensor<256x!tt.ptr<f32, 1>>
+    %11 = tt.addptr %10, %1 : tensor<256x!tt.ptr<f32, 1>>, tensor<256xi32>
+    %12 = tt.load %11, %2, %cst_1 {cache = 1 : i32, evict = 3 : i32, isVolatile = false} : tensor<256xf32>
+    %13 = tt.splat %arg3 : (!tt.ptr<f32, 1>) -> tensor<256x!tt.ptr<f32, 1>>
+    %14 = tt.addptr %13, %5 : tensor<256x!tt.ptr<f32, 1>>, tensor<256xi32>
+    %15 = tt.load %14, %2, %cst_1 {cache = 1 : i32, evict = 1 : i32, isVolatile = false} : tensor<256xf32>
+    %16 = tt.addptr %arg4, %0 : !tt.ptr<f32, 1>, i32
+    %17 = tt.splat %16 : (!tt.ptr<f32, 1>) -> tensor<1x!tt.ptr<f32, 1>>
+    %18 = tt.load %17 {cache = 1 : i32, evict = 3 : i32, isVolatile = false} : tensor<1xf32>
+    %19 = tt.addptr %arg5, %0 : !tt.ptr<f32, 1>, i32
+    %20 = tt.splat %19 : (!tt.ptr<f32, 1>) -> tensor<1x!tt.ptr<f32, 1>>
+    %21 = tt.load %20 {cache = 1 : i32, evict = 3 : i32, isVolatile = false} : tensor<1xf32>
+    %22 = tt.splat %arg0 : (!tt.ptr<f32, 1>) -> tensor<256x!tt.ptr<f32, 1>>
+    %23 = tt.addptr %22, %5 : tensor<256x!tt.ptr<f32, 1>>, tensor<256xi32>
+    %24 = tt.load %23, %2, %cst_1 {cache = 1 : i32, evict = 1 : i32, isVolatile = false} : tensor<256xf32>
+    %25 = arith.mulf %9, %12 : tensor<256xf32>
+    %26 = arith.select %2, %25, %cst_1 : tensor<256xi1>, tensor<256xf32>
+    %27 = "tt.reduce"(%26) <{axis = 0 : i32}> ({
+    ^bb0(%arg9: f32, %arg10: f32):
+      %50 = arith.addf %arg9, %arg10 : f32
+      tt.reduce.return %50 : f32
+    }) : (tensor<256xf32>) -> f32
+    %28 = arith.addf %27, %cst_0 : f32
+    %29 = tt.broadcast %18 : (tensor<1xf32>) -> tensor<256xf32>
+    %30 = arith.subf %15, %29 : tensor<256xf32>
+    %31 = tt.broadcast %21 : (tensor<1xf32>) -> tensor<256xf32>
+    %32 = arith.mulf %30, %31 : tensor<256xf32>
+    %33 = arith.mulf %25, %32 : tensor<256xf32>
+    %34 = arith.select %2, %33, %cst_1 : tensor<256xi1>, tensor<256xf32>
+    %35 = "tt.reduce"(%34) <{axis = 0 : i32}> ({
+    ^bb0(%arg9: f32, %arg10: f32):
+      %50 = arith.addf %arg9, %arg10 : f32
+      tt.reduce.return %50 : f32
+    }) : (tensor<256xf32>) -> f32
+    %36 = arith.addf %35, %cst_0 : f32
+    %37 = arith.divf %21, %cst_3 : tensor<1xf32>
+    %38 = arith.mulf %25, %cst_2 : tensor<256xf32>
+    %39 = tt.splat %28 : (f32) -> tensor<256xf32>
+    %40 = arith.subf %38, %39 : tensor<256xf32>
+    %41 = tt.splat %36 : (f32) -> tensor<256xf32>
+    %42 = arith.mulf %32, %41 : tensor<256xf32>
+    %43 = arith.subf %40, %42 : tensor<256xf32>
+    %44 = tt.broadcast %37 : (tensor<1xf32>) -> tensor<256xf32>
+    %45 = arith.mulf %44, %43 : tensor<256xf32>
+    %46 = arith.addf %24, %45 : tensor<256xf32>
+    tt.store %23, %46, %2 {cache = 1 : i32, evict = 1 : i32} : tensor<256xf32>
+    %47 = tt.splat %arg6 : (!tt.ptr<bf16, 1>) -> tensor<256x!tt.ptr<bf16, 1>>
+    %48 = tt.addptr %47, %5 : tensor<256x!tt.ptr<bf16, 1>>, tensor<256xi32>
+    %49 = arith.truncf %46 : tensor<256xf32> to tensor<256xbf16>
+    tt.store %48, %49, %2 {cache = 1 : i32, evict = 1 : i32} : tensor<256xbf16>
+    tt.return
+  }
+}

.triton/dump/397c6f2fc3ba128a214a60f646524724/triton_.llir

@@ -0,0 +1,132 @@
+; ModuleID = 'LLVMDialectModule'
+source_filename = "LLVMDialectModule"
+
+@global_smem = external addrspace(3) global [0 x i8]
+
+define void @triton__0d1d2d3de4e(ptr addrspace(1) %0, ptr addrspace(1) %1, ptr addrspace(1) %2, i32 %3, i32 %4) local_unnamed_addr !dbg !5 {
+  %6 = tail call i32 @llvm.nvvm.read.ptx.sreg.tid.x(), !dbg !8
+  %7 = and i32 %6, 63, !dbg !8
+  %8 = lshr i32 %6, 6, !dbg !9
+  %9 = and i32 %8, 3, !dbg !9
+  %10 = tail call i32 asm "mov.u32 $0, %ctaid.x;", "=r"() #3, !dbg !10
+  %11 = shl i32 %10, 6, !dbg !11
+  %12 = or i32 %11, %7, !dbg !12
+  br label %13, !dbg !13
+
+13:                                               ; preds = %5, %13
+  %14 = phi float [ 0.000000e+00, %5 ], [ %23, %13 ]
+  %15 = phi i32 [ 0, %5 ], [ %24, %13 ]
+  %16 = or i32 %15, %9, !dbg !14
+  %17 = shl i32 %16, 17, !dbg !15
+  %18 = add i32 %17, %12, !dbg !16
+  %19 = sext i32 %18 to i64, !dbg !17
+  %20 = getelementptr float, ptr addrspace(1) %0, i64 %19, !dbg !17
+  %21 = tail call i32 asm sideeffect "mov.u32 $0, 0x0;\0A\09@$2 ld.global.L1::evict_first.b32 { $0 }, [ $1 + 0 ];\0A\09@!$4 mov.u32 $0, $3;", "=r,l,b,r,b"(ptr addrspace(1) %20, i1 true, i32 0, i1 true) #3, !dbg !18
+  %22 = bitcast i32 %21 to float, !dbg !18
+  %23 = fadd float %14, %22, !dbg !19
+  %24 = add nuw nsw i32 %15, 4, !dbg !13
+  %25 = icmp ult i32 %15, 116, !dbg !13
+  br i1 %25, label %13, label %26, !dbg !13
+
+26:                                               ; preds = %13
+  %27 = shl nuw nsw i32 %7, 2, !dbg !20
+  %28 = or i32 %27, %9, !dbg !20
+  %29 = zext nneg i32 %28 to i64, !dbg !20
+  %30 = getelementptr float, ptr addrspace(3) @global_smem, i64 %29, !dbg !20
+  tail call void asm sideeffect "@$2 st.shared.b32 [ $0 + 0 ], $1;", "r,r,b"(ptr addrspace(3) %30, float %23, i1 true) #3, !dbg !20
+  tail call void @llvm.nvvm.barrier0(), !dbg !20
+  %31 = icmp slt i32 %6, 256, !dbg !20
+  %32 = sext i32 %6 to i64, !dbg !20
+  %33 = getelementptr float, ptr addrspace(3) @global_smem, i64 %32, !dbg !20
+  %34 = tail call float asm sideeffect "@$2 ld.shared.b32 $0, [ $1 + 0 ];", "=r,r,b"(ptr addrspace(3) %33, i1 %31) #3, !dbg !20
+  %35 = bitcast float %34 to i32, !dbg !20
+  %36 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %35, i32 2, i32 31), !dbg !20
+  %37 = bitcast i32 %36 to float, !dbg !20
+  %38 = fadd float %34, %37, !dbg !24
+  %39 = bitcast float %38 to i32, !dbg !20
+  %40 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %39, i32 1, i32 31), !dbg !20
+  %41 = bitcast i32 %40 to float, !dbg !20
+  %42 = fadd float %38, %41, !dbg !24
+  %43 = and i32 %6, 3, !dbg !20
+  %44 = icmp eq i32 %43, 0, !dbg !20
+  %45 = and i1 %31, %44, !dbg !20
+  tail call void asm sideeffect "@$2 st.shared.b32 [ $0 + 0 ], $1;", "r,r,b"(ptr addrspace(3) %33, float %42, i1 %45) #3, !dbg !20
+  tail call void @llvm.nvvm.barrier0(), !dbg !20
+  %46 = zext nneg i32 %27 to i64, !dbg !20
+  %47 = getelementptr float, ptr addrspace(3) @global_smem, i64 %46, !dbg !20
+  %48 = load float, ptr addrspace(3) %47, align 4, !dbg !20
+  %.frozen = freeze i32 %12
+  %49 = sdiv i32 %.frozen, 256, !dbg !28
+  %50 = mul i32 %49, 256
+  %.decomposed = sub i32 %.frozen, %50
+  %51 = sext i32 %49 to i64, !dbg !29
+  %52 = getelementptr i64, ptr addrspace(1) %1, i64 %51, !dbg !29
+  %53 = tail call i64 asm sideeffect "mov.u64 $0, 0x0;\0A\09@$2 ld.global.L1::evict_last.b64 { $0 }, [ $1 + 0 ];", "=l,l,b"(ptr addrspace(1) %52, i1 true) #3, !dbg !30
+  %54 = lshr i64 %53, 54, !dbg !31
+  %55 = and i64 %54, 512, !dbg !31
+  %56 = add i64 %55, %53, !dbg !31
+  %57 = shl i64 %56, 8, !dbg !32
+  %58 = sext i32 %.decomposed to i64, !dbg !33
+  %59 = getelementptr float, ptr addrspace(1) %2, i64 %57, !dbg !34
+  %60 = getelementptr float, ptr addrspace(1) %59, i64 %58, !dbg !34
+  %61 = icmp eq i32 %9, 0, !dbg !35
+  %62 = insertelement <1 x float> undef, float %48, i64 0, !dbg !35
+  %63 = tail call float asm sideeffect "mov.u32 $0, 0x0;\0A\09@$3 atom.global.gpu.acq_rel.add.f32 $0, [ $1 + 0 ], $2;", "=r,l,r,b"(ptr addrspace(1) %60, <1 x float> %62, i1 %61) #3, !dbg !35
+  ret void, !dbg !36
+}
+
+; Function Attrs: mustprogress nocallback nofree nosync nounwind speculatable willreturn memory(none)
+declare noundef i32 @llvm.nvvm.read.ptx.sreg.tid.x() #0
+
+; Function Attrs: convergent nocallback nounwind
+declare void @llvm.nvvm.barrier0() #1
+
+; Function Attrs: convergent nocallback nounwind memory(inaccessiblemem: readwrite)
+declare i32 @llvm.nvvm.shfl.sync.bfly.i32(i32, i32, i32, i32) #2
+
+attributes #0 = { mustprogress nocallback nofree nosync nounwind speculatable willreturn memory(none) }
+attributes #1 = { convergent nocallback nounwind }
+attributes #2 = { convergent nocallback nounwind memory(inaccessiblemem: readwrite) }
+attributes #3 = { nounwind }
+
+!llvm.module.flags = !{!0}
+!llvm.dbg.cu = !{!1}
+!nvvm.annotations = !{!3, !4, !4, !3}
+
+!0 = !{i32 2, !"Debug Info Version", i32 3}
+!1 = distinct !DICompileUnit(language: DW_LANG_C, file: !2, producer: "triton", isOptimized: true, runtimeVersion: 0, emissionKind: FullDebug)
+!2 = !DIFile(filename: "c6ik5vx7p22fpk4dcvh55zimw4t5nr5zn2b7inujxjauxshljumm.py", directory: "/tmp/torchinductor_root/6i")
+!3 = !{ptr @triton__0d1d2d3de4e, !"kernel", i32 1}
+!4 = !{ptr @triton__0d1d2d3de4e, !"maxntidx", i32 256}
+!5 = distinct !DISubprogram(name: "triton__0d1d2d3de4e", linkageName: "triton__0d1d2d3de4e", scope: !2, file: !2, line: 18, type: !6, scopeLine: 18, spFlags: DISPFlagDefinition | DISPFlagOptimized, unit: !1)
+!6 = !DISubroutineType(cc: DW_CC_normal, types: !7)
+!7 = !{}
+!8 = !DILocation(line: 22, column: 44, scope: !5)
+!9 = !DILocation(line: 24, column: 33, scope: !5)
+!10 = !DILocation(line: 21, column: 28, scope: !5)
+!11 = !DILocation(line: 21, column: 33, scope: !5)
+!12 = !DILocation(line: 22, column: 23, scope: !5)
+!13 = !DILocation(line: 27, column: 36, scope: !5)
+!14 = !DILocation(line: 28, column: 27, scope: !5)
+!15 = !DILocation(line: 31, column: 47, scope: !5)
+!16 = !DILocation(line: 31, column: 40, scope: !5)
+!17 = !DILocation(line: 31, column: 34, scope: !5)
+!18 = !DILocation(line: 31, column: 53, scope: !5)
+!19 = !DILocation(line: 34, column: 38, scope: !5)
+!20 = !DILocation(line: 243, column: 36, scope: !21, inlinedAt: !23)
+!21 = distinct !DILexicalBlockFile(scope: !5, file: !22, discriminator: 0)
+!22 = !DIFile(filename: "standard.py", directory: "/usr/local/lib/python3.10/dist-packages/triton/language")
+!23 = !DILocation(line: 35, column: 25, scope: !21)
+!24 = !DILocation(line: 233, column: 15, scope: !25, inlinedAt: !26)
+!25 = distinct !DILexicalBlockFile(scope: !21, file: !22, discriminator: 0)
+!26 = !DILocation(line: 243, column: 36, scope: !25, inlinedAt: !27)
+!27 = !DILocation(line: 35, column: 25, scope: !25)
+!28 = !DILocation(line: 36, column: 20, scope: !5)
+!29 = !DILocation(line: 38, column: 30, scope: !5)
+!30 = !DILocation(line: 38, column: 35, scope: !5)
+!31 = !DILocation(line: 41, column: 32, scope: !5)
+!32 = !DILocation(line: 45, column: 40, scope: !5)
+!33 = !DILocation(line: 45, column: 36, scope: !5)
+!34 = !DILocation(line: 45, column: 30, scope: !5)
+!35 = !DILocation(line: 45, column: 55, scope: !5)
+!36 = !DILocation(line: 45, column: 4, scope: !5)

.triton/dump/44b225411009956bfbae22f8bac7d703/triton_.llir

@@ -0,0 +1,304 @@
+; ModuleID = 'LLVMDialectModule'
+source_filename = "LLVMDialectModule"
+
+@global_smem = external addrspace(3) global [0 x i8]
+@.str = private unnamed_addr constant [11 x i8] c"__CUDA_FTZ\00", align 1
+
+define void @triton__0d1d2d3d4d5de6de(ptr addrspace(1) %0, ptr addrspace(1) %1, ptr addrspace(1) %2, ptr addrspace(1) %3, ptr addrspace(1) %4, i32 %5, i32 %6) local_unnamed_addr !dbg !7 {
+  %8 = tail call i32 @llvm.nvvm.read.ptx.sreg.tid.x(), !dbg !10
+  %9 = and i32 %8, 31, !dbg !10
+  %10 = lshr i32 %8, 5, !dbg !10
+  %11 = and i32 %10, 1, !dbg !10
+  %urem = shl i32 %8, 2, !dbg !10
+  %12 = and i32 %urem, 252, !dbg !10
+  %13 = tail call i32 asm "mov.u32 $0, %ctaid.x;", "=r"() #6, !dbg !11
+  %14 = shl i32 %13, 8, !dbg !12
+  %15 = or i32 %14, %12, !dbg !13
+  %16 = sext i32 %15 to i64, !dbg !14
+  %17 = getelementptr float, ptr addrspace(1) %0, i64 %16, !dbg !14
+  %18 = tail call { i32, i32, i32, i32 } asm sideeffect "mov.u32 $0, 0x0;\0A\09mov.u32 $1, 0x0;\0A\09mov.u32 $2, 0x0;\0A\09mov.u32 $3, 0x0;\0A\09@$5 ld.global.v4.b32 { $0, $1, $2, $3 }, [ $4 + 0 ];\0A\09@!$7 mov.u32 $0, $6;\0A\09@!$9 mov.u32 $1, $8;\0A\09@!$11 mov.u32 $2, $10;\0A\09@!$13 mov.u32 $3, $12;", "=r,=r,=r,=r,l,b,r,b,r,b,r,b,r,b"(ptr addrspace(1) %17, i1 true, i32 0, i1 true, i32 0, i1 true, i32 0, i1 true, i32 0, i1 true) #6, !dbg !15
+  %19 = extractvalue { i32, i32, i32, i32 } %18, 0, !dbg !15
+  %20 = extractvalue { i32, i32, i32, i32 } %18, 1, !dbg !15
+  %21 = extractvalue { i32, i32, i32, i32 } %18, 2, !dbg !15
+  %22 = extractvalue { i32, i32, i32, i32 } %18, 3, !dbg !15
+  %23 = bitcast i32 %21 to float, !dbg !15
+  %24 = bitcast i32 %22 to float, !dbg !15
+  %25 = getelementptr i16, ptr addrspace(1) %1, i64 %16, !dbg !16
+  %26 = tail call { i32, i32 } asm sideeffect "mov.u32 $0, 0x0;\0A\09mov.u32 $1, 0x0;\0A\09@$3 ld.global.v2.b32 { $0, $1 }, [ $2 + 0 ];\0A\09@!$5 mov.u32 $0, $4;\0A\09@!$7 mov.u32 $1, $6;", "=r,=r,l,b,r,b,r,b"(ptr addrspace(1) %25, i1 true, i32 0, i1 true, i32 0, i1 true) #6, !dbg !17
+  %27 = extractvalue { i32, i32 } %26, 0, !dbg !17
+  %28 = extractvalue { i32, i32 } %26, 1, !dbg !17
+  %29 = trunc i32 %27 to i16, !dbg !17
+  %extelt.offset = lshr i32 %27, 16, !dbg !17
+  %30 = trunc i32 %extelt.offset to i16, !dbg !17
+  %31 = trunc i32 %28 to i16, !dbg !17
+  %extelt.offset1 = lshr i32 %28, 16, !dbg !17
+  %32 = trunc i32 %extelt.offset1 to i16, !dbg !17
+  %33 = tail call float asm "cvt.f32.bf16 $0, $1;", "=r,h"(i16 %29) #6, !dbg !18
+  %34 = tail call float asm "cvt.f32.bf16 $0, $1;", "=r,h"(i16 %30) #6, !dbg !18
+  %35 = tail call float asm "cvt.f32.bf16 $0, $1;", "=r,h"(i16 %31) #6, !dbg !18
+  %36 = tail call float asm "cvt.f32.bf16 $0, $1;", "=r,h"(i16 %32) #6, !dbg !18
+  %37 = getelementptr i16, ptr addrspace(1) %2, i64 %16, !dbg !19
+  %38 = tail call { i32, i32 } asm sideeffect "mov.u32 $0, 0x0;\0A\09mov.u32 $1, 0x0;\0A\09@$3 ld.global.v2.b32 { $0, $1 }, [ $2 + 0 ];\0A\09@!$5 mov.u32 $0, $4;\0A\09@!$7 mov.u32 $1, $6;", "=r,=r,l,b,r,b,r,b"(ptr addrspace(1) %37, i1 true, i32 0, i1 true, i32 0, i1 true) #6, !dbg !20
+  %39 = extractvalue { i32, i32 } %38, 0, !dbg !20
+  %40 = extractvalue { i32, i32 } %38, 1, !dbg !20
+  %41 = trunc i32 %39 to i16, !dbg !20
+  %extelt.offset2 = lshr i32 %39, 16, !dbg !20
+  %42 = trunc i32 %extelt.offset2 to i16, !dbg !20
+  %43 = trunc i32 %40 to i16, !dbg !20
+  %extelt.offset3 = lshr i32 %40, 16, !dbg !20
+  %44 = trunc i32 %extelt.offset3 to i16, !dbg !20
+  %45 = tail call float asm "cvt.f32.bf16 $0, $1;", "=r,h"(i16 %41) #6, !dbg !21
+  %46 = tail call float asm "cvt.f32.bf16 $0, $1;", "=r,h"(i16 %42) #6, !dbg !21
+  %47 = tail call float asm "cvt.f32.bf16 $0, $1;", "=r,h"(i16 %43) #6, !dbg !21
+  %48 = tail call float asm "cvt.f32.bf16 $0, $1;", "=r,h"(i16 %44) #6, !dbg !21
+  %49 = zext nneg i32 %12 to i64, !dbg !22
+  %50 = getelementptr float, ptr addrspace(1) %3, i64 %49, !dbg !22
+  %51 = tail call { i32, i32, i32, i32 } asm sideeffect "mov.u32 $0, 0x0;\0A\09mov.u32 $1, 0x0;\0A\09mov.u32 $2, 0x0;\0A\09mov.u32 $3, 0x0;\0A\09@$5 ld.global.L1::evict_last.v4.b32 { $0, $1, $2, $3 }, [ $4 + 0 ];\0A\09@!$7 mov.u32 $0, $6;\0A\09@!$9 mov.u32 $1, $8;\0A\09@!$11 mov.u32 $2, $10;\0A\09@!$13 mov.u32 $3, $12;", "=r,=r,=r,=r,l,b,r,b,r,b,r,b,r,b"(ptr addrspace(1) %50, i1 true, i32 0, i1 true, i32 0, i1 true, i32 0, i1 true, i32 0, i1 true) #6, !dbg !23
+  %52 = fadd float %35, %23, !dbg !24
+  %53 = fadd float %36, %24, !dbg !24
+  %54 = insertelement <2 x i32> poison, i32 %19, i64 0, !dbg !15
+  %55 = insertelement <2 x i32> %54, i32 %20, i64 1, !dbg !15
+  %56 = bitcast <2 x i32> %55 to <2 x float>, !dbg !15
+  %57 = insertelement <2 x float> poison, float %33, i64 0, !dbg !24
+  %58 = insertelement <2 x float> %57, float %34, i64 1, !dbg !24
+  %59 = fadd <2 x float> %58, %56, !dbg !24
+  %60 = insertelement <2 x float> poison, float %45, i64 0, !dbg !25
+  %61 = insertelement <2 x float> %60, float %46, i64 1, !dbg !25
+  %62 = fadd <2 x float> %59, %61, !dbg !25
+  %63 = fadd float %52, %47, !dbg !25
+  %64 = fadd float %53, %48, !dbg !25
+  %65 = extractelement <2 x float> %62, i64 0, !dbg !26
+  %66 = extractelement <2 x float> %62, i64 1, !dbg !26
+  %67 = fadd float %65, %66, !dbg !26
+  %68 = fadd float %67, %63, !dbg !26
+  %69 = fadd float %68, %64, !dbg !26
+  %70 = bitcast float %69 to i32, !dbg !32
+  %71 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %70, i32 16, i32 31), !dbg !32
+  %72 = bitcast i32 %71 to float, !dbg !32
+  %73 = fadd float %69, %72, !dbg !26
+  %74 = bitcast float %73 to i32, !dbg !32
+  %75 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %74, i32 8, i32 31), !dbg !32
+  %76 = bitcast i32 %75 to float, !dbg !32
+  %77 = fadd float %73, %76, !dbg !26
+  %78 = bitcast float %77 to i32, !dbg !32
+  %79 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %78, i32 4, i32 31), !dbg !32
+  %80 = bitcast i32 %79 to float, !dbg !32
+  %81 = fadd float %77, %80, !dbg !26
+  %82 = bitcast float %81 to i32, !dbg !32
+  %83 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %82, i32 2, i32 31), !dbg !32
+  %84 = bitcast i32 %83 to float, !dbg !32
+  %85 = fadd float %81, %84, !dbg !26
+  %86 = bitcast float %85 to i32, !dbg !32
+  %87 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %86, i32 1, i32 31), !dbg !32
+  %88 = bitcast i32 %87 to float, !dbg !32
+  %89 = fadd float %85, %88, !dbg !26
+  %90 = icmp eq i32 %9, 0, !dbg !32
+  %91 = zext nneg i32 %11 to i64, !dbg !32
+  %92 = getelementptr float, ptr addrspace(3) @global_smem, i64 %91, !dbg !32
+  tail call void asm sideeffect "@$2 st.shared.b32 [ $0 + 0 ], $1;", "r,r,b"(ptr addrspace(3) %92, float %89, i1 %90) #6, !dbg !32
+  tail call void @llvm.nvvm.barrier0(), !dbg !32
+  %93 = icmp slt i32 %8, 2, !dbg !32
+  %94 = sext i32 %8 to i64, !dbg !32
+  %95 = getelementptr float, ptr addrspace(3) @global_smem, i64 %94, !dbg !32
+  %96 = tail call float asm sideeffect "@$2 ld.shared.b32 $0, [ $1 + 0 ];", "=r,r,b"(ptr addrspace(3) %95, i1 %93) #6, !dbg !32
+  %97 = bitcast float %96 to i32, !dbg !32
+  %98 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %97, i32 1, i32 31), !dbg !32
+  %99 = bitcast i32 %98 to float, !dbg !32
+  %100 = fadd float %96, %99, !dbg !26
+  %101 = and i32 %8, 1, !dbg !32
+  %102 = icmp eq i32 %101, 0, !dbg !32
+  %103 = and i1 %93, %102, !dbg !32
+  tail call void asm sideeffect "@$2 st.shared.b32 [ $0 + 0 ], $1;", "r,r,b"(ptr addrspace(3) %95, float %100, i1 %103) #6, !dbg !32
+  tail call void @llvm.nvvm.barrier0(), !dbg !32
+  %104 = load float, ptr addrspace(3) @global_smem, align 4, !dbg !32
+  %105 = fadd float %104, 0.000000e+00, !dbg !34
+  %106 = tail call float asm "div.full.f32 $0, $1, $2;", "=r,r,r"(float %105, float 2.560000e+02) #6, !dbg !38
+  %107 = fsub float %65, %106, !dbg !39
+  %108 = fsub float %66, %106, !dbg !39
+  %109 = fsub float %63, %106, !dbg !39
+  %110 = fsub float %64, %106, !dbg !39
+  %111 = fmul float %107, %107, !dbg !40
+  %112 = fmul float %108, %108, !dbg !40
+  %113 = fmul float %109, %109, !dbg !40
+  %114 = fmul float %110, %110, !dbg !40
+  tail call void @llvm.nvvm.barrier0(), !dbg !41
+  %115 = fadd float %111, %112, !dbg !43
+  %116 = fadd float %113, %115, !dbg !43
+  %117 = fadd float %114, %116, !dbg !43
+  %118 = bitcast float %117 to i32, !dbg !41
+  %119 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %118, i32 16, i32 31), !dbg !41
+  %120 = bitcast i32 %119 to float, !dbg !41
+  %121 = fadd float %117, %120, !dbg !43
+  %122 = bitcast float %121 to i32, !dbg !41
+  %123 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %122, i32 8, i32 31), !dbg !41
+  %124 = bitcast i32 %123 to float, !dbg !41
+  %125 = fadd float %121, %124, !dbg !43
+  %126 = bitcast float %125 to i32, !dbg !41
+  %127 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %126, i32 4, i32 31), !dbg !41
+  %128 = bitcast i32 %127 to float, !dbg !41
+  %129 = fadd float %125, %128, !dbg !43
+  %130 = bitcast float %129 to i32, !dbg !41
+  %131 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %130, i32 2, i32 31), !dbg !41
+  %132 = bitcast i32 %131 to float, !dbg !41
+  %133 = fadd float %129, %132, !dbg !43
+  %134 = bitcast float %133 to i32, !dbg !41
+  %135 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %134, i32 1, i32 31), !dbg !41
+  %136 = bitcast i32 %135 to float, !dbg !41
+  %137 = fadd float %133, %136, !dbg !43
+  tail call void asm sideeffect "@$2 st.shared.b32 [ $0 + 0 ], $1;", "r,r,b"(ptr addrspace(3) %92, float %137, i1 %90) #6, !dbg !41
+  tail call void @llvm.nvvm.barrier0(), !dbg !41
+  %138 = tail call float asm sideeffect "@$2 ld.shared.b32 $0, [ $1 + 0 ];", "=r,r,b"(ptr addrspace(3) %95, i1 %93) #6, !dbg !41
+  %139 = bitcast float %138 to i32, !dbg !41
+  %140 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %139, i32 1, i32 31), !dbg !41
+  %141 = bitcast i32 %140 to float, !dbg !41
+  %142 = fadd float %138, %141, !dbg !43
+  tail call void asm sideeffect "@$2 st.shared.b32 [ $0 + 0 ], $1;", "r,r,b"(ptr addrspace(3) %95, float %142, i1 %103) #6, !dbg !41
+  tail call void @llvm.nvvm.barrier0(), !dbg !41
+  %143 = load float, ptr addrspace(3) @global_smem, align 4, !dbg !41
+  %144 = fadd float %143, 0.000000e+00, !dbg !46
+  %145 = tail call float asm "div.full.f32 $0, $1, $2;", "=r,r,r"(float %144, float 2.560000e+02) #6, !dbg !48
+  %146 = fadd float %145, 0x3EE4F8B580000000, !dbg !49
+  %147 = tail call i32 @__nvvm_reflect(ptr nonnull @.str) #6, !dbg !50
+  %.not.i = icmp eq i32 %147, 0, !dbg !50
+  br i1 %.not.i, label %150, label %148, !dbg !50
+
+148:                                              ; preds = %7
+  %149 = tail call float @llvm.nvvm.rsqrt.approx.ftz.f(float %146), !dbg !50
+  br label %__nv_rsqrtf.exit, !dbg !50
+
+150:                                              ; preds = %7
+  %151 = tail call float @llvm.nvvm.rsqrt.approx.f(float %146), !dbg !50
+  br label %__nv_rsqrtf.exit, !dbg !50
+
+__nv_rsqrtf.exit:                                 ; preds = %148, %150
+  %.0.i = phi float [ %149, %148 ], [ %151, %150 ], !dbg !50
+  %152 = extractvalue { i32, i32, i32, i32 } %51, 3, !dbg !23
+  %153 = bitcast i32 %152 to float, !dbg !23
+  %154 = extractvalue { i32, i32, i32, i32 } %51, 2, !dbg !23
+  %155 = bitcast i32 %154 to float, !dbg !23
+  %156 = extractvalue { i32, i32, i32, i32 } %51, 1, !dbg !23
+  %157 = bitcast i32 %156 to float, !dbg !23
+  %158 = extractvalue { i32, i32, i32, i32 } %51, 0, !dbg !23
+  %159 = bitcast i32 %158 to float, !dbg !23
+  %160 = fmul float %107, %.0.i, !dbg !51
+  %161 = fmul float %108, %.0.i, !dbg !51
+  %162 = fmul float %109, %.0.i, !dbg !51
+  %163 = fmul float %110, %.0.i, !dbg !51
+  %164 = fmul float %160, %159, !dbg !52
+  %165 = fmul float %161, %157, !dbg !52
+  %166 = fmul float %162, %155, !dbg !52
+  %167 = fmul float %163, %153, !dbg !52
+  %168 = getelementptr float, ptr addrspace(1) %4, i64 %16, !dbg !53
+  %169 = bitcast float %164 to i32, !dbg !54
+  %170 = bitcast float %165 to i32, !dbg !54
+  %171 = bitcast float %166 to i32, !dbg !54
+  %172 = bitcast float %167 to i32, !dbg !54
+  tail call void asm sideeffect "@$5 st.global.v4.b32 [ $4 + 0 ], { $0, $1, $2, $3 };", "r,r,r,r,l,b"(i32 %169, i32 %170, i32 %171, i32 %172, ptr addrspace(1) %168, i1 true) #6, !dbg !54
+  ret void, !dbg !55
+}
+
+; Function Attrs: mustprogress nocallback nofree nosync nounwind speculatable willreturn memory(none)
+declare noundef i32 @llvm.nvvm.read.ptx.sreg.tid.x() #0
+
+; Function Attrs: convergent nocallback nounwind memory(inaccessiblemem: readwrite)
+declare i32 @llvm.nvvm.shfl.sync.bfly.i32(i32, i32, i32, i32) #1
+
+; Function Attrs: convergent nocallback nounwind
+declare void @llvm.nvvm.barrier0() #2
+
+; Function Attrs: alwaysinline nounwind
+define float @__nv_rsqrtf(float %x) local_unnamed_addr #3 {
+  %1 = tail call i32 @__nvvm_reflect(ptr nonnull @.str) #6
+  %.not = icmp eq i32 %1, 0
+  br i1 %.not, label %4, label %2
+
+2:                                                ; preds = %0
+  %3 = tail call float @llvm.nvvm.rsqrt.approx.ftz.f(float %x)
+  br label %6
+
+4:                                                ; preds = %0
+  %5 = tail call float @llvm.nvvm.rsqrt.approx.f(float %x)
+  br label %6
+
+6:                                                ; preds = %4, %2
+  %.0 = phi float [ %3, %2 ], [ %5, %4 ]
+  ret float %.0
+}
+
+declare i32 @__nvvm_reflect(ptr) local_unnamed_addr #4
+
+; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(none)
+declare float @llvm.nvvm.rsqrt.approx.ftz.f(float) #5
+
+; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(none)
+declare float @llvm.nvvm.rsqrt.approx.f(float) #5
+
+attributes #0 = { mustprogress nocallback nofree nosync nounwind speculatable willreturn memory(none) }
+attributes #1 = { convergent nocallback nounwind memory(inaccessiblemem: readwrite) }
+attributes #2 = { convergent nocallback nounwind }
+attributes #3 = { alwaysinline nounwind "disable-tail-calls"="false" "frame-pointer"="all" "less-precise-fpmad"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #4 = { "disable-tail-calls"="false" "frame-pointer"="all" "less-precise-fpmad"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #5 = { mustprogress nocallback nofree nosync nounwind willreturn memory(none) }
+attributes #6 = { nounwind }
+
+!llvm.module.flags = !{!0, !1}
+!llvm.dbg.cu = !{!2}
+!nvvm.annotations = !{!4, !5, !5, !4}
+!llvm.ident = !{!6}
+
+!0 = !{i32 2, !"Debug Info Version", i32 3}
+!1 = !{i32 4, !"nvvm-reflect-ftz", i32 1}
+!2 = distinct !DICompileUnit(language: DW_LANG_C, file: !3, producer: "triton", isOptimized: true, runtimeVersion: 0, emissionKind: FullDebug)
+!3 = !DIFile(filename: "cpedrbcgvftrmo3x6vfpo6dhkxbweq3ucfj5jibyyvr3hf67gsvx.py", directory: "/tmp/torchinductor_root/pe")
+!4 = !{ptr @triton__0d1d2d3d4d5de6de, !"kernel", i32 1}
+!5 = !{ptr @triton__0d1d2d3d4d5de6de, !"maxntidx", i32 64}
+!6 = !{!"clang version 3.8.0 (tags/RELEASE_380/final)"}
+!7 = distinct !DISubprogram(name: "triton__0d1d2d3d4d5de6de", linkageName: "triton__0d1d2d3d4d5de6de", scope: !3, file: !3, line: 18, type: !8, scopeLine: 18, spFlags: DISPFlagDefinition | DISPFlagOptimized, unit: !2)
+!8 = !DISubroutineType(cc: DW_CC_normal, types: !9)
+!9 = !{}
+!10 = !DILocation(line: 26, column: 26, scope: !7)
+!11 = !DILocation(line: 23, column: 28, scope: !7)
+!12 = !DILocation(line: 30, column: 40, scope: !7)
+!13 = !DILocation(line: 30, column: 36, scope: !7)
+!14 = !DILocation(line: 30, column: 30, scope: !7)
+!15 = !DILocation(line: 30, column: 46, scope: !7)
+!16 = !DILocation(line: 31, column: 30, scope: !7)
+!17 = !DILocation(line: 31, column: 46, scope: !7)
+!18 = !DILocation(line: 31, column: 67, scope: !7)
+!19 = !DILocation(line: 32, column: 30, scope: !7)
+!20 = !DILocation(line: 32, column: 46, scope: !7)
+!21 = !DILocation(line: 32, column: 67, scope: !7)
+!22 = !DILocation(line: 33, column: 31, scope: !7)
+!23 = !DILocation(line: 33, column: 36, scope: !7)
+!24 = !DILocation(line: 35, column: 18, scope: !7)
+!25 = !DILocation(line: 37, column: 18, scope: !7)
+!26 = !DILocation(line: 233, column: 15, scope: !27, inlinedAt: !30)
+!27 = distinct !DILexicalBlockFile(scope: !29, file: !28, discriminator: 0)
+!28 = !DIFile(filename: "standard.py", directory: "/usr/local/lib/python3.10/dist-packages/triton/language")
+!29 = distinct !DILexicalBlockFile(scope: !7, file: !28, discriminator: 0)
+!30 = !DILocation(line: 243, column: 36, scope: !27, inlinedAt: !31)
+!31 = !DILocation(line: 42, column: 59, scope: !27)
+!32 = !DILocation(line: 243, column: 36, scope: !29, inlinedAt: !33)
+!33 = !DILocation(line: 42, column: 59, scope: !29)
+!34 = !DILocation(line: 8, column: 15, scope: !35, inlinedAt: !37)
+!35 = distinct !DILexicalBlockFile(scope: !7, file: !36, discriminator: 0)
+!36 = !DIFile(filename: "triton_helpers.py", directory: "/usr/local/lib/python3.10/dist-packages/torch/_inductor")
+!37 = !DILocation(line: 42, column: 45, scope: !35)
+!38 = !DILocation(line: 45, column: 20, scope: !7)
+!39 = !DILocation(line: 46, column: 19, scope: !7)
+!40 = !DILocation(line: 47, column: 20, scope: !7)
+!41 = !DILocation(line: 243, column: 36, scope: !29, inlinedAt: !42)
+!42 = !DILocation(line: 50, column: 59, scope: !29)
+!43 = !DILocation(line: 233, column: 15, scope: !27, inlinedAt: !44)
+!44 = !DILocation(line: 243, column: 36, scope: !27, inlinedAt: !45)
+!45 = !DILocation(line: 50, column: 59, scope: !27)
+!46 = !DILocation(line: 8, column: 15, scope: !35, inlinedAt: !47)
+!47 = !DILocation(line: 50, column: 45, scope: !35)
+!48 = !DILocation(line: 53, column: 20, scope: !7)
+!49 = !DILocation(line: 55, column: 20, scope: !7)
+!50 = !DILocation(line: 56, column: 26, scope: !7)
+!51 = !DILocation(line: 57, column: 20, scope: !7)
+!52 = !DILocation(line: 58, column: 20, scope: !7)
+!53 = !DILocation(line: 59, column: 25, scope: !7)
+!54 = !DILocation(line: 59, column: 48, scope: !7)
+!55 = !DILocation(line: 59, column: 4, scope: !7)

.triton/dump/44b225411009956bfbae22f8bac7d703/triton_.ttgir

@@ -0,0 +1,62 @@
+#blocked = #triton_gpu.blocked<{sizePerThread = [4], threadsPerWarp = [32], warpsPerCTA = [2], order = [0], CTAsPerCGA = [1], CTASplitNum = [1], CTAOrder = [0]}>
+module attributes {"triton_gpu.compute-capability" = 89 : i32, "triton_gpu.num-ctas" = 1 : i32, "triton_gpu.num-warps" = 2 : i32, "triton_gpu.threads-per-warp" = 32 : i32} {
+  tt.func public @triton__0d1d2d3d4d5de6de(%arg0: !tt.ptr<f32, 1> {tt.divisibility = 16 : i32}, %arg1: !tt.ptr<bf16, 1> {tt.divisibility = 16 : i32}, %arg2: !tt.ptr<bf16, 1> {tt.divisibility = 16 : i32}, %arg3: !tt.ptr<f32, 1> {tt.divisibility = 16 : i32}, %arg4: !tt.ptr<f32, 1> {tt.divisibility = 16 : i32}, %arg5: i32 {tt.divisibility = 16 : i32, tt.max_divisibility = 16 : i32}, %arg6: i32 {tt.divisibility = 16 : i32, tt.max_divisibility = 16 : i32}) attributes {noinline = false} {
+    %cst = arith.constant dense<256> : tensor<256xi32, #blocked>
+    %cst_0 = arith.constant 9.99999974E-6 : f32
+    %cst_1 = arith.constant 2.560000e+02 : f32
+    %cst_2 = arith.constant 0.000000e+00 : f32
+    %c256_i32 = arith.constant 256 : i32
+    %cst_3 = arith.constant dense<0.000000e+00> : tensor<256xf32, #blocked>
+    %cst_4 = arith.constant dense<0.000000e+00> : tensor<256xbf16, #blocked>
+    %0 = tt.get_program_id x : i32
+    %1 = tt.make_range {end = 256 : i32, start = 0 : i32} : tensor<256xi32, #blocked>
+    %2 = arith.cmpi slt, %1, %cst : tensor<256xi32, #blocked>
+    %3 = arith.muli %0, %c256_i32 : i32
+    %4 = tt.splat %3 : (i32) -> tensor<256xi32, #blocked>
+    %5 = arith.addi %1, %4 : tensor<256xi32, #blocked>
+    %6 = tt.splat %arg0 : (!tt.ptr<f32, 1>) -> tensor<256x!tt.ptr<f32, 1>, #blocked>
+    %7 = tt.addptr %6, %5 : tensor<256x!tt.ptr<f32, 1>, #blocked>, tensor<256xi32, #blocked>
+    %8 = tt.load %7, %2, %cst_3 {cache = 1 : i32, evict = 1 : i32, isVolatile = false} : tensor<256xf32, #blocked>
+    %9 = tt.splat %arg1 : (!tt.ptr<bf16, 1>) -> tensor<256x!tt.ptr<bf16, 1>, #blocked>
+    %10 = tt.addptr %9, %5 : tensor<256x!tt.ptr<bf16, 1>, #blocked>, tensor<256xi32, #blocked>
+    %11 = tt.load %10, %2, %cst_4 {cache = 1 : i32, evict = 1 : i32, isVolatile = false} : tensor<256xbf16, #blocked>
+    %12 = arith.extf %11 : tensor<256xbf16, #blocked> to tensor<256xf32, #blocked>
+    %13 = tt.splat %arg2 : (!tt.ptr<bf16, 1>) -> tensor<256x!tt.ptr<bf16, 1>, #blocked>
+    %14 = tt.addptr %13, %5 : tensor<256x!tt.ptr<bf16, 1>, #blocked>, tensor<256xi32, #blocked>
+    %15 = tt.load %14, %2, %cst_4 {cache = 1 : i32, evict = 1 : i32, isVolatile = false} : tensor<256xbf16, #blocked>
+    %16 = arith.extf %15 : tensor<256xbf16, #blocked> to tensor<256xf32, #blocked>
+    %17 = tt.splat %arg3 : (!tt.ptr<f32, 1>) -> tensor<256x!tt.ptr<f32, 1>, #blocked>
+    %18 = tt.addptr %17, %1 : tensor<256x!tt.ptr<f32, 1>, #blocked>, tensor<256xi32, #blocked>
+    %19 = tt.load %18, %2, %cst_3 {cache = 1 : i32, evict = 3 : i32, isVolatile = false} : tensor<256xf32, #blocked>
+    %20 = arith.addf %8, %12 : tensor<256xf32, #blocked>
+    %21 = arith.addf %20, %16 : tensor<256xf32, #blocked>
+    %22 = arith.select %2, %21, %cst_3 : tensor<256xi1, #blocked>, tensor<256xf32, #blocked>
+    %23 = "tt.reduce"(%22) <{axis = 0 : i32}> ({
+    ^bb0(%arg7: f32, %arg8: f32):
+      %40 = arith.addf %arg7, %arg8 : f32
+      tt.reduce.return %40 : f32
+    }) : (tensor<256xf32, #blocked>) -> f32
+    %24 = arith.addf %23, %cst_2 : f32
+    %25 = arith.divf %24, %cst_1 : f32
+    %26 = tt.splat %25 : (f32) -> tensor<256xf32, #blocked>
+    %27 = arith.subf %21, %26 : tensor<256xf32, #blocked>
+    %28 = arith.mulf %27, %27 : tensor<256xf32, #blocked>
+    %29 = arith.select %2, %28, %cst_3 : tensor<256xi1, #blocked>, tensor<256xf32, #blocked>
+    %30 = "tt.reduce"(%29) <{axis = 0 : i32}> ({
+    ^bb0(%arg7: f32, %arg8: f32):
+      %40 = arith.addf %arg7, %arg8 : f32
+      tt.reduce.return %40 : f32
+    }) : (tensor<256xf32, #blocked>) -> f32
+    %31 = arith.addf %30, %cst_2 : f32
+    %32 = arith.divf %31, %cst_1 : f32
+    %33 = arith.addf %32, %cst_0 : f32
+    %34 = tt.extern_elementwise %33 {libname = "libdevice", libpath = "/usr/local/lib/python3.10/dist-packages/triton/language/../third_party/cuda/lib/libdevice.10.bc", pure = true, symbol = "__nv_rsqrtf"} : (f32) -> f32
+    %35 = tt.splat %34 : (f32) -> tensor<256xf32, #blocked>
+    %36 = arith.mulf %27, %35 : tensor<256xf32, #blocked>
+    %37 = arith.mulf %36, %19 : tensor<256xf32, #blocked>
+    %38 = tt.splat %arg4 : (!tt.ptr<f32, 1>) -> tensor<256x!tt.ptr<f32, 1>, #blocked>
+    %39 = tt.addptr %38, %5 : tensor<256x!tt.ptr<f32, 1>, #blocked>, tensor<256xi32, #blocked>
+    tt.store %39, %37, %2 {cache = 1 : i32, evict = 1 : i32} : tensor<256xf32, #blocked>
+    tt.return
+  }
+}

.triton/dump/44b225411009956bfbae22f8bac7d703/triton_.ttir

@@ -0,0 +1,61 @@
+module {
+  tt.func public @triton__0d1d2d3d4d5de6de(%arg0: !tt.ptr<f32, 1> {tt.divisibility = 16 : i32}, %arg1: !tt.ptr<bf16, 1> {tt.divisibility = 16 : i32}, %arg2: !tt.ptr<bf16, 1> {tt.divisibility = 16 : i32}, %arg3: !tt.ptr<f32, 1> {tt.divisibility = 16 : i32}, %arg4: !tt.ptr<f32, 1> {tt.divisibility = 16 : i32}, %arg5: i32 {tt.divisibility = 16 : i32, tt.max_divisibility = 16 : i32}, %arg6: i32 {tt.divisibility = 16 : i32, tt.max_divisibility = 16 : i32}) attributes {noinline = false} {
+    %c256_i32 = arith.constant 256 : i32
+    %cst = arith.constant dense<0.000000e+00> : tensor<256xbf16>
+    %cst_0 = arith.constant 0.000000e+00 : f32
+    %cst_1 = arith.constant 2.560000e+02 : f32
+    %cst_2 = arith.constant 9.99999974E-6 : f32
+    %cst_3 = arith.constant dense<0.000000e+00> : tensor<256xf32>
+    %cst_4 = arith.constant dense<256> : tensor<256xi32>
+    %0 = tt.get_program_id x : i32
+    %1 = tt.make_range {end = 256 : i32, start = 0 : i32} : tensor<256xi32>
+    %2 = arith.cmpi slt, %1, %cst_4 : tensor<256xi32>
+    %3 = arith.muli %0, %c256_i32 : i32
+    %4 = tt.splat %3 : (i32) -> tensor<256xi32>
+    %5 = arith.addi %1, %4 : tensor<256xi32>
+    %6 = tt.splat %arg0 : (!tt.ptr<f32, 1>) -> tensor<256x!tt.ptr<f32, 1>>
+    %7 = tt.addptr %6, %5 : tensor<256x!tt.ptr<f32, 1>>, tensor<256xi32>
+    %8 = tt.load %7, %2, %cst_3 {cache = 1 : i32, evict = 1 : i32, isVolatile = false} : tensor<256xf32>
+    %9 = tt.splat %arg1 : (!tt.ptr<bf16, 1>) -> tensor<256x!tt.ptr<bf16, 1>>
+    %10 = tt.addptr %9, %5 : tensor<256x!tt.ptr<bf16, 1>>, tensor<256xi32>
+    %11 = tt.load %10, %2, %cst {cache = 1 : i32, evict = 1 : i32, isVolatile = false} : tensor<256xbf16>
+    %12 = arith.extf %11 : tensor<256xbf16> to tensor<256xf32>
+    %13 = tt.splat %arg2 : (!tt.ptr<bf16, 1>) -> tensor<256x!tt.ptr<bf16, 1>>
+    %14 = tt.addptr %13, %5 : tensor<256x!tt.ptr<bf16, 1>>, tensor<256xi32>
+    %15 = tt.load %14, %2, %cst {cache = 1 : i32, evict = 1 : i32, isVolatile = false} : tensor<256xbf16>
+    %16 = arith.extf %15 : tensor<256xbf16> to tensor<256xf32>
+    %17 = tt.splat %arg3 : (!tt.ptr<f32, 1>) -> tensor<256x!tt.ptr<f32, 1>>
+    %18 = tt.addptr %17, %1 : tensor<256x!tt.ptr<f32, 1>>, tensor<256xi32>
+    %19 = tt.load %18, %2, %cst_3 {cache = 1 : i32, evict = 3 : i32, isVolatile = false} : tensor<256xf32>
+    %20 = arith.addf %8, %12 : tensor<256xf32>
+    %21 = arith.addf %20, %16 : tensor<256xf32>
+    %22 = arith.select %2, %21, %cst_3 : tensor<256xi1>, tensor<256xf32>
+    %23 = "tt.reduce"(%22) <{axis = 0 : i32}> ({
+    ^bb0(%arg7: f32, %arg8: f32):
+      %40 = arith.addf %arg7, %arg8 : f32
+      tt.reduce.return %40 : f32
+    }) : (tensor<256xf32>) -> f32
+    %24 = arith.addf %23, %cst_0 : f32
+    %25 = arith.divf %24, %cst_1 : f32
+    %26 = tt.splat %25 : (f32) -> tensor<256xf32>
+    %27 = arith.subf %21, %26 : tensor<256xf32>
+    %28 = arith.mulf %27, %27 : tensor<256xf32>
+    %29 = arith.select %2, %28, %cst_3 : tensor<256xi1>, tensor<256xf32>
+    %30 = "tt.reduce"(%29) <{axis = 0 : i32}> ({
+    ^bb0(%arg7: f32, %arg8: f32):
+      %40 = arith.addf %arg7, %arg8 : f32
+      tt.reduce.return %40 : f32
+    }) : (tensor<256xf32>) -> f32
+    %31 = arith.addf %30, %cst_0 : f32
+    %32 = arith.divf %31, %cst_1 : f32
+    %33 = arith.addf %32, %cst_2 : f32
+    %34 = tt.extern_elementwise %33 {libname = "libdevice", libpath = "/usr/local/lib/python3.10/dist-packages/triton/language/../third_party/cuda/lib/libdevice.10.bc", pure = true, symbol = "__nv_rsqrtf"} : (f32) -> f32
+    %35 = tt.splat %34 : (f32) -> tensor<256xf32>
+    %36 = arith.mulf %27, %35 : tensor<256xf32>
+    %37 = arith.mulf %36, %19 : tensor<256xf32>
+    %38 = tt.splat %arg4 : (!tt.ptr<f32, 1>) -> tensor<256x!tt.ptr<f32, 1>>
+    %39 = tt.addptr %38, %5 : tensor<256x!tt.ptr<f32, 1>>, tensor<256xi32>
+    tt.store %39, %37, %2 {cache = 1 : i32, evict = 1 : i32} : tensor<256xf32>
+    tt.return
+  }
+}

.triton/dump/4a587ee49c44b4c47e51f28541749625/triton_.llir

@@ -0,0 +1,213 @@
+; ModuleID = 'LLVMDialectModule'
+source_filename = "LLVMDialectModule"
+
+define void @triton__0d1d2d3d4de(ptr addrspace(1) %0, ptr addrspace(1) %1, ptr addrspace(1) %2, ptr addrspace(1) %3, i32 %4) local_unnamed_addr !dbg !5 {
+  %6 = tail call i32 @llvm.nvvm.read.ptx.sreg.tid.x(), !dbg !8
+  %7 = shl i32 %6, 3, !dbg !8
+  %8 = and i32 %7, 1016, !dbg !8
+  %9 = tail call i32 asm "mov.u32 $0, %ctaid.x;", "=r"() #1, !dbg !9
+  %10 = shl i32 %9, 10, !dbg !10
+  %11 = or i32 %10, %8, !dbg !11
+  %.frozen = freeze i32 %11
+  %12 = sdiv i32 %.frozen, 256, !dbg !12
+  %13 = srem i32 %12, 3, !dbg !13
+  %14 = mul i32 %12, 256
+  %.decomposed = sub i32 %.frozen, %14
+  %15 = sdiv i32 %11, 768, !dbg !14
+  %16 = shl nsw i32 %15, 8, !dbg !15
+  %17 = add nsw i32 %16, %.decomposed, !dbg !16
+  %18 = sext i32 %17 to i64, !dbg !17
+  %19 = getelementptr i16, ptr addrspace(1) %0, i64 %18, !dbg !17
+  %20 = tail call { i32, i32, i32, i32 } asm sideeffect "mov.u32 $0, 0x0;\0A\09mov.u32 $1, 0x0;\0A\09mov.u32 $2, 0x0;\0A\09mov.u32 $3, 0x0;\0A\09@$5 ld.global.L1::evict_last.v4.b32 { $0, $1, $2, $3 }, [ $4 + 0 ];", "=r,=r,=r,=r,l,b"(ptr addrspace(1) %19, i1 true) #1, !dbg !18
+  %21 = extractvalue { i32, i32, i32, i32 } %20, 0, !dbg !18
+  %22 = extractvalue { i32, i32, i32, i32 } %20, 1, !dbg !18
+  %23 = extractvalue { i32, i32, i32, i32 } %20, 2, !dbg !18
+  %24 = extractvalue { i32, i32, i32, i32 } %20, 3, !dbg !18
+  %25 = trunc i32 %21 to i16, !dbg !18
+  %extelt.offset = lshr i32 %21, 16, !dbg !18
+  %26 = trunc i32 %extelt.offset to i16, !dbg !18
+  %27 = trunc i32 %22 to i16, !dbg !18
+  %extelt.offset1 = lshr i32 %22, 16, !dbg !18
+  %28 = trunc i32 %extelt.offset1 to i16, !dbg !18
+  %29 = trunc i32 %23 to i16, !dbg !18
+  %extelt.offset2 = lshr i32 %23, 16, !dbg !18
+  %30 = trunc i32 %extelt.offset2 to i16, !dbg !18
+  %31 = trunc i32 %24 to i16, !dbg !18
+  %extelt.offset3 = lshr i32 %24, 16, !dbg !18
+  %32 = trunc i32 %extelt.offset3 to i16, !dbg !18
+  %33 = tail call float asm "cvt.f32.bf16 $0, $1;", "=r,h"(i16 %25) #1, !dbg !19
+  %34 = tail call float asm "cvt.f32.bf16 $0, $1;", "=r,h"(i16 %26) #1, !dbg !19
+  %35 = tail call float asm "cvt.f32.bf16 $0, $1;", "=r,h"(i16 %27) #1, !dbg !19
+  %36 = tail call float asm "cvt.f32.bf16 $0, $1;", "=r,h"(i16 %28) #1, !dbg !19
+  %37 = tail call float asm "cvt.f32.bf16 $0, $1;", "=r,h"(i16 %29) #1, !dbg !19
+  %38 = tail call float asm "cvt.f32.bf16 $0, $1;", "=r,h"(i16 %30) #1, !dbg !19
+  %39 = tail call float asm "cvt.f32.bf16 $0, $1;", "=r,h"(i16 %31) #1, !dbg !19
+  %40 = tail call float asm "cvt.f32.bf16 $0, $1;", "=r,h"(i16 %32) #1, !dbg !19
+  %41 = getelementptr i16, ptr addrspace(1) %1, i64 %18, !dbg !20
+  %42 = tail call { i32, i32, i32, i32 } asm sideeffect "mov.u32 $0, 0x0;\0A\09mov.u32 $1, 0x0;\0A\09mov.u32 $2, 0x0;\0A\09mov.u32 $3, 0x0;\0A\09@$5 ld.global.L1::evict_last.v4.b32 { $0, $1, $2, $3 }, [ $4 + 0 ];", "=r,=r,=r,=r,l,b"(ptr addrspace(1) %41, i1 true) #1, !dbg !21
+  %43 = extractvalue { i32, i32, i32, i32 } %42, 0, !dbg !21
+  %44 = extractvalue { i32, i32, i32, i32 } %42, 1, !dbg !21
+  %45 = extractvalue { i32, i32, i32, i32 } %42, 2, !dbg !21
+  %46 = extractvalue { i32, i32, i32, i32 } %42, 3, !dbg !21
+  %47 = trunc i32 %43 to i16, !dbg !21
+  %extelt.offset4 = lshr i32 %43, 16, !dbg !21
+  %48 = trunc i32 %extelt.offset4 to i16, !dbg !21
+  %49 = trunc i32 %44 to i16, !dbg !21
+  %extelt.offset5 = lshr i32 %44, 16, !dbg !21
+  %50 = trunc i32 %extelt.offset5 to i16, !dbg !21
+  %51 = trunc i32 %45 to i16, !dbg !21
+  %extelt.offset6 = lshr i32 %45, 16, !dbg !21
+  %52 = trunc i32 %extelt.offset6 to i16, !dbg !21
+  %53 = trunc i32 %46 to i16, !dbg !21
+  %extelt.offset7 = lshr i32 %46, 16, !dbg !21
+  %54 = trunc i32 %extelt.offset7 to i16, !dbg !21
+  %55 = tail call float asm "cvt.f32.bf16 $0, $1;", "=r,h"(i16 %47) #1, !dbg !22
+  %56 = tail call float asm "cvt.f32.bf16 $0, $1;", "=r,h"(i16 %48) #1, !dbg !22
+  %57 = tail call float asm "cvt.f32.bf16 $0, $1;", "=r,h"(i16 %49) #1, !dbg !22
+  %58 = tail call float asm "cvt.f32.bf16 $0, $1;", "=r,h"(i16 %50) #1, !dbg !22
+  %59 = tail call float asm "cvt.f32.bf16 $0, $1;", "=r,h"(i16 %51) #1, !dbg !22
+  %60 = tail call float asm "cvt.f32.bf16 $0, $1;", "=r,h"(i16 %52) #1, !dbg !22
+  %61 = tail call float asm "cvt.f32.bf16 $0, $1;", "=r,h"(i16 %53) #1, !dbg !22
+  %62 = tail call float asm "cvt.f32.bf16 $0, $1;", "=r,h"(i16 %54) #1, !dbg !22
+  %63 = getelementptr i16, ptr addrspace(1) %2, i64 %18, !dbg !23
+  %64 = tail call { i32, i32, i32, i32 } asm sideeffect "mov.u32 $0, 0x0;\0A\09mov.u32 $1, 0x0;\0A\09mov.u32 $2, 0x0;\0A\09mov.u32 $3, 0x0;\0A\09@$5 ld.global.L1::evict_last.v4.b32 { $0, $1, $2, $3 }, [ $4 + 0 ];", "=r,=r,=r,=r,l,b"(ptr addrspace(1) %63, i1 true) #1, !dbg !24
+  %65 = extractvalue { i32, i32, i32, i32 } %64, 0, !dbg !24
+  %66 = extractvalue { i32, i32, i32, i32 } %64, 1, !dbg !24
+  %67 = extractvalue { i32, i32, i32, i32 } %64, 2, !dbg !24
+  %68 = extractvalue { i32, i32, i32, i32 } %64, 3, !dbg !24
+  %69 = trunc i32 %65 to i16, !dbg !24
+  %extelt.offset8 = lshr i32 %65, 16, !dbg !24
+  %70 = trunc i32 %extelt.offset8 to i16, !dbg !24
+  %71 = trunc i32 %66 to i16, !dbg !24
+  %extelt.offset9 = lshr i32 %66, 16, !dbg !24
+  %72 = trunc i32 %extelt.offset9 to i16, !dbg !24
+  %73 = trunc i32 %67 to i16, !dbg !24
+  %extelt.offset10 = lshr i32 %67, 16, !dbg !24
+  %74 = trunc i32 %extelt.offset10 to i16, !dbg !24
+  %75 = trunc i32 %68 to i16, !dbg !24
+  %extelt.offset11 = lshr i32 %68, 16, !dbg !24
+  %76 = trunc i32 %extelt.offset11 to i16, !dbg !24
+  %77 = tail call float asm "cvt.f32.bf16 $0, $1;", "=r,h"(i16 %69) #1, !dbg !25
+  %78 = tail call float asm "cvt.f32.bf16 $0, $1;", "=r,h"(i16 %70) #1, !dbg !25
+  %79 = tail call float asm "cvt.f32.bf16 $0, $1;", "=r,h"(i16 %71) #1, !dbg !25
+  %80 = tail call float asm "cvt.f32.bf16 $0, $1;", "=r,h"(i16 %72) #1, !dbg !25
+  %81 = tail call float asm "cvt.f32.bf16 $0, $1;", "=r,h"(i16 %73) #1, !dbg !25
+  %82 = tail call float asm "cvt.f32.bf16 $0, $1;", "=r,h"(i16 %74) #1, !dbg !25
+  %83 = tail call float asm "cvt.f32.bf16 $0, $1;", "=r,h"(i16 %75) #1, !dbg !25
+  %84 = tail call float asm "cvt.f32.bf16 $0, $1;", "=r,h"(i16 %76) #1, !dbg !25
+  %85 = icmp eq i32 %13, 2, !dbg !26
+  %86 = select i1 %85, float %33, float 0.000000e+00, !dbg !27
+  %87 = select i1 %85, float %34, float 0.000000e+00, !dbg !27
+  %88 = select i1 %85, float %35, float 0.000000e+00, !dbg !27
+  %89 = select i1 %85, float %36, float 0.000000e+00, !dbg !27
+  %90 = select i1 %85, float %37, float 0.000000e+00, !dbg !27
+  %91 = select i1 %85, float %38, float 0.000000e+00, !dbg !27
+  %92 = select i1 %85, float %39, float 0.000000e+00, !dbg !27
+  %93 = select i1 %85, float %40, float 0.000000e+00, !dbg !27
+  %94 = icmp eq i32 %13, 1, !dbg !28
+  %95 = select i1 %94, float %55, float 0.000000e+00, !dbg !29
+  %96 = select i1 %94, float %56, float 0.000000e+00, !dbg !29
+  %97 = select i1 %94, float %57, float 0.000000e+00, !dbg !29
+  %98 = select i1 %94, float %58, float 0.000000e+00, !dbg !29
+  %99 = select i1 %94, float %59, float 0.000000e+00, !dbg !29
+  %100 = select i1 %94, float %60, float 0.000000e+00, !dbg !29
+  %101 = select i1 %94, float %61, float 0.000000e+00, !dbg !29
+  %102 = select i1 %94, float %62, float 0.000000e+00, !dbg !29
+  %103 = fadd float %86, %95, !dbg !30
+  %104 = fadd float %87, %96, !dbg !30
+  %105 = fadd float %88, %97, !dbg !30
+  %106 = fadd float %89, %98, !dbg !30
+  %107 = fadd float %90, %99, !dbg !30
+  %108 = fadd float %91, %100, !dbg !30
+  %109 = fadd float %92, %101, !dbg !30
+  %110 = fadd float %93, %102, !dbg !30
+  %111 = icmp eq i32 %13, 0, !dbg !31
+  %112 = select i1 %111, float %77, float 0.000000e+00, !dbg !32
+  %113 = select i1 %111, float %78, float 0.000000e+00, !dbg !32
+  %114 = select i1 %111, float %79, float 0.000000e+00, !dbg !32
+  %115 = select i1 %111, float %80, float 0.000000e+00, !dbg !32
+  %116 = select i1 %111, float %81, float 0.000000e+00, !dbg !32
+  %117 = select i1 %111, float %82, float 0.000000e+00, !dbg !32
+  %118 = select i1 %111, float %83, float 0.000000e+00, !dbg !32
+  %119 = select i1 %111, float %84, float 0.000000e+00, !dbg !32
+  %120 = fadd float %103, %112, !dbg !33
+  %121 = fadd float %104, %113, !dbg !33
+  %122 = fadd float %105, %114, !dbg !33
+  %123 = fadd float %106, %115, !dbg !33
+  %124 = fadd float %107, %116, !dbg !33
+  %125 = fadd float %108, %117, !dbg !33
+  %126 = fadd float %109, %118, !dbg !33
+  %127 = fadd float %110, %119, !dbg !33
+  %128 = sext i32 %11 to i64, !dbg !34
+  %129 = getelementptr i16, ptr addrspace(1) %3, i64 %128, !dbg !34
+  %130 = tail call i16 asm "cvt.rn.bf16.f32 $0, $1;", "=h,r"(float %120) #1, !dbg !35
+  %131 = tail call i16 asm "cvt.rn.bf16.f32 $0, $1;", "=h,r"(float %121) #1, !dbg !35
+  %132 = tail call i16 asm "cvt.rn.bf16.f32 $0, $1;", "=h,r"(float %122) #1, !dbg !35
+  %133 = tail call i16 asm "cvt.rn.bf16.f32 $0, $1;", "=h,r"(float %123) #1, !dbg !35
+  %134 = tail call i16 asm "cvt.rn.bf16.f32 $0, $1;", "=h,r"(float %124) #1, !dbg !35
+  %135 = tail call i16 asm "cvt.rn.bf16.f32 $0, $1;", "=h,r"(float %125) #1, !dbg !35
+  %136 = tail call i16 asm "cvt.rn.bf16.f32 $0, $1;", "=h,r"(float %126) #1, !dbg !35
+  %137 = tail call i16 asm "cvt.rn.bf16.f32 $0, $1;", "=h,r"(float %127) #1, !dbg !35
+  %138 = insertelement <2 x i16> undef, i16 %130, i64 0, !dbg !35
+  %139 = insertelement <2 x i16> %138, i16 %131, i64 1, !dbg !35
+  %140 = bitcast <2 x i16> %139 to i32, !dbg !35
+  %141 = insertelement <2 x i16> undef, i16 %132, i64 0, !dbg !35
+  %142 = insertelement <2 x i16> %141, i16 %133, i64 1, !dbg !35
+  %143 = bitcast <2 x i16> %142 to i32, !dbg !35
+  %144 = insertelement <2 x i16> undef, i16 %134, i64 0, !dbg !35
+  %145 = insertelement <2 x i16> %144, i16 %135, i64 1, !dbg !35
+  %146 = bitcast <2 x i16> %145 to i32, !dbg !35
+  %147 = insertelement <2 x i16> undef, i16 %136, i64 0, !dbg !35
+  %148 = insertelement <2 x i16> %147, i16 %137, i64 1, !dbg !35
+  %149 = bitcast <2 x i16> %148 to i32, !dbg !35
+  tail call void asm sideeffect "@$5 st.global.v4.b32 [ $4 + 0 ], { $0, $1, $2, $3 };", "r,r,r,r,l,b"(i32 %140, i32 %143, i32 %146, i32 %149, ptr addrspace(1) %129, i1 true) #1, !dbg !35
+  ret void, !dbg !36
+}
+
+; Function Attrs: mustprogress nocallback nofree nosync nounwind speculatable willreturn memory(none)
+declare noundef i32 @llvm.nvvm.read.ptx.sreg.tid.x() #0
+
+attributes #0 = { mustprogress nocallback nofree nosync nounwind speculatable willreturn memory(none) }
+attributes #1 = { nounwind }
+
+!llvm.module.flags = !{!0}
+!llvm.dbg.cu = !{!1}
+!nvvm.annotations = !{!3, !4, !4, !3}
+
+!0 = !{i32 2, !"Debug Info Version", i32 3}
+!1 = distinct !DICompileUnit(language: DW_LANG_C, file: !2, producer: "triton", isOptimized: true, runtimeVersion: 0, emissionKind: FullDebug)
+!2 = !DIFile(filename: "c63r7iurwk5ydlswh7rvhcmlx2cfretlrewgw6tljlursshgtfpp.py", directory: "/tmp/torchinductor_root/63")
+!3 = !{ptr @triton__0d1d2d3d4de, !"kernel", i32 1}
+!4 = !{ptr @triton__0d1d2d3d4de, !"maxntidx", i32 128}
+!5 = distinct !DISubprogram(name: "triton__0d1d2d3d4de", linkageName: "triton__0d1d2d3d4de", scope: !2, file: !2, line: 18, type: !6, scopeLine: 18, spFlags: DISPFlagDefinition | DISPFlagOptimized, unit: !1)
+!6 = !DISubroutineType(cc: DW_CC_normal, types: !7)
+!7 = !{}
+!8 = !DILocation(line: 21, column: 36, scope: !5)
+!9 = !DILocation(line: 20, column: 28, scope: !5)
+!10 = !DILocation(line: 20, column: 33, scope: !5)
+!11 = !DILocation(line: 21, column: 23, scope: !5)
+!12 = !DILocation(line: 23, column: 20, scope: !5)
+!13 = !DILocation(line: 23, column: 27, scope: !5)
+!14 = !DILocation(line: 25, column: 20, scope: !5)
+!15 = !DILocation(line: 27, column: 40, scope: !5)
+!16 = !DILocation(line: 27, column: 36, scope: !5)
+!17 = !DILocation(line: 27, column: 30, scope: !5)
+!18 = !DILocation(line: 27, column: 46, scope: !5)
+!19 = !DILocation(line: 27, column: 85, scope: !5)
+!20 = !DILocation(line: 28, column: 30, scope: !5)
+!21 = !DILocation(line: 28, column: 46, scope: !5)
+!22 = !DILocation(line: 28, column: 85, scope: !5)
+!23 = !DILocation(line: 29, column: 31, scope: !5)
+!24 = !DILocation(line: 29, column: 47, scope: !5)
+!25 = !DILocation(line: 29, column: 86, scope: !5)
+!26 = !DILocation(line: 32, column: 19, scope: !5)
+!27 = !DILocation(line: 34, column: 32, scope: !5)
+!28 = !DILocation(line: 36, column: 19, scope: !5)
+!29 = !DILocation(line: 37, column: 32, scope: !5)
+!30 = !DILocation(line: 38, column: 19, scope: !5)
+!31 = !DILocation(line: 40, column: 20, scope: !5)
+!32 = !DILocation(line: 41, column: 35, scope: !5)
+!33 = !DILocation(line: 42, column: 20, scope: !5)
+!34 = !DILocation(line: 43, column: 25, scope: !5)
+!35 = !DILocation(line: 43, column: 37, scope: !5)
+!36 = !DILocation(line: 43, column: 4, scope: !5)

.triton/dump/4a587ee49c44b4c47e51f28541749625/triton_.ptx

@@ -0,0 +1,495 @@
+//
+// Generated by LLVM NVPTX Back-End
+//
+
+.version 8.2
+.target sm_89
+.address_size 64
+
+	// .globl	triton__0d1d2d3d4de
+
+.visible .entry triton__0d1d2d3d4de(
+	.param .u64 triton__0d1d2d3d4de_param_0,
+	.param .u64 triton__0d1d2d3d4de_param_1,
+	.param .u64 triton__0d1d2d3d4de_param_2,
+	.param .u64 triton__0d1d2d3d4de_param_3,
+	.param .u32 triton__0d1d2d3d4de_param_4
+)
+.maxntid 128, 1, 1
+{
+	.reg .pred 	%p<8>;
+	.reg .b16 	%rs<33>;
+	.reg .b32 	%r<77>;
+	.reg .f32 	%f<65>;
+	.reg .b64 	%rd<11>;
+	.loc	1 18 0
+$L__func_begin0:
+	.loc	1 18 0
+
+	ld.param.u64 	%rd5, [triton__0d1d2d3d4de_param_0];
+	ld.param.u64 	%rd6, [triton__0d1d2d3d4de_param_1];
+$L__tmp0:
+	.loc	1 21 36
+	mov.u32 	%r50, %tid.x;
+	shl.b32 	%r51, %r50, 3;
+	ld.param.u64 	%rd7, [triton__0d1d2d3d4de_param_2];
+	and.b32  	%r52, %r51, 1016;
+	ld.param.u64 	%rd8, [triton__0d1d2d3d4de_param_3];
+	.loc	1 20 28
+	mov.u32 %r1, %ctaid.x;
+	.loc	1 20 33
+	shl.b32 	%r53, %r1, 10;
+	.loc	1 21 23
+	or.b32  	%r54, %r53, %r52;
+	.loc	1 23 20
+	shr.s32 	%r56, %r54, 31;
+	shr.u32 	%r57, %r56, 24;
+	add.s32 	%r58, %r54, %r57;
+	shr.s32 	%r59, %r58, 8;
+	.loc	1 23 27
+	mul.hi.s32 	%r60, %r59, 1431655766;
+	shr.u32 	%r61, %r60, 31;
+	add.s32 	%r62, %r60, %r61;
+	mul.lo.s32 	%r63, %r62, 3;
+	sub.s32 	%r64, %r59, %r63;
+	and.b32  	%r65, %r58, -256;
+	sub.s32 	%r66, %r54, %r65;
+	.loc	1 25 20
+	mul.hi.s32 	%r67, %r54, 715827883;
+	shr.u32 	%r68, %r67, 31;
+	shr.u32 	%r69, %r67, 7;
+	add.s32 	%r70, %r69, %r68;
+	.loc	1 27 40
+	shl.b32 	%r71, %r70, 8;
+	.loc	1 27 36
+	add.s32 	%r72, %r71, %r66;
+	.loc	1 27 30
+	mul.wide.s32 	%rd9, %r72, 2;
+	add.s64 	%rd1, %rd5, %rd9;
+	mov.pred 	%p1, -1;
+	.loc	1 27 46
+	mov.u32 %r2, 0x0;
+	mov.u32 %r3, 0x0;
+	mov.u32 %r4, 0x0;
+	mov.u32 %r5, 0x0;
+	@%p1 ld.global.L1::evict_last.v4.b32 { %r2, %r3, %r4, %r5 }, [ %rd1 + 0 ];
+	cvt.u16.u32 	%rs1, %r2;
+	{ .reg .b16 tmp; mov.b32 {tmp, %rs2}, %r2; }
+	cvt.u16.u32 	%rs3, %r3;
+	{ .reg .b16 tmp; mov.b32 {tmp, %rs4}, %r3; }
+	cvt.u16.u32 	%rs5, %r4;
+	{ .reg .b16 tmp; mov.b32 {tmp, %rs6}, %r4; }
+	cvt.u16.u32 	%rs7, %r5;
+	{ .reg .b16 tmp; mov.b32 {tmp, %rs8}, %r5; }
+	.loc	1 27 85
+	cvt.f32.bf16 %r6, %rs1;
+	mov.b32 	%f1, %r6;
+	cvt.f32.bf16 %r7, %rs2;
+	mov.b32 	%f2, %r7;
+	cvt.f32.bf16 %r8, %rs3;
+	mov.b32 	%f3, %r8;
+	cvt.f32.bf16 %r9, %rs4;
+	mov.b32 	%f4, %r9;
+	cvt.f32.bf16 %r10, %rs5;
+	mov.b32 	%f5, %r10;
+	cvt.f32.bf16 %r11, %rs6;
+	mov.b32 	%f6, %r11;
+	cvt.f32.bf16 %r12, %rs7;
+	mov.b32 	%f7, %r12;
+	cvt.f32.bf16 %r13, %rs8;
+	mov.b32 	%f8, %r13;
+	.loc	1 28 30
+	add.s64 	%rd2, %rd6, %rd9;
+	.loc	1 28 46
+	mov.u32 %r14, 0x0;
+	mov.u32 %r15, 0x0;
+	mov.u32 %r16, 0x0;
+	mov.u32 %r17, 0x0;
+	@%p1 ld.global.L1::evict_last.v4.b32 { %r14, %r15, %r16, %r17 }, [ %rd2 + 0 ];
+	cvt.u16.u32 	%rs9, %r14;
+	{ .reg .b16 tmp; mov.b32 {tmp, %rs10}, %r14; }
+	cvt.u16.u32 	%rs11, %r15;
+	{ .reg .b16 tmp; mov.b32 {tmp, %rs12}, %r15; }
+	cvt.u16.u32 	%rs13, %r16;
+	{ .reg .b16 tmp; mov.b32 {tmp, %rs14}, %r16; }
+	cvt.u16.u32 	%rs15, %r17;
+	{ .reg .b16 tmp; mov.b32 {tmp, %rs16}, %r17; }
+	.loc	1 28 85
+	cvt.f32.bf16 %r18, %rs9;
+	mov.b32 	%f9, %r18;
+	cvt.f32.bf16 %r19, %rs10;
+	mov.b32 	%f10, %r19;
+	cvt.f32.bf16 %r20, %rs11;
+	mov.b32 	%f11, %r20;
+	cvt.f32.bf16 %r21, %rs12;
+	mov.b32 	%f12, %r21;
+	cvt.f32.bf16 %r22, %rs13;
+	mov.b32 	%f13, %r22;
+	cvt.f32.bf16 %r23, %rs14;
+	mov.b32 	%f14, %r23;
+	cvt.f32.bf16 %r24, %rs15;
+	mov.b32 	%f15, %r24;
+	cvt.f32.bf16 %r25, %rs16;
+	mov.b32 	%f16, %r25;
+	.loc	1 29 31
+	add.s64 	%rd3, %rd7, %rd9;
+	.loc	1 29 47
+	mov.u32 %r26, 0x0;
+	mov.u32 %r27, 0x0;
+	mov.u32 %r28, 0x0;
+	mov.u32 %r29, 0x0;
+	@%p1 ld.global.L1::evict_last.v4.b32 { %r26, %r27, %r28, %r29 }, [ %rd3 + 0 ];
+	cvt.u16.u32 	%rs17, %r26;
+	{ .reg .b16 tmp; mov.b32 {tmp, %rs18}, %r26; }
+	cvt.u16.u32 	%rs19, %r27;
+	{ .reg .b16 tmp; mov.b32 {tmp, %rs20}, %r27; }
+	cvt.u16.u32 	%rs21, %r28;
+	{ .reg .b16 tmp; mov.b32 {tmp, %rs22}, %r28; }
+	cvt.u16.u32 	%rs23, %r29;
+	{ .reg .b16 tmp; mov.b32 {tmp, %rs24}, %r29; }
+	.loc	1 29 86
+	cvt.f32.bf16 %r30, %rs17;
+	mov.b32 	%f17, %r30;
+	cvt.f32.bf16 %r31, %rs18;
+	mov.b32 	%f18, %r31;
+	cvt.f32.bf16 %r32, %rs19;
+	mov.b32 	%f19, %r32;
+	cvt.f32.bf16 %r33, %rs20;
+	mov.b32 	%f20, %r33;
+	cvt.f32.bf16 %r34, %rs21;
+	mov.b32 	%f21, %r34;
+	cvt.f32.bf16 %r35, %rs22;
+	mov.b32 	%f22, %r35;
+	cvt.f32.bf16 %r36, %rs23;
+	mov.b32 	%f23, %r36;
+	cvt.f32.bf16 %r37, %rs24;
+	mov.b32 	%f24, %r37;
+	.loc	1 32 19
+	setp.eq.s32 	%p5, %r64, 2;
+	.loc	1 34 32
+	selp.f32 	%f25, %f1, 0f00000000, %p5;
+	selp.f32 	%f26, %f2, 0f00000000, %p5;
+	selp.f32 	%f27, %f3, 0f00000000, %p5;
+	selp.f32 	%f28, %f4, 0f00000000, %p5;
+	selp.f32 	%f29, %f5, 0f00000000, %p5;
+	selp.f32 	%f30, %f6, 0f00000000, %p5;
+	selp.f32 	%f31, %f7, 0f00000000, %p5;
+	selp.f32 	%f32, %f8, 0f00000000, %p5;
+	.loc	1 36 19
+	setp.eq.s32 	%p6, %r64, 1;
+	.loc	1 37 32
+	selp.f32 	%f33, %f9, 0f00000000, %p6;
+	selp.f32 	%f34, %f10, 0f00000000, %p6;
+	selp.f32 	%f35, %f11, 0f00000000, %p6;
+	selp.f32 	%f36, %f12, 0f00000000, %p6;
+	selp.f32 	%f37, %f13, 0f00000000, %p6;
+	selp.f32 	%f38, %f14, 0f00000000, %p6;
+	selp.f32 	%f39, %f15, 0f00000000, %p6;
+	selp.f32 	%f40, %f16, 0f00000000, %p6;
+	.loc	1 38 19
+	add.f32 	%f41, %f25, %f33;
+	add.f32 	%f42, %f26, %f34;
+	add.f32 	%f43, %f27, %f35;
+	add.f32 	%f44, %f28, %f36;
+	add.f32 	%f45, %f29, %f37;
+	add.f32 	%f46, %f30, %f38;
+	add.f32 	%f47, %f31, %f39;
+	add.f32 	%f48, %f32, %f40;
+	.loc	1 40 20
+	setp.eq.s32 	%p7, %r64, 0;
+	.loc	1 41 35
+	selp.f32 	%f49, %f17, 0f00000000, %p7;
+	selp.f32 	%f50, %f18, 0f00000000, %p7;
+	selp.f32 	%f51, %f19, 0f00000000, %p7;
+	selp.f32 	%f52, %f20, 0f00000000, %p7;
+	selp.f32 	%f53, %f21, 0f00000000, %p7;
+	selp.f32 	%f54, %f22, 0f00000000, %p7;
+	selp.f32 	%f55, %f23, 0f00000000, %p7;
+	selp.f32 	%f56, %f24, 0f00000000, %p7;
+	.loc	1 42 20
+	add.f32 	%f57, %f41, %f49;
+	add.f32 	%f58, %f42, %f50;
+	add.f32 	%f59, %f43, %f51;
+	add.f32 	%f60, %f44, %f52;
+	add.f32 	%f61, %f45, %f53;
+	add.f32 	%f62, %f46, %f54;
+	add.f32 	%f63, %f47, %f55;
+	add.f32 	%f64, %f48, %f56;
+	.loc	1 43 25
+	mul.wide.s32 	%rd10, %r54, 2;
+	add.s64 	%rd4, %rd8, %rd10;
+	.loc	1 43 37
+	mov.b32 	%r38, %f57;
+	cvt.rn.bf16.f32 %rs25, %r38;
+	mov.b32 	%r39, %f58;
+	cvt.rn.bf16.f32 %rs26, %r39;
+	mov.b32 	%r40, %f59;
+	cvt.rn.bf16.f32 %rs27, %r40;
+	mov.b32 	%r41, %f60;
+	cvt.rn.bf16.f32 %rs28, %r41;
+	mov.b32 	%r42, %f61;
+	cvt.rn.bf16.f32 %rs29, %r42;
+	mov.b32 	%r43, %f62;
+	cvt.rn.bf16.f32 %rs30, %r43;
+	mov.b32 	%r44, %f63;
+	cvt.rn.bf16.f32 %rs31, %r44;
+	mov.b32 	%r45, %f64;
+	cvt.rn.bf16.f32 %rs32, %r45;
+	mov.b32 	%r73, {%rs25, %rs26};
+	mov.b32 	%r74, {%rs27, %rs28};
+	mov.b32 	%r75, {%rs29, %rs30};
+	mov.b32 	%r76, {%rs31, %rs32};
+	@%p1 st.global.v4.b32 [ %rd4 + 0 ], { %r73, %r74, %r75, %r76 };
+	.loc	1 43 4
+	ret;
+$L__tmp1:
+$L__func_end0:
+
+}
+	.file	1 "/tmp/torchinductor_root/63/c63r7iurwk5ydlswh7rvhcmlx2cfretlrewgw6tljlursshgtfpp.py"
+	.section	.debug_abbrev
+	{
+.b8 1
+.b8 17
+.b8 1
+.b8 37
+.b8 8
+.b8 19
+.b8 5
+.b8 3
+.b8 8
+.b8 16
+.b8 6
+.b8 27
+.b8 8
+.b8 180
+.b8 66
+.b8 12
+.b8 17
+.b8 1
+.b8 18
+.b8 1
+.b8 0
+.b8 0
+.b8 2
+.b8 46
+.b8 0
+.b8 17
+.b8 1
+.b8 18
+.b8 1
+.b8 64
+.b8 10
+.b8 135
+.b8 64
+.b8 8
+.b8 3
+.b8 8
+.b8 58
+.b8 11
+.b8 59
+.b8 11
+.b8 63
+.b8 12
+.b8 0
+.b8 0
+.b8 0
+	}
+	.section	.debug_info
+	{
+.b32 184
+.b8 2
+.b8 0
+.b32 .debug_abbrev
+.b8 8
+.b8 1
+.b8 116
+.b8 114
+.b8 105
+.b8 116
+.b8 111
+.b8 110
+.b8 0
+.b8 2
+.b8 0
+.b8 99
+.b8 54
+.b8 51
+.b8 114
+.b8 55
+.b8 105
+.b8 117
+.b8 114
+.b8 119
+.b8 107
+.b8 53
+.b8 121
+.b8 100
+.b8 108
+.b8 115
+.b8 119
+.b8 104
+.b8 55
+.b8 114
+.b8 118
+.b8 104
+.b8 99
+.b8 109
+.b8 108
+.b8 120
+.b8 50
+.b8 99
+.b8 102
+.b8 114
+.b8 101
+.b8 116
+.b8 108
+.b8 114
+.b8 101
+.b8 119
+.b8 103
+.b8 119
+.b8 54
+.b8 116
+.b8 108
+.b8 106
+.b8 108
+.b8 117
+.b8 114
+.b8 115
+.b8 115
+.b8 104
+.b8 103
+.b8 116
+.b8 102
+.b8 112
+.b8 112
+.b8 46
+.b8 112
+.b8 121
+.b8 0
+.b32 .debug_line
+.b8 47
+.b8 116
+.b8 109
+.b8 112
+.b8 47
+.b8 116
+.b8 111
+.b8 114
+.b8 99
+.b8 104
+.b8 105
+.b8 110
+.b8 100
+.b8 117
+.b8 99
+.b8 116
+.b8 111
+.b8 114
+.b8 95
+.b8 114
+.b8 111
+.b8 111
+.b8 116
+.b8 47
+.b8 54
+.b8 51
+.b8 0
+.b8 1
+.b64 $L__func_begin0
+.b64 $L__func_end0
+.b8 2
+.b64 $L__func_begin0
+.b64 $L__func_end0
+.b8 1
+.b8 156
+.b8 116
+.b8 114
+.b8 105
+.b8 116
+.b8 111
+.b8 110
+.b8 95
+.b8 95
+.b8 48
+.b8 100
+.b8 49
+.b8 100
+.b8 50
+.b8 100
+.b8 51
+.b8 100
+.b8 52
+.b8 100
+.b8 101
+.b8 0
+.b8 116
+.b8 114
+.b8 105
+.b8 116
+.b8 111
+.b8 110
+.b8 95
+.b8 95
+.b8 48
+.b8 100
+.b8 49
+.b8 100
+.b8 50
+.b8 100
+.b8 51
+.b8 100
+.b8 52
+.b8 100
+.b8 101
+.b8 0
+.b8 1
+.b8 18
+.b8 1
+.b8 0
+	}
+	.section	.debug_pubnames
+	{
+.b32 $L__pubNames_end0-$L__pubNames_start0
+$L__pubNames_start0:
+.b8 2
+.b8 0
+.b32 .debug_info
+.b32 188
+.b32 125
+.b8 116
+.b8 114
+.b8 105
+.b8 116
+.b8 111
+.b8 110
+.b8 95
+.b8 95
+.b8 48
+.b8 100
+.b8 49
+.b8 100
+.b8 50
+.b8 100
+.b8 51
+.b8 100
+.b8 52
+.b8 100
+.b8 101
+.b8 0
+.b32 0
+$L__pubNames_end0:
+	}
+	.section	.debug_pubtypes
+	{
+.b32 $L__pubTypes_end0-$L__pubTypes_start0
+$L__pubTypes_start0:
+.b8 2
+.b8 0
+.b32 .debug_info
+.b32 188
+.b32 0
+$L__pubTypes_end0:
+	}
+	.section	.debug_loc	{	}

.triton/dump/4d7b96448927b8146af43cb9f39e0544/triton_.ptx

@@ -0,0 +1,486 @@
+//
+// Generated by LLVM NVPTX Back-End
+//
+
+.version 8.2
+.target sm_89
+.address_size 64
+
+	// .globl	triton__0d1d2de
+.global .align 1 .b8 _$_str[11] = {95, 95, 67, 85, 68, 65, 95, 70, 84, 90, 0};
+
+.visible .entry triton__0d1d2de(
+	.param .u64 triton__0d1d2de_param_0,
+	.param .u64 triton__0d1d2de_param_1,
+	.param .u32 triton__0d1d2de_param_2
+)
+.maxntid 256, 1, 1
+{
+	.reg .pred 	%p<10>;
+	.reg .b16 	%rs<7>;
+	.reg .b32 	%r<25>;
+	.reg .f32 	%f<127>;
+	.reg .b64 	%rd<8>;
+	.loc	1 18 0
+$L__func_begin0:
+	.loc	1 18 0
+
+	ld.param.u64 	%rd4, [triton__0d1d2de_param_0];
+	ld.param.u64 	%rd5, [triton__0d1d2de_param_1];
+$L__tmp0:
+	.loc	1 21 36
+	mov.u32 	%r8, %tid.x;
+	shl.b32 	%r9, %r8, 1;
+	and.b32  	%r10, %r9, 510;
+	.loc	1 20 28
+	mov.u32 %r1, %ctaid.x;
+	.loc	1 20 33
+	shl.b32 	%r11, %r1, 9;
+	.loc	1 21 23
+	or.b32  	%r12, %r11, %r10;
+	.loc	1 24 34
+	mul.wide.s32 	%rd6, %r12, 2;
+	add.s64 	%rd7, %rd4, %rd6;
+	mov.pred 	%p1, -1;
+	.loc	1 24 39
+	mov.u32 %r2, 0x0;
+	@%p1 ld.global.b32 { %r2 }, [ %rd7 + 0 ];
+	.loc	1 25 30
+	add.s64 	%rd3, %rd5, %rd6;
+	.loc	1 25 35
+	mov.u32 %r5, 0x0;
+	@%p1 ld.global.b32 { %r5 }, [ %rd3 + 0 ];
+	cvt.u16.u32 	%rs3, %r5;
+	{ .reg .b16 tmp; mov.b32 {tmp, %rs4}, %r5; }
+	.loc	1 25 44
+	cvt.f32.bf16 %r6, %rs3;
+	mov.b32 	%f3, %r6;
+	cvt.f32.bf16 %r7, %rs4;
+	mov.b32 	%f4, %r7;
+	.loc	1 29 18
+	mul.f32 	%f5, %f3, 0f3F3504F3;
+	.loc	1 30 23
+	abs.ftz.f32 	%f7, %f5;
+	setp.ge.f32 	%p3, %f7, 0f3F8060FE;
+	mov.f32 	%f115, 0f3789CA3C;
+	mov.f32 	%f114, 0fB9F560B9;
+	mov.f32 	%f113, 0f3BAC840B;
+	mov.f32 	%f112, 0fBD0C8162;
+	mov.f32 	%f111, 0f3E1CF906;
+	mov.f32 	%f110, 0f3F6A937E;
+	mov.f32 	%f109, 0f3F20D842;
+	mov.f32 	%f116, %f7;
+	@%p3 bra 	$L__BB0_2;
+	.loc	1 0 23
+	mov.f32 	%f115, 0f38B1E96A;
+	mov.f32 	%f114, 0fBA574D20;
+	mov.f32 	%f113, 0f3BAAD5EA;
+	mov.f32 	%f112, 0fBCDC1BE7;
+	mov.f32 	%f111, 0f3DE718AF;
+	mov.f32 	%f110, 0fBEC093AC;
+	mov.f32 	%f109, 0f3E0375D3;
+	.loc	1 30 23
+	mul.f32 	%f116, %f5, %f5;
+$L__BB0_2:
+	.loc	1 0 0
+	cvt.u16.u32 	%rs1, %r2;
+	{ .reg .b16 tmp; mov.b32 {tmp, %rs2}, %r2; }
+	mul.f32 	%f6, %f4, 0f3F3504F3;
+	.loc	1 30 23
+	setp.ltu.f32 	%p4, %f7, 0f3F8060FE;
+	fma.rn.ftz.f32 	%f47, %f115, %f116, %f114;
+	fma.rn.ftz.f32 	%f48, %f47, %f116, %f113;
+	fma.rn.ftz.f32 	%f49, %f48, %f116, %f112;
+	fma.rn.ftz.f32 	%f50, %f49, %f116, %f111;
+	fma.rn.ftz.f32 	%f51, %f50, %f116, %f110;
+	fma.rn.ftz.f32 	%f52, %f51, %f116, %f109;
+	neg.f32 	%f53, %f116;
+	selp.f32 	%f54, %f53, %f5, %p3;
+	fma.rn.ftz.f32 	%f117, %f52, %f54, %f54;
+	mov.f32 	%f108, 0f3F800000;
+	@%p4 bra 	$L__BB0_4;
+	ex2.approx.ftz.f32 	%f55, %f117;
+	sub.f32 	%f57, %f108, %f55;
+	mov.b32 	%r13, %f57;
+	mov.b32 	%r14, %f5;
+	and.b32  	%r15, %r14, -2147483648;
+	or.b32  	%r16, %r15, %r13;
+	mov.b32 	%f117, %r16;
+$L__BB0_4:
+	.loc	1 0 0
+	cvt.f32.bf16 %r3, %rs1;
+	cvt.f32.bf16 %r4, %rs2;
+	.loc	1 30 23
+	abs.ftz.f32 	%f20, %f6;
+	setp.ge.f32 	%p6, %f20, 0f3F8060FE;
+	mov.f32 	%f124, 0f3789CA3C;
+	mov.f32 	%f123, 0fB9F560B9;
+	mov.f32 	%f122, 0f3BAC840B;
+	mov.f32 	%f121, 0fBD0C8162;
+	mov.f32 	%f120, 0f3E1CF906;
+	mov.f32 	%f119, 0f3F6A937E;
+	mov.f32 	%f118, 0f3F20D842;
+	mov.f32 	%f125, %f20;
+	@%p6 bra 	$L__BB0_6;
+	mul.f32 	%f125, %f6, %f6;
+	mov.f32 	%f124, 0f38B1E96A;
+	mov.f32 	%f123, 0fBA574D20;
+	mov.f32 	%f122, 0f3BAAD5EA;
+	mov.f32 	%f121, 0fBCDC1BE7;
+	mov.f32 	%f120, 0f3DE718AF;
+	mov.f32 	%f119, 0fBEC093AC;
+	mov.f32 	%f118, 0f3E0375D3;
+$L__BB0_6:
+	.loc	1 0 0
+	mov.b32 	%f1, %r3;
+	mov.b32 	%f2, %r4;
+	.loc	1 30 23
+	setp.ltu.f32 	%p7, %f20, 0f3F8060FE;
+	fma.rn.ftz.f32 	%f72, %f124, %f125, %f123;
+	fma.rn.ftz.f32 	%f73, %f72, %f125, %f122;
+	fma.rn.ftz.f32 	%f74, %f73, %f125, %f121;
+	fma.rn.ftz.f32 	%f75, %f74, %f125, %f120;
+	fma.rn.ftz.f32 	%f76, %f75, %f125, %f119;
+	fma.rn.ftz.f32 	%f77, %f76, %f125, %f118;
+	neg.f32 	%f78, %f125;
+	selp.f32 	%f79, %f78, %f6, %p6;
+	fma.rn.ftz.f32 	%f126, %f77, %f79, %f79;
+	@%p7 bra 	$L__BB0_8;
+	ex2.approx.ftz.f32 	%f80, %f126;
+	sub.f32 	%f82, %f108, %f80;
+	mov.b32 	%r17, %f82;
+	mov.b32 	%r18, %f6;
+	and.b32  	%r19, %r18, -2147483648;
+	or.b32  	%r20, %r19, %r17;
+	mov.b32 	%f126, %r20;
+$L__BB0_8:
+	.loc	1 32 18
+	add.f32 	%f87, %f117, 0f3F800000;
+	add.f32 	%f88, %f126, 0f3F800000;
+	.loc	1 35 19
+	mul.f32 	%f89, %f3, %f3;
+	mul.f32 	%f90, %f4, %f4;
+	.loc	1 37 20
+	mul.f32 	%f91, %f89, 0fBF000000;
+	mul.f32 	%f92, %f90, 0fBF000000;
+	.loc	1 38 19
+	mul.f32 	%f84, %f91, 0f3FB8AA3B;
+	ex2.approx.f32 %f83, %f84;
+	mul.f32 	%f86, %f92, 0f3FB8AA3B;
+	ex2.approx.f32 %f85, %f86;
+	.loc	1 40 20
+	mul.f32 	%f93, %f83, 0f3ECC422A;
+	mul.f32 	%f94, %f85, 0f3ECC422A;
+	.loc	1 41 19
+	mul.f32 	%f95, %f3, %f93;
+	mul.f32 	%f96, %f4, %f94;
+	.loc	1 42 20
+	fma.rn.f32 	%f97, %f87, 0f3F000000, %f95;
+	fma.rn.f32 	%f98, %f88, 0f3F000000, %f96;
+	.loc	1 43 19
+	mul.f32 	%f99, %f1, %f97;
+	mul.f32 	%f100, %f2, %f98;
+	.loc	1 45 40
+	mov.b32 	%r21, %f99;
+	cvt.rn.bf16.f32 %rs5, %r21;
+	mov.b32 	%r22, %f100;
+	cvt.rn.bf16.f32 %rs6, %r22;
+	mov.b32 	%r24, {%rs5, %rs6};
+	@%p1 st.global.b32 [ %rd7 + 0 ], { %r24 };
+	.loc	1 45 4
+	ret;
+$L__tmp1:
+$L__func_end0:
+
+}
+	// .globl	__nv_erff
+.visible .func  (.param .b32 func_retval0) __nv_erff(
+	.param .b32 __nv_erff_param_0
+)
+{
+	.reg .pred 	%p<4>;
+	.reg .b32 	%r<5>;
+	.reg .f32 	%f<49>;
+$L__func_begin1:
+
+	ld.param.f32 	%f14, [__nv_erff_param_0];
+	abs.ftz.f32 	%f1, %f14;
+	setp.ge.f32 	%p1, %f1, 0f3F8060FE;
+	mov.f32 	%f46, 0f3789CA3C;
+	mov.f32 	%f45, 0fB9F560B9;
+	mov.f32 	%f44, 0f3BAC840B;
+	mov.f32 	%f43, 0fBD0C8162;
+	mov.f32 	%f42, 0f3E1CF906;
+	mov.f32 	%f41, 0f3F6A937E;
+	mov.f32 	%f40, 0f3F20D842;
+	mov.f32 	%f47, %f1;
+	@%p1 bra 	$L__BB1_2;
+	mul.f32 	%f47, %f14, %f14;
+	mov.f32 	%f46, 0f38B1E96A;
+	mov.f32 	%f45, 0fBA574D20;
+	mov.f32 	%f44, 0f3BAAD5EA;
+	mov.f32 	%f43, 0fBCDC1BE7;
+	mov.f32 	%f42, 0f3DE718AF;
+	mov.f32 	%f41, 0fBEC093AC;
+	mov.f32 	%f40, 0f3E0375D3;
+$L__BB1_2:
+	setp.ltu.f32 	%p2, %f1, 0f3F8060FE;
+	fma.rn.ftz.f32 	%f29, %f46, %f47, %f45;
+	fma.rn.ftz.f32 	%f30, %f29, %f47, %f44;
+	fma.rn.ftz.f32 	%f31, %f30, %f47, %f43;
+	fma.rn.ftz.f32 	%f32, %f31, %f47, %f42;
+	fma.rn.ftz.f32 	%f33, %f32, %f47, %f41;
+	fma.rn.ftz.f32 	%f34, %f33, %f47, %f40;
+	neg.f32 	%f35, %f47;
+	selp.f32 	%f36, %f35, %f14, %p1;
+	fma.rn.ftz.f32 	%f48, %f34, %f36, %f36;
+	@%p2 bra 	$L__BB1_4;
+	ex2.approx.ftz.f32 	%f37, %f48;
+	mov.f32 	%f38, 0f3F800000;
+	sub.f32 	%f39, %f38, %f37;
+	mov.b32 	%r1, %f39;
+	mov.b32 	%r2, %f14;
+	and.b32  	%r3, %r2, -2147483648;
+	or.b32  	%r4, %r3, %r1;
+	mov.b32 	%f48, %r4;
+$L__BB1_4:
+	st.param.f32 	[func_retval0+0], %f48;
+	ret;
+$L__func_end1:
+
+}
+	.file	1 "/tmp/torchinductor_root/5j/c5jxaguxho3nhrlt5vcinnz5fevodumlpwn4wyb2vx3xrveicerl.py"
+	.section	.debug_abbrev
+	{
+.b8 1
+.b8 17
+.b8 1
+.b8 37
+.b8 8
+.b8 19
+.b8 5
+.b8 3
+.b8 8
+.b8 16
+.b8 6
+.b8 27
+.b8 8
+.b8 180
+.b8 66
+.b8 12
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+.b8 2
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+.b8 0
+.b8 17
+.b8 1
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+.b8 1
+.b8 64
+.b8 10
+.b8 135
+.b8 64
+.b8 8
+.b8 3
+.b8 8
+.b8 58
+.b8 11
+.b8 59
+.b8 11
+.b8 63
+.b8 12
+.b8 0
+.b8 0
+.b8 0
+	}
+	.section	.debug_info
+	{
+.b32 176
+.b8 2
+.b8 0
+.b32 .debug_abbrev
+.b8 8
+.b8 1
+.b8 116
+.b8 114
+.b8 105
+.b8 116
+.b8 111
+.b8 110
+.b8 0
+.b8 2
+.b8 0
+.b8 99
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+.b8 97
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+.b8 117
+.b8 120
+.b8 104
+.b8 111
+.b8 51
+.b8 110
+.b8 104
+.b8 114
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+.b8 116
+.b8 53
+.b8 118
+.b8 99
+.b8 105
+.b8 110
+.b8 110
+.b8 122
+.b8 53
+.b8 102
+.b8 101
+.b8 118
+.b8 111
+.b8 100
+.b8 117
+.b8 109
+.b8 108
+.b8 112
+.b8 119
+.b8 110
+.b8 52
+.b8 119
+.b8 121
+.b8 98
+.b8 50
+.b8 118
+.b8 120
+.b8 51
+.b8 120
+.b8 114
+.b8 118
+.b8 101
+.b8 105
+.b8 99
+.b8 101
+.b8 114
+.b8 108
+.b8 46
+.b8 112
+.b8 121
+.b8 0
+.b32 .debug_line
+.b8 47
+.b8 116
+.b8 109
+.b8 112
+.b8 47
+.b8 116
+.b8 111
+.b8 114
+.b8 99
+.b8 104
+.b8 105
+.b8 110
+.b8 100
+.b8 117
+.b8 99
+.b8 116
+.b8 111
+.b8 114
+.b8 95
+.b8 114
+.b8 111
+.b8 111
+.b8 116
+.b8 47
+.b8 53
+.b8 106
+.b8 0
+.b8 1
+.b64 $L__func_begin0
+.b64 $L__func_end0
+.b8 2
+.b64 $L__func_begin0
+.b64 $L__func_end0
+.b8 1
+.b8 156
+.b8 116
+.b8 114
+.b8 105
+.b8 116
+.b8 111
+.b8 110
+.b8 95
+.b8 95
+.b8 48
+.b8 100
+.b8 49
+.b8 100
+.b8 50
+.b8 100
+.b8 101
+.b8 0
+.b8 116
+.b8 114
+.b8 105
+.b8 116
+.b8 111
+.b8 110
+.b8 95
+.b8 95
+.b8 48
+.b8 100
+.b8 49
+.b8 100
+.b8 50
+.b8 100
+.b8 101
+.b8 0
+.b8 1
+.b8 18
+.b8 1
+.b8 0
+	}
+	.section	.debug_pubnames
+	{
+.b32 $L__pubNames_end0-$L__pubNames_start0
+$L__pubNames_start0:
+.b8 2
+.b8 0
+.b32 .debug_info
+.b32 180
+.b32 125
+.b8 116
+.b8 114
+.b8 105
+.b8 116
+.b8 111
+.b8 110
+.b8 95
+.b8 95
+.b8 48
+.b8 100
+.b8 49
+.b8 100
+.b8 50
+.b8 100
+.b8 101
+.b8 0
+.b32 0
+$L__pubNames_end0:
+	}
+	.section	.debug_pubtypes
+	{
+.b32 $L__pubTypes_end0-$L__pubTypes_start0
+$L__pubTypes_start0:
+.b8 2
+.b8 0
+.b32 .debug_info
+.b32 180
+.b32 0
+$L__pubTypes_end0:
+	}
+	.section	.debug_loc	{	}

.triton/dump/4d7b96448927b8146af43cb9f39e0544/triton_.ttgir

@@ -0,0 +1,38 @@
+#blocked = #triton_gpu.blocked<{sizePerThread = [2], threadsPerWarp = [32], warpsPerCTA = [8], order = [0], CTAsPerCGA = [1], CTASplitNum = [1], CTAOrder = [0]}>
+module attributes {"triton_gpu.compute-capability" = 89 : i32, "triton_gpu.num-ctas" = 1 : i32, "triton_gpu.num-warps" = 8 : i32, "triton_gpu.threads-per-warp" = 32 : i32} {
+  tt.func public @triton__0d1d2de(%arg0: !tt.ptr<bf16, 1> {tt.divisibility = 16 : i32}, %arg1: !tt.ptr<bf16, 1> {tt.divisibility = 16 : i32}, %arg2: i32 {tt.divisibility = 16 : i32, tt.max_divisibility = 16 : i32}) attributes {noinline = false} {
+    %cst = arith.constant dense<0.398942292> : tensor<512xf32, #blocked>
+    %cst_0 = arith.constant dense<-5.000000e-01> : tensor<512xf32, #blocked>
+    %cst_1 = arith.constant dense<5.000000e-01> : tensor<512xf32, #blocked>
+    %cst_2 = arith.constant dense<1.000000e+00> : tensor<512xf32, #blocked>
+    %cst_3 = arith.constant dense<0.707106769> : tensor<512xf32, #blocked>
+    %c512_i32 = arith.constant 512 : i32
+    %0 = tt.get_program_id x : i32
+    %1 = arith.muli %0, %c512_i32 : i32
+    %2 = tt.make_range {end = 512 : i32, start = 0 : i32} : tensor<512xi32, #blocked>
+    %3 = tt.splat %1 : (i32) -> tensor<512xi32, #blocked>
+    %4 = arith.addi %3, %2 : tensor<512xi32, #blocked>
+    %5 = tt.splat %arg0 : (!tt.ptr<bf16, 1>) -> tensor<512x!tt.ptr<bf16, 1>, #blocked>
+    %6 = tt.addptr %5, %4 : tensor<512x!tt.ptr<bf16, 1>, #blocked>, tensor<512xi32, #blocked>
+    %7 = tt.load %6 {cache = 1 : i32, evict = 1 : i32, isVolatile = false} : tensor<512xbf16, #blocked>
+    %8 = arith.extf %7 : tensor<512xbf16, #blocked> to tensor<512xf32, #blocked>
+    %9 = tt.splat %arg1 : (!tt.ptr<bf16, 1>) -> tensor<512x!tt.ptr<bf16, 1>, #blocked>
+    %10 = tt.addptr %9, %4 : tensor<512x!tt.ptr<bf16, 1>, #blocked>, tensor<512xi32, #blocked>
+    %11 = tt.load %10 {cache = 1 : i32, evict = 1 : i32, isVolatile = false} : tensor<512xbf16, #blocked>
+    %12 = arith.extf %11 : tensor<512xbf16, #blocked> to tensor<512xf32, #blocked>
+    %13 = arith.mulf %12, %cst_3 : tensor<512xf32, #blocked>
+    %14 = tt.extern_elementwise %13 {libname = "libdevice", libpath = "/usr/local/lib/python3.10/dist-packages/triton/language/../third_party/cuda/lib/libdevice.10.bc", pure = true, symbol = "__nv_erff"} : (tensor<512xf32, #blocked>) -> tensor<512xf32, #blocked>
+    %15 = arith.addf %14, %cst_2 : tensor<512xf32, #blocked>
+    %16 = arith.mulf %15, %cst_1 : tensor<512xf32, #blocked>
+    %17 = arith.mulf %12, %12 : tensor<512xf32, #blocked>
+    %18 = arith.mulf %17, %cst_0 : tensor<512xf32, #blocked>
+    %19 = math.exp %18 : tensor<512xf32, #blocked>
+    %20 = arith.mulf %19, %cst : tensor<512xf32, #blocked>
+    %21 = arith.mulf %12, %20 : tensor<512xf32, #blocked>
+    %22 = arith.addf %16, %21 : tensor<512xf32, #blocked>
+    %23 = arith.mulf %8, %22 : tensor<512xf32, #blocked>
+    %24 = arith.truncf %23 : tensor<512xf32, #blocked> to tensor<512xbf16, #blocked>
+    tt.store %6, %24 {cache = 1 : i32, evict = 1 : i32} : tensor<512xbf16, #blocked>
+    tt.return
+  }
+}

.triton/dump/550b88a9db74a71f80def697002389b5/triton_.ttir

@@ -0,0 +1,53 @@
+module {
+  tt.func public @triton__0d1d2d3de4e(%arg0: !tt.ptr<f32, 1> {tt.divisibility = 16 : i32}, %arg1: !tt.ptr<i64, 1> {tt.divisibility = 16 : i32}, %arg2: !tt.ptr<f32, 1> {tt.divisibility = 16 : i32}, %arg3: i32 {tt.divisibility = 16 : i32, tt.max_divisibility = 16 : i32}, %arg4: i32 {tt.max_divisibility = 8 : i32}) attributes {noinline = false} {
+    %cst = arith.constant dense<256> : tensor<16x1xi64>
+    %cst_0 = arith.constant dense<0> : tensor<16x1xi64>
+    %cst_1 = arith.constant dense<512> : tensor<16x1xi64>
+    %cst_2 = arith.constant dense<true> : tensor<16x1xi1>
+    %cst_3 = arith.constant dense<256> : tensor<16x1xi32>
+    %cst_4 = arith.constant dense<131072> : tensor<1x128xi32>
+    %cst_5 = arith.constant dense<120> : tensor<1x128xi32>
+    %cst_6 = arith.constant dense<0.000000e+00> : tensor<16x128xf32>
+    %c16_i32 = arith.constant 16 : i32
+    %0 = tt.get_program_id x : i32
+    %1 = arith.muli %0, %c16_i32 : i32
+    %2 = tt.make_range {end = 16 : i32, start = 0 : i32} : tensor<16xi32>
+    %3 = tt.expand_dims %2 {axis = 1 : i32} : (tensor<16xi32>) -> tensor<16x1xi32>
+    %4 = tt.splat %1 : (i32) -> tensor<16x1xi32>
+    %5 = arith.addi %4, %3 : tensor<16x1xi32>
+    %6 = tt.make_range {end = 128 : i32, start = 0 : i32} : tensor<128xi32>
+    %7 = tt.expand_dims %6 {axis = 0 : i32} : (tensor<128xi32>) -> tensor<1x128xi32>
+    %8 = arith.cmpi slt, %7, %cst_5 : tensor<1x128xi32>
+    %9 = arith.muli %7, %cst_4 : tensor<1x128xi32>
+    %10 = tt.broadcast %5 : (tensor<16x1xi32>) -> tensor<16x128xi32>
+    %11 = tt.broadcast %9 : (tensor<1x128xi32>) -> tensor<16x128xi32>
+    %12 = arith.addi %10, %11 : tensor<16x128xi32>
+    %13 = tt.splat %arg0 : (!tt.ptr<f32, 1>) -> tensor<16x128x!tt.ptr<f32, 1>>
+    %14 = tt.addptr %13, %12 : tensor<16x128x!tt.ptr<f32, 1>>, tensor<16x128xi32>
+    %15 = tt.broadcast %8 : (tensor<1x128xi1>) -> tensor<16x128xi1>
+    %16 = tt.load %14, %15, %cst_6 {cache = 1 : i32, evict = 2 : i32, isVolatile = false} : tensor<16x128xf32>
+    %17 = arith.addf %16, %cst_6 : tensor<16x128xf32>
+    %18 = arith.select %15, %17, %cst_6 : tensor<16x128xi1>, tensor<16x128xf32>
+    %19 = "tt.reduce"(%18) <{axis = 1 : i32}> ({
+    ^bb0(%arg5: f32, %arg6: f32):
+      %35 = arith.addf %arg5, %arg6 : f32
+      tt.reduce.return %35 : f32
+    }) : (tensor<16x128xf32>) -> tensor<16xf32>
+    %20 = tt.expand_dims %19 {axis = 1 : i32} : (tensor<16xf32>) -> tensor<16x1xf32>
+    %21 = arith.divsi %5, %cst_3 : tensor<16x1xi32>
+    %22 = arith.remsi %5, %cst_3 : tensor<16x1xi32>
+    %23 = tt.splat %arg1 : (!tt.ptr<i64, 1>) -> tensor<16x1x!tt.ptr<i64, 1>>
+    %24 = tt.addptr %23, %21 : tensor<16x1x!tt.ptr<i64, 1>>, tensor<16x1xi32>
+    %25 = tt.load %24 {cache = 1 : i32, evict = 3 : i32, isVolatile = false} : tensor<16x1xi64>
+    %26 = arith.addi %25, %cst_1 : tensor<16x1xi64>
+    %27 = arith.cmpi slt, %25, %cst_0 : tensor<16x1xi64>
+    %28 = arith.select %27, %26, %25 : tensor<16x1xi1>, tensor<16x1xi64>
+    %29 = arith.muli %28, %cst : tensor<16x1xi64>
+    %30 = arith.extsi %22 : tensor<16x1xi32> to tensor<16x1xi64>
+    %31 = arith.addi %30, %29 : tensor<16x1xi64>
+    %32 = tt.splat %arg2 : (!tt.ptr<f32, 1>) -> tensor<16x1x!tt.ptr<f32, 1>>
+    %33 = tt.addptr %32, %31 : tensor<16x1x!tt.ptr<f32, 1>>, tensor<16x1xi64>
+    %34 = "tt.atomic_rmw"(%33, %20, %cst_2) <{atomic_rmw_op = 5 : i32, scope = 1 : i32, sem = 4 : i32}> : (tensor<16x1x!tt.ptr<f32, 1>>, tensor<16x1xf32>, tensor<16x1xi1>) -> tensor<16x1xf32>
+    tt.return
+  }
+}

.triton/dump/63ac7476060ddeef758fa13ad6ed58f5/triton_.ptx

@@ -0,0 +1,709 @@
+//
+// Generated by LLVM NVPTX Back-End
+//
+
+.version 8.2
+.target sm_89
+.address_size 64
+
+	// .globl	triton__0d1d2d3d4d5d6de7de
+.extern .shared .align 1 .b8 global_smem[];
+
+.visible .entry triton__0d1d2d3d4d5d6de7de(
+	.param .u64 triton__0d1d2d3d4d5d6de7de_param_0,
+	.param .u64 triton__0d1d2d3d4d5d6de7de_param_1,
+	.param .u64 triton__0d1d2d3d4d5d6de7de_param_2,
+	.param .u64 triton__0d1d2d3d4d5d6de7de_param_3,
+	.param .u64 triton__0d1d2d3d4d5d6de7de_param_4,
+	.param .u64 triton__0d1d2d3d4d5d6de7de_param_5,
+	.param .u32 triton__0d1d2d3d4d5d6de7de_param_6,
+	.param .u32 triton__0d1d2d3d4d5d6de7de_param_7
+)
+.maxntid 64, 1, 1
+{
+	.reg .pred 	%p<33>;
+	.reg .b16 	%rs<9>;
+	.reg .b32 	%r<106>;
+	.reg .f32 	%f<73>;
+	.reg .b64 	%rd<21>;
+	.loc	1 18 0
+$L__func_begin0:
+	.loc	1 18 0
+
+	ld.param.u64 	%rd11, [triton__0d1d2d3d4d5d6de7de_param_0];
+	ld.param.u64 	%rd12, [triton__0d1d2d3d4d5d6de7de_param_1];
+$L__tmp0:
+	.loc	1 26 26
+	mov.u32 	%r72, %tid.x;
+	and.b32  	%r73, %r72, 31;
+	ld.param.u64 	%rd13, [triton__0d1d2d3d4d5d6de7de_param_2];
+	ld.param.u64 	%rd14, [triton__0d1d2d3d4d5d6de7de_param_3];
+	ld.param.u64 	%rd15, [triton__0d1d2d3d4d5d6de7de_param_4];
+	shl.b32 	%r74, %r72, 2;
+	ld.param.u64 	%rd16, [triton__0d1d2d3d4d5d6de7de_param_5];
+	and.b32  	%r75, %r74, 252;
+	.loc	1 23 28
+	mov.u32 %r1, %ctaid.x;
+	.loc	1 30 40
+	shl.b32 	%r76, %r1, 8;
+	.loc	1 30 36
+	or.b32  	%r77, %r76, %r75;
+	.loc	1 30 30
+	mul.wide.s32 	%rd17, %r77, 2;
+	add.s64 	%rd1, %rd12, %rd17;
+	mov.b32 	%r4, 0;
+	mov.pred 	%p1, -1;
+	.loc	1 30 46
+	mov.u32 %r2, 0x0;
+	mov.u32 %r3, 0x0;
+	@%p1 ld.global.v2.b32 { %r2, %r3 }, [ %rd1 + 0 ];
+	@!%p1 mov.u32 %r2, %r4;
+	@!%p1 mov.u32 %r3, %r4;
+	cvt.u16.u32 	%rs1, %r2;
+	{ .reg .b16 tmp; mov.b32 {tmp, %rs2}, %r2; }
+	cvt.u16.u32 	%rs3, %r3;
+	{ .reg .b16 tmp; mov.b32 {tmp, %rs4}, %r3; }
+	.loc	1 30 67
+	cvt.f32.bf16 %r6, %rs1;
+	mov.b32 	%f1, %r6;
+	cvt.f32.bf16 %r7, %rs2;
+	mov.b32 	%f2, %r7;
+	cvt.f32.bf16 %r8, %rs3;
+	mov.b32 	%f3, %r8;
+	cvt.f32.bf16 %r9, %rs4;
+	mov.b32 	%f4, %r9;
+	.loc	1 31 30
+	mul.wide.u32 	%rd18, %r75, 4;
+	add.s64 	%rd2, %rd13, %rd18;
+	.loc	1 31 35
+	mov.u32 %r10, 0x0;
+	mov.u32 %r11, 0x0;
+	mov.u32 %r12, 0x0;
+	mov.u32 %r13, 0x0;
+	@%p1 ld.global.L1::evict_last.v4.b32 { %r10, %r11, %r12, %r13 }, [ %rd2 + 0 ];
+	@!%p1 mov.u32 %r10, %r4;
+	@!%p1 mov.u32 %r11, %r4;
+	@!%p1 mov.u32 %r12, %r4;
+	@!%p1 mov.u32 %r13, %r4;
+	mov.b32 	%f5, %r10;
+	mov.b32 	%f6, %r11;
+	mov.b32 	%f7, %r12;
+	mov.b32 	%f8, %r13;
+	.loc	1 32 30
+	mul.wide.s32 	%rd19, %r77, 4;
+	add.s64 	%rd3, %rd14, %rd19;
+	.loc	1 32 46
+	mov.u32 %r18, 0x0;
+	mov.u32 %r19, 0x0;
+	mov.u32 %r20, 0x0;
+	mov.u32 %r21, 0x0;
+	@%p1 ld.global.v4.b32 { %r18, %r19, %r20, %r21 }, [ %rd3 + 0 ];
+	@!%p1 mov.u32 %r18, %r4;
+	@!%p1 mov.u32 %r19, %r4;
+	@!%p1 mov.u32 %r20, %r4;
+	@!%p1 mov.u32 %r21, %r4;
+	mov.b32 	%f9, %r18;
+	mov.b32 	%f10, %r19;
+	mov.b32 	%f11, %r20;
+	mov.b32 	%f12, %r21;
+	.loc	1 33 35
+	add.s64 	%rd4, %rd11, %rd19;
+	.loc	1 33 51
+	mov.u32 %r26, 0x0;
+	mov.u32 %r27, 0x0;
+	mov.u32 %r28, 0x0;
+	mov.u32 %r29, 0x0;
+	@%p1 ld.global.v4.b32 { %r26, %r27, %r28, %r29 }, [ %rd4 + 0 ];
+	@!%p1 mov.u32 %r26, %r4;
+	@!%p1 mov.u32 %r27, %r4;
+	@!%p1 mov.u32 %r28, %r4;
+	@!%p1 mov.u32 %r29, %r4;
+	mov.b32 	%f13, %r26;
+	mov.b32 	%f14, %r27;
+	mov.b32 	%f15, %r28;
+	mov.b32 	%f16, %r29;
+	.loc	1 34 31
+	mul.wide.s32 	%rd20, %r1, 4;
+	add.s64 	%rd5, %rd15, %rd20;
+	.loc	1 34 36
+	mov.u32 %r51, 0x0;
+	@%p1 ld.global.L1::evict_last.b32 { %r51 }, [ %rd5 + 0 ];
+	mov.u32 %r35, 0x0;
+	@%p1 ld.global.L1::evict_last.b32 { %r35 }, [ %rd5 + 0 ];
+	mov.u32 %r36, 0x0;
+	@%p1 ld.global.L1::evict_last.b32 { %r36 }, [ %rd5 + 0 ];
+	mov.u32 %r37, 0x0;
+	@%p1 ld.global.L1::evict_last.b32 { %r37 }, [ %rd5 + 0 ];
+	.loc	1 36 18
+	mul.f32 	%f17, %f1, %f5;
+	mul.f32 	%f18, %f2, %f6;
+	mul.f32 	%f19, %f3, %f7;
+	mul.f32 	%f20, %f4, %f8;
+$L__tmp1:
+	.loc	2 233 15
+	fma.rn.f32 	%f21, %f1, %f5, %f18;
+	fma.rn.f32 	%f22, %f3, %f7, %f21;
+	fma.rn.f32 	%f23, %f4, %f8, %f22;
+$L__tmp2:
+	.loc	2 243 36
+	mov.b32 	%r78, %f23;
+	shfl.sync.bfly.b32	%r79, %r78, 16, 31, -1;
+	mov.b32 	%f24, %r79;
+$L__tmp3:
+	.loc	2 233 15
+	add.f32 	%f25, %f23, %f24;
+$L__tmp4:
+	.loc	2 243 36
+	mov.b32 	%r80, %f25;
+	shfl.sync.bfly.b32	%r81, %r80, 8, 31, -1;
+	mov.b32 	%f26, %r81;
+$L__tmp5:
+	.loc	2 233 15
+	add.f32 	%f27, %f25, %f26;
+$L__tmp6:
+	.loc	2 243 36
+	mov.b32 	%r82, %f27;
+	shfl.sync.bfly.b32	%r83, %r82, 4, 31, -1;
+	mov.b32 	%f28, %r83;
+$L__tmp7:
+	.loc	2 233 15
+	add.f32 	%f29, %f27, %f28;
+$L__tmp8:
+	.loc	2 243 36
+	mov.b32 	%r84, %f29;
+	shfl.sync.bfly.b32	%r85, %r84, 2, 31, -1;
+	mov.b32 	%f30, %r85;
+$L__tmp9:
+	.loc	2 233 15
+	add.f32 	%f31, %f29, %f30;
+$L__tmp10:
+	.loc	2 243 36
+	mov.b32 	%r86, %f31;
+	shfl.sync.bfly.b32	%r87, %r86, 1, 31, -1;
+	mov.b32 	%f32, %r87;
+$L__tmp11:
+	.loc	2 233 15
+	add.f32 	%f33, %f31, %f32;
+$L__tmp12:
+	.loc	2 243 36
+	setp.eq.s32 	%p23, %r73, 0;
+	shr.u32 	%r88, %r72, 3;
+	and.b32  	%r89, %r88, 4;
+	mov.u32 	%r90, global_smem;
+	add.s32 	%r38, %r90, %r89;
+	mov.b32 	%r39, %f33;
+	@%p23 st.shared.b32 [ %r38 + 0 ], %r39;
+	bar.sync 	0;
+	setp.lt.s32 	%p24, %r72, 2;
+	add.s32 	%r41, %r90, %r74;
+	@%p24 ld.shared.b32 %r40, [ %r41 + 0 ];
+	mov.b32 	%f34, %r40;
+	shfl.sync.bfly.b32	%r91, %r40, 1, 31, -1;
+	mov.b32 	%f35, %r91;
+$L__tmp13:
+	.loc	2 233 15
+	add.f32 	%f36, %f34, %f35;
+$L__tmp14:
+	.loc	2 243 36
+	and.b32  	%r92, %r72, 1;
+	setp.eq.b32 	%p31, %r92, 1;
+	not.pred 	%p32, %p31;
+	and.pred  	%p25, %p24, %p32;
+	mov.b32 	%r43, %f36;
+	@%p25 st.shared.b32 [ %r41 + 0 ], %r43;
+	bar.sync 	0;
+	ld.shared.f32 	%f37, [global_smem];
+$L__tmp15:
+	.loc	3 8 15
+	add.f32 	%f38, %f37, 0f00000000;
+$L__tmp16:
+	.loc	1 40 18
+	mul.f32 	%f39, %f18, %f10;
+$L__tmp17:
+	.loc	2 243 36
+	bar.sync 	0;
+$L__tmp18:
+	.loc	2 233 15
+	fma.rn.f32 	%f40, %f17, %f9, %f39;
+	fma.rn.f32 	%f41, %f19, %f11, %f40;
+	fma.rn.f32 	%f42, %f20, %f12, %f41;
+$L__tmp19:
+	.loc	2 243 36
+	mov.b32 	%r93, %f42;
+	shfl.sync.bfly.b32	%r94, %r93, 16, 31, -1;
+	mov.b32 	%f43, %r94;
+$L__tmp20:
+	.loc	2 233 15
+	add.f32 	%f44, %f42, %f43;
+$L__tmp21:
+	.loc	2 243 36
+	mov.b32 	%r95, %f44;
+	shfl.sync.bfly.b32	%r96, %r95, 8, 31, -1;
+	mov.b32 	%f45, %r96;
+$L__tmp22:
+	.loc	2 233 15
+	add.f32 	%f46, %f44, %f45;
+$L__tmp23:
+	.loc	2 243 36
+	mov.b32 	%r97, %f46;
+	shfl.sync.bfly.b32	%r98, %r97, 4, 31, -1;
+	mov.b32 	%f47, %r98;
+$L__tmp24:
+	.loc	2 233 15
+	add.f32 	%f48, %f46, %f47;
+$L__tmp25:
+	.loc	2 243 36
+	mov.b32 	%r99, %f48;
+	shfl.sync.bfly.b32	%r100, %r99, 2, 31, -1;
+	mov.b32 	%f49, %r100;
+$L__tmp26:
+	.loc	2 233 15
+	add.f32 	%f50, %f48, %f49;
+$L__tmp27:
+	.loc	2 243 36
+	mov.b32 	%r101, %f50;
+	shfl.sync.bfly.b32	%r102, %r101, 1, 31, -1;
+	mov.b32 	%f51, %r102;
+$L__tmp28:
+	.loc	2 233 15
+	add.f32 	%f52, %f50, %f51;
+$L__tmp29:
+	.loc	2 243 36
+	mov.b32 	%r45, %f52;
+	@%p23 st.shared.b32 [ %r38 + 0 ], %r45;
+	bar.sync 	0;
+	@%p24 ld.shared.b32 %r46, [ %r41 + 0 ];
+	mov.b32 	%f53, %r46;
+	shfl.sync.bfly.b32	%r103, %r46, 1, 31, -1;
+	mov.b32 	%f54, %r103;
+$L__tmp30:
+	.loc	2 233 15
+	add.f32 	%f55, %f53, %f54;
+$L__tmp31:
+	.loc	2 243 36
+	mov.b32 	%r49, %f55;
+	@%p25 st.shared.b32 [ %r41 + 0 ], %r49;
+	bar.sync 	0;
+	ld.shared.f32 	%f56, [global_smem];
+$L__tmp32:
+	.loc	3 8 15
+	add.f32 	%f57, %f56, 0f00000000;
+	mov.b32 	%r52, 1132462080;
+$L__tmp33:
+	.loc	1 45 20
+	div.full.f32 %r50, %r51, %r52;
+	mov.b32 	%f58, %r50;
+	.loc	1 47 20
+	neg.f32 	%f59, %f38;
+	fma.rn.f32 	%f60, %f17, 0f43800000, %f59;
+	fma.rn.f32 	%f61, %f18, 0f43800000, %f59;
+	fma.rn.f32 	%f62, %f19, 0f43800000, %f59;
+	fma.rn.f32 	%f63, %f20, 0f43800000, %f59;
+	.loc	1 49 20
+	neg.f32 	%f64, %f57;
+	fma.rn.f32 	%f65, %f64, %f9, %f60;
+	fma.rn.f32 	%f66, %f64, %f10, %f61;
+	fma.rn.f32 	%f67, %f64, %f11, %f62;
+	fma.rn.f32 	%f68, %f64, %f12, %f63;
+	.loc	1 51 20
+	fma.rn.f32 	%f69, %f58, %f65, %f13;
+	fma.rn.f32 	%f70, %f58, %f66, %f14;
+	fma.rn.f32 	%f71, %f58, %f67, %f15;
+	fma.rn.f32 	%f72, %f58, %f68, %f16;
+	.loc	1 53 51
+	mov.b32 	%r62, %f69;
+	mov.b32 	%r63, %f70;
+	mov.b32 	%r64, %f71;
+	mov.b32 	%r65, %f72;
+	@%p1 st.global.v4.b32 [ %rd4 + 0 ], { %r62, %r63, %r64, %r65 };
+	.loc	1 54 25
+	add.s64 	%rd10, %rd16, %rd17;
+	.loc	1 54 48
+	cvt.rn.bf16.f32 %rs5, %r62;
+	cvt.rn.bf16.f32 %rs6, %r63;
+	cvt.rn.bf16.f32 %rs7, %r64;
+	cvt.rn.bf16.f32 %rs8, %r65;
+	mov.b32 	%r104, {%rs5, %rs6};
+	mov.b32 	%r105, {%rs7, %rs8};
+	@%p1 st.global.v2.b32 [ %rd10 + 0 ], { %r104, %r105 };
+	.loc	1 54 4
+	ret;
+$L__tmp34:
+$L__func_end0:
+
+}
+	.file	1 "/tmp/torchinductor_root/rn/crnynbmsd2yell2lpjymb46rttfaea2xjwsbxr75j54gctfgi457.py"
+	.file	2 "/usr/local/lib/python3.10/dist-packages/triton/language/standard.py"
+	.file	3 "/usr/local/lib/python3.10/dist-packages/torch/_inductor/triton_helpers.py"
+	.section	.debug_abbrev
+	{
+.b8 1
+.b8 17
+.b8 1
+.b8 37
+.b8 8
+.b8 19
+.b8 5
+.b8 3
+.b8 8
+.b8 16
+.b8 6
+.b8 27
+.b8 8
+.b8 180
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+.b8 0
+.b8 0
+.b8 4
+.b8 29
+.b8 1
+.b8 49
+.b8 19
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+.b8 11
+.b8 0
+.b8 0
+.b8 5
+.b8 29
+.b8 0
+.b8 49
+.b8 19
+.b8 17
+.b8 1
+.b8 18
+.b8 1
+.b8 88
+.b8 11
+.b8 89
+.b8 11
+.b8 87
+.b8 11
+.b8 0
+.b8 0
+.b8 0
+	}
+	.section	.debug_info
+	{
+.b32 399
+.b8 2
+.b8 0
+.b32 .debug_abbrev
+.b8 8
+.b8 1
+.b8 116
+.b8 114
+.b8 105
+.b8 116
+.b8 111
+.b8 110
+.b8 0
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+.b8 102
+.b8 103
+.b8 105
+.b8 52
+.b8 53
+.b8 55
+.b8 46
+.b8 112
+.b8 121
+.b8 0
+.b32 .debug_line
+.b8 47
+.b8 116
+.b8 109
+.b8 112
+.b8 47
+.b8 116
+.b8 111
+.b8 114
+.b8 99
+.b8 104
+.b8 105
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+.b8 99
+.b8 116
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+.b8 95
+.b8 114
+.b8 111
+.b8 111
+.b8 116
+.b8 47
+.b8 114
+.b8 110
+.b8 0
+.b8 1
+.b64 $L__func_begin0
+.b64 $L__func_end0
+.b8 2
+.b8 116
+.b8 114
+.b8 105
+.b8 116
+.b8 111
+.b8 110
+.b8 95
+.b8 95
+.b8 48
+.b8 100
+.b8 49
+.b8 100
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+.b8 51
+.b8 100
+.b8 52
+.b8 100
+.b8 53
+.b8 100
+.b8 54
+.b8 100
+.b8 101
+.b8 55
+.b8 100
+.b8 101
+.b8 0
+.b8 116
+.b8 114
+.b8 105
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+.b8 111
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+.b8 95
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+.b8 48
+.b8 100
+.b8 49
+.b8 100
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+.b8 100
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+.b8 100
+.b8 53
+.b8 100
+.b8 54
+.b8 100
+.b8 101
+.b8 55
+.b8 100
+.b8 101
+.b8 0
+.b8 1
+.b8 18
+.b8 1
+.b8 1
+.b8 3
+.b64 $L__func_begin0
+.b64 $L__func_end0
+.b8 1
+.b8 156
+.b32 125
+.b8 4
+.b32 125
+.b64 $L__tmp1
+.b64 $L__tmp14
+.b8 2
+.b8 39
+.b8 57
+.b8 5
+.b32 125
+.b64 $L__tmp1
+.b64 $L__tmp14
+.b8 2
+.b8 243
+.b8 36
+.b8 0
+.b8 5
+.b32 125
+.b64 $L__tmp2
+.b64 $L__tmp15
+.b8 2
+.b8 39
+.b8 57
+.b8 5
+.b32 125
+.b64 $L__tmp15
+.b64 $L__tmp16
+.b8 3
+.b8 39
+.b8 44
+.b8 5
+.b32 125
+.b64 $L__tmp17
+.b64 $L__tmp32
+.b8 2
+.b8 43
+.b8 59
+.b8 4
+.b32 125
+.b64 $L__tmp18
+.b64 $L__tmp31
+.b8 2
+.b8 43
+.b8 59
+.b8 5
+.b32 125
+.b64 $L__tmp18
+.b64 $L__tmp31
+.b8 2
+.b8 243
+.b8 36
+.b8 0
+.b8 5
+.b32 125
+.b64 $L__tmp32
+.b64 $L__tmp33
+.b8 3
+.b8 43
+.b8 45
+.b8 0
+.b8 0
+	}
+	.section	.debug_pubnames
+	{
+.b32 $L__pubNames_end0-$L__pubNames_start0
+$L__pubNames_start0:
+.b8 2
+.b8 0
+.b32 .debug_info
+.b32 403
+.b32 125
+.b8 116
+.b8 114
+.b8 105
+.b8 116
+.b8 111
+.b8 110
+.b8 95
+.b8 95
+.b8 48
+.b8 100
+.b8 49
+.b8 100
+.b8 50
+.b8 100
+.b8 51
+.b8 100
+.b8 52
+.b8 100
+.b8 53
+.b8 100
+.b8 54
+.b8 100
+.b8 101
+.b8 55
+.b8 100
+.b8 101
+.b8 0
+.b32 0
+$L__pubNames_end0:
+	}
+	.section	.debug_pubtypes
+	{
+.b32 $L__pubTypes_end0-$L__pubTypes_start0
+$L__pubTypes_start0:
+.b8 2
+.b8 0
+.b32 .debug_info
+.b32 403
+.b32 0
+$L__pubTypes_end0:
+	}
+	.section	.debug_loc	{	}

.triton/dump/63ac7476060ddeef758fa13ad6ed58f5/triton_.ttgir

@@ -0,0 +1,66 @@
+#blocked = #triton_gpu.blocked<{sizePerThread = [4], threadsPerWarp = [32], warpsPerCTA = [2], order = [0], CTAsPerCGA = [1], CTASplitNum = [1], CTAOrder = [0]}>
+module attributes {"triton_gpu.compute-capability" = 89 : i32, "triton_gpu.num-ctas" = 1 : i32, "triton_gpu.num-warps" = 2 : i32, "triton_gpu.threads-per-warp" = 32 : i32} {
+  tt.func public @triton__0d1d2d3d4d5d6de7de(%arg0: !tt.ptr<f32, 1> {tt.divisibility = 16 : i32}, %arg1: !tt.ptr<bf16, 1> {tt.divisibility = 16 : i32}, %arg2: !tt.ptr<f32, 1> {tt.divisibility = 16 : i32}, %arg3: !tt.ptr<f32, 1> {tt.divisibility = 16 : i32}, %arg4: !tt.ptr<f32, 1> {tt.divisibility = 16 : i32}, %arg5: !tt.ptr<bf16, 1> {tt.divisibility = 16 : i32}, %arg6: i32 {tt.divisibility = 16 : i32, tt.max_divisibility = 16 : i32}, %arg7: i32 {tt.divisibility = 16 : i32, tt.max_divisibility = 16 : i32}) attributes {noinline = false} {
+    %cst = arith.constant dense<256> : tensor<256xi32, #blocked>
+    %cst_0 = arith.constant dense<2.560000e+02> : tensor<1xf32, #blocked>
+    %cst_1 = arith.constant 0.000000e+00 : f32
+    %c256_i32 = arith.constant 256 : i32
+    %cst_2 = arith.constant dense<0.000000e+00> : tensor<256xf32, #blocked>
+    %cst_3 = arith.constant dense<2.560000e+02> : tensor<256xf32, #blocked>
+    %cst_4 = arith.constant dense<0.000000e+00> : tensor<256xbf16, #blocked>
+    %0 = tt.get_program_id x : i32
+    %1 = tt.make_range {end = 256 : i32, start = 0 : i32} : tensor<256xi32, #blocked>
+    %2 = arith.cmpi slt, %1, %cst : tensor<256xi32, #blocked>
+    %3 = arith.muli %0, %c256_i32 : i32
+    %4 = tt.splat %3 : (i32) -> tensor<256xi32, #blocked>
+    %5 = arith.addi %1, %4 : tensor<256xi32, #blocked>
+    %6 = tt.splat %arg1 : (!tt.ptr<bf16, 1>) -> tensor<256x!tt.ptr<bf16, 1>, #blocked>
+    %7 = tt.addptr %6, %5 : tensor<256x!tt.ptr<bf16, 1>, #blocked>, tensor<256xi32, #blocked>
+    %8 = tt.load %7, %2, %cst_4 {cache = 1 : i32, evict = 1 : i32, isVolatile = false} : tensor<256xbf16, #blocked>
+    %9 = arith.extf %8 : tensor<256xbf16, #blocked> to tensor<256xf32, #blocked>
+    %10 = tt.splat %arg2 : (!tt.ptr<f32, 1>) -> tensor<256x!tt.ptr<f32, 1>, #blocked>
+    %11 = tt.addptr %10, %1 : tensor<256x!tt.ptr<f32, 1>, #blocked>, tensor<256xi32, #blocked>
+    %12 = tt.load %11, %2, %cst_2 {cache = 1 : i32, evict = 3 : i32, isVolatile = false} : tensor<256xf32, #blocked>
+    %13 = tt.splat %arg3 : (!tt.ptr<f32, 1>) -> tensor<256x!tt.ptr<f32, 1>, #blocked>
+    %14 = tt.addptr %13, %5 : tensor<256x!tt.ptr<f32, 1>, #blocked>, tensor<256xi32, #blocked>
+    %15 = tt.load %14, %2, %cst_2 {cache = 1 : i32, evict = 1 : i32, isVolatile = false} : tensor<256xf32, #blocked>
+    %16 = tt.splat %arg0 : (!tt.ptr<f32, 1>) -> tensor<256x!tt.ptr<f32, 1>, #blocked>
+    %17 = tt.addptr %16, %5 : tensor<256x!tt.ptr<f32, 1>, #blocked>, tensor<256xi32, #blocked>
+    %18 = tt.load %17, %2, %cst_2 {cache = 1 : i32, evict = 1 : i32, isVolatile = false} : tensor<256xf32, #blocked>
+    %19 = tt.addptr %arg4, %0 : !tt.ptr<f32, 1>, i32
+    %20 = tt.splat %19 : (!tt.ptr<f32, 1>) -> tensor<1x!tt.ptr<f32, 1>, #blocked>
+    %21 = tt.load %20 {cache = 1 : i32, evict = 3 : i32, isVolatile = false} : tensor<1xf32, #blocked>
+    %22 = arith.mulf %9, %12 : tensor<256xf32, #blocked>
+    %23 = arith.select %2, %22, %cst_2 : tensor<256xi1, #blocked>, tensor<256xf32, #blocked>
+    %24 = "tt.reduce"(%23) <{axis = 0 : i32}> ({
+    ^bb0(%arg8: f32, %arg9: f32):
+      %43 = arith.addf %arg8, %arg9 : f32
+      tt.reduce.return %43 : f32
+    }) : (tensor<256xf32, #blocked>) -> f32
+    %25 = arith.addf %24, %cst_1 : f32
+    %26 = arith.mulf %22, %15 : tensor<256xf32, #blocked>
+    %27 = arith.select %2, %26, %cst_2 : tensor<256xi1, #blocked>, tensor<256xf32, #blocked>
+    %28 = "tt.reduce"(%27) <{axis = 0 : i32}> ({
+    ^bb0(%arg8: f32, %arg9: f32):
+      %43 = arith.addf %arg8, %arg9 : f32
+      tt.reduce.return %43 : f32
+    }) : (tensor<256xf32, #blocked>) -> f32
+    %29 = arith.addf %28, %cst_1 : f32
+    %30 = arith.divf %21, %cst_0 : tensor<1xf32, #blocked>
+    %31 = arith.mulf %22, %cst_3 : tensor<256xf32, #blocked>
+    %32 = tt.splat %25 : (f32) -> tensor<256xf32, #blocked>
+    %33 = arith.subf %31, %32 : tensor<256xf32, #blocked>
+    %34 = tt.splat %29 : (f32) -> tensor<256xf32, #blocked>
+    %35 = arith.mulf %15, %34 : tensor<256xf32, #blocked>
+    %36 = arith.subf %33, %35 : tensor<256xf32, #blocked>
+    %37 = tt.broadcast %30 : (tensor<1xf32, #blocked>) -> tensor<256xf32, #blocked>
+    %38 = arith.mulf %37, %36 : tensor<256xf32, #blocked>
+    %39 = arith.addf %18, %38 : tensor<256xf32, #blocked>
+    tt.store %17, %39, %2 {cache = 1 : i32, evict = 1 : i32} : tensor<256xf32, #blocked>
+    %40 = tt.splat %arg5 : (!tt.ptr<bf16, 1>) -> tensor<256x!tt.ptr<bf16, 1>, #blocked>
+    %41 = tt.addptr %40, %5 : tensor<256x!tt.ptr<bf16, 1>, #blocked>, tensor<256xi32, #blocked>
+    %42 = arith.truncf %39 : tensor<256xf32, #blocked> to tensor<256xbf16, #blocked>
+    tt.store %41, %42, %2 {cache = 1 : i32, evict = 1 : i32} : tensor<256xbf16, #blocked>
+    tt.return
+  }
+}

.triton/dump/7b1a931e36ddc741e8bf98e3cbffe01d/triton_.ttir

@@ -0,0 +1,15 @@
+module {
+  tt.func public @triton__0d1de(%arg0: !tt.ptr<f32, 1> {tt.divisibility = 16 : i32}, %arg1: i32 {tt.divisibility = 16 : i32, tt.max_divisibility = 16 : i32}) attributes {noinline = false} {
+    %cst = arith.constant dense<0.000000e+00> : tensor<1024xf32>
+    %c1024_i32 = arith.constant 1024 : i32
+    %0 = tt.get_program_id x : i32
+    %1 = arith.muli %0, %c1024_i32 : i32
+    %2 = tt.make_range {end = 1024 : i32, start = 0 : i32} : tensor<1024xi32>
+    %3 = tt.splat %1 : (i32) -> tensor<1024xi32>
+    %4 = arith.addi %3, %2 : tensor<1024xi32>
+    %5 = tt.splat %arg0 : (!tt.ptr<f32, 1>) -> tensor<1024x!tt.ptr<f32, 1>>
+    %6 = tt.addptr %5, %4 : tensor<1024x!tt.ptr<f32, 1>>, tensor<1024xi32>
+    tt.store %6, %cst {cache = 1 : i32, evict = 1 : i32} : tensor<1024xf32>
+    tt.return
+  }
+}

.triton/dump/93e5abc5363b9438178c618128714f73/triton_.ttgir

@@ -0,0 +1,38 @@
+#blocked = #triton_gpu.blocked<{sizePerThread = [8], threadsPerWarp = [32], warpsPerCTA = [4], order = [0], CTAsPerCGA = [1], CTASplitNum = [1], CTAOrder = [0]}>
+module attributes {"triton_gpu.compute-capability" = 89 : i32, "triton_gpu.num-ctas" = 1 : i32, "triton_gpu.num-warps" = 4 : i32, "triton_gpu.threads-per-warp" = 32 : i32} {
+  tt.func public @triton__0d1d2de(%arg0: !tt.ptr<bf16, 1> {tt.divisibility = 16 : i32}, %arg1: !tt.ptr<bf16, 1> {tt.divisibility = 16 : i32}, %arg2: i32 {tt.divisibility = 16 : i32, tt.max_divisibility = 16 : i32}) attributes {noinline = false} {
+    %cst = arith.constant dense<0.398942292> : tensor<1024xf32, #blocked>
+    %cst_0 = arith.constant dense<-5.000000e-01> : tensor<1024xf32, #blocked>
+    %cst_1 = arith.constant dense<5.000000e-01> : tensor<1024xf32, #blocked>
+    %cst_2 = arith.constant dense<1.000000e+00> : tensor<1024xf32, #blocked>
+    %cst_3 = arith.constant dense<0.707106769> : tensor<1024xf32, #blocked>
+    %c1024_i32 = arith.constant 1024 : i32
+    %0 = tt.get_program_id x : i32
+    %1 = arith.muli %0, %c1024_i32 : i32
+    %2 = tt.make_range {end = 1024 : i32, start = 0 : i32} : tensor<1024xi32, #blocked>
+    %3 = tt.splat %1 : (i32) -> tensor<1024xi32, #blocked>
+    %4 = arith.addi %3, %2 : tensor<1024xi32, #blocked>
+    %5 = tt.splat %arg0 : (!tt.ptr<bf16, 1>) -> tensor<1024x!tt.ptr<bf16, 1>, #blocked>
+    %6 = tt.addptr %5, %4 : tensor<1024x!tt.ptr<bf16, 1>, #blocked>, tensor<1024xi32, #blocked>
+    %7 = tt.load %6 {cache = 1 : i32, evict = 1 : i32, isVolatile = false} : tensor<1024xbf16, #blocked>
+    %8 = arith.extf %7 : tensor<1024xbf16, #blocked> to tensor<1024xf32, #blocked>
+    %9 = tt.splat %arg1 : (!tt.ptr<bf16, 1>) -> tensor<1024x!tt.ptr<bf16, 1>, #blocked>
+    %10 = tt.addptr %9, %4 : tensor<1024x!tt.ptr<bf16, 1>, #blocked>, tensor<1024xi32, #blocked>
+    %11 = tt.load %10 {cache = 1 : i32, evict = 1 : i32, isVolatile = false} : tensor<1024xbf16, #blocked>
+    %12 = arith.extf %11 : tensor<1024xbf16, #blocked> to tensor<1024xf32, #blocked>
+    %13 = arith.mulf %12, %cst_3 : tensor<1024xf32, #blocked>
+    %14 = tt.extern_elementwise %13 {libname = "libdevice", libpath = "/usr/local/lib/python3.10/dist-packages/triton/language/../third_party/cuda/lib/libdevice.10.bc", pure = true, symbol = "__nv_erff"} : (tensor<1024xf32, #blocked>) -> tensor<1024xf32, #blocked>
+    %15 = arith.addf %14, %cst_2 : tensor<1024xf32, #blocked>
+    %16 = arith.mulf %15, %cst_1 : tensor<1024xf32, #blocked>
+    %17 = arith.mulf %12, %12 : tensor<1024xf32, #blocked>
+    %18 = arith.mulf %17, %cst_0 : tensor<1024xf32, #blocked>
+    %19 = math.exp %18 : tensor<1024xf32, #blocked>
+    %20 = arith.mulf %19, %cst : tensor<1024xf32, #blocked>
+    %21 = arith.mulf %12, %20 : tensor<1024xf32, #blocked>
+    %22 = arith.addf %16, %21 : tensor<1024xf32, #blocked>
+    %23 = arith.mulf %8, %22 : tensor<1024xf32, #blocked>
+    %24 = arith.truncf %23 : tensor<1024xf32, #blocked> to tensor<1024xbf16, #blocked>
+    tt.store %6, %24 {cache = 1 : i32, evict = 1 : i32} : tensor<1024xbf16, #blocked>
+    tt.return
+  }
+}

.triton/dump/93e5abc5363b9438178c618128714f73/triton_.ttir

@@ -0,0 +1,37 @@
+module {
+  tt.func public @triton__0d1d2de(%arg0: !tt.ptr<bf16, 1> {tt.divisibility = 16 : i32}, %arg1: !tt.ptr<bf16, 1> {tt.divisibility = 16 : i32}, %arg2: i32 {tt.divisibility = 16 : i32, tt.max_divisibility = 16 : i32}) attributes {noinline = false} {
+    %cst = arith.constant dense<0.398942292> : tensor<1024xf32>
+    %cst_0 = arith.constant dense<-5.000000e-01> : tensor<1024xf32>
+    %cst_1 = arith.constant dense<5.000000e-01> : tensor<1024xf32>
+    %cst_2 = arith.constant dense<1.000000e+00> : tensor<1024xf32>
+    %cst_3 = arith.constant dense<0.707106769> : tensor<1024xf32>
+    %c1024_i32 = arith.constant 1024 : i32
+    %0 = tt.get_program_id x : i32
+    %1 = arith.muli %0, %c1024_i32 : i32
+    %2 = tt.make_range {end = 1024 : i32, start = 0 : i32} : tensor<1024xi32>
+    %3 = tt.splat %1 : (i32) -> tensor<1024xi32>
+    %4 = arith.addi %3, %2 : tensor<1024xi32>
+    %5 = tt.splat %arg0 : (!tt.ptr<bf16, 1>) -> tensor<1024x!tt.ptr<bf16, 1>>
+    %6 = tt.addptr %5, %4 : tensor<1024x!tt.ptr<bf16, 1>>, tensor<1024xi32>
+    %7 = tt.load %6 {cache = 1 : i32, evict = 1 : i32, isVolatile = false} : tensor<1024xbf16>
+    %8 = arith.extf %7 : tensor<1024xbf16> to tensor<1024xf32>
+    %9 = tt.splat %arg1 : (!tt.ptr<bf16, 1>) -> tensor<1024x!tt.ptr<bf16, 1>>
+    %10 = tt.addptr %9, %4 : tensor<1024x!tt.ptr<bf16, 1>>, tensor<1024xi32>
+    %11 = tt.load %10 {cache = 1 : i32, evict = 1 : i32, isVolatile = false} : tensor<1024xbf16>
+    %12 = arith.extf %11 : tensor<1024xbf16> to tensor<1024xf32>
+    %13 = arith.mulf %12, %cst_3 : tensor<1024xf32>
+    %14 = tt.extern_elementwise %13 {libname = "libdevice", libpath = "/usr/local/lib/python3.10/dist-packages/triton/language/../third_party/cuda/lib/libdevice.10.bc", pure = true, symbol = "__nv_erff"} : (tensor<1024xf32>) -> tensor<1024xf32>
+    %15 = arith.addf %14, %cst_2 : tensor<1024xf32>
+    %16 = arith.mulf %15, %cst_1 : tensor<1024xf32>
+    %17 = arith.mulf %12, %12 : tensor<1024xf32>
+    %18 = arith.mulf %17, %cst_0 : tensor<1024xf32>
+    %19 = math.exp %18 : tensor<1024xf32>
+    %20 = arith.mulf %19, %cst : tensor<1024xf32>
+    %21 = arith.mulf %12, %20 : tensor<1024xf32>
+    %22 = arith.addf %16, %21 : tensor<1024xf32>
+    %23 = arith.mulf %8, %22 : tensor<1024xf32>
+    %24 = arith.truncf %23 : tensor<1024xf32> to tensor<1024xbf16>
+    tt.store %6, %24 {cache = 1 : i32, evict = 1 : i32} : tensor<1024xbf16>
+    tt.return
+  }
+}

.triton/dump/962d1809855a53123762906133b1d960/triton_.ttir

@@ -0,0 +1,17 @@
+module {
+  tt.func public @triton__0d1de(%arg0: !tt.ptr<f32, 1> {tt.divisibility = 16 : i32}, %arg1: i32 {tt.divisibility = 16 : i32, tt.max_divisibility = 16 : i32}) attributes {noinline = false} {
+    %cst = arith.constant dense<0.000000e+00> : tensor<1024xf32>
+    %cst_0 = arith.constant dense<12865792> : tensor<1024xi32>
+    %c1024_i32 = arith.constant 1024 : i32
+    %0 = tt.get_program_id x : i32
+    %1 = arith.muli %0, %c1024_i32 : i32
+    %2 = tt.make_range {end = 1024 : i32, start = 0 : i32} : tensor<1024xi32>
+    %3 = tt.splat %1 : (i32) -> tensor<1024xi32>
+    %4 = arith.addi %3, %2 : tensor<1024xi32>
+    %5 = arith.cmpi slt, %4, %cst_0 : tensor<1024xi32>
+    %6 = tt.splat %arg0 : (!tt.ptr<f32, 1>) -> tensor<1024x!tt.ptr<f32, 1>>
+    %7 = tt.addptr %6, %4 : tensor<1024x!tt.ptr<f32, 1>>, tensor<1024xi32>
+    tt.store %7, %cst, %5 {cache = 1 : i32, evict = 1 : i32} : tensor<1024xf32>
+    tt.return
+  }
+}

.triton/dump/99e09ac62cbb6a1b0eda5bd8218743c3/triton_.llir

@@ -0,0 +1,368 @@
+; ModuleID = 'LLVMDialectModule'
+source_filename = "LLVMDialectModule"
+
+@global_smem = external local_unnamed_addr addrspace(3) global [0 x i8]
+
+define void @triton__0d1d2d3d4d5d6d7d8d9d10de11de(ptr addrspace(1) %0, ptr addrspace(1) %1, ptr addrspace(1) %2, ptr addrspace(1) %3, ptr addrspace(1) %4, ptr addrspace(1) %5, ptr addrspace(1) %6, ptr addrspace(1) %7, ptr addrspace(1) %8, ptr addrspace(1) %9, i32 %10, i32 %11) local_unnamed_addr !dbg !5 {
+  %13 = tail call i32 @llvm.nvvm.read.ptx.sreg.tid.x(), !dbg !8
+  %14 = and i32 %13, 31, !dbg !8
+  %15 = lshr i32 %13, 5, !dbg !8
+  %16 = shl i32 %13, 2, !dbg !8
+  %17 = and i32 %16, 60, !dbg !8
+  %18 = and i32 %15, 3, !dbg !8
+  %19 = lshr i32 %14, 1, !dbg !8
+  %20 = shl nuw nsw i32 %18, 4, !dbg !8
+  %21 = or i32 %20, %19, !dbg !8
+  %22 = and i32 %16, 4, !dbg !9
+  %23 = lshr i32 %14, 4, !dbg !9
+  %24 = shl nuw nsw i32 %18, 1, !dbg !9
+  %25 = or i32 %24, %23, !dbg !9
+  %26 = tail call i32 asm "mov.u32 $0, %ctaid.x;", "=r"() #3, !dbg !10
+  %27 = shl i32 %26, 6, !dbg !11
+  %28 = or i32 %27, %17, !dbg !12
+  %29 = or i32 %27, %21, !dbg !12
+  %.frozen = freeze i32 %28
+  %30 = sdiv i32 %.frozen, 256, !dbg !13
+  %31 = mul i32 %30, 256
+  %.decomposed = sub i32 %.frozen, %31
+  %32 = sdiv i32 %29, 256, !dbg !13
+  %33 = shl i32 %30, 15, !dbg !14
+  %34 = shl nsw i32 %32, 7, !dbg !15
+  %35 = add i32 %33, %.decomposed
+  %36 = mul nuw nsw i32 %17, 12
+  %37 = or i32 %25, %36
+  %38 = zext nneg i32 %37 to i64
+  %39 = getelementptr i16, ptr addrspace(3) @global_smem, i64 %38
+  %40 = or i32 %36, 12
+  %41 = add nuw nsw i32 %40, %25
+  %42 = zext nneg i32 %41 to i64
+  %43 = getelementptr i16, ptr addrspace(3) @global_smem, i64 %42
+  %44 = add nuw nsw i32 %36, 24
+  %45 = or i32 %44, %25
+  %46 = zext nneg i32 %45 to i64
+  %47 = getelementptr i16, ptr addrspace(3) @global_smem, i64 %46
+  %48 = add nuw nsw i32 %36, 36
+  %49 = add nuw nsw i32 %48, %25
+  %50 = zext nneg i32 %49 to i64
+  %51 = getelementptr i16, ptr addrspace(3) @global_smem, i64 %50
+  %52 = mul nuw nsw i32 %21, 12
+  %53 = add nuw nsw i32 %52, %22
+  %54 = zext nneg i32 %53 to i64
+  %55 = getelementptr i16, ptr addrspace(3) @global_smem, i64 %54
+  %56 = getelementptr float, ptr addrspace(3) @global_smem, i64 %38
+  %57 = getelementptr float, ptr addrspace(3) @global_smem, i64 %42
+  %58 = getelementptr float, ptr addrspace(3) @global_smem, i64 %46
+  %59 = getelementptr float, ptr addrspace(3) @global_smem, i64 %50
+  %60 = getelementptr float, ptr addrspace(3) @global_smem, i64 %54
+  %61 = getelementptr inbounds <4 x i16>, ptr addrspace(3) %55, i64 0, i64 1
+  %62 = getelementptr inbounds <4 x i16>, ptr addrspace(3) %55, i64 0, i64 2
+  %63 = getelementptr inbounds <4 x i16>, ptr addrspace(3) %55, i64 0, i64 3
+  br label %64, !dbg !16
+
+64:                                               ; preds = %12, %64
+  %65 = phi i32 [ 0, %12 ], [ %205, %64 ]
+  %66 = phi <8 x float> [ zeroinitializer, %12 ], [ %204, %64 ]
+  %67 = or i32 %65, %22, !dbg !17
+  %68 = or i32 %65, %25, !dbg !17
+  %69 = shl i32 %68, 8, !dbg !18
+  %70 = add i32 %35, %69, !dbg !19
+  %71 = sext i32 %70 to i64, !dbg !20
+  %72 = getelementptr i16, ptr addrspace(1) %0, i64 %71, !dbg !20
+  %73 = tail call { i32, i32 } asm sideeffect "mov.u32 $0, 0x0;\0A\09mov.u32 $1, 0x0;\0A\09@$3 ld.global.L1::evict_first.v2.b32 { $0, $1 }, [ $2 + 0 ];\0A\09@!$5 mov.u32 $0, $4;\0A\09@!$7 mov.u32 $1, $6;", "=r,=r,l,b,r,b,r,b"(ptr addrspace(1) %72, i1 true, i32 0, i1 true, i32 0, i1 true) #3, !dbg !21
+  %74 = extractvalue { i32, i32 } %73, 0, !dbg !21
+  %75 = extractvalue { i32, i32 } %73, 1, !dbg !21
+  %76 = trunc i32 %74 to i16, !dbg !21
+  %extelt.offset = lshr i32 %74, 16, !dbg !21
+  %77 = trunc i32 %extelt.offset to i16, !dbg !21
+  %78 = trunc i32 %75 to i16, !dbg !21
+  %extelt.offset1 = lshr i32 %75, 16, !dbg !21
+  %79 = trunc i32 %extelt.offset1 to i16, !dbg !21
+  tail call void @llvm.nvvm.barrier0(), !dbg !22
+  %80 = insertelement <1 x i16> undef, i16 %76, i64 0, !dbg !22
+  store <1 x i16> %80, ptr addrspace(3) %39, align 2, !dbg !22
+  %81 = insertelement <1 x i16> undef, i16 %77, i64 0, !dbg !22
+  store <1 x i16> %81, ptr addrspace(3) %43, align 2, !dbg !22
+  %82 = insertelement <1 x i16> undef, i16 %78, i64 0, !dbg !22
+  store <1 x i16> %82, ptr addrspace(3) %47, align 2, !dbg !22
+  %83 = insertelement <1 x i16> undef, i16 %79, i64 0, !dbg !22
+  store <1 x i16> %83, ptr addrspace(3) %51, align 2, !dbg !22
+  tail call void @llvm.nvvm.barrier0(), !dbg !22
+  %84 = load i16, ptr addrspace(3) %55, align 8, !dbg !22
+  %85 = load i16, ptr addrspace(3) %61, align 2, !dbg !22
+  %86 = load i16, ptr addrspace(3) %62, align 4, !dbg !22
+  %87 = load i16, ptr addrspace(3) %63, align 2, !dbg !22
+  %88 = tail call float asm "cvt.f32.bf16 $0, $1;", "=r,h"(i16 %84) #3, !dbg !22
+  %89 = tail call float asm "cvt.f32.bf16 $0, $1;", "=r,h"(i16 %85) #3, !dbg !22
+  %90 = tail call float asm "cvt.f32.bf16 $0, $1;", "=r,h"(i16 %86) #3, !dbg !22
+  %91 = tail call float asm "cvt.f32.bf16 $0, $1;", "=r,h"(i16 %87) #3, !dbg !22
+  %92 = getelementptr float, ptr addrspace(1) %1, i64 %71, !dbg !23
+  %93 = tail call { i32, i32, i32, i32 } asm sideeffect "mov.u32 $0, 0x0;\0A\09mov.u32 $1, 0x0;\0A\09mov.u32 $2, 0x0;\0A\09mov.u32 $3, 0x0;\0A\09@$5 ld.global.L1::evict_first.v4.b32 { $0, $1, $2, $3 }, [ $4 + 0 ];\0A\09@!$7 mov.u32 $0, $6;\0A\09@!$9 mov.u32 $1, $8;\0A\09@!$11 mov.u32 $2, $10;\0A\09@!$13 mov.u32 $3, $12;", "=r,=r,=r,=r,l,b,r,b,r,b,r,b,r,b"(ptr addrspace(1) %92, i1 true, i32 0, i1 true, i32 0, i1 true, i32 0, i1 true, i32 0, i1 true) #3, !dbg !24
+  %94 = extractvalue { i32, i32, i32, i32 } %93, 0, !dbg !24
+  %95 = extractvalue { i32, i32, i32, i32 } %93, 1, !dbg !24
+  %96 = extractvalue { i32, i32, i32, i32 } %93, 2, !dbg !24
+  %97 = extractvalue { i32, i32, i32, i32 } %93, 3, !dbg !24
+  %98 = bitcast i32 %94 to float, !dbg !24
+  %99 = bitcast i32 %95 to float, !dbg !24
+  %100 = bitcast i32 %96 to float, !dbg !24
+  %101 = bitcast i32 %97 to float, !dbg !24
+  tail call void @llvm.nvvm.barrier0(), !dbg !24
+  %102 = insertelement <1 x float> undef, float %98, i64 0, !dbg !24
+  store <1 x float> %102, ptr addrspace(3) %56, align 4, !dbg !24
+  %103 = insertelement <1 x float> undef, float %99, i64 0, !dbg !24
+  store <1 x float> %103, ptr addrspace(3) %57, align 4, !dbg !24
+  %104 = insertelement <1 x float> undef, float %100, i64 0, !dbg !24
+  store <1 x float> %104, ptr addrspace(3) %58, align 4, !dbg !24
+  %105 = insertelement <1 x float> undef, float %101, i64 0, !dbg !24
+  store <1 x float> %105, ptr addrspace(3) %59, align 4, !dbg !24
+  tail call void @llvm.nvvm.barrier0(), !dbg !24
+  %106 = load <4 x float>, ptr addrspace(3) %60, align 16, !dbg !24
+  %107 = getelementptr i16, ptr addrspace(1) %2, i64 %71, !dbg !25
+  %108 = tail call { i32, i32 } asm sideeffect "mov.u32 $0, 0x0;\0A\09mov.u32 $1, 0x0;\0A\09@$3 ld.global.L1::evict_first.v2.b32 { $0, $1 }, [ $2 + 0 ];\0A\09@!$5 mov.u32 $0, $4;\0A\09@!$7 mov.u32 $1, $6;", "=r,=r,l,b,r,b,r,b"(ptr addrspace(1) %107, i1 true, i32 0, i1 true, i32 0, i1 true) #3, !dbg !26
+  %109 = extractvalue { i32, i32 } %108, 0, !dbg !26
+  %110 = extractvalue { i32, i32 } %108, 1, !dbg !26
+  %111 = trunc i32 %109 to i16, !dbg !26
+  %extelt.offset2 = lshr i32 %109, 16, !dbg !26
+  %112 = trunc i32 %extelt.offset2 to i16, !dbg !26
+  %113 = trunc i32 %110 to i16, !dbg !26
+  %extelt.offset3 = lshr i32 %110, 16, !dbg !26
+  %114 = trunc i32 %extelt.offset3 to i16, !dbg !26
+  %115 = tail call float asm "cvt.f32.bf16 $0, $1;", "=r,h"(i16 %111) #3, !dbg !27
+  %116 = tail call float asm "cvt.f32.bf16 $0, $1;", "=r,h"(i16 %112) #3, !dbg !27
+  %117 = tail call float asm "cvt.f32.bf16 $0, $1;", "=r,h"(i16 %113) #3, !dbg !27
+  %118 = tail call float asm "cvt.f32.bf16 $0, $1;", "=r,h"(i16 %114) #3, !dbg !27
+  %119 = add i32 %67, %34, !dbg !28
+  %120 = sext i32 %119 to i64, !dbg !29
+  %121 = getelementptr float, ptr addrspace(1) %3, i64 %120, !dbg !29
+  %122 = tail call { i32, i32, i32, i32 } asm sideeffect "mov.u32 $0, 0x0;\0A\09mov.u32 $1, 0x0;\0A\09mov.u32 $2, 0x0;\0A\09mov.u32 $3, 0x0;\0A\09@$5 ld.global.L1::evict_last.v4.b32 { $0, $1, $2, $3 }, [ $4 + 0 ];\0A\09@!$7 mov.u32 $0, $6;\0A\09@!$9 mov.u32 $1, $8;\0A\09@!$11 mov.u32 $2, $10;\0A\09@!$13 mov.u32 $3, $12;", "=r,=r,=r,=r,l,b,r,b,r,b,r,b,r,b"(ptr addrspace(1) %121, i1 true, i32 0, i1 true, i32 0, i1 true, i32 0, i1 true, i32 0, i1 true) #3, !dbg !30
+  %123 = extractvalue { i32, i32, i32, i32 } %122, 0, !dbg !30
+  %124 = extractvalue { i32, i32, i32, i32 } %122, 1, !dbg !30
+  %125 = extractvalue { i32, i32, i32, i32 } %122, 2, !dbg !30
+  %126 = extractvalue { i32, i32, i32, i32 } %122, 3, !dbg !30
+  %127 = getelementptr float, ptr addrspace(1) %4, i64 %120, !dbg !31
+  %128 = tail call { i32, i32, i32, i32 } asm sideeffect "mov.u32 $0, 0x0;\0A\09mov.u32 $1, 0x0;\0A\09mov.u32 $2, 0x0;\0A\09mov.u32 $3, 0x0;\0A\09@$5 ld.global.L1::evict_last.v4.b32 { $0, $1, $2, $3 }, [ $4 + 0 ];\0A\09@!$7 mov.u32 $0, $6;\0A\09@!$9 mov.u32 $1, $8;\0A\09@!$11 mov.u32 $2, $10;\0A\09@!$13 mov.u32 $3, $12;", "=r,=r,=r,=r,l,b,r,b,r,b,r,b,r,b"(ptr addrspace(1) %127, i1 true, i32 0, i1 true, i32 0, i1 true, i32 0, i1 true, i32 0, i1 true) #3, !dbg !32
+  %129 = extractvalue { i32, i32, i32, i32 } %128, 0, !dbg !32
+  %130 = extractvalue { i32, i32, i32, i32 } %128, 1, !dbg !32
+  %131 = extractvalue { i32, i32, i32, i32 } %128, 2, !dbg !32
+  %132 = extractvalue { i32, i32, i32, i32 } %128, 3, !dbg !32
+  %133 = getelementptr i16, ptr addrspace(1) %5, i64 %71, !dbg !33
+  %134 = tail call { i32, i32 } asm sideeffect "mov.u32 $0, 0x0;\0A\09mov.u32 $1, 0x0;\0A\09@$3 ld.global.L1::evict_first.v2.b32 { $0, $1 }, [ $2 + 0 ];\0A\09@!$5 mov.u32 $0, $4;\0A\09@!$7 mov.u32 $1, $6;", "=r,=r,l,b,r,b,r,b"(ptr addrspace(1) %133, i1 true, i32 0, i1 true, i32 0, i1 true) #3, !dbg !34
+  %135 = extractvalue { i32, i32 } %134, 0, !dbg !34
+  %136 = extractvalue { i32, i32 } %134, 1, !dbg !34
+  %137 = trunc i32 %135 to i16, !dbg !34
+  %extelt.offset4 = lshr i32 %135, 16, !dbg !34
+  %138 = trunc i32 %extelt.offset4 to i16, !dbg !34
+  %139 = trunc i32 %136 to i16, !dbg !34
+  %extelt.offset5 = lshr i32 %136, 16, !dbg !34
+  %140 = trunc i32 %extelt.offset5 to i16, !dbg !34
+  tail call void @llvm.nvvm.barrier0(), !dbg !35
+  %141 = insertelement <1 x i16> undef, i16 %137, i64 0, !dbg !35
+  store <1 x i16> %141, ptr addrspace(3) %39, align 2, !dbg !35
+  %142 = insertelement <1 x i16> undef, i16 %138, i64 0, !dbg !35
+  store <1 x i16> %142, ptr addrspace(3) %43, align 2, !dbg !35
+  %143 = insertelement <1 x i16> undef, i16 %139, i64 0, !dbg !35
+  store <1 x i16> %143, ptr addrspace(3) %47, align 2, !dbg !35
+  %144 = insertelement <1 x i16> undef, i16 %140, i64 0, !dbg !35
+  store <1 x i16> %144, ptr addrspace(3) %51, align 2, !dbg !35
+  tail call void @llvm.nvvm.barrier0(), !dbg !35
+  %145 = load i16, ptr addrspace(3) %55, align 8, !dbg !35
+  %146 = load i16, ptr addrspace(3) %61, align 2, !dbg !35
+  %147 = load i16, ptr addrspace(3) %62, align 4, !dbg !35
+  %148 = load i16, ptr addrspace(3) %63, align 2, !dbg !35
+  %149 = tail call float asm "cvt.f32.bf16 $0, $1;", "=r,h"(i16 %145) #3, !dbg !35
+  %150 = tail call float asm "cvt.f32.bf16 $0, $1;", "=r,h"(i16 %146) #3, !dbg !35
+  %151 = tail call float asm "cvt.f32.bf16 $0, $1;", "=r,h"(i16 %147) #3, !dbg !35
+  %152 = tail call float asm "cvt.f32.bf16 $0, $1;", "=r,h"(i16 %148) #3, !dbg !35
+  %153 = getelementptr float, ptr addrspace(1) %6, i64 %120, !dbg !36
+  %154 = tail call { i32, i32, i32, i32 } asm sideeffect "mov.u32 $0, 0x0;\0A\09mov.u32 $1, 0x0;\0A\09mov.u32 $2, 0x0;\0A\09mov.u32 $3, 0x0;\0A\09@$5 ld.global.L1::evict_last.v4.b32 { $0, $1, $2, $3 }, [ $4 + 0 ];\0A\09@!$7 mov.u32 $0, $6;\0A\09@!$9 mov.u32 $1, $8;\0A\09@!$11 mov.u32 $2, $10;\0A\09@!$13 mov.u32 $3, $12;", "=r,=r,=r,=r,l,b,r,b,r,b,r,b,r,b"(ptr addrspace(1) %153, i1 true, i32 0, i1 true, i32 0, i1 true, i32 0, i1 true, i32 0, i1 true) #3, !dbg !37
+  %155 = extractvalue { i32, i32, i32, i32 } %154, 0, !dbg !37
+  %156 = extractvalue { i32, i32, i32, i32 } %154, 1, !dbg !37
+  %157 = extractvalue { i32, i32, i32, i32 } %154, 2, !dbg !37
+  %158 = extractvalue { i32, i32, i32, i32 } %154, 3, !dbg !37
+  %159 = getelementptr float, ptr addrspace(1) %7, i64 %120, !dbg !38
+  %160 = tail call { i32, i32, i32, i32 } asm sideeffect "mov.u32 $0, 0x0;\0A\09mov.u32 $1, 0x0;\0A\09mov.u32 $2, 0x0;\0A\09mov.u32 $3, 0x0;\0A\09@$5 ld.global.L1::evict_last.v4.b32 { $0, $1, $2, $3 }, [ $4 + 0 ];\0A\09@!$7 mov.u32 $0, $6;\0A\09@!$9 mov.u32 $1, $8;\0A\09@!$11 mov.u32 $2, $10;\0A\09@!$13 mov.u32 $3, $12;", "=r,=r,=r,=r,l,b,r,b,r,b,r,b,r,b"(ptr addrspace(1) %159, i1 true, i32 0, i1 true, i32 0, i1 true, i32 0, i1 true, i32 0, i1 true) #3, !dbg !39
+  %161 = extractvalue { i32, i32, i32, i32 } %160, 0, !dbg !39
+  %162 = extractvalue { i32, i32, i32, i32 } %160, 1, !dbg !39
+  %163 = extractvalue { i32, i32, i32, i32 } %160, 2, !dbg !39
+  %164 = extractvalue { i32, i32, i32, i32 } %160, 3, !dbg !39
+  %165 = fadd float %115, %98, !dbg !40
+  %166 = fadd float %116, %99, !dbg !40
+  %167 = fadd float %117, %100, !dbg !40
+  %168 = fadd float %118, %101, !dbg !40
+  tail call void @llvm.nvvm.barrier0(), !dbg !40
+  %169 = insertelement <1 x float> undef, float %165, i64 0, !dbg !40
+  store <1 x float> %169, ptr addrspace(3) %56, align 4, !dbg !40
+  %170 = insertelement <1 x float> undef, float %166, i64 0, !dbg !40
+  store <1 x float> %170, ptr addrspace(3) %57, align 4, !dbg !40
+  %171 = insertelement <1 x float> undef, float %167, i64 0, !dbg !40
+  store <1 x float> %171, ptr addrspace(3) %58, align 4, !dbg !40
+  %172 = insertelement <1 x float> undef, float %168, i64 0, !dbg !40
+  store <1 x float> %172, ptr addrspace(3) %59, align 4, !dbg !40
+  tail call void @llvm.nvvm.barrier0(), !dbg !40
+  %173 = load <4 x float>, ptr addrspace(3) %60, align 16, !dbg !40
+  %174 = insertelement <8 x i32> poison, i32 %155, i64 0, !dbg !37
+  %175 = insertelement <8 x i32> %174, i32 %156, i64 1, !dbg !37
+  %176 = insertelement <8 x i32> %175, i32 %157, i64 2, !dbg !37
+  %177 = insertelement <8 x i32> %176, i32 %158, i64 3, !dbg !37
+  %178 = insertelement <8 x i32> %177, i32 %123, i64 4, !dbg !37
+  %179 = insertelement <8 x i32> %178, i32 %124, i64 5, !dbg !37
+  %180 = insertelement <8 x i32> %179, i32 %125, i64 6, !dbg !37
+  %181 = insertelement <8 x i32> %180, i32 %126, i64 7, !dbg !37
+  %182 = bitcast <8 x i32> %181 to <8 x float>, !dbg !37
+  %183 = insertelement <8 x i32> poison, i32 %161, i64 0, !dbg !39
+  %184 = insertelement <8 x i32> %183, i32 %162, i64 1, !dbg !39
+  %185 = insertelement <8 x i32> %184, i32 %163, i64 2, !dbg !39
+  %186 = insertelement <8 x i32> %185, i32 %164, i64 3, !dbg !39
+  %187 = insertelement <8 x i32> %186, i32 %129, i64 4, !dbg !39
+  %188 = insertelement <8 x i32> %187, i32 %130, i64 5, !dbg !39
+  %189 = insertelement <8 x i32> %188, i32 %131, i64 6, !dbg !39
+  %190 = insertelement <8 x i32> %189, i32 %132, i64 7, !dbg !39
+  %191 = bitcast <8 x i32> %190 to <8 x float>, !dbg !39
+  %192 = shufflevector <4 x float> %106, <4 x float> %173, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>, !dbg !41
+  %193 = fsub <8 x float> %192, %182, !dbg !41
+  %194 = fmul <8 x float> %193, %191, !dbg !42
+  %195 = insertelement <8 x float> poison, float %149, i64 0, !dbg !43
+  %196 = insertelement <8 x float> %195, float %150, i64 1, !dbg !43
+  %197 = insertelement <8 x float> %196, float %151, i64 2, !dbg !43
+  %198 = insertelement <8 x float> %197, float %152, i64 3, !dbg !43
+  %199 = insertelement <8 x float> %198, float %88, i64 4, !dbg !43
+  %200 = insertelement <8 x float> %199, float %89, i64 5, !dbg !43
+  %201 = insertelement <8 x float> %200, float %90, i64 6, !dbg !43
+  %202 = insertelement <8 x float> %201, float %91, i64 7, !dbg !43
+  %203 = fmul <8 x float> %202, %194, !dbg !43
+  %204 = fadd <8 x float> %66, %203, !dbg !44
+  %205 = add nuw nsw i32 %65, 8, !dbg !16
+  %206 = icmp ult i32 %65, 120, !dbg !16
+  br i1 %206, label %64, label %207, !dbg !16
+
+207:                                              ; preds = %64
+  %208 = and i32 %13, 63, !dbg !8
+  %209 = or i32 %27, %208, !dbg !12
+  %shift = shufflevector <8 x float> %204, <8 x float> poison, <8 x i32> <i32 poison, i32 poison, i32 poison, i32 poison, i32 5, i32 poison, i32 poison, i32 poison>, !dbg !45
+  %210 = fadd <8 x float> %204, %shift, !dbg !45
+  %shift28 = shufflevector <8 x float> %204, <8 x float> poison, <8 x i32> <i32 poison, i32 poison, i32 poison, i32 poison, i32 6, i32 poison, i32 poison, i32 poison>, !dbg !45
+  %211 = fadd <8 x float> %shift28, %210, !dbg !45
+  %shift29 = shufflevector <8 x float> %204, <8 x float> poison, <8 x i32> <i32 poison, i32 poison, i32 poison, i32 poison, i32 7, i32 poison, i32 poison, i32 poison>, !dbg !45
+  %212 = fadd <8 x float> %shift29, %211, !dbg !45
+  %213 = extractelement <8 x float> %212, i64 4, !dbg !45
+  %214 = bitcast float %213 to i32, !dbg !51
+  %215 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %214, i32 1, i32 31), !dbg !51
+  %216 = bitcast i32 %215 to float, !dbg !51
+  %217 = fadd float %213, %216, !dbg !45
+  tail call void @llvm.nvvm.barrier0(), !dbg !53
+  %218 = zext nneg i32 %21 to i64, !dbg !53
+  %219 = getelementptr float, ptr addrspace(3) @global_smem, i64 %218, !dbg !53
+  %220 = insertelement <1 x float> undef, float %217, i64 0, !dbg !53
+  store <1 x float> %220, ptr addrspace(3) %219, align 4, !dbg !53
+  tail call void @llvm.nvvm.barrier0(), !dbg !53
+  %221 = zext nneg i32 %208 to i64, !dbg !53
+  %222 = getelementptr float, ptr addrspace(3) @global_smem, i64 %221, !dbg !53
+  %223 = load i32, ptr addrspace(3) %222, align 4, !dbg !53
+  %224 = sext i32 %209 to i64, !dbg !54
+  %225 = getelementptr float, ptr addrspace(1) %8, i64 %224, !dbg !54
+  %226 = and i32 %13, 64, !dbg !55
+  %227 = icmp eq i32 %226, 0, !dbg !55
+  tail call void asm sideeffect "@$2 st.global.b32 [ $1 + 0 ], { $0 };", "r,l,b"(i32 %223, ptr addrspace(1) %225, i1 %227) #3, !dbg !55
+  %shift30 = shufflevector <8 x float> %204, <8 x float> poison, <8 x i32> <i32 1, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>, !dbg !56
+  %228 = fadd <8 x float> %204, %shift30, !dbg !56
+  %shift31 = shufflevector <8 x float> %204, <8 x float> poison, <8 x i32> <i32 2, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>, !dbg !56
+  %229 = fadd <8 x float> %shift31, %228, !dbg !56
+  %shift32 = shufflevector <8 x float> %204, <8 x float> poison, <8 x i32> <i32 3, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>, !dbg !56
+  %230 = fadd <8 x float> %shift32, %229, !dbg !56
+  %231 = extractelement <8 x float> %230, i64 0, !dbg !56
+  %232 = bitcast float %231 to i32, !dbg !59
+  %233 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %232, i32 1, i32 31), !dbg !59
+  %234 = bitcast i32 %233 to float, !dbg !59
+  %235 = fadd float %231, %234, !dbg !56
+  tail call void @llvm.nvvm.barrier0(), !dbg !61
+  %236 = insertelement <1 x float> undef, float %235, i64 0, !dbg !61
+  store <1 x float> %236, ptr addrspace(3) %219, align 4, !dbg !61
+  tail call void @llvm.nvvm.barrier0(), !dbg !61
+  %237 = load i32, ptr addrspace(3) %222, align 4, !dbg !61
+  %238 = getelementptr float, ptr addrspace(1) %9, i64 %224, !dbg !62
+  tail call void asm sideeffect "@$2 st.global.b32 [ $1 + 0 ], { $0 };", "r,l,b"(i32 %237, ptr addrspace(1) %238, i1 %227) #3, !dbg !63
+  ret void, !dbg !64
+}
+
+; Function Attrs: mustprogress nocallback nofree nosync nounwind speculatable willreturn memory(none)
+declare noundef i32 @llvm.nvvm.read.ptx.sreg.tid.x() #0
+
+; Function Attrs: convergent nocallback nounwind memory(inaccessiblemem: readwrite)
+declare i32 @llvm.nvvm.shfl.sync.bfly.i32(i32, i32, i32, i32) #1
+
+; Function Attrs: convergent nocallback nounwind
+declare void @llvm.nvvm.barrier0() #2
+
+attributes #0 = { mustprogress nocallback nofree nosync nounwind speculatable willreturn memory(none) }
+attributes #1 = { convergent nocallback nounwind memory(inaccessiblemem: readwrite) }
+attributes #2 = { convergent nocallback nounwind }
+attributes #3 = { nounwind }
+
+!llvm.module.flags = !{!0}
+!llvm.dbg.cu = !{!1}
+!nvvm.annotations = !{!3, !4, !4, !3}
+
+!0 = !{i32 2, !"Debug Info Version", i32 3}
+!1 = distinct !DICompileUnit(language: DW_LANG_C, file: !2, producer: "triton", isOptimized: true, runtimeVersion: 0, emissionKind: FullDebug)
+!2 = !DIFile(filename: "c3xxszvgtfnjb7welqvr33z4cqouxhqjy3dpwa2qmmx2xto6sgvz.py", directory: "/tmp/torchinductor_root/3x")
+!3 = !{ptr @triton__0d1d2d3d4d5d6d7d8d9d10de11de, !"kernel", i32 1}
+!4 = !{ptr @triton__0d1d2d3d4d5d6d7d8d9d10de11de, !"maxntidx", i32 128}
+!5 = distinct !DISubprogram(name: "triton__0d1d2d3d4d5d6d7d8d9d10de11de", linkageName: "triton__0d1d2d3d4d5d6d7d8d9d10de11de", scope: !2, file: !2, line: 18, type: !6, scopeLine: 18, spFlags: DISPFlagDefinition | DISPFlagOptimized, unit: !1)
+!6 = !DISubroutineType(cc: DW_CC_normal, types: !7)
+!7 = !{}
+!8 = !DILocation(line: 22, column: 44, scope: !5)
+!9 = !DILocation(line: 24, column: 33, scope: !5)
+!10 = !DILocation(line: 21, column: 28, scope: !5)
+!11 = !DILocation(line: 21, column: 33, scope: !5)
+!12 = !DILocation(line: 22, column: 23, scope: !5)
+!13 = !DILocation(line: 26, column: 20, scope: !5)
+!14 = !DILocation(line: 34, column: 57, scope: !5)
+!15 = !DILocation(line: 37, column: 44, scope: !5)
+!16 = !DILocation(line: 30, column: 36, scope: !5)
+!17 = !DILocation(line: 31, column: 27, scope: !5)
+!18 = !DILocation(line: 34, column: 44, scope: !5)
+!19 = !DILocation(line: 34, column: 51, scope: !5)
+!20 = !DILocation(line: 34, column: 34, scope: !5)
+!21 = !DILocation(line: 34, column: 63, scope: !5)
+!22 = !DILocation(line: 34, column: 115, scope: !5)
+!23 = !DILocation(line: 35, column: 34, scope: !5)
+!24 = !DILocation(line: 35, column: 63, scope: !5)
+!25 = !DILocation(line: 36, column: 34, scope: !5)
+!26 = !DILocation(line: 36, column: 63, scope: !5)
+!27 = !DILocation(line: 36, column: 115, scope: !5)
+!28 = !DILocation(line: 37, column: 40, scope: !5)
+!29 = !DILocation(line: 37, column: 34, scope: !5)
+!30 = !DILocation(line: 37, column: 50, scope: !5)
+!31 = !DILocation(line: 38, column: 34, scope: !5)
+!32 = !DILocation(line: 38, column: 50, scope: !5)
+!33 = !DILocation(line: 39, column: 35, scope: !5)
+!34 = !DILocation(line: 39, column: 64, scope: !5)
+!35 = !DILocation(line: 39, column: 116, scope: !5)
+!36 = !DILocation(line: 40, column: 35, scope: !5)
+!37 = !DILocation(line: 40, column: 51, scope: !5)
+!38 = !DILocation(line: 41, column: 35, scope: !5)
+!39 = !DILocation(line: 41, column: 51, scope: !5)
+!40 = !DILocation(line: 44, column: 22, scope: !5)
+!41 = !DILocation(line: 52, column: 23, scope: !5)
+!42 = !DILocation(line: 53, column: 24, scope: !5)
+!43 = !DILocation(line: 54, column: 24, scope: !5)
+!44 = !DILocation(line: 57, column: 40, scope: !5)
+!45 = !DILocation(line: 233, column: 15, scope: !46, inlinedAt: !49)
+!46 = distinct !DILexicalBlockFile(scope: !48, file: !47, discriminator: 0)
+!47 = !DIFile(filename: "standard.py", directory: "/usr/local/lib/python3.10/dist-packages/triton/language")
+!48 = distinct !DILexicalBlockFile(scope: !5, file: !47, discriminator: 0)
+!49 = !DILocation(line: 243, column: 36, scope: !46, inlinedAt: !50)
+!50 = !DILocation(line: 58, column: 27, scope: !46)
+!51 = !DILocation(line: 243, column: 36, scope: !48, inlinedAt: !52)
+!52 = !DILocation(line: 58, column: 27, scope: !48)
+!53 = !DILocation(line: 58, column: 30, scope: !5)
+!54 = !DILocation(line: 59, column: 25, scope: !5)
+!55 = !DILocation(line: 59, column: 37, scope: !5)
+!56 = !DILocation(line: 233, column: 15, scope: !46, inlinedAt: !57)
+!57 = !DILocation(line: 243, column: 36, scope: !46, inlinedAt: !58)
+!58 = !DILocation(line: 60, column: 27, scope: !46)
+!59 = !DILocation(line: 243, column: 36, scope: !48, inlinedAt: !60)
+!60 = !DILocation(line: 60, column: 27, scope: !48)
+!61 = !DILocation(line: 60, column: 30, scope: !5)
+!62 = !DILocation(line: 61, column: 25, scope: !5)
+!63 = !DILocation(line: 61, column: 37, scope: !5)
+!64 = !DILocation(line: 61, column: 4, scope: !5)

.triton/dump/99e09ac62cbb6a1b0eda5bd8218743c3/triton_.ttgir

@@ -0,0 +1,127 @@
+#blocked = #triton_gpu.blocked<{sizePerThread = [4, 1], threadsPerWarp = [16, 2], warpsPerCTA = [1, 4], order = [0, 1], CTAsPerCGA = [1, 1], CTASplitNum = [1, 1], CTAOrder = [1, 0]}>
+#blocked1 = #triton_gpu.blocked<{sizePerThread = [1, 4], threadsPerWarp = [16, 2], warpsPerCTA = [4, 1], order = [1, 0], CTAsPerCGA = [1, 1], CTASplitNum = [1, 1], CTAOrder = [1, 0]}>
+#blocked2 = #triton_gpu.blocked<{sizePerThread = [1, 1], threadsPerWarp = [32, 1], warpsPerCTA = [2, 2], order = [0, 1], CTAsPerCGA = [1, 1], CTASplitNum = [1, 1], CTAOrder = [1, 0]}>
+module attributes {"triton_gpu.compute-capability" = 89 : i32, "triton_gpu.num-ctas" = 1 : i32, "triton_gpu.num-warps" = 4 : i32, "triton_gpu.threads-per-warp" = 32 : i32} {
+  tt.func public @triton__0d1d2d3d4d5d6d7d8d9d10de11de(%arg0: !tt.ptr<bf16, 1> {tt.divisibility = 16 : i32}, %arg1: !tt.ptr<f32, 1> {tt.divisibility = 16 : i32}, %arg2: !tt.ptr<bf16, 1> {tt.divisibility = 16 : i32}, %arg3: !tt.ptr<f32, 1> {tt.divisibility = 16 : i32}, %arg4: !tt.ptr<f32, 1> {tt.divisibility = 16 : i32}, %arg5: !tt.ptr<bf16, 1> {tt.divisibility = 16 : i32}, %arg6: !tt.ptr<f32, 1> {tt.divisibility = 16 : i32}, %arg7: !tt.ptr<f32, 1> {tt.divisibility = 16 : i32}, %arg8: !tt.ptr<f32, 1> {tt.divisibility = 16 : i32}, %arg9: !tt.ptr<f32, 1> {tt.divisibility = 16 : i32}, %arg10: i32 {tt.divisibility = 16 : i32, tt.max_divisibility = 16 : i32}, %arg11: i32 {tt.divisibility = 16 : i32, tt.max_divisibility = 16 : i32}) attributes {noinline = false} {
+    %cst = arith.constant dense<256> : tensor<64x1xi32, #blocked>
+    %cst_0 = arith.constant dense<256> : tensor<64x1xi32, #blocked1>
+    %cst_1 = arith.constant dense<128> : tensor<64x1xi32, #blocked1>
+    %cst_2 = arith.constant dense<32768> : tensor<64x1xi32, #blocked>
+    %cst_3 = arith.constant dense<256> : tensor<1x8xi32, #blocked>
+    %cst_4 = arith.constant dense<128> : tensor<1x8xi32, #blocked1>
+    %cst_5 = arith.constant dense<128> : tensor<1x8xi32, #blocked>
+    %c0_i32 = arith.constant 0 : i32
+    %c128_i32 = arith.constant 128 : i32
+    %c8_i32 = arith.constant 8 : i32
+    %cst_6 = arith.constant dense<0.000000e+00> : tensor<64x8xf32, #blocked1>
+    %cst_7 = arith.constant dense<0.000000e+00> : tensor<64x8xf32, #blocked>
+    %cst_8 = arith.constant dense<0.000000e+00> : tensor<64x8xbf16, #blocked>
+    %c64_i32 = arith.constant 64 : i32
+    %0 = tt.get_program_id x : i32
+    %1 = arith.muli %0, %c64_i32 : i32
+    %2 = tt.make_range {end = 64 : i32, start = 0 : i32} : tensor<64xi32, #triton_gpu.slice<{dim = 1, parent = #blocked}>>
+    %3 = tt.make_range {end = 64 : i32, start = 0 : i32} : tensor<64xi32, #triton_gpu.slice<{dim = 1, parent = #blocked1}>>
+    %4 = tt.make_range {end = 64 : i32, start = 0 : i32} : tensor<64xi32, #triton_gpu.slice<{dim = 1, parent = #blocked2}>>
+    %5 = tt.expand_dims %2 {axis = 1 : i32} : (tensor<64xi32, #triton_gpu.slice<{dim = 1, parent = #blocked}>>) -> tensor<64x1xi32, #blocked>
+    %6 = tt.expand_dims %3 {axis = 1 : i32} : (tensor<64xi32, #triton_gpu.slice<{dim = 1, parent = #blocked1}>>) -> tensor<64x1xi32, #blocked1>
+    %7 = tt.expand_dims %4 {axis = 1 : i32} : (tensor<64xi32, #triton_gpu.slice<{dim = 1, parent = #blocked2}>>) -> tensor<64x1xi32, #blocked2>
+    %8 = tt.splat %1 : (i32) -> tensor<64x1xi32, #blocked>
+    %9 = tt.splat %1 : (i32) -> tensor<64x1xi32, #blocked1>
+    %10 = tt.splat %1 : (i32) -> tensor<64x1xi32, #blocked2>
+    %11 = arith.addi %8, %5 : tensor<64x1xi32, #blocked>
+    %12 = arith.addi %9, %6 : tensor<64x1xi32, #blocked1>
+    %13 = arith.addi %10, %7 : tensor<64x1xi32, #blocked2>
+    %14 = tt.make_range {end = 8 : i32, start = 0 : i32} : tensor<8xi32, #triton_gpu.slice<{dim = 0, parent = #blocked1}>>
+    %15 = tt.make_range {end = 8 : i32, start = 0 : i32} : tensor<8xi32, #triton_gpu.slice<{dim = 0, parent = #blocked}>>
+    %16 = tt.expand_dims %14 {axis = 0 : i32} : (tensor<8xi32, #triton_gpu.slice<{dim = 0, parent = #blocked1}>>) -> tensor<1x8xi32, #blocked1>
+    %17 = tt.expand_dims %15 {axis = 0 : i32} : (tensor<8xi32, #triton_gpu.slice<{dim = 0, parent = #blocked}>>) -> tensor<1x8xi32, #blocked>
+    %18 = arith.remsi %11, %cst : tensor<64x1xi32, #blocked>
+    %19 = arith.divsi %11, %cst : tensor<64x1xi32, #blocked>
+    %20 = arith.divsi %12, %cst_0 : tensor<64x1xi32, #blocked1>
+    %21 = tt.broadcast %18 : (tensor<64x1xi32, #blocked>) -> tensor<64x8xi32, #blocked>
+    %22 = arith.muli %19, %cst_2 : tensor<64x1xi32, #blocked>
+    %23 = tt.broadcast %22 : (tensor<64x1xi32, #blocked>) -> tensor<64x8xi32, #blocked>
+    %24 = tt.splat %arg0 : (!tt.ptr<bf16, 1>) -> tensor<64x8x!tt.ptr<bf16, 1>, #blocked>
+    %25 = tt.splat %arg1 : (!tt.ptr<f32, 1>) -> tensor<64x8x!tt.ptr<f32, 1>, #blocked>
+    %26 = tt.splat %arg2 : (!tt.ptr<bf16, 1>) -> tensor<64x8x!tt.ptr<bf16, 1>, #blocked>
+    %27 = arith.muli %20, %cst_1 : tensor<64x1xi32, #blocked1>
+    %28 = tt.broadcast %27 : (tensor<64x1xi32, #blocked1>) -> tensor<64x8xi32, #blocked1>
+    %29 = tt.splat %arg3 : (!tt.ptr<f32, 1>) -> tensor<64x8x!tt.ptr<f32, 1>, #blocked1>
+    %30 = tt.splat %arg4 : (!tt.ptr<f32, 1>) -> tensor<64x8x!tt.ptr<f32, 1>, #blocked1>
+    %31 = tt.splat %arg5 : (!tt.ptr<bf16, 1>) -> tensor<64x8x!tt.ptr<bf16, 1>, #blocked>
+    %32 = tt.splat %arg6 : (!tt.ptr<f32, 1>) -> tensor<64x8x!tt.ptr<f32, 1>, #blocked1>
+    %33 = tt.splat %arg7 : (!tt.ptr<f32, 1>) -> tensor<64x8x!tt.ptr<f32, 1>, #blocked1>
+    %34:2 = scf.for %arg12 = %c0_i32 to %c128_i32 step %c8_i32 iter_args(%arg13 = %cst_6, %arg14 = %cst_6) -> (tensor<64x8xf32, #blocked1>, tensor<64x8xf32, #blocked1>)  : i32 {
+      %45 = tt.splat %arg12 : (i32) -> tensor<1x8xi32, #blocked1>
+      %46 = tt.splat %arg12 : (i32) -> tensor<1x8xi32, #blocked>
+      %47 = arith.addi %45, %16 : tensor<1x8xi32, #blocked1>
+      %48 = arith.addi %46, %17 : tensor<1x8xi32, #blocked>
+      %49 = arith.cmpi slt, %47, %cst_4 : tensor<1x8xi32, #blocked1>
+      %50 = arith.cmpi slt, %48, %cst_5 : tensor<1x8xi32, #blocked>
+      %51 = arith.muli %48, %cst_3 : tensor<1x8xi32, #blocked>
+      %52 = tt.broadcast %51 : (tensor<1x8xi32, #blocked>) -> tensor<64x8xi32, #blocked>
+      %53 = arith.addi %21, %52 : tensor<64x8xi32, #blocked>
+      %54 = arith.addi %53, %23 : tensor<64x8xi32, #blocked>
+      %55 = tt.addptr %24, %54 : tensor<64x8x!tt.ptr<bf16, 1>, #blocked>, tensor<64x8xi32, #blocked>
+      %56 = tt.broadcast %49 : (tensor<1x8xi1, #blocked1>) -> tensor<64x8xi1, #blocked1>
+      %57 = tt.broadcast %50 : (tensor<1x8xi1, #blocked>) -> tensor<64x8xi1, #blocked>
+      %58 = tt.load %55, %57, %cst_8 {cache = 1 : i32, evict = 2 : i32, isVolatile = false} : tensor<64x8xbf16, #blocked>
+      %59 = triton_gpu.convert_layout %58 : (tensor<64x8xbf16, #blocked>) -> tensor<64x8xbf16, #blocked1>
+      %60 = arith.extf %59 : tensor<64x8xbf16, #blocked1> to tensor<64x8xf32, #blocked1>
+      %61 = tt.addptr %25, %54 : tensor<64x8x!tt.ptr<f32, 1>, #blocked>, tensor<64x8xi32, #blocked>
+      %62 = tt.load %61, %57, %cst_7 {cache = 1 : i32, evict = 2 : i32, isVolatile = false} : tensor<64x8xf32, #blocked>
+      %63 = triton_gpu.convert_layout %62 : (tensor<64x8xf32, #blocked>) -> tensor<64x8xf32, #blocked1>
+      %64 = tt.addptr %26, %54 : tensor<64x8x!tt.ptr<bf16, 1>, #blocked>, tensor<64x8xi32, #blocked>
+      %65 = tt.load %64, %57, %cst_8 {cache = 1 : i32, evict = 2 : i32, isVolatile = false} : tensor<64x8xbf16, #blocked>
+      %66 = arith.extf %65 : tensor<64x8xbf16, #blocked> to tensor<64x8xf32, #blocked>
+      %67 = tt.broadcast %47 : (tensor<1x8xi32, #blocked1>) -> tensor<64x8xi32, #blocked1>
+      %68 = arith.addi %67, %28 : tensor<64x8xi32, #blocked1>
+      %69 = tt.addptr %29, %68 : tensor<64x8x!tt.ptr<f32, 1>, #blocked1>, tensor<64x8xi32, #blocked1>
+      %70 = tt.load %69, %56, %cst_6 {cache = 1 : i32, evict = 3 : i32, isVolatile = false} : tensor<64x8xf32, #blocked1>
+      %71 = tt.addptr %30, %68 : tensor<64x8x!tt.ptr<f32, 1>, #blocked1>, tensor<64x8xi32, #blocked1>
+      %72 = tt.load %71, %56, %cst_6 {cache = 1 : i32, evict = 3 : i32, isVolatile = false} : tensor<64x8xf32, #blocked1>
+      %73 = tt.addptr %31, %54 : tensor<64x8x!tt.ptr<bf16, 1>, #blocked>, tensor<64x8xi32, #blocked>
+      %74 = tt.load %73, %57, %cst_8 {cache = 1 : i32, evict = 2 : i32, isVolatile = false} : tensor<64x8xbf16, #blocked>
+      %75 = triton_gpu.convert_layout %74 : (tensor<64x8xbf16, #blocked>) -> tensor<64x8xbf16, #blocked1>
+      %76 = arith.extf %75 : tensor<64x8xbf16, #blocked1> to tensor<64x8xf32, #blocked1>
+      %77 = tt.addptr %32, %68 : tensor<64x8x!tt.ptr<f32, 1>, #blocked1>, tensor<64x8xi32, #blocked1>
+      %78 = tt.load %77, %56, %cst_6 {cache = 1 : i32, evict = 3 : i32, isVolatile = false} : tensor<64x8xf32, #blocked1>
+      %79 = tt.addptr %33, %68 : tensor<64x8x!tt.ptr<f32, 1>, #blocked1>, tensor<64x8xi32, #blocked1>
+      %80 = tt.load %79, %56, %cst_6 {cache = 1 : i32, evict = 3 : i32, isVolatile = false} : tensor<64x8xf32, #blocked1>
+      %81 = arith.addf %62, %66 : tensor<64x8xf32, #blocked>
+      %82 = triton_gpu.convert_layout %81 : (tensor<64x8xf32, #blocked>) -> tensor<64x8xf32, #blocked1>
+      %83 = arith.subf %82, %70 : tensor<64x8xf32, #blocked1>
+      %84 = arith.mulf %83, %72 : tensor<64x8xf32, #blocked1>
+      %85 = arith.mulf %60, %84 : tensor<64x8xf32, #blocked1>
+      %86 = arith.addf %arg13, %85 : tensor<64x8xf32, #blocked1>
+      %87 = arith.select %56, %86, %arg13 : tensor<64x8xi1, #blocked1>, tensor<64x8xf32, #blocked1>
+      %88 = arith.subf %63, %78 : tensor<64x8xf32, #blocked1>
+      %89 = arith.mulf %88, %80 : tensor<64x8xf32, #blocked1>
+      %90 = arith.mulf %76, %89 : tensor<64x8xf32, #blocked1>
+      %91 = arith.addf %arg14, %90 : tensor<64x8xf32, #blocked1>
+      %92 = arith.select %56, %91, %arg14 : tensor<64x8xi1, #blocked1>, tensor<64x8xf32, #blocked1>
+      scf.yield %87, %92 : tensor<64x8xf32, #blocked1>, tensor<64x8xf32, #blocked1>
+    }
+    %35 = "tt.reduce"(%34#0) <{axis = 1 : i32}> ({
+    ^bb0(%arg12: f32, %arg13: f32):
+      %45 = arith.addf %arg12, %arg13 : f32
+      tt.reduce.return %45 : f32
+    }) : (tensor<64x8xf32, #blocked1>) -> tensor<64xf32, #triton_gpu.slice<{dim = 1, parent = #blocked1}>>
+    %36 = triton_gpu.convert_layout %35 : (tensor<64xf32, #triton_gpu.slice<{dim = 1, parent = #blocked1}>>) -> tensor<64xf32, #triton_gpu.slice<{dim = 1, parent = #blocked2}>>
+    %37 = tt.expand_dims %36 {axis = 1 : i32} : (tensor<64xf32, #triton_gpu.slice<{dim = 1, parent = #blocked2}>>) -> tensor<64x1xf32, #blocked2>
+    %38 = tt.splat %arg8 : (!tt.ptr<f32, 1>) -> tensor<64x1x!tt.ptr<f32, 1>, #blocked2>
+    %39 = tt.addptr %38, %13 : tensor<64x1x!tt.ptr<f32, 1>, #blocked2>, tensor<64x1xi32, #blocked2>
+    tt.store %39, %37 {cache = 1 : i32, evict = 1 : i32} : tensor<64x1xf32, #blocked2>
+    %40 = "tt.reduce"(%34#1) <{axis = 1 : i32}> ({
+    ^bb0(%arg12: f32, %arg13: f32):
+      %45 = arith.addf %arg12, %arg13 : f32
+      tt.reduce.return %45 : f32
+    }) : (tensor<64x8xf32, #blocked1>) -> tensor<64xf32, #triton_gpu.slice<{dim = 1, parent = #blocked1}>>
+    %41 = triton_gpu.convert_layout %40 : (tensor<64xf32, #triton_gpu.slice<{dim = 1, parent = #blocked1}>>) -> tensor<64xf32, #triton_gpu.slice<{dim = 1, parent = #blocked2}>>
+    %42 = tt.expand_dims %41 {axis = 1 : i32} : (tensor<64xf32, #triton_gpu.slice<{dim = 1, parent = #blocked2}>>) -> tensor<64x1xf32, #blocked2>
+    %43 = tt.splat %arg9 : (!tt.ptr<f32, 1>) -> tensor<64x1x!tt.ptr<f32, 1>, #blocked2>
+    %44 = tt.addptr %43, %13 : tensor<64x1x!tt.ptr<f32, 1>, #blocked2>, tensor<64x1xi32, #blocked2>
+    tt.store %44, %42 {cache = 1 : i32, evict = 1 : i32} : tensor<64x1xf32, #blocked2>
+    tt.return
+  }
+}

.triton/dump/99f0a4c15ca0aab38ccdae6c765f7333/triton_.llir

@@ -0,0 +1,333 @@
+; ModuleID = 'LLVMDialectModule'
+source_filename = "LLVMDialectModule"
+
+@global_smem = external addrspace(3) global [0 x i8]
+@.str = private unnamed_addr constant [11 x i8] c"__CUDA_FTZ\00", align 1
+
+define void @triton__0d1d2d3d4d5d6de7de(ptr addrspace(1) %0, ptr addrspace(1) %1, ptr addrspace(1) %2, ptr addrspace(1) %3, ptr addrspace(1) %4, ptr addrspace(1) %5, i32 %6, i32 %7) local_unnamed_addr !dbg !7 {
+  %9 = tail call i32 @llvm.nvvm.read.ptx.sreg.tid.x(), !dbg !10
+  %10 = and i32 %9, 31, !dbg !10
+  %11 = lshr i32 %9, 5, !dbg !10
+  %12 = and i32 %11, 1, !dbg !10
+  %urem = shl i32 %9, 2, !dbg !10
+  %13 = and i32 %urem, 252, !dbg !10
+  %14 = tail call i32 asm "mov.u32 $0, %ctaid.x;", "=r"() #6, !dbg !11
+  %15 = shl i32 %14, 8, !dbg !12
+  %16 = or i32 %15, %13, !dbg !13
+  %17 = sext i32 %16 to i64, !dbg !14
+  %18 = getelementptr float, ptr addrspace(1) %0, i64 %17, !dbg !14
+  %19 = tail call { i32, i32, i32, i32 } asm sideeffect "mov.u32 $0, 0x0;\0A\09mov.u32 $1, 0x0;\0A\09mov.u32 $2, 0x0;\0A\09mov.u32 $3, 0x0;\0A\09@$5 ld.global.v4.b32 { $0, $1, $2, $3 }, [ $4 + 0 ];\0A\09@!$7 mov.u32 $0, $6;\0A\09@!$9 mov.u32 $1, $8;\0A\09@!$11 mov.u32 $2, $10;\0A\09@!$13 mov.u32 $3, $12;", "=r,=r,=r,=r,l,b,r,b,r,b,r,b,r,b"(ptr addrspace(1) %18, i1 true, i32 0, i1 true, i32 0, i1 true, i32 0, i1 true, i32 0, i1 true) #6, !dbg !15
+  %20 = extractvalue { i32, i32, i32, i32 } %19, 0, !dbg !15
+  %21 = extractvalue { i32, i32, i32, i32 } %19, 1, !dbg !15
+  %22 = extractvalue { i32, i32, i32, i32 } %19, 2, !dbg !15
+  %23 = extractvalue { i32, i32, i32, i32 } %19, 3, !dbg !15
+  %24 = bitcast i32 %22 to float, !dbg !15
+  %25 = bitcast i32 %23 to float, !dbg !15
+  %26 = getelementptr i16, ptr addrspace(1) %1, i64 %17, !dbg !16
+  %27 = tail call { i32, i32 } asm sideeffect "mov.u32 $0, 0x0;\0A\09mov.u32 $1, 0x0;\0A\09@$3 ld.global.v2.b32 { $0, $1 }, [ $2 + 0 ];\0A\09@!$5 mov.u32 $0, $4;\0A\09@!$7 mov.u32 $1, $6;", "=r,=r,l,b,r,b,r,b"(ptr addrspace(1) %26, i1 true, i32 0, i1 true, i32 0, i1 true) #6, !dbg !17
+  %28 = extractvalue { i32, i32 } %27, 0, !dbg !17
+  %29 = extractvalue { i32, i32 } %27, 1, !dbg !17
+  %30 = trunc i32 %28 to i16, !dbg !17
+  %extelt.offset = lshr i32 %28, 16, !dbg !17
+  %31 = trunc i32 %extelt.offset to i16, !dbg !17
+  %32 = trunc i32 %29 to i16, !dbg !17
+  %extelt.offset1 = lshr i32 %29, 16, !dbg !17
+  %33 = trunc i32 %extelt.offset1 to i16, !dbg !17
+  %34 = tail call float asm "cvt.f32.bf16 $0, $1;", "=r,h"(i16 %30) #6, !dbg !18
+  %35 = tail call float asm "cvt.f32.bf16 $0, $1;", "=r,h"(i16 %31) #6, !dbg !18
+  %36 = tail call float asm "cvt.f32.bf16 $0, $1;", "=r,h"(i16 %32) #6, !dbg !18
+  %37 = tail call float asm "cvt.f32.bf16 $0, $1;", "=r,h"(i16 %33) #6, !dbg !18
+  %38 = getelementptr i16, ptr addrspace(1) %2, i64 %17, !dbg !19
+  %39 = tail call { i32, i32 } asm sideeffect "mov.u32 $0, 0x0;\0A\09mov.u32 $1, 0x0;\0A\09@$3 ld.global.v2.b32 { $0, $1 }, [ $2 + 0 ];\0A\09@!$5 mov.u32 $0, $4;\0A\09@!$7 mov.u32 $1, $6;", "=r,=r,l,b,r,b,r,b"(ptr addrspace(1) %38, i1 true, i32 0, i1 true, i32 0, i1 true) #6, !dbg !20
+  %40 = extractvalue { i32, i32 } %39, 0, !dbg !20
+  %41 = extractvalue { i32, i32 } %39, 1, !dbg !20
+  %42 = trunc i32 %40 to i16, !dbg !20
+  %extelt.offset2 = lshr i32 %40, 16, !dbg !20
+  %43 = trunc i32 %extelt.offset2 to i16, !dbg !20
+  %44 = trunc i32 %41 to i16, !dbg !20
+  %extelt.offset3 = lshr i32 %41, 16, !dbg !20
+  %45 = trunc i32 %extelt.offset3 to i16, !dbg !20
+  %46 = tail call float asm "cvt.f32.bf16 $0, $1;", "=r,h"(i16 %42) #6, !dbg !21
+  %47 = tail call float asm "cvt.f32.bf16 $0, $1;", "=r,h"(i16 %43) #6, !dbg !21
+  %48 = tail call float asm "cvt.f32.bf16 $0, $1;", "=r,h"(i16 %44) #6, !dbg !21
+  %49 = tail call float asm "cvt.f32.bf16 $0, $1;", "=r,h"(i16 %45) #6, !dbg !21
+  %50 = getelementptr i16, ptr addrspace(1) %3, i64 %17, !dbg !22
+  %51 = tail call { i32, i32 } asm sideeffect "mov.u32 $0, 0x0;\0A\09mov.u32 $1, 0x0;\0A\09@$3 ld.global.v2.b32 { $0, $1 }, [ $2 + 0 ];\0A\09@!$5 mov.u32 $0, $4;\0A\09@!$7 mov.u32 $1, $6;", "=r,=r,l,b,r,b,r,b"(ptr addrspace(1) %50, i1 true, i32 0, i1 true, i32 0, i1 true) #6, !dbg !23
+  %52 = extractvalue { i32, i32 } %51, 0, !dbg !23
+  %53 = extractvalue { i32, i32 } %51, 1, !dbg !23
+  %54 = trunc i32 %52 to i16, !dbg !23
+  %extelt.offset4 = lshr i32 %52, 16, !dbg !23
+  %55 = trunc i32 %extelt.offset4 to i16, !dbg !23
+  %56 = trunc i32 %53 to i16, !dbg !23
+  %extelt.offset5 = lshr i32 %53, 16, !dbg !23
+  %57 = trunc i32 %extelt.offset5 to i16, !dbg !23
+  %58 = tail call float asm "cvt.f32.bf16 $0, $1;", "=r,h"(i16 %54) #6, !dbg !24
+  %59 = tail call float asm "cvt.f32.bf16 $0, $1;", "=r,h"(i16 %55) #6, !dbg !24
+  %60 = tail call float asm "cvt.f32.bf16 $0, $1;", "=r,h"(i16 %56) #6, !dbg !24
+  %61 = tail call float asm "cvt.f32.bf16 $0, $1;", "=r,h"(i16 %57) #6, !dbg !24
+  %62 = zext nneg i32 %13 to i64, !dbg !25
+  %63 = getelementptr float, ptr addrspace(1) %4, i64 %62, !dbg !25
+  %64 = tail call { i32, i32, i32, i32 } asm sideeffect "mov.u32 $0, 0x0;\0A\09mov.u32 $1, 0x0;\0A\09mov.u32 $2, 0x0;\0A\09mov.u32 $3, 0x0;\0A\09@$5 ld.global.L1::evict_last.v4.b32 { $0, $1, $2, $3 }, [ $4 + 0 ];\0A\09@!$7 mov.u32 $0, $6;\0A\09@!$9 mov.u32 $1, $8;\0A\09@!$11 mov.u32 $2, $10;\0A\09@!$13 mov.u32 $3, $12;", "=r,=r,=r,=r,l,b,r,b,r,b,r,b,r,b"(ptr addrspace(1) %63, i1 true, i32 0, i1 true, i32 0, i1 true, i32 0, i1 true, i32 0, i1 true) #6, !dbg !26
+  %65 = fadd float %36, %24, !dbg !27
+  %66 = fadd float %37, %25, !dbg !27
+  %67 = fadd float %65, %48, !dbg !28
+  %68 = fadd float %66, %49, !dbg !28
+  %69 = insertelement <2 x i32> poison, i32 %20, i64 0, !dbg !15
+  %70 = insertelement <2 x i32> %69, i32 %21, i64 1, !dbg !15
+  %71 = bitcast <2 x i32> %70 to <2 x float>, !dbg !15
+  %72 = insertelement <2 x float> poison, float %34, i64 0, !dbg !27
+  %73 = insertelement <2 x float> %72, float %35, i64 1, !dbg !27
+  %74 = fadd <2 x float> %73, %71, !dbg !27
+  %75 = insertelement <2 x float> poison, float %46, i64 0, !dbg !28
+  %76 = insertelement <2 x float> %75, float %47, i64 1, !dbg !28
+  %77 = fadd <2 x float> %74, %76, !dbg !28
+  %78 = insertelement <2 x float> poison, float %58, i64 0, !dbg !29
+  %79 = insertelement <2 x float> %78, float %59, i64 1, !dbg !29
+  %80 = fadd <2 x float> %77, %79, !dbg !29
+  %81 = fadd float %67, %60, !dbg !29
+  %82 = fadd float %68, %61, !dbg !29
+  %83 = extractelement <2 x float> %80, i64 0, !dbg !30
+  %84 = extractelement <2 x float> %80, i64 1, !dbg !30
+  %85 = fadd float %83, %84, !dbg !30
+  %86 = fadd float %85, %81, !dbg !30
+  %87 = fadd float %86, %82, !dbg !30
+  %88 = bitcast float %87 to i32, !dbg !36
+  %89 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %88, i32 16, i32 31), !dbg !36
+  %90 = bitcast i32 %89 to float, !dbg !36
+  %91 = fadd float %87, %90, !dbg !30
+  %92 = bitcast float %91 to i32, !dbg !36
+  %93 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %92, i32 8, i32 31), !dbg !36
+  %94 = bitcast i32 %93 to float, !dbg !36
+  %95 = fadd float %91, %94, !dbg !30
+  %96 = bitcast float %95 to i32, !dbg !36
+  %97 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %96, i32 4, i32 31), !dbg !36
+  %98 = bitcast i32 %97 to float, !dbg !36
+  %99 = fadd float %95, %98, !dbg !30
+  %100 = bitcast float %99 to i32, !dbg !36
+  %101 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %100, i32 2, i32 31), !dbg !36
+  %102 = bitcast i32 %101 to float, !dbg !36
+  %103 = fadd float %99, %102, !dbg !30
+  %104 = bitcast float %103 to i32, !dbg !36
+  %105 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %104, i32 1, i32 31), !dbg !36
+  %106 = bitcast i32 %105 to float, !dbg !36
+  %107 = fadd float %103, %106, !dbg !30
+  %108 = icmp eq i32 %10, 0, !dbg !36
+  %109 = zext nneg i32 %12 to i64, !dbg !36
+  %110 = getelementptr float, ptr addrspace(3) @global_smem, i64 %109, !dbg !36
+  tail call void asm sideeffect "@$2 st.shared.b32 [ $0 + 0 ], $1;", "r,r,b"(ptr addrspace(3) %110, float %107, i1 %108) #6, !dbg !36
+  tail call void @llvm.nvvm.barrier0(), !dbg !36
+  %111 = icmp slt i32 %9, 2, !dbg !36
+  %112 = sext i32 %9 to i64, !dbg !36
+  %113 = getelementptr float, ptr addrspace(3) @global_smem, i64 %112, !dbg !36
+  %114 = tail call float asm sideeffect "@$2 ld.shared.b32 $0, [ $1 + 0 ];", "=r,r,b"(ptr addrspace(3) %113, i1 %111) #6, !dbg !36
+  %115 = bitcast float %114 to i32, !dbg !36
+  %116 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %115, i32 1, i32 31), !dbg !36
+  %117 = bitcast i32 %116 to float, !dbg !36
+  %118 = fadd float %114, %117, !dbg !30
+  %119 = and i32 %9, 1, !dbg !36
+  %120 = icmp eq i32 %119, 0, !dbg !36
+  %121 = and i1 %111, %120, !dbg !36
+  tail call void asm sideeffect "@$2 st.shared.b32 [ $0 + 0 ], $1;", "r,r,b"(ptr addrspace(3) %113, float %118, i1 %121) #6, !dbg !36
+  tail call void @llvm.nvvm.barrier0(), !dbg !36
+  %122 = load float, ptr addrspace(3) @global_smem, align 4, !dbg !36
+  %123 = fadd float %122, 0.000000e+00, !dbg !38
+  %124 = tail call float asm "div.full.f32 $0, $1, $2;", "=r,r,r"(float %123, float 2.560000e+02) #6, !dbg !42
+  %125 = fsub float %83, %124, !dbg !43
+  %126 = fsub float %84, %124, !dbg !43
+  %127 = fsub float %81, %124, !dbg !43
+  %128 = fsub float %82, %124, !dbg !43
+  %129 = fmul float %125, %125, !dbg !44
+  %130 = fmul float %126, %126, !dbg !44
+  %131 = fmul float %127, %127, !dbg !44
+  %132 = fmul float %128, %128, !dbg !44
+  tail call void @llvm.nvvm.barrier0(), !dbg !45
+  %133 = fadd float %129, %130, !dbg !47
+  %134 = fadd float %131, %133, !dbg !47
+  %135 = fadd float %132, %134, !dbg !47
+  %136 = bitcast float %135 to i32, !dbg !45
+  %137 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %136, i32 16, i32 31), !dbg !45
+  %138 = bitcast i32 %137 to float, !dbg !45
+  %139 = fadd float %135, %138, !dbg !47
+  %140 = bitcast float %139 to i32, !dbg !45
+  %141 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %140, i32 8, i32 31), !dbg !45
+  %142 = bitcast i32 %141 to float, !dbg !45
+  %143 = fadd float %139, %142, !dbg !47
+  %144 = bitcast float %143 to i32, !dbg !45
+  %145 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %144, i32 4, i32 31), !dbg !45
+  %146 = bitcast i32 %145 to float, !dbg !45
+  %147 = fadd float %143, %146, !dbg !47
+  %148 = bitcast float %147 to i32, !dbg !45
+  %149 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %148, i32 2, i32 31), !dbg !45
+  %150 = bitcast i32 %149 to float, !dbg !45
+  %151 = fadd float %147, %150, !dbg !47
+  %152 = bitcast float %151 to i32, !dbg !45
+  %153 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %152, i32 1, i32 31), !dbg !45
+  %154 = bitcast i32 %153 to float, !dbg !45
+  %155 = fadd float %151, %154, !dbg !47
+  tail call void asm sideeffect "@$2 st.shared.b32 [ $0 + 0 ], $1;", "r,r,b"(ptr addrspace(3) %110, float %155, i1 %108) #6, !dbg !45
+  tail call void @llvm.nvvm.barrier0(), !dbg !45
+  %156 = tail call float asm sideeffect "@$2 ld.shared.b32 $0, [ $1 + 0 ];", "=r,r,b"(ptr addrspace(3) %113, i1 %111) #6, !dbg !45
+  %157 = bitcast float %156 to i32, !dbg !45
+  %158 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %157, i32 1, i32 31), !dbg !45
+  %159 = bitcast i32 %158 to float, !dbg !45
+  %160 = fadd float %156, %159, !dbg !47
+  tail call void asm sideeffect "@$2 st.shared.b32 [ $0 + 0 ], $1;", "r,r,b"(ptr addrspace(3) %113, float %160, i1 %121) #6, !dbg !45
+  tail call void @llvm.nvvm.barrier0(), !dbg !45
+  %161 = load float, ptr addrspace(3) @global_smem, align 4, !dbg !45
+  %162 = fadd float %161, 0.000000e+00, !dbg !50
+  %163 = tail call float asm "div.full.f32 $0, $1, $2;", "=r,r,r"(float %162, float 2.560000e+02) #6, !dbg !52
+  %164 = fadd float %163, 0x3EE4F8B580000000, !dbg !53
+  %165 = tail call i32 @__nvvm_reflect(ptr nonnull @.str) #6, !dbg !54
+  %.not.i = icmp eq i32 %165, 0, !dbg !54
+  br i1 %.not.i, label %168, label %166, !dbg !54
+
+166:                                              ; preds = %8
+  %167 = tail call float @llvm.nvvm.rsqrt.approx.ftz.f(float %164), !dbg !54
+  br label %__nv_rsqrtf.exit, !dbg !54
+
+168:                                              ; preds = %8
+  %169 = tail call float @llvm.nvvm.rsqrt.approx.f(float %164), !dbg !54
+  br label %__nv_rsqrtf.exit, !dbg !54
+
+__nv_rsqrtf.exit:                                 ; preds = %166, %168
+  %.0.i = phi float [ %167, %166 ], [ %169, %168 ], !dbg !54
+  %170 = extractvalue { i32, i32, i32, i32 } %64, 3, !dbg !26
+  %171 = bitcast i32 %170 to float, !dbg !26
+  %172 = extractvalue { i32, i32, i32, i32 } %64, 2, !dbg !26
+  %173 = bitcast i32 %172 to float, !dbg !26
+  %174 = extractvalue { i32, i32, i32, i32 } %64, 1, !dbg !26
+  %175 = bitcast i32 %174 to float, !dbg !26
+  %176 = extractvalue { i32, i32, i32, i32 } %64, 0, !dbg !26
+  %177 = bitcast i32 %176 to float, !dbg !26
+  %178 = fmul float %125, %.0.i, !dbg !55
+  %179 = fmul float %126, %.0.i, !dbg !55
+  %180 = fmul float %127, %.0.i, !dbg !55
+  %181 = fmul float %128, %.0.i, !dbg !55
+  %182 = fmul float %178, %177, !dbg !56
+  %183 = fmul float %179, %175, !dbg !56
+  %184 = fmul float %180, %173, !dbg !56
+  %185 = fmul float %181, %171, !dbg !56
+  %186 = getelementptr i16, ptr addrspace(1) %5, i64 %17, !dbg !57
+  %187 = tail call i16 asm "cvt.rn.bf16.f32 $0, $1;", "=h,r"(float %182) #6, !dbg !58
+  %188 = tail call i16 asm "cvt.rn.bf16.f32 $0, $1;", "=h,r"(float %183) #6, !dbg !58
+  %189 = tail call i16 asm "cvt.rn.bf16.f32 $0, $1;", "=h,r"(float %184) #6, !dbg !58
+  %190 = tail call i16 asm "cvt.rn.bf16.f32 $0, $1;", "=h,r"(float %185) #6, !dbg !58
+  %191 = insertelement <2 x i16> undef, i16 %187, i64 0, !dbg !58
+  %192 = insertelement <2 x i16> %191, i16 %188, i64 1, !dbg !58
+  %193 = bitcast <2 x i16> %192 to i32, !dbg !58
+  %194 = insertelement <2 x i16> undef, i16 %189, i64 0, !dbg !58
+  %195 = insertelement <2 x i16> %194, i16 %190, i64 1, !dbg !58
+  %196 = bitcast <2 x i16> %195 to i32, !dbg !58
+  tail call void asm sideeffect "@$3 st.global.v2.b32 [ $2 + 0 ], { $0, $1 };", "r,r,l,b"(i32 %193, i32 %196, ptr addrspace(1) %186, i1 true) #6, !dbg !58
+  ret void, !dbg !59
+}
+
+; Function Attrs: mustprogress nocallback nofree nosync nounwind speculatable willreturn memory(none)
+declare noundef i32 @llvm.nvvm.read.ptx.sreg.tid.x() #0
+
+; Function Attrs: convergent nocallback nounwind memory(inaccessiblemem: readwrite)
+declare i32 @llvm.nvvm.shfl.sync.bfly.i32(i32, i32, i32, i32) #1
+
+; Function Attrs: convergent nocallback nounwind
+declare void @llvm.nvvm.barrier0() #2
+
+; Function Attrs: alwaysinline nounwind
+define float @__nv_rsqrtf(float %x) local_unnamed_addr #3 {
+  %1 = tail call i32 @__nvvm_reflect(ptr nonnull @.str) #6
+  %.not = icmp eq i32 %1, 0
+  br i1 %.not, label %4, label %2
+
+2:                                                ; preds = %0
+  %3 = tail call float @llvm.nvvm.rsqrt.approx.ftz.f(float %x)
+  br label %6
+
+4:                                                ; preds = %0
+  %5 = tail call float @llvm.nvvm.rsqrt.approx.f(float %x)
+  br label %6
+
+6:                                                ; preds = %4, %2
+  %.0 = phi float [ %3, %2 ], [ %5, %4 ]
+  ret float %.0
+}
+
+declare i32 @__nvvm_reflect(ptr) local_unnamed_addr #4
+
+; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(none)
+declare float @llvm.nvvm.rsqrt.approx.ftz.f(float) #5
+
+; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(none)
+declare float @llvm.nvvm.rsqrt.approx.f(float) #5
+
+attributes #0 = { mustprogress nocallback nofree nosync nounwind speculatable willreturn memory(none) }
+attributes #1 = { convergent nocallback nounwind memory(inaccessiblemem: readwrite) }
+attributes #2 = { convergent nocallback nounwind }
+attributes #3 = { alwaysinline nounwind "disable-tail-calls"="false" "frame-pointer"="all" "less-precise-fpmad"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #4 = { "disable-tail-calls"="false" "frame-pointer"="all" "less-precise-fpmad"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #5 = { mustprogress nocallback nofree nosync nounwind willreturn memory(none) }
+attributes #6 = { nounwind }
+
+!llvm.module.flags = !{!0, !1}
+!llvm.dbg.cu = !{!2}
+!nvvm.annotations = !{!4, !5, !5, !4}
+!llvm.ident = !{!6}
+
+!0 = !{i32 2, !"Debug Info Version", i32 3}
+!1 = !{i32 4, !"nvvm-reflect-ftz", i32 1}
+!2 = distinct !DICompileUnit(language: DW_LANG_C, file: !3, producer: "triton", isOptimized: true, runtimeVersion: 0, emissionKind: FullDebug)
+!3 = !DIFile(filename: "c4qmi2qsgi5mnuig7w3wx5jmjnmvktjlgcv4c6q7w2vaw3bk6qzb.py", directory: "/tmp/torchinductor_root/4q")
+!4 = !{ptr @triton__0d1d2d3d4d5d6de7de, !"kernel", i32 1}
+!5 = !{ptr @triton__0d1d2d3d4d5d6de7de, !"maxntidx", i32 64}
+!6 = !{!"clang version 3.8.0 (tags/RELEASE_380/final)"}
+!7 = distinct !DISubprogram(name: "triton__0d1d2d3d4d5d6de7de", linkageName: "triton__0d1d2d3d4d5d6de7de", scope: !3, file: !3, line: 18, type: !8, scopeLine: 18, spFlags: DISPFlagDefinition | DISPFlagOptimized, unit: !2)
+!8 = !DISubroutineType(cc: DW_CC_normal, types: !9)
+!9 = !{}
+!10 = !DILocation(line: 26, column: 26, scope: !7)
+!11 = !DILocation(line: 23, column: 28, scope: !7)
+!12 = !DILocation(line: 30, column: 40, scope: !7)
+!13 = !DILocation(line: 30, column: 36, scope: !7)
+!14 = !DILocation(line: 30, column: 30, scope: !7)
+!15 = !DILocation(line: 30, column: 46, scope: !7)
+!16 = !DILocation(line: 31, column: 30, scope: !7)
+!17 = !DILocation(line: 31, column: 46, scope: !7)
+!18 = !DILocation(line: 31, column: 67, scope: !7)
+!19 = !DILocation(line: 32, column: 30, scope: !7)
+!20 = !DILocation(line: 32, column: 46, scope: !7)
+!21 = !DILocation(line: 32, column: 67, scope: !7)
+!22 = !DILocation(line: 33, column: 30, scope: !7)
+!23 = !DILocation(line: 33, column: 46, scope: !7)
+!24 = !DILocation(line: 33, column: 67, scope: !7)
+!25 = !DILocation(line: 34, column: 31, scope: !7)
+!26 = !DILocation(line: 34, column: 36, scope: !7)
+!27 = !DILocation(line: 36, column: 18, scope: !7)
+!28 = !DILocation(line: 38, column: 18, scope: !7)
+!29 = !DILocation(line: 40, column: 18, scope: !7)
+!30 = !DILocation(line: 233, column: 15, scope: !31, inlinedAt: !34)
+!31 = distinct !DILexicalBlockFile(scope: !33, file: !32, discriminator: 0)
+!32 = !DIFile(filename: "standard.py", directory: "/usr/local/lib/python3.10/dist-packages/triton/language")
+!33 = distinct !DILexicalBlockFile(scope: !7, file: !32, discriminator: 0)
+!34 = !DILocation(line: 243, column: 36, scope: !31, inlinedAt: !35)
+!35 = !DILocation(line: 45, column: 59, scope: !31)
+!36 = !DILocation(line: 243, column: 36, scope: !33, inlinedAt: !37)
+!37 = !DILocation(line: 45, column: 59, scope: !33)
+!38 = !DILocation(line: 8, column: 15, scope: !39, inlinedAt: !41)
+!39 = distinct !DILexicalBlockFile(scope: !7, file: !40, discriminator: 0)
+!40 = !DIFile(filename: "triton_helpers.py", directory: "/usr/local/lib/python3.10/dist-packages/torch/_inductor")
+!41 = !DILocation(line: 45, column: 45, scope: !39)
+!42 = !DILocation(line: 48, column: 20, scope: !7)
+!43 = !DILocation(line: 49, column: 20, scope: !7)
+!44 = !DILocation(line: 50, column: 20, scope: !7)
+!45 = !DILocation(line: 243, column: 36, scope: !33, inlinedAt: !46)
+!46 = !DILocation(line: 53, column: 59, scope: !33)
+!47 = !DILocation(line: 233, column: 15, scope: !31, inlinedAt: !48)
+!48 = !DILocation(line: 243, column: 36, scope: !31, inlinedAt: !49)
+!49 = !DILocation(line: 53, column: 59, scope: !31)
+!50 = !DILocation(line: 8, column: 15, scope: !39, inlinedAt: !51)
+!51 = !DILocation(line: 53, column: 45, scope: !39)
+!52 = !DILocation(line: 56, column: 20, scope: !7)
+!53 = !DILocation(line: 58, column: 20, scope: !7)
+!54 = !DILocation(line: 59, column: 26, scope: !7)
+!55 = !DILocation(line: 60, column: 20, scope: !7)
+!56 = !DILocation(line: 61, column: 20, scope: !7)
+!57 = !DILocation(line: 63, column: 25, scope: !7)
+!58 = !DILocation(line: 63, column: 48, scope: !7)
+!59 = !DILocation(line: 63, column: 4, scope: !7)

.triton/dump/9aec2dd769dc1991d76fa64c70ec0e92/triton_.llir

@@ -0,0 +1,230 @@
+; ModuleID = 'LLVMDialectModule'
+source_filename = "LLVMDialectModule"
+
+@global_smem = external addrspace(3) global [0 x i8]
+
+define void @triton__0d1d2d3de4e(ptr addrspace(1) %0, ptr addrspace(1) %1, ptr addrspace(1) %2, i32 %3, i32 %4) local_unnamed_addr !dbg !5 {
+  %6 = tail call i32 @llvm.nvvm.read.ptx.sreg.tid.x(), !dbg !8
+  %7 = and i32 %6, 31, !dbg !8
+  %8 = lshr i32 %6, 5, !dbg !8
+  %9 = shl i32 %6, 2, !dbg !8
+  %10 = and i32 %9, 60, !dbg !8
+  %11 = and i32 %8, 3, !dbg !9
+  %12 = lshr i32 %7, 4, !dbg !9
+  %13 = shl nuw nsw i32 %11, 1, !dbg !9
+  %14 = or i32 %13, %12, !dbg !9
+  %15 = tail call i32 asm "mov.u32 $0, %ctaid.x;", "=r"() #3, !dbg !10
+  %16 = shl i32 %15, 6, !dbg !11
+  %17 = or i32 %16, %10, !dbg !12
+  br label %18, !dbg !13
+
+18:                                               ; preds = %5, %18
+  %19 = phi i32 [ 0, %5 ], [ %37, %18 ]
+  %20 = phi <4 x float> [ zeroinitializer, %5 ], [ %36, %18 ]
+  %21 = or i32 %19, %14, !dbg !14
+  %22 = shl i32 %21, 17, !dbg !15
+  %23 = add i32 %17, %22, !dbg !16
+  %24 = sext i32 %23 to i64, !dbg !17
+  %25 = getelementptr float, ptr addrspace(1) %0, i64 %24, !dbg !17
+  %26 = tail call { i32, i32, i32, i32 } asm sideeffect "mov.u32 $0, 0x0;\0A\09mov.u32 $1, 0x0;\0A\09mov.u32 $2, 0x0;\0A\09mov.u32 $3, 0x0;\0A\09@$5 ld.global.L1::evict_first.v4.b32 { $0, $1, $2, $3 }, [ $4 + 0 ];\0A\09@!$7 mov.u32 $0, $6;\0A\09@!$9 mov.u32 $1, $8;\0A\09@!$11 mov.u32 $2, $10;\0A\09@!$13 mov.u32 $3, $12;", "=r,=r,=r,=r,l,b,r,b,r,b,r,b,r,b"(ptr addrspace(1) %25, i1 true, i32 0, i1 true, i32 0, i1 true, i32 0, i1 true, i32 0, i1 true) #3, !dbg !18
+  %27 = extractvalue { i32, i32, i32, i32 } %26, 0, !dbg !18
+  %28 = extractvalue { i32, i32, i32, i32 } %26, 1, !dbg !18
+  %29 = extractvalue { i32, i32, i32, i32 } %26, 2, !dbg !18
+  %30 = extractvalue { i32, i32, i32, i32 } %26, 3, !dbg !18
+  %31 = insertelement <4 x i32> poison, i32 %27, i64 0, !dbg !18
+  %32 = insertelement <4 x i32> %31, i32 %28, i64 1, !dbg !18
+  %33 = insertelement <4 x i32> %32, i32 %29, i64 2, !dbg !18
+  %34 = insertelement <4 x i32> %33, i32 %30, i64 3, !dbg !18
+  %35 = bitcast <4 x i32> %34 to <4 x float>, !dbg !18
+  %36 = fadd <4 x float> %20, %35, !dbg !19
+  %37 = add nuw nsw i32 %19, 8, !dbg !13
+  %38 = icmp ult i32 %19, 112, !dbg !13
+  br i1 %38, label %18, label %39, !dbg !13
+
+39:                                               ; preds = %18
+  %40 = and i32 %6, 63, !dbg !8
+  %41 = or i32 %16, %40, !dbg !12
+  %42 = or i32 %10, 3, !dbg !20
+  %43 = or i32 %10, 2, !dbg !20
+  %44 = or i32 %10, 1, !dbg !20
+  %45 = extractelement <4 x float> %36, i64 0, !dbg !20
+  %46 = bitcast float %45 to i32, !dbg !20
+  %47 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %46, i32 16, i32 31), !dbg !20
+  %48 = bitcast i32 %47 to float, !dbg !20
+  %49 = fadd float %45, %48, !dbg !24
+  %50 = extractelement <4 x float> %36, i64 1, !dbg !20
+  %51 = bitcast float %50 to i32, !dbg !20
+  %52 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %51, i32 16, i32 31), !dbg !20
+  %53 = bitcast i32 %52 to float, !dbg !20
+  %54 = fadd float %50, %53, !dbg !24
+  %55 = extractelement <4 x float> %36, i64 2, !dbg !20
+  %56 = bitcast float %55 to i32, !dbg !20
+  %57 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %56, i32 16, i32 31), !dbg !20
+  %58 = bitcast i32 %57 to float, !dbg !20
+  %59 = fadd float %55, %58, !dbg !24
+  %60 = extractelement <4 x float> %36, i64 3, !dbg !20
+  %61 = bitcast float %60 to i32, !dbg !20
+  %62 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %61, i32 16, i32 31), !dbg !20
+  %63 = bitcast i32 %62 to float, !dbg !20
+  %64 = fadd float %60, %63, !dbg !24
+  %65 = icmp ult i32 %7, 16, !dbg !20
+  %66 = shl nuw nsw i32 %10, 2, !dbg !20
+  %67 = or i32 %66, %11, !dbg !20
+  %68 = zext nneg i32 %67 to i64, !dbg !20
+  %69 = getelementptr float, ptr addrspace(3) @global_smem, i64 %68, !dbg !20
+  tail call void asm sideeffect "@$2 st.shared.b32 [ $0 + 0 ], $1;", "r,r,b"(ptr addrspace(3) %69, float %49, i1 %65) #3, !dbg !20
+  %70 = shl nuw nsw i32 %44, 2, !dbg !20
+  %71 = or i32 %70, %11, !dbg !20
+  %72 = zext nneg i32 %71 to i64, !dbg !20
+  %73 = getelementptr float, ptr addrspace(3) @global_smem, i64 %72, !dbg !20
+  tail call void asm sideeffect "@$2 st.shared.b32 [ $0 + 0 ], $1;", "r,r,b"(ptr addrspace(3) %73, float %54, i1 %65) #3, !dbg !20
+  %74 = shl nuw nsw i32 %43, 2, !dbg !20
+  %75 = or i32 %74, %11, !dbg !20
+  %76 = zext nneg i32 %75 to i64, !dbg !20
+  %77 = getelementptr float, ptr addrspace(3) @global_smem, i64 %76, !dbg !20
+  tail call void asm sideeffect "@$2 st.shared.b32 [ $0 + 0 ], $1;", "r,r,b"(ptr addrspace(3) %77, float %59, i1 %65) #3, !dbg !20
+  %78 = shl nuw nsw i32 %42, 2, !dbg !20
+  %79 = or i32 %78, %11, !dbg !20
+  %80 = zext nneg i32 %79 to i64, !dbg !20
+  %81 = getelementptr float, ptr addrspace(3) @global_smem, i64 %80, !dbg !20
+  tail call void asm sideeffect "@$2 st.shared.b32 [ $0 + 0 ], $1;", "r,r,b"(ptr addrspace(3) %81, float %64, i1 %65) #3, !dbg !20
+  tail call void @llvm.nvvm.barrier0(), !dbg !20
+  %82 = icmp slt i32 %6, 256, !dbg !20
+  %83 = sext i32 %6 to i64, !dbg !20
+  %84 = getelementptr float, ptr addrspace(3) @global_smem, i64 %83, !dbg !20
+  %85 = tail call float asm sideeffect "@$2 ld.shared.b32 $0, [ $1 + 0 ];", "=r,r,b"(ptr addrspace(3) %84, i1 %82) #3, !dbg !20
+  %86 = bitcast float %85 to i32, !dbg !20
+  %87 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %86, i32 2, i32 31), !dbg !20
+  %88 = bitcast i32 %87 to float, !dbg !20
+  %89 = fadd float %85, %88, !dbg !24
+  %90 = bitcast float %89 to i32, !dbg !20
+  %91 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %90, i32 1, i32 31), !dbg !20
+  %92 = bitcast i32 %91 to float, !dbg !20
+  %93 = fadd float %89, %92, !dbg !24
+  %94 = and i32 %6, 3, !dbg !20
+  %95 = icmp eq i32 %94, 0, !dbg !20
+  %96 = and i1 %82, %95, !dbg !20
+  tail call void asm sideeffect "@$2 st.shared.b32 [ $0 + 0 ], $1;", "r,r,b"(ptr addrspace(3) %84, float %93, i1 %96) #3, !dbg !20
+  %97 = add i32 %6, 128, !dbg !20
+  %98 = sext i32 %97 to i64, !dbg !20
+  %99 = getelementptr float, ptr addrspace(3) @global_smem, i64 %98, !dbg !20
+  %100 = tail call float asm sideeffect "@$2 ld.shared.b32 $0, [ $1 + 0 ];", "=r,r,b"(ptr addrspace(3) %99, i1 %82) #3, !dbg !20
+  %101 = bitcast float %100 to i32, !dbg !20
+  %102 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %101, i32 2, i32 31), !dbg !20
+  %103 = bitcast i32 %102 to float, !dbg !20
+  %104 = fadd float %100, %103, !dbg !24
+  %105 = bitcast float %104 to i32, !dbg !20
+  %106 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %105, i32 1, i32 31), !dbg !20
+  %107 = bitcast i32 %106 to float, !dbg !20
+  %108 = fadd float %104, %107, !dbg !24
+  tail call void asm sideeffect "@$2 st.shared.b32 [ $0 + 0 ], $1;", "r,r,b"(ptr addrspace(3) %99, float %108, i1 %96) #3, !dbg !20
+  tail call void @llvm.nvvm.barrier0(), !dbg !20
+  %109 = zext nneg i32 %66 to i64, !dbg !20
+  %110 = getelementptr float, ptr addrspace(3) @global_smem, i64 %109, !dbg !20
+  %111 = load float, ptr addrspace(3) %110, align 4, !dbg !20
+  %112 = zext nneg i32 %70 to i64, !dbg !20
+  %113 = getelementptr float, ptr addrspace(3) @global_smem, i64 %112, !dbg !20
+  %114 = load float, ptr addrspace(3) %113, align 4, !dbg !20
+  %115 = zext nneg i32 %74 to i64, !dbg !20
+  %116 = getelementptr float, ptr addrspace(3) @global_smem, i64 %115, !dbg !20
+  %117 = load float, ptr addrspace(3) %116, align 4, !dbg !20
+  %118 = zext nneg i32 %78 to i64, !dbg !20
+  %119 = getelementptr float, ptr addrspace(3) @global_smem, i64 %118, !dbg !20
+  %120 = load float, ptr addrspace(3) %119, align 4, !dbg !20
+  tail call void @llvm.nvvm.barrier0(), !dbg !28
+  %121 = zext nneg i32 %10 to i64, !dbg !28
+  %122 = getelementptr float, ptr addrspace(3) @global_smem, i64 %121, !dbg !28
+  %123 = insertelement <1 x float> undef, float %111, i64 0, !dbg !28
+  store <1 x float> %123, ptr addrspace(3) %122, align 4, !dbg !28
+  %124 = zext nneg i32 %44 to i64, !dbg !28
+  %125 = getelementptr float, ptr addrspace(3) @global_smem, i64 %124, !dbg !28
+  %126 = insertelement <1 x float> undef, float %114, i64 0, !dbg !28
+  store <1 x float> %126, ptr addrspace(3) %125, align 4, !dbg !28
+  %127 = zext nneg i32 %43 to i64, !dbg !28
+  %128 = getelementptr float, ptr addrspace(3) @global_smem, i64 %127, !dbg !28
+  %129 = insertelement <1 x float> undef, float %117, i64 0, !dbg !28
+  store <1 x float> %129, ptr addrspace(3) %128, align 4, !dbg !28
+  %130 = zext nneg i32 %42 to i64, !dbg !28
+  %131 = getelementptr float, ptr addrspace(3) @global_smem, i64 %130, !dbg !28
+  %132 = insertelement <1 x float> undef, float %120, i64 0, !dbg !28
+  store <1 x float> %132, ptr addrspace(3) %131, align 4, !dbg !28
+  tail call void @llvm.nvvm.barrier0(), !dbg !28
+  %133 = zext nneg i32 %40 to i64, !dbg !28
+  %134 = getelementptr float, ptr addrspace(3) @global_smem, i64 %133, !dbg !28
+  %135 = load <1 x float>, ptr addrspace(3) %134, align 4, !dbg !28
+  %.frozen = freeze i32 %41
+  %136 = sdiv i32 %.frozen, 256, !dbg !29
+  %137 = mul i32 %136, 256
+  %.decomposed = sub i32 %.frozen, %137
+  %138 = sext i32 %136 to i64, !dbg !30
+  %139 = getelementptr i64, ptr addrspace(1) %1, i64 %138, !dbg !30
+  %140 = tail call i64 asm sideeffect "mov.u64 $0, 0x0;\0A\09@$2 ld.global.L1::evict_last.b64 { $0 }, [ $1 + 0 ];", "=l,l,b"(ptr addrspace(1) %139, i1 true) #3, !dbg !31
+  %141 = lshr i64 %140, 54, !dbg !32
+  %142 = and i64 %141, 512, !dbg !32
+  %143 = add i64 %142, %140, !dbg !32
+  %144 = shl i64 %143, 8, !dbg !33
+  %145 = sext i32 %.decomposed to i64, !dbg !34
+  %146 = getelementptr float, ptr addrspace(1) %2, i64 %144, !dbg !35
+  %147 = getelementptr float, ptr addrspace(1) %146, i64 %145, !dbg !35
+  %148 = and i32 %6, 64, !dbg !36
+  %149 = icmp eq i32 %148, 0, !dbg !36
+  %150 = tail call float asm sideeffect "mov.u32 $0, 0x0;\0A\09@$3 atom.global.gpu.acq_rel.add.f32 $0, [ $1 + 0 ], $2;", "=r,l,r,b"(ptr addrspace(1) %147, <1 x float> %135, i1 %149) #3, !dbg !36
+  ret void, !dbg !37
+}
+
+; Function Attrs: mustprogress nocallback nofree nosync nounwind speculatable willreturn memory(none)
+declare noundef i32 @llvm.nvvm.read.ptx.sreg.tid.x() #0
+
+; Function Attrs: convergent nocallback nounwind memory(inaccessiblemem: readwrite)
+declare i32 @llvm.nvvm.shfl.sync.bfly.i32(i32, i32, i32, i32) #1
+
+; Function Attrs: convergent nocallback nounwind
+declare void @llvm.nvvm.barrier0() #2
+
+attributes #0 = { mustprogress nocallback nofree nosync nounwind speculatable willreturn memory(none) }
+attributes #1 = { convergent nocallback nounwind memory(inaccessiblemem: readwrite) }
+attributes #2 = { convergent nocallback nounwind }
+attributes #3 = { nounwind }
+
+!llvm.module.flags = !{!0}
+!llvm.dbg.cu = !{!1}
+!nvvm.annotations = !{!3, !4, !4, !3}
+
+!0 = !{i32 2, !"Debug Info Version", i32 3}
+!1 = distinct !DICompileUnit(language: DW_LANG_C, file: !2, producer: "triton", isOptimized: true, runtimeVersion: 0, emissionKind: FullDebug)
+!2 = !DIFile(filename: "c6ik5vx7p22fpk4dcvh55zimw4t5nr5zn2b7inujxjauxshljumm.py", directory: "/tmp/torchinductor_root/6i")
+!3 = !{ptr @triton__0d1d2d3de4e, !"kernel", i32 1}
+!4 = !{ptr @triton__0d1d2d3de4e, !"maxntidx", i32 128}
+!5 = distinct !DISubprogram(name: "triton__0d1d2d3de4e", linkageName: "triton__0d1d2d3de4e", scope: !2, file: !2, line: 18, type: !6, scopeLine: 18, spFlags: DISPFlagDefinition | DISPFlagOptimized, unit: !1)
+!6 = !DISubroutineType(cc: DW_CC_normal, types: !7)
+!7 = !{}
+!8 = !DILocation(line: 22, column: 44, scope: !5)
+!9 = !DILocation(line: 24, column: 33, scope: !5)
+!10 = !DILocation(line: 21, column: 28, scope: !5)
+!11 = !DILocation(line: 21, column: 33, scope: !5)
+!12 = !DILocation(line: 22, column: 23, scope: !5)
+!13 = !DILocation(line: 27, column: 36, scope: !5)
+!14 = !DILocation(line: 28, column: 27, scope: !5)
+!15 = !DILocation(line: 31, column: 47, scope: !5)
+!16 = !DILocation(line: 31, column: 40, scope: !5)
+!17 = !DILocation(line: 31, column: 34, scope: !5)
+!18 = !DILocation(line: 31, column: 53, scope: !5)
+!19 = !DILocation(line: 34, column: 38, scope: !5)
+!20 = !DILocation(line: 243, column: 36, scope: !21, inlinedAt: !23)
+!21 = distinct !DILexicalBlockFile(scope: !5, file: !22, discriminator: 0)
+!22 = !DIFile(filename: "standard.py", directory: "/usr/local/lib/python3.10/dist-packages/triton/language")
+!23 = !DILocation(line: 35, column: 25, scope: !21)
+!24 = !DILocation(line: 233, column: 15, scope: !25, inlinedAt: !26)
+!25 = distinct !DILexicalBlockFile(scope: !21, file: !22, discriminator: 0)
+!26 = !DILocation(line: 243, column: 36, scope: !25, inlinedAt: !27)
+!27 = !DILocation(line: 35, column: 25, scope: !25)
+!28 = !DILocation(line: 35, column: 28, scope: !5)
+!29 = !DILocation(line: 36, column: 20, scope: !5)
+!30 = !DILocation(line: 38, column: 30, scope: !5)
+!31 = !DILocation(line: 38, column: 35, scope: !5)
+!32 = !DILocation(line: 41, column: 32, scope: !5)
+!33 = !DILocation(line: 45, column: 40, scope: !5)
+!34 = !DILocation(line: 45, column: 36, scope: !5)
+!35 = !DILocation(line: 45, column: 30, scope: !5)
+!36 = !DILocation(line: 45, column: 55, scope: !5)
+!37 = !DILocation(line: 45, column: 4, scope: !5)

.triton/dump/a4652f539404a11e3c068d96115a7427/triton_.ptx

@@ -0,0 +1,296 @@
+//
+// Generated by LLVM NVPTX Back-End
+//
+
+.version 8.2
+.target sm_89
+.address_size 64
+
+	// .globl	triton__0d1d2de
+
+.visible .entry triton__0d1d2de(
+	.param .u64 triton__0d1d2de_param_0,
+	.param .u64 triton__0d1d2de_param_1,
+	.param .u32 triton__0d1d2de_param_2
+)
+.maxntid 128, 1, 1
+{
+	.reg .pred 	%p<3>;
+	.reg .b16 	%rs<3>;
+	.reg .b32 	%r<12>;
+	.reg .b64 	%rd<7>;
+	.loc	1 18 0
+$L__func_begin0:
+	.loc	1 18 0
+
+	ld.param.u64 	%rd3, [triton__0d1d2de_param_0];
+	ld.param.u64 	%rd4, [triton__0d1d2de_param_1];
+$L__tmp0:
+	.loc	1 21 36
+	mov.u32 	%r7, %tid.x;
+	shl.b32 	%r8, %r7, 1;
+	and.b32  	%r9, %r8, 254;
+	.loc	1 20 28
+	mov.u32 %r1, %ctaid.x;
+	.loc	1 20 33
+	shl.b32 	%r10, %r1, 8;
+	.loc	1 21 23
+	or.b32  	%r11, %r10, %r9;
+	.loc	1 24 30
+	mul.wide.s32 	%rd5, %r11, 2;
+	add.s64 	%rd1, %rd3, %rd5;
+	mov.pred 	%p1, -1;
+	.loc	1 24 35
+	mov.u32 %r2, 0x0;
+	@%p1 ld.global.b32 { %r2 }, [ %rd1 + 0 ];
+	cvt.u16.u32 	%rs1, %r2;
+	{ .reg .b16 tmp; mov.b32 {tmp, %rs2}, %r2; }
+	.loc	1 24 44
+	cvt.f32.bf16 %r5, %rs1;
+	cvt.f32.bf16 %r6, %rs2;
+	.loc	1 26 25
+	mul.wide.s32 	%rd6, %r11, 4;
+	add.s64 	%rd2, %rd4, %rd6;
+	.loc	1 26 36
+	@%p1 st.global.v2.b32 [ %rd2 + 0 ], { %r5, %r6 };
+	.loc	1 26 4
+	ret;
+$L__tmp1:
+$L__func_end0:
+
+}
+	.file	1 "/tmp/torchinductor_root/zl/czl6nmwasl7k4ic55xowihczcooh3mhu5v6ls6w2xzqqocdc2da7.py"
+	.section	.debug_abbrev
+	{
+.b8 1
+.b8 17
+.b8 1
+.b8 37
+.b8 8
+.b8 19
+.b8 5
+.b8 3
+.b8 8
+.b8 16
+.b8 6
+.b8 27
+.b8 8
+.b8 180
+.b8 66
+.b8 12
+.b8 17
+.b8 1
+.b8 18
+.b8 1
+.b8 0
+.b8 0
+.b8 2
+.b8 46
+.b8 0
+.b8 17
+.b8 1
+.b8 18
+.b8 1
+.b8 64
+.b8 10
+.b8 135
+.b8 64
+.b8 8
+.b8 3
+.b8 8
+.b8 58
+.b8 11
+.b8 59
+.b8 11
+.b8 63
+.b8 12
+.b8 0
+.b8 0
+.b8 0
+	}
+	.section	.debug_info
+	{
+.b32 176
+.b8 2
+.b8 0
+.b32 .debug_abbrev
+.b8 8
+.b8 1
+.b8 116
+.b8 114
+.b8 105
+.b8 116
+.b8 111
+.b8 110
+.b8 0
+.b8 2
+.b8 0
+.b8 99
+.b8 122
+.b8 108
+.b8 54
+.b8 110
+.b8 109
+.b8 119
+.b8 97
+.b8 115
+.b8 108
+.b8 55
+.b8 107
+.b8 52
+.b8 105
+.b8 99
+.b8 53
+.b8 53
+.b8 120
+.b8 111
+.b8 119
+.b8 105
+.b8 104
+.b8 99
+.b8 122
+.b8 99
+.b8 111
+.b8 111
+.b8 104
+.b8 51
+.b8 109
+.b8 104
+.b8 117
+.b8 53
+.b8 118
+.b8 54
+.b8 108
+.b8 115
+.b8 54
+.b8 119
+.b8 50
+.b8 120
+.b8 122
+.b8 113
+.b8 113
+.b8 111
+.b8 99
+.b8 100
+.b8 99
+.b8 50
+.b8 100
+.b8 97
+.b8 55
+.b8 46
+.b8 112
+.b8 121
+.b8 0
+.b32 .debug_line
+.b8 47
+.b8 116
+.b8 109
+.b8 112
+.b8 47
+.b8 116
+.b8 111
+.b8 114
+.b8 99
+.b8 104
+.b8 105
+.b8 110
+.b8 100
+.b8 117
+.b8 99
+.b8 116
+.b8 111
+.b8 114
+.b8 95
+.b8 114
+.b8 111
+.b8 111
+.b8 116
+.b8 47
+.b8 122
+.b8 108
+.b8 0
+.b8 1
+.b64 $L__func_begin0
+.b64 $L__func_end0
+.b8 2
+.b64 $L__func_begin0
+.b64 $L__func_end0
+.b8 1
+.b8 156
+.b8 116
+.b8 114
+.b8 105
+.b8 116
+.b8 111
+.b8 110
+.b8 95
+.b8 95
+.b8 48
+.b8 100
+.b8 49
+.b8 100
+.b8 50
+.b8 100
+.b8 101
+.b8 0
+.b8 116
+.b8 114
+.b8 105
+.b8 116
+.b8 111
+.b8 110
+.b8 95
+.b8 95
+.b8 48
+.b8 100
+.b8 49
+.b8 100
+.b8 50
+.b8 100
+.b8 101
+.b8 0
+.b8 1
+.b8 18
+.b8 1
+.b8 0
+	}
+	.section	.debug_pubnames
+	{
+.b32 $L__pubNames_end0-$L__pubNames_start0
+$L__pubNames_start0:
+.b8 2
+.b8 0
+.b32 .debug_info
+.b32 180
+.b32 125
+.b8 116
+.b8 114
+.b8 105
+.b8 116
+.b8 111
+.b8 110
+.b8 95
+.b8 95
+.b8 48
+.b8 100
+.b8 49
+.b8 100
+.b8 50
+.b8 100
+.b8 101
+.b8 0
+.b32 0
+$L__pubNames_end0:
+	}
+	.section	.debug_pubtypes
+	{
+.b32 $L__pubTypes_end0-$L__pubTypes_start0
+$L__pubTypes_start0:
+.b8 2
+.b8 0
+.b32 .debug_info
+.b32 180
+.b32 0
+$L__pubTypes_end0:
+	}
+	.section	.debug_loc	{	}

.triton/dump/a99a310eb97b8a71c8c7102625cff179/triton_.ptx

@@ -0,0 +1,777 @@
+//
+// Generated by LLVM NVPTX Back-End
+//
+
+.version 8.2
+.target sm_89
+.address_size 64
+
+	// .globl	triton__0d1d2d3d4d5d6d7d8de9de
+.extern .shared .align 1 .b8 global_smem[];
+
+.visible .entry triton__0d1d2d3d4d5d6d7d8de9de(
+	.param .u64 triton__0d1d2d3d4d5d6d7d8de9de_param_0,
+	.param .u64 triton__0d1d2d3d4d5d6d7d8de9de_param_1,
+	.param .u64 triton__0d1d2d3d4d5d6d7d8de9de_param_2,
+	.param .u64 triton__0d1d2d3d4d5d6d7d8de9de_param_3,
+	.param .u64 triton__0d1d2d3d4d5d6d7d8de9de_param_4,
+	.param .u64 triton__0d1d2d3d4d5d6d7d8de9de_param_5,
+	.param .u64 triton__0d1d2d3d4d5d6d7d8de9de_param_6,
+	.param .u64 triton__0d1d2d3d4d5d6d7d8de9de_param_7,
+	.param .u32 triton__0d1d2d3d4d5d6d7d8de9de_param_8,
+	.param .u32 triton__0d1d2d3d4d5d6d7d8de9de_param_9
+)
+.maxntid 64, 1, 1
+{
+	.reg .pred 	%p<40>;
+	.reg .b16 	%rs<13>;
+	.reg .b32 	%r<118>;
+	.reg .f32 	%f<94>;
+	.reg .b64 	%rd<28>;
+	.loc	1 18 0
+$L__func_begin0:
+	.loc	1 18 0
+
+	ld.param.u64 	%rd16, [triton__0d1d2d3d4d5d6d7d8de9de_param_0];
+	ld.param.u64 	%rd17, [triton__0d1d2d3d4d5d6d7d8de9de_param_1];
+$L__tmp0:
+	.loc	1 26 26
+	mov.u32 	%r84, %tid.x;
+	and.b32  	%r85, %r84, 31;
+	ld.param.u64 	%rd18, [triton__0d1d2d3d4d5d6d7d8de9de_param_2];
+	ld.param.u64 	%rd19, [triton__0d1d2d3d4d5d6d7d8de9de_param_3];
+	ld.param.u64 	%rd20, [triton__0d1d2d3d4d5d6d7d8de9de_param_4];
+	shl.b32 	%r86, %r84, 2;
+	ld.param.u64 	%rd21, [triton__0d1d2d3d4d5d6d7d8de9de_param_5];
+	and.b32  	%r87, %r86, 252;
+	ld.param.u64 	%rd22, [triton__0d1d2d3d4d5d6d7d8de9de_param_6];
+	ld.param.u64 	%rd23, [triton__0d1d2d3d4d5d6d7d8de9de_param_7];
+	.loc	1 23 28
+	mov.u32 %r1, %ctaid.x;
+	.loc	1 30 40
+	shl.b32 	%r88, %r1, 8;
+	.loc	1 30 36
+	or.b32  	%r89, %r88, %r87;
+	.loc	1 30 30
+	mul.wide.s32 	%rd24, %r89, 2;
+	add.s64 	%rd1, %rd17, %rd24;
+	mov.b32 	%r4, 0;
+	mov.pred 	%p1, -1;
+	.loc	1 30 46
+	mov.u32 %r2, 0x0;
+	mov.u32 %r3, 0x0;
+	@%p1 ld.global.v2.b32 { %r2, %r3 }, [ %rd1 + 0 ];
+	@!%p1 mov.u32 %r2, %r4;
+	@!%p1 mov.u32 %r3, %r4;
+	cvt.u16.u32 	%rs1, %r2;
+	{ .reg .b16 tmp; mov.b32 {tmp, %rs2}, %r2; }
+	cvt.u16.u32 	%rs3, %r3;
+	{ .reg .b16 tmp; mov.b32 {tmp, %rs4}, %r3; }
+	.loc	1 30 67
+	cvt.f32.bf16 %r6, %rs1;
+	mov.b32 	%f1, %r6;
+	cvt.f32.bf16 %r7, %rs2;
+	mov.b32 	%f2, %r7;
+	cvt.f32.bf16 %r8, %rs3;
+	mov.b32 	%f3, %r8;
+	cvt.f32.bf16 %r9, %rs4;
+	mov.b32 	%f4, %r9;
+	.loc	1 31 30
+	mul.wide.u32 	%rd25, %r87, 4;
+	add.s64 	%rd2, %rd18, %rd25;
+	.loc	1 31 35
+	mov.u32 %r10, 0x0;
+	mov.u32 %r11, 0x0;
+	mov.u32 %r12, 0x0;
+	mov.u32 %r13, 0x0;
+	@%p1 ld.global.L1::evict_last.v4.b32 { %r10, %r11, %r12, %r13 }, [ %rd2 + 0 ];
+	@!%p1 mov.u32 %r10, %r4;
+	@!%p1 mov.u32 %r11, %r4;
+	@!%p1 mov.u32 %r12, %r4;
+	@!%p1 mov.u32 %r13, %r4;
+	mov.b32 	%f5, %r10;
+	mov.b32 	%f6, %r11;
+	mov.b32 	%f7, %r12;
+	mov.b32 	%f8, %r13;
+	.loc	1 32 30
+	mul.wide.s32 	%rd26, %r89, 4;
+	add.s64 	%rd3, %rd19, %rd26;
+	.loc	1 32 46
+	mov.u32 %r18, 0x0;
+	mov.u32 %r19, 0x0;
+	mov.u32 %r20, 0x0;
+	mov.u32 %r21, 0x0;
+	@%p1 ld.global.v4.b32 { %r18, %r19, %r20, %r21 }, [ %rd3 + 0 ];
+	@!%p1 mov.u32 %r18, %r4;
+	@!%p1 mov.u32 %r19, %r4;
+	@!%p1 mov.u32 %r20, %r4;
+	@!%p1 mov.u32 %r21, %r4;
+	mov.b32 	%f9, %r18;
+	mov.b32 	%f10, %r19;
+	mov.b32 	%f11, %r20;
+	mov.b32 	%f12, %r21;
+	.loc	1 33 30
+	add.s64 	%rd4, %rd20, %rd24;
+	.loc	1 33 46
+	mov.u32 %r26, 0x0;
+	mov.u32 %r27, 0x0;
+	@%p1 ld.global.v2.b32 { %r26, %r27 }, [ %rd4 + 0 ];
+	@!%p1 mov.u32 %r26, %r4;
+	@!%p1 mov.u32 %r27, %r4;
+	cvt.u16.u32 	%rs5, %r26;
+	{ .reg .b16 tmp; mov.b32 {tmp, %rs6}, %r26; }
+	cvt.u16.u32 	%rs7, %r27;
+	{ .reg .b16 tmp; mov.b32 {tmp, %rs8}, %r27; }
+	.loc	1 33 67
+	cvt.f32.bf16 %r30, %rs5;
+	mov.b32 	%f13, %r30;
+	cvt.f32.bf16 %r31, %rs6;
+	mov.b32 	%f14, %r31;
+	cvt.f32.bf16 %r32, %rs7;
+	mov.b32 	%f15, %r32;
+	cvt.f32.bf16 %r33, %rs8;
+	mov.b32 	%f16, %r33;
+	.loc	1 34 31
+	mul.wide.s32 	%rd27, %r1, 4;
+	add.s64 	%rd5, %rd21, %rd27;
+	.loc	1 34 36
+	mov.u32 %r34, 0x0;
+	@%p1 ld.global.L1::evict_last.b32 { %r34 }, [ %rd5 + 0 ];
+	mov.b32 	%f17, %r34;
+	mov.u32 %r35, 0x0;
+	@%p1 ld.global.L1::evict_last.b32 { %r35 }, [ %rd5 + 0 ];
+	mov.u32 %r36, 0x0;
+	@%p1 ld.global.L1::evict_last.b32 { %r36 }, [ %rd5 + 0 ];
+	mov.u32 %r37, 0x0;
+	@%p1 ld.global.L1::evict_last.b32 { %r37 }, [ %rd5 + 0 ];
+	.loc	1 35 31
+	add.s64 	%rd9, %rd22, %rd27;
+	.loc	1 35 36
+	mov.u32 %r63, 0x0;
+	@%p1 ld.global.L1::evict_last.b32 { %r63 }, [ %rd9 + 0 ];
+	mov.b32 	%f18, %r63;
+	mov.u32 %r39, 0x0;
+	@%p1 ld.global.L1::evict_last.b32 { %r39 }, [ %rd9 + 0 ];
+	mov.u32 %r40, 0x0;
+	@%p1 ld.global.L1::evict_last.b32 { %r40 }, [ %rd9 + 0 ];
+	mov.u32 %r41, 0x0;
+	@%p1 ld.global.L1::evict_last.b32 { %r41 }, [ %rd9 + 0 ];
+	.loc	1 36 35
+	add.s64 	%rd13, %rd16, %rd26;
+	.loc	1 36 51
+	mov.u32 %r42, 0x0;
+	mov.u32 %r43, 0x0;
+	mov.u32 %r44, 0x0;
+	mov.u32 %r45, 0x0;
+	@%p1 ld.global.v4.b32 { %r42, %r43, %r44, %r45 }, [ %rd13 + 0 ];
+	@!%p1 mov.u32 %r42, %r4;
+	@!%p1 mov.u32 %r43, %r4;
+	@!%p1 mov.u32 %r44, %r4;
+	@!%p1 mov.u32 %r45, %r4;
+	mov.b32 	%f19, %r42;
+	mov.b32 	%f20, %r43;
+	mov.b32 	%f21, %r44;
+	mov.b32 	%f22, %r45;
+	.loc	1 38 18
+	mul.f32 	%f23, %f1, %f5;
+	mul.f32 	%f24, %f2, %f6;
+	mul.f32 	%f25, %f3, %f7;
+	mul.f32 	%f26, %f4, %f8;
+$L__tmp1:
+	.loc	2 233 15
+	fma.rn.f32 	%f27, %f1, %f5, %f24;
+	fma.rn.f32 	%f28, %f3, %f7, %f27;
+	fma.rn.f32 	%f29, %f4, %f8, %f28;
+$L__tmp2:
+	.loc	2 243 36
+	mov.b32 	%r90, %f29;
+	shfl.sync.bfly.b32	%r91, %r90, 16, 31, -1;
+	mov.b32 	%f30, %r91;
+$L__tmp3:
+	.loc	2 233 15
+	add.f32 	%f31, %f29, %f30;
+$L__tmp4:
+	.loc	2 243 36
+	mov.b32 	%r92, %f31;
+	shfl.sync.bfly.b32	%r93, %r92, 8, 31, -1;
+	mov.b32 	%f32, %r93;
+$L__tmp5:
+	.loc	2 233 15
+	add.f32 	%f33, %f31, %f32;
+$L__tmp6:
+	.loc	2 243 36
+	mov.b32 	%r94, %f33;
+	shfl.sync.bfly.b32	%r95, %r94, 4, 31, -1;
+	mov.b32 	%f34, %r95;
+$L__tmp7:
+	.loc	2 233 15
+	add.f32 	%f35, %f33, %f34;
+$L__tmp8:
+	.loc	2 243 36
+	mov.b32 	%r96, %f35;
+	shfl.sync.bfly.b32	%r97, %r96, 2, 31, -1;
+	mov.b32 	%f36, %r97;
+$L__tmp9:
+	.loc	2 233 15
+	add.f32 	%f37, %f35, %f36;
+$L__tmp10:
+	.loc	2 243 36
+	mov.b32 	%r98, %f37;
+	shfl.sync.bfly.b32	%r99, %r98, 1, 31, -1;
+	mov.b32 	%f38, %r99;
+$L__tmp11:
+	.loc	2 233 15
+	add.f32 	%f39, %f37, %f38;
+$L__tmp12:
+	.loc	2 243 36
+	setp.eq.s32 	%p30, %r85, 0;
+	shr.u32 	%r100, %r84, 3;
+	and.b32  	%r101, %r100, 4;
+	mov.u32 	%r102, global_smem;
+	add.s32 	%r50, %r102, %r101;
+	mov.b32 	%r51, %f39;
+	@%p30 st.shared.b32 [ %r50 + 0 ], %r51;
+	bar.sync 	0;
+	setp.lt.s32 	%p31, %r84, 2;
+	add.s32 	%r53, %r102, %r86;
+	@%p31 ld.shared.b32 %r52, [ %r53 + 0 ];
+	mov.b32 	%f40, %r52;
+	shfl.sync.bfly.b32	%r103, %r52, 1, 31, -1;
+	mov.b32 	%f41, %r103;
+$L__tmp13:
+	.loc	2 233 15
+	add.f32 	%f42, %f40, %f41;
+$L__tmp14:
+	.loc	2 243 36
+	and.b32  	%r104, %r84, 1;
+	setp.eq.b32 	%p38, %r104, 1;
+	not.pred 	%p39, %p38;
+	and.pred  	%p32, %p31, %p39;
+	mov.b32 	%r55, %f42;
+	@%p32 st.shared.b32 [ %r53 + 0 ], %r55;
+	bar.sync 	0;
+	ld.shared.f32 	%f43, [global_smem];
+$L__tmp15:
+	.loc	3 8 15
+	add.f32 	%f44, %f43, 0f00000000;
+$L__tmp16:
+	.loc	1 43 19
+	add.f32 	%f45, %f13, %f9;
+	add.f32 	%f46, %f14, %f10;
+	add.f32 	%f47, %f15, %f11;
+	add.f32 	%f48, %f16, %f12;
+	.loc	1 44 20
+	sub.f32 	%f49, %f45, %f17;
+	sub.f32 	%f50, %f46, %f17;
+	sub.f32 	%f51, %f47, %f17;
+	sub.f32 	%f52, %f48, %f17;
+	.loc	1 45 20
+	mul.f32 	%f53, %f49, %f18;
+	mul.f32 	%f54, %f50, %f18;
+	mul.f32 	%f55, %f51, %f18;
+	mul.f32 	%f56, %f52, %f18;
+	.loc	1 46 19
+	mul.f32 	%f57, %f24, %f54;
+$L__tmp17:
+	.loc	2 243 36
+	bar.sync 	0;
+$L__tmp18:
+	.loc	2 233 15
+	fma.rn.f32 	%f58, %f23, %f53, %f57;
+	fma.rn.f32 	%f59, %f25, %f55, %f58;
+	fma.rn.f32 	%f60, %f26, %f56, %f59;
+$L__tmp19:
+	.loc	2 243 36
+	mov.b32 	%r105, %f60;
+	shfl.sync.bfly.b32	%r106, %r105, 16, 31, -1;
+	mov.b32 	%f61, %r106;
+$L__tmp20:
+	.loc	2 233 15
+	add.f32 	%f62, %f60, %f61;
+$L__tmp21:
+	.loc	2 243 36
+	mov.b32 	%r107, %f62;
+	shfl.sync.bfly.b32	%r108, %r107, 8, 31, -1;
+	mov.b32 	%f63, %r108;
+$L__tmp22:
+	.loc	2 233 15
+	add.f32 	%f64, %f62, %f63;
+$L__tmp23:
+	.loc	2 243 36
+	mov.b32 	%r109, %f64;
+	shfl.sync.bfly.b32	%r110, %r109, 4, 31, -1;
+	mov.b32 	%f65, %r110;
+$L__tmp24:
+	.loc	2 233 15
+	add.f32 	%f66, %f64, %f65;
+$L__tmp25:
+	.loc	2 243 36
+	mov.b32 	%r111, %f66;
+	shfl.sync.bfly.b32	%r112, %r111, 2, 31, -1;
+	mov.b32 	%f67, %r112;
+$L__tmp26:
+	.loc	2 233 15
+	add.f32 	%f68, %f66, %f67;
+$L__tmp27:
+	.loc	2 243 36
+	mov.b32 	%r113, %f68;
+	shfl.sync.bfly.b32	%r114, %r113, 1, 31, -1;
+	mov.b32 	%f69, %r114;
+$L__tmp28:
+	.loc	2 233 15
+	add.f32 	%f70, %f68, %f69;
+$L__tmp29:
+	.loc	2 243 36
+	mov.b32 	%r57, %f70;
+	@%p30 st.shared.b32 [ %r50 + 0 ], %r57;
+	bar.sync 	0;
+	@%p31 ld.shared.b32 %r58, [ %r53 + 0 ];
+	mov.b32 	%f71, %r58;
+	shfl.sync.bfly.b32	%r115, %r58, 1, 31, -1;
+	mov.b32 	%f72, %r115;
+$L__tmp30:
+	.loc	2 233 15
+	add.f32 	%f73, %f71, %f72;
+$L__tmp31:
+	.loc	2 243 36
+	mov.b32 	%r61, %f73;
+	@%p32 st.shared.b32 [ %r53 + 0 ], %r61;
+	bar.sync 	0;
+	ld.shared.f32 	%f74, [global_smem];
+$L__tmp32:
+	.loc	3 8 15
+	add.f32 	%f75, %f74, 0f00000000;
+	mov.b32 	%r64, 1132462080;
+$L__tmp33:
+	.loc	1 51 20
+	div.full.f32 %r62, %r63, %r64;
+	mov.b32 	%f76, %r62;
+	.loc	1 53 20
+	neg.f32 	%f77, %f44;
+	fma.rn.f32 	%f78, %f23, 0f43800000, %f77;
+	fma.rn.f32 	%f79, %f24, 0f43800000, %f77;
+	fma.rn.f32 	%f80, %f25, 0f43800000, %f77;
+	fma.rn.f32 	%f81, %f26, 0f43800000, %f77;
+	.loc	1 55 20
+	neg.f32 	%f82, %f53;
+	fma.rn.f32 	%f83, %f82, %f75, %f78;
+	neg.f32 	%f84, %f54;
+	fma.rn.f32 	%f85, %f84, %f75, %f79;
+	neg.f32 	%f86, %f55;
+	fma.rn.f32 	%f87, %f86, %f75, %f80;
+	neg.f32 	%f88, %f56;
+	fma.rn.f32 	%f89, %f88, %f75, %f81;
+	.loc	1 57 20
+	fma.rn.f32 	%f90, %f76, %f83, %f19;
+	fma.rn.f32 	%f91, %f76, %f85, %f20;
+	fma.rn.f32 	%f92, %f76, %f87, %f21;
+	fma.rn.f32 	%f93, %f76, %f89, %f22;
+	.loc	1 59 51
+	mov.b32 	%r74, %f90;
+	mov.b32 	%r75, %f91;
+	mov.b32 	%r76, %f92;
+	mov.b32 	%r77, %f93;
+	@%p1 st.global.v4.b32 [ %rd13 + 0 ], { %r74, %r75, %r76, %r77 };
+	.loc	1 60 25
+	add.s64 	%rd15, %rd23, %rd24;
+	.loc	1 60 48
+	cvt.rn.bf16.f32 %rs9, %r74;
+	cvt.rn.bf16.f32 %rs10, %r75;
+	cvt.rn.bf16.f32 %rs11, %r76;
+	cvt.rn.bf16.f32 %rs12, %r77;
+	mov.b32 	%r116, {%rs9, %rs10};
+	mov.b32 	%r117, {%rs11, %rs12};
+	@%p1 st.global.v2.b32 [ %rd15 + 0 ], { %r116, %r117 };
+	.loc	1 60 4
+	ret;
+$L__tmp34:
+$L__func_end0:
+
+}
+	.file	1 "/tmp/torchinductor_root/fh/cfhjzwujbd4bpel57x4hxw7d3m3qqfwrjg6bfe6e4wk2cyh77u45.py"
+	.file	2 "/usr/local/lib/python3.10/dist-packages/triton/language/standard.py"
+	.file	3 "/usr/local/lib/python3.10/dist-packages/torch/_inductor/triton_helpers.py"
+	.section	.debug_abbrev
+	{
+.b8 1
+.b8 17
+.b8 1
+.b8 37
+.b8 8
+.b8 19
+.b8 5
+.b8 3
+.b8 8
+.b8 16
+.b8 6
+.b8 27
+.b8 8
+.b8 180
+.b8 66
+.b8 12
+.b8 17
+.b8 1
+.b8 18
+.b8 1
+.b8 0
+.b8 0
+.b8 2
+.b8 46
+.b8 0
+.b8 135
+.b8 64
+.b8 8
+.b8 3
+.b8 8
+.b8 58
+.b8 11
+.b8 59
+.b8 11
+.b8 63
+.b8 12
+.b8 32
+.b8 11
+.b8 0
+.b8 0
+.b8 3
+.b8 46
+.b8 1
+.b8 17
+.b8 1
+.b8 18
+.b8 1
+.b8 64
+.b8 10
+.b8 49
+.b8 19
+.b8 0
+.b8 0
+.b8 4
+.b8 29
+.b8 1
+.b8 49
+.b8 19
+.b8 17
+.b8 1
+.b8 18
+.b8 1
+.b8 88
+.b8 11
+.b8 89
+.b8 11
+.b8 87
+.b8 11
+.b8 0
+.b8 0
+.b8 5
+.b8 29
+.b8 0
+.b8 49
+.b8 19
+.b8 17
+.b8 1
+.b8 18
+.b8 1
+.b8 88
+.b8 11
+.b8 89
+.b8 11
+.b8 87
+.b8 11
+.b8 0
+.b8 0
+.b8 0
+	}
+	.section	.debug_info
+	{
+.b32 407
+.b8 2
+.b8 0
+.b32 .debug_abbrev
+.b8 8
+.b8 1
+.b8 116
+.b8 114
+.b8 105
+.b8 116
+.b8 111
+.b8 110
+.b8 0
+.b8 2
+.b8 0
+.b8 99
+.b8 102
+.b8 104
+.b8 106
+.b8 122
+.b8 119
+.b8 117
+.b8 106
+.b8 98
+.b8 100
+.b8 52
+.b8 98
+.b8 112
+.b8 101
+.b8 108
+.b8 53
+.b8 55
+.b8 120
+.b8 52
+.b8 104
+.b8 120
+.b8 119
+.b8 55
+.b8 100
+.b8 51
+.b8 109
+.b8 51
+.b8 113
+.b8 113
+.b8 102
+.b8 119
+.b8 114
+.b8 106
+.b8 103
+.b8 54
+.b8 98
+.b8 102
+.b8 101
+.b8 54
+.b8 101
+.b8 52
+.b8 119
+.b8 107
+.b8 50
+.b8 99
+.b8 121
+.b8 104
+.b8 55
+.b8 55
+.b8 117
+.b8 52
+.b8 53
+.b8 46
+.b8 112
+.b8 121
+.b8 0
+.b32 .debug_line
+.b8 47
+.b8 116
+.b8 109
+.b8 112
+.b8 47
+.b8 116
+.b8 111
+.b8 114
+.b8 99
+.b8 104
+.b8 105
+.b8 110
+.b8 100
+.b8 117
+.b8 99
+.b8 116
+.b8 111
+.b8 114
+.b8 95
+.b8 114
+.b8 111
+.b8 111
+.b8 116
+.b8 47
+.b8 102
+.b8 104
+.b8 0
+.b8 1
+.b64 $L__func_begin0
+.b64 $L__func_end0
+.b8 2
+.b8 116
+.b8 114
+.b8 105
+.b8 116
+.b8 111
+.b8 110
+.b8 95
+.b8 95
+.b8 48
+.b8 100
+.b8 49
+.b8 100
+.b8 50
+.b8 100
+.b8 51
+.b8 100
+.b8 52
+.b8 100
+.b8 53
+.b8 100
+.b8 54
+.b8 100
+.b8 55
+.b8 100
+.b8 56
+.b8 100
+.b8 101
+.b8 57
+.b8 100
+.b8 101
+.b8 0
+.b8 116
+.b8 114
+.b8 105
+.b8 116
+.b8 111
+.b8 110
+.b8 95
+.b8 95
+.b8 48
+.b8 100
+.b8 49
+.b8 100
+.b8 50
+.b8 100
+.b8 51
+.b8 100
+.b8 52
+.b8 100
+.b8 53
+.b8 100
+.b8 54
+.b8 100
+.b8 55
+.b8 100
+.b8 56
+.b8 100
+.b8 101
+.b8 57
+.b8 100
+.b8 101
+.b8 0
+.b8 1
+.b8 18
+.b8 1
+.b8 1
+.b8 3
+.b64 $L__func_begin0
+.b64 $L__func_end0
+.b8 1
+.b8 156
+.b32 125
+.b8 4
+.b32 125
+.b64 $L__tmp1
+.b64 $L__tmp14
+.b8 2
+.b8 41
+.b8 57
+.b8 5
+.b32 125
+.b64 $L__tmp1
+.b64 $L__tmp14
+.b8 2
+.b8 243
+.b8 36
+.b8 0
+.b8 5
+.b32 125
+.b64 $L__tmp2
+.b64 $L__tmp15
+.b8 2
+.b8 41
+.b8 57
+.b8 5
+.b32 125
+.b64 $L__tmp15
+.b64 $L__tmp16
+.b8 3
+.b8 41
+.b8 44
+.b8 5
+.b32 125
+.b64 $L__tmp17
+.b64 $L__tmp32
+.b8 2
+.b8 49
+.b8 59
+.b8 4
+.b32 125
+.b64 $L__tmp18
+.b64 $L__tmp31
+.b8 2
+.b8 49
+.b8 59
+.b8 5
+.b32 125
+.b64 $L__tmp18
+.b64 $L__tmp31
+.b8 2
+.b8 243
+.b8 36
+.b8 0
+.b8 5
+.b32 125
+.b64 $L__tmp32
+.b64 $L__tmp33
+.b8 3
+.b8 49
+.b8 45
+.b8 0
+.b8 0
+	}
+	.section	.debug_pubnames
+	{
+.b32 $L__pubNames_end0-$L__pubNames_start0
+$L__pubNames_start0:
+.b8 2
+.b8 0
+.b32 .debug_info
+.b32 411
+.b32 125
+.b8 116
+.b8 114
+.b8 105
+.b8 116
+.b8 111
+.b8 110
+.b8 95
+.b8 95
+.b8 48
+.b8 100
+.b8 49
+.b8 100
+.b8 50
+.b8 100
+.b8 51
+.b8 100
+.b8 52
+.b8 100
+.b8 53
+.b8 100
+.b8 54
+.b8 100
+.b8 55
+.b8 100
+.b8 56
+.b8 100
+.b8 101
+.b8 57
+.b8 100
+.b8 101
+.b8 0
+.b32 0
+$L__pubNames_end0:
+	}
+	.section	.debug_pubtypes
+	{
+.b32 $L__pubTypes_end0-$L__pubTypes_start0
+$L__pubTypes_start0:
+.b8 2
+.b8 0
+.b32 .debug_info
+.b32 411
+.b32 0
+$L__pubTypes_end0:
+	}
+	.section	.debug_loc	{	}

.triton/dump/a99a310eb97b8a71c8c7102625cff179/triton_.ttgir

@@ -0,0 +1,78 @@
+#blocked = #triton_gpu.blocked<{sizePerThread = [4], threadsPerWarp = [32], warpsPerCTA = [2], order = [0], CTAsPerCGA = [1], CTASplitNum = [1], CTAOrder = [0]}>
+module attributes {"triton_gpu.compute-capability" = 89 : i32, "triton_gpu.num-ctas" = 1 : i32, "triton_gpu.num-warps" = 2 : i32, "triton_gpu.threads-per-warp" = 32 : i32} {
+  tt.func public @triton__0d1d2d3d4d5d6d7d8de9de(%arg0: !tt.ptr<f32, 1> {tt.divisibility = 16 : i32}, %arg1: !tt.ptr<bf16, 1> {tt.divisibility = 16 : i32}, %arg2: !tt.ptr<f32, 1> {tt.divisibility = 16 : i32}, %arg3: !tt.ptr<f32, 1> {tt.divisibility = 16 : i32}, %arg4: !tt.ptr<bf16, 1> {tt.divisibility = 16 : i32}, %arg5: !tt.ptr<f32, 1> {tt.divisibility = 16 : i32}, %arg6: !tt.ptr<f32, 1> {tt.divisibility = 16 : i32}, %arg7: !tt.ptr<bf16, 1> {tt.divisibility = 16 : i32}, %arg8: i32 {tt.divisibility = 16 : i32, tt.max_divisibility = 16 : i32}, %arg9: i32 {tt.divisibility = 16 : i32, tt.max_divisibility = 16 : i32}) attributes {noinline = false} {
+    %cst = arith.constant dense<256> : tensor<256xi32, #blocked>
+    %cst_0 = arith.constant dense<2.560000e+02> : tensor<1xf32, #blocked>
+    %cst_1 = arith.constant 0.000000e+00 : f32
+    %c256_i32 = arith.constant 256 : i32
+    %cst_2 = arith.constant dense<0.000000e+00> : tensor<256xf32, #blocked>
+    %cst_3 = arith.constant dense<2.560000e+02> : tensor<256xf32, #blocked>
+    %cst_4 = arith.constant dense<0.000000e+00> : tensor<256xbf16, #blocked>
+    %0 = tt.get_program_id x : i32
+    %1 = tt.make_range {end = 256 : i32, start = 0 : i32} : tensor<256xi32, #blocked>
+    %2 = arith.cmpi slt, %1, %cst : tensor<256xi32, #blocked>
+    %3 = arith.muli %0, %c256_i32 : i32
+    %4 = tt.splat %3 : (i32) -> tensor<256xi32, #blocked>
+    %5 = arith.addi %1, %4 : tensor<256xi32, #blocked>
+    %6 = tt.splat %arg1 : (!tt.ptr<bf16, 1>) -> tensor<256x!tt.ptr<bf16, 1>, #blocked>
+    %7 = tt.addptr %6, %5 : tensor<256x!tt.ptr<bf16, 1>, #blocked>, tensor<256xi32, #blocked>
+    %8 = tt.load %7, %2, %cst_4 {cache = 1 : i32, evict = 1 : i32, isVolatile = false} : tensor<256xbf16, #blocked>
+    %9 = arith.extf %8 : tensor<256xbf16, #blocked> to tensor<256xf32, #blocked>
+    %10 = tt.splat %arg2 : (!tt.ptr<f32, 1>) -> tensor<256x!tt.ptr<f32, 1>, #blocked>
+    %11 = tt.addptr %10, %1 : tensor<256x!tt.ptr<f32, 1>, #blocked>, tensor<256xi32, #blocked>
+    %12 = tt.load %11, %2, %cst_2 {cache = 1 : i32, evict = 3 : i32, isVolatile = false} : tensor<256xf32, #blocked>
+    %13 = tt.splat %arg3 : (!tt.ptr<f32, 1>) -> tensor<256x!tt.ptr<f32, 1>, #blocked>
+    %14 = tt.addptr %13, %5 : tensor<256x!tt.ptr<f32, 1>, #blocked>, tensor<256xi32, #blocked>
+    %15 = tt.load %14, %2, %cst_2 {cache = 1 : i32, evict = 1 : i32, isVolatile = false} : tensor<256xf32, #blocked>
+    %16 = tt.splat %arg4 : (!tt.ptr<bf16, 1>) -> tensor<256x!tt.ptr<bf16, 1>, #blocked>
+    %17 = tt.addptr %16, %5 : tensor<256x!tt.ptr<bf16, 1>, #blocked>, tensor<256xi32, #blocked>
+    %18 = tt.load %17, %2, %cst_4 {cache = 1 : i32, evict = 1 : i32, isVolatile = false} : tensor<256xbf16, #blocked>
+    %19 = arith.extf %18 : tensor<256xbf16, #blocked> to tensor<256xf32, #blocked>
+    %20 = tt.addptr %arg5, %0 : !tt.ptr<f32, 1>, i32
+    %21 = tt.splat %20 : (!tt.ptr<f32, 1>) -> tensor<1x!tt.ptr<f32, 1>, #blocked>
+    %22 = tt.load %21 {cache = 1 : i32, evict = 3 : i32, isVolatile = false} : tensor<1xf32, #blocked>
+    %23 = tt.addptr %arg6, %0 : !tt.ptr<f32, 1>, i32
+    %24 = tt.splat %23 : (!tt.ptr<f32, 1>) -> tensor<1x!tt.ptr<f32, 1>, #blocked>
+    %25 = tt.load %24 {cache = 1 : i32, evict = 3 : i32, isVolatile = false} : tensor<1xf32, #blocked>
+    %26 = tt.splat %arg0 : (!tt.ptr<f32, 1>) -> tensor<256x!tt.ptr<f32, 1>, #blocked>
+    %27 = tt.addptr %26, %5 : tensor<256x!tt.ptr<f32, 1>, #blocked>, tensor<256xi32, #blocked>
+    %28 = tt.load %27, %2, %cst_2 {cache = 1 : i32, evict = 1 : i32, isVolatile = false} : tensor<256xf32, #blocked>
+    %29 = arith.mulf %9, %12 : tensor<256xf32, #blocked>
+    %30 = arith.select %2, %29, %cst_2 : tensor<256xi1, #blocked>, tensor<256xf32, #blocked>
+    %31 = "tt.reduce"(%30) <{axis = 0 : i32}> ({
+    ^bb0(%arg10: f32, %arg11: f32):
+      %55 = arith.addf %arg10, %arg11 : f32
+      tt.reduce.return %55 : f32
+    }) : (tensor<256xf32, #blocked>) -> f32
+    %32 = arith.addf %31, %cst_1 : f32
+    %33 = arith.addf %15, %19 : tensor<256xf32, #blocked>
+    %34 = tt.broadcast %22 : (tensor<1xf32, #blocked>) -> tensor<256xf32, #blocked>
+    %35 = arith.subf %33, %34 : tensor<256xf32, #blocked>
+    %36 = tt.broadcast %25 : (tensor<1xf32, #blocked>) -> tensor<256xf32, #blocked>
+    %37 = arith.mulf %35, %36 : tensor<256xf32, #blocked>
+    %38 = arith.mulf %29, %37 : tensor<256xf32, #blocked>
+    %39 = arith.select %2, %38, %cst_2 : tensor<256xi1, #blocked>, tensor<256xf32, #blocked>
+    %40 = "tt.reduce"(%39) <{axis = 0 : i32}> ({
+    ^bb0(%arg10: f32, %arg11: f32):
+      %55 = arith.addf %arg10, %arg11 : f32
+      tt.reduce.return %55 : f32
+    }) : (tensor<256xf32, #blocked>) -> f32
+    %41 = arith.addf %40, %cst_1 : f32
+    %42 = arith.divf %25, %cst_0 : tensor<1xf32, #blocked>
+    %43 = arith.mulf %29, %cst_3 : tensor<256xf32, #blocked>
+    %44 = tt.splat %32 : (f32) -> tensor<256xf32, #blocked>
+    %45 = arith.subf %43, %44 : tensor<256xf32, #blocked>
+    %46 = tt.splat %41 : (f32) -> tensor<256xf32, #blocked>
+    %47 = arith.mulf %37, %46 : tensor<256xf32, #blocked>
+    %48 = arith.subf %45, %47 : tensor<256xf32, #blocked>
+    %49 = tt.broadcast %42 : (tensor<1xf32, #blocked>) -> tensor<256xf32, #blocked>
+    %50 = arith.mulf %49, %48 : tensor<256xf32, #blocked>
+    %51 = arith.addf %28, %50 : tensor<256xf32, #blocked>
+    tt.store %27, %51, %2 {cache = 1 : i32, evict = 1 : i32} : tensor<256xf32, #blocked>
+    %52 = tt.splat %arg7 : (!tt.ptr<bf16, 1>) -> tensor<256x!tt.ptr<bf16, 1>, #blocked>
+    %53 = tt.addptr %52, %5 : tensor<256x!tt.ptr<bf16, 1>, #blocked>, tensor<256xi32, #blocked>
+    %54 = arith.truncf %51 : tensor<256xf32, #blocked> to tensor<256xbf16, #blocked>
+    tt.store %53, %54, %2 {cache = 1 : i32, evict = 1 : i32} : tensor<256xbf16, #blocked>
+    tt.return
+  }
+}

.triton/dump/ab1bd569084d0d03cf386a4687040895/triton_.ttgir

@@ -0,0 +1,100 @@
+#blocked = #triton_gpu.blocked<{sizePerThread = [4], threadsPerWarp = [32], warpsPerCTA = [2], order = [0], CTAsPerCGA = [1], CTASplitNum = [1], CTAOrder = [0]}>
+#blocked1 = #triton_gpu.blocked<{sizePerThread = [1], threadsPerWarp = [32], warpsPerCTA = [2], order = [0], CTAsPerCGA = [1], CTASplitNum = [1], CTAOrder = [0]}>
+module attributes {"triton_gpu.compute-capability" = 89 : i32, "triton_gpu.num-ctas" = 1 : i32, "triton_gpu.num-warps" = 2 : i32, "triton_gpu.threads-per-warp" = 32 : i32} {
+  tt.func public @triton__0d1d2d3d4d5d6d7d8de9de(%arg0: !tt.ptr<i64, 1> {tt.divisibility = 16 : i32}, %arg1: !tt.ptr<f32, 1> {tt.divisibility = 16 : i32}, %arg2: !tt.ptr<f32, 1> {tt.divisibility = 16 : i32}, %arg3: !tt.ptr<bf16, 1> {tt.divisibility = 16 : i32}, %arg4: !tt.ptr<bf16, 1> {tt.divisibility = 16 : i32}, %arg5: !tt.ptr<f32, 1> {tt.divisibility = 16 : i32}, %arg6: !tt.ptr<f32, 1> {tt.divisibility = 16 : i32}, %arg7: !tt.ptr<bf16, 1> {tt.divisibility = 16 : i32}, %arg8: i32 {tt.divisibility = 16 : i32, tt.max_divisibility = 16 : i32}, %arg9: i32 {tt.divisibility = 16 : i32, tt.max_divisibility = 16 : i32}) attributes {noinline = false} {
+    %cst = arith.constant dense<256> : tensor<256xi32, #blocked>
+    %cst_0 = arith.constant dense<0> : tensor<1xi64, #blocked>
+    %cst_1 = arith.constant dense<50257> : tensor<1xi64, #blocked>
+    %cst_2 = arith.constant dense<256> : tensor<1xi64, #blocked>
+    %cst_3 = arith.constant 9.99999974E-6 : f32
+    %cst_4 = arith.constant 2.560000e+02 : f32
+    %cst_5 = arith.constant 0.000000e+00 : f32
+    %c256_i32 = arith.constant 256 : i32
+    %c512_i32 = arith.constant 512 : i32
+    %cst_6 = arith.constant dense<50257> : tensor<1xi64, #blocked1>
+    %cst_7 = arith.constant dense<0> : tensor<1xi64, #blocked1>
+    %cst_8 = arith.constant dense<0.000000e+00> : tensor<256xf32, #blocked>
+    %cst_9 = arith.constant dense<0.000000e+00> : tensor<256xbf16, #blocked>
+    %0 = tt.get_program_id x : i32
+    %1 = tt.make_range {end = 256 : i32, start = 0 : i32} : tensor<256xi32, #blocked>
+    %2 = arith.cmpi slt, %1, %cst : tensor<256xi32, #blocked>
+    %3 = arith.remsi %0, %c512_i32 : i32
+    %4 = tt.addptr %arg0, %0 : !tt.ptr<i64, 1>, i32
+    %5 = tt.splat %4 : (!tt.ptr<i64, 1>) -> tensor<1x!tt.ptr<i64, 1>, #blocked>
+    %6 = tt.splat %4 : (!tt.ptr<i64, 1>) -> tensor<1x!tt.ptr<i64, 1>, #blocked1>
+    %7 = tt.load %5 {cache = 1 : i32, evict = 3 : i32, isVolatile = false} : tensor<1xi64, #blocked>
+    %8 = tt.load %6 {cache = 1 : i32, evict = 3 : i32, isVolatile = false} : tensor<1xi64, #blocked1>
+    %9 = arith.muli %3, %c256_i32 : i32
+    %10 = tt.splat %9 : (i32) -> tensor<256xi32, #blocked>
+    %11 = arith.addi %1, %10 : tensor<256xi32, #blocked>
+    %12 = tt.splat %arg2 : (!tt.ptr<f32, 1>) -> tensor<256x!tt.ptr<f32, 1>, #blocked>
+    %13 = tt.addptr %12, %11 : tensor<256x!tt.ptr<f32, 1>, #blocked>, tensor<256xi32, #blocked>
+    %14 = tt.load %13, %2, %cst_8 {cache = 1 : i32, evict = 3 : i32, isVolatile = false} : tensor<256xf32, #blocked>
+    %15 = arith.muli %0, %c256_i32 : i32
+    %16 = tt.splat %15 : (i32) -> tensor<256xi32, #blocked>
+    %17 = arith.addi %1, %16 : tensor<256xi32, #blocked>
+    %18 = tt.splat %arg3 : (!tt.ptr<bf16, 1>) -> tensor<256x!tt.ptr<bf16, 1>, #blocked>
+    %19 = tt.addptr %18, %17 : tensor<256x!tt.ptr<bf16, 1>, #blocked>, tensor<256xi32, #blocked>
+    %20 = tt.load %19, %2, %cst_9 {cache = 1 : i32, evict = 1 : i32, isVolatile = false} : tensor<256xbf16, #blocked>
+    %21 = arith.extf %20 : tensor<256xbf16, #blocked> to tensor<256xf32, #blocked>
+    %22 = tt.splat %arg4 : (!tt.ptr<bf16, 1>) -> tensor<256x!tt.ptr<bf16, 1>, #blocked>
+    %23 = tt.addptr %22, %17 : tensor<256x!tt.ptr<bf16, 1>, #blocked>, tensor<256xi32, #blocked>
+    %24 = tt.load %23, %2, %cst_9 {cache = 1 : i32, evict = 1 : i32, isVolatile = false} : tensor<256xbf16, #blocked>
+    %25 = arith.extf %24 : tensor<256xbf16, #blocked> to tensor<256xf32, #blocked>
+    %26 = tt.splat %arg5 : (!tt.ptr<f32, 1>) -> tensor<256x!tt.ptr<f32, 1>, #blocked>
+    %27 = tt.addptr %26, %1 : tensor<256x!tt.ptr<f32, 1>, #blocked>, tensor<256xi32, #blocked>
+    %28 = tt.load %27, %2, %cst_8 {cache = 1 : i32, evict = 3 : i32, isVolatile = false} : tensor<256xf32, #blocked>
+    %29 = arith.addi %7, %cst_1 : tensor<1xi64, #blocked>
+    %30 = arith.addi %8, %cst_6 : tensor<1xi64, #blocked1>
+    %31 = arith.cmpi slt, %7, %cst_0 : tensor<1xi64, #blocked>
+    %32 = arith.cmpi slt, %8, %cst_7 : tensor<1xi64, #blocked1>
+    %33 = arith.select %31, %29, %7 : tensor<1xi1, #blocked>, tensor<1xi64, #blocked>
+    %34 = arith.select %32, %30, %8 : tensor<1xi1, #blocked1>, tensor<1xi64, #blocked1>
+    %35 = arith.cmpi sge, %34, %cst_7 : tensor<1xi64, #blocked1>
+    %36 = arith.cmpi slt, %34, %cst_6 : tensor<1xi64, #blocked1>
+    %37 = arith.andi %35, %36 : tensor<1xi1, #blocked1>
+    tt.assert %37, "index out of bounds: 0 <= tmp3 < 50257", "<frozen importlib._bootstrap_external>", "_call_with_frames_removed", 883 : tensor<1xi1, #blocked1>
+    %38 = arith.muli %33, %cst_2 : tensor<1xi64, #blocked>
+    %39 = tt.broadcast %38 : (tensor<1xi64, #blocked>) -> tensor<256xi64, #blocked>
+    %40 = arith.extsi %1 : tensor<256xi32, #blocked> to tensor<256xi64, #blocked>
+    %41 = arith.addi %40, %39 : tensor<256xi64, #blocked>
+    %42 = tt.splat %arg1 : (!tt.ptr<f32, 1>) -> tensor<256x!tt.ptr<f32, 1>, #blocked>
+    %43 = tt.addptr %42, %41 : tensor<256x!tt.ptr<f32, 1>, #blocked>, tensor<256xi64, #blocked>
+    %44 = tt.load %43, %2, %cst_8 {cache = 1 : i32, evict = 1 : i32, isVolatile = false} : tensor<256xf32, #blocked>
+    %45 = arith.addf %44, %14 : tensor<256xf32, #blocked>
+    %46 = arith.addf %45, %21 : tensor<256xf32, #blocked>
+    %47 = arith.addf %46, %25 : tensor<256xf32, #blocked>
+    %48 = arith.select %2, %47, %cst_8 : tensor<256xi1, #blocked>, tensor<256xf32, #blocked>
+    %49 = "tt.reduce"(%48) <{axis = 0 : i32}> ({
+    ^bb0(%arg10: f32, %arg11: f32):
+      %69 = arith.addf %arg10, %arg11 : f32
+      tt.reduce.return %69 : f32
+    }) : (tensor<256xf32, #blocked>) -> f32
+    %50 = arith.addf %49, %cst_5 : f32
+    %51 = arith.divf %50, %cst_4 : f32
+    %52 = tt.splat %51 : (f32) -> tensor<256xf32, #blocked>
+    %53 = arith.subf %47, %52 : tensor<256xf32, #blocked>
+    %54 = arith.mulf %53, %53 : tensor<256xf32, #blocked>
+    %55 = arith.select %2, %54, %cst_8 : tensor<256xi1, #blocked>, tensor<256xf32, #blocked>
+    %56 = "tt.reduce"(%55) <{axis = 0 : i32}> ({
+    ^bb0(%arg10: f32, %arg11: f32):
+      %69 = arith.addf %arg10, %arg11 : f32
+      tt.reduce.return %69 : f32
+    }) : (tensor<256xf32, #blocked>) -> f32
+    %57 = arith.addf %56, %cst_5 : f32
+    %58 = arith.divf %57, %cst_4 : f32
+    %59 = arith.addf %58, %cst_3 : f32
+    %60 = tt.extern_elementwise %59 {libname = "libdevice", libpath = "/usr/local/lib/python3.10/dist-packages/triton/language/../third_party/cuda/lib/libdevice.10.bc", pure = true, symbol = "__nv_rsqrtf"} : (f32) -> f32
+    %61 = tt.splat %60 : (f32) -> tensor<256xf32, #blocked>
+    %62 = arith.mulf %53, %61 : tensor<256xf32, #blocked>
+    %63 = arith.mulf %62, %28 : tensor<256xf32, #blocked>
+    %64 = tt.splat %arg6 : (!tt.ptr<f32, 1>) -> tensor<256x!tt.ptr<f32, 1>, #blocked>
+    %65 = tt.addptr %64, %17 : tensor<256x!tt.ptr<f32, 1>, #blocked>, tensor<256xi32, #blocked>
+    tt.store %65, %47, %2 {cache = 1 : i32, evict = 1 : i32} : tensor<256xf32, #blocked>
+    %66 = tt.splat %arg7 : (!tt.ptr<bf16, 1>) -> tensor<256x!tt.ptr<bf16, 1>, #blocked>
+    %67 = tt.addptr %66, %17 : tensor<256x!tt.ptr<bf16, 1>, #blocked>, tensor<256xi32, #blocked>
+    %68 = arith.truncf %63 : tensor<256xf32, #blocked> to tensor<256xbf16, #blocked>
+    tt.store %67, %68, %2 {cache = 1 : i32, evict = 1 : i32} : tensor<256xbf16, #blocked>
+    tt.return
+  }
+}

.triton/dump/ac249789b41c99e39c165fc12afa9269/triton_.ttgir

@@ -0,0 +1,16 @@
+#blocked = #triton_gpu.blocked<{sizePerThread = [2], threadsPerWarp = [32], warpsPerCTA = [8], order = [0], CTAsPerCGA = [1], CTASplitNum = [1], CTAOrder = [0]}>
+module attributes {"triton_gpu.compute-capability" = 89 : i32, "triton_gpu.num-ctas" = 1 : i32, "triton_gpu.num-warps" = 8 : i32, "triton_gpu.threads-per-warp" = 32 : i32} {
+  tt.func public @triton__0d1de(%arg0: !tt.ptr<f32, 1> {tt.divisibility = 16 : i32}, %arg1: i32 {tt.divisibility = 16 : i32, tt.max_divisibility = 16 : i32}) attributes {noinline = false} {
+    %cst = arith.constant dense<0.000000e+00> : tensor<512xf32, #blocked>
+    %c512_i32 = arith.constant 512 : i32
+    %0 = tt.get_program_id x : i32
+    %1 = arith.muli %0, %c512_i32 : i32
+    %2 = tt.make_range {end = 512 : i32, start = 0 : i32} : tensor<512xi32, #blocked>
+    %3 = tt.splat %1 : (i32) -> tensor<512xi32, #blocked>
+    %4 = arith.addi %3, %2 : tensor<512xi32, #blocked>
+    %5 = tt.splat %arg0 : (!tt.ptr<f32, 1>) -> tensor<512x!tt.ptr<f32, 1>, #blocked>
+    %6 = tt.addptr %5, %4 : tensor<512x!tt.ptr<f32, 1>, #blocked>, tensor<512xi32, #blocked>
+    tt.store %6, %cst {cache = 1 : i32, evict = 1 : i32} : tensor<512xf32, #blocked>
+    tt.return
+  }
+}