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%include "libavutil/x86/x86util.asm" |
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SECTION_RODATA |
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%if ARCH_X86_32 |
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cextern pb_80 |
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wm1010: dw 0, 0xffff, 0, 0xffff |
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d40000: dd 4 << 16, 0 |
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%define C0 23170 |
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%define C1 22725 |
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%define C2 21407 |
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%define C3 19266 |
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%define C4 16383 |
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%define C5 12873 |
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%define C6 8867 |
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%define C7 4520 |
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%define ROW_SHIFT 11 |
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%define COL_SHIFT 20 |
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coeffs: |
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dw 1 << (ROW_SHIFT - 1), 0 |
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dw 1 << (ROW_SHIFT - 1), 0 |
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dw 1 << (ROW_SHIFT - 1), 1 |
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dw 1 << (ROW_SHIFT - 1), 0 |
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dw C4, C4, C4, C4 |
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dw C4, -C4, C4, -C4 |
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dw C2, C6, C2, C6 |
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dw C6, -C2, C6, -C2 |
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dw C1, C3, C1, C3 |
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dw C5, C7, C5, C7 |
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dw C3, -C7, C3, -C7 |
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dw -C1, -C5, -C1, -C5 |
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dw C5, -C1, C5, -C1 |
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dw C7, C3, C7, C3 |
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dw C7, -C5, C7, -C5 |
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dw C3, -C1, C3, -C1 |
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SECTION .text |
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%macro DC_COND_IDCT 7 |
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movq mm0, [blockq + %1] |
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movq mm1, [blockq + %2] |
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movq mm2, [blockq + %3] |
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movq mm3, [blockq + %4] |
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movq mm4, [wm1010] |
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pand mm4, mm0 |
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por mm4, mm1 |
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por mm4, mm2 |
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por mm4, mm3 |
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packssdw mm4, mm4 |
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movd t0d, mm4 |
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or t0d, t0d |
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jz %%1 |
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movq mm4, [coeffs + 16] |
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pmaddwd mm4, mm0 |
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movq mm5, [coeffs + 24] |
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pmaddwd mm0, mm5 |
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movq mm5, [coeffs + 32] |
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pmaddwd mm5, mm1 |
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movq mm6, [coeffs + 40] |
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pmaddwd mm1, mm6 |
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movq mm7, [coeffs + 48] |
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pmaddwd mm7, mm2 |
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paddd mm4, [coeffs + 8] |
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movq mm6, mm4 |
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paddd mm4, mm5 |
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psubd mm6, mm5 |
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movq mm5, [coeffs + 56] |
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pmaddwd mm5, mm3 |
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paddd mm0, [coeffs + 8] |
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paddd mm1, mm0 |
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paddd mm0, mm0 |
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psubd mm0, mm1 |
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pmaddwd mm2, [coeffs + 64] |
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paddd mm7, mm5 |
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movq mm5, [coeffs + 72] |
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pmaddwd mm5, mm3 |
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paddd mm7, mm4 |
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paddd mm4, mm4 |
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psubd mm4, mm7 |
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paddd mm5, mm2 |
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psrad mm7, %7 |
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psrad mm4, %7 |
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movq mm2, mm1 |
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paddd mm1, mm5 |
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psubd mm2, mm5 |
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psrad mm1, %7 |
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psrad mm2, %7 |
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packssdw mm7, mm1 |
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packssdw mm2, mm4 |
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movq [%5], mm7 |
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movq mm1, [blockq + %3] |
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movq mm4, [coeffs + 80] |
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movq [24 + %5], mm2 |
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pmaddwd mm4, mm1 |
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movq mm7, [coeffs + 88] |
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pmaddwd mm1, [coeffs + 96] |
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pmaddwd mm7, mm3 |
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movq mm2, mm0 |
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pmaddwd mm3, [coeffs + 104] |
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paddd mm4, mm7 |
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paddd mm2, mm4 |
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psubd mm0, mm4 |
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psrad mm2, %7 |
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psrad mm0, %7 |
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movq mm4, mm6 |
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paddd mm3, mm1 |
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paddd mm6, mm3 |
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psubd mm4, mm3 |
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psrad mm6, %7 |
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packssdw mm2, mm6 |
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movq [8 + %5], mm2 |
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psrad mm4, %7 |
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packssdw mm4, mm0 |
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movq [16 + %5], mm4 |
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jmp %%2 |
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%%1: |
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pslld mm0, 16 |
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paddd mm0, [d40000] |
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psrad mm0, 13 |
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packssdw mm0, mm0 |
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movq [%5], mm0 |
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movq [8 + %5], mm0 |
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movq [16 + %5], mm0 |
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movq [24 + %5], mm0 |
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%%2: |
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%endmacro |
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%macro Z_COND_IDCT 8 |
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movq mm0, [blockq + %1] |
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movq mm1, [blockq + %2] |
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movq mm2, [blockq + %3] |
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movq mm3, [blockq + %4] |
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movq mm4, mm0 |
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por mm4, mm1 |
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por mm4, mm2 |
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por mm4, mm3 |
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packssdw mm4, mm4 |
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movd t0d, mm4 |
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or t0d, t0d |
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jz %8 |
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movq mm4, [coeffs + 16] |
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pmaddwd mm4, mm0 |
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movq mm5, [coeffs + 24] |
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pmaddwd mm0, mm5 |
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movq mm5, [coeffs + 32] |
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pmaddwd mm5, mm1 |
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movq mm6, [coeffs + 40] |
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pmaddwd mm1, mm6 |
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movq mm7, [coeffs + 48] |
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pmaddwd mm7, mm2 |
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paddd mm4, [coeffs] |
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movq mm6, mm4 |
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paddd mm4, mm5 |
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psubd mm6, mm5 |
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movq mm5, [coeffs + 56] |
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pmaddwd mm5, mm3 |
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paddd mm0, [coeffs] |
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paddd mm1, mm0 |
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paddd mm0, mm0 |
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psubd mm0, mm1 |
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pmaddwd mm2, [coeffs + 64] |
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paddd mm7, mm5 |
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movq mm5, [coeffs + 72] |
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pmaddwd mm5, mm3 |
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paddd mm7, mm4 |
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paddd mm4, mm4 |
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psubd mm4, mm7 |
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paddd mm5, mm2 |
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psrad mm7, %7 |
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psrad mm4, %7 |
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movq mm2, mm1 |
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paddd mm1, mm5 |
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psubd mm2, mm5 |
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psrad mm1, %7 |
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psrad mm2, %7 |
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packssdw mm7, mm1 |
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packssdw mm2, mm4 |
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movq [%5], mm7 |
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movq mm1, [blockq + %3] |
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movq mm4, [coeffs + 80] |
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movq [24 + %5], mm2 |
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pmaddwd mm4, mm1 |
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movq mm7, [coeffs + 88] |
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pmaddwd mm1, [coeffs + 96] |
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pmaddwd mm7, mm3 |
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movq mm2, mm0 |
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pmaddwd mm3, [coeffs + 104] |
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paddd mm4, mm7 |
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paddd mm2, mm4 |
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psubd mm0, mm4 |
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psrad mm2, %7 |
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psrad mm0, %7 |
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movq mm4, mm6 |
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paddd mm3, mm1 |
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paddd mm6, mm3 |
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psubd mm4, mm3 |
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psrad mm6, %7 |
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packssdw mm2, mm6 |
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movq [8 + %5], mm2 |
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psrad mm4, %7 |
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packssdw mm4, mm0 |
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movq [16 + %5], mm4 |
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%endmacro |
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%macro IDCT1 6 |
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movq mm0, %1 |
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movq mm1, %2 |
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movq mm2, %3 |
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movq mm3, %4 |
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movq mm4, [coeffs + 16] |
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pmaddwd mm4, mm0 |
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movq mm5, [coeffs + 24] |
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pmaddwd mm0, mm5 |
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movq mm5, [coeffs + 32] |
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pmaddwd mm5, mm1 |
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movq mm6, [coeffs + 40] |
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pmaddwd mm1, mm6 |
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movq mm6, mm4 |
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movq mm7, [coeffs + 48] |
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pmaddwd mm7, mm2 |
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paddd mm4, mm5 |
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psubd mm6, mm5 |
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movq mm5, mm0 |
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paddd mm0, mm1 |
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psubd mm5, mm1 |
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movq mm1, [coeffs + 56] |
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pmaddwd mm1, mm3 |
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pmaddwd mm2, [coeffs + 64] |
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paddd mm7, mm1 |
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movq mm1, [coeffs + 72] |
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pmaddwd mm1, mm3 |
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paddd mm7, mm4 |
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paddd mm4, mm4 |
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psubd mm4, mm7 |
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paddd mm1, mm2 |
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psrad mm7, %6 |
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psrad mm4, %6 |
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movq mm2, mm0 |
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paddd mm0, mm1 |
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psubd mm2, mm1 |
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psrad mm0, %6 |
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psrad mm2, %6 |
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packssdw mm7, mm7 |
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movd [%5], mm7 |
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packssdw mm0, mm0 |
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movd [16 + %5], mm0 |
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packssdw mm2, mm2 |
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movd [96 + %5], mm2 |
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packssdw mm4, mm4 |
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movd [112 + %5], mm4 |
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movq mm0, %3 |
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movq mm4, [coeffs + 80] |
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pmaddwd mm4, mm0 |
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movq mm7, [coeffs + 88] |
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pmaddwd mm0, [coeffs + 96] |
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pmaddwd mm7, mm3 |
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movq mm2, mm5 |
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pmaddwd mm3, [coeffs + 104] |
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paddd mm4, mm7 |
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paddd mm2, mm4 |
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psubd mm5, mm4 |
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psrad mm2, %6 |
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psrad mm5, %6 |
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movq mm4, mm6 |
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paddd mm3, mm0 |
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paddd mm6, mm3 |
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psubd mm4, mm3 |
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psrad mm6, %6 |
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psrad mm4, %6 |
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packssdw mm2, mm2 |
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packssdw mm6, mm6 |
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movd [32 + %5], mm2 |
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packssdw mm4, mm4 |
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packssdw mm5, mm5 |
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movd [48 + %5], mm6 |
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movd [64 + %5], mm4 |
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movd [80 + %5], mm5 |
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%endmacro |
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%macro IDCT2 6 |
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movq mm0, %1 |
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movq mm1, %2 |
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movq mm3, %4 |
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movq mm4, [coeffs + 16] |
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pmaddwd mm4, mm0 |
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movq mm5, [coeffs + 24] |
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pmaddwd mm0, mm5 |
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movq mm5, [coeffs + 32] |
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pmaddwd mm5, mm1 |
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movq mm6, [coeffs + 40] |
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pmaddwd mm1, mm6 |
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movq mm6, mm4 |
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paddd mm4, mm5 |
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psubd mm6, mm5 |
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movq mm5, mm0 |
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paddd mm0, mm1 |
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psubd mm5, mm1 |
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movq mm1, [coeffs + 56] |
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pmaddwd mm1, mm3 |
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movq mm7, [coeffs + 72] |
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pmaddwd mm7, mm3 |
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paddd mm1, mm4 |
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paddd mm4, mm4 |
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psubd mm4, mm1 |
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psrad mm1, %6 |
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psrad mm4, %6 |
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movq mm2, mm0 |
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paddd mm0, mm7 |
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psubd mm2, mm7 |
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psrad mm0, %6 |
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psrad mm2, %6 |
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packssdw mm1, mm1 |
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movd [%5], mm1 |
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packssdw mm0, mm0 |
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movd [16 + %5], mm0 |
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packssdw mm2, mm2 |
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movd [96 + %5], mm2 |
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packssdw mm4, mm4 |
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movd [112 + %5], mm4 |
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movq mm1, [coeffs + 88] |
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pmaddwd mm1, mm3 |
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movq mm2, mm5 |
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pmaddwd mm3, [coeffs + 104] |
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paddd mm2, mm1 |
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psubd mm5, mm1 |
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psrad mm2, %6 |
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psrad mm5, %6 |
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movq mm1, mm6 |
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paddd mm6, mm3 |
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psubd mm1, mm3 |
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psrad mm6, %6 |
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psrad mm1, %6 |
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packssdw mm2, mm2 |
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packssdw mm6, mm6 |
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movd [32 + %5], mm2 |
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packssdw mm1, mm1 |
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packssdw mm5, mm5 |
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movd [48 + %5], mm6 |
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movd [64 + %5], mm1 |
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movd [80 + %5], mm5 |
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%endmacro |
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%macro IDCT3 6 |
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movq mm0, %1 |
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movq mm3, %4 |
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movq mm4, [coeffs + 16] |
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pmaddwd mm4, mm0 |
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movq mm5, [coeffs + 24] |
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pmaddwd mm0, mm5 |
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movq mm6, mm4 |
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movq mm5, mm0 |
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movq mm1, [coeffs + 56] |
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pmaddwd mm1, mm3 |
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movq mm7, [coeffs + 72] |
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pmaddwd mm7, mm3 |
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paddd mm1, mm4 |
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paddd mm4, mm4 |
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psubd mm4, mm1 |
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psrad mm1, %6 |
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psrad mm4, %6 |
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movq mm2, mm0 |
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paddd mm0, mm7 |
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psubd mm2, mm7 |
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psrad mm0, %6 |
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psrad mm2, %6 |
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packssdw mm1, mm1 |
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movd [%5], mm1 |
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packssdw mm0, mm0 |
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movd [16 + %5], mm0 |
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packssdw mm2, mm2 |
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movd [96 + %5], mm2 |
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packssdw mm4, mm4 |
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movd [112 + %5], mm4 |
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movq mm1, [coeffs + 88] |
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pmaddwd mm1, mm3 |
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movq mm2, mm5 |
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pmaddwd mm3, [coeffs + 104] |
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paddd mm2, mm1 |
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psubd mm5, mm1 |
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psrad mm2, %6 |
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psrad mm5, %6 |
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movq mm1, mm6 |
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paddd mm6, mm3 |
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psubd mm1, mm3 |
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psrad mm6, %6 |
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psrad mm1, %6 |
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packssdw mm2, mm2 |
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packssdw mm6, mm6 |
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movd [32 + %5], mm2 |
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packssdw mm1, mm1 |
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packssdw mm5, mm5 |
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movd [48 + %5], mm6 |
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movd [64 + %5], mm1 |
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movd [80 + %5], mm5 |
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%endmacro |
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%macro IDCT4 6 |
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movq mm0, %1 |
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movq mm2, %3 |
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movq mm3, %4 |
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movq mm4, [coeffs + 16] |
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pmaddwd mm4, mm0 |
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movq mm5, [coeffs + 24] |
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pmaddwd mm0, mm5 |
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movq mm6, mm4 |
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movq mm7, [coeffs + 48] |
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pmaddwd mm7, mm2 |
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movq mm5, mm0 |
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movq mm1, [coeffs + 56] |
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pmaddwd mm1, mm3 |
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pmaddwd mm2, [coeffs + 64] |
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paddd mm7, mm1 |
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movq mm1, [coeffs + 72] |
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pmaddwd mm1, mm3 |
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paddd mm7, mm4 |
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paddd mm4, mm4 |
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psubd mm4, mm7 |
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paddd mm1, mm2 |
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psrad mm7, %6 |
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psrad mm4, %6 |
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movq mm2, mm0 |
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paddd mm0, mm1 |
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psubd mm2, mm1 |
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psrad mm0, %6 |
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psrad mm2, %6 |
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packssdw mm7, mm7 |
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movd [%5], mm7 |
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packssdw mm0, mm0 |
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movd [16 + %5], mm0 |
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packssdw mm2, mm2 |
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movd [96 + %5], mm2 |
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packssdw mm4, mm4 |
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movd [112 + %5], mm4 |
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movq mm0, %3 |
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movq mm4, [coeffs + 80] |
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pmaddwd mm4, mm0 |
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movq mm7, [coeffs + 88] |
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pmaddwd mm0, [coeffs + 96] |
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pmaddwd mm7, mm3 |
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movq mm2, mm5 |
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pmaddwd mm3, [coeffs + 104] |
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paddd mm4, mm7 |
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paddd mm2, mm4 |
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psubd mm5, mm4 |
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psrad mm2, %6 |
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psrad mm5, %6 |
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movq mm4, mm6 |
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paddd mm3, mm0 |
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paddd mm6, mm3 |
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psubd mm4, mm3 |
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psrad mm6, %6 |
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psrad mm4, %6 |
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packssdw mm2, mm2 |
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packssdw mm6, mm6 |
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movd [32 + %5], mm2 |
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packssdw mm4, mm4 |
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packssdw mm5, mm5 |
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movd [48 + %5], mm6 |
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movd [64 + %5], mm4 |
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movd [80 + %5], mm5 |
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%endmacro |
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%macro IDCT5 6 |
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movq mm0, %1 |
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movq mm2, %3 |
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movq mm4, [coeffs + 16] |
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pmaddwd mm4, mm0 |
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movq mm5, [coeffs + 24] |
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pmaddwd mm0, mm5 |
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movq mm6, mm4 |
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movq mm7, [coeffs + 48] |
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pmaddwd mm7, mm2 |
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movq mm5, mm0 |
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movq mm3, [coeffs + 64] |
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pmaddwd mm3, mm2 |
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paddd mm7, mm4 |
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paddd mm4, mm4 |
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psubd mm4, mm7 |
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psrad mm7, %6 |
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psrad mm4, %6 |
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movq mm1, mm0 |
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paddd mm0, mm3 |
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psubd mm1, mm3 |
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psrad mm0, %6 |
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psrad mm1, %6 |
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packssdw mm7, mm7 |
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movd [%5], mm7 |
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packssdw mm0, mm0 |
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movd [16 + %5], mm0 |
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packssdw mm1, mm1 |
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movd [96 + %5], mm1 |
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packssdw mm4, mm4 |
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movd [112 + %5], mm4 |
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movq mm4, [coeffs + 80] |
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pmaddwd mm4, mm2 |
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pmaddwd mm2, [coeffs + 96] |
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movq mm1, mm5 |
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paddd mm1, mm4 |
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psubd mm5, mm4 |
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psrad mm1, %6 |
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psrad mm5, %6 |
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movq mm4, mm6 |
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paddd mm6, mm2 |
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psubd mm4, mm2 |
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psrad mm6, %6 |
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psrad mm4, %6 |
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packssdw mm1, mm1 |
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packssdw mm6, mm6 |
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movd [32 + %5], mm1 |
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packssdw mm4, mm4 |
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packssdw mm5, mm5 |
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movd [48 + %5], mm6 |
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movd [64 + %5], mm4 |
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movd [80 + %5], mm5 |
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%endmacro |
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%macro IDCT6 6 |
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movq mm0, [%1] |
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movq mm1, [%2] |
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movq mm4, [coeffs + 16] |
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pmaddwd mm4, mm0 |
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movq mm5, [coeffs + 24] |
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pmaddwd mm0, mm5 |
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movq mm5, [coeffs + 32] |
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pmaddwd mm5, mm1 |
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movq mm6, [coeffs + 40] |
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pmaddwd mm1, mm6 |
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movq mm6, mm4 |
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paddd mm4, mm5 |
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psubd mm6, mm5 |
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movq mm5, mm0 |
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paddd mm0, mm1 |
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psubd mm5, mm1 |
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movq mm2, [8 + %1] |
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movq mm3, [8 + %2] |
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movq mm1, [coeffs + 16] |
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pmaddwd mm1, mm2 |
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movq mm7, [coeffs + 24] |
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pmaddwd mm2, mm7 |
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movq mm7, [coeffs + 32] |
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pmaddwd mm7, mm3 |
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pmaddwd mm3, [coeffs + 40] |
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paddd mm7, mm1 |
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paddd mm1, mm1 |
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psubd mm1, mm7 |
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paddd mm3, mm2 |
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paddd mm2, mm2 |
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psubd mm2, mm3 |
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psrad mm4, %6 |
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psrad mm7, %6 |
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psrad mm3, %6 |
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packssdw mm4, mm7 |
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movq [%5], mm4 |
|
psrad mm0, %6 |
|
packssdw mm0, mm3 |
|
movq [16 + %5], mm0 |
|
movq [96 + %5], mm0 |
|
movq [112 + %5], mm4 |
|
psrad mm5, %6 |
|
psrad mm6, %6 |
|
psrad mm2, %6 |
|
packssdw mm5, mm2 |
|
movq [32 + %5], mm5 |
|
psrad mm1, %6 |
|
packssdw mm6, mm1 |
|
movq [48 + %5], mm6 |
|
movq [64 + %5], mm6 |
|
movq [80 + %5], mm5 |
|
%endmacro |
|
|
|
%macro IDCT7 6 |
|
movq mm0, %1 |
|
movq mm1, %2 |
|
movq mm2, %3 |
|
movq mm4, [coeffs + 16] |
|
pmaddwd mm4, mm0 |
|
movq mm5, [coeffs + 24] |
|
pmaddwd mm0, mm5 |
|
movq mm5, [coeffs + 32] |
|
pmaddwd mm5, mm1 |
|
movq mm6, [coeffs + 40] |
|
pmaddwd mm1, mm6 |
|
movq mm6, mm4 |
|
movq mm7, [coeffs + 48] |
|
pmaddwd mm7, mm2 |
|
paddd mm4, mm5 |
|
psubd mm6, mm5 |
|
movq mm5, mm0 |
|
paddd mm0, mm1 |
|
psubd mm5, mm1 |
|
movq mm1, [coeffs + 64] |
|
pmaddwd mm1, mm2 |
|
paddd mm7, mm4 |
|
paddd mm4, mm4 |
|
psubd mm4, mm7 |
|
psrad mm7, %6 |
|
psrad mm4, %6 |
|
movq mm3, mm0 |
|
paddd mm0, mm1 |
|
psubd mm3, mm1 |
|
psrad mm0, %6 |
|
psrad mm3, %6 |
|
packssdw mm7, mm7 |
|
movd [%5], mm7 |
|
packssdw mm0, mm0 |
|
movd [16 + %5], mm0 |
|
packssdw mm3, mm3 |
|
movd [96 + %5], mm3 |
|
packssdw mm4, mm4 |
|
movd [112 + %5], mm4 |
|
movq mm4, [coeffs + 80] |
|
pmaddwd mm4, mm2 |
|
pmaddwd mm2, [coeffs + 96] |
|
movq mm3, mm5 |
|
paddd mm3, mm4 |
|
psubd mm5, mm4 |
|
psrad mm3, %6 |
|
psrad mm5, %6 |
|
movq mm4, mm6 |
|
paddd mm6, mm2 |
|
psubd mm4, mm2 |
|
psrad mm6, %6 |
|
packssdw mm3, mm3 |
|
movd [32 + %5], mm3 |
|
psrad mm4, %6 |
|
packssdw mm6, mm6 |
|
movd [48 + %5], mm6 |
|
packssdw mm4, mm4 |
|
packssdw mm5, mm5 |
|
movd [64 + %5], mm4 |
|
movd [80 + %5], mm5 |
|
%endmacro |
|
|
|
%macro IDCT8 6 |
|
movq mm0, [%1] |
|
movq mm4, [coeffs + 16] |
|
pmaddwd mm4, mm0 |
|
movq mm5, [coeffs + 24] |
|
pmaddwd mm0, mm5 |
|
psrad mm4, %6 |
|
psrad mm0, %6 |
|
movq mm2, [8 + %1] |
|
movq mm1, [coeffs + 16] |
|
pmaddwd mm1, mm2 |
|
movq mm7, [coeffs + 24] |
|
pmaddwd mm2, mm7 |
|
movq mm7, [coeffs + 32] |
|
psrad mm1, %6 |
|
packssdw mm4, mm1 |
|
movq [%5], mm4 |
|
psrad mm2, %6 |
|
packssdw mm0, mm2 |
|
movq [16 + %5], mm0 |
|
movq [96 + %5], mm0 |
|
movq [112 + %5], mm4 |
|
movq [32 + %5], mm0 |
|
movq [48 + %5], mm4 |
|
movq [64 + %5], mm4 |
|
movq [80 + %5], mm0 |
|
%endmacro |
|
|
|
%macro IDCT 0 |
|
DC_COND_IDCT 0, 8, 16, 24, rsp + 0, null, 11 |
|
Z_COND_IDCT 32, 40, 48, 56, rsp + 32, null, 11, %%4 |
|
Z_COND_IDCT 64, 72, 80, 88, rsp + 64, null, 11, %%2 |
|
Z_COND_IDCT 96, 104, 112, 120, rsp + 96, null, 11, %%1 |
|
|
|
IDCT1 [rsp + 0], [rsp + 64], [rsp + 32], [rsp + 96], blockq + 0, 20 |
|
IDCT1 [rsp + 8], [rsp + 72], [rsp + 40], [rsp + 104], blockq + 4, 20 |
|
IDCT1 [rsp + 16], [rsp + 80], [rsp + 48], [rsp + 112], blockq + 8, 20 |
|
IDCT1 [rsp + 24], [rsp + 88], [rsp + 56], [rsp + 120], blockq + 12, 20 |
|
jmp %%9 |
|
|
|
ALIGN 16 |
|
%%4: |
|
Z_COND_IDCT 64, 72, 80, 88, rsp + 64, null, 11, %%6 |
|
Z_COND_IDCT 96, 104, 112, 120, rsp + 96, null, 11, %%5 |
|
|
|
IDCT2 [rsp + 0], [rsp + 64], [rsp + 32], [rsp + 96], blockq + 0, 20 |
|
IDCT2 [rsp + 8], [rsp + 72], [rsp + 40], [rsp + 104], blockq + 4, 20 |
|
IDCT2 [rsp + 16], [rsp + 80], [rsp + 48], [rsp + 112], blockq + 8, 20 |
|
IDCT2 [rsp + 24], [rsp + 88], [rsp + 56], [rsp + 120], blockq + 12, 20 |
|
jmp %%9 |
|
|
|
ALIGN 16 |
|
%%6: |
|
Z_COND_IDCT 96, 104, 112, 120, rsp + 96, null, 11, %%7 |
|
|
|
IDCT3 [rsp + 0], [rsp + 64], [rsp + 32], [rsp + 96], blockq + 0, 20 |
|
IDCT3 [rsp + 8], [rsp + 72], [rsp + 40], [rsp + 104], blockq + 4, 20 |
|
IDCT3 [rsp + 16], [rsp + 80], [rsp + 48], [rsp + 112], blockq + 8, 20 |
|
IDCT3 [rsp + 24], [rsp + 88], [rsp + 56], [rsp + 120], blockq + 12, 20 |
|
jmp %%9 |
|
|
|
ALIGN 16 |
|
%%2: |
|
Z_COND_IDCT 96, 104, 112, 120, rsp + 96, null, 11, %%3 |
|
|
|
IDCT4 [rsp + 0], [rsp + 64], [rsp + 32], [rsp + 96], blockq + 0, 20 |
|
IDCT4 [rsp + 8], [rsp + 72], [rsp + 40], [rsp + 104], blockq + 4, 20 |
|
IDCT4 [rsp + 16], [rsp + 80], [rsp + 48], [rsp + 112], blockq + 8, 20 |
|
IDCT4 [rsp + 24], [rsp + 88], [rsp + 56], [rsp + 120], blockq + 12, 20 |
|
jmp %%9 |
|
|
|
ALIGN 16 |
|
%%3: |
|
|
|
IDCT5 [rsp + 0], [rsp + 64], [rsp + 32], [rsp + 96], blockq + 0, 20 |
|
IDCT5 [rsp + 8], [rsp + 72], [rsp + 40], [rsp + 104], blockq + 4, 20 |
|
IDCT5 [rsp + 16], [rsp + 80], [rsp + 48], [rsp + 112], blockq + 8, 20 |
|
IDCT5 [rsp + 24], [rsp + 88], [rsp + 56], [rsp + 120], blockq + 12, 20 |
|
jmp %%9 |
|
|
|
ALIGN 16 |
|
%%5: |
|
|
|
IDCT6 rsp + 0, rsp + 64, rsp + 32, rsp + 96, blockq + 0, 20 |
|
IDCT6 rsp + 16, rsp + 80, rsp + 48, rsp + 112, blockq + 8, 20 |
|
jmp %%9 |
|
|
|
ALIGN 16 |
|
%%1: |
|
|
|
IDCT7 [rsp + 0], [rsp + 64], [rsp + 32], [rsp + 96], blockq + 0, 20 |
|
IDCT7 [rsp + 8], [rsp + 72], [rsp + 40], [rsp + 104], blockq + 4, 20 |
|
IDCT7 [rsp + 16], [rsp + 80], [rsp + 48], [rsp + 112], blockq + 8, 20 |
|
IDCT7 [rsp + 24], [rsp + 88], [rsp + 56], [rsp + 120], blockq + 12, 20 |
|
jmp %%9 |
|
|
|
ALIGN 16 |
|
%%7: |
|
|
|
IDCT8 rsp + 0, rsp + 64, rsp + 32, rsp + 96, blockq + 0, 20 |
|
IDCT8 rsp + 16, rsp + 80, rsp + 48, rsp + 112, blockq + 8, 20 |
|
|
|
%%9: |
|
%endmacro |
|
|
|
%macro PUT_PIXELS_CLAMPED_HALF 1 |
|
mova m0, [blockq+mmsize*0+%1] |
|
mova m1, [blockq+mmsize*2+%1] |
|
%if mmsize == 8 |
|
mova m2, [blockq+mmsize*4+%1] |
|
mova m3, [blockq+mmsize*6+%1] |
|
%endif |
|
packuswb m0, [blockq+mmsize*1+%1] |
|
packuswb m1, [blockq+mmsize*3+%1] |
|
%if mmsize == 8 |
|
packuswb m2, [blockq+mmsize*5+%1] |
|
packuswb m3, [blockq+mmsize*7+%1] |
|
movq [pixelsq], m0 |
|
movq [lsizeq+pixelsq], m1 |
|
movq [2*lsizeq+pixelsq], m2 |
|
movq [lsize3q+pixelsq], m3 |
|
%else |
|
movq [pixelsq], m0 |
|
movhps [lsizeq+pixelsq], m0 |
|
movq [2*lsizeq+pixelsq], m1 |
|
movhps [lsize3q+pixelsq], m1 |
|
%endif |
|
%endmacro |
|
|
|
%macro ADD_PIXELS_CLAMPED 1 |
|
mova m0, [blockq+mmsize*0+%1] |
|
mova m1, [blockq+mmsize*1+%1] |
|
%if mmsize == 8 |
|
mova m5, [blockq+mmsize*2+%1] |
|
mova m6, [blockq+mmsize*3+%1] |
|
%endif |
|
movq m2, [pixelsq] |
|
movq m3, [pixelsq+lsizeq] |
|
%if mmsize == 8 |
|
mova m7, m2 |
|
punpcklbw m2, m4 |
|
punpckhbw m7, m4 |
|
paddsw m0, m2 |
|
paddsw m1, m7 |
|
mova m7, m3 |
|
punpcklbw m3, m4 |
|
punpckhbw m7, m4 |
|
paddsw m5, m3 |
|
paddsw m6, m7 |
|
%else |
|
punpcklbw m2, m4 |
|
punpcklbw m3, m4 |
|
paddsw m0, m2 |
|
paddsw m1, m3 |
|
%endif |
|
packuswb m0, m1 |
|
%if mmsize == 8 |
|
packuswb m5, m6 |
|
movq [pixelsq], m0 |
|
movq [pixelsq+lsizeq], m5 |
|
%else |
|
movq [pixelsq], m0 |
|
movhps [pixelsq+lsizeq], m0 |
|
%endif |
|
%endmacro |
|
|
|
INIT_MMX mmx |
|
|
|
cglobal simple_idct, 1, 2, 8, 128, block, t0 |
|
IDCT |
|
RET |
|
|
|
INIT_XMM sse2 |
|
|
|
cglobal simple_idct_put, 3, 5, 8, 128, pixels, lsize, block, lsize3, t0 |
|
IDCT |
|
lea lsize3q, [lsizeq*3] |
|
PUT_PIXELS_CLAMPED_HALF 0 |
|
lea pixelsq, [pixelsq+lsizeq*4] |
|
PUT_PIXELS_CLAMPED_HALF 64 |
|
RET |
|
|
|
cglobal simple_idct_add, 3, 4, 8, 128, pixels, lsize, block, t0 |
|
IDCT |
|
pxor m4, m4 |
|
ADD_PIXELS_CLAMPED 0 |
|
lea pixelsq, [pixelsq+lsizeq*2] |
|
ADD_PIXELS_CLAMPED 32 |
|
lea pixelsq, [pixelsq+lsizeq*2] |
|
ADD_PIXELS_CLAMPED 64 |
|
lea pixelsq, [pixelsq+lsizeq*2] |
|
ADD_PIXELS_CLAMPED 96 |
|
RET |
|
%endif |
|
|