AWfaw commited on
Commit
d5328f2
·
1 Parent(s): f7957a4

description updates

Browse files
Files changed (1) hide show
  1. README.md +79 -1
README.md CHANGED
@@ -12,4 +12,82 @@ task_categories:
12
  - text-generation
13
  task_ids:
14
  - language-modeling
15
- ---
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
12
  - text-generation
13
  task_ids:
14
  - language-modeling
15
+ ---
16
+ # Dataset Card for Dataset Name
17
+
18
+ ## Dataset Description
19
+ The GitHub Code dataset consists of 100M code files from GitHub in VHDL programming language with extensions totaling in 1.69 GB of data. The dataset was created from the public GitHub dataset on Google BiqQuery at Anhalt University of Applied Sciences.
20
+ - **Homepage:**
21
+ - https://www.hs-anhalt.de/hochschule-anhalt/emw/uebersicht.html
22
+ - **Point of Contact:**
23
24
+
25
+ ## Considerations for Using the Data
26
+
27
+ The dataset consists of source code from a wide range of repositories. As such they can potentially include harmful or biased code as well as sensitive information like passwords or usernames.
28
+
29
+ ### Languages
30
+
31
+ ```python
32
+ {
33
+ "VHDL": [".vhd", "vhd"],
34
+ }
35
+ ```
36
+
37
+ ## Dataset Structure
38
+
39
+ ### Data Instances
40
+
41
+ ```python
42
+ {
43
+ "repo_name": "sebgod/linguist",
44
+ "path": "samples/VHDL/foo.vhd",
45
+ "copies": "91",
46
+ "size": "217",
47
+ "content": "-- VHDL example file\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity inverter is\n\tport(a : in std_logic;\n\t b : out std_logic);\nend entity;\n\narchitecture rtl of inverter is\nbegin\n\tb \u003c\u003d not a;\nend architecture;\n",
48
+ "license": "mit"
49
+ }, {
50
+ "repo_name": "cybernet14/linguist",
51
+ "path": "samples/VHDL/foo.vhd",
52
+ "copies": "91",
53
+ "size": "217",
54
+ "content": "-- VHDL example file\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity inverter is\n\tport(a : in std_logic;\n\t b : out std_logic);\nend entity;\n\narchitecture rtl of inverter is\nbegin\n\tb \u003c\u003d not a;\nend architecture;\n",
55
+ "license": "mit"
56
+ }
57
+ ```
58
+
59
+ ### Data Fields
60
+
61
+ |Field|Type|Description|
62
+ |---|---|---|
63
+ |code|string|content of source file|
64
+ |repo_name|string|name of the GitHub repository|
65
+ |path|string|path of file in GitHub repository|
66
+ |language|string|programming language as inferred by extension|
67
+ |license|string|license of GitHub repository|
68
+ |size|int|size of source file in bytes|
69
+
70
+ ### Data Splits
71
+
72
+ The dataset contains a train split only
73
+
74
+ ### Licensing Information
75
+
76
+ ```python
77
+ [
78
+ 'agpl-3.0',
79
+ 'artistic-2.0',
80
+ 'mpl-2.0',
81
+ 'cc0-1.0',
82
+ 'mit',
83
+ 'gpl-2.0',
84
+ 'gpl-3.0',
85
+ 'lgpl-3.0',
86
+ 'apache-2.0',
87
+ 'bsd-3-clause'
88
+ ]
89
+ ```
90
+
91
+ ### v1.0
92
+ - Initial release of dataset
93
+ - The query was executed on 21.07.2023, 00:02:38 UTC+2