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asicguy/gplgpu | hdl/sim_lib/cycloneiii_atoms.vhd | 1 | 361479 | -- Copyright (C) 1991-2011 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
-- Quartus II 11.0 Build 157 04/27/2011
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
package cycloneiii_atom_pack is
function str_to_bin (lut_mask : string ) return std_logic_vector;
function product(list : std_logic_vector) return std_logic ;
function alt_conv_integer(arg : in std_logic_vector) return integer;
-- default generic values
CONSTANT DefWireDelay : VitalDelayType01 := (0 ns, 0 ns);
CONSTANT DefPropDelay01 : VitalDelayType01 := (0 ns, 0 ns);
CONSTANT DefPropDelay01Z : VitalDelayType01Z := (OTHERS => 0 ns);
CONSTANT DefSetupHoldCnst : TIME := 0 ns;
CONSTANT DefPulseWdthCnst : TIME := 0 ns;
-- default control options
-- CONSTANT DefGlitchMode : VitalGlitchKindType := OnEvent;
-- change default delay type to Transport : for spr 68748
CONSTANT DefGlitchMode : VitalGlitchKindType := VitalTransport;
CONSTANT DefGlitchMsgOn : BOOLEAN := FALSE;
CONSTANT DefGlitchXOn : BOOLEAN := FALSE;
CONSTANT DefMsgOnChecks : BOOLEAN := TRUE;
CONSTANT DefXOnChecks : BOOLEAN := TRUE;
-- output strength mapping
-- UX01ZWHL-
CONSTANT PullUp : VitalOutputMapType := "UX01HX01X";
CONSTANT NoPullUpZ : VitalOutputMapType := "UX01ZX01X";
CONSTANT PullDown : VitalOutputMapType := "UX01LX01X";
-- primitive result strength mapping
CONSTANT wiredOR : VitalResultMapType := ( 'U', 'X', 'L', '1' );
CONSTANT wiredAND : VitalResultMapType := ( 'U', 'X', '0', 'H' );
CONSTANT L : VitalTableSymbolType := '0';
CONSTANT H : VitalTableSymbolType := '1';
CONSTANT x : VitalTableSymbolType := '-';
CONSTANT S : VitalTableSymbolType := 'S';
CONSTANT R : VitalTableSymbolType := '/';
CONSTANT U : VitalTableSymbolType := 'X';
CONSTANT V : VitalTableSymbolType := 'B'; -- valid clock signal (non-rising)
-- Declare array types for CAM_SLICE
TYPE cycloneiii_mem_data IS ARRAY (0 to 31) of STD_LOGIC_VECTOR (31 downto 0);
function int2str( value : integer ) return string;
function map_x_to_0 (value : std_logic) return std_logic;
function SelectDelay (CONSTANT Paths: IN VitalPathArray01Type) return TIME;
function int2bit (arg : boolean) return std_logic;
function int2bit (arg : integer) return std_logic;
function bin2int (s : std_logic_vector) return integer;
function bin2int (s : std_logic) return integer;
function int2bin (arg : integer; size : integer) return std_logic_vector;
function int2bin (arg : boolean; size : integer) return std_logic_vector;
function calc_sum_len( widtha : integer; widthb : integer) return integer;
end cycloneiii_atom_pack;
library IEEE;
use IEEE.std_logic_1164.all;
package body cycloneiii_atom_pack is
type masklength is array (4 downto 1) of std_logic_vector(3 downto 0);
function str_to_bin (lut_mask : string) return std_logic_vector is
variable slice : masklength := (OTHERS => "0000");
variable mask : std_logic_vector(15 downto 0);
begin
for i in 1 to lut_mask'length loop
case lut_mask(i) is
when '0' => slice(i) := "0000";
when '1' => slice(i) := "0001";
when '2' => slice(i) := "0010";
when '3' => slice(i) := "0011";
when '4' => slice(i) := "0100";
when '5' => slice(i) := "0101";
when '6' => slice(i) := "0110";
when '7' => slice(i) := "0111";
when '8' => slice(i) := "1000";
when '9' => slice(i) := "1001";
when 'a' => slice(i) := "1010";
when 'A' => slice(i) := "1010";
when 'b' => slice(i) := "1011";
when 'B' => slice(i) := "1011";
when 'c' => slice(i) := "1100";
when 'C' => slice(i) := "1100";
when 'd' => slice(i) := "1101";
when 'D' => slice(i) := "1101";
when 'e' => slice(i) := "1110";
when 'E' => slice(i) := "1110";
when others => slice(i) := "1111";
end case;
end loop;
mask := (slice(1) & slice(2) & slice(3) & slice(4));
return (mask);
end str_to_bin;
function product (list: std_logic_vector) return std_logic is
begin
for i in 0 to 31 loop
if list(i) = '0' then
return ('0');
end if;
end loop;
return ('1');
end product;
function alt_conv_integer(arg : in std_logic_vector) return integer is
variable result : integer;
begin
result := 0;
for i in arg'range loop
if arg(i) = '1' then
result := result + 2**i;
end if;
end loop;
return result;
end alt_conv_integer;
function int2str( value : integer ) return string is
variable ivalue,index : integer;
variable digit : integer;
variable line_no: string(8 downto 1) := " ";
begin
ivalue := value;
index := 1;
if (ivalue = 0) then
line_no := " 0";
end if;
while (ivalue > 0) loop
digit := ivalue MOD 10;
ivalue := ivalue/10;
case digit is
when 0 =>
line_no(index) := '0';
when 1 =>
line_no(index) := '1';
when 2 =>
line_no(index) := '2';
when 3 =>
line_no(index) := '3';
when 4 =>
line_no(index) := '4';
when 5 =>
line_no(index) := '5';
when 6 =>
line_no(index) := '6';
when 7 =>
line_no(index) := '7';
when 8 =>
line_no(index) := '8';
when 9 =>
line_no(index) := '9';
when others =>
ASSERT FALSE
REPORT "Illegal number!"
SEVERITY ERROR;
end case;
index := index + 1;
end loop;
return line_no;
end;
function map_x_to_0 (value : std_logic) return std_logic is
begin
if (Is_X (value) = TRUE) then
return '0';
else
return value;
end if;
end;
function SelectDelay (CONSTANT Paths : IN VitalPathArray01Type) return TIME IS
variable Temp : TIME;
variable TransitionTime : TIME := TIME'HIGH;
variable PathDelay : TIME := TIME'HIGH;
begin
for i IN Paths'RANGE loop
next when not Paths(i).PathCondition;
next when Paths(i).InputChangeTime > TransitionTime;
Temp := Paths(i).PathDelay(tr01);
if Paths(i).InputChangeTime < TransitionTime then
PathDelay := Temp;
else
if Temp < PathDelay then
PathDelay := Temp;
end if;
end if;
TransitionTime := Paths(i).InputChangeTime;
end loop;
return PathDelay;
end;
function int2bit (arg : integer) return std_logic is
variable int_val : integer := arg;
variable result : std_logic;
begin
if (int_val = 0) then
result := '0';
else
result := '1';
end if;
return result;
end int2bit;
function int2bit (arg : boolean) return std_logic is
variable int_val : boolean := arg;
variable result : std_logic;
begin
if (int_val ) then
result := '1';
else
result := '0';
end if;
return result;
end int2bit;
function bin2int (s : std_logic_vector) return integer is
constant temp : std_logic_vector(s'high-s'low DOWNTO 0) := s;
variable result : integer := 0;
begin
for i in temp'range loop
if (temp(i) = '1') then
result := result + (2**i);
end if;
end loop;
return(result);
end bin2int;
function bin2int (s : std_logic) return integer is
constant temp : std_logic := s;
variable result : integer := 0;
begin
if (temp = '1') then
result := 1;
else
result := 0;
end if;
return(result);
end bin2int;
function int2bin (arg : integer; size : integer) return std_logic_vector is
variable int_val : integer := arg;
variable result : std_logic_vector(size-1 downto 0);
begin
for i in 0 to result'left loop
if ((int_val mod 2) = 0) then
result(i) := '0';
else
result(i) := '1';
end if;
int_val := int_val/2;
end loop;
return result;
end int2bin;
function int2bin (arg : boolean; size : integer) return std_logic_vector is
variable result : std_logic_vector(size-1 downto 0);
begin
if(arg)then
result := (OTHERS => '1');
else
result := (OTHERS => '0');
end if;
return result;
end int2bin;
function calc_sum_len( widtha : integer; widthb : integer) return integer is
variable result: integer;
begin
if(widtha >= widthb) then
result := widtha + 1;
else
result := widthb + 1;
end if;
return result;
end calc_sum_len;
end cycloneiii_atom_pack;
Library ieee;
use ieee.std_logic_1164.all;
Package cycloneiii_pllpack is
procedure find_simple_integer_fraction( numerator : in integer;
denominator : in integer;
max_denom : in integer;
fraction_num : out integer;
fraction_div : out integer);
procedure find_m_and_n_4_manual_phase ( inclock_period : in integer;
vco_phase_shift_step : in integer;
clk0_mult: in integer; clk1_mult: in integer;
clk2_mult: in integer; clk3_mult: in integer;
clk4_mult: in integer; clk5_mult: in integer;
clk6_mult: in integer; clk7_mult: in integer;
clk8_mult: in integer; clk9_mult: in integer;
clk0_div : in integer; clk1_div : in integer;
clk2_div : in integer; clk3_div : in integer;
clk4_div : in integer; clk5_div : in integer;
clk6_div : in integer; clk7_div : in integer;
clk8_div : in integer; clk9_div : in integer;
clk0_used : in string; clk1_used : in string;
clk2_used : in string; clk3_used : in string;
clk4_used : in string; clk5_used : in string;
clk6_used : in string; clk7_used : in string;
clk8_used : in string; clk9_used : in string;
m : out integer;
n : out integer );
function gcd (X: integer; Y: integer) return integer;
function count_digit (X: integer) return integer;
function scale_num (X: integer; Y: integer) return integer;
function lcm (A1: integer; A2: integer; A3: integer; A4: integer;
A5: integer; A6: integer; A7: integer;
A8: integer; A9: integer; A10: integer; P: integer) return integer;
function output_counter_value (clk_divide: integer; clk_mult : integer ;
M: integer; N: integer ) return integer;
function counter_mode (duty_cycle: integer; output_counter_value: integer) return string;
function counter_high (output_counter_value: integer := 1; duty_cycle: integer)
return integer;
function counter_low (output_counter_value: integer; duty_cycle: integer)
return integer;
function mintimedelay (t1: integer; t2: integer; t3: integer; t4: integer;
t5: integer; t6: integer; t7: integer; t8: integer;
t9: integer; t10: integer) return integer;
function maxnegabs (t1: integer; t2: integer; t3: integer; t4: integer;
t5: integer; t6: integer; t7: integer; t8: integer;
t9: integer; t10: integer) return integer;
function counter_time_delay ( clk_time_delay: integer;
m_time_delay: integer; n_time_delay: integer)
return integer;
function get_phase_degree (phase_shift: integer; clk_period: integer) return integer;
function counter_initial (tap_phase: integer; m: integer; n: integer)
return integer;
function counter_ph (tap_phase: integer; m : integer; n: integer) return integer;
function ph_adjust (tap_phase: integer; ph_base : integer) return integer;
function translate_string (mode : string) return string;
function str2int (s : string) return integer;
function dqs_str2int (s : string) return integer;
end cycloneiii_pllpack;
package body cycloneiii_pllpack is
-- finds the closest integer fraction of a given pair of numerator and denominator.
procedure find_simple_integer_fraction( numerator : in integer;
denominator : in integer;
max_denom : in integer;
fraction_num : out integer;
fraction_div : out integer) is
constant MAX_ITER : integer := 20;
type INT_ARRAY is array ((MAX_ITER-1) downto 0) of integer;
variable quotient_array : INT_ARRAY;
variable int_loop_iter : integer;
variable int_quot : integer;
variable m_value : integer;
variable d_value : integer;
variable old_m_value : integer;
variable swap : integer;
variable loop_iter : integer;
variable num : integer;
variable den : integer;
variable i_max_iter : integer;
begin
loop_iter := 0;
if (numerator = 0) then
num := 1;
else
num := numerator;
end if;
if (denominator = 0) then
den := 1;
else
den := denominator;
end if;
i_max_iter := max_iter;
while (loop_iter < i_max_iter) loop
int_quot := num / den;
quotient_array(loop_iter) := int_quot;
num := num - (den*int_quot);
loop_iter := loop_iter+1;
if ((num = 0) or (max_denom /= -1) or (loop_iter = i_max_iter)) then
-- calculate the numerator and denominator if there is a restriction on the
-- max denom value or if the loop is ending
m_value := 0;
d_value := 1;
-- get the rounded value at this stage for the remaining fraction
if (den /= 0) then
m_value := (2*num/den);
end if;
-- calculate the fraction numerator and denominator at this stage
for int_loop_iter in (loop_iter-1) downto 0 loop
if (m_value = 0) then
m_value := quotient_array(int_loop_iter);
d_value := 1;
else
old_m_value := m_value;
m_value := (quotient_array(int_loop_iter)*m_value) + d_value;
d_value := old_m_value;
end if;
end loop;
-- if the denominator is less than the maximum denom_value or if there is no restriction save it
if ((d_value <= max_denom) or (max_denom = -1)) then
if ((m_value = 0) or (d_value = 0)) then
fraction_num := numerator;
fraction_div := denominator;
else
fraction_num := m_value;
fraction_div := d_value;
end if;
end if;
-- end the loop if the denomitor has overflown or the numerator is zero (no remainder during this round)
if (((d_value > max_denom) and (max_denom /= -1)) or (num = 0)) then
i_max_iter := loop_iter;
end if;
end if;
-- swap the numerator and denominator for the next round
swap := den;
den := num;
num := swap;
end loop;
end find_simple_integer_fraction;
-- find the M and N values for Manual phase based on the following 5 criterias:
-- 1. The PFD frequency (i.e. Fin / N) must be in the range 5 MHz to 720 MHz
-- 2. The VCO frequency (i.e. Fin * M / N) must be in the range 300 MHz to 1300 MHz
-- 3. M is less than 512
-- 4. N is less than 512
-- 5. It's the smallest M/N which satisfies all the above constraints, and is within 2ps
-- of the desired vco-phase-shift-step
procedure find_m_and_n_4_manual_phase ( inclock_period : in integer;
vco_phase_shift_step : in integer;
clk0_mult: in integer; clk1_mult: in integer;
clk2_mult: in integer; clk3_mult: in integer;
clk4_mult: in integer; clk5_mult: in integer;
clk6_mult: in integer; clk7_mult: in integer;
clk8_mult: in integer; clk9_mult: in integer;
clk0_div : in integer; clk1_div : in integer;
clk2_div : in integer; clk3_div : in integer;
clk4_div : in integer; clk5_div : in integer;
clk6_div : in integer; clk7_div : in integer;
clk8_div : in integer; clk9_div : in integer;
clk0_used : in string; clk1_used : in string;
clk2_used : in string; clk3_used : in string;
clk4_used : in string; clk5_used : in string;
clk6_used : in string; clk7_used : in string;
clk8_used : in string; clk9_used : in string;
m : out integer;
n : out integer ) is
constant MAX_M : integer := 511;
constant MAX_N : integer := 511;
constant MAX_PFD : integer := 720;
constant MIN_PFD : integer := 5;
constant MAX_VCO : integer := 1600; -- max vco frequency. (in mHz)
constant MIN_VCO : integer := 300; -- min vco frequency. (in mHz)
constant MAX_OFFSET : real := 0.004;
variable vco_period : integer;
variable pfd_freq : integer;
variable vco_freq : integer;
variable vco_ps_step_value : integer;
variable i_m : integer;
variable i_n : integer;
variable i_pre_m : integer;
variable i_pre_n : integer;
variable closest_vco_step_value : integer;
variable i_max_iter : integer;
variable loop_iter : integer;
variable clk0_div_factor_real : real;
variable clk1_div_factor_real : real;
variable clk2_div_factor_real : real;
variable clk3_div_factor_real : real;
variable clk4_div_factor_real : real;
variable clk5_div_factor_real : real;
variable clk6_div_factor_real : real;
variable clk7_div_factor_real : real;
variable clk8_div_factor_real : real;
variable clk9_div_factor_real : real;
variable clk0_div_factor_int : integer;
variable clk1_div_factor_int : integer;
variable clk2_div_factor_int : integer;
variable clk3_div_factor_int : integer;
variable clk4_div_factor_int : integer;
variable clk5_div_factor_int : integer;
variable clk6_div_factor_int : integer;
variable clk7_div_factor_int : integer;
variable clk8_div_factor_int : integer;
variable clk9_div_factor_int : integer;
begin
vco_period := vco_phase_shift_step * 8;
i_pre_m := 0;
i_pre_n := 0;
closest_vco_step_value := 0;
LOOP_1 : for i_n_out in 1 to MAX_N loop
for i_m_out in 1 to MAX_M loop
clk0_div_factor_real := real(clk0_div * i_m_out) / real(clk0_mult * i_n_out);
clk1_div_factor_real := real(clk1_div * i_m_out) / real(clk1_mult * i_n_out);
clk2_div_factor_real := real(clk2_div * i_m_out) / real(clk2_mult * i_n_out);
clk3_div_factor_real := real(clk3_div * i_m_out) / real(clk3_mult * i_n_out);
clk4_div_factor_real := real(clk4_div * i_m_out) / real(clk4_mult * i_n_out);
clk5_div_factor_real := real(clk5_div * i_m_out) / real(clk5_mult * i_n_out);
clk6_div_factor_real := real(clk6_div * i_m_out) / real(clk6_mult * i_n_out);
clk7_div_factor_real := real(clk7_div * i_m_out) / real(clk7_mult * i_n_out);
clk8_div_factor_real := real(clk8_div * i_m_out) / real(clk8_mult * i_n_out);
clk9_div_factor_real := real(clk9_div * i_m_out) / real(clk9_mult * i_n_out);
clk0_div_factor_int := integer(clk0_div_factor_real);
clk1_div_factor_int := integer(clk1_div_factor_real);
clk2_div_factor_int := integer(clk2_div_factor_real);
clk3_div_factor_int := integer(clk3_div_factor_real);
clk4_div_factor_int := integer(clk4_div_factor_real);
clk5_div_factor_int := integer(clk5_div_factor_real);
clk6_div_factor_int := integer(clk6_div_factor_real);
clk7_div_factor_int := integer(clk7_div_factor_real);
clk8_div_factor_int := integer(clk8_div_factor_real);
clk9_div_factor_int := integer(clk9_div_factor_real);
if (((abs(clk0_div_factor_real - real(clk0_div_factor_int)) < MAX_OFFSET) or (clk0_used = "unused")) and
((abs(clk1_div_factor_real - real(clk1_div_factor_int)) < MAX_OFFSET) or (clk1_used = "unused")) and
((abs(clk2_div_factor_real - real(clk2_div_factor_int)) < MAX_OFFSET) or (clk2_used = "unused")) and
((abs(clk3_div_factor_real - real(clk3_div_factor_int)) < MAX_OFFSET) or (clk3_used = "unused")) and
((abs(clk4_div_factor_real - real(clk4_div_factor_int)) < MAX_OFFSET) or (clk4_used = "unused")) and
((abs(clk5_div_factor_real - real(clk5_div_factor_int)) < MAX_OFFSET) or (clk5_used = "unused")) and
((abs(clk6_div_factor_real - real(clk6_div_factor_int)) < MAX_OFFSET) or (clk6_used = "unused")) and
((abs(clk7_div_factor_real - real(clk7_div_factor_int)) < MAX_OFFSET) or (clk7_used = "unused")) and
((abs(clk8_div_factor_real - real(clk8_div_factor_int)) < MAX_OFFSET) or (clk8_used = "unused")) and
((abs(clk9_div_factor_real - real(clk9_div_factor_int)) < MAX_OFFSET) or (clk9_used = "unused")) )
then
if ((i_m_out /= 0) and (i_n_out /= 0))
then
pfd_freq := 1000000 / (inclock_period * i_n_out);
vco_freq := (1000000 * i_m_out) / (inclock_period * i_n_out);
vco_ps_step_value := (inclock_period * i_n_out) / (8 * i_m_out);
if ( (i_m_out < max_m) and (i_n_out < max_n) and (pfd_freq >= min_pfd) and (pfd_freq <= max_pfd) and
(vco_freq >= min_vco) and (vco_freq <= max_vco) )
then
if (abs(vco_ps_step_value - vco_phase_shift_step) <= 2)
then
i_pre_m := i_m_out;
i_pre_n := i_n_out;
exit LOOP_1;
else
if ((closest_vco_step_value = 0) or (abs(vco_ps_step_value - vco_phase_shift_step) < abs(closest_vco_step_value - vco_phase_shift_step)))
then
i_pre_m := i_m_out;
i_pre_n := i_n_out;
closest_vco_step_value := vco_ps_step_value;
end if;
end if;
end if;
end if;
end if;
end loop;
end loop;
if ((i_pre_m /= 0) and (i_pre_n /= 0))
then
find_simple_integer_fraction(i_pre_m, i_pre_n,
MAX_N, m, n);
else
n := 1;
m := lcm (clk0_mult, clk1_mult, clk2_mult, clk3_mult,
clk4_mult, clk5_mult, clk6_mult,
clk7_mult, clk8_mult, clk9_mult, inclock_period);
end if;
end find_m_and_n_4_manual_phase;
-- find the greatest common denominator of X and Y
function gcd (X: integer; Y: integer) return integer is
variable L, S, R, G : integer := 1;
begin
if (X < Y) then -- find which is smaller.
S := X;
L := Y;
else
S := Y;
L := X;
end if;
R := S;
while ( R > 1) loop
S := L;
L := R;
R := S rem L; -- divide bigger number by smaller.
-- remainder becomes smaller number.
end loop;
if (R = 0) then -- if evenly divisible then L is gcd else it is 1.
G := L;
else
G := R;
end if;
return G;
end gcd;
-- count the number of digits in the given integer
function count_digit (X: integer)
return integer is
variable count, result: integer := 0;
begin
result := X;
while (result /= 0) loop
result := (result / 10);
count := count + 1;
end loop;
return count;
end count_digit;
-- reduce the given huge number to Y significant digits
function scale_num (X: integer; Y: integer)
return integer is
variable count : integer := 0;
variable lc, fac_ten, result: integer := 1;
begin
count := count_digit(X);
for lc in 1 to (count-Y) loop
fac_ten := fac_ten * 10;
end loop;
result := (X / fac_ten);
return result;
end scale_num;
-- find the least common multiple of A1 to A10
function lcm (A1: integer; A2: integer; A3: integer; A4: integer;
A5: integer; A6: integer; A7: integer;
A8: integer; A9: integer; A10: integer; P: integer)
return integer is
variable M1, M2, M3, M4, M5 , M6, M7, M8, M9, R: integer := 1;
begin
M1 := (A1 * A2)/gcd(A1, A2);
M2 := (M1 * A3)/gcd(M1, A3);
M3 := (M2 * A4)/gcd(M2, A4);
M4 := (M3 * A5)/gcd(M3, A5);
M5 := (M4 * A6)/gcd(M4, A6);
M6 := (M5 * A7)/gcd(M5, A7);
M7 := (M6 * A8)/gcd(M6, A8);
M8 := (M7 * A9)/gcd(M7, A9);
M9 := (M8 * A10)/gcd(M8, A10);
if (M9 < 3) then
R := 10;
elsif (M9 = 3) then
R := 9;
elsif ((M9 <= 10) and (M9 > 3)) then
R := 4 * M9;
elsif (M9 > 1000) then
R := scale_num(M9,3);
else
R := M9 ;
end if;
return R;
end lcm;
-- find the factor of division of the output clock frequency compared to the VCO
function output_counter_value (clk_divide: integer; clk_mult: integer ;
M: integer; N: integer ) return integer is
variable r_real : real := 1.0;
variable r: integer := 1;
begin
r_real := real(clk_divide * M)/ real(clk_mult * N);
r := integer(r_real);
return R;
end output_counter_value;
-- find the mode of each PLL counter - bypass, even or odd
function counter_mode (duty_cycle: integer; output_counter_value: integer)
return string is
variable R: string (1 to 6) := " ";
variable counter_value: integer := 1;
begin
counter_value := (2*duty_cycle*output_counter_value)/100;
if output_counter_value = 1 then
R := "bypass";
elsif (counter_value REM 2) = 0 then
R := " even";
else
R := " odd";
end if;
return R;
end counter_mode;
-- find the number of VCO clock cycles to hold the output clock high
function counter_high (output_counter_value: integer := 1; duty_cycle: integer)
return integer is
variable R: integer := 1;
variable half_cycle_high : integer := 1;
begin
half_cycle_high := (duty_cycle * output_counter_value *2)/100 ;
if (half_cycle_high REM 2 = 0) then
R := half_cycle_high/2 ;
else
R := (half_cycle_high/2) + 1;
end if;
return R;
end;
-- find the number of VCO clock cycles to hold the output clock low
function counter_low (output_counter_value: integer; duty_cycle: integer)
return integer is
variable R, R1: integer := 1;
variable half_cycle_high : integer := 1;
begin
half_cycle_high := (duty_cycle * output_counter_value*2)/100 ;
if (half_cycle_high REM 2 = 0) then
R1 := half_cycle_high/2 ;
else
R1 := (half_cycle_high/2) + 1;
end if;
R := output_counter_value - R1;
if (R = 0) then
R := 1;
end if;
return R;
end;
-- find the smallest time delay amongst t1 to t10
function mintimedelay (t1: integer; t2: integer; t3: integer; t4: integer;
t5: integer; t6: integer; t7: integer; t8: integer;
t9: integer; t10: integer) return integer is
variable m1,m2,m3,m4,m5,m6,m7,m8,m9 : integer := 0;
begin
if (t1 < t2) then m1 := t1; else m1 := t2; end if;
if (m1 < t3) then m2 := m1; else m2 := t3; end if;
if (m2 < t4) then m3 := m2; else m3 := t4; end if;
if (m3 < t5) then m4 := m3; else m4 := t5; end if;
if (m4 < t6) then m5 := m4; else m5 := t6; end if;
if (m5 < t7) then m6 := m5; else m6 := t7; end if;
if (m6 < t8) then m7 := m6; else m7 := t8; end if;
if (m7 < t9) then m8 := m7; else m8 := t9; end if;
if (m8 < t10) then m9 := m8; else m9 := t10; end if;
if (m9 > 0) then return m9; else return 0; end if;
end;
-- find the numerically largest negative number, and return its absolute value
function maxnegabs (t1: integer; t2: integer; t3: integer; t4: integer;
t5: integer; t6: integer; t7: integer; t8: integer;
t9: integer; t10: integer) return integer is
variable m1,m2,m3,m4,m5,m6,m7,m8,m9 : integer := 0;
begin
if (t1 < t2) then m1 := t1; else m1 := t2; end if;
if (m1 < t3) then m2 := m1; else m2 := t3; end if;
if (m2 < t4) then m3 := m2; else m3 := t4; end if;
if (m3 < t5) then m4 := m3; else m4 := t5; end if;
if (m4 < t6) then m5 := m4; else m5 := t6; end if;
if (m5 < t7) then m6 := m5; else m6 := t7; end if;
if (m6 < t8) then m7 := m6; else m7 := t8; end if;
if (m7 < t9) then m8 := m7; else m8 := t9; end if;
if (m8 < t10) then m9 := m8; else m9 := t10; end if;
if (m9 < 0) then return (0 - m9); else return 0; end if;
end;
-- adjust the phase (tap_phase) with the largest negative number (ph_base)
function ph_adjust (tap_phase: integer; ph_base : integer) return integer is
begin
return (tap_phase + ph_base);
end;
-- find the time delay for each PLL counter
function counter_time_delay (clk_time_delay: integer;
m_time_delay: integer; n_time_delay: integer)
return integer is
variable R: integer := 0;
begin
R := clk_time_delay + m_time_delay - n_time_delay;
return R;
end;
-- calculate the given phase shift (in ps) in terms of degrees
function get_phase_degree (phase_shift: integer; clk_period: integer)
return integer is
variable result: integer := 0;
begin
result := ( phase_shift * 360 ) / clk_period;
-- to round up the calculation result
if (result > 0) then
result := result + 1;
elsif (result < 0) then
result := result - 1;
else
result := 0;
end if;
return result;
end;
-- find the number of VCO clock cycles to wait initially before the first rising
-- edge of the output clock
function counter_initial (tap_phase: integer; m: integer; n: integer)
return integer is
variable R: integer;
variable R1: real;
begin
R1 := (real(abs(tap_phase)) * real(m))/(360.0 * real(n)) + 0.6;
-- Note NCSim VHDL had problem in rounding up for 0.5 - 0.99.
-- This checking will ensure that the rounding up is done.
if (R1 >= 0.5) and (R1 <= 1.0) then
R1 := 1.0;
end if;
R := integer(R1);
return R;
end;
-- find which VCO phase tap (0 to 7) to align the rising edge of the output clock to
function counter_ph (tap_phase: integer; m: integer; n: integer) return integer is
variable R: integer := 0;
begin
-- 0.5 is added for proper rounding of the tap_phase.
R := integer(real(integer(real(tap_phase * m / n)+ 0.5) REM 360)/45.0) rem 8;
return R;
end;
-- convert given string to length 6 by padding with spaces
function translate_string (mode : string) return string is
variable new_mode : string (1 to 6) := " ";
begin
if (mode = "bypass") then
new_mode := "bypass";
elsif (mode = "even") then
new_mode := " even";
elsif (mode = "odd") then
new_mode := " odd";
end if;
return new_mode;
end;
function str2int (s : string) return integer is
variable len : integer := s'length;
variable newdigit : integer := 0;
variable sign : integer := 1;
variable digit : integer := 0;
begin
for i in 1 to len loop
case s(i) is
when '-' =>
if i = 1 then
sign := -1;
else
ASSERT FALSE
REPORT "Illegal Character "& s(i) & "i n string parameter! "
SEVERITY ERROR;
end if;
when '0' =>
digit := 0;
when '1' =>
digit := 1;
when '2' =>
digit := 2;
when '3' =>
digit := 3;
when '4' =>
digit := 4;
when '5' =>
digit := 5;
when '6' =>
digit := 6;
when '7' =>
digit := 7;
when '8' =>
digit := 8;
when '9' =>
digit := 9;
when others =>
ASSERT FALSE
REPORT "Illegal Character "& s(i) & "in string parameter! "
SEVERITY ERROR;
end case;
newdigit := newdigit * 10 + digit;
end loop;
return (sign*newdigit);
end;
function dqs_str2int (s : string) return integer is
variable len : integer := s'length;
variable newdigit : integer := 0;
variable sign : integer := 1;
variable digit : integer := 0;
variable err : boolean := false;
begin
for i in 1 to len loop
case s(i) is
when '-' =>
if i = 1 then
sign := -1;
else
ASSERT FALSE
REPORT "Illegal Character "& s(i) & " in string parameter! "
SEVERITY ERROR;
err := true;
end if;
when '0' =>
digit := 0;
when '1' =>
digit := 1;
when '2' =>
digit := 2;
when '3' =>
digit := 3;
when '4' =>
digit := 4;
when '5' =>
digit := 5;
when '6' =>
digit := 6;
when '7' =>
digit := 7;
when '8' =>
digit := 8;
when '9' =>
digit := 9;
when others =>
-- set error flag
err := true;
end case;
if (err) then
err := false;
else
newdigit := newdigit * 10 + digit;
end if;
end loop;
return (sign*newdigit);
end;
end cycloneiii_pllpack;
--
--
-- DFFE Model
--
--
LIBRARY IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.cycloneiii_atom_pack.all;
entity cycloneiii_dffe is
generic(
TimingChecksOn: Boolean := True;
XOn: Boolean := DefGlitchXOn;
MsgOn: Boolean := DefGlitchMsgOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*";
tpd_PRN_Q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_CLRN_Q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_CLK_Q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_ENA_Q_posedge : VitalDelayType01 := DefPropDelay01;
tsetup_D_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_D_CLK_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ENA_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_D_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_D_CLK_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
thold_ENA_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tipd_D : VitalDelayType01 := DefPropDelay01;
tipd_CLRN : VitalDelayType01 := DefPropDelay01;
tipd_PRN : VitalDelayType01 := DefPropDelay01;
tipd_CLK : VitalDelayType01 := DefPropDelay01;
tipd_ENA : VitalDelayType01 := DefPropDelay01);
port(
Q : out STD_LOGIC := '0';
D : in STD_LOGIC;
CLRN : in STD_LOGIC;
PRN : in STD_LOGIC;
CLK : in STD_LOGIC;
ENA : in STD_LOGIC);
attribute VITAL_LEVEL0 of cycloneiii_dffe : entity is TRUE;
end cycloneiii_dffe;
-- architecture body --
architecture behave of cycloneiii_dffe is
attribute VITAL_LEVEL0 of behave : architecture is TRUE;
signal D_ipd : STD_ULOGIC := 'U';
signal CLRN_ipd : STD_ULOGIC := 'U';
signal PRN_ipd : STD_ULOGIC := 'U';
signal CLK_ipd : STD_ULOGIC := 'U';
signal ENA_ipd : STD_ULOGIC := 'U';
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (D_ipd, D, tipd_D);
VitalWireDelay (CLRN_ipd, CLRN, tipd_CLRN);
VitalWireDelay (PRN_ipd, PRN, tipd_PRN);
VitalWireDelay (CLK_ipd, CLK, tipd_CLK);
VitalWireDelay (ENA_ipd, ENA, tipd_ENA);
end block;
--------------------
-- BEHAVIOR SECTION
--------------------
VITALBehavior : process (D_ipd, CLRN_ipd, PRN_ipd, CLK_ipd, ENA_ipd)
-- timing check results
VARIABLE Tviol_D_CLK : STD_ULOGIC := '0';
VARIABLE Tviol_ENA_CLK : STD_ULOGIC := '0';
VARIABLE TimingData_D_CLK : VitalTimingDataType := VitalTimingDataInit;
VARIABLE TimingData_ENA_CLK : VitalTimingDataType := VitalTimingDataInit;
-- functionality results
VARIABLE Violation : STD_ULOGIC := '0';
VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 7);
VARIABLE D_delayed : STD_ULOGIC := 'U';
VARIABLE CLK_delayed : STD_ULOGIC := 'U';
VARIABLE ENA_delayed : STD_ULOGIC := 'U';
VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => '0');
-- output glitch detection variables
VARIABLE Q_VitalGlitchData : VitalGlitchDataType;
CONSTANT dffe_Q_tab : VitalStateTableType := (
( L, L, x, x, x, x, x, x, x, L ),
( L, H, L, H, H, x, x, H, x, H ),
( L, H, L, H, x, L, x, H, x, H ),
( L, H, L, x, H, H, x, H, x, H ),
( L, H, H, x, x, x, H, x, x, S ),
( L, H, x, x, x, x, L, x, x, H ),
( L, H, x, x, x, x, H, L, x, S ),
( L, x, L, L, L, x, H, H, x, L ),
( L, x, L, L, x, L, H, H, x, L ),
( L, x, L, x, L, H, H, H, x, L ),
( L, x, x, x, x, x, x, x, x, S ));
begin
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_D_CLK,
TimingData => TimingData_D_CLK,
TestSignal => D_ipd,
TestSignalName => "D",
RefSignal => CLK_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_D_CLK_noedge_posedge,
SetupLow => tsetup_D_CLK_noedge_posedge,
HoldHigh => thold_D_CLK_noedge_posedge,
HoldLow => thold_D_CLK_noedge_posedge,
CheckEnabled => TO_X01(( (NOT PRN_ipd) ) OR ( (NOT CLRN_ipd) ) OR ( (NOT ENA_ipd) )) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/DFFE",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_ENA_CLK,
TimingData => TimingData_ENA_CLK,
TestSignal => ENA_ipd,
TestSignalName => "ENA",
RefSignal => CLK_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_ENA_CLK_noedge_posedge,
SetupLow => tsetup_ENA_CLK_noedge_posedge,
HoldHigh => thold_ENA_CLK_noedge_posedge,
HoldLow => thold_ENA_CLK_noedge_posedge,
CheckEnabled => TO_X01(( (NOT PRN_ipd) ) OR ( (NOT CLRN_ipd) ) ) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/DFFE",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
end if;
-------------------------
-- Functionality Section
-------------------------
Violation := Tviol_D_CLK or Tviol_ENA_CLK;
VitalStateTable(
StateTable => dffe_Q_tab,
DataIn => (
Violation, CLRN_ipd, CLK_delayed, Results(1), D_delayed, ENA_delayed, PRN_ipd, CLK_ipd),
Result => Results,
NumStates => 1,
PreviousDataIn => PrevData_Q);
D_delayed := D_ipd;
CLK_delayed := CLK_ipd;
ENA_delayed := ENA_ipd;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => Q,
OutSignalName => "Q",
OutTemp => Results(1),
Paths => ( 0 => (PRN_ipd'last_event, tpd_PRN_Q_negedge, TRUE),
1 => (CLRN_ipd'last_event, tpd_CLRN_Q_negedge, TRUE),
2 => (CLK_ipd'last_event, tpd_CLK_Q_posedge, TRUE)),
GlitchData => Q_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end behave;
--
--
-- cycloneiii_mux21 Model
--
--
LIBRARY IEEE;
use ieee.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use work.cycloneiii_atom_pack.all;
entity cycloneiii_mux21 is
generic(
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
InstancePath: STRING := "*";
tpd_A_MO : VitalDelayType01 := DefPropDelay01;
tpd_B_MO : VitalDelayType01 := DefPropDelay01;
tpd_S_MO : VitalDelayType01 := DefPropDelay01;
tipd_A : VitalDelayType01 := DefPropDelay01;
tipd_B : VitalDelayType01 := DefPropDelay01;
tipd_S : VitalDelayType01 := DefPropDelay01);
port (
A : in std_logic := '0';
B : in std_logic := '0';
S : in std_logic := '0';
MO : out std_logic);
attribute VITAL_LEVEL0 of cycloneiii_mux21 : entity is TRUE;
end cycloneiii_mux21;
architecture AltVITAL of cycloneiii_mux21 is
attribute VITAL_LEVEL0 of AltVITAL : architecture is TRUE;
signal A_ipd, B_ipd, S_ipd : std_logic;
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (A_ipd, A, tipd_A);
VitalWireDelay (B_ipd, B, tipd_B);
VitalWireDelay (S_ipd, S, tipd_S);
end block;
--------------------
-- BEHAVIOR SECTION
--------------------
VITALBehavior : process (A_ipd, B_ipd, S_ipd)
-- output glitch detection variables
VARIABLE MO_GlitchData : VitalGlitchDataType;
variable tmp_MO : std_logic;
begin
-------------------------
-- Functionality Section
-------------------------
if (S_ipd = '1') then
tmp_MO := B_ipd;
else
tmp_MO := A_ipd;
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => MO,
OutSignalName => "MO",
OutTemp => tmp_MO,
Paths => ( 0 => (A_ipd'last_event, tpd_A_MO, TRUE),
1 => (B_ipd'last_event, tpd_B_MO, TRUE),
2 => (S_ipd'last_event, tpd_S_MO, TRUE)),
GlitchData => MO_GlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end AltVITAL;
--
--
-- cycloneiii_mux41 Model
--
--
LIBRARY IEEE;
use ieee.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use work.cycloneiii_atom_pack.all;
entity cycloneiii_mux41 is
generic(
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
InstancePath: STRING := "*";
tpd_IN0_MO : VitalDelayType01 := DefPropDelay01;
tpd_IN1_MO : VitalDelayType01 := DefPropDelay01;
tpd_IN2_MO : VitalDelayType01 := DefPropDelay01;
tpd_IN3_MO : VitalDelayType01 := DefPropDelay01;
tpd_S_MO : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01);
tipd_IN0 : VitalDelayType01 := DefPropDelay01;
tipd_IN1 : VitalDelayType01 := DefPropDelay01;
tipd_IN2 : VitalDelayType01 := DefPropDelay01;
tipd_IN3 : VitalDelayType01 := DefPropDelay01;
tipd_S : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01)
);
port (
IN0 : in std_logic := '0';
IN1 : in std_logic := '0';
IN2 : in std_logic := '0';
IN3 : in std_logic := '0';
S : in std_logic_vector(1 downto 0) := (OTHERS => '0');
MO : out std_logic
);
attribute VITAL_LEVEL0 of cycloneiii_mux41 : entity is TRUE;
end cycloneiii_mux41;
architecture AltVITAL of cycloneiii_mux41 is
attribute VITAL_LEVEL0 of AltVITAL : architecture is TRUE;
signal IN0_ipd, IN1_ipd, IN2_ipd, IN3_ipd : std_logic;
signal S_ipd : std_logic_vector(1 downto 0);
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (IN0_ipd, IN0, tipd_IN0);
VitalWireDelay (IN1_ipd, IN1, tipd_IN1);
VitalWireDelay (IN2_ipd, IN2, tipd_IN2);
VitalWireDelay (IN3_ipd, IN3, tipd_IN3);
VitalWireDelay (S_ipd(0), S(0), tipd_S(0));
VitalWireDelay (S_ipd(1), S(1), tipd_S(1));
end block;
--------------------
-- BEHAVIOR SECTION
--------------------
VITALBehavior : process (IN0_ipd, IN1_ipd, IN2_ipd, IN3_ipd, S_ipd(0), S_ipd(1))
-- output glitch detection variables
VARIABLE MO_GlitchData : VitalGlitchDataType;
variable tmp_MO : std_logic;
begin
-------------------------
-- Functionality Section
-------------------------
if ((S_ipd(1) = '1') AND (S_ipd(0) = '1')) then
tmp_MO := IN3_ipd;
elsif ((S_ipd(1) = '1') AND (S_ipd(0) = '0')) then
tmp_MO := IN2_ipd;
elsif ((S_ipd(1) = '0') AND (S_ipd(0) = '1')) then
tmp_MO := IN1_ipd;
else
tmp_MO := IN0_ipd;
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => MO,
OutSignalName => "MO",
OutTemp => tmp_MO,
Paths => ( 0 => (IN0_ipd'last_event, tpd_IN0_MO, TRUE),
1 => (IN1_ipd'last_event, tpd_IN1_MO, TRUE),
2 => (IN2_ipd'last_event, tpd_IN2_MO, TRUE),
3 => (IN3_ipd'last_event, tpd_IN3_MO, TRUE),
4 => (S_ipd(0)'last_event, tpd_S_MO(0), TRUE),
5 => (S_ipd(1)'last_event, tpd_S_MO(1), TRUE)),
GlitchData => MO_GlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end AltVITAL;
--
--
-- cycloneiii_and1 Model
--
--
LIBRARY IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.VITAL_Timing.all;
use work.cycloneiii_atom_pack.all;
-- entity declaration --
entity cycloneiii_and1 is
generic(
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
InstancePath: STRING := "*";
tpd_IN1_Y : VitalDelayType01 := DefPropDelay01;
tipd_IN1 : VitalDelayType01 := DefPropDelay01);
port(
Y : out STD_LOGIC;
IN1 : in STD_LOGIC);
attribute VITAL_LEVEL0 of cycloneiii_and1 : entity is TRUE;
end cycloneiii_and1;
-- architecture body --
architecture AltVITAL of cycloneiii_and1 is
attribute VITAL_LEVEL0 of AltVITAL : architecture is TRUE;
SIGNAL IN1_ipd : STD_ULOGIC := 'U';
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (IN1_ipd, IN1, tipd_IN1);
end block;
--------------------
-- BEHAVIOR SECTION
--------------------
VITALBehavior : process (IN1_ipd)
-- functionality results
VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
ALIAS Y_zd : STD_ULOGIC is Results(1);
-- output glitch detection variables
VARIABLE Y_GlitchData : VitalGlitchDataType;
begin
-------------------------
-- Functionality Section
-------------------------
Y_zd := TO_X01(IN1_ipd);
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => Y,
OutSignalName => "Y",
OutTemp => Y_zd,
Paths => (0 => (IN1_ipd'last_event, tpd_IN1_Y, TRUE)),
GlitchData => Y_GlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end AltVITAL;
---------------------------------------------------------------------
--
-- Entity Name : cycloneiii_lcell_comb
--
-- Description : Cyclone II LCELL_COMB VHDL simulation model
--
--
---------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.cycloneiii_atom_pack.all;
entity cycloneiii_lcell_comb is
generic (
lut_mask : std_logic_vector(15 downto 0) := (OTHERS => '1');
sum_lutc_input : string := "datac";
dont_touch : string := "off";
lpm_type : string := "cycloneiii_lcell_comb";
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*";
tpd_dataa_combout : VitalDelayType01 := DefPropDelay01;
tpd_datab_combout : VitalDelayType01 := DefPropDelay01;
tpd_datac_combout : VitalDelayType01 := DefPropDelay01;
tpd_datad_combout : VitalDelayType01 := DefPropDelay01;
tpd_cin_combout : VitalDelayType01 := DefPropDelay01;
tpd_dataa_cout : VitalDelayType01 := DefPropDelay01;
tpd_datab_cout : VitalDelayType01 := DefPropDelay01;
tpd_datac_cout : VitalDelayType01 := DefPropDelay01;
tpd_datad_cout : VitalDelayType01 := DefPropDelay01;
tpd_cin_cout : VitalDelayType01 := DefPropDelay01;
tipd_dataa : VitalDelayType01 := DefPropDelay01;
tipd_datab : VitalDelayType01 := DefPropDelay01;
tipd_datac : VitalDelayType01 := DefPropDelay01;
tipd_datad : VitalDelayType01 := DefPropDelay01;
tipd_cin : VitalDelayType01 := DefPropDelay01
);
port (
dataa : in std_logic := '1';
datab : in std_logic := '1';
datac : in std_logic := '1';
datad : in std_logic := '1';
cin : in std_logic := '0';
combout : out std_logic;
cout : out std_logic
);
attribute VITAL_LEVEL0 of cycloneiii_lcell_comb : entity is TRUE;
end cycloneiii_lcell_comb;
architecture vital_lcell_comb of cycloneiii_lcell_comb is
attribute VITAL_LEVEL0 of vital_lcell_comb : architecture is TRUE;
signal dataa_ipd : std_logic;
signal datab_ipd : std_logic;
signal datac_ipd : std_logic;
signal datad_ipd : std_logic;
signal cin_ipd : std_logic;
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (dataa_ipd, dataa, tipd_dataa);
VitalWireDelay (datab_ipd, datab, tipd_datab);
VitalWireDelay (datac_ipd, datac, tipd_datac);
VitalWireDelay (datad_ipd, datad, tipd_datad);
VitalWireDelay (cin_ipd, cin, tipd_cin);
end block;
VITALtiming : process(dataa_ipd, datab_ipd, datac_ipd, datad_ipd,
cin_ipd)
variable combout_VitalGlitchData : VitalGlitchDataType;
variable cout_VitalGlitchData : VitalGlitchDataType;
-- output variables
variable combout_tmp : std_logic;
variable cout_tmp : std_logic;
begin
-- lut_mask_var := lut_mask;
------------------------
-- Timing Check Section
------------------------
if (sum_lutc_input = "datac") then
-- combout
combout_tmp := VitalMUX(data => lut_mask,
dselect => (datad_ipd,
datac_ipd,
datab_ipd,
dataa_ipd));
elsif (sum_lutc_input = "cin") then
-- combout
combout_tmp := VitalMUX(data => lut_mask,
dselect => (datad_ipd,
cin_ipd,
datab_ipd,
dataa_ipd));
end if;
-- cout
cout_tmp := VitalMUX(data => lut_mask,
dselect => ('0',
cin_ipd,
datab_ipd,
dataa_ipd));
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => combout,
OutSignalName => "COMBOUT",
OutTemp => combout_tmp,
Paths => (0 => (dataa_ipd'last_event, tpd_dataa_combout, TRUE),
1 => (datab_ipd'last_event, tpd_datab_combout, TRUE),
2 => (datac_ipd'last_event, tpd_datac_combout, TRUE),
3 => (datad_ipd'last_event, tpd_datad_combout, TRUE),
4 => (cin_ipd'last_event, tpd_cin_combout, TRUE)),
GlitchData => combout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => cout,
OutSignalName => "COUT",
OutTemp => cout_tmp,
Paths => (0 => (dataa_ipd'last_event, tpd_dataa_cout, TRUE),
1 => (datab_ipd'last_event, tpd_datab_cout, TRUE),
2 => (datac_ipd'last_event, tpd_datac_cout, TRUE),
3 => (datad_ipd'last_event, tpd_datad_cout, TRUE),
4 => (cin_ipd'last_event, tpd_cin_cout, TRUE)),
GlitchData => cout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end vital_lcell_comb;
---------------------------------------------------------------------
--
-- Entity Name : cycloneiii_routing_wire
--
-- Description : Cyclone III Routing Wire VHDL simulation model
--
--
---------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.cycloneiii_atom_pack.all;
ENTITY cycloneiii_routing_wire is
generic (
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
tpd_datain_dataout : VitalDelayType01 := DefPropDelay01;
tpd_datainglitch_dataout : VitalDelayType01 := DefPropDelay01;
tipd_datain : VitalDelayType01 := DefPropDelay01
);
PORT (
datain : in std_logic;
dataout : out std_logic
);
attribute VITAL_LEVEL0 of cycloneiii_routing_wire : entity is TRUE;
end cycloneiii_routing_wire;
ARCHITECTURE behave of cycloneiii_routing_wire is
attribute VITAL_LEVEL0 of behave : architecture is TRUE;
signal datain_ipd : std_logic;
signal datainglitch_inert : std_logic;
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (datain_ipd, datain, tipd_datain);
end block;
VITAL: process(datain_ipd, datainglitch_inert)
variable datain_inert_VitalGlitchData : VitalGlitchDataType;
variable dataout_VitalGlitchData : VitalGlitchDataType;
begin
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => datainglitch_inert,
OutSignalName => "datainglitch_inert",
OutTemp => datain_ipd,
Paths => (1 => (datain_ipd'last_event, tpd_datainglitch_dataout, TRUE)),
GlitchData => datain_inert_VitalGlitchData,
Mode => VitalInertial,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => dataout,
OutSignalName => "dataout",
OutTemp => datainglitch_inert,
Paths => (1 => (datain_ipd'last_event, tpd_datain_dataout, TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end behave;
--///////////////////////////////////////////////////////////////////////////
--
-- Entity Name : cycloneiii_mn_cntr
--
-- Description : Timing simulation model for the M and N counter. This is a
-- common model for the input counter and the loop feedback
-- counter of the Cyclone III PLL.
--
--///////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_unsigned.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
ENTITY cycloneiii_mn_cntr is
PORT( clk : IN std_logic;
reset : IN std_logic := '0';
cout : OUT std_logic;
initial_value : IN integer := 1;
modulus : IN integer := 1;
time_delay : IN integer := 0
);
END cycloneiii_mn_cntr;
ARCHITECTURE behave of cycloneiii_mn_cntr is
begin
process (clk, reset)
variable count : integer := 1;
variable first_rising_edge : boolean := true;
variable tmp_cout : std_logic;
begin
if (reset = '1') then
count := 1;
tmp_cout := '0';
first_rising_edge := true;
elsif (clk'event) then
if (clk = '1' and first_rising_edge) then
first_rising_edge := false;
tmp_cout := clk;
elsif (not first_rising_edge) then
if (count < modulus) then
count := count + 1;
else
count := 1;
tmp_cout := not tmp_cout;
end if;
end if;
end if;
cout <= transport tmp_cout after time_delay * 1 ps;
end process;
end behave;
--/////////////////////////////////////////////////////////////////////////////
--
-- Entity Name : cycloneiii_scale_cntr
--
-- Description : Timing simulation model for the output scale-down counters.
-- This is a common model for the C0, C1, C2, C3, C4 and C5
-- output counters of the Cyclone III PLL.
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
ENTITY cycloneiii_scale_cntr is
PORT( clk : IN std_logic;
reset : IN std_logic := '0';
initial : IN integer := 1;
high : IN integer := 1;
low : IN integer := 1;
mode : IN string := "bypass";
ph_tap : IN integer := 0;
cout : OUT std_logic
);
END cycloneiii_scale_cntr;
ARCHITECTURE behave of cycloneiii_scale_cntr is
begin
process (clk, reset)
variable tmp_cout : std_logic := '0';
variable count : integer := 1;
variable output_shift_count : integer := 1;
variable first_rising_edge : boolean := false;
begin
if (reset = '1') then
count := 1;
output_shift_count := 1;
tmp_cout := '0';
first_rising_edge := false;
elsif (clk'event) then
if (mode = " off") then
tmp_cout := '0';
elsif (mode = "bypass") then
tmp_cout := clk;
first_rising_edge := true;
elsif (not first_rising_edge) then
if (clk = '1') then
if (output_shift_count = initial) then
tmp_cout := clk;
first_rising_edge := true;
else
output_shift_count := output_shift_count + 1;
end if;
end if;
elsif (output_shift_count < initial) then
if (clk = '1') then
output_shift_count := output_shift_count + 1;
end if;
else
count := count + 1;
if (mode = " even" and (count = (high*2) + 1)) then
tmp_cout := '0';
elsif (mode = " odd" and (count = high*2)) then
tmp_cout := '0';
elsif (count = (high + low)*2 + 1) then
tmp_cout := '1';
count := 1; -- reset count
end if;
end if;
end if;
cout <= transport tmp_cout;
end process;
end behave;
--/////////////////////////////////////////////////////////////////////////////
--
-- Entity Name : cycloneiii_pll_reg
--
-- Description : Simulation model for a simple DFF.
-- This is required for the generation of the bit slip-signals.
-- No timing, powers upto 0.
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
ENTITY cycloneiii_pll_reg is
PORT( clk : in std_logic;
ena : in std_logic := '1';
d : in std_logic;
clrn : in std_logic := '1';
prn : in std_logic := '1';
q : out std_logic
);
end cycloneiii_pll_reg;
ARCHITECTURE behave of cycloneiii_pll_reg is
begin
process (clk, prn, clrn)
variable q_reg : std_logic := '0';
begin
if (prn = '0') then
q_reg := '1';
elsif (clrn = '0') then
q_reg := '0';
elsif (clk'event and clk = '1' and (ena = '1')) then
q_reg := D;
end if;
Q <= q_reg;
end process;
end behave;
--///////////////////////////////////////////////////////////////////////////
--
-- Entity Name : cycloneiii_pll
--
-- Description : Timing simulation model for the Cyclone III PLL.
-- In the functional mode, it is also the model for the altpll
-- megafunction.
--
-- Limitations : Does not support Spread Spectrum and Bandwidth.
--
-- Outputs : Up to 10 output clocks, each defined by its own set of
-- parameters. Locked output (active high) indicates when the
-- PLL locks. clkbad and activeclock are used for
-- clock switchover to indicate which input clock has gone
-- bad, when the clock switchover initiates and which input
-- clock is being used as the reference, respectively.
-- scandataout is the data output of the serial scan chain.
--
--///////////////////////////////////////////////////////////////////////////
LIBRARY IEEE, std;
USE IEEE.std_logic_1164.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE STD.TEXTIO.all;
USE work.cycloneiii_atom_pack.all;
USE work.cycloneiii_pllpack.all;
USE work.cycloneiii_mn_cntr;
USE work.cycloneiii_scale_cntr;
USE work.cycloneiii_dffe;
USE work.cycloneiii_pll_reg;
-- New Features : The list below outlines key new features in CYCLONEIII:
-- 1. Dynamic Phase Reconfiguration
-- 2. Dynamic PLL Reconfiguration (different protocol)
-- 3. More output counters
ENTITY cycloneiii_pll is
GENERIC (
operation_mode : string := "normal";
pll_type : string := "auto"; -- AUTO/FAST/ENHANCED/LEFT_RIGHT/TOP_BOTTOM
compensate_clock : string := "clock0";
inclk0_input_frequency : integer := 0;
inclk1_input_frequency : integer := 0;
self_reset_on_loss_lock : string := "off";
switch_over_type : string := "auto";
switch_over_counter : integer := 1;
enable_switch_over_counter : string := "off";
bandwidth : integer := 0;
bandwidth_type : string := "auto";
use_dc_coupling : string := "false";
lock_c : integer := 4;
sim_gate_lock_device_behavior : string := "off";
lock_high : integer := 0;
lock_low : integer := 0;
lock_window_ui : string := "0.05";
lock_window : time := 5 ps;
test_bypass_lock_detect : string := "off";
clk0_output_frequency : integer := 0;
clk0_multiply_by : integer := 0;
clk0_divide_by : integer := 0;
clk0_phase_shift : string := "0";
clk0_duty_cycle : integer := 50;
clk1_output_frequency : integer := 0;
clk1_multiply_by : integer := 0;
clk1_divide_by : integer := 0;
clk1_phase_shift : string := "0";
clk1_duty_cycle : integer := 50;
clk2_output_frequency : integer := 0;
clk2_multiply_by : integer := 0;
clk2_divide_by : integer := 0;
clk2_phase_shift : string := "0";
clk2_duty_cycle : integer := 50;
clk3_output_frequency : integer := 0;
clk3_multiply_by : integer := 0;
clk3_divide_by : integer := 0;
clk3_phase_shift : string := "0";
clk3_duty_cycle : integer := 50;
clk4_output_frequency : integer := 0;
clk4_multiply_by : integer := 0;
clk4_divide_by : integer := 0;
clk4_phase_shift : string := "0";
clk4_duty_cycle : integer := 50;
pfd_min : integer := 0;
pfd_max : integer := 0;
vco_min : integer := 0;
vco_max : integer := 0;
vco_center : integer := 0;
-- ADVANCED USER PARAMETERS
m_initial : integer := 1;
m : integer := 0;
n : integer := 1;
c0_high : integer := 1;
c0_low : integer := 1;
c0_initial : integer := 1;
c0_mode : string := "bypass";
c0_ph : integer := 0;
c1_high : integer := 1;
c1_low : integer := 1;
c1_initial : integer := 1;
c1_mode : string := "bypass";
c1_ph : integer := 0;
c2_high : integer := 1;
c2_low : integer := 1;
c2_initial : integer := 1;
c2_mode : string := "bypass";
c2_ph : integer := 0;
c3_high : integer := 1;
c3_low : integer := 1;
c3_initial : integer := 1;
c3_mode : string := "bypass";
c3_ph : integer := 0;
c4_high : integer := 1;
c4_low : integer := 1;
c4_initial : integer := 1;
c4_mode : string := "bypass";
c4_ph : integer := 0;
m_ph : integer := 0;
clk0_counter : string := "unused";
clk1_counter : string := "unused";
clk2_counter : string := "unused";
clk3_counter : string := "unused";
clk4_counter : string := "unused";
c1_use_casc_in : string := "off";
c2_use_casc_in : string := "off";
c3_use_casc_in : string := "off";
c4_use_casc_in : string := "off";
m_test_source : integer := -1;
c0_test_source : integer := -1;
c1_test_source : integer := -1;
c2_test_source : integer := -1;
c3_test_source : integer := -1;
c4_test_source : integer := -1;
vco_multiply_by : integer := 0;
vco_divide_by : integer := 0;
vco_post_scale : integer := 1;
vco_frequency_control : string := "auto";
vco_phase_shift_step : integer := 0;
charge_pump_current : integer := 10;
loop_filter_r : string := " 1.0";
loop_filter_c : integer := 0;
pll_compensation_delay : integer := 0;
simulation_type : string := "functional";
lpm_type : string := "cycloneiii_pll";
clk0_use_even_counter_mode : string := "off";
clk1_use_even_counter_mode : string := "off";
clk2_use_even_counter_mode : string := "off";
clk3_use_even_counter_mode : string := "off";
clk4_use_even_counter_mode : string := "off";
clk0_use_even_counter_value : string := "off";
clk1_use_even_counter_value : string := "off";
clk2_use_even_counter_value : string := "off";
clk3_use_even_counter_value : string := "off";
clk4_use_even_counter_value : string := "off";
-- Test only
init_block_reset_a_count : integer := 1;
init_block_reset_b_count : integer := 1;
charge_pump_current_bits : integer := 0;
lock_window_ui_bits : integer := 0;
loop_filter_c_bits : integer := 0;
loop_filter_r_bits : integer := 0;
test_counter_c0_delay_chain_bits : integer := 0;
test_counter_c1_delay_chain_bits : integer := 0;
test_counter_c2_delay_chain_bits : integer := 0;
test_counter_c3_delay_chain_bits : integer := 0;
test_counter_c4_delay_chain_bits : integer := 0;
test_counter_c5_delay_chain_bits : integer := 0;
test_counter_m_delay_chain_bits : integer := 0;
test_counter_n_delay_chain_bits : integer := 0;
test_feedback_comp_delay_chain_bits : integer := 0;
test_input_comp_delay_chain_bits : integer := 0;
test_volt_reg_output_mode_bits : integer := 0;
test_volt_reg_output_voltage_bits : integer := 0;
test_volt_reg_test_mode : string := "false";
vco_range_detector_high_bits : integer := -1;
vco_range_detector_low_bits : integer := -1;
scan_chain_mif_file : string := "";
auto_settings : string := "true";
-- Simulation only generics
family_name : string := "Cyclone III";
-- VITAL generics
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
TimingChecksOn : Boolean := true;
InstancePath : STRING := "*";
tipd_inclk : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01);
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_pfdena : VitalDelayType01 := DefPropDelay01;
tipd_areset : VitalDelayType01 := DefPropDelay01;
tipd_fbin : VitalDelayType01 := DefPropDelay01;
tipd_scanclk : VitalDelayType01 := DefPropDelay01;
tipd_scanclkena : VitalDelayType01 := DefPropDelay01;
tipd_scandata : VitalDelayType01 := DefPropDelay01;
tipd_configupdate : VitalDelayType01 := DefPropDelay01;
tipd_clkswitch : VitalDelayType01 := DefPropDelay01;
tipd_phaseupdown : VitalDelayType01 := DefPropDelay01;
tipd_phasecounterselect : VitalDelayArrayType01(2 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_phasestep : VitalDelayType01 := DefPropDelay01;
tsetup_scandata_scanclk_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
thold_scandata_scanclk_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
tsetup_scanclkena_scanclk_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
thold_scanclkena_scanclk_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
use_vco_bypass : string := "false"
);
PORT
(
inclk : in std_logic_vector(1 downto 0);
fbin : in std_logic := '0';
fbout : out std_logic;
clkswitch : in std_logic := '0';
areset : in std_logic := '0';
pfdena : in std_logic := '1';
scandata : in std_logic := '0';
scanclk : in std_logic := '0';
scanclkena : in std_logic := '1';
configupdate : in std_logic := '0';
clk : out std_logic_vector(4 downto 0);
phasecounterselect : in std_logic_vector(2 downto 0) := "000";
phaseupdown : in std_logic := '0';
phasestep : in std_logic := '0';
clkbad : out std_logic_vector(1 downto 0);
activeclock : out std_logic;
locked : out std_logic;
scandataout : out std_logic;
scandone : out std_logic;
phasedone : out std_logic;
vcooverrange : out std_logic;
vcounderrange : out std_logic
);
END cycloneiii_pll;
ARCHITECTURE vital_pll of cycloneiii_pll is
function get_vco_min_no_division(i_vco_post_scale : INTEGER) return INTEGER is
begin
if (i_vco_post_scale = 1) then
return vco_min * 2;
else
return vco_min;
end if;
end;
function get_vco_max_no_division(i_vco_post_scale : INTEGER) return INTEGER is
begin
if (i_vco_post_scale = 1) then
return vco_max * 2;
else
return vco_max;
end if;
end;
TYPE int_array is ARRAY(NATURAL RANGE <>) of integer;
TYPE str_array is ARRAY(NATURAL RANGE <>) of string(1 to 6);
TYPE str_array1 is ARRAY(NATURAL RANGE <>) of string(1 to 9);
TYPE std_logic_array is ARRAY(NATURAL RANGE <>) of std_logic;
constant VCO_MIN_NO_DIVISION : integer := get_vco_min_no_division(vco_post_scale);
constant VCO_MAX_NO_DIVISION : integer := get_vco_max_no_division(vco_post_scale);
-- internal advanced parameter signals
signal i_vco_min : integer := vco_min;
signal i_vco_max : integer := vco_max;
signal i_vco_center : integer;
signal i_pfd_min : integer;
signal i_pfd_max : integer;
signal c_ph_val : int_array(0 to 4) := (OTHERS => 0);
signal c_ph_val_tmp : int_array(0 to 4) := (OTHERS => 0);
signal c_high_val : int_array(0 to 4) := (OTHERS => 1);
signal c_low_val : int_array(0 to 4) := (OTHERS => 1);
signal c_initial_val : int_array(0 to 4) := (OTHERS => 1);
signal c_mode_val : str_array(0 to 4);
signal clk_num : str_array(0 to 4);
-- old values
signal c_high_val_old : int_array(0 to 4) := (OTHERS => 1);
signal c_low_val_old : int_array(0 to 4) := (OTHERS => 1);
signal c_ph_val_old : int_array(0 to 4) := (OTHERS => 0);
signal c_mode_val_old : str_array(0 to 4);
-- hold registers
signal c_high_val_hold : int_array(0 to 4) := (OTHERS => 1);
signal c_low_val_hold : int_array(0 to 4) := (OTHERS => 1);
signal c_ph_val_hold : int_array(0 to 4) := (OTHERS => 0);
signal c_mode_val_hold : str_array(0 to 4);
-- temp registers
signal sig_c_ph_val_tmp : int_array(0 to 4) := (OTHERS => 0);
signal c_ph_val_orig : int_array(0 to 4) := (OTHERS => 0);
signal real_lock_high : integer := 0;
signal i_clk4_counter : integer := 4;
signal i_clk3_counter : integer := 3;
signal i_clk2_counter : integer := 2;
signal i_clk1_counter : integer := 1;
signal i_clk0_counter : integer := 0;
signal i_charge_pump_current : integer;
signal i_loop_filter_r : integer;
-- end internal advanced parameter signals
-- CONSTANTS
CONSTANT SCAN_CHAIN : integer := 144;
CONSTANT GPP_SCAN_CHAIN : integer := 234;
CONSTANT FAST_SCAN_CHAIN : integer := 180;
CONSTANT cntrs : str_array(4 downto 0) := (" C4", " C3", " C2", " C1", " C0");
CONSTANT ss_cntrs : str_array(0 to 3) := (" M", " M2", " N", " N2");
CONSTANT loop_filter_c_arr : int_array(0 to 3) := (0,0,0,0);
CONSTANT fpll_loop_filter_c_arr : int_array(0 to 3) := (0,0,0,0);
CONSTANT charge_pump_curr_arr : int_array(0 to 15) := (0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0);
CONSTANT num_phase_taps : integer := 8;
-- signals
signal vcc : std_logic := '1';
signal fbclk : std_logic;
signal refclk : std_logic;
signal vco_over : std_logic := '0';
signal vco_under : std_logic := '1';
signal pll_locked : boolean := false;
signal c_clk : std_logic_array(0 to 4);
signal vco_out : std_logic_vector(7 downto 0) := (OTHERS => '0');
-- signals to assign values to counter params
signal m_val : integer := 1;
signal n_val : integer := 1;
signal m_ph_val : integer := 0;
signal m_ph_initial : integer := 0;
signal m_ph_val_tmp : integer := 0;
signal m_initial_val : integer := m_initial;
signal m_mode_val : string(1 to 6) := " ";
signal n_mode_val : string(1 to 6) := " ";
signal lfc_val : integer := 0;
signal vco_cur : integer := vco_post_scale;
signal cp_curr_val : integer := 0;
signal lfr_val : string(1 to 2) := " ";
signal cp_curr_old_bit_setting : integer := charge_pump_current_bits;
signal cp_curr_val_bit_setting : std_logic_vector(2 downto 0) := (OTHERS => '0');
signal lfr_old_bit_setting : integer := loop_filter_r_bits;
signal lfr_val_bit_setting : std_logic_vector(4 downto 0) := (OTHERS => '0');
signal lfc_old_bit_setting : integer := loop_filter_c_bits;
signal lfc_val_bit_setting : std_logic_vector(1 downto 0) := (OTHERS => '0');
signal pll_reconfig_display_full_setting : boolean := FALSE; -- display full setting, change to true
-- old values
signal m_val_old : integer := 1;
signal n_val_old : integer := 1;
signal m_mode_val_old : string(1 to 6) := " ";
signal n_mode_val_old : string(1 to 6) := " ";
signal m_ph_val_old : integer := 0;
signal lfc_old : integer := 0;
signal vco_old : integer := 0;
signal cp_curr_old : integer := 0;
signal lfr_old : string(1 to 2) := " ";
signal num_output_cntrs : integer := 5;
signal scanclk_period : time := 1 ps;
signal scan_data : std_logic_vector(0 to 143) := (OTHERS => '0');
signal clk_pfd : std_logic_vector(0 to 4);
signal clk0_tmp : std_logic;
signal clk1_tmp : std_logic;
signal clk2_tmp : std_logic;
signal clk3_tmp : std_logic;
signal clk4_tmp : std_logic;
signal update_conf_latches : std_logic := '0';
signal update_conf_latches_reg : std_logic := '0';
signal clkin : std_logic := '0';
signal gate_locked : std_logic := '0';
signal pfd_locked : std_logic := '0';
signal lock : std_logic := '0';
signal about_to_lock : boolean := false;
signal reconfig_err : boolean := false;
signal inclk_c0 : std_logic;
signal inclk_c1 : std_logic;
signal inclk_c2 : std_logic;
signal inclk_c3 : std_logic;
signal inclk_c4 : std_logic;
signal inclk_m : std_logic;
signal devpor : std_logic;
signal devclrn : std_logic;
signal inclk0_ipd : std_logic;
signal inclk1_ipd : std_logic;
signal pfdena_ipd : std_logic;
signal areset_ipd : std_logic;
signal fbin_ipd : std_logic;
signal scanclk_ipd : std_logic;
signal scanclkena_ipd, scanclkena_reg : std_logic;
signal scandata_ipd : std_logic;
signal clkswitch_ipd : std_logic;
signal phasecounterselect_ipd : std_logic_vector(2 downto 0);
signal phaseupdown_ipd : std_logic;
signal phasestep_ipd : std_logic;
signal configupdate_ipd : std_logic;
-- registered signals
signal sig_offset : time := 0 ps;
signal sig_refclk_time : time := 0 ps;
signal sig_fbclk_period : time := 0 ps;
signal sig_vco_period_was_phase_adjusted : boolean := false;
signal sig_phase_adjust_was_scheduled : boolean := false;
signal sig_stop_vco : std_logic := '0';
signal sig_m_times_vco_period : time := 0 ps;
signal sig_new_m_times_vco_period : time := 0 ps;
signal sig_got_refclk_posedge : boolean := false;
signal sig_got_fbclk_posedge : boolean := false;
signal sig_got_second_refclk : boolean := false;
signal m_delay : integer := 0;
signal n_delay : integer := 0;
signal inclk1_tmp : std_logic := '0';
signal reset_low : std_logic := '0';
-- Phase Reconfig
SIGNAL phasecounterselect_reg : std_logic_vector(2 DOWNTO 0);
SIGNAL phaseupdown_reg : std_logic := '0';
SIGNAL phasestep_reg : std_logic := '0';
SIGNAL phasestep_high_count : integer := 0;
SIGNAL update_phase : std_logic := '0';
signal scandataout_tmp : std_logic := '0';
signal scandata_in : std_logic := '0';
signal scandata_out : std_logic := '0';
signal scandone_tmp : std_logic := '1';
signal initiate_reconfig : std_logic := '0';
signal sig_refclk_period : time := (inclk0_input_frequency * 1 ps) * n;
signal schedule_vco : std_logic := '0';
signal areset_ena_sig : std_logic := '0';
signal pll_in_test_mode : boolean := false;
signal pll_has_just_been_reconfigured : boolean := false;
signal inclk_c_from_vco : std_logic_array(0 to 4);
signal inclk_m_from_vco : std_logic;
SIGNAL inclk0_period : time := 0 ps;
SIGNAL last_inclk0_period : time := 0 ps;
SIGNAL last_inclk0_edge : time := 0 ps;
SIGNAL first_inclk0_edge_detect : STD_LOGIC := '0';
SIGNAL inclk1_period : time := 0 ps;
SIGNAL last_inclk1_period : time := 0 ps;
SIGNAL last_inclk1_edge : time := 0 ps;
SIGNAL first_inclk1_edge_detect : STD_LOGIC := '0';
COMPONENT cycloneiii_mn_cntr
PORT (
clk : IN std_logic;
reset : IN std_logic := '0';
cout : OUT std_logic;
initial_value : IN integer := 1;
modulus : IN integer := 1;
time_delay : IN integer := 0
);
END COMPONENT;
COMPONENT cycloneiii_scale_cntr
PORT (
clk : IN std_logic;
reset : IN std_logic := '0';
cout : OUT std_logic;
initial : IN integer := 1;
high : IN integer := 1;
low : IN integer := 1;
mode : IN string := "bypass";
ph_tap : IN integer := 0
);
END COMPONENT;
COMPONENT cycloneiii_dffe
GENERIC(
TimingChecksOn: Boolean := true;
InstancePath: STRING := "*";
XOn: Boolean := DefGlitchXOn;
MsgOn: Boolean := DefGlitchMsgOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
tpd_PRN_Q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_CLRN_Q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_CLK_Q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_ENA_Q_posedge : VitalDelayType01 := DefPropDelay01;
tsetup_D_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_D_CLK_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ENA_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_D_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_D_CLK_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
thold_ENA_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tipd_D : VitalDelayType01 := DefPropDelay01;
tipd_CLRN : VitalDelayType01 := DefPropDelay01;
tipd_PRN : VitalDelayType01 := DefPropDelay01;
tipd_CLK : VitalDelayType01 := DefPropDelay01;
tipd_ENA : VitalDelayType01 := DefPropDelay01);
PORT(
Q : out STD_LOGIC := '0';
D : in STD_LOGIC := '1';
CLRN : in STD_LOGIC := '1';
PRN : in STD_LOGIC := '1';
CLK : in STD_LOGIC := '0';
ENA : in STD_LOGIC := '1');
END COMPONENT;
COMPONENT cycloneiii_pll_reg
PORT(
Q : out STD_LOGIC := '0';
D : in STD_LOGIC := '1';
CLRN : in STD_LOGIC := '1';
PRN : in STD_LOGIC := '1';
CLK : in STD_LOGIC := '0';
ENA : in STD_LOGIC := '1');
END COMPONENT;
begin
----------------------
-- INPUT PATH DELAYs
----------------------
WireDelay : block
begin
VitalWireDelay (inclk0_ipd, inclk(0), tipd_inclk(0));
VitalWireDelay (inclk1_ipd, inclk(1), tipd_inclk(1));
VitalWireDelay (areset_ipd, areset, tipd_areset);
VitalWireDelay (pfdena_ipd, pfdena, tipd_pfdena);
VitalWireDelay (scanclk_ipd, scanclk, tipd_scanclk);
VitalWireDelay (scanclkena_ipd, scanclkena, tipd_scanclkena);
VitalWireDelay (scandata_ipd, scandata, tipd_scandata);
VitalWireDelay (configupdate_ipd, configupdate, tipd_configupdate);
VitalWireDelay (clkswitch_ipd, clkswitch, tipd_clkswitch);
VitalWireDelay (phaseupdown_ipd, phaseupdown, tipd_phaseupdown);
VitalWireDelay (phasestep_ipd, phasestep, tipd_phasestep);
VitalWireDelay (phasecounterselect_ipd(0), phasecounterselect(0), tipd_phasecounterselect(0));
VitalWireDelay (phasecounterselect_ipd(1), phasecounterselect(1), tipd_phasecounterselect(1));
VitalWireDelay (phasecounterselect_ipd(2), phasecounterselect(2), tipd_phasecounterselect(2));
end block;
inclk_m <= fbclk when m_test_source = 0 else
refclk when m_test_source = 1 else
inclk_m_from_vco;
areset_ena_sig <= areset_ipd or sig_stop_vco;
pll_in_test_mode <= true when (m_test_source /= -1 or c0_test_source /= -1 or
c1_test_source /= -1 or c2_test_source /= -1 or
c3_test_source /= -1 or c4_test_source /= -1)
else false;
real_lock_high <= lock_high WHEN (sim_gate_lock_device_behavior = "on") ELSE 0;
m1 : cycloneiii_mn_cntr
port map ( clk => inclk_m,
reset => areset_ena_sig,
cout => fbclk,
initial_value => m_initial_val,
modulus => m_val,
time_delay => m_delay
);
-- add delta delay to inclk1 to ensure inclk0 and inclk1 are processed
-- in different simulation deltas.
inclk1_tmp <= inclk1_ipd;
-- Calculate the inclk0 period
PROCESS
VARIABLE inclk0_period_tmp : time := 0 ps;
BEGIN
WAIT UNTIL (inclk0_ipd'EVENT AND inclk0_ipd = '1');
IF (first_inclk0_edge_detect = '0') THEN
first_inclk0_edge_detect <= '1';
ELSE
last_inclk0_period <= inclk0_period;
inclk0_period_tmp := NOW - last_inclk0_edge;
END IF;
last_inclk0_edge <= NOW;
inclk0_period <= inclk0_period_tmp;
END PROCESS;
-- Calculate the inclk1 period
PROCESS
VARIABLE inclk1_period_tmp : time := 0 ps;
BEGIN
WAIT UNTIL (inclk1_ipd'EVENT AND inclk1_ipd = '1');
IF (first_inclk1_edge_detect = '0') THEN
first_inclk1_edge_detect <= '1';
ELSE
last_inclk1_period <= inclk1_period;
inclk1_period_tmp := NOW - last_inclk1_edge;
END IF;
last_inclk1_edge <= NOW;
inclk1_period <= inclk1_period_tmp;
END PROCESS;
process (inclk0_ipd, inclk1_tmp, clkswitch_ipd)
variable input_value : std_logic := '0';
variable current_clock : integer := 0;
variable clk0_count, clk1_count : integer := 0;
variable clk0_is_bad, clk1_is_bad : std_logic := '0';
variable primary_clk_is_bad : boolean := false;
variable current_clk_is_bad : boolean := false;
variable got_curr_clk_falling_edge_after_clkswitch : boolean := false;
variable switch_over_count : integer := 0;
variable active_clock : std_logic := '0';
variable external_switch : boolean := false;
variable diff_percent_period : integer := 0;
variable buf : line;
variable switch_clock : boolean := false;
begin
if (now = 0 ps) then
if (switch_over_type = "manual" and clkswitch_ipd = '1') then
current_clock := 1;
active_clock := '1';
end if;
end if;
if (clkswitch_ipd'event and clkswitch_ipd = '1' and switch_over_type = "auto") then
external_switch := true;
elsif (switch_over_type = "manual") then
if (clkswitch_ipd'event and clkswitch_ipd = '1') then
switch_clock := true;
elsif (clkswitch_ipd'event and clkswitch_ipd = '0') then
switch_clock := false;
end if;
end if;
if (switch_clock = true) then
if (inclk0_ipd'event or inclk1_tmp'event) then
if (current_clock = 0) then
current_clock := 1;
active_clock := '1';
clkin <= transport inclk1_tmp;
elsif (current_clock = 1) then
current_clock := 0;
active_clock := '0';
clkin <= transport inclk0_ipd;
end if;
switch_clock := false;
end if;
end if;
-- save the current inclk event value
if (inclk0_ipd'event) then
input_value := inclk0_ipd;
elsif (inclk1_tmp'event) then
input_value := inclk1_tmp;
end if;
-- check if either input clk is bad
if (inclk0_ipd'event and inclk0_ipd = '1') then
clk0_count := clk0_count + 1;
clk0_is_bad := '0';
clk1_count := 0;
if (clk0_count > 2) then
-- no event on other clk for 2 cycles
clk1_is_bad := '1';
if (current_clock = 1) then
current_clk_is_bad := true;
end if;
end if;
end if;
if (inclk1_tmp'event and inclk1_tmp = '1') then
clk1_count := clk1_count + 1;
clk1_is_bad := '0';
clk0_count := 0;
if (clk1_count > 2) then
-- no event on other clk for 2 cycles
clk0_is_bad := '1';
if (current_clock = 0) then
current_clk_is_bad := true;
end if;
end if;
end if;
-- check if the bad clk is the primary clock
if (clk0_is_bad = '1') then
primary_clk_is_bad := true;
else
primary_clk_is_bad := false;
end if;
-- actual switching
if (inclk0_ipd'event and current_clock = 0) then
if (external_switch) then
if (not got_curr_clk_falling_edge_after_clkswitch) then
if (inclk0_ipd = '0') then
got_curr_clk_falling_edge_after_clkswitch := true;
end if;
clkin <= transport inclk0_ipd;
end if;
else
clkin <= transport inclk0_ipd;
end if;
elsif (inclk1_tmp'event and current_clock = 1) then
if (external_switch) then
if (not got_curr_clk_falling_edge_after_clkswitch) then
if (inclk1_tmp = '0') then
got_curr_clk_falling_edge_after_clkswitch := true;
end if;
clkin <= transport inclk1_tmp;
end if;
else
clkin <= transport inclk1_tmp;
end if;
else
if (input_value = '1' and enable_switch_over_counter = "on" and primary_clk_is_bad) then
switch_over_count := switch_over_count + 1;
end if;
if ((input_value = '0')) then
if (external_switch and (got_curr_clk_falling_edge_after_clkswitch or current_clk_is_bad)) or (primary_clk_is_bad and clkswitch_ipd /= '1' and (enable_switch_over_counter = "off" or switch_over_count = switch_over_counter)) then
got_curr_clk_falling_edge_after_clkswitch := false;
if (areset_ipd = '0') then
if ((inclk0_period > inclk1_period) and (inclk1_period /= 0 ps)) then
diff_percent_period := (( inclk0_period - inclk1_period ) * 100) / inclk1_period;
elsif (inclk0_period /= 0 ps) then
diff_percent_period := (( inclk1_period - inclk0_period ) * 100) / inclk0_period;
end if;
if((diff_percent_period > 20)and ( switch_over_type = "auto")) then
WRITE(buf,string'("Warning : The input clock frequencies specified for the specified PLL are too far apart for auto-switch-over feature to work properly. Please make sure that the clock frequencies are 20 percent apart for correct functionality."));
writeline(output, buf);
end if;
end if;
if (current_clock = 0) then
current_clock := 1;
else
current_clock := 0;
end if;
active_clock := not active_clock;
switch_over_count := 0;
external_switch := false;
current_clk_is_bad := false;
else
if(switch_over_type = "auto") then
if(current_clock = 0 and clk0_is_bad = '1' and clk1_is_bad = '0' ) then
current_clock := 1;
active_clock := not active_clock;
end if;
if(current_clock = 1 and clk0_is_bad = '0' and clk1_is_bad = '1' ) then
current_clock := 0;
active_clock := not active_clock;
end if;
end if;
end if;
end if;
end if;
-- schedule outputs
clkbad(0) <= clk0_is_bad;
clkbad(1) <= clk1_is_bad;
activeclock <= active_clock;
end process;
n1 : cycloneiii_mn_cntr
port map (
clk => clkin,
reset => areset_ipd,
cout => refclk,
initial_value => n_val,
modulus => n_val);
inclk_c0 <= refclk when c0_test_source = 1 else
fbclk when c0_test_source = 0 else
inclk_c_from_vco(0);
c0 : cycloneiii_scale_cntr
port map (
clk => inclk_c0,
reset => areset_ena_sig,
cout => c_clk(0),
initial => c_initial_val(0),
high => c_high_val(0),
low => c_low_val(0),
mode => c_mode_val(0),
ph_tap => c_ph_val(0));
inclk_c1 <= refclk when c1_test_source = 1 else
fbclk when c1_test_source = 0 else
c_clk(0) when c1_use_casc_in = "on" else
inclk_c_from_vco(1);
c1 : cycloneiii_scale_cntr
port map (
clk => inclk_c1,
reset => areset_ena_sig,
cout => c_clk(1),
initial => c_initial_val(1),
high => c_high_val(1),
low => c_low_val(1),
mode => c_mode_val(1),
ph_tap => c_ph_val(1));
inclk_c2 <= refclk when c2_test_source = 1 else
fbclk when c2_test_source = 0 else
c_clk(1) when c2_use_casc_in = "on" else
inclk_c_from_vco(2);
c2 : cycloneiii_scale_cntr
port map (
clk => inclk_c2,
reset => areset_ena_sig,
cout => c_clk(2),
initial => c_initial_val(2),
high => c_high_val(2),
low => c_low_val(2),
mode => c_mode_val(2),
ph_tap => c_ph_val(2));
inclk_c3 <= refclk when c3_test_source = 1 else
fbclk when c3_test_source = 0 else
c_clk(2) when c3_use_casc_in = "on" else
inclk_c_from_vco(3);
c3 : cycloneiii_scale_cntr
port map (
clk => inclk_c3,
reset => areset_ena_sig,
cout => c_clk(3),
initial => c_initial_val(3),
high => c_high_val(3),
low => c_low_val(3),
mode => c_mode_val(3),
ph_tap => c_ph_val(3));
inclk_c4 <= refclk when c4_test_source = 1 else
fbclk when c4_test_source = 0 else
c_clk(3) when (c4_use_casc_in = "on") else
inclk_c_from_vco(4);
c4 : cycloneiii_scale_cntr
port map (
clk => inclk_c4,
reset => areset_ena_sig,
cout => c_clk(4),
initial => c_initial_val(4),
high => c_high_val(4),
low => c_low_val(4),
mode => c_mode_val(4),
ph_tap => c_ph_val(4));
process(scandone_tmp, lock)
begin
if (scandone_tmp'event and (scandone_tmp = '1')) then
pll_has_just_been_reconfigured <= true;
elsif (lock'event and (lock = '1')) then
pll_has_just_been_reconfigured <= false;
end if;
end process;
process(inclk_c0, inclk_c1, areset_ipd, sig_stop_vco)
variable c0_got_first_rising_edge : boolean := false;
variable c0_count : integer := 2;
variable c0_initial_count : integer := 1;
variable c0_tmp, c1_tmp : std_logic := '0';
variable c1_got_first_rising_edge : boolean := false;
variable c1_count : integer := 2;
variable c1_initial_count : integer := 1;
begin
if (areset_ipd = '1' or sig_stop_vco = '1') then
c0_count := 2;
c1_count := 2;
c0_initial_count := 1;
c1_initial_count := 1;
c0_got_first_rising_edge := false;
c1_got_first_rising_edge := false;
else
if (not c0_got_first_rising_edge) then
if (inclk_c0'event and inclk_c0 = '1') then
if (c0_initial_count = c_initial_val(0)) then
c0_got_first_rising_edge := true;
else
c0_initial_count := c0_initial_count + 1;
end if;
end if;
elsif (inclk_c0'event) then
c0_count := c0_count + 1;
if (c0_count = (c_high_val(0) + c_low_val(0)) * 2) then
c0_count := 1;
end if;
end if;
if (inclk_c0'event and inclk_c0 = '0') then
if (c0_count = 1) then
c0_tmp := '1';
c0_got_first_rising_edge := false;
else
c0_tmp := '0';
end if;
end if;
if (not c1_got_first_rising_edge) then
if (inclk_c1'event and inclk_c1 = '1') then
if (c1_initial_count = c_initial_val(1)) then
c1_got_first_rising_edge := true;
else
c1_initial_count := c1_initial_count + 1;
end if;
end if;
elsif (inclk_c1'event) then
c1_count := c1_count + 1;
if (c1_count = (c_high_val(1) + c_low_val(1)) * 2) then
c1_count := 1;
end if;
end if;
if (inclk_c1'event and inclk_c1 = '0') then
if (c1_count = 1) then
c1_tmp := '1';
c1_got_first_rising_edge := false;
else
c1_tmp := '0';
end if;
end if;
end if;
end process;
locked <= pfd_locked WHEN (test_bypass_lock_detect = "on") ELSE
lock;
process (scandone_tmp)
variable buf : line;
begin
if (scandone_tmp'event and scandone_tmp = '1') then
if (reconfig_err = false) then
ASSERT false REPORT "PLL Reprogramming completed with the following values (Values in parantheses indicate values before reprogramming) :" severity note;
write (buf, string'(" N modulus = "));
write (buf, n_val);
write (buf, string'(" ( "));
write (buf, n_val_old);
write (buf, string'(" )"));
writeline (output, buf);
write (buf, string'(" M modulus = "));
write (buf, m_val);
write (buf, string'(" ( "));
write (buf, m_val_old);
write (buf, string'(" )"));
writeline (output, buf);
write (buf, string'(" M ph_tap = "));
write (buf, m_ph_val);
write (buf, string'(" ( "));
write (buf, m_ph_val_old);
write (buf, string'(" )"));
writeline (output, buf);
for i in 0 to (num_output_cntrs-1) loop
write (buf, clk_num(i));
write (buf, string'(" : "));
write (buf, cntrs(i));
write (buf, string'(" : high = "));
write (buf, c_high_val(i));
write (buf, string'(" ("));
write (buf, c_high_val_old(i));
write (buf, string'(") "));
write (buf, string'(" , low = "));
write (buf, c_low_val(i));
write (buf, string'(" ("));
write (buf, c_low_val_old(i));
write (buf, string'(") "));
write (buf, string'(" , mode = "));
write (buf, c_mode_val(i));
write (buf, string'(" ("));
write (buf, c_mode_val_old(i));
write (buf, string'(") "));
write (buf, string'(" , phase tap = "));
write (buf, c_ph_val(i));
write (buf, string'(" ("));
write (buf, c_ph_val_old(i));
write (buf, string'(") "));
writeline(output, buf);
end loop;
IF (pll_reconfig_display_full_setting) THEN
write (buf, string'(" Charge Pump Current (uA) = "));
write (buf, cp_curr_val);
write (buf, string'(" ( "));
write (buf, cp_curr_old);
write (buf, string'(" ) "));
writeline (output, buf);
write (buf, string'(" Loop Filter Capacitor (pF) = "));
write (buf, lfc_val);
write (buf, string'(" ( "));
write (buf, lfc_old);
write (buf, string'(" ) "));
writeline (output, buf);
write (buf, string'(" Loop Filter Resistor (Kohm) = "));
write (buf, lfr_val);
write (buf, string'(" ( "));
write (buf, lfr_old);
write (buf, string'(" ) "));
writeline (output, buf);
write (buf, string'(" VCO_Post_Scale = "));
write (buf, vco_cur);
write (buf, string'(" ( "));
write (buf, vco_old);
write (buf, string'(" ) "));
writeline (output, buf);
ELSE
write (buf, string'(" Charge Pump Current (bit setting) = "));
write (buf, alt_conv_integer(cp_curr_val_bit_setting));
write (buf, string'(" ( "));
write (buf, cp_curr_old_bit_setting);
write (buf, string'(" ) "));
writeline (output, buf);
write (buf, string'(" Loop Filter Capacitor (bit setting) = "));
write (buf, alt_conv_integer(lfc_val_bit_setting));
write (buf, string'(" ( "));
write (buf, lfc_old_bit_setting);
write (buf, string'(" ) "));
writeline (output, buf);
write (buf, string'(" Loop Filter Resistor (bit setting) = "));
write (buf, alt_conv_integer(lfr_val_bit_setting));
write (buf, string'(" ( "));
write (buf, lfr_old_bit_setting);
write (buf, string'(" ) "));
writeline (output, buf);
write (buf, string'(" VCO_Post_Scale = "));
write (buf, vco_cur);
write (buf, string'(" ( "));
write (buf, vco_old);
write (buf, string'(" ) "));
writeline (output, buf);
END IF;
cp_curr_old_bit_setting <= alt_conv_integer(cp_curr_val_bit_setting);
lfc_old_bit_setting <= alt_conv_integer(lfc_val_bit_setting);
lfr_old_bit_setting <= alt_conv_integer(lfr_val_bit_setting);
else ASSERT false REPORT "Errors were encountered during PLL reprogramming. Please refer to error/warning messages above." severity warning;
end if;
end if;
end process;
update_conf_latches <= configupdate_ipd;
process (scandone_tmp,areset_ipd,update_conf_latches, c_clk(0), c_clk(1), c_clk(2), c_clk(3), c_clk(4), vco_out, fbclk, scanclk_ipd)
variable init : boolean := true;
variable low, high : std_logic_vector(7 downto 0);
variable low_fast, high_fast : std_logic_vector(3 downto 0);
variable mode : string(1 to 6) := "bypass";
variable is_error : boolean := false;
variable m_tmp, n_tmp : std_logic_vector(8 downto 0);
variable lfr_val_tmp : string(1 to 2) := " ";
variable c_high_val_tmp,c_hval : int_array(0 to 4) := (OTHERS => 1);
variable c_low_val_tmp,c_lval : int_array(0 to 4) := (OTHERS => 1);
variable c_mode_val_tmp : str_array(0 to 4);
variable m_val_tmp : integer := 0;
variable c0_rising_edge_transfer_done : boolean := false;
variable c1_rising_edge_transfer_done : boolean := false;
variable c2_rising_edge_transfer_done : boolean := false;
variable c3_rising_edge_transfer_done : boolean := false;
variable c4_rising_edge_transfer_done : boolean := false;
-- variables for scaling of multiply_by and divide_by values
variable i_clk0_mult_by : integer := 1;
variable i_clk0_div_by : integer := 1;
variable i_clk1_mult_by : integer := 1;
variable i_clk1_div_by : integer := 1;
variable i_clk2_mult_by : integer := 1;
variable i_clk2_div_by : integer := 1;
variable i_clk3_mult_by : integer := 1;
variable i_clk3_div_by : integer := 1;
variable i_clk4_mult_by : integer := 1;
variable i_clk4_div_by : integer := 1;
variable max_d_value : integer := 1;
variable new_multiplier : integer := 1;
-- internal variables for storing the phase shift number.(used in lvds mode only)
variable i_clk0_phase_shift : integer := 1;
variable i_clk1_phase_shift : integer := 1;
variable i_clk2_phase_shift : integer := 1;
-- user to advanced variables
variable max_neg_abs : integer := 0;
variable i_m_initial : integer;
variable i_m : integer := 1;
variable i_n : integer := 1;
variable i_c_high : int_array(0 to 4);
variable i_c_low : int_array(0 to 4);
variable i_c_initial : int_array(0 to 4);
variable i_c_ph : int_array(0 to 4);
variable i_c_mode : str_array(0 to 4);
variable i_m_ph : integer;
variable output_count : integer;
variable new_divisor : integer;
variable clk0_cntr : string(1 to 6) := " c0";
variable clk1_cntr : string(1 to 6) := " c1";
variable clk2_cntr : string(1 to 6) := " c2";
variable clk3_cntr : string(1 to 6) := " c3";
variable clk4_cntr : string(1 to 6) := " c4";
variable fbk_cntr : string(1 to 2);
variable fbk_cntr_index : integer;
variable start_bit : integer;
variable quiet_time : time := 0 ps;
variable slowest_clk_old : time := 0 ps;
variable slowest_clk_new : time := 0 ps;
variable i : integer := 0;
variable j : integer := 0;
variable scanread_active_edge : time := 0 ps;
variable got_first_scanclk : boolean := false;
variable scanclk_last_rising_edge : time := 0 ps;
variable current_scan_data : std_logic_vector(0 to 143) := (OTHERS => '0');
variable index : integer := 0;
variable Tviol_scandata_scanclk : std_ulogic := '0';
variable TimingData_scandata_scanclk : VitalTimingDataType := VitalTimingDataInit;
variable Tviol_scanclkena_scanclk : std_ulogic := '0';
variable TimingData_scanclkena_scanclk : VitalTimingDataType := VitalTimingDataInit;
variable scan_chain_length : integer := GPP_SCAN_CHAIN;
variable tmp_rem : integer := 0;
variable scanclk_cycles : integer := 0;
variable lfc_tmp : std_logic_vector(1 downto 0);
variable lfr_tmp : std_logic_vector(5 downto 0);
variable lfr_int : integer := 0;
variable n_hi,n_lo,m_hi,m_lo : std_logic_vector(7 downto 0);
variable buf : line;
variable buf_scan_data : STD_LOGIC_VECTOR(0 TO 1) := (OTHERS => '0');
variable buf_scan_data_2 : STD_LOGIC_VECTOR(0 TO 2) := (OTHERS => '0');
function slowest_clk (
C0 : integer; C0_mode : string(1 to 6);
C1 : integer; C1_mode : string(1 to 6);
C2 : integer; C2_mode : string(1 to 6);
C3 : integer; C3_mode : string(1 to 6);
C4 : integer; C4_mode : string(1 to 6);
C5 : integer; C5_mode : string(1 to 6);
C6 : integer; C6_mode : string(1 to 6);
C7 : integer; C7_mode : string(1 to 6);
C8 : integer; C8_mode : string(1 to 6);
C9 : integer; C9_mode : string(1 to 6);
refclk : time; m_mod : integer) return time is
variable max_modulus : integer := 1;
variable q_period : time := 0 ps;
variable refclk_int : integer := 0;
begin
if (C0_mode /= "bypass" and C0_mode /= " off") then
max_modulus := C0;
end if;
if (C1 > max_modulus and C1_mode /= "bypass" and C1_mode /= " off") then
max_modulus := C1;
end if;
if (C2 > max_modulus and C2_mode /= "bypass" and C2_mode /= " off") then
max_modulus := C2;
end if;
if (C3 > max_modulus and C3_mode /= "bypass" and C3_mode /= " off") then
max_modulus := C3;
end if;
if (C4 > max_modulus and C4_mode /= "bypass" and C4_mode /= " off") then
max_modulus := C4;
end if;
if (C5 > max_modulus and C5_mode /= "bypass" and C5_mode /= " off") then
max_modulus := C5;
end if;
if (C6 > max_modulus and C6_mode /= "bypass" and C6_mode /= " off") then
max_modulus := C6;
end if;
if (C7 > max_modulus and C7_mode /= "bypass" and C7_mode /= " off") then
max_modulus := C7;
end if;
if (C8 > max_modulus and C8_mode /= "bypass" and C8_mode /= " off") then
max_modulus := C8;
end if;
if (C9 > max_modulus and C9_mode /= "bypass" and C9_mode /= " off") then
max_modulus := C9;
end if;
refclk_int := refclk / 1 ps;
if (m_mod /= 0) then
q_period := (refclk_int * max_modulus / m_mod) * 1 ps;
end if;
return (2*q_period);
end slowest_clk;
function int2bin (arg : integer; size : integer) return std_logic_vector is
variable int_val : integer := arg;
variable result : std_logic_vector(size-1 downto 0);
begin
for i in 0 to result'left loop
if ((int_val mod 2) = 0) then
result(i) := '0';
else
result(i) := '1';
end if;
int_val := int_val/2;
end loop;
return result;
end int2bin;
function extract_cntr_string (arg:string) return string is
variable str : string(1 to 6) := " c0";
begin
if (arg = "c0") then
str := " c0";
elsif (arg = "c1") then
str := " c1";
elsif (arg = "c2") then
str := " c2";
elsif (arg = "c3") then
str := " c3";
elsif (arg = "c4") then
str := " c4";
elsif (arg = "c5") then
str := " c5";
elsif (arg = "c6") then
str := " c6";
elsif (arg = "c7") then
str := " c7";
elsif (arg = "c8") then
str := " c8";
elsif (arg = "c9") then
str := " c9";
else str := " c0";
end if;
return str;
end extract_cntr_string;
function extract_cntr_index (arg:string) return integer is
variable index : integer := 0;
begin
if (arg(6) = '0') then
index := 0;
elsif (arg(6) = '1') then
index := 1;
elsif (arg(6) = '2') then
index := 2;
elsif (arg(6) = '3') then
index := 3;
elsif (arg(6) = '4') then
index := 4;
elsif (arg(6) = '5') then
index := 5;
elsif (arg(6) = '6') then
index := 6;
elsif (arg(6) = '7') then
index := 7;
elsif (arg(6) = '8') then
index := 8;
else index := 9;
end if;
return index;
end extract_cntr_index;
function output_cntr_num (arg:string) return string is
variable str : string(1 to 6) := "unused";
begin
if (arg = "c0") then
str := " clk0";
elsif (arg = "c1") then
str := " clk1";
elsif (arg = "c2") then
str := " clk2";
elsif (arg = "c3") then
str := " clk3";
elsif (arg = "c4") then
str := " clk4";
elsif (arg = "c5") then
str := " clk5";
elsif (arg = "c6") then
str := " clk6";
elsif (arg = "c7") then
str := " clk7";
elsif (arg = "c8") then
str := " clk8";
elsif (arg = "c9") then
str := " clk9";
else str := "unused";
end if;
return str;
end output_cntr_num;
begin
IF (areset_ipd'EVENT AND areset_ipd = '1') then
c_ph_val <= i_c_ph;
END IF;
if (init) then
if (m = 0) then
clk4_cntr := " c4";
clk3_cntr := " c3";
clk2_cntr := " c2";
clk1_cntr := " c1";
clk0_cntr := " c0";
else
clk4_cntr := extract_cntr_string(clk4_counter);
clk3_cntr := extract_cntr_string(clk3_counter);
clk2_cntr := extract_cntr_string(clk2_counter);
clk1_cntr := extract_cntr_string(clk1_counter);
clk0_cntr := extract_cntr_string(clk0_counter);
end if;
clk_num(4) <= output_cntr_num(clk4_counter);
clk_num(3) <= output_cntr_num(clk3_counter);
clk_num(2) <= output_cntr_num(clk2_counter);
clk_num(1) <= output_cntr_num(clk1_counter);
clk_num(0) <= output_cntr_num(clk0_counter);
i_clk0_counter <= extract_cntr_index(clk0_cntr);
i_clk1_counter <= extract_cntr_index(clk1_cntr);
i_clk2_counter <= extract_cntr_index(clk2_cntr);
i_clk3_counter <= extract_cntr_index(clk3_cntr);
i_clk4_counter <= extract_cntr_index(clk4_cntr);
if (m = 0) then -- convert user parameters to advanced
-- set the limit of the divide_by value that can be returned by
-- the following function.
max_d_value := 500;
-- scale down the multiply_by and divide_by values provided by the design
-- before attempting to use them in the calculations below
find_simple_integer_fraction(clk0_multiply_by, clk0_divide_by,
max_d_value, i_clk0_mult_by, i_clk0_div_by);
find_simple_integer_fraction(clk1_multiply_by, clk1_divide_by,
max_d_value, i_clk1_mult_by, i_clk1_div_by);
find_simple_integer_fraction(clk2_multiply_by, clk2_divide_by,
max_d_value, i_clk2_mult_by, i_clk2_div_by);
find_simple_integer_fraction(clk3_multiply_by, clk3_divide_by,
max_d_value, i_clk3_mult_by, i_clk3_div_by);
find_simple_integer_fraction(clk4_multiply_by, clk4_divide_by,
max_d_value, i_clk4_mult_by, i_clk4_div_by);
if (vco_frequency_control = "manual_phase") then
find_m_and_n_4_manual_phase(inclk0_input_frequency, vco_phase_shift_step,
i_clk0_mult_by, i_clk1_mult_by,
i_clk2_mult_by, i_clk3_mult_by,
i_clk4_mult_by,
1,1,1,1,1,
i_clk0_div_by, i_clk1_div_by,
i_clk2_div_by, i_clk3_div_by,
i_clk4_div_by,
1,1,1,1,1,
clk0_counter, clk1_counter,
clk2_counter, clk3_counter,
clk4_counter,
"unused","unused","unused","unused","unused",
i_m, i_n);
elsif (((pll_type = "fast") or (pll_type = "lvds") OR (pll_type = "left_right")) and ((vco_multiply_by /= 0) and (vco_divide_by /= 0))) then
i_n := vco_divide_by;
i_m := vco_multiply_by;
else
i_n := 1;
if (((pll_type = "fast") or (pll_type = "left_right")) and (compensate_clock = "lvdsclk")) then
i_m := i_clk0_mult_by;
else
i_m := lcm (i_clk0_mult_by, i_clk1_mult_by,
i_clk2_mult_by, i_clk3_mult_by,
i_clk4_mult_by,
1,1,1,1,1,
inclk0_input_frequency);
end if;
end if;
if (pll_type = "flvds") then
-- Need to readjust phase shift values when the clock multiply value has been readjusted.
new_multiplier := clk0_multiply_by / i_clk0_mult_by;
i_clk0_phase_shift := str2int(clk0_phase_shift) * new_multiplier;
i_clk1_phase_shift := str2int(clk1_phase_shift) * new_multiplier;
i_clk2_phase_shift := str2int(clk2_phase_shift) * new_multiplier;
else
i_clk0_phase_shift := str2int(clk0_phase_shift);
i_clk1_phase_shift := str2int(clk1_phase_shift);
i_clk2_phase_shift := str2int(clk2_phase_shift);
end if;
max_neg_abs := maxnegabs(i_clk0_phase_shift,
i_clk1_phase_shift,
i_clk2_phase_shift,
str2int(clk3_phase_shift),
str2int(clk4_phase_shift),
0,
0,
0,
0,
0
);
i_m_ph := counter_ph(get_phase_degree(max_neg_abs,inclk0_input_frequency), i_m, i_n);
i_c_ph(0) := counter_ph(get_phase_degree(ph_adjust(i_clk0_phase_shift,max_neg_abs),inclk0_input_frequency), i_m, i_n);
i_c_ph(1) := counter_ph(get_phase_degree(ph_adjust(i_clk1_phase_shift,max_neg_abs),inclk0_input_frequency), i_m, i_n);
i_c_ph(2) := counter_ph(get_phase_degree(ph_adjust(i_clk2_phase_shift,max_neg_abs),inclk0_input_frequency), i_m, i_n);
i_c_ph(3) := counter_ph(get_phase_degree(ph_adjust(str2int(clk3_phase_shift),max_neg_abs),inclk0_input_frequency), i_m, i_n);
i_c_ph(4) := counter_ph(get_phase_degree(ph_adjust(str2int(clk4_phase_shift),max_neg_abs),inclk0_input_frequency), i_m, i_n);
i_c_high(0) := counter_high(output_counter_value(i_clk0_div_by,
i_clk0_mult_by, i_m, i_n), clk0_duty_cycle);
i_c_high(1) := counter_high(output_counter_value(i_clk1_div_by,
i_clk1_mult_by, i_m, i_n), clk1_duty_cycle);
i_c_high(2) := counter_high(output_counter_value(i_clk2_div_by,
i_clk2_mult_by, i_m, i_n), clk2_duty_cycle);
i_c_high(3) := counter_high(output_counter_value(i_clk3_div_by,
i_clk3_mult_by, i_m, i_n), clk3_duty_cycle);
i_c_high(4) := counter_high(output_counter_value(i_clk4_div_by,
i_clk4_mult_by, i_m, i_n), clk4_duty_cycle);
i_c_low(0) := counter_low(output_counter_value(i_clk0_div_by,
i_clk0_mult_by, i_m, i_n), clk0_duty_cycle);
i_c_low(1) := counter_low(output_counter_value(i_clk1_div_by,
i_clk1_mult_by, i_m, i_n), clk1_duty_cycle);
i_c_low(2) := counter_low(output_counter_value(i_clk2_div_by,
i_clk2_mult_by, i_m, i_n), clk2_duty_cycle);
i_c_low(3) := counter_low(output_counter_value(i_clk3_div_by,
i_clk3_mult_by, i_m, i_n), clk3_duty_cycle);
i_c_low(4) := counter_low(output_counter_value(i_clk4_div_by,
i_clk4_mult_by, i_m, i_n), clk4_duty_cycle);
i_m_initial := counter_initial(get_phase_degree(max_neg_abs, inclk0_input_frequency), i_m,i_n);
i_c_initial(0) := counter_initial(get_phase_degree(ph_adjust(i_clk0_phase_shift, max_neg_abs), inclk0_input_frequency), i_m, i_n);
i_c_initial(1) := counter_initial(get_phase_degree(ph_adjust(i_clk1_phase_shift, max_neg_abs), inclk0_input_frequency), i_m, i_n);
i_c_initial(2) := counter_initial(get_phase_degree(ph_adjust(i_clk2_phase_shift, max_neg_abs), inclk0_input_frequency), i_m, i_n);
i_c_initial(3) := counter_initial(get_phase_degree(ph_adjust(str2int(clk3_phase_shift), max_neg_abs), inclk0_input_frequency), i_m, i_n);
i_c_initial(4) := counter_initial(get_phase_degree(ph_adjust(str2int(clk4_phase_shift), max_neg_abs), inclk0_input_frequency), i_m, i_n);
i_c_mode(0) := counter_mode(clk0_duty_cycle, output_counter_value(i_clk0_div_by, i_clk0_mult_by, i_m, i_n));
i_c_mode(1) := counter_mode(clk1_duty_cycle, output_counter_value(i_clk1_div_by, i_clk1_mult_by, i_m, i_n));
i_c_mode(2) := counter_mode(clk2_duty_cycle, output_counter_value(i_clk2_div_by, i_clk2_mult_by, i_m, i_n));
i_c_mode(3) := counter_mode(clk3_duty_cycle, output_counter_value(i_clk3_div_by, i_clk3_mult_by, i_m, i_n));
i_c_mode(4) := counter_mode(clk4_duty_cycle, output_counter_value(i_clk4_div_by, i_clk4_mult_by, i_m, i_n));
else -- m /= 0
i_n := n;
i_m := m;
i_m_initial := m_initial;
i_m_ph := m_ph;
i_c_ph(0) := c0_ph;
i_c_ph(1) := c1_ph;
i_c_ph(2) := c2_ph;
i_c_ph(3) := c3_ph;
i_c_ph(4) := c4_ph;
i_c_high(0) := c0_high;
i_c_high(1) := c1_high;
i_c_high(2) := c2_high;
i_c_high(3) := c3_high;
i_c_high(4) := c4_high;
i_c_low(0) := c0_low;
i_c_low(1) := c1_low;
i_c_low(2) := c2_low;
i_c_low(3) := c3_low;
i_c_low(4) := c4_low;
i_c_initial(0) := c0_initial;
i_c_initial(1) := c1_initial;
i_c_initial(2) := c2_initial;
i_c_initial(3) := c3_initial;
i_c_initial(4) := c4_initial;
i_c_mode(0) := translate_string(c0_mode);
i_c_mode(1) := translate_string(c1_mode);
i_c_mode(2) := translate_string(c2_mode);
i_c_mode(3) := translate_string(c3_mode);
i_c_mode(4) := translate_string(c4_mode);
end if; -- user to advanced conversion.
m_initial_val <= i_m_initial;
n_val <= i_n;
m_val <= i_m;
if (i_m = 1) then
m_mode_val <= "bypass";
else
m_mode_val <= " ";
end if;
if (i_n = 1) then
n_mode_val <= "bypass";
else
n_mode_val <= " ";
end if;
m_ph_val <= i_m_ph;
m_ph_initial <= i_m_ph;
m_val_tmp := i_m;
for i in 0 to 4 loop
if (i_c_mode(i) = "bypass") then
if (pll_type = "fast" or pll_type = "lvds" OR (pll_type = "left_right")) then
i_c_high(i) := 16;
i_c_low(i) := 16;
else
i_c_high(i) := 256;
i_c_low(i) := 256;
end if;
end if;
c_ph_val(i) <= i_c_ph(i);
c_initial_val(i) <= i_c_initial(i);
c_high_val(i) <= i_c_high(i);
c_low_val(i) <= i_c_low(i);
c_mode_val(i) <= i_c_mode(i);
c_high_val_tmp(i) := i_c_high(i);
c_hval(i) := i_c_high(i);
c_low_val_tmp(i) := i_c_low(i);
c_lval(i) := i_c_low(i);
c_mode_val_tmp(i) := i_c_mode(i);
c_ph_val_orig(i) <= i_c_ph(i);
c_high_val_hold(i) <= i_c_high(i);
c_low_val_hold(i) <= i_c_low(i);
c_mode_val_hold(i) <= i_c_mode(i);
end loop;
scan_chain_length := SCAN_CHAIN;
num_output_cntrs <= 5;
init := false;
elsif (scandone_tmp'EVENT AND scandone_tmp = '1') then
c0_rising_edge_transfer_done := false;
c1_rising_edge_transfer_done := false;
c2_rising_edge_transfer_done := false;
c3_rising_edge_transfer_done := false;
c4_rising_edge_transfer_done := false;
update_conf_latches_reg <= '0';
elsif (update_conf_latches'event and update_conf_latches = '1') then
initiate_reconfig <= '1';
elsif (areset_ipd'event AND areset_ipd = '1') then
if (scandone_tmp = '0') then scandone_tmp <= '1' AFTER scanclk_period; end if;
elsif (scanclk_ipd'event and scanclk_ipd = '1') then
IF (initiate_reconfig = '1') THEN
initiate_reconfig <= '0';
ASSERT false REPORT "PLL Reprogramming Initiated" severity note;
update_conf_latches_reg <= update_conf_latches;
reconfig_err <= false;
scandone_tmp <= '0';
cp_curr_old <= cp_curr_val;
lfc_old <= lfc_val;
lfr_old <= lfr_val;
vco_old <= vco_cur;
-- LF unused : bit 0,1
-- LF Capacitance : bits 2,3 : all values are legal
buf_scan_data := scan_data(2 TO 3);
IF ((pll_type = "fast") OR (pll_type = "lvds") OR (pll_type = "left_right")) THEN
lfc_val <= fpll_loop_filter_c_arr(alt_conv_integer(buf_scan_data));
ELSE
lfc_val <= loop_filter_c_arr(alt_conv_integer(buf_scan_data));
END IF;
-- LF Resistance : bits 4-8
-- valid values - 00000,00100,10000,10100,11000,11011,11100,11110
IF (scan_data(4 TO 8) = "00000") THEN
lfr_val <= "20";
ELSIF (scan_data(4 TO 8) = "00100") THEN
lfr_val <= "16";
ELSIF (scan_data(4 TO 8) = "10000") THEN
lfr_val <= "12";
ELSIF (scan_data(4 TO 8) = "10100") THEN
lfr_val <= "08";
ELSIF (scan_data(4 TO 8) = "11000") THEN
lfr_val <= "06";
ELSIF (scan_data(4 TO 8) = "11011") THEN
lfr_val <= "04";
ELSIF (scan_data(4 TO 8) = "11100") THEN
lfr_val <= "02";
ELSE
lfr_val <= "01";
END IF;
-- VCO post scale assignment
if (scan_data(9) = '1') then -- vco_post_scale = 1
i_vco_max <= VCO_MAX_NO_DIVISION/2;
i_vco_min <= VCO_MIN_NO_DIVISION/2;
vco_cur <= 1;
else
i_vco_max <= vco_max;
i_vco_min <= vco_min;
vco_cur <= 2;
end if;
-- CP
-- Bit 9 : CRBYPASS
-- Bit 10-14 : unused
-- Bits 15-17 : all values are legal
buf_scan_data_2 := scan_data(15 TO 17);
cp_curr_val <= charge_pump_curr_arr(alt_conv_integer(buf_scan_data_2));
-- save old values for display info.
cp_curr_val_bit_setting <= scan_data(15 TO 17);
lfc_val_bit_setting <= scan_data(2 TO 3);
lfr_val_bit_setting <= scan_data(4 TO 8);
m_val_old <= m_val;
n_val_old <= n_val;
m_mode_val_old <= m_mode_val;
n_mode_val_old <= n_mode_val;
WHILE (i < num_output_cntrs) LOOP
c_high_val_old(i) <= c_high_val(i);
c_low_val_old(i) <= c_low_val(i);
c_mode_val_old(i) <= c_mode_val(i);
i := i + 1;
END LOOP;
-- M counter
-- 1. Mode - bypass (bit 18)
IF (scan_data(18) = '1') THEN
n_mode_val <= "bypass";
-- 3. Mode - odd/even (bit 27)
ELSIF (scan_data(27) = '1') THEN
n_mode_val <= " odd";
ELSE
n_mode_val <= " even";
END IF;
-- 2. High (bit 19-26)
n_hi := scan_data(19 TO 26);
-- 4. Low (bit 28-35)
n_lo := scan_data(28 TO 35);
-- N counter
-- 1. Mode - bypass (bit 36)
IF (scan_data(36) = '1') THEN
m_mode_val <= "bypass";
-- 3. Mode - odd/even (bit 45)
ELSIF (scan_data(45) = '1') THEN
m_mode_val <= " odd";
ELSE
m_mode_val <= " even";
END IF;
-- 2. High (bit 37-44)
m_hi := scan_data(37 TO 44);
-- 4. Low (bit 46-53)
m_lo := scan_data(46 TO 53);
-- C counters (start bit 54) bit 1:mode(bypass),bit 2-9:high,bit 10:mode(odd/even),bit 11-18:low
i := 0;
WHILE (i < num_output_cntrs) LOOP
-- 1. Mode - bypass
IF (scan_data(54 + i * 18 + 0) = '1') THEN
c_mode_val_tmp(i) := "bypass";
-- 3. Mode - odd/even
ELSIF (scan_data(54 + i * 18 + 9) = '1') THEN
c_mode_val_tmp(i) := " odd";
ELSE
c_mode_val_tmp(i) := " even";
END IF;
-- 2. Hi
high := scan_data(54 + i * 18 + 1 TO 54 + i * 18 + 8);
c_hval(i) := alt_conv_integer(high);
IF (c_hval(i) /= 0) THEN
c_high_val_tmp(i) := c_hval(i);
ELSE
c_high_val_tmp(i) := alt_conv_integer("000000001");
END IF;
-- 4. Low
low := scan_data(54 + i * 18 + 10 TO 54 + i * 18 + 17);
c_lval(i) := alt_conv_integer(low);
IF (c_lval(i) /= 0) THEN
c_low_val_tmp(i) := c_lval(i);
ELSE
c_low_val_tmp(i) := alt_conv_integer("000000001");
END IF;
i := i + 1;
END LOOP;
-- Legality Checks
-- M counter value
IF(scan_data(36) /= '1') THEN
IF ((m_hi /= m_lo) and (scan_data(45) /= '1')) THEN
reconfig_err <= TRUE;
WRITE(buf,string'("Warning : The M counter of the " & family_name & " Fast PLL should be configured for 50%% duty cycle only. In this case the HIGH and LOW moduli programmed will result in a duty cycle other than 50%%, which is illegal. Reconfiguration may not work"));
writeline(output, buf);
ELSIF (m_hi /= "00000000") THEN
m_val_tmp := alt_conv_integer(m_hi) + alt_conv_integer(m_lo);
ELSE
m_val_tmp := alt_conv_integer("000000001");
END IF;
ELSE
m_val_tmp := alt_conv_integer("10000000");
END IF;
-- N counter value
IF(scan_data(18) /= '1') THEN
IF ((n_hi /= n_lo)and (scan_data(27) /= '1')) THEN
reconfig_err <= TRUE;
WRITE(buf,string'("Warning : The N counter of the " & family_name & " Fast PLL should be configured for 50%% duty cycle only. In this case the HIGH and LOW moduli programmed will result in a duty cycle other than 50%%, which is illegal. Reconfiguration may not work"));
writeline(output, buf);
ELSIF (n_hi /= "00000000") THEN
n_val <= alt_conv_integer(n_hi) + alt_conv_integer(n_lo);
ELSE
n_val <= alt_conv_integer("000000001");
END IF;
ELSE
n_val <= alt_conv_integer("10000000");
END IF;
-- TODO : Give warnings/errors in the following cases?
-- 1. Illegal counter values (error)
-- 2. Change of mode (warning)
-- 3. Only 50% duty cycle allowed for M counter (odd mode - hi-lo=1,even - hi-lo=0)
END IF;
end if;
if (fbclk'event and fbclk = '1') then
m_val <= m_val_tmp;
end if;
if (update_conf_latches_reg = '1') then
if (scanclk_ipd'event and scanclk_ipd = '1') then
c0_rising_edge_transfer_done := true;
c_high_val(0) <= c_high_val_tmp(0);
c_mode_val(0) <= c_mode_val_tmp(0);
end if;
if (scanclk_ipd'event and scanclk_ipd = '1') then
c1_rising_edge_transfer_done := true;
c_high_val(1) <= c_high_val_tmp(1);
c_mode_val(1) <= c_mode_val_tmp(1);
end if;
if (scanclk_ipd'event and scanclk_ipd = '1') then
c2_rising_edge_transfer_done := true;
c_high_val(2) <= c_high_val_tmp(2);
c_mode_val(2) <= c_mode_val_tmp(2);
end if;
if (scanclk_ipd'event and scanclk_ipd = '1') then
c_high_val(3) <= c_high_val_tmp(3);
c_mode_val(3) <= c_mode_val_tmp(3);
c3_rising_edge_transfer_done := true;
end if;
if (scanclk_ipd'event and scanclk_ipd = '1') then
c_high_val(4) <= c_high_val_tmp(4);
c_mode_val(4) <= c_mode_val_tmp(4);
c4_rising_edge_transfer_done := true;
end if;
end if;
if (scanclk_ipd'event and scanclk_ipd = '0' and c0_rising_edge_transfer_done) then
c_low_val(0) <= c_low_val_tmp(0);
end if;
if (scanclk_ipd'event and scanclk_ipd = '0' and c1_rising_edge_transfer_done) then
c_low_val(1) <= c_low_val_tmp(1);
end if;
if (scanclk_ipd'event and scanclk_ipd = '0' and c2_rising_edge_transfer_done) then
c_low_val(2) <= c_low_val_tmp(2);
end if;
if (scanclk_ipd'event and scanclk_ipd = '0' and c3_rising_edge_transfer_done) then
c_low_val(3) <= c_low_val_tmp(3);
end if;
if (scanclk_ipd'event and scanclk_ipd = '0' and c4_rising_edge_transfer_done) then
c_low_val(4) <= c_low_val_tmp(4);
end if;
if (update_phase = '1') then
if (vco_out(0)'event and vco_out(0) = '0') then
for i in 0 to 4 loop
if (c_ph_val(i) = 0) then
c_ph_val(i) <= c_ph_val_tmp(i);
end if;
end loop;
if (m_ph_val = 0) then
m_ph_val <= m_ph_val_tmp;
end if;
end if;
if (vco_out(1)'event and vco_out(1) = '0') then
for i in 0 to 4 loop
if (c_ph_val(i) = 1) then
c_ph_val(i) <= c_ph_val_tmp(i);
end if;
end loop;
if (m_ph_val = 1) then
m_ph_val <= m_ph_val_tmp;
end if;
end if;
if (vco_out(2)'event and vco_out(2) = '0') then
for i in 0 to 4 loop
if (c_ph_val(i) = 2) then
c_ph_val(i) <= c_ph_val_tmp(i);
end if;
end loop;
if (m_ph_val = 2) then
m_ph_val <= m_ph_val_tmp;
end if;
end if;
if (vco_out(3)'event and vco_out(3) = '0') then
for i in 0 to 4 loop
if (c_ph_val(i) = 3) then
c_ph_val(i) <= c_ph_val_tmp(i);
end if;
end loop;
if (m_ph_val = 3) then
m_ph_val <= m_ph_val_tmp;
end if;
end if;
if (vco_out(4)'event and vco_out(4) = '0') then
for i in 0 to 4 loop
if (c_ph_val(i) = 4) then
c_ph_val(i) <= c_ph_val_tmp(i);
end if;
end loop;
if (m_ph_val = 4) then
m_ph_val <= m_ph_val_tmp;
end if;
end if;
if (vco_out(5)'event and vco_out(5) = '0') then
for i in 0 to 4 loop
if (c_ph_val(i) = 5) then
c_ph_val(i) <= c_ph_val_tmp(i);
end if;
end loop;
if (m_ph_val = 5) then
m_ph_val <= m_ph_val_tmp;
end if;
end if;
if (vco_out(6)'event and vco_out(6) = '0') then
for i in 0 to 4 loop
if (c_ph_val(i) = 6) then
c_ph_val(i) <= c_ph_val_tmp(i);
end if;
end loop;
if (m_ph_val = 6) then
m_ph_val <= m_ph_val_tmp;
end if;
end if;
if (vco_out(7)'event and vco_out(7) = '0') then
for i in 0 to 4 loop
if (c_ph_val(i) = 7) then
c_ph_val(i) <= c_ph_val_tmp(i);
end if;
end loop;
if (m_ph_val = 7) then
m_ph_val <= m_ph_val_tmp;
end if;
end if;
end if;
if (vco_out(0)'event) then
for i in 0 to 4 loop
if (c_ph_val(i) = 0) then
inclk_c_from_vco(i) <= vco_out(0);
end if;
end loop;
if (m_ph_val = 0) then
inclk_m_from_vco <= vco_out(0);
end if;
end if;
if (vco_out(1)'event) then
for i in 0 to 4 loop
if (c_ph_val(i) = 1) then
inclk_c_from_vco(i) <= vco_out(1);
end if;
end loop;
if (m_ph_val = 1) then
inclk_m_from_vco <= vco_out(1);
end if;
end if;
if (vco_out(2)'event) then
for i in 0 to 4 loop
if (c_ph_val(i) = 2) then
inclk_c_from_vco(i) <= vco_out(2);
end if;
end loop;
if (m_ph_val = 2) then
inclk_m_from_vco <= vco_out(2);
end if;
end if;
if (vco_out(3)'event) then
for i in 0 to 4 loop
if (c_ph_val(i) = 3) then
inclk_c_from_vco(i) <= vco_out(3);
end if;
end loop;
if (m_ph_val = 3) then
inclk_m_from_vco <= vco_out(3);
end if;
end if;
if (vco_out(4)'event) then
for i in 0 to 4 loop
if (c_ph_val(i) = 4) then
inclk_c_from_vco(i) <= vco_out(4);
end if;
end loop;
if (m_ph_val = 4) then
inclk_m_from_vco <= vco_out(4);
end if;
end if;
if (vco_out(5)'event) then
for i in 0 to 4 loop
if (c_ph_val(i) = 5) then
inclk_c_from_vco(i) <= vco_out(5);
end if;
end loop;
if (m_ph_val = 5) then
inclk_m_from_vco <= vco_out(5);
end if;
end if;
if (vco_out(6)'event) then
for i in 0 to 4 loop
if (c_ph_val(i) = 6) then
inclk_c_from_vco(i) <= vco_out(6);
end if;
end loop;
if (m_ph_val = 6) then
inclk_m_from_vco <= vco_out(6);
end if;
end if;
if (vco_out(7)'event) then
for i in 0 to 4 loop
if (c_ph_val(i) = 7) then
inclk_c_from_vco(i) <= vco_out(7);
end if;
end loop;
if (m_ph_val = 7) then
inclk_m_from_vco <= vco_out(7);
end if;
end if;
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_scandata_scanclk,
TimingData => TimingData_scandata_scanclk,
TestSignal => scandata_ipd,
TestSignalName => "scandata",
RefSignal => scanclk_ipd,
RefSignalName => "scanclk",
SetupHigh => tsetup_scandata_scanclk_noedge_negedge,
SetupLow => tsetup_scandata_scanclk_noedge_negedge,
HoldHigh => thold_scandata_scanclk_noedge_negedge,
HoldLow => thold_scandata_scanclk_noedge_negedge,
CheckEnabled => TRUE,
RefTransition => '\',
HeaderMsg => InstancePath & "/cycloneiii_pll",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_scanclkena_scanclk,
TimingData => TimingData_scanclkena_scanclk,
TestSignal => scanclkena_ipd,
TestSignalName => "scanclkena",
RefSignal => scanclk_ipd,
RefSignalName => "scanclk",
SetupHigh => tsetup_scanclkena_scanclk_noedge_negedge,
SetupLow => tsetup_scanclkena_scanclk_noedge_negedge,
HoldHigh => thold_scanclkena_scanclk_noedge_negedge,
HoldLow => thold_scanclkena_scanclk_noedge_negedge,
CheckEnabled => TRUE,
RefTransition => '\',
HeaderMsg => InstancePath & "/cycloneiii_pll",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
end if;
if (scanclk_ipd'event AND scanclk_ipd = '0' AND now > 0 ps) then
scanclkena_reg <= scanclkena_ipd;
if (scanclkena_reg = '1') then
scandata_in <= scandata_ipd;
scandata_out <= scandataout_tmp;
end if;
end if;
if (scanclk_ipd'event and scanclk_ipd = '1' and now > 0 ps) then
if (got_first_scanclk) then
scanclk_period <= now - scanclk_last_rising_edge;
else
got_first_scanclk := true;
end if;
if (scanclkena_reg = '1') then
for j in scan_chain_length - 1 downto 1 loop
scan_data(j) <= scan_data(j-1);
end loop;
scan_data(0) <= scandata_in;
end if;
scanclk_last_rising_edge := now;
end if;
end process;
-- PLL Phase Reconfiguration
PROCESS(scanclk_ipd, areset_ipd,phasestep_ipd)
VARIABLE i : INTEGER := 0;
VARIABLE c_ph : INTEGER := 0;
VARIABLE m_ph : INTEGER := 0;
VARIABLE select_counter : INTEGER := 0;
BEGIN
IF (NOW = 0 ps) THEN
m_ph_val_tmp <= m_ph_initial;
END IF;
-- Latch phase enable (same as phasestep) on neg edge of scan clock
IF (scanclk_ipd'EVENT AND scanclk_ipd = '0') THEN
phasestep_reg <= phasestep_ipd;
END IF;
IF (phasestep_ipd'EVENT and phasestep_ipd = '1') THEN
IF (update_phase = '0') THEN
phasestep_high_count <= 0; -- phase adjustments must be 1 cycle apart
-- if not, next phasestep cycle is skipped
END IF;
END IF;
-- revert counter phase tap values to POF programmed values
-- if PLL is reset
IF (areset_ipd'EVENT AND areset_ipd = '1') then
c_ph_val_tmp <= c_ph_val_orig;
m_ph_val_tmp <= m_ph_initial;
END IF;
IF (scanclk_ipd'EVENT AND scanclk_ipd = '1') THEN
IF (phasestep_reg = '1') THEN
IF (phasestep_high_count = 1) THEN
phasecounterselect_reg <= phasecounterselect_ipd;
phaseupdown_reg <= phaseupdown_ipd;
-- start reconfiguration
IF (phasecounterselect_ipd < "111") THEN -- no counters selected
IF (phasecounterselect_ipd = "000") THEN
i := 0;
WHILE (i < num_output_cntrs) LOOP
c_ph := c_ph_val(i);
IF (phaseupdown_ipd = '1') THEN
c_ph := (c_ph + 1) mod num_phase_taps;
ELSIF (c_ph = 0) THEN
c_ph := num_phase_taps - 1;
ELSE
c_ph := (c_ph - 1) mod num_phase_taps;
END IF;
c_ph_val_tmp(i) <= c_ph;
i := i + 1;
END LOOP;
ELSIF (phasecounterselect_ipd = "001") THEN
m_ph := m_ph_val;
IF (phaseupdown_ipd = '1') THEN
m_ph := (m_ph + 1) mod num_phase_taps;
ELSIF (m_ph = 0) THEN
m_ph := num_phase_taps - 1;
ELSE
m_ph := (m_ph - 1) mod num_phase_taps;
END IF;
m_ph_val_tmp <= m_ph;
ELSE
select_counter := alt_conv_integer(phasecounterselect_ipd) - 2;
c_ph := c_ph_val(select_counter);
IF (phaseupdown_ipd = '1') THEN
c_ph := (c_ph + 1) mod num_phase_taps;
ELSIF (c_ph = 0) THEN
c_ph := num_phase_taps - 1;
ELSE
c_ph := (c_ph - 1) mod num_phase_taps;
END IF;
c_ph_val_tmp(select_counter) <= c_ph;
END IF;
update_phase <= '1','0' AFTER (0.5 * scanclk_period);
END IF;
END IF;
phasestep_high_count <= phasestep_high_count + 1;
END IF;
END IF;
END PROCESS;
scandataout_tmp <= scan_data(SCAN_CHAIN - 2);
process (schedule_vco, areset_ipd, pfdena_ipd, refclk, fbclk)
variable sched_time : time := 0 ps;
TYPE time_array is ARRAY (0 to 7) of time;
variable init : boolean := true;
variable refclk_period : time;
variable m_times_vco_period : time;
variable new_m_times_vco_period : time;
variable phase_shift : time_array := (OTHERS => 0 ps);
variable last_phase_shift : time_array := (OTHERS => 0 ps);
variable l_index : integer := 1;
variable cycle_to_adjust : integer := 0;
variable stop_vco : boolean := false;
variable locked_tmp : std_logic := '0';
variable pll_is_locked : boolean := false;
variable cycles_pfd_low : integer := 0;
variable cycles_pfd_high : integer := 0;
variable cycles_to_lock : integer := 0;
variable cycles_to_unlock : integer := 0;
variable got_first_refclk : boolean := false;
variable got_second_refclk : boolean := false;
variable got_first_fbclk : boolean := false;
variable refclk_time : time := 0 ps;
variable fbclk_time : time := 0 ps;
variable first_fbclk_time : time := 0 ps;
variable fbclk_period : time := 0 ps;
variable first_schedule : boolean := true;
variable vco_val : std_logic := '0';
variable vco_period_was_phase_adjusted : boolean := false;
variable phase_adjust_was_scheduled : boolean := false;
variable loop_xplier : integer;
variable loop_initial : integer := 0;
variable loop_ph : integer := 0;
variable loop_time_delay : integer := 0;
variable initial_delay : time := 0 ps;
variable vco_per : time;
variable tmp_rem : integer;
variable my_rem : integer;
variable fbk_phase : integer := 0;
variable pull_back_M : integer := 0;
variable total_pull_back : integer := 0;
variable fbk_delay : integer := 0;
variable offset : time := 0 ps;
variable tmp_vco_per : integer := 0;
variable high_time : time;
variable low_time : time;
variable got_refclk_posedge : boolean := false;
variable got_fbclk_posedge : boolean := false;
variable inclk_out_of_range : boolean := false;
variable no_warn : boolean := false;
variable ext_fbk_cntr_modulus : integer := 1;
variable init_clks : boolean := true;
variable pll_is_in_reset : boolean := false;
variable buf : line;
begin
if (init) then
-- jump-start the VCO
-- add 1 ps delay to ensure all signals are updated to initial
-- values
schedule_vco <= transport not schedule_vco after 1 ps;
init := false;
end if;
if (schedule_vco'event) then
if (init_clks) then
refclk_period := inclk0_input_frequency * n_val * 1 ps;
m_times_vco_period := refclk_period;
new_m_times_vco_period := refclk_period;
init_clks := false;
end if;
sched_time := 0 ps;
for i in 0 to 7 loop
last_phase_shift(i) := phase_shift(i);
end loop;
cycle_to_adjust := 0;
l_index := 1;
m_times_vco_period := new_m_times_vco_period;
end if;
-- areset was asserted
if (areset_ipd'event and areset_ipd = '1') then
assert false report family_name & " PLL was reset" severity note;
-- reset lock parameters
pll_is_locked := false;
cycles_to_lock := 0;
cycles_to_unlock := 0;
end if;
if (areset_ipd = '1') then
pll_is_in_reset := true;
got_first_refclk := false;
got_second_refclk := false;
-- drop VCO taps to 0
for i in 0 to 7 loop
vco_out(i) <= transport '0' after 1 ps;
end loop;
end if;
if (schedule_vco'event and (areset_ipd = '1' or stop_vco)) then
-- drop VCO taps to 0
for i in 0 to 7 loop
vco_out(i) <= transport '0' after last_phase_shift(i);
phase_shift(i) := 0 ps;
last_phase_shift(i) := 0 ps;
end loop;
-- reset lock parameters
pll_is_locked := false;
cycles_to_lock := 0;
cycles_to_unlock := 0;
got_first_refclk := false;
got_second_refclk := false;
refclk_time := 0 ps;
got_first_fbclk := false;
fbclk_time := 0 ps;
first_fbclk_time := 0 ps;
fbclk_period := 0 ps;
first_schedule := true;
vco_val := '0';
vco_period_was_phase_adjusted := false;
phase_adjust_was_scheduled := false;
elsif ((schedule_vco'event or areset_ipd'event) and areset_ipd = '0' and (not stop_vco) and now > 0 ps) then
-- note areset deassert time
-- note it as refclk_time to prevent false triggering
-- of stop_vco after areset
if (areset_ipd'event and areset_ipd = '0' and pll_is_in_reset) then
refclk_time := now;
locked_tmp := '0';
end if;
pll_is_in_reset := false;
-- calculate loop_xplier : this will be different from m_val
-- in external_feedback_mode
loop_xplier := m_val;
loop_initial := m_initial_val - 1;
loop_ph := m_ph_val;
-- convert initial value to delay
initial_delay := (loop_initial * m_times_vco_period)/loop_xplier;
-- convert loop ph_tap to delay
my_rem := (m_times_vco_period/1 ps) rem loop_xplier;
tmp_vco_per := (m_times_vco_period/1 ps) / loop_xplier;
if (my_rem /= 0) then
tmp_vco_per := tmp_vco_per + 1;
end if;
fbk_phase := (loop_ph * tmp_vco_per)/8;
pull_back_M := initial_delay/1 ps + fbk_phase;
total_pull_back := pull_back_M;
if (simulation_type = "timing") then
total_pull_back := total_pull_back + pll_compensation_delay;
end if;
while (total_pull_back > refclk_period/1 ps) loop
total_pull_back := total_pull_back - refclk_period/1 ps;
end loop;
if (total_pull_back > 0) then
offset := refclk_period - (total_pull_back * 1 ps);
end if;
fbk_delay := total_pull_back - fbk_phase;
if (fbk_delay < 0) then
offset := offset - (fbk_phase * 1 ps);
fbk_delay := total_pull_back;
end if;
-- assign m_delay
m_delay <= transport fbk_delay after 1 ps;
my_rem := (m_times_vco_period/1 ps) rem loop_xplier;
for i in 1 to loop_xplier loop
-- adjust cycles
tmp_vco_per := (m_times_vco_period/1 ps)/loop_xplier;
if (my_rem /= 0 and l_index <= my_rem) then
tmp_rem := (loop_xplier * l_index) rem my_rem;
cycle_to_adjust := (loop_xplier * l_index) / my_rem;
if (tmp_rem /= 0) then
cycle_to_adjust := cycle_to_adjust + 1;
end if;
end if;
if (cycle_to_adjust = i) then
tmp_vco_per := tmp_vco_per + 1;
l_index := l_index + 1;
end if;
-- calculate high and low periods
vco_per := tmp_vco_per * 1 ps;
high_time := (tmp_vco_per/2) * 1 ps;
if (tmp_vco_per rem 2 /= 0) then
high_time := high_time + 1 ps;
end if;
low_time := vco_per - high_time;
-- schedule the rising and falling edges
for j in 1 to 2 loop
vco_val := not vco_val;
if (vco_val = '0') then
sched_time := sched_time + high_time;
elsif (vco_val = '1') then
sched_time := sched_time + low_time;
end if;
-- schedule the phase taps
for k in 0 to 7 loop
phase_shift(k) := (k * vco_per)/8;
if (first_schedule) then
vco_out(k) <= transport vco_val after (sched_time + phase_shift(k));
else
vco_out(k) <= transport vco_val after (sched_time + last_phase_shift(k));
end if;
end loop;
end loop;
end loop;
-- schedule once more
if (first_schedule) then
vco_val := not vco_val;
if (vco_val = '0') then
sched_time := sched_time + high_time;
elsif (vco_val = '1') then
sched_time := sched_time + low_time;
end if;
-- schedule the phase taps
for k in 0 to 7 loop
phase_shift(k) := (k * vco_per)/8;
vco_out(k) <= transport vco_val after (sched_time + phase_shift(k));
end loop;
first_schedule := false;
end if;
schedule_vco <= transport not schedule_vco after sched_time;
if (vco_period_was_phase_adjusted) then
m_times_vco_period := refclk_period;
new_m_times_vco_period := refclk_period;
vco_period_was_phase_adjusted := false;
phase_adjust_was_scheduled := true;
vco_per := m_times_vco_period/loop_xplier;
for k in 0 to 7 loop
phase_shift(k) := (k * vco_per)/8;
end loop;
end if;
end if;
-- Bypass lock detect
if (refclk'event and refclk = '1' and areset_ipd = '0') then
if (test_bypass_lock_detect = "on") then
if (pfdena_ipd = '1') then
cycles_pfd_low := 0;
if (pfd_locked = '0') then
if (cycles_pfd_high = lock_high) then
assert false report family_name & " PLL locked in test mode on PFD enable assertion." severity warning;
pfd_locked <= '1';
end if;
cycles_pfd_high := cycles_pfd_high + 1;
end if;
end if;
if (pfdena_ipd = '0') then
cycles_pfd_high := 0;
if (pfd_locked = '1') then
if (cycles_pfd_low = lock_low) then
assert false report family_name & " PLL lost lock in test mode on PFD enable de-assertion." severity warning;
pfd_locked <= '0';
end if;
cycles_pfd_low := cycles_pfd_low + 1;
end if;
end if;
end if;
if (refclk'event and refclk = '1' and areset_ipd = '0') then
got_refclk_posedge := true;
if (not got_first_refclk) then
got_first_refclk := true;
else
got_second_refclk := true;
refclk_period := now - refclk_time;
-- check if incoming freq. will cause VCO range to be
-- exceeded
if ( (i_vco_max /= 0 and i_vco_min /= 0 and pfdena_ipd = '1') and
(((refclk_period/1 ps)/loop_xplier > i_vco_max) or
((refclk_period/1 ps)/loop_xplier < i_vco_min)) ) then
if (pll_is_locked) then
if ((refclk_period/1 ps)/loop_xplier > i_vco_max) then
assert false report "Input clock freq. is over VCO range. " & family_name & " PLL may lose lock" severity warning;
vco_over <= '1';
end if;
if ((refclk_period/1 ps)/loop_xplier < i_vco_min) then
assert false report "Input clock freq. is under VCO range. " & family_name & " PLL may lose lock" severity warning;
vco_under <= '1';
end if;
if (inclk_out_of_range) then
pll_is_locked := false;
locked_tmp := '0';
cycles_to_lock := 0;
vco_period_was_phase_adjusted := false;
phase_adjust_was_scheduled := false;
assert false report family_name & " PLL lost lock." severity note;
end if;
elsif (not no_warn) then
if ((refclk_period/1 ps)/loop_xplier > i_vco_max) then
assert false report "Input clock freq. is over VCO range. " & family_name & " PLL may lose lock" severity warning;
vco_over <= '1';
end if;
if ((refclk_period/1 ps)/loop_xplier < i_vco_min) then
assert false report "Input clock freq. is under VCO range. " & family_name & " PLL may lose lock" severity warning;
vco_under <= '1';
end if;
assert false report " Input clock freq. is not within VCO range : " & family_name & " PLL may not lock. Please use the correct frequency." severity warning;
no_warn := true;
end if;
inclk_out_of_range := true;
else
vco_over <= '0';
vco_under <= '0';
inclk_out_of_range := false;
no_warn := false;
end if;
end if;
end if;
if (stop_vco) then
stop_vco := false;
schedule_vco <= not schedule_vco;
end if;
refclk_time := now;
else
got_refclk_posedge := false;
end if;
-- Update M counter value on feedback clock edge
if (fbclk'event and fbclk = '1') then
got_fbclk_posedge := true;
if (not got_first_fbclk) then
got_first_fbclk := true;
else
fbclk_period := now - fbclk_time;
end if;
-- need refclk_period here, so initialized to proper value above
if ( ( (now - refclk_time > 1.5 * refclk_period) and pfdena_ipd = '1' and pll_is_locked) or
( (now - refclk_time > 5 * refclk_period) and pfdena_ipd = '1' and pll_has_just_been_reconfigured = false) or
( (now - refclk_time > 50 * refclk_period) and pfdena_ipd = '1' and pll_has_just_been_reconfigured = true) ) then
stop_vco := true;
-- reset
got_first_refclk := false;
got_first_fbclk := false;
got_second_refclk := false;
if (pll_is_locked) then
pll_is_locked := false;
locked_tmp := '0';
assert false report family_name & " PLL lost lock due to loss of input clock or the input clock is not detected within the allowed time frame." severity note;
if ((i_vco_max = 0) and (i_vco_min = 0)) then
assert false report "Please run timing simulation to check whether the input clock is operating within the supported VCO range or not." severity note;
end if;
end if;
cycles_to_lock := 0;
cycles_to_unlock := 0;
first_schedule := true;
vco_period_was_phase_adjusted := false;
phase_adjust_was_scheduled := false;
end if;
fbclk_time := now;
else
got_fbclk_posedge := false;
end if;
if ((got_refclk_posedge or got_fbclk_posedge) and got_second_refclk and pfdena_ipd = '1' and (not inclk_out_of_range)) then
-- now we know actual incoming period
if ( abs(fbclk_time - refclk_time) <= 5 ps or
(got_first_fbclk and abs(refclk_period - abs(fbclk_time - refclk_time)) <= 5 ps)) then
-- considered in phase
if (cycles_to_lock = real_lock_high) then
if (not pll_is_locked) then
assert false report family_name & " PLL locked to incoming clock" severity note;
end if;
pll_is_locked := true;
locked_tmp := '1';
cycles_to_unlock := 0;
end if;
-- increment lock counter only if second part of above
-- time check is NOT true
if (not(abs(refclk_period - abs(fbclk_time - refclk_time)) <= lock_window)) then
cycles_to_lock := cycles_to_lock + 1;
end if;
-- adjust m_times_vco_period
new_m_times_vco_period := refclk_period;
else
-- if locked, begin unlock
if (pll_is_locked) then
cycles_to_unlock := cycles_to_unlock + 1;
if (cycles_to_unlock = lock_low) then
pll_is_locked := false;
locked_tmp := '0';
cycles_to_lock := 0;
vco_period_was_phase_adjusted := false;
phase_adjust_was_scheduled := false;
assert false report family_name & " PLL lost lock." severity note;
got_first_refclk := false;
got_first_fbclk := false;
got_second_refclk := false;
end if;
end if;
if ( abs(refclk_period - fbclk_period) <= 2 ps ) then
-- frequency is still good
if (now = fbclk_time and (not phase_adjust_was_scheduled)) then
if ( abs(fbclk_time - refclk_time) > refclk_period/2) then
new_m_times_vco_period := m_times_vco_period + (refclk_period - abs(fbclk_time - refclk_time));
vco_period_was_phase_adjusted := true;
else
new_m_times_vco_period := m_times_vco_period - abs(fbclk_time - refclk_time);
vco_period_was_phase_adjusted := true;
end if;
end if;
else
phase_adjust_was_scheduled := false;
new_m_times_vco_period := refclk_period;
end if;
end if;
end if;
if (pfdena_ipd = '0') then
if (pll_is_locked) then
locked_tmp := 'X';
end if;
pll_is_locked := false;
cycles_to_lock := 0;
end if;
-- give message only at time of deassertion
if (pfdena_ipd'event and pfdena_ipd = '0') then
assert false report "PFDENA deasserted." severity note;
elsif (pfdena_ipd'event and pfdena_ipd = '1') then
got_first_refclk := false;
got_second_refclk := false;
refclk_time := now;
end if;
if (reconfig_err) then
lock <= '0';
else
lock <= locked_tmp;
end if;
-- signal to calculate quiet_time
sig_refclk_period <= refclk_period;
if (stop_vco = true) then
sig_stop_vco <= '1';
else
sig_stop_vco <= '0';
end if;
pll_locked <= pll_is_locked;
end process;
clk0_tmp <= c_clk(i_clk0_counter);
clk_pfd(0) <= clk0_tmp WHEN (pfd_locked = '1') ELSE 'X';
clk(0) <= clk_pfd(0) WHEN (test_bypass_lock_detect = "on") ELSE
clk0_tmp when (areset_ipd = '1' or pll_in_test_mode) or (pll_locked and (not reconfig_err)) else
'X';
clk1_tmp <= c_clk(i_clk1_counter);
clk_pfd(1) <= clk1_tmp WHEN (pfd_locked = '1') ELSE 'X';
clk(1) <= clk_pfd(1) WHEN (test_bypass_lock_detect = "on") ELSE
clk1_tmp when (areset_ipd = '1' or pll_in_test_mode) or (pll_locked and (not reconfig_err)) else 'X';
clk2_tmp <= c_clk(i_clk2_counter);
clk_pfd(2) <= clk2_tmp WHEN (pfd_locked = '1') ELSE 'X';
clk(2) <= clk_pfd(2) WHEN (test_bypass_lock_detect = "on") ELSE
clk2_tmp when (areset_ipd = '1' or pll_in_test_mode) or (pll_locked and (not reconfig_err)) else 'X';
clk3_tmp <= c_clk(i_clk3_counter);
clk_pfd(3) <= clk3_tmp WHEN (pfd_locked = '1') ELSE 'X';
clk(3) <= clk_pfd(3) WHEN (test_bypass_lock_detect = "on") ELSE
clk3_tmp when (areset_ipd = '1' or pll_in_test_mode) or (pll_locked and (not reconfig_err)) else 'X';
clk4_tmp <= c_clk(i_clk4_counter);
clk_pfd(4) <= clk4_tmp WHEN (pfd_locked = '1') ELSE 'X';
clk(4) <= clk_pfd(4) WHEN (test_bypass_lock_detect = "on") ELSE
clk4_tmp when (areset_ipd = '1' or pll_in_test_mode) or (pll_locked and (not reconfig_err)) else 'X';
scandataout <= scandata_out;
scandone <= NOT scandone_tmp;
phasedone <= NOT update_phase;
vcooverrange <= 'Z' WHEN (vco_range_detector_high_bits = -1) ELSE vco_over;
vcounderrange <= 'Z' WHEN (vco_range_detector_low_bits = -1) ELSE vco_under;
fbout <= fbclk;
end vital_pll;
-- END ARCHITECTURE VITAL_PLL
---------------------------------------------------------------------
--
-- Entity Name : cycloneiii_ff
--
-- Description : Cyclone III FF VHDL simulation model
--
--
---------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.cycloneiii_atom_pack.all;
use work.cycloneiii_and1;
entity cycloneiii_ff is
generic (
power_up : string := "low";
x_on_violation : string := "on";
lpm_type : string := "cycloneiii_ff";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clrn_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_aload_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_asdata_q: VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_asdata : VitalDelayType01 := DefPropDelay01;
tipd_sclr : VitalDelayType01 := DefPropDelay01;
tipd_sload : VitalDelayType01 := DefPropDelay01;
tipd_clrn : VitalDelayType01 := DefPropDelay01;
tipd_aload : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*"
);
port (
d : in std_logic := '0';
clk : in std_logic := '0';
clrn : in std_logic := '1';
aload : in std_logic := '0';
sclr : in std_logic := '0';
sload : in std_logic := '0';
ena : in std_logic := '1';
asdata : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
q : out std_logic
);
attribute VITAL_LEVEL0 of cycloneiii_ff : entity is TRUE;
end cycloneiii_ff;
architecture vital_lcell_ff of cycloneiii_ff is
attribute VITAL_LEVEL0 of vital_lcell_ff : architecture is TRUE;
signal clk_ipd : std_logic;
signal d_ipd : std_logic;
signal d_dly : std_logic;
signal asdata_ipd : std_logic;
signal asdata_dly : std_logic;
signal asdata_dly1 : std_logic;
signal sclr_ipd : std_logic;
signal sload_ipd : std_logic;
signal clrn_ipd : std_logic;
signal aload_ipd : std_logic;
signal ena_ipd : std_logic;
component cycloneiii_and1
generic (XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
tpd_IN1_Y : VitalDelayType01 := DefPropDelay01;
tipd_IN1 : VitalDelayType01 := DefPropDelay01
);
port (Y : out STD_LOGIC;
IN1 : in STD_LOGIC
);
end component;
begin
ddelaybuffer: cycloneiii_and1
port map(IN1 => d_ipd,
Y => d_dly);
asdatadelaybuffer: cycloneiii_and1
port map(IN1 => asdata_ipd,
Y => asdata_dly);
asdatadelaybuffer1: cycloneiii_and1
port map(IN1 => asdata_dly,
Y => asdata_dly1);
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (d_ipd, d, tipd_d);
VitalWireDelay (asdata_ipd, asdata, tipd_asdata);
VitalWireDelay (sclr_ipd, sclr, tipd_sclr);
VitalWireDelay (sload_ipd, sload, tipd_sload);
VitalWireDelay (clrn_ipd, clrn, tipd_clrn);
VitalWireDelay (aload_ipd, aload, tipd_aload);
VitalWireDelay (ena_ipd, ena, tipd_ena);
end block;
VITALtiming : process (clk_ipd, d_dly, asdata_dly1,
sclr_ipd, sload_ipd, clrn_ipd, aload_ipd,
ena_ipd, devclrn, devpor)
variable Tviol_d_clk : std_ulogic := '0';
variable Tviol_asdata_clk : std_ulogic := '0';
variable Tviol_sclr_clk : std_ulogic := '0';
variable Tviol_sload_clk : std_ulogic := '0';
variable Tviol_ena_clk : std_ulogic := '0';
variable TimingData_d_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_asdata_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_sclr_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_sload_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_ena_clk : VitalTimingDataType := VitalTimingDataInit;
variable q_VitalGlitchData : VitalGlitchDataType;
variable iq : std_logic := '0';
variable idata: std_logic := '0';
-- variables for 'X' generation
variable violation : std_logic := '0';
begin
if (now = 0 ns) then
if (power_up = "low") then
iq := '0';
elsif (power_up = "high") then
iq := '1';
end if;
end if;
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_d_clk,
TimingData => TimingData_d_clk,
TestSignal => d,
TestSignalName => "DATAIN",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_d_clk_noedge_posedge,
SetupLow => tsetup_d_clk_noedge_posedge,
HoldHigh => thold_d_clk_noedge_posedge,
HoldLow => thold_d_clk_noedge_posedge,
CheckEnabled => TO_X01((NOT clrn_ipd) OR
(sload_ipd) OR
(sclr_ipd) OR
(NOT devpor) OR
(NOT devclrn) OR
(NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/LCELL_FF",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_asdata_clk,
TimingData => TimingData_asdata_clk,
TestSignal => asdata_ipd,
TestSignalName => "ASDATA",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_asdata_clk_noedge_posedge,
SetupLow => tsetup_asdata_clk_noedge_posedge,
HoldHigh => thold_asdata_clk_noedge_posedge,
HoldLow => thold_asdata_clk_noedge_posedge,
CheckEnabled => TO_X01((NOT clrn_ipd) OR
(NOT sload_ipd) OR
(NOT devpor) OR
(NOT devclrn) OR
(NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/LCELL_FF",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_sclr_clk,
TimingData => TimingData_sclr_clk,
TestSignal => sclr_ipd,
TestSignalName => "SCLR",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_sclr_clk_noedge_posedge,
SetupLow => tsetup_sclr_clk_noedge_posedge,
HoldHigh => thold_sclr_clk_noedge_posedge,
HoldLow => thold_sclr_clk_noedge_posedge,
CheckEnabled => TO_X01((NOT clrn_ipd) OR
(NOT devpor) OR
(NOT devclrn) OR
(NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/LCELL_FF",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_sload_clk,
TimingData => TimingData_sload_clk,
TestSignal => sload_ipd,
TestSignalName => "SLOAD",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_sload_clk_noedge_posedge,
SetupLow => tsetup_sload_clk_noedge_posedge,
HoldHigh => thold_sload_clk_noedge_posedge,
HoldLow => thold_sload_clk_noedge_posedge,
CheckEnabled => TO_X01((NOT clrn_ipd) OR
(NOT devpor) OR
(NOT devclrn) OR
(NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/LCELL_FF",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_ena_clk,
TimingData => TimingData_ena_clk,
TestSignal => ena_ipd,
TestSignalName => "ENA",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_ena_clk_noedge_posedge,
SetupLow => tsetup_ena_clk_noedge_posedge,
HoldHigh => thold_ena_clk_noedge_posedge,
HoldLow => thold_ena_clk_noedge_posedge,
CheckEnabled => TO_X01((NOT clrn_ipd) OR
(NOT devpor) OR
(NOT devclrn) ) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/LCELL_FF",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
end if;
violation := Tviol_d_clk or Tviol_asdata_clk or
Tviol_sclr_clk or Tviol_sload_clk or Tviol_ena_clk;
if ((devpor = '0') or (devclrn = '0') or (clrn_ipd = '0')) then
iq := '0';
elsif (aload_ipd = '1') then
iq := asdata_dly1;
elsif (violation = 'X' and x_on_violation = "on") then
iq := 'X';
elsif clk_ipd'event and clk_ipd = '1' and clk_ipd'last_value = '0' then
if (ena_ipd = '1') then
if (sclr_ipd = '1') then
iq := '0';
elsif (sload_ipd = '1') then
iq := asdata_dly1;
else
iq := d_dly;
end if;
end if;
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => q,
OutSignalName => "Q",
OutTemp => iq,
Paths => (0 => (clrn_ipd'last_event, tpd_clrn_q_posedge, TRUE),
1 => (aload_ipd'last_event, tpd_aload_q_posedge, TRUE),
2 => (asdata_ipd'last_event, tpd_asdata_q, TRUE),
3 => (clk_ipd'last_event, tpd_clk_q_posedge, TRUE)),
GlitchData => q_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end vital_lcell_ff;
----------------------------------------------------------------------------
-- Module Name : cycloneiii_ram_register
-- Description : Register module for RAM inputs/outputs
----------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.cycloneiii_atom_pack.all;
ENTITY cycloneiii_ram_register IS
GENERIC (
width : INTEGER := 1;
preset : STD_LOGIC := '0';
tipd_d : VitalDelayArrayType01(143 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_stall : VitalDelayType01 := DefPropDelay01;
tipd_aclr : VitalDelayType01 := DefPropDelay01;
tpw_ena_posedge : VitalDelayType := DefPulseWdthCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_aclr_q_posedge : VitalDelayType01 := DefPropDelay01;
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_stall_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_stall_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_aclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_aclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst
);
PORT (
d : IN STD_LOGIC_VECTOR(width - 1 DOWNTO 0);
clk : IN STD_LOGIC;
ena : IN STD_LOGIC;
stall : IN STD_LOGIC;
aclr : IN STD_LOGIC;
devclrn : IN STD_LOGIC;
devpor : IN STD_LOGIC;
q : OUT STD_LOGIC_VECTOR(width - 1 DOWNTO 0);
aclrout : OUT STD_LOGIC
);
END cycloneiii_ram_register;
ARCHITECTURE reg_arch OF cycloneiii_ram_register IS
SIGNAL d_ipd : STD_LOGIC_VECTOR(width - 1 DOWNTO 0);
SIGNAL clk_ipd : STD_LOGIC;
SIGNAL ena_ipd : STD_LOGIC;
SIGNAL aclr_ipd : STD_LOGIC;
SIGNAL stall_ipd : STD_LOGIC;
BEGIN
WireDelay : BLOCK
BEGIN
loopbits : FOR i in d'RANGE GENERATE
VitalWireDelay (d_ipd(i), d(i), tipd_d(i));
END GENERATE;
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (aclr_ipd, aclr, tipd_aclr);
VitalWireDelay (ena_ipd, ena, tipd_ena);
VitalWireDelay (stall_ipd, stall, tipd_stall);
END BLOCK;
PROCESS (d_ipd,ena_ipd,stall_ipd,clk_ipd,aclr_ipd,devclrn,devpor)
VARIABLE Tviol_clk_ena : STD_ULOGIC := '0';
VARIABLE Tviol_clk_aclr : STD_ULOGIC := '0';
VARIABLE Tviol_data_clk : STD_ULOGIC := '0';
VARIABLE TimingData_clk_ena : VitalTimingDataType := VitalTimingDataInit;
VARIABLE TimingData_clk_stall : VitalTimingDataType := VitalTimingDataInit;
VARIABLE TimingData_clk_aclr : VitalTimingDataType := VitalTimingDataInit;
VARIABLE TimingData_data_clk : VitalTimingDataType := VitalTimingDataInit;
VARIABLE Tviol_ena : STD_ULOGIC := '0';
VARIABLE PeriodData_ena : VitalPeriodDataType := VitalPeriodDataInit;
VARIABLE q_VitalGlitchDataArray : VitalGlitchDataArrayType(143 downto 0);
VARIABLE CQDelay : TIME := 0 ns;
VARIABLE q_reg : STD_LOGIC_VECTOR(width - 1 DOWNTO 0) := (OTHERS => preset);
BEGIN
IF (aclr_ipd = '1' OR devclrn = '0' OR devpor = '0') THEN
q_reg := (OTHERS => preset);
ELSIF (clk_ipd = '1' AND clk_ipd'EVENT AND ena_ipd = '1' AND stall_ipd = '0') THEN
q_reg := d_ipd;
END IF;
-- Timing checks
VitalSetupHoldCheck (
Violation => Tviol_clk_ena,
TimingData => TimingData_clk_ena,
TestSignal => ena_ipd,
TestSignalName => "ena",
RefSignal => clk_ipd,
RefSignalName => "clk",
SetupHigh => tsetup_ena_clk_noedge_posedge,
SetupLow => tsetup_ena_clk_noedge_posedge,
HoldHigh => thold_ena_clk_noedge_posedge,
HoldLow => thold_ena_clk_noedge_posedge,
CheckEnabled => ((aclr_ipd) OR (NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => "/RAM Register VitalSetupHoldCheck",
XOn => DefXOnChecks,
MsgOn => DefMsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_clk_ena,
TimingData => TimingData_clk_stall,
TestSignal => stall_ipd,
TestSignalName => "stall",
RefSignal => clk_ipd,
RefSignalName => "clk",
SetupHigh => tsetup_stall_clk_noedge_posedge,
SetupLow => tsetup_stall_clk_noedge_posedge,
HoldHigh => thold_stall_clk_noedge_posedge,
HoldLow => thold_stall_clk_noedge_posedge,
CheckEnabled => ((aclr_ipd) OR (NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => "/RAM Register VitalSetupHoldCheck",
XOn => DefXOnChecks,
MsgOn => DefMsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_clk_aclr,
TimingData => TimingData_clk_aclr,
TestSignal => aclr_ipd,
TestSignalName => "aclr",
RefSignal => clk_ipd,
RefSignalName => "clk",
SetupHigh => tsetup_aclr_clk_noedge_posedge,
SetupLow => tsetup_aclr_clk_noedge_posedge,
HoldHigh => thold_aclr_clk_noedge_posedge,
HoldLow => thold_aclr_clk_noedge_posedge,
CheckEnabled => ((aclr_ipd) OR (NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => "/RAM Register VitalSetupHoldCheck",
XOn => DefXOnChecks,
MsgOn => DefMsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_data_clk,
TimingData => TimingData_data_clk,
TestSignal => d_ipd,
TestSignalName => "data",
RefSignal => clk_ipd,
RefSignalName => "clk",
SetupHigh => tsetup_d_clk_noedge_posedge,
SetupLow => tsetup_d_clk_noedge_posedge,
HoldHigh => thold_d_clk_noedge_posedge,
HoldLow => thold_d_clk_noedge_posedge,
CheckEnabled => ((aclr_ipd) OR (NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => "/RAM Register VitalSetupHoldCheck",
XOn => DefXOnChecks,
MsgOn => DefMsgOnChecks );
VitalPeriodPulseCheck (
Violation => Tviol_ena,
PeriodData => PeriodData_ena,
TestSignal => ena_ipd,
TestSignalName => "ena",
PulseWidthHigh => tpw_ena_posedge,
HeaderMsg => "/RAM Register VitalPeriodPulseCheck",
XOn => DefXOnChecks,
MsgOn => DefMsgOnChecks );
-- Path Delay Selection
CQDelay := SelectDelay (
Paths => (
(0 => (clk_ipd'LAST_EVENT,tpd_clk_q_posedge,TRUE),
1 => (aclr_ipd'LAST_EVENT,tpd_aclr_q_posedge,TRUE))
)
);
q <= TRANSPORT q_reg AFTER CQDelay;
END PROCESS;
aclrout <= aclr_ipd;
END reg_arch;
----------------------------------------------------------------------------
-- Module Name : cycloneiii_ram_pulse_generator
-- Description : Generate pulse to initiate memory read/write operations
----------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.cycloneiii_atom_pack.all;
ENTITY cycloneiii_ram_pulse_generator IS
GENERIC (
tipd_clk : VitalDelayType01 := (0.5 ns,0.5 ns);
tipd_ena : VitalDelayType01 := DefPropDelay01;
tpd_clk_pulse_posedge : VitalDelayType01 := DefPropDelay01
);
PORT (
clk,ena : IN STD_LOGIC;
delaywrite : IN STD_LOGIC := '0';
pulse,cycle : OUT STD_LOGIC
);
ATTRIBUTE VITAL_Level0 OF cycloneiii_ram_pulse_generator:ENTITY IS TRUE;
END cycloneiii_ram_pulse_generator;
ARCHITECTURE pgen_arch OF cycloneiii_ram_pulse_generator IS
SIGNAL clk_ipd,ena_ipd : STD_LOGIC;
SIGNAL state : STD_LOGIC;
ATTRIBUTE VITAL_Level0 OF pgen_arch:ARCHITECTURE IS TRUE;
BEGIN
WireDelay : BLOCK
BEGIN
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (ena_ipd, ena, tipd_ena);
END BLOCK;
PROCESS (clk_ipd,state)
BEGIN
IF (state = '1' AND state'EVENT) THEN
state <= '0';
ELSIF (clk_ipd = '1' AND clk_ipd'EVENT AND ena_ipd = '1') THEN
IF (delaywrite = '1') THEN
state <= '1' AFTER 1 NS; -- delayed write
ELSE
state <= '1';
END IF;
END IF;
END PROCESS;
PathDelay : PROCESS
VARIABLE pulse_VitalGlitchData : VitalGlitchDataType;
BEGIN
WAIT UNTIL state'EVENT;
VitalPathDelay01 (
OutSignal => pulse,
OutSignalName => "pulse",
OutTemp => state,
Paths => (0 => (clk_ipd'LAST_EVENT,tpd_clk_pulse_posedge,TRUE)),
GlitchData => pulse_VitalGlitchData,
Mode => DefGlitchMode,
XOn => DefXOnChecks,
MsgOn => DefMsgOnChecks
);
END PROCESS;
cycle <= clk_ipd;
END pgen_arch;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.cycloneiii_atom_pack.all;
USE work.cycloneiii_ram_register;
USE work.cycloneiii_ram_pulse_generator;
ENTITY cycloneiii_ram_block IS
GENERIC (
-- -------- GLOBAL PARAMETERS ---------
operation_mode : STRING := "single_port";
mixed_port_feed_through_mode : STRING := "dont_care";
ram_block_type : STRING := "auto";
logical_ram_name : STRING := "ram_name";
init_file : STRING := "init_file.hex";
init_file_layout : STRING := "none";
data_interleave_width_in_bits : INTEGER := 1;
data_interleave_offset_in_bits : INTEGER := 1;
port_a_logical_ram_depth : INTEGER := 0;
port_a_logical_ram_width : INTEGER := 0;
port_a_first_address : INTEGER := 0;
port_a_last_address : INTEGER := 0;
port_a_first_bit_number : INTEGER := 0;
port_a_address_clear : STRING := "none";
port_a_data_out_clear : STRING := "none";
port_a_data_in_clock : STRING := "clock0";
port_a_address_clock : STRING := "clock0";
port_a_write_enable_clock : STRING := "clock0";
port_a_read_enable_clock : STRING := "clock0";
port_a_byte_enable_clock : STRING := "clock0";
port_a_data_out_clock : STRING := "none";
port_a_data_width : INTEGER := 1;
port_a_address_width : INTEGER := 1;
port_a_byte_enable_mask_width : INTEGER := 1;
port_b_logical_ram_depth : INTEGER := 0;
port_b_logical_ram_width : INTEGER := 0;
port_b_first_address : INTEGER := 0;
port_b_last_address : INTEGER := 0;
port_b_first_bit_number : INTEGER := 0;
port_b_address_clear : STRING := "none";
port_b_data_out_clear : STRING := "none";
port_b_data_in_clock : STRING := "clock1";
port_b_address_clock : STRING := "clock1";
port_b_write_enable_clock: STRING := "clock1";
port_b_read_enable_clock: STRING := "clock1";
port_b_byte_enable_clock : STRING := "clock1";
port_b_data_out_clock : STRING := "none";
port_b_data_width : INTEGER := 1;
port_b_address_width : INTEGER := 1;
port_b_byte_enable_mask_width : INTEGER := 1;
port_a_read_during_write_mode : STRING := "new_data_no_nbe_read";
port_b_read_during_write_mode : STRING := "new_data_no_nbe_read";
power_up_uninitialized : STRING := "false";
port_b_byte_size : INTEGER := 0;
port_a_byte_size : INTEGER := 0;
safe_write : STRING := "err_on_2clk";
init_file_restructured : STRING := "unused";
lpm_type : string := "cycloneiii_ram_block";
lpm_hint : string := "true";
clk0_input_clock_enable : STRING := "none"; -- ena0,ena2,none
clk0_core_clock_enable : STRING := "none"; -- ena0,ena2,none
clk0_output_clock_enable : STRING := "none"; -- ena0,none
clk1_input_clock_enable : STRING := "none"; -- ena1,ena3,none
clk1_core_clock_enable : STRING := "none"; -- ena1,ena3,none
clk1_output_clock_enable : STRING := "none"; -- ena1,none
mem_init0 : BIT_VECTOR := X"0";
mem_init1 : BIT_VECTOR := X"0";
mem_init2 : BIT_VECTOR := X"0";
mem_init3 : BIT_VECTOR := X"0";
mem_init4 : BIT_VECTOR := X"0";
connectivity_checking : string := "off"
);
-- -------- PORT DECLARATIONS ---------
PORT (
portadatain : IN STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0) := (OTHERS => '0');
portaaddr : IN STD_LOGIC_VECTOR(port_a_address_width - 1 DOWNTO 0) := (OTHERS => '0');
portawe : IN STD_LOGIC := '0';
portare : IN STD_LOGIC := '1';
portbdatain : IN STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0) := (OTHERS => '0');
portbaddr : IN STD_LOGIC_VECTOR(port_b_address_width - 1 DOWNTO 0) := (OTHERS => '0');
portbwe : IN STD_LOGIC := '0';
portbre : IN STD_LOGIC := '1';
clk0 : IN STD_LOGIC := '0';
clk1 : IN STD_LOGIC := '0';
ena0 : IN STD_LOGIC := '1';
ena1 : IN STD_LOGIC := '1';
ena2 : IN STD_LOGIC := '1';
ena3 : IN STD_LOGIC := '1';
clr0 : IN STD_LOGIC := '0';
clr1 : IN STD_LOGIC := '0';
portabyteenamasks : IN STD_LOGIC_VECTOR(port_a_byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '1');
portbbyteenamasks : IN STD_LOGIC_VECTOR(port_b_byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '1');
devclrn : IN STD_LOGIC := '1';
devpor : IN STD_LOGIC := '1';
portaaddrstall : IN STD_LOGIC := '0';
portbaddrstall : IN STD_LOGIC := '0';
portadataout : OUT STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0);
portbdataout : OUT STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0)
);
END cycloneiii_ram_block;
ARCHITECTURE block_arch OF cycloneiii_ram_block IS
COMPONENT cycloneiii_ram_pulse_generator
PORT (
clk : IN STD_LOGIC;
ena : IN STD_LOGIC;
delaywrite : IN STD_LOGIC := '0';
pulse : OUT STD_LOGIC;
cycle : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT cycloneiii_ram_register
GENERIC (
preset : STD_LOGIC := '0';
width : integer := 1
);
PORT (
d : IN STD_LOGIC_VECTOR(width - 1 DOWNTO 0);
clk : IN STD_LOGIC;
aclr : IN STD_LOGIC;
devclrn : IN STD_LOGIC;
devpor : IN STD_LOGIC;
ena : IN STD_LOGIC;
stall : IN STD_LOGIC;
q : OUT STD_LOGIC_VECTOR(width - 1 DOWNTO 0);
aclrout : OUT STD_LOGIC
);
END COMPONENT;
FUNCTION cond (condition : BOOLEAN;CONSTANT a,b : INTEGER) RETURN INTEGER IS
VARIABLE c: INTEGER;
BEGIN
IF (condition) THEN c := a; ELSE c := b; END IF;
RETURN c;
END;
SUBTYPE port_type IS BOOLEAN;
CONSTANT primary : port_type := TRUE;
CONSTANT secondary : port_type := FALSE;
CONSTANT primary_port_is_a : BOOLEAN := (port_b_data_width <= port_a_data_width);
CONSTANT primary_port_is_b : BOOLEAN := NOT primary_port_is_a;
CONSTANT mode_is_rom : BOOLEAN := (operation_mode = "rom");
CONSTANT mode_is_sp : BOOLEAN := (operation_mode = "single_port");
CONSTANT mode_is_dp : BOOLEAN := (operation_mode = "dual_port");
CONSTANT mode_is_bdp : BOOLEAN := (operation_mode = "bidir_dual_port");
CONSTANT wired_mode : BOOLEAN := (port_a_address_width = port_b_address_width) AND (port_a_address_width = 1)
AND (port_a_data_width /= port_b_data_width);
CONSTANT num_cols : INTEGER := cond(mode_is_rom OR mode_is_sp,1,
cond(wired_mode,2,2 ** (ABS(port_b_address_width - port_a_address_width))));
CONSTANT data_width : INTEGER := cond(primary_port_is_a,port_a_data_width,port_b_data_width);
CONSTANT data_unit_width : INTEGER := cond(mode_is_rom OR mode_is_sp OR primary_port_is_b,port_a_data_width,port_b_data_width);
CONSTANT address_unit_width : INTEGER := cond(mode_is_rom OR mode_is_sp OR primary_port_is_a,port_a_address_width,port_b_address_width);
CONSTANT address_width : INTEGER := cond(mode_is_rom OR mode_is_sp OR primary_port_is_b,port_a_address_width,port_b_address_width);
CONSTANT byte_size_a : INTEGER := port_a_data_width / port_a_byte_enable_mask_width;
CONSTANT byte_size_b : INTEGER := port_b_data_width / port_b_byte_enable_mask_width;
CONSTANT out_a_is_reg : BOOLEAN := (port_a_data_out_clock /= "none" AND port_a_data_out_clock /= "UNUSED");
CONSTANT out_b_is_reg : BOOLEAN := (port_b_data_out_clock /= "none" AND port_b_data_out_clock /= "UNUSED");
CONSTANT bytes_a_disabled : STD_LOGIC_VECTOR(port_a_byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '0');
CONSTANT bytes_b_disabled : STD_LOGIC_VECTOR(port_b_byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '0');
CONSTANT ram_type : BOOLEAN := FALSE;
TYPE bool_to_std_logic_map IS ARRAY(TRUE DOWNTO FALSE) OF STD_LOGIC;
CONSTANT bool_to_std_logic : bool_to_std_logic_map := ('1','0');
-- Hardware write modes
CONSTANT dual_clock : BOOLEAN := (operation_mode = "dual_port" OR
operation_mode = "bidir_dual_port") AND
(port_b_address_clock = "clock1");
CONSTANT both_new_data_same_port : BOOLEAN := (
((port_a_read_during_write_mode = "new_data_no_nbe_read") OR
(port_a_read_during_write_mode = "dont_care")) AND
((port_b_read_during_write_mode = "new_data_no_nbe_read") OR
(port_b_read_during_write_mode = "dont_care"))
);
SIGNAL hw_write_mode_a : STRING(3 DOWNTO 1);
SIGNAL hw_write_mode_b : STRING(3 DOWNTO 1);
SIGNAL delay_write_pulse_a : STD_LOGIC ;
SIGNAL delay_write_pulse_b : STD_LOGIC ;
CONSTANT be_mask_write_a : BOOLEAN := (port_a_read_during_write_mode = "new_data_with_nbe_read");
CONSTANT be_mask_write_b : BOOLEAN := (port_b_read_during_write_mode = "new_data_with_nbe_read");
CONSTANT old_data_write_a : BOOLEAN := (port_a_read_during_write_mode = "old_data");
CONSTANT old_data_write_b : BOOLEAN := (port_b_read_during_write_mode = "old_data");
SIGNAL read_before_write_a : BOOLEAN;
SIGNAL read_before_write_b : BOOLEAN;
-- -------- internal signals ---------
-- clock / clock enable
SIGNAL clk_a_in,clk_b_in : STD_LOGIC;
SIGNAL clk_a_byteena,clk_b_byteena : STD_LOGIC;
SIGNAL clk_a_out,clk_b_out : STD_LOGIC;
SIGNAL clkena_a_out,clkena_b_out : STD_LOGIC;
SIGNAL clkena_out_c0, clkena_out_c1 : STD_LOGIC;
SIGNAL write_cycle_a,write_cycle_b : STD_LOGIC;
SIGNAL clk_a_rena, clk_a_wena : STD_LOGIC;
SIGNAL clk_a_core : STD_LOGIC;
SIGNAL clk_b_rena, clk_b_wena : STD_LOGIC;
SIGNAL clk_b_core : STD_LOGIC;
SUBTYPE one_bit_bus_type IS STD_LOGIC_VECTOR(0 DOWNTO 0);
-- asynch clear
TYPE clear_mode_type IS ARRAY (port_type'HIGH DOWNTO port_type'LOW) OF BOOLEAN;
TYPE clear_vec_type IS ARRAY (port_type'HIGH DOWNTO port_type'LOW) OF STD_LOGIC;
SIGNAL datain_a_clr,datain_b_clr : STD_LOGIC;
SIGNAL dataout_a_clr,dataout_b_clr : STD_LOGIC;
SIGNAL dataout_a_clr_reg, dataout_b_clr_reg : STD_LOGIC;
SIGNAL dataout_a_clr_reg_in, dataout_b_clr_reg_in : one_bit_bus_type;
SIGNAL dataout_a_clr_reg_out, dataout_b_clr_reg_out : one_bit_bus_type;
SIGNAL dataout_a_clr_reg_latch, dataout_b_clr_reg_latch : STD_LOGIC;
SIGNAL dataout_a_clr_reg_latch_in, dataout_b_clr_reg_latch_in : one_bit_bus_type;
SIGNAL dataout_a_clr_reg_latch_out, dataout_b_clr_reg_latch_out : one_bit_bus_type;
SIGNAL addr_a_clr,addr_b_clr : STD_LOGIC;
SIGNAL byteena_a_clr,byteena_b_clr : STD_LOGIC;
SIGNAL we_a_clr,re_a_clr,we_b_clr,re_b_clr : STD_LOGIC;
SIGNAL datain_a_clr_in,datain_b_clr_in : STD_LOGIC;
SIGNAL addr_a_clr_in,addr_b_clr_in : STD_LOGIC;
SIGNAL byteena_a_clr_in,byteena_b_clr_in : STD_LOGIC;
SIGNAL we_a_clr_in,re_a_clr_in,we_b_clr_in,re_b_clr_in : STD_LOGIC;
SIGNAL mem_invalidate,mem_invalidate_loc,read_latch_invalidate : clear_mode_type;
SIGNAL clear_asserted_during_write : clear_vec_type;
-- port A registers
SIGNAL we_a_reg : STD_LOGIC;
SIGNAL re_a_reg : STD_LOGIC;
SIGNAL we_a_reg_in,we_a_reg_out : one_bit_bus_type;
SIGNAL re_a_reg_in,re_a_reg_out : one_bit_bus_type;
SIGNAL addr_a_reg : STD_LOGIC_VECTOR(port_a_address_width - 1 DOWNTO 0);
SIGNAL datain_a_reg : STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0);
SIGNAL dataout_a_reg : STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0);
SIGNAL dataout_a : STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0);
SIGNAL byteena_a_reg : STD_LOGIC_VECTOR(port_a_byte_enable_mask_width- 1 DOWNTO 0);
-- port B registers
SIGNAL we_b_reg, re_b_reg : STD_LOGIC;
SIGNAL re_b_reg_in,re_b_reg_out,we_b_reg_in,we_b_reg_out : one_bit_bus_type;
SIGNAL addr_b_reg : STD_LOGIC_VECTOR(port_b_address_width - 1 DOWNTO 0);
SIGNAL datain_b_reg : STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0);
SIGNAL dataout_b_reg : STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0);
SIGNAL dataout_b : STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0);
SIGNAL byteena_b_reg : STD_LOGIC_VECTOR(port_b_byte_enable_mask_width- 1 DOWNTO 0);
-- pulses
TYPE pulse_vec IS ARRAY (port_type'HIGH DOWNTO port_type'LOW) OF STD_LOGIC;
SIGNAL write_pulse,read_pulse,read_pulse_feedthru : pulse_vec;
SIGNAL rw_pulse : pulse_vec;
SIGNAL wpgen_a_clk,wpgen_a_clkena,wpgen_b_clk,wpgen_b_clkena : STD_LOGIC;
SIGNAL rpgen_a_clkena,rpgen_b_clkena : STD_LOGIC;
SIGNAL ftpgen_a_clkena,ftpgen_b_clkena : STD_LOGIC;
SIGNAL rwpgen_a_clkena,rwpgen_b_clkena : STD_LOGIC;
-- registered address
SIGNAL addr_prime_reg,addr_sec_reg : INTEGER;
-- input/output
SIGNAL datain_prime_reg,dataout_prime : STD_LOGIC_VECTOR(data_width - 1 DOWNTO 0);
SIGNAL datain_sec_reg,dataout_sec : STD_LOGIC_VECTOR(data_unit_width - 1 DOWNTO 0);
-- overlapping location write
SIGNAL dual_write : BOOLEAN;
-- byte enable mask write
TYPE be_mask_write_vec IS ARRAY (port_type'HIGH DOWNTO port_type'LOW) OF BOOLEAN;
SIGNAL be_mask_write : be_mask_write_vec;
-- memory core
SUBTYPE mem_word_type IS STD_LOGIC_VECTOR (data_width - 1 DOWNTO 0);
SUBTYPE mem_col_type IS STD_LOGIC_VECTOR (data_unit_width - 1 DOWNTO 0);
TYPE mem_row_type IS ARRAY (num_cols - 1 DOWNTO 0) OF mem_col_type;
TYPE mem_type IS ARRAY ((2 ** address_unit_width) - 1 DOWNTO 0) OF mem_row_type;
SIGNAL mem : mem_type;
SIGNAL init_mem : BOOLEAN := FALSE;
CONSTANT mem_x : mem_type := (OTHERS => (OTHERS => (OTHERS => 'X')));
CONSTANT row_x : mem_row_type := (OTHERS => (OTHERS => 'X'));
CONSTANT col_x : mem_col_type := (OTHERS => 'X');
SIGNAL mem_data : mem_row_type;
SIGNAL old_mem_data : mem_row_type;
SIGNAL mem_unit_data : mem_col_type;
-- latches
TYPE read_latch_rec IS RECORD
prime : mem_row_type;
sec : mem_col_type;
END RECORD;
SIGNAL read_latch : read_latch_rec;
-- (row,column) coordinates
SIGNAL row_sec,col_sec : INTEGER;
-- byte enable
TYPE mask_type IS (normal,inverse);
TYPE mask_prime_type IS ARRAY(mask_type'HIGH DOWNTO mask_type'LOW) OF mem_word_type;
TYPE mask_sec_type IS ARRAY(mask_type'HIGH DOWNTO mask_type'LOW) OF mem_col_type;
TYPE mask_rec IS RECORD
prime : mask_prime_type;
sec : mask_sec_type;
END RECORD;
SIGNAL mask_vector : mask_rec;
SIGNAL mask_vector_common : mem_col_type;
FUNCTION get_mask(
b_ena : IN STD_LOGIC_VECTOR;
mode : port_type;
CONSTANT b_ena_width ,byte_size: INTEGER
) RETURN mask_rec IS
VARIABLE l : INTEGER;
VARIABLE mask : mask_rec := (
(normal => (OTHERS => '0'),inverse => (OTHERS => 'X')),
(normal => (OTHERS => '0'),inverse => (OTHERS => 'X'))
);
BEGIN
FOR l in 0 TO b_ena_width - 1 LOOP
IF (b_ena(l) = '0') THEN
IF (mode = primary) THEN
mask.prime(normal) ((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => 'X');
mask.prime(inverse)((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => '0');
ELSE
mask.sec(normal) ((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => 'X');
mask.sec(inverse)((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => '0');
END IF;
ELSIF (b_ena(l) = 'X' OR b_ena(l) = 'U') THEN
IF (mode = primary) THEN
mask.prime(normal) ((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => 'X');
ELSE
mask.sec(normal) ((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => 'X');
END IF;
END IF;
END LOOP;
RETURN mask;
END get_mask;
-- port active for read/write
SIGNAL active_a_core_in_vec,active_b_core_in_vec,active_a_core_out,active_b_core_out : one_bit_bus_type;
SIGNAL active_a_in,active_b_in : STD_LOGIC;
SIGNAL active_write_a : BOOLEAN;
SIGNAL active_write_b : BOOLEAN;
SIGNAL active_b_in_c0,active_b_core_in_c0,active_b_in_c1,active_b_core_in_c1 : STD_LOGIC;
SIGNAL active_a_core_in,active_b_core_in : STD_LOGIC;
SIGNAL active_a_core, active_b_core : BOOLEAN;
SIGNAL wire_vcc : STD_LOGIC := '1';
SIGNAL wire_gnd : STD_LOGIC := '0';
BEGIN
-- memory initialization
init_mem <= TRUE;
-- hardware write modes
hw_write_mode_a <= "R+W" WHEN ((port_a_read_during_write_mode = "old_data") OR
(port_a_read_during_write_mode = "new_data_with_nbe_read")) ELSE
" FW" WHEN (dual_clock OR (
mixed_port_feed_through_mode = "dont_care" AND
both_new_data_same_port
)) ELSE
" DW";
hw_write_mode_b <= "R+W" WHEN ((port_b_read_during_write_mode = "old_data") OR
(port_b_read_during_write_mode = "new_data_with_nbe_read")) ELSE
" FW" WHEN (dual_clock OR (
mixed_port_feed_through_mode = "dont_care" AND
both_new_data_same_port
)) ELSE
" DW";
delay_write_pulse_a <= '1' WHEN (hw_write_mode_a /= " FW") ELSE '0';
delay_write_pulse_b <= '1' WHEN (hw_write_mode_b /= " FW") ELSE '0' ;
read_before_write_a <= (hw_write_mode_a = "R+W");
read_before_write_b <= (hw_write_mode_b = "R+W");
-- -------- core logic ---------------
clk_a_in <= clk0;
clk_a_wena <= '0' WHEN (port_a_write_enable_clock = "none") ELSE clk_a_in;
clk_a_rena <= '0' WHEN (port_a_read_enable_clock = "none") ELSE clk_a_in;
clk_a_byteena <= '0' WHEN (port_a_byte_enable_clock = "none" OR port_a_byte_enable_clock = "UNUSED") ELSE clk_a_in;
clk_a_out <= '0' WHEN (port_a_data_out_clock = "none" OR port_a_data_out_clock = "UNUSED") ELSE
clk0 WHEN (port_a_data_out_clock = "clock0") ELSE clk1;
clk_b_in <= clk0 WHEN (port_b_address_clock = "clock0") ELSE clk1;
clk_b_byteena <= '0' WHEN (port_b_byte_enable_clock = "none" OR port_b_byte_enable_clock = "UNUSED") ELSE
clk0 WHEN (port_b_byte_enable_clock = "clock0") ELSE clk1;
clk_b_wena <= '0' WHEN (port_b_write_enable_clock = "none") ELSE
clk0 WHEN (port_b_write_enable_clock = "clock0") ELSE
clk1;
clk_b_rena <= '0' WHEN (port_b_read_enable_clock = "none") ELSE
clk0 WHEN (port_b_read_enable_clock = "clock0") ELSE
clk1;
clk_b_out <= '0' WHEN (port_b_data_out_clock = "none" OR port_b_data_out_clock = "UNUSED") ELSE
clk0 WHEN (port_b_data_out_clock = "clock0") ELSE clk1;
addr_a_clr_in <= '0' WHEN (port_a_address_clear = "none" OR port_a_address_clear = "UNUSED") ELSE clr0;
addr_b_clr_in <= '0' WHEN (port_b_address_clear = "none" OR port_b_address_clear = "UNUSED") ELSE
clr0 WHEN (port_b_address_clear = "clear0") ELSE clr1;
datain_a_clr_in <= '0';
datain_b_clr_in <= '0';
dataout_a_clr_reg <= '0' WHEN (port_a_data_out_clear = "none" OR port_a_data_out_clear = "UNUSED") ELSE
clr0 WHEN (port_a_data_out_clear = "clear0") ELSE clr1;
dataout_a_clr <= dataout_a_clr_reg WHEN (port_a_data_out_clock = "none" OR port_a_data_out_clock = "UNUSED") ELSE
'0';
dataout_b_clr_reg <= '0' WHEN (port_b_data_out_clear = "none" OR port_b_data_out_clear = "UNUSED") ELSE
clr0 WHEN (port_b_data_out_clear = "clear0") ELSE clr1;
dataout_b_clr <= dataout_b_clr_reg WHEN (port_b_data_out_clock = "none" OR port_b_data_out_clock = "UNUSED") ELSE
'0';
byteena_a_clr_in <= '0';
byteena_b_clr_in <= '0';
we_a_clr_in <= '0';
re_a_clr_in <= '0';
we_b_clr_in <= '0';
re_b_clr_in <= '0';
active_a_in <= '1' WHEN (clk0_input_clock_enable = "none") ELSE
ena0 WHEN (clk0_input_clock_enable = "ena0") ELSE
ena2;
active_a_core_in <= '1' WHEN (clk0_core_clock_enable = "none") ELSE
ena0 WHEN (clk0_core_clock_enable = "ena0") ELSE
ena2;
be_mask_write(primary_port_is_a) <= be_mask_write_a;
be_mask_write(primary_port_is_b) <= be_mask_write_b;
active_b_in_c0 <= '1' WHEN (clk0_input_clock_enable = "none") ELSE
ena0 WHEN (clk0_input_clock_enable = "ena0") ELSE
ena2;
active_b_in_c1 <= '1' WHEN (clk1_input_clock_enable = "none") ELSE
ena1 WHEN (clk1_input_clock_enable = "ena1") ELSE
ena3;
active_b_in <= active_b_in_c0 WHEN (port_b_address_clock = "clock0") ELSE active_b_in_c1;
active_b_core_in_c0 <= '1' WHEN (clk0_core_clock_enable = "none") ELSE
ena0 WHEN (clk0_core_clock_enable = "ena0") ELSE
ena2;
active_b_core_in_c1 <= '1' WHEN (clk1_core_clock_enable = "none") ELSE
ena1 WHEN (clk1_core_clock_enable = "ena1") ELSE
ena3;
active_b_core_in <= active_b_core_in_c0 WHEN (port_b_address_clock = "clock0") ELSE active_b_core_in_c1;
active_write_a <= (byteena_a_reg /= bytes_a_disabled);
active_write_b <= (byteena_b_reg /= bytes_b_disabled);
-- Store core clock enable value for delayed write
-- port A core active
active_a_core_in_vec(0) <= active_a_core_in;
active_core_port_a : cycloneiii_ram_register
GENERIC MAP ( width => 1 )
PORT MAP (
d => active_a_core_in_vec,
clk => clk_a_in,
aclr => wire_gnd,
devclrn => wire_vcc,devpor => wire_vcc,
ena => wire_vcc,
stall => wire_gnd,
q => active_a_core_out
);
active_a_core <= (active_a_core_out(0) = '1');
-- port B core active
active_b_core_in_vec(0) <= active_b_core_in;
active_core_port_b : cycloneiii_ram_register
GENERIC MAP ( width => 1 )
PORT MAP (
d => active_b_core_in_vec,
clk => clk_b_in,
aclr => wire_gnd,
devclrn => wire_vcc,devpor => wire_vcc,
ena => wire_vcc,
stall => wire_gnd,
q => active_b_core_out
);
active_b_core <= (active_b_core_out(0) = '1');
-- ------ A input registers
-- write enable
we_a_reg_in(0) <= '0' WHEN mode_is_rom ELSE portawe;
we_a_register : cycloneiii_ram_register
GENERIC MAP ( width => 1 )
PORT MAP (
d => we_a_reg_in,
clk => clk_a_wena,
aclr => we_a_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => active_a_in,
q => we_a_reg_out,
aclrout => we_a_clr
);
we_a_reg <= we_a_reg_out(0);
-- read enable
re_a_reg_in(0) <= portare;
re_a_register : cycloneiii_ram_register
GENERIC MAP ( width => 1 )
PORT MAP (
d => re_a_reg_in,
clk => clk_a_rena,
aclr => re_a_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => active_a_in,
q => re_a_reg_out,
aclrout => re_a_clr
);
re_a_reg <= re_a_reg_out(0);
-- address
addr_a_register : cycloneiii_ram_register
GENERIC MAP ( width => port_a_address_width )
PORT MAP (
d => portaaddr,
clk => clk_a_in,
aclr => addr_a_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => portaaddrstall,
ena => active_a_in,
q => addr_a_reg,
aclrout => addr_a_clr
);
-- data
datain_a_register : cycloneiii_ram_register
GENERIC MAP ( width => port_a_data_width )
PORT MAP (
d => portadatain,
clk => clk_a_in,
aclr => datain_a_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => active_a_in,
q => datain_a_reg,
aclrout => datain_a_clr
);
-- byte enable
byteena_a_register : cycloneiii_ram_register
GENERIC MAP (
width => port_a_byte_enable_mask_width,
preset => '1'
)
PORT MAP (
d => portabyteenamasks,
clk => clk_a_byteena,
aclr => byteena_a_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => active_a_in,
q => byteena_a_reg,
aclrout => byteena_a_clr
);
-- ------ B input registers
-- read enable
re_b_reg_in(0) <= portbre;
re_b_register : cycloneiii_ram_register
GENERIC MAP (
width => 1
)
PORT MAP (
d => re_b_reg_in,
clk => clk_b_in,
aclr => re_b_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => active_b_in,
q => re_b_reg_out,
aclrout => re_b_clr
);
re_b_reg <= re_b_reg_out(0);
-- write enable
we_b_reg_in(0) <= portbwe;
we_b_register : cycloneiii_ram_register
GENERIC MAP (
width => 1
)
PORT MAP (
d => we_b_reg_in,
clk => clk_b_in,
aclr => we_b_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => active_b_in,
q => we_b_reg_out,
aclrout => we_b_clr
);
we_b_reg <= we_b_reg_out(0);
-- address
addr_b_register : cycloneiii_ram_register
GENERIC MAP ( width => port_b_address_width )
PORT MAP (
d => portbaddr,
clk => clk_b_in,
aclr => addr_b_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => portbaddrstall,
ena => active_b_in,
q => addr_b_reg,
aclrout => addr_b_clr
);
-- data
datain_b_register : cycloneiii_ram_register
GENERIC MAP ( width => port_b_data_width )
PORT MAP (
d => portbdatain,
clk => clk_b_in,
aclr => datain_b_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => active_b_in,
q => datain_b_reg,
aclrout => datain_b_clr
);
-- byte enable
byteena_b_register : cycloneiii_ram_register
GENERIC MAP (
width => port_b_byte_enable_mask_width,
preset => '1'
)
PORT MAP (
d => portbbyteenamasks,
clk => clk_b_byteena,
aclr => byteena_b_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => active_b_in,
q => byteena_b_reg,
aclrout => byteena_b_clr
);
datain_prime_reg <= datain_a_reg WHEN primary_port_is_a ELSE datain_b_reg;
addr_prime_reg <= alt_conv_integer(addr_a_reg) WHEN primary_port_is_a ELSE alt_conv_integer(addr_b_reg);
datain_sec_reg <= (OTHERS => 'U') WHEN (mode_is_rom OR mode_is_sp) ELSE
datain_b_reg WHEN primary_port_is_a ELSE datain_a_reg;
addr_sec_reg <= alt_conv_integer(addr_b_reg) WHEN primary_port_is_a ELSE alt_conv_integer(addr_a_reg);
-- Write pulse generation
wpgen_a_clk <= clk_a_in;
wpgen_a_clkena <= '1' WHEN (active_a_core AND active_write_a AND (we_a_reg = '1')) ELSE '0';
wpgen_a : cycloneiii_ram_pulse_generator
PORT MAP (
clk => wpgen_a_clk,
ena => wpgen_a_clkena,
delaywrite => delay_write_pulse_a,
pulse => write_pulse(primary_port_is_a),
cycle => write_cycle_a
);
wpgen_b_clk <= clk_b_in;
wpgen_b_clkena <= '1' WHEN (active_b_core AND active_write_b AND mode_is_bdp AND (we_b_reg = '1')) ELSE '0';
wpgen_b : cycloneiii_ram_pulse_generator
PORT MAP (
clk => wpgen_b_clk,
ena => wpgen_b_clkena,
delaywrite => delay_write_pulse_b,
pulse => write_pulse(primary_port_is_b),
cycle => write_cycle_b
);
-- Read pulse generation
rpgen_a_clkena <= '1' WHEN (active_a_core AND (re_a_reg = '1') AND (we_a_reg = '0') AND (dataout_a_clr = '0')) ELSE '0';
rpgen_a : cycloneiii_ram_pulse_generator
PORT MAP (
clk => clk_a_in,
ena => rpgen_a_clkena,
cycle => clk_a_core,
pulse => read_pulse(primary_port_is_a)
);
rpgen_b_clkena <= '1' WHEN ((mode_is_dp OR mode_is_bdp) AND active_b_core AND (re_b_reg = '1') AND (we_b_reg = '0') AND (dataout_b_clr = '0')) ELSE '0';
rpgen_b : cycloneiii_ram_pulse_generator
PORT MAP (
clk => clk_b_in,
ena => rpgen_b_clkena,
cycle => clk_b_core,
pulse => read_pulse(primary_port_is_b)
);
-- Read-during-Write pulse generation
rwpgen_a_clkena <= '1' WHEN (active_a_core AND (re_a_reg = '1') AND (we_a_reg = '1') AND read_before_write_a AND (dataout_a_clr = '0')) ELSE '0';
rwpgen_a : cycloneiii_ram_pulse_generator
PORT MAP (
clk => clk_a_in,
ena => rwpgen_a_clkena,
pulse => rw_pulse(primary_port_is_a)
);
rwpgen_b_clkena <= '1' WHEN (active_b_core AND mode_is_bdp AND (re_b_reg = '1') AND (we_b_reg = '1') AND read_before_write_b AND (dataout_b_clr = '0')) ELSE '0';
rwpgen_b : cycloneiii_ram_pulse_generator
PORT MAP (
clk => clk_b_in,
ena => rwpgen_b_clkena,
pulse => rw_pulse(primary_port_is_b)
);
-- Create internal masks for byte enable processing
mask_create : PROCESS (byteena_a_reg,byteena_b_reg)
VARIABLE mask : mask_rec;
BEGIN
IF (byteena_a_reg'EVENT) THEN
mask := get_mask(byteena_a_reg,primary_port_is_a,port_a_byte_enable_mask_width,byte_size_a);
IF (primary_port_is_a) THEN
mask_vector.prime <= mask.prime;
ELSE
mask_vector.sec <= mask.sec;
END IF;
END IF;
IF (byteena_b_reg'EVENT) THEN
mask := get_mask(byteena_b_reg,primary_port_is_b,port_b_byte_enable_mask_width,byte_size_b);
IF (primary_port_is_b) THEN
mask_vector.prime <= mask.prime;
ELSE
mask_vector.sec <= mask.sec;
END IF;
END IF;
END PROCESS mask_create;
-- (row,col) coordinates
row_sec <= addr_sec_reg / num_cols;
col_sec <= addr_sec_reg mod num_cols;
mem_rw : PROCESS (init_mem,
write_pulse,read_pulse,read_pulse_feedthru,
rw_pulse,
dataout_a_clr, dataout_b_clr,
mem_invalidate,mem_invalidate_loc,read_latch_invalidate)
-- mem init
TYPE rw_type IS ARRAY (port_type'HIGH DOWNTO port_type'LOW) OF BOOLEAN;
VARIABLE addr_range_init,row,col,index : INTEGER;
VARIABLE mem_init_std : STD_LOGIC_VECTOR((port_a_last_address - port_a_first_address + 1)*port_a_data_width - 1 DOWNTO 0);
VARIABLE mem_init : bit_vector(mem_init4'length + mem_init3'length + mem_init2'length + mem_init1'length + mem_init0'length - 1 DOWNTO 0);
VARIABLE mem_val : mem_type;
-- read/write
VARIABLE mem_data_p : mem_row_type;
VARIABLE old_mem_data_p : mem_row_type;
VARIABLE row_prime,col_prime : INTEGER;
VARIABLE access_same_location : BOOLEAN;
VARIABLE read_during_write : rw_type;
BEGIN
-- Latch Clear
IF (dataout_a_clr'EVENT AND dataout_a_clr = '1') THEN
IF (primary_port_is_a) THEN
read_latch.prime <= (OTHERS => (OTHERS => '0'));
dataout_prime <= (OTHERS => '0');
ELSE
read_latch.sec <= (OTHERS => '0');
dataout_sec <= (OTHERS => '0');
END IF;
END IF;
IF (dataout_b_clr'EVENT AND dataout_b_clr = '1') THEN
IF (primary_port_is_b) THEN
read_latch.prime <= (OTHERS => (OTHERS => '0'));
dataout_prime <= (OTHERS => '0');
ELSE
read_latch.sec <= (OTHERS => '0');
dataout_sec <= (OTHERS => '0');
END IF;
END IF;
read_during_write := (FALSE,FALSE);
-- Memory initialization
IF (init_mem'EVENT) THEN
-- Initialize output latches to 0
IF (primary_port_is_a) THEN
dataout_prime <= (OTHERS => '0');
IF (mode_is_dp OR mode_is_bdp) THEN dataout_sec <= (OTHERS => '0'); END IF;
ELSE
dataout_sec <= (OTHERS => '0');
IF (mode_is_dp OR mode_is_bdp) THEN dataout_prime <= (OTHERS => '0'); END IF;
END IF;
IF (power_up_uninitialized = "false" AND (NOT ram_type)) THEN
mem_val := (OTHERS => (OTHERS => (OTHERS => '0')));
END IF;
IF (primary_port_is_a) THEN
addr_range_init := port_a_last_address - port_a_first_address + 1;
ELSE
addr_range_init := port_b_last_address - port_b_first_address + 1;
END IF;
IF (init_file_layout = "port_a" OR init_file_layout = "port_b") THEN
mem_init := mem_init4 & mem_init3 & mem_init2 & mem_init1 & mem_init0;
mem_init_std := to_stdlogicvector(mem_init) ((port_a_last_address - port_a_first_address + 1)*port_a_data_width - 1 DOWNTO 0);
FOR row IN 0 TO addr_range_init - 1 LOOP
FOR col IN 0 to num_cols - 1 LOOP
index := row * data_width;
mem_val(row)(col) := mem_init_std(index + (col+1)*data_unit_width -1 DOWNTO
index + col*data_unit_width);
END LOOP;
END LOOP;
END IF;
mem <= mem_val;
END IF;
access_same_location := (mode_is_dp OR mode_is_bdp) AND (addr_prime_reg = row_sec);
-- Read before Write stage 1 : read data from memory
-- Read before Write stage 2 : send data to output
IF (rw_pulse(primary)'EVENT) THEN
IF (rw_pulse(primary) = '1') THEN
read_latch.prime <= mem(addr_prime_reg);
ELSE
IF (be_mask_write(primary)) THEN
FOR i IN 0 TO data_width - 1 LOOP
IF (mask_vector.prime(normal)(i) = 'X') THEN
row_prime := i / data_unit_width; col_prime := i mod data_unit_width;
dataout_prime(i) <= read_latch.prime(row_prime)(col_prime);
END IF;
END LOOP;
ELSE
FOR i IN 0 TO data_width - 1 LOOP
row_prime := i / data_unit_width; col_prime := i mod data_unit_width;
dataout_prime(i) <= read_latch.prime(row_prime)(col_prime);
END LOOP;
END IF;
END IF;
END IF;
IF (rw_pulse(secondary)'EVENT) THEN
IF (rw_pulse(secondary) = '1') THEN
read_latch.sec <= mem(row_sec)(col_sec);
ELSE
IF (be_mask_write(secondary)) THEN
FOR i IN 0 TO data_unit_width - 1 LOOP
IF (mask_vector.sec(normal)(i) = 'X') THEN
dataout_sec(i) <= read_latch.sec(i);
END IF;
END LOOP;
ELSE
dataout_sec <= read_latch.sec;
END IF;
END IF;
END IF;
-- Write stage 1 : X to buffer
-- Write stage 2 : actual data to memory
IF (write_pulse(primary)'EVENT) THEN
IF (write_pulse(primary) = '1') THEN
old_mem_data_p := mem(addr_prime_reg);
mem_data_p := mem(addr_prime_reg);
FOR i IN 0 TO num_cols - 1 LOOP
mem_data_p(i) := mem_data_p(i) XOR
mask_vector.prime(inverse)((i + 1)*data_unit_width - 1 DOWNTO i*data_unit_width);
END LOOP;
read_during_write(secondary) := (access_same_location AND read_pulse(secondary)'EVENT AND read_pulse(secondary) = '1');
IF (read_during_write(secondary)) THEN
read_latch.sec <= old_mem_data_p(col_sec);
ELSE
mem_data <= mem_data_p;
END IF;
ELSIF (clear_asserted_during_write(primary) /= '1') THEN
FOR i IN 0 TO data_width - 1 LOOP
IF (mask_vector.prime(normal)(i) = '0') THEN
mem(addr_prime_reg)(i / data_unit_width)(i mod data_unit_width) <= datain_prime_reg(i);
ELSIF (mask_vector.prime(inverse)(i) = 'X') THEN
mem(addr_prime_reg)(i / data_unit_width)(i mod data_unit_width) <= 'X';
END IF;
END LOOP;
END IF;
END IF;
IF (write_pulse(secondary)'EVENT) THEN
IF (write_pulse(secondary) = '1') THEN
read_during_write(primary) := (access_same_location AND read_pulse(primary)'EVENT AND read_pulse(primary) = '1');
IF (read_during_write(primary)) THEN
read_latch.prime <= mem(addr_prime_reg);
read_latch.prime(col_sec) <= mem(row_sec)(col_sec) XOR mask_vector.sec(inverse);
ELSE
mem_unit_data <= mem(row_sec)(col_sec) XOR mask_vector.sec(inverse);
END IF;
IF (access_same_location AND write_pulse(primary)'EVENT AND write_pulse(primary) = '1') THEN
mask_vector_common <=
mask_vector.prime(inverse)(((col_sec + 1)* data_unit_width - 1) DOWNTO col_sec*data_unit_width) AND
mask_vector.sec(inverse);
dual_write <= TRUE;
END IF;
ELSIF (clear_asserted_during_write(secondary) /= '1') THEN
FOR i IN 0 TO data_unit_width - 1 LOOP
IF (mask_vector.sec(normal)(i) = '0') THEN
mem(row_sec)(col_sec)(i) <= datain_sec_reg(i);
ELSIF (mask_vector.sec(inverse)(i) = 'X') THEN
mem(row_sec)(col_sec)(i) <= 'X';
END IF;
END LOOP;
END IF;
END IF;
-- Simultaneous write
IF (dual_write AND write_pulse = "00") THEN
mem(row_sec)(col_sec) <= mem(row_sec)(col_sec) XOR mask_vector_common;
dual_write <= FALSE;
END IF;
-- Read stage 1 : read data
-- Read stage 2 : send data to output
IF ((NOT read_during_write(primary)) AND read_pulse(primary)'EVENT) THEN
IF (read_pulse(primary) = '1') THEN
read_latch.prime <= mem(addr_prime_reg);
IF (access_same_location AND write_pulse(secondary) = '1') THEN
read_latch.prime(col_sec) <= mem_unit_data;
END IF;
ELSE
FOR i IN 0 TO data_width - 1 LOOP
row_prime := i / data_unit_width; col_prime := i mod data_unit_width;
dataout_prime(i) <= read_latch.prime(row_prime)(col_prime);
END LOOP;
END IF;
END IF;
IF ((NOT read_during_write(secondary)) AND read_pulse(secondary)'EVENT) THEN
IF (read_pulse(secondary) = '1') THEN
IF (access_same_location AND write_pulse(primary) = '1') THEN
read_latch.sec <= mem_data(col_sec);
ELSE
read_latch.sec <= mem(row_sec)(col_sec);
END IF;
ELSE
dataout_sec <= read_latch.sec;
END IF;
END IF;
-- Same port feed thru
IF (read_pulse_feedthru(primary)'EVENT AND read_pulse_feedthru(primary) = '0') THEN
IF (be_mask_write(primary)) THEN
FOR i IN 0 TO data_width - 1 LOOP
IF (mask_vector.prime(normal)(i) = '0') THEN
dataout_prime(i) <= datain_prime_reg(i);
END IF;
END LOOP;
ELSE
dataout_prime <= datain_prime_reg XOR mask_vector.prime(normal);
END IF;
END IF;
IF (read_pulse_feedthru(secondary)'EVENT AND read_pulse_feedthru(secondary) = '0') THEN
IF (be_mask_write(secondary)) THEN
FOR i IN 0 TO data_unit_width - 1 LOOP
IF (mask_vector.sec(normal)(i) = '0') THEN
dataout_sec(i) <= datain_sec_reg(i);
END IF;
END LOOP;
ELSE
dataout_sec <= datain_sec_reg XOR mask_vector.sec(normal);
END IF;
END IF;
-- Async clear
IF (mem_invalidate'EVENT) THEN
IF (mem_invalidate(primary) = TRUE OR mem_invalidate(secondary) = TRUE) THEN
mem <= mem_x;
END IF;
END IF;
IF (mem_invalidate_loc'EVENT) THEN
IF (mem_invalidate_loc(primary)) THEN mem(addr_prime_reg) <= row_x; END IF;
IF (mem_invalidate_loc(secondary)) THEN mem(row_sec)(col_sec) <= col_x; END IF;
END IF;
IF (read_latch_invalidate'EVENT) THEN
IF (read_latch_invalidate(primary)) THEN
read_latch.prime <= row_x;
END IF;
IF (read_latch_invalidate(secondary)) THEN
read_latch.sec <= col_x;
END IF;
END IF;
END PROCESS mem_rw;
-- Same port feed through
ftpgen_a_clkena <= '1' WHEN (active_a_core AND (NOT mode_is_dp) AND (NOT old_data_write_a) AND (we_a_reg = '1') AND (re_a_reg = '1') AND (dataout_a_clr = '0')) ELSE '0';
ftpgen_a : cycloneiii_ram_pulse_generator
PORT MAP (
clk => clk_a_in,
ena => ftpgen_a_clkena,
pulse => read_pulse_feedthru(primary_port_is_a)
);
ftpgen_b_clkena <= '1' WHEN (active_b_core AND mode_is_bdp AND (NOT old_data_write_b) AND (we_b_reg = '1') AND (re_b_reg = '1') AND (dataout_b_clr = '0')) ELSE '0';
ftpgen_b : cycloneiii_ram_pulse_generator
PORT MAP (
clk => clk_b_in,
ena => ftpgen_b_clkena,
pulse => read_pulse_feedthru(primary_port_is_b)
);
-- Asynch clear events
clear_a : PROCESS(addr_a_clr,we_a_clr,datain_a_clr)
BEGIN
IF (addr_a_clr'EVENT AND addr_a_clr = '1') THEN
clear_asserted_during_write(primary_port_is_a) <= write_pulse(primary_port_is_a);
IF (active_write_a AND (write_cycle_a = '1') AND (we_a_reg = '1')) THEN
mem_invalidate(primary_port_is_a) <= TRUE,FALSE AFTER 0.5 ns;
ELSIF (active_a_core AND re_a_reg = '1' AND dataout_a_clr = '0' AND dataout_a_clr_reg_latch = '0') THEN
read_latch_invalidate(primary_port_is_a) <= TRUE,FALSE AFTER 0.5 ns;
END IF;
END IF;
IF ((we_a_clr'EVENT AND we_a_clr = '1') OR (datain_a_clr'EVENT AND datain_a_clr = '1')) THEN
clear_asserted_during_write(primary_port_is_a) <= write_pulse(primary_port_is_a);
IF (active_write_a AND (write_cycle_a = '1') AND (we_a_reg = '1')) THEN
mem_invalidate_loc(primary_port_is_a) <= TRUE,FALSE AFTER 0.5 ns;
read_latch_invalidate(primary_port_is_a) <= TRUE,FALSE AFTER 0.5 ns;
END IF;
END IF;
END PROCESS clear_a;
clear_b : PROCESS(addr_b_clr,we_b_clr,datain_b_clr)
BEGIN
IF (addr_b_clr'EVENT AND addr_b_clr = '1') THEN
clear_asserted_during_write(primary_port_is_b) <= write_pulse(primary_port_is_b);
IF (mode_is_bdp AND active_write_b AND (write_cycle_b = '1') AND (we_b_reg = '1')) THEN
mem_invalidate(primary_port_is_b) <= TRUE,FALSE AFTER 0.5 ns;
ELSIF ((mode_is_dp OR mode_is_bdp) AND active_b_core AND re_b_reg = '1' AND dataout_b_clr = '0' AND dataout_b_clr_reg_latch = '0') THEN
read_latch_invalidate(primary_port_is_b) <= TRUE,FALSE AFTER 0.5 ns;
END IF;
END IF;
IF ((we_b_clr'EVENT AND we_b_clr = '1') OR (datain_b_clr'EVENT AND datain_b_clr = '1')) THEN
clear_asserted_during_write(primary_port_is_b) <= write_pulse(primary_port_is_b);
IF (mode_is_bdp AND active_write_b AND (write_cycle_b = '1') AND (we_b_reg = '1')) THEN
mem_invalidate_loc(primary_port_is_b) <= TRUE,FALSE AFTER 0.5 ns;
read_latch_invalidate(primary_port_is_b) <= TRUE,FALSE AFTER 0.5 ns;
END IF;
END IF;
END PROCESS clear_b;
-- Clear mux registers (Latch Clear)
-- Port A output register clear
dataout_a_clr_reg_latch_in(0) <= dataout_a_clr;
aclr_a_mux_register : cycloneiii_ram_register
GENERIC MAP ( width => 1 )
PORT MAP (
d => dataout_a_clr_reg_latch_in,
clk => clk_a_core,
aclr => wire_gnd,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => wire_vcc,
q => dataout_a_clr_reg_latch_out
);
dataout_a_clr_reg_latch <= dataout_a_clr_reg_latch_out(0);
-- Port B output register clear
dataout_b_clr_reg_latch_in(0) <= dataout_b_clr;
aclr_b_mux_register : cycloneiii_ram_register
GENERIC MAP ( width => 1 )
PORT MAP (
d => dataout_b_clr_reg_latch_in,
clk => clk_b_core,
aclr => wire_gnd,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => wire_vcc,
q => dataout_b_clr_reg_latch_out
);
dataout_b_clr_reg_latch <= dataout_b_clr_reg_latch_out(0);
-- ------ Output registers
clkena_out_c0 <= '1' WHEN (clk0_output_clock_enable = "none") ELSE ena0;
clkena_out_c1 <= '1' WHEN (clk1_output_clock_enable = "none") ELSE ena1;
clkena_a_out <= clkena_out_c0 WHEN (port_a_data_out_clock = "clock0") ELSE clkena_out_c1;
clkena_b_out <= clkena_out_c0 WHEN (port_b_data_out_clock = "clock0") ELSE clkena_out_c1;
dataout_a <= dataout_prime WHEN primary_port_is_a ELSE dataout_sec;
dataout_b <= (OTHERS => 'U') WHEN (mode_is_rom OR mode_is_sp) ELSE
dataout_prime WHEN primary_port_is_b ELSE dataout_sec;
dataout_a_register : cycloneiii_ram_register
GENERIC MAP ( width => port_a_data_width )
PORT MAP (
d => dataout_a,
clk => clk_a_out,
aclr => dataout_a_clr_reg,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => clkena_a_out,
q => dataout_a_reg
);
dataout_b_register : cycloneiii_ram_register
GENERIC MAP ( width => port_b_data_width )
PORT MAP (
d => dataout_b,
clk => clk_b_out,
aclr => dataout_b_clr_reg,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => clkena_b_out,
q => dataout_b_reg
);
portadataout <= dataout_a_reg WHEN out_a_is_reg ELSE dataout_a;
portbdataout <= dataout_b_reg WHEN out_b_is_reg ELSE dataout_b;
END block_arch;
-----------------------------------------------------------------------
--
-- Module Name : cycloneiii_mac_data_reg
--
-- Description : Simulation model for the data input register of
-- Cyclone II MAC_MULT
--
-----------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.VITAL_Primitives.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.std_logic_1164.all;
USE work.cycloneiii_atom_pack.all;
ENTITY cycloneiii_mac_data_reg IS
GENERIC (
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tipd_data : VitalDelayArrayType01(17 downto 0) := (OTHERS => DefPropDelay01);
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_aclr : VitalDelayType01 := DefPropDelay01;
tsetup_data_clk_noedge_posedge : VitalDelayArrayType(17 downto 0) := (OTHERS => DefSetupHoldCnst);
thold_data_clk_noedge_posedge : VitalDelayArrayType(17 downto 0) := (OTHERS => DefSetupHoldCnst);
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_aclr_dataout_posedge : VitalDelayArrayType01(17 downto 0) := (OTHERS => DefPropDelay01);
tpd_clk_dataout_posedge : VitalDelayArrayType01(17 downto 0) := (OTHERS => DefPropDelay01);
data_width : integer := 18
);
PORT (
-- INPUT PORTS
clk : IN std_logic;
data : IN std_logic_vector(17 DOWNTO 0);
ena : IN std_logic;
aclr : IN std_logic;
-- OUTPUT PORTS
dataout : OUT std_logic_vector(17 DOWNTO 0)
);
END cycloneiii_mac_data_reg;
ARCHITECTURE vital_cycloneiii_mac_data_reg OF cycloneiii_mac_data_reg IS
SIGNAL data_ipd : std_logic_vector(17 DOWNTO 0);
SIGNAL aclr_ipd : std_logic;
SIGNAL clk_ipd : std_logic;
SIGNAL ena_ipd : std_logic;
SIGNAL dataout_tmp : std_logic_vector(17 DOWNTO 0) := (OTHERS => '0');
BEGIN
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
g1 : for i in data'range generate
VitalWireDelay (data_ipd(i), data(i), tipd_data(i));
end generate;
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (aclr_ipd, aclr, tipd_aclr);
VitalWireDelay (ena_ipd, ena, tipd_ena);
end block;
process (clk_ipd, aclr_ipd, data_ipd)
begin
if (aclr_ipd = '1') then
dataout_tmp <= (OTHERS => '0');
elsif (clk_ipd'event and clk_ipd = '1' and (ena_ipd = '1')) then
dataout_tmp <= data_ipd;
end if;
end process;
sh: block
begin
g0 : for i in data'range generate
process (data_ipd(i),clk_ipd,ena_ipd)
variable Tviol_data_clk : std_ulogic := '0';
variable TimingData_data_clk : VitalTimingDataType := VitalTimingDataInit;
variable Tviol_ena_clk : std_ulogic := '0';
variable TimingData_ena_clk : VitalTimingDataType := VitalTimingDataInit;
begin
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_data_clk,
TimingData => TimingData_data_clk,
TestSignal => data_ipd(i),
TestSignalName => "DATA(i)",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_data_clk_noedge_posedge(i),
SetupLow => tsetup_data_clk_noedge_posedge(i),
HoldHigh => thold_data_clk_noedge_posedge(i),
HoldLow => thold_data_clk_noedge_posedge(i),
CheckEnabled => TO_X01((aclr) OR
(NOT ena)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/MAC_DATA_REG",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_ena_clk,
TimingData => TimingData_ena_clk,
TestSignal => ena_ipd,
TestSignalName => "ENA",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_ena_clk_noedge_posedge,
SetupLow => tsetup_ena_clk_noedge_posedge,
HoldHigh => thold_ena_clk_noedge_posedge,
HoldLow => thold_ena_clk_noedge_posedge,
CheckEnabled => TO_X01(aclr) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/MAC_DATA_REG",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
end if;
END PROCESS;
end generate g0;
end block;
----------------------
-- Path Delay Section
----------------------
PathDelay : block
begin
g1 : for i in dataout_tmp'range generate
VITALtiming : process (dataout_tmp(i))
variable dataout_VitalGlitchData : VitalGlitchDataType;
begin
VitalPathDelay01 (OutSignal => dataout(i),
OutSignalName => "DATAOUT",
OutTemp => dataout_tmp(i),
Paths => (0 => (clk_ipd'last_event, tpd_clk_dataout_posedge(i), TRUE),
1 => (aclr_ipd'last_event, tpd_aclr_dataout_posedge(i), TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn);
end process;
end generate;
end block;
END vital_cycloneiii_mac_data_reg;
--------------------------------------------------------------------
--
-- Module Name : cycloneiii_mac_sign_reg
--
-- Description : Simulation model for the sign input register of
-- Cyclone II MAC_MULT
--
--------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.VITAL_Primitives.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.std_logic_1164.all;
USE work.cycloneiii_atom_pack.all;
ENTITY cycloneiii_mac_sign_reg IS
GENERIC (
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_aclr_q_posedge : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_aclr : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01
);
PORT (
-- INPUT PORTS
clk : IN std_logic;
d : IN std_logic;
ena : IN std_logic;
aclr : IN std_logic;
-- OUTPUT PORTS
q : OUT std_logic
);
END cycloneiii_mac_sign_reg;
ARCHITECTURE cycloneiii_mac_sign_reg OF cycloneiii_mac_sign_reg IS
signal d_ipd : std_logic;
signal clk_ipd : std_logic;
signal aclr_ipd : std_logic;
signal ena_ipd : std_logic;
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (d_ipd, d, tipd_d);
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (aclr_ipd, aclr, tipd_aclr);
VitalWireDelay (ena_ipd, ena, tipd_ena);
end block;
VITALtiming : process (clk_ipd, aclr_ipd)
variable Tviol_d_clk : std_ulogic := '0';
variable TimingData_d_clk : VitalTimingDataType := VitalTimingDataInit;
variable Tviol_ena_clk : std_ulogic := '0';
variable TimingData_ena_clk : VitalTimingDataType := VitalTimingDataInit;
variable q_VitalGlitchData : VitalGlitchDataType;
variable q_reg : std_logic := '0';
begin
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_d_clk,
TimingData => TimingData_d_clk,
TestSignal => d,
TestSignalName => "D",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_d_clk_noedge_posedge,
SetupLow => tsetup_d_clk_noedge_posedge,
HoldHigh => thold_d_clk_noedge_posedge,
HoldLow => thold_d_clk_noedge_posedge,
CheckEnabled => TO_X01((aclr) OR
(NOT ena)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/SIGN_REG",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_ena_clk,
TimingData => TimingData_ena_clk,
TestSignal => ena,
TestSignalName => "ENA",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_ena_clk_noedge_posedge,
SetupLow => tsetup_ena_clk_noedge_posedge,
HoldHigh => thold_ena_clk_noedge_posedge,
HoldLow => thold_ena_clk_noedge_posedge,
CheckEnabled => TO_X01(aclr) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/SIGN_REG",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
end if;
if (aclr_ipd = '1') then
q_reg := '0';
elsif (clk_ipd'event and clk_ipd = '1' and (ena_ipd = '1')) then
q_reg := d_ipd;
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => q,
OutSignalName => "Q",
OutTemp => q_reg,
Paths => (0 => (clk_ipd'last_event, tpd_clk_q_posedge, TRUE),
1 => (aclr_ipd'last_event, tpd_aclr_q_posedge, TRUE)),
GlitchData => q_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
END cycloneiii_mac_sign_reg;
--------------------------------------------------------------------
--
-- Module Name : cycloneiii_mac_mult_internal
--
-- Description : Cyclone II MAC_MULT_INTERNAL VHDL simulation model
--
--------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.VITAL_Primitives.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_unsigned.all;
USE work.cycloneiii_atom_pack.all;
ENTITY cycloneiii_mac_mult_internal IS
GENERIC (
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tipd_dataa : VitalDelayArrayType01(17 downto 0)
:= (OTHERS => DefPropDelay01);
tipd_datab : VitalDelayArrayType01(17 downto 0)
:= (OTHERS => DefPropDelay01);
tipd_signa : VitalDelayType01 := DefPropDelay01;
tipd_signb : VitalDelayType01 := DefPropDelay01;
tpd_dataa_dataout : VitalDelayArrayType01(18*36 -1 downto 0) :=(others => DefPropDelay01);
tpd_datab_dataout : VitalDelayArrayType01(18*36 -1 downto 0) :=(others => DefPropDelay01);
tpd_signa_dataout : VitalDelayArrayType01(35 downto 0) :=(others => DefPropDelay01);
tpd_signb_dataout : VitalDelayArrayType01(35 downto 0) :=(others => DefPropDelay01);
dataa_width : integer := 18;
datab_width : integer := 18
);
PORT (
dataa : IN std_logic_vector(17 DOWNTO 0) := (OTHERS => '0');
datab : IN std_logic_vector(17 DOWNTO 0) := (OTHERS => '0');
signa : IN std_logic := '1';
signb : IN std_logic := '1';
dataout : OUT std_logic_vector((dataa_width+datab_width)-1 DOWNTO 0)
);
END cycloneiii_mac_mult_internal;
ARCHITECTURE vital_cycloneiii_mac_mult_internal OF cycloneiii_mac_mult_internal IS
-- Internal variables
SIGNAL dataa_ipd : std_logic_vector(17 DOWNTO 0);
SIGNAL datab_ipd : std_logic_vector(17 DOWNTO 0);
SIGNAL signa_ipd : std_logic;
SIGNAL signb_ipd : std_logic;
-- padding with 1's for input negation
SIGNAL reg_aclr : std_logic;
SIGNAL dataout_tmp : STD_LOGIC_VECTOR (dataa_width + datab_width downto 0) := (others => '0');
BEGIN
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
g1 : for i in dataa'range generate
VitalWireDelay (dataa_ipd(i), dataa(i), tipd_dataa(i));
end generate;
g2 : for i in datab'range generate
VitalWireDelay (datab_ipd(i), datab(i), tipd_datab(i));
end generate;
VitalWireDelay (signa_ipd, signa, tipd_signa);
VitalWireDelay (signb_ipd, signb, tipd_signb);
end block;
VITALtiming : process(dataa_ipd, datab_ipd, signa_ipd, signb_ipd)
begin
if((signa_ipd = '0') and (signb_ipd = '1')) then
dataout_tmp <=
unsigned(dataa_ipd(dataa_width-1 downto 0)) *
signed(datab_ipd(datab_width-1 downto 0));
elsif((signa_ipd = '1') and (signb_ipd = '0')) then
dataout_tmp <=
signed(dataa_ipd(dataa_width-1 downto 0)) *
unsigned(datab_ipd(datab_width-1 downto 0));
elsif((signa_ipd = '1') and (signb_ipd = '1')) then
dataout_tmp(dataout'range) <=
signed(dataa_ipd(dataa_width-1 downto 0)) *
signed(datab_ipd(datab_width-1 downto 0));
else --((signa_ipd = '0') and (signb_ipd = '0')) then
dataout_tmp(dataout'range) <=
unsigned(dataa_ipd(dataa_width-1 downto 0)) *
unsigned(datab_ipd(datab_width-1 downto 0));
end if;
end process;
----------------------
-- Path Delay Section
----------------------
PathDelay : block
begin
g1 : for i in dataout'range generate
VITALtiming : process (dataout_tmp(i))
variable dataout_VitalGlitchData : VitalGlitchDataType;
begin
VitalPathDelay01 (OutSignal => dataout(i),
OutSignalName => "dataout",
OutTemp => dataout_tmp(i),
Paths => (0 => (dataa_ipd'last_event, tpd_dataa_dataout(i), TRUE),
1 => (datab_ipd'last_event, tpd_datab_dataout(i), TRUE),
2 => (signa'last_event, tpd_signa_dataout(i), TRUE),
3 => (signb'last_event, tpd_signb_dataout(i), TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
MsgOn => FALSE,
XOn => TRUE );
end process;
end generate;
end block;
END vital_cycloneiii_mac_mult_internal;
--------------------------------------------------------------------
--
-- Module Name : cycloneiii_mac_mult
--
-- Description : Cyclone II MAC_MULT VHDL simulation model
--
--------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.VITAL_Primitives.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_unsigned.all;
USE work.cycloneiii_atom_pack.all;
USE work.cycloneiii_mac_data_reg;
USE work.cycloneiii_mac_sign_reg;
USE work.cycloneiii_mac_mult_internal;
ENTITY cycloneiii_mac_mult IS
GENERIC (
dataa_width : integer := 18;
datab_width : integer := 18;
dataa_clock : string := "none";
datab_clock : string := "none";
signa_clock : string := "none";
signb_clock : string := "none";
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
lpm_hint : string := "true";
lpm_type : string := "cycloneiii_mac_mult"
);
PORT (
dataa : IN std_logic_vector(dataa_width-1 DOWNTO 0) := (OTHERS => '0');
datab : IN std_logic_vector(datab_width-1 DOWNTO 0) := (OTHERS => '0');
signa : IN std_logic := '1';
signb : IN std_logic := '1';
clk : IN std_logic := '0';
aclr : IN std_logic := '0';
ena : IN std_logic := '0';
dataout : OUT std_logic_vector((dataa_width+datab_width)-1 DOWNTO 0);
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END cycloneiii_mac_mult;
ARCHITECTURE vital_cycloneiii_mac_mult OF cycloneiii_mac_mult IS
COMPONENT cycloneiii_mac_data_reg
GENERIC (
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tipd_data : VitalDelayArrayType01(17 downto 0) := (OTHERS => DefPropDelay01);
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_aclr : VitalDelayType01 := DefPropDelay01;
tsetup_data_clk_noedge_posedge : VitalDelayArrayType(17 downto 0) := (OTHERS => DefSetupHoldCnst);
thold_data_clk_noedge_posedge : VitalDelayArrayType(17 downto 0) := (OTHERS => DefSetupHoldCnst);
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_aclr_dataout_posedge : VitalDelayArrayType01(17 downto 0) := (OTHERS => DefPropDelay01);
tpd_clk_dataout_posedge : VitalDelayArrayType01(17 downto 0) := (OTHERS => DefPropDelay01);
data_width : integer := 18
);
PORT (
-- INPUT PORTS
clk : IN std_logic;
data : IN std_logic_vector(17 DOWNTO 0);
ena : IN std_logic;
aclr : IN std_logic;
-- OUTPUT PORTS
dataout : OUT std_logic_vector(17 DOWNTO 0)
);
END COMPONENT;
COMPONENT cycloneiii_mac_sign_reg
GENERIC (
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_aclr_q_posedge : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_aclr : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01
);
PORT (
-- INPUT PORTS
clk : IN std_logic;
d : IN std_logic;
ena : IN std_logic;
aclr : IN std_logic;
-- OUTPUT PORTS
q : OUT std_logic
);
END COMPONENT;
COMPONENT cycloneiii_mac_mult_internal
GENERIC (
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tipd_dataa : VitalDelayArrayType01(17 downto 0)
:= (OTHERS => DefPropDelay01);
tipd_datab : VitalDelayArrayType01(17 downto 0)
:= (OTHERS => DefPropDelay01);
tipd_signa : VitalDelayType01 := DefPropDelay01;
tipd_signb : VitalDelayType01 := DefPropDelay01;
tpd_dataa_dataout : VitalDelayArrayType01(18*36 -1 downto 0) :=(others => DefPropDelay01);
tpd_datab_dataout : VitalDelayArrayType01(18*36 -1 downto 0) :=(others => DefPropDelay01);
tpd_signa_dataout : VitalDelayArrayType01(35 downto 0) :=(others => DefPropDelay01);
tpd_signb_dataout : VitalDelayArrayType01(35 downto 0) :=(others => DefPropDelay01);
dataa_width : integer := 18;
datab_width : integer := 18
);
PORT (
dataa : IN std_logic_vector(17 DOWNTO 0) := (OTHERS => '0');
datab : IN std_logic_vector(17 DOWNTO 0) := (OTHERS => '0');
signa : IN std_logic := '1';
signb : IN std_logic := '1';
dataout : OUT std_logic_vector((dataa_width+datab_width)-1 DOWNTO 0)
);
END COMPONENT;
-- Internal variables
SIGNAL dataa_ipd : std_logic_vector(17 DOWNTO 0);
SIGNAL datab_ipd : std_logic_vector(17 DOWNTO 0);
SIGNAL idataa_reg : std_logic_vector(17 DOWNTO 0); -- optional register for dataa input
SIGNAL idatab_reg : std_logic_vector(17 DOWNTO 0); -- optional register for datab input
SIGNAL isigna_reg : std_logic; -- optional register for signa input
SIGNAL isignb_reg : std_logic; -- optional register for signb input
SIGNAL idataa_int : std_logic_vector(17 DOWNTO 0); -- dataa as seen by the multiplier input
SIGNAL idatab_int : std_logic_vector(17 DOWNTO 0); -- datab as seen by the multiplier input
SIGNAL isigna_int : std_logic; -- signa as seen by the multiplier input
SIGNAL isignb_int : std_logic; -- signb as seen by the multiplier input
-- padding with 1's for input negation
SIGNAL reg_aclr : std_logic;
SIGNAL dataout_tmp : STD_LOGIC_VECTOR (dataa_width + datab_width downto 0) := (others => '0');
BEGIN
---------------------
-- INPUT PATH DELAYs
---------------------
reg_aclr <= (NOT devpor) OR (NOT devclrn) OR (aclr) ;
-- padding input data to full bus width
dataa_ipd(dataa_width-1 downto 0) <= dataa;
datab_ipd(datab_width-1 downto 0) <= datab;
-- Optional input registers for dataa,b and signa,b
dataa_reg : cycloneiii_mac_data_reg
GENERIC MAP (
data_width => dataa_width)
PORT MAP (
clk => clk,
data => dataa_ipd,
ena => ena,
aclr => reg_aclr,
dataout => idataa_reg);
datab_reg : cycloneiii_mac_data_reg
GENERIC MAP (
data_width => datab_width)
PORT MAP (
clk => clk,
data => datab_ipd,
ena => ena,
aclr => reg_aclr,
dataout => idatab_reg);
signa_reg : cycloneiii_mac_sign_reg
PORT MAP (
clk => clk,
d => signa,
ena => ena,
aclr => reg_aclr,
q => isigna_reg);
signb_reg : cycloneiii_mac_sign_reg
PORT MAP (
clk => clk,
d => signb,
ena => ena,
aclr => reg_aclr,
q => isignb_reg);
idataa_int <= dataa_ipd WHEN (dataa_clock = "none") ELSE idataa_reg;
idatab_int <= datab_ipd WHEN (datab_clock = "none") ELSE idatab_reg;
isigna_int <= signa WHEN (signa_clock = "none") ELSE isigna_reg;
isignb_int <= signb WHEN (signb_clock = "none") ELSE isignb_reg;
mac_multiply : cycloneiii_mac_mult_internal
GENERIC MAP (
dataa_width => dataa_width,
datab_width => datab_width
)
PORT MAP (
dataa => idataa_int,
datab => idatab_int,
signa => isigna_int,
signb => isignb_int,
dataout => dataout
);
END vital_cycloneiii_mac_mult;
--------------------------------------------------------------------
--
-- Module Name : cycloneiii_mac_out
--
-- Description : Cyclone II MAC_OUT VHDL simulation model
--
--------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.VITAL_Primitives.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.std_logic_1164.all;
USE work.cycloneiii_atom_pack.all;
ENTITY cycloneiii_mac_out IS
GENERIC (
dataa_width : integer := 1;
output_clock : string := "none";
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tipd_dataa : VitalDelayArrayType01(35 downto 0)
:= (OTHERS => DefPropDelay01);
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_aclr : VitalDelayType01 := DefPropDelay01;
tpd_dataa_dataout :VitalDelayArrayType01(36*36 -1 downto 0) :=(others => DefPropDelay01);
tpd_aclr_dataout_posedge : VitalDelayArrayType01(35 downto 0) :=(others => DefPropDelay01);
tpd_clk_dataout_posedge :VitalDelayArrayType01(35 downto 0) :=(others => DefPropDelay01);
tsetup_dataa_clk_noedge_posedge : VitalDelayArrayType(35 downto 0) := (OTHERS => DefSetupHoldCnst);
thold_dataa_clk_noedge_posedge : VitalDelayArrayType(35 downto 0) := (OTHERS => DefSetupHoldCnst);
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
lpm_hint : string := "true";
lpm_type : string := "cycloneiii_mac_out");
PORT (
dataa : IN std_logic_vector(dataa_width-1 DOWNTO 0) := (OTHERS => '0');
clk : IN std_logic := '0';
aclr : IN std_logic := '0';
ena : IN std_logic := '1';
dataout : OUT std_logic_vector(dataa_width-1 DOWNTO 0);
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END cycloneiii_mac_out;
ARCHITECTURE vital_cycloneiii_mac_out OF cycloneiii_mac_out IS
-- internal variables
SIGNAL dataa_ipd : std_logic_vector(dataa'range);
SIGNAL clk_ipd : std_logic;
SIGNAL aclr_ipd : std_logic;
SIGNAL ena_ipd : std_logic;
-- optional register
SIGNAL use_reg : std_logic;
SIGNAL dataout_tmp : std_logic_vector(dataout'range) := (OTHERS => '0');
BEGIN
---------------------
-- PATH DELAYs
---------------------
WireDelay : block
begin
g1 : for i in dataa'range generate
VitalWireDelay (dataa_ipd(i), dataa(i), tipd_dataa(i));
VITALtiming : process (clk_ipd, aclr_ipd, dataout_tmp(i))
variable dataout_VitalGlitchData : VitalGlitchDataType;
begin
VitalPathDelay01 (
OutSignal => dataout(i),
OutSignalName => "DATAOUT",
OutTemp => dataout_tmp(i),
Paths => (0 => (clk_ipd'last_event, tpd_clk_dataout_posedge(i), use_reg = '1'),
1 => (aclr_ipd'last_event, tpd_aclr_dataout_posedge(i), use_reg = '1'),
2 => (dataa_ipd(i)'last_event, tpd_dataa_dataout(i), use_reg = '0')),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end generate;
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (aclr_ipd, aclr, tipd_aclr);
VitalWireDelay (ena_ipd, ena, tipd_ena);
end block;
use_reg <= '1' WHEN (output_clock /= "none") ELSE '0';
sh: block
begin
g0 : for i in dataa'range generate
VITALtiming : process (clk_ipd, ena_ipd, dataa_ipd(i))
variable Tviol_dataa_clk : std_ulogic := '0';
variable TimingData_dataa_clk : VitalTimingDataType := VitalTimingDataInit;
variable Tviol_ena_clk : std_ulogic := '0';
variable TimingData_ena_clk : VitalTimingDataType := VitalTimingDataInit;
begin
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_dataa_clk,
TimingData => TimingData_dataa_clk,
TestSignal => dataa(i),
TestSignalName => "D",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_dataa_clk_noedge_posedge(i),
SetupLow => tsetup_dataa_clk_noedge_posedge(i),
HoldHigh => thold_dataa_clk_noedge_posedge(i),
HoldLow => thold_dataa_clk_noedge_posedge(i),
CheckEnabled => TO_X01((aclr) OR (NOT use_reg) OR
(NOT ena)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/MAC_DATA_REG",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_ena_clk,
TimingData => TimingData_ena_clk,
TestSignal => ena,
TestSignalName => "ENA",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_ena_clk_noedge_posedge,
SetupLow => tsetup_ena_clk_noedge_posedge,
HoldHigh => thold_ena_clk_noedge_posedge,
HoldLow => thold_ena_clk_noedge_posedge,
CheckEnabled => TO_X01((aclr) OR
(NOT use_reg)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/MAC_DATA_REG",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
end if;
END PROCESS;
end generate g0;
end block;
process (clk_ipd, aclr_ipd,ena_ipd, dataa_ipd)
begin
if (use_reg = '0') then
dataout_tmp <= dataa_ipd;
else
if (aclr_ipd = '1') then
dataout_tmp <= (OTHERS => '0');
elsif (clk_ipd'event and clk_ipd = '1' and (ena_ipd = '1')) then
dataout_tmp <= dataa_ipd;
end if;
end if;
end process;
END vital_cycloneiii_mac_out;
---------------------------------------------------------------------
--
-- Entity Name : cycloneiii_io_ibuf
--
-- Description : Cyclone III IO Ibuf VHDL simulation model
--
--
---------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.cycloneiii_atom_pack.all;
ENTITY cycloneiii_io_ibuf IS
GENERIC (
tipd_i : VitalDelayType01 := DefPropDelay01;
tipd_ibar : VitalDelayType01 := DefPropDelay01;
tpd_i_o : VitalDelayType01 := DefPropDelay01;
tpd_ibar_o : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
differential_mode : string := "false";
bus_hold : string := "false";
simulate_z_as : string := "Z";
lpm_type : string := "cycloneiii_io_ibuf"
);
PORT (
i : IN std_logic := '0';
ibar : IN std_logic := '0';
o : OUT std_logic
);
END cycloneiii_io_ibuf;
ARCHITECTURE arch OF cycloneiii_io_ibuf IS
SIGNAL i_ipd : std_logic := '0';
SIGNAL ibar_ipd : std_logic := '0';
SIGNAL o_tmp : std_logic;
SIGNAL out_tmp : std_logic;
SIGNAL prev_value : std_logic := '0';
BEGIN
WireDelay : block
begin
VitalWireDelay (i_ipd, i, tipd_i);
VitalWireDelay (ibar_ipd, ibar, tipd_ibar);
end block;
PROCESS(i_ipd, ibar_ipd)
BEGIN
IF (differential_mode = "false") THEN
IF (i_ipd = '1') THEN
o_tmp <= '1';
prev_value <= '1';
ELSIF (i_ipd = '0') THEN
o_tmp <= '0';
prev_value <= '0';
ELSE
o_tmp <= i_ipd;
END IF;
ELSE
IF (( i_ipd = '0' ) and (ibar_ipd = '1')) then
o_tmp <= '0';
ELSIF (( i_ipd = '1' ) and (ibar_ipd = '0')) then
o_tmp <= '1';
ELSIF((( i_ipd = '1' ) and (ibar_ipd = '1')) or (( i_ipd = '0' ) and (ibar_ipd = '0')))then
o_tmp <= 'X';
ELSE
o_tmp <= 'X';
END IF;
END IF;
END PROCESS;
out_tmp <= prev_value when (bus_hold = "true") else
'Z' when((o_tmp = 'Z') AND (simulate_z_as = "Z")) else
'X' when((o_tmp = 'Z') AND (simulate_z_as = "X")) else
'1' when((o_tmp = 'Z') AND (simulate_z_as = "vcc")) else
'0' when((o_tmp = 'Z') AND (simulate_z_as = "gnd")) else
o_tmp;
----------------------
-- Path Delay Section
----------------------
PROCESS( out_tmp)
variable output_VitalGlitchData : VitalGlitchDataType;
BEGIN
VitalPathDelay01 (
OutSignal => o,
OutSignalName => "o",
OutTemp => out_tmp,
Paths => (0 => (i_ipd'last_event, tpd_i_o, TRUE),
1 => (ibar_ipd'last_event, tpd_ibar_o, TRUE)),
GlitchData => output_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn
);
END PROCESS;
END arch;
---------------------------------------------------------------------
--
-- Entity Name : cycloneiii_io_obuf
--
-- Description : Cyclone III IO Obuf VHDL simulation model
--
--
---------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.cycloneiii_atom_pack.all;
ENTITY cycloneiii_io_obuf IS
GENERIC (
tipd_i : VitalDelayType01 := DefPropDelay01;
tipd_oe : VitalDelayType01 := DefPropDelay01;
tipd_seriesterminationcontrol : VitalDelayArrayType01(15 DOWNTO 0) := (others => DefPropDelay01 );
tpd_i_o : VitalDelayType01 := DefPropDelay01;
tpd_oe_o : VitalDelayType01 := DefPropDelay01;
tpd_i_obar : VitalDelayType01 := DefPropDelay01;
tpd_oe_obar : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
open_drain_output : string := "false";
bus_hold : string := "false";
lpm_type : string := "cycloneiii_io_obuf"
);
PORT (
i : IN std_logic := '0';
oe : IN std_logic := '1';
seriesterminationcontrol : IN std_logic_vector(15 DOWNTO 0) := (others => '0');
devoe : IN std_logic := '1';
o : OUT std_logic;
obar : OUT std_logic
);
END cycloneiii_io_obuf;
ARCHITECTURE arch OF cycloneiii_io_obuf IS
--INTERNAL Signals
SIGNAL i_ipd : std_logic := '0';
SIGNAL oe_ipd : std_logic := '0';
SIGNAL out_tmp : std_logic := 'Z';
SIGNAL out_tmp_bar : std_logic;
SIGNAL prev_value : std_logic := '0';
SIGNAL o_tmp : std_logic;
SIGNAL obar_tmp : std_logic;
SIGNAL o_tmp1 : std_logic;
SIGNAL obar_tmp1 : std_logic;
SIGNAL seriesterminationcontrol_ipd : std_logic_vector(15 DOWNTO 0) := (others => '0');
BEGIN
WireDelay : block
begin
VitalWireDelay (i_ipd, i, tipd_i);
VitalWireDelay (oe_ipd, oe, tipd_oe);
g1 :for i in seriesterminationcontrol'range generate
VitalWireDelay (seriesterminationcontrol_ipd(i), seriesterminationcontrol(i), tipd_seriesterminationcontrol(i));
end generate;
end block;
PROCESS( i_ipd, oe_ipd)
BEGIN
IF (oe_ipd = '1') THEN
IF (open_drain_output = "true") THEN
IF (i_ipd = '0') THEN
out_tmp <= '0';
out_tmp_bar <= '1';
prev_value <= '0';
ELSE
out_tmp <= 'Z';
out_tmp_bar <= 'Z';
END IF;
ELSE
IF (i_ipd = '0') THEN
out_tmp <= '0';
out_tmp_bar <= '1';
prev_value <= '0';
ELSE
IF (i_ipd = '1') THEN
out_tmp <= '1';
out_tmp_bar <= '0';
prev_value <= '1';
ELSE
out_tmp <= i_ipd;
out_tmp_bar <= i_ipd;
END IF;
END IF;
END IF;
ELSE
IF (oe_ipd = '0') THEN
out_tmp <= 'Z';
out_tmp_bar <= 'Z';
ELSE
out_tmp <= 'X';
out_tmp_bar <= 'X';
END IF;
END IF;
END PROCESS;
o_tmp1 <= prev_value WHEN (bus_hold = "true") ELSE out_tmp;
obar_tmp1 <= NOT prev_value WHEN (bus_hold = "true") ELSE out_tmp_bar;
o_tmp <= o_tmp1 WHEN (devoe = '1') ELSE 'Z';
obar_tmp <= obar_tmp1 WHEN (devoe = '1') ELSE 'Z';
---------------------
-- Path Delay Section
----------------------
PROCESS( o_tmp,obar_tmp)
variable o_VitalGlitchData : VitalGlitchDataType;
variable obar_VitalGlitchData : VitalGlitchDataType;
BEGIN
VitalPathDelay01 (
OutSignal => o,
OutSignalName => "o",
OutTemp => o_tmp,
Paths => (0 => (i_ipd'last_event, tpd_i_o, TRUE),
1 => (oe_ipd'last_event, tpd_oe_o, TRUE)),
GlitchData => o_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn
);
VitalPathDelay01 (
OutSignal => obar,
OutSignalName => "obar",
OutTemp => obar_tmp,
Paths => (0 => (i_ipd'last_event, tpd_i_obar, TRUE),
1 => (oe_ipd'last_event, tpd_oe_obar, TRUE)),
GlitchData => obar_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn
);
END PROCESS;
END arch;
---------------------------------------------------------------------
--
-- Entity Name : cycloneiii_ddio_oe
--
-- Description : Cyclone III DDIO_OE VHDL simulation model
--
--
---------------------------------------------------------------------
LIBRARY IEEE;
LIBRARY altera;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use altera.all;
use work.cycloneiii_atom_pack.all;
ENTITY cycloneiii_ddio_oe IS
generic(
tipd_oe : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_areset : VitalDelayType01 := DefPropDelay01;
tipd_sreset : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
power_up : string := "low";
async_mode : string := "none";
sync_mode : string := "none";
lpm_type : string := "cycloneiii_ddio_oe"
);
PORT (
oe : IN std_logic := '1';
clk : IN std_logic := '0';
ena : IN std_logic := '1';
areset : IN std_logic := '0';
sreset : IN std_logic := '0';
dataout : OUT std_logic;
dfflo : OUT std_logic;
dffhi : OUT std_logic;
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END cycloneiii_ddio_oe;
ARCHITECTURE arch OF cycloneiii_ddio_oe IS
component cycloneiii_mux21
generic(
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
InstancePath: STRING := "*";
tpd_A_MO : VitalDelayType01 := DefPropDelay01;
tpd_B_MO : VitalDelayType01 := DefPropDelay01;
tpd_S_MO : VitalDelayType01 := DefPropDelay01;
tipd_A : VitalDelayType01 := DefPropDelay01;
tipd_B : VitalDelayType01 := DefPropDelay01;
tipd_S : VitalDelayType01 := DefPropDelay01
);
port (
A : in std_logic := '0';
B : in std_logic := '0';
S : in std_logic := '0';
MO : out std_logic
);
end component;
component dffeas
generic (
power_up : string := "DONT_CARE";
is_wysiwyg : string := "false";
x_on_violation : string := "on";
lpm_type : string := "DFFEAS";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clrn_q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_prn_q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_aload_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_asdata_q: VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_asdata : VitalDelayType01 := DefPropDelay01;
tipd_sclr : VitalDelayType01 := DefPropDelay01;
tipd_sload : VitalDelayType01 := DefPropDelay01;
tipd_clrn : VitalDelayType01 := DefPropDelay01;
tipd_prn : VitalDelayType01 := DefPropDelay01;
tipd_aload : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*"
);
port (
d : in std_logic := '0';
clk : in std_logic := '0';
ena : in std_logic := '1';
clrn : in std_logic := '1';
prn : in std_logic := '1';
aload : in std_logic := '0';
asdata : in std_logic := '1';
sclr : in std_logic := '0';
sload : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
q : out std_logic
);
end component;
--Internal Signals
SIGNAL oe_ipd : std_logic := '0';
SIGNAL clk_ipd : std_logic := '0';
SIGNAL ena_ipd : std_logic := '0';
SIGNAL areset_ipd : std_logic := '0';
SIGNAL sreset_ipd : std_logic := '0';
SIGNAL ddioreg_aclr : std_logic;
SIGNAL ddioreg_prn : std_logic;
SIGNAL ddioreg_adatasdata : std_logic;
SIGNAL ddioreg_sclr : std_logic;
SIGNAL ddioreg_sload : std_logic;
SIGNAL dfflo_tmp : std_logic;
SIGNAL dffhi_tmp : std_logic;
signal nclk : std_logic;
signal dataout_tmp : std_logic;
BEGIN
WireDelay : block
begin
VitalWireDelay (oe_ipd, oe, tipd_oe);
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (ena_ipd, ena, tipd_ena);
VitalWireDelay (areset_ipd, areset, tipd_areset);
VitalWireDelay (sreset_ipd, sreset, tipd_sreset);
end block;
nclk <= NOT clk_ipd;
PROCESS
BEGIN
WAIT UNTIL areset_ipd'EVENT OR sreset_ipd'EVENT;
IF (async_mode = "clear") THEN
ddioreg_aclr <= NOT areset_ipd;
ddioreg_prn <= '1';
ELSIF (async_mode = "preset") THEN
ddioreg_aclr <= '1';
ddioreg_prn <= NOT areset_ipd;
ELSE
ddioreg_aclr <= '1';
ddioreg_prn <= '1';
END IF;
IF (sync_mode = "clear") THEN
ddioreg_adatasdata <= '0';
ddioreg_sclr <= sreset_ipd;
ddioreg_sload <= '0';
ELSIF (sync_mode = "preset") THEN
ddioreg_adatasdata <= '1';
ddioreg_sclr <= '0';
ddioreg_sload <= sreset_ipd;
ELSE
ddioreg_adatasdata <= '0';
ddioreg_sclr <= '0';
ddioreg_sload <= '0';
END IF;
END PROCESS;
ddioreg_hi : dffeas
GENERIC MAP (
power_up => power_up
)
PORT MAP (
d => oe_ipd,
clk => clk_ipd,
clrn => ddioreg_aclr,
prn => ddioreg_prn,
sclr => ddioreg_sclr,
sload => ddioreg_sload,
asdata => ddioreg_adatasdata,
ena => ena_ipd,
q => dffhi_tmp,
devpor => devpor,
devclrn => devclrn
);
--DDIO Low Register
ddioreg_lo : dffeas
GENERIC MAP (
power_up => power_up
)
PORT MAP (
d => dffhi_tmp,
clk => nclk,
clrn => ddioreg_aclr,
prn => ddioreg_prn,
sclr => ddioreg_sclr,
sload => ddioreg_sload,
asdata => ddioreg_adatasdata,
ena => ena_ipd,
q => dfflo_tmp,
devpor => devpor,
devclrn => devclrn
);
--registered output
or_gate : cycloneiii_mux21
port map (
A => dffhi_tmp,
B => dfflo_tmp,
S => dfflo_tmp,
MO => dataout
);
dfflo <= dfflo_tmp ;
dffhi <= dffhi_tmp ;
END arch;
---------------------------------------------------------------------
--
-- Entity Name : cycloneiii_latch
--
-- Description : Cyclone III latch VHDL simulation model
--
--
---------------------------------------------------------------------
Library ieee;
use ieee.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.cycloneiii_atom_pack.all;
entity cycloneiii_latch is
generic(
is_wysiwyg : string := "false";
x_on_violation : string := "on";
lpm_type : string := "cycloneiii_latch";
tsetup_d_ena_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
thold_d_ena_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
tpd_d_q : VitalDelayType01 := DefPropDelay01;
tpd_ena_q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_clr_q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_pre_q_negedge : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_clr : VitalDelayType01 := DefPropDelay01;
tipd_pre : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*"
);
port(
d : in std_logic := '0';
ena : in std_logic := '1';
clr : in std_logic := '1';
pre : in std_logic := '1';
q : out std_logic
);
attribute VITAL_LEVEL0 of cycloneiii_latch : entity is TRUE;
end cycloneiii_latch;
architecture vital_latch of cycloneiii_latch is
attribute VITAL_LEVEL0 of vital_latch : architecture is TRUE;
signal d_ipd : std_logic;
signal d_dly : std_logic;
signal clr_ipd : std_logic;
signal pre_ipd : std_logic;
signal ena_ipd : std_logic;
begin
d_dly <= d_ipd;
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (d_ipd, d, tipd_d);
VitalWireDelay (clr_ipd, clr, tipd_clr);
VitalWireDelay (pre_ipd, pre, tipd_pre);
VitalWireDelay (ena_ipd, ena, tipd_ena);
end block;
VITALtiming : process ( d_dly, clr_ipd, pre_ipd,ena_ipd)
variable Tviol_d_ena : std_ulogic := '0';
variable TimingData_d_ena : VitalTimingDataType := VitalTimingDataInit;
variable q_VitalGlitchData : VitalGlitchDataType;
variable iq : std_logic := '0';
variable idata: std_logic := '0';
-- variables for 'X' generation
variable violation : std_logic := '0';
begin
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_d_ena,
TimingData => TimingData_d_ena,
TestSignal => d_ipd,
TestSignalName => "DATAIN",
RefSignal => ena_ipd,
RefSignalName => "ENA",
SetupHigh => tsetup_d_ena_noedge_negedge,
SetupLow => tsetup_d_ena_noedge_negedge,
HoldHigh => thold_d_ena_noedge_negedge,
HoldLow => thold_d_ena_noedge_negedge,
CheckEnabled => TRUE,
RefTransition => '\',
HeaderMsg => InstancePath & "/cycloneiii_latch",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
violation := Tviol_d_ena;
if ( (clr_ipd = '0')) then
iq := '0';
elsif (pre_ipd = '0') then
iq := '1';
elsif (violation = 'X' and x_on_violation = "on") then
iq := 'X';
elsif (ena_ipd = '1') then
iq := d_dly;
end if;
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => q,
OutSignalName => "Q",
OutTemp => iq,
Paths => (0 => (clr_ipd'last_event, tpd_clr_q_negedge, TRUE),
1 => (pre_ipd'last_event, tpd_pre_q_negedge, TRUE),
2 => (ena_ipd'last_event, tpd_ena_q_negedge, TRUE)),
GlitchData => q_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end vital_latch;
---------------------------------------------------------------------
--
-- Entity Name : cycloneiii_ddio_out
--
-- Description : Cyclone III DDIO_OUT VHDL simulation model
--
--
---------------------------------------------------------------------
LIBRARY IEEE;
LIBRARY altera;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use altera.all;
use work.cycloneiii_atom_pack.all;
ENTITY cycloneiii_ddio_out IS
generic(
tipd_datainlo : VitalDelayType01 := DefPropDelay01;
tipd_datainhi : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_clkhi : VitalDelayType01 := DefPropDelay01;
tipd_clklo : VitalDelayType01 := DefPropDelay01;
tipd_muxsel : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_areset : VitalDelayType01 := DefPropDelay01;
tipd_sreset : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
power_up : string := "low";
async_mode : string := "none";
sync_mode : string := "none";
use_new_clocking_model : string := "false";
lpm_type : string := "cycloneiii_ddio_out"
);
PORT (
datainlo : IN std_logic := '0';
datainhi : IN std_logic := '0';
clk : IN std_logic := '0';
clkhi : IN std_logic := '0';
clklo : IN std_logic := '0';
muxsel : IN std_logic := '0';
ena : IN std_logic := '1';
areset : IN std_logic := '0';
sreset : IN std_logic := '0';
dataout : OUT std_logic;
dfflo : OUT std_logic;
dffhi : OUT std_logic ;
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END cycloneiii_ddio_out;
ARCHITECTURE arch OF cycloneiii_ddio_out IS
component cycloneiii_mux21
generic(
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
InstancePath: STRING := "*";
tpd_A_MO : VitalDelayType01 := DefPropDelay01;
tpd_B_MO : VitalDelayType01 := DefPropDelay01;
tpd_S_MO : VitalDelayType01 := DefPropDelay01;
tipd_A : VitalDelayType01 := DefPropDelay01;
tipd_B : VitalDelayType01 := DefPropDelay01;
tipd_S : VitalDelayType01 := DefPropDelay01
);
port (
A : in std_logic := '0';
B : in std_logic := '0';
S : in std_logic := '0';
MO : out std_logic
);
end component;
component dffeas
generic (
power_up : string := "DONT_CARE";
is_wysiwyg : string := "false";
x_on_violation : string := "on";
lpm_type : string := "DFFEAS";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clrn_q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_prn_q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_aload_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_asdata_q: VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_asdata : VitalDelayType01 := DefPropDelay01;
tipd_sclr : VitalDelayType01 := DefPropDelay01;
tipd_sload : VitalDelayType01 := DefPropDelay01;
tipd_clrn : VitalDelayType01 := DefPropDelay01;
tipd_prn : VitalDelayType01 := DefPropDelay01;
tipd_aload : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*"
);
port (
d : in std_logic := '0';
clk : in std_logic := '0';
ena : in std_logic := '1';
clrn : in std_logic := '1';
prn : in std_logic := '1';
aload : in std_logic := '0';
asdata : in std_logic := '1';
sclr : in std_logic := '0';
sload : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
q : out std_logic
);
end component;
component cycloneiii_latch
generic(
is_wysiwyg : string := "false";
x_on_violation : string := "on";
lpm_type : string := "cycloneiii_latch";
tsetup_d_ena_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
thold_d_ena_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
tpd_d_q : VitalDelayType01 := DefPropDelay01;
tpd_ena_q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_clr_q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_pre_q_negedge : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_clr : VitalDelayType01 := DefPropDelay01;
tipd_pre : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*"
);
port(
d : in std_logic := '0';
ena : in std_logic := '1';
clr : in std_logic := '1';
pre : in std_logic := '1';
q : out std_logic
);
end component;
--Internal Signals
SIGNAL datainlo_ipd : std_logic := '0';
SIGNAL datainhi_ipd : std_logic := '0';
SIGNAL clk_ipd : std_logic := '0';
SIGNAL clkhi_ipd : std_logic := '0';
SIGNAL clklo_ipd : std_logic := '0';
SIGNAL muxsel_ipd : std_logic := '0';
SIGNAL ena_ipd : std_logic := '0';
SIGNAL areset_ipd : std_logic := '0';
SIGNAL sreset_ipd : std_logic := '0';
SIGNAL ddioreg_aclr : std_logic;
SIGNAL ddioreg_prn : std_logic;
SIGNAL ddioreg_adatasdata : std_logic;
SIGNAL ddioreg_sclr : std_logic;
SIGNAL ddioreg_sload : std_logic;
SIGNAL dfflo_tmp : std_logic;
SIGNAL dffhi_tmp : std_logic;
SIGNAL dataout_tmp : std_logic;
Signal mux_sel : std_logic;
Signal mux_hi : std_logic;
Signal sel_mux_hi_in : std_logic;
signal clk1 : std_logic;
signal clk_hi : std_logic;
signal clk_lo : std_logic;
signal muxsel1 : std_logic;
signal muxsel2: std_logic;
signal clk2 : std_logic;
signal muxsel_tmp: std_logic;
signal sel_mux_lo_in : std_logic;
signal datainlo_tmp : std_logic;
signal datainhi_tmp : std_logic;
signal dffhi_tmp1 : std_logic;
BEGIN
WireDelay : block
begin
VitalWireDelay (datainlo_ipd, datainlo, tipd_datainlo);
VitalWireDelay (datainhi_ipd, datainhi, tipd_datainhi);
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (clkhi_ipd, clkhi, tipd_clkhi);
VitalWireDelay (clklo_ipd, clklo, tipd_clklo);
VitalWireDelay (muxsel_ipd, muxsel, tipd_muxsel);
VitalWireDelay (ena_ipd, ena, tipd_ena);
VitalWireDelay (areset_ipd, areset, tipd_areset);
VitalWireDelay (sreset_ipd, sreset, tipd_sreset);
end block;
PROCESS
BEGIN
WAIT UNTIL areset_ipd'EVENT OR sreset_ipd'EVENT;
IF (async_mode = "clear") THEN
ddioreg_aclr <= NOT areset_ipd;
ddioreg_prn <= '1';
ELSIF (async_mode = "preset") THEN
ddioreg_aclr <= '1';
ddioreg_prn <= NOT areset_ipd;
ELSE
ddioreg_aclr <= '1';
ddioreg_prn <= '1';
END IF;
IF (sync_mode = "clear") THEN
ddioreg_adatasdata <= '0';
ddioreg_sclr <= sreset_ipd;
ddioreg_sload <= '0';
ELSIF (sync_mode = "preset") THEN
ddioreg_adatasdata <= '1';
ddioreg_sclr <= '0';
ddioreg_sload <= sreset_ipd;
ELSE
ddioreg_adatasdata <= '0';
ddioreg_sclr <= '0';
ddioreg_sload <= '0';
END IF;
END PROCESS;
process(clk_ipd)
begin
clk1 <= clk_ipd;
end process;
process(muxsel_ipd)
begin
muxsel1 <= muxsel_ipd;
end process;
process(dffhi_tmp)
begin
dffhi_tmp1 <= dffhi_tmp;
end process;
--DDIO HIGH Register
clk_hi <= ((NOT clkhi_ipd) and ena_ipd) when(use_new_clocking_model = "true") else ((NOT clk_ipd) and ena_ipd);
datainhi_tmp <= '1' when (ddioreg_sclr ='0'and ddioreg_sload = '1')else '0'when (ddioreg_sclr ='1'and ddioreg_sload = '0') else datainhi;
ddioreg_hi : cycloneiii_latch
PORT MAP (
d=> datainhi_tmp,
ena => clk_hi,
pre => ddioreg_prn,
clr => ddioreg_aclr,
q => dffhi_tmp
);
--DDIO Low Register
clk_lo <= clklo_ipd when(use_new_clocking_model = "true") else clk_ipd;
datainlo_tmp <= datainlo;
ddioreg_lo : dffeas
GENERIC MAP (
power_up => power_up
)
PORT MAP (
d => datainlo_tmp,
clk => clk_lo,
clrn => ddioreg_aclr,
prn => ddioreg_prn,
sclr => ddioreg_sclr,
sload => ddioreg_sload,
asdata => ddioreg_adatasdata,
ena => ena_ipd,
q => dfflo_tmp,
devpor => devpor,
devclrn => devclrn
);
muxsel2 <= muxsel1;
clk2 <= clk1;
mux_sel <= muxsel2 when(use_new_clocking_model = "true") else clk2;
muxsel_tmp <= NOT mux_sel;
sel_mux_lo_in <= dfflo_tmp;
sel_mux_hi_in <= dffhi_tmp1;
sel_mux : cycloneiii_mux21
port map (
A => sel_mux_hi_in,
B => sel_mux_lo_in,
S => muxsel_tmp,
MO => dataout
);
dfflo <= dfflo_tmp;
dffhi <= dffhi_tmp;
END arch;
----------------------------------------------------------------------------------
--Module Name: cycloneiii_pseudo_diff_out --
--Description: Simulation model for Cyclone III Pseudo Differential --
-- Output Buffer --
----------------------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.cycloneiii_atom_pack.all;
ENTITY cycloneiii_pseudo_diff_out IS
GENERIC (
tipd_i : VitalDelayType01 := DefPropDelay01;
tpd_i_o : VitalDelayType01 := DefPropDelay01;
tpd_i_obar : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
lpm_type : string := "cycloneiii_pseudo_diff_out"
);
PORT (
i : IN std_logic := '0';
o : OUT std_logic;
obar : OUT std_logic
);
END cycloneiii_pseudo_diff_out;
ARCHITECTURE arch OF cycloneiii_pseudo_diff_out IS
SIGNAL i_ipd : std_logic ;
SIGNAL o_tmp : std_logic ;
SIGNAL obar_tmp : std_logic;
BEGIN
WireDelay : block
begin
VitalWireDelay (i_ipd, i, tipd_i);
end block;
PROCESS( i_ipd)
BEGIN
IF (i_ipd = '0') THEN
o_tmp <= '0';
obar_tmp <= '1';
ELSE
IF (i_ipd = '1') THEN
o_tmp <= '1';
obar_tmp <= '0';
ELSE
o_tmp <= i_ipd;
obar_tmp <= i_ipd;
END IF;
END IF;
END PROCESS;
---------------------
-- Path Delay Section
----------------------
PROCESS( o_tmp,obar_tmp)
variable o_VitalGlitchData : VitalGlitchDataType;
variable obar_VitalGlitchData : VitalGlitchDataType;
BEGIN
VitalPathDelay01 (
OutSignal => o,
OutSignalName => "o",
OutTemp => o_tmp,
Paths => (0 => (i_ipd'last_event, tpd_i_o, TRUE)),
GlitchData => o_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn
);
VitalPathDelay01 (
OutSignal => obar,
OutSignalName => "obar",
OutTemp => obar_tmp,
Paths => (0 => (i_ipd'last_event, tpd_i_obar, TRUE)),
GlitchData => obar_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn
);
END PROCESS;
END arch;
----------------------------------------------------------------------------
-- Module Name : cycloneiii_io_pad
-- Description : Simulation model for cycloneiii IO pad
----------------------------------------------------------------------------
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
ENTITY cycloneiii_io_pad IS
GENERIC (
lpm_type : string := "cycloneiii_io_pad");
PORT (
--INPUT PORTS
padin : IN std_logic := '0'; -- Input Pad
--OUTPUT PORTS
padout : OUT std_logic); -- Output Pad
END cycloneiii_io_pad;
ARCHITECTURE arch OF cycloneiii_io_pad IS
BEGIN
padout <= padin;
END arch;
--/////////////////////////////////////////////////////////////////////////////
--
-- Entity Name : cycloneiii_ena_reg
--
-- Description : Simulation model for a simple DFF.
-- This is used for the gated clock generation
-- Powers upto 1.
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.cycloneiii_atom_pack.all;
ENTITY cycloneiii_ena_reg is
generic (
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01
);
PORT (
clk : in std_logic;
ena : in std_logic := '1';
d : in std_logic;
clrn : in std_logic := '1';
prn : in std_logic := '1';
q : out std_logic
);
attribute VITAL_LEVEL0 of cycloneiii_ena_reg : entity is TRUE;
end cycloneiii_ena_reg;
ARCHITECTURE behave of cycloneiii_ena_reg is
attribute VITAL_LEVEL0 of behave : architecture is TRUE;
signal d_ipd : std_logic;
signal clk_ipd : std_logic;
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (d_ipd, d, tipd_d);
VitalWireDelay (clk_ipd, clk, tipd_clk);
end block;
VITALtiming : process (clk_ipd, prn, clrn)
variable Tviol_d_clk : std_ulogic := '0';
variable TimingData_d_clk : VitalTimingDataType := VitalTimingDataInit;
variable q_VitalGlitchData : VitalGlitchDataType;
variable q_reg : std_logic := '1';
begin
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_d_clk,
TimingData => TimingData_d_clk,
TestSignal => d,
TestSignalName => "D",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_d_clk_noedge_posedge,
SetupLow => tsetup_d_clk_noedge_posedge,
HoldHigh => thold_d_clk_noedge_posedge,
HoldLow => thold_d_clk_noedge_posedge,
CheckEnabled => TO_X01((clrn) OR
(NOT ena)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/cycloneiii_ena_reg",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
end if;
if (prn = '0') then
q_reg := '1';
elsif (clrn = '0') then
q_reg := '0';
elsif (clk_ipd'event and clk_ipd = '1' and clk_ipd'last_value = '0' and (ena = '1')) then
q_reg := d_ipd;
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => q,
OutSignalName => "Q",
OutTemp => q_reg,
Paths => (0 => (clk_ipd'last_event, tpd_clk_q_posedge, TRUE)),
GlitchData => q_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end behave;
--/////////////////////////////////////////////////////////////////////////////
--
-- VHDL Simulation Model for Cyclone III CLKCTRL Atom
--
--/////////////////////////////////////////////////////////////////////////////
--
--
-- CYCLONEII_CLKCTRL Model
--
--
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.cycloneiii_atom_pack.all;
use work.cycloneiii_ena_reg;
entity cycloneiii_clkctrl is
generic (
clock_type : STRING := "Auto";
lpm_type : STRING := "cycloneiii_clkctrl";
ena_register_mode : STRING := "Falling Edge";
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tpd_inclk_outclk : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01);
tipd_inclk : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01);
tipd_clkselect : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01);
tipd_ena : VitalDelayType01 := DefPropDelay01
);
port (
inclk : in std_logic_vector(3 downto 0) := "0000";
clkselect : in std_logic_vector(1 downto 0) := "00";
ena : in std_logic := '1';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
outclk : out std_logic
);
attribute VITAL_LEVEL0 of cycloneiii_clkctrl : entity is TRUE;
end cycloneiii_clkctrl;
architecture vital_clkctrl of cycloneiii_clkctrl is
attribute VITAL_LEVEL0 of vital_clkctrl : architecture is TRUE;
component cycloneiii_ena_reg
generic (
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01
);
PORT (
clk : in std_logic;
ena : in std_logic := '1';
d : in std_logic;
clrn : in std_logic := '1';
prn : in std_logic := '1';
q : out std_logic
);
end component;
signal inclk_ipd : std_logic_vector(3 downto 0);
signal clkselect_ipd : std_logic_vector(1 downto 0);
signal ena_ipd : std_logic;
signal clkmux_out : std_logic;
signal clkmux_out_inv : std_logic;
signal cereg_clr : std_logic;
signal cereg1_out : std_logic;
signal cereg2_out : std_logic;
signal ena_out : std_logic;
signal outclk_tmp : std_logic;
signal vcc : std_logic := '1';
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (ena_ipd, ena, tipd_ena);
VitalWireDelay (inclk_ipd(0), inclk(0), tipd_inclk(0));
VitalWireDelay (inclk_ipd(1), inclk(1), tipd_inclk(1));
VitalWireDelay (inclk_ipd(2), inclk(2), tipd_inclk(2));
VitalWireDelay (inclk_ipd(3), inclk(3), tipd_inclk(3));
VitalWireDelay (clkselect_ipd(0), clkselect(0), tipd_clkselect(0));
VitalWireDelay (clkselect_ipd(1), clkselect(1), tipd_clkselect(1));
end block;
process(inclk_ipd, clkselect_ipd)
variable tmp : std_logic;
begin
if (clkselect_ipd = "11") then
tmp := inclk_ipd(3);
elsif (clkselect_ipd = "10") then
tmp := inclk_ipd(2);
elsif (clkselect_ipd = "01") then
tmp := inclk_ipd(1);
else
tmp := inclk_ipd(0);
end if;
clkmux_out <= tmp;
clkmux_out_inv <= NOT tmp;
end process;
extena0_reg : cycloneiii_ena_reg
port map (
clk => clkmux_out_inv,
ena => vcc,
d => ena_ipd,
clrn => vcc,
prn => devpor,
q => cereg1_out
);
extena1_reg : cycloneiii_ena_reg
port map (
clk => clkmux_out_inv,
ena => vcc,
d => cereg1_out,
clrn => vcc,
prn => devpor,
q => cereg2_out
);
ena_out <= cereg1_out WHEN (ena_register_mode = "falling edge") ELSE
ena_ipd WHEN (ena_register_mode = "none") ELSE cereg2_out;
outclk_tmp <= ena_out AND clkmux_out;
-- output path
process (inclk_ipd,outclk_tmp)
variable outclk_VitalGlitchData : VitalGlitchDataType;
begin
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01
(
OutSignal => outclk,
OutSignalName => "OUTCLK",
OutTemp => outclk_tmp,
Paths => (0 => (inclk_ipd(0)'last_event, tpd_inclk_outclk(0), TRUE),
1 => (inclk_ipd(1)'last_event, tpd_inclk_outclk(1), TRUE),
2 => (inclk_ipd(2)'last_event, tpd_inclk_outclk(2), TRUE),
3 => (inclk_ipd(3)'last_event, tpd_inclk_outclk(3), TRUE)),
GlitchData => outclk_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn
);
end process;
end vital_clkctrl;
--
--
-- CYCLONEIII_RUBLOCK Model
--
--
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use work.cycloneiii_atom_pack.all;
entity cycloneiii_rublock is
generic
(
sim_init_config : string := "factory";
sim_init_watchdog_value : integer := 0;
sim_init_status : integer := 0;
lpm_type : string := "cycloneiii_rublock"
);
port
(
clk : in std_logic;
shiftnld : in std_logic;
captnupdt : in std_logic;
regin : in std_logic;
rsttimer : in std_logic;
rconfig : in std_logic;
regout : out std_logic
);
end cycloneiii_rublock;
architecture architecture_rublock of cycloneiii_rublock is
begin
end architecture_rublock;
--
--
-- CYCLONEIII_APFCONTROLLER Model
--
--
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use work.cycloneiii_atom_pack.all;
entity cycloneiii_apfcontroller is
generic
(
lpm_type: string := "cycloneiii_apfcontroller"
);
port
(
usermode : out std_logic;
nceout : out std_logic
);
end cycloneiii_apfcontroller;
architecture architecture_apfcontroller of cycloneiii_apfcontroller is
begin
end architecture_apfcontroller;
--------------------------------------------------------------------
--
-- Module Name : cycloneiii_termination
--
-- Description : Cyclone III Termination Atom VHDL simulation model
--
--------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
ENTITY cycloneiii_termination IS
GENERIC (
pullup_control_to_core: string := "false";
power_down : string := "true";
test_mode : string := "false";
left_shift_termination_code : string := "false";
pullup_adder : integer := 0;
pulldown_adder : integer := 0;
clock_divide_by : integer := 32; -- 1, 4, 32
runtime_control : string := "false";
shift_vref_rup : string := "true";
shift_vref_rdn : string := "true";
shifted_vref_control : string := "true";
lpm_type : string := "cycloneiii_termination");
PORT (
rup : IN std_logic := '0';
rdn : IN std_logic := '0';
terminationclock : IN std_logic := '0';
terminationclear : IN std_logic := '0';
devpor : IN std_logic := '1';
devclrn : IN std_logic := '1';
comparatorprobe : OUT std_logic;
terminationcontrolprobe : OUT std_logic;
calibrationdone : OUT std_logic;
terminationcontrol : OUT std_logic_vector(15 DOWNTO 0));
END cycloneiii_termination;
ARCHITECTURE cycloneiii_termination_arch OF cycloneiii_termination IS
SIGNAL rup_compout : std_logic := '0';
SIGNAL rdn_compout : std_logic := '1';
BEGIN
calibrationdone <= '1'; -- power-up calibration status
comparatorprobe <= rup_compout WHEN (pullup_control_to_core = "true") ELSE rdn_compout;
rup_compout <= rup;
rdn_compout <= not rdn;
END cycloneiii_termination_arch;
-------------------------------------------------------------------
--
-- Entity Name : cycloneiii_jtag
--
-- Description : Cyclone III JTAG VHDL Simulation model
--
-------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use work.cycloneiii_atom_pack.all;
entity cycloneiii_jtag is
generic (
lpm_type : string := "cycloneiii_jtag"
);
port (
tms : in std_logic := '0';
tck : in std_logic := '0';
tdi : in std_logic := '0';
tdoutap : in std_logic := '0';
tdouser : in std_logic := '0';
tdo: out std_logic;
tmsutap: out std_logic;
tckutap: out std_logic;
tdiutap: out std_logic;
shiftuser: out std_logic;
clkdruser: out std_logic;
updateuser: out std_logic;
runidleuser: out std_logic;
usr1user: out std_logic
);
end cycloneiii_jtag;
architecture architecture_jtag of cycloneiii_jtag is
begin
end architecture_jtag;
-------------------------------------------------------------------
--
-- Entity Name : cycloneiii_crcblock
--
-- Description : Cyclone III CRCBLOCK VHDL Simulation model
--
-------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use work.cycloneiii_atom_pack.all;
entity cycloneiii_crcblock is
generic (
oscillator_divider : integer := 1;
lpm_type : string := "cycloneiii_crcblock"
);
port (
clk : in std_logic := '0';
shiftnld : in std_logic := '0';
ldsrc : in std_logic := '0';
crcerror : out std_logic;
regout : out std_logic
);
end cycloneiii_crcblock;
architecture architecture_crcblock of cycloneiii_crcblock is
begin
crcerror <= '0';
regout <= '0';
end architecture_crcblock;
--
--
-- CYCLONEIII_OSCILLATOR Model
--
--
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.cycloneiii_atom_pack.all;
entity cycloneiii_oscillator is
generic
(
lpm_type: string := "cycloneiii_oscillator";
TimingChecksOn: Boolean := True;
XOn: Boolean := DefGlitchXOn;
MsgOn: Boolean := DefGlitchMsgOn;
tpd_oscena_clkout_posedge : VitalDelayType01 := DefPropDelay01;
tipd_oscena : VitalDelayType01 := DefPropDelay01
);
port
(
oscena : in std_logic;
clkout : out std_logic
);
end cycloneiii_oscillator;
architecture architecture_oscillator of cycloneiii_oscillator is
signal oscena_ipd : std_logic;
signal int_osc : std_logic := '0';
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (oscena_ipd, oscena, tipd_oscena);
end block;
VITAL_osc : process(oscena_ipd, int_osc)
variable OSC_PW : time := 6250 ps; -- pulse width for 80MHz clock
variable osc_VitalGlitchData : VitalGlitchDataType;
begin
if (oscena_ipd = '1') then
if ((int_osc = '0') or (int_osc = '1')) then
int_osc <= not int_osc after OSC_PW;
else
int_osc <= '0' after OSC_PW;
end if;
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => clkout,
OutSignalName => "osc",
OutTemp => int_osc,
Paths => (0 => (InputChangeTime => oscena_ipd'last_event,
PathDelay => tpd_oscena_clkout_posedge,
PathCondition => (oscena_ipd = '1'))),
GlitchData => osc_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end architecture_oscillator;
| gpl-3.0 |
michaelfivez/ascon_hardware_implementation | ascon12864_serialized/Kernel/Ascon_block_datapath.vhd | 1 | 7915 | -------------------------------------------------------------------------------
--! @project Serialized hardware implementation of Asconv1286
--! @author Michael Fivez
--! @license This project is released under the GNU Public License.
--! The license and distribution terms for this file may be
--! found in the file LICENSE in this distribution or at
--! http://www.gnu.org/licenses/gpl-3.0.txt
--! @note This is an hardware implementation made for my graduation thesis
--! at the KULeuven, in the COSIC department (year 2015-2016)
--! The thesis is titled 'Energy efficient hardware implementations of CAESAR submissions',
--! and can be found on the COSIC website (www.esat.kuleuven.be/cosic/publications)
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity Ascon_StateUpdate_datapath is
port(
Clk : in std_logic; -- Clock
Reset : in std_logic; -- Reset (synchronous)
-- Control signals
RoundNr : in std_logic_vector(3 downto 0); -- biggest round is 12
sel1,sel2,sel3,sel4 : in std_logic_vector(1 downto 0);
sel0 : in std_logic_vector(2 downto 0);
selout : in std_logic;
SelSbox : in std_logic_vector(1 downto 0);
SelDiff : in std_logic_vector(2 downto 0);
Reg0En,Reg1En,Reg2En,Reg3En,Reg4En,RegOutEn : in std_logic;
SboxEnable : in std_logic;
ActivateGen : in std_logic;
GenSize : in std_logic_vector(2 downto 0);
-- Data signals
IV : in std_logic_vector(127 downto 0);
Key : in std_logic_vector(127 downto 0);
DataIn : in std_logic_vector(63 downto 0);
DataOut : out std_logic_vector(127 downto 0)
);
end entity Ascon_StateUpdate_datapath;
architecture structural of Ascon_StateUpdate_datapath is
-- constants
constant EXTRAIV : std_logic_vector(63 downto 0) := x"80400c0600000000"; -- used in the initialization
constant SEPCONSTANT : std_logic_vector(63 downto 0) := x"0000000000000001";
constant ADCONSTANT : std_logic_vector(63 downto 0) := x"8000000000000000";
-- Register signals
signal SboxReg0In,SboxReg1In,SboxReg2In,SboxReg3In,SboxReg4In : std_logic_vector(63 downto 0);
signal SboxReg0Out,SboxReg1Out,SboxReg2Out,SboxReg3Out,SboxReg4Out : std_logic_vector(63 downto 0);
signal RegOutIn,RegOutOut : std_logic_vector(127 downto 0);
-- Internal signals on datapath
signal Sbox0In,Sbox1In,Sbox2In,Sbox3In,Sbox4In : std_logic_vector(15 downto 0);
signal Sbox0Out,Sbox1Out,Sbox2Out,Sbox3Out,Sbox4Out : std_logic_vector(15 downto 0);
signal Diff1In, Diff2In, Diff3In, DiffOut : std_logic_vector(63 downto 0);
signal XorReg01,XorReg02,XorReg12,XorReg13,XorReg22 : std_logic_vector(63 downto 0);
signal XorReg31,XorReg4 : std_logic_vector(63 downto 0);
signal OutSig0 : std_logic_vector(63 downto 0);
signal OutSig1 : std_logic_vector(127 downto 0);
begin
-- declare and connect all sub entities
sboxregisters: entity work.Sbox_registers port map(Clk ,Sbox0Out, Sbox1Out, Sbox2Out, Sbox3Out, Sbox4Out, Sbox0In, Sbox1In, Sbox2In, Sbox3In, Sbox4In,
SboxReg0In, SboxReg1In, SboxReg2In, SboxReg3In, SboxReg4In, SboxReg0Out, SboxReg1Out, SboxReg2Out, SboxReg3Out, SboxReg4Out,
SelSbox, SboxEnable, Reg0En, Reg1En, Reg2En, Reg3En, Reg4En);
sbox: entity work.Sbox port map(Sbox0In,Sbox1In,Sbox2In,Sbox3In,Sbox4In,RoundNr,Sbox0Out,Sbox1Out,Sbox2Out,Sbox3Out,Sbox4Out,SelSbox);
difflayer: entity work.FullDiffusionLayer port map(Diff1In,Diff2In,Diff3In,DiffOut);
outpgen: entity work.OutputGenerator port map(SboxReg0Out,DataIn,GenSize,ActivateGen,XorReg01,OutSig0); -- ActivateGen is a bit that indicates decryption or not
---------------------------------------------
------ Combinatorial logic for a round ------
---------------------------------------------
datapath: process(Diff1In, Diff2In, Diff3In, DiffOut, SboxReg0In, SboxReg1In, SboxReg2In, SboxReg3In, SboxReg4In,
XorReg01,XorReg02,XorReg12,XorReg13,XorReg22,XorReg31,XorReg4,OutSig0, OutSig1,
SboxReg0Out, SboxReg1Out, SboxReg2Out, SboxReg3Out, SboxReg4Out, Key, IV, RegOutIn, RegOutOut, sel0, sel1, sel2, sel3, sel4,
selout) is
begin
-- Set correct inputs in registers
if sel0 = "000" then
SboxReg0In <= DiffOut;
elsif sel0 = "001" then
SboxReg0In <= EXTRAIV;
elsif sel0 = "010" then
SboxReg0In <= XorReg01;
elsif sel0 = "011" then
SboxReg0In <= XorReg02;
else
SboxReg0In <= SboxReg0Out xor ADCONSTANT;
end if;
if sel1 = "00" then
SboxReg1In <= DiffOut;
elsif sel1 = "01" then
SboxReg1In <= Key(127 downto 64);
elsif sel1 = "10" then
SboxReg1In <= XorReg13;
else
SboxReg1In <= XorReg12;
end if;
if sel2 = "00" then
SboxReg2In <= DiffOut;
elsif sel2 = "01" then
SboxReg2In <= Key(63 downto 0);
else
SboxReg2In <= XorReg22;
end if;
if sel3 = "00" then
SboxReg3In <= DiffOut;
elsif sel3 = "01" then
SboxReg3In <= IV(127 downto 64);
else
SboxReg3In <= XorReg31;
end if;
if sel4 = "00" then
SboxReg4In <= DiffOut;
elsif sel4 = "01" then
SboxReg4In <= IV(63 downto 0);
elsif sel4 = "10" then
SboxReg4In <= XorReg4;
else
SboxReg4In <= SboxReg4Out xor SEPCONSTANT;
end if;
XorReg02 <= SboxReg0Out xor Key(127 downto 64);
XorReg12 <= SboxReg1Out xor Key(63 downto 0);
XorReg13 <= SboxReg1Out xor Key(127 downto 64);
XorReg22 <= SboxReg2Out xor Key(63 downto 0);
XorReg31 <= SboxReg3Out xor Key(127 downto 64);
XorReg4 <= SboxReg4Out xor Key(63 downto 0);
-- Set output
OutSig1(127 downto 64) <= XorReg31;
OutSig1(63 downto 0) <= XorReg4;
if selout = '0' then
RegOutIn(127 downto 64) <= (others => '0');
RegOutIn(63 downto 0) <= OutSig0;
else
RegOutIn <= OutSig1;
end if;
DataOut <= RegOutOut;
if SelDiff = "000" then
Diff1In(63 downto 64 - 19) <= SboxReg0Out(19 - 1 downto 0);
Diff1In(63 - 19 downto 0) <= SboxReg0Out(63 downto 19);
Diff2In(63 downto 64 - 28) <= SboxReg0Out(28 - 1 downto 0);
Diff2In(63 - 28 downto 0) <= SboxReg0Out(63 downto 28);
Diff3In <= SboxReg0Out;
elsif SelDiff = "001" then
Diff1In(63 downto 64 - 61) <= SboxReg1Out(61 - 1 downto 0);
Diff1In(63 - 61 downto 0) <= SboxReg1Out(63 downto 61);
Diff2In(63 downto 64 - 39) <= SboxReg1Out(39 - 1 downto 0);
Diff2In(63 - 39 downto 0) <= SboxReg1Out(63 downto 39);
Diff3In <= SboxReg1Out;
elsif SelDiff = "010" then
Diff1In(63 downto 64 - 1) <= SboxReg2Out(1 - 1 downto 0);
Diff1In(63 - 1 downto 0) <= SboxReg2Out(63 downto 1);
Diff2In(63 downto 64 - 6) <= SboxReg2Out(6 - 1 downto 0);
Diff2In(63 - 6 downto 0) <= SboxReg2Out(63 downto 6);
Diff3In <= SboxReg2Out;
elsif SelDiff = "011" then
Diff1In(63 downto 64 - 10) <= SboxReg3Out(10 - 1 downto 0);
Diff1In(63 - 10 downto 0) <= SboxReg3Out(63 downto 10);
Diff2In(63 downto 64 - 17) <= SboxReg3Out(17 - 1 downto 0);
Diff2In(63 - 17 downto 0) <= SboxReg3Out(63 downto 17);
Diff3In <= SboxReg3Out;
else
Diff1In(63 downto 64 - 7) <= SboxReg4Out(7 - 1 downto 0);
Diff1In(63 - 7 downto 0) <= SboxReg4Out(63 downto 7);
Diff2In(63 downto 64 - 41) <= SboxReg4Out(41 - 1 downto 0);
Diff2In(63 - 41 downto 0) <= SboxReg4Out(63 downto 41);
Diff3In <= SboxReg4Out;
end if;
end process datapath;
---------------------------------------------
------ The registers in the datapath --------
---------------------------------------------
registerdatapath : process(Clk,Reset) is
begin
if(Clk = '1' and Clk'event) then
if Reset = '1' then -- synchronous reset
RegOutOut <= (others => '0');
else
if RegOutEn = '1' then
RegOutOut <= RegOutIn;
end if;
end if;
end if;
end process registerdatapath;
end architecture structural;
| gpl-3.0 |
michaelfivez/ascon_hardware_implementation | ascon128128_iterated/API_plus_CipherCore/AEAD.vhd | 9 | 5350 | -------------------------------------------------------------------------------
--! @file AEAD.vhd
--! @brief Top-level of authenticated encryption unit containing logic and memory region.
--! @project CAESAR Candidate Evaluation
--! @author Ekawat (ice) Homsirikamol
--! @copyright Copyright (c) 2015 Cryptographic Engineering Research Group
--! ECE Department, George Mason University Fairfax, VA, U.S.A.
--! All rights Reserved.
--! @license This project is released under the GNU Public License.
--! The license and distribution terms for this file may be
--! found in the file LICENSE in this distribution or at
--! http://www.gnu.org/licenses/gpl-3.0.txt
--! @note This is publicly available encryption source code that falls
--! under the License Exception TSU (Technology and software-
--! —unrestricted)
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.AEAD_pkg.all;
entity AEAD is
generic (
G_PWIDTH : integer := 32;
G_SWIDTH : integer := 32;
G_AUX_FIFO_CAPACITY : integer := 131072
);
port (
--! Global signals
clk : in std_logic;
rst : in std_logic;
--! Data in signals
pdi : in std_logic_vector(G_PWIDTH -1 downto 0);
pdi_valid : in std_logic;
pdi_ready : out std_logic;
--! Key signals
sdi : in std_logic_vector(G_SWIDTH -1 downto 0);
sdi_valid : in std_logic;
sdi_ready : out std_logic;
--! Data out signals
do : out std_logic_vector(G_PWIDTH -1 downto 0);
do_ready : in std_logic;
do_valid : out std_logic
);
end AEAD;
-------------------------------------------------------------------------------
--! @brief Architecture definition of crypto_template
-------------------------------------------------------------------------------
architecture structure of AEAD is
constant AUX_FIFO_DEPTH : integer := G_AUX_FIFO_CAPACITY/G_PWIDTH;
signal bypass_fifo_rd : std_logic;
signal bypass_fifo_wr : std_logic;
signal bypass_fifo_data : std_logic_vector(G_PWIDTH-1 downto 0);
signal bypass_fifo_full : std_logic;
signal bypass_fifo_empty : std_logic;
signal aux_fifo_din : std_logic_vector(G_PWIDTH-1 downto 0);
signal aux_fifo_dout : std_logic_vector(G_PWIDTH-1 downto 0);
signal aux_fifo_ctrl : std_logic_vector(3 downto 0);
signal aux_fifo_status : std_logic_vector(2 downto 0);
begin
u_logic:
entity work.AEAD_Core(structure)
generic map (
G_W => G_PWIDTH ,
G_SW => G_SWIDTH
)
port map (
clk => clk ,
rst => rst ,
pdi => pdi ,
pdi_valid => pdi_valid,
pdi_ready => pdi_ready,
sdi => sdi ,
sdi_valid => sdi_valid,
sdi_ready => sdi_ready,
do => do ,
do_ready => do_ready ,
do_valid => do_valid ,
--! FIFO signals
bypass_fifo_wr => bypass_fifo_wr,
bypass_fifo_rd => bypass_fifo_rd,
bypass_fifo_data => bypass_fifo_data,
bypass_fifo_full => bypass_fifo_full,
bypass_fifo_empty => bypass_fifo_empty,
aux_fifo_din => aux_fifo_din,
aux_fifo_dout => aux_fifo_dout,
aux_fifo_ctrl => aux_fifo_ctrl,
aux_fifo_status => aux_fifo_status
);
u_memory: block
begin
u_bypass_fifo:
entity work.fifo(structure)
generic map (G_W => G_PWIDTH, G_LOG2DEPTH => 6)
port map (
clk => clk ,
rst => rst ,
write => bypass_fifo_wr ,
read => bypass_fifo_rd ,
din => pdi ,
dout => bypass_fifo_data ,
almost_full => bypass_fifo_full ,
empty => bypass_fifo_empty
);
u_aux_fifo:
entity work.aux_fifo(structure)
generic map (G_W => G_PWIDTH, G_LOG2DEPTH => log2_ceil(AUX_FIFO_DEPTH))
port map (
clk => clk ,
rst => rst ,
fifo_din => aux_fifo_din ,
fifo_dout => aux_fifo_dout ,
fifo_ctrl_in => aux_fifo_ctrl ,
fifo_ctrl_out => aux_fifo_status
);
end block u_memory;
end structure; | gpl-3.0 |
michaelfivez/ascon_hardware_implementation | ascon128128_serialized/Kernel/Sbox.vhd | 1 | 4044 | -------------------------------------------------------------------------------
--! @project Serialized hardware implementation of Asconv128128
--! @author Michael Fivez
--! @license This project is released under the GNU Public License.
--! The license and distribution terms for this file may be
--! found in the file LICENSE in this distribution or at
--! http://www.gnu.org/licenses/gpl-3.0.txt
--! @note This is an hardware implementation made for my graduation thesis
--! at the KULeuven, in the COSIC department (year 2015-2016)
--! The thesis is titled 'Energy efficient hardware implementations of CAESAR submissions',
--! and can be found on the COSIC website (www.esat.kuleuven.be/cosic/publications)
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity Sbox is
port(
X0In : in std_logic_vector(15 downto 0);
X1In : in std_logic_vector(15 downto 0);
X2In : in std_logic_vector(15 downto 0);
X3In : in std_logic_vector(15 downto 0);
X4In : in std_logic_vector(15 downto 0);
RoundNr : in std_logic_vector(3 downto 0);
X0Out : out std_logic_vector(15 downto 0);
X1Out : out std_logic_vector(15 downto 0);
X2Out : out std_logic_vector(15 downto 0);
X3Out : out std_logic_vector(15 downto 0);
X4Out : out std_logic_vector(15 downto 0);
Sel : in std_logic_vector(1 downto 0));
end entity Sbox;
architecture structural of Sbox is
begin
Sbox: process(X0In,X1In,X2In,X3In,X4In,RoundNr,Sel) is
-- Procedure for 5-bit Sbox
procedure doSboxPart (
variable SboxPartIn : in std_logic_vector(4 downto 0);
variable SboxPartOut : out std_logic_vector(4 downto 0)) is
-- Temp variable
variable SboxPartTemp : std_logic_vector(17 downto 0);
begin
-- Sbox Interconnections
SboxPartTemp(0) := SboxPartIn(0) xor SboxPartIn(4);
SboxPartTemp(1) := SboxPartIn(2) xor SboxPartIn(1);
SboxPartTemp(2) := SboxPartIn(4) xor SboxPartIn(3);
SboxPartTemp(3) := not SboxPartTemp(0);
SboxPartTemp(4) := not SboxPartIn(1);
SboxPartTemp(5) := not SboxPartTemp(1);
SboxPartTemp(6) := not SboxPartIn(3);
SboxPartTemp(7) := not SboxPartTemp(2);
SboxPartTemp(8) := SboxPartIn(1) and SboxPartTemp(3);
SboxPartTemp(9) := SboxPartTemp(1) and SboxPartTemp(4);
SboxPartTemp(10) := SboxPartIn(3) and SboxPartTemp(5);
SboxPartTemp(11) := SboxPartTemp(2) and SboxPartTemp(6);
SboxPartTemp(12) := SboxPartTemp(0) and SboxPartTemp(7);
SboxPartTemp(13) := SboxPartTemp(0) xor SboxPartTemp(9);
SboxPartTemp(14) := SboxPartIn(1) xor SboxPartTemp(10);
SboxPartTemp(15) := SboxPartTemp(1) xor SboxPartTemp(11);
SboxPartTemp(16) := SboxPartIn(3) xor SboxPartTemp(12);
SboxPartTemp(17) := SboxPartTemp(2) xor SboxPartTemp(8);
SboxPartOut(0) := SboxPartTemp(13) xor SboxPartTemp(17);
SboxPartOut(1) := SboxPartTemp(13) xor SboxPartTemp(14);
SboxPartOut(2) := not SboxPartTemp(15);
SboxPartOut(3) := SboxPartTemp(15) xor SboxPartTemp(16);
SboxPartOut(4) := SboxPartTemp(17);
end procedure doSboxPart;
variable X2TempIn : std_logic_vector(15 downto 0);
variable TempIn,TempOut : std_logic_vector(4 downto 0);
begin
-- Xor with round constants
if Sel = "11" then
X2TempIn(3 downto 0) := X2In(3 downto 0) xor RoundNr;
X2TempIn(7 downto 4) := X2In(7 downto 4) xnor RoundNr;
X2TempIn(15 downto 8) := X2In(15 downto 8);
else
X2TempIn := X2In;
end if;
-- Apply 5-bit Sbox 64 times
for i in X0In'range loop
TempIn(0) := X0In(i);
TempIn(1) := X1In(i);
TempIn(2) := X2TempIn(i);
TempIn(3) := X3In(i);
TempIn(4) := X4In(i);
doSboxPart(TempIn,TempOut);
X0Out(i) <= TempOut(0);
X1Out(i) <= TempOut(1);
X2Out(i) <= TempOut(2);
X3Out(i) <= TempOut(3);
X4Out(i) <= TempOut(4);
end loop;
end process Sbox;
end architecture structural;
| gpl-3.0 |
michaelfivez/ascon_hardware_implementation | ascon12864_serialized/API_plus_CipherCore/std_logic_1164_additions.vhd | 9 | 70122 | ------------------------------------------------------------------------------
-- "std_logic_1164_additions" package contains the additions to the standard
-- "std_logic_1164" package proposed by the VHDL-200X-ft working group.
-- This package should be compiled into "ieee_proposed" and used as follows:
-- use ieee.std_logic_1164.all;
-- use ieee_proposed.std_logic_1164_additions.all;
-- Last Modified: $Date: 2007-05-31 14:53:37-04 $
-- RCS ID: $Id: std_logic_1164_additions.vhdl,v 1.10 2007-05-31 14:53:37-04 l435385 Exp $
--
-- Created for VHDL-200X par, David Bishop ([email protected])
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
package std_logic_1164_additions is
-- NOTE that in the new std_logic_1164, STD_LOGIC_VECTOR is a resolved
-- subtype of STD_ULOGIC_VECTOR. Thus there is no need for funcitons which
-- take inputs in STD_LOGIC_VECTOR.
-- For compatability with VHDL-2002, I have replicated all of these funcitons
-- here for STD_LOGIC_VECTOR.
-- new aliases
alias to_bv is ieee.std_logic_1164.To_bitvector [STD_LOGIC_VECTOR, BIT return BIT_VECTOR];
alias to_bv is ieee.std_logic_1164.To_bitvector [STD_ULOGIC_VECTOR, BIT return BIT_VECTOR];
alias to_bit_vector is ieee.std_logic_1164.To_bitvector [STD_LOGIC_VECTOR, BIT return BIT_VECTOR];
alias to_bit_vector is ieee.std_logic_1164.To_bitvector [STD_ULOGIC_VECTOR, BIT return BIT_VECTOR];
alias to_slv is ieee.std_logic_1164.To_StdLogicVector [BIT_VECTOR return STD_LOGIC_VECTOR];
alias to_slv is ieee.std_logic_1164.To_StdLogicVector [STD_ULOGIC_VECTOR return STD_LOGIC_VECTOR];
alias to_std_logic_vector is ieee.std_logic_1164.To_StdLogicVector [BIT_VECTOR return STD_LOGIC_VECTOR];
alias to_std_logic_vector is ieee.std_logic_1164.To_StdLogicVector [STD_ULOGIC_VECTOR return STD_LOGIC_VECTOR];
alias to_suv is ieee.std_logic_1164.To_StdULogicVector [BIT_VECTOR return STD_ULOGIC_VECTOR];
alias to_suv is ieee.std_logic_1164.To_StdULogicVector [STD_LOGIC_VECTOR return STD_ULOGIC_VECTOR];
alias to_std_ulogic_vector is ieee.std_logic_1164.To_StdULogicVector [BIT_VECTOR return STD_ULOGIC_VECTOR];
alias to_std_ulogic_vector is ieee.std_logic_1164.To_StdULogicVector [STD_LOGIC_VECTOR return STD_ULOGIC_VECTOR];
-------------------------------------------------------------------
-- overloaded shift operators
-------------------------------------------------------------------
function "sll" (l : STD_LOGIC_VECTOR; r : INTEGER) return STD_LOGIC_VECTOR;
function "sll" (l : STD_ULOGIC_VECTOR; r : INTEGER) return STD_ULOGIC_VECTOR;
function "srl" (l : STD_LOGIC_VECTOR; r : INTEGER) return STD_LOGIC_VECTOR;
function "srl" (l : STD_ULOGIC_VECTOR; r : INTEGER) return STD_ULOGIC_VECTOR;
function "rol" (l : STD_LOGIC_VECTOR; r : INTEGER) return STD_LOGIC_VECTOR;
function "rol" (l : STD_ULOGIC_VECTOR; r : INTEGER) return STD_ULOGIC_VECTOR;
function "ror" (l : STD_LOGIC_VECTOR; r : INTEGER) return STD_LOGIC_VECTOR;
function "ror" (l : STD_ULOGIC_VECTOR; r : INTEGER) return STD_ULOGIC_VECTOR;
-------------------------------------------------------------------
-- vector/scalar overloaded logical operators
-------------------------------------------------------------------
function "and" (l : STD_LOGIC_VECTOR; r : STD_ULOGIC) return STD_LOGIC_VECTOR;
function "and" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) return STD_ULOGIC_VECTOR;
function "and" (l : STD_ULOGIC; r : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "and" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
function "nand" (l : STD_LOGIC_VECTOR; r : STD_ULOGIC) return STD_LOGIC_VECTOR;
function "nand" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) return STD_ULOGIC_VECTOR;
function "nand" (l : STD_ULOGIC; r : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "nand" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
function "or" (l : STD_LOGIC_VECTOR; r : STD_ULOGIC) return STD_LOGIC_VECTOR;
function "or" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) return STD_ULOGIC_VECTOR;
function "or" (l : STD_ULOGIC; r : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "or" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
function "nor" (l : STD_LOGIC_VECTOR; r : STD_ULOGIC) return STD_LOGIC_VECTOR;
function "nor" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) return STD_ULOGIC_VECTOR;
function "nor" (l : STD_ULOGIC; r : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "nor" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
function "xor" (l : STD_LOGIC_VECTOR; r : STD_ULOGIC) return STD_LOGIC_VECTOR;
function "xor" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) return STD_ULOGIC_VECTOR;
function "xor" (l : STD_ULOGIC; r : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "xor" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
function "xnor" (l : STD_LOGIC_VECTOR; r : STD_ULOGIC) return STD_LOGIC_VECTOR;
function "xnor" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) return STD_ULOGIC_VECTOR;
function "xnor" (l : STD_ULOGIC; r : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "xnor" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
-------------------------------------------------------------------
-- vector-reduction functions.
-- "and" functions default to "1", or defaults to "0"
-------------------------------------------------------------------
-----------------------------------------------------------------------------
-- %%% Replace the "_reduce" functions with the ones commented out below.
-----------------------------------------------------------------------------
-- function "and" ( l : std_logic_vector ) RETURN std_ulogic;
-- function "and" ( l : std_ulogic_vector ) RETURN std_ulogic;
-- function "nand" ( l : std_logic_vector ) RETURN std_ulogic;
-- function "nand" ( l : std_ulogic_vector ) RETURN std_ulogic;
-- function "or" ( l : std_logic_vector ) RETURN std_ulogic;
-- function "or" ( l : std_ulogic_vector ) RETURN std_ulogic;
-- function "nor" ( l : std_logic_vector ) RETURN std_ulogic;
-- function "nor" ( l : std_ulogic_vector ) RETURN std_ulogic;
-- function "xor" ( l : std_logic_vector ) RETURN std_ulogic;
-- function "xor" ( l : std_ulogic_vector ) RETURN std_ulogic;
-- function "xnor" ( l : std_logic_vector ) RETURN std_ulogic;
-- function "xnor" ( l : std_ulogic_vector ) RETURN std_ulogic;
function and_reduce (l : STD_LOGIC_VECTOR) return STD_ULOGIC;
function and_reduce (l : STD_ULOGIC_VECTOR) return STD_ULOGIC;
function nand_reduce (l : STD_LOGIC_VECTOR) return STD_ULOGIC;
function nand_reduce (l : STD_ULOGIC_VECTOR) return STD_ULOGIC;
function or_reduce (l : STD_LOGIC_VECTOR) return STD_ULOGIC;
function or_reduce (l : STD_ULOGIC_VECTOR) return STD_ULOGIC;
function nor_reduce (l : STD_LOGIC_VECTOR) return STD_ULOGIC;
function nor_reduce (l : STD_ULOGIC_VECTOR) return STD_ULOGIC;
function xor_reduce (l : STD_LOGIC_VECTOR) return STD_ULOGIC;
function xor_reduce (l : STD_ULOGIC_VECTOR) return STD_ULOGIC;
function xnor_reduce (l : STD_LOGIC_VECTOR) return STD_ULOGIC;
function xnor_reduce (l : STD_ULOGIC_VECTOR) return STD_ULOGIC;
-------------------------------------------------------------------
-- ?= operators, same functionality as 1076.3 1994 std_match
-------------------------------------------------------------------
-- FUNCTION "?=" ( l, r : std_ulogic ) RETURN std_ulogic;
-- FUNCTION "?=" ( l, r : std_logic_vector ) RETURN std_ulogic;
-- FUNCTION "?=" ( l, r : std_ulogic_vector ) RETURN std_ulogic;
-- FUNCTION "?/=" ( l, r : std_ulogic ) RETURN std_ulogic;
-- FUNCTION "?/=" ( l, r : std_logic_vector ) RETURN std_ulogic;
-- FUNCTION "?/=" ( l, r : std_ulogic_vector ) RETURN std_ulogic;
-- FUNCTION "?>" ( l, r : std_ulogic ) RETURN std_ulogic;
-- FUNCTION "?>=" ( l, r : std_ulogic ) RETURN std_ulogic;
-- FUNCTION "?<" ( l, r : std_ulogic ) RETURN std_ulogic;
-- FUNCTION "?<=" ( l, r : std_ulogic ) RETURN std_ulogic;
function \?=\ (l, r : STD_ULOGIC) return STD_ULOGIC;
function \?=\ (l, r : STD_LOGIC_VECTOR) return STD_ULOGIC;
function \?=\ (l, r : STD_ULOGIC_VECTOR) return STD_ULOGIC;
function \?/=\ (l, r : STD_ULOGIC) return STD_ULOGIC;
function \?/=\ (l, r : STD_LOGIC_VECTOR) return STD_ULOGIC;
function \?/=\ (l, r : STD_ULOGIC_VECTOR) return STD_ULOGIC;
function \?>\ (l, r : STD_ULOGIC) return STD_ULOGIC;
function \?>=\ (l, r : STD_ULOGIC) return STD_ULOGIC;
function \?<\ (l, r : STD_ULOGIC) return STD_ULOGIC;
function \?<=\ (l, r : STD_ULOGIC) return STD_ULOGIC;
-- "??" operator, converts a std_ulogic to a boolean.
--%%% Uncomment the following operators
-- FUNCTION "??" (S : STD_ULOGIC) RETURN BOOLEAN;
--%%% REMOVE the following funciton (for testing only)
function \??\ (S : STD_ULOGIC) return BOOLEAN;
-- rtl_synthesis off
function to_string (value : STD_ULOGIC) return STRING;
function to_string (value : STD_ULOGIC_VECTOR) return STRING;
function to_string (value : STD_LOGIC_VECTOR) return STRING;
-- explicitly defined operations
alias TO_BSTRING is TO_STRING [STD_ULOGIC_VECTOR return STRING];
alias TO_BINARY_STRING is TO_STRING [STD_ULOGIC_VECTOR return STRING];
function TO_OSTRING (VALUE : STD_ULOGIC_VECTOR) return STRING;
alias TO_OCTAL_STRING is TO_OSTRING [STD_ULOGIC_VECTOR return STRING];
function TO_HSTRING (VALUE : STD_ULOGIC_VECTOR) return STRING;
alias TO_HEX_STRING is TO_HSTRING [STD_ULOGIC_VECTOR return STRING];
procedure READ (L : inout LINE; VALUE : out STD_ULOGIC; GOOD : out BOOLEAN);
procedure READ (L : inout LINE; VALUE : out STD_ULOGIC);
procedure READ (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR; GOOD : out BOOLEAN);
procedure READ (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR);
procedure WRITE (L : inout LINE; VALUE : in STD_ULOGIC;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0);
procedure WRITE (L : inout LINE; VALUE : in STD_ULOGIC_VECTOR;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0);
alias BREAD is READ [LINE, STD_ULOGIC_VECTOR, BOOLEAN];
alias BREAD is READ [LINE, STD_ULOGIC_VECTOR];
alias BINARY_READ is READ [LINE, STD_ULOGIC_VECTOR, BOOLEAN];
alias BINARY_READ is READ [LINE, STD_ULOGIC_VECTOR];
procedure OREAD (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR; GOOD : out BOOLEAN);
procedure OREAD (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR);
alias OCTAL_READ is OREAD [LINE, STD_ULOGIC_VECTOR, BOOLEAN];
alias OCTAL_READ is OREAD [LINE, STD_ULOGIC_VECTOR];
-- procedure HREAD (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR; GOOD : out BOOLEAN);
-- procedure HREAD (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR);
-- alias HEX_READ is HREAD [LINE, STD_ULOGIC_VECTOR, BOOLEAN];
-- alias HEX_READ is HREAD [LINE, STD_ULOGIC_VECTOR];
alias BWRITE is WRITE [LINE, STD_ULOGIC_VECTOR, SIDE, WIDTH];
alias BINARY_WRITE is WRITE [LINE, STD_ULOGIC_VECTOR, SIDE, WIDTH];
procedure OWRITE (L : inout LINE; VALUE : in STD_ULOGIC_VECTOR;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0);
alias OCTAL_WRITE is OWRITE [LINE, STD_ULOGIC_VECTOR, SIDE, WIDTH];
procedure HWRITE (L : inout LINE; VALUE : in STD_ULOGIC_VECTOR;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0);
alias HEX_WRITE is HWRITE [LINE, STD_ULOGIC_VECTOR, SIDE, WIDTH];
alias TO_BSTRING is TO_STRING [STD_LOGIC_VECTOR return STRING];
alias TO_BINARY_STRING is TO_STRING [STD_LOGIC_VECTOR return STRING];
function TO_OSTRING (VALUE : STD_LOGIC_VECTOR) return STRING;
alias TO_OCTAL_STRING is TO_OSTRING [STD_LOGIC_VECTOR return STRING];
function TO_HSTRING (VALUE : STD_LOGIC_VECTOR) return STRING;
alias TO_HEX_STRING is TO_HSTRING [STD_LOGIC_VECTOR return STRING];
procedure READ (L : inout LINE; VALUE : out STD_LOGIC_VECTOR; GOOD : out BOOLEAN);
procedure READ (L : inout LINE; VALUE : out STD_LOGIC_VECTOR);
procedure WRITE (L : inout LINE; VALUE : in STD_LOGIC_VECTOR;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0);
alias BREAD is READ [LINE, STD_LOGIC_VECTOR, BOOLEAN];
alias BREAD is READ [LINE, STD_LOGIC_VECTOR];
alias BINARY_READ is READ [LINE, STD_LOGIC_VECTOR, BOOLEAN];
alias BINARY_READ is READ [LINE, STD_LOGIC_VECTOR];
procedure OREAD (L : inout LINE; VALUE : out STD_LOGIC_VECTOR; GOOD : out BOOLEAN);
procedure OREAD (L : inout LINE; VALUE : out STD_LOGIC_VECTOR);
alias OCTAL_READ is OREAD [LINE, STD_LOGIC_VECTOR, BOOLEAN];
alias OCTAL_READ is OREAD [LINE, STD_LOGIC_VECTOR];
-- procedure HREAD (L : inout LINE; VALUE : out STD_LOGIC_VECTOR; GOOD : out BOOLEAN);
-- procedure HREAD (L : inout LINE; VALUE : out STD_LOGIC_VECTOR);
-- alias HEX_READ is HREAD [LINE, STD_LOGIC_VECTOR, BOOLEAN];
-- alias HEX_READ is HREAD [LINE, STD_LOGIC_VECTOR];
alias BWRITE is WRITE [LINE, STD_LOGIC_VECTOR, SIDE, WIDTH];
alias BINARY_WRITE is WRITE [LINE, STD_LOGIC_VECTOR, SIDE, WIDTH];
procedure OWRITE (L : inout LINE; VALUE : in STD_LOGIC_VECTOR;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0);
alias OCTAL_WRITE is OWRITE [LINE, STD_LOGIC_VECTOR, SIDE, WIDTH];
procedure HWRITE (L : inout LINE; VALUE : in STD_LOGIC_VECTOR;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0);
alias HEX_WRITE is HWRITE [LINE, STD_LOGIC_VECTOR, SIDE, WIDTH];
-- rtl_synthesis on
function maximum (l, r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
function maximum (l, r : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function maximum (l, r : STD_ULOGIC) return STD_ULOGIC;
function minimum (l, r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
function minimum (l, r : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function minimum (l, r : STD_ULOGIC) return STD_ULOGIC;
end package std_logic_1164_additions;
package body std_logic_1164_additions is
type stdlogic_table is array(STD_ULOGIC, STD_ULOGIC) of STD_ULOGIC;
-----------------------------------------------------------------------------
-- New/updated funcitons for VHDL-200X fast track
-----------------------------------------------------------------------------
-------------------------------------------------------------------
-- overloaded shift operators
-------------------------------------------------------------------
-------------------------------------------------------------------
-- sll
-------------------------------------------------------------------
function "sll" (l : STD_LOGIC_VECTOR; r : INTEGER) return STD_LOGIC_VECTOR is
alias lv : STD_LOGIC_VECTOR (1 to l'length) is l;
variable result : STD_LOGIC_VECTOR (1 to l'length) := (others => '0');
begin
if r >= 0 then
result(1 to l'length - r) := lv(r + 1 to l'length);
else
result := l srl -r;
end if;
return result;
end function "sll";
-------------------------------------------------------------------
function "sll" (l : STD_ULOGIC_VECTOR; r : INTEGER) return STD_ULOGIC_VECTOR is
alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;
variable result : STD_ULOGIC_VECTOR (1 to l'length) := (others => '0');
begin
if r >= 0 then
result(1 to l'length - r) := lv(r + 1 to l'length);
else
result := l srl -r;
end if;
return result;
end function "sll";
-------------------------------------------------------------------
-- srl
-------------------------------------------------------------------
function "srl" (l : STD_LOGIC_VECTOR; r : INTEGER) return STD_LOGIC_VECTOR is
alias lv : STD_LOGIC_VECTOR (1 to l'length) is l;
variable result : STD_LOGIC_VECTOR (1 to l'length) := (others => '0');
begin
if r >= 0 then
result(r + 1 to l'length) := lv(1 to l'length - r);
else
result := l sll -r;
end if;
return result;
end function "srl";
-------------------------------------------------------------------
function "srl" (l : STD_ULOGIC_VECTOR; r : INTEGER) return STD_ULOGIC_VECTOR is
alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;
variable result : STD_ULOGIC_VECTOR (1 to l'length) := (others => '0');
begin
if r >= 0 then
result(r + 1 to l'length) := lv(1 to l'length - r);
else
result := l sll -r;
end if;
return result;
end function "srl";
-------------------------------------------------------------------
-- rol
-------------------------------------------------------------------
function "rol" (l : STD_LOGIC_VECTOR; r : INTEGER) return STD_LOGIC_VECTOR is
alias lv : STD_LOGIC_VECTOR (1 to l'length) is l;
variable result : STD_LOGIC_VECTOR (1 to l'length);
constant rm : INTEGER := r mod l'length;
begin
if r >= 0 then
result(1 to l'length - rm) := lv(rm + 1 to l'length);
result(l'length - rm + 1 to l'length) := lv(1 to rm);
else
result := l ror -r;
end if;
return result;
end function "rol";
-------------------------------------------------------------------
function "rol" (l : STD_ULOGIC_VECTOR; r : INTEGER) return STD_ULOGIC_VECTOR is
alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;
variable result : STD_ULOGIC_VECTOR (1 to l'length);
constant rm : INTEGER := r mod l'length;
begin
if r >= 0 then
result(1 to l'length - rm) := lv(rm + 1 to l'length);
result(l'length - rm + 1 to l'length) := lv(1 to rm);
else
result := l ror -r;
end if;
return result;
end function "rol";
-------------------------------------------------------------------
-- ror
-------------------------------------------------------------------
function "ror" (l : STD_LOGIC_VECTOR; r : INTEGER) return STD_LOGIC_VECTOR is
alias lv : STD_LOGIC_VECTOR (1 to l'length) is l;
variable result : STD_LOGIC_VECTOR (1 to l'length) := (others => '0');
constant rm : INTEGER := r mod l'length;
begin
if r >= 0 then
result(rm + 1 to l'length) := lv(1 to l'length - rm);
result(1 to rm) := lv(l'length - rm + 1 to l'length);
else
result := l rol -r;
end if;
return result;
end function "ror";
-------------------------------------------------------------------
function "ror" (l : STD_ULOGIC_VECTOR; r : INTEGER) return STD_ULOGIC_VECTOR is
alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;
variable result : STD_ULOGIC_VECTOR (1 to l'length) := (others => '0');
constant rm : INTEGER := r mod l'length;
begin
if r >= 0 then
result(rm + 1 to l'length) := lv(1 to l'length - rm);
result(1 to rm) := lv(l'length - rm + 1 to l'length);
else
result := l rol -r;
end if;
return result;
end function "ror";
-------------------------------------------------------------------
-- vector/scalar overloaded logical operators
-------------------------------------------------------------------
-------------------------------------------------------------------
-- and
-------------------------------------------------------------------
function "and" (l : STD_LOGIC_VECTOR; r : STD_ULOGIC) return STD_LOGIC_VECTOR is
alias lv : STD_LOGIC_VECTOR (1 to l'length) is l;
variable result : STD_LOGIC_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := "and" (lv(i), r);
end loop;
return result;
end function "and";
-------------------------------------------------------------------
function "and" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) return STD_ULOGIC_VECTOR is
alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;
variable result : STD_ULOGIC_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := "and" (lv(i), r);
end loop;
return result;
end function "and";
-------------------------------------------------------------------
function "and" (l : STD_ULOGIC; r : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
alias rv : STD_LOGIC_VECTOR (1 to r'length) is r;
variable result : STD_LOGIC_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := "and" (l, rv(i));
end loop;
return result;
end function "and";
-------------------------------------------------------------------
function "and" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
alias rv : STD_ULOGIC_VECTOR (1 to r'length) is r;
variable result : STD_ULOGIC_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := "and" (l, rv(i));
end loop;
return result;
end function "and";
-------------------------------------------------------------------
-- nand
-------------------------------------------------------------------
function "nand" (l : STD_LOGIC_VECTOR; r : STD_ULOGIC) return STD_LOGIC_VECTOR is
alias lv : STD_LOGIC_VECTOR (1 to l'length) is l;
variable result : STD_LOGIC_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := "not"("and" (lv(i), r));
end loop;
return result;
end function "nand";
-------------------------------------------------------------------
function "nand" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) return STD_ULOGIC_VECTOR is
alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;
variable result : STD_ULOGIC_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := "not"("and" (lv(i), r));
end loop;
return result;
end function "nand";
-------------------------------------------------------------------
function "nand" (l : STD_ULOGIC; r : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
alias rv : STD_LOGIC_VECTOR (1 to r'length) is r;
variable result : STD_LOGIC_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := "not"("and" (l, rv(i)));
end loop;
return result;
end function "nand";
-------------------------------------------------------------------
function "nand" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
alias rv : STD_ULOGIC_VECTOR (1 to r'length) is r;
variable result : STD_ULOGIC_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := "not"("and" (l, rv(i)));
end loop;
return result;
end function "nand";
-------------------------------------------------------------------
-- or
-------------------------------------------------------------------
function "or" (l : STD_LOGIC_VECTOR; r : STD_ULOGIC) return STD_LOGIC_VECTOR is
alias lv : STD_LOGIC_VECTOR (1 to l'length) is l;
variable result : STD_LOGIC_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := "or" (lv(i), r);
end loop;
return result;
end function "or";
-------------------------------------------------------------------
function "or" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) return STD_ULOGIC_VECTOR is
alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;
variable result : STD_ULOGIC_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := "or" (lv(i), r);
end loop;
return result;
end function "or";
-------------------------------------------------------------------
function "or" (l : STD_ULOGIC; r : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
alias rv : STD_LOGIC_VECTOR (1 to r'length) is r;
variable result : STD_LOGIC_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := "or" (l, rv(i));
end loop;
return result;
end function "or";
-------------------------------------------------------------------
function "or" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
alias rv : STD_ULOGIC_VECTOR (1 to r'length) is r;
variable result : STD_ULOGIC_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := "or" (l, rv(i));
end loop;
return result;
end function "or";
-------------------------------------------------------------------
-- nor
-------------------------------------------------------------------
function "nor" (l : STD_LOGIC_VECTOR; r : STD_ULOGIC) return STD_LOGIC_VECTOR is
alias lv : STD_LOGIC_VECTOR (1 to l'length) is l;
variable result : STD_LOGIC_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := "not"("or" (lv(i), r));
end loop;
return result;
end function "nor";
-------------------------------------------------------------------
function "nor" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) return STD_ULOGIC_VECTOR is
alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;
variable result : STD_ULOGIC_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := "not"("or" (lv(i), r));
end loop;
return result;
end function "nor";
-------------------------------------------------------------------
function "nor" (l : STD_ULOGIC; r : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
alias rv : STD_LOGIC_VECTOR (1 to r'length) is r;
variable result : STD_LOGIC_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := "not"("or" (l, rv(i)));
end loop;
return result;
end function "nor";
-------------------------------------------------------------------
function "nor" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
alias rv : STD_ULOGIC_VECTOR (1 to r'length) is r;
variable result : STD_ULOGIC_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := "not"("or" (l, rv(i)));
end loop;
return result;
end function "nor";
-------------------------------------------------------------------
-- xor
-------------------------------------------------------------------
function "xor" (l : STD_LOGIC_VECTOR; r : STD_ULOGIC) return STD_LOGIC_VECTOR is
alias lv : STD_LOGIC_VECTOR (1 to l'length) is l;
variable result : STD_LOGIC_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := "xor" (lv(i), r);
end loop;
return result;
end function "xor";
-------------------------------------------------------------------
function "xor" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) return STD_ULOGIC_VECTOR is
alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;
variable result : STD_ULOGIC_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := "xor" (lv(i), r);
end loop;
return result;
end function "xor";
-------------------------------------------------------------------
function "xor" (l : STD_ULOGIC; r : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
alias rv : STD_LOGIC_VECTOR (1 to r'length) is r;
variable result : STD_LOGIC_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := "xor" (l, rv(i));
end loop;
return result;
end function "xor";
-------------------------------------------------------------------
function "xor" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
alias rv : STD_ULOGIC_VECTOR (1 to r'length) is r;
variable result : STD_ULOGIC_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := "xor" (l, rv(i));
end loop;
return result;
end function "xor";
-------------------------------------------------------------------
-- xnor
-------------------------------------------------------------------
function "xnor" (l : STD_LOGIC_VECTOR; r : STD_ULOGIC) return STD_LOGIC_VECTOR is
alias lv : STD_LOGIC_VECTOR (1 to l'length) is l;
variable result : STD_LOGIC_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := "not"("xor" (lv(i), r));
end loop;
return result;
end function "xnor";
-------------------------------------------------------------------
function "xnor" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) return STD_ULOGIC_VECTOR is
alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;
variable result : STD_ULOGIC_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := "not"("xor" (lv(i), r));
end loop;
return result;
end function "xnor";
-------------------------------------------------------------------
function "xnor" (l : STD_ULOGIC; r : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
alias rv : STD_LOGIC_VECTOR (1 to r'length) is r;
variable result : STD_LOGIC_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := "not"("xor" (l, rv(i)));
end loop;
return result;
end function "xnor";
-------------------------------------------------------------------
function "xnor" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
alias rv : STD_ULOGIC_VECTOR (1 to r'length) is r;
variable result : STD_ULOGIC_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := "not"("xor" (l, rv(i)));
end loop;
return result;
end function "xnor";
-------------------------------------------------------------------
-- vector-reduction functions
-------------------------------------------------------------------
-------------------------------------------------------------------
-- and
-------------------------------------------------------------------
function and_reduce (l : STD_LOGIC_VECTOR) return STD_ULOGIC is
begin
return and_reduce (to_StdULogicVector (l));
end function and_reduce;
-------------------------------------------------------------------
function and_reduce (l : STD_ULOGIC_VECTOR) return STD_ULOGIC is
variable result : STD_ULOGIC := '1';
begin
for i in l'reverse_range loop
result := (l(i) and result);
end loop;
return result;
end function and_reduce;
-------------------------------------------------------------------
-- nand
-------------------------------------------------------------------
function nand_reduce (l : STD_LOGIC_VECTOR) return STD_ULOGIC is
begin
return not (and_reduce(to_StdULogicVector(l)));
end function nand_reduce;
-------------------------------------------------------------------
function nand_reduce (l : STD_ULOGIC_VECTOR) return STD_ULOGIC is
begin
return not (and_reduce(l));
end function nand_reduce;
-------------------------------------------------------------------
-- or
-------------------------------------------------------------------
function or_reduce (l : STD_LOGIC_VECTOR) return STD_ULOGIC is
begin
return or_reduce (to_StdULogicVector (l));
end function or_reduce;
-------------------------------------------------------------------
function or_reduce (l : STD_ULOGIC_VECTOR) return STD_ULOGIC is
variable result : STD_ULOGIC := '0';
begin
for i in l'reverse_range loop
result := (l(i) or result);
end loop;
return result;
end function or_reduce;
-------------------------------------------------------------------
-- nor
-------------------------------------------------------------------
function nor_reduce (l : STD_LOGIC_VECTOR) return STD_ULOGIC is
begin
return "not"(or_reduce(To_StdULogicVector(l)));
end function nor_reduce;
-------------------------------------------------------------------
function nor_reduce (l : STD_ULOGIC_VECTOR) return STD_ULOGIC is
begin
return "not"(or_reduce(l));
end function nor_reduce;
-------------------------------------------------------------------
-- xor
-------------------------------------------------------------------
function xor_reduce (l : STD_LOGIC_VECTOR) return STD_ULOGIC is
begin
return xor_reduce (to_StdULogicVector (l));
end function xor_reduce;
-------------------------------------------------------------------
function xor_reduce (l : STD_ULOGIC_VECTOR) return STD_ULOGIC is
variable result : STD_ULOGIC := '0';
begin
for i in l'reverse_range loop
result := (l(i) xor result);
end loop;
return result;
end function xor_reduce;
-------------------------------------------------------------------
-- xnor
-------------------------------------------------------------------
function xnor_reduce (l : STD_LOGIC_VECTOR) return STD_ULOGIC is
begin
return "not"(xor_reduce(To_StdULogicVector(l)));
end function xnor_reduce;
-------------------------------------------------------------------
function xnor_reduce (l : STD_ULOGIC_VECTOR) return STD_ULOGIC is
begin
return "not"(xor_reduce(l));
end function xnor_reduce;
-- %%% End "remove the following functions"
-- The following functions are implicity in 1076-2006
-- truth table for "?=" function
constant match_logic_table : stdlogic_table := (
-----------------------------------------------------
-- U X 0 1 Z W L H - | |
-----------------------------------------------------
('U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', '1'), -- | U |
('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '1'), -- | X |
('U', 'X', '1', '0', 'X', 'X', '1', '0', '1'), -- | 0 |
('U', 'X', '0', '1', 'X', 'X', '0', '1', '1'), -- | 1 |
('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '1'), -- | Z |
('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '1'), -- | W |
('U', 'X', '1', '0', 'X', 'X', '1', '0', '1'), -- | L |
('U', 'X', '0', '1', 'X', 'X', '0', '1', '1'), -- | H |
('1', '1', '1', '1', '1', '1', '1', '1', '1') -- | - |
);
constant no_match_logic_table : stdlogic_table := (
-----------------------------------------------------
-- U X 0 1 Z W L H - | |
-----------------------------------------------------
('U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', '0'), -- | U |
('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '0'), -- | X |
('U', 'X', '0', '1', 'X', 'X', '0', '1', '0'), -- | 0 |
('U', 'X', '1', '0', 'X', 'X', '1', '0', '0'), -- | 1 |
('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '0'), -- | Z |
('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '0'), -- | W |
('U', 'X', '0', '1', 'X', 'X', '0', '1', '0'), -- | L |
('U', 'X', '1', '0', 'X', 'X', '1', '0', '0'), -- | H |
('0', '0', '0', '0', '0', '0', '0', '0', '0') -- | - |
);
-------------------------------------------------------------------
-- ?= functions, Similar to "std_match", but returns "std_ulogic".
-------------------------------------------------------------------
-- %%% FUNCTION "?=" ( l, r : std_ulogic ) RETURN std_ulogic IS
function \?=\ (l, r : STD_ULOGIC) return STD_ULOGIC is
begin
return match_logic_table (l, r);
end function \?=\;
-- %%% END FUNCTION "?=";
-------------------------------------------------------------------
-- %%% FUNCTION "?=" ( l, r : std_logic_vector ) RETURN std_ulogic IS
function \?=\ (l, r : STD_LOGIC_VECTOR) return STD_ULOGIC is
alias lv : STD_LOGIC_VECTOR(1 to l'length) is l;
alias rv : STD_LOGIC_VECTOR(1 to r'length) is r;
variable result, result1 : STD_ULOGIC; -- result
begin
-- Logically identical to an "=" operator.
if ((l'length < 1) or (r'length < 1)) then
report "STD_LOGIC_1164.""?="": null detected, returning X"
severity warning;
return 'X';
end if;
if lv'length /= rv'length then
report "STD_LOGIC_1164.""?="": L'LENGTH /= R'LENGTH, returning X"
severity warning;
return 'X';
else
result := '1';
for i in lv'low to lv'high loop
result1 := match_logic_table(lv(i), rv(i));
if result1 = 'U' then
return 'U';
elsif result1 = 'X' or result = 'X' then
result := 'X';
else
result := result and result1;
end if;
end loop;
return result;
end if;
end function \?=\;
-- %%% END FUNCTION "?=";
-------------------------------------------------------------------
-- %%% FUNCTION "?=" ( l, r : std_ulogic_vector ) RETURN std_ulogic IS
function \?=\ (l, r : STD_ULOGIC_VECTOR) return STD_ULOGIC is
alias lv : STD_ULOGIC_VECTOR(1 to l'length) is l;
alias rv : STD_ULOGIC_VECTOR(1 to r'length) is r;
variable result, result1 : STD_ULOGIC;
begin
if ((l'length < 1) or (r'length < 1)) then
report "STD_LOGIC_1164.""?="": null detected, returning X"
severity warning;
return 'X';
end if;
if lv'length /= rv'length then
report "STD_LOGIC_1164.""?="": L'LENGTH /= R'LENGTH, returning X"
severity warning;
return 'X';
else
result := '1';
for i in lv'low to lv'high loop
result1 := match_logic_table(lv(i), rv(i));
if result1 = 'U' then
return 'U';
elsif result1 = 'X' or result = 'X' then
result := 'X';
else
result := result and result1;
end if;
end loop;
return result;
end if;
end function \?=\;
-- %%% END FUNCTION "?=";
-- %%% FUNCTION "?/=" ( l, r : std_ulogic ) RETURN std_ulogic is
function \?/=\ (l, r : STD_ULOGIC) return STD_ULOGIC is
begin
return no_match_logic_table (l, r);
end function \?/=\;
-- %%% END FUNCTION "?/=";
-- %%% FUNCTION "?/=" ( l, r : std_logic_vector ) RETURN std_ulogic is
function \?/=\ (l, r : STD_LOGIC_VECTOR) return STD_ULOGIC is
alias lv : STD_LOGIC_VECTOR(1 to l'length) is l;
alias rv : STD_LOGIC_VECTOR(1 to r'length) is r;
variable result, result1 : STD_ULOGIC; -- result
begin
if ((l'length < 1) or (r'length < 1)) then
report "STD_LOGIC_1164.""?/="": null detected, returning X"
severity warning;
return 'X';
end if;
if lv'length /= rv'length then
report "STD_LOGIC_1164.""?/="": L'LENGTH /= R'LENGTH, returning X"
severity warning;
return 'X';
else
result := '0';
for i in lv'low to lv'high loop
result1 := no_match_logic_table(lv(i), rv(i));
if result1 = 'U' then
return 'U';
elsif result1 = 'X' or result = 'X' then
result := 'X';
else
result := result or result1;
end if;
end loop;
return result;
end if;
end function \?/=\;
-- %%% END FUNCTION "?/=";
-- %%% FUNCTION "?/=" ( l, r : std_ulogic_vector ) RETURN std_ulogic is
function \?/=\ (l, r : STD_ULOGIC_VECTOR) return STD_ULOGIC is
alias lv : STD_ULOGIC_VECTOR(1 to l'length) is l;
alias rv : STD_ULOGIC_VECTOR(1 to r'length) is r;
variable result, result1 : STD_ULOGIC;
begin
if ((l'length < 1) or (r'length < 1)) then
report "STD_LOGIC_1164.""?/="": null detected, returning X"
severity warning;
return 'X';
end if;
if lv'length /= rv'length then
report "STD_LOGIC_1164.""?/="": L'LENGTH /= R'LENGTH, returning X"
severity warning;
return 'X';
else
result := '0';
for i in lv'low to lv'high loop
result1 := no_match_logic_table(lv(i), rv(i));
if result1 = 'U' then
return 'U';
elsif result1 = 'X' or result = 'X' then
result := 'X';
else
result := result or result1;
end if;
end loop;
return result;
end if;
end function \?/=\;
-- %%% END FUNCTION "?/=";
-- %%% FUNCTION "?>" ( l, r : std_ulogic ) RETURN std_ulogic is
function \?>\ (l, r : STD_ULOGIC) return STD_ULOGIC is
variable lx, rx : STD_ULOGIC;
begin
if (l = '-') or (r = '-') then
report "STD_LOGIC_1164.""?>"": '-' found in compare string"
severity error;
return 'X';
else
lx := to_x01 (l);
rx := to_x01 (r);
if lx = 'X' or rx = 'X' then
return 'X';
elsif lx > rx then
return '1';
else
return '0';
end if;
end if;
end function \?>\;
-- %%% END FUNCTION "?>";
-- %%% FUNCTION "?>=" ( l, r : std_ulogic ) RETURN std_ulogic is
function \?>=\ (l, r : STD_ULOGIC) return STD_ULOGIC is
variable lx, rx : STD_ULOGIC;
begin
if (l = '-') or (r = '-') then
report "STD_LOGIC_1164.""?>="": '-' found in compare string"
severity error;
return 'X';
else
lx := to_x01 (l);
rx := to_x01 (r);
if lx = 'X' or rx = 'X' then
return 'X';
elsif lx >= rx then
return '1';
else
return '0';
end if;
end if;
end function \?>=\;
-- %%% END FUNCTION "?/>=";
-- %%% FUNCTION "?<" ( l, r : std_ulogic ) RETURN std_ulogic is
function \?<\ (l, r : STD_ULOGIC) return STD_ULOGIC is
variable lx, rx : STD_ULOGIC;
begin
if (l = '-') or (r = '-') then
report "STD_LOGIC_1164.""?<"": '-' found in compare string"
severity error;
return 'X';
else
lx := to_x01 (l);
rx := to_x01 (r);
if lx = 'X' or rx = 'X' then
return 'X';
elsif lx < rx then
return '1';
else
return '0';
end if;
end if;
end function \?<\;
-- %%% END FUNCTION "?/<";
-- %%% FUNCTION "?<=" ( l, r : std_ulogic ) RETURN std_ulogic is
function \?<=\ (l, r : STD_ULOGIC) return STD_ULOGIC is
variable lx, rx : STD_ULOGIC;
begin
if (l = '-') or (r = '-') then
report "STD_LOGIC_1164.""?<="": '-' found in compare string"
severity error;
return 'X';
else
lx := to_x01 (l);
rx := to_x01 (r);
if lx = 'X' or rx = 'X' then
return 'X';
elsif lx <= rx then
return '1';
else
return '0';
end if;
end if;
end function \?<=\;
-- %%% END FUNCTION "?/<=";
-- "??" operator, converts a std_ulogic to a boolean.
-- %%% FUNCTION "??"
function \??\ (S : STD_ULOGIC) return BOOLEAN is
begin
return S = '1' or S = 'H';
end function \??\;
-- %%% END FUNCTION "??";
-- rtl_synthesis off
-----------------------------------------------------------------------------
-- This section copied from "std_logic_textio"
-----------------------------------------------------------------------------
-- Type and constant definitions used to map STD_ULOGIC values
-- into/from character values.
type MVL9plus is ('U', 'X', '0', '1', 'Z', 'W', 'L', 'H', '-', error);
type char_indexed_by_MVL9 is array (STD_ULOGIC) of CHARACTER;
type MVL9_indexed_by_char is array (CHARACTER) of STD_ULOGIC;
type MVL9plus_indexed_by_char is array (CHARACTER) of MVL9plus;
constant MVL9_to_char : char_indexed_by_MVL9 := "UX01ZWLH-";
constant char_to_MVL9 : MVL9_indexed_by_char :=
('U' => 'U', 'X' => 'X', '0' => '0', '1' => '1', 'Z' => 'Z',
'W' => 'W', 'L' => 'L', 'H' => 'H', '-' => '-', others => 'U');
constant char_to_MVL9plus : MVL9plus_indexed_by_char :=
('U' => 'U', 'X' => 'X', '0' => '0', '1' => '1', 'Z' => 'Z',
'W' => 'W', 'L' => 'L', 'H' => 'H', '-' => '-', others => error);
constant NBSP : CHARACTER := CHARACTER'val(160); -- space character
constant NUS : STRING(2 to 1) := (others => ' '); -- null STRING
-- purpose: Skips white space
procedure skip_whitespace (
L : inout LINE) is
variable readOk : BOOLEAN;
variable c : CHARACTER;
begin
while L /= null and L.all'length /= 0 loop
if (L.all(1) = ' ' or L.all(1) = NBSP or L.all(1) = HT) then
read (l, c, readOk);
else
exit;
end if;
end loop;
end procedure skip_whitespace;
procedure READ (L : inout LINE; VALUE : out STD_ULOGIC;
GOOD : out BOOLEAN) is
variable c : CHARACTER;
variable readOk : BOOLEAN;
begin
VALUE := 'U'; -- initialize to a "U"
Skip_whitespace (L);
read (l, c, readOk);
if not readOk then
good := false;
else
if char_to_MVL9plus(c) = error then
good := false;
else
VALUE := char_to_MVL9(c);
good := true;
end if;
end if;
end procedure READ;
procedure READ (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR;
GOOD : out BOOLEAN) is
variable m : STD_ULOGIC;
variable c : CHARACTER;
variable mv : STD_ULOGIC_VECTOR(0 to VALUE'length-1);
variable readOk : BOOLEAN;
variable i : INTEGER;
variable lastu : BOOLEAN := false; -- last character was an "_"
begin
VALUE := (VALUE'range => 'U'); -- initialize to a "U"
Skip_whitespace (L);
if VALUE'length > 0 then
read (l, c, readOk);
i := 0;
good := false;
while i < VALUE'length loop
if not readOk then -- Bail out if there was a bad read
return;
elsif c = '_' then
if i = 0 then -- Begins with an "_"
return;
elsif lastu then -- "__" detected
return;
else
lastu := true;
end if;
elsif (char_to_MVL9plus(c) = error) then -- Illegal character
return;
else
mv(i) := char_to_MVL9(c);
i := i + 1;
if i > mv'high then -- reading done
good := true;
VALUE := mv;
return;
end if;
lastu := false;
end if;
read(L, c, readOk);
end loop;
else
good := true; -- read into a null array
end if;
end procedure READ;
procedure READ (L : inout LINE; VALUE : out STD_ULOGIC) is
variable c : CHARACTER;
variable readOk : BOOLEAN;
begin
VALUE := 'U'; -- initialize to a "U"
Skip_whitespace (L);
read (l, c, readOk);
if not readOk then
report "STD_LOGIC_1164.READ(STD_ULOGIC) "
& "End of string encountered"
severity error;
return;
elsif char_to_MVL9plus(c) = error then
report
"STD_LOGIC_1164.READ(STD_ULOGIC) Error: Character '" &
c & "' read, expected STD_ULOGIC literal."
severity error;
else
VALUE := char_to_MVL9(c);
end if;
end procedure READ;
procedure READ (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR) is
variable m : STD_ULOGIC;
variable c : CHARACTER;
variable readOk : BOOLEAN;
variable mv : STD_ULOGIC_VECTOR(0 to VALUE'length-1);
variable i : INTEGER;
variable lastu : BOOLEAN := false; -- last character was an "_"
begin
VALUE := (VALUE'range => 'U'); -- initialize to a "U"
Skip_whitespace (L);
if VALUE'length > 0 then -- non Null input string
read (l, c, readOk);
i := 0;
while i < VALUE'length loop
if readOk = false then -- Bail out if there was a bad read
report "STD_LOGIC_1164.READ(STD_ULOGIC_VECTOR) "
& "End of string encountered"
severity error;
return;
elsif c = '_' then
if i = 0 then
report "STD_LOGIC_1164.READ(STD_ULOGIC_VECTOR) "
& "String begins with an ""_""" severity error;
return;
elsif lastu then
report "STD_LOGIC_1164.READ(STD_ULOGIC_VECTOR) "
& "Two underscores detected in input string ""__"""
severity error;
return;
else
lastu := true;
end if;
elsif c = ' ' or c = NBSP or c = HT then -- reading done.
report "STD_LOGIC_1164.READ(STD_ULOGIC_VECTOR) "
& "Short read, Space encounted in input string"
severity error;
return;
elsif char_to_MVL9plus(c) = error then
report "STD_LOGIC_1164.READ(STD_ULOGIC_VECTOR) "
& "Error: Character '" &
c & "' read, expected STD_ULOGIC literal."
severity error;
return;
else
mv(i) := char_to_MVL9(c);
i := i + 1;
if i > mv'high then
VALUE := mv;
return;
end if;
lastu := false;
end if;
read(L, c, readOk);
end loop;
end if;
end procedure READ;
procedure WRITE (L : inout LINE; VALUE : in STD_ULOGIC;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is
begin
write(l, MVL9_to_char(VALUE), justified, field);
end procedure WRITE;
procedure WRITE (L : inout LINE; VALUE : in STD_ULOGIC_VECTOR;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is
variable s : STRING(1 to VALUE'length);
variable m : STD_ULOGIC_VECTOR(1 to VALUE'length) := VALUE;
begin
for i in 1 to VALUE'length loop
s(i) := MVL9_to_char(m(i));
end loop;
write(l, s, justified, field);
end procedure WRITE;
-- Read and Write procedures for STD_LOGIC_VECTOR
procedure READ (L : inout LINE; VALUE : out STD_LOGIC_VECTOR;
GOOD : out BOOLEAN) is
variable ivalue : STD_ULOGIC_VECTOR (VALUE'range);
begin
READ (L => L, VALUE => ivalue, GOOD => GOOD);
VALUE := to_stdlogicvector (ivalue);
end procedure READ;
procedure READ (L : inout LINE; VALUE : out STD_LOGIC_VECTOR) is
variable ivalue : STD_ULOGIC_VECTOR (VALUE'range);
begin
READ (L => L, VALUE => ivalue);
VALUE := to_stdlogicvector (ivalue);
end procedure READ;
procedure WRITE (L : inout LINE; VALUE : in STD_LOGIC_VECTOR;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is
variable s : STRING(1 to VALUE'length);
variable m : STD_LOGIC_VECTOR(1 to VALUE'length) := VALUE;
begin
for i in 1 to VALUE'length loop
s(i) := MVL9_to_char(m(i));
end loop;
write(L, s, justified, field);
end procedure WRITE;
-----------------------------------------------------------------------
-- Alias for bread and bwrite are provided with call out the read and
-- write functions.
-----------------------------------------------------------------------
-- Hex Read and Write procedures for STD_ULOGIC_VECTOR.
-- Modified from the original to be more forgiving.
procedure Char2QuadBits (C : CHARACTER;
RESULT : out STD_ULOGIC_VECTOR(3 downto 0);
GOOD : out BOOLEAN;
ISSUE_ERROR : in BOOLEAN) is
begin
case c is
when '0' => result := x"0"; good := true;
when '1' => result := x"1"; good := true;
when '2' => result := x"2"; good := true;
when '3' => result := x"3"; good := true;
when '4' => result := x"4"; good := true;
when '5' => result := x"5"; good := true;
when '6' => result := x"6"; good := true;
when '7' => result := x"7"; good := true;
when '8' => result := x"8"; good := true;
when '9' => result := x"9"; good := true;
when 'A' | 'a' => result := x"A"; good := true;
when 'B' | 'b' => result := x"B"; good := true;
when 'C' | 'c' => result := x"C"; good := true;
when 'D' | 'd' => result := x"D"; good := true;
when 'E' | 'e' => result := x"E"; good := true;
when 'F' | 'f' => result := x"F"; good := true;
when 'Z' => result := "ZZZZ"; good := true;
when 'X' => result := "XXXX"; good := true;
when others =>
assert not ISSUE_ERROR
report
"STD_LOGIC_1164.HREAD Read a '" & c &
"', expected a Hex character (0-F)."
severity error;
good := false;
end case;
end procedure Char2QuadBits;
-- procedure HREAD (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR;
-- GOOD : out BOOLEAN) is
-- variable ok : BOOLEAN;
-- variable c : CHARACTER;
-- constant ne : INTEGER := (VALUE'length+3)/4;
-- constant pad : INTEGER := ne*4 - VALUE'length;
-- variable sv : STD_ULOGIC_VECTOR(0 to ne*4 - 1);
-- variable i : INTEGER;
-- variable lastu : BOOLEAN := false; -- last character was an "_"
-- begin
-- VALUE := (VALUE'range => 'U'); -- initialize to a "U"
-- Skip_whitespace (L);
-- if VALUE'length > 0 then
-- read (l, c, ok);
-- i := 0;
-- while i < ne loop
-- -- Bail out if there was a bad read
-- if not ok then
-- good := false;
-- return;
-- elsif c = '_' then
-- if i = 0 then
-- good := false; -- Begins with an "_"
-- return;
-- elsif lastu then
-- good := false; -- "__" detected
-- return;
-- else
-- lastu := true;
-- end if;
-- else
-- Char2QuadBits(c, sv(4*i to 4*i+3), ok, false);
-- if not ok then
-- good := false;
-- return;
-- end if;
-- i := i + 1;
-- lastu := false;
-- end if;
-- if i < ne then
-- read(L, c, ok);
-- end if;
-- end loop;
-- if or_reduce (sv (0 to pad-1)) = '1' then -- %%% replace with "or"
-- good := false; -- vector was truncated.
-- else
-- good := true;
-- VALUE := sv (pad to sv'high);
-- end if;
-- else
-- good := true; -- Null input string, skips whitespace
-- end if;
-- end procedure HREAD;
-- procedure HREAD (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR) is
-- variable ok : BOOLEAN;
-- variable c : CHARACTER;
-- constant ne : INTEGER := (VALUE'length+3)/4;
-- constant pad : INTEGER := ne*4 - VALUE'length;
-- variable sv : STD_ULOGIC_VECTOR(0 to ne*4 - 1);
-- variable i : INTEGER;
-- variable lastu : BOOLEAN := false; -- last character was an "_"
-- begin
-- VALUE := (VALUE'range => 'U'); -- initialize to a "U"
-- Skip_whitespace (L);
-- if VALUE'length > 0 then -- non Null input string
-- read (l, c, ok);
-- i := 0;
-- while i < ne loop
-- -- Bail out if there was a bad read
-- if not ok then
-- report "STD_LOGIC_1164.HREAD "
-- & "End of string encountered"
-- severity error;
-- return;
-- end if;
-- if c = '_' then
-- if i = 0 then
-- report "STD_LOGIC_1164.HREAD "
-- & "String begins with an ""_""" severity error;
-- return;
-- elsif lastu then
-- report "STD_LOGIC_1164.HREAD "
-- & "Two underscores detected in input string ""__"""
-- severity error;
-- return;
-- else
-- lastu := true;
-- end if;
-- else
-- Char2QuadBits(c, sv(4*i to 4*i+3), ok, true);
-- if not ok then
-- return;
-- end if;
-- i := i + 1;
-- lastu := false;
-- end if;
-- if i < ne then
-- read(L, c, ok);
-- end if;
-- end loop;
-- if or_reduce (sv (0 to pad-1)) = '1' then -- %%% replace with "or"
-- report "STD_LOGIC_1164.HREAD Vector truncated"
-- severity error;
-- else
-- VALUE := sv (pad to sv'high);
-- end if;
-- end if;
-- end procedure HREAD;
procedure HWRITE (L : inout LINE; VALUE : in STD_ULOGIC_VECTOR;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is
begin
write (L, to_hstring (VALUE), JUSTIFIED, FIELD);
end procedure HWRITE;
-- Octal Read and Write procedures for STD_ULOGIC_VECTOR.
-- Modified from the original to be more forgiving.
procedure Char2TriBits (C : CHARACTER;
RESULT : out STD_ULOGIC_VECTOR(2 downto 0);
GOOD : out BOOLEAN;
ISSUE_ERROR : in BOOLEAN) is
begin
case c is
when '0' => result := o"0"; good := true;
when '1' => result := o"1"; good := true;
when '2' => result := o"2"; good := true;
when '3' => result := o"3"; good := true;
when '4' => result := o"4"; good := true;
when '5' => result := o"5"; good := true;
when '6' => result := o"6"; good := true;
when '7' => result := o"7"; good := true;
when 'Z' => result := "ZZZ"; good := true;
when 'X' => result := "XXX"; good := true;
when others =>
assert not ISSUE_ERROR
report
"STD_LOGIC_1164.OREAD Error: Read a '" & c &
"', expected an Octal character (0-7)."
severity error;
good := false;
end case;
end procedure Char2TriBits;
procedure OREAD (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR;
GOOD : out BOOLEAN) is
variable ok : BOOLEAN;
variable c : CHARACTER;
constant ne : INTEGER := (VALUE'length+2)/3;
constant pad : INTEGER := ne*3 - VALUE'length;
variable sv : STD_ULOGIC_VECTOR(0 to ne*3 - 1);
variable i : INTEGER;
variable lastu : BOOLEAN := false; -- last character was an "_"
begin
VALUE := (VALUE'range => 'U'); -- initialize to a "U"
Skip_whitespace (L);
if VALUE'length > 0 then
read (l, c, ok);
i := 0;
while i < ne loop
-- Bail out if there was a bad read
if not ok then
good := false;
return;
elsif c = '_' then
if i = 0 then
good := false; -- Begins with an "_"
return;
elsif lastu then
good := false; -- "__" detected
return;
else
lastu := true;
end if;
else
Char2TriBits(c, sv(3*i to 3*i+2), ok, false);
if not ok then
good := false;
return;
end if;
i := i + 1;
lastu := false;
end if;
if i < ne then
read(L, c, ok);
end if;
end loop;
if or_reduce (sv (0 to pad-1)) = '1' then -- %%% replace with "or"
good := false; -- vector was truncated.
else
good := true;
VALUE := sv (pad to sv'high);
end if;
else
good := true; -- read into a null array
end if;
end procedure OREAD;
procedure OREAD (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR) is
variable c : CHARACTER;
variable ok : BOOLEAN;
constant ne : INTEGER := (VALUE'length+2)/3;
constant pad : INTEGER := ne*3 - VALUE'length;
variable sv : STD_ULOGIC_VECTOR(0 to ne*3 - 1);
variable i : INTEGER;
variable lastu : BOOLEAN := false; -- last character was an "_"
begin
VALUE := (VALUE'range => 'U'); -- initialize to a "U"
Skip_whitespace (L);
if VALUE'length > 0 then
read (l, c, ok);
i := 0;
while i < ne loop
-- Bail out if there was a bad read
if not ok then
report "STD_LOGIC_1164.OREAD "
& "End of string encountered"
severity error;
return;
elsif c = '_' then
if i = 0 then
report "STD_LOGIC_1164.OREAD "
& "String begins with an ""_""" severity error;
return;
elsif lastu then
report "STD_LOGIC_1164.OREAD "
& "Two underscores detected in input string ""__"""
severity error;
return;
else
lastu := true;
end if;
else
Char2TriBits(c, sv(3*i to 3*i+2), ok, true);
if not ok then
return;
end if;
i := i + 1;
lastu := false;
end if;
if i < ne then
read(L, c, ok);
end if;
end loop;
if or_reduce (sv (0 to pad-1)) = '1' then -- %%% replace with "or"
report "STD_LOGIC_1164.OREAD Vector truncated"
severity error;
else
VALUE := sv (pad to sv'high);
end if;
end if;
end procedure OREAD;
procedure OWRITE (L : inout LINE; VALUE : in STD_ULOGIC_VECTOR;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is
begin
write (L, to_ostring(VALUE), JUSTIFIED, FIELD);
end procedure OWRITE;
-- Hex Read and Write procedures for STD_LOGIC_VECTOR
-- procedure HREAD (L : inout LINE; VALUE : out STD_LOGIC_VECTOR;
-- GOOD : out BOOLEAN) is
-- variable ivalue : STD_ULOGIC_VECTOR (VALUE'range);
-- begin
-- HREAD (L => L, VALUE => ivalue, GOOD => GOOD);
-- VALUE := to_stdlogicvector (ivalue);
-- end procedure HREAD;
-- procedure HREAD (L : inout LINE; VALUE : out STD_LOGIC_VECTOR) is
-- variable ivalue : STD_ULOGIC_VECTOR (VALUE'range);
-- begin
-- HREAD (L => L, VALUE => ivalue);
-- VALUE := to_stdlogicvector (ivalue);
-- end procedure HREAD;
procedure HWRITE (L : inout LINE; VALUE : in STD_LOGIC_VECTOR;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is
begin
write (L, to_hstring(VALUE), JUSTIFIED, FIELD);
end procedure HWRITE;
-- Octal Read and Write procedures for STD_LOGIC_VECTOR
procedure OREAD (L : inout LINE; VALUE : out STD_LOGIC_VECTOR;
GOOD : out BOOLEAN) is
variable ivalue : STD_ULOGIC_VECTOR (VALUE'range);
begin
OREAD (L => L, VALUE => ivalue, GOOD => GOOD);
VALUE := to_stdlogicvector (ivalue);
end procedure OREAD;
procedure OREAD (L : inout LINE; VALUE : out STD_LOGIC_VECTOR) is
variable ivalue : STD_ULOGIC_VECTOR (VALUE'range);
begin
OREAD (L => L, VALUE => ivalue);
VALUE := to_stdlogicvector (ivalue);
end procedure OREAD;
procedure OWRITE (L : inout LINE; VALUE : in STD_LOGIC_VECTOR;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is
begin
write (L, to_ostring(VALUE), JUSTIFIED, FIELD);
end procedure OWRITE;
-----------------------------------------------------------------------------
-- New string functions for vhdl-200x fast track
-----------------------------------------------------------------------------
function to_string (value : STD_ULOGIC) return STRING is
variable result : STRING (1 to 1);
begin
result (1) := MVL9_to_char (value);
return result;
end function to_string;
-------------------------------------------------------------------
-- TO_STRING (an alias called "to_bstring" is provide)
-------------------------------------------------------------------
function to_string (value : STD_ULOGIC_VECTOR) return STRING is
alias ivalue : STD_ULOGIC_VECTOR(1 to value'length) is value;
variable result : STRING(1 to value'length);
begin
if value'length < 1 then
return NUS;
else
for i in ivalue'range loop
result(i) := MVL9_to_char(iValue(i));
end loop;
return result;
end if;
end function to_string;
-------------------------------------------------------------------
-- TO_HSTRING
-------------------------------------------------------------------
function to_hstring (value : STD_ULOGIC_VECTOR) return STRING is
constant ne : INTEGER := (value'length+3)/4;
variable pad : STD_ULOGIC_VECTOR(0 to (ne*4 - value'length) - 1);
variable ivalue : STD_ULOGIC_VECTOR(0 to ne*4 - 1);
variable result : STRING(1 to ne);
variable quad : STD_ULOGIC_VECTOR(0 to 3);
begin
if value'length < 1 then
return NUS;
else
if value (value'left) = 'Z' then
pad := (others => 'Z');
else
pad := (others => '0');
end if;
ivalue := pad & value;
for i in 0 to ne-1 loop
quad := To_X01Z(ivalue(4*i to 4*i+3));
case quad is
when x"0" => result(i+1) := '0';
when x"1" => result(i+1) := '1';
when x"2" => result(i+1) := '2';
when x"3" => result(i+1) := '3';
when x"4" => result(i+1) := '4';
when x"5" => result(i+1) := '5';
when x"6" => result(i+1) := '6';
when x"7" => result(i+1) := '7';
when x"8" => result(i+1) := '8';
when x"9" => result(i+1) := '9';
when x"A" => result(i+1) := 'A';
when x"B" => result(i+1) := 'B';
when x"C" => result(i+1) := 'C';
when x"D" => result(i+1) := 'D';
when x"E" => result(i+1) := 'E';
when x"F" => result(i+1) := 'F';
when "ZZZZ" => result(i+1) := 'Z';
when others => result(i+1) := 'X';
end case;
end loop;
return result;
end if;
end function to_hstring;
-------------------------------------------------------------------
-- TO_OSTRING
-------------------------------------------------------------------
function to_ostring (value : STD_ULOGIC_VECTOR) return STRING is
constant ne : INTEGER := (value'length+2)/3;
variable pad : STD_ULOGIC_VECTOR(0 to (ne*3 - value'length) - 1);
variable ivalue : STD_ULOGIC_VECTOR(0 to ne*3 - 1);
variable result : STRING(1 to ne);
variable tri : STD_ULOGIC_VECTOR(0 to 2);
begin
if value'length < 1 then
return NUS;
else
if value (value'left) = 'Z' then
pad := (others => 'Z');
else
pad := (others => '0');
end if;
ivalue := pad & value;
for i in 0 to ne-1 loop
tri := To_X01Z(ivalue(3*i to 3*i+2));
case tri is
when o"0" => result(i+1) := '0';
when o"1" => result(i+1) := '1';
when o"2" => result(i+1) := '2';
when o"3" => result(i+1) := '3';
when o"4" => result(i+1) := '4';
when o"5" => result(i+1) := '5';
when o"6" => result(i+1) := '6';
when o"7" => result(i+1) := '7';
when "ZZZ" => result(i+1) := 'Z';
when others => result(i+1) := 'X';
end case;
end loop;
return result;
end if;
end function to_ostring;
function to_string (value : STD_LOGIC_VECTOR) return STRING is
begin
return to_string (to_stdulogicvector (value));
end function to_string;
function to_hstring (value : STD_LOGIC_VECTOR) return STRING is
begin
return to_hstring (to_stdulogicvector (value));
end function to_hstring;
function to_ostring (value : STD_LOGIC_VECTOR) return STRING is
begin
return to_ostring (to_stdulogicvector (value));
end function to_ostring;
-- rtl_synthesis on
function maximum (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
begin -- function maximum
if L > R then return L;
else return R;
end if;
end function maximum;
-- std_logic_vector output
function minimum (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
begin -- function minimum
if L > R then return R;
else return L;
end if;
end function minimum;
function maximum (L, R : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
begin -- function maximum
if L > R then return L;
else return R;
end if;
end function maximum;
-- std_logic_vector output
function minimum (L, R : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
begin -- function minimum
if L > R then return R;
else return L;
end if;
end function minimum;
function maximum (L, R : STD_ULOGIC) return STD_ULOGIC is
begin -- function maximum
if L > R then return L;
else return R;
end if;
end function maximum;
-- std_logic_vector output
function minimum (L, R : STD_ULOGIC) return STD_ULOGIC is
begin -- function minimum
if L > R then return R;
else return L;
end if;
end function minimum;
end package body std_logic_1164_additions; | gpl-3.0 |
michaelfivez/ascon_hardware_implementation | ascon128128_serialized/API_plus_CipherCore/fifo.vhd | 9 | 4405 | -------------------------------------------------------------------------------
--! @file fifo.vhd
--! @brief standard FIFO
--! @project CAESAR Candidate Evaluation
--! @author Ekawat (ice) Homsirikamol
--! @copyright Copyright (c) 2015 Cryptographic Engineering Research Group
--! ECE Department, George Mason University Fairfax, VA, U.S.A.
--! All rights Reserved.
--! @license This project is released under the GNU Public License.
--! The license and distribution terms for this file may be
--! found in the file LICENSE in this distribution or at
--! http://www.gnu.org/licenses/gpl-3.0.txt
--! @note This is publicly available encryption source code that falls
--! under the License Exception TSU (Technology and software-
--! —unrestricted)
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity fifo is
generic (
G_LOG2DEPTH : integer := 9; --! LOG(2) of depth
G_W : integer := 64 --! Width of I/O (bits)
);
port (
clk : in std_logic;
rst : in std_logic;
write : in std_logic;
read : in std_logic;
din : in std_logic_vector(G_W-1 downto 0);
dout : out std_logic_vector(G_W-1 downto 0);
almost_full : out std_logic;
almost_empty : out std_logic;
full : out std_logic;
empty : out std_logic
);
end fifo;
architecture structure of fifo is
signal readpointer : std_logic_vector(G_LOG2DEPTH -1 downto 0);
signal writepointer : std_logic_vector(G_LOG2DEPTH -1 downto 0);
signal bytecounter : std_logic_vector(G_LOG2DEPTH downto 0);
signal write_s : std_logic;
signal full_s : std_logic;
signal empty_s : std_logic;
type mem is array (2**G_LOG2DEPTH-1 downto 0) of std_logic_vector(G_W-1 downto 0);
signal memory : mem;
begin
p_fifo_ram:
process(clk)
begin
if ( rising_edge(clk) ) then
if (write_s = '1') then
memory(to_integer(unsigned(writepointer))) <= din;
end if;
if (read = '1') then
dout <= memory(to_integer(unsigned(readpointer)));
end if;
end if;
end process;
p_fifo_ptr:
process(clk)
begin
if rising_edge( clk ) then
if rst = '1' then
readpointer <= (others => '0');
writepointer <= (others => '0');
bytecounter <= (others => '0'); --differences (write pointer - read pointer)
else
if ( write = '1' and full_s = '0' and read = '0') then
writepointer <= writepointer + 1;
bytecounter <= bytecounter + 1;
elsif ( read = '1' and empty_s = '0' and write = '0') then
readpointer <= readpointer + 1;
bytecounter <= bytecounter - 1;
elsif ( read = '1' and empty_s = '0' and write = '1' and full_s = '0') then
readpointer <= readpointer + 1;
writepointer <= writepointer + 1;
elsif ( read = '1' and empty_s = '0' and write = '1' and full_s = '1') then -- cant write
readpointer <= readpointer + 1;
bytecounter <= bytecounter - 1;
elsif ( read = '1' and empty_s = '1' and write = '1' and full_s = '0') then -- cant read
writepointer <= writepointer + 1;
bytecounter <= bytecounter + 1;
end if;
end if;
end if;
end process;
empty_s <= '1' when (bytecounter = 0) else '0';
full_s <= bytecounter(G_LOG2DEPTH);
almost_full <= '1' when (bytecounter >= 2**G_LOG2DEPTH-1) else '0';
full <= full_s;
empty <= empty_s;
almost_empty <= '1' when (bytecounter = 1) else '0';
write_s <= '1' when ( write = '1' and full_s = '0') else '0';
end structure;
| gpl-3.0 |
michaelfivez/ascon_hardware_implementation | ascon12864_unrolled2/API_plus_CipherCore/fifo.vhd | 9 | 4405 | -------------------------------------------------------------------------------
--! @file fifo.vhd
--! @brief standard FIFO
--! @project CAESAR Candidate Evaluation
--! @author Ekawat (ice) Homsirikamol
--! @copyright Copyright (c) 2015 Cryptographic Engineering Research Group
--! ECE Department, George Mason University Fairfax, VA, U.S.A.
--! All rights Reserved.
--! @license This project is released under the GNU Public License.
--! The license and distribution terms for this file may be
--! found in the file LICENSE in this distribution or at
--! http://www.gnu.org/licenses/gpl-3.0.txt
--! @note This is publicly available encryption source code that falls
--! under the License Exception TSU (Technology and software-
--! —unrestricted)
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity fifo is
generic (
G_LOG2DEPTH : integer := 9; --! LOG(2) of depth
G_W : integer := 64 --! Width of I/O (bits)
);
port (
clk : in std_logic;
rst : in std_logic;
write : in std_logic;
read : in std_logic;
din : in std_logic_vector(G_W-1 downto 0);
dout : out std_logic_vector(G_W-1 downto 0);
almost_full : out std_logic;
almost_empty : out std_logic;
full : out std_logic;
empty : out std_logic
);
end fifo;
architecture structure of fifo is
signal readpointer : std_logic_vector(G_LOG2DEPTH -1 downto 0);
signal writepointer : std_logic_vector(G_LOG2DEPTH -1 downto 0);
signal bytecounter : std_logic_vector(G_LOG2DEPTH downto 0);
signal write_s : std_logic;
signal full_s : std_logic;
signal empty_s : std_logic;
type mem is array (2**G_LOG2DEPTH-1 downto 0) of std_logic_vector(G_W-1 downto 0);
signal memory : mem;
begin
p_fifo_ram:
process(clk)
begin
if ( rising_edge(clk) ) then
if (write_s = '1') then
memory(to_integer(unsigned(writepointer))) <= din;
end if;
if (read = '1') then
dout <= memory(to_integer(unsigned(readpointer)));
end if;
end if;
end process;
p_fifo_ptr:
process(clk)
begin
if rising_edge( clk ) then
if rst = '1' then
readpointer <= (others => '0');
writepointer <= (others => '0');
bytecounter <= (others => '0'); --differences (write pointer - read pointer)
else
if ( write = '1' and full_s = '0' and read = '0') then
writepointer <= writepointer + 1;
bytecounter <= bytecounter + 1;
elsif ( read = '1' and empty_s = '0' and write = '0') then
readpointer <= readpointer + 1;
bytecounter <= bytecounter - 1;
elsif ( read = '1' and empty_s = '0' and write = '1' and full_s = '0') then
readpointer <= readpointer + 1;
writepointer <= writepointer + 1;
elsif ( read = '1' and empty_s = '0' and write = '1' and full_s = '1') then -- cant write
readpointer <= readpointer + 1;
bytecounter <= bytecounter - 1;
elsif ( read = '1' and empty_s = '1' and write = '1' and full_s = '0') then -- cant read
writepointer <= writepointer + 1;
bytecounter <= bytecounter + 1;
end if;
end if;
end if;
end process;
empty_s <= '1' when (bytecounter = 0) else '0';
full_s <= bytecounter(G_LOG2DEPTH);
almost_full <= '1' when (bytecounter >= 2**G_LOG2DEPTH-1) else '0';
full <= full_s;
empty <= empty_s;
almost_empty <= '1' when (bytecounter = 1) else '0';
write_s <= '1' when ( write = '1' and full_s = '0') else '0';
end structure;
| gpl-3.0 |
michaelfivez/ascon_hardware_implementation | ascon12864_unrolled6/Kernel/DiffusionLayer.vhd | 1 | 1687 | -------------------------------------------------------------------------------
--! @project Unrolled (6) hardware implementation of Asconv1286
--! @author Michael Fivez
--! @license This project is released under the GNU Public License.
--! The license and distribution terms for this file may be
--! found in the file LICENSE in this distribution or at
--! http://www.gnu.org/licenses/gpl-3.0.txt
--! @note This is an hardware implementation made for my graduation thesis
--! at the KULeuven, in the COSIC department (year 2015-2016)
--! The thesis is titled 'Energy efficient hardware implementations of CAESAR submissions',
--! and can be found on the COSIC website (www.esat.kuleuven.be/cosic/publications)
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity DiffusionLayer is
generic( SHIFT1 : integer range 0 to 63;
SHIFT2 : integer range 0 to 63);
port( Input : in std_logic_vector(63 downto 0);
Output : out std_logic_vector(63 downto 0));
end entity DiffusionLayer;
architecture structural of DiffusionLayer is
begin
DiffLayer: process(Input) is
variable Temp0,Temp1 : std_logic_vector(63 downto 0);
begin
Temp0(63 downto 64-SHIFT1) := Input(SHIFT1-1 downto 0);
Temp0(63-SHIFT1 downto 0) := Input(63 downto SHIFT1);
Temp1(63 downto 64-SHIFT2) := Input(SHIFT2-1 downto 0);
Temp1(63-SHIFT2 downto 0) := Input(63 downto SHIFT2);
Output <= Temp0 xor Temp1 xor Input;
end process DiffLayer;
end architecture structural;
| gpl-3.0 |
mgiacomini/mips-monocycle | PC.vhd | 2 | 1499 | -- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- Complete implementation of Patterson and Hennessy single cycle MIPS processor
-- Copyright (C) 2015 Darci Luiz Tomasi Junior
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, version 3.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- Engineer: Darci Luiz Tomasi Junior
-- E-mail: [email protected]
-- Date : 01/07/2015 - 19:53
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
ENTITY PC IS
PORT(
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
IN_A : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
OUT_A : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END PC;
ARCHITECTURE ARC_PC OF PC IS
BEGIN
PROCESS(CLK, RESET)
BEGIN
IF RESET = '1' THEN
OUT_A <= X"00400000"; --Para utilizar com o MARS
ELSIF CLK'EVENT AND CLK = '1' THEN
OUT_A <= IN_A;
END IF;
END PROCESS;
END ARC_PC;
| gpl-3.0 |
michaelfivez/ascon_hardware_implementation | ascon12864_unrolled6/Kernel/Ascon_block_datapath.vhd | 1 | 6151 | -------------------------------------------------------------------------------
--! @project Unrolled (6) hardware implementation of Asconv1286
--! @author Michael Fivez
--! @license This project is released under the GNU Public License.
--! The license and distribution terms for this file may be
--! found in the file LICENSE in this distribution or at
--! http://www.gnu.org/licenses/gpl-3.0.txt
--! @note This is an hardware implementation made for my graduation thesis
--! at the KULeuven, in the COSIC department (year 2015-2016)
--! The thesis is titled 'Energy efficient hardware implementations of CAESAR submissions',
--! and can be found on the COSIC website (www.esat.kuleuven.be/cosic/publications)
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity Ascon_StateUpdate_datapath is
port(
Clk : in std_logic; -- Clock
Reset : in std_logic; -- Reset (synchronous)
-- Control signals
RoundNr : in std_logic; -- biggest round is 12
sel1,sel2,sel3,sel4 : in std_logic_vector(1 downto 0);
sel0 : in std_logic_vector(2 downto 0);
selout : in std_logic;
Reg0En,Reg1En,Reg2En,Reg3En,Reg4En,RegOutEn : in std_logic;
ActivateGen : in std_logic;
GenSize : in std_logic_vector(2 downto 0);
-- Data signals
IV : in std_logic_vector(127 downto 0);
Key : in std_logic_vector(127 downto 0);
DataIn : in std_logic_vector(63 downto 0);
DataOut : out std_logic_vector(127 downto 0)
);
end entity Ascon_StateUpdate_datapath;
architecture structural of Ascon_StateUpdate_datapath is
-- constants
constant EXTRAIV : std_logic_vector(63 downto 0) := x"80400c0600000000"; -- used in the initialization
constant SEPCONSTANT : std_logic_vector(63 downto 0) := x"0000000000000001";
constant ADCONSTANT : std_logic_vector(63 downto 0) := x"8000000000000000";
-- Register signals
signal Reg0In,Reg1In,Reg2In,Reg3In,Reg4In : std_logic_vector(63 downto 0);
signal Reg0Out,Reg1Out,Reg2Out,Reg3Out,Reg4Out : std_logic_vector(63 downto 0);
signal RegOutIn,RegOutOut : std_logic_vector(127 downto 0);
-- Internal signals on datapath
signal DiffOut0,DiffOut1,DiffOut2,DiffOut3,DiffOut4 : std_logic_vector(63 downto 0);
signal XorReg01,XorReg02,XorReg12,XorReg13,XorReg22 : std_logic_vector(63 downto 0);
signal XorReg2,XorReg31,XorReg4 : std_logic_vector(63 downto 0);
signal OutSig0: std_logic_vector(63 downto 0);
signal OutSig1: std_logic_vector(127 downto 0);
begin
-- declare and connect all sub entities
rounds: entity work.Fullrounds port map(Reg0Out,Reg1Out,Reg2Out,Reg3Out,Reg4Out,RoundNr,DiffOut0,DiffOut1,DiffOut2,DiffOut3,DiffOut4);
outpgen: entity work.OutputGenerator port map(Reg0Out,DataIn,GenSize,ActivateGen,XorReg01,OutSig0); -- ActivateGen is a bit that indicates decryption or not
---------------------------------------------
------ Combinatorial logic for a round ------
---------------------------------------------
datapath: process(IV,Key,DataIn,Reg0Out,Reg1Out,Reg2Out,Reg3Out,Reg4Out,RegOutOut, -- inputs blocks and registers
DiffOut0,DiffOut1,DiffOut2,DiffOut3,DiffOut4, -- internal signals
XorReg01,XorReg02,XorReg12,XorReg13,XorReg22,XorReg2,XorReg31,XorReg4,OutSig0,OutSig1, -- internal signals
RoundNr,sel0,sel1,sel2,sel3,sel4,ActivateGen,selout,GenSize) is -- control signals
begin
-- Set correct inputs in registers
if sel0 = "000" then
Reg0In <= DiffOut0;
elsif sel0 = "001" then
Reg0In <= EXTRAIV;
elsif sel0 = "010" then
Reg0In <= XorReg01;
elsif sel0 = "011" then
Reg0In <= XorReg02;
else
Reg0In <= Reg0Out xor ADCONSTANT;
end if;
if sel1 = "00" then
Reg1In <= DiffOut1;
elsif sel1 = "01" then
Reg1In <= Key(127 downto 64);
elsif sel1 = "10" then
Reg1In <= XorReg13;
else
Reg1In <= XorReg12;
end if;
if sel2 = "00" then
Reg2In <= DiffOut2;
elsif sel2 = "01" then
Reg2In <= Key(63 downto 0);
elsif sel2 = "10" then
Reg2In <= XorReg2;
else
Reg2In <= XorReg22;
end if;
if sel3 = "00" then
Reg3In <= DiffOut3;
elsif sel3 = "01" then
Reg3In <= IV(127 downto 64);
else
Reg3In <= XorReg31;
end if;
if sel4 = "00" then
Reg4In <= DiffOut4;
elsif sel4 = "01" then
Reg4In <= IV(63 downto 0);
elsif sel4 = "10" then
Reg4In <= XorReg4;
else
Reg4In <= Reg4Out xor SEPCONSTANT;
end if;
XorReg02 <= Reg0Out xor Key(127 downto 64);
XorReg12 <= Reg1Out xor Key(63 downto 0);
XorReg13 <= Reg1Out xor Key(127 downto 64);
XorReg22 <= Reg2Out xor Key(63 downto 0);
XorReg31 <= Reg3Out xor Key(127 downto 64);
XorReg4 <= Reg4Out xor Key(63 downto 0);
-- Set output
OutSig1(127 downto 64) <= XorReg31;
OutSig1(63 downto 0) <= XorReg4;
if selout = '0' then
RegOutIn(127 downto 64) <= (others => '0');
RegOutIn(63 downto 0) <= OutSig0;
else
RegOutIn <= OutSig1;
end if;
DataOut <= RegOutOut;
end process datapath;
---------------------------------------------
------ The registers in the datapath --------
---------------------------------------------
registerdatapath : process(Clk,Reset) is
begin
if(Clk = '1' and Clk'event) then
if Reset = '1' then -- synchronous reset
Reg0Out <= (others => '0');
Reg1Out <= (others => '0');
Reg2Out <= (others => '0');
Reg3Out <= (others => '0');
Reg4Out <= (others => '0');
RegOutOut <= (others => '0');
else
-- update registers with enable
if Reg0En = '1' then
Reg0Out <= Reg0In;
end if;
if Reg1En = '1' then
Reg1Out <= Reg1In;
end if;
if Reg2En = '1' then
Reg2Out <= Reg2In;
end if;
if Reg3En = '1' then
Reg3Out <= Reg3In;
end if;
if Reg4En = '1' then
Reg4Out <= Reg4In;
end if;
if RegOutEn = '1' then
RegOutOut <= RegOutIn;
end if;
end if;
end if;
end process registerdatapath;
end architecture structural;
| gpl-3.0 |
michaelfivez/ascon_hardware_implementation | ascon12864_unrolled3/API_plus_CipherCore/PreProcessor_Control.vhd | 9 | 77328 | -------------------------------------------------------------------------------
--! @file PreProcessor_Control.vhd
--! @brief Control unit for the pre-processor
--! @project CAESAR Candidate Evaluation
--! @author Ekawat (ice) Homsirikamol
--! @copyright Copyright (c) 2015 Cryptographic Engineering Research Group
--! ECE Department, George Mason University Fairfax, VA, U.S.A.
--! All rights Reserved.
--! @license This project is released under the GNU Public License.
--! The license and distribution terms for this file may be
--! found in the file LICENSE in this distribution or at
--! http://www.gnu.org/licenses/gpl-3.0.txt
--! @note This is publicly available encryption source code that falls
--! under the License Exception TSU (Technology and software-
--! —unrestricted)
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use work.AEAD_pkg.all;
entity PreProcessor_Control is
generic (
G_W : integer := 32; --! Public data width (bits)
G_SW : integer := 32; --! Secret data width (bits)
G_CIPHERTEXT_MODE : integer := 0; --! Ciphertext mode
G_PLAINTEXT_MODE : integer := 0; --! Plaintext Mode
G_ABLK_SIZE : integer := 128; --! Authenticated Data Block size (bits)
G_DBLK_SIZE : integer := 128; --! Data Block size (bits)
G_BS_BYTES : integer := 4; --! The number of bits required to hold block size expressed in bytes = log2_ceil(block_size/8)
G_KEY_SIZE : integer := 128; --! Key size (bits)
G_NPUB_DISABLE : integer := 0; --! Disable Npub related port(s)
G_NPUB_SIZE : integer := 128; --! Npub width (bits)
G_NSEC_ENABLE : integer := 0; --! Enable NSEC port
G_NSEC_SIZE : integer := 128; --! NSEC width (bits)
G_RDKEY_ENABLE : integer := 0; --! Enable rdkey port (also disables key port)
G_RDKEY_SIZE : integer := 128; --! Roundkey size (bits)
G_REVERSE_DBLK : integer := 0; --! Reverse block order (for message only)
G_LOADLEN_ENABLE : integer := 0; --! Enable load length section
G_CTR_AD_SIZE : integer := 16; --! Segment len size
G_CTR_D_SIZE : integer := 16; --! Segment len size
G_PAD : integer := 1; --! Enable padding
G_PAD_AD : integer := 1; --! (G_PAD's sub option) Enable AD Padding
G_PAD_D : integer := 1; --! (G_PAD's sub option) Enable Data padding
G_TAG_SIZE : integer := 128; --! Tag size (bits)
G_KEYAK : integer := 0 --! Special Keyak only mode
);
port (
--! =================
--! External Signals
--! =================
--! Global signals
clk : in std_logic;
rst : in std_logic;
--! Public signals
pdi : in std_logic_vector(G_W -1 downto 0);
pdi_valid : in std_logic;
pdi_ready : out std_logic;
--! Secret signals
sdi : in std_logic_vector(G_SW -1 downto 0);
sdi_valid : in std_logic;
sdi_ready : out std_logic;
error : out std_logic;
--! =================
--! Crypto Core Signals
--! =================
--! control signals
key_ready : out std_logic; --! Indicates that the key is ready
key_needs_update : out std_logic; --! Indicates that the key needs update and should be acknowledge by the core via key_updated signal
key_updated : in std_logic; --! Key has been updated
rdkey_ready : out std_logic; --! Round key ready
rdkey_read : in std_logic; --! Round key read
npub_ready : out std_logic; --! Npub ready
npub_read : in std_logic; --! Npub read
nsec_ready : out std_logic; --! Nsec ready
nsec_read : in std_logic; --! Nsec read
bdi_ready : out std_logic; --! Block ready
bdi_proc : out std_logic; --! Block processing
bdi_ad : out std_logic; --! Input block is an authenticated data
bdi_nsec : out std_logic; --! Input block is a secret message number
bdi_decrypt : out std_logic; --! Decryption operation
bdi_pad : out std_logic; --! Last block of segment type contain padding
bdi_eot : out std_logic; --! Last block of segment type (end-of-type)
bdi_eoi : out std_logic; --! Last block of message (end-of-input)
bdi_nodata : out std_logic; --! Control signal indicating that there's no plain-text or authenticated data. The unit should generate a tag right away.
bdi_read : in std_logic; --! Handshake signal indicating that the data block has been read
bdi_size : out std_logic_vector(G_BS_BYTES -1 downto 0); --! Block size signal. Note: 0 = Full block.
exp_tag_ready : out std_logic; --! Expected tag is ready
msg_auth_done : in std_logic; --! Tag comparison completion handshake
bypass_fifo_full : in std_logic; --! An input signal indicating that the bypass FIFO is full
bypass_fifo_wr : out std_logic; --! An output signal for writing data to bypass FIFO
--! =================
--! Internal Signals
--! =================
pad_shift : out std_logic_vector(log2_ceil(G_W/8) -1 downto 0);
en_data : out std_logic; --! Shift data SIPO
en_npub : out std_logic; --! Shift Npub SIPO
en_nsec : out std_logic; --! Shift Nsec SIPO
en_key : out std_logic; --! Shift Key SIPO
en_rdkey : out std_logic; --! Shift Round Key SIPO
sel_blank_pdi : out std_logic; --! Select input data as blank (for filling in the remaining data within a block)
clr_len : out std_logic; --! Clear stored length (len_a and len_d)
en_len_a_r : out std_logic; --! Add authenticated data counter
en_len_d_r : out std_logic; --! Add data counter
en_len_last_r : out std_logic; --! Special signal for en_len_*_r
en_len_a : out std_logic; --! Add authenticated data counter (instant)
en_len_d : out std_logic; --! Add data counter (instant)
en_exp_tag : out std_logic; --! Shift TAG SIPO
size_dword : out std_logic_vector(log2_ceil(G_W/8) downto 0); --! Size of data word
en_last_word : out std_logic; --! Last word of a block
--! Pad related control
pad_eot : out std_logic; --! Padding is EOT
pad_eoi : out std_logic; --! Padding is EOI
pad_type_ad : out std_logic; --! Padding is AD
pad_enable : out std_logic; --! Enable padding signal (indicates that the current word requires padding)
en_pad_loc : out std_logic; --! Save the padding location into a register
--! Supplemental control
key_updated_int : out std_logic; --! Only used for Keyak
sel_input : out std_logic_vector(2 downto 0) --! Sel input (used when (G_DBLK_SIZE mod G_W) > 0)
);
end PreProcessor_Control;
architecture behavior of PreProcessor_Control is
function getSwCount return integer is
variable maxval : integer := 0;
begin
if (G_NSEC_ENABLE = 1) then
maxval := G_NSEC_SIZE;
end if;
if (G_RDKEY_ENABLE = 1) then
maxval := maximum(maxval, G_RDKEY_SIZE);
else
maxval := maximum(maxval, G_KEY_SIZE);
end if;
return log2_ceil(maxval/G_SW);
end function;
--! Constants declaration
constant PARTIAL_LOAD : integer := isNotDivisible(G_DBLK_SIZE, G_W);
constant LOG2_W : integer := log2_ceil(G_W/8); --! LOG_2(G_W)
constant LOG2_SWORDS : integer := getSwCount; --! Expected key words
constant REGIV_WIDTH : integer := get_width(G_NPUB_SIZE, G_W); --! Calculate the width of Npub register
constant CNTR_WIDTH : integer := get_cntr_width(G_W); --! Calculate the length of p_size register
constant CNT_NPUB_WORDS : integer := get_words(G_NPUB_SIZE, G_W); --! Calculate the number of words required for Npub
constant CNT_AD_WORDS : integer := (G_ABLK_SIZE+(G_W-1))/G_W; --! Calculate the number of words required for data (rounded up)
constant CNT_DATA_WORDS : integer := (G_DBLK_SIZE+(G_W-1))/G_W; --! Calculate the number of words required for data (rounded up)
constant CNT_TAG_WORDS : integer := (G_TAG_SIZE+(G_W-1))/G_W; --! Calculate the number of words required for tag (rounded up)
constant CNT_LOADLEN_A_WORDS : integer := get_words(G_CTR_AD_SIZE, G_W);
constant CNT_LOADLEN_D_WORDS : integer := get_words(G_CTR_D_SIZE, G_W);
constant BSHIFT_INPUT : std_logic_vector(G_W/8 -1 downto 0) := std_logic_vector(to_unsigned(1,G_W/8));
constant WCOUNT_SIZE : integer := log2_ceil(maximum(maximum(CNT_NPUB_WORDS, CNT_DATA_WORDS), CNT_TAG_WORDS)+1);
constant ZEROS : std_logic_vector(G_DBLK_SIZE-1 downto 0) := (OTHERS => '0');
constant SWSIZE : integer := log2_ceil(G_SW/8);
constant SWREMSIZE : integer := (G_SW-16)-SWSIZE;
--! Types declaration
type pstate_type is (SP_WAIT_INSTR, SP_READ_INSTR,
SP_WAIT_HDR, SP_READ_HDR, SP_WAIT_NPUB, SP_WAIT_NSEC,
SP_INIT_KEYAK0, SP_INIT_KEYAK1, SP_INIT_KEYAK2, --! Special state for Keyak
SP_LOAD_SPECIAL_AD, SP_WAIT_SPECIAL_AD_READ, --! Special state for G_PAD_AD > 1
SP_LOADLEN, --! Special LOADLEN state
SP_WAIT_DATA, SP_WAIT_DATA_READ, SP_WAIT_MSG_AUTH,
SP_ERROR);
type sstate_type is (SS_WAIT_INSTR, SS_READ_INSTR,
SS_WAIT_HDR, SS_READ_HDR,
SS_WAIT_KEY, SS_DELAY,
SS_WAIT_RDKEY, SS_WAIT_RDKEY_READ);
--! State signals
signal pstate : pstate_type;
signal sstate : sstate_type;
--! Status controls
signal set_npub_ready : std_logic;
signal set_nsec_ready : std_logic;
signal clr_nsec_ready : std_logic;
signal set_rdkey_ready : std_logic;
--! SDI related signals
signal set_key_needs_update : std_logic;
signal set_key_ready : std_logic;
signal key_ready_r : std_logic;
signal key_needs_update_r : std_logic;
signal nsec_ready_r : std_logic;
signal rdkey_ready_r : std_logic;
signal key_id_r : std_logic_vector(8 -1 downto 0); --! Key id of the key_ready signal
signal key_act_id_init_r : std_logic; --! Status signal for key_act_id (used only after reset)
signal key_act_id_r : std_logic_vector(8 -1 downto 0); --! Activated key_id
signal s_opcode : std_logic_vector(LEN_OPCODE -1 downto 0); --! Secret data opcode
signal s_stype : std_logic_vector(LEN_SMT_HDR -1 downto 0); --! Secret data segment type
signal s_size : std_logic_vector(G_SW-16 -1 downto 0); --! Secret data segment size
signal swcount : std_logic_vector(LOG2_SWORDS -1 downto 0); --! Secret data words count
signal swrem : std_logic_vector(SWREMSIZE -1 downto 0); --! Secret data byte remainder
signal s_key_id : std_logic_vector(8 -1 downto 0); --! Secret data key id
--! Public data signals and registers
signal p_reg_stype : std_logic_vector(LEN_SMT_HDR -1 downto 0); --! Segment type register
signal pwrem : std_logic_vector(CNTR_WIDTH -1 downto 0); --! Private data words remaining
signal wcount : std_logic_vector(WCOUNT_SIZE -1 downto 0); --! Word count
signal p_opcode : std_logic_vector(LEN_OPCODE -1 downto 0); --! Opcode
signal p_stype : std_logic_vector(LEN_SMT_HDR -1 downto 0); --! Segment type
signal p_eot : std_logic; --! Last segment of the specified type flag
signal p_eoi : std_logic; --! Last segment of the message flag
signal p_id : std_logic_vector(LEN_MSG_ID -1 downto 0); --! ID
signal p_size : std_logic_vector(CNTR_WIDTH -1 downto 0); --! Public data segment size
signal p_size_r : std_logic_vector(CNTR_WIDTH -1 downto 0); --! Public data segment size register
signal p_key_id : std_logic_vector(8 -1 downto 0); --! Public data key id
signal remainder : std_logic_vector(CNTR_WIDTH -1 downto 0);
--! Data block status register
signal is_ae_r : std_logic; --! Current block is an authenticated encryption block
--! Data block status registers for external modules
signal npub_ready_r : std_logic;
signal ad_passed_r : std_logic;
signal tag_passed_r : std_logic;
signal is_decrypt_r : std_logic; --! Current message is a decryption
signal is_ad_r : std_logic; --! Current block is an authenticated data block
signal is_tag_r : std_logic; --! Current segment is a tag
signal is_nsec_r : std_logic; --! Current block is a nsec
signal is_ready_r : std_logic; --! Current block is ready
signal is_eot_r : std_logic; --! Current block is the last of its type in the current segment
signal is_eoi_r : std_logic; --! Current block is the last block of message
signal is_nodata_r : std_logic; --! Current block contains no message data (used for authenticated encryption data only mode)
signal is_first_blk : std_logic;
signal is_init_r : std_logic;
--! Padding related signals
signal pad_done : std_logic;
--! Other status registers
signal exp_tag_ready_r : std_logic; --! Needs a delay
signal needs_extra_block : std_logic;
signal needs_extra_block_ad : std_logic;
signal is_extra_block : std_logic;
signal is_partial_data : std_logic;
signal total_words : std_logic_vector(WCOUNT_SIZE -1 downto 0);
--! Error registers
signal errors : std_logic_vector(8 -1 downto 0); --! Error flag (Used for debugging)
signal error_pdi : std_logic_vector(8 downto 1);
signal error_sdi : std_logic_vector(8 downto 1);
begin
--! Datapath
p_reg:
process( clk )
begin
if rising_edge( clk ) then
if rst = '1' then
key_needs_update_r <= '0';
key_ready_r <= '0';
bdi_ready <= '0';
if (G_NPUB_DISABLE = 0) then
npub_ready_r <= '0';
end if;
if (G_NSEC_ENABLE = 1) then
nsec_ready_r <= '0';
end if;
if (G_RDKEY_ENABLE = 1) then
rdkey_ready_r <= '0';
end if;
key_act_id_init_r <= '0';
key_act_id_r <= (others => '0');
else
if (set_key_needs_update = '1') then
key_needs_update_r <= '1';
elsif (key_updated = '1') then
key_needs_update_r <= '0';
end if;
if (G_NSEC_ENABLE = 1) then
if (set_nsec_ready = '1') then
nsec_ready_r <= '1';
elsif (nsec_read = '1') then
nsec_ready_r <= '0';
end if;
end if;
if (G_NPUB_DISABLE = 0) then
if (set_npub_ready = '1') then
npub_ready_r <= '1';
elsif (npub_read = '1') then
npub_ready_r <= '0';
end if;
end if;
if (G_RDKEY_ENABLE = 1) then
if (set_rdkey_ready = '1') then
rdkey_ready_r <= '1';
elsif (rdkey_read = '1') then
rdkey_ready_r <= '0';
if (swrem = 0) then
key_act_id_init_r <= '1';
key_act_id_r <= key_id_r;
end if;
end if;
else
if (set_key_ready = '1') then
key_ready_r <= '1';
elsif (key_updated = '1') then
key_ready_r <= '0';
key_act_id_init_r <= '1';
key_act_id_r <= key_id_r;
end if;
end if;
exp_tag_ready <= exp_tag_ready_r;
bdi_ready <= is_ready_r and not bdi_read;
end if;
end if;
end process;
gRdkeyEnable0: if (G_RDKEY_ENABLE = 0) generate
key_ready <= key_ready_r;
end generate;
gRdkeyEnable1: if (G_RDKEY_ENABLE = 1) generate
rdkey_ready <= rdkey_ready_r;
end generate;
gNsecEnable1: if (G_NSEC_ENABLE = 1) generate
nsec_ready <= nsec_ready_r;
end generate;
key_needs_update <= key_needs_update_r;
s_key_id <= sdi(G_SW -1 downto G_SW- 8);
s_stype <= sdi(G_SW- 8 -1 downto G_SW-12);
s_opcode <= sdi(G_SW-12 -1 downto G_SW-16);
s_size <= sdi(G_SW-16 -1 downto 0);
p_stype <= pdi(G_W - 8 -1 downto G_W -12);
p_opcode <= pdi(G_W -12 -1 downto G_W -16);
p_key_id <= pdi(G_W -16 -1 downto G_W -24);
p_size <= pdi(CNTR_WIDTH -1 downto 0);
bdi_ad <= is_ad_r;
bdi_nsec <= is_nsec_r;
bdi_decrypt <= is_decrypt_r;
bdi_pad <= '0';
bdi_eot <= is_eot_r;
bdi_eoi <= is_eoi_r;
bdi_nodata <= is_nodata_r;
npub_ready <= npub_ready_r;
errors <= error_pdi or error_sdi;
error <= nway_or(errors);
genPad: if (G_PAD = 1) generate
-- genPadShiftReverse00: if (G_REVERSE_DBLK = 0 and G_PAD_AD /= 4) generate
-- en_pad_loc <= '1' when (PARTIAL_LOAD = 0 and pstate = SP_WAIT_DATA and p_eot = '1' and pwrem <= G_W/8 and pad_done = '0') or
-- (PARTIAL_LOAD = 1 and pstate = SP_WAIT_DATA and p_eot = '1' and pwrem <= G_W/8 and pad_done = '0' and wcount /= total_words) or
-- (PARTIAL_LOAD = 1 and pstate = SP_WAIT_DATA and p_eot = '1' and pwrem <= G_W/8 and pad_done = '0' and wcount = total_words and is_partial_data = '0')
-- else '0';
-- end generate;
genPadShiftReverse0: if (G_REVERSE_DBLK = 0) generate
en_pad_loc <= '1' when ((PARTIAL_LOAD = 0 and pstate = SP_WAIT_DATA and p_eot = '1' and pwrem <= G_W/8 and pad_done = '0') or
(PARTIAL_LOAD = 0 and (G_PAD_AD = 2 or G_PAD_AD = 4) and pstate = SP_LOAD_SPECIAL_AD and wcount = 0) or
(PARTIAL_LOAD = 1 and pstate = SP_WAIT_DATA and p_eot = '1' and pwrem <= G_W/8 and pad_done = '0' and wcount /= total_words) or
(PARTIAL_LOAD = 1 and pstate = SP_WAIT_DATA and p_eot = '1' and pwrem <= G_W/8 and pad_done = '0' and wcount = total_words and is_partial_data = '0'))
else '0';
end generate;
genPadShiftReverse1: if (G_REVERSE_DBLK = 1) generate
en_pad_loc <= '1' when ((pstate = SP_WAIT_DATA and p_eot = '1' and pwrem <= G_W/8 and pad_done = '0' and is_ad_r = '1') or
(pstate = SP_WAIT_DATA and is_tag_r = '0' and is_first_blk = '1' and is_ad_r = '0')) else '0';
end generate;
end generate;
genPadShiftX: if (G_PAD = 1 and (G_PAD_D < 2 and G_PAD_AD < 2)) generate
genPadShiftReverse0: if (G_REVERSE_DBLK = 0) generate
pad_shift <= p_size_r(log2_ceil(G_W/8)-1 downto 0);
end generate;
genPadShiftReverse1: if (G_REVERSE_DBLK = 1) generate
pad_shift <= remainder(log2_ceil(G_W/8)-1 downto 0) when (remainder(G_BS_BYTES-1 downto 0) < G_DBLK_SIZE/8) else (others => '0');
end generate;
end generate;
genPadShift2: if (G_PAD = 1 and (G_PAD_D > 1 or G_PAD_AD > 1)) generate
pad_shift <= p_size_r(log2_ceil(G_W/8)-1 downto 0) when is_extra_block = '0' else (others => '0');
end generate;
--! Control for public data
p_pstate:
process( clk )
begin
if rising_edge( clk ) then
if rst = '1' then
pstate <= SP_WAIT_INSTR;
en_data <= '0';
en_npub <= '0';
error_pdi <= (others => '0');
bypass_fifo_wr <= '0';
p_eot <= '0';
p_eoi <= '0';
p_id <= (others => '0');
bdi_proc <= '0';
is_ad_r <= '0';
is_tag_r <= '0';
is_nsec_r <= '0';
is_ae_r <= '0';
is_decrypt_r <= '0';
is_ready_r <= '0';
is_eot_r <= '0';
is_eoi_r <= '0';
is_nodata_r <= '0';
sel_blank_pdi <= '0';
exp_tag_ready_r <= '0';
ad_passed_r <= '0';
if (G_PAD = 1) then
pad_type_ad <= '0';
pad_eot <= '0';
pad_eoi <= '0';
end if;
p_reg_stype <= (others => '0');
set_key_needs_update <= '0';
if (PARTIAL_LOAD = 1) then
is_partial_data <= '0';
en_last_word <= '0';
sel_input <= (others => '0');
end if;
if (G_NSEC_ENABLE = 1) then
set_nsec_ready <= '0';
end if;
if (G_PAD = 1) then
pad_enable <= '0';
end if;
if (G_LOADLEN_ENABLE = 1) then
en_len_a_r <= '0';
en_len_d_r <= '0';
if ((G_CTR_AD_SIZE mod G_W /= 0) or (G_CTR_D_SIZE mod G_W /= 0)) then
en_len_last_r <= '0';
end if;
end if;
else
en_data <= '0';
bypass_fifo_wr <= '0';
clr_len <= '0';
sel_blank_pdi <= '0';
en_exp_tag <= '0';
set_key_needs_update <= '0';
if (G_PAD = 1) then
pad_type_ad <= '0';
pad_eot <= '0';
pad_eoi <= '0';
end if;
if (PARTIAL_LOAD = 1) then
en_last_word <= '0';
sel_input <= (others => '0');
end if;
if (G_NPUB_DISABLE = 0) then
en_npub <= '0';
set_npub_ready <= '0';
end if;
if (G_NSEC_ENABLE = 1) then
en_nsec <= '0';
set_nsec_ready <= '0';
end if;
if (G_PAD = 1) then
pad_enable <= '0';
end if;
if (G_KEYAK = 1) then
key_updated_int <= '0';
end if;
if (G_LOADLEN_ENABLE = 1) then
en_len_a_r <= '0';
en_len_d_r <= '0';
if ((G_CTR_AD_SIZE mod G_W /= 0) or (G_CTR_D_SIZE mod G_W /= 0)) then
en_len_last_r <= '0';
end if;
end if;
case pstate is
when SP_WAIT_INSTR =>
if (pdi_valid = '1' and bypass_fifo_full = '0') then
pstate <= SP_READ_INSTR;
bypass_fifo_wr <= '1';
end if;
pwrem <= (others => '0');
p_size_r <= (others => '0');
p_eot <= '0';
p_eoi <= '0';
p_id <= (others => '0');
wcount <= (others => '0');
is_ad_r <= '0';
is_tag_r <= '0';
is_nsec_r <= '0';
is_ae_r <= '0';
is_decrypt_r <= '0';
is_ready_r <= '0';
clr_len <= '1';
is_nodata_r <= '0';
exp_tag_ready_r <= '0';
bdi_size <= (others => '0');
tag_passed_r <= '0';
if G_REVERSE_DBLK = 1 then
is_first_blk <= '1';
end if;
if (G_KEYAK = 1) then
is_init_r <= '1';
end if;
if (G_PAD = 1) then
if (G_PAD_AD > 1 or G_PAD_D > 1) then
is_extra_block <= '0';
needs_extra_block <= '0';
needs_extra_block_ad <= '0';
end if;
if (G_PAD_AD > 1) then
ad_passed_r <= '0';
end if;
end if;
when SP_READ_INSTR =>
if (p_opcode /= OP_AE_ENC)
and (p_opcode /= OP_AE_DEC)
and (p_opcode /= OP_ACT_KEY)
and (p_opcode /= OP_ENC)
and (p_opcode /= OP_DEC)
then
pstate <= SP_ERROR;
error_pdi(1) <= '1'; --! Unsupported opcode
else
if (p_opcode = OP_AE_DEC) or (p_opcode = OP_DEC) then
is_decrypt_r <= '1';
end if;
if (p_opcode = OP_AE_DEC or p_opcode = OP_AE_ENC) then
is_ae_r <= '1';
end if;
if (p_opcode = OP_ACT_KEY) then
pstate <= SP_WAIT_INSTR;
if (key_act_id_init_r = '0'
or (key_act_id_init_r = '1'
and p_key_id /= key_act_id_r))
then
set_key_needs_update <= '1';
end if;
else
pstate <= SP_WAIT_HDR;
p_reg_stype <= p_stype;
bdi_proc <= '1';
end if;
end if;
when SP_WAIT_HDR =>
if (pdi_valid = '1' and bypass_fifo_full = '0') then
pstate <= SP_READ_HDR;
bypass_fifo_wr <= '1';
end if;
--! Pad
if G_PAD = 1 then
pad_done <= '0';
end if;
when SP_READ_HDR =>
if (not ((G_LOADLEN_ENABLE = 1 and p_stype = ST_LEN)
or (p_stype = ST_NPUB)
or (p_stype = ST_AD)
or (p_stype = ST_MESSAGE and is_decrypt_r = '0')
or (p_stype = ST_CIPHER and is_decrypt_r = '1')
or (p_stype = ST_TAG and is_decrypt_r = '1')))
then
pstate <= SP_ERROR;
error_pdi(7) <= '1'; --! Segment type incompatible with opcode
else
--! Store segment type
if (pdi(G_W-15-1) = '1') then
p_reg_stype <= p_stype;
end if;
--! Determining the type and appropriate sequence of inputs. Uses for debugging as well (not fully implemented).
if (p_stype = ST_NPUB) then
if (p_reg_stype = ST_INIT ) or
(G_LOADLEN_ENABLE = 1 and p_reg_stype = ST_LEN )
then
if ( p_size /= G_NPUB_SIZE/8 ) then
pstate <= SP_ERROR;
error_pdi(4) <= '1'; --! Unsupported Npub Length
else
pstate <= SP_WAIT_NPUB;
end if;
else
pstate <= SP_ERROR;
error_pdi(6) <= '1'; --! Segment out of sequence
end if;
elsif (p_stype = ST_AD) then
if ((G_PLAINTEXT_MODE = 0 and (p_reg_stype = ST_NPUB or p_reg_stype = ST_AD or (G_NSEC_ENABLE = 1 and (p_reg_stype = ST_NSEC or p_reg_stype = ST_NSEC_CIPH))))
or (G_PLAINTEXT_MODE = 1 and (p_reg_stype = ST_INIT or p_reg_stype = ST_AD))
or (G_PLAINTEXT_MODE = 2 and (p_reg_stype = ST_INIT or p_reg_stype = ST_AD))
or (G_PLAINTEXT_MODE = 3 and (p_reg_stype = ST_NPUB or p_reg_stype = ST_AD or p_reg_stype = ST_MESSAGE or p_reg_stype = ST_CIPHER))
or ((G_CIPHERTEXT_MODE = 2 and G_REVERSE_DBLK = 1) and (p_reg_stype = ST_TAG)))
then
if (G_KEYAK = 1 and is_init_r = '1') then
is_init_r <= '0';
pstate <= SP_INIT_KEYAK0;
else
pstate <= SP_WAIT_DATA;
end if;
is_ad_r <= '1';
is_tag_r <= '0';
is_nsec_r <= '0';
else
pstate <= SP_ERROR;
error_pdi(6) <= '1'; --! Segment out of sequence
end if;
if (PARTIAL_LOAD = 1) then
total_words <= std_logic_vector(to_unsigned(CNT_AD_WORDS-1, WCOUNT_SIZE));
is_partial_data <= '0';
end if;
if (G_PAD = 1) then
if (G_PAD_AD > 1) then
ad_passed_r <= '1';
end if;
if ((G_PAD_D = 2 or G_PAD_D = 4) and pdi(G_W-14-1) = '1') then --! EOI
needs_extra_block <= '1';
end if;
if ((G_ABLK_SIZE = G_DBLK_SIZE and (G_PAD_AD > 2) and G_PLAINTEXT_MODE < 3) and --! EOT and Full block
pdi(G_BS_BYTES-1 downto 0) = 0 and pdi(G_W-15-1) = '1')
then
needs_extra_block_ad <= '1';
end if;
end if;
elsif (p_stype = ST_MESSAGE or p_stype = ST_CIPHER) then
if ((G_PLAINTEXT_MODE = 0 and (p_reg_stype = ST_NPUB or p_reg_stype = ST_AD or p_reg_stype = ST_MESSAGE or p_reg_stype = ST_CIPHER or (G_NSEC_ENABLE = 1 and (p_reg_stype = ST_NSEC or p_reg_stype = ST_NSEC_CIPH))))
or (G_PLAINTEXT_MODE = 1)
or (G_PLAINTEXT_MODE = 2)
or (G_PLAINTEXT_MODE = 3 and (p_reg_stype = ST_NPUB or p_reg_stype = ST_AD or p_reg_stype = ST_MESSAGE or p_reg_stype = ST_CIPHER))
or ((G_CIPHERTEXT_MODE = 2 and G_REVERSE_DBLK = 1) and (p_reg_stype = ST_TAG)))
then
if (G_PLAINTEXT_MODE < 3 and G_PAD = 1 and (G_PAD_AD = 2 or G_PAD_AD = 4) and ad_passed_r = '0') then
--! Empty AD
pstate <= SP_LOAD_SPECIAL_AD;
is_ad_r <= '1';
is_extra_block <= '1';
else
pstate <= SP_WAIT_DATA;
is_ad_r <= '0';
end if;
is_tag_r <= '0';
is_nsec_r <= '0';
else
pstate <= SP_ERROR;
error_pdi(6) <= '1'; --! Segment out of sequence
end if;
if (PARTIAL_LOAD = 1) then
total_words <= std_logic_vector(to_unsigned(CNT_DATA_WORDS-1, WCOUNT_SIZE));
is_partial_data <= '0';
end if;
--! Calculate if additional block needs to be added (only for Message type)
if (G_PAD = 1 and G_PAD_D > 2) then
if (pdi(G_BS_BYTES-1 downto 0) = 0 and (G_CIPHERTEXT_MODE < 2 or is_decrypt_r = '0') and pdi(G_W-14-1) = '1') then
needs_extra_block <= '1';
else
needs_extra_block <= '0';
end if;
end if;
elsif (G_NSEC_ENABLE = 1 and (p_stype = ST_NSEC or p_stype = ST_NSEC_CIPH)) then
pstate <= SP_WAIT_NSEC;
elsif (p_stype = ST_TAG) then
tag_passed_r <= '1';
if (is_decrypt_r = '0') then
pstate <= SP_ERROR;
error_pdi(6) <= '1';
else
pstate <= SP_WAIT_DATA;
is_tag_r <= '1';
if (is_ready_r = '0') then
is_ad_r <= '0';
is_nsec_r <= '0';
end if;
end if;
elsif (G_LOADLEN_ENABLE = 1 and p_stype = ST_LEN) then
pstate <= SP_LOADLEN;
else --! Unsupported segment type
pstate <= SP_ERROR;
error_pdi(6) <= '1';
end if;
pwrem <= pdi(CNTR_WIDTH-1 downto 0);
p_size_r <= pdi(CNTR_WIDTH-1 downto 0);
p_eot <= pdi(G_W-15-1);
p_eoi <= pdi(G_W-14-1);
p_id <= pdi(G_W-1 downto G_W-8);
end if;
when SP_LOADLEN =>
if (pdi_valid = '1' and bypass_fifo_full = '0') then
bypass_fifo_wr <= '1';
if (wcount <= CNT_LOADLEN_A_WORDS-1) then
en_len_a_r <= '1';
else
en_len_d_r <= '1';
end if;
if ((G_CTR_AD_SIZE mod G_W /= 0) or (G_CTR_D_SIZE mod G_W /= 0)) then
if (wcount = CNT_LOADLEN_A_WORDS-1) or
(wcount = (CNT_LOADLEN_A_WORDS+CNT_LOADLEN_D_WORDS-1))
then
en_len_last_r <= '1';
end if;
end if;
if (wcount = (CNT_LOADLEN_A_WORDS+CNT_LOADLEN_D_WORDS-1)) then
pstate <= SP_WAIT_HDR;
wcount <= (others => '0');
else
wcount <= wcount + 1;
end if;
end if;
when SP_WAIT_NPUB =>
if (pdi_valid = '1' and bypass_fifo_full = '0'
and (G_NPUB_DISABLE = 1 or npub_ready_r = '0'))
then
if (pwrem <= G_W/8) then
pwrem <= (others => '0');
else
pwrem <= pwrem - G_W/8;
end if;
if (G_NPUB_DISABLE = 1) then
en_data <= '1';
else
en_npub <= '1';
end if;
bypass_fifo_wr <= '1';
if (wcount = CNT_NPUB_WORDS-1) then
pstate <= SP_WAIT_HDR;
wcount <= (others => '0');
if (G_NPUB_DISABLE = 0) then
set_npub_ready <= '1';
end if;
else
wcount <= wcount + 1;
end if;
end if;
when SP_WAIT_NSEC =>
if (pdi_valid = '1' and nsec_ready_r = '0') then
en_nsec <= '1';
if (G_NSEC_SIZE > G_W) then
if (wcount = (G_NSEC_SIZE/G_W)-1) then
pstate <= SP_WAIT_HDR;
set_nsec_ready <= '1';
else
wcount <= wcount + 1;
end if;
else
pstate <= SP_WAIT_HDR;
set_nsec_ready <= '1';
end if;
end if;
when SP_INIT_KEYAK0 =>
if (key_needs_update_r = '1' and key_ready_r = '1') then
key_updated_int <= '1';
pstate <= SP_INIT_KEYAK1;
elsif (key_needs_update_r = '0') then
pstate <= SP_INIT_KEYAK1;
end if;
when SP_INIT_KEYAK1 =>
sel_input <= "100";
en_data <= '1';
wcount <= wcount + 1;
pstate <= SP_INIT_KEYAK2;
when SP_INIT_KEYAK2 =>
sel_input <= "101";
en_data <= '1';
wcount <= wcount + 1;
pstate <= SP_WAIT_DATA;
when SP_LOAD_SPECIAL_AD =>
en_data <= '1';
sel_blank_pdi <= '1';
if (G_PAD = 1 and wcount = 0) then
pad_enable <= '1';
pad_done <= '1';
pad_eot <= p_eot;
pad_eoi <= p_eoi;
pad_type_ad <= is_ad_r;
end if;
if (wcount = CNT_DATA_WORDS-1) then
p_size_r <= p_size_r - G_DBLK_SIZE/8;
size_dword <= (others => '0');
bdi_size <= (others => '0');
wcount <= (others => '0');
is_ready_r <= '1';
is_nodata_r <= '1';
is_eot_r <= '1';
pstate <= SP_WAIT_SPECIAL_AD_READ;
else
wcount <= wcount + 1;
end if;
when SP_WAIT_SPECIAL_AD_READ =>
if (bdi_read = '1') then
is_ready_r <= '0';
is_eot_r <= '0';
is_eoi_r <= '0';
is_ad_r <= '0';
is_nodata_r <= '0';
is_extra_block <= '0';
pad_done <= '0';
if (p_reg_stype = ST_NPUB) then
pstate <= SP_WAIT_INSTR;
bdi_proc <= '0';
elsif (p_reg_stype = ST_AD) then
pstate <= SP_WAIT_HDR;
else
pstate <= SP_WAIT_DATA;
end if;
end if;
when SP_WAIT_DATA =>
if (((is_ad_r = '1' or (is_nsec_r = '1' and G_NSEC_ENABLE = 1))
and bypass_fifo_full = '0' and pdi_valid = '1')
or (is_ad_r = '0' and pdi_valid = '1')
or (pwrem = 0 and p_eot = '1')
or (PARTIAL_LOAD = 1 and is_partial_data = '1'))
then
--! If remaining data word is 0, pad input block with 0
if (pwrem /= 0) then
if (is_ad_r = '1' and is_tag_r = '0') then
if (PARTIAL_LOAD = 0) then
bypass_fifo_wr <= '1';
elsif (PARTIAL_LOAD = 1 and
((wcount < total_words) or
(wcount = total_words and is_partial_data = '0')))
then
bypass_fifo_wr <= '1';
end if;
end if;
else
sel_blank_pdi <= '1';
end if;
--! Perform padding
if (G_PAD = 1) then
if (((PARTIAL_LOAD = 0 and p_eot = '1'
and pwrem < G_W/8 and pad_done = '0')
or (PARTIAL_LOAD = 1 and p_eot = '1'
and pwrem < G_W/8 and pad_done = '0'
and (wcount /= total_words or (wcount = total_words and is_partial_data = '0')))
or (G_REVERSE_DBLK = 1 and is_first_blk = '1'
and is_ad_r = '0' and remainder(G_BS_BYTES-1 downto 0) < G_DBLK_SIZE/8
and remainder(G_BS_BYTES-1 downto 0) /= 0 and is_decrypt_r = '1')))
then
if ((is_ad_r = '0' and G_PAD_D > 0) or
(is_ad_r = '1' and is_tag_r = '0' and G_PAD_AD > 0) or
(G_PAD_D > 0 and G_PAD_AD > 0))
then
pad_enable <= '1';
pad_done <= '1';
pad_eot <= p_eot;
pad_eoi <= p_eoi;
pad_type_ad <= is_ad_r;
end if;
end if;
end if;
if ((PARTIAL_LOAD = 1) and
((G_ABLK_SIZE = G_DBLK_SIZE and wcount = CNT_DATA_WORDS-1)
or (G_ABLK_SIZE /= G_DBLK_SIZE and wcount = total_words)))
then
if (is_partial_data = '0') then
if (pwrem <= G_W/8) then
pwrem <= (others => '0');
else
pwrem <= pwrem - G_W/8;
end if;
end if;
else
if (G_ABLK_SIZE = G_DBLK_SIZE) then
if (pwrem <= G_W/8) then
pwrem <= (others => '0');
else
pwrem <= pwrem - G_W/8;
end if;
else
if (wcount < total_words) then
if (pwrem <= G_W/8) then
pwrem <= (others => '0');
else
pwrem <= pwrem - G_W/8;
end if;
end if;
end if;
end if;
if (G_REVERSE_DBLK = 0) then
if (pwrem <= G_W/8) then
size_dword <= pwrem(log2_ceil(G_W/8) downto 0);
else
size_dword <= std_logic_vector(to_unsigned(G_W/8,log2_ceil(G_W/8)+1));
end if;
else
--! Special case for PRIMATEs-APE
if (is_ad_r = '1' and pwrem <= G_W/8) then
size_dword <= pwrem(log2_ceil(G_W/8) downto 0);
elsif (is_ad_r = '0' and is_first_blk = '1' and remainder(G_BS_BYTES-1 downto 0) < G_DBLK_SIZE/8 and remainder(G_BS_BYTES-1 downto 0) /= 0) then
size_dword <= remainder(log2_ceil(G_W/8) downto 0);
else
size_dword <= std_logic_vector(to_unsigned(G_W/8,log2_ceil(G_W/8)+1));
end if;
end if;
if (is_tag_r = '0') then
en_data <= '1';
if (wcount = CNT_DATA_WORDS-1) then
--! Handling case when AD_BLOCK /= Data_BLOCK
if (G_ABLK_SIZE /= G_DBLK_SIZE) then
if (is_ad_r = '1') then
p_size_r <= p_size_r - G_ABLK_SIZE/8;
else
p_size_r <= p_size_r - G_DBLK_SIZE/8;
end if;
else
if (G_KEYAK = 0) then
p_size_r <= p_size_r - G_DBLK_SIZE/8;
else
p_size_r <= p_size_r - (G_DBLK_SIZE/8 - 256/8);
end if;
end if;
wcount <= (others => '0');
--! Status signals and state transition
is_ready_r <= '1';
if (PARTIAL_LOAD = 1) then
en_last_word <= '1';
if ((pwrem <= (G_W/8)/2) and
(is_partial_data = '0'))
then
--! If it's decrypt and of type message, start loading tag segment
if (is_decrypt_r = '1' and p_eoi = '1') then
pstate <= SP_WAIT_HDR;
else
pstate <= SP_WAIT_DATA_READ;
end if;
else
pstate <= SP_WAIT_DATA_READ;
end if;
else
if ((G_REVERSE_DBLK = 0) or (is_decrypt_r = '0') or (is_ad_r = '1')) then
--! Case when Reverse data block is required
if (pwrem < G_W/8) then
bdi_size <= p_size_r(G_BS_BYTES-1 downto 0);
else
bdi_size <= (others => '0');
end if;
else
if (is_first_blk = '1' and is_ad_r = '0') then
if (remainder(G_BS_BYTES-1 downto 0) < G_DBLK_SIZE/8) then
bdi_size <= remainder(G_BS_BYTES-1 downto 0);
else
bdi_size <= (others => '0');
end if;
is_first_blk <= '0';
else
bdi_size <= (others => '0');
end if;
end if;
if (pwrem <= G_W/8) then
if (G_PAD = 1 and ((G_PAD_D > 1 and needs_extra_block = '1' and is_ad_r = '0') or (G_PAD_AD > 1 and needs_extra_block_ad = '1'))) then
is_eot_r <= '0';
else
is_eot_r <= p_eot;
end if;
--! If it's decrypt and of type message, start loading tag segment
if (is_decrypt_r = '1' and is_ad_r = '0' and p_eot = '1') then
is_eoi_r <= p_eot;
if ((G_REVERSE_DBLK = 1 and G_CIPHERTEXT_MODE = 2) and p_eoi = '1') then
pstate <= SP_WAIT_MSG_AUTH;
elsif (G_PAD = 1 and (G_PAD_D > 2 and needs_extra_block = '1')) then
pstate <= SP_WAIT_DATA_READ;
else
pstate <= SP_WAIT_HDR;
end if;
else
if (G_PAD = 1 and ((G_PAD_D > 1 and needs_extra_block = '1') or (G_PAD_AD > 1 and needs_extra_block_ad = '1'))) then
is_eoi_r <= '0';
else
is_eoi_r <= p_eoi;
end if;
pstate <= SP_WAIT_DATA_READ;
end if;
else
pstate <= SP_WAIT_DATA_READ;
end if;
end if;
else
wcount <= wcount + 1;
end if;
if (PARTIAL_LOAD = 1) then
--! Special case when (G_DBLK_SIZE mod G_W = G_W/2)
if (wcount < total_words) then
if (pwrem <= (G_W/8)/2) then
is_partial_data <= '0';
end if;
elsif (wcount = total_words) then
if ((is_partial_data = '0')
and ((pwrem > ((G_ABLK_SIZE/8) mod (G_W/8)) and is_ad_r = '1')
or (pwrem > ((G_DBLK_SIZE/8) mod (G_W/8)) and is_ad_r = '0')))
then
is_partial_data <= '1';
else
is_partial_data <= '0';
end if;
if (((pwrem < (G_W/8)/2 and is_partial_data = '0')
or (pwrem = 0 and is_partial_data = '1'))
and ((is_ad_r = '1' and p_size_r(G_BS_BYTES-1 downto 0) /= G_ABLK_SIZE/8)
or (is_ad_r = '0' and p_size_r(G_BS_BYTES-1 downto 0) /= G_DBLK_SIZE/8)))
then
bdi_size <= p_size_r(G_BS_BYTES-1 downto 0);
else
bdi_size <= (others => '0');
end if;
if (is_partial_data = '0' and pwrem <= (G_W/8)/2) or
(is_partial_data = '1' and pwrem = 0 )
then
is_eot_r <= p_eot;
is_eoi_r <= p_eoi;
else
is_eot_r <= '0';
end if;
end if;
if (wcount < total_words) then
if (is_partial_data = '0') then
sel_input <= "000"; --! D[HI] & D[LO]
else
if (pwrem = 0) then
sel_input <= "011"; --! D[LO] & 00..
else
sel_input <= "010"; --! D[LO] & D[HI]
end if;
end if;
elsif (wcount = total_words) then
if (is_partial_data = '0') then
sel_input <= "001"; --! D[HI] & 00..
else
sel_input <= "011"; --! D[LO] & 00..
end if;
else
sel_input <= "111"; --! "00..."
end if;
end if;
else
if (bdi_read = '1') then
is_ready_r <= '0';
end if;
en_exp_tag <= '1';
if (wcount = CNT_TAG_WORDS-1) then
wcount <= (others => '0');
if (p_eoi = '1') then
pstate <= SP_WAIT_MSG_AUTH;
else
pstate <= SP_WAIT_HDR;
end if;
exp_tag_ready_r <= '1';
else
wcount <= wcount + 1;
end if;
end if;
end if;
when SP_WAIT_DATA_READ =>
wcount <= (others => '0');
if (bdi_read = '1') then
is_ready_r <= '0';
is_eot_r <= '0';
is_eoi_r <= '0';
is_nodata_r <= '0';
if (pwrem = 0) then
if (G_PAD = 1
and (G_PAD_AD > 1 or G_PAD_D > 1)
and (needs_extra_block = '1' or needs_extra_block_ad = '1')) then
--! Special cases
if (needs_extra_block = '1') then
pstate <= SP_WAIT_DATA;
needs_extra_block <= '0';
is_ad_r <= '0';
elsif (needs_extra_block_ad = '1') then
pstate <= SP_LOAD_SPECIAL_AD;
needs_extra_block_ad <= '0';
is_ad_r <= '1';
end if;
is_extra_block <= '1';
is_nodata_r <= '1';
pad_done <= '0';
elsif (PARTIAL_LOAD = 1 and is_partial_data = '1') then
pstate <= SP_WAIT_DATA;
else
if (G_PAD = 1 and (G_PAD_AD > 1 or G_PAD_D > 1)) then
is_extra_block <= '0';
end if;
if (p_eoi = '1') then
if (is_decrypt_r = '1') then --! If AEAD_DECRYPT, there must be a tag segment after last message segment
if (tag_passed_r = '1') then
pstate <= SP_WAIT_MSG_AUTH;
else
pstate <= SP_WAIT_HDR;
end if;
else
pstate <= SP_WAIT_INSTR;
bdi_proc <= '0';
end if;
else
pstate <= SP_WAIT_HDR;
end if;
end if;
else
if (G_PAD = 1
and (G_PAD_AD = 2 or G_PAD_AD = 4)
and is_extra_block = '1'
and is_ad_r = '1')
then --! Empty AD
is_ad_r <= '0';
is_nodata_r <= '0';
end if;
pstate <= SP_WAIT_DATA;
end if;
end if;
when SP_WAIT_MSG_AUTH =>
if (msg_auth_done = '1') then
pstate <= SP_WAIT_INSTR;
bdi_proc <= '0';
is_ready_r <= '0';
is_eot_r <= '0';
is_eoi_r <= '0';
elsif (bdi_read = '1') then
is_ready_r <= '0';
end if;
when SP_ERROR =>
pstate <= SP_ERROR;
end case;
end if;
end if;
end process;
--! Unregistered control signals (Required for correct timing)
pdi_ready <= '1' when pdi_valid = '1' and (
(pstate = SP_WAIT_INSTR and bypass_fifo_full = '0') or
(pstate = SP_WAIT_HDR and bypass_fifo_full = '0') or
(pstate = SP_WAIT_NPUB and (npub_ready_r = '0' or G_NPUB_DISABLE = 1) and bypass_fifo_full = '0') or
(pstate = SP_WAIT_NSEC and G_NSEC_ENABLE = 1 and nsec_ready_r = '0') or
(pstate = SP_LOADLEN and G_LOADLEN_ENABLE = 1) or
(pstate = SP_WAIT_DATA and PARTIAL_LOAD = 0
and (((is_ad_r = '1' or (is_nsec_r = '1' and G_NSEC_ENABLE = 1)) and bypass_fifo_full = '0' and pwrem /= 0)
or (is_ad_r = '0' and pwrem /= 0))) or
(pstate = SP_WAIT_DATA and PARTIAL_LOAD = 1 and
(wcount < total_words or (wcount = total_words and is_partial_data = '0')) and
(((is_ad_r = '1' or (is_nsec_r = '1' and G_NSEC_ENABLE = 1)) and bypass_fifo_full = '0' and pwrem /= 0) or
(is_ad_r = '0' and pwrem /= 0)))
) else '0';
gLoadLenDisable:
if (G_LOADLEN_ENABLE /= 1) generate
en_len_a <= '1' when (pstate = SP_READ_HDR and p_stype = ST_AD) else '0';
en_len_d <= '1' when (pstate = SP_READ_HDR and (p_stype = ST_MESSAGE or p_stype = ST_CIPHER)) else '0';
end generate;
--! Division required for reverse block mode
gRB:
if (G_REVERSE_DBLK = 1) generate
remainder <= std_logic_vector(unsigned(p_size_r) MOD to_unsigned(G_DBLK_SIZE/8, CNTR_WIDTH));
end generate;
--! Control for secret data
p_sstate:
process( clk )
begin
if rising_edge( clk ) then
if rst = '1' then
sstate <= SS_WAIT_INSTR;
if (G_RDKEY_ENABLE = 1) then
set_rdkey_ready <= '0';
else
set_key_ready <= '0';
end if;
error_sdi <= (others => '0');
else
if (G_RDKEY_ENABLE = 1) then
en_rdkey <= '0';
set_rdkey_ready <= '0';
else
en_key <= '0';
set_key_ready <= '0';
end if;
case sstate is
when SS_WAIT_INSTR =>
if (sdi_valid = '1') then
sstate <= SS_READ_INSTR;
end if;
when SS_READ_INSTR =>
if (s_opcode /= OP_LD_KEY and s_opcode /= OP_LD_RKEY) then
sstate <= SS_WAIT_INSTR;
error_sdi(1) <= '1'; --! Unsupported opcode
else
sstate <= SS_WAIT_HDR;
end if;
when SS_WAIT_HDR =>
if (sdi_valid = '1'
and ((G_RDKEY_ENABLE = 0 and key_ready_r = '0') or
(G_RDKEY_ENABLE = 1 and rdkey_ready_r = '0')))
then
sstate <= SS_READ_HDR;
end if;
when SS_READ_HDR =>
swcount <= (others => '0');
key_id_r <= s_key_id;
if (G_RDKEY_ENABLE = 0 and (s_stype = ST_KEY and s_size = G_KEY_SIZE/8)) then
sstate <= SS_WAIT_KEY;
elsif (G_RDKEY_ENABLE = 1 and s_stype = ST_RDKEY) then
sstate <= SS_WAIT_RDKEY;
swrem <= sdi(SWREMSIZE+SWSIZE-1 downto SWSIZE)+nway_or(sdi(SWSIZE-1 downto 0));
else
error_sdi(7) <= '1'; --! Segment error
sstate <= SS_WAIT_INSTR;
end if;
when SS_WAIT_KEY =>
if (sdi_valid = '1') then
en_key <= '1';
if (swcount = (G_KEY_SIZE/G_SW)-1) then
sstate <= SS_DELAY;
set_key_ready <= '1';
else
swcount <= swcount + 1;
end if;
end if;
when SS_DELAY =>
sstate <= SS_WAIT_INSTR;
when SS_WAIT_RDKEY =>
if (sdi_valid = '1') then
en_rdkey <= '1';
swrem <= swrem - 1;
if (swcount = (G_KEY_SIZE/G_SW)-1) then
set_rdkey_ready <= '1';
sstate <= SS_WAIT_RDKEY_READ;
else
swcount <= swcount + 1;
end if;
end if;
when SS_WAIT_RDKEY_READ =>
swcount <= (others => '0');
if (rdkey_read = '1') then
if (swrem = 0) then
sstate <= SS_WAIT_INSTR;
else
sstate <= SS_WAIT_RDKEY;
end if;
end if;
end case;
end if;
end if;
end process;
sdi_ready <= '1' when sdi_valid = '1' and (
(sstate = SS_WAIT_INSTR) or
(sstate = SS_WAIT_HDR and ((key_ready_r = '0' and G_RDKEY_ENABLE = 0) or (rdkey_ready_r = '0' and G_RDKEY_ENABLE = 1))) or
(sstate = SS_WAIT_KEY) or
(sstate = SS_WAIT_RDKEY and rdkey_read = '1')
) else '0';
end behavior;
| gpl-3.0 |
michaelfivez/ascon_hardware_implementation | ascon128128_unrolled4/API_plus_CipherCore/PreProcessor_Control.vhd | 9 | 77328 | -------------------------------------------------------------------------------
--! @file PreProcessor_Control.vhd
--! @brief Control unit for the pre-processor
--! @project CAESAR Candidate Evaluation
--! @author Ekawat (ice) Homsirikamol
--! @copyright Copyright (c) 2015 Cryptographic Engineering Research Group
--! ECE Department, George Mason University Fairfax, VA, U.S.A.
--! All rights Reserved.
--! @license This project is released under the GNU Public License.
--! The license and distribution terms for this file may be
--! found in the file LICENSE in this distribution or at
--! http://www.gnu.org/licenses/gpl-3.0.txt
--! @note This is publicly available encryption source code that falls
--! under the License Exception TSU (Technology and software-
--! —unrestricted)
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use work.AEAD_pkg.all;
entity PreProcessor_Control is
generic (
G_W : integer := 32; --! Public data width (bits)
G_SW : integer := 32; --! Secret data width (bits)
G_CIPHERTEXT_MODE : integer := 0; --! Ciphertext mode
G_PLAINTEXT_MODE : integer := 0; --! Plaintext Mode
G_ABLK_SIZE : integer := 128; --! Authenticated Data Block size (bits)
G_DBLK_SIZE : integer := 128; --! Data Block size (bits)
G_BS_BYTES : integer := 4; --! The number of bits required to hold block size expressed in bytes = log2_ceil(block_size/8)
G_KEY_SIZE : integer := 128; --! Key size (bits)
G_NPUB_DISABLE : integer := 0; --! Disable Npub related port(s)
G_NPUB_SIZE : integer := 128; --! Npub width (bits)
G_NSEC_ENABLE : integer := 0; --! Enable NSEC port
G_NSEC_SIZE : integer := 128; --! NSEC width (bits)
G_RDKEY_ENABLE : integer := 0; --! Enable rdkey port (also disables key port)
G_RDKEY_SIZE : integer := 128; --! Roundkey size (bits)
G_REVERSE_DBLK : integer := 0; --! Reverse block order (for message only)
G_LOADLEN_ENABLE : integer := 0; --! Enable load length section
G_CTR_AD_SIZE : integer := 16; --! Segment len size
G_CTR_D_SIZE : integer := 16; --! Segment len size
G_PAD : integer := 1; --! Enable padding
G_PAD_AD : integer := 1; --! (G_PAD's sub option) Enable AD Padding
G_PAD_D : integer := 1; --! (G_PAD's sub option) Enable Data padding
G_TAG_SIZE : integer := 128; --! Tag size (bits)
G_KEYAK : integer := 0 --! Special Keyak only mode
);
port (
--! =================
--! External Signals
--! =================
--! Global signals
clk : in std_logic;
rst : in std_logic;
--! Public signals
pdi : in std_logic_vector(G_W -1 downto 0);
pdi_valid : in std_logic;
pdi_ready : out std_logic;
--! Secret signals
sdi : in std_logic_vector(G_SW -1 downto 0);
sdi_valid : in std_logic;
sdi_ready : out std_logic;
error : out std_logic;
--! =================
--! Crypto Core Signals
--! =================
--! control signals
key_ready : out std_logic; --! Indicates that the key is ready
key_needs_update : out std_logic; --! Indicates that the key needs update and should be acknowledge by the core via key_updated signal
key_updated : in std_logic; --! Key has been updated
rdkey_ready : out std_logic; --! Round key ready
rdkey_read : in std_logic; --! Round key read
npub_ready : out std_logic; --! Npub ready
npub_read : in std_logic; --! Npub read
nsec_ready : out std_logic; --! Nsec ready
nsec_read : in std_logic; --! Nsec read
bdi_ready : out std_logic; --! Block ready
bdi_proc : out std_logic; --! Block processing
bdi_ad : out std_logic; --! Input block is an authenticated data
bdi_nsec : out std_logic; --! Input block is a secret message number
bdi_decrypt : out std_logic; --! Decryption operation
bdi_pad : out std_logic; --! Last block of segment type contain padding
bdi_eot : out std_logic; --! Last block of segment type (end-of-type)
bdi_eoi : out std_logic; --! Last block of message (end-of-input)
bdi_nodata : out std_logic; --! Control signal indicating that there's no plain-text or authenticated data. The unit should generate a tag right away.
bdi_read : in std_logic; --! Handshake signal indicating that the data block has been read
bdi_size : out std_logic_vector(G_BS_BYTES -1 downto 0); --! Block size signal. Note: 0 = Full block.
exp_tag_ready : out std_logic; --! Expected tag is ready
msg_auth_done : in std_logic; --! Tag comparison completion handshake
bypass_fifo_full : in std_logic; --! An input signal indicating that the bypass FIFO is full
bypass_fifo_wr : out std_logic; --! An output signal for writing data to bypass FIFO
--! =================
--! Internal Signals
--! =================
pad_shift : out std_logic_vector(log2_ceil(G_W/8) -1 downto 0);
en_data : out std_logic; --! Shift data SIPO
en_npub : out std_logic; --! Shift Npub SIPO
en_nsec : out std_logic; --! Shift Nsec SIPO
en_key : out std_logic; --! Shift Key SIPO
en_rdkey : out std_logic; --! Shift Round Key SIPO
sel_blank_pdi : out std_logic; --! Select input data as blank (for filling in the remaining data within a block)
clr_len : out std_logic; --! Clear stored length (len_a and len_d)
en_len_a_r : out std_logic; --! Add authenticated data counter
en_len_d_r : out std_logic; --! Add data counter
en_len_last_r : out std_logic; --! Special signal for en_len_*_r
en_len_a : out std_logic; --! Add authenticated data counter (instant)
en_len_d : out std_logic; --! Add data counter (instant)
en_exp_tag : out std_logic; --! Shift TAG SIPO
size_dword : out std_logic_vector(log2_ceil(G_W/8) downto 0); --! Size of data word
en_last_word : out std_logic; --! Last word of a block
--! Pad related control
pad_eot : out std_logic; --! Padding is EOT
pad_eoi : out std_logic; --! Padding is EOI
pad_type_ad : out std_logic; --! Padding is AD
pad_enable : out std_logic; --! Enable padding signal (indicates that the current word requires padding)
en_pad_loc : out std_logic; --! Save the padding location into a register
--! Supplemental control
key_updated_int : out std_logic; --! Only used for Keyak
sel_input : out std_logic_vector(2 downto 0) --! Sel input (used when (G_DBLK_SIZE mod G_W) > 0)
);
end PreProcessor_Control;
architecture behavior of PreProcessor_Control is
function getSwCount return integer is
variable maxval : integer := 0;
begin
if (G_NSEC_ENABLE = 1) then
maxval := G_NSEC_SIZE;
end if;
if (G_RDKEY_ENABLE = 1) then
maxval := maximum(maxval, G_RDKEY_SIZE);
else
maxval := maximum(maxval, G_KEY_SIZE);
end if;
return log2_ceil(maxval/G_SW);
end function;
--! Constants declaration
constant PARTIAL_LOAD : integer := isNotDivisible(G_DBLK_SIZE, G_W);
constant LOG2_W : integer := log2_ceil(G_W/8); --! LOG_2(G_W)
constant LOG2_SWORDS : integer := getSwCount; --! Expected key words
constant REGIV_WIDTH : integer := get_width(G_NPUB_SIZE, G_W); --! Calculate the width of Npub register
constant CNTR_WIDTH : integer := get_cntr_width(G_W); --! Calculate the length of p_size register
constant CNT_NPUB_WORDS : integer := get_words(G_NPUB_SIZE, G_W); --! Calculate the number of words required for Npub
constant CNT_AD_WORDS : integer := (G_ABLK_SIZE+(G_W-1))/G_W; --! Calculate the number of words required for data (rounded up)
constant CNT_DATA_WORDS : integer := (G_DBLK_SIZE+(G_W-1))/G_W; --! Calculate the number of words required for data (rounded up)
constant CNT_TAG_WORDS : integer := (G_TAG_SIZE+(G_W-1))/G_W; --! Calculate the number of words required for tag (rounded up)
constant CNT_LOADLEN_A_WORDS : integer := get_words(G_CTR_AD_SIZE, G_W);
constant CNT_LOADLEN_D_WORDS : integer := get_words(G_CTR_D_SIZE, G_W);
constant BSHIFT_INPUT : std_logic_vector(G_W/8 -1 downto 0) := std_logic_vector(to_unsigned(1,G_W/8));
constant WCOUNT_SIZE : integer := log2_ceil(maximum(maximum(CNT_NPUB_WORDS, CNT_DATA_WORDS), CNT_TAG_WORDS)+1);
constant ZEROS : std_logic_vector(G_DBLK_SIZE-1 downto 0) := (OTHERS => '0');
constant SWSIZE : integer := log2_ceil(G_SW/8);
constant SWREMSIZE : integer := (G_SW-16)-SWSIZE;
--! Types declaration
type pstate_type is (SP_WAIT_INSTR, SP_READ_INSTR,
SP_WAIT_HDR, SP_READ_HDR, SP_WAIT_NPUB, SP_WAIT_NSEC,
SP_INIT_KEYAK0, SP_INIT_KEYAK1, SP_INIT_KEYAK2, --! Special state for Keyak
SP_LOAD_SPECIAL_AD, SP_WAIT_SPECIAL_AD_READ, --! Special state for G_PAD_AD > 1
SP_LOADLEN, --! Special LOADLEN state
SP_WAIT_DATA, SP_WAIT_DATA_READ, SP_WAIT_MSG_AUTH,
SP_ERROR);
type sstate_type is (SS_WAIT_INSTR, SS_READ_INSTR,
SS_WAIT_HDR, SS_READ_HDR,
SS_WAIT_KEY, SS_DELAY,
SS_WAIT_RDKEY, SS_WAIT_RDKEY_READ);
--! State signals
signal pstate : pstate_type;
signal sstate : sstate_type;
--! Status controls
signal set_npub_ready : std_logic;
signal set_nsec_ready : std_logic;
signal clr_nsec_ready : std_logic;
signal set_rdkey_ready : std_logic;
--! SDI related signals
signal set_key_needs_update : std_logic;
signal set_key_ready : std_logic;
signal key_ready_r : std_logic;
signal key_needs_update_r : std_logic;
signal nsec_ready_r : std_logic;
signal rdkey_ready_r : std_logic;
signal key_id_r : std_logic_vector(8 -1 downto 0); --! Key id of the key_ready signal
signal key_act_id_init_r : std_logic; --! Status signal for key_act_id (used only after reset)
signal key_act_id_r : std_logic_vector(8 -1 downto 0); --! Activated key_id
signal s_opcode : std_logic_vector(LEN_OPCODE -1 downto 0); --! Secret data opcode
signal s_stype : std_logic_vector(LEN_SMT_HDR -1 downto 0); --! Secret data segment type
signal s_size : std_logic_vector(G_SW-16 -1 downto 0); --! Secret data segment size
signal swcount : std_logic_vector(LOG2_SWORDS -1 downto 0); --! Secret data words count
signal swrem : std_logic_vector(SWREMSIZE -1 downto 0); --! Secret data byte remainder
signal s_key_id : std_logic_vector(8 -1 downto 0); --! Secret data key id
--! Public data signals and registers
signal p_reg_stype : std_logic_vector(LEN_SMT_HDR -1 downto 0); --! Segment type register
signal pwrem : std_logic_vector(CNTR_WIDTH -1 downto 0); --! Private data words remaining
signal wcount : std_logic_vector(WCOUNT_SIZE -1 downto 0); --! Word count
signal p_opcode : std_logic_vector(LEN_OPCODE -1 downto 0); --! Opcode
signal p_stype : std_logic_vector(LEN_SMT_HDR -1 downto 0); --! Segment type
signal p_eot : std_logic; --! Last segment of the specified type flag
signal p_eoi : std_logic; --! Last segment of the message flag
signal p_id : std_logic_vector(LEN_MSG_ID -1 downto 0); --! ID
signal p_size : std_logic_vector(CNTR_WIDTH -1 downto 0); --! Public data segment size
signal p_size_r : std_logic_vector(CNTR_WIDTH -1 downto 0); --! Public data segment size register
signal p_key_id : std_logic_vector(8 -1 downto 0); --! Public data key id
signal remainder : std_logic_vector(CNTR_WIDTH -1 downto 0);
--! Data block status register
signal is_ae_r : std_logic; --! Current block is an authenticated encryption block
--! Data block status registers for external modules
signal npub_ready_r : std_logic;
signal ad_passed_r : std_logic;
signal tag_passed_r : std_logic;
signal is_decrypt_r : std_logic; --! Current message is a decryption
signal is_ad_r : std_logic; --! Current block is an authenticated data block
signal is_tag_r : std_logic; --! Current segment is a tag
signal is_nsec_r : std_logic; --! Current block is a nsec
signal is_ready_r : std_logic; --! Current block is ready
signal is_eot_r : std_logic; --! Current block is the last of its type in the current segment
signal is_eoi_r : std_logic; --! Current block is the last block of message
signal is_nodata_r : std_logic; --! Current block contains no message data (used for authenticated encryption data only mode)
signal is_first_blk : std_logic;
signal is_init_r : std_logic;
--! Padding related signals
signal pad_done : std_logic;
--! Other status registers
signal exp_tag_ready_r : std_logic; --! Needs a delay
signal needs_extra_block : std_logic;
signal needs_extra_block_ad : std_logic;
signal is_extra_block : std_logic;
signal is_partial_data : std_logic;
signal total_words : std_logic_vector(WCOUNT_SIZE -1 downto 0);
--! Error registers
signal errors : std_logic_vector(8 -1 downto 0); --! Error flag (Used for debugging)
signal error_pdi : std_logic_vector(8 downto 1);
signal error_sdi : std_logic_vector(8 downto 1);
begin
--! Datapath
p_reg:
process( clk )
begin
if rising_edge( clk ) then
if rst = '1' then
key_needs_update_r <= '0';
key_ready_r <= '0';
bdi_ready <= '0';
if (G_NPUB_DISABLE = 0) then
npub_ready_r <= '0';
end if;
if (G_NSEC_ENABLE = 1) then
nsec_ready_r <= '0';
end if;
if (G_RDKEY_ENABLE = 1) then
rdkey_ready_r <= '0';
end if;
key_act_id_init_r <= '0';
key_act_id_r <= (others => '0');
else
if (set_key_needs_update = '1') then
key_needs_update_r <= '1';
elsif (key_updated = '1') then
key_needs_update_r <= '0';
end if;
if (G_NSEC_ENABLE = 1) then
if (set_nsec_ready = '1') then
nsec_ready_r <= '1';
elsif (nsec_read = '1') then
nsec_ready_r <= '0';
end if;
end if;
if (G_NPUB_DISABLE = 0) then
if (set_npub_ready = '1') then
npub_ready_r <= '1';
elsif (npub_read = '1') then
npub_ready_r <= '0';
end if;
end if;
if (G_RDKEY_ENABLE = 1) then
if (set_rdkey_ready = '1') then
rdkey_ready_r <= '1';
elsif (rdkey_read = '1') then
rdkey_ready_r <= '0';
if (swrem = 0) then
key_act_id_init_r <= '1';
key_act_id_r <= key_id_r;
end if;
end if;
else
if (set_key_ready = '1') then
key_ready_r <= '1';
elsif (key_updated = '1') then
key_ready_r <= '0';
key_act_id_init_r <= '1';
key_act_id_r <= key_id_r;
end if;
end if;
exp_tag_ready <= exp_tag_ready_r;
bdi_ready <= is_ready_r and not bdi_read;
end if;
end if;
end process;
gRdkeyEnable0: if (G_RDKEY_ENABLE = 0) generate
key_ready <= key_ready_r;
end generate;
gRdkeyEnable1: if (G_RDKEY_ENABLE = 1) generate
rdkey_ready <= rdkey_ready_r;
end generate;
gNsecEnable1: if (G_NSEC_ENABLE = 1) generate
nsec_ready <= nsec_ready_r;
end generate;
key_needs_update <= key_needs_update_r;
s_key_id <= sdi(G_SW -1 downto G_SW- 8);
s_stype <= sdi(G_SW- 8 -1 downto G_SW-12);
s_opcode <= sdi(G_SW-12 -1 downto G_SW-16);
s_size <= sdi(G_SW-16 -1 downto 0);
p_stype <= pdi(G_W - 8 -1 downto G_W -12);
p_opcode <= pdi(G_W -12 -1 downto G_W -16);
p_key_id <= pdi(G_W -16 -1 downto G_W -24);
p_size <= pdi(CNTR_WIDTH -1 downto 0);
bdi_ad <= is_ad_r;
bdi_nsec <= is_nsec_r;
bdi_decrypt <= is_decrypt_r;
bdi_pad <= '0';
bdi_eot <= is_eot_r;
bdi_eoi <= is_eoi_r;
bdi_nodata <= is_nodata_r;
npub_ready <= npub_ready_r;
errors <= error_pdi or error_sdi;
error <= nway_or(errors);
genPad: if (G_PAD = 1) generate
-- genPadShiftReverse00: if (G_REVERSE_DBLK = 0 and G_PAD_AD /= 4) generate
-- en_pad_loc <= '1' when (PARTIAL_LOAD = 0 and pstate = SP_WAIT_DATA and p_eot = '1' and pwrem <= G_W/8 and pad_done = '0') or
-- (PARTIAL_LOAD = 1 and pstate = SP_WAIT_DATA and p_eot = '1' and pwrem <= G_W/8 and pad_done = '0' and wcount /= total_words) or
-- (PARTIAL_LOAD = 1 and pstate = SP_WAIT_DATA and p_eot = '1' and pwrem <= G_W/8 and pad_done = '0' and wcount = total_words and is_partial_data = '0')
-- else '0';
-- end generate;
genPadShiftReverse0: if (G_REVERSE_DBLK = 0) generate
en_pad_loc <= '1' when ((PARTIAL_LOAD = 0 and pstate = SP_WAIT_DATA and p_eot = '1' and pwrem <= G_W/8 and pad_done = '0') or
(PARTIAL_LOAD = 0 and (G_PAD_AD = 2 or G_PAD_AD = 4) and pstate = SP_LOAD_SPECIAL_AD and wcount = 0) or
(PARTIAL_LOAD = 1 and pstate = SP_WAIT_DATA and p_eot = '1' and pwrem <= G_W/8 and pad_done = '0' and wcount /= total_words) or
(PARTIAL_LOAD = 1 and pstate = SP_WAIT_DATA and p_eot = '1' and pwrem <= G_W/8 and pad_done = '0' and wcount = total_words and is_partial_data = '0'))
else '0';
end generate;
genPadShiftReverse1: if (G_REVERSE_DBLK = 1) generate
en_pad_loc <= '1' when ((pstate = SP_WAIT_DATA and p_eot = '1' and pwrem <= G_W/8 and pad_done = '0' and is_ad_r = '1') or
(pstate = SP_WAIT_DATA and is_tag_r = '0' and is_first_blk = '1' and is_ad_r = '0')) else '0';
end generate;
end generate;
genPadShiftX: if (G_PAD = 1 and (G_PAD_D < 2 and G_PAD_AD < 2)) generate
genPadShiftReverse0: if (G_REVERSE_DBLK = 0) generate
pad_shift <= p_size_r(log2_ceil(G_W/8)-1 downto 0);
end generate;
genPadShiftReverse1: if (G_REVERSE_DBLK = 1) generate
pad_shift <= remainder(log2_ceil(G_W/8)-1 downto 0) when (remainder(G_BS_BYTES-1 downto 0) < G_DBLK_SIZE/8) else (others => '0');
end generate;
end generate;
genPadShift2: if (G_PAD = 1 and (G_PAD_D > 1 or G_PAD_AD > 1)) generate
pad_shift <= p_size_r(log2_ceil(G_W/8)-1 downto 0) when is_extra_block = '0' else (others => '0');
end generate;
--! Control for public data
p_pstate:
process( clk )
begin
if rising_edge( clk ) then
if rst = '1' then
pstate <= SP_WAIT_INSTR;
en_data <= '0';
en_npub <= '0';
error_pdi <= (others => '0');
bypass_fifo_wr <= '0';
p_eot <= '0';
p_eoi <= '0';
p_id <= (others => '0');
bdi_proc <= '0';
is_ad_r <= '0';
is_tag_r <= '0';
is_nsec_r <= '0';
is_ae_r <= '0';
is_decrypt_r <= '0';
is_ready_r <= '0';
is_eot_r <= '0';
is_eoi_r <= '0';
is_nodata_r <= '0';
sel_blank_pdi <= '0';
exp_tag_ready_r <= '0';
ad_passed_r <= '0';
if (G_PAD = 1) then
pad_type_ad <= '0';
pad_eot <= '0';
pad_eoi <= '0';
end if;
p_reg_stype <= (others => '0');
set_key_needs_update <= '0';
if (PARTIAL_LOAD = 1) then
is_partial_data <= '0';
en_last_word <= '0';
sel_input <= (others => '0');
end if;
if (G_NSEC_ENABLE = 1) then
set_nsec_ready <= '0';
end if;
if (G_PAD = 1) then
pad_enable <= '0';
end if;
if (G_LOADLEN_ENABLE = 1) then
en_len_a_r <= '0';
en_len_d_r <= '0';
if ((G_CTR_AD_SIZE mod G_W /= 0) or (G_CTR_D_SIZE mod G_W /= 0)) then
en_len_last_r <= '0';
end if;
end if;
else
en_data <= '0';
bypass_fifo_wr <= '0';
clr_len <= '0';
sel_blank_pdi <= '0';
en_exp_tag <= '0';
set_key_needs_update <= '0';
if (G_PAD = 1) then
pad_type_ad <= '0';
pad_eot <= '0';
pad_eoi <= '0';
end if;
if (PARTIAL_LOAD = 1) then
en_last_word <= '0';
sel_input <= (others => '0');
end if;
if (G_NPUB_DISABLE = 0) then
en_npub <= '0';
set_npub_ready <= '0';
end if;
if (G_NSEC_ENABLE = 1) then
en_nsec <= '0';
set_nsec_ready <= '0';
end if;
if (G_PAD = 1) then
pad_enable <= '0';
end if;
if (G_KEYAK = 1) then
key_updated_int <= '0';
end if;
if (G_LOADLEN_ENABLE = 1) then
en_len_a_r <= '0';
en_len_d_r <= '0';
if ((G_CTR_AD_SIZE mod G_W /= 0) or (G_CTR_D_SIZE mod G_W /= 0)) then
en_len_last_r <= '0';
end if;
end if;
case pstate is
when SP_WAIT_INSTR =>
if (pdi_valid = '1' and bypass_fifo_full = '0') then
pstate <= SP_READ_INSTR;
bypass_fifo_wr <= '1';
end if;
pwrem <= (others => '0');
p_size_r <= (others => '0');
p_eot <= '0';
p_eoi <= '0';
p_id <= (others => '0');
wcount <= (others => '0');
is_ad_r <= '0';
is_tag_r <= '0';
is_nsec_r <= '0';
is_ae_r <= '0';
is_decrypt_r <= '0';
is_ready_r <= '0';
clr_len <= '1';
is_nodata_r <= '0';
exp_tag_ready_r <= '0';
bdi_size <= (others => '0');
tag_passed_r <= '0';
if G_REVERSE_DBLK = 1 then
is_first_blk <= '1';
end if;
if (G_KEYAK = 1) then
is_init_r <= '1';
end if;
if (G_PAD = 1) then
if (G_PAD_AD > 1 or G_PAD_D > 1) then
is_extra_block <= '0';
needs_extra_block <= '0';
needs_extra_block_ad <= '0';
end if;
if (G_PAD_AD > 1) then
ad_passed_r <= '0';
end if;
end if;
when SP_READ_INSTR =>
if (p_opcode /= OP_AE_ENC)
and (p_opcode /= OP_AE_DEC)
and (p_opcode /= OP_ACT_KEY)
and (p_opcode /= OP_ENC)
and (p_opcode /= OP_DEC)
then
pstate <= SP_ERROR;
error_pdi(1) <= '1'; --! Unsupported opcode
else
if (p_opcode = OP_AE_DEC) or (p_opcode = OP_DEC) then
is_decrypt_r <= '1';
end if;
if (p_opcode = OP_AE_DEC or p_opcode = OP_AE_ENC) then
is_ae_r <= '1';
end if;
if (p_opcode = OP_ACT_KEY) then
pstate <= SP_WAIT_INSTR;
if (key_act_id_init_r = '0'
or (key_act_id_init_r = '1'
and p_key_id /= key_act_id_r))
then
set_key_needs_update <= '1';
end if;
else
pstate <= SP_WAIT_HDR;
p_reg_stype <= p_stype;
bdi_proc <= '1';
end if;
end if;
when SP_WAIT_HDR =>
if (pdi_valid = '1' and bypass_fifo_full = '0') then
pstate <= SP_READ_HDR;
bypass_fifo_wr <= '1';
end if;
--! Pad
if G_PAD = 1 then
pad_done <= '0';
end if;
when SP_READ_HDR =>
if (not ((G_LOADLEN_ENABLE = 1 and p_stype = ST_LEN)
or (p_stype = ST_NPUB)
or (p_stype = ST_AD)
or (p_stype = ST_MESSAGE and is_decrypt_r = '0')
or (p_stype = ST_CIPHER and is_decrypt_r = '1')
or (p_stype = ST_TAG and is_decrypt_r = '1')))
then
pstate <= SP_ERROR;
error_pdi(7) <= '1'; --! Segment type incompatible with opcode
else
--! Store segment type
if (pdi(G_W-15-1) = '1') then
p_reg_stype <= p_stype;
end if;
--! Determining the type and appropriate sequence of inputs. Uses for debugging as well (not fully implemented).
if (p_stype = ST_NPUB) then
if (p_reg_stype = ST_INIT ) or
(G_LOADLEN_ENABLE = 1 and p_reg_stype = ST_LEN )
then
if ( p_size /= G_NPUB_SIZE/8 ) then
pstate <= SP_ERROR;
error_pdi(4) <= '1'; --! Unsupported Npub Length
else
pstate <= SP_WAIT_NPUB;
end if;
else
pstate <= SP_ERROR;
error_pdi(6) <= '1'; --! Segment out of sequence
end if;
elsif (p_stype = ST_AD) then
if ((G_PLAINTEXT_MODE = 0 and (p_reg_stype = ST_NPUB or p_reg_stype = ST_AD or (G_NSEC_ENABLE = 1 and (p_reg_stype = ST_NSEC or p_reg_stype = ST_NSEC_CIPH))))
or (G_PLAINTEXT_MODE = 1 and (p_reg_stype = ST_INIT or p_reg_stype = ST_AD))
or (G_PLAINTEXT_MODE = 2 and (p_reg_stype = ST_INIT or p_reg_stype = ST_AD))
or (G_PLAINTEXT_MODE = 3 and (p_reg_stype = ST_NPUB or p_reg_stype = ST_AD or p_reg_stype = ST_MESSAGE or p_reg_stype = ST_CIPHER))
or ((G_CIPHERTEXT_MODE = 2 and G_REVERSE_DBLK = 1) and (p_reg_stype = ST_TAG)))
then
if (G_KEYAK = 1 and is_init_r = '1') then
is_init_r <= '0';
pstate <= SP_INIT_KEYAK0;
else
pstate <= SP_WAIT_DATA;
end if;
is_ad_r <= '1';
is_tag_r <= '0';
is_nsec_r <= '0';
else
pstate <= SP_ERROR;
error_pdi(6) <= '1'; --! Segment out of sequence
end if;
if (PARTIAL_LOAD = 1) then
total_words <= std_logic_vector(to_unsigned(CNT_AD_WORDS-1, WCOUNT_SIZE));
is_partial_data <= '0';
end if;
if (G_PAD = 1) then
if (G_PAD_AD > 1) then
ad_passed_r <= '1';
end if;
if ((G_PAD_D = 2 or G_PAD_D = 4) and pdi(G_W-14-1) = '1') then --! EOI
needs_extra_block <= '1';
end if;
if ((G_ABLK_SIZE = G_DBLK_SIZE and (G_PAD_AD > 2) and G_PLAINTEXT_MODE < 3) and --! EOT and Full block
pdi(G_BS_BYTES-1 downto 0) = 0 and pdi(G_W-15-1) = '1')
then
needs_extra_block_ad <= '1';
end if;
end if;
elsif (p_stype = ST_MESSAGE or p_stype = ST_CIPHER) then
if ((G_PLAINTEXT_MODE = 0 and (p_reg_stype = ST_NPUB or p_reg_stype = ST_AD or p_reg_stype = ST_MESSAGE or p_reg_stype = ST_CIPHER or (G_NSEC_ENABLE = 1 and (p_reg_stype = ST_NSEC or p_reg_stype = ST_NSEC_CIPH))))
or (G_PLAINTEXT_MODE = 1)
or (G_PLAINTEXT_MODE = 2)
or (G_PLAINTEXT_MODE = 3 and (p_reg_stype = ST_NPUB or p_reg_stype = ST_AD or p_reg_stype = ST_MESSAGE or p_reg_stype = ST_CIPHER))
or ((G_CIPHERTEXT_MODE = 2 and G_REVERSE_DBLK = 1) and (p_reg_stype = ST_TAG)))
then
if (G_PLAINTEXT_MODE < 3 and G_PAD = 1 and (G_PAD_AD = 2 or G_PAD_AD = 4) and ad_passed_r = '0') then
--! Empty AD
pstate <= SP_LOAD_SPECIAL_AD;
is_ad_r <= '1';
is_extra_block <= '1';
else
pstate <= SP_WAIT_DATA;
is_ad_r <= '0';
end if;
is_tag_r <= '0';
is_nsec_r <= '0';
else
pstate <= SP_ERROR;
error_pdi(6) <= '1'; --! Segment out of sequence
end if;
if (PARTIAL_LOAD = 1) then
total_words <= std_logic_vector(to_unsigned(CNT_DATA_WORDS-1, WCOUNT_SIZE));
is_partial_data <= '0';
end if;
--! Calculate if additional block needs to be added (only for Message type)
if (G_PAD = 1 and G_PAD_D > 2) then
if (pdi(G_BS_BYTES-1 downto 0) = 0 and (G_CIPHERTEXT_MODE < 2 or is_decrypt_r = '0') and pdi(G_W-14-1) = '1') then
needs_extra_block <= '1';
else
needs_extra_block <= '0';
end if;
end if;
elsif (G_NSEC_ENABLE = 1 and (p_stype = ST_NSEC or p_stype = ST_NSEC_CIPH)) then
pstate <= SP_WAIT_NSEC;
elsif (p_stype = ST_TAG) then
tag_passed_r <= '1';
if (is_decrypt_r = '0') then
pstate <= SP_ERROR;
error_pdi(6) <= '1';
else
pstate <= SP_WAIT_DATA;
is_tag_r <= '1';
if (is_ready_r = '0') then
is_ad_r <= '0';
is_nsec_r <= '0';
end if;
end if;
elsif (G_LOADLEN_ENABLE = 1 and p_stype = ST_LEN) then
pstate <= SP_LOADLEN;
else --! Unsupported segment type
pstate <= SP_ERROR;
error_pdi(6) <= '1';
end if;
pwrem <= pdi(CNTR_WIDTH-1 downto 0);
p_size_r <= pdi(CNTR_WIDTH-1 downto 0);
p_eot <= pdi(G_W-15-1);
p_eoi <= pdi(G_W-14-1);
p_id <= pdi(G_W-1 downto G_W-8);
end if;
when SP_LOADLEN =>
if (pdi_valid = '1' and bypass_fifo_full = '0') then
bypass_fifo_wr <= '1';
if (wcount <= CNT_LOADLEN_A_WORDS-1) then
en_len_a_r <= '1';
else
en_len_d_r <= '1';
end if;
if ((G_CTR_AD_SIZE mod G_W /= 0) or (G_CTR_D_SIZE mod G_W /= 0)) then
if (wcount = CNT_LOADLEN_A_WORDS-1) or
(wcount = (CNT_LOADLEN_A_WORDS+CNT_LOADLEN_D_WORDS-1))
then
en_len_last_r <= '1';
end if;
end if;
if (wcount = (CNT_LOADLEN_A_WORDS+CNT_LOADLEN_D_WORDS-1)) then
pstate <= SP_WAIT_HDR;
wcount <= (others => '0');
else
wcount <= wcount + 1;
end if;
end if;
when SP_WAIT_NPUB =>
if (pdi_valid = '1' and bypass_fifo_full = '0'
and (G_NPUB_DISABLE = 1 or npub_ready_r = '0'))
then
if (pwrem <= G_W/8) then
pwrem <= (others => '0');
else
pwrem <= pwrem - G_W/8;
end if;
if (G_NPUB_DISABLE = 1) then
en_data <= '1';
else
en_npub <= '1';
end if;
bypass_fifo_wr <= '1';
if (wcount = CNT_NPUB_WORDS-1) then
pstate <= SP_WAIT_HDR;
wcount <= (others => '0');
if (G_NPUB_DISABLE = 0) then
set_npub_ready <= '1';
end if;
else
wcount <= wcount + 1;
end if;
end if;
when SP_WAIT_NSEC =>
if (pdi_valid = '1' and nsec_ready_r = '0') then
en_nsec <= '1';
if (G_NSEC_SIZE > G_W) then
if (wcount = (G_NSEC_SIZE/G_W)-1) then
pstate <= SP_WAIT_HDR;
set_nsec_ready <= '1';
else
wcount <= wcount + 1;
end if;
else
pstate <= SP_WAIT_HDR;
set_nsec_ready <= '1';
end if;
end if;
when SP_INIT_KEYAK0 =>
if (key_needs_update_r = '1' and key_ready_r = '1') then
key_updated_int <= '1';
pstate <= SP_INIT_KEYAK1;
elsif (key_needs_update_r = '0') then
pstate <= SP_INIT_KEYAK1;
end if;
when SP_INIT_KEYAK1 =>
sel_input <= "100";
en_data <= '1';
wcount <= wcount + 1;
pstate <= SP_INIT_KEYAK2;
when SP_INIT_KEYAK2 =>
sel_input <= "101";
en_data <= '1';
wcount <= wcount + 1;
pstate <= SP_WAIT_DATA;
when SP_LOAD_SPECIAL_AD =>
en_data <= '1';
sel_blank_pdi <= '1';
if (G_PAD = 1 and wcount = 0) then
pad_enable <= '1';
pad_done <= '1';
pad_eot <= p_eot;
pad_eoi <= p_eoi;
pad_type_ad <= is_ad_r;
end if;
if (wcount = CNT_DATA_WORDS-1) then
p_size_r <= p_size_r - G_DBLK_SIZE/8;
size_dword <= (others => '0');
bdi_size <= (others => '0');
wcount <= (others => '0');
is_ready_r <= '1';
is_nodata_r <= '1';
is_eot_r <= '1';
pstate <= SP_WAIT_SPECIAL_AD_READ;
else
wcount <= wcount + 1;
end if;
when SP_WAIT_SPECIAL_AD_READ =>
if (bdi_read = '1') then
is_ready_r <= '0';
is_eot_r <= '0';
is_eoi_r <= '0';
is_ad_r <= '0';
is_nodata_r <= '0';
is_extra_block <= '0';
pad_done <= '0';
if (p_reg_stype = ST_NPUB) then
pstate <= SP_WAIT_INSTR;
bdi_proc <= '0';
elsif (p_reg_stype = ST_AD) then
pstate <= SP_WAIT_HDR;
else
pstate <= SP_WAIT_DATA;
end if;
end if;
when SP_WAIT_DATA =>
if (((is_ad_r = '1' or (is_nsec_r = '1' and G_NSEC_ENABLE = 1))
and bypass_fifo_full = '0' and pdi_valid = '1')
or (is_ad_r = '0' and pdi_valid = '1')
or (pwrem = 0 and p_eot = '1')
or (PARTIAL_LOAD = 1 and is_partial_data = '1'))
then
--! If remaining data word is 0, pad input block with 0
if (pwrem /= 0) then
if (is_ad_r = '1' and is_tag_r = '0') then
if (PARTIAL_LOAD = 0) then
bypass_fifo_wr <= '1';
elsif (PARTIAL_LOAD = 1 and
((wcount < total_words) or
(wcount = total_words and is_partial_data = '0')))
then
bypass_fifo_wr <= '1';
end if;
end if;
else
sel_blank_pdi <= '1';
end if;
--! Perform padding
if (G_PAD = 1) then
if (((PARTIAL_LOAD = 0 and p_eot = '1'
and pwrem < G_W/8 and pad_done = '0')
or (PARTIAL_LOAD = 1 and p_eot = '1'
and pwrem < G_W/8 and pad_done = '0'
and (wcount /= total_words or (wcount = total_words and is_partial_data = '0')))
or (G_REVERSE_DBLK = 1 and is_first_blk = '1'
and is_ad_r = '0' and remainder(G_BS_BYTES-1 downto 0) < G_DBLK_SIZE/8
and remainder(G_BS_BYTES-1 downto 0) /= 0 and is_decrypt_r = '1')))
then
if ((is_ad_r = '0' and G_PAD_D > 0) or
(is_ad_r = '1' and is_tag_r = '0' and G_PAD_AD > 0) or
(G_PAD_D > 0 and G_PAD_AD > 0))
then
pad_enable <= '1';
pad_done <= '1';
pad_eot <= p_eot;
pad_eoi <= p_eoi;
pad_type_ad <= is_ad_r;
end if;
end if;
end if;
if ((PARTIAL_LOAD = 1) and
((G_ABLK_SIZE = G_DBLK_SIZE and wcount = CNT_DATA_WORDS-1)
or (G_ABLK_SIZE /= G_DBLK_SIZE and wcount = total_words)))
then
if (is_partial_data = '0') then
if (pwrem <= G_W/8) then
pwrem <= (others => '0');
else
pwrem <= pwrem - G_W/8;
end if;
end if;
else
if (G_ABLK_SIZE = G_DBLK_SIZE) then
if (pwrem <= G_W/8) then
pwrem <= (others => '0');
else
pwrem <= pwrem - G_W/8;
end if;
else
if (wcount < total_words) then
if (pwrem <= G_W/8) then
pwrem <= (others => '0');
else
pwrem <= pwrem - G_W/8;
end if;
end if;
end if;
end if;
if (G_REVERSE_DBLK = 0) then
if (pwrem <= G_W/8) then
size_dword <= pwrem(log2_ceil(G_W/8) downto 0);
else
size_dword <= std_logic_vector(to_unsigned(G_W/8,log2_ceil(G_W/8)+1));
end if;
else
--! Special case for PRIMATEs-APE
if (is_ad_r = '1' and pwrem <= G_W/8) then
size_dword <= pwrem(log2_ceil(G_W/8) downto 0);
elsif (is_ad_r = '0' and is_first_blk = '1' and remainder(G_BS_BYTES-1 downto 0) < G_DBLK_SIZE/8 and remainder(G_BS_BYTES-1 downto 0) /= 0) then
size_dword <= remainder(log2_ceil(G_W/8) downto 0);
else
size_dword <= std_logic_vector(to_unsigned(G_W/8,log2_ceil(G_W/8)+1));
end if;
end if;
if (is_tag_r = '0') then
en_data <= '1';
if (wcount = CNT_DATA_WORDS-1) then
--! Handling case when AD_BLOCK /= Data_BLOCK
if (G_ABLK_SIZE /= G_DBLK_SIZE) then
if (is_ad_r = '1') then
p_size_r <= p_size_r - G_ABLK_SIZE/8;
else
p_size_r <= p_size_r - G_DBLK_SIZE/8;
end if;
else
if (G_KEYAK = 0) then
p_size_r <= p_size_r - G_DBLK_SIZE/8;
else
p_size_r <= p_size_r - (G_DBLK_SIZE/8 - 256/8);
end if;
end if;
wcount <= (others => '0');
--! Status signals and state transition
is_ready_r <= '1';
if (PARTIAL_LOAD = 1) then
en_last_word <= '1';
if ((pwrem <= (G_W/8)/2) and
(is_partial_data = '0'))
then
--! If it's decrypt and of type message, start loading tag segment
if (is_decrypt_r = '1' and p_eoi = '1') then
pstate <= SP_WAIT_HDR;
else
pstate <= SP_WAIT_DATA_READ;
end if;
else
pstate <= SP_WAIT_DATA_READ;
end if;
else
if ((G_REVERSE_DBLK = 0) or (is_decrypt_r = '0') or (is_ad_r = '1')) then
--! Case when Reverse data block is required
if (pwrem < G_W/8) then
bdi_size <= p_size_r(G_BS_BYTES-1 downto 0);
else
bdi_size <= (others => '0');
end if;
else
if (is_first_blk = '1' and is_ad_r = '0') then
if (remainder(G_BS_BYTES-1 downto 0) < G_DBLK_SIZE/8) then
bdi_size <= remainder(G_BS_BYTES-1 downto 0);
else
bdi_size <= (others => '0');
end if;
is_first_blk <= '0';
else
bdi_size <= (others => '0');
end if;
end if;
if (pwrem <= G_W/8) then
if (G_PAD = 1 and ((G_PAD_D > 1 and needs_extra_block = '1' and is_ad_r = '0') or (G_PAD_AD > 1 and needs_extra_block_ad = '1'))) then
is_eot_r <= '0';
else
is_eot_r <= p_eot;
end if;
--! If it's decrypt and of type message, start loading tag segment
if (is_decrypt_r = '1' and is_ad_r = '0' and p_eot = '1') then
is_eoi_r <= p_eot;
if ((G_REVERSE_DBLK = 1 and G_CIPHERTEXT_MODE = 2) and p_eoi = '1') then
pstate <= SP_WAIT_MSG_AUTH;
elsif (G_PAD = 1 and (G_PAD_D > 2 and needs_extra_block = '1')) then
pstate <= SP_WAIT_DATA_READ;
else
pstate <= SP_WAIT_HDR;
end if;
else
if (G_PAD = 1 and ((G_PAD_D > 1 and needs_extra_block = '1') or (G_PAD_AD > 1 and needs_extra_block_ad = '1'))) then
is_eoi_r <= '0';
else
is_eoi_r <= p_eoi;
end if;
pstate <= SP_WAIT_DATA_READ;
end if;
else
pstate <= SP_WAIT_DATA_READ;
end if;
end if;
else
wcount <= wcount + 1;
end if;
if (PARTIAL_LOAD = 1) then
--! Special case when (G_DBLK_SIZE mod G_W = G_W/2)
if (wcount < total_words) then
if (pwrem <= (G_W/8)/2) then
is_partial_data <= '0';
end if;
elsif (wcount = total_words) then
if ((is_partial_data = '0')
and ((pwrem > ((G_ABLK_SIZE/8) mod (G_W/8)) and is_ad_r = '1')
or (pwrem > ((G_DBLK_SIZE/8) mod (G_W/8)) and is_ad_r = '0')))
then
is_partial_data <= '1';
else
is_partial_data <= '0';
end if;
if (((pwrem < (G_W/8)/2 and is_partial_data = '0')
or (pwrem = 0 and is_partial_data = '1'))
and ((is_ad_r = '1' and p_size_r(G_BS_BYTES-1 downto 0) /= G_ABLK_SIZE/8)
or (is_ad_r = '0' and p_size_r(G_BS_BYTES-1 downto 0) /= G_DBLK_SIZE/8)))
then
bdi_size <= p_size_r(G_BS_BYTES-1 downto 0);
else
bdi_size <= (others => '0');
end if;
if (is_partial_data = '0' and pwrem <= (G_W/8)/2) or
(is_partial_data = '1' and pwrem = 0 )
then
is_eot_r <= p_eot;
is_eoi_r <= p_eoi;
else
is_eot_r <= '0';
end if;
end if;
if (wcount < total_words) then
if (is_partial_data = '0') then
sel_input <= "000"; --! D[HI] & D[LO]
else
if (pwrem = 0) then
sel_input <= "011"; --! D[LO] & 00..
else
sel_input <= "010"; --! D[LO] & D[HI]
end if;
end if;
elsif (wcount = total_words) then
if (is_partial_data = '0') then
sel_input <= "001"; --! D[HI] & 00..
else
sel_input <= "011"; --! D[LO] & 00..
end if;
else
sel_input <= "111"; --! "00..."
end if;
end if;
else
if (bdi_read = '1') then
is_ready_r <= '0';
end if;
en_exp_tag <= '1';
if (wcount = CNT_TAG_WORDS-1) then
wcount <= (others => '0');
if (p_eoi = '1') then
pstate <= SP_WAIT_MSG_AUTH;
else
pstate <= SP_WAIT_HDR;
end if;
exp_tag_ready_r <= '1';
else
wcount <= wcount + 1;
end if;
end if;
end if;
when SP_WAIT_DATA_READ =>
wcount <= (others => '0');
if (bdi_read = '1') then
is_ready_r <= '0';
is_eot_r <= '0';
is_eoi_r <= '0';
is_nodata_r <= '0';
if (pwrem = 0) then
if (G_PAD = 1
and (G_PAD_AD > 1 or G_PAD_D > 1)
and (needs_extra_block = '1' or needs_extra_block_ad = '1')) then
--! Special cases
if (needs_extra_block = '1') then
pstate <= SP_WAIT_DATA;
needs_extra_block <= '0';
is_ad_r <= '0';
elsif (needs_extra_block_ad = '1') then
pstate <= SP_LOAD_SPECIAL_AD;
needs_extra_block_ad <= '0';
is_ad_r <= '1';
end if;
is_extra_block <= '1';
is_nodata_r <= '1';
pad_done <= '0';
elsif (PARTIAL_LOAD = 1 and is_partial_data = '1') then
pstate <= SP_WAIT_DATA;
else
if (G_PAD = 1 and (G_PAD_AD > 1 or G_PAD_D > 1)) then
is_extra_block <= '0';
end if;
if (p_eoi = '1') then
if (is_decrypt_r = '1') then --! If AEAD_DECRYPT, there must be a tag segment after last message segment
if (tag_passed_r = '1') then
pstate <= SP_WAIT_MSG_AUTH;
else
pstate <= SP_WAIT_HDR;
end if;
else
pstate <= SP_WAIT_INSTR;
bdi_proc <= '0';
end if;
else
pstate <= SP_WAIT_HDR;
end if;
end if;
else
if (G_PAD = 1
and (G_PAD_AD = 2 or G_PAD_AD = 4)
and is_extra_block = '1'
and is_ad_r = '1')
then --! Empty AD
is_ad_r <= '0';
is_nodata_r <= '0';
end if;
pstate <= SP_WAIT_DATA;
end if;
end if;
when SP_WAIT_MSG_AUTH =>
if (msg_auth_done = '1') then
pstate <= SP_WAIT_INSTR;
bdi_proc <= '0';
is_ready_r <= '0';
is_eot_r <= '0';
is_eoi_r <= '0';
elsif (bdi_read = '1') then
is_ready_r <= '0';
end if;
when SP_ERROR =>
pstate <= SP_ERROR;
end case;
end if;
end if;
end process;
--! Unregistered control signals (Required for correct timing)
pdi_ready <= '1' when pdi_valid = '1' and (
(pstate = SP_WAIT_INSTR and bypass_fifo_full = '0') or
(pstate = SP_WAIT_HDR and bypass_fifo_full = '0') or
(pstate = SP_WAIT_NPUB and (npub_ready_r = '0' or G_NPUB_DISABLE = 1) and bypass_fifo_full = '0') or
(pstate = SP_WAIT_NSEC and G_NSEC_ENABLE = 1 and nsec_ready_r = '0') or
(pstate = SP_LOADLEN and G_LOADLEN_ENABLE = 1) or
(pstate = SP_WAIT_DATA and PARTIAL_LOAD = 0
and (((is_ad_r = '1' or (is_nsec_r = '1' and G_NSEC_ENABLE = 1)) and bypass_fifo_full = '0' and pwrem /= 0)
or (is_ad_r = '0' and pwrem /= 0))) or
(pstate = SP_WAIT_DATA and PARTIAL_LOAD = 1 and
(wcount < total_words or (wcount = total_words and is_partial_data = '0')) and
(((is_ad_r = '1' or (is_nsec_r = '1' and G_NSEC_ENABLE = 1)) and bypass_fifo_full = '0' and pwrem /= 0) or
(is_ad_r = '0' and pwrem /= 0)))
) else '0';
gLoadLenDisable:
if (G_LOADLEN_ENABLE /= 1) generate
en_len_a <= '1' when (pstate = SP_READ_HDR and p_stype = ST_AD) else '0';
en_len_d <= '1' when (pstate = SP_READ_HDR and (p_stype = ST_MESSAGE or p_stype = ST_CIPHER)) else '0';
end generate;
--! Division required for reverse block mode
gRB:
if (G_REVERSE_DBLK = 1) generate
remainder <= std_logic_vector(unsigned(p_size_r) MOD to_unsigned(G_DBLK_SIZE/8, CNTR_WIDTH));
end generate;
--! Control for secret data
p_sstate:
process( clk )
begin
if rising_edge( clk ) then
if rst = '1' then
sstate <= SS_WAIT_INSTR;
if (G_RDKEY_ENABLE = 1) then
set_rdkey_ready <= '0';
else
set_key_ready <= '0';
end if;
error_sdi <= (others => '0');
else
if (G_RDKEY_ENABLE = 1) then
en_rdkey <= '0';
set_rdkey_ready <= '0';
else
en_key <= '0';
set_key_ready <= '0';
end if;
case sstate is
when SS_WAIT_INSTR =>
if (sdi_valid = '1') then
sstate <= SS_READ_INSTR;
end if;
when SS_READ_INSTR =>
if (s_opcode /= OP_LD_KEY and s_opcode /= OP_LD_RKEY) then
sstate <= SS_WAIT_INSTR;
error_sdi(1) <= '1'; --! Unsupported opcode
else
sstate <= SS_WAIT_HDR;
end if;
when SS_WAIT_HDR =>
if (sdi_valid = '1'
and ((G_RDKEY_ENABLE = 0 and key_ready_r = '0') or
(G_RDKEY_ENABLE = 1 and rdkey_ready_r = '0')))
then
sstate <= SS_READ_HDR;
end if;
when SS_READ_HDR =>
swcount <= (others => '0');
key_id_r <= s_key_id;
if (G_RDKEY_ENABLE = 0 and (s_stype = ST_KEY and s_size = G_KEY_SIZE/8)) then
sstate <= SS_WAIT_KEY;
elsif (G_RDKEY_ENABLE = 1 and s_stype = ST_RDKEY) then
sstate <= SS_WAIT_RDKEY;
swrem <= sdi(SWREMSIZE+SWSIZE-1 downto SWSIZE)+nway_or(sdi(SWSIZE-1 downto 0));
else
error_sdi(7) <= '1'; --! Segment error
sstate <= SS_WAIT_INSTR;
end if;
when SS_WAIT_KEY =>
if (sdi_valid = '1') then
en_key <= '1';
if (swcount = (G_KEY_SIZE/G_SW)-1) then
sstate <= SS_DELAY;
set_key_ready <= '1';
else
swcount <= swcount + 1;
end if;
end if;
when SS_DELAY =>
sstate <= SS_WAIT_INSTR;
when SS_WAIT_RDKEY =>
if (sdi_valid = '1') then
en_rdkey <= '1';
swrem <= swrem - 1;
if (swcount = (G_KEY_SIZE/G_SW)-1) then
set_rdkey_ready <= '1';
sstate <= SS_WAIT_RDKEY_READ;
else
swcount <= swcount + 1;
end if;
end if;
when SS_WAIT_RDKEY_READ =>
swcount <= (others => '0');
if (rdkey_read = '1') then
if (swrem = 0) then
sstate <= SS_WAIT_INSTR;
else
sstate <= SS_WAIT_RDKEY;
end if;
end if;
end case;
end if;
end if;
end process;
sdi_ready <= '1' when sdi_valid = '1' and (
(sstate = SS_WAIT_INSTR) or
(sstate = SS_WAIT_HDR and ((key_ready_r = '0' and G_RDKEY_ENABLE = 0) or (rdkey_ready_r = '0' and G_RDKEY_ENABLE = 1))) or
(sstate = SS_WAIT_KEY) or
(sstate = SS_WAIT_RDKEY and rdkey_read = '1')
) else '0';
end behavior;
| gpl-3.0 |
mgiacomini/mips-monocycle | ADD.vhd | 2 | 1366 | -- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- Complete implementation of Patterson and Hennessy single cycle MIPS processor
-- Copyright (C) 2015 Darci Luiz Tomasi Junior
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, version 3.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- Engineer: Darci Luiz Tomasi Junior
-- E-mail: [email protected]
-- Date : 08/07/2015 - 18:58
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
ENTITY ADD IS
PORT(
IN_A : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
IN_B : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
OUT_A : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END ADD;
ARCHITECTURE ARC_ADD OF ADD IS
BEGIN
OUT_A <= STD_LOGIC_VECTOR (UNSIGNED(IN_A ) + UNSIGNED(IN_B));
END ARC_ADD;
| gpl-3.0 |
michaelfivez/ascon_hardware_implementation | ascon12864_serialized/API_plus_CipherCore/AEAD_pkg.vhd | 9 | 7800 | -------------------------------------------------------------------------------
--! @file AEAD_pkg.vhd
--! @brief Package used for authenticated encyryption
--! @project CAESAR Candidate Evaluation
--! @author Ekawat (ice) Homsirikamol
--! @copyright Copyright (c) 2015 Cryptographic Engineering Research Group
--! ECE Department, George Mason University Fairfax, VA, U.S.A.
--! All rights Reserved.
--! @license This project is released under the GNU Public License.
--! The license and distribution terms for this file may be
--! found in the file LICENSE in this distribution or at
--! http://www.gnu.org/licenses/gpl-3.0.txt
--! @note This is publicly available encryption source code that falls
--! under the License Exception TSU (Technology and software-
--! —unrestricted)
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package AEAD_pkg is
--! Opcde
constant OP_ENC : std_logic_vector(4 -1 downto 0) := "0000"; --! Encryption only operation
constant OP_DEC : std_logic_vector(4 -1 downto 0) := "0001"; --! Decryption only operation
constant OP_AE_ENC : std_logic_vector(4 -1 downto 0) := "0010"; --! Authenticated Encryption operation
constant OP_AE_DEC : std_logic_vector(4 -1 downto 0) := "0011"; --! Authenticated Decryption operation
constant OP_LD_KEY : std_logic_vector(4 -1 downto 0) := "0100"; --! Load Key (Used by Secret Data Input)
constant OP_LD_RKEY : std_logic_vector(4 -1 downto 0) := "0101"; --! Load Round Key (Used by Public Data Input)
constant OP_ACT_KEY : std_logic_vector(4 -1 downto 0) := "0111"; --! Activate Key (Used by Public Data Input)
constant OP_AE_PASS : std_logic_vector(4 -1 downto 0) := "1110"; --! Authenticated Decryption Pass
constant OP_AE_FAIL : std_logic_vector(4 -1 downto 0) := "1111"; --! Authenticated Decryption Fail
--! Opcode extension for multi-mode operations
constant OP_MAC : std_logic_vector(4 -1 downto 0) := "0110"; --! MAC operation
constant OP_HASH : std_logic_vector(4 -1 downto 0) := "0111"; --! Hash operation
constant OP_PRNG : std_logic_vector(4 -1 downto 0) := "1000"; --! PRNG operation
--! Segment Type Encoding
constant ST_INSTR : std_logic_vector(4 -1 downto 0) := "0000"; --! Instruction type
constant ST_INIT : std_logic_vector(4 -1 downto 0) := "0000"; --! Initialization type
constant ST_NPUB : std_logic_vector(4 -1 downto 0) := "0001"; --! NPUB Type
constant ST_AD : std_logic_vector(4 -1 downto 0) := "0010"; --! Authenticated Data type
constant ST_MESSAGE : std_logic_vector(4 -1 downto 0) := "0011"; --! Message type
constant ST_CIPHER : std_logic_vector(4 -1 downto 0) := "0100"; --! Cipher type
constant ST_TAG : std_logic_vector(4 -1 downto 0) := "0101"; --! Tag type
constant ST_KEY : std_logic_vector(4 -1 downto 0) := "0110"; --! Key type
constant ST_RDKEY : std_logic_vector(4 -1 downto 0) := "0111"; --! Key type
constant ST_NSEC : std_logic_vector(4 -1 downto 0) := "1000"; --! Secret message number type
constant ST_NSEC_CIPH: std_logic_vector(4 -1 downto 0) := "1001"; --! Encrypted secret message number type
constant ST_LEN : std_logic_vector(4 -1 downto 0) := "1100"; --! Length type
--! Length specifier
constant LEN_MSG_ID : integer := 8; --! Length of message ID
constant LEN_KEY_ID : integer := 8; --! Length of Key ID
constant LEN_OPCODE : integer := 4; --! Length of opcode
constant LEN_SMT_HDR : integer := 4; --! Length of segment header
--! Other
constant CTR_SIZE_LIM : integer := 16; --! Limit to the segment counter size
--! Functions
function maximum(a, b: integer) return integer; --! Get maximum
function nway_or( x : std_logic_vector) return std_logic; --! Or all bits of an input
function get_words(size: integer; iowidth:integer) return integer; --! Calculate the number of I/O words for a particular size
function get_width(size: integer; iowidth: integer) return integer; --! Calculate the width of register (used when not divisible by I/O size, i.e. NPUB = 96 with I/O = 64-bit)
function get_cntr_width(iowidth: integer) return integer; --! Calculate the length of size register (used when I/O size < counter limit size)
function log2_ceil (N: natural) return natural; --! Log(2) ceil
function isNotDivisible(xx: integer; yy: integer) return integer; --! Determine a whether a value is divisible
end AEAD_pkg;
package body AEAD_pkg is
--! maximum
function maximum(a, b: integer) return integer is
begin
if (a > b) then
return a;
else
return b;
end if;
end function maximum;
--! Or gate to all the input
function nway_or( x : std_logic_vector) return std_logic is
variable y : std_logic;
begin
y := x(0);
for i in x'low+1 to x'high loop
y := y or x(i);
end loop;
return y;
end function nway_or;
--! Calculate the number of words
function get_words(size: integer; iowidth:integer) return integer is
begin
if (size mod iowidth) > 0 then
return size/iowidth + 1;
else
return size/iowidth;
end if;
end function get_words;
--! Calculate the expected width
function get_width(size: integer; iowidth: integer) return integer is
begin
if (iowidth >= size) then
return size;
else
return (size mod iowidth)+size;
end if;
end function get_width;
--! Get the size of the public data
function get_cntr_width(iowidth: integer) return integer is
begin
if iowidth-16 >= CTR_SIZE_LIM then
return CTR_SIZE_LIM;
else
return iowidth-16;
end if;
end function get_cntr_width;
--! Log of base 2
function log2_ceil (N: natural) return natural is
begin
if ( N = 0 ) then
return 0;
elsif N <= 2 then
return 1;
else
if (N mod 2 = 0) then
return 1 + log2_ceil(N/2);
else
return 1 + log2_ceil((N+1)/2);
end if;
end if;
end function log2_ceil;
function isNotDivisible(xx: integer; yy: integer) return integer is
begin
if (xx MOD yy) /= 0 then
return 1;
else
return 0;
end if;
end function isNotDivisible;
end package body AEAD_pkg;
| gpl-3.0 |
michaelfivez/ascon_hardware_implementation | ascon12864_unrolled6/Kernel/Ascon_block_control.vhd | 1 | 6626 | -------------------------------------------------------------------------------
--! @project Unrolled (6) hardware implementation of Asconv1286
--! @author Michael Fivez
--! @license This project is released under the GNU Public License.
--! The license and distribution terms for this file may be
--! found in the file LICENSE in this distribution or at
--! http://www.gnu.org/licenses/gpl-3.0.txt
--! @note This is an hardware implementation made for my graduation thesis
--! at the KULeuven, in the COSIC department (year 2015-2016)
--! The thesis is titled 'Energy efficient hardware implementations of CAESAR submissions',
--! and can be found on the COSIC website (www.esat.kuleuven.be/cosic/publications)
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity Ascon_StateUpdate_control is
port(
Clk : in std_logic; -- Clock
Reset : in std_logic; -- Reset (synchronous)
-- Control signals
RoundNr : out std_logic; -- biggest round is 12
sel1,sel2,sel3,sel4 : out std_logic_vector(1 downto 0);
sel0 : out std_logic_vector(2 downto 0);
selout : out std_logic;
Reg0En,Reg1En,Reg2En,Reg3En,Reg4En,RegOutEn : out std_logic;
ActivateGen : out std_logic;
GenSize : out std_logic_vector(2 downto 0);
-- External control signals
Start : in std_logic;
Mode : in std_logic_vector(3 downto 0);
Size : in std_logic_vector(2 downto 0); -- only matters for last block decryption
Busy : out std_logic
);
end entity Ascon_StateUpdate_control;
architecture structural of Ascon_StateUpdate_control is
begin
-----------------------------------------
------ The Finite state machine --------
-----------------------------------------
-- Modes: initialization, associative data, encryption, decryption, tag generation, final encryption, final decryption, seperation constant
-- 0010 0000 0110 0100 0001 0111 0101, 0011
-- case1 1000, case2 1001
fsm: process(Clk, Reset) is
type state_type is (IDLE,LOADNEW,CRYPT,TAG);
variable CurrState : state_type := IDLE;
variable RoundNrVar : std_logic_vector(1 downto 0);
begin
if Clk'event and Clk = '1' then
-- default values
sel0 <= "000";
sel1 <= "00";
sel2 <= "00";
sel3 <= "00";
sel4 <= "00";
selout <= '0';
Reg0En <= '0';
Reg1En <= '0';
Reg2En <= '0';
Reg3En <= '0';
Reg4En <= '0';
RegOutEn <= '0';
ActivateGen <= '0';
GenSize <= "000";
Busy <= '0';
if Reset = '1' then -- synchronous reset active high
-- registers used by fsm:
RoundNrVar := "00";
CurrState := IDLE;
else
FSMlogic : case CurrState is
when IDLE =>
if Start = '1' then
Busy <= '1';
if Mode = "0000" then -- AD mode
RoundNrVar := "11"; -- so starts at 0 next cycle
-- set Sel and Enables signal (Xor with DataIn)
sel0 <= "010";
Reg0En <= '1';
CurrState := CRYPT;
elsif Mode = "0100" then -- Decryption mode
RoundNrVar := "11"; -- so starts at 0 next cycle
-- set Sel and Enables signal (Generate output and xor state)
ActivateGen <= '1';
sel0 <= "010";
Reg0En <= '1';
RegOutEn <= '1';
CurrState := CRYPT;
elsif Mode = "0110" then -- Encryption
RoundNrVar := "11"; -- so starts at 0 next cycle
-- set Sel and Enables signal (Generate output and xor state)
sel0 <= "010";
Reg0En <= '1';
RegOutEn <= '1';
CurrState := CRYPT;
elsif Mode = "0001" then -- Tag mode
RoundNrVar := "11"; -- so starts at 0 next cycle
-- set Sel and Enables signal (XOR middle with key)
sel1 <= "10";
sel2 <= "11";
Reg1En <= '1';
Reg2En <= '1';
CurrState := TAG;
elsif Mode = "0111" then -- Last block encryption
-- set Sel and Enables signal (Generate output and xor state)
sel0 <= "010";
Reg0En <= '1';
RegOutEn <= '1';
CurrState := IDLE;
elsif Mode = "0101" then -- Last block decryption
-- set Sel and Enables signal (Generate output and xor state)
ActivateGen <= '1';
GenSize <= Size;
sel0 <= "010";
Reg0En <= '1';
RegOutEn <= '1';
CurrState := IDLE;
elsif Mode = "0011" then -- Seperation constant
sel4 <= "11";
Reg4En <= '1';
CurrState := IDLE;
elsif Mode = "0010" then -- Initialization mode
RoundNrVar := "11"; -- so starts at 0 next cycle
-- set Sel and Enables signal (Load in key and IV)
sel0 <= "001";
sel1 <= "01";
sel2 <= "01";
sel3 <= "01";
sel4 <= "01";
Reg0En <= '1';
Reg1En <= '1';
Reg2En <= '1';
Reg3En <= '1';
Reg4En <= '1';
CurrState := LOADNEW;
elsif Mode = "1000" then -- case1
sel0 <= "100";
Reg0En <= '1';
CurrState := IDLE;
else -- case2
sel0 <= "100";
Reg0En <= '1';
RoundNrVar := "11"; -- so starts at 0 next cycle
CurrState := CRYPT;
end if;
else
Busy <= '0';
CurrState := IDLE;
end if;
when LOADNEW =>
if RoundNrVar = "01" then -- first foesn't play a role, it's just to keep track in this if function
-- set Sel and Enables signal (Xor at the end)
sel3 <= "10";
sel4 <= "10";
Reg3En <= '1';
Reg4En <= '1';
CurrState := IDLE;
Busy <= '0';
else
RoundNrVar := std_logic_vector(unsigned(RoundNrVar) + 1);
-- set Sel and Enables signal (execute a round)
Reg0En <= '1';
Reg1En <= '1';
Reg2En <= '1';
Reg3En <= '1';
Reg4En <= '1';
CurrState := LOADNEW;
Busy <= '1';
end if;
when CRYPT =>
RoundNrVar := "00";
Reg0En <= '1';
Reg1En <= '1';
Reg2En <= '1';
Reg3En <= '1';
Reg4En <= '1';
CurrState := IDLE;
Busy <= '0';
when TAG =>
if RoundNrVar = "01" then
-- set Sel and Enables signal (connect tag to output)
selout <= '1';
RegOutEn <= '1';
CurrState := IDLE;
Busy <= '0';
else
RoundNrVar := std_logic_vector(unsigned(RoundNrVar) + 1);
-- set Sel and Enables signal (execute a round)
Reg0En <= '1';
Reg1En <= '1';
Reg2En <= '1';
Reg3En <= '1';
Reg4En <= '1';
CurrState := TAG;
Busy <= '1';
end if;
end case FSMlogic;
RoundNr <= RoundNrVar(0);
end if;
end if;
end process fsm;
end architecture structural;
| gpl-3.0 |
mgiacomini/mips-monocycle | TB_MAIN_PROCESSOR.vhd | 2 | 2119 | --------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17:35:44 08/06/2015
-- Design Name:
-- Module Name: E:/Programas_FPGA/SYNGLE_CYCLE_V3/TB_MAIN_PROCESSOR.vhd
-- Project Name: SYNGLE_CYCLE_V3
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: MAIN_PROCESSOR
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
USE ieee.numeric_std.ALL;
ENTITY TB_MAIN_PROCESSOR IS
END TB_MAIN_PROCESSOR;
ARCHITECTURE behavior OF TB_MAIN_PROCESSOR IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT MAIN_PROCESSOR
PORT(
CLK : IN std_logic;
RESET : IN std_logic
);
END COMPONENT;
--Inputs
signal CLK : std_logic := '0';
signal RESET : std_logic := '0';
-- Clock period definitions
constant CLK_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: MAIN_PROCESSOR PORT MAP (
CLK => CLK,
RESET => RESET
);
-- Clock process definitions
CLK_process :process
begin
CLK <= '0';
wait for CLK_period/2;
CLK <= '1';
wait for CLK_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
RESET <= '1';
wait for 10 ns;
RESET <= '0';
WAIT;
end process;
END;
| gpl-3.0 |
michaelfivez/ascon_hardware_implementation | ascon128128_unrolled2/Kernel/Sbox.vhd | 1 | 3941 | -------------------------------------------------------------------------------
--! @project Unrolled (factor 2) hardware implementation of Asconv128128
--! @author Michael Fivez
--! @license This project is released under the GNU Public License.
--! The license and distribution terms for this file may be
--! found in the file LICENSE in this distribution or at
--! http://www.gnu.org/licenses/gpl-3.0.txt
--! @note This is an hardware implementation made for my graduation thesis
--! at the KULeuven, in the COSIC department (year 2015-2016)
--! The thesis is titled 'Energy efficient hardware implementations of CAESAR submissions',
--! and can be found on the COSIC website (www.esat.kuleuven.be/cosic/publications)
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity Sbox is
port(
X0In : in std_logic_vector(63 downto 0);
X1In : in std_logic_vector(63 downto 0);
X2In : in std_logic_vector(63 downto 0);
X3In : in std_logic_vector(63 downto 0);
X4In : in std_logic_vector(63 downto 0);
RoundNr : in std_logic_vector(3 downto 0);
X0Out : out std_logic_vector(63 downto 0);
X1Out : out std_logic_vector(63 downto 0);
X2Out : out std_logic_vector(63 downto 0);
X3Out : out std_logic_vector(63 downto 0);
X4Out : out std_logic_vector(63 downto 0));
end entity Sbox;
architecture structural of Sbox is
begin
Sbox: process(X0In,X1In,X2In,X3In,X4In,RoundNr) is
-- Procedure for 5-bit Sbox
procedure doSboxPart (
variable SboxPartIn : in std_logic_vector(4 downto 0);
variable SboxPartOut : out std_logic_vector(4 downto 0)) is
-- Temp variable
variable SboxPartTemp : std_logic_vector(17 downto 0);
begin
-- Sbox Interconnections
SboxPartTemp(0) := SboxPartIn(0) xor SboxPartIn(4);
SboxPartTemp(1) := SboxPartIn(2) xor SboxPartIn(1);
SboxPartTemp(2) := SboxPartIn(4) xor SboxPartIn(3);
SboxPartTemp(3) := not SboxPartTemp(0);
SboxPartTemp(4) := not SboxPartIn(1);
SboxPartTemp(5) := not SboxPartTemp(1);
SboxPartTemp(6) := not SboxPartIn(3);
SboxPartTemp(7) := not SboxPartTemp(2);
SboxPartTemp(8) := SboxPartIn(1) and SboxPartTemp(3);
SboxPartTemp(9) := SboxPartTemp(1) and SboxPartTemp(4);
SboxPartTemp(10) := SboxPartIn(3) and SboxPartTemp(5);
SboxPartTemp(11) := SboxPartTemp(2) and SboxPartTemp(6);
SboxPartTemp(12) := SboxPartTemp(0) and SboxPartTemp(7);
SboxPartTemp(13) := SboxPartTemp(0) xor SboxPartTemp(9);
SboxPartTemp(14) := SboxPartIn(1) xor SboxPartTemp(10);
SboxPartTemp(15) := SboxPartTemp(1) xor SboxPartTemp(11);
SboxPartTemp(16) := SboxPartIn(3) xor SboxPartTemp(12);
SboxPartTemp(17) := SboxPartTemp(2) xor SboxPartTemp(8);
SboxPartOut(0) := SboxPartTemp(13) xor SboxPartTemp(17);
SboxPartOut(1) := SboxPartTemp(13) xor SboxPartTemp(14);
SboxPartOut(2) := not SboxPartTemp(15);
SboxPartOut(3) := SboxPartTemp(15) xor SboxPartTemp(16);
SboxPartOut(4) := SboxPartTemp(17);
end procedure doSboxPart;
variable X2TempIn : std_logic_vector(63 downto 0);
variable TempIn,TempOut : std_logic_vector(4 downto 0);
begin
-- Xor with round constants
X2TempIn(3 downto 0) := X2In(3 downto 0) xor RoundNr;
X2TempIn(7 downto 4) := X2In(7 downto 4) xnor RoundNr;
X2TempIn(63 downto 8) := X2In(63 downto 8);
-- Apply 5-bit Sbox 64 times
for i in X0In'range loop
TempIn(0) := X0In(i);
TempIn(1) := X1In(i);
TempIn(2) := X2TempIn(i);
TempIn(3) := X3In(i);
TempIn(4) := X4In(i);
doSboxPart(TempIn,TempOut);
X0Out(i) <= TempOut(0);
X1Out(i) <= TempOut(1);
X2Out(i) <= TempOut(2);
X3Out(i) <= TempOut(3);
X4Out(i) <= TempOut(4);
end loop;
end process Sbox;
end architecture structural;
| gpl-3.0 |
michaelfivez/ascon_hardware_implementation | ascon128128_serialized/API_plus_CipherCore/AEAD_Core.vhd | 4 | 15540 | -------------------------------------------------------------------------------
--! @file AEAD_Core.vhd
--! @brief Authenticated encryption unit core template module.
--! User should modification to the default generics based on the
--! implemented cipher.
--! @project CAESAR Candidate Evaluation
--! @author Ekawat (ice) Homsirikamol
--! @copyright Copyright (c) 2015 Cryptographic Engineering Research Group
--! ECE Department, George Mason University Fairfax, VA, U.S.A.
--! All rights Reserved.
--! @license This project is released under the GNU Public License.
--! The license and distribution terms for this file may be
--! found in the file LICENSE in this distribution or at
--! http://www.gnu.org/licenses/gpl-3.0.txt
--! @note This is publicly available encryption source code that falls
--! under the License Exception TSU (Technology and software-
--! —unrestricted)
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity AEAD_Core is
generic (
G_W : integer := 32; --! Public data width (bits)
G_SW : integer := 32; --! Secret data width (bits)
G_NPUB_SIZE : integer := 128; --! IV or Nonce size (bits)
G_NSEC_ENABLE : integer := 0; --! Enable NSEC port
G_NSEC_SIZE : integer := 1; --! NSEC width (bits)
G_ABLK_SIZE : integer := 128; --! Authenticated Data Block size (bits)
G_DBLK_SIZE : integer := 128; --! Data Block size (bits)
G_KEY_SIZE : integer := 128; --! Key size (bits)
G_RDKEY_ENABLE : integer := 0; --! Enable rdkey port (also disables key port)
G_RDKEY_SIZE : integer := 1; --! Roundkey size (bits)
G_TAG_SIZE : integer := 128; --! Tag size (bits)
G_BS_BYTES : integer := 4; --! The number of bits required to hold block size expressed in bytes = log2_ceil(max(G_ABLK_SIZE,G_DBLK_SIZE)/8)
G_LOADLEN_ENABLE : integer := 0; --! Enable load length section
G_PAD : integer := 1; --! Enable padding
G_PAD_STYLE : integer := 1; --! Padding mode
G_PAD_AD : integer := 1; --! (G_PAD's sub option) Enable AD Padding
G_PAD_D : integer := 1; --! (G_PAD's sub option) Enable Data padding
G_CTR_AD_SIZE : integer := 16; --! Maximum AD len value
G_CTR_D_SIZE : integer := 16; --! Maximum data len value
G_PLAINTEXT_MODE : integer := 0; --! Plaintext Mode
G_CIPHERTEXT_MODE : integer := 0; --! Ciphertext mode
G_REVERSE_DBLK : integer := 0 --! Reverse block order (for message only)
);
port (
--! Global signals
clk : in std_logic;
rst : in std_logic;
--! Data in signals
pdi : in std_logic_vector(G_W -1 downto 0);
pdi_valid : in std_logic;
pdi_ready : out std_logic;
--! Key signals
sdi : in std_logic_vector(G_SW -1 downto 0);
sdi_valid : in std_logic;
sdi_ready : out std_logic;
--! Data out signals
do : out std_logic_vector(G_W -1 downto 0);
do_ready : in std_logic;
do_valid : out std_logic;
--! FIFO signals
bypass_fifo_wr : out std_logic;
bypass_fifo_rd : out std_logic;
bypass_fifo_full : in std_logic;
bypass_fifo_empty : in std_logic;
bypass_fifo_data : in std_logic_vector(G_W -1 downto 0);
aux_fifo_din : out std_logic_vector(G_W -1 downto 0);
aux_fifo_ctrl : out std_logic_vector(4 -1 downto 0);
aux_fifo_dout : in std_logic_vector(G_W -1 downto 0);
aux_fifo_status : in std_logic_vector(3 -1 downto 0)
);
end AEAD_Core;
-------------------------------------------------------------------------------
--! @brief Architecture definition of AEAD_Core
-------------------------------------------------------------------------------
architecture structure of AEAD_Core is
--! Signals from input processor
signal npub : std_logic_vector(G_NPUB_SIZE -1 downto 0);
signal nsec : std_logic_vector(G_NSEC_SIZE -1 downto 0);
signal key : std_logic_vector(G_KEY_SIZE -1 downto 0);
signal rdkey : std_logic_vector(G_RDKEY_SIZE -1 downto 0);
signal bdi : std_logic_vector(G_DBLK_SIZE -1 downto 0);
signal exp_tag : std_logic_vector(G_TAG_SIZE -1 downto 0);
signal len_a : std_logic_vector(G_CTR_AD_SIZE -1 downto 0);
signal len_d : std_logic_vector(G_CTR_D_SIZE -1 downto 0);
signal key_ready : std_logic;
signal key_updated : std_logic;
signal key_needs_update : std_logic;
signal rdkey_ready : std_logic;
signal rdkey_read : std_logic;
signal npub_ready : std_logic;
signal npub_read : std_logic;
signal nsec_ready : std_logic;
signal nsec_read : std_logic;
signal bdi_ready : std_logic;
signal bdi_proc : std_logic;
signal bdi_ad : std_logic;
signal bdi_nsec : std_logic;
signal bdi_pad : std_logic;
signal bdi_decrypt : std_logic;
signal bdi_eot : std_logic;
signal bdi_eoi : std_logic;
signal bdi_read : std_logic;
signal bdi_size : std_logic_vector(G_BS_BYTES -1 downto 0);
signal bdi_valid_bytes : std_logic_vector(G_DBLK_SIZE/8 -1 downto 0);
signal bdi_pad_loc : std_logic_vector(G_DBLK_SIZE/8 -1 downto 0);
signal bdi_nodata : std_logic;
signal exp_tag_ready : std_logic;
--! Signals to output processor
signal bdo_ready : std_logic;
signal bdo_write : std_logic;
signal bdo : std_logic_vector(G_DBLK_SIZE -1 downto 0);
signal bdo_size : std_logic_vector(G_BS_BYTES+1 -1 downto 0);
signal bdo_nsec : std_logic;
signal tag_ready : std_logic;
signal tag_write : std_logic;
signal tag : std_logic_vector(G_TAG_SIZE -1 downto 0);
signal msg_auth_done : std_logic;
signal msg_auth_valid : std_logic;
begin
u_input:
entity work.PreProcessor(structure)
generic map (
G_W => G_W ,
G_SW => G_SW ,
G_NPUB_SIZE => G_NPUB_SIZE ,
G_NSEC_ENABLE => G_NSEC_ENABLE ,
G_NSEC_SIZE => G_NSEC_SIZE ,
G_ABLK_SIZE => G_ABLK_SIZE ,
G_DBLK_SIZE => G_DBLK_SIZE ,
G_KEY_SIZE => G_KEY_SIZE ,
G_RDKEY_ENABLE => G_RDKEY_ENABLE ,
G_RDKEY_SIZE => G_RDKEY_SIZE ,
G_TAG_SIZE => G_TAG_SIZE ,
G_BS_BYTES => G_BS_BYTES ,
G_LOADLEN_ENABLE => G_LOADLEN_ENABLE ,
G_PAD => G_PAD ,
G_PAD_STYLE => G_PAD_STYLE ,
G_PAD_AD => G_PAD_AD ,
G_PAD_D => G_PAD_D ,
G_CTR_AD_SIZE => G_CTR_AD_SIZE ,
G_CTR_D_SIZE => G_CTR_D_SIZE ,
G_PLAINTEXT_MODE => G_PLAINTEXT_MODE ,
G_CIPHERTEXT_MODE => G_CIPHERTEXT_MODE,
G_REVERSE_DBLK => G_REVERSE_DBLK
)
port map (
clk => clk ,
rst => rst ,
--! External
pdi => pdi ,
pdi_valid => pdi_valid ,
pdi_ready => pdi_ready ,
sdi => sdi ,
sdi_valid => sdi_valid ,
sdi_ready => sdi_ready ,
--! Datapath
npub => npub ,
nsec => nsec ,
key => key ,
rdkey => rdkey ,
bdi => bdi ,
exp_tag => exp_tag ,
len_a => len_a ,
len_d => len_d ,
--! Controller
key_ready => key_ready ,
key_updated => key_updated ,
key_needs_update => key_needs_update ,
rdkey_ready => rdkey_ready ,
rdkey_read => rdkey_read ,
npub_ready => npub_ready ,
npub_read => npub_read ,
nsec_ready => nsec_ready ,
nsec_read => nsec_read ,
bdi_ready => bdi_ready ,
bdi_proc => bdi_proc ,
bdi_ad => bdi_ad ,
bdi_nsec => bdi_nsec ,
bdi_pad => bdi_pad ,
bdi_decrypt => bdi_decrypt ,
bdi_eot => bdi_eot ,
bdi_eoi => bdi_eoi ,
bdi_nodata => bdi_nodata ,
bdi_read => bdi_read ,
bdi_size => bdi_size ,
bdi_valid_bytes => bdi_valid_bytes ,
bdi_pad_loc => bdi_pad_loc ,
exp_tag_ready => exp_tag_ready ,
msg_auth_done => msg_auth_done ,
--! FIFO
bypass_fifo_wr => bypass_fifo_wr ,
bypass_fifo_full => bypass_fifo_full
);
u_cc:
entity work.CipherCore(structure)
generic map (
G_NPUB_SIZE => G_NPUB_SIZE ,
G_NSEC_SIZE => G_NSEC_SIZE ,
G_DBLK_SIZE => G_DBLK_SIZE ,
G_KEY_SIZE => G_KEY_SIZE ,
G_RDKEY_SIZE => G_RDKEY_SIZE ,
G_TAG_SIZE => G_TAG_SIZE ,
G_BS_BYTES => G_BS_BYTES ,
G_CTR_AD_SIZE => G_CTR_AD_SIZE ,
G_CTR_D_SIZE => G_CTR_D_SIZE
)
port map (
clk => clk ,
rst => rst ,
npub => npub ,
nsec => nsec ,
key => key ,
rdkey => rdkey ,
bdi => bdi ,
exp_tag => exp_tag ,
len_a => len_a ,
len_d => len_d ,
key_ready => key_ready ,
key_updated => key_updated ,
key_needs_update => key_needs_update ,
rdkey_ready => rdkey_ready ,
rdkey_read => rdkey_read ,
npub_ready => npub_ready ,
npub_read => npub_read ,
nsec_ready => nsec_ready ,
nsec_read => nsec_read ,
bdi_ready => bdi_ready ,
bdi_proc => bdi_proc ,
bdi_ad => bdi_ad ,
bdi_nsec => bdi_nsec ,
bdi_pad => bdi_pad ,
bdi_decrypt => bdi_decrypt ,
bdi_eot => bdi_eot ,
bdi_eoi => bdi_eoi ,
bdi_read => bdi_read ,
bdi_size => bdi_size ,
bdi_valid_bytes => bdi_valid_bytes ,
bdi_pad_loc => bdi_pad_loc ,
bdi_nodata => bdi_nodata ,
exp_tag_ready => exp_tag_ready ,
msg_auth_done => msg_auth_done ,
bdo_write => bdo_write ,
bdo_ready => bdo_ready ,
bdo => bdo ,
bdo_size => bdo_size ,
bdo_nsec => bdo_nsec ,
tag_write => tag_write ,
tag_ready => tag_ready ,
tag => tag ,
msg_auth_valid => msg_auth_valid
);
u_output:
entity work.PostProcessor(structure)
generic map (
G_W => G_W ,
G_DBLK_SIZE => G_DBLK_SIZE ,
G_BS_BYTES => G_BS_BYTES ,
G_TAG_SIZE => G_TAG_SIZE ,
G_NSEC_ENABLE => G_NSEC_ENABLE ,
G_LOADLEN_ENABLE => G_LOADLEN_ENABLE ,
G_CIPHERTEXT_MODE => G_CIPHERTEXT_MODE,
G_REVERSE_DBLK => G_REVERSE_DBLK ,
G_PAD => G_PAD ,
G_PAD_D => G_PAD_D
)
port map (
--! Global
clk => clk ,
rst => rst ,
--! External
do => do ,
do_ready => do_ready ,
do_valid => do_valid ,
--! Processor
bdo_ready => bdo_ready ,
bdo_write => bdo_write ,
bdo_data => bdo ,
bdo_size => bdo_size ,
bdo_nsec => bdo_nsec ,
tag_ready => tag_ready ,
tag_write => tag_write ,
tag_data => tag ,
msg_auth_done => msg_auth_done ,
msg_auth_valid => msg_auth_valid ,
--! FIFOs
bypass_fifo_empty => bypass_fifo_empty,
bypass_fifo_rd => bypass_fifo_rd ,
bypass_fifo_data => bypass_fifo_data ,
aux_fifo_din => aux_fifo_din ,
aux_fifo_ctrl => aux_fifo_ctrl ,
aux_fifo_dout => aux_fifo_dout ,
aux_fifo_status => aux_fifo_status
);
end structure; | gpl-3.0 |
DreamIP/GPStudio | support/process/detectroi/hdl/detectroi_slave.vhd | 1 | 3615 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library std;
entity detectroi_slave is
generic (
CLK_PROC_FREQ : integer
);
port (
clk_proc : in std_logic;
reset_n : in std_logic;
---------------- dynamic parameters ports ---------------
status_reg_enable_bit : out std_logic;
in_size_reg_in_w_reg : out std_logic_vector(11 downto 0);
in_size_reg_in_h_reg : out std_logic_vector(11 downto 0);
--======================= Slaves ========================
------------------------- bus_sl ------------------------
addr_rel_i : in std_logic_vector(1 downto 0);
wr_i : in std_logic;
rd_i : in std_logic;
datawr_i : in std_logic_vector(31 downto 0);
datard_o : out std_logic_vector(31 downto 0)
);
end detectroi_slave;
architecture rtl of detectroi_slave is
-- Registers address
constant STATUS_REG_REG_ADDR : natural := 0;
constant IN_SIZE_REG_REG_ADDR : natural := 1;
-- Internal registers
signal status_reg_enable_bit_reg : std_logic;
signal in_size_reg_in_w_reg_reg : std_logic_vector (11 downto 0);
signal in_size_reg_in_h_reg_reg : std_logic_vector (11 downto 0);
begin
write_reg : process (clk_proc, reset_n)
begin
if(reset_n='0') then
status_reg_enable_bit_reg <= '0';
in_size_reg_in_w_reg_reg <= "000000000000";
in_size_reg_in_h_reg_reg <= "000000000000";
elsif(rising_edge(clk_proc)) then
if(wr_i='1') then
case to_integer(unsigned(addr_rel_i)) is
when STATUS_REG_REG_ADDR =>
status_reg_enable_bit_reg <= datawr_i(0);
when IN_SIZE_REG_REG_ADDR =>
in_size_reg_in_w_reg_reg <= datawr_i(11) & datawr_i(10) & datawr_i(9) & datawr_i(8) & datawr_i(7) & datawr_i(6) & datawr_i(5) & datawr_i(4) & datawr_i(3) & datawr_i(2) & datawr_i(1) & datawr_i(0);
in_size_reg_in_h_reg_reg <= datawr_i(27) & datawr_i(26) & datawr_i(25) & datawr_i(24) & datawr_i(23) & datawr_i(22) & datawr_i(21) & datawr_i(20) & datawr_i(19) & datawr_i(18) & datawr_i(17) & datawr_i(16);
when others=>
end case;
end if;
end if;
end process;
read_reg : process (clk_proc, reset_n)
begin
if(reset_n='0') then
datard_o <= (others => '0');
elsif(rising_edge(clk_proc)) then
if(rd_i='1') then
case to_integer(unsigned(addr_rel_i)) is
when STATUS_REG_REG_ADDR =>
datard_o <= "0000000000000000000000000000000" & status_reg_enable_bit_reg;
when IN_SIZE_REG_REG_ADDR =>
datard_o <= "0000" & in_size_reg_in_h_reg_reg(11) & in_size_reg_in_h_reg_reg(10) & in_size_reg_in_h_reg_reg(9) & in_size_reg_in_h_reg_reg(8) & in_size_reg_in_h_reg_reg(7) & in_size_reg_in_h_reg_reg(6) & in_size_reg_in_h_reg_reg(5) & in_size_reg_in_h_reg_reg(4) & in_size_reg_in_h_reg_reg(3) & in_size_reg_in_h_reg_reg(2) & in_size_reg_in_h_reg_reg(1) & in_size_reg_in_h_reg_reg(0) & "0000" & in_size_reg_in_w_reg_reg(11) & in_size_reg_in_w_reg_reg(10) & in_size_reg_in_w_reg_reg(9) & in_size_reg_in_w_reg_reg(8) & in_size_reg_in_w_reg_reg(7) & in_size_reg_in_w_reg_reg(6) & in_size_reg_in_w_reg_reg(5) & in_size_reg_in_w_reg_reg(4) & in_size_reg_in_w_reg_reg(3) & in_size_reg_in_w_reg_reg(2) & in_size_reg_in_w_reg_reg(1) & in_size_reg_in_w_reg_reg(0);
when others=>
datard_o <= (others => '0');
end case;
end if;
end if;
end process;
status_reg_enable_bit <= status_reg_enable_bit_reg;
in_size_reg_in_w_reg <= in_size_reg_in_w_reg_reg;
in_size_reg_in_h_reg <= in_size_reg_in_h_reg_reg;
end rtl;
| gpl-3.0 |
DreamIP/GPStudio | support/io/gps/hdl/gps_transmitter.vhd | 1 | 3432 | -----------------------------------------------------------------------
-- UART transmitter block. It sends the data to the GPS at the baud rate
-- defined. The data are sent following the Skytraq binary protocol.
-----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.gps_pkg.all;
entity gps_transmitter is
port(
clk : in std_logic;
reset : in std_logic;
enable : in std_logic;
start_flag : in std_logic;
done : out std_logic;
done_send : out std_logic;
count_bd : in unsigned(15 downto 0);
count_max : in unsigned(15 downto 0);
rst_count_bd : out std_logic;
TXD : out std_logic;
bytes : in unsigned(7 downto 0);
data_in : in std_logic_vector(7 downto 0)
);
end GPS_transmitter;
architecture RTL of gps_transmitter is
signal number_of_bits : unsigned(3 downto 0);
signal data_out_s : std_logic_vector(7 downto 0);
signal gngga : std_logic_vector(55 downto 0);
signal g_flag : std_logic;
signal data_to_send : std_logic_vector(7 downto 0);
signal count_bytes : unsigned(7 downto 0);
signal count_wait : unsigned(15 downto 0);
signal TXD_r : std_logic;
type type_state is (idle, start, data, wait_st, stop);
signal state : type_state;
begin
process(clk,reset,enable)
begin
if reset='0' then
rst_count_bd <='0';
number_of_bits <= x"0";
TXD_r <= '1';
state <= idle;
elsif clk'event and clk='1'then
if enable='1' then
case(state) is
----- Starting a communication
when(idle) =>
done <= '0';
done_send <= '0';
TXD_r <= '1';
if start_flag='1' then
state <= start;
data_to_send <= data_in;
rst_count_bd <= '1';
end if;
----- Writing start bit
when(start) =>
rst_count_bd <= '0';
data_to_send <= data_in;
done <= '0';
TXD_r <= '0';
if count_bd=count_max then
state <= data;
number_of_bits <= x"0";
end if;
----- Writing the 8 bits of data (LSB first)
when(data) =>
TXD_r <= data_to_send(0);
if count_bd=count_max then
data_to_send <= '0' & data_to_send(7 downto 1);
if number_of_bits= x"7" then
state <= stop;
else
number_of_bits <= number_of_bits +1;
end if;
end if;
----- Write stop bit
when(stop) =>
TXD_r <= '1';
if count_bd=count_max then
done <= '1';
number_of_bits <= x"0";
count_bytes <= count_bytes +1;
if count_bytes=bytes-1 then
if count_max=COUNT_BD_RATE_MAX then
count_wait <= x"0000";
else
count_wait <= x"7000";
end if;
state <= wait_st;
else
state <= start;
end if;
end if;
----- Full sequence sended, waiting before sending a new one
when wait_st =>
TXD_r <= '1';
if count_bd=count_max then
count_wait <= count_wait +1;
elsif count_wait=x"FFFF" then
state <= idle;
count_bytes <= x"00";
done_send <= '1';
end if;
when others =>
TXD_r <= '1';
state <= idle;
end case;
else
rst_count_bd <='0';
number_of_bits <= x"0";
TXD_r <= '1';
state <= idle;
end if;
end if;
end process;
TXD <= TXD_r;
end RTL;
| gpl-3.0 |
DougFirErickson/parallella-hw | fpga/ip/xilinx/fifo_async_103x16/fifo_async_103x16/fifo_async_103x16_funcsim.vhdl | 2 | 235213 | -- Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2014.3.1 (lin64) Build 1056140 Thu Oct 30 16:30:39 MDT 2014
-- Date : Wed Apr 8 20:38:45 2015
-- Host : parallella running 64-bit Ubuntu 14.04.2 LTS
-- Command : write_vhdl -force -mode funcsim
-- /home/aolofsson/Work_all/parallella-hw/fpga/vivado/junk/junk.srcs/sources_1/ip/fifo_async_103x16/fifo_async_103x16_funcsim.vhdl
-- Design : fifo_async_103x16
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z010clg400-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_async_103x16_dmem is
port (
Q : out STD_LOGIC_VECTOR ( 102 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
rd_clk : in STD_LOGIC;
I1 : in STD_LOGIC_VECTOR ( 0 to 0 );
wr_clk : in STD_LOGIC;
I2 : in STD_LOGIC_VECTOR ( 0 to 0 );
din : in STD_LOGIC_VECTOR ( 102 downto 0 );
ADDRA : in STD_LOGIC_VECTOR ( 3 downto 0 );
O3 : in STD_LOGIC_VECTOR ( 3 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_async_103x16_dmem : entity is "dmem";
end fifo_async_103x16_dmem;
architecture STRUCTURE of fifo_async_103x16_dmem is
signal p_0_out : STD_LOGIC_VECTOR ( 102 downto 0 );
signal NLW_RAM_reg_0_15_0_5_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_102_102_DOA_UNCONNECTED : STD_LOGIC_VECTOR ( 1 to 1 );
signal NLW_RAM_reg_0_15_102_102_DOB_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_102_102_DOC_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_102_102_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_12_17_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_18_23_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_24_29_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_30_35_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_36_41_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_42_47_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_48_53_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_54_59_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_60_65_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_66_71_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_6_11_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_72_77_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_78_83_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_84_89_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_90_95_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_96_101_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
begin
RAM_reg_0_15_0_5: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => ADDRA(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => ADDRA(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => ADDRA(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => O3(3 downto 0),
DIA(1 downto 0) => din(1 downto 0),
DIB(1 downto 0) => din(3 downto 2),
DIC(1 downto 0) => din(5 downto 4),
DID(1) => '0',
DID(0) => '0',
DOA(1 downto 0) => p_0_out(1 downto 0),
DOB(1 downto 0) => p_0_out(3 downto 2),
DOC(1 downto 0) => p_0_out(5 downto 4),
DOD(1 downto 0) => NLW_RAM_reg_0_15_0_5_DOD_UNCONNECTED(1 downto 0),
WCLK => wr_clk,
WE => I2(0)
);
RAM_reg_0_15_102_102: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => ADDRA(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => ADDRA(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => ADDRA(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => O3(3 downto 0),
DIA(1) => '0',
DIA(0) => din(102),
DIB(1) => '0',
DIB(0) => '0',
DIC(1) => '0',
DIC(0) => '0',
DID(1) => '0',
DID(0) => '0',
DOA(1) => NLW_RAM_reg_0_15_102_102_DOA_UNCONNECTED(1),
DOA(0) => p_0_out(102),
DOB(1 downto 0) => NLW_RAM_reg_0_15_102_102_DOB_UNCONNECTED(1 downto 0),
DOC(1 downto 0) => NLW_RAM_reg_0_15_102_102_DOC_UNCONNECTED(1 downto 0),
DOD(1 downto 0) => NLW_RAM_reg_0_15_102_102_DOD_UNCONNECTED(1 downto 0),
WCLK => wr_clk,
WE => I2(0)
);
RAM_reg_0_15_12_17: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => ADDRA(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => ADDRA(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => ADDRA(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => O3(3 downto 0),
DIA(1 downto 0) => din(13 downto 12),
DIB(1 downto 0) => din(15 downto 14),
DIC(1 downto 0) => din(17 downto 16),
DID(1) => '0',
DID(0) => '0',
DOA(1 downto 0) => p_0_out(13 downto 12),
DOB(1 downto 0) => p_0_out(15 downto 14),
DOC(1 downto 0) => p_0_out(17 downto 16),
DOD(1 downto 0) => NLW_RAM_reg_0_15_12_17_DOD_UNCONNECTED(1 downto 0),
WCLK => wr_clk,
WE => I2(0)
);
RAM_reg_0_15_18_23: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => ADDRA(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => ADDRA(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => ADDRA(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => O3(3 downto 0),
DIA(1 downto 0) => din(19 downto 18),
DIB(1 downto 0) => din(21 downto 20),
DIC(1 downto 0) => din(23 downto 22),
DID(1) => '0',
DID(0) => '0',
DOA(1 downto 0) => p_0_out(19 downto 18),
DOB(1 downto 0) => p_0_out(21 downto 20),
DOC(1 downto 0) => p_0_out(23 downto 22),
DOD(1 downto 0) => NLW_RAM_reg_0_15_18_23_DOD_UNCONNECTED(1 downto 0),
WCLK => wr_clk,
WE => I2(0)
);
RAM_reg_0_15_24_29: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => ADDRA(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => ADDRA(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => ADDRA(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => O3(3 downto 0),
DIA(1 downto 0) => din(25 downto 24),
DIB(1 downto 0) => din(27 downto 26),
DIC(1 downto 0) => din(29 downto 28),
DID(1) => '0',
DID(0) => '0',
DOA(1 downto 0) => p_0_out(25 downto 24),
DOB(1 downto 0) => p_0_out(27 downto 26),
DOC(1 downto 0) => p_0_out(29 downto 28),
DOD(1 downto 0) => NLW_RAM_reg_0_15_24_29_DOD_UNCONNECTED(1 downto 0),
WCLK => wr_clk,
WE => I2(0)
);
RAM_reg_0_15_30_35: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => ADDRA(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => ADDRA(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => ADDRA(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => O3(3 downto 0),
DIA(1 downto 0) => din(31 downto 30),
DIB(1 downto 0) => din(33 downto 32),
DIC(1 downto 0) => din(35 downto 34),
DID(1) => '0',
DID(0) => '0',
DOA(1 downto 0) => p_0_out(31 downto 30),
DOB(1 downto 0) => p_0_out(33 downto 32),
DOC(1 downto 0) => p_0_out(35 downto 34),
DOD(1 downto 0) => NLW_RAM_reg_0_15_30_35_DOD_UNCONNECTED(1 downto 0),
WCLK => wr_clk,
WE => I2(0)
);
RAM_reg_0_15_36_41: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => ADDRA(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => ADDRA(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => ADDRA(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => O3(3 downto 0),
DIA(1 downto 0) => din(37 downto 36),
DIB(1 downto 0) => din(39 downto 38),
DIC(1 downto 0) => din(41 downto 40),
DID(1) => '0',
DID(0) => '0',
DOA(1 downto 0) => p_0_out(37 downto 36),
DOB(1 downto 0) => p_0_out(39 downto 38),
DOC(1 downto 0) => p_0_out(41 downto 40),
DOD(1 downto 0) => NLW_RAM_reg_0_15_36_41_DOD_UNCONNECTED(1 downto 0),
WCLK => wr_clk,
WE => I2(0)
);
RAM_reg_0_15_42_47: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => ADDRA(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => ADDRA(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => ADDRA(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => O3(3 downto 0),
DIA(1 downto 0) => din(43 downto 42),
DIB(1 downto 0) => din(45 downto 44),
DIC(1 downto 0) => din(47 downto 46),
DID(1) => '0',
DID(0) => '0',
DOA(1 downto 0) => p_0_out(43 downto 42),
DOB(1 downto 0) => p_0_out(45 downto 44),
DOC(1 downto 0) => p_0_out(47 downto 46),
DOD(1 downto 0) => NLW_RAM_reg_0_15_42_47_DOD_UNCONNECTED(1 downto 0),
WCLK => wr_clk,
WE => I2(0)
);
RAM_reg_0_15_48_53: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => ADDRA(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => ADDRA(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => ADDRA(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => O3(3 downto 0),
DIA(1 downto 0) => din(49 downto 48),
DIB(1 downto 0) => din(51 downto 50),
DIC(1 downto 0) => din(53 downto 52),
DID(1) => '0',
DID(0) => '0',
DOA(1 downto 0) => p_0_out(49 downto 48),
DOB(1 downto 0) => p_0_out(51 downto 50),
DOC(1 downto 0) => p_0_out(53 downto 52),
DOD(1 downto 0) => NLW_RAM_reg_0_15_48_53_DOD_UNCONNECTED(1 downto 0),
WCLK => wr_clk,
WE => I2(0)
);
RAM_reg_0_15_54_59: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => ADDRA(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => ADDRA(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => ADDRA(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => O3(3 downto 0),
DIA(1 downto 0) => din(55 downto 54),
DIB(1 downto 0) => din(57 downto 56),
DIC(1 downto 0) => din(59 downto 58),
DID(1) => '0',
DID(0) => '0',
DOA(1 downto 0) => p_0_out(55 downto 54),
DOB(1 downto 0) => p_0_out(57 downto 56),
DOC(1 downto 0) => p_0_out(59 downto 58),
DOD(1 downto 0) => NLW_RAM_reg_0_15_54_59_DOD_UNCONNECTED(1 downto 0),
WCLK => wr_clk,
WE => I2(0)
);
RAM_reg_0_15_60_65: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => ADDRA(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => ADDRA(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => ADDRA(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => O3(3 downto 0),
DIA(1 downto 0) => din(61 downto 60),
DIB(1 downto 0) => din(63 downto 62),
DIC(1 downto 0) => din(65 downto 64),
DID(1) => '0',
DID(0) => '0',
DOA(1 downto 0) => p_0_out(61 downto 60),
DOB(1 downto 0) => p_0_out(63 downto 62),
DOC(1 downto 0) => p_0_out(65 downto 64),
DOD(1 downto 0) => NLW_RAM_reg_0_15_60_65_DOD_UNCONNECTED(1 downto 0),
WCLK => wr_clk,
WE => I2(0)
);
RAM_reg_0_15_66_71: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => ADDRA(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => ADDRA(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => ADDRA(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => O3(3 downto 0),
DIA(1 downto 0) => din(67 downto 66),
DIB(1 downto 0) => din(69 downto 68),
DIC(1 downto 0) => din(71 downto 70),
DID(1) => '0',
DID(0) => '0',
DOA(1 downto 0) => p_0_out(67 downto 66),
DOB(1 downto 0) => p_0_out(69 downto 68),
DOC(1 downto 0) => p_0_out(71 downto 70),
DOD(1 downto 0) => NLW_RAM_reg_0_15_66_71_DOD_UNCONNECTED(1 downto 0),
WCLK => wr_clk,
WE => I2(0)
);
RAM_reg_0_15_6_11: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => ADDRA(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => ADDRA(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => ADDRA(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => O3(3 downto 0),
DIA(1 downto 0) => din(7 downto 6),
DIB(1 downto 0) => din(9 downto 8),
DIC(1 downto 0) => din(11 downto 10),
DID(1) => '0',
DID(0) => '0',
DOA(1 downto 0) => p_0_out(7 downto 6),
DOB(1 downto 0) => p_0_out(9 downto 8),
DOC(1 downto 0) => p_0_out(11 downto 10),
DOD(1 downto 0) => NLW_RAM_reg_0_15_6_11_DOD_UNCONNECTED(1 downto 0),
WCLK => wr_clk,
WE => I2(0)
);
RAM_reg_0_15_72_77: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => ADDRA(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => ADDRA(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => ADDRA(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => O3(3 downto 0),
DIA(1 downto 0) => din(73 downto 72),
DIB(1 downto 0) => din(75 downto 74),
DIC(1 downto 0) => din(77 downto 76),
DID(1) => '0',
DID(0) => '0',
DOA(1 downto 0) => p_0_out(73 downto 72),
DOB(1 downto 0) => p_0_out(75 downto 74),
DOC(1 downto 0) => p_0_out(77 downto 76),
DOD(1 downto 0) => NLW_RAM_reg_0_15_72_77_DOD_UNCONNECTED(1 downto 0),
WCLK => wr_clk,
WE => I2(0)
);
RAM_reg_0_15_78_83: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => ADDRA(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => ADDRA(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => ADDRA(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => O3(3 downto 0),
DIA(1 downto 0) => din(79 downto 78),
DIB(1 downto 0) => din(81 downto 80),
DIC(1 downto 0) => din(83 downto 82),
DID(1) => '0',
DID(0) => '0',
DOA(1 downto 0) => p_0_out(79 downto 78),
DOB(1 downto 0) => p_0_out(81 downto 80),
DOC(1 downto 0) => p_0_out(83 downto 82),
DOD(1 downto 0) => NLW_RAM_reg_0_15_78_83_DOD_UNCONNECTED(1 downto 0),
WCLK => wr_clk,
WE => I2(0)
);
RAM_reg_0_15_84_89: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => ADDRA(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => ADDRA(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => ADDRA(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => O3(3 downto 0),
DIA(1 downto 0) => din(85 downto 84),
DIB(1 downto 0) => din(87 downto 86),
DIC(1 downto 0) => din(89 downto 88),
DID(1) => '0',
DID(0) => '0',
DOA(1 downto 0) => p_0_out(85 downto 84),
DOB(1 downto 0) => p_0_out(87 downto 86),
DOC(1 downto 0) => p_0_out(89 downto 88),
DOD(1 downto 0) => NLW_RAM_reg_0_15_84_89_DOD_UNCONNECTED(1 downto 0),
WCLK => wr_clk,
WE => I2(0)
);
RAM_reg_0_15_90_95: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => ADDRA(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => ADDRA(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => ADDRA(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => O3(3 downto 0),
DIA(1 downto 0) => din(91 downto 90),
DIB(1 downto 0) => din(93 downto 92),
DIC(1 downto 0) => din(95 downto 94),
DID(1) => '0',
DID(0) => '0',
DOA(1 downto 0) => p_0_out(91 downto 90),
DOB(1 downto 0) => p_0_out(93 downto 92),
DOC(1 downto 0) => p_0_out(95 downto 94),
DOD(1 downto 0) => NLW_RAM_reg_0_15_90_95_DOD_UNCONNECTED(1 downto 0),
WCLK => wr_clk,
WE => I2(0)
);
RAM_reg_0_15_96_101: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => ADDRA(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => ADDRA(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => ADDRA(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => O3(3 downto 0),
DIA(1 downto 0) => din(97 downto 96),
DIB(1 downto 0) => din(99 downto 98),
DIC(1 downto 0) => din(101 downto 100),
DID(1) => '0',
DID(0) => '0',
DOA(1 downto 0) => p_0_out(97 downto 96),
DOB(1 downto 0) => p_0_out(99 downto 98),
DOC(1 downto 0) => p_0_out(101 downto 100),
DOD(1 downto 0) => NLW_RAM_reg_0_15_96_101_DOD_UNCONNECTED(1 downto 0),
WCLK => wr_clk,
WE => I2(0)
);
\gpr1.dout_i_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(0),
Q => Q(0)
);
\gpr1.dout_i_reg[100]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(100),
Q => Q(100)
);
\gpr1.dout_i_reg[101]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(101),
Q => Q(101)
);
\gpr1.dout_i_reg[102]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(102),
Q => Q(102)
);
\gpr1.dout_i_reg[10]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(10),
Q => Q(10)
);
\gpr1.dout_i_reg[11]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(11),
Q => Q(11)
);
\gpr1.dout_i_reg[12]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(12),
Q => Q(12)
);
\gpr1.dout_i_reg[13]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(13),
Q => Q(13)
);
\gpr1.dout_i_reg[14]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(14),
Q => Q(14)
);
\gpr1.dout_i_reg[15]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(15),
Q => Q(15)
);
\gpr1.dout_i_reg[16]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(16),
Q => Q(16)
);
\gpr1.dout_i_reg[17]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(17),
Q => Q(17)
);
\gpr1.dout_i_reg[18]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(18),
Q => Q(18)
);
\gpr1.dout_i_reg[19]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(19),
Q => Q(19)
);
\gpr1.dout_i_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(1),
Q => Q(1)
);
\gpr1.dout_i_reg[20]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(20),
Q => Q(20)
);
\gpr1.dout_i_reg[21]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(21),
Q => Q(21)
);
\gpr1.dout_i_reg[22]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(22),
Q => Q(22)
);
\gpr1.dout_i_reg[23]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(23),
Q => Q(23)
);
\gpr1.dout_i_reg[24]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(24),
Q => Q(24)
);
\gpr1.dout_i_reg[25]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(25),
Q => Q(25)
);
\gpr1.dout_i_reg[26]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(26),
Q => Q(26)
);
\gpr1.dout_i_reg[27]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(27),
Q => Q(27)
);
\gpr1.dout_i_reg[28]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(28),
Q => Q(28)
);
\gpr1.dout_i_reg[29]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(29),
Q => Q(29)
);
\gpr1.dout_i_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(2),
Q => Q(2)
);
\gpr1.dout_i_reg[30]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(30),
Q => Q(30)
);
\gpr1.dout_i_reg[31]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(31),
Q => Q(31)
);
\gpr1.dout_i_reg[32]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(32),
Q => Q(32)
);
\gpr1.dout_i_reg[33]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(33),
Q => Q(33)
);
\gpr1.dout_i_reg[34]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(34),
Q => Q(34)
);
\gpr1.dout_i_reg[35]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(35),
Q => Q(35)
);
\gpr1.dout_i_reg[36]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(36),
Q => Q(36)
);
\gpr1.dout_i_reg[37]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(37),
Q => Q(37)
);
\gpr1.dout_i_reg[38]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(38),
Q => Q(38)
);
\gpr1.dout_i_reg[39]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(39),
Q => Q(39)
);
\gpr1.dout_i_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(3),
Q => Q(3)
);
\gpr1.dout_i_reg[40]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(40),
Q => Q(40)
);
\gpr1.dout_i_reg[41]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(41),
Q => Q(41)
);
\gpr1.dout_i_reg[42]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(42),
Q => Q(42)
);
\gpr1.dout_i_reg[43]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(43),
Q => Q(43)
);
\gpr1.dout_i_reg[44]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(44),
Q => Q(44)
);
\gpr1.dout_i_reg[45]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(45),
Q => Q(45)
);
\gpr1.dout_i_reg[46]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(46),
Q => Q(46)
);
\gpr1.dout_i_reg[47]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(47),
Q => Q(47)
);
\gpr1.dout_i_reg[48]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(48),
Q => Q(48)
);
\gpr1.dout_i_reg[49]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(49),
Q => Q(49)
);
\gpr1.dout_i_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(4),
Q => Q(4)
);
\gpr1.dout_i_reg[50]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(50),
Q => Q(50)
);
\gpr1.dout_i_reg[51]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(51),
Q => Q(51)
);
\gpr1.dout_i_reg[52]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(52),
Q => Q(52)
);
\gpr1.dout_i_reg[53]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(53),
Q => Q(53)
);
\gpr1.dout_i_reg[54]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(54),
Q => Q(54)
);
\gpr1.dout_i_reg[55]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(55),
Q => Q(55)
);
\gpr1.dout_i_reg[56]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(56),
Q => Q(56)
);
\gpr1.dout_i_reg[57]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(57),
Q => Q(57)
);
\gpr1.dout_i_reg[58]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(58),
Q => Q(58)
);
\gpr1.dout_i_reg[59]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(59),
Q => Q(59)
);
\gpr1.dout_i_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(5),
Q => Q(5)
);
\gpr1.dout_i_reg[60]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(60),
Q => Q(60)
);
\gpr1.dout_i_reg[61]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(61),
Q => Q(61)
);
\gpr1.dout_i_reg[62]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(62),
Q => Q(62)
);
\gpr1.dout_i_reg[63]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(63),
Q => Q(63)
);
\gpr1.dout_i_reg[64]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(64),
Q => Q(64)
);
\gpr1.dout_i_reg[65]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(65),
Q => Q(65)
);
\gpr1.dout_i_reg[66]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(66),
Q => Q(66)
);
\gpr1.dout_i_reg[67]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(67),
Q => Q(67)
);
\gpr1.dout_i_reg[68]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(68),
Q => Q(68)
);
\gpr1.dout_i_reg[69]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(69),
Q => Q(69)
);
\gpr1.dout_i_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(6),
Q => Q(6)
);
\gpr1.dout_i_reg[70]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(70),
Q => Q(70)
);
\gpr1.dout_i_reg[71]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(71),
Q => Q(71)
);
\gpr1.dout_i_reg[72]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(72),
Q => Q(72)
);
\gpr1.dout_i_reg[73]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(73),
Q => Q(73)
);
\gpr1.dout_i_reg[74]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(74),
Q => Q(74)
);
\gpr1.dout_i_reg[75]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(75),
Q => Q(75)
);
\gpr1.dout_i_reg[76]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(76),
Q => Q(76)
);
\gpr1.dout_i_reg[77]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(77),
Q => Q(77)
);
\gpr1.dout_i_reg[78]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(78),
Q => Q(78)
);
\gpr1.dout_i_reg[79]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(79),
Q => Q(79)
);
\gpr1.dout_i_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(7),
Q => Q(7)
);
\gpr1.dout_i_reg[80]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(80),
Q => Q(80)
);
\gpr1.dout_i_reg[81]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(81),
Q => Q(81)
);
\gpr1.dout_i_reg[82]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(82),
Q => Q(82)
);
\gpr1.dout_i_reg[83]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(83),
Q => Q(83)
);
\gpr1.dout_i_reg[84]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(84),
Q => Q(84)
);
\gpr1.dout_i_reg[85]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(85),
Q => Q(85)
);
\gpr1.dout_i_reg[86]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(86),
Q => Q(86)
);
\gpr1.dout_i_reg[87]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(87),
Q => Q(87)
);
\gpr1.dout_i_reg[88]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(88),
Q => Q(88)
);
\gpr1.dout_i_reg[89]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(89),
Q => Q(89)
);
\gpr1.dout_i_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(8),
Q => Q(8)
);
\gpr1.dout_i_reg[90]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(90),
Q => Q(90)
);
\gpr1.dout_i_reg[91]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(91),
Q => Q(91)
);
\gpr1.dout_i_reg[92]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(92),
Q => Q(92)
);
\gpr1.dout_i_reg[93]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(93),
Q => Q(93)
);
\gpr1.dout_i_reg[94]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(94),
Q => Q(94)
);
\gpr1.dout_i_reg[95]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(95),
Q => Q(95)
);
\gpr1.dout_i_reg[96]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(96),
Q => Q(96)
);
\gpr1.dout_i_reg[97]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(97),
Q => Q(97)
);
\gpr1.dout_i_reg[98]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(98),
Q => Q(98)
);
\gpr1.dout_i_reg[99]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(99),
Q => Q(99)
);
\gpr1.dout_i_reg[9]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(9),
Q => Q(9)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_async_103x16_rd_bin_cntr is
port (
Q : out STD_LOGIC_VECTOR ( 3 downto 0 );
O1 : out STD_LOGIC;
I6 : out STD_LOGIC_VECTOR ( 3 downto 0 );
O2 : out STD_LOGIC_VECTOR ( 2 downto 0 );
I1 : in STD_LOGIC;
I2 : in STD_LOGIC;
O3 : in STD_LOGIC_VECTOR ( 3 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
rd_clk : in STD_LOGIC;
I3 : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_async_103x16_rd_bin_cntr : entity is "rd_bin_cntr";
end fifo_async_103x16_rd_bin_cntr;
architecture STRUCTURE of fifo_async_103x16_rd_bin_cntr is
signal \^i6\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^o2\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \^q\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal n_0_ram_empty_fb_i_i_2 : STD_LOGIC;
signal n_0_ram_empty_fb_i_i_3 : STD_LOGIC;
signal \plusOp__0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gc0.count[2]_i_1\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \gc0.count[3]_i_1\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of ram_empty_fb_i_i_2 : label is "soft_lutpair9";
attribute SOFT_HLUTNM of ram_empty_fb_i_i_3 : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \rd_pntr_gc[0]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \rd_pntr_gc[2]_i_1\ : label is "soft_lutpair9";
begin
I6(3 downto 0) <= \^i6\(3 downto 0);
O2(2 downto 0) <= \^o2\(2 downto 0);
Q(3 downto 0) <= \^q\(3 downto 0);
\gc0.count[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^q\(0),
O => \plusOp__0\(0)
);
\gc0.count[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^q\(0),
I1 => \^q\(1),
O => \plusOp__0\(1)
);
\gc0.count[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \^q\(1),
I1 => \^q\(0),
I2 => \^q\(2),
O => \plusOp__0\(2)
);
\gc0.count[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \^q\(2),
I1 => \^q\(0),
I2 => \^q\(1),
I3 => \^q\(3),
O => \plusOp__0\(3)
);
\gc0.count_d1_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I3(0),
D => \^q\(0),
Q => \^o2\(0)
);
\gc0.count_d1_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I3(0),
D => \^q\(1),
Q => \^o2\(1)
);
\gc0.count_d1_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I3(0),
D => \^q\(2),
Q => \^o2\(2)
);
\gc0.count_d1_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I3(0),
D => \^q\(3),
Q => \^i6\(3)
);
\gc0.count_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => rd_clk,
CE => E(0),
D => \plusOp__0\(0),
PRE => I3(0),
Q => \^q\(0)
);
\gc0.count_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I3(0),
D => \plusOp__0\(1),
Q => \^q\(1)
);
\gc0.count_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I3(0),
D => \plusOp__0\(2),
Q => \^q\(2)
);
\gc0.count_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I3(0),
D => \plusOp__0\(3),
Q => \^q\(3)
);
ram_empty_fb_i_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => n_0_ram_empty_fb_i_i_2,
I1 => n_0_ram_empty_fb_i_i_3,
I2 => I1,
I3 => I2,
O => O1
);
ram_empty_fb_i_i_2: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^o2\(2),
I1 => O3(2),
I2 => \^i6\(3),
I3 => O3(3),
O => n_0_ram_empty_fb_i_i_2
);
ram_empty_fb_i_i_3: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^o2\(0),
I1 => O3(0),
I2 => \^o2\(1),
I3 => O3(1),
O => n_0_ram_empty_fb_i_i_3
);
\rd_pntr_gc[0]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^o2\(0),
I1 => \^o2\(1),
O => \^i6\(0)
);
\rd_pntr_gc[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^o2\(1),
I1 => \^o2\(2),
O => \^i6\(1)
);
\rd_pntr_gc[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^o2\(2),
I1 => \^i6\(3),
O => \^i6\(2)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_async_103x16_rd_fwft is
port (
empty : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
O1 : out STD_LOGIC;
O2 : out STD_LOGIC_VECTOR ( 0 to 0 );
O4 : out STD_LOGIC_VECTOR ( 0 to 0 );
rd_clk : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
rd_en : in STD_LOGIC;
p_18_out : in STD_LOGIC;
O3 : in STD_LOGIC_VECTOR ( 0 to 0 );
I1 : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_async_103x16_rd_fwft : entity is "rd_fwft";
end fifo_async_103x16_rd_fwft;
architecture STRUCTURE of fifo_async_103x16_rd_fwft is
signal curr_fwft_state : STD_LOGIC_VECTOR ( 0 to 0 );
signal empty_fwft_fb : STD_LOGIC;
signal empty_fwft_i0 : STD_LOGIC;
signal \n_0_gpregsm1.curr_fwft_state_reg[1]\ : STD_LOGIC;
signal next_fwft_state : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of empty_fwft_fb_reg : label is "no";
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of empty_fwft_i_i_1 : label is "soft_lutpair4";
attribute equivalent_register_removal of empty_fwft_i_reg : label is "no";
attribute SOFT_HLUTNM of \gc0.count_d1[3]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \goreg_dm.dout_i[102]_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \gpr1.dout_i[102]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \gpregsm1.curr_fwft_state[0]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \gpregsm1.curr_fwft_state[1]_i_1\ : label is "soft_lutpair5";
attribute equivalent_register_removal of \gpregsm1.curr_fwft_state_reg[0]\ : label is "no";
attribute equivalent_register_removal of \gpregsm1.curr_fwft_state_reg[1]\ : label is "no";
begin
empty_fwft_fb_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => rd_clk,
CE => '1',
D => empty_fwft_i0,
PRE => Q(0),
Q => empty_fwft_fb
);
empty_fwft_i_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"F540"
)
port map (
I0 => \n_0_gpregsm1.curr_fwft_state_reg[1]\,
I1 => rd_en,
I2 => curr_fwft_state(0),
I3 => empty_fwft_fb,
O => empty_fwft_i0
);
empty_fwft_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => rd_clk,
CE => '1',
D => empty_fwft_i0,
PRE => Q(0),
Q => empty
);
\gc0.count_d1[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"00DF"
)
port map (
I0 => \n_0_gpregsm1.curr_fwft_state_reg[1]\,
I1 => rd_en,
I2 => curr_fwft_state(0),
I3 => p_18_out,
O => O2(0)
);
\goreg_dm.dout_i[102]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"D0"
)
port map (
I0 => curr_fwft_state(0),
I1 => rd_en,
I2 => \n_0_gpregsm1.curr_fwft_state_reg[1]\,
O => E(0)
);
\gpr1.dout_i[102]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"00DF"
)
port map (
I0 => \n_0_gpregsm1.curr_fwft_state_reg[1]\,
I1 => rd_en,
I2 => curr_fwft_state(0),
I3 => p_18_out,
O => O4(0)
);
\gpregsm1.curr_fwft_state[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AE"
)
port map (
I0 => \n_0_gpregsm1.curr_fwft_state_reg[1]\,
I1 => curr_fwft_state(0),
I2 => rd_en,
O => next_fwft_state(0)
);
\gpregsm1.curr_fwft_state[1]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"20FF"
)
port map (
I0 => \n_0_gpregsm1.curr_fwft_state_reg[1]\,
I1 => rd_en,
I2 => curr_fwft_state(0),
I3 => p_18_out,
O => next_fwft_state(1)
);
\gpregsm1.curr_fwft_state_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => Q(0),
D => next_fwft_state(0),
Q => curr_fwft_state(0)
);
\gpregsm1.curr_fwft_state_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => Q(0),
D => next_fwft_state(1),
Q => \n_0_gpregsm1.curr_fwft_state_reg[1]\
);
ram_empty_fb_i_i_5: unisim.vcomponents.LUT6
generic map(
INIT => X"00DF0000000000DF"
)
port map (
I0 => \n_0_gpregsm1.curr_fwft_state_reg[1]\,
I1 => rd_en,
I2 => curr_fwft_state(0),
I3 => p_18_out,
I4 => O3(0),
I5 => I1(0),
O => O1
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_async_103x16_rd_status_flags_as is
port (
p_18_out : out STD_LOGIC;
I1 : in STD_LOGIC;
rd_clk : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_async_103x16_rd_status_flags_as : entity is "rd_status_flags_as";
end fifo_async_103x16_rd_status_flags_as;
architecture STRUCTURE of fifo_async_103x16_rd_status_flags_as is
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of ram_empty_fb_i_reg : label is "no";
begin
ram_empty_fb_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => rd_clk,
CE => '1',
D => I1,
PRE => Q(0),
Q => p_18_out
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_async_103x16_reset_blk_ramfifo is
port (
rst_d2 : out STD_LOGIC;
rst_full_gen_i : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 2 downto 0 );
O1 : out STD_LOGIC_VECTOR ( 1 downto 0 );
wr_clk : in STD_LOGIC;
rst : in STD_LOGIC;
rd_clk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_async_103x16_reset_blk_ramfifo : entity is "reset_blk_ramfifo";
end fifo_async_103x16_reset_blk_ramfifo;
architecture STRUCTURE of fifo_async_103x16_reset_blk_ramfifo is
signal \n_0_ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1\ : STD_LOGIC;
signal \n_0_ngwrdrst.grst.g7serrst.wr_rst_reg[1]_i_1\ : STD_LOGIC;
signal rd_rst_asreg : STD_LOGIC;
signal rd_rst_asreg_d1 : STD_LOGIC;
signal rd_rst_asreg_d2 : STD_LOGIC;
signal rst_d1 : STD_LOGIC;
signal \^rst_d2\ : STD_LOGIC;
signal rst_d3 : STD_LOGIC;
signal wr_rst_asreg : STD_LOGIC;
signal wr_rst_asreg_d1 : STD_LOGIC;
signal wr_rst_asreg_d2 : STD_LOGIC;
attribute ASYNC_REG : boolean;
attribute ASYNC_REG of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is std.standard.true;
attribute msgon : string;
attribute msgon of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is "true";
attribute ASYNC_REG of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is std.standard.true;
attribute msgon of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is "true";
attribute ASYNC_REG of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is std.standard.true;
attribute msgon of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is "true";
attribute ASYNC_REG of \ngwrdrst.grst.g7serrst.rd_rst_asreg_d1_reg\ : label is std.standard.true;
attribute msgon of \ngwrdrst.grst.g7serrst.rd_rst_asreg_d1_reg\ : label is "true";
attribute ASYNC_REG of \ngwrdrst.grst.g7serrst.rd_rst_asreg_d2_reg\ : label is std.standard.true;
attribute msgon of \ngwrdrst.grst.g7serrst.rd_rst_asreg_d2_reg\ : label is "true";
attribute ASYNC_REG of \ngwrdrst.grst.g7serrst.rd_rst_asreg_reg\ : label is std.standard.true;
attribute msgon of \ngwrdrst.grst.g7serrst.rd_rst_asreg_reg\ : label is "true";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\ : label is "no";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : label is "no";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : label is "no";
attribute ASYNC_REG of \ngwrdrst.grst.g7serrst.wr_rst_asreg_d1_reg\ : label is std.standard.true;
attribute msgon of \ngwrdrst.grst.g7serrst.wr_rst_asreg_d1_reg\ : label is "true";
attribute ASYNC_REG of \ngwrdrst.grst.g7serrst.wr_rst_asreg_d2_reg\ : label is std.standard.true;
attribute msgon of \ngwrdrst.grst.g7serrst.wr_rst_asreg_d2_reg\ : label is "true";
attribute ASYNC_REG of \ngwrdrst.grst.g7serrst.wr_rst_asreg_reg\ : label is std.standard.true;
attribute msgon of \ngwrdrst.grst.g7serrst.wr_rst_asreg_reg\ : label is "true";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\ : label is "no";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : label is "no";
begin
rst_d2 <= \^rst_d2\;
\grstd1.grst_full.grst_f.RST_FULL_GEN_reg\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => rst,
D => rst_d3,
Q => rst_full_gen_i
);
\grstd1.grst_full.grst_f.rst_d1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => '1',
D => '0',
PRE => rst,
Q => rst_d1
);
\grstd1.grst_full.grst_f.rst_d2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => '1',
D => rst_d1,
PRE => rst,
Q => \^rst_d2\
);
\grstd1.grst_full.grst_f.rst_d3_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => '1',
D => \^rst_d2\,
PRE => rst,
Q => rst_d3
);
\ngwrdrst.grst.g7serrst.rd_rst_asreg_d1_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
D => rd_rst_asreg,
Q => rd_rst_asreg_d1,
R => '0'
);
\ngwrdrst.grst.g7serrst.rd_rst_asreg_d2_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
D => rd_rst_asreg_d1,
Q => rd_rst_asreg_d2,
R => '0'
);
\ngwrdrst.grst.g7serrst.rd_rst_asreg_reg\: unisim.vcomponents.FDPE
port map (
C => rd_clk,
CE => rd_rst_asreg_d1,
D => '0',
PRE => rst,
Q => rd_rst_asreg
);
\ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => rd_rst_asreg,
I1 => rd_rst_asreg_d2,
O => \n_0_ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1\
);
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => rd_clk,
CE => '1',
D => '0',
PRE => \n_0_ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1\,
Q => Q(0)
);
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => rd_clk,
CE => '1',
D => '0',
PRE => \n_0_ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1\,
Q => Q(1)
);
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => rd_clk,
CE => '1',
D => '0',
PRE => \n_0_ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1\,
Q => Q(2)
);
\ngwrdrst.grst.g7serrst.wr_rst_asreg_d1_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
D => wr_rst_asreg,
Q => wr_rst_asreg_d1,
R => '0'
);
\ngwrdrst.grst.g7serrst.wr_rst_asreg_d2_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
D => wr_rst_asreg_d1,
Q => wr_rst_asreg_d2,
R => '0'
);
\ngwrdrst.grst.g7serrst.wr_rst_asreg_reg\: unisim.vcomponents.FDPE
port map (
C => wr_clk,
CE => wr_rst_asreg_d1,
D => '0',
PRE => rst,
Q => wr_rst_asreg
);
\ngwrdrst.grst.g7serrst.wr_rst_reg[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => wr_rst_asreg,
I1 => wr_rst_asreg_d2,
O => \n_0_ngwrdrst.grst.g7serrst.wr_rst_reg[1]_i_1\
);
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => '1',
D => '0',
PRE => \n_0_ngwrdrst.grst.g7serrst.wr_rst_reg[1]_i_1\,
Q => O1(0)
);
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => '1',
D => '0',
PRE => \n_0_ngwrdrst.grst.g7serrst.wr_rst_reg[1]_i_1\,
Q => O1(1)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_async_103x16_synchronizer_ff is
port (
Q : out STD_LOGIC_VECTOR ( 3 downto 0 );
I1 : in STD_LOGIC_VECTOR ( 3 downto 0 );
rd_clk : in STD_LOGIC;
I5 : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_async_103x16_synchronizer_ff : entity is "synchronizer_ff";
end fifo_async_103x16_synchronizer_ff;
architecture STRUCTURE of fifo_async_103x16_synchronizer_ff is
attribute ASYNC_REG : boolean;
attribute ASYNC_REG of \Q_reg_reg[0]\ : label is std.standard.true;
attribute msgon : string;
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG of \Q_reg_reg[1]\ : label is std.standard.true;
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG of \Q_reg_reg[2]\ : label is std.standard.true;
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG of \Q_reg_reg[3]\ : label is std.standard.true;
attribute msgon of \Q_reg_reg[3]\ : label is "true";
begin
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => I5(0),
D => I1(0),
Q => Q(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => I5(0),
D => I1(1),
Q => Q(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => I5(0),
D => I1(2),
Q => Q(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => I5(0),
D => I1(3),
Q => Q(3)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_async_103x16_synchronizer_ff_0 is
port (
Q : out STD_LOGIC_VECTOR ( 3 downto 0 );
I1 : in STD_LOGIC_VECTOR ( 3 downto 0 );
wr_clk : in STD_LOGIC;
I4 : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_async_103x16_synchronizer_ff_0 : entity is "synchronizer_ff";
end fifo_async_103x16_synchronizer_ff_0;
architecture STRUCTURE of fifo_async_103x16_synchronizer_ff_0 is
attribute ASYNC_REG : boolean;
attribute ASYNC_REG of \Q_reg_reg[0]\ : label is std.standard.true;
attribute msgon : string;
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG of \Q_reg_reg[1]\ : label is std.standard.true;
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG of \Q_reg_reg[2]\ : label is std.standard.true;
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG of \Q_reg_reg[3]\ : label is std.standard.true;
attribute msgon of \Q_reg_reg[3]\ : label is "true";
begin
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => I4(0),
D => I1(0),
Q => Q(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => I4(0),
D => I1(1),
Q => Q(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => I4(0),
D => I1(2),
Q => Q(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => I4(0),
D => I1(3),
Q => Q(3)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_async_103x16_synchronizer_ff_1 is
port (
p_0_in : out STD_LOGIC_VECTOR ( 3 downto 0 );
D : in STD_LOGIC_VECTOR ( 3 downto 0 );
rd_clk : in STD_LOGIC;
I5 : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_async_103x16_synchronizer_ff_1 : entity is "synchronizer_ff";
end fifo_async_103x16_synchronizer_ff_1;
architecture STRUCTURE of fifo_async_103x16_synchronizer_ff_1 is
signal \n_0_Q_reg_reg[0]\ : STD_LOGIC;
signal \n_0_Q_reg_reg[1]\ : STD_LOGIC;
signal \n_0_Q_reg_reg[2]\ : STD_LOGIC;
signal \^p_0_in\ : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute ASYNC_REG : boolean;
attribute ASYNC_REG of \Q_reg_reg[0]\ : label is std.standard.true;
attribute msgon : string;
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG of \Q_reg_reg[1]\ : label is std.standard.true;
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG of \Q_reg_reg[2]\ : label is std.standard.true;
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG of \Q_reg_reg[3]\ : label is std.standard.true;
attribute msgon of \Q_reg_reg[3]\ : label is "true";
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \wr_pntr_bin[0]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \wr_pntr_bin[1]_i_1\ : label is "soft_lutpair0";
begin
p_0_in(3 downto 0) <= \^p_0_in\(3 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => I5(0),
D => D(0),
Q => \n_0_Q_reg_reg[0]\
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => I5(0),
D => D(1),
Q => \n_0_Q_reg_reg[1]\
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => I5(0),
D => D(2),
Q => \n_0_Q_reg_reg[2]\
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => I5(0),
D => D(3),
Q => \^p_0_in\(3)
);
\wr_pntr_bin[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \n_0_Q_reg_reg[1]\,
I1 => \n_0_Q_reg_reg[0]\,
I2 => \^p_0_in\(3),
I3 => \n_0_Q_reg_reg[2]\,
O => \^p_0_in\(0)
);
\wr_pntr_bin[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \n_0_Q_reg_reg[2]\,
I1 => \n_0_Q_reg_reg[1]\,
I2 => \^p_0_in\(3),
O => \^p_0_in\(1)
);
\wr_pntr_bin[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \n_0_Q_reg_reg[2]\,
I1 => \^p_0_in\(3),
O => \^p_0_in\(2)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_async_103x16_synchronizer_ff_2 is
port (
Q : out STD_LOGIC_VECTOR ( 0 to 0 );
O1 : out STD_LOGIC_VECTOR ( 2 downto 0 );
D : in STD_LOGIC_VECTOR ( 3 downto 0 );
wr_clk : in STD_LOGIC;
I4 : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_async_103x16_synchronizer_ff_2 : entity is "synchronizer_ff";
end fifo_async_103x16_synchronizer_ff_2;
architecture STRUCTURE of fifo_async_103x16_synchronizer_ff_2 is
signal \^q\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \n_0_Q_reg_reg[0]\ : STD_LOGIC;
signal \n_0_Q_reg_reg[1]\ : STD_LOGIC;
signal \n_0_Q_reg_reg[2]\ : STD_LOGIC;
attribute ASYNC_REG : boolean;
attribute ASYNC_REG of \Q_reg_reg[0]\ : label is std.standard.true;
attribute msgon : string;
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG of \Q_reg_reg[1]\ : label is std.standard.true;
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG of \Q_reg_reg[2]\ : label is std.standard.true;
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG of \Q_reg_reg[3]\ : label is std.standard.true;
attribute msgon of \Q_reg_reg[3]\ : label is "true";
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \rd_pntr_bin[0]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \rd_pntr_bin[1]_i_1\ : label is "soft_lutpair1";
begin
Q(0) <= \^q\(0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => I4(0),
D => D(0),
Q => \n_0_Q_reg_reg[0]\
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => I4(0),
D => D(1),
Q => \n_0_Q_reg_reg[1]\
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => I4(0),
D => D(2),
Q => \n_0_Q_reg_reg[2]\
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => I4(0),
D => D(3),
Q => \^q\(0)
);
\rd_pntr_bin[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \n_0_Q_reg_reg[1]\,
I1 => \n_0_Q_reg_reg[0]\,
I2 => \^q\(0),
I3 => \n_0_Q_reg_reg[2]\,
O => O1(0)
);
\rd_pntr_bin[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \n_0_Q_reg_reg[2]\,
I1 => \n_0_Q_reg_reg[1]\,
I2 => \^q\(0),
O => O1(1)
);
\rd_pntr_bin[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \n_0_Q_reg_reg[2]\,
I1 => \^q\(0),
O => O1(2)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_async_103x16_wr_bin_cntr is
port (
Q : out STD_LOGIC_VECTOR ( 2 downto 0 );
O2 : out STD_LOGIC_VECTOR ( 3 downto 0 );
D : out STD_LOGIC_VECTOR ( 1 downto 0 );
ram_full_i : out STD_LOGIC;
O3 : out STD_LOGIC_VECTOR ( 3 downto 0 );
wr_en : in STD_LOGIC;
p_1_out : in STD_LOGIC;
O1 : in STD_LOGIC_VECTOR ( 3 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
I1 : in STD_LOGIC;
I2 : in STD_LOGIC;
rst_full_gen_i : in STD_LOGIC;
wr_clk : in STD_LOGIC;
I3 : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_async_103x16_wr_bin_cntr : entity is "wr_bin_cntr";
end fifo_async_103x16_wr_bin_cntr;
architecture STRUCTURE of fifo_async_103x16_wr_bin_cntr is
signal \^o2\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^q\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \n_0_gdiff.diff_pntr_pad[4]_i_2\ : STD_LOGIC;
signal \n_0_gdiff.diff_pntr_pad[4]_i_3\ : STD_LOGIC;
signal n_0_ram_full_i_i_2 : STD_LOGIC;
signal n_0_ram_full_i_i_3 : STD_LOGIC;
signal p_8_out : STD_LOGIC_VECTOR ( 3 to 3 );
signal \plusOp__1\ : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gdiff.diff_pntr_pad[4]_i_2\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \gic0.gc0.count[2]_i_1\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \gic0.gc0.count[3]_i_1\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of ram_full_i_i_2 : label is "soft_lutpair11";
begin
O2(3 downto 0) <= \^o2\(3 downto 0);
Q(2 downto 0) <= \^q\(2 downto 0);
\gdiff.diff_pntr_pad[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"9699999966669699"
)
port map (
I0 => \^q\(1),
I1 => O1(1),
I2 => p_1_out,
I3 => wr_en,
I4 => \^q\(0),
I5 => O1(0),
O => D(0)
);
\gdiff.diff_pntr_pad[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"9999669969996669"
)
port map (
I0 => p_8_out(3),
I1 => O1(3),
I2 => \n_0_gdiff.diff_pntr_pad[4]_i_2\,
I3 => \^q\(2),
I4 => O1(2),
I5 => \n_0_gdiff.diff_pntr_pad[4]_i_3\,
O => D(1)
);
\gdiff.diff_pntr_pad[4]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => \^q\(1),
I1 => O1(1),
O => \n_0_gdiff.diff_pntr_pad[4]_i_2\
);
\gdiff.diff_pntr_pad[4]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"DD0DFF0F0000DD0D"
)
port map (
I0 => wr_en,
I1 => p_1_out,
I2 => \^q\(1),
I3 => O1(1),
I4 => \^q\(0),
I5 => O1(0),
O => \n_0_gdiff.diff_pntr_pad[4]_i_3\
);
\gic0.gc0.count[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^o2\(0),
O => \plusOp__1\(0)
);
\gic0.gc0.count[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^o2\(0),
I1 => \^o2\(1),
O => \plusOp__1\(1)
);
\gic0.gc0.count[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => \^o2\(2),
I1 => \^o2\(1),
I2 => \^o2\(0),
O => \plusOp__1\(2)
);
\gic0.gc0.count[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AAA"
)
port map (
I0 => \^o2\(3),
I1 => \^o2\(0),
I2 => \^o2\(1),
I3 => \^o2\(2),
O => \plusOp__1\(3)
);
\gic0.gc0.count_d1_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => E(0),
D => \^o2\(0),
PRE => I3(0),
Q => \^q\(0)
);
\gic0.gc0.count_d1_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => I3(0),
D => \^o2\(1),
Q => \^q\(1)
);
\gic0.gc0.count_d1_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => I3(0),
D => \^o2\(2),
Q => \^q\(2)
);
\gic0.gc0.count_d1_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => I3(0),
D => \^o2\(3),
Q => p_8_out(3)
);
\gic0.gc0.count_d2_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => I3(0),
D => \^q\(0),
Q => O3(0)
);
\gic0.gc0.count_d2_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => I3(0),
D => \^q\(1),
Q => O3(1)
);
\gic0.gc0.count_d2_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => I3(0),
D => \^q\(2),
Q => O3(2)
);
\gic0.gc0.count_d2_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => I3(0),
D => p_8_out(3),
Q => O3(3)
);
\gic0.gc0.count_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => I3(0),
D => \plusOp__1\(0),
Q => \^o2\(0)
);
\gic0.gc0.count_reg[1]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => E(0),
D => \plusOp__1\(1),
PRE => I3(0),
Q => \^o2\(1)
);
\gic0.gc0.count_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => I3(0),
D => \plusOp__1\(2),
Q => \^o2\(2)
);
\gic0.gc0.count_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => I3(0),
D => \plusOp__1\(3),
Q => \^o2\(3)
);
ram_full_i_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000111111F1"
)
port map (
I0 => n_0_ram_full_i_i_2,
I1 => n_0_ram_full_i_i_3,
I2 => E(0),
I3 => I1,
I4 => I2,
I5 => rst_full_gen_i,
O => ram_full_i
);
ram_full_i_i_2: unisim.vcomponents.LUT4
generic map(
INIT => X"6FF6"
)
port map (
I0 => \^q\(1),
I1 => O1(1),
I2 => \^q\(2),
I3 => O1(2),
O => n_0_ram_full_i_i_2
);
ram_full_i_i_3: unisim.vcomponents.LUT4
generic map(
INIT => X"6FF6"
)
port map (
I0 => p_8_out(3),
I1 => O1(3),
I2 => O1(0),
I3 => \^q\(0),
O => n_0_ram_full_i_i_3
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_async_103x16_wr_pf_as is
port (
prog_full : out STD_LOGIC;
wr_clk : in STD_LOGIC;
rst_d2 : in STD_LOGIC;
rst_full_gen_i : in STD_LOGIC;
p_1_out : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 2 downto 0 );
I3 : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_async_103x16_wr_pf_as : entity is "wr_pf_as";
end fifo_async_103x16_wr_pf_as;
architecture STRUCTURE of fifo_async_103x16_wr_pf_as is
signal diff_pntr : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \n_0_gpf1.prog_full_i_i_1\ : STD_LOGIC;
signal \^prog_full\ : STD_LOGIC;
begin
prog_full <= \^prog_full\;
\gdiff.diff_pntr_pad_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => I3(0),
D => D(0),
Q => diff_pntr(1)
);
\gdiff.diff_pntr_pad_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => I3(0),
D => D(1),
Q => diff_pntr(2)
);
\gdiff.diff_pntr_pad_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => I3(0),
D => D(2),
Q => diff_pntr(3)
);
\gpf1.prog_full_i_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00FF00E0000000E0"
)
port map (
I0 => diff_pntr(1),
I1 => diff_pntr(2),
I2 => diff_pntr(3),
I3 => rst_full_gen_i,
I4 => p_1_out,
I5 => \^prog_full\,
O => \n_0_gpf1.prog_full_i_i_1\
);
\gpf1.prog_full_i_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => '1',
D => \n_0_gpf1.prog_full_i_i_1\,
PRE => rst_d2,
Q => \^prog_full\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_async_103x16_wr_status_flags_as is
port (
full : out STD_LOGIC;
p_1_out : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
ram_full_i : in STD_LOGIC;
wr_clk : in STD_LOGIC;
rst_d2 : in STD_LOGIC;
wr_en : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_async_103x16_wr_status_flags_as : entity is "wr_status_flags_as";
end fifo_async_103x16_wr_status_flags_as;
architecture STRUCTURE of fifo_async_103x16_wr_status_flags_as is
signal \^p_1_out\ : STD_LOGIC;
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of ram_full_fb_i_reg : label is "no";
attribute equivalent_register_removal of ram_full_i_reg : label is "no";
begin
p_1_out <= \^p_1_out\;
\gic0.gc0.count_d1[3]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => wr_en,
I1 => \^p_1_out\,
O => E(0)
);
ram_full_fb_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => '1',
D => ram_full_i,
PRE => rst_d2,
Q => \^p_1_out\
);
ram_full_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => '1',
D => ram_full_i,
PRE => rst_d2,
Q => full
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_async_103x16_clk_x_pntrs is
port (
D : out STD_LOGIC_VECTOR ( 0 to 0 );
O1 : out STD_LOGIC_VECTOR ( 3 downto 0 );
O2 : out STD_LOGIC;
O3 : out STD_LOGIC_VECTOR ( 3 downto 0 );
O4 : out STD_LOGIC;
O5 : out STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 2 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
I1 : in STD_LOGIC_VECTOR ( 2 downto 0 );
I2 : in STD_LOGIC_VECTOR ( 3 downto 0 );
I3 : in STD_LOGIC_VECTOR ( 3 downto 0 );
wr_clk : in STD_LOGIC;
I4 : in STD_LOGIC_VECTOR ( 0 to 0 );
rd_clk : in STD_LOGIC;
I5 : in STD_LOGIC_VECTOR ( 0 to 0 );
I6 : in STD_LOGIC_VECTOR ( 3 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_async_103x16_clk_x_pntrs : entity is "clk_x_pntrs";
end fifo_async_103x16_clk_x_pntrs;
architecture STRUCTURE of fifo_async_103x16_clk_x_pntrs is
signal \^o1\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^o3\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \n_0_gdiff.diff_pntr_pad[3]_i_2\ : STD_LOGIC;
signal \n_0_gsync_stage[1].rd_stg_inst\ : STD_LOGIC;
signal \n_0_gsync_stage[1].wr_stg_inst\ : STD_LOGIC;
signal \n_0_gsync_stage[2].wr_stg_inst\ : STD_LOGIC;
signal \n_1_gsync_stage[1].rd_stg_inst\ : STD_LOGIC;
signal \n_1_gsync_stage[1].wr_stg_inst\ : STD_LOGIC;
signal \n_1_gsync_stage[2].wr_stg_inst\ : STD_LOGIC;
signal \n_2_gsync_stage[1].rd_stg_inst\ : STD_LOGIC;
signal \n_2_gsync_stage[1].wr_stg_inst\ : STD_LOGIC;
signal \n_2_gsync_stage[2].wr_stg_inst\ : STD_LOGIC;
signal \n_3_gsync_stage[1].rd_stg_inst\ : STD_LOGIC;
signal \n_3_gsync_stage[1].wr_stg_inst\ : STD_LOGIC;
signal \n_3_gsync_stage[2].wr_stg_inst\ : STD_LOGIC;
signal p_0_in : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_0_in2_out : STD_LOGIC_VECTOR ( 2 downto 0 );
signal rd_pntr_gc : STD_LOGIC_VECTOR ( 3 downto 0 );
signal wr_pntr_gc : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gdiff.diff_pntr_pad[3]_i_2\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of ram_full_i_i_5 : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \wr_pntr_gc[0]_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \wr_pntr_gc[1]_i_1\ : label is "soft_lutpair3";
begin
O1(3 downto 0) <= \^o1\(3 downto 0);
O3(3 downto 0) <= \^o3\(3 downto 0);
\gdiff.diff_pntr_pad[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"9A5959599A9A9A59"
)
port map (
I0 => \n_0_gdiff.diff_pntr_pad[3]_i_2\,
I1 => Q(1),
I2 => \^o1\(1),
I3 => E(0),
I4 => Q(0),
I5 => \^o1\(0),
O => D(0)
);
\gdiff.diff_pntr_pad[3]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^o1\(2),
I1 => Q(2),
O => \n_0_gdiff.diff_pntr_pad[3]_i_2\
);
\gsync_stage[1].rd_stg_inst\: entity work.fifo_async_103x16_synchronizer_ff
port map (
I1(3 downto 0) => wr_pntr_gc(3 downto 0),
I5(0) => I5(0),
Q(3) => \n_0_gsync_stage[1].rd_stg_inst\,
Q(2) => \n_1_gsync_stage[1].rd_stg_inst\,
Q(1) => \n_2_gsync_stage[1].rd_stg_inst\,
Q(0) => \n_3_gsync_stage[1].rd_stg_inst\,
rd_clk => rd_clk
);
\gsync_stage[1].wr_stg_inst\: entity work.fifo_async_103x16_synchronizer_ff_0
port map (
I1(3 downto 0) => rd_pntr_gc(3 downto 0),
I4(0) => I4(0),
Q(3) => \n_0_gsync_stage[1].wr_stg_inst\,
Q(2) => \n_1_gsync_stage[1].wr_stg_inst\,
Q(1) => \n_2_gsync_stage[1].wr_stg_inst\,
Q(0) => \n_3_gsync_stage[1].wr_stg_inst\,
wr_clk => wr_clk
);
\gsync_stage[2].rd_stg_inst\: entity work.fifo_async_103x16_synchronizer_ff_1
port map (
D(3) => \n_0_gsync_stage[1].rd_stg_inst\,
D(2) => \n_1_gsync_stage[1].rd_stg_inst\,
D(1) => \n_2_gsync_stage[1].rd_stg_inst\,
D(0) => \n_3_gsync_stage[1].rd_stg_inst\,
I5(0) => I5(0),
p_0_in(3 downto 0) => p_0_in(3 downto 0),
rd_clk => rd_clk
);
\gsync_stage[2].wr_stg_inst\: entity work.fifo_async_103x16_synchronizer_ff_2
port map (
D(3) => \n_0_gsync_stage[1].wr_stg_inst\,
D(2) => \n_1_gsync_stage[1].wr_stg_inst\,
D(1) => \n_2_gsync_stage[1].wr_stg_inst\,
D(0) => \n_3_gsync_stage[1].wr_stg_inst\,
I4(0) => I4(0),
O1(2) => \n_1_gsync_stage[2].wr_stg_inst\,
O1(1) => \n_2_gsync_stage[2].wr_stg_inst\,
O1(0) => \n_3_gsync_stage[2].wr_stg_inst\,
Q(0) => \n_0_gsync_stage[2].wr_stg_inst\,
wr_clk => wr_clk
);
ram_empty_fb_i_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^o3\(2),
I1 => I1(2),
I2 => \^o3\(1),
I3 => I1(1),
I4 => I1(0),
I5 => \^o3\(0),
O => O2
);
ram_full_i_i_4: unisim.vcomponents.LUT4
generic map(
INIT => X"6FF6"
)
port map (
I0 => \^o1\(1),
I1 => I2(1),
I2 => \^o1\(0),
I3 => I2(0),
O => O4
);
ram_full_i_i_5: unisim.vcomponents.LUT4
generic map(
INIT => X"6FF6"
)
port map (
I0 => \^o1\(3),
I1 => I2(3),
I2 => \^o1\(2),
I3 => I2(2),
O => O5
);
\rd_pntr_bin_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => I4(0),
D => \n_3_gsync_stage[2].wr_stg_inst\,
Q => \^o1\(0)
);
\rd_pntr_bin_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => I4(0),
D => \n_2_gsync_stage[2].wr_stg_inst\,
Q => \^o1\(1)
);
\rd_pntr_bin_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => I4(0),
D => \n_1_gsync_stage[2].wr_stg_inst\,
Q => \^o1\(2)
);
\rd_pntr_bin_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => I4(0),
D => \n_0_gsync_stage[2].wr_stg_inst\,
Q => \^o1\(3)
);
\rd_pntr_gc_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => I5(0),
D => I6(0),
Q => rd_pntr_gc(0)
);
\rd_pntr_gc_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => I5(0),
D => I6(1),
Q => rd_pntr_gc(1)
);
\rd_pntr_gc_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => I5(0),
D => I6(2),
Q => rd_pntr_gc(2)
);
\rd_pntr_gc_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => I5(0),
D => I6(3),
Q => rd_pntr_gc(3)
);
\wr_pntr_bin_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => I5(0),
D => p_0_in(0),
Q => \^o3\(0)
);
\wr_pntr_bin_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => I5(0),
D => p_0_in(1),
Q => \^o3\(1)
);
\wr_pntr_bin_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => I5(0),
D => p_0_in(2),
Q => \^o3\(2)
);
\wr_pntr_bin_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => I5(0),
D => p_0_in(3),
Q => \^o3\(3)
);
\wr_pntr_gc[0]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => I3(0),
I1 => I3(1),
O => p_0_in2_out(0)
);
\wr_pntr_gc[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => I3(1),
I1 => I3(2),
O => p_0_in2_out(1)
);
\wr_pntr_gc[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => I3(2),
I1 => I3(3),
O => p_0_in2_out(2)
);
\wr_pntr_gc_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => I4(0),
D => p_0_in2_out(0),
Q => wr_pntr_gc(0)
);
\wr_pntr_gc_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => I4(0),
D => p_0_in2_out(1),
Q => wr_pntr_gc(1)
);
\wr_pntr_gc_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => I4(0),
D => p_0_in2_out(2),
Q => wr_pntr_gc(2)
);
\wr_pntr_gc_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => I4(0),
D => I3(3),
Q => wr_pntr_gc(3)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_async_103x16_memory is
port (
dout : out STD_LOGIC_VECTOR ( 102 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
rd_clk : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
wr_clk : in STD_LOGIC;
I1 : in STD_LOGIC_VECTOR ( 0 to 0 );
din : in STD_LOGIC_VECTOR ( 102 downto 0 );
ADDRA : in STD_LOGIC_VECTOR ( 3 downto 0 );
O3 : in STD_LOGIC_VECTOR ( 3 downto 0 );
I2 : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_async_103x16_memory : entity is "memory";
end fifo_async_103x16_memory;
architecture STRUCTURE of fifo_async_103x16_memory is
signal p_0_out : STD_LOGIC_VECTOR ( 102 downto 0 );
begin
\gdm.dm\: entity work.fifo_async_103x16_dmem
port map (
ADDRA(3 downto 0) => ADDRA(3 downto 0),
E(0) => E(0),
I1(0) => Q(0),
I2(0) => I1(0),
O3(3 downto 0) => O3(3 downto 0),
Q(102 downto 0) => p_0_out(102 downto 0),
din(102 downto 0) => din(102 downto 0),
rd_clk => rd_clk,
wr_clk => wr_clk
);
\goreg_dm.dout_i_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(0),
Q => dout(0)
);
\goreg_dm.dout_i_reg[100]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(100),
Q => dout(100)
);
\goreg_dm.dout_i_reg[101]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(101),
Q => dout(101)
);
\goreg_dm.dout_i_reg[102]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(102),
Q => dout(102)
);
\goreg_dm.dout_i_reg[10]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(10),
Q => dout(10)
);
\goreg_dm.dout_i_reg[11]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(11),
Q => dout(11)
);
\goreg_dm.dout_i_reg[12]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(12),
Q => dout(12)
);
\goreg_dm.dout_i_reg[13]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(13),
Q => dout(13)
);
\goreg_dm.dout_i_reg[14]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(14),
Q => dout(14)
);
\goreg_dm.dout_i_reg[15]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(15),
Q => dout(15)
);
\goreg_dm.dout_i_reg[16]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(16),
Q => dout(16)
);
\goreg_dm.dout_i_reg[17]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(17),
Q => dout(17)
);
\goreg_dm.dout_i_reg[18]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(18),
Q => dout(18)
);
\goreg_dm.dout_i_reg[19]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(19),
Q => dout(19)
);
\goreg_dm.dout_i_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(1),
Q => dout(1)
);
\goreg_dm.dout_i_reg[20]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(20),
Q => dout(20)
);
\goreg_dm.dout_i_reg[21]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(21),
Q => dout(21)
);
\goreg_dm.dout_i_reg[22]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(22),
Q => dout(22)
);
\goreg_dm.dout_i_reg[23]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(23),
Q => dout(23)
);
\goreg_dm.dout_i_reg[24]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(24),
Q => dout(24)
);
\goreg_dm.dout_i_reg[25]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(25),
Q => dout(25)
);
\goreg_dm.dout_i_reg[26]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(26),
Q => dout(26)
);
\goreg_dm.dout_i_reg[27]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(27),
Q => dout(27)
);
\goreg_dm.dout_i_reg[28]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(28),
Q => dout(28)
);
\goreg_dm.dout_i_reg[29]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(29),
Q => dout(29)
);
\goreg_dm.dout_i_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(2),
Q => dout(2)
);
\goreg_dm.dout_i_reg[30]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(30),
Q => dout(30)
);
\goreg_dm.dout_i_reg[31]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(31),
Q => dout(31)
);
\goreg_dm.dout_i_reg[32]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(32),
Q => dout(32)
);
\goreg_dm.dout_i_reg[33]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(33),
Q => dout(33)
);
\goreg_dm.dout_i_reg[34]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(34),
Q => dout(34)
);
\goreg_dm.dout_i_reg[35]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(35),
Q => dout(35)
);
\goreg_dm.dout_i_reg[36]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(36),
Q => dout(36)
);
\goreg_dm.dout_i_reg[37]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(37),
Q => dout(37)
);
\goreg_dm.dout_i_reg[38]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(38),
Q => dout(38)
);
\goreg_dm.dout_i_reg[39]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(39),
Q => dout(39)
);
\goreg_dm.dout_i_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(3),
Q => dout(3)
);
\goreg_dm.dout_i_reg[40]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(40),
Q => dout(40)
);
\goreg_dm.dout_i_reg[41]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(41),
Q => dout(41)
);
\goreg_dm.dout_i_reg[42]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(42),
Q => dout(42)
);
\goreg_dm.dout_i_reg[43]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(43),
Q => dout(43)
);
\goreg_dm.dout_i_reg[44]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(44),
Q => dout(44)
);
\goreg_dm.dout_i_reg[45]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(45),
Q => dout(45)
);
\goreg_dm.dout_i_reg[46]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(46),
Q => dout(46)
);
\goreg_dm.dout_i_reg[47]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(47),
Q => dout(47)
);
\goreg_dm.dout_i_reg[48]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(48),
Q => dout(48)
);
\goreg_dm.dout_i_reg[49]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(49),
Q => dout(49)
);
\goreg_dm.dout_i_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(4),
Q => dout(4)
);
\goreg_dm.dout_i_reg[50]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(50),
Q => dout(50)
);
\goreg_dm.dout_i_reg[51]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(51),
Q => dout(51)
);
\goreg_dm.dout_i_reg[52]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(52),
Q => dout(52)
);
\goreg_dm.dout_i_reg[53]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(53),
Q => dout(53)
);
\goreg_dm.dout_i_reg[54]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(54),
Q => dout(54)
);
\goreg_dm.dout_i_reg[55]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(55),
Q => dout(55)
);
\goreg_dm.dout_i_reg[56]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(56),
Q => dout(56)
);
\goreg_dm.dout_i_reg[57]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(57),
Q => dout(57)
);
\goreg_dm.dout_i_reg[58]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(58),
Q => dout(58)
);
\goreg_dm.dout_i_reg[59]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(59),
Q => dout(59)
);
\goreg_dm.dout_i_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(5),
Q => dout(5)
);
\goreg_dm.dout_i_reg[60]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(60),
Q => dout(60)
);
\goreg_dm.dout_i_reg[61]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(61),
Q => dout(61)
);
\goreg_dm.dout_i_reg[62]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(62),
Q => dout(62)
);
\goreg_dm.dout_i_reg[63]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(63),
Q => dout(63)
);
\goreg_dm.dout_i_reg[64]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(64),
Q => dout(64)
);
\goreg_dm.dout_i_reg[65]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(65),
Q => dout(65)
);
\goreg_dm.dout_i_reg[66]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(66),
Q => dout(66)
);
\goreg_dm.dout_i_reg[67]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(67),
Q => dout(67)
);
\goreg_dm.dout_i_reg[68]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(68),
Q => dout(68)
);
\goreg_dm.dout_i_reg[69]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(69),
Q => dout(69)
);
\goreg_dm.dout_i_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(6),
Q => dout(6)
);
\goreg_dm.dout_i_reg[70]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(70),
Q => dout(70)
);
\goreg_dm.dout_i_reg[71]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(71),
Q => dout(71)
);
\goreg_dm.dout_i_reg[72]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(72),
Q => dout(72)
);
\goreg_dm.dout_i_reg[73]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(73),
Q => dout(73)
);
\goreg_dm.dout_i_reg[74]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(74),
Q => dout(74)
);
\goreg_dm.dout_i_reg[75]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(75),
Q => dout(75)
);
\goreg_dm.dout_i_reg[76]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(76),
Q => dout(76)
);
\goreg_dm.dout_i_reg[77]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(77),
Q => dout(77)
);
\goreg_dm.dout_i_reg[78]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(78),
Q => dout(78)
);
\goreg_dm.dout_i_reg[79]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(79),
Q => dout(79)
);
\goreg_dm.dout_i_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(7),
Q => dout(7)
);
\goreg_dm.dout_i_reg[80]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(80),
Q => dout(80)
);
\goreg_dm.dout_i_reg[81]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(81),
Q => dout(81)
);
\goreg_dm.dout_i_reg[82]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(82),
Q => dout(82)
);
\goreg_dm.dout_i_reg[83]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(83),
Q => dout(83)
);
\goreg_dm.dout_i_reg[84]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(84),
Q => dout(84)
);
\goreg_dm.dout_i_reg[85]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(85),
Q => dout(85)
);
\goreg_dm.dout_i_reg[86]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(86),
Q => dout(86)
);
\goreg_dm.dout_i_reg[87]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(87),
Q => dout(87)
);
\goreg_dm.dout_i_reg[88]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(88),
Q => dout(88)
);
\goreg_dm.dout_i_reg[89]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(89),
Q => dout(89)
);
\goreg_dm.dout_i_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(8),
Q => dout(8)
);
\goreg_dm.dout_i_reg[90]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(90),
Q => dout(90)
);
\goreg_dm.dout_i_reg[91]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(91),
Q => dout(91)
);
\goreg_dm.dout_i_reg[92]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(92),
Q => dout(92)
);
\goreg_dm.dout_i_reg[93]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(93),
Q => dout(93)
);
\goreg_dm.dout_i_reg[94]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(94),
Q => dout(94)
);
\goreg_dm.dout_i_reg[95]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(95),
Q => dout(95)
);
\goreg_dm.dout_i_reg[96]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(96),
Q => dout(96)
);
\goreg_dm.dout_i_reg[97]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(97),
Q => dout(97)
);
\goreg_dm.dout_i_reg[98]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(98),
Q => dout(98)
);
\goreg_dm.dout_i_reg[99]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(99),
Q => dout(99)
);
\goreg_dm.dout_i_reg[9]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(9),
Q => dout(9)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_async_103x16_rd_logic is
port (
empty : out STD_LOGIC;
O1 : out STD_LOGIC_VECTOR ( 2 downto 0 );
E : out STD_LOGIC_VECTOR ( 0 to 0 );
O2 : out STD_LOGIC_VECTOR ( 0 to 0 );
I6 : out STD_LOGIC_VECTOR ( 3 downto 0 );
O4 : out STD_LOGIC_VECTOR ( 2 downto 0 );
rd_clk : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
rd_en : in STD_LOGIC;
I1 : in STD_LOGIC;
O3 : in STD_LOGIC_VECTOR ( 3 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_async_103x16_rd_logic : entity is "rd_logic";
end fifo_async_103x16_rd_logic;
architecture STRUCTURE of fifo_async_103x16_rd_logic is
signal \n_2_gr1.rfwft\ : STD_LOGIC;
signal n_4_rpntr : STD_LOGIC;
signal p_14_out : STD_LOGIC;
signal p_18_out : STD_LOGIC;
signal rd_pntr_plus1 : STD_LOGIC_VECTOR ( 3 to 3 );
begin
\gr1.rfwft\: entity work.fifo_async_103x16_rd_fwft
port map (
E(0) => E(0),
I1(0) => rd_pntr_plus1(3),
O1 => \n_2_gr1.rfwft\,
O2(0) => p_14_out,
O3(0) => O3(3),
O4(0) => O2(0),
Q(0) => Q(0),
empty => empty,
p_18_out => p_18_out,
rd_clk => rd_clk,
rd_en => rd_en
);
\gras.rsts\: entity work.fifo_async_103x16_rd_status_flags_as
port map (
I1 => n_4_rpntr,
Q(0) => Q(0),
p_18_out => p_18_out,
rd_clk => rd_clk
);
rpntr: entity work.fifo_async_103x16_rd_bin_cntr
port map (
E(0) => p_14_out,
I1 => I1,
I2 => \n_2_gr1.rfwft\,
I3(0) => Q(0),
I6(3 downto 0) => I6(3 downto 0),
O1 => n_4_rpntr,
O2(2 downto 0) => O4(2 downto 0),
O3(3 downto 0) => O3(3 downto 0),
Q(3) => rd_pntr_plus1(3),
Q(2 downto 0) => O1(2 downto 0),
rd_clk => rd_clk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_async_103x16_wr_logic is
port (
full : out STD_LOGIC;
prog_full : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 2 downto 0 );
O2 : out STD_LOGIC_VECTOR ( 3 downto 0 );
E : out STD_LOGIC_VECTOR ( 0 to 0 );
O3 : out STD_LOGIC_VECTOR ( 3 downto 0 );
wr_clk : in STD_LOGIC;
rst_d2 : in STD_LOGIC;
wr_en : in STD_LOGIC;
O1 : in STD_LOGIC_VECTOR ( 3 downto 0 );
I1 : in STD_LOGIC;
I2 : in STD_LOGIC;
rst_full_gen_i : in STD_LOGIC;
I3 : in STD_LOGIC_VECTOR ( 0 to 0 );
D : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_async_103x16_wr_logic : entity is "wr_logic";
end fifo_async_103x16_wr_logic;
architecture STRUCTURE of fifo_async_103x16_wr_logic is
signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal p_1_out : STD_LOGIC;
signal plusOp : STD_LOGIC_VECTOR ( 4 downto 2 );
signal ram_full_i : STD_LOGIC;
begin
E(0) <= \^e\(0);
\gwas.gpf.wrpf\: entity work.fifo_async_103x16_wr_pf_as
port map (
D(2) => plusOp(4),
D(1) => D(0),
D(0) => plusOp(2),
I3(0) => I3(0),
p_1_out => p_1_out,
prog_full => prog_full,
rst_d2 => rst_d2,
rst_full_gen_i => rst_full_gen_i,
wr_clk => wr_clk
);
\gwas.wsts\: entity work.fifo_async_103x16_wr_status_flags_as
port map (
E(0) => \^e\(0),
full => full,
p_1_out => p_1_out,
ram_full_i => ram_full_i,
rst_d2 => rst_d2,
wr_clk => wr_clk,
wr_en => wr_en
);
wpntr: entity work.fifo_async_103x16_wr_bin_cntr
port map (
D(1) => plusOp(4),
D(0) => plusOp(2),
E(0) => \^e\(0),
I1 => I1,
I2 => I2,
I3(0) => I3(0),
O1(3 downto 0) => O1(3 downto 0),
O2(3 downto 0) => O2(3 downto 0),
O3(3 downto 0) => O3(3 downto 0),
Q(2 downto 0) => Q(2 downto 0),
p_1_out => p_1_out,
ram_full_i => ram_full_i,
rst_full_gen_i => rst_full_gen_i,
wr_clk => wr_clk,
wr_en => wr_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_async_103x16_fifo_generator_ramfifo is
port (
dout : out STD_LOGIC_VECTOR ( 102 downto 0 );
empty : out STD_LOGIC;
full : out STD_LOGIC;
prog_full : out STD_LOGIC;
wr_en : in STD_LOGIC;
rd_clk : in STD_LOGIC;
wr_clk : in STD_LOGIC;
rst : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 102 downto 0 );
rd_en : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_async_103x16_fifo_generator_ramfifo : entity is "fifo_generator_ramfifo";
end fifo_async_103x16_fifo_generator_ramfifo;
architecture STRUCTURE of fifo_async_103x16_fifo_generator_ramfifo is
signal RD_RST : STD_LOGIC;
signal \^rst\ : STD_LOGIC;
signal WR_RST : STD_LOGIC;
signal \n_0_gntv_or_sync_fifo.gcx.clkx\ : STD_LOGIC;
signal \n_10_gntv_or_sync_fifo.gcx.clkx\ : STD_LOGIC;
signal \n_11_gntv_or_sync_fifo.gcx.clkx\ : STD_LOGIC;
signal n_2_rstblk : STD_LOGIC;
signal \n_5_gntv_or_sync_fifo.gcx.clkx\ : STD_LOGIC;
signal \n_7_gntv_or_sync_fifo.gl0.rd\ : STD_LOGIC;
signal \n_8_gntv_or_sync_fifo.gl0.rd\ : STD_LOGIC;
signal \n_9_gntv_or_sync_fifo.gl0.rd\ : STD_LOGIC;
signal p_0_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_15_out : STD_LOGIC;
signal p_1_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_20_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_3_out : STD_LOGIC;
signal p_8_out : STD_LOGIC_VECTOR ( 2 downto 0 );
signal p_9_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal ram_rd_en_i : STD_LOGIC;
signal rd_pntr_plus1 : STD_LOGIC_VECTOR ( 2 downto 0 );
signal rd_rst_i : STD_LOGIC_VECTOR ( 0 to 0 );
signal rst_d2 : STD_LOGIC;
signal rst_full_gen_i : STD_LOGIC;
signal wr_pntr_plus2 : STD_LOGIC_VECTOR ( 3 downto 0 );
begin
\gntv_or_sync_fifo.gcx.clkx\: entity work.fifo_async_103x16_clk_x_pntrs
port map (
D(0) => \n_0_gntv_or_sync_fifo.gcx.clkx\,
E(0) => p_3_out,
I1(2 downto 0) => rd_pntr_plus1(2 downto 0),
I2(3 downto 0) => wr_pntr_plus2(3 downto 0),
I3(3 downto 0) => p_9_out(3 downto 0),
I4(0) => \^rst\,
I5(0) => RD_RST,
I6(3) => p_20_out(3),
I6(2) => \n_7_gntv_or_sync_fifo.gl0.rd\,
I6(1) => \n_8_gntv_or_sync_fifo.gl0.rd\,
I6(0) => \n_9_gntv_or_sync_fifo.gl0.rd\,
O1(3 downto 0) => p_0_out(3 downto 0),
O2 => \n_5_gntv_or_sync_fifo.gcx.clkx\,
O3(3 downto 0) => p_1_out(3 downto 0),
O4 => \n_10_gntv_or_sync_fifo.gcx.clkx\,
O5 => \n_11_gntv_or_sync_fifo.gcx.clkx\,
Q(2 downto 0) => p_8_out(2 downto 0),
rd_clk => rd_clk,
wr_clk => wr_clk
);
\gntv_or_sync_fifo.gl0.rd\: entity work.fifo_async_103x16_rd_logic
port map (
E(0) => p_15_out,
I1 => \n_5_gntv_or_sync_fifo.gcx.clkx\,
I6(3) => p_20_out(3),
I6(2) => \n_7_gntv_or_sync_fifo.gl0.rd\,
I6(1) => \n_8_gntv_or_sync_fifo.gl0.rd\,
I6(0) => \n_9_gntv_or_sync_fifo.gl0.rd\,
O1(2 downto 0) => rd_pntr_plus1(2 downto 0),
O2(0) => ram_rd_en_i,
O3(3 downto 0) => p_1_out(3 downto 0),
O4(2 downto 0) => p_20_out(2 downto 0),
Q(0) => n_2_rstblk,
empty => empty,
rd_clk => rd_clk,
rd_en => rd_en
);
\gntv_or_sync_fifo.gl0.wr\: entity work.fifo_async_103x16_wr_logic
port map (
D(0) => \n_0_gntv_or_sync_fifo.gcx.clkx\,
E(0) => p_3_out,
I1 => \n_10_gntv_or_sync_fifo.gcx.clkx\,
I2 => \n_11_gntv_or_sync_fifo.gcx.clkx\,
I3(0) => WR_RST,
O1(3 downto 0) => p_0_out(3 downto 0),
O2(3 downto 0) => wr_pntr_plus2(3 downto 0),
O3(3 downto 0) => p_9_out(3 downto 0),
Q(2 downto 0) => p_8_out(2 downto 0),
full => full,
prog_full => prog_full,
rst_d2 => rst_d2,
rst_full_gen_i => rst_full_gen_i,
wr_clk => wr_clk,
wr_en => wr_en
);
\gntv_or_sync_fifo.mem\: entity work.fifo_async_103x16_memory
port map (
ADDRA(3 downto 0) => p_20_out(3 downto 0),
E(0) => ram_rd_en_i,
I1(0) => p_3_out,
I2(0) => p_15_out,
O3(3 downto 0) => p_9_out(3 downto 0),
Q(0) => rd_rst_i(0),
din(102 downto 0) => din(102 downto 0),
dout(102 downto 0) => dout(102 downto 0),
rd_clk => rd_clk,
wr_clk => wr_clk
);
rstblk: entity work.fifo_async_103x16_reset_blk_ramfifo
port map (
O1(1) => WR_RST,
O1(0) => \^rst\,
Q(2) => n_2_rstblk,
Q(1) => RD_RST,
Q(0) => rd_rst_i(0),
rd_clk => rd_clk,
rst => rst,
rst_d2 => rst_d2,
rst_full_gen_i => rst_full_gen_i,
wr_clk => wr_clk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_async_103x16_fifo_generator_top is
port (
dout : out STD_LOGIC_VECTOR ( 102 downto 0 );
empty : out STD_LOGIC;
full : out STD_LOGIC;
prog_full : out STD_LOGIC;
wr_en : in STD_LOGIC;
rd_clk : in STD_LOGIC;
wr_clk : in STD_LOGIC;
rst : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 102 downto 0 );
rd_en : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_async_103x16_fifo_generator_top : entity is "fifo_generator_top";
end fifo_async_103x16_fifo_generator_top;
architecture STRUCTURE of fifo_async_103x16_fifo_generator_top is
begin
\grf.rf\: entity work.fifo_async_103x16_fifo_generator_ramfifo
port map (
din(102 downto 0) => din(102 downto 0),
dout(102 downto 0) => dout(102 downto 0),
empty => empty,
full => full,
prog_full => prog_full,
rd_clk => rd_clk,
rd_en => rd_en,
rst => rst,
wr_clk => wr_clk,
wr_en => wr_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_async_103x16_fifo_generator_v12_0_synth is
port (
dout : out STD_LOGIC_VECTOR ( 102 downto 0 );
empty : out STD_LOGIC;
full : out STD_LOGIC;
prog_full : out STD_LOGIC;
wr_en : in STD_LOGIC;
rd_clk : in STD_LOGIC;
wr_clk : in STD_LOGIC;
rst : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 102 downto 0 );
rd_en : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_async_103x16_fifo_generator_v12_0_synth : entity is "fifo_generator_v12_0_synth";
end fifo_async_103x16_fifo_generator_v12_0_synth;
architecture STRUCTURE of fifo_async_103x16_fifo_generator_v12_0_synth is
begin
\gconvfifo.rf\: entity work.fifo_async_103x16_fifo_generator_top
port map (
din(102 downto 0) => din(102 downto 0),
dout(102 downto 0) => dout(102 downto 0),
empty => empty,
full => full,
prog_full => prog_full,
rd_clk => rd_clk,
rd_en => rd_en,
rst => rst,
wr_clk => wr_clk,
wr_en => wr_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ is
port (
backup : in STD_LOGIC;
backup_marker : in STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC;
srst : in STD_LOGIC;
wr_clk : in STD_LOGIC;
wr_rst : in STD_LOGIC;
rd_clk : in STD_LOGIC;
rd_rst : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 102 downto 0 );
wr_en : in STD_LOGIC;
rd_en : in STD_LOGIC;
prog_empty_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
prog_empty_thresh_assert : in STD_LOGIC_VECTOR ( 3 downto 0 );
prog_empty_thresh_negate : in STD_LOGIC_VECTOR ( 3 downto 0 );
prog_full_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
prog_full_thresh_assert : in STD_LOGIC_VECTOR ( 3 downto 0 );
prog_full_thresh_negate : in STD_LOGIC_VECTOR ( 3 downto 0 );
int_clk : in STD_LOGIC;
injectdbiterr : in STD_LOGIC;
injectsbiterr : in STD_LOGIC;
sleep : in STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 102 downto 0 );
full : out STD_LOGIC;
almost_full : out STD_LOGIC;
wr_ack : out STD_LOGIC;
overflow : out STD_LOGIC;
empty : out STD_LOGIC;
almost_empty : out STD_LOGIC;
valid : out STD_LOGIC;
underflow : out STD_LOGIC;
data_count : out STD_LOGIC_VECTOR ( 3 downto 0 );
rd_data_count : out STD_LOGIC_VECTOR ( 3 downto 0 );
wr_data_count : out STD_LOGIC_VECTOR ( 3 downto 0 );
prog_full : out STD_LOGIC;
prog_empty : out STD_LOGIC;
sbiterr : out STD_LOGIC;
dbiterr : out STD_LOGIC;
wr_rst_busy : out STD_LOGIC;
rd_rst_busy : out STD_LOGIC;
m_aclk : in STD_LOGIC;
s_aclk : in STD_LOGIC;
s_aresetn : in STD_LOGIC;
m_aclk_en : in STD_LOGIC;
s_aclk_en : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_buser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
m_axi_awid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awuser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_wlast : out STD_LOGIC;
m_axi_wuser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_buser : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_aruser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_ruser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_arid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_aruser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rlast : in STD_LOGIC;
m_axi_ruser : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC;
s_axis_tvalid : in STD_LOGIC;
s_axis_tready : out STD_LOGIC;
s_axis_tdata : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axis_tstrb : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tkeep : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tlast : in STD_LOGIC;
s_axis_tid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tdest : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tuser : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axis_tvalid : out STD_LOGIC;
m_axis_tready : in STD_LOGIC;
m_axis_tdata : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axis_tstrb : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tkeep : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tlast : out STD_LOGIC;
m_axis_tid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tdest : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tuser : out STD_LOGIC_VECTOR ( 3 downto 0 );
axi_aw_injectsbiterr : in STD_LOGIC;
axi_aw_injectdbiterr : in STD_LOGIC;
axi_aw_prog_full_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_aw_prog_empty_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_aw_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_aw_wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_aw_rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_aw_sbiterr : out STD_LOGIC;
axi_aw_dbiterr : out STD_LOGIC;
axi_aw_overflow : out STD_LOGIC;
axi_aw_underflow : out STD_LOGIC;
axi_aw_prog_full : out STD_LOGIC;
axi_aw_prog_empty : out STD_LOGIC;
axi_w_injectsbiterr : in STD_LOGIC;
axi_w_injectdbiterr : in STD_LOGIC;
axi_w_prog_full_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_w_prog_empty_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_w_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_w_wr_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_w_rd_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_w_sbiterr : out STD_LOGIC;
axi_w_dbiterr : out STD_LOGIC;
axi_w_overflow : out STD_LOGIC;
axi_w_underflow : out STD_LOGIC;
axi_w_prog_full : out STD_LOGIC;
axi_w_prog_empty : out STD_LOGIC;
axi_b_injectsbiterr : in STD_LOGIC;
axi_b_injectdbiterr : in STD_LOGIC;
axi_b_prog_full_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_b_prog_empty_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_b_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_b_wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_b_rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_b_sbiterr : out STD_LOGIC;
axi_b_dbiterr : out STD_LOGIC;
axi_b_overflow : out STD_LOGIC;
axi_b_underflow : out STD_LOGIC;
axi_b_prog_full : out STD_LOGIC;
axi_b_prog_empty : out STD_LOGIC;
axi_ar_injectsbiterr : in STD_LOGIC;
axi_ar_injectdbiterr : in STD_LOGIC;
axi_ar_prog_full_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_ar_prog_empty_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_ar_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_ar_wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_ar_rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_ar_sbiterr : out STD_LOGIC;
axi_ar_dbiterr : out STD_LOGIC;
axi_ar_overflow : out STD_LOGIC;
axi_ar_underflow : out STD_LOGIC;
axi_ar_prog_full : out STD_LOGIC;
axi_ar_prog_empty : out STD_LOGIC;
axi_r_injectsbiterr : in STD_LOGIC;
axi_r_injectdbiterr : in STD_LOGIC;
axi_r_prog_full_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_r_prog_empty_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_r_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_r_wr_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_r_rd_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_r_sbiterr : out STD_LOGIC;
axi_r_dbiterr : out STD_LOGIC;
axi_r_overflow : out STD_LOGIC;
axi_r_underflow : out STD_LOGIC;
axi_r_prog_full : out STD_LOGIC;
axi_r_prog_empty : out STD_LOGIC;
axis_injectsbiterr : in STD_LOGIC;
axis_injectdbiterr : in STD_LOGIC;
axis_prog_full_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axis_prog_empty_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axis_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axis_wr_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axis_rd_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axis_sbiterr : out STD_LOGIC;
axis_dbiterr : out STD_LOGIC;
axis_overflow : out STD_LOGIC;
axis_underflow : out STD_LOGIC;
axis_prog_full : out STD_LOGIC;
axis_prog_empty : out STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is "fifo_generator_v12_0";
attribute C_COMMON_CLOCK : integer;
attribute C_COMMON_CLOCK of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_COUNT_TYPE : integer;
attribute C_COUNT_TYPE of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_DATA_COUNT_WIDTH : integer;
attribute C_DATA_COUNT_WIDTH of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 4;
attribute C_DEFAULT_VALUE : string;
attribute C_DEFAULT_VALUE of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is "BlankString";
attribute C_DIN_WIDTH : integer;
attribute C_DIN_WIDTH of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 103;
attribute C_DOUT_RST_VAL : string;
attribute C_DOUT_RST_VAL of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is "0";
attribute C_DOUT_WIDTH : integer;
attribute C_DOUT_WIDTH of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 103;
attribute C_ENABLE_RLOCS : integer;
attribute C_ENABLE_RLOCS of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_FAMILY : string;
attribute C_FAMILY of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is "zynq";
attribute C_FULL_FLAGS_RST_VAL : integer;
attribute C_FULL_FLAGS_RST_VAL of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_HAS_ALMOST_EMPTY : integer;
attribute C_HAS_ALMOST_EMPTY of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_ALMOST_FULL : integer;
attribute C_HAS_ALMOST_FULL of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_BACKUP : integer;
attribute C_HAS_BACKUP of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_DATA_COUNT : integer;
attribute C_HAS_DATA_COUNT of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_INT_CLK : integer;
attribute C_HAS_INT_CLK of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_MEMINIT_FILE : integer;
attribute C_HAS_MEMINIT_FILE of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_OVERFLOW : integer;
attribute C_HAS_OVERFLOW of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_RD_DATA_COUNT : integer;
attribute C_HAS_RD_DATA_COUNT of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_RD_RST : integer;
attribute C_HAS_RD_RST of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_RST : integer;
attribute C_HAS_RST of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_HAS_SRST : integer;
attribute C_HAS_SRST of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_UNDERFLOW : integer;
attribute C_HAS_UNDERFLOW of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_VALID : integer;
attribute C_HAS_VALID of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_WR_ACK : integer;
attribute C_HAS_WR_ACK of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_WR_DATA_COUNT : integer;
attribute C_HAS_WR_DATA_COUNT of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_WR_RST : integer;
attribute C_HAS_WR_RST of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_IMPLEMENTATION_TYPE : integer;
attribute C_IMPLEMENTATION_TYPE of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 2;
attribute C_INIT_WR_PNTR_VAL : integer;
attribute C_INIT_WR_PNTR_VAL of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_MEMORY_TYPE : integer;
attribute C_MEMORY_TYPE of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 2;
attribute C_MIF_FILE_NAME : string;
attribute C_MIF_FILE_NAME of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is "BlankString";
attribute C_OPTIMIZATION_MODE : integer;
attribute C_OPTIMIZATION_MODE of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_OVERFLOW_LOW : integer;
attribute C_OVERFLOW_LOW of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_PRELOAD_LATENCY : integer;
attribute C_PRELOAD_LATENCY of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_PRELOAD_REGS : integer;
attribute C_PRELOAD_REGS of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_PRIM_FIFO_TYPE : string;
attribute C_PRIM_FIFO_TYPE of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is "512x72";
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 4;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL : integer;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 5;
attribute C_PROG_EMPTY_TYPE : integer;
attribute C_PROG_EMPTY_TYPE of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_PROG_FULL_THRESH_ASSERT_VAL : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 12;
attribute C_PROG_FULL_THRESH_NEGATE_VAL : integer;
attribute C_PROG_FULL_THRESH_NEGATE_VAL of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 11;
attribute C_PROG_FULL_TYPE : integer;
attribute C_PROG_FULL_TYPE of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_RD_DATA_COUNT_WIDTH : integer;
attribute C_RD_DATA_COUNT_WIDTH of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 4;
attribute C_RD_DEPTH : integer;
attribute C_RD_DEPTH of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 16;
attribute C_RD_FREQ : integer;
attribute C_RD_FREQ of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_RD_PNTR_WIDTH : integer;
attribute C_RD_PNTR_WIDTH of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 4;
attribute C_UNDERFLOW_LOW : integer;
attribute C_UNDERFLOW_LOW of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_USE_DOUT_RST : integer;
attribute C_USE_DOUT_RST of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_USE_EMBEDDED_REG : integer;
attribute C_USE_EMBEDDED_REG of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_USE_PIPELINE_REG : integer;
attribute C_USE_PIPELINE_REG of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_POWER_SAVING_MODE : integer;
attribute C_POWER_SAVING_MODE of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_USE_FIFO16_FLAGS : integer;
attribute C_USE_FIFO16_FLAGS of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_USE_FWFT_DATA_COUNT : integer;
attribute C_USE_FWFT_DATA_COUNT of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_VALID_LOW : integer;
attribute C_VALID_LOW of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_WR_ACK_LOW : integer;
attribute C_WR_ACK_LOW of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_WR_DATA_COUNT_WIDTH : integer;
attribute C_WR_DATA_COUNT_WIDTH of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 4;
attribute C_WR_DEPTH : integer;
attribute C_WR_DEPTH of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 16;
attribute C_WR_FREQ : integer;
attribute C_WR_FREQ of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_WR_PNTR_WIDTH : integer;
attribute C_WR_PNTR_WIDTH of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 4;
attribute C_WR_RESPONSE_LATENCY : integer;
attribute C_WR_RESPONSE_LATENCY of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_MSGON_VAL : integer;
attribute C_MSGON_VAL of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_ENABLE_RST_SYNC : integer;
attribute C_ENABLE_RST_SYNC of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_ERROR_INJECTION_TYPE : integer;
attribute C_ERROR_INJECTION_TYPE of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_SYNCHRONIZER_STAGE : integer;
attribute C_SYNCHRONIZER_STAGE of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 2;
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_HAS_AXI_WR_CHANNEL : integer;
attribute C_HAS_AXI_WR_CHANNEL of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_HAS_AXI_RD_CHANNEL : integer;
attribute C_HAS_AXI_RD_CHANNEL of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_HAS_SLAVE_CE : integer;
attribute C_HAS_SLAVE_CE of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_MASTER_CE : integer;
attribute C_HAS_MASTER_CE of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_ADD_NGC_CONSTRAINT : integer;
attribute C_ADD_NGC_CONSTRAINT of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_USE_COMMON_OVERFLOW : integer;
attribute C_USE_COMMON_OVERFLOW of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_USE_COMMON_UNDERFLOW : integer;
attribute C_USE_COMMON_UNDERFLOW of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_USE_DEFAULT_SETTINGS : integer;
attribute C_USE_DEFAULT_SETTINGS of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 32;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 64;
attribute C_AXI_LEN_WIDTH : integer;
attribute C_AXI_LEN_WIDTH of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 8;
attribute C_AXI_LOCK_WIDTH : integer;
attribute C_AXI_LOCK_WIDTH of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_AXI_AWUSER : integer;
attribute C_HAS_AXI_AWUSER of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_AXI_WUSER : integer;
attribute C_HAS_AXI_WUSER of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_AXI_BUSER : integer;
attribute C_HAS_AXI_BUSER of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_AXI_ARUSER : integer;
attribute C_HAS_AXI_ARUSER of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_AXI_RUSER : integer;
attribute C_HAS_AXI_RUSER of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_HAS_AXIS_TDATA : integer;
attribute C_HAS_AXIS_TDATA of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_HAS_AXIS_TID : integer;
attribute C_HAS_AXIS_TID of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_AXIS_TDEST : integer;
attribute C_HAS_AXIS_TDEST of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_AXIS_TUSER : integer;
attribute C_HAS_AXIS_TUSER of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_HAS_AXIS_TREADY : integer;
attribute C_HAS_AXIS_TREADY of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_HAS_AXIS_TLAST : integer;
attribute C_HAS_AXIS_TLAST of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_AXIS_TSTRB : integer;
attribute C_HAS_AXIS_TSTRB of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_AXIS_TKEEP : integer;
attribute C_HAS_AXIS_TKEEP of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_AXIS_TDATA_WIDTH : integer;
attribute C_AXIS_TDATA_WIDTH of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 8;
attribute C_AXIS_TID_WIDTH : integer;
attribute C_AXIS_TID_WIDTH of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_AXIS_TDEST_WIDTH : integer;
attribute C_AXIS_TDEST_WIDTH of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_AXIS_TUSER_WIDTH : integer;
attribute C_AXIS_TUSER_WIDTH of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 4;
attribute C_AXIS_TSTRB_WIDTH : integer;
attribute C_AXIS_TSTRB_WIDTH of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_AXIS_TKEEP_WIDTH : integer;
attribute C_AXIS_TKEEP_WIDTH of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_WACH_TYPE : integer;
attribute C_WACH_TYPE of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_WDCH_TYPE : integer;
attribute C_WDCH_TYPE of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_WRCH_TYPE : integer;
attribute C_WRCH_TYPE of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_RACH_TYPE : integer;
attribute C_RACH_TYPE of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_RDCH_TYPE : integer;
attribute C_RDCH_TYPE of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_AXIS_TYPE : integer;
attribute C_AXIS_TYPE of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_IMPLEMENTATION_TYPE_WACH : integer;
attribute C_IMPLEMENTATION_TYPE_WACH of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_IMPLEMENTATION_TYPE_WDCH : integer;
attribute C_IMPLEMENTATION_TYPE_WDCH of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_IMPLEMENTATION_TYPE_WRCH : integer;
attribute C_IMPLEMENTATION_TYPE_WRCH of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_IMPLEMENTATION_TYPE_RACH : integer;
attribute C_IMPLEMENTATION_TYPE_RACH of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_IMPLEMENTATION_TYPE_RDCH : integer;
attribute C_IMPLEMENTATION_TYPE_RDCH of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_IMPLEMENTATION_TYPE_AXIS : integer;
attribute C_IMPLEMENTATION_TYPE_AXIS of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_APPLICATION_TYPE_WACH : integer;
attribute C_APPLICATION_TYPE_WACH of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_APPLICATION_TYPE_WDCH : integer;
attribute C_APPLICATION_TYPE_WDCH of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_APPLICATION_TYPE_WRCH : integer;
attribute C_APPLICATION_TYPE_WRCH of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_APPLICATION_TYPE_RACH : integer;
attribute C_APPLICATION_TYPE_RACH of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_APPLICATION_TYPE_RDCH : integer;
attribute C_APPLICATION_TYPE_RDCH of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_APPLICATION_TYPE_AXIS : integer;
attribute C_APPLICATION_TYPE_AXIS of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_PRIM_FIFO_TYPE_WACH : string;
attribute C_PRIM_FIFO_TYPE_WACH of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is "512x36";
attribute C_PRIM_FIFO_TYPE_WDCH : string;
attribute C_PRIM_FIFO_TYPE_WDCH of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is "1kx36";
attribute C_PRIM_FIFO_TYPE_WRCH : string;
attribute C_PRIM_FIFO_TYPE_WRCH of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is "512x36";
attribute C_PRIM_FIFO_TYPE_RACH : string;
attribute C_PRIM_FIFO_TYPE_RACH of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is "512x36";
attribute C_PRIM_FIFO_TYPE_RDCH : string;
attribute C_PRIM_FIFO_TYPE_RDCH of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is "1kx36";
attribute C_PRIM_FIFO_TYPE_AXIS : string;
attribute C_PRIM_FIFO_TYPE_AXIS of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is "1kx18";
attribute C_USE_ECC_WACH : integer;
attribute C_USE_ECC_WACH of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_USE_ECC_WDCH : integer;
attribute C_USE_ECC_WDCH of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_USE_ECC_WRCH : integer;
attribute C_USE_ECC_WRCH of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_USE_ECC_RACH : integer;
attribute C_USE_ECC_RACH of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_USE_ECC_RDCH : integer;
attribute C_USE_ECC_RDCH of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_USE_ECC_AXIS : integer;
attribute C_USE_ECC_AXIS of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_ERROR_INJECTION_TYPE_WACH : integer;
attribute C_ERROR_INJECTION_TYPE_WACH of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_ERROR_INJECTION_TYPE_WDCH : integer;
attribute C_ERROR_INJECTION_TYPE_WDCH of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_ERROR_INJECTION_TYPE_WRCH : integer;
attribute C_ERROR_INJECTION_TYPE_WRCH of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_ERROR_INJECTION_TYPE_RACH : integer;
attribute C_ERROR_INJECTION_TYPE_RACH of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_ERROR_INJECTION_TYPE_RDCH : integer;
attribute C_ERROR_INJECTION_TYPE_RDCH of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_ERROR_INJECTION_TYPE_AXIS : integer;
attribute C_ERROR_INJECTION_TYPE_AXIS of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_DIN_WIDTH_WACH : integer;
attribute C_DIN_WIDTH_WACH of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 32;
attribute C_DIN_WIDTH_WDCH : integer;
attribute C_DIN_WIDTH_WDCH of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 64;
attribute C_DIN_WIDTH_WRCH : integer;
attribute C_DIN_WIDTH_WRCH of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 2;
attribute C_DIN_WIDTH_RACH : integer;
attribute C_DIN_WIDTH_RACH of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 32;
attribute C_DIN_WIDTH_RDCH : integer;
attribute C_DIN_WIDTH_RDCH of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 64;
attribute C_DIN_WIDTH_AXIS : integer;
attribute C_DIN_WIDTH_AXIS of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_WR_DEPTH_WACH : integer;
attribute C_WR_DEPTH_WACH of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 16;
attribute C_WR_DEPTH_WDCH : integer;
attribute C_WR_DEPTH_WDCH of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 1024;
attribute C_WR_DEPTH_WRCH : integer;
attribute C_WR_DEPTH_WRCH of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 16;
attribute C_WR_DEPTH_RACH : integer;
attribute C_WR_DEPTH_RACH of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 16;
attribute C_WR_DEPTH_RDCH : integer;
attribute C_WR_DEPTH_RDCH of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 1024;
attribute C_WR_DEPTH_AXIS : integer;
attribute C_WR_DEPTH_AXIS of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 1024;
attribute C_WR_PNTR_WIDTH_WACH : integer;
attribute C_WR_PNTR_WIDTH_WACH of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 4;
attribute C_WR_PNTR_WIDTH_WDCH : integer;
attribute C_WR_PNTR_WIDTH_WDCH of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 10;
attribute C_WR_PNTR_WIDTH_WRCH : integer;
attribute C_WR_PNTR_WIDTH_WRCH of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 4;
attribute C_WR_PNTR_WIDTH_RACH : integer;
attribute C_WR_PNTR_WIDTH_RACH of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 4;
attribute C_WR_PNTR_WIDTH_RDCH : integer;
attribute C_WR_PNTR_WIDTH_RDCH of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 10;
attribute C_WR_PNTR_WIDTH_AXIS : integer;
attribute C_WR_PNTR_WIDTH_AXIS of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 10;
attribute C_HAS_DATA_COUNTS_WACH : integer;
attribute C_HAS_DATA_COUNTS_WACH of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_DATA_COUNTS_WDCH : integer;
attribute C_HAS_DATA_COUNTS_WDCH of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_DATA_COUNTS_WRCH : integer;
attribute C_HAS_DATA_COUNTS_WRCH of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_DATA_COUNTS_RACH : integer;
attribute C_HAS_DATA_COUNTS_RACH of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_DATA_COUNTS_RDCH : integer;
attribute C_HAS_DATA_COUNTS_RDCH of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_DATA_COUNTS_AXIS : integer;
attribute C_HAS_DATA_COUNTS_AXIS of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_PROG_FLAGS_WACH : integer;
attribute C_HAS_PROG_FLAGS_WACH of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_PROG_FLAGS_WDCH : integer;
attribute C_HAS_PROG_FLAGS_WDCH of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_PROG_FLAGS_WRCH : integer;
attribute C_HAS_PROG_FLAGS_WRCH of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_PROG_FLAGS_RACH : integer;
attribute C_HAS_PROG_FLAGS_RACH of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_PROG_FLAGS_RDCH : integer;
attribute C_HAS_PROG_FLAGS_RDCH of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_PROG_FLAGS_AXIS : integer;
attribute C_HAS_PROG_FLAGS_AXIS of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_PROG_FULL_TYPE_WACH : integer;
attribute C_PROG_FULL_TYPE_WACH of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_PROG_FULL_TYPE_WDCH : integer;
attribute C_PROG_FULL_TYPE_WDCH of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_PROG_FULL_TYPE_WRCH : integer;
attribute C_PROG_FULL_TYPE_WRCH of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_PROG_FULL_TYPE_RACH : integer;
attribute C_PROG_FULL_TYPE_RACH of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_PROG_FULL_TYPE_RDCH : integer;
attribute C_PROG_FULL_TYPE_RDCH of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_PROG_FULL_TYPE_AXIS : integer;
attribute C_PROG_FULL_TYPE_AXIS of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 1023;
attribute C_PROG_EMPTY_TYPE_WACH : integer;
attribute C_PROG_EMPTY_TYPE_WACH of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_PROG_EMPTY_TYPE_WDCH : integer;
attribute C_PROG_EMPTY_TYPE_WDCH of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_PROG_EMPTY_TYPE_WRCH : integer;
attribute C_PROG_EMPTY_TYPE_WRCH of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_PROG_EMPTY_TYPE_RACH : integer;
attribute C_PROG_EMPTY_TYPE_RACH of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_PROG_EMPTY_TYPE_RDCH : integer;
attribute C_PROG_EMPTY_TYPE_RDCH of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_PROG_EMPTY_TYPE_AXIS : integer;
attribute C_PROG_EMPTY_TYPE_AXIS of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 1022;
attribute C_REG_SLICE_MODE_WACH : integer;
attribute C_REG_SLICE_MODE_WACH of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_REG_SLICE_MODE_WDCH : integer;
attribute C_REG_SLICE_MODE_WDCH of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_REG_SLICE_MODE_WRCH : integer;
attribute C_REG_SLICE_MODE_WRCH of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_REG_SLICE_MODE_RACH : integer;
attribute C_REG_SLICE_MODE_RACH of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_REG_SLICE_MODE_RDCH : integer;
attribute C_REG_SLICE_MODE_RDCH of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_REG_SLICE_MODE_AXIS : integer;
attribute C_REG_SLICE_MODE_AXIS of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 0;
end \fifo_async_103x16_fifo_generator_v12_0__parameterized0\;
architecture STRUCTURE of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ is
signal \<const0>\ : STD_LOGIC;
signal \<const1>\ : STD_LOGIC;
begin
almost_empty <= \<const0>\;
almost_full <= \<const0>\;
axi_ar_data_count(4) <= \<const0>\;
axi_ar_data_count(3) <= \<const0>\;
axi_ar_data_count(2) <= \<const0>\;
axi_ar_data_count(1) <= \<const0>\;
axi_ar_data_count(0) <= \<const0>\;
axi_ar_dbiterr <= \<const0>\;
axi_ar_overflow <= \<const0>\;
axi_ar_prog_empty <= \<const1>\;
axi_ar_prog_full <= \<const0>\;
axi_ar_rd_data_count(4) <= \<const0>\;
axi_ar_rd_data_count(3) <= \<const0>\;
axi_ar_rd_data_count(2) <= \<const0>\;
axi_ar_rd_data_count(1) <= \<const0>\;
axi_ar_rd_data_count(0) <= \<const0>\;
axi_ar_sbiterr <= \<const0>\;
axi_ar_underflow <= \<const0>\;
axi_ar_wr_data_count(4) <= \<const0>\;
axi_ar_wr_data_count(3) <= \<const0>\;
axi_ar_wr_data_count(2) <= \<const0>\;
axi_ar_wr_data_count(1) <= \<const0>\;
axi_ar_wr_data_count(0) <= \<const0>\;
axi_aw_data_count(4) <= \<const0>\;
axi_aw_data_count(3) <= \<const0>\;
axi_aw_data_count(2) <= \<const0>\;
axi_aw_data_count(1) <= \<const0>\;
axi_aw_data_count(0) <= \<const0>\;
axi_aw_dbiterr <= \<const0>\;
axi_aw_overflow <= \<const0>\;
axi_aw_prog_empty <= \<const1>\;
axi_aw_prog_full <= \<const0>\;
axi_aw_rd_data_count(4) <= \<const0>\;
axi_aw_rd_data_count(3) <= \<const0>\;
axi_aw_rd_data_count(2) <= \<const0>\;
axi_aw_rd_data_count(1) <= \<const0>\;
axi_aw_rd_data_count(0) <= \<const0>\;
axi_aw_sbiterr <= \<const0>\;
axi_aw_underflow <= \<const0>\;
axi_aw_wr_data_count(4) <= \<const0>\;
axi_aw_wr_data_count(3) <= \<const0>\;
axi_aw_wr_data_count(2) <= \<const0>\;
axi_aw_wr_data_count(1) <= \<const0>\;
axi_aw_wr_data_count(0) <= \<const0>\;
axi_b_data_count(4) <= \<const0>\;
axi_b_data_count(3) <= \<const0>\;
axi_b_data_count(2) <= \<const0>\;
axi_b_data_count(1) <= \<const0>\;
axi_b_data_count(0) <= \<const0>\;
axi_b_dbiterr <= \<const0>\;
axi_b_overflow <= \<const0>\;
axi_b_prog_empty <= \<const1>\;
axi_b_prog_full <= \<const0>\;
axi_b_rd_data_count(4) <= \<const0>\;
axi_b_rd_data_count(3) <= \<const0>\;
axi_b_rd_data_count(2) <= \<const0>\;
axi_b_rd_data_count(1) <= \<const0>\;
axi_b_rd_data_count(0) <= \<const0>\;
axi_b_sbiterr <= \<const0>\;
axi_b_underflow <= \<const0>\;
axi_b_wr_data_count(4) <= \<const0>\;
axi_b_wr_data_count(3) <= \<const0>\;
axi_b_wr_data_count(2) <= \<const0>\;
axi_b_wr_data_count(1) <= \<const0>\;
axi_b_wr_data_count(0) <= \<const0>\;
axi_r_data_count(10) <= \<const0>\;
axi_r_data_count(9) <= \<const0>\;
axi_r_data_count(8) <= \<const0>\;
axi_r_data_count(7) <= \<const0>\;
axi_r_data_count(6) <= \<const0>\;
axi_r_data_count(5) <= \<const0>\;
axi_r_data_count(4) <= \<const0>\;
axi_r_data_count(3) <= \<const0>\;
axi_r_data_count(2) <= \<const0>\;
axi_r_data_count(1) <= \<const0>\;
axi_r_data_count(0) <= \<const0>\;
axi_r_dbiterr <= \<const0>\;
axi_r_overflow <= \<const0>\;
axi_r_prog_empty <= \<const1>\;
axi_r_prog_full <= \<const0>\;
axi_r_rd_data_count(10) <= \<const0>\;
axi_r_rd_data_count(9) <= \<const0>\;
axi_r_rd_data_count(8) <= \<const0>\;
axi_r_rd_data_count(7) <= \<const0>\;
axi_r_rd_data_count(6) <= \<const0>\;
axi_r_rd_data_count(5) <= \<const0>\;
axi_r_rd_data_count(4) <= \<const0>\;
axi_r_rd_data_count(3) <= \<const0>\;
axi_r_rd_data_count(2) <= \<const0>\;
axi_r_rd_data_count(1) <= \<const0>\;
axi_r_rd_data_count(0) <= \<const0>\;
axi_r_sbiterr <= \<const0>\;
axi_r_underflow <= \<const0>\;
axi_r_wr_data_count(10) <= \<const0>\;
axi_r_wr_data_count(9) <= \<const0>\;
axi_r_wr_data_count(8) <= \<const0>\;
axi_r_wr_data_count(7) <= \<const0>\;
axi_r_wr_data_count(6) <= \<const0>\;
axi_r_wr_data_count(5) <= \<const0>\;
axi_r_wr_data_count(4) <= \<const0>\;
axi_r_wr_data_count(3) <= \<const0>\;
axi_r_wr_data_count(2) <= \<const0>\;
axi_r_wr_data_count(1) <= \<const0>\;
axi_r_wr_data_count(0) <= \<const0>\;
axi_w_data_count(10) <= \<const0>\;
axi_w_data_count(9) <= \<const0>\;
axi_w_data_count(8) <= \<const0>\;
axi_w_data_count(7) <= \<const0>\;
axi_w_data_count(6) <= \<const0>\;
axi_w_data_count(5) <= \<const0>\;
axi_w_data_count(4) <= \<const0>\;
axi_w_data_count(3) <= \<const0>\;
axi_w_data_count(2) <= \<const0>\;
axi_w_data_count(1) <= \<const0>\;
axi_w_data_count(0) <= \<const0>\;
axi_w_dbiterr <= \<const0>\;
axi_w_overflow <= \<const0>\;
axi_w_prog_empty <= \<const1>\;
axi_w_prog_full <= \<const0>\;
axi_w_rd_data_count(10) <= \<const0>\;
axi_w_rd_data_count(9) <= \<const0>\;
axi_w_rd_data_count(8) <= \<const0>\;
axi_w_rd_data_count(7) <= \<const0>\;
axi_w_rd_data_count(6) <= \<const0>\;
axi_w_rd_data_count(5) <= \<const0>\;
axi_w_rd_data_count(4) <= \<const0>\;
axi_w_rd_data_count(3) <= \<const0>\;
axi_w_rd_data_count(2) <= \<const0>\;
axi_w_rd_data_count(1) <= \<const0>\;
axi_w_rd_data_count(0) <= \<const0>\;
axi_w_sbiterr <= \<const0>\;
axi_w_underflow <= \<const0>\;
axi_w_wr_data_count(10) <= \<const0>\;
axi_w_wr_data_count(9) <= \<const0>\;
axi_w_wr_data_count(8) <= \<const0>\;
axi_w_wr_data_count(7) <= \<const0>\;
axi_w_wr_data_count(6) <= \<const0>\;
axi_w_wr_data_count(5) <= \<const0>\;
axi_w_wr_data_count(4) <= \<const0>\;
axi_w_wr_data_count(3) <= \<const0>\;
axi_w_wr_data_count(2) <= \<const0>\;
axi_w_wr_data_count(1) <= \<const0>\;
axi_w_wr_data_count(0) <= \<const0>\;
axis_data_count(10) <= \<const0>\;
axis_data_count(9) <= \<const0>\;
axis_data_count(8) <= \<const0>\;
axis_data_count(7) <= \<const0>\;
axis_data_count(6) <= \<const0>\;
axis_data_count(5) <= \<const0>\;
axis_data_count(4) <= \<const0>\;
axis_data_count(3) <= \<const0>\;
axis_data_count(2) <= \<const0>\;
axis_data_count(1) <= \<const0>\;
axis_data_count(0) <= \<const0>\;
axis_dbiterr <= \<const0>\;
axis_overflow <= \<const0>\;
axis_prog_empty <= \<const1>\;
axis_prog_full <= \<const0>\;
axis_rd_data_count(10) <= \<const0>\;
axis_rd_data_count(9) <= \<const0>\;
axis_rd_data_count(8) <= \<const0>\;
axis_rd_data_count(7) <= \<const0>\;
axis_rd_data_count(6) <= \<const0>\;
axis_rd_data_count(5) <= \<const0>\;
axis_rd_data_count(4) <= \<const0>\;
axis_rd_data_count(3) <= \<const0>\;
axis_rd_data_count(2) <= \<const0>\;
axis_rd_data_count(1) <= \<const0>\;
axis_rd_data_count(0) <= \<const0>\;
axis_sbiterr <= \<const0>\;
axis_underflow <= \<const0>\;
axis_wr_data_count(10) <= \<const0>\;
axis_wr_data_count(9) <= \<const0>\;
axis_wr_data_count(8) <= \<const0>\;
axis_wr_data_count(7) <= \<const0>\;
axis_wr_data_count(6) <= \<const0>\;
axis_wr_data_count(5) <= \<const0>\;
axis_wr_data_count(4) <= \<const0>\;
axis_wr_data_count(3) <= \<const0>\;
axis_wr_data_count(2) <= \<const0>\;
axis_wr_data_count(1) <= \<const0>\;
axis_wr_data_count(0) <= \<const0>\;
data_count(3) <= \<const0>\;
data_count(2) <= \<const0>\;
data_count(1) <= \<const0>\;
data_count(0) <= \<const0>\;
dbiterr <= \<const0>\;
m_axi_araddr(31) <= \<const0>\;
m_axi_araddr(30) <= \<const0>\;
m_axi_araddr(29) <= \<const0>\;
m_axi_araddr(28) <= \<const0>\;
m_axi_araddr(27) <= \<const0>\;
m_axi_araddr(26) <= \<const0>\;
m_axi_araddr(25) <= \<const0>\;
m_axi_araddr(24) <= \<const0>\;
m_axi_araddr(23) <= \<const0>\;
m_axi_araddr(22) <= \<const0>\;
m_axi_araddr(21) <= \<const0>\;
m_axi_araddr(20) <= \<const0>\;
m_axi_araddr(19) <= \<const0>\;
m_axi_araddr(18) <= \<const0>\;
m_axi_araddr(17) <= \<const0>\;
m_axi_araddr(16) <= \<const0>\;
m_axi_araddr(15) <= \<const0>\;
m_axi_araddr(14) <= \<const0>\;
m_axi_araddr(13) <= \<const0>\;
m_axi_araddr(12) <= \<const0>\;
m_axi_araddr(11) <= \<const0>\;
m_axi_araddr(10) <= \<const0>\;
m_axi_araddr(9) <= \<const0>\;
m_axi_araddr(8) <= \<const0>\;
m_axi_araddr(7) <= \<const0>\;
m_axi_araddr(6) <= \<const0>\;
m_axi_araddr(5) <= \<const0>\;
m_axi_araddr(4) <= \<const0>\;
m_axi_araddr(3) <= \<const0>\;
m_axi_araddr(2) <= \<const0>\;
m_axi_araddr(1) <= \<const0>\;
m_axi_araddr(0) <= \<const0>\;
m_axi_arburst(1) <= \<const0>\;
m_axi_arburst(0) <= \<const0>\;
m_axi_arcache(3) <= \<const0>\;
m_axi_arcache(2) <= \<const0>\;
m_axi_arcache(1) <= \<const0>\;
m_axi_arcache(0) <= \<const0>\;
m_axi_arid(0) <= \<const0>\;
m_axi_arlen(7) <= \<const0>\;
m_axi_arlen(6) <= \<const0>\;
m_axi_arlen(5) <= \<const0>\;
m_axi_arlen(4) <= \<const0>\;
m_axi_arlen(3) <= \<const0>\;
m_axi_arlen(2) <= \<const0>\;
m_axi_arlen(1) <= \<const0>\;
m_axi_arlen(0) <= \<const0>\;
m_axi_arlock(0) <= \<const0>\;
m_axi_arprot(2) <= \<const0>\;
m_axi_arprot(1) <= \<const0>\;
m_axi_arprot(0) <= \<const0>\;
m_axi_arqos(3) <= \<const0>\;
m_axi_arqos(2) <= \<const0>\;
m_axi_arqos(1) <= \<const0>\;
m_axi_arqos(0) <= \<const0>\;
m_axi_arregion(3) <= \<const0>\;
m_axi_arregion(2) <= \<const0>\;
m_axi_arregion(1) <= \<const0>\;
m_axi_arregion(0) <= \<const0>\;
m_axi_arsize(2) <= \<const0>\;
m_axi_arsize(1) <= \<const0>\;
m_axi_arsize(0) <= \<const0>\;
m_axi_aruser(0) <= \<const0>\;
m_axi_arvalid <= \<const0>\;
m_axi_awaddr(31) <= \<const0>\;
m_axi_awaddr(30) <= \<const0>\;
m_axi_awaddr(29) <= \<const0>\;
m_axi_awaddr(28) <= \<const0>\;
m_axi_awaddr(27) <= \<const0>\;
m_axi_awaddr(26) <= \<const0>\;
m_axi_awaddr(25) <= \<const0>\;
m_axi_awaddr(24) <= \<const0>\;
m_axi_awaddr(23) <= \<const0>\;
m_axi_awaddr(22) <= \<const0>\;
m_axi_awaddr(21) <= \<const0>\;
m_axi_awaddr(20) <= \<const0>\;
m_axi_awaddr(19) <= \<const0>\;
m_axi_awaddr(18) <= \<const0>\;
m_axi_awaddr(17) <= \<const0>\;
m_axi_awaddr(16) <= \<const0>\;
m_axi_awaddr(15) <= \<const0>\;
m_axi_awaddr(14) <= \<const0>\;
m_axi_awaddr(13) <= \<const0>\;
m_axi_awaddr(12) <= \<const0>\;
m_axi_awaddr(11) <= \<const0>\;
m_axi_awaddr(10) <= \<const0>\;
m_axi_awaddr(9) <= \<const0>\;
m_axi_awaddr(8) <= \<const0>\;
m_axi_awaddr(7) <= \<const0>\;
m_axi_awaddr(6) <= \<const0>\;
m_axi_awaddr(5) <= \<const0>\;
m_axi_awaddr(4) <= \<const0>\;
m_axi_awaddr(3) <= \<const0>\;
m_axi_awaddr(2) <= \<const0>\;
m_axi_awaddr(1) <= \<const0>\;
m_axi_awaddr(0) <= \<const0>\;
m_axi_awburst(1) <= \<const0>\;
m_axi_awburst(0) <= \<const0>\;
m_axi_awcache(3) <= \<const0>\;
m_axi_awcache(2) <= \<const0>\;
m_axi_awcache(1) <= \<const0>\;
m_axi_awcache(0) <= \<const0>\;
m_axi_awid(0) <= \<const0>\;
m_axi_awlen(7) <= \<const0>\;
m_axi_awlen(6) <= \<const0>\;
m_axi_awlen(5) <= \<const0>\;
m_axi_awlen(4) <= \<const0>\;
m_axi_awlen(3) <= \<const0>\;
m_axi_awlen(2) <= \<const0>\;
m_axi_awlen(1) <= \<const0>\;
m_axi_awlen(0) <= \<const0>\;
m_axi_awlock(0) <= \<const0>\;
m_axi_awprot(2) <= \<const0>\;
m_axi_awprot(1) <= \<const0>\;
m_axi_awprot(0) <= \<const0>\;
m_axi_awqos(3) <= \<const0>\;
m_axi_awqos(2) <= \<const0>\;
m_axi_awqos(1) <= \<const0>\;
m_axi_awqos(0) <= \<const0>\;
m_axi_awregion(3) <= \<const0>\;
m_axi_awregion(2) <= \<const0>\;
m_axi_awregion(1) <= \<const0>\;
m_axi_awregion(0) <= \<const0>\;
m_axi_awsize(2) <= \<const0>\;
m_axi_awsize(1) <= \<const0>\;
m_axi_awsize(0) <= \<const0>\;
m_axi_awuser(0) <= \<const0>\;
m_axi_awvalid <= \<const0>\;
m_axi_bready <= \<const0>\;
m_axi_rready <= \<const0>\;
m_axi_wdata(63) <= \<const0>\;
m_axi_wdata(62) <= \<const0>\;
m_axi_wdata(61) <= \<const0>\;
m_axi_wdata(60) <= \<const0>\;
m_axi_wdata(59) <= \<const0>\;
m_axi_wdata(58) <= \<const0>\;
m_axi_wdata(57) <= \<const0>\;
m_axi_wdata(56) <= \<const0>\;
m_axi_wdata(55) <= \<const0>\;
m_axi_wdata(54) <= \<const0>\;
m_axi_wdata(53) <= \<const0>\;
m_axi_wdata(52) <= \<const0>\;
m_axi_wdata(51) <= \<const0>\;
m_axi_wdata(50) <= \<const0>\;
m_axi_wdata(49) <= \<const0>\;
m_axi_wdata(48) <= \<const0>\;
m_axi_wdata(47) <= \<const0>\;
m_axi_wdata(46) <= \<const0>\;
m_axi_wdata(45) <= \<const0>\;
m_axi_wdata(44) <= \<const0>\;
m_axi_wdata(43) <= \<const0>\;
m_axi_wdata(42) <= \<const0>\;
m_axi_wdata(41) <= \<const0>\;
m_axi_wdata(40) <= \<const0>\;
m_axi_wdata(39) <= \<const0>\;
m_axi_wdata(38) <= \<const0>\;
m_axi_wdata(37) <= \<const0>\;
m_axi_wdata(36) <= \<const0>\;
m_axi_wdata(35) <= \<const0>\;
m_axi_wdata(34) <= \<const0>\;
m_axi_wdata(33) <= \<const0>\;
m_axi_wdata(32) <= \<const0>\;
m_axi_wdata(31) <= \<const0>\;
m_axi_wdata(30) <= \<const0>\;
m_axi_wdata(29) <= \<const0>\;
m_axi_wdata(28) <= \<const0>\;
m_axi_wdata(27) <= \<const0>\;
m_axi_wdata(26) <= \<const0>\;
m_axi_wdata(25) <= \<const0>\;
m_axi_wdata(24) <= \<const0>\;
m_axi_wdata(23) <= \<const0>\;
m_axi_wdata(22) <= \<const0>\;
m_axi_wdata(21) <= \<const0>\;
m_axi_wdata(20) <= \<const0>\;
m_axi_wdata(19) <= \<const0>\;
m_axi_wdata(18) <= \<const0>\;
m_axi_wdata(17) <= \<const0>\;
m_axi_wdata(16) <= \<const0>\;
m_axi_wdata(15) <= \<const0>\;
m_axi_wdata(14) <= \<const0>\;
m_axi_wdata(13) <= \<const0>\;
m_axi_wdata(12) <= \<const0>\;
m_axi_wdata(11) <= \<const0>\;
m_axi_wdata(10) <= \<const0>\;
m_axi_wdata(9) <= \<const0>\;
m_axi_wdata(8) <= \<const0>\;
m_axi_wdata(7) <= \<const0>\;
m_axi_wdata(6) <= \<const0>\;
m_axi_wdata(5) <= \<const0>\;
m_axi_wdata(4) <= \<const0>\;
m_axi_wdata(3) <= \<const0>\;
m_axi_wdata(2) <= \<const0>\;
m_axi_wdata(1) <= \<const0>\;
m_axi_wdata(0) <= \<const0>\;
m_axi_wid(0) <= \<const0>\;
m_axi_wlast <= \<const0>\;
m_axi_wstrb(7) <= \<const0>\;
m_axi_wstrb(6) <= \<const0>\;
m_axi_wstrb(5) <= \<const0>\;
m_axi_wstrb(4) <= \<const0>\;
m_axi_wstrb(3) <= \<const0>\;
m_axi_wstrb(2) <= \<const0>\;
m_axi_wstrb(1) <= \<const0>\;
m_axi_wstrb(0) <= \<const0>\;
m_axi_wuser(0) <= \<const0>\;
m_axi_wvalid <= \<const0>\;
m_axis_tdata(7) <= \<const0>\;
m_axis_tdata(6) <= \<const0>\;
m_axis_tdata(5) <= \<const0>\;
m_axis_tdata(4) <= \<const0>\;
m_axis_tdata(3) <= \<const0>\;
m_axis_tdata(2) <= \<const0>\;
m_axis_tdata(1) <= \<const0>\;
m_axis_tdata(0) <= \<const0>\;
m_axis_tdest(0) <= \<const0>\;
m_axis_tid(0) <= \<const0>\;
m_axis_tkeep(0) <= \<const0>\;
m_axis_tlast <= \<const0>\;
m_axis_tstrb(0) <= \<const0>\;
m_axis_tuser(3) <= \<const0>\;
m_axis_tuser(2) <= \<const0>\;
m_axis_tuser(1) <= \<const0>\;
m_axis_tuser(0) <= \<const0>\;
m_axis_tvalid <= \<const0>\;
overflow <= \<const0>\;
prog_empty <= \<const0>\;
rd_data_count(3) <= \<const0>\;
rd_data_count(2) <= \<const0>\;
rd_data_count(1) <= \<const0>\;
rd_data_count(0) <= \<const0>\;
rd_rst_busy <= \<const0>\;
s_axi_arready <= \<const0>\;
s_axi_awready <= \<const0>\;
s_axi_bid(0) <= \<const0>\;
s_axi_bresp(1) <= \<const0>\;
s_axi_bresp(0) <= \<const0>\;
s_axi_buser(0) <= \<const0>\;
s_axi_bvalid <= \<const0>\;
s_axi_rdata(63) <= \<const0>\;
s_axi_rdata(62) <= \<const0>\;
s_axi_rdata(61) <= \<const0>\;
s_axi_rdata(60) <= \<const0>\;
s_axi_rdata(59) <= \<const0>\;
s_axi_rdata(58) <= \<const0>\;
s_axi_rdata(57) <= \<const0>\;
s_axi_rdata(56) <= \<const0>\;
s_axi_rdata(55) <= \<const0>\;
s_axi_rdata(54) <= \<const0>\;
s_axi_rdata(53) <= \<const0>\;
s_axi_rdata(52) <= \<const0>\;
s_axi_rdata(51) <= \<const0>\;
s_axi_rdata(50) <= \<const0>\;
s_axi_rdata(49) <= \<const0>\;
s_axi_rdata(48) <= \<const0>\;
s_axi_rdata(47) <= \<const0>\;
s_axi_rdata(46) <= \<const0>\;
s_axi_rdata(45) <= \<const0>\;
s_axi_rdata(44) <= \<const0>\;
s_axi_rdata(43) <= \<const0>\;
s_axi_rdata(42) <= \<const0>\;
s_axi_rdata(41) <= \<const0>\;
s_axi_rdata(40) <= \<const0>\;
s_axi_rdata(39) <= \<const0>\;
s_axi_rdata(38) <= \<const0>\;
s_axi_rdata(37) <= \<const0>\;
s_axi_rdata(36) <= \<const0>\;
s_axi_rdata(35) <= \<const0>\;
s_axi_rdata(34) <= \<const0>\;
s_axi_rdata(33) <= \<const0>\;
s_axi_rdata(32) <= \<const0>\;
s_axi_rdata(31) <= \<const0>\;
s_axi_rdata(30) <= \<const0>\;
s_axi_rdata(29) <= \<const0>\;
s_axi_rdata(28) <= \<const0>\;
s_axi_rdata(27) <= \<const0>\;
s_axi_rdata(26) <= \<const0>\;
s_axi_rdata(25) <= \<const0>\;
s_axi_rdata(24) <= \<const0>\;
s_axi_rdata(23) <= \<const0>\;
s_axi_rdata(22) <= \<const0>\;
s_axi_rdata(21) <= \<const0>\;
s_axi_rdata(20) <= \<const0>\;
s_axi_rdata(19) <= \<const0>\;
s_axi_rdata(18) <= \<const0>\;
s_axi_rdata(17) <= \<const0>\;
s_axi_rdata(16) <= \<const0>\;
s_axi_rdata(15) <= \<const0>\;
s_axi_rdata(14) <= \<const0>\;
s_axi_rdata(13) <= \<const0>\;
s_axi_rdata(12) <= \<const0>\;
s_axi_rdata(11) <= \<const0>\;
s_axi_rdata(10) <= \<const0>\;
s_axi_rdata(9) <= \<const0>\;
s_axi_rdata(8) <= \<const0>\;
s_axi_rdata(7) <= \<const0>\;
s_axi_rdata(6) <= \<const0>\;
s_axi_rdata(5) <= \<const0>\;
s_axi_rdata(4) <= \<const0>\;
s_axi_rdata(3) <= \<const0>\;
s_axi_rdata(2) <= \<const0>\;
s_axi_rdata(1) <= \<const0>\;
s_axi_rdata(0) <= \<const0>\;
s_axi_rid(0) <= \<const0>\;
s_axi_rlast <= \<const0>\;
s_axi_rresp(1) <= \<const0>\;
s_axi_rresp(0) <= \<const0>\;
s_axi_ruser(0) <= \<const0>\;
s_axi_rvalid <= \<const0>\;
s_axi_wready <= \<const0>\;
s_axis_tready <= \<const0>\;
sbiterr <= \<const0>\;
underflow <= \<const0>\;
valid <= \<const0>\;
wr_ack <= \<const0>\;
wr_data_count(3) <= \<const0>\;
wr_data_count(2) <= \<const0>\;
wr_data_count(1) <= \<const0>\;
wr_data_count(0) <= \<const0>\;
wr_rst_busy <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
VCC: unisim.vcomponents.VCC
port map (
P => \<const1>\
);
inst_fifo_gen: entity work.fifo_async_103x16_fifo_generator_v12_0_synth
port map (
din(102 downto 0) => din(102 downto 0),
dout(102 downto 0) => dout(102 downto 0),
empty => empty,
full => full,
prog_full => prog_full,
rd_clk => rd_clk,
rd_en => rd_en,
rst => rst,
wr_clk => wr_clk,
wr_en => wr_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_async_103x16 is
port (
rst : in STD_LOGIC;
wr_clk : in STD_LOGIC;
rd_clk : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 102 downto 0 );
wr_en : in STD_LOGIC;
rd_en : in STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 102 downto 0 );
full : out STD_LOGIC;
empty : out STD_LOGIC;
prog_full : out STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of fifo_async_103x16 : entity is true;
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of fifo_async_103x16 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of fifo_async_103x16 : entity is "fifo_generator_v12_0,Vivado 2014.3.1";
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of fifo_async_103x16 : entity is "fifo_async_103x16,fifo_generator_v12_0,{}";
attribute core_generation_info : string;
attribute core_generation_info of fifo_async_103x16 : entity is "fifo_async_103x16,fifo_generator_v12_0,{x_ipProduct=Vivado 2014.3.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=fifo_generator,x_ipVersion=12.0,x_ipCoreRevision=2,x_ipLanguage=VERILOG,C_COMMON_CLOCK=0,C_COUNT_TYPE=0,C_DATA_COUNT_WIDTH=4,C_DEFAULT_VALUE=BlankString,C_DIN_WIDTH=103,C_DOUT_RST_VAL=0,C_DOUT_WIDTH=103,C_ENABLE_RLOCS=0,C_FAMILY=zynq,C_FULL_FLAGS_RST_VAL=1,C_HAS_ALMOST_EMPTY=0,C_HAS_ALMOST_FULL=0,C_HAS_BACKUP=0,C_HAS_DATA_COUNT=0,C_HAS_INT_CLK=0,C_HAS_MEMINIT_FILE=0,C_HAS_OVERFLOW=0,C_HAS_RD_DATA_COUNT=0,C_HAS_RD_RST=0,C_HAS_RST=1,C_HAS_SRST=0,C_HAS_UNDERFLOW=0,C_HAS_VALID=0,C_HAS_WR_ACK=0,C_HAS_WR_DATA_COUNT=0,C_HAS_WR_RST=0,C_IMPLEMENTATION_TYPE=2,C_INIT_WR_PNTR_VAL=0,C_MEMORY_TYPE=2,C_MIF_FILE_NAME=BlankString,C_OPTIMIZATION_MODE=0,C_OVERFLOW_LOW=0,C_PRELOAD_LATENCY=0,C_PRELOAD_REGS=1,C_PRIM_FIFO_TYPE=512x72,C_PROG_EMPTY_THRESH_ASSERT_VAL=4,C_PROG_EMPTY_THRESH_NEGATE_VAL=5,C_PROG_EMPTY_TYPE=0,C_PROG_FULL_THRESH_ASSERT_VAL=12,C_PROG_FULL_THRESH_NEGATE_VAL=11,C_PROG_FULL_TYPE=1,C_RD_DATA_COUNT_WIDTH=4,C_RD_DEPTH=16,C_RD_FREQ=1,C_RD_PNTR_WIDTH=4,C_UNDERFLOW_LOW=0,C_USE_DOUT_RST=1,C_USE_ECC=0,C_USE_EMBEDDED_REG=0,C_USE_PIPELINE_REG=0,C_POWER_SAVING_MODE=0,C_USE_FIFO16_FLAGS=0,C_USE_FWFT_DATA_COUNT=0,C_VALID_LOW=0,C_WR_ACK_LOW=0,C_WR_DATA_COUNT_WIDTH=4,C_WR_DEPTH=16,C_WR_FREQ=1,C_WR_PNTR_WIDTH=4,C_WR_RESPONSE_LATENCY=1,C_MSGON_VAL=1,C_ENABLE_RST_SYNC=1,C_ERROR_INJECTION_TYPE=0,C_SYNCHRONIZER_STAGE=2,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_HAS_AXI_WR_CHANNEL=1,C_HAS_AXI_RD_CHANNEL=1,C_HAS_SLAVE_CE=0,C_HAS_MASTER_CE=0,C_ADD_NGC_CONSTRAINT=0,C_USE_COMMON_OVERFLOW=0,C_USE_COMMON_UNDERFLOW=0,C_USE_DEFAULT_SETTINGS=0,C_AXI_ID_WIDTH=1,C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=64,C_AXI_LEN_WIDTH=8,C_AXI_LOCK_WIDTH=1,C_HAS_AXI_ID=0,C_HAS_AXI_AWUSER=0,C_HAS_AXI_WUSER=0,C_HAS_AXI_BUSER=0,C_HAS_AXI_ARUSER=0,C_HAS_AXI_RUSER=0,C_AXI_ARUSER_WIDTH=1,C_AXI_AWUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_AXI_RUSER_WIDTH=1,C_HAS_AXIS_TDATA=1,C_HAS_AXIS_TID=0,C_HAS_AXIS_TDEST=0,C_HAS_AXIS_TUSER=1,C_HAS_AXIS_TREADY=1,C_HAS_AXIS_TLAST=0,C_HAS_AXIS_TSTRB=0,C_HAS_AXIS_TKEEP=0,C_AXIS_TDATA_WIDTH=8,C_AXIS_TID_WIDTH=1,C_AXIS_TDEST_WIDTH=1,C_AXIS_TUSER_WIDTH=4,C_AXIS_TSTRB_WIDTH=1,C_AXIS_TKEEP_WIDTH=1,C_WACH_TYPE=0,C_WDCH_TYPE=0,C_WRCH_TYPE=0,C_RACH_TYPE=0,C_RDCH_TYPE=0,C_AXIS_TYPE=0,C_IMPLEMENTATION_TYPE_WACH=1,C_IMPLEMENTATION_TYPE_WDCH=1,C_IMPLEMENTATION_TYPE_WRCH=1,C_IMPLEMENTATION_TYPE_RACH=1,C_IMPLEMENTATION_TYPE_RDCH=1,C_IMPLEMENTATION_TYPE_AXIS=1,C_APPLICATION_TYPE_WACH=0,C_APPLICATION_TYPE_WDCH=0,C_APPLICATION_TYPE_WRCH=0,C_APPLICATION_TYPE_RACH=0,C_APPLICATION_TYPE_RDCH=0,C_APPLICATION_TYPE_AXIS=0,C_PRIM_FIFO_TYPE_WACH=512x36,C_PRIM_FIFO_TYPE_WDCH=1kx36,C_PRIM_FIFO_TYPE_WRCH=512x36,C_PRIM_FIFO_TYPE_RACH=512x36,C_PRIM_FIFO_TYPE_RDCH=1kx36,C_PRIM_FIFO_TYPE_AXIS=1kx18,C_USE_ECC_WACH=0,C_USE_ECC_WDCH=0,C_USE_ECC_WRCH=0,C_USE_ECC_RACH=0,C_USE_ECC_RDCH=0,C_USE_ECC_AXIS=0,C_ERROR_INJECTION_TYPE_WACH=0,C_ERROR_INJECTION_TYPE_WDCH=0,C_ERROR_INJECTION_TYPE_WRCH=0,C_ERROR_INJECTION_TYPE_RACH=0,C_ERROR_INJECTION_TYPE_RDCH=0,C_ERROR_INJECTION_TYPE_AXIS=0,C_DIN_WIDTH_WACH=32,C_DIN_WIDTH_WDCH=64,C_DIN_WIDTH_WRCH=2,C_DIN_WIDTH_RACH=32,C_DIN_WIDTH_RDCH=64,C_DIN_WIDTH_AXIS=1,C_WR_DEPTH_WACH=16,C_WR_DEPTH_WDCH=1024,C_WR_DEPTH_WRCH=16,C_WR_DEPTH_RACH=16,C_WR_DEPTH_RDCH=1024,C_WR_DEPTH_AXIS=1024,C_WR_PNTR_WIDTH_WACH=4,C_WR_PNTR_WIDTH_WDCH=10,C_WR_PNTR_WIDTH_WRCH=4,C_WR_PNTR_WIDTH_RACH=4,C_WR_PNTR_WIDTH_RDCH=10,C_WR_PNTR_WIDTH_AXIS=10,C_HAS_DATA_COUNTS_WACH=0,C_HAS_DATA_COUNTS_WDCH=0,C_HAS_DATA_COUNTS_WRCH=0,C_HAS_DATA_COUNTS_RACH=0,C_HAS_DATA_COUNTS_RDCH=0,C_HAS_DATA_COUNTS_AXIS=0,C_HAS_PROG_FLAGS_WACH=0,C_HAS_PROG_FLAGS_WDCH=0,C_HAS_PROG_FLAGS_WRCH=0,C_HAS_PROG_FLAGS_RACH=0,C_HAS_PROG_FLAGS_RDCH=0,C_HAS_PROG_FLAGS_AXIS=0,C_PROG_FULL_TYPE_WACH=0,C_PROG_FULL_TYPE_WDCH=0,C_PROG_FULL_TYPE_WRCH=0,C_PROG_FULL_TYPE_RACH=0,C_PROG_FULL_TYPE_RDCH=0,C_PROG_FULL_TYPE_AXIS=0,C_PROG_FULL_THRESH_ASSERT_VAL_WACH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WRCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RACH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_AXIS=1023,C_PROG_EMPTY_TYPE_WACH=0,C_PROG_EMPTY_TYPE_WDCH=0,C_PROG_EMPTY_TYPE_WRCH=0,C_PROG_EMPTY_TYPE_RACH=0,C_PROG_EMPTY_TYPE_RDCH=0,C_PROG_EMPTY_TYPE_AXIS=0,C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS=1022,C_REG_SLICE_MODE_WACH=0,C_REG_SLICE_MODE_WDCH=0,C_REG_SLICE_MODE_WRCH=0,C_REG_SLICE_MODE_RACH=0,C_REG_SLICE_MODE_RDCH=0,C_REG_SLICE_MODE_AXIS=0}";
end fifo_async_103x16;
architecture STRUCTURE of fifo_async_103x16 is
signal NLW_U0_almost_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_almost_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_arvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_awvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_bready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_rready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_wlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_wvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axis_tlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axis_tvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_rd_rst_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_arready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_awready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_bvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_wready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axis_tready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_valid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_wr_ack_UNCONNECTED : STD_LOGIC;
signal NLW_U0_wr_rst_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_ar_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_ar_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_aw_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_aw_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_aw_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_b_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_b_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_b_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_r_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_r_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_r_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_w_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_w_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_w_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axis_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axis_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axis_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_araddr_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_m_axi_arburst_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_m_axi_arcache_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_arid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_arlen_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_m_axi_arlock_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_arprot_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_U0_m_axi_arqos_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_arregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_arsize_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_U0_m_axi_aruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_awaddr_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_m_axi_awburst_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_m_axi_awcache_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_awid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_awlen_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_m_axi_awlock_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_awprot_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_U0_m_axi_awqos_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_awregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_awsize_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_U0_m_axi_awuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_wdata_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_U0_m_axi_wid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_wstrb_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_m_axi_wuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tdata_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_m_axis_tdest_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tkeep_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tstrb_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tuser_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_s_axi_buser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_U0_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_s_axi_ruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute C_ADD_NGC_CONSTRAINT : integer;
attribute C_ADD_NGC_CONSTRAINT of U0 : label is 0;
attribute C_APPLICATION_TYPE_AXIS : integer;
attribute C_APPLICATION_TYPE_AXIS of U0 : label is 0;
attribute C_APPLICATION_TYPE_RACH : integer;
attribute C_APPLICATION_TYPE_RACH of U0 : label is 0;
attribute C_APPLICATION_TYPE_RDCH : integer;
attribute C_APPLICATION_TYPE_RDCH of U0 : label is 0;
attribute C_APPLICATION_TYPE_WACH : integer;
attribute C_APPLICATION_TYPE_WACH of U0 : label is 0;
attribute C_APPLICATION_TYPE_WDCH : integer;
attribute C_APPLICATION_TYPE_WDCH of U0 : label is 0;
attribute C_APPLICATION_TYPE_WRCH : integer;
attribute C_APPLICATION_TYPE_WRCH of U0 : label is 0;
attribute C_AXIS_TDATA_WIDTH : integer;
attribute C_AXIS_TDATA_WIDTH of U0 : label is 8;
attribute C_AXIS_TDEST_WIDTH : integer;
attribute C_AXIS_TDEST_WIDTH of U0 : label is 1;
attribute C_AXIS_TID_WIDTH : integer;
attribute C_AXIS_TID_WIDTH of U0 : label is 1;
attribute C_AXIS_TKEEP_WIDTH : integer;
attribute C_AXIS_TKEEP_WIDTH of U0 : label is 1;
attribute C_AXIS_TSTRB_WIDTH : integer;
attribute C_AXIS_TSTRB_WIDTH of U0 : label is 1;
attribute C_AXIS_TUSER_WIDTH : integer;
attribute C_AXIS_TUSER_WIDTH of U0 : label is 4;
attribute C_AXIS_TYPE : integer;
attribute C_AXIS_TYPE of U0 : label is 0;
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of U0 : label is 32;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of U0 : label is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of U0 : label is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of U0 : label is 1;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of U0 : label is 64;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of U0 : label is 1;
attribute C_AXI_LEN_WIDTH : integer;
attribute C_AXI_LEN_WIDTH of U0 : label is 8;
attribute C_AXI_LOCK_WIDTH : integer;
attribute C_AXI_LOCK_WIDTH of U0 : label is 1;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of U0 : label is 1;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of U0 : label is 1;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of U0 : label is 1;
attribute C_COMMON_CLOCK : integer;
attribute C_COMMON_CLOCK of U0 : label is 0;
attribute C_COUNT_TYPE : integer;
attribute C_COUNT_TYPE of U0 : label is 0;
attribute C_DATA_COUNT_WIDTH : integer;
attribute C_DATA_COUNT_WIDTH of U0 : label is 4;
attribute C_DEFAULT_VALUE : string;
attribute C_DEFAULT_VALUE of U0 : label is "BlankString";
attribute C_DIN_WIDTH : integer;
attribute C_DIN_WIDTH of U0 : label is 103;
attribute C_DIN_WIDTH_AXIS : integer;
attribute C_DIN_WIDTH_AXIS of U0 : label is 1;
attribute C_DIN_WIDTH_RACH : integer;
attribute C_DIN_WIDTH_RACH of U0 : label is 32;
attribute C_DIN_WIDTH_RDCH : integer;
attribute C_DIN_WIDTH_RDCH of U0 : label is 64;
attribute C_DIN_WIDTH_WACH : integer;
attribute C_DIN_WIDTH_WACH of U0 : label is 32;
attribute C_DIN_WIDTH_WDCH : integer;
attribute C_DIN_WIDTH_WDCH of U0 : label is 64;
attribute C_DIN_WIDTH_WRCH : integer;
attribute C_DIN_WIDTH_WRCH of U0 : label is 2;
attribute C_DOUT_RST_VAL : string;
attribute C_DOUT_RST_VAL of U0 : label is "0";
attribute C_DOUT_WIDTH : integer;
attribute C_DOUT_WIDTH of U0 : label is 103;
attribute C_ENABLE_RLOCS : integer;
attribute C_ENABLE_RLOCS of U0 : label is 0;
attribute C_ENABLE_RST_SYNC : integer;
attribute C_ENABLE_RST_SYNC of U0 : label is 1;
attribute C_ERROR_INJECTION_TYPE : integer;
attribute C_ERROR_INJECTION_TYPE of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_AXIS : integer;
attribute C_ERROR_INJECTION_TYPE_AXIS of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_RACH : integer;
attribute C_ERROR_INJECTION_TYPE_RACH of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_RDCH : integer;
attribute C_ERROR_INJECTION_TYPE_RDCH of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_WACH : integer;
attribute C_ERROR_INJECTION_TYPE_WACH of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_WDCH : integer;
attribute C_ERROR_INJECTION_TYPE_WDCH of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_WRCH : integer;
attribute C_ERROR_INJECTION_TYPE_WRCH of U0 : label is 0;
attribute C_FAMILY : string;
attribute C_FAMILY of U0 : label is "zynq";
attribute C_FULL_FLAGS_RST_VAL : integer;
attribute C_FULL_FLAGS_RST_VAL of U0 : label is 1;
attribute C_HAS_ALMOST_EMPTY : integer;
attribute C_HAS_ALMOST_EMPTY of U0 : label is 0;
attribute C_HAS_ALMOST_FULL : integer;
attribute C_HAS_ALMOST_FULL of U0 : label is 0;
attribute C_HAS_AXIS_TDATA : integer;
attribute C_HAS_AXIS_TDATA of U0 : label is 1;
attribute C_HAS_AXIS_TDEST : integer;
attribute C_HAS_AXIS_TDEST of U0 : label is 0;
attribute C_HAS_AXIS_TID : integer;
attribute C_HAS_AXIS_TID of U0 : label is 0;
attribute C_HAS_AXIS_TKEEP : integer;
attribute C_HAS_AXIS_TKEEP of U0 : label is 0;
attribute C_HAS_AXIS_TLAST : integer;
attribute C_HAS_AXIS_TLAST of U0 : label is 0;
attribute C_HAS_AXIS_TREADY : integer;
attribute C_HAS_AXIS_TREADY of U0 : label is 1;
attribute C_HAS_AXIS_TSTRB : integer;
attribute C_HAS_AXIS_TSTRB of U0 : label is 0;
attribute C_HAS_AXIS_TUSER : integer;
attribute C_HAS_AXIS_TUSER of U0 : label is 1;
attribute C_HAS_AXI_ARUSER : integer;
attribute C_HAS_AXI_ARUSER of U0 : label is 0;
attribute C_HAS_AXI_AWUSER : integer;
attribute C_HAS_AXI_AWUSER of U0 : label is 0;
attribute C_HAS_AXI_BUSER : integer;
attribute C_HAS_AXI_BUSER of U0 : label is 0;
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of U0 : label is 0;
attribute C_HAS_AXI_RD_CHANNEL : integer;
attribute C_HAS_AXI_RD_CHANNEL of U0 : label is 1;
attribute C_HAS_AXI_RUSER : integer;
attribute C_HAS_AXI_RUSER of U0 : label is 0;
attribute C_HAS_AXI_WR_CHANNEL : integer;
attribute C_HAS_AXI_WR_CHANNEL of U0 : label is 1;
attribute C_HAS_AXI_WUSER : integer;
attribute C_HAS_AXI_WUSER of U0 : label is 0;
attribute C_HAS_BACKUP : integer;
attribute C_HAS_BACKUP of U0 : label is 0;
attribute C_HAS_DATA_COUNT : integer;
attribute C_HAS_DATA_COUNT of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_AXIS : integer;
attribute C_HAS_DATA_COUNTS_AXIS of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_RACH : integer;
attribute C_HAS_DATA_COUNTS_RACH of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_RDCH : integer;
attribute C_HAS_DATA_COUNTS_RDCH of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_WACH : integer;
attribute C_HAS_DATA_COUNTS_WACH of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_WDCH : integer;
attribute C_HAS_DATA_COUNTS_WDCH of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_WRCH : integer;
attribute C_HAS_DATA_COUNTS_WRCH of U0 : label is 0;
attribute C_HAS_INT_CLK : integer;
attribute C_HAS_INT_CLK of U0 : label is 0;
attribute C_HAS_MASTER_CE : integer;
attribute C_HAS_MASTER_CE of U0 : label is 0;
attribute C_HAS_MEMINIT_FILE : integer;
attribute C_HAS_MEMINIT_FILE of U0 : label is 0;
attribute C_HAS_OVERFLOW : integer;
attribute C_HAS_OVERFLOW of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_AXIS : integer;
attribute C_HAS_PROG_FLAGS_AXIS of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_RACH : integer;
attribute C_HAS_PROG_FLAGS_RACH of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_RDCH : integer;
attribute C_HAS_PROG_FLAGS_RDCH of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_WACH : integer;
attribute C_HAS_PROG_FLAGS_WACH of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_WDCH : integer;
attribute C_HAS_PROG_FLAGS_WDCH of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_WRCH : integer;
attribute C_HAS_PROG_FLAGS_WRCH of U0 : label is 0;
attribute C_HAS_RD_DATA_COUNT : integer;
attribute C_HAS_RD_DATA_COUNT of U0 : label is 0;
attribute C_HAS_RD_RST : integer;
attribute C_HAS_RD_RST of U0 : label is 0;
attribute C_HAS_RST : integer;
attribute C_HAS_RST of U0 : label is 1;
attribute C_HAS_SLAVE_CE : integer;
attribute C_HAS_SLAVE_CE of U0 : label is 0;
attribute C_HAS_SRST : integer;
attribute C_HAS_SRST of U0 : label is 0;
attribute C_HAS_UNDERFLOW : integer;
attribute C_HAS_UNDERFLOW of U0 : label is 0;
attribute C_HAS_VALID : integer;
attribute C_HAS_VALID of U0 : label is 0;
attribute C_HAS_WR_ACK : integer;
attribute C_HAS_WR_ACK of U0 : label is 0;
attribute C_HAS_WR_DATA_COUNT : integer;
attribute C_HAS_WR_DATA_COUNT of U0 : label is 0;
attribute C_HAS_WR_RST : integer;
attribute C_HAS_WR_RST of U0 : label is 0;
attribute C_IMPLEMENTATION_TYPE : integer;
attribute C_IMPLEMENTATION_TYPE of U0 : label is 2;
attribute C_IMPLEMENTATION_TYPE_AXIS : integer;
attribute C_IMPLEMENTATION_TYPE_AXIS of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_RACH : integer;
attribute C_IMPLEMENTATION_TYPE_RACH of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_RDCH : integer;
attribute C_IMPLEMENTATION_TYPE_RDCH of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_WACH : integer;
attribute C_IMPLEMENTATION_TYPE_WACH of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_WDCH : integer;
attribute C_IMPLEMENTATION_TYPE_WDCH of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_WRCH : integer;
attribute C_IMPLEMENTATION_TYPE_WRCH of U0 : label is 1;
attribute C_INIT_WR_PNTR_VAL : integer;
attribute C_INIT_WR_PNTR_VAL of U0 : label is 0;
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of U0 : label is 0;
attribute C_MEMORY_TYPE : integer;
attribute C_MEMORY_TYPE of U0 : label is 2;
attribute C_MIF_FILE_NAME : string;
attribute C_MIF_FILE_NAME of U0 : label is "BlankString";
attribute C_MSGON_VAL : integer;
attribute C_MSGON_VAL of U0 : label is 1;
attribute C_OPTIMIZATION_MODE : integer;
attribute C_OPTIMIZATION_MODE of U0 : label is 0;
attribute C_OVERFLOW_LOW : integer;
attribute C_OVERFLOW_LOW of U0 : label is 0;
attribute C_POWER_SAVING_MODE : integer;
attribute C_POWER_SAVING_MODE of U0 : label is 0;
attribute C_PRELOAD_LATENCY : integer;
attribute C_PRELOAD_LATENCY of U0 : label is 0;
attribute C_PRELOAD_REGS : integer;
attribute C_PRELOAD_REGS of U0 : label is 1;
attribute C_PRIM_FIFO_TYPE : string;
attribute C_PRIM_FIFO_TYPE of U0 : label is "512x72";
attribute C_PRIM_FIFO_TYPE_AXIS : string;
attribute C_PRIM_FIFO_TYPE_AXIS of U0 : label is "1kx18";
attribute C_PRIM_FIFO_TYPE_RACH : string;
attribute C_PRIM_FIFO_TYPE_RACH of U0 : label is "512x36";
attribute C_PRIM_FIFO_TYPE_RDCH : string;
attribute C_PRIM_FIFO_TYPE_RDCH of U0 : label is "1kx36";
attribute C_PRIM_FIFO_TYPE_WACH : string;
attribute C_PRIM_FIFO_TYPE_WACH of U0 : label is "512x36";
attribute C_PRIM_FIFO_TYPE_WDCH : string;
attribute C_PRIM_FIFO_TYPE_WDCH of U0 : label is "1kx36";
attribute C_PRIM_FIFO_TYPE_WRCH : string;
attribute C_PRIM_FIFO_TYPE_WRCH of U0 : label is "512x36";
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL of U0 : label is 4;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL : integer;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL of U0 : label is 5;
attribute C_PROG_EMPTY_TYPE : integer;
attribute C_PROG_EMPTY_TYPE of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_AXIS : integer;
attribute C_PROG_EMPTY_TYPE_AXIS of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_RACH : integer;
attribute C_PROG_EMPTY_TYPE_RACH of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_RDCH : integer;
attribute C_PROG_EMPTY_TYPE_RDCH of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_WACH : integer;
attribute C_PROG_EMPTY_TYPE_WACH of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_WDCH : integer;
attribute C_PROG_EMPTY_TYPE_WDCH of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_WRCH : integer;
attribute C_PROG_EMPTY_TYPE_WRCH of U0 : label is 0;
attribute C_PROG_FULL_THRESH_ASSERT_VAL : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL of U0 : label is 12;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_NEGATE_VAL : integer;
attribute C_PROG_FULL_THRESH_NEGATE_VAL of U0 : label is 11;
attribute C_PROG_FULL_TYPE : integer;
attribute C_PROG_FULL_TYPE of U0 : label is 1;
attribute C_PROG_FULL_TYPE_AXIS : integer;
attribute C_PROG_FULL_TYPE_AXIS of U0 : label is 0;
attribute C_PROG_FULL_TYPE_RACH : integer;
attribute C_PROG_FULL_TYPE_RACH of U0 : label is 0;
attribute C_PROG_FULL_TYPE_RDCH : integer;
attribute C_PROG_FULL_TYPE_RDCH of U0 : label is 0;
attribute C_PROG_FULL_TYPE_WACH : integer;
attribute C_PROG_FULL_TYPE_WACH of U0 : label is 0;
attribute C_PROG_FULL_TYPE_WDCH : integer;
attribute C_PROG_FULL_TYPE_WDCH of U0 : label is 0;
attribute C_PROG_FULL_TYPE_WRCH : integer;
attribute C_PROG_FULL_TYPE_WRCH of U0 : label is 0;
attribute C_RACH_TYPE : integer;
attribute C_RACH_TYPE of U0 : label is 0;
attribute C_RDCH_TYPE : integer;
attribute C_RDCH_TYPE of U0 : label is 0;
attribute C_RD_DATA_COUNT_WIDTH : integer;
attribute C_RD_DATA_COUNT_WIDTH of U0 : label is 4;
attribute C_RD_DEPTH : integer;
attribute C_RD_DEPTH of U0 : label is 16;
attribute C_RD_FREQ : integer;
attribute C_RD_FREQ of U0 : label is 1;
attribute C_RD_PNTR_WIDTH : integer;
attribute C_RD_PNTR_WIDTH of U0 : label is 4;
attribute C_REG_SLICE_MODE_AXIS : integer;
attribute C_REG_SLICE_MODE_AXIS of U0 : label is 0;
attribute C_REG_SLICE_MODE_RACH : integer;
attribute C_REG_SLICE_MODE_RACH of U0 : label is 0;
attribute C_REG_SLICE_MODE_RDCH : integer;
attribute C_REG_SLICE_MODE_RDCH of U0 : label is 0;
attribute C_REG_SLICE_MODE_WACH : integer;
attribute C_REG_SLICE_MODE_WACH of U0 : label is 0;
attribute C_REG_SLICE_MODE_WDCH : integer;
attribute C_REG_SLICE_MODE_WDCH of U0 : label is 0;
attribute C_REG_SLICE_MODE_WRCH : integer;
attribute C_REG_SLICE_MODE_WRCH of U0 : label is 0;
attribute C_SYNCHRONIZER_STAGE : integer;
attribute C_SYNCHRONIZER_STAGE of U0 : label is 2;
attribute C_UNDERFLOW_LOW : integer;
attribute C_UNDERFLOW_LOW of U0 : label is 0;
attribute C_USE_COMMON_OVERFLOW : integer;
attribute C_USE_COMMON_OVERFLOW of U0 : label is 0;
attribute C_USE_COMMON_UNDERFLOW : integer;
attribute C_USE_COMMON_UNDERFLOW of U0 : label is 0;
attribute C_USE_DEFAULT_SETTINGS : integer;
attribute C_USE_DEFAULT_SETTINGS of U0 : label is 0;
attribute C_USE_DOUT_RST : integer;
attribute C_USE_DOUT_RST of U0 : label is 1;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of U0 : label is 0;
attribute C_USE_ECC_AXIS : integer;
attribute C_USE_ECC_AXIS of U0 : label is 0;
attribute C_USE_ECC_RACH : integer;
attribute C_USE_ECC_RACH of U0 : label is 0;
attribute C_USE_ECC_RDCH : integer;
attribute C_USE_ECC_RDCH of U0 : label is 0;
attribute C_USE_ECC_WACH : integer;
attribute C_USE_ECC_WACH of U0 : label is 0;
attribute C_USE_ECC_WDCH : integer;
attribute C_USE_ECC_WDCH of U0 : label is 0;
attribute C_USE_ECC_WRCH : integer;
attribute C_USE_ECC_WRCH of U0 : label is 0;
attribute C_USE_EMBEDDED_REG : integer;
attribute C_USE_EMBEDDED_REG of U0 : label is 0;
attribute C_USE_FIFO16_FLAGS : integer;
attribute C_USE_FIFO16_FLAGS of U0 : label is 0;
attribute C_USE_FWFT_DATA_COUNT : integer;
attribute C_USE_FWFT_DATA_COUNT of U0 : label is 0;
attribute C_USE_PIPELINE_REG : integer;
attribute C_USE_PIPELINE_REG of U0 : label is 0;
attribute C_VALID_LOW : integer;
attribute C_VALID_LOW of U0 : label is 0;
attribute C_WACH_TYPE : integer;
attribute C_WACH_TYPE of U0 : label is 0;
attribute C_WDCH_TYPE : integer;
attribute C_WDCH_TYPE of U0 : label is 0;
attribute C_WRCH_TYPE : integer;
attribute C_WRCH_TYPE of U0 : label is 0;
attribute C_WR_ACK_LOW : integer;
attribute C_WR_ACK_LOW of U0 : label is 0;
attribute C_WR_DATA_COUNT_WIDTH : integer;
attribute C_WR_DATA_COUNT_WIDTH of U0 : label is 4;
attribute C_WR_DEPTH : integer;
attribute C_WR_DEPTH of U0 : label is 16;
attribute C_WR_DEPTH_AXIS : integer;
attribute C_WR_DEPTH_AXIS of U0 : label is 1024;
attribute C_WR_DEPTH_RACH : integer;
attribute C_WR_DEPTH_RACH of U0 : label is 16;
attribute C_WR_DEPTH_RDCH : integer;
attribute C_WR_DEPTH_RDCH of U0 : label is 1024;
attribute C_WR_DEPTH_WACH : integer;
attribute C_WR_DEPTH_WACH of U0 : label is 16;
attribute C_WR_DEPTH_WDCH : integer;
attribute C_WR_DEPTH_WDCH of U0 : label is 1024;
attribute C_WR_DEPTH_WRCH : integer;
attribute C_WR_DEPTH_WRCH of U0 : label is 16;
attribute C_WR_FREQ : integer;
attribute C_WR_FREQ of U0 : label is 1;
attribute C_WR_PNTR_WIDTH : integer;
attribute C_WR_PNTR_WIDTH of U0 : label is 4;
attribute C_WR_PNTR_WIDTH_AXIS : integer;
attribute C_WR_PNTR_WIDTH_AXIS of U0 : label is 10;
attribute C_WR_PNTR_WIDTH_RACH : integer;
attribute C_WR_PNTR_WIDTH_RACH of U0 : label is 4;
attribute C_WR_PNTR_WIDTH_RDCH : integer;
attribute C_WR_PNTR_WIDTH_RDCH of U0 : label is 10;
attribute C_WR_PNTR_WIDTH_WACH : integer;
attribute C_WR_PNTR_WIDTH_WACH of U0 : label is 4;
attribute C_WR_PNTR_WIDTH_WDCH : integer;
attribute C_WR_PNTR_WIDTH_WDCH of U0 : label is 10;
attribute C_WR_PNTR_WIDTH_WRCH : integer;
attribute C_WR_PNTR_WIDTH_WRCH of U0 : label is 4;
attribute C_WR_RESPONSE_LATENCY : integer;
attribute C_WR_RESPONSE_LATENCY of U0 : label is 1;
begin
U0: entity work.\fifo_async_103x16_fifo_generator_v12_0__parameterized0\
port map (
almost_empty => NLW_U0_almost_empty_UNCONNECTED,
almost_full => NLW_U0_almost_full_UNCONNECTED,
axi_ar_data_count(4 downto 0) => NLW_U0_axi_ar_data_count_UNCONNECTED(4 downto 0),
axi_ar_dbiterr => NLW_U0_axi_ar_dbiterr_UNCONNECTED,
axi_ar_injectdbiterr => '0',
axi_ar_injectsbiterr => '0',
axi_ar_overflow => NLW_U0_axi_ar_overflow_UNCONNECTED,
axi_ar_prog_empty => NLW_U0_axi_ar_prog_empty_UNCONNECTED,
axi_ar_prog_empty_thresh(3) => '0',
axi_ar_prog_empty_thresh(2) => '0',
axi_ar_prog_empty_thresh(1) => '0',
axi_ar_prog_empty_thresh(0) => '0',
axi_ar_prog_full => NLW_U0_axi_ar_prog_full_UNCONNECTED,
axi_ar_prog_full_thresh(3) => '0',
axi_ar_prog_full_thresh(2) => '0',
axi_ar_prog_full_thresh(1) => '0',
axi_ar_prog_full_thresh(0) => '0',
axi_ar_rd_data_count(4 downto 0) => NLW_U0_axi_ar_rd_data_count_UNCONNECTED(4 downto 0),
axi_ar_sbiterr => NLW_U0_axi_ar_sbiterr_UNCONNECTED,
axi_ar_underflow => NLW_U0_axi_ar_underflow_UNCONNECTED,
axi_ar_wr_data_count(4 downto 0) => NLW_U0_axi_ar_wr_data_count_UNCONNECTED(4 downto 0),
axi_aw_data_count(4 downto 0) => NLW_U0_axi_aw_data_count_UNCONNECTED(4 downto 0),
axi_aw_dbiterr => NLW_U0_axi_aw_dbiterr_UNCONNECTED,
axi_aw_injectdbiterr => '0',
axi_aw_injectsbiterr => '0',
axi_aw_overflow => NLW_U0_axi_aw_overflow_UNCONNECTED,
axi_aw_prog_empty => NLW_U0_axi_aw_prog_empty_UNCONNECTED,
axi_aw_prog_empty_thresh(3) => '0',
axi_aw_prog_empty_thresh(2) => '0',
axi_aw_prog_empty_thresh(1) => '0',
axi_aw_prog_empty_thresh(0) => '0',
axi_aw_prog_full => NLW_U0_axi_aw_prog_full_UNCONNECTED,
axi_aw_prog_full_thresh(3) => '0',
axi_aw_prog_full_thresh(2) => '0',
axi_aw_prog_full_thresh(1) => '0',
axi_aw_prog_full_thresh(0) => '0',
axi_aw_rd_data_count(4 downto 0) => NLW_U0_axi_aw_rd_data_count_UNCONNECTED(4 downto 0),
axi_aw_sbiterr => NLW_U0_axi_aw_sbiterr_UNCONNECTED,
axi_aw_underflow => NLW_U0_axi_aw_underflow_UNCONNECTED,
axi_aw_wr_data_count(4 downto 0) => NLW_U0_axi_aw_wr_data_count_UNCONNECTED(4 downto 0),
axi_b_data_count(4 downto 0) => NLW_U0_axi_b_data_count_UNCONNECTED(4 downto 0),
axi_b_dbiterr => NLW_U0_axi_b_dbiterr_UNCONNECTED,
axi_b_injectdbiterr => '0',
axi_b_injectsbiterr => '0',
axi_b_overflow => NLW_U0_axi_b_overflow_UNCONNECTED,
axi_b_prog_empty => NLW_U0_axi_b_prog_empty_UNCONNECTED,
axi_b_prog_empty_thresh(3) => '0',
axi_b_prog_empty_thresh(2) => '0',
axi_b_prog_empty_thresh(1) => '0',
axi_b_prog_empty_thresh(0) => '0',
axi_b_prog_full => NLW_U0_axi_b_prog_full_UNCONNECTED,
axi_b_prog_full_thresh(3) => '0',
axi_b_prog_full_thresh(2) => '0',
axi_b_prog_full_thresh(1) => '0',
axi_b_prog_full_thresh(0) => '0',
axi_b_rd_data_count(4 downto 0) => NLW_U0_axi_b_rd_data_count_UNCONNECTED(4 downto 0),
axi_b_sbiterr => NLW_U0_axi_b_sbiterr_UNCONNECTED,
axi_b_underflow => NLW_U0_axi_b_underflow_UNCONNECTED,
axi_b_wr_data_count(4 downto 0) => NLW_U0_axi_b_wr_data_count_UNCONNECTED(4 downto 0),
axi_r_data_count(10 downto 0) => NLW_U0_axi_r_data_count_UNCONNECTED(10 downto 0),
axi_r_dbiterr => NLW_U0_axi_r_dbiterr_UNCONNECTED,
axi_r_injectdbiterr => '0',
axi_r_injectsbiterr => '0',
axi_r_overflow => NLW_U0_axi_r_overflow_UNCONNECTED,
axi_r_prog_empty => NLW_U0_axi_r_prog_empty_UNCONNECTED,
axi_r_prog_empty_thresh(9) => '0',
axi_r_prog_empty_thresh(8) => '0',
axi_r_prog_empty_thresh(7) => '0',
axi_r_prog_empty_thresh(6) => '0',
axi_r_prog_empty_thresh(5) => '0',
axi_r_prog_empty_thresh(4) => '0',
axi_r_prog_empty_thresh(3) => '0',
axi_r_prog_empty_thresh(2) => '0',
axi_r_prog_empty_thresh(1) => '0',
axi_r_prog_empty_thresh(0) => '0',
axi_r_prog_full => NLW_U0_axi_r_prog_full_UNCONNECTED,
axi_r_prog_full_thresh(9) => '0',
axi_r_prog_full_thresh(8) => '0',
axi_r_prog_full_thresh(7) => '0',
axi_r_prog_full_thresh(6) => '0',
axi_r_prog_full_thresh(5) => '0',
axi_r_prog_full_thresh(4) => '0',
axi_r_prog_full_thresh(3) => '0',
axi_r_prog_full_thresh(2) => '0',
axi_r_prog_full_thresh(1) => '0',
axi_r_prog_full_thresh(0) => '0',
axi_r_rd_data_count(10 downto 0) => NLW_U0_axi_r_rd_data_count_UNCONNECTED(10 downto 0),
axi_r_sbiterr => NLW_U0_axi_r_sbiterr_UNCONNECTED,
axi_r_underflow => NLW_U0_axi_r_underflow_UNCONNECTED,
axi_r_wr_data_count(10 downto 0) => NLW_U0_axi_r_wr_data_count_UNCONNECTED(10 downto 0),
axi_w_data_count(10 downto 0) => NLW_U0_axi_w_data_count_UNCONNECTED(10 downto 0),
axi_w_dbiterr => NLW_U0_axi_w_dbiterr_UNCONNECTED,
axi_w_injectdbiterr => '0',
axi_w_injectsbiterr => '0',
axi_w_overflow => NLW_U0_axi_w_overflow_UNCONNECTED,
axi_w_prog_empty => NLW_U0_axi_w_prog_empty_UNCONNECTED,
axi_w_prog_empty_thresh(9) => '0',
axi_w_prog_empty_thresh(8) => '0',
axi_w_prog_empty_thresh(7) => '0',
axi_w_prog_empty_thresh(6) => '0',
axi_w_prog_empty_thresh(5) => '0',
axi_w_prog_empty_thresh(4) => '0',
axi_w_prog_empty_thresh(3) => '0',
axi_w_prog_empty_thresh(2) => '0',
axi_w_prog_empty_thresh(1) => '0',
axi_w_prog_empty_thresh(0) => '0',
axi_w_prog_full => NLW_U0_axi_w_prog_full_UNCONNECTED,
axi_w_prog_full_thresh(9) => '0',
axi_w_prog_full_thresh(8) => '0',
axi_w_prog_full_thresh(7) => '0',
axi_w_prog_full_thresh(6) => '0',
axi_w_prog_full_thresh(5) => '0',
axi_w_prog_full_thresh(4) => '0',
axi_w_prog_full_thresh(3) => '0',
axi_w_prog_full_thresh(2) => '0',
axi_w_prog_full_thresh(1) => '0',
axi_w_prog_full_thresh(0) => '0',
axi_w_rd_data_count(10 downto 0) => NLW_U0_axi_w_rd_data_count_UNCONNECTED(10 downto 0),
axi_w_sbiterr => NLW_U0_axi_w_sbiterr_UNCONNECTED,
axi_w_underflow => NLW_U0_axi_w_underflow_UNCONNECTED,
axi_w_wr_data_count(10 downto 0) => NLW_U0_axi_w_wr_data_count_UNCONNECTED(10 downto 0),
axis_data_count(10 downto 0) => NLW_U0_axis_data_count_UNCONNECTED(10 downto 0),
axis_dbiterr => NLW_U0_axis_dbiterr_UNCONNECTED,
axis_injectdbiterr => '0',
axis_injectsbiterr => '0',
axis_overflow => NLW_U0_axis_overflow_UNCONNECTED,
axis_prog_empty => NLW_U0_axis_prog_empty_UNCONNECTED,
axis_prog_empty_thresh(9) => '0',
axis_prog_empty_thresh(8) => '0',
axis_prog_empty_thresh(7) => '0',
axis_prog_empty_thresh(6) => '0',
axis_prog_empty_thresh(5) => '0',
axis_prog_empty_thresh(4) => '0',
axis_prog_empty_thresh(3) => '0',
axis_prog_empty_thresh(2) => '0',
axis_prog_empty_thresh(1) => '0',
axis_prog_empty_thresh(0) => '0',
axis_prog_full => NLW_U0_axis_prog_full_UNCONNECTED,
axis_prog_full_thresh(9) => '0',
axis_prog_full_thresh(8) => '0',
axis_prog_full_thresh(7) => '0',
axis_prog_full_thresh(6) => '0',
axis_prog_full_thresh(5) => '0',
axis_prog_full_thresh(4) => '0',
axis_prog_full_thresh(3) => '0',
axis_prog_full_thresh(2) => '0',
axis_prog_full_thresh(1) => '0',
axis_prog_full_thresh(0) => '0',
axis_rd_data_count(10 downto 0) => NLW_U0_axis_rd_data_count_UNCONNECTED(10 downto 0),
axis_sbiterr => NLW_U0_axis_sbiterr_UNCONNECTED,
axis_underflow => NLW_U0_axis_underflow_UNCONNECTED,
axis_wr_data_count(10 downto 0) => NLW_U0_axis_wr_data_count_UNCONNECTED(10 downto 0),
backup => '0',
backup_marker => '0',
clk => '0',
data_count(3 downto 0) => NLW_U0_data_count_UNCONNECTED(3 downto 0),
dbiterr => NLW_U0_dbiterr_UNCONNECTED,
din(102 downto 0) => din(102 downto 0),
dout(102 downto 0) => dout(102 downto 0),
empty => empty,
full => full,
injectdbiterr => '0',
injectsbiterr => '0',
int_clk => '0',
m_aclk => '0',
m_aclk_en => '0',
m_axi_araddr(31 downto 0) => NLW_U0_m_axi_araddr_UNCONNECTED(31 downto 0),
m_axi_arburst(1 downto 0) => NLW_U0_m_axi_arburst_UNCONNECTED(1 downto 0),
m_axi_arcache(3 downto 0) => NLW_U0_m_axi_arcache_UNCONNECTED(3 downto 0),
m_axi_arid(0) => NLW_U0_m_axi_arid_UNCONNECTED(0),
m_axi_arlen(7 downto 0) => NLW_U0_m_axi_arlen_UNCONNECTED(7 downto 0),
m_axi_arlock(0) => NLW_U0_m_axi_arlock_UNCONNECTED(0),
m_axi_arprot(2 downto 0) => NLW_U0_m_axi_arprot_UNCONNECTED(2 downto 0),
m_axi_arqos(3 downto 0) => NLW_U0_m_axi_arqos_UNCONNECTED(3 downto 0),
m_axi_arready => '0',
m_axi_arregion(3 downto 0) => NLW_U0_m_axi_arregion_UNCONNECTED(3 downto 0),
m_axi_arsize(2 downto 0) => NLW_U0_m_axi_arsize_UNCONNECTED(2 downto 0),
m_axi_aruser(0) => NLW_U0_m_axi_aruser_UNCONNECTED(0),
m_axi_arvalid => NLW_U0_m_axi_arvalid_UNCONNECTED,
m_axi_awaddr(31 downto 0) => NLW_U0_m_axi_awaddr_UNCONNECTED(31 downto 0),
m_axi_awburst(1 downto 0) => NLW_U0_m_axi_awburst_UNCONNECTED(1 downto 0),
m_axi_awcache(3 downto 0) => NLW_U0_m_axi_awcache_UNCONNECTED(3 downto 0),
m_axi_awid(0) => NLW_U0_m_axi_awid_UNCONNECTED(0),
m_axi_awlen(7 downto 0) => NLW_U0_m_axi_awlen_UNCONNECTED(7 downto 0),
m_axi_awlock(0) => NLW_U0_m_axi_awlock_UNCONNECTED(0),
m_axi_awprot(2 downto 0) => NLW_U0_m_axi_awprot_UNCONNECTED(2 downto 0),
m_axi_awqos(3 downto 0) => NLW_U0_m_axi_awqos_UNCONNECTED(3 downto 0),
m_axi_awready => '0',
m_axi_awregion(3 downto 0) => NLW_U0_m_axi_awregion_UNCONNECTED(3 downto 0),
m_axi_awsize(2 downto 0) => NLW_U0_m_axi_awsize_UNCONNECTED(2 downto 0),
m_axi_awuser(0) => NLW_U0_m_axi_awuser_UNCONNECTED(0),
m_axi_awvalid => NLW_U0_m_axi_awvalid_UNCONNECTED,
m_axi_bid(0) => '0',
m_axi_bready => NLW_U0_m_axi_bready_UNCONNECTED,
m_axi_bresp(1) => '0',
m_axi_bresp(0) => '0',
m_axi_buser(0) => '0',
m_axi_bvalid => '0',
m_axi_rdata(63) => '0',
m_axi_rdata(62) => '0',
m_axi_rdata(61) => '0',
m_axi_rdata(60) => '0',
m_axi_rdata(59) => '0',
m_axi_rdata(58) => '0',
m_axi_rdata(57) => '0',
m_axi_rdata(56) => '0',
m_axi_rdata(55) => '0',
m_axi_rdata(54) => '0',
m_axi_rdata(53) => '0',
m_axi_rdata(52) => '0',
m_axi_rdata(51) => '0',
m_axi_rdata(50) => '0',
m_axi_rdata(49) => '0',
m_axi_rdata(48) => '0',
m_axi_rdata(47) => '0',
m_axi_rdata(46) => '0',
m_axi_rdata(45) => '0',
m_axi_rdata(44) => '0',
m_axi_rdata(43) => '0',
m_axi_rdata(42) => '0',
m_axi_rdata(41) => '0',
m_axi_rdata(40) => '0',
m_axi_rdata(39) => '0',
m_axi_rdata(38) => '0',
m_axi_rdata(37) => '0',
m_axi_rdata(36) => '0',
m_axi_rdata(35) => '0',
m_axi_rdata(34) => '0',
m_axi_rdata(33) => '0',
m_axi_rdata(32) => '0',
m_axi_rdata(31) => '0',
m_axi_rdata(30) => '0',
m_axi_rdata(29) => '0',
m_axi_rdata(28) => '0',
m_axi_rdata(27) => '0',
m_axi_rdata(26) => '0',
m_axi_rdata(25) => '0',
m_axi_rdata(24) => '0',
m_axi_rdata(23) => '0',
m_axi_rdata(22) => '0',
m_axi_rdata(21) => '0',
m_axi_rdata(20) => '0',
m_axi_rdata(19) => '0',
m_axi_rdata(18) => '0',
m_axi_rdata(17) => '0',
m_axi_rdata(16) => '0',
m_axi_rdata(15) => '0',
m_axi_rdata(14) => '0',
m_axi_rdata(13) => '0',
m_axi_rdata(12) => '0',
m_axi_rdata(11) => '0',
m_axi_rdata(10) => '0',
m_axi_rdata(9) => '0',
m_axi_rdata(8) => '0',
m_axi_rdata(7) => '0',
m_axi_rdata(6) => '0',
m_axi_rdata(5) => '0',
m_axi_rdata(4) => '0',
m_axi_rdata(3) => '0',
m_axi_rdata(2) => '0',
m_axi_rdata(1) => '0',
m_axi_rdata(0) => '0',
m_axi_rid(0) => '0',
m_axi_rlast => '0',
m_axi_rready => NLW_U0_m_axi_rready_UNCONNECTED,
m_axi_rresp(1) => '0',
m_axi_rresp(0) => '0',
m_axi_ruser(0) => '0',
m_axi_rvalid => '0',
m_axi_wdata(63 downto 0) => NLW_U0_m_axi_wdata_UNCONNECTED(63 downto 0),
m_axi_wid(0) => NLW_U0_m_axi_wid_UNCONNECTED(0),
m_axi_wlast => NLW_U0_m_axi_wlast_UNCONNECTED,
m_axi_wready => '0',
m_axi_wstrb(7 downto 0) => NLW_U0_m_axi_wstrb_UNCONNECTED(7 downto 0),
m_axi_wuser(0) => NLW_U0_m_axi_wuser_UNCONNECTED(0),
m_axi_wvalid => NLW_U0_m_axi_wvalid_UNCONNECTED,
m_axis_tdata(7 downto 0) => NLW_U0_m_axis_tdata_UNCONNECTED(7 downto 0),
m_axis_tdest(0) => NLW_U0_m_axis_tdest_UNCONNECTED(0),
m_axis_tid(0) => NLW_U0_m_axis_tid_UNCONNECTED(0),
m_axis_tkeep(0) => NLW_U0_m_axis_tkeep_UNCONNECTED(0),
m_axis_tlast => NLW_U0_m_axis_tlast_UNCONNECTED,
m_axis_tready => '0',
m_axis_tstrb(0) => NLW_U0_m_axis_tstrb_UNCONNECTED(0),
m_axis_tuser(3 downto 0) => NLW_U0_m_axis_tuser_UNCONNECTED(3 downto 0),
m_axis_tvalid => NLW_U0_m_axis_tvalid_UNCONNECTED,
overflow => NLW_U0_overflow_UNCONNECTED,
prog_empty => NLW_U0_prog_empty_UNCONNECTED,
prog_empty_thresh(3) => '0',
prog_empty_thresh(2) => '0',
prog_empty_thresh(1) => '0',
prog_empty_thresh(0) => '0',
prog_empty_thresh_assert(3) => '0',
prog_empty_thresh_assert(2) => '0',
prog_empty_thresh_assert(1) => '0',
prog_empty_thresh_assert(0) => '0',
prog_empty_thresh_negate(3) => '0',
prog_empty_thresh_negate(2) => '0',
prog_empty_thresh_negate(1) => '0',
prog_empty_thresh_negate(0) => '0',
prog_full => prog_full,
prog_full_thresh(3) => '0',
prog_full_thresh(2) => '0',
prog_full_thresh(1) => '0',
prog_full_thresh(0) => '0',
prog_full_thresh_assert(3) => '0',
prog_full_thresh_assert(2) => '0',
prog_full_thresh_assert(1) => '0',
prog_full_thresh_assert(0) => '0',
prog_full_thresh_negate(3) => '0',
prog_full_thresh_negate(2) => '0',
prog_full_thresh_negate(1) => '0',
prog_full_thresh_negate(0) => '0',
rd_clk => rd_clk,
rd_data_count(3 downto 0) => NLW_U0_rd_data_count_UNCONNECTED(3 downto 0),
rd_en => rd_en,
rd_rst => '0',
rd_rst_busy => NLW_U0_rd_rst_busy_UNCONNECTED,
rst => rst,
s_aclk => '0',
s_aclk_en => '0',
s_aresetn => '0',
s_axi_araddr(31) => '0',
s_axi_araddr(30) => '0',
s_axi_araddr(29) => '0',
s_axi_araddr(28) => '0',
s_axi_araddr(27) => '0',
s_axi_araddr(26) => '0',
s_axi_araddr(25) => '0',
s_axi_araddr(24) => '0',
s_axi_araddr(23) => '0',
s_axi_araddr(22) => '0',
s_axi_araddr(21) => '0',
s_axi_araddr(20) => '0',
s_axi_araddr(19) => '0',
s_axi_araddr(18) => '0',
s_axi_araddr(17) => '0',
s_axi_araddr(16) => '0',
s_axi_araddr(15) => '0',
s_axi_araddr(14) => '0',
s_axi_araddr(13) => '0',
s_axi_araddr(12) => '0',
s_axi_araddr(11) => '0',
s_axi_araddr(10) => '0',
s_axi_araddr(9) => '0',
s_axi_araddr(8) => '0',
s_axi_araddr(7) => '0',
s_axi_araddr(6) => '0',
s_axi_araddr(5) => '0',
s_axi_araddr(4) => '0',
s_axi_araddr(3) => '0',
s_axi_araddr(2) => '0',
s_axi_araddr(1) => '0',
s_axi_araddr(0) => '0',
s_axi_arburst(1) => '0',
s_axi_arburst(0) => '0',
s_axi_arcache(3) => '0',
s_axi_arcache(2) => '0',
s_axi_arcache(1) => '0',
s_axi_arcache(0) => '0',
s_axi_arid(0) => '0',
s_axi_arlen(7) => '0',
s_axi_arlen(6) => '0',
s_axi_arlen(5) => '0',
s_axi_arlen(4) => '0',
s_axi_arlen(3) => '0',
s_axi_arlen(2) => '0',
s_axi_arlen(1) => '0',
s_axi_arlen(0) => '0',
s_axi_arlock(0) => '0',
s_axi_arprot(2) => '0',
s_axi_arprot(1) => '0',
s_axi_arprot(0) => '0',
s_axi_arqos(3) => '0',
s_axi_arqos(2) => '0',
s_axi_arqos(1) => '0',
s_axi_arqos(0) => '0',
s_axi_arready => NLW_U0_s_axi_arready_UNCONNECTED,
s_axi_arregion(3) => '0',
s_axi_arregion(2) => '0',
s_axi_arregion(1) => '0',
s_axi_arregion(0) => '0',
s_axi_arsize(2) => '0',
s_axi_arsize(1) => '0',
s_axi_arsize(0) => '0',
s_axi_aruser(0) => '0',
s_axi_arvalid => '0',
s_axi_awaddr(31) => '0',
s_axi_awaddr(30) => '0',
s_axi_awaddr(29) => '0',
s_axi_awaddr(28) => '0',
s_axi_awaddr(27) => '0',
s_axi_awaddr(26) => '0',
s_axi_awaddr(25) => '0',
s_axi_awaddr(24) => '0',
s_axi_awaddr(23) => '0',
s_axi_awaddr(22) => '0',
s_axi_awaddr(21) => '0',
s_axi_awaddr(20) => '0',
s_axi_awaddr(19) => '0',
s_axi_awaddr(18) => '0',
s_axi_awaddr(17) => '0',
s_axi_awaddr(16) => '0',
s_axi_awaddr(15) => '0',
s_axi_awaddr(14) => '0',
s_axi_awaddr(13) => '0',
s_axi_awaddr(12) => '0',
s_axi_awaddr(11) => '0',
s_axi_awaddr(10) => '0',
s_axi_awaddr(9) => '0',
s_axi_awaddr(8) => '0',
s_axi_awaddr(7) => '0',
s_axi_awaddr(6) => '0',
s_axi_awaddr(5) => '0',
s_axi_awaddr(4) => '0',
s_axi_awaddr(3) => '0',
s_axi_awaddr(2) => '0',
s_axi_awaddr(1) => '0',
s_axi_awaddr(0) => '0',
s_axi_awburst(1) => '0',
s_axi_awburst(0) => '0',
s_axi_awcache(3) => '0',
s_axi_awcache(2) => '0',
s_axi_awcache(1) => '0',
s_axi_awcache(0) => '0',
s_axi_awid(0) => '0',
s_axi_awlen(7) => '0',
s_axi_awlen(6) => '0',
s_axi_awlen(5) => '0',
s_axi_awlen(4) => '0',
s_axi_awlen(3) => '0',
s_axi_awlen(2) => '0',
s_axi_awlen(1) => '0',
s_axi_awlen(0) => '0',
s_axi_awlock(0) => '0',
s_axi_awprot(2) => '0',
s_axi_awprot(1) => '0',
s_axi_awprot(0) => '0',
s_axi_awqos(3) => '0',
s_axi_awqos(2) => '0',
s_axi_awqos(1) => '0',
s_axi_awqos(0) => '0',
s_axi_awready => NLW_U0_s_axi_awready_UNCONNECTED,
s_axi_awregion(3) => '0',
s_axi_awregion(2) => '0',
s_axi_awregion(1) => '0',
s_axi_awregion(0) => '0',
s_axi_awsize(2) => '0',
s_axi_awsize(1) => '0',
s_axi_awsize(0) => '0',
s_axi_awuser(0) => '0',
s_axi_awvalid => '0',
s_axi_bid(0) => NLW_U0_s_axi_bid_UNCONNECTED(0),
s_axi_bready => '0',
s_axi_bresp(1 downto 0) => NLW_U0_s_axi_bresp_UNCONNECTED(1 downto 0),
s_axi_buser(0) => NLW_U0_s_axi_buser_UNCONNECTED(0),
s_axi_bvalid => NLW_U0_s_axi_bvalid_UNCONNECTED,
s_axi_rdata(63 downto 0) => NLW_U0_s_axi_rdata_UNCONNECTED(63 downto 0),
s_axi_rid(0) => NLW_U0_s_axi_rid_UNCONNECTED(0),
s_axi_rlast => NLW_U0_s_axi_rlast_UNCONNECTED,
s_axi_rready => '0',
s_axi_rresp(1 downto 0) => NLW_U0_s_axi_rresp_UNCONNECTED(1 downto 0),
s_axi_ruser(0) => NLW_U0_s_axi_ruser_UNCONNECTED(0),
s_axi_rvalid => NLW_U0_s_axi_rvalid_UNCONNECTED,
s_axi_wdata(63) => '0',
s_axi_wdata(62) => '0',
s_axi_wdata(61) => '0',
s_axi_wdata(60) => '0',
s_axi_wdata(59) => '0',
s_axi_wdata(58) => '0',
s_axi_wdata(57) => '0',
s_axi_wdata(56) => '0',
s_axi_wdata(55) => '0',
s_axi_wdata(54) => '0',
s_axi_wdata(53) => '0',
s_axi_wdata(52) => '0',
s_axi_wdata(51) => '0',
s_axi_wdata(50) => '0',
s_axi_wdata(49) => '0',
s_axi_wdata(48) => '0',
s_axi_wdata(47) => '0',
s_axi_wdata(46) => '0',
s_axi_wdata(45) => '0',
s_axi_wdata(44) => '0',
s_axi_wdata(43) => '0',
s_axi_wdata(42) => '0',
s_axi_wdata(41) => '0',
s_axi_wdata(40) => '0',
s_axi_wdata(39) => '0',
s_axi_wdata(38) => '0',
s_axi_wdata(37) => '0',
s_axi_wdata(36) => '0',
s_axi_wdata(35) => '0',
s_axi_wdata(34) => '0',
s_axi_wdata(33) => '0',
s_axi_wdata(32) => '0',
s_axi_wdata(31) => '0',
s_axi_wdata(30) => '0',
s_axi_wdata(29) => '0',
s_axi_wdata(28) => '0',
s_axi_wdata(27) => '0',
s_axi_wdata(26) => '0',
s_axi_wdata(25) => '0',
s_axi_wdata(24) => '0',
s_axi_wdata(23) => '0',
s_axi_wdata(22) => '0',
s_axi_wdata(21) => '0',
s_axi_wdata(20) => '0',
s_axi_wdata(19) => '0',
s_axi_wdata(18) => '0',
s_axi_wdata(17) => '0',
s_axi_wdata(16) => '0',
s_axi_wdata(15) => '0',
s_axi_wdata(14) => '0',
s_axi_wdata(13) => '0',
s_axi_wdata(12) => '0',
s_axi_wdata(11) => '0',
s_axi_wdata(10) => '0',
s_axi_wdata(9) => '0',
s_axi_wdata(8) => '0',
s_axi_wdata(7) => '0',
s_axi_wdata(6) => '0',
s_axi_wdata(5) => '0',
s_axi_wdata(4) => '0',
s_axi_wdata(3) => '0',
s_axi_wdata(2) => '0',
s_axi_wdata(1) => '0',
s_axi_wdata(0) => '0',
s_axi_wid(0) => '0',
s_axi_wlast => '0',
s_axi_wready => NLW_U0_s_axi_wready_UNCONNECTED,
s_axi_wstrb(7) => '0',
s_axi_wstrb(6) => '0',
s_axi_wstrb(5) => '0',
s_axi_wstrb(4) => '0',
s_axi_wstrb(3) => '0',
s_axi_wstrb(2) => '0',
s_axi_wstrb(1) => '0',
s_axi_wstrb(0) => '0',
s_axi_wuser(0) => '0',
s_axi_wvalid => '0',
s_axis_tdata(7) => '0',
s_axis_tdata(6) => '0',
s_axis_tdata(5) => '0',
s_axis_tdata(4) => '0',
s_axis_tdata(3) => '0',
s_axis_tdata(2) => '0',
s_axis_tdata(1) => '0',
s_axis_tdata(0) => '0',
s_axis_tdest(0) => '0',
s_axis_tid(0) => '0',
s_axis_tkeep(0) => '0',
s_axis_tlast => '0',
s_axis_tready => NLW_U0_s_axis_tready_UNCONNECTED,
s_axis_tstrb(0) => '0',
s_axis_tuser(3) => '0',
s_axis_tuser(2) => '0',
s_axis_tuser(1) => '0',
s_axis_tuser(0) => '0',
s_axis_tvalid => '0',
sbiterr => NLW_U0_sbiterr_UNCONNECTED,
sleep => '0',
srst => '0',
underflow => NLW_U0_underflow_UNCONNECTED,
valid => NLW_U0_valid_UNCONNECTED,
wr_ack => NLW_U0_wr_ack_UNCONNECTED,
wr_clk => wr_clk,
wr_data_count(3 downto 0) => NLW_U0_wr_data_count_UNCONNECTED(3 downto 0),
wr_en => wr_en,
wr_rst => '0',
wr_rst_busy => NLW_U0_wr_rst_busy_UNCONNECTED
);
end STRUCTURE;
| gpl-3.0 |
JuanMarcosRamirez/WeightedMedianDisenoLogico | misc/FPGA/otros/loopback/uart_rx.vhd | 5 | 4974 | -- UART Receiver with integral 16 byte FIFO buffer
--
-- 8 bit, no parity, 1 stop bit
--
-- Version : 1.00
-- Version Date : 16th October 2002
--
-- Start of design entry : 16th October 2002
--
-- Ken Chapman
-- Xilinx Ltd
-- Benchmark House
-- 203 Brooklands Road
-- Weybridge
-- Surrey KT13 ORH
-- United Kingdom
--
-- [email protected]
--
------------------------------------------------------------------------------------
--
-- NOTICE:
--
-- Copyright Xilinx, Inc. 2002. This code may be contain portions patented by other
-- third parties. By providing this core as one possible implementation of a standard,
-- Xilinx is making no representation that the provided implementation of this standard
-- is free from any claims of infringement by any third party. Xilinx expressly
-- disclaims any warranty with respect to the adequacy of the implementation, including
-- but not limited to any warranty or representation that the implementation is free
-- from claims of any third party. Futhermore, Xilinx is providing this core as a
-- courtesy to you and suggests that you contact all third parties to obtain the
-- necessary rights to use this implementation.
--
------------------------------------------------------------------------------------
--
-- Library declarations
--
-- The Unisim Library is used to define Xilinx primitives. It is also used during
-- simulation. The source can be viewed at %XILINX%\vhdl\src\unisims\unisim_VCOMP.vhd
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library unisim;
use unisim.vcomponents.all;
--
------------------------------------------------------------------------------------
--
-- Main Entity for UART_RX
--
entity uart_rx is
Port ( serial_in : in std_logic;
data_out : out std_logic_vector(7 downto 0);
read_buffer : in std_logic;
reset_buffer : in std_logic;
en_16_x_baud : in std_logic;
buffer_data_present : out std_logic;
buffer_full : out std_logic;
buffer_half_full : out std_logic;
clk : in std_logic);
end uart_rx;
--
------------------------------------------------------------------------------------
--
-- Start of Main Architecture for UART_RX
--
architecture macro_level_definition of uart_rx is
--
------------------------------------------------------------------------------------
--
-- Components used in UART_RX and defined in subsequent entities.
--
------------------------------------------------------------------------------------
--
-- Constant (K) Compact UART Receiver
--
component kcuart_rx
Port ( serial_in : in std_logic;
data_out : out std_logic_vector(7 downto 0);
data_strobe : out std_logic;
en_16_x_baud : in std_logic;
clk : in std_logic);
end component;
--
-- 'Bucket Brigade' FIFO
--
component bbfifo_16x8
Port ( data_in : in std_logic_vector(7 downto 0);
data_out : out std_logic_vector(7 downto 0);
reset : in std_logic;
write : in std_logic;
read : in std_logic;
full : out std_logic;
half_full : out std_logic;
data_present : out std_logic;
clk : in std_logic);
end component;
--
------------------------------------------------------------------------------------
--
-- Signals used in UART_RX
--
------------------------------------------------------------------------------------
--
signal uart_data_out : std_logic_vector(7 downto 0);
signal fifo_write : std_logic;
--
------------------------------------------------------------------------------------
--
-- Start of UART_RX circuit description
--
------------------------------------------------------------------------------------
--
begin
-- 8 to 1 multiplexer to convert parallel data to serial
kcuart: kcuart_rx
port map ( serial_in => serial_in,
data_out => uart_data_out,
data_strobe => fifo_write,
en_16_x_baud => en_16_x_baud,
clk => clk );
buf: bbfifo_16x8
port map ( data_in => uart_data_out,
data_out => data_out,
reset => reset_buffer,
write => fifo_write,
read => read_buffer,
full => buffer_full,
half_full => buffer_half_full,
data_present => buffer_data_present,
clk => clk);
end macro_level_definition;
------------------------------------------------------------------------------------
--
-- END OF FILE UART_RX.VHD
--
------------------------------------------------------------------------------------
| gpl-3.0 |
DougFirErickson/parallella-hw | fpga/ip/xilinx/fifo_async_103x16/fifo_async_103x16/blk_mem_gen_v8_2/hdl/blk_mem_min_area_pkg.vhd | 8 | 20310 | `protect begin_protected
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`protect end_protected
| gpl-3.0 |
DougFirErickson/parallella-hw | fpga/ip/xilinx/memory_dp_48x4096/blk_mem_gen_v8_2/hdl/blk_mem_axi_regs_fwd.vhd | 8 | 9545 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 5328)
`protect data_block
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`protect end_protected
| gpl-3.0 |
JuanMarcosRamirez/WeightedMedianDisenoLogico | misc/FPGA/window_3x3_x.vhd | 3 | 12483 | --------------------------------------------------------------------------
-- Autor: Jorge Márquez
-- Archivo adaptado para la generación de ventanas de 3x3 píxeles para
-- imágenes de tamaño 512x512. El funcionamiento que se expone con detalle
-- en el capítulo 2 del informe.
--
-- Este código se encuentra también en la sección de
-- Apéndices del informe de trabajo de grado PROCESAMIENTO DE IMÁGENES DE
-- ANGIOGRAFÍA BIPLANA USANDO UNA TARJETA DE DESARROLLO SPARTAN-3E
--
-- UNIVERSIDAD DE LOS ANDES
-- FACULTAD DE INGENIERÍA
-- ESCUELA DE INGENIERÍA ELÉCTRICA
--
-- Mérida, Septiembre, 2008
--
---------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
entity window_3x3 is
generic (
vwidth: integer:=8
);
port (
Clk : in std_logic;
RSTn : in std_logic;
D : in std_logic_vector(vwidth-1 downto 0);
w11 : out std_logic_vector(vwidth -1 downto 0);
w12 : out std_logic_vector(vwidth -1 downto 0);
w13 : out std_logic_vector(vwidth -1 downto 0);
w21 : out std_logic_vector(vwidth -1 downto 0);
w22 : out std_logic_vector(vwidth -1 downto 0);
w23 : out std_logic_vector(vwidth -1 downto 0);
w31 : out std_logic_vector(vwidth -1 downto 0);
w32 : out std_logic_vector(vwidth -1 downto 0);
w33 : out std_logic_vector(vwidth -1 downto 0);
DV : out std_logic:='0'
);
end window_3x3;
architecture window_3x3 of window_3x3 is
component fifo_512x8x
port (
din : IN std_logic_VECTOR(7 downto 0);
wr_en : IN std_logic;
wr_clk : IN std_logic;
rd_en : IN std_logic;
rd_clk : IN std_logic;
rst : IN std_logic;
dout : OUT std_logic_VECTOR(7 downto 0);
full : OUT std_logic;
empty : OUT std_logic;
wr_data_count: OUT std_logic_VECTOR(8 downto 0));
end component;
signal a00 : std_logic_vector(vwidth-1 downto 0);
signal a11 : std_logic_vector(vwidth-1 downto 0);
signal a12 : std_logic_vector(vwidth-1 downto 0);
signal a13 : std_logic_vector(vwidth-1 downto 0);
signal a21 : std_logic_vector(vwidth-1 downto 0);
signal a22 : std_logic_vector(vwidth-1 downto 0);
signal a23 : std_logic_vector(vwidth-1 downto 0);
signal a31 : std_logic_vector(vwidth-1 downto 0);
signal a32 : std_logic_vector(vwidth-1 downto 0);
signal a33 : std_logic_vector(vwidth-1 downto 0);
--fifoa signals
signal clear : std_logic;
signal wrreqa : std_logic:='1';
signal rdreqa : std_logic:='0';
signal ofulla : std_logic;
signal oemptya : std_logic;
signal ofifoa : std_logic_vector(vwidth-1 downto 0);
signal ousedwa : std_logic_VECTOR(8 downto 0);
--fifob signals
signal wrreqb : std_logic:='0';
signal rdreqb : std_logic:='0';
signal ofullb : std_logic;
signal oemptyb : std_logic;
signal ofifob : std_logic_vector(vwidth-1 downto 0);
signal ousedwb : std_logic_VECTOR(8 downto 0);
signal dwrreqb: std_logic:='0';
-- signals for DV coordination
signal dddddddDV: std_logic :='0';
signal ddddddDV: std_logic:='0';
signal dddddDV: std_logic:='0';
signal ddddDV: std_logic:='0';
signal dddDV: std_logic:='0';
signal ddDV: std_logic:='0';
signal dDV: std_logic:='0';
signal ousedwa_temp: integer:=0;
signal ousedwb_temp: integer:=0;
begin
fifoa: fifo_512x8x
port map ( -- port map fifo a
din => a13, -- port map fifo a
wr_en => wrreqa, -- port map fifo a
wr_clk => Clk, -- port map fifo a
rd_en => rdreqa, -- port map fifo a
rd_clk => Clk, -- port map fifo a
rst => clear, -- port map fifo a
dout => ofifoa, -- port map fifo a
full => ofulla, -- port map fifo a
empty => oemptya, -- port map fifo a
wr_data_count => ousedwa -- port map fifo a
); -- port map fifo a
fifob: fifo_512x8x
port map ( -- port map fifo b
din => a23, -- port map fifo b
wr_en => wrreqb, -- port map fifo b
wr_clk => Clk, -- port map fifo b
rd_en => rdreqb, -- port map fifo b
rd_clk => Clk, -- port map fifo b
rst => clear, -- port map fifo b
dout => ofifob, -- port map fifo b
full => ofullb, -- port map fifo b
empty => oemptyb, -- port map fifo b
wr_data_count => ousedwb -- port map fifo b
); -- port map fifo b
clear <= not(RSTn);
clock: process(Clk,RSTn)
begin --clock
if RSTn = '0' then --clock
a11 <= (others=>'0'); --clock
a12 <= (others=>'0'); --clock
a13 <= (others=>'0'); --clock
a21 <= (others=>'0'); --clock
a22 <= (others=>'0'); --clock
a23 <= (others=>'0'); --clock
a31 <= (others=>'0'); --clock
a32 <= (others=>'0'); --clock
a33 <= (others=>'0'); --clock
w11 <= (others=>'0'); --clock
w12 <= (others=>'0'); --clock
w13 <= (others=>'0'); --clock
w21 <= (others=>'0'); --clock
w22 <= (others=>'0'); --clock
w23 <= (others=>'0'); --clock
w31 <= (others=>'0'); --clock
w32 <= (others=>'0'); --clock
w33 <= (others=>'0'); --clock
wrreqa <= '0'; --clock
wrreqb <= '0'; --clock
-- dddddddDV <= '0'; -- 7 ds --clock
ddddddDV <= '0'; --clock
dddddDV <= '0'; --clock
ddddDV <= '0'; --clock
dddDV <= '0'; --clock
ddDV <= '0'; --clock
dDV <= '0'; --clock
DV <= '0'; --clock
elsif rising_edge(Clk) then --clock
--clock
a00 <= D; --clock
--clock
a11 <= a00; --clock
w11 <= a00; --clock
--clock
--clock
w12 <= a11; --clock
a12 <= a11; --clock
--clock
w13 <= a12; --clock
a13 <= a12; --clock
--clock
--clock
w21 <= ofifoa; --clock
a21 <= ofifoa; --clock
--clock
w22 <= a21; --clock
a22 <= a21; --clock
--clock
w23 <= a22; --clock
a23 <= a22; --clock
--clock
w31 <= ofifob; --clock
a31 <= ofifob; --clock
--clock
w32 <= a31; --clock
a32 <= a31; --clock
--clock
w33 <= a32; --clock
a33 <= a32; --clock
--clock
wrreqa <= '1'; --clock
wrreqb <= dwrreqb; --clock
--clock
ddddddDV <= dddddddDV; --04/06/08 --clock
dddddDV <= ddddddDV; --clock
ddddDV <= dddddDV; --clock
dddDV <= ddddDV; --clock
ddDV <= dddDV; --clock
dDV <= ddDV; --clock
DV <= dDV; --clock
end if; --clock
end process; --clock
req: process(Clk) -- req
begin -- req
if rising_edge(Clk) then -- req
if ousedwa = "111111010" then -- req
rdreqa <= '1'; -- req
dwrreqb <= '1'; -- req
end if; -- req
if ousedwb = "111111010" then -- req
rdreqb <= '1'; -- req
dddddddDV <= '1'; --04/06/08 ds -- req
end if; -- req
end if; -- req
end process; -- req
end window_3x3;
| gpl-3.0 |
viccuad/fpga-lunarLanderGame | lunarLander.vhd | 1 | 60653 |
library IEEE;
library UNISIM;
use UNISIM.vcomponents.all;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- juego original de atari lunar lander en: http://my.ign.com/atari/lunar-lander
entity lunarLander is
port (
ps2Clk: IN std_logic;
ps2Data: IN std_logic;
clk: IN std_logic;
reset: IN std_logic; --reset activo a baja!
modoSiloIN: IN std_logic;
hSync: OUT std_logic;
Vsync: OUT std_logic;
segs: OUT std_logic_vector (6 downto 0);
R: OUT std_logic_vector (2 downto 0); -- alconversor D/A
G: OUT std_logic_vector (2 downto 0); -- alconversor D/A
B: OUT std_logic_vector (2 downto 0) -- alconversor D/A
);
end lunar-lander;
architecture Behavioral of lunarLander is
component ps2KeyboardInterface
port ( clk: IN std_logic;
rst: IN std_logic;
ps2Clk: IN std_logic;
ps2Data: IN std_logic;
data: OUT std_logic_vector (7 DOWNTO 0);
newData: OUT std_logic;
newDataAck: IN std_logic
);
end component;
--seniales estados
type fsmEstados is (pulsadas, despulsadas);
signal estadoTeclado: fsmEstados;
type fsmEstados2 is (iniciando, jugando, parado, reseteo);
signal estadoJuego: fsmEstados2;
type fsmEstados3 is (generaAleatOBase, guardaPixelVer, pintarCol);
signal estadoGenMundo: fsmEstados3;
--señales PS2
signal newData, newDataAck: std_logic;
signal scancode: std_logic_vector (7 downto 0);
--señales VGA
signal senialHSync, senialVSync: std_logic;
signal finPixelCont: std_logic;
signal cuentaPixelCont: std_logic_vector (10 downto 0);
signal cuentaLineCont: std_logic_vector (9 downto 0);
signal comp1, comp2, comp3, comp4, comp5, comp6: std_logic;
signal Rnave,Rmundo,Rbase,R_ml,R_l,R_r,R_mr,Rvel,Rfuego,Rfuel,Rboom: std_logic_vector (2 downto 0);
signal Gnave,Gmundo,Gbase,G_ml,G_l,G_r,G_mr,Gvel,Gfuego,Gfuel,Gboom: std_logic_vector (2 downto 0);
signal Bnave,Bmundo,Bbase,B_ml,B_l,B_r,B_mr,Bvel,Bfuego,Bfuel,Bboom: std_logic_vector (2 downto 0);
--seniales registro lsfr
signal D,Q: std_logic_vector (14 downto 0);
signal puertaAND: std_logic_vector (0 downto 0);
--señales mundo
signal pixelMundoHor, pixelNaveHor: std_logic_vector (7 downto 0); --153 pixeles (10011001)
signal pixelMundoVer, pixelNaveVer,pixelAnteriorVer: std_logic_vector (6 downto 0); --102 pixeles
signal regBaseDificil1,regBaseDificil2,regBaseFacil: std_logic_vector (6 downto 0);
signal contMod3: std_logic_vector(1 downto 0);
signal clContMod3,generarBases: std_logic;
--señales nave
signal haAterrizado,BiestableHaAterrizado: std_logic;
signal posNave: std_logic_vector (14 downto 0); --pixelNaveHor catenado pixelNaveVer
signal cuentaVelVertical, cuentaVelHorizontal: std_logic_vector (6 downto 0);
signal muyLentoVertical,lentoVertical,rapidoVertical,muyRapidoVertical: std_logic;
signal muyLentoHorizontal,lentoHorizontal,rapidoHorizontal,muyRapidoHorizontal: std_logic;
signal movNave: std_logic_vector (2 downto 0); -- 000 = no se mueve , 001 = arriba , 010 = abajo , 011 = izquierda, 100 = derecha
signal moverNave: std_logic;
--señales juego
signal teclaSPC,teclaW,teclaS,teclaA,teclaD: std_logic;
signal clTeclaSPC,clTeclaW,clTeclaS,clTeclaA,clTeclaD: std_logic;
signal ldTeclaSPC,ldTeclaW,ldTeclaS,ldTeclaA,ldTeclaD: std_logic;
signal cuentaMuyRapido: STD_LOGIC_VECTOR(20 downto 0);
signal cuentaRapido: STD_LOGIC_VECTOR(21 downto 0);
signal cuentaLento: STD_LOGIC_VECTOR(22 downto 0);
signal cuentaMuyLento: STD_LOGIC_VECTOR(23 downto 0);
signal cuentaGasolina: STD_LOGIC_VECTOR(30 downto 0);
signal finCuentaMuyRapido,finCuentaRapido,finCuentaLento,finCuentaMuyLento,finCuentaGasolina: STD_LOGIC;
signal cuentaContBarrido: std_logic_vector(14 downto 0);
signal finCuentaBarrido,enableContBarrido,hayColision: std_logic;
signal finGenerarMundo: std_logic;
signal ModoSilo: std_logic;
--seniales memorias
signal DOAmundoMenosSig,DOAmundoMasSig,DOBmundoMenosSig,DOBmundoMasSig: std_logic_vector(0 downto 0);
signal selPixelPantalla: std_logic_vector (14 downto 0); -- pixeles logicos hor (120) concatenado con pixeles logicos ver (153): cuentaPixelCont(10 downto 3)++cuentaLineCont(8 downto 2)
signal selPixelMundo: std_logic_vector (14 downto 0); --pixelMundoHor catenado pixelMundoVer
signal WEBmenosSig,WEBmasSig,senialWEB,senialWEA: std_logic;
signal DIB,DOBmundo,DOAmundo: std_logic_vector(0 downto 0);
signal senialADDRA: std_logic_vector(13 downto 0);
--señales de depuracion
signal st : std_logic_vector (2 downto 0);
begin
--entradas:
modoSilo <= modoSiloIN;
--------------------------- RAM ------------------------------------------------
selPixelMundo(14 downto 7) <= pixelMundoHor;
selPixelMundo(6 downto 0) <= pixelMundoVer;
selPixelPantalla(14 downto 7) <= cuentaPixelCont(10 downto 3);
selPixelPantalla(6 downto 0) <= cuentaLineCont(8 downto 2);
--http://www.xilinx.com/itp/xilinx10/books/docs/spartan3_hdl/spartan3_hdl.pdf
memMenosSignif: RAMB16_S1_S1
generic map(
WRITE_MODE_B => "READ_FIRST"
)
port map (
DOA => DOAmundoMenosSig, -- Port A 1-bit Data Output
DOB => DOBmundoMenosSig, -- Port B 2-bit Data Output
ADDRA => senialADDRA, -- Port A 14-bit Address Input
ADDRB => selPixelMundo(13 downto 0), -- Port B 14-bit Address Input
CLKA => clk, -- Port A Clock
CLKB => clk, -- Port B Clock
DIA => "0", -- Port A 1-bit Data Input
DIB => DIB, -- Port B 1-bit Data Input --pintamos azul
ENA => '1', -- Port A RAM Enable Input
ENB => '1', -- PortB RAM Enable Input
SSRA => '0', -- Port A Synchronous Set/Reset Input
SSRB => '0', -- Port B Synchronous Set/Reset Input
WEA => senialWEA, -- Port A Write Enable Input
WEB => WEBmenosSig -- Port B Write Enable Input
);
memMasSignif: RAMB16_S1_S1
generic map(
WRITE_MODE_B => "READ_FIRST"
)
port map (
DOA => DOAmundoMasSig, -- Port A 1-bit Data Output
DOB => DOBmundoMasSig, -- Port B 1-bit Data Output
ADDRA => senialADDRA, -- Port A 14-bit Address Input
ADDRB => selPixelMundo(13 downto 0), -- Port B 14-bit Address Input
CLKA => clk, -- Port A Clock
CLKB => clk, -- Port B Clock
DIA => "0", -- Port A 1-bit Data Input
DIB => DIB, -- Port B 1-bit Data Input --pintamos azul
ENA => '1', -- Port A RAM Enable Input
ENB => '1', -- PortB RAM Enable Input
SSRA => '0', -- Port A Synchronous Set/Reset Input
SSRB => '0', -- Port B Synchronous Set/Reset Input
WEA => senialWEA, -- Port A Write Enable Input
WEB => WEBmasSig -- Port B Write Enable Input
);
interfazPS2: ps2KeyboardInterface port map (
rst => reset,
clk => clk,
ps2Clk => ps2Clk,
ps2Data => ps2Data,
data => scancode,
newData => newData,
newDataAck => newDataAck
);
--multiplexores
WEBmenosSig <= senialWEB when (selPixelMundo(14) = '0') else '0';
WEBmasSig <= senialWEB when (selPixelMundo(14) = '1') else '0';
DOBmundo <= DOBmundoMenosSig when (selPixelMundo(14) = '0') else DOBmundoMasSig;
DOAmundo <= DOAmundoMenosSig when (selPixelPantalla(14) = '0') else DOAmundoMasSig;
senialADDRA <= selPixelPantalla(13 downto 0) when (enableContBarrido = '0') else cuentaContBarrido(13 downto 0);
----------------------- PANTALLA -----------------------------------------------
hSync <= senialHSync;
vSync <= senialVSync;
pantalla: process(clk, reset,cuentaPixelCont,cuentaLineCont,Rnave,Rmundo,Gnave,Gmundo,
Bnave,Bmundo,Rbase,Gbase,Bbase,Rvel,Gvel,Bvel,Rfuego,Gfuego,Bfuego,
Rfuel,Gfuel,Bfuel,Rboom,Gboom,Bboom,teclaW,cuentaMuyLento,teclaA,teclaD)
begin
--cont mod 1589 (pixelCont para sincronismo horizontal)
if (cuentaPixelCont = "11000110100") then
finPixelCont <= '1';
else
finPixelCont <= '0';
end if;
if(reset = '0')then
cuentaPixelCont <= (others => '0');
finPixelCont <= '0';
elsif(clk'event and clk = '1') then
if (cuentaPixelCont /= "11000110100") then --1588
cuentaPixelCont <= cuentaPixelCont + '1';
elsif (cuentaPixelCont = "11000110100") then
cuentaPixelCont <= (others => '0');
end if;
end if;
--cont mod 528 (lineCont para sincronismo vertical)
if(reset = '0')then
cuentaLineCont <= (others => '0');
elsif(clk'event and clk = '1') then
if (finPixelCont = '1' and cuentaLineCont /= "1000001111") then --527
cuentaLineCont <= cuentaLineCont + '1';
elsif (finPixelCont = '1' and cuentaLineCont = "1000001111") then
cuentaLineCont <= (others => '0');
end if;
end if;
--comparaciones para pintar dentro de los limites
if (cuentaPixelCont > 1257) then comp1 <= '1'; else comp1 <= '0'; end if;
if (cuentaPixelCont > 1304) then comp2 <= '1'; else comp2 <= '0'; end if;
if (cuentaPixelCont <= 1493) then comp3 <= '1'; else comp3 <= '0'; end if;
if (cuentaLineCont > 479) then comp4 <= '1'; else comp4 <= '0'; end if;
if (cuentaLineCont > 493) then comp5 <= '1'; else comp5 <= '0'; end if;
if (cuentaLineCont <= 495) then comp6 <= '1'; else comp6 <= '0'; end if;
senialHSync <= comp2 nand comp3;
senialVSync <= comp5 nand comp6;
if (senialHSync = '0' or senialVSync = '0') then --no pinta
R <= "000";
G <= "000";
B <= "000";
else --pintamos lo que tengamos que pintar
R(2) <= ( (not (comp1 or comp4)) and (Rnave(2) or Rmundo(2) or Rbase(2) or Rvel(2) or Rfuego(2) or Rfuel(2) or Rboom(2)) );
R(1) <= ( (not (comp1 or comp4)) and (Rnave(1) or Rmundo(1) or Rbase(1) or Rvel(1) or Rfuego(1) or Rfuel(1) or Rboom(1)) );
R(0) <= ( (not (comp1 or comp4)) and (Rnave(0) or Rmundo(0) or Rbase(0) or Rvel(0) or Rfuego(0) or Rfuel(0) or Rboom(0)) );
G(2) <= ( (not (comp1 or comp4)) and (Gnave(2) or Gmundo(2) or Gbase(2) or Gvel(2) or Gfuego(2) or Gfuel(2) or Gboom(2)) );
G(1) <= ( (not (comp1 or comp4)) and (Gnave(1) or Gmundo(1) or Gbase(1) or Gvel(1) or Gfuego(1) or Gfuel(1) or Gboom(1)) );
G(0) <= ( (not (comp1 or comp4)) and (Gnave(0) or Gmundo(0) or Gbase(0) or Gvel(0) or Gfuego(0) or Gfuel(0) or Gboom(0)) );
B(2) <= ( (not (comp1 or comp4)) and (Bnave(2) or Bmundo(2) or Bbase(2) or Bvel(2) or Bfuego(2) or Bfuel(2) or Bboom(2)) );
B(1) <= ( (not (comp1 or comp4)) and (Bnave(1) or Bmundo(1) or Bbase(1) or Bvel(1) or Bfuego(1) or Bfuel(1) or Bboom(1)) );
B(0) <= ( (not (comp1 or comp4)) and (Bnave(0) or Bmundo(0) or Bbase(0) or Bvel(0) or Bfuego(0) or Bfuel(0) or Bboom(0)) );
end if;
end process;
------------------ PINTAR JUEGO ------------------------------------------------
-- vertical: 479 limite de pixeles visibles
-- 120 pixeles -> 479 x= (479*1)/120 = 3.99 = aprox 4
-- 1 pixeles -> x
-- horizontal: 1257 limite de pixeles visibles
-- 153 pixeles -> 1257 x= (1257*1)/153 = 8.21 = aprox 8
-- 1 pixeles -> x
pintarNave: process(cuentaLineCont,cuentaPixelCont,pixelNaveVer,pixelNaveHor)
begin
-- inicializacion
Rnave <= "000";
Gnave <= "000";
Bnave <= "000";
--pintar
if ( (cuentaLineCont(9 downto 2) = pixelNaveVer-3 or cuentaLineCont(9 downto 2) = pixelNaveVer-1)
and (cuentaPixelCont(10 downto 3) = pixelNaveHor) ) then
Rnave <= "000";
Gnave <= "110";
Bnave <= "000";
end if;
if ((cuentaLineCont(9 downto 2) = pixelNaveVer-2)
and (cuentaPixelCont(10 downto 3) = pixelNaveHor)) then
Rnave <= "000";
Gnave <= "000";
Bnave <= "110";
end if;
if (((cuentaLineCont(9 downto 2) = pixelNaveVer) or (cuentaLineCont(9 downto 2) = pixelNaveVer-2))
and (cuentaPixelCont(10 downto 3) = pixelNaveHor-1 )) then
Rnave <= "000";
Gnave <= "110";
Bnave <= "000";
end if;
if (((cuentaLineCont(9 downto 2) = pixelNaveVer) or (cuentaLineCont(9 downto 2) = pixelNaveVer-2))
and (cuentaPixelCont(10 downto 3) = pixelNaveHor+1 )) then
Rnave <= "000";
Gnave <= "110";
Bnave <= "000";
end if;
end process pintarNave;
pintarFuego: process(cuentaLineCont,cuentaPixelCont,pixelNaveVer,pixelNaveHor,
teclaW,cuentaMuyLento,teclaA,teclaD,cuentaGasolina,moverNave)
begin
-- inicializacion
Rfuego <= "000";
Gfuego <= "000";
Bfuego <= "000";
if (cuentaGasolina(30 downto 24) /= "0000000" and moverNave = '1') then
if (teclaW = '1' and cuentaMuyLento(20 downto 20) = "1") then
--pintar amarillo:abajo
if ( cuentaLineCont(9 downto 2) = pixelNaveVer and cuentaPixelCont(10 downto 3) = pixelNaveHor) then
Rfuego <= "111";
Gfuego <= "111";
Bfuego <= "000";
end if;
--pintar amarillo:abajo
if (cuentaLineCont(9 downto 2) = pixelNaveVer+1 and cuentaPixelCont(10 downto 3) = pixelNaveHor) then
Rfuego <= "111";
Gfuego <= "111";
Bfuego <= "000";
end if;
--pintar rojo:abajo
if (((cuentaLineCont(9 downto 2) = pixelNaveVer+1))
and ((cuentaPixelCont(10 downto 3) = pixelNaveHor+1 ) or (cuentaPixelCont(10 downto 3) = pixelNaveHor-1 ))) then
Rfuego <= "111";
Gfuego <= "000";
Bfuego <= "000";
end if;
if (cuentaLineCont(9 downto 2) = pixelNaveVer+2 and cuentaPixelCont(10 downto 3) = pixelNaveHor) then
Rfuego <= "111";
Gfuego <= "000";
Bfuego <= "000";
end if;
end if;
--pintar fuego lateral a la derecha (voy a la izquierda), he apretado izq
if (teclaA = '1' and cuentaMuyLento(20 downto 20) = "1") then
if (cuentaLineCont(9 downto 2) = pixelNaveVer-2 and cuentaPixelCont(10 downto 3) = pixelNaveHor+2) then
Rfuego <= "111";
Gfuego <= "000";
Bfuego <= "000";
end if;
end if;
--pintar fuego lateral a la izquierda (voy a la derecha) he apretado der
if (teclaD = '1' and cuentaMuyLento(20 downto 20) = "1") then
if (cuentaLineCont(9 downto 2) = pixelNaveVer-2 and cuentaPixelCont(10 downto 3) = pixelNaveHor-2) then
Rfuego <= "111";
Gfuego <= "000";
Bfuego <= "000";
end if;
end if;
end if;
end process pintarFuego;
pintarMundo: process(DOAmundo)
begin
-- inicializacion
Rmundo <= "000";
Gmundo <= "000";
Bmundo <= "000";
--pintar
if (DOAmundo = "1") then
Rmundo <= "011";
Gmundo <= "011";
Bmundo <= "011";
end if;
end process pintarMundo;
pintarBases: process(cuentaLineCont,cuentaPixelCont,DOAmundo,regBaseDificil1,
regBaseDificil2,regBaseFacil,modoSilo)
begin
-- inicializacion
Rbase <= "000";
Gbase <= "000";
Bbase <= "000";
--pintar baseDificil1
if (DOAmundo = "1" and
(cuentaPixelCont(10 downto 3) >= regBaseDificil1 and
cuentaPixelCont(10 downto 3) <= regBaseDificil1 +4) ) then
if (modoSilo = '1') then
Rbase <= "000";
Gbase <= "000";
Bbase <= "100";
else
--pintar lineas
if ( cuentaLineCont(9 downto 2) <= 105 and
(cuentaPixelCont(10 downto 3) = regBaseDificil1 or
cuentaPixelCont(10 downto 3) = regBaseDificil1 + 4) )then
Rbase <= "111";
Gbase <= "111";
Bbase <= "111";
end if;
--F de fuel
if ( cuentaLineCont(9 downto 2) >= 110 and cuentaLineCont(9 downto 2) <= 113 and
cuentaPixelCont(10 downto 3) = regBaseDificil1 +1) then
Rbase <= "111";
Gbase <= "111";
Bbase <= "111";
end if;
if ( (cuentaLineCont(9 downto 2) = 110 or cuentaLineCont(9 downto 2) = 112) and
cuentaPixelCont(10 downto 3) = regBaseDificil1 + 2) then
Rbase <= "111";
Gbase <= "111";
Bbase <= "111";
end if;
end if;
end if;
--pintar baseDificil2
if (DOAmundo = "1" and
(cuentaPixelCont(10 downto 3) >= regBaseDificil2 and
cuentaPixelCont(10 downto 3) <= regBaseDificil2 +4) ) then
if (modoSilo = '1') then
Rbase <= "000";
Gbase <= "000";
Bbase <= "100";
else
--pintar lineas
if ( cuentaLineCont(9 downto 2) <= 105 and
(cuentaPixelCont(10 downto 3) = regBaseDificil2 or
cuentaPixelCont(10 downto 3) = regBaseDificil2 + 4) )then
Rbase <= "111";
Gbase <= "111";
Bbase <= "111";
end if;
--F de fuel
if ( cuentaLineCont(9 downto 2) >= 110 and cuentaLineCont(9 downto 2) <= 113 and
cuentaPixelCont(10 downto 3) = regBaseDificil2 +1) then
Rbase <= "111";
Gbase <= "111";
Bbase <= "111";
end if;
if ( (cuentaLineCont(9 downto 2) = 110 or cuentaLineCont(9 downto 2) = 112) and
cuentaPixelCont(10 downto 3) = regBaseDificil2 + 2) then
Rbase <= "111";
Gbase <= "111";
Bbase <= "111";
end if;
end if;
end if;
--pintar base facil
if (DOAmundo = "1" and
(cuentaPixelCont(10 downto 3) >= regBaseFacil and
cuentaPixelCont(10 downto 3) <= regBaseFacil +8) ) then
if (modoSilo = '1') then
Rbase <= "100";
Gbase <= "000";
Bbase <= "000";
else
--pintar lineas
if ( cuentaLineCont(9 downto 2) <= 105 and
(cuentaPixelCont(10 downto 3) = regBaseFacil or
cuentaPixelCont(10 downto 3) = regBaseFacil + 8) )then
Rbase <= "111";
Gbase <= "111";
Bbase <= "111";
end if;
--F de fuel
if ( cuentaLineCont(9 downto 2) >= 110 and cuentaLineCont(9 downto 2) <= 113 and
cuentaPixelCont(10 downto 3) = regBaseFacil + 3) then
Rbase <= "111";
Gbase <= "111";
Bbase <= "111";
end if;
if ( (cuentaLineCont(9 downto 2) = 110 or cuentaLineCont(9 downto 2) = 112) and
cuentaPixelCont(10 downto 3) = regBaseFacil + 4) then
Rbase <= "111";
Gbase <= "111";
Bbase <= "111";
end if;
end if;
end if;
end process pintarBases;
pintarBoom: process(estadoJuego,cuentaLineCont,cuentaPixelCont)
begin
-- inicializacion
Rboom <= "000";
Gboom <= "000";
Bboom <= "000";
--pintar boom!
if (estadoJuego = parado) then
--pintar B
if ( (cuentaLineCont(9 downto 2) >= 36 and cuentaLineCont(9 downto 2) <= 40) and
(cuentaPixelCont(10 downto 3) = 66 or cuentaPixelCont(10 downto 3) = 68)) then
Rboom <= "111";
Gboom <= "111";
Bboom <= "111";
end if;
if ((cuentaLineCont(9 downto 2) = 36 or
cuentaLineCont(9 downto 2) = 38 or cuentaLineCont(9 downto 2) = 40 ) and
cuentaPixelCont(10 downto 3) = 67 ) then
Rboom <= "111";
Gboom <= "111";
Bboom <= "111";
end if;
--pintar primera O
if ( (cuentaLineCont(9 downto 2) >= 36 and cuentaLineCont(9 downto 2) <= 40) and
(cuentaPixelCont(10 downto 3) = 70 or cuentaPixelCont(10 downto 3) = 72)) then
Rboom <= "111";
Gboom <= "111";
Bboom <= "111";
end if;
if ( (cuentaLineCont(9 downto 2) = 36 or cuentaLineCont(9 downto 2) = 40) and
cuentaPixelCont(10 downto 3) = 71) then
Rboom <= "111";
Gboom <= "111";
Bboom <= "111";
end if;
--pintar segunda O
if ( (cuentaLineCont(9 downto 2) >= 36 and cuentaLineCont(9 downto 2) <= 40) and
(cuentaPixelCont(10 downto 3) = 74 or cuentaPixelCont(10 downto 3) = 76)) then
Rboom <= "111";
Gboom <= "111";
Bboom <= "111";
end if;
if ( (cuentaLineCont(9 downto 2) = 36 or cuentaLineCont(9 downto 2) = 40) and
cuentaPixelCont(10 downto 3) = 75) then
Rboom <= "111";
Gboom <= "111";
Bboom <= "111";
end if;
--pintar M
if ( (cuentaLineCont(9 downto 2) >= 36 and cuentaLineCont(9 downto 2) <= 40) and
(cuentaPixelCont(10 downto 3) = 78 or cuentaPixelCont(10 downto 3) = 82)) then
Rboom <= "111";
Gboom <= "111";
Bboom <= "111";
end if;
if ( (cuentaLineCont(9 downto 2) = 37) and
(cuentaPixelCont(10 downto 3) = 79 or cuentaPixelCont(10 downto 3) = 81)) then
Rboom <= "111";
Gboom <= "111";
Bboom <= "111";
end if;
if ( (cuentaLineCont(9 downto 2) = 38) and
cuentaPixelCont(10 downto 3) = 80) then
Rboom <= "111";
Gboom <= "111";
Bboom <= "111";
end if;
--pintar '!'
if ( ((cuentaLineCont(9 downto 2) >= 36 and cuentaLineCont(9 downto 2) <= 38) or
cuentaLineCont(9 downto 2) = 40 ) and
(cuentaPixelCont(10 downto 3) = 85)) then
Rboom <= "111";
Gboom <= "111";
Bboom <= "111";
end if;
end if;
end process pintarBoom;
Rvel(2) <= (R_ml(2) or R_l(2) or R_r(2) or R_mr(2));
Rvel(1) <= (R_ml(1) or R_l(1) or R_r(1) or R_mr(1));
Rvel(0) <= (R_ml(0) or R_l(0) or R_r(0) or R_mr(0));
Gvel(2) <= (G_ml(2) or G_l(2) or G_r(2) or G_mr(2));
Gvel(1) <= (G_ml(1) or G_l(1) or G_r(1) or G_mr(1));
Gvel(0) <= (G_ml(0) or G_l(0) or G_r(0) or G_mr(0));
Bvel(2) <= (B_ml(2) or B_l(2) or B_r(2) or B_mr(2));
Bvel(1) <= (B_ml(1) or B_l(1) or B_r(1) or B_mr(1));
Bvel(0) <= (B_ml(0) or B_l(0) or B_r(0) or B_mr(0));
pintarVelMuyLento: process(cuentaLineCont,cuentaPixelCont,cuentaVelVertical,cuentaVelHorizontal,
muyLentoVertical,lentoVertical,rapidoVertical,muyRapidoVertical,
muyLentoHorizontal,lentoHorizontal,rapidoHorizontal,muyRapidoHorizontal)
begin
-- inicializacion
R_ml <= "000";
G_ml <= "000";
B_ml <= "000";
--inicializar a gris:
if ((cuentaLineCont(9 downto 2) >= 4 and cuentaLineCont(9 downto 2) <= 6)
and (cuentaPixelCont(10 downto 3) >= 144 and cuentaPixelCont(10 downto 3) <= 146)) then
if ((cuentaLineCont(9 downto 2) /= 5) and (cuentaPixelCont(10 downto 3) /= 145)) then
R_ml <= "001";
G_ml <= "001";
B_ml <= "001";
end if;
end if;
if (cuentaVelHorizontal >= 0 and cuentaVelHorizontal < 64) then --hor izq
--pintar pixel muyLento
if (muyLentoHorizontal = '1' or lentoHorizontal = '1' or rapidoHorizontal = '1' or muyRapidoHorizontal = '1') then
if ((cuentaLineCont(9 downto 2) = 5) and (cuentaPixelCont(10 downto 3) = 144) ) then
R_ml <= "000";
G_ml <= "111";
B_ml <= "000";
end if;
end if;
else -- hor derecha
--pintar pixel muyLento
if (muyLentoHorizontal = '1' or lentoHorizontal = '1' or rapidoHorizontal = '1' or muyRapidoHorizontal = '1') then
if ((cuentaLineCont(9 downto 2) = 5) and (cuentaPixelCont(10 downto 3) = 146) ) then
R_ml <= "000";
G_ml <= "111";
B_ml <= "000";
end if;
end if;
end if;
if (cuentaVelVertical >= 0 and cuentaVelVertical < 64) then --ver subir
--pintar pixel muyLento
if (muyLentoVertical = '1' or lentoVertical = '1' or rapidoVertical = '1' or muyRapidoVertical = '1') then
if ((cuentaLineCont(9 downto 2) = 4) and (cuentaPixelCont(10 downto 3) = 145) ) then
R_ml <= "000";
G_ml <= "111";
B_ml <= "000";
end if;
end if;
else -- ver abajo
--pintar pixel muyLento
if (muyLentoVertical = '1' or lentoVertical = '1' or rapidoVertical = '1' or muyRapidoVertical = '1') then
if ((cuentaLineCont(9 downto 2) = 6) and (cuentaPixelCont(10 downto 3) = 145) ) then
R_ml <= "000";
G_ml <= "111";
B_ml <= "000";
end if;
end if;
end if;
end process pintarVelMuyLento;
pintarVelLento: process(cuentaLineCont,cuentaPixelCont,cuentaVelVertical,cuentaVelHorizontal,
muyLentoVertical,lentoVertical,rapidoVertical,muyRapidoVertical,
muyLentoHorizontal,lentoHorizontal,rapidoHorizontal,muyRapidoHorizontal)
begin
-- inicializacion
R_l <= "000";
G_l <= "000";
B_l <= "000";
--inicializar a gris:
if ((cuentaLineCont(9 downto 2) >= 3 and cuentaLineCont(9 downto 2) <= 7)
and (cuentaPixelCont(10 downto 3) >= 143 and cuentaPixelCont(10 downto 3) <= 147)) then
if ((cuentaLineCont(9 downto 2) /= 5) and (cuentaPixelCont(10 downto 3) /= 145)) then
R_l <= "011";
G_l <= "011";
B_l <= "011";
end if;
end if;
if (cuentaVelHorizontal >= 0 and cuentaVelHorizontal < 64) then --hor izq
--pintar pixel Lento
if (lentoHorizontal = '1' or rapidoHorizontal = '1' or muyRapidoHorizontal = '1') then
if ((cuentaLineCont(9 downto 2) = 5) and (cuentaPixelCont(10 downto 3) = 143) ) then
R_l <= "111";
G_l <= "111";
B_l <= "000";
end if;
end if;
else -- hor derecha
--pintar pixel Lento
if (lentoHorizontal = '1' or rapidoHorizontal = '1' or muyRapidoHorizontal = '1') then
if ((cuentaLineCont(9 downto 2) = 5) and (cuentaPixelCont(10 downto 3) = 147) ) then
R_l <= "111";
G_l <= "111";
B_l <= "000";
end if;
end if;
end if;
if (cuentaVelVertical >= 0 and cuentaVelVertical < 64) then --ver subir
--pintar pixel Lento
if (lentoVertical = '1' or rapidoVertical = '1' or muyRapidoVertical = '1') then
if ((cuentaLineCont(9 downto 2) = 3) and (cuentaPixelCont(10 downto 3) = 145) ) then
R_l <= "111";
G_l <= "111";
B_l <= "000";
end if;
end if;
else -- ver abajo
--pintar pixel Lento
if (lentoVertical = '1' or rapidoVertical = '1' or muyRapidoVertical = '1') then
if ((cuentaLineCont(9 downto 2) = 7) and (cuentaPixelCont(10 downto 3) = 145) ) then
R_l <= "111";
G_l <= "111";
B_l <= "000";
end if;
end if;
end if;
end process pintarVelLento;
pintarVelRapido: process(cuentaLineCont,cuentaPixelCont,cuentaVelVertical,cuentaVelHorizontal,
muyLentoVertical,lentoVertical,rapidoVertical,muyRapidoVertical,
muyLentoHorizontal,lentoHorizontal,rapidoHorizontal,muyRapidoHorizontal)
begin
-- inicializacion
R_r <= "000";
G_r <= "000";
B_r <= "000";
--inicializar a gris:
if ((cuentaLineCont(9 downto 2) >= 2 and cuentaLineCont(9 downto 2) <= 8)
and (cuentaPixelCont(10 downto 3) >= 142 and cuentaPixelCont(10 downto 3) <= 148)) then
if ((cuentaLineCont(9 downto 2) /= 5) and (cuentaPixelCont(10 downto 3) /= 145)) then
R_r <= "010";
G_r <= "010";
B_r <= "010";
end if;
end if;
if (cuentaVelHorizontal >= 0 and cuentaVelHorizontal < 64) then --hor izq
--pintar pixel
if (rapidoHorizontal = '1' or muyRapidoHorizontal = '1') then
if ((cuentaLineCont(9 downto 2) = 5) and (cuentaPixelCont(10 downto 3) = 142) ) then
R_r <= "111";
G_r <= "011";
B_r <= "000";
end if;
end if;
else -- hor derecha
--pintar pixel
if (rapidoHorizontal = '1' or muyRapidoHorizontal = '1') then
if ((cuentaLineCont(9 downto 2) = 5) and (cuentaPixelCont(10 downto 3) = 148) ) then
R_r <= "111";
G_r <= "011";
B_r <= "000";
end if;
end if;
end if;
if (cuentaVelVertical >= 0 and cuentaVelVertical < 64) then --ver subir
--pintar pixel
if (rapidoVertical = '1' or muyRapidoVertical = '1') then
if ((cuentaLineCont(9 downto 2) = 2) and (cuentaPixelCont(10 downto 3) = 145) ) then
R_r <= "111";
G_r <= "011";
B_r <= "000";
end if;
end if;
else -- ver abajo
--pintar pixel
if (rapidoVertical = '1' or muyRapidoVertical = '1') then
if ((cuentaLineCont(9 downto 2) = 8) and (cuentaPixelCont(10 downto 3) = 145) ) then
R_r <= "111";
G_r <= "011";
B_r <= "000";
end if;
end if;
end if;
end process pintarVelRapido;
pintarVelMuyRapido: process(cuentaLineCont,cuentaPixelCont,cuentaVelVertical,cuentaVelHorizontal,
muyLentoVertical,lentoVertical,rapidoVertical,muyRapidoVertical,
muyLentoHorizontal,lentoHorizontal,rapidoHorizontal,muyRapidoHorizontal)
begin
-- inicializacion
R_mr <= "000";
G_mr <= "000";
B_mr <= "000";
--inicializar a gris:
if ((cuentaLineCont(9 downto 2) >= 1 and cuentaLineCont(9 downto 2) <= 9)
and (cuentaPixelCont(10 downto 3) >= 141 and cuentaPixelCont(10 downto 3) <= 149)) then
if ((cuentaLineCont(9 downto 2) /= 5) and (cuentaPixelCont(10 downto 3) /= 145)) then
R_mr <= "000";
G_mr <= "000";
B_mr <= "000";
end if;
end if;
if (cuentaVelHorizontal >= 0 and cuentaVelHorizontal < 64) then --hor izq
--pintar pixel
if (muyRapidoHorizontal = '1') then
if ((cuentaLineCont(9 downto 2) = 5) and (cuentaPixelCont(10 downto 3) = 141) ) then
R_mr <= "111";
G_mr <= "000";
B_mr <= "000";
end if;
end if;
else -- hor derecha
--pintar pixel muyLento
if (muyRapidoHorizontal = '1') then
if ((cuentaLineCont(9 downto 2) = 5) and (cuentaPixelCont(10 downto 3) = 149) ) then
R_mr <= "111";
G_mr <= "000";
B_mr <= "000";
end if;
end if;
end if;
if (cuentaVelVertical >= 0 and cuentaVelVertical < 64) then --ver subir
--pintar pixel muyLento
if (muyRapidoVertical = '1') then
if ((cuentaLineCont(9 downto 2) = 1) and (cuentaPixelCont(10 downto 3) = 145) ) then
R_mr <= "111";
G_mr <= "000";
B_mr <= "000";
end if;
end if;
else -- ver abajo
--pintar pixel muyLento
if (muyRapidoVertical = '1') then
if ((cuentaLineCont(9 downto 2) = 9) and (cuentaPixelCont(10 downto 3) = 145) ) then
R_mr <= "111";
G_mr <= "000";
B_mr <= "000";
end if;
end if;
end if;
end process pintarVelMuyRapido;
pintarGasolina: process(cuentaLineCont,cuentaPixelCont,cuentaGasolina)
begin
-- inicializacion
Rfuel <= "000";
Gfuel <= "000";
Bfuel <= "000";
--linea gris:
if ( cuentaLineCont(9 downto 2) = 7 and
cuentaPixelCont(10 downto 3) >= 116 and cuentaPixelCont(10 downto 3) <= 127) then
Rfuel <= "111";
Gfuel <= "111";
Bfuel <= "111";
end if;
--F de fuel
if ( cuentaLineCont(9 downto 2) >= 4 and cuentaLineCont(9 downto 2) <= 7 and
cuentaPixelCont(10 downto 3) = 112) then
Rfuel <= "111";
Gfuel <= "111";
Bfuel <= "111";
end if;
if ( (cuentaLineCont(9 downto 2) = 4 or cuentaLineCont(9 downto 2) = 6) and
cuentaPixelCont(10 downto 3) = 113) then
Rfuel <= "111";
Gfuel <= "111";
Bfuel <= "111";
end if;
--lineas rojas
if ( cuentaLineCont(9 downto 2) >= 4 and cuentaLineCont(9 downto 2) <= 6 and
cuentaPixelCont(10 downto 3) = 116 and
(cuentaGasolina(30 downto 24) > "0000000" and cuentaGasolina(30 downto 24) <= "1110111")) then
Rfuel <= "111";
Gfuel <= "000";
Bfuel <= "000";
end if;
if ( cuentaLineCont(9 downto 2) >= 4 and cuentaLineCont(9 downto 2) <= 6 and
cuentaPixelCont(10 downto 3) = 117 and
(cuentaGasolina(30 downto 24) > "0001010" and cuentaGasolina(30 downto 24) <= "1110111")) then
Rfuel <= "111";
Gfuel <= "000";
Bfuel <= "000";
end if;
if ( cuentaLineCont(9 downto 2) >= 4 and cuentaLineCont(9 downto 2) <= 6 and
cuentaPixelCont(10 downto 3) = 118 and
(cuentaGasolina(30 downto 24) > "0010100" and cuentaGasolina(30 downto 24) <= "1110111")) then
Rfuel <= "111";
Gfuel <= "000";
Bfuel <= "000";
end if;
--lineas naranjas
if ( cuentaLineCont(9 downto 2) >= 4 and cuentaLineCont(9 downto 2) <= 6 and
cuentaPixelCont(10 downto 3) = 119 and
(cuentaGasolina(30 downto 24) > "0011110" and cuentaGasolina(30 downto 24) <= "1110111")) then
Rfuel <= "111";
Gfuel <= "011";
Bfuel <= "000";
end if;
if ( cuentaLineCont(9 downto 2) >= 4 and cuentaLineCont(9 downto 2) <= 6 and
cuentaPixelCont(10 downto 3) = 120 and
(cuentaGasolina(30 downto 24) > "0101000" and cuentaGasolina(30 downto 24) <= "1110111")) then
Rfuel <= "111";
Gfuel <= "011";
Bfuel <= "000";
end if;
if ( cuentaLineCont(9 downto 2) >= 4 and cuentaLineCont(9 downto 2) <= 6 and
cuentaPixelCont(10 downto 3) = 121 and
(cuentaGasolina(30 downto 24) > "0110010" and cuentaGasolina(30 downto 24) <= "1110111")) then
Rfuel <= "111";
Gfuel <= "011";
Bfuel <= "000";
end if;
--lineas amarillas
if ( cuentaLineCont(9 downto 2) >= 4 and cuentaLineCont(9 downto 2) <= 6 and
cuentaPixelCont(10 downto 3) = 122 and
(cuentaGasolina(30 downto 24) > "0111100" and cuentaGasolina(30 downto 24) <= "1110111")) then
Rfuel <= "111";
Gfuel <= "111";
Bfuel <= "000";
end if;
if ( cuentaLineCont(9 downto 2) >= 4 and cuentaLineCont(9 downto 2) <= 6 and
cuentaPixelCont(10 downto 3) = 123 and
(cuentaGasolina(30 downto 24) > "1000110" and cuentaGasolina(30 downto 24) <= "1110111")) then
Rfuel <= "111";
Gfuel <= "111";
Bfuel <= "000";
end if;
if ( cuentaLineCont(9 downto 2) >= 4 and cuentaLineCont(9 downto 2) <= 6 and
cuentaPixelCont(10 downto 3) = 124 and
(cuentaGasolina(30 downto 24) > "1010000" and cuentaGasolina(30 downto 24) <= "1110111")) then
Rfuel <= "111";
Gfuel <= "111";
Bfuel <= "000";
end if;
--lineas verdes
if ( cuentaLineCont(9 downto 2) >= 4 and cuentaLineCont(9 downto 2) <= 6 and
cuentaPixelCont(10 downto 3) = 125 and
(cuentaGasolina(30 downto 24) > "1011010" and cuentaGasolina(30 downto 24) <= "1110111")) then
Rfuel <= "000";
Gfuel <= "111";
Bfuel <= "000";
end if;
if ( cuentaLineCont(9 downto 2) >= 4 and cuentaLineCont(9 downto 2) <= 6 and
cuentaPixelCont(10 downto 3) = 126 and
(cuentaGasolina(30 downto 24) > "1100100" and cuentaGasolina(30 downto 24) <= "1110111")) then
Rfuel <= "000";
Gfuel <= "111";
Bfuel <= "000";
end if;
if ( cuentaLineCont(9 downto 2) >= 4 and cuentaLineCont(9 downto 2) <= 6 and
cuentaPixelCont(10 downto 3) = 127 and
(cuentaGasolina(30 downto 24) > "1101110" and cuentaGasolina(30 downto 24) <= "1110111") ) then
Rfuel <= "000";
Gfuel <= "111";
Bfuel <= "000";
end if;
end process pintarGasolina;
--#################### CONTROL JUEGO #########################################--
contadorMuyRapido: process(reset,clk,cuentaMuyRapido) --contador mod 2.000.000 (de 0 a 1.999.999)
begin
if (cuentaMuyRapido = "111101000010001111111") then
finCuentaMuyRapido <= '1';
else
finCuentaMuyRapido <= '0';
end if;
if(reset = '0')then
cuentaMuyRapido <= (others => '0');
finCuentaMuyRapido <= '0';
elsif(clk'event and clk = '1') then
if (cuentaMuyRapido /= "111101000010001111111") then
cuentaMuyRapido <= cuentaMuyRapido + 1;
elsif (cuentaMuyRapido = "111101000010001111111") then
cuentaMuyRapido <= (others => '0');
end if;
end if;
end process contadorMuyRapido;
contadorRapido: process(reset,clk,cuentaRapido) --contador mod 4.000.000 (de 0 a 3.999.999)
begin
if (cuentaRapido = "1111010000100011111111") then
finCuentaRapido <= '1';
else
finCuentaRapido <= '0';
end if;
if(reset = '0')then
cuentaRapido <= (others => '0');
finCuentaRapido <= '0';
elsif(clk'event and clk = '1') then
if (cuentaRapido /= "1111010000100011111111") then
cuentaRapido <= cuentaRapido + 1;
elsif (cuentaRapido = "1111010000100011111111") then
cuentaRapido <= (others => '0');
end if;
end if;
end process contadorRapido;
contadorLento: process(reset,clk,cuentaLento) --contador mod 8.000.000 (de 0 a 7.999.999)
begin
if (cuentaLento = "11110100001000111111111") then
finCuentaLento <= '1';
else
finCuentaLento <= '0';
end if;
if(reset = '0')then
cuentaLento <= (others => '0');
finCuentaLento <= '0';
elsif(clk'event and clk = '1') then
if (cuentaLento /= "11110100001000111111111") then
cuentaLento <= cuentaLento + 1;
elsif (cuentaLento = "11110100001000111111111") then
cuentaLento <= (others => '0');
end if;
end if;
end process contadorLento;
contadorMuyLento: process(reset,clk,cuentaMuyLento) --contador mod 16.000.000 (de 0 a 15.999.999)
begin
if (cuentaMuyLento = "11110100001000111111111111") then
finCuentaMuyLento <= '1';
else
finCuentaMuyLento <= '0';
end if;
if(reset = '0')then
cuentaMuyLento <= (others => '0');
finCuentaMuyLento <= '0';
elsif(clk'event and clk = '1') then
if (cuentaMuyLento /= "11110100001000111111111111") then
cuentaMuyLento <= cuentaMuyLento + 1;
elsif (cuentaMuyLento = "11110100001000111111111111") then
cuentaMuyLento <= (others => '0');
end if;
end if;
end process contadorMuyLento;
contadorGasolina: process(reset,clk,cuentaGasolina,teclaSPC,haAterrizado) --contador mod 32.000.000 (de 0 a 31.999.999)
begin
if (cuentaGasolina = "0000000000000000000000000000") then
finCuentaGasolina <= '1';
else
finCuentaGasolina <= '0';
end if;
if(reset = '0')then
cuentaGasolina <= "1111010000100011111111111111111";
finCuentaGasolina <= '0';
elsif(clk'event and clk = '1') then
if (cuentaGasolina /= "0000000000000000000000000000") then
cuentaGasolina <= cuentaGasolina - 1;
end if;
if (modoSilo = '0') then
if (haAterrizado = '1' and cuentaGasolina(30 downto 24) < "1101110") then --recarga gasolina
cuentaGasolina <= cuentaGasolina +20;
end if;
else
if (pixelNaveVer = "1110111" and cuentaGasolina(30 downto 24) < "1101110") then --recarga gasolina
cuentaGasolina <= cuentaGasolina +20;
end if;
end if;
if (teclaSPC = '1') then
cuentaGasolina <= "1111010000100011111111111111111";
end if;
end if;
end process contadorGasolina;
contVelVertical: process(reset,clk,cuentaVelVertical,finCuentaLento,teclaSPC,
movNave,moverNave) --contador mod
begin
-- de 0 a 63, sube (para subir hay que restar)
-- de 64 a 127, baja (para bajar hay que sumar)
if(reset = '0')then
cuentaVelVertical <= "1000110"; --70: cae a poca velocidad
elsif(clk'event and clk = '1') then
if (finCuentaLento = '1' ) then--and moverNave = '1') then
--127: con el bit mas sig, si es 0 el resto de bits seran la vel de caida; lo mismo para la de subida cuando bit mas sig igual 1
--hay gravedad:
if ((haAterrizado = '0' or hayColision = '0') and cuentaVelVertical <= "1111101") then
cuentaVelVertical <= cuentaVelVertical +2;
end if;
if (haAterrizado = '1') then
cuentaVelVertical <= "1000000"; --no tiene velocidad de caida
end if;
if (movNave = "001") then --nave hacia arriba
if (cuentaVelVertical >= "0000100") then --4
cuentaVelVertical <= cuentaVelVertical - 4;
end if;
if (haAterrizado = '1') then --hemos aterrizado, si encendemos motores despegamos fuerte
cuentaVelVertical <= "0001111";
end if;
end if;
end if;
end if;
--generacion de velocidad
muyLentoVertical <= '0';
lentoVertical <= '0';
rapidoVertical <= '0';
muyRapidoVertical <= '0';
if ((cuentaVelVertical >= 0 and cuentaVelVertical < 15) or --subiendo muy rapido
(cuentaVelVertical >= 109 and cuentaVelVertical <= 127)) then --bajando muy rapido
muyRapidoVertical <= '1';
elsif ((cuentaVelVertical >=15 and cuentaVelVertical < 30) or --subiendo rapido
(cuentaVelVertical >= 94 and cuentaVelVertical < 109)) then --bajando rapido
rapidoVertical <= '1';
elsif ((cuentaVelVertical >= 30 and cuentaVelVertical < 45) or --subiendo lento
(cuentaVelVertical >= 79 and cuentaVelVertical < 94)) then --bajando lento
lentoVertical <= '1';
elsif ((cuentaVelVertical >= 45 and cuentaVelVertical < 64) or --subiendo muy lento
(cuentaVelVertical >= 64 and cuentaVelVertical <= 79)) then --bajando muy lento
muyLentoVertical <= '1';
end if;
if (teclaSPC = '1') then
cuentaVelVertical <= "1000110"; --70: cae a poca velocidad
end if;
end process contVelVertical;
contVelHorizontal: process(reset,clk,cuentaVelHorizontal,finCuentaLento,teclaSPC,
movNave,moverNave) --contador mod
begin
-- de 0 a 63, izquierda (para ir izquierda hay que restar)
-- de 64 a 127, derecha (para ir derecha hay que sumar)
if(reset = '0')then
cuentaVelHorizontal <= "1000110"; --70: cae a poca velocidad
elsif(clk'event and clk = '1') then
if (finCuentaLento = '1' and moverNave = '1') then
--127: con el bit mas sig, si es 0 el resto de bits seran la vel de izquiera; lo mismo para la derecha cuando bit mas sig igual 1
--si usamos los motores, cambiamos la velocidad
if (movNave = "100") then --nave hacia derecha
if (cuentaVelHorizontal < "1111011") then --123
cuentaVelHorizontal <= cuentaVelHorizontal + 4;
end if;
end if;
if (movNave = "011") then --nave hacia la izquierda
if (cuentaVelHorizontal >= "0000100") then --4
cuentaVelHorizontal <= cuentaVelHorizontal - 4;
end if;
end if;
end if;
end if;
--generacion de velocidad
muyLentoHorizontal <= '0';
lentoHorizontal <= '0';
rapidoHorizontal <= '0';
muyRapidoHorizontal <= '0';
if ((cuentaVelHorizontal >= 0 and cuentaVelHorizontal < 15) or --izq muy rapido
(cuentaVelHorizontal >= 109 and cuentaVelHorizontal <= 127)) then --der muy rapido
muyRapidoHorizontal <= '1';
elsif ((cuentaVelHorizontal >=15 and cuentaVelHorizontal < 30) or --izq rapido
(cuentaVelHorizontal >= 94 and cuentaVelHorizontal < 109)) then --der rapido
rapidoHorizontal <= '1';
elsif ((cuentaVelHorizontal >= 30 and cuentaVelHorizontal < 45) or --izq lento
(cuentaVelHorizontal >= 79 and cuentaVelHorizontal < 94)) then --der lento
lentoHorizontal <= '1';
elsif ((cuentaVelHorizontal >= 45 and cuentaVelHorizontal < 64) or --izq muy lento
(cuentaVelHorizontal >= 64 and cuentaVelHorizontal <= 79)) then --der muy lento
muyLentoHorizontal <= '1';
end if;
if (teclaSPC = '1') then
cuentaVelHorizontal <= "1000110"; --70: cae a poca velocidad
end if;
end process contVelHorizontal;
nave: process(clk,reset,moverNave,finCuentaLento,pixelNaveHor,pixelNaveVer,movNave,
cuentaVelVertical,cuentaVelHorizontal,muyLentoHorizontal,
lentoHorizontal,rapidoHorizontal,muyRapidoHorizontal,muyLentoVertical,
lentoVertical,rapidoVertical,muyRapidoVertical)
begin
posNave(14 downto 7) <= pixelNaveHor;
posNave(6 downto 0) <= pixelNaveVer;
--vertical: cont mod 102 y horizontal: cont mod 153
if (reset = '0')then --pos inicial coche1
pixelNaveVer <= "0001000"; --en 9
pixelNaveHor <= "00000011"; --en 3
elsif (clk'event and clk = '1' and moverNave = '1') then
--movimiento de la nave vertical
if (cuentaVelVertical < "1000000") then --64 limite: va hacia arriba
if (pixelNaveVer >= "0000001") then
if (muyLentoVertical = '1') then
if (finCuentaMuyLento = '1') then
if (pixelNaveVer-1 /= "0000000") then pixelNaveVer <= pixelNaveVer - 1; end if;
end if;
elsif (lentoVertical = '1') then
if (finCuentaLento = '1') then
if (pixelNaveVer-1 /= "0000000") then pixelNaveVer <= pixelNaveVer - 1; end if;
end if;
elsif (rapidoVertical = '1') then
if (finCuentaRapido = '1') then
if (pixelNaveVer-1 /= "0000000") then pixelNaveVer <= pixelNaveVer - 1; end if;
end if;
elsif (muyRapidoVertical = '1') then
if (finCuentaMuyRapido = '1') then
if (pixelNaveVer-1 /= "0000000") then pixelNaveVer <= pixelNaveVer - 1; end if;
end if;
end if;
end if;
elsif (cuentaVelVertical >= "1000000") then --va hacia abajo
if (pixelNaveVer < "1110111") then
if (muyLentoVertical = '1') then
if (finCuentaMuyLento = '1') then
if (pixelNaveVer-1 /= "1110111") then pixelNaveVer <= pixelNaveVer + 1; end if;
end if;
elsif (lentoVertical = '1') then
if (finCuentaLento = '1') then
if (pixelNaveVer-1 /= "1110111") then pixelNaveVer <= pixelNaveVer + 1; end if;
end if;
elsif (rapidoVertical = '1') then
if (finCuentaRapido = '1') then
if (pixelNaveVer-1 /= "1110111") then pixelNaveVer <= pixelNaveVer + 1; end if;
end if;
elsif (muyRapidoVertical = '1') then
if (finCuentaMuyRapido = '1') then
if (pixelNaveVer-1 /= "1110111") then pixelNaveVer <= pixelNaveVer + 1; end if;
end if;
end if;
end if;
end if;
--movimiento de la nave horizontal
if (cuentaVelHorizontal <"1000000") then --va hacia la izq
if (muyLentoHorizontal = '1') then
if (finCuentaMuyLento = '1') then
if (pixelNaveHor-1 /= "00000000") then pixelNaveHor <= pixelNaveHor - 1; end if;
end if;
elsif (lentoHorizontal = '1') then
if (finCuentaLento = '1') then
if (pixelNaveHor-1 /= "00000000") then pixelNaveHor <= pixelNaveHor - 1; end if;
end if;
elsif (rapidoHorizontal = '1') then
if (finCuentaRapido = '1') then
if (pixelNaveHor-1 /= "00000000") then pixelNaveHor <= pixelNaveHor - 1; end if;
end if;
elsif (muyRapidoHorizontal = '1') then
if (finCuentaMuyRapido = '1') then
if (pixelNaveHor-1 /= "00000000") then pixelNaveHor <= pixelNaveHor - 1; end if;
end if;
end if;
elsif (cuentaVelHorizontal >= "1000000") then --va hacia la der
if (muyLentoHorizontal = '1') then
if (finCuentaMuyLento = '1') then
if (pixelNaveHor-1 /= "10011000") then pixelNaveHor <= pixelNaveHor + 1; end if;
end if;
elsif (lentoHorizontal = '1') then
if (finCuentaLento = '1') then
if (pixelNaveHor-1 /= "10011000") then pixelNaveHor <= pixelNaveHor + 1; end if;
end if;
elsif (rapidoHorizontal = '1') then
if (finCuentaRapido = '1') then
if (pixelNaveHor-1 /= "10011000") then pixelNaveHor <= pixelNaveHor + 1; end if;
end if;
elsif (muyRapidoHorizontal = '1') then
if (finCuentaMuyRapido = '1') then
if (pixelNaveHor-1 /= "10011000") then pixelNaveHor <= pixelNaveHor + 1; end if;
end if;
end if;
end if;
if (teclaSPC = '1') then
pixelNaveVer <= "0001000"; --en 9
pixelNaveHor <= "00000011"; --en 3
end if;
end if;
end process nave;
asigMovNave: process(teclaA,teclaW,teclaS,teclaD,cuentaGasolina)
begin
movNave <= "000";
if (cuentaGasolina(30 downto 24) /= "0000000") then --si queda gasolina, enciendes motores
if (teclaW = '1') then movNave <= "001"; end if;
if (teclaS = '1') then movNave <= "010"; end if;
if (teclaA = '1') then movNave <= "011"; end if;
if (teclaD = '1') then movNave <= "100"; end if;
end if;
end process asigMovNave;
generacionBases: process(clk,reset,Q,contMod3,generarBases,clContMod3,selPixelMundo,
selPixelPantalla)
begin
if (reset = '0') then
regBaseDificil1 <= "0000000";
regBaseDificil2 <= "0000000";
regBaseFacil <= "0000000";
contMod3 <= "00";
elsif (clk'event and clk = '1') then
if (generarBases = '1' and contMod3 /= "11") then
case contMod3 is
when "00" => regBaseDificil1 <= Q(6 downto 0); --7 bits porque 100="1100100". A la dir base de nuestras bases vamos a sumar un num aleatorio
when "01" => regBaseDificil2 <= Q(6 downto 0);
when "10" => regBaseFacil <= Q(6 downto 0);
when others => null;
end case;
contMod3 <= contMod3 + 1;
end if;
if (clContMod3 = '1') then
contMod3 <= "00";
end if;
end if;
end process generacionBases;
colision: process(DOAmundo,posNave,selPixelPantalla,pixelNaveHor,regBaseDificil1,
regBaseDificil2,regBaseFacil,muyRapidoVertical,modoSilo)
begin
hayColision <= '0';
BiestablehaAterrizado <= '0';
if ((DOAmundo = "1" and posNave = selPixelPantalla) and not
((pixelNaveHor >= regBaseDificil1 and pixelNaveHor < regBaseDificil1 +5) or --en baseDificil1
(pixelNaveHor >= regBaseDificil2 and pixelNaveHor < regBaseDificil2 +5) or --en baseDificil2
(pixelNaveHor >= regBaseFacil and pixelNaveHor < regBaseFacil +9) --en baseFacil
)) then
hayColision <= '1';
end if;
if ((DOAmundo = "1" and modoSilo = '0' and
(posNave(14 downto 7) = selPixelPantalla(14 downto 7)) and --posicion de la nave
(posNave(6 downto 0) = selPixelPantalla(6 downto 0))
) and
((pixelNaveHor >= regBaseDificil1 and pixelNaveHor < regBaseDificil1 +5) or --en baseDificil1
(pixelNaveHor >= regBaseDificil2 and pixelNaveHor < regBaseDificil2 +5) or --en baseDificil2
(pixelNaveHor >= regBaseFacil and pixelNaveHor < regBaseFacil +9) --en baseFacil
)) then --si estamos donde la base
if (muyRapidoVertical = '0') then --no voy muy rapido hacia abajo
BiestablehaAterrizado <= '1';
else
hayColision <= '1';
end if;
end if;
end process colision;
biestable_D_haAterrizado: process(reset,clk,BiestablehaAterrizado,movNave) --con este biestableD conseguimos que continue el juego si ha aterrizado
begin
if(reset = '0')then
haAterrizado <= '0';
elsif(clk'event and clk = '1' ) then
if (teclaSPC = '1') then
haAterrizado <= '0';
end if;
if (posNave = selPixelPantalla) then
haAterrizado <= BiestablehaAterrizado;
end if;
end if;
end process biestable_D_haAterrizado;
--maquina de estados de la generacion de mundo -------------------------------------------------
controladorFSMgeneracionMundo: process (clk, reset, estadoJuego, pixelMundoVer)
begin
if(reset = '0') then
estadoGenMundo <= generaAleatOBase;
elsif (clk'event and clk = '1' and estadoJuego = iniciando) then
estadoGenMundo <= generaAleatOBase; -- estado por defecto, puede ser sobreescrito luego
case estadoGenMundo is
when generaAleatOBase =>
estadoGenMundo <= guardaPixelVer;
when guardaPixelVer =>
estadoGenMundo <= pintarCol;
when pintarCol =>
estadoGenMundo <= pintarCol;
if (pixelMundoVer = "1111000") then --ver 120
estadoGenMundo <= generaAleatOBase;
end if;
end case;
end if;
end process controladorFSMgeneracionMundo;
generadorMealyFSMgeneracionMundo: process (clk,reset,pixelMundoHor,pixelMundoVer,regBaseDificil1,regBaseDificil2,
regBaseFacil,pixelAnteriorVer,Q,estadoGenMundo)
begin
pixelMundoVer <= pixelMundoVer;
pixelMundoHor <= pixelMundoHor;
pixelAnteriorVer <= pixelAnteriorVer;
if (reset = '0') then
pixelMundoVer <= "1011010"; --90
pixelAnteriorVer <= "1011010"; --90
pixelMundoHor <= "00000000";
finGenerarMundo <= '0';
elsif (clk'event and clk = '1') then
case estadoGenMundo is
when generaAleatOBase =>
finGenerarMundo <= '0';
--si es base
if ((pixelMundoHor >= regBaseDificil1 and pixelMundoHor < regBaseDificil1 +5) or
(pixelMundoHor >= regBaseDificil2 and pixelMundoHor < regBaseDificil2 +5) or
(pixelMundoHor >= regBaseFacil and pixelMundoHor < regBaseFacil +9 ) ) then
pixelAnteriorVer <= pixelAnteriorVer;
--no es base
--sube y baja aleatoriamente dependiendo de unos valores fijados
-- 0 <= Q <= 32767 (num de pixeles fisicos) 1/4 = 8191 2/4 = 16383 3/4 = 24573
elsif (Q>=0 and Q <= 8191) then
pixelAnteriorVer <= pixelAnteriorVer - 2;
if (pixelAnteriorVer <= "0100111") then pixelAnteriorVer <= "0100111"; end if; --0100111=pixel logico 39 (el mundo no podrá subir más alla del tercio de la pantalla, para que entre la nave)
elsif (Q>8191 and Q <= 16383) then
pixelAnteriorVer <= pixelAnteriorVer - 1;
if (pixelAnteriorVer <= "0100111") then pixelAnteriorVer <= "0100111"; end if; --0100111=pixel logico 39
elsif (Q>16383 and Q <= 24573) then
pixelAnteriorVer <= pixelAnteriorVer + 2;
if (pixelAnteriorVer >= "1101110") then pixelAnteriorVer <= "1101110"; end if; --1101110=pixel logico 110 (el mundo no podrá bajar más alla del pixel 110 de la pantalla, para que se vea)
elsif (Q>24573 and Q <= 32767) then
pixelAnteriorVer <= pixelAnteriorVer + 1;
if (pixelAnteriorVer >= "1101110") then pixelAnteriorVer <= "1101110"; end if; --1101110=pixel logico 110
end if;
when guardaPixelVer =>
pixelMundoVer <= pixelAnteriorVer;
when pintarCol =>
if (pixelMundoVer /= "1111000") then --ver 120: si es distinto me pintas la columna
pixelMundoVer <= pixelMundoVer + 1;
elsif (pixelMundoVer = "1111000" and pixelMundoHor /= "10011001") then --ver 120 / hor 153: pasar a siguiente columna
pixelMundoHor <= pixelMundoHor + 1;
elsif (pixelMundoVer = "1111000" and pixelMundoHor = "10011001") then --ver 120 / hor 153: acabo de generar mundo, reinicio tambien para la sig vez
finGenerarMundo <= '1';
pixelMundoVer <= "1011010"; --90
pixelAnteriorVer <= "1011010"; --90
pixelMundoHor <= "00000000";
end if;
when others =>
pixelMundoHor <= pixelMundoHor;
pixelMundoVer <= pixelMundoVer;
pixelAnteriorVer <= pixelAnteriorVer;
end case;
end if;
end process generadorMealyFSMgeneracionMundo;
--------------------------------------------------------------------------------
--maquina de estados con registros de flags para el teclado---------------------
controladorFSMteclado: process (clk, reset, newData, scancode)
begin
if(reset = '0') then
estadoTeclado <= pulsadas;
elsif (clk'event and clk = '1') then
estadoTeclado <= pulsadas; -- estado por defecto, puede ser sobreescrito luego
case estadoTeclado is
when pulsadas =>
estadoTeclado <= pulsadas;
if (newData = '1' and scancode = "11110000") then --11110000: F0
estadoTeclado <= despulsadas;
end if;
when despulsadas =>
estadoTeclado <= despulsadas;
if (newData = '1') then
estadoTeclado <= pulsadas;
end if;
end case;
end if;
end process controladorFSMteclado;
generadorMealyFSMteclado: process (newDataAck, scancode, estadoTeclado, newData)
begin
newDataAck <= '0';
clTeclaW <= '0';
clTeclaS <= '0';
clTeclaA <= '0';
clTeclaD <= '0';
clTeclaSPC <= '0';
ldTeclaW <= '0';
ldTeclaS <= '0';
ldTeclaA <= '0';
ldTeclaD <= '0';
ldTeclaSPC <= '0';
case estadoTeclado is
when pulsadas =>
if (newData = '1') then --11110000: F0
case scancode is --registros de flags:
when "00011101" => ldTeclaW <= '1'; clTeclaW <= '0'; --W=1D
when "00011011" => ldTeclaS <= '1'; clTeclaS <= '0'; --S=1B
when "00011100" => ldTeclaA <= '1'; clTeclaA <= '0'; --A=1C
when "00100011" => ldTeclaD <= '1'; clTeclaD <= '0'; --D=23
when "00101001" => ldTeclaSPC <= '1'; clTeclaSPC <= '0'; --SPC=29
when others => null;
end case;
newDataAck <= '1';
end if;
when despulsadas =>
if (newData = '1') then
case scancode is --registros de flags:
when "00011101" => ldTeclaW <= '0'; clTeclaW <= '1'; --W=1D
when "00011011" => ldTeclaS <= '0'; clTeclaS <= '1'; --S=1B
when "00011100" => ldTeclaA <= '0'; clTeclaA <= '1'; --A=1C
when "00100011" => ldTeclaD <= '0'; clTeclaD <= '1'; --D=23
when "00101001" => ldTeclaSPC <= '0'; clTeclaSPC <= '1'; --SPC=29
when others => null;
end case;
newDataAck <= '1';
end if;
when others => null;
end case;
end process generadorMealyFSMteclado;
biestableDteclaSPC: process(reset,clk,ldTeclaSPC,clTeclaSPC)
begin
if(reset = '0')then
teclaSPC <= '0';
elsif(clk'event and clk = '1' ) then
if (clTeclaSPC = '1') then
teclaSPC <= '0';
elsif (ldTeclaSPC = '1') then
teclaSPC <= '1';
end if;
end if;
end process biestableDteclaSPC;
biestableDteclaW: process(reset,clk,ldTeclaW,clTeclaW)
begin
if(reset = '0')then
teclaW <= '0';
elsif(clk'event and clk = '1' ) then
if (clTeclaW = '1') then
teclaW <= '0';
elsif (ldTeclaW = '1') then
teclaW <= '1';
end if;
end if;
end process biestableDteclaW;
biestableDteclaS: process(reset,clk,ldTeclaS,clTeclaS)
begin
if(reset = '0')then
teclaS <= '0';
elsif(clk'event and clk = '1' ) then
if (clTeclaS = '1') then
teclaS <= '0';
elsif (ldTeclaS = '1') then
teclaS <= '1';
end if;
end if;
end process biestableDteclaS;
biestableDteclaA: process(reset,clk,ldTeclaA,clTeclaA)
begin
if(reset = '0')then
teclaA <= '0';
elsif(clk'event and clk = '1' ) then
if (clTeclaA = '1') then
teclaA <= '0';
elsif (ldTeclaA = '1') then
teclaA <= '1';
end if;
end if;
end process biestableDteclaA;
biestableDteclaD: process(reset,clk,ldTeclaD,clTeclaD)
begin
if(reset = '0')then
teclaD <= '0';
elsif(clk'event and clk = '1' ) then
if (clTeclaD = '1') then
teclaD <= '0';
elsif (ldTeclaD = '1') then
teclaD <= '1';
end if;
end if;
end process biestableDteclaD;
--maquina de estados del juego -------------------------------------------------
controladorFSMjuego: process (clk, reset, finGenerarMundo, finCuentaBarrido,
hayColision, teclaSPC)
begin
if(reset = '0') then
estadoJuego <= iniciando;
elsif (clk'event and clk = '1') then
estadoJuego <= iniciando; -- estado por defecto, puede ser sobreescrito luego
case estadoJuego is
when iniciando =>
estadoJuego <= iniciando;
if (finGenerarMundo = '1') then
estadoJuego <= jugando;
end if;
when jugando =>
estadoJuego <= jugando;
if (hayColision = '1') then
estadoJuego <= parado;
end if;
if (teclaSPC = '1') then
estadoJuego <= reseteo;
end if;
when parado =>
estadoJuego <= parado;
if (teclaSPC = '1') then
estadoJuego <= reseteo;
end if;
when reseteo =>
estadoJuego <= reseteo;
if (finCuentaBarrido = '1') then
estadoJuego <= iniciando;
end if;
end case;
end if;
end process controladorFSMjuego;
generadorMooreJuego: process (estadoJuego)
begin
--memorias
senialWEA <= '0';
senialWEB <= '0';
DIB <= "1";
enableContBarrido <= '0';
--juego:generar
clContMod3 <= '1';
generarBases <= '0';
--juego:estado
moverNave <= '0';
st <= "000";
case estadoJuego is
when iniciando =>
-- escribo por puerto B
--memorias
senialWEA <= '0';
senialWEB <= '1';
DIB <= "1";
enableContBarrido <= '0';
--juego:generar
clContMod3 <= '0';
generarBases <= '1';
--juego:estado
moverNave <= '0';
st <= "000";
when jugando =>
-- leo por puerto A, escribo por puerto B
--memorias
senialWEA <= '0';
senialWEB <= '0';
DIB <= "0";
enableContBarrido <= '0';--resetea contBarrido
--juego:generar
clContMod3 <= '0';
generarBases <= '0';
--juego:estado
moverNave <= '1';
st <= "001";
when parado =>
--memorias
senialWEA <= '0';
senialWEB <= '0';
DIB <= "0";
enableContBarrido <= '0'; --resetea contBarrido
--juego:generar
clContMod3 <= '0'; --no se toca, se necesitan los reg para calcular colisiones
generarBases <= '0';
--juego:estado
moverNave <= '0';
st <= "010";
when reseteo =>
-- reseteo por puerto A
--memorias
senialWEA <= '1';
senialWEB <= '0';
DIB <= "0";
enableContBarrido <= '1';
--juego:generar
clContMod3 <= '1'; --para que en iniciando se vuelvan a generar las bases
generarBases <= '0';
--juego:estado
moverNave <= '0';
st <= "011";
when others => null;
end case;
end process generadorMooreJuego;
conversor7seg: process(st)
begin
case st is
--gfedcba
when "000" => segs <= "0111111";
when "001" => segs <= "0000110";
when "010" => segs <= "1011011";
when "011" => segs <= "1001111";
when OTHERS => segs <= "1111001"; -- error
end case;
end process;
--------------------------------------------------------------------------------
--contador para limpiar la ram
contBarrido: process(reset,clk,cuentaContBarrido,enableContBarrido) --contador mod 2^15=32768 (120 x 153 pixeles)
begin
if (cuentaContBarrido = "111111111111111") then --32768 "111111111111111") then --70000 10001000101110000
finCuentaBarrido <= '1';
else
finCuentaBarrido <= '0';
end if;
if(reset = '0')then
cuentaContBarrido <= (others => '0');
finCuentaBarrido <= '0';
elsif(clk'event and clk = '1') then
if(enableContBarrido = '1') then
if (cuentaContBarrido /= "111111111111111") then --32768 "111111111111111") then
cuentaContBarrido <= cuentaContBarrido + 1;
end if;
elsif (enableContBarrido = '0') then
cuentaContBarrido <= (others => '0');
end if;
end if;
end process contBarrido;
--------------------------------------------------------------------------------
-- lsfr para la generacion aleatoria
lsfr: process(reset,clk,D,Q)
begin
--conexiones entre biestables
D(14 downto 1) <= Q(13 downto 0); --D(X) es Q(X-1)
--entrada de D1
puertaAND <= (Q(14 downto 14) and Q(13 downto 13) and Q(12 downto 12) and
Q(11 downto 11) and Q(10 downto 10) and Q(9 downto 9) and
Q(8 downto 8) and Q(7 downto 7) and Q(6 downto 6) and
Q(5 downto 5) and Q(4 downto 4) and Q(3 downto 3) and
Q(2 downto 2) and Q(1 downto 1) and Q(0 downto 0));
D(0 downto 0) <= ( (not (Q(14 downto 14) xor Q(13 downto 13)))
xor (puertaAND or puertaAND) );
if(reset = '0')then
Q(14 downto 0) <= (others => '0');
elsif(clk'event and clk = '1' ) then
Q <= D;
end if;
end process lsfr;
end Behavioral;
| gpl-3.0 |
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`protect end_protected
| gpl-3.0 |
DougFirErickson/parallella-hw | fpga/ip/xilinx/fifo_async_103x32/fifo_generator_v12_0/hdl/builtin/builtin_extdepth_low_latency.vhd | 6 | 43742 | `protect begin_protected
`protect version = 1
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`protect key_block
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`protect key_block
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`protect key_block
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| gpl-3.0 |
DougFirErickson/parallella-hw | fpga/ip/xilinx/axi_bram_ctrl_16b/axi_bram_ctrl_v4_0/hdl/vhdl/xor18.vhd | 7 | 8446 | -------------------------------------------------------------------------------
-- xor18.vhd
-------------------------------------------------------------------------------
--
--
-- (c) Copyright [2010 - 2013] Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--
------------------------------------------------------------------------------
-- Filename: xor18.vhd
--
-- Description: Basic 18-bit input XOR function.
--
-- VHDL-Standard: VHDL'93
--
-------------------------------------------------------------------------------
-- Structure:
-- axi_bram_ctrl.vhd (v1_03_a)
-- |
-- |-- full_axi.vhd
-- | -- sng_port_arb.vhd
-- | -- lite_ecc_reg.vhd
-- | -- axi_lite_if.vhd
-- | -- wr_chnl.vhd
-- | -- wrap_brst.vhd
-- | -- ua_narrow.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- checkbit_handler_64.vhd
-- | -- (same helper components as checkbit_handler)
-- | -- parity.vhd
-- | -- correct_one_bit.vhd
-- | -- correct_one_bit_64.vhd
-- |
-- | -- rd_chnl.vhd
-- | -- wrap_brst.vhd
-- | -- ua_narrow.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- checkbit_handler_64.vhd
-- | -- (same helper components as checkbit_handler)
-- | -- parity.vhd
-- | -- correct_one_bit.vhd
-- | -- correct_one_bit_64.vhd
-- |
-- |-- axi_lite.vhd
-- | -- lite_ecc_reg.vhd
-- | -- axi_lite_if.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- checkbit_handler_64.vhd
-- | -- (same helper components as checkbit_handler)
-- | -- correct_one_bit.vhd
-- | -- correct_one_bit_64.vhd
--
--
--
-------------------------------------------------------------------------------
--
-- History:
--
-- ^^^^^^
-- JLJ 2/2/2011 v1.03a
-- ~~~~~~
-- Migrate to v1.03a.
-- Plus minor code cleanup.
-- ^^^^^^
-- JLJ 3/17/2011 v1.03a
-- ~~~~~~
-- Add default on C_USE_LUT6 parameter.
-- ^^^^^^
--
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;
entity XOR18 is
generic (
C_USE_LUT6 : boolean := FALSE );
port (
InA : in std_logic_vector(0 to 17);
res : out std_logic);
end entity XOR18;
architecture IMP of XOR18 is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of IMP : architecture is "yes";
begin -- architecture IMP
Using_LUT6: if (C_USE_LUT6) generate
signal xor6_1 : std_logic;
signal xor6_2 : std_logic;
signal xor6_3 : std_logic;
signal xor18_c1 : std_logic;
signal xor18_c2 : std_logic;
begin -- generate Using_LUT6
XOR6_1_LUT : LUT6
generic map(
INIT => X"6996966996696996")
port map(
O => xor6_1,
I0 => InA(17),
I1 => InA(16),
I2 => InA(15),
I3 => InA(14),
I4 => InA(13),
I5 => InA(12));
XOR_1st_MUXCY : MUXCY_L
port map (
DI => '1',
CI => '0',
S => xor6_1,
LO => xor18_c1);
XOR6_2_LUT : LUT6
generic map(
INIT => X"6996966996696996")
port map(
O => xor6_2,
I0 => InA(11),
I1 => InA(10),
I2 => InA(9),
I3 => InA(8),
I4 => InA(7),
I5 => InA(6));
XOR_2nd_MUXCY : MUXCY_L
port map (
DI => xor6_1,
CI => xor18_c1,
S => xor6_2,
LO => xor18_c2);
XOR6_3_LUT : LUT6
generic map(
INIT => X"6996966996696996")
port map(
O => xor6_3,
I0 => InA(5),
I1 => InA(4),
I2 => InA(3),
I3 => InA(2),
I4 => InA(1),
I5 => InA(0));
XOR18_XORCY : XORCY
port map (
LI => xor6_3,
CI => xor18_c2,
O => res);
end generate Using_LUT6;
Not_Using_LUT6: if (not C_USE_LUT6) generate
begin -- generate Not_Using_LUT6
res <= InA(17) xor InA(16) xor InA(15) xor InA(14) xor InA(13) xor InA(12) xor
InA(11) xor InA(10) xor InA(9) xor InA(8) xor InA(7) xor InA(6) xor
InA(5) xor InA(4) xor InA(3) xor InA(2) xor InA(1) xor InA(0);
end generate Not_Using_LUT6;
end architecture IMP;
| gpl-3.0 |
DougFirErickson/parallella-hw | fpga/ip/xilinx/fifo_async_103x16/blk_mem_gen_v8_2/hdl/blk_mem_gen_v8_2_synth.vhd | 8 | 79859 | `protect begin_protected
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`protect end_protected
| gpl-3.0 |
DougFirErickson/parallella-hw | fpga/ip/xilinx/fifo_async_103x16/fifo_generator_v12_0/hdl/ramfifo/rd_fwft.vhd | 6 | 38466 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 26736)
`protect data_block
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`protect end_protected
| gpl-3.0 |
DougFirErickson/parallella-hw | fpga/ip/xilinx/fifo_async_103x16/synth/fifo_async_103x16.vhd | 2 | 38595 | -- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:fifo_generator:12.0
-- IP Revision: 2
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY fifo_generator_v12_0;
USE fifo_generator_v12_0.fifo_generator_v12_0;
ENTITY fifo_async_103x16 IS
PORT (
rst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(102 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(102 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
prog_full : OUT STD_LOGIC
);
END fifo_async_103x16;
ARCHITECTURE fifo_async_103x16_arch OF fifo_async_103x16 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF fifo_async_103x16_arch: ARCHITECTURE IS "yes";
COMPONENT fifo_generator_v12_0 IS
GENERIC (
C_COMMON_CLOCK : INTEGER;
C_COUNT_TYPE : INTEGER;
C_DATA_COUNT_WIDTH : INTEGER;
C_DEFAULT_VALUE : STRING;
C_DIN_WIDTH : INTEGER;
C_DOUT_RST_VAL : STRING;
C_DOUT_WIDTH : INTEGER;
C_ENABLE_RLOCS : INTEGER;
C_FAMILY : STRING;
C_FULL_FLAGS_RST_VAL : INTEGER;
C_HAS_ALMOST_EMPTY : INTEGER;
C_HAS_ALMOST_FULL : INTEGER;
C_HAS_BACKUP : INTEGER;
C_HAS_DATA_COUNT : INTEGER;
C_HAS_INT_CLK : INTEGER;
C_HAS_MEMINIT_FILE : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_RD_DATA_COUNT : INTEGER;
C_HAS_RD_RST : INTEGER;
C_HAS_RST : INTEGER;
C_HAS_SRST : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_VALID : INTEGER;
C_HAS_WR_ACK : INTEGER;
C_HAS_WR_DATA_COUNT : INTEGER;
C_HAS_WR_RST : INTEGER;
C_IMPLEMENTATION_TYPE : INTEGER;
C_INIT_WR_PNTR_VAL : INTEGER;
C_MEMORY_TYPE : INTEGER;
C_MIF_FILE_NAME : STRING;
C_OPTIMIZATION_MODE : INTEGER;
C_OVERFLOW_LOW : INTEGER;
C_PRELOAD_LATENCY : INTEGER;
C_PRELOAD_REGS : INTEGER;
C_PRIM_FIFO_TYPE : STRING;
C_PROG_EMPTY_THRESH_ASSERT_VAL : INTEGER;
C_PROG_EMPTY_THRESH_NEGATE_VAL : INTEGER;
C_PROG_EMPTY_TYPE : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL : INTEGER;
C_PROG_FULL_THRESH_NEGATE_VAL : INTEGER;
C_PROG_FULL_TYPE : INTEGER;
C_RD_DATA_COUNT_WIDTH : INTEGER;
C_RD_DEPTH : INTEGER;
C_RD_FREQ : INTEGER;
C_RD_PNTR_WIDTH : INTEGER;
C_UNDERFLOW_LOW : INTEGER;
C_USE_DOUT_RST : INTEGER;
C_USE_ECC : INTEGER;
C_USE_EMBEDDED_REG : INTEGER;
C_USE_PIPELINE_REG : INTEGER;
C_POWER_SAVING_MODE : INTEGER;
C_USE_FIFO16_FLAGS : INTEGER;
C_USE_FWFT_DATA_COUNT : INTEGER;
C_VALID_LOW : INTEGER;
C_WR_ACK_LOW : INTEGER;
C_WR_DATA_COUNT_WIDTH : INTEGER;
C_WR_DEPTH : INTEGER;
C_WR_FREQ : INTEGER;
C_WR_PNTR_WIDTH : INTEGER;
C_WR_RESPONSE_LATENCY : INTEGER;
C_MSGON_VAL : INTEGER;
C_ENABLE_RST_SYNC : INTEGER;
C_ERROR_INJECTION_TYPE : INTEGER;
C_SYNCHRONIZER_STAGE : INTEGER;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_HAS_AXI_WR_CHANNEL : INTEGER;
C_HAS_AXI_RD_CHANNEL : INTEGER;
C_HAS_SLAVE_CE : INTEGER;
C_HAS_MASTER_CE : INTEGER;
C_ADD_NGC_CONSTRAINT : INTEGER;
C_USE_COMMON_OVERFLOW : INTEGER;
C_USE_COMMON_UNDERFLOW : INTEGER;
C_USE_DEFAULT_SETTINGS : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_AXI_ADDR_WIDTH : INTEGER;
C_AXI_DATA_WIDTH : INTEGER;
C_AXI_LEN_WIDTH : INTEGER;
C_AXI_LOCK_WIDTH : INTEGER;
C_HAS_AXI_ID : INTEGER;
C_HAS_AXI_AWUSER : INTEGER;
C_HAS_AXI_WUSER : INTEGER;
C_HAS_AXI_BUSER : INTEGER;
C_HAS_AXI_ARUSER : INTEGER;
C_HAS_AXI_RUSER : INTEGER;
C_AXI_ARUSER_WIDTH : INTEGER;
C_AXI_AWUSER_WIDTH : INTEGER;
C_AXI_WUSER_WIDTH : INTEGER;
C_AXI_BUSER_WIDTH : INTEGER;
C_AXI_RUSER_WIDTH : INTEGER;
C_HAS_AXIS_TDATA : INTEGER;
C_HAS_AXIS_TID : INTEGER;
C_HAS_AXIS_TDEST : INTEGER;
C_HAS_AXIS_TUSER : INTEGER;
C_HAS_AXIS_TREADY : INTEGER;
C_HAS_AXIS_TLAST : INTEGER;
C_HAS_AXIS_TSTRB : INTEGER;
C_HAS_AXIS_TKEEP : INTEGER;
C_AXIS_TDATA_WIDTH : INTEGER;
C_AXIS_TID_WIDTH : INTEGER;
C_AXIS_TDEST_WIDTH : INTEGER;
C_AXIS_TUSER_WIDTH : INTEGER;
C_AXIS_TSTRB_WIDTH : INTEGER;
C_AXIS_TKEEP_WIDTH : INTEGER;
C_WACH_TYPE : INTEGER;
C_WDCH_TYPE : INTEGER;
C_WRCH_TYPE : INTEGER;
C_RACH_TYPE : INTEGER;
C_RDCH_TYPE : INTEGER;
C_AXIS_TYPE : INTEGER;
C_IMPLEMENTATION_TYPE_WACH : INTEGER;
C_IMPLEMENTATION_TYPE_WDCH : INTEGER;
C_IMPLEMENTATION_TYPE_WRCH : INTEGER;
C_IMPLEMENTATION_TYPE_RACH : INTEGER;
C_IMPLEMENTATION_TYPE_RDCH : INTEGER;
C_IMPLEMENTATION_TYPE_AXIS : INTEGER;
C_APPLICATION_TYPE_WACH : INTEGER;
C_APPLICATION_TYPE_WDCH : INTEGER;
C_APPLICATION_TYPE_WRCH : INTEGER;
C_APPLICATION_TYPE_RACH : INTEGER;
C_APPLICATION_TYPE_RDCH : INTEGER;
C_APPLICATION_TYPE_AXIS : INTEGER;
C_PRIM_FIFO_TYPE_WACH : STRING;
C_PRIM_FIFO_TYPE_WDCH : STRING;
C_PRIM_FIFO_TYPE_WRCH : STRING;
C_PRIM_FIFO_TYPE_RACH : STRING;
C_PRIM_FIFO_TYPE_RDCH : STRING;
C_PRIM_FIFO_TYPE_AXIS : STRING;
C_USE_ECC_WACH : INTEGER;
C_USE_ECC_WDCH : INTEGER;
C_USE_ECC_WRCH : INTEGER;
C_USE_ECC_RACH : INTEGER;
C_USE_ECC_RDCH : INTEGER;
C_USE_ECC_AXIS : INTEGER;
C_ERROR_INJECTION_TYPE_WACH : INTEGER;
C_ERROR_INJECTION_TYPE_WDCH : INTEGER;
C_ERROR_INJECTION_TYPE_WRCH : INTEGER;
C_ERROR_INJECTION_TYPE_RACH : INTEGER;
C_ERROR_INJECTION_TYPE_RDCH : INTEGER;
C_ERROR_INJECTION_TYPE_AXIS : INTEGER;
C_DIN_WIDTH_WACH : INTEGER;
C_DIN_WIDTH_WDCH : INTEGER;
C_DIN_WIDTH_WRCH : INTEGER;
C_DIN_WIDTH_RACH : INTEGER;
C_DIN_WIDTH_RDCH : INTEGER;
C_DIN_WIDTH_AXIS : INTEGER;
C_WR_DEPTH_WACH : INTEGER;
C_WR_DEPTH_WDCH : INTEGER;
C_WR_DEPTH_WRCH : INTEGER;
C_WR_DEPTH_RACH : INTEGER;
C_WR_DEPTH_RDCH : INTEGER;
C_WR_DEPTH_AXIS : INTEGER;
C_WR_PNTR_WIDTH_WACH : INTEGER;
C_WR_PNTR_WIDTH_WDCH : INTEGER;
C_WR_PNTR_WIDTH_WRCH : INTEGER;
C_WR_PNTR_WIDTH_RACH : INTEGER;
C_WR_PNTR_WIDTH_RDCH : INTEGER;
C_WR_PNTR_WIDTH_AXIS : INTEGER;
C_HAS_DATA_COUNTS_WACH : INTEGER;
C_HAS_DATA_COUNTS_WDCH : INTEGER;
C_HAS_DATA_COUNTS_WRCH : INTEGER;
C_HAS_DATA_COUNTS_RACH : INTEGER;
C_HAS_DATA_COUNTS_RDCH : INTEGER;
C_HAS_DATA_COUNTS_AXIS : INTEGER;
C_HAS_PROG_FLAGS_WACH : INTEGER;
C_HAS_PROG_FLAGS_WDCH : INTEGER;
C_HAS_PROG_FLAGS_WRCH : INTEGER;
C_HAS_PROG_FLAGS_RACH : INTEGER;
C_HAS_PROG_FLAGS_RDCH : INTEGER;
C_HAS_PROG_FLAGS_AXIS : INTEGER;
C_PROG_FULL_TYPE_WACH : INTEGER;
C_PROG_FULL_TYPE_WDCH : INTEGER;
C_PROG_FULL_TYPE_WRCH : INTEGER;
C_PROG_FULL_TYPE_RACH : INTEGER;
C_PROG_FULL_TYPE_RDCH : INTEGER;
C_PROG_FULL_TYPE_AXIS : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WACH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_RACH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : INTEGER;
C_PROG_EMPTY_TYPE_WACH : INTEGER;
C_PROG_EMPTY_TYPE_WDCH : INTEGER;
C_PROG_EMPTY_TYPE_WRCH : INTEGER;
C_PROG_EMPTY_TYPE_RACH : INTEGER;
C_PROG_EMPTY_TYPE_RDCH : INTEGER;
C_PROG_EMPTY_TYPE_AXIS : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : INTEGER;
C_REG_SLICE_MODE_WACH : INTEGER;
C_REG_SLICE_MODE_WDCH : INTEGER;
C_REG_SLICE_MODE_WRCH : INTEGER;
C_REG_SLICE_MODE_RACH : INTEGER;
C_REG_SLICE_MODE_RDCH : INTEGER;
C_REG_SLICE_MODE_AXIS : INTEGER
);
PORT (
backup : IN STD_LOGIC;
backup_marker : IN STD_LOGIC;
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
srst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
wr_rst : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
rd_rst : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(102 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
prog_empty_thresh_assert : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
prog_empty_thresh_negate : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
prog_full_thresh_assert : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
prog_full_thresh_negate : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
int_clk : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
injectsbiterr : IN STD_LOGIC;
sleep : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(102 DOWNTO 0);
full : OUT STD_LOGIC;
almost_full : OUT STD_LOGIC;
wr_ack : OUT STD_LOGIC;
overflow : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
almost_empty : OUT STD_LOGIC;
valid : OUT STD_LOGIC;
underflow : OUT STD_LOGIC;
data_count : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
rd_data_count : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
wr_data_count : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
prog_full : OUT STD_LOGIC;
prog_empty : OUT STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
wr_rst_busy : OUT STD_LOGIC;
rd_rst_busy : OUT STD_LOGIC;
m_aclk : IN STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
m_aclk_en : IN STD_LOGIC;
s_aclk_en : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awlock : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awregion : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_buser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
m_axi_awid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_awlock : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_awqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awvalid : OUT STD_LOGIC;
m_axi_awready : IN STD_LOGIC;
m_axi_wid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_wdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axi_wstrb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_wlast : OUT STD_LOGIC;
m_axi_wuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_wvalid : OUT STD_LOGIC;
m_axi_wready : IN STD_LOGIC;
m_axi_bid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_buser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_bvalid : IN STD_LOGIC;
m_axi_bready : OUT STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arlock : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arregion : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_aruser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_ruser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
m_axi_arid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_arlock : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_arqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_arregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_aruser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_arvalid : OUT STD_LOGIC;
m_axi_arready : IN STD_LOGIC;
m_axi_rid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_rdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axi_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_rlast : IN STD_LOGIC;
m_axi_ruser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_rvalid : IN STD_LOGIC;
m_axi_rready : OUT STD_LOGIC;
s_axis_tvalid : IN STD_LOGIC;
s_axis_tready : OUT STD_LOGIC;
s_axis_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_tstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tkeep : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tlast : IN STD_LOGIC;
s_axis_tid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tdest : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tuser : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_tvalid : OUT STD_LOGIC;
m_axis_tready : IN STD_LOGIC;
m_axis_tdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_tstrb : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tkeep : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tlast : OUT STD_LOGIC;
m_axis_tid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tdest : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_injectsbiterr : IN STD_LOGIC;
axi_aw_injectdbiterr : IN STD_LOGIC;
axi_aw_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_sbiterr : OUT STD_LOGIC;
axi_aw_dbiterr : OUT STD_LOGIC;
axi_aw_overflow : OUT STD_LOGIC;
axi_aw_underflow : OUT STD_LOGIC;
axi_aw_prog_full : OUT STD_LOGIC;
axi_aw_prog_empty : OUT STD_LOGIC;
axi_w_injectsbiterr : IN STD_LOGIC;
axi_w_injectdbiterr : IN STD_LOGIC;
axi_w_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_w_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_w_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_sbiterr : OUT STD_LOGIC;
axi_w_dbiterr : OUT STD_LOGIC;
axi_w_overflow : OUT STD_LOGIC;
axi_w_underflow : OUT STD_LOGIC;
axi_w_prog_full : OUT STD_LOGIC;
axi_w_prog_empty : OUT STD_LOGIC;
axi_b_injectsbiterr : IN STD_LOGIC;
axi_b_injectdbiterr : IN STD_LOGIC;
axi_b_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_b_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_b_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_sbiterr : OUT STD_LOGIC;
axi_b_dbiterr : OUT STD_LOGIC;
axi_b_overflow : OUT STD_LOGIC;
axi_b_underflow : OUT STD_LOGIC;
axi_b_prog_full : OUT STD_LOGIC;
axi_b_prog_empty : OUT STD_LOGIC;
axi_ar_injectsbiterr : IN STD_LOGIC;
axi_ar_injectdbiterr : IN STD_LOGIC;
axi_ar_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_ar_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_ar_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_sbiterr : OUT STD_LOGIC;
axi_ar_dbiterr : OUT STD_LOGIC;
axi_ar_overflow : OUT STD_LOGIC;
axi_ar_underflow : OUT STD_LOGIC;
axi_ar_prog_full : OUT STD_LOGIC;
axi_ar_prog_empty : OUT STD_LOGIC;
axi_r_injectsbiterr : IN STD_LOGIC;
axi_r_injectdbiterr : IN STD_LOGIC;
axi_r_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_r_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_r_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_sbiterr : OUT STD_LOGIC;
axi_r_dbiterr : OUT STD_LOGIC;
axi_r_overflow : OUT STD_LOGIC;
axi_r_underflow : OUT STD_LOGIC;
axi_r_prog_full : OUT STD_LOGIC;
axi_r_prog_empty : OUT STD_LOGIC;
axis_injectsbiterr : IN STD_LOGIC;
axis_injectdbiterr : IN STD_LOGIC;
axis_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axis_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axis_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_sbiterr : OUT STD_LOGIC;
axis_dbiterr : OUT STD_LOGIC;
axis_overflow : OUT STD_LOGIC;
axis_underflow : OUT STD_LOGIC;
axis_prog_full : OUT STD_LOGIC;
axis_prog_empty : OUT STD_LOGIC
);
END COMPONENT fifo_generator_v12_0;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF fifo_async_103x16_arch: ARCHITECTURE IS "fifo_generator_v12_0,Vivado 2014.3.1";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF fifo_async_103x16_arch : ARCHITECTURE IS "fifo_async_103x16,fifo_generator_v12_0,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF fifo_async_103x16_arch: ARCHITECTURE IS "fifo_async_103x16,fifo_generator_v12_0,{x_ipProduct=Vivado 2014.3.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=fifo_generator,x_ipVersion=12.0,x_ipCoreRevision=2,x_ipLanguage=VERILOG,C_COMMON_CLOCK=0,C_COUNT_TYPE=0,C_DATA_COUNT_WIDTH=4,C_DEFAULT_VALUE=BlankString,C_DIN_WIDTH=103,C_DOUT_RST_VAL=0,C_DOUT_WIDTH=103,C_ENABLE_RLOCS=0,C_FAMILY=zynq,C_FULL_FLAGS_RST_VAL=1,C_HAS_ALMOST_EMPTY=0,C_HAS_ALMOST_FULL=0,C_HAS_BACKUP=0,C_HAS_DATA_COUNT=0,C_HAS_INT_CLK=0,C_HAS_MEMINIT_FILE=0,C_HAS_OVERFLOW=0,C_HAS_RD_DATA_COUNT=0,C_HAS_RD_RST=0,C_HAS_RST=1,C_HAS_SRST=0,C_HAS_UNDERFLOW=0,C_HAS_VALID=0,C_HAS_WR_ACK=0,C_HAS_WR_DATA_COUNT=0,C_HAS_WR_RST=0,C_IMPLEMENTATION_TYPE=2,C_INIT_WR_PNTR_VAL=0,C_MEMORY_TYPE=2,C_MIF_FILE_NAME=BlankString,C_OPTIMIZATION_MODE=0,C_OVERFLOW_LOW=0,C_PRELOAD_LATENCY=0,C_PRELOAD_REGS=1,C_PRIM_FIFO_TYPE=512x72,C_PROG_EMPTY_THRESH_ASSERT_VAL=4,C_PROG_EMPTY_THRESH_NEGATE_VAL=5,C_PROG_EMPTY_TYPE=0,C_PROG_FULL_THRESH_ASSERT_VAL=12,C_PROG_FULL_THRESH_NEGATE_VAL=11,C_PROG_FULL_TYPE=1,C_RD_DATA_COUNT_WIDTH=4,C_RD_DEPTH=16,C_RD_FREQ=1,C_RD_PNTR_WIDTH=4,C_UNDERFLOW_LOW=0,C_USE_DOUT_RST=1,C_USE_ECC=0,C_USE_EMBEDDED_REG=0,C_USE_PIPELINE_REG=0,C_POWER_SAVING_MODE=0,C_USE_FIFO16_FLAGS=0,C_USE_FWFT_DATA_COUNT=0,C_VALID_LOW=0,C_WR_ACK_LOW=0,C_WR_DATA_COUNT_WIDTH=4,C_WR_DEPTH=16,C_WR_FREQ=1,C_WR_PNTR_WIDTH=4,C_WR_RESPONSE_LATENCY=1,C_MSGON_VAL=1,C_ENABLE_RST_SYNC=1,C_ERROR_INJECTION_TYPE=0,C_SYNCHRONIZER_STAGE=2,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_HAS_AXI_WR_CHANNEL=1,C_HAS_AXI_RD_CHANNEL=1,C_HAS_SLAVE_CE=0,C_HAS_MASTER_CE=0,C_ADD_NGC_CONSTRAINT=0,C_USE_COMMON_OVERFLOW=0,C_USE_COMMON_UNDERFLOW=0,C_USE_DEFAULT_SETTINGS=0,C_AXI_ID_WIDTH=1,C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=64,C_AXI_LEN_WIDTH=8,C_AXI_LOCK_WIDTH=1,C_HAS_AXI_ID=0,C_HAS_AXI_AWUSER=0,C_HAS_AXI_WUSER=0,C_HAS_AXI_BUSER=0,C_HAS_AXI_ARUSER=0,C_HAS_AXI_RUSER=0,C_AXI_ARUSER_WIDTH=1,C_AXI_AWUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_AXI_RUSER_WIDTH=1,C_HAS_AXIS_TDATA=1,C_HAS_AXIS_TID=0,C_HAS_AXIS_TDEST=0,C_HAS_AXIS_TUSER=1,C_HAS_AXIS_TREADY=1,C_HAS_AXIS_TLAST=0,C_HAS_AXIS_TSTRB=0,C_HAS_AXIS_TKEEP=0,C_AXIS_TDATA_WIDTH=8,C_AXIS_TID_WIDTH=1,C_AXIS_TDEST_WIDTH=1,C_AXIS_TUSER_WIDTH=4,C_AXIS_TSTRB_WIDTH=1,C_AXIS_TKEEP_WIDTH=1,C_WACH_TYPE=0,C_WDCH_TYPE=0,C_WRCH_TYPE=0,C_RACH_TYPE=0,C_RDCH_TYPE=0,C_AXIS_TYPE=0,C_IMPLEMENTATION_TYPE_WACH=1,C_IMPLEMENTATION_TYPE_WDCH=1,C_IMPLEMENTATION_TYPE_WRCH=1,C_IMPLEMENTATION_TYPE_RACH=1,C_IMPLEMENTATION_TYPE_RDCH=1,C_IMPLEMENTATION_TYPE_AXIS=1,C_APPLICATION_TYPE_WACH=0,C_APPLICATION_TYPE_WDCH=0,C_APPLICATION_TYPE_WRCH=0,C_APPLICATION_TYPE_RACH=0,C_APPLICATION_TYPE_RDCH=0,C_APPLICATION_TYPE_AXIS=0,C_PRIM_FIFO_TYPE_WACH=512x36,C_PRIM_FIFO_TYPE_WDCH=1kx36,C_PRIM_FIFO_TYPE_WRCH=512x36,C_PRIM_FIFO_TYPE_RACH=512x36,C_PRIM_FIFO_TYPE_RDCH=1kx36,C_PRIM_FIFO_TYPE_AXIS=1kx18,C_USE_ECC_WACH=0,C_USE_ECC_WDCH=0,C_USE_ECC_WRCH=0,C_USE_ECC_RACH=0,C_USE_ECC_RDCH=0,C_USE_ECC_AXIS=0,C_ERROR_INJECTION_TYPE_WACH=0,C_ERROR_INJECTION_TYPE_WDCH=0,C_ERROR_INJECTION_TYPE_WRCH=0,C_ERROR_INJECTION_TYPE_RACH=0,C_ERROR_INJECTION_TYPE_RDCH=0,C_ERROR_INJECTION_TYPE_AXIS=0,C_DIN_WIDTH_WACH=32,C_DIN_WIDTH_WDCH=64,C_DIN_WIDTH_WRCH=2,C_DIN_WIDTH_RACH=32,C_DIN_WIDTH_RDCH=64,C_DIN_WIDTH_AXIS=1,C_WR_DEPTH_WACH=16,C_WR_DEPTH_WDCH=1024,C_WR_DEPTH_WRCH=16,C_WR_DEPTH_RACH=16,C_WR_DEPTH_RDCH=1024,C_WR_DEPTH_AXIS=1024,C_WR_PNTR_WIDTH_WACH=4,C_WR_PNTR_WIDTH_WDCH=10,C_WR_PNTR_WIDTH_WRCH=4,C_WR_PNTR_WIDTH_RACH=4,C_WR_PNTR_WIDTH_RDCH=10,C_WR_PNTR_WIDTH_AXIS=10,C_HAS_DATA_COUNTS_WACH=0,C_HAS_DATA_COUNTS_WDCH=0,C_HAS_DATA_COUNTS_WRCH=0,C_HAS_DATA_COUNTS_RACH=0,C_HAS_DATA_COUNTS_RDCH=0,C_HAS_DATA_COUNTS_AXIS=0,C_HAS_PROG_FLAGS_WACH=0,C_HAS_PROG_FLAGS_WDCH=0,C_HAS_PROG_FLAGS_WRCH=0,C_HAS_PROG_FLAGS_RACH=0,C_HAS_PROG_FLAGS_RDCH=0,C_HAS_PROG_FLAGS_AXIS=0,C_PROG_FULL_TYPE_WACH=0,C_PROG_FULL_TYPE_WDCH=0,C_PROG_FULL_TYPE_WRCH=0,C_PROG_FULL_TYPE_RACH=0,C_PROG_FULL_TYPE_RDCH=0,C_PROG_FULL_TYPE_AXIS=0,C_PROG_FULL_THRESH_ASSERT_VAL_WACH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WRCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RACH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_AXIS=1023,C_PROG_EMPTY_TYPE_WACH=0,C_PROG_EMPTY_TYPE_WDCH=0,C_PROG_EMPTY_TYPE_WRCH=0,C_PROG_EMPTY_TYPE_RACH=0,C_PROG_EMPTY_TYPE_RDCH=0,C_PROG_EMPTY_TYPE_AXIS=0,C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS=1022,C_REG_SLICE_MODE_WACH=0,C_REG_SLICE_MODE_WDCH=0,C_REG_SLICE_MODE_WRCH=0,C_REG_SLICE_MODE_RACH=0,C_REG_SLICE_MODE_RDCH=0,C_REG_SLICE_MODE_AXIS=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF din: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_DATA";
ATTRIBUTE X_INTERFACE_INFO OF wr_en: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_EN";
ATTRIBUTE X_INTERFACE_INFO OF rd_en: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_EN";
ATTRIBUTE X_INTERFACE_INFO OF dout: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_DATA";
ATTRIBUTE X_INTERFACE_INFO OF full: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE FULL";
ATTRIBUTE X_INTERFACE_INFO OF empty: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ EMPTY";
BEGIN
U0 : fifo_generator_v12_0
GENERIC MAP (
C_COMMON_CLOCK => 0,
C_COUNT_TYPE => 0,
C_DATA_COUNT_WIDTH => 4,
C_DEFAULT_VALUE => "BlankString",
C_DIN_WIDTH => 103,
C_DOUT_RST_VAL => "0",
C_DOUT_WIDTH => 103,
C_ENABLE_RLOCS => 0,
C_FAMILY => "zynq",
C_FULL_FLAGS_RST_VAL => 1,
C_HAS_ALMOST_EMPTY => 0,
C_HAS_ALMOST_FULL => 0,
C_HAS_BACKUP => 0,
C_HAS_DATA_COUNT => 0,
C_HAS_INT_CLK => 0,
C_HAS_MEMINIT_FILE => 0,
C_HAS_OVERFLOW => 0,
C_HAS_RD_DATA_COUNT => 0,
C_HAS_RD_RST => 0,
C_HAS_RST => 1,
C_HAS_SRST => 0,
C_HAS_UNDERFLOW => 0,
C_HAS_VALID => 0,
C_HAS_WR_ACK => 0,
C_HAS_WR_DATA_COUNT => 0,
C_HAS_WR_RST => 0,
C_IMPLEMENTATION_TYPE => 2,
C_INIT_WR_PNTR_VAL => 0,
C_MEMORY_TYPE => 2,
C_MIF_FILE_NAME => "BlankString",
C_OPTIMIZATION_MODE => 0,
C_OVERFLOW_LOW => 0,
C_PRELOAD_LATENCY => 0,
C_PRELOAD_REGS => 1,
C_PRIM_FIFO_TYPE => "512x72",
C_PROG_EMPTY_THRESH_ASSERT_VAL => 4,
C_PROG_EMPTY_THRESH_NEGATE_VAL => 5,
C_PROG_EMPTY_TYPE => 0,
C_PROG_FULL_THRESH_ASSERT_VAL => 12,
C_PROG_FULL_THRESH_NEGATE_VAL => 11,
C_PROG_FULL_TYPE => 1,
C_RD_DATA_COUNT_WIDTH => 4,
C_RD_DEPTH => 16,
C_RD_FREQ => 1,
C_RD_PNTR_WIDTH => 4,
C_UNDERFLOW_LOW => 0,
C_USE_DOUT_RST => 1,
C_USE_ECC => 0,
C_USE_EMBEDDED_REG => 0,
C_USE_PIPELINE_REG => 0,
C_POWER_SAVING_MODE => 0,
C_USE_FIFO16_FLAGS => 0,
C_USE_FWFT_DATA_COUNT => 0,
C_VALID_LOW => 0,
C_WR_ACK_LOW => 0,
C_WR_DATA_COUNT_WIDTH => 4,
C_WR_DEPTH => 16,
C_WR_FREQ => 1,
C_WR_PNTR_WIDTH => 4,
C_WR_RESPONSE_LATENCY => 1,
C_MSGON_VAL => 1,
C_ENABLE_RST_SYNC => 1,
C_ERROR_INJECTION_TYPE => 0,
C_SYNCHRONIZER_STAGE => 2,
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_HAS_AXI_WR_CHANNEL => 1,
C_HAS_AXI_RD_CHANNEL => 1,
C_HAS_SLAVE_CE => 0,
C_HAS_MASTER_CE => 0,
C_ADD_NGC_CONSTRAINT => 0,
C_USE_COMMON_OVERFLOW => 0,
C_USE_COMMON_UNDERFLOW => 0,
C_USE_DEFAULT_SETTINGS => 0,
C_AXI_ID_WIDTH => 1,
C_AXI_ADDR_WIDTH => 32,
C_AXI_DATA_WIDTH => 64,
C_AXI_LEN_WIDTH => 8,
C_AXI_LOCK_WIDTH => 1,
C_HAS_AXI_ID => 0,
C_HAS_AXI_AWUSER => 0,
C_HAS_AXI_WUSER => 0,
C_HAS_AXI_BUSER => 0,
C_HAS_AXI_ARUSER => 0,
C_HAS_AXI_RUSER => 0,
C_AXI_ARUSER_WIDTH => 1,
C_AXI_AWUSER_WIDTH => 1,
C_AXI_WUSER_WIDTH => 1,
C_AXI_BUSER_WIDTH => 1,
C_AXI_RUSER_WIDTH => 1,
C_HAS_AXIS_TDATA => 1,
C_HAS_AXIS_TID => 0,
C_HAS_AXIS_TDEST => 0,
C_HAS_AXIS_TUSER => 1,
C_HAS_AXIS_TREADY => 1,
C_HAS_AXIS_TLAST => 0,
C_HAS_AXIS_TSTRB => 0,
C_HAS_AXIS_TKEEP => 0,
C_AXIS_TDATA_WIDTH => 8,
C_AXIS_TID_WIDTH => 1,
C_AXIS_TDEST_WIDTH => 1,
C_AXIS_TUSER_WIDTH => 4,
C_AXIS_TSTRB_WIDTH => 1,
C_AXIS_TKEEP_WIDTH => 1,
C_WACH_TYPE => 0,
C_WDCH_TYPE => 0,
C_WRCH_TYPE => 0,
C_RACH_TYPE => 0,
C_RDCH_TYPE => 0,
C_AXIS_TYPE => 0,
C_IMPLEMENTATION_TYPE_WACH => 1,
C_IMPLEMENTATION_TYPE_WDCH => 1,
C_IMPLEMENTATION_TYPE_WRCH => 1,
C_IMPLEMENTATION_TYPE_RACH => 1,
C_IMPLEMENTATION_TYPE_RDCH => 1,
C_IMPLEMENTATION_TYPE_AXIS => 1,
C_APPLICATION_TYPE_WACH => 0,
C_APPLICATION_TYPE_WDCH => 0,
C_APPLICATION_TYPE_WRCH => 0,
C_APPLICATION_TYPE_RACH => 0,
C_APPLICATION_TYPE_RDCH => 0,
C_APPLICATION_TYPE_AXIS => 0,
C_PRIM_FIFO_TYPE_WACH => "512x36",
C_PRIM_FIFO_TYPE_WDCH => "1kx36",
C_PRIM_FIFO_TYPE_WRCH => "512x36",
C_PRIM_FIFO_TYPE_RACH => "512x36",
C_PRIM_FIFO_TYPE_RDCH => "1kx36",
C_PRIM_FIFO_TYPE_AXIS => "1kx18",
C_USE_ECC_WACH => 0,
C_USE_ECC_WDCH => 0,
C_USE_ECC_WRCH => 0,
C_USE_ECC_RACH => 0,
C_USE_ECC_RDCH => 0,
C_USE_ECC_AXIS => 0,
C_ERROR_INJECTION_TYPE_WACH => 0,
C_ERROR_INJECTION_TYPE_WDCH => 0,
C_ERROR_INJECTION_TYPE_WRCH => 0,
C_ERROR_INJECTION_TYPE_RACH => 0,
C_ERROR_INJECTION_TYPE_RDCH => 0,
C_ERROR_INJECTION_TYPE_AXIS => 0,
C_DIN_WIDTH_WACH => 32,
C_DIN_WIDTH_WDCH => 64,
C_DIN_WIDTH_WRCH => 2,
C_DIN_WIDTH_RACH => 32,
C_DIN_WIDTH_RDCH => 64,
C_DIN_WIDTH_AXIS => 1,
C_WR_DEPTH_WACH => 16,
C_WR_DEPTH_WDCH => 1024,
C_WR_DEPTH_WRCH => 16,
C_WR_DEPTH_RACH => 16,
C_WR_DEPTH_RDCH => 1024,
C_WR_DEPTH_AXIS => 1024,
C_WR_PNTR_WIDTH_WACH => 4,
C_WR_PNTR_WIDTH_WDCH => 10,
C_WR_PNTR_WIDTH_WRCH => 4,
C_WR_PNTR_WIDTH_RACH => 4,
C_WR_PNTR_WIDTH_RDCH => 10,
C_WR_PNTR_WIDTH_AXIS => 10,
C_HAS_DATA_COUNTS_WACH => 0,
C_HAS_DATA_COUNTS_WDCH => 0,
C_HAS_DATA_COUNTS_WRCH => 0,
C_HAS_DATA_COUNTS_RACH => 0,
C_HAS_DATA_COUNTS_RDCH => 0,
C_HAS_DATA_COUNTS_AXIS => 0,
C_HAS_PROG_FLAGS_WACH => 0,
C_HAS_PROG_FLAGS_WDCH => 0,
C_HAS_PROG_FLAGS_WRCH => 0,
C_HAS_PROG_FLAGS_RACH => 0,
C_HAS_PROG_FLAGS_RDCH => 0,
C_HAS_PROG_FLAGS_AXIS => 0,
C_PROG_FULL_TYPE_WACH => 0,
C_PROG_FULL_TYPE_WDCH => 0,
C_PROG_FULL_TYPE_WRCH => 0,
C_PROG_FULL_TYPE_RACH => 0,
C_PROG_FULL_TYPE_RDCH => 0,
C_PROG_FULL_TYPE_AXIS => 0,
C_PROG_FULL_THRESH_ASSERT_VAL_WACH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_RACH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS => 1023,
C_PROG_EMPTY_TYPE_WACH => 0,
C_PROG_EMPTY_TYPE_WDCH => 0,
C_PROG_EMPTY_TYPE_WRCH => 0,
C_PROG_EMPTY_TYPE_RACH => 0,
C_PROG_EMPTY_TYPE_RDCH => 0,
C_PROG_EMPTY_TYPE_AXIS => 0,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS => 1022,
C_REG_SLICE_MODE_WACH => 0,
C_REG_SLICE_MODE_WDCH => 0,
C_REG_SLICE_MODE_WRCH => 0,
C_REG_SLICE_MODE_RACH => 0,
C_REG_SLICE_MODE_RDCH => 0,
C_REG_SLICE_MODE_AXIS => 0
)
PORT MAP (
backup => '0',
backup_marker => '0',
clk => '0',
rst => rst,
srst => '0',
wr_clk => wr_clk,
wr_rst => '0',
rd_clk => rd_clk,
rd_rst => '0',
din => din,
wr_en => wr_en,
rd_en => rd_en,
prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
prog_empty_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
prog_empty_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
prog_full_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
prog_full_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
int_clk => '0',
injectdbiterr => '0',
injectsbiterr => '0',
sleep => '0',
dout => dout,
full => full,
empty => empty,
prog_full => prog_full,
m_aclk => '0',
s_aclk => '0',
s_aresetn => '0',
m_aclk_en => '0',
s_aclk_en => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awvalid => '0',
s_axi_wid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_wlast => '0',
s_axi_wuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wvalid => '0',
s_axi_bready => '0',
m_axi_awready => '0',
m_axi_wready => '0',
m_axi_bid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_bresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_buser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_bvalid => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_arcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_arprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_arregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_aruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_arvalid => '0',
s_axi_rready => '0',
m_axi_arready => '0',
m_axi_rid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_rdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
m_axi_rresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_rlast => '0',
m_axi_ruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_rvalid => '0',
s_axis_tvalid => '0',
s_axis_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_tstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tkeep => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tlast => '0',
s_axis_tid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tdest => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
m_axis_tready => '0',
axi_aw_injectsbiterr => '0',
axi_aw_injectdbiterr => '0',
axi_aw_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_aw_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_w_injectsbiterr => '0',
axi_w_injectdbiterr => '0',
axi_w_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_w_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_b_injectsbiterr => '0',
axi_b_injectdbiterr => '0',
axi_b_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_b_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_ar_injectsbiterr => '0',
axi_ar_injectdbiterr => '0',
axi_ar_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_ar_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_r_injectsbiterr => '0',
axi_r_injectdbiterr => '0',
axi_r_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_r_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axis_injectsbiterr => '0',
axis_injectdbiterr => '0',
axis_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axis_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10))
);
END fifo_async_103x16_arch;
| gpl-3.0 |
JuanMarcosRamirez/WeightedMedianDisenoLogico | misc/Anexos/VHDL/ro_filt_3x3.vhd | 3 | 6378 | -------------------------------------------------------------- ------------
-- Autor original: Antony Nelson.
-- Modificaciones de esta versión: Jorge Márquez
--
-- Esta rutina contiene las modificaciones indicadas en la sección de
-- Anexos del informe de trabajo de grado PROCESAMIENTO DE IMÁGENES DE
-- ANGIOGRAFÍA BIPLANA USANDO UNA TARJETA DE DESARROLLO SPARTAN-3E
--
-- UNIVERSIDAD DE LOS ANDES
-- FACULTAD DE INGENIERÍA
-- ESCUELA DE INGENIERÍA ELÉCTRICA
--
-- Mérida, Septiembre, 2008
----------------------------------- ----------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity ro_filt_3x3 is
generic (
vwidth: integer:=8;
order: integer:=5;
num_cols: integer:=512;
num_rows: integer:=512
);
port (
Clk : in std_logic;
RSTn : in std_logic;
D : in std_logic_vector(vwidth-1 downto 0);
Dout : out std_logic_vector(vwidth -1 downto 0);
DV : out std_logic;
FColPos : out integer;
FRowPos : out integer
);
end ro_filt_3x3;
architecture ro_filt_3x3 of ro_filt_3x3 is
component sort_3x3
generic (
vwidth: integer:=8
);
port (
Clk : in std_logic;
RSTn : in std_logic;
w11 : in std_logic_vector((vwidth -1) downto 0);
w12 : in std_logic_vector((vwidth -1) downto 0);
w13 : in std_logic_vector((vwidth -1) downto 0);
w21 : in std_logic_vector((vwidth-1) downto 0);
w22 : in std_logic_vector((vwidth -1) downto 0);
w23 : in std_logic_vector((vwidth -1) downto 0);
w31 : in std_logic_vector((vwidth -1) downto 0);
w32 : in std_logic_vector((vwidth -1) downto 0);
w33 : in std_logic_vector((vwidth-1) downto 0);
DVw : in std_logic;
DVs : out std_logic;
s1 : out std_logic_vector(vwidth -1 downto 0);
s2 : out std_logic_vector(vwidth -1 downto 0);
s3 : out std_logic_vector(vwidth -1 downto 0);
s4 : out std_logic_vector(vwidth-1 downto 0);
s5 : out std_logic_vector(vwidth -1 downto 0);
s6 : out std_logic_vector(vwidth -1 downto 0);
s7 : out std_logic_vector(vwidth -1 downto 0);
s8 : out std_logic_vector(vwidth -1 downto 0);
s9 : out std_logic_vector(vwidth -1 downto 0)
);
end component sort_3x3;
signal w11: std_logic_vector((vwidth -1) downto 0);
signal w12: std_logic_vector((vwidth -1) downto 0);
signal w13: std_logic_vector((vwidth -1) downto 0);
signal w21: std_logic_vector((vwidth -1) downto 0);
signal w22: std_logic_vector((vwidth-1) downto 0);
signal w23: std_logic_vector((vwidth -1) downto 0);
signal w31: std_logic_vector((vwidth -1) downto 0);
signal w32: std_logic_vector((vwidth -1) downto 0);
signal w33: std_logic_vector((vwidth -1) downto 0);
signal DVw: std_logic;
signal DVs: std_logic;
signal s1: std_logic_vector(vwidth -1 downto 0);
signal s2: std_logic_vector(vwidth -1 downto 0);
signal s3: std_logic_vector(vwidth -1 downto 0);
signal s4: std_logic_vector(vwidth -1 downto 0);
signal s5: std_logic_vector(vwidth-1 downto 0);
signal s6: std_logic_vector(vwidth -1 downto 0);
signal s7: std_logic_vector(vwidth -1 downto 0);
signal s8: std_logic_vector(vwidth -1 downto 0);
signal s9: std_logic_vector(vwidth -1 downto 0);
component window_3x3
generic (
vwidth: integer:=8
);
port (
Clk : in std_logic;
RSTn : in std_logic;
D : in std_logic_vector(vwidth-1 downto 0);
w11 : out std_logic_vector(vwidth -1 downto 0);
w12 : out std_logic_vector(vwidth -1 downto 0);
w13 : out std_logic_vector(vwidth-1 downto 0);
w21 : out std_logic_vector(vwidth -1 downto 0);
w22 : out std_logic_vector(vwidth -1 downto 0);
w23 : out std_logic_vector(vwidth -1 downto 0);
w31 : out std_logic_vector(vwidth -1 downto 0);
w32 : out std_logic_vector(vwidth-1 downto 0);
w33 : out std_logic_vector(vwidth -1 downto 0);
DV : out std_logic:='0'
);
end component window_3x3;
component rc_counter
generic (
num_cols: integer:=512;
num_rows: integer:=512
);
port (
Clk : in std_logic;
RSTn : in std_logic;
En : in std_logic;
ColPos : out integer;
RowPos : out integer
);
end component rc_counter;
signal ColPos: integer:=0;
signal RowPos: integer:=0;
signal ColPos_c: integer:=0; -- corrected positions
signal RowPos_c: integer:=0;
signal rt1: integer:=0;
signal rt2: integer:=0;
signal rt3: integer:=0;
signal rt4: integer:=0;
signal rt5: integer:=0;
signal rt6: integer:=0;
signal rt7: integer:=0;
signal rt8: integer:=0;
signal rt9: integer:=0;
signal rt10: integer:=0;
signal rt11: integer:=0;
signal rt12: integer:=0;
signal rt13: integer:=0;
signal rt14: integer:=0;
signal rt15: integer:=0;
signal rt16: integer:=0;
signal flag: std_logic:='0';
begin
sort_3x3x: sort_3x3
generic map (
vwidth => 8
)
port map (
Clk => Clk,
RSTn => RSTn,
w11 => w11,
w12 => w12,
w13 => w13,
w21 => w21,
w22 => w22,
w23 => w23,
w31 => w31,
w32 => w32,
w33 => w33,
DVw => DVw,
DVs => DVs,
s1 => s1,
s2 => s2,
s3 => s3,
s4 => s4,
s5 => s5,
s6 => s6,
s7 => s7,
s8 => s8,
s9 => s9
);
window_3x3x: window_3x3
generic map (
vwidth => 8
)
port map (
Clk => Clk,
RSTn => RSTn,
D => D,
w11 => w11,
w12 => w12,
w13 => w13,
w21 => w21,
w22 => w22,
w23 => w23,
w31 => w31,
w32 => w32,
w33 => w33,
DV => DVw
);
rc_counterx: rc_counter
generic map (
num_cols => 512,
num_rows => 512
)
port map (
Clk => Clk,
RSTn => RSTn,
En => RSTn,
ColPos => ColPos,
RowPos => RowPos
);
FColPos <= ColPos;
FRowPos <= RowPos;
ro_filt_proc: process(RSTn,Clk)
begin
if RSTn = '0' then
ColPos_c <= 0;
rt1 <= 0;
rt2 <= 0;
rt3 <= 0;
rt4 <= 0;
rt5 <= 0;
rt6 <= 0;
rt7 <= 0;
rt8 <= 0;
rt9 <= 0;
rt10 <= 0;
rt11 <= 0;
rt12 <= 0;
rt13 <= 0;
rt14 <= 0;
rt15 <= 0;
rt16 <= 0;
RowPos_c <= 0;
Dout <= (others=>'0');
DV <= '0';
flag <= '0';
elsif rising_edge(Clk) then
-- counter correction
ColPos_c <= ((ColPos-17) mod 512);
rt1 <= ((RowPos-1) mod 512);
rt2 <= rt1;
rt3 <= rt2;
rt4 <= rt3;
rt5 <= rt4;
rt6 <= rt5;
rt7 <= rt6;
rt8 <= rt7;
rt9 <= rt8;
rt10 <= rt9;
rt11 <= rt10;
rt12 <= rt11;
rt13 <= rt12;
rt14 <= rt13;
rt15 <= rt14;
rt16 <= rt15;
RowPos_c <= rt16;
-- screen edge detection
if (ColPos_c = num_cols-1) or (RowPos_c = num_rows-1) or (ColPos_c
= num_cols-2) or (RowPos_c = 0) then
Dout <= (others=>'0');
else
if order = 1 then
Dout <= s1;
elsif order = 2 then
Dout <= s2;
elsif order = 3 then
Dout <= s3;
elsif order = 4 then
Dout <= s4;
elsif order = 5 then
Dout <= s5;
elsif order = 6 then
Dout <= s6;
elsif order = 7 then
Dout <= s7;
elsif order = 8 then
Dout <= s8;
elsif order = 9 then
Dout <= s9;
end if;
end if;
if ColPos >= 17 and RowPos >= 1 then
DV <= '1';
flag <= '1';
elsif flag = '1' then
DV <= '1';
else
DV <= '0';
end if;
end if;
end process;
end ro_filt_3x3; | gpl-3.0 |
DougFirErickson/parallella-hw | fpga/ip/xilinx/fifo_async_103x16/fifo_generator_v12_0/hdl/ramfifo/axi_reg_slice.vhd | 6 | 17522 | `protect begin_protected
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`protect end_protected
| gpl-3.0 |
DougFirErickson/parallella-hw | fpga/ip/xilinx/fifo_async_103x32/fifo_generator_v12_0/hdl/ramfifo/axi_reg_slice.vhd | 6 | 17522 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 11232)
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`protect end_protected
| gpl-3.0 |
DougFirErickson/parallella-hw | fpga/ip/xilinx/fifo_async_103x32/blk_mem_gen_v8_2/hdl/blk_mem_output_block.vhd | 8 | 17242 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 11024)
`protect data_block
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`protect end_protected
| gpl-3.0 |
DougFirErickson/parallella-hw | fpga/ip/xilinx/memory_dp_48x4096/blk_mem_gen_v8_2/hdl/blk_mem_output_block.vhd | 8 | 17242 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 11024)
`protect data_block
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`protect end_protected
| gpl-3.0 |
DougFirErickson/parallella-hw | fpga/ip/xilinx/fifo_async_103x16/fifo_async_103x16/fifo_generator_v12_0/hdl/fifo_generator_top.vhd | 6 | 36480 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 25264)
`protect data_block
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`protect end_protected
| gpl-3.0 |
DougFirErickson/parallella-hw | fpga/ip/xilinx/fifo_async_103x16/fifo_async_103x16/fifo_generator_v12_0/hdl/ramfifo/logic_sshft.vhd | 6 | 30599 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 20912)
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`protect end_protected
| gpl-3.0 |
DougFirErickson/parallella-hw | fpga/ip/xilinx/memory_dp_48x4096/blk_mem_gen_v8_2/hdl/blk_mem_gen_bindec.vhd | 8 | 10218 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 5824)
`protect data_block
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`protect end_protected
| gpl-3.0 |
DougFirErickson/parallella-hw | fpga/ip/xilinx/axi_bram_ctrl_16b/blk_mem_gen_v8_2/hdl/blk_mem_gen_bindec.vhd | 8 | 10218 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 5824)
`protect data_block
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`protect end_protected
| gpl-3.0 |
JuanMarcosRamirez/WeightedMedianDisenoLogico | misc/FPGA/rc_counter.vhd | 3 | 1352 | --------------------------------------------------------------------------
-- Autor original: Antony Nelson.
-- Modificaciones de esta versión: Jorge Márquez
--
-- Esta rutina contiene las modificaciones indicadas en la sección de
-- Anexos del informe de trabajo de grado PROCESAMIENTO DE IMÁGENES DE
-- ANGIOGRAFÍA BIPLANA USANDO UNA TARJETA DE DESARROLLO SPARTAN-3E
--
-- UNIVERSIDAD DE LOS ANDES
-- FACULTAD DE INGENIERÍA
-- ESCUELA DE INGENIERÍA ELÉCTRICA
--
-- Mérida, Septiembre, 2008
--
------------------------------------------- --------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity rc_counter is
generic (
num_cols: integer:=512;
num_rows: integer:=512
);
port (
Clk : in std_logic;
RSTn : in std_logic;
En : in std_logic;
ColPos : out integer;
RowPos : out integer
);
end rc_counter;
architecture rc_counter of rc_counter is
begin
process(RSTn,Clk,En)
variable ColPos_var: integer:=0;
variable RowPos_var: integer:=0;
begin
if RSTn = '0' then
ColPos_var := -1;
ColPos <= 0;
RowPos_var := 0;
RowPos <= 0;
elsif rising_edge(Clk) then
if En = '1' then
ColPos_var := ColPos_var +1;
if ColPos_var = num_cols then
RowPos_var := RowPos_var +1;
ColPos_var := 0;
if RowPos_var = num_rows then
RowPos_var := 0;
end if;
end if;
ColPos <= ColPos_var;
RowPos <= RowPos_var;
end if;
end if;
end process;
end rc_counter;
| gpl-3.0 |
JuanMarcosRamirez/WeightedMedianDisenoLogico | misc/Anexos/VHDL/rc_counter.vhd | 3 | 1352 | --------------------------------------------------------------------------
-- Autor original: Antony Nelson.
-- Modificaciones de esta versión: Jorge Márquez
--
-- Esta rutina contiene las modificaciones indicadas en la sección de
-- Anexos del informe de trabajo de grado PROCESAMIENTO DE IMÁGENES DE
-- ANGIOGRAFÍA BIPLANA USANDO UNA TARJETA DE DESARROLLO SPARTAN-3E
--
-- UNIVERSIDAD DE LOS ANDES
-- FACULTAD DE INGENIERÍA
-- ESCUELA DE INGENIERÍA ELÉCTRICA
--
-- Mérida, Septiembre, 2008
--
------------------------------------------- --------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity rc_counter is
generic (
num_cols: integer:=512;
num_rows: integer:=512
);
port (
Clk : in std_logic;
RSTn : in std_logic;
En : in std_logic;
ColPos : out integer;
RowPos : out integer
);
end rc_counter;
architecture rc_counter of rc_counter is
begin
process(RSTn,Clk,En)
variable ColPos_var: integer:=0;
variable RowPos_var: integer:=0;
begin
if RSTn = '0' then
ColPos_var := -1;
ColPos <= 0;
RowPos_var := 0;
RowPos <= 0;
elsif rising_edge(Clk) then
if En = '1' then
ColPos_var := ColPos_var +1;
if ColPos_var = num_cols then
RowPos_var := RowPos_var +1;
ColPos_var := 0;
if RowPos_var = num_rows then
RowPos_var := 0;
end if;
end if;
ColPos <= ColPos_var;
RowPos <= RowPos_var;
end if;
end if;
end process;
end rc_counter;
| gpl-3.0 |
JuanMarcosRamirez/WeightedMedianDisenoLogico | VHDL/ImageProcessingModule/bbfifo_16x8.vhd | 2 | 8392 | -- 'Bucket Brigade' FIFO
-- 16 deep
-- 8-bit data
--
-- Version : 1.10
-- Version Date : 3rd December 2003
-- Reason : '--translate' directives changed to '--synthesis translate' directives
--
-- Version : 1.00
-- Version Date : 14th October 2002
--
-- Start of design entry : 14th October 2002
--
-- Ken Chapman
-- Xilinx Ltd
-- Benchmark House
-- 203 Brooklands Road
-- Weybridge
-- Surrey KT13 ORH
-- United Kingdom
--
-- [email protected]
--
------------------------------------------------------------------------------------
--
-- NOTICE:
--
-- Copyright Xilinx, Inc. 2002. This code may be contain portions patented by other
-- third parties. By providing this core as one possible implementation of a standard,
-- Xilinx is making no representation that the provided implementation of this standard
-- is free from any claims of infringement by any third party. Xilinx expressly
-- disclaims any warranty with respect to the adequacy of the implementation, including
-- but not limited to any warranty or representation that the implementation is free
-- from claims of any third party. Futhermore, Xilinx is providing this core as a
-- courtesy to you and suggests that you contact all third parties to obtain the
-- necessary rights to use this implementation.
--
------------------------------------------------------------------------------------
--
-- Library declarations
--
-- The Unisim Library is used to define Xilinx primitives. It is also used during
-- simulation. The source can be viewed at %XILINX%\vhdl\src\unisims\unisim_VCOMP.vhd
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library unisim;
use unisim.vcomponents.all;
--
------------------------------------------------------------------------------------
--
-- Main Entity for BBFIFO_16x8
--
entity bbfifo_16x8 is
Port ( data_in : in std_logic_vector(7 downto 0);
data_out : out std_logic_vector(7 downto 0);
reset : in std_logic;
write : in std_logic;
read : in std_logic;
full : out std_logic;
half_full : out std_logic;
data_present : out std_logic;
clk : in std_logic);
end bbfifo_16x8;
--
------------------------------------------------------------------------------------
--
-- Start of Main Architecture for BBFIFO_16x8
--
architecture low_level_definition of bbfifo_16x8 is
--
------------------------------------------------------------------------------------
--
------------------------------------------------------------------------------------
--
-- Signals used in BBFIFO_16x8
--
------------------------------------------------------------------------------------
--
signal pointer : std_logic_vector(3 downto 0);
signal next_count : std_logic_vector(3 downto 0);
signal half_count : std_logic_vector(3 downto 0);
signal count_carry : std_logic_vector(2 downto 0);
signal pointer_zero : std_logic;
signal pointer_full : std_logic;
signal decode_data_present : std_logic;
signal data_present_int : std_logic;
signal valid_write : std_logic;
--
--
------------------------------------------------------------------------------------
--
-- Attributes to define LUT contents during implementation
-- The information is repeated in the generic map for functional simulation--
--
------------------------------------------------------------------------------------
--
attribute INIT : string;
attribute INIT of zero_lut : label is "0001";
attribute INIT of full_lut : label is "8000";
attribute INIT of dp_lut : label is "BFA0";
attribute INIT of valid_lut : label is "C4";
--
------------------------------------------------------------------------------------
--
-- Start of BBFIFO_16x8 circuit description
--
------------------------------------------------------------------------------------
--
begin
-- SRL16E data storage
data_width_loop: for i in 0 to 7 generate
--
attribute INIT : string;
attribute INIT of data_srl : label is "0000";
--
begin
data_srl: SRL16E
--synthesis translate_off
generic map (INIT => X"0000")
--synthesis translate_on
port map( D => data_in(i),
CE => valid_write,
CLK => clk,
A0 => pointer(0),
A1 => pointer(1),
A2 => pointer(2),
A3 => pointer(3),
Q => data_out(i) );
end generate data_width_loop;
-- 4-bit counter to act as data pointer
-- Counter is clock enabled by 'data_present'
-- Counter will be reset when 'reset' is active
-- Counter will increment when 'valid_write' is active
count_width_loop: for i in 0 to 3 generate
--
attribute INIT : string;
attribute INIT of count_lut : label is "6606";
--
begin
register_bit: FDRE
port map ( D => next_count(i),
Q => pointer(i),
CE => data_present_int,
R => reset,
C => clk);
count_lut: LUT4
--synthesis translate_off
generic map (INIT => X"6606")
--synthesis translate_on
port map( I0 => pointer(i),
I1 => read,
I2 => pointer_zero,
I3 => write,
O => half_count(i));
lsb_count: if i=0 generate
begin
count_muxcy: MUXCY
port map( DI => pointer(i),
CI => valid_write,
S => half_count(i),
O => count_carry(i));
count_xor: XORCY
port map( LI => half_count(i),
CI => valid_write,
O => next_count(i));
end generate lsb_count;
mid_count: if i>0 and i<3 generate
begin
count_muxcy: MUXCY
port map( DI => pointer(i),
CI => count_carry(i-1),
S => half_count(i),
O => count_carry(i));
count_xor: XORCY
port map( LI => half_count(i),
CI => count_carry(i-1),
O => next_count(i));
end generate mid_count;
upper_count: if i=3 generate
begin
count_xor: XORCY
port map( LI => half_count(i),
CI => count_carry(i-1),
O => next_count(i));
end generate upper_count;
end generate count_width_loop;
-- Detect when pointer is zero and maximum
zero_lut: LUT4
--synthesis translate_off
generic map (INIT => X"0001")
--synthesis translate_on
port map( I0 => pointer(0),
I1 => pointer(1),
I2 => pointer(2),
I3 => pointer(3),
O => pointer_zero );
full_lut: LUT4
--synthesis translate_off
generic map (INIT => X"8000")
--synthesis translate_on
port map( I0 => pointer(0),
I1 => pointer(1),
I2 => pointer(2),
I3 => pointer(3),
O => pointer_full );
-- Data Present status
dp_lut: LUT4
--synthesis translate_off
generic map (INIT => X"BFA0")
--synthesis translate_on
port map( I0 => write,
I1 => read,
I2 => pointer_zero,
I3 => data_present_int,
O => decode_data_present );
dp_flop: FDR
port map ( D => decode_data_present,
Q => data_present_int,
R => reset,
C => clk);
-- Valid write signal
valid_lut: LUT3
--synthesis translate_off
generic map (INIT => X"C4")
--synthesis translate_on
port map( I0 => pointer_full,
I1 => write,
I2 => read,
O => valid_write );
-- assign internal signals to outputs
full <= pointer_full;
half_full <= pointer(3);
data_present <= data_present_int;
end low_level_definition;
------------------------------------------------------------------------------------
--
-- END OF FILE BBFIFO_16x8.VHD
--
------------------------------------------------------------------------------------
| gpl-3.0 |
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| gpl-3.0 |
JuanMarcosRamirez/WeightedMedianDisenoLogico | misc/FPGA/FIFO 512x8/fifo_512x8x/fifo_512x8x.vhd | 4 | 5494 | --------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used --
-- solely for design, simulation, implementation and creation of --
-- design files limited to Xilinx devices or technologies. Use --
-- with non-Xilinx devices or technologies is expressly prohibited --
-- and immediately terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" --
-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR --
-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION --
-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION --
-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS --
-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, --
-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE --
-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY --
-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --
-- FOR A PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support --
-- appliances, devices, or systems. Use in such applications are --
-- expressly prohibited. --
-- --
-- (c) Copyright 1995-2007 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
-- You must compile the wrapper file fifo_512x8x.vhd when simulating
-- the core, fifo_512x8x. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
Library XilinxCoreLib;
-- synthesis translate_on
ENTITY fifo_512x8x IS
port (
din: IN std_logic_VECTOR(7 downto 0);
rd_clk: IN std_logic;
rd_en: IN std_logic;
rst: IN std_logic;
wr_clk: IN std_logic;
wr_en: IN std_logic;
dout: OUT std_logic_VECTOR(7 downto 0);
empty: OUT std_logic;
full: OUT std_logic;
wr_data_count: OUT std_logic_VECTOR(8 downto 0));
END fifo_512x8x;
ARCHITECTURE fifo_512x8x_a OF fifo_512x8x IS
-- synthesis translate_off
component wrapped_fifo_512x8x
port (
din: IN std_logic_VECTOR(7 downto 0);
rd_clk: IN std_logic;
rd_en: IN std_logic;
rst: IN std_logic;
wr_clk: IN std_logic;
wr_en: IN std_logic;
dout: OUT std_logic_VECTOR(7 downto 0);
empty: OUT std_logic;
full: OUT std_logic;
wr_data_count: OUT std_logic_VECTOR(8 downto 0));
end component;
-- Configuration specification
for all : wrapped_fifo_512x8x use entity XilinxCoreLib.fifo_generator_v3_3(behavioral)
generic map(
c_rd_freq => 100,
c_wr_response_latency => 1,
c_has_srst => 0,
c_has_rd_data_count => 0,
c_din_width => 8,
c_has_wr_data_count => 1,
c_implementation_type => 2,
c_family => "spartan3",
c_has_wr_rst => 0,
c_wr_freq => 100,
c_underflow_low => 0,
c_has_meminit_file => 0,
c_has_overflow => 0,
c_preload_latency => 1,
c_dout_width => 8,
c_rd_depth => 512,
c_default_value => "BlankString",
c_mif_file_name => "BlankString",
c_has_underflow => 0,
c_has_rd_rst => 0,
c_has_almost_full => 0,
c_has_rst => 1,
c_data_count_width => 9,
c_has_wr_ack => 0,
c_use_ecc => 0,
c_wr_ack_low => 0,
c_common_clock => 0,
c_rd_pntr_width => 9,
c_has_almost_empty => 0,
c_rd_data_count_width => 9,
c_enable_rlocs => 0,
c_wr_pntr_width => 9,
c_overflow_low => 0,
c_prog_empty_type => 0,
c_optimization_mode => 0,
c_wr_data_count_width => 9,
c_preload_regs => 0,
c_dout_rst_val => "0",
c_has_data_count => 0,
c_prog_full_thresh_negate_val => 509,
c_wr_depth => 512,
c_prog_empty_thresh_negate_val => 3,
c_prog_empty_thresh_assert_val => 2,
c_has_valid => 0,
c_init_wr_pntr_val => 0,
c_prog_full_thresh_assert_val => 510,
c_use_fifo16_flags => 0,
c_has_backup => 0,
c_valid_low => 0,
c_prim_fifo_type => "2kx9",
c_count_type => 0,
c_prog_full_type => 0,
c_memory_type => 1);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_fifo_512x8x
port map (
din => din,
rd_clk => rd_clk,
rd_en => rd_en,
rst => rst,
wr_clk => wr_clk,
wr_en => wr_en,
dout => dout,
empty => empty,
full => full,
wr_data_count => wr_data_count);
-- synthesis translate_on
END fifo_512x8x_a;
| gpl-3.0 |
DougFirErickson/parallella-hw | fpga/ip/xilinx/fifo_async_103x32/fifo_generator_v12_0/hdl/fifo_generator_top_bi_sim.vhd | 6 | 28804 | `protect begin_protected
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| gpl-3.0 |
JuanMarcosRamirez/WeightedMedianDisenoLogico | misc/FPGA/otros/auditoría_imagen_16x16/fifo_16x8x.vhd | 1 | 5480 | --------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used --
-- solely for design, simulation, implementation and creation of --
-- design files limited to Xilinx devices or technologies. Use --
-- with non-Xilinx devices or technologies is expressly prohibited --
-- and immediately terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" --
-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR --
-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION --
-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION --
-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS --
-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, --
-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE --
-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY --
-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --
-- FOR A PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support --
-- appliances, devices, or systems. Use in such applications are --
-- expressly prohibited. --
-- --
-- (c) Copyright 1995-2007 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
-- You must compile the wrapper file fifo_16x8x.vhd when simulating
-- the core, fifo_16x8x. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
Library XilinxCoreLib;
-- synthesis translate_on
ENTITY fifo_16x8x IS
port (
din: IN std_logic_VECTOR(7 downto 0);
rd_clk: IN std_logic;
rd_en: IN std_logic;
rst: IN std_logic;
wr_clk: IN std_logic;
wr_en: IN std_logic;
dout: OUT std_logic_VECTOR(7 downto 0);
empty: OUT std_logic;
full: OUT std_logic;
wr_data_count: OUT std_logic_VECTOR(3 downto 0));
END fifo_16x8x;
ARCHITECTURE fifo_16x8x_a OF fifo_16x8x IS
-- synthesis translate_off
component wrapped_fifo_16x8x
port (
din: IN std_logic_VECTOR(7 downto 0);
rd_clk: IN std_logic;
rd_en: IN std_logic;
rst: IN std_logic;
wr_clk: IN std_logic;
wr_en: IN std_logic;
dout: OUT std_logic_VECTOR(7 downto 0);
empty: OUT std_logic;
full: OUT std_logic;
wr_data_count: OUT std_logic_VECTOR(3 downto 0));
end component;
-- Configuration specification
for all : wrapped_fifo_16x8x use entity XilinxCoreLib.fifo_generator_v3_3(behavioral)
generic map(
c_rd_freq => 100,
c_wr_response_latency => 1,
c_has_srst => 0,
c_has_rd_data_count => 0,
c_din_width => 8,
c_has_wr_data_count => 1,
c_implementation_type => 2,
c_family => "spartan3",
c_has_wr_rst => 0,
c_wr_freq => 100,
c_underflow_low => 0,
c_has_meminit_file => 0,
c_has_overflow => 0,
c_preload_latency => 1,
c_dout_width => 8,
c_rd_depth => 16,
c_default_value => "BlankString",
c_mif_file_name => "BlankString",
c_has_underflow => 0,
c_has_rd_rst => 0,
c_has_almost_full => 0,
c_has_rst => 1,
c_data_count_width => 4,
c_has_wr_ack => 0,
c_use_ecc => 0,
c_wr_ack_low => 0,
c_common_clock => 0,
c_rd_pntr_width => 4,
c_has_almost_empty => 0,
c_rd_data_count_width => 4,
c_enable_rlocs => 0,
c_wr_pntr_width => 4,
c_overflow_low => 0,
c_prog_empty_type => 0,
c_optimization_mode => 0,
c_wr_data_count_width => 4,
c_preload_regs => 0,
c_dout_rst_val => "0",
c_has_data_count => 0,
c_prog_full_thresh_negate_val => 13,
c_wr_depth => 16,
c_prog_empty_thresh_negate_val => 3,
c_prog_empty_thresh_assert_val => 2,
c_has_valid => 0,
c_init_wr_pntr_val => 0,
c_prog_full_thresh_assert_val => 14,
c_use_fifo16_flags => 0,
c_has_backup => 0,
c_valid_low => 0,
c_prim_fifo_type => "2kx9",
c_count_type => 0,
c_prog_full_type => 0,
c_memory_type => 1);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_fifo_16x8x
port map (
din => din,
rd_clk => rd_clk,
rd_en => rd_en,
rst => rst,
wr_clk => wr_clk,
wr_en => wr_en,
dout => dout,
empty => empty,
full => full,
wr_data_count => wr_data_count);
-- synthesis translate_on
END fifo_16x8x_a;
| gpl-3.0 |
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`protect end_protected
| gpl-3.0 |
DougFirErickson/parallella-hw | fpga/ip/xilinx/fifo_async_103x16/fifo_async_103x16/fifo_generator_v12_0/hdl/ramfifo/memory.vhd | 6 | 114225 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect end_protected
| gpl-3.0 |
JuanMarcosRamirez/WeightedMedianDisenoLogico | misc/Adicionales/Programador_StrataFlash_modificado/Ensamblador/ROM_form.vhd | 1 | 12433 | ROM_form.vhd
Ken Chapman (Xilinx Ltd) July 2003
This is the VHDL template file for the KCPSM3 assembler.
It is used to configure a Spartan-3, Virtex-II or Virtex-IIPRO block RAM to act as
a single port program ROM.
This VHDL file is not valid as input directly into a synthesis or simulation tool.
The assembler will read this template and insert the data required to complete the
definition of program ROM and write it out to a new '.vhd' file associated with the
name of the original '.psm' file being assembled.
This template can be modified to define alternative memory definitions such as dual port.
However, you are responsible for ensuring the template is correct as the assembler does
not perform any checking of the VHDL.
The assembler identifies all text enclosed by {} characters, and replaces these
character strings. All templates should include these {} character strings for
the assembler to work correctly.
****************************************************************************************
This template defines a block RAM configured in 1024 x 18-bit single port mode and
conneceted to act as a single port ROM.
****************************************************************************************
The next line is used to determine where the template actually starts and must exist.
{begin template}
--
-- Definition of a single port ROM for KCPSM3 program defined by {name}.psm
-- and assmbled using KCPSM3 assembler.
--
-- Standard IEEE libraries
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--
-- The Unisim Library is used to define Xilinx primitives. It is also used during
-- simulation. The source can be viewed at %XILINX%\vhdl\src\unisims\unisim_VCOMP.vhd
--
library unisim;
use unisim.vcomponents.all;
--
--
entity {name} is
Port ( address : in std_logic_vector(9 downto 0);
instruction : out std_logic_vector(17 downto 0);
clk : in std_logic);
end {name};
--
architecture low_level_definition of {name} is
--
-- Attributes to define ROM contents during implementation synthesis.
-- The information is repeated in the generic map for functional simulation
--
attribute INIT_00 : string;
attribute INIT_01 : string;
attribute INIT_02 : string;
attribute INIT_03 : string;
attribute INIT_04 : string;
attribute INIT_05 : string;
attribute INIT_06 : string;
attribute INIT_07 : string;
attribute INIT_08 : string;
attribute INIT_09 : string;
attribute INIT_0A : string;
attribute INIT_0B : string;
attribute INIT_0C : string;
attribute INIT_0D : string;
attribute INIT_0E : string;
attribute INIT_0F : string;
attribute INIT_10 : string;
attribute INIT_11 : string;
attribute INIT_12 : string;
attribute INIT_13 : string;
attribute INIT_14 : string;
attribute INIT_15 : string;
attribute INIT_16 : string;
attribute INIT_17 : string;
attribute INIT_18 : string;
attribute INIT_19 : string;
attribute INIT_1A : string;
attribute INIT_1B : string;
attribute INIT_1C : string;
attribute INIT_1D : string;
attribute INIT_1E : string;
attribute INIT_1F : string;
attribute INIT_20 : string;
attribute INIT_21 : string;
attribute INIT_22 : string;
attribute INIT_23 : string;
attribute INIT_24 : string;
attribute INIT_25 : string;
attribute INIT_26 : string;
attribute INIT_27 : string;
attribute INIT_28 : string;
attribute INIT_29 : string;
attribute INIT_2A : string;
attribute INIT_2B : string;
attribute INIT_2C : string;
attribute INIT_2D : string;
attribute INIT_2E : string;
attribute INIT_2F : string;
attribute INIT_30 : string;
attribute INIT_31 : string;
attribute INIT_32 : string;
attribute INIT_33 : string;
attribute INIT_34 : string;
attribute INIT_35 : string;
attribute INIT_36 : string;
attribute INIT_37 : string;
attribute INIT_38 : string;
attribute INIT_39 : string;
attribute INIT_3A : string;
attribute INIT_3B : string;
attribute INIT_3C : string;
attribute INIT_3D : string;
attribute INIT_3E : string;
attribute INIT_3F : string;
attribute INITP_00 : string;
attribute INITP_01 : string;
attribute INITP_02 : string;
attribute INITP_03 : string;
attribute INITP_04 : string;
attribute INITP_05 : string;
attribute INITP_06 : string;
attribute INITP_07 : string;
--
-- Attributes to define ROM contents during implementation synthesis.
--
attribute INIT_00 of ram_1024_x_18 : label is "{INIT_00}";
attribute INIT_01 of ram_1024_x_18 : label is "{INIT_01}";
attribute INIT_02 of ram_1024_x_18 : label is "{INIT_02}";
attribute INIT_03 of ram_1024_x_18 : label is "{INIT_03}";
attribute INIT_04 of ram_1024_x_18 : label is "{INIT_04}";
attribute INIT_05 of ram_1024_x_18 : label is "{INIT_05}";
attribute INIT_06 of ram_1024_x_18 : label is "{INIT_06}";
attribute INIT_07 of ram_1024_x_18 : label is "{INIT_07}";
attribute INIT_08 of ram_1024_x_18 : label is "{INIT_08}";
attribute INIT_09 of ram_1024_x_18 : label is "{INIT_09}";
attribute INIT_0A of ram_1024_x_18 : label is "{INIT_0A}";
attribute INIT_0B of ram_1024_x_18 : label is "{INIT_0B}";
attribute INIT_0C of ram_1024_x_18 : label is "{INIT_0C}";
attribute INIT_0D of ram_1024_x_18 : label is "{INIT_0D}";
attribute INIT_0E of ram_1024_x_18 : label is "{INIT_0E}";
attribute INIT_0F of ram_1024_x_18 : label is "{INIT_0F}";
attribute INIT_10 of ram_1024_x_18 : label is "{INIT_10}";
attribute INIT_11 of ram_1024_x_18 : label is "{INIT_11}";
attribute INIT_12 of ram_1024_x_18 : label is "{INIT_12}";
attribute INIT_13 of ram_1024_x_18 : label is "{INIT_13}";
attribute INIT_14 of ram_1024_x_18 : label is "{INIT_14}";
attribute INIT_15 of ram_1024_x_18 : label is "{INIT_15}";
attribute INIT_16 of ram_1024_x_18 : label is "{INIT_16}";
attribute INIT_17 of ram_1024_x_18 : label is "{INIT_17}";
attribute INIT_18 of ram_1024_x_18 : label is "{INIT_18}";
attribute INIT_19 of ram_1024_x_18 : label is "{INIT_19}";
attribute INIT_1A of ram_1024_x_18 : label is "{INIT_1A}";
attribute INIT_1B of ram_1024_x_18 : label is "{INIT_1B}";
attribute INIT_1C of ram_1024_x_18 : label is "{INIT_1C}";
attribute INIT_1D of ram_1024_x_18 : label is "{INIT_1D}";
attribute INIT_1E of ram_1024_x_18 : label is "{INIT_1E}";
attribute INIT_1F of ram_1024_x_18 : label is "{INIT_1F}";
attribute INIT_20 of ram_1024_x_18 : label is "{INIT_20}";
attribute INIT_21 of ram_1024_x_18 : label is "{INIT_21}";
attribute INIT_22 of ram_1024_x_18 : label is "{INIT_22}";
attribute INIT_23 of ram_1024_x_18 : label is "{INIT_23}";
attribute INIT_24 of ram_1024_x_18 : label is "{INIT_24}";
attribute INIT_25 of ram_1024_x_18 : label is "{INIT_25}";
attribute INIT_26 of ram_1024_x_18 : label is "{INIT_26}";
attribute INIT_27 of ram_1024_x_18 : label is "{INIT_27}";
attribute INIT_28 of ram_1024_x_18 : label is "{INIT_28}";
attribute INIT_29 of ram_1024_x_18 : label is "{INIT_29}";
attribute INIT_2A of ram_1024_x_18 : label is "{INIT_2A}";
attribute INIT_2B of ram_1024_x_18 : label is "{INIT_2B}";
attribute INIT_2C of ram_1024_x_18 : label is "{INIT_2C}";
attribute INIT_2D of ram_1024_x_18 : label is "{INIT_2D}";
attribute INIT_2E of ram_1024_x_18 : label is "{INIT_2E}";
attribute INIT_2F of ram_1024_x_18 : label is "{INIT_2F}";
attribute INIT_30 of ram_1024_x_18 : label is "{INIT_30}";
attribute INIT_31 of ram_1024_x_18 : label is "{INIT_31}";
attribute INIT_32 of ram_1024_x_18 : label is "{INIT_32}";
attribute INIT_33 of ram_1024_x_18 : label is "{INIT_33}";
attribute INIT_34 of ram_1024_x_18 : label is "{INIT_34}";
attribute INIT_35 of ram_1024_x_18 : label is "{INIT_35}";
attribute INIT_36 of ram_1024_x_18 : label is "{INIT_36}";
attribute INIT_37 of ram_1024_x_18 : label is "{INIT_37}";
attribute INIT_38 of ram_1024_x_18 : label is "{INIT_38}";
attribute INIT_39 of ram_1024_x_18 : label is "{INIT_39}";
attribute INIT_3A of ram_1024_x_18 : label is "{INIT_3A}";
attribute INIT_3B of ram_1024_x_18 : label is "{INIT_3B}";
attribute INIT_3C of ram_1024_x_18 : label is "{INIT_3C}";
attribute INIT_3D of ram_1024_x_18 : label is "{INIT_3D}";
attribute INIT_3E of ram_1024_x_18 : label is "{INIT_3E}";
attribute INIT_3F of ram_1024_x_18 : label is "{INIT_3F}";
attribute INITP_00 of ram_1024_x_18 : label is "{INITP_00}";
attribute INITP_01 of ram_1024_x_18 : label is "{INITP_01}";
attribute INITP_02 of ram_1024_x_18 : label is "{INITP_02}";
attribute INITP_03 of ram_1024_x_18 : label is "{INITP_03}";
attribute INITP_04 of ram_1024_x_18 : label is "{INITP_04}";
attribute INITP_05 of ram_1024_x_18 : label is "{INITP_05}";
attribute INITP_06 of ram_1024_x_18 : label is "{INITP_06}";
attribute INITP_07 of ram_1024_x_18 : label is "{INITP_07}";
--
begin
--
--Instantiate the Xilinx primitive for a block RAM
ram_1024_x_18: RAMB16_S18
--synthesis translate_off
--INIT values repeated to define contents for functional simulation
generic map ( INIT_00 => X"{INIT_00}",
INIT_01 => X"{INIT_01}",
INIT_02 => X"{INIT_02}",
INIT_03 => X"{INIT_03}",
INIT_04 => X"{INIT_04}",
INIT_05 => X"{INIT_05}",
INIT_06 => X"{INIT_06}",
INIT_07 => X"{INIT_07}",
INIT_08 => X"{INIT_08}",
INIT_09 => X"{INIT_09}",
INIT_0A => X"{INIT_0A}",
INIT_0B => X"{INIT_0B}",
INIT_0C => X"{INIT_0C}",
INIT_0D => X"{INIT_0D}",
INIT_0E => X"{INIT_0E}",
INIT_0F => X"{INIT_0F}",
INIT_10 => X"{INIT_10}",
INIT_11 => X"{INIT_11}",
INIT_12 => X"{INIT_12}",
INIT_13 => X"{INIT_13}",
INIT_14 => X"{INIT_14}",
INIT_15 => X"{INIT_15}",
INIT_16 => X"{INIT_16}",
INIT_17 => X"{INIT_17}",
INIT_18 => X"{INIT_18}",
INIT_19 => X"{INIT_19}",
INIT_1A => X"{INIT_1A}",
INIT_1B => X"{INIT_1B}",
INIT_1C => X"{INIT_1C}",
INIT_1D => X"{INIT_1D}",
INIT_1E => X"{INIT_1E}",
INIT_1F => X"{INIT_1F}",
INIT_20 => X"{INIT_20}",
INIT_21 => X"{INIT_21}",
INIT_22 => X"{INIT_22}",
INIT_23 => X"{INIT_23}",
INIT_24 => X"{INIT_24}",
INIT_25 => X"{INIT_25}",
INIT_26 => X"{INIT_26}",
INIT_27 => X"{INIT_27}",
INIT_28 => X"{INIT_28}",
INIT_29 => X"{INIT_29}",
INIT_2A => X"{INIT_2A}",
INIT_2B => X"{INIT_2B}",
INIT_2C => X"{INIT_2C}",
INIT_2D => X"{INIT_2D}",
INIT_2E => X"{INIT_2E}",
INIT_2F => X"{INIT_2F}",
INIT_30 => X"{INIT_30}",
INIT_31 => X"{INIT_31}",
INIT_32 => X"{INIT_32}",
INIT_33 => X"{INIT_33}",
INIT_34 => X"{INIT_34}",
INIT_35 => X"{INIT_35}",
INIT_36 => X"{INIT_36}",
INIT_37 => X"{INIT_37}",
INIT_38 => X"{INIT_38}",
INIT_39 => X"{INIT_39}",
INIT_3A => X"{INIT_3A}",
INIT_3B => X"{INIT_3B}",
INIT_3C => X"{INIT_3C}",
INIT_3D => X"{INIT_3D}",
INIT_3E => X"{INIT_3E}",
INIT_3F => X"{INIT_3F}",
INITP_00 => X"{INITP_00}",
INITP_01 => X"{INITP_01}",
INITP_02 => X"{INITP_02}",
INITP_03 => X"{INITP_03}",
INITP_04 => X"{INITP_04}",
INITP_05 => X"{INITP_05}",
INITP_06 => X"{INITP_06}",
INITP_07 => X"{INITP_07}")
--synthesis translate_on
port map( DI => "0000000000000000",
DIP => "00",
EN => '1',
WE => '0',
SSR => '0',
CLK => clk,
ADDR => address,
DO => instruction(15 downto 0),
DOP => instruction(17 downto 16));
--
end low_level_definition;
--
------------------------------------------------------------------------------------
--
-- END OF FILE {name}.vhd
--
------------------------------------------------------------------------------------
| gpl-3.0 |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/if_statement/rule_011_test_input.vhd | 1 | 957 |
architecture RTL of FIFO is
begin
process
begin
if a = '1' then
b <= '0';
elsif c = '1' then
b <= '1';
else
if x = '1' then
z <= '0';
elsif x = '0' then
z <= '1';
else
z <= 'Z';
end if;
end if;
-- Violations below
if a = '1' then
b <= '0';
elsif c = '1' then
b <= '1';
else
if x = '1' then
z <= '0';
elsif x = '0' then
z <= '1';
else
z <= 'Z';
end if;
end if;
-- Check loop statements
if a = '1' then
else
LOOP_LABEL : loop
end loop;
end if;
if a = '1' then
else
loop
end loop;
end if;
if a = '1' then
else
while a = 0
loop
end loop;
end if;
if a = '1' then
else
for i in 0 to 13
loop
end loop;
end if;
end process;
end architecture RTL;
| gpl-3.0 |
rjarzmik/mips_processor | DI/RegisterFile.vhd | 1 | 4023 | -------------------------------------------------------------------------------
-- Title : Register File
-- Project :
-------------------------------------------------------------------------------
-- File : RegisterFile.vhd
-- Author : Robert Jarzmik <[email protected]>
-- Company :
-- Created : 2016-11-12
-- Last update: 2017-01-03
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: MIPS Register File, 32 registers
-------------------------------------------------------------------------------
-- Copyright (c) 2016
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2016-11-12 1.0 rj Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-------------------------------------------------------------------------------
entity RegisterFile is
generic (
DATA_WIDTH : positive := 32;
NB_REGISTERS : positive := 32; -- r0 to r31
NB_REGISTERS_SPECIAL : positive := 2 -- mflo and mfhi
);
port (
clk : in std_logic;
rst : in std_logic;
stall_req : in std_logic;
a_idx : in natural range 0 to NB_REGISTERS + NB_REGISTERS_SPECIAL - 1;
b_idx : in natural range 0 to NB_REGISTERS + NB_REGISTERS_SPECIAL - 1;
-- Writeback register
rwb_reg1_we : in std_logic;
rwb_reg1_idx : in natural range 0 to NB_REGISTERS + NB_REGISTERS_SPECIAL - 1;
rwb_reg1_data : in std_logic_vector(DATA_WIDTH - 1 downto 0);
rwb_reg2_we : in std_logic;
rwb_reg2_idx : in natural range 0 to NB_REGISTERS + NB_REGISTERS_SPECIAL - 1;
rwb_reg2_data : in std_logic_vector(DATA_WIDTH - 1 downto 0);
-- Output read registers, set on clk rising edge
a : out std_logic_vector(DATA_WIDTH - 1 downto 0);
b : out std_logic_vector(DATA_WIDTH - 1 downto 0)
);
end entity RegisterFile;
-------------------------------------------------------------------------------
architecture rtl of RegisterFile is
-----------------------------------------------------------------------------
-- Internal signal declarations
-----------------------------------------------------------------------------
type r_array is array (0 to NB_REGISTERS + NB_REGISTERS_SPECIAL - 1) of
std_logic_vector(DATA_WIDTH -1 downto 0);
signal registers : r_array := (
x"00000000", -- r0
x"00000000",
x"00000000",
x"00000000",
x"00000000",
x"00000000",
x"00000000",
x"00000000",
x"00000000",
x"00000000",
x"00000000",
x"00000000",
x"00000000",
x"00000000",
x"00000000",
x"00000000",
x"00000000",
x"00000000",
x"00000000",
x"00000000",
x"00000000",
x"00000000",
x"00000000",
x"00000000",
x"00000000",
x"00000000",
x"00000000",
x"00000000",
x"00000000",
x"00000000",
x"00000000",
x"00000000",
x"00000000",
x"00000000");
begin -- architecture rtl
-----------------------------------------------------------------------------
-- Component instantiations
-----------------------------------------------------------------------------
process(rst, clk, rwb_reg1_we, rwb_reg2_we)
begin
if rst = '1' then
a <= (others => 'X');
b <= (others => 'X');
elsif rising_edge(clk) then
if rwb_reg1_we = '1' then
registers(rwb_reg1_idx) <= rwb_reg1_data;
end if;
if rwb_reg2_we = '1' then
registers(rwb_reg2_idx) <= rwb_reg2_data;
end if;
if stall_req = '0' then
a <= registers(a_idx);
b <= registers(b_idx);
end if;
end if;
end process;
end architecture rtl;
-------------------------------------------------------------------------------
| gpl-3.0 |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/function/rule_017_test_input.fixed_lower.vhd | 1 | 552 |
architecture RTL of FIFO is
function func1 return integer;
pure function func1 return integer;
impure function func1 return integer;
function func1 return integer is
begin
end function func1;
-- Violations follow
function func1 return integer;
function func1 return integer;
pure function func1 return integer;
pure function func1 return integer;
impure function func1 return integer;
impure function func1 return integer;
-- This should be ignored
function "=" return boolean;
begin
end architecture RTL;
| gpl-3.0 |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/signal/rule_006_test_input.vhd | 1 | 194 |
architecture RTL of FIFO is
signal sig1 : std_logic;
signal sig2 : std_logic;
-- Violations below
signal sig1: std_logic;
signal sig2: std_logic;
begin
end architecture RTL;
| gpl-3.0 |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/process/rule_027_test_input.vhd | 1 | 485 |
architecture RTL of FIFO is
begin
process
variable var1 : integer;
begin
end process;
process (a, b)
variable var1 : integer;
begin
end process;
process is
variable var1 : integer;
begin
end process;
-- Violations below
process
variable var1 : integer;
begin
end process;
process (a, b)
variable var1 : integer;
begin
end process;
process is
variable var1 : integer;
begin
end process;
end architecture RTL;
| gpl-3.0 |
lelongdunet/dspunit | rtl/dspalu_acc.vhd | 2 | 13985 | -- ----------------------------------------------------------------------
-- DspUnit : Advanced So(P)C Sequential Signal Processor
-- Copyright (C) 2007-2010 by Adrien LELONG (www.lelongdunet.com)
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the
-- Free Software Foundation, Inc.,
-- 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
-- ----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.dspalu_pac.all;
use work.dsputil_pac.all;
-------------------------------------------------------------------------------
entity dspalu_acc is
generic (
sig_width : integer := 16;
acc_width : integer := 32;
acc_reduce_width : integer := 32);
port (
--@inputs
a1 : in std_logic_vector((sig_width - 1) downto 0);
b1 : in std_logic_vector((sig_width - 1) downto 0);
a2 : in std_logic_vector((sig_width - 1) downto 0);
b2 : in std_logic_vector((sig_width - 1) downto 0);
clk : in std_logic;
clr_acc : in std_logic;
acc_mode1 : in std_logic_vector((acc_mode_width - 1) downto 0); -- t_acc_mode;
acc_mode2 : in std_logic_vector((acc_mode_width - 1) downto 0); -- t_acc_mode;
alu_select : in std_logic_vector((alu_select_width - 1) downto 0); -- t_alu_select;
cmp_mode : in std_logic_vector((cmp_mode_width - 1) downto 0); -- t_cmp_mode;
cmp_pol : in std_logic;
cmp_store : in std_logic;
chain_acc : in std_logic;
--@outputs
result1 : out std_logic_vector((sig_width - 1) downto 0);
result_acc1 : out std_logic_vector((acc_width - 1) downto 0);
result2 : out std_logic_vector((sig_width - 1) downto 0);
result_acc2 : out std_logic_vector((acc_width - 1) downto 0);
cmp_reg : out std_logic_vector((acc_width - 1) downto 0);
cmp_greater : out std_logic;
cmp_out : out std_logic
);
end dspalu_acc;
--=----------------------------------------------------------------------------
architecture archi_dspalu_acc of dspalu_acc is
-----------------------------------------------------------------------------
-- @constants definition
-----------------------------------------------------------------------------
--=--------------------------------------------------------------------------
--
-- @component declarations
--
-----------------------------------------------------------------------------
--=--------------------------------------------------------------------------
-- @signals definition
-----------------------------------------------------------------------------
signal s_result1 : signed((2*sig_width - 1) downto 0);
signal s_result2 : signed((2*sig_width - 1) downto 0);
signal s_mul_out1 : signed((2*sig_width - 1) downto 0);
signal s_mul_out2 : signed((2*sig_width - 1) downto 0);
signal s_result_acc1 : signed((acc_width - 1) downto 0);
signal s_result_acc2 : signed((acc_width - 1) downto 0);
signal s_back_acc1 : signed((acc_width - 1) downto 0);
signal s_back_acc2 : signed((acc_width - 1) downto 0);
signal s_cmp_reg : signed((acc_width - 1) downto 0);
signal s_cmp_in : signed((acc_width - 1) downto 0);
signal s_cmp_reg_r : unsigned((acc_reduce_width - 2) downto 0);
signal s_cmp_in_r : unsigned((acc_reduce_width - 2) downto 0);
signal s_acc_mode1 : std_logic_vector((acc_mode_width - 1) downto 0); -- t_acc_mode;
signal s_acc_mode2 : std_logic_vector((acc_mode_width - 1) downto 0); -- t_acc_mode;
signal s_acc_mode1_n1 : std_logic_vector((acc_mode_width - 1) downto 0); -- t_acc_mode;
signal s_acc_mode2_n1 : std_logic_vector((acc_mode_width - 1) downto 0); -- t_acc_mode;
signal s_acc_mode1_inreg : std_logic_vector((acc_mode_width - 1) downto 0); -- t_acc_mode;
signal s_acc_mode2_inreg : std_logic_vector((acc_mode_width - 1) downto 0); -- t_acc_mode;
signal s_cmul_acc_mode1 : std_logic_vector((acc_mode_width - 1) downto 0); -- t_acc_mode;
signal s_cmul_acc_mode2 : std_logic_vector((acc_mode_width - 1) downto 0); -- t_acc_mode;
signal s_mul_a1 : std_logic_vector((sig_width - 1) downto 0);
signal s_mul_a2 : std_logic_vector((sig_width - 1) downto 0);
signal s_mul_b1 : std_logic_vector((sig_width - 1) downto 0);
signal s_mul_b2 : std_logic_vector((sig_width - 1) downto 0);
signal s_mul_a1_in : std_logic_vector((sig_width - 1) downto 0);
signal s_mul_a2_in : std_logic_vector((sig_width - 1) downto 0);
signal s_mul_b1_in : std_logic_vector((sig_width - 1) downto 0);
signal s_mul_b2_in : std_logic_vector((sig_width - 1) downto 0);
type t_cmul_state is (cmul_step, cmul_end);
signal s_cmul_state : t_cmul_state;
signal s_cmp_greater : std_logic;
signal s_cmp_greater_inreg : std_logic;
signal s_b2 : std_logic_vector((sig_width - 1) downto 0);
signal s_cmp_store : std_logic;
begin -- archs_dspalu_acc
-----------------------------------------------------------------------------
--
-- @instantiations
--
-----------------------------------------------------------------------------
--=---------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- First accumulator
-------------------------------------------------------------------------------
p_acc1 : process (clk)
variable v_tmp_acc1 : signed((acc_width - 1) downto 0);
begin -- process p_acc
if rising_edge(clk) then -- rising clock edge
if(clr_acc = '1') then
s_result_acc1 <= (others => '0');
else
v_tmp_acc1 := resize(s_result1, acc_width);
-- Accumulation mode
case s_acc_mode1 is
when acc_store =>
s_result_acc1 <= v_tmp_acc1;
when acc_sumstore =>
s_result_acc1 <= resize(signed(s_result1) + signed(s_result2), acc_width);
when acc_add =>
s_result_acc1 <= s_result_acc1 + v_tmp_acc1;
when acc_sub =>
s_result_acc1 <= s_result_acc1 - v_tmp_acc1;
when acc_back_add =>
s_result_acc1 <= s_back_acc1 + v_tmp_acc1;
when acc_minback_sub =>
s_result_acc1 <= - v_tmp_acc1 - s_back_acc1;
when others =>
s_result_acc1 <= (others => '0');
end case;
-- backup of accumulator content
s_back_acc1 <= s_result_acc1;
end if;
end if;
end process p_acc1;
-------------------------------------------------------------------------------
-- Second accumulator
-------------------------------------------------------------------------------
p_acc2 : process (clk)
variable v_tmp_acc2 : signed((acc_width - 1) downto 0);
begin -- process p_acc
if rising_edge(clk) then -- rising clock edge
if(clr_acc = '1') then
s_result_acc2 <= (others => '0');
else
v_tmp_acc2 := resize(s_result2, acc_width);
-- Accumulation mode
case s_acc_mode2 is
when acc_store =>
s_result_acc2 <= v_tmp_acc2;
when acc_diff =>
-- s_result_acc2 <= resize(signed(a2) + signed(b2), acc_width);
s_result_acc2 <= s_result_acc2 - s_result_acc1;
when acc_abs =>
s_result_acc2 <= s_result_acc2 + dsp_abs(s_result_acc1);
when acc_add =>
s_result_acc2 <= s_result_acc2 + v_tmp_acc2;
when acc_sub =>
s_result_acc2 <= s_result_acc2 - v_tmp_acc2;
when acc_back_add =>
s_result_acc2 <= s_back_acc2 + v_tmp_acc2;
when acc_minback_sub =>
s_result_acc2 <= - v_tmp_acc2 - s_back_acc2;
when others =>
s_result_acc2 <= (others => '0');
end case;
-- backup of accumulator content
s_back_acc2 <= s_result_acc2;
end if;
end if;
end process p_acc2;
-------------------------------------------------------------------------------
-- Comparator
-------------------------------------------------------------------------------
-- p_cmp_in : process (cmp_mode, s_result_acc1, s_result_acc2, s_cmp_reg, s_cmp_in)
p_cmp_in : process (clk)
begin -- process p_cmp_in
if rising_edge(clk) then
case cmp_mode is
when cmp_acc1 =>
if(s_result_acc1(acc_width - 1) = '0') then
s_cmp_in <= s_result_acc1;
else
s_cmp_in <= not s_result_acc1;
end if;
when cmp_acc2 =>
if(s_result_acc2(acc_width - 1) = '0') then
s_cmp_in <= s_result_acc2;
else
s_cmp_in <= not s_result_acc2;
end if;
when others =>
s_cmp_in <= (others => '0');
end case;
s_cmp_greater <= s_cmp_greater_inreg;
end if;
end process p_cmp_in;
s_cmp_reg_r <= unsigned(s_cmp_reg((acc_width - 2) downto (acc_width - acc_reduce_width))) ;
s_cmp_in_r <= unsigned(s_cmp_in((acc_width - 2) downto (acc_width - acc_reduce_width)));
s_cmp_greater_inreg <= '1' when s_cmp_reg_r < s_cmp_in_r else '0';
-- s_cmp_greater_inreg <= '1' when s_cmp_reg < s_cmp_in else '0';
p_cmp : process (clk)
begin -- process p_cmp_in
if rising_edge(clk) then -- rising clock edge
s_cmp_store <= cmp_store;
-- if(((s_cmp_greater_inreg xor cmp_pol) or s_cmp_store) = '1') then
if(s_cmp_store = '1') then
s_cmp_reg <= s_cmp_in;
elsif(s_cmp_greater_inreg = '1') then
s_cmp_reg <= s_cmp_in;
else
s_cmp_reg <= s_cmp_reg;
end if;
end if;
end process p_cmp;
-------------------------------------------------------------------------------
-- Operation controller (manage the complex multiplication)
-------------------------------------------------------------------------------
p_alu_ctrl : process (clk)
begin -- process p_alu_ctrl
if rising_edge(clk) then -- rising clock edge
if (alu_select = alu_mul or alu_select = alu_none) then
s_cmul_state <= cmul_end;
elsif (s_cmul_state = cmul_step) then
s_cmul_state <= cmul_end;
else
s_cmul_state <= cmul_step;
end if;
end if;
end process p_alu_ctrl;
p_mul_reg : process (clk)
begin -- process p_mul_reg
if rising_edge(clk) then -- rising clock edge
s_result1 <= s_mul_out1;
s_result2 <= s_mul_out2;
s_acc_mode1 <= s_acc_mode1_n1;
s_acc_mode2 <= s_acc_mode2_n1;
s_acc_mode1_n1 <= s_acc_mode1_inreg;
s_acc_mode2_n1 <= s_acc_mode2_inreg;
end if;
end process p_mul_reg;
--=---------------------------------------------------------------------------
--
-- @concurrent signal assignments
--
-----------------------------------------------------------------------------
result1 <= std_logic_vector(s_result1((2*sig_width - 2) downto (sig_width - 1)));
result2 <= std_logic_vector(s_result2((2*sig_width - 2) downto (sig_width - 1)));
s_mul_out1 <= signed(s_mul_a1) * signed(s_mul_b1);
s_mul_out2 <= signed(s_mul_a2) * signed(s_mul_b2);
result_acc1 <= std_logic_vector(s_result_acc1);
result_acc2 <= std_logic_vector(s_result_acc2);
-- accumulation mode is given by acc_modex except during complex multiplication (modified for step 2)
s_cmul_acc_mode1 <= acc_add when acc_mode1 = acc_sub else acc_sub;
s_cmul_acc_mode2 <= acc_sub when acc_mode1 = acc_sub else acc_add;
-- TODO move the mux to s_acc_modeX_n1!!!!
s_acc_mode1_inreg <= s_cmul_acc_mode1 when s_cmul_state = cmul_step else acc_mode1;
s_acc_mode2_inreg <= s_cmul_acc_mode2 when s_cmul_state = cmul_step else acc_mode2;
-- multipliers inputs (special selection during complex multiplication)
p_mul_in_reg : process (clk)
begin -- process p_mul_reg
if rising_edge(clk) then -- rising clock edge
s_mul_a1 <= s_mul_a1_in;
s_mul_a2 <= s_mul_a2_in;
s_mul_b1 <= s_mul_b1_in;
s_mul_b2 <= s_mul_b2_in;
end if;
end process p_mul_in_reg;
s_mul_a1_in <= a2 when s_cmul_state = cmul_step else a1;
s_mul_a2_in <= a1 when s_cmul_state = cmul_step else a2;
s_mul_b1_in <= s_b2 when s_cmul_state = cmul_step else b1;
-- ! can be more time critical than other entries because depends on alu_select
s_mul_b2_in <= b1 when (s_cmul_state = cmul_end and (alu_select = alu_cmul or alu_select = alu_cmul_conj)) else s_b2;
-- ------------------------------------------------------------------------------------------------------------------------
s_b2 <= std_logic_vector(-signed(b2)) when alu_select = alu_cmul_conj else b2;
cmp_reg <= std_logic_vector(s_cmp_reg);
cmp_greater <= s_cmp_greater;
end archi_dspalu_acc;
-------------------------------------------------------------------------------
| gpl-3.0 |
lelongdunet/dspunit | sim/bench_cpcomplex.vhd | 2 | 12144 | -- ----------------------------------------------------------------------
-- DspUnit : Advanced So(P)C Sequential Signal Processor
-- Copyright (C) 2007-2010 by Adrien LELONG (www.lelongdunet.com)
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the
-- Free Software Foundation, Inc.,
-- 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
-- ----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.dspunit_pac.all;
-------------------------------------------------------------------------------
entity bench_cpcomplex is
end bench_cpcomplex;
--=----------------------------------------------------------------------------
architecture archi_bench_cpcomplex of bench_cpcomplex is
-----------------------------------------------------------------------------
-- @constants definition
-----------------------------------------------------------------------------
--=--------------------------------------------------------------------------
--
-- @component declarations
--
-----------------------------------------------------------------------------
component dspunit
port (
clk : in std_logic;
clk_cpu : in std_logic;
reset : in std_logic;
data_in_m0 : in std_logic_vector((sig_width - 1) downto 0);
data_out_m0 : out std_logic_vector((sig_width - 1) downto 0);
addr_r_m0 : out std_logic_vector((cmdreg_width - 1) downto 0);
addr_w_m0 : out std_logic_vector((cmdreg_width - 1) downto 0);
wr_en_m0 : out std_logic;
c_en_m0 : out std_logic;
data_in_m1 : in std_logic_vector((sig_width - 1) downto 0);
data_out_m1 : out std_logic_vector((sig_width - 1) downto 0);
addr_m1 : out std_logic_vector((cmdreg_width - 1) downto 0);
wr_en_m1 : out std_logic;
c_en_m1 : out std_logic;
data_in_m2 : in std_logic_vector((sig_width - 1) downto 0);
data_out_m2 : out std_logic_vector((sig_width - 1) downto 0);
addr_m2 : out std_logic_vector((cmdreg_width - 1) downto 0);
wr_en_m2 : out std_logic;
c_en_m2 : out std_logic;
addr_cmdreg : in std_logic_vector((cmdreg_addr_width - 1) downto 0);
data_in_cmdreg : in std_logic_vector((cmdreg_data_width - 1) downto 0);
wr_en_cmdreg : in std_logic;
data_out_cmdreg : out std_logic_vector((cmdreg_data_width - 1) downto 0);
debug : out std_logic_vector(15 downto 0);
irq : out std_logic;
op_done : out std_logic
);
end component;
component gen_memoryf
generic (
addr_width : natural;
data_width : natural;
init_file : string
);
port (
address_a : in std_logic_vector((addr_width - 1) downto 0);
address_b : in std_logic_vector((addr_width - 1) downto 0);
clock_a : in std_logic;
clock_b : in std_logic;
data_a : in std_logic_vector((data_width - 1) downto 0);
data_b : in std_logic_vector((data_width - 1) downto 0);
wren_a : in std_logic;
wren_b : in std_logic;
q_a : out std_logic_vector((data_width - 1) downto 0);
q_b : out std_logic_vector((data_width - 1) downto 0)
);
end component;
component gen_memory
generic (
addr_width : natural;
data_width : natural
);
port (
address_a : in std_logic_vector((addr_width - 1) downto 0);
address_b : in std_logic_vector((addr_width - 1) downto 0);
clock_a : in std_logic;
clock_b : in std_logic;
data_a : in std_logic_vector((data_width - 1) downto 0);
data_b : in std_logic_vector((data_width - 1) downto 0);
wren_a : in std_logic;
wren_b : in std_logic;
q_a : out std_logic_vector((data_width - 1) downto 0);
q_b : out std_logic_vector((data_width - 1) downto 0)
);
end component;
component clock_gen
generic (
tpw : time;
tps : time
);
port (
clk : out std_logic;
reset : out std_logic
);
end component;
--=--------------------------------------------------------------------------
-- @signals definition
-----------------------------------------------------------------------------
signal s_clk : std_logic;
signal s_reset : std_logic;
signal s_data_in_m0 : std_logic_vector((sig_width - 1) downto 0);
signal s_data_out_m0 : std_logic_vector((sig_width - 1) downto 0);
signal s_addr_r_m0 : std_logic_vector((cmdreg_width - 1) downto 0);
signal s_addr_w_m0 : std_logic_vector((cmdreg_width - 1) downto 0);
signal s_wr_en_m0 : std_logic;
signal s_c_en_m0 : std_logic;
signal s_data_in_m1 : std_logic_vector((sig_width - 1) downto 0);
signal s_data_out_m1 : std_logic_vector((sig_width - 1) downto 0);
signal s_addr_m1 : std_logic_vector((cmdreg_width - 1) downto 0);
signal s_wr_en_m1 : std_logic;
signal s_c_en_m1 : std_logic;
signal s_data_in_m2 : std_logic_vector((sig_width - 1) downto 0);
signal s_data_out_m2 : std_logic_vector((sig_width - 1) downto 0);
signal s_addr_m2 : std_logic_vector((cmdreg_width - 1) downto 0);
signal s_wr_en_m2 : std_logic;
signal s_c_en_m2 : std_logic;
signal s_addr_cmdreg : std_logic_vector((cmdreg_addr_width - 1) downto 0);
signal s_data_in_cmdreg : std_logic_vector((cmdreg_data_width - 1) downto 0);
signal s_wr_en_cmdreg : std_logic;
signal s_data_out_cmdreg : std_logic_vector((cmdreg_data_width - 1) downto 0);
signal s_op_done : std_logic;
signal s_debug_dsp : std_logic_vector(15 downto 0);
signal s_irq : std_logic;
begin -- archs_bench_cpcomplex
-----------------------------------------------------------------------------
--
-- @instantiations
--
-----------------------------------------------------------------------------
dspunit_1 : dspunit
port map (
clk => s_clk,
clk_cpu => s_clk,
reset => s_reset,
data_in_m0 => s_data_in_m0,
data_out_m0 => s_data_out_m0,
addr_r_m0 => s_addr_r_m0,
addr_w_m0 => s_addr_w_m0,
wr_en_m0 => s_wr_en_m0,
c_en_m0 => s_c_en_m0,
data_in_m1 => s_data_in_m1,
data_out_m1 => s_data_out_m1,
addr_m1 => s_addr_m1,
wr_en_m1 => s_wr_en_m1,
c_en_m1 => s_c_en_m1,
data_in_m2 => s_data_in_m2,
data_out_m2 => s_data_out_m2,
addr_m2 => s_addr_m2,
wr_en_m2 => s_wr_en_m2,
c_en_m2 => s_c_en_m2,
addr_cmdreg => s_addr_cmdreg,
data_in_cmdreg => s_data_in_cmdreg,
wr_en_cmdreg => s_wr_en_cmdreg,
data_out_cmdreg => s_data_out_cmdreg,
debug => s_debug_dsp,
irq => s_irq,
op_done => s_op_done);
gen_memory_1 : gen_memoryf
generic map (
addr_width => 16,
data_width => 16,
-- init_file => "exsig.mif")
init_file => "exsig_fft.mif")
-- init_file => "Ones.mif")
port map (
address_a => s_addr_r_m0,
address_b => s_addr_w_m0,
clock_a => s_clk,
clock_b => s_clk,
data_a => (others => '0'),
data_b => s_data_out_m0,
wren_a => '0',
wren_b => s_wr_en_m0,
q_a => s_data_in_m0,
q_b => open);
gen_memory_2 : gen_memoryf
generic map (
addr_width => 16,
data_width => 16,
init_file => "exsig_fft.mif")
port map (
address_a => s_addr_m1,
address_b => (others => '0'),
clock_a => s_clk,
clock_b => s_clk,
data_a => s_data_out_m1,
data_b => (others => '0'),
wren_a => s_wr_en_m1,
wren_b => '0',
q_a => s_data_in_m1,
q_b => open);
gen_memory_3 : gen_memory
generic map (
addr_width => 16,
data_width => 16)
port map (
address_a => s_addr_m2,
address_b => (others => '0'),
clock_a => s_clk,
clock_b => s_clk,
data_a => s_data_out_m2,
data_b => (others => '0'),
wren_a => s_wr_en_m2,
wren_b => '0',
q_a => s_data_in_m2,
q_b => open);
clock_gen_1 : clock_gen
generic map (
tpw => 5 ns,
tps => 0 ns)
port map (
clk => s_clk,
reset => s_reset);
--=---------------------------------------------------------------------------
--=---------------------------------------------------------------------------
--
-- @concurrent signal assignments
--
-----------------------------------------------------------------------------
s_addr_cmdreg <= "000000", "000100" after 141 ns, "000010" after 151 ns, "000111" after 161 ns, "001000" after 171 ns,
-- "000010" after 8751 ns, "000111" after 8761 ns, "001000" after 8771 ns,
"000100" after 8741 ns, "000010" after 8751 ns, "000111" after 8761 ns, "001000" after 8771 ns,
"000001" after 11321 ns,
"000010" after 11341 ns, "000100" after 11351 ns, "000111" after 11361 ns, "001000" after 11371 ns,
"000100" after 19861 ns, "000010" after 19871 ns, "000111" after 19881 ns, "001000" after 19891 ns,
"000010" after 22341 ns, "000100" after 22351 ns, "000111" after 22361 ns, "001000" after 22371 ns,
"000100" after 30861 ns, "000010" after 30871 ns, "000111" after 30881 ns, "001000" after 30891 ns;
s_data_in_cmdreg <= x"0000", x"003F" after 141 ns, x"003F" after 151 ns, x"0464" after 161 ns, x"0002" after 171 ns, -- cp m0->m1
-- x"003F" after 8751 ns, x"002D" after 8761 ns, x"0002" after 8771 ns, -- dotcmul bitrev
x"0072" after 8741 ns, x"0080" after 8751 ns, x"0026" after 8761 ns, x"0002" after 8771 ns, -- sigshift bitrev
x"0080" after 11321 ns,
x"0040" after 11341 ns, x"000F" after 11351 ns, x"000C" after 11361 ns, x"0002" after 11371 ns, -- fft
x"0040" after 19861 ns, x"0040" after 19871 ns, x"000D" after 19881 ns, x"0002" after 19891 ns, -- dotcmul
x"0040" after 22341 ns, x"000A" after 22351 ns, x"003C" after 22361 ns, x"0002" after 22371 ns, -- ifft bitrev
x"0040" after 30861 ns, x"0040" after 30871 ns, x"002D" after 30881 ns, x"0002" after 30891 ns; -- dotcmul bitrev
s_wr_en_cmdreg <= '0', '1' after 141 ns, '0' after 181 ns,
'1' after 8741 ns, '0' after 8781 ns,
'1' after 11321 ns, '0' after 11331 ns,
'1' after 11341 ns, '0' after 11381 ns,
'1' after 19861 ns, '0' after 19901 ns,
'1' after 22341 ns, '0' after 22381 ns,
'1' after 30861 ns, '0' after 30901 ns;
end archi_bench_cpcomplex;
-------------------------------------------------------------------------------
-- Simulation parameters
-->SIMSTOPTIME=5000ns
-->SIMSAVFILE=debugfft.sav
-------------------------------------------------------------------------------
| gpl-3.0 |
michaelmiehling/A25_VME_TB | 16x010-00_src/Source/modelsim_lib.vhd | 1 | 4385 | --------------------------------------------------------------------------------
-- Title : ModelSim library for Riviera-PRO
-- Project :
--------------------------------------------------------------------------------
-- File : modelsim_lib.vhd
-- Author : M. Henze
-- Email :
-- Organization: MEN Mikro Elektronik Nuremberg GmbH
-- Created :
--------------------------------------------------------------------------------
-- Simulator : Riviera-PRO
-- Synthesis :
--------------------------------------------------------------------------------
-- Description :
-- CAUTION - this file shall not be used for new designs. It is only kept
-- for compliance with old designs.
-- For new designs use VHDL2008 syntax instead.
--
--------------------------------------------------------------------------------
-- Hierarchy :
--------------------------------------------------------------------------------
-- Copyright (C) 2016, MEN Mikro Elektronik Nuremberg GmbH
--
-- All rights reserved. Reproduction in whole or part is
-- prohibited without the written permission of the
-- copyright owner.
--------------------------------------------------------------------------------
LIBRARY aldec;
USE aldec.signal_agent_pkg.ALL;
USE aldec.aldec_tools.ALL;
----------------------------------------
-- CAUTION! Don't use for new designs!
-- Use VHDL2008 instead!
----------------------------------------
PACKAGE util IS
TYPE force_type IS (default, deposit, drive, freeze);
type del_mode is (MTI_INERTIAL, MTI_TRANSPORT);
PROCEDURE init_signal_spy( source : IN string;
destination : IN string;
verbose : IN integer;
control : IN integer);
procedure init_signal_spy(
source : in string;
dest : in string
);
PROCEDURE signal_force( destination : IN string;
value : IN string;
rel_time : IN time;
forcetype : IN force_type;
cancel_period : IN time;
verbose : IN integer);
PROCEDURE signal_release( destination : IN string;
verbose : IN integer);
procedure init_signal_driver(
src_obj : in string;
dest_obj : in string;
delay : in time;
delay_type : in del_mode;
verbose : in integer
);
END;
PACKAGE BODY util IS
PROCEDURE init_signal_spy( source : IN string;
destination : IN string;
verbose : IN integer;
control : IN integer) IS
BEGIN
signal_agent(source, destination ,verbose);
END PROCEDURE init_signal_spy;
procedure init_signal_spy(
source : in string;
dest : in string
) is
begin
signal_agent(source,dest,0);
end procedure init_signal_spy;
PROCEDURE signal_force( destination : IN string;
value : IN string;
rel_time : IN time;
forcetype : IN force_type;
cancel_period : IN time;
verbose : IN integer) IS
BEGIN
------------------------------------------------
-- in RivieraPRO2014 the force command changed
------------------------------------------------
--force(force_type'image(forcetype), destination, value);
force_signal(force_type'image(forcetype), destination, value);
END PROCEDURE signal_force;
PROCEDURE signal_release( destination : IN string;
verbose : IN integer) IS
BEGIN
------------------------------------------------
-- in RivieraPRO2014 the force command changed
------------------------------------------------
--noforce ( destination );
noforce_signal ( destination );
END PROCEDURE signal_release;
procedure init_signal_driver(
src_obj : in string;
dest_obj : in string;
delay : in time;
delay_type : in del_mode;
verbose : in integer
) is
begin
signal_agent(src_obj, dest_obj, 0);
end procedure init_signal_driver;
END;
| gpl-3.0 |
hsnuonly/PikachuVolleyFPGA | VGA.ip_user_files/ip/bg_rp/bg_rp_stub.vhdl | 2 | 1352 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Fri Jan 13 17:31:20 2017
-- Host : KLight-PC running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub D:/Document/Verilog/VGA/VGA.srcs/sources_1/ip/bg_rp/bg_rp_stub.vhdl
-- Design : bg_rp
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7a35tcpg236-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity bg_rp is
Port (
clka : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 7 downto 0 );
dina : in STD_LOGIC_VECTOR ( 11 downto 0 );
douta : out STD_LOGIC_VECTOR ( 11 downto 0 )
);
end bg_rp;
architecture stub of bg_rp is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "clka,wea[0:0],addra[7:0],dina[11:0],douta[11:0]";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "blk_mem_gen_v8_3_5,Vivado 2016.4";
begin
end;
| gpl-3.0 |
hsnuonly/PikachuVolleyFPGA | VGA.srcs/sources_1/ip/bg_rp/synth/bg_rp.vhd | 1 | 14247 | -- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:blk_mem_gen:8.3
-- IP Revision: 5
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY blk_mem_gen_v8_3_5;
USE blk_mem_gen_v8_3_5.blk_mem_gen_v8_3_5;
ENTITY bg_rp IS
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(11 DOWNTO 0)
);
END bg_rp;
ARCHITECTURE bg_rp_arch OF bg_rp IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF bg_rp_arch: ARCHITECTURE IS "yes";
COMPONENT blk_mem_gen_v8_3_5 IS
GENERIC (
C_FAMILY : STRING;
C_XDEVICEFAMILY : STRING;
C_ELABORATION_DIR : STRING;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_AXI_SLAVE_TYPE : INTEGER;
C_USE_BRAM_BLOCK : INTEGER;
C_ENABLE_32BIT_ADDRESS : INTEGER;
C_CTRL_ECC_ALGO : STRING;
C_HAS_AXI_ID : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_MEM_TYPE : INTEGER;
C_BYTE_SIZE : INTEGER;
C_ALGORITHM : INTEGER;
C_PRIM_TYPE : INTEGER;
C_LOAD_INIT_FILE : INTEGER;
C_INIT_FILE_NAME : STRING;
C_INIT_FILE : STRING;
C_USE_DEFAULT_DATA : INTEGER;
C_DEFAULT_DATA : STRING;
C_HAS_RSTA : INTEGER;
C_RST_PRIORITY_A : STRING;
C_RSTRAM_A : INTEGER;
C_INITA_VAL : STRING;
C_HAS_ENA : INTEGER;
C_HAS_REGCEA : INTEGER;
C_USE_BYTE_WEA : INTEGER;
C_WEA_WIDTH : INTEGER;
C_WRITE_MODE_A : STRING;
C_WRITE_WIDTH_A : INTEGER;
C_READ_WIDTH_A : INTEGER;
C_WRITE_DEPTH_A : INTEGER;
C_READ_DEPTH_A : INTEGER;
C_ADDRA_WIDTH : INTEGER;
C_HAS_RSTB : INTEGER;
C_RST_PRIORITY_B : STRING;
C_RSTRAM_B : INTEGER;
C_INITB_VAL : STRING;
C_HAS_ENB : INTEGER;
C_HAS_REGCEB : INTEGER;
C_USE_BYTE_WEB : INTEGER;
C_WEB_WIDTH : INTEGER;
C_WRITE_MODE_B : STRING;
C_WRITE_WIDTH_B : INTEGER;
C_READ_WIDTH_B : INTEGER;
C_WRITE_DEPTH_B : INTEGER;
C_READ_DEPTH_B : INTEGER;
C_ADDRB_WIDTH : INTEGER;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER;
C_MUX_PIPELINE_STAGES : INTEGER;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER;
C_USE_SOFTECC : INTEGER;
C_USE_ECC : INTEGER;
C_EN_ECC_PIPE : INTEGER;
C_HAS_INJECTERR : INTEGER;
C_SIM_COLLISION_CHECK : STRING;
C_COMMON_CLK : INTEGER;
C_DISABLE_WARN_BHV_COLL : INTEGER;
C_EN_SLEEP_PIN : INTEGER;
C_USE_URAM : INTEGER;
C_EN_RDADDRA_CHG : INTEGER;
C_EN_RDADDRB_CHG : INTEGER;
C_EN_DEEPSLEEP_PIN : INTEGER;
C_EN_SHUTDOWN_PIN : INTEGER;
C_EN_SAFETY_CKT : INTEGER;
C_DISABLE_WARN_BHV_RANGE : INTEGER;
C_COUNT_36K_BRAM : STRING;
C_COUNT_18K_BRAM : STRING;
C_EST_POWER_SUMMARY : STRING
);
PORT (
clka : IN STD_LOGIC;
rsta : IN STD_LOGIC;
ena : IN STD_LOGIC;
regcea : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
clkb : IN STD_LOGIC;
rstb : IN STD_LOGIC;
enb : IN STD_LOGIC;
regceb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
injectsbiterr : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
eccpipece : IN STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
rdaddrecc : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
sleep : IN STD_LOGIC;
deepsleep : IN STD_LOGIC;
shutdown : IN STD_LOGIC;
rsta_busy : OUT STD_LOGIC;
rstb_busy : OUT STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
s_axi_injectsbiterr : IN STD_LOGIC;
s_axi_injectdbiterr : IN STD_LOGIC;
s_axi_sbiterr : OUT STD_LOGIC;
s_axi_dbiterr : OUT STD_LOGIC;
s_axi_rdaddrecc : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT blk_mem_gen_v8_3_5;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF bg_rp_arch: ARCHITECTURE IS "blk_mem_gen_v8_3_5,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF bg_rp_arch : ARCHITECTURE IS "bg_rp,blk_mem_gen_v8_3_5,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF bg_rp_arch: ARCHITECTURE IS "bg_rp,blk_mem_gen_v8_3_5,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=blk_mem_gen,x_ipVersion=8.3,x_ipCoreRevision=5,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=artix7,C_XDEVICEFAMILY=artix7,C_ELABORATION_DIR=./,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_AXI_SLAVE_TYPE=0,C_USE_BRAM_BLOCK=0,C_ENABLE_32BIT_ADDRESS=0,C_CTRL_ECC_ALGO=NONE,C_HAS_AXI_ID=0,C_AXI_ID_WIDTH=4,C_MEM_TYPE=0,C_BYTE_SIZE=9,C_ALGORITHM=1,C_PRIM_TYPE=1,C_LOAD_INIT_FILE=1,C_INIT_FILE_NAME=bg_rp.mif,C_I" &
"NIT_FILE=bg_rp.mem,C_USE_DEFAULT_DATA=0,C_DEFAULT_DATA=0,C_HAS_RSTA=0,C_RST_PRIORITY_A=CE,C_RSTRAM_A=0,C_INITA_VAL=0,C_HAS_ENA=0,C_HAS_REGCEA=0,C_USE_BYTE_WEA=0,C_WEA_WIDTH=1,C_WRITE_MODE_A=WRITE_FIRST,C_WRITE_WIDTH_A=12,C_READ_WIDTH_A=12,C_WRITE_DEPTH_A=156,C_READ_DEPTH_A=156,C_ADDRA_WIDTH=8,C_HAS_RSTB=0,C_RST_PRIORITY_B=CE,C_RSTRAM_B=0,C_INITB_VAL=0,C_HAS_ENB=0,C_HAS_REGCEB=0,C_USE_BYTE_WEB=0,C_WEB_WIDTH=1,C_WRITE_MODE_B=WRITE_FIRST,C_WRITE_WIDTH_B=12,C_READ_WIDTH_B=12,C_WRITE_DEPTH_B=156,C_RE" &
"AD_DEPTH_B=156,C_ADDRB_WIDTH=8,C_HAS_MEM_OUTPUT_REGS_A=1,C_HAS_MEM_OUTPUT_REGS_B=0,C_HAS_MUX_OUTPUT_REGS_A=0,C_HAS_MUX_OUTPUT_REGS_B=0,C_MUX_PIPELINE_STAGES=0,C_HAS_SOFTECC_INPUT_REGS_A=0,C_HAS_SOFTECC_OUTPUT_REGS_B=0,C_USE_SOFTECC=0,C_USE_ECC=0,C_EN_ECC_PIPE=0,C_HAS_INJECTERR=0,C_SIM_COLLISION_CHECK=ALL,C_COMMON_CLK=0,C_DISABLE_WARN_BHV_COLL=0,C_EN_SLEEP_PIN=0,C_USE_URAM=0,C_EN_RDADDRA_CHG=0,C_EN_RDADDRB_CHG=0,C_EN_DEEPSLEEP_PIN=0,C_EN_SHUTDOWN_PIN=0,C_EN_SAFETY_CKT=0,C_DISABLE_WARN_BHV_RANGE=0" &
",C_COUNT_36K_BRAM=0,C_COUNT_18K_BRAM=1,C_EST_POWER_SUMMARY=Estimated Power for IP _ 2.70645 mW}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clka: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
ATTRIBUTE X_INTERFACE_INFO OF wea: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA WE";
ATTRIBUTE X_INTERFACE_INFO OF addra: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
ATTRIBUTE X_INTERFACE_INFO OF dina: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN";
ATTRIBUTE X_INTERFACE_INFO OF douta: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT";
BEGIN
U0 : blk_mem_gen_v8_3_5
GENERIC MAP (
C_FAMILY => "artix7",
C_XDEVICEFAMILY => "artix7",
C_ELABORATION_DIR => "./",
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_AXI_SLAVE_TYPE => 0,
C_USE_BRAM_BLOCK => 0,
C_ENABLE_32BIT_ADDRESS => 0,
C_CTRL_ECC_ALGO => "NONE",
C_HAS_AXI_ID => 0,
C_AXI_ID_WIDTH => 4,
C_MEM_TYPE => 0,
C_BYTE_SIZE => 9,
C_ALGORITHM => 1,
C_PRIM_TYPE => 1,
C_LOAD_INIT_FILE => 1,
C_INIT_FILE_NAME => "bg_rp.mif",
C_INIT_FILE => "bg_rp.mem",
C_USE_DEFAULT_DATA => 0,
C_DEFAULT_DATA => "0",
C_HAS_RSTA => 0,
C_RST_PRIORITY_A => "CE",
C_RSTRAM_A => 0,
C_INITA_VAL => "0",
C_HAS_ENA => 0,
C_HAS_REGCEA => 0,
C_USE_BYTE_WEA => 0,
C_WEA_WIDTH => 1,
C_WRITE_MODE_A => "WRITE_FIRST",
C_WRITE_WIDTH_A => 12,
C_READ_WIDTH_A => 12,
C_WRITE_DEPTH_A => 156,
C_READ_DEPTH_A => 156,
C_ADDRA_WIDTH => 8,
C_HAS_RSTB => 0,
C_RST_PRIORITY_B => "CE",
C_RSTRAM_B => 0,
C_INITB_VAL => "0",
C_HAS_ENB => 0,
C_HAS_REGCEB => 0,
C_USE_BYTE_WEB => 0,
C_WEB_WIDTH => 1,
C_WRITE_MODE_B => "WRITE_FIRST",
C_WRITE_WIDTH_B => 12,
C_READ_WIDTH_B => 12,
C_WRITE_DEPTH_B => 156,
C_READ_DEPTH_B => 156,
C_ADDRB_WIDTH => 8,
C_HAS_MEM_OUTPUT_REGS_A => 1,
C_HAS_MEM_OUTPUT_REGS_B => 0,
C_HAS_MUX_OUTPUT_REGS_A => 0,
C_HAS_MUX_OUTPUT_REGS_B => 0,
C_MUX_PIPELINE_STAGES => 0,
C_HAS_SOFTECC_INPUT_REGS_A => 0,
C_HAS_SOFTECC_OUTPUT_REGS_B => 0,
C_USE_SOFTECC => 0,
C_USE_ECC => 0,
C_EN_ECC_PIPE => 0,
C_HAS_INJECTERR => 0,
C_SIM_COLLISION_CHECK => "ALL",
C_COMMON_CLK => 0,
C_DISABLE_WARN_BHV_COLL => 0,
C_EN_SLEEP_PIN => 0,
C_USE_URAM => 0,
C_EN_RDADDRA_CHG => 0,
C_EN_RDADDRB_CHG => 0,
C_EN_DEEPSLEEP_PIN => 0,
C_EN_SHUTDOWN_PIN => 0,
C_EN_SAFETY_CKT => 0,
C_DISABLE_WARN_BHV_RANGE => 0,
C_COUNT_36K_BRAM => "0",
C_COUNT_18K_BRAM => "1",
C_EST_POWER_SUMMARY => "Estimated Power for IP : 2.70645 mW"
)
PORT MAP (
clka => clka,
rsta => '0',
ena => '0',
regcea => '0',
wea => wea,
addra => addra,
dina => dina,
douta => douta,
clkb => '0',
rstb => '0',
enb => '0',
regceb => '0',
web => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
addrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
dinb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 12)),
injectsbiterr => '0',
injectdbiterr => '0',
eccpipece => '0',
sleep => '0',
deepsleep => '0',
shutdown => '0',
s_aclk => '0',
s_aresetn => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awvalid => '0',
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 12)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wlast => '0',
s_axi_wvalid => '0',
s_axi_bready => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arvalid => '0',
s_axi_rready => '0',
s_axi_injectsbiterr => '0',
s_axi_injectdbiterr => '0'
);
END bg_rp_arch;
| gpl-3.0 |
hsnuonly/PikachuVolleyFPGA | VGA.srcs/sources_1/ip/crash_pixel/crash_pixel_stub.vhdl | 2 | 1407 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Fri Jan 13 17:35:17 2017
-- Host : KLight-PC running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub
-- D:/Document/Verilog/VGA/VGA.srcs/sources_1/ip/crash_pixel/crash_pixel_stub.vhdl
-- Design : crash_pixel
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7a35tcpg236-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity crash_pixel is
Port (
clka : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
dina : in STD_LOGIC_VECTOR ( 11 downto 0 );
douta : out STD_LOGIC_VECTOR ( 11 downto 0 )
);
end crash_pixel;
architecture stub of crash_pixel is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "clka,wea[0:0],addra[11:0],dina[11:0],douta[11:0]";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "blk_mem_gen_v8_3_5,Vivado 2016.4";
begin
end;
| gpl-3.0 |
hsnuonly/PikachuVolleyFPGA | VGA.srcs/sources_1/ip/bg_mid/misc/blk_mem_gen_v8_3.vhd | 45 | 8325 | library ieee;
use ieee.std_logic_1164.all;
entity blk_mem_gen_v8_3_5 is
generic (
C_FAMILY : string := "virtex7";
C_XDEVICEFAMILY : string := "virtex7";
C_ELABORATION_DIR : string := "";
C_INTERFACE_TYPE : integer := 0;
C_AXI_TYPE : integer := 1;
C_AXI_SLAVE_TYPE : integer := 0;
C_USE_BRAM_BLOCK : integer := 0;
C_ENABLE_32BIT_ADDRESS : integer := 0;
C_CTRL_ECC_ALGO : string := "ECCHSIAO32-7";
C_HAS_AXI_ID : integer := 0;
C_AXI_ID_WIDTH : integer := 4;
C_MEM_TYPE : integer := 2;
C_BYTE_SIZE : integer := 9;
C_ALGORITHM : integer := 0;
C_PRIM_TYPE : integer := 3;
C_LOAD_INIT_FILE : integer := 0;
C_INIT_FILE_NAME : string := "no_coe_file_loaded";
C_INIT_FILE : string := "no_mem_file_loaded";
C_USE_DEFAULT_DATA : integer := 0;
C_DEFAULT_DATA : string := "0";
C_HAS_RSTA : integer := 0;
C_RST_PRIORITY_A : string := "ce";
C_RSTRAM_A : integer := 0;
C_INITA_VAL : string := "0";
C_HAS_ENA : integer := 1;
C_HAS_REGCEA : integer := 0;
C_USE_BYTE_WEA : integer := 0;
C_WEA_WIDTH : integer := 1;
C_WRITE_MODE_A : string := "WRITE_FIRST";
C_WRITE_WIDTH_A : integer := 9;
C_READ_WIDTH_A : integer := 9;
C_WRITE_DEPTH_A : integer := 2048;
C_READ_DEPTH_A : integer := 2048;
C_ADDRA_WIDTH : integer := 11;
C_HAS_RSTB : integer := 0;
C_RST_PRIORITY_B : string := "ce";
C_RSTRAM_B : integer := 0;
C_INITB_VAL : string := "0";
C_HAS_ENB : integer := 1;
C_HAS_REGCEB : integer := 0;
C_USE_BYTE_WEB : integer := 0;
C_WEB_WIDTH : integer := 1;
C_WRITE_MODE_B : string := "WRITE_FIRST";
C_WRITE_WIDTH_B : integer := 9;
C_READ_WIDTH_B : integer := 9;
C_WRITE_DEPTH_B : integer := 2048;
C_READ_DEPTH_B : integer := 2048;
C_ADDRB_WIDTH : integer := 11;
C_HAS_MEM_OUTPUT_REGS_A : integer := 0;
C_HAS_MEM_OUTPUT_REGS_B : integer := 0;
C_HAS_MUX_OUTPUT_REGS_A : integer := 0;
C_HAS_MUX_OUTPUT_REGS_B : integer := 0;
C_MUX_PIPELINE_STAGES : integer := 0;
C_HAS_SOFTECC_INPUT_REGS_A : integer := 0;
C_HAS_SOFTECC_OUTPUT_REGS_B : integer := 0;
C_USE_SOFTECC : integer := 0;
C_USE_ECC : integer := 0;
C_EN_ECC_PIPE : integer := 0;
C_HAS_INJECTERR : integer := 0;
C_SIM_COLLISION_CHECK : string := "none";
C_COMMON_CLK : integer := 0;
C_DISABLE_WARN_BHV_COLL : integer := 0;
C_EN_SLEEP_PIN : integer := 0;
C_USE_URAM : integer := 0;
C_EN_RDADDRA_CHG : integer := 0;
C_EN_RDADDRB_CHG : integer := 0;
C_EN_DEEPSLEEP_PIN : integer := 0;
C_EN_SHUTDOWN_PIN : integer := 0;
C_EN_SAFETY_CKT : integer := 0;
C_DISABLE_WARN_BHV_RANGE : integer := 0;
C_COUNT_36K_BRAM : string := "";
C_COUNT_18K_BRAM : string := "";
C_EST_POWER_SUMMARY : string := ""
);
port (
clka : in std_logic := '0';
rsta : in std_logic := '0';
ena : in std_logic := '0';
regcea : in std_logic := '0';
wea : in std_logic_vector(c_wea_width - 1 downto 0) := (others => '0');
addra : in std_logic_vector(c_addra_width - 1 downto 0) := (others => '0');
dina : in std_logic_vector(c_write_width_a - 1 downto 0) := (others => '0');
douta : out std_logic_vector(c_read_width_a - 1 downto 0);
clkb : in std_logic := '0';
rstb : in std_logic := '0';
enb : in std_logic := '0';
regceb : in std_logic := '0';
web : in std_logic_vector(c_web_width - 1 downto 0) := (others => '0');
addrb : in std_logic_vector(c_addrb_width - 1 downto 0) := (others => '0');
dinb : in std_logic_vector(c_write_width_b - 1 downto 0) := (others => '0');
doutb : out std_logic_vector(c_read_width_b - 1 downto 0);
injectsbiterr : in std_logic := '0';
injectdbiterr : in std_logic := '0';
eccpipece : in std_logic := '0';
sbiterr : out std_logic;
dbiterr : out std_logic;
rdaddrecc : out std_logic_vector(c_addrb_width - 1 downto 0);
sleep : in std_logic := '0';
deepsleep : in std_logic := '0';
shutdown : in std_logic := '0';
rsta_busy : out std_logic;
rstb_busy : out std_logic;
s_aclk : in std_logic := '0';
s_aresetn : in std_logic := '0';
s_axi_awid : in std_logic_vector(c_axi_id_width - 1 downto 0) := (others => '0');
s_axi_awaddr : in std_logic_vector(31 downto 0) := (others => '0');
s_axi_awlen : in std_logic_vector(7 downto 0) := (others => '0');
s_axi_awsize : in std_logic_vector(2 downto 0) := (others => '0');
s_axi_awburst : in std_logic_vector(1 downto 0) := (others => '0');
s_axi_awvalid : in std_logic := '0';
s_axi_awready : out std_logic;
s_axi_wdata : in std_logic_vector(c_write_width_a - 1 downto 0) := (others => '0');
s_axi_wstrb : in std_logic_vector(c_wea_width - 1 downto 0) := (others => '0');
s_axi_wlast : in std_logic := '0';
s_axi_wvalid : in std_logic := '0';
s_axi_wready : out std_logic;
s_axi_bid : out std_logic_vector(c_axi_id_width - 1 downto 0);
s_axi_bresp : out std_logic_vector(1 downto 0);
s_axi_bvalid : out std_logic;
s_axi_bready : in std_logic := '0';
s_axi_arid : in std_logic_vector(c_axi_id_width - 1 downto 0) := (others => '0');
s_axi_araddr : in std_logic_vector(31 downto 0) := (others => '0');
s_axi_arlen : in std_logic_vector(8 - 1 downto 0) := (others => '0');
s_axi_arsize : in std_logic_vector(2 downto 0) := (others => '0');
s_axi_arburst : in std_logic_vector(1 downto 0) := (others => '0');
s_axi_arvalid : in std_logic := '0';
s_axi_arready : out std_logic;
s_axi_rid : out std_logic_vector(c_axi_id_width - 1 downto 0);
s_axi_rdata : out std_logic_vector(c_write_width_b - 1 downto 0);
s_axi_rresp : out std_logic_vector(2 - 1 downto 0);
s_axi_rlast : out std_logic;
s_axi_rvalid : out std_logic;
s_axi_rready : in std_logic := '0';
s_axi_injectsbiterr : in std_logic := '0';
s_axi_injectdbiterr : in std_logic := '0';
s_axi_sbiterr : out std_logic;
s_axi_dbiterr : out std_logic;
s_axi_rdaddrecc : out std_logic_vector(c_addrb_width - 1 downto 0)
);
end entity blk_mem_gen_v8_3_5;
architecture xilinx of blk_mem_gen_v8_3_5 is
begin
end
architecture xilinx;
| gpl-3.0 |
hsnuonly/PikachuVolleyFPGA | VGA.srcs/sources_1/ip/ball_pixel_1/misc/blk_mem_gen_v8_3.vhd | 45 | 8325 | library ieee;
use ieee.std_logic_1164.all;
entity blk_mem_gen_v8_3_5 is
generic (
C_FAMILY : string := "virtex7";
C_XDEVICEFAMILY : string := "virtex7";
C_ELABORATION_DIR : string := "";
C_INTERFACE_TYPE : integer := 0;
C_AXI_TYPE : integer := 1;
C_AXI_SLAVE_TYPE : integer := 0;
C_USE_BRAM_BLOCK : integer := 0;
C_ENABLE_32BIT_ADDRESS : integer := 0;
C_CTRL_ECC_ALGO : string := "ECCHSIAO32-7";
C_HAS_AXI_ID : integer := 0;
C_AXI_ID_WIDTH : integer := 4;
C_MEM_TYPE : integer := 2;
C_BYTE_SIZE : integer := 9;
C_ALGORITHM : integer := 0;
C_PRIM_TYPE : integer := 3;
C_LOAD_INIT_FILE : integer := 0;
C_INIT_FILE_NAME : string := "no_coe_file_loaded";
C_INIT_FILE : string := "no_mem_file_loaded";
C_USE_DEFAULT_DATA : integer := 0;
C_DEFAULT_DATA : string := "0";
C_HAS_RSTA : integer := 0;
C_RST_PRIORITY_A : string := "ce";
C_RSTRAM_A : integer := 0;
C_INITA_VAL : string := "0";
C_HAS_ENA : integer := 1;
C_HAS_REGCEA : integer := 0;
C_USE_BYTE_WEA : integer := 0;
C_WEA_WIDTH : integer := 1;
C_WRITE_MODE_A : string := "WRITE_FIRST";
C_WRITE_WIDTH_A : integer := 9;
C_READ_WIDTH_A : integer := 9;
C_WRITE_DEPTH_A : integer := 2048;
C_READ_DEPTH_A : integer := 2048;
C_ADDRA_WIDTH : integer := 11;
C_HAS_RSTB : integer := 0;
C_RST_PRIORITY_B : string := "ce";
C_RSTRAM_B : integer := 0;
C_INITB_VAL : string := "0";
C_HAS_ENB : integer := 1;
C_HAS_REGCEB : integer := 0;
C_USE_BYTE_WEB : integer := 0;
C_WEB_WIDTH : integer := 1;
C_WRITE_MODE_B : string := "WRITE_FIRST";
C_WRITE_WIDTH_B : integer := 9;
C_READ_WIDTH_B : integer := 9;
C_WRITE_DEPTH_B : integer := 2048;
C_READ_DEPTH_B : integer := 2048;
C_ADDRB_WIDTH : integer := 11;
C_HAS_MEM_OUTPUT_REGS_A : integer := 0;
C_HAS_MEM_OUTPUT_REGS_B : integer := 0;
C_HAS_MUX_OUTPUT_REGS_A : integer := 0;
C_HAS_MUX_OUTPUT_REGS_B : integer := 0;
C_MUX_PIPELINE_STAGES : integer := 0;
C_HAS_SOFTECC_INPUT_REGS_A : integer := 0;
C_HAS_SOFTECC_OUTPUT_REGS_B : integer := 0;
C_USE_SOFTECC : integer := 0;
C_USE_ECC : integer := 0;
C_EN_ECC_PIPE : integer := 0;
C_HAS_INJECTERR : integer := 0;
C_SIM_COLLISION_CHECK : string := "none";
C_COMMON_CLK : integer := 0;
C_DISABLE_WARN_BHV_COLL : integer := 0;
C_EN_SLEEP_PIN : integer := 0;
C_USE_URAM : integer := 0;
C_EN_RDADDRA_CHG : integer := 0;
C_EN_RDADDRB_CHG : integer := 0;
C_EN_DEEPSLEEP_PIN : integer := 0;
C_EN_SHUTDOWN_PIN : integer := 0;
C_EN_SAFETY_CKT : integer := 0;
C_DISABLE_WARN_BHV_RANGE : integer := 0;
C_COUNT_36K_BRAM : string := "";
C_COUNT_18K_BRAM : string := "";
C_EST_POWER_SUMMARY : string := ""
);
port (
clka : in std_logic := '0';
rsta : in std_logic := '0';
ena : in std_logic := '0';
regcea : in std_logic := '0';
wea : in std_logic_vector(c_wea_width - 1 downto 0) := (others => '0');
addra : in std_logic_vector(c_addra_width - 1 downto 0) := (others => '0');
dina : in std_logic_vector(c_write_width_a - 1 downto 0) := (others => '0');
douta : out std_logic_vector(c_read_width_a - 1 downto 0);
clkb : in std_logic := '0';
rstb : in std_logic := '0';
enb : in std_logic := '0';
regceb : in std_logic := '0';
web : in std_logic_vector(c_web_width - 1 downto 0) := (others => '0');
addrb : in std_logic_vector(c_addrb_width - 1 downto 0) := (others => '0');
dinb : in std_logic_vector(c_write_width_b - 1 downto 0) := (others => '0');
doutb : out std_logic_vector(c_read_width_b - 1 downto 0);
injectsbiterr : in std_logic := '0';
injectdbiterr : in std_logic := '0';
eccpipece : in std_logic := '0';
sbiterr : out std_logic;
dbiterr : out std_logic;
rdaddrecc : out std_logic_vector(c_addrb_width - 1 downto 0);
sleep : in std_logic := '0';
deepsleep : in std_logic := '0';
shutdown : in std_logic := '0';
rsta_busy : out std_logic;
rstb_busy : out std_logic;
s_aclk : in std_logic := '0';
s_aresetn : in std_logic := '0';
s_axi_awid : in std_logic_vector(c_axi_id_width - 1 downto 0) := (others => '0');
s_axi_awaddr : in std_logic_vector(31 downto 0) := (others => '0');
s_axi_awlen : in std_logic_vector(7 downto 0) := (others => '0');
s_axi_awsize : in std_logic_vector(2 downto 0) := (others => '0');
s_axi_awburst : in std_logic_vector(1 downto 0) := (others => '0');
s_axi_awvalid : in std_logic := '0';
s_axi_awready : out std_logic;
s_axi_wdata : in std_logic_vector(c_write_width_a - 1 downto 0) := (others => '0');
s_axi_wstrb : in std_logic_vector(c_wea_width - 1 downto 0) := (others => '0');
s_axi_wlast : in std_logic := '0';
s_axi_wvalid : in std_logic := '0';
s_axi_wready : out std_logic;
s_axi_bid : out std_logic_vector(c_axi_id_width - 1 downto 0);
s_axi_bresp : out std_logic_vector(1 downto 0);
s_axi_bvalid : out std_logic;
s_axi_bready : in std_logic := '0';
s_axi_arid : in std_logic_vector(c_axi_id_width - 1 downto 0) := (others => '0');
s_axi_araddr : in std_logic_vector(31 downto 0) := (others => '0');
s_axi_arlen : in std_logic_vector(8 - 1 downto 0) := (others => '0');
s_axi_arsize : in std_logic_vector(2 downto 0) := (others => '0');
s_axi_arburst : in std_logic_vector(1 downto 0) := (others => '0');
s_axi_arvalid : in std_logic := '0';
s_axi_arready : out std_logic;
s_axi_rid : out std_logic_vector(c_axi_id_width - 1 downto 0);
s_axi_rdata : out std_logic_vector(c_write_width_b - 1 downto 0);
s_axi_rresp : out std_logic_vector(2 - 1 downto 0);
s_axi_rlast : out std_logic;
s_axi_rvalid : out std_logic;
s_axi_rready : in std_logic := '0';
s_axi_injectsbiterr : in std_logic := '0';
s_axi_injectdbiterr : in std_logic := '0';
s_axi_sbiterr : out std_logic;
s_axi_dbiterr : out std_logic;
s_axi_rdaddrecc : out std_logic_vector(c_addrb_width - 1 downto 0)
);
end entity blk_mem_gen_v8_3_5;
architecture xilinx of blk_mem_gen_v8_3_5 is
begin
end
architecture xilinx;
| gpl-3.0 |
hsnuonly/PikachuVolleyFPGA | VGA.srcs/sources_1/ip/pikachu_jump_pixel/synth/pikachu_jump_pixel.vhd | 1 | 14462 | -- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:blk_mem_gen:8.3
-- IP Revision: 5
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY blk_mem_gen_v8_3_5;
USE blk_mem_gen_v8_3_5.blk_mem_gen_v8_3_5;
ENTITY pikachu_jump_pixel IS
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(11 DOWNTO 0)
);
END pikachu_jump_pixel;
ARCHITECTURE pikachu_jump_pixel_arch OF pikachu_jump_pixel IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF pikachu_jump_pixel_arch: ARCHITECTURE IS "yes";
COMPONENT blk_mem_gen_v8_3_5 IS
GENERIC (
C_FAMILY : STRING;
C_XDEVICEFAMILY : STRING;
C_ELABORATION_DIR : STRING;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_AXI_SLAVE_TYPE : INTEGER;
C_USE_BRAM_BLOCK : INTEGER;
C_ENABLE_32BIT_ADDRESS : INTEGER;
C_CTRL_ECC_ALGO : STRING;
C_HAS_AXI_ID : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_MEM_TYPE : INTEGER;
C_BYTE_SIZE : INTEGER;
C_ALGORITHM : INTEGER;
C_PRIM_TYPE : INTEGER;
C_LOAD_INIT_FILE : INTEGER;
C_INIT_FILE_NAME : STRING;
C_INIT_FILE : STRING;
C_USE_DEFAULT_DATA : INTEGER;
C_DEFAULT_DATA : STRING;
C_HAS_RSTA : INTEGER;
C_RST_PRIORITY_A : STRING;
C_RSTRAM_A : INTEGER;
C_INITA_VAL : STRING;
C_HAS_ENA : INTEGER;
C_HAS_REGCEA : INTEGER;
C_USE_BYTE_WEA : INTEGER;
C_WEA_WIDTH : INTEGER;
C_WRITE_MODE_A : STRING;
C_WRITE_WIDTH_A : INTEGER;
C_READ_WIDTH_A : INTEGER;
C_WRITE_DEPTH_A : INTEGER;
C_READ_DEPTH_A : INTEGER;
C_ADDRA_WIDTH : INTEGER;
C_HAS_RSTB : INTEGER;
C_RST_PRIORITY_B : STRING;
C_RSTRAM_B : INTEGER;
C_INITB_VAL : STRING;
C_HAS_ENB : INTEGER;
C_HAS_REGCEB : INTEGER;
C_USE_BYTE_WEB : INTEGER;
C_WEB_WIDTH : INTEGER;
C_WRITE_MODE_B : STRING;
C_WRITE_WIDTH_B : INTEGER;
C_READ_WIDTH_B : INTEGER;
C_WRITE_DEPTH_B : INTEGER;
C_READ_DEPTH_B : INTEGER;
C_ADDRB_WIDTH : INTEGER;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER;
C_MUX_PIPELINE_STAGES : INTEGER;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER;
C_USE_SOFTECC : INTEGER;
C_USE_ECC : INTEGER;
C_EN_ECC_PIPE : INTEGER;
C_HAS_INJECTERR : INTEGER;
C_SIM_COLLISION_CHECK : STRING;
C_COMMON_CLK : INTEGER;
C_DISABLE_WARN_BHV_COLL : INTEGER;
C_EN_SLEEP_PIN : INTEGER;
C_USE_URAM : INTEGER;
C_EN_RDADDRA_CHG : INTEGER;
C_EN_RDADDRB_CHG : INTEGER;
C_EN_DEEPSLEEP_PIN : INTEGER;
C_EN_SHUTDOWN_PIN : INTEGER;
C_EN_SAFETY_CKT : INTEGER;
C_DISABLE_WARN_BHV_RANGE : INTEGER;
C_COUNT_36K_BRAM : STRING;
C_COUNT_18K_BRAM : STRING;
C_EST_POWER_SUMMARY : STRING
);
PORT (
clka : IN STD_LOGIC;
rsta : IN STD_LOGIC;
ena : IN STD_LOGIC;
regcea : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
clkb : IN STD_LOGIC;
rstb : IN STD_LOGIC;
enb : IN STD_LOGIC;
regceb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
injectsbiterr : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
eccpipece : IN STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
rdaddrecc : OUT STD_LOGIC_VECTOR(12 DOWNTO 0);
sleep : IN STD_LOGIC;
deepsleep : IN STD_LOGIC;
shutdown : IN STD_LOGIC;
rsta_busy : OUT STD_LOGIC;
rstb_busy : OUT STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
s_axi_injectsbiterr : IN STD_LOGIC;
s_axi_injectdbiterr : IN STD_LOGIC;
s_axi_sbiterr : OUT STD_LOGIC;
s_axi_dbiterr : OUT STD_LOGIC;
s_axi_rdaddrecc : OUT STD_LOGIC_VECTOR(12 DOWNTO 0)
);
END COMPONENT blk_mem_gen_v8_3_5;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF pikachu_jump_pixel_arch: ARCHITECTURE IS "blk_mem_gen_v8_3_5,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF pikachu_jump_pixel_arch : ARCHITECTURE IS "pikachu_jump_pixel,blk_mem_gen_v8_3_5,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF pikachu_jump_pixel_arch: ARCHITECTURE IS "pikachu_jump_pixel,blk_mem_gen_v8_3_5,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=blk_mem_gen,x_ipVersion=8.3,x_ipCoreRevision=5,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=artix7,C_XDEVICEFAMILY=artix7,C_ELABORATION_DIR=./,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_AXI_SLAVE_TYPE=0,C_USE_BRAM_BLOCK=0,C_ENABLE_32BIT_ADDRESS=0,C_CTRL_ECC_ALGO=NONE,C_HAS_AXI_ID=0,C_AXI_ID_WIDTH=4,C_MEM_TYPE=0,C_BYTE_SIZE=9,C_ALGORITHM=1,C_PRIM_TYPE=1,C_LOAD_INIT_FILE=1,C_INIT_FILE_NAME=" &
"pikachu_jump_pixel.mif,C_INIT_FILE=pikachu_jump_pixel.mem,C_USE_DEFAULT_DATA=0,C_DEFAULT_DATA=0,C_HAS_RSTA=0,C_RST_PRIORITY_A=CE,C_RSTRAM_A=0,C_INITA_VAL=0,C_HAS_ENA=0,C_HAS_REGCEA=0,C_USE_BYTE_WEA=0,C_WEA_WIDTH=1,C_WRITE_MODE_A=WRITE_FIRST,C_WRITE_WIDTH_A=12,C_READ_WIDTH_A=12,C_WRITE_DEPTH_A=6804,C_READ_DEPTH_A=6804,C_ADDRA_WIDTH=13,C_HAS_RSTB=0,C_RST_PRIORITY_B=CE,C_RSTRAM_B=0,C_INITB_VAL=0,C_HAS_ENB=0,C_HAS_REGCEB=0,C_USE_BYTE_WEB=0,C_WEB_WIDTH=1,C_WRITE_MODE_B=WRITE_FIRST,C_WRITE_WIDTH_B=12," &
"C_READ_WIDTH_B=12,C_WRITE_DEPTH_B=6804,C_READ_DEPTH_B=6804,C_ADDRB_WIDTH=13,C_HAS_MEM_OUTPUT_REGS_A=1,C_HAS_MEM_OUTPUT_REGS_B=0,C_HAS_MUX_OUTPUT_REGS_A=0,C_HAS_MUX_OUTPUT_REGS_B=0,C_MUX_PIPELINE_STAGES=0,C_HAS_SOFTECC_INPUT_REGS_A=0,C_HAS_SOFTECC_OUTPUT_REGS_B=0,C_USE_SOFTECC=0,C_USE_ECC=0,C_EN_ECC_PIPE=0,C_HAS_INJECTERR=0,C_SIM_COLLISION_CHECK=ALL,C_COMMON_CLK=0,C_DISABLE_WARN_BHV_COLL=0,C_EN_SLEEP_PIN=0,C_USE_URAM=0,C_EN_RDADDRA_CHG=0,C_EN_RDADDRB_CHG=0,C_EN_DEEPSLEEP_PIN=0,C_EN_SHUTDOWN_PIN=0" &
",C_EN_SAFETY_CKT=0,C_DISABLE_WARN_BHV_RANGE=0,C_COUNT_36K_BRAM=3,C_COUNT_18K_BRAM=0,C_EST_POWER_SUMMARY=Estimated Power for IP _ 5.016775 mW}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clka: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
ATTRIBUTE X_INTERFACE_INFO OF wea: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA WE";
ATTRIBUTE X_INTERFACE_INFO OF addra: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
ATTRIBUTE X_INTERFACE_INFO OF dina: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN";
ATTRIBUTE X_INTERFACE_INFO OF douta: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT";
BEGIN
U0 : blk_mem_gen_v8_3_5
GENERIC MAP (
C_FAMILY => "artix7",
C_XDEVICEFAMILY => "artix7",
C_ELABORATION_DIR => "./",
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_AXI_SLAVE_TYPE => 0,
C_USE_BRAM_BLOCK => 0,
C_ENABLE_32BIT_ADDRESS => 0,
C_CTRL_ECC_ALGO => "NONE",
C_HAS_AXI_ID => 0,
C_AXI_ID_WIDTH => 4,
C_MEM_TYPE => 0,
C_BYTE_SIZE => 9,
C_ALGORITHM => 1,
C_PRIM_TYPE => 1,
C_LOAD_INIT_FILE => 1,
C_INIT_FILE_NAME => "pikachu_jump_pixel.mif",
C_INIT_FILE => "pikachu_jump_pixel.mem",
C_USE_DEFAULT_DATA => 0,
C_DEFAULT_DATA => "0",
C_HAS_RSTA => 0,
C_RST_PRIORITY_A => "CE",
C_RSTRAM_A => 0,
C_INITA_VAL => "0",
C_HAS_ENA => 0,
C_HAS_REGCEA => 0,
C_USE_BYTE_WEA => 0,
C_WEA_WIDTH => 1,
C_WRITE_MODE_A => "WRITE_FIRST",
C_WRITE_WIDTH_A => 12,
C_READ_WIDTH_A => 12,
C_WRITE_DEPTH_A => 6804,
C_READ_DEPTH_A => 6804,
C_ADDRA_WIDTH => 13,
C_HAS_RSTB => 0,
C_RST_PRIORITY_B => "CE",
C_RSTRAM_B => 0,
C_INITB_VAL => "0",
C_HAS_ENB => 0,
C_HAS_REGCEB => 0,
C_USE_BYTE_WEB => 0,
C_WEB_WIDTH => 1,
C_WRITE_MODE_B => "WRITE_FIRST",
C_WRITE_WIDTH_B => 12,
C_READ_WIDTH_B => 12,
C_WRITE_DEPTH_B => 6804,
C_READ_DEPTH_B => 6804,
C_ADDRB_WIDTH => 13,
C_HAS_MEM_OUTPUT_REGS_A => 1,
C_HAS_MEM_OUTPUT_REGS_B => 0,
C_HAS_MUX_OUTPUT_REGS_A => 0,
C_HAS_MUX_OUTPUT_REGS_B => 0,
C_MUX_PIPELINE_STAGES => 0,
C_HAS_SOFTECC_INPUT_REGS_A => 0,
C_HAS_SOFTECC_OUTPUT_REGS_B => 0,
C_USE_SOFTECC => 0,
C_USE_ECC => 0,
C_EN_ECC_PIPE => 0,
C_HAS_INJECTERR => 0,
C_SIM_COLLISION_CHECK => "ALL",
C_COMMON_CLK => 0,
C_DISABLE_WARN_BHV_COLL => 0,
C_EN_SLEEP_PIN => 0,
C_USE_URAM => 0,
C_EN_RDADDRA_CHG => 0,
C_EN_RDADDRB_CHG => 0,
C_EN_DEEPSLEEP_PIN => 0,
C_EN_SHUTDOWN_PIN => 0,
C_EN_SAFETY_CKT => 0,
C_DISABLE_WARN_BHV_RANGE => 0,
C_COUNT_36K_BRAM => "3",
C_COUNT_18K_BRAM => "0",
C_EST_POWER_SUMMARY => "Estimated Power for IP : 5.016775 mW"
)
PORT MAP (
clka => clka,
rsta => '0',
ena => '0',
regcea => '0',
wea => wea,
addra => addra,
dina => dina,
douta => douta,
clkb => '0',
rstb => '0',
enb => '0',
regceb => '0',
web => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
addrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 13)),
dinb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 12)),
injectsbiterr => '0',
injectdbiterr => '0',
eccpipece => '0',
sleep => '0',
deepsleep => '0',
shutdown => '0',
s_aclk => '0',
s_aresetn => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awvalid => '0',
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 12)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wlast => '0',
s_axi_wvalid => '0',
s_axi_bready => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arvalid => '0',
s_axi_rready => '0',
s_axi_injectsbiterr => '0',
s_axi_injectdbiterr => '0'
);
END pikachu_jump_pixel_arch;
| gpl-3.0 |
hsnuonly/PikachuVolleyFPGA | VGA.srcs/sources_1/ip/ball_pixel_1/synth/ball_pixel.vhd | 1 | 14342 | -- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:blk_mem_gen:8.3
-- IP Revision: 5
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY blk_mem_gen_v8_3_5;
USE blk_mem_gen_v8_3_5.blk_mem_gen_v8_3_5;
ENTITY ball_pixel IS
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(11 DOWNTO 0)
);
END ball_pixel;
ARCHITECTURE ball_pixel_arch OF ball_pixel IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF ball_pixel_arch: ARCHITECTURE IS "yes";
COMPONENT blk_mem_gen_v8_3_5 IS
GENERIC (
C_FAMILY : STRING;
C_XDEVICEFAMILY : STRING;
C_ELABORATION_DIR : STRING;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_AXI_SLAVE_TYPE : INTEGER;
C_USE_BRAM_BLOCK : INTEGER;
C_ENABLE_32BIT_ADDRESS : INTEGER;
C_CTRL_ECC_ALGO : STRING;
C_HAS_AXI_ID : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_MEM_TYPE : INTEGER;
C_BYTE_SIZE : INTEGER;
C_ALGORITHM : INTEGER;
C_PRIM_TYPE : INTEGER;
C_LOAD_INIT_FILE : INTEGER;
C_INIT_FILE_NAME : STRING;
C_INIT_FILE : STRING;
C_USE_DEFAULT_DATA : INTEGER;
C_DEFAULT_DATA : STRING;
C_HAS_RSTA : INTEGER;
C_RST_PRIORITY_A : STRING;
C_RSTRAM_A : INTEGER;
C_INITA_VAL : STRING;
C_HAS_ENA : INTEGER;
C_HAS_REGCEA : INTEGER;
C_USE_BYTE_WEA : INTEGER;
C_WEA_WIDTH : INTEGER;
C_WRITE_MODE_A : STRING;
C_WRITE_WIDTH_A : INTEGER;
C_READ_WIDTH_A : INTEGER;
C_WRITE_DEPTH_A : INTEGER;
C_READ_DEPTH_A : INTEGER;
C_ADDRA_WIDTH : INTEGER;
C_HAS_RSTB : INTEGER;
C_RST_PRIORITY_B : STRING;
C_RSTRAM_B : INTEGER;
C_INITB_VAL : STRING;
C_HAS_ENB : INTEGER;
C_HAS_REGCEB : INTEGER;
C_USE_BYTE_WEB : INTEGER;
C_WEB_WIDTH : INTEGER;
C_WRITE_MODE_B : STRING;
C_WRITE_WIDTH_B : INTEGER;
C_READ_WIDTH_B : INTEGER;
C_WRITE_DEPTH_B : INTEGER;
C_READ_DEPTH_B : INTEGER;
C_ADDRB_WIDTH : INTEGER;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER;
C_MUX_PIPELINE_STAGES : INTEGER;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER;
C_USE_SOFTECC : INTEGER;
C_USE_ECC : INTEGER;
C_EN_ECC_PIPE : INTEGER;
C_HAS_INJECTERR : INTEGER;
C_SIM_COLLISION_CHECK : STRING;
C_COMMON_CLK : INTEGER;
C_DISABLE_WARN_BHV_COLL : INTEGER;
C_EN_SLEEP_PIN : INTEGER;
C_USE_URAM : INTEGER;
C_EN_RDADDRA_CHG : INTEGER;
C_EN_RDADDRB_CHG : INTEGER;
C_EN_DEEPSLEEP_PIN : INTEGER;
C_EN_SHUTDOWN_PIN : INTEGER;
C_EN_SAFETY_CKT : INTEGER;
C_DISABLE_WARN_BHV_RANGE : INTEGER;
C_COUNT_36K_BRAM : STRING;
C_COUNT_18K_BRAM : STRING;
C_EST_POWER_SUMMARY : STRING
);
PORT (
clka : IN STD_LOGIC;
rsta : IN STD_LOGIC;
ena : IN STD_LOGIC;
regcea : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
clkb : IN STD_LOGIC;
rstb : IN STD_LOGIC;
enb : IN STD_LOGIC;
regceb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
injectsbiterr : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
eccpipece : IN STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
rdaddrecc : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
sleep : IN STD_LOGIC;
deepsleep : IN STD_LOGIC;
shutdown : IN STD_LOGIC;
rsta_busy : OUT STD_LOGIC;
rstb_busy : OUT STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
s_axi_injectsbiterr : IN STD_LOGIC;
s_axi_injectdbiterr : IN STD_LOGIC;
s_axi_sbiterr : OUT STD_LOGIC;
s_axi_dbiterr : OUT STD_LOGIC;
s_axi_rdaddrecc : OUT STD_LOGIC_VECTOR(11 DOWNTO 0)
);
END COMPONENT blk_mem_gen_v8_3_5;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF ball_pixel_arch: ARCHITECTURE IS "blk_mem_gen_v8_3_5,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF ball_pixel_arch : ARCHITECTURE IS "ball_pixel,blk_mem_gen_v8_3_5,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF ball_pixel_arch: ARCHITECTURE IS "ball_pixel,blk_mem_gen_v8_3_5,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=blk_mem_gen,x_ipVersion=8.3,x_ipCoreRevision=5,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=artix7,C_XDEVICEFAMILY=artix7,C_ELABORATION_DIR=./,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_AXI_SLAVE_TYPE=0,C_USE_BRAM_BLOCK=0,C_ENABLE_32BIT_ADDRESS=0,C_CTRL_ECC_ALGO=NONE,C_HAS_AXI_ID=0,C_AXI_ID_WIDTH=4,C_MEM_TYPE=0,C_BYTE_SIZE=9,C_ALGORITHM=1,C_PRIM_TYPE=1,C_LOAD_INIT_FILE=1,C_INIT_FILE_NAME=ball_pix" &
"el.mif,C_INIT_FILE=ball_pixel.mem,C_USE_DEFAULT_DATA=0,C_DEFAULT_DATA=0,C_HAS_RSTA=0,C_RST_PRIORITY_A=CE,C_RSTRAM_A=0,C_INITA_VAL=0,C_HAS_ENA=0,C_HAS_REGCEA=0,C_USE_BYTE_WEA=0,C_WEA_WIDTH=1,C_WRITE_MODE_A=WRITE_FIRST,C_WRITE_WIDTH_A=12,C_READ_WIDTH_A=12,C_WRITE_DEPTH_A=3600,C_READ_DEPTH_A=3600,C_ADDRA_WIDTH=12,C_HAS_RSTB=0,C_RST_PRIORITY_B=CE,C_RSTRAM_B=0,C_INITB_VAL=0,C_HAS_ENB=0,C_HAS_REGCEB=0,C_USE_BYTE_WEB=0,C_WEB_WIDTH=1,C_WRITE_MODE_B=WRITE_FIRST,C_WRITE_WIDTH_B=12,C_READ_WIDTH_B=12,C_WRIT" &
"E_DEPTH_B=3600,C_READ_DEPTH_B=3600,C_ADDRB_WIDTH=12,C_HAS_MEM_OUTPUT_REGS_A=1,C_HAS_MEM_OUTPUT_REGS_B=0,C_HAS_MUX_OUTPUT_REGS_A=0,C_HAS_MUX_OUTPUT_REGS_B=0,C_MUX_PIPELINE_STAGES=0,C_HAS_SOFTECC_INPUT_REGS_A=0,C_HAS_SOFTECC_OUTPUT_REGS_B=0,C_USE_SOFTECC=0,C_USE_ECC=0,C_EN_ECC_PIPE=0,C_HAS_INJECTERR=0,C_SIM_COLLISION_CHECK=ALL,C_COMMON_CLK=0,C_DISABLE_WARN_BHV_COLL=0,C_EN_SLEEP_PIN=0,C_USE_URAM=0,C_EN_RDADDRA_CHG=0,C_EN_RDADDRB_CHG=0,C_EN_DEEPSLEEP_PIN=0,C_EN_SHUTDOWN_PIN=0,C_EN_SAFETY_CKT=0,C_DIS" &
"ABLE_WARN_BHV_RANGE=0,C_COUNT_36K_BRAM=1,C_COUNT_18K_BRAM=1,C_EST_POWER_SUMMARY=Estimated Power for IP _ 3.822999 mW}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clka: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
ATTRIBUTE X_INTERFACE_INFO OF wea: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA WE";
ATTRIBUTE X_INTERFACE_INFO OF addra: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
ATTRIBUTE X_INTERFACE_INFO OF dina: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN";
ATTRIBUTE X_INTERFACE_INFO OF douta: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT";
BEGIN
U0 : blk_mem_gen_v8_3_5
GENERIC MAP (
C_FAMILY => "artix7",
C_XDEVICEFAMILY => "artix7",
C_ELABORATION_DIR => "./",
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_AXI_SLAVE_TYPE => 0,
C_USE_BRAM_BLOCK => 0,
C_ENABLE_32BIT_ADDRESS => 0,
C_CTRL_ECC_ALGO => "NONE",
C_HAS_AXI_ID => 0,
C_AXI_ID_WIDTH => 4,
C_MEM_TYPE => 0,
C_BYTE_SIZE => 9,
C_ALGORITHM => 1,
C_PRIM_TYPE => 1,
C_LOAD_INIT_FILE => 1,
C_INIT_FILE_NAME => "ball_pixel.mif",
C_INIT_FILE => "ball_pixel.mem",
C_USE_DEFAULT_DATA => 0,
C_DEFAULT_DATA => "0",
C_HAS_RSTA => 0,
C_RST_PRIORITY_A => "CE",
C_RSTRAM_A => 0,
C_INITA_VAL => "0",
C_HAS_ENA => 0,
C_HAS_REGCEA => 0,
C_USE_BYTE_WEA => 0,
C_WEA_WIDTH => 1,
C_WRITE_MODE_A => "WRITE_FIRST",
C_WRITE_WIDTH_A => 12,
C_READ_WIDTH_A => 12,
C_WRITE_DEPTH_A => 3600,
C_READ_DEPTH_A => 3600,
C_ADDRA_WIDTH => 12,
C_HAS_RSTB => 0,
C_RST_PRIORITY_B => "CE",
C_RSTRAM_B => 0,
C_INITB_VAL => "0",
C_HAS_ENB => 0,
C_HAS_REGCEB => 0,
C_USE_BYTE_WEB => 0,
C_WEB_WIDTH => 1,
C_WRITE_MODE_B => "WRITE_FIRST",
C_WRITE_WIDTH_B => 12,
C_READ_WIDTH_B => 12,
C_WRITE_DEPTH_B => 3600,
C_READ_DEPTH_B => 3600,
C_ADDRB_WIDTH => 12,
C_HAS_MEM_OUTPUT_REGS_A => 1,
C_HAS_MEM_OUTPUT_REGS_B => 0,
C_HAS_MUX_OUTPUT_REGS_A => 0,
C_HAS_MUX_OUTPUT_REGS_B => 0,
C_MUX_PIPELINE_STAGES => 0,
C_HAS_SOFTECC_INPUT_REGS_A => 0,
C_HAS_SOFTECC_OUTPUT_REGS_B => 0,
C_USE_SOFTECC => 0,
C_USE_ECC => 0,
C_EN_ECC_PIPE => 0,
C_HAS_INJECTERR => 0,
C_SIM_COLLISION_CHECK => "ALL",
C_COMMON_CLK => 0,
C_DISABLE_WARN_BHV_COLL => 0,
C_EN_SLEEP_PIN => 0,
C_USE_URAM => 0,
C_EN_RDADDRA_CHG => 0,
C_EN_RDADDRB_CHG => 0,
C_EN_DEEPSLEEP_PIN => 0,
C_EN_SHUTDOWN_PIN => 0,
C_EN_SAFETY_CKT => 0,
C_DISABLE_WARN_BHV_RANGE => 0,
C_COUNT_36K_BRAM => "1",
C_COUNT_18K_BRAM => "1",
C_EST_POWER_SUMMARY => "Estimated Power for IP : 3.822999 mW"
)
PORT MAP (
clka => clka,
rsta => '0',
ena => '0',
regcea => '0',
wea => wea,
addra => addra,
dina => dina,
douta => douta,
clkb => '0',
rstb => '0',
enb => '0',
regceb => '0',
web => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
addrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 12)),
dinb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 12)),
injectsbiterr => '0',
injectdbiterr => '0',
eccpipece => '0',
sleep => '0',
deepsleep => '0',
shutdown => '0',
s_aclk => '0',
s_aresetn => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awvalid => '0',
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 12)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wlast => '0',
s_axi_wvalid => '0',
s_axi_bready => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arvalid => '0',
s_axi_rready => '0',
s_axi_injectsbiterr => '0',
s_axi_injectdbiterr => '0'
);
END ball_pixel_arch;
| gpl-3.0 |
Darkin47/Zynq-TX-UTT | Vivado_HLS/image_contrast_adj/solution1/impl/vhdl/project.srcs/sources_1/ip/doHistStretch_ap_fdiv_14_no_dsp_32/axi_utils_v2_0_2/hdl/axi_utils_v2_0_vh_rfs.vhd | 9 | 292074 | `protect begin_protected
`protect version = 1
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`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
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leyXU0+bg63EYkTzMdkp4k0zhTlbbcRvq+k6awNZole4I3ZT71VBmdZHUIVej0847jxSrpquDi6m
Xr2wZYmIqNKHeM2BdlK1W31h70LO2aNnCBP6GGORZ6raVtcOd1vjr0O3/tIb
`protect end_protected
| gpl-3.0 |
freecores/usb_fpga_1_11 | examples/usb-fpga-2.01/2.01b/lightshow/fpga/lightshow.vhd | 17 | 3116 | library ieee;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity lightshow is
port(
led1 : out std_logic_vector(9 downto 0); -- LED1 on debug board
led2 : out std_logic_vector(19 downto 0); -- LED2 + LED3 on debug board
sw : in std_logic_vector(3 downto 0);
fxclk : in std_logic
);
end lightshow;
--signal declaration
architecture RTL of lightshow is
type tPattern1 is array(9 downto 0) of integer range 0 to 255;
type tPattern2 is array(19 downto 0) of integer range 0 to 255;
signal pattern1 : tPattern1 := (0, 10, 41, 92, 163, 255, 163, 92, 41, 10); -- pattern for LED1
signal pattern20 : tPattern2 := (0, 1, 2, 9, 16, 25, 36, 49, 64, 81, 64, 49, 36, 25, 16, 9, 2, 1, 0, 0); -- 1st pattern for LED2
signal pattern21 : tPattern2 := (0, 19, 77, 174, 77, 19, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); -- 2nd pattern for LED2
signal pattern2 : tPattern2; -- pattern20 + pattern21
signal cnt1,cnt20, cnt21 : std_logic_vector(22 downto 0);
signal pwm_cnt : std_logic_vector(19 downto 0);
signal pwm_cnt8 : std_logic_vector(7 downto 0);
begin
pwm_cnt8 <= pwm_cnt(19 downto 12);
dp_fxclk: process(fxclk)
begin
if fxclk' event and fxclk = '1' then
-- pattern for led 1
if ( cnt1 >= conv_std_logic_vector(7200000,23) ) -- 1/1.5 Hz
then
if ( sw(0) = '1' )
then
pattern1(8 downto 0) <= pattern1(9 downto 1);
pattern1(9) <= pattern1(0);
else
pattern1(9 downto 1) <= pattern1(8 downto 0);
pattern1(0) <= pattern1(9);
end if;
cnt1 <= (others => '0');
else
cnt1 <= cnt1 + 1;
end if;
-- pattern for led 2
if ( ( cnt20 >= conv_std_logic_vector(4800000,23) ) or ( (sw(2)= '1') and (cnt20 >= conv_std_logic_vector(1600000,23)) ) ) -- SW1 off: 1/3Hz, SW1 on: 1Hz
then
pattern20(18 downto 0) <= pattern20(19 downto 1);
pattern20(19) <= pattern20(0);
cnt20 <= (others => '0');
else
cnt20 <= cnt20 + 1;
end if;
if ( ( cnt21 >= conv_std_logic_vector(2000000,23) ) or ( (sw(3)= '1') and (cnt21 >= conv_std_logic_vector(500000,23)) ) )
then
if ( sw(1) = '1' )
then
pattern21(18 downto 0) <= pattern21(19 downto 1);
pattern21(19) <= pattern21(0);
else
pattern21(19 downto 1) <= pattern21(18 downto 0);
pattern21(0) <= pattern21(19);
end if;
cnt21 <= (others => '0');
else
cnt21 <= cnt21 + 1;
end if;
for i in 0 to 19 loop
pattern2(i) <= pattern20(i) + pattern21(i);
end loop;
-- pwm
if ( pwm_cnt8 = conv_std_logic_vector(255,8) )
then
pwm_cnt <= ( others => '0' );
else
pwm_cnt <= pwm_cnt + 1;
end if;
-- led1
for i in 0 to 9 loop
if ( pwm_cnt8 < pattern1(i) )
then
led1(i) <= '1';
else
led1(i) <= '0';
end if;
end loop;
for i in 0 to 19 loop
if (pwm_cnt8 < pattern2(i) )
then
led2(i) <= '1';
else
led2(i) <= '0';
end if;
end loop;
end if;
end process dp_fxclk;
end RTL;
| gpl-3.0 |
mistryalok/Zedboard | learning/opencv_hls/xapp1167_vivado/sw/median/prj/solution1/impl/vhdl/FIFO_image_filter_img_1_data_stream_0_V.vhd | 4 | 4629 | -- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.4
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity FIFO_image_filter_img_1_data_stream_0_V_shiftReg is
generic (
DATA_WIDTH : integer := 8;
ADDR_WIDTH : integer := 1;
DEPTH : integer := 2);
port (
clk : in std_logic;
data : in std_logic_vector(DATA_WIDTH-1 downto 0);
ce : in std_logic;
a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
q : out std_logic_vector(DATA_WIDTH-1 downto 0));
end FIFO_image_filter_img_1_data_stream_0_V_shiftReg;
architecture rtl of FIFO_image_filter_img_1_data_stream_0_V_shiftReg is
--constant DEPTH_WIDTH: integer := 16;
type SRL_ARRAY is array (0 to DEPTH-1) of std_logic_vector(DATA_WIDTH-1 downto 0);
signal SRL_SIG : SRL_ARRAY;
begin
p_shift: process (clk)
begin
if (clk'event and clk = '1') then
if (ce = '1') then
SRL_SIG <= data & SRL_SIG(0 to DEPTH-2);
end if;
end if;
end process;
q <= SRL_SIG(conv_integer(a));
end rtl;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity FIFO_image_filter_img_1_data_stream_0_V is
generic (
MEM_STYLE : string := "auto";
DATA_WIDTH : integer := 8;
ADDR_WIDTH : integer := 1;
DEPTH : integer := 2);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_empty_n : OUT STD_LOGIC;
if_read_ce : IN STD_LOGIC;
if_read : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
if_full_n : OUT STD_LOGIC;
if_write_ce : IN STD_LOGIC;
if_write : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0));
end entity;
architecture rtl of FIFO_image_filter_img_1_data_stream_0_V is
component FIFO_image_filter_img_1_data_stream_0_V_shiftReg is
generic (
DATA_WIDTH : integer := 8;
ADDR_WIDTH : integer := 1;
DEPTH : integer := 2);
port (
clk : in std_logic;
data : in std_logic_vector(DATA_WIDTH-1 downto 0);
ce : in std_logic;
a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
q : out std_logic_vector(DATA_WIDTH-1 downto 0));
end component;
signal shiftReg_addr : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0);
signal shiftReg_data, shiftReg_q : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
signal shiftReg_ce : STD_LOGIC;
signal mOutPtr : STD_LOGIC_VECTOR(ADDR_WIDTH downto 0) := (others => '1');
signal internal_empty_n : STD_LOGIC := '0';
signal internal_full_n : STD_LOGIC := '1';
begin
if_empty_n <= internal_empty_n;
if_full_n <= internal_full_n;
shiftReg_data <= if_din;
if_dout <= shiftReg_q;
process (clk)
begin
if clk'event and clk = '1' then
if reset = '1' then
mOutPtr <= (others => '1');
internal_empty_n <= '0';
internal_full_n <= '1';
else
if ((if_read and if_read_ce) = '1' and internal_empty_n = '1') and
((if_write and if_write_ce) = '0' or internal_full_n = '0') then
mOutPtr <= mOutPtr -1;
if (mOutPtr = 0) then
internal_empty_n <= '0';
end if;
internal_full_n <= '1';
elsif ((if_read and if_read_ce) = '0' or internal_empty_n = '0') and
((if_write and if_write_ce) = '1' and internal_full_n = '1') then
mOutPtr <= mOutPtr +1;
internal_empty_n <= '1';
if (mOutPtr = DEPTH -2) then
internal_full_n <= '0';
end if;
end if;
end if;
end if;
end process;
shiftReg_addr <= (others => '0') when mOutPtr(ADDR_WIDTH) = '1' else mOutPtr(ADDR_WIDTH-1 downto 0);
shiftReg_ce <= (if_write and if_write_ce) and internal_full_n;
U_FIFO_image_filter_img_1_data_stream_0_V_shiftReg : FIFO_image_filter_img_1_data_stream_0_V_shiftReg
generic map (
DATA_WIDTH => DATA_WIDTH,
ADDR_WIDTH => ADDR_WIDTH,
DEPTH => DEPTH)
port map (
clk => clk,
data => shiftReg_data,
ce => shiftReg_ce,
a => shiftReg_addr,
q => shiftReg_q);
end rtl;
| gpl-3.0 |
mistryalok/Zedboard | learning/opencv_hls/xapp1167_vivado/sw/fast-corner/prj/solution1/impl/vhdl/FIFO_image_filter_p_dst_rows_V.vhd | 2 | 4564 | -- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.4
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity FIFO_image_filter_p_dst_rows_V_shiftReg is
generic (
DATA_WIDTH : integer := 12;
ADDR_WIDTH : integer := 2;
DEPTH : integer := 3);
port (
clk : in std_logic;
data : in std_logic_vector(DATA_WIDTH-1 downto 0);
ce : in std_logic;
a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
q : out std_logic_vector(DATA_WIDTH-1 downto 0));
end FIFO_image_filter_p_dst_rows_V_shiftReg;
architecture rtl of FIFO_image_filter_p_dst_rows_V_shiftReg is
--constant DEPTH_WIDTH: integer := 16;
type SRL_ARRAY is array (0 to DEPTH-1) of std_logic_vector(DATA_WIDTH-1 downto 0);
signal SRL_SIG : SRL_ARRAY;
begin
p_shift: process (clk)
begin
if (clk'event and clk = '1') then
if (ce = '1') then
SRL_SIG <= data & SRL_SIG(0 to DEPTH-2);
end if;
end if;
end process;
q <= SRL_SIG(conv_integer(a));
end rtl;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity FIFO_image_filter_p_dst_rows_V is
generic (
MEM_STYLE : string := "shiftreg";
DATA_WIDTH : integer := 12;
ADDR_WIDTH : integer := 2;
DEPTH : integer := 3);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_empty_n : OUT STD_LOGIC;
if_read_ce : IN STD_LOGIC;
if_read : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
if_full_n : OUT STD_LOGIC;
if_write_ce : IN STD_LOGIC;
if_write : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0));
end entity;
architecture rtl of FIFO_image_filter_p_dst_rows_V is
component FIFO_image_filter_p_dst_rows_V_shiftReg is
generic (
DATA_WIDTH : integer := 12;
ADDR_WIDTH : integer := 2;
DEPTH : integer := 3);
port (
clk : in std_logic;
data : in std_logic_vector(DATA_WIDTH-1 downto 0);
ce : in std_logic;
a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
q : out std_logic_vector(DATA_WIDTH-1 downto 0));
end component;
signal shiftReg_addr : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0);
signal shiftReg_data, shiftReg_q : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
signal shiftReg_ce : STD_LOGIC;
signal mOutPtr : STD_LOGIC_VECTOR(ADDR_WIDTH downto 0) := (others => '1');
signal internal_empty_n : STD_LOGIC := '0';
signal internal_full_n : STD_LOGIC := '1';
begin
if_empty_n <= internal_empty_n;
if_full_n <= internal_full_n;
shiftReg_data <= if_din;
if_dout <= shiftReg_q;
process (clk)
begin
if clk'event and clk = '1' then
if reset = '1' then
mOutPtr <= (others => '1');
internal_empty_n <= '0';
internal_full_n <= '1';
else
if ((if_read and if_read_ce) = '1' and internal_empty_n = '1') and
((if_write and if_write_ce) = '0' or internal_full_n = '0') then
mOutPtr <= mOutPtr -1;
if (mOutPtr = 0) then
internal_empty_n <= '0';
end if;
internal_full_n <= '1';
elsif ((if_read and if_read_ce) = '0' or internal_empty_n = '0') and
((if_write and if_write_ce) = '1' and internal_full_n = '1') then
mOutPtr <= mOutPtr +1;
internal_empty_n <= '1';
if (mOutPtr = DEPTH -2) then
internal_full_n <= '0';
end if;
end if;
end if;
end if;
end process;
shiftReg_addr <= (others => '0') when mOutPtr(ADDR_WIDTH) = '1' else mOutPtr(ADDR_WIDTH-1 downto 0);
shiftReg_ce <= (if_write and if_write_ce) and internal_full_n;
U_FIFO_image_filter_p_dst_rows_V_shiftReg : FIFO_image_filter_p_dst_rows_V_shiftReg
generic map (
DATA_WIDTH => DATA_WIDTH,
ADDR_WIDTH => ADDR_WIDTH,
DEPTH => DEPTH)
port map (
clk => clk,
data => shiftReg_data,
ce => shiftReg_ce,
a => shiftReg_addr,
q => shiftReg_q);
end rtl;
| gpl-3.0 |
mistryalok/Zedboard | learning/training/MSD/s09/axi_dma_sg/vivado/project_1/project_1.srcs/sources_1/ipshared/xilinx.com/lib_pkg_v1_0/cd7baeb2/hdl/src/vhdl/lib_pkg.vhd | 28 | 16351 | -- Processor Common Library Package
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2001-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: lib_pkg.vhd
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-- need conversion function to convert reals/integers to std logic vectors
use ieee.std_logic_arith.conv_std_logic_vector;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
package lib_pkg is
-------------------------------------------------------------------------------
-- Type Declarations
-------------------------------------------------------------------------------
type CHAR_TO_INT_TYPE is array (character) of integer;
-- type INTEGER_ARRAY_TYPE is array (natural range <>) of integer;
-- Type SLV64_ARRAY_TYPE is array (natural range <>) of std_logic_vector(0 to 63);
-------------------------------------------------------------------------------
-- Function and Procedure Declarations
-------------------------------------------------------------------------------
function max2 (num1, num2 : integer) return integer;
function min2 (num1, num2 : integer) return integer;
function Addr_Bits(x,y : std_logic_vector) return integer;
function clog2(x : positive) return natural;
function pad_power2 ( in_num : integer ) return integer;
function pad_4 ( in_num : integer ) return integer;
function log2(x : natural) return integer;
function pwr(x: integer; y: integer) return integer;
function String_To_Int(S : string) return integer;
function itoa (int : integer) return string;
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
-- the RESET_ACTIVE constant should denote the logic level of an active reset
constant RESET_ACTIVE : std_logic := '1';
-- table containing strings representing hex characters for conversion to
-- integers
constant STRHEX_TO_INT_TABLE : CHAR_TO_INT_TYPE :=
('0' => 0,
'1' => 1,
'2' => 2,
'3' => 3,
'4' => 4,
'5' => 5,
'6' => 6,
'7' => 7,
'8' => 8,
'9' => 9,
'A'|'a' => 10,
'B'|'b' => 11,
'C'|'c' => 12,
'D'|'d' => 13,
'E'|'e' => 14,
'F'|'f' => 15,
others => -1);
end lib_pkg;
package body lib_pkg is
-------------------------------------------------------------------------------
-- Function Definitions
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Function max2
--
-- This function returns the greater of two numbers.
-------------------------------------------------------------------------------
function max2 (num1, num2 : integer) return integer is
begin
if num1 >= num2 then
return num1;
else
return num2;
end if;
end function max2;
-------------------------------------------------------------------------------
-- Function min2
--
-- This function returns the lesser of two numbers.
-------------------------------------------------------------------------------
function min2 (num1, num2 : integer) return integer is
begin
if num1 <= num2 then
return num1;
else
return num2;
end if;
end function min2;
-------------------------------------------------------------------------------
-- Function Addr_bits
--
-- function to convert an address range (base address and an upper address)
-- into the number of upper address bits needed for decoding a device
-- select signal. will handle slices and big or little endian
-------------------------------------------------------------------------------
function Addr_Bits(x,y : std_logic_vector) return integer is
variable addr_xor : std_logic_vector(x'range);
variable count : integer := 0;
begin
assert x'length = y'length and (x'ascending xnor y'ascending)
report "Addr_Bits: arguments are not the same type"
severity ERROR;
addr_xor := x xor y;
for i in x'range
loop
if addr_xor(i) = '1' then return count;
end if;
count := count + 1;
end loop;
return x'length;
end Addr_Bits;
--------------------------------------------------------------------------------
-- Function clog2 - returns the integer ceiling of the base 2 logarithm of x,
-- i.e., the least integer greater than or equal to log2(x).
--------------------------------------------------------------------------------
function clog2(x : positive) return natural is
variable r : natural := 0;
variable rp : natural := 1; -- rp tracks the value 2**r
begin
while rp < x loop -- Termination condition T: x <= 2**r
-- Loop invariant L: 2**(r-1) < x
r := r + 1;
if rp > integer'high - rp then exit; end if; -- If doubling rp overflows
-- the integer range, the doubled value would exceed x, so safe to exit.
rp := rp + rp;
end loop;
-- L and T <-> 2**(r-1) < x <= 2**r <-> (r-1) < log2(x) <= r
return r; --
end clog2;
-------------------------------------------------------------------------------
-- Function pad_power2
--
-- This function returns the next power of 2 from the input number. If the
-- input number is a power of 2, this function returns the input number.
--
-- This function is used to round up the number of masters to the next power
-- of 2 if the number of masters is not already a power of 2.
--
-- Input argument 0, which is not a power of two, is accepted and returns 0.
-- Input arguments less than 0 are not allowed.
-------------------------------------------------------------------------------
--
function pad_power2 (in_num : integer ) return integer is
begin
if in_num = 0 then
return 0;
else
return 2**(clog2(in_num));
end if;
end pad_power2;
-------------------------------------------------------------------------------
-- Function pad_4
--
-- This function returns the next multiple of 4 from the input number. If the
-- input number is a multiple of 4, this function returns the input number.
--
-------------------------------------------------------------------------------
--
function pad_4 (in_num : integer ) return integer is
variable out_num : integer;
begin
out_num := (((in_num-1)/4) + 1)*4;
return out_num;
end pad_4;
-------------------------------------------------------------------------------
-- Function log2 -- returns number of bits needed to encode x choices
-- x = 0 returns 0
-- x = 1 returns 0
-- x = 2 returns 1
-- x = 4 returns 2, etc.
-------------------------------------------------------------------------------
--
function log2(x : natural) return integer is
variable i : integer := 0;
variable val: integer := 1;
begin
if x = 0 then return 0;
else
for j in 0 to 29 loop -- for loop for XST
if val >= x then null;
else
i := i+1;
val := val*2;
end if;
end loop;
-- Fix per CR520627 XST was ignoring this anyway and printing a
-- Warning in SRP file. This will get rid of the warning and not
-- impact simulation.
-- synthesis translate_off
assert val >= x
report "Function log2 received argument larger" &
" than its capability of 2^30. "
severity failure;
-- synthesis translate_on
return i;
end if;
end function log2;
-------------------------------------------------------------------------------
-- Function pwr -- x**y
-- negative numbers not allowed for y
-------------------------------------------------------------------------------
function pwr(x: integer; y: integer) return integer is
variable z : integer := 1;
begin
if y = 0 then return 1;
else
for i in 1 to y loop
z := z * x;
end loop;
return z;
end if;
end function pwr;
-------------------------------------------------------------------------------
-- Function itoa
--
-- The itoa function converts an integer to a text string.
-- This function is required since `image doesn't work in Synplicity
-- Valid input range is -9999 to 9999
-------------------------------------------------------------------------------
--
function itoa (int : integer) return string is
type table is array (0 to 9) of string (1 to 1);
constant LUT : table :=
("0", "1", "2", "3", "4", "5", "6", "7", "8", "9");
variable str1 : string(1 to 1);
variable str2 : string(1 to 2);
variable str3 : string(1 to 3);
variable str4 : string(1 to 4);
variable str5 : string(1 to 5);
variable abs_int : natural;
variable thousands_place : natural;
variable hundreds_place : natural;
variable tens_place : natural;
variable ones_place : natural;
variable sign : integer;
begin
abs_int := abs(int);
if abs_int > int then sign := -1;
else sign := 1;
end if;
thousands_place := abs_int/1000;
hundreds_place := (abs_int-thousands_place*1000)/100;
tens_place := (abs_int-thousands_place*1000-hundreds_place*100)/10;
ones_place :=
(abs_int-thousands_place*1000-hundreds_place*100-tens_place*10);
if sign>0 then
if thousands_place>0 then
str4 := LUT(thousands_place) & LUT(hundreds_place) & LUT(tens_place) &
LUT(ones_place);
return str4;
elsif hundreds_place>0 then
str3 := LUT(hundreds_place) & LUT(tens_place) & LUT(ones_place);
return str3;
elsif tens_place>0 then
str2 := LUT(tens_place) & LUT(ones_place);
return str2;
else
str1 := LUT(ones_place);
return str1;
end if;
else
if thousands_place>0 then
str5 := "-" & LUT(thousands_place) & LUT(hundreds_place) &
LUT(tens_place) & LUT(ones_place);
return str5;
elsif hundreds_place>0 then
str4 := "-" & LUT(hundreds_place) & LUT(tens_place) & LUT(ones_place);
return str4;
elsif tens_place>0 then
str3 := "-" & LUT(tens_place) & LUT(ones_place);
return str3;
else
str2 := "-" & LUT(ones_place);
return str2;
end if;
end if;
end itoa;
-----------------------------------------------------------------------------
-- Function String_To_Int
--
-- Converts a string of hex character to an integer
-- accept negative numbers
-----------------------------------------------------------------------------
function String_To_Int(S : String) return Integer is
variable Result : integer := 0;
variable Temp : integer := S'Left;
variable Negative : integer := 1;
begin
for I in S'Left to S'Right loop
if (S(I) = '-') then
Temp := 0;
Negative := -1;
else
Temp := STRHEX_TO_INT_TABLE(S(I));
if (Temp = -1) then
assert false
report "Wrong value in String_To_Int conversion " & S(I)
severity error;
end if;
end if;
Result := Result * 16 + Temp;
end loop;
return (Negative * Result);
end String_To_Int;
end package body lib_pkg;
| gpl-3.0 |
mistryalok/Zedboard | learning/opencv_hls/xapp1167_vivado/sw/median/prj/solution1/syn/vhdl/image_filter_Mat2AXIvideo.vhd | 2 | 23118 | -- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.4
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity image_filter_Mat2AXIvideo is
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_continue : IN STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
img_rows_V_read : IN STD_LOGIC_VECTOR (11 downto 0);
img_cols_V_read : IN STD_LOGIC_VECTOR (11 downto 0);
img_data_stream_0_V_dout : IN STD_LOGIC_VECTOR (7 downto 0);
img_data_stream_0_V_empty_n : IN STD_LOGIC;
img_data_stream_0_V_read : OUT STD_LOGIC;
img_data_stream_1_V_dout : IN STD_LOGIC_VECTOR (7 downto 0);
img_data_stream_1_V_empty_n : IN STD_LOGIC;
img_data_stream_1_V_read : OUT STD_LOGIC;
img_data_stream_2_V_dout : IN STD_LOGIC_VECTOR (7 downto 0);
img_data_stream_2_V_empty_n : IN STD_LOGIC;
img_data_stream_2_V_read : OUT STD_LOGIC;
OUTPUT_STREAM_TDATA : OUT STD_LOGIC_VECTOR (31 downto 0);
OUTPUT_STREAM_TVALID : OUT STD_LOGIC;
OUTPUT_STREAM_TREADY : IN STD_LOGIC;
OUTPUT_STREAM_TKEEP : OUT STD_LOGIC_VECTOR (3 downto 0);
OUTPUT_STREAM_TSTRB : OUT STD_LOGIC_VECTOR (3 downto 0);
OUTPUT_STREAM_TUSER : OUT STD_LOGIC_VECTOR (0 downto 0);
OUTPUT_STREAM_TLAST : OUT STD_LOGIC_VECTOR (0 downto 0);
OUTPUT_STREAM_TID : OUT STD_LOGIC_VECTOR (0 downto 0);
OUTPUT_STREAM_TDEST : OUT STD_LOGIC_VECTOR (0 downto 0) );
end;
architecture behav of image_filter_Mat2AXIvideo is
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_st1_fsm_0 : STD_LOGIC_VECTOR (3 downto 0) := "0001";
constant ap_ST_st2_fsm_1 : STD_LOGIC_VECTOR (3 downto 0) := "0010";
constant ap_ST_pp0_stg0_fsm_2 : STD_LOGIC_VECTOR (3 downto 0) := "0100";
constant ap_ST_st5_fsm_3 : STD_LOGIC_VECTOR (3 downto 0) := "1000";
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
constant ap_const_lv1_1 : STD_LOGIC_VECTOR (0 downto 0) := "1";
constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
constant ap_const_lv32_2 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000010";
constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0";
constant ap_const_lv12_0 : STD_LOGIC_VECTOR (11 downto 0) := "000000000000";
constant ap_const_lv32_3 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000011";
constant ap_const_lv4_F : STD_LOGIC_VECTOR (3 downto 0) := "1111";
constant ap_const_lv4_0 : STD_LOGIC_VECTOR (3 downto 0) := "0000";
constant ap_const_lv13_1FFF : STD_LOGIC_VECTOR (12 downto 0) := "1111111111111";
constant ap_const_lv12_1 : STD_LOGIC_VECTOR (11 downto 0) := "000000000001";
constant ap_const_lv8_FF : STD_LOGIC_VECTOR (7 downto 0) := "11111111";
signal ap_done_reg : STD_LOGIC := '0';
signal ap_CS_fsm : STD_LOGIC_VECTOR (3 downto 0) := "0001";
attribute fsm_encoding : string;
attribute fsm_encoding of ap_CS_fsm : signal is "none";
signal ap_sig_cseq_ST_st1_fsm_0 : STD_LOGIC;
signal ap_sig_bdd_23 : BOOLEAN;
signal p_3_reg_170 : STD_LOGIC_VECTOR (11 downto 0);
signal ap_sig_bdd_60 : BOOLEAN;
signal op2_assign_fu_186_p2 : STD_LOGIC_VECTOR (12 downto 0);
signal op2_assign_reg_267 : STD_LOGIC_VECTOR (12 downto 0);
signal exitcond3_fu_197_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_sig_cseq_ST_st2_fsm_1 : STD_LOGIC;
signal ap_sig_bdd_74 : BOOLEAN;
signal i_V_fu_202_p2 : STD_LOGIC_VECTOR (11 downto 0);
signal i_V_reg_276 : STD_LOGIC_VECTOR (11 downto 0);
signal exitcond4_fu_208_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal exitcond4_reg_281 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_sig_cseq_ST_pp0_stg0_fsm_2 : STD_LOGIC;
signal ap_sig_bdd_85 : BOOLEAN;
signal ap_reg_ppiten_pp0_it0 : STD_LOGIC := '0';
signal ap_sig_bdd_99 : BOOLEAN;
signal ap_sig_ioackin_OUTPUT_STREAM_TREADY : STD_LOGIC;
signal ap_reg_ppiten_pp0_it1 : STD_LOGIC := '0';
signal j_V_fu_213_p2 : STD_LOGIC_VECTOR (11 downto 0);
signal axi_last_V_fu_223_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal axi_last_V_reg_290 : STD_LOGIC_VECTOR (0 downto 0);
signal p_s_reg_159 : STD_LOGIC_VECTOR (11 downto 0);
signal ap_sig_cseq_ST_st5_fsm_3 : STD_LOGIC;
signal ap_sig_bdd_130 : BOOLEAN;
signal tmp_user_V_fu_96 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ioackin_OUTPUT_STREAM_TREADY : STD_LOGIC := '0';
signal tmp_cast_fu_182_p1 : STD_LOGIC_VECTOR (12 downto 0);
signal tmp_cast_35_fu_219_p1 : STD_LOGIC_VECTOR (12 downto 0);
signal ap_NS_fsm : STD_LOGIC_VECTOR (3 downto 0);
begin
-- the current state (ap_CS_fsm) of the state machine. --
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_CS_fsm <= ap_ST_st1_fsm_0;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
-- ap_done_reg assign process. --
ap_done_reg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_done_reg <= ap_const_logic_0;
else
if ((ap_const_logic_1 = ap_continue)) then
ap_done_reg <= ap_const_logic_0;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and not((exitcond3_fu_197_p2 = ap_const_lv1_0)))) then
ap_done_reg <= ap_const_logic_1;
end if;
end if;
end if;
end process;
-- ap_reg_ioackin_OUTPUT_STREAM_TREADY assign process. --
ap_reg_ioackin_OUTPUT_STREAM_TREADY_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ioackin_OUTPUT_STREAM_TREADY <= ap_const_logic_0;
else
if ((((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and (exitcond4_reg_281 = ap_const_lv1_0) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and not(((ap_sig_bdd_99 or ((exitcond4_reg_281 = ap_const_lv1_0) and (ap_const_logic_0 = ap_sig_ioackin_OUTPUT_STREAM_TREADY))) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)))))) then
ap_reg_ioackin_OUTPUT_STREAM_TREADY <= ap_const_logic_0;
elsif ((((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and (exitcond4_reg_281 = ap_const_lv1_0) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and not((ap_sig_bdd_99 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1))) and (ap_const_logic_1 = OUTPUT_STREAM_TREADY)))) then
ap_reg_ioackin_OUTPUT_STREAM_TREADY <= ap_const_logic_1;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it0 assign process. --
ap_reg_ppiten_pp0_it0_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it0 <= ap_const_logic_0;
else
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and not(((ap_sig_bdd_99 or ((exitcond4_reg_281 = ap_const_lv1_0) and (ap_const_logic_0 = ap_sig_ioackin_OUTPUT_STREAM_TREADY))) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1))) and not((exitcond4_fu_208_p2 = ap_const_lv1_0)))) then
ap_reg_ppiten_pp0_it0 <= ap_const_logic_0;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and (exitcond3_fu_197_p2 = ap_const_lv1_0))) then
ap_reg_ppiten_pp0_it0 <= ap_const_logic_1;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it1 assign process. --
ap_reg_ppiten_pp0_it1_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it1 <= ap_const_logic_0;
else
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and not(((ap_sig_bdd_99 or ((exitcond4_reg_281 = ap_const_lv1_0) and (ap_const_logic_0 = ap_sig_ioackin_OUTPUT_STREAM_TREADY))) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1))) and (exitcond4_fu_208_p2 = ap_const_lv1_0))) then
ap_reg_ppiten_pp0_it1 <= ap_const_logic_1;
elsif ((((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and (exitcond3_fu_197_p2 = ap_const_lv1_0)) or ((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and not(((ap_sig_bdd_99 or ((exitcond4_reg_281 = ap_const_lv1_0) and (ap_const_logic_0 = ap_sig_ioackin_OUTPUT_STREAM_TREADY))) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1))) and not((exitcond4_fu_208_p2 = ap_const_lv1_0))))) then
ap_reg_ppiten_pp0_it1 <= ap_const_logic_0;
end if;
end if;
end if;
end process;
-- p_3_reg_170 assign process. --
p_3_reg_170_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not(((ap_sig_bdd_99 or ((exitcond4_reg_281 = ap_const_lv1_0) and (ap_const_logic_0 = ap_sig_ioackin_OUTPUT_STREAM_TREADY))) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1))) and (exitcond4_fu_208_p2 = ap_const_lv1_0))) then
p_3_reg_170 <= j_V_fu_213_p2;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and (exitcond3_fu_197_p2 = ap_const_lv1_0))) then
p_3_reg_170 <= ap_const_lv12_0;
end if;
end if;
end process;
-- p_s_reg_159 assign process. --
p_s_reg_159_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st5_fsm_3)) then
p_s_reg_159 <= i_V_reg_276;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not(ap_sig_bdd_60))) then
p_s_reg_159 <= ap_const_lv12_0;
end if;
end if;
end process;
-- tmp_user_V_fu_96 assign process. --
tmp_user_V_fu_96_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and (exitcond4_reg_281 = ap_const_lv1_0) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and not(((ap_sig_bdd_99 or ((exitcond4_reg_281 = ap_const_lv1_0) and (ap_const_logic_0 = ap_sig_ioackin_OUTPUT_STREAM_TREADY))) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1))))) then
tmp_user_V_fu_96 <= ap_const_lv1_0;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not(ap_sig_bdd_60))) then
tmp_user_V_fu_96 <= ap_const_lv1_1;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and not(((ap_sig_bdd_99 or ((exitcond4_reg_281 = ap_const_lv1_0) and (ap_const_logic_0 = ap_sig_ioackin_OUTPUT_STREAM_TREADY))) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1))) and (exitcond4_fu_208_p2 = ap_const_lv1_0))) then
axi_last_V_reg_290 <= axi_last_V_fu_223_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and not(((ap_sig_bdd_99 or ((exitcond4_reg_281 = ap_const_lv1_0) and (ap_const_logic_0 = ap_sig_ioackin_OUTPUT_STREAM_TREADY))) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1))))) then
exitcond4_reg_281 <= exitcond4_fu_208_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1)) then
i_V_reg_276 <= i_V_fu_202_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not(ap_sig_bdd_60))) then
op2_assign_reg_267 <= op2_assign_fu_186_p2;
end if;
end if;
end process;
-- the next state (ap_NS_fsm) of the state machine. --
ap_NS_fsm_assign_proc : process (ap_CS_fsm, ap_sig_bdd_60, exitcond3_fu_197_p2, exitcond4_fu_208_p2, exitcond4_reg_281, ap_reg_ppiten_pp0_it0, ap_sig_bdd_99, ap_sig_ioackin_OUTPUT_STREAM_TREADY, ap_reg_ppiten_pp0_it1)
begin
case ap_CS_fsm is
when ap_ST_st1_fsm_0 =>
if (not(ap_sig_bdd_60)) then
ap_NS_fsm <= ap_ST_st2_fsm_1;
else
ap_NS_fsm <= ap_ST_st1_fsm_0;
end if;
when ap_ST_st2_fsm_1 =>
if (not((exitcond3_fu_197_p2 = ap_const_lv1_0))) then
ap_NS_fsm <= ap_ST_st1_fsm_0;
else
ap_NS_fsm <= ap_ST_pp0_stg0_fsm_2;
end if;
when ap_ST_pp0_stg0_fsm_2 =>
if (not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not(((ap_sig_bdd_99 or ((exitcond4_reg_281 = ap_const_lv1_0) and (ap_const_logic_0 = ap_sig_ioackin_OUTPUT_STREAM_TREADY))) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1))) and not((exitcond4_fu_208_p2 = ap_const_lv1_0))))) then
ap_NS_fsm <= ap_ST_pp0_stg0_fsm_2;
elsif (((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not(((ap_sig_bdd_99 or ((exitcond4_reg_281 = ap_const_lv1_0) and (ap_const_logic_0 = ap_sig_ioackin_OUTPUT_STREAM_TREADY))) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1))) and not((exitcond4_fu_208_p2 = ap_const_lv1_0)))) then
ap_NS_fsm <= ap_ST_st5_fsm_3;
else
ap_NS_fsm <= ap_ST_pp0_stg0_fsm_2;
end if;
when ap_ST_st5_fsm_3 =>
ap_NS_fsm <= ap_ST_st2_fsm_1;
when others =>
ap_NS_fsm <= "XXXX";
end case;
end process;
OUTPUT_STREAM_TDATA <= (((ap_const_lv8_FF & img_data_stream_2_V_dout) & img_data_stream_1_V_dout) & img_data_stream_0_V_dout);
OUTPUT_STREAM_TDEST <= ap_const_lv1_0;
OUTPUT_STREAM_TID <= ap_const_lv1_0;
OUTPUT_STREAM_TKEEP <= ap_const_lv4_F;
OUTPUT_STREAM_TLAST <= axi_last_V_reg_290;
OUTPUT_STREAM_TSTRB <= ap_const_lv4_0;
OUTPUT_STREAM_TUSER <= tmp_user_V_fu_96;
-- OUTPUT_STREAM_TVALID assign process. --
OUTPUT_STREAM_TVALID_assign_proc : process(exitcond4_reg_281, ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_sig_bdd_99, ap_reg_ppiten_pp0_it1, ap_reg_ioackin_OUTPUT_STREAM_TREADY)
begin
if ((((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and (exitcond4_reg_281 = ap_const_lv1_0) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and not((ap_sig_bdd_99 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1))) and (ap_const_logic_0 = ap_reg_ioackin_OUTPUT_STREAM_TREADY)))) then
OUTPUT_STREAM_TVALID <= ap_const_logic_1;
else
OUTPUT_STREAM_TVALID <= ap_const_logic_0;
end if;
end process;
-- ap_done assign process. --
ap_done_assign_proc : process(ap_done_reg, exitcond3_fu_197_p2, ap_sig_cseq_ST_st2_fsm_1)
begin
if (((ap_const_logic_1 = ap_done_reg) or ((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and not((exitcond3_fu_197_p2 = ap_const_lv1_0))))) then
ap_done <= ap_const_logic_1;
else
ap_done <= ap_const_logic_0;
end if;
end process;
-- ap_idle assign process. --
ap_idle_assign_proc : process(ap_start, ap_sig_cseq_ST_st1_fsm_0)
begin
if ((not((ap_const_logic_1 = ap_start)) and (ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0))) then
ap_idle <= ap_const_logic_1;
else
ap_idle <= ap_const_logic_0;
end if;
end process;
-- ap_ready assign process. --
ap_ready_assign_proc : process(exitcond3_fu_197_p2, ap_sig_cseq_ST_st2_fsm_1)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and not((exitcond3_fu_197_p2 = ap_const_lv1_0)))) then
ap_ready <= ap_const_logic_1;
else
ap_ready <= ap_const_logic_0;
end if;
end process;
-- ap_sig_bdd_130 assign process. --
ap_sig_bdd_130_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_130 <= (ap_const_lv1_1 = ap_CS_fsm(3 downto 3));
end process;
-- ap_sig_bdd_23 assign process. --
ap_sig_bdd_23_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_23 <= (ap_CS_fsm(0 downto 0) = ap_const_lv1_1);
end process;
-- ap_sig_bdd_60 assign process. --
ap_sig_bdd_60_assign_proc : process(ap_start, ap_done_reg)
begin
ap_sig_bdd_60 <= ((ap_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1));
end process;
-- ap_sig_bdd_74 assign process. --
ap_sig_bdd_74_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_74 <= (ap_const_lv1_1 = ap_CS_fsm(1 downto 1));
end process;
-- ap_sig_bdd_85 assign process. --
ap_sig_bdd_85_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_85 <= (ap_const_lv1_1 = ap_CS_fsm(2 downto 2));
end process;
-- ap_sig_bdd_99 assign process. --
ap_sig_bdd_99_assign_proc : process(img_data_stream_0_V_empty_n, img_data_stream_1_V_empty_n, img_data_stream_2_V_empty_n, exitcond4_reg_281)
begin
ap_sig_bdd_99 <= (((img_data_stream_0_V_empty_n = ap_const_logic_0) and (exitcond4_reg_281 = ap_const_lv1_0)) or ((exitcond4_reg_281 = ap_const_lv1_0) and (img_data_stream_1_V_empty_n = ap_const_logic_0)) or ((exitcond4_reg_281 = ap_const_lv1_0) and (img_data_stream_2_V_empty_n = ap_const_logic_0)));
end process;
-- ap_sig_cseq_ST_pp0_stg0_fsm_2 assign process. --
ap_sig_cseq_ST_pp0_stg0_fsm_2_assign_proc : process(ap_sig_bdd_85)
begin
if (ap_sig_bdd_85) then
ap_sig_cseq_ST_pp0_stg0_fsm_2 <= ap_const_logic_1;
else
ap_sig_cseq_ST_pp0_stg0_fsm_2 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st1_fsm_0 assign process. --
ap_sig_cseq_ST_st1_fsm_0_assign_proc : process(ap_sig_bdd_23)
begin
if (ap_sig_bdd_23) then
ap_sig_cseq_ST_st1_fsm_0 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st1_fsm_0 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st2_fsm_1 assign process. --
ap_sig_cseq_ST_st2_fsm_1_assign_proc : process(ap_sig_bdd_74)
begin
if (ap_sig_bdd_74) then
ap_sig_cseq_ST_st2_fsm_1 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st2_fsm_1 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st5_fsm_3 assign process. --
ap_sig_cseq_ST_st5_fsm_3_assign_proc : process(ap_sig_bdd_130)
begin
if (ap_sig_bdd_130) then
ap_sig_cseq_ST_st5_fsm_3 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st5_fsm_3 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_ioackin_OUTPUT_STREAM_TREADY assign process. --
ap_sig_ioackin_OUTPUT_STREAM_TREADY_assign_proc : process(OUTPUT_STREAM_TREADY, ap_reg_ioackin_OUTPUT_STREAM_TREADY)
begin
if ((ap_const_logic_0 = ap_reg_ioackin_OUTPUT_STREAM_TREADY)) then
ap_sig_ioackin_OUTPUT_STREAM_TREADY <= OUTPUT_STREAM_TREADY;
else
ap_sig_ioackin_OUTPUT_STREAM_TREADY <= ap_const_logic_1;
end if;
end process;
axi_last_V_fu_223_p2 <= "1" when (tmp_cast_35_fu_219_p1 = op2_assign_reg_267) else "0";
exitcond3_fu_197_p2 <= "1" when (p_s_reg_159 = img_rows_V_read) else "0";
exitcond4_fu_208_p2 <= "1" when (p_3_reg_170 = img_cols_V_read) else "0";
i_V_fu_202_p2 <= std_logic_vector(unsigned(p_s_reg_159) + unsigned(ap_const_lv12_1));
-- img_data_stream_0_V_read assign process. --
img_data_stream_0_V_read_assign_proc : process(exitcond4_reg_281, ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_sig_bdd_99, ap_sig_ioackin_OUTPUT_STREAM_TREADY, ap_reg_ppiten_pp0_it1)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and (exitcond4_reg_281 = ap_const_lv1_0) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and not(((ap_sig_bdd_99 or ((exitcond4_reg_281 = ap_const_lv1_0) and (ap_const_logic_0 = ap_sig_ioackin_OUTPUT_STREAM_TREADY))) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1))))) then
img_data_stream_0_V_read <= ap_const_logic_1;
else
img_data_stream_0_V_read <= ap_const_logic_0;
end if;
end process;
-- img_data_stream_1_V_read assign process. --
img_data_stream_1_V_read_assign_proc : process(exitcond4_reg_281, ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_sig_bdd_99, ap_sig_ioackin_OUTPUT_STREAM_TREADY, ap_reg_ppiten_pp0_it1)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and (exitcond4_reg_281 = ap_const_lv1_0) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and not(((ap_sig_bdd_99 or ((exitcond4_reg_281 = ap_const_lv1_0) and (ap_const_logic_0 = ap_sig_ioackin_OUTPUT_STREAM_TREADY))) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1))))) then
img_data_stream_1_V_read <= ap_const_logic_1;
else
img_data_stream_1_V_read <= ap_const_logic_0;
end if;
end process;
-- img_data_stream_2_V_read assign process. --
img_data_stream_2_V_read_assign_proc : process(exitcond4_reg_281, ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_sig_bdd_99, ap_sig_ioackin_OUTPUT_STREAM_TREADY, ap_reg_ppiten_pp0_it1)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and (exitcond4_reg_281 = ap_const_lv1_0) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and not(((ap_sig_bdd_99 or ((exitcond4_reg_281 = ap_const_lv1_0) and (ap_const_logic_0 = ap_sig_ioackin_OUTPUT_STREAM_TREADY))) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1))))) then
img_data_stream_2_V_read <= ap_const_logic_1;
else
img_data_stream_2_V_read <= ap_const_logic_0;
end if;
end process;
j_V_fu_213_p2 <= std_logic_vector(unsigned(p_3_reg_170) + unsigned(ap_const_lv12_1));
op2_assign_fu_186_p2 <= std_logic_vector(unsigned(tmp_cast_fu_182_p1) + unsigned(ap_const_lv13_1FFF));
tmp_cast_35_fu_219_p1 <= std_logic_vector(resize(unsigned(p_3_reg_170),13));
tmp_cast_fu_182_p1 <= std_logic_vector(resize(unsigned(img_cols_V_read),13));
end behav;
| gpl-3.0 |
freecores/usb_fpga_1_11 | examples/usb-fpga-1.15/1.15a/lightshow/fpga/lightshow.vhd | 36 | 2235 | library ieee;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity lightshow is
port(
led : out std_logic_vector(11 downto 0);
CLK : in std_logic -- 32 MHz
);
end lightshow;
--signal declaration
architecture RTL of lightshow is
type tPattern is array(11 downto 0) of integer range 0 to 15;
signal pattern1 : tPattern := (0, 1, 2, 3, 4, 5, 6, 5, 4, 3, 2, 1);
signal pattern2 : tPattern := (6, 5, 4, 3, 2, 1, 0, 1, 2, 3, 4, 5);
signal pattern3 : tPattern := (0, 1, 4, 9, 4, 1, 0, 0, 0, 0, 0, 0);
type tXlatTable1 is array(0 to 12) of integer range 0 to 1023;
constant xt1 : tXlatTable1 := (0, 0, 1, 4, 13, 31, 64, 118, 202, 324, 493, 722, 1023);
type tXlatTable2 is array(0 to 9) of integer range 0 to 255;
--constant xt2 : tXlatTable2 := (0, 1, 11, 38, 90, 175, 303, 481, 718, 1023);
constant xt2 : tXlatTable2 := (0, 0, 3, 9, 22, 44, 76, 120, 179, 255);
signal cp1 : std_logic_vector(22 downto 0);
signal cp2 : std_logic_vector(22 downto 0);
signal cp3 : std_logic_vector(22 downto 0);
signal d : std_logic_vector(16 downto 0);
begin
dpCLK: process(CLK)
begin
if CLK' event and CLK = '1' then
if ( cp1 = conv_std_logic_vector(3000000,23) )
then
pattern1(10 downto 0) <= pattern1(11 downto 1);
pattern1(11) <= pattern1(0);
cp1 <= (others => '0');
else
cp1 <= cp1 + 1;
end if;
if ( cp2 = conv_std_logic_vector(2200000,23) )
then
pattern2(10 downto 0) <= pattern2(11 downto 1);
pattern2(11) <= pattern2(0);
cp2 <= (others => '0');
else
cp2 <= cp2 + 1;
end if;
if ( cp3 = conv_std_logic_vector(1500000,23) )
then
pattern3(11 downto 1) <= pattern3(10 downto 0);
pattern3(0) <= pattern3(11);
cp3 <= (others => '0');
else
cp3 <= cp3 + 1;
end if;
if ( d = conv_std_logic_vector(1278*64-1,17) )
then
d <= (others => '0');
else
d <= d + 1;
end if;
for i in 0 to 11 loop
if ( d(16 downto 6) < conv_std_logic_vector( xt1(pattern1(i) + pattern2(i)) + xt2(pattern3(i)) ,11) )
then
led(i) <= '1';
else
led(i) <= '0';
end if;
end loop;
end if;
end process dpCLK;
end RTL;
| gpl-3.0 |
mistryalok/Zedboard | learning/training/MSD/s05/project_1/project_1.srcs/sources_1/ipshared/xilinx.com/axi_sg_v4_1/0535f152/hdl/src/vhdl/axi_sg_cntrl_strm.vhd | 4 | 25017 | -- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_cntrl_strm.vhd
-- Description: This entity is MM2S control stream logic
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_sg_v4_1;
use axi_sg_v4_1.axi_sg_pkg.all;
library lib_fifo_v1_0;
library lib_cdc_v1_0;
library lib_pkg_v1_0;
use lib_pkg_v1_0.lib_pkg.clog2;
use lib_pkg_v1_0.lib_pkg.max2;
-------------------------------------------------------------------------------
entity axi_sg_cntrl_strm is
generic(
C_PRMRY_IS_ACLK_ASYNC : integer range 0 to 1 := 0;
-- Primary MM2S/S2MM sync/async mode
-- 0 = synchronous mode - all clocks are synchronous
-- 1 = asynchronous mode - Primary data path channels (MM2S and S2MM)
-- run asynchronous to AXI Lite, DMA Control,
-- and SG.
C_PRMY_CMDFIFO_DEPTH : integer range 1 to 16 := 1;
-- Depth of DataMover command FIFO
C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH : integer range 32 to 32 := 32;
-- Master AXI Control Stream Data Width
C_FAMILY : string := "virtex7"
-- Target FPGA Device Family
);
port (
-- Secondary clock / reset
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
-- Primary clock / reset --
axi_prmry_aclk : in std_logic ; --
p_reset_n : in std_logic ; --
--
-- MM2S Error --
mm2s_stop : in std_logic ; --
--
-- Control Stream FIFO write signals (from axi_dma_mm2s_sg_if) --
cntrlstrm_fifo_wren : in std_logic ; --
cntrlstrm_fifo_din : in std_logic_vector --
(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH downto 0); --
cntrlstrm_fifo_full : out std_logic ; --
--
--
-- Memory Map to Stream Control Stream Interface --
m_axis_mm2s_cntrl_tdata : out std_logic_vector --
(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH-1 downto 0); --
m_axis_mm2s_cntrl_tkeep : out std_logic_vector --
((C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH/8)-1 downto 0);--
m_axis_mm2s_cntrl_tvalid : out std_logic ; --
m_axis_mm2s_cntrl_tready : in std_logic ; --
m_axis_mm2s_cntrl_tlast : out std_logic --
);
end axi_sg_cntrl_strm;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_sg_cntrl_strm is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- Number of words deep fifo needs to be
-- Only 5 app fields, but set to 8 so depth is a power of 2
constant CNTRL_FIFO_DEPTH : integer := max2(16,8 * C_PRMY_CMDFIFO_DEPTH);
-- Width of fifo rd and wr counts - only used for proper fifo operation
constant CNTRL_FIFO_CNT_WIDTH : integer := clog2(CNTRL_FIFO_DEPTH+1);
constant USE_LOGIC_FIFOS : integer := 0; -- Use Logic FIFOs
constant USE_BRAM_FIFOS : integer := 1; -- Use BRAM FIFOs
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
-- FIFO signals
signal cntrl_fifo_rden : std_logic := '0';
signal cntrl_fifo_empty : std_logic := '0';
signal cntrl_fifo_dout, follower_reg_mm2s : std_logic_vector
(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH downto 0) := (others => '0');
signal cntrl_fifo_dvalid: std_logic := '0';
signal cntrl_tdata : std_logic_vector
(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH-1 downto 0) := (others => '0');
signal cntrl_tkeep : std_logic_vector
((C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal follower_full_mm2s, follower_empty_mm2s : std_logic := '0';
signal cntrl_tvalid : std_logic := '0';
signal cntrl_tready : std_logic := '0';
signal cntrl_tlast : std_logic := '0';
signal sinit : std_logic := '0';
signal m_valid : std_logic := '0';
signal m_ready : std_logic := '0';
signal m_data : std_logic_vector(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH-1 downto 0) := (others => '0');
signal m_strb : std_logic_vector((C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal m_last : std_logic := '0';
signal skid_rst : std_logic := '0';
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
-- All bytes always valid
cntrl_tkeep <= (others => '1');
-- Primary Clock is synchronous to Secondary Clock therfore
-- instantiate a sync fifo.
GEN_SYNC_FIFO : if C_PRMRY_IS_ACLK_ASYNC = 0 generate
signal mm2s_stop_d1 : std_logic := '0';
signal mm2s_stop_re : std_logic := '0';
signal xfer_in_progress : std_logic := '0';
begin
-- reset on hard reset or mm2s stop
sinit <= not m_axi_sg_aresetn or mm2s_stop;
-- Generate Synchronous FIFO
I_CNTRL_FIFO : entity lib_fifo_v1_0.sync_fifo_fg
generic map (
C_FAMILY => C_FAMILY ,
C_MEMORY_TYPE => USE_LOGIC_FIFOS,
C_WRITE_DATA_WIDTH => C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH + 1,
C_WRITE_DEPTH => CNTRL_FIFO_DEPTH ,
C_READ_DATA_WIDTH => C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH + 1,
C_READ_DEPTH => CNTRL_FIFO_DEPTH ,
C_PORTS_DIFFER => 0,
C_HAS_DCOUNT => 0, --req for proper fifo operation
C_HAS_ALMOST_FULL => 0,
C_HAS_RD_ACK => 0,
C_HAS_RD_ERR => 0,
C_HAS_WR_ACK => 0,
C_HAS_WR_ERR => 0,
C_RD_ACK_LOW => 0,
C_RD_ERR_LOW => 0,
C_WR_ACK_LOW => 0,
C_WR_ERR_LOW => 0,
C_PRELOAD_REGS => 1,-- 1 = first word fall through
C_PRELOAD_LATENCY => 0 -- 0 = first word fall through
-- C_USE_EMBEDDED_REG => 1 -- 0 ;
)
port map (
Clk => m_axi_sg_aclk ,
Sinit => sinit ,
Din => cntrlstrm_fifo_din ,
Wr_en => cntrlstrm_fifo_wren ,
Rd_en => cntrl_fifo_rden ,
Dout => cntrl_fifo_dout ,
Full => cntrlstrm_fifo_full ,
Empty => cntrl_fifo_empty ,
Almost_full => open ,
Data_count => open ,
Rd_ack => open ,
Rd_err => open ,
Wr_ack => open ,
Wr_err => open
);
-- I_UPDT_DATA_FIFO : entity proc_common_srl_fifo_v5_0.srl_fifo_f
-- generic map (
-- C_DWIDTH => 33 ,
-- C_DEPTH => 24 ,
-- C_FAMILY => C_FAMILY
-- )
-- port map (
-- Clk => m_axi_sg_aclk ,
-- Reset => sinit ,
-- FIFO_Write => cntrlstrm_fifo_wren ,
-- Data_In => cntrlstrm_fifo_din ,
-- FIFO_Read => cntrl_fifo_rden ,
-- Data_Out => cntrl_fifo_dout ,
-- FIFO_Empty => cntrl_fifo_empty ,
-- FIFO_Full => cntrlstrm_fifo_full,
-- Addr => open
-- );
cntrl_fifo_rden <= follower_empty_mm2s and (not cntrl_fifo_empty);
VALID_REG_MM2S_ACTIVE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or (cntrl_tready = '1' and follower_full_mm2s = '1'))then
-- follower_reg_mm2s <= (others => '0');
follower_full_mm2s <= '0';
follower_empty_mm2s <= '1';
else
if (cntrl_fifo_rden = '1') then
-- follower_reg_mm2s <= sts_queue_dout;
follower_full_mm2s <= '1';
follower_empty_mm2s <= '0';
end if;
end if;
end if;
end process VALID_REG_MM2S_ACTIVE;
VALID_REG_MM2S_ACTIVE1 : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
follower_reg_mm2s <= (others => '0');
else
if (cntrl_fifo_rden = '1') then
follower_reg_mm2s <= cntrl_fifo_dout;
end if;
end if;
end if;
end process VALID_REG_MM2S_ACTIVE1;
-----------------------------------------------------------------------
-- Control Stream OUT Side
-----------------------------------------------------------------------
-- Read if fifo is not empty and target is ready
-- cntrl_fifo_rden <= not cntrl_fifo_empty
-- and cntrl_tready;
-- Drive valid if fifo is not empty or in the middle
-- of transfer and stop issued.
cntrl_tvalid <= follower_full_mm2s --not cntrl_fifo_empty
or (xfer_in_progress and mm2s_stop_re);
-- Pass data out to control channel with MSB driving tlast
cntrl_tlast <= (cntrl_tvalid and follower_reg_mm2s(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH))
or (xfer_in_progress and mm2s_stop_re);
cntrl_tdata <= follower_reg_mm2s(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH-1 downto 0);
-- Register stop to create re pulse for cleaning shutting down
-- stream out during soft reset.
REG_STOP : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
mm2s_stop_d1 <= '0';
else
mm2s_stop_d1 <= mm2s_stop;
end if;
end if;
end process REG_STOP;
mm2s_stop_re <= mm2s_stop and not mm2s_stop_d1;
-------------------------------------------------------------
-- Flag transfer in progress. If xfer in progress then
-- a fake tlast and tvalid need to be asserted during soft
-- reset else no need of tlast.
-------------------------------------------------------------
TRANSFER_IN_PROGRESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(cntrl_tlast = '1' and cntrl_tvalid = '1' and cntrl_tready = '1')then
xfer_in_progress <= '0';
elsif(xfer_in_progress = '0' and cntrl_tvalid = '1')then
xfer_in_progress <= '1';
end if;
end if;
end process TRANSFER_IN_PROGRESS;
skid_rst <= not m_axi_sg_aresetn;
---------------------------------------------------------------------------
-- Buffer AXI Signals
---------------------------------------------------------------------------
-- CNTRL_SKID_BUF_I : entity axi_sg_v4_1.axi_sg_skid_buf
-- generic map(
-- C_WDATA_WIDTH => C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH
-- )
-- port map(
-- -- System Ports
-- ACLK => m_axi_sg_aclk ,
-- ARST => skid_rst ,
-- skid_stop => mm2s_stop_re ,
-- -- Slave Side (Stream Data Input)
-- S_VALID => cntrl_tvalid ,
-- S_READY => cntrl_tready ,
-- S_Data => cntrl_tdata ,
-- S_STRB => cntrl_tkeep ,
-- S_Last => cntrl_tlast ,
-- -- Master Side (Stream Data Output
-- M_VALID => m_axis_mm2s_cntrl_tvalid ,
-- M_READY => m_axis_mm2s_cntrl_tready ,
-- M_Data => m_axis_mm2s_cntrl_tdata ,
-- M_STRB => m_axis_mm2s_cntrl_tkeep ,
-- M_Last => m_axis_mm2s_cntrl_tlast
-- );
m_axis_mm2s_cntrl_tvalid <= cntrl_tvalid;
cntrl_tready <= m_axis_mm2s_cntrl_tready;
m_axis_mm2s_cntrl_tdata <= cntrl_tdata;
m_axis_mm2s_cntrl_tkeep <= cntrl_tkeep;
m_axis_mm2s_cntrl_tlast <= cntrl_tlast;
end generate GEN_SYNC_FIFO;
-- Primary Clock is asynchronous to Secondary Clock therfore
-- instantiate an async fifo.
GEN_ASYNC_FIFO : if C_PRMRY_IS_ACLK_ASYNC = 1 generate
ATTRIBUTE async_reg : STRING;
signal mm2s_stop_reg : std_logic := '0'; -- CR605883
signal p_mm2s_stop_d1_cdc_tig : std_logic := '0';
signal p_mm2s_stop_d2 : std_logic := '0';
signal p_mm2s_stop_d3 : std_logic := '0';
signal p_mm2s_stop_re : std_logic := '0';
signal xfer_in_progress : std_logic := '0';
-- ATTRIBUTE async_reg OF p_mm2s_stop_d1_cdc_tig : SIGNAL IS "true";
-- ATTRIBUTE async_reg OF p_mm2s_stop_d2 : SIGNAL IS "true";
begin
-- reset on hard reset, soft reset, or mm2s error
sinit <= not p_reset_n or p_mm2s_stop_d2;
-- Generate Asynchronous FIFO
I_CNTRL_STRM_FIFO : entity axi_sg_v4_1.axi_sg_afifo_autord
generic map(
C_DWIDTH => C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH + 1 ,
-- Temp work around for issue in async fifo model
C_DEPTH => CNTRL_FIFO_DEPTH-1 ,
C_CNT_WIDTH => CNTRL_FIFO_CNT_WIDTH ,
-- C_DEPTH => 31 ,
-- C_CNT_WIDTH => 5 ,
C_USE_BLKMEM => USE_LOGIC_FIFOS ,
C_FAMILY => C_FAMILY
)
port map(
-- Inputs
AFIFO_Ainit => sinit ,
AFIFO_Wr_clk => m_axi_sg_aclk ,
AFIFO_Wr_en => cntrlstrm_fifo_wren ,
AFIFO_Din => cntrlstrm_fifo_din ,
AFIFO_Rd_clk => axi_prmry_aclk ,
AFIFO_Rd_en => cntrl_fifo_rden ,
AFIFO_Clr_Rd_Data_Valid => '0' ,
-- Outputs
AFIFO_DValid => cntrl_fifo_dvalid ,
AFIFO_Dout => cntrl_fifo_dout ,
AFIFO_Full => cntrlstrm_fifo_full ,
AFIFO_Empty => cntrl_fifo_empty ,
AFIFO_Almost_full => open ,
AFIFO_Almost_empty => open ,
AFIFO_Wr_count => open ,
AFIFO_Rd_count => open ,
AFIFO_Corr_Rd_count => open ,
AFIFO_Corr_Rd_count_minus1 => open ,
AFIFO_Rd_ack => open
);
-----------------------------------------------------------------------
-- Control Stream OUT Side
-----------------------------------------------------------------------
-- Read if fifo is not empty and target is ready
cntrl_fifo_rden <= not cntrl_fifo_empty -- fifo has data
and cntrl_tready; -- target ready
-- Drive valid if fifo is not empty or in the middle
-- of transfer and stop issued.
cntrl_tvalid <= cntrl_fifo_dvalid
or (xfer_in_progress and p_mm2s_stop_re);
-- Pass data out to control channel with MSB driving tlast
cntrl_tlast <= cntrl_tvalid and cntrl_fifo_dout(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH);
-- cntrl_tlast <= (cntrl_tvalid and cntrl_fifo_dout(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH))
-- or (xfer_in_progress and p_mm2s_stop_re);
cntrl_tdata <= cntrl_fifo_dout(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH-1 downto 0);
-- CR605883
-- Register stop to provide pure FF output for synchronizer
REG_STOP : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
mm2s_stop_reg <= '0';
else
mm2s_stop_reg <= mm2s_stop;
end if;
end if;
end process REG_STOP;
-- Double/triple register mm2s error into primary clock domain
-- Triple register to give two versions with min double reg for use
-- in rising edge detection.
IMP_SYNC_FLOP : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => 2
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => mm2s_stop_reg,
prmry_vect_in => (others => '0'),
scndry_aclk => axi_prmry_aclk,
scndry_resetn => '0',
scndry_out => p_mm2s_stop_d2,
scndry_vect_out => open
);
REG_ERR2PRMRY : process(axi_prmry_aclk)
begin
if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
if(p_reset_n = '0')then
-- p_mm2s_stop_d1_cdc_tig <= '0';
-- p_mm2s_stop_d2 <= '0';
p_mm2s_stop_d3 <= '0';
else
--p_mm2s_stop_d1_cdc_tig <= mm2s_stop;
-- p_mm2s_stop_d1_cdc_tig <= mm2s_stop_reg;
-- p_mm2s_stop_d2 <= p_mm2s_stop_d1_cdc_tig;
p_mm2s_stop_d3 <= p_mm2s_stop_d2;
end if;
end if;
end process REG_ERR2PRMRY;
-- Rising edge pulse for use in shutting down stream output
p_mm2s_stop_re <= p_mm2s_stop_d2 and not p_mm2s_stop_d3;
-------------------------------------------------------------
-- Flag transfer in progress. If xfer in progress then
-- a fake tlast needs to be asserted during soft reset.
-- else no need of tlast.
-------------------------------------------------------------
TRANSFER_IN_PROGRESS : process(axi_prmry_aclk)
begin
if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
if(cntrl_tlast = '1' and cntrl_tvalid = '1' and cntrl_tready = '1')then
xfer_in_progress <= '0';
elsif(xfer_in_progress = '0' and cntrl_tvalid = '1')then
xfer_in_progress <= '1';
end if;
end if;
end process TRANSFER_IN_PROGRESS;
skid_rst <= not p_reset_n;
CNTRL_SKID_BUF_I : entity axi_sg_v4_1.axi_sg_skid_buf
generic map(
C_WDATA_WIDTH => C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH
)
port map(
-- System Ports
ACLK => axi_prmry_aclk ,
ARST => skid_rst ,
skid_stop => p_mm2s_stop_re ,
-- Slave Side (Stream Data Input)
S_VALID => cntrl_tvalid ,
S_READY => cntrl_tready ,
S_Data => cntrl_tdata ,
S_STRB => cntrl_tkeep ,
S_Last => cntrl_tlast ,
-- Master Side (Stream Data Output
M_VALID => m_axis_mm2s_cntrl_tvalid ,
M_READY => m_axis_mm2s_cntrl_tready ,
M_Data => m_axis_mm2s_cntrl_tdata ,
M_STRB => m_axis_mm2s_cntrl_tkeep ,
M_Last => m_axis_mm2s_cntrl_tlast
);
end generate GEN_ASYNC_FIFO;
end implementation;
| gpl-3.0 |
mistryalok/Zedboard | learning/training/MSD/s09/axi_dma_sg/vivado/project_1/project_1.srcs/sources_1/ipshared/xilinx.com/axi_sg_v4_1/0535f152/hdl/src/vhdl/axi_sg_mm2s_basic_wrap.vhd | 5 | 43235 | -- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_mm2s_basic_wrap.vhd
--
-- Description:
-- This file implements the DataMover MM2S Basic Wrapper.
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-- axi_sg Library Modules
library axi_sg_v4_1;
use axi_sg_v4_1.axi_sg_reset;
use axi_sg_v4_1.axi_sg_cmd_status;
use axi_sg_v4_1.axi_sg_scc;
use axi_sg_v4_1.axi_sg_addr_cntl;
use axi_sg_v4_1.axi_sg_rddata_cntl;
use axi_sg_v4_1.axi_sg_rd_status_cntl;
use axi_sg_v4_1.axi_sg_skid_buf;
-------------------------------------------------------------------------------
entity axi_sg_mm2s_basic_wrap is
generic (
C_INCLUDE_MM2S : Integer range 0 to 2 := 2;
-- Specifies the type of MM2S function to include
-- 0 = Omit MM2S functionality
-- 1 = Full MM2S Functionality
-- 2 = Basic MM2S functionality
C_MM2S_ARID : Integer range 0 to 255 := 8;
-- Specifies the constant value to output on
-- the ARID output port
C_MM2S_ID_WIDTH : Integer range 1 to 8 := 4;
-- Specifies the width of the MM2S ID port
C_MM2S_ADDR_WIDTH : Integer range 32 to 64 := 32;
-- Specifies the width of the MMap Read Address Channel
-- Address bus
C_MM2S_MDATA_WIDTH : Integer range 32 to 64 := 32;
-- Specifies the width of the MMap Read Data Channel
-- data bus
C_MM2S_SDATA_WIDTH : Integer range 8 to 64 := 32;
-- Specifies the width of the MM2S Master Stream Data
-- Channel data bus
C_INCLUDE_MM2S_STSFIFO : Integer range 0 to 1 := 1;
-- Specifies if a Status FIFO is to be implemented
-- 0 = Omit MM2S Status FIFO
-- 1 = Include MM2S Status FIFO
C_MM2S_STSCMD_FIFO_DEPTH : Integer range 1 to 16 := 1;
-- Specifies the depth of the MM2S Command FIFO and the
-- optional Status FIFO
-- Valid values are 1,4,8,16
C_MM2S_STSCMD_IS_ASYNC : Integer range 0 to 1 := 0;
-- Specifies if the Status and Command interfaces need to
-- be asynchronous to the primary data path clocking
-- 0 = Use same clocking as data path
-- 1 = Use special Status/Command clock for the interfaces
C_INCLUDE_MM2S_DRE : Integer range 0 to 1 := 0;
-- Specifies if DRE is to be included in the MM2S function
-- 0 = Omit DRE
-- 1 = Include DRE
C_MM2S_BURST_SIZE : Integer range 16 to 64 := 16;
-- Specifies the max number of databeats to use for MMap
-- burst transfers by the MM2S function
C_MM2S_BTT_USED : Integer range 8 to 23 := 16;
-- Specifies the number of bits used from the BTT field
-- of the input Command Word of the MM2S Command Interface
C_MM2S_ADDR_PIPE_DEPTH : Integer range 1 to 30 := 1;
-- This parameter specifies the depth of the MM2S internal
-- child command queues in the Read Address Controller and
-- the Read Data Controller. Increasing this value will
-- allow more Read Addresses to be issued to the AXI4 Read
-- Address Channel before receipt of the associated read
-- data on the Read Data Channel.
C_ENABLE_MULTI_CHANNEL : Integer range 0 to 1 := 1;
C_ENABLE_EXTRA_FIELD : integer range 0 to 1 := 0;
C_TAG_WIDTH : Integer range 1 to 8 := 4 ;
-- Width of the TAG field
C_FAMILY : String := "virtex7"
-- Specifies the target FPGA family type
);
port (
-- MM2S Primary Clock and Reset inputs -----------------------
mm2s_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- MM2S Primary Reset input --
mm2s_aresetn : in std_logic; --
-- Reset used for the internal master logic --
--------------------------------------------------------------
sg_ctl : in std_logic_vector (7 downto 0);
-- MM2S Halt request input control ---------------------------
mm2s_halt : in std_logic; --
-- Active high soft shutdown request --
--
-- MM2S Halt Complete status flag --
mm2s_halt_cmplt : Out std_logic; --
-- Active high soft shutdown complete status --
--------------------------------------------------------------
-- Error discrete output -------------------------------------
mm2s_err : Out std_logic; --
-- Composite Error indication --
--------------------------------------------------------------
-- Optional MM2S Command and Status Clock and Reset ----------
-- These are used when C_MM2S_STSCMD_IS_ASYNC = 1 --
mm2s_cmdsts_awclk : in std_logic; --
-- Secondary Clock input for async CMD/Status interface --
--
mm2s_cmdsts_aresetn : in std_logic; --
-- Secondary Reset input for async CMD/Status interface --
--------------------------------------------------------------
-- User Command Interface Ports (AXI Stream) -------------------------------------------------
mm2s_cmd_wvalid : in std_logic; --
mm2s_cmd_wready : out std_logic; --
mm2s_cmd_wdata : in std_logic_vector((C_TAG_WIDTH+(1+C_ENABLE_MULTI_CHANNEL)*C_MM2S_ADDR_WIDTH+36)-1 downto 0); --
----------------------------------------------------------------------------------------------
-- User Status Interface Ports (AXI Stream) -----------------
mm2s_sts_wvalid : out std_logic; --
mm2s_sts_wready : in std_logic; --
mm2s_sts_wdata : out std_logic_vector(7 downto 0); --
mm2s_sts_wstrb : out std_logic_vector(0 downto 0); --
mm2s_sts_wlast : out std_logic; --
-------------------------------------------------------------
-- Address Posting contols ----------------------------------
mm2s_allow_addr_req : in std_logic; --
mm2s_addr_req_posted : out std_logic; --
mm2s_rd_xfer_cmplt : out std_logic; --
-------------------------------------------------------------
-- MM2S AXI Address Channel I/O --------------------------------------
mm2s_arid : out std_logic_vector(C_MM2S_ID_WIDTH-1 downto 0); --
-- AXI Address Channel ID output --
--
mm2s_araddr : out std_logic_vector(C_MM2S_ADDR_WIDTH-1 downto 0); --
-- AXI Address Channel Address output --
--
mm2s_arlen : out std_logic_vector(7 downto 0); --
-- AXI Address Channel LEN output --
-- Sized to support 256 data beat bursts --
--
mm2s_arsize : out std_logic_vector(2 downto 0); --
-- AXI Address Channel SIZE output --
--
mm2s_arburst : out std_logic_vector(1 downto 0); --
-- AXI Address Channel BURST output --
--
mm2s_arprot : out std_logic_vector(2 downto 0); --
-- AXI Address Channel PROT output --
--
mm2s_arcache : out std_logic_vector(3 downto 0); --
-- AXI Address Channel CACHE output --
mm2s_aruser : out std_logic_vector(3 downto 0); --
-- AXI Address Channel USER output --
--
mm2s_arvalid : out std_logic; --
-- AXI Address Channel VALID output --
--
mm2s_arready : in std_logic; --
-- AXI Address Channel READY input --
-----------------------------------------------------------------------
-- Currently unsupported AXI Address Channel output signals -------
-- addr2axi_alock : out std_logic_vector(2 downto 0); --
-- addr2axi_acache : out std_logic_vector(4 downto 0); --
-- addr2axi_aqos : out std_logic_vector(3 downto 0); --
-- addr2axi_aregion : out std_logic_vector(3 downto 0); --
-------------------------------------------------------------------
-- MM2S AXI MMap Read Data Channel I/O ------------------------------------------
mm2s_rdata : In std_logic_vector(C_MM2S_MDATA_WIDTH-1 downto 0); --
mm2s_rresp : In std_logic_vector(1 downto 0); --
mm2s_rlast : In std_logic; --
mm2s_rvalid : In std_logic; --
mm2s_rready : Out std_logic; --
----------------------------------------------------------------------------------
-- MM2S AXI Master Stream Channel I/O -----------------------------------------------
mm2s_strm_wdata : Out std_logic_vector(C_MM2S_SDATA_WIDTH-1 downto 0); --
mm2s_strm_wstrb : Out std_logic_vector((C_MM2S_SDATA_WIDTH/8)-1 downto 0); --
mm2s_strm_wlast : Out std_logic; --
mm2s_strm_wvalid : Out std_logic; --
mm2s_strm_wready : In std_logic; --
--------------------------------------------------------------------------------------
-- Testing Support I/O --------------------------------------------
mm2s_dbg_sel : in std_logic_vector( 3 downto 0); --
mm2s_dbg_data : out std_logic_vector(31 downto 0) --
-------------------------------------------------------------------
);
end entity axi_sg_mm2s_basic_wrap;
architecture implementation of axi_sg_mm2s_basic_wrap is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Function Declarations ----------------------------------------
-------------------------------------------------------------------
-- Function
--
-- Function Name: func_calc_rdmux_sel_bits
--
-- Function Description:
-- This function calculates the number of address bits needed for
-- the Read data mux select control.
--
-------------------------------------------------------------------
function func_calc_rdmux_sel_bits (mmap_dwidth_value : integer) return integer is
Variable num_addr_bits_needed : Integer range 1 to 5 := 1;
begin
case mmap_dwidth_value is
when 32 =>
num_addr_bits_needed := 2;
-- coverage off
when 64 =>
num_addr_bits_needed := 3;
when 128 =>
num_addr_bits_needed := 4;
when others => -- 256 bits
num_addr_bits_needed := 5;
-- coverage on
end case;
Return (num_addr_bits_needed);
end function func_calc_rdmux_sel_bits;
-- Constant Declarations ----------------------------------------
Constant LOGIC_LOW : std_logic := '0';
Constant LOGIC_HIGH : std_logic := '1';
Constant INCLUDE_MM2S : integer range 0 to 2 := 2;
Constant MM2S_ARID_VALUE : integer range 0 to 255 := C_MM2S_ARID;
Constant MM2S_ARID_WIDTH : integer range 1 to 8 := C_MM2S_ID_WIDTH;
Constant MM2S_ADDR_WIDTH : integer range 32 to 64 := C_MM2S_ADDR_WIDTH;
Constant MM2S_MDATA_WIDTH : integer range 32 to 256 := C_MM2S_MDATA_WIDTH;
Constant MM2S_SDATA_WIDTH : integer range 8 to 256 := C_MM2S_SDATA_WIDTH;
Constant MM2S_CMD_WIDTH : integer := (C_TAG_WIDTH+C_MM2S_ADDR_WIDTH+32);
Constant MM2S_STS_WIDTH : integer := 8; -- always 8 for MM2S
Constant INCLUDE_MM2S_STSFIFO : integer range 0 to 1 := 1;
Constant MM2S_STSCMD_FIFO_DEPTH : integer range 1 to 64 := 1;
Constant MM2S_STSCMD_IS_ASYNC : integer range 0 to 1 := 0;
Constant INCLUDE_MM2S_DRE : integer range 0 to 1 := 0;
Constant DRE_ALIGN_WIDTH : integer range 1 to 3 := 2;
Constant MM2S_BURST_SIZE : integer range 16 to 256 := 16;
Constant RD_ADDR_CNTL_FIFO_DEPTH : integer range 1 to 30 := C_MM2S_ADDR_PIPE_DEPTH;
Constant RD_DATA_CNTL_FIFO_DEPTH : integer range 1 to 30 := C_MM2S_ADDR_PIPE_DEPTH;
Constant SEL_ADDR_WIDTH : integer := func_calc_rdmux_sel_bits(MM2S_MDATA_WIDTH);
Constant DRE_ALIGN_ZEROS : std_logic_vector(DRE_ALIGN_WIDTH-1 downto 0) := (others => '0');
-- obsoleted Constant DISABLE_WAIT_FOR_DATA : integer := 0;
-- Signal Declarations ------------------------------------------
signal sig_cmd_stat_rst_user : std_logic := '0';
signal sig_cmd_stat_rst_int : std_logic := '0';
signal sig_mmap_rst : std_logic := '0';
signal sig_stream_rst : std_logic := '0';
signal sig_mm2s_cmd_wdata : std_logic_vector(MM2S_CMD_WIDTH-1 downto 0);
signal sig_mm2s_cache_data : std_logic_vector(7 downto 0);
signal sig_cmd2mstr_command : std_logic_vector(MM2S_CMD_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd2mstr_cmd_valid : std_logic := '0';
signal sig_mst2cmd_cmd_ready : std_logic := '0';
signal sig_mstr2addr_addr : std_logic_vector(MM2S_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_mstr2addr_len : std_logic_vector(7 downto 0) := (others => '0');
signal sig_mstr2addr_size : std_logic_vector(2 downto 0) := (others => '0');
signal sig_mstr2addr_burst : std_logic_vector(1 downto 0) := (others => '0');
signal sig_mstr2addr_cache : std_logic_vector(3 downto 0) := (others => '0');
signal sig_mstr2addr_user : std_logic_vector(3 downto 0) := (others => '0');
signal sig_mstr2addr_cmd_cmplt : std_logic := '0';
signal sig_mstr2addr_calc_error : std_logic := '0';
signal sig_mstr2addr_cmd_valid : std_logic := '0';
signal sig_addr2mstr_cmd_ready : std_logic := '0';
signal sig_mstr2data_saddr_lsb : std_logic_vector(SEL_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_mstr2data_len : std_logic_vector(7 downto 0) := (others => '0');
signal sig_mstr2data_strt_strb : std_logic_vector((MM2S_SDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_mstr2data_last_strb : std_logic_vector((MM2S_SDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_mstr2data_drr : std_logic := '0';
signal sig_mstr2data_eof : std_logic := '0';
signal sig_mstr2data_sequential : std_logic := '0';
signal sig_mstr2data_calc_error : std_logic := '0';
signal sig_mstr2data_cmd_cmplt : std_logic := '0';
signal sig_mstr2data_cmd_valid : std_logic := '0';
signal sig_data2mstr_cmd_ready : std_logic := '0';
signal sig_addr2data_addr_posted : std_logic := '0';
signal sig_data2all_dcntlr_halted : std_logic := '0';
signal sig_addr2rsc_calc_error : std_logic := '0';
signal sig_addr2rsc_cmd_fifo_empty : std_logic := '0';
signal sig_data2rsc_tag : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_data2rsc_calc_err : std_logic := '0';
signal sig_data2rsc_okay : std_logic := '0';
signal sig_data2rsc_decerr : std_logic := '0';
signal sig_data2rsc_slverr : std_logic := '0';
signal sig_data2rsc_cmd_cmplt : std_logic := '0';
signal sig_rsc2data_ready : std_logic := '0';
signal sig_data2rsc_valid : std_logic := '0';
signal sig_calc2dm_calc_err : std_logic := '0';
signal sig_data2skid_wvalid : std_logic := '0';
signal sig_data2skid_wready : std_logic := '0';
signal sig_data2skid_wdata : std_logic_vector(MM2S_SDATA_WIDTH-1 downto 0) := (others => '0');
signal sig_data2skid_wstrb : std_logic_vector((MM2S_SDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_data2skid_wlast : std_logic := '0';
signal sig_rsc2stat_status : std_logic_vector(MM2S_STS_WIDTH-1 downto 0) := (others => '0');
signal sig_stat2rsc_status_ready : std_logic := '0';
signal sig_rsc2stat_status_valid : std_logic := '0';
signal sig_rsc2mstr_halt_pipe : std_logic := '0';
signal sig_mstr2data_tag : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_mstr2addr_tag : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_dbg_data_mux_out : std_logic_vector(31 downto 0) := (others => '0');
signal sig_dbg_data_0 : std_logic_vector(31 downto 0) := (others => '0');
signal sig_dbg_data_1 : std_logic_vector(31 downto 0) := (others => '0');
signal sig_rst2all_stop_request : std_logic := '0';
signal sig_data2rst_stop_cmplt : std_logic := '0';
signal sig_addr2rst_stop_cmplt : std_logic := '0';
signal sig_data2addr_stop_req : std_logic := '0';
signal sig_data2skid_halt : std_logic := '0';
signal sig_cache2mstr_command : std_logic_vector (7 downto 0) := (others => '0');
signal mm2s_arcache_int : std_logic_vector (3 downto 0);
begin --(architecture implementation)
-- Debug Support ------------------------------------------
mm2s_dbg_data <= sig_dbg_data_mux_out;
-- Note that only the mm2s_dbg_sel(0) is used at this time
sig_dbg_data_mux_out <= sig_dbg_data_1
When (mm2s_dbg_sel(0) = '1')
else sig_dbg_data_0 ;
sig_dbg_data_0 <= X"BEEF2222" ; -- 32 bit Constant indicating MM2S Basic type
sig_dbg_data_1(0) <= sig_cmd_stat_rst_user ;
sig_dbg_data_1(1) <= sig_cmd_stat_rst_int ;
sig_dbg_data_1(2) <= sig_mmap_rst ;
sig_dbg_data_1(3) <= sig_stream_rst ;
sig_dbg_data_1(4) <= sig_cmd2mstr_cmd_valid ;
sig_dbg_data_1(5) <= sig_mst2cmd_cmd_ready ;
sig_dbg_data_1(6) <= sig_stat2rsc_status_ready;
sig_dbg_data_1(7) <= sig_rsc2stat_status_valid;
sig_dbg_data_1(11 downto 8) <= sig_data2rsc_tag ; -- Current TAG of active data transfer
sig_dbg_data_1(15 downto 12) <= sig_rsc2stat_status(3 downto 0); -- Internal status tag field
sig_dbg_data_1(16) <= sig_rsc2stat_status(4) ; -- Internal error
sig_dbg_data_1(17) <= sig_rsc2stat_status(5) ; -- Decode Error
sig_dbg_data_1(18) <= sig_rsc2stat_status(6) ; -- Slave Error
sig_dbg_data_1(19) <= sig_rsc2stat_status(7) ; -- OKAY
sig_dbg_data_1(20) <= sig_stat2rsc_status_ready ; -- Status Ready Handshake
sig_dbg_data_1(21) <= sig_rsc2stat_status_valid ; -- Status Valid Handshake
-- Spare bits in debug1
sig_dbg_data_1(31 downto 22) <= (others => '0') ; -- spare bits
GEN_CACHE : if (C_ENABLE_MULTI_CHANNEL = 0) generate
begin
-- Cache signal tie-off
mm2s_arcache <= "0011"; -- Per Interface-X guidelines for Masters
mm2s_aruser <= "0000"; -- Per Interface-X guidelines for Masters
sig_mm2s_cache_data <= (others => '0'); --mm2s_cmd_wdata(103 downto 96);
end generate GEN_CACHE;
GEN_CACHE2 : if (C_ENABLE_MULTI_CHANNEL = 1) generate
begin
-- Cache signal tie-off
mm2s_arcache <= sg_ctl (3 downto 0); -- SG Cache from register
mm2s_aruser <= sg_ctl (7 downto 4); -- Per Interface-X guidelines for Masters
sig_mm2s_cache_data <= mm2s_cmd_wdata(103 downto 96);
end generate GEN_CACHE2;
-- Cache signal tie-off
-- Internal error output discrete ------------------------------
mm2s_err <= sig_calc2dm_calc_err;
-- Rip the used portion of the Command Interface Command Data
-- and throw away the padding
sig_mm2s_cmd_wdata <= mm2s_cmd_wdata(MM2S_CMD_WIDTH-1 downto 0);
------------------------------------------------------------
-- Instance: I_RESET
--
-- Description:
-- Reset Block
--
------------------------------------------------------------
I_RESET : entity axi_sg_v4_1.axi_sg_reset
generic map (
C_STSCMD_IS_ASYNC => MM2S_STSCMD_IS_ASYNC
)
port map (
primary_aclk => mm2s_aclk ,
primary_aresetn => mm2s_aresetn ,
secondary_awclk => mm2s_cmdsts_awclk ,
secondary_aresetn => mm2s_cmdsts_aresetn ,
halt_req => mm2s_halt ,
halt_cmplt => mm2s_halt_cmplt ,
flush_stop_request => sig_rst2all_stop_request ,
data_cntlr_stopped => sig_data2rst_stop_cmplt ,
addr_cntlr_stopped => sig_addr2rst_stop_cmplt ,
aux1_stopped => LOGIC_HIGH ,
aux2_stopped => LOGIC_HIGH ,
cmd_stat_rst_user => sig_cmd_stat_rst_user ,
cmd_stat_rst_int => sig_cmd_stat_rst_int ,
mmap_rst => sig_mmap_rst ,
stream_rst => sig_stream_rst
);
------------------------------------------------------------
-- Instance: I_CMD_STATUS
--
-- Description:
-- Command and Status Interface Block
--
------------------------------------------------------------
I_CMD_STATUS : entity axi_sg_v4_1.axi_sg_cmd_status
generic map (
C_ADDR_WIDTH => MM2S_ADDR_WIDTH ,
C_INCLUDE_STSFIFO => INCLUDE_MM2S_STSFIFO ,
C_STSCMD_FIFO_DEPTH => MM2S_STSCMD_FIFO_DEPTH ,
C_STSCMD_IS_ASYNC => MM2S_STSCMD_IS_ASYNC ,
C_CMD_WIDTH => MM2S_CMD_WIDTH ,
C_STS_WIDTH => MM2S_STS_WIDTH ,
C_FAMILY => C_FAMILY
)
port map (
primary_aclk => mm2s_aclk ,
secondary_awclk => mm2s_cmdsts_awclk ,
user_reset => sig_cmd_stat_rst_user ,
internal_reset => sig_cmd_stat_rst_int ,
cmd_wvalid => mm2s_cmd_wvalid ,
cmd_wready => mm2s_cmd_wready ,
cmd_wdata => sig_mm2s_cmd_wdata ,
cache_data => sig_mm2s_cache_data ,
sts_wvalid => mm2s_sts_wvalid ,
sts_wready => mm2s_sts_wready ,
sts_wdata => mm2s_sts_wdata ,
sts_wstrb => mm2s_sts_wstrb ,
sts_wlast => mm2s_sts_wlast ,
cmd2mstr_command => sig_cmd2mstr_command ,
mst2cmd_cmd_valid => sig_cmd2mstr_cmd_valid ,
cmd2mstr_cmd_ready => sig_mst2cmd_cmd_ready ,
mstr2stat_status => sig_rsc2stat_status ,
stat2mstr_status_ready => sig_stat2rsc_status_ready ,
mst2stst_status_valid => sig_rsc2stat_status_valid
);
------------------------------------------------------------
-- Instance: I_RD_STATUS_CNTLR
--
-- Description:
-- Read Status Controller Block
--
------------------------------------------------------------
I_RD_STATUS_CNTLR : entity axi_sg_v4_1.axi_sg_rd_status_cntl
generic map (
C_STS_WIDTH => MM2S_STS_WIDTH ,
C_TAG_WIDTH => C_TAG_WIDTH
)
port map (
primary_aclk => mm2s_aclk ,
mmap_reset => sig_mmap_rst ,
calc2rsc_calc_error => sig_calc2dm_calc_err ,
addr2rsc_calc_error => sig_addr2rsc_calc_error ,
addr2rsc_fifo_empty => sig_addr2rsc_cmd_fifo_empty ,
data2rsc_tag => sig_data2rsc_tag ,
data2rsc_calc_error => sig_data2rsc_calc_err ,
data2rsc_okay => sig_data2rsc_okay ,
data2rsc_decerr => sig_data2rsc_decerr ,
data2rsc_slverr => sig_data2rsc_slverr ,
data2rsc_cmd_cmplt => sig_data2rsc_cmd_cmplt ,
rsc2data_ready => sig_rsc2data_ready ,
data2rsc_valid => sig_data2rsc_valid ,
rsc2stat_status => sig_rsc2stat_status ,
stat2rsc_status_ready => sig_stat2rsc_status_ready ,
rsc2stat_status_valid => sig_rsc2stat_status_valid ,
rsc2mstr_halt_pipe => sig_rsc2mstr_halt_pipe
);
------------------------------------------------------------
-- Instance: I_MSTR_SCC
--
-- Description:
-- Simple Command Calculator Block
--
------------------------------------------------------------
I_MSTR_SCC : entity axi_sg_v4_1.axi_sg_scc
generic map (
C_SEL_ADDR_WIDTH => SEL_ADDR_WIDTH ,
C_ADDR_WIDTH => MM2S_ADDR_WIDTH ,
C_STREAM_DWIDTH => MM2S_SDATA_WIDTH ,
C_MAX_BURST_LEN => C_MM2S_BURST_SIZE ,
C_CMD_WIDTH => MM2S_CMD_WIDTH ,
C_ENABLE_EXTRA_FIELD => C_ENABLE_EXTRA_FIELD ,
C_TAG_WIDTH => C_TAG_WIDTH
)
port map (
-- Clock input
primary_aclk => mm2s_aclk ,
mmap_reset => sig_mmap_rst ,
cmd2mstr_command => sig_cmd2mstr_command ,
cache2mstr_command => sig_cache2mstr_command ,
cmd2mstr_cmd_valid => sig_cmd2mstr_cmd_valid ,
mst2cmd_cmd_ready => sig_mst2cmd_cmd_ready ,
mstr2addr_tag => sig_mstr2addr_tag ,
mstr2addr_addr => sig_mstr2addr_addr ,
mstr2addr_len => sig_mstr2addr_len ,
mstr2addr_size => sig_mstr2addr_size ,
mstr2addr_burst => sig_mstr2addr_burst ,
mstr2addr_calc_error => sig_mstr2addr_calc_error ,
mstr2addr_cmd_cmplt => sig_mstr2addr_cmd_cmplt ,
mstr2addr_cmd_valid => sig_mstr2addr_cmd_valid ,
addr2mstr_cmd_ready => sig_addr2mstr_cmd_ready ,
mstr2data_tag => sig_mstr2data_tag ,
mstr2data_saddr_lsb => sig_mstr2data_saddr_lsb ,
mstr2data_len => sig_mstr2data_len ,
mstr2data_strt_strb => sig_mstr2data_strt_strb ,
mstr2data_last_strb => sig_mstr2data_last_strb ,
mstr2data_sof => sig_mstr2data_drr ,
mstr2data_eof => sig_mstr2data_eof ,
mstr2data_calc_error => sig_mstr2data_calc_error ,
mstr2data_cmd_cmplt => sig_mstr2data_cmd_cmplt ,
mstr2data_cmd_valid => sig_mstr2data_cmd_valid ,
data2mstr_cmd_ready => sig_data2mstr_cmd_ready ,
calc_error => sig_calc2dm_calc_err
);
------------------------------------------------------------
-- Instance: I_ADDR_CNTL
--
-- Description:
-- Address Controller Block
--
------------------------------------------------------------
I_ADDR_CNTL : entity axi_sg_v4_1.axi_sg_addr_cntl
generic map (
-- obsoleted C_ENABlE_WAIT_FOR_DATA => DISABLE_WAIT_FOR_DATA ,
--C_ADDR_FIFO_DEPTH => MM2S_STSCMD_FIFO_DEPTH ,
C_ADDR_FIFO_DEPTH => RD_ADDR_CNTL_FIFO_DEPTH ,
C_ADDR_WIDTH => MM2S_ADDR_WIDTH ,
C_ADDR_ID => MM2S_ARID_VALUE ,
C_ADDR_ID_WIDTH => MM2S_ARID_WIDTH ,
C_TAG_WIDTH => C_TAG_WIDTH
)
port map (
primary_aclk => mm2s_aclk ,
mmap_reset => sig_mmap_rst ,
addr2axi_aid => mm2s_arid ,
addr2axi_aaddr => mm2s_araddr ,
addr2axi_alen => mm2s_arlen ,
addr2axi_asize => mm2s_arsize ,
addr2axi_aburst => mm2s_arburst ,
addr2axi_aprot => mm2s_arprot ,
addr2axi_avalid => mm2s_arvalid ,
addr2axi_acache => open ,
addr2axi_auser => open ,
axi2addr_aready => mm2s_arready ,
mstr2addr_tag => sig_mstr2addr_tag ,
mstr2addr_addr => sig_mstr2addr_addr ,
mstr2addr_len => sig_mstr2addr_len ,
mstr2addr_size => sig_mstr2addr_size ,
mstr2addr_burst => sig_mstr2addr_burst ,
mstr2addr_cache => sig_mstr2addr_cache ,
mstr2addr_user => sig_mstr2addr_user ,
mstr2addr_cmd_cmplt => sig_mstr2addr_cmd_cmplt ,
mstr2addr_calc_error => sig_mstr2addr_calc_error ,
mstr2addr_cmd_valid => sig_mstr2addr_cmd_valid ,
addr2mstr_cmd_ready => sig_addr2mstr_cmd_ready ,
addr2rst_stop_cmplt => sig_addr2rst_stop_cmplt ,
allow_addr_req => mm2s_allow_addr_req ,
addr_req_posted => mm2s_addr_req_posted ,
addr2data_addr_posted => sig_addr2data_addr_posted ,
data2addr_data_rdy => LOGIC_LOW ,
data2addr_stop_req => sig_data2addr_stop_req ,
addr2stat_calc_error => sig_addr2rsc_calc_error ,
addr2stat_cmd_fifo_empty => sig_addr2rsc_cmd_fifo_empty
);
------------------------------------------------------------
-- Instance: I_RD_DATA_CNTL
--
-- Description:
-- Read Data Controller Block
--
------------------------------------------------------------
I_RD_DATA_CNTL : entity axi_sg_v4_1.axi_sg_rddata_cntl
generic map (
C_INCLUDE_DRE => INCLUDE_MM2S_DRE ,
C_ALIGN_WIDTH => DRE_ALIGN_WIDTH ,
C_SEL_ADDR_WIDTH => SEL_ADDR_WIDTH ,
C_DATA_CNTL_FIFO_DEPTH => RD_DATA_CNTL_FIFO_DEPTH ,
C_MMAP_DWIDTH => MM2S_MDATA_WIDTH ,
C_STREAM_DWIDTH => MM2S_SDATA_WIDTH ,
C_TAG_WIDTH => C_TAG_WIDTH ,
C_FAMILY => C_FAMILY
)
port map (
-- Clock and Reset -----------------------------------
primary_aclk => mm2s_aclk ,
mmap_reset => sig_mmap_rst ,
-- Soft Shutdown Interface -----------------------------
rst2data_stop_request => sig_rst2all_stop_request ,
data2addr_stop_req => sig_data2addr_stop_req ,
data2rst_stop_cmplt => sig_data2rst_stop_cmplt ,
-- External Address Pipelining Contol support
mm2s_rd_xfer_cmplt => mm2s_rd_xfer_cmplt ,
-- AXI Read Data Channel I/O -------------------------------
mm2s_rdata => mm2s_rdata ,
mm2s_rresp => mm2s_rresp ,
mm2s_rlast => mm2s_rlast ,
mm2s_rvalid => mm2s_rvalid ,
mm2s_rready => mm2s_rready ,
-- MM2S DRE Control -----------------------------------
mm2s_dre_new_align => open ,
mm2s_dre_use_autodest => open ,
mm2s_dre_src_align => open ,
mm2s_dre_dest_align => open ,
mm2s_dre_flush => open ,
-- AXI Master Stream -----------------------------------
mm2s_strm_wvalid => mm2s_strm_wvalid ,
mm2s_strm_wready => mm2s_strm_wready ,
mm2s_strm_wdata => mm2s_strm_wdata ,
mm2s_strm_wstrb => mm2s_strm_wstrb ,
mm2s_strm_wlast => mm2s_strm_wlast ,
-- MM2S Store and Forward Supplimental Control -----------
mm2s_data2sf_cmd_cmplt => open ,
-- Command Calculator Interface --------------------------
mstr2data_tag => sig_mstr2data_tag ,
mstr2data_saddr_lsb => sig_mstr2data_saddr_lsb ,
mstr2data_len => sig_mstr2data_len ,
mstr2data_strt_strb => sig_mstr2data_strt_strb ,
mstr2data_last_strb => sig_mstr2data_last_strb ,
mstr2data_drr => sig_mstr2data_drr ,
mstr2data_eof => sig_mstr2data_eof ,
mstr2data_sequential => LOGIC_LOW ,
mstr2data_calc_error => sig_mstr2data_calc_error ,
mstr2data_cmd_cmplt => sig_mstr2data_cmd_cmplt ,
mstr2data_cmd_valid => sig_mstr2data_cmd_valid ,
data2mstr_cmd_ready => sig_data2mstr_cmd_ready ,
mstr2data_dre_src_align => DRE_ALIGN_ZEROS ,
mstr2data_dre_dest_align => DRE_ALIGN_ZEROS ,
-- Address Controller Interface --------------------------
addr2data_addr_posted => sig_addr2data_addr_posted ,
-- Data Controller Halted Status
data2all_dcntlr_halted => sig_data2all_dcntlr_halted,
-- Output Stream Skid Buffer Halt control
data2skid_halt => sig_data2skid_halt ,
-- Read Status Controller Interface --------------------------
data2rsc_tag => sig_data2rsc_tag ,
data2rsc_calc_err => sig_data2rsc_calc_err ,
data2rsc_okay => sig_data2rsc_okay ,
data2rsc_decerr => sig_data2rsc_decerr ,
data2rsc_slverr => sig_data2rsc_slverr ,
data2rsc_cmd_cmplt => sig_data2rsc_cmd_cmplt ,
rsc2data_ready => sig_rsc2data_ready ,
data2rsc_valid => sig_data2rsc_valid ,
rsc2mstr_halt_pipe => sig_rsc2mstr_halt_pipe
);
------------------------------------------------------------
-- Instance: I_MM2S_SKID_BUF
--
-- Description:
-- Instance for the MM2S Skid Buffer which provides for
-- registerd Master Stream outputs and supports bi-dir
-- throttling.
--
------------------------------------------------------------
-- I_MM2S_SKID_BUF : entity axi_sg_v4_1.axi_sg_skid_buf
-- generic map (
--
-- C_WDATA_WIDTH => MM2S_SDATA_WIDTH
--
-- )
-- port map (
--
-- -- System Ports
-- aclk => mm2s_aclk ,
-- arst => sig_stream_rst ,
--
-- -- Shutdown control (assert for 1 clk pulse)
-- skid_stop => sig_data2skid_halt ,
--
-- -- Slave Side (Stream Data Input)
-- s_valid => sig_data2skid_wvalid ,
-- s_ready => sig_data2skid_wready ,
-- s_data => sig_data2skid_wdata ,
-- s_strb => sig_data2skid_wstrb ,
-- s_last => sig_data2skid_wlast ,
--
-- -- Master Side (Stream Data Output
-- m_valid => mm2s_strm_wvalid ,
-- m_ready => mm2s_strm_wready ,
-- m_data => mm2s_strm_wdata ,
-- m_strb => mm2s_strm_wstrb ,
-- m_last => mm2s_strm_wlast
--
-- );
--
end implementation;
| gpl-3.0 |
mistryalok/Zedboard | learning/training/MSD/s09/axi_dma_sg/vivado/project_1/project_1.srcs/sources_1/ipshared/xilinx.com/axi_sg_v4_1/0535f152/hdl/src/vhdl/axi_sg_scc_wr.vhd | 13 | 44376 | -- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_scc_wr.vhd
--
-- Description:
-- This file implements the DataMover Lite Master Simple Command Calculator (SCC).
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-------------------------------------------------------------------------------
entity axi_sg_scc_wr is
generic (
C_SEL_ADDR_WIDTH : Integer range 1 to 8 := 5;
-- Sets the width of the LS address bus used for
-- Muxing/Demuxing data to/from a wider AXI4 data bus
C_ADDR_WIDTH : Integer range 32 to 64 := 32;
-- Sets the width of the AXi Address Channel
C_STREAM_DWIDTH : Integer range 8 to 64 := 32;
-- Sets the width of the Native Data width that
-- is being supported by the PCC
C_MAX_BURST_LEN : Integer range 16 to 64 := 16;
-- Indicates the max allowed burst length to use for
-- AXI4 transfer calculations
C_CMD_WIDTH : Integer := 68;
-- Sets the width of the input command port
C_TAG_WIDTH : Integer range 1 to 8 := 4;
-- Sets the width of the Tag field in the input command
C_ENABLE_EXTRA_FIELD : Integer range 0 to 1 := 1
);
port (
-- Clock and Reset inputs -------------------------------------
primary_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- Reset input --
mmap_reset : in std_logic; --
-- Reset used for the internal master logic --
---------------------------------------------------------------
-- Command Input Interface ---------------------------------------------------------
--
cmd2mstr_command : in std_logic_vector(C_CMD_WIDTH-1 downto 0); --
-- The next command value available from the Command FIFO/Register --
--
cache2mstr_command : in std_logic_vector(7 downto 0); --
-- The next command value available from the Command FIFO/Register --
--
cmd2mstr_cmd_valid : in std_logic; --
-- Handshake bit indicating if the Command FIFO/Register has at leasdt 1 entry --
--
mst2cmd_cmd_ready : out std_logic; --
-- Handshake bit indicating the Command Calculator is ready to accept --
-- another command --
------------------------------------------------------------------------------------
-- Address Channel Controller Interface --------------------------------------------
--
mstr2addr_tag : out std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The next command tag --
--
mstr2addr_addr : out std_logic_vector(C_ADDR_WIDTH-1 downto 0); --
-- The next command address to put on the AXI MMap ADDR --
--
mstr2addr_len : out std_logic_vector(7 downto 0); --
-- The next command length to put on the AXI MMap LEN --
--
mstr2addr_size : out std_logic_vector(2 downto 0); --
-- The next command size to put on the AXI MMap SIZE --
--
mstr2addr_burst : out std_logic_vector(1 downto 0); --
-- The next command burst type to put on the AXI MMap BURST --
--
mstr2addr_cache : out std_logic_vector(3 downto 0); --
-- The next command burst type to put on the AXI MMap BURST --
--
mstr2addr_user : out std_logic_vector(3 downto 0); --
-- The next command burst type to put on the AXI MMap BURST --
--
mstr2addr_cmd_cmplt : out std_logic; --
-- The indication to the Address Channel that the current --
-- sub-command output is the last one compiled from the --
-- parent command pulled from the Command FIFO --
--
mstr2addr_calc_error : out std_logic; --
-- Indication if the next command in the calculation pipe --
-- has a calcualtion error --
--
mstr2addr_cmd_valid : out std_logic; --
-- The next command valid indication to the Address Channel --
-- Controller for the AXI MMap --
--
addr2mstr_cmd_ready : In std_logic; --
-- Indication from the Address Channel Controller that the --
-- command is being accepted --
------------------------------------------------------------------------------------
-- Data Channel Controller Interface ----------------------------------------------
--
mstr2data_tag : out std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The next command tag --
--
mstr2data_saddr_lsb : out std_logic_vector(C_SEL_ADDR_WIDTH-1 downto 0); --
-- The next command start address LSbs to use for the read data --
-- mux (only used if Stream data width is 8 or 16 bits). --
--
mstr2data_len : out std_logic_vector(7 downto 0); --
-- The LEN value output to the Address Channel --
--
mstr2data_strt_strb : out std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- The starting strobe value to use for the data transfer --
--
mstr2data_last_strb : out std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- The endiing (LAST) strobe value to use for the data transfer --
--
mstr2data_sof : out std_logic; --
-- The starting tranfer of a sequence of transfers --
--
mstr2data_eof : out std_logic; --
-- The endiing tranfer of a sequence of parent transfer commands --
--
mstr2data_calc_error : out std_logic; --
-- Indication if the next command in the calculation pipe --
-- has a calculation error --
--
mstr2data_cmd_cmplt : out std_logic; --
-- The indication to the Data Channel that the current --
-- sub-command output is the last one compiled from the --
-- parent command pulled from the Command FIFO --
--
mstr2data_cmd_valid : out std_logic; --
-- The next command valid indication to the Data Channel --
-- Controller for the AXI MMap --
--
data2mstr_cmd_ready : In std_logic ; --
-- Indication from the Data Channel Controller that the --
-- command is being accepted on the AXI Address --
-- Channel --
--
calc_error : Out std_logic --
-- Indication from the Command Calculator that a calculation --
-- error has occured. --
------------------------------------------------------------------------------------
);
end entity axi_sg_scc_wr;
architecture implementation of axi_sg_scc_wr is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_slice_width
--
-- Function Description:
-- Calculates the bits to rip from the Command BTT field to calculate
-- the LEN value output to the AXI Address Channel.
--
-------------------------------------------------------------------
function funct_get_slice_width (max_burst_len : integer) return integer is
Variable temp_slice_width : Integer := 0;
begin
case max_burst_len is
-- coverage off
when 64 =>
temp_slice_width := 7;
when 32 =>
temp_slice_width := 6;
when others => -- assume 16 dbeats is max LEN
temp_slice_width := 5;
-- coverage on
end case;
Return (temp_slice_width);
end function funct_get_slice_width;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_residue_width
--
-- Function Description:
-- Calculates the number of Least significant bits of the BTT field
-- that are unused for the LEN calculation
--
-------------------------------------------------------------------
function funct_get_btt_ls_unused (transfer_width : integer) return integer is
Variable temp_btt_ls_unused : Integer := 0; -- 8-bit stream
begin
case transfer_width is
-- coverage off
when 64 =>
temp_btt_ls_unused := 3;
-- coverage on
when 32 =>
temp_btt_ls_unused := 2;
-- coverage off
when 16 =>
temp_btt_ls_unused := 1;
when others => -- assume 8-bit transfers
temp_btt_ls_unused := 0;
-- coverage on
end case;
Return (temp_btt_ls_unused);
end function funct_get_btt_ls_unused;
-- Constant Declarations ----------------------------------------
Constant BASE_CMD_WIDTH : integer := 32; -- Bit Width of Command LS (no address)
Constant CMD_TYPE_INDEX : integer := 23;
Constant CMD_ADDR_LS_INDEX : integer := BASE_CMD_WIDTH;
Constant CMD_ADDR_MS_INDEX : integer := (C_ADDR_WIDTH+BASE_CMD_WIDTH)-1;
Constant CMD_TAG_WIDTH : integer := C_TAG_WIDTH;
Constant CMD_TAG_LS_INDEX : integer := C_ADDR_WIDTH+BASE_CMD_WIDTH;
Constant CMD_TAG_MS_INDEX : integer := (CMD_TAG_LS_INDEX+CMD_TAG_WIDTH)-1;
Constant AXI_BURST_FIXED : std_logic_vector(1 downto 0) := "00";
Constant AXI_BURST_INCR : std_logic_vector(1 downto 0) := "01";
Constant AXI_BURST_WRAP : std_logic_vector(1 downto 0) := "10";
Constant AXI_BURST_RESVD : std_logic_vector(1 downto 0) := "11";
Constant AXI_SIZE_1BYTE : std_logic_vector(2 downto 0) := "000";
Constant AXI_SIZE_2BYTE : std_logic_vector(2 downto 0) := "001";
Constant AXI_SIZE_4BYTE : std_logic_vector(2 downto 0) := "010";
Constant AXI_SIZE_8BYTE : std_logic_vector(2 downto 0) := "011";
Constant AXI_SIZE_16BYTE : std_logic_vector(2 downto 0) := "100";
Constant AXI_SIZE_32BYTE : std_logic_vector(2 downto 0) := "101";
Constant AXI_SIZE_64BYTE : std_logic_vector(2 downto 0) := "110";
Constant AXI_SIZE_128BYTE : std_logic_vector(2 downto 0) := "111";
Constant BTT_SLICE_SIZE : integer := funct_get_slice_width(C_MAX_BURST_LEN);
Constant MAX_BURST_LEN_US : unsigned(BTT_SLICE_SIZE-1 downto 0) :=
TO_UNSIGNED(C_MAX_BURST_LEN-1, BTT_SLICE_SIZE);
Constant BTT_LS_UNUSED_WIDTH : integer := funct_get_btt_ls_unused(C_STREAM_DWIDTH);
Constant CMD_BTT_WIDTH : integer := BTT_SLICE_SIZE+BTT_LS_UNUSED_WIDTH;
Constant CMD_BTT_LS_INDEX : integer := 0;
Constant CMD_BTT_MS_INDEX : integer := CMD_BTT_WIDTH-1;
Constant BTT_ZEROS : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
Constant BTT_RESIDUE_ZEROS : unsigned(BTT_LS_UNUSED_WIDTH-1 downto 0) := (others => '0');
Constant BTT_SLICE_ONE : unsigned(BTT_SLICE_SIZE-1 downto 0) := TO_UNSIGNED(1, BTT_SLICE_SIZE);
Constant STRB_WIDTH : integer := C_STREAM_DWIDTH/8; -- Number of bytes in the Stream
Constant LEN_WIDTH : integer := 8;
-- Type Declarations --------------------------------------------
type SCC_SM_STATE_TYPE is (
INIT,
POP_RECOVER,
GET_NXT_CMD,
CHK_AND_CALC,
PUSH_TO_AXI,
ERROR_TRAP
);
-- Signal Declarations --------------------------------------------
signal sm_scc_state : SCC_SM_STATE_TYPE := INIT;
signal sm_scc_state_ns : SCC_SM_STATE_TYPE := INIT;
signal sm_pop_input_cmd : std_logic := '0';
signal sm_pop_input_cmd_ns : std_logic := '0';
signal sm_set_push2axi : std_logic := '0';
signal sm_set_push2axi_ns : std_logic := '0';
signal sm_set_error : std_logic := '0';
signal sm_set_error_ns : std_logic := '0';
Signal sm_scc_sm_ready : std_logic := '0';
Signal sm_scc_sm_ready_ns : std_logic := '0';
signal sig_cmd2data_valid : std_logic := '0';
signal sig_clr_cmd2data_valid : std_logic := '0';
signal sig_cmd2addr_valid : std_logic := '0';
signal sig_cmd2addr_valid1 : std_logic := '0';
signal sig_clr_cmd2addr_valid : std_logic := '0';
signal sig_addr_data_rdy_pending : std_logic := '0';
signal sig_cmd_btt_slice : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_load_input_cmd : std_logic := '0';
signal sig_cmd_reg_empty : std_logic := '0';
signal sig_cmd_reg_full : std_logic := '0';
signal sig_cmd_addr_reg : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd_btt_reg : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd_type_reg : std_logic := '0';
signal sig_cmd_burst_reg : std_logic_vector (1 downto 0) := "00";
signal sig_cmd_tag_reg : std_logic_vector(CMD_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_addr_data_rdy4cmd : std_logic := '0';
signal sig_btt_raw : std_logic := '0';
signal sig_btt_is_zero : std_logic := '0';
signal sig_btt_is_zero_reg : std_logic := '0';
signal sig_next_tag : std_logic_vector(CMD_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_next_addr : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_next_len : std_logic_vector(LEN_WIDTH-1 downto 0) := (others => '0');
signal sig_next_size : std_logic_vector(2 downto 0) := (others => '0');
signal sig_next_burst : std_logic_vector(1 downto 0) := (others => '0');
signal sig_next_cache : std_logic_vector(3 downto 0) := (others => '0');
signal sig_next_user : std_logic_vector(3 downto 0) := (others => '0');
signal sig_next_strt_strb : std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0) := (others => '0');
signal sig_next_end_strb : std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0) := (others => '0');
begin --(architecture implementation)
-- Assign calculation error output
calc_error <= sm_set_error;
-- Assign the ready output to the Command FIFO
mst2cmd_cmd_ready <= sig_cmd_reg_empty and addr2mstr_cmd_ready; --sm_scc_sm_ready;
-- Assign the Address Channel Controller Qualifiers
mstr2addr_tag <= sig_next_tag ;
mstr2addr_addr <= sig_next_addr ;
mstr2addr_len <= sig_next_len ;
mstr2addr_size <= sig_next_size ;
mstr2addr_burst <= sig_cmd_burst_reg;
mstr2addr_cache <= sig_next_cache;
mstr2addr_user <= sig_next_user;
mstr2addr_cmd_valid <= sig_cmd2addr_valid1;
mstr2addr_calc_error <= sm_set_error ;
mstr2addr_cmd_cmplt <= '1' ; -- Lite mode is always 1
-- Assign the Data Channel Controller Qualifiers
mstr2data_tag <= sig_next_tag ;
mstr2data_saddr_lsb <= sig_cmd_addr_reg(C_SEL_ADDR_WIDTH-1 downto 0);
mstr2data_len <= sig_next_len ;
mstr2data_strt_strb <= (others => '1'); --sig_next_strt_strb; -- always F
mstr2data_last_strb <= (others => '1'); --sig_next_end_strb; -- always F
mstr2data_sof <= '1'; -- Lite mode is always 1 cmd
mstr2data_eof <= '1'; -- Lite mode is always 1 cmd
mstr2data_cmd_cmplt <= '1'; -- Lite mode is always 1 cmd
-- mstr2data_cmd_valid <= sig_cmd2data_valid;
mstr2data_cmd_valid <= sig_cmd2addr_valid1; --sig_cmd2data_valid;
mstr2data_calc_error <= sm_set_error;
-- Internal logic ------------------------------
sig_addr_data_rdy_pending <= sig_cmd2addr_valid or
sig_cmd2data_valid;
sig_clr_cmd2data_valid <= sig_cmd2data_valid and data2mstr_cmd_ready;
sig_clr_cmd2addr_valid <= sig_cmd2addr_valid and addr2mstr_cmd_ready;
sig_load_input_cmd <= cmd2mstr_cmd_valid and
sig_cmd_reg_empty;-- and
-- sm_scc_sm_ready;
sig_next_tag <= sig_cmd_tag_reg;
sig_next_addr <= sig_cmd_addr_reg;
sig_addr_data_rdy4cmd <= addr2mstr_cmd_ready and data2mstr_cmd_ready;
sig_cmd_btt_slice <= cmd2mstr_command(CMD_BTT_MS_INDEX downto CMD_BTT_LS_INDEX);
sig_btt_is_zero <= '1'
when (sig_cmd_btt_slice = BTT_ZEROS)
Else '0';
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_NO_RESIDUE_BITS
--
-- If Generate Description:
--
--
--
------------------------------------------------------------
GEN_NO_RESIDUE_BITS : if (BTT_LS_UNUSED_WIDTH = 0) generate
-- signals
signal sig_len_btt_slice : unsigned(BTT_SLICE_SIZE-1 downto 0) := (others => '0');
signal sig_len_btt_slice_minus_1 : unsigned(BTT_SLICE_SIZE-1 downto 0) := (others => '0');
signal sig_len2use : unsigned(BTT_SLICE_SIZE-1 downto 0) := (others => '0');
begin
-- LEN Calculation logic ------------------------------------------
sig_next_len <= STD_LOGIC_VECTOR(RESIZE(sig_len2use, LEN_WIDTH));
sig_len_btt_slice <= UNSIGNED(sig_cmd_btt_reg(CMD_BTT_MS_INDEX downto 0));
sig_len_btt_slice_minus_1 <= sig_len_btt_slice-BTT_SLICE_ONE
when sig_btt_is_zero_reg = '0'
else (others => '0'); -- clip at zero
-- If most significant bit of BTT set then limit to
-- Max Burst Len, else rip it from the BTT value,
-- otheriwse subtract 1 from the BTT ripped value
-- 1 from the BTT ripped value
sig_len2use <= MAX_BURST_LEN_US
When (sig_cmd_btt_reg(CMD_BTT_MS_INDEX) = '1')
Else sig_len_btt_slice_minus_1;
end generate GEN_NO_RESIDUE_BITS;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_HAS_RESIDUE_BITS
--
-- If Generate Description:
--
--
--
------------------------------------------------------------
GEN_HAS_RESIDUE_BITS : if (BTT_LS_UNUSED_WIDTH > 0) generate
-- signals
signal sig_btt_len_residue : unsigned(BTT_LS_UNUSED_WIDTH-1 downto 0) := (others => '0');
signal sig_len_btt_slice : unsigned(BTT_SLICE_SIZE-1 downto 0) := (others => '0');
signal sig_len_btt_slice_minus_1 : unsigned(BTT_SLICE_SIZE-1 downto 0) := (others => '0');
signal sig_len2use : unsigned(BTT_SLICE_SIZE-1 downto 0) := (others => '0');
begin
-- LEN Calculation logic ------------------------------------------
WR_EXTRA_FIELDS : if (C_ENABLE_EXTRA_FIELD = 1) generate
sig_next_len <= "00000000" when sig_cmd_tag_reg (0) = '1'
else "00000101"; --STD_LOGIC_VECTOR(RESIZE(sig_len2use, LEN_WIDTH));
end generate WR_EXTRA_FIELDS;
NOWR_EXTRA_FIELDS : if (C_ENABLE_EXTRA_FIELD = 0) generate
sig_next_len <= "00000000";
end generate NOWR_EXTRA_FIELDS;
-- sig_next_len <= STD_LOGIC_VECTOR(RESIZE(sig_len2use, LEN_WIDTH));
sig_len_btt_slice <= UNSIGNED(sig_cmd_btt_reg(CMD_BTT_MS_INDEX downto BTT_LS_UNUSED_WIDTH));
sig_len_btt_slice_minus_1 <= sig_len_btt_slice-BTT_SLICE_ONE
when sig_btt_is_zero_reg = '0'
else (others => '0'); -- clip at zero
sig_btt_len_residue <= UNSIGNED(sig_cmd_btt_reg(BTT_LS_UNUSED_WIDTH-1 downto 0));
-- If most significant bit of BTT set then limit to
-- Max Burst Len, else rip it from the BTT value
-- However if residue bits are zeroes then subtract
-- 1 from the BTT ripped value
sig_len2use <= MAX_BURST_LEN_US
When (sig_cmd_btt_reg(CMD_BTT_MS_INDEX) = '1')
Else sig_len_btt_slice_minus_1
when (sig_btt_len_residue = BTT_RESIDUE_ZEROS)
Else sig_len_btt_slice;
end generate GEN_HAS_RESIDUE_BITS;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_INPUT_CMD
--
-- Process Description:
-- Implements the input command holding registers
--
-------------------------------------------------------------
REG_INPUT_CMD : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
addr2mstr_cmd_ready = '0') then
-- sm_pop_input_cmd = '1') then
sig_cmd_btt_reg <= (others => '0');
sig_cmd_type_reg <= '0';
sig_cmd_addr_reg <= (others => '0');
sig_cmd_tag_reg <= (others => '0');
sig_btt_is_zero_reg <= '0';
sig_cmd_reg_empty <= '1';
sig_cmd_reg_full <= '0';
sig_cmd_burst_reg <= "00";
sig_cmd2addr_valid1 <= '0';
elsif (sig_load_input_cmd = '1') then
sig_cmd_btt_reg <= sig_cmd_btt_slice;
sig_cmd_type_reg <= cmd2mstr_command(CMD_TYPE_INDEX);
sig_cmd_addr_reg <= cmd2mstr_command(CMD_ADDR_MS_INDEX downto CMD_ADDR_LS_INDEX);
sig_cmd_tag_reg <= cmd2mstr_command(CMD_TAG_MS_INDEX downto CMD_TAG_LS_INDEX);
sig_btt_is_zero_reg <= sig_btt_is_zero;
sig_cmd_reg_empty <= '0';
sig_cmd_reg_full <= '1';
sig_cmd2addr_valid1 <= '1';
sig_cmd_burst_reg <= sig_next_burst;
else
null; -- Hold current State
end if;
end if;
end process REG_INPUT_CMD;
-- Only Incrementing Burst type supported (per Interface_X guidelines)
sig_next_burst <= AXI_BURST_INCR when (cmd2mstr_command(CMD_TYPE_INDEX) = '1') else
AXI_BURST_FIXED;
sig_next_user <= cache2mstr_command (7 downto 4);
sig_next_cache <= cache2mstr_command (3 downto 0);
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_LEN_SDWIDTH_64
--
-- If Generate Description:
-- This IfGen implements the AXI LEN qualifier calculation
-- and the Stream data channel start/end STRB value.
--
-- This IfGen is for the 64-bit Stream data Width case.
--
------------------------------------------------------------
GEN_LEN_SDWIDTH_64 : if (C_STREAM_DWIDTH = 64) generate
-- Local Constants
Constant AXI_SIZE2USE : std_logic_vector(2 downto 0) := AXI_SIZE_8BYTE;
Constant RESIDUE_BIT_WIDTH : integer := 3;
-- local signals
signal sig_last_strb2use : std_logic_vector(STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_last_strb : std_logic_vector(STRB_WIDTH-1 downto 0) := (others => '0');
Signal sig_btt_ms_bit_value : std_logic := '0';
signal lsig_btt_len_residue : std_logic_vector(BTT_LS_UNUSED_WIDTH-1 downto 0) := (others => '0');
signal sig_btt_len_residue_composite : std_logic_vector(RESIDUE_BIT_WIDTH downto 0) := (others => '0');
-- note 1 extra bit implied
begin
-- Assign the Address Channel Controller Size Qualifier Value
sig_next_size <= AXI_SIZE2USE;
-- Assign the Strobe Values
sig_next_strt_strb <= (others => '1'); -- always aligned on first databeat for LITE DataMover
sig_next_end_strb <= sig_last_strb;
-- Local calculations ------------------------------
lsig_btt_len_residue <= sig_cmd_btt_reg(BTT_LS_UNUSED_WIDTH-1 downto 0);
sig_btt_ms_bit_value <= sig_cmd_btt_reg(CMD_BTT_MS_INDEX);
sig_btt_len_residue_composite <= sig_btt_ms_bit_value &
lsig_btt_len_residue;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: IMP_LAST_STRB_8bit
--
-- Process Description:
-- Generates the Strobe values for the LAST databeat of the
-- Burst to MMap when the Stream is 64 bits wide and 8 strobe
-- bits are required.
--
-------------------------------------------------------------
IMP_LAST_STRB_8bit : process (sig_btt_len_residue_composite)
begin
case sig_btt_len_residue_composite is
when "0001" =>
sig_last_strb <= "00000001";
when "0010" =>
sig_last_strb <= "00000011";
when "0011" =>
sig_last_strb <= "00000111";
when "0100" =>
sig_last_strb <= "00001111";
when "0101" =>
sig_last_strb <= "00011111";
when "0110" =>
sig_last_strb <= "00111111";
when "0111" =>
sig_last_strb <= "01111111";
when others =>
sig_last_strb <= "11111111";
end case;
end process IMP_LAST_STRB_8bit;
end generate GEN_LEN_SDWIDTH_64;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_LEN_SDWIDTH_32
--
-- If Generate Description:
-- This IfGen implements the AXI LEN qualifier calculation
-- and the Stream data channel start/end STRB value.
--
-- This IfGen is for the 32-bit Stream data Width case.
--
------------------------------------------------------------
GEN_LEN_SDWIDTH_32 : if (C_STREAM_DWIDTH = 32) generate
-- Local Constants
Constant AXI_SIZE2USE : std_logic_vector(2 downto 0) := AXI_SIZE_4BYTE;
Constant RESIDUE_BIT_WIDTH : integer := 2;
-- local signals
signal sig_last_strb2use : std_logic_vector(STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_last_strb : std_logic_vector(STRB_WIDTH-1 downto 0) := (others => '0');
Signal sig_btt_ms_bit_value : std_logic := '0';
signal sig_btt_len_residue_composite : std_logic_vector(RESIDUE_BIT_WIDTH downto 0) := (others => '0'); -- 1 extra bit
signal lsig_btt_len_residue : std_logic_vector(BTT_LS_UNUSED_WIDTH-1 downto 0) := (others => '0');
begin
-- Assign the Address Channel Controller Size Qualifier Value
sig_next_size <= AXI_SIZE2USE;
-- Assign the Strobe Values
sig_next_strt_strb <= (others => '1'); -- always aligned on first databeat for LITE DataMover
sig_next_end_strb <= sig_last_strb;
-- Local calculations ------------------------------
lsig_btt_len_residue <= sig_cmd_btt_reg(BTT_LS_UNUSED_WIDTH-1 downto 0);
sig_btt_ms_bit_value <= sig_cmd_btt_reg(CMD_BTT_MS_INDEX);
sig_btt_len_residue_composite <= sig_btt_ms_bit_value &
lsig_btt_len_residue;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: IMP_LAST_STRB_4bit
--
-- Process Description:
-- Generates the Strobe values for the LAST databeat of the
-- Burst to MMap when the Stream is 32 bits wide and 4 strobe
-- bits are required.
--
-------------------------------------------------------------
IMP_LAST_STRB_4bit : process (sig_btt_len_residue_composite)
begin
case sig_btt_len_residue_composite is
-- coverage off
when "001" =>
sig_last_strb <= "0001";
when "010" =>
sig_last_strb <= "0011";
when "011" =>
sig_last_strb <= "0111";
-- coverage on
when others =>
sig_last_strb <= "1111";
end case;
end process IMP_LAST_STRB_4bit;
end generate GEN_LEN_SDWIDTH_32;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_LEN_SDWIDTH_16
--
-- If Generate Description:
-- This IfGen implements the AXI LEN qualifier calculation
-- and the Stream data channel start/end STRB value.
--
-- This IfGen is for the 16-bit Stream data Width case.
--
------------------------------------------------------------
GEN_LEN_SDWIDTH_16 : if (C_STREAM_DWIDTH = 16) generate
-- Local Constants
Constant AXI_SIZE2USE : std_logic_vector(2 downto 0) := AXI_SIZE_2BYTE;
Constant RESIDUE_BIT_WIDTH : integer := 1;
-- local signals
signal sig_last_strb2use : std_logic_vector(STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_last_strb : std_logic_vector(STRB_WIDTH-1 downto 0) := (others => '0');
Signal sig_btt_ms_bit_value : std_logic := '0';
signal sig_btt_len_residue_composite : std_logic_vector(RESIDUE_BIT_WIDTH downto 0) := (others => '0'); -- 1 extra bit
signal lsig_btt_len_residue : std_logic_vector(BTT_LS_UNUSED_WIDTH-1 downto 0) := (others => '0');
begin
-- Assign the Address Channel Controller Size Qualifier Value
sig_next_size <= AXI_SIZE2USE;
-- Assign the Strobe Values
sig_next_strt_strb <= (others => '1'); -- always aligned on first databeat for LITE DataMover
sig_next_end_strb <= sig_last_strb;
-- Local calculations ------------------------------
lsig_btt_len_residue <= sig_cmd_btt_reg(BTT_LS_UNUSED_WIDTH-1 downto 0);
sig_btt_ms_bit_value <= sig_cmd_btt_reg(CMD_BTT_MS_INDEX);
sig_btt_len_residue_composite <= sig_btt_ms_bit_value &
lsig_btt_len_residue;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: IMP_LAST_STRB_2bit
--
-- Process Description:
-- Generates the Strobe values for the LAST databeat of the
-- Burst to MMap when the Stream is 16 bits wide and 2 strobe
-- bits are required.
--
-------------------------------------------------------------
IMP_LAST_STRB_2bit : process (sig_btt_len_residue_composite)
begin
case sig_btt_len_residue_composite is
when "01" =>
sig_last_strb <= "01";
when others =>
sig_last_strb <= "11";
end case;
end process IMP_LAST_STRB_2bit;
end generate GEN_LEN_SDWIDTH_16;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_LEN_SDWIDTH_8
--
-- If Generate Description:
-- This IfGen implements the AXI LEN qualifier calculation
-- and the Stream data channel start/end STRB value.
--
-- This IfGen is for the 8-bit Stream data Width case.
--
------------------------------------------------------------
GEN_LEN_SDWIDTH_8 : if (C_STREAM_DWIDTH = 8) generate
-- Local Constants
Constant AXI_SIZE2USE : std_logic_vector(2 downto 0) := AXI_SIZE_1BYTE;
begin
-- Assign the Address Channel Controller Qualifiers
sig_next_size <= AXI_SIZE2USE;
-- Assign the Data Channel Controller Qualifiers
sig_next_strt_strb <= (others => '1');
sig_next_end_strb <= (others => '1');
end generate GEN_LEN_SDWIDTH_8;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: CMD2DATA_VALID_FLOP
--
-- Process Description:
-- Implements the set/reset flop for the Command Ready control
-- to the Data Controller Module.
--
-------------------------------------------------------------
CMD2DATA_VALID_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_clr_cmd2data_valid = '1') then
sig_cmd2data_valid <= '0';
elsif (sm_set_push2axi_ns = '1') then
sig_cmd2data_valid <= '1';
else
null; -- hold current state
end if;
end if;
end process CMD2DATA_VALID_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: CMD2ADDR_VALID_FLOP
--
-- Process Description:
-- Implements the set/reset flop for the Command Ready control
-- to the Address Controller Module.
--
-------------------------------------------------------------
CMD2ADDR_VALID_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_clr_cmd2addr_valid = '1') then
sig_cmd2addr_valid <= '0';
elsif (sm_set_push2axi_ns = '1') then
sig_cmd2addr_valid <= '1';
else
null; -- hold current state
end if;
end if;
end process CMD2ADDR_VALID_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: SCC_SM_REG
--
-- Process Description:
-- Implements registered portion of state machine
--
-------------------------------------------------------------
SCC_SM_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
-- sm_scc_state <= INIT;
-- sm_pop_input_cmd <= '0' ;
-- sm_set_push2axi <= '0' ;
sm_set_error <= '0' ;
-- sm_scc_sm_ready <= '0' ;
elsif (sig_btt_is_zero_reg = '1') then
sm_set_error <= '1';
-- sm_scc_state <= sm_scc_state_ns ;
-- sm_pop_input_cmd <= sm_pop_input_cmd_ns ;
-- sm_set_push2axi <= sm_set_push2axi_ns ;
-- sm_set_error <= sm_set_error_ns ;
-- sm_scc_sm_ready <= sm_scc_sm_ready_ns ;
end if;
end if;
end process SCC_SM_REG;
end implementation;
| gpl-3.0 |
mistryalok/Zedboard | learning/training/Microsystem/axi_interface_part2/project_1/project_1.srcs/sources_1/ipshared/xilinx.com/axi_bram_ctrl_v4_0/b6365b74/hdl/vhdl/parity.vhd | 7 | 11625 | -------------------------------------------------------------------------------
-- parity.vhd
-------------------------------------------------------------------------------
--
--
-- (c) Copyright [2010 - 2013] Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--
------------------------------------------------------------------------------
-- Filename: parity.vhd
--
-- Description: Generate parity optimally for all target architectures.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- axi_bram_ctrl.vhd (v1_03_a)
-- |
-- |-- full_axi.vhd
-- | -- sng_port_arb.vhd
-- | -- lite_ecc_reg.vhd
-- | -- axi_lite_if.vhd
-- | -- wr_chnl.vhd
-- | -- wrap_brst.vhd
-- | -- ua_narrow.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- checkbit_handler_64.vhd
-- | -- (same helper components as checkbit_handler)
-- | -- parity.vhd
-- | -- correct_one_bit.vhd
-- | -- correct_one_bit_64.vhd
-- |
-- | -- rd_chnl.vhd
-- | -- wrap_brst.vhd
-- | -- ua_narrow.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- checkbit_handler_64.vhd
-- | -- (same helper components as checkbit_handler)
-- | -- parity.vhd
-- | -- correct_one_bit.vhd
-- | -- correct_one_bit_64.vhd
-- |
-- |-- axi_lite.vhd
-- | -- lite_ecc_reg.vhd
-- | -- axi_lite_if.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- checkbit_handler_64.vhd
-- | -- (same helper components as checkbit_handler)
-- | -- correct_one_bit.vhd
-- | -- correct_one_bit_64.vhd
--
--
--
-------------------------------------------------------------------------------
--
-- History:
--
-- ^^^^^^
-- JLJ 2/2/2011 v1.03a
-- ~~~~~~
-- Migrate to v1.03a.
-- Plus minor code cleanup.
-- ^^^^^^
--
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity Parity is
generic (
C_USE_LUT6 : boolean := true;
C_SIZE : integer := 6
);
port (
InA : in std_logic_vector(0 to C_SIZE - 1);
Res : out std_logic
);
end entity Parity;
library unisim;
use unisim.vcomponents.all;
architecture IMP of Parity is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of IMP : architecture is "yes";
-- Non-recursive loop implementation
function ParityGen (InA : std_logic_vector) return std_logic is
variable result : std_logic;
begin
result := '0';
for I in InA'range loop
result := result xor InA(I);
end loop;
return result;
end function ParityGen;
begin -- architecture IMP
Using_LUT6 : if (C_USE_LUT6) generate
--------------------------------------------------------------------------------------------------
-- Single LUT6
--------------------------------------------------------------------------------------------------
Single_LUT6 : if C_SIZE > 1 and C_SIZE <= 6 generate
signal inA6 : std_logic_vector(0 to 5);
begin
Assign_InA : process (InA) is
begin
inA6 <= (others => '0');
inA6(0 to InA'length - 1) <= InA;
end process Assign_InA;
XOR6_LUT : LUT6
generic map(
INIT => X"6996966996696996")
port map(
O => Res,
I0 => inA6(5),
I1 => inA6(4),
I2 => inA6(3),
I3 => inA6(2),
I4 => inA6(1),
I5 => inA6(0));
end generate Single_LUT6;
--------------------------------------------------------------------------------------------------
-- Two LUT6 and one MUXF7
--------------------------------------------------------------------------------------------------
Use_MUXF7 : if C_SIZE = 7 generate
signal inA7 : std_logic_vector(0 to 6);
signal result6 : std_logic;
signal result6n : std_logic;
begin
Assign_InA : process (InA) is
begin
inA7 <= (others => '0');
inA7(0 to InA'length - 1) <= InA;
end process Assign_InA;
XOR6_LUT : LUT6
generic map(
INIT => X"6996966996696996")
port map(
O => result6,
I0 => inA7(5),
I1 => inA7(4),
I2 => inA7(3),
I3 => inA7(2),
I4 => inA7(1),
I5 => inA7(0));
XOR6_LUT_N : LUT6
generic map(
INIT => X"9669699669969669")
port map(
O => result6n,
I0 => inA7(5),
I1 => inA7(4),
I2 => inA7(3),
I3 => inA7(2),
I4 => inA7(1),
I5 => inA7(0));
MUXF7_LUT : MUXF7
port map (
O => Res,
I0 => result6,
I1 => result6n,
S => inA7(6));
end generate Use_MUXF7;
--------------------------------------------------------------------------------------------------
-- Four LUT6, two MUXF7 and one MUXF8
--------------------------------------------------------------------------------------------------
Use_MUXF8 : if C_SIZE = 8 generate
signal inA8 : std_logic_vector(0 to 7);
signal result6_1 : std_logic;
signal result6_1n : std_logic;
signal result6_2 : std_logic;
signal result6_2n : std_logic;
signal result7_1 : std_logic;
signal result7_1n : std_logic;
begin
Assign_InA : process (InA) is
begin
inA8 <= (others => '0');
inA8(0 to InA'length - 1) <= InA;
end process Assign_InA;
XOR6_LUT1 : LUT6
generic map(
INIT => X"6996966996696996")
port map(
O => result6_1,
I0 => inA8(5),
I1 => inA8(4),
I2 => inA8(3),
I3 => inA8(2),
I4 => inA8(1),
I5 => inA8(0));
XOR6_LUT2_N : LUT6
generic map(
INIT => X"9669699669969669")
port map(
O => result6_1n,
I0 => inA8(5),
I1 => inA8(4),
I2 => inA8(3),
I3 => inA8(2),
I4 => inA8(1),
I5 => inA8(0));
MUXF7_LUT1 : MUXF7
port map (
O => result7_1,
I0 => result6_1,
I1 => result6_1n,
S => inA8(6));
XOR6_LUT3 : LUT6
generic map(
INIT => X"6996966996696996")
port map(
O => result6_2,
I0 => inA8(5),
I1 => inA8(4),
I2 => inA8(3),
I3 => inA8(2),
I4 => inA8(1),
I5 => inA8(0));
XOR6_LUT4_N : LUT6
generic map(
INIT => X"9669699669969669")
port map(
O => result6_2n,
I0 => inA8(5),
I1 => inA8(4),
I2 => inA8(3),
I3 => inA8(2),
I4 => inA8(1),
I5 => inA8(0));
MUXF7_LUT2 : MUXF7
port map (
O => result7_1n,
I0 => result6_2n,
I1 => result6_2,
S => inA8(6));
MUXF8_LUT : MUXF8
port map (
O => res,
I0 => result7_1,
I1 => result7_1n,
S => inA8(7));
end generate Use_MUXF8;
end generate Using_LUT6;
-- Fall-back implementation without LUT6
Not_Using_LUT6 : if not C_USE_LUT6 or C_SIZE > 8 generate
begin
Res <= ParityGen(InA);
end generate Not_Using_LUT6;
end architecture IMP;
| gpl-3.0 |
mistryalok/Zedboard | learning/training/MSD/s09/axi_dma_sg/vivado/project_1/project_1.srcs/sources_1/ipshared/xilinx.com/axi_gpio_v2_0/58435b11/hdl/src/vhdl/gpio_core.vhd | 5 | 35411 | -------------------------------------------------------------------------------
-- gpio_core - entity/architecture pair
-------------------------------------------------------------------------------
-- ***************************************************************************
-- DISCLAIMER OF LIABILITY
--
-- This file contains proprietary and confidential information of
-- Xilinx, Inc. ("Xilinx"), that is distributed under a license
-- from Xilinx, and may be used, copied and/or disclosed only
-- pursuant to the terms of a valid license agreement with Xilinx.
--
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
-- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
-- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
-- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
-- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
-- does not warrant that functions included in the Materials will
-- meet the requirements of Licensee, or that the operation of the
-- Materials will be uninterrupted or error-free, or that defects
-- in the Materials will be corrected. Furthermore, Xilinx does
-- not warrant or make any representations regarding use, or the
-- results of the use, of the Materials in terms of correctness,
-- accuracy, reliability or otherwise.
--
-- Xilinx products are not designed or intended to be fail-safe,
-- or for use in any application requiring fail-safe performance,
-- such as life-support or safety devices or systems, Class III
-- medical devices, nuclear facilities, applications related to
-- the deployment of airbags, or any other applications that could
-- lead to death, personal injury or severe property or
-- environmental damage (individually and collectively, "critical
-- applications"). Customer assumes the sole risk and liability
-- of any use of Xilinx products in critical applications,
-- subject only to applicable laws and regulations governing
-- limitations on product liability.
--
-- Copyright 2009 Xilinx, Inc.
-- All rights reserved.
--
-- This disclaimer and copyright notice must be retained as part
-- of this file at all times.
-- ***************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: gpio_core.vhd
-- Version: v1.01a
-- Description: General Purpose I/O for AXI Interface
--
-------------------------------------------------------------------------------
-- Structure:
-- axi_gpio.vhd
-- -- axi_lite_ipif.vhd
-- -- interrupt_control.vhd
-- -- gpio_core.vhd
--
-------------------------------------------------------------------------------
--
-- Author: KSB
-- History:
-- ~~~~~~~~~~~~~~
-- KSB 09/15/09
-- ^^^^^^^^^^^^^^
-- ~~~~~~~~~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library lib_cdc_v1_0;
-------------------------------------------------------------------------------
-- Definition of Generics : --
-------------------------------------------------------------------------------
-- C_DW -- Data width of PLB BUS.
-- C_AW -- Address width of PLB BUS.
-- C_GPIO_WIDTH -- GPIO Data Bus width.
-- C_GPIO2_WIDTH -- GPIO2 Data Bus width.
-- C_INTERRUPT_PRESENT -- GPIO Interrupt.
-- C_DOUT_DEFAULT -- GPIO_DATA Register reset value.
-- C_TRI_DEFAULT -- GPIO_TRI Register reset value.
-- C_IS_DUAL -- Dual Channel GPIO.
-- C_DOUT_DEFAULT_2 -- GPIO2_DATA Register reset value.
-- C_TRI_DEFAULT_2 -- GPIO2_TRI Register reset value.
-- C_FAMILY -- XILINX FPGA family
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Ports --
-------------------------------------------------------------------------------
-- Clk -- Input clock
-- Rst -- Reset
-- ABus_Reg -- Bus to IP address
-- BE_Reg -- Bus to IP byte enables
-- DBus_Reg -- Bus to IP data bus
-- RNW_Reg -- Bus to IP read write control
-- GPIO_DBus -- IP to Bus data bus
-- GPIO_xferAck -- GPIO transfer acknowledge
-- GPIO_intr -- GPIO channel 1 interrupt to IPIC
-- GPIO2_intr -- GPIO channel 2 interrupt to IPIC
-- GPIO_Select -- GPIO select
--
-- GPIO_IO_I -- Channel 1 General purpose I/O in port
-- GPIO_IO_O -- Channel 1 General purpose I/O out port
-- GPIO_IO_T -- Channel 1 General purpose I/O TRI-STATE control port
-- GPIO2_IO_I -- Channel 2 General purpose I/O in port
-- GPIO2_IO_O -- Channel 2 General purpose I/O out port
-- GPIO2_IO_T -- Channel 2 General purpose I/O TRI-STATE control port
-------------------------------------------------------------------------------
entity GPIO_Core is
generic
(
C_DW : integer := 32;
C_AW : integer := 32;
C_GPIO_WIDTH : integer := 32;
C_GPIO2_WIDTH : integer := 32;
C_MAX_GPIO_WIDTH : integer := 32;
C_INTERRUPT_PRESENT : integer := 0;
C_DOUT_DEFAULT : std_logic_vector (0 to 31) := X"0000_0000";
C_TRI_DEFAULT : std_logic_vector (0 to 31) := X"FFFF_FFFF";
C_IS_DUAL : integer := 0;
C_DOUT_DEFAULT_2 : std_logic_vector (0 to 31) := X"0000_0000";
C_TRI_DEFAULT_2 : std_logic_vector (0 to 31) := X"FFFF_FFFF";
C_FAMILY : string := "virtex7"
);
port
(
Clk : in std_logic;
Rst : in std_logic;
ABus_Reg : in std_logic_vector(0 to C_AW-1);
BE_Reg : in std_logic_vector(0 to C_DW/8-1);
DBus_Reg : in std_logic_vector(0 to C_MAX_GPIO_WIDTH-1);
RNW_Reg : in std_logic;
GPIO_DBus : out std_logic_vector(0 to C_DW-1);
GPIO_xferAck : out std_logic;
GPIO_intr : out std_logic;
GPIO2_intr : out std_logic;
GPIO_Select : in std_logic;
GPIO_IO_I : in std_logic_vector(0 to C_GPIO_WIDTH-1);
GPIO_IO_O : out std_logic_vector(0 to C_GPIO_WIDTH-1);
GPIO_IO_T : out std_logic_vector(0 to C_GPIO_WIDTH-1);
GPIO2_IO_I : in std_logic_vector(0 to C_GPIO2_WIDTH-1);
GPIO2_IO_O : out std_logic_vector(0 to C_GPIO2_WIDTH-1);
GPIO2_IO_T : out std_logic_vector(0 to C_GPIO2_WIDTH-1)
);
end entity GPIO_Core;
-------------------------------------------------------------------------------
-- Architecture section
-------------------------------------------------------------------------------
architecture IMP of GPIO_Core is
-- Pragma Added to supress synth warnings
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of IMP : architecture is "yes";
----------------------------------------------------------------------
-- Function for Reduction OR
----------------------------------------------------------------------
function or_reduce(l : std_logic_vector) return std_logic is
variable v : std_logic := '0';
begin
for i in l'range loop
v := v or l(i);
end loop;
return v;
end;
---------------------------------------------------------------------
-- End of Function
-------------------------------------------------------------------
signal gpio_Data_Select : std_logic_vector(0 to C_IS_DUAL);
signal gpio_OE_Select : std_logic_vector(0 to C_IS_DUAL);
signal Read_Reg_Rst : STD_LOGIC;
signal Read_Reg_In : std_logic_vector(0 to C_GPIO_WIDTH-1);
signal Read_Reg_CE : std_logic_vector(0 to C_GPIO_WIDTH-1);
signal gpio_Data_Out : std_logic_vector(0 to C_GPIO_WIDTH-1) := C_DOUT_DEFAULT(C_DW-C_GPIO_WIDTH to C_DW-1);
signal gpio_Data_In : std_logic_vector(0 to C_GPIO_WIDTH-1);
signal gpio_in_d1 : std_logic_vector(0 to C_GPIO_WIDTH-1);
signal gpio_in_d2 : std_logic_vector(0 to C_GPIO_WIDTH-1);
signal gpio_io_i_d1 : std_logic_vector(0 to C_GPIO_WIDTH-1);
signal gpio_io_i_d2 : std_logic_vector(0 to C_GPIO_WIDTH-1);
signal gpio_OE : std_logic_vector(0 to C_GPIO_WIDTH-1) := C_TRI_DEFAULT(C_DW-C_GPIO_WIDTH to C_DW-1);
signal GPIO_DBus_i : std_logic_vector(0 to C_DW-1);
signal gpio_data_in_xor : std_logic_vector(0 to C_GPIO_WIDTH-1);
signal gpio_data_in_xor_reg : std_logic_vector(0 to C_GPIO_WIDTH-1);
signal or_ints : std_logic_vector(0 to 0);
signal or_ints2 : std_logic_vector(0 to 0);
signal iGPIO_xferAck : STD_LOGIC;
signal gpio_xferAck_Reg : STD_LOGIC;
signal dout_default_i : std_logic_vector(0 to C_GPIO_WIDTH-1);
signal tri_default_i : std_logic_vector(0 to C_GPIO_WIDTH-1);
signal reset_zeros : std_logic_vector(0 to C_GPIO_WIDTH-1);
signal dout2_default_i : std_logic_vector(0 to C_GPIO2_WIDTH-1);
signal tri2_default_i : std_logic_vector(0 to C_GPIO2_WIDTH-1);
signal reset2_zeros : std_logic_vector(0 to C_GPIO2_WIDTH-1);
signal gpio_reg_en : std_logic;
begin -- architecture IMP
reset_zeros <= (others => '0');
reset2_zeros <= (others => '0');
TIE_DEFAULTS_GENERATE : if C_DW >= C_GPIO_WIDTH generate
SELECT_BITS_GENERATE : for i in 0 to C_GPIO_WIDTH-1 generate
dout_default_i(i) <= C_DOUT_DEFAULT(i-C_GPIO_WIDTH+C_DW);
tri_default_i(i) <= C_TRI_DEFAULT(i-C_GPIO_WIDTH+C_DW);
end generate SELECT_BITS_GENERATE;
end generate TIE_DEFAULTS_GENERATE;
TIE_DEFAULTS_2_GENERATE : if C_DW >= C_GPIO2_WIDTH generate
SELECT_BITS_2_GENERATE : for i in 0 to C_GPIO2_WIDTH-1 generate
dout2_default_i(i) <= C_DOUT_DEFAULT_2(i-C_GPIO2_WIDTH+C_DW);
tri2_default_i(i) <= C_TRI_DEFAULT_2(i-C_GPIO2_WIDTH+C_DW);
end generate SELECT_BITS_2_GENERATE;
end generate TIE_DEFAULTS_2_GENERATE;
Read_Reg_Rst <= iGPIO_xferAck or gpio_xferAck_Reg or (not GPIO_Select) or
(GPIO_Select and not RNW_Reg);
gpio_reg_en <= GPIO_Select when (ABus_Reg(0) = '0') else '0';
-----------------------------------------------------------------------------
-- XFER_ACK_PROCESS
-----------------------------------------------------------------------------
-- Generation of Transfer Ack signal for one clock pulse
-----------------------------------------------------------------------------
XFER_ACK_PROCESS : process (Clk) is
begin
if (Clk'EVENT and Clk = '1') then
if (Rst = '1') then
iGPIO_xferAck <= '0';
else
iGPIO_xferAck <= GPIO_Select and not gpio_xferAck_Reg;
if iGPIO_xferAck = '1' then
iGPIO_xferAck <= '0';
end if;
end if;
end if;
end process XFER_ACK_PROCESS;
-----------------------------------------------------------------------------
-- DELAYED_XFER_ACK_PROCESS
-----------------------------------------------------------------------------
-- Single Reg stage to make Transfer Ack period one clock pulse wide
-----------------------------------------------------------------------------
DELAYED_XFER_ACK_PROCESS : process (Clk) is
begin
if (Clk'EVENT and Clk = '1') then
if (Rst = '1') then
gpio_xferAck_Reg <= '0';
else
gpio_xferAck_Reg <= iGPIO_xferAck;
end if;
end if;
end process DELAYED_XFER_ACK_PROCESS;
GPIO_xferAck <= iGPIO_xferAck;
-----------------------------------------------------------------------------
-- Drive GPIO interrupts to '0' when interrupt not present
-----------------------------------------------------------------------------
DONT_GEN_INTERRUPT : if (C_INTERRUPT_PRESENT = 0) generate
gpio_intr <= '0';
gpio2_intr <= '0';
end generate DONT_GEN_INTERRUPT;
----------------------------------------------------------------------------
-- When only one channel is used, the additional logic for the second
-- channel ports is not present
-----------------------------------------------------------------------------
Not_Dual : if (C_IS_DUAL = 0) generate
GPIO2_IO_O <= C_DOUT_DEFAULT(0 to C_GPIO2_WIDTH-1);
GPIO2_IO_T <= C_TRI_DEFAULT_2(0 to C_GPIO2_WIDTH-1);
READ_REG_GEN : for i in 0 to C_GPIO_WIDTH-1 generate
----------------------------------------------------------------------------
-- XFER_ACK_PROCESS
----------------------------------------------------------------------------
-- Generation of Transfer Ack signal for one clock pulse
----------------------------------------------------------------------------
GPIO_DBUS_I_PROC : process(Clk)
begin
if Clk'event and Clk = '1' then
if Read_Reg_Rst = '1' then
GPIO_DBus_i(i-C_GPIO_WIDTH+C_DW) <= '0';
else
GPIO_DBus_i(i-C_GPIO_WIDTH+C_DW) <= Read_Reg_In(i);
end if;
end if;
end process;
end generate READ_REG_GEN;
TIE_DBUS_GENERATE : if C_DW > C_GPIO_WIDTH generate
GPIO_DBus_i(0 to C_DW-C_GPIO_WIDTH-1) <= (others => '0');
end generate TIE_DBUS_GENERATE;
-----------------------------------------------------------------------------
-- GPIO_DBUS_PROCESS
-----------------------------------------------------------------------------
-- This process generates the GPIO DATA BUS from the GPIO_DBUS_I based on
-- the channel select signals
-----------------------------------------------------------------------------
GPIO_DBus <= GPIO_DBus_i;
-----------------------------------------------------------------------------
-- REG_SELECT_PROCESS
-----------------------------------------------------------------------------
-- GPIO REGISTER selection decoder for single channel configuration
-----------------------------------------------------------------------------
--REG_SELECT_PROCESS : process (GPIO_Select, ABus_Reg) is
REG_SELECT_PROCESS : process (gpio_reg_en, ABus_Reg) is
begin
gpio_Data_Select(0) <= '0';
gpio_OE_Select(0) <= '0';
--if GPIO_Select = '1' then
if gpio_reg_en = '1' then
if (ABus_Reg(5) = '0') then
case ABus_Reg(6) is -- bit A29
when '0' => gpio_Data_Select(0) <= '1';
when '1' => gpio_OE_Select(0) <= '1';
-- coverage off
when others => null;
-- coverage on
end case;
end if;
end if;
end process REG_SELECT_PROCESS;
INPUT_DOUBLE_REGS3 : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 0,
C_VECTOR_WIDTH => C_GPIO_WIDTH,
C_MTBF_STAGES => 4
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => '0',
prmry_vect_in => GPIO_IO_I,
scndry_aclk => Clk,
scndry_resetn => '0',
scndry_out => open,
scndry_vect_out => gpio_io_i_d2
);
---------------------------------------------------------------------------
-- GPIO_INDATA_BIRDIR_PROCESS
---------------------------------------------------------------------------
-- Reading of channel 1 data from Bidirectional GPIO port
-- to GPIO_DATA REGISTER
---------------------------------------------------------------------------
GPIO_INDATA_BIRDIR_PROCESS : process(Clk) is
begin
if Clk = '1' and Clk'EVENT then
-- gpio_io_i_d1 <= GPIO_IO_I;
-- gpio_io_i_d2 <= gpio_io_i_d1;
gpio_Data_In <= gpio_io_i_d2;
end if;
end process GPIO_INDATA_BIRDIR_PROCESS;
---------------------------------------------------------------------------
-- READ_MUX_PROCESS
---------------------------------------------------------------------------
-- Selects GPIO_TRI control or GPIO_DATA Register to be read
---------------------------------------------------------------------------
READ_MUX_PROCESS : process (gpio_Data_In, gpio_Data_Select, gpio_OE,
gpio_OE_Select) is
begin
Read_Reg_In <= (others => '0');
if gpio_Data_Select(0) = '1' then
Read_Reg_In <= gpio_Data_In;
elsif gpio_OE_Select(0) = '1' then
Read_Reg_In <= gpio_OE;
end if;
end process READ_MUX_PROCESS;
---------------------------------------------------------------------------
-- GPIO_OUTDATA_PROCESS
---------------------------------------------------------------------------
-- Writing to Channel 1 GPIO_DATA REGISTER
---------------------------------------------------------------------------
GPIO_OUTDATA_PROCESS : process(Clk) is
begin
if Clk = '1' and Clk'EVENT then
if (Rst = '1') then
gpio_Data_Out <= dout_default_i;
elsif gpio_Data_Select(0) = '1' and RNW_Reg = '0' then
for i in 0 to C_GPIO_WIDTH-1 loop
gpio_Data_Out(i) <= DBus_Reg(i);
end loop;
end if;
end if;
end process GPIO_OUTDATA_PROCESS;
---------------------------------------------------------------------------
-- GPIO_OE_PROCESS
---------------------------------------------------------------------------
-- Writing to Channel 1 GPIO_TRI Control REGISTER
---------------------------------------------------------------------------
GPIO_OE_PROCESS : process(Clk) is
begin
if Clk = '1' and Clk'EVENT then
if (Rst = '1') then
gpio_OE <= tri_default_i;
elsif gpio_OE_Select(0) = '1' and RNW_Reg = '0' then
for i in 0 to C_GPIO_WIDTH-1 loop
gpio_OE(i) <= DBus_Reg(i);
end loop;
end if;
end if;
end process GPIO_OE_PROCESS;
GPIO_IO_O <= gpio_Data_Out;
GPIO_IO_T <= gpio_OE;
----------------------------------------------------------------------------
-- INTERRUPT IS PRESENT
----------------------------------------------------------------------------
-- When the C_INTERRUPT_PRESENT=1, the interrupt is driven based on whether
-- there is a change in the data coming in at the GPIO_IO_I port or GPIO_In
-- port
----------------------------------------------------------------------------
GEN_INTERRUPT : if (C_INTERRUPT_PRESENT = 1) generate
gpio_data_in_xor <= gpio_Data_In xor gpio_io_i_d2;
-------------------------------------------------------------------------
-- An interrupt conditon exists if there is a change on any bit.
-------------------------------------------------------------------------
or_ints(0) <= or_reduce(gpio_data_in_xor_reg);
-------------------------------------------------------------------------
-- Registering Interrupt condition
-------------------------------------------------------------------------
REGISTER_XOR_INTR : process (Clk) is
begin
if (Clk'EVENT and Clk = '1') then
if (Rst = '1') then
gpio_data_in_xor_reg <= reset_zeros;
GPIO_intr <= '0';
else
gpio_data_in_xor_reg <= gpio_data_in_xor;
GPIO_intr <= or_ints(0);
end if;
end if;
end process REGISTER_XOR_INTR;
gpio2_intr <= '0'; -- Channel 2 interrupt is driven low
end generate GEN_INTERRUPT;
end generate Not_Dual;
---)(------------------------------------------------------------------------
-- When both the channels are used, the additional logic for the second
-- channel ports
-----------------------------------------------------------------------------
Dual : if (C_IS_DUAL = 1) generate
signal gpio2_Data_In : std_logic_vector(0 to C_GPIO2_WIDTH-1);
signal gpio2_in_d1 : std_logic_vector(0 to C_GPIO2_WIDTH-1);
signal gpio2_in_d2 : std_logic_vector(0 to C_GPIO2_WIDTH-1);
signal gpio2_io_i_d1 : std_logic_vector(0 to C_GPIO2_WIDTH-1);
signal gpio2_io_i_d2 : std_logic_vector(0 to C_GPIO2_WIDTH-1);
signal gpio2_data_in_xor : std_logic_vector(0 to C_GPIO2_WIDTH-1);
signal gpio2_data_in_xor_reg : std_logic_vector(0 to C_GPIO2_WIDTH-1);
signal gpio2_Data_Out : std_logic_vector(0 to C_GPIO2_WIDTH-1) := C_DOUT_DEFAULT_2(C_DW-C_GPIO2_WIDTH to C_DW-1);
signal gpio2_OE : std_logic_vector(0 to C_GPIO2_WIDTH-1) := C_TRI_DEFAULT_2(C_DW-C_GPIO2_WIDTH to C_DW-1);
signal Read_Reg2_In : std_logic_vector(0 to C_GPIO2_WIDTH-1);
signal Read_Reg2_CE : std_logic_vector(0 to C_GPIO2_WIDTH-1);
signal GPIO2_DBus_i : std_logic_vector(0 to C_DW-1);
begin
READ_REG_GEN : for i in 0 to C_GPIO_WIDTH-1 generate
begin
--------------------------------------------------------------------------
-- GPIO_DBUS_I_PROCESS
--------------------------------------------------------------------------
-- This process generates the GPIO CHANNEL1 DATA BUS
--------------------------------------------------------------------------
GPIO_DBUS_I_PROC : process(Clk)
begin
if Clk'event and Clk = '1' then
if Read_Reg_Rst = '1' then
GPIO_DBus_i(i-C_GPIO_WIDTH+C_DW) <= '0';
else
GPIO_DBus_i(i-C_GPIO_WIDTH+C_DW) <= Read_Reg_In(i);
end if;
end if;
end process;
end generate READ_REG_GEN;
TIE_DBUS_GENERATE : if C_DW > C_GPIO_WIDTH generate
GPIO_DBus_i(0 to C_DW-C_GPIO_WIDTH-1) <= (others => '0');
end generate TIE_DBUS_GENERATE;
READ_REG2_GEN : for i in 0 to C_GPIO2_WIDTH-1 generate
--------------------------------------------------------------------------
-- GPIO2_DBUS_I_PROCESS
--------------------------------------------------------------------------
-- This process generates the GPIO CHANNEL2 DATA BUS
--------------------------------------------------------------------------
GPIO2_DBUS_I_PROC : process(Clk)
begin
if Clk'event and Clk = '1' then
if Read_Reg_Rst = '1' then
GPIO2_DBus_i(i-C_GPIO2_WIDTH+C_DW) <= '0';
else
GPIO2_DBus_i(i-C_GPIO2_WIDTH+C_DW) <= Read_Reg2_In(i);
end if;
end if;
end process;
end generate READ_REG2_GEN;
TIE_DBUS2_GENERATE : if C_DW > C_GPIO2_WIDTH generate
GPIO2_DBus_i(0 to C_DW-C_GPIO2_WIDTH-1) <= (others => '0');
end generate TIE_DBUS2_GENERATE;
---------------------------------------------------------------------------
-- GPIO_DBUS_PROCESS
---------------------------------------------------------------------------
-- This process generates the GPIO DATA BUS from the GPIO_DBUS_I and
-- GPIO2_DBUS_I based on which channel is selected
---------------------------------------------------------------------------
GPIO_DBus <= GPIO_DBus_i when (((gpio_Data_Select(0) = '1') or
(gpio_OE_Select(0) = '1')) and (RNW_Reg = '1'))
else GPIO2_DBus_i;
-----------------------------------------------------------------------------
-- DUAL_REG_SELECT_PROCESS
-----------------------------------------------------------------------------
-- GPIO REGISTER selection decoder for Dual channel configuration
-----------------------------------------------------------------------------
--DUAL_REG_SELECT_PROCESS : process (GPIO_Select, ABus_Reg) is
DUAL_REG_SELECT_PROCESS : process (gpio_reg_en, ABus_Reg) is
variable ABus_reg_select : std_logic_vector(0 to 1);
begin
ABus_reg_select := ABus_Reg(5 to 6);
gpio_Data_Select <= (others => '0');
gpio_OE_Select <= (others => '0');
--if GPIO_Select = '1' then
if gpio_reg_en = '1' then
-- case ABus_Reg(28 to 29) is -- bit A28,A29 for dual
case ABus_reg_select is -- bit A28,A29 for dual
when "00" => gpio_Data_Select(0) <= '1';
when "01" => gpio_OE_Select(0) <= '1';
when "10" => gpio_Data_Select(1) <= '1';
when "11" => gpio_OE_Select(1) <= '1';
-- coverage off
when others => null;
-- coverage on
end case;
end if;
end process DUAL_REG_SELECT_PROCESS;
---------------------------------------------------------------------------
-- GPIO_INDATA_BIRDIR_PROCESS
---------------------------------------------------------------------------
-- Reading of channel 1 data from Bidirectional GPIO port
-- to GPIO_DATA REGISTER
---------------------------------------------------------------------------
INPUT_DOUBLE_REGS4 : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 0,
C_VECTOR_WIDTH => C_GPIO_WIDTH,
C_MTBF_STAGES => 4
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => '0',
prmry_vect_in => GPIO_IO_I,
scndry_aclk => Clk,
scndry_resetn => '0',
scndry_out => open,
scndry_vect_out => gpio_io_i_d2
);
GPIO_INDATA_BIRDIR_PROCESS : process(Clk) is
begin
if Clk = '1' and Clk'EVENT then
-- gpio_io_i_d1 <= GPIO_IO_I;
-- gpio_io_i_d2 <= gpio_io_i_d1;
gpio_Data_In <= gpio_io_i_d2;
end if;
end process GPIO_INDATA_BIRDIR_PROCESS;
INPUT_DOUBLE_REGS5 : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 0,
C_VECTOR_WIDTH => C_GPIO2_WIDTH,
C_MTBF_STAGES => 4
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => '0',
prmry_vect_in => GPIO2_IO_I,
scndry_aclk => Clk,
scndry_resetn => '0',
scndry_out => open,
scndry_vect_out => gpio2_io_i_d2
);
---------------------------------------------------------------------------
-- GPIO2_INDATA_BIRDIR_PROCESS
---------------------------------------------------------------------------
-- Reading of channel 2 data from Bidirectional GPIO2 port
-- to GPIO2_DATA REGISTER
---------------------------------------------------------------------------
GPIO2_INDATA_BIRDIR_PROCESS : process(Clk) is
begin
if Clk = '1' and Clk'EVENT then
-- gpio2_io_i_d1 <= GPIO2_IO_I;
-- gpio2_io_i_d2 <= gpio2_io_i_d1;
gpio2_Data_In <= gpio2_io_i_d2;
end if;
end process GPIO2_INDATA_BIRDIR_PROCESS;
---------------------------------------------------------------------------
-- READ_MUX_PROCESS_0_0
---------------------------------------------------------------------------
-- Selects among Channel 1 GPIO_DATA ,GPIO_TRI and Channel 2 GPIO2_DATA
-- GPIO2_TRI REGISTERS for reading
---------------------------------------------------------------------------
READ_MUX_PROCESS_0_0 : process (gpio2_Data_In, gpio2_OE, gpio_Data_In,
gpio_Data_Select, gpio_OE,
gpio_OE_Select) is
begin
Read_Reg_In <= (others => '0');
Read_Reg2_In <= (others => '0');
if gpio_Data_Select(0) = '1' then
Read_Reg_In <= gpio_Data_In;
elsif gpio_OE_Select(0) = '1' then
Read_Reg_In <= gpio_OE;
elsif gpio_Data_Select(1) = '1' then
Read_Reg2_In <= gpio2_Data_In;
elsif gpio_OE_Select(1) = '1' then
Read_Reg2_In <= gpio2_OE;
end if;
end process READ_MUX_PROCESS_0_0;
---------------------------------------------------------------------------
-- GPIO_OUTDATA_PROCESS_0_0
---------------------------------------------------------------------------
-- Writing to Channel 1 GPIO_DATA REGISTER
---------------------------------------------------------------------------
GPIO_OUTDATA_PROCESS_0_0 : process(Clk) is
begin
if Clk = '1' and Clk'EVENT then
if (Rst = '1') then
gpio_Data_Out <= dout_default_i;
elsif gpio_Data_Select(0) = '1' and RNW_Reg = '0' then
for i in 0 to C_GPIO_WIDTH-1 loop
gpio_Data_Out(i) <= DBus_Reg(i);
end loop;
end if;
end if;
end process GPIO_OUTDATA_PROCESS_0_0;
---------------------------------------------------------------------------
-- GPIO_OE_PROCESS_0_0
---------------------------------------------------------------------------
-- Writing to Channel 1 GPIO_TRI Control REGISTER
---------------------------------------------------------------------------
GPIO_OE_PROCESS : process(Clk) is
begin
if Clk = '1' and Clk'EVENT then
if (Rst = '1') then
gpio_OE <= tri_default_i;
elsif gpio_OE_Select(0) = '1' and RNW_Reg = '0' then
for i in 0 to C_GPIO_WIDTH-1 loop
gpio_OE(i) <= DBus_Reg(i);
-- end if;
end loop;
end if;
end if;
end process GPIO_OE_PROCESS;
---------------------------------------------------------------------------
-- GPIO2_OUTDATA_PROCESS_0_0
---------------------------------------------------------------------------
-- Writing to Channel 2 GPIO2_DATA REGISTER
---------------------------------------------------------------------------
GPIO2_OUTDATA_PROCESS_0_0 : process(Clk) is
begin
if Clk = '1' and Clk'EVENT then
if (Rst = '1') then
gpio2_Data_Out <= dout2_default_i;
elsif gpio_Data_Select(1) = '1' and RNW_Reg = '0' then
for i in 0 to C_GPIO2_WIDTH-1 loop
gpio2_Data_Out(i) <= DBus_Reg(i);
-- end if;
end loop;
end if;
end if;
end process GPIO2_OUTDATA_PROCESS_0_0;
---------------------------------------------------------------------------
-- GPIO2_OE_PROCESS_0_0
---------------------------------------------------------------------------
-- Writing to Channel 2 GPIO2_TRI Control REGISTER
---------------------------------------------------------------------------
GPIO2_OE_PROCESS_0_0 : process(Clk) is
begin
if Clk = '1' and Clk'EVENT then
if (Rst = '1') then
gpio2_OE <= tri2_default_i;
elsif gpio_OE_Select(1) = '1' and RNW_Reg = '0' then
for i in 0 to C_GPIO2_WIDTH-1 loop
gpio2_OE(i) <= DBus_Reg(i);
end loop;
end if;
end if;
end process GPIO2_OE_PROCESS_0_0;
GPIO_IO_O <= gpio_Data_Out;
GPIO_IO_T <= gpio_OE;
GPIO2_IO_O <= gpio2_Data_Out;
GPIO2_IO_T <= gpio2_OE;
---------------------------------------------------------------------------
-- INTERRUPT IS PRESENT
---------------------------------------------------------------------------
gen_interrupt_dual : if (C_INTERRUPT_PRESENT = 1) generate
gpio_data_in_xor <= gpio_Data_In xor gpio_io_i_d2;
gpio2_data_in_xor <= gpio2_Data_In xor gpio2_io_i_d2;
-------------------------------------------------------------------------
-- An interrupt conditon exists if there is a change any bit.
-------------------------------------------------------------------------
or_ints(0) <= or_reduce(gpio_data_in_xor_reg);
or_ints2(0) <= or_reduce(gpio2_data_in_xor_reg);
-------------------------------------------------------------------------
-- Registering Interrupt condition
-------------------------------------------------------------------------
REGISTER_XORs_INTRs : process (Clk) is
begin
if (Clk'EVENT and Clk = '1') then
if (Rst = '1') then
gpio_data_in_xor_reg <= reset_zeros;
gpio2_data_in_xor_reg <= reset2_zeros;
GPIO_intr <= '0';
GPIO2_intr <= '0';
else
gpio_data_in_xor_reg <= gpio_data_in_xor;
gpio2_data_in_xor_reg <= gpio2_data_in_xor;
GPIO_intr <= or_ints(0);
GPIO2_intr <= or_ints2(0);
end if;
end if;
end process REGISTER_XORs_INTRs;
end generate gen_interrupt_dual;
end generate Dual;
end architecture IMP;
| gpl-3.0 |
mistryalok/Zedboard | learning/training/MSD/s05/project_1/project_1.srcs/sources_1/ipshared/xilinx.com/axi_cdma_v4_1/25515467/hdl/src/vhdl/axi_cdma.vhd | 1 | 38764 | -------------------------------------------------------------------------------
-- axi_cdma
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_cdma.vhd
-- Description: This entity is the top level entity for the AXI CDMA core.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library axi_cdma_v4_1;
use axi_cdma_v4_1.axi_cdma_pkg.all;
use axi_cdma_v4_1.axi_cdma_simple_wrap;
use axi_cdma_v4_1.axi_cdma_sg_wrap;
-------------------------------------------------------------------------------
entity axi_cdma is
generic(
-----------------------------------------------------------------------
-- AXI Lite Register Interface Parameters
-----------------------------------------------------------------------
C_S_AXI_LITE_ADDR_WIDTH : integer range 2 to 32 := 6;
-- Address width of the AXI Lite Interface (bits)
C_S_AXI_LITE_DATA_WIDTH : integer range 32 to 32 := 32;
-- Data width of the AXI Lite Interface (bits)
C_AXI_LITE_IS_ASYNC : Integer range 0 to 1 := 0;
-- Specifies if the AXI Lite Register interface needs to
-- be asynchronous to the CDMA data transport path clocking
-- 0 = s_axi_lite_aclk is the same as m_axi_aclk
-- 1 = s_axi_lite_aclk is asynchronous to the m_axi_aclk
-----------------------------------------------------------------------
-- DataMover Parameters
-----------------------------------------------------------------------
C_M_AXI_ADDR_WIDTH : integer range 32 to 32 := 32;
-- DataMover Master AXI Memory Map Address Width (bits)
C_M_AXI_DATA_WIDTH : integer range 32 to 1024 := 32;
-- DataMover Master AXI Memory Map Data Width (bits)
C_M_AXI_MAX_BURST_LEN : integer range 2 to 256 := 16;
-- DataMover Maximum burst length to use for AXI MMAP requests
-- Allowed values are 16, 32, 64, 128, and 256 (data beats)
C_INCLUDE_DRE : integer range 0 to 1 := 0;
-- Include or exclude DataMover Data Realignment (DRE)
-- NOTE: DRE is only available for 32 and 64 bit data widths
-- 0 = Exclude DRE
-- 1 = Include DRE
C_USE_DATAMOVER_LITE : integer range 0 to 1 := 0;
-- Enable DataMover Lite mode
-- NOTE: Data widths limited to 32 and 64 bits, max burst
-- limited to 16, 32, and 64 data beats, no DRE, 4K address
-- guarding must be done by SW programmer.
-- 0 = Normal DataMover mode
-- 1 = Lite dataMover mode
C_READ_ADDR_PIPE_DEPTH : Integer range 1 to 30 := 4;
-- This parameter specifies the depth of the DataMover
-- read address pipelining queues for the Main data transport
-- channels. The effective address pipelining on the AXI4 Read
-- Address Channel will be the value assigned plus 2.
C_WRITE_ADDR_PIPE_DEPTH : Integer range 1 to 30 := 4;
-- This parameter specifies the depth of the DataMover
-- write address pipelining queues for the Main data transport
-- channel. The effective address pipelining on the AXI4 Write
-- Address Channel will be the value assigned plus 2.
-----------------------------------------------------------------------
-- Store and Forward Parameters
-----------------------------------------------------------------------
C_INCLUDE_SF : integer range 0 to 1 := 1;
-- 0 = Omit Store and Forward functionality
-- 1 = Include Store and Forward functionality
-----------------------------------------------------------------------
-- Scatter Gather Parameters
-----------------------------------------------------------------------
C_INCLUDE_SG : integer range 0 to 1 := 0;
-- 0 = Omit Scatter Gather functionality
-- 1 = Include Scatter Gather functionality
C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 32 := 32;
-- Master AXI Memory Map Address Width for Scatter Gather
-- R/W Port (bits)
C_M_AXI_SG_DATA_WIDTH : integer range 32 to 32 := 32;
-- Master AXI Memory Map Data Width for Scatter Gather
-- R/W Port (bits)
C_DLYTMR_RESOLUTION : integer range 1 to 100000 := 125;
-- Interrupt Delay Timer resolution in clock ticks of axi_clk
-----------------------------------------------------------------------
-- Target FPGA Family Parameter
-----------------------------------------------------------------------
C_FAMILY : string := "virtex7";
-- Target FPGA Device Family
C_INSTANCE : string := "axi_cdma"
);
port (
-----------------------------------------------------------------------
-- Primary Clock
-----------------------------------------------------------------------
m_axi_aclk : in std_logic ;-- AXI4
-----------------------------------------------------------------------
-- Primary Reset Input (active low)
-----------------------------------------------------------------------
-- m_axi_aresetn : in std_logic ;-- AXI4
-----------------------------------------------------------------------
-- AXI Lite clock
-----------------------------------------------------------------------
s_axi_lite_aclk : in std_logic ;-- AXI4-Lite
-----------------------------------------------------------------------
-- AXI Lite reset
-----------------------------------------------------------------------
s_axi_lite_aresetn : in std_logic ;-- AXI4-Lite
-----------------------------------------------------------------------
-- Interrupt output
-----------------------------------------------------------------------
cdma_introut : out std_logic ;-- Interupt Out
---------------------------------------------------------------------------------
-- AXI4-Lite Register Access Interface
---------------------------------------------------------------------------------
-- AXI Lite Write Address Channel -- AXI4-Lite
s_axi_lite_awready : out std_logic ;-- AXI4-Lite
s_axi_lite_awvalid : in std_logic ;-- AXI4-Lite
s_axi_lite_awaddr : in std_logic_vector -- AXI4-Lite
(5 downto 0);-- AXI4-Lite
-- s_axi_lite_awaddr : in std_logic_vector -- AXI4-Lite
-- (C_S_AXI_LITE_ADDR_WIDTH-1 downto 0);-- AXI4-Lite
-- AXI4-Lite
-- AXI Lite Write Data Channel -- AXI4-Lite
s_axi_lite_wready : out std_logic ;-- AXI4-Lite
s_axi_lite_wvalid : in std_logic ;-- AXI4-Lite
s_axi_lite_wdata : in std_logic_vector -- AXI4-Lite
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);-- AXI4-Lite
-- AXI4-Lite
-- AXI Lite Write Response Channel -- AXI4-Lite
s_axi_lite_bready : in std_logic ;-- AXI4-Lite
s_axi_lite_bvalid : out std_logic ;-- AXI4-Lite
s_axi_lite_bresp : out std_logic_vector(1 downto 0) ;-- AXI4-Lite
-- AXI4-Lite
-- AXI Lite Read Address Channel -- AXI4-Lite
s_axi_lite_arready : out std_logic ;-- AXI4-Lite
s_axi_lite_arvalid : in std_logic ;-- AXI4-Lite
s_axi_lite_araddr : in std_logic_vector -- AXI4-Lite
(5 downto 0);-- AXI4-Lite
-- s_axi_lite_araddr : in std_logic_vector -- AXI4-Lite
-- (C_S_AXI_LITE_ADDR_WIDTH-1 downto 0);-- AXI4-Lite
-- AXI4-Lite
-- AXI Lite Read Data Channel -- AXI4-Lite
s_axi_lite_rready : in std_logic ;-- AXI4-Lite
s_axi_lite_rvalid : out std_logic ;-- AXI4-Lite
s_axi_lite_rdata : out std_logic_vector -- AXI4-Lite
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);-- AXI4-Lite
s_axi_lite_rresp : out std_logic_vector(1 downto 0) ;-- AXI4-Lite
----------------------------------------------------------------------------
-- AXI4 DataMover Read Channel
----------------------------------------------------------------------------
-- DataMover MMap Read Address Channel -- AXI4
m_axi_arready : in std_logic ;-- AXI4
m_axi_arvalid : out std_logic ;-- AXI4
m_axi_araddr : out std_logic_vector -- AXI4
(C_M_AXI_ADDR_WIDTH-1 downto 0) ;-- AXI4
m_axi_arlen : out std_logic_vector(7 downto 0) ;-- AXI4
m_axi_arsize : out std_logic_vector(2 downto 0) ;-- AXI4
m_axi_arburst : out std_logic_vector(1 downto 0) ;-- AXI4
m_axi_arprot : out std_logic_vector(2 downto 0) ;-- AXI4
m_axi_arcache : out std_logic_vector(3 downto 0) ;-- AXI4
-- AXI4
-- DataMover MMap Read Data Channel -- AXI4
m_axi_rready : out std_logic ;-- AXI4
m_axi_rvalid : in std_logic ;-- AXI4
m_axi_rdata : in std_logic_vector -- AXI4
(C_M_AXI_DATA_WIDTH-1 downto 0) ;-- AXI4
m_axi_rresp : in std_logic_vector(1 downto 0) ;-- AXI4
m_axi_rlast : in std_logic ;-- AXI4
-----------------------------------------------------------------------------
-- AXI4 DataMover Write Channel
-----------------------------------------------------------------------------
-- DataMover Write Address Channel -- AXI4
m_axi_awready : in std_logic ; -- AXI4
m_axi_awvalid : out std_logic ; -- AXI4
m_axi_awaddr : out std_logic_vector -- AXI4
(C_M_AXI_ADDR_WIDTH-1 downto 0) ; -- AXI4
m_axi_awlen : out std_logic_vector(7 downto 0) ; -- AXI4
m_axi_awsize : out std_logic_vector(2 downto 0) ; -- AXI4
m_axi_awburst : out std_logic_vector(1 downto 0) ; -- AXI4
m_axi_awprot : out std_logic_vector(2 downto 0) ; -- AXI4
m_axi_awcache : out std_logic_vector(3 downto 0) ; -- AXI4
-- AXI4
-- DataMover Write Data Channel -- AXI4
m_axi_wready : in std_logic ; -- AXI4
m_axi_wvalid : out std_logic ; -- AXI4
m_axi_wdata : out std_logic_vector -- AXI4
(C_M_AXI_DATA_WIDTH-1 downto 0) ; -- AXI4
m_axi_wstrb : out std_logic_vector -- AXI4
((C_M_AXI_DATA_WIDTH/8)-1 downto 0);-- AXI4
m_axi_wlast : out std_logic ; -- AXI4
-- AXI4
-- DataMover Write Response Channel -- AXI4
m_axi_bready : out std_logic ; -- AXI4
m_axi_bvalid : in std_logic ; -- AXI4
m_axi_bresp : in std_logic_vector(1 downto 0) ; -- AXI4
----------------------------------------------------------------------------
-- AXI4 Scatter Gather Interface
----------------------------------------------------------------------------
-- Scatter Gather Write Address Channel -- AXI4
m_axi_sg_awready : in std_logic := '0' ;-- AXI4
m_axi_sg_awvalid : out std_logic ;-- AXI4
m_axi_sg_awaddr : out std_logic_vector -- AXI4
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ;-- AXI4
m_axi_sg_awlen : out std_logic_vector(7 downto 0) ;-- AXI4
m_axi_sg_awsize : out std_logic_vector(2 downto 0) ;-- AXI4
m_axi_sg_awburst : out std_logic_vector(1 downto 0) ;-- AXI4
m_axi_sg_awprot : out std_logic_vector(2 downto 0) ;-- AXI4
m_axi_sg_awcache : out std_logic_vector(3 downto 0) ;-- AXI4
-- AXI4
-- Scatter Gather Write Data Channel -- AXI4
m_axi_sg_wready : in std_logic := '0' ;-- AXI4
m_axi_sg_wvalid : out std_logic ;-- AXI4
m_axi_sg_wdata : out std_logic_vector -- AXI4
(C_M_AXI_SG_DATA_WIDTH-1 downto 0);-- AXI4
m_axi_sg_wstrb : out std_logic_vector -- AXI4
((C_M_AXI_SG_DATA_WIDTH/8)-1 downto 0);-- AXI4
m_axi_sg_wlast : out std_logic ;-- AXI4
-- AXI4
-- Scatter Gather Write Response Channel -- AXI4
m_axi_sg_bready : out std_logic ;-- AXI4
m_axi_sg_bvalid : in std_logic := '0' ;-- AXI4
m_axi_sg_bresp : in std_logic_vector(1 downto 0) := (others => '0') ;-- AXI4
-- AXI4
-- Scatter Gather Read Address Channel -- AXI4
m_axi_sg_arready : in std_logic := '0' ;-- AXI4
m_axi_sg_arvalid : out std_logic ;-- AXI4
m_axi_sg_araddr : out std_logic_vector -- AXI4
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ;-- AXI4
m_axi_sg_arlen : out std_logic_vector(7 downto 0) ;-- AXI4
m_axi_sg_arsize : out std_logic_vector(2 downto 0) ;-- AXI4
m_axi_sg_arburst : out std_logic_vector(1 downto 0) ;-- AXI4
m_axi_sg_arprot : out std_logic_vector(2 downto 0) ;-- AXI4
m_axi_sg_arcache : out std_logic_vector(3 downto 0) ;-- AXI4
-- AXI4
-- Scatter Gather Read Data Channel -- AXI4
m_axi_sg_rready : out std_logic ;-- AXI4
m_axi_sg_rvalid : in std_logic := '0' ;-- AXI4
m_axi_sg_rdata : in std_logic_vector -- AXI4
(C_M_AXI_SG_DATA_WIDTH-1 downto 0) := (others => '0') ;-- AXI4
m_axi_sg_rresp : in std_logic_vector(1 downto 0) := (others => '0') ;-- AXI4
m_axi_sg_rlast : in std_logic := '0' ;-- AXI4
-----------------------------------------------------------------------
-- Test Support for Xilinx internal use
-----------------------------------------------------------------------
cdma_tvect_out : Out std_logic_vector(31 downto 0)
);
-----------------------------------------------------------------
-- Start of PSFUtil MPD attributes
-----------------------------------------------------------------
--attribute IP_GROUP : string;
--attribute IP_GROUP of axi_cdma : entity is "LOGICORE";
--attribute IPTYPE : string;
--attribute IPTYPE of axi_cdma : entity is "PERIPHERAL";
--attribute RUN_NGCBUILD : string;
--attribute RUN_NGCBUILD of axi_cdma : entity is "TRUE";
-----------------------------------------------------------------
-- End of PSFUtil MPD attributes
-----------------------------------------------------------------
end axi_cdma;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_cdma is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_max
--
-- Function Description:
-- Returns the greater of two integers.
--
-------------------------------------------------------------------
function funct_get_max (value_in_1 : integer;
value_in_2 : integer)
return integer is
Variable max_value : Integer := 0;
begin
If (value_in_1 > value_in_2) Then
max_value := value_in_1;
else
max_value := value_in_2;
End if;
Return (max_value);
end function funct_get_max;
-------------------------------------------------------------------
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_rnd2pwr_of_2
--
-- Function Description:
-- Rounds the input value up to the nearest power of 2 between
-- 128 and 8192.
--
-------------------------------------------------------------------
function funct_rnd2pwr_of_2 (input_value : integer) return integer is
Variable temp_pwr2 : Integer := 128;
begin
if (input_value <= 128) then
temp_pwr2 := 128;
elsif (input_value <= 256) then
temp_pwr2 := 256;
elsif (input_value <= 512) then
temp_pwr2 := 512;
elsif (input_value <= 1024) then
temp_pwr2 := 1024;
elsif (input_value <= 2048) then
temp_pwr2 := 2048;
elsif (input_value <= 4096) then
temp_pwr2 := 4096;
else
temp_pwr2 := 8192;
end if;
Return (temp_pwr2);
end function funct_rnd2pwr_of_2;
-------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
Constant SOFT_RST_TIME_CLKS : integer := 8;
-- Specifies the time of the soft reset assertion in
-- m_axi_aclk clock periods.
-- Calculates the minimum needed depth of the CDMA Store and Forward FIFO
Constant PIPEDEPTH_BURST_LEN_PROD : integer :=
(funct_get_max(C_READ_ADDR_PIPE_DEPTH, C_WRITE_ADDR_PIPE_DEPTH)+2)
* C_M_AXI_MAX_BURST_LEN;
-- Assigns the depth of the CDMA Store and Forward FIFO to the nearest
-- power of 2
Constant SF_FIFO_DEPTH : integer range 128 to 8192 :=
funct_rnd2pwr_of_2(PIPEDEPTH_BURST_LEN_PROD);
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
-- No signals Declared
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
signal m_axi_aresetn : std_logic;
begin
m_axi_aresetn <= '1';
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_SIMPLE_MODE
--
-- If Generate Description:
-- This IfGen Implements the CDMA with Simple Mode
--
--
------------------------------------------------------------
GEN_SIMPLE_MODE : if (C_INCLUDE_SG = 0) generate
begin
-----------------------------------------------------------
-- Housekeep the Scatter Gather output signals that are not
-- used in Simple DMA mode.
-----------------------------------------------------------
-- Scatter Gather Write Address Channel
m_axi_sg_awvalid <= '0' ;
m_axi_sg_awaddr <= (others => '0');
m_axi_sg_awlen <= (others => '0');
m_axi_sg_awsize <= (others => '0');
m_axi_sg_awburst <= (others => '0');
m_axi_sg_awprot <= (others => '0');
m_axi_sg_awcache <= (others => '0');
-- Scatter Gather Write Data Channel
m_axi_sg_wvalid <= '0';
m_axi_sg_wdata <= (others => '0');
m_axi_sg_wstrb <= (others => '0');
m_axi_sg_wlast <= '0' ;
-- Scatter Gather Write Response Channel
m_axi_sg_bready <= '0' ;
-- Scatter Gather Read Address Channel
m_axi_sg_arvalid <= '0' ;
m_axi_sg_araddr <= (others => '0');
m_axi_sg_arlen <= (others => '0');
m_axi_sg_arsize <= (others => '0');
m_axi_sg_arburst <= (others => '0');
m_axi_sg_arprot <= (others => '0');
m_axi_sg_arcache <= (others => '0');
-- Memory Map to Stream Scatter Gather Read Data Channel
m_axi_sg_rready <= '0' ;
------------------------------------------------------------
-- Instance: I_SIMPLE_MODE_WRAP
--
-- Description:
-- Instance for the CDMA Simple Mode Wrapper
--
------------------------------------------------------------
I_SIMPLE_MODE_WRAP : entity axi_cdma_v4_1.axi_cdma_simple_wrap
generic map (
C_S_AXI_LITE_ADDR_WIDTH => C_S_AXI_LITE_ADDR_WIDTH ,
C_S_AXI_LITE_DATA_WIDTH => C_S_AXI_LITE_DATA_WIDTH ,
C_AXI_LITE_IS_ASYNC => C_AXI_LITE_IS_ASYNC ,
C_M_AXI_ADDR_WIDTH => C_M_AXI_ADDR_WIDTH ,
C_M_AXI_DATA_WIDTH => C_M_AXI_DATA_WIDTH ,
C_M_AXI_MAX_BURST_LEN => C_M_AXI_MAX_BURST_LEN ,
C_INCLUDE_DRE => C_INCLUDE_DRE ,
C_USE_DATAMOVER_LITE => C_USE_DATAMOVER_LITE ,
C_READ_ADDR_PIPE_DEPTH => C_READ_ADDR_PIPE_DEPTH ,
C_WRITE_ADDR_PIPE_DEPTH => C_WRITE_ADDR_PIPE_DEPTH ,
C_INCLUDE_SF => C_INCLUDE_SF ,
C_SF_FIFO_DEPTH => SF_FIFO_DEPTH ,
C_SOFT_RST_TIME_CLKS => SOFT_RST_TIME_CLKS ,
C_FAMILY => C_FAMILY
)
port map (
-- Primary Clock and Reset
axi_aclk => m_axi_aclk ,
axi_resetn => m_axi_aresetn ,
-- AXI Lite clock and Reset
axi_lite_aclk => s_axi_lite_aclk ,
axi_lite_resetn => s_axi_lite_aresetn ,
-- Interrupt output
cdma_introut => cdma_introut ,
-- Error Discrete output
cdma_error_out => open ,
-- AXI Lite Write Address Channel
s_axi_lite_awready => s_axi_lite_awready ,
s_axi_lite_awvalid => s_axi_lite_awvalid ,
s_axi_lite_awaddr => s_axi_lite_awaddr ,
-- AXI Lite Write Data Channel
s_axi_lite_wready => s_axi_lite_wready ,
s_axi_lite_wvalid => s_axi_lite_wvalid ,
s_axi_lite_wdata => s_axi_lite_wdata ,
-- AXI Lite Write Response Channel
s_axi_lite_bready => s_axi_lite_bready ,
s_axi_lite_bvalid => s_axi_lite_bvalid ,
s_axi_lite_bresp => s_axi_lite_bresp ,
-- AXI Lite Read Address Channel
s_axi_lite_arready => s_axi_lite_arready ,
s_axi_lite_arvalid => s_axi_lite_arvalid ,
s_axi_lite_araddr => s_axi_lite_araddr ,
-- AXI Lite Read Data Channel
s_axi_lite_rready => s_axi_lite_rready ,
s_axi_lite_rvalid => s_axi_lite_rvalid ,
s_axi_lite_rdata => s_axi_lite_rdata ,
s_axi_lite_rresp => s_axi_lite_rresp ,
-- DataMover MMap Read Address Channel
m_axi_arready => m_axi_arready ,
m_axi_arvalid => m_axi_arvalid ,
m_axi_araddr => m_axi_araddr ,
m_axi_arlen => m_axi_arlen ,
m_axi_arsize => m_axi_arsize ,
m_axi_arburst => m_axi_arburst ,
m_axi_arprot => m_axi_arprot ,
m_axi_arcache => m_axi_arcache ,
-- DataMover MMap Read Data Channel
m_axi_rready => m_axi_rready ,
m_axi_rvalid => m_axi_rvalid ,
m_axi_rdata => m_axi_rdata ,
m_axi_rresp => m_axi_rresp ,
m_axi_rlast => m_axi_rlast ,
-- DataMover Write Address Channel
m_axi_awready => m_axi_awready ,
m_axi_awvalid => m_axi_awvalid ,
m_axi_awaddr => m_axi_awaddr ,
m_axi_awlen => m_axi_awlen ,
m_axi_awsize => m_axi_awsize ,
m_axi_awburst => m_axi_awburst ,
m_axi_awprot => m_axi_awprot ,
m_axi_awcache => m_axi_awcache ,
-- DataMover Write Data Channel
m_axi_wready => m_axi_wready ,
m_axi_wvalid => m_axi_wvalid ,
m_axi_wdata => m_axi_wdata ,
m_axi_wstrb => m_axi_wstrb ,
m_axi_wlast => m_axi_wlast ,
-- DataMover Write Response Channel
m_axi_bready => m_axi_bready ,
m_axi_bvalid => m_axi_bvalid ,
m_axi_bresp => m_axi_bresp ,
-- Debug test vector (Xilinx use only)
axi_cdma_tstvec => cdma_tvect_out
);
end generate GEN_SIMPLE_MODE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_SG_MODE
--
-- If Generate Description:
-- This IfGen Implements the CDMA with Scatter Gather Mode
--
--
------------------------------------------------------------
GEN_SG_MODE : if (C_INCLUDE_SG = 1) generate
begin
------------------------------------------------------------
-- Instance: I_SG_MODE_WRAP
--
-- Description:
-- Instance for the CDMA Scatter Gather Mode Wrapper
--
------------------------------------------------------------
I_SG_MODE_WRAP : entity axi_cdma_v4_1.axi_cdma_sg_wrap
generic map (
C_S_AXI_LITE_ADDR_WIDTH => C_S_AXI_LITE_ADDR_WIDTH ,
C_S_AXI_LITE_DATA_WIDTH => C_S_AXI_LITE_DATA_WIDTH ,
C_AXI_LITE_IS_ASYNC => C_AXI_LITE_IS_ASYNC ,
C_M_AXI_ADDR_WIDTH => C_M_AXI_ADDR_WIDTH ,
C_M_AXI_DATA_WIDTH => C_M_AXI_DATA_WIDTH ,
C_M_AXI_MAX_BURST_LEN => C_M_AXI_MAX_BURST_LEN ,
C_INCLUDE_DRE => C_INCLUDE_DRE ,
C_READ_ADDR_PIPE_DEPTH => C_READ_ADDR_PIPE_DEPTH ,
C_WRITE_ADDR_PIPE_DEPTH => C_WRITE_ADDR_PIPE_DEPTH ,
C_INCLUDE_SF => C_INCLUDE_SF ,
C_SF_FIFO_DEPTH => SF_FIFO_DEPTH ,
C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH ,
C_M_AXI_SG_DATA_WIDTH => C_M_AXI_SG_DATA_WIDTH ,
C_DLYTMR_RESOLUTION => C_DLYTMR_RESOLUTION ,
C_SOFT_RST_TIME_CLKS => SOFT_RST_TIME_CLKS ,
C_FAMILY => C_FAMILY
)
port map (
-- Primary Clock and Reset
axi_aclk => m_axi_aclk ,
axi_resetn => m_axi_aresetn ,
-- AXI Lite clock and Reset
axi_lite_aclk => s_axi_lite_aclk ,
axi_lite_resetn => s_axi_lite_aresetn ,
-- Interrupt output
cdma_introut => cdma_introut ,
-- Error Discrete output
cdma_error_out => open ,
-- AXI Lite Write Address Channel
s_axi_lite_awready => s_axi_lite_awready ,
s_axi_lite_awvalid => s_axi_lite_awvalid ,
s_axi_lite_awaddr => s_axi_lite_awaddr ,
-- AXI Lite Write Data Channel
s_axi_lite_wready => s_axi_lite_wready ,
s_axi_lite_wvalid => s_axi_lite_wvalid ,
s_axi_lite_wdata => s_axi_lite_wdata ,
-- AXI Lite Write Response Channel
s_axi_lite_bready => s_axi_lite_bready ,
s_axi_lite_bvalid => s_axi_lite_bvalid ,
s_axi_lite_bresp => s_axi_lite_bresp ,
-- AXI Lite Read Address Channel
s_axi_lite_arready => s_axi_lite_arready ,
s_axi_lite_arvalid => s_axi_lite_arvalid ,
s_axi_lite_araddr => s_axi_lite_araddr ,
-- AXI Lite Read Data Channel
s_axi_lite_rready => s_axi_lite_rready ,
s_axi_lite_rvalid => s_axi_lite_rvalid ,
s_axi_lite_rdata => s_axi_lite_rdata ,
s_axi_lite_rresp => s_axi_lite_rresp ,
-- DataMover MMap Read Address Channel
m_axi_arready => m_axi_arready ,
m_axi_arvalid => m_axi_arvalid ,
m_axi_araddr => m_axi_araddr ,
m_axi_arlen => m_axi_arlen ,
m_axi_arsize => m_axi_arsize ,
m_axi_arburst => m_axi_arburst ,
m_axi_arprot => m_axi_arprot ,
m_axi_arcache => m_axi_arcache ,
-- DataMover MMap Read Data Channel
m_axi_rready => m_axi_rready ,
m_axi_rvalid => m_axi_rvalid ,
m_axi_rdata => m_axi_rdata ,
m_axi_rresp => m_axi_rresp ,
m_axi_rlast => m_axi_rlast ,
-- DataMover Write Address Channel
m_axi_awready => m_axi_awready ,
m_axi_awvalid => m_axi_awvalid ,
m_axi_awaddr => m_axi_awaddr ,
m_axi_awlen => m_axi_awlen ,
m_axi_awsize => m_axi_awsize ,
m_axi_awburst => m_axi_awburst ,
m_axi_awprot => m_axi_awprot ,
m_axi_awcache => m_axi_awcache ,
-- DataMover Write Data Channel
m_axi_wready => m_axi_wready ,
m_axi_wvalid => m_axi_wvalid ,
m_axi_wdata => m_axi_wdata ,
m_axi_wstrb => m_axi_wstrb ,
m_axi_wlast => m_axi_wlast ,
-- DataMover Write Response Channel
m_axi_bready => m_axi_bready ,
m_axi_bvalid => m_axi_bvalid ,
m_axi_bresp => m_axi_bresp ,
-- Scatter Gather Write Address Channel
m_axi_sg_awready => m_axi_sg_awready ,
m_axi_sg_awvalid => m_axi_sg_awvalid ,
m_axi_sg_awaddr => m_axi_sg_awaddr ,
m_axi_sg_awlen => m_axi_sg_awlen ,
m_axi_sg_awsize => m_axi_sg_awsize ,
m_axi_sg_awburst => m_axi_sg_awburst ,
m_axi_sg_awprot => m_axi_sg_awprot ,
m_axi_sg_awcache => m_axi_sg_awcache ,
-- Scatter Gather Write Data Channel
m_axi_sg_wready => m_axi_sg_wready ,
m_axi_sg_wvalid => m_axi_sg_wvalid ,
m_axi_sg_wdata => m_axi_sg_wdata ,
m_axi_sg_wstrb => m_axi_sg_wstrb ,
m_axi_sg_wlast => m_axi_sg_wlast ,
-- Scatter Gather Write Response Channel
m_axi_sg_bready => m_axi_sg_bready ,
m_axi_sg_bvalid => m_axi_sg_bvalid ,
m_axi_sg_bresp => m_axi_sg_bresp ,
-- Scatter Gather Read Address Channel
m_axi_sg_arready => m_axi_sg_arready ,
m_axi_sg_arvalid => m_axi_sg_arvalid ,
m_axi_sg_araddr => m_axi_sg_araddr ,
m_axi_sg_arlen => m_axi_sg_arlen ,
m_axi_sg_arsize => m_axi_sg_arsize ,
m_axi_sg_arburst => m_axi_sg_arburst ,
m_axi_sg_arprot => m_axi_sg_arprot ,
m_axi_sg_arcache => m_axi_sg_arcache ,
-- Scatter Gather Read Data Channel
m_axi_sg_rready => m_axi_sg_rready ,
m_axi_sg_rvalid => m_axi_sg_rvalid ,
m_axi_sg_rdata => m_axi_sg_rdata ,
m_axi_sg_rresp => m_axi_sg_rresp ,
m_axi_sg_rlast => m_axi_sg_rlast ,
-- Debug test vector (Xilinx use only)
axi_cdma_tstvec => cdma_tvect_out
);
end generate GEN_SG_MODE;
end implementation;
| gpl-3.0 |
mistryalok/Zedboard | learning/training/MSD/s05/project_1/project_1.srcs/sources_1/ipshared/xilinx.com/axi_cdma_v4_1/25515467/hdl/src/vhdl/axi_cdma_pkg.vhd | 1 | 12302 | -------------------------------------------------------------------------------
-- axi_cdma_pkg
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_cdma_pkg.vhd
-- Description: This package contains various constants and functions for
-- AXI DMA operations.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library lib_pkg_v1_0;
use lib_pkg_v1_0.lib_pkg.clog2;
package axi_cdma_pkg is
-------------------------------------------------------------------------------
-- Function declarations
-------------------------------------------------------------------------------
-- Find minimum required btt width
function required_btt_width1 (dwidth,
burst_size,
btt_width : integer)
return integer;
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- AXI Responce Values
-------------------------------------------------------------------------------
constant OKAY_RESP : std_logic_vector(1 downto 0) := "00";
constant EXOKAY_RESP : std_logic_vector(1 downto 0) := "01";
constant SLVERR_RESP : std_logic_vector(1 downto 0) := "10";
constant DECERR_RESP : std_logic_vector(1 downto 0) := "11";
-------------------------------------------------------------------------------
-- Misc Constants
-------------------------------------------------------------------------------
constant NUM_REG_TOTAL : integer := 18;
constant NUM_REG_PER_CHANNEL : integer := 6;
constant REG_MSB_ADDR_BIT : integer := clog2(NUM_REG_TOTAL)-1;
--constant CMD_BASE_WIDTH : integer := 40;
constant CMD_BASE_WIDTH : integer := 104;
constant BUFFER_LENGTH_WIDTH : integer := 23;
-- Constants Used in Desc Updates
constant DESC_STS_TYPE : std_logic := '1';
constant DESC_DATA_TYPE : std_logic := '0';
constant DESC_LAST : std_logic := '1';
constant DESC_NOT_LAST : std_logic := '0';
-- Interrupt Coalescing
constant ZERO_THRESHOLD : std_logic_vector(7 downto 0) := (others => '0');
constant ONE_THRESHOLD : std_logic_vector(7 downto 0) := "00000001";
constant ZERO_DELAY : std_logic_vector(7 downto 0) := (others => '0');
constant MTBF_STAGES : integer := 4;
-------------------------------------------------------------------------------
-- Register Bit Constants
-------------------------------------------------------------------------------
-- DMACR
constant DMACR_RESERVED0_BIT : integer := 0;
constant DMACR_TAILPEN_BIT : integer := 1;
constant DMACR_RESET_BIT : integer := 2;
constant DMACR_SGMODE_BIT : integer := 3;
constant DMACR_KHREAD_BIT : integer := 4;
constant DMACR_KHWRITE_BIT : integer := 5;
--constant DMACR_RESERVED4_BIT : integer := 4;
--constant DMACR_RESERVED5_BIT : integer := 5;
constant DMACR_CYCLIC_BIT : integer := 6;
constant DMACR_RESERVED7_BIT : integer := 7;
constant DMACR_RESERVED8_BIT : integer := 8;
constant DMACR_RESERVED9_BIT : integer := 9;
constant DMACR_RESERVED10_BIT : integer := 10;
constant DMACR_RESERVED11_BIT : integer := 11;
constant DMACR_IOC_IRQEN_BIT : integer := 12;
constant DMACR_DLY_IRQEN_BIT : integer := 13;
constant DMACR_ERR_IRQEN_BIT : integer := 14;
constant DMACR_RESERVED15_BIT : integer := 15;
constant DMACR_IRQTHRESH_LSB_BIT : integer := 16;
constant DMACR_IRQTHRESH_MSB_BIT : integer := 23;
constant DMACR_IRQDELAY_LSB_BIT : integer := 24;
constant DMACR_IRQDELAY_MSB_BIT : integer := 31;
-- DMASR
constant DMASR_HALTED_BIT : integer := 0;
constant DMASR_IDLE_BIT : integer := 1;
constant DMASR_CMPLT_BIT : integer := 2;
constant DMASR_ERROR_BIT : integer := 3;
constant DMASR_DMAINTERR_BIT : integer := 4;
constant DMASR_DMASLVERR_BIT : integer := 5;
constant DMASR_DMADECERR_BIT : integer := 6;
constant DMASR_RESERVED7_BIT : integer := 7;
constant DMASR_SGINTERR_BIT : integer := 8;
constant DMASR_SGSLVERR_BIT : integer := 9;
constant DMASR_SGDECERR_BIT : integer := 10;
constant DMASR_RESERVED11_BIT : integer := 11;
constant DMASR_IOCIRQ_BIT : integer := 12;
constant DMASR_DLYIRQ_BIT : integer := 13;
constant DMASR_ERRIRQ_BIT : integer := 14;
constant DMASR_RESERVED15_BIT : integer := 15;
constant DMASR_IRQTHRESH_LSB_BIT : integer := 16;
constant DMASR_IRQTHRESH_MSB_BIT : integer := 23;
constant DMASR_IRQDELAY_LSB_BIT : integer := 24;
constant DMASR_IRQDELAY_MSB_BIT : integer := 31;
-- CURDESC
constant CURDESC_LOWER_MSB_BIT : integer := 31;
constant CURDESC_LOWER_LSB_BIT : integer := 6;
constant CURDESC_RESERVED_BIT5 : integer := 5;
constant CURDESC_RESERVED_BIT4 : integer := 4;
constant CURDESC_RESERVED_BIT3 : integer := 3;
constant CURDESC_RESERVED_BIT2 : integer := 2;
constant CURDESC_RESERVED_BIT1 : integer := 1;
constant CURDESC_RESERVED_BIT0 : integer := 0;
-- TAILDESC
constant TAILDESC_LOWER_MSB_BIT : integer := 31;
constant TAILDESC_LOWER_LSB_BIT : integer := 6;
constant TAILDESC_RESERVED_BIT5 : integer := 5;
constant TAILDESC_RESERVED_BIT4 : integer := 4;
constant TAILDESC_RESERVED_BIT3 : integer := 3;
constant TAILDESC_RESERVED_BIT2 : integer := 2;
constant TAILDESC_RESERVED_BIT1 : integer := 1;
constant TAILDESC_RESERVED_BIT0 : integer := 0;
-- BTT
constant BTT_MSB_BIT : integer := 22;
-- DataMover Command / Status Constants
constant DATAMOVER_CMDDONE_BIT : integer := 7;
constant DATAMOVER_SLVERR_BIT : integer := 6;
constant DATAMOVER_DECERR_BIT : integer := 5;
constant DATAMOVER_INTERR_BIT : integer := 4;
constant DATAMOVER_TAGMSB_BIT : integer := 3;
constant DATAMOVER_TAGLSB_BIT : integer := 0;
-- Descriptor Control Bits
constant DESC_BLENGTH_LSB_BIT : integer := 0;
constant DESC_BLENGTH_MSB_BIT : integer := 22;
constant DESC_RSVD23_BIT : integer := 23;
constant DESC_RSVD24_BIT : integer := 24;
constant DESC_RSVD25_BIT : integer := 25;
constant DESC_EOF_BIT : integer := 26;
constant DESC_SOF_BIT : integer := 27;
constant DESC_RSVD28_BIT : integer := 28;
constant DESC_RSVD29_BIT : integer := 29;
constant DESC_RSVD30_BIT : integer := 30;
constant DESC_IOC_BIT : integer := 31;
-- Descriptor Status Bits
constant DESC_STS_CMPLTD_BIT : integer := 31;
constant DESC_STS_DECERR_BIT : integer := 30;
constant DESC_STS_SLVERR_BIT : integer := 29;
constant DESC_STS_INTERR_BIT : integer := 28;
constant DESC_STS_RXSOF_BIT : integer := 27;
constant DESC_STS_RXEOF_BIT : integer := 26;
constant DESC_STS_RSVD25_BIT : integer := 25;
constant DESC_STS_RSVD24_BIT : integer := 24;
constant DESC_STS_RSVD23_BIT : integer := 23;
constant DESC_STS_XFRDBYTS_MSB_BIT : integer := 22;
constant DESC_STS_XFRDBYTS_LSB_BIT : integer := 0;
-- DataMover Command / Status Constants
constant DATAMOVER_STS_CMDDONE_BIT : integer := 7;
constant DATAMOVER_STS_SLVERR_BIT : integer := 6;
constant DATAMOVER_STS_DECERR_BIT : integer := 5;
constant DATAMOVER_STS_INTERR_BIT : integer := 4;
constant DATAMOVER_STS_TAGMSB_BIT : integer := 3;
constant DATAMOVER_STS_TAGLSB_BIT : integer := 0;
constant DATAMOVER_STS_TAGEOF_BIT : integer := 1;
constant DATAMOVER_STS_TLAST_BIT : integer := 31;
constant DATAMOVER_CMD_BTTLSB_BIT : integer := 0;
constant DATAMOVER_CMD_BTTMSB_BIT : integer := 22;
constant DATAMOVER_CMD_TYPE_BIT : integer := 23;
constant DATAMOVER_CMD_DSALSB_BIT : integer := 24;
constant DATAMOVER_CMD_DSAMSB_BIT : integer := 29;
constant DATAMOVER_CMD_EOF_BIT : integer := 30;
constant DATAMOVER_CMD_DRR_BIT : integer := 31;
constant DATAMOVER_CMD_ADDRLSB_BIT : integer := 32;
-- Note: Bit offset require adding ADDR WIDTH to get to actual bit index
constant DATAMOVER_CMD_ADDRMSB_BOFST: integer := 31;
constant DATAMOVER_CMD_TAGLSB_BOFST : integer := 32;
constant DATAMOVER_CMD_TAGMSB_BOFST : integer := 35;
constant DATAMOVER_CMD_RSVLSB_BOFST : integer := 36;
constant DATAMOVER_CMD_RSVMSB_BOFST : integer := 39;
end axi_cdma_pkg;
-------------------------------------------------------------------------------
-- PACKAGE BODY
-------------------------------------------------------------------------------
package body axi_cdma_pkg is
-------------------------------------------------------------------------------
-- Function to determine minimum bits required for BTT_SIZE field
-------------------------------------------------------------------------------
function required_btt_width1 ( dwidth,
burst_size,
btt_width : integer)
return integer is
variable min_width : integer;
begin
min_width := clog2((dwidth/8)*burst_size)+1;
if(min_width > btt_width)then
return min_width;
else
return btt_width;
end if;
end function required_btt_width1;
end package body axi_cdma_pkg;
| gpl-3.0 |
juhasch/myhdl | example/manual/rom.vhd | 13 | 663 | -- File: rom.vhd
-- Generated by MyHDL 0.8dev
-- Date: Fri Dec 21 15:02:39 2012
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;
use work.pck_myhdl_08.all;
entity rom is
port (
dout: out unsigned(7 downto 0);
addr: in unsigned(3 downto 0)
);
end entity rom;
-- ROM model
architecture MyHDL of rom is
begin
ROM_READ: process (addr) is
begin
case to_integer(addr) is
when 0 => dout <= "00010001";
when 1 => dout <= "10000110";
when 2 => dout <= "00110100";
when others => dout <= "00001001";
end case;
end process ROM_READ;
end architecture MyHDL;
| lgpl-2.1 |
bogdanvuk/sydpy | tests/test_ping_pong_cosim_pong.vhd | 1 | 331 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity pong is
port
(
din : in std_logic_vector(31 downto 0);
dout : out std_logic_vector(31 downto 0)
);
end entity pong;
architecture rtl of pong is
begin
dout <= din(23 downto 16) & din(23 downto 16) & din(7 downto 0) & din(7 downto 0);
end architecture rtl;
| lgpl-2.1 |
jmgc/myhdl-numeric | example/manual/bin2gray.vhd | 7 | 784 | -- File: bin2gray.vhd
-- Generated by MyHDL 0.8dev
-- Date: Fri Dec 21 15:02:38 2012
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;
use work.pck_myhdl_08.all;
entity bin2gray is
port (
B: in unsigned(7 downto 0);
G: out unsigned(7 downto 0)
);
end entity bin2gray;
-- Gray encoder.
--
-- B -- input intbv signal, binary encoded
-- G -- output intbv signal, gray encoded
-- width -- bit width
architecture MyHDL of bin2gray is
begin
BIN2GRAY_LOGIC: process (B) is
variable Bext: unsigned(8 downto 0);
begin
Bext := to_unsigned(0, 9);
Bext := resize(B, 9);
for i in 0 to 8-1 loop
G(i) <= (Bext((i + 1)) xor Bext(i));
end loop;
end process BIN2GRAY_LOGIC;
end architecture MyHDL;
| lgpl-2.1 |
jaruiz/light8080 | src/vhdl/rtl/mcu/mcu80_pkg.vhdl | 1 | 3231 | --------------------------------------------------------------------------------
-- mcu80_pkg.vhdl -- Support package for Light8080 MCU.
--
-- Contains functions used to initialize internal BRAM with object code.
--
-- This package will be used from the object code package where the program
-- initialized RAM constant is defined. If you use script obj2hdl it will
-- take care of this for you.
-- The package is used in entity mcu80 too, and nowhere else.
--
-- Please see the LICENSE file in the project root for license matters.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package mcu80_pkg is
-- Global signals for the TB to use in lieu of hierarchical names.
signal mon_addr : std_logic_vector(15 downto 0);
signal mon_fetch : std_logic;
signal mon_we : std_logic;
signal mon_wdata : std_logic_vector(7 downto 0);
signal mon_uart_ce : std_logic;
-- Basic array type for the declaration of initialization constants.
-- This type is meant to be used to declare a constant with the object code
-- that is to be preprogrammed in an initialized RAM.
type obj_code_t is array(integer range <>) of std_logic_vector(7 downto 0);
-- Basic array type for the definition of initialized RAMs.
type ram_t is array(integer range <>) of std_logic_vector(7 downto 0);
-- Builds BRAM initialization constant from a constant CONSTRAINED byte array
-- containing the application object code.
-- The object code is placed at the beginning of the BRAM and the rest is
-- filled with zeros.
-- CAN BE USED IN SYNTHESIZABLE CODE to compute a BRAM initialization constant
-- from a constant argument.
--
-- oC: Object code table (as generated by utility script obj2hdl for instance).
-- size: Size of the target memory.
-- Returns ram_t value size-bytes long, suitable for synth-time initialization
-- of a BRAM.
function objcode_to_bram(oC : obj_code_t; size : integer) return ram_t;
-- Compute log2(A), rounding up.
-- Use this to get the minimum width of the address bus necessary to
-- address A locations.
function log2(A : natural) return natural;
end package;
package body mcu80_pkg is
-- Builds BRAM initialization constant from a constant CONSTRAINED byte array
-- containing the application object code.
function objcode_to_bram(oC : obj_code_t; size : integer) return ram_t is
variable br : ram_t(integer range 0 to size-1);
variable i : integer;
variable obj_size : integer;
begin
-- If the object code table is longer than the array size, truncate code
if oC'length > size then
obj_size := size;
else
obj_size := oC'length;
end if;
-- Copy object code to start of BRAM...
for i in 0 to obj_size-1 loop
br(i) := oC(oC'low + i);
end loop;
-- ... and fill the rest with zeros
br(obj_size to size-1) := (others => x"00");
return br;
end function objcode_to_bram;
function log2(A : natural) return natural is
begin
for I in 1 to 30 loop -- Works for up to 32 bit integers
if(2**I >= A) then
return(I);
end if;
end loop;
return(30);
end function log2;
end package body;
| lgpl-2.1 |
jaruiz/light8080 | src/sw/hello/obj_code_pkg.vhdl | 1 | 4599 | --------------------------------------------------------------------------------
-- obj_code_pkg.vhdl -- Application object code in vhdl constant string format.
--------------------------------------------------------------------------------
-- Written by build_rom.py for project 'hello'.
--------------------------------------------------------------------------------
--
-- This source file may be used and distributed without
-- restriction provided that this copyright statement is not
-- removed from the file and that any derivative work contains
-- the original copyright notice and the associated disclaimer.
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.opencores.org/lgpl.shtml
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- Package with utility functions for handling SoC object code.
use work.mcu80_pkg.all;
package obj_code_pkg is
-- Object code initialization constant.
constant object_code : obj_code_t(0 to 248) := (
X"c3", X"60", X"00", X"00", X"00", X"00", X"00", X"00", -- 0000h : 0007h
X"c9", X"00", X"00", X"00", X"00", X"00", X"00", X"00", -- 0008h : 000fh
X"c9", X"00", X"00", X"00", X"00", X"00", X"00", X"00", -- 0010h : 0017h
X"c9", X"00", X"00", X"00", X"00", X"00", X"00", X"00", -- 0018h : 001fh
X"c9", X"00", X"00", X"00", X"00", X"00", X"00", X"00", -- 0020h : 0027h
X"c9", X"00", X"00", X"00", X"00", X"00", X"00", X"00", -- 0028h : 002fh
X"c9", X"00", X"00", X"00", X"00", X"00", X"00", X"00", -- 0030h : 0037h
X"c3", X"b0", X"00", X"00", X"00", X"00", X"00", X"00", -- 0038h : 003fh
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", -- 0040h : 0047h
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", -- 0048h : 004fh
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", -- 0050h : 0057h
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", -- 0058h : 005fh
X"31", X"5c", X"01", X"21", X"f7", X"00", X"22", X"f8", -- 0060h : 0067h
X"00", X"21", X"fc", X"00", X"22", X"fa", X"00", X"3e", -- 0068h : 006fh
X"14", X"d3", X"83", X"3e", X"58", X"d3", X"82", X"3e", -- 0070h : 0077h
X"00", X"d3", X"86", X"3e", X"08", X"d3", X"88", X"fb", -- 0078h : 007fh
X"21", X"9e", X"00", X"cd", X"e7", X"00", X"3e", X"55", -- 0080h : 0087h
X"d3", X"86", X"3e", X"04", X"d3", X"80", X"db", X"84", -- 0088h : 008fh
X"4f", X"07", X"07", X"81", X"d3", X"86", X"c3", X"8e", -- 0090h : 0097h
X"00", X"f3", X"76", X"c3", X"9b", X"00", X"0a", X"0d", -- 0098h : 009fh
X"0a", X"48", X"65", X"6c", X"6c", X"6f", X"20", X"57", -- 00a0h : 00a7h
X"6f", X"72", X"6c", X"64", X"21", X"0a", X"24", X"00", -- 00a8h : 00afh
X"e5", X"f5", X"db", X"81", X"e6", X"20", X"ca", X"c9", -- 00b0h : 00b7h
X"00", X"3e", X"20", X"d3", X"81", X"db", X"80", X"d3", -- 00b8h : 00bfh
X"86", X"2a", X"fa", X"00", X"77", X"23", X"22", X"fa", -- 00c0h : 00c7h
X"00", X"db", X"81", X"e6", X"10", X"ca", X"e3", X"00", -- 00c8h : 00cfh
X"3e", X"10", X"d3", X"81", X"2a", X"f8", X"00", X"7e", -- 00d0h : 00d7h
X"fe", X"24", X"ca", X"e3", X"00", X"23", X"22", X"f8", -- 00d8h : 00dfh
X"00", X"d3", X"80", X"f1", X"e1", X"fb", X"c9", X"7e", -- 00e0h : 00e7h
X"23", X"22", X"f8", X"00", X"fe", X"24", X"ca", X"f6", -- 00e8h : 00efh
X"00", X"d3", X"80", X"c3", X"e7", X"00", X"c9", X"24", -- 00f0h : 00f7h
X"00" -- 00f8h : 00f8h
);
end package obj_code_pkg;
| lgpl-2.1 |
jmgc/myhdl-numeric | example/manual/ram.vhd | 13 | 801 | -- File: ram.vhd
-- Generated by MyHDL 0.8dev
-- Date: Fri Dec 21 15:02:39 2012
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;
use work.pck_myhdl_08.all;
entity ram is
port (
dout: out unsigned(7 downto 0);
din: in unsigned(7 downto 0);
addr: in unsigned(6 downto 0);
we: in std_logic;
clk: in std_logic
);
end entity ram;
-- Ram model
architecture MyHDL of ram is
type t_array_mem is array(0 to 128-1) of unsigned(7 downto 0);
signal mem: t_array_mem;
begin
RAM_WRITE: process (clk) is
begin
if rising_edge(clk) then
if bool(we) then
mem(to_integer(addr)) <= din;
end if;
end if;
end process RAM_WRITE;
dout <= mem(to_integer(addr));
end architecture MyHDL;
| lgpl-2.1 |
yishinli/emc2 | src/hal/drivers/m5i20/hostmot5_src/hostmot5-8e.vhd | 1 | 25600 | library IEEE;
use IEEE.std_logic_1164.all; -- defines std_logic types
-- 8 axis version with 24 I/O bits
entity HostMot5_8 is
port
(
LRD: in STD_LOGIC;
LWR: in STD_LOGIC;
LW_R: in STD_LOGIC;
ALE: in STD_LOGIC;
ADS: in STD_LOGIC;
BLAST: in STD_LOGIC;
WAITO: in STD_LOGIC;
LOCKO: in STD_LOGIC;
CS0: in STD_LOGIC;
CS1: in STD_LOGIC;
READY: out STD_LOGIC;
INT: out STD_LOGIC;
LAD: inout STD_LOGIC_VECTOR (31 downto 0); -- data/address bus
LA: in STD_LOGIC_VECTOR (8 downto 2); -- non-muxed address bus
lBE: in STD_LOGIC_VECTOR (3 downto 0); -- byte enables
SYNCLK: in STD_LOGIC;
LCLK: in STD_LOGIC;
-- I/O signals
A: in STD_LOGIC_VECTOR (7 downto 0);
B: in STD_LOGIC_VECTOR (7 downto 0);
IDX: in STD_LOGIC_VECTOR (7 downto 0);
PWM: inout STD_LOGIC_VECTOR (7 downto 0);
ENA: out STD_LOGIC_VECTOR (7 downto 0);
DIR: inout STD_LOGIC_VECTOR (7 downto 0);
IOBITSA: inout STD_LOGIC_VECTOR (23 downto 0);
-- IOBITSB: inout STD_LOGIC_VECTOR (23 downto 0);
-- led bits
LEDS: out STD_LOGIC_VECTOR(7 downto 0)
);
end HostMot5_8; -- for 5I20 or 4I65
architecture dataflow of Hostmot5_8 is
alias BLE: STD_LOGIC is LBE(0); -- 16 bit mode
alias BHE: STD_LOGIC is LBE(3); -- 16 bit mode
alias LA1: STD_LOGIC is LBE(1); -- 8/16 bit mode
alias LA0: STD_LOGIC is LBE(0); -- 8 bit mode
-- misc global signals --
signal D: STD_LOGIC_VECTOR (31 downto 0); -- internal data bus
signal LatchedA: STD_LOGIC_VECTOR (15 downto 0);
signal LatchedLBE: STD_LOGIC_VECTOR (3 downto 0);
signal PreFastRead: STD_LOGIC;
signal FastRead: STD_LOGIC;
-- Version specific constants --
constant counters :integer := 8;
constant HMID : STD_LOGIC_VECTOR (31 downto 0) := x"AA010008"; -- MSW = rev 1, LSW = 4 axis
constant MasterClock : STD_LOGIC_VECTOR (31 downto 0) := x"01FCA055"; -- = 33.3333 MHz
-- misc global signals --
signal CardSelect: STD_LOGIC; -- card select decode
signal LEDView: STD_LOGIC_VECTOR (7 downto 0); -- index register
-- irq related signals
signal IRQSource: STD_LOGIC;
signal IRQLatch: STD_LOGIC;
signal IRQMask: STD_LOGIC;
signal MissedIRQ: STD_LOGIC;
signal StopOnMissedIRQ: STD_LOGIC;
signal ClearMissedIRQ: STD_LOGIC;
signal LatchOnInterrupt: STD_LOGIC;
-- timeout related signals
signal ReloadWDCmd: STD_LOGIC;
signal StopOnTimeout: STD_LOGIC;
signal WDTimeOut: STD_LOGIC;
-- LEDView and id reg signals
signal LoadLEDViewCmd: STD_LOGIC;
signal ReadLEDViewCmd: STD_LOGIC;
signal Enasigs :STD_LOGIC_VECTOR (counters-1 downto 0);
signal IDSel: STD_LOGIC;
signal ReadIDCmd: STD_LOGIC;
signal MCSel: STD_LOGIC;
signal ReadMCCmd: STD_LOGIC;
-- irqdiv reg signals
signal ReadIRQDivCmd: STD_LOGIC;
signal LoadIRQDivCmd: STD_LOGIC;
signal ClearIRQCmd: STD_LOGIC;
-- irq sel reg signals
signal loadGCRCmd: STD_LOGIC;
signal LoadGMRCmd: STD_LOGIC;
signal ReadGMRCmd: STD_LOGIC;
-- timeout reg signals
signal loadTimeoutCmd: STD_LOGIC;
signal ReadTimeoutCmd: STD_LOGIC;
signal ReadTimerCmd: STD_LOGIC;
-- phase accumulator signals
signal ReadPhaseCmd: STD_LOGIC;
signal LoadPhaseCmd: STD_LOGIC;
-- counter signals --
signal CounterRead: STD_LOGIC_VECTOR (counters-1 downto 0); -- read counter
signal GlobalCounterEnable: STD_LOGIC; -- enable counting
signal GlobalCountLatchcmd: STD_LOGIC; -- command to latch counter value
signal GlobalCountLatch: STD_LOGIC; -- command + irq generated latch count
signal CountLatchEdge1: STD_LOGIC;
signal CountLatchEdge2: STD_LOGIC;
signal CCRLoadCmds: STD_LOGIC_VECTOR (counters-1 downto 0); -- counter control reg loads
signal CCRReadCmds: STD_LOGIC_VECTOR (counters-1 downto 0); -- counter control reg reads
signal GlobalCounterClear: STD_LOGIC; -- clear counter
-- secondary counter signals --
signal SCounterRead: STD_LOGIC_VECTOR (counters-1 downto 0); -- read counter
signal SCCRLoadCmds: STD_LOGIC_VECTOR (counters-1 downto 0); -- counter control reg loads
signal SCCRReadCmds: STD_LOGIC_VECTOR (counters-1 downto 0); -- counter control reg reads
-- pwm generator signals --
signal RefCountBus: STD_LOGIC_VECTOR (9 downto 0);
signal LoadPWM: STD_LOGIC_VECTOR (counters-1 downto 0);
signal ReadPWM: STD_LOGIC_VECTOR (counters-1 downto 0);
signal PCRLoadCmds: STD_LOGIC_VECTOR (counters-1 downto 0);
signal PCRReadCmds: STD_LOGIC_VECTOR (counters-1 downto 0);
signal GlobalPWMEnable: STD_LOGIC;
signal GlobalClearPWM: STD_LOGIC;
signal GlobalClearPWMCmd: STD_LOGIC;
signal StopPWM: STD_LOGIC;
-- misc i/o signals
signal PortASel: STD_LOGIC;
signal DDRASel: STD_LOGIC;
signal LoadPortA: STD_LOGIC;
signal LoadDDRA: STD_LOGIC;
signal ReadDDRA: STD_LOGIC;
signal ReadPortA: STD_LOGIC;
signal PortBSel: STD_LOGIC;
signal DDRBSel: STD_LOGIC;
signal LoadPortB: STD_LOGIC;
signal LoadDDRB: STD_LOGIC;
signal ReadDDRB: STD_LOGIC;
signal ReadPortB: STD_LOGIC;
-- decodes --
signal LEDViewSel: STD_LOGIC;
signal IndexSel: STD_LOGIC;
signal GCRSel: STD_LOGIC;
signal GMRSel: STD_LOGIC;
signal CCRSel: STD_LOGIC;
signal SCCRSel: STD_LOGIC;
signal PCRSel: STD_LOGIC;
signal TimeOutSel: STD_LOGIC;
signal TimerSel: STD_LOGIC;
signal IRQDIVSel: STD_LOGIC;
signal PWMValSel: STD_LOGIC;
signal PhaseSel: STD_LOGIC;
signal CounterSel: STD_LOGIC;
signal SCounterSel: STD_LOGIC;
function OneOfEightDecode(ena : std_logic; dec : std_logic_vector(2 downto 0)) return std_logic_vector is
variable result : std_logic_vector(counters-1 downto 0);
begin
if ena = '1' then
case dec is
when "000" => result := "00000001";
when "001" => result := "00000010";
when "010" => result := "00000100";
when "011" => result := "00001000";
when "100" => result := "00010000";
when "101" => result := "00100000";
when "110" => result := "01000000";
when "111" => result := "10000000";
when others => result := "00000000";
end case;
else
result := "00000000";
end if;
return result;
end OneOfEightDecode;
function OneOfEightMux(sel: std_logic_vector (2 downto 0); input: std_logic_vector(counters-1 downto 0)) return std_logic is
variable result : std_logic;
begin
case sel is
when "000" => result := input(0);
when "001" => result := input(1);
when "010" => result := input(2);
when "011" => result := input(3);
when "100" => result := input(4);
when "101" => result := input(5);
when "110" => result := input(6);
when "111" => result := input(7);
when others => result := '0';
end case;
return result;
end OneOfEightMux;
component indexreg
port (
clk: in STD_LOGIC;
ibus: in STD_LOGIC_VECTOR (15 downto 0);
obus: out STD_LOGIC_VECTOR (15 downto 0);
loadindex: in STD_LOGIC;
readindex: in STD_LOGIC;
index: out STD_LOGIC_VECTOR (7 downto 0)
);
end component;
component counter
port (
obus: out STD_LOGIC_VECTOR (31 downto 0);
ibus: in STD_LOGIC_VECTOR (31 downto 0);
quada: in STD_LOGIC;
quadb: in STD_LOGIC;
index: in STD_LOGIC;
ccrloadcmd: in STD_LOGIC;
ccrreadcmd: in STD_LOGIC;
countoutreadcmd: in STD_LOGIC;
countlatchcmd: in STD_LOGIC;
countclearcmd: in STD_LOGIC;
countenable: in STD_LOGIC;
indexmask: in STD_LOGIC;
nads: in STD_LOGIC;
clk: in STD_LOGIC
);
end component;
component pwmgen
port (
clk: in STD_LOGIC;
refcount: in STD_LOGIC_VECTOR (9 downto 0);
ibus: in STD_LOGIC_VECTOR (15 downto 0);
obus: out STD_LOGIC_VECTOR (15 downto 0);
loadpwmval: in STD_LOGIC;
readpwmval: in STD_LOGIC;
clearpwmval: in STD_LOGIC;
pcrloadcmd: STD_LOGIC;
pcrreadcmd: STD_LOGIC;
pwmout: out STD_LOGIC;
dirio: inout STD_LOGIC;
enablein: in STD_LOGIC;
enableout: out STD_LOGIC
);
end component pwmgen;
component pwmref is
port (
clk: in STD_LOGIC;
refcount: out STD_LOGIC_VECTOR (9 downto 0);
irqgen: out STD_LOGIC;
ibus: in STD_LOGIC_VECTOR (15 downto 0);
obus: out STD_LOGIC_VECTOR (15 downto 0);
irqdivload: in STD_LOGIC;
irqdivread: in STD_LOGIC;
phaseload: in STD_LOGIC;
phaseread: in STD_LOGIC
);
end component pwmref;
component globalcontrolreg is
port (
clk: in STD_LOGIC;
ibus: in STD_LOGIC_VECTOR (15 downto 0);
reset: in STD_LOGIC;
loadgcr: in STD_LOGIC;
ctrclear: out STD_LOGIC;
ctrlatch: out STD_LOGIC;
pwmclear: out STD_LOGIC;
irqclear: out STD_LOGIC;
reloadwd: out STD_LOGIC
);
end component globalcontrolreg;
component globalmodereg is
port (
clk: in STD_LOGIC;
ibus: in STD_LOGIC_VECTOR (15 downto 0);
obus: out STD_LOGIC_VECTOR (15 downto 0);
reset: in STD_LOGIC;
loadglobalmode: in STD_LOGIC;
readglobalmode: in STD_LOGIC;
ctrena: out STD_LOGIC;
pwmena: out STD_LOGIC;
clearpwmena: in STD_LOGIC;
loi: out STD_LOGIC;
som: out STD_LOGIC;
sot: out STD_LOGIC;
miout: out STD_LOGIC;
miin: in STD_LOGIC;
irqmask: out STD_LOGIC;
irqstatus: in STD_LOGIC
);
end component globalmodereg;
component WordPR24 is
port (
clear: in STD_LOGIC;
clk: in STD_LOGIC;
ibus: in STD_LOGIC_VECTOR (23 downto 0);
obus: out STD_LOGIC_VECTOR (23 downto 0);
loadport: in STD_LOGIC;
loadddr: in STD_LOGIC;
readddr: in STD_LOGIC;
portdata: out STD_LOGIC_VECTOR (23 downto 0)
);
end component WordPR24;
component Word24RB is
Port (
obus: out STD_LOGIC_VECTOR (23 downto 0);
readport: in STD_LOGIC;
portdata: in STD_LOGIC_VECTOR (23 downto 0) );
end component Word24RB;
component Timeout is
Port ( clk : in std_logic;
ibus : in std_logic_vector(15 downto 0);
obus : out std_logic_vector(15 downto 0);
timeoutload : in std_logic;
timeoutread : in std_logic;
timerread : in std_logic;
reload : in std_logic;
timerz : out std_logic);
end component Timeout;
component idreadback is
Generic ( id : std_logic_vector(31 downto 0);
mc : std_logic_vector(31 downto 0));
Port ( readid : in std_logic;
readmc : in std_logic;
obus : out std_logic_vector(31 downto 0));
end component idreadback;
begin
makecounters: for i in 0 to (counters -1) generate
counterx: counter port map (
obus => D,
ibus => LAD,
quada => A(i),
quadb => B(i),
index => Idx(i),
ccrloadcmd => CCRLoadCmds(i),
ccrreadcmd => CCRReadCmds(i),
countoutreadcmd => CounterRead(i),
countlatchcmd => GlobalCountLatch,
countclearcmd => GlobalCounterClear,
countenable => GlobalCounterEnable,
indexmask => IOBITSA(16+i),
nads => ADS,
clk => LClk
);
end generate;
makescounters: for i in 0 to 3 generate
counterx: counter port map (
obus => D,
ibus => LAD,
quada => IOBITSA((i*4)),
quadb => IOBITSA((i*4)+1),
index => IOBITSA((i*4)+2),
ccrloadcmd => SCCRLoadCmds(i),
ccrreadcmd => SCCRReadCmds(i),
countoutreadcmd => SCounterRead(i),
countlatchcmd => GlobalCountLatch,
countclearcmd => GlobalCounterClear,
countenable => GlobalCounterEnable,
indexmask => IOBITSA((i*4)+3),
nads => ADS,
clk => LClk
);
end generate;
makepwmgen: for i in 0 to (counters -1) generate
pwmgenx: pwmgen port map (
clk => LClk,
refcount => RefCountBus,
ibus => LAD(15 downto 0),
obus => D(15 downto 0),
loadpwmval => LoadPWM(i),
readpwmval => ReadPWM(i),
clearpwmval => GlobalClearPWM,
pcrloadcmd => PCRLoadCmds(i),
pcrreadcmd => PCRReadCmds(i),
pwmout => PWM(i),
dirio => Dir(i),
enablein => GlobalPWMEnable,
enableout =>EnaSigs(i)
);
end generate;
oporta: WordPR24 port map (
clear => '0',
clk => LClk,
ibus => LAD(23 downto 0),
obus => D(23 downto 0),
loadport => LoadPortA,
loadddr => LoadDDRA,
readddr => ReadDDRA,
portdata => IOBITSA
);
iporta: Word24RB port map (
obus => D(23 downto 0),
readport => ReadPortA,
portdata => IOBITSA
);
-- oportb: WordPR24 port map (
-- clear => '0',
-- clk => LClk,
-- ibus => LAD(23 downto 0),
-- obus => D(23 downto 0),
-- loadport => LoadPortB,
-- loadddr => LoadDDRB,
-- readddr => ReadDDRB,
-- portdata => IOBITSB
-- );
-- iportb: Word24RB port map (
-- obus => D(23 downto 0),
-- readport => ReadPortB,
-- portdata => IOBitsB
-- );
pwmrefcount: pwmref port map (
clk => LClk,
refcount => RefCountBus,
irqgen => IRQSource,
ibus => LAD(15 downto 0),
obus => D(15 downto 0),
irqdivload => LoadIRQDivCmd,
irqdivread => ReadIRQDivCmd,
phaseload => LoadPhaseCmd,
phaseread => ReadPhaseCmd
);
gLedreg: indexreg port map (
clk => LClk,
ibus => LAD(15 downto 0),
obus => D(15 downto 0),
loadindex => LoadLEDViewCmd,
readindex => ReadLEDViewCmd,
index => LEDView
);
ggcontrolreg: globalcontrolreg port map (
clk => LClk,
ibus => LAD(15 downto 0),
reset => '0',
loadgcr => LoadGCRCmd,
ctrclear => GlobalCounterClear,
ctrlatch => GlobalCountLatchCmd,
pwmclear => GlobalClearPWMCmd,
irqclear => ClearIRQCmd,
reloadwd => ReloadWDCmd
);
gglobalmodereg: globalmodereg port map (
clk => LClk,
ibus => LAD(15 downto 0),
obus => D(15 downto 0),
reset => '0',
loadglobalmode => loadGMRCmd,
readglobalmode => ReadGMRCmd,
ctrena => GlobalCounterEnable,
pwmena => GlobalPWMEnable,
clearpwmena => StopPWM,
loi => LatchOnInterrupt,
som => StopOnMissedIRQ,
sot => StopOnTimeout,
miout => ClearMissedIRQ,
miin => MissedIRQ,
irqmask => IRQMask,
irqstatus => IRQLatch
);
atimeout: timeout port map (
clk => LClk,
ibus => LAD(15 downto 0),
obus => D(15 downto 0),
timeoutload => loadTimeOutCmd,
timeoutread => ReadTimeOutCmd,
timerread => ReadTimerCmd,
reload => ReLoadWDCmd,
timerz => WDTimeout
);
aidreadback: idreadback
generic map (
id => HMID,
mc => MasterClock
)
port map(
readid => ReadIDCmd,
readmc => ReadMCCmd,
obus => D
);
LADDrivers: process (D,FastRead)
begin
if FastRead ='1' then
LAD <= D;
else
LAD <= "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
end if;
end process LADDrivers;
AddressLatch: process (lclk)
begin
if lclk'event and LClk = '1' then
if ADS = '0' then
LatchedA <= LAD(15 downto 0);
LatchedLBE <= LBE;
end if;
end if;
end process AddressLatch;
-- we generate an early read from ADS and LR_W
-- since the 10 nS LRD delay and 5 nS setup time
-- only give us 15 nS to provide data to the PLX chip
MakeFastRead: process (lclk,PreFastread,LRD)
begin
if lclk'event and LClk = '1' then
if ADS = '0' and LW_R = '0'then
PreFastRead <= '1';
else
PreFastRead <= '0';
end if;
end if;
FastRead <= PreFastRead or (not LRD);
end process MakeFastRead;
Decode: process (LatchedA)
begin
if LatchedA(7 downto 5) = "000" then -- 32 bit access
CounterSel <= '1';
else
CounterSel <= '0';
end if;
if LatchedA(7 downto 5) = "001" then -- 32 bit access
SCounterSel <= '1';
else
SCounterSel <= '0';
end if;
if LatchedA(7 downto 4) = "0100" then -- 16 bit access
CCRSel <= '1';
else
CCRSel <= '0';
end if;
if LatchedA(7 downto 4) = "0101" then -- 16 bit access
SCCRSel <= '1';
else
SCCRSel <= '0';
end if;
if LatchedA(7 downto 5) = "011" then -- 16 bit access
PWMValSel <= '1';
else
PWMValSel <= '0';
end if;
if LatchedA(7 downto 5) = "100" then -- 16 bit access
PCRSel <= '1';
else
PCRSel <= '0';
end if;
if LatchedA(7 downto 2) = "101000" then -- 32 bit access
PortASel <= '1';
else
PortASel <= '0';
end if;
if LatchedA(7 downto 2) = "101001" then -- 32 bit access
DDRASel <= '1';
else
DDRASel <= '0';
end if;
-- if LatchedA(7 downto 2) = "101010" then -- 32 bit access
-- PortBSel <= '1';
-- else
-- PortBSel <= '0';
-- end if;
-- if LatchedA(7 downto 2) = "101011" then -- 32 bit access
-- DDRBSel <= '1';
-- else
-- DDRBSel <= '0';
-- end if;
if LatchedA(7 downto 2) = "110100" then -- 32 bit access D0
IDSel <= '1';
else
IDSel <= '0';
end if;
if LatchedA(7 downto 2) = "110101" then -- 32 bit access D4
MCSel <= '1';
else
MCSel <= '0';
end if;
if LatchedA(7 downto 1) = "1100000" then -- 16 bit access
GCRSel <= '1';
else
GCRSel <= '0';
end if;
if LatchedA(7 downto 1) = "1100001" then -- 16 bit access
GMRSel <= '1';
else
GMRSel <= '0';
end if;
if LatchedA(7 downto 1) = "1100010"then -- 16 bit access
IRQDivSel <= '1';
else
IRQDivSel <= '0';
end if;
if LatchedA(7 downto 1) = "1100011"then -- 16 bit access
PhaseSel <= '1';
else
PhaseSel <= '0';
end if;
if LatchedA(7 downto 1) = "1100100" then -- 16 bit access
TimeOutSel <= '1';
else
TimeOutSel <= '0';
end if;
if LatchedA(7 downto 1) = "1100101" then -- 16 bit access
TimerSel <= '1';
else
TimerSel <= '0';
end if;
if LatchedA(7 downto 1) = "1100110" then -- 16 bit access
LEDViewSel <= '1';
else
LEDViewSel <= '0';
end if;
end process;
SigsOut: process (EnaSigs)
begin
Ena <= EnaSigs;
end process;
CounterDecode: process (CounterSel, Fastread, LatchedA)
begin
if FastRead = '1' then
CounterRead <= OneOfEightDecode(CounterSel,LatchedA(4 downto 2));
else
CounterRead <= (others => '0');
end if;
end process;
SCounterDecode: process (SCounterSel, Fastread, LatchedA)
begin
if FastRead = '1' then
SCounterRead <= OneOfEightDecode(SCounterSel,LatchedA(4 downto 2));
else
SCounterRead <= (others => '0');
end if;
end process;
CCRegs: process (CCRSel, FastRead, LWR, LatchedA)
begin
if FastRead = '1' then
CCRReadCmds <= OneOfEightDecode(CCRSel,LatchedA(3 downto 1));
else
CCRReadCmds <= (others => '0');
end if;
if LWR = '0' then
CCRLoadCmds <= OneOfEightDecode(CCRSel,LatchedA(3 downto 1));
else
CCRLoadCmds <= (others => '0');
end if;
end process;
SCCRegs: process (SCCRSel, FastRead, LWR, LatchedA)
begin
if FastRead = '1' then
SCCRReadCmds <= OneOfEightDecode(SCCRSel,LatchedA(3 downto 1));
else
SCCRReadCmds <= (others => '0');
end if;
if LWR = '0' then
SCCRLoadCmds <= OneOfEightDecode(SCCRSel,LatchedA(3 downto 1));
else
SCCRLoadCmds <= (others => '0');
end if;
end process;
PWMdecode: process (PWMValSel,Fastread, LWR, LatchedA)
begin
if FastRead = '1' then
ReadPWM <= OneOfEightDecode(PWMValSel,LatchedA(3 downto 1));
else
ReadPWM <= (others => '0');
end if;
if LWR = '0' then
LoadPWM <= OneOfEightDecode(PWMValSel,LatchedA(3 downto 1));
else
LoadPWM <= (others => '0');
end if;
end process;
PCRegs: process (PCRSel,Fastread, LWR, LatchedA)
begin
if FastRead = '1' then
PCRReadCmds <= OneOfEightDecode(PCRSel,LatchedA(3 downto 1));
else
PCRReadCmds <= (others => '0');
end if;
if LWR = '0' then
PCRLoadCmds <= OneOfEightDecode(PCRSel,LatchedA(3 downto 1));
else
PCRLoadCmds <= (others => '0');
end if;
end process;
PortADecode: process (PortASel,FastRead,LWR)
begin
if PortASel = '1' and LWR = '0' then
LoadPortA <= '1';
else
LoadPortA <= '0';
end if;
if PortASel = '1' and FastRead = '1' then
ReadPortA <= '1';
else
ReadPortA <= '0';
end if;
end process PortADecode;
DDRADecode: process (DDRASel,FastRead,LWR)
begin
if DDRASel = '1' and LWR = '0' then
LoadDDRA <= '1';
else
LoadDDRA <= '0';
end if;
if DDRASel = '1' and FastRead = '1' then
ReadDDRA <= '1';
else
ReadDDRA <= '0';
end if;
end process DDRADecode;
-- PortBDecode: process (PortBSel,FastRead,LWR)
-- begin
-- if PortBSel = '1' and LWR = '0' then
-- LoadPortB <= '1';
-- else
-- LoadPortB <= '0';
-- end if;
-- if PortBSel = '1' and FastRead = '1' then
-- ReadPortB <= '1';
-- else
-- ReadPortB <= '0';
-- end if;
-- end process PortBDecode;
-- DDRBDecode: process (DDRBSel,FastRead,LWR)
-- begin
-- if DDRBSel = '1' and LWR = '0' then
-- LoadDDRB <= '1';
-- else
-- LoadDDRB <= '0';
-- end if;
-- if DDRBSel = '1' and FastRead = '1' then
-- ReadDDRB <= '1';
-- else
-- ReadDDRB <= '0';
-- end if;
-- end process DDRBDecode;
GCRDecode: process (GCRSel,LWR)
begin
if GCRSel = '1' and LWR = '0' then
LoadGCRCmd <= '1';
else
LoadGCRCmd <= '0';
end if;
end process GCRDecode;
GMRDecode: process (GMRSel,FastRead,LWR)
begin
if GMRSel = '1' and LWR = '0' then
LoadGMRCmd <= '1';
else
LoadGMRCmd <= '0';
end if;
if GMRSel = '1' and FastRead = '1' then
ReadGMRCmd <= '1';
else
ReadGMRCmd <= '0';
end if;
end process GMRDecode;
TimeOutDecode: process (TimeOutSel,FastRead,LWR)
begin
if TimeoutSel = '1' and LWR = '0' then
LoadTimeOutCmd <= '1';
else
LoadTimeOutCmd <= '0';
end if;
if TimeOutSel = '1' and FastRead = '1' then
ReadTimeOutCmd <= '1';
else
ReadTimeOutCmd <= '0';
end if;
end process TimeOutDecode;
TimerDecode: process (TimerSel,FastRead,LWR)
begin
if TimerSel = '1' and FastRead = '1' then
ReadTimerCmd <= '1';
else
ReadTimerCmd <= '0';
end if;
end process TimerDecode;
LEDViewDecode: process (LedViewSel,FastRead,LWR)
begin
if LEDViewSel = '1' and LWR = '0' then
LoadLEDViewCmd <= '1';
else
LoadLEDViewCmd <= '0';
end if;
if LEDViewSel = '1' and FastRead= '1' then
ReadLEDViewCmd <= '1';
else
ReadLEDViewCmd <= '0';
end if;
end process LEDViewDecode;
IRQDivDecode: process (IRQDivSel,FastRead,LWR)
begin
if IRQDivSel = '1' and LWR = '0' then
LoadIRQDivCmd <= '1';
else
LoadIRQDivCmd <= '0';
end if;
if IRQDivSel = '1' and FastRead = '1' then
ReadIRQDivCmd <= '1';
else
ReadIRQDivCmd <= '0';
end if;
end process IrqDivDecode;
PhaseDecode: process (PhaseSel,FastRead,LWR)
begin
if PhaseSel = '1' and LWR = '0' then
LoadPhaseCmd <= '1';
else
LoadPhaseCmd <= '0';
end if;
if PhaseSel = '1' and FastRead = '1' then
ReadPhaseCmd <= '1';
else
ReadPhaseCmd <= '0';
end if;
end process PhaseDecode;
IDDecode: process (IDSel,FastRead)
begin
if IDSel = '1' and FastRead = '1' then
ReadIDCmd <= '1';
else
ReadIDCmd <= '0';
end if;
end process IDDecode;
MCDecode: process (MCSel,FastRead)
begin
if MCSel = '1' and FastRead = '1' then
ReadMCCmd <= '1';
else
ReadMCCmd <= '0';
end if;
end process MCDecode;
irqlogic: process (CardSelect,
IRQSource,
IrqLatch,
ClearMissedIRQ,
MissedIRQ,
StopOnMissedIRQ,
LatchOnInterrupt,
GlobalCountLatchCmd,
GlobalClearPWMCmd,
ClearIRQCmd)
begin
if IrqSource'event and IRQsource = '1' then
IRQLatch <= '1';
if IRQLatch = '1' then -- if IRQLatch is set and we get the next interrupt
MissedIRQ <= '1'; -- set Missed IRQ latch
end if;
end if;
if LClk'event and LClk = '1' then
if ((IRQLatch = '1') and (LatchOnInterrupt = '1')) or (GlobalCountLatchCmd = '1') then
CountLatchEdge1 <= '1';
else
CountLatchEdge1 <= '0';
end if;
CountLatchEdge2 <= CountLatchEdge1;
if CountLatchEdge2 = '0' and CountLatchEdge1 = '1' then
GlobalCountLatch <= '1';
else
GlobalCountLatch <= '0';
end if;
end if;
if ClearMissedIRQ = '1' then
MissedIRQ <= '0';
end if;
if ((MissedIRQ = '1') and (StopOnMissedIRQ = '1')) or
((WDTimeOut = '1') and (StopOnTimeout = '1')) then
StopPWM <= '1';
else
StopPWM <= '0';
end if;
if (StopPWM = '1') or (GlobalClearPWMCmd = '1') then -- either stop on pwm or global clear reset pwm gens
GlobalClearPWM <= '1';
else
GlobalClearPWM <= '0';
end if;
if ClearIRQCmd = '1' then -- clear IRQ
IRQLatch <= '0';
end if;
Int <= not (IRQLatch and IRQMask); -- drive our (active low) interrupt pin
Ready <= '0'; -- We're always ready
end process;
LEDDrive: process (A,B,Idx,Dir,PWM,IRQLatch,LedView)
begin
LEDS(7) <= not IRQLatch;
LEDS(6) <= not OneOfEightMux(LEDView(2 downto 0),A);
LEDS(5) <= not OneOfEightMux(LEDView(2 downto 0),B);
LEDS(4) <= not OneOfEightMux(LEDView(2 downto 0),Idx);
LEDS(3) <= not OneOfEightMux(LEDView(2 downto 0),Dir);
LEDS(2) <= not OneOfEightMux(LEDView(2 downto 0),PWM);
LEDS(1) <= OneOfEightMux(LEDView(2 downto 0),EnaSigs);
LEDS(0) <= not WDTimeout;
end process leddrive;
end dataflow;
| lgpl-2.1 |
pwsoft/fpga_examples | rtl/video/video_dither_tb.vhd | 1 | 1258 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
-- -----------------------------------------------------------------------
entity video_dither_tb is
end entity;
-- -----------------------------------------------------------------------
architecture tb of video_dither_tb is
signal clk : std_logic := '0';
signal stop : std_logic := '0';
type test_t is record
dither : unsigned(5 downto 0);
d : unsigned(7 downto 0);
end record;
signal test_reg : test_t := (
(others => '0'),
(others => '0'));
signal q : unsigned(1 downto 0);
procedure wait_clk is
begin
if clk = '1' then
wait until clk = '0';
end if;
wait until clk = '1';
end procedure;
begin
clk <= (not stop) and (not clk) after 5 ns;
dither_inst : entity work.video_dither
generic map (
dBits => 8,
qBits => 2,
ditherBits => 6
)
port map (
clk => clk,
dither => test_reg.dither,
d => test_reg.d,
q => q
);
process
begin
wait_clk;
pixel_loop : for pixel in 0 to 255 loop
dither_loop : for dither in 0 to 63 loop
test_reg.d <= to_unsigned(pixel, 8);
test_reg.dither <= to_unsigned(dither, 6);
wait_clk;
end loop;
end loop;
wait_clk;
stop <= '1';
wait;
end process;
end architecture;
| lgpl-2.1 |
pwsoft/fpga_examples | rtl/general/gen_bin2gray_tb.vhd | 1 | 2184 | -- -----------------------------------------------------------------------
--
-- Syntiac's generic VHDL support files.
--
-- -----------------------------------------------------------------------
-- Copyright 2005-2012 by Peter Wendrich ([email protected])
-- http://www.syntiac.com/fpga64.html
--
-- This source file is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published
-- by the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This source file is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- -----------------------------------------------------------------------
--
-- gen_bin2gray_tb.vhd
--
-- -----------------------------------------------------------------------
--
-- Testbench for binary to gray-code converter
--
-- -----------------------------------------------------------------------
library IEEE;
use STD.textio.ALL;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
-- -----------------------------------------------------------------------
entity gen_bin2gray_tb is
end entity;
-- -----------------------------------------------------------------------
architecture rtl of gen_bin2gray_tb is
signal d : unsigned(3 downto 0);
signal q : unsigned(3 downto 0);
begin
myBin2Gray : entity work.gen_bin2gray
port map (
d => d,
q => q
);
process
begin
d <= "0000";
wait for 1 ns;
assert(q = "0000");
d <= "0001";
wait for 1 ns;
assert(q = "0001");
d <= "0010";
wait for 1 ns;
assert(q = "0011");
d <= "0011";
wait for 1 ns;
assert(q = "0010");
d <= "0110";
wait for 1 ns;
assert(q = "0101");
d <= "1100";
wait for 1 ns;
-- write(output, integer'image(to_integer(q)));
assert(q = "1010");
wait;
end process;
end architecture;
| lgpl-2.1 |
estadofinito/biblioteca-vhdl | proyectos/pjt002-mux-7seg-6bits/clk200Hz.vhd | 8 | 1564 | ----------------------------------------------------------------------------------
-- Compañía: Estado Finito
-- Ingeniero: Carlos Ramos
--
-- Fecha de creación: 2012/07/26 08:23:31
-- Nombre del módulo: clk200Hz - Behavioral
-- Descripción:
-- Divisor de frecuencia implementado con contadores. Este divisor de frecuencia
-- reduce la escala en un factor de 125000 veces. En este caso, la frecuencia se
-- reduce de 50MHz de entrada a 200Hz a la salida.
--
-- Comentarios adicionales:
-- Se puede encontrar más información en la siguiente dirección:
-- http://www.estadofinito.com/divisor-frecuencia-vhdl/
--
-- Revisión:
-- Revisión 0.01 - Archivo creado.
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity clk200Hz is
Port (
entrada: in STD_LOGIC;
reset : in STD_LOGIC;
salida : out STD_LOGIC
);
end clk200Hz;
architecture Behavioral of clk200Hz is
signal temporal: STD_LOGIC;
signal contador: integer range 0 to 124999 := 0;
begin
divisor_frecuencia: process (reset, entrada) begin
if (reset = '1') then
temporal <= '0';
contador <= 0;
elsif rising_edge(entrada) then
if (contador = 124999) then
temporal <= NOT(temporal);
contador <= 0;
else
contador <= contador+1;
end if;
end if;
end process;
salida <= temporal;
end Behavioral; | lgpl-2.1 |
estadofinito/biblioteca-vhdl | proyectos/pjt004-pwm-servo/servo_pwm.vhd | 4 | 2008 | ----------------------------------------------------------------------------------
-- Compañía: Estado Finito
-- Ingeniero: Carlos Ramos
--
-- Fecha de creación: 2012/12/18 12:38:52
-- Nombre del módulo: servo_pwm - Behavioral
-- Descripción:
-- Controlador en VHDL para servomotor con las siguientes especificaciones:
-- Frecuencia de actualización de 20ms.
-- 128 estados posibles.
-- Ancho de pulso entre 0.5ms y 2.5ms.
--
-- NOTA: Para cumplir con las especificaciones mencionadas arriba debe recibir
-- una señal de reloj de 64kHz.Favor de consultar las URL mencionadas debajo
-- para conocer más acerca de los cálculos relacionados al diseño.
--
-- Comentarios adicionales:
-- Se puede encontrar más información en la siguiente dirección:
-- http://www.estadofinito.com/servo-pwm-vhdl
--
-- Revisión:
-- Revisión 0.01 - Archivo creado.
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity servo_pwm is
PORT (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
pos : IN STD_LOGIC_VECTOR(6 downto 0);
servo : OUT STD_LOGIC
);
end servo_pwm;
architecture Behavioral of servo_pwm is
-- Contador de 0 a 1279.
signal cnt : unsigned(10 downto 0);
-- Señal temporal para generar el PWM.
signal pwmi: unsigned(7 downto 0);
begin
-- Valor mínimo debe ser de 0.5ms.
pwmi <= unsigned('0' & pos) + 32;
-- Proceso del contador, de 0 a 1279.
contador: process (reset, clk) begin
if (reset = '1') then
cnt <= (others => '0');
elsif rising_edge(clk) then
if (cnt = 1279) then
cnt <= (others => '0');
else
cnt <= cnt + 1;
end if;
end if;
end process;
-- Señal de salida para el servomotor.
servo <= '1' when (cnt < pwmi) else '0';
end Behavioral; | lgpl-2.1 |
estadofinito/biblioteca-vhdl | todos-los-archivos/siete_segmentos_4bits.vhd | 4 | 1260 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity siete_segmentos_4bits is
PORT (
entrada: IN STD_LOGIC_VECTOR(3 downto 0);
salida : OUT STD_LOGIC_VECTOR(7 downto 0)
);
end siete_segmentos_4bits;
architecture Behavioral of siete_segmentos_4bits is
begin
visualizador: process (entrada) begin
case entrada is
when "0000" => salida <= x"C0"; -- 0
when "0001" => salida <= x"F9"; -- 1
when "0010" => salida <= x"A4"; -- 2
when "0011" => salida <= x"B0"; -- 3
when "0100" => salida <= x"99"; -- 4
when "0101" => salida <= x"92"; -- 5
when "0110" => salida <= x"82"; -- 6
when "0111" => salida <= x"F8"; -- 7
when "1000" => salida <= x"80"; -- 8
when "1001" => salida <= x"98"; -- 9
when "1010" => salida <= x"88"; -- A
when "1011" => salida <= x"83"; -- B
when "1100" => salida <= x"C6"; -- C
when "1101" => salida <= x"A1"; -- D
when "1110" => salida <= x"86"; -- E
when "1111" => salida <= x"8E"; -- F
when others => salida <= x"FF"; -- Nada
end case;
end process;
end Behavioral;
| lgpl-2.1 |
estadofinito/biblioteca-vhdl | todos-los-archivos/multiplexor_frecuencias.vhd | 2 | 1818 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity multiplexor_frecuencias is
PORT (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
selector: IN STD_LOGIC_VECTOR(2 DOWNTO 0);
salida : OUT STD_LOGIC
);
end multiplexor_frecuencias;
architecture Behavioral of multiplexor_frecuencias is
COMPONENT mux8a1 IS
PORT (
entrada : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
selector: IN STD_LOGIC_VECTOR(2 DOWNTO 0);
salida : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT clk0_0625Hz IS PORT (clk: IN STD_LOGIC; reset: IN STD_LOGIC; clk_out: OUT STD_LOGIC); END COMPONENT;
COMPONENT clk0_125Hz IS PORT (clk: IN STD_LOGIC; reset: IN STD_LOGIC; clk_out: OUT STD_LOGIC); END COMPONENT;
COMPONENT clk0_25Hz IS PORT (clk: IN STD_LOGIC; reset: IN STD_LOGIC; clk_out: OUT STD_LOGIC); END COMPONENT;
COMPONENT clk0_5Hz IS PORT (clk: IN STD_LOGIC; reset: IN STD_LOGIC; clk_out: OUT STD_LOGIC); END COMPONENT;
COMPONENT clk1Hz IS PORT (clk: IN STD_LOGIC; reset: IN STD_LOGIC; clk_out: OUT STD_LOGIC); END COMPONENT;
COMPONENT clk2Hz IS PORT (clk: IN STD_LOGIC; reset: IN STD_LOGIC; clk_out: OUT STD_LOGIC); END COMPONENT;
COMPONENT clk4Hz IS PORT (clk: IN STD_LOGIC; reset: IN STD_LOGIC; clk_out: OUT STD_LOGIC); END COMPONENT;
signal clks : STD_LOGIC_VECTOR(7 DOWNTO 0) := x"00";
begin
clks(0) <= '0';
clk0_0625Hz_i: clk0_0625Hz PORT MAP(clk, reset, clks(1));
clk0_125Hz_i: clk0_125Hz PORT MAP(clk, reset, clks(2));
clk0_25Hz_i: clk0_25Hz PORT MAP(clk, reset, clks(3));
clk0_5Hz_i: clk0_5Hz PORT MAP(clk, reset, clks(4));
clk1Hz_i: clk1Hz PORT MAP(clk, reset, clks(5));
clk2Hz_i: clk2Hz PORT MAP(clk, reset, clks(6));
clk4Hz_i: clk4Hz PORT MAP(clk, reset, clks(7));
mux8a1_i: mux8a1 PORT MAP(clks, selector, salida);
end Behavioral; | lgpl-2.1 |
estadofinito/biblioteca-vhdl | todos-los-archivos/rom512_28b.vhd | 4 | 9875 | ----------------------------------------------------------------------------------
-- Compañía: Estado Finito
-- Ingeniero: Carlos Ramos
--
-- Fecha de creación: 2014/04/02 17:50:33
-- Nombre del módulo: rom512_28b - Behavioral
-- Descripción:
-- Módulo que contiene 512 registros de 28 bits cada uno, correspondientes a las
-- escalas necesarias a para implementar divisores de frecuencia en el rango de
-- 1 BPM a 512 BPM, asumiendo que el reloj de entrada sea de 3.125MHz.
--
-- Comentarios adicionales:
-- Se puede encontrar más información en la siguiente dirección:
-- http://www.estadofinito.com/rom/
--
-- Revisión:
-- Revisión 0.01 - Archivo creado.
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity rom512_28b is
port (
clk : in std_logic;
en : in std_logic;
addr : in std_logic_vector(8 downto 0);
data : out std_logic_vector(27 downto 0)
);
end rom512_28b;
architecture behavioral of rom512_28b is
type memoria_rom is array (0 to 511) of std_logic_vector (27 downto 0);
signal ROM : memoria_rom := (
x"b2d05df", x"59682ef", x"3b9ac9f", x"2cb4177", x"23c345f", x"1dcd64f", x"198b7b1", x"165a0bb", -- Fila con datos 0 a 7
x"13de434", x"11e1a2f", x"10417ce", x"0ee6b27", x"0dc1424", x"0cc5bd8", x"0bebc1f", x"0b2d05d", -- Fila con datos 8 a 15
x"0a84ba3", x"09ef21a", x"0969484", x"08f0d17", x"0883d3a", x"0820be6", x"07c646d", x"0773593", -- Fila con datos 16 a 23
x"07270df", x"06e0a11", x"069f6bb", x"0662dec", x"062a7ec", x"05f5e0f", x"05c4a82", x"059682e", -- Fila con datos 24 a 31
x"056b299", x"05425d1", x"051be56", x"04f790c", x"04d532f", x"04b4a42", x"0495c0b", x"047868b", -- Fila con datos 32 a 39
x"045c7f2", x"0441e9d", x"0428910", x"04105f3", x"03f940a", x"03e3236", x"03cdf71", x"03b9ac9", -- Fila con datos 40 a 47
x"03a6362", x"039386f", x"0381936", x"0370508", x"035fb47", x"034fb5d", x"03404c2", x"03316f5", -- Fila con datos 48 a 55
x"0323181", x"03153f6", x"0307ded", x"02faf07", x"02ee6e9", x"02e2541", x"02d69bd", x"02cb416", -- Fila con datos 56 a 63
x"02c0406", x"02b594c", x"02ab3aa", x"02a12e8", x"02976ce", x"028df2a", x"0284bcc", x"027bc86", -- Fila con datos 64 a 71
x"027312c", x"026a997", x"026259f", x"025a520", x"02527f8", x"024ae05", x"0243729", x"023c345", -- Fila con datos 72 a 79
x"023523e", x"022e3f8", x"022785b", x"0220f4e", x"021a8b9", x"0214488", x"020e2a3", x"02082f9", -- Fila con datos 80 a 87
x"0202575", x"01fca04", x"01f7097", x"01f191a", x"01ec380", x"01e6fb8", x"01e1db3", x"01dcd64", -- Fila con datos 88 a 95
x"01d7ebd", x"01d31b0", x"01ce632", x"01c9c37", x"01c53b3", x"01c0c9a", x"01bc6e3", x"01b8284", -- Fila con datos 96 a 103
x"01b3f71", x"01afda3", x"01abd0f", x"01a7dae", x"01a3f76", x"01a0260", x"019c664", x"0198b7a", -- Fila con datos 104 a 111
x"019519b", x"01918c0", x"018e0e2", x"018a9fa", x"0187403", x"0183ef6", x"0180acd", x"017d783", -- Fila con datos 112 a 119
x"017a512", x"0177374", x"01742a5", x"01712a0", x"016e35f", x"016b4de", x"0168719", x"0165a0b", -- Fila con datos 120 a 127
x"0162daf", x"0160203", x"015d701", x"015aca6", x"01582ed", x"01559d5", x"0153158", x"0150973", -- Fila con datos 128 a 135
x"014e224", x"014bb67", x"0149538", x"0146f95", x"0144a7a", x"01425e6", x"01401d4", x"013de42", -- Fila con datos 136 a 143
x"013bb2e", x"0139896", x"0137675", x"01354cb", x"0133394", x"01312cf", x"012f279", x"012d290", -- Fila con datos 144 a 151
x"012b311", x"01293fb", x"012754c", x"0125702", x"012391b", x"0121b94", x"011fe6c", x"011e1a2", -- Fila con datos 152 a 159
x"011c533", x"011a91e", x"0118d62", x"01171fc", x"01156eb", x"0113c2d", x"01121c1", x"01107a6", -- Fila con datos 160 a 167
x"010edda", x"010d45c", x"010bb2a", x"010a243", x"01089a6", x"0107151", x"0105944", x"010417c", -- Fila con datos 168 a 175
x"01029f9", x"01012ba", x"00ffbbd", x"00fe502", x"00fce87", x"00fb84b", x"00fa24d", x"00f8c8d", -- Fila con datos 176 a 183
x"00f7709", x"00f61c0", x"00f4cb1", x"00f37db", x"00f233e", x"00f0ed9", x"00efaaa", x"00ee6b1", -- Fila con datos 184 a 191
x"00ed2ee", x"00ebf5e", x"00eac01", x"00e98d8", x"00e85e0", x"00e7319", x"00e6082", x"00e4e1b", -- Fila con datos 192 a 199
x"00e3be3", x"00e29d9", x"00e17fc", x"00e064d", x"00df4c9", x"00de371", x"00dd244", x"00dc141", -- Fila con datos 200 a 207
x"00db068", x"00d9fb8", x"00d8f31", x"00d7ed1", x"00d6e99", x"00d5e87", x"00d4e9c", x"00d3ed7", -- Fila con datos 208 a 215
x"00d2f36", x"00d1fbb", x"00d1063", x"00d0130", x"00cf21f", x"00ce332", x"00cd466", x"00cc5bd", -- Fila con datos 216 a 223
x"00cb734", x"00ca8cd", x"00c9a86", x"00c8c5f", x"00c7e58", x"00c7070", x"00c62a7", x"00c54fd", -- Fila con datos 224 a 231
x"00c4770", x"00c3a01", x"00c2caf", x"00c1f7b", x"00c1262", x"00c0566", x"00bf886", x"00bebc1", -- Fila con datos 232 a 239
x"00bdf17", x"00bd288", x"00bc614", x"00bb9ba", x"00bad79", x"00ba152", x"00b9544", x"00b894f", -- Fila con datos 240 a 247
x"00b7d73", x"00b71af", x"00b6603", x"00b5a6f", x"00b4ef2", x"00b438c", x"00b383d", x"00b2d05", -- Fila con datos 248 a 255
x"00b21e3", x"00b16d7", x"00b0be1", x"00b0101", x"00af636", x"00aeb80", x"00ae0df", x"00ad652", -- Fila con datos 256 a 263
x"00acbda", x"00ac176", x"00ab726", x"00aacea", x"00aa2c1", x"00a98ab", x"00a8ea9", x"00a84b9", -- Fila con datos 264 a 271
x"00a7adc", x"00a7112", x"00a6759", x"00a5db3", x"00a541e", x"00a4a9b", x"00a412a", x"00a37ca", -- Fila con datos 272 a 279
x"00a2e7b", x"00a253d", x"00a1c0f", x"00a12f2", x"00a09e6", x"00a00e9", x"009f7fd", x"009ef21", -- Fila con datos 280 a 287
x"009e654", x"009dd97", x"009d4e9", x"009cc4a", x"009c3bb", x"009bb3a", x"009b2c8", x"009aa65", -- Fila con datos 288 a 295
x"009a210", x"00999ca", x"0099191", x"0098967", x"009814b", x"009793c", x"009713b", x"0096947", -- Fila con datos 296 a 303
x"0096161", x"0095988", x"00951bc", x"00949fd", x"009424b", x"0093aa6", x"009330d", x"0092b81", -- Fila con datos 304 a 311
x"0092401", x"0091c8d", x"0091525", x"0090dc9", x"009067a", x"008ff36", x"008f7fd", x"008f0d0", -- Fila con datos 312 a 319
x"008e9af", x"008e299", x"008db8e", x"008d48f", x"008cd9a", x"008c6b0", x"008bfd1", x"008b8fd", -- Fila con datos 320 a 327
x"008b234", x"008ab75", x"008a4c0", x"0089e16", x"0089776", x"00890e0", x"0088a54", x"00883d3", -- Fila con datos 328 a 335
x"0087d5b", x"00876ed", x"0087088", x"0086a2e", x"00863dc", x"0085d95", x"0085756", x"0085121", -- Fila con datos 336 a 343
x"0084af5", x"00844d3", x"0083eb9", x"00838a8", x"00832a0", x"0082ca1", x"00826ab", x"00820bd", -- Fila con datos 344 a 351
x"0081ad8", x"00814fc", x"0080f28", x"008095c", x"0080399", x"007fdde", x"007f82b", x"007f280", -- Fila con datos 352 a 359
x"007ecde", x"007e743", x"007e1b0", x"007dc25", x"007d6a2", x"007d126", x"007cbb2", x"007c646", -- Fila con datos 360 a 367
x"007c0e1", x"007bb84", x"007b62e", x"007b0df", x"007ab98", x"007a658", x"007a11f", x"0079bed", -- Fila con datos 368 a 375
x"00796c2", x"007919f", x"0078c82", x"007876c", x"007825d", x"0077d55", x"0077853", x"0077358", -- Fila con datos 376 a 383
x"0076e64", x"0076976", x"007648f", x"0075fae", x"0075ad4", x"0075600", x"0075133", x"0074c6b", -- Fila con datos 384 a 391
x"00747aa", x"00742ef", x"0073e3b", x"007398c", x"00734e3", x"0073041", x"0072ba4", x"007270d", -- Fila con datos 392 a 399
x"007227c", x"0071df1", x"007196c", x"00714ec", x"0071072", x"0070bfe", x"007078f", x"0070326", -- Fila con datos 400 a 407
x"006fec2", x"006fa64", x"006f60b", x"006f1b8", x"006ed6a", x"006e922", x"006e4de", x"006e0a0", -- Fila con datos 408 a 415
x"006dc67", x"006d834", x"006d405", x"006cfdc", x"006cbb7", x"006c798", x"006c37d", x"006bf68", -- Fila con datos 416 a 423
x"006bb57", x"006b74c", x"006b345", x"006af43", x"006ab46", x"006a74e", x"006a35a", x"0069f6b", -- Fila con datos 424 a 431
x"0069b80", x"006979b", x"00693b9", x"0068fdd", x"0068c05", x"0068831", x"0068462", x"0068097", -- Fila con datos 432 a 439
x"0067cd1", x"006790f", x"0067552", x"0067198", x"0066de3", x"0066a33", x"0066686", x"00662de", -- Fila con datos 440 a 447
x"0065f3a", x"0065b9a", x"00657fe", x"0065466", x"00650d2", x"0064d43", x"00649b7", x"006462f", -- Fila con datos 448 a 455
x"00642ab", x"0063f2c", x"0063bb0", x"0063838", x"00634c4", x"0063153", x"0062de7", x"0062a7e", -- Fila con datos 456 a 463
x"0062719", x"00623b8", x"006205a", x"0061d00", x"00619aa", x"0061657", x"0061308", x"0060fbd", -- Fila con datos 464 a 471
x"0060c75", x"0060931", x"00605f0", x"00602b3", x"005ff79", x"005fc42", x"005f910", x"005f5e0", -- Fila con datos 472 a 479
x"005f2b4", x"005ef8b", x"005ec66", x"005e944", x"005e625", x"005e309", x"005dff1", x"005dcdc", -- Fila con datos 480 a 487
x"005d9cb", x"005d6bc", x"005d3b1", x"005d0a9", x"005cda4", x"005caa2", x"005c7a3", x"005c4a7", -- Fila con datos 488 a 495
x"005c1af", x"005beb9", x"005bbc7", x"005b8d7", x"005b5ea", x"005b301", x"005b01a", x"005ad37", -- Fila con datos 496 a 503
x"005aa56", x"005a778", x"005a49d", x"005a1c5", x"0059ef0", x"0059c1e", x"005994f", x"0059682" -- Fila con datos 504 a 511
);
begin
process (clk) begin
if rising_edge(clk) then
if (en = '1') then
data <= ROM(conv_integer(addr));
end if;
end if;
end process;
end behavioral; | lgpl-2.1 |
estadofinito/biblioteca-vhdl | proyectos/pjt005-pwm-servo-dos-btn/servo_pwm_contador_clk64kHz_tb.vhd | 2 | 1339 | LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY servo_pwm_contador_clk64kHz_tb IS
END servo_pwm_contador_clk64kHz_tb;
ARCHITECTURE behavior OF servo_pwm_contador_clk64kHz_tb IS
-- Unidad bajo prueba.
COMPONENT servo_pwm_contador_clk64kHz
PORT(
clk : IN std_logic;
reset : IN std_logic;
cnt_up: IN std_logic;
cnt_dn: IN std_logic;
servo : OUT std_logic
);
END COMPONENT;
-- Entradas.
signal clk : std_logic := '0';
signal reset : std_logic := '0';
signal cnt_up : std_logic := '0';
signal cnt_dn : std_logic := '0';
-- Salidas.
signal servo : std_logic;
-- Definición del reloj.
constant clk_period : time := 10 ns;
BEGIN
-- Instancia de la unidad bajo prueba.
uut: servo_pwm_contador_clk64kHz PORT MAP (
clk => clk,
reset => reset,
cnt_up => cnt_up,
cnt_dn => cnt_dn,
servo => servo
);
-- Definición del proceso de reloj.
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Procesamiento de estímulos.
proceso_estimulos: process begin
-- Crear condición de reset.
reset <= '1';
wait for 50 ns;
reset <= '0';
-- Esperar poco menos de dos ciclos.
wait for 39 ms;
-- Crear el estímulo.
cnt_up <= '1';
wait for 15 us; -- Tiempo a editar.
--cnt_up <= '0';
wait;
end process;
END; | lgpl-2.1 |
estadofinito/biblioteca-vhdl | proyectos/pjt003-reloj-digital/reloj.vhd | 2 | 2426 | ----------------------------------------------------------------------------------
-- Compañía: Estado Finito
-- Ingeniero: Carlos Ramos
--
-- Fecha de creación: 2012/10/26 21:01:42
-- Nombre del módulo: reloj - Behavioral
-- Descripción:
-- Une el contador del reloj con los divisores de frecuencia y el controlador
-- de siete segmentos completo para mostrar la hora en una tarjeta Basys2.
-- Comentarios adicionales:
-- Se puede encontrar más información en la siguiente dirección:
-- http://www.estadofinito.com/reloj-digital/
-- Revisión:
-- Revisión 0.01 - Archivo creado.
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity reloj is
PORT(
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
salida: OUT STD_LOGIC_VECTOR(7 downto 0);
MUX : OUT STD_LOGIC_VECTOR(3 downto 0)
);
end reloj;
architecture Behavioral of reloj is
COMPONENT clk1Hz IS
PORT (
entrada: IN STD_LOGIC;
reset : IN STD_LOGIC;
salida : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT contador_reloj IS
PORT (
clk : IN STD_LOGIC;
reset: IN STD_LOGIC;
H1 : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
H0 : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M1 : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M0 : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
);
END COMPONENT;
COMPONENT siete_segmentos_completo IS
PORT (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
D0 : IN STD_LOGIC_VECTOR(5 downto 0);
D1 : IN STD_LOGIC_VECTOR(5 downto 0);
D2 : IN STD_LOGIC_VECTOR(5 downto 0);
D3 : IN STD_LOGIC_VECTOR(5 downto 0);
salida: OUT STD_LOGIC_VECTOR(7 downto 0);
MUX : OUT STD_LOGIC_VECTOR(3 downto 0)
);
END COMPONENT;
signal clk_out : STD_LOGIC := '0';
signal HH1, MM1: STD_LOGIC_VECTOR(2 downto 0);
signal HH0, MM0: STD_LOGIC_VECTOR(3 downto 0);
signal pHH1, pHH0, pMM1, pMM0: STD_LOGIC_VECTOR(5 downto 0);
begin
--PORT MAPs necesarios para habilitar el reloj.
clk_i: clk1Hz PORT MAP(clk, reset, clk_out);
cnt_i: contador_reloj PORT MAP(clk_out, reset, HH1, HH0, MM1, MM0);
seg_i: siete_segmentos_completo PORT MAP(clk, reset, pMM0, pMM1, pHH0, pHH1, salida, MUX);
--Padding de las señales del contador para siete segmentos.
pHH1 <= "000" & HH1;
pHH0 <= "00" & HH0;
pMM1 <= "000" & MM1;
pMM0 <= "00" & MM0;
end Behavioral; | lgpl-2.1 |
jandecaluwe/myhdl | example/manual/inc.vhd | 6 | 852 | -- File: inc.vhd
-- Generated by MyHDL 1.0dev
-- Date: Sun May 22 18:46:37 2016
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;
use work.pck_myhdl_10.all;
entity inc is
port (
count: inout unsigned(7 downto 0);
enable: in std_logic;
clock: in std_logic;
reset: in std_logic
);
end entity inc;
-- Incrementer with enable.
--
-- count -- output
-- enable -- control input, increment when 1
-- clock -- clock input
-- reset -- asynchronous reset input
architecture MyHDL of inc is
begin
INC_SEQ: process (clock, reset) is
begin
if (reset = '0') then
count <= to_unsigned(0, 8);
elsif rising_edge(clock) then
if bool(enable) then
count <= (count + 1);
end if;
end if;
end process INC_SEQ;
end architecture MyHDL;
| lgpl-2.1 |
hgomersall/myhdl | example/manual/pck_myhdl_10.vhd | 6 | 4346 | -- File: pck_myhdl_10.vhd
-- Generated by MyHDL 1.0dev
-- Date: Thu Jun 23 19:06:43 2016
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package pck_myhdl_10 is
attribute enum_encoding: string;
function stdl (arg: boolean) return std_logic;
function stdl (arg: integer) return std_logic;
function to_unsigned (arg: boolean; size: natural) return unsigned;
function to_signed (arg: boolean; size: natural) return signed;
function to_integer(arg: boolean) return integer;
function to_integer(arg: std_logic) return integer;
function to_unsigned (arg: std_logic; size: natural) return unsigned;
function to_signed (arg: std_logic; size: natural) return signed;
function bool (arg: std_logic) return boolean;
function bool (arg: unsigned) return boolean;
function bool (arg: signed) return boolean;
function bool (arg: integer) return boolean;
function "-" (arg: unsigned) return signed;
function tern_op(cond: boolean; if_true: std_logic; if_false: std_logic) return std_logic;
function tern_op(cond: boolean; if_true: unsigned; if_false: unsigned) return unsigned;
function tern_op(cond: boolean; if_true: signed; if_false: signed) return signed;
end pck_myhdl_10;
package body pck_myhdl_10 is
function stdl (arg: boolean) return std_logic is
begin
if arg then
return '1';
else
return '0';
end if;
end function stdl;
function stdl (arg: integer) return std_logic is
begin
if arg /= 0 then
return '1';
else
return '0';
end if;
end function stdl;
function to_unsigned (arg: boolean; size: natural) return unsigned is
variable res: unsigned(size-1 downto 0) := (others => '0');
begin
if arg then
res(0):= '1';
end if;
return res;
end function to_unsigned;
function to_signed (arg: boolean; size: natural) return signed is
variable res: signed(size-1 downto 0) := (others => '0');
begin
if arg then
res(0) := '1';
end if;
return res;
end function to_signed;
function to_integer(arg: boolean) return integer is
begin
if arg then
return 1;
else
return 0;
end if;
end function to_integer;
function to_integer(arg: std_logic) return integer is
begin
if arg = '1' then
return 1;
else
return 0;
end if;
end function to_integer;
function to_unsigned (arg: std_logic; size: natural) return unsigned is
variable res: unsigned(size-1 downto 0) := (others => '0');
begin
res(0):= arg;
return res;
end function to_unsigned;
function to_signed (arg: std_logic; size: natural) return signed is
variable res: signed(size-1 downto 0) := (others => '0');
begin
res(0) := arg;
return res;
end function to_signed;
function bool (arg: std_logic) return boolean is
begin
return arg = '1';
end function bool;
function bool (arg: unsigned) return boolean is
begin
return arg /= 0;
end function bool;
function bool (arg: signed) return boolean is
begin
return arg /= 0;
end function bool;
function bool (arg: integer) return boolean is
begin
return arg /= 0;
end function bool;
function "-" (arg: unsigned) return signed is
begin
return - signed(resize(arg, arg'length+1));
end function "-";
function tern_op(cond: boolean; if_true: std_logic; if_false: std_logic) return std_logic is
begin
if cond then
return if_true;
else
return if_false;
end if;
end function tern_op;
function tern_op(cond: boolean; if_true: unsigned; if_false: unsigned) return unsigned is
begin
if cond then
return if_true;
else
return if_false;
end if;
end function tern_op;
function tern_op(cond: boolean; if_true: signed; if_false: signed) return signed is
begin
if cond then
return if_true;
else
return if_false;
end if;
end function tern_op;
end pck_myhdl_10;
| lgpl-2.1 |
PsiStarPsi/firmware-ethernet | Ethernet/1000BASE-X/sim/CoreDataSim.vhd | 1 | 7796 | --------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 00:36:20 08/28/2015
-- Design Name:
-- Module Name: C:/Users/Kurtis/Google Drive/mTC/svn/src/Ethernet/General/sim/IPv4Test.vhd
-- Project Name: ethernet
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: IPv4Tx
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use work.UtilityPkg.all;
use work.GigabitEthPkg.all;
use work.Eth1000BaseXPkg.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY CoreDataSim IS
END CoreDataSim;
ARCHITECTURE behavior OF CoreDataSim IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT IPv4Tx
PORT(
ethTxClk : IN std_logic;
ethTxRst : IN std_logic;
ipPacketLength : IN std_logic_vector(15 downto 0);
ipPacketId : IN std_logic_vector(15 downto 0);
ipMoreFragments : IN std_logic;
ipFragOffset : IN std_logic_vector(12 downto 0);
ipProtocol : IN std_logic_vector(7 downto 0);
ipSrcAddr : IN IpAddrType;
ipDstAddr : IN IpAddrType;
ipData : IN std_logic_vector(31 downto 0);
ipDataValid : IN std_logic;
ipDataReady : OUT std_logic;
ethTxDataIn : OUT std_logic_vector(7 downto 0);
ethTxDataValid : OUT std_logic;
ethTxDataLastByte : OUT std_logic;
ethTxDataReady : IN std_logic
);
END COMPONENT;
--Inputs
signal ethClk125 : std_logic := '0';
signal ethClk125Rst : std_logic := '0';
signal ethClk62 : std_logic := '0';
signal ethClk62Rst : std_logic := '0';
signal ethCoreMacAddr : MacAddrType := MAC_ADDR_DEFAULT_C;
signal ethCoreIpAddr : IpAddrType := IP_ADDR_DEFAULT_C;
signal phyRxLaneIn : EthRxPhyLaneInType;
signal phyTxLaneOut : EthTxPhyLaneOutType;
signal dummyPhyRxLaneIn : EthRxPhyLaneInType;
signal dummyPhyTxLaneOut : EthTxPhyLaneOutType;
signal ethRxLinkSync : sl;
signal ethAutoNegDone : sl;
-- User Data signals
signal tpData : slv(31 downto 0);
signal tpDataValid : sl;
signal tpDataLast : sl := '0';
signal tpDataReady : sl;
-- Clock period definitions
constant ethClk125_period : time := 8 ns;
constant ethClk62_period : time := 16 ns;
constant GATE_DELAY_C : time := 1 ns;
BEGIN
--------------------------------
-- Gigabit Ethernet Interface --
--------------------------------
U_Eth1000BaseXCore : entity work.Eth1000BaseXCore
generic map (
NUM_IP_G => 1,
EN_AUTONEG_G => true,
SIM_SPEEDUP_G => true,
GATE_DELAY_G => GATE_DELAY_C
)
port map (
-- 125 MHz clock and reset
eth125Clk => ethClk125,
eth125Rst => ethClk125Rst,
-- 62 MHz clock and reset
eth62Clk => ethClk62,
eth62Rst => ethClk62Rst,
-- Addressing
macAddr => ethCoreMacAddr,
ipAddrs => (0 => ethCoreIpAddr),
udpPorts => (0 => x"07D0"), --x7D0 = 2000
-- Data to/from GT
phyRxData => phyRxLaneIn,
phyTxData => phyTxLaneOut,
-- Status signals
statusSync => ethRxLinkSync,
statusAutoNeg => ethAutoNegDone,
-- User clock and reset
userClk => ethClk125,
userRst => ethClk125Rst,
-- User data
userTxData => (0 => tpData),
userTxDataValid => (0 => tpDataValid),
userTxDataLast => (0 => tpDataLast),
userTxDataReady(0) => tpDataReady,
userRxData => open,
userRxDataValid => open,
userRxDataLast => open,
userRxDataReady => (others => '1')
);
U_TpGenTx : entity work.TpGenTx
generic map (
NUM_WORDS_G => 1000,
WAIT_CYCLES_G => 5,
GATE_DELAY_G => GATE_DELAY_C
)
port map (
-- User clock and reset
userClk => ethClk125,
userRst => ethClk125Rst or not(ethAutoNegDone),
-- Connection to user logic
userTxData => tpData,
userTxDataValid => tpDataValid,
userTxDataLast => tpDataLast,
userTxDataReady => tpDataReady
);
--------------------------------
-- DummyCore Ethernet Interface --
--------------------------------
U_DummyCore : entity work.Eth1000BaseXCore
generic map (
NUM_IP_G => 1,
EN_AUTONEG_G => true,
SIM_SPEEDUP_G => true,
GATE_DELAY_G => GATE_DELAY_C
)
port map (
-- 125 MHz clock and reset
eth125Clk => ethClk125,
eth125Rst => ethClk125Rst,
-- 62 MHz clock and reset
eth62Clk => ethClk62,
eth62Rst => ethClk62Rst,
-- Addressing
macAddr => ethCoreMacAddr,
ipAddrs => (0 => ethCoreIpAddr),
udpPorts => (0 => x"07D0"), --x7D0 = 2000
-- Data to/from GT
phyRxData => dummyPhyRxLaneIn,
phyTxData => dummyPhyTxLaneOut,
-- Status signals
statusSync => ethRxLinkSync,
statusAutoNeg => ethAutoNegDone,
-- User clock and reset
userClk => ethClk125,
userRst => ethClk125Rst,
-- User data
userTxData => (0 => tpData),
userTxDataValid => (0 => tpDataValid),
userTxDataLast => (0 => tpDataLast),
userTxDataReady(0) => tpDataReady,
userRxData => open,
userRxDataValid => open,
userRxDataLast => open,
userRxDataReady => (others => '1')
);
-- Match up B TX to A RX
phyRxLaneIn.data <= dummyPhyTxLaneOut.data;
phyRxLaneIn.dataK <= dummyPhyTxLaneOut.dataK;
phyRxLaneIn.dispErr <= (others => '0');
phyRxLaneIn.decErr <= (others => '0');
-- Match up A TX to B RX
dummyPhyRxLaneIn.data <= phyTxLaneOut.data;
dummyPhyRxLaneIn.dataK <= phyTxLaneOut.dataK;
dummyPhyRxLaneIn.dispErr <= (others => '0');
dummyPhyRxLaneIn.decErr <= (others => '0');
-- Clock process definitions
ethClk125_process : process
begin
ethClk125 <= '0';
wait for ethClk125_period/2;
ethClk125 <= '1';
wait for ethClk125_period/2;
end process;
ethClk62_process : process
begin
ethClk62 <= '0';
wait for ethClk62_period/2;
ethClk62 <= '1';
wait for ethClk62_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
ethClk125Rst <= '1';
ethClk62Rst <= '1';
wait for 100 ns;
ethClk125Rst <= '0';
ethClk62Rst <= '0';
wait for ethClk125_period*10;
-- insert stimulus here
wait;
end process;
END;
| lgpl-2.1 |
PsiStarPsi/firmware-ethernet | Ethernet/General/rtl/ArpIpArbiter.vhd | 1 | 4657 | ---------------------------------------------------------------------------------
-- Title : Arbiter between ARP and IPv4
-- Project : General Purpose Core
---------------------------------------------------------------------------------
-- File : ArpIpArbiter.vhd
-- Author : Kurtis Nishimura
---------------------------------------------------------------------------------
-- Description:
-- Prioritizes responding to ARP requests.
---------------------------------------------------------------------------------
LIBRARY ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use work.UtilityPkg.all;
use work.GigabitEthPkg.all;
entity ArpIpArbiter is
generic (
GATE_DELAY_G : in time := 1 ns
);
port (
-- 125 MHz ethernet clock in
ethTxClk : in sl;
ethTxRst : in sl;
-- ARP request/ack, data interface
arpTxReq : in sl;
arpTxAck : in sl;
arpTxData : in slv(7 downto 0);
arpTxDataValid : in sl;
arpTxDataLastByte : in sl;
arpTxDataReady : out sl;
-- IPv4 request/ack, data interface
ipTxData : in slv(7 downto 0);
ipTxDataValid : in sl;
ipTxDataLastByte : in sl;
ipTxDataReady : out sl;
-- Output MUXed data
ethTxEtherType : out EtherType;
ethTxData : out slv(7 downto 0);
ethTxDataValid : out sl;
ethTxDataLastByte : out sl;
ethTxDataReady : in sl
);
end ArpIpArbiter;
architecture rtl of ArpIpArbiter is
type StateType is (IDLE_S, WAIT_ARP_S, WAIT_IP_S, FINISH_ARP_S);
type RegType is record
state : StateType;
end record RegType;
constant REG_INIT_C : RegType := (
state => IDLE_S
);
signal r : RegType := REG_INIT_C;
signal rin : RegType;
-- ISE attributes to keep signals for debugging
-- attribute keep : string;
-- attribute keep of r : signal is "true";
-- attribute keep of crcOut : signal is "true";
-- Vivado attributes to keep signals for debugging
-- attribute dont_touch : string;
-- attribute dont_touch of r : signal is "true";
-- attribute dont_touch of crcOut : signal is "true";
begin
comb : process(r,ethTxRst,arpTxReq,arpTxAck,arpTxData,arpTxDataValid,arpTxDataLastByte,
ipTxData,ipTxDataValid,ipTxDataLastByte,ethTxDataReady) is
variable v : RegType;
begin
v := r;
-- Set defaults / reset any pulsed signals
ethTxEtherType <= (others => '0');
ethTxData <= (others => '0');
ethTxDataValid <= '0';
ethTxDataLastByte <= '0';
arpTxDataReady <= '0';
ipTxDataReady <= '0';
-- State machine
case(r.state) is
-- Ready should be zero for all possible output types
-- If we see an ARP request, go ahead with it
-- (if we want to add ICMP, put it here)
-- Otherwise, default to IP data
when IDLE_S =>
if (arpTxReq = '1') then
v.state := WAIT_ARP_S;
elsif ipTxDataValid = '1' then
v.state := WAIT_IP_S;
end if;
when WAIT_ARP_S =>
ethTxEtherType <= ETH_TYPE_ARP_C;
ethTxData <= arpTxData;
ethTxDataValid <= arpTxDataValid;
ethTxDataLastByte <= arpTxDataLastByte;
arpTxDataReady <= ethTxDataReady;
if arpTxAck = '1' then
v.state := FINISH_ARP_S;
end if;
when WAIT_IP_S =>
ethTxEtherType <= ETH_TYPE_IPV4_C;
ethTxData <= ipTxData;
ethTxDataValid <= ipTxDataValid;
ethTxDataLastByte <= ipTxDataLastByte;
ipTxDataReady <= ethTxDataReady;
-- Byte was valid, last, and accepted
if ipTxDataValid = '1' and ipTxDataLastByte = '1' and ethTxDataReady = '1' then
v.state := IDLE_S;
end if;
when FINISH_ARP_S =>
if arpTxReq = '0' then
v.state := IDLE_S;
end if;
when others =>
v.state := IDLE_S;
end case;
-- Reset logic
if (ethTxRst = '1') then
v := REG_INIT_C;
end if;
-- Outputs to ports
-- Assign variable to signal
rin <= v;
end process;
seq : process (ethTxClk) is
begin
if (rising_edge(ethTxClk)) then
r <= rin after GATE_DELAY_G;
end if;
end process seq;
end rtl;
| lgpl-2.1 |
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