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// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
`celldefine
module denoise_g3_p0_core (q, ra, ce, clk, d, wa, we);
parameter READ_PORT_COUNT=32'd2;
parameter WRITE_PORT_COUNT=32'd1;
parameter DATA_WIDTH=32'd32;
parameter ADDRESS_WIDTH=32'd8;
parameter WORD_COUNT=32'd225;
output [READ_PORT_COUNT*DATA_WIDTH-1:0] q;
input [READ_PORT_COUNT*ADDRESS_WIDTH-1:0] ra;
input [READ_PORT_COUNT-1:0] ce;
input [WRITE_PORT_COUNT*DATA_WIDTH-1:0] d;
input [WRITE_PORT_COUNT*ADDRESS_WIDTH-1:0] wa;
input [WRITE_PORT_COUNT-1:0] we;
input clk;
integer i,j,k;
reg [DATA_WIDTH-1:0] mem [0:WORD_COUNT-1];
reg [ADDRESS_WIDTH-1:0] rat;
reg [ADDRESS_WIDTH-1:0] rai [READ_PORT_COUNT-1:0];
reg [ADDRESS_WIDTH-1:0] rai_reg [READ_PORT_COUNT-1:0];
reg [READ_PORT_COUNT*DATA_WIDTH-1:0] qi;
reg [DATA_WIDTH-1:0] qt;
reg [DATA_WIDTH-1:0] di [WRITE_PORT_COUNT-1:0];
reg [DATA_WIDTH-1:0] dt;
reg [ADDRESS_WIDTH-1:0] wat;
reg [ADDRESS_WIDTH-1:0] wai [WRITE_PORT_COUNT-1:0];
// Split input data
always @ (d) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<DATA_WIDTH;j=j+1) begin
dt[j]=d[i*DATA_WIDTH+j];
end
di[i]=dt;
end
end
// Split write addresses
always @ (wa) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
wat[j]=wa[i*ADDRESS_WIDTH+j];
end
wai[i]=wat;
end
end
// Write memory
always @ (posedge clk) begin
for (j=0;j<WRITE_PORT_COUNT;j=j+1) begin
if (we[j]) begin
mem[wai[j]] <= di[j];
end
end
end
// Split read addresses
always @ (ra) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
rat[j]=ra[i*ADDRESS_WIDTH+j];
end
rai[i]=rat;
end
end
// guide read addresses using CE
always @ (posedge clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if ( ce[i] ) begin
rai_reg[i] <= rai[i];
end
end
end
// Memory read
always @ (rai_reg[0] or rai_reg[1] or clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if (rai_reg[i] >= WORD_COUNT) begin
qt={DATA_WIDTH {1'b0}};
end else begin
qt=mem[rai_reg[i]];
end
for (j=0;j<DATA_WIDTH;j=j+1) begin
qi[i*DATA_WIDTH+j]=qt[j];
end
end
end
assign q=qi;
endmodule
`endcelldefine
module denoise_g3_p0 (
address0,
ce0,
q0,
we0,
d0,
address1,
ce1,
q1,
clk);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd225;
parameter AddressWidth = 32'd8;
input[AddressWidth-1:0] address0;
input ce0;
output[DataWidth-1:0] q0;
input we0;
input[DataWidth-1:0] d0;
input[AddressWidth-1:0] address1;
input ce1;
output[DataWidth-1:0] q1;
input clk;
reg[DataWidth-1:0] q0;
reg[DataWidth-1:0] q1;
wire[2 * DataWidth - 1:0] mem_q;
wire[DataWidth - 1:0] mem_q0;
wire[DataWidth - 1:0] mem_q1;
wire[1 - 1:0] mem_we;
wire[1 * DataWidth - 1:0] mem_d;
wire[1 * AddressWidth - 1:0] mem_wa;
wire[2 * AddressWidth - 1:0] mem_ra;
wire[2 - 1:0] mem_ce;
denoise_g3_p0_core #(
.READ_PORT_COUNT( 2 ),
.WRITE_PORT_COUNT( 1 ),
.DATA_WIDTH( DataWidth ),
.ADDRESS_WIDTH( AddressWidth ),
.WORD_COUNT( AddressRange ))
core_inst (
.q( mem_q ),
.ra( mem_ra ),
.ce( mem_ce ),
.d( mem_d ),
.wa( mem_wa ),
.we( mem_we ),
.clk( clk ));
assign mem_q0 = mem_q[2 * DataWidth - 1 : 1 * DataWidth];
always @ (mem_q0) begin
q0 = mem_q0;
end
assign mem_q1 = mem_q[1 * DataWidth - 1 : 0 * DataWidth];
always @ (mem_q1) begin
q1 = mem_q1;
end
assign mem_ra = {address0, address1};
assign mem_ce = {ce0, ce1};
assign mem_we[0] = we0;
assign mem_d = {d0};
assign mem_wa = {address0};
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
`celldefine
module denoise_g3_p1_core (q, ra, ce, clk, d, wa, we);
parameter READ_PORT_COUNT=32'd1;
parameter WRITE_PORT_COUNT=32'd1;
parameter DATA_WIDTH=32'd32;
parameter ADDRESS_WIDTH=32'd8;
parameter WORD_COUNT=32'd225;
output [READ_PORT_COUNT*DATA_WIDTH-1:0] q;
input [READ_PORT_COUNT*ADDRESS_WIDTH-1:0] ra;
input [READ_PORT_COUNT-1:0] ce;
input [WRITE_PORT_COUNT*DATA_WIDTH-1:0] d;
input [WRITE_PORT_COUNT*ADDRESS_WIDTH-1:0] wa;
input [WRITE_PORT_COUNT-1:0] we;
input clk;
integer i,j,k;
reg [DATA_WIDTH-1:0] mem [0:WORD_COUNT-1];
reg [ADDRESS_WIDTH-1:0] rat;
reg [ADDRESS_WIDTH-1:0] rai [READ_PORT_COUNT-1:0];
reg [ADDRESS_WIDTH-1:0] rai_reg [READ_PORT_COUNT-1:0];
reg [READ_PORT_COUNT*DATA_WIDTH-1:0] qi;
reg [DATA_WIDTH-1:0] qt;
reg [DATA_WIDTH-1:0] di [WRITE_PORT_COUNT-1:0];
reg [DATA_WIDTH-1:0] dt;
reg [ADDRESS_WIDTH-1:0] wat;
reg [ADDRESS_WIDTH-1:0] wai [WRITE_PORT_COUNT-1:0];
// Split input data
always @ (d) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<DATA_WIDTH;j=j+1) begin
dt[j]=d[i*DATA_WIDTH+j];
end
di[i]=dt;
end
end
// Split write addresses
always @ (wa) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
wat[j]=wa[i*ADDRESS_WIDTH+j];
end
wai[i]=wat;
end
end
// Write memory
always @ (posedge clk) begin
for (j=0;j<WRITE_PORT_COUNT;j=j+1) begin
if (we[j]) begin
mem[wai[j]] <= di[j];
end
end
end
// Split read addresses
always @ (ra) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
rat[j]=ra[i*ADDRESS_WIDTH+j];
end
rai[i]=rat;
end
end
// guide read addresses using CE
always @ (posedge clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if ( ce[i] ) begin
rai_reg[i] <= rai[i];
end
end
end
// Memory read
always @ (rai_reg[0] or clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if (rai_reg[i] >= WORD_COUNT) begin
qt={DATA_WIDTH {1'b0}};
end else begin
qt=mem[rai_reg[i]];
end
for (j=0;j<DATA_WIDTH;j=j+1) begin
qi[i*DATA_WIDTH+j]=qt[j];
end
end
end
assign q=qi;
endmodule
`endcelldefine
module denoise_g3_p1 (
address0,
ce0,
q0,
we0,
d0,
clk);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd225;
parameter AddressWidth = 32'd8;
input[AddressWidth-1:0] address0;
input ce0;
output[DataWidth-1:0] q0;
input we0;
input[DataWidth-1:0] d0;
input clk;
reg[DataWidth-1:0] q0;
wire[1 * DataWidth - 1:0] mem_q;
wire[DataWidth - 1:0] mem_q0;
wire[1 - 1:0] mem_we;
wire[1 * DataWidth - 1:0] mem_d;
wire[1 * AddressWidth - 1:0] mem_wa;
wire[1 * AddressWidth - 1:0] mem_ra;
wire[1 - 1:0] mem_ce;
denoise_g3_p1_core #(
.READ_PORT_COUNT( 1 ),
.WRITE_PORT_COUNT( 1 ),
.DATA_WIDTH( DataWidth ),
.ADDRESS_WIDTH( AddressWidth ),
.WORD_COUNT( AddressRange ))
core_inst (
.q( mem_q ),
.ra( mem_ra ),
.ce( mem_ce ),
.d( mem_d ),
.wa( mem_wa ),
.we( mem_we ),
.clk( clk ));
assign mem_q0 = mem_q[1 * DataWidth - 1 : 0 * DataWidth];
always @ (mem_q0) begin
q0 = mem_q0;
end
assign mem_ra = {address0};
assign mem_ce = {ce0};
assign mem_we[0] = we0;
assign mem_d = {d0};
assign mem_wa = {address0};
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
`celldefine
module denoise_g3_p2_core (q, ra, ce, clk, d, wa, we);
parameter READ_PORT_COUNT=32'd1;
parameter WRITE_PORT_COUNT=32'd1;
parameter DATA_WIDTH=32'd32;
parameter ADDRESS_WIDTH=32'd8;
parameter WORD_COUNT=32'd225;
output [READ_PORT_COUNT*DATA_WIDTH-1:0] q;
input [READ_PORT_COUNT*ADDRESS_WIDTH-1:0] ra;
input [READ_PORT_COUNT-1:0] ce;
input [WRITE_PORT_COUNT*DATA_WIDTH-1:0] d;
input [WRITE_PORT_COUNT*ADDRESS_WIDTH-1:0] wa;
input [WRITE_PORT_COUNT-1:0] we;
input clk;
integer i,j,k;
reg [DATA_WIDTH-1:0] mem [0:WORD_COUNT-1];
reg [ADDRESS_WIDTH-1:0] rat;
reg [ADDRESS_WIDTH-1:0] rai [READ_PORT_COUNT-1:0];
reg [ADDRESS_WIDTH-1:0] rai_reg [READ_PORT_COUNT-1:0];
reg [READ_PORT_COUNT*DATA_WIDTH-1:0] qi;
reg [DATA_WIDTH-1:0] qt;
reg [DATA_WIDTH-1:0] di [WRITE_PORT_COUNT-1:0];
reg [DATA_WIDTH-1:0] dt;
reg [ADDRESS_WIDTH-1:0] wat;
reg [ADDRESS_WIDTH-1:0] wai [WRITE_PORT_COUNT-1:0];
// Split input data
always @ (d) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<DATA_WIDTH;j=j+1) begin
dt[j]=d[i*DATA_WIDTH+j];
end
di[i]=dt;
end
end
// Split write addresses
always @ (wa) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
wat[j]=wa[i*ADDRESS_WIDTH+j];
end
wai[i]=wat;
end
end
// Write memory
always @ (posedge clk) begin
for (j=0;j<WRITE_PORT_COUNT;j=j+1) begin
if (we[j]) begin
mem[wai[j]] <= di[j];
end
end
end
// Split read addresses
always @ (ra) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
rat[j]=ra[i*ADDRESS_WIDTH+j];
end
rai[i]=rat;
end
end
// guide read addresses using CE
always @ (posedge clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if ( ce[i] ) begin
rai_reg[i] <= rai[i];
end
end
end
// Memory read
always @ (rai_reg[0] or clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if (rai_reg[i] >= WORD_COUNT) begin
qt={DATA_WIDTH {1'b0}};
end else begin
qt=mem[rai_reg[i]];
end
for (j=0;j<DATA_WIDTH;j=j+1) begin
qi[i*DATA_WIDTH+j]=qt[j];
end
end
end
assign q=qi;
endmodule
`endcelldefine
module denoise_g3_p2 (
address0,
ce0,
q0,
we0,
d0,
clk);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd225;
parameter AddressWidth = 32'd8;
input[AddressWidth-1:0] address0;
input ce0;
output[DataWidth-1:0] q0;
input we0;
input[DataWidth-1:0] d0;
input clk;
reg[DataWidth-1:0] q0;
wire[1 * DataWidth - 1:0] mem_q;
wire[DataWidth - 1:0] mem_q0;
wire[1 - 1:0] mem_we;
wire[1 * DataWidth - 1:0] mem_d;
wire[1 * AddressWidth - 1:0] mem_wa;
wire[1 * AddressWidth - 1:0] mem_ra;
wire[1 - 1:0] mem_ce;
denoise_g3_p2_core #(
.READ_PORT_COUNT( 1 ),
.WRITE_PORT_COUNT( 1 ),
.DATA_WIDTH( DataWidth ),
.ADDRESS_WIDTH( AddressWidth ),
.WORD_COUNT( AddressRange ))
core_inst (
.q( mem_q ),
.ra( mem_ra ),
.ce( mem_ce ),
.d( mem_d ),
.wa( mem_wa ),
.we( mem_we ),
.clk( clk ));
assign mem_q0 = mem_q[1 * DataWidth - 1 : 0 * DataWidth];
always @ (mem_q0) begin
q0 = mem_q0;
end
assign mem_ra = {address0};
assign mem_ce = {ce0};
assign mem_we[0] = we0;
assign mem_d = {d0};
assign mem_wa = {address0};
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
`celldefine
module denoise_g3_p3_core (q, ra, ce, clk, d, wa, we);
parameter READ_PORT_COUNT=32'd2;
parameter WRITE_PORT_COUNT=32'd1;
parameter DATA_WIDTH=32'd32;
parameter ADDRESS_WIDTH=32'd8;
parameter WORD_COUNT=32'd225;
output [READ_PORT_COUNT*DATA_WIDTH-1:0] q;
input [READ_PORT_COUNT*ADDRESS_WIDTH-1:0] ra;
input [READ_PORT_COUNT-1:0] ce;
input [WRITE_PORT_COUNT*DATA_WIDTH-1:0] d;
input [WRITE_PORT_COUNT*ADDRESS_WIDTH-1:0] wa;
input [WRITE_PORT_COUNT-1:0] we;
input clk;
integer i,j,k;
reg [DATA_WIDTH-1:0] mem [0:WORD_COUNT-1];
reg [ADDRESS_WIDTH-1:0] rat;
reg [ADDRESS_WIDTH-1:0] rai [READ_PORT_COUNT-1:0];
reg [ADDRESS_WIDTH-1:0] rai_reg [READ_PORT_COUNT-1:0];
reg [READ_PORT_COUNT*DATA_WIDTH-1:0] qi;
reg [DATA_WIDTH-1:0] qt;
reg [DATA_WIDTH-1:0] di [WRITE_PORT_COUNT-1:0];
reg [DATA_WIDTH-1:0] dt;
reg [ADDRESS_WIDTH-1:0] wat;
reg [ADDRESS_WIDTH-1:0] wai [WRITE_PORT_COUNT-1:0];
// Split input data
always @ (d) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<DATA_WIDTH;j=j+1) begin
dt[j]=d[i*DATA_WIDTH+j];
end
di[i]=dt;
end
end
// Split write addresses
always @ (wa) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
wat[j]=wa[i*ADDRESS_WIDTH+j];
end
wai[i]=wat;
end
end
// Write memory
always @ (posedge clk) begin
for (j=0;j<WRITE_PORT_COUNT;j=j+1) begin
if (we[j]) begin
mem[wai[j]] <= di[j];
end
end
end
// Split read addresses
always @ (ra) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
rat[j]=ra[i*ADDRESS_WIDTH+j];
end
rai[i]=rat;
end
end
// guide read addresses using CE
always @ (posedge clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if ( ce[i] ) begin
rai_reg[i] <= rai[i];
end
end
end
// Memory read
always @ (rai_reg[0] or rai_reg[1] or clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if (rai_reg[i] >= WORD_COUNT) begin
qt={DATA_WIDTH {1'b0}};
end else begin
qt=mem[rai_reg[i]];
end
for (j=0;j<DATA_WIDTH;j=j+1) begin
qi[i*DATA_WIDTH+j]=qt[j];
end
end
end
assign q=qi;
endmodule
`endcelldefine
module denoise_g3_p3 (
address0,
ce0,
q0,
we0,
d0,
address1,
ce1,
q1,
clk);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd225;
parameter AddressWidth = 32'd8;
input[AddressWidth-1:0] address0;
input ce0;
output[DataWidth-1:0] q0;
input we0;
input[DataWidth-1:0] d0;
input[AddressWidth-1:0] address1;
input ce1;
output[DataWidth-1:0] q1;
input clk;
reg[DataWidth-1:0] q0;
reg[DataWidth-1:0] q1;
wire[2 * DataWidth - 1:0] mem_q;
wire[DataWidth - 1:0] mem_q0;
wire[DataWidth - 1:0] mem_q1;
wire[1 - 1:0] mem_we;
wire[1 * DataWidth - 1:0] mem_d;
wire[1 * AddressWidth - 1:0] mem_wa;
wire[2 * AddressWidth - 1:0] mem_ra;
wire[2 - 1:0] mem_ce;
denoise_g3_p3_core #(
.READ_PORT_COUNT( 2 ),
.WRITE_PORT_COUNT( 1 ),
.DATA_WIDTH( DataWidth ),
.ADDRESS_WIDTH( AddressWidth ),
.WORD_COUNT( AddressRange ))
core_inst (
.q( mem_q ),
.ra( mem_ra ),
.ce( mem_ce ),
.d( mem_d ),
.wa( mem_wa ),
.we( mem_we ),
.clk( clk ));
assign mem_q0 = mem_q[2 * DataWidth - 1 : 1 * DataWidth];
always @ (mem_q0) begin
q0 = mem_q0;
end
assign mem_q1 = mem_q[1 * DataWidth - 1 : 0 * DataWidth];
always @ (mem_q1) begin
q1 = mem_q1;
end
assign mem_ra = {address0, address1};
assign mem_ce = {ce0, ce1};
assign mem_we[0] = we0;
assign mem_d = {d0};
assign mem_wa = {address0};
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
`celldefine
module denoise_g4_p0_core (q, ra, ce, clk, d, wa, we);
parameter READ_PORT_COUNT=32'd2;
parameter WRITE_PORT_COUNT=32'd1;
parameter DATA_WIDTH=32'd32;
parameter ADDRESS_WIDTH=32'd8;
parameter WORD_COUNT=32'd225;
output [READ_PORT_COUNT*DATA_WIDTH-1:0] q;
input [READ_PORT_COUNT*ADDRESS_WIDTH-1:0] ra;
input [READ_PORT_COUNT-1:0] ce;
input [WRITE_PORT_COUNT*DATA_WIDTH-1:0] d;
input [WRITE_PORT_COUNT*ADDRESS_WIDTH-1:0] wa;
input [WRITE_PORT_COUNT-1:0] we;
input clk;
integer i,j,k;
reg [DATA_WIDTH-1:0] mem [0:WORD_COUNT-1];
reg [ADDRESS_WIDTH-1:0] rat;
reg [ADDRESS_WIDTH-1:0] rai [READ_PORT_COUNT-1:0];
reg [ADDRESS_WIDTH-1:0] rai_reg [READ_PORT_COUNT-1:0];
reg [READ_PORT_COUNT*DATA_WIDTH-1:0] qi;
reg [DATA_WIDTH-1:0] qt;
reg [DATA_WIDTH-1:0] di [WRITE_PORT_COUNT-1:0];
reg [DATA_WIDTH-1:0] dt;
reg [ADDRESS_WIDTH-1:0] wat;
reg [ADDRESS_WIDTH-1:0] wai [WRITE_PORT_COUNT-1:0];
// Split input data
always @ (d) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<DATA_WIDTH;j=j+1) begin
dt[j]=d[i*DATA_WIDTH+j];
end
di[i]=dt;
end
end
// Split write addresses
always @ (wa) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
wat[j]=wa[i*ADDRESS_WIDTH+j];
end
wai[i]=wat;
end
end
// Write memory
always @ (posedge clk) begin
for (j=0;j<WRITE_PORT_COUNT;j=j+1) begin
if (we[j]) begin
mem[wai[j]] <= di[j];
end
end
end
// Split read addresses
always @ (ra) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
rat[j]=ra[i*ADDRESS_WIDTH+j];
end
rai[i]=rat;
end
end
// guide read addresses using CE
always @ (posedge clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if ( ce[i] ) begin
rai_reg[i] <= rai[i];
end
end
end
// Memory read
always @ (rai_reg[0] or rai_reg[1] or clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if (rai_reg[i] >= WORD_COUNT) begin
qt={DATA_WIDTH {1'b0}};
end else begin
qt=mem[rai_reg[i]];
end
for (j=0;j<DATA_WIDTH;j=j+1) begin
qi[i*DATA_WIDTH+j]=qt[j];
end
end
end
assign q=qi;
endmodule
`endcelldefine
module denoise_g4_p0 (
address0,
ce0,
q0,
we0,
d0,
address1,
ce1,
q1,
clk);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd225;
parameter AddressWidth = 32'd8;
input[AddressWidth-1:0] address0;
input ce0;
output[DataWidth-1:0] q0;
input we0;
input[DataWidth-1:0] d0;
input[AddressWidth-1:0] address1;
input ce1;
output[DataWidth-1:0] q1;
input clk;
reg[DataWidth-1:0] q0;
reg[DataWidth-1:0] q1;
wire[2 * DataWidth - 1:0] mem_q;
wire[DataWidth - 1:0] mem_q0;
wire[DataWidth - 1:0] mem_q1;
wire[1 - 1:0] mem_we;
wire[1 * DataWidth - 1:0] mem_d;
wire[1 * AddressWidth - 1:0] mem_wa;
wire[2 * AddressWidth - 1:0] mem_ra;
wire[2 - 1:0] mem_ce;
denoise_g4_p0_core #(
.READ_PORT_COUNT( 2 ),
.WRITE_PORT_COUNT( 1 ),
.DATA_WIDTH( DataWidth ),
.ADDRESS_WIDTH( AddressWidth ),
.WORD_COUNT( AddressRange ))
core_inst (
.q( mem_q ),
.ra( mem_ra ),
.ce( mem_ce ),
.d( mem_d ),
.wa( mem_wa ),
.we( mem_we ),
.clk( clk ));
assign mem_q0 = mem_q[2 * DataWidth - 1 : 1 * DataWidth];
always @ (mem_q0) begin
q0 = mem_q0;
end
assign mem_q1 = mem_q[1 * DataWidth - 1 : 0 * DataWidth];
always @ (mem_q1) begin
q1 = mem_q1;
end
assign mem_ra = {address0, address1};
assign mem_ce = {ce0, ce1};
assign mem_we[0] = we0;
assign mem_d = {d0};
assign mem_wa = {address0};
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
`celldefine
module denoise_g4_p1_core (q, ra, ce, clk, d, wa, we);
parameter READ_PORT_COUNT=32'd1;
parameter WRITE_PORT_COUNT=32'd1;
parameter DATA_WIDTH=32'd32;
parameter ADDRESS_WIDTH=32'd8;
parameter WORD_COUNT=32'd225;
output [READ_PORT_COUNT*DATA_WIDTH-1:0] q;
input [READ_PORT_COUNT*ADDRESS_WIDTH-1:0] ra;
input [READ_PORT_COUNT-1:0] ce;
input [WRITE_PORT_COUNT*DATA_WIDTH-1:0] d;
input [WRITE_PORT_COUNT*ADDRESS_WIDTH-1:0] wa;
input [WRITE_PORT_COUNT-1:0] we;
input clk;
integer i,j,k;
reg [DATA_WIDTH-1:0] mem [0:WORD_COUNT-1];
reg [ADDRESS_WIDTH-1:0] rat;
reg [ADDRESS_WIDTH-1:0] rai [READ_PORT_COUNT-1:0];
reg [ADDRESS_WIDTH-1:0] rai_reg [READ_PORT_COUNT-1:0];
reg [READ_PORT_COUNT*DATA_WIDTH-1:0] qi;
reg [DATA_WIDTH-1:0] qt;
reg [DATA_WIDTH-1:0] di [WRITE_PORT_COUNT-1:0];
reg [DATA_WIDTH-1:0] dt;
reg [ADDRESS_WIDTH-1:0] wat;
reg [ADDRESS_WIDTH-1:0] wai [WRITE_PORT_COUNT-1:0];
// Split input data
always @ (d) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<DATA_WIDTH;j=j+1) begin
dt[j]=d[i*DATA_WIDTH+j];
end
di[i]=dt;
end
end
// Split write addresses
always @ (wa) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
wat[j]=wa[i*ADDRESS_WIDTH+j];
end
wai[i]=wat;
end
end
// Write memory
always @ (posedge clk) begin
for (j=0;j<WRITE_PORT_COUNT;j=j+1) begin
if (we[j]) begin
mem[wai[j]] <= di[j];
end
end
end
// Split read addresses
always @ (ra) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
rat[j]=ra[i*ADDRESS_WIDTH+j];
end
rai[i]=rat;
end
end
// guide read addresses using CE
always @ (posedge clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if ( ce[i] ) begin
rai_reg[i] <= rai[i];
end
end
end
// Memory read
always @ (rai_reg[0] or clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if (rai_reg[i] >= WORD_COUNT) begin
qt={DATA_WIDTH {1'b0}};
end else begin
qt=mem[rai_reg[i]];
end
for (j=0;j<DATA_WIDTH;j=j+1) begin
qi[i*DATA_WIDTH+j]=qt[j];
end
end
end
assign q=qi;
endmodule
`endcelldefine
module denoise_g4_p1 (
address0,
ce0,
q0,
we0,
d0,
clk);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd225;
parameter AddressWidth = 32'd8;
input[AddressWidth-1:0] address0;
input ce0;
output[DataWidth-1:0] q0;
input we0;
input[DataWidth-1:0] d0;
input clk;
reg[DataWidth-1:0] q0;
wire[1 * DataWidth - 1:0] mem_q;
wire[DataWidth - 1:0] mem_q0;
wire[1 - 1:0] mem_we;
wire[1 * DataWidth - 1:0] mem_d;
wire[1 * AddressWidth - 1:0] mem_wa;
wire[1 * AddressWidth - 1:0] mem_ra;
wire[1 - 1:0] mem_ce;
denoise_g4_p1_core #(
.READ_PORT_COUNT( 1 ),
.WRITE_PORT_COUNT( 1 ),
.DATA_WIDTH( DataWidth ),
.ADDRESS_WIDTH( AddressWidth ),
.WORD_COUNT( AddressRange ))
core_inst (
.q( mem_q ),
.ra( mem_ra ),
.ce( mem_ce ),
.d( mem_d ),
.wa( mem_wa ),
.we( mem_we ),
.clk( clk ));
assign mem_q0 = mem_q[1 * DataWidth - 1 : 0 * DataWidth];
always @ (mem_q0) begin
q0 = mem_q0;
end
assign mem_ra = {address0};
assign mem_ce = {ce0};
assign mem_we[0] = we0;
assign mem_d = {d0};
assign mem_wa = {address0};
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
`celldefine
module denoise_g4_p2_core (q, ra, ce, clk, d, wa, we);
parameter READ_PORT_COUNT=32'd1;
parameter WRITE_PORT_COUNT=32'd1;
parameter DATA_WIDTH=32'd32;
parameter ADDRESS_WIDTH=32'd8;
parameter WORD_COUNT=32'd225;
output [READ_PORT_COUNT*DATA_WIDTH-1:0] q;
input [READ_PORT_COUNT*ADDRESS_WIDTH-1:0] ra;
input [READ_PORT_COUNT-1:0] ce;
input [WRITE_PORT_COUNT*DATA_WIDTH-1:0] d;
input [WRITE_PORT_COUNT*ADDRESS_WIDTH-1:0] wa;
input [WRITE_PORT_COUNT-1:0] we;
input clk;
integer i,j,k;
reg [DATA_WIDTH-1:0] mem [0:WORD_COUNT-1];
reg [ADDRESS_WIDTH-1:0] rat;
reg [ADDRESS_WIDTH-1:0] rai [READ_PORT_COUNT-1:0];
reg [ADDRESS_WIDTH-1:0] rai_reg [READ_PORT_COUNT-1:0];
reg [READ_PORT_COUNT*DATA_WIDTH-1:0] qi;
reg [DATA_WIDTH-1:0] qt;
reg [DATA_WIDTH-1:0] di [WRITE_PORT_COUNT-1:0];
reg [DATA_WIDTH-1:0] dt;
reg [ADDRESS_WIDTH-1:0] wat;
reg [ADDRESS_WIDTH-1:0] wai [WRITE_PORT_COUNT-1:0];
// Split input data
always @ (d) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<DATA_WIDTH;j=j+1) begin
dt[j]=d[i*DATA_WIDTH+j];
end
di[i]=dt;
end
end
// Split write addresses
always @ (wa) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
wat[j]=wa[i*ADDRESS_WIDTH+j];
end
wai[i]=wat;
end
end
// Write memory
always @ (posedge clk) begin
for (j=0;j<WRITE_PORT_COUNT;j=j+1) begin
if (we[j]) begin
mem[wai[j]] <= di[j];
end
end
end
// Split read addresses
always @ (ra) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
rat[j]=ra[i*ADDRESS_WIDTH+j];
end
rai[i]=rat;
end
end
// guide read addresses using CE
always @ (posedge clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if ( ce[i] ) begin
rai_reg[i] <= rai[i];
end
end
end
// Memory read
always @ (rai_reg[0] or clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if (rai_reg[i] >= WORD_COUNT) begin
qt={DATA_WIDTH {1'b0}};
end else begin
qt=mem[rai_reg[i]];
end
for (j=0;j<DATA_WIDTH;j=j+1) begin
qi[i*DATA_WIDTH+j]=qt[j];
end
end
end
assign q=qi;
endmodule
`endcelldefine
module denoise_g4_p2 (
address0,
ce0,
q0,
we0,
d0,
clk);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd225;
parameter AddressWidth = 32'd8;
input[AddressWidth-1:0] address0;
input ce0;
output[DataWidth-1:0] q0;
input we0;
input[DataWidth-1:0] d0;
input clk;
reg[DataWidth-1:0] q0;
wire[1 * DataWidth - 1:0] mem_q;
wire[DataWidth - 1:0] mem_q0;
wire[1 - 1:0] mem_we;
wire[1 * DataWidth - 1:0] mem_d;
wire[1 * AddressWidth - 1:0] mem_wa;
wire[1 * AddressWidth - 1:0] mem_ra;
wire[1 - 1:0] mem_ce;
denoise_g4_p2_core #(
.READ_PORT_COUNT( 1 ),
.WRITE_PORT_COUNT( 1 ),
.DATA_WIDTH( DataWidth ),
.ADDRESS_WIDTH( AddressWidth ),
.WORD_COUNT( AddressRange ))
core_inst (
.q( mem_q ),
.ra( mem_ra ),
.ce( mem_ce ),
.d( mem_d ),
.wa( mem_wa ),
.we( mem_we ),
.clk( clk ));
assign mem_q0 = mem_q[1 * DataWidth - 1 : 0 * DataWidth];
always @ (mem_q0) begin
q0 = mem_q0;
end
assign mem_ra = {address0};
assign mem_ce = {ce0};
assign mem_we[0] = we0;
assign mem_d = {d0};
assign mem_wa = {address0};
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
`celldefine
module denoise_g4_p3_core (q, ra, ce, clk, d, wa, we);
parameter READ_PORT_COUNT=32'd2;
parameter WRITE_PORT_COUNT=32'd1;
parameter DATA_WIDTH=32'd32;
parameter ADDRESS_WIDTH=32'd8;
parameter WORD_COUNT=32'd225;
output [READ_PORT_COUNT*DATA_WIDTH-1:0] q;
input [READ_PORT_COUNT*ADDRESS_WIDTH-1:0] ra;
input [READ_PORT_COUNT-1:0] ce;
input [WRITE_PORT_COUNT*DATA_WIDTH-1:0] d;
input [WRITE_PORT_COUNT*ADDRESS_WIDTH-1:0] wa;
input [WRITE_PORT_COUNT-1:0] we;
input clk;
integer i,j,k;
reg [DATA_WIDTH-1:0] mem [0:WORD_COUNT-1];
reg [ADDRESS_WIDTH-1:0] rat;
reg [ADDRESS_WIDTH-1:0] rai [READ_PORT_COUNT-1:0];
reg [ADDRESS_WIDTH-1:0] rai_reg [READ_PORT_COUNT-1:0];
reg [READ_PORT_COUNT*DATA_WIDTH-1:0] qi;
reg [DATA_WIDTH-1:0] qt;
reg [DATA_WIDTH-1:0] di [WRITE_PORT_COUNT-1:0];
reg [DATA_WIDTH-1:0] dt;
reg [ADDRESS_WIDTH-1:0] wat;
reg [ADDRESS_WIDTH-1:0] wai [WRITE_PORT_COUNT-1:0];
// Split input data
always @ (d) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<DATA_WIDTH;j=j+1) begin
dt[j]=d[i*DATA_WIDTH+j];
end
di[i]=dt;
end
end
// Split write addresses
always @ (wa) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
wat[j]=wa[i*ADDRESS_WIDTH+j];
end
wai[i]=wat;
end
end
// Write memory
always @ (posedge clk) begin
for (j=0;j<WRITE_PORT_COUNT;j=j+1) begin
if (we[j]) begin
mem[wai[j]] <= di[j];
end
end
end
// Split read addresses
always @ (ra) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
rat[j]=ra[i*ADDRESS_WIDTH+j];
end
rai[i]=rat;
end
end
// guide read addresses using CE
always @ (posedge clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if ( ce[i] ) begin
rai_reg[i] <= rai[i];
end
end
end
// Memory read
always @ (rai_reg[0] or rai_reg[1] or clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if (rai_reg[i] >= WORD_COUNT) begin
qt={DATA_WIDTH {1'b0}};
end else begin
qt=mem[rai_reg[i]];
end
for (j=0;j<DATA_WIDTH;j=j+1) begin
qi[i*DATA_WIDTH+j]=qt[j];
end
end
end
assign q=qi;
endmodule
`endcelldefine
module denoise_g4_p3 (
address0,
ce0,
q0,
we0,
d0,
address1,
ce1,
q1,
clk);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd225;
parameter AddressWidth = 32'd8;
input[AddressWidth-1:0] address0;
input ce0;
output[DataWidth-1:0] q0;
input we0;
input[DataWidth-1:0] d0;
input[AddressWidth-1:0] address1;
input ce1;
output[DataWidth-1:0] q1;
input clk;
reg[DataWidth-1:0] q0;
reg[DataWidth-1:0] q1;
wire[2 * DataWidth - 1:0] mem_q;
wire[DataWidth - 1:0] mem_q0;
wire[DataWidth - 1:0] mem_q1;
wire[1 - 1:0] mem_we;
wire[1 * DataWidth - 1:0] mem_d;
wire[1 * AddressWidth - 1:0] mem_wa;
wire[2 * AddressWidth - 1:0] mem_ra;
wire[2 - 1:0] mem_ce;
denoise_g4_p3_core #(
.READ_PORT_COUNT( 2 ),
.WRITE_PORT_COUNT( 1 ),
.DATA_WIDTH( DataWidth ),
.ADDRESS_WIDTH( AddressWidth ),
.WORD_COUNT( AddressRange ))
core_inst (
.q( mem_q ),
.ra( mem_ra ),
.ce( mem_ce ),
.d( mem_d ),
.wa( mem_wa ),
.we( mem_we ),
.clk( clk ));
assign mem_q0 = mem_q[2 * DataWidth - 1 : 1 * DataWidth];
always @ (mem_q0) begin
q0 = mem_q0;
end
assign mem_q1 = mem_q[1 * DataWidth - 1 : 0 * DataWidth];
always @ (mem_q1) begin
q1 = mem_q1;
end
assign mem_ra = {address0, address1};
assign mem_ce = {ce0, ce1};
assign mem_we[0] = we0;
assign mem_d = {d0};
assign mem_wa = {address0};
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
`celldefine
module denoise_r0_p0_core (q, ra, ce, clk, d, wa, we);
parameter READ_PORT_COUNT=32'd1;
parameter WRITE_PORT_COUNT=32'd1;
parameter DATA_WIDTH=32'd32;
parameter ADDRESS_WIDTH=32'd8;
parameter WORD_COUNT=32'd225;
output [READ_PORT_COUNT*DATA_WIDTH-1:0] q;
input [READ_PORT_COUNT*ADDRESS_WIDTH-1:0] ra;
input [READ_PORT_COUNT-1:0] ce;
input [WRITE_PORT_COUNT*DATA_WIDTH-1:0] d;
input [WRITE_PORT_COUNT*ADDRESS_WIDTH-1:0] wa;
input [WRITE_PORT_COUNT-1:0] we;
input clk;
integer i,j,k;
reg [DATA_WIDTH-1:0] mem [0:WORD_COUNT-1];
reg [ADDRESS_WIDTH-1:0] rat;
reg [ADDRESS_WIDTH-1:0] rai [READ_PORT_COUNT-1:0];
reg [ADDRESS_WIDTH-1:0] rai_reg [READ_PORT_COUNT-1:0];
reg [READ_PORT_COUNT*DATA_WIDTH-1:0] qi;
reg [DATA_WIDTH-1:0] qt;
reg [DATA_WIDTH-1:0] di [WRITE_PORT_COUNT-1:0];
reg [DATA_WIDTH-1:0] dt;
reg [ADDRESS_WIDTH-1:0] wat;
reg [ADDRESS_WIDTH-1:0] wai [WRITE_PORT_COUNT-1:0];
// Split input data
always @ (d) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<DATA_WIDTH;j=j+1) begin
dt[j]=d[i*DATA_WIDTH+j];
end
di[i]=dt;
end
end
// Split write addresses
always @ (wa) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
wat[j]=wa[i*ADDRESS_WIDTH+j];
end
wai[i]=wat;
end
end
// Write memory
always @ (posedge clk) begin
for (j=0;j<WRITE_PORT_COUNT;j=j+1) begin
if (we[j]) begin
mem[wai[j]] <= di[j];
end
end
end
// Split read addresses
always @ (ra) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
rat[j]=ra[i*ADDRESS_WIDTH+j];
end
rai[i]=rat;
end
end
// guide read addresses using CE
always @ (posedge clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if ( ce[i] ) begin
rai_reg[i] <= rai[i];
end
end
end
// Memory read
always @ (rai_reg[0] or clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if (rai_reg[i] >= WORD_COUNT) begin
qt={DATA_WIDTH {1'b0}};
end else begin
qt=mem[rai_reg[i]];
end
for (j=0;j<DATA_WIDTH;j=j+1) begin
qi[i*DATA_WIDTH+j]=qt[j];
end
end
end
assign q=qi;
endmodule
`endcelldefine
module denoise_r0_p0 (
address0,
ce0,
q0,
we0,
d0,
clk);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd225;
parameter AddressWidth = 32'd8;
input[AddressWidth-1:0] address0;
input ce0;
output[DataWidth-1:0] q0;
input we0;
input[DataWidth-1:0] d0;
input clk;
reg[DataWidth-1:0] q0;
wire[1 * DataWidth - 1:0] mem_q;
wire[DataWidth - 1:0] mem_q0;
wire[1 - 1:0] mem_we;
wire[1 * DataWidth - 1:0] mem_d;
wire[1 * AddressWidth - 1:0] mem_wa;
wire[1 * AddressWidth - 1:0] mem_ra;
wire[1 - 1:0] mem_ce;
denoise_r0_p0_core #(
.READ_PORT_COUNT( 1 ),
.WRITE_PORT_COUNT( 1 ),
.DATA_WIDTH( DataWidth ),
.ADDRESS_WIDTH( AddressWidth ),
.WORD_COUNT( AddressRange ))
core_inst (
.q( mem_q ),
.ra( mem_ra ),
.ce( mem_ce ),
.d( mem_d ),
.wa( mem_wa ),
.we( mem_we ),
.clk( clk ));
assign mem_q0 = mem_q[1 * DataWidth - 1 : 0 * DataWidth];
always @ (mem_q0) begin
q0 = mem_q0;
end
assign mem_ra = {address0};
assign mem_ce = {ce0};
assign mem_we[0] = we0;
assign mem_d = {d0};
assign mem_wa = {address0};
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
`celldefine
module denoise_r0_p1_core (q, ra, ce, clk, d, wa, we);
parameter READ_PORT_COUNT=32'd1;
parameter WRITE_PORT_COUNT=32'd1;
parameter DATA_WIDTH=32'd32;
parameter ADDRESS_WIDTH=32'd8;
parameter WORD_COUNT=32'd225;
output [READ_PORT_COUNT*DATA_WIDTH-1:0] q;
input [READ_PORT_COUNT*ADDRESS_WIDTH-1:0] ra;
input [READ_PORT_COUNT-1:0] ce;
input [WRITE_PORT_COUNT*DATA_WIDTH-1:0] d;
input [WRITE_PORT_COUNT*ADDRESS_WIDTH-1:0] wa;
input [WRITE_PORT_COUNT-1:0] we;
input clk;
integer i,j,k;
reg [DATA_WIDTH-1:0] mem [0:WORD_COUNT-1];
reg [ADDRESS_WIDTH-1:0] rat;
reg [ADDRESS_WIDTH-1:0] rai [READ_PORT_COUNT-1:0];
reg [ADDRESS_WIDTH-1:0] rai_reg [READ_PORT_COUNT-1:0];
reg [READ_PORT_COUNT*DATA_WIDTH-1:0] qi;
reg [DATA_WIDTH-1:0] qt;
reg [DATA_WIDTH-1:0] di [WRITE_PORT_COUNT-1:0];
reg [DATA_WIDTH-1:0] dt;
reg [ADDRESS_WIDTH-1:0] wat;
reg [ADDRESS_WIDTH-1:0] wai [WRITE_PORT_COUNT-1:0];
// Split input data
always @ (d) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<DATA_WIDTH;j=j+1) begin
dt[j]=d[i*DATA_WIDTH+j];
end
di[i]=dt;
end
end
// Split write addresses
always @ (wa) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
wat[j]=wa[i*ADDRESS_WIDTH+j];
end
wai[i]=wat;
end
end
// Write memory
always @ (posedge clk) begin
for (j=0;j<WRITE_PORT_COUNT;j=j+1) begin
if (we[j]) begin
mem[wai[j]] <= di[j];
end
end
end
// Split read addresses
always @ (ra) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
rat[j]=ra[i*ADDRESS_WIDTH+j];
end
rai[i]=rat;
end
end
// guide read addresses using CE
always @ (posedge clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if ( ce[i] ) begin
rai_reg[i] <= rai[i];
end
end
end
// Memory read
always @ (rai_reg[0] or clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if (rai_reg[i] >= WORD_COUNT) begin
qt={DATA_WIDTH {1'b0}};
end else begin
qt=mem[rai_reg[i]];
end
for (j=0;j<DATA_WIDTH;j=j+1) begin
qi[i*DATA_WIDTH+j]=qt[j];
end
end
end
assign q=qi;
endmodule
`endcelldefine
module denoise_r0_p1 (
address0,
ce0,
q0,
we0,
d0,
clk);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd225;
parameter AddressWidth = 32'd8;
input[AddressWidth-1:0] address0;
input ce0;
output[DataWidth-1:0] q0;
input we0;
input[DataWidth-1:0] d0;
input clk;
reg[DataWidth-1:0] q0;
wire[1 * DataWidth - 1:0] mem_q;
wire[DataWidth - 1:0] mem_q0;
wire[1 - 1:0] mem_we;
wire[1 * DataWidth - 1:0] mem_d;
wire[1 * AddressWidth - 1:0] mem_wa;
wire[1 * AddressWidth - 1:0] mem_ra;
wire[1 - 1:0] mem_ce;
denoise_r0_p1_core #(
.READ_PORT_COUNT( 1 ),
.WRITE_PORT_COUNT( 1 ),
.DATA_WIDTH( DataWidth ),
.ADDRESS_WIDTH( AddressWidth ),
.WORD_COUNT( AddressRange ))
core_inst (
.q( mem_q ),
.ra( mem_ra ),
.ce( mem_ce ),
.d( mem_d ),
.wa( mem_wa ),
.we( mem_we ),
.clk( clk ));
assign mem_q0 = mem_q[1 * DataWidth - 1 : 0 * DataWidth];
always @ (mem_q0) begin
q0 = mem_q0;
end
assign mem_ra = {address0};
assign mem_ce = {ce0};
assign mem_we[0] = we0;
assign mem_d = {d0};
assign mem_wa = {address0};
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
`celldefine
module denoise_r0_p2_core (q, ra, ce, clk, d, wa, we);
parameter READ_PORT_COUNT=32'd1;
parameter WRITE_PORT_COUNT=32'd1;
parameter DATA_WIDTH=32'd32;
parameter ADDRESS_WIDTH=32'd8;
parameter WORD_COUNT=32'd225;
output [READ_PORT_COUNT*DATA_WIDTH-1:0] q;
input [READ_PORT_COUNT*ADDRESS_WIDTH-1:0] ra;
input [READ_PORT_COUNT-1:0] ce;
input [WRITE_PORT_COUNT*DATA_WIDTH-1:0] d;
input [WRITE_PORT_COUNT*ADDRESS_WIDTH-1:0] wa;
input [WRITE_PORT_COUNT-1:0] we;
input clk;
integer i,j,k;
reg [DATA_WIDTH-1:0] mem [0:WORD_COUNT-1];
reg [ADDRESS_WIDTH-1:0] rat;
reg [ADDRESS_WIDTH-1:0] rai [READ_PORT_COUNT-1:0];
reg [ADDRESS_WIDTH-1:0] rai_reg [READ_PORT_COUNT-1:0];
reg [READ_PORT_COUNT*DATA_WIDTH-1:0] qi;
reg [DATA_WIDTH-1:0] qt;
reg [DATA_WIDTH-1:0] di [WRITE_PORT_COUNT-1:0];
reg [DATA_WIDTH-1:0] dt;
reg [ADDRESS_WIDTH-1:0] wat;
reg [ADDRESS_WIDTH-1:0] wai [WRITE_PORT_COUNT-1:0];
// Split input data
always @ (d) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<DATA_WIDTH;j=j+1) begin
dt[j]=d[i*DATA_WIDTH+j];
end
di[i]=dt;
end
end
// Split write addresses
always @ (wa) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
wat[j]=wa[i*ADDRESS_WIDTH+j];
end
wai[i]=wat;
end
end
// Write memory
always @ (posedge clk) begin
for (j=0;j<WRITE_PORT_COUNT;j=j+1) begin
if (we[j]) begin
mem[wai[j]] <= di[j];
end
end
end
// Split read addresses
always @ (ra) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
rat[j]=ra[i*ADDRESS_WIDTH+j];
end
rai[i]=rat;
end
end
// guide read addresses using CE
always @ (posedge clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if ( ce[i] ) begin
rai_reg[i] <= rai[i];
end
end
end
// Memory read
always @ (rai_reg[0] or clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if (rai_reg[i] >= WORD_COUNT) begin
qt={DATA_WIDTH {1'b0}};
end else begin
qt=mem[rai_reg[i]];
end
for (j=0;j<DATA_WIDTH;j=j+1) begin
qi[i*DATA_WIDTH+j]=qt[j];
end
end
end
assign q=qi;
endmodule
`endcelldefine
module denoise_r0_p2 (
address0,
ce0,
q0,
we0,
d0,
clk);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd225;
parameter AddressWidth = 32'd8;
input[AddressWidth-1:0] address0;
input ce0;
output[DataWidth-1:0] q0;
input we0;
input[DataWidth-1:0] d0;
input clk;
reg[DataWidth-1:0] q0;
wire[1 * DataWidth - 1:0] mem_q;
wire[DataWidth - 1:0] mem_q0;
wire[1 - 1:0] mem_we;
wire[1 * DataWidth - 1:0] mem_d;
wire[1 * AddressWidth - 1:0] mem_wa;
wire[1 * AddressWidth - 1:0] mem_ra;
wire[1 - 1:0] mem_ce;
denoise_r0_p2_core #(
.READ_PORT_COUNT( 1 ),
.WRITE_PORT_COUNT( 1 ),
.DATA_WIDTH( DataWidth ),
.ADDRESS_WIDTH( AddressWidth ),
.WORD_COUNT( AddressRange ))
core_inst (
.q( mem_q ),
.ra( mem_ra ),
.ce( mem_ce ),
.d( mem_d ),
.wa( mem_wa ),
.we( mem_we ),
.clk( clk ));
assign mem_q0 = mem_q[1 * DataWidth - 1 : 0 * DataWidth];
always @ (mem_q0) begin
q0 = mem_q0;
end
assign mem_ra = {address0};
assign mem_ce = {ce0};
assign mem_we[0] = we0;
assign mem_d = {d0};
assign mem_wa = {address0};
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
`celldefine
module denoise_r0_p3_core (q, ra, ce, clk, d, wa, we);
parameter READ_PORT_COUNT=32'd1;
parameter WRITE_PORT_COUNT=32'd1;
parameter DATA_WIDTH=32'd32;
parameter ADDRESS_WIDTH=32'd8;
parameter WORD_COUNT=32'd225;
output [READ_PORT_COUNT*DATA_WIDTH-1:0] q;
input [READ_PORT_COUNT*ADDRESS_WIDTH-1:0] ra;
input [READ_PORT_COUNT-1:0] ce;
input [WRITE_PORT_COUNT*DATA_WIDTH-1:0] d;
input [WRITE_PORT_COUNT*ADDRESS_WIDTH-1:0] wa;
input [WRITE_PORT_COUNT-1:0] we;
input clk;
integer i,j,k;
reg [DATA_WIDTH-1:0] mem [0:WORD_COUNT-1];
reg [ADDRESS_WIDTH-1:0] rat;
reg [ADDRESS_WIDTH-1:0] rai [READ_PORT_COUNT-1:0];
reg [ADDRESS_WIDTH-1:0] rai_reg [READ_PORT_COUNT-1:0];
reg [READ_PORT_COUNT*DATA_WIDTH-1:0] qi;
reg [DATA_WIDTH-1:0] qt;
reg [DATA_WIDTH-1:0] di [WRITE_PORT_COUNT-1:0];
reg [DATA_WIDTH-1:0] dt;
reg [ADDRESS_WIDTH-1:0] wat;
reg [ADDRESS_WIDTH-1:0] wai [WRITE_PORT_COUNT-1:0];
// Split input data
always @ (d) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<DATA_WIDTH;j=j+1) begin
dt[j]=d[i*DATA_WIDTH+j];
end
di[i]=dt;
end
end
// Split write addresses
always @ (wa) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
wat[j]=wa[i*ADDRESS_WIDTH+j];
end
wai[i]=wat;
end
end
// Write memory
always @ (posedge clk) begin
for (j=0;j<WRITE_PORT_COUNT;j=j+1) begin
if (we[j]) begin
mem[wai[j]] <= di[j];
end
end
end
// Split read addresses
always @ (ra) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
rat[j]=ra[i*ADDRESS_WIDTH+j];
end
rai[i]=rat;
end
end
// guide read addresses using CE
always @ (posedge clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if ( ce[i] ) begin
rai_reg[i] <= rai[i];
end
end
end
// Memory read
always @ (rai_reg[0] or clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if (rai_reg[i] >= WORD_COUNT) begin
qt={DATA_WIDTH {1'b0}};
end else begin
qt=mem[rai_reg[i]];
end
for (j=0;j<DATA_WIDTH;j=j+1) begin
qi[i*DATA_WIDTH+j]=qt[j];
end
end
end
assign q=qi;
endmodule
`endcelldefine
module denoise_r0_p3 (
address0,
ce0,
q0,
we0,
d0,
clk);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd225;
parameter AddressWidth = 32'd8;
input[AddressWidth-1:0] address0;
input ce0;
output[DataWidth-1:0] q0;
input we0;
input[DataWidth-1:0] d0;
input clk;
reg[DataWidth-1:0] q0;
wire[1 * DataWidth - 1:0] mem_q;
wire[DataWidth - 1:0] mem_q0;
wire[1 - 1:0] mem_we;
wire[1 * DataWidth - 1:0] mem_d;
wire[1 * AddressWidth - 1:0] mem_wa;
wire[1 * AddressWidth - 1:0] mem_ra;
wire[1 - 1:0] mem_ce;
denoise_r0_p3_core #(
.READ_PORT_COUNT( 1 ),
.WRITE_PORT_COUNT( 1 ),
.DATA_WIDTH( DataWidth ),
.ADDRESS_WIDTH( AddressWidth ),
.WORD_COUNT( AddressRange ))
core_inst (
.q( mem_q ),
.ra( mem_ra ),
.ce( mem_ce ),
.d( mem_d ),
.wa( mem_wa ),
.we( mem_we ),
.clk( clk ));
assign mem_q0 = mem_q[1 * DataWidth - 1 : 0 * DataWidth];
always @ (mem_q0) begin
q0 = mem_q0;
end
assign mem_ra = {address0};
assign mem_ce = {ce0};
assign mem_we[0] = we0;
assign mem_d = {d0};
assign mem_wa = {address0};
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
`celldefine
module denoise_r1_p0_core (q, ra, ce, clk, d, wa, we);
parameter READ_PORT_COUNT=32'd1;
parameter WRITE_PORT_COUNT=32'd1;
parameter DATA_WIDTH=32'd32;
parameter ADDRESS_WIDTH=32'd8;
parameter WORD_COUNT=32'd225;
output [READ_PORT_COUNT*DATA_WIDTH-1:0] q;
input [READ_PORT_COUNT*ADDRESS_WIDTH-1:0] ra;
input [READ_PORT_COUNT-1:0] ce;
input [WRITE_PORT_COUNT*DATA_WIDTH-1:0] d;
input [WRITE_PORT_COUNT*ADDRESS_WIDTH-1:0] wa;
input [WRITE_PORT_COUNT-1:0] we;
input clk;
integer i,j,k;
reg [DATA_WIDTH-1:0] mem [0:WORD_COUNT-1];
reg [ADDRESS_WIDTH-1:0] rat;
reg [ADDRESS_WIDTH-1:0] rai [READ_PORT_COUNT-1:0];
reg [ADDRESS_WIDTH-1:0] rai_reg [READ_PORT_COUNT-1:0];
reg [READ_PORT_COUNT*DATA_WIDTH-1:0] qi;
reg [DATA_WIDTH-1:0] qt;
reg [DATA_WIDTH-1:0] di [WRITE_PORT_COUNT-1:0];
reg [DATA_WIDTH-1:0] dt;
reg [ADDRESS_WIDTH-1:0] wat;
reg [ADDRESS_WIDTH-1:0] wai [WRITE_PORT_COUNT-1:0];
// Split input data
always @ (d) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<DATA_WIDTH;j=j+1) begin
dt[j]=d[i*DATA_WIDTH+j];
end
di[i]=dt;
end
end
// Split write addresses
always @ (wa) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
wat[j]=wa[i*ADDRESS_WIDTH+j];
end
wai[i]=wat;
end
end
// Write memory
always @ (posedge clk) begin
for (j=0;j<WRITE_PORT_COUNT;j=j+1) begin
if (we[j]) begin
mem[wai[j]] <= di[j];
end
end
end
// Split read addresses
always @ (ra) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
rat[j]=ra[i*ADDRESS_WIDTH+j];
end
rai[i]=rat;
end
end
// guide read addresses using CE
always @ (posedge clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if ( ce[i] ) begin
rai_reg[i] <= rai[i];
end
end
end
// Memory read
always @ (rai_reg[0] or clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if (rai_reg[i] >= WORD_COUNT) begin
qt={DATA_WIDTH {1'b0}};
end else begin
qt=mem[rai_reg[i]];
end
for (j=0;j<DATA_WIDTH;j=j+1) begin
qi[i*DATA_WIDTH+j]=qt[j];
end
end
end
assign q=qi;
endmodule
`endcelldefine
module denoise_r1_p0 (
address0,
ce0,
q0,
we0,
d0,
clk);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd225;
parameter AddressWidth = 32'd8;
input[AddressWidth-1:0] address0;
input ce0;
output[DataWidth-1:0] q0;
input we0;
input[DataWidth-1:0] d0;
input clk;
reg[DataWidth-1:0] q0;
wire[1 * DataWidth - 1:0] mem_q;
wire[DataWidth - 1:0] mem_q0;
wire[1 - 1:0] mem_we;
wire[1 * DataWidth - 1:0] mem_d;
wire[1 * AddressWidth - 1:0] mem_wa;
wire[1 * AddressWidth - 1:0] mem_ra;
wire[1 - 1:0] mem_ce;
denoise_r1_p0_core #(
.READ_PORT_COUNT( 1 ),
.WRITE_PORT_COUNT( 1 ),
.DATA_WIDTH( DataWidth ),
.ADDRESS_WIDTH( AddressWidth ),
.WORD_COUNT( AddressRange ))
core_inst (
.q( mem_q ),
.ra( mem_ra ),
.ce( mem_ce ),
.d( mem_d ),
.wa( mem_wa ),
.we( mem_we ),
.clk( clk ));
assign mem_q0 = mem_q[1 * DataWidth - 1 : 0 * DataWidth];
always @ (mem_q0) begin
q0 = mem_q0;
end
assign mem_ra = {address0};
assign mem_ce = {ce0};
assign mem_we[0] = we0;
assign mem_d = {d0};
assign mem_wa = {address0};
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
`celldefine
module denoise_r1_p1_core (q, ra, ce, clk, d, wa, we);
parameter READ_PORT_COUNT=32'd1;
parameter WRITE_PORT_COUNT=32'd1;
parameter DATA_WIDTH=32'd32;
parameter ADDRESS_WIDTH=32'd8;
parameter WORD_COUNT=32'd225;
output [READ_PORT_COUNT*DATA_WIDTH-1:0] q;
input [READ_PORT_COUNT*ADDRESS_WIDTH-1:0] ra;
input [READ_PORT_COUNT-1:0] ce;
input [WRITE_PORT_COUNT*DATA_WIDTH-1:0] d;
input [WRITE_PORT_COUNT*ADDRESS_WIDTH-1:0] wa;
input [WRITE_PORT_COUNT-1:0] we;
input clk;
integer i,j,k;
reg [DATA_WIDTH-1:0] mem [0:WORD_COUNT-1];
reg [ADDRESS_WIDTH-1:0] rat;
reg [ADDRESS_WIDTH-1:0] rai [READ_PORT_COUNT-1:0];
reg [ADDRESS_WIDTH-1:0] rai_reg [READ_PORT_COUNT-1:0];
reg [READ_PORT_COUNT*DATA_WIDTH-1:0] qi;
reg [DATA_WIDTH-1:0] qt;
reg [DATA_WIDTH-1:0] di [WRITE_PORT_COUNT-1:0];
reg [DATA_WIDTH-1:0] dt;
reg [ADDRESS_WIDTH-1:0] wat;
reg [ADDRESS_WIDTH-1:0] wai [WRITE_PORT_COUNT-1:0];
// Split input data
always @ (d) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<DATA_WIDTH;j=j+1) begin
dt[j]=d[i*DATA_WIDTH+j];
end
di[i]=dt;
end
end
// Split write addresses
always @ (wa) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
wat[j]=wa[i*ADDRESS_WIDTH+j];
end
wai[i]=wat;
end
end
// Write memory
always @ (posedge clk) begin
for (j=0;j<WRITE_PORT_COUNT;j=j+1) begin
if (we[j]) begin
mem[wai[j]] <= di[j];
end
end
end
// Split read addresses
always @ (ra) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
rat[j]=ra[i*ADDRESS_WIDTH+j];
end
rai[i]=rat;
end
end
// guide read addresses using CE
always @ (posedge clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if ( ce[i] ) begin
rai_reg[i] <= rai[i];
end
end
end
// Memory read
always @ (rai_reg[0] or clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if (rai_reg[i] >= WORD_COUNT) begin
qt={DATA_WIDTH {1'b0}};
end else begin
qt=mem[rai_reg[i]];
end
for (j=0;j<DATA_WIDTH;j=j+1) begin
qi[i*DATA_WIDTH+j]=qt[j];
end
end
end
assign q=qi;
endmodule
`endcelldefine
module denoise_r1_p1 (
address0,
ce0,
q0,
we0,
d0,
clk);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd225;
parameter AddressWidth = 32'd8;
input[AddressWidth-1:0] address0;
input ce0;
output[DataWidth-1:0] q0;
input we0;
input[DataWidth-1:0] d0;
input clk;
reg[DataWidth-1:0] q0;
wire[1 * DataWidth - 1:0] mem_q;
wire[DataWidth - 1:0] mem_q0;
wire[1 - 1:0] mem_we;
wire[1 * DataWidth - 1:0] mem_d;
wire[1 * AddressWidth - 1:0] mem_wa;
wire[1 * AddressWidth - 1:0] mem_ra;
wire[1 - 1:0] mem_ce;
denoise_r1_p1_core #(
.READ_PORT_COUNT( 1 ),
.WRITE_PORT_COUNT( 1 ),
.DATA_WIDTH( DataWidth ),
.ADDRESS_WIDTH( AddressWidth ),
.WORD_COUNT( AddressRange ))
core_inst (
.q( mem_q ),
.ra( mem_ra ),
.ce( mem_ce ),
.d( mem_d ),
.wa( mem_wa ),
.we( mem_we ),
.clk( clk ));
assign mem_q0 = mem_q[1 * DataWidth - 1 : 0 * DataWidth];
always @ (mem_q0) begin
q0 = mem_q0;
end
assign mem_ra = {address0};
assign mem_ce = {ce0};
assign mem_we[0] = we0;
assign mem_d = {d0};
assign mem_wa = {address0};
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
`celldefine
module denoise_r1_p2_core (q, ra, ce, clk, d, wa, we);
parameter READ_PORT_COUNT=32'd1;
parameter WRITE_PORT_COUNT=32'd1;
parameter DATA_WIDTH=32'd32;
parameter ADDRESS_WIDTH=32'd8;
parameter WORD_COUNT=32'd225;
output [READ_PORT_COUNT*DATA_WIDTH-1:0] q;
input [READ_PORT_COUNT*ADDRESS_WIDTH-1:0] ra;
input [READ_PORT_COUNT-1:0] ce;
input [WRITE_PORT_COUNT*DATA_WIDTH-1:0] d;
input [WRITE_PORT_COUNT*ADDRESS_WIDTH-1:0] wa;
input [WRITE_PORT_COUNT-1:0] we;
input clk;
integer i,j,k;
reg [DATA_WIDTH-1:0] mem [0:WORD_COUNT-1];
reg [ADDRESS_WIDTH-1:0] rat;
reg [ADDRESS_WIDTH-1:0] rai [READ_PORT_COUNT-1:0];
reg [ADDRESS_WIDTH-1:0] rai_reg [READ_PORT_COUNT-1:0];
reg [READ_PORT_COUNT*DATA_WIDTH-1:0] qi;
reg [DATA_WIDTH-1:0] qt;
reg [DATA_WIDTH-1:0] di [WRITE_PORT_COUNT-1:0];
reg [DATA_WIDTH-1:0] dt;
reg [ADDRESS_WIDTH-1:0] wat;
reg [ADDRESS_WIDTH-1:0] wai [WRITE_PORT_COUNT-1:0];
// Split input data
always @ (d) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<DATA_WIDTH;j=j+1) begin
dt[j]=d[i*DATA_WIDTH+j];
end
di[i]=dt;
end
end
// Split write addresses
always @ (wa) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
wat[j]=wa[i*ADDRESS_WIDTH+j];
end
wai[i]=wat;
end
end
// Write memory
always @ (posedge clk) begin
for (j=0;j<WRITE_PORT_COUNT;j=j+1) begin
if (we[j]) begin
mem[wai[j]] <= di[j];
end
end
end
// Split read addresses
always @ (ra) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
rat[j]=ra[i*ADDRESS_WIDTH+j];
end
rai[i]=rat;
end
end
// guide read addresses using CE
always @ (posedge clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if ( ce[i] ) begin
rai_reg[i] <= rai[i];
end
end
end
// Memory read
always @ (rai_reg[0] or clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if (rai_reg[i] >= WORD_COUNT) begin
qt={DATA_WIDTH {1'b0}};
end else begin
qt=mem[rai_reg[i]];
end
for (j=0;j<DATA_WIDTH;j=j+1) begin
qi[i*DATA_WIDTH+j]=qt[j];
end
end
end
assign q=qi;
endmodule
`endcelldefine
module denoise_r1_p2 (
address0,
ce0,
q0,
we0,
d0,
clk);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd225;
parameter AddressWidth = 32'd8;
input[AddressWidth-1:0] address0;
input ce0;
output[DataWidth-1:0] q0;
input we0;
input[DataWidth-1:0] d0;
input clk;
reg[DataWidth-1:0] q0;
wire[1 * DataWidth - 1:0] mem_q;
wire[DataWidth - 1:0] mem_q0;
wire[1 - 1:0] mem_we;
wire[1 * DataWidth - 1:0] mem_d;
wire[1 * AddressWidth - 1:0] mem_wa;
wire[1 * AddressWidth - 1:0] mem_ra;
wire[1 - 1:0] mem_ce;
denoise_r1_p2_core #(
.READ_PORT_COUNT( 1 ),
.WRITE_PORT_COUNT( 1 ),
.DATA_WIDTH( DataWidth ),
.ADDRESS_WIDTH( AddressWidth ),
.WORD_COUNT( AddressRange ))
core_inst (
.q( mem_q ),
.ra( mem_ra ),
.ce( mem_ce ),
.d( mem_d ),
.wa( mem_wa ),
.we( mem_we ),
.clk( clk ));
assign mem_q0 = mem_q[1 * DataWidth - 1 : 0 * DataWidth];
always @ (mem_q0) begin
q0 = mem_q0;
end
assign mem_ra = {address0};
assign mem_ce = {ce0};
assign mem_we[0] = we0;
assign mem_d = {d0};
assign mem_wa = {address0};
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
`celldefine
module denoise_r1_p3_core (q, ra, ce, clk, d, wa, we);
parameter READ_PORT_COUNT=32'd1;
parameter WRITE_PORT_COUNT=32'd1;
parameter DATA_WIDTH=32'd32;
parameter ADDRESS_WIDTH=32'd8;
parameter WORD_COUNT=32'd225;
output [READ_PORT_COUNT*DATA_WIDTH-1:0] q;
input [READ_PORT_COUNT*ADDRESS_WIDTH-1:0] ra;
input [READ_PORT_COUNT-1:0] ce;
input [WRITE_PORT_COUNT*DATA_WIDTH-1:0] d;
input [WRITE_PORT_COUNT*ADDRESS_WIDTH-1:0] wa;
input [WRITE_PORT_COUNT-1:0] we;
input clk;
integer i,j,k;
reg [DATA_WIDTH-1:0] mem [0:WORD_COUNT-1];
reg [ADDRESS_WIDTH-1:0] rat;
reg [ADDRESS_WIDTH-1:0] rai [READ_PORT_COUNT-1:0];
reg [ADDRESS_WIDTH-1:0] rai_reg [READ_PORT_COUNT-1:0];
reg [READ_PORT_COUNT*DATA_WIDTH-1:0] qi;
reg [DATA_WIDTH-1:0] qt;
reg [DATA_WIDTH-1:0] di [WRITE_PORT_COUNT-1:0];
reg [DATA_WIDTH-1:0] dt;
reg [ADDRESS_WIDTH-1:0] wat;
reg [ADDRESS_WIDTH-1:0] wai [WRITE_PORT_COUNT-1:0];
// Split input data
always @ (d) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<DATA_WIDTH;j=j+1) begin
dt[j]=d[i*DATA_WIDTH+j];
end
di[i]=dt;
end
end
// Split write addresses
always @ (wa) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
wat[j]=wa[i*ADDRESS_WIDTH+j];
end
wai[i]=wat;
end
end
// Write memory
always @ (posedge clk) begin
for (j=0;j<WRITE_PORT_COUNT;j=j+1) begin
if (we[j]) begin
mem[wai[j]] <= di[j];
end
end
end
// Split read addresses
always @ (ra) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
rat[j]=ra[i*ADDRESS_WIDTH+j];
end
rai[i]=rat;
end
end
// guide read addresses using CE
always @ (posedge clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if ( ce[i] ) begin
rai_reg[i] <= rai[i];
end
end
end
// Memory read
always @ (rai_reg[0] or clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if (rai_reg[i] >= WORD_COUNT) begin
qt={DATA_WIDTH {1'b0}};
end else begin
qt=mem[rai_reg[i]];
end
for (j=0;j<DATA_WIDTH;j=j+1) begin
qi[i*DATA_WIDTH+j]=qt[j];
end
end
end
assign q=qi;
endmodule
`endcelldefine
module denoise_r1_p3 (
address0,
ce0,
q0,
we0,
d0,
clk);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd225;
parameter AddressWidth = 32'd8;
input[AddressWidth-1:0] address0;
input ce0;
output[DataWidth-1:0] q0;
input we0;
input[DataWidth-1:0] d0;
input clk;
reg[DataWidth-1:0] q0;
wire[1 * DataWidth - 1:0] mem_q;
wire[DataWidth - 1:0] mem_q0;
wire[1 - 1:0] mem_we;
wire[1 * DataWidth - 1:0] mem_d;
wire[1 * AddressWidth - 1:0] mem_wa;
wire[1 * AddressWidth - 1:0] mem_ra;
wire[1 - 1:0] mem_ce;
denoise_r1_p3_core #(
.READ_PORT_COUNT( 1 ),
.WRITE_PORT_COUNT( 1 ),
.DATA_WIDTH( DataWidth ),
.ADDRESS_WIDTH( AddressWidth ),
.WORD_COUNT( AddressRange ))
core_inst (
.q( mem_q ),
.ra( mem_ra ),
.ce( mem_ce ),
.d( mem_d ),
.wa( mem_wa ),
.we( mem_we ),
.clk( clk ));
assign mem_q0 = mem_q[1 * DataWidth - 1 : 0 * DataWidth];
always @ (mem_q0) begin
q0 = mem_q0;
end
assign mem_ra = {address0};
assign mem_ce = {ce0};
assign mem_we[0] = we0;
assign mem_d = {d0};
assign mem_wa = {address0};
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
`celldefine
module denoise_sm0_p0_core (q, ra, ce, clk, d, wa, we);
parameter READ_PORT_COUNT=32'd1;
parameter WRITE_PORT_COUNT=32'd1;
parameter DATA_WIDTH=32'd32;
parameter ADDRESS_WIDTH=32'd8;
parameter WORD_COUNT=32'd225;
output [READ_PORT_COUNT*DATA_WIDTH-1:0] q;
input [READ_PORT_COUNT*ADDRESS_WIDTH-1:0] ra;
input [READ_PORT_COUNT-1:0] ce;
input [WRITE_PORT_COUNT*DATA_WIDTH-1:0] d;
input [WRITE_PORT_COUNT*ADDRESS_WIDTH-1:0] wa;
input [WRITE_PORT_COUNT-1:0] we;
input clk;
integer i,j,k;
reg [DATA_WIDTH-1:0] mem [0:WORD_COUNT-1];
reg [ADDRESS_WIDTH-1:0] rat;
reg [ADDRESS_WIDTH-1:0] rai [READ_PORT_COUNT-1:0];
reg [ADDRESS_WIDTH-1:0] rai_reg [READ_PORT_COUNT-1:0];
reg [READ_PORT_COUNT*DATA_WIDTH-1:0] qi;
reg [DATA_WIDTH-1:0] qt;
reg [DATA_WIDTH-1:0] di [WRITE_PORT_COUNT-1:0];
reg [DATA_WIDTH-1:0] dt;
reg [ADDRESS_WIDTH-1:0] wat;
reg [ADDRESS_WIDTH-1:0] wai [WRITE_PORT_COUNT-1:0];
// Split input data
always @ (d) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<DATA_WIDTH;j=j+1) begin
dt[j]=d[i*DATA_WIDTH+j];
end
di[i]=dt;
end
end
// Split write addresses
always @ (wa) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
wat[j]=wa[i*ADDRESS_WIDTH+j];
end
wai[i]=wat;
end
end
// Write memory
always @ (posedge clk) begin
for (j=0;j<WRITE_PORT_COUNT;j=j+1) begin
if (we[j]) begin
mem[wai[j]] <= di[j];
end
end
end
// Split read addresses
always @ (ra) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
rat[j]=ra[i*ADDRESS_WIDTH+j];
end
rai[i]=rat;
end
end
// guide read addresses using CE
always @ (posedge clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if ( ce[i] ) begin
rai_reg[i] <= rai[i];
end
end
end
// Memory read
always @ (rai_reg[0] or clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if (rai_reg[i] >= WORD_COUNT) begin
qt={DATA_WIDTH {1'b0}};
end else begin
qt=mem[rai_reg[i]];
end
for (j=0;j<DATA_WIDTH;j=j+1) begin
qi[i*DATA_WIDTH+j]=qt[j];
end
end
end
assign q=qi;
endmodule
`endcelldefine
module denoise_sm0_p0 (
address0,
ce0,
q0,
we0,
d0,
clk);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd225;
parameter AddressWidth = 32'd8;
input[AddressWidth-1:0] address0;
input ce0;
output[DataWidth-1:0] q0;
input we0;
input[DataWidth-1:0] d0;
input clk;
reg[DataWidth-1:0] q0;
wire[1 * DataWidth - 1:0] mem_q;
wire[DataWidth - 1:0] mem_q0;
wire[1 - 1:0] mem_we;
wire[1 * DataWidth - 1:0] mem_d;
wire[1 * AddressWidth - 1:0] mem_wa;
wire[1 * AddressWidth - 1:0] mem_ra;
wire[1 - 1:0] mem_ce;
denoise_sm0_p0_core #(
.READ_PORT_COUNT( 1 ),
.WRITE_PORT_COUNT( 1 ),
.DATA_WIDTH( DataWidth ),
.ADDRESS_WIDTH( AddressWidth ),
.WORD_COUNT( AddressRange ))
core_inst (
.q( mem_q ),
.ra( mem_ra ),
.ce( mem_ce ),
.d( mem_d ),
.wa( mem_wa ),
.we( mem_we ),
.clk( clk ));
assign mem_q0 = mem_q[1 * DataWidth - 1 : 0 * DataWidth];
always @ (mem_q0) begin
q0 = mem_q0;
end
assign mem_ra = {address0};
assign mem_ce = {ce0};
assign mem_we[0] = we0;
assign mem_d = {d0};
assign mem_wa = {address0};
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
`celldefine
module denoise_sm0_p1_core (q, ra, ce, clk, d, wa, we);
parameter READ_PORT_COUNT=32'd1;
parameter WRITE_PORT_COUNT=32'd1;
parameter DATA_WIDTH=32'd32;
parameter ADDRESS_WIDTH=32'd8;
parameter WORD_COUNT=32'd225;
output [READ_PORT_COUNT*DATA_WIDTH-1:0] q;
input [READ_PORT_COUNT*ADDRESS_WIDTH-1:0] ra;
input [READ_PORT_COUNT-1:0] ce;
input [WRITE_PORT_COUNT*DATA_WIDTH-1:0] d;
input [WRITE_PORT_COUNT*ADDRESS_WIDTH-1:0] wa;
input [WRITE_PORT_COUNT-1:0] we;
input clk;
integer i,j,k;
reg [DATA_WIDTH-1:0] mem [0:WORD_COUNT-1];
reg [ADDRESS_WIDTH-1:0] rat;
reg [ADDRESS_WIDTH-1:0] rai [READ_PORT_COUNT-1:0];
reg [ADDRESS_WIDTH-1:0] rai_reg [READ_PORT_COUNT-1:0];
reg [READ_PORT_COUNT*DATA_WIDTH-1:0] qi;
reg [DATA_WIDTH-1:0] qt;
reg [DATA_WIDTH-1:0] di [WRITE_PORT_COUNT-1:0];
reg [DATA_WIDTH-1:0] dt;
reg [ADDRESS_WIDTH-1:0] wat;
reg [ADDRESS_WIDTH-1:0] wai [WRITE_PORT_COUNT-1:0];
// Split input data
always @ (d) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<DATA_WIDTH;j=j+1) begin
dt[j]=d[i*DATA_WIDTH+j];
end
di[i]=dt;
end
end
// Split write addresses
always @ (wa) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
wat[j]=wa[i*ADDRESS_WIDTH+j];
end
wai[i]=wat;
end
end
// Write memory
always @ (posedge clk) begin
for (j=0;j<WRITE_PORT_COUNT;j=j+1) begin
if (we[j]) begin
mem[wai[j]] <= di[j];
end
end
end
// Split read addresses
always @ (ra) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
rat[j]=ra[i*ADDRESS_WIDTH+j];
end
rai[i]=rat;
end
end
// guide read addresses using CE
always @ (posedge clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if ( ce[i] ) begin
rai_reg[i] <= rai[i];
end
end
end
// Memory read
always @ (rai_reg[0] or clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if (rai_reg[i] >= WORD_COUNT) begin
qt={DATA_WIDTH {1'b0}};
end else begin
qt=mem[rai_reg[i]];
end
for (j=0;j<DATA_WIDTH;j=j+1) begin
qi[i*DATA_WIDTH+j]=qt[j];
end
end
end
assign q=qi;
endmodule
`endcelldefine
module denoise_sm0_p1 (
address0,
ce0,
q0,
we0,
d0,
clk);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd225;
parameter AddressWidth = 32'd8;
input[AddressWidth-1:0] address0;
input ce0;
output[DataWidth-1:0] q0;
input we0;
input[DataWidth-1:0] d0;
input clk;
reg[DataWidth-1:0] q0;
wire[1 * DataWidth - 1:0] mem_q;
wire[DataWidth - 1:0] mem_q0;
wire[1 - 1:0] mem_we;
wire[1 * DataWidth - 1:0] mem_d;
wire[1 * AddressWidth - 1:0] mem_wa;
wire[1 * AddressWidth - 1:0] mem_ra;
wire[1 - 1:0] mem_ce;
denoise_sm0_p1_core #(
.READ_PORT_COUNT( 1 ),
.WRITE_PORT_COUNT( 1 ),
.DATA_WIDTH( DataWidth ),
.ADDRESS_WIDTH( AddressWidth ),
.WORD_COUNT( AddressRange ))
core_inst (
.q( mem_q ),
.ra( mem_ra ),
.ce( mem_ce ),
.d( mem_d ),
.wa( mem_wa ),
.we( mem_we ),
.clk( clk ));
assign mem_q0 = mem_q[1 * DataWidth - 1 : 0 * DataWidth];
always @ (mem_q0) begin
q0 = mem_q0;
end
assign mem_ra = {address0};
assign mem_ce = {ce0};
assign mem_we[0] = we0;
assign mem_d = {d0};
assign mem_wa = {address0};
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
`celldefine
module denoise_sm0_p2_core (q, ra, ce, clk, d, wa, we);
parameter READ_PORT_COUNT=32'd1;
parameter WRITE_PORT_COUNT=32'd1;
parameter DATA_WIDTH=32'd32;
parameter ADDRESS_WIDTH=32'd8;
parameter WORD_COUNT=32'd225;
output [READ_PORT_COUNT*DATA_WIDTH-1:0] q;
input [READ_PORT_COUNT*ADDRESS_WIDTH-1:0] ra;
input [READ_PORT_COUNT-1:0] ce;
input [WRITE_PORT_COUNT*DATA_WIDTH-1:0] d;
input [WRITE_PORT_COUNT*ADDRESS_WIDTH-1:0] wa;
input [WRITE_PORT_COUNT-1:0] we;
input clk;
integer i,j,k;
reg [DATA_WIDTH-1:0] mem [0:WORD_COUNT-1];
reg [ADDRESS_WIDTH-1:0] rat;
reg [ADDRESS_WIDTH-1:0] rai [READ_PORT_COUNT-1:0];
reg [ADDRESS_WIDTH-1:0] rai_reg [READ_PORT_COUNT-1:0];
reg [READ_PORT_COUNT*DATA_WIDTH-1:0] qi;
reg [DATA_WIDTH-1:0] qt;
reg [DATA_WIDTH-1:0] di [WRITE_PORT_COUNT-1:0];
reg [DATA_WIDTH-1:0] dt;
reg [ADDRESS_WIDTH-1:0] wat;
reg [ADDRESS_WIDTH-1:0] wai [WRITE_PORT_COUNT-1:0];
// Split input data
always @ (d) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<DATA_WIDTH;j=j+1) begin
dt[j]=d[i*DATA_WIDTH+j];
end
di[i]=dt;
end
end
// Split write addresses
always @ (wa) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
wat[j]=wa[i*ADDRESS_WIDTH+j];
end
wai[i]=wat;
end
end
// Write memory
always @ (posedge clk) begin
for (j=0;j<WRITE_PORT_COUNT;j=j+1) begin
if (we[j]) begin
mem[wai[j]] <= di[j];
end
end
end
// Split read addresses
always @ (ra) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
rat[j]=ra[i*ADDRESS_WIDTH+j];
end
rai[i]=rat;
end
end
// guide read addresses using CE
always @ (posedge clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if ( ce[i] ) begin
rai_reg[i] <= rai[i];
end
end
end
// Memory read
always @ (rai_reg[0] or clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if (rai_reg[i] >= WORD_COUNT) begin
qt={DATA_WIDTH {1'b0}};
end else begin
qt=mem[rai_reg[i]];
end
for (j=0;j<DATA_WIDTH;j=j+1) begin
qi[i*DATA_WIDTH+j]=qt[j];
end
end
end
assign q=qi;
endmodule
`endcelldefine
module denoise_sm0_p2 (
address0,
ce0,
q0,
we0,
d0,
clk);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd225;
parameter AddressWidth = 32'd8;
input[AddressWidth-1:0] address0;
input ce0;
output[DataWidth-1:0] q0;
input we0;
input[DataWidth-1:0] d0;
input clk;
reg[DataWidth-1:0] q0;
wire[1 * DataWidth - 1:0] mem_q;
wire[DataWidth - 1:0] mem_q0;
wire[1 - 1:0] mem_we;
wire[1 * DataWidth - 1:0] mem_d;
wire[1 * AddressWidth - 1:0] mem_wa;
wire[1 * AddressWidth - 1:0] mem_ra;
wire[1 - 1:0] mem_ce;
denoise_sm0_p2_core #(
.READ_PORT_COUNT( 1 ),
.WRITE_PORT_COUNT( 1 ),
.DATA_WIDTH( DataWidth ),
.ADDRESS_WIDTH( AddressWidth ),
.WORD_COUNT( AddressRange ))
core_inst (
.q( mem_q ),
.ra( mem_ra ),
.ce( mem_ce ),
.d( mem_d ),
.wa( mem_wa ),
.we( mem_we ),
.clk( clk ));
assign mem_q0 = mem_q[1 * DataWidth - 1 : 0 * DataWidth];
always @ (mem_q0) begin
q0 = mem_q0;
end
assign mem_ra = {address0};
assign mem_ce = {ce0};
assign mem_we[0] = we0;
assign mem_d = {d0};
assign mem_wa = {address0};
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
`celldefine
module denoise_sm0_p3_core (q, ra, ce, clk, d, wa, we);
parameter READ_PORT_COUNT=32'd1;
parameter WRITE_PORT_COUNT=32'd1;
parameter DATA_WIDTH=32'd32;
parameter ADDRESS_WIDTH=32'd8;
parameter WORD_COUNT=32'd225;
output [READ_PORT_COUNT*DATA_WIDTH-1:0] q;
input [READ_PORT_COUNT*ADDRESS_WIDTH-1:0] ra;
input [READ_PORT_COUNT-1:0] ce;
input [WRITE_PORT_COUNT*DATA_WIDTH-1:0] d;
input [WRITE_PORT_COUNT*ADDRESS_WIDTH-1:0] wa;
input [WRITE_PORT_COUNT-1:0] we;
input clk;
integer i,j,k;
reg [DATA_WIDTH-1:0] mem [0:WORD_COUNT-1];
reg [ADDRESS_WIDTH-1:0] rat;
reg [ADDRESS_WIDTH-1:0] rai [READ_PORT_COUNT-1:0];
reg [ADDRESS_WIDTH-1:0] rai_reg [READ_PORT_COUNT-1:0];
reg [READ_PORT_COUNT*DATA_WIDTH-1:0] qi;
reg [DATA_WIDTH-1:0] qt;
reg [DATA_WIDTH-1:0] di [WRITE_PORT_COUNT-1:0];
reg [DATA_WIDTH-1:0] dt;
reg [ADDRESS_WIDTH-1:0] wat;
reg [ADDRESS_WIDTH-1:0] wai [WRITE_PORT_COUNT-1:0];
// Split input data
always @ (d) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<DATA_WIDTH;j=j+1) begin
dt[j]=d[i*DATA_WIDTH+j];
end
di[i]=dt;
end
end
// Split write addresses
always @ (wa) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
wat[j]=wa[i*ADDRESS_WIDTH+j];
end
wai[i]=wat;
end
end
// Write memory
always @ (posedge clk) begin
for (j=0;j<WRITE_PORT_COUNT;j=j+1) begin
if (we[j]) begin
mem[wai[j]] <= di[j];
end
end
end
// Split read addresses
always @ (ra) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
rat[j]=ra[i*ADDRESS_WIDTH+j];
end
rai[i]=rat;
end
end
// guide read addresses using CE
always @ (posedge clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if ( ce[i] ) begin
rai_reg[i] <= rai[i];
end
end
end
// Memory read
always @ (rai_reg[0] or clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if (rai_reg[i] >= WORD_COUNT) begin
qt={DATA_WIDTH {1'b0}};
end else begin
qt=mem[rai_reg[i]];
end
for (j=0;j<DATA_WIDTH;j=j+1) begin
qi[i*DATA_WIDTH+j]=qt[j];
end
end
end
assign q=qi;
endmodule
`endcelldefine
module denoise_sm0_p3 (
address0,
ce0,
q0,
we0,
d0,
clk);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd225;
parameter AddressWidth = 32'd8;
input[AddressWidth-1:0] address0;
input ce0;
output[DataWidth-1:0] q0;
input we0;
input[DataWidth-1:0] d0;
input clk;
reg[DataWidth-1:0] q0;
wire[1 * DataWidth - 1:0] mem_q;
wire[DataWidth - 1:0] mem_q0;
wire[1 - 1:0] mem_we;
wire[1 * DataWidth - 1:0] mem_d;
wire[1 * AddressWidth - 1:0] mem_wa;
wire[1 * AddressWidth - 1:0] mem_ra;
wire[1 - 1:0] mem_ce;
denoise_sm0_p3_core #(
.READ_PORT_COUNT( 1 ),
.WRITE_PORT_COUNT( 1 ),
.DATA_WIDTH( DataWidth ),
.ADDRESS_WIDTH( AddressWidth ),
.WORD_COUNT( AddressRange ))
core_inst (
.q( mem_q ),
.ra( mem_ra ),
.ce( mem_ce ),
.d( mem_d ),
.wa( mem_wa ),
.we( mem_we ),
.clk( clk ));
assign mem_q0 = mem_q[1 * DataWidth - 1 : 0 * DataWidth];
always @ (mem_q0) begin
q0 = mem_q0;
end
assign mem_ra = {address0};
assign mem_ce = {ce0};
assign mem_we[0] = we0;
assign mem_d = {d0};
assign mem_wa = {address0};
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
`celldefine
module denoise_sm1_p0_core (q, ra, ce, clk, d, wa, we);
parameter READ_PORT_COUNT=32'd1;
parameter WRITE_PORT_COUNT=32'd1;
parameter DATA_WIDTH=32'd32;
parameter ADDRESS_WIDTH=32'd8;
parameter WORD_COUNT=32'd225;
output [READ_PORT_COUNT*DATA_WIDTH-1:0] q;
input [READ_PORT_COUNT*ADDRESS_WIDTH-1:0] ra;
input [READ_PORT_COUNT-1:0] ce;
input [WRITE_PORT_COUNT*DATA_WIDTH-1:0] d;
input [WRITE_PORT_COUNT*ADDRESS_WIDTH-1:0] wa;
input [WRITE_PORT_COUNT-1:0] we;
input clk;
integer i,j,k;
reg [DATA_WIDTH-1:0] mem [0:WORD_COUNT-1];
reg [ADDRESS_WIDTH-1:0] rat;
reg [ADDRESS_WIDTH-1:0] rai [READ_PORT_COUNT-1:0];
reg [ADDRESS_WIDTH-1:0] rai_reg [READ_PORT_COUNT-1:0];
reg [READ_PORT_COUNT*DATA_WIDTH-1:0] qi;
reg [DATA_WIDTH-1:0] qt;
reg [DATA_WIDTH-1:0] di [WRITE_PORT_COUNT-1:0];
reg [DATA_WIDTH-1:0] dt;
reg [ADDRESS_WIDTH-1:0] wat;
reg [ADDRESS_WIDTH-1:0] wai [WRITE_PORT_COUNT-1:0];
// Split input data
always @ (d) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<DATA_WIDTH;j=j+1) begin
dt[j]=d[i*DATA_WIDTH+j];
end
di[i]=dt;
end
end
// Split write addresses
always @ (wa) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
wat[j]=wa[i*ADDRESS_WIDTH+j];
end
wai[i]=wat;
end
end
// Write memory
always @ (posedge clk) begin
for (j=0;j<WRITE_PORT_COUNT;j=j+1) begin
if (we[j]) begin
mem[wai[j]] <= di[j];
end
end
end
// Split read addresses
always @ (ra) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
rat[j]=ra[i*ADDRESS_WIDTH+j];
end
rai[i]=rat;
end
end
// guide read addresses using CE
always @ (posedge clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if ( ce[i] ) begin
rai_reg[i] <= rai[i];
end
end
end
// Memory read
always @ (rai_reg[0] or clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if (rai_reg[i] >= WORD_COUNT) begin
qt={DATA_WIDTH {1'b0}};
end else begin
qt=mem[rai_reg[i]];
end
for (j=0;j<DATA_WIDTH;j=j+1) begin
qi[i*DATA_WIDTH+j]=qt[j];
end
end
end
assign q=qi;
endmodule
`endcelldefine
module denoise_sm1_p0 (
address0,
ce0,
q0,
we0,
d0,
clk);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd225;
parameter AddressWidth = 32'd8;
input[AddressWidth-1:0] address0;
input ce0;
output[DataWidth-1:0] q0;
input we0;
input[DataWidth-1:0] d0;
input clk;
reg[DataWidth-1:0] q0;
wire[1 * DataWidth - 1:0] mem_q;
wire[DataWidth - 1:0] mem_q0;
wire[1 - 1:0] mem_we;
wire[1 * DataWidth - 1:0] mem_d;
wire[1 * AddressWidth - 1:0] mem_wa;
wire[1 * AddressWidth - 1:0] mem_ra;
wire[1 - 1:0] mem_ce;
denoise_sm1_p0_core #(
.READ_PORT_COUNT( 1 ),
.WRITE_PORT_COUNT( 1 ),
.DATA_WIDTH( DataWidth ),
.ADDRESS_WIDTH( AddressWidth ),
.WORD_COUNT( AddressRange ))
core_inst (
.q( mem_q ),
.ra( mem_ra ),
.ce( mem_ce ),
.d( mem_d ),
.wa( mem_wa ),
.we( mem_we ),
.clk( clk ));
assign mem_q0 = mem_q[1 * DataWidth - 1 : 0 * DataWidth];
always @ (mem_q0) begin
q0 = mem_q0;
end
assign mem_ra = {address0};
assign mem_ce = {ce0};
assign mem_we[0] = we0;
assign mem_d = {d0};
assign mem_wa = {address0};
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
`celldefine
module denoise_sm1_p1_core (q, ra, ce, clk, d, wa, we);
parameter READ_PORT_COUNT=32'd1;
parameter WRITE_PORT_COUNT=32'd1;
parameter DATA_WIDTH=32'd32;
parameter ADDRESS_WIDTH=32'd8;
parameter WORD_COUNT=32'd225;
output [READ_PORT_COUNT*DATA_WIDTH-1:0] q;
input [READ_PORT_COUNT*ADDRESS_WIDTH-1:0] ra;
input [READ_PORT_COUNT-1:0] ce;
input [WRITE_PORT_COUNT*DATA_WIDTH-1:0] d;
input [WRITE_PORT_COUNT*ADDRESS_WIDTH-1:0] wa;
input [WRITE_PORT_COUNT-1:0] we;
input clk;
integer i,j,k;
reg [DATA_WIDTH-1:0] mem [0:WORD_COUNT-1];
reg [ADDRESS_WIDTH-1:0] rat;
reg [ADDRESS_WIDTH-1:0] rai [READ_PORT_COUNT-1:0];
reg [ADDRESS_WIDTH-1:0] rai_reg [READ_PORT_COUNT-1:0];
reg [READ_PORT_COUNT*DATA_WIDTH-1:0] qi;
reg [DATA_WIDTH-1:0] qt;
reg [DATA_WIDTH-1:0] di [WRITE_PORT_COUNT-1:0];
reg [DATA_WIDTH-1:0] dt;
reg [ADDRESS_WIDTH-1:0] wat;
reg [ADDRESS_WIDTH-1:0] wai [WRITE_PORT_COUNT-1:0];
// Split input data
always @ (d) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<DATA_WIDTH;j=j+1) begin
dt[j]=d[i*DATA_WIDTH+j];
end
di[i]=dt;
end
end
// Split write addresses
always @ (wa) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
wat[j]=wa[i*ADDRESS_WIDTH+j];
end
wai[i]=wat;
end
end
// Write memory
always @ (posedge clk) begin
for (j=0;j<WRITE_PORT_COUNT;j=j+1) begin
if (we[j]) begin
mem[wai[j]] <= di[j];
end
end
end
// Split read addresses
always @ (ra) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
rat[j]=ra[i*ADDRESS_WIDTH+j];
end
rai[i]=rat;
end
end
// guide read addresses using CE
always @ (posedge clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if ( ce[i] ) begin
rai_reg[i] <= rai[i];
end
end
end
// Memory read
always @ (rai_reg[0] or clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if (rai_reg[i] >= WORD_COUNT) begin
qt={DATA_WIDTH {1'b0}};
end else begin
qt=mem[rai_reg[i]];
end
for (j=0;j<DATA_WIDTH;j=j+1) begin
qi[i*DATA_WIDTH+j]=qt[j];
end
end
end
assign q=qi;
endmodule
`endcelldefine
module denoise_sm1_p1 (
address0,
ce0,
q0,
we0,
d0,
clk);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd225;
parameter AddressWidth = 32'd8;
input[AddressWidth-1:0] address0;
input ce0;
output[DataWidth-1:0] q0;
input we0;
input[DataWidth-1:0] d0;
input clk;
reg[DataWidth-1:0] q0;
wire[1 * DataWidth - 1:0] mem_q;
wire[DataWidth - 1:0] mem_q0;
wire[1 - 1:0] mem_we;
wire[1 * DataWidth - 1:0] mem_d;
wire[1 * AddressWidth - 1:0] mem_wa;
wire[1 * AddressWidth - 1:0] mem_ra;
wire[1 - 1:0] mem_ce;
denoise_sm1_p1_core #(
.READ_PORT_COUNT( 1 ),
.WRITE_PORT_COUNT( 1 ),
.DATA_WIDTH( DataWidth ),
.ADDRESS_WIDTH( AddressWidth ),
.WORD_COUNT( AddressRange ))
core_inst (
.q( mem_q ),
.ra( mem_ra ),
.ce( mem_ce ),
.d( mem_d ),
.wa( mem_wa ),
.we( mem_we ),
.clk( clk ));
assign mem_q0 = mem_q[1 * DataWidth - 1 : 0 * DataWidth];
always @ (mem_q0) begin
q0 = mem_q0;
end
assign mem_ra = {address0};
assign mem_ce = {ce0};
assign mem_we[0] = we0;
assign mem_d = {d0};
assign mem_wa = {address0};
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
`celldefine
module denoise_sm1_p2_core (q, ra, ce, clk, d, wa, we);
parameter READ_PORT_COUNT=32'd1;
parameter WRITE_PORT_COUNT=32'd1;
parameter DATA_WIDTH=32'd32;
parameter ADDRESS_WIDTH=32'd8;
parameter WORD_COUNT=32'd225;
output [READ_PORT_COUNT*DATA_WIDTH-1:0] q;
input [READ_PORT_COUNT*ADDRESS_WIDTH-1:0] ra;
input [READ_PORT_COUNT-1:0] ce;
input [WRITE_PORT_COUNT*DATA_WIDTH-1:0] d;
input [WRITE_PORT_COUNT*ADDRESS_WIDTH-1:0] wa;
input [WRITE_PORT_COUNT-1:0] we;
input clk;
integer i,j,k;
reg [DATA_WIDTH-1:0] mem [0:WORD_COUNT-1];
reg [ADDRESS_WIDTH-1:0] rat;
reg [ADDRESS_WIDTH-1:0] rai [READ_PORT_COUNT-1:0];
reg [ADDRESS_WIDTH-1:0] rai_reg [READ_PORT_COUNT-1:0];
reg [READ_PORT_COUNT*DATA_WIDTH-1:0] qi;
reg [DATA_WIDTH-1:0] qt;
reg [DATA_WIDTH-1:0] di [WRITE_PORT_COUNT-1:0];
reg [DATA_WIDTH-1:0] dt;
reg [ADDRESS_WIDTH-1:0] wat;
reg [ADDRESS_WIDTH-1:0] wai [WRITE_PORT_COUNT-1:0];
// Split input data
always @ (d) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<DATA_WIDTH;j=j+1) begin
dt[j]=d[i*DATA_WIDTH+j];
end
di[i]=dt;
end
end
// Split write addresses
always @ (wa) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
wat[j]=wa[i*ADDRESS_WIDTH+j];
end
wai[i]=wat;
end
end
// Write memory
always @ (posedge clk) begin
for (j=0;j<WRITE_PORT_COUNT;j=j+1) begin
if (we[j]) begin
mem[wai[j]] <= di[j];
end
end
end
// Split read addresses
always @ (ra) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
rat[j]=ra[i*ADDRESS_WIDTH+j];
end
rai[i]=rat;
end
end
// guide read addresses using CE
always @ (posedge clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if ( ce[i] ) begin
rai_reg[i] <= rai[i];
end
end
end
// Memory read
always @ (rai_reg[0] or clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if (rai_reg[i] >= WORD_COUNT) begin
qt={DATA_WIDTH {1'b0}};
end else begin
qt=mem[rai_reg[i]];
end
for (j=0;j<DATA_WIDTH;j=j+1) begin
qi[i*DATA_WIDTH+j]=qt[j];
end
end
end
assign q=qi;
endmodule
`endcelldefine
module denoise_sm1_p2 (
address0,
ce0,
q0,
we0,
d0,
clk);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd225;
parameter AddressWidth = 32'd8;
input[AddressWidth-1:0] address0;
input ce0;
output[DataWidth-1:0] q0;
input we0;
input[DataWidth-1:0] d0;
input clk;
reg[DataWidth-1:0] q0;
wire[1 * DataWidth - 1:0] mem_q;
wire[DataWidth - 1:0] mem_q0;
wire[1 - 1:0] mem_we;
wire[1 * DataWidth - 1:0] mem_d;
wire[1 * AddressWidth - 1:0] mem_wa;
wire[1 * AddressWidth - 1:0] mem_ra;
wire[1 - 1:0] mem_ce;
denoise_sm1_p2_core #(
.READ_PORT_COUNT( 1 ),
.WRITE_PORT_COUNT( 1 ),
.DATA_WIDTH( DataWidth ),
.ADDRESS_WIDTH( AddressWidth ),
.WORD_COUNT( AddressRange ))
core_inst (
.q( mem_q ),
.ra( mem_ra ),
.ce( mem_ce ),
.d( mem_d ),
.wa( mem_wa ),
.we( mem_we ),
.clk( clk ));
assign mem_q0 = mem_q[1 * DataWidth - 1 : 0 * DataWidth];
always @ (mem_q0) begin
q0 = mem_q0;
end
assign mem_ra = {address0};
assign mem_ce = {ce0};
assign mem_we[0] = we0;
assign mem_d = {d0};
assign mem_wa = {address0};
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
`celldefine
module denoise_sm1_p3_core (q, ra, ce, clk, d, wa, we);
parameter READ_PORT_COUNT=32'd1;
parameter WRITE_PORT_COUNT=32'd1;
parameter DATA_WIDTH=32'd32;
parameter ADDRESS_WIDTH=32'd8;
parameter WORD_COUNT=32'd225;
output [READ_PORT_COUNT*DATA_WIDTH-1:0] q;
input [READ_PORT_COUNT*ADDRESS_WIDTH-1:0] ra;
input [READ_PORT_COUNT-1:0] ce;
input [WRITE_PORT_COUNT*DATA_WIDTH-1:0] d;
input [WRITE_PORT_COUNT*ADDRESS_WIDTH-1:0] wa;
input [WRITE_PORT_COUNT-1:0] we;
input clk;
integer i,j,k;
reg [DATA_WIDTH-1:0] mem [0:WORD_COUNT-1];
reg [ADDRESS_WIDTH-1:0] rat;
reg [ADDRESS_WIDTH-1:0] rai [READ_PORT_COUNT-1:0];
reg [ADDRESS_WIDTH-1:0] rai_reg [READ_PORT_COUNT-1:0];
reg [READ_PORT_COUNT*DATA_WIDTH-1:0] qi;
reg [DATA_WIDTH-1:0] qt;
reg [DATA_WIDTH-1:0] di [WRITE_PORT_COUNT-1:0];
reg [DATA_WIDTH-1:0] dt;
reg [ADDRESS_WIDTH-1:0] wat;
reg [ADDRESS_WIDTH-1:0] wai [WRITE_PORT_COUNT-1:0];
// Split input data
always @ (d) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<DATA_WIDTH;j=j+1) begin
dt[j]=d[i*DATA_WIDTH+j];
end
di[i]=dt;
end
end
// Split write addresses
always @ (wa) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
wat[j]=wa[i*ADDRESS_WIDTH+j];
end
wai[i]=wat;
end
end
// Write memory
always @ (posedge clk) begin
for (j=0;j<WRITE_PORT_COUNT;j=j+1) begin
if (we[j]) begin
mem[wai[j]] <= di[j];
end
end
end
// Split read addresses
always @ (ra) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
rat[j]=ra[i*ADDRESS_WIDTH+j];
end
rai[i]=rat;
end
end
// guide read addresses using CE
always @ (posedge clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if ( ce[i] ) begin
rai_reg[i] <= rai[i];
end
end
end
// Memory read
always @ (rai_reg[0] or clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if (rai_reg[i] >= WORD_COUNT) begin
qt={DATA_WIDTH {1'b0}};
end else begin
qt=mem[rai_reg[i]];
end
for (j=0;j<DATA_WIDTH;j=j+1) begin
qi[i*DATA_WIDTH+j]=qt[j];
end
end
end
assign q=qi;
endmodule
`endcelldefine
module denoise_sm1_p3 (
address0,
ce0,
q0,
we0,
d0,
clk);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd225;
parameter AddressWidth = 32'd8;
input[AddressWidth-1:0] address0;
input ce0;
output[DataWidth-1:0] q0;
input we0;
input[DataWidth-1:0] d0;
input clk;
reg[DataWidth-1:0] q0;
wire[1 * DataWidth - 1:0] mem_q;
wire[DataWidth - 1:0] mem_q0;
wire[1 - 1:0] mem_we;
wire[1 * DataWidth - 1:0] mem_d;
wire[1 * AddressWidth - 1:0] mem_wa;
wire[1 * AddressWidth - 1:0] mem_ra;
wire[1 - 1:0] mem_ce;
denoise_sm1_p3_core #(
.READ_PORT_COUNT( 1 ),
.WRITE_PORT_COUNT( 1 ),
.DATA_WIDTH( DataWidth ),
.ADDRESS_WIDTH( AddressWidth ),
.WORD_COUNT( AddressRange ))
core_inst (
.q( mem_q ),
.ra( mem_ra ),
.ce( mem_ce ),
.d( mem_d ),
.wa( mem_wa ),
.we( mem_we ),
.clk( clk ));
assign mem_q0 = mem_q[1 * DataWidth - 1 : 0 * DataWidth];
always @ (mem_q0) begin
q0 = mem_q0;
end
assign mem_ra = {address0};
assign mem_ce = {ce0};
assign mem_we[0] = we0;
assign mem_d = {d0};
assign mem_wa = {address0};
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
`celldefine
module denoise_sn0_p0_core (q, ra, ce, clk, d, wa, we);
parameter READ_PORT_COUNT=32'd2;
parameter WRITE_PORT_COUNT=32'd1;
parameter DATA_WIDTH=32'd32;
parameter ADDRESS_WIDTH=32'd8;
parameter WORD_COUNT=32'd225;
output [READ_PORT_COUNT*DATA_WIDTH-1:0] q;
input [READ_PORT_COUNT*ADDRESS_WIDTH-1:0] ra;
input [READ_PORT_COUNT-1:0] ce;
input [WRITE_PORT_COUNT*DATA_WIDTH-1:0] d;
input [WRITE_PORT_COUNT*ADDRESS_WIDTH-1:0] wa;
input [WRITE_PORT_COUNT-1:0] we;
input clk;
integer i,j,k;
reg [DATA_WIDTH-1:0] mem [0:WORD_COUNT-1];
reg [ADDRESS_WIDTH-1:0] rat;
reg [ADDRESS_WIDTH-1:0] rai [READ_PORT_COUNT-1:0];
reg [ADDRESS_WIDTH-1:0] rai_reg [READ_PORT_COUNT-1:0];
reg [READ_PORT_COUNT*DATA_WIDTH-1:0] qi;
reg [DATA_WIDTH-1:0] qt;
reg [DATA_WIDTH-1:0] di [WRITE_PORT_COUNT-1:0];
reg [DATA_WIDTH-1:0] dt;
reg [ADDRESS_WIDTH-1:0] wat;
reg [ADDRESS_WIDTH-1:0] wai [WRITE_PORT_COUNT-1:0];
// Split input data
always @ (d) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<DATA_WIDTH;j=j+1) begin
dt[j]=d[i*DATA_WIDTH+j];
end
di[i]=dt;
end
end
// Split write addresses
always @ (wa) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
wat[j]=wa[i*ADDRESS_WIDTH+j];
end
wai[i]=wat;
end
end
// Write memory
always @ (posedge clk) begin
for (j=0;j<WRITE_PORT_COUNT;j=j+1) begin
if (we[j]) begin
mem[wai[j]] <= di[j];
end
end
end
// Split read addresses
always @ (ra) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
rat[j]=ra[i*ADDRESS_WIDTH+j];
end
rai[i]=rat;
end
end
// guide read addresses using CE
always @ (posedge clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if ( ce[i] ) begin
rai_reg[i] <= rai[i];
end
end
end
// Memory read
always @ (rai_reg[0] or rai_reg[1] or clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if (rai_reg[i] >= WORD_COUNT) begin
qt={DATA_WIDTH {1'b0}};
end else begin
qt=mem[rai_reg[i]];
end
for (j=0;j<DATA_WIDTH;j=j+1) begin
qi[i*DATA_WIDTH+j]=qt[j];
end
end
end
assign q=qi;
endmodule
`endcelldefine
module denoise_sn0_p0 (
address0,
ce0,
q0,
we0,
d0,
address1,
ce1,
q1,
clk);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd225;
parameter AddressWidth = 32'd8;
input[AddressWidth-1:0] address0;
input ce0;
output[DataWidth-1:0] q0;
input we0;
input[DataWidth-1:0] d0;
input[AddressWidth-1:0] address1;
input ce1;
output[DataWidth-1:0] q1;
input clk;
reg[DataWidth-1:0] q0;
reg[DataWidth-1:0] q1;
wire[2 * DataWidth - 1:0] mem_q;
wire[DataWidth - 1:0] mem_q0;
wire[DataWidth - 1:0] mem_q1;
wire[1 - 1:0] mem_we;
wire[1 * DataWidth - 1:0] mem_d;
wire[1 * AddressWidth - 1:0] mem_wa;
wire[2 * AddressWidth - 1:0] mem_ra;
wire[2 - 1:0] mem_ce;
denoise_sn0_p0_core #(
.READ_PORT_COUNT( 2 ),
.WRITE_PORT_COUNT( 1 ),
.DATA_WIDTH( DataWidth ),
.ADDRESS_WIDTH( AddressWidth ),
.WORD_COUNT( AddressRange ))
core_inst (
.q( mem_q ),
.ra( mem_ra ),
.ce( mem_ce ),
.d( mem_d ),
.wa( mem_wa ),
.we( mem_we ),
.clk( clk ));
assign mem_q0 = mem_q[2 * DataWidth - 1 : 1 * DataWidth];
always @ (mem_q0) begin
q0 = mem_q0;
end
assign mem_q1 = mem_q[1 * DataWidth - 1 : 0 * DataWidth];
always @ (mem_q1) begin
q1 = mem_q1;
end
assign mem_ra = {address0, address1};
assign mem_ce = {ce0, ce1};
assign mem_we[0] = we0;
assign mem_d = {d0};
assign mem_wa = {address0};
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
`celldefine
module denoise_sn0_p1_core (q, ra, ce, clk, d, wa, we);
parameter READ_PORT_COUNT=32'd1;
parameter WRITE_PORT_COUNT=32'd1;
parameter DATA_WIDTH=32'd32;
parameter ADDRESS_WIDTH=32'd8;
parameter WORD_COUNT=32'd225;
output [READ_PORT_COUNT*DATA_WIDTH-1:0] q;
input [READ_PORT_COUNT*ADDRESS_WIDTH-1:0] ra;
input [READ_PORT_COUNT-1:0] ce;
input [WRITE_PORT_COUNT*DATA_WIDTH-1:0] d;
input [WRITE_PORT_COUNT*ADDRESS_WIDTH-1:0] wa;
input [WRITE_PORT_COUNT-1:0] we;
input clk;
integer i,j,k;
reg [DATA_WIDTH-1:0] mem [0:WORD_COUNT-1];
reg [ADDRESS_WIDTH-1:0] rat;
reg [ADDRESS_WIDTH-1:0] rai [READ_PORT_COUNT-1:0];
reg [ADDRESS_WIDTH-1:0] rai_reg [READ_PORT_COUNT-1:0];
reg [READ_PORT_COUNT*DATA_WIDTH-1:0] qi;
reg [DATA_WIDTH-1:0] qt;
reg [DATA_WIDTH-1:0] di [WRITE_PORT_COUNT-1:0];
reg [DATA_WIDTH-1:0] dt;
reg [ADDRESS_WIDTH-1:0] wat;
reg [ADDRESS_WIDTH-1:0] wai [WRITE_PORT_COUNT-1:0];
// Split input data
always @ (d) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<DATA_WIDTH;j=j+1) begin
dt[j]=d[i*DATA_WIDTH+j];
end
di[i]=dt;
end
end
// Split write addresses
always @ (wa) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
wat[j]=wa[i*ADDRESS_WIDTH+j];
end
wai[i]=wat;
end
end
// Write memory
always @ (posedge clk) begin
for (j=0;j<WRITE_PORT_COUNT;j=j+1) begin
if (we[j]) begin
mem[wai[j]] <= di[j];
end
end
end
// Split read addresses
always @ (ra) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
rat[j]=ra[i*ADDRESS_WIDTH+j];
end
rai[i]=rat;
end
end
// guide read addresses using CE
always @ (posedge clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if ( ce[i] ) begin
rai_reg[i] <= rai[i];
end
end
end
// Memory read
always @ (rai_reg[0] or clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if (rai_reg[i] >= WORD_COUNT) begin
qt={DATA_WIDTH {1'b0}};
end else begin
qt=mem[rai_reg[i]];
end
for (j=0;j<DATA_WIDTH;j=j+1) begin
qi[i*DATA_WIDTH+j]=qt[j];
end
end
end
assign q=qi;
endmodule
`endcelldefine
module denoise_sn0_p1 (
address0,
ce0,
q0,
we0,
d0,
clk);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd225;
parameter AddressWidth = 32'd8;
input[AddressWidth-1:0] address0;
input ce0;
output[DataWidth-1:0] q0;
input we0;
input[DataWidth-1:0] d0;
input clk;
reg[DataWidth-1:0] q0;
wire[1 * DataWidth - 1:0] mem_q;
wire[DataWidth - 1:0] mem_q0;
wire[1 - 1:0] mem_we;
wire[1 * DataWidth - 1:0] mem_d;
wire[1 * AddressWidth - 1:0] mem_wa;
wire[1 * AddressWidth - 1:0] mem_ra;
wire[1 - 1:0] mem_ce;
denoise_sn0_p1_core #(
.READ_PORT_COUNT( 1 ),
.WRITE_PORT_COUNT( 1 ),
.DATA_WIDTH( DataWidth ),
.ADDRESS_WIDTH( AddressWidth ),
.WORD_COUNT( AddressRange ))
core_inst (
.q( mem_q ),
.ra( mem_ra ),
.ce( mem_ce ),
.d( mem_d ),
.wa( mem_wa ),
.we( mem_we ),
.clk( clk ));
assign mem_q0 = mem_q[1 * DataWidth - 1 : 0 * DataWidth];
always @ (mem_q0) begin
q0 = mem_q0;
end
assign mem_ra = {address0};
assign mem_ce = {ce0};
assign mem_we[0] = we0;
assign mem_d = {d0};
assign mem_wa = {address0};
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
`celldefine
module denoise_sn0_p2_core (q, ra, ce, clk, d, wa, we);
parameter READ_PORT_COUNT=32'd1;
parameter WRITE_PORT_COUNT=32'd1;
parameter DATA_WIDTH=32'd32;
parameter ADDRESS_WIDTH=32'd8;
parameter WORD_COUNT=32'd225;
output [READ_PORT_COUNT*DATA_WIDTH-1:0] q;
input [READ_PORT_COUNT*ADDRESS_WIDTH-1:0] ra;
input [READ_PORT_COUNT-1:0] ce;
input [WRITE_PORT_COUNT*DATA_WIDTH-1:0] d;
input [WRITE_PORT_COUNT*ADDRESS_WIDTH-1:0] wa;
input [WRITE_PORT_COUNT-1:0] we;
input clk;
integer i,j,k;
reg [DATA_WIDTH-1:0] mem [0:WORD_COUNT-1];
reg [ADDRESS_WIDTH-1:0] rat;
reg [ADDRESS_WIDTH-1:0] rai [READ_PORT_COUNT-1:0];
reg [ADDRESS_WIDTH-1:0] rai_reg [READ_PORT_COUNT-1:0];
reg [READ_PORT_COUNT*DATA_WIDTH-1:0] qi;
reg [DATA_WIDTH-1:0] qt;
reg [DATA_WIDTH-1:0] di [WRITE_PORT_COUNT-1:0];
reg [DATA_WIDTH-1:0] dt;
reg [ADDRESS_WIDTH-1:0] wat;
reg [ADDRESS_WIDTH-1:0] wai [WRITE_PORT_COUNT-1:0];
// Split input data
always @ (d) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<DATA_WIDTH;j=j+1) begin
dt[j]=d[i*DATA_WIDTH+j];
end
di[i]=dt;
end
end
// Split write addresses
always @ (wa) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
wat[j]=wa[i*ADDRESS_WIDTH+j];
end
wai[i]=wat;
end
end
// Write memory
always @ (posedge clk) begin
for (j=0;j<WRITE_PORT_COUNT;j=j+1) begin
if (we[j]) begin
mem[wai[j]] <= di[j];
end
end
end
// Split read addresses
always @ (ra) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
rat[j]=ra[i*ADDRESS_WIDTH+j];
end
rai[i]=rat;
end
end
// guide read addresses using CE
always @ (posedge clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if ( ce[i] ) begin
rai_reg[i] <= rai[i];
end
end
end
// Memory read
always @ (rai_reg[0] or clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if (rai_reg[i] >= WORD_COUNT) begin
qt={DATA_WIDTH {1'b0}};
end else begin
qt=mem[rai_reg[i]];
end
for (j=0;j<DATA_WIDTH;j=j+1) begin
qi[i*DATA_WIDTH+j]=qt[j];
end
end
end
assign q=qi;
endmodule
`endcelldefine
module denoise_sn0_p2 (
address0,
ce0,
q0,
we0,
d0,
clk);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd225;
parameter AddressWidth = 32'd8;
input[AddressWidth-1:0] address0;
input ce0;
output[DataWidth-1:0] q0;
input we0;
input[DataWidth-1:0] d0;
input clk;
reg[DataWidth-1:0] q0;
wire[1 * DataWidth - 1:0] mem_q;
wire[DataWidth - 1:0] mem_q0;
wire[1 - 1:0] mem_we;
wire[1 * DataWidth - 1:0] mem_d;
wire[1 * AddressWidth - 1:0] mem_wa;
wire[1 * AddressWidth - 1:0] mem_ra;
wire[1 - 1:0] mem_ce;
denoise_sn0_p2_core #(
.READ_PORT_COUNT( 1 ),
.WRITE_PORT_COUNT( 1 ),
.DATA_WIDTH( DataWidth ),
.ADDRESS_WIDTH( AddressWidth ),
.WORD_COUNT( AddressRange ))
core_inst (
.q( mem_q ),
.ra( mem_ra ),
.ce( mem_ce ),
.d( mem_d ),
.wa( mem_wa ),
.we( mem_we ),
.clk( clk ));
assign mem_q0 = mem_q[1 * DataWidth - 1 : 0 * DataWidth];
always @ (mem_q0) begin
q0 = mem_q0;
end
assign mem_ra = {address0};
assign mem_ce = {ce0};
assign mem_we[0] = we0;
assign mem_d = {d0};
assign mem_wa = {address0};
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
`celldefine
module denoise_sn0_p3_core (q, ra, ce, clk, d, wa, we);
parameter READ_PORT_COUNT=32'd1;
parameter WRITE_PORT_COUNT=32'd1;
parameter DATA_WIDTH=32'd32;
parameter ADDRESS_WIDTH=32'd8;
parameter WORD_COUNT=32'd225;
output [READ_PORT_COUNT*DATA_WIDTH-1:0] q;
input [READ_PORT_COUNT*ADDRESS_WIDTH-1:0] ra;
input [READ_PORT_COUNT-1:0] ce;
input [WRITE_PORT_COUNT*DATA_WIDTH-1:0] d;
input [WRITE_PORT_COUNT*ADDRESS_WIDTH-1:0] wa;
input [WRITE_PORT_COUNT-1:0] we;
input clk;
integer i,j,k;
reg [DATA_WIDTH-1:0] mem [0:WORD_COUNT-1];
reg [ADDRESS_WIDTH-1:0] rat;
reg [ADDRESS_WIDTH-1:0] rai [READ_PORT_COUNT-1:0];
reg [ADDRESS_WIDTH-1:0] rai_reg [READ_PORT_COUNT-1:0];
reg [READ_PORT_COUNT*DATA_WIDTH-1:0] qi;
reg [DATA_WIDTH-1:0] qt;
reg [DATA_WIDTH-1:0] di [WRITE_PORT_COUNT-1:0];
reg [DATA_WIDTH-1:0] dt;
reg [ADDRESS_WIDTH-1:0] wat;
reg [ADDRESS_WIDTH-1:0] wai [WRITE_PORT_COUNT-1:0];
// Split input data
always @ (d) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<DATA_WIDTH;j=j+1) begin
dt[j]=d[i*DATA_WIDTH+j];
end
di[i]=dt;
end
end
// Split write addresses
always @ (wa) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
wat[j]=wa[i*ADDRESS_WIDTH+j];
end
wai[i]=wat;
end
end
// Write memory
always @ (posedge clk) begin
for (j=0;j<WRITE_PORT_COUNT;j=j+1) begin
if (we[j]) begin
mem[wai[j]] <= di[j];
end
end
end
// Split read addresses
always @ (ra) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
rat[j]=ra[i*ADDRESS_WIDTH+j];
end
rai[i]=rat;
end
end
// guide read addresses using CE
always @ (posedge clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if ( ce[i] ) begin
rai_reg[i] <= rai[i];
end
end
end
// Memory read
always @ (rai_reg[0] or clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if (rai_reg[i] >= WORD_COUNT) begin
qt={DATA_WIDTH {1'b0}};
end else begin
qt=mem[rai_reg[i]];
end
for (j=0;j<DATA_WIDTH;j=j+1) begin
qi[i*DATA_WIDTH+j]=qt[j];
end
end
end
assign q=qi;
endmodule
`endcelldefine
module denoise_sn0_p3 (
address0,
ce0,
q0,
we0,
d0,
clk);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd225;
parameter AddressWidth = 32'd8;
input[AddressWidth-1:0] address0;
input ce0;
output[DataWidth-1:0] q0;
input we0;
input[DataWidth-1:0] d0;
input clk;
reg[DataWidth-1:0] q0;
wire[1 * DataWidth - 1:0] mem_q;
wire[DataWidth - 1:0] mem_q0;
wire[1 - 1:0] mem_we;
wire[1 * DataWidth - 1:0] mem_d;
wire[1 * AddressWidth - 1:0] mem_wa;
wire[1 * AddressWidth - 1:0] mem_ra;
wire[1 - 1:0] mem_ce;
denoise_sn0_p3_core #(
.READ_PORT_COUNT( 1 ),
.WRITE_PORT_COUNT( 1 ),
.DATA_WIDTH( DataWidth ),
.ADDRESS_WIDTH( AddressWidth ),
.WORD_COUNT( AddressRange ))
core_inst (
.q( mem_q ),
.ra( mem_ra ),
.ce( mem_ce ),
.d( mem_d ),
.wa( mem_wa ),
.we( mem_we ),
.clk( clk ));
assign mem_q0 = mem_q[1 * DataWidth - 1 : 0 * DataWidth];
always @ (mem_q0) begin
q0 = mem_q0;
end
assign mem_ra = {address0};
assign mem_ce = {ce0};
assign mem_we[0] = we0;
assign mem_d = {d0};
assign mem_wa = {address0};
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
`celldefine
module denoise_sn1_p0_core (q, ra, ce, clk, d, wa, we);
parameter READ_PORT_COUNT=32'd2;
parameter WRITE_PORT_COUNT=32'd1;
parameter DATA_WIDTH=32'd32;
parameter ADDRESS_WIDTH=32'd8;
parameter WORD_COUNT=32'd225;
output [READ_PORT_COUNT*DATA_WIDTH-1:0] q;
input [READ_PORT_COUNT*ADDRESS_WIDTH-1:0] ra;
input [READ_PORT_COUNT-1:0] ce;
input [WRITE_PORT_COUNT*DATA_WIDTH-1:0] d;
input [WRITE_PORT_COUNT*ADDRESS_WIDTH-1:0] wa;
input [WRITE_PORT_COUNT-1:0] we;
input clk;
integer i,j,k;
reg [DATA_WIDTH-1:0] mem [0:WORD_COUNT-1];
reg [ADDRESS_WIDTH-1:0] rat;
reg [ADDRESS_WIDTH-1:0] rai [READ_PORT_COUNT-1:0];
reg [ADDRESS_WIDTH-1:0] rai_reg [READ_PORT_COUNT-1:0];
reg [READ_PORT_COUNT*DATA_WIDTH-1:0] qi;
reg [DATA_WIDTH-1:0] qt;
reg [DATA_WIDTH-1:0] di [WRITE_PORT_COUNT-1:0];
reg [DATA_WIDTH-1:0] dt;
reg [ADDRESS_WIDTH-1:0] wat;
reg [ADDRESS_WIDTH-1:0] wai [WRITE_PORT_COUNT-1:0];
// Split input data
always @ (d) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<DATA_WIDTH;j=j+1) begin
dt[j]=d[i*DATA_WIDTH+j];
end
di[i]=dt;
end
end
// Split write addresses
always @ (wa) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
wat[j]=wa[i*ADDRESS_WIDTH+j];
end
wai[i]=wat;
end
end
// Write memory
always @ (posedge clk) begin
for (j=0;j<WRITE_PORT_COUNT;j=j+1) begin
if (we[j]) begin
mem[wai[j]] <= di[j];
end
end
end
// Split read addresses
always @ (ra) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
rat[j]=ra[i*ADDRESS_WIDTH+j];
end
rai[i]=rat;
end
end
// guide read addresses using CE
always @ (posedge clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if ( ce[i] ) begin
rai_reg[i] <= rai[i];
end
end
end
// Memory read
always @ (rai_reg[0] or rai_reg[1] or clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if (rai_reg[i] >= WORD_COUNT) begin
qt={DATA_WIDTH {1'b0}};
end else begin
qt=mem[rai_reg[i]];
end
for (j=0;j<DATA_WIDTH;j=j+1) begin
qi[i*DATA_WIDTH+j]=qt[j];
end
end
end
assign q=qi;
endmodule
`endcelldefine
module denoise_sn1_p0 (
address0,
ce0,
q0,
we0,
d0,
address1,
ce1,
q1,
clk);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd225;
parameter AddressWidth = 32'd8;
input[AddressWidth-1:0] address0;
input ce0;
output[DataWidth-1:0] q0;
input we0;
input[DataWidth-1:0] d0;
input[AddressWidth-1:0] address1;
input ce1;
output[DataWidth-1:0] q1;
input clk;
reg[DataWidth-1:0] q0;
reg[DataWidth-1:0] q1;
wire[2 * DataWidth - 1:0] mem_q;
wire[DataWidth - 1:0] mem_q0;
wire[DataWidth - 1:0] mem_q1;
wire[1 - 1:0] mem_we;
wire[1 * DataWidth - 1:0] mem_d;
wire[1 * AddressWidth - 1:0] mem_wa;
wire[2 * AddressWidth - 1:0] mem_ra;
wire[2 - 1:0] mem_ce;
denoise_sn1_p0_core #(
.READ_PORT_COUNT( 2 ),
.WRITE_PORT_COUNT( 1 ),
.DATA_WIDTH( DataWidth ),
.ADDRESS_WIDTH( AddressWidth ),
.WORD_COUNT( AddressRange ))
core_inst (
.q( mem_q ),
.ra( mem_ra ),
.ce( mem_ce ),
.d( mem_d ),
.wa( mem_wa ),
.we( mem_we ),
.clk( clk ));
assign mem_q0 = mem_q[2 * DataWidth - 1 : 1 * DataWidth];
always @ (mem_q0) begin
q0 = mem_q0;
end
assign mem_q1 = mem_q[1 * DataWidth - 1 : 0 * DataWidth];
always @ (mem_q1) begin
q1 = mem_q1;
end
assign mem_ra = {address0, address1};
assign mem_ce = {ce0, ce1};
assign mem_we[0] = we0;
assign mem_d = {d0};
assign mem_wa = {address0};
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
`celldefine
module denoise_sn1_p1_core (q, ra, ce, clk, d, wa, we);
parameter READ_PORT_COUNT=32'd1;
parameter WRITE_PORT_COUNT=32'd1;
parameter DATA_WIDTH=32'd32;
parameter ADDRESS_WIDTH=32'd8;
parameter WORD_COUNT=32'd225;
output [READ_PORT_COUNT*DATA_WIDTH-1:0] q;
input [READ_PORT_COUNT*ADDRESS_WIDTH-1:0] ra;
input [READ_PORT_COUNT-1:0] ce;
input [WRITE_PORT_COUNT*DATA_WIDTH-1:0] d;
input [WRITE_PORT_COUNT*ADDRESS_WIDTH-1:0] wa;
input [WRITE_PORT_COUNT-1:0] we;
input clk;
integer i,j,k;
reg [DATA_WIDTH-1:0] mem [0:WORD_COUNT-1];
reg [ADDRESS_WIDTH-1:0] rat;
reg [ADDRESS_WIDTH-1:0] rai [READ_PORT_COUNT-1:0];
reg [ADDRESS_WIDTH-1:0] rai_reg [READ_PORT_COUNT-1:0];
reg [READ_PORT_COUNT*DATA_WIDTH-1:0] qi;
reg [DATA_WIDTH-1:0] qt;
reg [DATA_WIDTH-1:0] di [WRITE_PORT_COUNT-1:0];
reg [DATA_WIDTH-1:0] dt;
reg [ADDRESS_WIDTH-1:0] wat;
reg [ADDRESS_WIDTH-1:0] wai [WRITE_PORT_COUNT-1:0];
// Split input data
always @ (d) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<DATA_WIDTH;j=j+1) begin
dt[j]=d[i*DATA_WIDTH+j];
end
di[i]=dt;
end
end
// Split write addresses
always @ (wa) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
wat[j]=wa[i*ADDRESS_WIDTH+j];
end
wai[i]=wat;
end
end
// Write memory
always @ (posedge clk) begin
for (j=0;j<WRITE_PORT_COUNT;j=j+1) begin
if (we[j]) begin
mem[wai[j]] <= di[j];
end
end
end
// Split read addresses
always @ (ra) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
rat[j]=ra[i*ADDRESS_WIDTH+j];
end
rai[i]=rat;
end
end
// guide read addresses using CE
always @ (posedge clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if ( ce[i] ) begin
rai_reg[i] <= rai[i];
end
end
end
// Memory read
always @ (rai_reg[0] or clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if (rai_reg[i] >= WORD_COUNT) begin
qt={DATA_WIDTH {1'b0}};
end else begin
qt=mem[rai_reg[i]];
end
for (j=0;j<DATA_WIDTH;j=j+1) begin
qi[i*DATA_WIDTH+j]=qt[j];
end
end
end
assign q=qi;
endmodule
`endcelldefine
module denoise_sn1_p1 (
address0,
ce0,
q0,
we0,
d0,
clk);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd225;
parameter AddressWidth = 32'd8;
input[AddressWidth-1:0] address0;
input ce0;
output[DataWidth-1:0] q0;
input we0;
input[DataWidth-1:0] d0;
input clk;
reg[DataWidth-1:0] q0;
wire[1 * DataWidth - 1:0] mem_q;
wire[DataWidth - 1:0] mem_q0;
wire[1 - 1:0] mem_we;
wire[1 * DataWidth - 1:0] mem_d;
wire[1 * AddressWidth - 1:0] mem_wa;
wire[1 * AddressWidth - 1:0] mem_ra;
wire[1 - 1:0] mem_ce;
denoise_sn1_p1_core #(
.READ_PORT_COUNT( 1 ),
.WRITE_PORT_COUNT( 1 ),
.DATA_WIDTH( DataWidth ),
.ADDRESS_WIDTH( AddressWidth ),
.WORD_COUNT( AddressRange ))
core_inst (
.q( mem_q ),
.ra( mem_ra ),
.ce( mem_ce ),
.d( mem_d ),
.wa( mem_wa ),
.we( mem_we ),
.clk( clk ));
assign mem_q0 = mem_q[1 * DataWidth - 1 : 0 * DataWidth];
always @ (mem_q0) begin
q0 = mem_q0;
end
assign mem_ra = {address0};
assign mem_ce = {ce0};
assign mem_we[0] = we0;
assign mem_d = {d0};
assign mem_wa = {address0};
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
`celldefine
module denoise_sn1_p2_core (q, ra, ce, clk, d, wa, we);
parameter READ_PORT_COUNT=32'd1;
parameter WRITE_PORT_COUNT=32'd1;
parameter DATA_WIDTH=32'd32;
parameter ADDRESS_WIDTH=32'd8;
parameter WORD_COUNT=32'd225;
output [READ_PORT_COUNT*DATA_WIDTH-1:0] q;
input [READ_PORT_COUNT*ADDRESS_WIDTH-1:0] ra;
input [READ_PORT_COUNT-1:0] ce;
input [WRITE_PORT_COUNT*DATA_WIDTH-1:0] d;
input [WRITE_PORT_COUNT*ADDRESS_WIDTH-1:0] wa;
input [WRITE_PORT_COUNT-1:0] we;
input clk;
integer i,j,k;
reg [DATA_WIDTH-1:0] mem [0:WORD_COUNT-1];
reg [ADDRESS_WIDTH-1:0] rat;
reg [ADDRESS_WIDTH-1:0] rai [READ_PORT_COUNT-1:0];
reg [ADDRESS_WIDTH-1:0] rai_reg [READ_PORT_COUNT-1:0];
reg [READ_PORT_COUNT*DATA_WIDTH-1:0] qi;
reg [DATA_WIDTH-1:0] qt;
reg [DATA_WIDTH-1:0] di [WRITE_PORT_COUNT-1:0];
reg [DATA_WIDTH-1:0] dt;
reg [ADDRESS_WIDTH-1:0] wat;
reg [ADDRESS_WIDTH-1:0] wai [WRITE_PORT_COUNT-1:0];
// Split input data
always @ (d) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<DATA_WIDTH;j=j+1) begin
dt[j]=d[i*DATA_WIDTH+j];
end
di[i]=dt;
end
end
// Split write addresses
always @ (wa) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
wat[j]=wa[i*ADDRESS_WIDTH+j];
end
wai[i]=wat;
end
end
// Write memory
always @ (posedge clk) begin
for (j=0;j<WRITE_PORT_COUNT;j=j+1) begin
if (we[j]) begin
mem[wai[j]] <= di[j];
end
end
end
// Split read addresses
always @ (ra) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
rat[j]=ra[i*ADDRESS_WIDTH+j];
end
rai[i]=rat;
end
end
// guide read addresses using CE
always @ (posedge clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if ( ce[i] ) begin
rai_reg[i] <= rai[i];
end
end
end
// Memory read
always @ (rai_reg[0] or clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if (rai_reg[i] >= WORD_COUNT) begin
qt={DATA_WIDTH {1'b0}};
end else begin
qt=mem[rai_reg[i]];
end
for (j=0;j<DATA_WIDTH;j=j+1) begin
qi[i*DATA_WIDTH+j]=qt[j];
end
end
end
assign q=qi;
endmodule
`endcelldefine
module denoise_sn1_p2 (
address0,
ce0,
q0,
we0,
d0,
clk);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd225;
parameter AddressWidth = 32'd8;
input[AddressWidth-1:0] address0;
input ce0;
output[DataWidth-1:0] q0;
input we0;
input[DataWidth-1:0] d0;
input clk;
reg[DataWidth-1:0] q0;
wire[1 * DataWidth - 1:0] mem_q;
wire[DataWidth - 1:0] mem_q0;
wire[1 - 1:0] mem_we;
wire[1 * DataWidth - 1:0] mem_d;
wire[1 * AddressWidth - 1:0] mem_wa;
wire[1 * AddressWidth - 1:0] mem_ra;
wire[1 - 1:0] mem_ce;
denoise_sn1_p2_core #(
.READ_PORT_COUNT( 1 ),
.WRITE_PORT_COUNT( 1 ),
.DATA_WIDTH( DataWidth ),
.ADDRESS_WIDTH( AddressWidth ),
.WORD_COUNT( AddressRange ))
core_inst (
.q( mem_q ),
.ra( mem_ra ),
.ce( mem_ce ),
.d( mem_d ),
.wa( mem_wa ),
.we( mem_we ),
.clk( clk ));
assign mem_q0 = mem_q[1 * DataWidth - 1 : 0 * DataWidth];
always @ (mem_q0) begin
q0 = mem_q0;
end
assign mem_ra = {address0};
assign mem_ce = {ce0};
assign mem_we[0] = we0;
assign mem_d = {d0};
assign mem_wa = {address0};
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
`celldefine
module denoise_sn1_p3_core (q, ra, ce, clk, d, wa, we);
parameter READ_PORT_COUNT=32'd1;
parameter WRITE_PORT_COUNT=32'd1;
parameter DATA_WIDTH=32'd32;
parameter ADDRESS_WIDTH=32'd8;
parameter WORD_COUNT=32'd225;
output [READ_PORT_COUNT*DATA_WIDTH-1:0] q;
input [READ_PORT_COUNT*ADDRESS_WIDTH-1:0] ra;
input [READ_PORT_COUNT-1:0] ce;
input [WRITE_PORT_COUNT*DATA_WIDTH-1:0] d;
input [WRITE_PORT_COUNT*ADDRESS_WIDTH-1:0] wa;
input [WRITE_PORT_COUNT-1:0] we;
input clk;
integer i,j,k;
reg [DATA_WIDTH-1:0] mem [0:WORD_COUNT-1];
reg [ADDRESS_WIDTH-1:0] rat;
reg [ADDRESS_WIDTH-1:0] rai [READ_PORT_COUNT-1:0];
reg [ADDRESS_WIDTH-1:0] rai_reg [READ_PORT_COUNT-1:0];
reg [READ_PORT_COUNT*DATA_WIDTH-1:0] qi;
reg [DATA_WIDTH-1:0] qt;
reg [DATA_WIDTH-1:0] di [WRITE_PORT_COUNT-1:0];
reg [DATA_WIDTH-1:0] dt;
reg [ADDRESS_WIDTH-1:0] wat;
reg [ADDRESS_WIDTH-1:0] wai [WRITE_PORT_COUNT-1:0];
// Split input data
always @ (d) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<DATA_WIDTH;j=j+1) begin
dt[j]=d[i*DATA_WIDTH+j];
end
di[i]=dt;
end
end
// Split write addresses
always @ (wa) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
wat[j]=wa[i*ADDRESS_WIDTH+j];
end
wai[i]=wat;
end
end
// Write memory
always @ (posedge clk) begin
for (j=0;j<WRITE_PORT_COUNT;j=j+1) begin
if (we[j]) begin
mem[wai[j]] <= di[j];
end
end
end
// Split read addresses
always @ (ra) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
rat[j]=ra[i*ADDRESS_WIDTH+j];
end
rai[i]=rat;
end
end
// guide read addresses using CE
always @ (posedge clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if ( ce[i] ) begin
rai_reg[i] <= rai[i];
end
end
end
// Memory read
always @ (rai_reg[0] or clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if (rai_reg[i] >= WORD_COUNT) begin
qt={DATA_WIDTH {1'b0}};
end else begin
qt=mem[rai_reg[i]];
end
for (j=0;j<DATA_WIDTH;j=j+1) begin
qi[i*DATA_WIDTH+j]=qt[j];
end
end
end
assign q=qi;
endmodule
`endcelldefine
module denoise_sn1_p3 (
address0,
ce0,
q0,
we0,
d0,
clk);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd225;
parameter AddressWidth = 32'd8;
input[AddressWidth-1:0] address0;
input ce0;
output[DataWidth-1:0] q0;
input we0;
input[DataWidth-1:0] d0;
input clk;
reg[DataWidth-1:0] q0;
wire[1 * DataWidth - 1:0] mem_q;
wire[DataWidth - 1:0] mem_q0;
wire[1 - 1:0] mem_we;
wire[1 * DataWidth - 1:0] mem_d;
wire[1 * AddressWidth - 1:0] mem_wa;
wire[1 * AddressWidth - 1:0] mem_ra;
wire[1 - 1:0] mem_ce;
denoise_sn1_p3_core #(
.READ_PORT_COUNT( 1 ),
.WRITE_PORT_COUNT( 1 ),
.DATA_WIDTH( DataWidth ),
.ADDRESS_WIDTH( AddressWidth ),
.WORD_COUNT( AddressRange ))
core_inst (
.q( mem_q ),
.ra( mem_ra ),
.ce( mem_ce ),
.d( mem_d ),
.wa( mem_wa ),
.we( mem_we ),
.clk( clk ));
assign mem_q0 = mem_q[1 * DataWidth - 1 : 0 * DataWidth];
always @ (mem_q0) begin
q0 = mem_q0;
end
assign mem_ra = {address0};
assign mem_ce = {ce0};
assign mem_we[0] = we0;
assign mem_d = {d0};
assign mem_wa = {address0};
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
`celldefine
module denoise_sp0_p0_core (q, ra, ce, clk, d, wa, we);
parameter READ_PORT_COUNT=32'd1;
parameter WRITE_PORT_COUNT=32'd1;
parameter DATA_WIDTH=32'd32;
parameter ADDRESS_WIDTH=32'd8;
parameter WORD_COUNT=32'd225;
output [READ_PORT_COUNT*DATA_WIDTH-1:0] q;
input [READ_PORT_COUNT*ADDRESS_WIDTH-1:0] ra;
input [READ_PORT_COUNT-1:0] ce;
input [WRITE_PORT_COUNT*DATA_WIDTH-1:0] d;
input [WRITE_PORT_COUNT*ADDRESS_WIDTH-1:0] wa;
input [WRITE_PORT_COUNT-1:0] we;
input clk;
integer i,j,k;
reg [DATA_WIDTH-1:0] mem [0:WORD_COUNT-1];
reg [ADDRESS_WIDTH-1:0] rat;
reg [ADDRESS_WIDTH-1:0] rai [READ_PORT_COUNT-1:0];
reg [ADDRESS_WIDTH-1:0] rai_reg [READ_PORT_COUNT-1:0];
reg [READ_PORT_COUNT*DATA_WIDTH-1:0] qi;
reg [DATA_WIDTH-1:0] qt;
reg [DATA_WIDTH-1:0] di [WRITE_PORT_COUNT-1:0];
reg [DATA_WIDTH-1:0] dt;
reg [ADDRESS_WIDTH-1:0] wat;
reg [ADDRESS_WIDTH-1:0] wai [WRITE_PORT_COUNT-1:0];
// Split input data
always @ (d) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<DATA_WIDTH;j=j+1) begin
dt[j]=d[i*DATA_WIDTH+j];
end
di[i]=dt;
end
end
// Split write addresses
always @ (wa) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
wat[j]=wa[i*ADDRESS_WIDTH+j];
end
wai[i]=wat;
end
end
// Write memory
always @ (posedge clk) begin
for (j=0;j<WRITE_PORT_COUNT;j=j+1) begin
if (we[j]) begin
mem[wai[j]] <= di[j];
end
end
end
// Split read addresses
always @ (ra) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
rat[j]=ra[i*ADDRESS_WIDTH+j];
end
rai[i]=rat;
end
end
// guide read addresses using CE
always @ (posedge clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if ( ce[i] ) begin
rai_reg[i] <= rai[i];
end
end
end
// Memory read
always @ (rai_reg[0] or clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if (rai_reg[i] >= WORD_COUNT) begin
qt={DATA_WIDTH {1'b0}};
end else begin
qt=mem[rai_reg[i]];
end
for (j=0;j<DATA_WIDTH;j=j+1) begin
qi[i*DATA_WIDTH+j]=qt[j];
end
end
end
assign q=qi;
endmodule
`endcelldefine
module denoise_sp0_p0 (
address0,
ce0,
q0,
we0,
d0,
clk);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd225;
parameter AddressWidth = 32'd8;
input[AddressWidth-1:0] address0;
input ce0;
output[DataWidth-1:0] q0;
input we0;
input[DataWidth-1:0] d0;
input clk;
reg[DataWidth-1:0] q0;
wire[1 * DataWidth - 1:0] mem_q;
wire[DataWidth - 1:0] mem_q0;
wire[1 - 1:0] mem_we;
wire[1 * DataWidth - 1:0] mem_d;
wire[1 * AddressWidth - 1:0] mem_wa;
wire[1 * AddressWidth - 1:0] mem_ra;
wire[1 - 1:0] mem_ce;
denoise_sp0_p0_core #(
.READ_PORT_COUNT( 1 ),
.WRITE_PORT_COUNT( 1 ),
.DATA_WIDTH( DataWidth ),
.ADDRESS_WIDTH( AddressWidth ),
.WORD_COUNT( AddressRange ))
core_inst (
.q( mem_q ),
.ra( mem_ra ),
.ce( mem_ce ),
.d( mem_d ),
.wa( mem_wa ),
.we( mem_we ),
.clk( clk ));
assign mem_q0 = mem_q[1 * DataWidth - 1 : 0 * DataWidth];
always @ (mem_q0) begin
q0 = mem_q0;
end
assign mem_ra = {address0};
assign mem_ce = {ce0};
assign mem_we[0] = we0;
assign mem_d = {d0};
assign mem_wa = {address0};
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
`celldefine
module denoise_sp0_p1_core (q, ra, ce, clk, d, wa, we);
parameter READ_PORT_COUNT=32'd1;
parameter WRITE_PORT_COUNT=32'd1;
parameter DATA_WIDTH=32'd32;
parameter ADDRESS_WIDTH=32'd8;
parameter WORD_COUNT=32'd225;
output [READ_PORT_COUNT*DATA_WIDTH-1:0] q;
input [READ_PORT_COUNT*ADDRESS_WIDTH-1:0] ra;
input [READ_PORT_COUNT-1:0] ce;
input [WRITE_PORT_COUNT*DATA_WIDTH-1:0] d;
input [WRITE_PORT_COUNT*ADDRESS_WIDTH-1:0] wa;
input [WRITE_PORT_COUNT-1:0] we;
input clk;
integer i,j,k;
reg [DATA_WIDTH-1:0] mem [0:WORD_COUNT-1];
reg [ADDRESS_WIDTH-1:0] rat;
reg [ADDRESS_WIDTH-1:0] rai [READ_PORT_COUNT-1:0];
reg [ADDRESS_WIDTH-1:0] rai_reg [READ_PORT_COUNT-1:0];
reg [READ_PORT_COUNT*DATA_WIDTH-1:0] qi;
reg [DATA_WIDTH-1:0] qt;
reg [DATA_WIDTH-1:0] di [WRITE_PORT_COUNT-1:0];
reg [DATA_WIDTH-1:0] dt;
reg [ADDRESS_WIDTH-1:0] wat;
reg [ADDRESS_WIDTH-1:0] wai [WRITE_PORT_COUNT-1:0];
// Split input data
always @ (d) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<DATA_WIDTH;j=j+1) begin
dt[j]=d[i*DATA_WIDTH+j];
end
di[i]=dt;
end
end
// Split write addresses
always @ (wa) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
wat[j]=wa[i*ADDRESS_WIDTH+j];
end
wai[i]=wat;
end
end
// Write memory
always @ (posedge clk) begin
for (j=0;j<WRITE_PORT_COUNT;j=j+1) begin
if (we[j]) begin
mem[wai[j]] <= di[j];
end
end
end
// Split read addresses
always @ (ra) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
rat[j]=ra[i*ADDRESS_WIDTH+j];
end
rai[i]=rat;
end
end
// guide read addresses using CE
always @ (posedge clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if ( ce[i] ) begin
rai_reg[i] <= rai[i];
end
end
end
// Memory read
always @ (rai_reg[0] or clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if (rai_reg[i] >= WORD_COUNT) begin
qt={DATA_WIDTH {1'b0}};
end else begin
qt=mem[rai_reg[i]];
end
for (j=0;j<DATA_WIDTH;j=j+1) begin
qi[i*DATA_WIDTH+j]=qt[j];
end
end
end
assign q=qi;
endmodule
`endcelldefine
module denoise_sp0_p1 (
address0,
ce0,
q0,
we0,
d0,
clk);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd225;
parameter AddressWidth = 32'd8;
input[AddressWidth-1:0] address0;
input ce0;
output[DataWidth-1:0] q0;
input we0;
input[DataWidth-1:0] d0;
input clk;
reg[DataWidth-1:0] q0;
wire[1 * DataWidth - 1:0] mem_q;
wire[DataWidth - 1:0] mem_q0;
wire[1 - 1:0] mem_we;
wire[1 * DataWidth - 1:0] mem_d;
wire[1 * AddressWidth - 1:0] mem_wa;
wire[1 * AddressWidth - 1:0] mem_ra;
wire[1 - 1:0] mem_ce;
denoise_sp0_p1_core #(
.READ_PORT_COUNT( 1 ),
.WRITE_PORT_COUNT( 1 ),
.DATA_WIDTH( DataWidth ),
.ADDRESS_WIDTH( AddressWidth ),
.WORD_COUNT( AddressRange ))
core_inst (
.q( mem_q ),
.ra( mem_ra ),
.ce( mem_ce ),
.d( mem_d ),
.wa( mem_wa ),
.we( mem_we ),
.clk( clk ));
assign mem_q0 = mem_q[1 * DataWidth - 1 : 0 * DataWidth];
always @ (mem_q0) begin
q0 = mem_q0;
end
assign mem_ra = {address0};
assign mem_ce = {ce0};
assign mem_we[0] = we0;
assign mem_d = {d0};
assign mem_wa = {address0};
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
`celldefine
module denoise_sp0_p2_core (q, ra, ce, clk, d, wa, we);
parameter READ_PORT_COUNT=32'd1;
parameter WRITE_PORT_COUNT=32'd1;
parameter DATA_WIDTH=32'd32;
parameter ADDRESS_WIDTH=32'd8;
parameter WORD_COUNT=32'd225;
output [READ_PORT_COUNT*DATA_WIDTH-1:0] q;
input [READ_PORT_COUNT*ADDRESS_WIDTH-1:0] ra;
input [READ_PORT_COUNT-1:0] ce;
input [WRITE_PORT_COUNT*DATA_WIDTH-1:0] d;
input [WRITE_PORT_COUNT*ADDRESS_WIDTH-1:0] wa;
input [WRITE_PORT_COUNT-1:0] we;
input clk;
integer i,j,k;
reg [DATA_WIDTH-1:0] mem [0:WORD_COUNT-1];
reg [ADDRESS_WIDTH-1:0] rat;
reg [ADDRESS_WIDTH-1:0] rai [READ_PORT_COUNT-1:0];
reg [ADDRESS_WIDTH-1:0] rai_reg [READ_PORT_COUNT-1:0];
reg [READ_PORT_COUNT*DATA_WIDTH-1:0] qi;
reg [DATA_WIDTH-1:0] qt;
reg [DATA_WIDTH-1:0] di [WRITE_PORT_COUNT-1:0];
reg [DATA_WIDTH-1:0] dt;
reg [ADDRESS_WIDTH-1:0] wat;
reg [ADDRESS_WIDTH-1:0] wai [WRITE_PORT_COUNT-1:0];
// Split input data
always @ (d) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<DATA_WIDTH;j=j+1) begin
dt[j]=d[i*DATA_WIDTH+j];
end
di[i]=dt;
end
end
// Split write addresses
always @ (wa) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
wat[j]=wa[i*ADDRESS_WIDTH+j];
end
wai[i]=wat;
end
end
// Write memory
always @ (posedge clk) begin
for (j=0;j<WRITE_PORT_COUNT;j=j+1) begin
if (we[j]) begin
mem[wai[j]] <= di[j];
end
end
end
// Split read addresses
always @ (ra) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
rat[j]=ra[i*ADDRESS_WIDTH+j];
end
rai[i]=rat;
end
end
// guide read addresses using CE
always @ (posedge clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if ( ce[i] ) begin
rai_reg[i] <= rai[i];
end
end
end
// Memory read
always @ (rai_reg[0] or clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if (rai_reg[i] >= WORD_COUNT) begin
qt={DATA_WIDTH {1'b0}};
end else begin
qt=mem[rai_reg[i]];
end
for (j=0;j<DATA_WIDTH;j=j+1) begin
qi[i*DATA_WIDTH+j]=qt[j];
end
end
end
assign q=qi;
endmodule
`endcelldefine
module denoise_sp0_p2 (
address0,
ce0,
q0,
we0,
d0,
clk);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd225;
parameter AddressWidth = 32'd8;
input[AddressWidth-1:0] address0;
input ce0;
output[DataWidth-1:0] q0;
input we0;
input[DataWidth-1:0] d0;
input clk;
reg[DataWidth-1:0] q0;
wire[1 * DataWidth - 1:0] mem_q;
wire[DataWidth - 1:0] mem_q0;
wire[1 - 1:0] mem_we;
wire[1 * DataWidth - 1:0] mem_d;
wire[1 * AddressWidth - 1:0] mem_wa;
wire[1 * AddressWidth - 1:0] mem_ra;
wire[1 - 1:0] mem_ce;
denoise_sp0_p2_core #(
.READ_PORT_COUNT( 1 ),
.WRITE_PORT_COUNT( 1 ),
.DATA_WIDTH( DataWidth ),
.ADDRESS_WIDTH( AddressWidth ),
.WORD_COUNT( AddressRange ))
core_inst (
.q( mem_q ),
.ra( mem_ra ),
.ce( mem_ce ),
.d( mem_d ),
.wa( mem_wa ),
.we( mem_we ),
.clk( clk ));
assign mem_q0 = mem_q[1 * DataWidth - 1 : 0 * DataWidth];
always @ (mem_q0) begin
q0 = mem_q0;
end
assign mem_ra = {address0};
assign mem_ce = {ce0};
assign mem_we[0] = we0;
assign mem_d = {d0};
assign mem_wa = {address0};
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
`celldefine
module denoise_sp0_p3_core (q, ra, ce, clk, d, wa, we);
parameter READ_PORT_COUNT=32'd1;
parameter WRITE_PORT_COUNT=32'd1;
parameter DATA_WIDTH=32'd32;
parameter ADDRESS_WIDTH=32'd8;
parameter WORD_COUNT=32'd225;
output [READ_PORT_COUNT*DATA_WIDTH-1:0] q;
input [READ_PORT_COUNT*ADDRESS_WIDTH-1:0] ra;
input [READ_PORT_COUNT-1:0] ce;
input [WRITE_PORT_COUNT*DATA_WIDTH-1:0] d;
input [WRITE_PORT_COUNT*ADDRESS_WIDTH-1:0] wa;
input [WRITE_PORT_COUNT-1:0] we;
input clk;
integer i,j,k;
reg [DATA_WIDTH-1:0] mem [0:WORD_COUNT-1];
reg [ADDRESS_WIDTH-1:0] rat;
reg [ADDRESS_WIDTH-1:0] rai [READ_PORT_COUNT-1:0];
reg [ADDRESS_WIDTH-1:0] rai_reg [READ_PORT_COUNT-1:0];
reg [READ_PORT_COUNT*DATA_WIDTH-1:0] qi;
reg [DATA_WIDTH-1:0] qt;
reg [DATA_WIDTH-1:0] di [WRITE_PORT_COUNT-1:0];
reg [DATA_WIDTH-1:0] dt;
reg [ADDRESS_WIDTH-1:0] wat;
reg [ADDRESS_WIDTH-1:0] wai [WRITE_PORT_COUNT-1:0];
// Split input data
always @ (d) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<DATA_WIDTH;j=j+1) begin
dt[j]=d[i*DATA_WIDTH+j];
end
di[i]=dt;
end
end
// Split write addresses
always @ (wa) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
wat[j]=wa[i*ADDRESS_WIDTH+j];
end
wai[i]=wat;
end
end
// Write memory
always @ (posedge clk) begin
for (j=0;j<WRITE_PORT_COUNT;j=j+1) begin
if (we[j]) begin
mem[wai[j]] <= di[j];
end
end
end
// Split read addresses
always @ (ra) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
rat[j]=ra[i*ADDRESS_WIDTH+j];
end
rai[i]=rat;
end
end
// guide read addresses using CE
always @ (posedge clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if ( ce[i] ) begin
rai_reg[i] <= rai[i];
end
end
end
// Memory read
always @ (rai_reg[0] or clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if (rai_reg[i] >= WORD_COUNT) begin
qt={DATA_WIDTH {1'b0}};
end else begin
qt=mem[rai_reg[i]];
end
for (j=0;j<DATA_WIDTH;j=j+1) begin
qi[i*DATA_WIDTH+j]=qt[j];
end
end
end
assign q=qi;
endmodule
`endcelldefine
module denoise_sp0_p3 (
address0,
ce0,
q0,
we0,
d0,
clk);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd225;
parameter AddressWidth = 32'd8;
input[AddressWidth-1:0] address0;
input ce0;
output[DataWidth-1:0] q0;
input we0;
input[DataWidth-1:0] d0;
input clk;
reg[DataWidth-1:0] q0;
wire[1 * DataWidth - 1:0] mem_q;
wire[DataWidth - 1:0] mem_q0;
wire[1 - 1:0] mem_we;
wire[1 * DataWidth - 1:0] mem_d;
wire[1 * AddressWidth - 1:0] mem_wa;
wire[1 * AddressWidth - 1:0] mem_ra;
wire[1 - 1:0] mem_ce;
denoise_sp0_p3_core #(
.READ_PORT_COUNT( 1 ),
.WRITE_PORT_COUNT( 1 ),
.DATA_WIDTH( DataWidth ),
.ADDRESS_WIDTH( AddressWidth ),
.WORD_COUNT( AddressRange ))
core_inst (
.q( mem_q ),
.ra( mem_ra ),
.ce( mem_ce ),
.d( mem_d ),
.wa( mem_wa ),
.we( mem_we ),
.clk( clk ));
assign mem_q0 = mem_q[1 * DataWidth - 1 : 0 * DataWidth];
always @ (mem_q0) begin
q0 = mem_q0;
end
assign mem_ra = {address0};
assign mem_ce = {ce0};
assign mem_we[0] = we0;
assign mem_d = {d0};
assign mem_wa = {address0};
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
`celldefine
module denoise_sp1_p0_core (q, ra, ce, clk, d, wa, we);
parameter READ_PORT_COUNT=32'd1;
parameter WRITE_PORT_COUNT=32'd1;
parameter DATA_WIDTH=32'd32;
parameter ADDRESS_WIDTH=32'd8;
parameter WORD_COUNT=32'd225;
output [READ_PORT_COUNT*DATA_WIDTH-1:0] q;
input [READ_PORT_COUNT*ADDRESS_WIDTH-1:0] ra;
input [READ_PORT_COUNT-1:0] ce;
input [WRITE_PORT_COUNT*DATA_WIDTH-1:0] d;
input [WRITE_PORT_COUNT*ADDRESS_WIDTH-1:0] wa;
input [WRITE_PORT_COUNT-1:0] we;
input clk;
integer i,j,k;
reg [DATA_WIDTH-1:0] mem [0:WORD_COUNT-1];
reg [ADDRESS_WIDTH-1:0] rat;
reg [ADDRESS_WIDTH-1:0] rai [READ_PORT_COUNT-1:0];
reg [ADDRESS_WIDTH-1:0] rai_reg [READ_PORT_COUNT-1:0];
reg [READ_PORT_COUNT*DATA_WIDTH-1:0] qi;
reg [DATA_WIDTH-1:0] qt;
reg [DATA_WIDTH-1:0] di [WRITE_PORT_COUNT-1:0];
reg [DATA_WIDTH-1:0] dt;
reg [ADDRESS_WIDTH-1:0] wat;
reg [ADDRESS_WIDTH-1:0] wai [WRITE_PORT_COUNT-1:0];
// Split input data
always @ (d) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<DATA_WIDTH;j=j+1) begin
dt[j]=d[i*DATA_WIDTH+j];
end
di[i]=dt;
end
end
// Split write addresses
always @ (wa) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
wat[j]=wa[i*ADDRESS_WIDTH+j];
end
wai[i]=wat;
end
end
// Write memory
always @ (posedge clk) begin
for (j=0;j<WRITE_PORT_COUNT;j=j+1) begin
if (we[j]) begin
mem[wai[j]] <= di[j];
end
end
end
// Split read addresses
always @ (ra) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
rat[j]=ra[i*ADDRESS_WIDTH+j];
end
rai[i]=rat;
end
end
// guide read addresses using CE
always @ (posedge clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if ( ce[i] ) begin
rai_reg[i] <= rai[i];
end
end
end
// Memory read
always @ (rai_reg[0] or clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if (rai_reg[i] >= WORD_COUNT) begin
qt={DATA_WIDTH {1'b0}};
end else begin
qt=mem[rai_reg[i]];
end
for (j=0;j<DATA_WIDTH;j=j+1) begin
qi[i*DATA_WIDTH+j]=qt[j];
end
end
end
assign q=qi;
endmodule
`endcelldefine
module denoise_sp1_p0 (
address0,
ce0,
q0,
we0,
d0,
clk);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd225;
parameter AddressWidth = 32'd8;
input[AddressWidth-1:0] address0;
input ce0;
output[DataWidth-1:0] q0;
input we0;
input[DataWidth-1:0] d0;
input clk;
reg[DataWidth-1:0] q0;
wire[1 * DataWidth - 1:0] mem_q;
wire[DataWidth - 1:0] mem_q0;
wire[1 - 1:0] mem_we;
wire[1 * DataWidth - 1:0] mem_d;
wire[1 * AddressWidth - 1:0] mem_wa;
wire[1 * AddressWidth - 1:0] mem_ra;
wire[1 - 1:0] mem_ce;
denoise_sp1_p0_core #(
.READ_PORT_COUNT( 1 ),
.WRITE_PORT_COUNT( 1 ),
.DATA_WIDTH( DataWidth ),
.ADDRESS_WIDTH( AddressWidth ),
.WORD_COUNT( AddressRange ))
core_inst (
.q( mem_q ),
.ra( mem_ra ),
.ce( mem_ce ),
.d( mem_d ),
.wa( mem_wa ),
.we( mem_we ),
.clk( clk ));
assign mem_q0 = mem_q[1 * DataWidth - 1 : 0 * DataWidth];
always @ (mem_q0) begin
q0 = mem_q0;
end
assign mem_ra = {address0};
assign mem_ce = {ce0};
assign mem_we[0] = we0;
assign mem_d = {d0};
assign mem_wa = {address0};
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
`celldefine
module denoise_sp1_p1_core (q, ra, ce, clk, d, wa, we);
parameter READ_PORT_COUNT=32'd1;
parameter WRITE_PORT_COUNT=32'd1;
parameter DATA_WIDTH=32'd32;
parameter ADDRESS_WIDTH=32'd8;
parameter WORD_COUNT=32'd225;
output [READ_PORT_COUNT*DATA_WIDTH-1:0] q;
input [READ_PORT_COUNT*ADDRESS_WIDTH-1:0] ra;
input [READ_PORT_COUNT-1:0] ce;
input [WRITE_PORT_COUNT*DATA_WIDTH-1:0] d;
input [WRITE_PORT_COUNT*ADDRESS_WIDTH-1:0] wa;
input [WRITE_PORT_COUNT-1:0] we;
input clk;
integer i,j,k;
reg [DATA_WIDTH-1:0] mem [0:WORD_COUNT-1];
reg [ADDRESS_WIDTH-1:0] rat;
reg [ADDRESS_WIDTH-1:0] rai [READ_PORT_COUNT-1:0];
reg [ADDRESS_WIDTH-1:0] rai_reg [READ_PORT_COUNT-1:0];
reg [READ_PORT_COUNT*DATA_WIDTH-1:0] qi;
reg [DATA_WIDTH-1:0] qt;
reg [DATA_WIDTH-1:0] di [WRITE_PORT_COUNT-1:0];
reg [DATA_WIDTH-1:0] dt;
reg [ADDRESS_WIDTH-1:0] wat;
reg [ADDRESS_WIDTH-1:0] wai [WRITE_PORT_COUNT-1:0];
// Split input data
always @ (d) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<DATA_WIDTH;j=j+1) begin
dt[j]=d[i*DATA_WIDTH+j];
end
di[i]=dt;
end
end
// Split write addresses
always @ (wa) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
wat[j]=wa[i*ADDRESS_WIDTH+j];
end
wai[i]=wat;
end
end
// Write memory
always @ (posedge clk) begin
for (j=0;j<WRITE_PORT_COUNT;j=j+1) begin
if (we[j]) begin
mem[wai[j]] <= di[j];
end
end
end
// Split read addresses
always @ (ra) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
rat[j]=ra[i*ADDRESS_WIDTH+j];
end
rai[i]=rat;
end
end
// guide read addresses using CE
always @ (posedge clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if ( ce[i] ) begin
rai_reg[i] <= rai[i];
end
end
end
// Memory read
always @ (rai_reg[0] or clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if (rai_reg[i] >= WORD_COUNT) begin
qt={DATA_WIDTH {1'b0}};
end else begin
qt=mem[rai_reg[i]];
end
for (j=0;j<DATA_WIDTH;j=j+1) begin
qi[i*DATA_WIDTH+j]=qt[j];
end
end
end
assign q=qi;
endmodule
`endcelldefine
module denoise_sp1_p1 (
address0,
ce0,
q0,
we0,
d0,
clk);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd225;
parameter AddressWidth = 32'd8;
input[AddressWidth-1:0] address0;
input ce0;
output[DataWidth-1:0] q0;
input we0;
input[DataWidth-1:0] d0;
input clk;
reg[DataWidth-1:0] q0;
wire[1 * DataWidth - 1:0] mem_q;
wire[DataWidth - 1:0] mem_q0;
wire[1 - 1:0] mem_we;
wire[1 * DataWidth - 1:0] mem_d;
wire[1 * AddressWidth - 1:0] mem_wa;
wire[1 * AddressWidth - 1:0] mem_ra;
wire[1 - 1:0] mem_ce;
denoise_sp1_p1_core #(
.READ_PORT_COUNT( 1 ),
.WRITE_PORT_COUNT( 1 ),
.DATA_WIDTH( DataWidth ),
.ADDRESS_WIDTH( AddressWidth ),
.WORD_COUNT( AddressRange ))
core_inst (
.q( mem_q ),
.ra( mem_ra ),
.ce( mem_ce ),
.d( mem_d ),
.wa( mem_wa ),
.we( mem_we ),
.clk( clk ));
assign mem_q0 = mem_q[1 * DataWidth - 1 : 0 * DataWidth];
always @ (mem_q0) begin
q0 = mem_q0;
end
assign mem_ra = {address0};
assign mem_ce = {ce0};
assign mem_we[0] = we0;
assign mem_d = {d0};
assign mem_wa = {address0};
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
`celldefine
module denoise_sp1_p2_core (q, ra, ce, clk, d, wa, we);
parameter READ_PORT_COUNT=32'd1;
parameter WRITE_PORT_COUNT=32'd1;
parameter DATA_WIDTH=32'd32;
parameter ADDRESS_WIDTH=32'd8;
parameter WORD_COUNT=32'd225;
output [READ_PORT_COUNT*DATA_WIDTH-1:0] q;
input [READ_PORT_COUNT*ADDRESS_WIDTH-1:0] ra;
input [READ_PORT_COUNT-1:0] ce;
input [WRITE_PORT_COUNT*DATA_WIDTH-1:0] d;
input [WRITE_PORT_COUNT*ADDRESS_WIDTH-1:0] wa;
input [WRITE_PORT_COUNT-1:0] we;
input clk;
integer i,j,k;
reg [DATA_WIDTH-1:0] mem [0:WORD_COUNT-1];
reg [ADDRESS_WIDTH-1:0] rat;
reg [ADDRESS_WIDTH-1:0] rai [READ_PORT_COUNT-1:0];
reg [ADDRESS_WIDTH-1:0] rai_reg [READ_PORT_COUNT-1:0];
reg [READ_PORT_COUNT*DATA_WIDTH-1:0] qi;
reg [DATA_WIDTH-1:0] qt;
reg [DATA_WIDTH-1:0] di [WRITE_PORT_COUNT-1:0];
reg [DATA_WIDTH-1:0] dt;
reg [ADDRESS_WIDTH-1:0] wat;
reg [ADDRESS_WIDTH-1:0] wai [WRITE_PORT_COUNT-1:0];
// Split input data
always @ (d) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<DATA_WIDTH;j=j+1) begin
dt[j]=d[i*DATA_WIDTH+j];
end
di[i]=dt;
end
end
// Split write addresses
always @ (wa) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
wat[j]=wa[i*ADDRESS_WIDTH+j];
end
wai[i]=wat;
end
end
// Write memory
always @ (posedge clk) begin
for (j=0;j<WRITE_PORT_COUNT;j=j+1) begin
if (we[j]) begin
mem[wai[j]] <= di[j];
end
end
end
// Split read addresses
always @ (ra) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
rat[j]=ra[i*ADDRESS_WIDTH+j];
end
rai[i]=rat;
end
end
// guide read addresses using CE
always @ (posedge clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if ( ce[i] ) begin
rai_reg[i] <= rai[i];
end
end
end
// Memory read
always @ (rai_reg[0] or clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if (rai_reg[i] >= WORD_COUNT) begin
qt={DATA_WIDTH {1'b0}};
end else begin
qt=mem[rai_reg[i]];
end
for (j=0;j<DATA_WIDTH;j=j+1) begin
qi[i*DATA_WIDTH+j]=qt[j];
end
end
end
assign q=qi;
endmodule
`endcelldefine
module denoise_sp1_p2 (
address0,
ce0,
q0,
we0,
d0,
clk);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd225;
parameter AddressWidth = 32'd8;
input[AddressWidth-1:0] address0;
input ce0;
output[DataWidth-1:0] q0;
input we0;
input[DataWidth-1:0] d0;
input clk;
reg[DataWidth-1:0] q0;
wire[1 * DataWidth - 1:0] mem_q;
wire[DataWidth - 1:0] mem_q0;
wire[1 - 1:0] mem_we;
wire[1 * DataWidth - 1:0] mem_d;
wire[1 * AddressWidth - 1:0] mem_wa;
wire[1 * AddressWidth - 1:0] mem_ra;
wire[1 - 1:0] mem_ce;
denoise_sp1_p2_core #(
.READ_PORT_COUNT( 1 ),
.WRITE_PORT_COUNT( 1 ),
.DATA_WIDTH( DataWidth ),
.ADDRESS_WIDTH( AddressWidth ),
.WORD_COUNT( AddressRange ))
core_inst (
.q( mem_q ),
.ra( mem_ra ),
.ce( mem_ce ),
.d( mem_d ),
.wa( mem_wa ),
.we( mem_we ),
.clk( clk ));
assign mem_q0 = mem_q[1 * DataWidth - 1 : 0 * DataWidth];
always @ (mem_q0) begin
q0 = mem_q0;
end
assign mem_ra = {address0};
assign mem_ce = {ce0};
assign mem_we[0] = we0;
assign mem_d = {d0};
assign mem_wa = {address0};
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
`celldefine
module denoise_sp1_p3_core (q, ra, ce, clk, d, wa, we);
parameter READ_PORT_COUNT=32'd1;
parameter WRITE_PORT_COUNT=32'd1;
parameter DATA_WIDTH=32'd32;
parameter ADDRESS_WIDTH=32'd8;
parameter WORD_COUNT=32'd225;
output [READ_PORT_COUNT*DATA_WIDTH-1:0] q;
input [READ_PORT_COUNT*ADDRESS_WIDTH-1:0] ra;
input [READ_PORT_COUNT-1:0] ce;
input [WRITE_PORT_COUNT*DATA_WIDTH-1:0] d;
input [WRITE_PORT_COUNT*ADDRESS_WIDTH-1:0] wa;
input [WRITE_PORT_COUNT-1:0] we;
input clk;
integer i,j,k;
reg [DATA_WIDTH-1:0] mem [0:WORD_COUNT-1];
reg [ADDRESS_WIDTH-1:0] rat;
reg [ADDRESS_WIDTH-1:0] rai [READ_PORT_COUNT-1:0];
reg [ADDRESS_WIDTH-1:0] rai_reg [READ_PORT_COUNT-1:0];
reg [READ_PORT_COUNT*DATA_WIDTH-1:0] qi;
reg [DATA_WIDTH-1:0] qt;
reg [DATA_WIDTH-1:0] di [WRITE_PORT_COUNT-1:0];
reg [DATA_WIDTH-1:0] dt;
reg [ADDRESS_WIDTH-1:0] wat;
reg [ADDRESS_WIDTH-1:0] wai [WRITE_PORT_COUNT-1:0];
// Split input data
always @ (d) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<DATA_WIDTH;j=j+1) begin
dt[j]=d[i*DATA_WIDTH+j];
end
di[i]=dt;
end
end
// Split write addresses
always @ (wa) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
wat[j]=wa[i*ADDRESS_WIDTH+j];
end
wai[i]=wat;
end
end
// Write memory
always @ (posedge clk) begin
for (j=0;j<WRITE_PORT_COUNT;j=j+1) begin
if (we[j]) begin
mem[wai[j]] <= di[j];
end
end
end
// Split read addresses
always @ (ra) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
rat[j]=ra[i*ADDRESS_WIDTH+j];
end
rai[i]=rat;
end
end
// guide read addresses using CE
always @ (posedge clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if ( ce[i] ) begin
rai_reg[i] <= rai[i];
end
end
end
// Memory read
always @ (rai_reg[0] or clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if (rai_reg[i] >= WORD_COUNT) begin
qt={DATA_WIDTH {1'b0}};
end else begin
qt=mem[rai_reg[i]];
end
for (j=0;j<DATA_WIDTH;j=j+1) begin
qi[i*DATA_WIDTH+j]=qt[j];
end
end
end
assign q=qi;
endmodule
`endcelldefine
module denoise_sp1_p3 (
address0,
ce0,
q0,
we0,
d0,
clk);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd225;
parameter AddressWidth = 32'd8;
input[AddressWidth-1:0] address0;
input ce0;
output[DataWidth-1:0] q0;
input we0;
input[DataWidth-1:0] d0;
input clk;
reg[DataWidth-1:0] q0;
wire[1 * DataWidth - 1:0] mem_q;
wire[DataWidth - 1:0] mem_q0;
wire[1 - 1:0] mem_we;
wire[1 * DataWidth - 1:0] mem_d;
wire[1 * AddressWidth - 1:0] mem_wa;
wire[1 * AddressWidth - 1:0] mem_ra;
wire[1 - 1:0] mem_ce;
denoise_sp1_p3_core #(
.READ_PORT_COUNT( 1 ),
.WRITE_PORT_COUNT( 1 ),
.DATA_WIDTH( DataWidth ),
.ADDRESS_WIDTH( AddressWidth ),
.WORD_COUNT( AddressRange ))
core_inst (
.q( mem_q ),
.ra( mem_ra ),
.ce( mem_ce ),
.d( mem_d ),
.wa( mem_wa ),
.we( mem_we ),
.clk( clk ));
assign mem_q0 = mem_q[1 * DataWidth - 1 : 0 * DataWidth];
always @ (mem_q0) begin
q0 = mem_q0;
end
assign mem_ra = {address0};
assign mem_ce = {ce0};
assign mem_we[0] = we0;
assign mem_d = {d0};
assign mem_wa = {address0};
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
`celldefine
module denoise_sp2_p0_core (q, ra, ce, clk, d, wa, we);
parameter READ_PORT_COUNT=32'd1;
parameter WRITE_PORT_COUNT=32'd1;
parameter DATA_WIDTH=32'd32;
parameter ADDRESS_WIDTH=32'd8;
parameter WORD_COUNT=32'd225;
output [READ_PORT_COUNT*DATA_WIDTH-1:0] q;
input [READ_PORT_COUNT*ADDRESS_WIDTH-1:0] ra;
input [READ_PORT_COUNT-1:0] ce;
input [WRITE_PORT_COUNT*DATA_WIDTH-1:0] d;
input [WRITE_PORT_COUNT*ADDRESS_WIDTH-1:0] wa;
input [WRITE_PORT_COUNT-1:0] we;
input clk;
integer i,j,k;
reg [DATA_WIDTH-1:0] mem [0:WORD_COUNT-1];
reg [ADDRESS_WIDTH-1:0] rat;
reg [ADDRESS_WIDTH-1:0] rai [READ_PORT_COUNT-1:0];
reg [ADDRESS_WIDTH-1:0] rai_reg [READ_PORT_COUNT-1:0];
reg [READ_PORT_COUNT*DATA_WIDTH-1:0] qi;
reg [DATA_WIDTH-1:0] qt;
reg [DATA_WIDTH-1:0] di [WRITE_PORT_COUNT-1:0];
reg [DATA_WIDTH-1:0] dt;
reg [ADDRESS_WIDTH-1:0] wat;
reg [ADDRESS_WIDTH-1:0] wai [WRITE_PORT_COUNT-1:0];
// Split input data
always @ (d) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<DATA_WIDTH;j=j+1) begin
dt[j]=d[i*DATA_WIDTH+j];
end
di[i]=dt;
end
end
// Split write addresses
always @ (wa) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
wat[j]=wa[i*ADDRESS_WIDTH+j];
end
wai[i]=wat;
end
end
// Write memory
always @ (posedge clk) begin
for (j=0;j<WRITE_PORT_COUNT;j=j+1) begin
if (we[j]) begin
mem[wai[j]] <= di[j];
end
end
end
// Split read addresses
always @ (ra) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
rat[j]=ra[i*ADDRESS_WIDTH+j];
end
rai[i]=rat;
end
end
// guide read addresses using CE
always @ (posedge clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if ( ce[i] ) begin
rai_reg[i] <= rai[i];
end
end
end
// Memory read
always @ (rai_reg[0] or clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if (rai_reg[i] >= WORD_COUNT) begin
qt={DATA_WIDTH {1'b0}};
end else begin
qt=mem[rai_reg[i]];
end
for (j=0;j<DATA_WIDTH;j=j+1) begin
qi[i*DATA_WIDTH+j]=qt[j];
end
end
end
assign q=qi;
endmodule
`endcelldefine
module denoise_sp2_p0 (
address0,
ce0,
q0,
we0,
d0,
clk);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd225;
parameter AddressWidth = 32'd8;
input[AddressWidth-1:0] address0;
input ce0;
output[DataWidth-1:0] q0;
input we0;
input[DataWidth-1:0] d0;
input clk;
reg[DataWidth-1:0] q0;
wire[1 * DataWidth - 1:0] mem_q;
wire[DataWidth - 1:0] mem_q0;
wire[1 - 1:0] mem_we;
wire[1 * DataWidth - 1:0] mem_d;
wire[1 * AddressWidth - 1:0] mem_wa;
wire[1 * AddressWidth - 1:0] mem_ra;
wire[1 - 1:0] mem_ce;
denoise_sp2_p0_core #(
.READ_PORT_COUNT( 1 ),
.WRITE_PORT_COUNT( 1 ),
.DATA_WIDTH( DataWidth ),
.ADDRESS_WIDTH( AddressWidth ),
.WORD_COUNT( AddressRange ))
core_inst (
.q( mem_q ),
.ra( mem_ra ),
.ce( mem_ce ),
.d( mem_d ),
.wa( mem_wa ),
.we( mem_we ),
.clk( clk ));
assign mem_q0 = mem_q[1 * DataWidth - 1 : 0 * DataWidth];
always @ (mem_q0) begin
q0 = mem_q0;
end
assign mem_ra = {address0};
assign mem_ce = {ce0};
assign mem_we[0] = we0;
assign mem_d = {d0};
assign mem_wa = {address0};
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
`celldefine
module denoise_sp2_p1_core (q, ra, ce, clk, d, wa, we);
parameter READ_PORT_COUNT=32'd1;
parameter WRITE_PORT_COUNT=32'd1;
parameter DATA_WIDTH=32'd32;
parameter ADDRESS_WIDTH=32'd8;
parameter WORD_COUNT=32'd225;
output [READ_PORT_COUNT*DATA_WIDTH-1:0] q;
input [READ_PORT_COUNT*ADDRESS_WIDTH-1:0] ra;
input [READ_PORT_COUNT-1:0] ce;
input [WRITE_PORT_COUNT*DATA_WIDTH-1:0] d;
input [WRITE_PORT_COUNT*ADDRESS_WIDTH-1:0] wa;
input [WRITE_PORT_COUNT-1:0] we;
input clk;
integer i,j,k;
reg [DATA_WIDTH-1:0] mem [0:WORD_COUNT-1];
reg [ADDRESS_WIDTH-1:0] rat;
reg [ADDRESS_WIDTH-1:0] rai [READ_PORT_COUNT-1:0];
reg [ADDRESS_WIDTH-1:0] rai_reg [READ_PORT_COUNT-1:0];
reg [READ_PORT_COUNT*DATA_WIDTH-1:0] qi;
reg [DATA_WIDTH-1:0] qt;
reg [DATA_WIDTH-1:0] di [WRITE_PORT_COUNT-1:0];
reg [DATA_WIDTH-1:0] dt;
reg [ADDRESS_WIDTH-1:0] wat;
reg [ADDRESS_WIDTH-1:0] wai [WRITE_PORT_COUNT-1:0];
// Split input data
always @ (d) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<DATA_WIDTH;j=j+1) begin
dt[j]=d[i*DATA_WIDTH+j];
end
di[i]=dt;
end
end
// Split write addresses
always @ (wa) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
wat[j]=wa[i*ADDRESS_WIDTH+j];
end
wai[i]=wat;
end
end
// Write memory
always @ (posedge clk) begin
for (j=0;j<WRITE_PORT_COUNT;j=j+1) begin
if (we[j]) begin
mem[wai[j]] <= di[j];
end
end
end
// Split read addresses
always @ (ra) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
rat[j]=ra[i*ADDRESS_WIDTH+j];
end
rai[i]=rat;
end
end
// guide read addresses using CE
always @ (posedge clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if ( ce[i] ) begin
rai_reg[i] <= rai[i];
end
end
end
// Memory read
always @ (rai_reg[0] or clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if (rai_reg[i] >= WORD_COUNT) begin
qt={DATA_WIDTH {1'b0}};
end else begin
qt=mem[rai_reg[i]];
end
for (j=0;j<DATA_WIDTH;j=j+1) begin
qi[i*DATA_WIDTH+j]=qt[j];
end
end
end
assign q=qi;
endmodule
`endcelldefine
module denoise_sp2_p1 (
address0,
ce0,
q0,
we0,
d0,
clk);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd225;
parameter AddressWidth = 32'd8;
input[AddressWidth-1:0] address0;
input ce0;
output[DataWidth-1:0] q0;
input we0;
input[DataWidth-1:0] d0;
input clk;
reg[DataWidth-1:0] q0;
wire[1 * DataWidth - 1:0] mem_q;
wire[DataWidth - 1:0] mem_q0;
wire[1 - 1:0] mem_we;
wire[1 * DataWidth - 1:0] mem_d;
wire[1 * AddressWidth - 1:0] mem_wa;
wire[1 * AddressWidth - 1:0] mem_ra;
wire[1 - 1:0] mem_ce;
denoise_sp2_p1_core #(
.READ_PORT_COUNT( 1 ),
.WRITE_PORT_COUNT( 1 ),
.DATA_WIDTH( DataWidth ),
.ADDRESS_WIDTH( AddressWidth ),
.WORD_COUNT( AddressRange ))
core_inst (
.q( mem_q ),
.ra( mem_ra ),
.ce( mem_ce ),
.d( mem_d ),
.wa( mem_wa ),
.we( mem_we ),
.clk( clk ));
assign mem_q0 = mem_q[1 * DataWidth - 1 : 0 * DataWidth];
always @ (mem_q0) begin
q0 = mem_q0;
end
assign mem_ra = {address0};
assign mem_ce = {ce0};
assign mem_we[0] = we0;
assign mem_d = {d0};
assign mem_wa = {address0};
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
`celldefine
module denoise_sp2_p2_core (q, ra, ce, clk, d, wa, we);
parameter READ_PORT_COUNT=32'd1;
parameter WRITE_PORT_COUNT=32'd1;
parameter DATA_WIDTH=32'd32;
parameter ADDRESS_WIDTH=32'd8;
parameter WORD_COUNT=32'd225;
output [READ_PORT_COUNT*DATA_WIDTH-1:0] q;
input [READ_PORT_COUNT*ADDRESS_WIDTH-1:0] ra;
input [READ_PORT_COUNT-1:0] ce;
input [WRITE_PORT_COUNT*DATA_WIDTH-1:0] d;
input [WRITE_PORT_COUNT*ADDRESS_WIDTH-1:0] wa;
input [WRITE_PORT_COUNT-1:0] we;
input clk;
integer i,j,k;
reg [DATA_WIDTH-1:0] mem [0:WORD_COUNT-1];
reg [ADDRESS_WIDTH-1:0] rat;
reg [ADDRESS_WIDTH-1:0] rai [READ_PORT_COUNT-1:0];
reg [ADDRESS_WIDTH-1:0] rai_reg [READ_PORT_COUNT-1:0];
reg [READ_PORT_COUNT*DATA_WIDTH-1:0] qi;
reg [DATA_WIDTH-1:0] qt;
reg [DATA_WIDTH-1:0] di [WRITE_PORT_COUNT-1:0];
reg [DATA_WIDTH-1:0] dt;
reg [ADDRESS_WIDTH-1:0] wat;
reg [ADDRESS_WIDTH-1:0] wai [WRITE_PORT_COUNT-1:0];
// Split input data
always @ (d) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<DATA_WIDTH;j=j+1) begin
dt[j]=d[i*DATA_WIDTH+j];
end
di[i]=dt;
end
end
// Split write addresses
always @ (wa) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
wat[j]=wa[i*ADDRESS_WIDTH+j];
end
wai[i]=wat;
end
end
// Write memory
always @ (posedge clk) begin
for (j=0;j<WRITE_PORT_COUNT;j=j+1) begin
if (we[j]) begin
mem[wai[j]] <= di[j];
end
end
end
// Split read addresses
always @ (ra) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
rat[j]=ra[i*ADDRESS_WIDTH+j];
end
rai[i]=rat;
end
end
// guide read addresses using CE
always @ (posedge clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if ( ce[i] ) begin
rai_reg[i] <= rai[i];
end
end
end
// Memory read
always @ (rai_reg[0] or clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if (rai_reg[i] >= WORD_COUNT) begin
qt={DATA_WIDTH {1'b0}};
end else begin
qt=mem[rai_reg[i]];
end
for (j=0;j<DATA_WIDTH;j=j+1) begin
qi[i*DATA_WIDTH+j]=qt[j];
end
end
end
assign q=qi;
endmodule
`endcelldefine
module denoise_sp2_p2 (
address0,
ce0,
q0,
we0,
d0,
clk);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd225;
parameter AddressWidth = 32'd8;
input[AddressWidth-1:0] address0;
input ce0;
output[DataWidth-1:0] q0;
input we0;
input[DataWidth-1:0] d0;
input clk;
reg[DataWidth-1:0] q0;
wire[1 * DataWidth - 1:0] mem_q;
wire[DataWidth - 1:0] mem_q0;
wire[1 - 1:0] mem_we;
wire[1 * DataWidth - 1:0] mem_d;
wire[1 * AddressWidth - 1:0] mem_wa;
wire[1 * AddressWidth - 1:0] mem_ra;
wire[1 - 1:0] mem_ce;
denoise_sp2_p2_core #(
.READ_PORT_COUNT( 1 ),
.WRITE_PORT_COUNT( 1 ),
.DATA_WIDTH( DataWidth ),
.ADDRESS_WIDTH( AddressWidth ),
.WORD_COUNT( AddressRange ))
core_inst (
.q( mem_q ),
.ra( mem_ra ),
.ce( mem_ce ),
.d( mem_d ),
.wa( mem_wa ),
.we( mem_we ),
.clk( clk ));
assign mem_q0 = mem_q[1 * DataWidth - 1 : 0 * DataWidth];
always @ (mem_q0) begin
q0 = mem_q0;
end
assign mem_ra = {address0};
assign mem_ce = {ce0};
assign mem_we[0] = we0;
assign mem_d = {d0};
assign mem_wa = {address0};
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
`celldefine
module denoise_sp2_p3_core (q, ra, ce, clk, d, wa, we);
parameter READ_PORT_COUNT=32'd1;
parameter WRITE_PORT_COUNT=32'd1;
parameter DATA_WIDTH=32'd32;
parameter ADDRESS_WIDTH=32'd8;
parameter WORD_COUNT=32'd225;
output [READ_PORT_COUNT*DATA_WIDTH-1:0] q;
input [READ_PORT_COUNT*ADDRESS_WIDTH-1:0] ra;
input [READ_PORT_COUNT-1:0] ce;
input [WRITE_PORT_COUNT*DATA_WIDTH-1:0] d;
input [WRITE_PORT_COUNT*ADDRESS_WIDTH-1:0] wa;
input [WRITE_PORT_COUNT-1:0] we;
input clk;
integer i,j,k;
reg [DATA_WIDTH-1:0] mem [0:WORD_COUNT-1];
reg [ADDRESS_WIDTH-1:0] rat;
reg [ADDRESS_WIDTH-1:0] rai [READ_PORT_COUNT-1:0];
reg [ADDRESS_WIDTH-1:0] rai_reg [READ_PORT_COUNT-1:0];
reg [READ_PORT_COUNT*DATA_WIDTH-1:0] qi;
reg [DATA_WIDTH-1:0] qt;
reg [DATA_WIDTH-1:0] di [WRITE_PORT_COUNT-1:0];
reg [DATA_WIDTH-1:0] dt;
reg [ADDRESS_WIDTH-1:0] wat;
reg [ADDRESS_WIDTH-1:0] wai [WRITE_PORT_COUNT-1:0];
// Split input data
always @ (d) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<DATA_WIDTH;j=j+1) begin
dt[j]=d[i*DATA_WIDTH+j];
end
di[i]=dt;
end
end
// Split write addresses
always @ (wa) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
wat[j]=wa[i*ADDRESS_WIDTH+j];
end
wai[i]=wat;
end
end
// Write memory
always @ (posedge clk) begin
for (j=0;j<WRITE_PORT_COUNT;j=j+1) begin
if (we[j]) begin
mem[wai[j]] <= di[j];
end
end
end
// Split read addresses
always @ (ra) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
rat[j]=ra[i*ADDRESS_WIDTH+j];
end
rai[i]=rat;
end
end
// guide read addresses using CE
always @ (posedge clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if ( ce[i] ) begin
rai_reg[i] <= rai[i];
end
end
end
// Memory read
always @ (rai_reg[0] or clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if (rai_reg[i] >= WORD_COUNT) begin
qt={DATA_WIDTH {1'b0}};
end else begin
qt=mem[rai_reg[i]];
end
for (j=0;j<DATA_WIDTH;j=j+1) begin
qi[i*DATA_WIDTH+j]=qt[j];
end
end
end
assign q=qi;
endmodule
`endcelldefine
module denoise_sp2_p3 (
address0,
ce0,
q0,
we0,
d0,
clk);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd225;
parameter AddressWidth = 32'd8;
input[AddressWidth-1:0] address0;
input ce0;
output[DataWidth-1:0] q0;
input we0;
input[DataWidth-1:0] d0;
input clk;
reg[DataWidth-1:0] q0;
wire[1 * DataWidth - 1:0] mem_q;
wire[DataWidth - 1:0] mem_q0;
wire[1 - 1:0] mem_we;
wire[1 * DataWidth - 1:0] mem_d;
wire[1 * AddressWidth - 1:0] mem_wa;
wire[1 * AddressWidth - 1:0] mem_ra;
wire[1 - 1:0] mem_ce;
denoise_sp2_p3_core #(
.READ_PORT_COUNT( 1 ),
.WRITE_PORT_COUNT( 1 ),
.DATA_WIDTH( DataWidth ),
.ADDRESS_WIDTH( AddressWidth ),
.WORD_COUNT( AddressRange ))
core_inst (
.q( mem_q ),
.ra( mem_ra ),
.ce( mem_ce ),
.d( mem_d ),
.wa( mem_wa ),
.we( mem_we ),
.clk( clk ));
assign mem_q0 = mem_q[1 * DataWidth - 1 : 0 * DataWidth];
always @ (mem_q0) begin
q0 = mem_q0;
end
assign mem_ra = {address0};
assign mem_ce = {ce0};
assign mem_we[0] = we0;
assign mem_d = {d0};
assign mem_wa = {address0};
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
`celldefine
module denoise_u0_p0_core (q, ra, ce, clk, d, wa, we);
parameter READ_PORT_COUNT=32'd1;
parameter WRITE_PORT_COUNT=32'd1;
parameter DATA_WIDTH=32'd32;
parameter ADDRESS_WIDTH=32'd8;
parameter WORD_COUNT=32'd225;
output [READ_PORT_COUNT*DATA_WIDTH-1:0] q;
input [READ_PORT_COUNT*ADDRESS_WIDTH-1:0] ra;
input [READ_PORT_COUNT-1:0] ce;
input [WRITE_PORT_COUNT*DATA_WIDTH-1:0] d;
input [WRITE_PORT_COUNT*ADDRESS_WIDTH-1:0] wa;
input [WRITE_PORT_COUNT-1:0] we;
input clk;
integer i,j,k;
reg [DATA_WIDTH-1:0] mem [0:WORD_COUNT-1];
reg [ADDRESS_WIDTH-1:0] rat;
reg [ADDRESS_WIDTH-1:0] rai [READ_PORT_COUNT-1:0];
reg [ADDRESS_WIDTH-1:0] rai_reg [READ_PORT_COUNT-1:0];
reg [READ_PORT_COUNT*DATA_WIDTH-1:0] qi;
reg [DATA_WIDTH-1:0] qt;
reg [DATA_WIDTH-1:0] di [WRITE_PORT_COUNT-1:0];
reg [DATA_WIDTH-1:0] dt;
reg [ADDRESS_WIDTH-1:0] wat;
reg [ADDRESS_WIDTH-1:0] wai [WRITE_PORT_COUNT-1:0];
// Split input data
always @ (d) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<DATA_WIDTH;j=j+1) begin
dt[j]=d[i*DATA_WIDTH+j];
end
di[i]=dt;
end
end
// Split write addresses
always @ (wa) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
wat[j]=wa[i*ADDRESS_WIDTH+j];
end
wai[i]=wat;
end
end
// Write memory
always @ (posedge clk) begin
for (j=0;j<WRITE_PORT_COUNT;j=j+1) begin
if (we[j]) begin
mem[wai[j]] <= di[j];
end
end
end
// Split read addresses
always @ (ra) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
rat[j]=ra[i*ADDRESS_WIDTH+j];
end
rai[i]=rat;
end
end
// guide read addresses using CE
always @ (posedge clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if ( ce[i] ) begin
rai_reg[i] <= rai[i];
end
end
end
// Memory read
always @ (rai_reg[0] or clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if (rai_reg[i] >= WORD_COUNT) begin
qt={DATA_WIDTH {1'b0}};
end else begin
qt=mem[rai_reg[i]];
end
for (j=0;j<DATA_WIDTH;j=j+1) begin
qi[i*DATA_WIDTH+j]=qt[j];
end
end
end
assign q=qi;
endmodule
`endcelldefine
module denoise_u0_p0 (
address0,
ce0,
q0,
we0,
d0,
clk);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd225;
parameter AddressWidth = 32'd8;
input[AddressWidth-1:0] address0;
input ce0;
output[DataWidth-1:0] q0;
input we0;
input[DataWidth-1:0] d0;
input clk;
reg[DataWidth-1:0] q0;
wire[1 * DataWidth - 1:0] mem_q;
wire[DataWidth - 1:0] mem_q0;
wire[1 - 1:0] mem_we;
wire[1 * DataWidth - 1:0] mem_d;
wire[1 * AddressWidth - 1:0] mem_wa;
wire[1 * AddressWidth - 1:0] mem_ra;
wire[1 - 1:0] mem_ce;
denoise_u0_p0_core #(
.READ_PORT_COUNT( 1 ),
.WRITE_PORT_COUNT( 1 ),
.DATA_WIDTH( DataWidth ),
.ADDRESS_WIDTH( AddressWidth ),
.WORD_COUNT( AddressRange ))
core_inst (
.q( mem_q ),
.ra( mem_ra ),
.ce( mem_ce ),
.d( mem_d ),
.wa( mem_wa ),
.we( mem_we ),
.clk( clk ));
assign mem_q0 = mem_q[1 * DataWidth - 1 : 0 * DataWidth];
always @ (mem_q0) begin
q0 = mem_q0;
end
assign mem_ra = {address0};
assign mem_ce = {ce0};
assign mem_we[0] = we0;
assign mem_d = {d0};
assign mem_wa = {address0};
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
`celldefine
module denoise_u0_p1_core (q, ra, ce, clk, d, wa, we);
parameter READ_PORT_COUNT=32'd1;
parameter WRITE_PORT_COUNT=32'd1;
parameter DATA_WIDTH=32'd32;
parameter ADDRESS_WIDTH=32'd8;
parameter WORD_COUNT=32'd225;
output [READ_PORT_COUNT*DATA_WIDTH-1:0] q;
input [READ_PORT_COUNT*ADDRESS_WIDTH-1:0] ra;
input [READ_PORT_COUNT-1:0] ce;
input [WRITE_PORT_COUNT*DATA_WIDTH-1:0] d;
input [WRITE_PORT_COUNT*ADDRESS_WIDTH-1:0] wa;
input [WRITE_PORT_COUNT-1:0] we;
input clk;
integer i,j,k;
reg [DATA_WIDTH-1:0] mem [0:WORD_COUNT-1];
reg [ADDRESS_WIDTH-1:0] rat;
reg [ADDRESS_WIDTH-1:0] rai [READ_PORT_COUNT-1:0];
reg [ADDRESS_WIDTH-1:0] rai_reg [READ_PORT_COUNT-1:0];
reg [READ_PORT_COUNT*DATA_WIDTH-1:0] qi;
reg [DATA_WIDTH-1:0] qt;
reg [DATA_WIDTH-1:0] di [WRITE_PORT_COUNT-1:0];
reg [DATA_WIDTH-1:0] dt;
reg [ADDRESS_WIDTH-1:0] wat;
reg [ADDRESS_WIDTH-1:0] wai [WRITE_PORT_COUNT-1:0];
// Split input data
always @ (d) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<DATA_WIDTH;j=j+1) begin
dt[j]=d[i*DATA_WIDTH+j];
end
di[i]=dt;
end
end
// Split write addresses
always @ (wa) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
wat[j]=wa[i*ADDRESS_WIDTH+j];
end
wai[i]=wat;
end
end
// Write memory
always @ (posedge clk) begin
for (j=0;j<WRITE_PORT_COUNT;j=j+1) begin
if (we[j]) begin
mem[wai[j]] <= di[j];
end
end
end
// Split read addresses
always @ (ra) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
rat[j]=ra[i*ADDRESS_WIDTH+j];
end
rai[i]=rat;
end
end
// guide read addresses using CE
always @ (posedge clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if ( ce[i] ) begin
rai_reg[i] <= rai[i];
end
end
end
// Memory read
always @ (rai_reg[0] or clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if (rai_reg[i] >= WORD_COUNT) begin
qt={DATA_WIDTH {1'b0}};
end else begin
qt=mem[rai_reg[i]];
end
for (j=0;j<DATA_WIDTH;j=j+1) begin
qi[i*DATA_WIDTH+j]=qt[j];
end
end
end
assign q=qi;
endmodule
`endcelldefine
module denoise_u0_p1 (
address0,
ce0,
q0,
we0,
d0,
clk);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd225;
parameter AddressWidth = 32'd8;
input[AddressWidth-1:0] address0;
input ce0;
output[DataWidth-1:0] q0;
input we0;
input[DataWidth-1:0] d0;
input clk;
reg[DataWidth-1:0] q0;
wire[1 * DataWidth - 1:0] mem_q;
wire[DataWidth - 1:0] mem_q0;
wire[1 - 1:0] mem_we;
wire[1 * DataWidth - 1:0] mem_d;
wire[1 * AddressWidth - 1:0] mem_wa;
wire[1 * AddressWidth - 1:0] mem_ra;
wire[1 - 1:0] mem_ce;
denoise_u0_p1_core #(
.READ_PORT_COUNT( 1 ),
.WRITE_PORT_COUNT( 1 ),
.DATA_WIDTH( DataWidth ),
.ADDRESS_WIDTH( AddressWidth ),
.WORD_COUNT( AddressRange ))
core_inst (
.q( mem_q ),
.ra( mem_ra ),
.ce( mem_ce ),
.d( mem_d ),
.wa( mem_wa ),
.we( mem_we ),
.clk( clk ));
assign mem_q0 = mem_q[1 * DataWidth - 1 : 0 * DataWidth];
always @ (mem_q0) begin
q0 = mem_q0;
end
assign mem_ra = {address0};
assign mem_ce = {ce0};
assign mem_we[0] = we0;
assign mem_d = {d0};
assign mem_wa = {address0};
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
`celldefine
module denoise_u0_p2_core (q, ra, ce, clk, d, wa, we);
parameter READ_PORT_COUNT=32'd1;
parameter WRITE_PORT_COUNT=32'd1;
parameter DATA_WIDTH=32'd32;
parameter ADDRESS_WIDTH=32'd8;
parameter WORD_COUNT=32'd225;
output [READ_PORT_COUNT*DATA_WIDTH-1:0] q;
input [READ_PORT_COUNT*ADDRESS_WIDTH-1:0] ra;
input [READ_PORT_COUNT-1:0] ce;
input [WRITE_PORT_COUNT*DATA_WIDTH-1:0] d;
input [WRITE_PORT_COUNT*ADDRESS_WIDTH-1:0] wa;
input [WRITE_PORT_COUNT-1:0] we;
input clk;
integer i,j,k;
reg [DATA_WIDTH-1:0] mem [0:WORD_COUNT-1];
reg [ADDRESS_WIDTH-1:0] rat;
reg [ADDRESS_WIDTH-1:0] rai [READ_PORT_COUNT-1:0];
reg [ADDRESS_WIDTH-1:0] rai_reg [READ_PORT_COUNT-1:0];
reg [READ_PORT_COUNT*DATA_WIDTH-1:0] qi;
reg [DATA_WIDTH-1:0] qt;
reg [DATA_WIDTH-1:0] di [WRITE_PORT_COUNT-1:0];
reg [DATA_WIDTH-1:0] dt;
reg [ADDRESS_WIDTH-1:0] wat;
reg [ADDRESS_WIDTH-1:0] wai [WRITE_PORT_COUNT-1:0];
// Split input data
always @ (d) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<DATA_WIDTH;j=j+1) begin
dt[j]=d[i*DATA_WIDTH+j];
end
di[i]=dt;
end
end
// Split write addresses
always @ (wa) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
wat[j]=wa[i*ADDRESS_WIDTH+j];
end
wai[i]=wat;
end
end
// Write memory
always @ (posedge clk) begin
for (j=0;j<WRITE_PORT_COUNT;j=j+1) begin
if (we[j]) begin
mem[wai[j]] <= di[j];
end
end
end
// Split read addresses
always @ (ra) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
rat[j]=ra[i*ADDRESS_WIDTH+j];
end
rai[i]=rat;
end
end
// guide read addresses using CE
always @ (posedge clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if ( ce[i] ) begin
rai_reg[i] <= rai[i];
end
end
end
// Memory read
always @ (rai_reg[0] or clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if (rai_reg[i] >= WORD_COUNT) begin
qt={DATA_WIDTH {1'b0}};
end else begin
qt=mem[rai_reg[i]];
end
for (j=0;j<DATA_WIDTH;j=j+1) begin
qi[i*DATA_WIDTH+j]=qt[j];
end
end
end
assign q=qi;
endmodule
`endcelldefine
module denoise_u0_p2 (
address0,
ce0,
q0,
we0,
d0,
clk);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd225;
parameter AddressWidth = 32'd8;
input[AddressWidth-1:0] address0;
input ce0;
output[DataWidth-1:0] q0;
input we0;
input[DataWidth-1:0] d0;
input clk;
reg[DataWidth-1:0] q0;
wire[1 * DataWidth - 1:0] mem_q;
wire[DataWidth - 1:0] mem_q0;
wire[1 - 1:0] mem_we;
wire[1 * DataWidth - 1:0] mem_d;
wire[1 * AddressWidth - 1:0] mem_wa;
wire[1 * AddressWidth - 1:0] mem_ra;
wire[1 - 1:0] mem_ce;
denoise_u0_p2_core #(
.READ_PORT_COUNT( 1 ),
.WRITE_PORT_COUNT( 1 ),
.DATA_WIDTH( DataWidth ),
.ADDRESS_WIDTH( AddressWidth ),
.WORD_COUNT( AddressRange ))
core_inst (
.q( mem_q ),
.ra( mem_ra ),
.ce( mem_ce ),
.d( mem_d ),
.wa( mem_wa ),
.we( mem_we ),
.clk( clk ));
assign mem_q0 = mem_q[1 * DataWidth - 1 : 0 * DataWidth];
always @ (mem_q0) begin
q0 = mem_q0;
end
assign mem_ra = {address0};
assign mem_ce = {ce0};
assign mem_we[0] = we0;
assign mem_d = {d0};
assign mem_wa = {address0};
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
`celldefine
module denoise_u0_p3_core (q, ra, ce, clk, d, wa, we);
parameter READ_PORT_COUNT=32'd2;
parameter WRITE_PORT_COUNT=32'd1;
parameter DATA_WIDTH=32'd32;
parameter ADDRESS_WIDTH=32'd8;
parameter WORD_COUNT=32'd225;
output [READ_PORT_COUNT*DATA_WIDTH-1:0] q;
input [READ_PORT_COUNT*ADDRESS_WIDTH-1:0] ra;
input [READ_PORT_COUNT-1:0] ce;
input [WRITE_PORT_COUNT*DATA_WIDTH-1:0] d;
input [WRITE_PORT_COUNT*ADDRESS_WIDTH-1:0] wa;
input [WRITE_PORT_COUNT-1:0] we;
input clk;
integer i,j,k;
reg [DATA_WIDTH-1:0] mem [0:WORD_COUNT-1];
reg [ADDRESS_WIDTH-1:0] rat;
reg [ADDRESS_WIDTH-1:0] rai [READ_PORT_COUNT-1:0];
reg [ADDRESS_WIDTH-1:0] rai_reg [READ_PORT_COUNT-1:0];
reg [READ_PORT_COUNT*DATA_WIDTH-1:0] qi;
reg [DATA_WIDTH-1:0] qt;
reg [DATA_WIDTH-1:0] di [WRITE_PORT_COUNT-1:0];
reg [DATA_WIDTH-1:0] dt;
reg [ADDRESS_WIDTH-1:0] wat;
reg [ADDRESS_WIDTH-1:0] wai [WRITE_PORT_COUNT-1:0];
// Split input data
always @ (d) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<DATA_WIDTH;j=j+1) begin
dt[j]=d[i*DATA_WIDTH+j];
end
di[i]=dt;
end
end
// Split write addresses
always @ (wa) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
wat[j]=wa[i*ADDRESS_WIDTH+j];
end
wai[i]=wat;
end
end
// Write memory
always @ (posedge clk) begin
for (j=0;j<WRITE_PORT_COUNT;j=j+1) begin
if (we[j]) begin
mem[wai[j]] <= di[j];
end
end
end
// Split read addresses
always @ (ra) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
rat[j]=ra[i*ADDRESS_WIDTH+j];
end
rai[i]=rat;
end
end
// guide read addresses using CE
always @ (posedge clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if ( ce[i] ) begin
rai_reg[i] <= rai[i];
end
end
end
// Memory read
always @ (rai_reg[0] or rai_reg[1] or clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if (rai_reg[i] >= WORD_COUNT) begin
qt={DATA_WIDTH {1'b0}};
end else begin
qt=mem[rai_reg[i]];
end
for (j=0;j<DATA_WIDTH;j=j+1) begin
qi[i*DATA_WIDTH+j]=qt[j];
end
end
end
assign q=qi;
endmodule
`endcelldefine
module denoise_u0_p3 (
address0,
ce0,
q0,
we0,
d0,
address1,
ce1,
q1,
clk);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd225;
parameter AddressWidth = 32'd8;
input[AddressWidth-1:0] address0;
input ce0;
output[DataWidth-1:0] q0;
input we0;
input[DataWidth-1:0] d0;
input[AddressWidth-1:0] address1;
input ce1;
output[DataWidth-1:0] q1;
input clk;
reg[DataWidth-1:0] q0;
reg[DataWidth-1:0] q1;
wire[2 * DataWidth - 1:0] mem_q;
wire[DataWidth - 1:0] mem_q0;
wire[DataWidth - 1:0] mem_q1;
wire[1 - 1:0] mem_we;
wire[1 * DataWidth - 1:0] mem_d;
wire[1 * AddressWidth - 1:0] mem_wa;
wire[2 * AddressWidth - 1:0] mem_ra;
wire[2 - 1:0] mem_ce;
denoise_u0_p3_core #(
.READ_PORT_COUNT( 2 ),
.WRITE_PORT_COUNT( 1 ),
.DATA_WIDTH( DataWidth ),
.ADDRESS_WIDTH( AddressWidth ),
.WORD_COUNT( AddressRange ))
core_inst (
.q( mem_q ),
.ra( mem_ra ),
.ce( mem_ce ),
.d( mem_d ),
.wa( mem_wa ),
.we( mem_we ),
.clk( clk ));
assign mem_q0 = mem_q[2 * DataWidth - 1 : 1 * DataWidth];
always @ (mem_q0) begin
q0 = mem_q0;
end
assign mem_q1 = mem_q[1 * DataWidth - 1 : 0 * DataWidth];
always @ (mem_q1) begin
q1 = mem_q1;
end
assign mem_ra = {address0, address1};
assign mem_ce = {ce0, ce1};
assign mem_we[0] = we0;
assign mem_d = {d0};
assign mem_wa = {address0};
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
`celldefine
module denoise_u1_p0_core (q, ra, ce, clk, d, wa, we);
parameter READ_PORT_COUNT=32'd1;
parameter WRITE_PORT_COUNT=32'd1;
parameter DATA_WIDTH=32'd32;
parameter ADDRESS_WIDTH=32'd8;
parameter WORD_COUNT=32'd225;
output [READ_PORT_COUNT*DATA_WIDTH-1:0] q;
input [READ_PORT_COUNT*ADDRESS_WIDTH-1:0] ra;
input [READ_PORT_COUNT-1:0] ce;
input [WRITE_PORT_COUNT*DATA_WIDTH-1:0] d;
input [WRITE_PORT_COUNT*ADDRESS_WIDTH-1:0] wa;
input [WRITE_PORT_COUNT-1:0] we;
input clk;
integer i,j,k;
reg [DATA_WIDTH-1:0] mem [0:WORD_COUNT-1];
reg [ADDRESS_WIDTH-1:0] rat;
reg [ADDRESS_WIDTH-1:0] rai [READ_PORT_COUNT-1:0];
reg [ADDRESS_WIDTH-1:0] rai_reg [READ_PORT_COUNT-1:0];
reg [READ_PORT_COUNT*DATA_WIDTH-1:0] qi;
reg [DATA_WIDTH-1:0] qt;
reg [DATA_WIDTH-1:0] di [WRITE_PORT_COUNT-1:0];
reg [DATA_WIDTH-1:0] dt;
reg [ADDRESS_WIDTH-1:0] wat;
reg [ADDRESS_WIDTH-1:0] wai [WRITE_PORT_COUNT-1:0];
// Split input data
always @ (d) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<DATA_WIDTH;j=j+1) begin
dt[j]=d[i*DATA_WIDTH+j];
end
di[i]=dt;
end
end
// Split write addresses
always @ (wa) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
wat[j]=wa[i*ADDRESS_WIDTH+j];
end
wai[i]=wat;
end
end
// Write memory
always @ (posedge clk) begin
for (j=0;j<WRITE_PORT_COUNT;j=j+1) begin
if (we[j]) begin
mem[wai[j]] <= di[j];
end
end
end
// Split read addresses
always @ (ra) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
rat[j]=ra[i*ADDRESS_WIDTH+j];
end
rai[i]=rat;
end
end
// guide read addresses using CE
always @ (posedge clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if ( ce[i] ) begin
rai_reg[i] <= rai[i];
end
end
end
// Memory read
always @ (rai_reg[0] or clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if (rai_reg[i] >= WORD_COUNT) begin
qt={DATA_WIDTH {1'b0}};
end else begin
qt=mem[rai_reg[i]];
end
for (j=0;j<DATA_WIDTH;j=j+1) begin
qi[i*DATA_WIDTH+j]=qt[j];
end
end
end
assign q=qi;
endmodule
`endcelldefine
module denoise_u1_p0 (
address0,
ce0,
q0,
we0,
d0,
clk);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd225;
parameter AddressWidth = 32'd8;
input[AddressWidth-1:0] address0;
input ce0;
output[DataWidth-1:0] q0;
input we0;
input[DataWidth-1:0] d0;
input clk;
reg[DataWidth-1:0] q0;
wire[1 * DataWidth - 1:0] mem_q;
wire[DataWidth - 1:0] mem_q0;
wire[1 - 1:0] mem_we;
wire[1 * DataWidth - 1:0] mem_d;
wire[1 * AddressWidth - 1:0] mem_wa;
wire[1 * AddressWidth - 1:0] mem_ra;
wire[1 - 1:0] mem_ce;
denoise_u1_p0_core #(
.READ_PORT_COUNT( 1 ),
.WRITE_PORT_COUNT( 1 ),
.DATA_WIDTH( DataWidth ),
.ADDRESS_WIDTH( AddressWidth ),
.WORD_COUNT( AddressRange ))
core_inst (
.q( mem_q ),
.ra( mem_ra ),
.ce( mem_ce ),
.d( mem_d ),
.wa( mem_wa ),
.we( mem_we ),
.clk( clk ));
assign mem_q0 = mem_q[1 * DataWidth - 1 : 0 * DataWidth];
always @ (mem_q0) begin
q0 = mem_q0;
end
assign mem_ra = {address0};
assign mem_ce = {ce0};
assign mem_we[0] = we0;
assign mem_d = {d0};
assign mem_wa = {address0};
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
`celldefine
module denoise_u1_p1_core (q, ra, ce, clk, d, wa, we);
parameter READ_PORT_COUNT=32'd1;
parameter WRITE_PORT_COUNT=32'd1;
parameter DATA_WIDTH=32'd32;
parameter ADDRESS_WIDTH=32'd8;
parameter WORD_COUNT=32'd225;
output [READ_PORT_COUNT*DATA_WIDTH-1:0] q;
input [READ_PORT_COUNT*ADDRESS_WIDTH-1:0] ra;
input [READ_PORT_COUNT-1:0] ce;
input [WRITE_PORT_COUNT*DATA_WIDTH-1:0] d;
input [WRITE_PORT_COUNT*ADDRESS_WIDTH-1:0] wa;
input [WRITE_PORT_COUNT-1:0] we;
input clk;
integer i,j,k;
reg [DATA_WIDTH-1:0] mem [0:WORD_COUNT-1];
reg [ADDRESS_WIDTH-1:0] rat;
reg [ADDRESS_WIDTH-1:0] rai [READ_PORT_COUNT-1:0];
reg [ADDRESS_WIDTH-1:0] rai_reg [READ_PORT_COUNT-1:0];
reg [READ_PORT_COUNT*DATA_WIDTH-1:0] qi;
reg [DATA_WIDTH-1:0] qt;
reg [DATA_WIDTH-1:0] di [WRITE_PORT_COUNT-1:0];
reg [DATA_WIDTH-1:0] dt;
reg [ADDRESS_WIDTH-1:0] wat;
reg [ADDRESS_WIDTH-1:0] wai [WRITE_PORT_COUNT-1:0];
// Split input data
always @ (d) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<DATA_WIDTH;j=j+1) begin
dt[j]=d[i*DATA_WIDTH+j];
end
di[i]=dt;
end
end
// Split write addresses
always @ (wa) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
wat[j]=wa[i*ADDRESS_WIDTH+j];
end
wai[i]=wat;
end
end
// Write memory
always @ (posedge clk) begin
for (j=0;j<WRITE_PORT_COUNT;j=j+1) begin
if (we[j]) begin
mem[wai[j]] <= di[j];
end
end
end
// Split read addresses
always @ (ra) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
rat[j]=ra[i*ADDRESS_WIDTH+j];
end
rai[i]=rat;
end
end
// guide read addresses using CE
always @ (posedge clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if ( ce[i] ) begin
rai_reg[i] <= rai[i];
end
end
end
// Memory read
always @ (rai_reg[0] or clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if (rai_reg[i] >= WORD_COUNT) begin
qt={DATA_WIDTH {1'b0}};
end else begin
qt=mem[rai_reg[i]];
end
for (j=0;j<DATA_WIDTH;j=j+1) begin
qi[i*DATA_WIDTH+j]=qt[j];
end
end
end
assign q=qi;
endmodule
`endcelldefine
module denoise_u1_p1 (
address0,
ce0,
q0,
we0,
d0,
clk);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd225;
parameter AddressWidth = 32'd8;
input[AddressWidth-1:0] address0;
input ce0;
output[DataWidth-1:0] q0;
input we0;
input[DataWidth-1:0] d0;
input clk;
reg[DataWidth-1:0] q0;
wire[1 * DataWidth - 1:0] mem_q;
wire[DataWidth - 1:0] mem_q0;
wire[1 - 1:0] mem_we;
wire[1 * DataWidth - 1:0] mem_d;
wire[1 * AddressWidth - 1:0] mem_wa;
wire[1 * AddressWidth - 1:0] mem_ra;
wire[1 - 1:0] mem_ce;
denoise_u1_p1_core #(
.READ_PORT_COUNT( 1 ),
.WRITE_PORT_COUNT( 1 ),
.DATA_WIDTH( DataWidth ),
.ADDRESS_WIDTH( AddressWidth ),
.WORD_COUNT( AddressRange ))
core_inst (
.q( mem_q ),
.ra( mem_ra ),
.ce( mem_ce ),
.d( mem_d ),
.wa( mem_wa ),
.we( mem_we ),
.clk( clk ));
assign mem_q0 = mem_q[1 * DataWidth - 1 : 0 * DataWidth];
always @ (mem_q0) begin
q0 = mem_q0;
end
assign mem_ra = {address0};
assign mem_ce = {ce0};
assign mem_we[0] = we0;
assign mem_d = {d0};
assign mem_wa = {address0};
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
`celldefine
module denoise_u1_p2_core (q, ra, ce, clk, d, wa, we);
parameter READ_PORT_COUNT=32'd1;
parameter WRITE_PORT_COUNT=32'd1;
parameter DATA_WIDTH=32'd32;
parameter ADDRESS_WIDTH=32'd8;
parameter WORD_COUNT=32'd225;
output [READ_PORT_COUNT*DATA_WIDTH-1:0] q;
input [READ_PORT_COUNT*ADDRESS_WIDTH-1:0] ra;
input [READ_PORT_COUNT-1:0] ce;
input [WRITE_PORT_COUNT*DATA_WIDTH-1:0] d;
input [WRITE_PORT_COUNT*ADDRESS_WIDTH-1:0] wa;
input [WRITE_PORT_COUNT-1:0] we;
input clk;
integer i,j,k;
reg [DATA_WIDTH-1:0] mem [0:WORD_COUNT-1];
reg [ADDRESS_WIDTH-1:0] rat;
reg [ADDRESS_WIDTH-1:0] rai [READ_PORT_COUNT-1:0];
reg [ADDRESS_WIDTH-1:0] rai_reg [READ_PORT_COUNT-1:0];
reg [READ_PORT_COUNT*DATA_WIDTH-1:0] qi;
reg [DATA_WIDTH-1:0] qt;
reg [DATA_WIDTH-1:0] di [WRITE_PORT_COUNT-1:0];
reg [DATA_WIDTH-1:0] dt;
reg [ADDRESS_WIDTH-1:0] wat;
reg [ADDRESS_WIDTH-1:0] wai [WRITE_PORT_COUNT-1:0];
// Split input data
always @ (d) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<DATA_WIDTH;j=j+1) begin
dt[j]=d[i*DATA_WIDTH+j];
end
di[i]=dt;
end
end
// Split write addresses
always @ (wa) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
wat[j]=wa[i*ADDRESS_WIDTH+j];
end
wai[i]=wat;
end
end
// Write memory
always @ (posedge clk) begin
for (j=0;j<WRITE_PORT_COUNT;j=j+1) begin
if (we[j]) begin
mem[wai[j]] <= di[j];
end
end
end
// Split read addresses
always @ (ra) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
rat[j]=ra[i*ADDRESS_WIDTH+j];
end
rai[i]=rat;
end
end
// guide read addresses using CE
always @ (posedge clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if ( ce[i] ) begin
rai_reg[i] <= rai[i];
end
end
end
// Memory read
always @ (rai_reg[0] or clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if (rai_reg[i] >= WORD_COUNT) begin
qt={DATA_WIDTH {1'b0}};
end else begin
qt=mem[rai_reg[i]];
end
for (j=0;j<DATA_WIDTH;j=j+1) begin
qi[i*DATA_WIDTH+j]=qt[j];
end
end
end
assign q=qi;
endmodule
`endcelldefine
module denoise_u1_p2 (
address0,
ce0,
q0,
we0,
d0,
clk);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd225;
parameter AddressWidth = 32'd8;
input[AddressWidth-1:0] address0;
input ce0;
output[DataWidth-1:0] q0;
input we0;
input[DataWidth-1:0] d0;
input clk;
reg[DataWidth-1:0] q0;
wire[1 * DataWidth - 1:0] mem_q;
wire[DataWidth - 1:0] mem_q0;
wire[1 - 1:0] mem_we;
wire[1 * DataWidth - 1:0] mem_d;
wire[1 * AddressWidth - 1:0] mem_wa;
wire[1 * AddressWidth - 1:0] mem_ra;
wire[1 - 1:0] mem_ce;
denoise_u1_p2_core #(
.READ_PORT_COUNT( 1 ),
.WRITE_PORT_COUNT( 1 ),
.DATA_WIDTH( DataWidth ),
.ADDRESS_WIDTH( AddressWidth ),
.WORD_COUNT( AddressRange ))
core_inst (
.q( mem_q ),
.ra( mem_ra ),
.ce( mem_ce ),
.d( mem_d ),
.wa( mem_wa ),
.we( mem_we ),
.clk( clk ));
assign mem_q0 = mem_q[1 * DataWidth - 1 : 0 * DataWidth];
always @ (mem_q0) begin
q0 = mem_q0;
end
assign mem_ra = {address0};
assign mem_ce = {ce0};
assign mem_we[0] = we0;
assign mem_d = {d0};
assign mem_wa = {address0};
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
`celldefine
module denoise_u1_p3_core (q, ra, ce, clk, d, wa, we);
parameter READ_PORT_COUNT=32'd2;
parameter WRITE_PORT_COUNT=32'd1;
parameter DATA_WIDTH=32'd32;
parameter ADDRESS_WIDTH=32'd8;
parameter WORD_COUNT=32'd225;
output [READ_PORT_COUNT*DATA_WIDTH-1:0] q;
input [READ_PORT_COUNT*ADDRESS_WIDTH-1:0] ra;
input [READ_PORT_COUNT-1:0] ce;
input [WRITE_PORT_COUNT*DATA_WIDTH-1:0] d;
input [WRITE_PORT_COUNT*ADDRESS_WIDTH-1:0] wa;
input [WRITE_PORT_COUNT-1:0] we;
input clk;
integer i,j,k;
reg [DATA_WIDTH-1:0] mem [0:WORD_COUNT-1];
reg [ADDRESS_WIDTH-1:0] rat;
reg [ADDRESS_WIDTH-1:0] rai [READ_PORT_COUNT-1:0];
reg [ADDRESS_WIDTH-1:0] rai_reg [READ_PORT_COUNT-1:0];
reg [READ_PORT_COUNT*DATA_WIDTH-1:0] qi;
reg [DATA_WIDTH-1:0] qt;
reg [DATA_WIDTH-1:0] di [WRITE_PORT_COUNT-1:0];
reg [DATA_WIDTH-1:0] dt;
reg [ADDRESS_WIDTH-1:0] wat;
reg [ADDRESS_WIDTH-1:0] wai [WRITE_PORT_COUNT-1:0];
// Split input data
always @ (d) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<DATA_WIDTH;j=j+1) begin
dt[j]=d[i*DATA_WIDTH+j];
end
di[i]=dt;
end
end
// Split write addresses
always @ (wa) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
wat[j]=wa[i*ADDRESS_WIDTH+j];
end
wai[i]=wat;
end
end
// Write memory
always @ (posedge clk) begin
for (j=0;j<WRITE_PORT_COUNT;j=j+1) begin
if (we[j]) begin
mem[wai[j]] <= di[j];
end
end
end
// Split read addresses
always @ (ra) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
rat[j]=ra[i*ADDRESS_WIDTH+j];
end
rai[i]=rat;
end
end
// guide read addresses using CE
always @ (posedge clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if ( ce[i] ) begin
rai_reg[i] <= rai[i];
end
end
end
// Memory read
always @ (rai_reg[0] or rai_reg[1] or clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if (rai_reg[i] >= WORD_COUNT) begin
qt={DATA_WIDTH {1'b0}};
end else begin
qt=mem[rai_reg[i]];
end
for (j=0;j<DATA_WIDTH;j=j+1) begin
qi[i*DATA_WIDTH+j]=qt[j];
end
end
end
assign q=qi;
endmodule
`endcelldefine
module denoise_u1_p3 (
address0,
ce0,
q0,
we0,
d0,
address1,
ce1,
q1,
clk);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd225;
parameter AddressWidth = 32'd8;
input[AddressWidth-1:0] address0;
input ce0;
output[DataWidth-1:0] q0;
input we0;
input[DataWidth-1:0] d0;
input[AddressWidth-1:0] address1;
input ce1;
output[DataWidth-1:0] q1;
input clk;
reg[DataWidth-1:0] q0;
reg[DataWidth-1:0] q1;
wire[2 * DataWidth - 1:0] mem_q;
wire[DataWidth - 1:0] mem_q0;
wire[DataWidth - 1:0] mem_q1;
wire[1 - 1:0] mem_we;
wire[1 * DataWidth - 1:0] mem_d;
wire[1 * AddressWidth - 1:0] mem_wa;
wire[2 * AddressWidth - 1:0] mem_ra;
wire[2 - 1:0] mem_ce;
denoise_u1_p3_core #(
.READ_PORT_COUNT( 2 ),
.WRITE_PORT_COUNT( 1 ),
.DATA_WIDTH( DataWidth ),
.ADDRESS_WIDTH( AddressWidth ),
.WORD_COUNT( AddressRange ))
core_inst (
.q( mem_q ),
.ra( mem_ra ),
.ce( mem_ce ),
.d( mem_d ),
.wa( mem_wa ),
.we( mem_we ),
.clk( clk ));
assign mem_q0 = mem_q[2 * DataWidth - 1 : 1 * DataWidth];
always @ (mem_q0) begin
q0 = mem_q0;
end
assign mem_q1 = mem_q[1 * DataWidth - 1 : 0 * DataWidth];
always @ (mem_q1) begin
q1 = mem_q1;
end
assign mem_ra = {address0, address1};
assign mem_ce = {ce0, ce1};
assign mem_we[0] = we0;
assign mem_d = {d0};
assign mem_wa = {address0};
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
`celldefine
module denoise_u2_p0_core (q, ra, ce, clk, d, wa, we);
parameter READ_PORT_COUNT=32'd1;
parameter WRITE_PORT_COUNT=32'd1;
parameter DATA_WIDTH=32'd32;
parameter ADDRESS_WIDTH=32'd8;
parameter WORD_COUNT=32'd225;
output [READ_PORT_COUNT*DATA_WIDTH-1:0] q;
input [READ_PORT_COUNT*ADDRESS_WIDTH-1:0] ra;
input [READ_PORT_COUNT-1:0] ce;
input [WRITE_PORT_COUNT*DATA_WIDTH-1:0] d;
input [WRITE_PORT_COUNT*ADDRESS_WIDTH-1:0] wa;
input [WRITE_PORT_COUNT-1:0] we;
input clk;
integer i,j,k;
reg [DATA_WIDTH-1:0] mem [0:WORD_COUNT-1];
reg [ADDRESS_WIDTH-1:0] rat;
reg [ADDRESS_WIDTH-1:0] rai [READ_PORT_COUNT-1:0];
reg [ADDRESS_WIDTH-1:0] rai_reg [READ_PORT_COUNT-1:0];
reg [READ_PORT_COUNT*DATA_WIDTH-1:0] qi;
reg [DATA_WIDTH-1:0] qt;
reg [DATA_WIDTH-1:0] di [WRITE_PORT_COUNT-1:0];
reg [DATA_WIDTH-1:0] dt;
reg [ADDRESS_WIDTH-1:0] wat;
reg [ADDRESS_WIDTH-1:0] wai [WRITE_PORT_COUNT-1:0];
// Split input data
always @ (d) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<DATA_WIDTH;j=j+1) begin
dt[j]=d[i*DATA_WIDTH+j];
end
di[i]=dt;
end
end
// Split write addresses
always @ (wa) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
wat[j]=wa[i*ADDRESS_WIDTH+j];
end
wai[i]=wat;
end
end
// Write memory
always @ (posedge clk) begin
for (j=0;j<WRITE_PORT_COUNT;j=j+1) begin
if (we[j]) begin
mem[wai[j]] <= di[j];
end
end
end
// Split read addresses
always @ (ra) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
rat[j]=ra[i*ADDRESS_WIDTH+j];
end
rai[i]=rat;
end
end
// guide read addresses using CE
always @ (posedge clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if ( ce[i] ) begin
rai_reg[i] <= rai[i];
end
end
end
// Memory read
always @ (rai_reg[0] or clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if (rai_reg[i] >= WORD_COUNT) begin
qt={DATA_WIDTH {1'b0}};
end else begin
qt=mem[rai_reg[i]];
end
for (j=0;j<DATA_WIDTH;j=j+1) begin
qi[i*DATA_WIDTH+j]=qt[j];
end
end
end
assign q=qi;
endmodule
`endcelldefine
module denoise_u2_p0 (
address0,
ce0,
q0,
we0,
d0,
clk);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd225;
parameter AddressWidth = 32'd8;
input[AddressWidth-1:0] address0;
input ce0;
output[DataWidth-1:0] q0;
input we0;
input[DataWidth-1:0] d0;
input clk;
reg[DataWidth-1:0] q0;
wire[1 * DataWidth - 1:0] mem_q;
wire[DataWidth - 1:0] mem_q0;
wire[1 - 1:0] mem_we;
wire[1 * DataWidth - 1:0] mem_d;
wire[1 * AddressWidth - 1:0] mem_wa;
wire[1 * AddressWidth - 1:0] mem_ra;
wire[1 - 1:0] mem_ce;
denoise_u2_p0_core #(
.READ_PORT_COUNT( 1 ),
.WRITE_PORT_COUNT( 1 ),
.DATA_WIDTH( DataWidth ),
.ADDRESS_WIDTH( AddressWidth ),
.WORD_COUNT( AddressRange ))
core_inst (
.q( mem_q ),
.ra( mem_ra ),
.ce( mem_ce ),
.d( mem_d ),
.wa( mem_wa ),
.we( mem_we ),
.clk( clk ));
assign mem_q0 = mem_q[1 * DataWidth - 1 : 0 * DataWidth];
always @ (mem_q0) begin
q0 = mem_q0;
end
assign mem_ra = {address0};
assign mem_ce = {ce0};
assign mem_we[0] = we0;
assign mem_d = {d0};
assign mem_wa = {address0};
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
`celldefine
module denoise_u2_p1_core (q, ra, ce, clk, d, wa, we);
parameter READ_PORT_COUNT=32'd1;
parameter WRITE_PORT_COUNT=32'd1;
parameter DATA_WIDTH=32'd32;
parameter ADDRESS_WIDTH=32'd8;
parameter WORD_COUNT=32'd225;
output [READ_PORT_COUNT*DATA_WIDTH-1:0] q;
input [READ_PORT_COUNT*ADDRESS_WIDTH-1:0] ra;
input [READ_PORT_COUNT-1:0] ce;
input [WRITE_PORT_COUNT*DATA_WIDTH-1:0] d;
input [WRITE_PORT_COUNT*ADDRESS_WIDTH-1:0] wa;
input [WRITE_PORT_COUNT-1:0] we;
input clk;
integer i,j,k;
reg [DATA_WIDTH-1:0] mem [0:WORD_COUNT-1];
reg [ADDRESS_WIDTH-1:0] rat;
reg [ADDRESS_WIDTH-1:0] rai [READ_PORT_COUNT-1:0];
reg [ADDRESS_WIDTH-1:0] rai_reg [READ_PORT_COUNT-1:0];
reg [READ_PORT_COUNT*DATA_WIDTH-1:0] qi;
reg [DATA_WIDTH-1:0] qt;
reg [DATA_WIDTH-1:0] di [WRITE_PORT_COUNT-1:0];
reg [DATA_WIDTH-1:0] dt;
reg [ADDRESS_WIDTH-1:0] wat;
reg [ADDRESS_WIDTH-1:0] wai [WRITE_PORT_COUNT-1:0];
// Split input data
always @ (d) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<DATA_WIDTH;j=j+1) begin
dt[j]=d[i*DATA_WIDTH+j];
end
di[i]=dt;
end
end
// Split write addresses
always @ (wa) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
wat[j]=wa[i*ADDRESS_WIDTH+j];
end
wai[i]=wat;
end
end
// Write memory
always @ (posedge clk) begin
for (j=0;j<WRITE_PORT_COUNT;j=j+1) begin
if (we[j]) begin
mem[wai[j]] <= di[j];
end
end
end
// Split read addresses
always @ (ra) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
rat[j]=ra[i*ADDRESS_WIDTH+j];
end
rai[i]=rat;
end
end
// guide read addresses using CE
always @ (posedge clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if ( ce[i] ) begin
rai_reg[i] <= rai[i];
end
end
end
// Memory read
always @ (rai_reg[0] or clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if (rai_reg[i] >= WORD_COUNT) begin
qt={DATA_WIDTH {1'b0}};
end else begin
qt=mem[rai_reg[i]];
end
for (j=0;j<DATA_WIDTH;j=j+1) begin
qi[i*DATA_WIDTH+j]=qt[j];
end
end
end
assign q=qi;
endmodule
`endcelldefine
module denoise_u2_p1 (
address0,
ce0,
q0,
we0,
d0,
clk);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd225;
parameter AddressWidth = 32'd8;
input[AddressWidth-1:0] address0;
input ce0;
output[DataWidth-1:0] q0;
input we0;
input[DataWidth-1:0] d0;
input clk;
reg[DataWidth-1:0] q0;
wire[1 * DataWidth - 1:0] mem_q;
wire[DataWidth - 1:0] mem_q0;
wire[1 - 1:0] mem_we;
wire[1 * DataWidth - 1:0] mem_d;
wire[1 * AddressWidth - 1:0] mem_wa;
wire[1 * AddressWidth - 1:0] mem_ra;
wire[1 - 1:0] mem_ce;
denoise_u2_p1_core #(
.READ_PORT_COUNT( 1 ),
.WRITE_PORT_COUNT( 1 ),
.DATA_WIDTH( DataWidth ),
.ADDRESS_WIDTH( AddressWidth ),
.WORD_COUNT( AddressRange ))
core_inst (
.q( mem_q ),
.ra( mem_ra ),
.ce( mem_ce ),
.d( mem_d ),
.wa( mem_wa ),
.we( mem_we ),
.clk( clk ));
assign mem_q0 = mem_q[1 * DataWidth - 1 : 0 * DataWidth];
always @ (mem_q0) begin
q0 = mem_q0;
end
assign mem_ra = {address0};
assign mem_ce = {ce0};
assign mem_we[0] = we0;
assign mem_d = {d0};
assign mem_wa = {address0};
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
`celldefine
module denoise_u2_p2_core (q, ra, ce, clk, d, wa, we);
parameter READ_PORT_COUNT=32'd1;
parameter WRITE_PORT_COUNT=32'd1;
parameter DATA_WIDTH=32'd32;
parameter ADDRESS_WIDTH=32'd8;
parameter WORD_COUNT=32'd225;
output [READ_PORT_COUNT*DATA_WIDTH-1:0] q;
input [READ_PORT_COUNT*ADDRESS_WIDTH-1:0] ra;
input [READ_PORT_COUNT-1:0] ce;
input [WRITE_PORT_COUNT*DATA_WIDTH-1:0] d;
input [WRITE_PORT_COUNT*ADDRESS_WIDTH-1:0] wa;
input [WRITE_PORT_COUNT-1:0] we;
input clk;
integer i,j,k;
reg [DATA_WIDTH-1:0] mem [0:WORD_COUNT-1];
reg [ADDRESS_WIDTH-1:0] rat;
reg [ADDRESS_WIDTH-1:0] rai [READ_PORT_COUNT-1:0];
reg [ADDRESS_WIDTH-1:0] rai_reg [READ_PORT_COUNT-1:0];
reg [READ_PORT_COUNT*DATA_WIDTH-1:0] qi;
reg [DATA_WIDTH-1:0] qt;
reg [DATA_WIDTH-1:0] di [WRITE_PORT_COUNT-1:0];
reg [DATA_WIDTH-1:0] dt;
reg [ADDRESS_WIDTH-1:0] wat;
reg [ADDRESS_WIDTH-1:0] wai [WRITE_PORT_COUNT-1:0];
// Split input data
always @ (d) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<DATA_WIDTH;j=j+1) begin
dt[j]=d[i*DATA_WIDTH+j];
end
di[i]=dt;
end
end
// Split write addresses
always @ (wa) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
wat[j]=wa[i*ADDRESS_WIDTH+j];
end
wai[i]=wat;
end
end
// Write memory
always @ (posedge clk) begin
for (j=0;j<WRITE_PORT_COUNT;j=j+1) begin
if (we[j]) begin
mem[wai[j]] <= di[j];
end
end
end
// Split read addresses
always @ (ra) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
rat[j]=ra[i*ADDRESS_WIDTH+j];
end
rai[i]=rat;
end
end
// guide read addresses using CE
always @ (posedge clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if ( ce[i] ) begin
rai_reg[i] <= rai[i];
end
end
end
// Memory read
always @ (rai_reg[0] or clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if (rai_reg[i] >= WORD_COUNT) begin
qt={DATA_WIDTH {1'b0}};
end else begin
qt=mem[rai_reg[i]];
end
for (j=0;j<DATA_WIDTH;j=j+1) begin
qi[i*DATA_WIDTH+j]=qt[j];
end
end
end
assign q=qi;
endmodule
`endcelldefine
module denoise_u2_p2 (
address0,
ce0,
q0,
we0,
d0,
clk);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd225;
parameter AddressWidth = 32'd8;
input[AddressWidth-1:0] address0;
input ce0;
output[DataWidth-1:0] q0;
input we0;
input[DataWidth-1:0] d0;
input clk;
reg[DataWidth-1:0] q0;
wire[1 * DataWidth - 1:0] mem_q;
wire[DataWidth - 1:0] mem_q0;
wire[1 - 1:0] mem_we;
wire[1 * DataWidth - 1:0] mem_d;
wire[1 * AddressWidth - 1:0] mem_wa;
wire[1 * AddressWidth - 1:0] mem_ra;
wire[1 - 1:0] mem_ce;
denoise_u2_p2_core #(
.READ_PORT_COUNT( 1 ),
.WRITE_PORT_COUNT( 1 ),
.DATA_WIDTH( DataWidth ),
.ADDRESS_WIDTH( AddressWidth ),
.WORD_COUNT( AddressRange ))
core_inst (
.q( mem_q ),
.ra( mem_ra ),
.ce( mem_ce ),
.d( mem_d ),
.wa( mem_wa ),
.we( mem_we ),
.clk( clk ));
assign mem_q0 = mem_q[1 * DataWidth - 1 : 0 * DataWidth];
always @ (mem_q0) begin
q0 = mem_q0;
end
assign mem_ra = {address0};
assign mem_ce = {ce0};
assign mem_we[0] = we0;
assign mem_d = {d0};
assign mem_wa = {address0};
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
`celldefine
module denoise_u2_p3_core (q, ra, ce, clk, d, wa, we);
parameter READ_PORT_COUNT=32'd2;
parameter WRITE_PORT_COUNT=32'd1;
parameter DATA_WIDTH=32'd32;
parameter ADDRESS_WIDTH=32'd8;
parameter WORD_COUNT=32'd225;
output [READ_PORT_COUNT*DATA_WIDTH-1:0] q;
input [READ_PORT_COUNT*ADDRESS_WIDTH-1:0] ra;
input [READ_PORT_COUNT-1:0] ce;
input [WRITE_PORT_COUNT*DATA_WIDTH-1:0] d;
input [WRITE_PORT_COUNT*ADDRESS_WIDTH-1:0] wa;
input [WRITE_PORT_COUNT-1:0] we;
input clk;
integer i,j,k;
reg [DATA_WIDTH-1:0] mem [0:WORD_COUNT-1];
reg [ADDRESS_WIDTH-1:0] rat;
reg [ADDRESS_WIDTH-1:0] rai [READ_PORT_COUNT-1:0];
reg [ADDRESS_WIDTH-1:0] rai_reg [READ_PORT_COUNT-1:0];
reg [READ_PORT_COUNT*DATA_WIDTH-1:0] qi;
reg [DATA_WIDTH-1:0] qt;
reg [DATA_WIDTH-1:0] di [WRITE_PORT_COUNT-1:0];
reg [DATA_WIDTH-1:0] dt;
reg [ADDRESS_WIDTH-1:0] wat;
reg [ADDRESS_WIDTH-1:0] wai [WRITE_PORT_COUNT-1:0];
// Split input data
always @ (d) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<DATA_WIDTH;j=j+1) begin
dt[j]=d[i*DATA_WIDTH+j];
end
di[i]=dt;
end
end
// Split write addresses
always @ (wa) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
wat[j]=wa[i*ADDRESS_WIDTH+j];
end
wai[i]=wat;
end
end
// Write memory
always @ (posedge clk) begin
for (j=0;j<WRITE_PORT_COUNT;j=j+1) begin
if (we[j]) begin
mem[wai[j]] <= di[j];
end
end
end
// Split read addresses
always @ (ra) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
rat[j]=ra[i*ADDRESS_WIDTH+j];
end
rai[i]=rat;
end
end
// guide read addresses using CE
always @ (posedge clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if ( ce[i] ) begin
rai_reg[i] <= rai[i];
end
end
end
// Memory read
always @ (rai_reg[0] or rai_reg[1] or clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if (rai_reg[i] >= WORD_COUNT) begin
qt={DATA_WIDTH {1'b0}};
end else begin
qt=mem[rai_reg[i]];
end
for (j=0;j<DATA_WIDTH;j=j+1) begin
qi[i*DATA_WIDTH+j]=qt[j];
end
end
end
assign q=qi;
endmodule
`endcelldefine
module denoise_u2_p3 (
address0,
ce0,
q0,
we0,
d0,
address1,
ce1,
q1,
clk);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd225;
parameter AddressWidth = 32'd8;
input[AddressWidth-1:0] address0;
input ce0;
output[DataWidth-1:0] q0;
input we0;
input[DataWidth-1:0] d0;
input[AddressWidth-1:0] address1;
input ce1;
output[DataWidth-1:0] q1;
input clk;
reg[DataWidth-1:0] q0;
reg[DataWidth-1:0] q1;
wire[2 * DataWidth - 1:0] mem_q;
wire[DataWidth - 1:0] mem_q0;
wire[DataWidth - 1:0] mem_q1;
wire[1 - 1:0] mem_we;
wire[1 * DataWidth - 1:0] mem_d;
wire[1 * AddressWidth - 1:0] mem_wa;
wire[2 * AddressWidth - 1:0] mem_ra;
wire[2 - 1:0] mem_ce;
denoise_u2_p3_core #(
.READ_PORT_COUNT( 2 ),
.WRITE_PORT_COUNT( 1 ),
.DATA_WIDTH( DataWidth ),
.ADDRESS_WIDTH( AddressWidth ),
.WORD_COUNT( AddressRange ))
core_inst (
.q( mem_q ),
.ra( mem_ra ),
.ce( mem_ce ),
.d( mem_d ),
.wa( mem_wa ),
.we( mem_we ),
.clk( clk ));
assign mem_q0 = mem_q[2 * DataWidth - 1 : 1 * DataWidth];
always @ (mem_q0) begin
q0 = mem_q0;
end
assign mem_q1 = mem_q[1 * DataWidth - 1 : 0 * DataWidth];
always @ (mem_q1) begin
q1 = mem_q1;
end
assign mem_ra = {address0, address1};
assign mem_ce = {ce0, ce1};
assign mem_we[0] = we0;
assign mem_d = {d0};
assign mem_wa = {address0};
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
`celldefine
module denoise_u3_p0_core (q, ra, ce, clk, d, wa, we);
parameter READ_PORT_COUNT=32'd1;
parameter WRITE_PORT_COUNT=32'd1;
parameter DATA_WIDTH=32'd32;
parameter ADDRESS_WIDTH=32'd8;
parameter WORD_COUNT=32'd225;
output [READ_PORT_COUNT*DATA_WIDTH-1:0] q;
input [READ_PORT_COUNT*ADDRESS_WIDTH-1:0] ra;
input [READ_PORT_COUNT-1:0] ce;
input [WRITE_PORT_COUNT*DATA_WIDTH-1:0] d;
input [WRITE_PORT_COUNT*ADDRESS_WIDTH-1:0] wa;
input [WRITE_PORT_COUNT-1:0] we;
input clk;
integer i,j,k;
reg [DATA_WIDTH-1:0] mem [0:WORD_COUNT-1];
reg [ADDRESS_WIDTH-1:0] rat;
reg [ADDRESS_WIDTH-1:0] rai [READ_PORT_COUNT-1:0];
reg [ADDRESS_WIDTH-1:0] rai_reg [READ_PORT_COUNT-1:0];
reg [READ_PORT_COUNT*DATA_WIDTH-1:0] qi;
reg [DATA_WIDTH-1:0] qt;
reg [DATA_WIDTH-1:0] di [WRITE_PORT_COUNT-1:0];
reg [DATA_WIDTH-1:0] dt;
reg [ADDRESS_WIDTH-1:0] wat;
reg [ADDRESS_WIDTH-1:0] wai [WRITE_PORT_COUNT-1:0];
// Split input data
always @ (d) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<DATA_WIDTH;j=j+1) begin
dt[j]=d[i*DATA_WIDTH+j];
end
di[i]=dt;
end
end
// Split write addresses
always @ (wa) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
wat[j]=wa[i*ADDRESS_WIDTH+j];
end
wai[i]=wat;
end
end
// Write memory
always @ (posedge clk) begin
for (j=0;j<WRITE_PORT_COUNT;j=j+1) begin
if (we[j]) begin
mem[wai[j]] <= di[j];
end
end
end
// Split read addresses
always @ (ra) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
rat[j]=ra[i*ADDRESS_WIDTH+j];
end
rai[i]=rat;
end
end
// guide read addresses using CE
always @ (posedge clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if ( ce[i] ) begin
rai_reg[i] <= rai[i];
end
end
end
// Memory read
always @ (rai_reg[0] or clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if (rai_reg[i] >= WORD_COUNT) begin
qt={DATA_WIDTH {1'b0}};
end else begin
qt=mem[rai_reg[i]];
end
for (j=0;j<DATA_WIDTH;j=j+1) begin
qi[i*DATA_WIDTH+j]=qt[j];
end
end
end
assign q=qi;
endmodule
`endcelldefine
module denoise_u3_p0 (
address0,
ce0,
q0,
we0,
d0,
clk);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd225;
parameter AddressWidth = 32'd8;
input[AddressWidth-1:0] address0;
input ce0;
output[DataWidth-1:0] q0;
input we0;
input[DataWidth-1:0] d0;
input clk;
reg[DataWidth-1:0] q0;
wire[1 * DataWidth - 1:0] mem_q;
wire[DataWidth - 1:0] mem_q0;
wire[1 - 1:0] mem_we;
wire[1 * DataWidth - 1:0] mem_d;
wire[1 * AddressWidth - 1:0] mem_wa;
wire[1 * AddressWidth - 1:0] mem_ra;
wire[1 - 1:0] mem_ce;
denoise_u3_p0_core #(
.READ_PORT_COUNT( 1 ),
.WRITE_PORT_COUNT( 1 ),
.DATA_WIDTH( DataWidth ),
.ADDRESS_WIDTH( AddressWidth ),
.WORD_COUNT( AddressRange ))
core_inst (
.q( mem_q ),
.ra( mem_ra ),
.ce( mem_ce ),
.d( mem_d ),
.wa( mem_wa ),
.we( mem_we ),
.clk( clk ));
assign mem_q0 = mem_q[1 * DataWidth - 1 : 0 * DataWidth];
always @ (mem_q0) begin
q0 = mem_q0;
end
assign mem_ra = {address0};
assign mem_ce = {ce0};
assign mem_we[0] = we0;
assign mem_d = {d0};
assign mem_wa = {address0};
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
`celldefine
module denoise_u3_p1_core (q, ra, ce, clk, d, wa, we);
parameter READ_PORT_COUNT=32'd1;
parameter WRITE_PORT_COUNT=32'd1;
parameter DATA_WIDTH=32'd32;
parameter ADDRESS_WIDTH=32'd8;
parameter WORD_COUNT=32'd225;
output [READ_PORT_COUNT*DATA_WIDTH-1:0] q;
input [READ_PORT_COUNT*ADDRESS_WIDTH-1:0] ra;
input [READ_PORT_COUNT-1:0] ce;
input [WRITE_PORT_COUNT*DATA_WIDTH-1:0] d;
input [WRITE_PORT_COUNT*ADDRESS_WIDTH-1:0] wa;
input [WRITE_PORT_COUNT-1:0] we;
input clk;
integer i,j,k;
reg [DATA_WIDTH-1:0] mem [0:WORD_COUNT-1];
reg [ADDRESS_WIDTH-1:0] rat;
reg [ADDRESS_WIDTH-1:0] rai [READ_PORT_COUNT-1:0];
reg [ADDRESS_WIDTH-1:0] rai_reg [READ_PORT_COUNT-1:0];
reg [READ_PORT_COUNT*DATA_WIDTH-1:0] qi;
reg [DATA_WIDTH-1:0] qt;
reg [DATA_WIDTH-1:0] di [WRITE_PORT_COUNT-1:0];
reg [DATA_WIDTH-1:0] dt;
reg [ADDRESS_WIDTH-1:0] wat;
reg [ADDRESS_WIDTH-1:0] wai [WRITE_PORT_COUNT-1:0];
// Split input data
always @ (d) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<DATA_WIDTH;j=j+1) begin
dt[j]=d[i*DATA_WIDTH+j];
end
di[i]=dt;
end
end
// Split write addresses
always @ (wa) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
wat[j]=wa[i*ADDRESS_WIDTH+j];
end
wai[i]=wat;
end
end
// Write memory
always @ (posedge clk) begin
for (j=0;j<WRITE_PORT_COUNT;j=j+1) begin
if (we[j]) begin
mem[wai[j]] <= di[j];
end
end
end
// Split read addresses
always @ (ra) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
rat[j]=ra[i*ADDRESS_WIDTH+j];
end
rai[i]=rat;
end
end
// guide read addresses using CE
always @ (posedge clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if ( ce[i] ) begin
rai_reg[i] <= rai[i];
end
end
end
// Memory read
always @ (rai_reg[0] or clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if (rai_reg[i] >= WORD_COUNT) begin
qt={DATA_WIDTH {1'b0}};
end else begin
qt=mem[rai_reg[i]];
end
for (j=0;j<DATA_WIDTH;j=j+1) begin
qi[i*DATA_WIDTH+j]=qt[j];
end
end
end
assign q=qi;
endmodule
`endcelldefine
module denoise_u3_p1 (
address0,
ce0,
q0,
we0,
d0,
clk);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd225;
parameter AddressWidth = 32'd8;
input[AddressWidth-1:0] address0;
input ce0;
output[DataWidth-1:0] q0;
input we0;
input[DataWidth-1:0] d0;
input clk;
reg[DataWidth-1:0] q0;
wire[1 * DataWidth - 1:0] mem_q;
wire[DataWidth - 1:0] mem_q0;
wire[1 - 1:0] mem_we;
wire[1 * DataWidth - 1:0] mem_d;
wire[1 * AddressWidth - 1:0] mem_wa;
wire[1 * AddressWidth - 1:0] mem_ra;
wire[1 - 1:0] mem_ce;
denoise_u3_p1_core #(
.READ_PORT_COUNT( 1 ),
.WRITE_PORT_COUNT( 1 ),
.DATA_WIDTH( DataWidth ),
.ADDRESS_WIDTH( AddressWidth ),
.WORD_COUNT( AddressRange ))
core_inst (
.q( mem_q ),
.ra( mem_ra ),
.ce( mem_ce ),
.d( mem_d ),
.wa( mem_wa ),
.we( mem_we ),
.clk( clk ));
assign mem_q0 = mem_q[1 * DataWidth - 1 : 0 * DataWidth];
always @ (mem_q0) begin
q0 = mem_q0;
end
assign mem_ra = {address0};
assign mem_ce = {ce0};
assign mem_we[0] = we0;
assign mem_d = {d0};
assign mem_wa = {address0};
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
`celldefine
module denoise_u3_p2_core (q, ra, ce, clk, d, wa, we);
parameter READ_PORT_COUNT=32'd1;
parameter WRITE_PORT_COUNT=32'd1;
parameter DATA_WIDTH=32'd32;
parameter ADDRESS_WIDTH=32'd8;
parameter WORD_COUNT=32'd225;
output [READ_PORT_COUNT*DATA_WIDTH-1:0] q;
input [READ_PORT_COUNT*ADDRESS_WIDTH-1:0] ra;
input [READ_PORT_COUNT-1:0] ce;
input [WRITE_PORT_COUNT*DATA_WIDTH-1:0] d;
input [WRITE_PORT_COUNT*ADDRESS_WIDTH-1:0] wa;
input [WRITE_PORT_COUNT-1:0] we;
input clk;
integer i,j,k;
reg [DATA_WIDTH-1:0] mem [0:WORD_COUNT-1];
reg [ADDRESS_WIDTH-1:0] rat;
reg [ADDRESS_WIDTH-1:0] rai [READ_PORT_COUNT-1:0];
reg [ADDRESS_WIDTH-1:0] rai_reg [READ_PORT_COUNT-1:0];
reg [READ_PORT_COUNT*DATA_WIDTH-1:0] qi;
reg [DATA_WIDTH-1:0] qt;
reg [DATA_WIDTH-1:0] di [WRITE_PORT_COUNT-1:0];
reg [DATA_WIDTH-1:0] dt;
reg [ADDRESS_WIDTH-1:0] wat;
reg [ADDRESS_WIDTH-1:0] wai [WRITE_PORT_COUNT-1:0];
// Split input data
always @ (d) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<DATA_WIDTH;j=j+1) begin
dt[j]=d[i*DATA_WIDTH+j];
end
di[i]=dt;
end
end
// Split write addresses
always @ (wa) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
wat[j]=wa[i*ADDRESS_WIDTH+j];
end
wai[i]=wat;
end
end
// Write memory
always @ (posedge clk) begin
for (j=0;j<WRITE_PORT_COUNT;j=j+1) begin
if (we[j]) begin
mem[wai[j]] <= di[j];
end
end
end
// Split read addresses
always @ (ra) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
rat[j]=ra[i*ADDRESS_WIDTH+j];
end
rai[i]=rat;
end
end
// guide read addresses using CE
always @ (posedge clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if ( ce[i] ) begin
rai_reg[i] <= rai[i];
end
end
end
// Memory read
always @ (rai_reg[0] or clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if (rai_reg[i] >= WORD_COUNT) begin
qt={DATA_WIDTH {1'b0}};
end else begin
qt=mem[rai_reg[i]];
end
for (j=0;j<DATA_WIDTH;j=j+1) begin
qi[i*DATA_WIDTH+j]=qt[j];
end
end
end
assign q=qi;
endmodule
`endcelldefine
module denoise_u3_p2 (
address0,
ce0,
q0,
we0,
d0,
clk);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd225;
parameter AddressWidth = 32'd8;
input[AddressWidth-1:0] address0;
input ce0;
output[DataWidth-1:0] q0;
input we0;
input[DataWidth-1:0] d0;
input clk;
reg[DataWidth-1:0] q0;
wire[1 * DataWidth - 1:0] mem_q;
wire[DataWidth - 1:0] mem_q0;
wire[1 - 1:0] mem_we;
wire[1 * DataWidth - 1:0] mem_d;
wire[1 * AddressWidth - 1:0] mem_wa;
wire[1 * AddressWidth - 1:0] mem_ra;
wire[1 - 1:0] mem_ce;
denoise_u3_p2_core #(
.READ_PORT_COUNT( 1 ),
.WRITE_PORT_COUNT( 1 ),
.DATA_WIDTH( DataWidth ),
.ADDRESS_WIDTH( AddressWidth ),
.WORD_COUNT( AddressRange ))
core_inst (
.q( mem_q ),
.ra( mem_ra ),
.ce( mem_ce ),
.d( mem_d ),
.wa( mem_wa ),
.we( mem_we ),
.clk( clk ));
assign mem_q0 = mem_q[1 * DataWidth - 1 : 0 * DataWidth];
always @ (mem_q0) begin
q0 = mem_q0;
end
assign mem_ra = {address0};
assign mem_ce = {ce0};
assign mem_we[0] = we0;
assign mem_d = {d0};
assign mem_wa = {address0};
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
`celldefine
module denoise_u3_p3_core (q, ra, ce, clk, d, wa, we);
parameter READ_PORT_COUNT=32'd2;
parameter WRITE_PORT_COUNT=32'd1;
parameter DATA_WIDTH=32'd32;
parameter ADDRESS_WIDTH=32'd8;
parameter WORD_COUNT=32'd225;
output [READ_PORT_COUNT*DATA_WIDTH-1:0] q;
input [READ_PORT_COUNT*ADDRESS_WIDTH-1:0] ra;
input [READ_PORT_COUNT-1:0] ce;
input [WRITE_PORT_COUNT*DATA_WIDTH-1:0] d;
input [WRITE_PORT_COUNT*ADDRESS_WIDTH-1:0] wa;
input [WRITE_PORT_COUNT-1:0] we;
input clk;
integer i,j,k;
reg [DATA_WIDTH-1:0] mem [0:WORD_COUNT-1];
reg [ADDRESS_WIDTH-1:0] rat;
reg [ADDRESS_WIDTH-1:0] rai [READ_PORT_COUNT-1:0];
reg [ADDRESS_WIDTH-1:0] rai_reg [READ_PORT_COUNT-1:0];
reg [READ_PORT_COUNT*DATA_WIDTH-1:0] qi;
reg [DATA_WIDTH-1:0] qt;
reg [DATA_WIDTH-1:0] di [WRITE_PORT_COUNT-1:0];
reg [DATA_WIDTH-1:0] dt;
reg [ADDRESS_WIDTH-1:0] wat;
reg [ADDRESS_WIDTH-1:0] wai [WRITE_PORT_COUNT-1:0];
// Split input data
always @ (d) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<DATA_WIDTH;j=j+1) begin
dt[j]=d[i*DATA_WIDTH+j];
end
di[i]=dt;
end
end
// Split write addresses
always @ (wa) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
wat[j]=wa[i*ADDRESS_WIDTH+j];
end
wai[i]=wat;
end
end
// Write memory
always @ (posedge clk) begin
for (j=0;j<WRITE_PORT_COUNT;j=j+1) begin
if (we[j]) begin
mem[wai[j]] <= di[j];
end
end
end
// Split read addresses
always @ (ra) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
rat[j]=ra[i*ADDRESS_WIDTH+j];
end
rai[i]=rat;
end
end
// guide read addresses using CE
always @ (posedge clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if ( ce[i] ) begin
rai_reg[i] <= rai[i];
end
end
end
// Memory read
always @ (rai_reg[0] or rai_reg[1] or clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if (rai_reg[i] >= WORD_COUNT) begin
qt={DATA_WIDTH {1'b0}};
end else begin
qt=mem[rai_reg[i]];
end
for (j=0;j<DATA_WIDTH;j=j+1) begin
qi[i*DATA_WIDTH+j]=qt[j];
end
end
end
assign q=qi;
endmodule
`endcelldefine
module denoise_u3_p3 (
address0,
ce0,
q0,
we0,
d0,
address1,
ce1,
q1,
clk);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd225;
parameter AddressWidth = 32'd8;
input[AddressWidth-1:0] address0;
input ce0;
output[DataWidth-1:0] q0;
input we0;
input[DataWidth-1:0] d0;
input[AddressWidth-1:0] address1;
input ce1;
output[DataWidth-1:0] q1;
input clk;
reg[DataWidth-1:0] q0;
reg[DataWidth-1:0] q1;
wire[2 * DataWidth - 1:0] mem_q;
wire[DataWidth - 1:0] mem_q0;
wire[DataWidth - 1:0] mem_q1;
wire[1 - 1:0] mem_we;
wire[1 * DataWidth - 1:0] mem_d;
wire[1 * AddressWidth - 1:0] mem_wa;
wire[2 * AddressWidth - 1:0] mem_ra;
wire[2 - 1:0] mem_ce;
denoise_u3_p3_core #(
.READ_PORT_COUNT( 2 ),
.WRITE_PORT_COUNT( 1 ),
.DATA_WIDTH( DataWidth ),
.ADDRESS_WIDTH( AddressWidth ),
.WORD_COUNT( AddressRange ))
core_inst (
.q( mem_q ),
.ra( mem_ra ),
.ce( mem_ce ),
.d( mem_d ),
.wa( mem_wa ),
.we( mem_we ),
.clk( clk ));
assign mem_q0 = mem_q[2 * DataWidth - 1 : 1 * DataWidth];
always @ (mem_q0) begin
q0 = mem_q0;
end
assign mem_q1 = mem_q[1 * DataWidth - 1 : 0 * DataWidth];
always @ (mem_q1) begin
q1 = mem_q1;
end
assign mem_ra = {address0, address1};
assign mem_ce = {ce0, ce1};
assign mem_we[0] = we0;
assign mem_d = {d0};
assign mem_wa = {address0};
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
`celldefine
module denoise_u4_p0_core (q, ra, ce, clk, d, wa, we);
parameter READ_PORT_COUNT=32'd1;
parameter WRITE_PORT_COUNT=32'd1;
parameter DATA_WIDTH=32'd32;
parameter ADDRESS_WIDTH=32'd8;
parameter WORD_COUNT=32'd225;
output [READ_PORT_COUNT*DATA_WIDTH-1:0] q;
input [READ_PORT_COUNT*ADDRESS_WIDTH-1:0] ra;
input [READ_PORT_COUNT-1:0] ce;
input [WRITE_PORT_COUNT*DATA_WIDTH-1:0] d;
input [WRITE_PORT_COUNT*ADDRESS_WIDTH-1:0] wa;
input [WRITE_PORT_COUNT-1:0] we;
input clk;
integer i,j,k;
reg [DATA_WIDTH-1:0] mem [0:WORD_COUNT-1];
reg [ADDRESS_WIDTH-1:0] rat;
reg [ADDRESS_WIDTH-1:0] rai [READ_PORT_COUNT-1:0];
reg [ADDRESS_WIDTH-1:0] rai_reg [READ_PORT_COUNT-1:0];
reg [READ_PORT_COUNT*DATA_WIDTH-1:0] qi;
reg [DATA_WIDTH-1:0] qt;
reg [DATA_WIDTH-1:0] di [WRITE_PORT_COUNT-1:0];
reg [DATA_WIDTH-1:0] dt;
reg [ADDRESS_WIDTH-1:0] wat;
reg [ADDRESS_WIDTH-1:0] wai [WRITE_PORT_COUNT-1:0];
// Split input data
always @ (d) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<DATA_WIDTH;j=j+1) begin
dt[j]=d[i*DATA_WIDTH+j];
end
di[i]=dt;
end
end
// Split write addresses
always @ (wa) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
wat[j]=wa[i*ADDRESS_WIDTH+j];
end
wai[i]=wat;
end
end
// Write memory
always @ (posedge clk) begin
for (j=0;j<WRITE_PORT_COUNT;j=j+1) begin
if (we[j]) begin
mem[wai[j]] <= di[j];
end
end
end
// Split read addresses
always @ (ra) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
rat[j]=ra[i*ADDRESS_WIDTH+j];
end
rai[i]=rat;
end
end
// guide read addresses using CE
always @ (posedge clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if ( ce[i] ) begin
rai_reg[i] <= rai[i];
end
end
end
// Memory read
always @ (rai_reg[0] or clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if (rai_reg[i] >= WORD_COUNT) begin
qt={DATA_WIDTH {1'b0}};
end else begin
qt=mem[rai_reg[i]];
end
for (j=0;j<DATA_WIDTH;j=j+1) begin
qi[i*DATA_WIDTH+j]=qt[j];
end
end
end
assign q=qi;
endmodule
`endcelldefine
module denoise_u4_p0 (
address0,
ce0,
q0,
we0,
d0,
clk);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd225;
parameter AddressWidth = 32'd8;
input[AddressWidth-1:0] address0;
input ce0;
output[DataWidth-1:0] q0;
input we0;
input[DataWidth-1:0] d0;
input clk;
reg[DataWidth-1:0] q0;
wire[1 * DataWidth - 1:0] mem_q;
wire[DataWidth - 1:0] mem_q0;
wire[1 - 1:0] mem_we;
wire[1 * DataWidth - 1:0] mem_d;
wire[1 * AddressWidth - 1:0] mem_wa;
wire[1 * AddressWidth - 1:0] mem_ra;
wire[1 - 1:0] mem_ce;
denoise_u4_p0_core #(
.READ_PORT_COUNT( 1 ),
.WRITE_PORT_COUNT( 1 ),
.DATA_WIDTH( DataWidth ),
.ADDRESS_WIDTH( AddressWidth ),
.WORD_COUNT( AddressRange ))
core_inst (
.q( mem_q ),
.ra( mem_ra ),
.ce( mem_ce ),
.d( mem_d ),
.wa( mem_wa ),
.we( mem_we ),
.clk( clk ));
assign mem_q0 = mem_q[1 * DataWidth - 1 : 0 * DataWidth];
always @ (mem_q0) begin
q0 = mem_q0;
end
assign mem_ra = {address0};
assign mem_ce = {ce0};
assign mem_we[0] = we0;
assign mem_d = {d0};
assign mem_wa = {address0};
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
`celldefine
module denoise_u4_p1_core (q, ra, ce, clk, d, wa, we);
parameter READ_PORT_COUNT=32'd1;
parameter WRITE_PORT_COUNT=32'd1;
parameter DATA_WIDTH=32'd32;
parameter ADDRESS_WIDTH=32'd8;
parameter WORD_COUNT=32'd225;
output [READ_PORT_COUNT*DATA_WIDTH-1:0] q;
input [READ_PORT_COUNT*ADDRESS_WIDTH-1:0] ra;
input [READ_PORT_COUNT-1:0] ce;
input [WRITE_PORT_COUNT*DATA_WIDTH-1:0] d;
input [WRITE_PORT_COUNT*ADDRESS_WIDTH-1:0] wa;
input [WRITE_PORT_COUNT-1:0] we;
input clk;
integer i,j,k;
reg [DATA_WIDTH-1:0] mem [0:WORD_COUNT-1];
reg [ADDRESS_WIDTH-1:0] rat;
reg [ADDRESS_WIDTH-1:0] rai [READ_PORT_COUNT-1:0];
reg [ADDRESS_WIDTH-1:0] rai_reg [READ_PORT_COUNT-1:0];
reg [READ_PORT_COUNT*DATA_WIDTH-1:0] qi;
reg [DATA_WIDTH-1:0] qt;
reg [DATA_WIDTH-1:0] di [WRITE_PORT_COUNT-1:0];
reg [DATA_WIDTH-1:0] dt;
reg [ADDRESS_WIDTH-1:0] wat;
reg [ADDRESS_WIDTH-1:0] wai [WRITE_PORT_COUNT-1:0];
// Split input data
always @ (d) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<DATA_WIDTH;j=j+1) begin
dt[j]=d[i*DATA_WIDTH+j];
end
di[i]=dt;
end
end
// Split write addresses
always @ (wa) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
wat[j]=wa[i*ADDRESS_WIDTH+j];
end
wai[i]=wat;
end
end
// Write memory
always @ (posedge clk) begin
for (j=0;j<WRITE_PORT_COUNT;j=j+1) begin
if (we[j]) begin
mem[wai[j]] <= di[j];
end
end
end
// Split read addresses
always @ (ra) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
rat[j]=ra[i*ADDRESS_WIDTH+j];
end
rai[i]=rat;
end
end
// guide read addresses using CE
always @ (posedge clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if ( ce[i] ) begin
rai_reg[i] <= rai[i];
end
end
end
// Memory read
always @ (rai_reg[0] or clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if (rai_reg[i] >= WORD_COUNT) begin
qt={DATA_WIDTH {1'b0}};
end else begin
qt=mem[rai_reg[i]];
end
for (j=0;j<DATA_WIDTH;j=j+1) begin
qi[i*DATA_WIDTH+j]=qt[j];
end
end
end
assign q=qi;
endmodule
`endcelldefine
module denoise_u4_p1 (
address0,
ce0,
q0,
we0,
d0,
clk);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd225;
parameter AddressWidth = 32'd8;
input[AddressWidth-1:0] address0;
input ce0;
output[DataWidth-1:0] q0;
input we0;
input[DataWidth-1:0] d0;
input clk;
reg[DataWidth-1:0] q0;
wire[1 * DataWidth - 1:0] mem_q;
wire[DataWidth - 1:0] mem_q0;
wire[1 - 1:0] mem_we;
wire[1 * DataWidth - 1:0] mem_d;
wire[1 * AddressWidth - 1:0] mem_wa;
wire[1 * AddressWidth - 1:0] mem_ra;
wire[1 - 1:0] mem_ce;
denoise_u4_p1_core #(
.READ_PORT_COUNT( 1 ),
.WRITE_PORT_COUNT( 1 ),
.DATA_WIDTH( DataWidth ),
.ADDRESS_WIDTH( AddressWidth ),
.WORD_COUNT( AddressRange ))
core_inst (
.q( mem_q ),
.ra( mem_ra ),
.ce( mem_ce ),
.d( mem_d ),
.wa( mem_wa ),
.we( mem_we ),
.clk( clk ));
assign mem_q0 = mem_q[1 * DataWidth - 1 : 0 * DataWidth];
always @ (mem_q0) begin
q0 = mem_q0;
end
assign mem_ra = {address0};
assign mem_ce = {ce0};
assign mem_we[0] = we0;
assign mem_d = {d0};
assign mem_wa = {address0};
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
`celldefine
module denoise_u4_p2_core (q, ra, ce, clk, d, wa, we);
parameter READ_PORT_COUNT=32'd1;
parameter WRITE_PORT_COUNT=32'd1;
parameter DATA_WIDTH=32'd32;
parameter ADDRESS_WIDTH=32'd8;
parameter WORD_COUNT=32'd225;
output [READ_PORT_COUNT*DATA_WIDTH-1:0] q;
input [READ_PORT_COUNT*ADDRESS_WIDTH-1:0] ra;
input [READ_PORT_COUNT-1:0] ce;
input [WRITE_PORT_COUNT*DATA_WIDTH-1:0] d;
input [WRITE_PORT_COUNT*ADDRESS_WIDTH-1:0] wa;
input [WRITE_PORT_COUNT-1:0] we;
input clk;
integer i,j,k;
reg [DATA_WIDTH-1:0] mem [0:WORD_COUNT-1];
reg [ADDRESS_WIDTH-1:0] rat;
reg [ADDRESS_WIDTH-1:0] rai [READ_PORT_COUNT-1:0];
reg [ADDRESS_WIDTH-1:0] rai_reg [READ_PORT_COUNT-1:0];
reg [READ_PORT_COUNT*DATA_WIDTH-1:0] qi;
reg [DATA_WIDTH-1:0] qt;
reg [DATA_WIDTH-1:0] di [WRITE_PORT_COUNT-1:0];
reg [DATA_WIDTH-1:0] dt;
reg [ADDRESS_WIDTH-1:0] wat;
reg [ADDRESS_WIDTH-1:0] wai [WRITE_PORT_COUNT-1:0];
// Split input data
always @ (d) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<DATA_WIDTH;j=j+1) begin
dt[j]=d[i*DATA_WIDTH+j];
end
di[i]=dt;
end
end
// Split write addresses
always @ (wa) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
wat[j]=wa[i*ADDRESS_WIDTH+j];
end
wai[i]=wat;
end
end
// Write memory
always @ (posedge clk) begin
for (j=0;j<WRITE_PORT_COUNT;j=j+1) begin
if (we[j]) begin
mem[wai[j]] <= di[j];
end
end
end
// Split read addresses
always @ (ra) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
rat[j]=ra[i*ADDRESS_WIDTH+j];
end
rai[i]=rat;
end
end
// guide read addresses using CE
always @ (posedge clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if ( ce[i] ) begin
rai_reg[i] <= rai[i];
end
end
end
// Memory read
always @ (rai_reg[0] or clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if (rai_reg[i] >= WORD_COUNT) begin
qt={DATA_WIDTH {1'b0}};
end else begin
qt=mem[rai_reg[i]];
end
for (j=0;j<DATA_WIDTH;j=j+1) begin
qi[i*DATA_WIDTH+j]=qt[j];
end
end
end
assign q=qi;
endmodule
`endcelldefine
module denoise_u4_p2 (
address0,
ce0,
q0,
we0,
d0,
clk);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd225;
parameter AddressWidth = 32'd8;
input[AddressWidth-1:0] address0;
input ce0;
output[DataWidth-1:0] q0;
input we0;
input[DataWidth-1:0] d0;
input clk;
reg[DataWidth-1:0] q0;
wire[1 * DataWidth - 1:0] mem_q;
wire[DataWidth - 1:0] mem_q0;
wire[1 - 1:0] mem_we;
wire[1 * DataWidth - 1:0] mem_d;
wire[1 * AddressWidth - 1:0] mem_wa;
wire[1 * AddressWidth - 1:0] mem_ra;
wire[1 - 1:0] mem_ce;
denoise_u4_p2_core #(
.READ_PORT_COUNT( 1 ),
.WRITE_PORT_COUNT( 1 ),
.DATA_WIDTH( DataWidth ),
.ADDRESS_WIDTH( AddressWidth ),
.WORD_COUNT( AddressRange ))
core_inst (
.q( mem_q ),
.ra( mem_ra ),
.ce( mem_ce ),
.d( mem_d ),
.wa( mem_wa ),
.we( mem_we ),
.clk( clk ));
assign mem_q0 = mem_q[1 * DataWidth - 1 : 0 * DataWidth];
always @ (mem_q0) begin
q0 = mem_q0;
end
assign mem_ra = {address0};
assign mem_ce = {ce0};
assign mem_we[0] = we0;
assign mem_d = {d0};
assign mem_wa = {address0};
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
`celldefine
module denoise_u4_p3_core (q, ra, ce, clk, d, wa, we);
parameter READ_PORT_COUNT=32'd2;
parameter WRITE_PORT_COUNT=32'd1;
parameter DATA_WIDTH=32'd32;
parameter ADDRESS_WIDTH=32'd8;
parameter WORD_COUNT=32'd225;
output [READ_PORT_COUNT*DATA_WIDTH-1:0] q;
input [READ_PORT_COUNT*ADDRESS_WIDTH-1:0] ra;
input [READ_PORT_COUNT-1:0] ce;
input [WRITE_PORT_COUNT*DATA_WIDTH-1:0] d;
input [WRITE_PORT_COUNT*ADDRESS_WIDTH-1:0] wa;
input [WRITE_PORT_COUNT-1:0] we;
input clk;
integer i,j,k;
reg [DATA_WIDTH-1:0] mem [0:WORD_COUNT-1];
reg [ADDRESS_WIDTH-1:0] rat;
reg [ADDRESS_WIDTH-1:0] rai [READ_PORT_COUNT-1:0];
reg [ADDRESS_WIDTH-1:0] rai_reg [READ_PORT_COUNT-1:0];
reg [READ_PORT_COUNT*DATA_WIDTH-1:0] qi;
reg [DATA_WIDTH-1:0] qt;
reg [DATA_WIDTH-1:0] di [WRITE_PORT_COUNT-1:0];
reg [DATA_WIDTH-1:0] dt;
reg [ADDRESS_WIDTH-1:0] wat;
reg [ADDRESS_WIDTH-1:0] wai [WRITE_PORT_COUNT-1:0];
// Split input data
always @ (d) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<DATA_WIDTH;j=j+1) begin
dt[j]=d[i*DATA_WIDTH+j];
end
di[i]=dt;
end
end
// Split write addresses
always @ (wa) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
wat[j]=wa[i*ADDRESS_WIDTH+j];
end
wai[i]=wat;
end
end
// Write memory
always @ (posedge clk) begin
for (j=0;j<WRITE_PORT_COUNT;j=j+1) begin
if (we[j]) begin
mem[wai[j]] <= di[j];
end
end
end
// Split read addresses
always @ (ra) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
rat[j]=ra[i*ADDRESS_WIDTH+j];
end
rai[i]=rat;
end
end
// guide read addresses using CE
always @ (posedge clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if ( ce[i] ) begin
rai_reg[i] <= rai[i];
end
end
end
// Memory read
always @ (rai_reg[0] or rai_reg[1] or clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if (rai_reg[i] >= WORD_COUNT) begin
qt={DATA_WIDTH {1'b0}};
end else begin
qt=mem[rai_reg[i]];
end
for (j=0;j<DATA_WIDTH;j=j+1) begin
qi[i*DATA_WIDTH+j]=qt[j];
end
end
end
assign q=qi;
endmodule
`endcelldefine
module denoise_u4_p3 (
address0,
ce0,
q0,
we0,
d0,
address1,
ce1,
q1,
clk);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd225;
parameter AddressWidth = 32'd8;
input[AddressWidth-1:0] address0;
input ce0;
output[DataWidth-1:0] q0;
input we0;
input[DataWidth-1:0] d0;
input[AddressWidth-1:0] address1;
input ce1;
output[DataWidth-1:0] q1;
input clk;
reg[DataWidth-1:0] q0;
reg[DataWidth-1:0] q1;
wire[2 * DataWidth - 1:0] mem_q;
wire[DataWidth - 1:0] mem_q0;
wire[DataWidth - 1:0] mem_q1;
wire[1 - 1:0] mem_we;
wire[1 * DataWidth - 1:0] mem_d;
wire[1 * AddressWidth - 1:0] mem_wa;
wire[2 * AddressWidth - 1:0] mem_ra;
wire[2 - 1:0] mem_ce;
denoise_u4_p3_core #(
.READ_PORT_COUNT( 2 ),
.WRITE_PORT_COUNT( 1 ),
.DATA_WIDTH( DataWidth ),
.ADDRESS_WIDTH( AddressWidth ),
.WORD_COUNT( AddressRange ))
core_inst (
.q( mem_q ),
.ra( mem_ra ),
.ce( mem_ce ),
.d( mem_d ),
.wa( mem_wa ),
.we( mem_we ),
.clk( clk ));
assign mem_q0 = mem_q[2 * DataWidth - 1 : 1 * DataWidth];
always @ (mem_q0) begin
q0 = mem_q0;
end
assign mem_q1 = mem_q[1 * DataWidth - 1 : 0 * DataWidth];
always @ (mem_q1) begin
q1 = mem_q1;
end
assign mem_ra = {address0, address1};
assign mem_ce = {ce0, ce1};
assign mem_we[0] = we0;
assign mem_d = {d0};
assign mem_wa = {address0};
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
`celldefine
module denoise_u5_p0_core (q, ra, ce, clk, d, wa, we);
parameter READ_PORT_COUNT=32'd1;
parameter WRITE_PORT_COUNT=32'd1;
parameter DATA_WIDTH=32'd32;
parameter ADDRESS_WIDTH=32'd8;
parameter WORD_COUNT=32'd225;
output [READ_PORT_COUNT*DATA_WIDTH-1:0] q;
input [READ_PORT_COUNT*ADDRESS_WIDTH-1:0] ra;
input [READ_PORT_COUNT-1:0] ce;
input [WRITE_PORT_COUNT*DATA_WIDTH-1:0] d;
input [WRITE_PORT_COUNT*ADDRESS_WIDTH-1:0] wa;
input [WRITE_PORT_COUNT-1:0] we;
input clk;
integer i,j,k;
reg [DATA_WIDTH-1:0] mem [0:WORD_COUNT-1];
reg [ADDRESS_WIDTH-1:0] rat;
reg [ADDRESS_WIDTH-1:0] rai [READ_PORT_COUNT-1:0];
reg [ADDRESS_WIDTH-1:0] rai_reg [READ_PORT_COUNT-1:0];
reg [READ_PORT_COUNT*DATA_WIDTH-1:0] qi;
reg [DATA_WIDTH-1:0] qt;
reg [DATA_WIDTH-1:0] di [WRITE_PORT_COUNT-1:0];
reg [DATA_WIDTH-1:0] dt;
reg [ADDRESS_WIDTH-1:0] wat;
reg [ADDRESS_WIDTH-1:0] wai [WRITE_PORT_COUNT-1:0];
// Split input data
always @ (d) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<DATA_WIDTH;j=j+1) begin
dt[j]=d[i*DATA_WIDTH+j];
end
di[i]=dt;
end
end
// Split write addresses
always @ (wa) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
wat[j]=wa[i*ADDRESS_WIDTH+j];
end
wai[i]=wat;
end
end
// Write memory
always @ (posedge clk) begin
for (j=0;j<WRITE_PORT_COUNT;j=j+1) begin
if (we[j]) begin
mem[wai[j]] <= di[j];
end
end
end
// Split read addresses
always @ (ra) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
rat[j]=ra[i*ADDRESS_WIDTH+j];
end
rai[i]=rat;
end
end
// guide read addresses using CE
always @ (posedge clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if ( ce[i] ) begin
rai_reg[i] <= rai[i];
end
end
end
// Memory read
always @ (rai_reg[0] or clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if (rai_reg[i] >= WORD_COUNT) begin
qt={DATA_WIDTH {1'b0}};
end else begin
qt=mem[rai_reg[i]];
end
for (j=0;j<DATA_WIDTH;j=j+1) begin
qi[i*DATA_WIDTH+j]=qt[j];
end
end
end
assign q=qi;
endmodule
`endcelldefine
module denoise_u5_p0 (
address0,
ce0,
q0,
we0,
d0,
clk);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd225;
parameter AddressWidth = 32'd8;
input[AddressWidth-1:0] address0;
input ce0;
output[DataWidth-1:0] q0;
input we0;
input[DataWidth-1:0] d0;
input clk;
reg[DataWidth-1:0] q0;
wire[1 * DataWidth - 1:0] mem_q;
wire[DataWidth - 1:0] mem_q0;
wire[1 - 1:0] mem_we;
wire[1 * DataWidth - 1:0] mem_d;
wire[1 * AddressWidth - 1:0] mem_wa;
wire[1 * AddressWidth - 1:0] mem_ra;
wire[1 - 1:0] mem_ce;
denoise_u5_p0_core #(
.READ_PORT_COUNT( 1 ),
.WRITE_PORT_COUNT( 1 ),
.DATA_WIDTH( DataWidth ),
.ADDRESS_WIDTH( AddressWidth ),
.WORD_COUNT( AddressRange ))
core_inst (
.q( mem_q ),
.ra( mem_ra ),
.ce( mem_ce ),
.d( mem_d ),
.wa( mem_wa ),
.we( mem_we ),
.clk( clk ));
assign mem_q0 = mem_q[1 * DataWidth - 1 : 0 * DataWidth];
always @ (mem_q0) begin
q0 = mem_q0;
end
assign mem_ra = {address0};
assign mem_ce = {ce0};
assign mem_we[0] = we0;
assign mem_d = {d0};
assign mem_wa = {address0};
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
`celldefine
module denoise_u5_p1_core (q, ra, ce, clk, d, wa, we);
parameter READ_PORT_COUNT=32'd1;
parameter WRITE_PORT_COUNT=32'd1;
parameter DATA_WIDTH=32'd32;
parameter ADDRESS_WIDTH=32'd8;
parameter WORD_COUNT=32'd225;
output [READ_PORT_COUNT*DATA_WIDTH-1:0] q;
input [READ_PORT_COUNT*ADDRESS_WIDTH-1:0] ra;
input [READ_PORT_COUNT-1:0] ce;
input [WRITE_PORT_COUNT*DATA_WIDTH-1:0] d;
input [WRITE_PORT_COUNT*ADDRESS_WIDTH-1:0] wa;
input [WRITE_PORT_COUNT-1:0] we;
input clk;
integer i,j,k;
reg [DATA_WIDTH-1:0] mem [0:WORD_COUNT-1];
reg [ADDRESS_WIDTH-1:0] rat;
reg [ADDRESS_WIDTH-1:0] rai [READ_PORT_COUNT-1:0];
reg [ADDRESS_WIDTH-1:0] rai_reg [READ_PORT_COUNT-1:0];
reg [READ_PORT_COUNT*DATA_WIDTH-1:0] qi;
reg [DATA_WIDTH-1:0] qt;
reg [DATA_WIDTH-1:0] di [WRITE_PORT_COUNT-1:0];
reg [DATA_WIDTH-1:0] dt;
reg [ADDRESS_WIDTH-1:0] wat;
reg [ADDRESS_WIDTH-1:0] wai [WRITE_PORT_COUNT-1:0];
// Split input data
always @ (d) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<DATA_WIDTH;j=j+1) begin
dt[j]=d[i*DATA_WIDTH+j];
end
di[i]=dt;
end
end
// Split write addresses
always @ (wa) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
wat[j]=wa[i*ADDRESS_WIDTH+j];
end
wai[i]=wat;
end
end
// Write memory
always @ (posedge clk) begin
for (j=0;j<WRITE_PORT_COUNT;j=j+1) begin
if (we[j]) begin
mem[wai[j]] <= di[j];
end
end
end
// Split read addresses
always @ (ra) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
rat[j]=ra[i*ADDRESS_WIDTH+j];
end
rai[i]=rat;
end
end
// guide read addresses using CE
always @ (posedge clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if ( ce[i] ) begin
rai_reg[i] <= rai[i];
end
end
end
// Memory read
always @ (rai_reg[0] or clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if (rai_reg[i] >= WORD_COUNT) begin
qt={DATA_WIDTH {1'b0}};
end else begin
qt=mem[rai_reg[i]];
end
for (j=0;j<DATA_WIDTH;j=j+1) begin
qi[i*DATA_WIDTH+j]=qt[j];
end
end
end
assign q=qi;
endmodule
`endcelldefine
module denoise_u5_p1 (
address0,
ce0,
q0,
we0,
d0,
clk);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd225;
parameter AddressWidth = 32'd8;
input[AddressWidth-1:0] address0;
input ce0;
output[DataWidth-1:0] q0;
input we0;
input[DataWidth-1:0] d0;
input clk;
reg[DataWidth-1:0] q0;
wire[1 * DataWidth - 1:0] mem_q;
wire[DataWidth - 1:0] mem_q0;
wire[1 - 1:0] mem_we;
wire[1 * DataWidth - 1:0] mem_d;
wire[1 * AddressWidth - 1:0] mem_wa;
wire[1 * AddressWidth - 1:0] mem_ra;
wire[1 - 1:0] mem_ce;
denoise_u5_p1_core #(
.READ_PORT_COUNT( 1 ),
.WRITE_PORT_COUNT( 1 ),
.DATA_WIDTH( DataWidth ),
.ADDRESS_WIDTH( AddressWidth ),
.WORD_COUNT( AddressRange ))
core_inst (
.q( mem_q ),
.ra( mem_ra ),
.ce( mem_ce ),
.d( mem_d ),
.wa( mem_wa ),
.we( mem_we ),
.clk( clk ));
assign mem_q0 = mem_q[1 * DataWidth - 1 : 0 * DataWidth];
always @ (mem_q0) begin
q0 = mem_q0;
end
assign mem_ra = {address0};
assign mem_ce = {ce0};
assign mem_we[0] = we0;
assign mem_d = {d0};
assign mem_wa = {address0};
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
`celldefine
module denoise_u5_p2_core (q, ra, ce, clk, d, wa, we);
parameter READ_PORT_COUNT=32'd1;
parameter WRITE_PORT_COUNT=32'd1;
parameter DATA_WIDTH=32'd32;
parameter ADDRESS_WIDTH=32'd8;
parameter WORD_COUNT=32'd225;
output [READ_PORT_COUNT*DATA_WIDTH-1:0] q;
input [READ_PORT_COUNT*ADDRESS_WIDTH-1:0] ra;
input [READ_PORT_COUNT-1:0] ce;
input [WRITE_PORT_COUNT*DATA_WIDTH-1:0] d;
input [WRITE_PORT_COUNT*ADDRESS_WIDTH-1:0] wa;
input [WRITE_PORT_COUNT-1:0] we;
input clk;
integer i,j,k;
reg [DATA_WIDTH-1:0] mem [0:WORD_COUNT-1];
reg [ADDRESS_WIDTH-1:0] rat;
reg [ADDRESS_WIDTH-1:0] rai [READ_PORT_COUNT-1:0];
reg [ADDRESS_WIDTH-1:0] rai_reg [READ_PORT_COUNT-1:0];
reg [READ_PORT_COUNT*DATA_WIDTH-1:0] qi;
reg [DATA_WIDTH-1:0] qt;
reg [DATA_WIDTH-1:0] di [WRITE_PORT_COUNT-1:0];
reg [DATA_WIDTH-1:0] dt;
reg [ADDRESS_WIDTH-1:0] wat;
reg [ADDRESS_WIDTH-1:0] wai [WRITE_PORT_COUNT-1:0];
// Split input data
always @ (d) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<DATA_WIDTH;j=j+1) begin
dt[j]=d[i*DATA_WIDTH+j];
end
di[i]=dt;
end
end
// Split write addresses
always @ (wa) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
wat[j]=wa[i*ADDRESS_WIDTH+j];
end
wai[i]=wat;
end
end
// Write memory
always @ (posedge clk) begin
for (j=0;j<WRITE_PORT_COUNT;j=j+1) begin
if (we[j]) begin
mem[wai[j]] <= di[j];
end
end
end
// Split read addresses
always @ (ra) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
rat[j]=ra[i*ADDRESS_WIDTH+j];
end
rai[i]=rat;
end
end
// guide read addresses using CE
always @ (posedge clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if ( ce[i] ) begin
rai_reg[i] <= rai[i];
end
end
end
// Memory read
always @ (rai_reg[0] or clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if (rai_reg[i] >= WORD_COUNT) begin
qt={DATA_WIDTH {1'b0}};
end else begin
qt=mem[rai_reg[i]];
end
for (j=0;j<DATA_WIDTH;j=j+1) begin
qi[i*DATA_WIDTH+j]=qt[j];
end
end
end
assign q=qi;
endmodule
`endcelldefine
module denoise_u5_p2 (
address0,
ce0,
q0,
we0,
d0,
clk);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd225;
parameter AddressWidth = 32'd8;
input[AddressWidth-1:0] address0;
input ce0;
output[DataWidth-1:0] q0;
input we0;
input[DataWidth-1:0] d0;
input clk;
reg[DataWidth-1:0] q0;
wire[1 * DataWidth - 1:0] mem_q;
wire[DataWidth - 1:0] mem_q0;
wire[1 - 1:0] mem_we;
wire[1 * DataWidth - 1:0] mem_d;
wire[1 * AddressWidth - 1:0] mem_wa;
wire[1 * AddressWidth - 1:0] mem_ra;
wire[1 - 1:0] mem_ce;
denoise_u5_p2_core #(
.READ_PORT_COUNT( 1 ),
.WRITE_PORT_COUNT( 1 ),
.DATA_WIDTH( DataWidth ),
.ADDRESS_WIDTH( AddressWidth ),
.WORD_COUNT( AddressRange ))
core_inst (
.q( mem_q ),
.ra( mem_ra ),
.ce( mem_ce ),
.d( mem_d ),
.wa( mem_wa ),
.we( mem_we ),
.clk( clk ));
assign mem_q0 = mem_q[1 * DataWidth - 1 : 0 * DataWidth];
always @ (mem_q0) begin
q0 = mem_q0;
end
assign mem_ra = {address0};
assign mem_ce = {ce0};
assign mem_we[0] = we0;
assign mem_d = {d0};
assign mem_wa = {address0};
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
`celldefine
module denoise_u5_p3_core (q, ra, ce, clk, d, wa, we);
parameter READ_PORT_COUNT=32'd2;
parameter WRITE_PORT_COUNT=32'd1;
parameter DATA_WIDTH=32'd32;
parameter ADDRESS_WIDTH=32'd8;
parameter WORD_COUNT=32'd225;
output [READ_PORT_COUNT*DATA_WIDTH-1:0] q;
input [READ_PORT_COUNT*ADDRESS_WIDTH-1:0] ra;
input [READ_PORT_COUNT-1:0] ce;
input [WRITE_PORT_COUNT*DATA_WIDTH-1:0] d;
input [WRITE_PORT_COUNT*ADDRESS_WIDTH-1:0] wa;
input [WRITE_PORT_COUNT-1:0] we;
input clk;
integer i,j,k;
reg [DATA_WIDTH-1:0] mem [0:WORD_COUNT-1];
reg [ADDRESS_WIDTH-1:0] rat;
reg [ADDRESS_WIDTH-1:0] rai [READ_PORT_COUNT-1:0];
reg [ADDRESS_WIDTH-1:0] rai_reg [READ_PORT_COUNT-1:0];
reg [READ_PORT_COUNT*DATA_WIDTH-1:0] qi;
reg [DATA_WIDTH-1:0] qt;
reg [DATA_WIDTH-1:0] di [WRITE_PORT_COUNT-1:0];
reg [DATA_WIDTH-1:0] dt;
reg [ADDRESS_WIDTH-1:0] wat;
reg [ADDRESS_WIDTH-1:0] wai [WRITE_PORT_COUNT-1:0];
// Split input data
always @ (d) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<DATA_WIDTH;j=j+1) begin
dt[j]=d[i*DATA_WIDTH+j];
end
di[i]=dt;
end
end
// Split write addresses
always @ (wa) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
wat[j]=wa[i*ADDRESS_WIDTH+j];
end
wai[i]=wat;
end
end
// Write memory
always @ (posedge clk) begin
for (j=0;j<WRITE_PORT_COUNT;j=j+1) begin
if (we[j]) begin
mem[wai[j]] <= di[j];
end
end
end
// Split read addresses
always @ (ra) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
rat[j]=ra[i*ADDRESS_WIDTH+j];
end
rai[i]=rat;
end
end
// guide read addresses using CE
always @ (posedge clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if ( ce[i] ) begin
rai_reg[i] <= rai[i];
end
end
end
// Memory read
always @ (rai_reg[0] or rai_reg[1] or clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if (rai_reg[i] >= WORD_COUNT) begin
qt={DATA_WIDTH {1'b0}};
end else begin
qt=mem[rai_reg[i]];
end
for (j=0;j<DATA_WIDTH;j=j+1) begin
qi[i*DATA_WIDTH+j]=qt[j];
end
end
end
assign q=qi;
endmodule
`endcelldefine
module denoise_u5_p3 (
address0,
ce0,
q0,
we0,
d0,
address1,
ce1,
q1,
clk);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd225;
parameter AddressWidth = 32'd8;
input[AddressWidth-1:0] address0;
input ce0;
output[DataWidth-1:0] q0;
input we0;
input[DataWidth-1:0] d0;
input[AddressWidth-1:0] address1;
input ce1;
output[DataWidth-1:0] q1;
input clk;
reg[DataWidth-1:0] q0;
reg[DataWidth-1:0] q1;
wire[2 * DataWidth - 1:0] mem_q;
wire[DataWidth - 1:0] mem_q0;
wire[DataWidth - 1:0] mem_q1;
wire[1 - 1:0] mem_we;
wire[1 * DataWidth - 1:0] mem_d;
wire[1 * AddressWidth - 1:0] mem_wa;
wire[2 * AddressWidth - 1:0] mem_ra;
wire[2 - 1:0] mem_ce;
denoise_u5_p3_core #(
.READ_PORT_COUNT( 2 ),
.WRITE_PORT_COUNT( 1 ),
.DATA_WIDTH( DataWidth ),
.ADDRESS_WIDTH( AddressWidth ),
.WORD_COUNT( AddressRange ))
core_inst (
.q( mem_q ),
.ra( mem_ra ),
.ce( mem_ce ),
.d( mem_d ),
.wa( mem_wa ),
.we( mem_we ),
.clk( clk ));
assign mem_q0 = mem_q[2 * DataWidth - 1 : 1 * DataWidth];
always @ (mem_q0) begin
q0 = mem_q0;
end
assign mem_q1 = mem_q[1 * DataWidth - 1 : 0 * DataWidth];
always @ (mem_q1) begin
q1 = mem_q1;
end
assign mem_ra = {address0, address1};
assign mem_ce = {ce0, ce1};
assign mem_we[0] = we0;
assign mem_d = {d0};
assign mem_wa = {address0};
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
`celldefine
module denoise_u6_p0_core (q, ra, ce, clk, d, wa, we);
parameter READ_PORT_COUNT=32'd1;
parameter WRITE_PORT_COUNT=32'd1;
parameter DATA_WIDTH=32'd32;
parameter ADDRESS_WIDTH=32'd8;
parameter WORD_COUNT=32'd225;
output [READ_PORT_COUNT*DATA_WIDTH-1:0] q;
input [READ_PORT_COUNT*ADDRESS_WIDTH-1:0] ra;
input [READ_PORT_COUNT-1:0] ce;
input [WRITE_PORT_COUNT*DATA_WIDTH-1:0] d;
input [WRITE_PORT_COUNT*ADDRESS_WIDTH-1:0] wa;
input [WRITE_PORT_COUNT-1:0] we;
input clk;
integer i,j,k;
reg [DATA_WIDTH-1:0] mem [0:WORD_COUNT-1];
reg [ADDRESS_WIDTH-1:0] rat;
reg [ADDRESS_WIDTH-1:0] rai [READ_PORT_COUNT-1:0];
reg [ADDRESS_WIDTH-1:0] rai_reg [READ_PORT_COUNT-1:0];
reg [READ_PORT_COUNT*DATA_WIDTH-1:0] qi;
reg [DATA_WIDTH-1:0] qt;
reg [DATA_WIDTH-1:0] di [WRITE_PORT_COUNT-1:0];
reg [DATA_WIDTH-1:0] dt;
reg [ADDRESS_WIDTH-1:0] wat;
reg [ADDRESS_WIDTH-1:0] wai [WRITE_PORT_COUNT-1:0];
// Split input data
always @ (d) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<DATA_WIDTH;j=j+1) begin
dt[j]=d[i*DATA_WIDTH+j];
end
di[i]=dt;
end
end
// Split write addresses
always @ (wa) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
wat[j]=wa[i*ADDRESS_WIDTH+j];
end
wai[i]=wat;
end
end
// Write memory
always @ (posedge clk) begin
for (j=0;j<WRITE_PORT_COUNT;j=j+1) begin
if (we[j]) begin
mem[wai[j]] <= di[j];
end
end
end
// Split read addresses
always @ (ra) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
rat[j]=ra[i*ADDRESS_WIDTH+j];
end
rai[i]=rat;
end
end
// guide read addresses using CE
always @ (posedge clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if ( ce[i] ) begin
rai_reg[i] <= rai[i];
end
end
end
// Memory read
always @ (rai_reg[0] or clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if (rai_reg[i] >= WORD_COUNT) begin
qt={DATA_WIDTH {1'b0}};
end else begin
qt=mem[rai_reg[i]];
end
for (j=0;j<DATA_WIDTH;j=j+1) begin
qi[i*DATA_WIDTH+j]=qt[j];
end
end
end
assign q=qi;
endmodule
`endcelldefine
module denoise_u6_p0 (
address0,
ce0,
q0,
we0,
d0,
clk);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd225;
parameter AddressWidth = 32'd8;
input[AddressWidth-1:0] address0;
input ce0;
output[DataWidth-1:0] q0;
input we0;
input[DataWidth-1:0] d0;
input clk;
reg[DataWidth-1:0] q0;
wire[1 * DataWidth - 1:0] mem_q;
wire[DataWidth - 1:0] mem_q0;
wire[1 - 1:0] mem_we;
wire[1 * DataWidth - 1:0] mem_d;
wire[1 * AddressWidth - 1:0] mem_wa;
wire[1 * AddressWidth - 1:0] mem_ra;
wire[1 - 1:0] mem_ce;
denoise_u6_p0_core #(
.READ_PORT_COUNT( 1 ),
.WRITE_PORT_COUNT( 1 ),
.DATA_WIDTH( DataWidth ),
.ADDRESS_WIDTH( AddressWidth ),
.WORD_COUNT( AddressRange ))
core_inst (
.q( mem_q ),
.ra( mem_ra ),
.ce( mem_ce ),
.d( mem_d ),
.wa( mem_wa ),
.we( mem_we ),
.clk( clk ));
assign mem_q0 = mem_q[1 * DataWidth - 1 : 0 * DataWidth];
always @ (mem_q0) begin
q0 = mem_q0;
end
assign mem_ra = {address0};
assign mem_ce = {ce0};
assign mem_we[0] = we0;
assign mem_d = {d0};
assign mem_wa = {address0};
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
`celldefine
module denoise_u6_p1_core (q, ra, ce, clk, d, wa, we);
parameter READ_PORT_COUNT=32'd1;
parameter WRITE_PORT_COUNT=32'd1;
parameter DATA_WIDTH=32'd32;
parameter ADDRESS_WIDTH=32'd8;
parameter WORD_COUNT=32'd225;
output [READ_PORT_COUNT*DATA_WIDTH-1:0] q;
input [READ_PORT_COUNT*ADDRESS_WIDTH-1:0] ra;
input [READ_PORT_COUNT-1:0] ce;
input [WRITE_PORT_COUNT*DATA_WIDTH-1:0] d;
input [WRITE_PORT_COUNT*ADDRESS_WIDTH-1:0] wa;
input [WRITE_PORT_COUNT-1:0] we;
input clk;
integer i,j,k;
reg [DATA_WIDTH-1:0] mem [0:WORD_COUNT-1];
reg [ADDRESS_WIDTH-1:0] rat;
reg [ADDRESS_WIDTH-1:0] rai [READ_PORT_COUNT-1:0];
reg [ADDRESS_WIDTH-1:0] rai_reg [READ_PORT_COUNT-1:0];
reg [READ_PORT_COUNT*DATA_WIDTH-1:0] qi;
reg [DATA_WIDTH-1:0] qt;
reg [DATA_WIDTH-1:0] di [WRITE_PORT_COUNT-1:0];
reg [DATA_WIDTH-1:0] dt;
reg [ADDRESS_WIDTH-1:0] wat;
reg [ADDRESS_WIDTH-1:0] wai [WRITE_PORT_COUNT-1:0];
// Split input data
always @ (d) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<DATA_WIDTH;j=j+1) begin
dt[j]=d[i*DATA_WIDTH+j];
end
di[i]=dt;
end
end
// Split write addresses
always @ (wa) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
wat[j]=wa[i*ADDRESS_WIDTH+j];
end
wai[i]=wat;
end
end
// Write memory
always @ (posedge clk) begin
for (j=0;j<WRITE_PORT_COUNT;j=j+1) begin
if (we[j]) begin
mem[wai[j]] <= di[j];
end
end
end
// Split read addresses
always @ (ra) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
rat[j]=ra[i*ADDRESS_WIDTH+j];
end
rai[i]=rat;
end
end
// guide read addresses using CE
always @ (posedge clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if ( ce[i] ) begin
rai_reg[i] <= rai[i];
end
end
end
// Memory read
always @ (rai_reg[0] or clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if (rai_reg[i] >= WORD_COUNT) begin
qt={DATA_WIDTH {1'b0}};
end else begin
qt=mem[rai_reg[i]];
end
for (j=0;j<DATA_WIDTH;j=j+1) begin
qi[i*DATA_WIDTH+j]=qt[j];
end
end
end
assign q=qi;
endmodule
`endcelldefine
module denoise_u6_p1 (
address0,
ce0,
q0,
we0,
d0,
clk);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd225;
parameter AddressWidth = 32'd8;
input[AddressWidth-1:0] address0;
input ce0;
output[DataWidth-1:0] q0;
input we0;
input[DataWidth-1:0] d0;
input clk;
reg[DataWidth-1:0] q0;
wire[1 * DataWidth - 1:0] mem_q;
wire[DataWidth - 1:0] mem_q0;
wire[1 - 1:0] mem_we;
wire[1 * DataWidth - 1:0] mem_d;
wire[1 * AddressWidth - 1:0] mem_wa;
wire[1 * AddressWidth - 1:0] mem_ra;
wire[1 - 1:0] mem_ce;
denoise_u6_p1_core #(
.READ_PORT_COUNT( 1 ),
.WRITE_PORT_COUNT( 1 ),
.DATA_WIDTH( DataWidth ),
.ADDRESS_WIDTH( AddressWidth ),
.WORD_COUNT( AddressRange ))
core_inst (
.q( mem_q ),
.ra( mem_ra ),
.ce( mem_ce ),
.d( mem_d ),
.wa( mem_wa ),
.we( mem_we ),
.clk( clk ));
assign mem_q0 = mem_q[1 * DataWidth - 1 : 0 * DataWidth];
always @ (mem_q0) begin
q0 = mem_q0;
end
assign mem_ra = {address0};
assign mem_ce = {ce0};
assign mem_we[0] = we0;
assign mem_d = {d0};
assign mem_wa = {address0};
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
`celldefine
module denoise_u6_p2_core (q, ra, ce, clk, d, wa, we);
parameter READ_PORT_COUNT=32'd1;
parameter WRITE_PORT_COUNT=32'd1;
parameter DATA_WIDTH=32'd32;
parameter ADDRESS_WIDTH=32'd8;
parameter WORD_COUNT=32'd225;
output [READ_PORT_COUNT*DATA_WIDTH-1:0] q;
input [READ_PORT_COUNT*ADDRESS_WIDTH-1:0] ra;
input [READ_PORT_COUNT-1:0] ce;
input [WRITE_PORT_COUNT*DATA_WIDTH-1:0] d;
input [WRITE_PORT_COUNT*ADDRESS_WIDTH-1:0] wa;
input [WRITE_PORT_COUNT-1:0] we;
input clk;
integer i,j,k;
reg [DATA_WIDTH-1:0] mem [0:WORD_COUNT-1];
reg [ADDRESS_WIDTH-1:0] rat;
reg [ADDRESS_WIDTH-1:0] rai [READ_PORT_COUNT-1:0];
reg [ADDRESS_WIDTH-1:0] rai_reg [READ_PORT_COUNT-1:0];
reg [READ_PORT_COUNT*DATA_WIDTH-1:0] qi;
reg [DATA_WIDTH-1:0] qt;
reg [DATA_WIDTH-1:0] di [WRITE_PORT_COUNT-1:0];
reg [DATA_WIDTH-1:0] dt;
reg [ADDRESS_WIDTH-1:0] wat;
reg [ADDRESS_WIDTH-1:0] wai [WRITE_PORT_COUNT-1:0];
// Split input data
always @ (d) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<DATA_WIDTH;j=j+1) begin
dt[j]=d[i*DATA_WIDTH+j];
end
di[i]=dt;
end
end
// Split write addresses
always @ (wa) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
wat[j]=wa[i*ADDRESS_WIDTH+j];
end
wai[i]=wat;
end
end
// Write memory
always @ (posedge clk) begin
for (j=0;j<WRITE_PORT_COUNT;j=j+1) begin
if (we[j]) begin
mem[wai[j]] <= di[j];
end
end
end
// Split read addresses
always @ (ra) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
rat[j]=ra[i*ADDRESS_WIDTH+j];
end
rai[i]=rat;
end
end
// guide read addresses using CE
always @ (posedge clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if ( ce[i] ) begin
rai_reg[i] <= rai[i];
end
end
end
// Memory read
always @ (rai_reg[0] or clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if (rai_reg[i] >= WORD_COUNT) begin
qt={DATA_WIDTH {1'b0}};
end else begin
qt=mem[rai_reg[i]];
end
for (j=0;j<DATA_WIDTH;j=j+1) begin
qi[i*DATA_WIDTH+j]=qt[j];
end
end
end
assign q=qi;
endmodule
`endcelldefine
module denoise_u6_p2 (
address0,
ce0,
q0,
we0,
d0,
clk);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd225;
parameter AddressWidth = 32'd8;
input[AddressWidth-1:0] address0;
input ce0;
output[DataWidth-1:0] q0;
input we0;
input[DataWidth-1:0] d0;
input clk;
reg[DataWidth-1:0] q0;
wire[1 * DataWidth - 1:0] mem_q;
wire[DataWidth - 1:0] mem_q0;
wire[1 - 1:0] mem_we;
wire[1 * DataWidth - 1:0] mem_d;
wire[1 * AddressWidth - 1:0] mem_wa;
wire[1 * AddressWidth - 1:0] mem_ra;
wire[1 - 1:0] mem_ce;
denoise_u6_p2_core #(
.READ_PORT_COUNT( 1 ),
.WRITE_PORT_COUNT( 1 ),
.DATA_WIDTH( DataWidth ),
.ADDRESS_WIDTH( AddressWidth ),
.WORD_COUNT( AddressRange ))
core_inst (
.q( mem_q ),
.ra( mem_ra ),
.ce( mem_ce ),
.d( mem_d ),
.wa( mem_wa ),
.we( mem_we ),
.clk( clk ));
assign mem_q0 = mem_q[1 * DataWidth - 1 : 0 * DataWidth];
always @ (mem_q0) begin
q0 = mem_q0;
end
assign mem_ra = {address0};
assign mem_ce = {ce0};
assign mem_we[0] = we0;
assign mem_d = {d0};
assign mem_wa = {address0};
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
`celldefine
module denoise_u6_p3_core (q, ra, ce, clk, d, wa, we);
parameter READ_PORT_COUNT=32'd2;
parameter WRITE_PORT_COUNT=32'd1;
parameter DATA_WIDTH=32'd32;
parameter ADDRESS_WIDTH=32'd8;
parameter WORD_COUNT=32'd225;
output [READ_PORT_COUNT*DATA_WIDTH-1:0] q;
input [READ_PORT_COUNT*ADDRESS_WIDTH-1:0] ra;
input [READ_PORT_COUNT-1:0] ce;
input [WRITE_PORT_COUNT*DATA_WIDTH-1:0] d;
input [WRITE_PORT_COUNT*ADDRESS_WIDTH-1:0] wa;
input [WRITE_PORT_COUNT-1:0] we;
input clk;
integer i,j,k;
reg [DATA_WIDTH-1:0] mem [0:WORD_COUNT-1];
reg [ADDRESS_WIDTH-1:0] rat;
reg [ADDRESS_WIDTH-1:0] rai [READ_PORT_COUNT-1:0];
reg [ADDRESS_WIDTH-1:0] rai_reg [READ_PORT_COUNT-1:0];
reg [READ_PORT_COUNT*DATA_WIDTH-1:0] qi;
reg [DATA_WIDTH-1:0] qt;
reg [DATA_WIDTH-1:0] di [WRITE_PORT_COUNT-1:0];
reg [DATA_WIDTH-1:0] dt;
reg [ADDRESS_WIDTH-1:0] wat;
reg [ADDRESS_WIDTH-1:0] wai [WRITE_PORT_COUNT-1:0];
// Split input data
always @ (d) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<DATA_WIDTH;j=j+1) begin
dt[j]=d[i*DATA_WIDTH+j];
end
di[i]=dt;
end
end
// Split write addresses
always @ (wa) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
wat[j]=wa[i*ADDRESS_WIDTH+j];
end
wai[i]=wat;
end
end
// Write memory
always @ (posedge clk) begin
for (j=0;j<WRITE_PORT_COUNT;j=j+1) begin
if (we[j]) begin
mem[wai[j]] <= di[j];
end
end
end
// Split read addresses
always @ (ra) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
rat[j]=ra[i*ADDRESS_WIDTH+j];
end
rai[i]=rat;
end
end
// guide read addresses using CE
always @ (posedge clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if ( ce[i] ) begin
rai_reg[i] <= rai[i];
end
end
end
// Memory read
always @ (rai_reg[0] or rai_reg[1] or clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if (rai_reg[i] >= WORD_COUNT) begin
qt={DATA_WIDTH {1'b0}};
end else begin
qt=mem[rai_reg[i]];
end
for (j=0;j<DATA_WIDTH;j=j+1) begin
qi[i*DATA_WIDTH+j]=qt[j];
end
end
end
assign q=qi;
endmodule
`endcelldefine
module denoise_u6_p3 (
address0,
ce0,
q0,
we0,
d0,
address1,
ce1,
q1,
clk);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd225;
parameter AddressWidth = 32'd8;
input[AddressWidth-1:0] address0;
input ce0;
output[DataWidth-1:0] q0;
input we0;
input[DataWidth-1:0] d0;
input[AddressWidth-1:0] address1;
input ce1;
output[DataWidth-1:0] q1;
input clk;
reg[DataWidth-1:0] q0;
reg[DataWidth-1:0] q1;
wire[2 * DataWidth - 1:0] mem_q;
wire[DataWidth - 1:0] mem_q0;
wire[DataWidth - 1:0] mem_q1;
wire[1 - 1:0] mem_we;
wire[1 * DataWidth - 1:0] mem_d;
wire[1 * AddressWidth - 1:0] mem_wa;
wire[2 * AddressWidth - 1:0] mem_ra;
wire[2 - 1:0] mem_ce;
denoise_u6_p3_core #(
.READ_PORT_COUNT( 2 ),
.WRITE_PORT_COUNT( 1 ),
.DATA_WIDTH( DataWidth ),
.ADDRESS_WIDTH( AddressWidth ),
.WORD_COUNT( AddressRange ))
core_inst (
.q( mem_q ),
.ra( mem_ra ),
.ce( mem_ce ),
.d( mem_d ),
.wa( mem_wa ),
.we( mem_we ),
.clk( clk ));
assign mem_q0 = mem_q[2 * DataWidth - 1 : 1 * DataWidth];
always @ (mem_q0) begin
q0 = mem_q0;
end
assign mem_q1 = mem_q[1 * DataWidth - 1 : 0 * DataWidth];
always @ (mem_q1) begin
q1 = mem_q1;
end
assign mem_ra = {address0, address1};
assign mem_ce = {ce0, ce1};
assign mem_we[0] = we0;
assign mem_d = {d0};
assign mem_wa = {address0};
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
`celldefine
module denoise_ug0_p0_core (q, ra, ce, clk, d, wa, we);
parameter READ_PORT_COUNT=32'd2;
parameter WRITE_PORT_COUNT=32'd1;
parameter DATA_WIDTH=32'd32;
parameter ADDRESS_WIDTH=32'd8;
parameter WORD_COUNT=32'd225;
output [READ_PORT_COUNT*DATA_WIDTH-1:0] q;
input [READ_PORT_COUNT*ADDRESS_WIDTH-1:0] ra;
input [READ_PORT_COUNT-1:0] ce;
input [WRITE_PORT_COUNT*DATA_WIDTH-1:0] d;
input [WRITE_PORT_COUNT*ADDRESS_WIDTH-1:0] wa;
input [WRITE_PORT_COUNT-1:0] we;
input clk;
integer i,j,k;
reg [DATA_WIDTH-1:0] mem [0:WORD_COUNT-1];
reg [ADDRESS_WIDTH-1:0] rat;
reg [ADDRESS_WIDTH-1:0] rai [READ_PORT_COUNT-1:0];
reg [ADDRESS_WIDTH-1:0] rai_reg [READ_PORT_COUNT-1:0];
reg [READ_PORT_COUNT*DATA_WIDTH-1:0] qi;
reg [DATA_WIDTH-1:0] qt;
reg [DATA_WIDTH-1:0] di [WRITE_PORT_COUNT-1:0];
reg [DATA_WIDTH-1:0] dt;
reg [ADDRESS_WIDTH-1:0] wat;
reg [ADDRESS_WIDTH-1:0] wai [WRITE_PORT_COUNT-1:0];
// Split input data
always @ (d) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<DATA_WIDTH;j=j+1) begin
dt[j]=d[i*DATA_WIDTH+j];
end
di[i]=dt;
end
end
// Split write addresses
always @ (wa) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
wat[j]=wa[i*ADDRESS_WIDTH+j];
end
wai[i]=wat;
end
end
// Write memory
always @ (posedge clk) begin
for (j=0;j<WRITE_PORT_COUNT;j=j+1) begin
if (we[j]) begin
mem[wai[j]] <= di[j];
end
end
end
// Split read addresses
always @ (ra) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
rat[j]=ra[i*ADDRESS_WIDTH+j];
end
rai[i]=rat;
end
end
// guide read addresses using CE
always @ (posedge clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if ( ce[i] ) begin
rai_reg[i] <= rai[i];
end
end
end
// Memory read
always @ (rai_reg[0] or rai_reg[1] or clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if (rai_reg[i] >= WORD_COUNT) begin
qt={DATA_WIDTH {1'b0}};
end else begin
qt=mem[rai_reg[i]];
end
for (j=0;j<DATA_WIDTH;j=j+1) begin
qi[i*DATA_WIDTH+j]=qt[j];
end
end
end
assign q=qi;
endmodule
`endcelldefine
module denoise_ug0_p0 (
address0,
ce0,
q0,
we0,
d0,
address1,
ce1,
q1,
clk);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd225;
parameter AddressWidth = 32'd8;
input[AddressWidth-1:0] address0;
input ce0;
output[DataWidth-1:0] q0;
input we0;
input[DataWidth-1:0] d0;
input[AddressWidth-1:0] address1;
input ce1;
output[DataWidth-1:0] q1;
input clk;
reg[DataWidth-1:0] q0;
reg[DataWidth-1:0] q1;
wire[2 * DataWidth - 1:0] mem_q;
wire[DataWidth - 1:0] mem_q0;
wire[DataWidth - 1:0] mem_q1;
wire[1 - 1:0] mem_we;
wire[1 * DataWidth - 1:0] mem_d;
wire[1 * AddressWidth - 1:0] mem_wa;
wire[2 * AddressWidth - 1:0] mem_ra;
wire[2 - 1:0] mem_ce;
denoise_ug0_p0_core #(
.READ_PORT_COUNT( 2 ),
.WRITE_PORT_COUNT( 1 ),
.DATA_WIDTH( DataWidth ),
.ADDRESS_WIDTH( AddressWidth ),
.WORD_COUNT( AddressRange ))
core_inst (
.q( mem_q ),
.ra( mem_ra ),
.ce( mem_ce ),
.d( mem_d ),
.wa( mem_wa ),
.we( mem_we ),
.clk( clk ));
assign mem_q0 = mem_q[2 * DataWidth - 1 : 1 * DataWidth];
always @ (mem_q0) begin
q0 = mem_q0;
end
assign mem_q1 = mem_q[1 * DataWidth - 1 : 0 * DataWidth];
always @ (mem_q1) begin
q1 = mem_q1;
end
assign mem_ra = {address0, address1};
assign mem_ce = {ce0, ce1};
assign mem_we[0] = we0;
assign mem_d = {d0};
assign mem_wa = {address0};
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
`celldefine
module denoise_ug0_p1_core (q, ra, ce, clk, d, wa, we);
parameter READ_PORT_COUNT=32'd1;
parameter WRITE_PORT_COUNT=32'd1;
parameter DATA_WIDTH=32'd32;
parameter ADDRESS_WIDTH=32'd8;
parameter WORD_COUNT=32'd225;
output [READ_PORT_COUNT*DATA_WIDTH-1:0] q;
input [READ_PORT_COUNT*ADDRESS_WIDTH-1:0] ra;
input [READ_PORT_COUNT-1:0] ce;
input [WRITE_PORT_COUNT*DATA_WIDTH-1:0] d;
input [WRITE_PORT_COUNT*ADDRESS_WIDTH-1:0] wa;
input [WRITE_PORT_COUNT-1:0] we;
input clk;
integer i,j,k;
reg [DATA_WIDTH-1:0] mem [0:WORD_COUNT-1];
reg [ADDRESS_WIDTH-1:0] rat;
reg [ADDRESS_WIDTH-1:0] rai [READ_PORT_COUNT-1:0];
reg [ADDRESS_WIDTH-1:0] rai_reg [READ_PORT_COUNT-1:0];
reg [READ_PORT_COUNT*DATA_WIDTH-1:0] qi;
reg [DATA_WIDTH-1:0] qt;
reg [DATA_WIDTH-1:0] di [WRITE_PORT_COUNT-1:0];
reg [DATA_WIDTH-1:0] dt;
reg [ADDRESS_WIDTH-1:0] wat;
reg [ADDRESS_WIDTH-1:0] wai [WRITE_PORT_COUNT-1:0];
// Split input data
always @ (d) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<DATA_WIDTH;j=j+1) begin
dt[j]=d[i*DATA_WIDTH+j];
end
di[i]=dt;
end
end
// Split write addresses
always @ (wa) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
wat[j]=wa[i*ADDRESS_WIDTH+j];
end
wai[i]=wat;
end
end
// Write memory
always @ (posedge clk) begin
for (j=0;j<WRITE_PORT_COUNT;j=j+1) begin
if (we[j]) begin
mem[wai[j]] <= di[j];
end
end
end
// Split read addresses
always @ (ra) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
rat[j]=ra[i*ADDRESS_WIDTH+j];
end
rai[i]=rat;
end
end
// guide read addresses using CE
always @ (posedge clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if ( ce[i] ) begin
rai_reg[i] <= rai[i];
end
end
end
// Memory read
always @ (rai_reg[0] or clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if (rai_reg[i] >= WORD_COUNT) begin
qt={DATA_WIDTH {1'b0}};
end else begin
qt=mem[rai_reg[i]];
end
for (j=0;j<DATA_WIDTH;j=j+1) begin
qi[i*DATA_WIDTH+j]=qt[j];
end
end
end
assign q=qi;
endmodule
`endcelldefine
module denoise_ug0_p1 (
address0,
ce0,
q0,
we0,
d0,
clk);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd225;
parameter AddressWidth = 32'd8;
input[AddressWidth-1:0] address0;
input ce0;
output[DataWidth-1:0] q0;
input we0;
input[DataWidth-1:0] d0;
input clk;
reg[DataWidth-1:0] q0;
wire[1 * DataWidth - 1:0] mem_q;
wire[DataWidth - 1:0] mem_q0;
wire[1 - 1:0] mem_we;
wire[1 * DataWidth - 1:0] mem_d;
wire[1 * AddressWidth - 1:0] mem_wa;
wire[1 * AddressWidth - 1:0] mem_ra;
wire[1 - 1:0] mem_ce;
denoise_ug0_p1_core #(
.READ_PORT_COUNT( 1 ),
.WRITE_PORT_COUNT( 1 ),
.DATA_WIDTH( DataWidth ),
.ADDRESS_WIDTH( AddressWidth ),
.WORD_COUNT( AddressRange ))
core_inst (
.q( mem_q ),
.ra( mem_ra ),
.ce( mem_ce ),
.d( mem_d ),
.wa( mem_wa ),
.we( mem_we ),
.clk( clk ));
assign mem_q0 = mem_q[1 * DataWidth - 1 : 0 * DataWidth];
always @ (mem_q0) begin
q0 = mem_q0;
end
assign mem_ra = {address0};
assign mem_ce = {ce0};
assign mem_we[0] = we0;
assign mem_d = {d0};
assign mem_wa = {address0};
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
`celldefine
module denoise_ug0_p2_core (q, ra, ce, clk, d, wa, we);
parameter READ_PORT_COUNT=32'd1;
parameter WRITE_PORT_COUNT=32'd1;
parameter DATA_WIDTH=32'd32;
parameter ADDRESS_WIDTH=32'd8;
parameter WORD_COUNT=32'd225;
output [READ_PORT_COUNT*DATA_WIDTH-1:0] q;
input [READ_PORT_COUNT*ADDRESS_WIDTH-1:0] ra;
input [READ_PORT_COUNT-1:0] ce;
input [WRITE_PORT_COUNT*DATA_WIDTH-1:0] d;
input [WRITE_PORT_COUNT*ADDRESS_WIDTH-1:0] wa;
input [WRITE_PORT_COUNT-1:0] we;
input clk;
integer i,j,k;
reg [DATA_WIDTH-1:0] mem [0:WORD_COUNT-1];
reg [ADDRESS_WIDTH-1:0] rat;
reg [ADDRESS_WIDTH-1:0] rai [READ_PORT_COUNT-1:0];
reg [ADDRESS_WIDTH-1:0] rai_reg [READ_PORT_COUNT-1:0];
reg [READ_PORT_COUNT*DATA_WIDTH-1:0] qi;
reg [DATA_WIDTH-1:0] qt;
reg [DATA_WIDTH-1:0] di [WRITE_PORT_COUNT-1:0];
reg [DATA_WIDTH-1:0] dt;
reg [ADDRESS_WIDTH-1:0] wat;
reg [ADDRESS_WIDTH-1:0] wai [WRITE_PORT_COUNT-1:0];
// Split input data
always @ (d) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<DATA_WIDTH;j=j+1) begin
dt[j]=d[i*DATA_WIDTH+j];
end
di[i]=dt;
end
end
// Split write addresses
always @ (wa) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
wat[j]=wa[i*ADDRESS_WIDTH+j];
end
wai[i]=wat;
end
end
// Write memory
always @ (posedge clk) begin
for (j=0;j<WRITE_PORT_COUNT;j=j+1) begin
if (we[j]) begin
mem[wai[j]] <= di[j];
end
end
end
// Split read addresses
always @ (ra) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
rat[j]=ra[i*ADDRESS_WIDTH+j];
end
rai[i]=rat;
end
end
// guide read addresses using CE
always @ (posedge clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if ( ce[i] ) begin
rai_reg[i] <= rai[i];
end
end
end
// Memory read
always @ (rai_reg[0] or clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if (rai_reg[i] >= WORD_COUNT) begin
qt={DATA_WIDTH {1'b0}};
end else begin
qt=mem[rai_reg[i]];
end
for (j=0;j<DATA_WIDTH;j=j+1) begin
qi[i*DATA_WIDTH+j]=qt[j];
end
end
end
assign q=qi;
endmodule
`endcelldefine
module denoise_ug0_p2 (
address0,
ce0,
q0,
we0,
d0,
clk);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd225;
parameter AddressWidth = 32'd8;
input[AddressWidth-1:0] address0;
input ce0;
output[DataWidth-1:0] q0;
input we0;
input[DataWidth-1:0] d0;
input clk;
reg[DataWidth-1:0] q0;
wire[1 * DataWidth - 1:0] mem_q;
wire[DataWidth - 1:0] mem_q0;
wire[1 - 1:0] mem_we;
wire[1 * DataWidth - 1:0] mem_d;
wire[1 * AddressWidth - 1:0] mem_wa;
wire[1 * AddressWidth - 1:0] mem_ra;
wire[1 - 1:0] mem_ce;
denoise_ug0_p2_core #(
.READ_PORT_COUNT( 1 ),
.WRITE_PORT_COUNT( 1 ),
.DATA_WIDTH( DataWidth ),
.ADDRESS_WIDTH( AddressWidth ),
.WORD_COUNT( AddressRange ))
core_inst (
.q( mem_q ),
.ra( mem_ra ),
.ce( mem_ce ),
.d( mem_d ),
.wa( mem_wa ),
.we( mem_we ),
.clk( clk ));
assign mem_q0 = mem_q[1 * DataWidth - 1 : 0 * DataWidth];
always @ (mem_q0) begin
q0 = mem_q0;
end
assign mem_ra = {address0};
assign mem_ce = {ce0};
assign mem_we[0] = we0;
assign mem_d = {d0};
assign mem_wa = {address0};
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
`celldefine
module denoise_ug0_p3_core (q, ra, ce, clk, d, wa, we);
parameter READ_PORT_COUNT=32'd2;
parameter WRITE_PORT_COUNT=32'd1;
parameter DATA_WIDTH=32'd32;
parameter ADDRESS_WIDTH=32'd8;
parameter WORD_COUNT=32'd225;
output [READ_PORT_COUNT*DATA_WIDTH-1:0] q;
input [READ_PORT_COUNT*ADDRESS_WIDTH-1:0] ra;
input [READ_PORT_COUNT-1:0] ce;
input [WRITE_PORT_COUNT*DATA_WIDTH-1:0] d;
input [WRITE_PORT_COUNT*ADDRESS_WIDTH-1:0] wa;
input [WRITE_PORT_COUNT-1:0] we;
input clk;
integer i,j,k;
reg [DATA_WIDTH-1:0] mem [0:WORD_COUNT-1];
reg [ADDRESS_WIDTH-1:0] rat;
reg [ADDRESS_WIDTH-1:0] rai [READ_PORT_COUNT-1:0];
reg [ADDRESS_WIDTH-1:0] rai_reg [READ_PORT_COUNT-1:0];
reg [READ_PORT_COUNT*DATA_WIDTH-1:0] qi;
reg [DATA_WIDTH-1:0] qt;
reg [DATA_WIDTH-1:0] di [WRITE_PORT_COUNT-1:0];
reg [DATA_WIDTH-1:0] dt;
reg [ADDRESS_WIDTH-1:0] wat;
reg [ADDRESS_WIDTH-1:0] wai [WRITE_PORT_COUNT-1:0];
// Split input data
always @ (d) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<DATA_WIDTH;j=j+1) begin
dt[j]=d[i*DATA_WIDTH+j];
end
di[i]=dt;
end
end
// Split write addresses
always @ (wa) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
wat[j]=wa[i*ADDRESS_WIDTH+j];
end
wai[i]=wat;
end
end
// Write memory
always @ (posedge clk) begin
for (j=0;j<WRITE_PORT_COUNT;j=j+1) begin
if (we[j]) begin
mem[wai[j]] <= di[j];
end
end
end
// Split read addresses
always @ (ra) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
rat[j]=ra[i*ADDRESS_WIDTH+j];
end
rai[i]=rat;
end
end
// guide read addresses using CE
always @ (posedge clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if ( ce[i] ) begin
rai_reg[i] <= rai[i];
end
end
end
// Memory read
always @ (rai_reg[0] or rai_reg[1] or clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if (rai_reg[i] >= WORD_COUNT) begin
qt={DATA_WIDTH {1'b0}};
end else begin
qt=mem[rai_reg[i]];
end
for (j=0;j<DATA_WIDTH;j=j+1) begin
qi[i*DATA_WIDTH+j]=qt[j];
end
end
end
assign q=qi;
endmodule
`endcelldefine
module denoise_ug0_p3 (
address0,
ce0,
q0,
we0,
d0,
address1,
ce1,
q1,
clk);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd225;
parameter AddressWidth = 32'd8;
input[AddressWidth-1:0] address0;
input ce0;
output[DataWidth-1:0] q0;
input we0;
input[DataWidth-1:0] d0;
input[AddressWidth-1:0] address1;
input ce1;
output[DataWidth-1:0] q1;
input clk;
reg[DataWidth-1:0] q0;
reg[DataWidth-1:0] q1;
wire[2 * DataWidth - 1:0] mem_q;
wire[DataWidth - 1:0] mem_q0;
wire[DataWidth - 1:0] mem_q1;
wire[1 - 1:0] mem_we;
wire[1 * DataWidth - 1:0] mem_d;
wire[1 * AddressWidth - 1:0] mem_wa;
wire[2 * AddressWidth - 1:0] mem_ra;
wire[2 - 1:0] mem_ce;
denoise_ug0_p3_core #(
.READ_PORT_COUNT( 2 ),
.WRITE_PORT_COUNT( 1 ),
.DATA_WIDTH( DataWidth ),
.ADDRESS_WIDTH( AddressWidth ),
.WORD_COUNT( AddressRange ))
core_inst (
.q( mem_q ),
.ra( mem_ra ),
.ce( mem_ce ),
.d( mem_d ),
.wa( mem_wa ),
.we( mem_we ),
.clk( clk ));
assign mem_q0 = mem_q[2 * DataWidth - 1 : 1 * DataWidth];
always @ (mem_q0) begin
q0 = mem_q0;
end
assign mem_q1 = mem_q[1 * DataWidth - 1 : 0 * DataWidth];
always @ (mem_q1) begin
q1 = mem_q1;
end
assign mem_ra = {address0, address1};
assign mem_ce = {ce0, ce1};
assign mem_we[0] = we0;
assign mem_d = {d0};
assign mem_wa = {address0};
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
`celldefine
module denoise_ug1_p0_core (q, ra, ce, clk, d, wa, we);
parameter READ_PORT_COUNT=32'd2;
parameter WRITE_PORT_COUNT=32'd1;
parameter DATA_WIDTH=32'd32;
parameter ADDRESS_WIDTH=32'd8;
parameter WORD_COUNT=32'd225;
output [READ_PORT_COUNT*DATA_WIDTH-1:0] q;
input [READ_PORT_COUNT*ADDRESS_WIDTH-1:0] ra;
input [READ_PORT_COUNT-1:0] ce;
input [WRITE_PORT_COUNT*DATA_WIDTH-1:0] d;
input [WRITE_PORT_COUNT*ADDRESS_WIDTH-1:0] wa;
input [WRITE_PORT_COUNT-1:0] we;
input clk;
integer i,j,k;
reg [DATA_WIDTH-1:0] mem [0:WORD_COUNT-1];
reg [ADDRESS_WIDTH-1:0] rat;
reg [ADDRESS_WIDTH-1:0] rai [READ_PORT_COUNT-1:0];
reg [ADDRESS_WIDTH-1:0] rai_reg [READ_PORT_COUNT-1:0];
reg [READ_PORT_COUNT*DATA_WIDTH-1:0] qi;
reg [DATA_WIDTH-1:0] qt;
reg [DATA_WIDTH-1:0] di [WRITE_PORT_COUNT-1:0];
reg [DATA_WIDTH-1:0] dt;
reg [ADDRESS_WIDTH-1:0] wat;
reg [ADDRESS_WIDTH-1:0] wai [WRITE_PORT_COUNT-1:0];
// Split input data
always @ (d) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<DATA_WIDTH;j=j+1) begin
dt[j]=d[i*DATA_WIDTH+j];
end
di[i]=dt;
end
end
// Split write addresses
always @ (wa) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
wat[j]=wa[i*ADDRESS_WIDTH+j];
end
wai[i]=wat;
end
end
// Write memory
always @ (posedge clk) begin
for (j=0;j<WRITE_PORT_COUNT;j=j+1) begin
if (we[j]) begin
mem[wai[j]] <= di[j];
end
end
end
// Split read addresses
always @ (ra) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
rat[j]=ra[i*ADDRESS_WIDTH+j];
end
rai[i]=rat;
end
end
// guide read addresses using CE
always @ (posedge clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if ( ce[i] ) begin
rai_reg[i] <= rai[i];
end
end
end
// Memory read
always @ (rai_reg[0] or rai_reg[1] or clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if (rai_reg[i] >= WORD_COUNT) begin
qt={DATA_WIDTH {1'b0}};
end else begin
qt=mem[rai_reg[i]];
end
for (j=0;j<DATA_WIDTH;j=j+1) begin
qi[i*DATA_WIDTH+j]=qt[j];
end
end
end
assign q=qi;
endmodule
`endcelldefine
module denoise_ug1_p0 (
address0,
ce0,
q0,
we0,
d0,
address1,
ce1,
q1,
clk);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd225;
parameter AddressWidth = 32'd8;
input[AddressWidth-1:0] address0;
input ce0;
output[DataWidth-1:0] q0;
input we0;
input[DataWidth-1:0] d0;
input[AddressWidth-1:0] address1;
input ce1;
output[DataWidth-1:0] q1;
input clk;
reg[DataWidth-1:0] q0;
reg[DataWidth-1:0] q1;
wire[2 * DataWidth - 1:0] mem_q;
wire[DataWidth - 1:0] mem_q0;
wire[DataWidth - 1:0] mem_q1;
wire[1 - 1:0] mem_we;
wire[1 * DataWidth - 1:0] mem_d;
wire[1 * AddressWidth - 1:0] mem_wa;
wire[2 * AddressWidth - 1:0] mem_ra;
wire[2 - 1:0] mem_ce;
denoise_ug1_p0_core #(
.READ_PORT_COUNT( 2 ),
.WRITE_PORT_COUNT( 1 ),
.DATA_WIDTH( DataWidth ),
.ADDRESS_WIDTH( AddressWidth ),
.WORD_COUNT( AddressRange ))
core_inst (
.q( mem_q ),
.ra( mem_ra ),
.ce( mem_ce ),
.d( mem_d ),
.wa( mem_wa ),
.we( mem_we ),
.clk( clk ));
assign mem_q0 = mem_q[2 * DataWidth - 1 : 1 * DataWidth];
always @ (mem_q0) begin
q0 = mem_q0;
end
assign mem_q1 = mem_q[1 * DataWidth - 1 : 0 * DataWidth];
always @ (mem_q1) begin
q1 = mem_q1;
end
assign mem_ra = {address0, address1};
assign mem_ce = {ce0, ce1};
assign mem_we[0] = we0;
assign mem_d = {d0};
assign mem_wa = {address0};
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
`celldefine
module denoise_ug1_p1_core (q, ra, ce, clk, d, wa, we);
parameter READ_PORT_COUNT=32'd1;
parameter WRITE_PORT_COUNT=32'd1;
parameter DATA_WIDTH=32'd32;
parameter ADDRESS_WIDTH=32'd8;
parameter WORD_COUNT=32'd225;
output [READ_PORT_COUNT*DATA_WIDTH-1:0] q;
input [READ_PORT_COUNT*ADDRESS_WIDTH-1:0] ra;
input [READ_PORT_COUNT-1:0] ce;
input [WRITE_PORT_COUNT*DATA_WIDTH-1:0] d;
input [WRITE_PORT_COUNT*ADDRESS_WIDTH-1:0] wa;
input [WRITE_PORT_COUNT-1:0] we;
input clk;
integer i,j,k;
reg [DATA_WIDTH-1:0] mem [0:WORD_COUNT-1];
reg [ADDRESS_WIDTH-1:0] rat;
reg [ADDRESS_WIDTH-1:0] rai [READ_PORT_COUNT-1:0];
reg [ADDRESS_WIDTH-1:0] rai_reg [READ_PORT_COUNT-1:0];
reg [READ_PORT_COUNT*DATA_WIDTH-1:0] qi;
reg [DATA_WIDTH-1:0] qt;
reg [DATA_WIDTH-1:0] di [WRITE_PORT_COUNT-1:0];
reg [DATA_WIDTH-1:0] dt;
reg [ADDRESS_WIDTH-1:0] wat;
reg [ADDRESS_WIDTH-1:0] wai [WRITE_PORT_COUNT-1:0];
// Split input data
always @ (d) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<DATA_WIDTH;j=j+1) begin
dt[j]=d[i*DATA_WIDTH+j];
end
di[i]=dt;
end
end
// Split write addresses
always @ (wa) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
wat[j]=wa[i*ADDRESS_WIDTH+j];
end
wai[i]=wat;
end
end
// Write memory
always @ (posedge clk) begin
for (j=0;j<WRITE_PORT_COUNT;j=j+1) begin
if (we[j]) begin
mem[wai[j]] <= di[j];
end
end
end
// Split read addresses
always @ (ra) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
rat[j]=ra[i*ADDRESS_WIDTH+j];
end
rai[i]=rat;
end
end
// guide read addresses using CE
always @ (posedge clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if ( ce[i] ) begin
rai_reg[i] <= rai[i];
end
end
end
// Memory read
always @ (rai_reg[0] or clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if (rai_reg[i] >= WORD_COUNT) begin
qt={DATA_WIDTH {1'b0}};
end else begin
qt=mem[rai_reg[i]];
end
for (j=0;j<DATA_WIDTH;j=j+1) begin
qi[i*DATA_WIDTH+j]=qt[j];
end
end
end
assign q=qi;
endmodule
`endcelldefine
module denoise_ug1_p1 (
address0,
ce0,
q0,
we0,
d0,
clk);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd225;
parameter AddressWidth = 32'd8;
input[AddressWidth-1:0] address0;
input ce0;
output[DataWidth-1:0] q0;
input we0;
input[DataWidth-1:0] d0;
input clk;
reg[DataWidth-1:0] q0;
wire[1 * DataWidth - 1:0] mem_q;
wire[DataWidth - 1:0] mem_q0;
wire[1 - 1:0] mem_we;
wire[1 * DataWidth - 1:0] mem_d;
wire[1 * AddressWidth - 1:0] mem_wa;
wire[1 * AddressWidth - 1:0] mem_ra;
wire[1 - 1:0] mem_ce;
denoise_ug1_p1_core #(
.READ_PORT_COUNT( 1 ),
.WRITE_PORT_COUNT( 1 ),
.DATA_WIDTH( DataWidth ),
.ADDRESS_WIDTH( AddressWidth ),
.WORD_COUNT( AddressRange ))
core_inst (
.q( mem_q ),
.ra( mem_ra ),
.ce( mem_ce ),
.d( mem_d ),
.wa( mem_wa ),
.we( mem_we ),
.clk( clk ));
assign mem_q0 = mem_q[1 * DataWidth - 1 : 0 * DataWidth];
always @ (mem_q0) begin
q0 = mem_q0;
end
assign mem_ra = {address0};
assign mem_ce = {ce0};
assign mem_we[0] = we0;
assign mem_d = {d0};
assign mem_wa = {address0};
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
`celldefine
module denoise_ug1_p2_core (q, ra, ce, clk, d, wa, we);
parameter READ_PORT_COUNT=32'd1;
parameter WRITE_PORT_COUNT=32'd1;
parameter DATA_WIDTH=32'd32;
parameter ADDRESS_WIDTH=32'd8;
parameter WORD_COUNT=32'd225;
output [READ_PORT_COUNT*DATA_WIDTH-1:0] q;
input [READ_PORT_COUNT*ADDRESS_WIDTH-1:0] ra;
input [READ_PORT_COUNT-1:0] ce;
input [WRITE_PORT_COUNT*DATA_WIDTH-1:0] d;
input [WRITE_PORT_COUNT*ADDRESS_WIDTH-1:0] wa;
input [WRITE_PORT_COUNT-1:0] we;
input clk;
integer i,j,k;
reg [DATA_WIDTH-1:0] mem [0:WORD_COUNT-1];
reg [ADDRESS_WIDTH-1:0] rat;
reg [ADDRESS_WIDTH-1:0] rai [READ_PORT_COUNT-1:0];
reg [ADDRESS_WIDTH-1:0] rai_reg [READ_PORT_COUNT-1:0];
reg [READ_PORT_COUNT*DATA_WIDTH-1:0] qi;
reg [DATA_WIDTH-1:0] qt;
reg [DATA_WIDTH-1:0] di [WRITE_PORT_COUNT-1:0];
reg [DATA_WIDTH-1:0] dt;
reg [ADDRESS_WIDTH-1:0] wat;
reg [ADDRESS_WIDTH-1:0] wai [WRITE_PORT_COUNT-1:0];
// Split input data
always @ (d) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<DATA_WIDTH;j=j+1) begin
dt[j]=d[i*DATA_WIDTH+j];
end
di[i]=dt;
end
end
// Split write addresses
always @ (wa) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
wat[j]=wa[i*ADDRESS_WIDTH+j];
end
wai[i]=wat;
end
end
// Write memory
always @ (posedge clk) begin
for (j=0;j<WRITE_PORT_COUNT;j=j+1) begin
if (we[j]) begin
mem[wai[j]] <= di[j];
end
end
end
// Split read addresses
always @ (ra) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
rat[j]=ra[i*ADDRESS_WIDTH+j];
end
rai[i]=rat;
end
end
// guide read addresses using CE
always @ (posedge clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if ( ce[i] ) begin
rai_reg[i] <= rai[i];
end
end
end
// Memory read
always @ (rai_reg[0] or clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if (rai_reg[i] >= WORD_COUNT) begin
qt={DATA_WIDTH {1'b0}};
end else begin
qt=mem[rai_reg[i]];
end
for (j=0;j<DATA_WIDTH;j=j+1) begin
qi[i*DATA_WIDTH+j]=qt[j];
end
end
end
assign q=qi;
endmodule
`endcelldefine
module denoise_ug1_p2 (
address0,
ce0,
q0,
we0,
d0,
clk);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd225;
parameter AddressWidth = 32'd8;
input[AddressWidth-1:0] address0;
input ce0;
output[DataWidth-1:0] q0;
input we0;
input[DataWidth-1:0] d0;
input clk;
reg[DataWidth-1:0] q0;
wire[1 * DataWidth - 1:0] mem_q;
wire[DataWidth - 1:0] mem_q0;
wire[1 - 1:0] mem_we;
wire[1 * DataWidth - 1:0] mem_d;
wire[1 * AddressWidth - 1:0] mem_wa;
wire[1 * AddressWidth - 1:0] mem_ra;
wire[1 - 1:0] mem_ce;
denoise_ug1_p2_core #(
.READ_PORT_COUNT( 1 ),
.WRITE_PORT_COUNT( 1 ),
.DATA_WIDTH( DataWidth ),
.ADDRESS_WIDTH( AddressWidth ),
.WORD_COUNT( AddressRange ))
core_inst (
.q( mem_q ),
.ra( mem_ra ),
.ce( mem_ce ),
.d( mem_d ),
.wa( mem_wa ),
.we( mem_we ),
.clk( clk ));
assign mem_q0 = mem_q[1 * DataWidth - 1 : 0 * DataWidth];
always @ (mem_q0) begin
q0 = mem_q0;
end
assign mem_ra = {address0};
assign mem_ce = {ce0};
assign mem_we[0] = we0;
assign mem_d = {d0};
assign mem_wa = {address0};
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
`celldefine
module denoise_ug1_p3_core (q, ra, ce, clk, d, wa, we);
parameter READ_PORT_COUNT=32'd2;
parameter WRITE_PORT_COUNT=32'd1;
parameter DATA_WIDTH=32'd32;
parameter ADDRESS_WIDTH=32'd8;
parameter WORD_COUNT=32'd225;
output [READ_PORT_COUNT*DATA_WIDTH-1:0] q;
input [READ_PORT_COUNT*ADDRESS_WIDTH-1:0] ra;
input [READ_PORT_COUNT-1:0] ce;
input [WRITE_PORT_COUNT*DATA_WIDTH-1:0] d;
input [WRITE_PORT_COUNT*ADDRESS_WIDTH-1:0] wa;
input [WRITE_PORT_COUNT-1:0] we;
input clk;
integer i,j,k;
reg [DATA_WIDTH-1:0] mem [0:WORD_COUNT-1];
reg [ADDRESS_WIDTH-1:0] rat;
reg [ADDRESS_WIDTH-1:0] rai [READ_PORT_COUNT-1:0];
reg [ADDRESS_WIDTH-1:0] rai_reg [READ_PORT_COUNT-1:0];
reg [READ_PORT_COUNT*DATA_WIDTH-1:0] qi;
reg [DATA_WIDTH-1:0] qt;
reg [DATA_WIDTH-1:0] di [WRITE_PORT_COUNT-1:0];
reg [DATA_WIDTH-1:0] dt;
reg [ADDRESS_WIDTH-1:0] wat;
reg [ADDRESS_WIDTH-1:0] wai [WRITE_PORT_COUNT-1:0];
// Split input data
always @ (d) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<DATA_WIDTH;j=j+1) begin
dt[j]=d[i*DATA_WIDTH+j];
end
di[i]=dt;
end
end
// Split write addresses
always @ (wa) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
wat[j]=wa[i*ADDRESS_WIDTH+j];
end
wai[i]=wat;
end
end
// Write memory
always @ (posedge clk) begin
for (j=0;j<WRITE_PORT_COUNT;j=j+1) begin
if (we[j]) begin
mem[wai[j]] <= di[j];
end
end
end
// Split read addresses
always @ (ra) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
rat[j]=ra[i*ADDRESS_WIDTH+j];
end
rai[i]=rat;
end
end
// guide read addresses using CE
always @ (posedge clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if ( ce[i] ) begin
rai_reg[i] <= rai[i];
end
end
end
// Memory read
always @ (rai_reg[0] or rai_reg[1] or clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if (rai_reg[i] >= WORD_COUNT) begin
qt={DATA_WIDTH {1'b0}};
end else begin
qt=mem[rai_reg[i]];
end
for (j=0;j<DATA_WIDTH;j=j+1) begin
qi[i*DATA_WIDTH+j]=qt[j];
end
end
end
assign q=qi;
endmodule
`endcelldefine
module denoise_ug1_p3 (
address0,
ce0,
q0,
we0,
d0,
address1,
ce1,
q1,
clk);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd225;
parameter AddressWidth = 32'd8;
input[AddressWidth-1:0] address0;
input ce0;
output[DataWidth-1:0] q0;
input we0;
input[DataWidth-1:0] d0;
input[AddressWidth-1:0] address1;
input ce1;
output[DataWidth-1:0] q1;
input clk;
reg[DataWidth-1:0] q0;
reg[DataWidth-1:0] q1;
wire[2 * DataWidth - 1:0] mem_q;
wire[DataWidth - 1:0] mem_q0;
wire[DataWidth - 1:0] mem_q1;
wire[1 - 1:0] mem_we;
wire[1 * DataWidth - 1:0] mem_d;
wire[1 * AddressWidth - 1:0] mem_wa;
wire[2 * AddressWidth - 1:0] mem_ra;
wire[2 - 1:0] mem_ce;
denoise_ug1_p3_core #(
.READ_PORT_COUNT( 2 ),
.WRITE_PORT_COUNT( 1 ),
.DATA_WIDTH( DataWidth ),
.ADDRESS_WIDTH( AddressWidth ),
.WORD_COUNT( AddressRange ))
core_inst (
.q( mem_q ),
.ra( mem_ra ),
.ce( mem_ce ),
.d( mem_d ),
.wa( mem_wa ),
.we( mem_we ),
.clk( clk ));
assign mem_q0 = mem_q[2 * DataWidth - 1 : 1 * DataWidth];
always @ (mem_q0) begin
q0 = mem_q0;
end
assign mem_q1 = mem_q[1 * DataWidth - 1 : 0 * DataWidth];
always @ (mem_q1) begin
q1 = mem_q1;
end
assign mem_ra = {address0, address1};
assign mem_ce = {ce0, ce1};
assign mem_we[0] = we0;
assign mem_d = {d0};
assign mem_wa = {address0};
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
`celldefine
module denoise_ug2_p0_core (q, ra, ce, clk, d, wa, we);
parameter READ_PORT_COUNT=32'd2;
parameter WRITE_PORT_COUNT=32'd1;
parameter DATA_WIDTH=32'd32;
parameter ADDRESS_WIDTH=32'd8;
parameter WORD_COUNT=32'd225;
output [READ_PORT_COUNT*DATA_WIDTH-1:0] q;
input [READ_PORT_COUNT*ADDRESS_WIDTH-1:0] ra;
input [READ_PORT_COUNT-1:0] ce;
input [WRITE_PORT_COUNT*DATA_WIDTH-1:0] d;
input [WRITE_PORT_COUNT*ADDRESS_WIDTH-1:0] wa;
input [WRITE_PORT_COUNT-1:0] we;
input clk;
integer i,j,k;
reg [DATA_WIDTH-1:0] mem [0:WORD_COUNT-1];
reg [ADDRESS_WIDTH-1:0] rat;
reg [ADDRESS_WIDTH-1:0] rai [READ_PORT_COUNT-1:0];
reg [ADDRESS_WIDTH-1:0] rai_reg [READ_PORT_COUNT-1:0];
reg [READ_PORT_COUNT*DATA_WIDTH-1:0] qi;
reg [DATA_WIDTH-1:0] qt;
reg [DATA_WIDTH-1:0] di [WRITE_PORT_COUNT-1:0];
reg [DATA_WIDTH-1:0] dt;
reg [ADDRESS_WIDTH-1:0] wat;
reg [ADDRESS_WIDTH-1:0] wai [WRITE_PORT_COUNT-1:0];
// Split input data
always @ (d) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<DATA_WIDTH;j=j+1) begin
dt[j]=d[i*DATA_WIDTH+j];
end
di[i]=dt;
end
end
// Split write addresses
always @ (wa) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
wat[j]=wa[i*ADDRESS_WIDTH+j];
end
wai[i]=wat;
end
end
// Write memory
always @ (posedge clk) begin
for (j=0;j<WRITE_PORT_COUNT;j=j+1) begin
if (we[j]) begin
mem[wai[j]] <= di[j];
end
end
end
// Split read addresses
always @ (ra) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
rat[j]=ra[i*ADDRESS_WIDTH+j];
end
rai[i]=rat;
end
end
// guide read addresses using CE
always @ (posedge clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if ( ce[i] ) begin
rai_reg[i] <= rai[i];
end
end
end
// Memory read
always @ (rai_reg[0] or rai_reg[1] or clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if (rai_reg[i] >= WORD_COUNT) begin
qt={DATA_WIDTH {1'b0}};
end else begin
qt=mem[rai_reg[i]];
end
for (j=0;j<DATA_WIDTH;j=j+1) begin
qi[i*DATA_WIDTH+j]=qt[j];
end
end
end
assign q=qi;
endmodule
`endcelldefine
module denoise_ug2_p0 (
address0,
ce0,
q0,
we0,
d0,
address1,
ce1,
q1,
clk);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd225;
parameter AddressWidth = 32'd8;
input[AddressWidth-1:0] address0;
input ce0;
output[DataWidth-1:0] q0;
input we0;
input[DataWidth-1:0] d0;
input[AddressWidth-1:0] address1;
input ce1;
output[DataWidth-1:0] q1;
input clk;
reg[DataWidth-1:0] q0;
reg[DataWidth-1:0] q1;
wire[2 * DataWidth - 1:0] mem_q;
wire[DataWidth - 1:0] mem_q0;
wire[DataWidth - 1:0] mem_q1;
wire[1 - 1:0] mem_we;
wire[1 * DataWidth - 1:0] mem_d;
wire[1 * AddressWidth - 1:0] mem_wa;
wire[2 * AddressWidth - 1:0] mem_ra;
wire[2 - 1:0] mem_ce;
denoise_ug2_p0_core #(
.READ_PORT_COUNT( 2 ),
.WRITE_PORT_COUNT( 1 ),
.DATA_WIDTH( DataWidth ),
.ADDRESS_WIDTH( AddressWidth ),
.WORD_COUNT( AddressRange ))
core_inst (
.q( mem_q ),
.ra( mem_ra ),
.ce( mem_ce ),
.d( mem_d ),
.wa( mem_wa ),
.we( mem_we ),
.clk( clk ));
assign mem_q0 = mem_q[2 * DataWidth - 1 : 1 * DataWidth];
always @ (mem_q0) begin
q0 = mem_q0;
end
assign mem_q1 = mem_q[1 * DataWidth - 1 : 0 * DataWidth];
always @ (mem_q1) begin
q1 = mem_q1;
end
assign mem_ra = {address0, address1};
assign mem_ce = {ce0, ce1};
assign mem_we[0] = we0;
assign mem_d = {d0};
assign mem_wa = {address0};
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
`celldefine
module denoise_ug2_p1_core (q, ra, ce, clk, d, wa, we);
parameter READ_PORT_COUNT=32'd1;
parameter WRITE_PORT_COUNT=32'd1;
parameter DATA_WIDTH=32'd32;
parameter ADDRESS_WIDTH=32'd8;
parameter WORD_COUNT=32'd225;
output [READ_PORT_COUNT*DATA_WIDTH-1:0] q;
input [READ_PORT_COUNT*ADDRESS_WIDTH-1:0] ra;
input [READ_PORT_COUNT-1:0] ce;
input [WRITE_PORT_COUNT*DATA_WIDTH-1:0] d;
input [WRITE_PORT_COUNT*ADDRESS_WIDTH-1:0] wa;
input [WRITE_PORT_COUNT-1:0] we;
input clk;
integer i,j,k;
reg [DATA_WIDTH-1:0] mem [0:WORD_COUNT-1];
reg [ADDRESS_WIDTH-1:0] rat;
reg [ADDRESS_WIDTH-1:0] rai [READ_PORT_COUNT-1:0];
reg [ADDRESS_WIDTH-1:0] rai_reg [READ_PORT_COUNT-1:0];
reg [READ_PORT_COUNT*DATA_WIDTH-1:0] qi;
reg [DATA_WIDTH-1:0] qt;
reg [DATA_WIDTH-1:0] di [WRITE_PORT_COUNT-1:0];
reg [DATA_WIDTH-1:0] dt;
reg [ADDRESS_WIDTH-1:0] wat;
reg [ADDRESS_WIDTH-1:0] wai [WRITE_PORT_COUNT-1:0];
// Split input data
always @ (d) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<DATA_WIDTH;j=j+1) begin
dt[j]=d[i*DATA_WIDTH+j];
end
di[i]=dt;
end
end
// Split write addresses
always @ (wa) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
wat[j]=wa[i*ADDRESS_WIDTH+j];
end
wai[i]=wat;
end
end
// Write memory
always @ (posedge clk) begin
for (j=0;j<WRITE_PORT_COUNT;j=j+1) begin
if (we[j]) begin
mem[wai[j]] <= di[j];
end
end
end
// Split read addresses
always @ (ra) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
rat[j]=ra[i*ADDRESS_WIDTH+j];
end
rai[i]=rat;
end
end
// guide read addresses using CE
always @ (posedge clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if ( ce[i] ) begin
rai_reg[i] <= rai[i];
end
end
end
// Memory read
always @ (rai_reg[0] or clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if (rai_reg[i] >= WORD_COUNT) begin
qt={DATA_WIDTH {1'b0}};
end else begin
qt=mem[rai_reg[i]];
end
for (j=0;j<DATA_WIDTH;j=j+1) begin
qi[i*DATA_WIDTH+j]=qt[j];
end
end
end
assign q=qi;
endmodule
`endcelldefine
module denoise_ug2_p1 (
address0,
ce0,
q0,
we0,
d0,
clk);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd225;
parameter AddressWidth = 32'd8;
input[AddressWidth-1:0] address0;
input ce0;
output[DataWidth-1:0] q0;
input we0;
input[DataWidth-1:0] d0;
input clk;
reg[DataWidth-1:0] q0;
wire[1 * DataWidth - 1:0] mem_q;
wire[DataWidth - 1:0] mem_q0;
wire[1 - 1:0] mem_we;
wire[1 * DataWidth - 1:0] mem_d;
wire[1 * AddressWidth - 1:0] mem_wa;
wire[1 * AddressWidth - 1:0] mem_ra;
wire[1 - 1:0] mem_ce;
denoise_ug2_p1_core #(
.READ_PORT_COUNT( 1 ),
.WRITE_PORT_COUNT( 1 ),
.DATA_WIDTH( DataWidth ),
.ADDRESS_WIDTH( AddressWidth ),
.WORD_COUNT( AddressRange ))
core_inst (
.q( mem_q ),
.ra( mem_ra ),
.ce( mem_ce ),
.d( mem_d ),
.wa( mem_wa ),
.we( mem_we ),
.clk( clk ));
assign mem_q0 = mem_q[1 * DataWidth - 1 : 0 * DataWidth];
always @ (mem_q0) begin
q0 = mem_q0;
end
assign mem_ra = {address0};
assign mem_ce = {ce0};
assign mem_we[0] = we0;
assign mem_d = {d0};
assign mem_wa = {address0};
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
`celldefine
module denoise_ug2_p2_core (q, ra, ce, clk, d, wa, we);
parameter READ_PORT_COUNT=32'd1;
parameter WRITE_PORT_COUNT=32'd1;
parameter DATA_WIDTH=32'd32;
parameter ADDRESS_WIDTH=32'd8;
parameter WORD_COUNT=32'd225;
output [READ_PORT_COUNT*DATA_WIDTH-1:0] q;
input [READ_PORT_COUNT*ADDRESS_WIDTH-1:0] ra;
input [READ_PORT_COUNT-1:0] ce;
input [WRITE_PORT_COUNT*DATA_WIDTH-1:0] d;
input [WRITE_PORT_COUNT*ADDRESS_WIDTH-1:0] wa;
input [WRITE_PORT_COUNT-1:0] we;
input clk;
integer i,j,k;
reg [DATA_WIDTH-1:0] mem [0:WORD_COUNT-1];
reg [ADDRESS_WIDTH-1:0] rat;
reg [ADDRESS_WIDTH-1:0] rai [READ_PORT_COUNT-1:0];
reg [ADDRESS_WIDTH-1:0] rai_reg [READ_PORT_COUNT-1:0];
reg [READ_PORT_COUNT*DATA_WIDTH-1:0] qi;
reg [DATA_WIDTH-1:0] qt;
reg [DATA_WIDTH-1:0] di [WRITE_PORT_COUNT-1:0];
reg [DATA_WIDTH-1:0] dt;
reg [ADDRESS_WIDTH-1:0] wat;
reg [ADDRESS_WIDTH-1:0] wai [WRITE_PORT_COUNT-1:0];
// Split input data
always @ (d) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<DATA_WIDTH;j=j+1) begin
dt[j]=d[i*DATA_WIDTH+j];
end
di[i]=dt;
end
end
// Split write addresses
always @ (wa) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
wat[j]=wa[i*ADDRESS_WIDTH+j];
end
wai[i]=wat;
end
end
// Write memory
always @ (posedge clk) begin
for (j=0;j<WRITE_PORT_COUNT;j=j+1) begin
if (we[j]) begin
mem[wai[j]] <= di[j];
end
end
end
// Split read addresses
always @ (ra) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
rat[j]=ra[i*ADDRESS_WIDTH+j];
end
rai[i]=rat;
end
end
// guide read addresses using CE
always @ (posedge clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if ( ce[i] ) begin
rai_reg[i] <= rai[i];
end
end
end
// Memory read
always @ (rai_reg[0] or clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if (rai_reg[i] >= WORD_COUNT) begin
qt={DATA_WIDTH {1'b0}};
end else begin
qt=mem[rai_reg[i]];
end
for (j=0;j<DATA_WIDTH;j=j+1) begin
qi[i*DATA_WIDTH+j]=qt[j];
end
end
end
assign q=qi;
endmodule
`endcelldefine
module denoise_ug2_p2 (
address0,
ce0,
q0,
we0,
d0,
clk);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd225;
parameter AddressWidth = 32'd8;
input[AddressWidth-1:0] address0;
input ce0;
output[DataWidth-1:0] q0;
input we0;
input[DataWidth-1:0] d0;
input clk;
reg[DataWidth-1:0] q0;
wire[1 * DataWidth - 1:0] mem_q;
wire[DataWidth - 1:0] mem_q0;
wire[1 - 1:0] mem_we;
wire[1 * DataWidth - 1:0] mem_d;
wire[1 * AddressWidth - 1:0] mem_wa;
wire[1 * AddressWidth - 1:0] mem_ra;
wire[1 - 1:0] mem_ce;
denoise_ug2_p2_core #(
.READ_PORT_COUNT( 1 ),
.WRITE_PORT_COUNT( 1 ),
.DATA_WIDTH( DataWidth ),
.ADDRESS_WIDTH( AddressWidth ),
.WORD_COUNT( AddressRange ))
core_inst (
.q( mem_q ),
.ra( mem_ra ),
.ce( mem_ce ),
.d( mem_d ),
.wa( mem_wa ),
.we( mem_we ),
.clk( clk ));
assign mem_q0 = mem_q[1 * DataWidth - 1 : 0 * DataWidth];
always @ (mem_q0) begin
q0 = mem_q0;
end
assign mem_ra = {address0};
assign mem_ce = {ce0};
assign mem_we[0] = we0;
assign mem_d = {d0};
assign mem_wa = {address0};
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
`celldefine
module denoise_ug2_p3_core (q, ra, ce, clk, d, wa, we);
parameter READ_PORT_COUNT=32'd2;
parameter WRITE_PORT_COUNT=32'd1;
parameter DATA_WIDTH=32'd32;
parameter ADDRESS_WIDTH=32'd8;
parameter WORD_COUNT=32'd225;
output [READ_PORT_COUNT*DATA_WIDTH-1:0] q;
input [READ_PORT_COUNT*ADDRESS_WIDTH-1:0] ra;
input [READ_PORT_COUNT-1:0] ce;
input [WRITE_PORT_COUNT*DATA_WIDTH-1:0] d;
input [WRITE_PORT_COUNT*ADDRESS_WIDTH-1:0] wa;
input [WRITE_PORT_COUNT-1:0] we;
input clk;
integer i,j,k;
reg [DATA_WIDTH-1:0] mem [0:WORD_COUNT-1];
reg [ADDRESS_WIDTH-1:0] rat;
reg [ADDRESS_WIDTH-1:0] rai [READ_PORT_COUNT-1:0];
reg [ADDRESS_WIDTH-1:0] rai_reg [READ_PORT_COUNT-1:0];
reg [READ_PORT_COUNT*DATA_WIDTH-1:0] qi;
reg [DATA_WIDTH-1:0] qt;
reg [DATA_WIDTH-1:0] di [WRITE_PORT_COUNT-1:0];
reg [DATA_WIDTH-1:0] dt;
reg [ADDRESS_WIDTH-1:0] wat;
reg [ADDRESS_WIDTH-1:0] wai [WRITE_PORT_COUNT-1:0];
// Split input data
always @ (d) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<DATA_WIDTH;j=j+1) begin
dt[j]=d[i*DATA_WIDTH+j];
end
di[i]=dt;
end
end
// Split write addresses
always @ (wa) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
wat[j]=wa[i*ADDRESS_WIDTH+j];
end
wai[i]=wat;
end
end
// Write memory
always @ (posedge clk) begin
for (j=0;j<WRITE_PORT_COUNT;j=j+1) begin
if (we[j]) begin
mem[wai[j]] <= di[j];
end
end
end
// Split read addresses
always @ (ra) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
rat[j]=ra[i*ADDRESS_WIDTH+j];
end
rai[i]=rat;
end
end
// guide read addresses using CE
always @ (posedge clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if ( ce[i] ) begin
rai_reg[i] <= rai[i];
end
end
end
// Memory read
always @ (rai_reg[0] or rai_reg[1] or clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if (rai_reg[i] >= WORD_COUNT) begin
qt={DATA_WIDTH {1'b0}};
end else begin
qt=mem[rai_reg[i]];
end
for (j=0;j<DATA_WIDTH;j=j+1) begin
qi[i*DATA_WIDTH+j]=qt[j];
end
end
end
assign q=qi;
endmodule
`endcelldefine
module denoise_ug2_p3 (
address0,
ce0,
q0,
we0,
d0,
address1,
ce1,
q1,
clk);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd225;
parameter AddressWidth = 32'd8;
input[AddressWidth-1:0] address0;
input ce0;
output[DataWidth-1:0] q0;
input we0;
input[DataWidth-1:0] d0;
input[AddressWidth-1:0] address1;
input ce1;
output[DataWidth-1:0] q1;
input clk;
reg[DataWidth-1:0] q0;
reg[DataWidth-1:0] q1;
wire[2 * DataWidth - 1:0] mem_q;
wire[DataWidth - 1:0] mem_q0;
wire[DataWidth - 1:0] mem_q1;
wire[1 - 1:0] mem_we;
wire[1 * DataWidth - 1:0] mem_d;
wire[1 * AddressWidth - 1:0] mem_wa;
wire[2 * AddressWidth - 1:0] mem_ra;
wire[2 - 1:0] mem_ce;
denoise_ug2_p3_core #(
.READ_PORT_COUNT( 2 ),
.WRITE_PORT_COUNT( 1 ),
.DATA_WIDTH( DataWidth ),
.ADDRESS_WIDTH( AddressWidth ),
.WORD_COUNT( AddressRange ))
core_inst (
.q( mem_q ),
.ra( mem_ra ),
.ce( mem_ce ),
.d( mem_d ),
.wa( mem_wa ),
.we( mem_we ),
.clk( clk ));
assign mem_q0 = mem_q[2 * DataWidth - 1 : 1 * DataWidth];
always @ (mem_q0) begin
q0 = mem_q0;
end
assign mem_q1 = mem_q[1 * DataWidth - 1 : 0 * DataWidth];
always @ (mem_q1) begin
q1 = mem_q1;
end
assign mem_ra = {address0, address1};
assign mem_ce = {ce0, ce1};
assign mem_we[0] = we0;
assign mem_d = {d0};
assign mem_wa = {address0};
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
`celldefine
module denoise_ug3_p0_core (q, ra, ce, clk, d, wa, we);
parameter READ_PORT_COUNT=32'd2;
parameter WRITE_PORT_COUNT=32'd1;
parameter DATA_WIDTH=32'd32;
parameter ADDRESS_WIDTH=32'd8;
parameter WORD_COUNT=32'd225;
output [READ_PORT_COUNT*DATA_WIDTH-1:0] q;
input [READ_PORT_COUNT*ADDRESS_WIDTH-1:0] ra;
input [READ_PORT_COUNT-1:0] ce;
input [WRITE_PORT_COUNT*DATA_WIDTH-1:0] d;
input [WRITE_PORT_COUNT*ADDRESS_WIDTH-1:0] wa;
input [WRITE_PORT_COUNT-1:0] we;
input clk;
integer i,j,k;
reg [DATA_WIDTH-1:0] mem [0:WORD_COUNT-1];
reg [ADDRESS_WIDTH-1:0] rat;
reg [ADDRESS_WIDTH-1:0] rai [READ_PORT_COUNT-1:0];
reg [ADDRESS_WIDTH-1:0] rai_reg [READ_PORT_COUNT-1:0];
reg [READ_PORT_COUNT*DATA_WIDTH-1:0] qi;
reg [DATA_WIDTH-1:0] qt;
reg [DATA_WIDTH-1:0] di [WRITE_PORT_COUNT-1:0];
reg [DATA_WIDTH-1:0] dt;
reg [ADDRESS_WIDTH-1:0] wat;
reg [ADDRESS_WIDTH-1:0] wai [WRITE_PORT_COUNT-1:0];
// Split input data
always @ (d) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<DATA_WIDTH;j=j+1) begin
dt[j]=d[i*DATA_WIDTH+j];
end
di[i]=dt;
end
end
// Split write addresses
always @ (wa) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
wat[j]=wa[i*ADDRESS_WIDTH+j];
end
wai[i]=wat;
end
end
// Write memory
always @ (posedge clk) begin
for (j=0;j<WRITE_PORT_COUNT;j=j+1) begin
if (we[j]) begin
mem[wai[j]] <= di[j];
end
end
end
// Split read addresses
always @ (ra) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
rat[j]=ra[i*ADDRESS_WIDTH+j];
end
rai[i]=rat;
end
end
// guide read addresses using CE
always @ (posedge clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if ( ce[i] ) begin
rai_reg[i] <= rai[i];
end
end
end
// Memory read
always @ (rai_reg[0] or rai_reg[1] or clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if (rai_reg[i] >= WORD_COUNT) begin
qt={DATA_WIDTH {1'b0}};
end else begin
qt=mem[rai_reg[i]];
end
for (j=0;j<DATA_WIDTH;j=j+1) begin
qi[i*DATA_WIDTH+j]=qt[j];
end
end
end
assign q=qi;
endmodule
`endcelldefine
module denoise_ug3_p0 (
address0,
ce0,
q0,
we0,
d0,
address1,
ce1,
q1,
clk);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd225;
parameter AddressWidth = 32'd8;
input[AddressWidth-1:0] address0;
input ce0;
output[DataWidth-1:0] q0;
input we0;
input[DataWidth-1:0] d0;
input[AddressWidth-1:0] address1;
input ce1;
output[DataWidth-1:0] q1;
input clk;
reg[DataWidth-1:0] q0;
reg[DataWidth-1:0] q1;
wire[2 * DataWidth - 1:0] mem_q;
wire[DataWidth - 1:0] mem_q0;
wire[DataWidth - 1:0] mem_q1;
wire[1 - 1:0] mem_we;
wire[1 * DataWidth - 1:0] mem_d;
wire[1 * AddressWidth - 1:0] mem_wa;
wire[2 * AddressWidth - 1:0] mem_ra;
wire[2 - 1:0] mem_ce;
denoise_ug3_p0_core #(
.READ_PORT_COUNT( 2 ),
.WRITE_PORT_COUNT( 1 ),
.DATA_WIDTH( DataWidth ),
.ADDRESS_WIDTH( AddressWidth ),
.WORD_COUNT( AddressRange ))
core_inst (
.q( mem_q ),
.ra( mem_ra ),
.ce( mem_ce ),
.d( mem_d ),
.wa( mem_wa ),
.we( mem_we ),
.clk( clk ));
assign mem_q0 = mem_q[2 * DataWidth - 1 : 1 * DataWidth];
always @ (mem_q0) begin
q0 = mem_q0;
end
assign mem_q1 = mem_q[1 * DataWidth - 1 : 0 * DataWidth];
always @ (mem_q1) begin
q1 = mem_q1;
end
assign mem_ra = {address0, address1};
assign mem_ce = {ce0, ce1};
assign mem_we[0] = we0;
assign mem_d = {d0};
assign mem_wa = {address0};
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
`celldefine
module denoise_ug3_p1_core (q, ra, ce, clk, d, wa, we);
parameter READ_PORT_COUNT=32'd1;
parameter WRITE_PORT_COUNT=32'd1;
parameter DATA_WIDTH=32'd32;
parameter ADDRESS_WIDTH=32'd8;
parameter WORD_COUNT=32'd225;
output [READ_PORT_COUNT*DATA_WIDTH-1:0] q;
input [READ_PORT_COUNT*ADDRESS_WIDTH-1:0] ra;
input [READ_PORT_COUNT-1:0] ce;
input [WRITE_PORT_COUNT*DATA_WIDTH-1:0] d;
input [WRITE_PORT_COUNT*ADDRESS_WIDTH-1:0] wa;
input [WRITE_PORT_COUNT-1:0] we;
input clk;
integer i,j,k;
reg [DATA_WIDTH-1:0] mem [0:WORD_COUNT-1];
reg [ADDRESS_WIDTH-1:0] rat;
reg [ADDRESS_WIDTH-1:0] rai [READ_PORT_COUNT-1:0];
reg [ADDRESS_WIDTH-1:0] rai_reg [READ_PORT_COUNT-1:0];
reg [READ_PORT_COUNT*DATA_WIDTH-1:0] qi;
reg [DATA_WIDTH-1:0] qt;
reg [DATA_WIDTH-1:0] di [WRITE_PORT_COUNT-1:0];
reg [DATA_WIDTH-1:0] dt;
reg [ADDRESS_WIDTH-1:0] wat;
reg [ADDRESS_WIDTH-1:0] wai [WRITE_PORT_COUNT-1:0];
// Split input data
always @ (d) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<DATA_WIDTH;j=j+1) begin
dt[j]=d[i*DATA_WIDTH+j];
end
di[i]=dt;
end
end
// Split write addresses
always @ (wa) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
wat[j]=wa[i*ADDRESS_WIDTH+j];
end
wai[i]=wat;
end
end
// Write memory
always @ (posedge clk) begin
for (j=0;j<WRITE_PORT_COUNT;j=j+1) begin
if (we[j]) begin
mem[wai[j]] <= di[j];
end
end
end
// Split read addresses
always @ (ra) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
rat[j]=ra[i*ADDRESS_WIDTH+j];
end
rai[i]=rat;
end
end
// guide read addresses using CE
always @ (posedge clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if ( ce[i] ) begin
rai_reg[i] <= rai[i];
end
end
end
// Memory read
always @ (rai_reg[0] or clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if (rai_reg[i] >= WORD_COUNT) begin
qt={DATA_WIDTH {1'b0}};
end else begin
qt=mem[rai_reg[i]];
end
for (j=0;j<DATA_WIDTH;j=j+1) begin
qi[i*DATA_WIDTH+j]=qt[j];
end
end
end
assign q=qi;
endmodule
`endcelldefine
module denoise_ug3_p1 (
address0,
ce0,
q0,
we0,
d0,
clk);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd225;
parameter AddressWidth = 32'd8;
input[AddressWidth-1:0] address0;
input ce0;
output[DataWidth-1:0] q0;
input we0;
input[DataWidth-1:0] d0;
input clk;
reg[DataWidth-1:0] q0;
wire[1 * DataWidth - 1:0] mem_q;
wire[DataWidth - 1:0] mem_q0;
wire[1 - 1:0] mem_we;
wire[1 * DataWidth - 1:0] mem_d;
wire[1 * AddressWidth - 1:0] mem_wa;
wire[1 * AddressWidth - 1:0] mem_ra;
wire[1 - 1:0] mem_ce;
denoise_ug3_p1_core #(
.READ_PORT_COUNT( 1 ),
.WRITE_PORT_COUNT( 1 ),
.DATA_WIDTH( DataWidth ),
.ADDRESS_WIDTH( AddressWidth ),
.WORD_COUNT( AddressRange ))
core_inst (
.q( mem_q ),
.ra( mem_ra ),
.ce( mem_ce ),
.d( mem_d ),
.wa( mem_wa ),
.we( mem_we ),
.clk( clk ));
assign mem_q0 = mem_q[1 * DataWidth - 1 : 0 * DataWidth];
always @ (mem_q0) begin
q0 = mem_q0;
end
assign mem_ra = {address0};
assign mem_ce = {ce0};
assign mem_we[0] = we0;
assign mem_d = {d0};
assign mem_wa = {address0};
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
`celldefine
module denoise_ug3_p2_core (q, ra, ce, clk, d, wa, we);
parameter READ_PORT_COUNT=32'd1;
parameter WRITE_PORT_COUNT=32'd1;
parameter DATA_WIDTH=32'd32;
parameter ADDRESS_WIDTH=32'd8;
parameter WORD_COUNT=32'd225;
output [READ_PORT_COUNT*DATA_WIDTH-1:0] q;
input [READ_PORT_COUNT*ADDRESS_WIDTH-1:0] ra;
input [READ_PORT_COUNT-1:0] ce;
input [WRITE_PORT_COUNT*DATA_WIDTH-1:0] d;
input [WRITE_PORT_COUNT*ADDRESS_WIDTH-1:0] wa;
input [WRITE_PORT_COUNT-1:0] we;
input clk;
integer i,j,k;
reg [DATA_WIDTH-1:0] mem [0:WORD_COUNT-1];
reg [ADDRESS_WIDTH-1:0] rat;
reg [ADDRESS_WIDTH-1:0] rai [READ_PORT_COUNT-1:0];
reg [ADDRESS_WIDTH-1:0] rai_reg [READ_PORT_COUNT-1:0];
reg [READ_PORT_COUNT*DATA_WIDTH-1:0] qi;
reg [DATA_WIDTH-1:0] qt;
reg [DATA_WIDTH-1:0] di [WRITE_PORT_COUNT-1:0];
reg [DATA_WIDTH-1:0] dt;
reg [ADDRESS_WIDTH-1:0] wat;
reg [ADDRESS_WIDTH-1:0] wai [WRITE_PORT_COUNT-1:0];
// Split input data
always @ (d) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<DATA_WIDTH;j=j+1) begin
dt[j]=d[i*DATA_WIDTH+j];
end
di[i]=dt;
end
end
// Split write addresses
always @ (wa) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
wat[j]=wa[i*ADDRESS_WIDTH+j];
end
wai[i]=wat;
end
end
// Write memory
always @ (posedge clk) begin
for (j=0;j<WRITE_PORT_COUNT;j=j+1) begin
if (we[j]) begin
mem[wai[j]] <= di[j];
end
end
end
// Split read addresses
always @ (ra) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
rat[j]=ra[i*ADDRESS_WIDTH+j];
end
rai[i]=rat;
end
end
// guide read addresses using CE
always @ (posedge clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if ( ce[i] ) begin
rai_reg[i] <= rai[i];
end
end
end
// Memory read
always @ (rai_reg[0] or clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if (rai_reg[i] >= WORD_COUNT) begin
qt={DATA_WIDTH {1'b0}};
end else begin
qt=mem[rai_reg[i]];
end
for (j=0;j<DATA_WIDTH;j=j+1) begin
qi[i*DATA_WIDTH+j]=qt[j];
end
end
end
assign q=qi;
endmodule
`endcelldefine
module denoise_ug3_p2 (
address0,
ce0,
q0,
we0,
d0,
clk);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd225;
parameter AddressWidth = 32'd8;
input[AddressWidth-1:0] address0;
input ce0;
output[DataWidth-1:0] q0;
input we0;
input[DataWidth-1:0] d0;
input clk;
reg[DataWidth-1:0] q0;
wire[1 * DataWidth - 1:0] mem_q;
wire[DataWidth - 1:0] mem_q0;
wire[1 - 1:0] mem_we;
wire[1 * DataWidth - 1:0] mem_d;
wire[1 * AddressWidth - 1:0] mem_wa;
wire[1 * AddressWidth - 1:0] mem_ra;
wire[1 - 1:0] mem_ce;
denoise_ug3_p2_core #(
.READ_PORT_COUNT( 1 ),
.WRITE_PORT_COUNT( 1 ),
.DATA_WIDTH( DataWidth ),
.ADDRESS_WIDTH( AddressWidth ),
.WORD_COUNT( AddressRange ))
core_inst (
.q( mem_q ),
.ra( mem_ra ),
.ce( mem_ce ),
.d( mem_d ),
.wa( mem_wa ),
.we( mem_we ),
.clk( clk ));
assign mem_q0 = mem_q[1 * DataWidth - 1 : 0 * DataWidth];
always @ (mem_q0) begin
q0 = mem_q0;
end
assign mem_ra = {address0};
assign mem_ce = {ce0};
assign mem_we[0] = we0;
assign mem_d = {d0};
assign mem_wa = {address0};
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
`celldefine
module denoise_ug3_p3_core (q, ra, ce, clk, d, wa, we);
parameter READ_PORT_COUNT=32'd2;
parameter WRITE_PORT_COUNT=32'd1;
parameter DATA_WIDTH=32'd32;
parameter ADDRESS_WIDTH=32'd8;
parameter WORD_COUNT=32'd225;
output [READ_PORT_COUNT*DATA_WIDTH-1:0] q;
input [READ_PORT_COUNT*ADDRESS_WIDTH-1:0] ra;
input [READ_PORT_COUNT-1:0] ce;
input [WRITE_PORT_COUNT*DATA_WIDTH-1:0] d;
input [WRITE_PORT_COUNT*ADDRESS_WIDTH-1:0] wa;
input [WRITE_PORT_COUNT-1:0] we;
input clk;
integer i,j,k;
reg [DATA_WIDTH-1:0] mem [0:WORD_COUNT-1];
reg [ADDRESS_WIDTH-1:0] rat;
reg [ADDRESS_WIDTH-1:0] rai [READ_PORT_COUNT-1:0];
reg [ADDRESS_WIDTH-1:0] rai_reg [READ_PORT_COUNT-1:0];
reg [READ_PORT_COUNT*DATA_WIDTH-1:0] qi;
reg [DATA_WIDTH-1:0] qt;
reg [DATA_WIDTH-1:0] di [WRITE_PORT_COUNT-1:0];
reg [DATA_WIDTH-1:0] dt;
reg [ADDRESS_WIDTH-1:0] wat;
reg [ADDRESS_WIDTH-1:0] wai [WRITE_PORT_COUNT-1:0];
// Split input data
always @ (d) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<DATA_WIDTH;j=j+1) begin
dt[j]=d[i*DATA_WIDTH+j];
end
di[i]=dt;
end
end
// Split write addresses
always @ (wa) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
wat[j]=wa[i*ADDRESS_WIDTH+j];
end
wai[i]=wat;
end
end
// Write memory
always @ (posedge clk) begin
for (j=0;j<WRITE_PORT_COUNT;j=j+1) begin
if (we[j]) begin
mem[wai[j]] <= di[j];
end
end
end
// Split read addresses
always @ (ra) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
rat[j]=ra[i*ADDRESS_WIDTH+j];
end
rai[i]=rat;
end
end
// guide read addresses using CE
always @ (posedge clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if ( ce[i] ) begin
rai_reg[i] <= rai[i];
end
end
end
// Memory read
always @ (rai_reg[0] or rai_reg[1] or clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if (rai_reg[i] >= WORD_COUNT) begin
qt={DATA_WIDTH {1'b0}};
end else begin
qt=mem[rai_reg[i]];
end
for (j=0;j<DATA_WIDTH;j=j+1) begin
qi[i*DATA_WIDTH+j]=qt[j];
end
end
end
assign q=qi;
endmodule
`endcelldefine
module denoise_ug3_p3 (
address0,
ce0,
q0,
we0,
d0,
address1,
ce1,
q1,
clk);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd225;
parameter AddressWidth = 32'd8;
input[AddressWidth-1:0] address0;
input ce0;
output[DataWidth-1:0] q0;
input we0;
input[DataWidth-1:0] d0;
input[AddressWidth-1:0] address1;
input ce1;
output[DataWidth-1:0] q1;
input clk;
reg[DataWidth-1:0] q0;
reg[DataWidth-1:0] q1;
wire[2 * DataWidth - 1:0] mem_q;
wire[DataWidth - 1:0] mem_q0;
wire[DataWidth - 1:0] mem_q1;
wire[1 - 1:0] mem_we;
wire[1 * DataWidth - 1:0] mem_d;
wire[1 * AddressWidth - 1:0] mem_wa;
wire[2 * AddressWidth - 1:0] mem_ra;
wire[2 - 1:0] mem_ce;
denoise_ug3_p3_core #(
.READ_PORT_COUNT( 2 ),
.WRITE_PORT_COUNT( 1 ),
.DATA_WIDTH( DataWidth ),
.ADDRESS_WIDTH( AddressWidth ),
.WORD_COUNT( AddressRange ))
core_inst (
.q( mem_q ),
.ra( mem_ra ),
.ce( mem_ce ),
.d( mem_d ),
.wa( mem_wa ),
.we( mem_we ),
.clk( clk ));
assign mem_q0 = mem_q[2 * DataWidth - 1 : 1 * DataWidth];
always @ (mem_q0) begin
q0 = mem_q0;
end
assign mem_q1 = mem_q[1 * DataWidth - 1 : 0 * DataWidth];
always @ (mem_q1) begin
q1 = mem_q1;
end
assign mem_ra = {address0, address1};
assign mem_ce = {ce0, ce1};
assign mem_we[0] = we0;
assign mem_d = {d0};
assign mem_wa = {address0};
endmodule
|
// ==============================================================
// RTL generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ===========================================================
`timescale 1 ns / 1 ps
module fFetch_array (
ap_clk,
ap_rst,
ap_start,
ap_done,
ap_idle,
bus_r_req_din,
bus_r_req_full_n,
bus_r_req_write,
bus_r_rsp_dout,
bus_r_rsp_empty_n,
bus_r_rsp_read,
bus_r_address,
bus_r_datain,
bus_r_dataout,
bus_r_size,
data_p0_address0,
data_p0_ce0,
data_p0_we0,
data_p0_d0,
data_p1_address0,
data_p1_ce0,
data_p1_we0,
data_p1_d0,
data_p2_address0,
data_p2_ce0,
data_p2_we0,
data_p2_d0,
data_p3_address0,
data_p3_ce0,
data_p3_we0,
data_p3_d0
);
input ap_clk;
input ap_rst;
input ap_start;
output ap_done;
output ap_idle;
output bus_r_req_din;
input bus_r_req_full_n;
output bus_r_req_write;
input bus_r_rsp_dout;
input bus_r_rsp_empty_n;
output bus_r_rsp_read;
output [31:0] bus_r_address;
input [127:0] bus_r_datain;
output [127:0] bus_r_dataout;
output [31:0] bus_r_size;
output [7:0] data_p0_address0;
output data_p0_ce0;
output data_p0_we0;
output [31:0] data_p0_d0;
output [7:0] data_p1_address0;
output data_p1_ce0;
output data_p1_we0;
output [31:0] data_p1_d0;
output [7:0] data_p2_address0;
output data_p2_ce0;
output data_p2_we0;
output [31:0] data_p2_d0;
output [7:0] data_p3_address0;
output data_p3_ce0;
output data_p3_we0;
output [31:0] data_p3_d0;
reg ap_done;
reg ap_idle;
reg bus_r_req_write;
reg bus_r_rsp_read;
reg data_p0_ce0;
reg data_p0_we0;
reg data_p1_ce0;
reg data_p1_we0;
reg data_p2_ce0;
reg data_p2_we0;
reg data_p3_ce0;
reg data_p3_we0;
reg [1:0] ap_CS_fsm;
reg [31:0] fIndex;
reg [7:0] indvar_flatten_reg_128;
reg [5:0] i_reg_139;
reg [2:0] indvar_reg_150;
wire [0:0] exitcond_fu_162_p2;
reg [0:0] exitcond_reg_319;
reg ap_reg_ppiten_pp0_it0;
reg ap_sig_bdd_76;
reg ap_sig_bdd_81;
reg ap_reg_ppiten_pp0_it1;
reg ap_reg_ppiten_pp0_it2;
reg [0:0] ap_reg_ppstg_exitcond_reg_319_pp0_it1;
reg [7:0] indvar_next_reg_323;
wire [5:0] i_mid_fu_194_p3;
reg [5:0] i_mid_reg_328;
reg [7:0] data_p0_addr_reg_338;
reg [7:0] ap_reg_ppstg_data_p0_addr_reg_338_pp0_it1;
reg [2:0] indvar_next1_reg_343;
reg [31:0] Result1_reg_348;
reg [31:0] Result3_reg_353;
reg [31:0] Result2_reg_358;
reg [31:0] Result_reg_363;
reg [7:0] indvar_flatten_phi_fu_132_p4;
reg [5:0] i_phi_fu_143_p4;
reg [2:0] indvar_phi_fu_154_p4;
wire [31:0] data_p0_addr1_cast_fu_300_p1;
wire [63:0] tmp_fu_212_p1;
wire [7:0] exitcond_fu_162_p1;
wire [2:0] exitcond1_fu_180_p1;
wire [0:0] exitcond1_fu_180_p2;
wire [5:0] indvar_next6_dup_fu_174_p2;
wire [2:0] indvar_mid_fu_186_p3;
wire [3:0] indvar_cast_fu_202_p1;
wire [3:0] j_fu_206_p2;
wire [7:0] tmp4_trn_cast_fu_234_p1;
wire [7:0] p_shl_fu_238_p2;
wire [7:0] data_p0_addr_cast_fu_244_p2;
wire [7:0] tmp8_trn_cast_fu_230_p1;
reg [1:0] ap_NS_fsm;
parameter ap_const_logic_1 = 1'b1;
parameter ap_const_logic_0 = 1'b0;
parameter ap_ST_st0_fsm_0 = 2'b00;
parameter ap_ST_st1_fsm_1 = 2'b01;
parameter ap_ST_pp0_stg0_fsm_2 = 2'b10;
parameter ap_ST_st5_fsm_3 = 2'b11;
parameter ap_const_lv32_0 = 32'b00000000000000000000000000000000;
parameter ap_const_lv1_0 = 1'b0;
parameter ap_const_lv8_0 = 8'b00000000;
parameter ap_const_lv6_0 = 6'b000000;
parameter ap_const_lv3_0 = 3'b000;
parameter ap_const_lv8_F0 = 8'b11110000;
parameter ap_const_lv8_1 = 8'b00000001;
parameter ap_const_lv6_1 = 6'b000001;
parameter ap_const_lv3_4 = 3'b100;
parameter ap_const_lv4_2 = 4'b0010;
parameter ap_const_lv32_1 = 32'b00000000000000000000000000000001;
parameter ap_const_lv8_4 = 8'b00000100;
parameter ap_const_lv3_1 = 3'b001;
parameter ap_const_lv32_20 = 32'b00000000000000000000000000100000;
parameter ap_const_lv32_3F = 32'b00000000000000000000000000111111;
parameter ap_const_lv32_40 = 32'b00000000000000000000000001000000;
parameter ap_const_lv32_5F = 32'b00000000000000000000000001011111;
parameter ap_const_lv32_60 = 32'b00000000000000000000000001100000;
parameter ap_const_lv32_7F = 32'b00000000000000000000000001111111;
parameter ap_const_lv128_lc_1 = 128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_true = 1'b1;
/// ap_CS_fsm assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_CS_fsm
if (ap_rst == 1'b1) begin
ap_CS_fsm <= ap_ST_st0_fsm_0;
end else begin
ap_CS_fsm <= ap_NS_fsm;
end
end
/// ap_reg_ppiten_pp0_it0 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it0
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it0 <= ap_const_logic_0;
end else begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & ~(((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ap_sig_bdd_76) | (ap_sig_bdd_81 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1))) & ~(exitcond_fu_162_p2 == ap_const_lv1_0))) begin
ap_reg_ppiten_pp0_it0 <= ap_const_logic_0;
end else if ((ap_ST_st1_fsm_1 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it0 <= ap_const_logic_1;
end
end
end
/// ap_reg_ppiten_pp0_it1 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it1
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it1 <= ap_const_logic_0;
end else begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (exitcond_fu_162_p2 == ap_const_lv1_0) & ~(((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ap_sig_bdd_76) | (ap_sig_bdd_81 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1))))) begin
ap_reg_ppiten_pp0_it1 <= ap_const_logic_1;
end else if (((ap_ST_st1_fsm_1 == ap_CS_fsm) | ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & ~(((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ap_sig_bdd_76) | (ap_sig_bdd_81 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1))) & ~(exitcond_fu_162_p2 == ap_const_lv1_0)))) begin
ap_reg_ppiten_pp0_it1 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp0_it2 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it2
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it2 <= ap_const_logic_0;
end else begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & ~(((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ap_sig_bdd_76) | (ap_sig_bdd_81 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1))))) begin
ap_reg_ppiten_pp0_it2 <= ap_reg_ppiten_pp0_it1;
end else if ((ap_ST_st1_fsm_1 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it2 <= ap_const_logic_0;
end
end
end
/// fIndex assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_fIndex
if (ap_rst == 1'b1) begin
fIndex <= ap_const_lv32_0;
end else begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_fu_162_p2 == ap_const_lv1_0) & ~(((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ap_sig_bdd_76) | (ap_sig_bdd_81 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1))))) begin
fIndex <= (fIndex + ap_const_lv32_1);
end
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (exitcond_reg_319 == ap_const_lv1_0) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & ~(((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ap_sig_bdd_76) | (ap_sig_bdd_81 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1))))) begin
Result1_reg_348 <= bus_r_datain[31:0];
end
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (exitcond_reg_319 == ap_const_lv1_0) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & ~(((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ap_sig_bdd_76) | (ap_sig_bdd_81 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1))))) begin
Result2_reg_358 <= {{bus_r_datain[ap_const_lv32_5F : ap_const_lv32_40]}};
end
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (exitcond_reg_319 == ap_const_lv1_0) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & ~(((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ap_sig_bdd_76) | (ap_sig_bdd_81 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1))))) begin
Result3_reg_353 <= {{bus_r_datain[ap_const_lv32_3F : ap_const_lv32_20]}};
end
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (exitcond_reg_319 == ap_const_lv1_0) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & ~(((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ap_sig_bdd_76) | (ap_sig_bdd_81 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1))))) begin
Result_reg_363 <= {{bus_r_datain[ap_const_lv32_7F : ap_const_lv32_60]}};
end
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & ~(((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ap_sig_bdd_76) | (ap_sig_bdd_81 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1))))) begin
ap_reg_ppstg_data_p0_addr_reg_338_pp0_it1 <= data_p0_addr_reg_338;
end
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & ~(((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ap_sig_bdd_76) | (ap_sig_bdd_81 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1))))) begin
ap_reg_ppstg_exitcond_reg_319_pp0_it1 <= exitcond_reg_319;
end
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_fu_162_p2 == ap_const_lv1_0) & ~(((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ap_sig_bdd_76) | (ap_sig_bdd_81 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1))))) begin
data_p0_addr_reg_338 <= (data_p0_addr_cast_fu_244_p2 + tmp8_trn_cast_fu_230_p1);
end
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ~(((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ap_sig_bdd_76) | (ap_sig_bdd_81 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1))))) begin
exitcond_reg_319 <= (indvar_flatten_phi_fu_132_p4 == exitcond_fu_162_p1? 1'b1: 1'b0);
end
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_fu_162_p2 == ap_const_lv1_0) & ~(((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ap_sig_bdd_76) | (ap_sig_bdd_81 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1))))) begin
if (exitcond1_fu_180_p2) begin
i_mid_reg_328 <= indvar_next6_dup_fu_174_p2;
end else begin
i_mid_reg_328 <= i_phi_fu_143_p4;
end
end
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (exitcond_reg_319 == ap_const_lv1_0) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & ~(((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ap_sig_bdd_76) | (ap_sig_bdd_81 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1))))) begin
i_reg_139 <= i_mid_reg_328;
end else if ((ap_ST_st1_fsm_1 == ap_CS_fsm)) begin
i_reg_139 <= ap_const_lv6_0;
end
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (exitcond_reg_319 == ap_const_lv1_0) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & ~(((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ap_sig_bdd_76) | (ap_sig_bdd_81 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1))))) begin
indvar_flatten_reg_128 <= indvar_next_reg_323;
end else if ((ap_ST_st1_fsm_1 == ap_CS_fsm)) begin
indvar_flatten_reg_128 <= ap_const_lv8_0;
end
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_fu_162_p2 == ap_const_lv1_0) & ~(((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ap_sig_bdd_76) | (ap_sig_bdd_81 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1))))) begin
indvar_next1_reg_343 <= (indvar_mid_fu_186_p3 + ap_const_lv3_1);
end
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ~(((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ap_sig_bdd_76) | (ap_sig_bdd_81 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1))))) begin
indvar_next_reg_323 <= (indvar_flatten_phi_fu_132_p4 + ap_const_lv8_1);
end
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (exitcond_reg_319 == ap_const_lv1_0) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & ~(((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ap_sig_bdd_76) | (ap_sig_bdd_81 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1))))) begin
indvar_reg_150 <= indvar_next1_reg_343;
end else if ((ap_ST_st1_fsm_1 == ap_CS_fsm)) begin
indvar_reg_150 <= ap_const_lv3_0;
end
end
/// ap_NS_fsm assign process. ///
always @ (ap_start or ap_CS_fsm or exitcond_fu_162_p2 or ap_reg_ppiten_pp0_it0 or ap_sig_bdd_76 or ap_sig_bdd_81 or ap_reg_ppiten_pp0_it1 or ap_reg_ppiten_pp0_it2)
begin
if ((((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it2) & ~(((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ap_sig_bdd_76) | (ap_sig_bdd_81 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1))) & ~(ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ~(((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ap_sig_bdd_76) | (ap_sig_bdd_81 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1))) & ~(exitcond_fu_162_p2 == ap_const_lv1_0) & ~(ap_const_logic_1 == ap_reg_ppiten_pp0_it1)))) begin
ap_NS_fsm = ap_ST_st5_fsm_3;
end else if ((~(ap_const_logic_1 == ap_start) & (ap_ST_st5_fsm_3 == ap_CS_fsm))) begin
ap_NS_fsm = ap_ST_st0_fsm_0;
end else if ((ap_ST_st1_fsm_1 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_pp0_stg0_fsm_2;
end else if ((((ap_ST_st0_fsm_0 == ap_CS_fsm) & (ap_const_logic_1 == ap_start)) | ((ap_const_logic_1 == ap_start) & (ap_ST_st5_fsm_3 == ap_CS_fsm)))) begin
ap_NS_fsm = ap_ST_st1_fsm_1;
end else begin
ap_NS_fsm = ap_CS_fsm;
end
end
/// ap_done assign process. ///
always @ (ap_CS_fsm)
begin
if (((ap_ST_st0_fsm_0 == ap_CS_fsm) | (ap_ST_st5_fsm_3 == ap_CS_fsm))) begin
ap_done = ap_const_logic_1;
end else begin
ap_done = ap_const_logic_0;
end
end
/// ap_idle assign process. ///
always @ (ap_CS_fsm)
begin
if ((ap_ST_st0_fsm_0 == ap_CS_fsm)) begin
ap_idle = ap_const_logic_1;
end else begin
ap_idle = ap_const_logic_0;
end
end
/// bus_r_req_write assign process. ///
always @ (ap_CS_fsm or exitcond_fu_162_p2 or ap_reg_ppiten_pp0_it0 or ap_sig_bdd_76 or ap_sig_bdd_81 or ap_reg_ppiten_pp0_it1)
begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_fu_162_p2 == ap_const_lv1_0) & ~(((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ap_sig_bdd_76) | (ap_sig_bdd_81 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1))))) begin
bus_r_req_write = ap_const_logic_1;
end else begin
bus_r_req_write = ap_const_logic_0;
end
end
/// bus_r_rsp_read assign process. ///
always @ (ap_CS_fsm or exitcond_reg_319 or ap_reg_ppiten_pp0_it0 or ap_sig_bdd_76 or ap_sig_bdd_81 or ap_reg_ppiten_pp0_it1)
begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (exitcond_reg_319 == ap_const_lv1_0) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & ~(((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ap_sig_bdd_76) | (ap_sig_bdd_81 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1))))) begin
bus_r_rsp_read = ap_const_logic_1;
end else begin
bus_r_rsp_read = ap_const_logic_0;
end
end
/// data_p0_ce0 assign process. ///
always @ (ap_CS_fsm or ap_reg_ppiten_pp0_it0 or ap_sig_bdd_76 or ap_sig_bdd_81 or ap_reg_ppiten_pp0_it1 or ap_reg_ppiten_pp0_it2 or ap_reg_ppstg_exitcond_reg_319_pp0_it1)
begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it2) & ~(((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ap_sig_bdd_76) | (ap_sig_bdd_81 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1))) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_319_pp0_it1))) begin
data_p0_ce0 = ap_const_logic_1;
end else begin
data_p0_ce0 = ap_const_logic_0;
end
end
/// data_p0_we0 assign process. ///
always @ (ap_CS_fsm or ap_reg_ppiten_pp0_it0 or ap_sig_bdd_76 or ap_sig_bdd_81 or ap_reg_ppiten_pp0_it1 or ap_reg_ppiten_pp0_it2 or ap_reg_ppstg_exitcond_reg_319_pp0_it1)
begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it2) & ~(((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ap_sig_bdd_76) | (ap_sig_bdd_81 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1))) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_319_pp0_it1))) begin
data_p0_we0 = ap_const_logic_1;
end else begin
data_p0_we0 = ap_const_logic_0;
end
end
/// data_p1_ce0 assign process. ///
always @ (ap_CS_fsm or ap_reg_ppiten_pp0_it0 or ap_sig_bdd_76 or ap_sig_bdd_81 or ap_reg_ppiten_pp0_it1 or ap_reg_ppiten_pp0_it2 or ap_reg_ppstg_exitcond_reg_319_pp0_it1)
begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it2) & ~(((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ap_sig_bdd_76) | (ap_sig_bdd_81 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1))) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_319_pp0_it1))) begin
data_p1_ce0 = ap_const_logic_1;
end else begin
data_p1_ce0 = ap_const_logic_0;
end
end
/// data_p1_we0 assign process. ///
always @ (ap_CS_fsm or ap_reg_ppiten_pp0_it0 or ap_sig_bdd_76 or ap_sig_bdd_81 or ap_reg_ppiten_pp0_it1 or ap_reg_ppiten_pp0_it2 or ap_reg_ppstg_exitcond_reg_319_pp0_it1)
begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it2) & ~(((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ap_sig_bdd_76) | (ap_sig_bdd_81 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1))) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_319_pp0_it1))) begin
data_p1_we0 = ap_const_logic_1;
end else begin
data_p1_we0 = ap_const_logic_0;
end
end
/// data_p2_ce0 assign process. ///
always @ (ap_CS_fsm or ap_reg_ppiten_pp0_it0 or ap_sig_bdd_76 or ap_sig_bdd_81 or ap_reg_ppiten_pp0_it1 or ap_reg_ppiten_pp0_it2 or ap_reg_ppstg_exitcond_reg_319_pp0_it1)
begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it2) & ~(((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ap_sig_bdd_76) | (ap_sig_bdd_81 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1))) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_319_pp0_it1))) begin
data_p2_ce0 = ap_const_logic_1;
end else begin
data_p2_ce0 = ap_const_logic_0;
end
end
/// data_p2_we0 assign process. ///
always @ (ap_CS_fsm or ap_reg_ppiten_pp0_it0 or ap_sig_bdd_76 or ap_sig_bdd_81 or ap_reg_ppiten_pp0_it1 or ap_reg_ppiten_pp0_it2 or ap_reg_ppstg_exitcond_reg_319_pp0_it1)
begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it2) & ~(((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ap_sig_bdd_76) | (ap_sig_bdd_81 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1))) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_319_pp0_it1))) begin
data_p2_we0 = ap_const_logic_1;
end else begin
data_p2_we0 = ap_const_logic_0;
end
end
/// data_p3_ce0 assign process. ///
always @ (ap_CS_fsm or ap_reg_ppiten_pp0_it0 or ap_sig_bdd_76 or ap_sig_bdd_81 or ap_reg_ppiten_pp0_it1 or ap_reg_ppiten_pp0_it2 or ap_reg_ppstg_exitcond_reg_319_pp0_it1)
begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it2) & ~(((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ap_sig_bdd_76) | (ap_sig_bdd_81 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1))) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_319_pp0_it1))) begin
data_p3_ce0 = ap_const_logic_1;
end else begin
data_p3_ce0 = ap_const_logic_0;
end
end
/// data_p3_we0 assign process. ///
always @ (ap_CS_fsm or ap_reg_ppiten_pp0_it0 or ap_sig_bdd_76 or ap_sig_bdd_81 or ap_reg_ppiten_pp0_it1 or ap_reg_ppiten_pp0_it2 or ap_reg_ppstg_exitcond_reg_319_pp0_it1)
begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it2) & ~(((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ap_sig_bdd_76) | (ap_sig_bdd_81 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1))) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_319_pp0_it1))) begin
data_p3_we0 = ap_const_logic_1;
end else begin
data_p3_we0 = ap_const_logic_0;
end
end
/// i_phi_fu_143_p4 assign process. ///
always @ (ap_CS_fsm or i_reg_139 or exitcond_reg_319 or ap_reg_ppiten_pp0_it1 or i_mid_reg_328)
begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (exitcond_reg_319 == ap_const_lv1_0) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1))) begin
i_phi_fu_143_p4 = i_mid_reg_328;
end else begin
i_phi_fu_143_p4 = i_reg_139;
end
end
/// indvar_flatten_phi_fu_132_p4 assign process. ///
always @ (ap_CS_fsm or indvar_flatten_reg_128 or exitcond_reg_319 or ap_reg_ppiten_pp0_it1 or indvar_next_reg_323)
begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (exitcond_reg_319 == ap_const_lv1_0) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1))) begin
indvar_flatten_phi_fu_132_p4 = indvar_next_reg_323;
end else begin
indvar_flatten_phi_fu_132_p4 = indvar_flatten_reg_128;
end
end
/// indvar_phi_fu_154_p4 assign process. ///
always @ (ap_CS_fsm or indvar_reg_150 or exitcond_reg_319 or ap_reg_ppiten_pp0_it1 or indvar_next1_reg_343)
begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (exitcond_reg_319 == ap_const_lv1_0) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1))) begin
indvar_phi_fu_154_p4 = indvar_next1_reg_343;
end else begin
indvar_phi_fu_154_p4 = indvar_reg_150;
end
end
/// ap_sig_bdd_76 assign process. ///
always @ (bus_r_req_full_n or exitcond_fu_162_p2)
begin
ap_sig_bdd_76 = ((bus_r_req_full_n == ap_const_logic_0) & (exitcond_fu_162_p2 == ap_const_lv1_0));
end
/// ap_sig_bdd_81 assign process. ///
always @ (bus_r_rsp_empty_n or exitcond_reg_319)
begin
ap_sig_bdd_81 = ((bus_r_rsp_empty_n == ap_const_logic_0) & (exitcond_reg_319 == ap_const_lv1_0));
end
assign bus_r_address = tmp_fu_212_p1;
assign bus_r_dataout = ap_const_lv128_lc_1;
assign bus_r_req_din = ap_const_logic_0;
assign bus_r_size = ap_const_lv32_0;
assign data_p0_addr1_cast_fu_300_p1 = {{24{1'b0}}, {ap_reg_ppstg_data_p0_addr_reg_338_pp0_it1}};
assign data_p0_addr_cast_fu_244_p2 = (p_shl_fu_238_p2 - tmp4_trn_cast_fu_234_p1);
assign data_p0_address0 = data_p0_addr1_cast_fu_300_p1;
assign data_p0_d0 = Result1_reg_348;
assign data_p1_address0 = data_p0_addr1_cast_fu_300_p1;
assign data_p1_d0 = Result3_reg_353;
assign data_p2_address0 = data_p0_addr1_cast_fu_300_p1;
assign data_p2_d0 = Result2_reg_358;
assign data_p3_address0 = data_p0_addr1_cast_fu_300_p1;
assign data_p3_d0 = Result_reg_363;
assign exitcond1_fu_180_p1 = ap_const_lv3_4;
assign exitcond1_fu_180_p2 = (indvar_phi_fu_154_p4 == exitcond1_fu_180_p1? 1'b1: 1'b0);
assign exitcond_fu_162_p1 = ap_const_lv8_F0;
assign exitcond_fu_162_p2 = (indvar_flatten_phi_fu_132_p4 == exitcond_fu_162_p1? 1'b1: 1'b0);
assign i_mid_fu_194_p3 = ((exitcond1_fu_180_p2)? indvar_next6_dup_fu_174_p2: i_phi_fu_143_p4);
assign indvar_cast_fu_202_p1 = {{1{1'b0}}, {indvar_mid_fu_186_p3}};
assign indvar_mid_fu_186_p3 = ((exitcond1_fu_180_p2)? ap_const_lv3_0: indvar_phi_fu_154_p4);
assign indvar_next6_dup_fu_174_p2 = (i_phi_fu_143_p4 + ap_const_lv6_1);
assign j_fu_206_p2 = indvar_cast_fu_202_p1 << ap_const_lv4_2;
assign p_shl_fu_238_p2 = tmp4_trn_cast_fu_234_p1 << ap_const_lv8_4;
assign tmp4_trn_cast_fu_234_p1 = {{2{1'b0}}, {i_mid_fu_194_p3}};
assign tmp8_trn_cast_fu_230_p1 = {{4{1'b0}}, {j_fu_206_p2}};
assign tmp_fu_212_p1 = {{32{fIndex[31]}}, {fIndex}};
endmodule //fFetch_array
|
// ==============================================================
// RTL generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ===========================================================
`timescale 1 ns / 1 ps
module uFetch_array (
ap_clk,
ap_rst,
ap_start,
ap_done,
ap_idle,
bus_r_req_din,
bus_r_req_full_n,
bus_r_req_write,
bus_r_rsp_dout,
bus_r_rsp_empty_n,
bus_r_rsp_read,
bus_r_address,
bus_r_datain,
bus_r_dataout,
bus_r_size,
data_p0_address0,
data_p0_ce0,
data_p0_we0,
data_p0_d0,
data_p1_address0,
data_p1_ce0,
data_p1_we0,
data_p1_d0,
data_p2_address0,
data_p2_ce0,
data_p2_we0,
data_p2_d0,
data_p3_address0,
data_p3_ce0,
data_p3_we0,
data_p3_d0
);
input ap_clk;
input ap_rst;
input ap_start;
output ap_done;
output ap_idle;
output bus_r_req_din;
input bus_r_req_full_n;
output bus_r_req_write;
input bus_r_rsp_dout;
input bus_r_rsp_empty_n;
output bus_r_rsp_read;
output [31:0] bus_r_address;
input [127:0] bus_r_datain;
output [127:0] bus_r_dataout;
output [31:0] bus_r_size;
output [7:0] data_p0_address0;
output data_p0_ce0;
output data_p0_we0;
output [31:0] data_p0_d0;
output [7:0] data_p1_address0;
output data_p1_ce0;
output data_p1_we0;
output [31:0] data_p1_d0;
output [7:0] data_p2_address0;
output data_p2_ce0;
output data_p2_we0;
output [31:0] data_p2_d0;
output [7:0] data_p3_address0;
output data_p3_ce0;
output data_p3_we0;
output [31:0] data_p3_d0;
reg ap_done;
reg ap_idle;
reg bus_r_req_write;
reg bus_r_rsp_read;
reg data_p0_ce0;
reg data_p0_we0;
reg data_p1_ce0;
reg data_p1_we0;
reg data_p2_ce0;
reg data_p2_we0;
reg data_p3_ce0;
reg data_p3_we0;
reg [1:0] ap_CS_fsm;
reg [31:0] uIndex;
reg [7:0] indvar_flatten_reg_128;
reg [5:0] i_reg_139;
reg [2:0] indvar_reg_150;
wire [0:0] exitcond_fu_162_p2;
reg [0:0] exitcond_reg_319;
reg ap_reg_ppiten_pp0_it0;
reg ap_sig_bdd_76;
reg ap_sig_bdd_81;
reg ap_reg_ppiten_pp0_it1;
reg ap_reg_ppiten_pp0_it2;
reg [0:0] ap_reg_ppstg_exitcond_reg_319_pp0_it1;
reg [7:0] indvar_next_reg_323;
wire [5:0] i_mid_fu_194_p3;
reg [5:0] i_mid_reg_328;
reg [7:0] data_p0_addr_reg_338;
reg [7:0] ap_reg_ppstg_data_p0_addr_reg_338_pp0_it1;
reg [2:0] indvar_next1_reg_343;
reg [31:0] Result1_reg_348;
reg [31:0] Result3_reg_353;
reg [31:0] Result2_reg_358;
reg [31:0] Result_reg_363;
reg [7:0] indvar_flatten_phi_fu_132_p4;
reg [5:0] i_phi_fu_143_p4;
reg [2:0] indvar_phi_fu_154_p4;
wire [31:0] data_p0_addr1_cast_fu_300_p1;
wire [63:0] tmp_fu_212_p1;
wire [7:0] exitcond_fu_162_p1;
wire [2:0] exitcond1_fu_180_p1;
wire [0:0] exitcond1_fu_180_p2;
wire [5:0] indvar_next6_dup_fu_174_p2;
wire [2:0] indvar_mid_fu_186_p3;
wire [3:0] indvar_cast_fu_202_p1;
wire [3:0] j_fu_206_p2;
wire [7:0] tmp4_trn_cast_fu_234_p1;
wire [7:0] p_shl_fu_238_p2;
wire [7:0] data_p0_addr_cast_fu_244_p2;
wire [7:0] tmp8_trn_cast_fu_230_p1;
reg [1:0] ap_NS_fsm;
parameter ap_const_logic_1 = 1'b1;
parameter ap_const_logic_0 = 1'b0;
parameter ap_ST_st0_fsm_0 = 2'b00;
parameter ap_ST_st1_fsm_1 = 2'b01;
parameter ap_ST_pp0_stg0_fsm_2 = 2'b10;
parameter ap_ST_st5_fsm_3 = 2'b11;
parameter ap_const_lv32_0 = 32'b00000000000000000000000000000000;
parameter ap_const_lv1_0 = 1'b0;
parameter ap_const_lv8_0 = 8'b00000000;
parameter ap_const_lv6_0 = 6'b000000;
parameter ap_const_lv3_0 = 3'b000;
parameter ap_const_lv8_F0 = 8'b11110000;
parameter ap_const_lv8_1 = 8'b00000001;
parameter ap_const_lv6_1 = 6'b000001;
parameter ap_const_lv3_4 = 3'b100;
parameter ap_const_lv4_2 = 4'b0010;
parameter ap_const_lv32_1 = 32'b00000000000000000000000000000001;
parameter ap_const_lv8_4 = 8'b00000100;
parameter ap_const_lv3_1 = 3'b001;
parameter ap_const_lv32_20 = 32'b00000000000000000000000000100000;
parameter ap_const_lv32_3F = 32'b00000000000000000000000000111111;
parameter ap_const_lv32_40 = 32'b00000000000000000000000001000000;
parameter ap_const_lv32_5F = 32'b00000000000000000000000001011111;
parameter ap_const_lv32_60 = 32'b00000000000000000000000001100000;
parameter ap_const_lv32_7F = 32'b00000000000000000000000001111111;
parameter ap_const_lv128_lc_1 = 128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_true = 1'b1;
/// ap_CS_fsm assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_CS_fsm
if (ap_rst == 1'b1) begin
ap_CS_fsm <= ap_ST_st0_fsm_0;
end else begin
ap_CS_fsm <= ap_NS_fsm;
end
end
/// ap_reg_ppiten_pp0_it0 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it0
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it0 <= ap_const_logic_0;
end else begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & ~(((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ap_sig_bdd_76) | (ap_sig_bdd_81 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1))) & ~(exitcond_fu_162_p2 == ap_const_lv1_0))) begin
ap_reg_ppiten_pp0_it0 <= ap_const_logic_0;
end else if ((ap_ST_st1_fsm_1 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it0 <= ap_const_logic_1;
end
end
end
/// ap_reg_ppiten_pp0_it1 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it1
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it1 <= ap_const_logic_0;
end else begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (exitcond_fu_162_p2 == ap_const_lv1_0) & ~(((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ap_sig_bdd_76) | (ap_sig_bdd_81 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1))))) begin
ap_reg_ppiten_pp0_it1 <= ap_const_logic_1;
end else if (((ap_ST_st1_fsm_1 == ap_CS_fsm) | ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & ~(((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ap_sig_bdd_76) | (ap_sig_bdd_81 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1))) & ~(exitcond_fu_162_p2 == ap_const_lv1_0)))) begin
ap_reg_ppiten_pp0_it1 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp0_it2 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it2
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it2 <= ap_const_logic_0;
end else begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & ~(((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ap_sig_bdd_76) | (ap_sig_bdd_81 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1))))) begin
ap_reg_ppiten_pp0_it2 <= ap_reg_ppiten_pp0_it1;
end else if ((ap_ST_st1_fsm_1 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it2 <= ap_const_logic_0;
end
end
end
/// uIndex assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_uIndex
if (ap_rst == 1'b1) begin
uIndex <= ap_const_lv32_0;
end else begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_fu_162_p2 == ap_const_lv1_0) & ~(((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ap_sig_bdd_76) | (ap_sig_bdd_81 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1))))) begin
uIndex <= (uIndex + ap_const_lv32_1);
end
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (exitcond_reg_319 == ap_const_lv1_0) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & ~(((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ap_sig_bdd_76) | (ap_sig_bdd_81 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1))))) begin
Result1_reg_348 <= bus_r_datain[31:0];
end
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (exitcond_reg_319 == ap_const_lv1_0) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & ~(((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ap_sig_bdd_76) | (ap_sig_bdd_81 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1))))) begin
Result2_reg_358 <= {{bus_r_datain[ap_const_lv32_5F : ap_const_lv32_40]}};
end
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (exitcond_reg_319 == ap_const_lv1_0) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & ~(((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ap_sig_bdd_76) | (ap_sig_bdd_81 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1))))) begin
Result3_reg_353 <= {{bus_r_datain[ap_const_lv32_3F : ap_const_lv32_20]}};
end
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (exitcond_reg_319 == ap_const_lv1_0) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & ~(((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ap_sig_bdd_76) | (ap_sig_bdd_81 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1))))) begin
Result_reg_363 <= {{bus_r_datain[ap_const_lv32_7F : ap_const_lv32_60]}};
end
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & ~(((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ap_sig_bdd_76) | (ap_sig_bdd_81 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1))))) begin
ap_reg_ppstg_data_p0_addr_reg_338_pp0_it1 <= data_p0_addr_reg_338;
end
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & ~(((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ap_sig_bdd_76) | (ap_sig_bdd_81 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1))))) begin
ap_reg_ppstg_exitcond_reg_319_pp0_it1 <= exitcond_reg_319;
end
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_fu_162_p2 == ap_const_lv1_0) & ~(((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ap_sig_bdd_76) | (ap_sig_bdd_81 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1))))) begin
data_p0_addr_reg_338 <= (data_p0_addr_cast_fu_244_p2 + tmp8_trn_cast_fu_230_p1);
end
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ~(((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ap_sig_bdd_76) | (ap_sig_bdd_81 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1))))) begin
exitcond_reg_319 <= (indvar_flatten_phi_fu_132_p4 == exitcond_fu_162_p1? 1'b1: 1'b0);
end
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_fu_162_p2 == ap_const_lv1_0) & ~(((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ap_sig_bdd_76) | (ap_sig_bdd_81 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1))))) begin
if (exitcond1_fu_180_p2) begin
i_mid_reg_328 <= indvar_next6_dup_fu_174_p2;
end else begin
i_mid_reg_328 <= i_phi_fu_143_p4;
end
end
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (exitcond_reg_319 == ap_const_lv1_0) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & ~(((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ap_sig_bdd_76) | (ap_sig_bdd_81 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1))))) begin
i_reg_139 <= i_mid_reg_328;
end else if ((ap_ST_st1_fsm_1 == ap_CS_fsm)) begin
i_reg_139 <= ap_const_lv6_0;
end
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (exitcond_reg_319 == ap_const_lv1_0) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & ~(((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ap_sig_bdd_76) | (ap_sig_bdd_81 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1))))) begin
indvar_flatten_reg_128 <= indvar_next_reg_323;
end else if ((ap_ST_st1_fsm_1 == ap_CS_fsm)) begin
indvar_flatten_reg_128 <= ap_const_lv8_0;
end
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_fu_162_p2 == ap_const_lv1_0) & ~(((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ap_sig_bdd_76) | (ap_sig_bdd_81 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1))))) begin
indvar_next1_reg_343 <= (indvar_mid_fu_186_p3 + ap_const_lv3_1);
end
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ~(((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ap_sig_bdd_76) | (ap_sig_bdd_81 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1))))) begin
indvar_next_reg_323 <= (indvar_flatten_phi_fu_132_p4 + ap_const_lv8_1);
end
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (exitcond_reg_319 == ap_const_lv1_0) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & ~(((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ap_sig_bdd_76) | (ap_sig_bdd_81 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1))))) begin
indvar_reg_150 <= indvar_next1_reg_343;
end else if ((ap_ST_st1_fsm_1 == ap_CS_fsm)) begin
indvar_reg_150 <= ap_const_lv3_0;
end
end
/// ap_NS_fsm assign process. ///
always @ (ap_start or ap_CS_fsm or exitcond_fu_162_p2 or ap_reg_ppiten_pp0_it0 or ap_sig_bdd_76 or ap_sig_bdd_81 or ap_reg_ppiten_pp0_it1 or ap_reg_ppiten_pp0_it2)
begin
if ((((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it2) & ~(((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ap_sig_bdd_76) | (ap_sig_bdd_81 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1))) & ~(ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ~(((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ap_sig_bdd_76) | (ap_sig_bdd_81 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1))) & ~(exitcond_fu_162_p2 == ap_const_lv1_0) & ~(ap_const_logic_1 == ap_reg_ppiten_pp0_it1)))) begin
ap_NS_fsm = ap_ST_st5_fsm_3;
end else if ((~(ap_const_logic_1 == ap_start) & (ap_ST_st5_fsm_3 == ap_CS_fsm))) begin
ap_NS_fsm = ap_ST_st0_fsm_0;
end else if ((ap_ST_st1_fsm_1 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_pp0_stg0_fsm_2;
end else if ((((ap_ST_st0_fsm_0 == ap_CS_fsm) & (ap_const_logic_1 == ap_start)) | ((ap_const_logic_1 == ap_start) & (ap_ST_st5_fsm_3 == ap_CS_fsm)))) begin
ap_NS_fsm = ap_ST_st1_fsm_1;
end else begin
ap_NS_fsm = ap_CS_fsm;
end
end
/// ap_done assign process. ///
always @ (ap_CS_fsm)
begin
if (((ap_ST_st0_fsm_0 == ap_CS_fsm) | (ap_ST_st5_fsm_3 == ap_CS_fsm))) begin
ap_done = ap_const_logic_1;
end else begin
ap_done = ap_const_logic_0;
end
end
/// ap_idle assign process. ///
always @ (ap_CS_fsm)
begin
if ((ap_ST_st0_fsm_0 == ap_CS_fsm)) begin
ap_idle = ap_const_logic_1;
end else begin
ap_idle = ap_const_logic_0;
end
end
/// bus_r_req_write assign process. ///
always @ (ap_CS_fsm or exitcond_fu_162_p2 or ap_reg_ppiten_pp0_it0 or ap_sig_bdd_76 or ap_sig_bdd_81 or ap_reg_ppiten_pp0_it1)
begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_fu_162_p2 == ap_const_lv1_0) & ~(((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ap_sig_bdd_76) | (ap_sig_bdd_81 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1))))) begin
bus_r_req_write = ap_const_logic_1;
end else begin
bus_r_req_write = ap_const_logic_0;
end
end
/// bus_r_rsp_read assign process. ///
always @ (ap_CS_fsm or exitcond_reg_319 or ap_reg_ppiten_pp0_it0 or ap_sig_bdd_76 or ap_sig_bdd_81 or ap_reg_ppiten_pp0_it1)
begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (exitcond_reg_319 == ap_const_lv1_0) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & ~(((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ap_sig_bdd_76) | (ap_sig_bdd_81 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1))))) begin
bus_r_rsp_read = ap_const_logic_1;
end else begin
bus_r_rsp_read = ap_const_logic_0;
end
end
/// data_p0_ce0 assign process. ///
always @ (ap_CS_fsm or ap_reg_ppiten_pp0_it0 or ap_sig_bdd_76 or ap_sig_bdd_81 or ap_reg_ppiten_pp0_it1 or ap_reg_ppiten_pp0_it2 or ap_reg_ppstg_exitcond_reg_319_pp0_it1)
begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it2) & ~(((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ap_sig_bdd_76) | (ap_sig_bdd_81 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1))) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_319_pp0_it1))) begin
data_p0_ce0 = ap_const_logic_1;
end else begin
data_p0_ce0 = ap_const_logic_0;
end
end
/// data_p0_we0 assign process. ///
always @ (ap_CS_fsm or ap_reg_ppiten_pp0_it0 or ap_sig_bdd_76 or ap_sig_bdd_81 or ap_reg_ppiten_pp0_it1 or ap_reg_ppiten_pp0_it2 or ap_reg_ppstg_exitcond_reg_319_pp0_it1)
begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it2) & ~(((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ap_sig_bdd_76) | (ap_sig_bdd_81 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1))) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_319_pp0_it1))) begin
data_p0_we0 = ap_const_logic_1;
end else begin
data_p0_we0 = ap_const_logic_0;
end
end
/// data_p1_ce0 assign process. ///
always @ (ap_CS_fsm or ap_reg_ppiten_pp0_it0 or ap_sig_bdd_76 or ap_sig_bdd_81 or ap_reg_ppiten_pp0_it1 or ap_reg_ppiten_pp0_it2 or ap_reg_ppstg_exitcond_reg_319_pp0_it1)
begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it2) & ~(((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ap_sig_bdd_76) | (ap_sig_bdd_81 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1))) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_319_pp0_it1))) begin
data_p1_ce0 = ap_const_logic_1;
end else begin
data_p1_ce0 = ap_const_logic_0;
end
end
/// data_p1_we0 assign process. ///
always @ (ap_CS_fsm or ap_reg_ppiten_pp0_it0 or ap_sig_bdd_76 or ap_sig_bdd_81 or ap_reg_ppiten_pp0_it1 or ap_reg_ppiten_pp0_it2 or ap_reg_ppstg_exitcond_reg_319_pp0_it1)
begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it2) & ~(((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ap_sig_bdd_76) | (ap_sig_bdd_81 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1))) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_319_pp0_it1))) begin
data_p1_we0 = ap_const_logic_1;
end else begin
data_p1_we0 = ap_const_logic_0;
end
end
/// data_p2_ce0 assign process. ///
always @ (ap_CS_fsm or ap_reg_ppiten_pp0_it0 or ap_sig_bdd_76 or ap_sig_bdd_81 or ap_reg_ppiten_pp0_it1 or ap_reg_ppiten_pp0_it2 or ap_reg_ppstg_exitcond_reg_319_pp0_it1)
begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it2) & ~(((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ap_sig_bdd_76) | (ap_sig_bdd_81 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1))) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_319_pp0_it1))) begin
data_p2_ce0 = ap_const_logic_1;
end else begin
data_p2_ce0 = ap_const_logic_0;
end
end
/// data_p2_we0 assign process. ///
always @ (ap_CS_fsm or ap_reg_ppiten_pp0_it0 or ap_sig_bdd_76 or ap_sig_bdd_81 or ap_reg_ppiten_pp0_it1 or ap_reg_ppiten_pp0_it2 or ap_reg_ppstg_exitcond_reg_319_pp0_it1)
begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it2) & ~(((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ap_sig_bdd_76) | (ap_sig_bdd_81 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1))) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_319_pp0_it1))) begin
data_p2_we0 = ap_const_logic_1;
end else begin
data_p2_we0 = ap_const_logic_0;
end
end
/// data_p3_ce0 assign process. ///
always @ (ap_CS_fsm or ap_reg_ppiten_pp0_it0 or ap_sig_bdd_76 or ap_sig_bdd_81 or ap_reg_ppiten_pp0_it1 or ap_reg_ppiten_pp0_it2 or ap_reg_ppstg_exitcond_reg_319_pp0_it1)
begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it2) & ~(((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ap_sig_bdd_76) | (ap_sig_bdd_81 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1))) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_319_pp0_it1))) begin
data_p3_ce0 = ap_const_logic_1;
end else begin
data_p3_ce0 = ap_const_logic_0;
end
end
/// data_p3_we0 assign process. ///
always @ (ap_CS_fsm or ap_reg_ppiten_pp0_it0 or ap_sig_bdd_76 or ap_sig_bdd_81 or ap_reg_ppiten_pp0_it1 or ap_reg_ppiten_pp0_it2 or ap_reg_ppstg_exitcond_reg_319_pp0_it1)
begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it2) & ~(((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ap_sig_bdd_76) | (ap_sig_bdd_81 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1))) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_319_pp0_it1))) begin
data_p3_we0 = ap_const_logic_1;
end else begin
data_p3_we0 = ap_const_logic_0;
end
end
/// i_phi_fu_143_p4 assign process. ///
always @ (ap_CS_fsm or i_reg_139 or exitcond_reg_319 or ap_reg_ppiten_pp0_it1 or i_mid_reg_328)
begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (exitcond_reg_319 == ap_const_lv1_0) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1))) begin
i_phi_fu_143_p4 = i_mid_reg_328;
end else begin
i_phi_fu_143_p4 = i_reg_139;
end
end
/// indvar_flatten_phi_fu_132_p4 assign process. ///
always @ (ap_CS_fsm or indvar_flatten_reg_128 or exitcond_reg_319 or ap_reg_ppiten_pp0_it1 or indvar_next_reg_323)
begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (exitcond_reg_319 == ap_const_lv1_0) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1))) begin
indvar_flatten_phi_fu_132_p4 = indvar_next_reg_323;
end else begin
indvar_flatten_phi_fu_132_p4 = indvar_flatten_reg_128;
end
end
/// indvar_phi_fu_154_p4 assign process. ///
always @ (ap_CS_fsm or indvar_reg_150 or exitcond_reg_319 or ap_reg_ppiten_pp0_it1 or indvar_next1_reg_343)
begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (exitcond_reg_319 == ap_const_lv1_0) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1))) begin
indvar_phi_fu_154_p4 = indvar_next1_reg_343;
end else begin
indvar_phi_fu_154_p4 = indvar_reg_150;
end
end
/// ap_sig_bdd_76 assign process. ///
always @ (bus_r_req_full_n or exitcond_fu_162_p2)
begin
ap_sig_bdd_76 = ((bus_r_req_full_n == ap_const_logic_0) & (exitcond_fu_162_p2 == ap_const_lv1_0));
end
/// ap_sig_bdd_81 assign process. ///
always @ (bus_r_rsp_empty_n or exitcond_reg_319)
begin
ap_sig_bdd_81 = ((bus_r_rsp_empty_n == ap_const_logic_0) & (exitcond_reg_319 == ap_const_lv1_0));
end
assign bus_r_address = tmp_fu_212_p1;
assign bus_r_dataout = ap_const_lv128_lc_1;
assign bus_r_req_din = ap_const_logic_0;
assign bus_r_size = ap_const_lv32_0;
assign data_p0_addr1_cast_fu_300_p1 = {{24{1'b0}}, {ap_reg_ppstg_data_p0_addr_reg_338_pp0_it1}};
assign data_p0_addr_cast_fu_244_p2 = (p_shl_fu_238_p2 - tmp4_trn_cast_fu_234_p1);
assign data_p0_address0 = data_p0_addr1_cast_fu_300_p1;
assign data_p0_d0 = Result1_reg_348;
assign data_p1_address0 = data_p0_addr1_cast_fu_300_p1;
assign data_p1_d0 = Result3_reg_353;
assign data_p2_address0 = data_p0_addr1_cast_fu_300_p1;
assign data_p2_d0 = Result2_reg_358;
assign data_p3_address0 = data_p0_addr1_cast_fu_300_p1;
assign data_p3_d0 = Result_reg_363;
assign exitcond1_fu_180_p1 = ap_const_lv3_4;
assign exitcond1_fu_180_p2 = (indvar_phi_fu_154_p4 == exitcond1_fu_180_p1? 1'b1: 1'b0);
assign exitcond_fu_162_p1 = ap_const_lv8_F0;
assign exitcond_fu_162_p2 = (indvar_flatten_phi_fu_132_p4 == exitcond_fu_162_p1? 1'b1: 1'b0);
assign i_mid_fu_194_p3 = ((exitcond1_fu_180_p2)? indvar_next6_dup_fu_174_p2: i_phi_fu_143_p4);
assign indvar_cast_fu_202_p1 = {{1{1'b0}}, {indvar_mid_fu_186_p3}};
assign indvar_mid_fu_186_p3 = ((exitcond1_fu_180_p2)? ap_const_lv3_0: indvar_phi_fu_154_p4);
assign indvar_next6_dup_fu_174_p2 = (i_phi_fu_143_p4 + ap_const_lv6_1);
assign j_fu_206_p2 = indvar_cast_fu_202_p1 << ap_const_lv4_2;
assign p_shl_fu_238_p2 = tmp4_trn_cast_fu_234_p1 << ap_const_lv8_4;
assign tmp4_trn_cast_fu_234_p1 = {{2{1'b0}}, {i_mid_fu_194_p3}};
assign tmp8_trn_cast_fu_230_p1 = {{4{1'b0}}, {j_fu_206_p2}};
assign tmp_fu_212_p1 = {{32{uIndex[31]}}, {uIndex}};
endmodule //uFetch_array
|
// ==============================================================
// RTL generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ===========================================================
`timescale 1 ns / 1 ps
module write_array (
ap_clk,
ap_rst,
ap_start,
ap_done,
ap_idle,
bus_r_req_din,
bus_r_req_full_n,
bus_r_req_write,
bus_r_rsp_dout,
bus_r_rsp_empty_n,
bus_r_rsp_read,
bus_r_address,
bus_r_datain,
bus_r_dataout,
bus_r_size,
data_p0_address0,
data_p0_ce0,
data_p0_q0,
data_p1_address0,
data_p1_ce0,
data_p1_q0,
data_p2_address0,
data_p2_ce0,
data_p2_q0,
data_p3_address0,
data_p3_ce0,
data_p3_q0
);
input ap_clk;
input ap_rst;
input ap_start;
output ap_done;
output ap_idle;
output bus_r_req_din;
input bus_r_req_full_n;
output bus_r_req_write;
input bus_r_rsp_dout;
input bus_r_rsp_empty_n;
output bus_r_rsp_read;
output [31:0] bus_r_address;
input [127:0] bus_r_datain;
output [127:0] bus_r_dataout;
output [31:0] bus_r_size;
output [7:0] data_p0_address0;
output data_p0_ce0;
input [31:0] data_p0_q0;
output [7:0] data_p1_address0;
output data_p1_ce0;
input [31:0] data_p1_q0;
output [7:0] data_p2_address0;
output data_p2_ce0;
input [31:0] data_p2_q0;
output [7:0] data_p3_address0;
output data_p3_ce0;
input [31:0] data_p3_q0;
reg ap_done;
reg ap_idle;
reg bus_r_req_din;
reg bus_r_req_write;
reg data_p0_ce0;
reg data_p1_ce0;
reg data_p2_ce0;
reg data_p3_ce0;
reg [1:0] ap_CS_fsm;
reg [31:0] rIndex;
reg [7:0] indvar_flatten_reg_117;
reg [5:0] i_reg_128;
reg [2:0] indvar_reg_139;
wire [0:0] exitcond_fu_151_p2;
reg [0:0] exitcond_reg_284;
reg ap_reg_ppiten_pp0_it0;
reg ap_reg_ppiten_pp0_it1;
reg [0:0] ap_reg_ppstg_exitcond_reg_284_pp0_it1;
reg ap_sig_bdd_75;
reg ap_reg_ppiten_pp0_it2;
reg ap_reg_ppiten_pp0_it3;
reg [7:0] indvar_next_reg_288;
wire [5:0] i_mid_fu_183_p3;
reg [5:0] i_mid_reg_293;
reg [2:0] indvar_next1_reg_318;
reg [31:0] data_p0_load_reg_323;
reg [31:0] data_p1_load_reg_328;
reg [31:0] data_p2_load_reg_333;
reg [31:0] data_p3_load_reg_338;
reg [7:0] indvar_flatten_phi_fu_121_p4;
reg [5:0] i_phi_fu_132_p4;
reg [2:0] indvar_phi_fu_143_p4;
wire [31:0] data_p0_addr1_cast_fu_227_p1;
wire [63:0] tmp4_fu_266_p1;
wire [7:0] exitcond_fu_151_p1;
wire [2:0] exitcond1_fu_169_p1;
wire [0:0] exitcond1_fu_169_p2;
wire [5:0] indvar_next6_dup_fu_163_p2;
wire [2:0] indvar_mid_fu_175_p3;
wire [3:0] indvar_cast_fu_191_p1;
wire [3:0] j_fu_195_p2;
wire [7:0] tmp4_trn_cast_fu_205_p1;
wire [7:0] p_shl_fu_209_p2;
wire [7:0] data_p0_addr_cast_fu_215_p2;
wire [7:0] tmp6_trn_cast_fu_201_p1;
wire [7:0] data_p0_addr_fu_221_p2;
wire [31:0] empty_92_fu_253_p1;
wire [31:0] empty_92_fu_253_p2;
wire [31:0] empty_92_fu_253_p3;
wire [31:0] tmp3_fu_250_p1;
reg [1:0] ap_NS_fsm;
parameter ap_const_logic_1 = 1'b1;
parameter ap_const_logic_0 = 1'b0;
parameter ap_ST_st0_fsm_0 = 2'b00;
parameter ap_ST_st1_fsm_1 = 2'b01;
parameter ap_ST_pp0_stg0_fsm_2 = 2'b10;
parameter ap_ST_st6_fsm_3 = 2'b11;
parameter ap_const_lv32_0 = 32'b00000000000000000000000000000000;
parameter ap_const_lv1_0 = 1'b0;
parameter ap_const_lv8_0 = 8'b00000000;
parameter ap_const_lv6_0 = 6'b000000;
parameter ap_const_lv3_0 = 3'b000;
parameter ap_const_lv8_F0 = 8'b11110000;
parameter ap_const_lv8_1 = 8'b00000001;
parameter ap_const_lv6_1 = 6'b000001;
parameter ap_const_lv3_4 = 3'b100;
parameter ap_const_lv4_2 = 4'b0010;
parameter ap_const_lv8_4 = 8'b00000100;
parameter ap_const_lv3_1 = 3'b001;
parameter ap_const_lv32_1 = 32'b00000000000000000000000000000001;
parameter ap_true = 1'b1;
/// ap_CS_fsm assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_CS_fsm
if (ap_rst == 1'b1) begin
ap_CS_fsm <= ap_ST_st0_fsm_0;
end else begin
ap_CS_fsm <= ap_NS_fsm;
end
end
/// ap_reg_ppiten_pp0_it0 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it0
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it0 <= ap_const_logic_0;
end else begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & ~(ap_sig_bdd_75 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it2)) & ~(exitcond_fu_151_p2 == ap_const_lv1_0))) begin
ap_reg_ppiten_pp0_it0 <= ap_const_logic_0;
end else if ((ap_ST_st1_fsm_1 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it0 <= ap_const_logic_1;
end
end
end
/// ap_reg_ppiten_pp0_it1 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it1
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it1 <= ap_const_logic_0;
end else begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & ~(ap_sig_bdd_75 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it2)) & (exitcond_fu_151_p2 == ap_const_lv1_0))) begin
ap_reg_ppiten_pp0_it1 <= ap_const_logic_1;
end else if (((ap_ST_st1_fsm_1 == ap_CS_fsm) | ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & ~(ap_sig_bdd_75 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it2)) & ~(exitcond_fu_151_p2 == ap_const_lv1_0)))) begin
ap_reg_ppiten_pp0_it1 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp0_it2 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it2
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it2 <= ap_const_logic_0;
end else begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & ~(ap_sig_bdd_75 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it2)))) begin
ap_reg_ppiten_pp0_it2 <= ap_reg_ppiten_pp0_it1;
end else if ((ap_ST_st1_fsm_1 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it2 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp0_it3 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it3
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it3 <= ap_const_logic_0;
end else begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & ~(ap_sig_bdd_75 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it2)))) begin
ap_reg_ppiten_pp0_it3 <= ap_reg_ppiten_pp0_it2;
end else if ((ap_ST_st1_fsm_1 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it3 <= ap_const_logic_0;
end
end
end
/// rIndex assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_rIndex
if (ap_rst == 1'b1) begin
rIndex <= ap_const_lv32_0;
end else begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_reg_ppstg_exitcond_reg_284_pp0_it1 == ap_const_lv1_0) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it2) & ~(ap_sig_bdd_75 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it2)))) begin
rIndex <= (rIndex + ap_const_lv32_1);
end
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & ~(ap_sig_bdd_75 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it2)))) begin
ap_reg_ppstg_exitcond_reg_284_pp0_it1 <= exitcond_reg_284;
end
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & ~(ap_sig_bdd_75 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it2)) & (exitcond_reg_284 == ap_const_lv1_0))) begin
data_p0_load_reg_323 <= data_p0_q0;
end
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & ~(ap_sig_bdd_75 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it2)) & (exitcond_reg_284 == ap_const_lv1_0))) begin
data_p1_load_reg_328 <= data_p1_q0;
end
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & ~(ap_sig_bdd_75 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it2)) & (exitcond_reg_284 == ap_const_lv1_0))) begin
data_p2_load_reg_333 <= data_p2_q0;
end
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & ~(ap_sig_bdd_75 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it2)) & (exitcond_reg_284 == ap_const_lv1_0))) begin
data_p3_load_reg_338 <= data_p3_q0;
end
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ~(ap_sig_bdd_75 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it2)))) begin
exitcond_reg_284 <= (indvar_flatten_phi_fu_121_p4 == exitcond_fu_151_p1? 1'b1: 1'b0);
end
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ~(ap_sig_bdd_75 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it2)) & (exitcond_fu_151_p2 == ap_const_lv1_0))) begin
if (exitcond1_fu_169_p2) begin
i_mid_reg_293 <= indvar_next6_dup_fu_163_p2;
end else begin
i_mid_reg_293 <= i_phi_fu_132_p4;
end
end
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & ~(ap_sig_bdd_75 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it2)) & (exitcond_reg_284 == ap_const_lv1_0))) begin
i_reg_128 <= i_mid_reg_293;
end else if ((ap_ST_st1_fsm_1 == ap_CS_fsm)) begin
i_reg_128 <= ap_const_lv6_0;
end
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & ~(ap_sig_bdd_75 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it2)) & (exitcond_reg_284 == ap_const_lv1_0))) begin
indvar_flatten_reg_117 <= indvar_next_reg_288;
end else if ((ap_ST_st1_fsm_1 == ap_CS_fsm)) begin
indvar_flatten_reg_117 <= ap_const_lv8_0;
end
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ~(ap_sig_bdd_75 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it2)) & (exitcond_fu_151_p2 == ap_const_lv1_0))) begin
indvar_next1_reg_318 <= (indvar_mid_fu_175_p3 + ap_const_lv3_1);
end
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ~(ap_sig_bdd_75 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it2)))) begin
indvar_next_reg_288 <= (indvar_flatten_phi_fu_121_p4 + ap_const_lv8_1);
end
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & ~(ap_sig_bdd_75 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it2)) & (exitcond_reg_284 == ap_const_lv1_0))) begin
indvar_reg_139 <= indvar_next1_reg_318;
end else if ((ap_ST_st1_fsm_1 == ap_CS_fsm)) begin
indvar_reg_139 <= ap_const_lv3_0;
end
end
/// ap_NS_fsm assign process. ///
always @ (ap_start or ap_CS_fsm or exitcond_fu_151_p2 or ap_reg_ppiten_pp0_it0 or ap_reg_ppiten_pp0_it1 or ap_sig_bdd_75 or ap_reg_ppiten_pp0_it2 or ap_reg_ppiten_pp0_it3)
begin
if ((((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it3) & ~(ap_sig_bdd_75 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it2)) & ~(ap_const_logic_1 == ap_reg_ppiten_pp0_it2)) | ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ~(ap_sig_bdd_75 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it2)) & ~(exitcond_fu_151_p2 == ap_const_lv1_0) & ~(ap_const_logic_1 == ap_reg_ppiten_pp0_it1)))) begin
ap_NS_fsm = ap_ST_st6_fsm_3;
end else if ((~(ap_const_logic_1 == ap_start) & (ap_ST_st6_fsm_3 == ap_CS_fsm))) begin
ap_NS_fsm = ap_ST_st0_fsm_0;
end else if ((ap_ST_st1_fsm_1 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_pp0_stg0_fsm_2;
end else if ((((ap_ST_st0_fsm_0 == ap_CS_fsm) & (ap_const_logic_1 == ap_start)) | ((ap_const_logic_1 == ap_start) & (ap_ST_st6_fsm_3 == ap_CS_fsm)))) begin
ap_NS_fsm = ap_ST_st1_fsm_1;
end else begin
ap_NS_fsm = ap_CS_fsm;
end
end
/// ap_done assign process. ///
always @ (ap_CS_fsm)
begin
if (((ap_ST_st0_fsm_0 == ap_CS_fsm) | (ap_ST_st6_fsm_3 == ap_CS_fsm))) begin
ap_done = ap_const_logic_1;
end else begin
ap_done = ap_const_logic_0;
end
end
/// ap_idle assign process. ///
always @ (ap_CS_fsm)
begin
if ((ap_ST_st0_fsm_0 == ap_CS_fsm)) begin
ap_idle = ap_const_logic_1;
end else begin
ap_idle = ap_const_logic_0;
end
end
/// bus_r_req_din assign process. ///
always @ (ap_CS_fsm or ap_reg_ppstg_exitcond_reg_284_pp0_it1 or ap_sig_bdd_75 or ap_reg_ppiten_pp0_it2)
begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_reg_ppstg_exitcond_reg_284_pp0_it1 == ap_const_lv1_0) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it2) & ~(ap_sig_bdd_75 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it2)))) begin
bus_r_req_din = ap_const_logic_1;
end else begin
bus_r_req_din = ap_const_logic_0;
end
end
/// bus_r_req_write assign process. ///
always @ (ap_CS_fsm or ap_reg_ppstg_exitcond_reg_284_pp0_it1 or ap_sig_bdd_75 or ap_reg_ppiten_pp0_it2)
begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_reg_ppstg_exitcond_reg_284_pp0_it1 == ap_const_lv1_0) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it2) & ~(ap_sig_bdd_75 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it2)))) begin
bus_r_req_write = ap_const_logic_1;
end else begin
bus_r_req_write = ap_const_logic_0;
end
end
/// data_p0_ce0 assign process. ///
always @ (ap_CS_fsm or exitcond_fu_151_p2 or ap_reg_ppiten_pp0_it0 or ap_sig_bdd_75 or ap_reg_ppiten_pp0_it2)
begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ~(ap_sig_bdd_75 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it2)) & (exitcond_fu_151_p2 == ap_const_lv1_0))) begin
data_p0_ce0 = ap_const_logic_1;
end else begin
data_p0_ce0 = ap_const_logic_0;
end
end
/// data_p1_ce0 assign process. ///
always @ (ap_CS_fsm or exitcond_fu_151_p2 or ap_reg_ppiten_pp0_it0 or ap_sig_bdd_75 or ap_reg_ppiten_pp0_it2)
begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ~(ap_sig_bdd_75 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it2)) & (exitcond_fu_151_p2 == ap_const_lv1_0))) begin
data_p1_ce0 = ap_const_logic_1;
end else begin
data_p1_ce0 = ap_const_logic_0;
end
end
/// data_p2_ce0 assign process. ///
always @ (ap_CS_fsm or exitcond_fu_151_p2 or ap_reg_ppiten_pp0_it0 or ap_sig_bdd_75 or ap_reg_ppiten_pp0_it2)
begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ~(ap_sig_bdd_75 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it2)) & (exitcond_fu_151_p2 == ap_const_lv1_0))) begin
data_p2_ce0 = ap_const_logic_1;
end else begin
data_p2_ce0 = ap_const_logic_0;
end
end
/// data_p3_ce0 assign process. ///
always @ (ap_CS_fsm or exitcond_fu_151_p2 or ap_reg_ppiten_pp0_it0 or ap_sig_bdd_75 or ap_reg_ppiten_pp0_it2)
begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ~(ap_sig_bdd_75 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it2)) & (exitcond_fu_151_p2 == ap_const_lv1_0))) begin
data_p3_ce0 = ap_const_logic_1;
end else begin
data_p3_ce0 = ap_const_logic_0;
end
end
/// i_phi_fu_132_p4 assign process. ///
always @ (ap_CS_fsm or i_reg_128 or exitcond_reg_284 or ap_reg_ppiten_pp0_it1 or i_mid_reg_293)
begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (exitcond_reg_284 == ap_const_lv1_0))) begin
i_phi_fu_132_p4 = i_mid_reg_293;
end else begin
i_phi_fu_132_p4 = i_reg_128;
end
end
/// indvar_flatten_phi_fu_121_p4 assign process. ///
always @ (ap_CS_fsm or indvar_flatten_reg_117 or exitcond_reg_284 or ap_reg_ppiten_pp0_it1 or indvar_next_reg_288)
begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (exitcond_reg_284 == ap_const_lv1_0))) begin
indvar_flatten_phi_fu_121_p4 = indvar_next_reg_288;
end else begin
indvar_flatten_phi_fu_121_p4 = indvar_flatten_reg_117;
end
end
/// indvar_phi_fu_143_p4 assign process. ///
always @ (ap_CS_fsm or indvar_reg_139 or exitcond_reg_284 or ap_reg_ppiten_pp0_it1 or indvar_next1_reg_318)
begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (exitcond_reg_284 == ap_const_lv1_0))) begin
indvar_phi_fu_143_p4 = indvar_next1_reg_318;
end else begin
indvar_phi_fu_143_p4 = indvar_reg_139;
end
end
/// ap_sig_bdd_75 assign process. ///
always @ (bus_r_req_full_n or ap_reg_ppstg_exitcond_reg_284_pp0_it1)
begin
ap_sig_bdd_75 = ((bus_r_req_full_n == ap_const_logic_0) & (ap_reg_ppstg_exitcond_reg_284_pp0_it1 == ap_const_lv1_0));
end
assign bus_r_address = tmp4_fu_266_p1;
assign bus_r_dataout = {{{{{{empty_92_fu_253_p1}, {empty_92_fu_253_p2}}}, {empty_92_fu_253_p3}}}, {tmp3_fu_250_p1}};
assign bus_r_rsp_read = ap_const_logic_0;
assign bus_r_size = ap_const_lv32_0;
assign data_p0_addr1_cast_fu_227_p1 = {{24{1'b0}}, {data_p0_addr_fu_221_p2}};
assign data_p0_addr_cast_fu_215_p2 = (p_shl_fu_209_p2 - tmp4_trn_cast_fu_205_p1);
assign data_p0_addr_fu_221_p2 = (data_p0_addr_cast_fu_215_p2 + tmp6_trn_cast_fu_201_p1);
assign data_p0_address0 = data_p0_addr1_cast_fu_227_p1;
assign data_p1_address0 = data_p0_addr1_cast_fu_227_p1;
assign data_p2_address0 = data_p0_addr1_cast_fu_227_p1;
assign data_p3_address0 = data_p0_addr1_cast_fu_227_p1;
assign empty_92_fu_253_p1 = data_p0_load_reg_323;
assign empty_92_fu_253_p2 = data_p1_load_reg_328;
assign empty_92_fu_253_p3 = data_p2_load_reg_333;
assign exitcond1_fu_169_p1 = ap_const_lv3_4;
assign exitcond1_fu_169_p2 = (indvar_phi_fu_143_p4 == exitcond1_fu_169_p1? 1'b1: 1'b0);
assign exitcond_fu_151_p1 = ap_const_lv8_F0;
assign exitcond_fu_151_p2 = (indvar_flatten_phi_fu_121_p4 == exitcond_fu_151_p1? 1'b1: 1'b0);
assign i_mid_fu_183_p3 = ((exitcond1_fu_169_p2)? indvar_next6_dup_fu_163_p2: i_phi_fu_132_p4);
assign indvar_cast_fu_191_p1 = {{1{1'b0}}, {indvar_mid_fu_175_p3}};
assign indvar_mid_fu_175_p3 = ((exitcond1_fu_169_p2)? ap_const_lv3_0: indvar_phi_fu_143_p4);
assign indvar_next6_dup_fu_163_p2 = (i_phi_fu_132_p4 + ap_const_lv6_1);
assign j_fu_195_p2 = indvar_cast_fu_191_p1 << ap_const_lv4_2;
assign p_shl_fu_209_p2 = tmp4_trn_cast_fu_205_p1 << ap_const_lv8_4;
assign tmp3_fu_250_p1 = data_p3_load_reg_338;
assign tmp4_fu_266_p1 = {{32{rIndex[31]}}, {rIndex}};
assign tmp4_trn_cast_fu_205_p1 = {{2{1'b0}}, {i_mid_fu_183_p3}};
assign tmp6_trn_cast_fu_201_p1 = {{4{1'b0}}, {j_fu_195_p2}};
endmodule //write_array
|
/////////////////////////////////////////////////////////////////////
//// ////
//// DES ////
//// DES Top Level module ////
//// ////
//// Author: Rudolf Usselmann ////
//// [email protected] ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Rudolf Usselmann ////
//// [email protected] ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
module des(desOut, desIn, key, decrypt, roundSel, clk);
output [63:0] desOut;
input [63:0] desIn;
input [55:0] key;
input decrypt;
input [3:0] roundSel;
input clk;
wire [1:48] K_sub;
wire [1:64] IP, FP;
reg [1:32] L, R;
wire [1:32] Xin;
wire [1:32] Lout, Rout;
wire [1:32] out;
assign Lout = (roundSel == 0) ? IP[33:64] : R;
assign Xin = (roundSel == 0) ? IP[01:32] : L;
assign Rout = Xin ^ out;
assign FP = { Rout, Lout};
crp u0( .P(out), .R(Lout), .K_sub(K_sub) );
always @(posedge clk)
L <= #1 Lout;
always @(posedge clk)
R <= #1 Rout;
// Select a subkey from key.
key_sel u1(
.K_sub( K_sub ),
.K( key ),
.roundSel( roundSel ),
.decrypt( decrypt )
);
// Perform initial permutation
assign IP[1:64] = { desIn[06], desIn[14], desIn[22], desIn[30], desIn[38], desIn[46],
desIn[54], desIn[62], desIn[04], desIn[12], desIn[20], desIn[28],
desIn[36], desIn[44], desIn[52], desIn[60], desIn[02], desIn[10],
desIn[18], desIn[26], desIn[34], desIn[42], desIn[50], desIn[58],
desIn[00], desIn[08], desIn[16], desIn[24], desIn[32], desIn[40],
desIn[48], desIn[56], desIn[07], desIn[15], desIn[23], desIn[31],
desIn[39], desIn[47], desIn[55], desIn[63], desIn[05], desIn[13],
desIn[21], desIn[29], desIn[37], desIn[45], desIn[53], desIn[61],
desIn[03], desIn[11], desIn[19], desIn[27], desIn[35], desIn[43],
desIn[51], desIn[59], desIn[01], desIn[09], desIn[17], desIn[25],
desIn[33], desIn[41], desIn[49], desIn[57] };
// Perform final permutation
assign desOut = { FP[40], FP[08], FP[48], FP[16], FP[56], FP[24], FP[64], FP[32],
FP[39], FP[07], FP[47], FP[15], FP[55], FP[23], FP[63], FP[31],
FP[38], FP[06], FP[46], FP[14], FP[54], FP[22], FP[62], FP[30],
FP[37], FP[05], FP[45], FP[13], FP[53], FP[21], FP[61], FP[29],
FP[36], FP[04], FP[44], FP[12], FP[52], FP[20], FP[60], FP[28],
FP[35], FP[03], FP[43], FP[11], FP[51], FP[19], FP[59], FP[27],
FP[34], FP[02], FP[42], FP[10], FP[50], FP[18], FP[58], FP[26],
FP[33], FP[01], FP[41], FP[09], FP[49], FP[17], FP[57], FP[25] };
endmodule
|
/////////////////////////////////////////////////////////////////////
//// ////
//// DES ////
//// DES Top Level module ////
//// ////
//// Author: Rudolf Usselmann ////
//// [email protected] ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Rudolf Usselmann ////
//// [email protected] ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
module des3(desOut, desIn, key1, key2, key3, decrypt, roundSel, clk);
output [63:0] desOut;
input [63:0] desIn;
input [55:0] key1;
input [55:0] key2;
input [55:0] key3;
input decrypt;
input [5:0] roundSel;
input clk;
wire [1:48] K_sub;
wire [1:64] IP, FP, tmp;
reg [1:64] FP_R;
reg [1:32] L, R;
wire [1:32] Xin;
wire [1:32] Lout;
wire [1:32] Rout;
wire [1:32] out;
//assign Lout = (roundSel == 0) ? IP[33:64] : R;
//assign Xin = (roundSel == 0) ? IP[01:32] : L;
assign Lout = (roundSel == 0) ? IP[33:64] :
( (roundSel == 16) ? FP_R[33:64] :
( (roundSel == 32) ? FP_R[33:64] :
R ));
assign Xin = (roundSel == 0) ? IP[01:32] :
( (roundSel == 16) ? FP_R[01:32] :
( (roundSel == 32) ? FP_R[01:32] :
L ));
/*
always @(roundSel or IP or tmp or R or FP)
case(roundSel)
6'h0: Lout = IP[33:64];
6'h10: Lout = FP[33:64];
6'h20: Lout = FP[33:64];
default: Lout = R;
endcase
always @(roundSel or IP or tmp or L or FP)
case(roundSel)
6'h0: Xin = IP[01:32];
6'h10: Xin = FP[01:32];
6'h20: Xin = FP[01:32];
default: Xin = L;
endcase
*/
always @(posedge clk)
FP_R <= #1 FP;
assign Rout = Xin ^ out;
assign FP = { Rout, Lout};
crp u0( .P(out), .R(Lout), .K_sub(K_sub) );
always @(posedge clk)
L <= #1 Lout;
always @(posedge clk)
R <= #1 Rout;
// Select a subkey from key.
key_sel3 u1(
.K_sub( K_sub ),
.key1( key1 ),
.key2( key2 ),
.key3( key3 ),
.roundSel( roundSel ),
.decrypt( decrypt )
);
assign tmp[1:64] = { desOut[06], desOut[14], desOut[22], desOut[30], desOut[38], desOut[46],
desOut[54], desOut[62], desOut[04], desOut[12], desOut[20], desOut[28],
desOut[36], desOut[44], desOut[52], desOut[60], desOut[02], desOut[10],
desOut[18], desOut[26], desOut[34], desOut[42], desOut[50], desOut[58],
desOut[00], desOut[08], desOut[16], desOut[24], desOut[32], desOut[40],
desOut[48], desOut[56], desOut[07], desOut[15], desOut[23], desOut[31],
desOut[39], desOut[47], desOut[55], desOut[63], desOut[05], desOut[13],
desOut[21], desOut[29], desOut[37], desOut[45], desOut[53], desOut[61],
desOut[03], desOut[11], desOut[19], desOut[27], desOut[35], desOut[43],
desOut[51], desOut[59], desOut[01], desOut[09], desOut[17], desOut[25],
desOut[33], desOut[41], desOut[49], desOut[57] };
// Perform initial permutation
assign IP[1:64] = { desIn[06], desIn[14], desIn[22], desIn[30], desIn[38], desIn[46],
desIn[54], desIn[62], desIn[04], desIn[12], desIn[20], desIn[28],
desIn[36], desIn[44], desIn[52], desIn[60], desIn[02], desIn[10],
desIn[18], desIn[26], desIn[34], desIn[42], desIn[50], desIn[58],
desIn[00], desIn[08], desIn[16], desIn[24], desIn[32], desIn[40],
desIn[48], desIn[56], desIn[07], desIn[15], desIn[23], desIn[31],
desIn[39], desIn[47], desIn[55], desIn[63], desIn[05], desIn[13],
desIn[21], desIn[29], desIn[37], desIn[45], desIn[53], desIn[61],
desIn[03], desIn[11], desIn[19], desIn[27], desIn[35], desIn[43],
desIn[51], desIn[59], desIn[01], desIn[09], desIn[17], desIn[25],
desIn[33], desIn[41], desIn[49], desIn[57] };
// Perform final permutation
assign desOut = { FP[40], FP[08], FP[48], FP[16], FP[56], FP[24], FP[64], FP[32],
FP[39], FP[07], FP[47], FP[15], FP[55], FP[23], FP[63], FP[31],
FP[38], FP[06], FP[46], FP[14], FP[54], FP[22], FP[62], FP[30],
FP[37], FP[05], FP[45], FP[13], FP[53], FP[21], FP[61], FP[29],
FP[36], FP[04], FP[44], FP[12], FP[52], FP[20], FP[60], FP[28],
FP[35], FP[03], FP[43], FP[11], FP[51], FP[19], FP[59], FP[27],
FP[34], FP[02], FP[42], FP[10], FP[50], FP[18], FP[58], FP[26],
FP[33], FP[01], FP[41], FP[09], FP[49], FP[17], FP[57], FP[25] };
endmodule
|
/////////////////////////////////////////////////////////////////////
//// ////
//// KEY_SEL_Half ////
//// Select one of 16 sub-keys for round ////
//// ////
//// Author: Rudolf Usselmann ////
//// [email protected] ////
//// ////
//// Original: Rudolf Usselmann ////
//// ////
//// Modified : 2004/07/10 ////
//// Modified: Sakamoto YASUHIRO ////
//// Modified: for about Half slices decreased ////
//// (XILINX SPARTAN2 Number of SLICEs 546 to 258) ////
//// Web : http://hp.vector.co.jp/authors/VA014069 ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Rudolf Usselmann ////
//// [email protected] ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
module key_sel(K_sub, K, roundSel, decrypt);
output [1:48] K_sub;
input [55:0] K;
input [3:0] roundSel;
input decrypt;
reg [1:48] K_sub;
wire [1:48] K1, K2, K3, K4, K5, K6, K7, K8;
//// Modified: for about Half slices decreased
wire [2:0] roundSelH; // ADD Sakamoto
wire decryptH; // ADD Sakamoto
assign roundSelH[2:0] = roundSel[3] ? (~roundSel[2:0]) : roundSel[2:0];
assign decryptH = decrypt ^ roundSel[3];
always @(K1 or K2 or K3 or K4 or K5 or K6 or K7 or K8 or roundSelH)
case (roundSelH) // synopsys full_case parallel_case
0: K_sub = K1;
1: K_sub = K2;
2: K_sub = K3;
3: K_sub = K4;
4: K_sub = K5;
5: K_sub = K6;
6: K_sub = K7;
7: K_sub = K8;
endcase
assign K8[1] = decryptH ? K[6] : K[24];
assign K8[2] = decryptH ? K[27] : K[20];
assign K8[3] = decryptH ? K[10] : K[3] ;
assign K8[4] = decryptH ? K[19] : K[12];
assign K8[5] = decryptH ? K[54] : K[47];
assign K8[6] = decryptH ? K[25] : K[18];
assign K8[7] = decryptH ? K[11] : K[4] ;
assign K8[8] = decryptH ? K[47] : K[40];
assign K8[9] = decryptH ? K[13] : K[6] ;
assign K8[10] = decryptH ? K[32] : K[25];
assign K8[11] = decryptH ? K[55] : K[48];
assign K8[12] = decryptH ? K[3] : K[53];
assign K8[13] = decryptH ? K[12] : K[5] ;
assign K8[14] = decryptH ? K[41] : K[34];
assign K8[15] = decryptH ? K[17] : K[10];
assign K8[16] = decryptH ? K[18] : K[11];
assign K8[17] = decryptH ? K[33] : K[26];
assign K8[18] = decryptH ? K[46] : K[39];
assign K8[19] = decryptH ? K[20] : K[13];
assign K8[20] = decryptH ? K[39] : K[32];
assign K8[21] = decryptH ? K[40] : K[33];
assign K8[22] = decryptH ? K[48] : K[41];
assign K8[23] = decryptH ? K[24] : K[17];
assign K8[24] = decryptH ? K[4] : K[54];
assign K8[25] = decryptH ? K[52] : K[45];
assign K8[26] = decryptH ? K[15] : K[8] ;
assign K8[27] = decryptH ? K[9] : K[2] ;
assign K8[28] = decryptH ? K[51] : K[44];
assign K8[29] = decryptH ? K[35] : K[28];
assign K8[30] = decryptH ? K[36] : K[29];
assign K8[31] = decryptH ? K[2] : K[50];
assign K8[32] = decryptH ? K[45] : K[38];
assign K8[33] = decryptH ? K[8] : K[1] ;
assign K8[34] = decryptH ? K[21] : K[14];
assign K8[35] = decryptH ? K[23] : K[16];
assign K8[36] = decryptH ? K[42] : K[35];
assign K8[37] = decryptH ? K[14] : K[7] ;
assign K8[38] = decryptH ? K[49] : K[42];
assign K8[39] = decryptH ? K[38] : K[31];
assign K8[40] = decryptH ? K[43] : K[36];
assign K8[41] = decryptH ? K[30] : K[23];
assign K8[42] = decryptH ? K[22] : K[15];
assign K8[43] = decryptH ? K[28] : K[21];
assign K8[44] = decryptH ? K[0] : K[52];
assign K8[45] = decryptH ? K[1] : K[49];
assign K8[46] = decryptH ? K[44] : K[37];
assign K8[47] = decryptH ? K[50] : K[43];
assign K8[48] = decryptH ? K[16] : K[9] ;
assign K7[1] = decryptH ? K[20] : K[10];
assign K7[2] = decryptH ? K[41] : K[6] ;
assign K7[3] = decryptH ? K[24] : K[46];
assign K7[4] = decryptH ? K[33] : K[55];
assign K7[5] = decryptH ? K[11] : K[33];
assign K7[6] = decryptH ? K[39] : K[4] ;
assign K7[7] = decryptH ? K[25] : K[47];
assign K7[8] = decryptH ? K[4] : K[26];
assign K7[9] = decryptH ? K[27] : K[17];
assign K7[10] = decryptH ? K[46] : K[11];
assign K7[11] = decryptH ? K[12] : K[34];
assign K7[12] = decryptH ? K[17] : K[39];
assign K7[13] = decryptH ? K[26] : K[48];
assign K7[14] = decryptH ? K[55] : K[20];
assign K7[15] = decryptH ? K[6] : K[53];
assign K7[16] = decryptH ? K[32] : K[54];
assign K7[17] = decryptH ? K[47] : K[12];
assign K7[18] = decryptH ? K[3] : K[25];
assign K7[19] = decryptH ? K[34] : K[24];
assign K7[20] = decryptH ? K[53] : K[18];
assign K7[21] = decryptH ? K[54] : K[19];
assign K7[22] = decryptH ? K[5] : K[27];
assign K7[23] = decryptH ? K[13] : K[3] ;
assign K7[24] = decryptH ? K[18] : K[40];
assign K7[25] = decryptH ? K[7] : K[31];
assign K7[26] = decryptH ? K[29] : K[49];
assign K7[27] = decryptH ? K[23] : K[43];
assign K7[28] = decryptH ? K[38] : K[30];
assign K7[29] = decryptH ? K[49] : K[14];
assign K7[30] = decryptH ? K[50] : K[15];
assign K7[31] = decryptH ? K[16] : K[36];
assign K7[32] = decryptH ? K[0] : K[51];
assign K7[33] = decryptH ? K[22] : K[42];
assign K7[34] = decryptH ? K[35] : K[0] ;
assign K7[35] = decryptH ? K[37] : K[2] ;
assign K7[36] = decryptH ? K[1] : K[21];
assign K7[37] = decryptH ? K[28] : K[52];
assign K7[38] = decryptH ? K[8] : K[28];
assign K7[39] = decryptH ? K[52] : K[44];
assign K7[40] = decryptH ? K[2] : K[22];
assign K7[41] = decryptH ? K[44] : K[9] ;
assign K7[42] = decryptH ? K[36] : K[1] ;
assign K7[43] = decryptH ? K[42] : K[7] ;
assign K7[44] = decryptH ? K[14] : K[38];
assign K7[45] = decryptH ? K[15] : K[35];
assign K7[46] = decryptH ? K[31] : K[23];
assign K7[47] = decryptH ? K[9] : K[29];
assign K7[48] = decryptH ? K[30] : K[50];
assign K6[1] = decryptH ? K[34] : K[53];
assign K6[2] = decryptH ? K[55] : K[17];
assign K6[3] = decryptH ? K[13] : K[32];
assign K6[4] = decryptH ? K[47] : K[41];
assign K6[5] = decryptH ? K[25] : K[19];
assign K6[6] = decryptH ? K[53] : K[47];
assign K6[7] = decryptH ? K[39] : K[33];
assign K6[8] = decryptH ? K[18] : K[12];
assign K6[9] = decryptH ? K[41] : K[3] ;
assign K6[10] = decryptH ? K[3] : K[54];
assign K6[11] = decryptH ? K[26] : K[20];
assign K6[12] = decryptH ? K[6] : K[25];
assign K6[13] = decryptH ? K[40] : K[34];
assign K6[14] = decryptH ? K[12] : K[6] ;
assign K6[15] = decryptH ? K[20] : K[39];
assign K6[16] = decryptH ? K[46] : K[40];
assign K6[17] = decryptH ? K[4] : K[55];
assign K6[18] = decryptH ? K[17] : K[11];
assign K6[19] = decryptH ? K[48] : K[10];
assign K6[20] = decryptH ? K[10] : K[4] ;
assign K6[21] = decryptH ? K[11] : K[5] ;
assign K6[22] = decryptH ? K[19] : K[13];
assign K6[23] = decryptH ? K[27] : K[46];
assign K6[24] = decryptH ? K[32] : K[26];
assign K6[25] = decryptH ? K[21] : K[44];
assign K6[26] = decryptH ? K[43] : K[35];
assign K6[27] = decryptH ? K[37] : K[29];
assign K6[28] = decryptH ? K[52] : K[16];
assign K6[29] = decryptH ? K[8] : K[0] ;
assign K6[30] = decryptH ? K[9] : K[1] ;
assign K6[31] = decryptH ? K[30] : K[22];
assign K6[32] = decryptH ? K[14] : K[37];
assign K6[33] = decryptH ? K[36] : K[28];
assign K6[34] = decryptH ? K[49] : K[45];
assign K6[35] = decryptH ? K[51] : K[43];
assign K6[36] = decryptH ? K[15] : K[7] ;
assign K6[37] = decryptH ? K[42] : K[38];
assign K6[38] = decryptH ? K[22] : K[14];
assign K6[39] = decryptH ? K[7] : K[30];
assign K6[40] = decryptH ? K[16] : K[8] ;
assign K6[41] = decryptH ? K[31] : K[50];
assign K6[42] = decryptH ? K[50] : K[42];
assign K6[43] = decryptH ? K[1] : K[52];
assign K6[44] = decryptH ? K[28] : K[51];
assign K6[45] = decryptH ? K[29] : K[21];
assign K6[46] = decryptH ? K[45] : K[9] ;
assign K6[47] = decryptH ? K[23] : K[15];
assign K6[48] = decryptH ? K[44] : K[36];
assign K5[1] = decryptH ? K[48] : K[39];
assign K5[2] = decryptH ? K[12] : K[3] ;
assign K5[3] = decryptH ? K[27] : K[18];
assign K5[4] = decryptH ? K[4] : K[27];
assign K5[5] = decryptH ? K[39] : K[5] ;
assign K5[6] = decryptH ? K[10] : K[33];
assign K5[7] = decryptH ? K[53] : K[19];
assign K5[8] = decryptH ? K[32] : K[55];
assign K5[9] = decryptH ? K[55] : K[46];
assign K5[10] = decryptH ? K[17] : K[40];
assign K5[11] = decryptH ? K[40] : K[6] ;
assign K5[12] = decryptH ? K[20] : K[11];
assign K5[13] = decryptH ? K[54] : K[20];
assign K5[14] = decryptH ? K[26] : K[17];
assign K5[15] = decryptH ? K[34] : K[25];
assign K5[16] = decryptH ? K[3] : K[26];
assign K5[17] = decryptH ? K[18] : K[41];
assign K5[18] = decryptH ? K[6] : K[54];
assign K5[19] = decryptH ? K[5] : K[53];
assign K5[20] = decryptH ? K[24] : K[47];
assign K5[21] = decryptH ? K[25] : K[48];
assign K5[22] = decryptH ? K[33] : K[24];
assign K5[23] = decryptH ? K[41] : K[32];
assign K5[24] = decryptH ? K[46] : K[12];
assign K5[25] = decryptH ? K[35] : K[30];
assign K5[26] = decryptH ? K[2] : K[21];
assign K5[27] = decryptH ? K[51] : K[15];
assign K5[28] = decryptH ? K[7] : K[2] ;
assign K5[29] = decryptH ? K[22] : K[45];
assign K5[30] = decryptH ? K[23] : K[42];
assign K5[31] = decryptH ? K[44] : K[8] ;
assign K5[32] = decryptH ? K[28] : K[23];
assign K5[33] = decryptH ? K[50] : K[14];
assign K5[34] = decryptH ? K[8] : K[31];
assign K5[35] = decryptH ? K[38] : K[29];
assign K5[36] = decryptH ? K[29] : K[52];
assign K5[37] = decryptH ? K[1] : K[51];
assign K5[38] = decryptH ? K[36] : K[0] ;
assign K5[39] = decryptH ? K[21] : K[16];
assign K5[40] = decryptH ? K[30] : K[49];
assign K5[41] = decryptH ? K[45] : K[36];
assign K5[42] = decryptH ? K[9] : K[28];
assign K5[43] = decryptH ? K[15] : K[38];
assign K5[44] = decryptH ? K[42] : K[37];
assign K5[45] = decryptH ? K[43] : K[7] ;
assign K5[46] = decryptH ? K[0] : K[50];
assign K5[47] = decryptH ? K[37] : K[1] ;
assign K5[48] = decryptH ? K[31] : K[22];
assign K4[1] = decryptH ? K[5] : K[25];
assign K4[2] = decryptH ? K[26] : K[46];
assign K4[3] = decryptH ? K[41] : K[4] ;
assign K4[4] = decryptH ? K[18] : K[13];
assign K4[5] = decryptH ? K[53] : K[48];
assign K4[6] = decryptH ? K[24] : K[19];
assign K4[7] = decryptH ? K[10] : K[5] ;
assign K4[8] = decryptH ? K[46] : K[41];
assign K4[9] = decryptH ? K[12] : K[32];
assign K4[10] = decryptH ? K[6] : K[26];
assign K4[11] = decryptH ? K[54] : K[17];
assign K4[12] = decryptH ? K[34] : K[54];
assign K4[13] = decryptH ? K[11] : K[6] ;
assign K4[14] = decryptH ? K[40] : K[3] ;
assign K4[15] = decryptH ? K[48] : K[11];
assign K4[16] = decryptH ? K[17] : K[12];
assign K4[17] = decryptH ? K[32] : K[27];
assign K4[18] = decryptH ? K[20] : K[40];
assign K4[19] = decryptH ? K[19] : K[39];
assign K4[20] = decryptH ? K[13] : K[33];
assign K4[21] = decryptH ? K[39] : K[34];
assign K4[22] = decryptH ? K[47] : K[10];
assign K4[23] = decryptH ? K[55] : K[18];
assign K4[24] = decryptH ? K[3] : K[55];
assign K4[25] = decryptH ? K[49] : K[16];
assign K4[26] = decryptH ? K[16] : K[7] ;
assign K4[27] = decryptH ? K[38] : K[1] ;
assign K4[28] = decryptH ? K[21] : K[43];
assign K4[29] = decryptH ? K[36] : K[31];
assign K4[30] = decryptH ? K[37] : K[28];
assign K4[31] = decryptH ? K[31] : K[49];
assign K4[32] = decryptH ? K[42] : K[9] ;
assign K4[33] = decryptH ? K[9] : K[0] ;
assign K4[34] = decryptH ? K[22] : K[44];
assign K4[35] = decryptH ? K[52] : K[15];
assign K4[36] = decryptH ? K[43] : K[38];
assign K4[37] = decryptH ? K[15] : K[37];
assign K4[38] = decryptH ? K[50] : K[45];
assign K4[39] = decryptH ? K[35] : K[2] ;
assign K4[40] = decryptH ? K[44] : K[35];
assign K4[41] = decryptH ? K[0] : K[22];
assign K4[42] = decryptH ? K[23] : K[14];
assign K4[43] = decryptH ? K[29] : K[51];
assign K4[44] = decryptH ? K[1] : K[23];
assign K4[45] = decryptH ? K[2] : K[52];
assign K4[46] = decryptH ? K[14] : K[36];
assign K4[47] = decryptH ? K[51] : K[42];
assign K4[48] = decryptH ? K[45] : K[8] ;
assign K3[1] = decryptH ? K[19] : K[11];
assign K3[2] = decryptH ? K[40] : K[32];
assign K3[3] = decryptH ? K[55] : K[47];
assign K3[4] = decryptH ? K[32] : K[24];
assign K3[5] = decryptH ? K[10] : K[34];
assign K3[6] = decryptH ? K[13] : K[5] ;
assign K3[7] = decryptH ? K[24] : K[48];
assign K3[8] = decryptH ? K[3] : K[27];
assign K3[9] = decryptH ? K[26] : K[18];
assign K3[10] = decryptH ? K[20] : K[12];
assign K3[11] = decryptH ? K[11] : K[3] ;
assign K3[12] = decryptH ? K[48] : K[40];
assign K3[13] = decryptH ? K[25] : K[17];
assign K3[14] = decryptH ? K[54] : K[46];
assign K3[15] = decryptH ? K[5] : K[54];
assign K3[16] = decryptH ? K[6] : K[55];
assign K3[17] = decryptH ? K[46] : K[13];
assign K3[18] = decryptH ? K[34] : K[26];
assign K3[19] = decryptH ? K[33] : K[25];
assign K3[20] = decryptH ? K[27] : K[19];
assign K3[21] = decryptH ? K[53] : K[20];
assign K3[22] = decryptH ? K[4] : K[53];
assign K3[23] = decryptH ? K[12] : K[4] ;
assign K3[24] = decryptH ? K[17] : K[41];
assign K3[25] = decryptH ? K[8] : K[2] ;
assign K3[26] = decryptH ? K[30] : K[52];
assign K3[27] = decryptH ? K[52] : K[42];
assign K3[28] = decryptH ? K[35] : K[29];
assign K3[29] = decryptH ? K[50] : K[44];
assign K3[30] = decryptH ? K[51] : K[14];
assign K3[31] = decryptH ? K[45] : K[35];
assign K3[32] = decryptH ? K[1] : K[50];
assign K3[33] = decryptH ? K[23] : K[45];
assign K3[34] = decryptH ? K[36] : K[30];
assign K3[35] = decryptH ? K[7] : K[1] ;
assign K3[36] = decryptH ? K[2] : K[51];
assign K3[37] = decryptH ? K[29] : K[23];
assign K3[38] = decryptH ? K[9] : K[31];
assign K3[39] = decryptH ? K[49] : K[43];
assign K3[40] = decryptH ? K[31] : K[21];
assign K3[41] = decryptH ? K[14] : K[8] ;
assign K3[42] = decryptH ? K[37] : K[0] ;
assign K3[43] = decryptH ? K[43] : K[37];
assign K3[44] = decryptH ? K[15] : K[9] ;
assign K3[45] = decryptH ? K[16] : K[38];
assign K3[46] = decryptH ? K[28] : K[22];
assign K3[47] = decryptH ? K[38] : K[28];
assign K3[48] = decryptH ? K[0] : K[49];
assign K2[1] = decryptH ? K[33] : K[54];
assign K2[2] = decryptH ? K[54] : K[18];
assign K2[3] = decryptH ? K[12] : K[33];
assign K2[4] = decryptH ? K[46] : K[10];
assign K2[5] = decryptH ? K[24] : K[20];
assign K2[6] = decryptH ? K[27] : K[48];
assign K2[7] = decryptH ? K[13] : K[34];
assign K2[8] = decryptH ? K[17] : K[13];
assign K2[9] = decryptH ? K[40] : K[4] ;
assign K2[10] = decryptH ? K[34] : K[55];
assign K2[11] = decryptH ? K[25] : K[46];
assign K2[12] = decryptH ? K[5] : K[26];
assign K2[13] = decryptH ? K[39] : K[3] ;
assign K2[14] = decryptH ? K[11] : K[32];
assign K2[15] = decryptH ? K[19] : K[40];
assign K2[16] = decryptH ? K[20] : K[41];
assign K2[17] = decryptH ? K[3] : K[24];
assign K2[18] = decryptH ? K[48] : K[12];
assign K2[19] = decryptH ? K[47] : K[11];
assign K2[20] = decryptH ? K[41] : K[5] ;
assign K2[21] = decryptH ? K[10] : K[6] ;
assign K2[22] = decryptH ? K[18] : K[39];
assign K2[23] = decryptH ? K[26] : K[47];
assign K2[24] = decryptH ? K[6] : K[27];
assign K2[25] = decryptH ? K[22] : K[43];
assign K2[26] = decryptH ? K[44] : K[38];
assign K2[27] = decryptH ? K[7] : K[28];
assign K2[28] = decryptH ? K[49] : K[15];
assign K2[29] = decryptH ? K[9] : K[30];
assign K2[30] = decryptH ? K[38] : K[0] ;
assign K2[31] = decryptH ? K[0] : K[21];
assign K2[32] = decryptH ? K[15] : K[36];
assign K2[33] = decryptH ? K[37] : K[31];
assign K2[34] = decryptH ? K[50] : K[16];
assign K2[35] = decryptH ? K[21] : K[42];
assign K2[36] = decryptH ? K[16] : K[37];
assign K2[37] = decryptH ? K[43] : K[9] ;
assign K2[38] = decryptH ? K[23] : K[44];
assign K2[39] = decryptH ? K[8] : K[29];
assign K2[40] = decryptH ? K[45] : K[7] ;
assign K2[41] = decryptH ? K[28] : K[49];
assign K2[42] = decryptH ? K[51] : K[45];
assign K2[43] = decryptH ? K[2] : K[23];
assign K2[44] = decryptH ? K[29] : K[50];
assign K2[45] = decryptH ? K[30] : K[51];
assign K2[46] = decryptH ? K[42] : K[8] ;
assign K2[47] = decryptH ? K[52] : K[14];
assign K2[48] = decryptH ? K[14] : K[35];
assign K1[1] = decryptH ? K[40] : K[47];
assign K1[2] = decryptH ? K[4] : K[11];
assign K1[3] = decryptH ? K[19] : K[26];
assign K1[4] = decryptH ? K[53] : K[3] ;
assign K1[5] = decryptH ? K[6] : K[13];
assign K1[6] = decryptH ? K[34] : K[41];
assign K1[7] = decryptH ? K[20] : K[27];
assign K1[8] = decryptH ? K[24] : K[6] ;
assign K1[9] = decryptH ? K[47] : K[54];
assign K1[10] = decryptH ? K[41] : K[48];
assign K1[11] = decryptH ? K[32] : K[39];
assign K1[12] = decryptH ? K[12] : K[19];
assign K1[13] = decryptH ? K[46] : K[53];
assign K1[14] = decryptH ? K[18] : K[25];
assign K1[15] = decryptH ? K[26] : K[33];
assign K1[16] = decryptH ? K[27] : K[34];
assign K1[17] = decryptH ? K[10] : K[17];
assign K1[18] = decryptH ? K[55] : K[5] ;
assign K1[19] = decryptH ? K[54] : K[4] ;
assign K1[20] = decryptH ? K[48] : K[55];
assign K1[21] = decryptH ? K[17] : K[24];
assign K1[22] = decryptH ? K[25] : K[32];
assign K1[23] = decryptH ? K[33] : K[40];
assign K1[24] = decryptH ? K[13] : K[20];
assign K1[25] = decryptH ? K[29] : K[36];
assign K1[26] = decryptH ? K[51] : K[31];
assign K1[27] = decryptH ? K[14] : K[21];
assign K1[28] = decryptH ? K[1] : K[8] ;
assign K1[29] = decryptH ? K[16] : K[23];
assign K1[30] = decryptH ? K[45] : K[52];
assign K1[31] = decryptH ? K[7] : K[14];
assign K1[32] = decryptH ? K[22] : K[29];
assign K1[33] = decryptH ? K[44] : K[51];
assign K1[34] = decryptH ? K[2] : K[9] ;
assign K1[35] = decryptH ? K[28] : K[35];
assign K1[36] = decryptH ? K[23] : K[30];
assign K1[37] = decryptH ? K[50] : K[2] ;
assign K1[38] = decryptH ? K[30] : K[37];
assign K1[39] = decryptH ? K[15] : K[22];
assign K1[40] = decryptH ? K[52] : K[0] ;
assign K1[41] = decryptH ? K[35] : K[42];
assign K1[42] = decryptH ? K[31] : K[38];
assign K1[43] = decryptH ? K[9] : K[16];
assign K1[44] = decryptH ? K[36] : K[43];
assign K1[45] = decryptH ? K[37] : K[44];
assign K1[46] = decryptH ? K[49] : K[1] ;
assign K1[47] = decryptH ? K[0] : K[7] ;
assign K1[48] = decryptH ? K[21] : K[28];
endmodule
|
/////////////////////////////////////////////////////////////////////
//// ////
//// KEY_SEL ////
//// Select one of 16 sub-keys for round ////
//// ////
//// Author: Rudolf Usselmann ////
//// [email protected] ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Rudolf Usselmann ////
//// [email protected] ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
module key_sel3(K_sub, key1, key2, key3, roundSel, decrypt);
output [1:48] K_sub;
input [55:0] key1, key2, key3;
input [5:0] roundSel;
input decrypt;
wire decrypt_int;
reg [55:0] K;
reg [1:48] K_sub;
wire [1:48] K1, K2, K3, K4, K5, K6, K7, K8, K9;
wire [1:48] K10, K11, K12, K13, K14, K15, K16;
always @(roundSel or decrypt or key1 or key2 or key3)
case ({decrypt, roundSel[5:4]}) // synopsys full_case parallel_case
3'b0_00: K = key1;
3'b0_01: K = key2;
3'b0_10: K = key3;
3'b1_00: K = key3;
3'b1_01: K = key2;
3'b1_10: K = key1;
endcase
assign decrypt_int = (roundSel[5:4]==2'h1) ? !decrypt : decrypt;
always @(K1 or K2 or K3 or K4 or K5 or K6 or K7 or K8 or K9 or K10
or K11 or K12 or K13 or K14 or K15 or K16 or roundSel)
case(roundSel[3:0]) // synopsys full_case parallel_case
0: K_sub = K1;
1: K_sub = K2;
2: K_sub = K3;
3: K_sub = K4;
4: K_sub = K5;
5: K_sub = K6;
6: K_sub = K7;
7: K_sub = K8;
8: K_sub = K9;
9: K_sub = K10;
10: K_sub = K11;
11: K_sub = K12;
12: K_sub = K13;
13: K_sub = K14;
14: K_sub = K15;
15: K_sub = K16;
endcase
assign K16[1] = decrypt_int ? K[47] : K[40];
assign K16[2] = decrypt_int ? K[11] : K[4];
assign K16[3] = decrypt_int ? K[26] : K[19];
assign K16[4] = decrypt_int ? K[3] : K[53];
assign K16[5] = decrypt_int ? K[13] : K[6];
assign K16[6] = decrypt_int ? K[41] : K[34];
assign K16[7] = decrypt_int ? K[27] : K[20];
assign K16[8] = decrypt_int ? K[6] : K[24];
assign K16[9] = decrypt_int ? K[54] : K[47];
assign K16[10] = decrypt_int ? K[48] : K[41];
assign K16[11] = decrypt_int ? K[39] : K[32];
assign K16[12] = decrypt_int ? K[19] : K[12];
assign K16[13] = decrypt_int ? K[53] : K[46];
assign K16[14] = decrypt_int ? K[25] : K[18];
assign K16[15] = decrypt_int ? K[33] : K[26];
assign K16[16] = decrypt_int ? K[34] : K[27];
assign K16[17] = decrypt_int ? K[17] : K[10];
assign K16[18] = decrypt_int ? K[5] : K[55];
assign K16[19] = decrypt_int ? K[4] : K[54];
assign K16[20] = decrypt_int ? K[55] : K[48];
assign K16[21] = decrypt_int ? K[24] : K[17];
assign K16[22] = decrypt_int ? K[32] : K[25];
assign K16[23] = decrypt_int ? K[40] : K[33];
assign K16[24] = decrypt_int ? K[20] : K[13];
assign K16[25] = decrypt_int ? K[36] : K[29];
assign K16[26] = decrypt_int ? K[31] : K[51];
assign K16[27] = decrypt_int ? K[21] : K[14];
assign K16[28] = decrypt_int ? K[8] : K[1];
assign K16[29] = decrypt_int ? K[23] : K[16];
assign K16[30] = decrypt_int ? K[52] : K[45];
assign K16[31] = decrypt_int ? K[14] : K[7];
assign K16[32] = decrypt_int ? K[29] : K[22];
assign K16[33] = decrypt_int ? K[51] : K[44];
assign K16[34] = decrypt_int ? K[9] : K[2];
assign K16[35] = decrypt_int ? K[35] : K[28];
assign K16[36] = decrypt_int ? K[30] : K[23];
assign K16[37] = decrypt_int ? K[2] : K[50];
assign K16[38] = decrypt_int ? K[37] : K[30];
assign K16[39] = decrypt_int ? K[22] : K[15];
assign K16[40] = decrypt_int ? K[0] : K[52];
assign K16[41] = decrypt_int ? K[42] : K[35];
assign K16[42] = decrypt_int ? K[38] : K[31];
assign K16[43] = decrypt_int ? K[16] : K[9];
assign K16[44] = decrypt_int ? K[43] : K[36];
assign K16[45] = decrypt_int ? K[44] : K[37];
assign K16[46] = decrypt_int ? K[1] : K[49];
assign K16[47] = decrypt_int ? K[7] : K[0];
assign K16[48] = decrypt_int ? K[28] : K[21];
assign K15[1] = decrypt_int ? K[54] : K[33];
assign K15[2] = decrypt_int ? K[18] : K[54];
assign K15[3] = decrypt_int ? K[33] : K[12];
assign K15[4] = decrypt_int ? K[10] : K[46];
assign K15[5] = decrypt_int ? K[20] : K[24];
assign K15[6] = decrypt_int ? K[48] : K[27];
assign K15[7] = decrypt_int ? K[34] : K[13];
assign K15[8] = decrypt_int ? K[13] : K[17];
assign K15[9] = decrypt_int ? K[4] : K[40];
assign K15[10] = decrypt_int ? K[55] : K[34];
assign K15[11] = decrypt_int ? K[46] : K[25];
assign K15[12] = decrypt_int ? K[26] : K[5];
assign K15[13] = decrypt_int ? K[3] : K[39];
assign K15[14] = decrypt_int ? K[32] : K[11];
assign K15[15] = decrypt_int ? K[40] : K[19];
assign K15[16] = decrypt_int ? K[41] : K[20];
assign K15[17] = decrypt_int ? K[24] : K[3];
assign K15[18] = decrypt_int ? K[12] : K[48];
assign K15[19] = decrypt_int ? K[11] : K[47];
assign K15[20] = decrypt_int ? K[5] : K[41];
assign K15[21] = decrypt_int ? K[6] : K[10];
assign K15[22] = decrypt_int ? K[39] : K[18];
assign K15[23] = decrypt_int ? K[47] : K[26];
assign K15[24] = decrypt_int ? K[27] : K[6];
assign K15[25] = decrypt_int ? K[43] : K[22];
assign K15[26] = decrypt_int ? K[38] : K[44];
assign K15[27] = decrypt_int ? K[28] : K[7];
assign K15[28] = decrypt_int ? K[15] : K[49];
assign K15[29] = decrypt_int ? K[30] : K[9];
assign K15[30] = decrypt_int ? K[0] : K[38];
assign K15[31] = decrypt_int ? K[21] : K[0];
assign K15[32] = decrypt_int ? K[36] : K[15];
assign K15[33] = decrypt_int ? K[31] : K[37];
assign K15[34] = decrypt_int ? K[16] : K[50];
assign K15[35] = decrypt_int ? K[42] : K[21];
assign K15[36] = decrypt_int ? K[37] : K[16];
assign K15[37] = decrypt_int ? K[9] : K[43];
assign K15[38] = decrypt_int ? K[44] : K[23];
assign K15[39] = decrypt_int ? K[29] : K[8];
assign K15[40] = decrypt_int ? K[7] : K[45];
assign K15[41] = decrypt_int ? K[49] : K[28];
assign K15[42] = decrypt_int ? K[45] : K[51];
assign K15[43] = decrypt_int ? K[23] : K[2];
assign K15[44] = decrypt_int ? K[50] : K[29];
assign K15[45] = decrypt_int ? K[51] : K[30];
assign K15[46] = decrypt_int ? K[8] : K[42];
assign K15[47] = decrypt_int ? K[14] : K[52];
assign K15[48] = decrypt_int ? K[35] : K[14];
assign K14[1] = decrypt_int ? K[11] : K[19];
assign K14[2] = decrypt_int ? K[32] : K[40];
assign K14[3] = decrypt_int ? K[47] : K[55];
assign K14[4] = decrypt_int ? K[24] : K[32];
assign K14[5] = decrypt_int ? K[34] : K[10];
assign K14[6] = decrypt_int ? K[5] : K[13];
assign K14[7] = decrypt_int ? K[48] : K[24];
assign K14[8] = decrypt_int ? K[27] : K[3];
assign K14[9] = decrypt_int ? K[18] : K[26];
assign K14[10] = decrypt_int ? K[12] : K[20];
assign K14[11] = decrypt_int ? K[3] : K[11];
assign K14[12] = decrypt_int ? K[40] : K[48];
assign K14[13] = decrypt_int ? K[17] : K[25];
assign K14[14] = decrypt_int ? K[46] : K[54];
assign K14[15] = decrypt_int ? K[54] : K[5];
assign K14[16] = decrypt_int ? K[55] : K[6];
assign K14[17] = decrypt_int ? K[13] : K[46];
assign K14[18] = decrypt_int ? K[26] : K[34];
assign K14[19] = decrypt_int ? K[25] : K[33];
assign K14[20] = decrypt_int ? K[19] : K[27];
assign K14[21] = decrypt_int ? K[20] : K[53];
assign K14[22] = decrypt_int ? K[53] : K[4];
assign K14[23] = decrypt_int ? K[4] : K[12];
assign K14[24] = decrypt_int ? K[41] : K[17];
assign K14[25] = decrypt_int ? K[2] : K[8];
assign K14[26] = decrypt_int ? K[52] : K[30];
assign K14[27] = decrypt_int ? K[42] : K[52];
assign K14[28] = decrypt_int ? K[29] : K[35];
assign K14[29] = decrypt_int ? K[44] : K[50];
assign K14[30] = decrypt_int ? K[14] : K[51];
assign K14[31] = decrypt_int ? K[35] : K[45];
assign K14[32] = decrypt_int ? K[50] : K[1];
assign K14[33] = decrypt_int ? K[45] : K[23];
assign K14[34] = decrypt_int ? K[30] : K[36];
assign K14[35] = decrypt_int ? K[1] : K[7];
assign K14[36] = decrypt_int ? K[51] : K[2];
assign K14[37] = decrypt_int ? K[23] : K[29];
assign K14[38] = decrypt_int ? K[31] : K[9];
assign K14[39] = decrypt_int ? K[43] : K[49];
assign K14[40] = decrypt_int ? K[21] : K[31];
assign K14[41] = decrypt_int ? K[8] : K[14];
assign K14[42] = decrypt_int ? K[0] : K[37];
assign K14[43] = decrypt_int ? K[37] : K[43];
assign K14[44] = decrypt_int ? K[9] : K[15];
assign K14[45] = decrypt_int ? K[38] : K[16];
assign K14[46] = decrypt_int ? K[22] : K[28];
assign K14[47] = decrypt_int ? K[28] : K[38];
assign K14[48] = decrypt_int ? K[49] : K[0];
assign K13[1] = decrypt_int ? K[25] : K[5];
assign K13[2] = decrypt_int ? K[46] : K[26];
assign K13[3] = decrypt_int ? K[4] : K[41];
assign K13[4] = decrypt_int ? K[13] : K[18];
assign K13[5] = decrypt_int ? K[48] : K[53];
assign K13[6] = decrypt_int ? K[19] : K[24];
assign K13[7] = decrypt_int ? K[5] : K[10];
assign K13[8] = decrypt_int ? K[41] : K[46];
assign K13[9] = decrypt_int ? K[32] : K[12];
assign K13[10] = decrypt_int ? K[26] : K[6];
assign K13[11] = decrypt_int ? K[17] : K[54];
assign K13[12] = decrypt_int ? K[54] : K[34];
assign K13[13] = decrypt_int ? K[6] : K[11];
assign K13[14] = decrypt_int ? K[3] : K[40];
assign K13[15] = decrypt_int ? K[11] : K[48];
assign K13[16] = decrypt_int ? K[12] : K[17];
assign K13[17] = decrypt_int ? K[27] : K[32];
assign K13[18] = decrypt_int ? K[40] : K[20];
assign K13[19] = decrypt_int ? K[39] : K[19];
assign K13[20] = decrypt_int ? K[33] : K[13];
assign K13[21] = decrypt_int ? K[34] : K[39];
assign K13[22] = decrypt_int ? K[10] : K[47];
assign K13[23] = decrypt_int ? K[18] : K[55];
assign K13[24] = decrypt_int ? K[55] : K[3];
assign K13[25] = decrypt_int ? K[16] : K[49];
assign K13[26] = decrypt_int ? K[7] : K[16];
assign K13[27] = decrypt_int ? K[1] : K[38];
assign K13[28] = decrypt_int ? K[43] : K[21];
assign K13[29] = decrypt_int ? K[31] : K[36];
assign K13[30] = decrypt_int ? K[28] : K[37];
assign K13[31] = decrypt_int ? K[49] : K[31];
assign K13[32] = decrypt_int ? K[9] : K[42];
assign K13[33] = decrypt_int ? K[0] : K[9];
assign K13[34] = decrypt_int ? K[44] : K[22];
assign K13[35] = decrypt_int ? K[15] : K[52];
assign K13[36] = decrypt_int ? K[38] : K[43];
assign K13[37] = decrypt_int ? K[37] : K[15];
assign K13[38] = decrypt_int ? K[45] : K[50];
assign K13[39] = decrypt_int ? K[2] : K[35];
assign K13[40] = decrypt_int ? K[35] : K[44];
assign K13[41] = decrypt_int ? K[22] : K[0];
assign K13[42] = decrypt_int ? K[14] : K[23];
assign K13[43] = decrypt_int ? K[51] : K[29];
assign K13[44] = decrypt_int ? K[23] : K[1];
assign K13[45] = decrypt_int ? K[52] : K[2];
assign K13[46] = decrypt_int ? K[36] : K[14];
assign K13[47] = decrypt_int ? K[42] : K[51];
assign K13[48] = decrypt_int ? K[8] : K[45];
assign K12[1] = decrypt_int ? K[39] : K[48];
assign K12[2] = decrypt_int ? K[3] : K[12];
assign K12[3] = decrypt_int ? K[18] : K[27];
assign K12[4] = decrypt_int ? K[27] : K[4];
assign K12[5] = decrypt_int ? K[5] : K[39];
assign K12[6] = decrypt_int ? K[33] : K[10];
assign K12[7] = decrypt_int ? K[19] : K[53];
assign K12[8] = decrypt_int ? K[55] : K[32];
assign K12[9] = decrypt_int ? K[46] : K[55];
assign K12[10] = decrypt_int ? K[40] : K[17];
assign K12[11] = decrypt_int ? K[6] : K[40];
assign K12[12] = decrypt_int ? K[11] : K[20];
assign K12[13] = decrypt_int ? K[20] : K[54];
assign K12[14] = decrypt_int ? K[17] : K[26];
assign K12[15] = decrypt_int ? K[25] : K[34];
assign K12[16] = decrypt_int ? K[26] : K[3];
assign K12[17] = decrypt_int ? K[41] : K[18];
assign K12[18] = decrypt_int ? K[54] : K[6];
assign K12[19] = decrypt_int ? K[53] : K[5];
assign K12[20] = decrypt_int ? K[47] : K[24];
assign K12[21] = decrypt_int ? K[48] : K[25];
assign K12[22] = decrypt_int ? K[24] : K[33];
assign K12[23] = decrypt_int ? K[32] : K[41];
assign K12[24] = decrypt_int ? K[12] : K[46];
assign K12[25] = decrypt_int ? K[30] : K[35];
assign K12[26] = decrypt_int ? K[21] : K[2];
assign K12[27] = decrypt_int ? K[15] : K[51];
assign K12[28] = decrypt_int ? K[2] : K[7];
assign K12[29] = decrypt_int ? K[45] : K[22];
assign K12[30] = decrypt_int ? K[42] : K[23];
assign K12[31] = decrypt_int ? K[8] : K[44];
assign K12[32] = decrypt_int ? K[23] : K[28];
assign K12[33] = decrypt_int ? K[14] : K[50];
assign K12[34] = decrypt_int ? K[31] : K[8];
assign K12[35] = decrypt_int ? K[29] : K[38];
assign K12[36] = decrypt_int ? K[52] : K[29];
assign K12[37] = decrypt_int ? K[51] : K[1];
assign K12[38] = decrypt_int ? K[0] : K[36];
assign K12[39] = decrypt_int ? K[16] : K[21];
assign K12[40] = decrypt_int ? K[49] : K[30];
assign K12[41] = decrypt_int ? K[36] : K[45];
assign K12[42] = decrypt_int ? K[28] : K[9];
assign K12[43] = decrypt_int ? K[38] : K[15];
assign K12[44] = decrypt_int ? K[37] : K[42];
assign K12[45] = decrypt_int ? K[7] : K[43];
assign K12[46] = decrypt_int ? K[50] : K[0];
assign K12[47] = decrypt_int ? K[1] : K[37];
assign K12[48] = decrypt_int ? K[22] : K[31];
assign K11[1] = decrypt_int ? K[53] : K[34];
assign K11[2] = decrypt_int ? K[17] : K[55];
assign K11[3] = decrypt_int ? K[32] : K[13];
assign K11[4] = decrypt_int ? K[41] : K[47];
assign K11[5] = decrypt_int ? K[19] : K[25];
assign K11[6] = decrypt_int ? K[47] : K[53];
assign K11[7] = decrypt_int ? K[33] : K[39];
assign K11[8] = decrypt_int ? K[12] : K[18];
assign K11[9] = decrypt_int ? K[3] : K[41];
assign K11[10] = decrypt_int ? K[54] : K[3];
assign K11[11] = decrypt_int ? K[20] : K[26];
assign K11[12] = decrypt_int ? K[25] : K[6];
assign K11[13] = decrypt_int ? K[34] : K[40];
assign K11[14] = decrypt_int ? K[6] : K[12];
assign K11[15] = decrypt_int ? K[39] : K[20];
assign K11[16] = decrypt_int ? K[40] : K[46];
assign K11[17] = decrypt_int ? K[55] : K[4];
assign K11[18] = decrypt_int ? K[11] : K[17];
assign K11[19] = decrypt_int ? K[10] : K[48];
assign K11[20] = decrypt_int ? K[4] : K[10];
assign K11[21] = decrypt_int ? K[5] : K[11];
assign K11[22] = decrypt_int ? K[13] : K[19];
assign K11[23] = decrypt_int ? K[46] : K[27];
assign K11[24] = decrypt_int ? K[26] : K[32];
assign K11[25] = decrypt_int ? K[44] : K[21];
assign K11[26] = decrypt_int ? K[35] : K[43];
assign K11[27] = decrypt_int ? K[29] : K[37];
assign K11[28] = decrypt_int ? K[16] : K[52];
assign K11[29] = decrypt_int ? K[0] : K[8];
assign K11[30] = decrypt_int ? K[1] : K[9];
assign K11[31] = decrypt_int ? K[22] : K[30];
assign K11[32] = decrypt_int ? K[37] : K[14];
assign K11[33] = decrypt_int ? K[28] : K[36];
assign K11[34] = decrypt_int ? K[45] : K[49];
assign K11[35] = decrypt_int ? K[43] : K[51];
assign K11[36] = decrypt_int ? K[7] : K[15];
assign K11[37] = decrypt_int ? K[38] : K[42];
assign K11[38] = decrypt_int ? K[14] : K[22];
assign K11[39] = decrypt_int ? K[30] : K[7];
assign K11[40] = decrypt_int ? K[8] : K[16];
assign K11[41] = decrypt_int ? K[50] : K[31];
assign K11[42] = decrypt_int ? K[42] : K[50];
assign K11[43] = decrypt_int ? K[52] : K[1];
assign K11[44] = decrypt_int ? K[51] : K[28];
assign K11[45] = decrypt_int ? K[21] : K[29];
assign K11[46] = decrypt_int ? K[9] : K[45];
assign K11[47] = decrypt_int ? K[15] : K[23];
assign K11[48] = decrypt_int ? K[36] : K[44];
assign K10[1] = decrypt_int ? K[10] : K[20];
assign K10[2] = decrypt_int ? K[6] : K[41];
assign K10[3] = decrypt_int ? K[46] : K[24];
assign K10[4] = decrypt_int ? K[55] : K[33];
assign K10[5] = decrypt_int ? K[33] : K[11];
assign K10[6] = decrypt_int ? K[4] : K[39];
assign K10[7] = decrypt_int ? K[47] : K[25];
assign K10[8] = decrypt_int ? K[26] : K[4];
assign K10[9] = decrypt_int ? K[17] : K[27];
assign K10[10] = decrypt_int ? K[11] : K[46];
assign K10[11] = decrypt_int ? K[34] : K[12];
assign K10[12] = decrypt_int ? K[39] : K[17];
assign K10[13] = decrypt_int ? K[48] : K[26];
assign K10[14] = decrypt_int ? K[20] : K[55];
assign K10[15] = decrypt_int ? K[53] : K[6];
assign K10[16] = decrypt_int ? K[54] : K[32];
assign K10[17] = decrypt_int ? K[12] : K[47];
assign K10[18] = decrypt_int ? K[25] : K[3];
assign K10[19] = decrypt_int ? K[24] : K[34];
assign K10[20] = decrypt_int ? K[18] : K[53];
assign K10[21] = decrypt_int ? K[19] : K[54];
assign K10[22] = decrypt_int ? K[27] : K[5];
assign K10[23] = decrypt_int ? K[3] : K[13];
assign K10[24] = decrypt_int ? K[40] : K[18];
assign K10[25] = decrypt_int ? K[31] : K[7];
assign K10[26] = decrypt_int ? K[49] : K[29];
assign K10[27] = decrypt_int ? K[43] : K[23];
assign K10[28] = decrypt_int ? K[30] : K[38];
assign K10[29] = decrypt_int ? K[14] : K[49];
assign K10[30] = decrypt_int ? K[15] : K[50];
assign K10[31] = decrypt_int ? K[36] : K[16];
assign K10[32] = decrypt_int ? K[51] : K[0];
assign K10[33] = decrypt_int ? K[42] : K[22];
assign K10[34] = decrypt_int ? K[0] : K[35];
assign K10[35] = decrypt_int ? K[2] : K[37];
assign K10[36] = decrypt_int ? K[21] : K[1];
assign K10[37] = decrypt_int ? K[52] : K[28];
assign K10[38] = decrypt_int ? K[28] : K[8];
assign K10[39] = decrypt_int ? K[44] : K[52];
assign K10[40] = decrypt_int ? K[22] : K[2];
assign K10[41] = decrypt_int ? K[9] : K[44];
assign K10[42] = decrypt_int ? K[1] : K[36];
assign K10[43] = decrypt_int ? K[7] : K[42];
assign K10[44] = decrypt_int ? K[38] : K[14];
assign K10[45] = decrypt_int ? K[35] : K[15];
assign K10[46] = decrypt_int ? K[23] : K[31];
assign K10[47] = decrypt_int ? K[29] : K[9];
assign K10[48] = decrypt_int ? K[50] : K[30];
assign K9[1] = decrypt_int ? K[24] : K[6];
assign K9[2] = decrypt_int ? K[20] : K[27];
assign K9[3] = decrypt_int ? K[3] : K[10];
assign K9[4] = decrypt_int ? K[12] : K[19];
assign K9[5] = decrypt_int ? K[47] : K[54];
assign K9[6] = decrypt_int ? K[18] : K[25];
assign K9[7] = decrypt_int ? K[4] : K[11];
assign K9[8] = decrypt_int ? K[40] : K[47];
assign K9[9] = decrypt_int ? K[6] : K[13];
assign K9[10] = decrypt_int ? K[25] : K[32];
assign K9[11] = decrypt_int ? K[48] : K[55];
assign K9[12] = decrypt_int ? K[53] : K[3];
assign K9[13] = decrypt_int ? K[5] : K[12];
assign K9[14] = decrypt_int ? K[34] : K[41];
assign K9[15] = decrypt_int ? K[10] : K[17];
assign K9[16] = decrypt_int ? K[11] : K[18];
assign K9[17] = decrypt_int ? K[26] : K[33];
assign K9[18] = decrypt_int ? K[39] : K[46];
assign K9[19] = decrypt_int ? K[13] : K[20];
assign K9[20] = decrypt_int ? K[32] : K[39];
assign K9[21] = decrypt_int ? K[33] : K[40];
assign K9[22] = decrypt_int ? K[41] : K[48];
assign K9[23] = decrypt_int ? K[17] : K[24];
assign K9[24] = decrypt_int ? K[54] : K[4];
assign K9[25] = decrypt_int ? K[45] : K[52];
assign K9[26] = decrypt_int ? K[8] : K[15];
assign K9[27] = decrypt_int ? K[2] : K[9];
assign K9[28] = decrypt_int ? K[44] : K[51];
assign K9[29] = decrypt_int ? K[28] : K[35];
assign K9[30] = decrypt_int ? K[29] : K[36];
assign K9[31] = decrypt_int ? K[50] : K[2];
assign K9[32] = decrypt_int ? K[38] : K[45];
assign K9[33] = decrypt_int ? K[1] : K[8];
assign K9[34] = decrypt_int ? K[14] : K[21];
assign K9[35] = decrypt_int ? K[16] : K[23];
assign K9[36] = decrypt_int ? K[35] : K[42];
assign K9[37] = decrypt_int ? K[7] : K[14];
assign K9[38] = decrypt_int ? K[42] : K[49];
assign K9[39] = decrypt_int ? K[31] : K[38];
assign K9[40] = decrypt_int ? K[36] : K[43];
assign K9[41] = decrypt_int ? K[23] : K[30];
assign K9[42] = decrypt_int ? K[15] : K[22];
assign K9[43] = decrypt_int ? K[21] : K[28];
assign K9[44] = decrypt_int ? K[52] : K[0];
assign K9[45] = decrypt_int ? K[49] : K[1];
assign K9[46] = decrypt_int ? K[37] : K[44];
assign K9[47] = decrypt_int ? K[43] : K[50];
assign K9[48] = decrypt_int ? K[9] : K[16];
assign K8[1] = decrypt_int ? K[6] : K[24];
assign K8[2] = decrypt_int ? K[27] : K[20];
assign K8[3] = decrypt_int ? K[10] : K[3];
assign K8[4] = decrypt_int ? K[19] : K[12];
assign K8[5] = decrypt_int ? K[54] : K[47];
assign K8[6] = decrypt_int ? K[25] : K[18];
assign K8[7] = decrypt_int ? K[11] : K[4];
assign K8[8] = decrypt_int ? K[47] : K[40];
assign K8[9] = decrypt_int ? K[13] : K[6];
assign K8[10] = decrypt_int ? K[32] : K[25];
assign K8[11] = decrypt_int ? K[55] : K[48];
assign K8[12] = decrypt_int ? K[3] : K[53];
assign K8[13] = decrypt_int ? K[12] : K[5];
assign K8[14] = decrypt_int ? K[41] : K[34];
assign K8[15] = decrypt_int ? K[17] : K[10];
assign K8[16] = decrypt_int ? K[18] : K[11];
assign K8[17] = decrypt_int ? K[33] : K[26];
assign K8[18] = decrypt_int ? K[46] : K[39];
assign K8[19] = decrypt_int ? K[20] : K[13];
assign K8[20] = decrypt_int ? K[39] : K[32];
assign K8[21] = decrypt_int ? K[40] : K[33];
assign K8[22] = decrypt_int ? K[48] : K[41];
assign K8[23] = decrypt_int ? K[24] : K[17];
assign K8[24] = decrypt_int ? K[4] : K[54];
assign K8[25] = decrypt_int ? K[52] : K[45];
assign K8[26] = decrypt_int ? K[15] : K[8];
assign K8[27] = decrypt_int ? K[9] : K[2];
assign K8[28] = decrypt_int ? K[51] : K[44];
assign K8[29] = decrypt_int ? K[35] : K[28];
assign K8[30] = decrypt_int ? K[36] : K[29];
assign K8[31] = decrypt_int ? K[2] : K[50];
assign K8[32] = decrypt_int ? K[45] : K[38];
assign K8[33] = decrypt_int ? K[8] : K[1];
assign K8[34] = decrypt_int ? K[21] : K[14];
assign K8[35] = decrypt_int ? K[23] : K[16];
assign K8[36] = decrypt_int ? K[42] : K[35];
assign K8[37] = decrypt_int ? K[14] : K[7];
assign K8[38] = decrypt_int ? K[49] : K[42];
assign K8[39] = decrypt_int ? K[38] : K[31];
assign K8[40] = decrypt_int ? K[43] : K[36];
assign K8[41] = decrypt_int ? K[30] : K[23];
assign K8[42] = decrypt_int ? K[22] : K[15];
assign K8[43] = decrypt_int ? K[28] : K[21];
assign K8[44] = decrypt_int ? K[0] : K[52];
assign K8[45] = decrypt_int ? K[1] : K[49];
assign K8[46] = decrypt_int ? K[44] : K[37];
assign K8[47] = decrypt_int ? K[50] : K[43];
assign K8[48] = decrypt_int ? K[16] : K[9];
assign K7[1] = decrypt_int ? K[20] : K[10];
assign K7[2] = decrypt_int ? K[41] : K[6];
assign K7[3] = decrypt_int ? K[24] : K[46];
assign K7[4] = decrypt_int ? K[33] : K[55];
assign K7[5] = decrypt_int ? K[11] : K[33];
assign K7[6] = decrypt_int ? K[39] : K[4];
assign K7[7] = decrypt_int ? K[25] : K[47];
assign K7[8] = decrypt_int ? K[4] : K[26];
assign K7[9] = decrypt_int ? K[27] : K[17];
assign K7[10] = decrypt_int ? K[46] : K[11];
assign K7[11] = decrypt_int ? K[12] : K[34];
assign K7[12] = decrypt_int ? K[17] : K[39];
assign K7[13] = decrypt_int ? K[26] : K[48];
assign K7[14] = decrypt_int ? K[55] : K[20];
assign K7[15] = decrypt_int ? K[6] : K[53];
assign K7[16] = decrypt_int ? K[32] : K[54];
assign K7[17] = decrypt_int ? K[47] : K[12];
assign K7[18] = decrypt_int ? K[3] : K[25];
assign K7[19] = decrypt_int ? K[34] : K[24];
assign K7[20] = decrypt_int ? K[53] : K[18];
assign K7[21] = decrypt_int ? K[54] : K[19];
assign K7[22] = decrypt_int ? K[5] : K[27];
assign K7[23] = decrypt_int ? K[13] : K[3];
assign K7[24] = decrypt_int ? K[18] : K[40];
assign K7[25] = decrypt_int ? K[7] : K[31];
assign K7[26] = decrypt_int ? K[29] : K[49];
assign K7[27] = decrypt_int ? K[23] : K[43];
assign K7[28] = decrypt_int ? K[38] : K[30];
assign K7[29] = decrypt_int ? K[49] : K[14];
assign K7[30] = decrypt_int ? K[50] : K[15];
assign K7[31] = decrypt_int ? K[16] : K[36];
assign K7[32] = decrypt_int ? K[0] : K[51];
assign K7[33] = decrypt_int ? K[22] : K[42];
assign K7[34] = decrypt_int ? K[35] : K[0];
assign K7[35] = decrypt_int ? K[37] : K[2];
assign K7[36] = decrypt_int ? K[1] : K[21];
assign K7[37] = decrypt_int ? K[28] : K[52];
assign K7[38] = decrypt_int ? K[8] : K[28];
assign K7[39] = decrypt_int ? K[52] : K[44];
assign K7[40] = decrypt_int ? K[2] : K[22];
assign K7[41] = decrypt_int ? K[44] : K[9];
assign K7[42] = decrypt_int ? K[36] : K[1];
assign K7[43] = decrypt_int ? K[42] : K[7];
assign K7[44] = decrypt_int ? K[14] : K[38];
assign K7[45] = decrypt_int ? K[15] : K[35];
assign K7[46] = decrypt_int ? K[31] : K[23];
assign K7[47] = decrypt_int ? K[9] : K[29];
assign K7[48] = decrypt_int ? K[30] : K[50];
assign K6[1] = decrypt_int ? K[34] : K[53];
assign K6[2] = decrypt_int ? K[55] : K[17];
assign K6[3] = decrypt_int ? K[13] : K[32];
assign K6[4] = decrypt_int ? K[47] : K[41];
assign K6[5] = decrypt_int ? K[25] : K[19];
assign K6[6] = decrypt_int ? K[53] : K[47];
assign K6[7] = decrypt_int ? K[39] : K[33];
assign K6[8] = decrypt_int ? K[18] : K[12];
assign K6[9] = decrypt_int ? K[41] : K[3];
assign K6[10] = decrypt_int ? K[3] : K[54];
assign K6[11] = decrypt_int ? K[26] : K[20];
assign K6[12] = decrypt_int ? K[6] : K[25];
assign K6[13] = decrypt_int ? K[40] : K[34];
assign K6[14] = decrypt_int ? K[12] : K[6];
assign K6[15] = decrypt_int ? K[20] : K[39];
assign K6[16] = decrypt_int ? K[46] : K[40];
assign K6[17] = decrypt_int ? K[4] : K[55];
assign K6[18] = decrypt_int ? K[17] : K[11];
assign K6[19] = decrypt_int ? K[48] : K[10];
assign K6[20] = decrypt_int ? K[10] : K[4];
assign K6[21] = decrypt_int ? K[11] : K[5];
assign K6[22] = decrypt_int ? K[19] : K[13];
assign K6[23] = decrypt_int ? K[27] : K[46];
assign K6[24] = decrypt_int ? K[32] : K[26];
assign K6[25] = decrypt_int ? K[21] : K[44];
assign K6[26] = decrypt_int ? K[43] : K[35];
assign K6[27] = decrypt_int ? K[37] : K[29];
assign K6[28] = decrypt_int ? K[52] : K[16];
assign K6[29] = decrypt_int ? K[8] : K[0];
assign K6[30] = decrypt_int ? K[9] : K[1];
assign K6[31] = decrypt_int ? K[30] : K[22];
assign K6[32] = decrypt_int ? K[14] : K[37];
assign K6[33] = decrypt_int ? K[36] : K[28];
assign K6[34] = decrypt_int ? K[49] : K[45];
assign K6[35] = decrypt_int ? K[51] : K[43];
assign K6[36] = decrypt_int ? K[15] : K[7];
assign K6[37] = decrypt_int ? K[42] : K[38];
assign K6[38] = decrypt_int ? K[22] : K[14];
assign K6[39] = decrypt_int ? K[7] : K[30];
assign K6[40] = decrypt_int ? K[16] : K[8];
assign K6[41] = decrypt_int ? K[31] : K[50];
assign K6[42] = decrypt_int ? K[50] : K[42];
assign K6[43] = decrypt_int ? K[1] : K[52];
assign K6[44] = decrypt_int ? K[28] : K[51];
assign K6[45] = decrypt_int ? K[29] : K[21];
assign K6[46] = decrypt_int ? K[45] : K[9];
assign K6[47] = decrypt_int ? K[23] : K[15];
assign K6[48] = decrypt_int ? K[44] : K[36];
assign K5[1] = decrypt_int ? K[48] : K[39];
assign K5[2] = decrypt_int ? K[12] : K[3];
assign K5[3] = decrypt_int ? K[27] : K[18];
assign K5[4] = decrypt_int ? K[4] : K[27];
assign K5[5] = decrypt_int ? K[39] : K[5];
assign K5[6] = decrypt_int ? K[10] : K[33];
assign K5[7] = decrypt_int ? K[53] : K[19];
assign K5[8] = decrypt_int ? K[32] : K[55];
assign K5[9] = decrypt_int ? K[55] : K[46];
assign K5[10] = decrypt_int ? K[17] : K[40];
assign K5[11] = decrypt_int ? K[40] : K[6];
assign K5[12] = decrypt_int ? K[20] : K[11];
assign K5[13] = decrypt_int ? K[54] : K[20];
assign K5[14] = decrypt_int ? K[26] : K[17];
assign K5[15] = decrypt_int ? K[34] : K[25];
assign K5[16] = decrypt_int ? K[3] : K[26];
assign K5[17] = decrypt_int ? K[18] : K[41];
assign K5[18] = decrypt_int ? K[6] : K[54];
assign K5[19] = decrypt_int ? K[5] : K[53];
assign K5[20] = decrypt_int ? K[24] : K[47];
assign K5[21] = decrypt_int ? K[25] : K[48];
assign K5[22] = decrypt_int ? K[33] : K[24];
assign K5[23] = decrypt_int ? K[41] : K[32];
assign K5[24] = decrypt_int ? K[46] : K[12];
assign K5[25] = decrypt_int ? K[35] : K[30];
assign K5[26] = decrypt_int ? K[2] : K[21];
assign K5[27] = decrypt_int ? K[51] : K[15];
assign K5[28] = decrypt_int ? K[7] : K[2];
assign K5[29] = decrypt_int ? K[22] : K[45];
assign K5[30] = decrypt_int ? K[23] : K[42];
assign K5[31] = decrypt_int ? K[44] : K[8];
assign K5[32] = decrypt_int ? K[28] : K[23];
assign K5[33] = decrypt_int ? K[50] : K[14];
assign K5[34] = decrypt_int ? K[8] : K[31];
assign K5[35] = decrypt_int ? K[38] : K[29];
assign K5[36] = decrypt_int ? K[29] : K[52];
assign K5[37] = decrypt_int ? K[1] : K[51];
assign K5[38] = decrypt_int ? K[36] : K[0];
assign K5[39] = decrypt_int ? K[21] : K[16];
assign K5[40] = decrypt_int ? K[30] : K[49];
assign K5[41] = decrypt_int ? K[45] : K[36];
assign K5[42] = decrypt_int ? K[9] : K[28];
assign K5[43] = decrypt_int ? K[15] : K[38];
assign K5[44] = decrypt_int ? K[42] : K[37];
assign K5[45] = decrypt_int ? K[43] : K[7];
assign K5[46] = decrypt_int ? K[0] : K[50];
assign K5[47] = decrypt_int ? K[37] : K[1];
assign K5[48] = decrypt_int ? K[31] : K[22];
assign K4[1] = decrypt_int ? K[5] : K[25];
assign K4[2] = decrypt_int ? K[26] : K[46];
assign K4[3] = decrypt_int ? K[41] : K[4];
assign K4[4] = decrypt_int ? K[18] : K[13];
assign K4[5] = decrypt_int ? K[53] : K[48];
assign K4[6] = decrypt_int ? K[24] : K[19];
assign K4[7] = decrypt_int ? K[10] : K[5];
assign K4[8] = decrypt_int ? K[46] : K[41];
assign K4[9] = decrypt_int ? K[12] : K[32];
assign K4[10] = decrypt_int ? K[6] : K[26];
assign K4[11] = decrypt_int ? K[54] : K[17];
assign K4[12] = decrypt_int ? K[34] : K[54];
assign K4[13] = decrypt_int ? K[11] : K[6];
assign K4[14] = decrypt_int ? K[40] : K[3];
assign K4[15] = decrypt_int ? K[48] : K[11];
assign K4[16] = decrypt_int ? K[17] : K[12];
assign K4[17] = decrypt_int ? K[32] : K[27];
assign K4[18] = decrypt_int ? K[20] : K[40];
assign K4[19] = decrypt_int ? K[19] : K[39];
assign K4[20] = decrypt_int ? K[13] : K[33];
assign K4[21] = decrypt_int ? K[39] : K[34];
assign K4[22] = decrypt_int ? K[47] : K[10];
assign K4[23] = decrypt_int ? K[55] : K[18];
assign K4[24] = decrypt_int ? K[3] : K[55];
assign K4[25] = decrypt_int ? K[49] : K[16];
assign K4[26] = decrypt_int ? K[16] : K[7];
assign K4[27] = decrypt_int ? K[38] : K[1];
assign K4[28] = decrypt_int ? K[21] : K[43];
assign K4[29] = decrypt_int ? K[36] : K[31];
assign K4[30] = decrypt_int ? K[37] : K[28];
assign K4[31] = decrypt_int ? K[31] : K[49];
assign K4[32] = decrypt_int ? K[42] : K[9];
assign K4[33] = decrypt_int ? K[9] : K[0];
assign K4[34] = decrypt_int ? K[22] : K[44];
assign K4[35] = decrypt_int ? K[52] : K[15];
assign K4[36] = decrypt_int ? K[43] : K[38];
assign K4[37] = decrypt_int ? K[15] : K[37];
assign K4[38] = decrypt_int ? K[50] : K[45];
assign K4[39] = decrypt_int ? K[35] : K[2];
assign K4[40] = decrypt_int ? K[44] : K[35];
assign K4[41] = decrypt_int ? K[0] : K[22];
assign K4[42] = decrypt_int ? K[23] : K[14];
assign K4[43] = decrypt_int ? K[29] : K[51];
assign K4[44] = decrypt_int ? K[1] : K[23];
assign K4[45] = decrypt_int ? K[2] : K[52];
assign K4[46] = decrypt_int ? K[14] : K[36];
assign K4[47] = decrypt_int ? K[51] : K[42];
assign K4[48] = decrypt_int ? K[45] : K[8];
assign K3[1] = decrypt_int ? K[19] : K[11];
assign K3[2] = decrypt_int ? K[40] : K[32];
assign K3[3] = decrypt_int ? K[55] : K[47];
assign K3[4] = decrypt_int ? K[32] : K[24];
assign K3[5] = decrypt_int ? K[10] : K[34];
assign K3[6] = decrypt_int ? K[13] : K[5];
assign K3[7] = decrypt_int ? K[24] : K[48];
assign K3[8] = decrypt_int ? K[3] : K[27];
assign K3[9] = decrypt_int ? K[26] : K[18];
assign K3[10] = decrypt_int ? K[20] : K[12];
assign K3[11] = decrypt_int ? K[11] : K[3];
assign K3[12] = decrypt_int ? K[48] : K[40];
assign K3[13] = decrypt_int ? K[25] : K[17];
assign K3[14] = decrypt_int ? K[54] : K[46];
assign K3[15] = decrypt_int ? K[5] : K[54];
assign K3[16] = decrypt_int ? K[6] : K[55];
assign K3[17] = decrypt_int ? K[46] : K[13];
assign K3[18] = decrypt_int ? K[34] : K[26];
assign K3[19] = decrypt_int ? K[33] : K[25];
assign K3[20] = decrypt_int ? K[27] : K[19];
assign K3[21] = decrypt_int ? K[53] : K[20];
assign K3[22] = decrypt_int ? K[4] : K[53];
assign K3[23] = decrypt_int ? K[12] : K[4];
assign K3[24] = decrypt_int ? K[17] : K[41];
assign K3[25] = decrypt_int ? K[8] : K[2];
assign K3[26] = decrypt_int ? K[30] : K[52];
assign K3[27] = decrypt_int ? K[52] : K[42];
assign K3[28] = decrypt_int ? K[35] : K[29];
assign K3[29] = decrypt_int ? K[50] : K[44];
assign K3[30] = decrypt_int ? K[51] : K[14];
assign K3[31] = decrypt_int ? K[45] : K[35];
assign K3[32] = decrypt_int ? K[1] : K[50];
assign K3[33] = decrypt_int ? K[23] : K[45];
assign K3[34] = decrypt_int ? K[36] : K[30];
assign K3[35] = decrypt_int ? K[7] : K[1];
assign K3[36] = decrypt_int ? K[2] : K[51];
assign K3[37] = decrypt_int ? K[29] : K[23];
assign K3[38] = decrypt_int ? K[9] : K[31];
assign K3[39] = decrypt_int ? K[49] : K[43];
assign K3[40] = decrypt_int ? K[31] : K[21];
assign K3[41] = decrypt_int ? K[14] : K[8];
assign K3[42] = decrypt_int ? K[37] : K[0];
assign K3[43] = decrypt_int ? K[43] : K[37];
assign K3[44] = decrypt_int ? K[15] : K[9];
assign K3[45] = decrypt_int ? K[16] : K[38];
assign K3[46] = decrypt_int ? K[28] : K[22];
assign K3[47] = decrypt_int ? K[38] : K[28];
assign K3[48] = decrypt_int ? K[0] : K[49];
assign K2[1] = decrypt_int ? K[33] : K[54];
assign K2[2] = decrypt_int ? K[54] : K[18];
assign K2[3] = decrypt_int ? K[12] : K[33];
assign K2[4] = decrypt_int ? K[46] : K[10];
assign K2[5] = decrypt_int ? K[24] : K[20];
assign K2[6] = decrypt_int ? K[27] : K[48];
assign K2[7] = decrypt_int ? K[13] : K[34];
assign K2[8] = decrypt_int ? K[17] : K[13];
assign K2[9] = decrypt_int ? K[40] : K[4];
assign K2[10] = decrypt_int ? K[34] : K[55];
assign K2[11] = decrypt_int ? K[25] : K[46];
assign K2[12] = decrypt_int ? K[5] : K[26];
assign K2[13] = decrypt_int ? K[39] : K[3];
assign K2[14] = decrypt_int ? K[11] : K[32];
assign K2[15] = decrypt_int ? K[19] : K[40];
assign K2[16] = decrypt_int ? K[20] : K[41];
assign K2[17] = decrypt_int ? K[3] : K[24];
assign K2[18] = decrypt_int ? K[48] : K[12];
assign K2[19] = decrypt_int ? K[47] : K[11];
assign K2[20] = decrypt_int ? K[41] : K[5];
assign K2[21] = decrypt_int ? K[10] : K[6];
assign K2[22] = decrypt_int ? K[18] : K[39];
assign K2[23] = decrypt_int ? K[26] : K[47];
assign K2[24] = decrypt_int ? K[6] : K[27];
assign K2[25] = decrypt_int ? K[22] : K[43];
assign K2[26] = decrypt_int ? K[44] : K[38];
assign K2[27] = decrypt_int ? K[7] : K[28];
assign K2[28] = decrypt_int ? K[49] : K[15];
assign K2[29] = decrypt_int ? K[9] : K[30];
assign K2[30] = decrypt_int ? K[38] : K[0];
assign K2[31] = decrypt_int ? K[0] : K[21];
assign K2[32] = decrypt_int ? K[15] : K[36];
assign K2[33] = decrypt_int ? K[37] : K[31];
assign K2[34] = decrypt_int ? K[50] : K[16];
assign K2[35] = decrypt_int ? K[21] : K[42];
assign K2[36] = decrypt_int ? K[16] : K[37];
assign K2[37] = decrypt_int ? K[43] : K[9];
assign K2[38] = decrypt_int ? K[23] : K[44];
assign K2[39] = decrypt_int ? K[8] : K[29];
assign K2[40] = decrypt_int ? K[45] : K[7];
assign K2[41] = decrypt_int ? K[28] : K[49];
assign K2[42] = decrypt_int ? K[51] : K[45];
assign K2[43] = decrypt_int ? K[2] : K[23];
assign K2[44] = decrypt_int ? K[29] : K[50];
assign K2[45] = decrypt_int ? K[30] : K[51];
assign K2[46] = decrypt_int ? K[42] : K[8];
assign K2[47] = decrypt_int ? K[52] : K[14];
assign K2[48] = decrypt_int ? K[14] : K[35];
assign K1[1] = decrypt_int ? K[40] : K[47];
assign K1[2] = decrypt_int ? K[4] : K[11];
assign K1[3] = decrypt_int ? K[19] : K[26];
assign K1[4] = decrypt_int ? K[53] : K[3];
assign K1[5] = decrypt_int ? K[6] : K[13];
assign K1[6] = decrypt_int ? K[34] : K[41];
assign K1[7] = decrypt_int ? K[20] : K[27];
assign K1[8] = decrypt_int ? K[24] : K[6];
assign K1[9] = decrypt_int ? K[47] : K[54];
assign K1[10] = decrypt_int ? K[41] : K[48];
assign K1[11] = decrypt_int ? K[32] : K[39];
assign K1[12] = decrypt_int ? K[12] : K[19];
assign K1[13] = decrypt_int ? K[46] : K[53];
assign K1[14] = decrypt_int ? K[18] : K[25];
assign K1[15] = decrypt_int ? K[26] : K[33];
assign K1[16] = decrypt_int ? K[27] : K[34];
assign K1[17] = decrypt_int ? K[10] : K[17];
assign K1[18] = decrypt_int ? K[55] : K[5];
assign K1[19] = decrypt_int ? K[54] : K[4];
assign K1[20] = decrypt_int ? K[48] : K[55];
assign K1[21] = decrypt_int ? K[17] : K[24];
assign K1[22] = decrypt_int ? K[25] : K[32];
assign K1[23] = decrypt_int ? K[33] : K[40];
assign K1[24] = decrypt_int ? K[13] : K[20];
assign K1[25] = decrypt_int ? K[29] : K[36];
assign K1[26] = decrypt_int ? K[51] : K[31];
assign K1[27] = decrypt_int ? K[14] : K[21];
assign K1[28] = decrypt_int ? K[1] : K[8];
assign K1[29] = decrypt_int ? K[16] : K[23];
assign K1[30] = decrypt_int ? K[45] : K[52];
assign K1[31] = decrypt_int ? K[7] : K[14];
assign K1[32] = decrypt_int ? K[22] : K[29];
assign K1[33] = decrypt_int ? K[44] : K[51];
assign K1[34] = decrypt_int ? K[2] : K[9];
assign K1[35] = decrypt_int ? K[28] : K[35];
assign K1[36] = decrypt_int ? K[23] : K[30];
assign K1[37] = decrypt_int ? K[50] : K[2];
assign K1[38] = decrypt_int ? K[30] : K[37];
assign K1[39] = decrypt_int ? K[15] : K[22];
assign K1[40] = decrypt_int ? K[52] : K[0];
assign K1[41] = decrypt_int ? K[35] : K[42];
assign K1[42] = decrypt_int ? K[31] : K[38];
assign K1[43] = decrypt_int ? K[9] : K[16];
assign K1[44] = decrypt_int ? K[36] : K[43];
assign K1[45] = decrypt_int ? K[37] : K[44];
assign K1[46] = decrypt_int ? K[49] : K[1];
assign K1[47] = decrypt_int ? K[0] : K[7];
assign K1[48] = decrypt_int ? K[21] : K[28];
endmodule
|
/****************************************************************************
AddSub unit
- Should perform ADD, ADDU, SUBU, SUB, SLT, SLTU
is_slt signext addsub
op[2] op[1] op[0] | Operation
0 0 0 0 SUBU
2 0 1 0 SUB
1 0 0 1 ADDU
3 0 1 1 ADD
4 1 0 0 SLTU
6 1 1 0 SLT
****************************************************************************/
module addersub (
opA, opB,
op,
result,
result_slt );
parameter WIDTH=32;
input [WIDTH-1:0] opA;
input [WIDTH-1:0] opB;
//input carry_in;
input [3-1:0] op;
output [WIDTH-1:0] result;
output result_slt;
wire carry_out;
wire [WIDTH:0] sum;
// Mux between sum, and slt
wire is_slt;
wire signext;
wire addsub;
assign is_slt=op[2];
assign signext=op[1];
assign addsub=op[0];
assign result=sum[WIDTH-1:0];
//assign result_slt[WIDTH-1:1]={31{1'b0}};
//assign result_slt[0]=sum[WIDTH];
assign result_slt=sum[WIDTH];
lpm_add_sub adder_inst(
.dataa({signext&opA[WIDTH-1],opA}),
.datab({signext&opB[WIDTH-1],opB}),
.cin(~addsub),
.add_sub(addsub),
.result(sum)
// synopsys translate_off
,
.cout (),
.clken (),
.clock (),
.overflow (),
.aclr ()
// synopsys translate_on
);
defparam
adder_inst.lpm_width=WIDTH+1,
adder_inst.lpm_representation="SIGNED";
assign carry_out=sum[WIDTH];
endmodule
|
module branchresolve ( en, rs, rt, eq, ne, ltz, lez, gtz, gez, eqz);
parameter WIDTH=32; //Deepak : Change from parameter to define
input en;
input [WIDTH-1:0] rs;
input [WIDTH-1:0] rt;
output eq;
output ne;
output ltz;
output lez;
output gtz;
output gez;
output eqz;
assign eq=(en)&(rs==rt);
assign ne=(en)&~eq;
assign eqz=(en)&~(|rs);
assign ltz=(en)&rs[WIDTH-1];
assign lez=(en)&rs[WIDTH-1] | eqz;
assign gtz=(en)&(~rs[WIDTH-1]) & ~eqz;
assign gez=(en)&(~rs[WIDTH-1]);
endmodule
|
/****************************************************************************
Generic Register
****************************************************************************/
module register(d,clk,resetn,en,q);
parameter WIDTH=32;
input clk;
input resetn;
input en;
input [WIDTH-1:0] d;
output [WIDTH-1:0] q;
reg [WIDTH-1:0] q;
always @(posedge clk or negedge resetn) //asynchronous reset
begin
if (resetn==0)
q<=0;
else if (en==1)
q<=d;
end
endmodule
/****************************************************************************
Generic Register - synchronous reset
****************************************************************************/
module register_sync(d,clk,resetn,en,q);
parameter WIDTH=32;
input clk;
input resetn;
input en;
input [WIDTH-1:0] d;
output [WIDTH-1:0] q;
reg [WIDTH-1:0] q;
always @(posedge clk) //synchronous reset
begin
if (resetn==0)
q<=0;
else if (en==1)
q<=d;
end
endmodule
/****************************************************************************
Generic Pipelined Register
- Special component, components starting with "pipereg" have
their enables treated independently of instructrions that use them.
- They are enabled whenever the stage is active and not stalled
****************************************************************************/
module pipereg(d,clk,resetn,en,squashn,q);
parameter WIDTH=32;
input clk;
input resetn;
input en;
input squashn;
input [WIDTH-1:0] d;
output [WIDTH-1:0] q;
reg [WIDTH-1:0] q;
always @(posedge clk) //synchronous reset
begin
if (resetn==0 || squashn==0)
q<=0;
else if (en==1)
q<=d;
end
endmodule
/****************************************************************************
Generic Pipelined Register 2 -OLD: If not enabled, queues squash
- This piperegister stalls the reset signal as well
module pipereg_full(d,clk,resetn,squashn,en,q);
parameter WIDTH=32;
input clk;
input resetn;
input en;
input squashn;
input [WIDTH-1:0] d;
output [WIDTH-1:0] q;
reg [WIDTH-1:0] q;
reg squash_save;
always @(posedge clk) //synchronous reset
begin
if (resetn==0 || (squashn==0 && en==1) || (squash_save&en))
q<=0;
else if (en==1)
q<=d;
end
always @(posedge clk)
begin
if (resetn==1 && squashn==0 && en==0)
squash_save<=1;
else
squash_save<=0;
end
endmodule
****************************************************************************/
/****************************************************************************
One cycle Stall circuit
****************************************************************************/
module onecyclestall(request,clk,resetn,stalled);
input request;
input clk;
input resetn;
output stalled;
reg T,Tnext;
// State machine for Stalling 1 cycle
always@(request or T)
begin
case(T)
1'b0: Tnext=request;
1'b1: Tnext=0;
endcase
end
always@(posedge clk)
if (~resetn)
T<=0;
else
T<=Tnext;
assign stalled=(request&~T);
endmodule
/****************************************************************************
Multi cycle Stall circuit - with wait signal
- One FF plus one 2:1 mux to stall 1st cycle on request, then wait
- this makes wait don't care for the first cycle
****************************************************************************/
module multicyclestall(request, devwait,clk,resetn,stalled);
input request;
input devwait;
input clk;
input resetn;
output stalled;
reg T;
always@(posedge clk)
if (~resetn)
T<=0;
else
T<=stalled;
assign stalled=(T) ? devwait : request;
endmodule
/****************************************************************************
One cycle - Pipeline delay register
****************************************************************************/
module pipedelayreg(d,en,clk,resetn,squashn,dst,stalled,q);
parameter WIDTH=32;
input [WIDTH-1:0] d;
input [4:0] dst;
input en;
input clk;
input resetn;
input squashn;
output stalled;
output [WIDTH-1:0] q;
reg [WIDTH-1:0] q;
reg T,Tnext;
// State machine for Stalling 1 cycle
always@(en or T or dst)
begin
case(T)
0: Tnext=en&(|dst);
1: Tnext=0;
endcase
end
always@(posedge clk)
if (~resetn)
T<=0;
else
T<=Tnext;
always @(posedge clk) //synchronous reset
begin
if (resetn==0 || squashn==0)
q<=0;
else if (en==1)
q<=d;
end
assign stalled=(en&~T&(|dst));
endmodule
/****************************************************************************
Fake Delay
****************************************************************************/
module fakedelay(d,clk,q);
parameter WIDTH=32;
input [WIDTH-1:0] d;
input clk;
output [WIDTH-1:0] q;
assign q=d;
endmodule
/****************************************************************************
Zeroer
****************************************************************************/
module zeroer(d,en,q);
parameter WIDTH=32;
input en;
input [WIDTH-1:0] d;
output [WIDTH-1:0] q;
assign q= (en) ? d : 0;
endmodule
/****************************************************************************
NOP - used to hack position of multiplexors
****************************************************************************/
module nop(d,q);
parameter WIDTH=32;
input [WIDTH-1:0] d;
output [WIDTH-1:0] q;
assign q=d;
endmodule
/****************************************************************************
Const
****************************************************************************/
//Deepak : Changed const to constant to resolve compilation error
module constant (out);
parameter WIDTH=32;
parameter VAL=31;
output [WIDTH-1:0] out;
assign out=VAL;
endmodule
/****************************************************************************
Branch detector
****************************************************************************/
module branch_detector(opcode, func, is_branch);
input [5:0] opcode;
input [5:0] func;
output is_branch;
wire is_special;
assign is_special=!(|opcode);
assign is_branch=((!(|opcode[5:3])) && !is_special) ||
((is_special)&&(func[5:3]==3'b001));
endmodule
|
/******************************************************************************
Data memory and interface
Operation table:
load/store sign size1 size0 | Operation
7 0 1 1 1 | LB
5 0 1 0 1 | LH
0 0 X 0 0 | LW
3 0 0 1 1 | LBU
1 0 0 0 1 | LHU
11 1 X 1 1 | SB
9 1 X 0 1 | SH
8 1 X 0 0 | SW
******************************************************************************/
module data_mem( clk, resetn, en, stalled,
d_writedata,
d_address,
boot_daddr, boot_ddata, boot_dwe,
op,
d_loadresult);
parameter D_ADDRESSWIDTH=32;
parameter DM_DATAWIDTH=32;
parameter DM_BYTEENAWIDTH=4; // usually should be DM_DATAWIDTH/8
//parameter DM_ADDRESSWIDTH=16; //Deepak commented
//parameter DM_SIZE=16384; //Deepak commented
//Deepak : UnCommented to see why the processor is stopping after the first instruction
parameter DM_ADDRESSWIDTH=8; //Deepak
parameter DM_SIZE=64; //Deepak : Increased the size of memory
input clk;
input resetn;
input en;
output stalled;
input [31:0] boot_daddr;
input [31:0] boot_ddata;
input boot_dwe;
input [D_ADDRESSWIDTH-1:0] d_address;
input [4-1:0] op;
input [DM_DATAWIDTH-1:0] d_writedata;
output [DM_DATAWIDTH-1:0] d_loadresult;
wire [DM_BYTEENAWIDTH-1:0] d_byteena;
wire [DM_DATAWIDTH-1:0] d_readdatain;
wire [DM_DATAWIDTH-1:0] d_writedatamem;
wire d_write;
wire [1:0] d_address_latched;
assign d_write=op[3];
//assign d_write = d_write;//deepak
register d_address_reg(d_address[1:0],clk,1'b1,en,d_address_latched);
defparam d_address_reg.WIDTH=2;
store_data_translator sdtrans_inst(
.write_data(d_writedata),
.d_address(d_address[1:0]),
.store_size(op[1:0]),
.d_byteena(d_byteena),
.d_writedataout(d_writedatamem));
load_data_translator ldtrans_inst(
.d_readdatain(d_readdatain),
.d_address(d_address_latched[1:0]),
.load_size(op[1:0]),
.load_sign_ext(op[2]),
.d_loadresult(d_loadresult));
altsyncram dmem (
.wren_a (d_write&en&(~d_address[31])),
.clock0 (clk),
.clocken0 (),
.clock1 (clk),
.clocken1 (boot_dwe),
`ifdef TEST_BENCH
.aclr0(~resetn),
`endif
.byteena_a (d_byteena),
.address_a (d_address[DM_ADDRESSWIDTH+2-1:2]),
.data_a (d_writedatamem),
.wren_b (boot_dwe), .data_b (boot_ddata), .address_b (boot_daddr),
// synopsys translate_off
.rden_b (),
.aclr1 (), .byteena_b (),
.addressstall_a (), .addressstall_b (), .q_b (),
// synopsys translate_on
.q_a (d_readdatain)
);
defparam
dmem.intended_device_family = "Stratix", //Deepak changed from Stratix to Cyclone
dmem.width_a = DM_DATAWIDTH,
dmem.widthad_a = DM_ADDRESSWIDTH-2,
dmem.numwords_a = DM_SIZE,
dmem.width_byteena_a = DM_BYTEENAWIDTH,
dmem.operation_mode = "BIDIR_DUAL_PORT",
dmem.width_b = DM_DATAWIDTH,
dmem.widthad_b = DM_ADDRESSWIDTH-2,
dmem.numwords_b = DM_SIZE,
dmem.width_byteena_b = 1,
dmem.outdata_reg_a = "UNREGISTERED",
dmem.address_reg_b = "CLOCK1",
dmem.wrcontrol_wraddress_reg_b = "CLOCK1",
dmem.wrcontrol_aclr_a = "NONE",
dmem.address_aclr_a = "NONE",
dmem.outdata_aclr_a = "NONE",
dmem.byteena_aclr_a = "NONE",
dmem.byte_size = 8,
`ifdef TEST_BENCH
dmem.indata_aclr_a = "CLEAR0",
dmem.init_file = "data.rif",
`endif
//`ifdef QUARTUS_SIM
dmem.init_file = "data.mif",
dmem.ram_block_type = "M4K",
//`else
// dmem.ram_block_type = "MEGARAM",
//`endif
dmem.lpm_type = "altsyncram";
// 1 cycle stall state machine
onecyclestall staller(en&~d_write,clk,resetn,stalled);
endmodule
/****************************************************************************
Store data translator
- moves store data to appropriate byte/halfword
- interfaces with altera blockrams
****************************************************************************/
module store_data_translator(
write_data, // data in least significant position
d_address,
store_size,
d_byteena,
d_writedataout); // shifted data to coincide with address
parameter WIDTH=32;
input [WIDTH-1:0] write_data;
input [1:0] d_address;
input [1:0] store_size;
output [3:0] d_byteena;
output [WIDTH-1:0] d_writedataout;
reg [3:0] d_byteena;
reg [WIDTH-1:0] d_writedataout;
always @(write_data or d_address or store_size)
begin
case (store_size)
2'b11:
case(d_address[1:0])
0:
begin
d_byteena=4'b1000;
d_writedataout={write_data[7:0],24'b0};
end
1:
begin
d_byteena=4'b0100;
d_writedataout={8'b0,write_data[7:0],16'b0};
end
2:
begin
d_byteena=4'b0010;
d_writedataout={16'b0,write_data[7:0],8'b0};
end
default:
begin
d_byteena=4'b0001;
d_writedataout={24'b0,write_data[7:0]};
end
endcase
2'b01:
case(d_address[1])
0:
begin
d_byteena=4'b1100;
d_writedataout={write_data[15:0],16'b0};
end
default:
begin
d_byteena=4'b0011;
d_writedataout={16'b0,write_data[15:0]};
end
endcase
default:
begin
d_byteena=4'b1111;
d_writedataout=write_data;
end
endcase
end
endmodule
/****************************************************************************
Load data translator
- moves read data to appropriate byte/halfword and zero/sign extends
****************************************************************************/
module load_data_translator(
d_readdatain,
d_address,
load_size,
load_sign_ext,
d_loadresult);
parameter WIDTH=32;
input [WIDTH-1:0] d_readdatain;
input [1:0] d_address;
input [1:0] load_size;
input load_sign_ext;
output [WIDTH-1:0] d_loadresult;
reg [WIDTH-1:0] d_loadresult;
always @(d_readdatain or d_address or load_size or load_sign_ext)
begin
case (load_size)
2'b11:
begin
case (d_address[1:0])
0: d_loadresult[7:0]=d_readdatain[31:24];
1: d_loadresult[7:0]=d_readdatain[23:16];
2: d_loadresult[7:0]=d_readdatain[15:8];
default: d_loadresult[7:0]=d_readdatain[7:0];
endcase
d_loadresult[31:8]={24{load_sign_ext&d_loadresult[7]}};
end
2'b01:
begin
case (d_address[1])
0: d_loadresult[15:0]=d_readdatain[31:16];
default: d_loadresult[15:0]=d_readdatain[15:0];
endcase
d_loadresult[31:16]={16{load_sign_ext&d_loadresult[15]}};
end
default:
d_loadresult=d_readdatain;
endcase
end
endmodule
|
// A FIFO is used for a non-duplex communication between a processor and another
module fifo(clk,resetn,dataIn,dataOut,wr,rd,full,empty,overflow);
parameter LOGSIZE = 2; //Default size is 4 elements (only 3 reqd)
parameter WIDTH = 32; //Default width is 32 bits
parameter SIZE = 1 << LOGSIZE;
input clk,resetn,rd,wr;
input [WIDTH-1:0] dataIn;
output[WIDTH-1:0] dataOut;
output full,empty,overflow;
reg [WIDTH-1:0] fifo[SIZE-1:0] ; //Fifo data stored here
reg overflow; //true if WR but no room, cleared on RD
reg [LOGSIZE-1:0] wptr,rptr; //Fifo read and write pointers
wire [WIDTH-1:0] fifoWire[SIZE-1:0] ; //Fifo data stored here
reg counter = 0;
reg [WIDTH-1:0] tempOut;
wire [LOGSIZE-1:0] wptr_inc = wptr+1;
assign empty = (wptr==rptr);
assign full = (wptr_inc==rptr);
assign dataOut = tempOut;
assign fifoWire[0] = fifo[0];
//always @ (posedge clk) begin
// if(reset) begin
// wptr<=0;
// rptr<=0;
// fifo[0] <= 32'hdeadbeef;
// fifo[1] <= 32'hdeadbeef;
// fifo[2] <= 32'hdeadbeef;
// end
//end
always @ (posedge clk) begin
if(wr==1) begin
fifo[wptr]<=dataIn;
wptr <= wptr + 1;
end
if(rd==1&&!empty) begin
casex(counter)
0: begin
tempOut <= fifo[rptr];
rptr <= rptr + 1;
counter <= 1;
end
endcase
end
if(rd==0) begin
counter <=0;
end
if(resetn==0) begin
rptr<=0;
wptr<=0;
end
end
endmodule
|
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