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/****************************************************************************
Generic Register
****************************************************************************/
module hi_reg(d,clk,resetn,en,q);
parameter WIDTH=32;
input clk;
input resetn;
input en;
input [WIDTH-1:0] d;
output [WIDTH-1:0] q;
reg [WIDTH-1:0] q;
always @(posedge clk or negedge resetn) //asynchronous reset
begin
if (resetn==0)
q<=0;
else if (en==1)
q<=d;
end
endmodule
|
/****************************************************************************
Fetch Unit
op
0 Conditional PC write
1 UnConditional PC write
****************************************************************************/
module ifetch(clk,resetn,
en,
squashn,
we,
op,
load,
load_data,
pc_out,
next_pc,
boot_iaddr,
boot_idata,
boot_iwe,
opcode,
rs,
rt,
rd,
sa,
offset,
instr_index,
func,
instr);
parameter PC_WIDTH=30;
parameter I_DATAWIDTH=32;
parameter I_ADDRESSWIDTH=8;
parameter I_SIZE=64;
input [31:0] boot_iaddr;
input [31:0] boot_idata;
input boot_iwe;
input clk;
input resetn;
input en; // PC increment enable
input we; // PC write enable
input squashn;// squash fetch
input op; // determines if conditional or unconditional branch
input load;
input [I_DATAWIDTH-1:0] load_data;
output [I_DATAWIDTH-1:0] pc_out; // output pc + 1 shifted left 2 bits
output [PC_WIDTH-1:0] next_pc;
output [31:26] opcode;
output [25:21] rs;
output [20:16] rt;
output [15:11] rd;
output [10:6] sa;
output [15:0] offset;
output [25:0] instr_index;
output [5:0] func;
output [I_DATAWIDTH-1:0] instr;
wire [PC_WIDTH-1:0] pc_plus_1;
wire [PC_WIDTH-1:0] pc;
wire ctrl_load;
wire out_of_sync;
assign ctrl_load=(load&~op|op);
lpm_counter pc_register(
.data(load_data[I_DATAWIDTH-1:2]),
.clock(clk),
.clk_en(en|we),
.cnt_en((~ctrl_load)&~out_of_sync),
.aset(~resetn),
.sload(ctrl_load),
// synopsys translate_off
.updown(), .cin(), .sset(), .sclr(), .aclr(), .aload(),
.eq(), .cout(),
// synopsys translate_on
.q(pc));
defparam pc_register.lpm_width=PC_WIDTH,
pc_register.lpm_avalue="16777215"; // 0x4000000 divide by 4
/****** Re-synchronize for case:
* en=0 && we=1 -> pc_register gets updated but not imem address
*
* Solution: stall pc_register and load memory address by changing
* incrementer to increment by 0
*******/
register sync_pcs_up( (we&~en&squashn), clk, resetn,en|we, out_of_sync);
defparam sync_pcs_up.WIDTH=1;
altsyncram imem (
.clock0 (clk),
.clocken0 (en|~squashn|~resetn),
.clock1 (clk), // changed
.clocken1 (boot_iwe), // changed
`ifdef TEST_BENCH
.aclr0(~resetn),
`endif
.address_a (next_pc[I_ADDRESSWIDTH-1:0]),
.wren_b (boot_iwe), .data_b (boot_idata), .address_b (boot_iaddr), //changed
// synopsys translate_off
.wren_a (), .rden_b (), .data_a (),
.aclr1 (), .byteena_a (), .byteena_b (),
.addressstall_a (), .addressstall_b (), .q_b (),
// synopsys translate_on
.q_a (instr)
);
defparam
imem.intended_device_family = "Stratix",
imem.width_a = I_DATAWIDTH,
imem.widthad_a = I_ADDRESSWIDTH,
imem.numwords_a = I_SIZE,
imem.operation_mode = "BIDIR_DUAL_PORT", // changed
imem.width_b = I_DATAWIDTH, // new
imem.widthad_b = I_ADDRESSWIDTH, // new
imem.numwords_b = I_SIZE, // new
imem.outdata_reg_b = "UNREGISTERED",
imem.outdata_reg_a = "UNREGISTERED",
imem.address_reg_b = "CLOCK1", // new
imem.wrcontrol_wraddress_reg_b = "CLOCK1", // new
imem.width_byteena_a = 1,
`ifdef TEST_BENCH
imem.address_aclr_a = "CLEAR0",
imem.outdata_aclr_a = "CLEAR0",
imem.init_file = "instr.rif",
`endif
`ifdef QUARTUS_SIM
imem.init_file = "instr.mif",
imem.ram_block_type = "AUTO",
`else
imem.ram_block_type = "M4K",
`endif
imem.lpm_type = "altsyncram";
wire dummy;
assign {dummy,pc_plus_1} = pc + {1'b0,~out_of_sync};
assign pc_out={pc_plus_1,2'b0};
assign next_pc = ctrl_load ? load_data[I_DATAWIDTH-1:2] : pc_plus_1;
assign opcode=instr[31:26];
assign rs=instr[25:21];
assign rt=instr[20:16];
assign rd=instr[15:11];
assign sa=instr[10:6];
assign offset=instr[15:0];
assign instr_index=instr[25:0];
assign func=instr[5:0];
endmodule
|
/****************************************************************************
ISA definition file
- The MIPS I ISA has a 6 bit opcode in the upper 6 bits.
- The opcode can also specify a "class". There are two classes:
1. SPECIAL - look in lowest 6 bits to find operation
2. REGIMM - look in [20:16] to find type of branch
****************************************************************************/
/****** OPCODES - bits 31...26 *******/
parameter OP_SPECIAL = 6'b000000;
parameter OP_REGIMM = 6'b000001;
parameter OP_J = 6'b000010;
parameter OP_JAL = 6'b000011;
parameter OP_BEQ = 6'b000100;
parameter OP_BNE = 6'b000101;
parameter OP_BLEZ = 6'b000110;
parameter OP_BGTZ = 6'b000111;
parameter OP_ADDI = 6'b001000;
parameter OP_ADDIU = 6'b001001;
parameter OP_SLTI = 6'b001010;
parameter OP_SLTIU = 6'b001011;
parameter OP_ANDI = 6'b001100;
parameter OP_ORI = 6'b001101;
parameter OP_XORI = 6'b001110;
parameter OP_LUI = 6'b001111;
parameter OP_LB = 6'b100000;
parameter OP_LH = 6'b100001;
parameter OP_LWL = 6'b100010;
parameter OP_LW = 6'b100011;
parameter OP_LBU = 6'b100100;
parameter OP_LHU = 6'b100101;
parameter OP_LWR = 6'b100110;
parameter OP_SB = 6'b101x00;
parameter OP_SH = 6'b101x01;
parameter OP_SWL = 6'b101010;
parameter OP_SW = 6'b101x11;
parameter OP_SWR = 6'b101110;
/****** FUNCTION CLASS - bits 5...0 *******/
parameter FUNC_SLL = 6'b000000;
parameter FUNC_SRL = 6'b000010;
parameter FUNC_SRA = 6'b000011;
parameter FUNC_SLLV = 6'b000100;
parameter FUNC_SRLV = 6'b000110;
parameter FUNC_SRAV = 6'b000111;
parameter FUNC_JR = 6'b001xx0;
parameter FUNC_JALR = 6'b001xx1;
parameter FUNC_MFHI = 6'bx10x00;
parameter FUNC_MTHI = 6'bx10x01;
parameter FUNC_MFLO = 6'bx10x10;
parameter FUNC_MTLO = 6'bx10x11;
parameter FUNC_MULT = 6'bx11x00;
parameter FUNC_MULTU = 6'bx11x01;
parameter FUNC_DIV = 6'bx11x10;
parameter FUNC_DIVU = 6'bx11x11;
parameter FUNC_ADD = 6'b100000;
parameter FUNC_ADDU = 6'b100001;
parameter FUNC_SUB = 6'b100010;
parameter FUNC_SUBU = 6'b100011;
parameter FUNC_AND = 6'b100100;
parameter FUNC_OR = 6'b100101;
parameter FUNC_XOR = 6'b100110;
parameter FUNC_NOR = 6'b100111;
parameter FUNC_SLT = 6'b101010;
parameter FUNC_SLTU = 6'b101011;
/****** REGIMM Class - bits 20...16 *******/
parameter FUNC_BLTZ = 1'b0;
parameter FUNC_BGEZ = 1'b1;
parameter OP_COP2 = 6'b010010;
parameter COP2_FUNC_CFC2 = 6'b111000;
parameter COP2_FUNC_CTC2 = 6'b111010;
parameter COP2_FUNC_MTC2 = 6'b111011;
//parameter FUNC_BLTZAL = 5'b10000;
//parameter FUNC_BGEZAL = 5'b10001;
/******
* Original REGIMM class, compressed above to save decode logic
parameter FUNC_BLTZ = 5'b00000;
parameter FUNC_BGEZ = 5'b00001;
parameter FUNC_BLTZAL = 5'b10000;
parameter FUNC_BGEZAL = 5'b10001;
*/
|
/****************************************************************************
logic unit
- note ALU must be able to increment PC for JAL type instructions
Operation Table
op
0 AND
1 OR
2 XOR
3 NOR
****************************************************************************/
module logic_unit (
opA, opB,
op,
result);
parameter WIDTH=32;
input [WIDTH-1:0] opA;
input [WIDTH-1:0] opB;
input [2-1:0] op;
output [WIDTH-1:0] result;
reg [WIDTH-1:0] logic_result;
always@(opA or opB or op )
case(op)
2'b00:
logic_result=opA&opB;
2'b01:
logic_result=opA|opB;
2'b10:
logic_result=opA^opB;
2'b11:
logic_result=~(opA|opB);
endcase
assign result=logic_result;
endmodule
|
/****************************************************************************
Generic Register
****************************************************************************/
module lo_reg(d,clk,resetn,en,q);
parameter WIDTH=32;
input clk;
input resetn;
input en;
input [WIDTH-1:0] d;
output [WIDTH-1:0] q;
reg [WIDTH-1:0] q;
always @(posedge clk or negedge resetn) //asynchronous reset
begin
if (resetn==0)
q<=0;
else if (en==1)
q<=d;
end
endmodule
|
module merge26lo(in1, in2, out);
input [31:0] in1;
input [25:0] in2;
output [31:0] out;
assign out[31:0]={in1[31:28],in2[25:0],2'b0};
endmodule
|
/****************************************************************************
MUL/DIV unit
Operation table
op
0 MULTU
1 MULT
****************************************************************************/
module mul(
opA, opB,
op, //is_signed
hi, lo);
parameter WIDTH=32;
input [WIDTH-1:0] opA;
input [WIDTH-1:0] opB;
input op;
output [WIDTH-1:0] hi;
output [WIDTH-1:0] lo;
wire is_signed;
assign is_signed=op;
wire dum,dum2;
lpm_mult lpm_mult_component (
.dataa ({is_signed&opA[WIDTH-1],opA}),
.datab ({is_signed&opB[WIDTH-1],opB}),
.result ({dum2,dum,hi,lo})
// synopsys translate_off
,
.clken (1'b1),
.clock (1'b0),
.sum (1'b0),
.aclr (1'b0)
// synopsys translate_on
);
defparam
lpm_mult_component.lpm_widtha = WIDTH+1,
lpm_mult_component.lpm_widthb = WIDTH+1,
lpm_mult_component.lpm_widthp = 2*WIDTH+2,
lpm_mult_component.lpm_widths = 1,
lpm_mult_component.lpm_pipeline = 0,
lpm_mult_component.lpm_type = "LPM_MULT",
lpm_mult_component.lpm_representation = "SIGNED",
lpm_mult_component.lpm_hint = "MAXIMIZE_SPEED=6";
endmodule
|
module pcadder(pc, offset, result);
parameter PC_WIDTH=32;
input [PC_WIDTH-1:0] pc;
input [PC_WIDTH-1:0] offset;
output [PC_WIDTH-1:0] result;
wire dum;
assign {dum,result} = pc + {offset[PC_WIDTH-3:0],2'b0};
endmodule
|
/****************************************************************************
Register File
- Has two read ports (a and b) and one write port (c)
- sel chooses the register to be read/written
****************************************************************************/
module reg_file(clk,resetn,
a_reg, a_readdataout, a_en,
b_reg, b_readdataout, b_en,
c_reg, c_writedatain, c_we);
parameter WIDTH=32;
parameter NUMREGS=32;
parameter LOG2NUMREGS=5;
input clk;
input resetn;
input a_en;
input b_en;
input [LOG2NUMREGS-1:0] a_reg,b_reg,c_reg;
output [WIDTH-1:0] a_readdataout, b_readdataout;
input [WIDTH-1:0] c_writedatain;
input c_we;
altsyncram reg_file1(
.wren_a (c_we&(|c_reg)),
.clock0 (clk),
.clock1 (clk),
.clocken1 (a_en),
.address_a (c_reg[LOG2NUMREGS-1:0]),
.address_b (a_reg[LOG2NUMREGS-1:0]),
.data_a (c_writedatain),
.q_b (a_readdataout)
// synopsys translate_off
,
.aclr0 (1'b0),
.aclr1 (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.data_b (32'b11111111),
.wren_b (1'b0),
.rden_b(1'b1),
.q_a (),
.clocken0 (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0)
// synopsys translate_on
);
defparam
reg_file1.operation_mode = "DUAL_PORT",
reg_file1.width_a = WIDTH,
reg_file1.widthad_a = LOG2NUMREGS,
reg_file1.numwords_a = NUMREGS,
reg_file1.width_b = WIDTH,
reg_file1.widthad_b = LOG2NUMREGS,
reg_file1.numwords_b = NUMREGS,
reg_file1.lpm_type = "altsyncram",
reg_file1.width_byteena_a = 1,
reg_file1.outdata_reg_b = "UNREGISTERED",
reg_file1.indata_aclr_a = "NONE",
reg_file1.wrcontrol_aclr_a = "NONE",
reg_file1.address_aclr_a = "NONE",
reg_file1.rdcontrol_reg_b = "CLOCK1",
reg_file1.address_reg_b = "CLOCK1",
reg_file1.address_aclr_b = "NONE",
reg_file1.outdata_aclr_b = "NONE",
reg_file1.read_during_write_mode_mixed_ports = "OLD_DATA",
reg_file1.ram_block_type = "AUTO",
reg_file1.intended_device_family = "Stratix";
//Reg file duplicated to avoid contention between 2 read
//and 1 write
altsyncram reg_file2(
.wren_a (c_we&(|c_reg)),
.clock0 (clk),
.clock1 (clk),
.clocken1 (b_en),
.address_a (c_reg[LOG2NUMREGS-1:0]),
.address_b (b_reg[LOG2NUMREGS-1:0]),
.data_a (c_writedatain),
.q_b (b_readdataout)
// synopsys translate_off
,
.aclr0 (1'b0),
.aclr1 (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.data_b (32'b11111111),
.rden_b(1'b1),
.wren_b (1'b0),
.q_a (),
.clocken0 (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0)
// synopsys translate_on
);
defparam
reg_file2.operation_mode = "DUAL_PORT",
reg_file2.width_a = WIDTH,
reg_file2.widthad_a = LOG2NUMREGS,
reg_file2.numwords_a = NUMREGS,
reg_file2.width_b = WIDTH,
reg_file2.widthad_b = LOG2NUMREGS,
reg_file2.numwords_b = NUMREGS,
reg_file2.lpm_type = "altsyncram",
reg_file2.width_byteena_a = 1,
reg_file2.outdata_reg_b = "UNREGISTERED",
reg_file2.indata_aclr_a = "NONE",
reg_file2.wrcontrol_aclr_a = "NONE",
reg_file2.address_aclr_a = "NONE",
reg_file2.rdcontrol_reg_b = "CLOCK1",
reg_file2.address_reg_b = "CLOCK1",
reg_file2.address_aclr_b = "NONE",
reg_file2.outdata_aclr_b = "NONE",
reg_file2.read_during_write_mode_mixed_ports = "OLD_DATA",
reg_file2.ram_block_type = "AUTO",
reg_file2.intended_device_family = "Stratix";
endmodule
|
/****************************************************************************
Shifter unit
Opcode Table:
sign_ext dir
0 0 | ShiftLeft
0 1 | ShiftRightLogic
1 1 | ShiftRightArith
****************************************************************************/
module shifter(clk, resetn,
opB, sa,
op, start, stalled,
dst,
result);
parameter WIDTH=32;
input clk;
input resetn;
input [WIDTH-1:0] opB;
input [4:0] sa; // Shift Amount
input [2-1:0] op;
input start;
output stalled;
input [4:0] dst;
output [WIDTH-1:0] result;
wire sign_ext;
wire shift_direction;
assign sign_ext=op[1];
assign shift_direction=op[0];
reg [WIDTH-1:0] shifter;
reg shift_state;
reg [4:0] shift_count;
wire wasjustbusy;
wire is_zeroshift;
wire was_zeroshift;
wire is_nop;
wire hi_bit, lo_bit;
assign hi_bit=sign_ext&opB[WIDTH-1];
assign lo_bit=0;
// to separate nops from zero shifts (which occur) we hack this
assign is_nop=~(|dst);
assign is_zeroshift=(~|sa)&~is_nop;
assign stalled = (start&(~wasjustbusy)&~is_nop&~was_zeroshift)|shift_state;
assign result=shifter;
register wasjustbusy_reg(shift_state,clk,resetn,1'b1,wasjustbusy);
defparam wasjustbusy_reg.WIDTH=1;
register was_zeroshift_reg(is_zeroshift&~was_zeroshift,
clk,resetn,start,was_zeroshift);
defparam was_zeroshift_reg.WIDTH=1;
always @(posedge clk or negedge resetn)
begin
if (!resetn)
begin
shifter<=0;
shift_state<=0;
shift_count<=0;
end
else
begin
case(shift_state)
0:
if (start&~wasjustbusy)
begin
shift_count<=sa;
shifter<=opB;
if (!is_zeroshift && !is_nop)
shift_state<=1;
end
default:
begin
if (shift_count==1)
shift_state<=0;
shift_count<=shift_count-1;
shifter[31]<=(shift_direction) ? hi_bit : shifter[30];
shifter[30]<=(shift_direction) ? shifter[31] : shifter[29];
shifter[29]<=(shift_direction) ? shifter[30] : shifter[28];
shifter[28]<=(shift_direction) ? shifter[29] : shifter[27];
shifter[27]<=(shift_direction) ? shifter[28] : shifter[26];
shifter[26]<=(shift_direction) ? shifter[27] : shifter[25];
shifter[25]<=(shift_direction) ? shifter[26] : shifter[24];
shifter[24]<=(shift_direction) ? shifter[25] : shifter[23];
shifter[23]<=(shift_direction) ? shifter[24] : shifter[22];
shifter[22]<=(shift_direction) ? shifter[23] : shifter[21];
shifter[21]<=(shift_direction) ? shifter[22] : shifter[20];
shifter[20]<=(shift_direction) ? shifter[21] : shifter[19];
shifter[19]<=(shift_direction) ? shifter[20] : shifter[18];
shifter[18]<=(shift_direction) ? shifter[19] : shifter[17];
shifter[17]<=(shift_direction) ? shifter[18] : shifter[16];
shifter[16]<=(shift_direction) ? shifter[17] : shifter[15];
shifter[15]<=(shift_direction) ? shifter[16] : shifter[14];
shifter[14]<=(shift_direction) ? shifter[15] : shifter[13];
shifter[13]<=(shift_direction) ? shifter[14] : shifter[12];
shifter[12]<=(shift_direction) ? shifter[13] : shifter[11];
shifter[11]<=(shift_direction) ? shifter[12] : shifter[10];
shifter[10]<=(shift_direction) ? shifter[11] : shifter[9];
shifter[9]<=(shift_direction) ? shifter[10] : shifter[8];
shifter[8]<=(shift_direction) ? shifter[9] : shifter[7];
shifter[7]<=(shift_direction) ? shifter[8] : shifter[6];
shifter[6]<=(shift_direction) ? shifter[7] : shifter[5];
shifter[5]<=(shift_direction) ? shifter[6] : shifter[4];
shifter[4]<=(shift_direction) ? shifter[5] : shifter[3];
shifter[3]<=(shift_direction) ? shifter[4] : shifter[2];
shifter[2]<=(shift_direction) ? shifter[3] : shifter[1];
shifter[1]<=(shift_direction) ? shifter[2] : shifter[0];
shifter[0]<=(shift_direction) ? shifter[1] : lo_bit;
end
endcase
end
end
endmodule
|
module signext16 ( in, out);
input [15:0] in;
output [31:0] out;
assign out={{16{in[15]}},in[15:0]};
endmodule
|
//Deepak: Commeted due to error: Module cannot be declared more than once
//`include "lo_reg.v"
//`include "hi_reg.v"
//`include "data_mem_stall.v"
//`include "mul.v"
//`include "shifter_perbit_pipe.v"
//`include "logic_unit.v"
//`include "addersub_slt.v"
//`include "merge26lo.v"
//`include "branchresolve.v"
//`include "pcadder.v"
//`include "signext16.v"
//`include "reg_file_pipe.v"
//`include "ifetch_pipe.v"
//`include "components.v"
/*To remove an instruction and the associated logic, comment the specific `defines*/
/*Instruction Set and Processor Logic Optimization Block*/
`define ADDI
`define ADDIU
`define ANDI
`define SPECIAL
`define REGIMM
`define J
`define JAL
`define BEQ
`define BNE
`define BLEZ
`define BGTZ
`define ADDI
`define ADDIU
`define SLTI
`define SLTIU
`define ANDI
`define ORI
`define XORI
`define LUI
`define LB
`define LH
`define LWL
`define LW
`define LBU
`define LHU
`define LWR
`define SB
`define SH
`define SWL
`define SW
`define SWR
/****** FUNCTION CLASS - bits 5...0 *******/
`define SLL
`define SRL
`define SRA
`define SLLV
`define SRLV
`define SRAV
`define JR
`define JALR
`define MFHI
`define MTHI
`define MFLO
`define MTLO
`define MULT
`define MULTU
`define ADD
`define ADDU
`define SUB
`define SUBU
`define AND
`define OR
`define XOR
`define NOR
`define SLT
`define SLTU
`define BLTZ
`define BGEZ
/*End of Instruction Set and Processor Logic Optimization Block*/
module system (
clk,
resetn,
boot_iaddr,
boot_idata,
boot_iwe,
boot_daddr,
boot_ddata,
boot_dwe,
reg_file_b_readdataout,
dataInNorth,dataOutNorth,wrNorth,rdNorth,fullNorth,emptyNorth,overflowNorth,
dataInSouth,dataOutSouth,wrSouth,rdSouth,fullSouth,emptySouth,overflowSouth,
dataInWest,dataOutWest,wrWest,rdWest,fullWest,emptyWest,overflowWest,
dataInEast,dataOutEast,wrEast,rdEast,fullEast,emptyEast,overflowEast,
wrGeneric,genericDataOut); //FIFO Signals
/************************* IO Declarations *********************/
`include "isa.v"
input clk;
input resetn;
input [31:0] boot_iaddr;
input [31:0] boot_idata;
input boot_iwe;
input [31:0] boot_daddr;
input [31:0] boot_ddata;
input boot_dwe;
input [31:0] dataInNorth; //FIFO
input [31:0] dataInSouth; //FIFO
input [31:0] dataInWest; //FIFO
input [31:0] dataInEast; //FIFO
output [31:0] dataOutNorth; //FIFO
output [31:0] dataOutSouth; //FIFO
output [31:0] dataOutWest; //FIFO
output [31:0] dataOutEast; //FIFO
output [31:0] genericDataOut;
output wrNorth; //FIFO write signal
output wrSouth; //FIFO write signal
output wrEast; //FIFO write signal
output wrWest; //FIFO write signal
output wrGeneric;
output rdNorth; //FIFO write signal
output rdSouth; //FIFO write signal
output rdEast; //FIFO write signal
output rdWest; //FIFO write signal
input fullNorth; //FIFO signal which indicates whether FIFO is full or not
input fullSouth;
input fullEast;
input fullWest;
input emptyNorth; //FIFO signal which indicates whether FIFO is full or not
input emptySouth;
input emptyEast;
input emptyWest;
input overflowNorth; //FIFO signal which indicates whether FIFO has overflowed or not
input overflowSouth;
input overflowEast;
input overflowWest;
output [31:0] reg_file_b_readdataout;
/*********************** Signal Declarations *******************/
wire branch_mispred;
wire stall_2nd_delayslot;
wire has_delayslot;
wire haz_zeroer0_q_pipereg5_q;
wire haz_zeroer_q_pipereg5_q;
// Datapath signals declarations
wire addersub_result_slt;
wire [ 31 : 0 ] addersub_result;
wire [ 31 : 0 ] logic_unit_result;
wire [ 31 : 0 ] shifter_result;
wire ctrl_shifter_stalled;
wire [ 31 : 0 ] mul_lo;
wire [ 31 : 0 ] mul_hi;
wire [ 31 : 0 ] ifetch_pc_out;
wire [ 31 : 0 ] ifetch_instr;
wire [ 5 : 0 ] ifetch_opcode;
wire [ 5 : 0 ] ifetch_func;
wire [ 4 : 0 ] ifetch_rs;
wire [ 4 : 0 ] ifetch_rt;
wire [ 4 : 0 ] ifetch_rd;
wire [ 25 : 0 ] ifetch_instr_index;
wire [ 15 : 0 ] ifetch_offset;
wire [ 4 : 0 ] ifetch_sa;
wire [ 31 : 0 ] ifetch_next_pc;
wire [ 31 : 0 ] data_mem_d_loadresult;
wire ctrl_data_mem_stalled;
wire [ 31 : 0 ] pcadder_result;
wire [ 31 : 0 ] signext16_out;
wire [ 31 : 0 ] reg_file_b_readdataout;
wire [ 31 : 0 ] reg_file_a_readdataout;
wire [ 31 : 0 ] merge26lo_out;
wire branchresolve_eqz;
wire branchresolve_gez;
wire branchresolve_gtz;
wire branchresolve_lez;
wire branchresolve_ltz;
wire branchresolve_ne;
wire branchresolve_eq;
wire [ 31 : 0 ] hi_reg_q;
wire [ 31 : 0 ] lo_reg_q;
wire [ 31 : 0 ] const6_out;
wire [ 31 : 0 ] const7_out;
wire [ 31 : 0 ] const_out;
wire [ 31 : 0 ] pipereg_q;
wire [ 25 : 0 ] pipereg1_q;
wire [ 4 : 0 ] pipereg2_q;
wire [ 4 : 0 ] pipereg5_q;
wire [ 31 : 0 ] pipereg3_q;
wire [ 31 : 0 ] fakedelay_q;
wire [ 31 : 0 ] nop_q;
wire [ 4 : 0 ] zeroer_q;
wire [ 4 : 0 ] zeroer0_q;
wire [ 4 : 0 ] zeroer4_q;
wire [ 4 : 0 ] mux3to1_shifter_sa_out;
wire [ 31 : 0 ] mux3to1_ifetch_load_data_out;
wire mux6to1_ifetch_load_out;
wire [ 31 : 0 ] mux7to1_reg_file_c_writedatain_out;
wire [ 31 : 0 ] mux2to1_addersub_opA_out;
wire [ 31 : 0 ] mux2to1_pipereg_d_out;
wire [ 4 : 0 ] mux3to1_zeroer4_d_out;
wire [ 31 : 0 ] mux3to1_nop_d_out;
wire [ 5 : 0 ] pipereg8_q;
wire [ 5 : 0 ] pipereg9_q;
wire [ 4 : 0 ] pipereg10_q;
/***************** Control Signals ***************/
//Decoded Opcode signal declarations
reg [ 1 : 0 ] ctrl_mux3to1_nop_d_sel;
reg [ 1 : 0 ] ctrl_mux3to1_zeroer4_d_sel;
reg ctrl_mux2to1_pipereg_d_sel;
reg ctrl_mux2to1_addersub_opA_sel;
reg ctrl_zeroer0_en;
reg [ 4 : 0 ] ctrl_mux7to1_reg_file_c_writedatain_sel; //Deepak Increased select lines
reg [ 2 : 0 ] ctrl_mux6to1_ifetch_load_sel;
reg [ 1 : 0 ] ctrl_mux3to1_ifetch_load_data_sel;
reg [ 1 : 0 ] ctrl_mux3to1_shifter_sa_sel;
reg ctrl_zeroer4_en;
reg ctrl_zeroer_en;
reg [ 2 : 0 ] ctrl_addersub_op;
reg ctrl_ifetch_op;
reg [ 3 : 0 ] ctrl_data_mem_op;
reg ctrl_mul_op;
reg [ 1 : 0 ] ctrl_logic_unit_op;
reg [ 1 : 0 ] ctrl_shifter_op;
//Enable signal declarations
reg ctrl_reg_file_c_we;
reg ctrl_reg_file_b_en;
reg ctrl_lo_reg_en;
reg ctrl_branchresolve_en;
reg ctrl_hi_reg_en;
reg ctrl_reg_file_a_en;
reg ctrl_ifetch_we;
reg ctrl_ifetch_en;
reg ctrl_data_mem_en;
reg ctrl_shifter_start;
//Other Signals
wire squash_stage2;
wire stall_out_stage2;
wire squash_stage1;
wire stall_out_stage1;
wire ctrl_pipereg_squashn;
wire ctrl_pipereg5_squashn;
wire ctrl_pipereg2_squashn;
wire ctrl_pipereg3_squashn;
wire ctrl_pipereg1_squashn;
wire ctrl_pipereg8_squashn;
wire ctrl_pipereg9_squashn;
wire ctrl_pipereg10_squashn;
wire ctrl_pipereg_resetn;
wire ctrl_pipereg5_resetn;
wire ctrl_pipereg2_resetn;
wire ctrl_pipereg3_resetn;
wire ctrl_pipereg1_resetn;
wire ctrl_pipereg8_resetn;
wire ctrl_pipereg9_resetn;
wire ctrl_pipereg10_resetn;
wire ctrl_pipereg_en;
wire ctrl_pipereg5_en;
wire ctrl_pipereg2_en;
wire ctrl_pipereg3_en;
wire ctrl_pipereg1_en;
wire ctrl_pipereg8_en;
wire ctrl_pipereg9_en;
wire ctrl_pipereg10_en;
wire [31:0] tempFifoDataInNorth;
wire [31:0] tempFifoDataInSouth;
wire [31:0] tempFifoDataInEast;
wire [31:0] tempFifoDataInWest;
wire [31:0] northEmpty;
wire [31:0] southEmpty;
wire [31:0] eastEmpty;
wire [31:0] westEmpty;
wire [31:0] northFull;
wire [31:0] southFull;
wire [31:0] eastFull;
wire [31:0] westFull;
reg writeFifoWest;
reg writeFifoEast;
reg writeFifoNorth;
reg writeFifoSouth;
reg readFifoWest;
reg readFifoEast;
reg readFifoNorth;
reg readFifoSouth;
reg writeGenOut;
reg [31:0] tempDataOutNorth;
reg [31:0] tempDataOutSouth;
reg [31:0] tempDataOutEast;
reg [31:0] tempDataOutWest;
reg [31:0] tempDataOutGeneric;
/*****Parameter Declarations and Port Map*******/
parameter NorthIn = 32'h00001000;
parameter NorthOut = 32'h00001004;
parameter SouthIn = 32'h00001008;
parameter SouthOut = 32'h0000100c;
parameter EastIn = 32'h00001010;
parameter EastOut = 32'h00001014;
parameter WestIn = 32'h00001018;
parameter WestOut = 32'h0000101c;
parameter NorthEmptyPort = 32'h00001020;
parameter NorthFullPort = 32'h00001024;
parameter SouthEmptyPort = 32'h00001028;
parameter SouthFullPort = 32'h0000102c;
parameter EastEmptyPort = 32'h00001030;
parameter EastFullPort = 32'h00001034;
parameter WestEmptyPort = 32'h00001038;
parameter WestFullPort = 32'h0000103c;
parameter genericDataOutPort = 32'h00001200;
/*********Parameter Declartions End************/
assign northFull = 32'h00000000|fullNorth;
assign southFull = 32'h00000000|fullSouth;
assign eastFull = 32'h00000000|fullEast;
assign westFull = 32'h00000000|fullWest;
assign northEmpty = 32'h00000000|emptyNorth;
assign southEmpty = 32'h00000000|emptySouth;
assign eastEmpty = 32'h00000000|emptyEast;
assign westEmpty = 32'h00000000|emptyWest;
// Port Map Table
// ****************
// 0x1000 North In
// 0x1004 North Out
// 0x1008 South In
// 0x100c South Out
// 0x1010 East In
// 0x1014 East Out
// 0x1018 West In
// 0x101c West Out
//Software will check the status of "full" mapped registers before writing.
//That is write as long as full is not high
//Software will check the status of "empty" mapped registers before read.
//That is read as long as empty is not high
// 0x1020 NorthEmpty
// 0x1024 NorthFull
// 0x1028 SouthEmpty
// 0x102c SouthFull
// 0x1030 EastEmpty
// 0x1034 EastFull
// 0x1038 WestEmpty
// 0x103c WestFull
/********************Store (Moving data out of the processor **************************/
//assign dataOutWest = (addersub_result==WestOut) ? reg_file_b_readdataout : 32'hxxxxxxxx;
assign dataOutWest = tempDataOutWest;
assign wrWest = writeFifoWest;
//assign dataOutEast = (addersub_result==EastOut) ? reg_file_b_readdataout : 32'hxxxxxxxx;
assign dataOutEast = tempDataOutEast;
assign wrEast = writeFifoEast;
//assign dataOutNorth = (addersub_result==NorthOut) ? reg_file_b_readdataout : 32'hxxxxxxxx;
assign dataOutNorth = tempDataOutNorth;
assign wrNorth = writeFifoNorth;
//assign dataOutSouth = (addersub_result==SouthOut) ? reg_file_b_readdataout : 32'hxxxxxxxx;
assign dataOutSouth = tempDataOutSouth;
assign wrSouth = writeFifoSouth;
//assign genericDataOut = (addersub_result==genericDataOutPort) ? reg_file_b_readdataout : 32'hxxxxxxxx;
assign wrGeneric = writeGenOut;
assign genericDataOut = tempDataOutGeneric;
always@ (posedge clk) begin
writeFifoWest <= (addersub_result==WestOut) ? 1'b1:1'b0;
writeFifoEast <= (addersub_result==EastOut) ? 1'b1:1'b0;
writeFifoNorth <= (addersub_result==NorthOut) ? 1'b1:1'b0;
writeFifoSouth <= (addersub_result==SouthOut) ? 1'b1:1'b0;
writeGenOut <= (addersub_result==genericDataOutPort) ? 1'b1:1'b0;
tempDataOutWest <= (addersub_result==WestOut) ? reg_file_b_readdataout : 32'hxxxxxxxx;
tempDataOutEast <= (addersub_result==EastOut) ? reg_file_b_readdataout : 32'hxxxxxxxx;
tempDataOutNorth <= (addersub_result==NorthOut) ? reg_file_b_readdataout : 32'hxxxxxxxx;
tempDataOutSouth <= (addersub_result==SouthOut) ? reg_file_b_readdataout : 32'hxxxxxxxx;
tempDataOutGeneric <= (addersub_result==genericDataOutPort) ? reg_file_b_readdataout : 32'hxxxxxxxx;
//readFifoNorth <= (addersub_result==NorthIn) ? 1'b1:1'b0;
//readFifoSouth <= (addersub_result==SouthIn) ? 1'b1:1'b0;
//readFifoEast <= (addersub_result==EastIn) ? 1'b1:1'b0;
//readFifoWest <= (addersub_result==WestIn) ? 1'b1:1'b0;
//tempFifoDataInEast = (eastEmpty!=32'h00000001) ? dataInEast : 32'hxxxxxxxx;
//tempFifoDataInWest = (westEmpty!=32'h00000001) ? dataInWest : 32'hxxxxxxxx;
//tempFifoDataInNorth = (northEmpty!=32'h00000001) ? dataInNorth : 32'hxxxxxxxx;
//tempFifoDataInSouth = (southEmpty!=32'h00000001) ? dataInSouth : 32'hxxxxxxxx;
end
/********************Load (Taking data into processor from output port*******************/
//If east port has something (indicated by eastEmpty != 1), read data to temp datain east
//assign tempFifoDataInEast = (eastEmpty!=32'h00000001) ? dataInEast : 32'hxxxxxxxx;
assign tempFifoDataInEast = dataInEast;
assign rdEast = (addersub_result==EastIn) ? 1'b1:1'b0;
//assign rdEast = readFifoEast;
//assign tempFifoDataInWest = (westEmpty!=32'h00000001) ? dataInWest : 32'hxxxxxxxx;
assign tempFifoDataInWest = dataInWest;
assign rdWest = (addersub_result==WestIn) ? 1'b1:1'b0;
//assign rdWest = readFifoWest;
//assign tempFifoDataInNorth = (northEmpty!=32'h00000001) ? dataInNorth : 32'hxxxxxxxx;
assign tempFifoDataInNorth = dataInNorth;
assign rdNorth = (addersub_result==NorthIn) ? 1'b1:1'b0;
//assign rdNorth = readFifoNorth;
//assign tempFifoDataInSouth = (southEmpty!=32'h00000001) ? dataInSouth : 32'hxxxxxxxx;
assign tempFifoDataInSouth = dataInSouth;
assign rdSouth = (addersub_result==SouthIn) ? 1'b1:1'b0;
//assign rdSouth = readFifoSouth;
/****************************** Control **************************/
//Decode Logic for Opcode and Multiplex Select signals
always @(ifetch_opcode or ifetch_func or ifetch_rt)
begin
// Initialize control opcodes to zero
ctrl_mux3to1_zeroer4_d_sel = 0;
ctrl_mux2to1_pipereg_d_sel = 0;
ctrl_zeroer0_en = 0;
ctrl_zeroer4_en = 0;
ctrl_zeroer_en = 0;
casex (ifetch_opcode)
`ifdef ADDI
OP_ADDI:
begin
ctrl_mux3to1_zeroer4_d_sel = 2;
ctrl_mux2to1_pipereg_d_sel = 0;
ctrl_zeroer4_en = 1;
ctrl_zeroer_en = 1;
end
`endif
`ifdef ADDIU
OP_ADDIU:
begin
ctrl_mux3to1_zeroer4_d_sel = 2;
ctrl_mux2to1_pipereg_d_sel = 0;
ctrl_zeroer4_en = 1;
ctrl_zeroer_en = 1;
end
`endif
`ifdef ANDI
OP_ANDI:
begin
ctrl_mux3to1_zeroer4_d_sel = 2;
ctrl_mux2to1_pipereg_d_sel = 1;
ctrl_zeroer4_en = 1;
ctrl_zeroer_en = 1;
end
`endif
`ifdef BEQ
OP_BEQ:
begin
ctrl_mux2to1_pipereg_d_sel = 0;
ctrl_zeroer0_en = 1;
ctrl_zeroer_en = 1;
end
`endif
`ifdef BGTZ
OP_BGTZ:
begin
ctrl_mux2to1_pipereg_d_sel = 0;
ctrl_zeroer_en = 1;
end
`endif
`ifdef BLEZ
OP_BLEZ:
begin
ctrl_mux2to1_pipereg_d_sel = 0;
ctrl_zeroer_en = 1;
end
`endif
`ifdef BNE
OP_BNE:
begin
ctrl_mux2to1_pipereg_d_sel = 0;
ctrl_zeroer0_en = 1;
ctrl_zeroer_en = 1;
end
`endif
`ifdef JAL
OP_JAL:
begin
ctrl_mux3to1_zeroer4_d_sel = 0;
ctrl_zeroer4_en = 1;
end
`endif
`ifdef LB
OP_LB:
begin
ctrl_mux3to1_zeroer4_d_sel = 2;
ctrl_mux2to1_pipereg_d_sel = 0;
ctrl_zeroer4_en = 1;
ctrl_zeroer_en = 1;
end
`endif
`ifdef LBU
OP_LBU:
begin
ctrl_mux3to1_zeroer4_d_sel = 2;
ctrl_mux2to1_pipereg_d_sel = 0;
ctrl_zeroer4_en = 1;
ctrl_zeroer_en = 1;
end
`endif
`ifdef LW
OP_LH:
begin
ctrl_mux3to1_zeroer4_d_sel = 2;
ctrl_mux2to1_pipereg_d_sel = 0;
ctrl_zeroer4_en = 1;
ctrl_zeroer_en = 1;
end
`endif
`ifdef LHU
OP_LHU:
begin
ctrl_mux3to1_zeroer4_d_sel = 2;
ctrl_mux2to1_pipereg_d_sel = 0;
ctrl_zeroer4_en = 1;
ctrl_zeroer_en = 1;
end
`endif
`ifdef LUI
OP_LUI:
begin
ctrl_mux3to1_zeroer4_d_sel = 2;
ctrl_mux2to1_pipereg_d_sel = 1;
ctrl_zeroer4_en = 1;
end
`endif
`ifdef LW
OP_LW:
begin
ctrl_mux3to1_zeroer4_d_sel = 2;
ctrl_mux2to1_pipereg_d_sel = 0;
ctrl_zeroer4_en = 1;
ctrl_zeroer_en = 1;
end
`endif
`ifdef ORI
OP_ORI:
begin
ctrl_mux3to1_zeroer4_d_sel = 2;
ctrl_mux2to1_pipereg_d_sel = 1;
ctrl_zeroer4_en = 1;
ctrl_zeroer_en = 1;
end
`endif
OP_REGIMM:
casex (ifetch_rt[0])
`ifdef BGEZ
FUNC_BGEZ:
begin
ctrl_mux2to1_pipereg_d_sel = 0;
ctrl_zeroer_en = 1;
end
`endif
`ifdef BLTZ
FUNC_BLTZ:
begin
ctrl_mux2to1_pipereg_d_sel = 0;
ctrl_zeroer_en = 1;
end
`endif
endcase
`ifdef SB
OP_SB:
begin
ctrl_mux2to1_pipereg_d_sel = 0;
ctrl_zeroer0_en = 1;
ctrl_zeroer_en = 1;
end
`endif
`ifdef SH
OP_SH:
begin
ctrl_mux2to1_pipereg_d_sel = 0;
ctrl_zeroer0_en = 1;
ctrl_zeroer_en = 1;
end
`endif
`ifdef SLTI
OP_SLTI:
begin
ctrl_mux3to1_zeroer4_d_sel = 2;
ctrl_mux2to1_pipereg_d_sel = 0;
ctrl_zeroer4_en = 1;
ctrl_zeroer_en = 1;
end
`endif
`ifdef SLTIU
OP_SLTIU:
begin
ctrl_mux3to1_zeroer4_d_sel = 2;
ctrl_mux2to1_pipereg_d_sel = 0;
ctrl_zeroer4_en = 1;
ctrl_zeroer_en = 1;
end
`endif
OP_SPECIAL:
casex (ifetch_func)
`ifdef ADD
FUNC_ADD:
begin
ctrl_mux3to1_zeroer4_d_sel = 1;
ctrl_zeroer0_en = 1;
ctrl_zeroer4_en = 1;
ctrl_zeroer_en = 1;
end
`endif
`ifdef ADDU
FUNC_ADDU:
begin
ctrl_mux3to1_zeroer4_d_sel = 1;
ctrl_zeroer0_en = 1;
ctrl_zeroer4_en = 1;
ctrl_zeroer_en = 1;
end
`endif
`ifdef AND
FUNC_AND:
begin
ctrl_mux3to1_zeroer4_d_sel = 1;
ctrl_zeroer0_en = 1;
ctrl_zeroer4_en = 1;
ctrl_zeroer_en = 1;
end
`endif
`ifdef JALR
FUNC_JALR:
begin
ctrl_mux3to1_zeroer4_d_sel = 0;
ctrl_zeroer4_en = 1;
ctrl_zeroer_en = 1;
end
`endif
`ifdef JR
FUNC_JR:
ctrl_zeroer_en = 1;
`endif
`ifdef MFHI
FUNC_MFHI:
begin
ctrl_mux3to1_zeroer4_d_sel = 1;
ctrl_zeroer4_en = 1;
end
`endif
`ifdef MFLO
FUNC_MFLO:
begin
ctrl_mux3to1_zeroer4_d_sel = 1;
ctrl_zeroer4_en = 1;
end
`endif
`ifdef MULT
FUNC_MULT:
begin
ctrl_zeroer0_en = 1;
ctrl_zeroer_en = 1;
end
`endif
`ifdef MULTU
FUNC_MULTU:
begin
ctrl_zeroer0_en = 1;
ctrl_zeroer_en = 1;
end
`endif
`ifdef NOR
FUNC_NOR:
begin
ctrl_mux3to1_zeroer4_d_sel = 1;
ctrl_zeroer0_en = 1;
ctrl_zeroer4_en = 1;
ctrl_zeroer_en = 1;
end
`endif
`ifdef OR
FUNC_OR:
begin
ctrl_mux3to1_zeroer4_d_sel = 1;
ctrl_zeroer0_en = 1;
ctrl_zeroer4_en = 1;
ctrl_zeroer_en = 1;
end
`endif
`ifdef SLL
FUNC_SLL:
begin
ctrl_mux3to1_zeroer4_d_sel = 1;
ctrl_zeroer0_en = 1;
ctrl_zeroer4_en = 1;
end
`endif
`ifdef SLLV
FUNC_SLLV:
begin
ctrl_mux3to1_zeroer4_d_sel = 1;
ctrl_zeroer0_en = 1;
ctrl_zeroer4_en = 1;
ctrl_zeroer_en = 1;
end
`endif
`ifdef SLT
FUNC_SLT:
begin
ctrl_mux3to1_zeroer4_d_sel = 1;
ctrl_zeroer0_en = 1;
ctrl_zeroer4_en = 1;
ctrl_zeroer_en = 1;
end
`endif
`ifdef SLTU
FUNC_SLTU:
begin
ctrl_mux3to1_zeroer4_d_sel = 1;
ctrl_zeroer0_en = 1;
ctrl_zeroer4_en = 1;
ctrl_zeroer_en = 1;
end
`endif
`ifdef SRA
FUNC_SRA:
begin
ctrl_mux3to1_zeroer4_d_sel = 1;
ctrl_zeroer0_en = 1;
ctrl_zeroer4_en = 1;
end
`endif
`ifdef SRAV
FUNC_SRAV:
begin
ctrl_mux3to1_zeroer4_d_sel = 1;
ctrl_zeroer0_en = 1;
ctrl_zeroer4_en = 1;
ctrl_zeroer_en = 1;
end
`endif
`ifdef SRL
FUNC_SRL:
begin
ctrl_mux3to1_zeroer4_d_sel = 1;
ctrl_zeroer0_en = 1;
ctrl_zeroer4_en = 1;
end
`endif
`ifdef SRLV
FUNC_SRLV:
begin
ctrl_mux3to1_zeroer4_d_sel = 1;
ctrl_zeroer0_en = 1;
ctrl_zeroer4_en = 1;
ctrl_zeroer_en = 1;
end
`endif
`ifdef SUB
FUNC_SUB:
begin
ctrl_mux3to1_zeroer4_d_sel = 1;
ctrl_zeroer0_en = 1;
ctrl_zeroer4_en = 1;
ctrl_zeroer_en = 1;
end
`endif
`ifdef SUBU
FUNC_SUBU:
begin
ctrl_mux3to1_zeroer4_d_sel = 1;
ctrl_zeroer0_en = 1;
ctrl_zeroer4_en = 1;
ctrl_zeroer_en = 1;
end
`endif
`ifdef XOR
FUNC_XOR:
begin
ctrl_mux3to1_zeroer4_d_sel = 1;
ctrl_zeroer0_en = 1;
ctrl_zeroer4_en = 1;
ctrl_zeroer_en = 1;
end
`endif
endcase
`ifdef SW
OP_SW:
begin
ctrl_mux2to1_pipereg_d_sel = 0;
ctrl_zeroer0_en = 1;
ctrl_zeroer_en = 1;
end
`endif
`ifdef XORI
OP_XORI:
begin
ctrl_mux3to1_zeroer4_d_sel = 2;
ctrl_mux2to1_pipereg_d_sel = 1;
ctrl_zeroer4_en = 1;
ctrl_zeroer_en = 1;
end
`endif
endcase
end
//Logic for enable signals in Pipe Stage 1
always@(ifetch_opcode or ifetch_func or ifetch_rt[0] or stall_out_stage2 or haz_zeroer_q_pipereg5_q or haz_zeroer0_q_pipereg5_q)
begin
ctrl_reg_file_b_en = 1 &~haz_zeroer0_q_pipereg5_q&~haz_zeroer_q_pipereg5_q&~stall_out_stage2;
ctrl_reg_file_a_en = 1 &~haz_zeroer0_q_pipereg5_q&~haz_zeroer_q_pipereg5_q&~stall_out_stage2;
ctrl_ifetch_en = 1 &~haz_zeroer0_q_pipereg5_q&~haz_zeroer_q_pipereg5_q&~stall_out_stage2;
end
//Decode Logic for Opcode and Multiplex Select signals
always@(pipereg8_q or pipereg9_q or pipereg10_q or addersub_result)
begin
// Initialize control opcodes to zero
ctrl_mux3to1_nop_d_sel = 0;
ctrl_mux2to1_addersub_opA_sel = 0;
ctrl_mux7to1_reg_file_c_writedatain_sel = 0;
ctrl_mux6to1_ifetch_load_sel = 0;
ctrl_mux3to1_ifetch_load_data_sel = 0;
ctrl_mux3to1_shifter_sa_sel = 0;
ctrl_addersub_op = 0;
ctrl_ifetch_op = 0;
ctrl_data_mem_op = 0;
ctrl_mul_op = 0;
ctrl_logic_unit_op = 0;
ctrl_shifter_op = 0;
casex (pipereg8_q)
`ifdef ADDI
OP_ADDI:
begin
ctrl_mux3to1_nop_d_sel = 2;
ctrl_mux2to1_addersub_opA_sel = 0;
ctrl_mux7to1_reg_file_c_writedatain_sel = 6;
ctrl_addersub_op = 3;
end
`endif
`ifdef ADDIU
OP_ADDIU:
begin
ctrl_mux3to1_nop_d_sel = 2;
ctrl_mux2to1_addersub_opA_sel = 0;
ctrl_mux7to1_reg_file_c_writedatain_sel = 6;
ctrl_addersub_op = 1;
end
`endif
`ifdef ANDI
OP_ANDI:
begin
ctrl_mux3to1_nop_d_sel = 2;
ctrl_mux7to1_reg_file_c_writedatain_sel = 4;
ctrl_logic_unit_op = 0;
end
`endif
`ifdef BEQ
OP_BEQ:
begin
ctrl_mux6to1_ifetch_load_sel = 5;
ctrl_mux3to1_ifetch_load_data_sel = 2;
ctrl_ifetch_op = 0;
end
`endif
`ifdef BGTZ
OP_BGTZ:
begin
ctrl_mux6to1_ifetch_load_sel = 0;
ctrl_mux3to1_ifetch_load_data_sel = 2;
ctrl_ifetch_op = 0;
end
`endif
`ifdef BLEZ
OP_BLEZ:
begin
ctrl_mux6to1_ifetch_load_sel = 3;
ctrl_mux3to1_ifetch_load_data_sel = 2;
ctrl_ifetch_op = 0;
end
`endif
`ifdef BNE
OP_BNE:
begin
ctrl_mux6to1_ifetch_load_sel = 4;
ctrl_mux3to1_ifetch_load_data_sel = 2;
ctrl_ifetch_op = 0;
end
`endif
`ifdef J
OP_J:
begin
ctrl_mux3to1_ifetch_load_data_sel = 1;
ctrl_ifetch_op = 1;
end
`endif
`ifdef JAL
OP_JAL:
begin
ctrl_mux2to1_addersub_opA_sel = 1;
ctrl_mux7to1_reg_file_c_writedatain_sel = 6;
ctrl_mux3to1_ifetch_load_data_sel = 1;
ctrl_addersub_op = 1;
ctrl_ifetch_op = 1;
end
`endif
`ifdef LB
OP_LB:
begin
ctrl_mux3to1_nop_d_sel = 2;
ctrl_mux2to1_addersub_opA_sel = 0;
ctrl_mux7to1_reg_file_c_writedatain_sel = 2;
ctrl_addersub_op = 3;
ctrl_data_mem_op = 7;
end
`endif
`ifdef LBU
OP_LBU:
begin
ctrl_mux3to1_nop_d_sel = 2;
ctrl_mux2to1_addersub_opA_sel = 0;
ctrl_mux7to1_reg_file_c_writedatain_sel = 2;
ctrl_addersub_op = 3;
ctrl_data_mem_op = 3;
end
`endif
`ifdef LH
OP_LH:
begin
ctrl_mux3to1_nop_d_sel = 2;
ctrl_mux2to1_addersub_opA_sel = 0;
ctrl_mux7to1_reg_file_c_writedatain_sel = 2;
ctrl_addersub_op = 3;
ctrl_data_mem_op = 5;
end
`endif
`ifdef LHU
OP_LHU:
begin
ctrl_mux3to1_nop_d_sel = 2;
ctrl_mux2to1_addersub_opA_sel = 0;
ctrl_mux7to1_reg_file_c_writedatain_sel = 2;
ctrl_addersub_op = 3;
ctrl_data_mem_op = 1;
end
`endif
`ifdef LUI
OP_LUI:
begin
ctrl_mux3to1_nop_d_sel = 2;
ctrl_mux7to1_reg_file_c_writedatain_sel = 3;
ctrl_mux3to1_shifter_sa_sel = 1;
ctrl_shifter_op = 0;
end
`endif
`ifdef LW
OP_LW:
begin
casex(addersub_result)
NorthIn: begin ctrl_mux7to1_reg_file_c_writedatain_sel = 8; end
SouthIn: begin ctrl_mux7to1_reg_file_c_writedatain_sel = 9; end
EastIn: begin ctrl_mux7to1_reg_file_c_writedatain_sel = 10; end
WestIn: begin ctrl_mux7to1_reg_file_c_writedatain_sel = 11; end
NorthEmptyPort:begin ctrl_mux7to1_reg_file_c_writedatain_sel = 12; end
SouthEmptyPort:begin ctrl_mux7to1_reg_file_c_writedatain_sel = 13; end
EastEmptyPort: begin ctrl_mux7to1_reg_file_c_writedatain_sel = 14; end
WestEmptyPort: begin ctrl_mux7to1_reg_file_c_writedatain_sel = 15; end
NorthFullPort: begin ctrl_mux7to1_reg_file_c_writedatain_sel = 16; end
SouthFullPort: begin ctrl_mux7to1_reg_file_c_writedatain_sel = 17; end
EastFullPort: begin ctrl_mux7to1_reg_file_c_writedatain_sel = 18; end
WestFullPort: begin ctrl_mux7to1_reg_file_c_writedatain_sel = 19; end
default: begin ctrl_mux7to1_reg_file_c_writedatain_sel = 2; end
endcase
ctrl_mux3to1_nop_d_sel = 2;
ctrl_mux2to1_addersub_opA_sel = 0;
ctrl_addersub_op = 3;
ctrl_data_mem_op = 0;
end
`endif
`ifdef ORI
OP_ORI:
begin
ctrl_mux3to1_nop_d_sel = 2;
ctrl_mux7to1_reg_file_c_writedatain_sel = 4;
ctrl_logic_unit_op = 1;
end
`endif
`ifdef REGIMM
OP_REGIMM:
casex (pipereg10_q[0])
`ifdef BGEZ
FUNC_BGEZ:
begin
ctrl_mux6to1_ifetch_load_sel = 1;
ctrl_mux3to1_ifetch_load_data_sel = 2;
ctrl_ifetch_op = 0;
end
`endif
`ifdef BLTZ
FUNC_BLTZ:
begin
ctrl_mux6to1_ifetch_load_sel = 2;
ctrl_mux3to1_ifetch_load_data_sel = 2;
ctrl_ifetch_op = 0;
end
`endif
endcase
`endif
`ifdef SB
OP_SB:
begin
ctrl_mux3to1_nop_d_sel = 2;
ctrl_mux2to1_addersub_opA_sel = 0;
ctrl_addersub_op = 3;
ctrl_data_mem_op = 11;
end
`endif
`ifdef SH
OP_SH:
begin
ctrl_mux3to1_nop_d_sel = 2;
ctrl_mux2to1_addersub_opA_sel = 0;
ctrl_addersub_op = 3;
ctrl_data_mem_op = 9;
end
`endif
`ifdef SLTI
OP_SLTI:
begin
ctrl_mux3to1_nop_d_sel = 2;
ctrl_mux2to1_addersub_opA_sel = 0;
ctrl_mux7to1_reg_file_c_writedatain_sel = 5;
ctrl_addersub_op = 6;
end
`endif
`ifdef SLTIU
OP_SLTIU:
begin
ctrl_mux3to1_nop_d_sel = 2;
ctrl_mux2to1_addersub_opA_sel = 0;
ctrl_mux7to1_reg_file_c_writedatain_sel = 5;
ctrl_addersub_op = 4;
end
`endif
OP_SPECIAL:
casex (pipereg9_q)
`ifdef ADD
FUNC_ADD:
begin
ctrl_mux3to1_nop_d_sel = 1;
ctrl_mux2to1_addersub_opA_sel = 0;
ctrl_mux7to1_reg_file_c_writedatain_sel = 6;
ctrl_addersub_op = 3;
end
`endif
`ifdef ADDU
FUNC_ADDU:
begin
ctrl_mux3to1_nop_d_sel = 1;
ctrl_mux2to1_addersub_opA_sel = 0;
ctrl_mux7to1_reg_file_c_writedatain_sel = 6;
ctrl_addersub_op = 1;
end
`endif
`ifdef AND
FUNC_AND:
begin
ctrl_mux3to1_nop_d_sel = 1;
ctrl_mux7to1_reg_file_c_writedatain_sel = 4;
ctrl_logic_unit_op = 0;
end
`endif
`ifdef JALR
FUNC_JALR:
begin
ctrl_mux2to1_addersub_opA_sel = 1;
ctrl_mux7to1_reg_file_c_writedatain_sel = 6;
ctrl_mux3to1_ifetch_load_data_sel = 0;
ctrl_addersub_op = 1;
ctrl_ifetch_op = 1;
end
`endif
`ifdef JR
FUNC_JR:
begin
ctrl_mux3to1_ifetch_load_data_sel = 0;
ctrl_ifetch_op = 1;
end
`endif
`ifdef MFHI
FUNC_MFHI:
ctrl_mux7to1_reg_file_c_writedatain_sel = 1;
`endif
`ifdef MFLO
FUNC_MFLO:
ctrl_mux7to1_reg_file_c_writedatain_sel = 0;
`endif
`ifdef MULT
FUNC_MULT:
ctrl_mul_op = 1;
`endif
`ifdef MULTU
FUNC_MULTU:
ctrl_mul_op = 0;
`endif
`ifdef NOR
FUNC_NOR:
begin
ctrl_mux3to1_nop_d_sel = 1;
ctrl_mux7to1_reg_file_c_writedatain_sel = 4;
ctrl_logic_unit_op = 3;
end
`endif
`ifdef OR
FUNC_OR:
begin
ctrl_mux3to1_nop_d_sel = 1;
ctrl_mux7to1_reg_file_c_writedatain_sel = 4;
ctrl_logic_unit_op = 1;
end
`endif
`ifdef SLL
FUNC_SLL:
begin
ctrl_mux3to1_nop_d_sel = 1;
ctrl_mux7to1_reg_file_c_writedatain_sel = 3;
ctrl_mux3to1_shifter_sa_sel = 0;
ctrl_shifter_op = 0;
end
`endif
`ifdef SLLV
FUNC_SLLV:
begin
ctrl_mux3to1_nop_d_sel = 1;
ctrl_mux7to1_reg_file_c_writedatain_sel = 3;
ctrl_mux3to1_shifter_sa_sel = 2;
ctrl_shifter_op = 0;
end
`endif
`ifdef SLT
FUNC_SLT:
begin
ctrl_mux3to1_nop_d_sel = 1;
ctrl_mux2to1_addersub_opA_sel = 0;
ctrl_mux7to1_reg_file_c_writedatain_sel = 5;
ctrl_addersub_op = 6;
end
`endif
`ifdef SLTU
FUNC_SLTU:
begin
ctrl_mux3to1_nop_d_sel = 1;
ctrl_mux2to1_addersub_opA_sel = 0;
ctrl_mux7to1_reg_file_c_writedatain_sel = 5;
ctrl_addersub_op = 4;
end
`endif
`ifdef SRA
FUNC_SRA:
begin
ctrl_mux3to1_nop_d_sel = 1;
ctrl_mux7to1_reg_file_c_writedatain_sel = 3;
ctrl_mux3to1_shifter_sa_sel = 0;
ctrl_shifter_op = 3;
end
`endif
`ifdef SRAV
FUNC_SRAV:
begin
ctrl_mux3to1_nop_d_sel = 1;
ctrl_mux7to1_reg_file_c_writedatain_sel = 3;
ctrl_mux3to1_shifter_sa_sel = 2;
ctrl_shifter_op = 3;
end
`endif
`ifdef SRL
FUNC_SRL:
begin
ctrl_mux3to1_nop_d_sel = 1;
ctrl_mux7to1_reg_file_c_writedatain_sel = 3;
ctrl_mux3to1_shifter_sa_sel = 0;
ctrl_shifter_op = 1;
end
`endif
`ifdef SRLV
FUNC_SRLV:
begin
ctrl_mux3to1_nop_d_sel = 1;
ctrl_mux7to1_reg_file_c_writedatain_sel = 3;
ctrl_mux3to1_shifter_sa_sel = 2;
ctrl_shifter_op = 1;
end
`endif
`ifdef SUB
FUNC_SUB:
begin
ctrl_mux3to1_nop_d_sel = 1;
ctrl_mux2to1_addersub_opA_sel = 0;
ctrl_mux7to1_reg_file_c_writedatain_sel = 6;
ctrl_addersub_op = 0;
end
`endif
`ifdef SUBU
FUNC_SUBU:
begin
ctrl_mux3to1_nop_d_sel = 1;
ctrl_mux2to1_addersub_opA_sel = 0;
ctrl_mux7to1_reg_file_c_writedatain_sel = 6;
ctrl_addersub_op = 2;
end
`endif
`ifdef XOR
FUNC_XOR:
begin
ctrl_mux3to1_nop_d_sel = 1;
ctrl_mux7to1_reg_file_c_writedatain_sel = 4;
ctrl_logic_unit_op = 2;
end
`endif
endcase
`ifdef SW
OP_SW:
begin
ctrl_mux3to1_nop_d_sel = 2;
ctrl_mux2to1_addersub_opA_sel = 0;
ctrl_addersub_op = 3;
ctrl_data_mem_op = 8;
end
`endif
`ifdef XORI
OP_XORI:
begin
ctrl_mux3to1_nop_d_sel = 2;
ctrl_mux7to1_reg_file_c_writedatain_sel = 4;
ctrl_logic_unit_op = 2;
end
`endif
endcase
end
//Logic for enable signals in Pipe Stage 2
always@(pipereg8_q or pipereg9_q or pipereg10_q[0] or 1'b0 or ctrl_shifter_stalled or ctrl_data_mem_stalled)
begin
ctrl_reg_file_c_we = 0;
ctrl_lo_reg_en = 0;
ctrl_branchresolve_en = 0;
ctrl_hi_reg_en = 0;
ctrl_ifetch_we = 0;
ctrl_data_mem_en = 0;
ctrl_shifter_start = 0;
casex (pipereg8_q)
`ifdef ADDI
OP_ADDI:
ctrl_reg_file_c_we = 1 &~ctrl_data_mem_stalled&~ctrl_shifter_stalled&~1'b0;
`endif
`ifdef ADDIU
OP_ADDIU:
ctrl_reg_file_c_we = 1 &~ctrl_data_mem_stalled&~ctrl_shifter_stalled&~1'b0;
`endif
`ifdef ANDI
OP_ANDI:
ctrl_reg_file_c_we = 1 &~ctrl_data_mem_stalled&~ctrl_shifter_stalled&~1'b0;
`endif
`ifdef BEQ
OP_BEQ:
begin
ctrl_branchresolve_en = 1 &~ctrl_data_mem_stalled&~ctrl_shifter_stalled&~1'b0;
ctrl_ifetch_we = 1 &~ctrl_data_mem_stalled&~ctrl_shifter_stalled&~1'b0;
end
`endif
`ifdef BGTZ
OP_BGTZ:
begin
ctrl_branchresolve_en = 1 &~ctrl_data_mem_stalled&~ctrl_shifter_stalled&~1'b0;
ctrl_ifetch_we = 1 &~ctrl_data_mem_stalled&~ctrl_shifter_stalled&~1'b0;
end
`endif
`ifdef BLEZ
OP_BLEZ:
begin
ctrl_branchresolve_en = 1 &~ctrl_data_mem_stalled&~ctrl_shifter_stalled&~1'b0;
ctrl_ifetch_we = 1 &~ctrl_data_mem_stalled&~ctrl_shifter_stalled&~1'b0;
end
`endif
`ifdef BNE
OP_BNE:
begin
ctrl_branchresolve_en = 1 &~ctrl_data_mem_stalled&~ctrl_shifter_stalled&~1'b0;
ctrl_ifetch_we = 1 &~ctrl_data_mem_stalled&~ctrl_shifter_stalled&~1'b0;
end
`endif
`ifdef J
OP_J:
ctrl_ifetch_we = 1 &~ctrl_data_mem_stalled&~ctrl_shifter_stalled&~1'b0;
`endif
`ifdef JAL
OP_JAL:
begin
ctrl_reg_file_c_we = 1 &~ctrl_data_mem_stalled&~ctrl_shifter_stalled&~1'b0;
ctrl_ifetch_we = 1 &~ctrl_data_mem_stalled&~ctrl_shifter_stalled&~1'b0;
end
`endif
`ifdef LB
OP_LB:
begin
ctrl_reg_file_c_we = 1 &~ctrl_data_mem_stalled&~ctrl_shifter_stalled&~1'b0;
ctrl_data_mem_en = 1 &~1'b0;
end
`endif
`ifdef LBU
OP_LBU:
begin
ctrl_reg_file_c_we = 1 &~ctrl_data_mem_stalled&~ctrl_shifter_stalled&~1'b0;
ctrl_data_mem_en = 1 &~1'b0;
end
`endif
`ifdef LH
OP_LH:
begin
ctrl_reg_file_c_we = 1 &~ctrl_data_mem_stalled&~ctrl_shifter_stalled&~1'b0;
ctrl_data_mem_en = 1 &~1'b0;
end
`endif
`ifdef LHU
OP_LHU:
begin
ctrl_reg_file_c_we = 1 &~ctrl_data_mem_stalled&~ctrl_shifter_stalled&~1'b0;
ctrl_data_mem_en = 1 &~1'b0;
end
`endif
`ifdef LUI
OP_LUI:
begin
ctrl_reg_file_c_we = 1 &~ctrl_data_mem_stalled&~ctrl_shifter_stalled&~1'b0;
ctrl_shifter_start = 1 &~1'b0;
end
`endif
`ifdef LW
OP_LW:
begin
ctrl_reg_file_c_we = 1 &~ctrl_data_mem_stalled&~ctrl_shifter_stalled&~1'b0;
ctrl_data_mem_en = 1 &~1'b0;
end
`endif
`ifdef ORI
OP_ORI:
ctrl_reg_file_c_we = 1 &~ctrl_data_mem_stalled&~ctrl_shifter_stalled&~1'b0;
`endif
OP_REGIMM:
casex (pipereg10_q[0])
`ifdef BGEZ
FUNC_BGEZ:
begin
ctrl_branchresolve_en = 1 &~ctrl_data_mem_stalled&~ctrl_shifter_stalled&~1'b0;
ctrl_ifetch_we = 1 &~ctrl_data_mem_stalled&~ctrl_shifter_stalled&~1'b0;
end
`endif
`ifdef BLTZ
FUNC_BLTZ:
begin
ctrl_branchresolve_en = 1 &~ctrl_data_mem_stalled&~ctrl_shifter_stalled&~1'b0;
ctrl_ifetch_we = 1 &~ctrl_data_mem_stalled&~ctrl_shifter_stalled&~1'b0;
end
`endif
endcase
`ifdef SB
OP_SB:
ctrl_data_mem_en = 1 &~1'b0;
`endif
`ifdef SH
OP_SH:
ctrl_data_mem_en = 1 &~1'b0;
`endif
`ifdef SLTI
OP_SLTI:
ctrl_reg_file_c_we = 1 &~ctrl_data_mem_stalled&~ctrl_shifter_stalled&~1'b0;
`endif
`ifdef SLTIU
OP_SLTIU:
ctrl_reg_file_c_we = 1 &~ctrl_data_mem_stalled&~ctrl_shifter_stalled&~1'b0;
`endif
OP_SPECIAL:
casex (pipereg9_q)
`ifdef ADD
FUNC_ADD:
ctrl_reg_file_c_we = 1 &~ctrl_data_mem_stalled&~ctrl_shifter_stalled&~1'b0;
`endif
`ifdef ADDU
FUNC_ADDU:
ctrl_reg_file_c_we = 1 &~ctrl_data_mem_stalled&~ctrl_shifter_stalled&~1'b0;
`endif
`ifdef AND
FUNC_AND:
ctrl_reg_file_c_we = 1 &~ctrl_data_mem_stalled&~ctrl_shifter_stalled&~1'b0;
`endif
`ifdef JALR
FUNC_JALR:
begin
ctrl_reg_file_c_we = 1 &~ctrl_data_mem_stalled&~ctrl_shifter_stalled&~1'b0;
ctrl_ifetch_we = 1 &~ctrl_data_mem_stalled&~ctrl_shifter_stalled&~1'b0;
end
`endif
`ifdef JR
FUNC_JR:
ctrl_ifetch_we = 1 &~ctrl_data_mem_stalled&~ctrl_shifter_stalled&~1'b0;
`endif
`ifdef MFHI
FUNC_MFHI:
ctrl_reg_file_c_we = 1 &~ctrl_data_mem_stalled&~ctrl_shifter_stalled&~1'b0;
`endif
`ifdef MFLO
FUNC_MFLO:
ctrl_reg_file_c_we = 1 &~ctrl_data_mem_stalled&~ctrl_shifter_stalled&~1'b0;
`endif
`ifdef MULT
FUNC_MULT:
begin
ctrl_lo_reg_en = 1 &~ctrl_data_mem_stalled&~ctrl_shifter_stalled&~1'b0;
ctrl_hi_reg_en = 1 &~ctrl_data_mem_stalled&~ctrl_shifter_stalled&~1'b0;
end
`endif
`ifdef MULTU
FUNC_MULTU:
begin
ctrl_lo_reg_en = 1 &~ctrl_data_mem_stalled&~ctrl_shifter_stalled&~1'b0;
ctrl_hi_reg_en = 1 &~ctrl_data_mem_stalled&~ctrl_shifter_stalled&~1'b0;
end
`endif
`ifdef NOR
FUNC_NOR:
ctrl_reg_file_c_we = 1 &~ctrl_data_mem_stalled&~ctrl_shifter_stalled&~1'b0;
`endif
`ifdef OR
FUNC_OR:
ctrl_reg_file_c_we = 1 &~ctrl_data_mem_stalled&~ctrl_shifter_stalled&~1'b0;
`endif
`ifdef SLL
FUNC_SLL:
begin
ctrl_reg_file_c_we = 1 &~ctrl_data_mem_stalled&~ctrl_shifter_stalled&~1'b0;
ctrl_shifter_start = 1 &~1'b0;
end
`endif
`ifdef SLLV
FUNC_SLLV:
begin
ctrl_reg_file_c_we = 1 &~ctrl_data_mem_stalled&~ctrl_shifter_stalled&~1'b0;
ctrl_shifter_start = 1 &~1'b0;
end
`endif
`ifdef SLT
FUNC_SLT:
ctrl_reg_file_c_we = 1 &~ctrl_data_mem_stalled&~ctrl_shifter_stalled&~1'b0;
`endif
`ifdef SLTU
FUNC_SLTU:
ctrl_reg_file_c_we = 1 &~ctrl_data_mem_stalled&~ctrl_shifter_stalled&~1'b0;
`endif
`ifdef SRA
FUNC_SRA:
begin
ctrl_reg_file_c_we = 1 &~ctrl_data_mem_stalled&~ctrl_shifter_stalled&~1'b0;
ctrl_shifter_start = 1 &~1'b0;
end
`endif
`ifdef SRAV
FUNC_SRAV:
begin
ctrl_reg_file_c_we = 1 &~ctrl_data_mem_stalled&~ctrl_shifter_stalled&~1'b0;
ctrl_shifter_start = 1 &~1'b0;
end
`endif
`ifdef SRL
FUNC_SRL:
begin
ctrl_reg_file_c_we = 1 &~ctrl_data_mem_stalled&~ctrl_shifter_stalled&~1'b0;
ctrl_shifter_start = 1 &~1'b0;
end
`endif
`ifdef SRLV
FUNC_SRLV:
begin
ctrl_reg_file_c_we = 1 &~ctrl_data_mem_stalled&~ctrl_shifter_stalled&~1'b0;
ctrl_shifter_start = 1 &~1'b0;
end
`endif
`ifdef SUB
FUNC_SUB:
ctrl_reg_file_c_we = 1 &~ctrl_data_mem_stalled&~ctrl_shifter_stalled&~1'b0;
`endif
`ifdef SUB
FUNC_SUBU:
ctrl_reg_file_c_we = 1 &~ctrl_data_mem_stalled&~ctrl_shifter_stalled&~1'b0;
`endif
`ifdef XOR
FUNC_XOR:
ctrl_reg_file_c_we = 1 &~ctrl_data_mem_stalled&~ctrl_shifter_stalled&~1'b0;
`endif
endcase
`ifdef SW
OP_SW:
ctrl_data_mem_en = 1 &~1'b0;
`endif
`ifdef XORI
OP_XORI:
ctrl_reg_file_c_we = 1 &~ctrl_data_mem_stalled&~ctrl_shifter_stalled&~1'b0;
`endif
endcase
end
/********* Stall Network & PipeReg Control ********/
assign stall_out_stage1 = stall_out_stage2|haz_zeroer0_q_pipereg5_q|haz_zeroer_q_pipereg5_q;
assign ctrl_pipereg10_en = ~stall_out_stage1;
assign ctrl_pipereg9_en = ~stall_out_stage1;
assign ctrl_pipereg8_en = ~stall_out_stage1;
assign ctrl_pipereg1_en = ~stall_out_stage1;
assign ctrl_pipereg3_en = ~stall_out_stage1;
assign ctrl_pipereg2_en = ~stall_out_stage1;
assign ctrl_pipereg5_en = ~stall_out_stage1;
assign ctrl_pipereg_en = ~stall_out_stage1;
assign stall_out_stage2 = 1'b0|ctrl_data_mem_stalled|ctrl_shifter_stalled;
assign branch_mispred = (((ctrl_ifetch_op==1) || (ctrl_ifetch_op==0 && mux6to1_ifetch_load_out)) & ctrl_ifetch_we);
assign stall_2nd_delayslot = &has_delayslot;
assign has_delayslot = 0;
assign squash_stage1 = ((stall_out_stage1&~stall_out_stage2))|~resetn;
assign ctrl_pipereg10_resetn = ~squash_stage1;
assign ctrl_pipereg9_resetn = ~squash_stage1;
assign ctrl_pipereg8_resetn = ~squash_stage1;
assign ctrl_pipereg1_resetn = ~squash_stage1;
assign ctrl_pipereg3_resetn = ~squash_stage1;
assign ctrl_pipereg2_resetn = ~squash_stage1;
assign ctrl_pipereg5_resetn = ~squash_stage1;
assign ctrl_pipereg_resetn = ~squash_stage1;
assign ctrl_pipereg_squashn = ~(0);
assign ctrl_pipereg5_squashn = ~(0);
assign ctrl_pipereg2_squashn = ~(0);
assign ctrl_pipereg3_squashn = ~(0);
assign ctrl_pipereg1_squashn = ~(0);
assign ctrl_pipereg8_squashn = ~(0);
assign ctrl_pipereg9_squashn = ~(0);
assign ctrl_pipereg10_squashn = ~(0);
assign ctrl_ifetch_squashn = ~(0);
assign squash_stage2 = ((stall_out_stage2&~1'b0))|~resetn;
/****************************** Datapath **************************/
/******************** Hazard Detection Logic ***********************/
assign haz_zeroer0_q_pipereg5_q = (zeroer0_q==pipereg5_q) && (|zeroer0_q);
assign haz_zeroer_q_pipereg5_q = (zeroer_q==pipereg5_q) && (|zeroer_q);
/*************** DATAPATH COMPONENTS **************/
addersub addersub (
.opB(nop_q),
.opA(mux2to1_addersub_opA_out),
.op(ctrl_addersub_op),
.result_slt(addersub_result_slt),
.result(addersub_result));
defparam
addersub.WIDTH=32;
logic_unit logic_unit (
.opB(nop_q),
.opA(reg_file_a_readdataout),
.op(ctrl_logic_unit_op),
.result(logic_unit_result));
defparam
logic_unit.WIDTH=32;
shifter shifter (
.clk(clk),
.resetn(resetn),
.dst(pipereg5_q),
.sa(mux3to1_shifter_sa_out),
.opB(nop_q),
.op(ctrl_shifter_op),
.start(ctrl_shifter_start),
.stalled(ctrl_shifter_stalled),
.result(shifter_result));
defparam
shifter.WIDTH=32;
mul mul (
.opB(reg_file_b_readdataout),
.opA(reg_file_a_readdataout),
.op(ctrl_mul_op),
.lo(mul_lo),
.hi(mul_hi));
defparam
mul.WIDTH=32;
ifetch ifetch (
.clk(clk),
.resetn(resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe),
.load(mux6to1_ifetch_load_out),
.load_data(mux3to1_ifetch_load_data_out),
.op(ctrl_ifetch_op),
.we(ctrl_ifetch_we),
.squashn(ctrl_ifetch_squashn),
.en(ctrl_ifetch_en),
.pc_out(ifetch_pc_out),
.instr(ifetch_instr),
.opcode(ifetch_opcode),
.func(ifetch_func),
.rs(ifetch_rs),
.rt(ifetch_rt),
.rd(ifetch_rd),
.instr_index(ifetch_instr_index),
.offset(ifetch_offset),
.sa(ifetch_sa),
.next_pc(ifetch_next_pc));
data_mem data_mem (
.clk(clk),
.resetn(resetn),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe),
.d_address(addersub_result),
.d_writedata(reg_file_b_readdataout),
.op(ctrl_data_mem_op),
.en(ctrl_data_mem_en),
.stalled(ctrl_data_mem_stalled),
.d_loadresult(data_mem_d_loadresult));
pcadder pcadder (
.offset(pipereg_q),
.pc(pipereg3_q),
.result(pcadder_result));
signext16 signext16 (
.in(ifetch_offset),
.out(signext16_out));
reg_file reg_file (
.clk(clk),
.resetn(resetn),
.c_writedatain(mux7to1_reg_file_c_writedatain_out),
.c_reg(pipereg5_q),
.b_reg(zeroer0_q),
.a_reg(zeroer_q),
.c_we(ctrl_reg_file_c_we),
.b_en(ctrl_reg_file_b_en),
.a_en(ctrl_reg_file_a_en),
.b_readdataout(reg_file_b_readdataout),
.a_readdataout(reg_file_a_readdataout));
merge26lo merge26lo (
.in2(pipereg1_q),
.in1(pipereg3_q),
.out(merge26lo_out));
branchresolve branchresolve (
.rt(reg_file_b_readdataout),
.rs(reg_file_a_readdataout),
.en(ctrl_branchresolve_en),
.eqz(branchresolve_eqz),
.gez(branchresolve_gez),
.gtz(branchresolve_gtz),
.lez(branchresolve_lez),
.ltz(branchresolve_ltz),
.ne(branchresolve_ne),
.eq(branchresolve_eq));
defparam
branchresolve.WIDTH=32;
hi_reg hi_reg (
.clk(clk),
.resetn(resetn),
.d(mul_hi),
.en(ctrl_hi_reg_en),
.q(hi_reg_q));
defparam
hi_reg.WIDTH=32;
lo_reg lo_reg (
.clk(clk),
.resetn(resetn),
.d(mul_lo),
.en(ctrl_lo_reg_en),
.q(lo_reg_q));
defparam
lo_reg.WIDTH=32;
constant const6 (
.out(const6_out));
defparam
const6.WIDTH=32,
const6.VAL=0;
constant const7 (
.out(const7_out));
defparam
const7.WIDTH=32,
const7.VAL=16;
constant constant (
.out(const_out));
defparam
constant.WIDTH=32,
constant.VAL=31;
pipereg pipereg (
.clk(clk),
.resetn(ctrl_pipereg_resetn),
.d(mux2to1_pipereg_d_out),
.squashn(ctrl_pipereg_squashn),
.en(ctrl_pipereg_en),
.q(pipereg_q));
defparam
pipereg.WIDTH=32;
pipereg pipereg1 (
.clk(clk),
.resetn(ctrl_pipereg1_resetn),
.d(ifetch_instr_index),
.squashn(ctrl_pipereg1_squashn),
.en(ctrl_pipereg1_en),
.q(pipereg1_q));
defparam
pipereg1.WIDTH=26;
pipereg pipereg2 (
.clk(clk),
.resetn(ctrl_pipereg2_resetn),
.d(ifetch_sa),
.squashn(ctrl_pipereg2_squashn),
.en(ctrl_pipereg2_en),
.q(pipereg2_q));
defparam
pipereg2.WIDTH=5;
pipereg pipereg5 (
.clk(clk),
.resetn(ctrl_pipereg5_resetn),
.d(zeroer4_q),
.squashn(ctrl_pipereg5_squashn),
.en(ctrl_pipereg5_en),
.q(pipereg5_q));
defparam
pipereg5.WIDTH=5;
pipereg pipereg3 (
.clk(clk),
.resetn(ctrl_pipereg3_resetn),
.d(ifetch_pc_out),
.squashn(ctrl_pipereg3_squashn),
.en(ctrl_pipereg3_en),
.q(pipereg3_q));
defparam
pipereg3.WIDTH=32;
fakedelay fakedelay (
.clk(clk),
.d(ifetch_pc_out),
.q(fakedelay_q));
defparam
fakedelay.WIDTH=32;
nop nop (
.d(mux3to1_nop_d_out),
.q(nop_q));
defparam
nop.WIDTH=32;
zeroer zeroer (
.d(ifetch_rs),
.en(ctrl_zeroer_en),
.q(zeroer_q));
defparam
zeroer.WIDTH=5;
zeroer zeroer0 (
.d(ifetch_rt),
.en(ctrl_zeroer0_en),
.q(zeroer0_q));
defparam
zeroer0.WIDTH=5;
zeroer zeroer4 (
.d(mux3to1_zeroer4_d_out),
.en(ctrl_zeroer4_en),
.q(zeroer4_q));
defparam
zeroer4.WIDTH=5;
// Multiplexor mux3to1_shifter_sa instantiation
assign mux3to1_shifter_sa_out =
(ctrl_mux3to1_shifter_sa_sel==2) ? reg_file_a_readdataout :
(ctrl_mux3to1_shifter_sa_sel==1) ? const7_out :
pipereg2_q;
// Multiplexor mux3to1_ifetch_load_data instantiation
assign mux3to1_ifetch_load_data_out =
(ctrl_mux3to1_ifetch_load_data_sel==2) ? pcadder_result :
(ctrl_mux3to1_ifetch_load_data_sel==1) ? merge26lo_out :
reg_file_a_readdataout;
// Multiplexor mux6to1_ifetch_load instantiation
assign mux6to1_ifetch_load_out =
(ctrl_mux6to1_ifetch_load_sel==5) ? branchresolve_eq :
(ctrl_mux6to1_ifetch_load_sel==4) ? branchresolve_ne :
(ctrl_mux6to1_ifetch_load_sel==3) ? branchresolve_lez :
(ctrl_mux6to1_ifetch_load_sel==2) ? branchresolve_ltz :
(ctrl_mux6to1_ifetch_load_sel==1) ? branchresolve_gez :
branchresolve_gtz;
// Multiplexor mux7to1_reg_file_c_writedatain instantiation
assign mux7to1_reg_file_c_writedatain_out =
(ctrl_mux7to1_reg_file_c_writedatain_sel==6) ? addersub_result :
(ctrl_mux7to1_reg_file_c_writedatain_sel==5) ? addersub_result_slt :
(ctrl_mux7to1_reg_file_c_writedatain_sel==4) ? logic_unit_result :
(ctrl_mux7to1_reg_file_c_writedatain_sel==3) ? shifter_result :
(ctrl_mux7to1_reg_file_c_writedatain_sel==2) ? data_mem_d_loadresult :
(ctrl_mux7to1_reg_file_c_writedatain_sel==8) ? tempFifoDataInNorth : //Deepak
(ctrl_mux7to1_reg_file_c_writedatain_sel==9) ? tempFifoDataInSouth : //Deepak
(ctrl_mux7to1_reg_file_c_writedatain_sel==10)? tempFifoDataInEast : //Deepak
(ctrl_mux7to1_reg_file_c_writedatain_sel==11)? tempFifoDataInWest : //Deepak
(ctrl_mux7to1_reg_file_c_writedatain_sel==12)? northEmpty : //Deepak
(ctrl_mux7to1_reg_file_c_writedatain_sel==13)? southEmpty : //Deepak
(ctrl_mux7to1_reg_file_c_writedatain_sel==14)? eastEmpty : //Deepak
(ctrl_mux7to1_reg_file_c_writedatain_sel==15)? westEmpty : //Deepak
(ctrl_mux7to1_reg_file_c_writedatain_sel==16)? northFull : //Deepak
(ctrl_mux7to1_reg_file_c_writedatain_sel==17)? southFull : //Deepak
(ctrl_mux7to1_reg_file_c_writedatain_sel==18)? eastFull : //Deepak
(ctrl_mux7to1_reg_file_c_writedatain_sel==19)? westFull : //Deepak
(ctrl_mux7to1_reg_file_c_writedatain_sel==1) ? hi_reg_q :
lo_reg_q;
// Multiplexor mux2to1_addersub_opA instantiation
assign mux2to1_addersub_opA_out =
(ctrl_mux2to1_addersub_opA_sel==1) ? fakedelay_q :
reg_file_a_readdataout;
// Multiplexor mux2to1_pipereg_d instantiation
assign mux2to1_pipereg_d_out =
(ctrl_mux2to1_pipereg_d_sel==1) ? ifetch_offset :
signext16_out;
// Multiplexor mux3to1_zeroer4_d instantiation
assign mux3to1_zeroer4_d_out =
(ctrl_mux3to1_zeroer4_d_sel==2) ? ifetch_rt :
(ctrl_mux3to1_zeroer4_d_sel==1) ? ifetch_rd :
const_out;
// Multiplexor mux3to1_nop_d instantiation
assign mux3to1_nop_d_out =
(ctrl_mux3to1_nop_d_sel==2) ? pipereg_q :
(ctrl_mux3to1_nop_d_sel==1) ? reg_file_b_readdataout :
const6_out;
pipereg pipereg8 (
.clk(clk),
.resetn(ctrl_pipereg8_resetn),
.d(ifetch_opcode),
.squashn(ctrl_pipereg8_squashn),
.en(ctrl_pipereg8_en),
.q(pipereg8_q));
defparam
pipereg8.WIDTH=6;
pipereg pipereg9 (
.clk(clk),
.resetn(ctrl_pipereg9_resetn),
.d(ifetch_func),
.squashn(ctrl_pipereg9_squashn),
.en(ctrl_pipereg9_en),
.q(pipereg9_q));
defparam
pipereg9.WIDTH=6;
pipereg pipereg10 (
.clk(clk),
.resetn(ctrl_pipereg10_resetn),
.d(ifetch_rt),
.squashn(ctrl_pipereg10_squashn),
.en(ctrl_pipereg10_en),
.q(pipereg10_q));
defparam
pipereg10.WIDTH=5;
endmodule
|
`timescale 1ns / 1ns
module system50(clk,resetn,boot_iaddr,boot_idata,boot_daddr,boot_ddata,reg_file_b_readdataout,processor_select);
input clk;
input resetn;
input [6:0] processor_select;
output [31:0] reg_file_b_readdataout;
input [13:0] boot_iaddr;
input [31:0] boot_idata;
input [13:0] boot_daddr;
input [31:0] boot_ddata;
reg boot_iwe0;
reg boot_dwe0;
reg boot_iwe1;
reg boot_dwe1;
reg boot_iwe2;
reg boot_dwe2;
reg boot_iwe3;
reg boot_dwe3;
reg boot_iwe4;
reg boot_dwe4;
reg boot_iwe5;
reg boot_dwe5;
reg boot_iwe6;
reg boot_dwe6;
reg boot_iwe7;
reg boot_dwe7;
reg boot_iwe8;
reg boot_dwe8;
reg boot_iwe9;
reg boot_dwe9;
reg boot_iwe10;
reg boot_dwe10;
reg boot_iwe11;
reg boot_dwe11;
reg boot_iwe12;
reg boot_dwe12;
reg boot_iwe13;
reg boot_dwe13;
reg boot_iwe14;
reg boot_dwe14;
reg boot_iwe15;
reg boot_dwe15;
reg boot_iwe16;
reg boot_dwe16;
reg boot_iwe17;
reg boot_dwe17;
reg boot_iwe18;
reg boot_dwe18;
reg boot_iwe19;
reg boot_dwe19;
reg boot_iwe20;
reg boot_dwe20;
reg boot_iwe21;
reg boot_dwe21;
reg boot_iwe22;
reg boot_dwe22;
reg boot_iwe23;
reg boot_dwe23;
reg boot_iwe24;
reg boot_dwe24;
reg boot_iwe25;
reg boot_dwe25;
reg boot_iwe26;
reg boot_dwe26;
reg boot_iwe27;
reg boot_dwe27;
reg boot_iwe28;
reg boot_dwe28;
reg boot_iwe29;
reg boot_dwe29;
reg boot_iwe30;
reg boot_dwe30;
reg boot_iwe31;
reg boot_dwe31;
reg boot_iwe32;
reg boot_dwe32;
reg boot_iwe33;
reg boot_dwe33;
reg boot_iwe34;
reg boot_dwe34;
reg boot_iwe35;
reg boot_dwe35;
reg boot_iwe36;
reg boot_dwe36;
reg boot_iwe37;
reg boot_dwe37;
reg boot_iwe38;
reg boot_dwe38;
reg boot_iwe39;
reg boot_dwe39;
reg boot_iwe40;
reg boot_dwe40;
reg boot_iwe41;
reg boot_dwe41;
reg boot_iwe42;
reg boot_dwe42;
reg boot_iwe43;
reg boot_dwe43;
reg boot_iwe44;
reg boot_dwe44;
reg boot_iwe45;
reg boot_dwe45;
reg boot_iwe46;
reg boot_dwe46;
reg boot_iwe47;
reg boot_dwe47;
reg boot_iwe48;
reg boot_dwe48;
reg boot_iwe49;
reg boot_dwe49;
//Processor 0 control and data signals
wire wrProc0South;
wire fullProc0South;
wire [31:0] dataOutProc0South;
//Processor 0 control and data signals
wire rdProc0East;
wire emptyProc0East;
wire [31:0] dataInProc0East;
//Processor 0 control and data signals
wire wrProc0East;
wire fullProc0East;
wire [31:0] dataOutProc0East;
//Processor 1 control and data signals
wire rdProc1West;
wire emptyProc1West;
wire [31:0] dataInProc1West;
//Processor 1 control and data signals
wire wrProc1West;
wire fullProc1West;
wire [31:0] dataOutProc1West;
//Processor 2 control and data signals
wire rdProc2East;
wire emptyProc2East;
wire [31:0] dataInProc2East;
//Processor 3 control and data signals
wire rdProc3East;
wire emptyProc3East;
wire [31:0] dataInProc3East;
//Processor 3 control and data signals
wire wrProc3West;
wire fullProc3West;
wire [31:0] dataOutProc3West;
//Processor 4 control and data signals
wire rdProc4East;
wire emptyProc4East;
wire [31:0] dataInProc4East;
//Processor 4 control and data signals
wire wrProc4West;
wire fullProc4West;
wire [31:0] dataOutProc4West;
//Processor 5 control and data signals
wire rdProc5East;
wire emptyProc5East;
wire [31:0] dataInProc5East;
//Processor 5 control and data signals
wire wrProc5West;
wire fullProc5West;
wire [31:0] dataOutProc5West;
//Processor 6 control and data signals
wire rdProc6South;
wire emptyProc6South;
wire [31:0] dataInProc6South;
//Processor 6 control and data signals
wire wrProc6South;
wire fullProc6South;
wire [31:0] dataOutProc6South;
//Processor 6 control and data signals
wire rdProc6East;
wire emptyProc6East;
wire [31:0] dataInProc6East;
//Processor 6 control and data signals
wire wrProc6West;
wire fullProc6West;
wire [31:0] dataOutProc6West;
//Processor 7 control and data signals
wire wrProc7South;
wire fullProc7South;
wire [31:0] dataOutProc7South;
//Processor 7 control and data signals
wire rdProc7East;
wire emptyProc7East;
wire [31:0] dataInProc7East;
//Processor 7 control and data signals
wire wrProc7West;
wire fullProc7West;
wire [31:0] dataOutProc7West;
//Processor 8 control and data signals
wire rdProc8South;
wire emptyProc8South;
wire [31:0] dataInProc8South;
//Processor 8 control and data signals
wire rdProc8East;
wire emptyProc8East;
wire [31:0] dataInProc8East;
//Processor 8 control and data signals
wire wrProc8West;
wire fullProc8West;
wire [31:0] dataOutProc8West;
//Processor 9 control and data signals
wire rdProc9South;
wire emptyProc9South;
wire [31:0] dataInProc9South;
//Processor 9 control and data signals
wire wrProc9West;
wire fullProc9West;
wire [31:0] dataOutProc9West;
//Processor 10 control and data signals
wire rdProc10North;
wire emptyProc10North;
wire [31:0] dataInProc10North;
//Processor 10 control and data signals
wire wrProc10South;
wire fullProc10South;
wire [31:0] dataOutProc10South;
//Processor 11 control and data signals
wire rdProc11South;
wire emptyProc11South;
wire [31:0] dataInProc11South;
//Processor 11 control and data signals
wire wrProc11East;
wire fullProc11East;
wire [31:0] dataOutProc11East;
//Processor 12 control and data signals
wire rdProc12South;
wire emptyProc12South;
wire [31:0] dataInProc12South;
//Processor 12 control and data signals
wire wrProc12South;
wire fullProc12South;
wire [31:0] dataOutProc12South;
//Processor 12 control and data signals
wire wrProc12East;
wire fullProc12East;
wire [31:0] dataOutProc12East;
//Processor 12 control and data signals
wire rdProc12West;
wire emptyProc12West;
wire [31:0] dataInProc12West;
//Processor 13 control and data signals
wire wrProc13East;
wire fullProc13East;
wire [31:0] dataOutProc13East;
//Processor 13 control and data signals
wire rdProc13West;
wire emptyProc13West;
wire [31:0] dataInProc13West;
//Processor 14 control and data signals
wire rdProc14South;
wire emptyProc14South;
wire [31:0] dataInProc14South;
//Processor 14 control and data signals
wire wrProc14South;
wire fullProc14South;
wire [31:0] dataOutProc14South;
//Processor 14 control and data signals
wire rdProc14East;
wire emptyProc14East;
wire [31:0] dataInProc14East;
//Processor 14 control and data signals
wire wrProc14East;
wire fullProc14East;
wire [31:0] dataOutProc14East;
//Processor 14 control and data signals
wire rdProc14West;
wire emptyProc14West;
wire [31:0] dataInProc14West;
//Processor 15 control and data signals
wire wrProc15South;
wire fullProc15South;
wire [31:0] dataOutProc15South;
//Processor 15 control and data signals
wire rdProc15East;
wire emptyProc15East;
wire [31:0] dataInProc15East;
//Processor 15 control and data signals
wire wrProc15East;
wire fullProc15East;
wire [31:0] dataOutProc15East;
//Processor 15 control and data signals
wire rdProc15West;
wire emptyProc15West;
wire [31:0] dataInProc15West;
//Processor 15 control and data signals
wire wrProc15West;
wire fullProc15West;
wire [31:0] dataOutProc15West;
//Processor 16 control and data signals
wire rdProc16North;
wire emptyProc16North;
wire [31:0] dataInProc16North;
//Processor 16 control and data signals
wire wrProc16North;
wire fullProc16North;
wire [31:0] dataOutProc16North;
//Processor 16 control and data signals
wire rdProc16South;
wire emptyProc16South;
wire [31:0] dataInProc16South;
//Processor 16 control and data signals
wire wrProc16South;
wire fullProc16South;
wire [31:0] dataOutProc16South;
//Processor 16 control and data signals
wire rdProc16East;
wire emptyProc16East;
wire [31:0] dataInProc16East;
//Processor 16 control and data signals
wire rdProc16West;
wire emptyProc16West;
wire [31:0] dataInProc16West;
//Processor 16 control and data signals
wire wrProc16West;
wire fullProc16West;
wire [31:0] dataOutProc16West;
//Processor 17 control and data signals
wire rdProc17North;
wire emptyProc17North;
wire [31:0] dataInProc17North;
//Processor 17 control and data signals
wire wrProc17West;
wire fullProc17West;
wire [31:0] dataOutProc17West;
//Processor 18 control and data signals
wire wrProc18North;
wire fullProc18North;
wire [31:0] dataOutProc18North;
//Processor 18 control and data signals
wire rdProc18South;
wire emptyProc18South;
wire [31:0] dataInProc18South;
//Processor 18 control and data signals
wire rdProc18East;
wire emptyProc18East;
wire [31:0] dataInProc18East;
//Processor 18 control and data signals
wire wrProc18East;
wire fullProc18East;
wire [31:0] dataOutProc18East;
//Processor 19 control and data signals
wire wrProc19North;
wire fullProc19North;
wire [31:0] dataOutProc19North;
//Processor 19 control and data signals
wire rdProc19South;
wire emptyProc19South;
wire [31:0] dataInProc19South;
//Processor 19 control and data signals
wire rdProc19West;
wire emptyProc19West;
wire [31:0] dataInProc19West;
//Processor 19 control and data signals
wire wrProc19West;
wire fullProc19West;
wire [31:0] dataOutProc19West;
//Processor 20 control and data signals
wire rdProc20North;
wire emptyProc20North;
wire [31:0] dataInProc20North;
//Processor 20 control and data signals
wire wrProc20South;
wire fullProc20South;
wire [31:0] dataOutProc20South;
//Processor 21 control and data signals
wire wrProc21North;
wire fullProc21North;
wire [31:0] dataOutProc21North;
//Processor 21 control and data signals
wire rdProc21South;
wire emptyProc21South;
wire [31:0] dataInProc21South;
//Processor 21 control and data signals
wire wrProc21East;
wire fullProc21East;
wire [31:0] dataOutProc21East;
//Processor 22 control and data signals
wire rdProc22North;
wire emptyProc22North;
wire [31:0] dataInProc22North;
//Processor 22 control and data signals
wire wrProc22North;
wire fullProc22North;
wire [31:0] dataOutProc22North;
//Processor 22 control and data signals
wire rdProc22South;
wire emptyProc22South;
wire [31:0] dataInProc22South;
//Processor 22 control and data signals
wire wrProc22East;
wire fullProc22East;
wire [31:0] dataOutProc22East;
//Processor 22 control and data signals
wire rdProc22West;
wire emptyProc22West;
wire [31:0] dataInProc22West;
//Processor 23 control and data signals
wire rdProc23South;
wire emptyProc23South;
wire [31:0] dataInProc23South;
//Processor 23 control and data signals
wire wrProc23East;
wire fullProc23East;
wire [31:0] dataOutProc23East;
//Processor 23 control and data signals
wire rdProc23West;
wire emptyProc23West;
wire [31:0] dataInProc23West;
//Processor 24 control and data signals
wire rdProc24North;
wire emptyProc24North;
wire [31:0] dataInProc24North;
//Processor 24 control and data signals
wire wrProc24North;
wire fullProc24North;
wire [31:0] dataOutProc24North;
//Processor 24 control and data signals
wire wrProc24South;
wire fullProc24South;
wire [31:0] dataOutProc24South;
//Processor 24 control and data signals
wire wrProc24East;
wire fullProc24East;
wire [31:0] dataOutProc24East;
//Processor 24 control and data signals
wire rdProc24West;
wire emptyProc24West;
wire [31:0] dataInProc24West;
//Processor 25 control and data signals
wire rdProc25North;
wire emptyProc25North;
wire [31:0] dataInProc25North;
//Processor 25 control and data signals
wire wrProc25South;
wire fullProc25South;
wire [31:0] dataOutProc25South;
//Processor 25 control and data signals
wire wrProc25East;
wire fullProc25East;
wire [31:0] dataOutProc25East;
//Processor 25 control and data signals
wire rdProc25West;
wire emptyProc25West;
wire [31:0] dataInProc25West;
//Processor 26 control and data signals
wire rdProc26North;
wire emptyProc26North;
wire [31:0] dataInProc26North;
//Processor 26 control and data signals
wire wrProc26North;
wire fullProc26North;
wire [31:0] dataOutProc26North;
//Processor 26 control and data signals
wire rdProc26South;
wire emptyProc26South;
wire [31:0] dataInProc26South;
//Processor 26 control and data signals
wire wrProc26South;
wire fullProc26South;
wire [31:0] dataOutProc26South;
//Processor 26 control and data signals
wire rdProc26East;
wire emptyProc26East;
wire [31:0] dataInProc26East;
//Processor 26 control and data signals
wire wrProc26East;
wire fullProc26East;
wire [31:0] dataOutProc26East;
//Processor 26 control and data signals
wire rdProc26West;
wire emptyProc26West;
wire [31:0] dataInProc26West;
//Processor 27 control and data signals
wire rdProc27South;
wire Proc27South;
wire [31:0] dataInProc27South;
//Processor 27 control and data signals
wire wrProc27East;
wire fullProc27East;
wire [31:0] dataOutProc27East;
//Processor 27 control and data signals
wire rdProc27West;
wire emptyProc27West;
wire [31:0] dataInProc27West;
//Processor 27 control and data signals
wire wrProc27West;
wire fullProc27West;
wire [31:0] dataOutProc27West;
//Processor 28 control and data signals
wire wrProc28North;
wire fullProc28North;
wire [31:0] dataOutProc28North;
//Processor 28 control and data signals
wire wrProc28East;
wire fullProc28East;
wire [31:0] dataOutProc28East;
//Processor 28 control and data signals
wire rdProc28West;
wire emptyProc28West;
wire [31:0] dataInProc28West;
//Processor 29 control and data signals
wire wrProc29North;
wire fullProc29North;
wire [31:0] dataOutProc29North;
//Processor 29 control and data signals
wire rdProc29West;
wire emptyProc29West;
wire [31:0] dataInProc29West;
//Processor 30 control and data signals
wire rdProc30North;
wire emptyProc30North;
wire [31:0] dataInProc30North;
//Processor 30 control and data signals
wire wrProc30South;
wire fullProc30South;
wire [31:0] dataOutProc30South;
//Processor 30 control and data signals
wire wrProc30East;
wire fullProc30East;
wire [31:0] dataOutProc30East;
//Processor 31 control and data signals
wire wrProc31North;
wire fullProc31North;
wire [31:0] dataOutProc31North;
//Processor 31 control and data signals
wire rdProc31South;
wire emptyProc31South;
wire [31:0] dataInProc31South;
//Processor 31 control and data signals
wire wrProc31South;
wire fullProc31South;
wire [31:0] dataOutProc31South;
//Processor 31 control and data signals
wire rdProc31East;
wire emptyProc31East;
wire [31:0] dataInProc31East;
//Processor 31 control and data signals
wire rdProc31West;
wire emptyProc31West;
wire [31:0] dataInProc31West;
//Processor 32 control and data signals
wire wrProc32North;
wire fullProc32North;
wire [31:0] dataOutProc32North;
//Processor 32 control and data signals
wire rdProc32South;
wire emptyProc32South;
wire [31:0] dataInProc32South;
//Processor 32 control and data signals
wire wrProc32East;
wire fullProc32East;
wire [31:0] dataOutProc32East;
//Processor 32 control and data signals
wire wrProc32West;
wire fullProc32West;
wire [31:0] dataOutProc32West;
//Processor 33 control and data signals
wire wrProc33North;
wire fullProc33North;
wire [31:0] dataOutProc33North;
//Processor 33 control and data signals
wire rdProc33West;
wire emptyProc33West;
wire [31:0] dataInProc33West;
//Processor 34 control and data signals
wire rdProc34North;
wire emptyProc34North;
wire [31:0] dataInProc34North;
//Processor 34 control and data signals
wire wrProc34South;
wire fullProc34South;
wire [31:0] dataOutProc34South;
//Processor 35 control and data signals
wire rdProc35North;
wire emptyProc35North;
wire [31:0] dataInProc35North;
//Processor 35 control and data signals
wire wrProc35South;
wire fullProc35South;
wire [31:0] dataOutProc35South;
//Processor 35 control and data signals
wire wrProc35East;
wire fullProc35East;
wire [31:0] dataOutProc35East;
//Processor 36 control and data signals
wire rdProc36North;
wire emptyProc36North;
wire [31:0] dataInProc36North;
//Processor 36 control and data signals
wire wrProc36North;
wire fullProc36North;
wire [31:0] dataOutProc36North;
//Processor 36 control and data signals
wire wrProc36South;
wire fullProc36South;
wire [31:0] dataOutProc36South;
//Processor 36 control and data signals
wire rdProc36East;
wire emptyProc36East;
wire [31:0] dataInProc36East;
//Processor 36 control and data signals
wire wrProc36East;
wire fullProc36East;
wire [31:0] dataOutProc36East;
//Processor 36 control and data signals
wire rdProc36West;
wire emptyProc36West;
wire [31:0] dataInProc36West;
//Processor 37 control and data signals
wire wrProc37North;
wire fullProc37North;
wire [31:0] dataOutProc37North;
//Processor 37 control and data signals
wire wrProc37South;
wire fullProc37South;
wire [31:0] dataOutProc37South;
//Processor 37 control and data signals
wire rdProc37East;
wire emptyProc37East;
wire [31:0] dataInProc37East;
//Processor 37 control and data signals
wire rdProc37West;
wire emptyProc37West;
wire [31:0] dataInProc37West;
//Processor 37 control and data signals
wire wrProc37West;
wire fullProc37West;
wire [31:0] dataOutProc37West;
//Processor 38 control and data signals
wire rdProc38South;
wire emptyProc38South;
wire [31:0] dataInProc38South;
//Processor 38 control and data signals
wire rdProc38East;
wire emptyProc38East;
wire [31:0] dataInProc38East;
//Processor 38 control and data signals
wire wrProc38East;
wire fullProc38East;
wire [31:0] dataOutProc38East;
//Processor 38 control and data signals
wire wrProc38West;
wire fullProc38West;
wire [31:0] dataOutProc38West;
//Processor 39 control and data signals
wire rdProc39West;
wire emptyProc39West;
wire [31:0] dataInProc39West;
//Processor 39 control and data signals
wire wrProc39West;
wire fullProc39West;
wire [31:0] dataOutProc39West;
//Processor 40 control and data signals
wire rdProc40North;
wire emptyProc40North;
wire [31:0] dataInProc40North;
//Processor 40 control and data signals
wire wrProc40East;
wire fullProc40East;
wire [31:0] dataOutProc40East;
//Processor 41 control and data signals
wire rdProc41North;
wire emptyProc41North;
wire [31:0] dataInProc41North;
//Processor 41 control and data signals
wire wrProc41North;
wire fullProc41North;
wire [31:0] dataOutProc41North;
//Processor 41 control and data signals
wire wrProc41East;
wire fullProc41East;
wire [31:0] dataOutProc41East;
//Processor 41 control and data signals
wire rdProc41West;
wire emptyProc41West;
wire [31:0] dataInProc41West;
//Processor 42 control and data signals
wire wrProc42North;
wire fullProc42North;
wire [31:0] dataOutProc42North;
//Processor 42 control and data signals
wire rdProc42East;
wire emptyProc42East;
wire [31:0] dataInProc42East;
//Processor 42 control and data signals
wire rdProc42West;
wire emptyProc42West;
wire [31:0] dataInProc42West;
//Processor 43 control and data signals
wire rdProc43East;
wire emptyProc43East;
wire [31:0] dataInProc43East;
//Processor 43 control and data signals
wire wrProc43West;
wire fullProc43West;
wire [31:0] dataOutProc43West;
//Processor 44 control and data signals
wire rdProc44North;
wire emptyProc44North;
wire [31:0] dataInProc44North;
//Processor 44 control and data signals
wire rdProc44East;
wire emptyProc44East;
wire [31:0] dataInProc44East;
//Processor 44 control and data signals
wire wrProc44West;
wire fullProc44West;
wire [31:0] dataOutProc44West;
//Processor 45 control and data signals
wire rdProc45North;
wire emptyProc45North;
wire [31:0] dataInProc45North;
//Processor 45 control and data signals
wire wrProc45West;
wire fullProc45West;
wire [31:0] dataOutProc45West;
//Processor 46 control and data signals
wire rdProc46North;
wire emptyProc46North;
wire [31:0] dataInProc46North;
//Processor 46 control and data signals
wire wrProc46East;
wire fullProc46East;
wire [31:0] dataOutProc46East;
//Processor 47 control and data signals
wire rdProc47North;
wire emptyProc47North;
wire [31:0] dataInProc47North;
//Processor 47 control and data signals
wire wrProc47East;
wire fullProc47East;
wire [31:0] dataOutProc47East;
//Processor 47 control and data signals
wire rdProc47West;
wire emptyProc47West;
wire [31:0] dataInProc47West;
//Processor 48 control and data signals
wire wrProc48North;
wire fullProc48North;
wire [31:0] dataOutProc48North;
//Processor 48 control and data signals
wire rdProc48East;
wire emptyProc48East;
wire [31:0] dataInProc48East;
//Processor 48 control and data signals
wire wrProc48East;
wire fullProc48East;
wire [31:0] dataOutProc48East;
//Processor 48 control and data signals
wire rdProc48West;
wire emptyProc48West;
wire [31:0] dataInProc48West;
//Processor 49 control and data signals
wire rdProc49West;
wire emptyProc49West;
wire [31:0] dataInProc49West;
//Processor 49 control and data signals
wire wrProc49West;
wire fullProc49West;
wire [31:0] dataOutProc49West;
//PROCESSOR 0
system proc0(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe0),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe0),
.wrSouth(wrProc0South),
.fullSouth(fullProc0South),
.dataOutSouth(dataOutProc0South),
.rdEast(rdProc0East),
.emptyEast(emptyProc0East),
.dataInEast(dataInProc0East),
.wrEast(wrProc0East),
.fullEast(fullProc0East),
.dataOutEast(dataOutProc0East));
//PROCESSOR 1
system proc1(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe1),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe1),
.rdWest(rdProc1West),
.emptyWest(emptyProc1West),
.dataInWest(dataInProc1West),
.wrWest(wrProc1West),
.fullWest(fullProc1West),
.dataOutWest(dataOutProc1West));
//PROCESSOR 2
system proc2(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe2),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe2),
.rdEast(rdProc2East),
.emptyEast(emptyProc2East),
.dataInEast(dataInProc2East),
.reg_file_b_readdataout(reg_file_b_readdataout));
//PROCESSOR 3
system proc3(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe3),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe3),
.rdEast(rdProc3East),
.emptyEast(emptyProc3East),
.dataInEast(dataInProc3East),
.wrWest(wrProc3West),
.fullWest(fullProc3West),
.dataOutWest(dataOutProc3West));
//PROCESSOR 4
system proc4(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe4),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe4),
.rdEast(rdProc4East),
.emptyEast(emptyProc4East),
.dataInEast(dataInProc4East),
.wrWest(wrProc4West),
.fullWest(fullProc4West),
.dataOutWest(dataOutProc4West));
//PROCESSOR 5
system proc5(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe5),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe5),
.rdEast(rdProc5East),
.emptyEast(emptyProc5East),
.dataInEast(dataInProc5East),
.wrWest(wrProc5West),
.fullWest(fullProc5West),
.dataOutWest(dataOutProc5West));
//PROCESSOR 6
system proc6(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe6),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe6),
.rdSouth(rdProc6South),
.emptySouth(emptyProc6South),
.dataInSouth(dataInProc6South),
.wrSouth(wrProc6South),
.fullSouth(fullProc6South),
.dataOutSouth(dataOutProc6South),
.rdEast(rdProc6East),
.emptyEast(emptyProc6East),
.dataInEast(dataInProc6East),
.wrWest(wrProc6West),
.fullWest(fullProc6West),
.dataOutWest(dataOutProc6West));
//PROCESSOR 7
system proc7(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe7),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe7),
.wrSouth(wrProc7South),
.fullSouth(fullProc7South),
.dataOutSouth(dataOutProc7South),
.rdEast(rdProc7East),
.emptyEast(emptyProc7East),
.dataInEast(dataInProc7East),
.wrWest(wrProc7West),
.fullWest(fullProc7West),
.dataOutWest(dataOutProc7West));
//PROCESSOR 8
system proc8(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe8),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe8),
.rdSouth(rdProc8South),
.emptySouth(emptyProc8South),
.dataInSouth(dataInProc8South),
.rdEast(rdProc8East),
.emptyEast(emptyProc8East),
.dataInEast(dataInProc8East),
.wrWest(wrProc8West),
.fullWest(fullProc8West),
.dataOutWest(dataOutProc8West));
//PROCESSOR 9
system proc9(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe9),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe9),
.rdSouth(rdProc9South),
.emptySouth(emptyProc9South),
.dataInSouth(dataInProc9South),
.wrWest(wrProc9West),
.fullWest(fullProc9West),
.dataOutWest(dataOutProc9West));
//PROCESSOR 10
system proc10(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe10),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe10),
.rdNorth(rdProc10North),
.emptyNorth(emptyProc10North),
.dataInNorth(dataInProc10North),
.wrSouth(wrProc10South),
.fullSouth(fullProc10South),
.dataOutSouth(dataOutProc10South));
//PROCESSOR 11
system proc11(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe11),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe11),
.rdSouth(rdProc11South),
.emptySouth(emptyProc11South),
.dataInSouth(dataInProc11South),
.wrEast(wrProc11East),
.fullEast(fullProc11East),
.dataOutEast(dataOutProc11East));
//PROCESSOR 12
system proc12(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe12),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe12),
.rdSouth(rdProc12South),
.emptySouth(emptyProc12South),
.dataInSouth(dataInProc12South),
.wrSouth(wrProc12South),
.fullSouth(fullProc12South),
.dataOutSouth(dataOutProc12South),
.wrEast(wrProc12East),
.fullEast(fullProc12East),
.dataOutEast(dataOutProc12East),
.rdWest(rdProc12West),
.emptyWest(emptyProc12West),
.dataInWest(dataInProc12West));
//PROCESSOR 13
system proc13(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe13),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe13),
.wrEast(wrProc13East),
.fullEast(fullProc13East),
.dataOutEast(dataOutProc13East),
.rdWest(rdProc13West),
.emptyWest(emptyProc13West),
.dataInWest(dataInProc13West));
//PROCESSOR 14
system proc14(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe14),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe14),
.rdSouth(rdProc14South),
.emptySouth(emptyProc14South),
.dataInSouth(dataInProc14South),
.wrSouth(wrProc14South),
.fullSouth(fullProc14South),
.dataOutSouth(dataOutProc14South),
.rdEast(rdProc14East),
.emptyEast(emptyProc14East),
.dataInEast(dataInProc14East),
.wrEast(wrProc14East),
.fullEast(fullProc14East),
.dataOutEast(dataOutProc14East),
.rdWest(rdProc14West),
.emptyWest(emptyProc14West),
.dataInWest(dataInProc14West));
//PROCESSOR 15
system proc15(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe15),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe15),
.wrSouth(wrProc15South),
.fullSouth(fullProc15South),
.dataOutSouth(dataOutProc15South),
.rdEast(rdProc15East),
.emptyEast(emptyProc15East),
.dataInEast(dataInProc15East),
.wrEast(wrProc15East),
.fullEast(fullProc15East),
.dataOutEast(dataOutProc15East),
.rdWest(rdProc15West),
.emptyWest(emptyProc15West),
.dataInWest(dataInProc15West),
.wrWest(wrProc15West),
.fullWest(fullProc15West),
.dataOutWest(dataOutProc15West));
//PROCESSOR 16
system proc16(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe16),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe16),
.rdNorth(rdProc16North),
.emptyNorth(emptyProc16North),
.dataInNorth(dataInProc16North),
.wrNorth(wrProc16North),
.fullNorth(fullProc16North),
.dataOutNorth(dataOutProc16North),
.rdSouth(rdProc16South),
.emptySouth(emptyProc16South),
.dataInSouth(dataInProc16South),
.wrSouth(wrProc16South),
.fullSouth(fullProc16South),
.dataOutSouth(dataOutProc16South),
.rdEast(rdProc16East),
.emptyEast(emptyProc16East),
.dataInEast(dataInProc16East),
.rdWest(rdProc16West),
.emptyWest(emptyProc16West),
.dataInWest(dataInProc16West),
.wrWest(wrProc16West),
.fullWest(fullProc16West),
.dataOutWest(dataOutProc16West));
//PROCESSOR 17
system proc17(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe17),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe17),
.rdNorth(rdProc17North),
.emptyNorth(emptyProc17North),
.dataInNorth(dataInProc17North),
.wrWest(wrProc17West),
.fullWest(fullProc17West),
.dataOutWest(dataOutProc17West));
//PROCESSOR 18
system proc18(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe18),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe18),
.wrNorth(wrProc18North),
.fullNorth(fullProc18North),
.dataOutNorth(dataOutProc18North),
.rdSouth(rdProc18South),
.emptySouth(emptyProc18South),
.dataInSouth(dataInProc18South),
.rdEast(rdProc18East),
.emptyEast(emptyProc18East),
.dataInEast(dataInProc18East),
.wrEast(wrProc18East),
.fullEast(fullProc18East),
.dataOutEast(dataOutProc18East));
//PROCESSOR 19
system proc19(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe19),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe19),
.wrNorth(wrProc19North),
.fullNorth(fullProc19North),
.dataOutNorth(dataOutProc19North),
.rdSouth(rdProc19South),
.emptySouth(emptyProc19South),
.dataInSouth(dataInProc19South),
.rdWest(rdProc19West),
.emptyWest(emptyProc19West),
.dataInWest(dataInProc19West),
.wrWest(wrProc19West),
.fullWest(fullProc19West),
.dataOutWest(dataOutProc19West));
//PROCESSOR 20
system proc20(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe20),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe20),
.rdNorth(rdProc20North),
.emptyNorth(emptyProc20North),
.dataInNorth(dataInProc20North),
.wrSouth(wrProc20South),
.fullSouth(fullProc20South),
.dataOutSouth(dataOutProc20South));
//PROCESSOR 21
system proc21(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe21),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe21),
.wrNorth(wrProc21North),
.fullNorth(fullProc21North),
.dataOutNorth(dataOutProc21North),
.rdSouth(rdProc21South),
.emptySouth(emptyProc21South),
.dataInSouth(dataInProc21South),
.wrEast(wrProc21East),
.fullEast(fullProc21East),
.dataOutEast(dataOutProc21East));
//PROCESSOR 22
system proc22(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe22),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe22),
.rdNorth(rdProc22North),
.emptyNorth(emptyProc22North),
.dataInNorth(dataInProc22North),
.wrNorth(wrProc22North),
.fullNorth(fullProc22North),
.dataOutNorth(dataOutProc22North),
.rdSouth(rdProc22South),
.emptySouth(emptyProc22South),
.dataInSouth(dataInProc22South),
.wrEast(wrProc22East),
.fullEast(fullProc22East),
.dataOutEast(dataOutProc22East),
.rdWest(rdProc22West),
.emptyWest(emptyProc22West),
.dataInWest(dataInProc22West));
//PROCESSOR 23
system proc23(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe23),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe23),
.rdSouth(rdProc23South),
.emptySouth(emptyProc23South),
.dataInSouth(dataInProc23South),
.wrEast(wrProc23East),
.fullEast(fullProc23East),
.dataOutEast(dataOutProc23East),
.rdWest(rdProc23West),
.emptyWest(emptyProc23West),
.dataInWest(dataInProc23West));
//PROCESSOR 24
system proc24(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe24),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe24),
.rdNorth(rdProc24North),
.emptyNorth(emptyProc24North),
.dataInNorth(dataInProc24North),
.wrNorth(wrProc24North),
.fullNorth(fullProc24North),
.dataOutNorth(dataOutProc24North),
.wrSouth(wrProc24South),
.fullSouth(fullProc24South),
.dataOutSouth(dataOutProc24South),
.wrEast(wrProc24East),
.fullEast(fullProc24East),
.dataOutEast(dataOutProc24East),
.rdWest(rdProc24West),
.emptyWest(emptyProc24West),
.dataInWest(dataInProc24West));
//PROCESSOR 25
system proc25(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe25),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe25),
.rdNorth(rdProc25North),
.emptyNorth(emptyProc25North),
.dataInNorth(dataInProc25North),
.wrSouth(wrProc25South),
.fullSouth(fullProc25South),
.dataOutSouth(dataOutProc25South),
.wrEast(wrProc25East),
.fullEast(fullProc25East),
.dataOutEast(dataOutProc25East),
.rdWest(rdProc25West),
.emptyWest(emptyProc25West),
.dataInWest(dataInProc25West));
//PROCESSOR 26
system proc26(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe26),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe26),
.rdNorth(rdProc26North),
.emptyNorth(emptyProc26North),
.dataInNorth(dataInProc26North),
.wrNorth(wrProc26North),
.fullNorth(fullProc26North),
.dataOutNorth(dataOutProc26North),
.rdSouth(rdProc26South),
.emptySouth(emptyProc26South),
.dataInSouth(dataInProc26South),
.wrSouth(wrProc26South),
.fullSouth(fullProc26South),
.dataOutSouth(dataOutProc26South),
.rdEast(rdProc26East),
.emptyEast(emptyProc26East),
.dataInEast(dataInProc26East),
.wrEast(wrProc26East),
.fullEast(fullProc26East),
.dataOutEast(dataOutProc26East),
.rdWest(rdProc26West),
.emptyWest(emptyProc26West),
.dataInWest(dataInProc26West));
//PROCESSOR 27
system proc27(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe27),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe27),
.rdSouth(rdProc27South),
.emptySouth(emptyProc27South),
.dataInSouth(dataInProc27South),
.wrEast(wrProc27East),
.fullEast(fullProc27East),
.dataOutEast(dataOutProc27East),
.rdWest(rdProc27West),
.emptyWest(emptyProc27West),
.dataInWest(dataInProc27West),
.wrWest(wrProc27West),
.fullWest(fullProc27West),
.dataOutWest(dataOutProc27West));
//PROCESSOR 28
system proc28(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe28),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe28),
.wrNorth(wrProc28North),
.fullNorth(fullProc28North),
.dataOutNorth(dataOutProc28North),
.wrEast(wrProc28East),
.fullEast(fullProc28East),
.dataOutEast(dataOutProc28East),
.rdWest(rdProc28West),
.emptyWest(emptyProc28West),
.dataInWest(dataInProc28West));
//PROCESSOR 29
system proc29(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe29),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe29),
.wrNorth(wrProc29North),
.fullNorth(fullProc29North),
.dataOutNorth(dataOutProc29North),
.rdWest(rdProc29West),
.emptyWest(emptyProc29West),
.dataInWest(dataInProc29West));
//PROCESSOR 30
system proc30(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe30),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe30),
.rdNorth(rdProc30North),
.emptyNorth(emptyProc30North),
.dataInNorth(dataInProc30North),
.wrSouth(wrProc30South),
.fullSouth(fullProc30South),
.dataOutSouth(dataOutProc30South),
.wrEast(wrProc30East),
.fullEast(fullProc30East),
.dataOutEast(dataOutProc30East));
//PROCESSOR 31
system proc31(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe31),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe31),
.wrNorth(wrProc31North),
.fullNorth(fullProc31North),
.dataOutNorth(dataOutProc31North),
.rdSouth(rdProc31South),
.emptySouth(emptyProc31South),
.dataInSouth(dataInProc31South),
.wrSouth(wrProc31South),
.fullSouth(fullProc31South),
.dataOutSouth(dataOutProc31South),
.rdEast(rdProc31East),
.emptyEast(emptyProc31East),
.dataInEast(dataInProc31East),
.rdWest(rdProc31West),
.emptyWest(emptyProc31West),
.dataInWest(dataInProc31West));
//PROCESSOR 32
system proc32(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe32),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe32),
.wrNorth(wrProc32North),
.fullNorth(fullProc32North),
.dataOutNorth(dataOutProc32North),
.rdSouth(rdProc32South),
.emptySouth(emptyProc32South),
.dataInSouth(dataInProc32South),
.wrEast(wrProc32East),
.fullEast(fullProc32East),
.dataOutEast(dataOutProc32East),
.wrWest(wrProc32West),
.fullWest(fullProc32West),
.dataOutWest(dataOutProc32West));
//PROCESSOR 33
system proc33(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe33),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe33),
.wrNorth(wrProc33North),
.fullNorth(fullProc33North),
.dataOutNorth(dataOutProc33North),
.rdWest(rdProc33West),
.emptyWest(emptyProc33West),
.dataInWest(dataInProc33West));
//PROCESSOR 34
system proc34(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe34),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe34),
.rdNorth(rdProc34North),
.emptyNorth(emptyProc34North),
.dataInNorth(dataInProc34North),
.wrSouth(wrProc34South),
.fullSouth(fullProc34South),
.dataOutSouth(dataOutProc34South));
//PROCESSOR 35
system proc35(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe35),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe35),
.rdNorth(rdProc35North),
.emptyNorth(emptyProc35North),
.dataInNorth(dataInProc35North),
.wrSouth(wrProc35South),
.fullSouth(fullProc35South),
.dataOutSouth(dataOutProc35South),
.wrEast(wrProc35East),
.fullEast(fullProc35East),
.dataOutEast(dataOutProc35East));
//PROCESSOR 36
system proc36(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe36),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe36),
.rdNorth(rdProc36North),
.emptyNorth(emptyProc36North),
.dataInNorth(dataInProc36North),
.wrNorth(wrProc36North),
.fullNorth(fullProc36North),
.dataOutNorth(dataOutProc36North),
.wrSouth(wrProc36South),
.fullSouth(fullProc36South),
.dataOutSouth(dataOutProc36South),
.rdEast(rdProc36East),
.emptyEast(emptyProc36East),
.dataInEast(dataInProc36East),
.wrEast(wrProc36East),
.fullEast(fullProc36East),
.dataOutEast(dataOutProc36East),
.rdWest(rdProc36West),
.emptyWest(emptyProc36West),
.dataInWest(dataInProc36West));
//PROCESSOR 37
system proc37(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe37),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe37),
.wrNorth(wrProc37North),
.fullNorth(fullProc37North),
.dataOutNorth(dataOutProc37North),
.wrSouth(wrProc37South),
.fullSouth(fullProc37South),
.dataOutSouth(dataOutProc37South),
.rdEast(rdProc37East),
.emptyEast(emptyProc37East),
.dataInEast(dataInProc37East),
.rdWest(rdProc37West),
.emptyWest(emptyProc37West),
.dataInWest(dataInProc37West),
.wrWest(wrProc37West),
.fullWest(fullProc37West),
.dataOutWest(dataOutProc37West));
//PROCESSOR 38
system proc38(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe38),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe38),
.rdSouth(rdProc38South),
.emptySouth(emptyProc38South),
.dataInSouth(dataInProc38South),
.rdEast(rdProc38East),
.emptyEast(emptyProc38East),
.dataInEast(dataInProc38East),
.wrEast(wrProc38East),
.fullEast(fullProc38East),
.dataOutEast(dataOutProc38East),
.wrWest(wrProc38West),
.fullWest(fullProc38West),
.dataOutWest(dataOutProc38West));
//PROCESSOR 39
system proc39(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe39),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe39),
.rdWest(rdProc39West),
.emptyWest(emptyProc39West),
.dataInWest(dataInProc39West),
.wrWest(wrProc39West),
.fullWest(fullProc39West),
.dataOutWest(dataOutProc39West));
//PROCESSOR 40
system proc40(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe40),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe40),
.rdNorth(rdProc40North),
.emptyNorth(emptyProc40North),
.dataInNorth(dataInProc40North),
.wrEast(wrProc40East),
.fullEast(fullProc40East),
.dataOutEast(dataOutProc40East));
//PROCESSOR 41
system proc41(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe41),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe41),
.rdNorth(rdProc41North),
.emptyNorth(emptyProc41North),
.dataInNorth(dataInProc41North),
.wrNorth(wrProc41North),
.fullNorth(fullProc41North),
.dataOutNorth(dataOutProc41North),
.wrEast(wrProc41East),
.fullEast(fullProc41East),
.dataOutEast(dataOutProc41East),
.rdWest(rdProc41West),
.emptyWest(emptyProc41West),
.dataInWest(dataInProc41West));
//PROCESSOR 42
system proc42(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe42),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe42),
.wrNorth(wrProc42North),
.fullNorth(fullProc42North),
.dataOutNorth(dataOutProc42North),
.rdEast(rdProc42East),
.emptyEast(emptyProc42East),
.dataInEast(dataInProc42East),
.rdWest(rdProc42West),
.emptyWest(emptyProc42West),
.dataInWest(dataInProc42West));
//PROCESSOR 43
system proc43(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe43),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe43),
.rdEast(rdProc43East),
.emptyEast(emptyProc43East),
.dataInEast(dataInProc43East),
.wrWest(wrProc43West),
.fullWest(fullProc43West),
.dataOutWest(dataOutProc43West));
//PROCESSOR 44
system proc44(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe44),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe44),
.rdNorth(rdProc44North),
.emptyNorth(emptyProc44North),
.dataInNorth(dataInProc44North),
.rdEast(rdProc44East),
.emptyEast(emptyProc44East),
.dataInEast(dataInProc44East),
.wrWest(wrProc44West),
.fullWest(fullProc44West),
.dataOutWest(dataOutProc44West));
//PROCESSOR 45
system proc45(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe45),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe45),
.rdNorth(rdProc45North),
.emptyNorth(emptyProc45North),
.dataInNorth(dataInProc45North),
.wrWest(wrProc45West),
.fullWest(fullProc45West),
.dataOutWest(dataOutProc45West));
//PROCESSOR 46
system proc46(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe46),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe46),
.rdNorth(rdProc46North),
.emptyNorth(emptyProc46North),
.dataInNorth(dataInProc46North),
.wrEast(wrProc46East),
.fullEast(fullProc46East),
.dataOutEast(dataOutProc46East));
//PROCESSOR 47
system proc47(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe47),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe47),
.rdNorth(rdProc47North),
.emptyNorth(emptyProc47North),
.dataInNorth(dataInProc47North),
.wrEast(wrProc47East),
.fullEast(fullProc47East),
.dataOutEast(dataOutProc47East),
.rdWest(rdProc47West),
.emptyWest(emptyProc47West),
.dataInWest(dataInProc47West));
//PROCESSOR 48
system proc48(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe48),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe48),
.wrNorth(wrProc48North),
.fullNorth(fullProc48North),
.dataOutNorth(dataOutProc48North),
.rdEast(rdProc48East),
.emptyEast(emptyProc48East),
.dataInEast(dataInProc48East),
.wrEast(wrProc48East),
.fullEast(fullProc48East),
.dataOutEast(dataOutProc48East),
.rdWest(rdProc48West),
.emptyWest(emptyProc48West),
.dataInWest(dataInProc48West));
//PROCESSOR 49
system proc49(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe49),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe49),
.rdWest(rdProc49West),
.emptyWest(emptyProc49West),
.dataInWest(dataInProc49West),
.wrWest(wrProc49West),
.fullWest(fullProc49West),
.dataOutWest(dataOutProc49West));
//FIFO 0 TO 10
fifo fifo_proc0_to_proc10(
.clk(clk),
.resetn(resetn),
.wr(wrProc0South),
.full(fullProc0South),
.dataIn(dataOutProc0South),
.rd(rdProc10North),
.empty(emptyProc10North),
.dataOut(dataInProc10North));
//FIFO 1 TO 0
fifo fifo_proc1_to_proc0(
.clk(clk),
.resetn(resetn),
.wr(wrProc1West),
.full(fullProc1West),
.dataIn(dataOutProc1West),
.rd(rdProc0East),
.empty(emptyProc0East),
.dataOut(dataInProc0East));
//FIFO 0 TO 1
fifo fifo_proc0_to_proc1(
.clk(clk),
.resetn(resetn),
.wr(wrProc0East),
.full(fullProc0East),
.dataIn(dataOutProc0East),
.rd(rdProc1West),
.empty(emptyProc1West),
.dataOut(dataInProc1West));
//FIFO 3 TO 2
fifo fifo_proc3_to_proc2(
.clk(clk),
.resetn(resetn),
.wr(wrProc3West),
.full(fullProc3West),
.dataIn(dataOutProc3West),
.rd(rdProc2East),
.empty(emptyProc2East),
.dataOut(dataInProc2East));
//FIFO 4 TO 3
fifo fifo_proc4_to_proc3(
.clk(clk),
.resetn(resetn),
.wr(wrProc4West),
.full(fullProc4West),
.dataIn(dataOutProc4West),
.rd(rdProc3East),
.empty(emptyProc3East),
.dataOut(dataInProc3East));
//FIFO 5 TO 4
fifo fifo_proc5_to_proc4(
.clk(clk),
.resetn(resetn),
.wr(wrProc5West),
.full(fullProc5West),
.dataIn(dataOutProc5West),
.rd(rdProc4East),
.empty(emptyProc4East),
.dataOut(dataInProc4East));
//FIFO 6 TO 5
fifo fifo_proc6_to_proc5(
.clk(clk),
.resetn(resetn),
.wr(wrProc6West),
.full(fullProc6West),
.dataIn(dataOutProc6West),
.rd(rdProc5East),
.empty(emptyProc5East),
.dataOut(dataInProc5East));
//FIFO 16 TO 6
fifo fifo_proc16_to_proc6(
.clk(clk),
.resetn(resetn),
.wr(wrProc16North),
.full(fullProc16North),
.dataIn(dataOutProc16North),
.rd(rdProc6South),
.empty(emptyProc6South),
.dataOut(dataInProc6South));
//FIFO 6 TO 16
fifo fifo_proc6_to_proc16(
.clk(clk),
.resetn(resetn),
.wr(wrProc6South),
.full(fullProc6South),
.dataIn(dataOutProc6South),
.rd(rdProc16North),
.empty(emptyProc16North),
.dataOut(dataInProc16North));
//FIFO 7 TO 6
fifo fifo_proc7_to_proc6(
.clk(clk),
.resetn(resetn),
.wr(wrProc7West),
.full(fullProc7West),
.dataIn(dataOutProc7West),
.rd(rdProc6East),
.empty(emptyProc6East),
.dataOut(dataInProc6East));
//FIFO 7 TO 17
fifo fifo_proc7_to_proc17(
.clk(clk),
.resetn(resetn),
.wr(wrProc7South),
.full(fullProc7South),
.dataIn(dataOutProc7South),
.rd(rdProc17North),
.empty(emptyProc17North),
.dataOut(dataInProc17North));
//FIFO 8 TO 7
fifo fifo_proc8_to_proc7(
.clk(clk),
.resetn(resetn),
.wr(wrProc8West),
.full(fullProc8West),
.dataIn(dataOutProc8West),
.rd(rdProc7East),
.empty(emptyProc7East),
.dataOut(dataInProc7East));
//FIFO 18 TO 8
fifo fifo_proc18_to_proc8(
.clk(clk),
.resetn(resetn),
.wr(wrProc18North),
.full(fullProc18North),
.dataIn(dataOutProc18North),
.rd(rdProc8South),
.empty(emptyProc8South),
.dataOut(dataInProc8South));
//FIFO 9 TO 8
fifo fifo_proc9_to_proc8(
.clk(clk),
.resetn(resetn),
.wr(wrProc9West),
.full(fullProc9West),
.dataIn(dataOutProc9West),
.rd(rdProc8East),
.empty(emptyProc8East),
.dataOut(dataInProc8East));
//FIFO 19 TO 9
fifo fifo_proc19_to_proc9(
.clk(clk),
.resetn(resetn),
.wr(wrProc19North),
.full(fullProc19North),
.dataIn(dataOutProc19North),
.rd(rdProc9South),
.empty(emptyProc9South),
.dataOut(dataInProc9South));
//FIFO 10 TO 20
fifo fifo_proc10_to_proc20(
.clk(clk),
.resetn(resetn),
.wr(wrProc10South),
.full(fullProc10South),
.dataIn(dataOutProc10South),
.rd(rdProc20North),
.empty(emptyProc20North),
.dataOut(dataInProc20North));
//FIFO 21 TO 11
fifo fifo_proc21_to_proc11(
.clk(clk),
.resetn(resetn),
.wr(wrProc21North),
.full(fullProc21North),
.dataIn(dataOutProc21North),
.rd(rdProc11South),
.empty(emptyProc11South),
.dataOut(dataInProc11South));
//FIFO 11 TO 12
fifo fifo_proc11_to_proc12(
.clk(clk),
.resetn(resetn),
.wr(wrProc11East),
.full(fullProc11East),
.dataIn(dataOutProc11East),
.rd(rdProc12West),
.empty(emptyProc12West),
.dataOut(dataInProc12West));
//FIFO 22 TO 12
fifo fifo_proc22_to_proc12(
.clk(clk),
.resetn(resetn),
.wr(wrProc22North),
.full(fullProc22North),
.dataIn(dataOutProc22North),
.rd(rdProc12South),
.empty(emptyProc12South),
.dataOut(dataInProc12South));
//FIFO 12 TO 22
fifo fifo_proc12_to_proc22(
.clk(clk),
.resetn(resetn),
.wr(wrProc12South),
.full(fullProc12South),
.dataIn(dataOutProc12South),
.rd(rdProc22North),
.empty(emptyProc22North),
.dataOut(dataInProc22North));
//FIFO 12 TO 13
fifo fifo_proc12_to_proc13(
.clk(clk),
.resetn(resetn),
.wr(wrProc12East),
.full(fullProc12East),
.dataIn(dataOutProc12East),
.rd(rdProc13West),
.empty(emptyProc13West),
.dataOut(dataInProc13West));
//FIFO 13 TO 14
fifo fifo_proc13_to_proc14(
.clk(clk),
.resetn(resetn),
.wr(wrProc13East),
.full(fullProc13East),
.dataIn(dataOutProc13East),
.rd(rdProc14West),
.empty(emptyProc14West),
.dataOut(dataInProc14West));
//FIFO 24 TO 14
fifo fifo_proc24_to_proc14(
.clk(clk),
.resetn(resetn),
.wr(wrProc24North),
.full(fullProc24North),
.dataIn(dataOutProc24North),
.rd(rdProc14South),
.empty(emptyProc14South),
.dataOut(dataInProc14South));
//FIFO 14 TO 24
fifo fifo_proc14_to_proc24(
.clk(clk),
.resetn(resetn),
.wr(wrProc14South),
.full(fullProc14South),
.dataIn(dataOutProc14South),
.rd(rdProc24North),
.empty(emptyProc24North),
.dataOut(dataInProc24North));
//FIFO 15 TO 14
fifo fifo_proc15_to_proc14(
.clk(clk),
.resetn(resetn),
.wr(wrProc15West),
.full(fullProc15West),
.dataIn(dataOutProc15West),
.rd(rdProc14East),
.empty(emptyProc14East),
.dataOut(dataInProc14East));
//FIFO 14 TO 15
fifo fifo_proc14_to_proc15(
.clk(clk),
.resetn(resetn),
.wr(wrProc14East),
.full(fullProc14East),
.dataIn(dataOutProc14East),
.rd(rdProc15West),
.empty(emptyProc15West),
.dataOut(dataInProc15West));
//FIFO 15 TO 25
fifo fifo_proc15_to_proc25(
.clk(clk),
.resetn(resetn),
.wr(wrProc15South),
.full(fullProc15South),
.dataIn(dataOutProc15South),
.rd(rdProc25North),
.empty(emptyProc25North),
.dataOut(dataInProc25North));
//FIFO 16 TO 15
fifo fifo_proc16_to_proc15(
.clk(clk),
.resetn(resetn),
.wr(wrProc16West),
.full(fullProc16West),
.dataIn(dataOutProc16West),
.rd(rdProc15East),
.empty(emptyProc15East),
.dataOut(dataInProc15East));
//FIFO 15 TO 16
fifo fifo_proc15_to_proc16(
.clk(clk),
.resetn(resetn),
.wr(wrProc15East),
.full(fullProc15East),
.dataIn(dataOutProc15East),
.rd(rdProc16West),
.empty(emptyProc16West),
.dataOut(dataInProc16West));
//FIFO 26 TO 16
fifo fifo_proc26_to_proc16(
.clk(clk),
.resetn(resetn),
.wr(wrProc26North),
.full(fullProc26North),
.dataIn(dataOutProc26North),
.rd(rdProc16South),
.empty(emptyProc16South),
.dataOut(dataInProc16South));
//FIFO 16 TO 26
fifo fifo_proc16_to_proc26(
.clk(clk),
.resetn(resetn),
.wr(wrProc16South),
.full(fullProc16South),
.dataIn(dataOutProc16South),
.rd(rdProc26North),
.empty(emptyProc26North),
.dataOut(dataInProc26North));
//FIFO 17 TO 16
fifo fifo_proc17_to_proc16(
.clk(clk),
.resetn(resetn),
.wr(wrProc17West),
.full(fullProc17West),
.dataIn(dataOutProc17West),
.rd(rdProc16East),
.empty(emptyProc16East),
.dataOut(dataInProc16East));
//FIFO 28 TO 18
fifo fifo_proc28_to_proc18(
.clk(clk),
.resetn(resetn),
.wr(wrProc28North),
.full(fullProc28North),
.dataIn(dataOutProc28North),
.rd(rdProc18South),
.empty(emptyProc18South),
.dataOut(dataInProc18South));
//FIFO 19 TO 18
fifo fifo_proc19_to_proc18(
.clk(clk),
.resetn(resetn),
.wr(wrProc19West),
.full(fullProc19West),
.dataIn(dataOutProc19West),
.rd(rdProc18East),
.empty(emptyProc18East),
.dataOut(dataInProc18East));
//FIFO 18 TO 19
fifo fifo_proc18_to_proc19(
.clk(clk),
.resetn(resetn),
.wr(wrProc18East),
.full(fullProc18East),
.dataIn(dataOutProc18East),
.rd(rdProc19West),
.empty(emptyProc19West),
.dataOut(dataInProc19West));
//FIFO 29 TO 19
fifo fifo_proc29_to_proc19(
.clk(clk),
.resetn(resetn),
.wr(wrProc29North),
.full(fullProc29North),
.dataIn(dataOutProc29North),
.rd(rdProc19South),
.empty(emptyProc19South),
.dataOut(dataInProc19South));
//FIFO 20 TO 30
fifo fifo_proc20_to_proc30(
.clk(clk),
.resetn(resetn),
.wr(wrProc20South),
.full(fullProc20South),
.dataIn(dataOutProc20South),
.rd(rdProc30North),
.empty(emptyProc30North),
.dataOut(dataInProc30North));
//FIFO 31 TO 21
fifo fifo_proc31_to_proc21(
.clk(clk),
.resetn(resetn),
.wr(wrProc31North),
.full(fullProc31North),
.dataIn(dataOutProc31North),
.rd(rdProc21South),
.empty(emptyProc21South),
.dataOut(dataInProc21South));
//FIFO 21 TO 22
fifo fifo_proc21_to_proc22(
.clk(clk),
.resetn(resetn),
.wr(wrProc21East),
.full(fullProc21East),
.dataIn(dataOutProc21East),
.rd(rdProc22West),
.empty(emptyProc22West),
.dataOut(dataInProc22West));
//FIFO 32 TO 22
fifo fifo_proc32_to_proc22(
.clk(clk),
.resetn(resetn),
.wr(wrProc32North),
.full(fullProc32North),
.dataIn(dataOutProc32North),
.rd(rdProc22South),
.empty(emptyProc22South),
.dataOut(dataInProc22South));
//FIFO 22 TO 23
fifo fifo_proc22_to_proc23(
.clk(clk),
.resetn(resetn),
.wr(wrProc22East),
.full(fullProc22East),
.dataIn(dataOutProc22East),
.rd(rdProc23West),
.empty(emptyProc23West),
.dataOut(dataInProc23West));
//FIFO 33 TO 23
fifo fifo_proc33_to_proc23(
.clk(clk),
.resetn(resetn),
.wr(wrProc33North),
.full(fullProc33North),
.dataIn(dataOutProc33North),
.rd(rdProc23South),
.empty(emptyProc23South),
.dataOut(dataInProc23South));
//FIFO 23 TO 24
fifo fifo_proc23_to_proc24(
.clk(clk),
.resetn(resetn),
.wr(wrProc23East),
.full(fullProc23East),
.dataIn(dataOutProc23East),
.rd(rdProc24West),
.empty(emptyProc24West),
.dataOut(dataInProc24West));
//FIFO 24 TO 34
fifo fifo_proc24_to_proc34(
.clk(clk),
.resetn(resetn),
.wr(wrProc24South),
.full(fullProc24South),
.dataIn(dataOutProc24South),
.rd(rdProc34North),
.empty(emptyProc34North),
.dataOut(dataInProc34North));
//FIFO 24 TO 25
fifo fifo_proc24_to_proc25(
.clk(clk),
.resetn(resetn),
.wr(wrProc24East),
.full(fullProc24East),
.dataIn(dataOutProc24East),
.rd(rdProc25West),
.empty(emptyProc25West),
.dataOut(dataInProc25West));
//FIFO 25 TO 35
fifo fifo_proc25_to_proc35(
.clk(clk),
.resetn(resetn),
.wr(wrProc25South),
.full(fullProc25South),
.dataIn(dataOutProc25South),
.rd(rdProc35North),
.empty(emptyProc35North),
.dataOut(dataInProc35North));
//FIFO 25 TO 26
fifo fifo_proc25_to_proc26(
.clk(clk),
.resetn(resetn),
.wr(wrProc25East),
.full(fullProc25East),
.dataIn(dataOutProc25East),
.rd(rdProc26West),
.empty(emptyProc26West),
.dataOut(dataInProc26West));
//FIFO 36 TO 26
fifo fifo_proc36_to_proc26(
.clk(clk),
.resetn(resetn),
.wr(wrProc36North),
.full(fullProc36North),
.dataIn(dataOutProc36North),
.rd(rdProc26South),
.empty(emptyProc26South),
.dataOut(dataInProc26South));
//FIFO 26 TO 36
fifo fifo_proc26_to_proc36(
.clk(clk),
.resetn(resetn),
.wr(wrProc26South),
.full(fullProc26South),
.dataIn(dataOutProc26South),
.rd(rdProc36North),
.empty(emptyProc36North),
.dataOut(dataInProc36North));
//FIFO 27 TO 26
fifo fifo_proc27_to_proc26(
.clk(clk),
.resetn(resetn),
.wr(wrProc27West),
.full(fullProc27West),
.dataIn(dataOutProc27West),
.rd(rdProc26East),
.empty(emptyProc26East),
.dataOut(dataInProc26East));
//FIFO 26 TO 27
fifo fifo_proc26_to_proc27(
.clk(clk),
.resetn(resetn),
.wr(wrProc26East),
.full(fullProc26East),
.dataIn(dataOutProc26East),
.rd(rdProc27West),
.empty(emptyProc27West),
.dataOut(dataInProc27West));
//FIFO 37 TO 27
fifo fifo_proc37_to_proc27(
.clk(clk),
.resetn(resetn),
.wr(wrProc37North),
.full(fullProc37North),
.dataIn(dataOutProc37North),
.rd(rdProc27South),
.empty(emptyProc27South),
.dataOut(dataInProc27South));
//FIFO 27 TO 28
fifo fifo_proc27_to_proc28(
.clk(clk),
.resetn(resetn),
.wr(wrProc27East),
.full(fullProc27East),
.dataIn(dataOutProc27East),
.rd(rdProc28West),
.empty(emptyProc28West),
.dataOut(dataInProc28West));
//FIFO 28 TO 29
fifo fifo_proc28_to_proc29(
.clk(clk),
.resetn(resetn),
.wr(wrProc28East),
.full(fullProc28East),
.dataIn(dataOutProc28East),
.rd(rdProc29West),
.empty(emptyProc29West),
.dataOut(dataInProc29West));
//FIFO 30 TO 40
fifo fifo_proc30_to_proc40(
.clk(clk),
.resetn(resetn),
.wr(wrProc30South),
.full(fullProc30South),
.dataIn(dataOutProc30South),
.rd(rdProc40North),
.empty(emptyProc40North),
.dataOut(dataInProc40North));
//FIFO 30 TO 31
fifo fifo_proc30_to_proc31(
.clk(clk),
.resetn(resetn),
.wr(wrProc30East),
.full(fullProc30East),
.dataIn(dataOutProc30East),
.rd(rdProc31West),
.empty(emptyProc31West),
.dataOut(dataInProc31West));
//FIFO 41 TO 31
fifo fifo_proc41_to_proc31(
.clk(clk),
.resetn(resetn),
.wr(wrProc41North),
.full(fullProc41North),
.dataIn(dataOutProc41North),
.rd(rdProc31South),
.empty(emptyProc31South),
.dataOut(dataInProc31South));
//FIFO 31 TO 41
fifo fifo_proc31_to_proc41(
.clk(clk),
.resetn(resetn),
.wr(wrProc31South),
.full(fullProc31South),
.dataIn(dataOutProc31South),
.rd(rdProc41North),
.empty(emptyProc41North),
.dataOut(dataInProc41North));
//FIFO 32 TO 31
fifo fifo_proc32_to_proc31(
.clk(clk),
.resetn(resetn),
.wr(wrProc32West),
.full(fullProc32West),
.dataIn(dataOutProc32West),
.rd(rdProc31East),
.empty(emptyProc31East),
.dataOut(dataInProc31East));
//FIFO 42 TO 32
fifo fifo_proc42_to_proc32(
.clk(clk),
.resetn(resetn),
.wr(wrProc42North),
.full(fullProc42North),
.dataIn(dataOutProc42North),
.rd(rdProc32South),
.empty(emptyProc32South),
.dataOut(dataInProc32South));
//FIFO 32 TO 33
fifo fifo_proc32_to_proc33(
.clk(clk),
.resetn(resetn),
.wr(wrProc32East),
.full(fullProc32East),
.dataIn(dataOutProc32East),
.rd(rdProc33West),
.empty(emptyProc33West),
.dataOut(dataInProc33West));
//FIFO 34 TO 44
fifo fifo_proc34_to_proc44(
.clk(clk),
.resetn(resetn),
.wr(wrProc34South),
.full(fullProc34South),
.dataIn(dataOutProc34South),
.rd(rdProc44North),
.empty(emptyProc44North),
.dataOut(dataInProc44North));
//FIFO 35 TO 45
fifo fifo_proc35_to_proc45(
.clk(clk),
.resetn(resetn),
.wr(wrProc35South),
.full(fullProc35South),
.dataIn(dataOutProc35South),
.rd(rdProc45North),
.empty(emptyProc45North),
.dataOut(dataInProc45North));
//FIFO 35 TO 36
fifo fifo_proc35_to_proc36(
.clk(clk),
.resetn(resetn),
.wr(wrProc35East),
.full(fullProc35East),
.dataIn(dataOutProc35East),
.rd(rdProc36West),
.empty(emptyProc36West),
.dataOut(dataInProc36West));
//FIFO 36 TO 46
fifo fifo_proc36_to_proc46(
.clk(clk),
.resetn(resetn),
.wr(wrProc36South),
.full(fullProc36South),
.dataIn(dataOutProc36South),
.rd(rdProc46North),
.empty(emptyProc46North),
.dataOut(dataInProc46North));
//FIFO 37 TO 36
fifo fifo_proc37_to_proc36(
.clk(clk),
.resetn(resetn),
.wr(wrProc37West),
.full(fullProc37West),
.dataIn(dataOutProc37West),
.rd(rdProc36East),
.empty(emptyProc36East),
.dataOut(dataInProc36East));
//FIFO 36 TO 37
fifo fifo_proc36_to_proc37(
.clk(clk),
.resetn(resetn),
.wr(wrProc36East),
.full(fullProc36East),
.dataIn(dataOutProc36East),
.rd(rdProc37West),
.empty(emptyProc37West),
.dataOut(dataInProc37West));
//FIFO 37 TO 47
fifo fifo_proc37_to_proc47(
.clk(clk),
.resetn(resetn),
.wr(wrProc37South),
.full(fullProc37South),
.dataIn(dataOutProc37South),
.rd(rdProc47North),
.empty(emptyProc47North),
.dataOut(dataInProc47North));
//FIFO 38 TO 37
fifo fifo_proc38_to_proc37(
.clk(clk),
.resetn(resetn),
.wr(wrProc38West),
.full(fullProc38West),
.dataIn(dataOutProc38West),
.rd(rdProc37East),
.empty(emptyProc37East),
.dataOut(dataInProc37East));
//FIFO 48 TO 38
fifo fifo_proc48_to_proc38(
.clk(clk),
.resetn(resetn),
.wr(wrProc48North),
.full(fullProc48North),
.dataIn(dataOutProc48North),
.rd(rdProc38South),
.empty(emptyProc38South),
.dataOut(dataInProc38South));
//FIFO 39 TO 38
fifo fifo_proc39_to_proc38(
.clk(clk),
.resetn(resetn),
.wr(wrProc39West),
.full(fullProc39West),
.dataIn(dataOutProc39West),
.rd(rdProc38East),
.empty(emptyProc38East),
.dataOut(dataInProc38East));
//FIFO 38 TO 39
fifo fifo_proc38_to_proc39(
.clk(clk),
.resetn(resetn),
.wr(wrProc38East),
.full(fullProc38East),
.dataIn(dataOutProc38East),
.rd(rdProc39West),
.empty(emptyProc39West),
.dataOut(dataInProc39West));
//FIFO 40 TO 41
fifo fifo_proc40_to_proc41(
.clk(clk),
.resetn(resetn),
.wr(wrProc40East),
.full(fullProc40East),
.dataIn(dataOutProc40East),
.rd(rdProc41West),
.empty(emptyProc41West),
.dataOut(dataInProc41West));
//FIFO 41 TO 42
fifo fifo_proc41_to_proc42(
.clk(clk),
.resetn(resetn),
.wr(wrProc41East),
.full(fullProc41East),
.dataIn(dataOutProc41East),
.rd(rdProc42West),
.empty(emptyProc42West),
.dataOut(dataInProc42West));
//FIFO 43 TO 42
fifo fifo_proc43_to_proc42(
.clk(clk),
.resetn(resetn),
.wr(wrProc43West),
.full(fullProc43West),
.dataIn(dataOutProc43West),
.rd(rdProc42East),
.empty(emptyProc42East),
.dataOut(dataInProc42East));
//FIFO 44 TO 43
fifo fifo_proc44_to_proc43(
.clk(clk),
.resetn(resetn),
.wr(wrProc44West),
.full(fullProc44West),
.dataIn(dataOutProc44West),
.rd(rdProc43East),
.empty(emptyProc43East),
.dataOut(dataInProc43East));
//FIFO 45 TO 44
fifo fifo_proc45_to_proc44(
.clk(clk),
.resetn(resetn),
.wr(wrProc45West),
.full(fullProc45West),
.dataIn(dataOutProc45West),
.rd(rdProc44East),
.empty(emptyProc44East),
.dataOut(dataInProc44East));
//FIFO 46 TO 47
fifo fifo_proc46_to_proc47(
.clk(clk),
.resetn(resetn),
.wr(wrProc46East),
.full(fullProc46East),
.dataIn(dataOutProc46East),
.rd(rdProc47West),
.empty(emptyProc47West),
.dataOut(dataInProc47West));
//FIFO 47 TO 48
fifo fifo_proc47_to_proc48(
.clk(clk),
.resetn(resetn),
.wr(wrProc47East),
.full(fullProc47East),
.dataIn(dataOutProc47East),
.rd(rdProc48West),
.empty(emptyProc48West),
.dataOut(dataInProc48West));
//FIFO 49 TO 48
fifo fifo_proc49_to_proc48(
.clk(clk),
.resetn(resetn),
.wr(wrProc49West),
.full(fullProc49West),
.dataIn(dataOutProc49West),
.rd(rdProc48East),
.empty(emptyProc48East),
.dataOut(dataInProc48East));
//FIFO 48 TO 49
fifo fifo_proc48_to_proc49(
.clk(clk),
.resetn(resetn),
.wr(wrProc48East),
.full(fullProc48East),
.dataIn(dataOutProc48East),
.rd(rdProc49West),
.empty(emptyProc49West),
.dataOut(dataInProc49West));
/**************** Boot loader ********************/
/*******Boot up each processor one by one*********/
always@(posedge clk)
begin
case(processor_select)
0: begin
boot_iwe0 = ~resetn;
boot_dwe0 = ~resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
end
1: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = ~resetn;
boot_dwe1 = ~resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
end
2: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = ~resetn;
boot_dwe2 = ~resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
end
3: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = ~resetn;
boot_dwe3 = ~resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
end
4: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = ~resetn;
boot_dwe4 = ~resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
end
5: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = ~resetn;
boot_dwe5 = ~resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
end
6: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = ~resetn;
boot_dwe6 = ~resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
end
7: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = ~resetn;
boot_dwe7 = ~resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
end
8: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = ~resetn;
boot_dwe8 = ~resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
end
9: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = ~resetn;
boot_dwe9 = ~resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
end
10: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = ~resetn;
boot_dwe10 = ~resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
end
11: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = ~resetn;
boot_dwe11 = ~resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
end
12: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = ~resetn;
boot_dwe12 = ~resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
end
13: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = ~resetn;
boot_dwe13 = ~resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
end
14: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = ~resetn;
boot_dwe14 = ~resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
end
15: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = ~resetn;
boot_dwe15 = ~resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
end
16: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = ~resetn;
boot_dwe16 = ~resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
end
17: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = ~resetn;
boot_dwe17 = ~resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
end
18: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = ~resetn;
boot_dwe18 = ~resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
end
19: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = ~resetn;
boot_dwe19 = ~resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
end
20: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = ~resetn;
boot_dwe20 = ~resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
end
21: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = ~resetn;
boot_dwe21 = ~resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
end
22: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = ~resetn;
boot_dwe22 = ~resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
end
23: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = ~resetn;
boot_dwe23 = ~resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
end
24: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = ~resetn;
boot_dwe24 = ~resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
end
25: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = ~resetn;
boot_dwe25 = ~resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
end
26: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = ~resetn;
boot_dwe26 = ~resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
end
27: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = ~resetn;
boot_dwe27 = ~resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
end
28: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = ~resetn;
boot_dwe28 = ~resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
end
29: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = ~resetn;
boot_dwe29 = ~resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
end
30: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = ~resetn;
boot_dwe30 = ~resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
end
31: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = ~resetn;
boot_dwe31 = ~resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
end
32: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = ~resetn;
boot_dwe32 = ~resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
end
33: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = ~resetn;
boot_dwe33 = ~resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
end
34: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = ~resetn;
boot_dwe34 = ~resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
end
35: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = ~resetn;
boot_dwe35 = ~resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
end
36: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = ~resetn;
boot_dwe36 = ~resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
end
37: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = ~resetn;
boot_dwe37 = ~resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
end
38: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = ~resetn;
boot_dwe38 = ~resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
end
39: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = ~resetn;
boot_dwe39 = ~resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
end
40: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = ~resetn;
boot_dwe40 = ~resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
end
41: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = ~resetn;
boot_dwe41 = ~resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
end
42: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = ~resetn;
boot_dwe42 = ~resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
end
43: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = ~resetn;
boot_dwe43 = ~resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
end
44: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = ~resetn;
boot_dwe44 = ~resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
end
45: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = ~resetn;
boot_dwe45 = ~resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
end
46: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = ~resetn;
boot_dwe46 = ~resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
end
47: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = ~resetn;
boot_dwe47 = ~resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
end
48: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = ~resetn;
boot_dwe48 = ~resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
end
49: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = ~resetn;
boot_dwe49 = ~resetn;
end
50: begin
boot_iwe0 = 0;
boot_dwe0 = 0;
boot_iwe1 = 0;
boot_dwe1 = 0;
boot_iwe2 = 0;
boot_dwe2 = 0;
boot_iwe3 = 0;
boot_dwe3 = 0;
boot_iwe4 = 0;
boot_dwe4 = 0;
boot_iwe5 = 0;
boot_dwe5 = 0;
boot_iwe6 = 0;
boot_dwe6 = 0;
boot_iwe7 = 0;
boot_dwe7 = 0;
boot_iwe8 = 0;
boot_dwe8 = 0;
boot_iwe9 = 0;
boot_dwe9 = 0;
boot_iwe10 = 0;
boot_dwe10 = 0;
boot_iwe11 = 0;
boot_dwe11 = 0;
boot_iwe12 = 0;
boot_dwe12 = 0;
boot_iwe13 = 0;
boot_dwe13 = 0;
boot_iwe14 = 0;
boot_dwe14 = 0;
boot_iwe15 = 0;
boot_dwe15 = 0;
boot_iwe16 = 0;
boot_dwe16 = 0;
boot_iwe17 = 0;
boot_dwe17 = 0;
boot_iwe18 = 0;
boot_dwe18 = 0;
boot_iwe19 = 0;
boot_dwe19 = 0;
boot_iwe20 = 0;
boot_dwe20 = 0;
boot_iwe21 = 0;
boot_dwe21 = 0;
boot_iwe22 = 0;
boot_dwe22 = 0;
boot_iwe23 = 0;
boot_dwe23 = 0;
boot_iwe24 = 0;
boot_dwe24 = 0;
boot_iwe25 = 0;
boot_dwe25 = 0;
boot_iwe26 = 0;
boot_dwe26 = 0;
boot_iwe27 = 0;
boot_dwe27 = 0;
boot_iwe28 = 0;
boot_dwe28 = 0;
boot_iwe29 = 0;
boot_dwe29 = 0;
boot_iwe30 = 0;
boot_dwe30 = 0;
boot_iwe31 = 0;
boot_dwe31 = 0;
boot_iwe32 = 0;
boot_dwe32 = 0;
boot_iwe33 = 0;
boot_dwe33 = 0;
boot_iwe34 = 0;
boot_dwe34 = 0;
boot_iwe35 = 0;
boot_dwe35 = 0;
boot_iwe36 = 0;
boot_dwe36 = 0;
boot_iwe37 = 0;
boot_dwe37 = 0;
boot_iwe38 = 0;
boot_dwe38 = 0;
boot_iwe39 = 0;
boot_dwe39 = 0;
boot_iwe40 = 0;
boot_dwe40 = 0;
boot_iwe41 = 0;
boot_dwe41 = 0;
boot_iwe42 = 0;
boot_dwe42 = 0;
boot_iwe43 = 0;
boot_dwe43 = 0;
boot_iwe44 = 0;
boot_dwe44 = 0;
boot_iwe45 = 0;
boot_dwe45 = 0;
boot_iwe46 = 0;
boot_dwe46 = 0;
boot_iwe47 = 0;
boot_dwe47 = 0;
boot_iwe48 = 0;
boot_dwe48 = 0;
boot_iwe49 = 0;
boot_dwe49 = 0;
end
endcase
end
endmodule |
`timescale 1ns / 1ns
module system90(clk,resetn,boot_iaddr,boot_idata,boot_daddr,boot_ddata,reg_file_b_readdataout,processor_select);
input clk;
input resetn;
input [6:0] processor_select;
output [31:0] reg_file_b_readdataout;
input [13:0] boot_iaddr;
input [31:0] boot_idata;
input [13:0] boot_daddr;
input [31:0] boot_ddata;
reg boot_iwe0;
reg boot_dwe0;
reg boot_iwe1;
reg boot_dwe1;
reg boot_iwe2;
reg boot_dwe2;
reg boot_iwe3;
reg boot_dwe3;
reg boot_iwe4;
reg boot_dwe4;
reg boot_iwe5;
reg boot_dwe5;
reg boot_iwe6;
reg boot_dwe6;
reg boot_iwe7;
reg boot_dwe7;
reg boot_iwe8;
reg boot_dwe8;
reg boot_iwe9;
reg boot_dwe9;
reg boot_iwe10;
reg boot_dwe10;
reg boot_iwe11;
reg boot_dwe11;
reg boot_iwe12;
reg boot_dwe12;
reg boot_iwe13;
reg boot_dwe13;
reg boot_iwe14;
reg boot_dwe14;
reg boot_iwe15;
reg boot_dwe15;
reg boot_iwe16;
reg boot_dwe16;
reg boot_iwe17;
reg boot_dwe17;
reg boot_iwe18;
reg boot_dwe18;
reg boot_iwe19;
reg boot_dwe19;
reg boot_iwe20;
reg boot_dwe20;
reg boot_iwe21;
reg boot_dwe21;
reg boot_iwe22;
reg boot_dwe22;
reg boot_iwe23;
reg boot_dwe23;
reg boot_iwe24;
reg boot_dwe24;
reg boot_iwe25;
reg boot_dwe25;
reg boot_iwe26;
reg boot_dwe26;
reg boot_iwe27;
reg boot_dwe27;
reg boot_iwe28;
reg boot_dwe28;
reg boot_iwe29;
reg boot_dwe29;
reg boot_iwe30;
reg boot_dwe30;
reg boot_iwe31;
reg boot_dwe31;
reg boot_iwe32;
reg boot_dwe32;
reg boot_iwe33;
reg boot_dwe33;
reg boot_iwe34;
reg boot_dwe34;
reg boot_iwe35;
reg boot_dwe35;
reg boot_iwe36;
reg boot_dwe36;
reg boot_iwe37;
reg boot_dwe37;
reg boot_iwe38;
reg boot_dwe38;
reg boot_iwe39;
reg boot_dwe39;
reg boot_iwe40;
reg boot_dwe40;
reg boot_iwe41;
reg boot_dwe41;
reg boot_iwe42;
reg boot_dwe42;
reg boot_iwe43;
reg boot_dwe43;
reg boot_iwe44;
reg boot_dwe44;
reg boot_iwe45;
reg boot_dwe45;
reg boot_iwe46;
reg boot_dwe46;
reg boot_iwe47;
reg boot_dwe47;
reg boot_iwe48;
reg boot_dwe48;
reg boot_iwe49;
reg boot_dwe49;
reg boot_iwe50;
reg boot_dwe50;
reg boot_iwe51;
reg boot_dwe51;
reg boot_iwe52;
reg boot_dwe52;
reg boot_iwe53;
reg boot_dwe53;
reg boot_iwe54;
reg boot_dwe54;
reg boot_iwe55;
reg boot_dwe55;
reg boot_iwe56;
reg boot_dwe56;
reg boot_iwe57;
reg boot_dwe57;
reg boot_iwe58;
reg boot_dwe58;
reg boot_iwe59;
reg boot_dwe59;
reg boot_iwe60;
reg boot_dwe60;
reg boot_iwe61;
reg boot_dwe61;
reg boot_iwe62;
reg boot_dwe62;
reg boot_iwe63;
reg boot_dwe63;
reg boot_iwe64;
reg boot_dwe64;
reg boot_iwe65;
reg boot_dwe65;
reg boot_iwe66;
reg boot_dwe66;
reg boot_iwe67;
reg boot_dwe67;
reg boot_iwe68;
reg boot_dwe68;
reg boot_iwe69;
reg boot_dwe69;
reg boot_iwe70;
reg boot_dwe70;
reg boot_iwe71;
reg boot_dwe71;
reg boot_iwe72;
reg boot_dwe72;
reg boot_iwe73;
reg boot_dwe73;
reg boot_iwe74;
reg boot_dwe74;
reg boot_iwe75;
reg boot_dwe75;
reg boot_iwe76;
reg boot_dwe76;
reg boot_iwe77;
reg boot_dwe77;
reg boot_iwe78;
reg boot_dwe78;
reg boot_iwe79;
reg boot_dwe79;
reg boot_iwe80;
reg boot_dwe80;
reg boot_iwe81;
reg boot_dwe81;
reg boot_iwe82;
reg boot_dwe82;
reg boot_iwe83;
reg boot_dwe83;
reg boot_iwe84;
reg boot_dwe84;
reg boot_iwe85;
reg boot_dwe85;
reg boot_iwe86;
reg boot_dwe86;
reg boot_iwe87;
reg boot_dwe87;
reg boot_iwe88;
reg boot_dwe88;
reg boot_iwe89;
reg boot_dwe89;
//Processor 0 control and data signals
wire wrProc0South;
wire fullProc0South;
wire [31:0] dataOutProc0South;
//Processor 0 control and data signals
wire wrProc0East;
wire fullProc0East;
wire [31:0] dataOutProc0East;
//Processor 1 control and data signals
wire wrProc1South;
wire fullProc1South;
wire [31:0] dataOutProc1South;
//Processor 1 control and data signals
wire rdProc1West;
wire emptyProc1West;
wire [31:0] dataInProc1West;
//Processor 4 control and data signals
wire rdProc4South;
wire emptyProc4South;
wire [31:0] dataInProc4South;
//Processor 4 control and data signals
wire rdProc4East;
wire emptyProc4East;
wire [31:0] dataInProc4East;
//Processor 4 control and data signals
wire wrProc4East;
wire fullProc4East;
wire [31:0] dataOutProc4East;
//Processor 5 control and data signals
wire rdProc5East;
wire emptyProc5East;
wire [31:0] dataInProc5East;
//Processor 5 control and data signals
wire rdProc5West;
wire emptyProc5West;
wire [31:0] dataInProc5West;
//Processor 5 control and data signals
wire wrProc5West;
wire fullProc5West;
wire [31:0] dataOutProc5West;
//Processor 6 control and data signals
wire rdProc6South;
wire emptyProc6South;
wire [31:0] dataInProc6South;
//Processor 6 control and data signals
wire wrProc6South;
wire fullProc6South;
wire [31:0] dataOutProc6South;
//Processor 6 control and data signals
wire rdProc6East;
wire emptyProc6East;
wire [31:0] dataInProc6East;
//Processor 6 control and data signals
wire wrProc6West;
wire fullProc6West;
wire [31:0] dataOutProc6West;
//Processor 7 control and data signals
wire rdProc7South;
wire emptyProc7South;
wire [31:0] dataInProc7South;
//Processor 7 control and data signals
wire wrProc7West;
wire fullProc7West;
wire [31:0] dataOutProc7West;
//Processor 8 control and data signals
wire rdProc8South;
wire emptyProc8South;
wire [31:0] dataInProc8South;
//Processor 8 control and data signals
wire wrProc8South;
wire fullProc8South;
wire [31:0] dataOutProc8South;
//Processor 8 control and data signals
wire rdProc8East;
wire emptyProc8East;
wire [31:0] dataInProc8East;
//Processor 9 control and data signals
wire rdProc9South;
wire emptyProc9South;
wire [31:0] dataInProc9South;
//Processor 9 control and data signals
wire wrProc9West;
wire fullProc9West;
wire [31:0] dataOutProc9West;
//Processor 10 control and data signals
wire rdProc10North;
wire emptyProc10North;
wire [31:0] dataInProc10North;
//Processor 10 control and data signals
wire wrProc10East;
wire fullProc10East;
wire [31:0] dataOutProc10East;
//Processor 11 control and data signals
wire rdProc11North;
wire emptyProc11North;
wire [31:0] dataInProc11North;
//Processor 11 control and data signals
wire wrProc11South;
wire fullProc11South;
wire [31:0] dataOutProc11South;
//Processor 11 control and data signals
wire rdProc11West;
wire emptyProc11West;
wire [31:0] dataInProc11West;
//Processor 12 control and data signals
wire rdProc12South;
wire emptyProc12South;
wire [31:0] dataInProc12South;
//Processor 12 control and data signals
wire wrProc12East;
wire fullProc12East;
wire [31:0] dataOutProc12East;
//Processor 13 control and data signals
wire rdProc13South;
wire emptyProc13South;
wire [31:0] dataInProc13South;
//Processor 13 control and data signals
wire wrProc13East;
wire fullProc13East;
wire [31:0] dataOutProc13East;
//Processor 13 control and data signals
wire rdProc13West;
wire emptyProc13West;
wire [31:0] dataInProc13West;
//Processor 14 control and data signals
wire wrProc14North;
wire fullProc14North;
wire [31:0] dataOutProc14North;
//Processor 14 control and data signals
wire rdProc14South;
wire emptyProc14South;
wire [31:0] dataInProc14South;
//Processor 14 control and data signals
wire wrProc14South;
wire fullProc14South;
wire [31:0] dataOutProc14South;
//Processor 14 control and data signals
wire wrProc14East;
wire fullProc14East;
wire [31:0] dataOutProc14East;
//Processor 14 control and data signals
wire rdProc14West;
wire emptyProc14West;
wire [31:0] dataInProc14West;
//Processor 15 control and data signals
wire wrProc15East;
wire fullProc15East;
wire [31:0] dataOutProc15East;
//Processor 15 control and data signals
wire rdProc15West;
wire emptyProc15West;
wire [31:0] dataInProc15West;
//Processor 16 control and data signals
wire rdProc16North;
wire emptyProc16North;
wire [31:0] dataInProc16North;
//Processor 16 control and data signals
wire wrProc16North;
wire fullProc16North;
wire [31:0] dataOutProc16North;
//Processor 16 control and data signals
wire wrProc16South;
wire fullProc16South;
wire [31:0] dataOutProc16South;
//Processor 16 control and data signals
wire rdProc16West;
wire emptyProc16West;
wire [31:0] dataInProc16West;
//Processor 17 control and data signals
wire wrProc17North;
wire fullProc17North;
wire [31:0] dataOutProc17North;
//Processor 17 control and data signals
wire rdProc17South;
wire emptyProc17South;
wire [31:0] dataInProc17South;
//Processor 18 control and data signals
wire rdProc18North;
wire emptyProc18North;
wire [31:0] dataInProc18North;
//Processor 18 control and data signals
wire wrProc18North;
wire fullProc18North;
wire [31:0] dataOutProc18North;
//Processor 18 control and data signals
wire wrProc18South;
wire fullProc18South;
wire [31:0] dataOutProc18South;
//Processor 19 control and data signals
wire wrProc19North;
wire fullProc19North;
wire [31:0] dataOutProc19North;
//Processor 19 control and data signals
wire rdProc19South;
wire emptyProc19South;
wire [31:0] dataInProc19South;
//Processor 19 control and data signals
wire wrProc19South;
wire fullProc19South;
wire [31:0] dataOutProc19South;
//Processor 20 control and data signals
wire rdProc20South;
wire emptyProc20South;
wire [31:0] dataInProc20South;
//Processor 20 control and data signals
wire wrProc20East;
wire fullProc20East;
wire [31:0] dataOutProc20East;
//Processor 21 control and data signals
wire rdProc21North;
wire emptyProc21North;
wire [31:0] dataInProc21North;
//Processor 21 control and data signals
wire rdProc21South;
wire emptyProc21South;
wire [31:0] dataInProc21South;
//Processor 21 control and data signals
wire wrProc21South;
wire fullProc21South;
wire [31:0] dataOutProc21South;
//Processor 21 control and data signals
wire wrProc21East;
wire fullProc21East;
wire [31:0] dataOutProc21East;
//Processor 21 control and data signals
wire rdProc21West;
wire emptyProc21West;
wire [31:0] dataInProc21West;
//Processor 22 control and data signals
wire wrProc22North;
wire fullProc22North;
wire [31:0] dataOutProc22North;
//Processor 22 control and data signals
wire rdProc22South;
wire emptyProc22South;
wire [31:0] dataInProc22South;
//Processor 22 control and data signals
wire wrProc22South;
wire fullProc22South;
wire [31:0] dataOutProc22South;
//Processor 22 control and data signals
wire rdProc22East;
wire emptyProc22East;
wire [31:0] dataInProc22East;
//Processor 22 control and data signals
wire wrProc22East;
wire fullProc22East;
wire [31:0] dataOutProc22East;
//Processor 22 control and data signals
wire rdProc22West;
wire emptyProc22West;
wire [31:0] dataInProc22West;
//Processor 23 control and data signals
wire wrProc23North;
wire fullProc23North;
wire [31:0] dataOutProc23North;
//Processor 23 control and data signals
wire rdProc23South;
wire emptyProc23South;
wire [31:0] dataInProc23South;
//Processor 23 control and data signals
wire rdProc23East;
wire emptyProc23East;
wire [31:0] dataInProc23East;
//Processor 23 control and data signals
wire wrProc23East;
wire fullProc23East;
wire [31:0] dataOutProc23East;
//Processor 23 control and data signals
wire rdProc23West;
wire emptyProc23West;
wire [31:0] dataInProc23West;
//Processor 23 control and data signals
wire wrProc23West;
wire fullProc23West;
wire [31:0] dataOutProc23West;
//Processor 24 control and data signals
wire rdProc24North;
wire emptyProc24North;
wire [31:0] dataInProc24North;
//Processor 24 control and data signals
wire wrProc24North;
wire fullProc24North;
wire [31:0] dataOutProc24North;
//Processor 24 control and data signals
wire wrProc24South;
wire fullProc24South;
wire [31:0] dataOutProc24South;
//Processor 24 control and data signals
wire rdProc24East;
wire emptyProc24East;
wire [31:0] dataInProc24East;
//Processor 24 control and data signals
wire wrProc24East;
wire fullProc24East;
wire [31:0] dataOutProc24East;
//Processor 24 control and data signals
wire rdProc24West;
wire emptyProc24West;
wire [31:0] dataInProc24West;
//Processor 24 control and data signals
wire wrProc24West;
wire fullProc24West;
wire [31:0] dataOutProc24West;
//Processor 25 control and data signals
wire rdProc25South;
wire emptyProc25South;
wire [31:0] dataInProc25South;
//Processor 25 control and data signals
wire wrProc25South;
wire fullProc25South;
wire [31:0] dataOutProc25South;
//Processor 25 control and data signals
wire rdProc25East;
wire emptyProc25East;
wire [31:0] dataInProc25East;
//Processor 25 control and data signals
wire wrProc25East;
wire fullProc25East;
wire [31:0] dataOutProc25East;
//Processor 25 control and data signals
wire rdProc25West;
wire emptyProc25West;
wire [31:0] dataInProc25West;
//Processor 25 control and data signals
wire wrProc25West;
wire fullProc25West;
wire [31:0] dataOutProc25West;
//Processor 26 control and data signals
wire rdProc26North;
wire emptyProc26North;
wire [31:0] dataInProc26North;
//Processor 26 control and data signals
wire wrProc26South;
wire fullProc26South;
wire [31:0] dataOutProc26South;
//Processor 26 control and data signals
wire wrProc26East;
wire fullProc26East;
wire [31:0] dataOutProc26East;
//Processor 26 control and data signals
wire rdProc26West;
wire emptyProc26West;
wire [31:0] dataInProc26West;
//Processor 26 control and data signals
wire wrProc26West;
wire fullProc26West;
wire [31:0] dataOutProc26West;
//Processor 27 control and data signals
wire wrProc27North;
wire fullProc27North;
wire [31:0] dataOutProc27North;
//Processor 27 control and data signals
wire wrProc27South;
wire fullProc27South;
wire [31:0] dataOutProc27South;
//Processor 27 control and data signals
wire rdProc27East;
wire emptyProc27East;
wire [31:0] dataInProc27East;
//Processor 27 control and data signals
wire wrProc27East;
wire fullProc27East;
wire [31:0] dataOutProc27East;
//Processor 27 control and data signals
wire rdProc27West;
wire emptyProc27West;
wire [31:0] dataInProc27West;
//Processor 28 control and data signals
wire rdProc28North;
wire emptyProc28North;
wire [31:0] dataInProc28North;
//Processor 28 control and data signals
wire wrProc28South;
wire fullProc28South;
wire [31:0] dataOutProc28South;
//Processor 28 control and data signals
wire rdProc28East;
wire emptyProc28East;
wire [31:0] dataInProc28East;
//Processor 28 control and data signals
wire rdProc28West;
wire emptyProc28West;
wire [31:0] dataInProc28West;
//Processor 28 control and data signals
wire wrProc28West;
wire fullProc28West;
wire [31:0] dataOutProc28West;
//Processor 29 control and data signals
wire rdProc29North;
wire emptyProc29North;
wire [31:0] dataInProc29North;
//Processor 29 control and data signals
wire wrProc29North;
wire fullProc29North;
wire [31:0] dataOutProc29North;
//Processor 29 control and data signals
wire rdProc29South;
wire emptyProc29South;
wire [31:0] dataInProc29South;
//Processor 29 control and data signals
wire wrProc29West;
wire fullProc29West;
wire [31:0] dataOutProc29West;
//Processor 30 control and data signals
wire wrProc30North;
wire fullProc30North;
wire [31:0] dataOutProc30North;
//Processor 30 control and data signals
wire rdProc30South;
wire emptyProc30South;
wire [31:0] dataInProc30South;
//Processor 31 control and data signals
wire rdProc31North;
wire emptyProc31North;
wire [31:0] dataInProc31North;
//Processor 31 control and data signals
wire wrProc31North;
wire fullProc31North;
wire [31:0] dataOutProc31North;
//Processor 32 control and data signals
wire rdProc32North;
wire emptyProc32North;
wire [31:0] dataInProc32North;
//Processor 32 control and data signals
wire wrProc32North;
wire fullProc32North;
wire [31:0] dataOutProc32North;
//Processor 33 control and data signals
wire wrProc33North;
wire fullProc33North;
wire [31:0] dataOutProc33North;
//Processor 33 control and data signals
wire rdProc33South;
wire emptyProc33South;
wire [31:0] dataInProc33South;
//Processor 33 control and data signals
wire wrProc33South;
wire fullProc33South;
wire [31:0] dataOutProc33South;
//Processor 33 control and data signals
wire rdProc33East;
wire emptyProc33East;
wire [31:0] dataInProc33East;
//Processor 34 control and data signals
wire rdProc34North;
wire emptyProc34North;
wire [31:0] dataInProc34North;
//Processor 34 control and data signals
wire wrProc34West;
wire fullProc34West;
wire [31:0] dataOutProc34West;
//Processor 35 control and data signals
wire rdProc35North;
wire emptyProc35North;
wire [31:0] dataInProc35North;
//Processor 35 control and data signals
wire wrProc35North;
wire fullProc35North;
wire [31:0] dataOutProc35North;
//Processor 35 control and data signals
wire rdProc35South;
wire emptyProc35South;
wire [31:0] dataInProc35South;
//Processor 35 control and data signals
wire wrProc35East;
wire fullProc35East;
wire [31:0] dataOutProc35East;
//Processor 36 control and data signals
wire rdProc36North;
wire emptyProc36North;
wire [31:0] dataInProc36North;
//Processor 36 control and data signals
wire wrProc36South;
wire fullProc36South;
wire [31:0] dataOutProc36South;
//Processor 36 control and data signals
wire wrProc36East;
wire fullProc36East;
wire [31:0] dataOutProc36East;
//Processor 36 control and data signals
wire rdProc36West;
wire emptyProc36West;
wire [31:0] dataInProc36West;
//Processor 37 control and data signals
wire rdProc37North;
wire emptyProc37North;
wire [31:0] dataInProc37North;
//Processor 37 control and data signals
wire wrProc37South;
wire fullProc37South;
wire [31:0] dataOutProc37South;
//Processor 37 control and data signals
wire rdProc37West;
wire emptyProc37West;
wire [31:0] dataInProc37West;
//Processor 38 control and data signals
wire rdProc38North;
wire emptyProc38North;
wire [31:0] dataInProc38North;
//Processor 38 control and data signals
wire rdProc38South;
wire emptyProc38South;
wire [31:0] dataInProc38South;
//Processor 38 control and data signals
wire wrProc38South;
wire fullProc38South;
wire [31:0] dataOutProc38South;
//Processor 38 control and data signals
wire wrProc38East;
wire fullProc38East;
wire [31:0] dataOutProc38East;
//Processor 39 control and data signals
wire wrProc39North;
wire fullProc39North;
wire [31:0] dataOutProc39North;
//Processor 39 control and data signals
wire rdProc39South;
wire emptyProc39South;
wire [31:0] dataInProc39South;
//Processor 39 control and data signals
wire rdProc39West;
wire emptyProc39West;
wire [31:0] dataInProc39West;
//Processor 40 control and data signals
wire wrProc40North;
wire fullProc40North;
wire [31:0] dataOutProc40North;
//Processor 40 control and data signals
wire rdProc40South;
wire emptyProc40South;
wire [31:0] dataInProc40South;
//Processor 40 control and data signals
wire wrProc40South;
wire fullProc40South;
wire [31:0] dataOutProc40South;
//Processor 40 control and data signals
wire rdProc40East;
wire emptyProc40East;
wire [31:0] dataInProc40East;
//Processor 41 control and data signals
wire rdProc41East;
wire emptyProc41East;
wire [31:0] dataInProc41East;
//Processor 41 control and data signals
wire wrProc41West;
wire fullProc41West;
wire [31:0] dataOutProc41West;
//Processor 42 control and data signals
wire rdProc42South;
wire emptyProc42South;
wire [31:0] dataInProc42South;
//Processor 42 control and data signals
wire rdProc42East;
wire emptyProc42East;
wire [31:0] dataInProc42East;
//Processor 42 control and data signals
wire wrProc42East;
wire fullProc42East;
wire [31:0] dataOutProc42East;
//Processor 42 control and data signals
wire wrProc42West;
wire fullProc42West;
wire [31:0] dataOutProc42West;
//Processor 43 control and data signals
wire rdProc43North;
wire emptyProc43North;
wire [31:0] dataInProc43North;
//Processor 43 control and data signals
wire wrProc43North;
wire fullProc43North;
wire [31:0] dataOutProc43North;
//Processor 43 control and data signals
wire rdProc43South;
wire emptyProc43South;
wire [31:0] dataInProc43South;
//Processor 43 control and data signals
wire wrProc43South;
wire fullProc43South;
wire [31:0] dataOutProc43South;
//Processor 43 control and data signals
wire wrProc43East;
wire fullProc43East;
wire [31:0] dataOutProc43East;
//Processor 43 control and data signals
wire rdProc43West;
wire emptyProc43West;
wire [31:0] dataInProc43West;
//Processor 43 control and data signals
wire wrProc43West;
wire fullProc43West;
wire [31:0] dataOutProc43West;
//Processor 44 control and data signals
wire wrProc44East;
wire fullProc44East;
wire [31:0] dataOutProc44East;
//Processor 44 control and data signals
wire rdProc44West;
wire emptyProc44West;
wire [31:0] dataInProc44West;
//Processor 45 control and data signals
wire wrProc45North;
wire fullProc45North;
wire [31:0] dataOutProc45North;
//Processor 45 control and data signals
wire wrProc45South;
wire fullProc45South;
wire [31:0] dataOutProc45South;
//Processor 45 control and data signals
wire rdProc45East;
wire emptyProc45East;
wire [31:0] dataInProc45East;
//Processor 45 control and data signals
wire rdProc45West;
wire emptyProc45West;
wire [31:0] dataInProc45West;
//Processor 46 control and data signals
wire rdProc46North;
wire emptyProc46North;
wire [31:0] dataInProc46North;
//Processor 46 control and data signals
wire wrProc46South;
wire fullProc46South;
wire [31:0] dataOutProc46South;
//Processor 46 control and data signals
wire rdProc46East;
wire emptyProc46East;
wire [31:0] dataInProc46East;
//Processor 46 control and data signals
wire wrProc46West;
wire fullProc46West;
wire [31:0] dataOutProc46West;
//Processor 47 control and data signals
wire rdProc47North;
wire emptyProc47North;
wire [31:0] dataInProc47North;
//Processor 47 control and data signals
wire wrProc47South;
wire fullProc47South;
wire [31:0] dataOutProc47South;
//Processor 47 control and data signals
wire wrProc47West;
wire fullProc47West;
wire [31:0] dataOutProc47West;
//Processor 48 control and data signals
wire rdProc48North;
wire emptyProc48North;
wire [31:0] dataInProc48North;
//Processor 48 control and data signals
wire wrProc48North;
wire fullProc48North;
wire [31:0] dataOutProc48North;
//Processor 48 control and data signals
wire rdProc48South;
wire emptyProc48South;
wire [31:0] dataInProc48South;
//Processor 48 control and data signals
wire wrProc48South;
wire fullProc48South;
wire [31:0] dataOutProc48South;
//Processor 49 control and data signals
wire wrProc49North;
wire fullProc49North;
wire [31:0] dataOutProc49North;
//Processor 49 control and data signals
wire rdProc49South;
wire emptyProc49South;
wire [31:0] dataInProc49South;
//Processor 50 control and data signals
wire rdProc50North;
wire emptyProc50North;
wire [31:0] dataInProc50North;
//Processor 50 control and data signals
wire wrProc50North;
wire fullProc50North;
wire [31:0] dataOutProc50North;
//Processor 50 control and data signals
wire rdProc50East;
wire emptyProc50East;
wire [31:0] dataInProc50East;
//Processor 50 control and data signals
wire wrProc50East;
wire fullProc50East;
wire [31:0] dataOutProc50East;
//Processor 51 control and data signals
wire rdProc51East;
wire emptyProc51East;
wire [31:0] dataInProc51East;
//Processor 51 control and data signals
wire wrProc51East;
wire fullProc51East;
wire [31:0] dataOutProc51East;
//Processor 51 control and data signals
wire rdProc51West;
wire emptyProc51West;
wire [31:0] dataInProc51West;
//Processor 51 control and data signals
wire wrProc51West;
wire fullProc51West;
wire [31:0] dataOutProc51West;
//Processor 52 control and data signals
wire wrProc52North;
wire fullProc52North;
wire [31:0] dataOutProc52North;
//Processor 52 control and data signals
wire rdProc52South;
wire emptyProc52South;
wire [31:0] dataInProc52South;
//Processor 52 control and data signals
wire wrProc52South;
wire fullProc52South;
wire [31:0] dataOutProc52South;
//Processor 52 control and data signals
wire rdProc52East;
wire emptyProc52East;
wire [31:0] dataInProc52East;
//Processor 52 control and data signals
wire wrProc52East;
wire fullProc52East;
wire [31:0] dataOutProc52East;
//Processor 52 control and data signals
wire rdProc52West;
wire emptyProc52West;
wire [31:0] dataInProc52West;
//Processor 52 control and data signals
wire wrProc52West;
wire fullProc52West;
wire [31:0] dataOutProc52West;
//Processor 53 control and data signals
wire rdProc53North;
wire emptyProc53North;
wire [31:0] dataInProc53North;
//Processor 53 control and data signals
wire wrProc53North;
wire fullProc53North;
wire [31:0] dataOutProc53North;
//Processor 53 control and data signals
wire rdProc53South;
wire emptyProc53South;
wire [31:0] dataInProc53South;
//Processor 53 control and data signals
wire wrProc53South;
wire fullProc53South;
wire [31:0] dataOutProc53South;
//Processor 53 control and data signals
wire rdProc53East;
wire emptyProc53East;
wire [31:0] dataInProc53East;
//Processor 53 control and data signals
wire rdProc53West;
wire emptyProc53West;
wire [31:0] dataInProc53West;
//Processor 53 control and data signals
wire wrProc53West;
wire fullProc53West;
wire [31:0] dataOutProc53West;
//Processor 54 control and data signals
wire rdProc54East;
wire emptyProc54East;
wire [31:0] dataInProc54East;
//Processor 54 control and data signals
wire wrProc54West;
wire fullProc54West;
wire [31:0] dataOutProc54West;
//Processor 55 control and data signals
wire rdProc55North;
wire emptyProc55North;
wire [31:0] dataInProc55North;
//Processor 55 control and data signals
wire rdProc55East;
wire emptyProc55East;
wire [31:0] dataInProc55East;
//Processor 55 control and data signals
wire wrProc55West;
wire fullProc55West;
wire [31:0] dataOutProc55West;
//Processor 56 control and data signals
wire rdProc56North;
wire emptyProc56North;
wire [31:0] dataInProc56North;
//Processor 56 control and data signals
wire rdProc56East;
wire emptyProc56East;
wire [31:0] dataInProc56East;
//Processor 56 control and data signals
wire wrProc56East;
wire fullProc56East;
wire [31:0] dataOutProc56East;
//Processor 56 control and data signals
wire wrProc56West;
wire fullProc56West;
wire [31:0] dataOutProc56West;
//Processor 57 control and data signals
wire rdProc57North;
wire emptyProc57North;
wire [31:0] dataInProc57North;
//Processor 57 control and data signals
wire wrProc57South;
wire fullProc57South;
wire [31:0] dataOutProc57South;
//Processor 57 control and data signals
wire rdProc57West;
wire emptyProc57West;
wire [31:0] dataInProc57West;
//Processor 57 control and data signals
wire wrProc57West;
wire fullProc57West;
wire [31:0] dataOutProc57West;
//Processor 58 control and data signals
wire rdProc58North;
wire emptyProc58North;
wire [31:0] dataInProc58North;
//Processor 58 control and data signals
wire wrProc58North;
wire fullProc58North;
wire [31:0] dataOutProc58North;
//Processor 58 control and data signals
wire wrProc58South;
wire fullProc58South;
wire [31:0] dataOutProc58South;
//Processor 58 control and data signals
wire rdProc58East;
wire emptyProc58East;
wire [31:0] dataInProc58East;
//Processor 59 control and data signals
wire wrProc59North;
wire fullProc59North;
wire [31:0] dataOutProc59North;
//Processor 59 control and data signals
wire rdProc59South;
wire emptyProc59South;
wire [31:0] dataInProc59South;
//Processor 59 control and data signals
wire wrProc59West;
wire fullProc59West;
wire [31:0] dataOutProc59West;
//Processor 60 control and data signals
wire wrProc60South;
wire fullProc60South;
wire [31:0] dataOutProc60South;
//Processor 60 control and data signals
wire rdProc60East;
wire emptyProc60East;
wire [31:0] dataInProc60East;
//Processor 61 control and data signals
wire rdProc61South;
wire emptyProc61South;
wire [31:0] dataInProc61South;
//Processor 61 control and data signals
wire wrProc61East;
wire fullProc61East;
wire [31:0] dataOutProc61East;
//Processor 61 control and data signals
wire wrProc61West;
wire fullProc61West;
wire [31:0] dataOutProc61West;
//Processor 62 control and data signals
wire rdProc62North;
wire emptyProc62North;
wire [31:0] dataInProc62North;
//Processor 62 control and data signals
wire wrProc62North;
wire fullProc62North;
wire [31:0] dataOutProc62North;
//Processor 62 control and data signals
wire rdProc62South;
wire emptyProc62South;
wire [31:0] dataInProc62South;
//Processor 62 control and data signals
wire wrProc62South;
wire fullProc62South;
wire [31:0] dataOutProc62South;
//Processor 62 control and data signals
wire wrProc62East;
wire fullProc62East;
wire [31:0] dataOutProc62East;
//Processor 62 control and data signals
wire rdProc62West;
wire emptyProc62West;
wire [31:0] dataInProc62West;
//Processor 63 control and data signals
wire rdProc63North;
wire emptyProc63North;
wire [31:0] dataInProc63North;
//Processor 63 control and data signals
wire wrProc63North;
wire fullProc63North;
wire [31:0] dataOutProc63North;
//Processor 63 control and data signals
wire rdProc63South;
wire emptyProc63South;
wire [31:0] dataInProc63South;
//Processor 63 control and data signals
wire wrProc63South;
wire fullProc63South;
wire [31:0] dataOutProc63South;
//Processor 63 control and data signals
wire wrProc63East;
wire fullProc63East;
wire [31:0] dataOutProc63East;
//Processor 63 control and data signals
wire rdProc63West;
wire emptyProc63West;
wire [31:0] dataInProc63West;
//Processor 64 control and data signals
wire wrProc64South;
wire fullProc64South;
wire [31:0] dataOutProc64South;
//Processor 64 control and data signals
wire rdProc64East;
wire emptyProc64East;
wire [31:0] dataInProc64East;
//Processor 64 control and data signals
wire wrProc64East;
wire fullProc64East;
wire [31:0] dataOutProc64East;
//Processor 64 control and data signals
wire rdProc64West;
wire emptyProc64West;
wire [31:0] dataInProc64West;
//Processor 65 control and data signals
wire rdProc65West;
wire emptyProc65West;
wire [31:0] dataInProc65West;
//Processor 65 control and data signals
wire wrProc65West;
wire fullProc65West;
wire [31:0] dataOutProc65West;
//Processor 66 control and data signals
wire rdProc66South;
wire emptyProc66South;
wire [31:0] dataInProc66South;
//Processor 66 control and data signals
wire wrProc66East;
wire fullProc66East;
wire [31:0] dataOutProc66East;
//Processor 67 control and data signals
wire rdProc67North;
wire emptyProc67North;
wire [31:0] dataInProc67North;
//Processor 67 control and data signals
wire wrProc67South;
wire fullProc67South;
wire [31:0] dataOutProc67South;
//Processor 67 control and data signals
wire wrProc67East;
wire fullProc67East;
wire [31:0] dataOutProc67East;
//Processor 67 control and data signals
wire rdProc67West;
wire emptyProc67West;
wire [31:0] dataInProc67West;
//Processor 68 control and data signals
wire rdProc68North;
wire emptyProc68North;
wire [31:0] dataInProc68North;
//Processor 68 control and data signals
wire wrProc68South;
wire fullProc68South;
wire [31:0] dataOutProc68South;
//Processor 68 control and data signals
wire wrProc68East;
wire fullProc68East;
wire [31:0] dataOutProc68East;
//Processor 68 control and data signals
wire rdProc68West;
wire emptyProc68West;
wire [31:0] dataInProc68West;
//Processor 69 control and data signals
wire wrProc69North;
wire fullProc69North;
wire [31:0] dataOutProc69North;
//Processor 69 control and data signals
wire rdProc69South;
wire emptyProc69South;
wire [31:0] dataInProc69South;
//Processor 69 control and data signals
wire rdProc69West;
wire emptyProc69West;
wire [31:0] dataInProc69West;
//Processor 70 control and data signals
wire rdProc70North;
wire emptyProc70North;
wire [31:0] dataInProc70North;
//Processor 70 control and data signals
wire wrProc70South;
wire fullProc70South;
wire [31:0] dataOutProc70South;
//Processor 71 control and data signals
wire wrProc71North;
wire fullProc71North;
wire [31:0] dataOutProc71North;
//Processor 71 control and data signals
wire rdProc71South;
wire emptyProc71South;
wire [31:0] dataInProc71South;
//Processor 72 control and data signals
wire rdProc72North;
wire emptyProc72North;
wire [31:0] dataInProc72North;
//Processor 72 control and data signals
wire wrProc72North;
wire fullProc72North;
wire [31:0] dataOutProc72North;
//Processor 72 control and data signals
wire rdProc72East;
wire emptyProc72East;
wire [31:0] dataInProc72East;
//Processor 72 control and data signals
wire wrProc72East;
wire fullProc72East;
wire [31:0] dataOutProc72East;
//Processor 73 control and data signals
wire rdProc73North;
wire emptyProc73North;
wire [31:0] dataInProc73North;
//Processor 73 control and data signals
wire wrProc73North;
wire fullProc73North;
wire [31:0] dataOutProc73North;
//Processor 73 control and data signals
wire wrProc73South;
wire fullProc73South;
wire [31:0] dataOutProc73South;
//Processor 73 control and data signals
wire rdProc73East;
wire emptyProc73East;
wire [31:0] dataInProc73East;
//Processor 73 control and data signals
wire rdProc73West;
wire emptyProc73West;
wire [31:0] dataInProc73West;
//Processor 73 control and data signals
wire wrProc73West;
wire fullProc73West;
wire [31:0] dataOutProc73West;
//Processor 74 control and data signals
wire rdProc74North;
wire emptyProc74North;
wire [31:0] dataInProc74North;
//Processor 74 control and data signals
wire rdProc74South;
wire emptyProc74South;
wire [31:0] dataInProc74South;
//Processor 74 control and data signals
wire wrProc74South;
wire fullProc74South;
wire [31:0] dataOutProc74South;
//Processor 74 control and data signals
wire rdProc74East;
wire emptyProc74East;
wire [31:0] dataInProc74East;
//Processor 74 control and data signals
wire wrProc74East;
wire fullProc74East;
wire [31:0] dataOutProc74East;
//Processor 74 control and data signals
wire wrProc74West;
wire fullProc74West;
wire [31:0] dataOutProc74West;
//Processor 75 control and data signals
wire rdProc75East;
wire emptyProc75East;
wire [31:0] dataInProc75East;
//Processor 75 control and data signals
wire wrProc75East;
wire fullProc75East;
wire [31:0] dataOutProc75East;
//Processor 75 control and data signals
wire rdProc75West;
wire emptyProc75West;
wire [31:0] dataInProc75West;
//Processor 75 control and data signals
wire wrProc75West;
wire fullProc75West;
wire [31:0] dataOutProc75West;
//Processor 76 control and data signals
wire wrProc76North;
wire fullProc76North;
wire [31:0] dataOutProc76North;
//Processor 76 control and data signals
wire rdProc76South;
wire emptyProc76South;
wire [31:0] dataInProc76South;
//Processor 76 control and data signals
wire rdProc76West;
wire emptyProc76West;
wire [31:0] dataInProc76West;
//Processor 76 control and data signals
wire wrProc76West;
wire fullProc76West;
wire [31:0] dataOutProc76West;
//Processor 77 control and data signals
wire rdProc77North;
wire emptyProc77North;
wire [31:0] dataInProc77North;
//Processor 77 control and data signals
wire wrProc77South;
wire fullProc77South;
wire [31:0] dataOutProc77South;
//Processor 77 control and data signals
wire rdProc77East;
wire emptyProc77East;
wire [31:0] dataInProc77East;
//Processor 78 control and data signals
wire rdProc78North;
wire emptyProc78North;
wire [31:0] dataInProc78North;
//Processor 78 control and data signals
wire wrProc78West;
wire fullProc78West;
wire [31:0] dataOutProc78West;
//Processor 79 control and data signals
wire wrProc79North;
wire fullProc79North;
wire [31:0] dataOutProc79North;
//Processor 79 control and data signals
wire rdProc79South;
wire emptyProc79South;
wire [31:0] dataInProc79South;
//Processor 80 control and data signals
wire rdProc80North;
wire emptyProc80North;
wire [31:0] dataInProc80North;
//Processor 80 control and data signals
wire wrProc80East;
wire fullProc80East;
wire [31:0] dataOutProc80East;
//Processor 81 control and data signals
wire wrProc81North;
wire fullProc81North;
wire [31:0] dataOutProc81North;
//Processor 81 control and data signals
wire rdProc81East;
wire emptyProc81East;
wire [31:0] dataInProc81East;
//Processor 81 control and data signals
wire wrProc81East;
wire fullProc81East;
wire [31:0] dataOutProc81East;
//Processor 81 control and data signals
wire rdProc81West;
wire emptyProc81West;
wire [31:0] dataInProc81West;
//Processor 82 control and data signals
wire rdProc82East;
wire emptyProc82East;
wire [31:0] dataInProc82East;
//Processor 82 control and data signals
wire wrProc82East;
wire fullProc82East;
wire [31:0] dataOutProc82East;
//Processor 82 control and data signals
wire rdProc82West;
wire emptyProc82West;
wire [31:0] dataInProc82West;
//Processor 82 control and data signals
wire wrProc82West;
wire fullProc82West;
wire [31:0] dataOutProc82West;
//Processor 83 control and data signals
wire rdProc83North;
wire emptyProc83North;
wire [31:0] dataInProc83North;
//Processor 83 control and data signals
wire rdProc83East;
wire emptyProc83East;
wire [31:0] dataInProc83East;
//Processor 83 control and data signals
wire wrProc83East;
wire fullProc83East;
wire [31:0] dataOutProc83East;
//Processor 83 control and data signals
wire rdProc83West;
wire emptyProc83West;
wire [31:0] dataInProc83West;
//Processor 83 control and data signals
wire wrProc83West;
wire fullProc83West;
wire [31:0] dataOutProc83West;
//Processor 84 control and data signals
wire rdProc84North;
wire emptyProc84North;
wire [31:0] dataInProc84North;
//Processor 84 control and data signals
wire wrProc84North;
wire fullProc84North;
wire [31:0] dataOutProc84North;
//Processor 84 control and data signals
wire rdProc84East;
wire emptyProc84East;
wire [31:0] dataInProc84East;
//Processor 84 control and data signals
wire wrProc84East;
wire fullProc84East;
wire [31:0] dataOutProc84East;
//Processor 84 control and data signals
wire rdProc84West;
wire emptyProc84West;
wire [31:0] dataInProc84West;
//Processor 84 control and data signals
wire wrProc84West;
wire fullProc84West;
wire [31:0] dataOutProc84West;
//Processor 85 control and data signals
wire rdProc85West;
wire emptyProc85West;
wire [31:0] dataInProc85West;
//Processor 85 control and data signals
wire wrProc85West;
wire fullProc85West;
wire [31:0] dataOutProc85West;
//Processor 86 control and data signals
wire wrProc86North;
wire fullProc86North;
wire [31:0] dataOutProc86North;
//Processor 86 control and data signals
wire rdProc86East;
wire emptyProc86East;
wire [31:0] dataInProc86East;
//Processor 87 control and data signals
wire rdProc87North;
wire emptyProc87North;
wire [31:0] dataInProc87North;
//Processor 87 control and data signals
wire wrProc87East;
wire fullProc87East;
wire [31:0] dataOutProc87East;
//Processor 87 control and data signals
wire wrProc87West;
wire fullProc87West;
wire [31:0] dataOutProc87West;
//Processor 88 control and data signals
wire wrProc88East;
wire fullProc88East;
wire [31:0] dataOutProc88East;
//Processor 88 control and data signals
wire rdProc88West;
wire emptyProc88West;
wire [31:0] dataInProc88West;
//Processor 89 control and data signals
wire wrProc89North;
wire fullProc89North;
wire [31:0] dataOutProc89North;
//Processor 89 control and data signals
wire rdProc89West;
wire emptyProc89West;
wire [31:0] dataInProc89West;
//PROCESSOR 0
system proc0(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe0),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe0),
.wrSouth(wrProc0South),
.fullSouth(fullProc0South),
.dataOutSouth(dataOutProc0South),
.wrEast(wrProc0East),
.fullEast(fullProc0East),
.dataOutEast(dataOutProc0East));
//PROCESSOR 1
system proc1(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe1),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe1),
.wrSouth(wrProc1South),
.fullSouth(fullProc1South),
.dataOutSouth(dataOutProc1South),
.rdWest(rdProc1West),
.emptyWest(emptyProc1West),
.dataInWest(dataInProc1West));
//PROCESSOR 2
system proc2(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe2),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe2));
//PROCESSOR 3
system proc3(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe3),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe3));
//PROCESSOR 4
system proc4(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe4),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe4),
.rdSouth(rdProc4South),
.emptySouth(emptyProc4South),
.dataInSouth(dataInProc4South),
.rdEast(rdProc4East),
.emptyEast(emptyProc4East),
.dataInEast(dataInProc4East),
.wrEast(wrProc4East),
.fullEast(fullProc4East),
.dataOutEast(dataOutProc4East));
//PROCESSOR 5
system proc5(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe5),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe5),
.rdEast(rdProc5East),
.emptyEast(emptyProc5East),
.dataInEast(dataInProc5East),
.rdWest(rdProc5West),
.emptyWest(emptyProc5West),
.dataInWest(dataInProc5West),
.wrWest(wrProc5West),
.fullWest(fullProc5West),
.dataOutWest(dataOutProc5West),
.reg_file_b_readdataout(reg_file_b_readdataout));
//PROCESSOR 6
system proc6(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe6),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe6),
.rdSouth(rdProc6South),
.emptySouth(emptyProc6South),
.dataInSouth(dataInProc6South),
.wrSouth(wrProc6South),
.fullSouth(fullProc6South),
.dataOutSouth(dataOutProc6South),
.rdEast(rdProc6East),
.emptyEast(emptyProc6East),
.dataInEast(dataInProc6East),
.wrWest(wrProc6West),
.fullWest(fullProc6West),
.dataOutWest(dataOutProc6West));
//PROCESSOR 7
system proc7(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe7),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe7),
.rdSouth(rdProc7South),
.emptySouth(emptyProc7South),
.dataInSouth(dataInProc7South),
.wrWest(wrProc7West),
.fullWest(fullProc7West),
.dataOutWest(dataOutProc7West));
//PROCESSOR 8
system proc8(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe8),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe8),
.rdSouth(rdProc8South),
.emptySouth(emptyProc8South),
.dataInSouth(dataInProc8South),
.wrSouth(wrProc8South),
.fullSouth(fullProc8South),
.dataOutSouth(dataOutProc8South),
.rdEast(rdProc8East),
.emptyEast(emptyProc8East),
.dataInEast(dataInProc8East));
//PROCESSOR 9
system proc9(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe9),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe9),
.rdSouth(rdProc9South),
.emptySouth(emptyProc9South),
.dataInSouth(dataInProc9South),
.wrWest(wrProc9West),
.fullWest(fullProc9West),
.dataOutWest(dataOutProc9West));
//PROCESSOR 10
system proc10(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe10),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe10),
.rdNorth(rdProc10North),
.emptyNorth(emptyProc10North),
.dataInNorth(dataInProc10North),
.wrEast(wrProc10East),
.fullEast(fullProc10East),
.dataOutEast(dataOutProc10East));
//PROCESSOR 11
system proc11(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe11),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe11),
.rdNorth(rdProc11North),
.emptyNorth(emptyProc11North),
.dataInNorth(dataInProc11North),
.wrSouth(wrProc11South),
.fullSouth(fullProc11South),
.dataOutSouth(dataOutProc11South),
.rdWest(rdProc11West),
.emptyWest(emptyProc11West),
.dataInWest(dataInProc11West));
//PROCESSOR 12
system proc12(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe12),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe12),
.rdSouth(rdProc12South),
.emptySouth(emptyProc12South),
.dataInSouth(dataInProc12South),
.wrEast(wrProc12East),
.fullEast(fullProc12East),
.dataOutEast(dataOutProc12East));
//PROCESSOR 13
system proc13(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe13),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe13),
.rdSouth(rdProc13South),
.emptySouth(emptyProc13South),
.dataInSouth(dataInProc13South),
.wrEast(wrProc13East),
.fullEast(fullProc13East),
.dataOutEast(dataOutProc13East),
.rdWest(rdProc13West),
.emptyWest(emptyProc13West),
.dataInWest(dataInProc13West));
//PROCESSOR 14
system proc14(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe14),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe14),
.wrNorth(wrProc14North),
.fullNorth(fullProc14North),
.dataOutNorth(dataOutProc14North),
.rdSouth(rdProc14South),
.emptySouth(emptyProc14South),
.dataInSouth(dataInProc14South),
.wrSouth(wrProc14South),
.fullSouth(fullProc14South),
.dataOutSouth(dataOutProc14South),
.wrEast(wrProc14East),
.fullEast(fullProc14East),
.dataOutEast(dataOutProc14East),
.rdWest(rdProc14West),
.emptyWest(emptyProc14West),
.dataInWest(dataInProc14West));
//PROCESSOR 15
system proc15(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe15),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe15),
.wrEast(wrProc15East),
.fullEast(fullProc15East),
.dataOutEast(dataOutProc15East),
.rdWest(rdProc15West),
.emptyWest(emptyProc15West),
.dataInWest(dataInProc15West));
//PROCESSOR 16
system proc16(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe16),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe16),
.rdNorth(rdProc16North),
.emptyNorth(emptyProc16North),
.dataInNorth(dataInProc16North),
.wrNorth(wrProc16North),
.fullNorth(fullProc16North),
.dataOutNorth(dataOutProc16North),
.wrSouth(wrProc16South),
.fullSouth(fullProc16South),
.dataOutSouth(dataOutProc16South),
.rdWest(rdProc16West),
.emptyWest(emptyProc16West),
.dataInWest(dataInProc16West));
//PROCESSOR 17
system proc17(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe17),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe17),
.wrNorth(wrProc17North),
.fullNorth(fullProc17North),
.dataOutNorth(dataOutProc17North),
.rdSouth(rdProc17South),
.emptySouth(emptyProc17South),
.dataInSouth(dataInProc17South));
//PROCESSOR 18
system proc18(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe18),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe18),
.rdNorth(rdProc18North),
.emptyNorth(emptyProc18North),
.dataInNorth(dataInProc18North),
.wrNorth(wrProc18North),
.fullNorth(fullProc18North),
.dataOutNorth(dataOutProc18North),
.wrSouth(wrProc18South),
.fullSouth(fullProc18South),
.dataOutSouth(dataOutProc18South));
//PROCESSOR 19
system proc19(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe19),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe19),
.wrNorth(wrProc19North),
.fullNorth(fullProc19North),
.dataOutNorth(dataOutProc19North),
.rdSouth(rdProc19South),
.emptySouth(emptyProc19South),
.dataInSouth(dataInProc19South),
.wrSouth(wrProc19South),
.fullSouth(fullProc19South),
.dataOutSouth(dataOutProc19South));
//PROCESSOR 20
system proc20(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe20),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe20),
.rdSouth(rdProc20South),
.emptySouth(emptyProc20South),
.dataInSouth(dataInProc20South),
.wrEast(wrProc20East),
.fullEast(fullProc20East),
.dataOutEast(dataOutProc20East));
//PROCESSOR 21
system proc21(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe21),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe21),
.rdNorth(rdProc21North),
.emptyNorth(emptyProc21North),
.dataInNorth(dataInProc21North),
.rdSouth(rdProc21South),
.emptySouth(emptyProc21South),
.dataInSouth(dataInProc21South),
.wrSouth(wrProc21South),
.fullSouth(fullProc21South),
.dataOutSouth(dataOutProc21South),
.wrEast(wrProc21East),
.fullEast(fullProc21East),
.dataOutEast(dataOutProc21East),
.rdWest(rdProc21West),
.emptyWest(emptyProc21West),
.dataInWest(dataInProc21West));
//PROCESSOR 22
system proc22(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe22),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe22),
.wrNorth(wrProc22North),
.fullNorth(fullProc22North),
.dataOutNorth(dataOutProc22North),
.rdSouth(rdProc22South),
.emptySouth(emptyProc22South),
.dataInSouth(dataInProc22South),
.wrSouth(wrProc22South),
.fullSouth(fullProc22South),
.dataOutSouth(dataOutProc22South),
.rdEast(rdProc22East),
.emptyEast(emptyProc22East),
.dataInEast(dataInProc22East),
.wrEast(wrProc22East),
.fullEast(fullProc22East),
.dataOutEast(dataOutProc22East),
.rdWest(rdProc22West),
.emptyWest(emptyProc22West),
.dataInWest(dataInProc22West));
//PROCESSOR 23
system proc23(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe23),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe23),
.wrNorth(wrProc23North),
.fullNorth(fullProc23North),
.dataOutNorth(dataOutProc23North),
.rdSouth(rdProc23South),
.emptySouth(emptyProc23South),
.dataInSouth(dataInProc23South),
.rdEast(rdProc23East),
.emptyEast(emptyProc23East),
.dataInEast(dataInProc23East),
.wrEast(wrProc23East),
.fullEast(fullProc23East),
.dataOutEast(dataOutProc23East),
.rdWest(rdProc23West),
.emptyWest(emptyProc23West),
.dataInWest(dataInProc23West),
.wrWest(wrProc23West),
.fullWest(fullProc23West),
.dataOutWest(dataOutProc23West));
//PROCESSOR 24
system proc24(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe24),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe24),
.rdNorth(rdProc24North),
.emptyNorth(emptyProc24North),
.dataInNorth(dataInProc24North),
.wrNorth(wrProc24North),
.fullNorth(fullProc24North),
.dataOutNorth(dataOutProc24North),
.wrSouth(wrProc24South),
.fullSouth(fullProc24South),
.dataOutSouth(dataOutProc24South),
.rdEast(rdProc24East),
.emptyEast(emptyProc24East),
.dataInEast(dataInProc24East),
.wrEast(wrProc24East),
.fullEast(fullProc24East),
.dataOutEast(dataOutProc24East),
.rdWest(rdProc24West),
.emptyWest(emptyProc24West),
.dataInWest(dataInProc24West),
.wrWest(wrProc24West),
.fullWest(fullProc24West),
.dataOutWest(dataOutProc24West));
//PROCESSOR 25
system proc25(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe25),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe25),
.rdSouth(rdProc25South),
.emptySouth(emptyProc25South),
.dataInSouth(dataInProc25South),
.wrSouth(wrProc25South),
.fullSouth(fullProc25South),
.dataOutSouth(dataOutProc25South),
.rdEast(rdProc25East),
.emptyEast(emptyProc25East),
.dataInEast(dataInProc25East),
.wrEast(wrProc25East),
.fullEast(fullProc25East),
.dataOutEast(dataOutProc25East),
.rdWest(rdProc25West),
.emptyWest(emptyProc25West),
.dataInWest(dataInProc25West),
.wrWest(wrProc25West),
.fullWest(fullProc25West),
.dataOutWest(dataOutProc25West));
//PROCESSOR 26
system proc26(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe26),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe26),
.rdNorth(rdProc26North),
.emptyNorth(emptyProc26North),
.dataInNorth(dataInProc26North),
.wrSouth(wrProc26South),
.fullSouth(fullProc26South),
.dataOutSouth(dataOutProc26South),
.wrEast(wrProc26East),
.fullEast(fullProc26East),
.dataOutEast(dataOutProc26East),
.rdWest(rdProc26West),
.emptyWest(emptyProc26West),
.dataInWest(dataInProc26West),
.wrWest(wrProc26West),
.fullWest(fullProc26West),
.dataOutWest(dataOutProc26West));
//PROCESSOR 27
system proc27(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe27),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe27),
.wrNorth(wrProc27North),
.fullNorth(fullProc27North),
.dataOutNorth(dataOutProc27North),
.wrSouth(wrProc27South),
.fullSouth(fullProc27South),
.dataOutSouth(dataOutProc27South),
.rdEast(rdProc27East),
.emptyEast(emptyProc27East),
.dataInEast(dataInProc27East),
.wrEast(wrProc27East),
.fullEast(fullProc27East),
.dataOutEast(dataOutProc27East),
.rdWest(rdProc27West),
.emptyWest(emptyProc27West),
.dataInWest(dataInProc27West));
//PROCESSOR 28
system proc28(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe28),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe28),
.rdNorth(rdProc28North),
.emptyNorth(emptyProc28North),
.dataInNorth(dataInProc28North),
.wrSouth(wrProc28South),
.fullSouth(fullProc28South),
.dataOutSouth(dataOutProc28South),
.rdEast(rdProc28East),
.emptyEast(emptyProc28East),
.dataInEast(dataInProc28East),
.rdWest(rdProc28West),
.emptyWest(emptyProc28West),
.dataInWest(dataInProc28West),
.wrWest(wrProc28West),
.fullWest(fullProc28West),
.dataOutWest(dataOutProc28West));
//PROCESSOR 29
system proc29(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe29),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe29),
.rdNorth(rdProc29North),
.emptyNorth(emptyProc29North),
.dataInNorth(dataInProc29North),
.wrNorth(wrProc29North),
.fullNorth(fullProc29North),
.dataOutNorth(dataOutProc29North),
.rdSouth(rdProc29South),
.emptySouth(emptyProc29South),
.dataInSouth(dataInProc29South),
.wrWest(wrProc29West),
.fullWest(fullProc29West),
.dataOutWest(dataOutProc29West));
//PROCESSOR 30
system proc30(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe30),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe30),
.wrNorth(wrProc30North),
.fullNorth(fullProc30North),
.dataOutNorth(dataOutProc30North),
.rdSouth(rdProc30South),
.emptySouth(emptyProc30South),
.dataInSouth(dataInProc30South));
//PROCESSOR 31
system proc31(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe31),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe31),
.rdNorth(rdProc31North),
.emptyNorth(emptyProc31North),
.dataInNorth(dataInProc31North),
.wrNorth(wrProc31North),
.fullNorth(fullProc31North),
.dataOutNorth(dataOutProc31North));
//PROCESSOR 32
system proc32(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe32),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe32),
.rdNorth(rdProc32North),
.emptyNorth(emptyProc32North),
.dataInNorth(dataInProc32North),
.wrNorth(wrProc32North),
.fullNorth(fullProc32North),
.dataOutNorth(dataOutProc32North));
//PROCESSOR 33
system proc33(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe33),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe33),
.wrNorth(wrProc33North),
.fullNorth(fullProc33North),
.dataOutNorth(dataOutProc33North),
.rdSouth(rdProc33South),
.emptySouth(emptyProc33South),
.dataInSouth(dataInProc33South),
.wrSouth(wrProc33South),
.fullSouth(fullProc33South),
.dataOutSouth(dataOutProc33South),
.rdEast(rdProc33East),
.emptyEast(emptyProc33East),
.dataInEast(dataInProc33East));
//PROCESSOR 34
system proc34(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe34),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe34),
.rdNorth(rdProc34North),
.emptyNorth(emptyProc34North),
.dataInNorth(dataInProc34North),
.wrWest(wrProc34West),
.fullWest(fullProc34West),
.dataOutWest(dataOutProc34West));
//PROCESSOR 35
system proc35(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe35),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe35),
.rdNorth(rdProc35North),
.emptyNorth(emptyProc35North),
.dataInNorth(dataInProc35North),
.wrNorth(wrProc35North),
.fullNorth(fullProc35North),
.dataOutNorth(dataOutProc35North),
.rdSouth(rdProc35South),
.emptySouth(emptyProc35South),
.dataInSouth(dataInProc35South),
.wrEast(wrProc35East),
.fullEast(fullProc35East),
.dataOutEast(dataOutProc35East));
//PROCESSOR 36
system proc36(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe36),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe36),
.rdNorth(rdProc36North),
.emptyNorth(emptyProc36North),
.dataInNorth(dataInProc36North),
.wrSouth(wrProc36South),
.fullSouth(fullProc36South),
.dataOutSouth(dataOutProc36South),
.wrEast(wrProc36East),
.fullEast(fullProc36East),
.dataOutEast(dataOutProc36East),
.rdWest(rdProc36West),
.emptyWest(emptyProc36West),
.dataInWest(dataInProc36West));
//PROCESSOR 37
system proc37(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe37),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe37),
.rdNorth(rdProc37North),
.emptyNorth(emptyProc37North),
.dataInNorth(dataInProc37North),
.wrSouth(wrProc37South),
.fullSouth(fullProc37South),
.dataOutSouth(dataOutProc37South),
.rdWest(rdProc37West),
.emptyWest(emptyProc37West),
.dataInWest(dataInProc37West));
//PROCESSOR 38
system proc38(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe38),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe38),
.rdNorth(rdProc38North),
.emptyNorth(emptyProc38North),
.dataInNorth(dataInProc38North),
.rdSouth(rdProc38South),
.emptySouth(emptyProc38South),
.dataInSouth(dataInProc38South),
.wrSouth(wrProc38South),
.fullSouth(fullProc38South),
.dataOutSouth(dataOutProc38South),
.wrEast(wrProc38East),
.fullEast(fullProc38East),
.dataOutEast(dataOutProc38East));
//PROCESSOR 39
system proc39(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe39),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe39),
.wrNorth(wrProc39North),
.fullNorth(fullProc39North),
.dataOutNorth(dataOutProc39North),
.rdSouth(rdProc39South),
.emptySouth(emptyProc39South),
.dataInSouth(dataInProc39South),
.rdWest(rdProc39West),
.emptyWest(emptyProc39West),
.dataInWest(dataInProc39West));
//PROCESSOR 40
system proc40(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe40),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe40),
.wrNorth(wrProc40North),
.fullNorth(fullProc40North),
.dataOutNorth(dataOutProc40North),
.rdSouth(rdProc40South),
.emptySouth(emptyProc40South),
.dataInSouth(dataInProc40South),
.wrSouth(wrProc40South),
.fullSouth(fullProc40South),
.dataOutSouth(dataOutProc40South),
.rdEast(rdProc40East),
.emptyEast(emptyProc40East),
.dataInEast(dataInProc40East));
//PROCESSOR 41
system proc41(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe41),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe41),
.rdEast(rdProc41East),
.emptyEast(emptyProc41East),
.dataInEast(dataInProc41East),
.wrWest(wrProc41West),
.fullWest(fullProc41West),
.dataOutWest(dataOutProc41West));
//PROCESSOR 42
system proc42(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe42),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe42),
.rdSouth(rdProc42South),
.emptySouth(emptyProc42South),
.dataInSouth(dataInProc42South),
.rdEast(rdProc42East),
.emptyEast(emptyProc42East),
.dataInEast(dataInProc42East),
.wrEast(wrProc42East),
.fullEast(fullProc42East),
.dataOutEast(dataOutProc42East),
.wrWest(wrProc42West),
.fullWest(fullProc42West),
.dataOutWest(dataOutProc42West));
//PROCESSOR 43
system proc43(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe43),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe43),
.rdNorth(rdProc43North),
.emptyNorth(emptyProc43North),
.dataInNorth(dataInProc43North),
.wrNorth(wrProc43North),
.fullNorth(fullProc43North),
.dataOutNorth(dataOutProc43North),
.rdSouth(rdProc43South),
.emptySouth(emptyProc43South),
.dataInSouth(dataInProc43South),
.wrSouth(wrProc43South),
.fullSouth(fullProc43South),
.dataOutSouth(dataOutProc43South),
.wrEast(wrProc43East),
.fullEast(fullProc43East),
.dataOutEast(dataOutProc43East),
.rdWest(rdProc43West),
.emptyWest(emptyProc43West),
.dataInWest(dataInProc43West),
.wrWest(wrProc43West),
.fullWest(fullProc43West),
.dataOutWest(dataOutProc43West));
//PROCESSOR 44
system proc44(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe44),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe44),
.wrEast(wrProc44East),
.fullEast(fullProc44East),
.dataOutEast(dataOutProc44East),
.rdWest(rdProc44West),
.emptyWest(emptyProc44West),
.dataInWest(dataInProc44West));
//PROCESSOR 45
system proc45(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe45),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe45),
.wrNorth(wrProc45North),
.fullNorth(fullProc45North),
.dataOutNorth(dataOutProc45North),
.wrSouth(wrProc45South),
.fullSouth(fullProc45South),
.dataOutSouth(dataOutProc45South),
.rdEast(rdProc45East),
.emptyEast(emptyProc45East),
.dataInEast(dataInProc45East),
.rdWest(rdProc45West),
.emptyWest(emptyProc45West),
.dataInWest(dataInProc45West));
//PROCESSOR 46
system proc46(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe46),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe46),
.rdNorth(rdProc46North),
.emptyNorth(emptyProc46North),
.dataInNorth(dataInProc46North),
.wrSouth(wrProc46South),
.fullSouth(fullProc46South),
.dataOutSouth(dataOutProc46South),
.rdEast(rdProc46East),
.emptyEast(emptyProc46East),
.dataInEast(dataInProc46East),
.wrWest(wrProc46West),
.fullWest(fullProc46West),
.dataOutWest(dataOutProc46West));
//PROCESSOR 47
system proc47(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe47),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe47),
.rdNorth(rdProc47North),
.emptyNorth(emptyProc47North),
.dataInNorth(dataInProc47North),
.wrSouth(wrProc47South),
.fullSouth(fullProc47South),
.dataOutSouth(dataOutProc47South),
.wrWest(wrProc47West),
.fullWest(fullProc47West),
.dataOutWest(dataOutProc47West));
//PROCESSOR 48
system proc48(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe48),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe48),
.rdNorth(rdProc48North),
.emptyNorth(emptyProc48North),
.dataInNorth(dataInProc48North),
.wrNorth(wrProc48North),
.fullNorth(fullProc48North),
.dataOutNorth(dataOutProc48North),
.rdSouth(rdProc48South),
.emptySouth(emptyProc48South),
.dataInSouth(dataInProc48South),
.wrSouth(wrProc48South),
.fullSouth(fullProc48South),
.dataOutSouth(dataOutProc48South));
//PROCESSOR 49
system proc49(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe49),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe49),
.wrNorth(wrProc49North),
.fullNorth(fullProc49North),
.dataOutNorth(dataOutProc49North),
.rdSouth(rdProc49South),
.emptySouth(emptyProc49South),
.dataInSouth(dataInProc49South));
//PROCESSOR 50
system proc50(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe50),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe50),
.rdNorth(rdProc50North),
.emptyNorth(emptyProc50North),
.dataInNorth(dataInProc50North),
.wrNorth(wrProc50North),
.fullNorth(fullProc50North),
.dataOutNorth(dataOutProc50North),
.rdEast(rdProc50East),
.emptyEast(emptyProc50East),
.dataInEast(dataInProc50East),
.wrEast(wrProc50East),
.fullEast(fullProc50East),
.dataOutEast(dataOutProc50East));
//PROCESSOR 51
system proc51(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe51),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe51),
.rdEast(rdProc51East),
.emptyEast(emptyProc51East),
.dataInEast(dataInProc51East),
.wrEast(wrProc51East),
.fullEast(fullProc51East),
.dataOutEast(dataOutProc51East),
.rdWest(rdProc51West),
.emptyWest(emptyProc51West),
.dataInWest(dataInProc51West),
.wrWest(wrProc51West),
.fullWest(fullProc51West),
.dataOutWest(dataOutProc51West));
//PROCESSOR 52
system proc52(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe52),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe52),
.wrNorth(wrProc52North),
.fullNorth(fullProc52North),
.dataOutNorth(dataOutProc52North),
.rdSouth(rdProc52South),
.emptySouth(emptyProc52South),
.dataInSouth(dataInProc52South),
.wrSouth(wrProc52South),
.fullSouth(fullProc52South),
.dataOutSouth(dataOutProc52South),
.rdEast(rdProc52East),
.emptyEast(emptyProc52East),
.dataInEast(dataInProc52East),
.wrEast(wrProc52East),
.fullEast(fullProc52East),
.dataOutEast(dataOutProc52East),
.rdWest(rdProc52West),
.emptyWest(emptyProc52West),
.dataInWest(dataInProc52West),
.wrWest(wrProc52West),
.fullWest(fullProc52West),
.dataOutWest(dataOutProc52West));
//PROCESSOR 53
system proc53(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe53),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe53),
.rdNorth(rdProc53North),
.emptyNorth(emptyProc53North),
.dataInNorth(dataInProc53North),
.wrNorth(wrProc53North),
.fullNorth(fullProc53North),
.dataOutNorth(dataOutProc53North),
.rdSouth(rdProc53South),
.emptySouth(emptyProc53South),
.dataInSouth(dataInProc53South),
.wrSouth(wrProc53South),
.fullSouth(fullProc53South),
.dataOutSouth(dataOutProc53South),
.rdEast(rdProc53East),
.emptyEast(emptyProc53East),
.dataInEast(dataInProc53East),
.rdWest(rdProc53West),
.emptyWest(emptyProc53West),
.dataInWest(dataInProc53West),
.wrWest(wrProc53West),
.fullWest(fullProc53West),
.dataOutWest(dataOutProc53West));
//PROCESSOR 54
system proc54(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe54),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe54),
.rdEast(rdProc54East),
.emptyEast(emptyProc54East),
.dataInEast(dataInProc54East),
.wrWest(wrProc54West),
.fullWest(fullProc54West),
.dataOutWest(dataOutProc54West));
//PROCESSOR 55
system proc55(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe55),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe55),
.rdNorth(rdProc55North),
.emptyNorth(emptyProc55North),
.dataInNorth(dataInProc55North),
.rdEast(rdProc55East),
.emptyEast(emptyProc55East),
.dataInEast(dataInProc55East),
.wrWest(wrProc55West),
.fullWest(fullProc55West),
.dataOutWest(dataOutProc55West));
//PROCESSOR 56
system proc56(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe56),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe56),
.rdNorth(rdProc56North),
.emptyNorth(emptyProc56North),
.dataInNorth(dataInProc56North),
.rdEast(rdProc56East),
.emptyEast(emptyProc56East),
.dataInEast(dataInProc56East),
.wrEast(wrProc56East),
.fullEast(fullProc56East),
.dataOutEast(dataOutProc56East),
.wrWest(wrProc56West),
.fullWest(fullProc56West),
.dataOutWest(dataOutProc56West));
//PROCESSOR 57
system proc57(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe57),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe57),
.rdNorth(rdProc57North),
.emptyNorth(emptyProc57North),
.dataInNorth(dataInProc57North),
.wrSouth(wrProc57South),
.fullSouth(fullProc57South),
.dataOutSouth(dataOutProc57South),
.rdWest(rdProc57West),
.emptyWest(emptyProc57West),
.dataInWest(dataInProc57West),
.wrWest(wrProc57West),
.fullWest(fullProc57West),
.dataOutWest(dataOutProc57West));
//PROCESSOR 58
system proc58(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe58),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe58),
.rdNorth(rdProc58North),
.emptyNorth(emptyProc58North),
.dataInNorth(dataInProc58North),
.wrNorth(wrProc58North),
.fullNorth(fullProc58North),
.dataOutNorth(dataOutProc58North),
.wrSouth(wrProc58South),
.fullSouth(fullProc58South),
.dataOutSouth(dataOutProc58South),
.rdEast(rdProc58East),
.emptyEast(emptyProc58East),
.dataInEast(dataInProc58East));
//PROCESSOR 59
system proc59(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe59),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe59),
.wrNorth(wrProc59North),
.fullNorth(fullProc59North),
.dataOutNorth(dataOutProc59North),
.rdSouth(rdProc59South),
.emptySouth(emptyProc59South),
.dataInSouth(dataInProc59South),
.wrWest(wrProc59West),
.fullWest(fullProc59West),
.dataOutWest(dataOutProc59West));
//PROCESSOR 60
system proc60(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe60),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe60),
.wrSouth(wrProc60South),
.fullSouth(fullProc60South),
.dataOutSouth(dataOutProc60South),
.rdEast(rdProc60East),
.emptyEast(emptyProc60East),
.dataInEast(dataInProc60East));
//PROCESSOR 61
system proc61(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe61),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe61),
.rdSouth(rdProc61South),
.emptySouth(emptyProc61South),
.dataInSouth(dataInProc61South),
.wrEast(wrProc61East),
.fullEast(fullProc61East),
.dataOutEast(dataOutProc61East),
.wrWest(wrProc61West),
.fullWest(fullProc61West),
.dataOutWest(dataOutProc61West));
//PROCESSOR 62
system proc62(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe62),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe62),
.rdNorth(rdProc62North),
.emptyNorth(emptyProc62North),
.dataInNorth(dataInProc62North),
.wrNorth(wrProc62North),
.fullNorth(fullProc62North),
.dataOutNorth(dataOutProc62North),
.rdSouth(rdProc62South),
.emptySouth(emptyProc62South),
.dataInSouth(dataInProc62South),
.wrSouth(wrProc62South),
.fullSouth(fullProc62South),
.dataOutSouth(dataOutProc62South),
.wrEast(wrProc62East),
.fullEast(fullProc62East),
.dataOutEast(dataOutProc62East),
.rdWest(rdProc62West),
.emptyWest(emptyProc62West),
.dataInWest(dataInProc62West));
//PROCESSOR 63
system proc63(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe63),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe63),
.rdNorth(rdProc63North),
.emptyNorth(emptyProc63North),
.dataInNorth(dataInProc63North),
.wrNorth(wrProc63North),
.fullNorth(fullProc63North),
.dataOutNorth(dataOutProc63North),
.rdSouth(rdProc63South),
.emptySouth(emptyProc63South),
.dataInSouth(dataInProc63South),
.wrSouth(wrProc63South),
.fullSouth(fullProc63South),
.dataOutSouth(dataOutProc63South),
.wrEast(wrProc63East),
.fullEast(fullProc63East),
.dataOutEast(dataOutProc63East),
.rdWest(rdProc63West),
.emptyWest(emptyProc63West),
.dataInWest(dataInProc63West));
//PROCESSOR 64
system proc64(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe64),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe64),
.wrSouth(wrProc64South),
.fullSouth(fullProc64South),
.dataOutSouth(dataOutProc64South),
.rdEast(rdProc64East),
.emptyEast(emptyProc64East),
.dataInEast(dataInProc64East),
.wrEast(wrProc64East),
.fullEast(fullProc64East),
.dataOutEast(dataOutProc64East),
.rdWest(rdProc64West),
.emptyWest(emptyProc64West),
.dataInWest(dataInProc64West));
//PROCESSOR 65
system proc65(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe65),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe65),
.rdWest(rdProc65West),
.emptyWest(emptyProc65West),
.dataInWest(dataInProc65West),
.wrWest(wrProc65West),
.fullWest(fullProc65West),
.dataOutWest(dataOutProc65West));
//PROCESSOR 66
system proc66(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe66),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe66),
.rdSouth(rdProc66South),
.emptySouth(emptyProc66South),
.dataInSouth(dataInProc66South),
.wrEast(wrProc66East),
.fullEast(fullProc66East),
.dataOutEast(dataOutProc66East));
//PROCESSOR 67
system proc67(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe67),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe67),
.rdNorth(rdProc67North),
.emptyNorth(emptyProc67North),
.dataInNorth(dataInProc67North),
.wrSouth(wrProc67South),
.fullSouth(fullProc67South),
.dataOutSouth(dataOutProc67South),
.wrEast(wrProc67East),
.fullEast(fullProc67East),
.dataOutEast(dataOutProc67East),
.rdWest(rdProc67West),
.emptyWest(emptyProc67West),
.dataInWest(dataInProc67West));
//PROCESSOR 68
system proc68(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe68),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe68),
.rdNorth(rdProc68North),
.emptyNorth(emptyProc68North),
.dataInNorth(dataInProc68North),
.wrSouth(wrProc68South),
.fullSouth(fullProc68South),
.dataOutSouth(dataOutProc68South),
.wrEast(wrProc68East),
.fullEast(fullProc68East),
.dataOutEast(dataOutProc68East),
.rdWest(rdProc68West),
.emptyWest(emptyProc68West),
.dataInWest(dataInProc68West));
//PROCESSOR 69
system proc69(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe69),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe69),
.wrNorth(wrProc69North),
.fullNorth(fullProc69North),
.dataOutNorth(dataOutProc69North),
.rdSouth(rdProc69South),
.emptySouth(emptyProc69South),
.dataInSouth(dataInProc69South),
.rdWest(rdProc69West),
.emptyWest(emptyProc69West),
.dataInWest(dataInProc69West));
//PROCESSOR 70
system proc70(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe70),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe70),
.rdNorth(rdProc70North),
.emptyNorth(emptyProc70North),
.dataInNorth(dataInProc70North),
.wrSouth(wrProc70South),
.fullSouth(fullProc70South),
.dataOutSouth(dataOutProc70South));
//PROCESSOR 71
system proc71(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe71),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe71),
.wrNorth(wrProc71North),
.fullNorth(fullProc71North),
.dataOutNorth(dataOutProc71North),
.rdSouth(rdProc71South),
.emptySouth(emptyProc71South),
.dataInSouth(dataInProc71South));
//PROCESSOR 72
system proc72(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe72),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe72),
.rdNorth(rdProc72North),
.emptyNorth(emptyProc72North),
.dataInNorth(dataInProc72North),
.wrNorth(wrProc72North),
.fullNorth(fullProc72North),
.dataOutNorth(dataOutProc72North),
.rdEast(rdProc72East),
.emptyEast(emptyProc72East),
.dataInEast(dataInProc72East),
.wrEast(wrProc72East),
.fullEast(fullProc72East),
.dataOutEast(dataOutProc72East));
//PROCESSOR 73
system proc73(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe73),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe73),
.rdNorth(rdProc73North),
.emptyNorth(emptyProc73North),
.dataInNorth(dataInProc73North),
.wrNorth(wrProc73North),
.fullNorth(fullProc73North),
.dataOutNorth(dataOutProc73North),
.wrSouth(wrProc73South),
.fullSouth(fullProc73South),
.dataOutSouth(dataOutProc73South),
.rdEast(rdProc73East),
.emptyEast(emptyProc73East),
.dataInEast(dataInProc73East),
.rdWest(rdProc73West),
.emptyWest(emptyProc73West),
.dataInWest(dataInProc73West),
.wrWest(wrProc73West),
.fullWest(fullProc73West),
.dataOutWest(dataOutProc73West));
//PROCESSOR 74
system proc74(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe74),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe74),
.rdNorth(rdProc74North),
.emptyNorth(emptyProc74North),
.dataInNorth(dataInProc74North),
.rdSouth(rdProc74South),
.emptySouth(emptyProc74South),
.dataInSouth(dataInProc74South),
.wrSouth(wrProc74South),
.fullSouth(fullProc74South),
.dataOutSouth(dataOutProc74South),
.rdEast(rdProc74East),
.emptyEast(emptyProc74East),
.dataInEast(dataInProc74East),
.wrEast(wrProc74East),
.fullEast(fullProc74East),
.dataOutEast(dataOutProc74East),
.wrWest(wrProc74West),
.fullWest(fullProc74West),
.dataOutWest(dataOutProc74West));
//PROCESSOR 75
system proc75(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe75),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe75),
.rdEast(rdProc75East),
.emptyEast(emptyProc75East),
.dataInEast(dataInProc75East),
.wrEast(wrProc75East),
.fullEast(fullProc75East),
.dataOutEast(dataOutProc75East),
.rdWest(rdProc75West),
.emptyWest(emptyProc75West),
.dataInWest(dataInProc75West),
.wrWest(wrProc75West),
.fullWest(fullProc75West),
.dataOutWest(dataOutProc75West));
//PROCESSOR 76
system proc76(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe76),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe76),
.wrNorth(wrProc76North),
.fullNorth(fullProc76North),
.dataOutNorth(dataOutProc76North),
.rdSouth(rdProc76South),
.emptySouth(emptyProc76South),
.dataInSouth(dataInProc76South),
.rdWest(rdProc76West),
.emptyWest(emptyProc76West),
.dataInWest(dataInProc76West),
.wrWest(wrProc76West),
.fullWest(fullProc76West),
.dataOutWest(dataOutProc76West));
//PROCESSOR 77
system proc77(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe77),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe77),
.rdNorth(rdProc77North),
.emptyNorth(emptyProc77North),
.dataInNorth(dataInProc77North),
.wrSouth(wrProc77South),
.fullSouth(fullProc77South),
.dataOutSouth(dataOutProc77South),
.rdEast(rdProc77East),
.emptyEast(emptyProc77East),
.dataInEast(dataInProc77East));
//PROCESSOR 78
system proc78(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe78),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe78),
.rdNorth(rdProc78North),
.emptyNorth(emptyProc78North),
.dataInNorth(dataInProc78North),
.wrWest(wrProc78West),
.fullWest(fullProc78West),
.dataOutWest(dataOutProc78West));
//PROCESSOR 79
system proc79(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe79),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe79),
.wrNorth(wrProc79North),
.fullNorth(fullProc79North),
.dataOutNorth(dataOutProc79North),
.rdSouth(rdProc79South),
.emptySouth(emptyProc79South),
.dataInSouth(dataInProc79South));
//PROCESSOR 80
system proc80(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe80),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe80),
.rdNorth(rdProc80North),
.emptyNorth(emptyProc80North),
.dataInNorth(dataInProc80North),
.wrEast(wrProc80East),
.fullEast(fullProc80East),
.dataOutEast(dataOutProc80East));
//PROCESSOR 81
system proc81(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe81),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe81),
.wrNorth(wrProc81North),
.fullNorth(fullProc81North),
.dataOutNorth(dataOutProc81North),
.rdEast(rdProc81East),
.emptyEast(emptyProc81East),
.dataInEast(dataInProc81East),
.wrEast(wrProc81East),
.fullEast(fullProc81East),
.dataOutEast(dataOutProc81East),
.rdWest(rdProc81West),
.emptyWest(emptyProc81West),
.dataInWest(dataInProc81West));
//PROCESSOR 82
system proc82(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe82),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe82),
.rdEast(rdProc82East),
.emptyEast(emptyProc82East),
.dataInEast(dataInProc82East),
.wrEast(wrProc82East),
.fullEast(fullProc82East),
.dataOutEast(dataOutProc82East),
.rdWest(rdProc82West),
.emptyWest(emptyProc82West),
.dataInWest(dataInProc82West),
.wrWest(wrProc82West),
.fullWest(fullProc82West),
.dataOutWest(dataOutProc82West));
//PROCESSOR 83
system proc83(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe83),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe83),
.rdNorth(rdProc83North),
.emptyNorth(emptyProc83North),
.dataInNorth(dataInProc83North),
.rdEast(rdProc83East),
.emptyEast(emptyProc83East),
.dataInEast(dataInProc83East),
.wrEast(wrProc83East),
.fullEast(fullProc83East),
.dataOutEast(dataOutProc83East),
.rdWest(rdProc83West),
.emptyWest(emptyProc83West),
.dataInWest(dataInProc83West),
.wrWest(wrProc83West),
.fullWest(fullProc83West),
.dataOutWest(dataOutProc83West));
//PROCESSOR 84
system proc84(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe84),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe84),
.rdNorth(rdProc84North),
.emptyNorth(emptyProc84North),
.dataInNorth(dataInProc84North),
.wrNorth(wrProc84North),
.fullNorth(fullProc84North),
.dataOutNorth(dataOutProc84North),
.rdEast(rdProc84East),
.emptyEast(emptyProc84East),
.dataInEast(dataInProc84East),
.wrEast(wrProc84East),
.fullEast(fullProc84East),
.dataOutEast(dataOutProc84East),
.rdWest(rdProc84West),
.emptyWest(emptyProc84West),
.dataInWest(dataInProc84West),
.wrWest(wrProc84West),
.fullWest(fullProc84West),
.dataOutWest(dataOutProc84West));
//PROCESSOR 85
system proc85(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe85),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe85),
.rdWest(rdProc85West),
.emptyWest(emptyProc85West),
.dataInWest(dataInProc85West),
.wrWest(wrProc85West),
.fullWest(fullProc85West),
.dataOutWest(dataOutProc85West));
//PROCESSOR 86
system proc86(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe86),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe86),
.wrNorth(wrProc86North),
.fullNorth(fullProc86North),
.dataOutNorth(dataOutProc86North),
.rdEast(rdProc86East),
.emptyEast(emptyProc86East),
.dataInEast(dataInProc86East));
//PROCESSOR 87
system proc87(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe87),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe87),
.rdNorth(rdProc87North),
.emptyNorth(emptyProc87North),
.dataInNorth(dataInProc87North),
.wrEast(wrProc87East),
.fullEast(fullProc87East),
.dataOutEast(dataOutProc87East),
.wrWest(wrProc87West),
.fullWest(fullProc87West),
.dataOutWest(dataOutProc87West));
//PROCESSOR 88
system proc88(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe88),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe88),
.wrEast(wrProc88East),
.fullEast(fullProc88East),
.dataOutEast(dataOutProc88East),
.rdWest(rdProc88West),
.emptyWest(emptyProc88West),
.dataInWest(dataInProc88West));
//PROCESSOR 89
system proc89(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe89),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe89),
.wrNorth(wrProc89North),
.fullNorth(fullProc89North),
.dataOutNorth(dataOutProc89North),
.rdWest(rdProc89West),
.emptyWest(emptyProc89West),
.dataInWest(dataInProc89West));
//FIFO 0 TO 10
fifo fifo_proc0_to_proc10(
.clk(clk),
.resetn(resetn),
.wr(wrProc0South),
.full(fullProc0South),
.dataIn(dataOutProc0South),
.rd(rdProc10North),
.empty(emptyProc10North),
.dataOut(dataInProc10North));
//FIFO 0 TO 1
fifo fifo_proc0_to_proc1(
.clk(clk),
.resetn(resetn),
.wr(wrProc0East),
.full(fullProc0East),
.dataIn(dataOutProc0East),
.rd(rdProc1West),
.empty(emptyProc1West),
.dataOut(dataInProc1West));
//FIFO 1 TO 11
fifo fifo_proc1_to_proc11(
.clk(clk),
.resetn(resetn),
.wr(wrProc1South),
.full(fullProc1South),
.dataIn(dataOutProc1South),
.rd(rdProc11North),
.empty(emptyProc11North),
.dataOut(dataInProc11North));
//FIFO 14 TO 4
fifo fifo_proc14_to_proc4(
.clk(clk),
.resetn(resetn),
.wr(wrProc14North),
.full(fullProc14North),
.dataIn(dataOutProc14North),
.rd(rdProc4South),
.empty(emptyProc4South),
.dataOut(dataInProc4South));
//FIFO 5 TO 4
fifo fifo_proc5_to_proc4(
.clk(clk),
.resetn(resetn),
.wr(wrProc5West),
.full(fullProc5West),
.dataIn(dataOutProc5West),
.rd(rdProc4East),
.empty(emptyProc4East),
.dataOut(dataInProc4East));
//FIFO 4 TO 5
fifo fifo_proc4_to_proc5(
.clk(clk),
.resetn(resetn),
.wr(wrProc4East),
.full(fullProc4East),
.dataIn(dataOutProc4East),
.rd(rdProc5West),
.empty(emptyProc5West),
.dataOut(dataInProc5West));
//FIFO 6 TO 5
fifo fifo_proc6_to_proc5(
.clk(clk),
.resetn(resetn),
.wr(wrProc6West),
.full(fullProc6West),
.dataIn(dataOutProc6West),
.rd(rdProc5East),
.empty(emptyProc5East),
.dataOut(dataInProc5East));
//FIFO 16 TO 6
fifo fifo_proc16_to_proc6(
.clk(clk),
.resetn(resetn),
.wr(wrProc16North),
.full(fullProc16North),
.dataIn(dataOutProc16North),
.rd(rdProc6South),
.empty(emptyProc6South),
.dataOut(dataInProc6South));
//FIFO 6 TO 16
fifo fifo_proc6_to_proc16(
.clk(clk),
.resetn(resetn),
.wr(wrProc6South),
.full(fullProc6South),
.dataIn(dataOutProc6South),
.rd(rdProc16North),
.empty(emptyProc16North),
.dataOut(dataInProc16North));
//FIFO 7 TO 6
fifo fifo_proc7_to_proc6(
.clk(clk),
.resetn(resetn),
.wr(wrProc7West),
.full(fullProc7West),
.dataIn(dataOutProc7West),
.rd(rdProc6East),
.empty(emptyProc6East),
.dataOut(dataInProc6East));
//FIFO 17 TO 7
fifo fifo_proc17_to_proc7(
.clk(clk),
.resetn(resetn),
.wr(wrProc17North),
.full(fullProc17North),
.dataIn(dataOutProc17North),
.rd(rdProc7South),
.empty(emptyProc7South),
.dataOut(dataInProc7South));
//FIFO 18 TO 8
fifo fifo_proc18_to_proc8(
.clk(clk),
.resetn(resetn),
.wr(wrProc18North),
.full(fullProc18North),
.dataIn(dataOutProc18North),
.rd(rdProc8South),
.empty(emptyProc8South),
.dataOut(dataInProc8South));
//FIFO 8 TO 18
fifo fifo_proc8_to_proc18(
.clk(clk),
.resetn(resetn),
.wr(wrProc8South),
.full(fullProc8South),
.dataIn(dataOutProc8South),
.rd(rdProc18North),
.empty(emptyProc18North),
.dataOut(dataInProc18North));
//FIFO 9 TO 8
fifo fifo_proc9_to_proc8(
.clk(clk),
.resetn(resetn),
.wr(wrProc9West),
.full(fullProc9West),
.dataIn(dataOutProc9West),
.rd(rdProc8East),
.empty(emptyProc8East),
.dataOut(dataInProc8East));
//FIFO 19 TO 9
fifo fifo_proc19_to_proc9(
.clk(clk),
.resetn(resetn),
.wr(wrProc19North),
.full(fullProc19North),
.dataIn(dataOutProc19North),
.rd(rdProc9South),
.empty(emptyProc9South),
.dataOut(dataInProc9South));
//FIFO 10 TO 11
fifo fifo_proc10_to_proc11(
.clk(clk),
.resetn(resetn),
.wr(wrProc10East),
.full(fullProc10East),
.dataIn(dataOutProc10East),
.rd(rdProc11West),
.empty(emptyProc11West),
.dataOut(dataInProc11West));
//FIFO 11 TO 21
fifo fifo_proc11_to_proc21(
.clk(clk),
.resetn(resetn),
.wr(wrProc11South),
.full(fullProc11South),
.dataIn(dataOutProc11South),
.rd(rdProc21North),
.empty(emptyProc21North),
.dataOut(dataInProc21North));
//FIFO 22 TO 12
fifo fifo_proc22_to_proc12(
.clk(clk),
.resetn(resetn),
.wr(wrProc22North),
.full(fullProc22North),
.dataIn(dataOutProc22North),
.rd(rdProc12South),
.empty(emptyProc12South),
.dataOut(dataInProc12South));
//FIFO 12 TO 13
fifo fifo_proc12_to_proc13(
.clk(clk),
.resetn(resetn),
.wr(wrProc12East),
.full(fullProc12East),
.dataIn(dataOutProc12East),
.rd(rdProc13West),
.empty(emptyProc13West),
.dataOut(dataInProc13West));
//FIFO 23 TO 13
fifo fifo_proc23_to_proc13(
.clk(clk),
.resetn(resetn),
.wr(wrProc23North),
.full(fullProc23North),
.dataIn(dataOutProc23North),
.rd(rdProc13South),
.empty(emptyProc13South),
.dataOut(dataInProc13South));
//FIFO 13 TO 14
fifo fifo_proc13_to_proc14(
.clk(clk),
.resetn(resetn),
.wr(wrProc13East),
.full(fullProc13East),
.dataIn(dataOutProc13East),
.rd(rdProc14West),
.empty(emptyProc14West),
.dataOut(dataInProc14West));
//FIFO 24 TO 14
fifo fifo_proc24_to_proc14(
.clk(clk),
.resetn(resetn),
.wr(wrProc24North),
.full(fullProc24North),
.dataIn(dataOutProc24North),
.rd(rdProc14South),
.empty(emptyProc14South),
.dataOut(dataInProc14South));
//FIFO 14 TO 24
fifo fifo_proc14_to_proc24(
.clk(clk),
.resetn(resetn),
.wr(wrProc14South),
.full(fullProc14South),
.dataIn(dataOutProc14South),
.rd(rdProc24North),
.empty(emptyProc24North),
.dataOut(dataInProc24North));
//FIFO 14 TO 15
fifo fifo_proc14_to_proc15(
.clk(clk),
.resetn(resetn),
.wr(wrProc14East),
.full(fullProc14East),
.dataIn(dataOutProc14East),
.rd(rdProc15West),
.empty(emptyProc15West),
.dataOut(dataInProc15West));
//FIFO 15 TO 16
fifo fifo_proc15_to_proc16(
.clk(clk),
.resetn(resetn),
.wr(wrProc15East),
.full(fullProc15East),
.dataIn(dataOutProc15East),
.rd(rdProc16West),
.empty(emptyProc16West),
.dataOut(dataInProc16West));
//FIFO 16 TO 26
fifo fifo_proc16_to_proc26(
.clk(clk),
.resetn(resetn),
.wr(wrProc16South),
.full(fullProc16South),
.dataIn(dataOutProc16South),
.rd(rdProc26North),
.empty(emptyProc26North),
.dataOut(dataInProc26North));
//FIFO 27 TO 17
fifo fifo_proc27_to_proc17(
.clk(clk),
.resetn(resetn),
.wr(wrProc27North),
.full(fullProc27North),
.dataIn(dataOutProc27North),
.rd(rdProc17South),
.empty(emptyProc17South),
.dataOut(dataInProc17South));
//FIFO 18 TO 28
fifo fifo_proc18_to_proc28(
.clk(clk),
.resetn(resetn),
.wr(wrProc18South),
.full(fullProc18South),
.dataIn(dataOutProc18South),
.rd(rdProc28North),
.empty(emptyProc28North),
.dataOut(dataInProc28North));
//FIFO 29 TO 19
fifo fifo_proc29_to_proc19(
.clk(clk),
.resetn(resetn),
.wr(wrProc29North),
.full(fullProc29North),
.dataIn(dataOutProc29North),
.rd(rdProc19South),
.empty(emptyProc19South),
.dataOut(dataInProc19South));
//FIFO 19 TO 29
fifo fifo_proc19_to_proc29(
.clk(clk),
.resetn(resetn),
.wr(wrProc19South),
.full(fullProc19South),
.dataIn(dataOutProc19South),
.rd(rdProc29North),
.empty(emptyProc29North),
.dataOut(dataInProc29North));
//FIFO 30 TO 20
fifo fifo_proc30_to_proc20(
.clk(clk),
.resetn(resetn),
.wr(wrProc30North),
.full(fullProc30North),
.dataIn(dataOutProc30North),
.rd(rdProc20South),
.empty(emptyProc20South),
.dataOut(dataInProc20South));
//FIFO 20 TO 21
fifo fifo_proc20_to_proc21(
.clk(clk),
.resetn(resetn),
.wr(wrProc20East),
.full(fullProc20East),
.dataIn(dataOutProc20East),
.rd(rdProc21West),
.empty(emptyProc21West),
.dataOut(dataInProc21West));
//FIFO 31 TO 21
fifo fifo_proc31_to_proc21(
.clk(clk),
.resetn(resetn),
.wr(wrProc31North),
.full(fullProc31North),
.dataIn(dataOutProc31North),
.rd(rdProc21South),
.empty(emptyProc21South),
.dataOut(dataInProc21South));
//FIFO 21 TO 31
fifo fifo_proc21_to_proc31(
.clk(clk),
.resetn(resetn),
.wr(wrProc21South),
.full(fullProc21South),
.dataIn(dataOutProc21South),
.rd(rdProc31North),
.empty(emptyProc31North),
.dataOut(dataInProc31North));
//FIFO 21 TO 22
fifo fifo_proc21_to_proc22(
.clk(clk),
.resetn(resetn),
.wr(wrProc21East),
.full(fullProc21East),
.dataIn(dataOutProc21East),
.rd(rdProc22West),
.empty(emptyProc22West),
.dataOut(dataInProc22West));
//FIFO 32 TO 22
fifo fifo_proc32_to_proc22(
.clk(clk),
.resetn(resetn),
.wr(wrProc32North),
.full(fullProc32North),
.dataIn(dataOutProc32North),
.rd(rdProc22South),
.empty(emptyProc22South),
.dataOut(dataInProc22South));
//FIFO 22 TO 32
fifo fifo_proc22_to_proc32(
.clk(clk),
.resetn(resetn),
.wr(wrProc22South),
.full(fullProc22South),
.dataIn(dataOutProc22South),
.rd(rdProc32North),
.empty(emptyProc32North),
.dataOut(dataInProc32North));
//FIFO 23 TO 22
fifo fifo_proc23_to_proc22(
.clk(clk),
.resetn(resetn),
.wr(wrProc23West),
.full(fullProc23West),
.dataIn(dataOutProc23West),
.rd(rdProc22East),
.empty(emptyProc22East),
.dataOut(dataInProc22East));
//FIFO 22 TO 23
fifo fifo_proc22_to_proc23(
.clk(clk),
.resetn(resetn),
.wr(wrProc22East),
.full(fullProc22East),
.dataIn(dataOutProc22East),
.rd(rdProc23West),
.empty(emptyProc23West),
.dataOut(dataInProc23West));
//FIFO 33 TO 23
fifo fifo_proc33_to_proc23(
.clk(clk),
.resetn(resetn),
.wr(wrProc33North),
.full(fullProc33North),
.dataIn(dataOutProc33North),
.rd(rdProc23South),
.empty(emptyProc23South),
.dataOut(dataInProc23South));
//FIFO 24 TO 23
fifo fifo_proc24_to_proc23(
.clk(clk),
.resetn(resetn),
.wr(wrProc24West),
.full(fullProc24West),
.dataIn(dataOutProc24West),
.rd(rdProc23East),
.empty(emptyProc23East),
.dataOut(dataInProc23East));
//FIFO 23 TO 24
fifo fifo_proc23_to_proc24(
.clk(clk),
.resetn(resetn),
.wr(wrProc23East),
.full(fullProc23East),
.dataIn(dataOutProc23East),
.rd(rdProc24West),
.empty(emptyProc24West),
.dataOut(dataInProc24West));
//FIFO 24 TO 34
fifo fifo_proc24_to_proc34(
.clk(clk),
.resetn(resetn),
.wr(wrProc24South),
.full(fullProc24South),
.dataIn(dataOutProc24South),
.rd(rdProc34North),
.empty(emptyProc34North),
.dataOut(dataInProc34North));
//FIFO 25 TO 24
fifo fifo_proc25_to_proc24(
.clk(clk),
.resetn(resetn),
.wr(wrProc25West),
.full(fullProc25West),
.dataIn(dataOutProc25West),
.rd(rdProc24East),
.empty(emptyProc24East),
.dataOut(dataInProc24East));
//FIFO 24 TO 25
fifo fifo_proc24_to_proc25(
.clk(clk),
.resetn(resetn),
.wr(wrProc24East),
.full(fullProc24East),
.dataIn(dataOutProc24East),
.rd(rdProc25West),
.empty(emptyProc25West),
.dataOut(dataInProc25West));
//FIFO 35 TO 25
fifo fifo_proc35_to_proc25(
.clk(clk),
.resetn(resetn),
.wr(wrProc35North),
.full(fullProc35North),
.dataIn(dataOutProc35North),
.rd(rdProc25South),
.empty(emptyProc25South),
.dataOut(dataInProc25South));
//FIFO 25 TO 35
fifo fifo_proc25_to_proc35(
.clk(clk),
.resetn(resetn),
.wr(wrProc25South),
.full(fullProc25South),
.dataIn(dataOutProc25South),
.rd(rdProc35North),
.empty(emptyProc35North),
.dataOut(dataInProc35North));
//FIFO 26 TO 25
fifo fifo_proc26_to_proc25(
.clk(clk),
.resetn(resetn),
.wr(wrProc26West),
.full(fullProc26West),
.dataIn(dataOutProc26West),
.rd(rdProc25East),
.empty(emptyProc25East),
.dataOut(dataInProc25East));
//FIFO 25 TO 26
fifo fifo_proc25_to_proc26(
.clk(clk),
.resetn(resetn),
.wr(wrProc25East),
.full(fullProc25East),
.dataIn(dataOutProc25East),
.rd(rdProc26West),
.empty(emptyProc26West),
.dataOut(dataInProc26West));
//FIFO 26 TO 36
fifo fifo_proc26_to_proc36(
.clk(clk),
.resetn(resetn),
.wr(wrProc26South),
.full(fullProc26South),
.dataIn(dataOutProc26South),
.rd(rdProc36North),
.empty(emptyProc36North),
.dataOut(dataInProc36North));
//FIFO 26 TO 27
fifo fifo_proc26_to_proc27(
.clk(clk),
.resetn(resetn),
.wr(wrProc26East),
.full(fullProc26East),
.dataIn(dataOutProc26East),
.rd(rdProc27West),
.empty(emptyProc27West),
.dataOut(dataInProc27West));
//FIFO 27 TO 37
fifo fifo_proc27_to_proc37(
.clk(clk),
.resetn(resetn),
.wr(wrProc27South),
.full(fullProc27South),
.dataIn(dataOutProc27South),
.rd(rdProc37North),
.empty(emptyProc37North),
.dataOut(dataInProc37North));
//FIFO 28 TO 27
fifo fifo_proc28_to_proc27(
.clk(clk),
.resetn(resetn),
.wr(wrProc28West),
.full(fullProc28West),
.dataIn(dataOutProc28West),
.rd(rdProc27East),
.empty(emptyProc27East),
.dataOut(dataInProc27East));
//FIFO 27 TO 28
fifo fifo_proc27_to_proc28(
.clk(clk),
.resetn(resetn),
.wr(wrProc27East),
.full(fullProc27East),
.dataIn(dataOutProc27East),
.rd(rdProc28West),
.empty(emptyProc28West),
.dataOut(dataInProc28West));
//FIFO 28 TO 38
fifo fifo_proc28_to_proc38(
.clk(clk),
.resetn(resetn),
.wr(wrProc28South),
.full(fullProc28South),
.dataIn(dataOutProc28South),
.rd(rdProc38North),
.empty(emptyProc38North),
.dataOut(dataInProc38North));
//FIFO 29 TO 28
fifo fifo_proc29_to_proc28(
.clk(clk),
.resetn(resetn),
.wr(wrProc29West),
.full(fullProc29West),
.dataIn(dataOutProc29West),
.rd(rdProc28East),
.empty(emptyProc28East),
.dataOut(dataInProc28East));
//FIFO 39 TO 29
fifo fifo_proc39_to_proc29(
.clk(clk),
.resetn(resetn),
.wr(wrProc39North),
.full(fullProc39North),
.dataIn(dataOutProc39North),
.rd(rdProc29South),
.empty(emptyProc29South),
.dataOut(dataInProc29South));
//FIFO 40 TO 30
fifo fifo_proc40_to_proc30(
.clk(clk),
.resetn(resetn),
.wr(wrProc40North),
.full(fullProc40North),
.dataIn(dataOutProc40North),
.rd(rdProc30South),
.empty(emptyProc30South),
.dataOut(dataInProc30South));
//FIFO 43 TO 33
fifo fifo_proc43_to_proc33(
.clk(clk),
.resetn(resetn),
.wr(wrProc43North),
.full(fullProc43North),
.dataIn(dataOutProc43North),
.rd(rdProc33South),
.empty(emptyProc33South),
.dataOut(dataInProc33South));
//FIFO 33 TO 43
fifo fifo_proc33_to_proc43(
.clk(clk),
.resetn(resetn),
.wr(wrProc33South),
.full(fullProc33South),
.dataIn(dataOutProc33South),
.rd(rdProc43North),
.empty(emptyProc43North),
.dataOut(dataInProc43North));
//FIFO 34 TO 33
fifo fifo_proc34_to_proc33(
.clk(clk),
.resetn(resetn),
.wr(wrProc34West),
.full(fullProc34West),
.dataIn(dataOutProc34West),
.rd(rdProc33East),
.empty(emptyProc33East),
.dataOut(dataInProc33East));
//FIFO 45 TO 35
fifo fifo_proc45_to_proc35(
.clk(clk),
.resetn(resetn),
.wr(wrProc45North),
.full(fullProc45North),
.dataIn(dataOutProc45North),
.rd(rdProc35South),
.empty(emptyProc35South),
.dataOut(dataInProc35South));
//FIFO 35 TO 36
fifo fifo_proc35_to_proc36(
.clk(clk),
.resetn(resetn),
.wr(wrProc35East),
.full(fullProc35East),
.dataIn(dataOutProc35East),
.rd(rdProc36West),
.empty(emptyProc36West),
.dataOut(dataInProc36West));
//FIFO 36 TO 46
fifo fifo_proc36_to_proc46(
.clk(clk),
.resetn(resetn),
.wr(wrProc36South),
.full(fullProc36South),
.dataIn(dataOutProc36South),
.rd(rdProc46North),
.empty(emptyProc46North),
.dataOut(dataInProc46North));
//FIFO 36 TO 37
fifo fifo_proc36_to_proc37(
.clk(clk),
.resetn(resetn),
.wr(wrProc36East),
.full(fullProc36East),
.dataIn(dataOutProc36East),
.rd(rdProc37West),
.empty(emptyProc37West),
.dataOut(dataInProc37West));
//FIFO 37 TO 47
fifo fifo_proc37_to_proc47(
.clk(clk),
.resetn(resetn),
.wr(wrProc37South),
.full(fullProc37South),
.dataIn(dataOutProc37South),
.rd(rdProc47North),
.empty(emptyProc47North),
.dataOut(dataInProc47North));
//FIFO 48 TO 38
fifo fifo_proc48_to_proc38(
.clk(clk),
.resetn(resetn),
.wr(wrProc48North),
.full(fullProc48North),
.dataIn(dataOutProc48North),
.rd(rdProc38South),
.empty(emptyProc38South),
.dataOut(dataInProc38South));
//FIFO 38 TO 48
fifo fifo_proc38_to_proc48(
.clk(clk),
.resetn(resetn),
.wr(wrProc38South),
.full(fullProc38South),
.dataIn(dataOutProc38South),
.rd(rdProc48North),
.empty(emptyProc48North),
.dataOut(dataInProc48North));
//FIFO 38 TO 39
fifo fifo_proc38_to_proc39(
.clk(clk),
.resetn(resetn),
.wr(wrProc38East),
.full(fullProc38East),
.dataIn(dataOutProc38East),
.rd(rdProc39West),
.empty(emptyProc39West),
.dataOut(dataInProc39West));
//FIFO 49 TO 39
fifo fifo_proc49_to_proc39(
.clk(clk),
.resetn(resetn),
.wr(wrProc49North),
.full(fullProc49North),
.dataIn(dataOutProc49North),
.rd(rdProc39South),
.empty(emptyProc39South),
.dataOut(dataInProc39South));
//FIFO 50 TO 40
fifo fifo_proc50_to_proc40(
.clk(clk),
.resetn(resetn),
.wr(wrProc50North),
.full(fullProc50North),
.dataIn(dataOutProc50North),
.rd(rdProc40South),
.empty(emptyProc40South),
.dataOut(dataInProc40South));
//FIFO 40 TO 50
fifo fifo_proc40_to_proc50(
.clk(clk),
.resetn(resetn),
.wr(wrProc40South),
.full(fullProc40South),
.dataIn(dataOutProc40South),
.rd(rdProc50North),
.empty(emptyProc50North),
.dataOut(dataInProc50North));
//FIFO 41 TO 40
fifo fifo_proc41_to_proc40(
.clk(clk),
.resetn(resetn),
.wr(wrProc41West),
.full(fullProc41West),
.dataIn(dataOutProc41West),
.rd(rdProc40East),
.empty(emptyProc40East),
.dataOut(dataInProc40East));
//FIFO 42 TO 41
fifo fifo_proc42_to_proc41(
.clk(clk),
.resetn(resetn),
.wr(wrProc42West),
.full(fullProc42West),
.dataIn(dataOutProc42West),
.rd(rdProc41East),
.empty(emptyProc41East),
.dataOut(dataInProc41East));
//FIFO 52 TO 42
fifo fifo_proc52_to_proc42(
.clk(clk),
.resetn(resetn),
.wr(wrProc52North),
.full(fullProc52North),
.dataIn(dataOutProc52North),
.rd(rdProc42South),
.empty(emptyProc42South),
.dataOut(dataInProc42South));
//FIFO 43 TO 42
fifo fifo_proc43_to_proc42(
.clk(clk),
.resetn(resetn),
.wr(wrProc43West),
.full(fullProc43West),
.dataIn(dataOutProc43West),
.rd(rdProc42East),
.empty(emptyProc42East),
.dataOut(dataInProc42East));
//FIFO 42 TO 43
fifo fifo_proc42_to_proc43(
.clk(clk),
.resetn(resetn),
.wr(wrProc42East),
.full(fullProc42East),
.dataIn(dataOutProc42East),
.rd(rdProc43West),
.empty(emptyProc43West),
.dataOut(dataInProc43West));
//FIFO 53 TO 43
fifo fifo_proc53_to_proc43(
.clk(clk),
.resetn(resetn),
.wr(wrProc53North),
.full(fullProc53North),
.dataIn(dataOutProc53North),
.rd(rdProc43South),
.empty(emptyProc43South),
.dataOut(dataInProc43South));
//FIFO 43 TO 53
fifo fifo_proc43_to_proc53(
.clk(clk),
.resetn(resetn),
.wr(wrProc43South),
.full(fullProc43South),
.dataIn(dataOutProc43South),
.rd(rdProc53North),
.empty(emptyProc53North),
.dataOut(dataInProc53North));
//FIFO 43 TO 44
fifo fifo_proc43_to_proc44(
.clk(clk),
.resetn(resetn),
.wr(wrProc43East),
.full(fullProc43East),
.dataIn(dataOutProc43East),
.rd(rdProc44West),
.empty(emptyProc44West),
.dataOut(dataInProc44West));
//FIFO 44 TO 45
fifo fifo_proc44_to_proc45(
.clk(clk),
.resetn(resetn),
.wr(wrProc44East),
.full(fullProc44East),
.dataIn(dataOutProc44East),
.rd(rdProc45West),
.empty(emptyProc45West),
.dataOut(dataInProc45West));
//FIFO 45 TO 55
fifo fifo_proc45_to_proc55(
.clk(clk),
.resetn(resetn),
.wr(wrProc45South),
.full(fullProc45South),
.dataIn(dataOutProc45South),
.rd(rdProc55North),
.empty(emptyProc55North),
.dataOut(dataInProc55North));
//FIFO 46 TO 45
fifo fifo_proc46_to_proc45(
.clk(clk),
.resetn(resetn),
.wr(wrProc46West),
.full(fullProc46West),
.dataIn(dataOutProc46West),
.rd(rdProc45East),
.empty(emptyProc45East),
.dataOut(dataInProc45East));
//FIFO 46 TO 56
fifo fifo_proc46_to_proc56(
.clk(clk),
.resetn(resetn),
.wr(wrProc46South),
.full(fullProc46South),
.dataIn(dataOutProc46South),
.rd(rdProc56North),
.empty(emptyProc56North),
.dataOut(dataInProc56North));
//FIFO 47 TO 46
fifo fifo_proc47_to_proc46(
.clk(clk),
.resetn(resetn),
.wr(wrProc47West),
.full(fullProc47West),
.dataIn(dataOutProc47West),
.rd(rdProc46East),
.empty(emptyProc46East),
.dataOut(dataInProc46East));
//FIFO 47 TO 57
fifo fifo_proc47_to_proc57(
.clk(clk),
.resetn(resetn),
.wr(wrProc47South),
.full(fullProc47South),
.dataIn(dataOutProc47South),
.rd(rdProc57North),
.empty(emptyProc57North),
.dataOut(dataInProc57North));
//FIFO 58 TO 48
fifo fifo_proc58_to_proc48(
.clk(clk),
.resetn(resetn),
.wr(wrProc58North),
.full(fullProc58North),
.dataIn(dataOutProc58North),
.rd(rdProc48South),
.empty(emptyProc48South),
.dataOut(dataInProc48South));
//FIFO 48 TO 58
fifo fifo_proc48_to_proc58(
.clk(clk),
.resetn(resetn),
.wr(wrProc48South),
.full(fullProc48South),
.dataIn(dataOutProc48South),
.rd(rdProc58North),
.empty(emptyProc58North),
.dataOut(dataInProc58North));
//FIFO 59 TO 49
fifo fifo_proc59_to_proc49(
.clk(clk),
.resetn(resetn),
.wr(wrProc59North),
.full(fullProc59North),
.dataIn(dataOutProc59North),
.rd(rdProc49South),
.empty(emptyProc49South),
.dataOut(dataInProc49South));
//FIFO 51 TO 50
fifo fifo_proc51_to_proc50(
.clk(clk),
.resetn(resetn),
.wr(wrProc51West),
.full(fullProc51West),
.dataIn(dataOutProc51West),
.rd(rdProc50East),
.empty(emptyProc50East),
.dataOut(dataInProc50East));
//FIFO 50 TO 51
fifo fifo_proc50_to_proc51(
.clk(clk),
.resetn(resetn),
.wr(wrProc50East),
.full(fullProc50East),
.dataIn(dataOutProc50East),
.rd(rdProc51West),
.empty(emptyProc51West),
.dataOut(dataInProc51West));
//FIFO 52 TO 51
fifo fifo_proc52_to_proc51(
.clk(clk),
.resetn(resetn),
.wr(wrProc52West),
.full(fullProc52West),
.dataIn(dataOutProc52West),
.rd(rdProc51East),
.empty(emptyProc51East),
.dataOut(dataInProc51East));
//FIFO 51 TO 52
fifo fifo_proc51_to_proc52(
.clk(clk),
.resetn(resetn),
.wr(wrProc51East),
.full(fullProc51East),
.dataIn(dataOutProc51East),
.rd(rdProc52West),
.empty(emptyProc52West),
.dataOut(dataInProc52West));
//FIFO 62 TO 52
fifo fifo_proc62_to_proc52(
.clk(clk),
.resetn(resetn),
.wr(wrProc62North),
.full(fullProc62North),
.dataIn(dataOutProc62North),
.rd(rdProc52South),
.empty(emptyProc52South),
.dataOut(dataInProc52South));
//FIFO 52 TO 62
fifo fifo_proc52_to_proc62(
.clk(clk),
.resetn(resetn),
.wr(wrProc52South),
.full(fullProc52South),
.dataIn(dataOutProc52South),
.rd(rdProc62North),
.empty(emptyProc62North),
.dataOut(dataInProc62North));
//FIFO 53 TO 52
fifo fifo_proc53_to_proc52(
.clk(clk),
.resetn(resetn),
.wr(wrProc53West),
.full(fullProc53West),
.dataIn(dataOutProc53West),
.rd(rdProc52East),
.empty(emptyProc52East),
.dataOut(dataInProc52East));
//FIFO 52 TO 53
fifo fifo_proc52_to_proc53(
.clk(clk),
.resetn(resetn),
.wr(wrProc52East),
.full(fullProc52East),
.dataIn(dataOutProc52East),
.rd(rdProc53West),
.empty(emptyProc53West),
.dataOut(dataInProc53West));
//FIFO 63 TO 53
fifo fifo_proc63_to_proc53(
.clk(clk),
.resetn(resetn),
.wr(wrProc63North),
.full(fullProc63North),
.dataIn(dataOutProc63North),
.rd(rdProc53South),
.empty(emptyProc53South),
.dataOut(dataInProc53South));
//FIFO 53 TO 63
fifo fifo_proc53_to_proc63(
.clk(clk),
.resetn(resetn),
.wr(wrProc53South),
.full(fullProc53South),
.dataIn(dataOutProc53South),
.rd(rdProc63North),
.empty(emptyProc63North),
.dataOut(dataInProc63North));
//FIFO 54 TO 53
fifo fifo_proc54_to_proc53(
.clk(clk),
.resetn(resetn),
.wr(wrProc54West),
.full(fullProc54West),
.dataIn(dataOutProc54West),
.rd(rdProc53East),
.empty(emptyProc53East),
.dataOut(dataInProc53East));
//FIFO 55 TO 54
fifo fifo_proc55_to_proc54(
.clk(clk),
.resetn(resetn),
.wr(wrProc55West),
.full(fullProc55West),
.dataIn(dataOutProc55West),
.rd(rdProc54East),
.empty(emptyProc54East),
.dataOut(dataInProc54East));
//FIFO 56 TO 55
fifo fifo_proc56_to_proc55(
.clk(clk),
.resetn(resetn),
.wr(wrProc56West),
.full(fullProc56West),
.dataIn(dataOutProc56West),
.rd(rdProc55East),
.empty(emptyProc55East),
.dataOut(dataInProc55East));
//FIFO 57 TO 56
fifo fifo_proc57_to_proc56(
.clk(clk),
.resetn(resetn),
.wr(wrProc57West),
.full(fullProc57West),
.dataIn(dataOutProc57West),
.rd(rdProc56East),
.empty(emptyProc56East),
.dataOut(dataInProc56East));
//FIFO 56 TO 57
fifo fifo_proc56_to_proc57(
.clk(clk),
.resetn(resetn),
.wr(wrProc56East),
.full(fullProc56East),
.dataIn(dataOutProc56East),
.rd(rdProc57West),
.empty(emptyProc57West),
.dataOut(dataInProc57West));
//FIFO 57 TO 67
fifo fifo_proc57_to_proc67(
.clk(clk),
.resetn(resetn),
.wr(wrProc57South),
.full(fullProc57South),
.dataIn(dataOutProc57South),
.rd(rdProc67North),
.empty(emptyProc67North),
.dataOut(dataInProc67North));
//FIFO 58 TO 68
fifo fifo_proc58_to_proc68(
.clk(clk),
.resetn(resetn),
.wr(wrProc58South),
.full(fullProc58South),
.dataIn(dataOutProc58South),
.rd(rdProc68North),
.empty(emptyProc68North),
.dataOut(dataInProc68North));
//FIFO 59 TO 58
fifo fifo_proc59_to_proc58(
.clk(clk),
.resetn(resetn),
.wr(wrProc59West),
.full(fullProc59West),
.dataIn(dataOutProc59West),
.rd(rdProc58East),
.empty(emptyProc58East),
.dataOut(dataInProc58East));
//FIFO 69 TO 59
fifo fifo_proc69_to_proc59(
.clk(clk),
.resetn(resetn),
.wr(wrProc69North),
.full(fullProc69North),
.dataIn(dataOutProc69North),
.rd(rdProc59South),
.empty(emptyProc59South),
.dataOut(dataInProc59South));
//FIFO 60 TO 70
fifo fifo_proc60_to_proc70(
.clk(clk),
.resetn(resetn),
.wr(wrProc60South),
.full(fullProc60South),
.dataIn(dataOutProc60South),
.rd(rdProc70North),
.empty(emptyProc70North),
.dataOut(dataInProc70North));
//FIFO 61 TO 60
fifo fifo_proc61_to_proc60(
.clk(clk),
.resetn(resetn),
.wr(wrProc61West),
.full(fullProc61West),
.dataIn(dataOutProc61West),
.rd(rdProc60East),
.empty(emptyProc60East),
.dataOut(dataInProc60East));
//FIFO 71 TO 61
fifo fifo_proc71_to_proc61(
.clk(clk),
.resetn(resetn),
.wr(wrProc71North),
.full(fullProc71North),
.dataIn(dataOutProc71North),
.rd(rdProc61South),
.empty(emptyProc61South),
.dataOut(dataInProc61South));
//FIFO 61 TO 62
fifo fifo_proc61_to_proc62(
.clk(clk),
.resetn(resetn),
.wr(wrProc61East),
.full(fullProc61East),
.dataIn(dataOutProc61East),
.rd(rdProc62West),
.empty(emptyProc62West),
.dataOut(dataInProc62West));
//FIFO 72 TO 62
fifo fifo_proc72_to_proc62(
.clk(clk),
.resetn(resetn),
.wr(wrProc72North),
.full(fullProc72North),
.dataIn(dataOutProc72North),
.rd(rdProc62South),
.empty(emptyProc62South),
.dataOut(dataInProc62South));
//FIFO 62 TO 72
fifo fifo_proc62_to_proc72(
.clk(clk),
.resetn(resetn),
.wr(wrProc62South),
.full(fullProc62South),
.dataIn(dataOutProc62South),
.rd(rdProc72North),
.empty(emptyProc72North),
.dataOut(dataInProc72North));
//FIFO 62 TO 63
fifo fifo_proc62_to_proc63(
.clk(clk),
.resetn(resetn),
.wr(wrProc62East),
.full(fullProc62East),
.dataIn(dataOutProc62East),
.rd(rdProc63West),
.empty(emptyProc63West),
.dataOut(dataInProc63West));
//FIFO 73 TO 63
fifo fifo_proc73_to_proc63(
.clk(clk),
.resetn(resetn),
.wr(wrProc73North),
.full(fullProc73North),
.dataIn(dataOutProc73North),
.rd(rdProc63South),
.empty(emptyProc63South),
.dataOut(dataInProc63South));
//FIFO 63 TO 73
fifo fifo_proc63_to_proc73(
.clk(clk),
.resetn(resetn),
.wr(wrProc63South),
.full(fullProc63South),
.dataIn(dataOutProc63South),
.rd(rdProc73North),
.empty(emptyProc73North),
.dataOut(dataInProc73North));
//FIFO 63 TO 64
fifo fifo_proc63_to_proc64(
.clk(clk),
.resetn(resetn),
.wr(wrProc63East),
.full(fullProc63East),
.dataIn(dataOutProc63East),
.rd(rdProc64West),
.empty(emptyProc64West),
.dataOut(dataInProc64West));
//FIFO 64 TO 74
fifo fifo_proc64_to_proc74(
.clk(clk),
.resetn(resetn),
.wr(wrProc64South),
.full(fullProc64South),
.dataIn(dataOutProc64South),
.rd(rdProc74North),
.empty(emptyProc74North),
.dataOut(dataInProc74North));
//FIFO 65 TO 64
fifo fifo_proc65_to_proc64(
.clk(clk),
.resetn(resetn),
.wr(wrProc65West),
.full(fullProc65West),
.dataIn(dataOutProc65West),
.rd(rdProc64East),
.empty(emptyProc64East),
.dataOut(dataInProc64East));
//FIFO 64 TO 65
fifo fifo_proc64_to_proc65(
.clk(clk),
.resetn(resetn),
.wr(wrProc64East),
.full(fullProc64East),
.dataIn(dataOutProc64East),
.rd(rdProc65West),
.empty(emptyProc65West),
.dataOut(dataInProc65West));
//FIFO 76 TO 66
fifo fifo_proc76_to_proc66(
.clk(clk),
.resetn(resetn),
.wr(wrProc76North),
.full(fullProc76North),
.dataIn(dataOutProc76North),
.rd(rdProc66South),
.empty(emptyProc66South),
.dataOut(dataInProc66South));
//FIFO 66 TO 67
fifo fifo_proc66_to_proc67(
.clk(clk),
.resetn(resetn),
.wr(wrProc66East),
.full(fullProc66East),
.dataIn(dataOutProc66East),
.rd(rdProc67West),
.empty(emptyProc67West),
.dataOut(dataInProc67West));
//FIFO 67 TO 77
fifo fifo_proc67_to_proc77(
.clk(clk),
.resetn(resetn),
.wr(wrProc67South),
.full(fullProc67South),
.dataIn(dataOutProc67South),
.rd(rdProc77North),
.empty(emptyProc77North),
.dataOut(dataInProc77North));
//FIFO 67 TO 68
fifo fifo_proc67_to_proc68(
.clk(clk),
.resetn(resetn),
.wr(wrProc67East),
.full(fullProc67East),
.dataIn(dataOutProc67East),
.rd(rdProc68West),
.empty(emptyProc68West),
.dataOut(dataInProc68West));
//FIFO 68 TO 78
fifo fifo_proc68_to_proc78(
.clk(clk),
.resetn(resetn),
.wr(wrProc68South),
.full(fullProc68South),
.dataIn(dataOutProc68South),
.rd(rdProc78North),
.empty(emptyProc78North),
.dataOut(dataInProc78North));
//FIFO 68 TO 69
fifo fifo_proc68_to_proc69(
.clk(clk),
.resetn(resetn),
.wr(wrProc68East),
.full(fullProc68East),
.dataIn(dataOutProc68East),
.rd(rdProc69West),
.empty(emptyProc69West),
.dataOut(dataInProc69West));
//FIFO 79 TO 69
fifo fifo_proc79_to_proc69(
.clk(clk),
.resetn(resetn),
.wr(wrProc79North),
.full(fullProc79North),
.dataIn(dataOutProc79North),
.rd(rdProc69South),
.empty(emptyProc69South),
.dataOut(dataInProc69South));
//FIFO 70 TO 80
fifo fifo_proc70_to_proc80(
.clk(clk),
.resetn(resetn),
.wr(wrProc70South),
.full(fullProc70South),
.dataIn(dataOutProc70South),
.rd(rdProc80North),
.empty(emptyProc80North),
.dataOut(dataInProc80North));
//FIFO 81 TO 71
fifo fifo_proc81_to_proc71(
.clk(clk),
.resetn(resetn),
.wr(wrProc81North),
.full(fullProc81North),
.dataIn(dataOutProc81North),
.rd(rdProc71South),
.empty(emptyProc71South),
.dataOut(dataInProc71South));
//FIFO 73 TO 72
fifo fifo_proc73_to_proc72(
.clk(clk),
.resetn(resetn),
.wr(wrProc73West),
.full(fullProc73West),
.dataIn(dataOutProc73West),
.rd(rdProc72East),
.empty(emptyProc72East),
.dataOut(dataInProc72East));
//FIFO 72 TO 73
fifo fifo_proc72_to_proc73(
.clk(clk),
.resetn(resetn),
.wr(wrProc72East),
.full(fullProc72East),
.dataIn(dataOutProc72East),
.rd(rdProc73West),
.empty(emptyProc73West),
.dataOut(dataInProc73West));
//FIFO 73 TO 83
fifo fifo_proc73_to_proc83(
.clk(clk),
.resetn(resetn),
.wr(wrProc73South),
.full(fullProc73South),
.dataIn(dataOutProc73South),
.rd(rdProc83North),
.empty(emptyProc83North),
.dataOut(dataInProc83North));
//FIFO 74 TO 73
fifo fifo_proc74_to_proc73(
.clk(clk),
.resetn(resetn),
.wr(wrProc74West),
.full(fullProc74West),
.dataIn(dataOutProc74West),
.rd(rdProc73East),
.empty(emptyProc73East),
.dataOut(dataInProc73East));
//FIFO 84 TO 74
fifo fifo_proc84_to_proc74(
.clk(clk),
.resetn(resetn),
.wr(wrProc84North),
.full(fullProc84North),
.dataIn(dataOutProc84North),
.rd(rdProc74South),
.empty(emptyProc74South),
.dataOut(dataInProc74South));
//FIFO 74 TO 84
fifo fifo_proc74_to_proc84(
.clk(clk),
.resetn(resetn),
.wr(wrProc74South),
.full(fullProc74South),
.dataIn(dataOutProc74South),
.rd(rdProc84North),
.empty(emptyProc84North),
.dataOut(dataInProc84North));
//FIFO 75 TO 74
fifo fifo_proc75_to_proc74(
.clk(clk),
.resetn(resetn),
.wr(wrProc75West),
.full(fullProc75West),
.dataIn(dataOutProc75West),
.rd(rdProc74East),
.empty(emptyProc74East),
.dataOut(dataInProc74East));
//FIFO 74 TO 75
fifo fifo_proc74_to_proc75(
.clk(clk),
.resetn(resetn),
.wr(wrProc74East),
.full(fullProc74East),
.dataIn(dataOutProc74East),
.rd(rdProc75West),
.empty(emptyProc75West),
.dataOut(dataInProc75West));
//FIFO 76 TO 75
fifo fifo_proc76_to_proc75(
.clk(clk),
.resetn(resetn),
.wr(wrProc76West),
.full(fullProc76West),
.dataIn(dataOutProc76West),
.rd(rdProc75East),
.empty(emptyProc75East),
.dataOut(dataInProc75East));
//FIFO 75 TO 76
fifo fifo_proc75_to_proc76(
.clk(clk),
.resetn(resetn),
.wr(wrProc75East),
.full(fullProc75East),
.dataIn(dataOutProc75East),
.rd(rdProc76West),
.empty(emptyProc76West),
.dataOut(dataInProc76West));
//FIFO 86 TO 76
fifo fifo_proc86_to_proc76(
.clk(clk),
.resetn(resetn),
.wr(wrProc86North),
.full(fullProc86North),
.dataIn(dataOutProc86North),
.rd(rdProc76South),
.empty(emptyProc76South),
.dataOut(dataInProc76South));
//FIFO 77 TO 87
fifo fifo_proc77_to_proc87(
.clk(clk),
.resetn(resetn),
.wr(wrProc77South),
.full(fullProc77South),
.dataIn(dataOutProc77South),
.rd(rdProc87North),
.empty(emptyProc87North),
.dataOut(dataInProc87North));
//FIFO 78 TO 77
fifo fifo_proc78_to_proc77(
.clk(clk),
.resetn(resetn),
.wr(wrProc78West),
.full(fullProc78West),
.dataIn(dataOutProc78West),
.rd(rdProc77East),
.empty(emptyProc77East),
.dataOut(dataInProc77East));
//FIFO 89 TO 79
fifo fifo_proc89_to_proc79(
.clk(clk),
.resetn(resetn),
.wr(wrProc89North),
.full(fullProc89North),
.dataIn(dataOutProc89North),
.rd(rdProc79South),
.empty(emptyProc79South),
.dataOut(dataInProc79South));
//FIFO 80 TO 81
fifo fifo_proc80_to_proc81(
.clk(clk),
.resetn(resetn),
.wr(wrProc80East),
.full(fullProc80East),
.dataIn(dataOutProc80East),
.rd(rdProc81West),
.empty(emptyProc81West),
.dataOut(dataInProc81West));
//FIFO 82 TO 81
fifo fifo_proc82_to_proc81(
.clk(clk),
.resetn(resetn),
.wr(wrProc82West),
.full(fullProc82West),
.dataIn(dataOutProc82West),
.rd(rdProc81East),
.empty(emptyProc81East),
.dataOut(dataInProc81East));
//FIFO 81 TO 82
fifo fifo_proc81_to_proc82(
.clk(clk),
.resetn(resetn),
.wr(wrProc81East),
.full(fullProc81East),
.dataIn(dataOutProc81East),
.rd(rdProc82West),
.empty(emptyProc82West),
.dataOut(dataInProc82West));
//FIFO 83 TO 82
fifo fifo_proc83_to_proc82(
.clk(clk),
.resetn(resetn),
.wr(wrProc83West),
.full(fullProc83West),
.dataIn(dataOutProc83West),
.rd(rdProc82East),
.empty(emptyProc82East),
.dataOut(dataInProc82East));
//FIFO 82 TO 83
fifo fifo_proc82_to_proc83(
.clk(clk),
.resetn(resetn),
.wr(wrProc82East),
.full(fullProc82East),
.dataIn(dataOutProc82East),
.rd(rdProc83West),
.empty(emptyProc83West),
.dataOut(dataInProc83West));
//FIFO 84 TO 83
fifo fifo_proc84_to_proc83(
.clk(clk),
.resetn(resetn),
.wr(wrProc84West),
.full(fullProc84West),
.dataIn(dataOutProc84West),
.rd(rdProc83East),
.empty(emptyProc83East),
.dataOut(dataInProc83East));
//FIFO 83 TO 84
fifo fifo_proc83_to_proc84(
.clk(clk),
.resetn(resetn),
.wr(wrProc83East),
.full(fullProc83East),
.dataIn(dataOutProc83East),
.rd(rdProc84West),
.empty(emptyProc84West),
.dataOut(dataInProc84West));
//FIFO 85 TO 84
fifo fifo_proc85_to_proc84(
.clk(clk),
.resetn(resetn),
.wr(wrProc85West),
.full(fullProc85West),
.dataIn(dataOutProc85West),
.rd(rdProc84East),
.empty(emptyProc84East),
.dataOut(dataInProc84East));
//FIFO 84 TO 85
fifo fifo_proc84_to_proc85(
.clk(clk),
.resetn(resetn),
.wr(wrProc84East),
.full(fullProc84East),
.dataIn(dataOutProc84East),
.rd(rdProc85West),
.empty(emptyProc85West),
.dataOut(dataInProc85West));
//FIFO 87 TO 86
fifo fifo_proc87_to_proc86(
.clk(clk),
.resetn(resetn),
.wr(wrProc87West),
.full(fullProc87West),
.dataIn(dataOutProc87West),
.rd(rdProc86East),
.empty(emptyProc86East),
.dataOut(dataInProc86East));
//FIFO 87 TO 88
fifo fifo_proc87_to_proc88(
.clk(clk),
.resetn(resetn),
.wr(wrProc87East),
.full(fullProc87East),
.dataIn(dataOutProc87East),
.rd(rdProc88West),
.empty(emptyProc88West),
.dataOut(dataInProc88West));
//FIFO 88 TO 89
fifo fifo_proc88_to_proc89(
.clk(clk),
.resetn(resetn),
.wr(wrProc88East),
.full(fullProc88East),
.dataIn(dataOutProc88East),
.rd(rdProc89West),
.empty(emptyProc89West),
.dataOut(dataInProc89West));
/**************** Boot loader ********************/
/*******Boot up each processor one by one*********/
always@(posedge clk)
begin
case(processor_select)
0: begin
boot_iwe0 = ~resetn;
boot_dwe0 = ~resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
boot_iwe50 = resetn;
boot_dwe50 = resetn;
boot_iwe51 = resetn;
boot_dwe51 = resetn;
boot_iwe52 = resetn;
boot_dwe52 = resetn;
boot_iwe53 = resetn;
boot_dwe53 = resetn;
boot_iwe54 = resetn;
boot_dwe54 = resetn;
boot_iwe55 = resetn;
boot_dwe55 = resetn;
boot_iwe56 = resetn;
boot_dwe56 = resetn;
boot_iwe57 = resetn;
boot_dwe57 = resetn;
boot_iwe58 = resetn;
boot_dwe58 = resetn;
boot_iwe59 = resetn;
boot_dwe59 = resetn;
boot_iwe60 = resetn;
boot_dwe60 = resetn;
boot_iwe61 = resetn;
boot_dwe61 = resetn;
boot_iwe62 = resetn;
boot_dwe62 = resetn;
boot_iwe63 = resetn;
boot_dwe63 = resetn;
boot_iwe64 = resetn;
boot_dwe64 = resetn;
boot_iwe65 = resetn;
boot_dwe65 = resetn;
boot_iwe66 = resetn;
boot_dwe66 = resetn;
boot_iwe67 = resetn;
boot_dwe67 = resetn;
boot_iwe68 = resetn;
boot_dwe68 = resetn;
boot_iwe69 = resetn;
boot_dwe69 = resetn;
boot_iwe70 = resetn;
boot_dwe70 = resetn;
boot_iwe71 = resetn;
boot_dwe71 = resetn;
boot_iwe72 = resetn;
boot_dwe72 = resetn;
boot_iwe73 = resetn;
boot_dwe73 = resetn;
boot_iwe74 = resetn;
boot_dwe74 = resetn;
boot_iwe75 = resetn;
boot_dwe75 = resetn;
boot_iwe76 = resetn;
boot_dwe76 = resetn;
boot_iwe77 = resetn;
boot_dwe77 = resetn;
boot_iwe78 = resetn;
boot_dwe78 = resetn;
boot_iwe79 = resetn;
boot_dwe79 = resetn;
boot_iwe80 = resetn;
boot_dwe80 = resetn;
boot_iwe81 = resetn;
boot_dwe81 = resetn;
boot_iwe82 = resetn;
boot_dwe82 = resetn;
boot_iwe83 = resetn;
boot_dwe83 = resetn;
boot_iwe84 = resetn;
boot_dwe84 = resetn;
boot_iwe85 = resetn;
boot_dwe85 = resetn;
boot_iwe86 = resetn;
boot_dwe86 = resetn;
boot_iwe87 = resetn;
boot_dwe87 = resetn;
boot_iwe88 = resetn;
boot_dwe88 = resetn;
boot_iwe89 = resetn;
boot_dwe89 = resetn;
end
1: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = ~resetn;
boot_dwe1 = ~resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
boot_iwe50 = resetn;
boot_dwe50 = resetn;
boot_iwe51 = resetn;
boot_dwe51 = resetn;
boot_iwe52 = resetn;
boot_dwe52 = resetn;
boot_iwe53 = resetn;
boot_dwe53 = resetn;
boot_iwe54 = resetn;
boot_dwe54 = resetn;
boot_iwe55 = resetn;
boot_dwe55 = resetn;
boot_iwe56 = resetn;
boot_dwe56 = resetn;
boot_iwe57 = resetn;
boot_dwe57 = resetn;
boot_iwe58 = resetn;
boot_dwe58 = resetn;
boot_iwe59 = resetn;
boot_dwe59 = resetn;
boot_iwe60 = resetn;
boot_dwe60 = resetn;
boot_iwe61 = resetn;
boot_dwe61 = resetn;
boot_iwe62 = resetn;
boot_dwe62 = resetn;
boot_iwe63 = resetn;
boot_dwe63 = resetn;
boot_iwe64 = resetn;
boot_dwe64 = resetn;
boot_iwe65 = resetn;
boot_dwe65 = resetn;
boot_iwe66 = resetn;
boot_dwe66 = resetn;
boot_iwe67 = resetn;
boot_dwe67 = resetn;
boot_iwe68 = resetn;
boot_dwe68 = resetn;
boot_iwe69 = resetn;
boot_dwe69 = resetn;
boot_iwe70 = resetn;
boot_dwe70 = resetn;
boot_iwe71 = resetn;
boot_dwe71 = resetn;
boot_iwe72 = resetn;
boot_dwe72 = resetn;
boot_iwe73 = resetn;
boot_dwe73 = resetn;
boot_iwe74 = resetn;
boot_dwe74 = resetn;
boot_iwe75 = resetn;
boot_dwe75 = resetn;
boot_iwe76 = resetn;
boot_dwe76 = resetn;
boot_iwe77 = resetn;
boot_dwe77 = resetn;
boot_iwe78 = resetn;
boot_dwe78 = resetn;
boot_iwe79 = resetn;
boot_dwe79 = resetn;
boot_iwe80 = resetn;
boot_dwe80 = resetn;
boot_iwe81 = resetn;
boot_dwe81 = resetn;
boot_iwe82 = resetn;
boot_dwe82 = resetn;
boot_iwe83 = resetn;
boot_dwe83 = resetn;
boot_iwe84 = resetn;
boot_dwe84 = resetn;
boot_iwe85 = resetn;
boot_dwe85 = resetn;
boot_iwe86 = resetn;
boot_dwe86 = resetn;
boot_iwe87 = resetn;
boot_dwe87 = resetn;
boot_iwe88 = resetn;
boot_dwe88 = resetn;
boot_iwe89 = resetn;
boot_dwe89 = resetn;
end
2: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = ~resetn;
boot_dwe2 = ~resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
boot_iwe50 = resetn;
boot_dwe50 = resetn;
boot_iwe51 = resetn;
boot_dwe51 = resetn;
boot_iwe52 = resetn;
boot_dwe52 = resetn;
boot_iwe53 = resetn;
boot_dwe53 = resetn;
boot_iwe54 = resetn;
boot_dwe54 = resetn;
boot_iwe55 = resetn;
boot_dwe55 = resetn;
boot_iwe56 = resetn;
boot_dwe56 = resetn;
boot_iwe57 = resetn;
boot_dwe57 = resetn;
boot_iwe58 = resetn;
boot_dwe58 = resetn;
boot_iwe59 = resetn;
boot_dwe59 = resetn;
boot_iwe60 = resetn;
boot_dwe60 = resetn;
boot_iwe61 = resetn;
boot_dwe61 = resetn;
boot_iwe62 = resetn;
boot_dwe62 = resetn;
boot_iwe63 = resetn;
boot_dwe63 = resetn;
boot_iwe64 = resetn;
boot_dwe64 = resetn;
boot_iwe65 = resetn;
boot_dwe65 = resetn;
boot_iwe66 = resetn;
boot_dwe66 = resetn;
boot_iwe67 = resetn;
boot_dwe67 = resetn;
boot_iwe68 = resetn;
boot_dwe68 = resetn;
boot_iwe69 = resetn;
boot_dwe69 = resetn;
boot_iwe70 = resetn;
boot_dwe70 = resetn;
boot_iwe71 = resetn;
boot_dwe71 = resetn;
boot_iwe72 = resetn;
boot_dwe72 = resetn;
boot_iwe73 = resetn;
boot_dwe73 = resetn;
boot_iwe74 = resetn;
boot_dwe74 = resetn;
boot_iwe75 = resetn;
boot_dwe75 = resetn;
boot_iwe76 = resetn;
boot_dwe76 = resetn;
boot_iwe77 = resetn;
boot_dwe77 = resetn;
boot_iwe78 = resetn;
boot_dwe78 = resetn;
boot_iwe79 = resetn;
boot_dwe79 = resetn;
boot_iwe80 = resetn;
boot_dwe80 = resetn;
boot_iwe81 = resetn;
boot_dwe81 = resetn;
boot_iwe82 = resetn;
boot_dwe82 = resetn;
boot_iwe83 = resetn;
boot_dwe83 = resetn;
boot_iwe84 = resetn;
boot_dwe84 = resetn;
boot_iwe85 = resetn;
boot_dwe85 = resetn;
boot_iwe86 = resetn;
boot_dwe86 = resetn;
boot_iwe87 = resetn;
boot_dwe87 = resetn;
boot_iwe88 = resetn;
boot_dwe88 = resetn;
boot_iwe89 = resetn;
boot_dwe89 = resetn;
end
3: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = ~resetn;
boot_dwe3 = ~resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
boot_iwe50 = resetn;
boot_dwe50 = resetn;
boot_iwe51 = resetn;
boot_dwe51 = resetn;
boot_iwe52 = resetn;
boot_dwe52 = resetn;
boot_iwe53 = resetn;
boot_dwe53 = resetn;
boot_iwe54 = resetn;
boot_dwe54 = resetn;
boot_iwe55 = resetn;
boot_dwe55 = resetn;
boot_iwe56 = resetn;
boot_dwe56 = resetn;
boot_iwe57 = resetn;
boot_dwe57 = resetn;
boot_iwe58 = resetn;
boot_dwe58 = resetn;
boot_iwe59 = resetn;
boot_dwe59 = resetn;
boot_iwe60 = resetn;
boot_dwe60 = resetn;
boot_iwe61 = resetn;
boot_dwe61 = resetn;
boot_iwe62 = resetn;
boot_dwe62 = resetn;
boot_iwe63 = resetn;
boot_dwe63 = resetn;
boot_iwe64 = resetn;
boot_dwe64 = resetn;
boot_iwe65 = resetn;
boot_dwe65 = resetn;
boot_iwe66 = resetn;
boot_dwe66 = resetn;
boot_iwe67 = resetn;
boot_dwe67 = resetn;
boot_iwe68 = resetn;
boot_dwe68 = resetn;
boot_iwe69 = resetn;
boot_dwe69 = resetn;
boot_iwe70 = resetn;
boot_dwe70 = resetn;
boot_iwe71 = resetn;
boot_dwe71 = resetn;
boot_iwe72 = resetn;
boot_dwe72 = resetn;
boot_iwe73 = resetn;
boot_dwe73 = resetn;
boot_iwe74 = resetn;
boot_dwe74 = resetn;
boot_iwe75 = resetn;
boot_dwe75 = resetn;
boot_iwe76 = resetn;
boot_dwe76 = resetn;
boot_iwe77 = resetn;
boot_dwe77 = resetn;
boot_iwe78 = resetn;
boot_dwe78 = resetn;
boot_iwe79 = resetn;
boot_dwe79 = resetn;
boot_iwe80 = resetn;
boot_dwe80 = resetn;
boot_iwe81 = resetn;
boot_dwe81 = resetn;
boot_iwe82 = resetn;
boot_dwe82 = resetn;
boot_iwe83 = resetn;
boot_dwe83 = resetn;
boot_iwe84 = resetn;
boot_dwe84 = resetn;
boot_iwe85 = resetn;
boot_dwe85 = resetn;
boot_iwe86 = resetn;
boot_dwe86 = resetn;
boot_iwe87 = resetn;
boot_dwe87 = resetn;
boot_iwe88 = resetn;
boot_dwe88 = resetn;
boot_iwe89 = resetn;
boot_dwe89 = resetn;
end
4: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = ~resetn;
boot_dwe4 = ~resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
boot_iwe50 = resetn;
boot_dwe50 = resetn;
boot_iwe51 = resetn;
boot_dwe51 = resetn;
boot_iwe52 = resetn;
boot_dwe52 = resetn;
boot_iwe53 = resetn;
boot_dwe53 = resetn;
boot_iwe54 = resetn;
boot_dwe54 = resetn;
boot_iwe55 = resetn;
boot_dwe55 = resetn;
boot_iwe56 = resetn;
boot_dwe56 = resetn;
boot_iwe57 = resetn;
boot_dwe57 = resetn;
boot_iwe58 = resetn;
boot_dwe58 = resetn;
boot_iwe59 = resetn;
boot_dwe59 = resetn;
boot_iwe60 = resetn;
boot_dwe60 = resetn;
boot_iwe61 = resetn;
boot_dwe61 = resetn;
boot_iwe62 = resetn;
boot_dwe62 = resetn;
boot_iwe63 = resetn;
boot_dwe63 = resetn;
boot_iwe64 = resetn;
boot_dwe64 = resetn;
boot_iwe65 = resetn;
boot_dwe65 = resetn;
boot_iwe66 = resetn;
boot_dwe66 = resetn;
boot_iwe67 = resetn;
boot_dwe67 = resetn;
boot_iwe68 = resetn;
boot_dwe68 = resetn;
boot_iwe69 = resetn;
boot_dwe69 = resetn;
boot_iwe70 = resetn;
boot_dwe70 = resetn;
boot_iwe71 = resetn;
boot_dwe71 = resetn;
boot_iwe72 = resetn;
boot_dwe72 = resetn;
boot_iwe73 = resetn;
boot_dwe73 = resetn;
boot_iwe74 = resetn;
boot_dwe74 = resetn;
boot_iwe75 = resetn;
boot_dwe75 = resetn;
boot_iwe76 = resetn;
boot_dwe76 = resetn;
boot_iwe77 = resetn;
boot_dwe77 = resetn;
boot_iwe78 = resetn;
boot_dwe78 = resetn;
boot_iwe79 = resetn;
boot_dwe79 = resetn;
boot_iwe80 = resetn;
boot_dwe80 = resetn;
boot_iwe81 = resetn;
boot_dwe81 = resetn;
boot_iwe82 = resetn;
boot_dwe82 = resetn;
boot_iwe83 = resetn;
boot_dwe83 = resetn;
boot_iwe84 = resetn;
boot_dwe84 = resetn;
boot_iwe85 = resetn;
boot_dwe85 = resetn;
boot_iwe86 = resetn;
boot_dwe86 = resetn;
boot_iwe87 = resetn;
boot_dwe87 = resetn;
boot_iwe88 = resetn;
boot_dwe88 = resetn;
boot_iwe89 = resetn;
boot_dwe89 = resetn;
end
5: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = ~resetn;
boot_dwe5 = ~resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
boot_iwe50 = resetn;
boot_dwe50 = resetn;
boot_iwe51 = resetn;
boot_dwe51 = resetn;
boot_iwe52 = resetn;
boot_dwe52 = resetn;
boot_iwe53 = resetn;
boot_dwe53 = resetn;
boot_iwe54 = resetn;
boot_dwe54 = resetn;
boot_iwe55 = resetn;
boot_dwe55 = resetn;
boot_iwe56 = resetn;
boot_dwe56 = resetn;
boot_iwe57 = resetn;
boot_dwe57 = resetn;
boot_iwe58 = resetn;
boot_dwe58 = resetn;
boot_iwe59 = resetn;
boot_dwe59 = resetn;
boot_iwe60 = resetn;
boot_dwe60 = resetn;
boot_iwe61 = resetn;
boot_dwe61 = resetn;
boot_iwe62 = resetn;
boot_dwe62 = resetn;
boot_iwe63 = resetn;
boot_dwe63 = resetn;
boot_iwe64 = resetn;
boot_dwe64 = resetn;
boot_iwe65 = resetn;
boot_dwe65 = resetn;
boot_iwe66 = resetn;
boot_dwe66 = resetn;
boot_iwe67 = resetn;
boot_dwe67 = resetn;
boot_iwe68 = resetn;
boot_dwe68 = resetn;
boot_iwe69 = resetn;
boot_dwe69 = resetn;
boot_iwe70 = resetn;
boot_dwe70 = resetn;
boot_iwe71 = resetn;
boot_dwe71 = resetn;
boot_iwe72 = resetn;
boot_dwe72 = resetn;
boot_iwe73 = resetn;
boot_dwe73 = resetn;
boot_iwe74 = resetn;
boot_dwe74 = resetn;
boot_iwe75 = resetn;
boot_dwe75 = resetn;
boot_iwe76 = resetn;
boot_dwe76 = resetn;
boot_iwe77 = resetn;
boot_dwe77 = resetn;
boot_iwe78 = resetn;
boot_dwe78 = resetn;
boot_iwe79 = resetn;
boot_dwe79 = resetn;
boot_iwe80 = resetn;
boot_dwe80 = resetn;
boot_iwe81 = resetn;
boot_dwe81 = resetn;
boot_iwe82 = resetn;
boot_dwe82 = resetn;
boot_iwe83 = resetn;
boot_dwe83 = resetn;
boot_iwe84 = resetn;
boot_dwe84 = resetn;
boot_iwe85 = resetn;
boot_dwe85 = resetn;
boot_iwe86 = resetn;
boot_dwe86 = resetn;
boot_iwe87 = resetn;
boot_dwe87 = resetn;
boot_iwe88 = resetn;
boot_dwe88 = resetn;
boot_iwe89 = resetn;
boot_dwe89 = resetn;
end
6: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = ~resetn;
boot_dwe6 = ~resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
boot_iwe50 = resetn;
boot_dwe50 = resetn;
boot_iwe51 = resetn;
boot_dwe51 = resetn;
boot_iwe52 = resetn;
boot_dwe52 = resetn;
boot_iwe53 = resetn;
boot_dwe53 = resetn;
boot_iwe54 = resetn;
boot_dwe54 = resetn;
boot_iwe55 = resetn;
boot_dwe55 = resetn;
boot_iwe56 = resetn;
boot_dwe56 = resetn;
boot_iwe57 = resetn;
boot_dwe57 = resetn;
boot_iwe58 = resetn;
boot_dwe58 = resetn;
boot_iwe59 = resetn;
boot_dwe59 = resetn;
boot_iwe60 = resetn;
boot_dwe60 = resetn;
boot_iwe61 = resetn;
boot_dwe61 = resetn;
boot_iwe62 = resetn;
boot_dwe62 = resetn;
boot_iwe63 = resetn;
boot_dwe63 = resetn;
boot_iwe64 = resetn;
boot_dwe64 = resetn;
boot_iwe65 = resetn;
boot_dwe65 = resetn;
boot_iwe66 = resetn;
boot_dwe66 = resetn;
boot_iwe67 = resetn;
boot_dwe67 = resetn;
boot_iwe68 = resetn;
boot_dwe68 = resetn;
boot_iwe69 = resetn;
boot_dwe69 = resetn;
boot_iwe70 = resetn;
boot_dwe70 = resetn;
boot_iwe71 = resetn;
boot_dwe71 = resetn;
boot_iwe72 = resetn;
boot_dwe72 = resetn;
boot_iwe73 = resetn;
boot_dwe73 = resetn;
boot_iwe74 = resetn;
boot_dwe74 = resetn;
boot_iwe75 = resetn;
boot_dwe75 = resetn;
boot_iwe76 = resetn;
boot_dwe76 = resetn;
boot_iwe77 = resetn;
boot_dwe77 = resetn;
boot_iwe78 = resetn;
boot_dwe78 = resetn;
boot_iwe79 = resetn;
boot_dwe79 = resetn;
boot_iwe80 = resetn;
boot_dwe80 = resetn;
boot_iwe81 = resetn;
boot_dwe81 = resetn;
boot_iwe82 = resetn;
boot_dwe82 = resetn;
boot_iwe83 = resetn;
boot_dwe83 = resetn;
boot_iwe84 = resetn;
boot_dwe84 = resetn;
boot_iwe85 = resetn;
boot_dwe85 = resetn;
boot_iwe86 = resetn;
boot_dwe86 = resetn;
boot_iwe87 = resetn;
boot_dwe87 = resetn;
boot_iwe88 = resetn;
boot_dwe88 = resetn;
boot_iwe89 = resetn;
boot_dwe89 = resetn;
end
7: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = ~resetn;
boot_dwe7 = ~resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
boot_iwe50 = resetn;
boot_dwe50 = resetn;
boot_iwe51 = resetn;
boot_dwe51 = resetn;
boot_iwe52 = resetn;
boot_dwe52 = resetn;
boot_iwe53 = resetn;
boot_dwe53 = resetn;
boot_iwe54 = resetn;
boot_dwe54 = resetn;
boot_iwe55 = resetn;
boot_dwe55 = resetn;
boot_iwe56 = resetn;
boot_dwe56 = resetn;
boot_iwe57 = resetn;
boot_dwe57 = resetn;
boot_iwe58 = resetn;
boot_dwe58 = resetn;
boot_iwe59 = resetn;
boot_dwe59 = resetn;
boot_iwe60 = resetn;
boot_dwe60 = resetn;
boot_iwe61 = resetn;
boot_dwe61 = resetn;
boot_iwe62 = resetn;
boot_dwe62 = resetn;
boot_iwe63 = resetn;
boot_dwe63 = resetn;
boot_iwe64 = resetn;
boot_dwe64 = resetn;
boot_iwe65 = resetn;
boot_dwe65 = resetn;
boot_iwe66 = resetn;
boot_dwe66 = resetn;
boot_iwe67 = resetn;
boot_dwe67 = resetn;
boot_iwe68 = resetn;
boot_dwe68 = resetn;
boot_iwe69 = resetn;
boot_dwe69 = resetn;
boot_iwe70 = resetn;
boot_dwe70 = resetn;
boot_iwe71 = resetn;
boot_dwe71 = resetn;
boot_iwe72 = resetn;
boot_dwe72 = resetn;
boot_iwe73 = resetn;
boot_dwe73 = resetn;
boot_iwe74 = resetn;
boot_dwe74 = resetn;
boot_iwe75 = resetn;
boot_dwe75 = resetn;
boot_iwe76 = resetn;
boot_dwe76 = resetn;
boot_iwe77 = resetn;
boot_dwe77 = resetn;
boot_iwe78 = resetn;
boot_dwe78 = resetn;
boot_iwe79 = resetn;
boot_dwe79 = resetn;
boot_iwe80 = resetn;
boot_dwe80 = resetn;
boot_iwe81 = resetn;
boot_dwe81 = resetn;
boot_iwe82 = resetn;
boot_dwe82 = resetn;
boot_iwe83 = resetn;
boot_dwe83 = resetn;
boot_iwe84 = resetn;
boot_dwe84 = resetn;
boot_iwe85 = resetn;
boot_dwe85 = resetn;
boot_iwe86 = resetn;
boot_dwe86 = resetn;
boot_iwe87 = resetn;
boot_dwe87 = resetn;
boot_iwe88 = resetn;
boot_dwe88 = resetn;
boot_iwe89 = resetn;
boot_dwe89 = resetn;
end
8: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = ~resetn;
boot_dwe8 = ~resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
boot_iwe50 = resetn;
boot_dwe50 = resetn;
boot_iwe51 = resetn;
boot_dwe51 = resetn;
boot_iwe52 = resetn;
boot_dwe52 = resetn;
boot_iwe53 = resetn;
boot_dwe53 = resetn;
boot_iwe54 = resetn;
boot_dwe54 = resetn;
boot_iwe55 = resetn;
boot_dwe55 = resetn;
boot_iwe56 = resetn;
boot_dwe56 = resetn;
boot_iwe57 = resetn;
boot_dwe57 = resetn;
boot_iwe58 = resetn;
boot_dwe58 = resetn;
boot_iwe59 = resetn;
boot_dwe59 = resetn;
boot_iwe60 = resetn;
boot_dwe60 = resetn;
boot_iwe61 = resetn;
boot_dwe61 = resetn;
boot_iwe62 = resetn;
boot_dwe62 = resetn;
boot_iwe63 = resetn;
boot_dwe63 = resetn;
boot_iwe64 = resetn;
boot_dwe64 = resetn;
boot_iwe65 = resetn;
boot_dwe65 = resetn;
boot_iwe66 = resetn;
boot_dwe66 = resetn;
boot_iwe67 = resetn;
boot_dwe67 = resetn;
boot_iwe68 = resetn;
boot_dwe68 = resetn;
boot_iwe69 = resetn;
boot_dwe69 = resetn;
boot_iwe70 = resetn;
boot_dwe70 = resetn;
boot_iwe71 = resetn;
boot_dwe71 = resetn;
boot_iwe72 = resetn;
boot_dwe72 = resetn;
boot_iwe73 = resetn;
boot_dwe73 = resetn;
boot_iwe74 = resetn;
boot_dwe74 = resetn;
boot_iwe75 = resetn;
boot_dwe75 = resetn;
boot_iwe76 = resetn;
boot_dwe76 = resetn;
boot_iwe77 = resetn;
boot_dwe77 = resetn;
boot_iwe78 = resetn;
boot_dwe78 = resetn;
boot_iwe79 = resetn;
boot_dwe79 = resetn;
boot_iwe80 = resetn;
boot_dwe80 = resetn;
boot_iwe81 = resetn;
boot_dwe81 = resetn;
boot_iwe82 = resetn;
boot_dwe82 = resetn;
boot_iwe83 = resetn;
boot_dwe83 = resetn;
boot_iwe84 = resetn;
boot_dwe84 = resetn;
boot_iwe85 = resetn;
boot_dwe85 = resetn;
boot_iwe86 = resetn;
boot_dwe86 = resetn;
boot_iwe87 = resetn;
boot_dwe87 = resetn;
boot_iwe88 = resetn;
boot_dwe88 = resetn;
boot_iwe89 = resetn;
boot_dwe89 = resetn;
end
9: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = ~resetn;
boot_dwe9 = ~resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
boot_iwe50 = resetn;
boot_dwe50 = resetn;
boot_iwe51 = resetn;
boot_dwe51 = resetn;
boot_iwe52 = resetn;
boot_dwe52 = resetn;
boot_iwe53 = resetn;
boot_dwe53 = resetn;
boot_iwe54 = resetn;
boot_dwe54 = resetn;
boot_iwe55 = resetn;
boot_dwe55 = resetn;
boot_iwe56 = resetn;
boot_dwe56 = resetn;
boot_iwe57 = resetn;
boot_dwe57 = resetn;
boot_iwe58 = resetn;
boot_dwe58 = resetn;
boot_iwe59 = resetn;
boot_dwe59 = resetn;
boot_iwe60 = resetn;
boot_dwe60 = resetn;
boot_iwe61 = resetn;
boot_dwe61 = resetn;
boot_iwe62 = resetn;
boot_dwe62 = resetn;
boot_iwe63 = resetn;
boot_dwe63 = resetn;
boot_iwe64 = resetn;
boot_dwe64 = resetn;
boot_iwe65 = resetn;
boot_dwe65 = resetn;
boot_iwe66 = resetn;
boot_dwe66 = resetn;
boot_iwe67 = resetn;
boot_dwe67 = resetn;
boot_iwe68 = resetn;
boot_dwe68 = resetn;
boot_iwe69 = resetn;
boot_dwe69 = resetn;
boot_iwe70 = resetn;
boot_dwe70 = resetn;
boot_iwe71 = resetn;
boot_dwe71 = resetn;
boot_iwe72 = resetn;
boot_dwe72 = resetn;
boot_iwe73 = resetn;
boot_dwe73 = resetn;
boot_iwe74 = resetn;
boot_dwe74 = resetn;
boot_iwe75 = resetn;
boot_dwe75 = resetn;
boot_iwe76 = resetn;
boot_dwe76 = resetn;
boot_iwe77 = resetn;
boot_dwe77 = resetn;
boot_iwe78 = resetn;
boot_dwe78 = resetn;
boot_iwe79 = resetn;
boot_dwe79 = resetn;
boot_iwe80 = resetn;
boot_dwe80 = resetn;
boot_iwe81 = resetn;
boot_dwe81 = resetn;
boot_iwe82 = resetn;
boot_dwe82 = resetn;
boot_iwe83 = resetn;
boot_dwe83 = resetn;
boot_iwe84 = resetn;
boot_dwe84 = resetn;
boot_iwe85 = resetn;
boot_dwe85 = resetn;
boot_iwe86 = resetn;
boot_dwe86 = resetn;
boot_iwe87 = resetn;
boot_dwe87 = resetn;
boot_iwe88 = resetn;
boot_dwe88 = resetn;
boot_iwe89 = resetn;
boot_dwe89 = resetn;
end
10: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = ~resetn;
boot_dwe10 = ~resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
boot_iwe50 = resetn;
boot_dwe50 = resetn;
boot_iwe51 = resetn;
boot_dwe51 = resetn;
boot_iwe52 = resetn;
boot_dwe52 = resetn;
boot_iwe53 = resetn;
boot_dwe53 = resetn;
boot_iwe54 = resetn;
boot_dwe54 = resetn;
boot_iwe55 = resetn;
boot_dwe55 = resetn;
boot_iwe56 = resetn;
boot_dwe56 = resetn;
boot_iwe57 = resetn;
boot_dwe57 = resetn;
boot_iwe58 = resetn;
boot_dwe58 = resetn;
boot_iwe59 = resetn;
boot_dwe59 = resetn;
boot_iwe60 = resetn;
boot_dwe60 = resetn;
boot_iwe61 = resetn;
boot_dwe61 = resetn;
boot_iwe62 = resetn;
boot_dwe62 = resetn;
boot_iwe63 = resetn;
boot_dwe63 = resetn;
boot_iwe64 = resetn;
boot_dwe64 = resetn;
boot_iwe65 = resetn;
boot_dwe65 = resetn;
boot_iwe66 = resetn;
boot_dwe66 = resetn;
boot_iwe67 = resetn;
boot_dwe67 = resetn;
boot_iwe68 = resetn;
boot_dwe68 = resetn;
boot_iwe69 = resetn;
boot_dwe69 = resetn;
boot_iwe70 = resetn;
boot_dwe70 = resetn;
boot_iwe71 = resetn;
boot_dwe71 = resetn;
boot_iwe72 = resetn;
boot_dwe72 = resetn;
boot_iwe73 = resetn;
boot_dwe73 = resetn;
boot_iwe74 = resetn;
boot_dwe74 = resetn;
boot_iwe75 = resetn;
boot_dwe75 = resetn;
boot_iwe76 = resetn;
boot_dwe76 = resetn;
boot_iwe77 = resetn;
boot_dwe77 = resetn;
boot_iwe78 = resetn;
boot_dwe78 = resetn;
boot_iwe79 = resetn;
boot_dwe79 = resetn;
boot_iwe80 = resetn;
boot_dwe80 = resetn;
boot_iwe81 = resetn;
boot_dwe81 = resetn;
boot_iwe82 = resetn;
boot_dwe82 = resetn;
boot_iwe83 = resetn;
boot_dwe83 = resetn;
boot_iwe84 = resetn;
boot_dwe84 = resetn;
boot_iwe85 = resetn;
boot_dwe85 = resetn;
boot_iwe86 = resetn;
boot_dwe86 = resetn;
boot_iwe87 = resetn;
boot_dwe87 = resetn;
boot_iwe88 = resetn;
boot_dwe88 = resetn;
boot_iwe89 = resetn;
boot_dwe89 = resetn;
end
11: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = ~resetn;
boot_dwe11 = ~resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
boot_iwe50 = resetn;
boot_dwe50 = resetn;
boot_iwe51 = resetn;
boot_dwe51 = resetn;
boot_iwe52 = resetn;
boot_dwe52 = resetn;
boot_iwe53 = resetn;
boot_dwe53 = resetn;
boot_iwe54 = resetn;
boot_dwe54 = resetn;
boot_iwe55 = resetn;
boot_dwe55 = resetn;
boot_iwe56 = resetn;
boot_dwe56 = resetn;
boot_iwe57 = resetn;
boot_dwe57 = resetn;
boot_iwe58 = resetn;
boot_dwe58 = resetn;
boot_iwe59 = resetn;
boot_dwe59 = resetn;
boot_iwe60 = resetn;
boot_dwe60 = resetn;
boot_iwe61 = resetn;
boot_dwe61 = resetn;
boot_iwe62 = resetn;
boot_dwe62 = resetn;
boot_iwe63 = resetn;
boot_dwe63 = resetn;
boot_iwe64 = resetn;
boot_dwe64 = resetn;
boot_iwe65 = resetn;
boot_dwe65 = resetn;
boot_iwe66 = resetn;
boot_dwe66 = resetn;
boot_iwe67 = resetn;
boot_dwe67 = resetn;
boot_iwe68 = resetn;
boot_dwe68 = resetn;
boot_iwe69 = resetn;
boot_dwe69 = resetn;
boot_iwe70 = resetn;
boot_dwe70 = resetn;
boot_iwe71 = resetn;
boot_dwe71 = resetn;
boot_iwe72 = resetn;
boot_dwe72 = resetn;
boot_iwe73 = resetn;
boot_dwe73 = resetn;
boot_iwe74 = resetn;
boot_dwe74 = resetn;
boot_iwe75 = resetn;
boot_dwe75 = resetn;
boot_iwe76 = resetn;
boot_dwe76 = resetn;
boot_iwe77 = resetn;
boot_dwe77 = resetn;
boot_iwe78 = resetn;
boot_dwe78 = resetn;
boot_iwe79 = resetn;
boot_dwe79 = resetn;
boot_iwe80 = resetn;
boot_dwe80 = resetn;
boot_iwe81 = resetn;
boot_dwe81 = resetn;
boot_iwe82 = resetn;
boot_dwe82 = resetn;
boot_iwe83 = resetn;
boot_dwe83 = resetn;
boot_iwe84 = resetn;
boot_dwe84 = resetn;
boot_iwe85 = resetn;
boot_dwe85 = resetn;
boot_iwe86 = resetn;
boot_dwe86 = resetn;
boot_iwe87 = resetn;
boot_dwe87 = resetn;
boot_iwe88 = resetn;
boot_dwe88 = resetn;
boot_iwe89 = resetn;
boot_dwe89 = resetn;
end
12: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = ~resetn;
boot_dwe12 = ~resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
boot_iwe50 = resetn;
boot_dwe50 = resetn;
boot_iwe51 = resetn;
boot_dwe51 = resetn;
boot_iwe52 = resetn;
boot_dwe52 = resetn;
boot_iwe53 = resetn;
boot_dwe53 = resetn;
boot_iwe54 = resetn;
boot_dwe54 = resetn;
boot_iwe55 = resetn;
boot_dwe55 = resetn;
boot_iwe56 = resetn;
boot_dwe56 = resetn;
boot_iwe57 = resetn;
boot_dwe57 = resetn;
boot_iwe58 = resetn;
boot_dwe58 = resetn;
boot_iwe59 = resetn;
boot_dwe59 = resetn;
boot_iwe60 = resetn;
boot_dwe60 = resetn;
boot_iwe61 = resetn;
boot_dwe61 = resetn;
boot_iwe62 = resetn;
boot_dwe62 = resetn;
boot_iwe63 = resetn;
boot_dwe63 = resetn;
boot_iwe64 = resetn;
boot_dwe64 = resetn;
boot_iwe65 = resetn;
boot_dwe65 = resetn;
boot_iwe66 = resetn;
boot_dwe66 = resetn;
boot_iwe67 = resetn;
boot_dwe67 = resetn;
boot_iwe68 = resetn;
boot_dwe68 = resetn;
boot_iwe69 = resetn;
boot_dwe69 = resetn;
boot_iwe70 = resetn;
boot_dwe70 = resetn;
boot_iwe71 = resetn;
boot_dwe71 = resetn;
boot_iwe72 = resetn;
boot_dwe72 = resetn;
boot_iwe73 = resetn;
boot_dwe73 = resetn;
boot_iwe74 = resetn;
boot_dwe74 = resetn;
boot_iwe75 = resetn;
boot_dwe75 = resetn;
boot_iwe76 = resetn;
boot_dwe76 = resetn;
boot_iwe77 = resetn;
boot_dwe77 = resetn;
boot_iwe78 = resetn;
boot_dwe78 = resetn;
boot_iwe79 = resetn;
boot_dwe79 = resetn;
boot_iwe80 = resetn;
boot_dwe80 = resetn;
boot_iwe81 = resetn;
boot_dwe81 = resetn;
boot_iwe82 = resetn;
boot_dwe82 = resetn;
boot_iwe83 = resetn;
boot_dwe83 = resetn;
boot_iwe84 = resetn;
boot_dwe84 = resetn;
boot_iwe85 = resetn;
boot_dwe85 = resetn;
boot_iwe86 = resetn;
boot_dwe86 = resetn;
boot_iwe87 = resetn;
boot_dwe87 = resetn;
boot_iwe88 = resetn;
boot_dwe88 = resetn;
boot_iwe89 = resetn;
boot_dwe89 = resetn;
end
13: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = ~resetn;
boot_dwe13 = ~resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
boot_iwe50 = resetn;
boot_dwe50 = resetn;
boot_iwe51 = resetn;
boot_dwe51 = resetn;
boot_iwe52 = resetn;
boot_dwe52 = resetn;
boot_iwe53 = resetn;
boot_dwe53 = resetn;
boot_iwe54 = resetn;
boot_dwe54 = resetn;
boot_iwe55 = resetn;
boot_dwe55 = resetn;
boot_iwe56 = resetn;
boot_dwe56 = resetn;
boot_iwe57 = resetn;
boot_dwe57 = resetn;
boot_iwe58 = resetn;
boot_dwe58 = resetn;
boot_iwe59 = resetn;
boot_dwe59 = resetn;
boot_iwe60 = resetn;
boot_dwe60 = resetn;
boot_iwe61 = resetn;
boot_dwe61 = resetn;
boot_iwe62 = resetn;
boot_dwe62 = resetn;
boot_iwe63 = resetn;
boot_dwe63 = resetn;
boot_iwe64 = resetn;
boot_dwe64 = resetn;
boot_iwe65 = resetn;
boot_dwe65 = resetn;
boot_iwe66 = resetn;
boot_dwe66 = resetn;
boot_iwe67 = resetn;
boot_dwe67 = resetn;
boot_iwe68 = resetn;
boot_dwe68 = resetn;
boot_iwe69 = resetn;
boot_dwe69 = resetn;
boot_iwe70 = resetn;
boot_dwe70 = resetn;
boot_iwe71 = resetn;
boot_dwe71 = resetn;
boot_iwe72 = resetn;
boot_dwe72 = resetn;
boot_iwe73 = resetn;
boot_dwe73 = resetn;
boot_iwe74 = resetn;
boot_dwe74 = resetn;
boot_iwe75 = resetn;
boot_dwe75 = resetn;
boot_iwe76 = resetn;
boot_dwe76 = resetn;
boot_iwe77 = resetn;
boot_dwe77 = resetn;
boot_iwe78 = resetn;
boot_dwe78 = resetn;
boot_iwe79 = resetn;
boot_dwe79 = resetn;
boot_iwe80 = resetn;
boot_dwe80 = resetn;
boot_iwe81 = resetn;
boot_dwe81 = resetn;
boot_iwe82 = resetn;
boot_dwe82 = resetn;
boot_iwe83 = resetn;
boot_dwe83 = resetn;
boot_iwe84 = resetn;
boot_dwe84 = resetn;
boot_iwe85 = resetn;
boot_dwe85 = resetn;
boot_iwe86 = resetn;
boot_dwe86 = resetn;
boot_iwe87 = resetn;
boot_dwe87 = resetn;
boot_iwe88 = resetn;
boot_dwe88 = resetn;
boot_iwe89 = resetn;
boot_dwe89 = resetn;
end
14: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = ~resetn;
boot_dwe14 = ~resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
boot_iwe50 = resetn;
boot_dwe50 = resetn;
boot_iwe51 = resetn;
boot_dwe51 = resetn;
boot_iwe52 = resetn;
boot_dwe52 = resetn;
boot_iwe53 = resetn;
boot_dwe53 = resetn;
boot_iwe54 = resetn;
boot_dwe54 = resetn;
boot_iwe55 = resetn;
boot_dwe55 = resetn;
boot_iwe56 = resetn;
boot_dwe56 = resetn;
boot_iwe57 = resetn;
boot_dwe57 = resetn;
boot_iwe58 = resetn;
boot_dwe58 = resetn;
boot_iwe59 = resetn;
boot_dwe59 = resetn;
boot_iwe60 = resetn;
boot_dwe60 = resetn;
boot_iwe61 = resetn;
boot_dwe61 = resetn;
boot_iwe62 = resetn;
boot_dwe62 = resetn;
boot_iwe63 = resetn;
boot_dwe63 = resetn;
boot_iwe64 = resetn;
boot_dwe64 = resetn;
boot_iwe65 = resetn;
boot_dwe65 = resetn;
boot_iwe66 = resetn;
boot_dwe66 = resetn;
boot_iwe67 = resetn;
boot_dwe67 = resetn;
boot_iwe68 = resetn;
boot_dwe68 = resetn;
boot_iwe69 = resetn;
boot_dwe69 = resetn;
boot_iwe70 = resetn;
boot_dwe70 = resetn;
boot_iwe71 = resetn;
boot_dwe71 = resetn;
boot_iwe72 = resetn;
boot_dwe72 = resetn;
boot_iwe73 = resetn;
boot_dwe73 = resetn;
boot_iwe74 = resetn;
boot_dwe74 = resetn;
boot_iwe75 = resetn;
boot_dwe75 = resetn;
boot_iwe76 = resetn;
boot_dwe76 = resetn;
boot_iwe77 = resetn;
boot_dwe77 = resetn;
boot_iwe78 = resetn;
boot_dwe78 = resetn;
boot_iwe79 = resetn;
boot_dwe79 = resetn;
boot_iwe80 = resetn;
boot_dwe80 = resetn;
boot_iwe81 = resetn;
boot_dwe81 = resetn;
boot_iwe82 = resetn;
boot_dwe82 = resetn;
boot_iwe83 = resetn;
boot_dwe83 = resetn;
boot_iwe84 = resetn;
boot_dwe84 = resetn;
boot_iwe85 = resetn;
boot_dwe85 = resetn;
boot_iwe86 = resetn;
boot_dwe86 = resetn;
boot_iwe87 = resetn;
boot_dwe87 = resetn;
boot_iwe88 = resetn;
boot_dwe88 = resetn;
boot_iwe89 = resetn;
boot_dwe89 = resetn;
end
15: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = ~resetn;
boot_dwe15 = ~resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
boot_iwe50 = resetn;
boot_dwe50 = resetn;
boot_iwe51 = resetn;
boot_dwe51 = resetn;
boot_iwe52 = resetn;
boot_dwe52 = resetn;
boot_iwe53 = resetn;
boot_dwe53 = resetn;
boot_iwe54 = resetn;
boot_dwe54 = resetn;
boot_iwe55 = resetn;
boot_dwe55 = resetn;
boot_iwe56 = resetn;
boot_dwe56 = resetn;
boot_iwe57 = resetn;
boot_dwe57 = resetn;
boot_iwe58 = resetn;
boot_dwe58 = resetn;
boot_iwe59 = resetn;
boot_dwe59 = resetn;
boot_iwe60 = resetn;
boot_dwe60 = resetn;
boot_iwe61 = resetn;
boot_dwe61 = resetn;
boot_iwe62 = resetn;
boot_dwe62 = resetn;
boot_iwe63 = resetn;
boot_dwe63 = resetn;
boot_iwe64 = resetn;
boot_dwe64 = resetn;
boot_iwe65 = resetn;
boot_dwe65 = resetn;
boot_iwe66 = resetn;
boot_dwe66 = resetn;
boot_iwe67 = resetn;
boot_dwe67 = resetn;
boot_iwe68 = resetn;
boot_dwe68 = resetn;
boot_iwe69 = resetn;
boot_dwe69 = resetn;
boot_iwe70 = resetn;
boot_dwe70 = resetn;
boot_iwe71 = resetn;
boot_dwe71 = resetn;
boot_iwe72 = resetn;
boot_dwe72 = resetn;
boot_iwe73 = resetn;
boot_dwe73 = resetn;
boot_iwe74 = resetn;
boot_dwe74 = resetn;
boot_iwe75 = resetn;
boot_dwe75 = resetn;
boot_iwe76 = resetn;
boot_dwe76 = resetn;
boot_iwe77 = resetn;
boot_dwe77 = resetn;
boot_iwe78 = resetn;
boot_dwe78 = resetn;
boot_iwe79 = resetn;
boot_dwe79 = resetn;
boot_iwe80 = resetn;
boot_dwe80 = resetn;
boot_iwe81 = resetn;
boot_dwe81 = resetn;
boot_iwe82 = resetn;
boot_dwe82 = resetn;
boot_iwe83 = resetn;
boot_dwe83 = resetn;
boot_iwe84 = resetn;
boot_dwe84 = resetn;
boot_iwe85 = resetn;
boot_dwe85 = resetn;
boot_iwe86 = resetn;
boot_dwe86 = resetn;
boot_iwe87 = resetn;
boot_dwe87 = resetn;
boot_iwe88 = resetn;
boot_dwe88 = resetn;
boot_iwe89 = resetn;
boot_dwe89 = resetn;
end
16: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = ~resetn;
boot_dwe16 = ~resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
boot_iwe50 = resetn;
boot_dwe50 = resetn;
boot_iwe51 = resetn;
boot_dwe51 = resetn;
boot_iwe52 = resetn;
boot_dwe52 = resetn;
boot_iwe53 = resetn;
boot_dwe53 = resetn;
boot_iwe54 = resetn;
boot_dwe54 = resetn;
boot_iwe55 = resetn;
boot_dwe55 = resetn;
boot_iwe56 = resetn;
boot_dwe56 = resetn;
boot_iwe57 = resetn;
boot_dwe57 = resetn;
boot_iwe58 = resetn;
boot_dwe58 = resetn;
boot_iwe59 = resetn;
boot_dwe59 = resetn;
boot_iwe60 = resetn;
boot_dwe60 = resetn;
boot_iwe61 = resetn;
boot_dwe61 = resetn;
boot_iwe62 = resetn;
boot_dwe62 = resetn;
boot_iwe63 = resetn;
boot_dwe63 = resetn;
boot_iwe64 = resetn;
boot_dwe64 = resetn;
boot_iwe65 = resetn;
boot_dwe65 = resetn;
boot_iwe66 = resetn;
boot_dwe66 = resetn;
boot_iwe67 = resetn;
boot_dwe67 = resetn;
boot_iwe68 = resetn;
boot_dwe68 = resetn;
boot_iwe69 = resetn;
boot_dwe69 = resetn;
boot_iwe70 = resetn;
boot_dwe70 = resetn;
boot_iwe71 = resetn;
boot_dwe71 = resetn;
boot_iwe72 = resetn;
boot_dwe72 = resetn;
boot_iwe73 = resetn;
boot_dwe73 = resetn;
boot_iwe74 = resetn;
boot_dwe74 = resetn;
boot_iwe75 = resetn;
boot_dwe75 = resetn;
boot_iwe76 = resetn;
boot_dwe76 = resetn;
boot_iwe77 = resetn;
boot_dwe77 = resetn;
boot_iwe78 = resetn;
boot_dwe78 = resetn;
boot_iwe79 = resetn;
boot_dwe79 = resetn;
boot_iwe80 = resetn;
boot_dwe80 = resetn;
boot_iwe81 = resetn;
boot_dwe81 = resetn;
boot_iwe82 = resetn;
boot_dwe82 = resetn;
boot_iwe83 = resetn;
boot_dwe83 = resetn;
boot_iwe84 = resetn;
boot_dwe84 = resetn;
boot_iwe85 = resetn;
boot_dwe85 = resetn;
boot_iwe86 = resetn;
boot_dwe86 = resetn;
boot_iwe87 = resetn;
boot_dwe87 = resetn;
boot_iwe88 = resetn;
boot_dwe88 = resetn;
boot_iwe89 = resetn;
boot_dwe89 = resetn;
end
17: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = ~resetn;
boot_dwe17 = ~resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
boot_iwe50 = resetn;
boot_dwe50 = resetn;
boot_iwe51 = resetn;
boot_dwe51 = resetn;
boot_iwe52 = resetn;
boot_dwe52 = resetn;
boot_iwe53 = resetn;
boot_dwe53 = resetn;
boot_iwe54 = resetn;
boot_dwe54 = resetn;
boot_iwe55 = resetn;
boot_dwe55 = resetn;
boot_iwe56 = resetn;
boot_dwe56 = resetn;
boot_iwe57 = resetn;
boot_dwe57 = resetn;
boot_iwe58 = resetn;
boot_dwe58 = resetn;
boot_iwe59 = resetn;
boot_dwe59 = resetn;
boot_iwe60 = resetn;
boot_dwe60 = resetn;
boot_iwe61 = resetn;
boot_dwe61 = resetn;
boot_iwe62 = resetn;
boot_dwe62 = resetn;
boot_iwe63 = resetn;
boot_dwe63 = resetn;
boot_iwe64 = resetn;
boot_dwe64 = resetn;
boot_iwe65 = resetn;
boot_dwe65 = resetn;
boot_iwe66 = resetn;
boot_dwe66 = resetn;
boot_iwe67 = resetn;
boot_dwe67 = resetn;
boot_iwe68 = resetn;
boot_dwe68 = resetn;
boot_iwe69 = resetn;
boot_dwe69 = resetn;
boot_iwe70 = resetn;
boot_dwe70 = resetn;
boot_iwe71 = resetn;
boot_dwe71 = resetn;
boot_iwe72 = resetn;
boot_dwe72 = resetn;
boot_iwe73 = resetn;
boot_dwe73 = resetn;
boot_iwe74 = resetn;
boot_dwe74 = resetn;
boot_iwe75 = resetn;
boot_dwe75 = resetn;
boot_iwe76 = resetn;
boot_dwe76 = resetn;
boot_iwe77 = resetn;
boot_dwe77 = resetn;
boot_iwe78 = resetn;
boot_dwe78 = resetn;
boot_iwe79 = resetn;
boot_dwe79 = resetn;
boot_iwe80 = resetn;
boot_dwe80 = resetn;
boot_iwe81 = resetn;
boot_dwe81 = resetn;
boot_iwe82 = resetn;
boot_dwe82 = resetn;
boot_iwe83 = resetn;
boot_dwe83 = resetn;
boot_iwe84 = resetn;
boot_dwe84 = resetn;
boot_iwe85 = resetn;
boot_dwe85 = resetn;
boot_iwe86 = resetn;
boot_dwe86 = resetn;
boot_iwe87 = resetn;
boot_dwe87 = resetn;
boot_iwe88 = resetn;
boot_dwe88 = resetn;
boot_iwe89 = resetn;
boot_dwe89 = resetn;
end
18: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = ~resetn;
boot_dwe18 = ~resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
boot_iwe50 = resetn;
boot_dwe50 = resetn;
boot_iwe51 = resetn;
boot_dwe51 = resetn;
boot_iwe52 = resetn;
boot_dwe52 = resetn;
boot_iwe53 = resetn;
boot_dwe53 = resetn;
boot_iwe54 = resetn;
boot_dwe54 = resetn;
boot_iwe55 = resetn;
boot_dwe55 = resetn;
boot_iwe56 = resetn;
boot_dwe56 = resetn;
boot_iwe57 = resetn;
boot_dwe57 = resetn;
boot_iwe58 = resetn;
boot_dwe58 = resetn;
boot_iwe59 = resetn;
boot_dwe59 = resetn;
boot_iwe60 = resetn;
boot_dwe60 = resetn;
boot_iwe61 = resetn;
boot_dwe61 = resetn;
boot_iwe62 = resetn;
boot_dwe62 = resetn;
boot_iwe63 = resetn;
boot_dwe63 = resetn;
boot_iwe64 = resetn;
boot_dwe64 = resetn;
boot_iwe65 = resetn;
boot_dwe65 = resetn;
boot_iwe66 = resetn;
boot_dwe66 = resetn;
boot_iwe67 = resetn;
boot_dwe67 = resetn;
boot_iwe68 = resetn;
boot_dwe68 = resetn;
boot_iwe69 = resetn;
boot_dwe69 = resetn;
boot_iwe70 = resetn;
boot_dwe70 = resetn;
boot_iwe71 = resetn;
boot_dwe71 = resetn;
boot_iwe72 = resetn;
boot_dwe72 = resetn;
boot_iwe73 = resetn;
boot_dwe73 = resetn;
boot_iwe74 = resetn;
boot_dwe74 = resetn;
boot_iwe75 = resetn;
boot_dwe75 = resetn;
boot_iwe76 = resetn;
boot_dwe76 = resetn;
boot_iwe77 = resetn;
boot_dwe77 = resetn;
boot_iwe78 = resetn;
boot_dwe78 = resetn;
boot_iwe79 = resetn;
boot_dwe79 = resetn;
boot_iwe80 = resetn;
boot_dwe80 = resetn;
boot_iwe81 = resetn;
boot_dwe81 = resetn;
boot_iwe82 = resetn;
boot_dwe82 = resetn;
boot_iwe83 = resetn;
boot_dwe83 = resetn;
boot_iwe84 = resetn;
boot_dwe84 = resetn;
boot_iwe85 = resetn;
boot_dwe85 = resetn;
boot_iwe86 = resetn;
boot_dwe86 = resetn;
boot_iwe87 = resetn;
boot_dwe87 = resetn;
boot_iwe88 = resetn;
boot_dwe88 = resetn;
boot_iwe89 = resetn;
boot_dwe89 = resetn;
end
19: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = ~resetn;
boot_dwe19 = ~resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
boot_iwe50 = resetn;
boot_dwe50 = resetn;
boot_iwe51 = resetn;
boot_dwe51 = resetn;
boot_iwe52 = resetn;
boot_dwe52 = resetn;
boot_iwe53 = resetn;
boot_dwe53 = resetn;
boot_iwe54 = resetn;
boot_dwe54 = resetn;
boot_iwe55 = resetn;
boot_dwe55 = resetn;
boot_iwe56 = resetn;
boot_dwe56 = resetn;
boot_iwe57 = resetn;
boot_dwe57 = resetn;
boot_iwe58 = resetn;
boot_dwe58 = resetn;
boot_iwe59 = resetn;
boot_dwe59 = resetn;
boot_iwe60 = resetn;
boot_dwe60 = resetn;
boot_iwe61 = resetn;
boot_dwe61 = resetn;
boot_iwe62 = resetn;
boot_dwe62 = resetn;
boot_iwe63 = resetn;
boot_dwe63 = resetn;
boot_iwe64 = resetn;
boot_dwe64 = resetn;
boot_iwe65 = resetn;
boot_dwe65 = resetn;
boot_iwe66 = resetn;
boot_dwe66 = resetn;
boot_iwe67 = resetn;
boot_dwe67 = resetn;
boot_iwe68 = resetn;
boot_dwe68 = resetn;
boot_iwe69 = resetn;
boot_dwe69 = resetn;
boot_iwe70 = resetn;
boot_dwe70 = resetn;
boot_iwe71 = resetn;
boot_dwe71 = resetn;
boot_iwe72 = resetn;
boot_dwe72 = resetn;
boot_iwe73 = resetn;
boot_dwe73 = resetn;
boot_iwe74 = resetn;
boot_dwe74 = resetn;
boot_iwe75 = resetn;
boot_dwe75 = resetn;
boot_iwe76 = resetn;
boot_dwe76 = resetn;
boot_iwe77 = resetn;
boot_dwe77 = resetn;
boot_iwe78 = resetn;
boot_dwe78 = resetn;
boot_iwe79 = resetn;
boot_dwe79 = resetn;
boot_iwe80 = resetn;
boot_dwe80 = resetn;
boot_iwe81 = resetn;
boot_dwe81 = resetn;
boot_iwe82 = resetn;
boot_dwe82 = resetn;
boot_iwe83 = resetn;
boot_dwe83 = resetn;
boot_iwe84 = resetn;
boot_dwe84 = resetn;
boot_iwe85 = resetn;
boot_dwe85 = resetn;
boot_iwe86 = resetn;
boot_dwe86 = resetn;
boot_iwe87 = resetn;
boot_dwe87 = resetn;
boot_iwe88 = resetn;
boot_dwe88 = resetn;
boot_iwe89 = resetn;
boot_dwe89 = resetn;
end
20: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = ~resetn;
boot_dwe20 = ~resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
boot_iwe50 = resetn;
boot_dwe50 = resetn;
boot_iwe51 = resetn;
boot_dwe51 = resetn;
boot_iwe52 = resetn;
boot_dwe52 = resetn;
boot_iwe53 = resetn;
boot_dwe53 = resetn;
boot_iwe54 = resetn;
boot_dwe54 = resetn;
boot_iwe55 = resetn;
boot_dwe55 = resetn;
boot_iwe56 = resetn;
boot_dwe56 = resetn;
boot_iwe57 = resetn;
boot_dwe57 = resetn;
boot_iwe58 = resetn;
boot_dwe58 = resetn;
boot_iwe59 = resetn;
boot_dwe59 = resetn;
boot_iwe60 = resetn;
boot_dwe60 = resetn;
boot_iwe61 = resetn;
boot_dwe61 = resetn;
boot_iwe62 = resetn;
boot_dwe62 = resetn;
boot_iwe63 = resetn;
boot_dwe63 = resetn;
boot_iwe64 = resetn;
boot_dwe64 = resetn;
boot_iwe65 = resetn;
boot_dwe65 = resetn;
boot_iwe66 = resetn;
boot_dwe66 = resetn;
boot_iwe67 = resetn;
boot_dwe67 = resetn;
boot_iwe68 = resetn;
boot_dwe68 = resetn;
boot_iwe69 = resetn;
boot_dwe69 = resetn;
boot_iwe70 = resetn;
boot_dwe70 = resetn;
boot_iwe71 = resetn;
boot_dwe71 = resetn;
boot_iwe72 = resetn;
boot_dwe72 = resetn;
boot_iwe73 = resetn;
boot_dwe73 = resetn;
boot_iwe74 = resetn;
boot_dwe74 = resetn;
boot_iwe75 = resetn;
boot_dwe75 = resetn;
boot_iwe76 = resetn;
boot_dwe76 = resetn;
boot_iwe77 = resetn;
boot_dwe77 = resetn;
boot_iwe78 = resetn;
boot_dwe78 = resetn;
boot_iwe79 = resetn;
boot_dwe79 = resetn;
boot_iwe80 = resetn;
boot_dwe80 = resetn;
boot_iwe81 = resetn;
boot_dwe81 = resetn;
boot_iwe82 = resetn;
boot_dwe82 = resetn;
boot_iwe83 = resetn;
boot_dwe83 = resetn;
boot_iwe84 = resetn;
boot_dwe84 = resetn;
boot_iwe85 = resetn;
boot_dwe85 = resetn;
boot_iwe86 = resetn;
boot_dwe86 = resetn;
boot_iwe87 = resetn;
boot_dwe87 = resetn;
boot_iwe88 = resetn;
boot_dwe88 = resetn;
boot_iwe89 = resetn;
boot_dwe89 = resetn;
end
21: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = ~resetn;
boot_dwe21 = ~resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
boot_iwe50 = resetn;
boot_dwe50 = resetn;
boot_iwe51 = resetn;
boot_dwe51 = resetn;
boot_iwe52 = resetn;
boot_dwe52 = resetn;
boot_iwe53 = resetn;
boot_dwe53 = resetn;
boot_iwe54 = resetn;
boot_dwe54 = resetn;
boot_iwe55 = resetn;
boot_dwe55 = resetn;
boot_iwe56 = resetn;
boot_dwe56 = resetn;
boot_iwe57 = resetn;
boot_dwe57 = resetn;
boot_iwe58 = resetn;
boot_dwe58 = resetn;
boot_iwe59 = resetn;
boot_dwe59 = resetn;
boot_iwe60 = resetn;
boot_dwe60 = resetn;
boot_iwe61 = resetn;
boot_dwe61 = resetn;
boot_iwe62 = resetn;
boot_dwe62 = resetn;
boot_iwe63 = resetn;
boot_dwe63 = resetn;
boot_iwe64 = resetn;
boot_dwe64 = resetn;
boot_iwe65 = resetn;
boot_dwe65 = resetn;
boot_iwe66 = resetn;
boot_dwe66 = resetn;
boot_iwe67 = resetn;
boot_dwe67 = resetn;
boot_iwe68 = resetn;
boot_dwe68 = resetn;
boot_iwe69 = resetn;
boot_dwe69 = resetn;
boot_iwe70 = resetn;
boot_dwe70 = resetn;
boot_iwe71 = resetn;
boot_dwe71 = resetn;
boot_iwe72 = resetn;
boot_dwe72 = resetn;
boot_iwe73 = resetn;
boot_dwe73 = resetn;
boot_iwe74 = resetn;
boot_dwe74 = resetn;
boot_iwe75 = resetn;
boot_dwe75 = resetn;
boot_iwe76 = resetn;
boot_dwe76 = resetn;
boot_iwe77 = resetn;
boot_dwe77 = resetn;
boot_iwe78 = resetn;
boot_dwe78 = resetn;
boot_iwe79 = resetn;
boot_dwe79 = resetn;
boot_iwe80 = resetn;
boot_dwe80 = resetn;
boot_iwe81 = resetn;
boot_dwe81 = resetn;
boot_iwe82 = resetn;
boot_dwe82 = resetn;
boot_iwe83 = resetn;
boot_dwe83 = resetn;
boot_iwe84 = resetn;
boot_dwe84 = resetn;
boot_iwe85 = resetn;
boot_dwe85 = resetn;
boot_iwe86 = resetn;
boot_dwe86 = resetn;
boot_iwe87 = resetn;
boot_dwe87 = resetn;
boot_iwe88 = resetn;
boot_dwe88 = resetn;
boot_iwe89 = resetn;
boot_dwe89 = resetn;
end
22: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = ~resetn;
boot_dwe22 = ~resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
boot_iwe50 = resetn;
boot_dwe50 = resetn;
boot_iwe51 = resetn;
boot_dwe51 = resetn;
boot_iwe52 = resetn;
boot_dwe52 = resetn;
boot_iwe53 = resetn;
boot_dwe53 = resetn;
boot_iwe54 = resetn;
boot_dwe54 = resetn;
boot_iwe55 = resetn;
boot_dwe55 = resetn;
boot_iwe56 = resetn;
boot_dwe56 = resetn;
boot_iwe57 = resetn;
boot_dwe57 = resetn;
boot_iwe58 = resetn;
boot_dwe58 = resetn;
boot_iwe59 = resetn;
boot_dwe59 = resetn;
boot_iwe60 = resetn;
boot_dwe60 = resetn;
boot_iwe61 = resetn;
boot_dwe61 = resetn;
boot_iwe62 = resetn;
boot_dwe62 = resetn;
boot_iwe63 = resetn;
boot_dwe63 = resetn;
boot_iwe64 = resetn;
boot_dwe64 = resetn;
boot_iwe65 = resetn;
boot_dwe65 = resetn;
boot_iwe66 = resetn;
boot_dwe66 = resetn;
boot_iwe67 = resetn;
boot_dwe67 = resetn;
boot_iwe68 = resetn;
boot_dwe68 = resetn;
boot_iwe69 = resetn;
boot_dwe69 = resetn;
boot_iwe70 = resetn;
boot_dwe70 = resetn;
boot_iwe71 = resetn;
boot_dwe71 = resetn;
boot_iwe72 = resetn;
boot_dwe72 = resetn;
boot_iwe73 = resetn;
boot_dwe73 = resetn;
boot_iwe74 = resetn;
boot_dwe74 = resetn;
boot_iwe75 = resetn;
boot_dwe75 = resetn;
boot_iwe76 = resetn;
boot_dwe76 = resetn;
boot_iwe77 = resetn;
boot_dwe77 = resetn;
boot_iwe78 = resetn;
boot_dwe78 = resetn;
boot_iwe79 = resetn;
boot_dwe79 = resetn;
boot_iwe80 = resetn;
boot_dwe80 = resetn;
boot_iwe81 = resetn;
boot_dwe81 = resetn;
boot_iwe82 = resetn;
boot_dwe82 = resetn;
boot_iwe83 = resetn;
boot_dwe83 = resetn;
boot_iwe84 = resetn;
boot_dwe84 = resetn;
boot_iwe85 = resetn;
boot_dwe85 = resetn;
boot_iwe86 = resetn;
boot_dwe86 = resetn;
boot_iwe87 = resetn;
boot_dwe87 = resetn;
boot_iwe88 = resetn;
boot_dwe88 = resetn;
boot_iwe89 = resetn;
boot_dwe89 = resetn;
end
23: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = ~resetn;
boot_dwe23 = ~resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
boot_iwe50 = resetn;
boot_dwe50 = resetn;
boot_iwe51 = resetn;
boot_dwe51 = resetn;
boot_iwe52 = resetn;
boot_dwe52 = resetn;
boot_iwe53 = resetn;
boot_dwe53 = resetn;
boot_iwe54 = resetn;
boot_dwe54 = resetn;
boot_iwe55 = resetn;
boot_dwe55 = resetn;
boot_iwe56 = resetn;
boot_dwe56 = resetn;
boot_iwe57 = resetn;
boot_dwe57 = resetn;
boot_iwe58 = resetn;
boot_dwe58 = resetn;
boot_iwe59 = resetn;
boot_dwe59 = resetn;
boot_iwe60 = resetn;
boot_dwe60 = resetn;
boot_iwe61 = resetn;
boot_dwe61 = resetn;
boot_iwe62 = resetn;
boot_dwe62 = resetn;
boot_iwe63 = resetn;
boot_dwe63 = resetn;
boot_iwe64 = resetn;
boot_dwe64 = resetn;
boot_iwe65 = resetn;
boot_dwe65 = resetn;
boot_iwe66 = resetn;
boot_dwe66 = resetn;
boot_iwe67 = resetn;
boot_dwe67 = resetn;
boot_iwe68 = resetn;
boot_dwe68 = resetn;
boot_iwe69 = resetn;
boot_dwe69 = resetn;
boot_iwe70 = resetn;
boot_dwe70 = resetn;
boot_iwe71 = resetn;
boot_dwe71 = resetn;
boot_iwe72 = resetn;
boot_dwe72 = resetn;
boot_iwe73 = resetn;
boot_dwe73 = resetn;
boot_iwe74 = resetn;
boot_dwe74 = resetn;
boot_iwe75 = resetn;
boot_dwe75 = resetn;
boot_iwe76 = resetn;
boot_dwe76 = resetn;
boot_iwe77 = resetn;
boot_dwe77 = resetn;
boot_iwe78 = resetn;
boot_dwe78 = resetn;
boot_iwe79 = resetn;
boot_dwe79 = resetn;
boot_iwe80 = resetn;
boot_dwe80 = resetn;
boot_iwe81 = resetn;
boot_dwe81 = resetn;
boot_iwe82 = resetn;
boot_dwe82 = resetn;
boot_iwe83 = resetn;
boot_dwe83 = resetn;
boot_iwe84 = resetn;
boot_dwe84 = resetn;
boot_iwe85 = resetn;
boot_dwe85 = resetn;
boot_iwe86 = resetn;
boot_dwe86 = resetn;
boot_iwe87 = resetn;
boot_dwe87 = resetn;
boot_iwe88 = resetn;
boot_dwe88 = resetn;
boot_iwe89 = resetn;
boot_dwe89 = resetn;
end
24: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = ~resetn;
boot_dwe24 = ~resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
boot_iwe50 = resetn;
boot_dwe50 = resetn;
boot_iwe51 = resetn;
boot_dwe51 = resetn;
boot_iwe52 = resetn;
boot_dwe52 = resetn;
boot_iwe53 = resetn;
boot_dwe53 = resetn;
boot_iwe54 = resetn;
boot_dwe54 = resetn;
boot_iwe55 = resetn;
boot_dwe55 = resetn;
boot_iwe56 = resetn;
boot_dwe56 = resetn;
boot_iwe57 = resetn;
boot_dwe57 = resetn;
boot_iwe58 = resetn;
boot_dwe58 = resetn;
boot_iwe59 = resetn;
boot_dwe59 = resetn;
boot_iwe60 = resetn;
boot_dwe60 = resetn;
boot_iwe61 = resetn;
boot_dwe61 = resetn;
boot_iwe62 = resetn;
boot_dwe62 = resetn;
boot_iwe63 = resetn;
boot_dwe63 = resetn;
boot_iwe64 = resetn;
boot_dwe64 = resetn;
boot_iwe65 = resetn;
boot_dwe65 = resetn;
boot_iwe66 = resetn;
boot_dwe66 = resetn;
boot_iwe67 = resetn;
boot_dwe67 = resetn;
boot_iwe68 = resetn;
boot_dwe68 = resetn;
boot_iwe69 = resetn;
boot_dwe69 = resetn;
boot_iwe70 = resetn;
boot_dwe70 = resetn;
boot_iwe71 = resetn;
boot_dwe71 = resetn;
boot_iwe72 = resetn;
boot_dwe72 = resetn;
boot_iwe73 = resetn;
boot_dwe73 = resetn;
boot_iwe74 = resetn;
boot_dwe74 = resetn;
boot_iwe75 = resetn;
boot_dwe75 = resetn;
boot_iwe76 = resetn;
boot_dwe76 = resetn;
boot_iwe77 = resetn;
boot_dwe77 = resetn;
boot_iwe78 = resetn;
boot_dwe78 = resetn;
boot_iwe79 = resetn;
boot_dwe79 = resetn;
boot_iwe80 = resetn;
boot_dwe80 = resetn;
boot_iwe81 = resetn;
boot_dwe81 = resetn;
boot_iwe82 = resetn;
boot_dwe82 = resetn;
boot_iwe83 = resetn;
boot_dwe83 = resetn;
boot_iwe84 = resetn;
boot_dwe84 = resetn;
boot_iwe85 = resetn;
boot_dwe85 = resetn;
boot_iwe86 = resetn;
boot_dwe86 = resetn;
boot_iwe87 = resetn;
boot_dwe87 = resetn;
boot_iwe88 = resetn;
boot_dwe88 = resetn;
boot_iwe89 = resetn;
boot_dwe89 = resetn;
end
25: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = ~resetn;
boot_dwe25 = ~resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
boot_iwe50 = resetn;
boot_dwe50 = resetn;
boot_iwe51 = resetn;
boot_dwe51 = resetn;
boot_iwe52 = resetn;
boot_dwe52 = resetn;
boot_iwe53 = resetn;
boot_dwe53 = resetn;
boot_iwe54 = resetn;
boot_dwe54 = resetn;
boot_iwe55 = resetn;
boot_dwe55 = resetn;
boot_iwe56 = resetn;
boot_dwe56 = resetn;
boot_iwe57 = resetn;
boot_dwe57 = resetn;
boot_iwe58 = resetn;
boot_dwe58 = resetn;
boot_iwe59 = resetn;
boot_dwe59 = resetn;
boot_iwe60 = resetn;
boot_dwe60 = resetn;
boot_iwe61 = resetn;
boot_dwe61 = resetn;
boot_iwe62 = resetn;
boot_dwe62 = resetn;
boot_iwe63 = resetn;
boot_dwe63 = resetn;
boot_iwe64 = resetn;
boot_dwe64 = resetn;
boot_iwe65 = resetn;
boot_dwe65 = resetn;
boot_iwe66 = resetn;
boot_dwe66 = resetn;
boot_iwe67 = resetn;
boot_dwe67 = resetn;
boot_iwe68 = resetn;
boot_dwe68 = resetn;
boot_iwe69 = resetn;
boot_dwe69 = resetn;
boot_iwe70 = resetn;
boot_dwe70 = resetn;
boot_iwe71 = resetn;
boot_dwe71 = resetn;
boot_iwe72 = resetn;
boot_dwe72 = resetn;
boot_iwe73 = resetn;
boot_dwe73 = resetn;
boot_iwe74 = resetn;
boot_dwe74 = resetn;
boot_iwe75 = resetn;
boot_dwe75 = resetn;
boot_iwe76 = resetn;
boot_dwe76 = resetn;
boot_iwe77 = resetn;
boot_dwe77 = resetn;
boot_iwe78 = resetn;
boot_dwe78 = resetn;
boot_iwe79 = resetn;
boot_dwe79 = resetn;
boot_iwe80 = resetn;
boot_dwe80 = resetn;
boot_iwe81 = resetn;
boot_dwe81 = resetn;
boot_iwe82 = resetn;
boot_dwe82 = resetn;
boot_iwe83 = resetn;
boot_dwe83 = resetn;
boot_iwe84 = resetn;
boot_dwe84 = resetn;
boot_iwe85 = resetn;
boot_dwe85 = resetn;
boot_iwe86 = resetn;
boot_dwe86 = resetn;
boot_iwe87 = resetn;
boot_dwe87 = resetn;
boot_iwe88 = resetn;
boot_dwe88 = resetn;
boot_iwe89 = resetn;
boot_dwe89 = resetn;
end
26: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = ~resetn;
boot_dwe26 = ~resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
boot_iwe50 = resetn;
boot_dwe50 = resetn;
boot_iwe51 = resetn;
boot_dwe51 = resetn;
boot_iwe52 = resetn;
boot_dwe52 = resetn;
boot_iwe53 = resetn;
boot_dwe53 = resetn;
boot_iwe54 = resetn;
boot_dwe54 = resetn;
boot_iwe55 = resetn;
boot_dwe55 = resetn;
boot_iwe56 = resetn;
boot_dwe56 = resetn;
boot_iwe57 = resetn;
boot_dwe57 = resetn;
boot_iwe58 = resetn;
boot_dwe58 = resetn;
boot_iwe59 = resetn;
boot_dwe59 = resetn;
boot_iwe60 = resetn;
boot_dwe60 = resetn;
boot_iwe61 = resetn;
boot_dwe61 = resetn;
boot_iwe62 = resetn;
boot_dwe62 = resetn;
boot_iwe63 = resetn;
boot_dwe63 = resetn;
boot_iwe64 = resetn;
boot_dwe64 = resetn;
boot_iwe65 = resetn;
boot_dwe65 = resetn;
boot_iwe66 = resetn;
boot_dwe66 = resetn;
boot_iwe67 = resetn;
boot_dwe67 = resetn;
boot_iwe68 = resetn;
boot_dwe68 = resetn;
boot_iwe69 = resetn;
boot_dwe69 = resetn;
boot_iwe70 = resetn;
boot_dwe70 = resetn;
boot_iwe71 = resetn;
boot_dwe71 = resetn;
boot_iwe72 = resetn;
boot_dwe72 = resetn;
boot_iwe73 = resetn;
boot_dwe73 = resetn;
boot_iwe74 = resetn;
boot_dwe74 = resetn;
boot_iwe75 = resetn;
boot_dwe75 = resetn;
boot_iwe76 = resetn;
boot_dwe76 = resetn;
boot_iwe77 = resetn;
boot_dwe77 = resetn;
boot_iwe78 = resetn;
boot_dwe78 = resetn;
boot_iwe79 = resetn;
boot_dwe79 = resetn;
boot_iwe80 = resetn;
boot_dwe80 = resetn;
boot_iwe81 = resetn;
boot_dwe81 = resetn;
boot_iwe82 = resetn;
boot_dwe82 = resetn;
boot_iwe83 = resetn;
boot_dwe83 = resetn;
boot_iwe84 = resetn;
boot_dwe84 = resetn;
boot_iwe85 = resetn;
boot_dwe85 = resetn;
boot_iwe86 = resetn;
boot_dwe86 = resetn;
boot_iwe87 = resetn;
boot_dwe87 = resetn;
boot_iwe88 = resetn;
boot_dwe88 = resetn;
boot_iwe89 = resetn;
boot_dwe89 = resetn;
end
27: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = ~resetn;
boot_dwe27 = ~resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
boot_iwe50 = resetn;
boot_dwe50 = resetn;
boot_iwe51 = resetn;
boot_dwe51 = resetn;
boot_iwe52 = resetn;
boot_dwe52 = resetn;
boot_iwe53 = resetn;
boot_dwe53 = resetn;
boot_iwe54 = resetn;
boot_dwe54 = resetn;
boot_iwe55 = resetn;
boot_dwe55 = resetn;
boot_iwe56 = resetn;
boot_dwe56 = resetn;
boot_iwe57 = resetn;
boot_dwe57 = resetn;
boot_iwe58 = resetn;
boot_dwe58 = resetn;
boot_iwe59 = resetn;
boot_dwe59 = resetn;
boot_iwe60 = resetn;
boot_dwe60 = resetn;
boot_iwe61 = resetn;
boot_dwe61 = resetn;
boot_iwe62 = resetn;
boot_dwe62 = resetn;
boot_iwe63 = resetn;
boot_dwe63 = resetn;
boot_iwe64 = resetn;
boot_dwe64 = resetn;
boot_iwe65 = resetn;
boot_dwe65 = resetn;
boot_iwe66 = resetn;
boot_dwe66 = resetn;
boot_iwe67 = resetn;
boot_dwe67 = resetn;
boot_iwe68 = resetn;
boot_dwe68 = resetn;
boot_iwe69 = resetn;
boot_dwe69 = resetn;
boot_iwe70 = resetn;
boot_dwe70 = resetn;
boot_iwe71 = resetn;
boot_dwe71 = resetn;
boot_iwe72 = resetn;
boot_dwe72 = resetn;
boot_iwe73 = resetn;
boot_dwe73 = resetn;
boot_iwe74 = resetn;
boot_dwe74 = resetn;
boot_iwe75 = resetn;
boot_dwe75 = resetn;
boot_iwe76 = resetn;
boot_dwe76 = resetn;
boot_iwe77 = resetn;
boot_dwe77 = resetn;
boot_iwe78 = resetn;
boot_dwe78 = resetn;
boot_iwe79 = resetn;
boot_dwe79 = resetn;
boot_iwe80 = resetn;
boot_dwe80 = resetn;
boot_iwe81 = resetn;
boot_dwe81 = resetn;
boot_iwe82 = resetn;
boot_dwe82 = resetn;
boot_iwe83 = resetn;
boot_dwe83 = resetn;
boot_iwe84 = resetn;
boot_dwe84 = resetn;
boot_iwe85 = resetn;
boot_dwe85 = resetn;
boot_iwe86 = resetn;
boot_dwe86 = resetn;
boot_iwe87 = resetn;
boot_dwe87 = resetn;
boot_iwe88 = resetn;
boot_dwe88 = resetn;
boot_iwe89 = resetn;
boot_dwe89 = resetn;
end
28: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = ~resetn;
boot_dwe28 = ~resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
boot_iwe50 = resetn;
boot_dwe50 = resetn;
boot_iwe51 = resetn;
boot_dwe51 = resetn;
boot_iwe52 = resetn;
boot_dwe52 = resetn;
boot_iwe53 = resetn;
boot_dwe53 = resetn;
boot_iwe54 = resetn;
boot_dwe54 = resetn;
boot_iwe55 = resetn;
boot_dwe55 = resetn;
boot_iwe56 = resetn;
boot_dwe56 = resetn;
boot_iwe57 = resetn;
boot_dwe57 = resetn;
boot_iwe58 = resetn;
boot_dwe58 = resetn;
boot_iwe59 = resetn;
boot_dwe59 = resetn;
boot_iwe60 = resetn;
boot_dwe60 = resetn;
boot_iwe61 = resetn;
boot_dwe61 = resetn;
boot_iwe62 = resetn;
boot_dwe62 = resetn;
boot_iwe63 = resetn;
boot_dwe63 = resetn;
boot_iwe64 = resetn;
boot_dwe64 = resetn;
boot_iwe65 = resetn;
boot_dwe65 = resetn;
boot_iwe66 = resetn;
boot_dwe66 = resetn;
boot_iwe67 = resetn;
boot_dwe67 = resetn;
boot_iwe68 = resetn;
boot_dwe68 = resetn;
boot_iwe69 = resetn;
boot_dwe69 = resetn;
boot_iwe70 = resetn;
boot_dwe70 = resetn;
boot_iwe71 = resetn;
boot_dwe71 = resetn;
boot_iwe72 = resetn;
boot_dwe72 = resetn;
boot_iwe73 = resetn;
boot_dwe73 = resetn;
boot_iwe74 = resetn;
boot_dwe74 = resetn;
boot_iwe75 = resetn;
boot_dwe75 = resetn;
boot_iwe76 = resetn;
boot_dwe76 = resetn;
boot_iwe77 = resetn;
boot_dwe77 = resetn;
boot_iwe78 = resetn;
boot_dwe78 = resetn;
boot_iwe79 = resetn;
boot_dwe79 = resetn;
boot_iwe80 = resetn;
boot_dwe80 = resetn;
boot_iwe81 = resetn;
boot_dwe81 = resetn;
boot_iwe82 = resetn;
boot_dwe82 = resetn;
boot_iwe83 = resetn;
boot_dwe83 = resetn;
boot_iwe84 = resetn;
boot_dwe84 = resetn;
boot_iwe85 = resetn;
boot_dwe85 = resetn;
boot_iwe86 = resetn;
boot_dwe86 = resetn;
boot_iwe87 = resetn;
boot_dwe87 = resetn;
boot_iwe88 = resetn;
boot_dwe88 = resetn;
boot_iwe89 = resetn;
boot_dwe89 = resetn;
end
29: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = ~resetn;
boot_dwe29 = ~resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
boot_iwe50 = resetn;
boot_dwe50 = resetn;
boot_iwe51 = resetn;
boot_dwe51 = resetn;
boot_iwe52 = resetn;
boot_dwe52 = resetn;
boot_iwe53 = resetn;
boot_dwe53 = resetn;
boot_iwe54 = resetn;
boot_dwe54 = resetn;
boot_iwe55 = resetn;
boot_dwe55 = resetn;
boot_iwe56 = resetn;
boot_dwe56 = resetn;
boot_iwe57 = resetn;
boot_dwe57 = resetn;
boot_iwe58 = resetn;
boot_dwe58 = resetn;
boot_iwe59 = resetn;
boot_dwe59 = resetn;
boot_iwe60 = resetn;
boot_dwe60 = resetn;
boot_iwe61 = resetn;
boot_dwe61 = resetn;
boot_iwe62 = resetn;
boot_dwe62 = resetn;
boot_iwe63 = resetn;
boot_dwe63 = resetn;
boot_iwe64 = resetn;
boot_dwe64 = resetn;
boot_iwe65 = resetn;
boot_dwe65 = resetn;
boot_iwe66 = resetn;
boot_dwe66 = resetn;
boot_iwe67 = resetn;
boot_dwe67 = resetn;
boot_iwe68 = resetn;
boot_dwe68 = resetn;
boot_iwe69 = resetn;
boot_dwe69 = resetn;
boot_iwe70 = resetn;
boot_dwe70 = resetn;
boot_iwe71 = resetn;
boot_dwe71 = resetn;
boot_iwe72 = resetn;
boot_dwe72 = resetn;
boot_iwe73 = resetn;
boot_dwe73 = resetn;
boot_iwe74 = resetn;
boot_dwe74 = resetn;
boot_iwe75 = resetn;
boot_dwe75 = resetn;
boot_iwe76 = resetn;
boot_dwe76 = resetn;
boot_iwe77 = resetn;
boot_dwe77 = resetn;
boot_iwe78 = resetn;
boot_dwe78 = resetn;
boot_iwe79 = resetn;
boot_dwe79 = resetn;
boot_iwe80 = resetn;
boot_dwe80 = resetn;
boot_iwe81 = resetn;
boot_dwe81 = resetn;
boot_iwe82 = resetn;
boot_dwe82 = resetn;
boot_iwe83 = resetn;
boot_dwe83 = resetn;
boot_iwe84 = resetn;
boot_dwe84 = resetn;
boot_iwe85 = resetn;
boot_dwe85 = resetn;
boot_iwe86 = resetn;
boot_dwe86 = resetn;
boot_iwe87 = resetn;
boot_dwe87 = resetn;
boot_iwe88 = resetn;
boot_dwe88 = resetn;
boot_iwe89 = resetn;
boot_dwe89 = resetn;
end
30: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = ~resetn;
boot_dwe30 = ~resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
boot_iwe50 = resetn;
boot_dwe50 = resetn;
boot_iwe51 = resetn;
boot_dwe51 = resetn;
boot_iwe52 = resetn;
boot_dwe52 = resetn;
boot_iwe53 = resetn;
boot_dwe53 = resetn;
boot_iwe54 = resetn;
boot_dwe54 = resetn;
boot_iwe55 = resetn;
boot_dwe55 = resetn;
boot_iwe56 = resetn;
boot_dwe56 = resetn;
boot_iwe57 = resetn;
boot_dwe57 = resetn;
boot_iwe58 = resetn;
boot_dwe58 = resetn;
boot_iwe59 = resetn;
boot_dwe59 = resetn;
boot_iwe60 = resetn;
boot_dwe60 = resetn;
boot_iwe61 = resetn;
boot_dwe61 = resetn;
boot_iwe62 = resetn;
boot_dwe62 = resetn;
boot_iwe63 = resetn;
boot_dwe63 = resetn;
boot_iwe64 = resetn;
boot_dwe64 = resetn;
boot_iwe65 = resetn;
boot_dwe65 = resetn;
boot_iwe66 = resetn;
boot_dwe66 = resetn;
boot_iwe67 = resetn;
boot_dwe67 = resetn;
boot_iwe68 = resetn;
boot_dwe68 = resetn;
boot_iwe69 = resetn;
boot_dwe69 = resetn;
boot_iwe70 = resetn;
boot_dwe70 = resetn;
boot_iwe71 = resetn;
boot_dwe71 = resetn;
boot_iwe72 = resetn;
boot_dwe72 = resetn;
boot_iwe73 = resetn;
boot_dwe73 = resetn;
boot_iwe74 = resetn;
boot_dwe74 = resetn;
boot_iwe75 = resetn;
boot_dwe75 = resetn;
boot_iwe76 = resetn;
boot_dwe76 = resetn;
boot_iwe77 = resetn;
boot_dwe77 = resetn;
boot_iwe78 = resetn;
boot_dwe78 = resetn;
boot_iwe79 = resetn;
boot_dwe79 = resetn;
boot_iwe80 = resetn;
boot_dwe80 = resetn;
boot_iwe81 = resetn;
boot_dwe81 = resetn;
boot_iwe82 = resetn;
boot_dwe82 = resetn;
boot_iwe83 = resetn;
boot_dwe83 = resetn;
boot_iwe84 = resetn;
boot_dwe84 = resetn;
boot_iwe85 = resetn;
boot_dwe85 = resetn;
boot_iwe86 = resetn;
boot_dwe86 = resetn;
boot_iwe87 = resetn;
boot_dwe87 = resetn;
boot_iwe88 = resetn;
boot_dwe88 = resetn;
boot_iwe89 = resetn;
boot_dwe89 = resetn;
end
31: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = ~resetn;
boot_dwe31 = ~resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
boot_iwe50 = resetn;
boot_dwe50 = resetn;
boot_iwe51 = resetn;
boot_dwe51 = resetn;
boot_iwe52 = resetn;
boot_dwe52 = resetn;
boot_iwe53 = resetn;
boot_dwe53 = resetn;
boot_iwe54 = resetn;
boot_dwe54 = resetn;
boot_iwe55 = resetn;
boot_dwe55 = resetn;
boot_iwe56 = resetn;
boot_dwe56 = resetn;
boot_iwe57 = resetn;
boot_dwe57 = resetn;
boot_iwe58 = resetn;
boot_dwe58 = resetn;
boot_iwe59 = resetn;
boot_dwe59 = resetn;
boot_iwe60 = resetn;
boot_dwe60 = resetn;
boot_iwe61 = resetn;
boot_dwe61 = resetn;
boot_iwe62 = resetn;
boot_dwe62 = resetn;
boot_iwe63 = resetn;
boot_dwe63 = resetn;
boot_iwe64 = resetn;
boot_dwe64 = resetn;
boot_iwe65 = resetn;
boot_dwe65 = resetn;
boot_iwe66 = resetn;
boot_dwe66 = resetn;
boot_iwe67 = resetn;
boot_dwe67 = resetn;
boot_iwe68 = resetn;
boot_dwe68 = resetn;
boot_iwe69 = resetn;
boot_dwe69 = resetn;
boot_iwe70 = resetn;
boot_dwe70 = resetn;
boot_iwe71 = resetn;
boot_dwe71 = resetn;
boot_iwe72 = resetn;
boot_dwe72 = resetn;
boot_iwe73 = resetn;
boot_dwe73 = resetn;
boot_iwe74 = resetn;
boot_dwe74 = resetn;
boot_iwe75 = resetn;
boot_dwe75 = resetn;
boot_iwe76 = resetn;
boot_dwe76 = resetn;
boot_iwe77 = resetn;
boot_dwe77 = resetn;
boot_iwe78 = resetn;
boot_dwe78 = resetn;
boot_iwe79 = resetn;
boot_dwe79 = resetn;
boot_iwe80 = resetn;
boot_dwe80 = resetn;
boot_iwe81 = resetn;
boot_dwe81 = resetn;
boot_iwe82 = resetn;
boot_dwe82 = resetn;
boot_iwe83 = resetn;
boot_dwe83 = resetn;
boot_iwe84 = resetn;
boot_dwe84 = resetn;
boot_iwe85 = resetn;
boot_dwe85 = resetn;
boot_iwe86 = resetn;
boot_dwe86 = resetn;
boot_iwe87 = resetn;
boot_dwe87 = resetn;
boot_iwe88 = resetn;
boot_dwe88 = resetn;
boot_iwe89 = resetn;
boot_dwe89 = resetn;
end
32: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = ~resetn;
boot_dwe32 = ~resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
boot_iwe50 = resetn;
boot_dwe50 = resetn;
boot_iwe51 = resetn;
boot_dwe51 = resetn;
boot_iwe52 = resetn;
boot_dwe52 = resetn;
boot_iwe53 = resetn;
boot_dwe53 = resetn;
boot_iwe54 = resetn;
boot_dwe54 = resetn;
boot_iwe55 = resetn;
boot_dwe55 = resetn;
boot_iwe56 = resetn;
boot_dwe56 = resetn;
boot_iwe57 = resetn;
boot_dwe57 = resetn;
boot_iwe58 = resetn;
boot_dwe58 = resetn;
boot_iwe59 = resetn;
boot_dwe59 = resetn;
boot_iwe60 = resetn;
boot_dwe60 = resetn;
boot_iwe61 = resetn;
boot_dwe61 = resetn;
boot_iwe62 = resetn;
boot_dwe62 = resetn;
boot_iwe63 = resetn;
boot_dwe63 = resetn;
boot_iwe64 = resetn;
boot_dwe64 = resetn;
boot_iwe65 = resetn;
boot_dwe65 = resetn;
boot_iwe66 = resetn;
boot_dwe66 = resetn;
boot_iwe67 = resetn;
boot_dwe67 = resetn;
boot_iwe68 = resetn;
boot_dwe68 = resetn;
boot_iwe69 = resetn;
boot_dwe69 = resetn;
boot_iwe70 = resetn;
boot_dwe70 = resetn;
boot_iwe71 = resetn;
boot_dwe71 = resetn;
boot_iwe72 = resetn;
boot_dwe72 = resetn;
boot_iwe73 = resetn;
boot_dwe73 = resetn;
boot_iwe74 = resetn;
boot_dwe74 = resetn;
boot_iwe75 = resetn;
boot_dwe75 = resetn;
boot_iwe76 = resetn;
boot_dwe76 = resetn;
boot_iwe77 = resetn;
boot_dwe77 = resetn;
boot_iwe78 = resetn;
boot_dwe78 = resetn;
boot_iwe79 = resetn;
boot_dwe79 = resetn;
boot_iwe80 = resetn;
boot_dwe80 = resetn;
boot_iwe81 = resetn;
boot_dwe81 = resetn;
boot_iwe82 = resetn;
boot_dwe82 = resetn;
boot_iwe83 = resetn;
boot_dwe83 = resetn;
boot_iwe84 = resetn;
boot_dwe84 = resetn;
boot_iwe85 = resetn;
boot_dwe85 = resetn;
boot_iwe86 = resetn;
boot_dwe86 = resetn;
boot_iwe87 = resetn;
boot_dwe87 = resetn;
boot_iwe88 = resetn;
boot_dwe88 = resetn;
boot_iwe89 = resetn;
boot_dwe89 = resetn;
end
33: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = ~resetn;
boot_dwe33 = ~resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
boot_iwe50 = resetn;
boot_dwe50 = resetn;
boot_iwe51 = resetn;
boot_dwe51 = resetn;
boot_iwe52 = resetn;
boot_dwe52 = resetn;
boot_iwe53 = resetn;
boot_dwe53 = resetn;
boot_iwe54 = resetn;
boot_dwe54 = resetn;
boot_iwe55 = resetn;
boot_dwe55 = resetn;
boot_iwe56 = resetn;
boot_dwe56 = resetn;
boot_iwe57 = resetn;
boot_dwe57 = resetn;
boot_iwe58 = resetn;
boot_dwe58 = resetn;
boot_iwe59 = resetn;
boot_dwe59 = resetn;
boot_iwe60 = resetn;
boot_dwe60 = resetn;
boot_iwe61 = resetn;
boot_dwe61 = resetn;
boot_iwe62 = resetn;
boot_dwe62 = resetn;
boot_iwe63 = resetn;
boot_dwe63 = resetn;
boot_iwe64 = resetn;
boot_dwe64 = resetn;
boot_iwe65 = resetn;
boot_dwe65 = resetn;
boot_iwe66 = resetn;
boot_dwe66 = resetn;
boot_iwe67 = resetn;
boot_dwe67 = resetn;
boot_iwe68 = resetn;
boot_dwe68 = resetn;
boot_iwe69 = resetn;
boot_dwe69 = resetn;
boot_iwe70 = resetn;
boot_dwe70 = resetn;
boot_iwe71 = resetn;
boot_dwe71 = resetn;
boot_iwe72 = resetn;
boot_dwe72 = resetn;
boot_iwe73 = resetn;
boot_dwe73 = resetn;
boot_iwe74 = resetn;
boot_dwe74 = resetn;
boot_iwe75 = resetn;
boot_dwe75 = resetn;
boot_iwe76 = resetn;
boot_dwe76 = resetn;
boot_iwe77 = resetn;
boot_dwe77 = resetn;
boot_iwe78 = resetn;
boot_dwe78 = resetn;
boot_iwe79 = resetn;
boot_dwe79 = resetn;
boot_iwe80 = resetn;
boot_dwe80 = resetn;
boot_iwe81 = resetn;
boot_dwe81 = resetn;
boot_iwe82 = resetn;
boot_dwe82 = resetn;
boot_iwe83 = resetn;
boot_dwe83 = resetn;
boot_iwe84 = resetn;
boot_dwe84 = resetn;
boot_iwe85 = resetn;
boot_dwe85 = resetn;
boot_iwe86 = resetn;
boot_dwe86 = resetn;
boot_iwe87 = resetn;
boot_dwe87 = resetn;
boot_iwe88 = resetn;
boot_dwe88 = resetn;
boot_iwe89 = resetn;
boot_dwe89 = resetn;
end
34: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = ~resetn;
boot_dwe34 = ~resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
boot_iwe50 = resetn;
boot_dwe50 = resetn;
boot_iwe51 = resetn;
boot_dwe51 = resetn;
boot_iwe52 = resetn;
boot_dwe52 = resetn;
boot_iwe53 = resetn;
boot_dwe53 = resetn;
boot_iwe54 = resetn;
boot_dwe54 = resetn;
boot_iwe55 = resetn;
boot_dwe55 = resetn;
boot_iwe56 = resetn;
boot_dwe56 = resetn;
boot_iwe57 = resetn;
boot_dwe57 = resetn;
boot_iwe58 = resetn;
boot_dwe58 = resetn;
boot_iwe59 = resetn;
boot_dwe59 = resetn;
boot_iwe60 = resetn;
boot_dwe60 = resetn;
boot_iwe61 = resetn;
boot_dwe61 = resetn;
boot_iwe62 = resetn;
boot_dwe62 = resetn;
boot_iwe63 = resetn;
boot_dwe63 = resetn;
boot_iwe64 = resetn;
boot_dwe64 = resetn;
boot_iwe65 = resetn;
boot_dwe65 = resetn;
boot_iwe66 = resetn;
boot_dwe66 = resetn;
boot_iwe67 = resetn;
boot_dwe67 = resetn;
boot_iwe68 = resetn;
boot_dwe68 = resetn;
boot_iwe69 = resetn;
boot_dwe69 = resetn;
boot_iwe70 = resetn;
boot_dwe70 = resetn;
boot_iwe71 = resetn;
boot_dwe71 = resetn;
boot_iwe72 = resetn;
boot_dwe72 = resetn;
boot_iwe73 = resetn;
boot_dwe73 = resetn;
boot_iwe74 = resetn;
boot_dwe74 = resetn;
boot_iwe75 = resetn;
boot_dwe75 = resetn;
boot_iwe76 = resetn;
boot_dwe76 = resetn;
boot_iwe77 = resetn;
boot_dwe77 = resetn;
boot_iwe78 = resetn;
boot_dwe78 = resetn;
boot_iwe79 = resetn;
boot_dwe79 = resetn;
boot_iwe80 = resetn;
boot_dwe80 = resetn;
boot_iwe81 = resetn;
boot_dwe81 = resetn;
boot_iwe82 = resetn;
boot_dwe82 = resetn;
boot_iwe83 = resetn;
boot_dwe83 = resetn;
boot_iwe84 = resetn;
boot_dwe84 = resetn;
boot_iwe85 = resetn;
boot_dwe85 = resetn;
boot_iwe86 = resetn;
boot_dwe86 = resetn;
boot_iwe87 = resetn;
boot_dwe87 = resetn;
boot_iwe88 = resetn;
boot_dwe88 = resetn;
boot_iwe89 = resetn;
boot_dwe89 = resetn;
end
35: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = ~resetn;
boot_dwe35 = ~resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
boot_iwe50 = resetn;
boot_dwe50 = resetn;
boot_iwe51 = resetn;
boot_dwe51 = resetn;
boot_iwe52 = resetn;
boot_dwe52 = resetn;
boot_iwe53 = resetn;
boot_dwe53 = resetn;
boot_iwe54 = resetn;
boot_dwe54 = resetn;
boot_iwe55 = resetn;
boot_dwe55 = resetn;
boot_iwe56 = resetn;
boot_dwe56 = resetn;
boot_iwe57 = resetn;
boot_dwe57 = resetn;
boot_iwe58 = resetn;
boot_dwe58 = resetn;
boot_iwe59 = resetn;
boot_dwe59 = resetn;
boot_iwe60 = resetn;
boot_dwe60 = resetn;
boot_iwe61 = resetn;
boot_dwe61 = resetn;
boot_iwe62 = resetn;
boot_dwe62 = resetn;
boot_iwe63 = resetn;
boot_dwe63 = resetn;
boot_iwe64 = resetn;
boot_dwe64 = resetn;
boot_iwe65 = resetn;
boot_dwe65 = resetn;
boot_iwe66 = resetn;
boot_dwe66 = resetn;
boot_iwe67 = resetn;
boot_dwe67 = resetn;
boot_iwe68 = resetn;
boot_dwe68 = resetn;
boot_iwe69 = resetn;
boot_dwe69 = resetn;
boot_iwe70 = resetn;
boot_dwe70 = resetn;
boot_iwe71 = resetn;
boot_dwe71 = resetn;
boot_iwe72 = resetn;
boot_dwe72 = resetn;
boot_iwe73 = resetn;
boot_dwe73 = resetn;
boot_iwe74 = resetn;
boot_dwe74 = resetn;
boot_iwe75 = resetn;
boot_dwe75 = resetn;
boot_iwe76 = resetn;
boot_dwe76 = resetn;
boot_iwe77 = resetn;
boot_dwe77 = resetn;
boot_iwe78 = resetn;
boot_dwe78 = resetn;
boot_iwe79 = resetn;
boot_dwe79 = resetn;
boot_iwe80 = resetn;
boot_dwe80 = resetn;
boot_iwe81 = resetn;
boot_dwe81 = resetn;
boot_iwe82 = resetn;
boot_dwe82 = resetn;
boot_iwe83 = resetn;
boot_dwe83 = resetn;
boot_iwe84 = resetn;
boot_dwe84 = resetn;
boot_iwe85 = resetn;
boot_dwe85 = resetn;
boot_iwe86 = resetn;
boot_dwe86 = resetn;
boot_iwe87 = resetn;
boot_dwe87 = resetn;
boot_iwe88 = resetn;
boot_dwe88 = resetn;
boot_iwe89 = resetn;
boot_dwe89 = resetn;
end
36: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = ~resetn;
boot_dwe36 = ~resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
boot_iwe50 = resetn;
boot_dwe50 = resetn;
boot_iwe51 = resetn;
boot_dwe51 = resetn;
boot_iwe52 = resetn;
boot_dwe52 = resetn;
boot_iwe53 = resetn;
boot_dwe53 = resetn;
boot_iwe54 = resetn;
boot_dwe54 = resetn;
boot_iwe55 = resetn;
boot_dwe55 = resetn;
boot_iwe56 = resetn;
boot_dwe56 = resetn;
boot_iwe57 = resetn;
boot_dwe57 = resetn;
boot_iwe58 = resetn;
boot_dwe58 = resetn;
boot_iwe59 = resetn;
boot_dwe59 = resetn;
boot_iwe60 = resetn;
boot_dwe60 = resetn;
boot_iwe61 = resetn;
boot_dwe61 = resetn;
boot_iwe62 = resetn;
boot_dwe62 = resetn;
boot_iwe63 = resetn;
boot_dwe63 = resetn;
boot_iwe64 = resetn;
boot_dwe64 = resetn;
boot_iwe65 = resetn;
boot_dwe65 = resetn;
boot_iwe66 = resetn;
boot_dwe66 = resetn;
boot_iwe67 = resetn;
boot_dwe67 = resetn;
boot_iwe68 = resetn;
boot_dwe68 = resetn;
boot_iwe69 = resetn;
boot_dwe69 = resetn;
boot_iwe70 = resetn;
boot_dwe70 = resetn;
boot_iwe71 = resetn;
boot_dwe71 = resetn;
boot_iwe72 = resetn;
boot_dwe72 = resetn;
boot_iwe73 = resetn;
boot_dwe73 = resetn;
boot_iwe74 = resetn;
boot_dwe74 = resetn;
boot_iwe75 = resetn;
boot_dwe75 = resetn;
boot_iwe76 = resetn;
boot_dwe76 = resetn;
boot_iwe77 = resetn;
boot_dwe77 = resetn;
boot_iwe78 = resetn;
boot_dwe78 = resetn;
boot_iwe79 = resetn;
boot_dwe79 = resetn;
boot_iwe80 = resetn;
boot_dwe80 = resetn;
boot_iwe81 = resetn;
boot_dwe81 = resetn;
boot_iwe82 = resetn;
boot_dwe82 = resetn;
boot_iwe83 = resetn;
boot_dwe83 = resetn;
boot_iwe84 = resetn;
boot_dwe84 = resetn;
boot_iwe85 = resetn;
boot_dwe85 = resetn;
boot_iwe86 = resetn;
boot_dwe86 = resetn;
boot_iwe87 = resetn;
boot_dwe87 = resetn;
boot_iwe88 = resetn;
boot_dwe88 = resetn;
boot_iwe89 = resetn;
boot_dwe89 = resetn;
end
37: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = ~resetn;
boot_dwe37 = ~resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
boot_iwe50 = resetn;
boot_dwe50 = resetn;
boot_iwe51 = resetn;
boot_dwe51 = resetn;
boot_iwe52 = resetn;
boot_dwe52 = resetn;
boot_iwe53 = resetn;
boot_dwe53 = resetn;
boot_iwe54 = resetn;
boot_dwe54 = resetn;
boot_iwe55 = resetn;
boot_dwe55 = resetn;
boot_iwe56 = resetn;
boot_dwe56 = resetn;
boot_iwe57 = resetn;
boot_dwe57 = resetn;
boot_iwe58 = resetn;
boot_dwe58 = resetn;
boot_iwe59 = resetn;
boot_dwe59 = resetn;
boot_iwe60 = resetn;
boot_dwe60 = resetn;
boot_iwe61 = resetn;
boot_dwe61 = resetn;
boot_iwe62 = resetn;
boot_dwe62 = resetn;
boot_iwe63 = resetn;
boot_dwe63 = resetn;
boot_iwe64 = resetn;
boot_dwe64 = resetn;
boot_iwe65 = resetn;
boot_dwe65 = resetn;
boot_iwe66 = resetn;
boot_dwe66 = resetn;
boot_iwe67 = resetn;
boot_dwe67 = resetn;
boot_iwe68 = resetn;
boot_dwe68 = resetn;
boot_iwe69 = resetn;
boot_dwe69 = resetn;
boot_iwe70 = resetn;
boot_dwe70 = resetn;
boot_iwe71 = resetn;
boot_dwe71 = resetn;
boot_iwe72 = resetn;
boot_dwe72 = resetn;
boot_iwe73 = resetn;
boot_dwe73 = resetn;
boot_iwe74 = resetn;
boot_dwe74 = resetn;
boot_iwe75 = resetn;
boot_dwe75 = resetn;
boot_iwe76 = resetn;
boot_dwe76 = resetn;
boot_iwe77 = resetn;
boot_dwe77 = resetn;
boot_iwe78 = resetn;
boot_dwe78 = resetn;
boot_iwe79 = resetn;
boot_dwe79 = resetn;
boot_iwe80 = resetn;
boot_dwe80 = resetn;
boot_iwe81 = resetn;
boot_dwe81 = resetn;
boot_iwe82 = resetn;
boot_dwe82 = resetn;
boot_iwe83 = resetn;
boot_dwe83 = resetn;
boot_iwe84 = resetn;
boot_dwe84 = resetn;
boot_iwe85 = resetn;
boot_dwe85 = resetn;
boot_iwe86 = resetn;
boot_dwe86 = resetn;
boot_iwe87 = resetn;
boot_dwe87 = resetn;
boot_iwe88 = resetn;
boot_dwe88 = resetn;
boot_iwe89 = resetn;
boot_dwe89 = resetn;
end
38: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = ~resetn;
boot_dwe38 = ~resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
boot_iwe50 = resetn;
boot_dwe50 = resetn;
boot_iwe51 = resetn;
boot_dwe51 = resetn;
boot_iwe52 = resetn;
boot_dwe52 = resetn;
boot_iwe53 = resetn;
boot_dwe53 = resetn;
boot_iwe54 = resetn;
boot_dwe54 = resetn;
boot_iwe55 = resetn;
boot_dwe55 = resetn;
boot_iwe56 = resetn;
boot_dwe56 = resetn;
boot_iwe57 = resetn;
boot_dwe57 = resetn;
boot_iwe58 = resetn;
boot_dwe58 = resetn;
boot_iwe59 = resetn;
boot_dwe59 = resetn;
boot_iwe60 = resetn;
boot_dwe60 = resetn;
boot_iwe61 = resetn;
boot_dwe61 = resetn;
boot_iwe62 = resetn;
boot_dwe62 = resetn;
boot_iwe63 = resetn;
boot_dwe63 = resetn;
boot_iwe64 = resetn;
boot_dwe64 = resetn;
boot_iwe65 = resetn;
boot_dwe65 = resetn;
boot_iwe66 = resetn;
boot_dwe66 = resetn;
boot_iwe67 = resetn;
boot_dwe67 = resetn;
boot_iwe68 = resetn;
boot_dwe68 = resetn;
boot_iwe69 = resetn;
boot_dwe69 = resetn;
boot_iwe70 = resetn;
boot_dwe70 = resetn;
boot_iwe71 = resetn;
boot_dwe71 = resetn;
boot_iwe72 = resetn;
boot_dwe72 = resetn;
boot_iwe73 = resetn;
boot_dwe73 = resetn;
boot_iwe74 = resetn;
boot_dwe74 = resetn;
boot_iwe75 = resetn;
boot_dwe75 = resetn;
boot_iwe76 = resetn;
boot_dwe76 = resetn;
boot_iwe77 = resetn;
boot_dwe77 = resetn;
boot_iwe78 = resetn;
boot_dwe78 = resetn;
boot_iwe79 = resetn;
boot_dwe79 = resetn;
boot_iwe80 = resetn;
boot_dwe80 = resetn;
boot_iwe81 = resetn;
boot_dwe81 = resetn;
boot_iwe82 = resetn;
boot_dwe82 = resetn;
boot_iwe83 = resetn;
boot_dwe83 = resetn;
boot_iwe84 = resetn;
boot_dwe84 = resetn;
boot_iwe85 = resetn;
boot_dwe85 = resetn;
boot_iwe86 = resetn;
boot_dwe86 = resetn;
boot_iwe87 = resetn;
boot_dwe87 = resetn;
boot_iwe88 = resetn;
boot_dwe88 = resetn;
boot_iwe89 = resetn;
boot_dwe89 = resetn;
end
39: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = ~resetn;
boot_dwe39 = ~resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
boot_iwe50 = resetn;
boot_dwe50 = resetn;
boot_iwe51 = resetn;
boot_dwe51 = resetn;
boot_iwe52 = resetn;
boot_dwe52 = resetn;
boot_iwe53 = resetn;
boot_dwe53 = resetn;
boot_iwe54 = resetn;
boot_dwe54 = resetn;
boot_iwe55 = resetn;
boot_dwe55 = resetn;
boot_iwe56 = resetn;
boot_dwe56 = resetn;
boot_iwe57 = resetn;
boot_dwe57 = resetn;
boot_iwe58 = resetn;
boot_dwe58 = resetn;
boot_iwe59 = resetn;
boot_dwe59 = resetn;
boot_iwe60 = resetn;
boot_dwe60 = resetn;
boot_iwe61 = resetn;
boot_dwe61 = resetn;
boot_iwe62 = resetn;
boot_dwe62 = resetn;
boot_iwe63 = resetn;
boot_dwe63 = resetn;
boot_iwe64 = resetn;
boot_dwe64 = resetn;
boot_iwe65 = resetn;
boot_dwe65 = resetn;
boot_iwe66 = resetn;
boot_dwe66 = resetn;
boot_iwe67 = resetn;
boot_dwe67 = resetn;
boot_iwe68 = resetn;
boot_dwe68 = resetn;
boot_iwe69 = resetn;
boot_dwe69 = resetn;
boot_iwe70 = resetn;
boot_dwe70 = resetn;
boot_iwe71 = resetn;
boot_dwe71 = resetn;
boot_iwe72 = resetn;
boot_dwe72 = resetn;
boot_iwe73 = resetn;
boot_dwe73 = resetn;
boot_iwe74 = resetn;
boot_dwe74 = resetn;
boot_iwe75 = resetn;
boot_dwe75 = resetn;
boot_iwe76 = resetn;
boot_dwe76 = resetn;
boot_iwe77 = resetn;
boot_dwe77 = resetn;
boot_iwe78 = resetn;
boot_dwe78 = resetn;
boot_iwe79 = resetn;
boot_dwe79 = resetn;
boot_iwe80 = resetn;
boot_dwe80 = resetn;
boot_iwe81 = resetn;
boot_dwe81 = resetn;
boot_iwe82 = resetn;
boot_dwe82 = resetn;
boot_iwe83 = resetn;
boot_dwe83 = resetn;
boot_iwe84 = resetn;
boot_dwe84 = resetn;
boot_iwe85 = resetn;
boot_dwe85 = resetn;
boot_iwe86 = resetn;
boot_dwe86 = resetn;
boot_iwe87 = resetn;
boot_dwe87 = resetn;
boot_iwe88 = resetn;
boot_dwe88 = resetn;
boot_iwe89 = resetn;
boot_dwe89 = resetn;
end
40: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = ~resetn;
boot_dwe40 = ~resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
boot_iwe50 = resetn;
boot_dwe50 = resetn;
boot_iwe51 = resetn;
boot_dwe51 = resetn;
boot_iwe52 = resetn;
boot_dwe52 = resetn;
boot_iwe53 = resetn;
boot_dwe53 = resetn;
boot_iwe54 = resetn;
boot_dwe54 = resetn;
boot_iwe55 = resetn;
boot_dwe55 = resetn;
boot_iwe56 = resetn;
boot_dwe56 = resetn;
boot_iwe57 = resetn;
boot_dwe57 = resetn;
boot_iwe58 = resetn;
boot_dwe58 = resetn;
boot_iwe59 = resetn;
boot_dwe59 = resetn;
boot_iwe60 = resetn;
boot_dwe60 = resetn;
boot_iwe61 = resetn;
boot_dwe61 = resetn;
boot_iwe62 = resetn;
boot_dwe62 = resetn;
boot_iwe63 = resetn;
boot_dwe63 = resetn;
boot_iwe64 = resetn;
boot_dwe64 = resetn;
boot_iwe65 = resetn;
boot_dwe65 = resetn;
boot_iwe66 = resetn;
boot_dwe66 = resetn;
boot_iwe67 = resetn;
boot_dwe67 = resetn;
boot_iwe68 = resetn;
boot_dwe68 = resetn;
boot_iwe69 = resetn;
boot_dwe69 = resetn;
boot_iwe70 = resetn;
boot_dwe70 = resetn;
boot_iwe71 = resetn;
boot_dwe71 = resetn;
boot_iwe72 = resetn;
boot_dwe72 = resetn;
boot_iwe73 = resetn;
boot_dwe73 = resetn;
boot_iwe74 = resetn;
boot_dwe74 = resetn;
boot_iwe75 = resetn;
boot_dwe75 = resetn;
boot_iwe76 = resetn;
boot_dwe76 = resetn;
boot_iwe77 = resetn;
boot_dwe77 = resetn;
boot_iwe78 = resetn;
boot_dwe78 = resetn;
boot_iwe79 = resetn;
boot_dwe79 = resetn;
boot_iwe80 = resetn;
boot_dwe80 = resetn;
boot_iwe81 = resetn;
boot_dwe81 = resetn;
boot_iwe82 = resetn;
boot_dwe82 = resetn;
boot_iwe83 = resetn;
boot_dwe83 = resetn;
boot_iwe84 = resetn;
boot_dwe84 = resetn;
boot_iwe85 = resetn;
boot_dwe85 = resetn;
boot_iwe86 = resetn;
boot_dwe86 = resetn;
boot_iwe87 = resetn;
boot_dwe87 = resetn;
boot_iwe88 = resetn;
boot_dwe88 = resetn;
boot_iwe89 = resetn;
boot_dwe89 = resetn;
end
41: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = ~resetn;
boot_dwe41 = ~resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
boot_iwe50 = resetn;
boot_dwe50 = resetn;
boot_iwe51 = resetn;
boot_dwe51 = resetn;
boot_iwe52 = resetn;
boot_dwe52 = resetn;
boot_iwe53 = resetn;
boot_dwe53 = resetn;
boot_iwe54 = resetn;
boot_dwe54 = resetn;
boot_iwe55 = resetn;
boot_dwe55 = resetn;
boot_iwe56 = resetn;
boot_dwe56 = resetn;
boot_iwe57 = resetn;
boot_dwe57 = resetn;
boot_iwe58 = resetn;
boot_dwe58 = resetn;
boot_iwe59 = resetn;
boot_dwe59 = resetn;
boot_iwe60 = resetn;
boot_dwe60 = resetn;
boot_iwe61 = resetn;
boot_dwe61 = resetn;
boot_iwe62 = resetn;
boot_dwe62 = resetn;
boot_iwe63 = resetn;
boot_dwe63 = resetn;
boot_iwe64 = resetn;
boot_dwe64 = resetn;
boot_iwe65 = resetn;
boot_dwe65 = resetn;
boot_iwe66 = resetn;
boot_dwe66 = resetn;
boot_iwe67 = resetn;
boot_dwe67 = resetn;
boot_iwe68 = resetn;
boot_dwe68 = resetn;
boot_iwe69 = resetn;
boot_dwe69 = resetn;
boot_iwe70 = resetn;
boot_dwe70 = resetn;
boot_iwe71 = resetn;
boot_dwe71 = resetn;
boot_iwe72 = resetn;
boot_dwe72 = resetn;
boot_iwe73 = resetn;
boot_dwe73 = resetn;
boot_iwe74 = resetn;
boot_dwe74 = resetn;
boot_iwe75 = resetn;
boot_dwe75 = resetn;
boot_iwe76 = resetn;
boot_dwe76 = resetn;
boot_iwe77 = resetn;
boot_dwe77 = resetn;
boot_iwe78 = resetn;
boot_dwe78 = resetn;
boot_iwe79 = resetn;
boot_dwe79 = resetn;
boot_iwe80 = resetn;
boot_dwe80 = resetn;
boot_iwe81 = resetn;
boot_dwe81 = resetn;
boot_iwe82 = resetn;
boot_dwe82 = resetn;
boot_iwe83 = resetn;
boot_dwe83 = resetn;
boot_iwe84 = resetn;
boot_dwe84 = resetn;
boot_iwe85 = resetn;
boot_dwe85 = resetn;
boot_iwe86 = resetn;
boot_dwe86 = resetn;
boot_iwe87 = resetn;
boot_dwe87 = resetn;
boot_iwe88 = resetn;
boot_dwe88 = resetn;
boot_iwe89 = resetn;
boot_dwe89 = resetn;
end
42: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = ~resetn;
boot_dwe42 = ~resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
boot_iwe50 = resetn;
boot_dwe50 = resetn;
boot_iwe51 = resetn;
boot_dwe51 = resetn;
boot_iwe52 = resetn;
boot_dwe52 = resetn;
boot_iwe53 = resetn;
boot_dwe53 = resetn;
boot_iwe54 = resetn;
boot_dwe54 = resetn;
boot_iwe55 = resetn;
boot_dwe55 = resetn;
boot_iwe56 = resetn;
boot_dwe56 = resetn;
boot_iwe57 = resetn;
boot_dwe57 = resetn;
boot_iwe58 = resetn;
boot_dwe58 = resetn;
boot_iwe59 = resetn;
boot_dwe59 = resetn;
boot_iwe60 = resetn;
boot_dwe60 = resetn;
boot_iwe61 = resetn;
boot_dwe61 = resetn;
boot_iwe62 = resetn;
boot_dwe62 = resetn;
boot_iwe63 = resetn;
boot_dwe63 = resetn;
boot_iwe64 = resetn;
boot_dwe64 = resetn;
boot_iwe65 = resetn;
boot_dwe65 = resetn;
boot_iwe66 = resetn;
boot_dwe66 = resetn;
boot_iwe67 = resetn;
boot_dwe67 = resetn;
boot_iwe68 = resetn;
boot_dwe68 = resetn;
boot_iwe69 = resetn;
boot_dwe69 = resetn;
boot_iwe70 = resetn;
boot_dwe70 = resetn;
boot_iwe71 = resetn;
boot_dwe71 = resetn;
boot_iwe72 = resetn;
boot_dwe72 = resetn;
boot_iwe73 = resetn;
boot_dwe73 = resetn;
boot_iwe74 = resetn;
boot_dwe74 = resetn;
boot_iwe75 = resetn;
boot_dwe75 = resetn;
boot_iwe76 = resetn;
boot_dwe76 = resetn;
boot_iwe77 = resetn;
boot_dwe77 = resetn;
boot_iwe78 = resetn;
boot_dwe78 = resetn;
boot_iwe79 = resetn;
boot_dwe79 = resetn;
boot_iwe80 = resetn;
boot_dwe80 = resetn;
boot_iwe81 = resetn;
boot_dwe81 = resetn;
boot_iwe82 = resetn;
boot_dwe82 = resetn;
boot_iwe83 = resetn;
boot_dwe83 = resetn;
boot_iwe84 = resetn;
boot_dwe84 = resetn;
boot_iwe85 = resetn;
boot_dwe85 = resetn;
boot_iwe86 = resetn;
boot_dwe86 = resetn;
boot_iwe87 = resetn;
boot_dwe87 = resetn;
boot_iwe88 = resetn;
boot_dwe88 = resetn;
boot_iwe89 = resetn;
boot_dwe89 = resetn;
end
43: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = ~resetn;
boot_dwe43 = ~resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
boot_iwe50 = resetn;
boot_dwe50 = resetn;
boot_iwe51 = resetn;
boot_dwe51 = resetn;
boot_iwe52 = resetn;
boot_dwe52 = resetn;
boot_iwe53 = resetn;
boot_dwe53 = resetn;
boot_iwe54 = resetn;
boot_dwe54 = resetn;
boot_iwe55 = resetn;
boot_dwe55 = resetn;
boot_iwe56 = resetn;
boot_dwe56 = resetn;
boot_iwe57 = resetn;
boot_dwe57 = resetn;
boot_iwe58 = resetn;
boot_dwe58 = resetn;
boot_iwe59 = resetn;
boot_dwe59 = resetn;
boot_iwe60 = resetn;
boot_dwe60 = resetn;
boot_iwe61 = resetn;
boot_dwe61 = resetn;
boot_iwe62 = resetn;
boot_dwe62 = resetn;
boot_iwe63 = resetn;
boot_dwe63 = resetn;
boot_iwe64 = resetn;
boot_dwe64 = resetn;
boot_iwe65 = resetn;
boot_dwe65 = resetn;
boot_iwe66 = resetn;
boot_dwe66 = resetn;
boot_iwe67 = resetn;
boot_dwe67 = resetn;
boot_iwe68 = resetn;
boot_dwe68 = resetn;
boot_iwe69 = resetn;
boot_dwe69 = resetn;
boot_iwe70 = resetn;
boot_dwe70 = resetn;
boot_iwe71 = resetn;
boot_dwe71 = resetn;
boot_iwe72 = resetn;
boot_dwe72 = resetn;
boot_iwe73 = resetn;
boot_dwe73 = resetn;
boot_iwe74 = resetn;
boot_dwe74 = resetn;
boot_iwe75 = resetn;
boot_dwe75 = resetn;
boot_iwe76 = resetn;
boot_dwe76 = resetn;
boot_iwe77 = resetn;
boot_dwe77 = resetn;
boot_iwe78 = resetn;
boot_dwe78 = resetn;
boot_iwe79 = resetn;
boot_dwe79 = resetn;
boot_iwe80 = resetn;
boot_dwe80 = resetn;
boot_iwe81 = resetn;
boot_dwe81 = resetn;
boot_iwe82 = resetn;
boot_dwe82 = resetn;
boot_iwe83 = resetn;
boot_dwe83 = resetn;
boot_iwe84 = resetn;
boot_dwe84 = resetn;
boot_iwe85 = resetn;
boot_dwe85 = resetn;
boot_iwe86 = resetn;
boot_dwe86 = resetn;
boot_iwe87 = resetn;
boot_dwe87 = resetn;
boot_iwe88 = resetn;
boot_dwe88 = resetn;
boot_iwe89 = resetn;
boot_dwe89 = resetn;
end
44: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = ~resetn;
boot_dwe44 = ~resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
boot_iwe50 = resetn;
boot_dwe50 = resetn;
boot_iwe51 = resetn;
boot_dwe51 = resetn;
boot_iwe52 = resetn;
boot_dwe52 = resetn;
boot_iwe53 = resetn;
boot_dwe53 = resetn;
boot_iwe54 = resetn;
boot_dwe54 = resetn;
boot_iwe55 = resetn;
boot_dwe55 = resetn;
boot_iwe56 = resetn;
boot_dwe56 = resetn;
boot_iwe57 = resetn;
boot_dwe57 = resetn;
boot_iwe58 = resetn;
boot_dwe58 = resetn;
boot_iwe59 = resetn;
boot_dwe59 = resetn;
boot_iwe60 = resetn;
boot_dwe60 = resetn;
boot_iwe61 = resetn;
boot_dwe61 = resetn;
boot_iwe62 = resetn;
boot_dwe62 = resetn;
boot_iwe63 = resetn;
boot_dwe63 = resetn;
boot_iwe64 = resetn;
boot_dwe64 = resetn;
boot_iwe65 = resetn;
boot_dwe65 = resetn;
boot_iwe66 = resetn;
boot_dwe66 = resetn;
boot_iwe67 = resetn;
boot_dwe67 = resetn;
boot_iwe68 = resetn;
boot_dwe68 = resetn;
boot_iwe69 = resetn;
boot_dwe69 = resetn;
boot_iwe70 = resetn;
boot_dwe70 = resetn;
boot_iwe71 = resetn;
boot_dwe71 = resetn;
boot_iwe72 = resetn;
boot_dwe72 = resetn;
boot_iwe73 = resetn;
boot_dwe73 = resetn;
boot_iwe74 = resetn;
boot_dwe74 = resetn;
boot_iwe75 = resetn;
boot_dwe75 = resetn;
boot_iwe76 = resetn;
boot_dwe76 = resetn;
boot_iwe77 = resetn;
boot_dwe77 = resetn;
boot_iwe78 = resetn;
boot_dwe78 = resetn;
boot_iwe79 = resetn;
boot_dwe79 = resetn;
boot_iwe80 = resetn;
boot_dwe80 = resetn;
boot_iwe81 = resetn;
boot_dwe81 = resetn;
boot_iwe82 = resetn;
boot_dwe82 = resetn;
boot_iwe83 = resetn;
boot_dwe83 = resetn;
boot_iwe84 = resetn;
boot_dwe84 = resetn;
boot_iwe85 = resetn;
boot_dwe85 = resetn;
boot_iwe86 = resetn;
boot_dwe86 = resetn;
boot_iwe87 = resetn;
boot_dwe87 = resetn;
boot_iwe88 = resetn;
boot_dwe88 = resetn;
boot_iwe89 = resetn;
boot_dwe89 = resetn;
end
45: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = ~resetn;
boot_dwe45 = ~resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
boot_iwe50 = resetn;
boot_dwe50 = resetn;
boot_iwe51 = resetn;
boot_dwe51 = resetn;
boot_iwe52 = resetn;
boot_dwe52 = resetn;
boot_iwe53 = resetn;
boot_dwe53 = resetn;
boot_iwe54 = resetn;
boot_dwe54 = resetn;
boot_iwe55 = resetn;
boot_dwe55 = resetn;
boot_iwe56 = resetn;
boot_dwe56 = resetn;
boot_iwe57 = resetn;
boot_dwe57 = resetn;
boot_iwe58 = resetn;
boot_dwe58 = resetn;
boot_iwe59 = resetn;
boot_dwe59 = resetn;
boot_iwe60 = resetn;
boot_dwe60 = resetn;
boot_iwe61 = resetn;
boot_dwe61 = resetn;
boot_iwe62 = resetn;
boot_dwe62 = resetn;
boot_iwe63 = resetn;
boot_dwe63 = resetn;
boot_iwe64 = resetn;
boot_dwe64 = resetn;
boot_iwe65 = resetn;
boot_dwe65 = resetn;
boot_iwe66 = resetn;
boot_dwe66 = resetn;
boot_iwe67 = resetn;
boot_dwe67 = resetn;
boot_iwe68 = resetn;
boot_dwe68 = resetn;
boot_iwe69 = resetn;
boot_dwe69 = resetn;
boot_iwe70 = resetn;
boot_dwe70 = resetn;
boot_iwe71 = resetn;
boot_dwe71 = resetn;
boot_iwe72 = resetn;
boot_dwe72 = resetn;
boot_iwe73 = resetn;
boot_dwe73 = resetn;
boot_iwe74 = resetn;
boot_dwe74 = resetn;
boot_iwe75 = resetn;
boot_dwe75 = resetn;
boot_iwe76 = resetn;
boot_dwe76 = resetn;
boot_iwe77 = resetn;
boot_dwe77 = resetn;
boot_iwe78 = resetn;
boot_dwe78 = resetn;
boot_iwe79 = resetn;
boot_dwe79 = resetn;
boot_iwe80 = resetn;
boot_dwe80 = resetn;
boot_iwe81 = resetn;
boot_dwe81 = resetn;
boot_iwe82 = resetn;
boot_dwe82 = resetn;
boot_iwe83 = resetn;
boot_dwe83 = resetn;
boot_iwe84 = resetn;
boot_dwe84 = resetn;
boot_iwe85 = resetn;
boot_dwe85 = resetn;
boot_iwe86 = resetn;
boot_dwe86 = resetn;
boot_iwe87 = resetn;
boot_dwe87 = resetn;
boot_iwe88 = resetn;
boot_dwe88 = resetn;
boot_iwe89 = resetn;
boot_dwe89 = resetn;
end
46: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = ~resetn;
boot_dwe46 = ~resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
boot_iwe50 = resetn;
boot_dwe50 = resetn;
boot_iwe51 = resetn;
boot_dwe51 = resetn;
boot_iwe52 = resetn;
boot_dwe52 = resetn;
boot_iwe53 = resetn;
boot_dwe53 = resetn;
boot_iwe54 = resetn;
boot_dwe54 = resetn;
boot_iwe55 = resetn;
boot_dwe55 = resetn;
boot_iwe56 = resetn;
boot_dwe56 = resetn;
boot_iwe57 = resetn;
boot_dwe57 = resetn;
boot_iwe58 = resetn;
boot_dwe58 = resetn;
boot_iwe59 = resetn;
boot_dwe59 = resetn;
boot_iwe60 = resetn;
boot_dwe60 = resetn;
boot_iwe61 = resetn;
boot_dwe61 = resetn;
boot_iwe62 = resetn;
boot_dwe62 = resetn;
boot_iwe63 = resetn;
boot_dwe63 = resetn;
boot_iwe64 = resetn;
boot_dwe64 = resetn;
boot_iwe65 = resetn;
boot_dwe65 = resetn;
boot_iwe66 = resetn;
boot_dwe66 = resetn;
boot_iwe67 = resetn;
boot_dwe67 = resetn;
boot_iwe68 = resetn;
boot_dwe68 = resetn;
boot_iwe69 = resetn;
boot_dwe69 = resetn;
boot_iwe70 = resetn;
boot_dwe70 = resetn;
boot_iwe71 = resetn;
boot_dwe71 = resetn;
boot_iwe72 = resetn;
boot_dwe72 = resetn;
boot_iwe73 = resetn;
boot_dwe73 = resetn;
boot_iwe74 = resetn;
boot_dwe74 = resetn;
boot_iwe75 = resetn;
boot_dwe75 = resetn;
boot_iwe76 = resetn;
boot_dwe76 = resetn;
boot_iwe77 = resetn;
boot_dwe77 = resetn;
boot_iwe78 = resetn;
boot_dwe78 = resetn;
boot_iwe79 = resetn;
boot_dwe79 = resetn;
boot_iwe80 = resetn;
boot_dwe80 = resetn;
boot_iwe81 = resetn;
boot_dwe81 = resetn;
boot_iwe82 = resetn;
boot_dwe82 = resetn;
boot_iwe83 = resetn;
boot_dwe83 = resetn;
boot_iwe84 = resetn;
boot_dwe84 = resetn;
boot_iwe85 = resetn;
boot_dwe85 = resetn;
boot_iwe86 = resetn;
boot_dwe86 = resetn;
boot_iwe87 = resetn;
boot_dwe87 = resetn;
boot_iwe88 = resetn;
boot_dwe88 = resetn;
boot_iwe89 = resetn;
boot_dwe89 = resetn;
end
47: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = ~resetn;
boot_dwe47 = ~resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
boot_iwe50 = resetn;
boot_dwe50 = resetn;
boot_iwe51 = resetn;
boot_dwe51 = resetn;
boot_iwe52 = resetn;
boot_dwe52 = resetn;
boot_iwe53 = resetn;
boot_dwe53 = resetn;
boot_iwe54 = resetn;
boot_dwe54 = resetn;
boot_iwe55 = resetn;
boot_dwe55 = resetn;
boot_iwe56 = resetn;
boot_dwe56 = resetn;
boot_iwe57 = resetn;
boot_dwe57 = resetn;
boot_iwe58 = resetn;
boot_dwe58 = resetn;
boot_iwe59 = resetn;
boot_dwe59 = resetn;
boot_iwe60 = resetn;
boot_dwe60 = resetn;
boot_iwe61 = resetn;
boot_dwe61 = resetn;
boot_iwe62 = resetn;
boot_dwe62 = resetn;
boot_iwe63 = resetn;
boot_dwe63 = resetn;
boot_iwe64 = resetn;
boot_dwe64 = resetn;
boot_iwe65 = resetn;
boot_dwe65 = resetn;
boot_iwe66 = resetn;
boot_dwe66 = resetn;
boot_iwe67 = resetn;
boot_dwe67 = resetn;
boot_iwe68 = resetn;
boot_dwe68 = resetn;
boot_iwe69 = resetn;
boot_dwe69 = resetn;
boot_iwe70 = resetn;
boot_dwe70 = resetn;
boot_iwe71 = resetn;
boot_dwe71 = resetn;
boot_iwe72 = resetn;
boot_dwe72 = resetn;
boot_iwe73 = resetn;
boot_dwe73 = resetn;
boot_iwe74 = resetn;
boot_dwe74 = resetn;
boot_iwe75 = resetn;
boot_dwe75 = resetn;
boot_iwe76 = resetn;
boot_dwe76 = resetn;
boot_iwe77 = resetn;
boot_dwe77 = resetn;
boot_iwe78 = resetn;
boot_dwe78 = resetn;
boot_iwe79 = resetn;
boot_dwe79 = resetn;
boot_iwe80 = resetn;
boot_dwe80 = resetn;
boot_iwe81 = resetn;
boot_dwe81 = resetn;
boot_iwe82 = resetn;
boot_dwe82 = resetn;
boot_iwe83 = resetn;
boot_dwe83 = resetn;
boot_iwe84 = resetn;
boot_dwe84 = resetn;
boot_iwe85 = resetn;
boot_dwe85 = resetn;
boot_iwe86 = resetn;
boot_dwe86 = resetn;
boot_iwe87 = resetn;
boot_dwe87 = resetn;
boot_iwe88 = resetn;
boot_dwe88 = resetn;
boot_iwe89 = resetn;
boot_dwe89 = resetn;
end
48: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = ~resetn;
boot_dwe48 = ~resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
boot_iwe50 = resetn;
boot_dwe50 = resetn;
boot_iwe51 = resetn;
boot_dwe51 = resetn;
boot_iwe52 = resetn;
boot_dwe52 = resetn;
boot_iwe53 = resetn;
boot_dwe53 = resetn;
boot_iwe54 = resetn;
boot_dwe54 = resetn;
boot_iwe55 = resetn;
boot_dwe55 = resetn;
boot_iwe56 = resetn;
boot_dwe56 = resetn;
boot_iwe57 = resetn;
boot_dwe57 = resetn;
boot_iwe58 = resetn;
boot_dwe58 = resetn;
boot_iwe59 = resetn;
boot_dwe59 = resetn;
boot_iwe60 = resetn;
boot_dwe60 = resetn;
boot_iwe61 = resetn;
boot_dwe61 = resetn;
boot_iwe62 = resetn;
boot_dwe62 = resetn;
boot_iwe63 = resetn;
boot_dwe63 = resetn;
boot_iwe64 = resetn;
boot_dwe64 = resetn;
boot_iwe65 = resetn;
boot_dwe65 = resetn;
boot_iwe66 = resetn;
boot_dwe66 = resetn;
boot_iwe67 = resetn;
boot_dwe67 = resetn;
boot_iwe68 = resetn;
boot_dwe68 = resetn;
boot_iwe69 = resetn;
boot_dwe69 = resetn;
boot_iwe70 = resetn;
boot_dwe70 = resetn;
boot_iwe71 = resetn;
boot_dwe71 = resetn;
boot_iwe72 = resetn;
boot_dwe72 = resetn;
boot_iwe73 = resetn;
boot_dwe73 = resetn;
boot_iwe74 = resetn;
boot_dwe74 = resetn;
boot_iwe75 = resetn;
boot_dwe75 = resetn;
boot_iwe76 = resetn;
boot_dwe76 = resetn;
boot_iwe77 = resetn;
boot_dwe77 = resetn;
boot_iwe78 = resetn;
boot_dwe78 = resetn;
boot_iwe79 = resetn;
boot_dwe79 = resetn;
boot_iwe80 = resetn;
boot_dwe80 = resetn;
boot_iwe81 = resetn;
boot_dwe81 = resetn;
boot_iwe82 = resetn;
boot_dwe82 = resetn;
boot_iwe83 = resetn;
boot_dwe83 = resetn;
boot_iwe84 = resetn;
boot_dwe84 = resetn;
boot_iwe85 = resetn;
boot_dwe85 = resetn;
boot_iwe86 = resetn;
boot_dwe86 = resetn;
boot_iwe87 = resetn;
boot_dwe87 = resetn;
boot_iwe88 = resetn;
boot_dwe88 = resetn;
boot_iwe89 = resetn;
boot_dwe89 = resetn;
end
49: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = ~resetn;
boot_dwe49 = ~resetn;
boot_iwe50 = resetn;
boot_dwe50 = resetn;
boot_iwe51 = resetn;
boot_dwe51 = resetn;
boot_iwe52 = resetn;
boot_dwe52 = resetn;
boot_iwe53 = resetn;
boot_dwe53 = resetn;
boot_iwe54 = resetn;
boot_dwe54 = resetn;
boot_iwe55 = resetn;
boot_dwe55 = resetn;
boot_iwe56 = resetn;
boot_dwe56 = resetn;
boot_iwe57 = resetn;
boot_dwe57 = resetn;
boot_iwe58 = resetn;
boot_dwe58 = resetn;
boot_iwe59 = resetn;
boot_dwe59 = resetn;
boot_iwe60 = resetn;
boot_dwe60 = resetn;
boot_iwe61 = resetn;
boot_dwe61 = resetn;
boot_iwe62 = resetn;
boot_dwe62 = resetn;
boot_iwe63 = resetn;
boot_dwe63 = resetn;
boot_iwe64 = resetn;
boot_dwe64 = resetn;
boot_iwe65 = resetn;
boot_dwe65 = resetn;
boot_iwe66 = resetn;
boot_dwe66 = resetn;
boot_iwe67 = resetn;
boot_dwe67 = resetn;
boot_iwe68 = resetn;
boot_dwe68 = resetn;
boot_iwe69 = resetn;
boot_dwe69 = resetn;
boot_iwe70 = resetn;
boot_dwe70 = resetn;
boot_iwe71 = resetn;
boot_dwe71 = resetn;
boot_iwe72 = resetn;
boot_dwe72 = resetn;
boot_iwe73 = resetn;
boot_dwe73 = resetn;
boot_iwe74 = resetn;
boot_dwe74 = resetn;
boot_iwe75 = resetn;
boot_dwe75 = resetn;
boot_iwe76 = resetn;
boot_dwe76 = resetn;
boot_iwe77 = resetn;
boot_dwe77 = resetn;
boot_iwe78 = resetn;
boot_dwe78 = resetn;
boot_iwe79 = resetn;
boot_dwe79 = resetn;
boot_iwe80 = resetn;
boot_dwe80 = resetn;
boot_iwe81 = resetn;
boot_dwe81 = resetn;
boot_iwe82 = resetn;
boot_dwe82 = resetn;
boot_iwe83 = resetn;
boot_dwe83 = resetn;
boot_iwe84 = resetn;
boot_dwe84 = resetn;
boot_iwe85 = resetn;
boot_dwe85 = resetn;
boot_iwe86 = resetn;
boot_dwe86 = resetn;
boot_iwe87 = resetn;
boot_dwe87 = resetn;
boot_iwe88 = resetn;
boot_dwe88 = resetn;
boot_iwe89 = resetn;
boot_dwe89 = resetn;
end
50: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
boot_iwe50 = ~resetn;
boot_dwe50 = ~resetn;
boot_iwe51 = resetn;
boot_dwe51 = resetn;
boot_iwe52 = resetn;
boot_dwe52 = resetn;
boot_iwe53 = resetn;
boot_dwe53 = resetn;
boot_iwe54 = resetn;
boot_dwe54 = resetn;
boot_iwe55 = resetn;
boot_dwe55 = resetn;
boot_iwe56 = resetn;
boot_dwe56 = resetn;
boot_iwe57 = resetn;
boot_dwe57 = resetn;
boot_iwe58 = resetn;
boot_dwe58 = resetn;
boot_iwe59 = resetn;
boot_dwe59 = resetn;
boot_iwe60 = resetn;
boot_dwe60 = resetn;
boot_iwe61 = resetn;
boot_dwe61 = resetn;
boot_iwe62 = resetn;
boot_dwe62 = resetn;
boot_iwe63 = resetn;
boot_dwe63 = resetn;
boot_iwe64 = resetn;
boot_dwe64 = resetn;
boot_iwe65 = resetn;
boot_dwe65 = resetn;
boot_iwe66 = resetn;
boot_dwe66 = resetn;
boot_iwe67 = resetn;
boot_dwe67 = resetn;
boot_iwe68 = resetn;
boot_dwe68 = resetn;
boot_iwe69 = resetn;
boot_dwe69 = resetn;
boot_iwe70 = resetn;
boot_dwe70 = resetn;
boot_iwe71 = resetn;
boot_dwe71 = resetn;
boot_iwe72 = resetn;
boot_dwe72 = resetn;
boot_iwe73 = resetn;
boot_dwe73 = resetn;
boot_iwe74 = resetn;
boot_dwe74 = resetn;
boot_iwe75 = resetn;
boot_dwe75 = resetn;
boot_iwe76 = resetn;
boot_dwe76 = resetn;
boot_iwe77 = resetn;
boot_dwe77 = resetn;
boot_iwe78 = resetn;
boot_dwe78 = resetn;
boot_iwe79 = resetn;
boot_dwe79 = resetn;
boot_iwe80 = resetn;
boot_dwe80 = resetn;
boot_iwe81 = resetn;
boot_dwe81 = resetn;
boot_iwe82 = resetn;
boot_dwe82 = resetn;
boot_iwe83 = resetn;
boot_dwe83 = resetn;
boot_iwe84 = resetn;
boot_dwe84 = resetn;
boot_iwe85 = resetn;
boot_dwe85 = resetn;
boot_iwe86 = resetn;
boot_dwe86 = resetn;
boot_iwe87 = resetn;
boot_dwe87 = resetn;
boot_iwe88 = resetn;
boot_dwe88 = resetn;
boot_iwe89 = resetn;
boot_dwe89 = resetn;
end
51: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
boot_iwe50 = resetn;
boot_dwe50 = resetn;
boot_iwe51 = ~resetn;
boot_dwe51 = ~resetn;
boot_iwe52 = resetn;
boot_dwe52 = resetn;
boot_iwe53 = resetn;
boot_dwe53 = resetn;
boot_iwe54 = resetn;
boot_dwe54 = resetn;
boot_iwe55 = resetn;
boot_dwe55 = resetn;
boot_iwe56 = resetn;
boot_dwe56 = resetn;
boot_iwe57 = resetn;
boot_dwe57 = resetn;
boot_iwe58 = resetn;
boot_dwe58 = resetn;
boot_iwe59 = resetn;
boot_dwe59 = resetn;
boot_iwe60 = resetn;
boot_dwe60 = resetn;
boot_iwe61 = resetn;
boot_dwe61 = resetn;
boot_iwe62 = resetn;
boot_dwe62 = resetn;
boot_iwe63 = resetn;
boot_dwe63 = resetn;
boot_iwe64 = resetn;
boot_dwe64 = resetn;
boot_iwe65 = resetn;
boot_dwe65 = resetn;
boot_iwe66 = resetn;
boot_dwe66 = resetn;
boot_iwe67 = resetn;
boot_dwe67 = resetn;
boot_iwe68 = resetn;
boot_dwe68 = resetn;
boot_iwe69 = resetn;
boot_dwe69 = resetn;
boot_iwe70 = resetn;
boot_dwe70 = resetn;
boot_iwe71 = resetn;
boot_dwe71 = resetn;
boot_iwe72 = resetn;
boot_dwe72 = resetn;
boot_iwe73 = resetn;
boot_dwe73 = resetn;
boot_iwe74 = resetn;
boot_dwe74 = resetn;
boot_iwe75 = resetn;
boot_dwe75 = resetn;
boot_iwe76 = resetn;
boot_dwe76 = resetn;
boot_iwe77 = resetn;
boot_dwe77 = resetn;
boot_iwe78 = resetn;
boot_dwe78 = resetn;
boot_iwe79 = resetn;
boot_dwe79 = resetn;
boot_iwe80 = resetn;
boot_dwe80 = resetn;
boot_iwe81 = resetn;
boot_dwe81 = resetn;
boot_iwe82 = resetn;
boot_dwe82 = resetn;
boot_iwe83 = resetn;
boot_dwe83 = resetn;
boot_iwe84 = resetn;
boot_dwe84 = resetn;
boot_iwe85 = resetn;
boot_dwe85 = resetn;
boot_iwe86 = resetn;
boot_dwe86 = resetn;
boot_iwe87 = resetn;
boot_dwe87 = resetn;
boot_iwe88 = resetn;
boot_dwe88 = resetn;
boot_iwe89 = resetn;
boot_dwe89 = resetn;
end
52: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
boot_iwe50 = resetn;
boot_dwe50 = resetn;
boot_iwe51 = resetn;
boot_dwe51 = resetn;
boot_iwe52 = ~resetn;
boot_dwe52 = ~resetn;
boot_iwe53 = resetn;
boot_dwe53 = resetn;
boot_iwe54 = resetn;
boot_dwe54 = resetn;
boot_iwe55 = resetn;
boot_dwe55 = resetn;
boot_iwe56 = resetn;
boot_dwe56 = resetn;
boot_iwe57 = resetn;
boot_dwe57 = resetn;
boot_iwe58 = resetn;
boot_dwe58 = resetn;
boot_iwe59 = resetn;
boot_dwe59 = resetn;
boot_iwe60 = resetn;
boot_dwe60 = resetn;
boot_iwe61 = resetn;
boot_dwe61 = resetn;
boot_iwe62 = resetn;
boot_dwe62 = resetn;
boot_iwe63 = resetn;
boot_dwe63 = resetn;
boot_iwe64 = resetn;
boot_dwe64 = resetn;
boot_iwe65 = resetn;
boot_dwe65 = resetn;
boot_iwe66 = resetn;
boot_dwe66 = resetn;
boot_iwe67 = resetn;
boot_dwe67 = resetn;
boot_iwe68 = resetn;
boot_dwe68 = resetn;
boot_iwe69 = resetn;
boot_dwe69 = resetn;
boot_iwe70 = resetn;
boot_dwe70 = resetn;
boot_iwe71 = resetn;
boot_dwe71 = resetn;
boot_iwe72 = resetn;
boot_dwe72 = resetn;
boot_iwe73 = resetn;
boot_dwe73 = resetn;
boot_iwe74 = resetn;
boot_dwe74 = resetn;
boot_iwe75 = resetn;
boot_dwe75 = resetn;
boot_iwe76 = resetn;
boot_dwe76 = resetn;
boot_iwe77 = resetn;
boot_dwe77 = resetn;
boot_iwe78 = resetn;
boot_dwe78 = resetn;
boot_iwe79 = resetn;
boot_dwe79 = resetn;
boot_iwe80 = resetn;
boot_dwe80 = resetn;
boot_iwe81 = resetn;
boot_dwe81 = resetn;
boot_iwe82 = resetn;
boot_dwe82 = resetn;
boot_iwe83 = resetn;
boot_dwe83 = resetn;
boot_iwe84 = resetn;
boot_dwe84 = resetn;
boot_iwe85 = resetn;
boot_dwe85 = resetn;
boot_iwe86 = resetn;
boot_dwe86 = resetn;
boot_iwe87 = resetn;
boot_dwe87 = resetn;
boot_iwe88 = resetn;
boot_dwe88 = resetn;
boot_iwe89 = resetn;
boot_dwe89 = resetn;
end
53: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
boot_iwe50 = resetn;
boot_dwe50 = resetn;
boot_iwe51 = resetn;
boot_dwe51 = resetn;
boot_iwe52 = resetn;
boot_dwe52 = resetn;
boot_iwe53 = ~resetn;
boot_dwe53 = ~resetn;
boot_iwe54 = resetn;
boot_dwe54 = resetn;
boot_iwe55 = resetn;
boot_dwe55 = resetn;
boot_iwe56 = resetn;
boot_dwe56 = resetn;
boot_iwe57 = resetn;
boot_dwe57 = resetn;
boot_iwe58 = resetn;
boot_dwe58 = resetn;
boot_iwe59 = resetn;
boot_dwe59 = resetn;
boot_iwe60 = resetn;
boot_dwe60 = resetn;
boot_iwe61 = resetn;
boot_dwe61 = resetn;
boot_iwe62 = resetn;
boot_dwe62 = resetn;
boot_iwe63 = resetn;
boot_dwe63 = resetn;
boot_iwe64 = resetn;
boot_dwe64 = resetn;
boot_iwe65 = resetn;
boot_dwe65 = resetn;
boot_iwe66 = resetn;
boot_dwe66 = resetn;
boot_iwe67 = resetn;
boot_dwe67 = resetn;
boot_iwe68 = resetn;
boot_dwe68 = resetn;
boot_iwe69 = resetn;
boot_dwe69 = resetn;
boot_iwe70 = resetn;
boot_dwe70 = resetn;
boot_iwe71 = resetn;
boot_dwe71 = resetn;
boot_iwe72 = resetn;
boot_dwe72 = resetn;
boot_iwe73 = resetn;
boot_dwe73 = resetn;
boot_iwe74 = resetn;
boot_dwe74 = resetn;
boot_iwe75 = resetn;
boot_dwe75 = resetn;
boot_iwe76 = resetn;
boot_dwe76 = resetn;
boot_iwe77 = resetn;
boot_dwe77 = resetn;
boot_iwe78 = resetn;
boot_dwe78 = resetn;
boot_iwe79 = resetn;
boot_dwe79 = resetn;
boot_iwe80 = resetn;
boot_dwe80 = resetn;
boot_iwe81 = resetn;
boot_dwe81 = resetn;
boot_iwe82 = resetn;
boot_dwe82 = resetn;
boot_iwe83 = resetn;
boot_dwe83 = resetn;
boot_iwe84 = resetn;
boot_dwe84 = resetn;
boot_iwe85 = resetn;
boot_dwe85 = resetn;
boot_iwe86 = resetn;
boot_dwe86 = resetn;
boot_iwe87 = resetn;
boot_dwe87 = resetn;
boot_iwe88 = resetn;
boot_dwe88 = resetn;
boot_iwe89 = resetn;
boot_dwe89 = resetn;
end
54: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
boot_iwe50 = resetn;
boot_dwe50 = resetn;
boot_iwe51 = resetn;
boot_dwe51 = resetn;
boot_iwe52 = resetn;
boot_dwe52 = resetn;
boot_iwe53 = resetn;
boot_dwe53 = resetn;
boot_iwe54 = ~resetn;
boot_dwe54 = ~resetn;
boot_iwe55 = resetn;
boot_dwe55 = resetn;
boot_iwe56 = resetn;
boot_dwe56 = resetn;
boot_iwe57 = resetn;
boot_dwe57 = resetn;
boot_iwe58 = resetn;
boot_dwe58 = resetn;
boot_iwe59 = resetn;
boot_dwe59 = resetn;
boot_iwe60 = resetn;
boot_dwe60 = resetn;
boot_iwe61 = resetn;
boot_dwe61 = resetn;
boot_iwe62 = resetn;
boot_dwe62 = resetn;
boot_iwe63 = resetn;
boot_dwe63 = resetn;
boot_iwe64 = resetn;
boot_dwe64 = resetn;
boot_iwe65 = resetn;
boot_dwe65 = resetn;
boot_iwe66 = resetn;
boot_dwe66 = resetn;
boot_iwe67 = resetn;
boot_dwe67 = resetn;
boot_iwe68 = resetn;
boot_dwe68 = resetn;
boot_iwe69 = resetn;
boot_dwe69 = resetn;
boot_iwe70 = resetn;
boot_dwe70 = resetn;
boot_iwe71 = resetn;
boot_dwe71 = resetn;
boot_iwe72 = resetn;
boot_dwe72 = resetn;
boot_iwe73 = resetn;
boot_dwe73 = resetn;
boot_iwe74 = resetn;
boot_dwe74 = resetn;
boot_iwe75 = resetn;
boot_dwe75 = resetn;
boot_iwe76 = resetn;
boot_dwe76 = resetn;
boot_iwe77 = resetn;
boot_dwe77 = resetn;
boot_iwe78 = resetn;
boot_dwe78 = resetn;
boot_iwe79 = resetn;
boot_dwe79 = resetn;
boot_iwe80 = resetn;
boot_dwe80 = resetn;
boot_iwe81 = resetn;
boot_dwe81 = resetn;
boot_iwe82 = resetn;
boot_dwe82 = resetn;
boot_iwe83 = resetn;
boot_dwe83 = resetn;
boot_iwe84 = resetn;
boot_dwe84 = resetn;
boot_iwe85 = resetn;
boot_dwe85 = resetn;
boot_iwe86 = resetn;
boot_dwe86 = resetn;
boot_iwe87 = resetn;
boot_dwe87 = resetn;
boot_iwe88 = resetn;
boot_dwe88 = resetn;
boot_iwe89 = resetn;
boot_dwe89 = resetn;
end
55: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
boot_iwe50 = resetn;
boot_dwe50 = resetn;
boot_iwe51 = resetn;
boot_dwe51 = resetn;
boot_iwe52 = resetn;
boot_dwe52 = resetn;
boot_iwe53 = resetn;
boot_dwe53 = resetn;
boot_iwe54 = resetn;
boot_dwe54 = resetn;
boot_iwe55 = ~resetn;
boot_dwe55 = ~resetn;
boot_iwe56 = resetn;
boot_dwe56 = resetn;
boot_iwe57 = resetn;
boot_dwe57 = resetn;
boot_iwe58 = resetn;
boot_dwe58 = resetn;
boot_iwe59 = resetn;
boot_dwe59 = resetn;
boot_iwe60 = resetn;
boot_dwe60 = resetn;
boot_iwe61 = resetn;
boot_dwe61 = resetn;
boot_iwe62 = resetn;
boot_dwe62 = resetn;
boot_iwe63 = resetn;
boot_dwe63 = resetn;
boot_iwe64 = resetn;
boot_dwe64 = resetn;
boot_iwe65 = resetn;
boot_dwe65 = resetn;
boot_iwe66 = resetn;
boot_dwe66 = resetn;
boot_iwe67 = resetn;
boot_dwe67 = resetn;
boot_iwe68 = resetn;
boot_dwe68 = resetn;
boot_iwe69 = resetn;
boot_dwe69 = resetn;
boot_iwe70 = resetn;
boot_dwe70 = resetn;
boot_iwe71 = resetn;
boot_dwe71 = resetn;
boot_iwe72 = resetn;
boot_dwe72 = resetn;
boot_iwe73 = resetn;
boot_dwe73 = resetn;
boot_iwe74 = resetn;
boot_dwe74 = resetn;
boot_iwe75 = resetn;
boot_dwe75 = resetn;
boot_iwe76 = resetn;
boot_dwe76 = resetn;
boot_iwe77 = resetn;
boot_dwe77 = resetn;
boot_iwe78 = resetn;
boot_dwe78 = resetn;
boot_iwe79 = resetn;
boot_dwe79 = resetn;
boot_iwe80 = resetn;
boot_dwe80 = resetn;
boot_iwe81 = resetn;
boot_dwe81 = resetn;
boot_iwe82 = resetn;
boot_dwe82 = resetn;
boot_iwe83 = resetn;
boot_dwe83 = resetn;
boot_iwe84 = resetn;
boot_dwe84 = resetn;
boot_iwe85 = resetn;
boot_dwe85 = resetn;
boot_iwe86 = resetn;
boot_dwe86 = resetn;
boot_iwe87 = resetn;
boot_dwe87 = resetn;
boot_iwe88 = resetn;
boot_dwe88 = resetn;
boot_iwe89 = resetn;
boot_dwe89 = resetn;
end
56: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
boot_iwe50 = resetn;
boot_dwe50 = resetn;
boot_iwe51 = resetn;
boot_dwe51 = resetn;
boot_iwe52 = resetn;
boot_dwe52 = resetn;
boot_iwe53 = resetn;
boot_dwe53 = resetn;
boot_iwe54 = resetn;
boot_dwe54 = resetn;
boot_iwe55 = resetn;
boot_dwe55 = resetn;
boot_iwe56 = ~resetn;
boot_dwe56 = ~resetn;
boot_iwe57 = resetn;
boot_dwe57 = resetn;
boot_iwe58 = resetn;
boot_dwe58 = resetn;
boot_iwe59 = resetn;
boot_dwe59 = resetn;
boot_iwe60 = resetn;
boot_dwe60 = resetn;
boot_iwe61 = resetn;
boot_dwe61 = resetn;
boot_iwe62 = resetn;
boot_dwe62 = resetn;
boot_iwe63 = resetn;
boot_dwe63 = resetn;
boot_iwe64 = resetn;
boot_dwe64 = resetn;
boot_iwe65 = resetn;
boot_dwe65 = resetn;
boot_iwe66 = resetn;
boot_dwe66 = resetn;
boot_iwe67 = resetn;
boot_dwe67 = resetn;
boot_iwe68 = resetn;
boot_dwe68 = resetn;
boot_iwe69 = resetn;
boot_dwe69 = resetn;
boot_iwe70 = resetn;
boot_dwe70 = resetn;
boot_iwe71 = resetn;
boot_dwe71 = resetn;
boot_iwe72 = resetn;
boot_dwe72 = resetn;
boot_iwe73 = resetn;
boot_dwe73 = resetn;
boot_iwe74 = resetn;
boot_dwe74 = resetn;
boot_iwe75 = resetn;
boot_dwe75 = resetn;
boot_iwe76 = resetn;
boot_dwe76 = resetn;
boot_iwe77 = resetn;
boot_dwe77 = resetn;
boot_iwe78 = resetn;
boot_dwe78 = resetn;
boot_iwe79 = resetn;
boot_dwe79 = resetn;
boot_iwe80 = resetn;
boot_dwe80 = resetn;
boot_iwe81 = resetn;
boot_dwe81 = resetn;
boot_iwe82 = resetn;
boot_dwe82 = resetn;
boot_iwe83 = resetn;
boot_dwe83 = resetn;
boot_iwe84 = resetn;
boot_dwe84 = resetn;
boot_iwe85 = resetn;
boot_dwe85 = resetn;
boot_iwe86 = resetn;
boot_dwe86 = resetn;
boot_iwe87 = resetn;
boot_dwe87 = resetn;
boot_iwe88 = resetn;
boot_dwe88 = resetn;
boot_iwe89 = resetn;
boot_dwe89 = resetn;
end
57: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
boot_iwe50 = resetn;
boot_dwe50 = resetn;
boot_iwe51 = resetn;
boot_dwe51 = resetn;
boot_iwe52 = resetn;
boot_dwe52 = resetn;
boot_iwe53 = resetn;
boot_dwe53 = resetn;
boot_iwe54 = resetn;
boot_dwe54 = resetn;
boot_iwe55 = resetn;
boot_dwe55 = resetn;
boot_iwe56 = resetn;
boot_dwe56 = resetn;
boot_iwe57 = ~resetn;
boot_dwe57 = ~resetn;
boot_iwe58 = resetn;
boot_dwe58 = resetn;
boot_iwe59 = resetn;
boot_dwe59 = resetn;
boot_iwe60 = resetn;
boot_dwe60 = resetn;
boot_iwe61 = resetn;
boot_dwe61 = resetn;
boot_iwe62 = resetn;
boot_dwe62 = resetn;
boot_iwe63 = resetn;
boot_dwe63 = resetn;
boot_iwe64 = resetn;
boot_dwe64 = resetn;
boot_iwe65 = resetn;
boot_dwe65 = resetn;
boot_iwe66 = resetn;
boot_dwe66 = resetn;
boot_iwe67 = resetn;
boot_dwe67 = resetn;
boot_iwe68 = resetn;
boot_dwe68 = resetn;
boot_iwe69 = resetn;
boot_dwe69 = resetn;
boot_iwe70 = resetn;
boot_dwe70 = resetn;
boot_iwe71 = resetn;
boot_dwe71 = resetn;
boot_iwe72 = resetn;
boot_dwe72 = resetn;
boot_iwe73 = resetn;
boot_dwe73 = resetn;
boot_iwe74 = resetn;
boot_dwe74 = resetn;
boot_iwe75 = resetn;
boot_dwe75 = resetn;
boot_iwe76 = resetn;
boot_dwe76 = resetn;
boot_iwe77 = resetn;
boot_dwe77 = resetn;
boot_iwe78 = resetn;
boot_dwe78 = resetn;
boot_iwe79 = resetn;
boot_dwe79 = resetn;
boot_iwe80 = resetn;
boot_dwe80 = resetn;
boot_iwe81 = resetn;
boot_dwe81 = resetn;
boot_iwe82 = resetn;
boot_dwe82 = resetn;
boot_iwe83 = resetn;
boot_dwe83 = resetn;
boot_iwe84 = resetn;
boot_dwe84 = resetn;
boot_iwe85 = resetn;
boot_dwe85 = resetn;
boot_iwe86 = resetn;
boot_dwe86 = resetn;
boot_iwe87 = resetn;
boot_dwe87 = resetn;
boot_iwe88 = resetn;
boot_dwe88 = resetn;
boot_iwe89 = resetn;
boot_dwe89 = resetn;
end
58: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
boot_iwe50 = resetn;
boot_dwe50 = resetn;
boot_iwe51 = resetn;
boot_dwe51 = resetn;
boot_iwe52 = resetn;
boot_dwe52 = resetn;
boot_iwe53 = resetn;
boot_dwe53 = resetn;
boot_iwe54 = resetn;
boot_dwe54 = resetn;
boot_iwe55 = resetn;
boot_dwe55 = resetn;
boot_iwe56 = resetn;
boot_dwe56 = resetn;
boot_iwe57 = resetn;
boot_dwe57 = resetn;
boot_iwe58 = ~resetn;
boot_dwe58 = ~resetn;
boot_iwe59 = resetn;
boot_dwe59 = resetn;
boot_iwe60 = resetn;
boot_dwe60 = resetn;
boot_iwe61 = resetn;
boot_dwe61 = resetn;
boot_iwe62 = resetn;
boot_dwe62 = resetn;
boot_iwe63 = resetn;
boot_dwe63 = resetn;
boot_iwe64 = resetn;
boot_dwe64 = resetn;
boot_iwe65 = resetn;
boot_dwe65 = resetn;
boot_iwe66 = resetn;
boot_dwe66 = resetn;
boot_iwe67 = resetn;
boot_dwe67 = resetn;
boot_iwe68 = resetn;
boot_dwe68 = resetn;
boot_iwe69 = resetn;
boot_dwe69 = resetn;
boot_iwe70 = resetn;
boot_dwe70 = resetn;
boot_iwe71 = resetn;
boot_dwe71 = resetn;
boot_iwe72 = resetn;
boot_dwe72 = resetn;
boot_iwe73 = resetn;
boot_dwe73 = resetn;
boot_iwe74 = resetn;
boot_dwe74 = resetn;
boot_iwe75 = resetn;
boot_dwe75 = resetn;
boot_iwe76 = resetn;
boot_dwe76 = resetn;
boot_iwe77 = resetn;
boot_dwe77 = resetn;
boot_iwe78 = resetn;
boot_dwe78 = resetn;
boot_iwe79 = resetn;
boot_dwe79 = resetn;
boot_iwe80 = resetn;
boot_dwe80 = resetn;
boot_iwe81 = resetn;
boot_dwe81 = resetn;
boot_iwe82 = resetn;
boot_dwe82 = resetn;
boot_iwe83 = resetn;
boot_dwe83 = resetn;
boot_iwe84 = resetn;
boot_dwe84 = resetn;
boot_iwe85 = resetn;
boot_dwe85 = resetn;
boot_iwe86 = resetn;
boot_dwe86 = resetn;
boot_iwe87 = resetn;
boot_dwe87 = resetn;
boot_iwe88 = resetn;
boot_dwe88 = resetn;
boot_iwe89 = resetn;
boot_dwe89 = resetn;
end
59: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
boot_iwe50 = resetn;
boot_dwe50 = resetn;
boot_iwe51 = resetn;
boot_dwe51 = resetn;
boot_iwe52 = resetn;
boot_dwe52 = resetn;
boot_iwe53 = resetn;
boot_dwe53 = resetn;
boot_iwe54 = resetn;
boot_dwe54 = resetn;
boot_iwe55 = resetn;
boot_dwe55 = resetn;
boot_iwe56 = resetn;
boot_dwe56 = resetn;
boot_iwe57 = resetn;
boot_dwe57 = resetn;
boot_iwe58 = resetn;
boot_dwe58 = resetn;
boot_iwe59 = ~resetn;
boot_dwe59 = ~resetn;
boot_iwe60 = resetn;
boot_dwe60 = resetn;
boot_iwe61 = resetn;
boot_dwe61 = resetn;
boot_iwe62 = resetn;
boot_dwe62 = resetn;
boot_iwe63 = resetn;
boot_dwe63 = resetn;
boot_iwe64 = resetn;
boot_dwe64 = resetn;
boot_iwe65 = resetn;
boot_dwe65 = resetn;
boot_iwe66 = resetn;
boot_dwe66 = resetn;
boot_iwe67 = resetn;
boot_dwe67 = resetn;
boot_iwe68 = resetn;
boot_dwe68 = resetn;
boot_iwe69 = resetn;
boot_dwe69 = resetn;
boot_iwe70 = resetn;
boot_dwe70 = resetn;
boot_iwe71 = resetn;
boot_dwe71 = resetn;
boot_iwe72 = resetn;
boot_dwe72 = resetn;
boot_iwe73 = resetn;
boot_dwe73 = resetn;
boot_iwe74 = resetn;
boot_dwe74 = resetn;
boot_iwe75 = resetn;
boot_dwe75 = resetn;
boot_iwe76 = resetn;
boot_dwe76 = resetn;
boot_iwe77 = resetn;
boot_dwe77 = resetn;
boot_iwe78 = resetn;
boot_dwe78 = resetn;
boot_iwe79 = resetn;
boot_dwe79 = resetn;
boot_iwe80 = resetn;
boot_dwe80 = resetn;
boot_iwe81 = resetn;
boot_dwe81 = resetn;
boot_iwe82 = resetn;
boot_dwe82 = resetn;
boot_iwe83 = resetn;
boot_dwe83 = resetn;
boot_iwe84 = resetn;
boot_dwe84 = resetn;
boot_iwe85 = resetn;
boot_dwe85 = resetn;
boot_iwe86 = resetn;
boot_dwe86 = resetn;
boot_iwe87 = resetn;
boot_dwe87 = resetn;
boot_iwe88 = resetn;
boot_dwe88 = resetn;
boot_iwe89 = resetn;
boot_dwe89 = resetn;
end
60: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
boot_iwe50 = resetn;
boot_dwe50 = resetn;
boot_iwe51 = resetn;
boot_dwe51 = resetn;
boot_iwe52 = resetn;
boot_dwe52 = resetn;
boot_iwe53 = resetn;
boot_dwe53 = resetn;
boot_iwe54 = resetn;
boot_dwe54 = resetn;
boot_iwe55 = resetn;
boot_dwe55 = resetn;
boot_iwe56 = resetn;
boot_dwe56 = resetn;
boot_iwe57 = resetn;
boot_dwe57 = resetn;
boot_iwe58 = resetn;
boot_dwe58 = resetn;
boot_iwe59 = resetn;
boot_dwe59 = resetn;
boot_iwe60 = ~resetn;
boot_dwe60 = ~resetn;
boot_iwe61 = resetn;
boot_dwe61 = resetn;
boot_iwe62 = resetn;
boot_dwe62 = resetn;
boot_iwe63 = resetn;
boot_dwe63 = resetn;
boot_iwe64 = resetn;
boot_dwe64 = resetn;
boot_iwe65 = resetn;
boot_dwe65 = resetn;
boot_iwe66 = resetn;
boot_dwe66 = resetn;
boot_iwe67 = resetn;
boot_dwe67 = resetn;
boot_iwe68 = resetn;
boot_dwe68 = resetn;
boot_iwe69 = resetn;
boot_dwe69 = resetn;
boot_iwe70 = resetn;
boot_dwe70 = resetn;
boot_iwe71 = resetn;
boot_dwe71 = resetn;
boot_iwe72 = resetn;
boot_dwe72 = resetn;
boot_iwe73 = resetn;
boot_dwe73 = resetn;
boot_iwe74 = resetn;
boot_dwe74 = resetn;
boot_iwe75 = resetn;
boot_dwe75 = resetn;
boot_iwe76 = resetn;
boot_dwe76 = resetn;
boot_iwe77 = resetn;
boot_dwe77 = resetn;
boot_iwe78 = resetn;
boot_dwe78 = resetn;
boot_iwe79 = resetn;
boot_dwe79 = resetn;
boot_iwe80 = resetn;
boot_dwe80 = resetn;
boot_iwe81 = resetn;
boot_dwe81 = resetn;
boot_iwe82 = resetn;
boot_dwe82 = resetn;
boot_iwe83 = resetn;
boot_dwe83 = resetn;
boot_iwe84 = resetn;
boot_dwe84 = resetn;
boot_iwe85 = resetn;
boot_dwe85 = resetn;
boot_iwe86 = resetn;
boot_dwe86 = resetn;
boot_iwe87 = resetn;
boot_dwe87 = resetn;
boot_iwe88 = resetn;
boot_dwe88 = resetn;
boot_iwe89 = resetn;
boot_dwe89 = resetn;
end
61: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
boot_iwe50 = resetn;
boot_dwe50 = resetn;
boot_iwe51 = resetn;
boot_dwe51 = resetn;
boot_iwe52 = resetn;
boot_dwe52 = resetn;
boot_iwe53 = resetn;
boot_dwe53 = resetn;
boot_iwe54 = resetn;
boot_dwe54 = resetn;
boot_iwe55 = resetn;
boot_dwe55 = resetn;
boot_iwe56 = resetn;
boot_dwe56 = resetn;
boot_iwe57 = resetn;
boot_dwe57 = resetn;
boot_iwe58 = resetn;
boot_dwe58 = resetn;
boot_iwe59 = resetn;
boot_dwe59 = resetn;
boot_iwe60 = resetn;
boot_dwe60 = resetn;
boot_iwe61 = ~resetn;
boot_dwe61 = ~resetn;
boot_iwe62 = resetn;
boot_dwe62 = resetn;
boot_iwe63 = resetn;
boot_dwe63 = resetn;
boot_iwe64 = resetn;
boot_dwe64 = resetn;
boot_iwe65 = resetn;
boot_dwe65 = resetn;
boot_iwe66 = resetn;
boot_dwe66 = resetn;
boot_iwe67 = resetn;
boot_dwe67 = resetn;
boot_iwe68 = resetn;
boot_dwe68 = resetn;
boot_iwe69 = resetn;
boot_dwe69 = resetn;
boot_iwe70 = resetn;
boot_dwe70 = resetn;
boot_iwe71 = resetn;
boot_dwe71 = resetn;
boot_iwe72 = resetn;
boot_dwe72 = resetn;
boot_iwe73 = resetn;
boot_dwe73 = resetn;
boot_iwe74 = resetn;
boot_dwe74 = resetn;
boot_iwe75 = resetn;
boot_dwe75 = resetn;
boot_iwe76 = resetn;
boot_dwe76 = resetn;
boot_iwe77 = resetn;
boot_dwe77 = resetn;
boot_iwe78 = resetn;
boot_dwe78 = resetn;
boot_iwe79 = resetn;
boot_dwe79 = resetn;
boot_iwe80 = resetn;
boot_dwe80 = resetn;
boot_iwe81 = resetn;
boot_dwe81 = resetn;
boot_iwe82 = resetn;
boot_dwe82 = resetn;
boot_iwe83 = resetn;
boot_dwe83 = resetn;
boot_iwe84 = resetn;
boot_dwe84 = resetn;
boot_iwe85 = resetn;
boot_dwe85 = resetn;
boot_iwe86 = resetn;
boot_dwe86 = resetn;
boot_iwe87 = resetn;
boot_dwe87 = resetn;
boot_iwe88 = resetn;
boot_dwe88 = resetn;
boot_iwe89 = resetn;
boot_dwe89 = resetn;
end
62: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
boot_iwe50 = resetn;
boot_dwe50 = resetn;
boot_iwe51 = resetn;
boot_dwe51 = resetn;
boot_iwe52 = resetn;
boot_dwe52 = resetn;
boot_iwe53 = resetn;
boot_dwe53 = resetn;
boot_iwe54 = resetn;
boot_dwe54 = resetn;
boot_iwe55 = resetn;
boot_dwe55 = resetn;
boot_iwe56 = resetn;
boot_dwe56 = resetn;
boot_iwe57 = resetn;
boot_dwe57 = resetn;
boot_iwe58 = resetn;
boot_dwe58 = resetn;
boot_iwe59 = resetn;
boot_dwe59 = resetn;
boot_iwe60 = resetn;
boot_dwe60 = resetn;
boot_iwe61 = resetn;
boot_dwe61 = resetn;
boot_iwe62 = ~resetn;
boot_dwe62 = ~resetn;
boot_iwe63 = resetn;
boot_dwe63 = resetn;
boot_iwe64 = resetn;
boot_dwe64 = resetn;
boot_iwe65 = resetn;
boot_dwe65 = resetn;
boot_iwe66 = resetn;
boot_dwe66 = resetn;
boot_iwe67 = resetn;
boot_dwe67 = resetn;
boot_iwe68 = resetn;
boot_dwe68 = resetn;
boot_iwe69 = resetn;
boot_dwe69 = resetn;
boot_iwe70 = resetn;
boot_dwe70 = resetn;
boot_iwe71 = resetn;
boot_dwe71 = resetn;
boot_iwe72 = resetn;
boot_dwe72 = resetn;
boot_iwe73 = resetn;
boot_dwe73 = resetn;
boot_iwe74 = resetn;
boot_dwe74 = resetn;
boot_iwe75 = resetn;
boot_dwe75 = resetn;
boot_iwe76 = resetn;
boot_dwe76 = resetn;
boot_iwe77 = resetn;
boot_dwe77 = resetn;
boot_iwe78 = resetn;
boot_dwe78 = resetn;
boot_iwe79 = resetn;
boot_dwe79 = resetn;
boot_iwe80 = resetn;
boot_dwe80 = resetn;
boot_iwe81 = resetn;
boot_dwe81 = resetn;
boot_iwe82 = resetn;
boot_dwe82 = resetn;
boot_iwe83 = resetn;
boot_dwe83 = resetn;
boot_iwe84 = resetn;
boot_dwe84 = resetn;
boot_iwe85 = resetn;
boot_dwe85 = resetn;
boot_iwe86 = resetn;
boot_dwe86 = resetn;
boot_iwe87 = resetn;
boot_dwe87 = resetn;
boot_iwe88 = resetn;
boot_dwe88 = resetn;
boot_iwe89 = resetn;
boot_dwe89 = resetn;
end
63: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
boot_iwe50 = resetn;
boot_dwe50 = resetn;
boot_iwe51 = resetn;
boot_dwe51 = resetn;
boot_iwe52 = resetn;
boot_dwe52 = resetn;
boot_iwe53 = resetn;
boot_dwe53 = resetn;
boot_iwe54 = resetn;
boot_dwe54 = resetn;
boot_iwe55 = resetn;
boot_dwe55 = resetn;
boot_iwe56 = resetn;
boot_dwe56 = resetn;
boot_iwe57 = resetn;
boot_dwe57 = resetn;
boot_iwe58 = resetn;
boot_dwe58 = resetn;
boot_iwe59 = resetn;
boot_dwe59 = resetn;
boot_iwe60 = resetn;
boot_dwe60 = resetn;
boot_iwe61 = resetn;
boot_dwe61 = resetn;
boot_iwe62 = resetn;
boot_dwe62 = resetn;
boot_iwe63 = ~resetn;
boot_dwe63 = ~resetn;
boot_iwe64 = resetn;
boot_dwe64 = resetn;
boot_iwe65 = resetn;
boot_dwe65 = resetn;
boot_iwe66 = resetn;
boot_dwe66 = resetn;
boot_iwe67 = resetn;
boot_dwe67 = resetn;
boot_iwe68 = resetn;
boot_dwe68 = resetn;
boot_iwe69 = resetn;
boot_dwe69 = resetn;
boot_iwe70 = resetn;
boot_dwe70 = resetn;
boot_iwe71 = resetn;
boot_dwe71 = resetn;
boot_iwe72 = resetn;
boot_dwe72 = resetn;
boot_iwe73 = resetn;
boot_dwe73 = resetn;
boot_iwe74 = resetn;
boot_dwe74 = resetn;
boot_iwe75 = resetn;
boot_dwe75 = resetn;
boot_iwe76 = resetn;
boot_dwe76 = resetn;
boot_iwe77 = resetn;
boot_dwe77 = resetn;
boot_iwe78 = resetn;
boot_dwe78 = resetn;
boot_iwe79 = resetn;
boot_dwe79 = resetn;
boot_iwe80 = resetn;
boot_dwe80 = resetn;
boot_iwe81 = resetn;
boot_dwe81 = resetn;
boot_iwe82 = resetn;
boot_dwe82 = resetn;
boot_iwe83 = resetn;
boot_dwe83 = resetn;
boot_iwe84 = resetn;
boot_dwe84 = resetn;
boot_iwe85 = resetn;
boot_dwe85 = resetn;
boot_iwe86 = resetn;
boot_dwe86 = resetn;
boot_iwe87 = resetn;
boot_dwe87 = resetn;
boot_iwe88 = resetn;
boot_dwe88 = resetn;
boot_iwe89 = resetn;
boot_dwe89 = resetn;
end
64: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
boot_iwe50 = resetn;
boot_dwe50 = resetn;
boot_iwe51 = resetn;
boot_dwe51 = resetn;
boot_iwe52 = resetn;
boot_dwe52 = resetn;
boot_iwe53 = resetn;
boot_dwe53 = resetn;
boot_iwe54 = resetn;
boot_dwe54 = resetn;
boot_iwe55 = resetn;
boot_dwe55 = resetn;
boot_iwe56 = resetn;
boot_dwe56 = resetn;
boot_iwe57 = resetn;
boot_dwe57 = resetn;
boot_iwe58 = resetn;
boot_dwe58 = resetn;
boot_iwe59 = resetn;
boot_dwe59 = resetn;
boot_iwe60 = resetn;
boot_dwe60 = resetn;
boot_iwe61 = resetn;
boot_dwe61 = resetn;
boot_iwe62 = resetn;
boot_dwe62 = resetn;
boot_iwe63 = resetn;
boot_dwe63 = resetn;
boot_iwe64 = ~resetn;
boot_dwe64 = ~resetn;
boot_iwe65 = resetn;
boot_dwe65 = resetn;
boot_iwe66 = resetn;
boot_dwe66 = resetn;
boot_iwe67 = resetn;
boot_dwe67 = resetn;
boot_iwe68 = resetn;
boot_dwe68 = resetn;
boot_iwe69 = resetn;
boot_dwe69 = resetn;
boot_iwe70 = resetn;
boot_dwe70 = resetn;
boot_iwe71 = resetn;
boot_dwe71 = resetn;
boot_iwe72 = resetn;
boot_dwe72 = resetn;
boot_iwe73 = resetn;
boot_dwe73 = resetn;
boot_iwe74 = resetn;
boot_dwe74 = resetn;
boot_iwe75 = resetn;
boot_dwe75 = resetn;
boot_iwe76 = resetn;
boot_dwe76 = resetn;
boot_iwe77 = resetn;
boot_dwe77 = resetn;
boot_iwe78 = resetn;
boot_dwe78 = resetn;
boot_iwe79 = resetn;
boot_dwe79 = resetn;
boot_iwe80 = resetn;
boot_dwe80 = resetn;
boot_iwe81 = resetn;
boot_dwe81 = resetn;
boot_iwe82 = resetn;
boot_dwe82 = resetn;
boot_iwe83 = resetn;
boot_dwe83 = resetn;
boot_iwe84 = resetn;
boot_dwe84 = resetn;
boot_iwe85 = resetn;
boot_dwe85 = resetn;
boot_iwe86 = resetn;
boot_dwe86 = resetn;
boot_iwe87 = resetn;
boot_dwe87 = resetn;
boot_iwe88 = resetn;
boot_dwe88 = resetn;
boot_iwe89 = resetn;
boot_dwe89 = resetn;
end
65: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
boot_iwe50 = resetn;
boot_dwe50 = resetn;
boot_iwe51 = resetn;
boot_dwe51 = resetn;
boot_iwe52 = resetn;
boot_dwe52 = resetn;
boot_iwe53 = resetn;
boot_dwe53 = resetn;
boot_iwe54 = resetn;
boot_dwe54 = resetn;
boot_iwe55 = resetn;
boot_dwe55 = resetn;
boot_iwe56 = resetn;
boot_dwe56 = resetn;
boot_iwe57 = resetn;
boot_dwe57 = resetn;
boot_iwe58 = resetn;
boot_dwe58 = resetn;
boot_iwe59 = resetn;
boot_dwe59 = resetn;
boot_iwe60 = resetn;
boot_dwe60 = resetn;
boot_iwe61 = resetn;
boot_dwe61 = resetn;
boot_iwe62 = resetn;
boot_dwe62 = resetn;
boot_iwe63 = resetn;
boot_dwe63 = resetn;
boot_iwe64 = resetn;
boot_dwe64 = resetn;
boot_iwe65 = ~resetn;
boot_dwe65 = ~resetn;
boot_iwe66 = resetn;
boot_dwe66 = resetn;
boot_iwe67 = resetn;
boot_dwe67 = resetn;
boot_iwe68 = resetn;
boot_dwe68 = resetn;
boot_iwe69 = resetn;
boot_dwe69 = resetn;
boot_iwe70 = resetn;
boot_dwe70 = resetn;
boot_iwe71 = resetn;
boot_dwe71 = resetn;
boot_iwe72 = resetn;
boot_dwe72 = resetn;
boot_iwe73 = resetn;
boot_dwe73 = resetn;
boot_iwe74 = resetn;
boot_dwe74 = resetn;
boot_iwe75 = resetn;
boot_dwe75 = resetn;
boot_iwe76 = resetn;
boot_dwe76 = resetn;
boot_iwe77 = resetn;
boot_dwe77 = resetn;
boot_iwe78 = resetn;
boot_dwe78 = resetn;
boot_iwe79 = resetn;
boot_dwe79 = resetn;
boot_iwe80 = resetn;
boot_dwe80 = resetn;
boot_iwe81 = resetn;
boot_dwe81 = resetn;
boot_iwe82 = resetn;
boot_dwe82 = resetn;
boot_iwe83 = resetn;
boot_dwe83 = resetn;
boot_iwe84 = resetn;
boot_dwe84 = resetn;
boot_iwe85 = resetn;
boot_dwe85 = resetn;
boot_iwe86 = resetn;
boot_dwe86 = resetn;
boot_iwe87 = resetn;
boot_dwe87 = resetn;
boot_iwe88 = resetn;
boot_dwe88 = resetn;
boot_iwe89 = resetn;
boot_dwe89 = resetn;
end
66: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
boot_iwe50 = resetn;
boot_dwe50 = resetn;
boot_iwe51 = resetn;
boot_dwe51 = resetn;
boot_iwe52 = resetn;
boot_dwe52 = resetn;
boot_iwe53 = resetn;
boot_dwe53 = resetn;
boot_iwe54 = resetn;
boot_dwe54 = resetn;
boot_iwe55 = resetn;
boot_dwe55 = resetn;
boot_iwe56 = resetn;
boot_dwe56 = resetn;
boot_iwe57 = resetn;
boot_dwe57 = resetn;
boot_iwe58 = resetn;
boot_dwe58 = resetn;
boot_iwe59 = resetn;
boot_dwe59 = resetn;
boot_iwe60 = resetn;
boot_dwe60 = resetn;
boot_iwe61 = resetn;
boot_dwe61 = resetn;
boot_iwe62 = resetn;
boot_dwe62 = resetn;
boot_iwe63 = resetn;
boot_dwe63 = resetn;
boot_iwe64 = resetn;
boot_dwe64 = resetn;
boot_iwe65 = resetn;
boot_dwe65 = resetn;
boot_iwe66 = ~resetn;
boot_dwe66 = ~resetn;
boot_iwe67 = resetn;
boot_dwe67 = resetn;
boot_iwe68 = resetn;
boot_dwe68 = resetn;
boot_iwe69 = resetn;
boot_dwe69 = resetn;
boot_iwe70 = resetn;
boot_dwe70 = resetn;
boot_iwe71 = resetn;
boot_dwe71 = resetn;
boot_iwe72 = resetn;
boot_dwe72 = resetn;
boot_iwe73 = resetn;
boot_dwe73 = resetn;
boot_iwe74 = resetn;
boot_dwe74 = resetn;
boot_iwe75 = resetn;
boot_dwe75 = resetn;
boot_iwe76 = resetn;
boot_dwe76 = resetn;
boot_iwe77 = resetn;
boot_dwe77 = resetn;
boot_iwe78 = resetn;
boot_dwe78 = resetn;
boot_iwe79 = resetn;
boot_dwe79 = resetn;
boot_iwe80 = resetn;
boot_dwe80 = resetn;
boot_iwe81 = resetn;
boot_dwe81 = resetn;
boot_iwe82 = resetn;
boot_dwe82 = resetn;
boot_iwe83 = resetn;
boot_dwe83 = resetn;
boot_iwe84 = resetn;
boot_dwe84 = resetn;
boot_iwe85 = resetn;
boot_dwe85 = resetn;
boot_iwe86 = resetn;
boot_dwe86 = resetn;
boot_iwe87 = resetn;
boot_dwe87 = resetn;
boot_iwe88 = resetn;
boot_dwe88 = resetn;
boot_iwe89 = resetn;
boot_dwe89 = resetn;
end
67: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
boot_iwe50 = resetn;
boot_dwe50 = resetn;
boot_iwe51 = resetn;
boot_dwe51 = resetn;
boot_iwe52 = resetn;
boot_dwe52 = resetn;
boot_iwe53 = resetn;
boot_dwe53 = resetn;
boot_iwe54 = resetn;
boot_dwe54 = resetn;
boot_iwe55 = resetn;
boot_dwe55 = resetn;
boot_iwe56 = resetn;
boot_dwe56 = resetn;
boot_iwe57 = resetn;
boot_dwe57 = resetn;
boot_iwe58 = resetn;
boot_dwe58 = resetn;
boot_iwe59 = resetn;
boot_dwe59 = resetn;
boot_iwe60 = resetn;
boot_dwe60 = resetn;
boot_iwe61 = resetn;
boot_dwe61 = resetn;
boot_iwe62 = resetn;
boot_dwe62 = resetn;
boot_iwe63 = resetn;
boot_dwe63 = resetn;
boot_iwe64 = resetn;
boot_dwe64 = resetn;
boot_iwe65 = resetn;
boot_dwe65 = resetn;
boot_iwe66 = resetn;
boot_dwe66 = resetn;
boot_iwe67 = ~resetn;
boot_dwe67 = ~resetn;
boot_iwe68 = resetn;
boot_dwe68 = resetn;
boot_iwe69 = resetn;
boot_dwe69 = resetn;
boot_iwe70 = resetn;
boot_dwe70 = resetn;
boot_iwe71 = resetn;
boot_dwe71 = resetn;
boot_iwe72 = resetn;
boot_dwe72 = resetn;
boot_iwe73 = resetn;
boot_dwe73 = resetn;
boot_iwe74 = resetn;
boot_dwe74 = resetn;
boot_iwe75 = resetn;
boot_dwe75 = resetn;
boot_iwe76 = resetn;
boot_dwe76 = resetn;
boot_iwe77 = resetn;
boot_dwe77 = resetn;
boot_iwe78 = resetn;
boot_dwe78 = resetn;
boot_iwe79 = resetn;
boot_dwe79 = resetn;
boot_iwe80 = resetn;
boot_dwe80 = resetn;
boot_iwe81 = resetn;
boot_dwe81 = resetn;
boot_iwe82 = resetn;
boot_dwe82 = resetn;
boot_iwe83 = resetn;
boot_dwe83 = resetn;
boot_iwe84 = resetn;
boot_dwe84 = resetn;
boot_iwe85 = resetn;
boot_dwe85 = resetn;
boot_iwe86 = resetn;
boot_dwe86 = resetn;
boot_iwe87 = resetn;
boot_dwe87 = resetn;
boot_iwe88 = resetn;
boot_dwe88 = resetn;
boot_iwe89 = resetn;
boot_dwe89 = resetn;
end
68: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
boot_iwe50 = resetn;
boot_dwe50 = resetn;
boot_iwe51 = resetn;
boot_dwe51 = resetn;
boot_iwe52 = resetn;
boot_dwe52 = resetn;
boot_iwe53 = resetn;
boot_dwe53 = resetn;
boot_iwe54 = resetn;
boot_dwe54 = resetn;
boot_iwe55 = resetn;
boot_dwe55 = resetn;
boot_iwe56 = resetn;
boot_dwe56 = resetn;
boot_iwe57 = resetn;
boot_dwe57 = resetn;
boot_iwe58 = resetn;
boot_dwe58 = resetn;
boot_iwe59 = resetn;
boot_dwe59 = resetn;
boot_iwe60 = resetn;
boot_dwe60 = resetn;
boot_iwe61 = resetn;
boot_dwe61 = resetn;
boot_iwe62 = resetn;
boot_dwe62 = resetn;
boot_iwe63 = resetn;
boot_dwe63 = resetn;
boot_iwe64 = resetn;
boot_dwe64 = resetn;
boot_iwe65 = resetn;
boot_dwe65 = resetn;
boot_iwe66 = resetn;
boot_dwe66 = resetn;
boot_iwe67 = resetn;
boot_dwe67 = resetn;
boot_iwe68 = ~resetn;
boot_dwe68 = ~resetn;
boot_iwe69 = resetn;
boot_dwe69 = resetn;
boot_iwe70 = resetn;
boot_dwe70 = resetn;
boot_iwe71 = resetn;
boot_dwe71 = resetn;
boot_iwe72 = resetn;
boot_dwe72 = resetn;
boot_iwe73 = resetn;
boot_dwe73 = resetn;
boot_iwe74 = resetn;
boot_dwe74 = resetn;
boot_iwe75 = resetn;
boot_dwe75 = resetn;
boot_iwe76 = resetn;
boot_dwe76 = resetn;
boot_iwe77 = resetn;
boot_dwe77 = resetn;
boot_iwe78 = resetn;
boot_dwe78 = resetn;
boot_iwe79 = resetn;
boot_dwe79 = resetn;
boot_iwe80 = resetn;
boot_dwe80 = resetn;
boot_iwe81 = resetn;
boot_dwe81 = resetn;
boot_iwe82 = resetn;
boot_dwe82 = resetn;
boot_iwe83 = resetn;
boot_dwe83 = resetn;
boot_iwe84 = resetn;
boot_dwe84 = resetn;
boot_iwe85 = resetn;
boot_dwe85 = resetn;
boot_iwe86 = resetn;
boot_dwe86 = resetn;
boot_iwe87 = resetn;
boot_dwe87 = resetn;
boot_iwe88 = resetn;
boot_dwe88 = resetn;
boot_iwe89 = resetn;
boot_dwe89 = resetn;
end
69: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
boot_iwe50 = resetn;
boot_dwe50 = resetn;
boot_iwe51 = resetn;
boot_dwe51 = resetn;
boot_iwe52 = resetn;
boot_dwe52 = resetn;
boot_iwe53 = resetn;
boot_dwe53 = resetn;
boot_iwe54 = resetn;
boot_dwe54 = resetn;
boot_iwe55 = resetn;
boot_dwe55 = resetn;
boot_iwe56 = resetn;
boot_dwe56 = resetn;
boot_iwe57 = resetn;
boot_dwe57 = resetn;
boot_iwe58 = resetn;
boot_dwe58 = resetn;
boot_iwe59 = resetn;
boot_dwe59 = resetn;
boot_iwe60 = resetn;
boot_dwe60 = resetn;
boot_iwe61 = resetn;
boot_dwe61 = resetn;
boot_iwe62 = resetn;
boot_dwe62 = resetn;
boot_iwe63 = resetn;
boot_dwe63 = resetn;
boot_iwe64 = resetn;
boot_dwe64 = resetn;
boot_iwe65 = resetn;
boot_dwe65 = resetn;
boot_iwe66 = resetn;
boot_dwe66 = resetn;
boot_iwe67 = resetn;
boot_dwe67 = resetn;
boot_iwe68 = resetn;
boot_dwe68 = resetn;
boot_iwe69 = ~resetn;
boot_dwe69 = ~resetn;
boot_iwe70 = resetn;
boot_dwe70 = resetn;
boot_iwe71 = resetn;
boot_dwe71 = resetn;
boot_iwe72 = resetn;
boot_dwe72 = resetn;
boot_iwe73 = resetn;
boot_dwe73 = resetn;
boot_iwe74 = resetn;
boot_dwe74 = resetn;
boot_iwe75 = resetn;
boot_dwe75 = resetn;
boot_iwe76 = resetn;
boot_dwe76 = resetn;
boot_iwe77 = resetn;
boot_dwe77 = resetn;
boot_iwe78 = resetn;
boot_dwe78 = resetn;
boot_iwe79 = resetn;
boot_dwe79 = resetn;
boot_iwe80 = resetn;
boot_dwe80 = resetn;
boot_iwe81 = resetn;
boot_dwe81 = resetn;
boot_iwe82 = resetn;
boot_dwe82 = resetn;
boot_iwe83 = resetn;
boot_dwe83 = resetn;
boot_iwe84 = resetn;
boot_dwe84 = resetn;
boot_iwe85 = resetn;
boot_dwe85 = resetn;
boot_iwe86 = resetn;
boot_dwe86 = resetn;
boot_iwe87 = resetn;
boot_dwe87 = resetn;
boot_iwe88 = resetn;
boot_dwe88 = resetn;
boot_iwe89 = resetn;
boot_dwe89 = resetn;
end
70: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
boot_iwe50 = resetn;
boot_dwe50 = resetn;
boot_iwe51 = resetn;
boot_dwe51 = resetn;
boot_iwe52 = resetn;
boot_dwe52 = resetn;
boot_iwe53 = resetn;
boot_dwe53 = resetn;
boot_iwe54 = resetn;
boot_dwe54 = resetn;
boot_iwe55 = resetn;
boot_dwe55 = resetn;
boot_iwe56 = resetn;
boot_dwe56 = resetn;
boot_iwe57 = resetn;
boot_dwe57 = resetn;
boot_iwe58 = resetn;
boot_dwe58 = resetn;
boot_iwe59 = resetn;
boot_dwe59 = resetn;
boot_iwe60 = resetn;
boot_dwe60 = resetn;
boot_iwe61 = resetn;
boot_dwe61 = resetn;
boot_iwe62 = resetn;
boot_dwe62 = resetn;
boot_iwe63 = resetn;
boot_dwe63 = resetn;
boot_iwe64 = resetn;
boot_dwe64 = resetn;
boot_iwe65 = resetn;
boot_dwe65 = resetn;
boot_iwe66 = resetn;
boot_dwe66 = resetn;
boot_iwe67 = resetn;
boot_dwe67 = resetn;
boot_iwe68 = resetn;
boot_dwe68 = resetn;
boot_iwe69 = resetn;
boot_dwe69 = resetn;
boot_iwe70 = ~resetn;
boot_dwe70 = ~resetn;
boot_iwe71 = resetn;
boot_dwe71 = resetn;
boot_iwe72 = resetn;
boot_dwe72 = resetn;
boot_iwe73 = resetn;
boot_dwe73 = resetn;
boot_iwe74 = resetn;
boot_dwe74 = resetn;
boot_iwe75 = resetn;
boot_dwe75 = resetn;
boot_iwe76 = resetn;
boot_dwe76 = resetn;
boot_iwe77 = resetn;
boot_dwe77 = resetn;
boot_iwe78 = resetn;
boot_dwe78 = resetn;
boot_iwe79 = resetn;
boot_dwe79 = resetn;
boot_iwe80 = resetn;
boot_dwe80 = resetn;
boot_iwe81 = resetn;
boot_dwe81 = resetn;
boot_iwe82 = resetn;
boot_dwe82 = resetn;
boot_iwe83 = resetn;
boot_dwe83 = resetn;
boot_iwe84 = resetn;
boot_dwe84 = resetn;
boot_iwe85 = resetn;
boot_dwe85 = resetn;
boot_iwe86 = resetn;
boot_dwe86 = resetn;
boot_iwe87 = resetn;
boot_dwe87 = resetn;
boot_iwe88 = resetn;
boot_dwe88 = resetn;
boot_iwe89 = resetn;
boot_dwe89 = resetn;
end
71: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
boot_iwe50 = resetn;
boot_dwe50 = resetn;
boot_iwe51 = resetn;
boot_dwe51 = resetn;
boot_iwe52 = resetn;
boot_dwe52 = resetn;
boot_iwe53 = resetn;
boot_dwe53 = resetn;
boot_iwe54 = resetn;
boot_dwe54 = resetn;
boot_iwe55 = resetn;
boot_dwe55 = resetn;
boot_iwe56 = resetn;
boot_dwe56 = resetn;
boot_iwe57 = resetn;
boot_dwe57 = resetn;
boot_iwe58 = resetn;
boot_dwe58 = resetn;
boot_iwe59 = resetn;
boot_dwe59 = resetn;
boot_iwe60 = resetn;
boot_dwe60 = resetn;
boot_iwe61 = resetn;
boot_dwe61 = resetn;
boot_iwe62 = resetn;
boot_dwe62 = resetn;
boot_iwe63 = resetn;
boot_dwe63 = resetn;
boot_iwe64 = resetn;
boot_dwe64 = resetn;
boot_iwe65 = resetn;
boot_dwe65 = resetn;
boot_iwe66 = resetn;
boot_dwe66 = resetn;
boot_iwe67 = resetn;
boot_dwe67 = resetn;
boot_iwe68 = resetn;
boot_dwe68 = resetn;
boot_iwe69 = resetn;
boot_dwe69 = resetn;
boot_iwe70 = resetn;
boot_dwe70 = resetn;
boot_iwe71 = ~resetn;
boot_dwe71 = ~resetn;
boot_iwe72 = resetn;
boot_dwe72 = resetn;
boot_iwe73 = resetn;
boot_dwe73 = resetn;
boot_iwe74 = resetn;
boot_dwe74 = resetn;
boot_iwe75 = resetn;
boot_dwe75 = resetn;
boot_iwe76 = resetn;
boot_dwe76 = resetn;
boot_iwe77 = resetn;
boot_dwe77 = resetn;
boot_iwe78 = resetn;
boot_dwe78 = resetn;
boot_iwe79 = resetn;
boot_dwe79 = resetn;
boot_iwe80 = resetn;
boot_dwe80 = resetn;
boot_iwe81 = resetn;
boot_dwe81 = resetn;
boot_iwe82 = resetn;
boot_dwe82 = resetn;
boot_iwe83 = resetn;
boot_dwe83 = resetn;
boot_iwe84 = resetn;
boot_dwe84 = resetn;
boot_iwe85 = resetn;
boot_dwe85 = resetn;
boot_iwe86 = resetn;
boot_dwe86 = resetn;
boot_iwe87 = resetn;
boot_dwe87 = resetn;
boot_iwe88 = resetn;
boot_dwe88 = resetn;
boot_iwe89 = resetn;
boot_dwe89 = resetn;
end
72: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
boot_iwe50 = resetn;
boot_dwe50 = resetn;
boot_iwe51 = resetn;
boot_dwe51 = resetn;
boot_iwe52 = resetn;
boot_dwe52 = resetn;
boot_iwe53 = resetn;
boot_dwe53 = resetn;
boot_iwe54 = resetn;
boot_dwe54 = resetn;
boot_iwe55 = resetn;
boot_dwe55 = resetn;
boot_iwe56 = resetn;
boot_dwe56 = resetn;
boot_iwe57 = resetn;
boot_dwe57 = resetn;
boot_iwe58 = resetn;
boot_dwe58 = resetn;
boot_iwe59 = resetn;
boot_dwe59 = resetn;
boot_iwe60 = resetn;
boot_dwe60 = resetn;
boot_iwe61 = resetn;
boot_dwe61 = resetn;
boot_iwe62 = resetn;
boot_dwe62 = resetn;
boot_iwe63 = resetn;
boot_dwe63 = resetn;
boot_iwe64 = resetn;
boot_dwe64 = resetn;
boot_iwe65 = resetn;
boot_dwe65 = resetn;
boot_iwe66 = resetn;
boot_dwe66 = resetn;
boot_iwe67 = resetn;
boot_dwe67 = resetn;
boot_iwe68 = resetn;
boot_dwe68 = resetn;
boot_iwe69 = resetn;
boot_dwe69 = resetn;
boot_iwe70 = resetn;
boot_dwe70 = resetn;
boot_iwe71 = resetn;
boot_dwe71 = resetn;
boot_iwe72 = ~resetn;
boot_dwe72 = ~resetn;
boot_iwe73 = resetn;
boot_dwe73 = resetn;
boot_iwe74 = resetn;
boot_dwe74 = resetn;
boot_iwe75 = resetn;
boot_dwe75 = resetn;
boot_iwe76 = resetn;
boot_dwe76 = resetn;
boot_iwe77 = resetn;
boot_dwe77 = resetn;
boot_iwe78 = resetn;
boot_dwe78 = resetn;
boot_iwe79 = resetn;
boot_dwe79 = resetn;
boot_iwe80 = resetn;
boot_dwe80 = resetn;
boot_iwe81 = resetn;
boot_dwe81 = resetn;
boot_iwe82 = resetn;
boot_dwe82 = resetn;
boot_iwe83 = resetn;
boot_dwe83 = resetn;
boot_iwe84 = resetn;
boot_dwe84 = resetn;
boot_iwe85 = resetn;
boot_dwe85 = resetn;
boot_iwe86 = resetn;
boot_dwe86 = resetn;
boot_iwe87 = resetn;
boot_dwe87 = resetn;
boot_iwe88 = resetn;
boot_dwe88 = resetn;
boot_iwe89 = resetn;
boot_dwe89 = resetn;
end
73: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
boot_iwe50 = resetn;
boot_dwe50 = resetn;
boot_iwe51 = resetn;
boot_dwe51 = resetn;
boot_iwe52 = resetn;
boot_dwe52 = resetn;
boot_iwe53 = resetn;
boot_dwe53 = resetn;
boot_iwe54 = resetn;
boot_dwe54 = resetn;
boot_iwe55 = resetn;
boot_dwe55 = resetn;
boot_iwe56 = resetn;
boot_dwe56 = resetn;
boot_iwe57 = resetn;
boot_dwe57 = resetn;
boot_iwe58 = resetn;
boot_dwe58 = resetn;
boot_iwe59 = resetn;
boot_dwe59 = resetn;
boot_iwe60 = resetn;
boot_dwe60 = resetn;
boot_iwe61 = resetn;
boot_dwe61 = resetn;
boot_iwe62 = resetn;
boot_dwe62 = resetn;
boot_iwe63 = resetn;
boot_dwe63 = resetn;
boot_iwe64 = resetn;
boot_dwe64 = resetn;
boot_iwe65 = resetn;
boot_dwe65 = resetn;
boot_iwe66 = resetn;
boot_dwe66 = resetn;
boot_iwe67 = resetn;
boot_dwe67 = resetn;
boot_iwe68 = resetn;
boot_dwe68 = resetn;
boot_iwe69 = resetn;
boot_dwe69 = resetn;
boot_iwe70 = resetn;
boot_dwe70 = resetn;
boot_iwe71 = resetn;
boot_dwe71 = resetn;
boot_iwe72 = resetn;
boot_dwe72 = resetn;
boot_iwe73 = ~resetn;
boot_dwe73 = ~resetn;
boot_iwe74 = resetn;
boot_dwe74 = resetn;
boot_iwe75 = resetn;
boot_dwe75 = resetn;
boot_iwe76 = resetn;
boot_dwe76 = resetn;
boot_iwe77 = resetn;
boot_dwe77 = resetn;
boot_iwe78 = resetn;
boot_dwe78 = resetn;
boot_iwe79 = resetn;
boot_dwe79 = resetn;
boot_iwe80 = resetn;
boot_dwe80 = resetn;
boot_iwe81 = resetn;
boot_dwe81 = resetn;
boot_iwe82 = resetn;
boot_dwe82 = resetn;
boot_iwe83 = resetn;
boot_dwe83 = resetn;
boot_iwe84 = resetn;
boot_dwe84 = resetn;
boot_iwe85 = resetn;
boot_dwe85 = resetn;
boot_iwe86 = resetn;
boot_dwe86 = resetn;
boot_iwe87 = resetn;
boot_dwe87 = resetn;
boot_iwe88 = resetn;
boot_dwe88 = resetn;
boot_iwe89 = resetn;
boot_dwe89 = resetn;
end
74: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
boot_iwe50 = resetn;
boot_dwe50 = resetn;
boot_iwe51 = resetn;
boot_dwe51 = resetn;
boot_iwe52 = resetn;
boot_dwe52 = resetn;
boot_iwe53 = resetn;
boot_dwe53 = resetn;
boot_iwe54 = resetn;
boot_dwe54 = resetn;
boot_iwe55 = resetn;
boot_dwe55 = resetn;
boot_iwe56 = resetn;
boot_dwe56 = resetn;
boot_iwe57 = resetn;
boot_dwe57 = resetn;
boot_iwe58 = resetn;
boot_dwe58 = resetn;
boot_iwe59 = resetn;
boot_dwe59 = resetn;
boot_iwe60 = resetn;
boot_dwe60 = resetn;
boot_iwe61 = resetn;
boot_dwe61 = resetn;
boot_iwe62 = resetn;
boot_dwe62 = resetn;
boot_iwe63 = resetn;
boot_dwe63 = resetn;
boot_iwe64 = resetn;
boot_dwe64 = resetn;
boot_iwe65 = resetn;
boot_dwe65 = resetn;
boot_iwe66 = resetn;
boot_dwe66 = resetn;
boot_iwe67 = resetn;
boot_dwe67 = resetn;
boot_iwe68 = resetn;
boot_dwe68 = resetn;
boot_iwe69 = resetn;
boot_dwe69 = resetn;
boot_iwe70 = resetn;
boot_dwe70 = resetn;
boot_iwe71 = resetn;
boot_dwe71 = resetn;
boot_iwe72 = resetn;
boot_dwe72 = resetn;
boot_iwe73 = resetn;
boot_dwe73 = resetn;
boot_iwe74 = ~resetn;
boot_dwe74 = ~resetn;
boot_iwe75 = resetn;
boot_dwe75 = resetn;
boot_iwe76 = resetn;
boot_dwe76 = resetn;
boot_iwe77 = resetn;
boot_dwe77 = resetn;
boot_iwe78 = resetn;
boot_dwe78 = resetn;
boot_iwe79 = resetn;
boot_dwe79 = resetn;
boot_iwe80 = resetn;
boot_dwe80 = resetn;
boot_iwe81 = resetn;
boot_dwe81 = resetn;
boot_iwe82 = resetn;
boot_dwe82 = resetn;
boot_iwe83 = resetn;
boot_dwe83 = resetn;
boot_iwe84 = resetn;
boot_dwe84 = resetn;
boot_iwe85 = resetn;
boot_dwe85 = resetn;
boot_iwe86 = resetn;
boot_dwe86 = resetn;
boot_iwe87 = resetn;
boot_dwe87 = resetn;
boot_iwe88 = resetn;
boot_dwe88 = resetn;
boot_iwe89 = resetn;
boot_dwe89 = resetn;
end
75: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
boot_iwe50 = resetn;
boot_dwe50 = resetn;
boot_iwe51 = resetn;
boot_dwe51 = resetn;
boot_iwe52 = resetn;
boot_dwe52 = resetn;
boot_iwe53 = resetn;
boot_dwe53 = resetn;
boot_iwe54 = resetn;
boot_dwe54 = resetn;
boot_iwe55 = resetn;
boot_dwe55 = resetn;
boot_iwe56 = resetn;
boot_dwe56 = resetn;
boot_iwe57 = resetn;
boot_dwe57 = resetn;
boot_iwe58 = resetn;
boot_dwe58 = resetn;
boot_iwe59 = resetn;
boot_dwe59 = resetn;
boot_iwe60 = resetn;
boot_dwe60 = resetn;
boot_iwe61 = resetn;
boot_dwe61 = resetn;
boot_iwe62 = resetn;
boot_dwe62 = resetn;
boot_iwe63 = resetn;
boot_dwe63 = resetn;
boot_iwe64 = resetn;
boot_dwe64 = resetn;
boot_iwe65 = resetn;
boot_dwe65 = resetn;
boot_iwe66 = resetn;
boot_dwe66 = resetn;
boot_iwe67 = resetn;
boot_dwe67 = resetn;
boot_iwe68 = resetn;
boot_dwe68 = resetn;
boot_iwe69 = resetn;
boot_dwe69 = resetn;
boot_iwe70 = resetn;
boot_dwe70 = resetn;
boot_iwe71 = resetn;
boot_dwe71 = resetn;
boot_iwe72 = resetn;
boot_dwe72 = resetn;
boot_iwe73 = resetn;
boot_dwe73 = resetn;
boot_iwe74 = resetn;
boot_dwe74 = resetn;
boot_iwe75 = ~resetn;
boot_dwe75 = ~resetn;
boot_iwe76 = resetn;
boot_dwe76 = resetn;
boot_iwe77 = resetn;
boot_dwe77 = resetn;
boot_iwe78 = resetn;
boot_dwe78 = resetn;
boot_iwe79 = resetn;
boot_dwe79 = resetn;
boot_iwe80 = resetn;
boot_dwe80 = resetn;
boot_iwe81 = resetn;
boot_dwe81 = resetn;
boot_iwe82 = resetn;
boot_dwe82 = resetn;
boot_iwe83 = resetn;
boot_dwe83 = resetn;
boot_iwe84 = resetn;
boot_dwe84 = resetn;
boot_iwe85 = resetn;
boot_dwe85 = resetn;
boot_iwe86 = resetn;
boot_dwe86 = resetn;
boot_iwe87 = resetn;
boot_dwe87 = resetn;
boot_iwe88 = resetn;
boot_dwe88 = resetn;
boot_iwe89 = resetn;
boot_dwe89 = resetn;
end
76: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
boot_iwe50 = resetn;
boot_dwe50 = resetn;
boot_iwe51 = resetn;
boot_dwe51 = resetn;
boot_iwe52 = resetn;
boot_dwe52 = resetn;
boot_iwe53 = resetn;
boot_dwe53 = resetn;
boot_iwe54 = resetn;
boot_dwe54 = resetn;
boot_iwe55 = resetn;
boot_dwe55 = resetn;
boot_iwe56 = resetn;
boot_dwe56 = resetn;
boot_iwe57 = resetn;
boot_dwe57 = resetn;
boot_iwe58 = resetn;
boot_dwe58 = resetn;
boot_iwe59 = resetn;
boot_dwe59 = resetn;
boot_iwe60 = resetn;
boot_dwe60 = resetn;
boot_iwe61 = resetn;
boot_dwe61 = resetn;
boot_iwe62 = resetn;
boot_dwe62 = resetn;
boot_iwe63 = resetn;
boot_dwe63 = resetn;
boot_iwe64 = resetn;
boot_dwe64 = resetn;
boot_iwe65 = resetn;
boot_dwe65 = resetn;
boot_iwe66 = resetn;
boot_dwe66 = resetn;
boot_iwe67 = resetn;
boot_dwe67 = resetn;
boot_iwe68 = resetn;
boot_dwe68 = resetn;
boot_iwe69 = resetn;
boot_dwe69 = resetn;
boot_iwe70 = resetn;
boot_dwe70 = resetn;
boot_iwe71 = resetn;
boot_dwe71 = resetn;
boot_iwe72 = resetn;
boot_dwe72 = resetn;
boot_iwe73 = resetn;
boot_dwe73 = resetn;
boot_iwe74 = resetn;
boot_dwe74 = resetn;
boot_iwe75 = resetn;
boot_dwe75 = resetn;
boot_iwe76 = ~resetn;
boot_dwe76 = ~resetn;
boot_iwe77 = resetn;
boot_dwe77 = resetn;
boot_iwe78 = resetn;
boot_dwe78 = resetn;
boot_iwe79 = resetn;
boot_dwe79 = resetn;
boot_iwe80 = resetn;
boot_dwe80 = resetn;
boot_iwe81 = resetn;
boot_dwe81 = resetn;
boot_iwe82 = resetn;
boot_dwe82 = resetn;
boot_iwe83 = resetn;
boot_dwe83 = resetn;
boot_iwe84 = resetn;
boot_dwe84 = resetn;
boot_iwe85 = resetn;
boot_dwe85 = resetn;
boot_iwe86 = resetn;
boot_dwe86 = resetn;
boot_iwe87 = resetn;
boot_dwe87 = resetn;
boot_iwe88 = resetn;
boot_dwe88 = resetn;
boot_iwe89 = resetn;
boot_dwe89 = resetn;
end
77: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
boot_iwe50 = resetn;
boot_dwe50 = resetn;
boot_iwe51 = resetn;
boot_dwe51 = resetn;
boot_iwe52 = resetn;
boot_dwe52 = resetn;
boot_iwe53 = resetn;
boot_dwe53 = resetn;
boot_iwe54 = resetn;
boot_dwe54 = resetn;
boot_iwe55 = resetn;
boot_dwe55 = resetn;
boot_iwe56 = resetn;
boot_dwe56 = resetn;
boot_iwe57 = resetn;
boot_dwe57 = resetn;
boot_iwe58 = resetn;
boot_dwe58 = resetn;
boot_iwe59 = resetn;
boot_dwe59 = resetn;
boot_iwe60 = resetn;
boot_dwe60 = resetn;
boot_iwe61 = resetn;
boot_dwe61 = resetn;
boot_iwe62 = resetn;
boot_dwe62 = resetn;
boot_iwe63 = resetn;
boot_dwe63 = resetn;
boot_iwe64 = resetn;
boot_dwe64 = resetn;
boot_iwe65 = resetn;
boot_dwe65 = resetn;
boot_iwe66 = resetn;
boot_dwe66 = resetn;
boot_iwe67 = resetn;
boot_dwe67 = resetn;
boot_iwe68 = resetn;
boot_dwe68 = resetn;
boot_iwe69 = resetn;
boot_dwe69 = resetn;
boot_iwe70 = resetn;
boot_dwe70 = resetn;
boot_iwe71 = resetn;
boot_dwe71 = resetn;
boot_iwe72 = resetn;
boot_dwe72 = resetn;
boot_iwe73 = resetn;
boot_dwe73 = resetn;
boot_iwe74 = resetn;
boot_dwe74 = resetn;
boot_iwe75 = resetn;
boot_dwe75 = resetn;
boot_iwe76 = resetn;
boot_dwe76 = resetn;
boot_iwe77 = ~resetn;
boot_dwe77 = ~resetn;
boot_iwe78 = resetn;
boot_dwe78 = resetn;
boot_iwe79 = resetn;
boot_dwe79 = resetn;
boot_iwe80 = resetn;
boot_dwe80 = resetn;
boot_iwe81 = resetn;
boot_dwe81 = resetn;
boot_iwe82 = resetn;
boot_dwe82 = resetn;
boot_iwe83 = resetn;
boot_dwe83 = resetn;
boot_iwe84 = resetn;
boot_dwe84 = resetn;
boot_iwe85 = resetn;
boot_dwe85 = resetn;
boot_iwe86 = resetn;
boot_dwe86 = resetn;
boot_iwe87 = resetn;
boot_dwe87 = resetn;
boot_iwe88 = resetn;
boot_dwe88 = resetn;
boot_iwe89 = resetn;
boot_dwe89 = resetn;
end
78: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
boot_iwe50 = resetn;
boot_dwe50 = resetn;
boot_iwe51 = resetn;
boot_dwe51 = resetn;
boot_iwe52 = resetn;
boot_dwe52 = resetn;
boot_iwe53 = resetn;
boot_dwe53 = resetn;
boot_iwe54 = resetn;
boot_dwe54 = resetn;
boot_iwe55 = resetn;
boot_dwe55 = resetn;
boot_iwe56 = resetn;
boot_dwe56 = resetn;
boot_iwe57 = resetn;
boot_dwe57 = resetn;
boot_iwe58 = resetn;
boot_dwe58 = resetn;
boot_iwe59 = resetn;
boot_dwe59 = resetn;
boot_iwe60 = resetn;
boot_dwe60 = resetn;
boot_iwe61 = resetn;
boot_dwe61 = resetn;
boot_iwe62 = resetn;
boot_dwe62 = resetn;
boot_iwe63 = resetn;
boot_dwe63 = resetn;
boot_iwe64 = resetn;
boot_dwe64 = resetn;
boot_iwe65 = resetn;
boot_dwe65 = resetn;
boot_iwe66 = resetn;
boot_dwe66 = resetn;
boot_iwe67 = resetn;
boot_dwe67 = resetn;
boot_iwe68 = resetn;
boot_dwe68 = resetn;
boot_iwe69 = resetn;
boot_dwe69 = resetn;
boot_iwe70 = resetn;
boot_dwe70 = resetn;
boot_iwe71 = resetn;
boot_dwe71 = resetn;
boot_iwe72 = resetn;
boot_dwe72 = resetn;
boot_iwe73 = resetn;
boot_dwe73 = resetn;
boot_iwe74 = resetn;
boot_dwe74 = resetn;
boot_iwe75 = resetn;
boot_dwe75 = resetn;
boot_iwe76 = resetn;
boot_dwe76 = resetn;
boot_iwe77 = resetn;
boot_dwe77 = resetn;
boot_iwe78 = ~resetn;
boot_dwe78 = ~resetn;
boot_iwe79 = resetn;
boot_dwe79 = resetn;
boot_iwe80 = resetn;
boot_dwe80 = resetn;
boot_iwe81 = resetn;
boot_dwe81 = resetn;
boot_iwe82 = resetn;
boot_dwe82 = resetn;
boot_iwe83 = resetn;
boot_dwe83 = resetn;
boot_iwe84 = resetn;
boot_dwe84 = resetn;
boot_iwe85 = resetn;
boot_dwe85 = resetn;
boot_iwe86 = resetn;
boot_dwe86 = resetn;
boot_iwe87 = resetn;
boot_dwe87 = resetn;
boot_iwe88 = resetn;
boot_dwe88 = resetn;
boot_iwe89 = resetn;
boot_dwe89 = resetn;
end
79: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
boot_iwe50 = resetn;
boot_dwe50 = resetn;
boot_iwe51 = resetn;
boot_dwe51 = resetn;
boot_iwe52 = resetn;
boot_dwe52 = resetn;
boot_iwe53 = resetn;
boot_dwe53 = resetn;
boot_iwe54 = resetn;
boot_dwe54 = resetn;
boot_iwe55 = resetn;
boot_dwe55 = resetn;
boot_iwe56 = resetn;
boot_dwe56 = resetn;
boot_iwe57 = resetn;
boot_dwe57 = resetn;
boot_iwe58 = resetn;
boot_dwe58 = resetn;
boot_iwe59 = resetn;
boot_dwe59 = resetn;
boot_iwe60 = resetn;
boot_dwe60 = resetn;
boot_iwe61 = resetn;
boot_dwe61 = resetn;
boot_iwe62 = resetn;
boot_dwe62 = resetn;
boot_iwe63 = resetn;
boot_dwe63 = resetn;
boot_iwe64 = resetn;
boot_dwe64 = resetn;
boot_iwe65 = resetn;
boot_dwe65 = resetn;
boot_iwe66 = resetn;
boot_dwe66 = resetn;
boot_iwe67 = resetn;
boot_dwe67 = resetn;
boot_iwe68 = resetn;
boot_dwe68 = resetn;
boot_iwe69 = resetn;
boot_dwe69 = resetn;
boot_iwe70 = resetn;
boot_dwe70 = resetn;
boot_iwe71 = resetn;
boot_dwe71 = resetn;
boot_iwe72 = resetn;
boot_dwe72 = resetn;
boot_iwe73 = resetn;
boot_dwe73 = resetn;
boot_iwe74 = resetn;
boot_dwe74 = resetn;
boot_iwe75 = resetn;
boot_dwe75 = resetn;
boot_iwe76 = resetn;
boot_dwe76 = resetn;
boot_iwe77 = resetn;
boot_dwe77 = resetn;
boot_iwe78 = resetn;
boot_dwe78 = resetn;
boot_iwe79 = ~resetn;
boot_dwe79 = ~resetn;
boot_iwe80 = resetn;
boot_dwe80 = resetn;
boot_iwe81 = resetn;
boot_dwe81 = resetn;
boot_iwe82 = resetn;
boot_dwe82 = resetn;
boot_iwe83 = resetn;
boot_dwe83 = resetn;
boot_iwe84 = resetn;
boot_dwe84 = resetn;
boot_iwe85 = resetn;
boot_dwe85 = resetn;
boot_iwe86 = resetn;
boot_dwe86 = resetn;
boot_iwe87 = resetn;
boot_dwe87 = resetn;
boot_iwe88 = resetn;
boot_dwe88 = resetn;
boot_iwe89 = resetn;
boot_dwe89 = resetn;
end
80: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
boot_iwe50 = resetn;
boot_dwe50 = resetn;
boot_iwe51 = resetn;
boot_dwe51 = resetn;
boot_iwe52 = resetn;
boot_dwe52 = resetn;
boot_iwe53 = resetn;
boot_dwe53 = resetn;
boot_iwe54 = resetn;
boot_dwe54 = resetn;
boot_iwe55 = resetn;
boot_dwe55 = resetn;
boot_iwe56 = resetn;
boot_dwe56 = resetn;
boot_iwe57 = resetn;
boot_dwe57 = resetn;
boot_iwe58 = resetn;
boot_dwe58 = resetn;
boot_iwe59 = resetn;
boot_dwe59 = resetn;
boot_iwe60 = resetn;
boot_dwe60 = resetn;
boot_iwe61 = resetn;
boot_dwe61 = resetn;
boot_iwe62 = resetn;
boot_dwe62 = resetn;
boot_iwe63 = resetn;
boot_dwe63 = resetn;
boot_iwe64 = resetn;
boot_dwe64 = resetn;
boot_iwe65 = resetn;
boot_dwe65 = resetn;
boot_iwe66 = resetn;
boot_dwe66 = resetn;
boot_iwe67 = resetn;
boot_dwe67 = resetn;
boot_iwe68 = resetn;
boot_dwe68 = resetn;
boot_iwe69 = resetn;
boot_dwe69 = resetn;
boot_iwe70 = resetn;
boot_dwe70 = resetn;
boot_iwe71 = resetn;
boot_dwe71 = resetn;
boot_iwe72 = resetn;
boot_dwe72 = resetn;
boot_iwe73 = resetn;
boot_dwe73 = resetn;
boot_iwe74 = resetn;
boot_dwe74 = resetn;
boot_iwe75 = resetn;
boot_dwe75 = resetn;
boot_iwe76 = resetn;
boot_dwe76 = resetn;
boot_iwe77 = resetn;
boot_dwe77 = resetn;
boot_iwe78 = resetn;
boot_dwe78 = resetn;
boot_iwe79 = resetn;
boot_dwe79 = resetn;
boot_iwe80 = ~resetn;
boot_dwe80 = ~resetn;
boot_iwe81 = resetn;
boot_dwe81 = resetn;
boot_iwe82 = resetn;
boot_dwe82 = resetn;
boot_iwe83 = resetn;
boot_dwe83 = resetn;
boot_iwe84 = resetn;
boot_dwe84 = resetn;
boot_iwe85 = resetn;
boot_dwe85 = resetn;
boot_iwe86 = resetn;
boot_dwe86 = resetn;
boot_iwe87 = resetn;
boot_dwe87 = resetn;
boot_iwe88 = resetn;
boot_dwe88 = resetn;
boot_iwe89 = resetn;
boot_dwe89 = resetn;
end
81: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
boot_iwe50 = resetn;
boot_dwe50 = resetn;
boot_iwe51 = resetn;
boot_dwe51 = resetn;
boot_iwe52 = resetn;
boot_dwe52 = resetn;
boot_iwe53 = resetn;
boot_dwe53 = resetn;
boot_iwe54 = resetn;
boot_dwe54 = resetn;
boot_iwe55 = resetn;
boot_dwe55 = resetn;
boot_iwe56 = resetn;
boot_dwe56 = resetn;
boot_iwe57 = resetn;
boot_dwe57 = resetn;
boot_iwe58 = resetn;
boot_dwe58 = resetn;
boot_iwe59 = resetn;
boot_dwe59 = resetn;
boot_iwe60 = resetn;
boot_dwe60 = resetn;
boot_iwe61 = resetn;
boot_dwe61 = resetn;
boot_iwe62 = resetn;
boot_dwe62 = resetn;
boot_iwe63 = resetn;
boot_dwe63 = resetn;
boot_iwe64 = resetn;
boot_dwe64 = resetn;
boot_iwe65 = resetn;
boot_dwe65 = resetn;
boot_iwe66 = resetn;
boot_dwe66 = resetn;
boot_iwe67 = resetn;
boot_dwe67 = resetn;
boot_iwe68 = resetn;
boot_dwe68 = resetn;
boot_iwe69 = resetn;
boot_dwe69 = resetn;
boot_iwe70 = resetn;
boot_dwe70 = resetn;
boot_iwe71 = resetn;
boot_dwe71 = resetn;
boot_iwe72 = resetn;
boot_dwe72 = resetn;
boot_iwe73 = resetn;
boot_dwe73 = resetn;
boot_iwe74 = resetn;
boot_dwe74 = resetn;
boot_iwe75 = resetn;
boot_dwe75 = resetn;
boot_iwe76 = resetn;
boot_dwe76 = resetn;
boot_iwe77 = resetn;
boot_dwe77 = resetn;
boot_iwe78 = resetn;
boot_dwe78 = resetn;
boot_iwe79 = resetn;
boot_dwe79 = resetn;
boot_iwe80 = resetn;
boot_dwe80 = resetn;
boot_iwe81 = ~resetn;
boot_dwe81 = ~resetn;
boot_iwe82 = resetn;
boot_dwe82 = resetn;
boot_iwe83 = resetn;
boot_dwe83 = resetn;
boot_iwe84 = resetn;
boot_dwe84 = resetn;
boot_iwe85 = resetn;
boot_dwe85 = resetn;
boot_iwe86 = resetn;
boot_dwe86 = resetn;
boot_iwe87 = resetn;
boot_dwe87 = resetn;
boot_iwe88 = resetn;
boot_dwe88 = resetn;
boot_iwe89 = resetn;
boot_dwe89 = resetn;
end
82: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
boot_iwe50 = resetn;
boot_dwe50 = resetn;
boot_iwe51 = resetn;
boot_dwe51 = resetn;
boot_iwe52 = resetn;
boot_dwe52 = resetn;
boot_iwe53 = resetn;
boot_dwe53 = resetn;
boot_iwe54 = resetn;
boot_dwe54 = resetn;
boot_iwe55 = resetn;
boot_dwe55 = resetn;
boot_iwe56 = resetn;
boot_dwe56 = resetn;
boot_iwe57 = resetn;
boot_dwe57 = resetn;
boot_iwe58 = resetn;
boot_dwe58 = resetn;
boot_iwe59 = resetn;
boot_dwe59 = resetn;
boot_iwe60 = resetn;
boot_dwe60 = resetn;
boot_iwe61 = resetn;
boot_dwe61 = resetn;
boot_iwe62 = resetn;
boot_dwe62 = resetn;
boot_iwe63 = resetn;
boot_dwe63 = resetn;
boot_iwe64 = resetn;
boot_dwe64 = resetn;
boot_iwe65 = resetn;
boot_dwe65 = resetn;
boot_iwe66 = resetn;
boot_dwe66 = resetn;
boot_iwe67 = resetn;
boot_dwe67 = resetn;
boot_iwe68 = resetn;
boot_dwe68 = resetn;
boot_iwe69 = resetn;
boot_dwe69 = resetn;
boot_iwe70 = resetn;
boot_dwe70 = resetn;
boot_iwe71 = resetn;
boot_dwe71 = resetn;
boot_iwe72 = resetn;
boot_dwe72 = resetn;
boot_iwe73 = resetn;
boot_dwe73 = resetn;
boot_iwe74 = resetn;
boot_dwe74 = resetn;
boot_iwe75 = resetn;
boot_dwe75 = resetn;
boot_iwe76 = resetn;
boot_dwe76 = resetn;
boot_iwe77 = resetn;
boot_dwe77 = resetn;
boot_iwe78 = resetn;
boot_dwe78 = resetn;
boot_iwe79 = resetn;
boot_dwe79 = resetn;
boot_iwe80 = resetn;
boot_dwe80 = resetn;
boot_iwe81 = resetn;
boot_dwe81 = resetn;
boot_iwe82 = ~resetn;
boot_dwe82 = ~resetn;
boot_iwe83 = resetn;
boot_dwe83 = resetn;
boot_iwe84 = resetn;
boot_dwe84 = resetn;
boot_iwe85 = resetn;
boot_dwe85 = resetn;
boot_iwe86 = resetn;
boot_dwe86 = resetn;
boot_iwe87 = resetn;
boot_dwe87 = resetn;
boot_iwe88 = resetn;
boot_dwe88 = resetn;
boot_iwe89 = resetn;
boot_dwe89 = resetn;
end
83: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
boot_iwe50 = resetn;
boot_dwe50 = resetn;
boot_iwe51 = resetn;
boot_dwe51 = resetn;
boot_iwe52 = resetn;
boot_dwe52 = resetn;
boot_iwe53 = resetn;
boot_dwe53 = resetn;
boot_iwe54 = resetn;
boot_dwe54 = resetn;
boot_iwe55 = resetn;
boot_dwe55 = resetn;
boot_iwe56 = resetn;
boot_dwe56 = resetn;
boot_iwe57 = resetn;
boot_dwe57 = resetn;
boot_iwe58 = resetn;
boot_dwe58 = resetn;
boot_iwe59 = resetn;
boot_dwe59 = resetn;
boot_iwe60 = resetn;
boot_dwe60 = resetn;
boot_iwe61 = resetn;
boot_dwe61 = resetn;
boot_iwe62 = resetn;
boot_dwe62 = resetn;
boot_iwe63 = resetn;
boot_dwe63 = resetn;
boot_iwe64 = resetn;
boot_dwe64 = resetn;
boot_iwe65 = resetn;
boot_dwe65 = resetn;
boot_iwe66 = resetn;
boot_dwe66 = resetn;
boot_iwe67 = resetn;
boot_dwe67 = resetn;
boot_iwe68 = resetn;
boot_dwe68 = resetn;
boot_iwe69 = resetn;
boot_dwe69 = resetn;
boot_iwe70 = resetn;
boot_dwe70 = resetn;
boot_iwe71 = resetn;
boot_dwe71 = resetn;
boot_iwe72 = resetn;
boot_dwe72 = resetn;
boot_iwe73 = resetn;
boot_dwe73 = resetn;
boot_iwe74 = resetn;
boot_dwe74 = resetn;
boot_iwe75 = resetn;
boot_dwe75 = resetn;
boot_iwe76 = resetn;
boot_dwe76 = resetn;
boot_iwe77 = resetn;
boot_dwe77 = resetn;
boot_iwe78 = resetn;
boot_dwe78 = resetn;
boot_iwe79 = resetn;
boot_dwe79 = resetn;
boot_iwe80 = resetn;
boot_dwe80 = resetn;
boot_iwe81 = resetn;
boot_dwe81 = resetn;
boot_iwe82 = resetn;
boot_dwe82 = resetn;
boot_iwe83 = ~resetn;
boot_dwe83 = ~resetn;
boot_iwe84 = resetn;
boot_dwe84 = resetn;
boot_iwe85 = resetn;
boot_dwe85 = resetn;
boot_iwe86 = resetn;
boot_dwe86 = resetn;
boot_iwe87 = resetn;
boot_dwe87 = resetn;
boot_iwe88 = resetn;
boot_dwe88 = resetn;
boot_iwe89 = resetn;
boot_dwe89 = resetn;
end
84: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
boot_iwe50 = resetn;
boot_dwe50 = resetn;
boot_iwe51 = resetn;
boot_dwe51 = resetn;
boot_iwe52 = resetn;
boot_dwe52 = resetn;
boot_iwe53 = resetn;
boot_dwe53 = resetn;
boot_iwe54 = resetn;
boot_dwe54 = resetn;
boot_iwe55 = resetn;
boot_dwe55 = resetn;
boot_iwe56 = resetn;
boot_dwe56 = resetn;
boot_iwe57 = resetn;
boot_dwe57 = resetn;
boot_iwe58 = resetn;
boot_dwe58 = resetn;
boot_iwe59 = resetn;
boot_dwe59 = resetn;
boot_iwe60 = resetn;
boot_dwe60 = resetn;
boot_iwe61 = resetn;
boot_dwe61 = resetn;
boot_iwe62 = resetn;
boot_dwe62 = resetn;
boot_iwe63 = resetn;
boot_dwe63 = resetn;
boot_iwe64 = resetn;
boot_dwe64 = resetn;
boot_iwe65 = resetn;
boot_dwe65 = resetn;
boot_iwe66 = resetn;
boot_dwe66 = resetn;
boot_iwe67 = resetn;
boot_dwe67 = resetn;
boot_iwe68 = resetn;
boot_dwe68 = resetn;
boot_iwe69 = resetn;
boot_dwe69 = resetn;
boot_iwe70 = resetn;
boot_dwe70 = resetn;
boot_iwe71 = resetn;
boot_dwe71 = resetn;
boot_iwe72 = resetn;
boot_dwe72 = resetn;
boot_iwe73 = resetn;
boot_dwe73 = resetn;
boot_iwe74 = resetn;
boot_dwe74 = resetn;
boot_iwe75 = resetn;
boot_dwe75 = resetn;
boot_iwe76 = resetn;
boot_dwe76 = resetn;
boot_iwe77 = resetn;
boot_dwe77 = resetn;
boot_iwe78 = resetn;
boot_dwe78 = resetn;
boot_iwe79 = resetn;
boot_dwe79 = resetn;
boot_iwe80 = resetn;
boot_dwe80 = resetn;
boot_iwe81 = resetn;
boot_dwe81 = resetn;
boot_iwe82 = resetn;
boot_dwe82 = resetn;
boot_iwe83 = resetn;
boot_dwe83 = resetn;
boot_iwe84 = ~resetn;
boot_dwe84 = ~resetn;
boot_iwe85 = resetn;
boot_dwe85 = resetn;
boot_iwe86 = resetn;
boot_dwe86 = resetn;
boot_iwe87 = resetn;
boot_dwe87 = resetn;
boot_iwe88 = resetn;
boot_dwe88 = resetn;
boot_iwe89 = resetn;
boot_dwe89 = resetn;
end
85: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
boot_iwe50 = resetn;
boot_dwe50 = resetn;
boot_iwe51 = resetn;
boot_dwe51 = resetn;
boot_iwe52 = resetn;
boot_dwe52 = resetn;
boot_iwe53 = resetn;
boot_dwe53 = resetn;
boot_iwe54 = resetn;
boot_dwe54 = resetn;
boot_iwe55 = resetn;
boot_dwe55 = resetn;
boot_iwe56 = resetn;
boot_dwe56 = resetn;
boot_iwe57 = resetn;
boot_dwe57 = resetn;
boot_iwe58 = resetn;
boot_dwe58 = resetn;
boot_iwe59 = resetn;
boot_dwe59 = resetn;
boot_iwe60 = resetn;
boot_dwe60 = resetn;
boot_iwe61 = resetn;
boot_dwe61 = resetn;
boot_iwe62 = resetn;
boot_dwe62 = resetn;
boot_iwe63 = resetn;
boot_dwe63 = resetn;
boot_iwe64 = resetn;
boot_dwe64 = resetn;
boot_iwe65 = resetn;
boot_dwe65 = resetn;
boot_iwe66 = resetn;
boot_dwe66 = resetn;
boot_iwe67 = resetn;
boot_dwe67 = resetn;
boot_iwe68 = resetn;
boot_dwe68 = resetn;
boot_iwe69 = resetn;
boot_dwe69 = resetn;
boot_iwe70 = resetn;
boot_dwe70 = resetn;
boot_iwe71 = resetn;
boot_dwe71 = resetn;
boot_iwe72 = resetn;
boot_dwe72 = resetn;
boot_iwe73 = resetn;
boot_dwe73 = resetn;
boot_iwe74 = resetn;
boot_dwe74 = resetn;
boot_iwe75 = resetn;
boot_dwe75 = resetn;
boot_iwe76 = resetn;
boot_dwe76 = resetn;
boot_iwe77 = resetn;
boot_dwe77 = resetn;
boot_iwe78 = resetn;
boot_dwe78 = resetn;
boot_iwe79 = resetn;
boot_dwe79 = resetn;
boot_iwe80 = resetn;
boot_dwe80 = resetn;
boot_iwe81 = resetn;
boot_dwe81 = resetn;
boot_iwe82 = resetn;
boot_dwe82 = resetn;
boot_iwe83 = resetn;
boot_dwe83 = resetn;
boot_iwe84 = resetn;
boot_dwe84 = resetn;
boot_iwe85 = ~resetn;
boot_dwe85 = ~resetn;
boot_iwe86 = resetn;
boot_dwe86 = resetn;
boot_iwe87 = resetn;
boot_dwe87 = resetn;
boot_iwe88 = resetn;
boot_dwe88 = resetn;
boot_iwe89 = resetn;
boot_dwe89 = resetn;
end
86: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
boot_iwe50 = resetn;
boot_dwe50 = resetn;
boot_iwe51 = resetn;
boot_dwe51 = resetn;
boot_iwe52 = resetn;
boot_dwe52 = resetn;
boot_iwe53 = resetn;
boot_dwe53 = resetn;
boot_iwe54 = resetn;
boot_dwe54 = resetn;
boot_iwe55 = resetn;
boot_dwe55 = resetn;
boot_iwe56 = resetn;
boot_dwe56 = resetn;
boot_iwe57 = resetn;
boot_dwe57 = resetn;
boot_iwe58 = resetn;
boot_dwe58 = resetn;
boot_iwe59 = resetn;
boot_dwe59 = resetn;
boot_iwe60 = resetn;
boot_dwe60 = resetn;
boot_iwe61 = resetn;
boot_dwe61 = resetn;
boot_iwe62 = resetn;
boot_dwe62 = resetn;
boot_iwe63 = resetn;
boot_dwe63 = resetn;
boot_iwe64 = resetn;
boot_dwe64 = resetn;
boot_iwe65 = resetn;
boot_dwe65 = resetn;
boot_iwe66 = resetn;
boot_dwe66 = resetn;
boot_iwe67 = resetn;
boot_dwe67 = resetn;
boot_iwe68 = resetn;
boot_dwe68 = resetn;
boot_iwe69 = resetn;
boot_dwe69 = resetn;
boot_iwe70 = resetn;
boot_dwe70 = resetn;
boot_iwe71 = resetn;
boot_dwe71 = resetn;
boot_iwe72 = resetn;
boot_dwe72 = resetn;
boot_iwe73 = resetn;
boot_dwe73 = resetn;
boot_iwe74 = resetn;
boot_dwe74 = resetn;
boot_iwe75 = resetn;
boot_dwe75 = resetn;
boot_iwe76 = resetn;
boot_dwe76 = resetn;
boot_iwe77 = resetn;
boot_dwe77 = resetn;
boot_iwe78 = resetn;
boot_dwe78 = resetn;
boot_iwe79 = resetn;
boot_dwe79 = resetn;
boot_iwe80 = resetn;
boot_dwe80 = resetn;
boot_iwe81 = resetn;
boot_dwe81 = resetn;
boot_iwe82 = resetn;
boot_dwe82 = resetn;
boot_iwe83 = resetn;
boot_dwe83 = resetn;
boot_iwe84 = resetn;
boot_dwe84 = resetn;
boot_iwe85 = resetn;
boot_dwe85 = resetn;
boot_iwe86 = ~resetn;
boot_dwe86 = ~resetn;
boot_iwe87 = resetn;
boot_dwe87 = resetn;
boot_iwe88 = resetn;
boot_dwe88 = resetn;
boot_iwe89 = resetn;
boot_dwe89 = resetn;
end
87: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
boot_iwe50 = resetn;
boot_dwe50 = resetn;
boot_iwe51 = resetn;
boot_dwe51 = resetn;
boot_iwe52 = resetn;
boot_dwe52 = resetn;
boot_iwe53 = resetn;
boot_dwe53 = resetn;
boot_iwe54 = resetn;
boot_dwe54 = resetn;
boot_iwe55 = resetn;
boot_dwe55 = resetn;
boot_iwe56 = resetn;
boot_dwe56 = resetn;
boot_iwe57 = resetn;
boot_dwe57 = resetn;
boot_iwe58 = resetn;
boot_dwe58 = resetn;
boot_iwe59 = resetn;
boot_dwe59 = resetn;
boot_iwe60 = resetn;
boot_dwe60 = resetn;
boot_iwe61 = resetn;
boot_dwe61 = resetn;
boot_iwe62 = resetn;
boot_dwe62 = resetn;
boot_iwe63 = resetn;
boot_dwe63 = resetn;
boot_iwe64 = resetn;
boot_dwe64 = resetn;
boot_iwe65 = resetn;
boot_dwe65 = resetn;
boot_iwe66 = resetn;
boot_dwe66 = resetn;
boot_iwe67 = resetn;
boot_dwe67 = resetn;
boot_iwe68 = resetn;
boot_dwe68 = resetn;
boot_iwe69 = resetn;
boot_dwe69 = resetn;
boot_iwe70 = resetn;
boot_dwe70 = resetn;
boot_iwe71 = resetn;
boot_dwe71 = resetn;
boot_iwe72 = resetn;
boot_dwe72 = resetn;
boot_iwe73 = resetn;
boot_dwe73 = resetn;
boot_iwe74 = resetn;
boot_dwe74 = resetn;
boot_iwe75 = resetn;
boot_dwe75 = resetn;
boot_iwe76 = resetn;
boot_dwe76 = resetn;
boot_iwe77 = resetn;
boot_dwe77 = resetn;
boot_iwe78 = resetn;
boot_dwe78 = resetn;
boot_iwe79 = resetn;
boot_dwe79 = resetn;
boot_iwe80 = resetn;
boot_dwe80 = resetn;
boot_iwe81 = resetn;
boot_dwe81 = resetn;
boot_iwe82 = resetn;
boot_dwe82 = resetn;
boot_iwe83 = resetn;
boot_dwe83 = resetn;
boot_iwe84 = resetn;
boot_dwe84 = resetn;
boot_iwe85 = resetn;
boot_dwe85 = resetn;
boot_iwe86 = resetn;
boot_dwe86 = resetn;
boot_iwe87 = ~resetn;
boot_dwe87 = ~resetn;
boot_iwe88 = resetn;
boot_dwe88 = resetn;
boot_iwe89 = resetn;
boot_dwe89 = resetn;
end
88: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
boot_iwe50 = resetn;
boot_dwe50 = resetn;
boot_iwe51 = resetn;
boot_dwe51 = resetn;
boot_iwe52 = resetn;
boot_dwe52 = resetn;
boot_iwe53 = resetn;
boot_dwe53 = resetn;
boot_iwe54 = resetn;
boot_dwe54 = resetn;
boot_iwe55 = resetn;
boot_dwe55 = resetn;
boot_iwe56 = resetn;
boot_dwe56 = resetn;
boot_iwe57 = resetn;
boot_dwe57 = resetn;
boot_iwe58 = resetn;
boot_dwe58 = resetn;
boot_iwe59 = resetn;
boot_dwe59 = resetn;
boot_iwe60 = resetn;
boot_dwe60 = resetn;
boot_iwe61 = resetn;
boot_dwe61 = resetn;
boot_iwe62 = resetn;
boot_dwe62 = resetn;
boot_iwe63 = resetn;
boot_dwe63 = resetn;
boot_iwe64 = resetn;
boot_dwe64 = resetn;
boot_iwe65 = resetn;
boot_dwe65 = resetn;
boot_iwe66 = resetn;
boot_dwe66 = resetn;
boot_iwe67 = resetn;
boot_dwe67 = resetn;
boot_iwe68 = resetn;
boot_dwe68 = resetn;
boot_iwe69 = resetn;
boot_dwe69 = resetn;
boot_iwe70 = resetn;
boot_dwe70 = resetn;
boot_iwe71 = resetn;
boot_dwe71 = resetn;
boot_iwe72 = resetn;
boot_dwe72 = resetn;
boot_iwe73 = resetn;
boot_dwe73 = resetn;
boot_iwe74 = resetn;
boot_dwe74 = resetn;
boot_iwe75 = resetn;
boot_dwe75 = resetn;
boot_iwe76 = resetn;
boot_dwe76 = resetn;
boot_iwe77 = resetn;
boot_dwe77 = resetn;
boot_iwe78 = resetn;
boot_dwe78 = resetn;
boot_iwe79 = resetn;
boot_dwe79 = resetn;
boot_iwe80 = resetn;
boot_dwe80 = resetn;
boot_iwe81 = resetn;
boot_dwe81 = resetn;
boot_iwe82 = resetn;
boot_dwe82 = resetn;
boot_iwe83 = resetn;
boot_dwe83 = resetn;
boot_iwe84 = resetn;
boot_dwe84 = resetn;
boot_iwe85 = resetn;
boot_dwe85 = resetn;
boot_iwe86 = resetn;
boot_dwe86 = resetn;
boot_iwe87 = resetn;
boot_dwe87 = resetn;
boot_iwe88 = ~resetn;
boot_dwe88 = ~resetn;
boot_iwe89 = resetn;
boot_dwe89 = resetn;
end
89: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
boot_iwe50 = resetn;
boot_dwe50 = resetn;
boot_iwe51 = resetn;
boot_dwe51 = resetn;
boot_iwe52 = resetn;
boot_dwe52 = resetn;
boot_iwe53 = resetn;
boot_dwe53 = resetn;
boot_iwe54 = resetn;
boot_dwe54 = resetn;
boot_iwe55 = resetn;
boot_dwe55 = resetn;
boot_iwe56 = resetn;
boot_dwe56 = resetn;
boot_iwe57 = resetn;
boot_dwe57 = resetn;
boot_iwe58 = resetn;
boot_dwe58 = resetn;
boot_iwe59 = resetn;
boot_dwe59 = resetn;
boot_iwe60 = resetn;
boot_dwe60 = resetn;
boot_iwe61 = resetn;
boot_dwe61 = resetn;
boot_iwe62 = resetn;
boot_dwe62 = resetn;
boot_iwe63 = resetn;
boot_dwe63 = resetn;
boot_iwe64 = resetn;
boot_dwe64 = resetn;
boot_iwe65 = resetn;
boot_dwe65 = resetn;
boot_iwe66 = resetn;
boot_dwe66 = resetn;
boot_iwe67 = resetn;
boot_dwe67 = resetn;
boot_iwe68 = resetn;
boot_dwe68 = resetn;
boot_iwe69 = resetn;
boot_dwe69 = resetn;
boot_iwe70 = resetn;
boot_dwe70 = resetn;
boot_iwe71 = resetn;
boot_dwe71 = resetn;
boot_iwe72 = resetn;
boot_dwe72 = resetn;
boot_iwe73 = resetn;
boot_dwe73 = resetn;
boot_iwe74 = resetn;
boot_dwe74 = resetn;
boot_iwe75 = resetn;
boot_dwe75 = resetn;
boot_iwe76 = resetn;
boot_dwe76 = resetn;
boot_iwe77 = resetn;
boot_dwe77 = resetn;
boot_iwe78 = resetn;
boot_dwe78 = resetn;
boot_iwe79 = resetn;
boot_dwe79 = resetn;
boot_iwe80 = resetn;
boot_dwe80 = resetn;
boot_iwe81 = resetn;
boot_dwe81 = resetn;
boot_iwe82 = resetn;
boot_dwe82 = resetn;
boot_iwe83 = resetn;
boot_dwe83 = resetn;
boot_iwe84 = resetn;
boot_dwe84 = resetn;
boot_iwe85 = resetn;
boot_dwe85 = resetn;
boot_iwe86 = resetn;
boot_dwe86 = resetn;
boot_iwe87 = resetn;
boot_dwe87 = resetn;
boot_iwe88 = resetn;
boot_dwe88 = resetn;
boot_iwe89 = ~resetn;
boot_dwe89 = ~resetn;
end
90: begin
boot_iwe0 = 0;
boot_dwe0 = 0;
boot_iwe1 = 0;
boot_dwe1 = 0;
boot_iwe2 = 0;
boot_dwe2 = 0;
boot_iwe3 = 0;
boot_dwe3 = 0;
boot_iwe4 = 0;
boot_dwe4 = 0;
boot_iwe5 = 0;
boot_dwe5 = 0;
boot_iwe6 = 0;
boot_dwe6 = 0;
boot_iwe7 = 0;
boot_dwe7 = 0;
boot_iwe8 = 0;
boot_dwe8 = 0;
boot_iwe9 = 0;
boot_dwe9 = 0;
boot_iwe10 = 0;
boot_dwe10 = 0;
boot_iwe11 = 0;
boot_dwe11 = 0;
boot_iwe12 = 0;
boot_dwe12 = 0;
boot_iwe13 = 0;
boot_dwe13 = 0;
boot_iwe14 = 0;
boot_dwe14 = 0;
boot_iwe15 = 0;
boot_dwe15 = 0;
boot_iwe16 = 0;
boot_dwe16 = 0;
boot_iwe17 = 0;
boot_dwe17 = 0;
boot_iwe18 = 0;
boot_dwe18 = 0;
boot_iwe19 = 0;
boot_dwe19 = 0;
boot_iwe20 = 0;
boot_dwe20 = 0;
boot_iwe21 = 0;
boot_dwe21 = 0;
boot_iwe22 = 0;
boot_dwe22 = 0;
boot_iwe23 = 0;
boot_dwe23 = 0;
boot_iwe24 = 0;
boot_dwe24 = 0;
boot_iwe25 = 0;
boot_dwe25 = 0;
boot_iwe26 = 0;
boot_dwe26 = 0;
boot_iwe27 = 0;
boot_dwe27 = 0;
boot_iwe28 = 0;
boot_dwe28 = 0;
boot_iwe29 = 0;
boot_dwe29 = 0;
boot_iwe30 = 0;
boot_dwe30 = 0;
boot_iwe31 = 0;
boot_dwe31 = 0;
boot_iwe32 = 0;
boot_dwe32 = 0;
boot_iwe33 = 0;
boot_dwe33 = 0;
boot_iwe34 = 0;
boot_dwe34 = 0;
boot_iwe35 = 0;
boot_dwe35 = 0;
boot_iwe36 = 0;
boot_dwe36 = 0;
boot_iwe37 = 0;
boot_dwe37 = 0;
boot_iwe38 = 0;
boot_dwe38 = 0;
boot_iwe39 = 0;
boot_dwe39 = 0;
boot_iwe40 = 0;
boot_dwe40 = 0;
boot_iwe41 = 0;
boot_dwe41 = 0;
boot_iwe42 = 0;
boot_dwe42 = 0;
boot_iwe43 = 0;
boot_dwe43 = 0;
boot_iwe44 = 0;
boot_dwe44 = 0;
boot_iwe45 = 0;
boot_dwe45 = 0;
boot_iwe46 = 0;
boot_dwe46 = 0;
boot_iwe47 = 0;
boot_dwe47 = 0;
boot_iwe48 = 0;
boot_dwe48 = 0;
boot_iwe49 = 0;
boot_dwe49 = 0;
boot_iwe50 = 0;
boot_dwe50 = 0;
boot_iwe51 = 0;
boot_dwe51 = 0;
boot_iwe52 = 0;
boot_dwe52 = 0;
boot_iwe53 = 0;
boot_dwe53 = 0;
boot_iwe54 = 0;
boot_dwe54 = 0;
boot_iwe55 = 0;
boot_dwe55 = 0;
boot_iwe56 = 0;
boot_dwe56 = 0;
boot_iwe57 = 0;
boot_dwe57 = 0;
boot_iwe58 = 0;
boot_dwe58 = 0;
boot_iwe59 = 0;
boot_dwe59 = 0;
boot_iwe60 = 0;
boot_dwe60 = 0;
boot_iwe61 = 0;
boot_dwe61 = 0;
boot_iwe62 = 0;
boot_dwe62 = 0;
boot_iwe63 = 0;
boot_dwe63 = 0;
boot_iwe64 = 0;
boot_dwe64 = 0;
boot_iwe65 = 0;
boot_dwe65 = 0;
boot_iwe66 = 0;
boot_dwe66 = 0;
boot_iwe67 = 0;
boot_dwe67 = 0;
boot_iwe68 = 0;
boot_dwe68 = 0;
boot_iwe69 = 0;
boot_dwe69 = 0;
boot_iwe70 = 0;
boot_dwe70 = 0;
boot_iwe71 = 0;
boot_dwe71 = 0;
boot_iwe72 = 0;
boot_dwe72 = 0;
boot_iwe73 = 0;
boot_dwe73 = 0;
boot_iwe74 = 0;
boot_dwe74 = 0;
boot_iwe75 = 0;
boot_dwe75 = 0;
boot_iwe76 = 0;
boot_dwe76 = 0;
boot_iwe77 = 0;
boot_dwe77 = 0;
boot_iwe78 = 0;
boot_dwe78 = 0;
boot_iwe79 = 0;
boot_dwe79 = 0;
boot_iwe80 = 0;
boot_dwe80 = 0;
boot_iwe81 = 0;
boot_dwe81 = 0;
boot_iwe82 = 0;
boot_dwe82 = 0;
boot_iwe83 = 0;
boot_dwe83 = 0;
boot_iwe84 = 0;
boot_dwe84 = 0;
boot_iwe85 = 0;
boot_dwe85 = 0;
boot_iwe86 = 0;
boot_dwe86 = 0;
boot_iwe87 = 0;
boot_dwe87 = 0;
boot_iwe88 = 0;
boot_dwe88 = 0;
boot_iwe89 = 0;
boot_dwe89 = 0;
end
endcase
end
endmodule |
`define NO_PLI 1
`define TEST_BENCH 1
`timescale 1ms / 10us
module test_bench ;
parameter I_DATAWIDTH=32;
parameter I_ADDRESSWIDTH=16;
parameter I_SIZE=65536;
parameter D_DATAWIDTH=32;
parameter D_BYTEENAWIDTH=4; // usually should be D_DATAWIDTH/8
parameter D_ADDRESSWIDTH=16;
parameter D_SIZE=65536;
reg clk;
reg resetn;
wire [31:0] d_writedataout;
reg [13:0] boot_iaddr;
wire [31:0] boot_idata;
reg [13:0] boot_daddr;
wire [31:0] boot_ddata;
reg [31:0] imem [16383:0];
reg [31:0] dmem [16383:0];
reg [6:0] processor_select;
system90 p
(
.clk (clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.reg_file_b_readdataout (d_writedataout),
.processor_select(processor_select));
/**************** Reset and stimulate clock ********************/
initial
clk = 1'b1;
always
#0.01 clk <= ~clk;
initial
begin
#0 resetn <= 0;
#29700 resetn <= 1;
end
initial // NEW
begin
#0 processor_select = 0;
#0 $readmemh("./app/tile0.instr.rif",imem);
#0 $readmemh("./app/tile0.data.rif",dmem);
#0 boot_iaddr=0;
#0 boot_daddr=0;
#330 processor_select = 1;
#0 $readmemh("./app/tile1.instr.rif",imem);
#0 $readmemh("./app/tile1.data.rif",dmem);
#0 boot_iaddr=0;
#0 boot_daddr=0;
#330 processor_select = 2;
#0 $readmemh("./app/tile2.instr.rif",imem);
#0 $readmemh("./app/tile2.data.rif",dmem);
#0 boot_iaddr=0;
#0 boot_daddr=0;
#330 processor_select = 3;
#0 $readmemh("./app/tile3.instr.rif",imem);
#0 $readmemh("./app/tile3.data.rif",dmem);
#0 boot_iaddr=0;
#0 boot_daddr=0;
#330 processor_select = 4;
#0 $readmemh("./app/tile4.instr.rif",imem);
#0 $readmemh("./app/tile4.data.rif",dmem);
#0 boot_iaddr=0;
#0 boot_daddr=0;
#330 processor_select = 5;
#0 $readmemh("./app/tile5.instr.rif",imem);
#0 $readmemh("./app/tile5.data.rif",dmem);
#0 boot_iaddr=0;
#0 boot_daddr=0;
#330 processor_select = 6;
#0 $readmemh("./app/tile6.instr.rif",imem);
#0 $readmemh("./app/tile6.data.rif",dmem);
#0 boot_iaddr=0;
#0 boot_daddr=0;
#330 processor_select = 7;
#0 $readmemh("./app/tile7.instr.rif",imem);
#0 $readmemh("./app/tile7.data.rif",dmem);
#0 boot_iaddr=0;
#0 boot_daddr=0;
#330 processor_select = 8;
#0 $readmemh("./app/tile8.instr.rif",imem);
#0 $readmemh("./app/tile8.data.rif",dmem);
#0 boot_iaddr=0;
#0 boot_daddr=0;
#330 processor_select = 9;
#0 $readmemh("./app/tile9.instr.rif",imem);
#0 $readmemh("./app/tile9.data.rif",dmem);
#0 boot_iaddr=0;
#0 boot_daddr=0;
#330 processor_select = 10;
#0 $readmemh("./app/tile10.instr.rif",imem);
#0 $readmemh("./app/tile10.data.rif",dmem);
#0 boot_iaddr=0;
#0 boot_daddr=0;
#330 processor_select = 11;
#0 $readmemh("./app/tile11.instr.rif",imem);
#0 $readmemh("./app/tile11.data.rif",dmem);
#0 boot_iaddr=0;
#0 boot_daddr=0;
#330 processor_select = 12;
#0 $readmemh("./app/tile12.instr.rif",imem);
#0 $readmemh("./app/tile12.data.rif",dmem);
#0 boot_iaddr=0;
#0 boot_daddr=0;
#330 processor_select = 13;
#0 $readmemh("./app/tile13.instr.rif",imem);
#0 $readmemh("./app/tile13.data.rif",dmem);
#0 boot_iaddr=0;
#0 boot_daddr=0;
#330 processor_select = 14;
#0 $readmemh("./app/tile14.instr.rif",imem);
#0 $readmemh("./app/tile14.data.rif",dmem);
#0 boot_iaddr=0;
#0 boot_daddr=0;
#330 processor_select = 15;
#0 $readmemh("./app/tile15.instr.rif",imem);
#0 $readmemh("./app/tile15.data.rif",dmem);
#0 boot_iaddr=0;
#0 boot_daddr=0;
#330 processor_select = 16;
#0 $readmemh("./app/tile16.instr.rif",imem);
#0 $readmemh("./app/tile16.data.rif",dmem);
#0 boot_iaddr=0;
#0 boot_daddr=0;
#330 processor_select = 17;
#0 $readmemh("./app/tile17.instr.rif",imem);
#0 $readmemh("./app/tile17.data.rif",dmem);
#0 boot_iaddr=0;
#0 boot_daddr=0;
#330 processor_select = 18;
#0 $readmemh("./app/tile18.instr.rif",imem);
#0 $readmemh("./app/tile18.data.rif",dmem);
#0 boot_iaddr=0;
#0 boot_daddr=0;
#330 processor_select = 19;
#0 $readmemh("./app/tile19.instr.rif",imem);
#0 $readmemh("./app/tile19.data.rif",dmem);
#0 boot_iaddr=0;
#0 boot_daddr=0;
#330 processor_select = 20;
#0 $readmemh("./app/tile20.instr.rif",imem);
#0 $readmemh("./app/tile20.data.rif",dmem);
#0 boot_iaddr=0;
#0 boot_daddr=0;
#330 processor_select = 21;
#0 $readmemh("./app/tile21.instr.rif",imem);
#0 $readmemh("./app/tile21.data.rif",dmem);
#0 boot_iaddr=0;
#0 boot_daddr=0;
#330 processor_select = 22;
#0 $readmemh("./app/tile22.instr.rif",imem);
#0 $readmemh("./app/tile22.data.rif",dmem);
#0 boot_iaddr=0;
#0 boot_daddr=0;
#330 processor_select = 23;
#0 $readmemh("./app/tile23.instr.rif",imem);
#0 $readmemh("./app/tile23.data.rif",dmem);
#0 boot_iaddr=0;
#0 boot_daddr=0;
#330 processor_select = 24;
#0 $readmemh("./app/tile24.instr.rif",imem);
#0 $readmemh("./app/tile24.data.rif",dmem);
#0 boot_iaddr=0;
#0 boot_daddr=0;
#330 processor_select = 25;
#0 $readmemh("./app/tile25.instr.rif",imem);
#0 $readmemh("./app/tile25.data.rif",dmem);
#0 boot_iaddr=0;
#0 boot_daddr=0;
#330 processor_select = 26;
#0 $readmemh("./app/tile26.instr.rif",imem);
#0 $readmemh("./app/tile26.data.rif",dmem);
#0 boot_iaddr=0;
#0 boot_daddr=0;
#330 processor_select = 27;
#0 $readmemh("./app/tile27.instr.rif",imem);
#0 $readmemh("./app/tile27.data.rif",dmem);
#0 boot_iaddr=0;
#0 boot_daddr=0;
#330 processor_select = 28;
#0 $readmemh("./app/tile28.instr.rif",imem);
#0 $readmemh("./app/tile28.data.rif",dmem);
#0 boot_iaddr=0;
#0 boot_daddr=0;
#330 processor_select = 29;
#0 $readmemh("./app/tile29.instr.rif",imem);
#0 $readmemh("./app/tile29.data.rif",dmem);
#0 boot_iaddr=0;
#0 boot_daddr=0;
#330 processor_select = 30;
#0 $readmemh("./app/tile30.instr.rif",imem);
#0 $readmemh("./app/tile30.data.rif",dmem);
#0 boot_iaddr=0;
#0 boot_daddr=0;
#330 processor_select = 31;
#0 $readmemh("./app/tile31.instr.rif",imem);
#0 $readmemh("./app/tile31.data.rif",dmem);
#0 boot_iaddr=0;
#0 boot_daddr=0;
#330 processor_select = 32;
#0 $readmemh("./app/tile32.instr.rif",imem);
#0 $readmemh("./app/tile32.data.rif",dmem);
#0 boot_iaddr=0;
#0 boot_daddr=0;
#330 processor_select = 33;
#0 $readmemh("./app/tile33.instr.rif",imem);
#0 $readmemh("./app/tile33.data.rif",dmem);
#0 boot_iaddr=0;
#0 boot_daddr=0;
#330 processor_select = 34;
#0 $readmemh("./app/tile34.instr.rif",imem);
#0 $readmemh("./app/tile34.data.rif",dmem);
#0 boot_iaddr=0;
#0 boot_daddr=0;
#330 processor_select = 35;
#0 $readmemh("./app/tile35.instr.rif",imem);
#0 $readmemh("./app/tile35.data.rif",dmem);
#0 boot_iaddr=0;
#0 boot_daddr=0;
#330 processor_select = 36;
#0 $readmemh("./app/tile36.instr.rif",imem);
#0 $readmemh("./app/tile36.data.rif",dmem);
#0 boot_iaddr=0;
#0 boot_daddr=0;
#330 processor_select = 37;
#0 $readmemh("./app/tile37.instr.rif",imem);
#0 $readmemh("./app/tile37.data.rif",dmem);
#0 boot_iaddr=0;
#0 boot_daddr=0;
#330 processor_select = 38;
#0 $readmemh("./app/tile38.instr.rif",imem);
#0 $readmemh("./app/tile38.data.rif",dmem);
#0 boot_iaddr=0;
#0 boot_daddr=0;
#330 processor_select = 39;
#0 $readmemh("./app/tile39.instr.rif",imem);
#0 $readmemh("./app/tile39.data.rif",dmem);
#0 boot_iaddr=0;
#0 boot_daddr=0;
#330 processor_select = 40;
#0 $readmemh("./app/tile40.instr.rif",imem);
#0 $readmemh("./app/tile40.data.rif",dmem);
#0 boot_iaddr=0;
#0 boot_daddr=0;
#330 processor_select = 41;
#0 $readmemh("./app/tile41.instr.rif",imem);
#0 $readmemh("./app/tile41.data.rif",dmem);
#0 boot_iaddr=0;
#0 boot_daddr=0;
#330 processor_select = 42;
#0 $readmemh("./app/tile42.instr.rif",imem);
#0 $readmemh("./app/tile42.data.rif",dmem);
#0 boot_iaddr=0;
#0 boot_daddr=0;
#330 processor_select = 43;
#0 $readmemh("./app/tile43.instr.rif",imem);
#0 $readmemh("./app/tile43.data.rif",dmem);
#0 boot_iaddr=0;
#0 boot_daddr=0;
#330 processor_select = 44;
#0 $readmemh("./app/tile44.instr.rif",imem);
#0 $readmemh("./app/tile44.data.rif",dmem);
#0 boot_iaddr=0;
#0 boot_daddr=0;
#330 processor_select = 45;
#0 $readmemh("./app/tile45.instr.rif",imem);
#0 $readmemh("./app/tile45.data.rif",dmem);
#0 boot_iaddr=0;
#0 boot_daddr=0;
#330 processor_select = 46;
#0 $readmemh("./app/tile46.instr.rif",imem);
#0 $readmemh("./app/tile46.data.rif",dmem);
#0 boot_iaddr=0;
#0 boot_daddr=0;
#330 processor_select = 47;
#0 $readmemh("./app/tile47.instr.rif",imem);
#0 $readmemh("./app/tile47.data.rif",dmem);
#0 boot_iaddr=0;
#0 boot_daddr=0;
#330 processor_select = 48;
#0 $readmemh("./app/tile48.instr.rif",imem);
#0 $readmemh("./app/tile48.data.rif",dmem);
#0 boot_iaddr=0;
#0 boot_daddr=0;
#330 processor_select = 49;
#0 $readmemh("./app/tile49.instr.rif",imem);
#0 $readmemh("./app/tile49.data.rif",dmem);
#0 boot_iaddr=0;
#0 boot_daddr=0;
#330 processor_select = 50;
#0 $readmemh("./app/tile50.instr.rif",imem);
#0 $readmemh("./app/tile50.data.rif",dmem);
#0 boot_iaddr=0;
#0 boot_daddr=0;
#330 processor_select = 51;
#0 $readmemh("./app/tile51.instr.rif",imem);
#0 $readmemh("./app/tile51.data.rif",dmem);
#0 boot_iaddr=0;
#0 boot_daddr=0;
#330 processor_select = 52;
#0 $readmemh("./app/tile52.instr.rif",imem);
#0 $readmemh("./app/tile52.data.rif",dmem);
#0 boot_iaddr=0;
#0 boot_daddr=0;
#330 processor_select = 53;
#0 $readmemh("./app/tile53.instr.rif",imem);
#0 $readmemh("./app/tile53.data.rif",dmem);
#0 boot_iaddr=0;
#0 boot_daddr=0;
#330 processor_select = 54;
#0 $readmemh("./app/tile54.instr.rif",imem);
#0 $readmemh("./app/tile54.data.rif",dmem);
#0 boot_iaddr=0;
#0 boot_daddr=0;
#330 processor_select = 55;
#0 $readmemh("./app/tile55.instr.rif",imem);
#0 $readmemh("./app/tile55.data.rif",dmem);
#0 boot_iaddr=0;
#0 boot_daddr=0;
#330 processor_select = 56;
#0 $readmemh("./app/tile56.instr.rif",imem);
#0 $readmemh("./app/tile56.data.rif",dmem);
#0 boot_iaddr=0;
#0 boot_daddr=0;
#330 processor_select = 57;
#0 $readmemh("./app/tile57.instr.rif",imem);
#0 $readmemh("./app/tile57.data.rif",dmem);
#0 boot_iaddr=0;
#0 boot_daddr=0;
#330 processor_select = 58;
#0 $readmemh("./app/tile58.instr.rif",imem);
#0 $readmemh("./app/tile58.data.rif",dmem);
#0 boot_iaddr=0;
#0 boot_daddr=0;
#330 processor_select = 59;
#0 $readmemh("./app/tile59.instr.rif",imem);
#0 $readmemh("./app/tile59.data.rif",dmem);
#0 boot_iaddr=0;
#0 boot_daddr=0;
#330 processor_select = 60;
#0 $readmemh("./app/tile60.instr.rif",imem);
#0 $readmemh("./app/tile60.data.rif",dmem);
#0 boot_iaddr=0;
#0 boot_daddr=0;
#330 processor_select = 61;
#0 $readmemh("./app/tile61.instr.rif",imem);
#0 $readmemh("./app/tile61.data.rif",dmem);
#0 boot_iaddr=0;
#0 boot_daddr=0;
#330 processor_select = 62;
#0 $readmemh("./app/tile62.instr.rif",imem);
#0 $readmemh("./app/tile62.data.rif",dmem);
#0 boot_iaddr=0;
#0 boot_daddr=0;
#330 processor_select = 63;
#0 $readmemh("./app/tile63.instr.rif",imem);
#0 $readmemh("./app/tile63.data.rif",dmem);
#0 boot_iaddr=0;
#0 boot_daddr=0;
#330 processor_select = 64;
#0 $readmemh("./app/tile64.instr.rif",imem);
#0 $readmemh("./app/tile64.data.rif",dmem);
#0 boot_iaddr=0;
#0 boot_daddr=0;
#330 processor_select = 65;
#0 $readmemh("./app/tile65.instr.rif",imem);
#0 $readmemh("./app/tile65.data.rif",dmem);
#0 boot_iaddr=0;
#0 boot_daddr=0;
#330 processor_select = 66;
#0 $readmemh("./app/tile66.instr.rif",imem);
#0 $readmemh("./app/tile66.data.rif",dmem);
#0 boot_iaddr=0;
#0 boot_daddr=0;
#330 processor_select = 67;
#0 $readmemh("./app/tile67.instr.rif",imem);
#0 $readmemh("./app/tile67.data.rif",dmem);
#0 boot_iaddr=0;
#0 boot_daddr=0;
#330 processor_select = 68;
#0 $readmemh("./app/tile68.instr.rif",imem);
#0 $readmemh("./app/tile68.data.rif",dmem);
#0 boot_iaddr=0;
#0 boot_daddr=0;
#330 processor_select = 69;
#0 $readmemh("./app/tile69.instr.rif",imem);
#0 $readmemh("./app/tile69.data.rif",dmem);
#0 boot_iaddr=0;
#0 boot_daddr=0;
#330 processor_select = 70;
#0 $readmemh("./app/tile70.instr.rif",imem);
#0 $readmemh("./app/tile70.data.rif",dmem);
#0 boot_iaddr=0;
#0 boot_daddr=0;
#330 processor_select = 71;
#0 $readmemh("./app/tile71.instr.rif",imem);
#0 $readmemh("./app/tile71.data.rif",dmem);
#0 boot_iaddr=0;
#0 boot_daddr=0;
#330 processor_select = 72;
#0 $readmemh("./app/tile72.instr.rif",imem);
#0 $readmemh("./app/tile72.data.rif",dmem);
#0 boot_iaddr=0;
#0 boot_daddr=0;
#330 processor_select = 73;
#0 $readmemh("./app/tile73.instr.rif",imem);
#0 $readmemh("./app/tile73.data.rif",dmem);
#0 boot_iaddr=0;
#0 boot_daddr=0;
#330 processor_select = 74;
#0 $readmemh("./app/tile74.instr.rif",imem);
#0 $readmemh("./app/tile74.data.rif",dmem);
#0 boot_iaddr=0;
#0 boot_daddr=0;
#330 processor_select = 75;
#0 $readmemh("./app/tile75.instr.rif",imem);
#0 $readmemh("./app/tile75.data.rif",dmem);
#0 boot_iaddr=0;
#0 boot_daddr=0;
#330 processor_select = 76;
#0 $readmemh("./app/tile76.instr.rif",imem);
#0 $readmemh("./app/tile76.data.rif",dmem);
#0 boot_iaddr=0;
#0 boot_daddr=0;
#330 processor_select = 77;
#0 $readmemh("./app/tile77.instr.rif",imem);
#0 $readmemh("./app/tile77.data.rif",dmem);
#0 boot_iaddr=0;
#0 boot_daddr=0;
#330 processor_select = 78;
#0 $readmemh("./app/tile78.instr.rif",imem);
#0 $readmemh("./app/tile78.data.rif",dmem);
#0 boot_iaddr=0;
#0 boot_daddr=0;
#330 processor_select = 79;
#0 $readmemh("./app/tile79.instr.rif",imem);
#0 $readmemh("./app/tile79.data.rif",dmem);
#0 boot_iaddr=0;
#0 boot_daddr=0;
#330 processor_select = 80;
#0 $readmemh("./app/tile80.instr.rif",imem);
#0 $readmemh("./app/tile80.data.rif",dmem);
#0 boot_iaddr=0;
#0 boot_daddr=0;
#330 processor_select = 81;
#0 $readmemh("./app/tile81.instr.rif",imem);
#0 $readmemh("./app/tile81.data.rif",dmem);
#0 boot_iaddr=0;
#0 boot_daddr=0;
#330 processor_select = 82;
#0 $readmemh("./app/tile82.instr.rif",imem);
#0 $readmemh("./app/tile82.data.rif",dmem);
#0 boot_iaddr=0;
#0 boot_daddr=0;
#330 processor_select = 83;
#0 $readmemh("./app/tile83.instr.rif",imem);
#0 $readmemh("./app/tile83.data.rif",dmem);
#0 boot_iaddr=0;
#0 boot_daddr=0;
#330 processor_select = 84;
#0 $readmemh("./app/tile84.instr.rif",imem);
#0 $readmemh("./app/tile84.data.rif",dmem);
#0 boot_iaddr=0;
#0 boot_daddr=0;
#330 processor_select = 85;
#0 $readmemh("./app/tile85.instr.rif",imem);
#0 $readmemh("./app/tile85.data.rif",dmem);
#0 boot_iaddr=0;
#0 boot_daddr=0;
#330 processor_select = 86;
#0 $readmemh("./app/tile86.instr.rif",imem);
#0 $readmemh("./app/tile86.data.rif",dmem);
#0 boot_iaddr=0;
#0 boot_daddr=0;
#330 processor_select = 87;
#0 $readmemh("./app/tile87.instr.rif",imem);
#0 $readmemh("./app/tile87.data.rif",dmem);
#0 boot_iaddr=0;
#0 boot_daddr=0;
#330 processor_select = 88;
#0 $readmemh("./app/tile88.instr.rif",imem);
#0 $readmemh("./app/tile88.data.rif",dmem);
#0 boot_iaddr=0;
#0 boot_daddr=0;
#330 processor_select = 89;
#0 $readmemh("./app/tile89.instr.rif",imem);
#0 $readmemh("./app/tile89.data.rif",dmem);
#0 boot_iaddr=0;
#0 boot_daddr=0;
#330 processor_select = 90;
end
/**************** Boot loader ********************/
always@(posedge clk)
begin
if (~resetn)
boot_iaddr<=boot_iaddr+1;
if (~resetn)
boot_daddr<=boot_daddr+1;
end
assign boot_idata=imem[boot_iaddr];
assign boot_ddata=dmem[boot_daddr];
endmodule |
/****************************************************************************
AddSub unit
- Should perform ADD, ADDU, SUBU, SUB, SLT, SLTU
is_slt signext addsub
op[2] op[1] op[0] | Operation
0 0 0 0 SUBU
2 0 1 0 SUB
1 0 0 1 ADDU
3 0 1 1 ADD
4 1 0 0 SLTU
6 1 1 0 SLT
****************************************************************************/
module addersub (
opA, opB,
op,
result,
result_slt );
parameter WIDTH=32;
input [WIDTH-1:0] opA;
input [WIDTH-1:0] opB;
//input carry_in;
input [3-1:0] op;
output [WIDTH-1:0] result;
output result_slt;
wire carry_out;
wire [WIDTH:0] sum;
// Mux between sum, and slt
wire is_slt;
wire signext;
wire addsub;
assign is_slt=op[2];
assign signext=op[1];
assign addsub=op[0];
assign result=sum[WIDTH-1:0];
//assign result_slt[WIDTH-1:1]={31{1'b0}};
//assign result_slt[0]=sum[WIDTH];
assign result_slt=sum[WIDTH];
lpm_add_sub adder_inst(
.dataa({signext&opA[WIDTH-1],opA}),
.datab({signext&opB[WIDTH-1],opB}),
.cin(~addsub),
.add_sub(addsub),
.result(sum)
// synopsys translate_off
,
.cout (),
.clken (),
.clock (),
.overflow (),
.aclr ()
// synopsys translate_on
);
defparam
adder_inst.lpm_width=WIDTH+1,
adder_inst.lpm_representation="SIGNED";
assign carry_out=sum[WIDTH];
endmodule
|
module branchresolve ( en, rs, rt, eq, ne, ltz, lez, gtz, gez, eqz);
parameter WIDTH=32; //Deepak : Change from parameter to define
input en;
input [WIDTH-1:0] rs;
input [WIDTH-1:0] rt;
output eq;
output ne;
output ltz;
output lez;
output gtz;
output gez;
output eqz;
assign eq=(en)&(rs==rt);
assign ne=(en)&~eq;
assign eqz=(en)&~(|rs);
assign ltz=(en)&rs[WIDTH-1];
assign lez=(en)&rs[WIDTH-1] | eqz;
assign gtz=(en)&(~rs[WIDTH-1]) & ~eqz;
assign gez=(en)&(~rs[WIDTH-1]);
endmodule
|
/****************************************************************************
Generic Register
****************************************************************************/
module register(d,clk,resetn,en,q);
parameter WIDTH=32;
input clk;
input resetn;
input en;
input [WIDTH-1:0] d;
output [WIDTH-1:0] q;
reg [WIDTH-1:0] q;
always @(posedge clk or negedge resetn) //asynchronous reset
begin
if (resetn==0)
q<=0;
else if (en==1)
q<=d;
end
endmodule
/****************************************************************************
Generic Register - synchronous reset
****************************************************************************/
module register_sync(d,clk,resetn,en,q);
parameter WIDTH=32;
input clk;
input resetn;
input en;
input [WIDTH-1:0] d;
output [WIDTH-1:0] q;
reg [WIDTH-1:0] q;
always @(posedge clk) //synchronous reset
begin
if (resetn==0)
q<=0;
else if (en==1)
q<=d;
end
endmodule
/****************************************************************************
Generic Pipelined Register
- Special component, components starting with "pipereg" have
their enables treated independently of instructrions that use them.
- They are enabled whenever the stage is active and not stalled
****************************************************************************/
module pipereg(d,clk,resetn,en,squashn,q);
parameter WIDTH=32;
input clk;
input resetn;
input en;
input squashn;
input [WIDTH-1:0] d;
output [WIDTH-1:0] q;
reg [WIDTH-1:0] q;
always @(posedge clk) //synchronous reset
begin
if (resetn==0 || squashn==0)
q<=0;
else if (en==1)
q<=d;
end
endmodule
/****************************************************************************
Generic Pipelined Register 2 -OLD: If not enabled, queues squash
- This piperegister stalls the reset signal as well
module pipereg_full(d,clk,resetn,squashn,en,q);
parameter WIDTH=32;
input clk;
input resetn;
input en;
input squashn;
input [WIDTH-1:0] d;
output [WIDTH-1:0] q;
reg [WIDTH-1:0] q;
reg squash_save;
always @(posedge clk) //synchronous reset
begin
if (resetn==0 || (squashn==0 && en==1) || (squash_save&en))
q<=0;
else if (en==1)
q<=d;
end
always @(posedge clk)
begin
if (resetn==1 && squashn==0 && en==0)
squash_save<=1;
else
squash_save<=0;
end
endmodule
****************************************************************************/
/****************************************************************************
One cycle Stall circuit
****************************************************************************/
module onecyclestall(request,clk,resetn,stalled);
input request;
input clk;
input resetn;
output stalled;
reg T,Tnext;
// State machine for Stalling 1 cycle
always@(request or T)
begin
case(T)
1'b0: Tnext=request;
1'b1: Tnext=0;
endcase
end
always@(posedge clk)
if (~resetn)
T<=0;
else
T<=Tnext;
assign stalled=(request&~T);
endmodule
/****************************************************************************
Multi cycle Stall circuit - with wait signal
- One FF plus one 2:1 mux to stall 1st cycle on request, then wait
- this makes wait don't care for the first cycle
****************************************************************************/
module multicyclestall(request, devwait,clk,resetn,stalled);
input request;
input devwait;
input clk;
input resetn;
output stalled;
reg T;
always@(posedge clk)
if (~resetn)
T<=0;
else
T<=stalled;
assign stalled=(T) ? devwait : request;
endmodule
/****************************************************************************
One cycle - Pipeline delay register
****************************************************************************/
module pipedelayreg(d,en,clk,resetn,squashn,dst,stalled,q);
parameter WIDTH=32;
input [WIDTH-1:0] d;
input [4:0] dst;
input en;
input clk;
input resetn;
input squashn;
output stalled;
output [WIDTH-1:0] q;
reg [WIDTH-1:0] q;
reg T,Tnext;
// State machine for Stalling 1 cycle
always@(en or T or dst)
begin
case(T)
0: Tnext=en&(|dst);
1: Tnext=0;
endcase
end
always@(posedge clk)
if (~resetn)
T<=0;
else
T<=Tnext;
always @(posedge clk) //synchronous reset
begin
if (resetn==0 || squashn==0)
q<=0;
else if (en==1)
q<=d;
end
assign stalled=(en&~T&(|dst));
endmodule
/****************************************************************************
Fake Delay
****************************************************************************/
module fakedelay(d,clk,q);
parameter WIDTH=32;
input [WIDTH-1:0] d;
input clk;
output [WIDTH-1:0] q;
assign q=d;
endmodule
/****************************************************************************
Zeroer
****************************************************************************/
module zeroer(d,en,q);
parameter WIDTH=32;
input en;
input [WIDTH-1:0] d;
output [WIDTH-1:0] q;
assign q= (en) ? d : 0;
endmodule
/****************************************************************************
NOP - used to hack position of multiplexors
****************************************************************************/
module nop(d,q);
parameter WIDTH=32;
input [WIDTH-1:0] d;
output [WIDTH-1:0] q;
assign q=d;
endmodule
/****************************************************************************
Const
****************************************************************************/
//Deepak : Changed const to constant to resolve compilation error
module constant (out);
parameter WIDTH=32;
parameter VAL=31;
output [WIDTH-1:0] out;
assign out=VAL;
endmodule
/****************************************************************************
Branch detector
****************************************************************************/
module branch_detector(opcode, func, is_branch);
input [5:0] opcode;
input [5:0] func;
output is_branch;
wire is_special;
assign is_special=!(|opcode);
assign is_branch=((!(|opcode[5:3])) && !is_special) ||
((is_special)&&(func[5:3]==3'b001));
endmodule
|
/******************************************************************************
Data memory and interface
Operation table:
load/store sign size1 size0 | Operation
7 0 1 1 1 | LB
5 0 1 0 1 | LH
0 0 X 0 0 | LW
3 0 0 1 1 | LBU
1 0 0 0 1 | LHU
11 1 X 1 1 | SB
9 1 X 0 1 | SH
8 1 X 0 0 | SW
******************************************************************************/
module data_mem( clk, resetn, en, stalled,
d_writedata,
d_address,
boot_daddr, boot_ddata, boot_dwe,
op,
d_loadresult);
parameter D_ADDRESSWIDTH=32;
parameter DM_DATAWIDTH=32;
parameter DM_BYTEENAWIDTH=4; // usually should be DM_DATAWIDTH/8
//parameter DM_ADDRESSWIDTH=16; //Deepak commented
//parameter DM_SIZE=16384; //Deepak commented
//Deepak : UnCommented to see why the processor is stopping after the first instruction
parameter DM_ADDRESSWIDTH=8; //Deepak
parameter DM_SIZE=64; //Deepak : Increased the size of memory
input clk;
input resetn;
input en;
output stalled;
input [31:0] boot_daddr;
input [31:0] boot_ddata;
input boot_dwe;
input [D_ADDRESSWIDTH-1:0] d_address;
input [4-1:0] op;
input [DM_DATAWIDTH-1:0] d_writedata;
output [DM_DATAWIDTH-1:0] d_loadresult;
wire [DM_BYTEENAWIDTH-1:0] d_byteena;
wire [DM_DATAWIDTH-1:0] d_readdatain;
wire [DM_DATAWIDTH-1:0] d_writedatamem;
wire d_write;
wire [1:0] d_address_latched;
assign d_write=op[3];
//assign d_write = d_write;//deepak
register d_address_reg(d_address[1:0],clk,1'b1,en,d_address_latched);
defparam d_address_reg.WIDTH=2;
store_data_translator sdtrans_inst(
.write_data(d_writedata),
.d_address(d_address[1:0]),
.store_size(op[1:0]),
.d_byteena(d_byteena),
.d_writedataout(d_writedatamem));
load_data_translator ldtrans_inst(
.d_readdatain(d_readdatain),
.d_address(d_address_latched[1:0]),
.load_size(op[1:0]),
.load_sign_ext(op[2]),
.d_loadresult(d_loadresult));
altsyncram dmem (
.wren_a (d_write&en&(~d_address[31])),
.clock0 (clk),
.clocken0 (),
.clock1 (clk),
.clocken1 (boot_dwe),
`ifdef TEST_BENCH
.aclr0(~resetn),
`endif
.byteena_a (d_byteena),
.address_a (d_address[DM_ADDRESSWIDTH+2-1:2]),
.data_a (d_writedatamem),
.wren_b (boot_dwe), .data_b (boot_ddata), .address_b (boot_daddr),
// synopsys translate_off
.rden_b (),
.aclr1 (), .byteena_b (),
.addressstall_a (), .addressstall_b (), .q_b (),
// synopsys translate_on
.q_a (d_readdatain)
);
defparam
dmem.intended_device_family = "Stratix", //Deepak changed from Stratix to Cyclone
dmem.width_a = DM_DATAWIDTH,
dmem.widthad_a = DM_ADDRESSWIDTH-2,
dmem.numwords_a = DM_SIZE,
dmem.width_byteena_a = DM_BYTEENAWIDTH,
dmem.operation_mode = "BIDIR_DUAL_PORT",
dmem.width_b = DM_DATAWIDTH,
dmem.widthad_b = DM_ADDRESSWIDTH-2,
dmem.numwords_b = DM_SIZE,
dmem.width_byteena_b = 1,
dmem.outdata_reg_a = "UNREGISTERED",
dmem.address_reg_b = "CLOCK1",
dmem.wrcontrol_wraddress_reg_b = "CLOCK1",
dmem.wrcontrol_aclr_a = "NONE",
dmem.address_aclr_a = "NONE",
dmem.outdata_aclr_a = "NONE",
dmem.byteena_aclr_a = "NONE",
dmem.byte_size = 8,
`ifdef TEST_BENCH
dmem.indata_aclr_a = "CLEAR0",
dmem.init_file = "data.rif",
`endif
//`ifdef QUARTUS_SIM
dmem.init_file = "data.mif",
dmem.ram_block_type = "M4K",
//`else
// dmem.ram_block_type = "MEGARAM",
//`endif
dmem.lpm_type = "altsyncram";
// 1 cycle stall state machine
onecyclestall staller(en&~d_write,clk,resetn,stalled);
endmodule
/****************************************************************************
Store data translator
- moves store data to appropriate byte/halfword
- interfaces with altera blockrams
****************************************************************************/
module store_data_translator(
write_data, // data in least significant position
d_address,
store_size,
d_byteena,
d_writedataout); // shifted data to coincide with address
parameter WIDTH=32;
input [WIDTH-1:0] write_data;
input [1:0] d_address;
input [1:0] store_size;
output [3:0] d_byteena;
output [WIDTH-1:0] d_writedataout;
reg [3:0] d_byteena;
reg [WIDTH-1:0] d_writedataout;
always @(write_data or d_address or store_size)
begin
case (store_size)
2'b11:
case(d_address[1:0])
0:
begin
d_byteena=4'b1000;
d_writedataout={write_data[7:0],24'b0};
end
1:
begin
d_byteena=4'b0100;
d_writedataout={8'b0,write_data[7:0],16'b0};
end
2:
begin
d_byteena=4'b0010;
d_writedataout={16'b0,write_data[7:0],8'b0};
end
default:
begin
d_byteena=4'b0001;
d_writedataout={24'b0,write_data[7:0]};
end
endcase
2'b01:
case(d_address[1])
0:
begin
d_byteena=4'b1100;
d_writedataout={write_data[15:0],16'b0};
end
default:
begin
d_byteena=4'b0011;
d_writedataout={16'b0,write_data[15:0]};
end
endcase
default:
begin
d_byteena=4'b1111;
d_writedataout=write_data;
end
endcase
end
endmodule
/****************************************************************************
Load data translator
- moves read data to appropriate byte/halfword and zero/sign extends
****************************************************************************/
module load_data_translator(
d_readdatain,
d_address,
load_size,
load_sign_ext,
d_loadresult);
parameter WIDTH=32;
input [WIDTH-1:0] d_readdatain;
input [1:0] d_address;
input [1:0] load_size;
input load_sign_ext;
output [WIDTH-1:0] d_loadresult;
reg [WIDTH-1:0] d_loadresult;
always @(d_readdatain or d_address or load_size or load_sign_ext)
begin
case (load_size)
2'b11:
begin
case (d_address[1:0])
0: d_loadresult[7:0]=d_readdatain[31:24];
1: d_loadresult[7:0]=d_readdatain[23:16];
2: d_loadresult[7:0]=d_readdatain[15:8];
default: d_loadresult[7:0]=d_readdatain[7:0];
endcase
d_loadresult[31:8]={24{load_sign_ext&d_loadresult[7]}};
end
2'b01:
begin
case (d_address[1])
0: d_loadresult[15:0]=d_readdatain[31:16];
default: d_loadresult[15:0]=d_readdatain[15:0];
endcase
d_loadresult[31:16]={16{load_sign_ext&d_loadresult[15]}};
end
default:
d_loadresult=d_readdatain;
endcase
end
endmodule
|
// A FIFO is used for a non-duplex communication between a processor and another
module fifo(clk,resetn,dataIn,dataOut,wr,rd,full,empty,overflow);
parameter LOGSIZE = 2; //Default size is 4 elements (only 3 reqd)
parameter WIDTH = 32; //Default width is 32 bits
parameter SIZE = 1 << LOGSIZE;
input clk,resetn,rd,wr;
input [WIDTH-1:0] dataIn;
output[WIDTH-1:0] dataOut;
output full,empty,overflow;
reg [WIDTH-1:0] fifo[SIZE-1:0] ; //Fifo data stored here
reg overflow; //true if WR but no room, cleared on RD
reg [LOGSIZE-1:0] wptr,rptr; //Fifo read and write pointers
wire [WIDTH-1:0] fifoWire[SIZE-1:0] ; //Fifo data stored here
reg counter = 0;
reg [WIDTH-1:0] tempOut;
wire [LOGSIZE-1:0] wptr_inc = wptr+1;
assign empty = (wptr==rptr);
assign full = (wptr_inc==rptr);
assign dataOut = tempOut;
assign fifoWire[0] = fifo[0];
//always @ (posedge clk) begin
// if(reset) begin
// wptr<=0;
// rptr<=0;
// fifo[0] <= 32'hdeadbeef;
// fifo[1] <= 32'hdeadbeef;
// fifo[2] <= 32'hdeadbeef;
// end
//end
always @ (posedge clk) begin
if(wr==1) begin
fifo[wptr]<=dataIn;
wptr <= wptr + 1;
end
if(rd==1&&!empty) begin
casex(counter)
0: begin
tempOut <= fifo[rptr];
rptr <= rptr + 1;
counter <= 1;
end
endcase
end
if(rd==0) begin
counter <=0;
end
if(resetn==0) begin
rptr<=0;
wptr<=0;
end
end
endmodule
|
/****************************************************************************
Generic Register
****************************************************************************/
module hi_reg(d,clk,resetn,en,q);
parameter WIDTH=32;
input clk;
input resetn;
input en;
input [WIDTH-1:0] d;
output [WIDTH-1:0] q;
reg [WIDTH-1:0] q;
always @(posedge clk or negedge resetn) //asynchronous reset
begin
if (resetn==0)
q<=0;
else if (en==1)
q<=d;
end
endmodule
|
/****************************************************************************
Fetch Unit
op
0 Conditional PC write
1 UnConditional PC write
****************************************************************************/
module ifetch(clk,resetn,
en,
squashn,
we,
op,
load,
load_data,
pc_out,
next_pc,
boot_iaddr,
boot_idata,
boot_iwe,
opcode,
rs,
rt,
rd,
sa,
offset,
instr_index,
func,
instr);
parameter PC_WIDTH=30;
parameter I_DATAWIDTH=32;
parameter I_ADDRESSWIDTH=8;
parameter I_SIZE=64;
input [31:0] boot_iaddr;
input [31:0] boot_idata;
input boot_iwe;
input clk;
input resetn;
input en; // PC increment enable
input we; // PC write enable
input squashn;// squash fetch
input op; // determines if conditional or unconditional branch
input load;
input [I_DATAWIDTH-1:0] load_data;
output [I_DATAWIDTH-1:0] pc_out; // output pc + 1 shifted left 2 bits
output [PC_WIDTH-1:0] next_pc;
output [31:26] opcode;
output [25:21] rs;
output [20:16] rt;
output [15:11] rd;
output [10:6] sa;
output [15:0] offset;
output [25:0] instr_index;
output [5:0] func;
output [I_DATAWIDTH-1:0] instr;
wire [PC_WIDTH-1:0] pc_plus_1;
wire [PC_WIDTH-1:0] pc;
wire ctrl_load;
wire out_of_sync;
assign ctrl_load=(load&~op|op);
lpm_counter pc_register(
.data(load_data[I_DATAWIDTH-1:2]),
.clock(clk),
.clk_en(en|we),
.cnt_en((~ctrl_load)&~out_of_sync),
.aset(~resetn),
.sload(ctrl_load),
// synopsys translate_off
.updown(), .cin(), .sset(), .sclr(), .aclr(), .aload(),
.eq(), .cout(),
// synopsys translate_on
.q(pc));
defparam pc_register.lpm_width=PC_WIDTH,
pc_register.lpm_avalue="16777215"; // 0x4000000 divide by 4
/****** Re-synchronize for case:
* en=0 && we=1 -> pc_register gets updated but not imem address
*
* Solution: stall pc_register and load memory address by changing
* incrementer to increment by 0
*******/
register sync_pcs_up( (we&~en&squashn), clk, resetn,en|we, out_of_sync);
defparam sync_pcs_up.WIDTH=1;
altsyncram imem (
.clock0 (clk),
.clocken0 (en|~squashn|~resetn),
.clock1 (clk), // changed
.clocken1 (boot_iwe), // changed
`ifdef TEST_BENCH
.aclr0(~resetn),
`endif
.address_a (next_pc[I_ADDRESSWIDTH-1:0]),
.wren_b (boot_iwe), .data_b (boot_idata), .address_b (boot_iaddr), //changed
// synopsys translate_off
.wren_a (), .rden_b (), .data_a (),
.aclr1 (), .byteena_a (), .byteena_b (),
.addressstall_a (), .addressstall_b (), .q_b (),
// synopsys translate_on
.q_a (instr)
);
defparam
imem.intended_device_family = "Stratix",
imem.width_a = I_DATAWIDTH,
imem.widthad_a = I_ADDRESSWIDTH,
imem.numwords_a = I_SIZE,
imem.operation_mode = "BIDIR_DUAL_PORT", // changed
imem.width_b = I_DATAWIDTH, // new
imem.widthad_b = I_ADDRESSWIDTH, // new
imem.numwords_b = I_SIZE, // new
imem.outdata_reg_b = "UNREGISTERED",
imem.outdata_reg_a = "UNREGISTERED",
imem.address_reg_b = "CLOCK1", // new
imem.wrcontrol_wraddress_reg_b = "CLOCK1", // new
imem.width_byteena_a = 1,
`ifdef TEST_BENCH
imem.address_aclr_a = "CLEAR0",
imem.outdata_aclr_a = "CLEAR0",
imem.init_file = "instr.rif",
`endif
`ifdef QUARTUS_SIM
imem.init_file = "instr.mif",
imem.ram_block_type = "AUTO",
`else
imem.ram_block_type = "M4K",
`endif
imem.lpm_type = "altsyncram";
wire dummy;
assign {dummy,pc_plus_1} = pc + {1'b0,~out_of_sync};
assign pc_out={pc_plus_1,2'b0};
assign next_pc = ctrl_load ? load_data[I_DATAWIDTH-1:2] : pc_plus_1;
assign opcode=instr[31:26];
assign rs=instr[25:21];
assign rt=instr[20:16];
assign rd=instr[15:11];
assign sa=instr[10:6];
assign offset=instr[15:0];
assign instr_index=instr[25:0];
assign func=instr[5:0];
endmodule
|
/****************************************************************************
ISA definition file
- The MIPS I ISA has a 6 bit opcode in the upper 6 bits.
- The opcode can also specify a "class". There are two classes:
1. SPECIAL - look in lowest 6 bits to find operation
2. REGIMM - look in [20:16] to find type of branch
****************************************************************************/
/****** OPCODES - bits 31...26 *******/
parameter OP_SPECIAL = 6'b000000;
parameter OP_REGIMM = 6'b000001;
parameter OP_J = 6'b000010;
parameter OP_JAL = 6'b000011;
parameter OP_BEQ = 6'b000100;
parameter OP_BNE = 6'b000101;
parameter OP_BLEZ = 6'b000110;
parameter OP_BGTZ = 6'b000111;
parameter OP_ADDI = 6'b001000;
parameter OP_ADDIU = 6'b001001;
parameter OP_SLTI = 6'b001010;
parameter OP_SLTIU = 6'b001011;
parameter OP_ANDI = 6'b001100;
parameter OP_ORI = 6'b001101;
parameter OP_XORI = 6'b001110;
parameter OP_LUI = 6'b001111;
parameter OP_LB = 6'b100000;
parameter OP_LH = 6'b100001;
parameter OP_LWL = 6'b100010;
parameter OP_LW = 6'b100011;
parameter OP_LBU = 6'b100100;
parameter OP_LHU = 6'b100101;
parameter OP_LWR = 6'b100110;
parameter OP_SB = 6'b101x00;
parameter OP_SH = 6'b101x01;
parameter OP_SWL = 6'b101010;
parameter OP_SW = 6'b101x11;
parameter OP_SWR = 6'b101110;
/****** FUNCTION CLASS - bits 5...0 *******/
parameter FUNC_SLL = 6'b000000;
parameter FUNC_SRL = 6'b000010;
parameter FUNC_SRA = 6'b000011;
parameter FUNC_SLLV = 6'b000100;
parameter FUNC_SRLV = 6'b000110;
parameter FUNC_SRAV = 6'b000111;
parameter FUNC_JR = 6'b001xx0;
parameter FUNC_JALR = 6'b001xx1;
parameter FUNC_MFHI = 6'bx10x00;
parameter FUNC_MTHI = 6'bx10x01;
parameter FUNC_MFLO = 6'bx10x10;
parameter FUNC_MTLO = 6'bx10x11;
parameter FUNC_MULT = 6'bx11x00;
parameter FUNC_MULTU = 6'bx11x01;
parameter FUNC_DIV = 6'bx11x10;
parameter FUNC_DIVU = 6'bx11x11;
parameter FUNC_ADD = 6'b100000;
parameter FUNC_ADDU = 6'b100001;
parameter FUNC_SUB = 6'b100010;
parameter FUNC_SUBU = 6'b100011;
parameter FUNC_AND = 6'b100100;
parameter FUNC_OR = 6'b100101;
parameter FUNC_XOR = 6'b100110;
parameter FUNC_NOR = 6'b100111;
parameter FUNC_SLT = 6'b101010;
parameter FUNC_SLTU = 6'b101011;
/****** REGIMM Class - bits 20...16 *******/
parameter FUNC_BLTZ = 1'b0;
parameter FUNC_BGEZ = 1'b1;
parameter OP_COP2 = 6'b010010;
parameter COP2_FUNC_CFC2 = 6'b111000;
parameter COP2_FUNC_CTC2 = 6'b111010;
parameter COP2_FUNC_MTC2 = 6'b111011;
//parameter FUNC_BLTZAL = 5'b10000;
//parameter FUNC_BGEZAL = 5'b10001;
/******
* Original REGIMM class, compressed above to save decode logic
parameter FUNC_BLTZ = 5'b00000;
parameter FUNC_BGEZ = 5'b00001;
parameter FUNC_BLTZAL = 5'b10000;
parameter FUNC_BGEZAL = 5'b10001;
*/
|
/****************************************************************************
logic unit
- note ALU must be able to increment PC for JAL type instructions
Operation Table
op
0 AND
1 OR
2 XOR
3 NOR
****************************************************************************/
module logic_unit (
opA, opB,
op,
result);
parameter WIDTH=32;
input [WIDTH-1:0] opA;
input [WIDTH-1:0] opB;
input [2-1:0] op;
output [WIDTH-1:0] result;
reg [WIDTH-1:0] logic_result;
always@(opA or opB or op )
case(op)
2'b00:
logic_result=opA&opB;
2'b01:
logic_result=opA|opB;
2'b10:
logic_result=opA^opB;
2'b11:
logic_result=~(opA|opB);
endcase
assign result=logic_result;
endmodule
|
/****************************************************************************
Generic Register
****************************************************************************/
module lo_reg(d,clk,resetn,en,q);
parameter WIDTH=32;
input clk;
input resetn;
input en;
input [WIDTH-1:0] d;
output [WIDTH-1:0] q;
reg [WIDTH-1:0] q;
always @(posedge clk or negedge resetn) //asynchronous reset
begin
if (resetn==0)
q<=0;
else if (en==1)
q<=d;
end
endmodule
|
module merge26lo(in1, in2, out);
input [31:0] in1;
input [25:0] in2;
output [31:0] out;
assign out[31:0]={in1[31:28],in2[25:0],2'b0};
endmodule
|
/****************************************************************************
MUL/DIV unit
Operation table
op
0 MULTU
1 MULT
****************************************************************************/
module mul(
opA, opB,
op, //is_signed
hi, lo);
parameter WIDTH=32;
input [WIDTH-1:0] opA;
input [WIDTH-1:0] opB;
input op;
output [WIDTH-1:0] hi;
output [WIDTH-1:0] lo;
wire is_signed;
assign is_signed=op;
wire dum,dum2;
lpm_mult lpm_mult_component (
.dataa ({is_signed&opA[WIDTH-1],opA}),
.datab ({is_signed&opB[WIDTH-1],opB}),
.result ({dum2,dum,hi,lo})
// synopsys translate_off
,
.clken (1'b1),
.clock (1'b0),
.sum (1'b0),
.aclr (1'b0)
// synopsys translate_on
);
defparam
lpm_mult_component.lpm_widtha = WIDTH+1,
lpm_mult_component.lpm_widthb = WIDTH+1,
lpm_mult_component.lpm_widthp = 2*WIDTH+2,
lpm_mult_component.lpm_widths = 1,
lpm_mult_component.lpm_pipeline = 0,
lpm_mult_component.lpm_type = "LPM_MULT",
lpm_mult_component.lpm_representation = "SIGNED",
lpm_mult_component.lpm_hint = "MAXIMIZE_SPEED=6";
endmodule
|
module pcadder(pc, offset, result);
parameter PC_WIDTH=32;
input [PC_WIDTH-1:0] pc;
input [PC_WIDTH-1:0] offset;
output [PC_WIDTH-1:0] result;
wire dum;
assign {dum,result} = pc + {offset[PC_WIDTH-3:0],2'b0};
endmodule
|
/****************************************************************************
Register File
- Has two read ports (a and b) and one write port (c)
- sel chooses the register to be read/written
****************************************************************************/
module reg_file(clk,resetn,
a_reg, a_readdataout, a_en,
b_reg, b_readdataout, b_en,
c_reg, c_writedatain, c_we);
parameter WIDTH=32;
parameter NUMREGS=32;
parameter LOG2NUMREGS=5;
input clk;
input resetn;
input a_en;
input b_en;
input [LOG2NUMREGS-1:0] a_reg,b_reg,c_reg;
output [WIDTH-1:0] a_readdataout, b_readdataout;
input [WIDTH-1:0] c_writedatain;
input c_we;
altsyncram reg_file1(
.wren_a (c_we&(|c_reg)),
.clock0 (clk),
.clock1 (clk),
.clocken1 (a_en),
.address_a (c_reg[LOG2NUMREGS-1:0]),
.address_b (a_reg[LOG2NUMREGS-1:0]),
.data_a (c_writedatain),
.q_b (a_readdataout)
// synopsys translate_off
,
.aclr0 (1'b0),
.aclr1 (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.data_b (32'b11111111),
.wren_b (1'b0),
.rden_b(1'b1),
.q_a (),
.clocken0 (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0)
// synopsys translate_on
);
defparam
reg_file1.operation_mode = "DUAL_PORT",
reg_file1.width_a = WIDTH,
reg_file1.widthad_a = LOG2NUMREGS,
reg_file1.numwords_a = NUMREGS,
reg_file1.width_b = WIDTH,
reg_file1.widthad_b = LOG2NUMREGS,
reg_file1.numwords_b = NUMREGS,
reg_file1.lpm_type = "altsyncram",
reg_file1.width_byteena_a = 1,
reg_file1.outdata_reg_b = "UNREGISTERED",
reg_file1.indata_aclr_a = "NONE",
reg_file1.wrcontrol_aclr_a = "NONE",
reg_file1.address_aclr_a = "NONE",
reg_file1.rdcontrol_reg_b = "CLOCK1",
reg_file1.address_reg_b = "CLOCK1",
reg_file1.address_aclr_b = "NONE",
reg_file1.outdata_aclr_b = "NONE",
reg_file1.read_during_write_mode_mixed_ports = "OLD_DATA",
reg_file1.ram_block_type = "AUTO",
reg_file1.intended_device_family = "Stratix";
//Reg file duplicated to avoid contention between 2 read
//and 1 write
altsyncram reg_file2(
.wren_a (c_we&(|c_reg)),
.clock0 (clk),
.clock1 (clk),
.clocken1 (b_en),
.address_a (c_reg[LOG2NUMREGS-1:0]),
.address_b (b_reg[LOG2NUMREGS-1:0]),
.data_a (c_writedatain),
.q_b (b_readdataout)
// synopsys translate_off
,
.aclr0 (1'b0),
.aclr1 (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.data_b (32'b11111111),
.rden_b(1'b1),
.wren_b (1'b0),
.q_a (),
.clocken0 (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0)
// synopsys translate_on
);
defparam
reg_file2.operation_mode = "DUAL_PORT",
reg_file2.width_a = WIDTH,
reg_file2.widthad_a = LOG2NUMREGS,
reg_file2.numwords_a = NUMREGS,
reg_file2.width_b = WIDTH,
reg_file2.widthad_b = LOG2NUMREGS,
reg_file2.numwords_b = NUMREGS,
reg_file2.lpm_type = "altsyncram",
reg_file2.width_byteena_a = 1,
reg_file2.outdata_reg_b = "UNREGISTERED",
reg_file2.indata_aclr_a = "NONE",
reg_file2.wrcontrol_aclr_a = "NONE",
reg_file2.address_aclr_a = "NONE",
reg_file2.rdcontrol_reg_b = "CLOCK1",
reg_file2.address_reg_b = "CLOCK1",
reg_file2.address_aclr_b = "NONE",
reg_file2.outdata_aclr_b = "NONE",
reg_file2.read_during_write_mode_mixed_ports = "OLD_DATA",
reg_file2.ram_block_type = "AUTO",
reg_file2.intended_device_family = "Stratix";
endmodule
|
/****************************************************************************
Shifter unit
Opcode Table:
sign_ext dir
0 0 | ShiftLeft
0 1 | ShiftRightLogic
1 1 | ShiftRightArith
****************************************************************************/
module shifter(clk, resetn,
opB, sa,
op, start, stalled,
dst,
result);
parameter WIDTH=32;
input clk;
input resetn;
input [WIDTH-1:0] opB;
input [4:0] sa; // Shift Amount
input [2-1:0] op;
input start;
output stalled;
input [4:0] dst;
output [WIDTH-1:0] result;
wire sign_ext;
wire shift_direction;
assign sign_ext=op[1];
assign shift_direction=op[0];
reg [WIDTH-1:0] shifter;
reg shift_state;
reg [4:0] shift_count;
wire wasjustbusy;
wire is_zeroshift;
wire was_zeroshift;
wire is_nop;
wire hi_bit, lo_bit;
assign hi_bit=sign_ext&opB[WIDTH-1];
assign lo_bit=0;
// to separate nops from zero shifts (which occur) we hack this
assign is_nop=~(|dst);
assign is_zeroshift=(~|sa)&~is_nop;
assign stalled = (start&(~wasjustbusy)&~is_nop&~was_zeroshift)|shift_state;
assign result=shifter;
register wasjustbusy_reg(shift_state,clk,resetn,1'b1,wasjustbusy);
defparam wasjustbusy_reg.WIDTH=1;
register was_zeroshift_reg(is_zeroshift&~was_zeroshift,
clk,resetn,start,was_zeroshift);
defparam was_zeroshift_reg.WIDTH=1;
always @(posedge clk or negedge resetn)
begin
if (!resetn)
begin
shifter<=0;
shift_state<=0;
shift_count<=0;
end
else
begin
case(shift_state)
0:
if (start&~wasjustbusy)
begin
shift_count<=sa;
shifter<=opB;
if (!is_zeroshift && !is_nop)
shift_state<=1;
end
default:
begin
if (shift_count==1)
shift_state<=0;
shift_count<=shift_count-1;
shifter[31]<=(shift_direction) ? hi_bit : shifter[30];
shifter[30]<=(shift_direction) ? shifter[31] : shifter[29];
shifter[29]<=(shift_direction) ? shifter[30] : shifter[28];
shifter[28]<=(shift_direction) ? shifter[29] : shifter[27];
shifter[27]<=(shift_direction) ? shifter[28] : shifter[26];
shifter[26]<=(shift_direction) ? shifter[27] : shifter[25];
shifter[25]<=(shift_direction) ? shifter[26] : shifter[24];
shifter[24]<=(shift_direction) ? shifter[25] : shifter[23];
shifter[23]<=(shift_direction) ? shifter[24] : shifter[22];
shifter[22]<=(shift_direction) ? shifter[23] : shifter[21];
shifter[21]<=(shift_direction) ? shifter[22] : shifter[20];
shifter[20]<=(shift_direction) ? shifter[21] : shifter[19];
shifter[19]<=(shift_direction) ? shifter[20] : shifter[18];
shifter[18]<=(shift_direction) ? shifter[19] : shifter[17];
shifter[17]<=(shift_direction) ? shifter[18] : shifter[16];
shifter[16]<=(shift_direction) ? shifter[17] : shifter[15];
shifter[15]<=(shift_direction) ? shifter[16] : shifter[14];
shifter[14]<=(shift_direction) ? shifter[15] : shifter[13];
shifter[13]<=(shift_direction) ? shifter[14] : shifter[12];
shifter[12]<=(shift_direction) ? shifter[13] : shifter[11];
shifter[11]<=(shift_direction) ? shifter[12] : shifter[10];
shifter[10]<=(shift_direction) ? shifter[11] : shifter[9];
shifter[9]<=(shift_direction) ? shifter[10] : shifter[8];
shifter[8]<=(shift_direction) ? shifter[9] : shifter[7];
shifter[7]<=(shift_direction) ? shifter[8] : shifter[6];
shifter[6]<=(shift_direction) ? shifter[7] : shifter[5];
shifter[5]<=(shift_direction) ? shifter[6] : shifter[4];
shifter[4]<=(shift_direction) ? shifter[5] : shifter[3];
shifter[3]<=(shift_direction) ? shifter[4] : shifter[2];
shifter[2]<=(shift_direction) ? shifter[3] : shifter[1];
shifter[1]<=(shift_direction) ? shifter[2] : shifter[0];
shifter[0]<=(shift_direction) ? shifter[1] : lo_bit;
end
endcase
end
end
endmodule
|
module signext16 ( in, out);
input [15:0] in;
output [31:0] out;
assign out={{16{in[15]}},in[15:0]};
endmodule
|
//Deepak: Commeted due to error: Module cannot be declared more than once
//`include "lo_reg.v"
//`include "hi_reg.v"
//`include "data_mem_stall.v"
//`include "mul.v"
//`include "shifter_perbit_pipe.v"
//`include "logic_unit.v"
//`include "addersub_slt.v"
//`include "merge26lo.v"
//`include "branchresolve.v"
//`include "pcadder.v"
//`include "signext16.v"
//`include "reg_file_pipe.v"
//`include "ifetch_pipe.v"
//`include "components.v"
/*To remove an instruction and the associated logic, comment the specific `defines*/
/*Instruction Set and Processor Logic Optimization Block*/
`define ADDI
`define ADDIU
`define ANDI
`define SPECIAL
`define REGIMM
`define J
`define JAL
`define BEQ
`define BNE
`define BLEZ
`define BGTZ
`define ADDI
`define ADDIU
`define SLTI
`define SLTIU
`define ANDI
`define ORI
`define XORI
`define LUI
`define LB
`define LH
`define LWL
`define LW
`define LBU
`define LHU
`define LWR
`define SB
`define SH
`define SWL
`define SW
`define SWR
/****** FUNCTION CLASS - bits 5...0 *******/
`define SLL
`define SRL
`define SRA
`define SLLV
`define SRLV
`define SRAV
`define JR
`define JALR
`define MFHI
`define MTHI
`define MFLO
`define MTLO
`define MULT
`define MULTU
`define ADD
`define ADDU
`define SUB
`define SUBU
`define AND
`define OR
`define XOR
`define NOR
`define SLT
`define SLTU
`define BLTZ
`define BGEZ
/*End of Instruction Set and Processor Logic Optimization Block*/
module system (
clk,
resetn,
boot_iaddr,
boot_idata,
boot_iwe,
boot_daddr,
boot_ddata,
boot_dwe,
reg_file_b_readdataout,
dataInNorth,dataOutNorth,wrNorth,rdNorth,fullNorth,emptyNorth,overflowNorth,
dataInSouth,dataOutSouth,wrSouth,rdSouth,fullSouth,emptySouth,overflowSouth,
dataInWest,dataOutWest,wrWest,rdWest,fullWest,emptyWest,overflowWest,
dataInEast,dataOutEast,wrEast,rdEast,fullEast,emptyEast,overflowEast,
wrGeneric,genericDataOut); //FIFO Signals
/************************* IO Declarations *********************/
`include "isa.v"
input clk;
input resetn;
input [31:0] boot_iaddr;
input [31:0] boot_idata;
input boot_iwe;
input [31:0] boot_daddr;
input [31:0] boot_ddata;
input boot_dwe;
input [31:0] dataInNorth; //FIFO
input [31:0] dataInSouth; //FIFO
input [31:0] dataInWest; //FIFO
input [31:0] dataInEast; //FIFO
output [31:0] dataOutNorth; //FIFO
output [31:0] dataOutSouth; //FIFO
output [31:0] dataOutWest; //FIFO
output [31:0] dataOutEast; //FIFO
output [31:0] genericDataOut;
output wrNorth; //FIFO write signal
output wrSouth; //FIFO write signal
output wrEast; //FIFO write signal
output wrWest; //FIFO write signal
output wrGeneric;
output rdNorth; //FIFO write signal
output rdSouth; //FIFO write signal
output rdEast; //FIFO write signal
output rdWest; //FIFO write signal
input fullNorth; //FIFO signal which indicates whether FIFO is full or not
input fullSouth;
input fullEast;
input fullWest;
input emptyNorth; //FIFO signal which indicates whether FIFO is full or not
input emptySouth;
input emptyEast;
input emptyWest;
input overflowNorth; //FIFO signal which indicates whether FIFO has overflowed or not
input overflowSouth;
input overflowEast;
input overflowWest;
output [31:0] reg_file_b_readdataout;
/*********************** Signal Declarations *******************/
wire branch_mispred;
wire stall_2nd_delayslot;
wire has_delayslot;
wire haz_zeroer0_q_pipereg5_q;
wire haz_zeroer_q_pipereg5_q;
// Datapath signals declarations
wire addersub_result_slt;
wire [ 31 : 0 ] addersub_result;
wire [ 31 : 0 ] logic_unit_result;
wire [ 31 : 0 ] shifter_result;
wire ctrl_shifter_stalled;
wire [ 31 : 0 ] mul_lo;
wire [ 31 : 0 ] mul_hi;
wire [ 31 : 0 ] ifetch_pc_out;
wire [ 31 : 0 ] ifetch_instr;
wire [ 5 : 0 ] ifetch_opcode;
wire [ 5 : 0 ] ifetch_func;
wire [ 4 : 0 ] ifetch_rs;
wire [ 4 : 0 ] ifetch_rt;
wire [ 4 : 0 ] ifetch_rd;
wire [ 25 : 0 ] ifetch_instr_index;
wire [ 15 : 0 ] ifetch_offset;
wire [ 4 : 0 ] ifetch_sa;
wire [ 31 : 0 ] ifetch_next_pc;
wire [ 31 : 0 ] data_mem_d_loadresult;
wire ctrl_data_mem_stalled;
wire [ 31 : 0 ] pcadder_result;
wire [ 31 : 0 ] signext16_out;
wire [ 31 : 0 ] reg_file_b_readdataout;
wire [ 31 : 0 ] reg_file_a_readdataout;
wire [ 31 : 0 ] merge26lo_out;
wire branchresolve_eqz;
wire branchresolve_gez;
wire branchresolve_gtz;
wire branchresolve_lez;
wire branchresolve_ltz;
wire branchresolve_ne;
wire branchresolve_eq;
wire [ 31 : 0 ] hi_reg_q;
wire [ 31 : 0 ] lo_reg_q;
wire [ 31 : 0 ] const6_out;
wire [ 31 : 0 ] const7_out;
wire [ 31 : 0 ] const_out;
wire [ 31 : 0 ] pipereg_q;
wire [ 25 : 0 ] pipereg1_q;
wire [ 4 : 0 ] pipereg2_q;
wire [ 4 : 0 ] pipereg5_q;
wire [ 31 : 0 ] pipereg3_q;
wire [ 31 : 0 ] fakedelay_q;
wire [ 31 : 0 ] nop_q;
wire [ 4 : 0 ] zeroer_q;
wire [ 4 : 0 ] zeroer0_q;
wire [ 4 : 0 ] zeroer4_q;
wire [ 4 : 0 ] mux3to1_shifter_sa_out;
wire [ 31 : 0 ] mux3to1_ifetch_load_data_out;
wire mux6to1_ifetch_load_out;
wire [ 31 : 0 ] mux7to1_reg_file_c_writedatain_out;
wire [ 31 : 0 ] mux2to1_addersub_opA_out;
wire [ 31 : 0 ] mux2to1_pipereg_d_out;
wire [ 4 : 0 ] mux3to1_zeroer4_d_out;
wire [ 31 : 0 ] mux3to1_nop_d_out;
wire [ 5 : 0 ] pipereg8_q;
wire [ 5 : 0 ] pipereg9_q;
wire [ 4 : 0 ] pipereg10_q;
/***************** Control Signals ***************/
//Decoded Opcode signal declarations
reg [ 1 : 0 ] ctrl_mux3to1_nop_d_sel;
reg [ 1 : 0 ] ctrl_mux3to1_zeroer4_d_sel;
reg ctrl_mux2to1_pipereg_d_sel;
reg ctrl_mux2to1_addersub_opA_sel;
reg ctrl_zeroer0_en;
reg [ 4 : 0 ] ctrl_mux7to1_reg_file_c_writedatain_sel; //Deepak Increased select lines
reg [ 2 : 0 ] ctrl_mux6to1_ifetch_load_sel;
reg [ 1 : 0 ] ctrl_mux3to1_ifetch_load_data_sel;
reg [ 1 : 0 ] ctrl_mux3to1_shifter_sa_sel;
reg ctrl_zeroer4_en;
reg ctrl_zeroer_en;
reg [ 2 : 0 ] ctrl_addersub_op;
reg ctrl_ifetch_op;
reg [ 3 : 0 ] ctrl_data_mem_op;
reg ctrl_mul_op;
reg [ 1 : 0 ] ctrl_logic_unit_op;
reg [ 1 : 0 ] ctrl_shifter_op;
//Enable signal declarations
reg ctrl_reg_file_c_we;
reg ctrl_reg_file_b_en;
reg ctrl_lo_reg_en;
reg ctrl_branchresolve_en;
reg ctrl_hi_reg_en;
reg ctrl_reg_file_a_en;
reg ctrl_ifetch_we;
reg ctrl_ifetch_en;
reg ctrl_data_mem_en;
reg ctrl_shifter_start;
//Other Signals
wire squash_stage2;
wire stall_out_stage2;
wire squash_stage1;
wire stall_out_stage1;
wire ctrl_pipereg_squashn;
wire ctrl_pipereg5_squashn;
wire ctrl_pipereg2_squashn;
wire ctrl_pipereg3_squashn;
wire ctrl_pipereg1_squashn;
wire ctrl_pipereg8_squashn;
wire ctrl_pipereg9_squashn;
wire ctrl_pipereg10_squashn;
wire ctrl_pipereg_resetn;
wire ctrl_pipereg5_resetn;
wire ctrl_pipereg2_resetn;
wire ctrl_pipereg3_resetn;
wire ctrl_pipereg1_resetn;
wire ctrl_pipereg8_resetn;
wire ctrl_pipereg9_resetn;
wire ctrl_pipereg10_resetn;
wire ctrl_pipereg_en;
wire ctrl_pipereg5_en;
wire ctrl_pipereg2_en;
wire ctrl_pipereg3_en;
wire ctrl_pipereg1_en;
wire ctrl_pipereg8_en;
wire ctrl_pipereg9_en;
wire ctrl_pipereg10_en;
wire [31:0] tempFifoDataInNorth;
wire [31:0] tempFifoDataInSouth;
wire [31:0] tempFifoDataInEast;
wire [31:0] tempFifoDataInWest;
wire [31:0] northEmpty;
wire [31:0] southEmpty;
wire [31:0] eastEmpty;
wire [31:0] westEmpty;
wire [31:0] northFull;
wire [31:0] southFull;
wire [31:0] eastFull;
wire [31:0] westFull;
reg writeFifoWest;
reg writeFifoEast;
reg writeFifoNorth;
reg writeFifoSouth;
reg readFifoWest;
reg readFifoEast;
reg readFifoNorth;
reg readFifoSouth;
reg writeGenOut;
reg [31:0] tempDataOutNorth;
reg [31:0] tempDataOutSouth;
reg [31:0] tempDataOutEast;
reg [31:0] tempDataOutWest;
reg [31:0] tempDataOutGeneric;
/*****Parameter Declarations and Port Map*******/
parameter NorthIn = 32'h00001000;
parameter NorthOut = 32'h00001004;
parameter SouthIn = 32'h00001008;
parameter SouthOut = 32'h0000100c;
parameter EastIn = 32'h00001010;
parameter EastOut = 32'h00001014;
parameter WestIn = 32'h00001018;
parameter WestOut = 32'h0000101c;
parameter NorthEmptyPort = 32'h00001020;
parameter NorthFullPort = 32'h00001024;
parameter SouthEmptyPort = 32'h00001028;
parameter SouthFullPort = 32'h0000102c;
parameter EastEmptyPort = 32'h00001030;
parameter EastFullPort = 32'h00001034;
parameter WestEmptyPort = 32'h00001038;
parameter WestFullPort = 32'h0000103c;
parameter genericDataOutPort = 32'h00001200;
/*********Parameter Declartions End************/
assign northFull = 32'h00000000|fullNorth;
assign southFull = 32'h00000000|fullSouth;
assign eastFull = 32'h00000000|fullEast;
assign westFull = 32'h00000000|fullWest;
assign northEmpty = 32'h00000000|emptyNorth;
assign southEmpty = 32'h00000000|emptySouth;
assign eastEmpty = 32'h00000000|emptyEast;
assign westEmpty = 32'h00000000|emptyWest;
// Port Map Table
// ****************
// 0x1000 North In
// 0x1004 North Out
// 0x1008 South In
// 0x100c South Out
// 0x1010 East In
// 0x1014 East Out
// 0x1018 West In
// 0x101c West Out
//Software will check the status of "full" mapped registers before writing.
//That is write as long as full is not high
//Software will check the status of "empty" mapped registers before read.
//That is read as long as empty is not high
// 0x1020 NorthEmpty
// 0x1024 NorthFull
// 0x1028 SouthEmpty
// 0x102c SouthFull
// 0x1030 EastEmpty
// 0x1034 EastFull
// 0x1038 WestEmpty
// 0x103c WestFull
/********************Store (Moving data out of the processor **************************/
//assign dataOutWest = (addersub_result==WestOut) ? reg_file_b_readdataout : 32'hxxxxxxxx;
assign dataOutWest = tempDataOutWest;
assign wrWest = writeFifoWest;
//assign dataOutEast = (addersub_result==EastOut) ? reg_file_b_readdataout : 32'hxxxxxxxx;
assign dataOutEast = tempDataOutEast;
assign wrEast = writeFifoEast;
//assign dataOutNorth = (addersub_result==NorthOut) ? reg_file_b_readdataout : 32'hxxxxxxxx;
assign dataOutNorth = tempDataOutNorth;
assign wrNorth = writeFifoNorth;
//assign dataOutSouth = (addersub_result==SouthOut) ? reg_file_b_readdataout : 32'hxxxxxxxx;
assign dataOutSouth = tempDataOutSouth;
assign wrSouth = writeFifoSouth;
//assign genericDataOut = (addersub_result==genericDataOutPort) ? reg_file_b_readdataout : 32'hxxxxxxxx;
assign wrGeneric = writeGenOut;
assign genericDataOut = tempDataOutGeneric;
always@ (posedge clk) begin
writeFifoWest <= (addersub_result==WestOut) ? 1'b1:1'b0;
writeFifoEast <= (addersub_result==EastOut) ? 1'b1:1'b0;
writeFifoNorth <= (addersub_result==NorthOut) ? 1'b1:1'b0;
writeFifoSouth <= (addersub_result==SouthOut) ? 1'b1:1'b0;
writeGenOut <= (addersub_result==genericDataOutPort) ? 1'b1:1'b0;
tempDataOutWest <= (addersub_result==WestOut) ? reg_file_b_readdataout : 32'hxxxxxxxx;
tempDataOutEast <= (addersub_result==EastOut) ? reg_file_b_readdataout : 32'hxxxxxxxx;
tempDataOutNorth <= (addersub_result==NorthOut) ? reg_file_b_readdataout : 32'hxxxxxxxx;
tempDataOutSouth <= (addersub_result==SouthOut) ? reg_file_b_readdataout : 32'hxxxxxxxx;
tempDataOutGeneric <= (addersub_result==genericDataOutPort) ? reg_file_b_readdataout : 32'hxxxxxxxx;
//readFifoNorth <= (addersub_result==NorthIn) ? 1'b1:1'b0;
//readFifoSouth <= (addersub_result==SouthIn) ? 1'b1:1'b0;
//readFifoEast <= (addersub_result==EastIn) ? 1'b1:1'b0;
//readFifoWest <= (addersub_result==WestIn) ? 1'b1:1'b0;
//tempFifoDataInEast = (eastEmpty!=32'h00000001) ? dataInEast : 32'hxxxxxxxx;
//tempFifoDataInWest = (westEmpty!=32'h00000001) ? dataInWest : 32'hxxxxxxxx;
//tempFifoDataInNorth = (northEmpty!=32'h00000001) ? dataInNorth : 32'hxxxxxxxx;
//tempFifoDataInSouth = (southEmpty!=32'h00000001) ? dataInSouth : 32'hxxxxxxxx;
end
/********************Load (Taking data into processor from output port*******************/
//If east port has something (indicated by eastEmpty != 1), read data to temp datain east
//assign tempFifoDataInEast = (eastEmpty!=32'h00000001) ? dataInEast : 32'hxxxxxxxx;
assign tempFifoDataInEast = dataInEast;
assign rdEast = (addersub_result==EastIn) ? 1'b1:1'b0;
//assign rdEast = readFifoEast;
//assign tempFifoDataInWest = (westEmpty!=32'h00000001) ? dataInWest : 32'hxxxxxxxx;
assign tempFifoDataInWest = dataInWest;
assign rdWest = (addersub_result==WestIn) ? 1'b1:1'b0;
//assign rdWest = readFifoWest;
//assign tempFifoDataInNorth = (northEmpty!=32'h00000001) ? dataInNorth : 32'hxxxxxxxx;
assign tempFifoDataInNorth = dataInNorth;
assign rdNorth = (addersub_result==NorthIn) ? 1'b1:1'b0;
//assign rdNorth = readFifoNorth;
//assign tempFifoDataInSouth = (southEmpty!=32'h00000001) ? dataInSouth : 32'hxxxxxxxx;
assign tempFifoDataInSouth = dataInSouth;
assign rdSouth = (addersub_result==SouthIn) ? 1'b1:1'b0;
//assign rdSouth = readFifoSouth;
/****************************** Control **************************/
//Decode Logic for Opcode and Multiplex Select signals
always @(ifetch_opcode or ifetch_func or ifetch_rt)
begin
// Initialize control opcodes to zero
ctrl_mux3to1_zeroer4_d_sel = 0;
ctrl_mux2to1_pipereg_d_sel = 0;
ctrl_zeroer0_en = 0;
ctrl_zeroer4_en = 0;
ctrl_zeroer_en = 0;
casex (ifetch_opcode)
`ifdef ADDI
OP_ADDI:
begin
ctrl_mux3to1_zeroer4_d_sel = 2;
ctrl_mux2to1_pipereg_d_sel = 0;
ctrl_zeroer4_en = 1;
ctrl_zeroer_en = 1;
end
`endif
`ifdef ADDIU
OP_ADDIU:
begin
ctrl_mux3to1_zeroer4_d_sel = 2;
ctrl_mux2to1_pipereg_d_sel = 0;
ctrl_zeroer4_en = 1;
ctrl_zeroer_en = 1;
end
`endif
`ifdef ANDI
OP_ANDI:
begin
ctrl_mux3to1_zeroer4_d_sel = 2;
ctrl_mux2to1_pipereg_d_sel = 1;
ctrl_zeroer4_en = 1;
ctrl_zeroer_en = 1;
end
`endif
`ifdef BEQ
OP_BEQ:
begin
ctrl_mux2to1_pipereg_d_sel = 0;
ctrl_zeroer0_en = 1;
ctrl_zeroer_en = 1;
end
`endif
`ifdef BGTZ
OP_BGTZ:
begin
ctrl_mux2to1_pipereg_d_sel = 0;
ctrl_zeroer_en = 1;
end
`endif
`ifdef BLEZ
OP_BLEZ:
begin
ctrl_mux2to1_pipereg_d_sel = 0;
ctrl_zeroer_en = 1;
end
`endif
`ifdef BNE
OP_BNE:
begin
ctrl_mux2to1_pipereg_d_sel = 0;
ctrl_zeroer0_en = 1;
ctrl_zeroer_en = 1;
end
`endif
`ifdef JAL
OP_JAL:
begin
ctrl_mux3to1_zeroer4_d_sel = 0;
ctrl_zeroer4_en = 1;
end
`endif
`ifdef LB
OP_LB:
begin
ctrl_mux3to1_zeroer4_d_sel = 2;
ctrl_mux2to1_pipereg_d_sel = 0;
ctrl_zeroer4_en = 1;
ctrl_zeroer_en = 1;
end
`endif
`ifdef LBU
OP_LBU:
begin
ctrl_mux3to1_zeroer4_d_sel = 2;
ctrl_mux2to1_pipereg_d_sel = 0;
ctrl_zeroer4_en = 1;
ctrl_zeroer_en = 1;
end
`endif
`ifdef LW
OP_LH:
begin
ctrl_mux3to1_zeroer4_d_sel = 2;
ctrl_mux2to1_pipereg_d_sel = 0;
ctrl_zeroer4_en = 1;
ctrl_zeroer_en = 1;
end
`endif
`ifdef LHU
OP_LHU:
begin
ctrl_mux3to1_zeroer4_d_sel = 2;
ctrl_mux2to1_pipereg_d_sel = 0;
ctrl_zeroer4_en = 1;
ctrl_zeroer_en = 1;
end
`endif
`ifdef LUI
OP_LUI:
begin
ctrl_mux3to1_zeroer4_d_sel = 2;
ctrl_mux2to1_pipereg_d_sel = 1;
ctrl_zeroer4_en = 1;
end
`endif
`ifdef LW
OP_LW:
begin
ctrl_mux3to1_zeroer4_d_sel = 2;
ctrl_mux2to1_pipereg_d_sel = 0;
ctrl_zeroer4_en = 1;
ctrl_zeroer_en = 1;
end
`endif
`ifdef ORI
OP_ORI:
begin
ctrl_mux3to1_zeroer4_d_sel = 2;
ctrl_mux2to1_pipereg_d_sel = 1;
ctrl_zeroer4_en = 1;
ctrl_zeroer_en = 1;
end
`endif
OP_REGIMM:
casex (ifetch_rt[0])
`ifdef BGEZ
FUNC_BGEZ:
begin
ctrl_mux2to1_pipereg_d_sel = 0;
ctrl_zeroer_en = 1;
end
`endif
`ifdef BLTZ
FUNC_BLTZ:
begin
ctrl_mux2to1_pipereg_d_sel = 0;
ctrl_zeroer_en = 1;
end
`endif
endcase
`ifdef SB
OP_SB:
begin
ctrl_mux2to1_pipereg_d_sel = 0;
ctrl_zeroer0_en = 1;
ctrl_zeroer_en = 1;
end
`endif
`ifdef SH
OP_SH:
begin
ctrl_mux2to1_pipereg_d_sel = 0;
ctrl_zeroer0_en = 1;
ctrl_zeroer_en = 1;
end
`endif
`ifdef SLTI
OP_SLTI:
begin
ctrl_mux3to1_zeroer4_d_sel = 2;
ctrl_mux2to1_pipereg_d_sel = 0;
ctrl_zeroer4_en = 1;
ctrl_zeroer_en = 1;
end
`endif
`ifdef SLTIU
OP_SLTIU:
begin
ctrl_mux3to1_zeroer4_d_sel = 2;
ctrl_mux2to1_pipereg_d_sel = 0;
ctrl_zeroer4_en = 1;
ctrl_zeroer_en = 1;
end
`endif
OP_SPECIAL:
casex (ifetch_func)
`ifdef ADD
FUNC_ADD:
begin
ctrl_mux3to1_zeroer4_d_sel = 1;
ctrl_zeroer0_en = 1;
ctrl_zeroer4_en = 1;
ctrl_zeroer_en = 1;
end
`endif
`ifdef ADDU
FUNC_ADDU:
begin
ctrl_mux3to1_zeroer4_d_sel = 1;
ctrl_zeroer0_en = 1;
ctrl_zeroer4_en = 1;
ctrl_zeroer_en = 1;
end
`endif
`ifdef AND
FUNC_AND:
begin
ctrl_mux3to1_zeroer4_d_sel = 1;
ctrl_zeroer0_en = 1;
ctrl_zeroer4_en = 1;
ctrl_zeroer_en = 1;
end
`endif
`ifdef JALR
FUNC_JALR:
begin
ctrl_mux3to1_zeroer4_d_sel = 0;
ctrl_zeroer4_en = 1;
ctrl_zeroer_en = 1;
end
`endif
`ifdef JR
FUNC_JR:
ctrl_zeroer_en = 1;
`endif
`ifdef MFHI
FUNC_MFHI:
begin
ctrl_mux3to1_zeroer4_d_sel = 1;
ctrl_zeroer4_en = 1;
end
`endif
`ifdef MFLO
FUNC_MFLO:
begin
ctrl_mux3to1_zeroer4_d_sel = 1;
ctrl_zeroer4_en = 1;
end
`endif
`ifdef MULT
FUNC_MULT:
begin
ctrl_zeroer0_en = 1;
ctrl_zeroer_en = 1;
end
`endif
`ifdef MULTU
FUNC_MULTU:
begin
ctrl_zeroer0_en = 1;
ctrl_zeroer_en = 1;
end
`endif
`ifdef NOR
FUNC_NOR:
begin
ctrl_mux3to1_zeroer4_d_sel = 1;
ctrl_zeroer0_en = 1;
ctrl_zeroer4_en = 1;
ctrl_zeroer_en = 1;
end
`endif
`ifdef OR
FUNC_OR:
begin
ctrl_mux3to1_zeroer4_d_sel = 1;
ctrl_zeroer0_en = 1;
ctrl_zeroer4_en = 1;
ctrl_zeroer_en = 1;
end
`endif
`ifdef SLL
FUNC_SLL:
begin
ctrl_mux3to1_zeroer4_d_sel = 1;
ctrl_zeroer0_en = 1;
ctrl_zeroer4_en = 1;
end
`endif
`ifdef SLLV
FUNC_SLLV:
begin
ctrl_mux3to1_zeroer4_d_sel = 1;
ctrl_zeroer0_en = 1;
ctrl_zeroer4_en = 1;
ctrl_zeroer_en = 1;
end
`endif
`ifdef SLT
FUNC_SLT:
begin
ctrl_mux3to1_zeroer4_d_sel = 1;
ctrl_zeroer0_en = 1;
ctrl_zeroer4_en = 1;
ctrl_zeroer_en = 1;
end
`endif
`ifdef SLTU
FUNC_SLTU:
begin
ctrl_mux3to1_zeroer4_d_sel = 1;
ctrl_zeroer0_en = 1;
ctrl_zeroer4_en = 1;
ctrl_zeroer_en = 1;
end
`endif
`ifdef SRA
FUNC_SRA:
begin
ctrl_mux3to1_zeroer4_d_sel = 1;
ctrl_zeroer0_en = 1;
ctrl_zeroer4_en = 1;
end
`endif
`ifdef SRAV
FUNC_SRAV:
begin
ctrl_mux3to1_zeroer4_d_sel = 1;
ctrl_zeroer0_en = 1;
ctrl_zeroer4_en = 1;
ctrl_zeroer_en = 1;
end
`endif
`ifdef SRL
FUNC_SRL:
begin
ctrl_mux3to1_zeroer4_d_sel = 1;
ctrl_zeroer0_en = 1;
ctrl_zeroer4_en = 1;
end
`endif
`ifdef SRLV
FUNC_SRLV:
begin
ctrl_mux3to1_zeroer4_d_sel = 1;
ctrl_zeroer0_en = 1;
ctrl_zeroer4_en = 1;
ctrl_zeroer_en = 1;
end
`endif
`ifdef SUB
FUNC_SUB:
begin
ctrl_mux3to1_zeroer4_d_sel = 1;
ctrl_zeroer0_en = 1;
ctrl_zeroer4_en = 1;
ctrl_zeroer_en = 1;
end
`endif
`ifdef SUBU
FUNC_SUBU:
begin
ctrl_mux3to1_zeroer4_d_sel = 1;
ctrl_zeroer0_en = 1;
ctrl_zeroer4_en = 1;
ctrl_zeroer_en = 1;
end
`endif
`ifdef XOR
FUNC_XOR:
begin
ctrl_mux3to1_zeroer4_d_sel = 1;
ctrl_zeroer0_en = 1;
ctrl_zeroer4_en = 1;
ctrl_zeroer_en = 1;
end
`endif
endcase
`ifdef SW
OP_SW:
begin
ctrl_mux2to1_pipereg_d_sel = 0;
ctrl_zeroer0_en = 1;
ctrl_zeroer_en = 1;
end
`endif
`ifdef XORI
OP_XORI:
begin
ctrl_mux3to1_zeroer4_d_sel = 2;
ctrl_mux2to1_pipereg_d_sel = 1;
ctrl_zeroer4_en = 1;
ctrl_zeroer_en = 1;
end
`endif
endcase
end
//Logic for enable signals in Pipe Stage 1
always@(ifetch_opcode or ifetch_func or ifetch_rt[0] or stall_out_stage2 or haz_zeroer_q_pipereg5_q or haz_zeroer0_q_pipereg5_q)
begin
ctrl_reg_file_b_en = 1 &~haz_zeroer0_q_pipereg5_q&~haz_zeroer_q_pipereg5_q&~stall_out_stage2;
ctrl_reg_file_a_en = 1 &~haz_zeroer0_q_pipereg5_q&~haz_zeroer_q_pipereg5_q&~stall_out_stage2;
ctrl_ifetch_en = 1 &~haz_zeroer0_q_pipereg5_q&~haz_zeroer_q_pipereg5_q&~stall_out_stage2;
end
//Decode Logic for Opcode and Multiplex Select signals
always@(pipereg8_q or pipereg9_q or pipereg10_q or addersub_result)
begin
// Initialize control opcodes to zero
ctrl_mux3to1_nop_d_sel = 0;
ctrl_mux2to1_addersub_opA_sel = 0;
ctrl_mux7to1_reg_file_c_writedatain_sel = 0;
ctrl_mux6to1_ifetch_load_sel = 0;
ctrl_mux3to1_ifetch_load_data_sel = 0;
ctrl_mux3to1_shifter_sa_sel = 0;
ctrl_addersub_op = 0;
ctrl_ifetch_op = 0;
ctrl_data_mem_op = 0;
ctrl_mul_op = 0;
ctrl_logic_unit_op = 0;
ctrl_shifter_op = 0;
casex (pipereg8_q)
`ifdef ADDI
OP_ADDI:
begin
ctrl_mux3to1_nop_d_sel = 2;
ctrl_mux2to1_addersub_opA_sel = 0;
ctrl_mux7to1_reg_file_c_writedatain_sel = 6;
ctrl_addersub_op = 3;
end
`endif
`ifdef ADDIU
OP_ADDIU:
begin
ctrl_mux3to1_nop_d_sel = 2;
ctrl_mux2to1_addersub_opA_sel = 0;
ctrl_mux7to1_reg_file_c_writedatain_sel = 6;
ctrl_addersub_op = 1;
end
`endif
`ifdef ANDI
OP_ANDI:
begin
ctrl_mux3to1_nop_d_sel = 2;
ctrl_mux7to1_reg_file_c_writedatain_sel = 4;
ctrl_logic_unit_op = 0;
end
`endif
`ifdef BEQ
OP_BEQ:
begin
ctrl_mux6to1_ifetch_load_sel = 5;
ctrl_mux3to1_ifetch_load_data_sel = 2;
ctrl_ifetch_op = 0;
end
`endif
`ifdef BGTZ
OP_BGTZ:
begin
ctrl_mux6to1_ifetch_load_sel = 0;
ctrl_mux3to1_ifetch_load_data_sel = 2;
ctrl_ifetch_op = 0;
end
`endif
`ifdef BLEZ
OP_BLEZ:
begin
ctrl_mux6to1_ifetch_load_sel = 3;
ctrl_mux3to1_ifetch_load_data_sel = 2;
ctrl_ifetch_op = 0;
end
`endif
`ifdef BNE
OP_BNE:
begin
ctrl_mux6to1_ifetch_load_sel = 4;
ctrl_mux3to1_ifetch_load_data_sel = 2;
ctrl_ifetch_op = 0;
end
`endif
`ifdef J
OP_J:
begin
ctrl_mux3to1_ifetch_load_data_sel = 1;
ctrl_ifetch_op = 1;
end
`endif
`ifdef JAL
OP_JAL:
begin
ctrl_mux2to1_addersub_opA_sel = 1;
ctrl_mux7to1_reg_file_c_writedatain_sel = 6;
ctrl_mux3to1_ifetch_load_data_sel = 1;
ctrl_addersub_op = 1;
ctrl_ifetch_op = 1;
end
`endif
`ifdef LB
OP_LB:
begin
ctrl_mux3to1_nop_d_sel = 2;
ctrl_mux2to1_addersub_opA_sel = 0;
ctrl_mux7to1_reg_file_c_writedatain_sel = 2;
ctrl_addersub_op = 3;
ctrl_data_mem_op = 7;
end
`endif
`ifdef LBU
OP_LBU:
begin
ctrl_mux3to1_nop_d_sel = 2;
ctrl_mux2to1_addersub_opA_sel = 0;
ctrl_mux7to1_reg_file_c_writedatain_sel = 2;
ctrl_addersub_op = 3;
ctrl_data_mem_op = 3;
end
`endif
`ifdef LH
OP_LH:
begin
ctrl_mux3to1_nop_d_sel = 2;
ctrl_mux2to1_addersub_opA_sel = 0;
ctrl_mux7to1_reg_file_c_writedatain_sel = 2;
ctrl_addersub_op = 3;
ctrl_data_mem_op = 5;
end
`endif
`ifdef LHU
OP_LHU:
begin
ctrl_mux3to1_nop_d_sel = 2;
ctrl_mux2to1_addersub_opA_sel = 0;
ctrl_mux7to1_reg_file_c_writedatain_sel = 2;
ctrl_addersub_op = 3;
ctrl_data_mem_op = 1;
end
`endif
`ifdef LUI
OP_LUI:
begin
ctrl_mux3to1_nop_d_sel = 2;
ctrl_mux7to1_reg_file_c_writedatain_sel = 3;
ctrl_mux3to1_shifter_sa_sel = 1;
ctrl_shifter_op = 0;
end
`endif
`ifdef LW
OP_LW:
begin
casex(addersub_result)
NorthIn: begin ctrl_mux7to1_reg_file_c_writedatain_sel = 8; end
SouthIn: begin ctrl_mux7to1_reg_file_c_writedatain_sel = 9; end
EastIn: begin ctrl_mux7to1_reg_file_c_writedatain_sel = 10; end
WestIn: begin ctrl_mux7to1_reg_file_c_writedatain_sel = 11; end
NorthEmptyPort:begin ctrl_mux7to1_reg_file_c_writedatain_sel = 12; end
SouthEmptyPort:begin ctrl_mux7to1_reg_file_c_writedatain_sel = 13; end
EastEmptyPort: begin ctrl_mux7to1_reg_file_c_writedatain_sel = 14; end
WestEmptyPort: begin ctrl_mux7to1_reg_file_c_writedatain_sel = 15; end
NorthFullPort: begin ctrl_mux7to1_reg_file_c_writedatain_sel = 16; end
SouthFullPort: begin ctrl_mux7to1_reg_file_c_writedatain_sel = 17; end
EastFullPort: begin ctrl_mux7to1_reg_file_c_writedatain_sel = 18; end
WestFullPort: begin ctrl_mux7to1_reg_file_c_writedatain_sel = 19; end
default: begin ctrl_mux7to1_reg_file_c_writedatain_sel = 2; end
endcase
ctrl_mux3to1_nop_d_sel = 2;
ctrl_mux2to1_addersub_opA_sel = 0;
ctrl_addersub_op = 3;
ctrl_data_mem_op = 0;
end
`endif
`ifdef ORI
OP_ORI:
begin
ctrl_mux3to1_nop_d_sel = 2;
ctrl_mux7to1_reg_file_c_writedatain_sel = 4;
ctrl_logic_unit_op = 1;
end
`endif
`ifdef REGIMM
OP_REGIMM:
casex (pipereg10_q[0])
`ifdef BGEZ
FUNC_BGEZ:
begin
ctrl_mux6to1_ifetch_load_sel = 1;
ctrl_mux3to1_ifetch_load_data_sel = 2;
ctrl_ifetch_op = 0;
end
`endif
`ifdef BLTZ
FUNC_BLTZ:
begin
ctrl_mux6to1_ifetch_load_sel = 2;
ctrl_mux3to1_ifetch_load_data_sel = 2;
ctrl_ifetch_op = 0;
end
`endif
endcase
`endif
`ifdef SB
OP_SB:
begin
ctrl_mux3to1_nop_d_sel = 2;
ctrl_mux2to1_addersub_opA_sel = 0;
ctrl_addersub_op = 3;
ctrl_data_mem_op = 11;
end
`endif
`ifdef SH
OP_SH:
begin
ctrl_mux3to1_nop_d_sel = 2;
ctrl_mux2to1_addersub_opA_sel = 0;
ctrl_addersub_op = 3;
ctrl_data_mem_op = 9;
end
`endif
`ifdef SLTI
OP_SLTI:
begin
ctrl_mux3to1_nop_d_sel = 2;
ctrl_mux2to1_addersub_opA_sel = 0;
ctrl_mux7to1_reg_file_c_writedatain_sel = 5;
ctrl_addersub_op = 6;
end
`endif
`ifdef SLTIU
OP_SLTIU:
begin
ctrl_mux3to1_nop_d_sel = 2;
ctrl_mux2to1_addersub_opA_sel = 0;
ctrl_mux7to1_reg_file_c_writedatain_sel = 5;
ctrl_addersub_op = 4;
end
`endif
OP_SPECIAL:
casex (pipereg9_q)
`ifdef ADD
FUNC_ADD:
begin
ctrl_mux3to1_nop_d_sel = 1;
ctrl_mux2to1_addersub_opA_sel = 0;
ctrl_mux7to1_reg_file_c_writedatain_sel = 6;
ctrl_addersub_op = 3;
end
`endif
`ifdef ADDU
FUNC_ADDU:
begin
ctrl_mux3to1_nop_d_sel = 1;
ctrl_mux2to1_addersub_opA_sel = 0;
ctrl_mux7to1_reg_file_c_writedatain_sel = 6;
ctrl_addersub_op = 1;
end
`endif
`ifdef AND
FUNC_AND:
begin
ctrl_mux3to1_nop_d_sel = 1;
ctrl_mux7to1_reg_file_c_writedatain_sel = 4;
ctrl_logic_unit_op = 0;
end
`endif
`ifdef JALR
FUNC_JALR:
begin
ctrl_mux2to1_addersub_opA_sel = 1;
ctrl_mux7to1_reg_file_c_writedatain_sel = 6;
ctrl_mux3to1_ifetch_load_data_sel = 0;
ctrl_addersub_op = 1;
ctrl_ifetch_op = 1;
end
`endif
`ifdef JR
FUNC_JR:
begin
ctrl_mux3to1_ifetch_load_data_sel = 0;
ctrl_ifetch_op = 1;
end
`endif
`ifdef MFHI
FUNC_MFHI:
ctrl_mux7to1_reg_file_c_writedatain_sel = 1;
`endif
`ifdef MFLO
FUNC_MFLO:
ctrl_mux7to1_reg_file_c_writedatain_sel = 0;
`endif
`ifdef MULT
FUNC_MULT:
ctrl_mul_op = 1;
`endif
`ifdef MULTU
FUNC_MULTU:
ctrl_mul_op = 0;
`endif
`ifdef NOR
FUNC_NOR:
begin
ctrl_mux3to1_nop_d_sel = 1;
ctrl_mux7to1_reg_file_c_writedatain_sel = 4;
ctrl_logic_unit_op = 3;
end
`endif
`ifdef OR
FUNC_OR:
begin
ctrl_mux3to1_nop_d_sel = 1;
ctrl_mux7to1_reg_file_c_writedatain_sel = 4;
ctrl_logic_unit_op = 1;
end
`endif
`ifdef SLL
FUNC_SLL:
begin
ctrl_mux3to1_nop_d_sel = 1;
ctrl_mux7to1_reg_file_c_writedatain_sel = 3;
ctrl_mux3to1_shifter_sa_sel = 0;
ctrl_shifter_op = 0;
end
`endif
`ifdef SLLV
FUNC_SLLV:
begin
ctrl_mux3to1_nop_d_sel = 1;
ctrl_mux7to1_reg_file_c_writedatain_sel = 3;
ctrl_mux3to1_shifter_sa_sel = 2;
ctrl_shifter_op = 0;
end
`endif
`ifdef SLT
FUNC_SLT:
begin
ctrl_mux3to1_nop_d_sel = 1;
ctrl_mux2to1_addersub_opA_sel = 0;
ctrl_mux7to1_reg_file_c_writedatain_sel = 5;
ctrl_addersub_op = 6;
end
`endif
`ifdef SLTU
FUNC_SLTU:
begin
ctrl_mux3to1_nop_d_sel = 1;
ctrl_mux2to1_addersub_opA_sel = 0;
ctrl_mux7to1_reg_file_c_writedatain_sel = 5;
ctrl_addersub_op = 4;
end
`endif
`ifdef SRA
FUNC_SRA:
begin
ctrl_mux3to1_nop_d_sel = 1;
ctrl_mux7to1_reg_file_c_writedatain_sel = 3;
ctrl_mux3to1_shifter_sa_sel = 0;
ctrl_shifter_op = 3;
end
`endif
`ifdef SRAV
FUNC_SRAV:
begin
ctrl_mux3to1_nop_d_sel = 1;
ctrl_mux7to1_reg_file_c_writedatain_sel = 3;
ctrl_mux3to1_shifter_sa_sel = 2;
ctrl_shifter_op = 3;
end
`endif
`ifdef SRL
FUNC_SRL:
begin
ctrl_mux3to1_nop_d_sel = 1;
ctrl_mux7to1_reg_file_c_writedatain_sel = 3;
ctrl_mux3to1_shifter_sa_sel = 0;
ctrl_shifter_op = 1;
end
`endif
`ifdef SRLV
FUNC_SRLV:
begin
ctrl_mux3to1_nop_d_sel = 1;
ctrl_mux7to1_reg_file_c_writedatain_sel = 3;
ctrl_mux3to1_shifter_sa_sel = 2;
ctrl_shifter_op = 1;
end
`endif
`ifdef SUB
FUNC_SUB:
begin
ctrl_mux3to1_nop_d_sel = 1;
ctrl_mux2to1_addersub_opA_sel = 0;
ctrl_mux7to1_reg_file_c_writedatain_sel = 6;
ctrl_addersub_op = 0;
end
`endif
`ifdef SUBU
FUNC_SUBU:
begin
ctrl_mux3to1_nop_d_sel = 1;
ctrl_mux2to1_addersub_opA_sel = 0;
ctrl_mux7to1_reg_file_c_writedatain_sel = 6;
ctrl_addersub_op = 2;
end
`endif
`ifdef XOR
FUNC_XOR:
begin
ctrl_mux3to1_nop_d_sel = 1;
ctrl_mux7to1_reg_file_c_writedatain_sel = 4;
ctrl_logic_unit_op = 2;
end
`endif
endcase
`ifdef SW
OP_SW:
begin
ctrl_mux3to1_nop_d_sel = 2;
ctrl_mux2to1_addersub_opA_sel = 0;
ctrl_addersub_op = 3;
ctrl_data_mem_op = 8;
end
`endif
`ifdef XORI
OP_XORI:
begin
ctrl_mux3to1_nop_d_sel = 2;
ctrl_mux7to1_reg_file_c_writedatain_sel = 4;
ctrl_logic_unit_op = 2;
end
`endif
endcase
end
//Logic for enable signals in Pipe Stage 2
always@(pipereg8_q or pipereg9_q or pipereg10_q[0] or 1'b0 or ctrl_shifter_stalled or ctrl_data_mem_stalled)
begin
ctrl_reg_file_c_we = 0;
ctrl_lo_reg_en = 0;
ctrl_branchresolve_en = 0;
ctrl_hi_reg_en = 0;
ctrl_ifetch_we = 0;
ctrl_data_mem_en = 0;
ctrl_shifter_start = 0;
casex (pipereg8_q)
`ifdef ADDI
OP_ADDI:
ctrl_reg_file_c_we = 1 &~ctrl_data_mem_stalled&~ctrl_shifter_stalled&~1'b0;
`endif
`ifdef ADDIU
OP_ADDIU:
ctrl_reg_file_c_we = 1 &~ctrl_data_mem_stalled&~ctrl_shifter_stalled&~1'b0;
`endif
`ifdef ANDI
OP_ANDI:
ctrl_reg_file_c_we = 1 &~ctrl_data_mem_stalled&~ctrl_shifter_stalled&~1'b0;
`endif
`ifdef BEQ
OP_BEQ:
begin
ctrl_branchresolve_en = 1 &~ctrl_data_mem_stalled&~ctrl_shifter_stalled&~1'b0;
ctrl_ifetch_we = 1 &~ctrl_data_mem_stalled&~ctrl_shifter_stalled&~1'b0;
end
`endif
`ifdef BGTZ
OP_BGTZ:
begin
ctrl_branchresolve_en = 1 &~ctrl_data_mem_stalled&~ctrl_shifter_stalled&~1'b0;
ctrl_ifetch_we = 1 &~ctrl_data_mem_stalled&~ctrl_shifter_stalled&~1'b0;
end
`endif
`ifdef BLEZ
OP_BLEZ:
begin
ctrl_branchresolve_en = 1 &~ctrl_data_mem_stalled&~ctrl_shifter_stalled&~1'b0;
ctrl_ifetch_we = 1 &~ctrl_data_mem_stalled&~ctrl_shifter_stalled&~1'b0;
end
`endif
`ifdef BNE
OP_BNE:
begin
ctrl_branchresolve_en = 1 &~ctrl_data_mem_stalled&~ctrl_shifter_stalled&~1'b0;
ctrl_ifetch_we = 1 &~ctrl_data_mem_stalled&~ctrl_shifter_stalled&~1'b0;
end
`endif
`ifdef J
OP_J:
ctrl_ifetch_we = 1 &~ctrl_data_mem_stalled&~ctrl_shifter_stalled&~1'b0;
`endif
`ifdef JAL
OP_JAL:
begin
ctrl_reg_file_c_we = 1 &~ctrl_data_mem_stalled&~ctrl_shifter_stalled&~1'b0;
ctrl_ifetch_we = 1 &~ctrl_data_mem_stalled&~ctrl_shifter_stalled&~1'b0;
end
`endif
`ifdef LB
OP_LB:
begin
ctrl_reg_file_c_we = 1 &~ctrl_data_mem_stalled&~ctrl_shifter_stalled&~1'b0;
ctrl_data_mem_en = 1 &~1'b0;
end
`endif
`ifdef LBU
OP_LBU:
begin
ctrl_reg_file_c_we = 1 &~ctrl_data_mem_stalled&~ctrl_shifter_stalled&~1'b0;
ctrl_data_mem_en = 1 &~1'b0;
end
`endif
`ifdef LH
OP_LH:
begin
ctrl_reg_file_c_we = 1 &~ctrl_data_mem_stalled&~ctrl_shifter_stalled&~1'b0;
ctrl_data_mem_en = 1 &~1'b0;
end
`endif
`ifdef LHU
OP_LHU:
begin
ctrl_reg_file_c_we = 1 &~ctrl_data_mem_stalled&~ctrl_shifter_stalled&~1'b0;
ctrl_data_mem_en = 1 &~1'b0;
end
`endif
`ifdef LUI
OP_LUI:
begin
ctrl_reg_file_c_we = 1 &~ctrl_data_mem_stalled&~ctrl_shifter_stalled&~1'b0;
ctrl_shifter_start = 1 &~1'b0;
end
`endif
`ifdef LW
OP_LW:
begin
ctrl_reg_file_c_we = 1 &~ctrl_data_mem_stalled&~ctrl_shifter_stalled&~1'b0;
ctrl_data_mem_en = 1 &~1'b0;
end
`endif
`ifdef ORI
OP_ORI:
ctrl_reg_file_c_we = 1 &~ctrl_data_mem_stalled&~ctrl_shifter_stalled&~1'b0;
`endif
OP_REGIMM:
casex (pipereg10_q[0])
`ifdef BGEZ
FUNC_BGEZ:
begin
ctrl_branchresolve_en = 1 &~ctrl_data_mem_stalled&~ctrl_shifter_stalled&~1'b0;
ctrl_ifetch_we = 1 &~ctrl_data_mem_stalled&~ctrl_shifter_stalled&~1'b0;
end
`endif
`ifdef BLTZ
FUNC_BLTZ:
begin
ctrl_branchresolve_en = 1 &~ctrl_data_mem_stalled&~ctrl_shifter_stalled&~1'b0;
ctrl_ifetch_we = 1 &~ctrl_data_mem_stalled&~ctrl_shifter_stalled&~1'b0;
end
`endif
endcase
`ifdef SB
OP_SB:
ctrl_data_mem_en = 1 &~1'b0;
`endif
`ifdef SH
OP_SH:
ctrl_data_mem_en = 1 &~1'b0;
`endif
`ifdef SLTI
OP_SLTI:
ctrl_reg_file_c_we = 1 &~ctrl_data_mem_stalled&~ctrl_shifter_stalled&~1'b0;
`endif
`ifdef SLTIU
OP_SLTIU:
ctrl_reg_file_c_we = 1 &~ctrl_data_mem_stalled&~ctrl_shifter_stalled&~1'b0;
`endif
OP_SPECIAL:
casex (pipereg9_q)
`ifdef ADD
FUNC_ADD:
ctrl_reg_file_c_we = 1 &~ctrl_data_mem_stalled&~ctrl_shifter_stalled&~1'b0;
`endif
`ifdef ADDU
FUNC_ADDU:
ctrl_reg_file_c_we = 1 &~ctrl_data_mem_stalled&~ctrl_shifter_stalled&~1'b0;
`endif
`ifdef AND
FUNC_AND:
ctrl_reg_file_c_we = 1 &~ctrl_data_mem_stalled&~ctrl_shifter_stalled&~1'b0;
`endif
`ifdef JALR
FUNC_JALR:
begin
ctrl_reg_file_c_we = 1 &~ctrl_data_mem_stalled&~ctrl_shifter_stalled&~1'b0;
ctrl_ifetch_we = 1 &~ctrl_data_mem_stalled&~ctrl_shifter_stalled&~1'b0;
end
`endif
`ifdef JR
FUNC_JR:
ctrl_ifetch_we = 1 &~ctrl_data_mem_stalled&~ctrl_shifter_stalled&~1'b0;
`endif
`ifdef MFHI
FUNC_MFHI:
ctrl_reg_file_c_we = 1 &~ctrl_data_mem_stalled&~ctrl_shifter_stalled&~1'b0;
`endif
`ifdef MFLO
FUNC_MFLO:
ctrl_reg_file_c_we = 1 &~ctrl_data_mem_stalled&~ctrl_shifter_stalled&~1'b0;
`endif
`ifdef MULT
FUNC_MULT:
begin
ctrl_lo_reg_en = 1 &~ctrl_data_mem_stalled&~ctrl_shifter_stalled&~1'b0;
ctrl_hi_reg_en = 1 &~ctrl_data_mem_stalled&~ctrl_shifter_stalled&~1'b0;
end
`endif
`ifdef MULTU
FUNC_MULTU:
begin
ctrl_lo_reg_en = 1 &~ctrl_data_mem_stalled&~ctrl_shifter_stalled&~1'b0;
ctrl_hi_reg_en = 1 &~ctrl_data_mem_stalled&~ctrl_shifter_stalled&~1'b0;
end
`endif
`ifdef NOR
FUNC_NOR:
ctrl_reg_file_c_we = 1 &~ctrl_data_mem_stalled&~ctrl_shifter_stalled&~1'b0;
`endif
`ifdef OR
FUNC_OR:
ctrl_reg_file_c_we = 1 &~ctrl_data_mem_stalled&~ctrl_shifter_stalled&~1'b0;
`endif
`ifdef SLL
FUNC_SLL:
begin
ctrl_reg_file_c_we = 1 &~ctrl_data_mem_stalled&~ctrl_shifter_stalled&~1'b0;
ctrl_shifter_start = 1 &~1'b0;
end
`endif
`ifdef SLLV
FUNC_SLLV:
begin
ctrl_reg_file_c_we = 1 &~ctrl_data_mem_stalled&~ctrl_shifter_stalled&~1'b0;
ctrl_shifter_start = 1 &~1'b0;
end
`endif
`ifdef SLT
FUNC_SLT:
ctrl_reg_file_c_we = 1 &~ctrl_data_mem_stalled&~ctrl_shifter_stalled&~1'b0;
`endif
`ifdef SLTU
FUNC_SLTU:
ctrl_reg_file_c_we = 1 &~ctrl_data_mem_stalled&~ctrl_shifter_stalled&~1'b0;
`endif
`ifdef SRA
FUNC_SRA:
begin
ctrl_reg_file_c_we = 1 &~ctrl_data_mem_stalled&~ctrl_shifter_stalled&~1'b0;
ctrl_shifter_start = 1 &~1'b0;
end
`endif
`ifdef SRAV
FUNC_SRAV:
begin
ctrl_reg_file_c_we = 1 &~ctrl_data_mem_stalled&~ctrl_shifter_stalled&~1'b0;
ctrl_shifter_start = 1 &~1'b0;
end
`endif
`ifdef SRL
FUNC_SRL:
begin
ctrl_reg_file_c_we = 1 &~ctrl_data_mem_stalled&~ctrl_shifter_stalled&~1'b0;
ctrl_shifter_start = 1 &~1'b0;
end
`endif
`ifdef SRLV
FUNC_SRLV:
begin
ctrl_reg_file_c_we = 1 &~ctrl_data_mem_stalled&~ctrl_shifter_stalled&~1'b0;
ctrl_shifter_start = 1 &~1'b0;
end
`endif
`ifdef SUB
FUNC_SUB:
ctrl_reg_file_c_we = 1 &~ctrl_data_mem_stalled&~ctrl_shifter_stalled&~1'b0;
`endif
`ifdef SUB
FUNC_SUBU:
ctrl_reg_file_c_we = 1 &~ctrl_data_mem_stalled&~ctrl_shifter_stalled&~1'b0;
`endif
`ifdef XOR
FUNC_XOR:
ctrl_reg_file_c_we = 1 &~ctrl_data_mem_stalled&~ctrl_shifter_stalled&~1'b0;
`endif
endcase
`ifdef SW
OP_SW:
ctrl_data_mem_en = 1 &~1'b0;
`endif
`ifdef XORI
OP_XORI:
ctrl_reg_file_c_we = 1 &~ctrl_data_mem_stalled&~ctrl_shifter_stalled&~1'b0;
`endif
endcase
end
/********* Stall Network & PipeReg Control ********/
assign stall_out_stage1 = stall_out_stage2|haz_zeroer0_q_pipereg5_q|haz_zeroer_q_pipereg5_q;
assign ctrl_pipereg10_en = ~stall_out_stage1;
assign ctrl_pipereg9_en = ~stall_out_stage1;
assign ctrl_pipereg8_en = ~stall_out_stage1;
assign ctrl_pipereg1_en = ~stall_out_stage1;
assign ctrl_pipereg3_en = ~stall_out_stage1;
assign ctrl_pipereg2_en = ~stall_out_stage1;
assign ctrl_pipereg5_en = ~stall_out_stage1;
assign ctrl_pipereg_en = ~stall_out_stage1;
assign stall_out_stage2 = 1'b0|ctrl_data_mem_stalled|ctrl_shifter_stalled;
assign branch_mispred = (((ctrl_ifetch_op==1) || (ctrl_ifetch_op==0 && mux6to1_ifetch_load_out)) & ctrl_ifetch_we);
assign stall_2nd_delayslot = &has_delayslot;
assign has_delayslot = 0;
assign squash_stage1 = ((stall_out_stage1&~stall_out_stage2))|~resetn;
assign ctrl_pipereg10_resetn = ~squash_stage1;
assign ctrl_pipereg9_resetn = ~squash_stage1;
assign ctrl_pipereg8_resetn = ~squash_stage1;
assign ctrl_pipereg1_resetn = ~squash_stage1;
assign ctrl_pipereg3_resetn = ~squash_stage1;
assign ctrl_pipereg2_resetn = ~squash_stage1;
assign ctrl_pipereg5_resetn = ~squash_stage1;
assign ctrl_pipereg_resetn = ~squash_stage1;
assign ctrl_pipereg_squashn = ~(0);
assign ctrl_pipereg5_squashn = ~(0);
assign ctrl_pipereg2_squashn = ~(0);
assign ctrl_pipereg3_squashn = ~(0);
assign ctrl_pipereg1_squashn = ~(0);
assign ctrl_pipereg8_squashn = ~(0);
assign ctrl_pipereg9_squashn = ~(0);
assign ctrl_pipereg10_squashn = ~(0);
assign ctrl_ifetch_squashn = ~(0);
assign squash_stage2 = ((stall_out_stage2&~1'b0))|~resetn;
/****************************** Datapath **************************/
/******************** Hazard Detection Logic ***********************/
assign haz_zeroer0_q_pipereg5_q = (zeroer0_q==pipereg5_q) && (|zeroer0_q);
assign haz_zeroer_q_pipereg5_q = (zeroer_q==pipereg5_q) && (|zeroer_q);
/*************** DATAPATH COMPONENTS **************/
addersub addersub (
.opB(nop_q),
.opA(mux2to1_addersub_opA_out),
.op(ctrl_addersub_op),
.result_slt(addersub_result_slt),
.result(addersub_result));
defparam
addersub.WIDTH=32;
logic_unit logic_unit (
.opB(nop_q),
.opA(reg_file_a_readdataout),
.op(ctrl_logic_unit_op),
.result(logic_unit_result));
defparam
logic_unit.WIDTH=32;
shifter shifter (
.clk(clk),
.resetn(resetn),
.dst(pipereg5_q),
.sa(mux3to1_shifter_sa_out),
.opB(nop_q),
.op(ctrl_shifter_op),
.start(ctrl_shifter_start),
.stalled(ctrl_shifter_stalled),
.result(shifter_result));
defparam
shifter.WIDTH=32;
mul mul (
.opB(reg_file_b_readdataout),
.opA(reg_file_a_readdataout),
.op(ctrl_mul_op),
.lo(mul_lo),
.hi(mul_hi));
defparam
mul.WIDTH=32;
ifetch ifetch (
.clk(clk),
.resetn(resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe),
.load(mux6to1_ifetch_load_out),
.load_data(mux3to1_ifetch_load_data_out),
.op(ctrl_ifetch_op),
.we(ctrl_ifetch_we),
.squashn(ctrl_ifetch_squashn),
.en(ctrl_ifetch_en),
.pc_out(ifetch_pc_out),
.instr(ifetch_instr),
.opcode(ifetch_opcode),
.func(ifetch_func),
.rs(ifetch_rs),
.rt(ifetch_rt),
.rd(ifetch_rd),
.instr_index(ifetch_instr_index),
.offset(ifetch_offset),
.sa(ifetch_sa),
.next_pc(ifetch_next_pc));
data_mem data_mem (
.clk(clk),
.resetn(resetn),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe),
.d_address(addersub_result),
.d_writedata(reg_file_b_readdataout),
.op(ctrl_data_mem_op),
.en(ctrl_data_mem_en),
.stalled(ctrl_data_mem_stalled),
.d_loadresult(data_mem_d_loadresult));
pcadder pcadder (
.offset(pipereg_q),
.pc(pipereg3_q),
.result(pcadder_result));
signext16 signext16 (
.in(ifetch_offset),
.out(signext16_out));
reg_file reg_file (
.clk(clk),
.resetn(resetn),
.c_writedatain(mux7to1_reg_file_c_writedatain_out),
.c_reg(pipereg5_q),
.b_reg(zeroer0_q),
.a_reg(zeroer_q),
.c_we(ctrl_reg_file_c_we),
.b_en(ctrl_reg_file_b_en),
.a_en(ctrl_reg_file_a_en),
.b_readdataout(reg_file_b_readdataout),
.a_readdataout(reg_file_a_readdataout));
merge26lo merge26lo (
.in2(pipereg1_q),
.in1(pipereg3_q),
.out(merge26lo_out));
branchresolve branchresolve (
.rt(reg_file_b_readdataout),
.rs(reg_file_a_readdataout),
.en(ctrl_branchresolve_en),
.eqz(branchresolve_eqz),
.gez(branchresolve_gez),
.gtz(branchresolve_gtz),
.lez(branchresolve_lez),
.ltz(branchresolve_ltz),
.ne(branchresolve_ne),
.eq(branchresolve_eq));
defparam
branchresolve.WIDTH=32;
hi_reg hi_reg (
.clk(clk),
.resetn(resetn),
.d(mul_hi),
.en(ctrl_hi_reg_en),
.q(hi_reg_q));
defparam
hi_reg.WIDTH=32;
lo_reg lo_reg (
.clk(clk),
.resetn(resetn),
.d(mul_lo),
.en(ctrl_lo_reg_en),
.q(lo_reg_q));
defparam
lo_reg.WIDTH=32;
constant const6 (
.out(const6_out));
defparam
const6.WIDTH=32,
const6.VAL=0;
constant const7 (
.out(const7_out));
defparam
const7.WIDTH=32,
const7.VAL=16;
constant constant (
.out(const_out));
defparam
constant.WIDTH=32,
constant.VAL=31;
pipereg pipereg (
.clk(clk),
.resetn(ctrl_pipereg_resetn),
.d(mux2to1_pipereg_d_out),
.squashn(ctrl_pipereg_squashn),
.en(ctrl_pipereg_en),
.q(pipereg_q));
defparam
pipereg.WIDTH=32;
pipereg pipereg1 (
.clk(clk),
.resetn(ctrl_pipereg1_resetn),
.d(ifetch_instr_index),
.squashn(ctrl_pipereg1_squashn),
.en(ctrl_pipereg1_en),
.q(pipereg1_q));
defparam
pipereg1.WIDTH=26;
pipereg pipereg2 (
.clk(clk),
.resetn(ctrl_pipereg2_resetn),
.d(ifetch_sa),
.squashn(ctrl_pipereg2_squashn),
.en(ctrl_pipereg2_en),
.q(pipereg2_q));
defparam
pipereg2.WIDTH=5;
pipereg pipereg5 (
.clk(clk),
.resetn(ctrl_pipereg5_resetn),
.d(zeroer4_q),
.squashn(ctrl_pipereg5_squashn),
.en(ctrl_pipereg5_en),
.q(pipereg5_q));
defparam
pipereg5.WIDTH=5;
pipereg pipereg3 (
.clk(clk),
.resetn(ctrl_pipereg3_resetn),
.d(ifetch_pc_out),
.squashn(ctrl_pipereg3_squashn),
.en(ctrl_pipereg3_en),
.q(pipereg3_q));
defparam
pipereg3.WIDTH=32;
fakedelay fakedelay (
.clk(clk),
.d(ifetch_pc_out),
.q(fakedelay_q));
defparam
fakedelay.WIDTH=32;
nop nop (
.d(mux3to1_nop_d_out),
.q(nop_q));
defparam
nop.WIDTH=32;
zeroer zeroer (
.d(ifetch_rs),
.en(ctrl_zeroer_en),
.q(zeroer_q));
defparam
zeroer.WIDTH=5;
zeroer zeroer0 (
.d(ifetch_rt),
.en(ctrl_zeroer0_en),
.q(zeroer0_q));
defparam
zeroer0.WIDTH=5;
zeroer zeroer4 (
.d(mux3to1_zeroer4_d_out),
.en(ctrl_zeroer4_en),
.q(zeroer4_q));
defparam
zeroer4.WIDTH=5;
// Multiplexor mux3to1_shifter_sa instantiation
assign mux3to1_shifter_sa_out =
(ctrl_mux3to1_shifter_sa_sel==2) ? reg_file_a_readdataout :
(ctrl_mux3to1_shifter_sa_sel==1) ? const7_out :
pipereg2_q;
// Multiplexor mux3to1_ifetch_load_data instantiation
assign mux3to1_ifetch_load_data_out =
(ctrl_mux3to1_ifetch_load_data_sel==2) ? pcadder_result :
(ctrl_mux3to1_ifetch_load_data_sel==1) ? merge26lo_out :
reg_file_a_readdataout;
// Multiplexor mux6to1_ifetch_load instantiation
assign mux6to1_ifetch_load_out =
(ctrl_mux6to1_ifetch_load_sel==5) ? branchresolve_eq :
(ctrl_mux6to1_ifetch_load_sel==4) ? branchresolve_ne :
(ctrl_mux6to1_ifetch_load_sel==3) ? branchresolve_lez :
(ctrl_mux6to1_ifetch_load_sel==2) ? branchresolve_ltz :
(ctrl_mux6to1_ifetch_load_sel==1) ? branchresolve_gez :
branchresolve_gtz;
// Multiplexor mux7to1_reg_file_c_writedatain instantiation
assign mux7to1_reg_file_c_writedatain_out =
(ctrl_mux7to1_reg_file_c_writedatain_sel==6) ? addersub_result :
(ctrl_mux7to1_reg_file_c_writedatain_sel==5) ? addersub_result_slt :
(ctrl_mux7to1_reg_file_c_writedatain_sel==4) ? logic_unit_result :
(ctrl_mux7to1_reg_file_c_writedatain_sel==3) ? shifter_result :
(ctrl_mux7to1_reg_file_c_writedatain_sel==2) ? data_mem_d_loadresult :
(ctrl_mux7to1_reg_file_c_writedatain_sel==8) ? tempFifoDataInNorth : //Deepak
(ctrl_mux7to1_reg_file_c_writedatain_sel==9) ? tempFifoDataInSouth : //Deepak
(ctrl_mux7to1_reg_file_c_writedatain_sel==10)? tempFifoDataInEast : //Deepak
(ctrl_mux7to1_reg_file_c_writedatain_sel==11)? tempFifoDataInWest : //Deepak
(ctrl_mux7to1_reg_file_c_writedatain_sel==12)? northEmpty : //Deepak
(ctrl_mux7to1_reg_file_c_writedatain_sel==13)? southEmpty : //Deepak
(ctrl_mux7to1_reg_file_c_writedatain_sel==14)? eastEmpty : //Deepak
(ctrl_mux7to1_reg_file_c_writedatain_sel==15)? westEmpty : //Deepak
(ctrl_mux7to1_reg_file_c_writedatain_sel==16)? northFull : //Deepak
(ctrl_mux7to1_reg_file_c_writedatain_sel==17)? southFull : //Deepak
(ctrl_mux7to1_reg_file_c_writedatain_sel==18)? eastFull : //Deepak
(ctrl_mux7to1_reg_file_c_writedatain_sel==19)? westFull : //Deepak
(ctrl_mux7to1_reg_file_c_writedatain_sel==1) ? hi_reg_q :
lo_reg_q;
// Multiplexor mux2to1_addersub_opA instantiation
assign mux2to1_addersub_opA_out =
(ctrl_mux2to1_addersub_opA_sel==1) ? fakedelay_q :
reg_file_a_readdataout;
// Multiplexor mux2to1_pipereg_d instantiation
assign mux2to1_pipereg_d_out =
(ctrl_mux2to1_pipereg_d_sel==1) ? ifetch_offset :
signext16_out;
// Multiplexor mux3to1_zeroer4_d instantiation
assign mux3to1_zeroer4_d_out =
(ctrl_mux3to1_zeroer4_d_sel==2) ? ifetch_rt :
(ctrl_mux3to1_zeroer4_d_sel==1) ? ifetch_rd :
const_out;
// Multiplexor mux3to1_nop_d instantiation
assign mux3to1_nop_d_out =
(ctrl_mux3to1_nop_d_sel==2) ? pipereg_q :
(ctrl_mux3to1_nop_d_sel==1) ? reg_file_b_readdataout :
const6_out;
pipereg pipereg8 (
.clk(clk),
.resetn(ctrl_pipereg8_resetn),
.d(ifetch_opcode),
.squashn(ctrl_pipereg8_squashn),
.en(ctrl_pipereg8_en),
.q(pipereg8_q));
defparam
pipereg8.WIDTH=6;
pipereg pipereg9 (
.clk(clk),
.resetn(ctrl_pipereg9_resetn),
.d(ifetch_func),
.squashn(ctrl_pipereg9_squashn),
.en(ctrl_pipereg9_en),
.q(pipereg9_q));
defparam
pipereg9.WIDTH=6;
pipereg pipereg10 (
.clk(clk),
.resetn(ctrl_pipereg10_resetn),
.d(ifetch_rt),
.squashn(ctrl_pipereg10_squashn),
.en(ctrl_pipereg10_en),
.q(pipereg10_q));
defparam
pipereg10.WIDTH=5;
endmodule
|
`timescale 1ns / 1ns
module system50(clk,resetn,boot_iaddr,boot_idata,boot_daddr,boot_ddata,reg_file_b_readdataout,processor_select);
input clk;
input resetn;
input [6:0] processor_select;
output [31:0] reg_file_b_readdataout;
input [13:0] boot_iaddr;
input [31:0] boot_idata;
input [13:0] boot_daddr;
input [31:0] boot_ddata;
reg boot_iwe0;
reg boot_dwe0;
reg boot_iwe1;
reg boot_dwe1;
reg boot_iwe2;
reg boot_dwe2;
reg boot_iwe3;
reg boot_dwe3;
reg boot_iwe4;
reg boot_dwe4;
reg boot_iwe5;
reg boot_dwe5;
reg boot_iwe6;
reg boot_dwe6;
reg boot_iwe7;
reg boot_dwe7;
reg boot_iwe8;
reg boot_dwe8;
reg boot_iwe9;
reg boot_dwe9;
reg boot_iwe10;
reg boot_dwe10;
reg boot_iwe11;
reg boot_dwe11;
reg boot_iwe12;
reg boot_dwe12;
reg boot_iwe13;
reg boot_dwe13;
reg boot_iwe14;
reg boot_dwe14;
reg boot_iwe15;
reg boot_dwe15;
reg boot_iwe16;
reg boot_dwe16;
reg boot_iwe17;
reg boot_dwe17;
reg boot_iwe18;
reg boot_dwe18;
reg boot_iwe19;
reg boot_dwe19;
reg boot_iwe20;
reg boot_dwe20;
reg boot_iwe21;
reg boot_dwe21;
reg boot_iwe22;
reg boot_dwe22;
reg boot_iwe23;
reg boot_dwe23;
reg boot_iwe24;
reg boot_dwe24;
reg boot_iwe25;
reg boot_dwe25;
reg boot_iwe26;
reg boot_dwe26;
reg boot_iwe27;
reg boot_dwe27;
reg boot_iwe28;
reg boot_dwe28;
reg boot_iwe29;
reg boot_dwe29;
reg boot_iwe30;
reg boot_dwe30;
reg boot_iwe31;
reg boot_dwe31;
reg boot_iwe32;
reg boot_dwe32;
reg boot_iwe33;
reg boot_dwe33;
reg boot_iwe34;
reg boot_dwe34;
reg boot_iwe35;
reg boot_dwe35;
reg boot_iwe36;
reg boot_dwe36;
reg boot_iwe37;
reg boot_dwe37;
reg boot_iwe38;
reg boot_dwe38;
reg boot_iwe39;
reg boot_dwe39;
reg boot_iwe40;
reg boot_dwe40;
reg boot_iwe41;
reg boot_dwe41;
reg boot_iwe42;
reg boot_dwe42;
reg boot_iwe43;
reg boot_dwe43;
reg boot_iwe44;
reg boot_dwe44;
reg boot_iwe45;
reg boot_dwe45;
reg boot_iwe46;
reg boot_dwe46;
reg boot_iwe47;
reg boot_dwe47;
reg boot_iwe48;
reg boot_dwe48;
reg boot_iwe49;
reg boot_dwe49;
//Processor 0 control and data signals
wire wrProc0South;
wire fullProc0South;
wire [31:0] dataOutProc0South;
//Processor 0 control and data signals
wire rdProc0East;
wire emptyProc0East;
wire [31:0] dataInProc0East;
//Processor 0 control and data signals
wire wrProc0East;
wire fullProc0East;
wire [31:0] dataOutProc0East;
//Processor 1 control and data signals
wire rdProc1West;
wire emptyProc1West;
wire [31:0] dataInProc1West;
//Processor 1 control and data signals
wire wrProc1West;
wire fullProc1West;
wire [31:0] dataOutProc1West;
//Processor 2 control and data signals
wire rdProc2East;
wire emptyProc2East;
wire [31:0] dataInProc2East;
//Processor 3 control and data signals
wire rdProc3East;
wire emptyProc3East;
wire [31:0] dataInProc3East;
//Processor 3 control and data signals
wire wrProc3West;
wire fullProc3West;
wire [31:0] dataOutProc3West;
//Processor 4 control and data signals
wire rdProc4East;
wire emptyProc4East;
wire [31:0] dataInProc4East;
//Processor 4 control and data signals
wire wrProc4West;
wire fullProc4West;
wire [31:0] dataOutProc4West;
//Processor 5 control and data signals
wire rdProc5East;
wire emptyProc5East;
wire [31:0] dataInProc5East;
//Processor 5 control and data signals
wire wrProc5West;
wire fullProc5West;
wire [31:0] dataOutProc5West;
//Processor 6 control and data signals
wire rdProc6South;
wire emptyProc6South;
wire [31:0] dataInProc6South;
//Processor 6 control and data signals
wire wrProc6South;
wire fullProc6South;
wire [31:0] dataOutProc6South;
//Processor 6 control and data signals
wire rdProc6East;
wire emptyProc6East;
wire [31:0] dataInProc6East;
//Processor 6 control and data signals
wire wrProc6West;
wire fullProc6West;
wire [31:0] dataOutProc6West;
//Processor 7 control and data signals
wire wrProc7South;
wire fullProc7South;
wire [31:0] dataOutProc7South;
//Processor 7 control and data signals
wire rdProc7East;
wire emptyProc7East;
wire [31:0] dataInProc7East;
//Processor 7 control and data signals
wire wrProc7West;
wire fullProc7West;
wire [31:0] dataOutProc7West;
//Processor 8 control and data signals
wire rdProc8South;
wire emptyProc8South;
wire [31:0] dataInProc8South;
//Processor 8 control and data signals
wire rdProc8East;
wire emptyProc8East;
wire [31:0] dataInProc8East;
//Processor 8 control and data signals
wire wrProc8West;
wire fullProc8West;
wire [31:0] dataOutProc8West;
//Processor 9 control and data signals
wire rdProc9South;
wire emptyProc9South;
wire [31:0] dataInProc9South;
//Processor 9 control and data signals
wire wrProc9West;
wire fullProc9West;
wire [31:0] dataOutProc9West;
//Processor 10 control and data signals
wire rdProc10North;
wire emptyProc10North;
wire [31:0] dataInProc10North;
//Processor 10 control and data signals
wire wrProc10South;
wire fullProc10South;
wire [31:0] dataOutProc10South;
//Processor 11 control and data signals
wire rdProc11South;
wire emptyProc11South;
wire [31:0] dataInProc11South;
//Processor 11 control and data signals
wire wrProc11East;
wire fullProc11East;
wire [31:0] dataOutProc11East;
//Processor 12 control and data signals
wire rdProc12South;
wire emptyProc12South;
wire [31:0] dataInProc12South;
//Processor 12 control and data signals
wire wrProc12South;
wire fullProc12South;
wire [31:0] dataOutProc12South;
//Processor 12 control and data signals
wire wrProc12East;
wire fullProc12East;
wire [31:0] dataOutProc12East;
//Processor 12 control and data signals
wire rdProc12West;
wire emptyProc12West;
wire [31:0] dataInProc12West;
//Processor 13 control and data signals
wire wrProc13East;
wire fullProc13East;
wire [31:0] dataOutProc13East;
//Processor 13 control and data signals
wire rdProc13West;
wire emptyProc13West;
wire [31:0] dataInProc13West;
//Processor 14 control and data signals
wire rdProc14South;
wire emptyProc14South;
wire [31:0] dataInProc14South;
//Processor 14 control and data signals
wire wrProc14South;
wire fullProc14South;
wire [31:0] dataOutProc14South;
//Processor 14 control and data signals
wire rdProc14East;
wire emptyProc14East;
wire [31:0] dataInProc14East;
//Processor 14 control and data signals
wire wrProc14East;
wire fullProc14East;
wire [31:0] dataOutProc14East;
//Processor 14 control and data signals
wire rdProc14West;
wire emptyProc14West;
wire [31:0] dataInProc14West;
//Processor 15 control and data signals
wire wrProc15South;
wire fullProc15South;
wire [31:0] dataOutProc15South;
//Processor 15 control and data signals
wire rdProc15East;
wire emptyProc15East;
wire [31:0] dataInProc15East;
//Processor 15 control and data signals
wire wrProc15East;
wire fullProc15East;
wire [31:0] dataOutProc15East;
//Processor 15 control and data signals
wire rdProc15West;
wire emptyProc15West;
wire [31:0] dataInProc15West;
//Processor 15 control and data signals
wire wrProc15West;
wire fullProc15West;
wire [31:0] dataOutProc15West;
//Processor 16 control and data signals
wire rdProc16North;
wire emptyProc16North;
wire [31:0] dataInProc16North;
//Processor 16 control and data signals
wire wrProc16North;
wire fullProc16North;
wire [31:0] dataOutProc16North;
//Processor 16 control and data signals
wire rdProc16South;
wire emptyProc16South;
wire [31:0] dataInProc16South;
//Processor 16 control and data signals
wire wrProc16South;
wire fullProc16South;
wire [31:0] dataOutProc16South;
//Processor 16 control and data signals
wire rdProc16East;
wire emptyProc16East;
wire [31:0] dataInProc16East;
//Processor 16 control and data signals
wire rdProc16West;
wire emptyProc16West;
wire [31:0] dataInProc16West;
//Processor 16 control and data signals
wire wrProc16West;
wire fullProc16West;
wire [31:0] dataOutProc16West;
//Processor 17 control and data signals
wire rdProc17North;
wire emptyProc17North;
wire [31:0] dataInProc17North;
//Processor 17 control and data signals
wire wrProc17West;
wire fullProc17West;
wire [31:0] dataOutProc17West;
//Processor 18 control and data signals
wire wrProc18North;
wire fullProc18North;
wire [31:0] dataOutProc18North;
//Processor 18 control and data signals
wire rdProc18South;
wire emptyProc18South;
wire [31:0] dataInProc18South;
//Processor 18 control and data signals
wire rdProc18East;
wire emptyProc18East;
wire [31:0] dataInProc18East;
//Processor 18 control and data signals
wire wrProc18East;
wire fullProc18East;
wire [31:0] dataOutProc18East;
//Processor 19 control and data signals
wire wrProc19North;
wire fullProc19North;
wire [31:0] dataOutProc19North;
//Processor 19 control and data signals
wire rdProc19South;
wire emptyProc19South;
wire [31:0] dataInProc19South;
//Processor 19 control and data signals
wire rdProc19West;
wire emptyProc19West;
wire [31:0] dataInProc19West;
//Processor 19 control and data signals
wire wrProc19West;
wire fullProc19West;
wire [31:0] dataOutProc19West;
//Processor 20 control and data signals
wire rdProc20North;
wire emptyProc20North;
wire [31:0] dataInProc20North;
//Processor 20 control and data signals
wire wrProc20South;
wire fullProc20South;
wire [31:0] dataOutProc20South;
//Processor 21 control and data signals
wire wrProc21North;
wire fullProc21North;
wire [31:0] dataOutProc21North;
//Processor 21 control and data signals
wire rdProc21South;
wire emptyProc21South;
wire [31:0] dataInProc21South;
//Processor 21 control and data signals
wire wrProc21East;
wire fullProc21East;
wire [31:0] dataOutProc21East;
//Processor 22 control and data signals
wire rdProc22North;
wire emptyProc22North;
wire [31:0] dataInProc22North;
//Processor 22 control and data signals
wire wrProc22North;
wire fullProc22North;
wire [31:0] dataOutProc22North;
//Processor 22 control and data signals
wire rdProc22South;
wire emptyProc22South;
wire [31:0] dataInProc22South;
//Processor 22 control and data signals
wire wrProc22East;
wire fullProc22East;
wire [31:0] dataOutProc22East;
//Processor 22 control and data signals
wire rdProc22West;
wire emptyProc22West;
wire [31:0] dataInProc22West;
//Processor 23 control and data signals
wire rdProc23South;
wire emptyProc23South;
wire [31:0] dataInProc23South;
//Processor 23 control and data signals
wire wrProc23East;
wire fullProc23East;
wire [31:0] dataOutProc23East;
//Processor 23 control and data signals
wire rdProc23West;
wire emptyProc23West;
wire [31:0] dataInProc23West;
//Processor 24 control and data signals
wire rdProc24North;
wire emptyProc24North;
wire [31:0] dataInProc24North;
//Processor 24 control and data signals
wire wrProc24North;
wire fullProc24North;
wire [31:0] dataOutProc24North;
//Processor 24 control and data signals
wire wrProc24South;
wire fullProc24South;
wire [31:0] dataOutProc24South;
//Processor 24 control and data signals
wire wrProc24East;
wire fullProc24East;
wire [31:0] dataOutProc24East;
//Processor 24 control and data signals
wire rdProc24West;
wire emptyProc24West;
wire [31:0] dataInProc24West;
//Processor 25 control and data signals
wire rdProc25North;
wire emptyProc25North;
wire [31:0] dataInProc25North;
//Processor 25 control and data signals
wire wrProc25South;
wire fullProc25South;
wire [31:0] dataOutProc25South;
//Processor 25 control and data signals
wire wrProc25East;
wire fullProc25East;
wire [31:0] dataOutProc25East;
//Processor 25 control and data signals
wire rdProc25West;
wire emptyProc25West;
wire [31:0] dataInProc25West;
//Processor 26 control and data signals
wire rdProc26North;
wire emptyProc26North;
wire [31:0] dataInProc26North;
//Processor 26 control and data signals
wire wrProc26North;
wire fullProc26North;
wire [31:0] dataOutProc26North;
//Processor 26 control and data signals
wire rdProc26South;
wire emptyProc26South;
wire [31:0] dataInProc26South;
//Processor 26 control and data signals
wire wrProc26South;
wire fullProc26South;
wire [31:0] dataOutProc26South;
//Processor 26 control and data signals
wire rdProc26East;
wire emptyProc26East;
wire [31:0] dataInProc26East;
//Processor 26 control and data signals
wire wrProc26East;
wire fullProc26East;
wire [31:0] dataOutProc26East;
//Processor 26 control and data signals
wire rdProc26West;
wire emptyProc26West;
wire [31:0] dataInProc26West;
//Processor 27 control and data signals
wire rdProc27South;
wire Proc27South;
wire [31:0] dataInProc27South;
//Processor 27 control and data signals
wire wrProc27East;
wire fullProc27East;
wire [31:0] dataOutProc27East;
//Processor 27 control and data signals
wire rdProc27West;
wire emptyProc27West;
wire [31:0] dataInProc27West;
//Processor 27 control and data signals
wire wrProc27West;
wire fullProc27West;
wire [31:0] dataOutProc27West;
//Processor 28 control and data signals
wire wrProc28North;
wire fullProc28North;
wire [31:0] dataOutProc28North;
//Processor 28 control and data signals
wire wrProc28East;
wire fullProc28East;
wire [31:0] dataOutProc28East;
//Processor 28 control and data signals
wire rdProc28West;
wire emptyProc28West;
wire [31:0] dataInProc28West;
//Processor 29 control and data signals
wire wrProc29North;
wire fullProc29North;
wire [31:0] dataOutProc29North;
//Processor 29 control and data signals
wire rdProc29West;
wire emptyProc29West;
wire [31:0] dataInProc29West;
//Processor 30 control and data signals
wire rdProc30North;
wire emptyProc30North;
wire [31:0] dataInProc30North;
//Processor 30 control and data signals
wire wrProc30South;
wire fullProc30South;
wire [31:0] dataOutProc30South;
//Processor 30 control and data signals
wire wrProc30East;
wire fullProc30East;
wire [31:0] dataOutProc30East;
//Processor 31 control and data signals
wire wrProc31North;
wire fullProc31North;
wire [31:0] dataOutProc31North;
//Processor 31 control and data signals
wire rdProc31South;
wire emptyProc31South;
wire [31:0] dataInProc31South;
//Processor 31 control and data signals
wire wrProc31South;
wire fullProc31South;
wire [31:0] dataOutProc31South;
//Processor 31 control and data signals
wire rdProc31East;
wire emptyProc31East;
wire [31:0] dataInProc31East;
//Processor 31 control and data signals
wire rdProc31West;
wire emptyProc31West;
wire [31:0] dataInProc31West;
//Processor 32 control and data signals
wire wrProc32North;
wire fullProc32North;
wire [31:0] dataOutProc32North;
//Processor 32 control and data signals
wire rdProc32South;
wire emptyProc32South;
wire [31:0] dataInProc32South;
//Processor 32 control and data signals
wire wrProc32East;
wire fullProc32East;
wire [31:0] dataOutProc32East;
//Processor 32 control and data signals
wire wrProc32West;
wire fullProc32West;
wire [31:0] dataOutProc32West;
//Processor 33 control and data signals
wire wrProc33North;
wire fullProc33North;
wire [31:0] dataOutProc33North;
//Processor 33 control and data signals
wire rdProc33West;
wire emptyProc33West;
wire [31:0] dataInProc33West;
//Processor 34 control and data signals
wire rdProc34North;
wire emptyProc34North;
wire [31:0] dataInProc34North;
//Processor 34 control and data signals
wire wrProc34South;
wire fullProc34South;
wire [31:0] dataOutProc34South;
//Processor 35 control and data signals
wire rdProc35North;
wire emptyProc35North;
wire [31:0] dataInProc35North;
//Processor 35 control and data signals
wire wrProc35South;
wire fullProc35South;
wire [31:0] dataOutProc35South;
//Processor 35 control and data signals
wire wrProc35East;
wire fullProc35East;
wire [31:0] dataOutProc35East;
//Processor 36 control and data signals
wire rdProc36North;
wire emptyProc36North;
wire [31:0] dataInProc36North;
//Processor 36 control and data signals
wire wrProc36North;
wire fullProc36North;
wire [31:0] dataOutProc36North;
//Processor 36 control and data signals
wire wrProc36South;
wire fullProc36South;
wire [31:0] dataOutProc36South;
//Processor 36 control and data signals
wire rdProc36East;
wire emptyProc36East;
wire [31:0] dataInProc36East;
//Processor 36 control and data signals
wire wrProc36East;
wire fullProc36East;
wire [31:0] dataOutProc36East;
//Processor 36 control and data signals
wire rdProc36West;
wire emptyProc36West;
wire [31:0] dataInProc36West;
//Processor 37 control and data signals
wire wrProc37North;
wire fullProc37North;
wire [31:0] dataOutProc37North;
//Processor 37 control and data signals
wire wrProc37South;
wire fullProc37South;
wire [31:0] dataOutProc37South;
//Processor 37 control and data signals
wire rdProc37East;
wire emptyProc37East;
wire [31:0] dataInProc37East;
//Processor 37 control and data signals
wire rdProc37West;
wire emptyProc37West;
wire [31:0] dataInProc37West;
//Processor 37 control and data signals
wire wrProc37West;
wire fullProc37West;
wire [31:0] dataOutProc37West;
//Processor 38 control and data signals
wire rdProc38South;
wire emptyProc38South;
wire [31:0] dataInProc38South;
//Processor 38 control and data signals
wire rdProc38East;
wire emptyProc38East;
wire [31:0] dataInProc38East;
//Processor 38 control and data signals
wire wrProc38East;
wire fullProc38East;
wire [31:0] dataOutProc38East;
//Processor 38 control and data signals
wire wrProc38West;
wire fullProc38West;
wire [31:0] dataOutProc38West;
//Processor 39 control and data signals
wire rdProc39West;
wire emptyProc39West;
wire [31:0] dataInProc39West;
//Processor 39 control and data signals
wire wrProc39West;
wire fullProc39West;
wire [31:0] dataOutProc39West;
//Processor 40 control and data signals
wire rdProc40North;
wire emptyProc40North;
wire [31:0] dataInProc40North;
//Processor 40 control and data signals
wire wrProc40East;
wire fullProc40East;
wire [31:0] dataOutProc40East;
//Processor 41 control and data signals
wire rdProc41North;
wire emptyProc41North;
wire [31:0] dataInProc41North;
//Processor 41 control and data signals
wire wrProc41North;
wire fullProc41North;
wire [31:0] dataOutProc41North;
//Processor 41 control and data signals
wire wrProc41East;
wire fullProc41East;
wire [31:0] dataOutProc41East;
//Processor 41 control and data signals
wire rdProc41West;
wire emptyProc41West;
wire [31:0] dataInProc41West;
//Processor 42 control and data signals
wire wrProc42North;
wire fullProc42North;
wire [31:0] dataOutProc42North;
//Processor 42 control and data signals
wire rdProc42East;
wire emptyProc42East;
wire [31:0] dataInProc42East;
//Processor 42 control and data signals
wire rdProc42West;
wire emptyProc42West;
wire [31:0] dataInProc42West;
//Processor 43 control and data signals
wire rdProc43East;
wire emptyProc43East;
wire [31:0] dataInProc43East;
//Processor 43 control and data signals
wire wrProc43West;
wire fullProc43West;
wire [31:0] dataOutProc43West;
//Processor 44 control and data signals
wire rdProc44North;
wire emptyProc44North;
wire [31:0] dataInProc44North;
//Processor 44 control and data signals
wire rdProc44East;
wire emptyProc44East;
wire [31:0] dataInProc44East;
//Processor 44 control and data signals
wire wrProc44West;
wire fullProc44West;
wire [31:0] dataOutProc44West;
//Processor 45 control and data signals
wire rdProc45North;
wire emptyProc45North;
wire [31:0] dataInProc45North;
//Processor 45 control and data signals
wire wrProc45West;
wire fullProc45West;
wire [31:0] dataOutProc45West;
//Processor 46 control and data signals
wire rdProc46North;
wire emptyProc46North;
wire [31:0] dataInProc46North;
//Processor 46 control and data signals
wire wrProc46East;
wire fullProc46East;
wire [31:0] dataOutProc46East;
//Processor 47 control and data signals
wire rdProc47North;
wire emptyProc47North;
wire [31:0] dataInProc47North;
//Processor 47 control and data signals
wire wrProc47East;
wire fullProc47East;
wire [31:0] dataOutProc47East;
//Processor 47 control and data signals
wire rdProc47West;
wire emptyProc47West;
wire [31:0] dataInProc47West;
//Processor 48 control and data signals
wire wrProc48North;
wire fullProc48North;
wire [31:0] dataOutProc48North;
//Processor 48 control and data signals
wire rdProc48East;
wire emptyProc48East;
wire [31:0] dataInProc48East;
//Processor 48 control and data signals
wire wrProc48East;
wire fullProc48East;
wire [31:0] dataOutProc48East;
//Processor 48 control and data signals
wire rdProc48West;
wire emptyProc48West;
wire [31:0] dataInProc48West;
//Processor 49 control and data signals
wire rdProc49West;
wire emptyProc49West;
wire [31:0] dataInProc49West;
//Processor 49 control and data signals
wire wrProc49West;
wire fullProc49West;
wire [31:0] dataOutProc49West;
//PROCESSOR 0
system proc0(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe0),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe0),
.wrSouth(wrProc0South),
.fullSouth(fullProc0South),
.dataOutSouth(dataOutProc0South),
.rdEast(rdProc0East),
.emptyEast(emptyProc0East),
.dataInEast(dataInProc0East),
.wrEast(wrProc0East),
.fullEast(fullProc0East),
.dataOutEast(dataOutProc0East));
//PROCESSOR 1
system proc1(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe1),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe1),
.rdWest(rdProc1West),
.emptyWest(emptyProc1West),
.dataInWest(dataInProc1West),
.wrWest(wrProc1West),
.fullWest(fullProc1West),
.dataOutWest(dataOutProc1West));
//PROCESSOR 2
system proc2(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe2),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe2),
.rdEast(rdProc2East),
.emptyEast(emptyProc2East),
.dataInEast(dataInProc2East),
.reg_file_b_readdataout(reg_file_b_readdataout));
//PROCESSOR 3
system proc3(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe3),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe3),
.rdEast(rdProc3East),
.emptyEast(emptyProc3East),
.dataInEast(dataInProc3East),
.wrWest(wrProc3West),
.fullWest(fullProc3West),
.dataOutWest(dataOutProc3West));
//PROCESSOR 4
system proc4(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe4),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe4),
.rdEast(rdProc4East),
.emptyEast(emptyProc4East),
.dataInEast(dataInProc4East),
.wrWest(wrProc4West),
.fullWest(fullProc4West),
.dataOutWest(dataOutProc4West));
//PROCESSOR 5
system proc5(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe5),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe5),
.rdEast(rdProc5East),
.emptyEast(emptyProc5East),
.dataInEast(dataInProc5East),
.wrWest(wrProc5West),
.fullWest(fullProc5West),
.dataOutWest(dataOutProc5West));
//PROCESSOR 6
system proc6(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe6),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe6),
.rdSouth(rdProc6South),
.emptySouth(emptyProc6South),
.dataInSouth(dataInProc6South),
.wrSouth(wrProc6South),
.fullSouth(fullProc6South),
.dataOutSouth(dataOutProc6South),
.rdEast(rdProc6East),
.emptyEast(emptyProc6East),
.dataInEast(dataInProc6East),
.wrWest(wrProc6West),
.fullWest(fullProc6West),
.dataOutWest(dataOutProc6West));
//PROCESSOR 7
system proc7(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe7),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe7),
.wrSouth(wrProc7South),
.fullSouth(fullProc7South),
.dataOutSouth(dataOutProc7South),
.rdEast(rdProc7East),
.emptyEast(emptyProc7East),
.dataInEast(dataInProc7East),
.wrWest(wrProc7West),
.fullWest(fullProc7West),
.dataOutWest(dataOutProc7West));
//PROCESSOR 8
system proc8(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe8),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe8),
.rdSouth(rdProc8South),
.emptySouth(emptyProc8South),
.dataInSouth(dataInProc8South),
.rdEast(rdProc8East),
.emptyEast(emptyProc8East),
.dataInEast(dataInProc8East),
.wrWest(wrProc8West),
.fullWest(fullProc8West),
.dataOutWest(dataOutProc8West));
//PROCESSOR 9
system proc9(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe9),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe9),
.rdSouth(rdProc9South),
.emptySouth(emptyProc9South),
.dataInSouth(dataInProc9South),
.wrWest(wrProc9West),
.fullWest(fullProc9West),
.dataOutWest(dataOutProc9West));
//PROCESSOR 10
system proc10(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe10),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe10),
.rdNorth(rdProc10North),
.emptyNorth(emptyProc10North),
.dataInNorth(dataInProc10North),
.wrSouth(wrProc10South),
.fullSouth(fullProc10South),
.dataOutSouth(dataOutProc10South));
//PROCESSOR 11
system proc11(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe11),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe11),
.rdSouth(rdProc11South),
.emptySouth(emptyProc11South),
.dataInSouth(dataInProc11South),
.wrEast(wrProc11East),
.fullEast(fullProc11East),
.dataOutEast(dataOutProc11East));
//PROCESSOR 12
system proc12(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe12),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe12),
.rdSouth(rdProc12South),
.emptySouth(emptyProc12South),
.dataInSouth(dataInProc12South),
.wrSouth(wrProc12South),
.fullSouth(fullProc12South),
.dataOutSouth(dataOutProc12South),
.wrEast(wrProc12East),
.fullEast(fullProc12East),
.dataOutEast(dataOutProc12East),
.rdWest(rdProc12West),
.emptyWest(emptyProc12West),
.dataInWest(dataInProc12West));
//PROCESSOR 13
system proc13(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe13),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe13),
.wrEast(wrProc13East),
.fullEast(fullProc13East),
.dataOutEast(dataOutProc13East),
.rdWest(rdProc13West),
.emptyWest(emptyProc13West),
.dataInWest(dataInProc13West));
//PROCESSOR 14
system proc14(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe14),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe14),
.rdSouth(rdProc14South),
.emptySouth(emptyProc14South),
.dataInSouth(dataInProc14South),
.wrSouth(wrProc14South),
.fullSouth(fullProc14South),
.dataOutSouth(dataOutProc14South),
.rdEast(rdProc14East),
.emptyEast(emptyProc14East),
.dataInEast(dataInProc14East),
.wrEast(wrProc14East),
.fullEast(fullProc14East),
.dataOutEast(dataOutProc14East),
.rdWest(rdProc14West),
.emptyWest(emptyProc14West),
.dataInWest(dataInProc14West));
//PROCESSOR 15
system proc15(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe15),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe15),
.wrSouth(wrProc15South),
.fullSouth(fullProc15South),
.dataOutSouth(dataOutProc15South),
.rdEast(rdProc15East),
.emptyEast(emptyProc15East),
.dataInEast(dataInProc15East),
.wrEast(wrProc15East),
.fullEast(fullProc15East),
.dataOutEast(dataOutProc15East),
.rdWest(rdProc15West),
.emptyWest(emptyProc15West),
.dataInWest(dataInProc15West),
.wrWest(wrProc15West),
.fullWest(fullProc15West),
.dataOutWest(dataOutProc15West));
//PROCESSOR 16
system proc16(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe16),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe16),
.rdNorth(rdProc16North),
.emptyNorth(emptyProc16North),
.dataInNorth(dataInProc16North),
.wrNorth(wrProc16North),
.fullNorth(fullProc16North),
.dataOutNorth(dataOutProc16North),
.rdSouth(rdProc16South),
.emptySouth(emptyProc16South),
.dataInSouth(dataInProc16South),
.wrSouth(wrProc16South),
.fullSouth(fullProc16South),
.dataOutSouth(dataOutProc16South),
.rdEast(rdProc16East),
.emptyEast(emptyProc16East),
.dataInEast(dataInProc16East),
.rdWest(rdProc16West),
.emptyWest(emptyProc16West),
.dataInWest(dataInProc16West),
.wrWest(wrProc16West),
.fullWest(fullProc16West),
.dataOutWest(dataOutProc16West));
//PROCESSOR 17
system proc17(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe17),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe17),
.rdNorth(rdProc17North),
.emptyNorth(emptyProc17North),
.dataInNorth(dataInProc17North),
.wrWest(wrProc17West),
.fullWest(fullProc17West),
.dataOutWest(dataOutProc17West));
//PROCESSOR 18
system proc18(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe18),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe18),
.wrNorth(wrProc18North),
.fullNorth(fullProc18North),
.dataOutNorth(dataOutProc18North),
.rdSouth(rdProc18South),
.emptySouth(emptyProc18South),
.dataInSouth(dataInProc18South),
.rdEast(rdProc18East),
.emptyEast(emptyProc18East),
.dataInEast(dataInProc18East),
.wrEast(wrProc18East),
.fullEast(fullProc18East),
.dataOutEast(dataOutProc18East));
//PROCESSOR 19
system proc19(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe19),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe19),
.wrNorth(wrProc19North),
.fullNorth(fullProc19North),
.dataOutNorth(dataOutProc19North),
.rdSouth(rdProc19South),
.emptySouth(emptyProc19South),
.dataInSouth(dataInProc19South),
.rdWest(rdProc19West),
.emptyWest(emptyProc19West),
.dataInWest(dataInProc19West),
.wrWest(wrProc19West),
.fullWest(fullProc19West),
.dataOutWest(dataOutProc19West));
//PROCESSOR 20
system proc20(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe20),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe20),
.rdNorth(rdProc20North),
.emptyNorth(emptyProc20North),
.dataInNorth(dataInProc20North),
.wrSouth(wrProc20South),
.fullSouth(fullProc20South),
.dataOutSouth(dataOutProc20South));
//PROCESSOR 21
system proc21(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe21),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe21),
.wrNorth(wrProc21North),
.fullNorth(fullProc21North),
.dataOutNorth(dataOutProc21North),
.rdSouth(rdProc21South),
.emptySouth(emptyProc21South),
.dataInSouth(dataInProc21South),
.wrEast(wrProc21East),
.fullEast(fullProc21East),
.dataOutEast(dataOutProc21East));
//PROCESSOR 22
system proc22(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe22),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe22),
.rdNorth(rdProc22North),
.emptyNorth(emptyProc22North),
.dataInNorth(dataInProc22North),
.wrNorth(wrProc22North),
.fullNorth(fullProc22North),
.dataOutNorth(dataOutProc22North),
.rdSouth(rdProc22South),
.emptySouth(emptyProc22South),
.dataInSouth(dataInProc22South),
.wrEast(wrProc22East),
.fullEast(fullProc22East),
.dataOutEast(dataOutProc22East),
.rdWest(rdProc22West),
.emptyWest(emptyProc22West),
.dataInWest(dataInProc22West));
//PROCESSOR 23
system proc23(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe23),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe23),
.rdSouth(rdProc23South),
.emptySouth(emptyProc23South),
.dataInSouth(dataInProc23South),
.wrEast(wrProc23East),
.fullEast(fullProc23East),
.dataOutEast(dataOutProc23East),
.rdWest(rdProc23West),
.emptyWest(emptyProc23West),
.dataInWest(dataInProc23West));
//PROCESSOR 24
system proc24(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe24),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe24),
.rdNorth(rdProc24North),
.emptyNorth(emptyProc24North),
.dataInNorth(dataInProc24North),
.wrNorth(wrProc24North),
.fullNorth(fullProc24North),
.dataOutNorth(dataOutProc24North),
.wrSouth(wrProc24South),
.fullSouth(fullProc24South),
.dataOutSouth(dataOutProc24South),
.wrEast(wrProc24East),
.fullEast(fullProc24East),
.dataOutEast(dataOutProc24East),
.rdWest(rdProc24West),
.emptyWest(emptyProc24West),
.dataInWest(dataInProc24West));
//PROCESSOR 25
system proc25(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe25),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe25),
.rdNorth(rdProc25North),
.emptyNorth(emptyProc25North),
.dataInNorth(dataInProc25North),
.wrSouth(wrProc25South),
.fullSouth(fullProc25South),
.dataOutSouth(dataOutProc25South),
.wrEast(wrProc25East),
.fullEast(fullProc25East),
.dataOutEast(dataOutProc25East),
.rdWest(rdProc25West),
.emptyWest(emptyProc25West),
.dataInWest(dataInProc25West));
//PROCESSOR 26
system proc26(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe26),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe26),
.rdNorth(rdProc26North),
.emptyNorth(emptyProc26North),
.dataInNorth(dataInProc26North),
.wrNorth(wrProc26North),
.fullNorth(fullProc26North),
.dataOutNorth(dataOutProc26North),
.rdSouth(rdProc26South),
.emptySouth(emptyProc26South),
.dataInSouth(dataInProc26South),
.wrSouth(wrProc26South),
.fullSouth(fullProc26South),
.dataOutSouth(dataOutProc26South),
.rdEast(rdProc26East),
.emptyEast(emptyProc26East),
.dataInEast(dataInProc26East),
.wrEast(wrProc26East),
.fullEast(fullProc26East),
.dataOutEast(dataOutProc26East),
.rdWest(rdProc26West),
.emptyWest(emptyProc26West),
.dataInWest(dataInProc26West));
//PROCESSOR 27
system proc27(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe27),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe27),
.rdSouth(rdProc27South),
.emptySouth(emptyProc27South),
.dataInSouth(dataInProc27South),
.wrEast(wrProc27East),
.fullEast(fullProc27East),
.dataOutEast(dataOutProc27East),
.rdWest(rdProc27West),
.emptyWest(emptyProc27West),
.dataInWest(dataInProc27West),
.wrWest(wrProc27West),
.fullWest(fullProc27West),
.dataOutWest(dataOutProc27West));
//PROCESSOR 28
system proc28(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe28),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe28),
.wrNorth(wrProc28North),
.fullNorth(fullProc28North),
.dataOutNorth(dataOutProc28North),
.wrEast(wrProc28East),
.fullEast(fullProc28East),
.dataOutEast(dataOutProc28East),
.rdWest(rdProc28West),
.emptyWest(emptyProc28West),
.dataInWest(dataInProc28West));
//PROCESSOR 29
system proc29(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe29),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe29),
.wrNorth(wrProc29North),
.fullNorth(fullProc29North),
.dataOutNorth(dataOutProc29North),
.rdWest(rdProc29West),
.emptyWest(emptyProc29West),
.dataInWest(dataInProc29West));
//PROCESSOR 30
system proc30(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe30),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe30),
.rdNorth(rdProc30North),
.emptyNorth(emptyProc30North),
.dataInNorth(dataInProc30North),
.wrSouth(wrProc30South),
.fullSouth(fullProc30South),
.dataOutSouth(dataOutProc30South),
.wrEast(wrProc30East),
.fullEast(fullProc30East),
.dataOutEast(dataOutProc30East));
//PROCESSOR 31
system proc31(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe31),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe31),
.wrNorth(wrProc31North),
.fullNorth(fullProc31North),
.dataOutNorth(dataOutProc31North),
.rdSouth(rdProc31South),
.emptySouth(emptyProc31South),
.dataInSouth(dataInProc31South),
.wrSouth(wrProc31South),
.fullSouth(fullProc31South),
.dataOutSouth(dataOutProc31South),
.rdEast(rdProc31East),
.emptyEast(emptyProc31East),
.dataInEast(dataInProc31East),
.rdWest(rdProc31West),
.emptyWest(emptyProc31West),
.dataInWest(dataInProc31West));
//PROCESSOR 32
system proc32(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe32),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe32),
.wrNorth(wrProc32North),
.fullNorth(fullProc32North),
.dataOutNorth(dataOutProc32North),
.rdSouth(rdProc32South),
.emptySouth(emptyProc32South),
.dataInSouth(dataInProc32South),
.wrEast(wrProc32East),
.fullEast(fullProc32East),
.dataOutEast(dataOutProc32East),
.wrWest(wrProc32West),
.fullWest(fullProc32West),
.dataOutWest(dataOutProc32West));
//PROCESSOR 33
system proc33(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe33),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe33),
.wrNorth(wrProc33North),
.fullNorth(fullProc33North),
.dataOutNorth(dataOutProc33North),
.rdWest(rdProc33West),
.emptyWest(emptyProc33West),
.dataInWest(dataInProc33West));
//PROCESSOR 34
system proc34(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe34),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe34),
.rdNorth(rdProc34North),
.emptyNorth(emptyProc34North),
.dataInNorth(dataInProc34North),
.wrSouth(wrProc34South),
.fullSouth(fullProc34South),
.dataOutSouth(dataOutProc34South));
//PROCESSOR 35
system proc35(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe35),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe35),
.rdNorth(rdProc35North),
.emptyNorth(emptyProc35North),
.dataInNorth(dataInProc35North),
.wrSouth(wrProc35South),
.fullSouth(fullProc35South),
.dataOutSouth(dataOutProc35South),
.wrEast(wrProc35East),
.fullEast(fullProc35East),
.dataOutEast(dataOutProc35East));
//PROCESSOR 36
system proc36(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe36),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe36),
.rdNorth(rdProc36North),
.emptyNorth(emptyProc36North),
.dataInNorth(dataInProc36North),
.wrNorth(wrProc36North),
.fullNorth(fullProc36North),
.dataOutNorth(dataOutProc36North),
.wrSouth(wrProc36South),
.fullSouth(fullProc36South),
.dataOutSouth(dataOutProc36South),
.rdEast(rdProc36East),
.emptyEast(emptyProc36East),
.dataInEast(dataInProc36East),
.wrEast(wrProc36East),
.fullEast(fullProc36East),
.dataOutEast(dataOutProc36East),
.rdWest(rdProc36West),
.emptyWest(emptyProc36West),
.dataInWest(dataInProc36West));
//PROCESSOR 37
system proc37(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe37),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe37),
.wrNorth(wrProc37North),
.fullNorth(fullProc37North),
.dataOutNorth(dataOutProc37North),
.wrSouth(wrProc37South),
.fullSouth(fullProc37South),
.dataOutSouth(dataOutProc37South),
.rdEast(rdProc37East),
.emptyEast(emptyProc37East),
.dataInEast(dataInProc37East),
.rdWest(rdProc37West),
.emptyWest(emptyProc37West),
.dataInWest(dataInProc37West),
.wrWest(wrProc37West),
.fullWest(fullProc37West),
.dataOutWest(dataOutProc37West));
//PROCESSOR 38
system proc38(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe38),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe38),
.rdSouth(rdProc38South),
.emptySouth(emptyProc38South),
.dataInSouth(dataInProc38South),
.rdEast(rdProc38East),
.emptyEast(emptyProc38East),
.dataInEast(dataInProc38East),
.wrEast(wrProc38East),
.fullEast(fullProc38East),
.dataOutEast(dataOutProc38East),
.wrWest(wrProc38West),
.fullWest(fullProc38West),
.dataOutWest(dataOutProc38West));
//PROCESSOR 39
system proc39(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe39),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe39),
.rdWest(rdProc39West),
.emptyWest(emptyProc39West),
.dataInWest(dataInProc39West),
.wrWest(wrProc39West),
.fullWest(fullProc39West),
.dataOutWest(dataOutProc39West));
//PROCESSOR 40
system proc40(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe40),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe40),
.rdNorth(rdProc40North),
.emptyNorth(emptyProc40North),
.dataInNorth(dataInProc40North),
.wrEast(wrProc40East),
.fullEast(fullProc40East),
.dataOutEast(dataOutProc40East));
//PROCESSOR 41
system proc41(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe41),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe41),
.rdNorth(rdProc41North),
.emptyNorth(emptyProc41North),
.dataInNorth(dataInProc41North),
.wrNorth(wrProc41North),
.fullNorth(fullProc41North),
.dataOutNorth(dataOutProc41North),
.wrEast(wrProc41East),
.fullEast(fullProc41East),
.dataOutEast(dataOutProc41East),
.rdWest(rdProc41West),
.emptyWest(emptyProc41West),
.dataInWest(dataInProc41West));
//PROCESSOR 42
system proc42(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe42),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe42),
.wrNorth(wrProc42North),
.fullNorth(fullProc42North),
.dataOutNorth(dataOutProc42North),
.rdEast(rdProc42East),
.emptyEast(emptyProc42East),
.dataInEast(dataInProc42East),
.rdWest(rdProc42West),
.emptyWest(emptyProc42West),
.dataInWest(dataInProc42West));
//PROCESSOR 43
system proc43(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe43),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe43),
.rdEast(rdProc43East),
.emptyEast(emptyProc43East),
.dataInEast(dataInProc43East),
.wrWest(wrProc43West),
.fullWest(fullProc43West),
.dataOutWest(dataOutProc43West));
//PROCESSOR 44
system proc44(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe44),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe44),
.rdNorth(rdProc44North),
.emptyNorth(emptyProc44North),
.dataInNorth(dataInProc44North),
.rdEast(rdProc44East),
.emptyEast(emptyProc44East),
.dataInEast(dataInProc44East),
.wrWest(wrProc44West),
.fullWest(fullProc44West),
.dataOutWest(dataOutProc44West));
//PROCESSOR 45
system proc45(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe45),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe45),
.rdNorth(rdProc45North),
.emptyNorth(emptyProc45North),
.dataInNorth(dataInProc45North),
.wrWest(wrProc45West),
.fullWest(fullProc45West),
.dataOutWest(dataOutProc45West));
//PROCESSOR 46
system proc46(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe46),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe46),
.rdNorth(rdProc46North),
.emptyNorth(emptyProc46North),
.dataInNorth(dataInProc46North),
.wrEast(wrProc46East),
.fullEast(fullProc46East),
.dataOutEast(dataOutProc46East));
//PROCESSOR 47
system proc47(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe47),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe47),
.rdNorth(rdProc47North),
.emptyNorth(emptyProc47North),
.dataInNorth(dataInProc47North),
.wrEast(wrProc47East),
.fullEast(fullProc47East),
.dataOutEast(dataOutProc47East),
.rdWest(rdProc47West),
.emptyWest(emptyProc47West),
.dataInWest(dataInProc47West));
//PROCESSOR 48
system proc48(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe48),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe48),
.wrNorth(wrProc48North),
.fullNorth(fullProc48North),
.dataOutNorth(dataOutProc48North),
.rdEast(rdProc48East),
.emptyEast(emptyProc48East),
.dataInEast(dataInProc48East),
.wrEast(wrProc48East),
.fullEast(fullProc48East),
.dataOutEast(dataOutProc48East),
.rdWest(rdProc48West),
.emptyWest(emptyProc48West),
.dataInWest(dataInProc48West));
//PROCESSOR 49
system proc49(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe49),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe49),
.rdWest(rdProc49West),
.emptyWest(emptyProc49West),
.dataInWest(dataInProc49West),
.wrWest(wrProc49West),
.fullWest(fullProc49West),
.dataOutWest(dataOutProc49West));
//FIFO 0 TO 10
fifo fifo_proc0_to_proc10(
.clk(clk),
.resetn(resetn),
.wr(wrProc0South),
.full(fullProc0South),
.dataIn(dataOutProc0South),
.rd(rdProc10North),
.empty(emptyProc10North),
.dataOut(dataInProc10North));
//FIFO 1 TO 0
fifo fifo_proc1_to_proc0(
.clk(clk),
.resetn(resetn),
.wr(wrProc1West),
.full(fullProc1West),
.dataIn(dataOutProc1West),
.rd(rdProc0East),
.empty(emptyProc0East),
.dataOut(dataInProc0East));
//FIFO 0 TO 1
fifo fifo_proc0_to_proc1(
.clk(clk),
.resetn(resetn),
.wr(wrProc0East),
.full(fullProc0East),
.dataIn(dataOutProc0East),
.rd(rdProc1West),
.empty(emptyProc1West),
.dataOut(dataInProc1West));
//FIFO 3 TO 2
fifo fifo_proc3_to_proc2(
.clk(clk),
.resetn(resetn),
.wr(wrProc3West),
.full(fullProc3West),
.dataIn(dataOutProc3West),
.rd(rdProc2East),
.empty(emptyProc2East),
.dataOut(dataInProc2East));
//FIFO 4 TO 3
fifo fifo_proc4_to_proc3(
.clk(clk),
.resetn(resetn),
.wr(wrProc4West),
.full(fullProc4West),
.dataIn(dataOutProc4West),
.rd(rdProc3East),
.empty(emptyProc3East),
.dataOut(dataInProc3East));
//FIFO 5 TO 4
fifo fifo_proc5_to_proc4(
.clk(clk),
.resetn(resetn),
.wr(wrProc5West),
.full(fullProc5West),
.dataIn(dataOutProc5West),
.rd(rdProc4East),
.empty(emptyProc4East),
.dataOut(dataInProc4East));
//FIFO 6 TO 5
fifo fifo_proc6_to_proc5(
.clk(clk),
.resetn(resetn),
.wr(wrProc6West),
.full(fullProc6West),
.dataIn(dataOutProc6West),
.rd(rdProc5East),
.empty(emptyProc5East),
.dataOut(dataInProc5East));
//FIFO 16 TO 6
fifo fifo_proc16_to_proc6(
.clk(clk),
.resetn(resetn),
.wr(wrProc16North),
.full(fullProc16North),
.dataIn(dataOutProc16North),
.rd(rdProc6South),
.empty(emptyProc6South),
.dataOut(dataInProc6South));
//FIFO 6 TO 16
fifo fifo_proc6_to_proc16(
.clk(clk),
.resetn(resetn),
.wr(wrProc6South),
.full(fullProc6South),
.dataIn(dataOutProc6South),
.rd(rdProc16North),
.empty(emptyProc16North),
.dataOut(dataInProc16North));
//FIFO 7 TO 6
fifo fifo_proc7_to_proc6(
.clk(clk),
.resetn(resetn),
.wr(wrProc7West),
.full(fullProc7West),
.dataIn(dataOutProc7West),
.rd(rdProc6East),
.empty(emptyProc6East),
.dataOut(dataInProc6East));
//FIFO 7 TO 17
fifo fifo_proc7_to_proc17(
.clk(clk),
.resetn(resetn),
.wr(wrProc7South),
.full(fullProc7South),
.dataIn(dataOutProc7South),
.rd(rdProc17North),
.empty(emptyProc17North),
.dataOut(dataInProc17North));
//FIFO 8 TO 7
fifo fifo_proc8_to_proc7(
.clk(clk),
.resetn(resetn),
.wr(wrProc8West),
.full(fullProc8West),
.dataIn(dataOutProc8West),
.rd(rdProc7East),
.empty(emptyProc7East),
.dataOut(dataInProc7East));
//FIFO 18 TO 8
fifo fifo_proc18_to_proc8(
.clk(clk),
.resetn(resetn),
.wr(wrProc18North),
.full(fullProc18North),
.dataIn(dataOutProc18North),
.rd(rdProc8South),
.empty(emptyProc8South),
.dataOut(dataInProc8South));
//FIFO 9 TO 8
fifo fifo_proc9_to_proc8(
.clk(clk),
.resetn(resetn),
.wr(wrProc9West),
.full(fullProc9West),
.dataIn(dataOutProc9West),
.rd(rdProc8East),
.empty(emptyProc8East),
.dataOut(dataInProc8East));
//FIFO 19 TO 9
fifo fifo_proc19_to_proc9(
.clk(clk),
.resetn(resetn),
.wr(wrProc19North),
.full(fullProc19North),
.dataIn(dataOutProc19North),
.rd(rdProc9South),
.empty(emptyProc9South),
.dataOut(dataInProc9South));
//FIFO 10 TO 20
fifo fifo_proc10_to_proc20(
.clk(clk),
.resetn(resetn),
.wr(wrProc10South),
.full(fullProc10South),
.dataIn(dataOutProc10South),
.rd(rdProc20North),
.empty(emptyProc20North),
.dataOut(dataInProc20North));
//FIFO 21 TO 11
fifo fifo_proc21_to_proc11(
.clk(clk),
.resetn(resetn),
.wr(wrProc21North),
.full(fullProc21North),
.dataIn(dataOutProc21North),
.rd(rdProc11South),
.empty(emptyProc11South),
.dataOut(dataInProc11South));
//FIFO 11 TO 12
fifo fifo_proc11_to_proc12(
.clk(clk),
.resetn(resetn),
.wr(wrProc11East),
.full(fullProc11East),
.dataIn(dataOutProc11East),
.rd(rdProc12West),
.empty(emptyProc12West),
.dataOut(dataInProc12West));
//FIFO 22 TO 12
fifo fifo_proc22_to_proc12(
.clk(clk),
.resetn(resetn),
.wr(wrProc22North),
.full(fullProc22North),
.dataIn(dataOutProc22North),
.rd(rdProc12South),
.empty(emptyProc12South),
.dataOut(dataInProc12South));
//FIFO 12 TO 22
fifo fifo_proc12_to_proc22(
.clk(clk),
.resetn(resetn),
.wr(wrProc12South),
.full(fullProc12South),
.dataIn(dataOutProc12South),
.rd(rdProc22North),
.empty(emptyProc22North),
.dataOut(dataInProc22North));
//FIFO 12 TO 13
fifo fifo_proc12_to_proc13(
.clk(clk),
.resetn(resetn),
.wr(wrProc12East),
.full(fullProc12East),
.dataIn(dataOutProc12East),
.rd(rdProc13West),
.empty(emptyProc13West),
.dataOut(dataInProc13West));
//FIFO 13 TO 14
fifo fifo_proc13_to_proc14(
.clk(clk),
.resetn(resetn),
.wr(wrProc13East),
.full(fullProc13East),
.dataIn(dataOutProc13East),
.rd(rdProc14West),
.empty(emptyProc14West),
.dataOut(dataInProc14West));
//FIFO 24 TO 14
fifo fifo_proc24_to_proc14(
.clk(clk),
.resetn(resetn),
.wr(wrProc24North),
.full(fullProc24North),
.dataIn(dataOutProc24North),
.rd(rdProc14South),
.empty(emptyProc14South),
.dataOut(dataInProc14South));
//FIFO 14 TO 24
fifo fifo_proc14_to_proc24(
.clk(clk),
.resetn(resetn),
.wr(wrProc14South),
.full(fullProc14South),
.dataIn(dataOutProc14South),
.rd(rdProc24North),
.empty(emptyProc24North),
.dataOut(dataInProc24North));
//FIFO 15 TO 14
fifo fifo_proc15_to_proc14(
.clk(clk),
.resetn(resetn),
.wr(wrProc15West),
.full(fullProc15West),
.dataIn(dataOutProc15West),
.rd(rdProc14East),
.empty(emptyProc14East),
.dataOut(dataInProc14East));
//FIFO 14 TO 15
fifo fifo_proc14_to_proc15(
.clk(clk),
.resetn(resetn),
.wr(wrProc14East),
.full(fullProc14East),
.dataIn(dataOutProc14East),
.rd(rdProc15West),
.empty(emptyProc15West),
.dataOut(dataInProc15West));
//FIFO 15 TO 25
fifo fifo_proc15_to_proc25(
.clk(clk),
.resetn(resetn),
.wr(wrProc15South),
.full(fullProc15South),
.dataIn(dataOutProc15South),
.rd(rdProc25North),
.empty(emptyProc25North),
.dataOut(dataInProc25North));
//FIFO 16 TO 15
fifo fifo_proc16_to_proc15(
.clk(clk),
.resetn(resetn),
.wr(wrProc16West),
.full(fullProc16West),
.dataIn(dataOutProc16West),
.rd(rdProc15East),
.empty(emptyProc15East),
.dataOut(dataInProc15East));
//FIFO 15 TO 16
fifo fifo_proc15_to_proc16(
.clk(clk),
.resetn(resetn),
.wr(wrProc15East),
.full(fullProc15East),
.dataIn(dataOutProc15East),
.rd(rdProc16West),
.empty(emptyProc16West),
.dataOut(dataInProc16West));
//FIFO 26 TO 16
fifo fifo_proc26_to_proc16(
.clk(clk),
.resetn(resetn),
.wr(wrProc26North),
.full(fullProc26North),
.dataIn(dataOutProc26North),
.rd(rdProc16South),
.empty(emptyProc16South),
.dataOut(dataInProc16South));
//FIFO 16 TO 26
fifo fifo_proc16_to_proc26(
.clk(clk),
.resetn(resetn),
.wr(wrProc16South),
.full(fullProc16South),
.dataIn(dataOutProc16South),
.rd(rdProc26North),
.empty(emptyProc26North),
.dataOut(dataInProc26North));
//FIFO 17 TO 16
fifo fifo_proc17_to_proc16(
.clk(clk),
.resetn(resetn),
.wr(wrProc17West),
.full(fullProc17West),
.dataIn(dataOutProc17West),
.rd(rdProc16East),
.empty(emptyProc16East),
.dataOut(dataInProc16East));
//FIFO 28 TO 18
fifo fifo_proc28_to_proc18(
.clk(clk),
.resetn(resetn),
.wr(wrProc28North),
.full(fullProc28North),
.dataIn(dataOutProc28North),
.rd(rdProc18South),
.empty(emptyProc18South),
.dataOut(dataInProc18South));
//FIFO 19 TO 18
fifo fifo_proc19_to_proc18(
.clk(clk),
.resetn(resetn),
.wr(wrProc19West),
.full(fullProc19West),
.dataIn(dataOutProc19West),
.rd(rdProc18East),
.empty(emptyProc18East),
.dataOut(dataInProc18East));
//FIFO 18 TO 19
fifo fifo_proc18_to_proc19(
.clk(clk),
.resetn(resetn),
.wr(wrProc18East),
.full(fullProc18East),
.dataIn(dataOutProc18East),
.rd(rdProc19West),
.empty(emptyProc19West),
.dataOut(dataInProc19West));
//FIFO 29 TO 19
fifo fifo_proc29_to_proc19(
.clk(clk),
.resetn(resetn),
.wr(wrProc29North),
.full(fullProc29North),
.dataIn(dataOutProc29North),
.rd(rdProc19South),
.empty(emptyProc19South),
.dataOut(dataInProc19South));
//FIFO 20 TO 30
fifo fifo_proc20_to_proc30(
.clk(clk),
.resetn(resetn),
.wr(wrProc20South),
.full(fullProc20South),
.dataIn(dataOutProc20South),
.rd(rdProc30North),
.empty(emptyProc30North),
.dataOut(dataInProc30North));
//FIFO 31 TO 21
fifo fifo_proc31_to_proc21(
.clk(clk),
.resetn(resetn),
.wr(wrProc31North),
.full(fullProc31North),
.dataIn(dataOutProc31North),
.rd(rdProc21South),
.empty(emptyProc21South),
.dataOut(dataInProc21South));
//FIFO 21 TO 22
fifo fifo_proc21_to_proc22(
.clk(clk),
.resetn(resetn),
.wr(wrProc21East),
.full(fullProc21East),
.dataIn(dataOutProc21East),
.rd(rdProc22West),
.empty(emptyProc22West),
.dataOut(dataInProc22West));
//FIFO 32 TO 22
fifo fifo_proc32_to_proc22(
.clk(clk),
.resetn(resetn),
.wr(wrProc32North),
.full(fullProc32North),
.dataIn(dataOutProc32North),
.rd(rdProc22South),
.empty(emptyProc22South),
.dataOut(dataInProc22South));
//FIFO 22 TO 23
fifo fifo_proc22_to_proc23(
.clk(clk),
.resetn(resetn),
.wr(wrProc22East),
.full(fullProc22East),
.dataIn(dataOutProc22East),
.rd(rdProc23West),
.empty(emptyProc23West),
.dataOut(dataInProc23West));
//FIFO 33 TO 23
fifo fifo_proc33_to_proc23(
.clk(clk),
.resetn(resetn),
.wr(wrProc33North),
.full(fullProc33North),
.dataIn(dataOutProc33North),
.rd(rdProc23South),
.empty(emptyProc23South),
.dataOut(dataInProc23South));
//FIFO 23 TO 24
fifo fifo_proc23_to_proc24(
.clk(clk),
.resetn(resetn),
.wr(wrProc23East),
.full(fullProc23East),
.dataIn(dataOutProc23East),
.rd(rdProc24West),
.empty(emptyProc24West),
.dataOut(dataInProc24West));
//FIFO 24 TO 34
fifo fifo_proc24_to_proc34(
.clk(clk),
.resetn(resetn),
.wr(wrProc24South),
.full(fullProc24South),
.dataIn(dataOutProc24South),
.rd(rdProc34North),
.empty(emptyProc34North),
.dataOut(dataInProc34North));
//FIFO 24 TO 25
fifo fifo_proc24_to_proc25(
.clk(clk),
.resetn(resetn),
.wr(wrProc24East),
.full(fullProc24East),
.dataIn(dataOutProc24East),
.rd(rdProc25West),
.empty(emptyProc25West),
.dataOut(dataInProc25West));
//FIFO 25 TO 35
fifo fifo_proc25_to_proc35(
.clk(clk),
.resetn(resetn),
.wr(wrProc25South),
.full(fullProc25South),
.dataIn(dataOutProc25South),
.rd(rdProc35North),
.empty(emptyProc35North),
.dataOut(dataInProc35North));
//FIFO 25 TO 26
fifo fifo_proc25_to_proc26(
.clk(clk),
.resetn(resetn),
.wr(wrProc25East),
.full(fullProc25East),
.dataIn(dataOutProc25East),
.rd(rdProc26West),
.empty(emptyProc26West),
.dataOut(dataInProc26West));
//FIFO 36 TO 26
fifo fifo_proc36_to_proc26(
.clk(clk),
.resetn(resetn),
.wr(wrProc36North),
.full(fullProc36North),
.dataIn(dataOutProc36North),
.rd(rdProc26South),
.empty(emptyProc26South),
.dataOut(dataInProc26South));
//FIFO 26 TO 36
fifo fifo_proc26_to_proc36(
.clk(clk),
.resetn(resetn),
.wr(wrProc26South),
.full(fullProc26South),
.dataIn(dataOutProc26South),
.rd(rdProc36North),
.empty(emptyProc36North),
.dataOut(dataInProc36North));
//FIFO 27 TO 26
fifo fifo_proc27_to_proc26(
.clk(clk),
.resetn(resetn),
.wr(wrProc27West),
.full(fullProc27West),
.dataIn(dataOutProc27West),
.rd(rdProc26East),
.empty(emptyProc26East),
.dataOut(dataInProc26East));
//FIFO 26 TO 27
fifo fifo_proc26_to_proc27(
.clk(clk),
.resetn(resetn),
.wr(wrProc26East),
.full(fullProc26East),
.dataIn(dataOutProc26East),
.rd(rdProc27West),
.empty(emptyProc27West),
.dataOut(dataInProc27West));
//FIFO 37 TO 27
fifo fifo_proc37_to_proc27(
.clk(clk),
.resetn(resetn),
.wr(wrProc37North),
.full(fullProc37North),
.dataIn(dataOutProc37North),
.rd(rdProc27South),
.empty(emptyProc27South),
.dataOut(dataInProc27South));
//FIFO 27 TO 28
fifo fifo_proc27_to_proc28(
.clk(clk),
.resetn(resetn),
.wr(wrProc27East),
.full(fullProc27East),
.dataIn(dataOutProc27East),
.rd(rdProc28West),
.empty(emptyProc28West),
.dataOut(dataInProc28West));
//FIFO 28 TO 29
fifo fifo_proc28_to_proc29(
.clk(clk),
.resetn(resetn),
.wr(wrProc28East),
.full(fullProc28East),
.dataIn(dataOutProc28East),
.rd(rdProc29West),
.empty(emptyProc29West),
.dataOut(dataInProc29West));
//FIFO 30 TO 40
fifo fifo_proc30_to_proc40(
.clk(clk),
.resetn(resetn),
.wr(wrProc30South),
.full(fullProc30South),
.dataIn(dataOutProc30South),
.rd(rdProc40North),
.empty(emptyProc40North),
.dataOut(dataInProc40North));
//FIFO 30 TO 31
fifo fifo_proc30_to_proc31(
.clk(clk),
.resetn(resetn),
.wr(wrProc30East),
.full(fullProc30East),
.dataIn(dataOutProc30East),
.rd(rdProc31West),
.empty(emptyProc31West),
.dataOut(dataInProc31West));
//FIFO 41 TO 31
fifo fifo_proc41_to_proc31(
.clk(clk),
.resetn(resetn),
.wr(wrProc41North),
.full(fullProc41North),
.dataIn(dataOutProc41North),
.rd(rdProc31South),
.empty(emptyProc31South),
.dataOut(dataInProc31South));
//FIFO 31 TO 41
fifo fifo_proc31_to_proc41(
.clk(clk),
.resetn(resetn),
.wr(wrProc31South),
.full(fullProc31South),
.dataIn(dataOutProc31South),
.rd(rdProc41North),
.empty(emptyProc41North),
.dataOut(dataInProc41North));
//FIFO 32 TO 31
fifo fifo_proc32_to_proc31(
.clk(clk),
.resetn(resetn),
.wr(wrProc32West),
.full(fullProc32West),
.dataIn(dataOutProc32West),
.rd(rdProc31East),
.empty(emptyProc31East),
.dataOut(dataInProc31East));
//FIFO 42 TO 32
fifo fifo_proc42_to_proc32(
.clk(clk),
.resetn(resetn),
.wr(wrProc42North),
.full(fullProc42North),
.dataIn(dataOutProc42North),
.rd(rdProc32South),
.empty(emptyProc32South),
.dataOut(dataInProc32South));
//FIFO 32 TO 33
fifo fifo_proc32_to_proc33(
.clk(clk),
.resetn(resetn),
.wr(wrProc32East),
.full(fullProc32East),
.dataIn(dataOutProc32East),
.rd(rdProc33West),
.empty(emptyProc33West),
.dataOut(dataInProc33West));
//FIFO 34 TO 44
fifo fifo_proc34_to_proc44(
.clk(clk),
.resetn(resetn),
.wr(wrProc34South),
.full(fullProc34South),
.dataIn(dataOutProc34South),
.rd(rdProc44North),
.empty(emptyProc44North),
.dataOut(dataInProc44North));
//FIFO 35 TO 45
fifo fifo_proc35_to_proc45(
.clk(clk),
.resetn(resetn),
.wr(wrProc35South),
.full(fullProc35South),
.dataIn(dataOutProc35South),
.rd(rdProc45North),
.empty(emptyProc45North),
.dataOut(dataInProc45North));
//FIFO 35 TO 36
fifo fifo_proc35_to_proc36(
.clk(clk),
.resetn(resetn),
.wr(wrProc35East),
.full(fullProc35East),
.dataIn(dataOutProc35East),
.rd(rdProc36West),
.empty(emptyProc36West),
.dataOut(dataInProc36West));
//FIFO 36 TO 46
fifo fifo_proc36_to_proc46(
.clk(clk),
.resetn(resetn),
.wr(wrProc36South),
.full(fullProc36South),
.dataIn(dataOutProc36South),
.rd(rdProc46North),
.empty(emptyProc46North),
.dataOut(dataInProc46North));
//FIFO 37 TO 36
fifo fifo_proc37_to_proc36(
.clk(clk),
.resetn(resetn),
.wr(wrProc37West),
.full(fullProc37West),
.dataIn(dataOutProc37West),
.rd(rdProc36East),
.empty(emptyProc36East),
.dataOut(dataInProc36East));
//FIFO 36 TO 37
fifo fifo_proc36_to_proc37(
.clk(clk),
.resetn(resetn),
.wr(wrProc36East),
.full(fullProc36East),
.dataIn(dataOutProc36East),
.rd(rdProc37West),
.empty(emptyProc37West),
.dataOut(dataInProc37West));
//FIFO 37 TO 47
fifo fifo_proc37_to_proc47(
.clk(clk),
.resetn(resetn),
.wr(wrProc37South),
.full(fullProc37South),
.dataIn(dataOutProc37South),
.rd(rdProc47North),
.empty(emptyProc47North),
.dataOut(dataInProc47North));
//FIFO 38 TO 37
fifo fifo_proc38_to_proc37(
.clk(clk),
.resetn(resetn),
.wr(wrProc38West),
.full(fullProc38West),
.dataIn(dataOutProc38West),
.rd(rdProc37East),
.empty(emptyProc37East),
.dataOut(dataInProc37East));
//FIFO 48 TO 38
fifo fifo_proc48_to_proc38(
.clk(clk),
.resetn(resetn),
.wr(wrProc48North),
.full(fullProc48North),
.dataIn(dataOutProc48North),
.rd(rdProc38South),
.empty(emptyProc38South),
.dataOut(dataInProc38South));
//FIFO 39 TO 38
fifo fifo_proc39_to_proc38(
.clk(clk),
.resetn(resetn),
.wr(wrProc39West),
.full(fullProc39West),
.dataIn(dataOutProc39West),
.rd(rdProc38East),
.empty(emptyProc38East),
.dataOut(dataInProc38East));
//FIFO 38 TO 39
fifo fifo_proc38_to_proc39(
.clk(clk),
.resetn(resetn),
.wr(wrProc38East),
.full(fullProc38East),
.dataIn(dataOutProc38East),
.rd(rdProc39West),
.empty(emptyProc39West),
.dataOut(dataInProc39West));
//FIFO 40 TO 41
fifo fifo_proc40_to_proc41(
.clk(clk),
.resetn(resetn),
.wr(wrProc40East),
.full(fullProc40East),
.dataIn(dataOutProc40East),
.rd(rdProc41West),
.empty(emptyProc41West),
.dataOut(dataInProc41West));
//FIFO 41 TO 42
fifo fifo_proc41_to_proc42(
.clk(clk),
.resetn(resetn),
.wr(wrProc41East),
.full(fullProc41East),
.dataIn(dataOutProc41East),
.rd(rdProc42West),
.empty(emptyProc42West),
.dataOut(dataInProc42West));
//FIFO 43 TO 42
fifo fifo_proc43_to_proc42(
.clk(clk),
.resetn(resetn),
.wr(wrProc43West),
.full(fullProc43West),
.dataIn(dataOutProc43West),
.rd(rdProc42East),
.empty(emptyProc42East),
.dataOut(dataInProc42East));
//FIFO 44 TO 43
fifo fifo_proc44_to_proc43(
.clk(clk),
.resetn(resetn),
.wr(wrProc44West),
.full(fullProc44West),
.dataIn(dataOutProc44West),
.rd(rdProc43East),
.empty(emptyProc43East),
.dataOut(dataInProc43East));
//FIFO 45 TO 44
fifo fifo_proc45_to_proc44(
.clk(clk),
.resetn(resetn),
.wr(wrProc45West),
.full(fullProc45West),
.dataIn(dataOutProc45West),
.rd(rdProc44East),
.empty(emptyProc44East),
.dataOut(dataInProc44East));
//FIFO 46 TO 47
fifo fifo_proc46_to_proc47(
.clk(clk),
.resetn(resetn),
.wr(wrProc46East),
.full(fullProc46East),
.dataIn(dataOutProc46East),
.rd(rdProc47West),
.empty(emptyProc47West),
.dataOut(dataInProc47West));
//FIFO 47 TO 48
fifo fifo_proc47_to_proc48(
.clk(clk),
.resetn(resetn),
.wr(wrProc47East),
.full(fullProc47East),
.dataIn(dataOutProc47East),
.rd(rdProc48West),
.empty(emptyProc48West),
.dataOut(dataInProc48West));
//FIFO 49 TO 48
fifo fifo_proc49_to_proc48(
.clk(clk),
.resetn(resetn),
.wr(wrProc49West),
.full(fullProc49West),
.dataIn(dataOutProc49West),
.rd(rdProc48East),
.empty(emptyProc48East),
.dataOut(dataInProc48East));
//FIFO 48 TO 49
fifo fifo_proc48_to_proc49(
.clk(clk),
.resetn(resetn),
.wr(wrProc48East),
.full(fullProc48East),
.dataIn(dataOutProc48East),
.rd(rdProc49West),
.empty(emptyProc49West),
.dataOut(dataInProc49West));
/**************** Boot loader ********************/
/*******Boot up each processor one by one*********/
always@(posedge clk)
begin
case(processor_select)
0: begin
boot_iwe0 = ~resetn;
boot_dwe0 = ~resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
end
1: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = ~resetn;
boot_dwe1 = ~resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
end
2: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = ~resetn;
boot_dwe2 = ~resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
end
3: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = ~resetn;
boot_dwe3 = ~resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
end
4: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = ~resetn;
boot_dwe4 = ~resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
end
5: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = ~resetn;
boot_dwe5 = ~resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
end
6: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = ~resetn;
boot_dwe6 = ~resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
end
7: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = ~resetn;
boot_dwe7 = ~resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
end
8: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = ~resetn;
boot_dwe8 = ~resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
end
9: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = ~resetn;
boot_dwe9 = ~resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
end
10: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = ~resetn;
boot_dwe10 = ~resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
end
11: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = ~resetn;
boot_dwe11 = ~resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
end
12: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = ~resetn;
boot_dwe12 = ~resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
end
13: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = ~resetn;
boot_dwe13 = ~resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
end
14: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = ~resetn;
boot_dwe14 = ~resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
end
15: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = ~resetn;
boot_dwe15 = ~resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
end
16: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = ~resetn;
boot_dwe16 = ~resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
end
17: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = ~resetn;
boot_dwe17 = ~resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
end
18: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = ~resetn;
boot_dwe18 = ~resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
end
19: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = ~resetn;
boot_dwe19 = ~resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
end
20: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = ~resetn;
boot_dwe20 = ~resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
end
21: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = ~resetn;
boot_dwe21 = ~resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
end
22: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = ~resetn;
boot_dwe22 = ~resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
end
23: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = ~resetn;
boot_dwe23 = ~resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
end
24: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = ~resetn;
boot_dwe24 = ~resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
end
25: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = ~resetn;
boot_dwe25 = ~resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
end
26: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = ~resetn;
boot_dwe26 = ~resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
end
27: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = ~resetn;
boot_dwe27 = ~resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
end
28: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = ~resetn;
boot_dwe28 = ~resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
end
29: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = ~resetn;
boot_dwe29 = ~resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
end
30: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = ~resetn;
boot_dwe30 = ~resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
end
31: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = ~resetn;
boot_dwe31 = ~resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
end
32: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = ~resetn;
boot_dwe32 = ~resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
end
33: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = ~resetn;
boot_dwe33 = ~resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
end
34: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = ~resetn;
boot_dwe34 = ~resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
end
35: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = ~resetn;
boot_dwe35 = ~resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
end
36: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = ~resetn;
boot_dwe36 = ~resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
end
37: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = ~resetn;
boot_dwe37 = ~resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
end
38: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = ~resetn;
boot_dwe38 = ~resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
end
39: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = ~resetn;
boot_dwe39 = ~resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
end
40: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = ~resetn;
boot_dwe40 = ~resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
end
41: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = ~resetn;
boot_dwe41 = ~resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
end
42: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = ~resetn;
boot_dwe42 = ~resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
end
43: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = ~resetn;
boot_dwe43 = ~resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
end
44: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = ~resetn;
boot_dwe44 = ~resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
end
45: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = ~resetn;
boot_dwe45 = ~resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
end
46: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = ~resetn;
boot_dwe46 = ~resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
end
47: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = ~resetn;
boot_dwe47 = ~resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
end
48: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = ~resetn;
boot_dwe48 = ~resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
end
49: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = ~resetn;
boot_dwe49 = ~resetn;
end
50: begin
boot_iwe0 = 0;
boot_dwe0 = 0;
boot_iwe1 = 0;
boot_dwe1 = 0;
boot_iwe2 = 0;
boot_dwe2 = 0;
boot_iwe3 = 0;
boot_dwe3 = 0;
boot_iwe4 = 0;
boot_dwe4 = 0;
boot_iwe5 = 0;
boot_dwe5 = 0;
boot_iwe6 = 0;
boot_dwe6 = 0;
boot_iwe7 = 0;
boot_dwe7 = 0;
boot_iwe8 = 0;
boot_dwe8 = 0;
boot_iwe9 = 0;
boot_dwe9 = 0;
boot_iwe10 = 0;
boot_dwe10 = 0;
boot_iwe11 = 0;
boot_dwe11 = 0;
boot_iwe12 = 0;
boot_dwe12 = 0;
boot_iwe13 = 0;
boot_dwe13 = 0;
boot_iwe14 = 0;
boot_dwe14 = 0;
boot_iwe15 = 0;
boot_dwe15 = 0;
boot_iwe16 = 0;
boot_dwe16 = 0;
boot_iwe17 = 0;
boot_dwe17 = 0;
boot_iwe18 = 0;
boot_dwe18 = 0;
boot_iwe19 = 0;
boot_dwe19 = 0;
boot_iwe20 = 0;
boot_dwe20 = 0;
boot_iwe21 = 0;
boot_dwe21 = 0;
boot_iwe22 = 0;
boot_dwe22 = 0;
boot_iwe23 = 0;
boot_dwe23 = 0;
boot_iwe24 = 0;
boot_dwe24 = 0;
boot_iwe25 = 0;
boot_dwe25 = 0;
boot_iwe26 = 0;
boot_dwe26 = 0;
boot_iwe27 = 0;
boot_dwe27 = 0;
boot_iwe28 = 0;
boot_dwe28 = 0;
boot_iwe29 = 0;
boot_dwe29 = 0;
boot_iwe30 = 0;
boot_dwe30 = 0;
boot_iwe31 = 0;
boot_dwe31 = 0;
boot_iwe32 = 0;
boot_dwe32 = 0;
boot_iwe33 = 0;
boot_dwe33 = 0;
boot_iwe34 = 0;
boot_dwe34 = 0;
boot_iwe35 = 0;
boot_dwe35 = 0;
boot_iwe36 = 0;
boot_dwe36 = 0;
boot_iwe37 = 0;
boot_dwe37 = 0;
boot_iwe38 = 0;
boot_dwe38 = 0;
boot_iwe39 = 0;
boot_dwe39 = 0;
boot_iwe40 = 0;
boot_dwe40 = 0;
boot_iwe41 = 0;
boot_dwe41 = 0;
boot_iwe42 = 0;
boot_dwe42 = 0;
boot_iwe43 = 0;
boot_dwe43 = 0;
boot_iwe44 = 0;
boot_dwe44 = 0;
boot_iwe45 = 0;
boot_dwe45 = 0;
boot_iwe46 = 0;
boot_dwe46 = 0;
boot_iwe47 = 0;
boot_dwe47 = 0;
boot_iwe48 = 0;
boot_dwe48 = 0;
boot_iwe49 = 0;
boot_dwe49 = 0;
end
endcase
end
endmodule |
`timescale 1ns / 1ns
module system90(clk,resetn,boot_iaddr,boot_idata,boot_daddr,boot_ddata,reg_file_b_readdataout,processor_select);
input clk;
input resetn;
input [6:0] processor_select;
output [31:0] reg_file_b_readdataout;
input [13:0] boot_iaddr;
input [31:0] boot_idata;
input [13:0] boot_daddr;
input [31:0] boot_ddata;
reg boot_iwe0;
reg boot_dwe0;
reg boot_iwe1;
reg boot_dwe1;
reg boot_iwe2;
reg boot_dwe2;
reg boot_iwe3;
reg boot_dwe3;
reg boot_iwe4;
reg boot_dwe4;
reg boot_iwe5;
reg boot_dwe5;
reg boot_iwe6;
reg boot_dwe6;
reg boot_iwe7;
reg boot_dwe7;
reg boot_iwe8;
reg boot_dwe8;
reg boot_iwe9;
reg boot_dwe9;
reg boot_iwe10;
reg boot_dwe10;
reg boot_iwe11;
reg boot_dwe11;
reg boot_iwe12;
reg boot_dwe12;
reg boot_iwe13;
reg boot_dwe13;
reg boot_iwe14;
reg boot_dwe14;
reg boot_iwe15;
reg boot_dwe15;
reg boot_iwe16;
reg boot_dwe16;
reg boot_iwe17;
reg boot_dwe17;
reg boot_iwe18;
reg boot_dwe18;
reg boot_iwe19;
reg boot_dwe19;
reg boot_iwe20;
reg boot_dwe20;
reg boot_iwe21;
reg boot_dwe21;
reg boot_iwe22;
reg boot_dwe22;
reg boot_iwe23;
reg boot_dwe23;
reg boot_iwe24;
reg boot_dwe24;
reg boot_iwe25;
reg boot_dwe25;
reg boot_iwe26;
reg boot_dwe26;
reg boot_iwe27;
reg boot_dwe27;
reg boot_iwe28;
reg boot_dwe28;
reg boot_iwe29;
reg boot_dwe29;
reg boot_iwe30;
reg boot_dwe30;
reg boot_iwe31;
reg boot_dwe31;
reg boot_iwe32;
reg boot_dwe32;
reg boot_iwe33;
reg boot_dwe33;
reg boot_iwe34;
reg boot_dwe34;
reg boot_iwe35;
reg boot_dwe35;
reg boot_iwe36;
reg boot_dwe36;
reg boot_iwe37;
reg boot_dwe37;
reg boot_iwe38;
reg boot_dwe38;
reg boot_iwe39;
reg boot_dwe39;
reg boot_iwe40;
reg boot_dwe40;
reg boot_iwe41;
reg boot_dwe41;
reg boot_iwe42;
reg boot_dwe42;
reg boot_iwe43;
reg boot_dwe43;
reg boot_iwe44;
reg boot_dwe44;
reg boot_iwe45;
reg boot_dwe45;
reg boot_iwe46;
reg boot_dwe46;
reg boot_iwe47;
reg boot_dwe47;
reg boot_iwe48;
reg boot_dwe48;
reg boot_iwe49;
reg boot_dwe49;
reg boot_iwe50;
reg boot_dwe50;
reg boot_iwe51;
reg boot_dwe51;
reg boot_iwe52;
reg boot_dwe52;
reg boot_iwe53;
reg boot_dwe53;
reg boot_iwe54;
reg boot_dwe54;
reg boot_iwe55;
reg boot_dwe55;
reg boot_iwe56;
reg boot_dwe56;
reg boot_iwe57;
reg boot_dwe57;
reg boot_iwe58;
reg boot_dwe58;
reg boot_iwe59;
reg boot_dwe59;
reg boot_iwe60;
reg boot_dwe60;
reg boot_iwe61;
reg boot_dwe61;
reg boot_iwe62;
reg boot_dwe62;
reg boot_iwe63;
reg boot_dwe63;
reg boot_iwe64;
reg boot_dwe64;
reg boot_iwe65;
reg boot_dwe65;
reg boot_iwe66;
reg boot_dwe66;
reg boot_iwe67;
reg boot_dwe67;
reg boot_iwe68;
reg boot_dwe68;
reg boot_iwe69;
reg boot_dwe69;
reg boot_iwe70;
reg boot_dwe70;
reg boot_iwe71;
reg boot_dwe71;
reg boot_iwe72;
reg boot_dwe72;
reg boot_iwe73;
reg boot_dwe73;
reg boot_iwe74;
reg boot_dwe74;
reg boot_iwe75;
reg boot_dwe75;
reg boot_iwe76;
reg boot_dwe76;
reg boot_iwe77;
reg boot_dwe77;
reg boot_iwe78;
reg boot_dwe78;
reg boot_iwe79;
reg boot_dwe79;
reg boot_iwe80;
reg boot_dwe80;
reg boot_iwe81;
reg boot_dwe81;
reg boot_iwe82;
reg boot_dwe82;
reg boot_iwe83;
reg boot_dwe83;
reg boot_iwe84;
reg boot_dwe84;
reg boot_iwe85;
reg boot_dwe85;
reg boot_iwe86;
reg boot_dwe86;
reg boot_iwe87;
reg boot_dwe87;
reg boot_iwe88;
reg boot_dwe88;
reg boot_iwe89;
reg boot_dwe89;
//Processor 0 control and data signals
wire wrProc0South;
wire fullProc0South;
wire [31:0] dataOutProc0South;
//Processor 0 control and data signals
wire wrProc0East;
wire fullProc0East;
wire [31:0] dataOutProc0East;
//Processor 1 control and data signals
wire wrProc1South;
wire fullProc1South;
wire [31:0] dataOutProc1South;
//Processor 1 control and data signals
wire rdProc1West;
wire emptyProc1West;
wire [31:0] dataInProc1West;
//Processor 4 control and data signals
wire rdProc4South;
wire emptyProc4South;
wire [31:0] dataInProc4South;
//Processor 4 control and data signals
wire rdProc4East;
wire emptyProc4East;
wire [31:0] dataInProc4East;
//Processor 4 control and data signals
wire wrProc4East;
wire fullProc4East;
wire [31:0] dataOutProc4East;
//Processor 5 control and data signals
wire rdProc5East;
wire emptyProc5East;
wire [31:0] dataInProc5East;
//Processor 5 control and data signals
wire rdProc5West;
wire emptyProc5West;
wire [31:0] dataInProc5West;
//Processor 5 control and data signals
wire wrProc5West;
wire fullProc5West;
wire [31:0] dataOutProc5West;
//Processor 6 control and data signals
wire rdProc6South;
wire emptyProc6South;
wire [31:0] dataInProc6South;
//Processor 6 control and data signals
wire wrProc6South;
wire fullProc6South;
wire [31:0] dataOutProc6South;
//Processor 6 control and data signals
wire rdProc6East;
wire emptyProc6East;
wire [31:0] dataInProc6East;
//Processor 6 control and data signals
wire wrProc6West;
wire fullProc6West;
wire [31:0] dataOutProc6West;
//Processor 7 control and data signals
wire rdProc7South;
wire emptyProc7South;
wire [31:0] dataInProc7South;
//Processor 7 control and data signals
wire wrProc7West;
wire fullProc7West;
wire [31:0] dataOutProc7West;
//Processor 8 control and data signals
wire rdProc8South;
wire emptyProc8South;
wire [31:0] dataInProc8South;
//Processor 8 control and data signals
wire wrProc8South;
wire fullProc8South;
wire [31:0] dataOutProc8South;
//Processor 8 control and data signals
wire rdProc8East;
wire emptyProc8East;
wire [31:0] dataInProc8East;
//Processor 9 control and data signals
wire rdProc9South;
wire emptyProc9South;
wire [31:0] dataInProc9South;
//Processor 9 control and data signals
wire wrProc9West;
wire fullProc9West;
wire [31:0] dataOutProc9West;
//Processor 10 control and data signals
wire rdProc10North;
wire emptyProc10North;
wire [31:0] dataInProc10North;
//Processor 10 control and data signals
wire wrProc10East;
wire fullProc10East;
wire [31:0] dataOutProc10East;
//Processor 11 control and data signals
wire rdProc11North;
wire emptyProc11North;
wire [31:0] dataInProc11North;
//Processor 11 control and data signals
wire wrProc11South;
wire fullProc11South;
wire [31:0] dataOutProc11South;
//Processor 11 control and data signals
wire rdProc11West;
wire emptyProc11West;
wire [31:0] dataInProc11West;
//Processor 12 control and data signals
wire rdProc12South;
wire emptyProc12South;
wire [31:0] dataInProc12South;
//Processor 12 control and data signals
wire wrProc12East;
wire fullProc12East;
wire [31:0] dataOutProc12East;
//Processor 13 control and data signals
wire rdProc13South;
wire emptyProc13South;
wire [31:0] dataInProc13South;
//Processor 13 control and data signals
wire wrProc13East;
wire fullProc13East;
wire [31:0] dataOutProc13East;
//Processor 13 control and data signals
wire rdProc13West;
wire emptyProc13West;
wire [31:0] dataInProc13West;
//Processor 14 control and data signals
wire wrProc14North;
wire fullProc14North;
wire [31:0] dataOutProc14North;
//Processor 14 control and data signals
wire rdProc14South;
wire emptyProc14South;
wire [31:0] dataInProc14South;
//Processor 14 control and data signals
wire wrProc14South;
wire fullProc14South;
wire [31:0] dataOutProc14South;
//Processor 14 control and data signals
wire wrProc14East;
wire fullProc14East;
wire [31:0] dataOutProc14East;
//Processor 14 control and data signals
wire rdProc14West;
wire emptyProc14West;
wire [31:0] dataInProc14West;
//Processor 15 control and data signals
wire wrProc15East;
wire fullProc15East;
wire [31:0] dataOutProc15East;
//Processor 15 control and data signals
wire rdProc15West;
wire emptyProc15West;
wire [31:0] dataInProc15West;
//Processor 16 control and data signals
wire rdProc16North;
wire emptyProc16North;
wire [31:0] dataInProc16North;
//Processor 16 control and data signals
wire wrProc16North;
wire fullProc16North;
wire [31:0] dataOutProc16North;
//Processor 16 control and data signals
wire wrProc16South;
wire fullProc16South;
wire [31:0] dataOutProc16South;
//Processor 16 control and data signals
wire rdProc16West;
wire emptyProc16West;
wire [31:0] dataInProc16West;
//Processor 17 control and data signals
wire wrProc17North;
wire fullProc17North;
wire [31:0] dataOutProc17North;
//Processor 17 control and data signals
wire rdProc17South;
wire emptyProc17South;
wire [31:0] dataInProc17South;
//Processor 18 control and data signals
wire rdProc18North;
wire emptyProc18North;
wire [31:0] dataInProc18North;
//Processor 18 control and data signals
wire wrProc18North;
wire fullProc18North;
wire [31:0] dataOutProc18North;
//Processor 18 control and data signals
wire wrProc18South;
wire fullProc18South;
wire [31:0] dataOutProc18South;
//Processor 19 control and data signals
wire wrProc19North;
wire fullProc19North;
wire [31:0] dataOutProc19North;
//Processor 19 control and data signals
wire rdProc19South;
wire emptyProc19South;
wire [31:0] dataInProc19South;
//Processor 19 control and data signals
wire wrProc19South;
wire fullProc19South;
wire [31:0] dataOutProc19South;
//Processor 20 control and data signals
wire rdProc20South;
wire emptyProc20South;
wire [31:0] dataInProc20South;
//Processor 20 control and data signals
wire wrProc20East;
wire fullProc20East;
wire [31:0] dataOutProc20East;
//Processor 21 control and data signals
wire rdProc21North;
wire emptyProc21North;
wire [31:0] dataInProc21North;
//Processor 21 control and data signals
wire rdProc21South;
wire emptyProc21South;
wire [31:0] dataInProc21South;
//Processor 21 control and data signals
wire wrProc21South;
wire fullProc21South;
wire [31:0] dataOutProc21South;
//Processor 21 control and data signals
wire wrProc21East;
wire fullProc21East;
wire [31:0] dataOutProc21East;
//Processor 21 control and data signals
wire rdProc21West;
wire emptyProc21West;
wire [31:0] dataInProc21West;
//Processor 22 control and data signals
wire wrProc22North;
wire fullProc22North;
wire [31:0] dataOutProc22North;
//Processor 22 control and data signals
wire rdProc22South;
wire emptyProc22South;
wire [31:0] dataInProc22South;
//Processor 22 control and data signals
wire wrProc22South;
wire fullProc22South;
wire [31:0] dataOutProc22South;
//Processor 22 control and data signals
wire rdProc22East;
wire emptyProc22East;
wire [31:0] dataInProc22East;
//Processor 22 control and data signals
wire wrProc22East;
wire fullProc22East;
wire [31:0] dataOutProc22East;
//Processor 22 control and data signals
wire rdProc22West;
wire emptyProc22West;
wire [31:0] dataInProc22West;
//Processor 23 control and data signals
wire wrProc23North;
wire fullProc23North;
wire [31:0] dataOutProc23North;
//Processor 23 control and data signals
wire rdProc23South;
wire emptyProc23South;
wire [31:0] dataInProc23South;
//Processor 23 control and data signals
wire rdProc23East;
wire emptyProc23East;
wire [31:0] dataInProc23East;
//Processor 23 control and data signals
wire wrProc23East;
wire fullProc23East;
wire [31:0] dataOutProc23East;
//Processor 23 control and data signals
wire rdProc23West;
wire emptyProc23West;
wire [31:0] dataInProc23West;
//Processor 23 control and data signals
wire wrProc23West;
wire fullProc23West;
wire [31:0] dataOutProc23West;
//Processor 24 control and data signals
wire rdProc24North;
wire emptyProc24North;
wire [31:0] dataInProc24North;
//Processor 24 control and data signals
wire wrProc24North;
wire fullProc24North;
wire [31:0] dataOutProc24North;
//Processor 24 control and data signals
wire wrProc24South;
wire fullProc24South;
wire [31:0] dataOutProc24South;
//Processor 24 control and data signals
wire rdProc24East;
wire emptyProc24East;
wire [31:0] dataInProc24East;
//Processor 24 control and data signals
wire wrProc24East;
wire fullProc24East;
wire [31:0] dataOutProc24East;
//Processor 24 control and data signals
wire rdProc24West;
wire emptyProc24West;
wire [31:0] dataInProc24West;
//Processor 24 control and data signals
wire wrProc24West;
wire fullProc24West;
wire [31:0] dataOutProc24West;
//Processor 25 control and data signals
wire rdProc25South;
wire emptyProc25South;
wire [31:0] dataInProc25South;
//Processor 25 control and data signals
wire wrProc25South;
wire fullProc25South;
wire [31:0] dataOutProc25South;
//Processor 25 control and data signals
wire rdProc25East;
wire emptyProc25East;
wire [31:0] dataInProc25East;
//Processor 25 control and data signals
wire wrProc25East;
wire fullProc25East;
wire [31:0] dataOutProc25East;
//Processor 25 control and data signals
wire rdProc25West;
wire emptyProc25West;
wire [31:0] dataInProc25West;
//Processor 25 control and data signals
wire wrProc25West;
wire fullProc25West;
wire [31:0] dataOutProc25West;
//Processor 26 control and data signals
wire rdProc26North;
wire emptyProc26North;
wire [31:0] dataInProc26North;
//Processor 26 control and data signals
wire wrProc26South;
wire fullProc26South;
wire [31:0] dataOutProc26South;
//Processor 26 control and data signals
wire wrProc26East;
wire fullProc26East;
wire [31:0] dataOutProc26East;
//Processor 26 control and data signals
wire rdProc26West;
wire emptyProc26West;
wire [31:0] dataInProc26West;
//Processor 26 control and data signals
wire wrProc26West;
wire fullProc26West;
wire [31:0] dataOutProc26West;
//Processor 27 control and data signals
wire wrProc27North;
wire fullProc27North;
wire [31:0] dataOutProc27North;
//Processor 27 control and data signals
wire wrProc27South;
wire fullProc27South;
wire [31:0] dataOutProc27South;
//Processor 27 control and data signals
wire rdProc27East;
wire emptyProc27East;
wire [31:0] dataInProc27East;
//Processor 27 control and data signals
wire wrProc27East;
wire fullProc27East;
wire [31:0] dataOutProc27East;
//Processor 27 control and data signals
wire rdProc27West;
wire emptyProc27West;
wire [31:0] dataInProc27West;
//Processor 28 control and data signals
wire rdProc28North;
wire emptyProc28North;
wire [31:0] dataInProc28North;
//Processor 28 control and data signals
wire wrProc28South;
wire fullProc28South;
wire [31:0] dataOutProc28South;
//Processor 28 control and data signals
wire rdProc28East;
wire emptyProc28East;
wire [31:0] dataInProc28East;
//Processor 28 control and data signals
wire rdProc28West;
wire emptyProc28West;
wire [31:0] dataInProc28West;
//Processor 28 control and data signals
wire wrProc28West;
wire fullProc28West;
wire [31:0] dataOutProc28West;
//Processor 29 control and data signals
wire rdProc29North;
wire emptyProc29North;
wire [31:0] dataInProc29North;
//Processor 29 control and data signals
wire wrProc29North;
wire fullProc29North;
wire [31:0] dataOutProc29North;
//Processor 29 control and data signals
wire rdProc29South;
wire emptyProc29South;
wire [31:0] dataInProc29South;
//Processor 29 control and data signals
wire wrProc29West;
wire fullProc29West;
wire [31:0] dataOutProc29West;
//Processor 30 control and data signals
wire wrProc30North;
wire fullProc30North;
wire [31:0] dataOutProc30North;
//Processor 30 control and data signals
wire rdProc30South;
wire emptyProc30South;
wire [31:0] dataInProc30South;
//Processor 31 control and data signals
wire rdProc31North;
wire emptyProc31North;
wire [31:0] dataInProc31North;
//Processor 31 control and data signals
wire wrProc31North;
wire fullProc31North;
wire [31:0] dataOutProc31North;
//Processor 32 control and data signals
wire rdProc32North;
wire emptyProc32North;
wire [31:0] dataInProc32North;
//Processor 32 control and data signals
wire wrProc32North;
wire fullProc32North;
wire [31:0] dataOutProc32North;
//Processor 33 control and data signals
wire wrProc33North;
wire fullProc33North;
wire [31:0] dataOutProc33North;
//Processor 33 control and data signals
wire rdProc33South;
wire emptyProc33South;
wire [31:0] dataInProc33South;
//Processor 33 control and data signals
wire wrProc33South;
wire fullProc33South;
wire [31:0] dataOutProc33South;
//Processor 33 control and data signals
wire rdProc33East;
wire emptyProc33East;
wire [31:0] dataInProc33East;
//Processor 34 control and data signals
wire rdProc34North;
wire emptyProc34North;
wire [31:0] dataInProc34North;
//Processor 34 control and data signals
wire wrProc34West;
wire fullProc34West;
wire [31:0] dataOutProc34West;
//Processor 35 control and data signals
wire rdProc35North;
wire emptyProc35North;
wire [31:0] dataInProc35North;
//Processor 35 control and data signals
wire wrProc35North;
wire fullProc35North;
wire [31:0] dataOutProc35North;
//Processor 35 control and data signals
wire rdProc35South;
wire emptyProc35South;
wire [31:0] dataInProc35South;
//Processor 35 control and data signals
wire wrProc35East;
wire fullProc35East;
wire [31:0] dataOutProc35East;
//Processor 36 control and data signals
wire rdProc36North;
wire emptyProc36North;
wire [31:0] dataInProc36North;
//Processor 36 control and data signals
wire wrProc36South;
wire fullProc36South;
wire [31:0] dataOutProc36South;
//Processor 36 control and data signals
wire wrProc36East;
wire fullProc36East;
wire [31:0] dataOutProc36East;
//Processor 36 control and data signals
wire rdProc36West;
wire emptyProc36West;
wire [31:0] dataInProc36West;
//Processor 37 control and data signals
wire rdProc37North;
wire emptyProc37North;
wire [31:0] dataInProc37North;
//Processor 37 control and data signals
wire wrProc37South;
wire fullProc37South;
wire [31:0] dataOutProc37South;
//Processor 37 control and data signals
wire rdProc37West;
wire emptyProc37West;
wire [31:0] dataInProc37West;
//Processor 38 control and data signals
wire rdProc38North;
wire emptyProc38North;
wire [31:0] dataInProc38North;
//Processor 38 control and data signals
wire rdProc38South;
wire emptyProc38South;
wire [31:0] dataInProc38South;
//Processor 38 control and data signals
wire wrProc38South;
wire fullProc38South;
wire [31:0] dataOutProc38South;
//Processor 38 control and data signals
wire wrProc38East;
wire fullProc38East;
wire [31:0] dataOutProc38East;
//Processor 39 control and data signals
wire wrProc39North;
wire fullProc39North;
wire [31:0] dataOutProc39North;
//Processor 39 control and data signals
wire rdProc39South;
wire emptyProc39South;
wire [31:0] dataInProc39South;
//Processor 39 control and data signals
wire rdProc39West;
wire emptyProc39West;
wire [31:0] dataInProc39West;
//Processor 40 control and data signals
wire wrProc40North;
wire fullProc40North;
wire [31:0] dataOutProc40North;
//Processor 40 control and data signals
wire rdProc40South;
wire emptyProc40South;
wire [31:0] dataInProc40South;
//Processor 40 control and data signals
wire wrProc40South;
wire fullProc40South;
wire [31:0] dataOutProc40South;
//Processor 40 control and data signals
wire rdProc40East;
wire emptyProc40East;
wire [31:0] dataInProc40East;
//Processor 41 control and data signals
wire rdProc41East;
wire emptyProc41East;
wire [31:0] dataInProc41East;
//Processor 41 control and data signals
wire wrProc41West;
wire fullProc41West;
wire [31:0] dataOutProc41West;
//Processor 42 control and data signals
wire rdProc42South;
wire emptyProc42South;
wire [31:0] dataInProc42South;
//Processor 42 control and data signals
wire rdProc42East;
wire emptyProc42East;
wire [31:0] dataInProc42East;
//Processor 42 control and data signals
wire wrProc42East;
wire fullProc42East;
wire [31:0] dataOutProc42East;
//Processor 42 control and data signals
wire wrProc42West;
wire fullProc42West;
wire [31:0] dataOutProc42West;
//Processor 43 control and data signals
wire rdProc43North;
wire emptyProc43North;
wire [31:0] dataInProc43North;
//Processor 43 control and data signals
wire wrProc43North;
wire fullProc43North;
wire [31:0] dataOutProc43North;
//Processor 43 control and data signals
wire rdProc43South;
wire emptyProc43South;
wire [31:0] dataInProc43South;
//Processor 43 control and data signals
wire wrProc43South;
wire fullProc43South;
wire [31:0] dataOutProc43South;
//Processor 43 control and data signals
wire wrProc43East;
wire fullProc43East;
wire [31:0] dataOutProc43East;
//Processor 43 control and data signals
wire rdProc43West;
wire emptyProc43West;
wire [31:0] dataInProc43West;
//Processor 43 control and data signals
wire wrProc43West;
wire fullProc43West;
wire [31:0] dataOutProc43West;
//Processor 44 control and data signals
wire wrProc44East;
wire fullProc44East;
wire [31:0] dataOutProc44East;
//Processor 44 control and data signals
wire rdProc44West;
wire emptyProc44West;
wire [31:0] dataInProc44West;
//Processor 45 control and data signals
wire wrProc45North;
wire fullProc45North;
wire [31:0] dataOutProc45North;
//Processor 45 control and data signals
wire wrProc45South;
wire fullProc45South;
wire [31:0] dataOutProc45South;
//Processor 45 control and data signals
wire rdProc45East;
wire emptyProc45East;
wire [31:0] dataInProc45East;
//Processor 45 control and data signals
wire rdProc45West;
wire emptyProc45West;
wire [31:0] dataInProc45West;
//Processor 46 control and data signals
wire rdProc46North;
wire emptyProc46North;
wire [31:0] dataInProc46North;
//Processor 46 control and data signals
wire wrProc46South;
wire fullProc46South;
wire [31:0] dataOutProc46South;
//Processor 46 control and data signals
wire rdProc46East;
wire emptyProc46East;
wire [31:0] dataInProc46East;
//Processor 46 control and data signals
wire wrProc46West;
wire fullProc46West;
wire [31:0] dataOutProc46West;
//Processor 47 control and data signals
wire rdProc47North;
wire emptyProc47North;
wire [31:0] dataInProc47North;
//Processor 47 control and data signals
wire wrProc47South;
wire fullProc47South;
wire [31:0] dataOutProc47South;
//Processor 47 control and data signals
wire wrProc47West;
wire fullProc47West;
wire [31:0] dataOutProc47West;
//Processor 48 control and data signals
wire rdProc48North;
wire emptyProc48North;
wire [31:0] dataInProc48North;
//Processor 48 control and data signals
wire wrProc48North;
wire fullProc48North;
wire [31:0] dataOutProc48North;
//Processor 48 control and data signals
wire rdProc48South;
wire emptyProc48South;
wire [31:0] dataInProc48South;
//Processor 48 control and data signals
wire wrProc48South;
wire fullProc48South;
wire [31:0] dataOutProc48South;
//Processor 49 control and data signals
wire wrProc49North;
wire fullProc49North;
wire [31:0] dataOutProc49North;
//Processor 49 control and data signals
wire rdProc49South;
wire emptyProc49South;
wire [31:0] dataInProc49South;
//Processor 50 control and data signals
wire rdProc50North;
wire emptyProc50North;
wire [31:0] dataInProc50North;
//Processor 50 control and data signals
wire wrProc50North;
wire fullProc50North;
wire [31:0] dataOutProc50North;
//Processor 50 control and data signals
wire rdProc50East;
wire emptyProc50East;
wire [31:0] dataInProc50East;
//Processor 50 control and data signals
wire wrProc50East;
wire fullProc50East;
wire [31:0] dataOutProc50East;
//Processor 51 control and data signals
wire rdProc51East;
wire emptyProc51East;
wire [31:0] dataInProc51East;
//Processor 51 control and data signals
wire wrProc51East;
wire fullProc51East;
wire [31:0] dataOutProc51East;
//Processor 51 control and data signals
wire rdProc51West;
wire emptyProc51West;
wire [31:0] dataInProc51West;
//Processor 51 control and data signals
wire wrProc51West;
wire fullProc51West;
wire [31:0] dataOutProc51West;
//Processor 52 control and data signals
wire wrProc52North;
wire fullProc52North;
wire [31:0] dataOutProc52North;
//Processor 52 control and data signals
wire rdProc52South;
wire emptyProc52South;
wire [31:0] dataInProc52South;
//Processor 52 control and data signals
wire wrProc52South;
wire fullProc52South;
wire [31:0] dataOutProc52South;
//Processor 52 control and data signals
wire rdProc52East;
wire emptyProc52East;
wire [31:0] dataInProc52East;
//Processor 52 control and data signals
wire wrProc52East;
wire fullProc52East;
wire [31:0] dataOutProc52East;
//Processor 52 control and data signals
wire rdProc52West;
wire emptyProc52West;
wire [31:0] dataInProc52West;
//Processor 52 control and data signals
wire wrProc52West;
wire fullProc52West;
wire [31:0] dataOutProc52West;
//Processor 53 control and data signals
wire rdProc53North;
wire emptyProc53North;
wire [31:0] dataInProc53North;
//Processor 53 control and data signals
wire wrProc53North;
wire fullProc53North;
wire [31:0] dataOutProc53North;
//Processor 53 control and data signals
wire rdProc53South;
wire emptyProc53South;
wire [31:0] dataInProc53South;
//Processor 53 control and data signals
wire wrProc53South;
wire fullProc53South;
wire [31:0] dataOutProc53South;
//Processor 53 control and data signals
wire rdProc53East;
wire emptyProc53East;
wire [31:0] dataInProc53East;
//Processor 53 control and data signals
wire rdProc53West;
wire emptyProc53West;
wire [31:0] dataInProc53West;
//Processor 53 control and data signals
wire wrProc53West;
wire fullProc53West;
wire [31:0] dataOutProc53West;
//Processor 54 control and data signals
wire rdProc54East;
wire emptyProc54East;
wire [31:0] dataInProc54East;
//Processor 54 control and data signals
wire wrProc54West;
wire fullProc54West;
wire [31:0] dataOutProc54West;
//Processor 55 control and data signals
wire rdProc55North;
wire emptyProc55North;
wire [31:0] dataInProc55North;
//Processor 55 control and data signals
wire rdProc55East;
wire emptyProc55East;
wire [31:0] dataInProc55East;
//Processor 55 control and data signals
wire wrProc55West;
wire fullProc55West;
wire [31:0] dataOutProc55West;
//Processor 56 control and data signals
wire rdProc56North;
wire emptyProc56North;
wire [31:0] dataInProc56North;
//Processor 56 control and data signals
wire rdProc56East;
wire emptyProc56East;
wire [31:0] dataInProc56East;
//Processor 56 control and data signals
wire wrProc56East;
wire fullProc56East;
wire [31:0] dataOutProc56East;
//Processor 56 control and data signals
wire wrProc56West;
wire fullProc56West;
wire [31:0] dataOutProc56West;
//Processor 57 control and data signals
wire rdProc57North;
wire emptyProc57North;
wire [31:0] dataInProc57North;
//Processor 57 control and data signals
wire wrProc57South;
wire fullProc57South;
wire [31:0] dataOutProc57South;
//Processor 57 control and data signals
wire rdProc57West;
wire emptyProc57West;
wire [31:0] dataInProc57West;
//Processor 57 control and data signals
wire wrProc57West;
wire fullProc57West;
wire [31:0] dataOutProc57West;
//Processor 58 control and data signals
wire rdProc58North;
wire emptyProc58North;
wire [31:0] dataInProc58North;
//Processor 58 control and data signals
wire wrProc58North;
wire fullProc58North;
wire [31:0] dataOutProc58North;
//Processor 58 control and data signals
wire wrProc58South;
wire fullProc58South;
wire [31:0] dataOutProc58South;
//Processor 58 control and data signals
wire rdProc58East;
wire emptyProc58East;
wire [31:0] dataInProc58East;
//Processor 59 control and data signals
wire wrProc59North;
wire fullProc59North;
wire [31:0] dataOutProc59North;
//Processor 59 control and data signals
wire rdProc59South;
wire emptyProc59South;
wire [31:0] dataInProc59South;
//Processor 59 control and data signals
wire wrProc59West;
wire fullProc59West;
wire [31:0] dataOutProc59West;
//Processor 60 control and data signals
wire wrProc60South;
wire fullProc60South;
wire [31:0] dataOutProc60South;
//Processor 60 control and data signals
wire rdProc60East;
wire emptyProc60East;
wire [31:0] dataInProc60East;
//Processor 61 control and data signals
wire rdProc61South;
wire emptyProc61South;
wire [31:0] dataInProc61South;
//Processor 61 control and data signals
wire wrProc61East;
wire fullProc61East;
wire [31:0] dataOutProc61East;
//Processor 61 control and data signals
wire wrProc61West;
wire fullProc61West;
wire [31:0] dataOutProc61West;
//Processor 62 control and data signals
wire rdProc62North;
wire emptyProc62North;
wire [31:0] dataInProc62North;
//Processor 62 control and data signals
wire wrProc62North;
wire fullProc62North;
wire [31:0] dataOutProc62North;
//Processor 62 control and data signals
wire rdProc62South;
wire emptyProc62South;
wire [31:0] dataInProc62South;
//Processor 62 control and data signals
wire wrProc62South;
wire fullProc62South;
wire [31:0] dataOutProc62South;
//Processor 62 control and data signals
wire wrProc62East;
wire fullProc62East;
wire [31:0] dataOutProc62East;
//Processor 62 control and data signals
wire rdProc62West;
wire emptyProc62West;
wire [31:0] dataInProc62West;
//Processor 63 control and data signals
wire rdProc63North;
wire emptyProc63North;
wire [31:0] dataInProc63North;
//Processor 63 control and data signals
wire wrProc63North;
wire fullProc63North;
wire [31:0] dataOutProc63North;
//Processor 63 control and data signals
wire rdProc63South;
wire emptyProc63South;
wire [31:0] dataInProc63South;
//Processor 63 control and data signals
wire wrProc63South;
wire fullProc63South;
wire [31:0] dataOutProc63South;
//Processor 63 control and data signals
wire wrProc63East;
wire fullProc63East;
wire [31:0] dataOutProc63East;
//Processor 63 control and data signals
wire rdProc63West;
wire emptyProc63West;
wire [31:0] dataInProc63West;
//Processor 64 control and data signals
wire wrProc64South;
wire fullProc64South;
wire [31:0] dataOutProc64South;
//Processor 64 control and data signals
wire rdProc64East;
wire emptyProc64East;
wire [31:0] dataInProc64East;
//Processor 64 control and data signals
wire wrProc64East;
wire fullProc64East;
wire [31:0] dataOutProc64East;
//Processor 64 control and data signals
wire rdProc64West;
wire emptyProc64West;
wire [31:0] dataInProc64West;
//Processor 65 control and data signals
wire rdProc65West;
wire emptyProc65West;
wire [31:0] dataInProc65West;
//Processor 65 control and data signals
wire wrProc65West;
wire fullProc65West;
wire [31:0] dataOutProc65West;
//Processor 66 control and data signals
wire rdProc66South;
wire emptyProc66South;
wire [31:0] dataInProc66South;
//Processor 66 control and data signals
wire wrProc66East;
wire fullProc66East;
wire [31:0] dataOutProc66East;
//Processor 67 control and data signals
wire rdProc67North;
wire emptyProc67North;
wire [31:0] dataInProc67North;
//Processor 67 control and data signals
wire wrProc67South;
wire fullProc67South;
wire [31:0] dataOutProc67South;
//Processor 67 control and data signals
wire wrProc67East;
wire fullProc67East;
wire [31:0] dataOutProc67East;
//Processor 67 control and data signals
wire rdProc67West;
wire emptyProc67West;
wire [31:0] dataInProc67West;
//Processor 68 control and data signals
wire rdProc68North;
wire emptyProc68North;
wire [31:0] dataInProc68North;
//Processor 68 control and data signals
wire wrProc68South;
wire fullProc68South;
wire [31:0] dataOutProc68South;
//Processor 68 control and data signals
wire wrProc68East;
wire fullProc68East;
wire [31:0] dataOutProc68East;
//Processor 68 control and data signals
wire rdProc68West;
wire emptyProc68West;
wire [31:0] dataInProc68West;
//Processor 69 control and data signals
wire wrProc69North;
wire fullProc69North;
wire [31:0] dataOutProc69North;
//Processor 69 control and data signals
wire rdProc69South;
wire emptyProc69South;
wire [31:0] dataInProc69South;
//Processor 69 control and data signals
wire rdProc69West;
wire emptyProc69West;
wire [31:0] dataInProc69West;
//Processor 70 control and data signals
wire rdProc70North;
wire emptyProc70North;
wire [31:0] dataInProc70North;
//Processor 70 control and data signals
wire wrProc70South;
wire fullProc70South;
wire [31:0] dataOutProc70South;
//Processor 71 control and data signals
wire wrProc71North;
wire fullProc71North;
wire [31:0] dataOutProc71North;
//Processor 71 control and data signals
wire rdProc71South;
wire emptyProc71South;
wire [31:0] dataInProc71South;
//Processor 72 control and data signals
wire rdProc72North;
wire emptyProc72North;
wire [31:0] dataInProc72North;
//Processor 72 control and data signals
wire wrProc72North;
wire fullProc72North;
wire [31:0] dataOutProc72North;
//Processor 72 control and data signals
wire rdProc72East;
wire emptyProc72East;
wire [31:0] dataInProc72East;
//Processor 72 control and data signals
wire wrProc72East;
wire fullProc72East;
wire [31:0] dataOutProc72East;
//Processor 73 control and data signals
wire rdProc73North;
wire emptyProc73North;
wire [31:0] dataInProc73North;
//Processor 73 control and data signals
wire wrProc73North;
wire fullProc73North;
wire [31:0] dataOutProc73North;
//Processor 73 control and data signals
wire wrProc73South;
wire fullProc73South;
wire [31:0] dataOutProc73South;
//Processor 73 control and data signals
wire rdProc73East;
wire emptyProc73East;
wire [31:0] dataInProc73East;
//Processor 73 control and data signals
wire rdProc73West;
wire emptyProc73West;
wire [31:0] dataInProc73West;
//Processor 73 control and data signals
wire wrProc73West;
wire fullProc73West;
wire [31:0] dataOutProc73West;
//Processor 74 control and data signals
wire rdProc74North;
wire emptyProc74North;
wire [31:0] dataInProc74North;
//Processor 74 control and data signals
wire rdProc74South;
wire emptyProc74South;
wire [31:0] dataInProc74South;
//Processor 74 control and data signals
wire wrProc74South;
wire fullProc74South;
wire [31:0] dataOutProc74South;
//Processor 74 control and data signals
wire rdProc74East;
wire emptyProc74East;
wire [31:0] dataInProc74East;
//Processor 74 control and data signals
wire wrProc74East;
wire fullProc74East;
wire [31:0] dataOutProc74East;
//Processor 74 control and data signals
wire wrProc74West;
wire fullProc74West;
wire [31:0] dataOutProc74West;
//Processor 75 control and data signals
wire rdProc75East;
wire emptyProc75East;
wire [31:0] dataInProc75East;
//Processor 75 control and data signals
wire wrProc75East;
wire fullProc75East;
wire [31:0] dataOutProc75East;
//Processor 75 control and data signals
wire rdProc75West;
wire emptyProc75West;
wire [31:0] dataInProc75West;
//Processor 75 control and data signals
wire wrProc75West;
wire fullProc75West;
wire [31:0] dataOutProc75West;
//Processor 76 control and data signals
wire wrProc76North;
wire fullProc76North;
wire [31:0] dataOutProc76North;
//Processor 76 control and data signals
wire rdProc76South;
wire emptyProc76South;
wire [31:0] dataInProc76South;
//Processor 76 control and data signals
wire rdProc76West;
wire emptyProc76West;
wire [31:0] dataInProc76West;
//Processor 76 control and data signals
wire wrProc76West;
wire fullProc76West;
wire [31:0] dataOutProc76West;
//Processor 77 control and data signals
wire rdProc77North;
wire emptyProc77North;
wire [31:0] dataInProc77North;
//Processor 77 control and data signals
wire wrProc77South;
wire fullProc77South;
wire [31:0] dataOutProc77South;
//Processor 77 control and data signals
wire rdProc77East;
wire emptyProc77East;
wire [31:0] dataInProc77East;
//Processor 78 control and data signals
wire rdProc78North;
wire emptyProc78North;
wire [31:0] dataInProc78North;
//Processor 78 control and data signals
wire wrProc78West;
wire fullProc78West;
wire [31:0] dataOutProc78West;
//Processor 79 control and data signals
wire wrProc79North;
wire fullProc79North;
wire [31:0] dataOutProc79North;
//Processor 79 control and data signals
wire rdProc79South;
wire emptyProc79South;
wire [31:0] dataInProc79South;
//Processor 80 control and data signals
wire rdProc80North;
wire emptyProc80North;
wire [31:0] dataInProc80North;
//Processor 80 control and data signals
wire wrProc80East;
wire fullProc80East;
wire [31:0] dataOutProc80East;
//Processor 81 control and data signals
wire wrProc81North;
wire fullProc81North;
wire [31:0] dataOutProc81North;
//Processor 81 control and data signals
wire rdProc81East;
wire emptyProc81East;
wire [31:0] dataInProc81East;
//Processor 81 control and data signals
wire wrProc81East;
wire fullProc81East;
wire [31:0] dataOutProc81East;
//Processor 81 control and data signals
wire rdProc81West;
wire emptyProc81West;
wire [31:0] dataInProc81West;
//Processor 82 control and data signals
wire rdProc82East;
wire emptyProc82East;
wire [31:0] dataInProc82East;
//Processor 82 control and data signals
wire wrProc82East;
wire fullProc82East;
wire [31:0] dataOutProc82East;
//Processor 82 control and data signals
wire rdProc82West;
wire emptyProc82West;
wire [31:0] dataInProc82West;
//Processor 82 control and data signals
wire wrProc82West;
wire fullProc82West;
wire [31:0] dataOutProc82West;
//Processor 83 control and data signals
wire rdProc83North;
wire emptyProc83North;
wire [31:0] dataInProc83North;
//Processor 83 control and data signals
wire rdProc83East;
wire emptyProc83East;
wire [31:0] dataInProc83East;
//Processor 83 control and data signals
wire wrProc83East;
wire fullProc83East;
wire [31:0] dataOutProc83East;
//Processor 83 control and data signals
wire rdProc83West;
wire emptyProc83West;
wire [31:0] dataInProc83West;
//Processor 83 control and data signals
wire wrProc83West;
wire fullProc83West;
wire [31:0] dataOutProc83West;
//Processor 84 control and data signals
wire rdProc84North;
wire emptyProc84North;
wire [31:0] dataInProc84North;
//Processor 84 control and data signals
wire wrProc84North;
wire fullProc84North;
wire [31:0] dataOutProc84North;
//Processor 84 control and data signals
wire rdProc84East;
wire emptyProc84East;
wire [31:0] dataInProc84East;
//Processor 84 control and data signals
wire wrProc84East;
wire fullProc84East;
wire [31:0] dataOutProc84East;
//Processor 84 control and data signals
wire rdProc84West;
wire emptyProc84West;
wire [31:0] dataInProc84West;
//Processor 84 control and data signals
wire wrProc84West;
wire fullProc84West;
wire [31:0] dataOutProc84West;
//Processor 85 control and data signals
wire rdProc85West;
wire emptyProc85West;
wire [31:0] dataInProc85West;
//Processor 85 control and data signals
wire wrProc85West;
wire fullProc85West;
wire [31:0] dataOutProc85West;
//Processor 86 control and data signals
wire wrProc86North;
wire fullProc86North;
wire [31:0] dataOutProc86North;
//Processor 86 control and data signals
wire rdProc86East;
wire emptyProc86East;
wire [31:0] dataInProc86East;
//Processor 87 control and data signals
wire rdProc87North;
wire emptyProc87North;
wire [31:0] dataInProc87North;
//Processor 87 control and data signals
wire wrProc87East;
wire fullProc87East;
wire [31:0] dataOutProc87East;
//Processor 87 control and data signals
wire wrProc87West;
wire fullProc87West;
wire [31:0] dataOutProc87West;
//Processor 88 control and data signals
wire wrProc88East;
wire fullProc88East;
wire [31:0] dataOutProc88East;
//Processor 88 control and data signals
wire rdProc88West;
wire emptyProc88West;
wire [31:0] dataInProc88West;
//Processor 89 control and data signals
wire wrProc89North;
wire fullProc89North;
wire [31:0] dataOutProc89North;
//Processor 89 control and data signals
wire rdProc89West;
wire emptyProc89West;
wire [31:0] dataInProc89West;
//PROCESSOR 0
system proc0(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe0),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe0),
.wrSouth(wrProc0South),
.fullSouth(fullProc0South),
.dataOutSouth(dataOutProc0South),
.wrEast(wrProc0East),
.fullEast(fullProc0East),
.dataOutEast(dataOutProc0East));
//PROCESSOR 1
system proc1(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe1),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe1),
.wrSouth(wrProc1South),
.fullSouth(fullProc1South),
.dataOutSouth(dataOutProc1South),
.rdWest(rdProc1West),
.emptyWest(emptyProc1West),
.dataInWest(dataInProc1West));
//PROCESSOR 2
system proc2(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe2),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe2));
//PROCESSOR 3
system proc3(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe3),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe3));
//PROCESSOR 4
system proc4(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe4),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe4),
.rdSouth(rdProc4South),
.emptySouth(emptyProc4South),
.dataInSouth(dataInProc4South),
.rdEast(rdProc4East),
.emptyEast(emptyProc4East),
.dataInEast(dataInProc4East),
.wrEast(wrProc4East),
.fullEast(fullProc4East),
.dataOutEast(dataOutProc4East));
//PROCESSOR 5
system proc5(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe5),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe5),
.rdEast(rdProc5East),
.emptyEast(emptyProc5East),
.dataInEast(dataInProc5East),
.rdWest(rdProc5West),
.emptyWest(emptyProc5West),
.dataInWest(dataInProc5West),
.wrWest(wrProc5West),
.fullWest(fullProc5West),
.dataOutWest(dataOutProc5West),
.reg_file_b_readdataout(reg_file_b_readdataout));
//PROCESSOR 6
system proc6(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe6),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe6),
.rdSouth(rdProc6South),
.emptySouth(emptyProc6South),
.dataInSouth(dataInProc6South),
.wrSouth(wrProc6South),
.fullSouth(fullProc6South),
.dataOutSouth(dataOutProc6South),
.rdEast(rdProc6East),
.emptyEast(emptyProc6East),
.dataInEast(dataInProc6East),
.wrWest(wrProc6West),
.fullWest(fullProc6West),
.dataOutWest(dataOutProc6West));
//PROCESSOR 7
system proc7(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe7),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe7),
.rdSouth(rdProc7South),
.emptySouth(emptyProc7South),
.dataInSouth(dataInProc7South),
.wrWest(wrProc7West),
.fullWest(fullProc7West),
.dataOutWest(dataOutProc7West));
//PROCESSOR 8
system proc8(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe8),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe8),
.rdSouth(rdProc8South),
.emptySouth(emptyProc8South),
.dataInSouth(dataInProc8South),
.wrSouth(wrProc8South),
.fullSouth(fullProc8South),
.dataOutSouth(dataOutProc8South),
.rdEast(rdProc8East),
.emptyEast(emptyProc8East),
.dataInEast(dataInProc8East));
//PROCESSOR 9
system proc9(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe9),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe9),
.rdSouth(rdProc9South),
.emptySouth(emptyProc9South),
.dataInSouth(dataInProc9South),
.wrWest(wrProc9West),
.fullWest(fullProc9West),
.dataOutWest(dataOutProc9West));
//PROCESSOR 10
system proc10(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe10),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe10),
.rdNorth(rdProc10North),
.emptyNorth(emptyProc10North),
.dataInNorth(dataInProc10North),
.wrEast(wrProc10East),
.fullEast(fullProc10East),
.dataOutEast(dataOutProc10East));
//PROCESSOR 11
system proc11(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe11),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe11),
.rdNorth(rdProc11North),
.emptyNorth(emptyProc11North),
.dataInNorth(dataInProc11North),
.wrSouth(wrProc11South),
.fullSouth(fullProc11South),
.dataOutSouth(dataOutProc11South),
.rdWest(rdProc11West),
.emptyWest(emptyProc11West),
.dataInWest(dataInProc11West));
//PROCESSOR 12
system proc12(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe12),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe12),
.rdSouth(rdProc12South),
.emptySouth(emptyProc12South),
.dataInSouth(dataInProc12South),
.wrEast(wrProc12East),
.fullEast(fullProc12East),
.dataOutEast(dataOutProc12East));
//PROCESSOR 13
system proc13(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe13),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe13),
.rdSouth(rdProc13South),
.emptySouth(emptyProc13South),
.dataInSouth(dataInProc13South),
.wrEast(wrProc13East),
.fullEast(fullProc13East),
.dataOutEast(dataOutProc13East),
.rdWest(rdProc13West),
.emptyWest(emptyProc13West),
.dataInWest(dataInProc13West));
//PROCESSOR 14
system proc14(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe14),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe14),
.wrNorth(wrProc14North),
.fullNorth(fullProc14North),
.dataOutNorth(dataOutProc14North),
.rdSouth(rdProc14South),
.emptySouth(emptyProc14South),
.dataInSouth(dataInProc14South),
.wrSouth(wrProc14South),
.fullSouth(fullProc14South),
.dataOutSouth(dataOutProc14South),
.wrEast(wrProc14East),
.fullEast(fullProc14East),
.dataOutEast(dataOutProc14East),
.rdWest(rdProc14West),
.emptyWest(emptyProc14West),
.dataInWest(dataInProc14West));
//PROCESSOR 15
system proc15(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe15),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe15),
.wrEast(wrProc15East),
.fullEast(fullProc15East),
.dataOutEast(dataOutProc15East),
.rdWest(rdProc15West),
.emptyWest(emptyProc15West),
.dataInWest(dataInProc15West));
//PROCESSOR 16
system proc16(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe16),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe16),
.rdNorth(rdProc16North),
.emptyNorth(emptyProc16North),
.dataInNorth(dataInProc16North),
.wrNorth(wrProc16North),
.fullNorth(fullProc16North),
.dataOutNorth(dataOutProc16North),
.wrSouth(wrProc16South),
.fullSouth(fullProc16South),
.dataOutSouth(dataOutProc16South),
.rdWest(rdProc16West),
.emptyWest(emptyProc16West),
.dataInWest(dataInProc16West));
//PROCESSOR 17
system proc17(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe17),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe17),
.wrNorth(wrProc17North),
.fullNorth(fullProc17North),
.dataOutNorth(dataOutProc17North),
.rdSouth(rdProc17South),
.emptySouth(emptyProc17South),
.dataInSouth(dataInProc17South));
//PROCESSOR 18
system proc18(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe18),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe18),
.rdNorth(rdProc18North),
.emptyNorth(emptyProc18North),
.dataInNorth(dataInProc18North),
.wrNorth(wrProc18North),
.fullNorth(fullProc18North),
.dataOutNorth(dataOutProc18North),
.wrSouth(wrProc18South),
.fullSouth(fullProc18South),
.dataOutSouth(dataOutProc18South));
//PROCESSOR 19
system proc19(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe19),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe19),
.wrNorth(wrProc19North),
.fullNorth(fullProc19North),
.dataOutNorth(dataOutProc19North),
.rdSouth(rdProc19South),
.emptySouth(emptyProc19South),
.dataInSouth(dataInProc19South),
.wrSouth(wrProc19South),
.fullSouth(fullProc19South),
.dataOutSouth(dataOutProc19South));
//PROCESSOR 20
system proc20(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe20),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe20),
.rdSouth(rdProc20South),
.emptySouth(emptyProc20South),
.dataInSouth(dataInProc20South),
.wrEast(wrProc20East),
.fullEast(fullProc20East),
.dataOutEast(dataOutProc20East));
//PROCESSOR 21
system proc21(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe21),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe21),
.rdNorth(rdProc21North),
.emptyNorth(emptyProc21North),
.dataInNorth(dataInProc21North),
.rdSouth(rdProc21South),
.emptySouth(emptyProc21South),
.dataInSouth(dataInProc21South),
.wrSouth(wrProc21South),
.fullSouth(fullProc21South),
.dataOutSouth(dataOutProc21South),
.wrEast(wrProc21East),
.fullEast(fullProc21East),
.dataOutEast(dataOutProc21East),
.rdWest(rdProc21West),
.emptyWest(emptyProc21West),
.dataInWest(dataInProc21West));
//PROCESSOR 22
system proc22(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe22),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe22),
.wrNorth(wrProc22North),
.fullNorth(fullProc22North),
.dataOutNorth(dataOutProc22North),
.rdSouth(rdProc22South),
.emptySouth(emptyProc22South),
.dataInSouth(dataInProc22South),
.wrSouth(wrProc22South),
.fullSouth(fullProc22South),
.dataOutSouth(dataOutProc22South),
.rdEast(rdProc22East),
.emptyEast(emptyProc22East),
.dataInEast(dataInProc22East),
.wrEast(wrProc22East),
.fullEast(fullProc22East),
.dataOutEast(dataOutProc22East),
.rdWest(rdProc22West),
.emptyWest(emptyProc22West),
.dataInWest(dataInProc22West));
//PROCESSOR 23
system proc23(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe23),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe23),
.wrNorth(wrProc23North),
.fullNorth(fullProc23North),
.dataOutNorth(dataOutProc23North),
.rdSouth(rdProc23South),
.emptySouth(emptyProc23South),
.dataInSouth(dataInProc23South),
.rdEast(rdProc23East),
.emptyEast(emptyProc23East),
.dataInEast(dataInProc23East),
.wrEast(wrProc23East),
.fullEast(fullProc23East),
.dataOutEast(dataOutProc23East),
.rdWest(rdProc23West),
.emptyWest(emptyProc23West),
.dataInWest(dataInProc23West),
.wrWest(wrProc23West),
.fullWest(fullProc23West),
.dataOutWest(dataOutProc23West));
//PROCESSOR 24
system proc24(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe24),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe24),
.rdNorth(rdProc24North),
.emptyNorth(emptyProc24North),
.dataInNorth(dataInProc24North),
.wrNorth(wrProc24North),
.fullNorth(fullProc24North),
.dataOutNorth(dataOutProc24North),
.wrSouth(wrProc24South),
.fullSouth(fullProc24South),
.dataOutSouth(dataOutProc24South),
.rdEast(rdProc24East),
.emptyEast(emptyProc24East),
.dataInEast(dataInProc24East),
.wrEast(wrProc24East),
.fullEast(fullProc24East),
.dataOutEast(dataOutProc24East),
.rdWest(rdProc24West),
.emptyWest(emptyProc24West),
.dataInWest(dataInProc24West),
.wrWest(wrProc24West),
.fullWest(fullProc24West),
.dataOutWest(dataOutProc24West));
//PROCESSOR 25
system proc25(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe25),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe25),
.rdSouth(rdProc25South),
.emptySouth(emptyProc25South),
.dataInSouth(dataInProc25South),
.wrSouth(wrProc25South),
.fullSouth(fullProc25South),
.dataOutSouth(dataOutProc25South),
.rdEast(rdProc25East),
.emptyEast(emptyProc25East),
.dataInEast(dataInProc25East),
.wrEast(wrProc25East),
.fullEast(fullProc25East),
.dataOutEast(dataOutProc25East),
.rdWest(rdProc25West),
.emptyWest(emptyProc25West),
.dataInWest(dataInProc25West),
.wrWest(wrProc25West),
.fullWest(fullProc25West),
.dataOutWest(dataOutProc25West));
//PROCESSOR 26
system proc26(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe26),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe26),
.rdNorth(rdProc26North),
.emptyNorth(emptyProc26North),
.dataInNorth(dataInProc26North),
.wrSouth(wrProc26South),
.fullSouth(fullProc26South),
.dataOutSouth(dataOutProc26South),
.wrEast(wrProc26East),
.fullEast(fullProc26East),
.dataOutEast(dataOutProc26East),
.rdWest(rdProc26West),
.emptyWest(emptyProc26West),
.dataInWest(dataInProc26West),
.wrWest(wrProc26West),
.fullWest(fullProc26West),
.dataOutWest(dataOutProc26West));
//PROCESSOR 27
system proc27(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe27),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe27),
.wrNorth(wrProc27North),
.fullNorth(fullProc27North),
.dataOutNorth(dataOutProc27North),
.wrSouth(wrProc27South),
.fullSouth(fullProc27South),
.dataOutSouth(dataOutProc27South),
.rdEast(rdProc27East),
.emptyEast(emptyProc27East),
.dataInEast(dataInProc27East),
.wrEast(wrProc27East),
.fullEast(fullProc27East),
.dataOutEast(dataOutProc27East),
.rdWest(rdProc27West),
.emptyWest(emptyProc27West),
.dataInWest(dataInProc27West));
//PROCESSOR 28
system proc28(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe28),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe28),
.rdNorth(rdProc28North),
.emptyNorth(emptyProc28North),
.dataInNorth(dataInProc28North),
.wrSouth(wrProc28South),
.fullSouth(fullProc28South),
.dataOutSouth(dataOutProc28South),
.rdEast(rdProc28East),
.emptyEast(emptyProc28East),
.dataInEast(dataInProc28East),
.rdWest(rdProc28West),
.emptyWest(emptyProc28West),
.dataInWest(dataInProc28West),
.wrWest(wrProc28West),
.fullWest(fullProc28West),
.dataOutWest(dataOutProc28West));
//PROCESSOR 29
system proc29(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe29),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe29),
.rdNorth(rdProc29North),
.emptyNorth(emptyProc29North),
.dataInNorth(dataInProc29North),
.wrNorth(wrProc29North),
.fullNorth(fullProc29North),
.dataOutNorth(dataOutProc29North),
.rdSouth(rdProc29South),
.emptySouth(emptyProc29South),
.dataInSouth(dataInProc29South),
.wrWest(wrProc29West),
.fullWest(fullProc29West),
.dataOutWest(dataOutProc29West));
//PROCESSOR 30
system proc30(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe30),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe30),
.wrNorth(wrProc30North),
.fullNorth(fullProc30North),
.dataOutNorth(dataOutProc30North),
.rdSouth(rdProc30South),
.emptySouth(emptyProc30South),
.dataInSouth(dataInProc30South));
//PROCESSOR 31
system proc31(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe31),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe31),
.rdNorth(rdProc31North),
.emptyNorth(emptyProc31North),
.dataInNorth(dataInProc31North),
.wrNorth(wrProc31North),
.fullNorth(fullProc31North),
.dataOutNorth(dataOutProc31North));
//PROCESSOR 32
system proc32(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe32),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe32),
.rdNorth(rdProc32North),
.emptyNorth(emptyProc32North),
.dataInNorth(dataInProc32North),
.wrNorth(wrProc32North),
.fullNorth(fullProc32North),
.dataOutNorth(dataOutProc32North));
//PROCESSOR 33
system proc33(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe33),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe33),
.wrNorth(wrProc33North),
.fullNorth(fullProc33North),
.dataOutNorth(dataOutProc33North),
.rdSouth(rdProc33South),
.emptySouth(emptyProc33South),
.dataInSouth(dataInProc33South),
.wrSouth(wrProc33South),
.fullSouth(fullProc33South),
.dataOutSouth(dataOutProc33South),
.rdEast(rdProc33East),
.emptyEast(emptyProc33East),
.dataInEast(dataInProc33East));
//PROCESSOR 34
system proc34(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe34),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe34),
.rdNorth(rdProc34North),
.emptyNorth(emptyProc34North),
.dataInNorth(dataInProc34North),
.wrWest(wrProc34West),
.fullWest(fullProc34West),
.dataOutWest(dataOutProc34West));
//PROCESSOR 35
system proc35(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe35),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe35),
.rdNorth(rdProc35North),
.emptyNorth(emptyProc35North),
.dataInNorth(dataInProc35North),
.wrNorth(wrProc35North),
.fullNorth(fullProc35North),
.dataOutNorth(dataOutProc35North),
.rdSouth(rdProc35South),
.emptySouth(emptyProc35South),
.dataInSouth(dataInProc35South),
.wrEast(wrProc35East),
.fullEast(fullProc35East),
.dataOutEast(dataOutProc35East));
//PROCESSOR 36
system proc36(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe36),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe36),
.rdNorth(rdProc36North),
.emptyNorth(emptyProc36North),
.dataInNorth(dataInProc36North),
.wrSouth(wrProc36South),
.fullSouth(fullProc36South),
.dataOutSouth(dataOutProc36South),
.wrEast(wrProc36East),
.fullEast(fullProc36East),
.dataOutEast(dataOutProc36East),
.rdWest(rdProc36West),
.emptyWest(emptyProc36West),
.dataInWest(dataInProc36West));
//PROCESSOR 37
system proc37(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe37),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe37),
.rdNorth(rdProc37North),
.emptyNorth(emptyProc37North),
.dataInNorth(dataInProc37North),
.wrSouth(wrProc37South),
.fullSouth(fullProc37South),
.dataOutSouth(dataOutProc37South),
.rdWest(rdProc37West),
.emptyWest(emptyProc37West),
.dataInWest(dataInProc37West));
//PROCESSOR 38
system proc38(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe38),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe38),
.rdNorth(rdProc38North),
.emptyNorth(emptyProc38North),
.dataInNorth(dataInProc38North),
.rdSouth(rdProc38South),
.emptySouth(emptyProc38South),
.dataInSouth(dataInProc38South),
.wrSouth(wrProc38South),
.fullSouth(fullProc38South),
.dataOutSouth(dataOutProc38South),
.wrEast(wrProc38East),
.fullEast(fullProc38East),
.dataOutEast(dataOutProc38East));
//PROCESSOR 39
system proc39(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe39),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe39),
.wrNorth(wrProc39North),
.fullNorth(fullProc39North),
.dataOutNorth(dataOutProc39North),
.rdSouth(rdProc39South),
.emptySouth(emptyProc39South),
.dataInSouth(dataInProc39South),
.rdWest(rdProc39West),
.emptyWest(emptyProc39West),
.dataInWest(dataInProc39West));
//PROCESSOR 40
system proc40(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe40),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe40),
.wrNorth(wrProc40North),
.fullNorth(fullProc40North),
.dataOutNorth(dataOutProc40North),
.rdSouth(rdProc40South),
.emptySouth(emptyProc40South),
.dataInSouth(dataInProc40South),
.wrSouth(wrProc40South),
.fullSouth(fullProc40South),
.dataOutSouth(dataOutProc40South),
.rdEast(rdProc40East),
.emptyEast(emptyProc40East),
.dataInEast(dataInProc40East));
//PROCESSOR 41
system proc41(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe41),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe41),
.rdEast(rdProc41East),
.emptyEast(emptyProc41East),
.dataInEast(dataInProc41East),
.wrWest(wrProc41West),
.fullWest(fullProc41West),
.dataOutWest(dataOutProc41West));
//PROCESSOR 42
system proc42(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe42),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe42),
.rdSouth(rdProc42South),
.emptySouth(emptyProc42South),
.dataInSouth(dataInProc42South),
.rdEast(rdProc42East),
.emptyEast(emptyProc42East),
.dataInEast(dataInProc42East),
.wrEast(wrProc42East),
.fullEast(fullProc42East),
.dataOutEast(dataOutProc42East),
.wrWest(wrProc42West),
.fullWest(fullProc42West),
.dataOutWest(dataOutProc42West));
//PROCESSOR 43
system proc43(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe43),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe43),
.rdNorth(rdProc43North),
.emptyNorth(emptyProc43North),
.dataInNorth(dataInProc43North),
.wrNorth(wrProc43North),
.fullNorth(fullProc43North),
.dataOutNorth(dataOutProc43North),
.rdSouth(rdProc43South),
.emptySouth(emptyProc43South),
.dataInSouth(dataInProc43South),
.wrSouth(wrProc43South),
.fullSouth(fullProc43South),
.dataOutSouth(dataOutProc43South),
.wrEast(wrProc43East),
.fullEast(fullProc43East),
.dataOutEast(dataOutProc43East),
.rdWest(rdProc43West),
.emptyWest(emptyProc43West),
.dataInWest(dataInProc43West),
.wrWest(wrProc43West),
.fullWest(fullProc43West),
.dataOutWest(dataOutProc43West));
//PROCESSOR 44
system proc44(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe44),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe44),
.wrEast(wrProc44East),
.fullEast(fullProc44East),
.dataOutEast(dataOutProc44East),
.rdWest(rdProc44West),
.emptyWest(emptyProc44West),
.dataInWest(dataInProc44West));
//PROCESSOR 45
system proc45(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe45),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe45),
.wrNorth(wrProc45North),
.fullNorth(fullProc45North),
.dataOutNorth(dataOutProc45North),
.wrSouth(wrProc45South),
.fullSouth(fullProc45South),
.dataOutSouth(dataOutProc45South),
.rdEast(rdProc45East),
.emptyEast(emptyProc45East),
.dataInEast(dataInProc45East),
.rdWest(rdProc45West),
.emptyWest(emptyProc45West),
.dataInWest(dataInProc45West));
//PROCESSOR 46
system proc46(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe46),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe46),
.rdNorth(rdProc46North),
.emptyNorth(emptyProc46North),
.dataInNorth(dataInProc46North),
.wrSouth(wrProc46South),
.fullSouth(fullProc46South),
.dataOutSouth(dataOutProc46South),
.rdEast(rdProc46East),
.emptyEast(emptyProc46East),
.dataInEast(dataInProc46East),
.wrWest(wrProc46West),
.fullWest(fullProc46West),
.dataOutWest(dataOutProc46West));
//PROCESSOR 47
system proc47(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe47),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe47),
.rdNorth(rdProc47North),
.emptyNorth(emptyProc47North),
.dataInNorth(dataInProc47North),
.wrSouth(wrProc47South),
.fullSouth(fullProc47South),
.dataOutSouth(dataOutProc47South),
.wrWest(wrProc47West),
.fullWest(fullProc47West),
.dataOutWest(dataOutProc47West));
//PROCESSOR 48
system proc48(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe48),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe48),
.rdNorth(rdProc48North),
.emptyNorth(emptyProc48North),
.dataInNorth(dataInProc48North),
.wrNorth(wrProc48North),
.fullNorth(fullProc48North),
.dataOutNorth(dataOutProc48North),
.rdSouth(rdProc48South),
.emptySouth(emptyProc48South),
.dataInSouth(dataInProc48South),
.wrSouth(wrProc48South),
.fullSouth(fullProc48South),
.dataOutSouth(dataOutProc48South));
//PROCESSOR 49
system proc49(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe49),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe49),
.wrNorth(wrProc49North),
.fullNorth(fullProc49North),
.dataOutNorth(dataOutProc49North),
.rdSouth(rdProc49South),
.emptySouth(emptyProc49South),
.dataInSouth(dataInProc49South));
//PROCESSOR 50
system proc50(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe50),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe50),
.rdNorth(rdProc50North),
.emptyNorth(emptyProc50North),
.dataInNorth(dataInProc50North),
.wrNorth(wrProc50North),
.fullNorth(fullProc50North),
.dataOutNorth(dataOutProc50North),
.rdEast(rdProc50East),
.emptyEast(emptyProc50East),
.dataInEast(dataInProc50East),
.wrEast(wrProc50East),
.fullEast(fullProc50East),
.dataOutEast(dataOutProc50East));
//PROCESSOR 51
system proc51(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe51),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe51),
.rdEast(rdProc51East),
.emptyEast(emptyProc51East),
.dataInEast(dataInProc51East),
.wrEast(wrProc51East),
.fullEast(fullProc51East),
.dataOutEast(dataOutProc51East),
.rdWest(rdProc51West),
.emptyWest(emptyProc51West),
.dataInWest(dataInProc51West),
.wrWest(wrProc51West),
.fullWest(fullProc51West),
.dataOutWest(dataOutProc51West));
//PROCESSOR 52
system proc52(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe52),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe52),
.wrNorth(wrProc52North),
.fullNorth(fullProc52North),
.dataOutNorth(dataOutProc52North),
.rdSouth(rdProc52South),
.emptySouth(emptyProc52South),
.dataInSouth(dataInProc52South),
.wrSouth(wrProc52South),
.fullSouth(fullProc52South),
.dataOutSouth(dataOutProc52South),
.rdEast(rdProc52East),
.emptyEast(emptyProc52East),
.dataInEast(dataInProc52East),
.wrEast(wrProc52East),
.fullEast(fullProc52East),
.dataOutEast(dataOutProc52East),
.rdWest(rdProc52West),
.emptyWest(emptyProc52West),
.dataInWest(dataInProc52West),
.wrWest(wrProc52West),
.fullWest(fullProc52West),
.dataOutWest(dataOutProc52West));
//PROCESSOR 53
system proc53(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe53),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe53),
.rdNorth(rdProc53North),
.emptyNorth(emptyProc53North),
.dataInNorth(dataInProc53North),
.wrNorth(wrProc53North),
.fullNorth(fullProc53North),
.dataOutNorth(dataOutProc53North),
.rdSouth(rdProc53South),
.emptySouth(emptyProc53South),
.dataInSouth(dataInProc53South),
.wrSouth(wrProc53South),
.fullSouth(fullProc53South),
.dataOutSouth(dataOutProc53South),
.rdEast(rdProc53East),
.emptyEast(emptyProc53East),
.dataInEast(dataInProc53East),
.rdWest(rdProc53West),
.emptyWest(emptyProc53West),
.dataInWest(dataInProc53West),
.wrWest(wrProc53West),
.fullWest(fullProc53West),
.dataOutWest(dataOutProc53West));
//PROCESSOR 54
system proc54(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe54),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe54),
.rdEast(rdProc54East),
.emptyEast(emptyProc54East),
.dataInEast(dataInProc54East),
.wrWest(wrProc54West),
.fullWest(fullProc54West),
.dataOutWest(dataOutProc54West));
//PROCESSOR 55
system proc55(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe55),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe55),
.rdNorth(rdProc55North),
.emptyNorth(emptyProc55North),
.dataInNorth(dataInProc55North),
.rdEast(rdProc55East),
.emptyEast(emptyProc55East),
.dataInEast(dataInProc55East),
.wrWest(wrProc55West),
.fullWest(fullProc55West),
.dataOutWest(dataOutProc55West));
//PROCESSOR 56
system proc56(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe56),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe56),
.rdNorth(rdProc56North),
.emptyNorth(emptyProc56North),
.dataInNorth(dataInProc56North),
.rdEast(rdProc56East),
.emptyEast(emptyProc56East),
.dataInEast(dataInProc56East),
.wrEast(wrProc56East),
.fullEast(fullProc56East),
.dataOutEast(dataOutProc56East),
.wrWest(wrProc56West),
.fullWest(fullProc56West),
.dataOutWest(dataOutProc56West));
//PROCESSOR 57
system proc57(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe57),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe57),
.rdNorth(rdProc57North),
.emptyNorth(emptyProc57North),
.dataInNorth(dataInProc57North),
.wrSouth(wrProc57South),
.fullSouth(fullProc57South),
.dataOutSouth(dataOutProc57South),
.rdWest(rdProc57West),
.emptyWest(emptyProc57West),
.dataInWest(dataInProc57West),
.wrWest(wrProc57West),
.fullWest(fullProc57West),
.dataOutWest(dataOutProc57West));
//PROCESSOR 58
system proc58(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe58),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe58),
.rdNorth(rdProc58North),
.emptyNorth(emptyProc58North),
.dataInNorth(dataInProc58North),
.wrNorth(wrProc58North),
.fullNorth(fullProc58North),
.dataOutNorth(dataOutProc58North),
.wrSouth(wrProc58South),
.fullSouth(fullProc58South),
.dataOutSouth(dataOutProc58South),
.rdEast(rdProc58East),
.emptyEast(emptyProc58East),
.dataInEast(dataInProc58East));
//PROCESSOR 59
system proc59(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe59),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe59),
.wrNorth(wrProc59North),
.fullNorth(fullProc59North),
.dataOutNorth(dataOutProc59North),
.rdSouth(rdProc59South),
.emptySouth(emptyProc59South),
.dataInSouth(dataInProc59South),
.wrWest(wrProc59West),
.fullWest(fullProc59West),
.dataOutWest(dataOutProc59West));
//PROCESSOR 60
system proc60(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe60),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe60),
.wrSouth(wrProc60South),
.fullSouth(fullProc60South),
.dataOutSouth(dataOutProc60South),
.rdEast(rdProc60East),
.emptyEast(emptyProc60East),
.dataInEast(dataInProc60East));
//PROCESSOR 61
system proc61(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe61),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe61),
.rdSouth(rdProc61South),
.emptySouth(emptyProc61South),
.dataInSouth(dataInProc61South),
.wrEast(wrProc61East),
.fullEast(fullProc61East),
.dataOutEast(dataOutProc61East),
.wrWest(wrProc61West),
.fullWest(fullProc61West),
.dataOutWest(dataOutProc61West));
//PROCESSOR 62
system proc62(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe62),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe62),
.rdNorth(rdProc62North),
.emptyNorth(emptyProc62North),
.dataInNorth(dataInProc62North),
.wrNorth(wrProc62North),
.fullNorth(fullProc62North),
.dataOutNorth(dataOutProc62North),
.rdSouth(rdProc62South),
.emptySouth(emptyProc62South),
.dataInSouth(dataInProc62South),
.wrSouth(wrProc62South),
.fullSouth(fullProc62South),
.dataOutSouth(dataOutProc62South),
.wrEast(wrProc62East),
.fullEast(fullProc62East),
.dataOutEast(dataOutProc62East),
.rdWest(rdProc62West),
.emptyWest(emptyProc62West),
.dataInWest(dataInProc62West));
//PROCESSOR 63
system proc63(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe63),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe63),
.rdNorth(rdProc63North),
.emptyNorth(emptyProc63North),
.dataInNorth(dataInProc63North),
.wrNorth(wrProc63North),
.fullNorth(fullProc63North),
.dataOutNorth(dataOutProc63North),
.rdSouth(rdProc63South),
.emptySouth(emptyProc63South),
.dataInSouth(dataInProc63South),
.wrSouth(wrProc63South),
.fullSouth(fullProc63South),
.dataOutSouth(dataOutProc63South),
.wrEast(wrProc63East),
.fullEast(fullProc63East),
.dataOutEast(dataOutProc63East),
.rdWest(rdProc63West),
.emptyWest(emptyProc63West),
.dataInWest(dataInProc63West));
//PROCESSOR 64
system proc64(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe64),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe64),
.wrSouth(wrProc64South),
.fullSouth(fullProc64South),
.dataOutSouth(dataOutProc64South),
.rdEast(rdProc64East),
.emptyEast(emptyProc64East),
.dataInEast(dataInProc64East),
.wrEast(wrProc64East),
.fullEast(fullProc64East),
.dataOutEast(dataOutProc64East),
.rdWest(rdProc64West),
.emptyWest(emptyProc64West),
.dataInWest(dataInProc64West));
//PROCESSOR 65
system proc65(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe65),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe65),
.rdWest(rdProc65West),
.emptyWest(emptyProc65West),
.dataInWest(dataInProc65West),
.wrWest(wrProc65West),
.fullWest(fullProc65West),
.dataOutWest(dataOutProc65West));
//PROCESSOR 66
system proc66(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe66),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe66),
.rdSouth(rdProc66South),
.emptySouth(emptyProc66South),
.dataInSouth(dataInProc66South),
.wrEast(wrProc66East),
.fullEast(fullProc66East),
.dataOutEast(dataOutProc66East));
//PROCESSOR 67
system proc67(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe67),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe67),
.rdNorth(rdProc67North),
.emptyNorth(emptyProc67North),
.dataInNorth(dataInProc67North),
.wrSouth(wrProc67South),
.fullSouth(fullProc67South),
.dataOutSouth(dataOutProc67South),
.wrEast(wrProc67East),
.fullEast(fullProc67East),
.dataOutEast(dataOutProc67East),
.rdWest(rdProc67West),
.emptyWest(emptyProc67West),
.dataInWest(dataInProc67West));
//PROCESSOR 68
system proc68(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe68),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe68),
.rdNorth(rdProc68North),
.emptyNorth(emptyProc68North),
.dataInNorth(dataInProc68North),
.wrSouth(wrProc68South),
.fullSouth(fullProc68South),
.dataOutSouth(dataOutProc68South),
.wrEast(wrProc68East),
.fullEast(fullProc68East),
.dataOutEast(dataOutProc68East),
.rdWest(rdProc68West),
.emptyWest(emptyProc68West),
.dataInWest(dataInProc68West));
//PROCESSOR 69
system proc69(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe69),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe69),
.wrNorth(wrProc69North),
.fullNorth(fullProc69North),
.dataOutNorth(dataOutProc69North),
.rdSouth(rdProc69South),
.emptySouth(emptyProc69South),
.dataInSouth(dataInProc69South),
.rdWest(rdProc69West),
.emptyWest(emptyProc69West),
.dataInWest(dataInProc69West));
//PROCESSOR 70
system proc70(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe70),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe70),
.rdNorth(rdProc70North),
.emptyNorth(emptyProc70North),
.dataInNorth(dataInProc70North),
.wrSouth(wrProc70South),
.fullSouth(fullProc70South),
.dataOutSouth(dataOutProc70South));
//PROCESSOR 71
system proc71(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe71),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe71),
.wrNorth(wrProc71North),
.fullNorth(fullProc71North),
.dataOutNorth(dataOutProc71North),
.rdSouth(rdProc71South),
.emptySouth(emptyProc71South),
.dataInSouth(dataInProc71South));
//PROCESSOR 72
system proc72(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe72),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe72),
.rdNorth(rdProc72North),
.emptyNorth(emptyProc72North),
.dataInNorth(dataInProc72North),
.wrNorth(wrProc72North),
.fullNorth(fullProc72North),
.dataOutNorth(dataOutProc72North),
.rdEast(rdProc72East),
.emptyEast(emptyProc72East),
.dataInEast(dataInProc72East),
.wrEast(wrProc72East),
.fullEast(fullProc72East),
.dataOutEast(dataOutProc72East));
//PROCESSOR 73
system proc73(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe73),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe73),
.rdNorth(rdProc73North),
.emptyNorth(emptyProc73North),
.dataInNorth(dataInProc73North),
.wrNorth(wrProc73North),
.fullNorth(fullProc73North),
.dataOutNorth(dataOutProc73North),
.wrSouth(wrProc73South),
.fullSouth(fullProc73South),
.dataOutSouth(dataOutProc73South),
.rdEast(rdProc73East),
.emptyEast(emptyProc73East),
.dataInEast(dataInProc73East),
.rdWest(rdProc73West),
.emptyWest(emptyProc73West),
.dataInWest(dataInProc73West),
.wrWest(wrProc73West),
.fullWest(fullProc73West),
.dataOutWest(dataOutProc73West));
//PROCESSOR 74
system proc74(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe74),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe74),
.rdNorth(rdProc74North),
.emptyNorth(emptyProc74North),
.dataInNorth(dataInProc74North),
.rdSouth(rdProc74South),
.emptySouth(emptyProc74South),
.dataInSouth(dataInProc74South),
.wrSouth(wrProc74South),
.fullSouth(fullProc74South),
.dataOutSouth(dataOutProc74South),
.rdEast(rdProc74East),
.emptyEast(emptyProc74East),
.dataInEast(dataInProc74East),
.wrEast(wrProc74East),
.fullEast(fullProc74East),
.dataOutEast(dataOutProc74East),
.wrWest(wrProc74West),
.fullWest(fullProc74West),
.dataOutWest(dataOutProc74West));
//PROCESSOR 75
system proc75(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe75),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe75),
.rdEast(rdProc75East),
.emptyEast(emptyProc75East),
.dataInEast(dataInProc75East),
.wrEast(wrProc75East),
.fullEast(fullProc75East),
.dataOutEast(dataOutProc75East),
.rdWest(rdProc75West),
.emptyWest(emptyProc75West),
.dataInWest(dataInProc75West),
.wrWest(wrProc75West),
.fullWest(fullProc75West),
.dataOutWest(dataOutProc75West));
//PROCESSOR 76
system proc76(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe76),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe76),
.wrNorth(wrProc76North),
.fullNorth(fullProc76North),
.dataOutNorth(dataOutProc76North),
.rdSouth(rdProc76South),
.emptySouth(emptyProc76South),
.dataInSouth(dataInProc76South),
.rdWest(rdProc76West),
.emptyWest(emptyProc76West),
.dataInWest(dataInProc76West),
.wrWest(wrProc76West),
.fullWest(fullProc76West),
.dataOutWest(dataOutProc76West));
//PROCESSOR 77
system proc77(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe77),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe77),
.rdNorth(rdProc77North),
.emptyNorth(emptyProc77North),
.dataInNorth(dataInProc77North),
.wrSouth(wrProc77South),
.fullSouth(fullProc77South),
.dataOutSouth(dataOutProc77South),
.rdEast(rdProc77East),
.emptyEast(emptyProc77East),
.dataInEast(dataInProc77East));
//PROCESSOR 78
system proc78(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe78),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe78),
.rdNorth(rdProc78North),
.emptyNorth(emptyProc78North),
.dataInNorth(dataInProc78North),
.wrWest(wrProc78West),
.fullWest(fullProc78West),
.dataOutWest(dataOutProc78West));
//PROCESSOR 79
system proc79(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe79),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe79),
.wrNorth(wrProc79North),
.fullNorth(fullProc79North),
.dataOutNorth(dataOutProc79North),
.rdSouth(rdProc79South),
.emptySouth(emptyProc79South),
.dataInSouth(dataInProc79South));
//PROCESSOR 80
system proc80(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe80),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe80),
.rdNorth(rdProc80North),
.emptyNorth(emptyProc80North),
.dataInNorth(dataInProc80North),
.wrEast(wrProc80East),
.fullEast(fullProc80East),
.dataOutEast(dataOutProc80East));
//PROCESSOR 81
system proc81(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe81),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe81),
.wrNorth(wrProc81North),
.fullNorth(fullProc81North),
.dataOutNorth(dataOutProc81North),
.rdEast(rdProc81East),
.emptyEast(emptyProc81East),
.dataInEast(dataInProc81East),
.wrEast(wrProc81East),
.fullEast(fullProc81East),
.dataOutEast(dataOutProc81East),
.rdWest(rdProc81West),
.emptyWest(emptyProc81West),
.dataInWest(dataInProc81West));
//PROCESSOR 82
system proc82(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe82),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe82),
.rdEast(rdProc82East),
.emptyEast(emptyProc82East),
.dataInEast(dataInProc82East),
.wrEast(wrProc82East),
.fullEast(fullProc82East),
.dataOutEast(dataOutProc82East),
.rdWest(rdProc82West),
.emptyWest(emptyProc82West),
.dataInWest(dataInProc82West),
.wrWest(wrProc82West),
.fullWest(fullProc82West),
.dataOutWest(dataOutProc82West));
//PROCESSOR 83
system proc83(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe83),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe83),
.rdNorth(rdProc83North),
.emptyNorth(emptyProc83North),
.dataInNorth(dataInProc83North),
.rdEast(rdProc83East),
.emptyEast(emptyProc83East),
.dataInEast(dataInProc83East),
.wrEast(wrProc83East),
.fullEast(fullProc83East),
.dataOutEast(dataOutProc83East),
.rdWest(rdProc83West),
.emptyWest(emptyProc83West),
.dataInWest(dataInProc83West),
.wrWest(wrProc83West),
.fullWest(fullProc83West),
.dataOutWest(dataOutProc83West));
//PROCESSOR 84
system proc84(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe84),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe84),
.rdNorth(rdProc84North),
.emptyNorth(emptyProc84North),
.dataInNorth(dataInProc84North),
.wrNorth(wrProc84North),
.fullNorth(fullProc84North),
.dataOutNorth(dataOutProc84North),
.rdEast(rdProc84East),
.emptyEast(emptyProc84East),
.dataInEast(dataInProc84East),
.wrEast(wrProc84East),
.fullEast(fullProc84East),
.dataOutEast(dataOutProc84East),
.rdWest(rdProc84West),
.emptyWest(emptyProc84West),
.dataInWest(dataInProc84West),
.wrWest(wrProc84West),
.fullWest(fullProc84West),
.dataOutWest(dataOutProc84West));
//PROCESSOR 85
system proc85(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe85),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe85),
.rdWest(rdProc85West),
.emptyWest(emptyProc85West),
.dataInWest(dataInProc85West),
.wrWest(wrProc85West),
.fullWest(fullProc85West),
.dataOutWest(dataOutProc85West));
//PROCESSOR 86
system proc86(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe86),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe86),
.wrNorth(wrProc86North),
.fullNorth(fullProc86North),
.dataOutNorth(dataOutProc86North),
.rdEast(rdProc86East),
.emptyEast(emptyProc86East),
.dataInEast(dataInProc86East));
//PROCESSOR 87
system proc87(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe87),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe87),
.rdNorth(rdProc87North),
.emptyNorth(emptyProc87North),
.dataInNorth(dataInProc87North),
.wrEast(wrProc87East),
.fullEast(fullProc87East),
.dataOutEast(dataOutProc87East),
.wrWest(wrProc87West),
.fullWest(fullProc87West),
.dataOutWest(dataOutProc87West));
//PROCESSOR 88
system proc88(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe88),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe88),
.wrEast(wrProc88East),
.fullEast(fullProc88East),
.dataOutEast(dataOutProc88East),
.rdWest(rdProc88West),
.emptyWest(emptyProc88West),
.dataInWest(dataInProc88West));
//PROCESSOR 89
system proc89(.clk(clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe89),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe89),
.wrNorth(wrProc89North),
.fullNorth(fullProc89North),
.dataOutNorth(dataOutProc89North),
.rdWest(rdProc89West),
.emptyWest(emptyProc89West),
.dataInWest(dataInProc89West));
//FIFO 0 TO 10
fifo fifo_proc0_to_proc10(
.clk(clk),
.resetn(resetn),
.wr(wrProc0South),
.full(fullProc0South),
.dataIn(dataOutProc0South),
.rd(rdProc10North),
.empty(emptyProc10North),
.dataOut(dataInProc10North));
//FIFO 0 TO 1
fifo fifo_proc0_to_proc1(
.clk(clk),
.resetn(resetn),
.wr(wrProc0East),
.full(fullProc0East),
.dataIn(dataOutProc0East),
.rd(rdProc1West),
.empty(emptyProc1West),
.dataOut(dataInProc1West));
//FIFO 1 TO 11
fifo fifo_proc1_to_proc11(
.clk(clk),
.resetn(resetn),
.wr(wrProc1South),
.full(fullProc1South),
.dataIn(dataOutProc1South),
.rd(rdProc11North),
.empty(emptyProc11North),
.dataOut(dataInProc11North));
//FIFO 14 TO 4
fifo fifo_proc14_to_proc4(
.clk(clk),
.resetn(resetn),
.wr(wrProc14North),
.full(fullProc14North),
.dataIn(dataOutProc14North),
.rd(rdProc4South),
.empty(emptyProc4South),
.dataOut(dataInProc4South));
//FIFO 5 TO 4
fifo fifo_proc5_to_proc4(
.clk(clk),
.resetn(resetn),
.wr(wrProc5West),
.full(fullProc5West),
.dataIn(dataOutProc5West),
.rd(rdProc4East),
.empty(emptyProc4East),
.dataOut(dataInProc4East));
//FIFO 4 TO 5
fifo fifo_proc4_to_proc5(
.clk(clk),
.resetn(resetn),
.wr(wrProc4East),
.full(fullProc4East),
.dataIn(dataOutProc4East),
.rd(rdProc5West),
.empty(emptyProc5West),
.dataOut(dataInProc5West));
//FIFO 6 TO 5
fifo fifo_proc6_to_proc5(
.clk(clk),
.resetn(resetn),
.wr(wrProc6West),
.full(fullProc6West),
.dataIn(dataOutProc6West),
.rd(rdProc5East),
.empty(emptyProc5East),
.dataOut(dataInProc5East));
//FIFO 16 TO 6
fifo fifo_proc16_to_proc6(
.clk(clk),
.resetn(resetn),
.wr(wrProc16North),
.full(fullProc16North),
.dataIn(dataOutProc16North),
.rd(rdProc6South),
.empty(emptyProc6South),
.dataOut(dataInProc6South));
//FIFO 6 TO 16
fifo fifo_proc6_to_proc16(
.clk(clk),
.resetn(resetn),
.wr(wrProc6South),
.full(fullProc6South),
.dataIn(dataOutProc6South),
.rd(rdProc16North),
.empty(emptyProc16North),
.dataOut(dataInProc16North));
//FIFO 7 TO 6
fifo fifo_proc7_to_proc6(
.clk(clk),
.resetn(resetn),
.wr(wrProc7West),
.full(fullProc7West),
.dataIn(dataOutProc7West),
.rd(rdProc6East),
.empty(emptyProc6East),
.dataOut(dataInProc6East));
//FIFO 17 TO 7
fifo fifo_proc17_to_proc7(
.clk(clk),
.resetn(resetn),
.wr(wrProc17North),
.full(fullProc17North),
.dataIn(dataOutProc17North),
.rd(rdProc7South),
.empty(emptyProc7South),
.dataOut(dataInProc7South));
//FIFO 18 TO 8
fifo fifo_proc18_to_proc8(
.clk(clk),
.resetn(resetn),
.wr(wrProc18North),
.full(fullProc18North),
.dataIn(dataOutProc18North),
.rd(rdProc8South),
.empty(emptyProc8South),
.dataOut(dataInProc8South));
//FIFO 8 TO 18
fifo fifo_proc8_to_proc18(
.clk(clk),
.resetn(resetn),
.wr(wrProc8South),
.full(fullProc8South),
.dataIn(dataOutProc8South),
.rd(rdProc18North),
.empty(emptyProc18North),
.dataOut(dataInProc18North));
//FIFO 9 TO 8
fifo fifo_proc9_to_proc8(
.clk(clk),
.resetn(resetn),
.wr(wrProc9West),
.full(fullProc9West),
.dataIn(dataOutProc9West),
.rd(rdProc8East),
.empty(emptyProc8East),
.dataOut(dataInProc8East));
//FIFO 19 TO 9
fifo fifo_proc19_to_proc9(
.clk(clk),
.resetn(resetn),
.wr(wrProc19North),
.full(fullProc19North),
.dataIn(dataOutProc19North),
.rd(rdProc9South),
.empty(emptyProc9South),
.dataOut(dataInProc9South));
//FIFO 10 TO 11
fifo fifo_proc10_to_proc11(
.clk(clk),
.resetn(resetn),
.wr(wrProc10East),
.full(fullProc10East),
.dataIn(dataOutProc10East),
.rd(rdProc11West),
.empty(emptyProc11West),
.dataOut(dataInProc11West));
//FIFO 11 TO 21
fifo fifo_proc11_to_proc21(
.clk(clk),
.resetn(resetn),
.wr(wrProc11South),
.full(fullProc11South),
.dataIn(dataOutProc11South),
.rd(rdProc21North),
.empty(emptyProc21North),
.dataOut(dataInProc21North));
//FIFO 22 TO 12
fifo fifo_proc22_to_proc12(
.clk(clk),
.resetn(resetn),
.wr(wrProc22North),
.full(fullProc22North),
.dataIn(dataOutProc22North),
.rd(rdProc12South),
.empty(emptyProc12South),
.dataOut(dataInProc12South));
//FIFO 12 TO 13
fifo fifo_proc12_to_proc13(
.clk(clk),
.resetn(resetn),
.wr(wrProc12East),
.full(fullProc12East),
.dataIn(dataOutProc12East),
.rd(rdProc13West),
.empty(emptyProc13West),
.dataOut(dataInProc13West));
//FIFO 23 TO 13
fifo fifo_proc23_to_proc13(
.clk(clk),
.resetn(resetn),
.wr(wrProc23North),
.full(fullProc23North),
.dataIn(dataOutProc23North),
.rd(rdProc13South),
.empty(emptyProc13South),
.dataOut(dataInProc13South));
//FIFO 13 TO 14
fifo fifo_proc13_to_proc14(
.clk(clk),
.resetn(resetn),
.wr(wrProc13East),
.full(fullProc13East),
.dataIn(dataOutProc13East),
.rd(rdProc14West),
.empty(emptyProc14West),
.dataOut(dataInProc14West));
//FIFO 24 TO 14
fifo fifo_proc24_to_proc14(
.clk(clk),
.resetn(resetn),
.wr(wrProc24North),
.full(fullProc24North),
.dataIn(dataOutProc24North),
.rd(rdProc14South),
.empty(emptyProc14South),
.dataOut(dataInProc14South));
//FIFO 14 TO 24
fifo fifo_proc14_to_proc24(
.clk(clk),
.resetn(resetn),
.wr(wrProc14South),
.full(fullProc14South),
.dataIn(dataOutProc14South),
.rd(rdProc24North),
.empty(emptyProc24North),
.dataOut(dataInProc24North));
//FIFO 14 TO 15
fifo fifo_proc14_to_proc15(
.clk(clk),
.resetn(resetn),
.wr(wrProc14East),
.full(fullProc14East),
.dataIn(dataOutProc14East),
.rd(rdProc15West),
.empty(emptyProc15West),
.dataOut(dataInProc15West));
//FIFO 15 TO 16
fifo fifo_proc15_to_proc16(
.clk(clk),
.resetn(resetn),
.wr(wrProc15East),
.full(fullProc15East),
.dataIn(dataOutProc15East),
.rd(rdProc16West),
.empty(emptyProc16West),
.dataOut(dataInProc16West));
//FIFO 16 TO 26
fifo fifo_proc16_to_proc26(
.clk(clk),
.resetn(resetn),
.wr(wrProc16South),
.full(fullProc16South),
.dataIn(dataOutProc16South),
.rd(rdProc26North),
.empty(emptyProc26North),
.dataOut(dataInProc26North));
//FIFO 27 TO 17
fifo fifo_proc27_to_proc17(
.clk(clk),
.resetn(resetn),
.wr(wrProc27North),
.full(fullProc27North),
.dataIn(dataOutProc27North),
.rd(rdProc17South),
.empty(emptyProc17South),
.dataOut(dataInProc17South));
//FIFO 18 TO 28
fifo fifo_proc18_to_proc28(
.clk(clk),
.resetn(resetn),
.wr(wrProc18South),
.full(fullProc18South),
.dataIn(dataOutProc18South),
.rd(rdProc28North),
.empty(emptyProc28North),
.dataOut(dataInProc28North));
//FIFO 29 TO 19
fifo fifo_proc29_to_proc19(
.clk(clk),
.resetn(resetn),
.wr(wrProc29North),
.full(fullProc29North),
.dataIn(dataOutProc29North),
.rd(rdProc19South),
.empty(emptyProc19South),
.dataOut(dataInProc19South));
//FIFO 19 TO 29
fifo fifo_proc19_to_proc29(
.clk(clk),
.resetn(resetn),
.wr(wrProc19South),
.full(fullProc19South),
.dataIn(dataOutProc19South),
.rd(rdProc29North),
.empty(emptyProc29North),
.dataOut(dataInProc29North));
//FIFO 30 TO 20
fifo fifo_proc30_to_proc20(
.clk(clk),
.resetn(resetn),
.wr(wrProc30North),
.full(fullProc30North),
.dataIn(dataOutProc30North),
.rd(rdProc20South),
.empty(emptyProc20South),
.dataOut(dataInProc20South));
//FIFO 20 TO 21
fifo fifo_proc20_to_proc21(
.clk(clk),
.resetn(resetn),
.wr(wrProc20East),
.full(fullProc20East),
.dataIn(dataOutProc20East),
.rd(rdProc21West),
.empty(emptyProc21West),
.dataOut(dataInProc21West));
//FIFO 31 TO 21
fifo fifo_proc31_to_proc21(
.clk(clk),
.resetn(resetn),
.wr(wrProc31North),
.full(fullProc31North),
.dataIn(dataOutProc31North),
.rd(rdProc21South),
.empty(emptyProc21South),
.dataOut(dataInProc21South));
//FIFO 21 TO 31
fifo fifo_proc21_to_proc31(
.clk(clk),
.resetn(resetn),
.wr(wrProc21South),
.full(fullProc21South),
.dataIn(dataOutProc21South),
.rd(rdProc31North),
.empty(emptyProc31North),
.dataOut(dataInProc31North));
//FIFO 21 TO 22
fifo fifo_proc21_to_proc22(
.clk(clk),
.resetn(resetn),
.wr(wrProc21East),
.full(fullProc21East),
.dataIn(dataOutProc21East),
.rd(rdProc22West),
.empty(emptyProc22West),
.dataOut(dataInProc22West));
//FIFO 32 TO 22
fifo fifo_proc32_to_proc22(
.clk(clk),
.resetn(resetn),
.wr(wrProc32North),
.full(fullProc32North),
.dataIn(dataOutProc32North),
.rd(rdProc22South),
.empty(emptyProc22South),
.dataOut(dataInProc22South));
//FIFO 22 TO 32
fifo fifo_proc22_to_proc32(
.clk(clk),
.resetn(resetn),
.wr(wrProc22South),
.full(fullProc22South),
.dataIn(dataOutProc22South),
.rd(rdProc32North),
.empty(emptyProc32North),
.dataOut(dataInProc32North));
//FIFO 23 TO 22
fifo fifo_proc23_to_proc22(
.clk(clk),
.resetn(resetn),
.wr(wrProc23West),
.full(fullProc23West),
.dataIn(dataOutProc23West),
.rd(rdProc22East),
.empty(emptyProc22East),
.dataOut(dataInProc22East));
//FIFO 22 TO 23
fifo fifo_proc22_to_proc23(
.clk(clk),
.resetn(resetn),
.wr(wrProc22East),
.full(fullProc22East),
.dataIn(dataOutProc22East),
.rd(rdProc23West),
.empty(emptyProc23West),
.dataOut(dataInProc23West));
//FIFO 33 TO 23
fifo fifo_proc33_to_proc23(
.clk(clk),
.resetn(resetn),
.wr(wrProc33North),
.full(fullProc33North),
.dataIn(dataOutProc33North),
.rd(rdProc23South),
.empty(emptyProc23South),
.dataOut(dataInProc23South));
//FIFO 24 TO 23
fifo fifo_proc24_to_proc23(
.clk(clk),
.resetn(resetn),
.wr(wrProc24West),
.full(fullProc24West),
.dataIn(dataOutProc24West),
.rd(rdProc23East),
.empty(emptyProc23East),
.dataOut(dataInProc23East));
//FIFO 23 TO 24
fifo fifo_proc23_to_proc24(
.clk(clk),
.resetn(resetn),
.wr(wrProc23East),
.full(fullProc23East),
.dataIn(dataOutProc23East),
.rd(rdProc24West),
.empty(emptyProc24West),
.dataOut(dataInProc24West));
//FIFO 24 TO 34
fifo fifo_proc24_to_proc34(
.clk(clk),
.resetn(resetn),
.wr(wrProc24South),
.full(fullProc24South),
.dataIn(dataOutProc24South),
.rd(rdProc34North),
.empty(emptyProc34North),
.dataOut(dataInProc34North));
//FIFO 25 TO 24
fifo fifo_proc25_to_proc24(
.clk(clk),
.resetn(resetn),
.wr(wrProc25West),
.full(fullProc25West),
.dataIn(dataOutProc25West),
.rd(rdProc24East),
.empty(emptyProc24East),
.dataOut(dataInProc24East));
//FIFO 24 TO 25
fifo fifo_proc24_to_proc25(
.clk(clk),
.resetn(resetn),
.wr(wrProc24East),
.full(fullProc24East),
.dataIn(dataOutProc24East),
.rd(rdProc25West),
.empty(emptyProc25West),
.dataOut(dataInProc25West));
//FIFO 35 TO 25
fifo fifo_proc35_to_proc25(
.clk(clk),
.resetn(resetn),
.wr(wrProc35North),
.full(fullProc35North),
.dataIn(dataOutProc35North),
.rd(rdProc25South),
.empty(emptyProc25South),
.dataOut(dataInProc25South));
//FIFO 25 TO 35
fifo fifo_proc25_to_proc35(
.clk(clk),
.resetn(resetn),
.wr(wrProc25South),
.full(fullProc25South),
.dataIn(dataOutProc25South),
.rd(rdProc35North),
.empty(emptyProc35North),
.dataOut(dataInProc35North));
//FIFO 26 TO 25
fifo fifo_proc26_to_proc25(
.clk(clk),
.resetn(resetn),
.wr(wrProc26West),
.full(fullProc26West),
.dataIn(dataOutProc26West),
.rd(rdProc25East),
.empty(emptyProc25East),
.dataOut(dataInProc25East));
//FIFO 25 TO 26
fifo fifo_proc25_to_proc26(
.clk(clk),
.resetn(resetn),
.wr(wrProc25East),
.full(fullProc25East),
.dataIn(dataOutProc25East),
.rd(rdProc26West),
.empty(emptyProc26West),
.dataOut(dataInProc26West));
//FIFO 26 TO 36
fifo fifo_proc26_to_proc36(
.clk(clk),
.resetn(resetn),
.wr(wrProc26South),
.full(fullProc26South),
.dataIn(dataOutProc26South),
.rd(rdProc36North),
.empty(emptyProc36North),
.dataOut(dataInProc36North));
//FIFO 26 TO 27
fifo fifo_proc26_to_proc27(
.clk(clk),
.resetn(resetn),
.wr(wrProc26East),
.full(fullProc26East),
.dataIn(dataOutProc26East),
.rd(rdProc27West),
.empty(emptyProc27West),
.dataOut(dataInProc27West));
//FIFO 27 TO 37
fifo fifo_proc27_to_proc37(
.clk(clk),
.resetn(resetn),
.wr(wrProc27South),
.full(fullProc27South),
.dataIn(dataOutProc27South),
.rd(rdProc37North),
.empty(emptyProc37North),
.dataOut(dataInProc37North));
//FIFO 28 TO 27
fifo fifo_proc28_to_proc27(
.clk(clk),
.resetn(resetn),
.wr(wrProc28West),
.full(fullProc28West),
.dataIn(dataOutProc28West),
.rd(rdProc27East),
.empty(emptyProc27East),
.dataOut(dataInProc27East));
//FIFO 27 TO 28
fifo fifo_proc27_to_proc28(
.clk(clk),
.resetn(resetn),
.wr(wrProc27East),
.full(fullProc27East),
.dataIn(dataOutProc27East),
.rd(rdProc28West),
.empty(emptyProc28West),
.dataOut(dataInProc28West));
//FIFO 28 TO 38
fifo fifo_proc28_to_proc38(
.clk(clk),
.resetn(resetn),
.wr(wrProc28South),
.full(fullProc28South),
.dataIn(dataOutProc28South),
.rd(rdProc38North),
.empty(emptyProc38North),
.dataOut(dataInProc38North));
//FIFO 29 TO 28
fifo fifo_proc29_to_proc28(
.clk(clk),
.resetn(resetn),
.wr(wrProc29West),
.full(fullProc29West),
.dataIn(dataOutProc29West),
.rd(rdProc28East),
.empty(emptyProc28East),
.dataOut(dataInProc28East));
//FIFO 39 TO 29
fifo fifo_proc39_to_proc29(
.clk(clk),
.resetn(resetn),
.wr(wrProc39North),
.full(fullProc39North),
.dataIn(dataOutProc39North),
.rd(rdProc29South),
.empty(emptyProc29South),
.dataOut(dataInProc29South));
//FIFO 40 TO 30
fifo fifo_proc40_to_proc30(
.clk(clk),
.resetn(resetn),
.wr(wrProc40North),
.full(fullProc40North),
.dataIn(dataOutProc40North),
.rd(rdProc30South),
.empty(emptyProc30South),
.dataOut(dataInProc30South));
//FIFO 43 TO 33
fifo fifo_proc43_to_proc33(
.clk(clk),
.resetn(resetn),
.wr(wrProc43North),
.full(fullProc43North),
.dataIn(dataOutProc43North),
.rd(rdProc33South),
.empty(emptyProc33South),
.dataOut(dataInProc33South));
//FIFO 33 TO 43
fifo fifo_proc33_to_proc43(
.clk(clk),
.resetn(resetn),
.wr(wrProc33South),
.full(fullProc33South),
.dataIn(dataOutProc33South),
.rd(rdProc43North),
.empty(emptyProc43North),
.dataOut(dataInProc43North));
//FIFO 34 TO 33
fifo fifo_proc34_to_proc33(
.clk(clk),
.resetn(resetn),
.wr(wrProc34West),
.full(fullProc34West),
.dataIn(dataOutProc34West),
.rd(rdProc33East),
.empty(emptyProc33East),
.dataOut(dataInProc33East));
//FIFO 45 TO 35
fifo fifo_proc45_to_proc35(
.clk(clk),
.resetn(resetn),
.wr(wrProc45North),
.full(fullProc45North),
.dataIn(dataOutProc45North),
.rd(rdProc35South),
.empty(emptyProc35South),
.dataOut(dataInProc35South));
//FIFO 35 TO 36
fifo fifo_proc35_to_proc36(
.clk(clk),
.resetn(resetn),
.wr(wrProc35East),
.full(fullProc35East),
.dataIn(dataOutProc35East),
.rd(rdProc36West),
.empty(emptyProc36West),
.dataOut(dataInProc36West));
//FIFO 36 TO 46
fifo fifo_proc36_to_proc46(
.clk(clk),
.resetn(resetn),
.wr(wrProc36South),
.full(fullProc36South),
.dataIn(dataOutProc36South),
.rd(rdProc46North),
.empty(emptyProc46North),
.dataOut(dataInProc46North));
//FIFO 36 TO 37
fifo fifo_proc36_to_proc37(
.clk(clk),
.resetn(resetn),
.wr(wrProc36East),
.full(fullProc36East),
.dataIn(dataOutProc36East),
.rd(rdProc37West),
.empty(emptyProc37West),
.dataOut(dataInProc37West));
//FIFO 37 TO 47
fifo fifo_proc37_to_proc47(
.clk(clk),
.resetn(resetn),
.wr(wrProc37South),
.full(fullProc37South),
.dataIn(dataOutProc37South),
.rd(rdProc47North),
.empty(emptyProc47North),
.dataOut(dataInProc47North));
//FIFO 48 TO 38
fifo fifo_proc48_to_proc38(
.clk(clk),
.resetn(resetn),
.wr(wrProc48North),
.full(fullProc48North),
.dataIn(dataOutProc48North),
.rd(rdProc38South),
.empty(emptyProc38South),
.dataOut(dataInProc38South));
//FIFO 38 TO 48
fifo fifo_proc38_to_proc48(
.clk(clk),
.resetn(resetn),
.wr(wrProc38South),
.full(fullProc38South),
.dataIn(dataOutProc38South),
.rd(rdProc48North),
.empty(emptyProc48North),
.dataOut(dataInProc48North));
//FIFO 38 TO 39
fifo fifo_proc38_to_proc39(
.clk(clk),
.resetn(resetn),
.wr(wrProc38East),
.full(fullProc38East),
.dataIn(dataOutProc38East),
.rd(rdProc39West),
.empty(emptyProc39West),
.dataOut(dataInProc39West));
//FIFO 49 TO 39
fifo fifo_proc49_to_proc39(
.clk(clk),
.resetn(resetn),
.wr(wrProc49North),
.full(fullProc49North),
.dataIn(dataOutProc49North),
.rd(rdProc39South),
.empty(emptyProc39South),
.dataOut(dataInProc39South));
//FIFO 50 TO 40
fifo fifo_proc50_to_proc40(
.clk(clk),
.resetn(resetn),
.wr(wrProc50North),
.full(fullProc50North),
.dataIn(dataOutProc50North),
.rd(rdProc40South),
.empty(emptyProc40South),
.dataOut(dataInProc40South));
//FIFO 40 TO 50
fifo fifo_proc40_to_proc50(
.clk(clk),
.resetn(resetn),
.wr(wrProc40South),
.full(fullProc40South),
.dataIn(dataOutProc40South),
.rd(rdProc50North),
.empty(emptyProc50North),
.dataOut(dataInProc50North));
//FIFO 41 TO 40
fifo fifo_proc41_to_proc40(
.clk(clk),
.resetn(resetn),
.wr(wrProc41West),
.full(fullProc41West),
.dataIn(dataOutProc41West),
.rd(rdProc40East),
.empty(emptyProc40East),
.dataOut(dataInProc40East));
//FIFO 42 TO 41
fifo fifo_proc42_to_proc41(
.clk(clk),
.resetn(resetn),
.wr(wrProc42West),
.full(fullProc42West),
.dataIn(dataOutProc42West),
.rd(rdProc41East),
.empty(emptyProc41East),
.dataOut(dataInProc41East));
//FIFO 52 TO 42
fifo fifo_proc52_to_proc42(
.clk(clk),
.resetn(resetn),
.wr(wrProc52North),
.full(fullProc52North),
.dataIn(dataOutProc52North),
.rd(rdProc42South),
.empty(emptyProc42South),
.dataOut(dataInProc42South));
//FIFO 43 TO 42
fifo fifo_proc43_to_proc42(
.clk(clk),
.resetn(resetn),
.wr(wrProc43West),
.full(fullProc43West),
.dataIn(dataOutProc43West),
.rd(rdProc42East),
.empty(emptyProc42East),
.dataOut(dataInProc42East));
//FIFO 42 TO 43
fifo fifo_proc42_to_proc43(
.clk(clk),
.resetn(resetn),
.wr(wrProc42East),
.full(fullProc42East),
.dataIn(dataOutProc42East),
.rd(rdProc43West),
.empty(emptyProc43West),
.dataOut(dataInProc43West));
//FIFO 53 TO 43
fifo fifo_proc53_to_proc43(
.clk(clk),
.resetn(resetn),
.wr(wrProc53North),
.full(fullProc53North),
.dataIn(dataOutProc53North),
.rd(rdProc43South),
.empty(emptyProc43South),
.dataOut(dataInProc43South));
//FIFO 43 TO 53
fifo fifo_proc43_to_proc53(
.clk(clk),
.resetn(resetn),
.wr(wrProc43South),
.full(fullProc43South),
.dataIn(dataOutProc43South),
.rd(rdProc53North),
.empty(emptyProc53North),
.dataOut(dataInProc53North));
//FIFO 43 TO 44
fifo fifo_proc43_to_proc44(
.clk(clk),
.resetn(resetn),
.wr(wrProc43East),
.full(fullProc43East),
.dataIn(dataOutProc43East),
.rd(rdProc44West),
.empty(emptyProc44West),
.dataOut(dataInProc44West));
//FIFO 44 TO 45
fifo fifo_proc44_to_proc45(
.clk(clk),
.resetn(resetn),
.wr(wrProc44East),
.full(fullProc44East),
.dataIn(dataOutProc44East),
.rd(rdProc45West),
.empty(emptyProc45West),
.dataOut(dataInProc45West));
//FIFO 45 TO 55
fifo fifo_proc45_to_proc55(
.clk(clk),
.resetn(resetn),
.wr(wrProc45South),
.full(fullProc45South),
.dataIn(dataOutProc45South),
.rd(rdProc55North),
.empty(emptyProc55North),
.dataOut(dataInProc55North));
//FIFO 46 TO 45
fifo fifo_proc46_to_proc45(
.clk(clk),
.resetn(resetn),
.wr(wrProc46West),
.full(fullProc46West),
.dataIn(dataOutProc46West),
.rd(rdProc45East),
.empty(emptyProc45East),
.dataOut(dataInProc45East));
//FIFO 46 TO 56
fifo fifo_proc46_to_proc56(
.clk(clk),
.resetn(resetn),
.wr(wrProc46South),
.full(fullProc46South),
.dataIn(dataOutProc46South),
.rd(rdProc56North),
.empty(emptyProc56North),
.dataOut(dataInProc56North));
//FIFO 47 TO 46
fifo fifo_proc47_to_proc46(
.clk(clk),
.resetn(resetn),
.wr(wrProc47West),
.full(fullProc47West),
.dataIn(dataOutProc47West),
.rd(rdProc46East),
.empty(emptyProc46East),
.dataOut(dataInProc46East));
//FIFO 47 TO 57
fifo fifo_proc47_to_proc57(
.clk(clk),
.resetn(resetn),
.wr(wrProc47South),
.full(fullProc47South),
.dataIn(dataOutProc47South),
.rd(rdProc57North),
.empty(emptyProc57North),
.dataOut(dataInProc57North));
//FIFO 58 TO 48
fifo fifo_proc58_to_proc48(
.clk(clk),
.resetn(resetn),
.wr(wrProc58North),
.full(fullProc58North),
.dataIn(dataOutProc58North),
.rd(rdProc48South),
.empty(emptyProc48South),
.dataOut(dataInProc48South));
//FIFO 48 TO 58
fifo fifo_proc48_to_proc58(
.clk(clk),
.resetn(resetn),
.wr(wrProc48South),
.full(fullProc48South),
.dataIn(dataOutProc48South),
.rd(rdProc58North),
.empty(emptyProc58North),
.dataOut(dataInProc58North));
//FIFO 59 TO 49
fifo fifo_proc59_to_proc49(
.clk(clk),
.resetn(resetn),
.wr(wrProc59North),
.full(fullProc59North),
.dataIn(dataOutProc59North),
.rd(rdProc49South),
.empty(emptyProc49South),
.dataOut(dataInProc49South));
//FIFO 51 TO 50
fifo fifo_proc51_to_proc50(
.clk(clk),
.resetn(resetn),
.wr(wrProc51West),
.full(fullProc51West),
.dataIn(dataOutProc51West),
.rd(rdProc50East),
.empty(emptyProc50East),
.dataOut(dataInProc50East));
//FIFO 50 TO 51
fifo fifo_proc50_to_proc51(
.clk(clk),
.resetn(resetn),
.wr(wrProc50East),
.full(fullProc50East),
.dataIn(dataOutProc50East),
.rd(rdProc51West),
.empty(emptyProc51West),
.dataOut(dataInProc51West));
//FIFO 52 TO 51
fifo fifo_proc52_to_proc51(
.clk(clk),
.resetn(resetn),
.wr(wrProc52West),
.full(fullProc52West),
.dataIn(dataOutProc52West),
.rd(rdProc51East),
.empty(emptyProc51East),
.dataOut(dataInProc51East));
//FIFO 51 TO 52
fifo fifo_proc51_to_proc52(
.clk(clk),
.resetn(resetn),
.wr(wrProc51East),
.full(fullProc51East),
.dataIn(dataOutProc51East),
.rd(rdProc52West),
.empty(emptyProc52West),
.dataOut(dataInProc52West));
//FIFO 62 TO 52
fifo fifo_proc62_to_proc52(
.clk(clk),
.resetn(resetn),
.wr(wrProc62North),
.full(fullProc62North),
.dataIn(dataOutProc62North),
.rd(rdProc52South),
.empty(emptyProc52South),
.dataOut(dataInProc52South));
//FIFO 52 TO 62
fifo fifo_proc52_to_proc62(
.clk(clk),
.resetn(resetn),
.wr(wrProc52South),
.full(fullProc52South),
.dataIn(dataOutProc52South),
.rd(rdProc62North),
.empty(emptyProc62North),
.dataOut(dataInProc62North));
//FIFO 53 TO 52
fifo fifo_proc53_to_proc52(
.clk(clk),
.resetn(resetn),
.wr(wrProc53West),
.full(fullProc53West),
.dataIn(dataOutProc53West),
.rd(rdProc52East),
.empty(emptyProc52East),
.dataOut(dataInProc52East));
//FIFO 52 TO 53
fifo fifo_proc52_to_proc53(
.clk(clk),
.resetn(resetn),
.wr(wrProc52East),
.full(fullProc52East),
.dataIn(dataOutProc52East),
.rd(rdProc53West),
.empty(emptyProc53West),
.dataOut(dataInProc53West));
//FIFO 63 TO 53
fifo fifo_proc63_to_proc53(
.clk(clk),
.resetn(resetn),
.wr(wrProc63North),
.full(fullProc63North),
.dataIn(dataOutProc63North),
.rd(rdProc53South),
.empty(emptyProc53South),
.dataOut(dataInProc53South));
//FIFO 53 TO 63
fifo fifo_proc53_to_proc63(
.clk(clk),
.resetn(resetn),
.wr(wrProc53South),
.full(fullProc53South),
.dataIn(dataOutProc53South),
.rd(rdProc63North),
.empty(emptyProc63North),
.dataOut(dataInProc63North));
//FIFO 54 TO 53
fifo fifo_proc54_to_proc53(
.clk(clk),
.resetn(resetn),
.wr(wrProc54West),
.full(fullProc54West),
.dataIn(dataOutProc54West),
.rd(rdProc53East),
.empty(emptyProc53East),
.dataOut(dataInProc53East));
//FIFO 55 TO 54
fifo fifo_proc55_to_proc54(
.clk(clk),
.resetn(resetn),
.wr(wrProc55West),
.full(fullProc55West),
.dataIn(dataOutProc55West),
.rd(rdProc54East),
.empty(emptyProc54East),
.dataOut(dataInProc54East));
//FIFO 56 TO 55
fifo fifo_proc56_to_proc55(
.clk(clk),
.resetn(resetn),
.wr(wrProc56West),
.full(fullProc56West),
.dataIn(dataOutProc56West),
.rd(rdProc55East),
.empty(emptyProc55East),
.dataOut(dataInProc55East));
//FIFO 57 TO 56
fifo fifo_proc57_to_proc56(
.clk(clk),
.resetn(resetn),
.wr(wrProc57West),
.full(fullProc57West),
.dataIn(dataOutProc57West),
.rd(rdProc56East),
.empty(emptyProc56East),
.dataOut(dataInProc56East));
//FIFO 56 TO 57
fifo fifo_proc56_to_proc57(
.clk(clk),
.resetn(resetn),
.wr(wrProc56East),
.full(fullProc56East),
.dataIn(dataOutProc56East),
.rd(rdProc57West),
.empty(emptyProc57West),
.dataOut(dataInProc57West));
//FIFO 57 TO 67
fifo fifo_proc57_to_proc67(
.clk(clk),
.resetn(resetn),
.wr(wrProc57South),
.full(fullProc57South),
.dataIn(dataOutProc57South),
.rd(rdProc67North),
.empty(emptyProc67North),
.dataOut(dataInProc67North));
//FIFO 58 TO 68
fifo fifo_proc58_to_proc68(
.clk(clk),
.resetn(resetn),
.wr(wrProc58South),
.full(fullProc58South),
.dataIn(dataOutProc58South),
.rd(rdProc68North),
.empty(emptyProc68North),
.dataOut(dataInProc68North));
//FIFO 59 TO 58
fifo fifo_proc59_to_proc58(
.clk(clk),
.resetn(resetn),
.wr(wrProc59West),
.full(fullProc59West),
.dataIn(dataOutProc59West),
.rd(rdProc58East),
.empty(emptyProc58East),
.dataOut(dataInProc58East));
//FIFO 69 TO 59
fifo fifo_proc69_to_proc59(
.clk(clk),
.resetn(resetn),
.wr(wrProc69North),
.full(fullProc69North),
.dataIn(dataOutProc69North),
.rd(rdProc59South),
.empty(emptyProc59South),
.dataOut(dataInProc59South));
//FIFO 60 TO 70
fifo fifo_proc60_to_proc70(
.clk(clk),
.resetn(resetn),
.wr(wrProc60South),
.full(fullProc60South),
.dataIn(dataOutProc60South),
.rd(rdProc70North),
.empty(emptyProc70North),
.dataOut(dataInProc70North));
//FIFO 61 TO 60
fifo fifo_proc61_to_proc60(
.clk(clk),
.resetn(resetn),
.wr(wrProc61West),
.full(fullProc61West),
.dataIn(dataOutProc61West),
.rd(rdProc60East),
.empty(emptyProc60East),
.dataOut(dataInProc60East));
//FIFO 71 TO 61
fifo fifo_proc71_to_proc61(
.clk(clk),
.resetn(resetn),
.wr(wrProc71North),
.full(fullProc71North),
.dataIn(dataOutProc71North),
.rd(rdProc61South),
.empty(emptyProc61South),
.dataOut(dataInProc61South));
//FIFO 61 TO 62
fifo fifo_proc61_to_proc62(
.clk(clk),
.resetn(resetn),
.wr(wrProc61East),
.full(fullProc61East),
.dataIn(dataOutProc61East),
.rd(rdProc62West),
.empty(emptyProc62West),
.dataOut(dataInProc62West));
//FIFO 72 TO 62
fifo fifo_proc72_to_proc62(
.clk(clk),
.resetn(resetn),
.wr(wrProc72North),
.full(fullProc72North),
.dataIn(dataOutProc72North),
.rd(rdProc62South),
.empty(emptyProc62South),
.dataOut(dataInProc62South));
//FIFO 62 TO 72
fifo fifo_proc62_to_proc72(
.clk(clk),
.resetn(resetn),
.wr(wrProc62South),
.full(fullProc62South),
.dataIn(dataOutProc62South),
.rd(rdProc72North),
.empty(emptyProc72North),
.dataOut(dataInProc72North));
//FIFO 62 TO 63
fifo fifo_proc62_to_proc63(
.clk(clk),
.resetn(resetn),
.wr(wrProc62East),
.full(fullProc62East),
.dataIn(dataOutProc62East),
.rd(rdProc63West),
.empty(emptyProc63West),
.dataOut(dataInProc63West));
//FIFO 73 TO 63
fifo fifo_proc73_to_proc63(
.clk(clk),
.resetn(resetn),
.wr(wrProc73North),
.full(fullProc73North),
.dataIn(dataOutProc73North),
.rd(rdProc63South),
.empty(emptyProc63South),
.dataOut(dataInProc63South));
//FIFO 63 TO 73
fifo fifo_proc63_to_proc73(
.clk(clk),
.resetn(resetn),
.wr(wrProc63South),
.full(fullProc63South),
.dataIn(dataOutProc63South),
.rd(rdProc73North),
.empty(emptyProc73North),
.dataOut(dataInProc73North));
//FIFO 63 TO 64
fifo fifo_proc63_to_proc64(
.clk(clk),
.resetn(resetn),
.wr(wrProc63East),
.full(fullProc63East),
.dataIn(dataOutProc63East),
.rd(rdProc64West),
.empty(emptyProc64West),
.dataOut(dataInProc64West));
//FIFO 64 TO 74
fifo fifo_proc64_to_proc74(
.clk(clk),
.resetn(resetn),
.wr(wrProc64South),
.full(fullProc64South),
.dataIn(dataOutProc64South),
.rd(rdProc74North),
.empty(emptyProc74North),
.dataOut(dataInProc74North));
//FIFO 65 TO 64
fifo fifo_proc65_to_proc64(
.clk(clk),
.resetn(resetn),
.wr(wrProc65West),
.full(fullProc65West),
.dataIn(dataOutProc65West),
.rd(rdProc64East),
.empty(emptyProc64East),
.dataOut(dataInProc64East));
//FIFO 64 TO 65
fifo fifo_proc64_to_proc65(
.clk(clk),
.resetn(resetn),
.wr(wrProc64East),
.full(fullProc64East),
.dataIn(dataOutProc64East),
.rd(rdProc65West),
.empty(emptyProc65West),
.dataOut(dataInProc65West));
//FIFO 76 TO 66
fifo fifo_proc76_to_proc66(
.clk(clk),
.resetn(resetn),
.wr(wrProc76North),
.full(fullProc76North),
.dataIn(dataOutProc76North),
.rd(rdProc66South),
.empty(emptyProc66South),
.dataOut(dataInProc66South));
//FIFO 66 TO 67
fifo fifo_proc66_to_proc67(
.clk(clk),
.resetn(resetn),
.wr(wrProc66East),
.full(fullProc66East),
.dataIn(dataOutProc66East),
.rd(rdProc67West),
.empty(emptyProc67West),
.dataOut(dataInProc67West));
//FIFO 67 TO 77
fifo fifo_proc67_to_proc77(
.clk(clk),
.resetn(resetn),
.wr(wrProc67South),
.full(fullProc67South),
.dataIn(dataOutProc67South),
.rd(rdProc77North),
.empty(emptyProc77North),
.dataOut(dataInProc77North));
//FIFO 67 TO 68
fifo fifo_proc67_to_proc68(
.clk(clk),
.resetn(resetn),
.wr(wrProc67East),
.full(fullProc67East),
.dataIn(dataOutProc67East),
.rd(rdProc68West),
.empty(emptyProc68West),
.dataOut(dataInProc68West));
//FIFO 68 TO 78
fifo fifo_proc68_to_proc78(
.clk(clk),
.resetn(resetn),
.wr(wrProc68South),
.full(fullProc68South),
.dataIn(dataOutProc68South),
.rd(rdProc78North),
.empty(emptyProc78North),
.dataOut(dataInProc78North));
//FIFO 68 TO 69
fifo fifo_proc68_to_proc69(
.clk(clk),
.resetn(resetn),
.wr(wrProc68East),
.full(fullProc68East),
.dataIn(dataOutProc68East),
.rd(rdProc69West),
.empty(emptyProc69West),
.dataOut(dataInProc69West));
//FIFO 79 TO 69
fifo fifo_proc79_to_proc69(
.clk(clk),
.resetn(resetn),
.wr(wrProc79North),
.full(fullProc79North),
.dataIn(dataOutProc79North),
.rd(rdProc69South),
.empty(emptyProc69South),
.dataOut(dataInProc69South));
//FIFO 70 TO 80
fifo fifo_proc70_to_proc80(
.clk(clk),
.resetn(resetn),
.wr(wrProc70South),
.full(fullProc70South),
.dataIn(dataOutProc70South),
.rd(rdProc80North),
.empty(emptyProc80North),
.dataOut(dataInProc80North));
//FIFO 81 TO 71
fifo fifo_proc81_to_proc71(
.clk(clk),
.resetn(resetn),
.wr(wrProc81North),
.full(fullProc81North),
.dataIn(dataOutProc81North),
.rd(rdProc71South),
.empty(emptyProc71South),
.dataOut(dataInProc71South));
//FIFO 73 TO 72
fifo fifo_proc73_to_proc72(
.clk(clk),
.resetn(resetn),
.wr(wrProc73West),
.full(fullProc73West),
.dataIn(dataOutProc73West),
.rd(rdProc72East),
.empty(emptyProc72East),
.dataOut(dataInProc72East));
//FIFO 72 TO 73
fifo fifo_proc72_to_proc73(
.clk(clk),
.resetn(resetn),
.wr(wrProc72East),
.full(fullProc72East),
.dataIn(dataOutProc72East),
.rd(rdProc73West),
.empty(emptyProc73West),
.dataOut(dataInProc73West));
//FIFO 73 TO 83
fifo fifo_proc73_to_proc83(
.clk(clk),
.resetn(resetn),
.wr(wrProc73South),
.full(fullProc73South),
.dataIn(dataOutProc73South),
.rd(rdProc83North),
.empty(emptyProc83North),
.dataOut(dataInProc83North));
//FIFO 74 TO 73
fifo fifo_proc74_to_proc73(
.clk(clk),
.resetn(resetn),
.wr(wrProc74West),
.full(fullProc74West),
.dataIn(dataOutProc74West),
.rd(rdProc73East),
.empty(emptyProc73East),
.dataOut(dataInProc73East));
//FIFO 84 TO 74
fifo fifo_proc84_to_proc74(
.clk(clk),
.resetn(resetn),
.wr(wrProc84North),
.full(fullProc84North),
.dataIn(dataOutProc84North),
.rd(rdProc74South),
.empty(emptyProc74South),
.dataOut(dataInProc74South));
//FIFO 74 TO 84
fifo fifo_proc74_to_proc84(
.clk(clk),
.resetn(resetn),
.wr(wrProc74South),
.full(fullProc74South),
.dataIn(dataOutProc74South),
.rd(rdProc84North),
.empty(emptyProc84North),
.dataOut(dataInProc84North));
//FIFO 75 TO 74
fifo fifo_proc75_to_proc74(
.clk(clk),
.resetn(resetn),
.wr(wrProc75West),
.full(fullProc75West),
.dataIn(dataOutProc75West),
.rd(rdProc74East),
.empty(emptyProc74East),
.dataOut(dataInProc74East));
//FIFO 74 TO 75
fifo fifo_proc74_to_proc75(
.clk(clk),
.resetn(resetn),
.wr(wrProc74East),
.full(fullProc74East),
.dataIn(dataOutProc74East),
.rd(rdProc75West),
.empty(emptyProc75West),
.dataOut(dataInProc75West));
//FIFO 76 TO 75
fifo fifo_proc76_to_proc75(
.clk(clk),
.resetn(resetn),
.wr(wrProc76West),
.full(fullProc76West),
.dataIn(dataOutProc76West),
.rd(rdProc75East),
.empty(emptyProc75East),
.dataOut(dataInProc75East));
//FIFO 75 TO 76
fifo fifo_proc75_to_proc76(
.clk(clk),
.resetn(resetn),
.wr(wrProc75East),
.full(fullProc75East),
.dataIn(dataOutProc75East),
.rd(rdProc76West),
.empty(emptyProc76West),
.dataOut(dataInProc76West));
//FIFO 86 TO 76
fifo fifo_proc86_to_proc76(
.clk(clk),
.resetn(resetn),
.wr(wrProc86North),
.full(fullProc86North),
.dataIn(dataOutProc86North),
.rd(rdProc76South),
.empty(emptyProc76South),
.dataOut(dataInProc76South));
//FIFO 77 TO 87
fifo fifo_proc77_to_proc87(
.clk(clk),
.resetn(resetn),
.wr(wrProc77South),
.full(fullProc77South),
.dataIn(dataOutProc77South),
.rd(rdProc87North),
.empty(emptyProc87North),
.dataOut(dataInProc87North));
//FIFO 78 TO 77
fifo fifo_proc78_to_proc77(
.clk(clk),
.resetn(resetn),
.wr(wrProc78West),
.full(fullProc78West),
.dataIn(dataOutProc78West),
.rd(rdProc77East),
.empty(emptyProc77East),
.dataOut(dataInProc77East));
//FIFO 89 TO 79
fifo fifo_proc89_to_proc79(
.clk(clk),
.resetn(resetn),
.wr(wrProc89North),
.full(fullProc89North),
.dataIn(dataOutProc89North),
.rd(rdProc79South),
.empty(emptyProc79South),
.dataOut(dataInProc79South));
//FIFO 80 TO 81
fifo fifo_proc80_to_proc81(
.clk(clk),
.resetn(resetn),
.wr(wrProc80East),
.full(fullProc80East),
.dataIn(dataOutProc80East),
.rd(rdProc81West),
.empty(emptyProc81West),
.dataOut(dataInProc81West));
//FIFO 82 TO 81
fifo fifo_proc82_to_proc81(
.clk(clk),
.resetn(resetn),
.wr(wrProc82West),
.full(fullProc82West),
.dataIn(dataOutProc82West),
.rd(rdProc81East),
.empty(emptyProc81East),
.dataOut(dataInProc81East));
//FIFO 81 TO 82
fifo fifo_proc81_to_proc82(
.clk(clk),
.resetn(resetn),
.wr(wrProc81East),
.full(fullProc81East),
.dataIn(dataOutProc81East),
.rd(rdProc82West),
.empty(emptyProc82West),
.dataOut(dataInProc82West));
//FIFO 83 TO 82
fifo fifo_proc83_to_proc82(
.clk(clk),
.resetn(resetn),
.wr(wrProc83West),
.full(fullProc83West),
.dataIn(dataOutProc83West),
.rd(rdProc82East),
.empty(emptyProc82East),
.dataOut(dataInProc82East));
//FIFO 82 TO 83
fifo fifo_proc82_to_proc83(
.clk(clk),
.resetn(resetn),
.wr(wrProc82East),
.full(fullProc82East),
.dataIn(dataOutProc82East),
.rd(rdProc83West),
.empty(emptyProc83West),
.dataOut(dataInProc83West));
//FIFO 84 TO 83
fifo fifo_proc84_to_proc83(
.clk(clk),
.resetn(resetn),
.wr(wrProc84West),
.full(fullProc84West),
.dataIn(dataOutProc84West),
.rd(rdProc83East),
.empty(emptyProc83East),
.dataOut(dataInProc83East));
//FIFO 83 TO 84
fifo fifo_proc83_to_proc84(
.clk(clk),
.resetn(resetn),
.wr(wrProc83East),
.full(fullProc83East),
.dataIn(dataOutProc83East),
.rd(rdProc84West),
.empty(emptyProc84West),
.dataOut(dataInProc84West));
//FIFO 85 TO 84
fifo fifo_proc85_to_proc84(
.clk(clk),
.resetn(resetn),
.wr(wrProc85West),
.full(fullProc85West),
.dataIn(dataOutProc85West),
.rd(rdProc84East),
.empty(emptyProc84East),
.dataOut(dataInProc84East));
//FIFO 84 TO 85
fifo fifo_proc84_to_proc85(
.clk(clk),
.resetn(resetn),
.wr(wrProc84East),
.full(fullProc84East),
.dataIn(dataOutProc84East),
.rd(rdProc85West),
.empty(emptyProc85West),
.dataOut(dataInProc85West));
//FIFO 87 TO 86
fifo fifo_proc87_to_proc86(
.clk(clk),
.resetn(resetn),
.wr(wrProc87West),
.full(fullProc87West),
.dataIn(dataOutProc87West),
.rd(rdProc86East),
.empty(emptyProc86East),
.dataOut(dataInProc86East));
//FIFO 87 TO 88
fifo fifo_proc87_to_proc88(
.clk(clk),
.resetn(resetn),
.wr(wrProc87East),
.full(fullProc87East),
.dataIn(dataOutProc87East),
.rd(rdProc88West),
.empty(emptyProc88West),
.dataOut(dataInProc88West));
//FIFO 88 TO 89
fifo fifo_proc88_to_proc89(
.clk(clk),
.resetn(resetn),
.wr(wrProc88East),
.full(fullProc88East),
.dataIn(dataOutProc88East),
.rd(rdProc89West),
.empty(emptyProc89West),
.dataOut(dataInProc89West));
/**************** Boot loader ********************/
/*******Boot up each processor one by one*********/
always@(posedge clk)
begin
case(processor_select)
0: begin
boot_iwe0 = ~resetn;
boot_dwe0 = ~resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
boot_iwe50 = resetn;
boot_dwe50 = resetn;
boot_iwe51 = resetn;
boot_dwe51 = resetn;
boot_iwe52 = resetn;
boot_dwe52 = resetn;
boot_iwe53 = resetn;
boot_dwe53 = resetn;
boot_iwe54 = resetn;
boot_dwe54 = resetn;
boot_iwe55 = resetn;
boot_dwe55 = resetn;
boot_iwe56 = resetn;
boot_dwe56 = resetn;
boot_iwe57 = resetn;
boot_dwe57 = resetn;
boot_iwe58 = resetn;
boot_dwe58 = resetn;
boot_iwe59 = resetn;
boot_dwe59 = resetn;
boot_iwe60 = resetn;
boot_dwe60 = resetn;
boot_iwe61 = resetn;
boot_dwe61 = resetn;
boot_iwe62 = resetn;
boot_dwe62 = resetn;
boot_iwe63 = resetn;
boot_dwe63 = resetn;
boot_iwe64 = resetn;
boot_dwe64 = resetn;
boot_iwe65 = resetn;
boot_dwe65 = resetn;
boot_iwe66 = resetn;
boot_dwe66 = resetn;
boot_iwe67 = resetn;
boot_dwe67 = resetn;
boot_iwe68 = resetn;
boot_dwe68 = resetn;
boot_iwe69 = resetn;
boot_dwe69 = resetn;
boot_iwe70 = resetn;
boot_dwe70 = resetn;
boot_iwe71 = resetn;
boot_dwe71 = resetn;
boot_iwe72 = resetn;
boot_dwe72 = resetn;
boot_iwe73 = resetn;
boot_dwe73 = resetn;
boot_iwe74 = resetn;
boot_dwe74 = resetn;
boot_iwe75 = resetn;
boot_dwe75 = resetn;
boot_iwe76 = resetn;
boot_dwe76 = resetn;
boot_iwe77 = resetn;
boot_dwe77 = resetn;
boot_iwe78 = resetn;
boot_dwe78 = resetn;
boot_iwe79 = resetn;
boot_dwe79 = resetn;
boot_iwe80 = resetn;
boot_dwe80 = resetn;
boot_iwe81 = resetn;
boot_dwe81 = resetn;
boot_iwe82 = resetn;
boot_dwe82 = resetn;
boot_iwe83 = resetn;
boot_dwe83 = resetn;
boot_iwe84 = resetn;
boot_dwe84 = resetn;
boot_iwe85 = resetn;
boot_dwe85 = resetn;
boot_iwe86 = resetn;
boot_dwe86 = resetn;
boot_iwe87 = resetn;
boot_dwe87 = resetn;
boot_iwe88 = resetn;
boot_dwe88 = resetn;
boot_iwe89 = resetn;
boot_dwe89 = resetn;
end
1: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = ~resetn;
boot_dwe1 = ~resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
boot_iwe50 = resetn;
boot_dwe50 = resetn;
boot_iwe51 = resetn;
boot_dwe51 = resetn;
boot_iwe52 = resetn;
boot_dwe52 = resetn;
boot_iwe53 = resetn;
boot_dwe53 = resetn;
boot_iwe54 = resetn;
boot_dwe54 = resetn;
boot_iwe55 = resetn;
boot_dwe55 = resetn;
boot_iwe56 = resetn;
boot_dwe56 = resetn;
boot_iwe57 = resetn;
boot_dwe57 = resetn;
boot_iwe58 = resetn;
boot_dwe58 = resetn;
boot_iwe59 = resetn;
boot_dwe59 = resetn;
boot_iwe60 = resetn;
boot_dwe60 = resetn;
boot_iwe61 = resetn;
boot_dwe61 = resetn;
boot_iwe62 = resetn;
boot_dwe62 = resetn;
boot_iwe63 = resetn;
boot_dwe63 = resetn;
boot_iwe64 = resetn;
boot_dwe64 = resetn;
boot_iwe65 = resetn;
boot_dwe65 = resetn;
boot_iwe66 = resetn;
boot_dwe66 = resetn;
boot_iwe67 = resetn;
boot_dwe67 = resetn;
boot_iwe68 = resetn;
boot_dwe68 = resetn;
boot_iwe69 = resetn;
boot_dwe69 = resetn;
boot_iwe70 = resetn;
boot_dwe70 = resetn;
boot_iwe71 = resetn;
boot_dwe71 = resetn;
boot_iwe72 = resetn;
boot_dwe72 = resetn;
boot_iwe73 = resetn;
boot_dwe73 = resetn;
boot_iwe74 = resetn;
boot_dwe74 = resetn;
boot_iwe75 = resetn;
boot_dwe75 = resetn;
boot_iwe76 = resetn;
boot_dwe76 = resetn;
boot_iwe77 = resetn;
boot_dwe77 = resetn;
boot_iwe78 = resetn;
boot_dwe78 = resetn;
boot_iwe79 = resetn;
boot_dwe79 = resetn;
boot_iwe80 = resetn;
boot_dwe80 = resetn;
boot_iwe81 = resetn;
boot_dwe81 = resetn;
boot_iwe82 = resetn;
boot_dwe82 = resetn;
boot_iwe83 = resetn;
boot_dwe83 = resetn;
boot_iwe84 = resetn;
boot_dwe84 = resetn;
boot_iwe85 = resetn;
boot_dwe85 = resetn;
boot_iwe86 = resetn;
boot_dwe86 = resetn;
boot_iwe87 = resetn;
boot_dwe87 = resetn;
boot_iwe88 = resetn;
boot_dwe88 = resetn;
boot_iwe89 = resetn;
boot_dwe89 = resetn;
end
2: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = ~resetn;
boot_dwe2 = ~resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
boot_iwe50 = resetn;
boot_dwe50 = resetn;
boot_iwe51 = resetn;
boot_dwe51 = resetn;
boot_iwe52 = resetn;
boot_dwe52 = resetn;
boot_iwe53 = resetn;
boot_dwe53 = resetn;
boot_iwe54 = resetn;
boot_dwe54 = resetn;
boot_iwe55 = resetn;
boot_dwe55 = resetn;
boot_iwe56 = resetn;
boot_dwe56 = resetn;
boot_iwe57 = resetn;
boot_dwe57 = resetn;
boot_iwe58 = resetn;
boot_dwe58 = resetn;
boot_iwe59 = resetn;
boot_dwe59 = resetn;
boot_iwe60 = resetn;
boot_dwe60 = resetn;
boot_iwe61 = resetn;
boot_dwe61 = resetn;
boot_iwe62 = resetn;
boot_dwe62 = resetn;
boot_iwe63 = resetn;
boot_dwe63 = resetn;
boot_iwe64 = resetn;
boot_dwe64 = resetn;
boot_iwe65 = resetn;
boot_dwe65 = resetn;
boot_iwe66 = resetn;
boot_dwe66 = resetn;
boot_iwe67 = resetn;
boot_dwe67 = resetn;
boot_iwe68 = resetn;
boot_dwe68 = resetn;
boot_iwe69 = resetn;
boot_dwe69 = resetn;
boot_iwe70 = resetn;
boot_dwe70 = resetn;
boot_iwe71 = resetn;
boot_dwe71 = resetn;
boot_iwe72 = resetn;
boot_dwe72 = resetn;
boot_iwe73 = resetn;
boot_dwe73 = resetn;
boot_iwe74 = resetn;
boot_dwe74 = resetn;
boot_iwe75 = resetn;
boot_dwe75 = resetn;
boot_iwe76 = resetn;
boot_dwe76 = resetn;
boot_iwe77 = resetn;
boot_dwe77 = resetn;
boot_iwe78 = resetn;
boot_dwe78 = resetn;
boot_iwe79 = resetn;
boot_dwe79 = resetn;
boot_iwe80 = resetn;
boot_dwe80 = resetn;
boot_iwe81 = resetn;
boot_dwe81 = resetn;
boot_iwe82 = resetn;
boot_dwe82 = resetn;
boot_iwe83 = resetn;
boot_dwe83 = resetn;
boot_iwe84 = resetn;
boot_dwe84 = resetn;
boot_iwe85 = resetn;
boot_dwe85 = resetn;
boot_iwe86 = resetn;
boot_dwe86 = resetn;
boot_iwe87 = resetn;
boot_dwe87 = resetn;
boot_iwe88 = resetn;
boot_dwe88 = resetn;
boot_iwe89 = resetn;
boot_dwe89 = resetn;
end
3: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = ~resetn;
boot_dwe3 = ~resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
boot_iwe50 = resetn;
boot_dwe50 = resetn;
boot_iwe51 = resetn;
boot_dwe51 = resetn;
boot_iwe52 = resetn;
boot_dwe52 = resetn;
boot_iwe53 = resetn;
boot_dwe53 = resetn;
boot_iwe54 = resetn;
boot_dwe54 = resetn;
boot_iwe55 = resetn;
boot_dwe55 = resetn;
boot_iwe56 = resetn;
boot_dwe56 = resetn;
boot_iwe57 = resetn;
boot_dwe57 = resetn;
boot_iwe58 = resetn;
boot_dwe58 = resetn;
boot_iwe59 = resetn;
boot_dwe59 = resetn;
boot_iwe60 = resetn;
boot_dwe60 = resetn;
boot_iwe61 = resetn;
boot_dwe61 = resetn;
boot_iwe62 = resetn;
boot_dwe62 = resetn;
boot_iwe63 = resetn;
boot_dwe63 = resetn;
boot_iwe64 = resetn;
boot_dwe64 = resetn;
boot_iwe65 = resetn;
boot_dwe65 = resetn;
boot_iwe66 = resetn;
boot_dwe66 = resetn;
boot_iwe67 = resetn;
boot_dwe67 = resetn;
boot_iwe68 = resetn;
boot_dwe68 = resetn;
boot_iwe69 = resetn;
boot_dwe69 = resetn;
boot_iwe70 = resetn;
boot_dwe70 = resetn;
boot_iwe71 = resetn;
boot_dwe71 = resetn;
boot_iwe72 = resetn;
boot_dwe72 = resetn;
boot_iwe73 = resetn;
boot_dwe73 = resetn;
boot_iwe74 = resetn;
boot_dwe74 = resetn;
boot_iwe75 = resetn;
boot_dwe75 = resetn;
boot_iwe76 = resetn;
boot_dwe76 = resetn;
boot_iwe77 = resetn;
boot_dwe77 = resetn;
boot_iwe78 = resetn;
boot_dwe78 = resetn;
boot_iwe79 = resetn;
boot_dwe79 = resetn;
boot_iwe80 = resetn;
boot_dwe80 = resetn;
boot_iwe81 = resetn;
boot_dwe81 = resetn;
boot_iwe82 = resetn;
boot_dwe82 = resetn;
boot_iwe83 = resetn;
boot_dwe83 = resetn;
boot_iwe84 = resetn;
boot_dwe84 = resetn;
boot_iwe85 = resetn;
boot_dwe85 = resetn;
boot_iwe86 = resetn;
boot_dwe86 = resetn;
boot_iwe87 = resetn;
boot_dwe87 = resetn;
boot_iwe88 = resetn;
boot_dwe88 = resetn;
boot_iwe89 = resetn;
boot_dwe89 = resetn;
end
4: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = ~resetn;
boot_dwe4 = ~resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
boot_iwe50 = resetn;
boot_dwe50 = resetn;
boot_iwe51 = resetn;
boot_dwe51 = resetn;
boot_iwe52 = resetn;
boot_dwe52 = resetn;
boot_iwe53 = resetn;
boot_dwe53 = resetn;
boot_iwe54 = resetn;
boot_dwe54 = resetn;
boot_iwe55 = resetn;
boot_dwe55 = resetn;
boot_iwe56 = resetn;
boot_dwe56 = resetn;
boot_iwe57 = resetn;
boot_dwe57 = resetn;
boot_iwe58 = resetn;
boot_dwe58 = resetn;
boot_iwe59 = resetn;
boot_dwe59 = resetn;
boot_iwe60 = resetn;
boot_dwe60 = resetn;
boot_iwe61 = resetn;
boot_dwe61 = resetn;
boot_iwe62 = resetn;
boot_dwe62 = resetn;
boot_iwe63 = resetn;
boot_dwe63 = resetn;
boot_iwe64 = resetn;
boot_dwe64 = resetn;
boot_iwe65 = resetn;
boot_dwe65 = resetn;
boot_iwe66 = resetn;
boot_dwe66 = resetn;
boot_iwe67 = resetn;
boot_dwe67 = resetn;
boot_iwe68 = resetn;
boot_dwe68 = resetn;
boot_iwe69 = resetn;
boot_dwe69 = resetn;
boot_iwe70 = resetn;
boot_dwe70 = resetn;
boot_iwe71 = resetn;
boot_dwe71 = resetn;
boot_iwe72 = resetn;
boot_dwe72 = resetn;
boot_iwe73 = resetn;
boot_dwe73 = resetn;
boot_iwe74 = resetn;
boot_dwe74 = resetn;
boot_iwe75 = resetn;
boot_dwe75 = resetn;
boot_iwe76 = resetn;
boot_dwe76 = resetn;
boot_iwe77 = resetn;
boot_dwe77 = resetn;
boot_iwe78 = resetn;
boot_dwe78 = resetn;
boot_iwe79 = resetn;
boot_dwe79 = resetn;
boot_iwe80 = resetn;
boot_dwe80 = resetn;
boot_iwe81 = resetn;
boot_dwe81 = resetn;
boot_iwe82 = resetn;
boot_dwe82 = resetn;
boot_iwe83 = resetn;
boot_dwe83 = resetn;
boot_iwe84 = resetn;
boot_dwe84 = resetn;
boot_iwe85 = resetn;
boot_dwe85 = resetn;
boot_iwe86 = resetn;
boot_dwe86 = resetn;
boot_iwe87 = resetn;
boot_dwe87 = resetn;
boot_iwe88 = resetn;
boot_dwe88 = resetn;
boot_iwe89 = resetn;
boot_dwe89 = resetn;
end
5: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = ~resetn;
boot_dwe5 = ~resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
boot_iwe50 = resetn;
boot_dwe50 = resetn;
boot_iwe51 = resetn;
boot_dwe51 = resetn;
boot_iwe52 = resetn;
boot_dwe52 = resetn;
boot_iwe53 = resetn;
boot_dwe53 = resetn;
boot_iwe54 = resetn;
boot_dwe54 = resetn;
boot_iwe55 = resetn;
boot_dwe55 = resetn;
boot_iwe56 = resetn;
boot_dwe56 = resetn;
boot_iwe57 = resetn;
boot_dwe57 = resetn;
boot_iwe58 = resetn;
boot_dwe58 = resetn;
boot_iwe59 = resetn;
boot_dwe59 = resetn;
boot_iwe60 = resetn;
boot_dwe60 = resetn;
boot_iwe61 = resetn;
boot_dwe61 = resetn;
boot_iwe62 = resetn;
boot_dwe62 = resetn;
boot_iwe63 = resetn;
boot_dwe63 = resetn;
boot_iwe64 = resetn;
boot_dwe64 = resetn;
boot_iwe65 = resetn;
boot_dwe65 = resetn;
boot_iwe66 = resetn;
boot_dwe66 = resetn;
boot_iwe67 = resetn;
boot_dwe67 = resetn;
boot_iwe68 = resetn;
boot_dwe68 = resetn;
boot_iwe69 = resetn;
boot_dwe69 = resetn;
boot_iwe70 = resetn;
boot_dwe70 = resetn;
boot_iwe71 = resetn;
boot_dwe71 = resetn;
boot_iwe72 = resetn;
boot_dwe72 = resetn;
boot_iwe73 = resetn;
boot_dwe73 = resetn;
boot_iwe74 = resetn;
boot_dwe74 = resetn;
boot_iwe75 = resetn;
boot_dwe75 = resetn;
boot_iwe76 = resetn;
boot_dwe76 = resetn;
boot_iwe77 = resetn;
boot_dwe77 = resetn;
boot_iwe78 = resetn;
boot_dwe78 = resetn;
boot_iwe79 = resetn;
boot_dwe79 = resetn;
boot_iwe80 = resetn;
boot_dwe80 = resetn;
boot_iwe81 = resetn;
boot_dwe81 = resetn;
boot_iwe82 = resetn;
boot_dwe82 = resetn;
boot_iwe83 = resetn;
boot_dwe83 = resetn;
boot_iwe84 = resetn;
boot_dwe84 = resetn;
boot_iwe85 = resetn;
boot_dwe85 = resetn;
boot_iwe86 = resetn;
boot_dwe86 = resetn;
boot_iwe87 = resetn;
boot_dwe87 = resetn;
boot_iwe88 = resetn;
boot_dwe88 = resetn;
boot_iwe89 = resetn;
boot_dwe89 = resetn;
end
6: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = ~resetn;
boot_dwe6 = ~resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
boot_iwe50 = resetn;
boot_dwe50 = resetn;
boot_iwe51 = resetn;
boot_dwe51 = resetn;
boot_iwe52 = resetn;
boot_dwe52 = resetn;
boot_iwe53 = resetn;
boot_dwe53 = resetn;
boot_iwe54 = resetn;
boot_dwe54 = resetn;
boot_iwe55 = resetn;
boot_dwe55 = resetn;
boot_iwe56 = resetn;
boot_dwe56 = resetn;
boot_iwe57 = resetn;
boot_dwe57 = resetn;
boot_iwe58 = resetn;
boot_dwe58 = resetn;
boot_iwe59 = resetn;
boot_dwe59 = resetn;
boot_iwe60 = resetn;
boot_dwe60 = resetn;
boot_iwe61 = resetn;
boot_dwe61 = resetn;
boot_iwe62 = resetn;
boot_dwe62 = resetn;
boot_iwe63 = resetn;
boot_dwe63 = resetn;
boot_iwe64 = resetn;
boot_dwe64 = resetn;
boot_iwe65 = resetn;
boot_dwe65 = resetn;
boot_iwe66 = resetn;
boot_dwe66 = resetn;
boot_iwe67 = resetn;
boot_dwe67 = resetn;
boot_iwe68 = resetn;
boot_dwe68 = resetn;
boot_iwe69 = resetn;
boot_dwe69 = resetn;
boot_iwe70 = resetn;
boot_dwe70 = resetn;
boot_iwe71 = resetn;
boot_dwe71 = resetn;
boot_iwe72 = resetn;
boot_dwe72 = resetn;
boot_iwe73 = resetn;
boot_dwe73 = resetn;
boot_iwe74 = resetn;
boot_dwe74 = resetn;
boot_iwe75 = resetn;
boot_dwe75 = resetn;
boot_iwe76 = resetn;
boot_dwe76 = resetn;
boot_iwe77 = resetn;
boot_dwe77 = resetn;
boot_iwe78 = resetn;
boot_dwe78 = resetn;
boot_iwe79 = resetn;
boot_dwe79 = resetn;
boot_iwe80 = resetn;
boot_dwe80 = resetn;
boot_iwe81 = resetn;
boot_dwe81 = resetn;
boot_iwe82 = resetn;
boot_dwe82 = resetn;
boot_iwe83 = resetn;
boot_dwe83 = resetn;
boot_iwe84 = resetn;
boot_dwe84 = resetn;
boot_iwe85 = resetn;
boot_dwe85 = resetn;
boot_iwe86 = resetn;
boot_dwe86 = resetn;
boot_iwe87 = resetn;
boot_dwe87 = resetn;
boot_iwe88 = resetn;
boot_dwe88 = resetn;
boot_iwe89 = resetn;
boot_dwe89 = resetn;
end
7: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = ~resetn;
boot_dwe7 = ~resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
boot_iwe50 = resetn;
boot_dwe50 = resetn;
boot_iwe51 = resetn;
boot_dwe51 = resetn;
boot_iwe52 = resetn;
boot_dwe52 = resetn;
boot_iwe53 = resetn;
boot_dwe53 = resetn;
boot_iwe54 = resetn;
boot_dwe54 = resetn;
boot_iwe55 = resetn;
boot_dwe55 = resetn;
boot_iwe56 = resetn;
boot_dwe56 = resetn;
boot_iwe57 = resetn;
boot_dwe57 = resetn;
boot_iwe58 = resetn;
boot_dwe58 = resetn;
boot_iwe59 = resetn;
boot_dwe59 = resetn;
boot_iwe60 = resetn;
boot_dwe60 = resetn;
boot_iwe61 = resetn;
boot_dwe61 = resetn;
boot_iwe62 = resetn;
boot_dwe62 = resetn;
boot_iwe63 = resetn;
boot_dwe63 = resetn;
boot_iwe64 = resetn;
boot_dwe64 = resetn;
boot_iwe65 = resetn;
boot_dwe65 = resetn;
boot_iwe66 = resetn;
boot_dwe66 = resetn;
boot_iwe67 = resetn;
boot_dwe67 = resetn;
boot_iwe68 = resetn;
boot_dwe68 = resetn;
boot_iwe69 = resetn;
boot_dwe69 = resetn;
boot_iwe70 = resetn;
boot_dwe70 = resetn;
boot_iwe71 = resetn;
boot_dwe71 = resetn;
boot_iwe72 = resetn;
boot_dwe72 = resetn;
boot_iwe73 = resetn;
boot_dwe73 = resetn;
boot_iwe74 = resetn;
boot_dwe74 = resetn;
boot_iwe75 = resetn;
boot_dwe75 = resetn;
boot_iwe76 = resetn;
boot_dwe76 = resetn;
boot_iwe77 = resetn;
boot_dwe77 = resetn;
boot_iwe78 = resetn;
boot_dwe78 = resetn;
boot_iwe79 = resetn;
boot_dwe79 = resetn;
boot_iwe80 = resetn;
boot_dwe80 = resetn;
boot_iwe81 = resetn;
boot_dwe81 = resetn;
boot_iwe82 = resetn;
boot_dwe82 = resetn;
boot_iwe83 = resetn;
boot_dwe83 = resetn;
boot_iwe84 = resetn;
boot_dwe84 = resetn;
boot_iwe85 = resetn;
boot_dwe85 = resetn;
boot_iwe86 = resetn;
boot_dwe86 = resetn;
boot_iwe87 = resetn;
boot_dwe87 = resetn;
boot_iwe88 = resetn;
boot_dwe88 = resetn;
boot_iwe89 = resetn;
boot_dwe89 = resetn;
end
8: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = ~resetn;
boot_dwe8 = ~resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
boot_iwe50 = resetn;
boot_dwe50 = resetn;
boot_iwe51 = resetn;
boot_dwe51 = resetn;
boot_iwe52 = resetn;
boot_dwe52 = resetn;
boot_iwe53 = resetn;
boot_dwe53 = resetn;
boot_iwe54 = resetn;
boot_dwe54 = resetn;
boot_iwe55 = resetn;
boot_dwe55 = resetn;
boot_iwe56 = resetn;
boot_dwe56 = resetn;
boot_iwe57 = resetn;
boot_dwe57 = resetn;
boot_iwe58 = resetn;
boot_dwe58 = resetn;
boot_iwe59 = resetn;
boot_dwe59 = resetn;
boot_iwe60 = resetn;
boot_dwe60 = resetn;
boot_iwe61 = resetn;
boot_dwe61 = resetn;
boot_iwe62 = resetn;
boot_dwe62 = resetn;
boot_iwe63 = resetn;
boot_dwe63 = resetn;
boot_iwe64 = resetn;
boot_dwe64 = resetn;
boot_iwe65 = resetn;
boot_dwe65 = resetn;
boot_iwe66 = resetn;
boot_dwe66 = resetn;
boot_iwe67 = resetn;
boot_dwe67 = resetn;
boot_iwe68 = resetn;
boot_dwe68 = resetn;
boot_iwe69 = resetn;
boot_dwe69 = resetn;
boot_iwe70 = resetn;
boot_dwe70 = resetn;
boot_iwe71 = resetn;
boot_dwe71 = resetn;
boot_iwe72 = resetn;
boot_dwe72 = resetn;
boot_iwe73 = resetn;
boot_dwe73 = resetn;
boot_iwe74 = resetn;
boot_dwe74 = resetn;
boot_iwe75 = resetn;
boot_dwe75 = resetn;
boot_iwe76 = resetn;
boot_dwe76 = resetn;
boot_iwe77 = resetn;
boot_dwe77 = resetn;
boot_iwe78 = resetn;
boot_dwe78 = resetn;
boot_iwe79 = resetn;
boot_dwe79 = resetn;
boot_iwe80 = resetn;
boot_dwe80 = resetn;
boot_iwe81 = resetn;
boot_dwe81 = resetn;
boot_iwe82 = resetn;
boot_dwe82 = resetn;
boot_iwe83 = resetn;
boot_dwe83 = resetn;
boot_iwe84 = resetn;
boot_dwe84 = resetn;
boot_iwe85 = resetn;
boot_dwe85 = resetn;
boot_iwe86 = resetn;
boot_dwe86 = resetn;
boot_iwe87 = resetn;
boot_dwe87 = resetn;
boot_iwe88 = resetn;
boot_dwe88 = resetn;
boot_iwe89 = resetn;
boot_dwe89 = resetn;
end
9: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = ~resetn;
boot_dwe9 = ~resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
boot_iwe50 = resetn;
boot_dwe50 = resetn;
boot_iwe51 = resetn;
boot_dwe51 = resetn;
boot_iwe52 = resetn;
boot_dwe52 = resetn;
boot_iwe53 = resetn;
boot_dwe53 = resetn;
boot_iwe54 = resetn;
boot_dwe54 = resetn;
boot_iwe55 = resetn;
boot_dwe55 = resetn;
boot_iwe56 = resetn;
boot_dwe56 = resetn;
boot_iwe57 = resetn;
boot_dwe57 = resetn;
boot_iwe58 = resetn;
boot_dwe58 = resetn;
boot_iwe59 = resetn;
boot_dwe59 = resetn;
boot_iwe60 = resetn;
boot_dwe60 = resetn;
boot_iwe61 = resetn;
boot_dwe61 = resetn;
boot_iwe62 = resetn;
boot_dwe62 = resetn;
boot_iwe63 = resetn;
boot_dwe63 = resetn;
boot_iwe64 = resetn;
boot_dwe64 = resetn;
boot_iwe65 = resetn;
boot_dwe65 = resetn;
boot_iwe66 = resetn;
boot_dwe66 = resetn;
boot_iwe67 = resetn;
boot_dwe67 = resetn;
boot_iwe68 = resetn;
boot_dwe68 = resetn;
boot_iwe69 = resetn;
boot_dwe69 = resetn;
boot_iwe70 = resetn;
boot_dwe70 = resetn;
boot_iwe71 = resetn;
boot_dwe71 = resetn;
boot_iwe72 = resetn;
boot_dwe72 = resetn;
boot_iwe73 = resetn;
boot_dwe73 = resetn;
boot_iwe74 = resetn;
boot_dwe74 = resetn;
boot_iwe75 = resetn;
boot_dwe75 = resetn;
boot_iwe76 = resetn;
boot_dwe76 = resetn;
boot_iwe77 = resetn;
boot_dwe77 = resetn;
boot_iwe78 = resetn;
boot_dwe78 = resetn;
boot_iwe79 = resetn;
boot_dwe79 = resetn;
boot_iwe80 = resetn;
boot_dwe80 = resetn;
boot_iwe81 = resetn;
boot_dwe81 = resetn;
boot_iwe82 = resetn;
boot_dwe82 = resetn;
boot_iwe83 = resetn;
boot_dwe83 = resetn;
boot_iwe84 = resetn;
boot_dwe84 = resetn;
boot_iwe85 = resetn;
boot_dwe85 = resetn;
boot_iwe86 = resetn;
boot_dwe86 = resetn;
boot_iwe87 = resetn;
boot_dwe87 = resetn;
boot_iwe88 = resetn;
boot_dwe88 = resetn;
boot_iwe89 = resetn;
boot_dwe89 = resetn;
end
10: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = ~resetn;
boot_dwe10 = ~resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
boot_iwe50 = resetn;
boot_dwe50 = resetn;
boot_iwe51 = resetn;
boot_dwe51 = resetn;
boot_iwe52 = resetn;
boot_dwe52 = resetn;
boot_iwe53 = resetn;
boot_dwe53 = resetn;
boot_iwe54 = resetn;
boot_dwe54 = resetn;
boot_iwe55 = resetn;
boot_dwe55 = resetn;
boot_iwe56 = resetn;
boot_dwe56 = resetn;
boot_iwe57 = resetn;
boot_dwe57 = resetn;
boot_iwe58 = resetn;
boot_dwe58 = resetn;
boot_iwe59 = resetn;
boot_dwe59 = resetn;
boot_iwe60 = resetn;
boot_dwe60 = resetn;
boot_iwe61 = resetn;
boot_dwe61 = resetn;
boot_iwe62 = resetn;
boot_dwe62 = resetn;
boot_iwe63 = resetn;
boot_dwe63 = resetn;
boot_iwe64 = resetn;
boot_dwe64 = resetn;
boot_iwe65 = resetn;
boot_dwe65 = resetn;
boot_iwe66 = resetn;
boot_dwe66 = resetn;
boot_iwe67 = resetn;
boot_dwe67 = resetn;
boot_iwe68 = resetn;
boot_dwe68 = resetn;
boot_iwe69 = resetn;
boot_dwe69 = resetn;
boot_iwe70 = resetn;
boot_dwe70 = resetn;
boot_iwe71 = resetn;
boot_dwe71 = resetn;
boot_iwe72 = resetn;
boot_dwe72 = resetn;
boot_iwe73 = resetn;
boot_dwe73 = resetn;
boot_iwe74 = resetn;
boot_dwe74 = resetn;
boot_iwe75 = resetn;
boot_dwe75 = resetn;
boot_iwe76 = resetn;
boot_dwe76 = resetn;
boot_iwe77 = resetn;
boot_dwe77 = resetn;
boot_iwe78 = resetn;
boot_dwe78 = resetn;
boot_iwe79 = resetn;
boot_dwe79 = resetn;
boot_iwe80 = resetn;
boot_dwe80 = resetn;
boot_iwe81 = resetn;
boot_dwe81 = resetn;
boot_iwe82 = resetn;
boot_dwe82 = resetn;
boot_iwe83 = resetn;
boot_dwe83 = resetn;
boot_iwe84 = resetn;
boot_dwe84 = resetn;
boot_iwe85 = resetn;
boot_dwe85 = resetn;
boot_iwe86 = resetn;
boot_dwe86 = resetn;
boot_iwe87 = resetn;
boot_dwe87 = resetn;
boot_iwe88 = resetn;
boot_dwe88 = resetn;
boot_iwe89 = resetn;
boot_dwe89 = resetn;
end
11: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = ~resetn;
boot_dwe11 = ~resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
boot_iwe50 = resetn;
boot_dwe50 = resetn;
boot_iwe51 = resetn;
boot_dwe51 = resetn;
boot_iwe52 = resetn;
boot_dwe52 = resetn;
boot_iwe53 = resetn;
boot_dwe53 = resetn;
boot_iwe54 = resetn;
boot_dwe54 = resetn;
boot_iwe55 = resetn;
boot_dwe55 = resetn;
boot_iwe56 = resetn;
boot_dwe56 = resetn;
boot_iwe57 = resetn;
boot_dwe57 = resetn;
boot_iwe58 = resetn;
boot_dwe58 = resetn;
boot_iwe59 = resetn;
boot_dwe59 = resetn;
boot_iwe60 = resetn;
boot_dwe60 = resetn;
boot_iwe61 = resetn;
boot_dwe61 = resetn;
boot_iwe62 = resetn;
boot_dwe62 = resetn;
boot_iwe63 = resetn;
boot_dwe63 = resetn;
boot_iwe64 = resetn;
boot_dwe64 = resetn;
boot_iwe65 = resetn;
boot_dwe65 = resetn;
boot_iwe66 = resetn;
boot_dwe66 = resetn;
boot_iwe67 = resetn;
boot_dwe67 = resetn;
boot_iwe68 = resetn;
boot_dwe68 = resetn;
boot_iwe69 = resetn;
boot_dwe69 = resetn;
boot_iwe70 = resetn;
boot_dwe70 = resetn;
boot_iwe71 = resetn;
boot_dwe71 = resetn;
boot_iwe72 = resetn;
boot_dwe72 = resetn;
boot_iwe73 = resetn;
boot_dwe73 = resetn;
boot_iwe74 = resetn;
boot_dwe74 = resetn;
boot_iwe75 = resetn;
boot_dwe75 = resetn;
boot_iwe76 = resetn;
boot_dwe76 = resetn;
boot_iwe77 = resetn;
boot_dwe77 = resetn;
boot_iwe78 = resetn;
boot_dwe78 = resetn;
boot_iwe79 = resetn;
boot_dwe79 = resetn;
boot_iwe80 = resetn;
boot_dwe80 = resetn;
boot_iwe81 = resetn;
boot_dwe81 = resetn;
boot_iwe82 = resetn;
boot_dwe82 = resetn;
boot_iwe83 = resetn;
boot_dwe83 = resetn;
boot_iwe84 = resetn;
boot_dwe84 = resetn;
boot_iwe85 = resetn;
boot_dwe85 = resetn;
boot_iwe86 = resetn;
boot_dwe86 = resetn;
boot_iwe87 = resetn;
boot_dwe87 = resetn;
boot_iwe88 = resetn;
boot_dwe88 = resetn;
boot_iwe89 = resetn;
boot_dwe89 = resetn;
end
12: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = ~resetn;
boot_dwe12 = ~resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
boot_iwe50 = resetn;
boot_dwe50 = resetn;
boot_iwe51 = resetn;
boot_dwe51 = resetn;
boot_iwe52 = resetn;
boot_dwe52 = resetn;
boot_iwe53 = resetn;
boot_dwe53 = resetn;
boot_iwe54 = resetn;
boot_dwe54 = resetn;
boot_iwe55 = resetn;
boot_dwe55 = resetn;
boot_iwe56 = resetn;
boot_dwe56 = resetn;
boot_iwe57 = resetn;
boot_dwe57 = resetn;
boot_iwe58 = resetn;
boot_dwe58 = resetn;
boot_iwe59 = resetn;
boot_dwe59 = resetn;
boot_iwe60 = resetn;
boot_dwe60 = resetn;
boot_iwe61 = resetn;
boot_dwe61 = resetn;
boot_iwe62 = resetn;
boot_dwe62 = resetn;
boot_iwe63 = resetn;
boot_dwe63 = resetn;
boot_iwe64 = resetn;
boot_dwe64 = resetn;
boot_iwe65 = resetn;
boot_dwe65 = resetn;
boot_iwe66 = resetn;
boot_dwe66 = resetn;
boot_iwe67 = resetn;
boot_dwe67 = resetn;
boot_iwe68 = resetn;
boot_dwe68 = resetn;
boot_iwe69 = resetn;
boot_dwe69 = resetn;
boot_iwe70 = resetn;
boot_dwe70 = resetn;
boot_iwe71 = resetn;
boot_dwe71 = resetn;
boot_iwe72 = resetn;
boot_dwe72 = resetn;
boot_iwe73 = resetn;
boot_dwe73 = resetn;
boot_iwe74 = resetn;
boot_dwe74 = resetn;
boot_iwe75 = resetn;
boot_dwe75 = resetn;
boot_iwe76 = resetn;
boot_dwe76 = resetn;
boot_iwe77 = resetn;
boot_dwe77 = resetn;
boot_iwe78 = resetn;
boot_dwe78 = resetn;
boot_iwe79 = resetn;
boot_dwe79 = resetn;
boot_iwe80 = resetn;
boot_dwe80 = resetn;
boot_iwe81 = resetn;
boot_dwe81 = resetn;
boot_iwe82 = resetn;
boot_dwe82 = resetn;
boot_iwe83 = resetn;
boot_dwe83 = resetn;
boot_iwe84 = resetn;
boot_dwe84 = resetn;
boot_iwe85 = resetn;
boot_dwe85 = resetn;
boot_iwe86 = resetn;
boot_dwe86 = resetn;
boot_iwe87 = resetn;
boot_dwe87 = resetn;
boot_iwe88 = resetn;
boot_dwe88 = resetn;
boot_iwe89 = resetn;
boot_dwe89 = resetn;
end
13: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = ~resetn;
boot_dwe13 = ~resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
boot_iwe50 = resetn;
boot_dwe50 = resetn;
boot_iwe51 = resetn;
boot_dwe51 = resetn;
boot_iwe52 = resetn;
boot_dwe52 = resetn;
boot_iwe53 = resetn;
boot_dwe53 = resetn;
boot_iwe54 = resetn;
boot_dwe54 = resetn;
boot_iwe55 = resetn;
boot_dwe55 = resetn;
boot_iwe56 = resetn;
boot_dwe56 = resetn;
boot_iwe57 = resetn;
boot_dwe57 = resetn;
boot_iwe58 = resetn;
boot_dwe58 = resetn;
boot_iwe59 = resetn;
boot_dwe59 = resetn;
boot_iwe60 = resetn;
boot_dwe60 = resetn;
boot_iwe61 = resetn;
boot_dwe61 = resetn;
boot_iwe62 = resetn;
boot_dwe62 = resetn;
boot_iwe63 = resetn;
boot_dwe63 = resetn;
boot_iwe64 = resetn;
boot_dwe64 = resetn;
boot_iwe65 = resetn;
boot_dwe65 = resetn;
boot_iwe66 = resetn;
boot_dwe66 = resetn;
boot_iwe67 = resetn;
boot_dwe67 = resetn;
boot_iwe68 = resetn;
boot_dwe68 = resetn;
boot_iwe69 = resetn;
boot_dwe69 = resetn;
boot_iwe70 = resetn;
boot_dwe70 = resetn;
boot_iwe71 = resetn;
boot_dwe71 = resetn;
boot_iwe72 = resetn;
boot_dwe72 = resetn;
boot_iwe73 = resetn;
boot_dwe73 = resetn;
boot_iwe74 = resetn;
boot_dwe74 = resetn;
boot_iwe75 = resetn;
boot_dwe75 = resetn;
boot_iwe76 = resetn;
boot_dwe76 = resetn;
boot_iwe77 = resetn;
boot_dwe77 = resetn;
boot_iwe78 = resetn;
boot_dwe78 = resetn;
boot_iwe79 = resetn;
boot_dwe79 = resetn;
boot_iwe80 = resetn;
boot_dwe80 = resetn;
boot_iwe81 = resetn;
boot_dwe81 = resetn;
boot_iwe82 = resetn;
boot_dwe82 = resetn;
boot_iwe83 = resetn;
boot_dwe83 = resetn;
boot_iwe84 = resetn;
boot_dwe84 = resetn;
boot_iwe85 = resetn;
boot_dwe85 = resetn;
boot_iwe86 = resetn;
boot_dwe86 = resetn;
boot_iwe87 = resetn;
boot_dwe87 = resetn;
boot_iwe88 = resetn;
boot_dwe88 = resetn;
boot_iwe89 = resetn;
boot_dwe89 = resetn;
end
14: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = ~resetn;
boot_dwe14 = ~resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
boot_iwe50 = resetn;
boot_dwe50 = resetn;
boot_iwe51 = resetn;
boot_dwe51 = resetn;
boot_iwe52 = resetn;
boot_dwe52 = resetn;
boot_iwe53 = resetn;
boot_dwe53 = resetn;
boot_iwe54 = resetn;
boot_dwe54 = resetn;
boot_iwe55 = resetn;
boot_dwe55 = resetn;
boot_iwe56 = resetn;
boot_dwe56 = resetn;
boot_iwe57 = resetn;
boot_dwe57 = resetn;
boot_iwe58 = resetn;
boot_dwe58 = resetn;
boot_iwe59 = resetn;
boot_dwe59 = resetn;
boot_iwe60 = resetn;
boot_dwe60 = resetn;
boot_iwe61 = resetn;
boot_dwe61 = resetn;
boot_iwe62 = resetn;
boot_dwe62 = resetn;
boot_iwe63 = resetn;
boot_dwe63 = resetn;
boot_iwe64 = resetn;
boot_dwe64 = resetn;
boot_iwe65 = resetn;
boot_dwe65 = resetn;
boot_iwe66 = resetn;
boot_dwe66 = resetn;
boot_iwe67 = resetn;
boot_dwe67 = resetn;
boot_iwe68 = resetn;
boot_dwe68 = resetn;
boot_iwe69 = resetn;
boot_dwe69 = resetn;
boot_iwe70 = resetn;
boot_dwe70 = resetn;
boot_iwe71 = resetn;
boot_dwe71 = resetn;
boot_iwe72 = resetn;
boot_dwe72 = resetn;
boot_iwe73 = resetn;
boot_dwe73 = resetn;
boot_iwe74 = resetn;
boot_dwe74 = resetn;
boot_iwe75 = resetn;
boot_dwe75 = resetn;
boot_iwe76 = resetn;
boot_dwe76 = resetn;
boot_iwe77 = resetn;
boot_dwe77 = resetn;
boot_iwe78 = resetn;
boot_dwe78 = resetn;
boot_iwe79 = resetn;
boot_dwe79 = resetn;
boot_iwe80 = resetn;
boot_dwe80 = resetn;
boot_iwe81 = resetn;
boot_dwe81 = resetn;
boot_iwe82 = resetn;
boot_dwe82 = resetn;
boot_iwe83 = resetn;
boot_dwe83 = resetn;
boot_iwe84 = resetn;
boot_dwe84 = resetn;
boot_iwe85 = resetn;
boot_dwe85 = resetn;
boot_iwe86 = resetn;
boot_dwe86 = resetn;
boot_iwe87 = resetn;
boot_dwe87 = resetn;
boot_iwe88 = resetn;
boot_dwe88 = resetn;
boot_iwe89 = resetn;
boot_dwe89 = resetn;
end
15: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = ~resetn;
boot_dwe15 = ~resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
boot_iwe50 = resetn;
boot_dwe50 = resetn;
boot_iwe51 = resetn;
boot_dwe51 = resetn;
boot_iwe52 = resetn;
boot_dwe52 = resetn;
boot_iwe53 = resetn;
boot_dwe53 = resetn;
boot_iwe54 = resetn;
boot_dwe54 = resetn;
boot_iwe55 = resetn;
boot_dwe55 = resetn;
boot_iwe56 = resetn;
boot_dwe56 = resetn;
boot_iwe57 = resetn;
boot_dwe57 = resetn;
boot_iwe58 = resetn;
boot_dwe58 = resetn;
boot_iwe59 = resetn;
boot_dwe59 = resetn;
boot_iwe60 = resetn;
boot_dwe60 = resetn;
boot_iwe61 = resetn;
boot_dwe61 = resetn;
boot_iwe62 = resetn;
boot_dwe62 = resetn;
boot_iwe63 = resetn;
boot_dwe63 = resetn;
boot_iwe64 = resetn;
boot_dwe64 = resetn;
boot_iwe65 = resetn;
boot_dwe65 = resetn;
boot_iwe66 = resetn;
boot_dwe66 = resetn;
boot_iwe67 = resetn;
boot_dwe67 = resetn;
boot_iwe68 = resetn;
boot_dwe68 = resetn;
boot_iwe69 = resetn;
boot_dwe69 = resetn;
boot_iwe70 = resetn;
boot_dwe70 = resetn;
boot_iwe71 = resetn;
boot_dwe71 = resetn;
boot_iwe72 = resetn;
boot_dwe72 = resetn;
boot_iwe73 = resetn;
boot_dwe73 = resetn;
boot_iwe74 = resetn;
boot_dwe74 = resetn;
boot_iwe75 = resetn;
boot_dwe75 = resetn;
boot_iwe76 = resetn;
boot_dwe76 = resetn;
boot_iwe77 = resetn;
boot_dwe77 = resetn;
boot_iwe78 = resetn;
boot_dwe78 = resetn;
boot_iwe79 = resetn;
boot_dwe79 = resetn;
boot_iwe80 = resetn;
boot_dwe80 = resetn;
boot_iwe81 = resetn;
boot_dwe81 = resetn;
boot_iwe82 = resetn;
boot_dwe82 = resetn;
boot_iwe83 = resetn;
boot_dwe83 = resetn;
boot_iwe84 = resetn;
boot_dwe84 = resetn;
boot_iwe85 = resetn;
boot_dwe85 = resetn;
boot_iwe86 = resetn;
boot_dwe86 = resetn;
boot_iwe87 = resetn;
boot_dwe87 = resetn;
boot_iwe88 = resetn;
boot_dwe88 = resetn;
boot_iwe89 = resetn;
boot_dwe89 = resetn;
end
16: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = ~resetn;
boot_dwe16 = ~resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
boot_iwe50 = resetn;
boot_dwe50 = resetn;
boot_iwe51 = resetn;
boot_dwe51 = resetn;
boot_iwe52 = resetn;
boot_dwe52 = resetn;
boot_iwe53 = resetn;
boot_dwe53 = resetn;
boot_iwe54 = resetn;
boot_dwe54 = resetn;
boot_iwe55 = resetn;
boot_dwe55 = resetn;
boot_iwe56 = resetn;
boot_dwe56 = resetn;
boot_iwe57 = resetn;
boot_dwe57 = resetn;
boot_iwe58 = resetn;
boot_dwe58 = resetn;
boot_iwe59 = resetn;
boot_dwe59 = resetn;
boot_iwe60 = resetn;
boot_dwe60 = resetn;
boot_iwe61 = resetn;
boot_dwe61 = resetn;
boot_iwe62 = resetn;
boot_dwe62 = resetn;
boot_iwe63 = resetn;
boot_dwe63 = resetn;
boot_iwe64 = resetn;
boot_dwe64 = resetn;
boot_iwe65 = resetn;
boot_dwe65 = resetn;
boot_iwe66 = resetn;
boot_dwe66 = resetn;
boot_iwe67 = resetn;
boot_dwe67 = resetn;
boot_iwe68 = resetn;
boot_dwe68 = resetn;
boot_iwe69 = resetn;
boot_dwe69 = resetn;
boot_iwe70 = resetn;
boot_dwe70 = resetn;
boot_iwe71 = resetn;
boot_dwe71 = resetn;
boot_iwe72 = resetn;
boot_dwe72 = resetn;
boot_iwe73 = resetn;
boot_dwe73 = resetn;
boot_iwe74 = resetn;
boot_dwe74 = resetn;
boot_iwe75 = resetn;
boot_dwe75 = resetn;
boot_iwe76 = resetn;
boot_dwe76 = resetn;
boot_iwe77 = resetn;
boot_dwe77 = resetn;
boot_iwe78 = resetn;
boot_dwe78 = resetn;
boot_iwe79 = resetn;
boot_dwe79 = resetn;
boot_iwe80 = resetn;
boot_dwe80 = resetn;
boot_iwe81 = resetn;
boot_dwe81 = resetn;
boot_iwe82 = resetn;
boot_dwe82 = resetn;
boot_iwe83 = resetn;
boot_dwe83 = resetn;
boot_iwe84 = resetn;
boot_dwe84 = resetn;
boot_iwe85 = resetn;
boot_dwe85 = resetn;
boot_iwe86 = resetn;
boot_dwe86 = resetn;
boot_iwe87 = resetn;
boot_dwe87 = resetn;
boot_iwe88 = resetn;
boot_dwe88 = resetn;
boot_iwe89 = resetn;
boot_dwe89 = resetn;
end
17: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = ~resetn;
boot_dwe17 = ~resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
boot_iwe50 = resetn;
boot_dwe50 = resetn;
boot_iwe51 = resetn;
boot_dwe51 = resetn;
boot_iwe52 = resetn;
boot_dwe52 = resetn;
boot_iwe53 = resetn;
boot_dwe53 = resetn;
boot_iwe54 = resetn;
boot_dwe54 = resetn;
boot_iwe55 = resetn;
boot_dwe55 = resetn;
boot_iwe56 = resetn;
boot_dwe56 = resetn;
boot_iwe57 = resetn;
boot_dwe57 = resetn;
boot_iwe58 = resetn;
boot_dwe58 = resetn;
boot_iwe59 = resetn;
boot_dwe59 = resetn;
boot_iwe60 = resetn;
boot_dwe60 = resetn;
boot_iwe61 = resetn;
boot_dwe61 = resetn;
boot_iwe62 = resetn;
boot_dwe62 = resetn;
boot_iwe63 = resetn;
boot_dwe63 = resetn;
boot_iwe64 = resetn;
boot_dwe64 = resetn;
boot_iwe65 = resetn;
boot_dwe65 = resetn;
boot_iwe66 = resetn;
boot_dwe66 = resetn;
boot_iwe67 = resetn;
boot_dwe67 = resetn;
boot_iwe68 = resetn;
boot_dwe68 = resetn;
boot_iwe69 = resetn;
boot_dwe69 = resetn;
boot_iwe70 = resetn;
boot_dwe70 = resetn;
boot_iwe71 = resetn;
boot_dwe71 = resetn;
boot_iwe72 = resetn;
boot_dwe72 = resetn;
boot_iwe73 = resetn;
boot_dwe73 = resetn;
boot_iwe74 = resetn;
boot_dwe74 = resetn;
boot_iwe75 = resetn;
boot_dwe75 = resetn;
boot_iwe76 = resetn;
boot_dwe76 = resetn;
boot_iwe77 = resetn;
boot_dwe77 = resetn;
boot_iwe78 = resetn;
boot_dwe78 = resetn;
boot_iwe79 = resetn;
boot_dwe79 = resetn;
boot_iwe80 = resetn;
boot_dwe80 = resetn;
boot_iwe81 = resetn;
boot_dwe81 = resetn;
boot_iwe82 = resetn;
boot_dwe82 = resetn;
boot_iwe83 = resetn;
boot_dwe83 = resetn;
boot_iwe84 = resetn;
boot_dwe84 = resetn;
boot_iwe85 = resetn;
boot_dwe85 = resetn;
boot_iwe86 = resetn;
boot_dwe86 = resetn;
boot_iwe87 = resetn;
boot_dwe87 = resetn;
boot_iwe88 = resetn;
boot_dwe88 = resetn;
boot_iwe89 = resetn;
boot_dwe89 = resetn;
end
18: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = ~resetn;
boot_dwe18 = ~resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
boot_iwe50 = resetn;
boot_dwe50 = resetn;
boot_iwe51 = resetn;
boot_dwe51 = resetn;
boot_iwe52 = resetn;
boot_dwe52 = resetn;
boot_iwe53 = resetn;
boot_dwe53 = resetn;
boot_iwe54 = resetn;
boot_dwe54 = resetn;
boot_iwe55 = resetn;
boot_dwe55 = resetn;
boot_iwe56 = resetn;
boot_dwe56 = resetn;
boot_iwe57 = resetn;
boot_dwe57 = resetn;
boot_iwe58 = resetn;
boot_dwe58 = resetn;
boot_iwe59 = resetn;
boot_dwe59 = resetn;
boot_iwe60 = resetn;
boot_dwe60 = resetn;
boot_iwe61 = resetn;
boot_dwe61 = resetn;
boot_iwe62 = resetn;
boot_dwe62 = resetn;
boot_iwe63 = resetn;
boot_dwe63 = resetn;
boot_iwe64 = resetn;
boot_dwe64 = resetn;
boot_iwe65 = resetn;
boot_dwe65 = resetn;
boot_iwe66 = resetn;
boot_dwe66 = resetn;
boot_iwe67 = resetn;
boot_dwe67 = resetn;
boot_iwe68 = resetn;
boot_dwe68 = resetn;
boot_iwe69 = resetn;
boot_dwe69 = resetn;
boot_iwe70 = resetn;
boot_dwe70 = resetn;
boot_iwe71 = resetn;
boot_dwe71 = resetn;
boot_iwe72 = resetn;
boot_dwe72 = resetn;
boot_iwe73 = resetn;
boot_dwe73 = resetn;
boot_iwe74 = resetn;
boot_dwe74 = resetn;
boot_iwe75 = resetn;
boot_dwe75 = resetn;
boot_iwe76 = resetn;
boot_dwe76 = resetn;
boot_iwe77 = resetn;
boot_dwe77 = resetn;
boot_iwe78 = resetn;
boot_dwe78 = resetn;
boot_iwe79 = resetn;
boot_dwe79 = resetn;
boot_iwe80 = resetn;
boot_dwe80 = resetn;
boot_iwe81 = resetn;
boot_dwe81 = resetn;
boot_iwe82 = resetn;
boot_dwe82 = resetn;
boot_iwe83 = resetn;
boot_dwe83 = resetn;
boot_iwe84 = resetn;
boot_dwe84 = resetn;
boot_iwe85 = resetn;
boot_dwe85 = resetn;
boot_iwe86 = resetn;
boot_dwe86 = resetn;
boot_iwe87 = resetn;
boot_dwe87 = resetn;
boot_iwe88 = resetn;
boot_dwe88 = resetn;
boot_iwe89 = resetn;
boot_dwe89 = resetn;
end
19: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = ~resetn;
boot_dwe19 = ~resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
boot_iwe50 = resetn;
boot_dwe50 = resetn;
boot_iwe51 = resetn;
boot_dwe51 = resetn;
boot_iwe52 = resetn;
boot_dwe52 = resetn;
boot_iwe53 = resetn;
boot_dwe53 = resetn;
boot_iwe54 = resetn;
boot_dwe54 = resetn;
boot_iwe55 = resetn;
boot_dwe55 = resetn;
boot_iwe56 = resetn;
boot_dwe56 = resetn;
boot_iwe57 = resetn;
boot_dwe57 = resetn;
boot_iwe58 = resetn;
boot_dwe58 = resetn;
boot_iwe59 = resetn;
boot_dwe59 = resetn;
boot_iwe60 = resetn;
boot_dwe60 = resetn;
boot_iwe61 = resetn;
boot_dwe61 = resetn;
boot_iwe62 = resetn;
boot_dwe62 = resetn;
boot_iwe63 = resetn;
boot_dwe63 = resetn;
boot_iwe64 = resetn;
boot_dwe64 = resetn;
boot_iwe65 = resetn;
boot_dwe65 = resetn;
boot_iwe66 = resetn;
boot_dwe66 = resetn;
boot_iwe67 = resetn;
boot_dwe67 = resetn;
boot_iwe68 = resetn;
boot_dwe68 = resetn;
boot_iwe69 = resetn;
boot_dwe69 = resetn;
boot_iwe70 = resetn;
boot_dwe70 = resetn;
boot_iwe71 = resetn;
boot_dwe71 = resetn;
boot_iwe72 = resetn;
boot_dwe72 = resetn;
boot_iwe73 = resetn;
boot_dwe73 = resetn;
boot_iwe74 = resetn;
boot_dwe74 = resetn;
boot_iwe75 = resetn;
boot_dwe75 = resetn;
boot_iwe76 = resetn;
boot_dwe76 = resetn;
boot_iwe77 = resetn;
boot_dwe77 = resetn;
boot_iwe78 = resetn;
boot_dwe78 = resetn;
boot_iwe79 = resetn;
boot_dwe79 = resetn;
boot_iwe80 = resetn;
boot_dwe80 = resetn;
boot_iwe81 = resetn;
boot_dwe81 = resetn;
boot_iwe82 = resetn;
boot_dwe82 = resetn;
boot_iwe83 = resetn;
boot_dwe83 = resetn;
boot_iwe84 = resetn;
boot_dwe84 = resetn;
boot_iwe85 = resetn;
boot_dwe85 = resetn;
boot_iwe86 = resetn;
boot_dwe86 = resetn;
boot_iwe87 = resetn;
boot_dwe87 = resetn;
boot_iwe88 = resetn;
boot_dwe88 = resetn;
boot_iwe89 = resetn;
boot_dwe89 = resetn;
end
20: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = ~resetn;
boot_dwe20 = ~resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
boot_iwe50 = resetn;
boot_dwe50 = resetn;
boot_iwe51 = resetn;
boot_dwe51 = resetn;
boot_iwe52 = resetn;
boot_dwe52 = resetn;
boot_iwe53 = resetn;
boot_dwe53 = resetn;
boot_iwe54 = resetn;
boot_dwe54 = resetn;
boot_iwe55 = resetn;
boot_dwe55 = resetn;
boot_iwe56 = resetn;
boot_dwe56 = resetn;
boot_iwe57 = resetn;
boot_dwe57 = resetn;
boot_iwe58 = resetn;
boot_dwe58 = resetn;
boot_iwe59 = resetn;
boot_dwe59 = resetn;
boot_iwe60 = resetn;
boot_dwe60 = resetn;
boot_iwe61 = resetn;
boot_dwe61 = resetn;
boot_iwe62 = resetn;
boot_dwe62 = resetn;
boot_iwe63 = resetn;
boot_dwe63 = resetn;
boot_iwe64 = resetn;
boot_dwe64 = resetn;
boot_iwe65 = resetn;
boot_dwe65 = resetn;
boot_iwe66 = resetn;
boot_dwe66 = resetn;
boot_iwe67 = resetn;
boot_dwe67 = resetn;
boot_iwe68 = resetn;
boot_dwe68 = resetn;
boot_iwe69 = resetn;
boot_dwe69 = resetn;
boot_iwe70 = resetn;
boot_dwe70 = resetn;
boot_iwe71 = resetn;
boot_dwe71 = resetn;
boot_iwe72 = resetn;
boot_dwe72 = resetn;
boot_iwe73 = resetn;
boot_dwe73 = resetn;
boot_iwe74 = resetn;
boot_dwe74 = resetn;
boot_iwe75 = resetn;
boot_dwe75 = resetn;
boot_iwe76 = resetn;
boot_dwe76 = resetn;
boot_iwe77 = resetn;
boot_dwe77 = resetn;
boot_iwe78 = resetn;
boot_dwe78 = resetn;
boot_iwe79 = resetn;
boot_dwe79 = resetn;
boot_iwe80 = resetn;
boot_dwe80 = resetn;
boot_iwe81 = resetn;
boot_dwe81 = resetn;
boot_iwe82 = resetn;
boot_dwe82 = resetn;
boot_iwe83 = resetn;
boot_dwe83 = resetn;
boot_iwe84 = resetn;
boot_dwe84 = resetn;
boot_iwe85 = resetn;
boot_dwe85 = resetn;
boot_iwe86 = resetn;
boot_dwe86 = resetn;
boot_iwe87 = resetn;
boot_dwe87 = resetn;
boot_iwe88 = resetn;
boot_dwe88 = resetn;
boot_iwe89 = resetn;
boot_dwe89 = resetn;
end
21: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = ~resetn;
boot_dwe21 = ~resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
boot_iwe50 = resetn;
boot_dwe50 = resetn;
boot_iwe51 = resetn;
boot_dwe51 = resetn;
boot_iwe52 = resetn;
boot_dwe52 = resetn;
boot_iwe53 = resetn;
boot_dwe53 = resetn;
boot_iwe54 = resetn;
boot_dwe54 = resetn;
boot_iwe55 = resetn;
boot_dwe55 = resetn;
boot_iwe56 = resetn;
boot_dwe56 = resetn;
boot_iwe57 = resetn;
boot_dwe57 = resetn;
boot_iwe58 = resetn;
boot_dwe58 = resetn;
boot_iwe59 = resetn;
boot_dwe59 = resetn;
boot_iwe60 = resetn;
boot_dwe60 = resetn;
boot_iwe61 = resetn;
boot_dwe61 = resetn;
boot_iwe62 = resetn;
boot_dwe62 = resetn;
boot_iwe63 = resetn;
boot_dwe63 = resetn;
boot_iwe64 = resetn;
boot_dwe64 = resetn;
boot_iwe65 = resetn;
boot_dwe65 = resetn;
boot_iwe66 = resetn;
boot_dwe66 = resetn;
boot_iwe67 = resetn;
boot_dwe67 = resetn;
boot_iwe68 = resetn;
boot_dwe68 = resetn;
boot_iwe69 = resetn;
boot_dwe69 = resetn;
boot_iwe70 = resetn;
boot_dwe70 = resetn;
boot_iwe71 = resetn;
boot_dwe71 = resetn;
boot_iwe72 = resetn;
boot_dwe72 = resetn;
boot_iwe73 = resetn;
boot_dwe73 = resetn;
boot_iwe74 = resetn;
boot_dwe74 = resetn;
boot_iwe75 = resetn;
boot_dwe75 = resetn;
boot_iwe76 = resetn;
boot_dwe76 = resetn;
boot_iwe77 = resetn;
boot_dwe77 = resetn;
boot_iwe78 = resetn;
boot_dwe78 = resetn;
boot_iwe79 = resetn;
boot_dwe79 = resetn;
boot_iwe80 = resetn;
boot_dwe80 = resetn;
boot_iwe81 = resetn;
boot_dwe81 = resetn;
boot_iwe82 = resetn;
boot_dwe82 = resetn;
boot_iwe83 = resetn;
boot_dwe83 = resetn;
boot_iwe84 = resetn;
boot_dwe84 = resetn;
boot_iwe85 = resetn;
boot_dwe85 = resetn;
boot_iwe86 = resetn;
boot_dwe86 = resetn;
boot_iwe87 = resetn;
boot_dwe87 = resetn;
boot_iwe88 = resetn;
boot_dwe88 = resetn;
boot_iwe89 = resetn;
boot_dwe89 = resetn;
end
22: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = ~resetn;
boot_dwe22 = ~resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
boot_iwe50 = resetn;
boot_dwe50 = resetn;
boot_iwe51 = resetn;
boot_dwe51 = resetn;
boot_iwe52 = resetn;
boot_dwe52 = resetn;
boot_iwe53 = resetn;
boot_dwe53 = resetn;
boot_iwe54 = resetn;
boot_dwe54 = resetn;
boot_iwe55 = resetn;
boot_dwe55 = resetn;
boot_iwe56 = resetn;
boot_dwe56 = resetn;
boot_iwe57 = resetn;
boot_dwe57 = resetn;
boot_iwe58 = resetn;
boot_dwe58 = resetn;
boot_iwe59 = resetn;
boot_dwe59 = resetn;
boot_iwe60 = resetn;
boot_dwe60 = resetn;
boot_iwe61 = resetn;
boot_dwe61 = resetn;
boot_iwe62 = resetn;
boot_dwe62 = resetn;
boot_iwe63 = resetn;
boot_dwe63 = resetn;
boot_iwe64 = resetn;
boot_dwe64 = resetn;
boot_iwe65 = resetn;
boot_dwe65 = resetn;
boot_iwe66 = resetn;
boot_dwe66 = resetn;
boot_iwe67 = resetn;
boot_dwe67 = resetn;
boot_iwe68 = resetn;
boot_dwe68 = resetn;
boot_iwe69 = resetn;
boot_dwe69 = resetn;
boot_iwe70 = resetn;
boot_dwe70 = resetn;
boot_iwe71 = resetn;
boot_dwe71 = resetn;
boot_iwe72 = resetn;
boot_dwe72 = resetn;
boot_iwe73 = resetn;
boot_dwe73 = resetn;
boot_iwe74 = resetn;
boot_dwe74 = resetn;
boot_iwe75 = resetn;
boot_dwe75 = resetn;
boot_iwe76 = resetn;
boot_dwe76 = resetn;
boot_iwe77 = resetn;
boot_dwe77 = resetn;
boot_iwe78 = resetn;
boot_dwe78 = resetn;
boot_iwe79 = resetn;
boot_dwe79 = resetn;
boot_iwe80 = resetn;
boot_dwe80 = resetn;
boot_iwe81 = resetn;
boot_dwe81 = resetn;
boot_iwe82 = resetn;
boot_dwe82 = resetn;
boot_iwe83 = resetn;
boot_dwe83 = resetn;
boot_iwe84 = resetn;
boot_dwe84 = resetn;
boot_iwe85 = resetn;
boot_dwe85 = resetn;
boot_iwe86 = resetn;
boot_dwe86 = resetn;
boot_iwe87 = resetn;
boot_dwe87 = resetn;
boot_iwe88 = resetn;
boot_dwe88 = resetn;
boot_iwe89 = resetn;
boot_dwe89 = resetn;
end
23: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = ~resetn;
boot_dwe23 = ~resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
boot_iwe50 = resetn;
boot_dwe50 = resetn;
boot_iwe51 = resetn;
boot_dwe51 = resetn;
boot_iwe52 = resetn;
boot_dwe52 = resetn;
boot_iwe53 = resetn;
boot_dwe53 = resetn;
boot_iwe54 = resetn;
boot_dwe54 = resetn;
boot_iwe55 = resetn;
boot_dwe55 = resetn;
boot_iwe56 = resetn;
boot_dwe56 = resetn;
boot_iwe57 = resetn;
boot_dwe57 = resetn;
boot_iwe58 = resetn;
boot_dwe58 = resetn;
boot_iwe59 = resetn;
boot_dwe59 = resetn;
boot_iwe60 = resetn;
boot_dwe60 = resetn;
boot_iwe61 = resetn;
boot_dwe61 = resetn;
boot_iwe62 = resetn;
boot_dwe62 = resetn;
boot_iwe63 = resetn;
boot_dwe63 = resetn;
boot_iwe64 = resetn;
boot_dwe64 = resetn;
boot_iwe65 = resetn;
boot_dwe65 = resetn;
boot_iwe66 = resetn;
boot_dwe66 = resetn;
boot_iwe67 = resetn;
boot_dwe67 = resetn;
boot_iwe68 = resetn;
boot_dwe68 = resetn;
boot_iwe69 = resetn;
boot_dwe69 = resetn;
boot_iwe70 = resetn;
boot_dwe70 = resetn;
boot_iwe71 = resetn;
boot_dwe71 = resetn;
boot_iwe72 = resetn;
boot_dwe72 = resetn;
boot_iwe73 = resetn;
boot_dwe73 = resetn;
boot_iwe74 = resetn;
boot_dwe74 = resetn;
boot_iwe75 = resetn;
boot_dwe75 = resetn;
boot_iwe76 = resetn;
boot_dwe76 = resetn;
boot_iwe77 = resetn;
boot_dwe77 = resetn;
boot_iwe78 = resetn;
boot_dwe78 = resetn;
boot_iwe79 = resetn;
boot_dwe79 = resetn;
boot_iwe80 = resetn;
boot_dwe80 = resetn;
boot_iwe81 = resetn;
boot_dwe81 = resetn;
boot_iwe82 = resetn;
boot_dwe82 = resetn;
boot_iwe83 = resetn;
boot_dwe83 = resetn;
boot_iwe84 = resetn;
boot_dwe84 = resetn;
boot_iwe85 = resetn;
boot_dwe85 = resetn;
boot_iwe86 = resetn;
boot_dwe86 = resetn;
boot_iwe87 = resetn;
boot_dwe87 = resetn;
boot_iwe88 = resetn;
boot_dwe88 = resetn;
boot_iwe89 = resetn;
boot_dwe89 = resetn;
end
24: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = ~resetn;
boot_dwe24 = ~resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
boot_iwe50 = resetn;
boot_dwe50 = resetn;
boot_iwe51 = resetn;
boot_dwe51 = resetn;
boot_iwe52 = resetn;
boot_dwe52 = resetn;
boot_iwe53 = resetn;
boot_dwe53 = resetn;
boot_iwe54 = resetn;
boot_dwe54 = resetn;
boot_iwe55 = resetn;
boot_dwe55 = resetn;
boot_iwe56 = resetn;
boot_dwe56 = resetn;
boot_iwe57 = resetn;
boot_dwe57 = resetn;
boot_iwe58 = resetn;
boot_dwe58 = resetn;
boot_iwe59 = resetn;
boot_dwe59 = resetn;
boot_iwe60 = resetn;
boot_dwe60 = resetn;
boot_iwe61 = resetn;
boot_dwe61 = resetn;
boot_iwe62 = resetn;
boot_dwe62 = resetn;
boot_iwe63 = resetn;
boot_dwe63 = resetn;
boot_iwe64 = resetn;
boot_dwe64 = resetn;
boot_iwe65 = resetn;
boot_dwe65 = resetn;
boot_iwe66 = resetn;
boot_dwe66 = resetn;
boot_iwe67 = resetn;
boot_dwe67 = resetn;
boot_iwe68 = resetn;
boot_dwe68 = resetn;
boot_iwe69 = resetn;
boot_dwe69 = resetn;
boot_iwe70 = resetn;
boot_dwe70 = resetn;
boot_iwe71 = resetn;
boot_dwe71 = resetn;
boot_iwe72 = resetn;
boot_dwe72 = resetn;
boot_iwe73 = resetn;
boot_dwe73 = resetn;
boot_iwe74 = resetn;
boot_dwe74 = resetn;
boot_iwe75 = resetn;
boot_dwe75 = resetn;
boot_iwe76 = resetn;
boot_dwe76 = resetn;
boot_iwe77 = resetn;
boot_dwe77 = resetn;
boot_iwe78 = resetn;
boot_dwe78 = resetn;
boot_iwe79 = resetn;
boot_dwe79 = resetn;
boot_iwe80 = resetn;
boot_dwe80 = resetn;
boot_iwe81 = resetn;
boot_dwe81 = resetn;
boot_iwe82 = resetn;
boot_dwe82 = resetn;
boot_iwe83 = resetn;
boot_dwe83 = resetn;
boot_iwe84 = resetn;
boot_dwe84 = resetn;
boot_iwe85 = resetn;
boot_dwe85 = resetn;
boot_iwe86 = resetn;
boot_dwe86 = resetn;
boot_iwe87 = resetn;
boot_dwe87 = resetn;
boot_iwe88 = resetn;
boot_dwe88 = resetn;
boot_iwe89 = resetn;
boot_dwe89 = resetn;
end
25: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = ~resetn;
boot_dwe25 = ~resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
boot_iwe50 = resetn;
boot_dwe50 = resetn;
boot_iwe51 = resetn;
boot_dwe51 = resetn;
boot_iwe52 = resetn;
boot_dwe52 = resetn;
boot_iwe53 = resetn;
boot_dwe53 = resetn;
boot_iwe54 = resetn;
boot_dwe54 = resetn;
boot_iwe55 = resetn;
boot_dwe55 = resetn;
boot_iwe56 = resetn;
boot_dwe56 = resetn;
boot_iwe57 = resetn;
boot_dwe57 = resetn;
boot_iwe58 = resetn;
boot_dwe58 = resetn;
boot_iwe59 = resetn;
boot_dwe59 = resetn;
boot_iwe60 = resetn;
boot_dwe60 = resetn;
boot_iwe61 = resetn;
boot_dwe61 = resetn;
boot_iwe62 = resetn;
boot_dwe62 = resetn;
boot_iwe63 = resetn;
boot_dwe63 = resetn;
boot_iwe64 = resetn;
boot_dwe64 = resetn;
boot_iwe65 = resetn;
boot_dwe65 = resetn;
boot_iwe66 = resetn;
boot_dwe66 = resetn;
boot_iwe67 = resetn;
boot_dwe67 = resetn;
boot_iwe68 = resetn;
boot_dwe68 = resetn;
boot_iwe69 = resetn;
boot_dwe69 = resetn;
boot_iwe70 = resetn;
boot_dwe70 = resetn;
boot_iwe71 = resetn;
boot_dwe71 = resetn;
boot_iwe72 = resetn;
boot_dwe72 = resetn;
boot_iwe73 = resetn;
boot_dwe73 = resetn;
boot_iwe74 = resetn;
boot_dwe74 = resetn;
boot_iwe75 = resetn;
boot_dwe75 = resetn;
boot_iwe76 = resetn;
boot_dwe76 = resetn;
boot_iwe77 = resetn;
boot_dwe77 = resetn;
boot_iwe78 = resetn;
boot_dwe78 = resetn;
boot_iwe79 = resetn;
boot_dwe79 = resetn;
boot_iwe80 = resetn;
boot_dwe80 = resetn;
boot_iwe81 = resetn;
boot_dwe81 = resetn;
boot_iwe82 = resetn;
boot_dwe82 = resetn;
boot_iwe83 = resetn;
boot_dwe83 = resetn;
boot_iwe84 = resetn;
boot_dwe84 = resetn;
boot_iwe85 = resetn;
boot_dwe85 = resetn;
boot_iwe86 = resetn;
boot_dwe86 = resetn;
boot_iwe87 = resetn;
boot_dwe87 = resetn;
boot_iwe88 = resetn;
boot_dwe88 = resetn;
boot_iwe89 = resetn;
boot_dwe89 = resetn;
end
26: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = ~resetn;
boot_dwe26 = ~resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
boot_iwe50 = resetn;
boot_dwe50 = resetn;
boot_iwe51 = resetn;
boot_dwe51 = resetn;
boot_iwe52 = resetn;
boot_dwe52 = resetn;
boot_iwe53 = resetn;
boot_dwe53 = resetn;
boot_iwe54 = resetn;
boot_dwe54 = resetn;
boot_iwe55 = resetn;
boot_dwe55 = resetn;
boot_iwe56 = resetn;
boot_dwe56 = resetn;
boot_iwe57 = resetn;
boot_dwe57 = resetn;
boot_iwe58 = resetn;
boot_dwe58 = resetn;
boot_iwe59 = resetn;
boot_dwe59 = resetn;
boot_iwe60 = resetn;
boot_dwe60 = resetn;
boot_iwe61 = resetn;
boot_dwe61 = resetn;
boot_iwe62 = resetn;
boot_dwe62 = resetn;
boot_iwe63 = resetn;
boot_dwe63 = resetn;
boot_iwe64 = resetn;
boot_dwe64 = resetn;
boot_iwe65 = resetn;
boot_dwe65 = resetn;
boot_iwe66 = resetn;
boot_dwe66 = resetn;
boot_iwe67 = resetn;
boot_dwe67 = resetn;
boot_iwe68 = resetn;
boot_dwe68 = resetn;
boot_iwe69 = resetn;
boot_dwe69 = resetn;
boot_iwe70 = resetn;
boot_dwe70 = resetn;
boot_iwe71 = resetn;
boot_dwe71 = resetn;
boot_iwe72 = resetn;
boot_dwe72 = resetn;
boot_iwe73 = resetn;
boot_dwe73 = resetn;
boot_iwe74 = resetn;
boot_dwe74 = resetn;
boot_iwe75 = resetn;
boot_dwe75 = resetn;
boot_iwe76 = resetn;
boot_dwe76 = resetn;
boot_iwe77 = resetn;
boot_dwe77 = resetn;
boot_iwe78 = resetn;
boot_dwe78 = resetn;
boot_iwe79 = resetn;
boot_dwe79 = resetn;
boot_iwe80 = resetn;
boot_dwe80 = resetn;
boot_iwe81 = resetn;
boot_dwe81 = resetn;
boot_iwe82 = resetn;
boot_dwe82 = resetn;
boot_iwe83 = resetn;
boot_dwe83 = resetn;
boot_iwe84 = resetn;
boot_dwe84 = resetn;
boot_iwe85 = resetn;
boot_dwe85 = resetn;
boot_iwe86 = resetn;
boot_dwe86 = resetn;
boot_iwe87 = resetn;
boot_dwe87 = resetn;
boot_iwe88 = resetn;
boot_dwe88 = resetn;
boot_iwe89 = resetn;
boot_dwe89 = resetn;
end
27: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = ~resetn;
boot_dwe27 = ~resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
boot_iwe50 = resetn;
boot_dwe50 = resetn;
boot_iwe51 = resetn;
boot_dwe51 = resetn;
boot_iwe52 = resetn;
boot_dwe52 = resetn;
boot_iwe53 = resetn;
boot_dwe53 = resetn;
boot_iwe54 = resetn;
boot_dwe54 = resetn;
boot_iwe55 = resetn;
boot_dwe55 = resetn;
boot_iwe56 = resetn;
boot_dwe56 = resetn;
boot_iwe57 = resetn;
boot_dwe57 = resetn;
boot_iwe58 = resetn;
boot_dwe58 = resetn;
boot_iwe59 = resetn;
boot_dwe59 = resetn;
boot_iwe60 = resetn;
boot_dwe60 = resetn;
boot_iwe61 = resetn;
boot_dwe61 = resetn;
boot_iwe62 = resetn;
boot_dwe62 = resetn;
boot_iwe63 = resetn;
boot_dwe63 = resetn;
boot_iwe64 = resetn;
boot_dwe64 = resetn;
boot_iwe65 = resetn;
boot_dwe65 = resetn;
boot_iwe66 = resetn;
boot_dwe66 = resetn;
boot_iwe67 = resetn;
boot_dwe67 = resetn;
boot_iwe68 = resetn;
boot_dwe68 = resetn;
boot_iwe69 = resetn;
boot_dwe69 = resetn;
boot_iwe70 = resetn;
boot_dwe70 = resetn;
boot_iwe71 = resetn;
boot_dwe71 = resetn;
boot_iwe72 = resetn;
boot_dwe72 = resetn;
boot_iwe73 = resetn;
boot_dwe73 = resetn;
boot_iwe74 = resetn;
boot_dwe74 = resetn;
boot_iwe75 = resetn;
boot_dwe75 = resetn;
boot_iwe76 = resetn;
boot_dwe76 = resetn;
boot_iwe77 = resetn;
boot_dwe77 = resetn;
boot_iwe78 = resetn;
boot_dwe78 = resetn;
boot_iwe79 = resetn;
boot_dwe79 = resetn;
boot_iwe80 = resetn;
boot_dwe80 = resetn;
boot_iwe81 = resetn;
boot_dwe81 = resetn;
boot_iwe82 = resetn;
boot_dwe82 = resetn;
boot_iwe83 = resetn;
boot_dwe83 = resetn;
boot_iwe84 = resetn;
boot_dwe84 = resetn;
boot_iwe85 = resetn;
boot_dwe85 = resetn;
boot_iwe86 = resetn;
boot_dwe86 = resetn;
boot_iwe87 = resetn;
boot_dwe87 = resetn;
boot_iwe88 = resetn;
boot_dwe88 = resetn;
boot_iwe89 = resetn;
boot_dwe89 = resetn;
end
28: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = ~resetn;
boot_dwe28 = ~resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
boot_iwe50 = resetn;
boot_dwe50 = resetn;
boot_iwe51 = resetn;
boot_dwe51 = resetn;
boot_iwe52 = resetn;
boot_dwe52 = resetn;
boot_iwe53 = resetn;
boot_dwe53 = resetn;
boot_iwe54 = resetn;
boot_dwe54 = resetn;
boot_iwe55 = resetn;
boot_dwe55 = resetn;
boot_iwe56 = resetn;
boot_dwe56 = resetn;
boot_iwe57 = resetn;
boot_dwe57 = resetn;
boot_iwe58 = resetn;
boot_dwe58 = resetn;
boot_iwe59 = resetn;
boot_dwe59 = resetn;
boot_iwe60 = resetn;
boot_dwe60 = resetn;
boot_iwe61 = resetn;
boot_dwe61 = resetn;
boot_iwe62 = resetn;
boot_dwe62 = resetn;
boot_iwe63 = resetn;
boot_dwe63 = resetn;
boot_iwe64 = resetn;
boot_dwe64 = resetn;
boot_iwe65 = resetn;
boot_dwe65 = resetn;
boot_iwe66 = resetn;
boot_dwe66 = resetn;
boot_iwe67 = resetn;
boot_dwe67 = resetn;
boot_iwe68 = resetn;
boot_dwe68 = resetn;
boot_iwe69 = resetn;
boot_dwe69 = resetn;
boot_iwe70 = resetn;
boot_dwe70 = resetn;
boot_iwe71 = resetn;
boot_dwe71 = resetn;
boot_iwe72 = resetn;
boot_dwe72 = resetn;
boot_iwe73 = resetn;
boot_dwe73 = resetn;
boot_iwe74 = resetn;
boot_dwe74 = resetn;
boot_iwe75 = resetn;
boot_dwe75 = resetn;
boot_iwe76 = resetn;
boot_dwe76 = resetn;
boot_iwe77 = resetn;
boot_dwe77 = resetn;
boot_iwe78 = resetn;
boot_dwe78 = resetn;
boot_iwe79 = resetn;
boot_dwe79 = resetn;
boot_iwe80 = resetn;
boot_dwe80 = resetn;
boot_iwe81 = resetn;
boot_dwe81 = resetn;
boot_iwe82 = resetn;
boot_dwe82 = resetn;
boot_iwe83 = resetn;
boot_dwe83 = resetn;
boot_iwe84 = resetn;
boot_dwe84 = resetn;
boot_iwe85 = resetn;
boot_dwe85 = resetn;
boot_iwe86 = resetn;
boot_dwe86 = resetn;
boot_iwe87 = resetn;
boot_dwe87 = resetn;
boot_iwe88 = resetn;
boot_dwe88 = resetn;
boot_iwe89 = resetn;
boot_dwe89 = resetn;
end
29: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = ~resetn;
boot_dwe29 = ~resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
boot_iwe50 = resetn;
boot_dwe50 = resetn;
boot_iwe51 = resetn;
boot_dwe51 = resetn;
boot_iwe52 = resetn;
boot_dwe52 = resetn;
boot_iwe53 = resetn;
boot_dwe53 = resetn;
boot_iwe54 = resetn;
boot_dwe54 = resetn;
boot_iwe55 = resetn;
boot_dwe55 = resetn;
boot_iwe56 = resetn;
boot_dwe56 = resetn;
boot_iwe57 = resetn;
boot_dwe57 = resetn;
boot_iwe58 = resetn;
boot_dwe58 = resetn;
boot_iwe59 = resetn;
boot_dwe59 = resetn;
boot_iwe60 = resetn;
boot_dwe60 = resetn;
boot_iwe61 = resetn;
boot_dwe61 = resetn;
boot_iwe62 = resetn;
boot_dwe62 = resetn;
boot_iwe63 = resetn;
boot_dwe63 = resetn;
boot_iwe64 = resetn;
boot_dwe64 = resetn;
boot_iwe65 = resetn;
boot_dwe65 = resetn;
boot_iwe66 = resetn;
boot_dwe66 = resetn;
boot_iwe67 = resetn;
boot_dwe67 = resetn;
boot_iwe68 = resetn;
boot_dwe68 = resetn;
boot_iwe69 = resetn;
boot_dwe69 = resetn;
boot_iwe70 = resetn;
boot_dwe70 = resetn;
boot_iwe71 = resetn;
boot_dwe71 = resetn;
boot_iwe72 = resetn;
boot_dwe72 = resetn;
boot_iwe73 = resetn;
boot_dwe73 = resetn;
boot_iwe74 = resetn;
boot_dwe74 = resetn;
boot_iwe75 = resetn;
boot_dwe75 = resetn;
boot_iwe76 = resetn;
boot_dwe76 = resetn;
boot_iwe77 = resetn;
boot_dwe77 = resetn;
boot_iwe78 = resetn;
boot_dwe78 = resetn;
boot_iwe79 = resetn;
boot_dwe79 = resetn;
boot_iwe80 = resetn;
boot_dwe80 = resetn;
boot_iwe81 = resetn;
boot_dwe81 = resetn;
boot_iwe82 = resetn;
boot_dwe82 = resetn;
boot_iwe83 = resetn;
boot_dwe83 = resetn;
boot_iwe84 = resetn;
boot_dwe84 = resetn;
boot_iwe85 = resetn;
boot_dwe85 = resetn;
boot_iwe86 = resetn;
boot_dwe86 = resetn;
boot_iwe87 = resetn;
boot_dwe87 = resetn;
boot_iwe88 = resetn;
boot_dwe88 = resetn;
boot_iwe89 = resetn;
boot_dwe89 = resetn;
end
30: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = ~resetn;
boot_dwe30 = ~resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
boot_iwe50 = resetn;
boot_dwe50 = resetn;
boot_iwe51 = resetn;
boot_dwe51 = resetn;
boot_iwe52 = resetn;
boot_dwe52 = resetn;
boot_iwe53 = resetn;
boot_dwe53 = resetn;
boot_iwe54 = resetn;
boot_dwe54 = resetn;
boot_iwe55 = resetn;
boot_dwe55 = resetn;
boot_iwe56 = resetn;
boot_dwe56 = resetn;
boot_iwe57 = resetn;
boot_dwe57 = resetn;
boot_iwe58 = resetn;
boot_dwe58 = resetn;
boot_iwe59 = resetn;
boot_dwe59 = resetn;
boot_iwe60 = resetn;
boot_dwe60 = resetn;
boot_iwe61 = resetn;
boot_dwe61 = resetn;
boot_iwe62 = resetn;
boot_dwe62 = resetn;
boot_iwe63 = resetn;
boot_dwe63 = resetn;
boot_iwe64 = resetn;
boot_dwe64 = resetn;
boot_iwe65 = resetn;
boot_dwe65 = resetn;
boot_iwe66 = resetn;
boot_dwe66 = resetn;
boot_iwe67 = resetn;
boot_dwe67 = resetn;
boot_iwe68 = resetn;
boot_dwe68 = resetn;
boot_iwe69 = resetn;
boot_dwe69 = resetn;
boot_iwe70 = resetn;
boot_dwe70 = resetn;
boot_iwe71 = resetn;
boot_dwe71 = resetn;
boot_iwe72 = resetn;
boot_dwe72 = resetn;
boot_iwe73 = resetn;
boot_dwe73 = resetn;
boot_iwe74 = resetn;
boot_dwe74 = resetn;
boot_iwe75 = resetn;
boot_dwe75 = resetn;
boot_iwe76 = resetn;
boot_dwe76 = resetn;
boot_iwe77 = resetn;
boot_dwe77 = resetn;
boot_iwe78 = resetn;
boot_dwe78 = resetn;
boot_iwe79 = resetn;
boot_dwe79 = resetn;
boot_iwe80 = resetn;
boot_dwe80 = resetn;
boot_iwe81 = resetn;
boot_dwe81 = resetn;
boot_iwe82 = resetn;
boot_dwe82 = resetn;
boot_iwe83 = resetn;
boot_dwe83 = resetn;
boot_iwe84 = resetn;
boot_dwe84 = resetn;
boot_iwe85 = resetn;
boot_dwe85 = resetn;
boot_iwe86 = resetn;
boot_dwe86 = resetn;
boot_iwe87 = resetn;
boot_dwe87 = resetn;
boot_iwe88 = resetn;
boot_dwe88 = resetn;
boot_iwe89 = resetn;
boot_dwe89 = resetn;
end
31: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = ~resetn;
boot_dwe31 = ~resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
boot_iwe50 = resetn;
boot_dwe50 = resetn;
boot_iwe51 = resetn;
boot_dwe51 = resetn;
boot_iwe52 = resetn;
boot_dwe52 = resetn;
boot_iwe53 = resetn;
boot_dwe53 = resetn;
boot_iwe54 = resetn;
boot_dwe54 = resetn;
boot_iwe55 = resetn;
boot_dwe55 = resetn;
boot_iwe56 = resetn;
boot_dwe56 = resetn;
boot_iwe57 = resetn;
boot_dwe57 = resetn;
boot_iwe58 = resetn;
boot_dwe58 = resetn;
boot_iwe59 = resetn;
boot_dwe59 = resetn;
boot_iwe60 = resetn;
boot_dwe60 = resetn;
boot_iwe61 = resetn;
boot_dwe61 = resetn;
boot_iwe62 = resetn;
boot_dwe62 = resetn;
boot_iwe63 = resetn;
boot_dwe63 = resetn;
boot_iwe64 = resetn;
boot_dwe64 = resetn;
boot_iwe65 = resetn;
boot_dwe65 = resetn;
boot_iwe66 = resetn;
boot_dwe66 = resetn;
boot_iwe67 = resetn;
boot_dwe67 = resetn;
boot_iwe68 = resetn;
boot_dwe68 = resetn;
boot_iwe69 = resetn;
boot_dwe69 = resetn;
boot_iwe70 = resetn;
boot_dwe70 = resetn;
boot_iwe71 = resetn;
boot_dwe71 = resetn;
boot_iwe72 = resetn;
boot_dwe72 = resetn;
boot_iwe73 = resetn;
boot_dwe73 = resetn;
boot_iwe74 = resetn;
boot_dwe74 = resetn;
boot_iwe75 = resetn;
boot_dwe75 = resetn;
boot_iwe76 = resetn;
boot_dwe76 = resetn;
boot_iwe77 = resetn;
boot_dwe77 = resetn;
boot_iwe78 = resetn;
boot_dwe78 = resetn;
boot_iwe79 = resetn;
boot_dwe79 = resetn;
boot_iwe80 = resetn;
boot_dwe80 = resetn;
boot_iwe81 = resetn;
boot_dwe81 = resetn;
boot_iwe82 = resetn;
boot_dwe82 = resetn;
boot_iwe83 = resetn;
boot_dwe83 = resetn;
boot_iwe84 = resetn;
boot_dwe84 = resetn;
boot_iwe85 = resetn;
boot_dwe85 = resetn;
boot_iwe86 = resetn;
boot_dwe86 = resetn;
boot_iwe87 = resetn;
boot_dwe87 = resetn;
boot_iwe88 = resetn;
boot_dwe88 = resetn;
boot_iwe89 = resetn;
boot_dwe89 = resetn;
end
32: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = ~resetn;
boot_dwe32 = ~resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
boot_iwe50 = resetn;
boot_dwe50 = resetn;
boot_iwe51 = resetn;
boot_dwe51 = resetn;
boot_iwe52 = resetn;
boot_dwe52 = resetn;
boot_iwe53 = resetn;
boot_dwe53 = resetn;
boot_iwe54 = resetn;
boot_dwe54 = resetn;
boot_iwe55 = resetn;
boot_dwe55 = resetn;
boot_iwe56 = resetn;
boot_dwe56 = resetn;
boot_iwe57 = resetn;
boot_dwe57 = resetn;
boot_iwe58 = resetn;
boot_dwe58 = resetn;
boot_iwe59 = resetn;
boot_dwe59 = resetn;
boot_iwe60 = resetn;
boot_dwe60 = resetn;
boot_iwe61 = resetn;
boot_dwe61 = resetn;
boot_iwe62 = resetn;
boot_dwe62 = resetn;
boot_iwe63 = resetn;
boot_dwe63 = resetn;
boot_iwe64 = resetn;
boot_dwe64 = resetn;
boot_iwe65 = resetn;
boot_dwe65 = resetn;
boot_iwe66 = resetn;
boot_dwe66 = resetn;
boot_iwe67 = resetn;
boot_dwe67 = resetn;
boot_iwe68 = resetn;
boot_dwe68 = resetn;
boot_iwe69 = resetn;
boot_dwe69 = resetn;
boot_iwe70 = resetn;
boot_dwe70 = resetn;
boot_iwe71 = resetn;
boot_dwe71 = resetn;
boot_iwe72 = resetn;
boot_dwe72 = resetn;
boot_iwe73 = resetn;
boot_dwe73 = resetn;
boot_iwe74 = resetn;
boot_dwe74 = resetn;
boot_iwe75 = resetn;
boot_dwe75 = resetn;
boot_iwe76 = resetn;
boot_dwe76 = resetn;
boot_iwe77 = resetn;
boot_dwe77 = resetn;
boot_iwe78 = resetn;
boot_dwe78 = resetn;
boot_iwe79 = resetn;
boot_dwe79 = resetn;
boot_iwe80 = resetn;
boot_dwe80 = resetn;
boot_iwe81 = resetn;
boot_dwe81 = resetn;
boot_iwe82 = resetn;
boot_dwe82 = resetn;
boot_iwe83 = resetn;
boot_dwe83 = resetn;
boot_iwe84 = resetn;
boot_dwe84 = resetn;
boot_iwe85 = resetn;
boot_dwe85 = resetn;
boot_iwe86 = resetn;
boot_dwe86 = resetn;
boot_iwe87 = resetn;
boot_dwe87 = resetn;
boot_iwe88 = resetn;
boot_dwe88 = resetn;
boot_iwe89 = resetn;
boot_dwe89 = resetn;
end
33: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = ~resetn;
boot_dwe33 = ~resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
boot_iwe50 = resetn;
boot_dwe50 = resetn;
boot_iwe51 = resetn;
boot_dwe51 = resetn;
boot_iwe52 = resetn;
boot_dwe52 = resetn;
boot_iwe53 = resetn;
boot_dwe53 = resetn;
boot_iwe54 = resetn;
boot_dwe54 = resetn;
boot_iwe55 = resetn;
boot_dwe55 = resetn;
boot_iwe56 = resetn;
boot_dwe56 = resetn;
boot_iwe57 = resetn;
boot_dwe57 = resetn;
boot_iwe58 = resetn;
boot_dwe58 = resetn;
boot_iwe59 = resetn;
boot_dwe59 = resetn;
boot_iwe60 = resetn;
boot_dwe60 = resetn;
boot_iwe61 = resetn;
boot_dwe61 = resetn;
boot_iwe62 = resetn;
boot_dwe62 = resetn;
boot_iwe63 = resetn;
boot_dwe63 = resetn;
boot_iwe64 = resetn;
boot_dwe64 = resetn;
boot_iwe65 = resetn;
boot_dwe65 = resetn;
boot_iwe66 = resetn;
boot_dwe66 = resetn;
boot_iwe67 = resetn;
boot_dwe67 = resetn;
boot_iwe68 = resetn;
boot_dwe68 = resetn;
boot_iwe69 = resetn;
boot_dwe69 = resetn;
boot_iwe70 = resetn;
boot_dwe70 = resetn;
boot_iwe71 = resetn;
boot_dwe71 = resetn;
boot_iwe72 = resetn;
boot_dwe72 = resetn;
boot_iwe73 = resetn;
boot_dwe73 = resetn;
boot_iwe74 = resetn;
boot_dwe74 = resetn;
boot_iwe75 = resetn;
boot_dwe75 = resetn;
boot_iwe76 = resetn;
boot_dwe76 = resetn;
boot_iwe77 = resetn;
boot_dwe77 = resetn;
boot_iwe78 = resetn;
boot_dwe78 = resetn;
boot_iwe79 = resetn;
boot_dwe79 = resetn;
boot_iwe80 = resetn;
boot_dwe80 = resetn;
boot_iwe81 = resetn;
boot_dwe81 = resetn;
boot_iwe82 = resetn;
boot_dwe82 = resetn;
boot_iwe83 = resetn;
boot_dwe83 = resetn;
boot_iwe84 = resetn;
boot_dwe84 = resetn;
boot_iwe85 = resetn;
boot_dwe85 = resetn;
boot_iwe86 = resetn;
boot_dwe86 = resetn;
boot_iwe87 = resetn;
boot_dwe87 = resetn;
boot_iwe88 = resetn;
boot_dwe88 = resetn;
boot_iwe89 = resetn;
boot_dwe89 = resetn;
end
34: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = ~resetn;
boot_dwe34 = ~resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
boot_iwe50 = resetn;
boot_dwe50 = resetn;
boot_iwe51 = resetn;
boot_dwe51 = resetn;
boot_iwe52 = resetn;
boot_dwe52 = resetn;
boot_iwe53 = resetn;
boot_dwe53 = resetn;
boot_iwe54 = resetn;
boot_dwe54 = resetn;
boot_iwe55 = resetn;
boot_dwe55 = resetn;
boot_iwe56 = resetn;
boot_dwe56 = resetn;
boot_iwe57 = resetn;
boot_dwe57 = resetn;
boot_iwe58 = resetn;
boot_dwe58 = resetn;
boot_iwe59 = resetn;
boot_dwe59 = resetn;
boot_iwe60 = resetn;
boot_dwe60 = resetn;
boot_iwe61 = resetn;
boot_dwe61 = resetn;
boot_iwe62 = resetn;
boot_dwe62 = resetn;
boot_iwe63 = resetn;
boot_dwe63 = resetn;
boot_iwe64 = resetn;
boot_dwe64 = resetn;
boot_iwe65 = resetn;
boot_dwe65 = resetn;
boot_iwe66 = resetn;
boot_dwe66 = resetn;
boot_iwe67 = resetn;
boot_dwe67 = resetn;
boot_iwe68 = resetn;
boot_dwe68 = resetn;
boot_iwe69 = resetn;
boot_dwe69 = resetn;
boot_iwe70 = resetn;
boot_dwe70 = resetn;
boot_iwe71 = resetn;
boot_dwe71 = resetn;
boot_iwe72 = resetn;
boot_dwe72 = resetn;
boot_iwe73 = resetn;
boot_dwe73 = resetn;
boot_iwe74 = resetn;
boot_dwe74 = resetn;
boot_iwe75 = resetn;
boot_dwe75 = resetn;
boot_iwe76 = resetn;
boot_dwe76 = resetn;
boot_iwe77 = resetn;
boot_dwe77 = resetn;
boot_iwe78 = resetn;
boot_dwe78 = resetn;
boot_iwe79 = resetn;
boot_dwe79 = resetn;
boot_iwe80 = resetn;
boot_dwe80 = resetn;
boot_iwe81 = resetn;
boot_dwe81 = resetn;
boot_iwe82 = resetn;
boot_dwe82 = resetn;
boot_iwe83 = resetn;
boot_dwe83 = resetn;
boot_iwe84 = resetn;
boot_dwe84 = resetn;
boot_iwe85 = resetn;
boot_dwe85 = resetn;
boot_iwe86 = resetn;
boot_dwe86 = resetn;
boot_iwe87 = resetn;
boot_dwe87 = resetn;
boot_iwe88 = resetn;
boot_dwe88 = resetn;
boot_iwe89 = resetn;
boot_dwe89 = resetn;
end
35: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = ~resetn;
boot_dwe35 = ~resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
boot_iwe50 = resetn;
boot_dwe50 = resetn;
boot_iwe51 = resetn;
boot_dwe51 = resetn;
boot_iwe52 = resetn;
boot_dwe52 = resetn;
boot_iwe53 = resetn;
boot_dwe53 = resetn;
boot_iwe54 = resetn;
boot_dwe54 = resetn;
boot_iwe55 = resetn;
boot_dwe55 = resetn;
boot_iwe56 = resetn;
boot_dwe56 = resetn;
boot_iwe57 = resetn;
boot_dwe57 = resetn;
boot_iwe58 = resetn;
boot_dwe58 = resetn;
boot_iwe59 = resetn;
boot_dwe59 = resetn;
boot_iwe60 = resetn;
boot_dwe60 = resetn;
boot_iwe61 = resetn;
boot_dwe61 = resetn;
boot_iwe62 = resetn;
boot_dwe62 = resetn;
boot_iwe63 = resetn;
boot_dwe63 = resetn;
boot_iwe64 = resetn;
boot_dwe64 = resetn;
boot_iwe65 = resetn;
boot_dwe65 = resetn;
boot_iwe66 = resetn;
boot_dwe66 = resetn;
boot_iwe67 = resetn;
boot_dwe67 = resetn;
boot_iwe68 = resetn;
boot_dwe68 = resetn;
boot_iwe69 = resetn;
boot_dwe69 = resetn;
boot_iwe70 = resetn;
boot_dwe70 = resetn;
boot_iwe71 = resetn;
boot_dwe71 = resetn;
boot_iwe72 = resetn;
boot_dwe72 = resetn;
boot_iwe73 = resetn;
boot_dwe73 = resetn;
boot_iwe74 = resetn;
boot_dwe74 = resetn;
boot_iwe75 = resetn;
boot_dwe75 = resetn;
boot_iwe76 = resetn;
boot_dwe76 = resetn;
boot_iwe77 = resetn;
boot_dwe77 = resetn;
boot_iwe78 = resetn;
boot_dwe78 = resetn;
boot_iwe79 = resetn;
boot_dwe79 = resetn;
boot_iwe80 = resetn;
boot_dwe80 = resetn;
boot_iwe81 = resetn;
boot_dwe81 = resetn;
boot_iwe82 = resetn;
boot_dwe82 = resetn;
boot_iwe83 = resetn;
boot_dwe83 = resetn;
boot_iwe84 = resetn;
boot_dwe84 = resetn;
boot_iwe85 = resetn;
boot_dwe85 = resetn;
boot_iwe86 = resetn;
boot_dwe86 = resetn;
boot_iwe87 = resetn;
boot_dwe87 = resetn;
boot_iwe88 = resetn;
boot_dwe88 = resetn;
boot_iwe89 = resetn;
boot_dwe89 = resetn;
end
36: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = ~resetn;
boot_dwe36 = ~resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
boot_iwe50 = resetn;
boot_dwe50 = resetn;
boot_iwe51 = resetn;
boot_dwe51 = resetn;
boot_iwe52 = resetn;
boot_dwe52 = resetn;
boot_iwe53 = resetn;
boot_dwe53 = resetn;
boot_iwe54 = resetn;
boot_dwe54 = resetn;
boot_iwe55 = resetn;
boot_dwe55 = resetn;
boot_iwe56 = resetn;
boot_dwe56 = resetn;
boot_iwe57 = resetn;
boot_dwe57 = resetn;
boot_iwe58 = resetn;
boot_dwe58 = resetn;
boot_iwe59 = resetn;
boot_dwe59 = resetn;
boot_iwe60 = resetn;
boot_dwe60 = resetn;
boot_iwe61 = resetn;
boot_dwe61 = resetn;
boot_iwe62 = resetn;
boot_dwe62 = resetn;
boot_iwe63 = resetn;
boot_dwe63 = resetn;
boot_iwe64 = resetn;
boot_dwe64 = resetn;
boot_iwe65 = resetn;
boot_dwe65 = resetn;
boot_iwe66 = resetn;
boot_dwe66 = resetn;
boot_iwe67 = resetn;
boot_dwe67 = resetn;
boot_iwe68 = resetn;
boot_dwe68 = resetn;
boot_iwe69 = resetn;
boot_dwe69 = resetn;
boot_iwe70 = resetn;
boot_dwe70 = resetn;
boot_iwe71 = resetn;
boot_dwe71 = resetn;
boot_iwe72 = resetn;
boot_dwe72 = resetn;
boot_iwe73 = resetn;
boot_dwe73 = resetn;
boot_iwe74 = resetn;
boot_dwe74 = resetn;
boot_iwe75 = resetn;
boot_dwe75 = resetn;
boot_iwe76 = resetn;
boot_dwe76 = resetn;
boot_iwe77 = resetn;
boot_dwe77 = resetn;
boot_iwe78 = resetn;
boot_dwe78 = resetn;
boot_iwe79 = resetn;
boot_dwe79 = resetn;
boot_iwe80 = resetn;
boot_dwe80 = resetn;
boot_iwe81 = resetn;
boot_dwe81 = resetn;
boot_iwe82 = resetn;
boot_dwe82 = resetn;
boot_iwe83 = resetn;
boot_dwe83 = resetn;
boot_iwe84 = resetn;
boot_dwe84 = resetn;
boot_iwe85 = resetn;
boot_dwe85 = resetn;
boot_iwe86 = resetn;
boot_dwe86 = resetn;
boot_iwe87 = resetn;
boot_dwe87 = resetn;
boot_iwe88 = resetn;
boot_dwe88 = resetn;
boot_iwe89 = resetn;
boot_dwe89 = resetn;
end
37: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = ~resetn;
boot_dwe37 = ~resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
boot_iwe50 = resetn;
boot_dwe50 = resetn;
boot_iwe51 = resetn;
boot_dwe51 = resetn;
boot_iwe52 = resetn;
boot_dwe52 = resetn;
boot_iwe53 = resetn;
boot_dwe53 = resetn;
boot_iwe54 = resetn;
boot_dwe54 = resetn;
boot_iwe55 = resetn;
boot_dwe55 = resetn;
boot_iwe56 = resetn;
boot_dwe56 = resetn;
boot_iwe57 = resetn;
boot_dwe57 = resetn;
boot_iwe58 = resetn;
boot_dwe58 = resetn;
boot_iwe59 = resetn;
boot_dwe59 = resetn;
boot_iwe60 = resetn;
boot_dwe60 = resetn;
boot_iwe61 = resetn;
boot_dwe61 = resetn;
boot_iwe62 = resetn;
boot_dwe62 = resetn;
boot_iwe63 = resetn;
boot_dwe63 = resetn;
boot_iwe64 = resetn;
boot_dwe64 = resetn;
boot_iwe65 = resetn;
boot_dwe65 = resetn;
boot_iwe66 = resetn;
boot_dwe66 = resetn;
boot_iwe67 = resetn;
boot_dwe67 = resetn;
boot_iwe68 = resetn;
boot_dwe68 = resetn;
boot_iwe69 = resetn;
boot_dwe69 = resetn;
boot_iwe70 = resetn;
boot_dwe70 = resetn;
boot_iwe71 = resetn;
boot_dwe71 = resetn;
boot_iwe72 = resetn;
boot_dwe72 = resetn;
boot_iwe73 = resetn;
boot_dwe73 = resetn;
boot_iwe74 = resetn;
boot_dwe74 = resetn;
boot_iwe75 = resetn;
boot_dwe75 = resetn;
boot_iwe76 = resetn;
boot_dwe76 = resetn;
boot_iwe77 = resetn;
boot_dwe77 = resetn;
boot_iwe78 = resetn;
boot_dwe78 = resetn;
boot_iwe79 = resetn;
boot_dwe79 = resetn;
boot_iwe80 = resetn;
boot_dwe80 = resetn;
boot_iwe81 = resetn;
boot_dwe81 = resetn;
boot_iwe82 = resetn;
boot_dwe82 = resetn;
boot_iwe83 = resetn;
boot_dwe83 = resetn;
boot_iwe84 = resetn;
boot_dwe84 = resetn;
boot_iwe85 = resetn;
boot_dwe85 = resetn;
boot_iwe86 = resetn;
boot_dwe86 = resetn;
boot_iwe87 = resetn;
boot_dwe87 = resetn;
boot_iwe88 = resetn;
boot_dwe88 = resetn;
boot_iwe89 = resetn;
boot_dwe89 = resetn;
end
38: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = ~resetn;
boot_dwe38 = ~resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
boot_iwe50 = resetn;
boot_dwe50 = resetn;
boot_iwe51 = resetn;
boot_dwe51 = resetn;
boot_iwe52 = resetn;
boot_dwe52 = resetn;
boot_iwe53 = resetn;
boot_dwe53 = resetn;
boot_iwe54 = resetn;
boot_dwe54 = resetn;
boot_iwe55 = resetn;
boot_dwe55 = resetn;
boot_iwe56 = resetn;
boot_dwe56 = resetn;
boot_iwe57 = resetn;
boot_dwe57 = resetn;
boot_iwe58 = resetn;
boot_dwe58 = resetn;
boot_iwe59 = resetn;
boot_dwe59 = resetn;
boot_iwe60 = resetn;
boot_dwe60 = resetn;
boot_iwe61 = resetn;
boot_dwe61 = resetn;
boot_iwe62 = resetn;
boot_dwe62 = resetn;
boot_iwe63 = resetn;
boot_dwe63 = resetn;
boot_iwe64 = resetn;
boot_dwe64 = resetn;
boot_iwe65 = resetn;
boot_dwe65 = resetn;
boot_iwe66 = resetn;
boot_dwe66 = resetn;
boot_iwe67 = resetn;
boot_dwe67 = resetn;
boot_iwe68 = resetn;
boot_dwe68 = resetn;
boot_iwe69 = resetn;
boot_dwe69 = resetn;
boot_iwe70 = resetn;
boot_dwe70 = resetn;
boot_iwe71 = resetn;
boot_dwe71 = resetn;
boot_iwe72 = resetn;
boot_dwe72 = resetn;
boot_iwe73 = resetn;
boot_dwe73 = resetn;
boot_iwe74 = resetn;
boot_dwe74 = resetn;
boot_iwe75 = resetn;
boot_dwe75 = resetn;
boot_iwe76 = resetn;
boot_dwe76 = resetn;
boot_iwe77 = resetn;
boot_dwe77 = resetn;
boot_iwe78 = resetn;
boot_dwe78 = resetn;
boot_iwe79 = resetn;
boot_dwe79 = resetn;
boot_iwe80 = resetn;
boot_dwe80 = resetn;
boot_iwe81 = resetn;
boot_dwe81 = resetn;
boot_iwe82 = resetn;
boot_dwe82 = resetn;
boot_iwe83 = resetn;
boot_dwe83 = resetn;
boot_iwe84 = resetn;
boot_dwe84 = resetn;
boot_iwe85 = resetn;
boot_dwe85 = resetn;
boot_iwe86 = resetn;
boot_dwe86 = resetn;
boot_iwe87 = resetn;
boot_dwe87 = resetn;
boot_iwe88 = resetn;
boot_dwe88 = resetn;
boot_iwe89 = resetn;
boot_dwe89 = resetn;
end
39: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = ~resetn;
boot_dwe39 = ~resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
boot_iwe50 = resetn;
boot_dwe50 = resetn;
boot_iwe51 = resetn;
boot_dwe51 = resetn;
boot_iwe52 = resetn;
boot_dwe52 = resetn;
boot_iwe53 = resetn;
boot_dwe53 = resetn;
boot_iwe54 = resetn;
boot_dwe54 = resetn;
boot_iwe55 = resetn;
boot_dwe55 = resetn;
boot_iwe56 = resetn;
boot_dwe56 = resetn;
boot_iwe57 = resetn;
boot_dwe57 = resetn;
boot_iwe58 = resetn;
boot_dwe58 = resetn;
boot_iwe59 = resetn;
boot_dwe59 = resetn;
boot_iwe60 = resetn;
boot_dwe60 = resetn;
boot_iwe61 = resetn;
boot_dwe61 = resetn;
boot_iwe62 = resetn;
boot_dwe62 = resetn;
boot_iwe63 = resetn;
boot_dwe63 = resetn;
boot_iwe64 = resetn;
boot_dwe64 = resetn;
boot_iwe65 = resetn;
boot_dwe65 = resetn;
boot_iwe66 = resetn;
boot_dwe66 = resetn;
boot_iwe67 = resetn;
boot_dwe67 = resetn;
boot_iwe68 = resetn;
boot_dwe68 = resetn;
boot_iwe69 = resetn;
boot_dwe69 = resetn;
boot_iwe70 = resetn;
boot_dwe70 = resetn;
boot_iwe71 = resetn;
boot_dwe71 = resetn;
boot_iwe72 = resetn;
boot_dwe72 = resetn;
boot_iwe73 = resetn;
boot_dwe73 = resetn;
boot_iwe74 = resetn;
boot_dwe74 = resetn;
boot_iwe75 = resetn;
boot_dwe75 = resetn;
boot_iwe76 = resetn;
boot_dwe76 = resetn;
boot_iwe77 = resetn;
boot_dwe77 = resetn;
boot_iwe78 = resetn;
boot_dwe78 = resetn;
boot_iwe79 = resetn;
boot_dwe79 = resetn;
boot_iwe80 = resetn;
boot_dwe80 = resetn;
boot_iwe81 = resetn;
boot_dwe81 = resetn;
boot_iwe82 = resetn;
boot_dwe82 = resetn;
boot_iwe83 = resetn;
boot_dwe83 = resetn;
boot_iwe84 = resetn;
boot_dwe84 = resetn;
boot_iwe85 = resetn;
boot_dwe85 = resetn;
boot_iwe86 = resetn;
boot_dwe86 = resetn;
boot_iwe87 = resetn;
boot_dwe87 = resetn;
boot_iwe88 = resetn;
boot_dwe88 = resetn;
boot_iwe89 = resetn;
boot_dwe89 = resetn;
end
40: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = ~resetn;
boot_dwe40 = ~resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
boot_iwe50 = resetn;
boot_dwe50 = resetn;
boot_iwe51 = resetn;
boot_dwe51 = resetn;
boot_iwe52 = resetn;
boot_dwe52 = resetn;
boot_iwe53 = resetn;
boot_dwe53 = resetn;
boot_iwe54 = resetn;
boot_dwe54 = resetn;
boot_iwe55 = resetn;
boot_dwe55 = resetn;
boot_iwe56 = resetn;
boot_dwe56 = resetn;
boot_iwe57 = resetn;
boot_dwe57 = resetn;
boot_iwe58 = resetn;
boot_dwe58 = resetn;
boot_iwe59 = resetn;
boot_dwe59 = resetn;
boot_iwe60 = resetn;
boot_dwe60 = resetn;
boot_iwe61 = resetn;
boot_dwe61 = resetn;
boot_iwe62 = resetn;
boot_dwe62 = resetn;
boot_iwe63 = resetn;
boot_dwe63 = resetn;
boot_iwe64 = resetn;
boot_dwe64 = resetn;
boot_iwe65 = resetn;
boot_dwe65 = resetn;
boot_iwe66 = resetn;
boot_dwe66 = resetn;
boot_iwe67 = resetn;
boot_dwe67 = resetn;
boot_iwe68 = resetn;
boot_dwe68 = resetn;
boot_iwe69 = resetn;
boot_dwe69 = resetn;
boot_iwe70 = resetn;
boot_dwe70 = resetn;
boot_iwe71 = resetn;
boot_dwe71 = resetn;
boot_iwe72 = resetn;
boot_dwe72 = resetn;
boot_iwe73 = resetn;
boot_dwe73 = resetn;
boot_iwe74 = resetn;
boot_dwe74 = resetn;
boot_iwe75 = resetn;
boot_dwe75 = resetn;
boot_iwe76 = resetn;
boot_dwe76 = resetn;
boot_iwe77 = resetn;
boot_dwe77 = resetn;
boot_iwe78 = resetn;
boot_dwe78 = resetn;
boot_iwe79 = resetn;
boot_dwe79 = resetn;
boot_iwe80 = resetn;
boot_dwe80 = resetn;
boot_iwe81 = resetn;
boot_dwe81 = resetn;
boot_iwe82 = resetn;
boot_dwe82 = resetn;
boot_iwe83 = resetn;
boot_dwe83 = resetn;
boot_iwe84 = resetn;
boot_dwe84 = resetn;
boot_iwe85 = resetn;
boot_dwe85 = resetn;
boot_iwe86 = resetn;
boot_dwe86 = resetn;
boot_iwe87 = resetn;
boot_dwe87 = resetn;
boot_iwe88 = resetn;
boot_dwe88 = resetn;
boot_iwe89 = resetn;
boot_dwe89 = resetn;
end
41: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = ~resetn;
boot_dwe41 = ~resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
boot_iwe50 = resetn;
boot_dwe50 = resetn;
boot_iwe51 = resetn;
boot_dwe51 = resetn;
boot_iwe52 = resetn;
boot_dwe52 = resetn;
boot_iwe53 = resetn;
boot_dwe53 = resetn;
boot_iwe54 = resetn;
boot_dwe54 = resetn;
boot_iwe55 = resetn;
boot_dwe55 = resetn;
boot_iwe56 = resetn;
boot_dwe56 = resetn;
boot_iwe57 = resetn;
boot_dwe57 = resetn;
boot_iwe58 = resetn;
boot_dwe58 = resetn;
boot_iwe59 = resetn;
boot_dwe59 = resetn;
boot_iwe60 = resetn;
boot_dwe60 = resetn;
boot_iwe61 = resetn;
boot_dwe61 = resetn;
boot_iwe62 = resetn;
boot_dwe62 = resetn;
boot_iwe63 = resetn;
boot_dwe63 = resetn;
boot_iwe64 = resetn;
boot_dwe64 = resetn;
boot_iwe65 = resetn;
boot_dwe65 = resetn;
boot_iwe66 = resetn;
boot_dwe66 = resetn;
boot_iwe67 = resetn;
boot_dwe67 = resetn;
boot_iwe68 = resetn;
boot_dwe68 = resetn;
boot_iwe69 = resetn;
boot_dwe69 = resetn;
boot_iwe70 = resetn;
boot_dwe70 = resetn;
boot_iwe71 = resetn;
boot_dwe71 = resetn;
boot_iwe72 = resetn;
boot_dwe72 = resetn;
boot_iwe73 = resetn;
boot_dwe73 = resetn;
boot_iwe74 = resetn;
boot_dwe74 = resetn;
boot_iwe75 = resetn;
boot_dwe75 = resetn;
boot_iwe76 = resetn;
boot_dwe76 = resetn;
boot_iwe77 = resetn;
boot_dwe77 = resetn;
boot_iwe78 = resetn;
boot_dwe78 = resetn;
boot_iwe79 = resetn;
boot_dwe79 = resetn;
boot_iwe80 = resetn;
boot_dwe80 = resetn;
boot_iwe81 = resetn;
boot_dwe81 = resetn;
boot_iwe82 = resetn;
boot_dwe82 = resetn;
boot_iwe83 = resetn;
boot_dwe83 = resetn;
boot_iwe84 = resetn;
boot_dwe84 = resetn;
boot_iwe85 = resetn;
boot_dwe85 = resetn;
boot_iwe86 = resetn;
boot_dwe86 = resetn;
boot_iwe87 = resetn;
boot_dwe87 = resetn;
boot_iwe88 = resetn;
boot_dwe88 = resetn;
boot_iwe89 = resetn;
boot_dwe89 = resetn;
end
42: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = ~resetn;
boot_dwe42 = ~resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
boot_iwe50 = resetn;
boot_dwe50 = resetn;
boot_iwe51 = resetn;
boot_dwe51 = resetn;
boot_iwe52 = resetn;
boot_dwe52 = resetn;
boot_iwe53 = resetn;
boot_dwe53 = resetn;
boot_iwe54 = resetn;
boot_dwe54 = resetn;
boot_iwe55 = resetn;
boot_dwe55 = resetn;
boot_iwe56 = resetn;
boot_dwe56 = resetn;
boot_iwe57 = resetn;
boot_dwe57 = resetn;
boot_iwe58 = resetn;
boot_dwe58 = resetn;
boot_iwe59 = resetn;
boot_dwe59 = resetn;
boot_iwe60 = resetn;
boot_dwe60 = resetn;
boot_iwe61 = resetn;
boot_dwe61 = resetn;
boot_iwe62 = resetn;
boot_dwe62 = resetn;
boot_iwe63 = resetn;
boot_dwe63 = resetn;
boot_iwe64 = resetn;
boot_dwe64 = resetn;
boot_iwe65 = resetn;
boot_dwe65 = resetn;
boot_iwe66 = resetn;
boot_dwe66 = resetn;
boot_iwe67 = resetn;
boot_dwe67 = resetn;
boot_iwe68 = resetn;
boot_dwe68 = resetn;
boot_iwe69 = resetn;
boot_dwe69 = resetn;
boot_iwe70 = resetn;
boot_dwe70 = resetn;
boot_iwe71 = resetn;
boot_dwe71 = resetn;
boot_iwe72 = resetn;
boot_dwe72 = resetn;
boot_iwe73 = resetn;
boot_dwe73 = resetn;
boot_iwe74 = resetn;
boot_dwe74 = resetn;
boot_iwe75 = resetn;
boot_dwe75 = resetn;
boot_iwe76 = resetn;
boot_dwe76 = resetn;
boot_iwe77 = resetn;
boot_dwe77 = resetn;
boot_iwe78 = resetn;
boot_dwe78 = resetn;
boot_iwe79 = resetn;
boot_dwe79 = resetn;
boot_iwe80 = resetn;
boot_dwe80 = resetn;
boot_iwe81 = resetn;
boot_dwe81 = resetn;
boot_iwe82 = resetn;
boot_dwe82 = resetn;
boot_iwe83 = resetn;
boot_dwe83 = resetn;
boot_iwe84 = resetn;
boot_dwe84 = resetn;
boot_iwe85 = resetn;
boot_dwe85 = resetn;
boot_iwe86 = resetn;
boot_dwe86 = resetn;
boot_iwe87 = resetn;
boot_dwe87 = resetn;
boot_iwe88 = resetn;
boot_dwe88 = resetn;
boot_iwe89 = resetn;
boot_dwe89 = resetn;
end
43: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = ~resetn;
boot_dwe43 = ~resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
boot_iwe50 = resetn;
boot_dwe50 = resetn;
boot_iwe51 = resetn;
boot_dwe51 = resetn;
boot_iwe52 = resetn;
boot_dwe52 = resetn;
boot_iwe53 = resetn;
boot_dwe53 = resetn;
boot_iwe54 = resetn;
boot_dwe54 = resetn;
boot_iwe55 = resetn;
boot_dwe55 = resetn;
boot_iwe56 = resetn;
boot_dwe56 = resetn;
boot_iwe57 = resetn;
boot_dwe57 = resetn;
boot_iwe58 = resetn;
boot_dwe58 = resetn;
boot_iwe59 = resetn;
boot_dwe59 = resetn;
boot_iwe60 = resetn;
boot_dwe60 = resetn;
boot_iwe61 = resetn;
boot_dwe61 = resetn;
boot_iwe62 = resetn;
boot_dwe62 = resetn;
boot_iwe63 = resetn;
boot_dwe63 = resetn;
boot_iwe64 = resetn;
boot_dwe64 = resetn;
boot_iwe65 = resetn;
boot_dwe65 = resetn;
boot_iwe66 = resetn;
boot_dwe66 = resetn;
boot_iwe67 = resetn;
boot_dwe67 = resetn;
boot_iwe68 = resetn;
boot_dwe68 = resetn;
boot_iwe69 = resetn;
boot_dwe69 = resetn;
boot_iwe70 = resetn;
boot_dwe70 = resetn;
boot_iwe71 = resetn;
boot_dwe71 = resetn;
boot_iwe72 = resetn;
boot_dwe72 = resetn;
boot_iwe73 = resetn;
boot_dwe73 = resetn;
boot_iwe74 = resetn;
boot_dwe74 = resetn;
boot_iwe75 = resetn;
boot_dwe75 = resetn;
boot_iwe76 = resetn;
boot_dwe76 = resetn;
boot_iwe77 = resetn;
boot_dwe77 = resetn;
boot_iwe78 = resetn;
boot_dwe78 = resetn;
boot_iwe79 = resetn;
boot_dwe79 = resetn;
boot_iwe80 = resetn;
boot_dwe80 = resetn;
boot_iwe81 = resetn;
boot_dwe81 = resetn;
boot_iwe82 = resetn;
boot_dwe82 = resetn;
boot_iwe83 = resetn;
boot_dwe83 = resetn;
boot_iwe84 = resetn;
boot_dwe84 = resetn;
boot_iwe85 = resetn;
boot_dwe85 = resetn;
boot_iwe86 = resetn;
boot_dwe86 = resetn;
boot_iwe87 = resetn;
boot_dwe87 = resetn;
boot_iwe88 = resetn;
boot_dwe88 = resetn;
boot_iwe89 = resetn;
boot_dwe89 = resetn;
end
44: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = ~resetn;
boot_dwe44 = ~resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
boot_iwe50 = resetn;
boot_dwe50 = resetn;
boot_iwe51 = resetn;
boot_dwe51 = resetn;
boot_iwe52 = resetn;
boot_dwe52 = resetn;
boot_iwe53 = resetn;
boot_dwe53 = resetn;
boot_iwe54 = resetn;
boot_dwe54 = resetn;
boot_iwe55 = resetn;
boot_dwe55 = resetn;
boot_iwe56 = resetn;
boot_dwe56 = resetn;
boot_iwe57 = resetn;
boot_dwe57 = resetn;
boot_iwe58 = resetn;
boot_dwe58 = resetn;
boot_iwe59 = resetn;
boot_dwe59 = resetn;
boot_iwe60 = resetn;
boot_dwe60 = resetn;
boot_iwe61 = resetn;
boot_dwe61 = resetn;
boot_iwe62 = resetn;
boot_dwe62 = resetn;
boot_iwe63 = resetn;
boot_dwe63 = resetn;
boot_iwe64 = resetn;
boot_dwe64 = resetn;
boot_iwe65 = resetn;
boot_dwe65 = resetn;
boot_iwe66 = resetn;
boot_dwe66 = resetn;
boot_iwe67 = resetn;
boot_dwe67 = resetn;
boot_iwe68 = resetn;
boot_dwe68 = resetn;
boot_iwe69 = resetn;
boot_dwe69 = resetn;
boot_iwe70 = resetn;
boot_dwe70 = resetn;
boot_iwe71 = resetn;
boot_dwe71 = resetn;
boot_iwe72 = resetn;
boot_dwe72 = resetn;
boot_iwe73 = resetn;
boot_dwe73 = resetn;
boot_iwe74 = resetn;
boot_dwe74 = resetn;
boot_iwe75 = resetn;
boot_dwe75 = resetn;
boot_iwe76 = resetn;
boot_dwe76 = resetn;
boot_iwe77 = resetn;
boot_dwe77 = resetn;
boot_iwe78 = resetn;
boot_dwe78 = resetn;
boot_iwe79 = resetn;
boot_dwe79 = resetn;
boot_iwe80 = resetn;
boot_dwe80 = resetn;
boot_iwe81 = resetn;
boot_dwe81 = resetn;
boot_iwe82 = resetn;
boot_dwe82 = resetn;
boot_iwe83 = resetn;
boot_dwe83 = resetn;
boot_iwe84 = resetn;
boot_dwe84 = resetn;
boot_iwe85 = resetn;
boot_dwe85 = resetn;
boot_iwe86 = resetn;
boot_dwe86 = resetn;
boot_iwe87 = resetn;
boot_dwe87 = resetn;
boot_iwe88 = resetn;
boot_dwe88 = resetn;
boot_iwe89 = resetn;
boot_dwe89 = resetn;
end
45: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = ~resetn;
boot_dwe45 = ~resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
boot_iwe50 = resetn;
boot_dwe50 = resetn;
boot_iwe51 = resetn;
boot_dwe51 = resetn;
boot_iwe52 = resetn;
boot_dwe52 = resetn;
boot_iwe53 = resetn;
boot_dwe53 = resetn;
boot_iwe54 = resetn;
boot_dwe54 = resetn;
boot_iwe55 = resetn;
boot_dwe55 = resetn;
boot_iwe56 = resetn;
boot_dwe56 = resetn;
boot_iwe57 = resetn;
boot_dwe57 = resetn;
boot_iwe58 = resetn;
boot_dwe58 = resetn;
boot_iwe59 = resetn;
boot_dwe59 = resetn;
boot_iwe60 = resetn;
boot_dwe60 = resetn;
boot_iwe61 = resetn;
boot_dwe61 = resetn;
boot_iwe62 = resetn;
boot_dwe62 = resetn;
boot_iwe63 = resetn;
boot_dwe63 = resetn;
boot_iwe64 = resetn;
boot_dwe64 = resetn;
boot_iwe65 = resetn;
boot_dwe65 = resetn;
boot_iwe66 = resetn;
boot_dwe66 = resetn;
boot_iwe67 = resetn;
boot_dwe67 = resetn;
boot_iwe68 = resetn;
boot_dwe68 = resetn;
boot_iwe69 = resetn;
boot_dwe69 = resetn;
boot_iwe70 = resetn;
boot_dwe70 = resetn;
boot_iwe71 = resetn;
boot_dwe71 = resetn;
boot_iwe72 = resetn;
boot_dwe72 = resetn;
boot_iwe73 = resetn;
boot_dwe73 = resetn;
boot_iwe74 = resetn;
boot_dwe74 = resetn;
boot_iwe75 = resetn;
boot_dwe75 = resetn;
boot_iwe76 = resetn;
boot_dwe76 = resetn;
boot_iwe77 = resetn;
boot_dwe77 = resetn;
boot_iwe78 = resetn;
boot_dwe78 = resetn;
boot_iwe79 = resetn;
boot_dwe79 = resetn;
boot_iwe80 = resetn;
boot_dwe80 = resetn;
boot_iwe81 = resetn;
boot_dwe81 = resetn;
boot_iwe82 = resetn;
boot_dwe82 = resetn;
boot_iwe83 = resetn;
boot_dwe83 = resetn;
boot_iwe84 = resetn;
boot_dwe84 = resetn;
boot_iwe85 = resetn;
boot_dwe85 = resetn;
boot_iwe86 = resetn;
boot_dwe86 = resetn;
boot_iwe87 = resetn;
boot_dwe87 = resetn;
boot_iwe88 = resetn;
boot_dwe88 = resetn;
boot_iwe89 = resetn;
boot_dwe89 = resetn;
end
46: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = ~resetn;
boot_dwe46 = ~resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
boot_iwe50 = resetn;
boot_dwe50 = resetn;
boot_iwe51 = resetn;
boot_dwe51 = resetn;
boot_iwe52 = resetn;
boot_dwe52 = resetn;
boot_iwe53 = resetn;
boot_dwe53 = resetn;
boot_iwe54 = resetn;
boot_dwe54 = resetn;
boot_iwe55 = resetn;
boot_dwe55 = resetn;
boot_iwe56 = resetn;
boot_dwe56 = resetn;
boot_iwe57 = resetn;
boot_dwe57 = resetn;
boot_iwe58 = resetn;
boot_dwe58 = resetn;
boot_iwe59 = resetn;
boot_dwe59 = resetn;
boot_iwe60 = resetn;
boot_dwe60 = resetn;
boot_iwe61 = resetn;
boot_dwe61 = resetn;
boot_iwe62 = resetn;
boot_dwe62 = resetn;
boot_iwe63 = resetn;
boot_dwe63 = resetn;
boot_iwe64 = resetn;
boot_dwe64 = resetn;
boot_iwe65 = resetn;
boot_dwe65 = resetn;
boot_iwe66 = resetn;
boot_dwe66 = resetn;
boot_iwe67 = resetn;
boot_dwe67 = resetn;
boot_iwe68 = resetn;
boot_dwe68 = resetn;
boot_iwe69 = resetn;
boot_dwe69 = resetn;
boot_iwe70 = resetn;
boot_dwe70 = resetn;
boot_iwe71 = resetn;
boot_dwe71 = resetn;
boot_iwe72 = resetn;
boot_dwe72 = resetn;
boot_iwe73 = resetn;
boot_dwe73 = resetn;
boot_iwe74 = resetn;
boot_dwe74 = resetn;
boot_iwe75 = resetn;
boot_dwe75 = resetn;
boot_iwe76 = resetn;
boot_dwe76 = resetn;
boot_iwe77 = resetn;
boot_dwe77 = resetn;
boot_iwe78 = resetn;
boot_dwe78 = resetn;
boot_iwe79 = resetn;
boot_dwe79 = resetn;
boot_iwe80 = resetn;
boot_dwe80 = resetn;
boot_iwe81 = resetn;
boot_dwe81 = resetn;
boot_iwe82 = resetn;
boot_dwe82 = resetn;
boot_iwe83 = resetn;
boot_dwe83 = resetn;
boot_iwe84 = resetn;
boot_dwe84 = resetn;
boot_iwe85 = resetn;
boot_dwe85 = resetn;
boot_iwe86 = resetn;
boot_dwe86 = resetn;
boot_iwe87 = resetn;
boot_dwe87 = resetn;
boot_iwe88 = resetn;
boot_dwe88 = resetn;
boot_iwe89 = resetn;
boot_dwe89 = resetn;
end
47: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = ~resetn;
boot_dwe47 = ~resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
boot_iwe50 = resetn;
boot_dwe50 = resetn;
boot_iwe51 = resetn;
boot_dwe51 = resetn;
boot_iwe52 = resetn;
boot_dwe52 = resetn;
boot_iwe53 = resetn;
boot_dwe53 = resetn;
boot_iwe54 = resetn;
boot_dwe54 = resetn;
boot_iwe55 = resetn;
boot_dwe55 = resetn;
boot_iwe56 = resetn;
boot_dwe56 = resetn;
boot_iwe57 = resetn;
boot_dwe57 = resetn;
boot_iwe58 = resetn;
boot_dwe58 = resetn;
boot_iwe59 = resetn;
boot_dwe59 = resetn;
boot_iwe60 = resetn;
boot_dwe60 = resetn;
boot_iwe61 = resetn;
boot_dwe61 = resetn;
boot_iwe62 = resetn;
boot_dwe62 = resetn;
boot_iwe63 = resetn;
boot_dwe63 = resetn;
boot_iwe64 = resetn;
boot_dwe64 = resetn;
boot_iwe65 = resetn;
boot_dwe65 = resetn;
boot_iwe66 = resetn;
boot_dwe66 = resetn;
boot_iwe67 = resetn;
boot_dwe67 = resetn;
boot_iwe68 = resetn;
boot_dwe68 = resetn;
boot_iwe69 = resetn;
boot_dwe69 = resetn;
boot_iwe70 = resetn;
boot_dwe70 = resetn;
boot_iwe71 = resetn;
boot_dwe71 = resetn;
boot_iwe72 = resetn;
boot_dwe72 = resetn;
boot_iwe73 = resetn;
boot_dwe73 = resetn;
boot_iwe74 = resetn;
boot_dwe74 = resetn;
boot_iwe75 = resetn;
boot_dwe75 = resetn;
boot_iwe76 = resetn;
boot_dwe76 = resetn;
boot_iwe77 = resetn;
boot_dwe77 = resetn;
boot_iwe78 = resetn;
boot_dwe78 = resetn;
boot_iwe79 = resetn;
boot_dwe79 = resetn;
boot_iwe80 = resetn;
boot_dwe80 = resetn;
boot_iwe81 = resetn;
boot_dwe81 = resetn;
boot_iwe82 = resetn;
boot_dwe82 = resetn;
boot_iwe83 = resetn;
boot_dwe83 = resetn;
boot_iwe84 = resetn;
boot_dwe84 = resetn;
boot_iwe85 = resetn;
boot_dwe85 = resetn;
boot_iwe86 = resetn;
boot_dwe86 = resetn;
boot_iwe87 = resetn;
boot_dwe87 = resetn;
boot_iwe88 = resetn;
boot_dwe88 = resetn;
boot_iwe89 = resetn;
boot_dwe89 = resetn;
end
48: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = ~resetn;
boot_dwe48 = ~resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
boot_iwe50 = resetn;
boot_dwe50 = resetn;
boot_iwe51 = resetn;
boot_dwe51 = resetn;
boot_iwe52 = resetn;
boot_dwe52 = resetn;
boot_iwe53 = resetn;
boot_dwe53 = resetn;
boot_iwe54 = resetn;
boot_dwe54 = resetn;
boot_iwe55 = resetn;
boot_dwe55 = resetn;
boot_iwe56 = resetn;
boot_dwe56 = resetn;
boot_iwe57 = resetn;
boot_dwe57 = resetn;
boot_iwe58 = resetn;
boot_dwe58 = resetn;
boot_iwe59 = resetn;
boot_dwe59 = resetn;
boot_iwe60 = resetn;
boot_dwe60 = resetn;
boot_iwe61 = resetn;
boot_dwe61 = resetn;
boot_iwe62 = resetn;
boot_dwe62 = resetn;
boot_iwe63 = resetn;
boot_dwe63 = resetn;
boot_iwe64 = resetn;
boot_dwe64 = resetn;
boot_iwe65 = resetn;
boot_dwe65 = resetn;
boot_iwe66 = resetn;
boot_dwe66 = resetn;
boot_iwe67 = resetn;
boot_dwe67 = resetn;
boot_iwe68 = resetn;
boot_dwe68 = resetn;
boot_iwe69 = resetn;
boot_dwe69 = resetn;
boot_iwe70 = resetn;
boot_dwe70 = resetn;
boot_iwe71 = resetn;
boot_dwe71 = resetn;
boot_iwe72 = resetn;
boot_dwe72 = resetn;
boot_iwe73 = resetn;
boot_dwe73 = resetn;
boot_iwe74 = resetn;
boot_dwe74 = resetn;
boot_iwe75 = resetn;
boot_dwe75 = resetn;
boot_iwe76 = resetn;
boot_dwe76 = resetn;
boot_iwe77 = resetn;
boot_dwe77 = resetn;
boot_iwe78 = resetn;
boot_dwe78 = resetn;
boot_iwe79 = resetn;
boot_dwe79 = resetn;
boot_iwe80 = resetn;
boot_dwe80 = resetn;
boot_iwe81 = resetn;
boot_dwe81 = resetn;
boot_iwe82 = resetn;
boot_dwe82 = resetn;
boot_iwe83 = resetn;
boot_dwe83 = resetn;
boot_iwe84 = resetn;
boot_dwe84 = resetn;
boot_iwe85 = resetn;
boot_dwe85 = resetn;
boot_iwe86 = resetn;
boot_dwe86 = resetn;
boot_iwe87 = resetn;
boot_dwe87 = resetn;
boot_iwe88 = resetn;
boot_dwe88 = resetn;
boot_iwe89 = resetn;
boot_dwe89 = resetn;
end
49: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = ~resetn;
boot_dwe49 = ~resetn;
boot_iwe50 = resetn;
boot_dwe50 = resetn;
boot_iwe51 = resetn;
boot_dwe51 = resetn;
boot_iwe52 = resetn;
boot_dwe52 = resetn;
boot_iwe53 = resetn;
boot_dwe53 = resetn;
boot_iwe54 = resetn;
boot_dwe54 = resetn;
boot_iwe55 = resetn;
boot_dwe55 = resetn;
boot_iwe56 = resetn;
boot_dwe56 = resetn;
boot_iwe57 = resetn;
boot_dwe57 = resetn;
boot_iwe58 = resetn;
boot_dwe58 = resetn;
boot_iwe59 = resetn;
boot_dwe59 = resetn;
boot_iwe60 = resetn;
boot_dwe60 = resetn;
boot_iwe61 = resetn;
boot_dwe61 = resetn;
boot_iwe62 = resetn;
boot_dwe62 = resetn;
boot_iwe63 = resetn;
boot_dwe63 = resetn;
boot_iwe64 = resetn;
boot_dwe64 = resetn;
boot_iwe65 = resetn;
boot_dwe65 = resetn;
boot_iwe66 = resetn;
boot_dwe66 = resetn;
boot_iwe67 = resetn;
boot_dwe67 = resetn;
boot_iwe68 = resetn;
boot_dwe68 = resetn;
boot_iwe69 = resetn;
boot_dwe69 = resetn;
boot_iwe70 = resetn;
boot_dwe70 = resetn;
boot_iwe71 = resetn;
boot_dwe71 = resetn;
boot_iwe72 = resetn;
boot_dwe72 = resetn;
boot_iwe73 = resetn;
boot_dwe73 = resetn;
boot_iwe74 = resetn;
boot_dwe74 = resetn;
boot_iwe75 = resetn;
boot_dwe75 = resetn;
boot_iwe76 = resetn;
boot_dwe76 = resetn;
boot_iwe77 = resetn;
boot_dwe77 = resetn;
boot_iwe78 = resetn;
boot_dwe78 = resetn;
boot_iwe79 = resetn;
boot_dwe79 = resetn;
boot_iwe80 = resetn;
boot_dwe80 = resetn;
boot_iwe81 = resetn;
boot_dwe81 = resetn;
boot_iwe82 = resetn;
boot_dwe82 = resetn;
boot_iwe83 = resetn;
boot_dwe83 = resetn;
boot_iwe84 = resetn;
boot_dwe84 = resetn;
boot_iwe85 = resetn;
boot_dwe85 = resetn;
boot_iwe86 = resetn;
boot_dwe86 = resetn;
boot_iwe87 = resetn;
boot_dwe87 = resetn;
boot_iwe88 = resetn;
boot_dwe88 = resetn;
boot_iwe89 = resetn;
boot_dwe89 = resetn;
end
50: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
boot_iwe50 = ~resetn;
boot_dwe50 = ~resetn;
boot_iwe51 = resetn;
boot_dwe51 = resetn;
boot_iwe52 = resetn;
boot_dwe52 = resetn;
boot_iwe53 = resetn;
boot_dwe53 = resetn;
boot_iwe54 = resetn;
boot_dwe54 = resetn;
boot_iwe55 = resetn;
boot_dwe55 = resetn;
boot_iwe56 = resetn;
boot_dwe56 = resetn;
boot_iwe57 = resetn;
boot_dwe57 = resetn;
boot_iwe58 = resetn;
boot_dwe58 = resetn;
boot_iwe59 = resetn;
boot_dwe59 = resetn;
boot_iwe60 = resetn;
boot_dwe60 = resetn;
boot_iwe61 = resetn;
boot_dwe61 = resetn;
boot_iwe62 = resetn;
boot_dwe62 = resetn;
boot_iwe63 = resetn;
boot_dwe63 = resetn;
boot_iwe64 = resetn;
boot_dwe64 = resetn;
boot_iwe65 = resetn;
boot_dwe65 = resetn;
boot_iwe66 = resetn;
boot_dwe66 = resetn;
boot_iwe67 = resetn;
boot_dwe67 = resetn;
boot_iwe68 = resetn;
boot_dwe68 = resetn;
boot_iwe69 = resetn;
boot_dwe69 = resetn;
boot_iwe70 = resetn;
boot_dwe70 = resetn;
boot_iwe71 = resetn;
boot_dwe71 = resetn;
boot_iwe72 = resetn;
boot_dwe72 = resetn;
boot_iwe73 = resetn;
boot_dwe73 = resetn;
boot_iwe74 = resetn;
boot_dwe74 = resetn;
boot_iwe75 = resetn;
boot_dwe75 = resetn;
boot_iwe76 = resetn;
boot_dwe76 = resetn;
boot_iwe77 = resetn;
boot_dwe77 = resetn;
boot_iwe78 = resetn;
boot_dwe78 = resetn;
boot_iwe79 = resetn;
boot_dwe79 = resetn;
boot_iwe80 = resetn;
boot_dwe80 = resetn;
boot_iwe81 = resetn;
boot_dwe81 = resetn;
boot_iwe82 = resetn;
boot_dwe82 = resetn;
boot_iwe83 = resetn;
boot_dwe83 = resetn;
boot_iwe84 = resetn;
boot_dwe84 = resetn;
boot_iwe85 = resetn;
boot_dwe85 = resetn;
boot_iwe86 = resetn;
boot_dwe86 = resetn;
boot_iwe87 = resetn;
boot_dwe87 = resetn;
boot_iwe88 = resetn;
boot_dwe88 = resetn;
boot_iwe89 = resetn;
boot_dwe89 = resetn;
end
51: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
boot_iwe50 = resetn;
boot_dwe50 = resetn;
boot_iwe51 = ~resetn;
boot_dwe51 = ~resetn;
boot_iwe52 = resetn;
boot_dwe52 = resetn;
boot_iwe53 = resetn;
boot_dwe53 = resetn;
boot_iwe54 = resetn;
boot_dwe54 = resetn;
boot_iwe55 = resetn;
boot_dwe55 = resetn;
boot_iwe56 = resetn;
boot_dwe56 = resetn;
boot_iwe57 = resetn;
boot_dwe57 = resetn;
boot_iwe58 = resetn;
boot_dwe58 = resetn;
boot_iwe59 = resetn;
boot_dwe59 = resetn;
boot_iwe60 = resetn;
boot_dwe60 = resetn;
boot_iwe61 = resetn;
boot_dwe61 = resetn;
boot_iwe62 = resetn;
boot_dwe62 = resetn;
boot_iwe63 = resetn;
boot_dwe63 = resetn;
boot_iwe64 = resetn;
boot_dwe64 = resetn;
boot_iwe65 = resetn;
boot_dwe65 = resetn;
boot_iwe66 = resetn;
boot_dwe66 = resetn;
boot_iwe67 = resetn;
boot_dwe67 = resetn;
boot_iwe68 = resetn;
boot_dwe68 = resetn;
boot_iwe69 = resetn;
boot_dwe69 = resetn;
boot_iwe70 = resetn;
boot_dwe70 = resetn;
boot_iwe71 = resetn;
boot_dwe71 = resetn;
boot_iwe72 = resetn;
boot_dwe72 = resetn;
boot_iwe73 = resetn;
boot_dwe73 = resetn;
boot_iwe74 = resetn;
boot_dwe74 = resetn;
boot_iwe75 = resetn;
boot_dwe75 = resetn;
boot_iwe76 = resetn;
boot_dwe76 = resetn;
boot_iwe77 = resetn;
boot_dwe77 = resetn;
boot_iwe78 = resetn;
boot_dwe78 = resetn;
boot_iwe79 = resetn;
boot_dwe79 = resetn;
boot_iwe80 = resetn;
boot_dwe80 = resetn;
boot_iwe81 = resetn;
boot_dwe81 = resetn;
boot_iwe82 = resetn;
boot_dwe82 = resetn;
boot_iwe83 = resetn;
boot_dwe83 = resetn;
boot_iwe84 = resetn;
boot_dwe84 = resetn;
boot_iwe85 = resetn;
boot_dwe85 = resetn;
boot_iwe86 = resetn;
boot_dwe86 = resetn;
boot_iwe87 = resetn;
boot_dwe87 = resetn;
boot_iwe88 = resetn;
boot_dwe88 = resetn;
boot_iwe89 = resetn;
boot_dwe89 = resetn;
end
52: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
boot_iwe50 = resetn;
boot_dwe50 = resetn;
boot_iwe51 = resetn;
boot_dwe51 = resetn;
boot_iwe52 = ~resetn;
boot_dwe52 = ~resetn;
boot_iwe53 = resetn;
boot_dwe53 = resetn;
boot_iwe54 = resetn;
boot_dwe54 = resetn;
boot_iwe55 = resetn;
boot_dwe55 = resetn;
boot_iwe56 = resetn;
boot_dwe56 = resetn;
boot_iwe57 = resetn;
boot_dwe57 = resetn;
boot_iwe58 = resetn;
boot_dwe58 = resetn;
boot_iwe59 = resetn;
boot_dwe59 = resetn;
boot_iwe60 = resetn;
boot_dwe60 = resetn;
boot_iwe61 = resetn;
boot_dwe61 = resetn;
boot_iwe62 = resetn;
boot_dwe62 = resetn;
boot_iwe63 = resetn;
boot_dwe63 = resetn;
boot_iwe64 = resetn;
boot_dwe64 = resetn;
boot_iwe65 = resetn;
boot_dwe65 = resetn;
boot_iwe66 = resetn;
boot_dwe66 = resetn;
boot_iwe67 = resetn;
boot_dwe67 = resetn;
boot_iwe68 = resetn;
boot_dwe68 = resetn;
boot_iwe69 = resetn;
boot_dwe69 = resetn;
boot_iwe70 = resetn;
boot_dwe70 = resetn;
boot_iwe71 = resetn;
boot_dwe71 = resetn;
boot_iwe72 = resetn;
boot_dwe72 = resetn;
boot_iwe73 = resetn;
boot_dwe73 = resetn;
boot_iwe74 = resetn;
boot_dwe74 = resetn;
boot_iwe75 = resetn;
boot_dwe75 = resetn;
boot_iwe76 = resetn;
boot_dwe76 = resetn;
boot_iwe77 = resetn;
boot_dwe77 = resetn;
boot_iwe78 = resetn;
boot_dwe78 = resetn;
boot_iwe79 = resetn;
boot_dwe79 = resetn;
boot_iwe80 = resetn;
boot_dwe80 = resetn;
boot_iwe81 = resetn;
boot_dwe81 = resetn;
boot_iwe82 = resetn;
boot_dwe82 = resetn;
boot_iwe83 = resetn;
boot_dwe83 = resetn;
boot_iwe84 = resetn;
boot_dwe84 = resetn;
boot_iwe85 = resetn;
boot_dwe85 = resetn;
boot_iwe86 = resetn;
boot_dwe86 = resetn;
boot_iwe87 = resetn;
boot_dwe87 = resetn;
boot_iwe88 = resetn;
boot_dwe88 = resetn;
boot_iwe89 = resetn;
boot_dwe89 = resetn;
end
53: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
boot_iwe50 = resetn;
boot_dwe50 = resetn;
boot_iwe51 = resetn;
boot_dwe51 = resetn;
boot_iwe52 = resetn;
boot_dwe52 = resetn;
boot_iwe53 = ~resetn;
boot_dwe53 = ~resetn;
boot_iwe54 = resetn;
boot_dwe54 = resetn;
boot_iwe55 = resetn;
boot_dwe55 = resetn;
boot_iwe56 = resetn;
boot_dwe56 = resetn;
boot_iwe57 = resetn;
boot_dwe57 = resetn;
boot_iwe58 = resetn;
boot_dwe58 = resetn;
boot_iwe59 = resetn;
boot_dwe59 = resetn;
boot_iwe60 = resetn;
boot_dwe60 = resetn;
boot_iwe61 = resetn;
boot_dwe61 = resetn;
boot_iwe62 = resetn;
boot_dwe62 = resetn;
boot_iwe63 = resetn;
boot_dwe63 = resetn;
boot_iwe64 = resetn;
boot_dwe64 = resetn;
boot_iwe65 = resetn;
boot_dwe65 = resetn;
boot_iwe66 = resetn;
boot_dwe66 = resetn;
boot_iwe67 = resetn;
boot_dwe67 = resetn;
boot_iwe68 = resetn;
boot_dwe68 = resetn;
boot_iwe69 = resetn;
boot_dwe69 = resetn;
boot_iwe70 = resetn;
boot_dwe70 = resetn;
boot_iwe71 = resetn;
boot_dwe71 = resetn;
boot_iwe72 = resetn;
boot_dwe72 = resetn;
boot_iwe73 = resetn;
boot_dwe73 = resetn;
boot_iwe74 = resetn;
boot_dwe74 = resetn;
boot_iwe75 = resetn;
boot_dwe75 = resetn;
boot_iwe76 = resetn;
boot_dwe76 = resetn;
boot_iwe77 = resetn;
boot_dwe77 = resetn;
boot_iwe78 = resetn;
boot_dwe78 = resetn;
boot_iwe79 = resetn;
boot_dwe79 = resetn;
boot_iwe80 = resetn;
boot_dwe80 = resetn;
boot_iwe81 = resetn;
boot_dwe81 = resetn;
boot_iwe82 = resetn;
boot_dwe82 = resetn;
boot_iwe83 = resetn;
boot_dwe83 = resetn;
boot_iwe84 = resetn;
boot_dwe84 = resetn;
boot_iwe85 = resetn;
boot_dwe85 = resetn;
boot_iwe86 = resetn;
boot_dwe86 = resetn;
boot_iwe87 = resetn;
boot_dwe87 = resetn;
boot_iwe88 = resetn;
boot_dwe88 = resetn;
boot_iwe89 = resetn;
boot_dwe89 = resetn;
end
54: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
boot_iwe50 = resetn;
boot_dwe50 = resetn;
boot_iwe51 = resetn;
boot_dwe51 = resetn;
boot_iwe52 = resetn;
boot_dwe52 = resetn;
boot_iwe53 = resetn;
boot_dwe53 = resetn;
boot_iwe54 = ~resetn;
boot_dwe54 = ~resetn;
boot_iwe55 = resetn;
boot_dwe55 = resetn;
boot_iwe56 = resetn;
boot_dwe56 = resetn;
boot_iwe57 = resetn;
boot_dwe57 = resetn;
boot_iwe58 = resetn;
boot_dwe58 = resetn;
boot_iwe59 = resetn;
boot_dwe59 = resetn;
boot_iwe60 = resetn;
boot_dwe60 = resetn;
boot_iwe61 = resetn;
boot_dwe61 = resetn;
boot_iwe62 = resetn;
boot_dwe62 = resetn;
boot_iwe63 = resetn;
boot_dwe63 = resetn;
boot_iwe64 = resetn;
boot_dwe64 = resetn;
boot_iwe65 = resetn;
boot_dwe65 = resetn;
boot_iwe66 = resetn;
boot_dwe66 = resetn;
boot_iwe67 = resetn;
boot_dwe67 = resetn;
boot_iwe68 = resetn;
boot_dwe68 = resetn;
boot_iwe69 = resetn;
boot_dwe69 = resetn;
boot_iwe70 = resetn;
boot_dwe70 = resetn;
boot_iwe71 = resetn;
boot_dwe71 = resetn;
boot_iwe72 = resetn;
boot_dwe72 = resetn;
boot_iwe73 = resetn;
boot_dwe73 = resetn;
boot_iwe74 = resetn;
boot_dwe74 = resetn;
boot_iwe75 = resetn;
boot_dwe75 = resetn;
boot_iwe76 = resetn;
boot_dwe76 = resetn;
boot_iwe77 = resetn;
boot_dwe77 = resetn;
boot_iwe78 = resetn;
boot_dwe78 = resetn;
boot_iwe79 = resetn;
boot_dwe79 = resetn;
boot_iwe80 = resetn;
boot_dwe80 = resetn;
boot_iwe81 = resetn;
boot_dwe81 = resetn;
boot_iwe82 = resetn;
boot_dwe82 = resetn;
boot_iwe83 = resetn;
boot_dwe83 = resetn;
boot_iwe84 = resetn;
boot_dwe84 = resetn;
boot_iwe85 = resetn;
boot_dwe85 = resetn;
boot_iwe86 = resetn;
boot_dwe86 = resetn;
boot_iwe87 = resetn;
boot_dwe87 = resetn;
boot_iwe88 = resetn;
boot_dwe88 = resetn;
boot_iwe89 = resetn;
boot_dwe89 = resetn;
end
55: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
boot_iwe50 = resetn;
boot_dwe50 = resetn;
boot_iwe51 = resetn;
boot_dwe51 = resetn;
boot_iwe52 = resetn;
boot_dwe52 = resetn;
boot_iwe53 = resetn;
boot_dwe53 = resetn;
boot_iwe54 = resetn;
boot_dwe54 = resetn;
boot_iwe55 = ~resetn;
boot_dwe55 = ~resetn;
boot_iwe56 = resetn;
boot_dwe56 = resetn;
boot_iwe57 = resetn;
boot_dwe57 = resetn;
boot_iwe58 = resetn;
boot_dwe58 = resetn;
boot_iwe59 = resetn;
boot_dwe59 = resetn;
boot_iwe60 = resetn;
boot_dwe60 = resetn;
boot_iwe61 = resetn;
boot_dwe61 = resetn;
boot_iwe62 = resetn;
boot_dwe62 = resetn;
boot_iwe63 = resetn;
boot_dwe63 = resetn;
boot_iwe64 = resetn;
boot_dwe64 = resetn;
boot_iwe65 = resetn;
boot_dwe65 = resetn;
boot_iwe66 = resetn;
boot_dwe66 = resetn;
boot_iwe67 = resetn;
boot_dwe67 = resetn;
boot_iwe68 = resetn;
boot_dwe68 = resetn;
boot_iwe69 = resetn;
boot_dwe69 = resetn;
boot_iwe70 = resetn;
boot_dwe70 = resetn;
boot_iwe71 = resetn;
boot_dwe71 = resetn;
boot_iwe72 = resetn;
boot_dwe72 = resetn;
boot_iwe73 = resetn;
boot_dwe73 = resetn;
boot_iwe74 = resetn;
boot_dwe74 = resetn;
boot_iwe75 = resetn;
boot_dwe75 = resetn;
boot_iwe76 = resetn;
boot_dwe76 = resetn;
boot_iwe77 = resetn;
boot_dwe77 = resetn;
boot_iwe78 = resetn;
boot_dwe78 = resetn;
boot_iwe79 = resetn;
boot_dwe79 = resetn;
boot_iwe80 = resetn;
boot_dwe80 = resetn;
boot_iwe81 = resetn;
boot_dwe81 = resetn;
boot_iwe82 = resetn;
boot_dwe82 = resetn;
boot_iwe83 = resetn;
boot_dwe83 = resetn;
boot_iwe84 = resetn;
boot_dwe84 = resetn;
boot_iwe85 = resetn;
boot_dwe85 = resetn;
boot_iwe86 = resetn;
boot_dwe86 = resetn;
boot_iwe87 = resetn;
boot_dwe87 = resetn;
boot_iwe88 = resetn;
boot_dwe88 = resetn;
boot_iwe89 = resetn;
boot_dwe89 = resetn;
end
56: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
boot_iwe50 = resetn;
boot_dwe50 = resetn;
boot_iwe51 = resetn;
boot_dwe51 = resetn;
boot_iwe52 = resetn;
boot_dwe52 = resetn;
boot_iwe53 = resetn;
boot_dwe53 = resetn;
boot_iwe54 = resetn;
boot_dwe54 = resetn;
boot_iwe55 = resetn;
boot_dwe55 = resetn;
boot_iwe56 = ~resetn;
boot_dwe56 = ~resetn;
boot_iwe57 = resetn;
boot_dwe57 = resetn;
boot_iwe58 = resetn;
boot_dwe58 = resetn;
boot_iwe59 = resetn;
boot_dwe59 = resetn;
boot_iwe60 = resetn;
boot_dwe60 = resetn;
boot_iwe61 = resetn;
boot_dwe61 = resetn;
boot_iwe62 = resetn;
boot_dwe62 = resetn;
boot_iwe63 = resetn;
boot_dwe63 = resetn;
boot_iwe64 = resetn;
boot_dwe64 = resetn;
boot_iwe65 = resetn;
boot_dwe65 = resetn;
boot_iwe66 = resetn;
boot_dwe66 = resetn;
boot_iwe67 = resetn;
boot_dwe67 = resetn;
boot_iwe68 = resetn;
boot_dwe68 = resetn;
boot_iwe69 = resetn;
boot_dwe69 = resetn;
boot_iwe70 = resetn;
boot_dwe70 = resetn;
boot_iwe71 = resetn;
boot_dwe71 = resetn;
boot_iwe72 = resetn;
boot_dwe72 = resetn;
boot_iwe73 = resetn;
boot_dwe73 = resetn;
boot_iwe74 = resetn;
boot_dwe74 = resetn;
boot_iwe75 = resetn;
boot_dwe75 = resetn;
boot_iwe76 = resetn;
boot_dwe76 = resetn;
boot_iwe77 = resetn;
boot_dwe77 = resetn;
boot_iwe78 = resetn;
boot_dwe78 = resetn;
boot_iwe79 = resetn;
boot_dwe79 = resetn;
boot_iwe80 = resetn;
boot_dwe80 = resetn;
boot_iwe81 = resetn;
boot_dwe81 = resetn;
boot_iwe82 = resetn;
boot_dwe82 = resetn;
boot_iwe83 = resetn;
boot_dwe83 = resetn;
boot_iwe84 = resetn;
boot_dwe84 = resetn;
boot_iwe85 = resetn;
boot_dwe85 = resetn;
boot_iwe86 = resetn;
boot_dwe86 = resetn;
boot_iwe87 = resetn;
boot_dwe87 = resetn;
boot_iwe88 = resetn;
boot_dwe88 = resetn;
boot_iwe89 = resetn;
boot_dwe89 = resetn;
end
57: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
boot_iwe50 = resetn;
boot_dwe50 = resetn;
boot_iwe51 = resetn;
boot_dwe51 = resetn;
boot_iwe52 = resetn;
boot_dwe52 = resetn;
boot_iwe53 = resetn;
boot_dwe53 = resetn;
boot_iwe54 = resetn;
boot_dwe54 = resetn;
boot_iwe55 = resetn;
boot_dwe55 = resetn;
boot_iwe56 = resetn;
boot_dwe56 = resetn;
boot_iwe57 = ~resetn;
boot_dwe57 = ~resetn;
boot_iwe58 = resetn;
boot_dwe58 = resetn;
boot_iwe59 = resetn;
boot_dwe59 = resetn;
boot_iwe60 = resetn;
boot_dwe60 = resetn;
boot_iwe61 = resetn;
boot_dwe61 = resetn;
boot_iwe62 = resetn;
boot_dwe62 = resetn;
boot_iwe63 = resetn;
boot_dwe63 = resetn;
boot_iwe64 = resetn;
boot_dwe64 = resetn;
boot_iwe65 = resetn;
boot_dwe65 = resetn;
boot_iwe66 = resetn;
boot_dwe66 = resetn;
boot_iwe67 = resetn;
boot_dwe67 = resetn;
boot_iwe68 = resetn;
boot_dwe68 = resetn;
boot_iwe69 = resetn;
boot_dwe69 = resetn;
boot_iwe70 = resetn;
boot_dwe70 = resetn;
boot_iwe71 = resetn;
boot_dwe71 = resetn;
boot_iwe72 = resetn;
boot_dwe72 = resetn;
boot_iwe73 = resetn;
boot_dwe73 = resetn;
boot_iwe74 = resetn;
boot_dwe74 = resetn;
boot_iwe75 = resetn;
boot_dwe75 = resetn;
boot_iwe76 = resetn;
boot_dwe76 = resetn;
boot_iwe77 = resetn;
boot_dwe77 = resetn;
boot_iwe78 = resetn;
boot_dwe78 = resetn;
boot_iwe79 = resetn;
boot_dwe79 = resetn;
boot_iwe80 = resetn;
boot_dwe80 = resetn;
boot_iwe81 = resetn;
boot_dwe81 = resetn;
boot_iwe82 = resetn;
boot_dwe82 = resetn;
boot_iwe83 = resetn;
boot_dwe83 = resetn;
boot_iwe84 = resetn;
boot_dwe84 = resetn;
boot_iwe85 = resetn;
boot_dwe85 = resetn;
boot_iwe86 = resetn;
boot_dwe86 = resetn;
boot_iwe87 = resetn;
boot_dwe87 = resetn;
boot_iwe88 = resetn;
boot_dwe88 = resetn;
boot_iwe89 = resetn;
boot_dwe89 = resetn;
end
58: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
boot_iwe50 = resetn;
boot_dwe50 = resetn;
boot_iwe51 = resetn;
boot_dwe51 = resetn;
boot_iwe52 = resetn;
boot_dwe52 = resetn;
boot_iwe53 = resetn;
boot_dwe53 = resetn;
boot_iwe54 = resetn;
boot_dwe54 = resetn;
boot_iwe55 = resetn;
boot_dwe55 = resetn;
boot_iwe56 = resetn;
boot_dwe56 = resetn;
boot_iwe57 = resetn;
boot_dwe57 = resetn;
boot_iwe58 = ~resetn;
boot_dwe58 = ~resetn;
boot_iwe59 = resetn;
boot_dwe59 = resetn;
boot_iwe60 = resetn;
boot_dwe60 = resetn;
boot_iwe61 = resetn;
boot_dwe61 = resetn;
boot_iwe62 = resetn;
boot_dwe62 = resetn;
boot_iwe63 = resetn;
boot_dwe63 = resetn;
boot_iwe64 = resetn;
boot_dwe64 = resetn;
boot_iwe65 = resetn;
boot_dwe65 = resetn;
boot_iwe66 = resetn;
boot_dwe66 = resetn;
boot_iwe67 = resetn;
boot_dwe67 = resetn;
boot_iwe68 = resetn;
boot_dwe68 = resetn;
boot_iwe69 = resetn;
boot_dwe69 = resetn;
boot_iwe70 = resetn;
boot_dwe70 = resetn;
boot_iwe71 = resetn;
boot_dwe71 = resetn;
boot_iwe72 = resetn;
boot_dwe72 = resetn;
boot_iwe73 = resetn;
boot_dwe73 = resetn;
boot_iwe74 = resetn;
boot_dwe74 = resetn;
boot_iwe75 = resetn;
boot_dwe75 = resetn;
boot_iwe76 = resetn;
boot_dwe76 = resetn;
boot_iwe77 = resetn;
boot_dwe77 = resetn;
boot_iwe78 = resetn;
boot_dwe78 = resetn;
boot_iwe79 = resetn;
boot_dwe79 = resetn;
boot_iwe80 = resetn;
boot_dwe80 = resetn;
boot_iwe81 = resetn;
boot_dwe81 = resetn;
boot_iwe82 = resetn;
boot_dwe82 = resetn;
boot_iwe83 = resetn;
boot_dwe83 = resetn;
boot_iwe84 = resetn;
boot_dwe84 = resetn;
boot_iwe85 = resetn;
boot_dwe85 = resetn;
boot_iwe86 = resetn;
boot_dwe86 = resetn;
boot_iwe87 = resetn;
boot_dwe87 = resetn;
boot_iwe88 = resetn;
boot_dwe88 = resetn;
boot_iwe89 = resetn;
boot_dwe89 = resetn;
end
59: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
boot_iwe50 = resetn;
boot_dwe50 = resetn;
boot_iwe51 = resetn;
boot_dwe51 = resetn;
boot_iwe52 = resetn;
boot_dwe52 = resetn;
boot_iwe53 = resetn;
boot_dwe53 = resetn;
boot_iwe54 = resetn;
boot_dwe54 = resetn;
boot_iwe55 = resetn;
boot_dwe55 = resetn;
boot_iwe56 = resetn;
boot_dwe56 = resetn;
boot_iwe57 = resetn;
boot_dwe57 = resetn;
boot_iwe58 = resetn;
boot_dwe58 = resetn;
boot_iwe59 = ~resetn;
boot_dwe59 = ~resetn;
boot_iwe60 = resetn;
boot_dwe60 = resetn;
boot_iwe61 = resetn;
boot_dwe61 = resetn;
boot_iwe62 = resetn;
boot_dwe62 = resetn;
boot_iwe63 = resetn;
boot_dwe63 = resetn;
boot_iwe64 = resetn;
boot_dwe64 = resetn;
boot_iwe65 = resetn;
boot_dwe65 = resetn;
boot_iwe66 = resetn;
boot_dwe66 = resetn;
boot_iwe67 = resetn;
boot_dwe67 = resetn;
boot_iwe68 = resetn;
boot_dwe68 = resetn;
boot_iwe69 = resetn;
boot_dwe69 = resetn;
boot_iwe70 = resetn;
boot_dwe70 = resetn;
boot_iwe71 = resetn;
boot_dwe71 = resetn;
boot_iwe72 = resetn;
boot_dwe72 = resetn;
boot_iwe73 = resetn;
boot_dwe73 = resetn;
boot_iwe74 = resetn;
boot_dwe74 = resetn;
boot_iwe75 = resetn;
boot_dwe75 = resetn;
boot_iwe76 = resetn;
boot_dwe76 = resetn;
boot_iwe77 = resetn;
boot_dwe77 = resetn;
boot_iwe78 = resetn;
boot_dwe78 = resetn;
boot_iwe79 = resetn;
boot_dwe79 = resetn;
boot_iwe80 = resetn;
boot_dwe80 = resetn;
boot_iwe81 = resetn;
boot_dwe81 = resetn;
boot_iwe82 = resetn;
boot_dwe82 = resetn;
boot_iwe83 = resetn;
boot_dwe83 = resetn;
boot_iwe84 = resetn;
boot_dwe84 = resetn;
boot_iwe85 = resetn;
boot_dwe85 = resetn;
boot_iwe86 = resetn;
boot_dwe86 = resetn;
boot_iwe87 = resetn;
boot_dwe87 = resetn;
boot_iwe88 = resetn;
boot_dwe88 = resetn;
boot_iwe89 = resetn;
boot_dwe89 = resetn;
end
60: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
boot_iwe50 = resetn;
boot_dwe50 = resetn;
boot_iwe51 = resetn;
boot_dwe51 = resetn;
boot_iwe52 = resetn;
boot_dwe52 = resetn;
boot_iwe53 = resetn;
boot_dwe53 = resetn;
boot_iwe54 = resetn;
boot_dwe54 = resetn;
boot_iwe55 = resetn;
boot_dwe55 = resetn;
boot_iwe56 = resetn;
boot_dwe56 = resetn;
boot_iwe57 = resetn;
boot_dwe57 = resetn;
boot_iwe58 = resetn;
boot_dwe58 = resetn;
boot_iwe59 = resetn;
boot_dwe59 = resetn;
boot_iwe60 = ~resetn;
boot_dwe60 = ~resetn;
boot_iwe61 = resetn;
boot_dwe61 = resetn;
boot_iwe62 = resetn;
boot_dwe62 = resetn;
boot_iwe63 = resetn;
boot_dwe63 = resetn;
boot_iwe64 = resetn;
boot_dwe64 = resetn;
boot_iwe65 = resetn;
boot_dwe65 = resetn;
boot_iwe66 = resetn;
boot_dwe66 = resetn;
boot_iwe67 = resetn;
boot_dwe67 = resetn;
boot_iwe68 = resetn;
boot_dwe68 = resetn;
boot_iwe69 = resetn;
boot_dwe69 = resetn;
boot_iwe70 = resetn;
boot_dwe70 = resetn;
boot_iwe71 = resetn;
boot_dwe71 = resetn;
boot_iwe72 = resetn;
boot_dwe72 = resetn;
boot_iwe73 = resetn;
boot_dwe73 = resetn;
boot_iwe74 = resetn;
boot_dwe74 = resetn;
boot_iwe75 = resetn;
boot_dwe75 = resetn;
boot_iwe76 = resetn;
boot_dwe76 = resetn;
boot_iwe77 = resetn;
boot_dwe77 = resetn;
boot_iwe78 = resetn;
boot_dwe78 = resetn;
boot_iwe79 = resetn;
boot_dwe79 = resetn;
boot_iwe80 = resetn;
boot_dwe80 = resetn;
boot_iwe81 = resetn;
boot_dwe81 = resetn;
boot_iwe82 = resetn;
boot_dwe82 = resetn;
boot_iwe83 = resetn;
boot_dwe83 = resetn;
boot_iwe84 = resetn;
boot_dwe84 = resetn;
boot_iwe85 = resetn;
boot_dwe85 = resetn;
boot_iwe86 = resetn;
boot_dwe86 = resetn;
boot_iwe87 = resetn;
boot_dwe87 = resetn;
boot_iwe88 = resetn;
boot_dwe88 = resetn;
boot_iwe89 = resetn;
boot_dwe89 = resetn;
end
61: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
boot_iwe50 = resetn;
boot_dwe50 = resetn;
boot_iwe51 = resetn;
boot_dwe51 = resetn;
boot_iwe52 = resetn;
boot_dwe52 = resetn;
boot_iwe53 = resetn;
boot_dwe53 = resetn;
boot_iwe54 = resetn;
boot_dwe54 = resetn;
boot_iwe55 = resetn;
boot_dwe55 = resetn;
boot_iwe56 = resetn;
boot_dwe56 = resetn;
boot_iwe57 = resetn;
boot_dwe57 = resetn;
boot_iwe58 = resetn;
boot_dwe58 = resetn;
boot_iwe59 = resetn;
boot_dwe59 = resetn;
boot_iwe60 = resetn;
boot_dwe60 = resetn;
boot_iwe61 = ~resetn;
boot_dwe61 = ~resetn;
boot_iwe62 = resetn;
boot_dwe62 = resetn;
boot_iwe63 = resetn;
boot_dwe63 = resetn;
boot_iwe64 = resetn;
boot_dwe64 = resetn;
boot_iwe65 = resetn;
boot_dwe65 = resetn;
boot_iwe66 = resetn;
boot_dwe66 = resetn;
boot_iwe67 = resetn;
boot_dwe67 = resetn;
boot_iwe68 = resetn;
boot_dwe68 = resetn;
boot_iwe69 = resetn;
boot_dwe69 = resetn;
boot_iwe70 = resetn;
boot_dwe70 = resetn;
boot_iwe71 = resetn;
boot_dwe71 = resetn;
boot_iwe72 = resetn;
boot_dwe72 = resetn;
boot_iwe73 = resetn;
boot_dwe73 = resetn;
boot_iwe74 = resetn;
boot_dwe74 = resetn;
boot_iwe75 = resetn;
boot_dwe75 = resetn;
boot_iwe76 = resetn;
boot_dwe76 = resetn;
boot_iwe77 = resetn;
boot_dwe77 = resetn;
boot_iwe78 = resetn;
boot_dwe78 = resetn;
boot_iwe79 = resetn;
boot_dwe79 = resetn;
boot_iwe80 = resetn;
boot_dwe80 = resetn;
boot_iwe81 = resetn;
boot_dwe81 = resetn;
boot_iwe82 = resetn;
boot_dwe82 = resetn;
boot_iwe83 = resetn;
boot_dwe83 = resetn;
boot_iwe84 = resetn;
boot_dwe84 = resetn;
boot_iwe85 = resetn;
boot_dwe85 = resetn;
boot_iwe86 = resetn;
boot_dwe86 = resetn;
boot_iwe87 = resetn;
boot_dwe87 = resetn;
boot_iwe88 = resetn;
boot_dwe88 = resetn;
boot_iwe89 = resetn;
boot_dwe89 = resetn;
end
62: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
boot_iwe50 = resetn;
boot_dwe50 = resetn;
boot_iwe51 = resetn;
boot_dwe51 = resetn;
boot_iwe52 = resetn;
boot_dwe52 = resetn;
boot_iwe53 = resetn;
boot_dwe53 = resetn;
boot_iwe54 = resetn;
boot_dwe54 = resetn;
boot_iwe55 = resetn;
boot_dwe55 = resetn;
boot_iwe56 = resetn;
boot_dwe56 = resetn;
boot_iwe57 = resetn;
boot_dwe57 = resetn;
boot_iwe58 = resetn;
boot_dwe58 = resetn;
boot_iwe59 = resetn;
boot_dwe59 = resetn;
boot_iwe60 = resetn;
boot_dwe60 = resetn;
boot_iwe61 = resetn;
boot_dwe61 = resetn;
boot_iwe62 = ~resetn;
boot_dwe62 = ~resetn;
boot_iwe63 = resetn;
boot_dwe63 = resetn;
boot_iwe64 = resetn;
boot_dwe64 = resetn;
boot_iwe65 = resetn;
boot_dwe65 = resetn;
boot_iwe66 = resetn;
boot_dwe66 = resetn;
boot_iwe67 = resetn;
boot_dwe67 = resetn;
boot_iwe68 = resetn;
boot_dwe68 = resetn;
boot_iwe69 = resetn;
boot_dwe69 = resetn;
boot_iwe70 = resetn;
boot_dwe70 = resetn;
boot_iwe71 = resetn;
boot_dwe71 = resetn;
boot_iwe72 = resetn;
boot_dwe72 = resetn;
boot_iwe73 = resetn;
boot_dwe73 = resetn;
boot_iwe74 = resetn;
boot_dwe74 = resetn;
boot_iwe75 = resetn;
boot_dwe75 = resetn;
boot_iwe76 = resetn;
boot_dwe76 = resetn;
boot_iwe77 = resetn;
boot_dwe77 = resetn;
boot_iwe78 = resetn;
boot_dwe78 = resetn;
boot_iwe79 = resetn;
boot_dwe79 = resetn;
boot_iwe80 = resetn;
boot_dwe80 = resetn;
boot_iwe81 = resetn;
boot_dwe81 = resetn;
boot_iwe82 = resetn;
boot_dwe82 = resetn;
boot_iwe83 = resetn;
boot_dwe83 = resetn;
boot_iwe84 = resetn;
boot_dwe84 = resetn;
boot_iwe85 = resetn;
boot_dwe85 = resetn;
boot_iwe86 = resetn;
boot_dwe86 = resetn;
boot_iwe87 = resetn;
boot_dwe87 = resetn;
boot_iwe88 = resetn;
boot_dwe88 = resetn;
boot_iwe89 = resetn;
boot_dwe89 = resetn;
end
63: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
boot_iwe50 = resetn;
boot_dwe50 = resetn;
boot_iwe51 = resetn;
boot_dwe51 = resetn;
boot_iwe52 = resetn;
boot_dwe52 = resetn;
boot_iwe53 = resetn;
boot_dwe53 = resetn;
boot_iwe54 = resetn;
boot_dwe54 = resetn;
boot_iwe55 = resetn;
boot_dwe55 = resetn;
boot_iwe56 = resetn;
boot_dwe56 = resetn;
boot_iwe57 = resetn;
boot_dwe57 = resetn;
boot_iwe58 = resetn;
boot_dwe58 = resetn;
boot_iwe59 = resetn;
boot_dwe59 = resetn;
boot_iwe60 = resetn;
boot_dwe60 = resetn;
boot_iwe61 = resetn;
boot_dwe61 = resetn;
boot_iwe62 = resetn;
boot_dwe62 = resetn;
boot_iwe63 = ~resetn;
boot_dwe63 = ~resetn;
boot_iwe64 = resetn;
boot_dwe64 = resetn;
boot_iwe65 = resetn;
boot_dwe65 = resetn;
boot_iwe66 = resetn;
boot_dwe66 = resetn;
boot_iwe67 = resetn;
boot_dwe67 = resetn;
boot_iwe68 = resetn;
boot_dwe68 = resetn;
boot_iwe69 = resetn;
boot_dwe69 = resetn;
boot_iwe70 = resetn;
boot_dwe70 = resetn;
boot_iwe71 = resetn;
boot_dwe71 = resetn;
boot_iwe72 = resetn;
boot_dwe72 = resetn;
boot_iwe73 = resetn;
boot_dwe73 = resetn;
boot_iwe74 = resetn;
boot_dwe74 = resetn;
boot_iwe75 = resetn;
boot_dwe75 = resetn;
boot_iwe76 = resetn;
boot_dwe76 = resetn;
boot_iwe77 = resetn;
boot_dwe77 = resetn;
boot_iwe78 = resetn;
boot_dwe78 = resetn;
boot_iwe79 = resetn;
boot_dwe79 = resetn;
boot_iwe80 = resetn;
boot_dwe80 = resetn;
boot_iwe81 = resetn;
boot_dwe81 = resetn;
boot_iwe82 = resetn;
boot_dwe82 = resetn;
boot_iwe83 = resetn;
boot_dwe83 = resetn;
boot_iwe84 = resetn;
boot_dwe84 = resetn;
boot_iwe85 = resetn;
boot_dwe85 = resetn;
boot_iwe86 = resetn;
boot_dwe86 = resetn;
boot_iwe87 = resetn;
boot_dwe87 = resetn;
boot_iwe88 = resetn;
boot_dwe88 = resetn;
boot_iwe89 = resetn;
boot_dwe89 = resetn;
end
64: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
boot_iwe50 = resetn;
boot_dwe50 = resetn;
boot_iwe51 = resetn;
boot_dwe51 = resetn;
boot_iwe52 = resetn;
boot_dwe52 = resetn;
boot_iwe53 = resetn;
boot_dwe53 = resetn;
boot_iwe54 = resetn;
boot_dwe54 = resetn;
boot_iwe55 = resetn;
boot_dwe55 = resetn;
boot_iwe56 = resetn;
boot_dwe56 = resetn;
boot_iwe57 = resetn;
boot_dwe57 = resetn;
boot_iwe58 = resetn;
boot_dwe58 = resetn;
boot_iwe59 = resetn;
boot_dwe59 = resetn;
boot_iwe60 = resetn;
boot_dwe60 = resetn;
boot_iwe61 = resetn;
boot_dwe61 = resetn;
boot_iwe62 = resetn;
boot_dwe62 = resetn;
boot_iwe63 = resetn;
boot_dwe63 = resetn;
boot_iwe64 = ~resetn;
boot_dwe64 = ~resetn;
boot_iwe65 = resetn;
boot_dwe65 = resetn;
boot_iwe66 = resetn;
boot_dwe66 = resetn;
boot_iwe67 = resetn;
boot_dwe67 = resetn;
boot_iwe68 = resetn;
boot_dwe68 = resetn;
boot_iwe69 = resetn;
boot_dwe69 = resetn;
boot_iwe70 = resetn;
boot_dwe70 = resetn;
boot_iwe71 = resetn;
boot_dwe71 = resetn;
boot_iwe72 = resetn;
boot_dwe72 = resetn;
boot_iwe73 = resetn;
boot_dwe73 = resetn;
boot_iwe74 = resetn;
boot_dwe74 = resetn;
boot_iwe75 = resetn;
boot_dwe75 = resetn;
boot_iwe76 = resetn;
boot_dwe76 = resetn;
boot_iwe77 = resetn;
boot_dwe77 = resetn;
boot_iwe78 = resetn;
boot_dwe78 = resetn;
boot_iwe79 = resetn;
boot_dwe79 = resetn;
boot_iwe80 = resetn;
boot_dwe80 = resetn;
boot_iwe81 = resetn;
boot_dwe81 = resetn;
boot_iwe82 = resetn;
boot_dwe82 = resetn;
boot_iwe83 = resetn;
boot_dwe83 = resetn;
boot_iwe84 = resetn;
boot_dwe84 = resetn;
boot_iwe85 = resetn;
boot_dwe85 = resetn;
boot_iwe86 = resetn;
boot_dwe86 = resetn;
boot_iwe87 = resetn;
boot_dwe87 = resetn;
boot_iwe88 = resetn;
boot_dwe88 = resetn;
boot_iwe89 = resetn;
boot_dwe89 = resetn;
end
65: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
boot_iwe50 = resetn;
boot_dwe50 = resetn;
boot_iwe51 = resetn;
boot_dwe51 = resetn;
boot_iwe52 = resetn;
boot_dwe52 = resetn;
boot_iwe53 = resetn;
boot_dwe53 = resetn;
boot_iwe54 = resetn;
boot_dwe54 = resetn;
boot_iwe55 = resetn;
boot_dwe55 = resetn;
boot_iwe56 = resetn;
boot_dwe56 = resetn;
boot_iwe57 = resetn;
boot_dwe57 = resetn;
boot_iwe58 = resetn;
boot_dwe58 = resetn;
boot_iwe59 = resetn;
boot_dwe59 = resetn;
boot_iwe60 = resetn;
boot_dwe60 = resetn;
boot_iwe61 = resetn;
boot_dwe61 = resetn;
boot_iwe62 = resetn;
boot_dwe62 = resetn;
boot_iwe63 = resetn;
boot_dwe63 = resetn;
boot_iwe64 = resetn;
boot_dwe64 = resetn;
boot_iwe65 = ~resetn;
boot_dwe65 = ~resetn;
boot_iwe66 = resetn;
boot_dwe66 = resetn;
boot_iwe67 = resetn;
boot_dwe67 = resetn;
boot_iwe68 = resetn;
boot_dwe68 = resetn;
boot_iwe69 = resetn;
boot_dwe69 = resetn;
boot_iwe70 = resetn;
boot_dwe70 = resetn;
boot_iwe71 = resetn;
boot_dwe71 = resetn;
boot_iwe72 = resetn;
boot_dwe72 = resetn;
boot_iwe73 = resetn;
boot_dwe73 = resetn;
boot_iwe74 = resetn;
boot_dwe74 = resetn;
boot_iwe75 = resetn;
boot_dwe75 = resetn;
boot_iwe76 = resetn;
boot_dwe76 = resetn;
boot_iwe77 = resetn;
boot_dwe77 = resetn;
boot_iwe78 = resetn;
boot_dwe78 = resetn;
boot_iwe79 = resetn;
boot_dwe79 = resetn;
boot_iwe80 = resetn;
boot_dwe80 = resetn;
boot_iwe81 = resetn;
boot_dwe81 = resetn;
boot_iwe82 = resetn;
boot_dwe82 = resetn;
boot_iwe83 = resetn;
boot_dwe83 = resetn;
boot_iwe84 = resetn;
boot_dwe84 = resetn;
boot_iwe85 = resetn;
boot_dwe85 = resetn;
boot_iwe86 = resetn;
boot_dwe86 = resetn;
boot_iwe87 = resetn;
boot_dwe87 = resetn;
boot_iwe88 = resetn;
boot_dwe88 = resetn;
boot_iwe89 = resetn;
boot_dwe89 = resetn;
end
66: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
boot_iwe50 = resetn;
boot_dwe50 = resetn;
boot_iwe51 = resetn;
boot_dwe51 = resetn;
boot_iwe52 = resetn;
boot_dwe52 = resetn;
boot_iwe53 = resetn;
boot_dwe53 = resetn;
boot_iwe54 = resetn;
boot_dwe54 = resetn;
boot_iwe55 = resetn;
boot_dwe55 = resetn;
boot_iwe56 = resetn;
boot_dwe56 = resetn;
boot_iwe57 = resetn;
boot_dwe57 = resetn;
boot_iwe58 = resetn;
boot_dwe58 = resetn;
boot_iwe59 = resetn;
boot_dwe59 = resetn;
boot_iwe60 = resetn;
boot_dwe60 = resetn;
boot_iwe61 = resetn;
boot_dwe61 = resetn;
boot_iwe62 = resetn;
boot_dwe62 = resetn;
boot_iwe63 = resetn;
boot_dwe63 = resetn;
boot_iwe64 = resetn;
boot_dwe64 = resetn;
boot_iwe65 = resetn;
boot_dwe65 = resetn;
boot_iwe66 = ~resetn;
boot_dwe66 = ~resetn;
boot_iwe67 = resetn;
boot_dwe67 = resetn;
boot_iwe68 = resetn;
boot_dwe68 = resetn;
boot_iwe69 = resetn;
boot_dwe69 = resetn;
boot_iwe70 = resetn;
boot_dwe70 = resetn;
boot_iwe71 = resetn;
boot_dwe71 = resetn;
boot_iwe72 = resetn;
boot_dwe72 = resetn;
boot_iwe73 = resetn;
boot_dwe73 = resetn;
boot_iwe74 = resetn;
boot_dwe74 = resetn;
boot_iwe75 = resetn;
boot_dwe75 = resetn;
boot_iwe76 = resetn;
boot_dwe76 = resetn;
boot_iwe77 = resetn;
boot_dwe77 = resetn;
boot_iwe78 = resetn;
boot_dwe78 = resetn;
boot_iwe79 = resetn;
boot_dwe79 = resetn;
boot_iwe80 = resetn;
boot_dwe80 = resetn;
boot_iwe81 = resetn;
boot_dwe81 = resetn;
boot_iwe82 = resetn;
boot_dwe82 = resetn;
boot_iwe83 = resetn;
boot_dwe83 = resetn;
boot_iwe84 = resetn;
boot_dwe84 = resetn;
boot_iwe85 = resetn;
boot_dwe85 = resetn;
boot_iwe86 = resetn;
boot_dwe86 = resetn;
boot_iwe87 = resetn;
boot_dwe87 = resetn;
boot_iwe88 = resetn;
boot_dwe88 = resetn;
boot_iwe89 = resetn;
boot_dwe89 = resetn;
end
67: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
boot_iwe50 = resetn;
boot_dwe50 = resetn;
boot_iwe51 = resetn;
boot_dwe51 = resetn;
boot_iwe52 = resetn;
boot_dwe52 = resetn;
boot_iwe53 = resetn;
boot_dwe53 = resetn;
boot_iwe54 = resetn;
boot_dwe54 = resetn;
boot_iwe55 = resetn;
boot_dwe55 = resetn;
boot_iwe56 = resetn;
boot_dwe56 = resetn;
boot_iwe57 = resetn;
boot_dwe57 = resetn;
boot_iwe58 = resetn;
boot_dwe58 = resetn;
boot_iwe59 = resetn;
boot_dwe59 = resetn;
boot_iwe60 = resetn;
boot_dwe60 = resetn;
boot_iwe61 = resetn;
boot_dwe61 = resetn;
boot_iwe62 = resetn;
boot_dwe62 = resetn;
boot_iwe63 = resetn;
boot_dwe63 = resetn;
boot_iwe64 = resetn;
boot_dwe64 = resetn;
boot_iwe65 = resetn;
boot_dwe65 = resetn;
boot_iwe66 = resetn;
boot_dwe66 = resetn;
boot_iwe67 = ~resetn;
boot_dwe67 = ~resetn;
boot_iwe68 = resetn;
boot_dwe68 = resetn;
boot_iwe69 = resetn;
boot_dwe69 = resetn;
boot_iwe70 = resetn;
boot_dwe70 = resetn;
boot_iwe71 = resetn;
boot_dwe71 = resetn;
boot_iwe72 = resetn;
boot_dwe72 = resetn;
boot_iwe73 = resetn;
boot_dwe73 = resetn;
boot_iwe74 = resetn;
boot_dwe74 = resetn;
boot_iwe75 = resetn;
boot_dwe75 = resetn;
boot_iwe76 = resetn;
boot_dwe76 = resetn;
boot_iwe77 = resetn;
boot_dwe77 = resetn;
boot_iwe78 = resetn;
boot_dwe78 = resetn;
boot_iwe79 = resetn;
boot_dwe79 = resetn;
boot_iwe80 = resetn;
boot_dwe80 = resetn;
boot_iwe81 = resetn;
boot_dwe81 = resetn;
boot_iwe82 = resetn;
boot_dwe82 = resetn;
boot_iwe83 = resetn;
boot_dwe83 = resetn;
boot_iwe84 = resetn;
boot_dwe84 = resetn;
boot_iwe85 = resetn;
boot_dwe85 = resetn;
boot_iwe86 = resetn;
boot_dwe86 = resetn;
boot_iwe87 = resetn;
boot_dwe87 = resetn;
boot_iwe88 = resetn;
boot_dwe88 = resetn;
boot_iwe89 = resetn;
boot_dwe89 = resetn;
end
68: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
boot_iwe50 = resetn;
boot_dwe50 = resetn;
boot_iwe51 = resetn;
boot_dwe51 = resetn;
boot_iwe52 = resetn;
boot_dwe52 = resetn;
boot_iwe53 = resetn;
boot_dwe53 = resetn;
boot_iwe54 = resetn;
boot_dwe54 = resetn;
boot_iwe55 = resetn;
boot_dwe55 = resetn;
boot_iwe56 = resetn;
boot_dwe56 = resetn;
boot_iwe57 = resetn;
boot_dwe57 = resetn;
boot_iwe58 = resetn;
boot_dwe58 = resetn;
boot_iwe59 = resetn;
boot_dwe59 = resetn;
boot_iwe60 = resetn;
boot_dwe60 = resetn;
boot_iwe61 = resetn;
boot_dwe61 = resetn;
boot_iwe62 = resetn;
boot_dwe62 = resetn;
boot_iwe63 = resetn;
boot_dwe63 = resetn;
boot_iwe64 = resetn;
boot_dwe64 = resetn;
boot_iwe65 = resetn;
boot_dwe65 = resetn;
boot_iwe66 = resetn;
boot_dwe66 = resetn;
boot_iwe67 = resetn;
boot_dwe67 = resetn;
boot_iwe68 = ~resetn;
boot_dwe68 = ~resetn;
boot_iwe69 = resetn;
boot_dwe69 = resetn;
boot_iwe70 = resetn;
boot_dwe70 = resetn;
boot_iwe71 = resetn;
boot_dwe71 = resetn;
boot_iwe72 = resetn;
boot_dwe72 = resetn;
boot_iwe73 = resetn;
boot_dwe73 = resetn;
boot_iwe74 = resetn;
boot_dwe74 = resetn;
boot_iwe75 = resetn;
boot_dwe75 = resetn;
boot_iwe76 = resetn;
boot_dwe76 = resetn;
boot_iwe77 = resetn;
boot_dwe77 = resetn;
boot_iwe78 = resetn;
boot_dwe78 = resetn;
boot_iwe79 = resetn;
boot_dwe79 = resetn;
boot_iwe80 = resetn;
boot_dwe80 = resetn;
boot_iwe81 = resetn;
boot_dwe81 = resetn;
boot_iwe82 = resetn;
boot_dwe82 = resetn;
boot_iwe83 = resetn;
boot_dwe83 = resetn;
boot_iwe84 = resetn;
boot_dwe84 = resetn;
boot_iwe85 = resetn;
boot_dwe85 = resetn;
boot_iwe86 = resetn;
boot_dwe86 = resetn;
boot_iwe87 = resetn;
boot_dwe87 = resetn;
boot_iwe88 = resetn;
boot_dwe88 = resetn;
boot_iwe89 = resetn;
boot_dwe89 = resetn;
end
69: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
boot_iwe50 = resetn;
boot_dwe50 = resetn;
boot_iwe51 = resetn;
boot_dwe51 = resetn;
boot_iwe52 = resetn;
boot_dwe52 = resetn;
boot_iwe53 = resetn;
boot_dwe53 = resetn;
boot_iwe54 = resetn;
boot_dwe54 = resetn;
boot_iwe55 = resetn;
boot_dwe55 = resetn;
boot_iwe56 = resetn;
boot_dwe56 = resetn;
boot_iwe57 = resetn;
boot_dwe57 = resetn;
boot_iwe58 = resetn;
boot_dwe58 = resetn;
boot_iwe59 = resetn;
boot_dwe59 = resetn;
boot_iwe60 = resetn;
boot_dwe60 = resetn;
boot_iwe61 = resetn;
boot_dwe61 = resetn;
boot_iwe62 = resetn;
boot_dwe62 = resetn;
boot_iwe63 = resetn;
boot_dwe63 = resetn;
boot_iwe64 = resetn;
boot_dwe64 = resetn;
boot_iwe65 = resetn;
boot_dwe65 = resetn;
boot_iwe66 = resetn;
boot_dwe66 = resetn;
boot_iwe67 = resetn;
boot_dwe67 = resetn;
boot_iwe68 = resetn;
boot_dwe68 = resetn;
boot_iwe69 = ~resetn;
boot_dwe69 = ~resetn;
boot_iwe70 = resetn;
boot_dwe70 = resetn;
boot_iwe71 = resetn;
boot_dwe71 = resetn;
boot_iwe72 = resetn;
boot_dwe72 = resetn;
boot_iwe73 = resetn;
boot_dwe73 = resetn;
boot_iwe74 = resetn;
boot_dwe74 = resetn;
boot_iwe75 = resetn;
boot_dwe75 = resetn;
boot_iwe76 = resetn;
boot_dwe76 = resetn;
boot_iwe77 = resetn;
boot_dwe77 = resetn;
boot_iwe78 = resetn;
boot_dwe78 = resetn;
boot_iwe79 = resetn;
boot_dwe79 = resetn;
boot_iwe80 = resetn;
boot_dwe80 = resetn;
boot_iwe81 = resetn;
boot_dwe81 = resetn;
boot_iwe82 = resetn;
boot_dwe82 = resetn;
boot_iwe83 = resetn;
boot_dwe83 = resetn;
boot_iwe84 = resetn;
boot_dwe84 = resetn;
boot_iwe85 = resetn;
boot_dwe85 = resetn;
boot_iwe86 = resetn;
boot_dwe86 = resetn;
boot_iwe87 = resetn;
boot_dwe87 = resetn;
boot_iwe88 = resetn;
boot_dwe88 = resetn;
boot_iwe89 = resetn;
boot_dwe89 = resetn;
end
70: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
boot_iwe50 = resetn;
boot_dwe50 = resetn;
boot_iwe51 = resetn;
boot_dwe51 = resetn;
boot_iwe52 = resetn;
boot_dwe52 = resetn;
boot_iwe53 = resetn;
boot_dwe53 = resetn;
boot_iwe54 = resetn;
boot_dwe54 = resetn;
boot_iwe55 = resetn;
boot_dwe55 = resetn;
boot_iwe56 = resetn;
boot_dwe56 = resetn;
boot_iwe57 = resetn;
boot_dwe57 = resetn;
boot_iwe58 = resetn;
boot_dwe58 = resetn;
boot_iwe59 = resetn;
boot_dwe59 = resetn;
boot_iwe60 = resetn;
boot_dwe60 = resetn;
boot_iwe61 = resetn;
boot_dwe61 = resetn;
boot_iwe62 = resetn;
boot_dwe62 = resetn;
boot_iwe63 = resetn;
boot_dwe63 = resetn;
boot_iwe64 = resetn;
boot_dwe64 = resetn;
boot_iwe65 = resetn;
boot_dwe65 = resetn;
boot_iwe66 = resetn;
boot_dwe66 = resetn;
boot_iwe67 = resetn;
boot_dwe67 = resetn;
boot_iwe68 = resetn;
boot_dwe68 = resetn;
boot_iwe69 = resetn;
boot_dwe69 = resetn;
boot_iwe70 = ~resetn;
boot_dwe70 = ~resetn;
boot_iwe71 = resetn;
boot_dwe71 = resetn;
boot_iwe72 = resetn;
boot_dwe72 = resetn;
boot_iwe73 = resetn;
boot_dwe73 = resetn;
boot_iwe74 = resetn;
boot_dwe74 = resetn;
boot_iwe75 = resetn;
boot_dwe75 = resetn;
boot_iwe76 = resetn;
boot_dwe76 = resetn;
boot_iwe77 = resetn;
boot_dwe77 = resetn;
boot_iwe78 = resetn;
boot_dwe78 = resetn;
boot_iwe79 = resetn;
boot_dwe79 = resetn;
boot_iwe80 = resetn;
boot_dwe80 = resetn;
boot_iwe81 = resetn;
boot_dwe81 = resetn;
boot_iwe82 = resetn;
boot_dwe82 = resetn;
boot_iwe83 = resetn;
boot_dwe83 = resetn;
boot_iwe84 = resetn;
boot_dwe84 = resetn;
boot_iwe85 = resetn;
boot_dwe85 = resetn;
boot_iwe86 = resetn;
boot_dwe86 = resetn;
boot_iwe87 = resetn;
boot_dwe87 = resetn;
boot_iwe88 = resetn;
boot_dwe88 = resetn;
boot_iwe89 = resetn;
boot_dwe89 = resetn;
end
71: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
boot_iwe50 = resetn;
boot_dwe50 = resetn;
boot_iwe51 = resetn;
boot_dwe51 = resetn;
boot_iwe52 = resetn;
boot_dwe52 = resetn;
boot_iwe53 = resetn;
boot_dwe53 = resetn;
boot_iwe54 = resetn;
boot_dwe54 = resetn;
boot_iwe55 = resetn;
boot_dwe55 = resetn;
boot_iwe56 = resetn;
boot_dwe56 = resetn;
boot_iwe57 = resetn;
boot_dwe57 = resetn;
boot_iwe58 = resetn;
boot_dwe58 = resetn;
boot_iwe59 = resetn;
boot_dwe59 = resetn;
boot_iwe60 = resetn;
boot_dwe60 = resetn;
boot_iwe61 = resetn;
boot_dwe61 = resetn;
boot_iwe62 = resetn;
boot_dwe62 = resetn;
boot_iwe63 = resetn;
boot_dwe63 = resetn;
boot_iwe64 = resetn;
boot_dwe64 = resetn;
boot_iwe65 = resetn;
boot_dwe65 = resetn;
boot_iwe66 = resetn;
boot_dwe66 = resetn;
boot_iwe67 = resetn;
boot_dwe67 = resetn;
boot_iwe68 = resetn;
boot_dwe68 = resetn;
boot_iwe69 = resetn;
boot_dwe69 = resetn;
boot_iwe70 = resetn;
boot_dwe70 = resetn;
boot_iwe71 = ~resetn;
boot_dwe71 = ~resetn;
boot_iwe72 = resetn;
boot_dwe72 = resetn;
boot_iwe73 = resetn;
boot_dwe73 = resetn;
boot_iwe74 = resetn;
boot_dwe74 = resetn;
boot_iwe75 = resetn;
boot_dwe75 = resetn;
boot_iwe76 = resetn;
boot_dwe76 = resetn;
boot_iwe77 = resetn;
boot_dwe77 = resetn;
boot_iwe78 = resetn;
boot_dwe78 = resetn;
boot_iwe79 = resetn;
boot_dwe79 = resetn;
boot_iwe80 = resetn;
boot_dwe80 = resetn;
boot_iwe81 = resetn;
boot_dwe81 = resetn;
boot_iwe82 = resetn;
boot_dwe82 = resetn;
boot_iwe83 = resetn;
boot_dwe83 = resetn;
boot_iwe84 = resetn;
boot_dwe84 = resetn;
boot_iwe85 = resetn;
boot_dwe85 = resetn;
boot_iwe86 = resetn;
boot_dwe86 = resetn;
boot_iwe87 = resetn;
boot_dwe87 = resetn;
boot_iwe88 = resetn;
boot_dwe88 = resetn;
boot_iwe89 = resetn;
boot_dwe89 = resetn;
end
72: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
boot_iwe50 = resetn;
boot_dwe50 = resetn;
boot_iwe51 = resetn;
boot_dwe51 = resetn;
boot_iwe52 = resetn;
boot_dwe52 = resetn;
boot_iwe53 = resetn;
boot_dwe53 = resetn;
boot_iwe54 = resetn;
boot_dwe54 = resetn;
boot_iwe55 = resetn;
boot_dwe55 = resetn;
boot_iwe56 = resetn;
boot_dwe56 = resetn;
boot_iwe57 = resetn;
boot_dwe57 = resetn;
boot_iwe58 = resetn;
boot_dwe58 = resetn;
boot_iwe59 = resetn;
boot_dwe59 = resetn;
boot_iwe60 = resetn;
boot_dwe60 = resetn;
boot_iwe61 = resetn;
boot_dwe61 = resetn;
boot_iwe62 = resetn;
boot_dwe62 = resetn;
boot_iwe63 = resetn;
boot_dwe63 = resetn;
boot_iwe64 = resetn;
boot_dwe64 = resetn;
boot_iwe65 = resetn;
boot_dwe65 = resetn;
boot_iwe66 = resetn;
boot_dwe66 = resetn;
boot_iwe67 = resetn;
boot_dwe67 = resetn;
boot_iwe68 = resetn;
boot_dwe68 = resetn;
boot_iwe69 = resetn;
boot_dwe69 = resetn;
boot_iwe70 = resetn;
boot_dwe70 = resetn;
boot_iwe71 = resetn;
boot_dwe71 = resetn;
boot_iwe72 = ~resetn;
boot_dwe72 = ~resetn;
boot_iwe73 = resetn;
boot_dwe73 = resetn;
boot_iwe74 = resetn;
boot_dwe74 = resetn;
boot_iwe75 = resetn;
boot_dwe75 = resetn;
boot_iwe76 = resetn;
boot_dwe76 = resetn;
boot_iwe77 = resetn;
boot_dwe77 = resetn;
boot_iwe78 = resetn;
boot_dwe78 = resetn;
boot_iwe79 = resetn;
boot_dwe79 = resetn;
boot_iwe80 = resetn;
boot_dwe80 = resetn;
boot_iwe81 = resetn;
boot_dwe81 = resetn;
boot_iwe82 = resetn;
boot_dwe82 = resetn;
boot_iwe83 = resetn;
boot_dwe83 = resetn;
boot_iwe84 = resetn;
boot_dwe84 = resetn;
boot_iwe85 = resetn;
boot_dwe85 = resetn;
boot_iwe86 = resetn;
boot_dwe86 = resetn;
boot_iwe87 = resetn;
boot_dwe87 = resetn;
boot_iwe88 = resetn;
boot_dwe88 = resetn;
boot_iwe89 = resetn;
boot_dwe89 = resetn;
end
73: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
boot_iwe50 = resetn;
boot_dwe50 = resetn;
boot_iwe51 = resetn;
boot_dwe51 = resetn;
boot_iwe52 = resetn;
boot_dwe52 = resetn;
boot_iwe53 = resetn;
boot_dwe53 = resetn;
boot_iwe54 = resetn;
boot_dwe54 = resetn;
boot_iwe55 = resetn;
boot_dwe55 = resetn;
boot_iwe56 = resetn;
boot_dwe56 = resetn;
boot_iwe57 = resetn;
boot_dwe57 = resetn;
boot_iwe58 = resetn;
boot_dwe58 = resetn;
boot_iwe59 = resetn;
boot_dwe59 = resetn;
boot_iwe60 = resetn;
boot_dwe60 = resetn;
boot_iwe61 = resetn;
boot_dwe61 = resetn;
boot_iwe62 = resetn;
boot_dwe62 = resetn;
boot_iwe63 = resetn;
boot_dwe63 = resetn;
boot_iwe64 = resetn;
boot_dwe64 = resetn;
boot_iwe65 = resetn;
boot_dwe65 = resetn;
boot_iwe66 = resetn;
boot_dwe66 = resetn;
boot_iwe67 = resetn;
boot_dwe67 = resetn;
boot_iwe68 = resetn;
boot_dwe68 = resetn;
boot_iwe69 = resetn;
boot_dwe69 = resetn;
boot_iwe70 = resetn;
boot_dwe70 = resetn;
boot_iwe71 = resetn;
boot_dwe71 = resetn;
boot_iwe72 = resetn;
boot_dwe72 = resetn;
boot_iwe73 = ~resetn;
boot_dwe73 = ~resetn;
boot_iwe74 = resetn;
boot_dwe74 = resetn;
boot_iwe75 = resetn;
boot_dwe75 = resetn;
boot_iwe76 = resetn;
boot_dwe76 = resetn;
boot_iwe77 = resetn;
boot_dwe77 = resetn;
boot_iwe78 = resetn;
boot_dwe78 = resetn;
boot_iwe79 = resetn;
boot_dwe79 = resetn;
boot_iwe80 = resetn;
boot_dwe80 = resetn;
boot_iwe81 = resetn;
boot_dwe81 = resetn;
boot_iwe82 = resetn;
boot_dwe82 = resetn;
boot_iwe83 = resetn;
boot_dwe83 = resetn;
boot_iwe84 = resetn;
boot_dwe84 = resetn;
boot_iwe85 = resetn;
boot_dwe85 = resetn;
boot_iwe86 = resetn;
boot_dwe86 = resetn;
boot_iwe87 = resetn;
boot_dwe87 = resetn;
boot_iwe88 = resetn;
boot_dwe88 = resetn;
boot_iwe89 = resetn;
boot_dwe89 = resetn;
end
74: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
boot_iwe50 = resetn;
boot_dwe50 = resetn;
boot_iwe51 = resetn;
boot_dwe51 = resetn;
boot_iwe52 = resetn;
boot_dwe52 = resetn;
boot_iwe53 = resetn;
boot_dwe53 = resetn;
boot_iwe54 = resetn;
boot_dwe54 = resetn;
boot_iwe55 = resetn;
boot_dwe55 = resetn;
boot_iwe56 = resetn;
boot_dwe56 = resetn;
boot_iwe57 = resetn;
boot_dwe57 = resetn;
boot_iwe58 = resetn;
boot_dwe58 = resetn;
boot_iwe59 = resetn;
boot_dwe59 = resetn;
boot_iwe60 = resetn;
boot_dwe60 = resetn;
boot_iwe61 = resetn;
boot_dwe61 = resetn;
boot_iwe62 = resetn;
boot_dwe62 = resetn;
boot_iwe63 = resetn;
boot_dwe63 = resetn;
boot_iwe64 = resetn;
boot_dwe64 = resetn;
boot_iwe65 = resetn;
boot_dwe65 = resetn;
boot_iwe66 = resetn;
boot_dwe66 = resetn;
boot_iwe67 = resetn;
boot_dwe67 = resetn;
boot_iwe68 = resetn;
boot_dwe68 = resetn;
boot_iwe69 = resetn;
boot_dwe69 = resetn;
boot_iwe70 = resetn;
boot_dwe70 = resetn;
boot_iwe71 = resetn;
boot_dwe71 = resetn;
boot_iwe72 = resetn;
boot_dwe72 = resetn;
boot_iwe73 = resetn;
boot_dwe73 = resetn;
boot_iwe74 = ~resetn;
boot_dwe74 = ~resetn;
boot_iwe75 = resetn;
boot_dwe75 = resetn;
boot_iwe76 = resetn;
boot_dwe76 = resetn;
boot_iwe77 = resetn;
boot_dwe77 = resetn;
boot_iwe78 = resetn;
boot_dwe78 = resetn;
boot_iwe79 = resetn;
boot_dwe79 = resetn;
boot_iwe80 = resetn;
boot_dwe80 = resetn;
boot_iwe81 = resetn;
boot_dwe81 = resetn;
boot_iwe82 = resetn;
boot_dwe82 = resetn;
boot_iwe83 = resetn;
boot_dwe83 = resetn;
boot_iwe84 = resetn;
boot_dwe84 = resetn;
boot_iwe85 = resetn;
boot_dwe85 = resetn;
boot_iwe86 = resetn;
boot_dwe86 = resetn;
boot_iwe87 = resetn;
boot_dwe87 = resetn;
boot_iwe88 = resetn;
boot_dwe88 = resetn;
boot_iwe89 = resetn;
boot_dwe89 = resetn;
end
75: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
boot_iwe50 = resetn;
boot_dwe50 = resetn;
boot_iwe51 = resetn;
boot_dwe51 = resetn;
boot_iwe52 = resetn;
boot_dwe52 = resetn;
boot_iwe53 = resetn;
boot_dwe53 = resetn;
boot_iwe54 = resetn;
boot_dwe54 = resetn;
boot_iwe55 = resetn;
boot_dwe55 = resetn;
boot_iwe56 = resetn;
boot_dwe56 = resetn;
boot_iwe57 = resetn;
boot_dwe57 = resetn;
boot_iwe58 = resetn;
boot_dwe58 = resetn;
boot_iwe59 = resetn;
boot_dwe59 = resetn;
boot_iwe60 = resetn;
boot_dwe60 = resetn;
boot_iwe61 = resetn;
boot_dwe61 = resetn;
boot_iwe62 = resetn;
boot_dwe62 = resetn;
boot_iwe63 = resetn;
boot_dwe63 = resetn;
boot_iwe64 = resetn;
boot_dwe64 = resetn;
boot_iwe65 = resetn;
boot_dwe65 = resetn;
boot_iwe66 = resetn;
boot_dwe66 = resetn;
boot_iwe67 = resetn;
boot_dwe67 = resetn;
boot_iwe68 = resetn;
boot_dwe68 = resetn;
boot_iwe69 = resetn;
boot_dwe69 = resetn;
boot_iwe70 = resetn;
boot_dwe70 = resetn;
boot_iwe71 = resetn;
boot_dwe71 = resetn;
boot_iwe72 = resetn;
boot_dwe72 = resetn;
boot_iwe73 = resetn;
boot_dwe73 = resetn;
boot_iwe74 = resetn;
boot_dwe74 = resetn;
boot_iwe75 = ~resetn;
boot_dwe75 = ~resetn;
boot_iwe76 = resetn;
boot_dwe76 = resetn;
boot_iwe77 = resetn;
boot_dwe77 = resetn;
boot_iwe78 = resetn;
boot_dwe78 = resetn;
boot_iwe79 = resetn;
boot_dwe79 = resetn;
boot_iwe80 = resetn;
boot_dwe80 = resetn;
boot_iwe81 = resetn;
boot_dwe81 = resetn;
boot_iwe82 = resetn;
boot_dwe82 = resetn;
boot_iwe83 = resetn;
boot_dwe83 = resetn;
boot_iwe84 = resetn;
boot_dwe84 = resetn;
boot_iwe85 = resetn;
boot_dwe85 = resetn;
boot_iwe86 = resetn;
boot_dwe86 = resetn;
boot_iwe87 = resetn;
boot_dwe87 = resetn;
boot_iwe88 = resetn;
boot_dwe88 = resetn;
boot_iwe89 = resetn;
boot_dwe89 = resetn;
end
76: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
boot_iwe50 = resetn;
boot_dwe50 = resetn;
boot_iwe51 = resetn;
boot_dwe51 = resetn;
boot_iwe52 = resetn;
boot_dwe52 = resetn;
boot_iwe53 = resetn;
boot_dwe53 = resetn;
boot_iwe54 = resetn;
boot_dwe54 = resetn;
boot_iwe55 = resetn;
boot_dwe55 = resetn;
boot_iwe56 = resetn;
boot_dwe56 = resetn;
boot_iwe57 = resetn;
boot_dwe57 = resetn;
boot_iwe58 = resetn;
boot_dwe58 = resetn;
boot_iwe59 = resetn;
boot_dwe59 = resetn;
boot_iwe60 = resetn;
boot_dwe60 = resetn;
boot_iwe61 = resetn;
boot_dwe61 = resetn;
boot_iwe62 = resetn;
boot_dwe62 = resetn;
boot_iwe63 = resetn;
boot_dwe63 = resetn;
boot_iwe64 = resetn;
boot_dwe64 = resetn;
boot_iwe65 = resetn;
boot_dwe65 = resetn;
boot_iwe66 = resetn;
boot_dwe66 = resetn;
boot_iwe67 = resetn;
boot_dwe67 = resetn;
boot_iwe68 = resetn;
boot_dwe68 = resetn;
boot_iwe69 = resetn;
boot_dwe69 = resetn;
boot_iwe70 = resetn;
boot_dwe70 = resetn;
boot_iwe71 = resetn;
boot_dwe71 = resetn;
boot_iwe72 = resetn;
boot_dwe72 = resetn;
boot_iwe73 = resetn;
boot_dwe73 = resetn;
boot_iwe74 = resetn;
boot_dwe74 = resetn;
boot_iwe75 = resetn;
boot_dwe75 = resetn;
boot_iwe76 = ~resetn;
boot_dwe76 = ~resetn;
boot_iwe77 = resetn;
boot_dwe77 = resetn;
boot_iwe78 = resetn;
boot_dwe78 = resetn;
boot_iwe79 = resetn;
boot_dwe79 = resetn;
boot_iwe80 = resetn;
boot_dwe80 = resetn;
boot_iwe81 = resetn;
boot_dwe81 = resetn;
boot_iwe82 = resetn;
boot_dwe82 = resetn;
boot_iwe83 = resetn;
boot_dwe83 = resetn;
boot_iwe84 = resetn;
boot_dwe84 = resetn;
boot_iwe85 = resetn;
boot_dwe85 = resetn;
boot_iwe86 = resetn;
boot_dwe86 = resetn;
boot_iwe87 = resetn;
boot_dwe87 = resetn;
boot_iwe88 = resetn;
boot_dwe88 = resetn;
boot_iwe89 = resetn;
boot_dwe89 = resetn;
end
77: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
boot_iwe50 = resetn;
boot_dwe50 = resetn;
boot_iwe51 = resetn;
boot_dwe51 = resetn;
boot_iwe52 = resetn;
boot_dwe52 = resetn;
boot_iwe53 = resetn;
boot_dwe53 = resetn;
boot_iwe54 = resetn;
boot_dwe54 = resetn;
boot_iwe55 = resetn;
boot_dwe55 = resetn;
boot_iwe56 = resetn;
boot_dwe56 = resetn;
boot_iwe57 = resetn;
boot_dwe57 = resetn;
boot_iwe58 = resetn;
boot_dwe58 = resetn;
boot_iwe59 = resetn;
boot_dwe59 = resetn;
boot_iwe60 = resetn;
boot_dwe60 = resetn;
boot_iwe61 = resetn;
boot_dwe61 = resetn;
boot_iwe62 = resetn;
boot_dwe62 = resetn;
boot_iwe63 = resetn;
boot_dwe63 = resetn;
boot_iwe64 = resetn;
boot_dwe64 = resetn;
boot_iwe65 = resetn;
boot_dwe65 = resetn;
boot_iwe66 = resetn;
boot_dwe66 = resetn;
boot_iwe67 = resetn;
boot_dwe67 = resetn;
boot_iwe68 = resetn;
boot_dwe68 = resetn;
boot_iwe69 = resetn;
boot_dwe69 = resetn;
boot_iwe70 = resetn;
boot_dwe70 = resetn;
boot_iwe71 = resetn;
boot_dwe71 = resetn;
boot_iwe72 = resetn;
boot_dwe72 = resetn;
boot_iwe73 = resetn;
boot_dwe73 = resetn;
boot_iwe74 = resetn;
boot_dwe74 = resetn;
boot_iwe75 = resetn;
boot_dwe75 = resetn;
boot_iwe76 = resetn;
boot_dwe76 = resetn;
boot_iwe77 = ~resetn;
boot_dwe77 = ~resetn;
boot_iwe78 = resetn;
boot_dwe78 = resetn;
boot_iwe79 = resetn;
boot_dwe79 = resetn;
boot_iwe80 = resetn;
boot_dwe80 = resetn;
boot_iwe81 = resetn;
boot_dwe81 = resetn;
boot_iwe82 = resetn;
boot_dwe82 = resetn;
boot_iwe83 = resetn;
boot_dwe83 = resetn;
boot_iwe84 = resetn;
boot_dwe84 = resetn;
boot_iwe85 = resetn;
boot_dwe85 = resetn;
boot_iwe86 = resetn;
boot_dwe86 = resetn;
boot_iwe87 = resetn;
boot_dwe87 = resetn;
boot_iwe88 = resetn;
boot_dwe88 = resetn;
boot_iwe89 = resetn;
boot_dwe89 = resetn;
end
78: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
boot_iwe50 = resetn;
boot_dwe50 = resetn;
boot_iwe51 = resetn;
boot_dwe51 = resetn;
boot_iwe52 = resetn;
boot_dwe52 = resetn;
boot_iwe53 = resetn;
boot_dwe53 = resetn;
boot_iwe54 = resetn;
boot_dwe54 = resetn;
boot_iwe55 = resetn;
boot_dwe55 = resetn;
boot_iwe56 = resetn;
boot_dwe56 = resetn;
boot_iwe57 = resetn;
boot_dwe57 = resetn;
boot_iwe58 = resetn;
boot_dwe58 = resetn;
boot_iwe59 = resetn;
boot_dwe59 = resetn;
boot_iwe60 = resetn;
boot_dwe60 = resetn;
boot_iwe61 = resetn;
boot_dwe61 = resetn;
boot_iwe62 = resetn;
boot_dwe62 = resetn;
boot_iwe63 = resetn;
boot_dwe63 = resetn;
boot_iwe64 = resetn;
boot_dwe64 = resetn;
boot_iwe65 = resetn;
boot_dwe65 = resetn;
boot_iwe66 = resetn;
boot_dwe66 = resetn;
boot_iwe67 = resetn;
boot_dwe67 = resetn;
boot_iwe68 = resetn;
boot_dwe68 = resetn;
boot_iwe69 = resetn;
boot_dwe69 = resetn;
boot_iwe70 = resetn;
boot_dwe70 = resetn;
boot_iwe71 = resetn;
boot_dwe71 = resetn;
boot_iwe72 = resetn;
boot_dwe72 = resetn;
boot_iwe73 = resetn;
boot_dwe73 = resetn;
boot_iwe74 = resetn;
boot_dwe74 = resetn;
boot_iwe75 = resetn;
boot_dwe75 = resetn;
boot_iwe76 = resetn;
boot_dwe76 = resetn;
boot_iwe77 = resetn;
boot_dwe77 = resetn;
boot_iwe78 = ~resetn;
boot_dwe78 = ~resetn;
boot_iwe79 = resetn;
boot_dwe79 = resetn;
boot_iwe80 = resetn;
boot_dwe80 = resetn;
boot_iwe81 = resetn;
boot_dwe81 = resetn;
boot_iwe82 = resetn;
boot_dwe82 = resetn;
boot_iwe83 = resetn;
boot_dwe83 = resetn;
boot_iwe84 = resetn;
boot_dwe84 = resetn;
boot_iwe85 = resetn;
boot_dwe85 = resetn;
boot_iwe86 = resetn;
boot_dwe86 = resetn;
boot_iwe87 = resetn;
boot_dwe87 = resetn;
boot_iwe88 = resetn;
boot_dwe88 = resetn;
boot_iwe89 = resetn;
boot_dwe89 = resetn;
end
79: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
boot_iwe50 = resetn;
boot_dwe50 = resetn;
boot_iwe51 = resetn;
boot_dwe51 = resetn;
boot_iwe52 = resetn;
boot_dwe52 = resetn;
boot_iwe53 = resetn;
boot_dwe53 = resetn;
boot_iwe54 = resetn;
boot_dwe54 = resetn;
boot_iwe55 = resetn;
boot_dwe55 = resetn;
boot_iwe56 = resetn;
boot_dwe56 = resetn;
boot_iwe57 = resetn;
boot_dwe57 = resetn;
boot_iwe58 = resetn;
boot_dwe58 = resetn;
boot_iwe59 = resetn;
boot_dwe59 = resetn;
boot_iwe60 = resetn;
boot_dwe60 = resetn;
boot_iwe61 = resetn;
boot_dwe61 = resetn;
boot_iwe62 = resetn;
boot_dwe62 = resetn;
boot_iwe63 = resetn;
boot_dwe63 = resetn;
boot_iwe64 = resetn;
boot_dwe64 = resetn;
boot_iwe65 = resetn;
boot_dwe65 = resetn;
boot_iwe66 = resetn;
boot_dwe66 = resetn;
boot_iwe67 = resetn;
boot_dwe67 = resetn;
boot_iwe68 = resetn;
boot_dwe68 = resetn;
boot_iwe69 = resetn;
boot_dwe69 = resetn;
boot_iwe70 = resetn;
boot_dwe70 = resetn;
boot_iwe71 = resetn;
boot_dwe71 = resetn;
boot_iwe72 = resetn;
boot_dwe72 = resetn;
boot_iwe73 = resetn;
boot_dwe73 = resetn;
boot_iwe74 = resetn;
boot_dwe74 = resetn;
boot_iwe75 = resetn;
boot_dwe75 = resetn;
boot_iwe76 = resetn;
boot_dwe76 = resetn;
boot_iwe77 = resetn;
boot_dwe77 = resetn;
boot_iwe78 = resetn;
boot_dwe78 = resetn;
boot_iwe79 = ~resetn;
boot_dwe79 = ~resetn;
boot_iwe80 = resetn;
boot_dwe80 = resetn;
boot_iwe81 = resetn;
boot_dwe81 = resetn;
boot_iwe82 = resetn;
boot_dwe82 = resetn;
boot_iwe83 = resetn;
boot_dwe83 = resetn;
boot_iwe84 = resetn;
boot_dwe84 = resetn;
boot_iwe85 = resetn;
boot_dwe85 = resetn;
boot_iwe86 = resetn;
boot_dwe86 = resetn;
boot_iwe87 = resetn;
boot_dwe87 = resetn;
boot_iwe88 = resetn;
boot_dwe88 = resetn;
boot_iwe89 = resetn;
boot_dwe89 = resetn;
end
80: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
boot_iwe50 = resetn;
boot_dwe50 = resetn;
boot_iwe51 = resetn;
boot_dwe51 = resetn;
boot_iwe52 = resetn;
boot_dwe52 = resetn;
boot_iwe53 = resetn;
boot_dwe53 = resetn;
boot_iwe54 = resetn;
boot_dwe54 = resetn;
boot_iwe55 = resetn;
boot_dwe55 = resetn;
boot_iwe56 = resetn;
boot_dwe56 = resetn;
boot_iwe57 = resetn;
boot_dwe57 = resetn;
boot_iwe58 = resetn;
boot_dwe58 = resetn;
boot_iwe59 = resetn;
boot_dwe59 = resetn;
boot_iwe60 = resetn;
boot_dwe60 = resetn;
boot_iwe61 = resetn;
boot_dwe61 = resetn;
boot_iwe62 = resetn;
boot_dwe62 = resetn;
boot_iwe63 = resetn;
boot_dwe63 = resetn;
boot_iwe64 = resetn;
boot_dwe64 = resetn;
boot_iwe65 = resetn;
boot_dwe65 = resetn;
boot_iwe66 = resetn;
boot_dwe66 = resetn;
boot_iwe67 = resetn;
boot_dwe67 = resetn;
boot_iwe68 = resetn;
boot_dwe68 = resetn;
boot_iwe69 = resetn;
boot_dwe69 = resetn;
boot_iwe70 = resetn;
boot_dwe70 = resetn;
boot_iwe71 = resetn;
boot_dwe71 = resetn;
boot_iwe72 = resetn;
boot_dwe72 = resetn;
boot_iwe73 = resetn;
boot_dwe73 = resetn;
boot_iwe74 = resetn;
boot_dwe74 = resetn;
boot_iwe75 = resetn;
boot_dwe75 = resetn;
boot_iwe76 = resetn;
boot_dwe76 = resetn;
boot_iwe77 = resetn;
boot_dwe77 = resetn;
boot_iwe78 = resetn;
boot_dwe78 = resetn;
boot_iwe79 = resetn;
boot_dwe79 = resetn;
boot_iwe80 = ~resetn;
boot_dwe80 = ~resetn;
boot_iwe81 = resetn;
boot_dwe81 = resetn;
boot_iwe82 = resetn;
boot_dwe82 = resetn;
boot_iwe83 = resetn;
boot_dwe83 = resetn;
boot_iwe84 = resetn;
boot_dwe84 = resetn;
boot_iwe85 = resetn;
boot_dwe85 = resetn;
boot_iwe86 = resetn;
boot_dwe86 = resetn;
boot_iwe87 = resetn;
boot_dwe87 = resetn;
boot_iwe88 = resetn;
boot_dwe88 = resetn;
boot_iwe89 = resetn;
boot_dwe89 = resetn;
end
81: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
boot_iwe50 = resetn;
boot_dwe50 = resetn;
boot_iwe51 = resetn;
boot_dwe51 = resetn;
boot_iwe52 = resetn;
boot_dwe52 = resetn;
boot_iwe53 = resetn;
boot_dwe53 = resetn;
boot_iwe54 = resetn;
boot_dwe54 = resetn;
boot_iwe55 = resetn;
boot_dwe55 = resetn;
boot_iwe56 = resetn;
boot_dwe56 = resetn;
boot_iwe57 = resetn;
boot_dwe57 = resetn;
boot_iwe58 = resetn;
boot_dwe58 = resetn;
boot_iwe59 = resetn;
boot_dwe59 = resetn;
boot_iwe60 = resetn;
boot_dwe60 = resetn;
boot_iwe61 = resetn;
boot_dwe61 = resetn;
boot_iwe62 = resetn;
boot_dwe62 = resetn;
boot_iwe63 = resetn;
boot_dwe63 = resetn;
boot_iwe64 = resetn;
boot_dwe64 = resetn;
boot_iwe65 = resetn;
boot_dwe65 = resetn;
boot_iwe66 = resetn;
boot_dwe66 = resetn;
boot_iwe67 = resetn;
boot_dwe67 = resetn;
boot_iwe68 = resetn;
boot_dwe68 = resetn;
boot_iwe69 = resetn;
boot_dwe69 = resetn;
boot_iwe70 = resetn;
boot_dwe70 = resetn;
boot_iwe71 = resetn;
boot_dwe71 = resetn;
boot_iwe72 = resetn;
boot_dwe72 = resetn;
boot_iwe73 = resetn;
boot_dwe73 = resetn;
boot_iwe74 = resetn;
boot_dwe74 = resetn;
boot_iwe75 = resetn;
boot_dwe75 = resetn;
boot_iwe76 = resetn;
boot_dwe76 = resetn;
boot_iwe77 = resetn;
boot_dwe77 = resetn;
boot_iwe78 = resetn;
boot_dwe78 = resetn;
boot_iwe79 = resetn;
boot_dwe79 = resetn;
boot_iwe80 = resetn;
boot_dwe80 = resetn;
boot_iwe81 = ~resetn;
boot_dwe81 = ~resetn;
boot_iwe82 = resetn;
boot_dwe82 = resetn;
boot_iwe83 = resetn;
boot_dwe83 = resetn;
boot_iwe84 = resetn;
boot_dwe84 = resetn;
boot_iwe85 = resetn;
boot_dwe85 = resetn;
boot_iwe86 = resetn;
boot_dwe86 = resetn;
boot_iwe87 = resetn;
boot_dwe87 = resetn;
boot_iwe88 = resetn;
boot_dwe88 = resetn;
boot_iwe89 = resetn;
boot_dwe89 = resetn;
end
82: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
boot_iwe50 = resetn;
boot_dwe50 = resetn;
boot_iwe51 = resetn;
boot_dwe51 = resetn;
boot_iwe52 = resetn;
boot_dwe52 = resetn;
boot_iwe53 = resetn;
boot_dwe53 = resetn;
boot_iwe54 = resetn;
boot_dwe54 = resetn;
boot_iwe55 = resetn;
boot_dwe55 = resetn;
boot_iwe56 = resetn;
boot_dwe56 = resetn;
boot_iwe57 = resetn;
boot_dwe57 = resetn;
boot_iwe58 = resetn;
boot_dwe58 = resetn;
boot_iwe59 = resetn;
boot_dwe59 = resetn;
boot_iwe60 = resetn;
boot_dwe60 = resetn;
boot_iwe61 = resetn;
boot_dwe61 = resetn;
boot_iwe62 = resetn;
boot_dwe62 = resetn;
boot_iwe63 = resetn;
boot_dwe63 = resetn;
boot_iwe64 = resetn;
boot_dwe64 = resetn;
boot_iwe65 = resetn;
boot_dwe65 = resetn;
boot_iwe66 = resetn;
boot_dwe66 = resetn;
boot_iwe67 = resetn;
boot_dwe67 = resetn;
boot_iwe68 = resetn;
boot_dwe68 = resetn;
boot_iwe69 = resetn;
boot_dwe69 = resetn;
boot_iwe70 = resetn;
boot_dwe70 = resetn;
boot_iwe71 = resetn;
boot_dwe71 = resetn;
boot_iwe72 = resetn;
boot_dwe72 = resetn;
boot_iwe73 = resetn;
boot_dwe73 = resetn;
boot_iwe74 = resetn;
boot_dwe74 = resetn;
boot_iwe75 = resetn;
boot_dwe75 = resetn;
boot_iwe76 = resetn;
boot_dwe76 = resetn;
boot_iwe77 = resetn;
boot_dwe77 = resetn;
boot_iwe78 = resetn;
boot_dwe78 = resetn;
boot_iwe79 = resetn;
boot_dwe79 = resetn;
boot_iwe80 = resetn;
boot_dwe80 = resetn;
boot_iwe81 = resetn;
boot_dwe81 = resetn;
boot_iwe82 = ~resetn;
boot_dwe82 = ~resetn;
boot_iwe83 = resetn;
boot_dwe83 = resetn;
boot_iwe84 = resetn;
boot_dwe84 = resetn;
boot_iwe85 = resetn;
boot_dwe85 = resetn;
boot_iwe86 = resetn;
boot_dwe86 = resetn;
boot_iwe87 = resetn;
boot_dwe87 = resetn;
boot_iwe88 = resetn;
boot_dwe88 = resetn;
boot_iwe89 = resetn;
boot_dwe89 = resetn;
end
83: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
boot_iwe50 = resetn;
boot_dwe50 = resetn;
boot_iwe51 = resetn;
boot_dwe51 = resetn;
boot_iwe52 = resetn;
boot_dwe52 = resetn;
boot_iwe53 = resetn;
boot_dwe53 = resetn;
boot_iwe54 = resetn;
boot_dwe54 = resetn;
boot_iwe55 = resetn;
boot_dwe55 = resetn;
boot_iwe56 = resetn;
boot_dwe56 = resetn;
boot_iwe57 = resetn;
boot_dwe57 = resetn;
boot_iwe58 = resetn;
boot_dwe58 = resetn;
boot_iwe59 = resetn;
boot_dwe59 = resetn;
boot_iwe60 = resetn;
boot_dwe60 = resetn;
boot_iwe61 = resetn;
boot_dwe61 = resetn;
boot_iwe62 = resetn;
boot_dwe62 = resetn;
boot_iwe63 = resetn;
boot_dwe63 = resetn;
boot_iwe64 = resetn;
boot_dwe64 = resetn;
boot_iwe65 = resetn;
boot_dwe65 = resetn;
boot_iwe66 = resetn;
boot_dwe66 = resetn;
boot_iwe67 = resetn;
boot_dwe67 = resetn;
boot_iwe68 = resetn;
boot_dwe68 = resetn;
boot_iwe69 = resetn;
boot_dwe69 = resetn;
boot_iwe70 = resetn;
boot_dwe70 = resetn;
boot_iwe71 = resetn;
boot_dwe71 = resetn;
boot_iwe72 = resetn;
boot_dwe72 = resetn;
boot_iwe73 = resetn;
boot_dwe73 = resetn;
boot_iwe74 = resetn;
boot_dwe74 = resetn;
boot_iwe75 = resetn;
boot_dwe75 = resetn;
boot_iwe76 = resetn;
boot_dwe76 = resetn;
boot_iwe77 = resetn;
boot_dwe77 = resetn;
boot_iwe78 = resetn;
boot_dwe78 = resetn;
boot_iwe79 = resetn;
boot_dwe79 = resetn;
boot_iwe80 = resetn;
boot_dwe80 = resetn;
boot_iwe81 = resetn;
boot_dwe81 = resetn;
boot_iwe82 = resetn;
boot_dwe82 = resetn;
boot_iwe83 = ~resetn;
boot_dwe83 = ~resetn;
boot_iwe84 = resetn;
boot_dwe84 = resetn;
boot_iwe85 = resetn;
boot_dwe85 = resetn;
boot_iwe86 = resetn;
boot_dwe86 = resetn;
boot_iwe87 = resetn;
boot_dwe87 = resetn;
boot_iwe88 = resetn;
boot_dwe88 = resetn;
boot_iwe89 = resetn;
boot_dwe89 = resetn;
end
84: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
boot_iwe50 = resetn;
boot_dwe50 = resetn;
boot_iwe51 = resetn;
boot_dwe51 = resetn;
boot_iwe52 = resetn;
boot_dwe52 = resetn;
boot_iwe53 = resetn;
boot_dwe53 = resetn;
boot_iwe54 = resetn;
boot_dwe54 = resetn;
boot_iwe55 = resetn;
boot_dwe55 = resetn;
boot_iwe56 = resetn;
boot_dwe56 = resetn;
boot_iwe57 = resetn;
boot_dwe57 = resetn;
boot_iwe58 = resetn;
boot_dwe58 = resetn;
boot_iwe59 = resetn;
boot_dwe59 = resetn;
boot_iwe60 = resetn;
boot_dwe60 = resetn;
boot_iwe61 = resetn;
boot_dwe61 = resetn;
boot_iwe62 = resetn;
boot_dwe62 = resetn;
boot_iwe63 = resetn;
boot_dwe63 = resetn;
boot_iwe64 = resetn;
boot_dwe64 = resetn;
boot_iwe65 = resetn;
boot_dwe65 = resetn;
boot_iwe66 = resetn;
boot_dwe66 = resetn;
boot_iwe67 = resetn;
boot_dwe67 = resetn;
boot_iwe68 = resetn;
boot_dwe68 = resetn;
boot_iwe69 = resetn;
boot_dwe69 = resetn;
boot_iwe70 = resetn;
boot_dwe70 = resetn;
boot_iwe71 = resetn;
boot_dwe71 = resetn;
boot_iwe72 = resetn;
boot_dwe72 = resetn;
boot_iwe73 = resetn;
boot_dwe73 = resetn;
boot_iwe74 = resetn;
boot_dwe74 = resetn;
boot_iwe75 = resetn;
boot_dwe75 = resetn;
boot_iwe76 = resetn;
boot_dwe76 = resetn;
boot_iwe77 = resetn;
boot_dwe77 = resetn;
boot_iwe78 = resetn;
boot_dwe78 = resetn;
boot_iwe79 = resetn;
boot_dwe79 = resetn;
boot_iwe80 = resetn;
boot_dwe80 = resetn;
boot_iwe81 = resetn;
boot_dwe81 = resetn;
boot_iwe82 = resetn;
boot_dwe82 = resetn;
boot_iwe83 = resetn;
boot_dwe83 = resetn;
boot_iwe84 = ~resetn;
boot_dwe84 = ~resetn;
boot_iwe85 = resetn;
boot_dwe85 = resetn;
boot_iwe86 = resetn;
boot_dwe86 = resetn;
boot_iwe87 = resetn;
boot_dwe87 = resetn;
boot_iwe88 = resetn;
boot_dwe88 = resetn;
boot_iwe89 = resetn;
boot_dwe89 = resetn;
end
85: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
boot_iwe50 = resetn;
boot_dwe50 = resetn;
boot_iwe51 = resetn;
boot_dwe51 = resetn;
boot_iwe52 = resetn;
boot_dwe52 = resetn;
boot_iwe53 = resetn;
boot_dwe53 = resetn;
boot_iwe54 = resetn;
boot_dwe54 = resetn;
boot_iwe55 = resetn;
boot_dwe55 = resetn;
boot_iwe56 = resetn;
boot_dwe56 = resetn;
boot_iwe57 = resetn;
boot_dwe57 = resetn;
boot_iwe58 = resetn;
boot_dwe58 = resetn;
boot_iwe59 = resetn;
boot_dwe59 = resetn;
boot_iwe60 = resetn;
boot_dwe60 = resetn;
boot_iwe61 = resetn;
boot_dwe61 = resetn;
boot_iwe62 = resetn;
boot_dwe62 = resetn;
boot_iwe63 = resetn;
boot_dwe63 = resetn;
boot_iwe64 = resetn;
boot_dwe64 = resetn;
boot_iwe65 = resetn;
boot_dwe65 = resetn;
boot_iwe66 = resetn;
boot_dwe66 = resetn;
boot_iwe67 = resetn;
boot_dwe67 = resetn;
boot_iwe68 = resetn;
boot_dwe68 = resetn;
boot_iwe69 = resetn;
boot_dwe69 = resetn;
boot_iwe70 = resetn;
boot_dwe70 = resetn;
boot_iwe71 = resetn;
boot_dwe71 = resetn;
boot_iwe72 = resetn;
boot_dwe72 = resetn;
boot_iwe73 = resetn;
boot_dwe73 = resetn;
boot_iwe74 = resetn;
boot_dwe74 = resetn;
boot_iwe75 = resetn;
boot_dwe75 = resetn;
boot_iwe76 = resetn;
boot_dwe76 = resetn;
boot_iwe77 = resetn;
boot_dwe77 = resetn;
boot_iwe78 = resetn;
boot_dwe78 = resetn;
boot_iwe79 = resetn;
boot_dwe79 = resetn;
boot_iwe80 = resetn;
boot_dwe80 = resetn;
boot_iwe81 = resetn;
boot_dwe81 = resetn;
boot_iwe82 = resetn;
boot_dwe82 = resetn;
boot_iwe83 = resetn;
boot_dwe83 = resetn;
boot_iwe84 = resetn;
boot_dwe84 = resetn;
boot_iwe85 = ~resetn;
boot_dwe85 = ~resetn;
boot_iwe86 = resetn;
boot_dwe86 = resetn;
boot_iwe87 = resetn;
boot_dwe87 = resetn;
boot_iwe88 = resetn;
boot_dwe88 = resetn;
boot_iwe89 = resetn;
boot_dwe89 = resetn;
end
86: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
boot_iwe50 = resetn;
boot_dwe50 = resetn;
boot_iwe51 = resetn;
boot_dwe51 = resetn;
boot_iwe52 = resetn;
boot_dwe52 = resetn;
boot_iwe53 = resetn;
boot_dwe53 = resetn;
boot_iwe54 = resetn;
boot_dwe54 = resetn;
boot_iwe55 = resetn;
boot_dwe55 = resetn;
boot_iwe56 = resetn;
boot_dwe56 = resetn;
boot_iwe57 = resetn;
boot_dwe57 = resetn;
boot_iwe58 = resetn;
boot_dwe58 = resetn;
boot_iwe59 = resetn;
boot_dwe59 = resetn;
boot_iwe60 = resetn;
boot_dwe60 = resetn;
boot_iwe61 = resetn;
boot_dwe61 = resetn;
boot_iwe62 = resetn;
boot_dwe62 = resetn;
boot_iwe63 = resetn;
boot_dwe63 = resetn;
boot_iwe64 = resetn;
boot_dwe64 = resetn;
boot_iwe65 = resetn;
boot_dwe65 = resetn;
boot_iwe66 = resetn;
boot_dwe66 = resetn;
boot_iwe67 = resetn;
boot_dwe67 = resetn;
boot_iwe68 = resetn;
boot_dwe68 = resetn;
boot_iwe69 = resetn;
boot_dwe69 = resetn;
boot_iwe70 = resetn;
boot_dwe70 = resetn;
boot_iwe71 = resetn;
boot_dwe71 = resetn;
boot_iwe72 = resetn;
boot_dwe72 = resetn;
boot_iwe73 = resetn;
boot_dwe73 = resetn;
boot_iwe74 = resetn;
boot_dwe74 = resetn;
boot_iwe75 = resetn;
boot_dwe75 = resetn;
boot_iwe76 = resetn;
boot_dwe76 = resetn;
boot_iwe77 = resetn;
boot_dwe77 = resetn;
boot_iwe78 = resetn;
boot_dwe78 = resetn;
boot_iwe79 = resetn;
boot_dwe79 = resetn;
boot_iwe80 = resetn;
boot_dwe80 = resetn;
boot_iwe81 = resetn;
boot_dwe81 = resetn;
boot_iwe82 = resetn;
boot_dwe82 = resetn;
boot_iwe83 = resetn;
boot_dwe83 = resetn;
boot_iwe84 = resetn;
boot_dwe84 = resetn;
boot_iwe85 = resetn;
boot_dwe85 = resetn;
boot_iwe86 = ~resetn;
boot_dwe86 = ~resetn;
boot_iwe87 = resetn;
boot_dwe87 = resetn;
boot_iwe88 = resetn;
boot_dwe88 = resetn;
boot_iwe89 = resetn;
boot_dwe89 = resetn;
end
87: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
boot_iwe50 = resetn;
boot_dwe50 = resetn;
boot_iwe51 = resetn;
boot_dwe51 = resetn;
boot_iwe52 = resetn;
boot_dwe52 = resetn;
boot_iwe53 = resetn;
boot_dwe53 = resetn;
boot_iwe54 = resetn;
boot_dwe54 = resetn;
boot_iwe55 = resetn;
boot_dwe55 = resetn;
boot_iwe56 = resetn;
boot_dwe56 = resetn;
boot_iwe57 = resetn;
boot_dwe57 = resetn;
boot_iwe58 = resetn;
boot_dwe58 = resetn;
boot_iwe59 = resetn;
boot_dwe59 = resetn;
boot_iwe60 = resetn;
boot_dwe60 = resetn;
boot_iwe61 = resetn;
boot_dwe61 = resetn;
boot_iwe62 = resetn;
boot_dwe62 = resetn;
boot_iwe63 = resetn;
boot_dwe63 = resetn;
boot_iwe64 = resetn;
boot_dwe64 = resetn;
boot_iwe65 = resetn;
boot_dwe65 = resetn;
boot_iwe66 = resetn;
boot_dwe66 = resetn;
boot_iwe67 = resetn;
boot_dwe67 = resetn;
boot_iwe68 = resetn;
boot_dwe68 = resetn;
boot_iwe69 = resetn;
boot_dwe69 = resetn;
boot_iwe70 = resetn;
boot_dwe70 = resetn;
boot_iwe71 = resetn;
boot_dwe71 = resetn;
boot_iwe72 = resetn;
boot_dwe72 = resetn;
boot_iwe73 = resetn;
boot_dwe73 = resetn;
boot_iwe74 = resetn;
boot_dwe74 = resetn;
boot_iwe75 = resetn;
boot_dwe75 = resetn;
boot_iwe76 = resetn;
boot_dwe76 = resetn;
boot_iwe77 = resetn;
boot_dwe77 = resetn;
boot_iwe78 = resetn;
boot_dwe78 = resetn;
boot_iwe79 = resetn;
boot_dwe79 = resetn;
boot_iwe80 = resetn;
boot_dwe80 = resetn;
boot_iwe81 = resetn;
boot_dwe81 = resetn;
boot_iwe82 = resetn;
boot_dwe82 = resetn;
boot_iwe83 = resetn;
boot_dwe83 = resetn;
boot_iwe84 = resetn;
boot_dwe84 = resetn;
boot_iwe85 = resetn;
boot_dwe85 = resetn;
boot_iwe86 = resetn;
boot_dwe86 = resetn;
boot_iwe87 = ~resetn;
boot_dwe87 = ~resetn;
boot_iwe88 = resetn;
boot_dwe88 = resetn;
boot_iwe89 = resetn;
boot_dwe89 = resetn;
end
88: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
boot_iwe50 = resetn;
boot_dwe50 = resetn;
boot_iwe51 = resetn;
boot_dwe51 = resetn;
boot_iwe52 = resetn;
boot_dwe52 = resetn;
boot_iwe53 = resetn;
boot_dwe53 = resetn;
boot_iwe54 = resetn;
boot_dwe54 = resetn;
boot_iwe55 = resetn;
boot_dwe55 = resetn;
boot_iwe56 = resetn;
boot_dwe56 = resetn;
boot_iwe57 = resetn;
boot_dwe57 = resetn;
boot_iwe58 = resetn;
boot_dwe58 = resetn;
boot_iwe59 = resetn;
boot_dwe59 = resetn;
boot_iwe60 = resetn;
boot_dwe60 = resetn;
boot_iwe61 = resetn;
boot_dwe61 = resetn;
boot_iwe62 = resetn;
boot_dwe62 = resetn;
boot_iwe63 = resetn;
boot_dwe63 = resetn;
boot_iwe64 = resetn;
boot_dwe64 = resetn;
boot_iwe65 = resetn;
boot_dwe65 = resetn;
boot_iwe66 = resetn;
boot_dwe66 = resetn;
boot_iwe67 = resetn;
boot_dwe67 = resetn;
boot_iwe68 = resetn;
boot_dwe68 = resetn;
boot_iwe69 = resetn;
boot_dwe69 = resetn;
boot_iwe70 = resetn;
boot_dwe70 = resetn;
boot_iwe71 = resetn;
boot_dwe71 = resetn;
boot_iwe72 = resetn;
boot_dwe72 = resetn;
boot_iwe73 = resetn;
boot_dwe73 = resetn;
boot_iwe74 = resetn;
boot_dwe74 = resetn;
boot_iwe75 = resetn;
boot_dwe75 = resetn;
boot_iwe76 = resetn;
boot_dwe76 = resetn;
boot_iwe77 = resetn;
boot_dwe77 = resetn;
boot_iwe78 = resetn;
boot_dwe78 = resetn;
boot_iwe79 = resetn;
boot_dwe79 = resetn;
boot_iwe80 = resetn;
boot_dwe80 = resetn;
boot_iwe81 = resetn;
boot_dwe81 = resetn;
boot_iwe82 = resetn;
boot_dwe82 = resetn;
boot_iwe83 = resetn;
boot_dwe83 = resetn;
boot_iwe84 = resetn;
boot_dwe84 = resetn;
boot_iwe85 = resetn;
boot_dwe85 = resetn;
boot_iwe86 = resetn;
boot_dwe86 = resetn;
boot_iwe87 = resetn;
boot_dwe87 = resetn;
boot_iwe88 = ~resetn;
boot_dwe88 = ~resetn;
boot_iwe89 = resetn;
boot_dwe89 = resetn;
end
89: begin
boot_iwe0 = resetn;
boot_dwe0 = resetn;
boot_iwe1 = resetn;
boot_dwe1 = resetn;
boot_iwe2 = resetn;
boot_dwe2 = resetn;
boot_iwe3 = resetn;
boot_dwe3 = resetn;
boot_iwe4 = resetn;
boot_dwe4 = resetn;
boot_iwe5 = resetn;
boot_dwe5 = resetn;
boot_iwe6 = resetn;
boot_dwe6 = resetn;
boot_iwe7 = resetn;
boot_dwe7 = resetn;
boot_iwe8 = resetn;
boot_dwe8 = resetn;
boot_iwe9 = resetn;
boot_dwe9 = resetn;
boot_iwe10 = resetn;
boot_dwe10 = resetn;
boot_iwe11 = resetn;
boot_dwe11 = resetn;
boot_iwe12 = resetn;
boot_dwe12 = resetn;
boot_iwe13 = resetn;
boot_dwe13 = resetn;
boot_iwe14 = resetn;
boot_dwe14 = resetn;
boot_iwe15 = resetn;
boot_dwe15 = resetn;
boot_iwe16 = resetn;
boot_dwe16 = resetn;
boot_iwe17 = resetn;
boot_dwe17 = resetn;
boot_iwe18 = resetn;
boot_dwe18 = resetn;
boot_iwe19 = resetn;
boot_dwe19 = resetn;
boot_iwe20 = resetn;
boot_dwe20 = resetn;
boot_iwe21 = resetn;
boot_dwe21 = resetn;
boot_iwe22 = resetn;
boot_dwe22 = resetn;
boot_iwe23 = resetn;
boot_dwe23 = resetn;
boot_iwe24 = resetn;
boot_dwe24 = resetn;
boot_iwe25 = resetn;
boot_dwe25 = resetn;
boot_iwe26 = resetn;
boot_dwe26 = resetn;
boot_iwe27 = resetn;
boot_dwe27 = resetn;
boot_iwe28 = resetn;
boot_dwe28 = resetn;
boot_iwe29 = resetn;
boot_dwe29 = resetn;
boot_iwe30 = resetn;
boot_dwe30 = resetn;
boot_iwe31 = resetn;
boot_dwe31 = resetn;
boot_iwe32 = resetn;
boot_dwe32 = resetn;
boot_iwe33 = resetn;
boot_dwe33 = resetn;
boot_iwe34 = resetn;
boot_dwe34 = resetn;
boot_iwe35 = resetn;
boot_dwe35 = resetn;
boot_iwe36 = resetn;
boot_dwe36 = resetn;
boot_iwe37 = resetn;
boot_dwe37 = resetn;
boot_iwe38 = resetn;
boot_dwe38 = resetn;
boot_iwe39 = resetn;
boot_dwe39 = resetn;
boot_iwe40 = resetn;
boot_dwe40 = resetn;
boot_iwe41 = resetn;
boot_dwe41 = resetn;
boot_iwe42 = resetn;
boot_dwe42 = resetn;
boot_iwe43 = resetn;
boot_dwe43 = resetn;
boot_iwe44 = resetn;
boot_dwe44 = resetn;
boot_iwe45 = resetn;
boot_dwe45 = resetn;
boot_iwe46 = resetn;
boot_dwe46 = resetn;
boot_iwe47 = resetn;
boot_dwe47 = resetn;
boot_iwe48 = resetn;
boot_dwe48 = resetn;
boot_iwe49 = resetn;
boot_dwe49 = resetn;
boot_iwe50 = resetn;
boot_dwe50 = resetn;
boot_iwe51 = resetn;
boot_dwe51 = resetn;
boot_iwe52 = resetn;
boot_dwe52 = resetn;
boot_iwe53 = resetn;
boot_dwe53 = resetn;
boot_iwe54 = resetn;
boot_dwe54 = resetn;
boot_iwe55 = resetn;
boot_dwe55 = resetn;
boot_iwe56 = resetn;
boot_dwe56 = resetn;
boot_iwe57 = resetn;
boot_dwe57 = resetn;
boot_iwe58 = resetn;
boot_dwe58 = resetn;
boot_iwe59 = resetn;
boot_dwe59 = resetn;
boot_iwe60 = resetn;
boot_dwe60 = resetn;
boot_iwe61 = resetn;
boot_dwe61 = resetn;
boot_iwe62 = resetn;
boot_dwe62 = resetn;
boot_iwe63 = resetn;
boot_dwe63 = resetn;
boot_iwe64 = resetn;
boot_dwe64 = resetn;
boot_iwe65 = resetn;
boot_dwe65 = resetn;
boot_iwe66 = resetn;
boot_dwe66 = resetn;
boot_iwe67 = resetn;
boot_dwe67 = resetn;
boot_iwe68 = resetn;
boot_dwe68 = resetn;
boot_iwe69 = resetn;
boot_dwe69 = resetn;
boot_iwe70 = resetn;
boot_dwe70 = resetn;
boot_iwe71 = resetn;
boot_dwe71 = resetn;
boot_iwe72 = resetn;
boot_dwe72 = resetn;
boot_iwe73 = resetn;
boot_dwe73 = resetn;
boot_iwe74 = resetn;
boot_dwe74 = resetn;
boot_iwe75 = resetn;
boot_dwe75 = resetn;
boot_iwe76 = resetn;
boot_dwe76 = resetn;
boot_iwe77 = resetn;
boot_dwe77 = resetn;
boot_iwe78 = resetn;
boot_dwe78 = resetn;
boot_iwe79 = resetn;
boot_dwe79 = resetn;
boot_iwe80 = resetn;
boot_dwe80 = resetn;
boot_iwe81 = resetn;
boot_dwe81 = resetn;
boot_iwe82 = resetn;
boot_dwe82 = resetn;
boot_iwe83 = resetn;
boot_dwe83 = resetn;
boot_iwe84 = resetn;
boot_dwe84 = resetn;
boot_iwe85 = resetn;
boot_dwe85 = resetn;
boot_iwe86 = resetn;
boot_dwe86 = resetn;
boot_iwe87 = resetn;
boot_dwe87 = resetn;
boot_iwe88 = resetn;
boot_dwe88 = resetn;
boot_iwe89 = ~resetn;
boot_dwe89 = ~resetn;
end
90: begin
boot_iwe0 = 0;
boot_dwe0 = 0;
boot_iwe1 = 0;
boot_dwe1 = 0;
boot_iwe2 = 0;
boot_dwe2 = 0;
boot_iwe3 = 0;
boot_dwe3 = 0;
boot_iwe4 = 0;
boot_dwe4 = 0;
boot_iwe5 = 0;
boot_dwe5 = 0;
boot_iwe6 = 0;
boot_dwe6 = 0;
boot_iwe7 = 0;
boot_dwe7 = 0;
boot_iwe8 = 0;
boot_dwe8 = 0;
boot_iwe9 = 0;
boot_dwe9 = 0;
boot_iwe10 = 0;
boot_dwe10 = 0;
boot_iwe11 = 0;
boot_dwe11 = 0;
boot_iwe12 = 0;
boot_dwe12 = 0;
boot_iwe13 = 0;
boot_dwe13 = 0;
boot_iwe14 = 0;
boot_dwe14 = 0;
boot_iwe15 = 0;
boot_dwe15 = 0;
boot_iwe16 = 0;
boot_dwe16 = 0;
boot_iwe17 = 0;
boot_dwe17 = 0;
boot_iwe18 = 0;
boot_dwe18 = 0;
boot_iwe19 = 0;
boot_dwe19 = 0;
boot_iwe20 = 0;
boot_dwe20 = 0;
boot_iwe21 = 0;
boot_dwe21 = 0;
boot_iwe22 = 0;
boot_dwe22 = 0;
boot_iwe23 = 0;
boot_dwe23 = 0;
boot_iwe24 = 0;
boot_dwe24 = 0;
boot_iwe25 = 0;
boot_dwe25 = 0;
boot_iwe26 = 0;
boot_dwe26 = 0;
boot_iwe27 = 0;
boot_dwe27 = 0;
boot_iwe28 = 0;
boot_dwe28 = 0;
boot_iwe29 = 0;
boot_dwe29 = 0;
boot_iwe30 = 0;
boot_dwe30 = 0;
boot_iwe31 = 0;
boot_dwe31 = 0;
boot_iwe32 = 0;
boot_dwe32 = 0;
boot_iwe33 = 0;
boot_dwe33 = 0;
boot_iwe34 = 0;
boot_dwe34 = 0;
boot_iwe35 = 0;
boot_dwe35 = 0;
boot_iwe36 = 0;
boot_dwe36 = 0;
boot_iwe37 = 0;
boot_dwe37 = 0;
boot_iwe38 = 0;
boot_dwe38 = 0;
boot_iwe39 = 0;
boot_dwe39 = 0;
boot_iwe40 = 0;
boot_dwe40 = 0;
boot_iwe41 = 0;
boot_dwe41 = 0;
boot_iwe42 = 0;
boot_dwe42 = 0;
boot_iwe43 = 0;
boot_dwe43 = 0;
boot_iwe44 = 0;
boot_dwe44 = 0;
boot_iwe45 = 0;
boot_dwe45 = 0;
boot_iwe46 = 0;
boot_dwe46 = 0;
boot_iwe47 = 0;
boot_dwe47 = 0;
boot_iwe48 = 0;
boot_dwe48 = 0;
boot_iwe49 = 0;
boot_dwe49 = 0;
boot_iwe50 = 0;
boot_dwe50 = 0;
boot_iwe51 = 0;
boot_dwe51 = 0;
boot_iwe52 = 0;
boot_dwe52 = 0;
boot_iwe53 = 0;
boot_dwe53 = 0;
boot_iwe54 = 0;
boot_dwe54 = 0;
boot_iwe55 = 0;
boot_dwe55 = 0;
boot_iwe56 = 0;
boot_dwe56 = 0;
boot_iwe57 = 0;
boot_dwe57 = 0;
boot_iwe58 = 0;
boot_dwe58 = 0;
boot_iwe59 = 0;
boot_dwe59 = 0;
boot_iwe60 = 0;
boot_dwe60 = 0;
boot_iwe61 = 0;
boot_dwe61 = 0;
boot_iwe62 = 0;
boot_dwe62 = 0;
boot_iwe63 = 0;
boot_dwe63 = 0;
boot_iwe64 = 0;
boot_dwe64 = 0;
boot_iwe65 = 0;
boot_dwe65 = 0;
boot_iwe66 = 0;
boot_dwe66 = 0;
boot_iwe67 = 0;
boot_dwe67 = 0;
boot_iwe68 = 0;
boot_dwe68 = 0;
boot_iwe69 = 0;
boot_dwe69 = 0;
boot_iwe70 = 0;
boot_dwe70 = 0;
boot_iwe71 = 0;
boot_dwe71 = 0;
boot_iwe72 = 0;
boot_dwe72 = 0;
boot_iwe73 = 0;
boot_dwe73 = 0;
boot_iwe74 = 0;
boot_dwe74 = 0;
boot_iwe75 = 0;
boot_dwe75 = 0;
boot_iwe76 = 0;
boot_dwe76 = 0;
boot_iwe77 = 0;
boot_dwe77 = 0;
boot_iwe78 = 0;
boot_dwe78 = 0;
boot_iwe79 = 0;
boot_dwe79 = 0;
boot_iwe80 = 0;
boot_dwe80 = 0;
boot_iwe81 = 0;
boot_dwe81 = 0;
boot_iwe82 = 0;
boot_dwe82 = 0;
boot_iwe83 = 0;
boot_dwe83 = 0;
boot_iwe84 = 0;
boot_dwe84 = 0;
boot_iwe85 = 0;
boot_dwe85 = 0;
boot_iwe86 = 0;
boot_dwe86 = 0;
boot_iwe87 = 0;
boot_dwe87 = 0;
boot_iwe88 = 0;
boot_dwe88 = 0;
boot_iwe89 = 0;
boot_dwe89 = 0;
end
endcase
end
endmodule |
`define NO_PLI 1
`define TEST_BENCH 1
`timescale 1ms / 10us
module test_bench ;
parameter I_DATAWIDTH=32;
parameter I_ADDRESSWIDTH=16;
parameter I_SIZE=65536;
parameter D_DATAWIDTH=32;
parameter D_BYTEENAWIDTH=4; // usually should be D_DATAWIDTH/8
parameter D_ADDRESSWIDTH=16;
parameter D_SIZE=65536;
reg clk;
reg resetn;
wire [31:0] d_writedataout;
reg [13:0] boot_iaddr;
wire [31:0] boot_idata;
reg [13:0] boot_daddr;
wire [31:0] boot_ddata;
reg [31:0] imem [16383:0];
reg [31:0] dmem [16383:0];
reg [6:0] processor_select;
system90 p
(
.clk (clk),
.resetn (resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.reg_file_b_readdataout (d_writedataout),
.processor_select(processor_select));
/**************** Reset and stimulate clock ********************/
initial
clk = 1'b1;
always
#0.01 clk <= ~clk;
initial
begin
#0 resetn <= 0;
#29700 resetn <= 1;
end
initial // NEW
begin
#0 processor_select = 0;
#0 $readmemh("./app/tile0.instr.rif",imem);
#0 $readmemh("./app/tile0.data.rif",dmem);
#0 boot_iaddr=0;
#0 boot_daddr=0;
#330 processor_select = 1;
#0 $readmemh("./app/tile1.instr.rif",imem);
#0 $readmemh("./app/tile1.data.rif",dmem);
#0 boot_iaddr=0;
#0 boot_daddr=0;
#330 processor_select = 2;
#0 $readmemh("./app/tile2.instr.rif",imem);
#0 $readmemh("./app/tile2.data.rif",dmem);
#0 boot_iaddr=0;
#0 boot_daddr=0;
#330 processor_select = 3;
#0 $readmemh("./app/tile3.instr.rif",imem);
#0 $readmemh("./app/tile3.data.rif",dmem);
#0 boot_iaddr=0;
#0 boot_daddr=0;
#330 processor_select = 4;
#0 $readmemh("./app/tile4.instr.rif",imem);
#0 $readmemh("./app/tile4.data.rif",dmem);
#0 boot_iaddr=0;
#0 boot_daddr=0;
#330 processor_select = 5;
#0 $readmemh("./app/tile5.instr.rif",imem);
#0 $readmemh("./app/tile5.data.rif",dmem);
#0 boot_iaddr=0;
#0 boot_daddr=0;
#330 processor_select = 6;
#0 $readmemh("./app/tile6.instr.rif",imem);
#0 $readmemh("./app/tile6.data.rif",dmem);
#0 boot_iaddr=0;
#0 boot_daddr=0;
#330 processor_select = 7;
#0 $readmemh("./app/tile7.instr.rif",imem);
#0 $readmemh("./app/tile7.data.rif",dmem);
#0 boot_iaddr=0;
#0 boot_daddr=0;
#330 processor_select = 8;
#0 $readmemh("./app/tile8.instr.rif",imem);
#0 $readmemh("./app/tile8.data.rif",dmem);
#0 boot_iaddr=0;
#0 boot_daddr=0;
#330 processor_select = 9;
#0 $readmemh("./app/tile9.instr.rif",imem);
#0 $readmemh("./app/tile9.data.rif",dmem);
#0 boot_iaddr=0;
#0 boot_daddr=0;
#330 processor_select = 10;
#0 $readmemh("./app/tile10.instr.rif",imem);
#0 $readmemh("./app/tile10.data.rif",dmem);
#0 boot_iaddr=0;
#0 boot_daddr=0;
#330 processor_select = 11;
#0 $readmemh("./app/tile11.instr.rif",imem);
#0 $readmemh("./app/tile11.data.rif",dmem);
#0 boot_iaddr=0;
#0 boot_daddr=0;
#330 processor_select = 12;
#0 $readmemh("./app/tile12.instr.rif",imem);
#0 $readmemh("./app/tile12.data.rif",dmem);
#0 boot_iaddr=0;
#0 boot_daddr=0;
#330 processor_select = 13;
#0 $readmemh("./app/tile13.instr.rif",imem);
#0 $readmemh("./app/tile13.data.rif",dmem);
#0 boot_iaddr=0;
#0 boot_daddr=0;
#330 processor_select = 14;
#0 $readmemh("./app/tile14.instr.rif",imem);
#0 $readmemh("./app/tile14.data.rif",dmem);
#0 boot_iaddr=0;
#0 boot_daddr=0;
#330 processor_select = 15;
#0 $readmemh("./app/tile15.instr.rif",imem);
#0 $readmemh("./app/tile15.data.rif",dmem);
#0 boot_iaddr=0;
#0 boot_daddr=0;
#330 processor_select = 16;
#0 $readmemh("./app/tile16.instr.rif",imem);
#0 $readmemh("./app/tile16.data.rif",dmem);
#0 boot_iaddr=0;
#0 boot_daddr=0;
#330 processor_select = 17;
#0 $readmemh("./app/tile17.instr.rif",imem);
#0 $readmemh("./app/tile17.data.rif",dmem);
#0 boot_iaddr=0;
#0 boot_daddr=0;
#330 processor_select = 18;
#0 $readmemh("./app/tile18.instr.rif",imem);
#0 $readmemh("./app/tile18.data.rif",dmem);
#0 boot_iaddr=0;
#0 boot_daddr=0;
#330 processor_select = 19;
#0 $readmemh("./app/tile19.instr.rif",imem);
#0 $readmemh("./app/tile19.data.rif",dmem);
#0 boot_iaddr=0;
#0 boot_daddr=0;
#330 processor_select = 20;
#0 $readmemh("./app/tile20.instr.rif",imem);
#0 $readmemh("./app/tile20.data.rif",dmem);
#0 boot_iaddr=0;
#0 boot_daddr=0;
#330 processor_select = 21;
#0 $readmemh("./app/tile21.instr.rif",imem);
#0 $readmemh("./app/tile21.data.rif",dmem);
#0 boot_iaddr=0;
#0 boot_daddr=0;
#330 processor_select = 22;
#0 $readmemh("./app/tile22.instr.rif",imem);
#0 $readmemh("./app/tile22.data.rif",dmem);
#0 boot_iaddr=0;
#0 boot_daddr=0;
#330 processor_select = 23;
#0 $readmemh("./app/tile23.instr.rif",imem);
#0 $readmemh("./app/tile23.data.rif",dmem);
#0 boot_iaddr=0;
#0 boot_daddr=0;
#330 processor_select = 24;
#0 $readmemh("./app/tile24.instr.rif",imem);
#0 $readmemh("./app/tile24.data.rif",dmem);
#0 boot_iaddr=0;
#0 boot_daddr=0;
#330 processor_select = 25;
#0 $readmemh("./app/tile25.instr.rif",imem);
#0 $readmemh("./app/tile25.data.rif",dmem);
#0 boot_iaddr=0;
#0 boot_daddr=0;
#330 processor_select = 26;
#0 $readmemh("./app/tile26.instr.rif",imem);
#0 $readmemh("./app/tile26.data.rif",dmem);
#0 boot_iaddr=0;
#0 boot_daddr=0;
#330 processor_select = 27;
#0 $readmemh("./app/tile27.instr.rif",imem);
#0 $readmemh("./app/tile27.data.rif",dmem);
#0 boot_iaddr=0;
#0 boot_daddr=0;
#330 processor_select = 28;
#0 $readmemh("./app/tile28.instr.rif",imem);
#0 $readmemh("./app/tile28.data.rif",dmem);
#0 boot_iaddr=0;
#0 boot_daddr=0;
#330 processor_select = 29;
#0 $readmemh("./app/tile29.instr.rif",imem);
#0 $readmemh("./app/tile29.data.rif",dmem);
#0 boot_iaddr=0;
#0 boot_daddr=0;
#330 processor_select = 30;
#0 $readmemh("./app/tile30.instr.rif",imem);
#0 $readmemh("./app/tile30.data.rif",dmem);
#0 boot_iaddr=0;
#0 boot_daddr=0;
#330 processor_select = 31;
#0 $readmemh("./app/tile31.instr.rif",imem);
#0 $readmemh("./app/tile31.data.rif",dmem);
#0 boot_iaddr=0;
#0 boot_daddr=0;
#330 processor_select = 32;
#0 $readmemh("./app/tile32.instr.rif",imem);
#0 $readmemh("./app/tile32.data.rif",dmem);
#0 boot_iaddr=0;
#0 boot_daddr=0;
#330 processor_select = 33;
#0 $readmemh("./app/tile33.instr.rif",imem);
#0 $readmemh("./app/tile33.data.rif",dmem);
#0 boot_iaddr=0;
#0 boot_daddr=0;
#330 processor_select = 34;
#0 $readmemh("./app/tile34.instr.rif",imem);
#0 $readmemh("./app/tile34.data.rif",dmem);
#0 boot_iaddr=0;
#0 boot_daddr=0;
#330 processor_select = 35;
#0 $readmemh("./app/tile35.instr.rif",imem);
#0 $readmemh("./app/tile35.data.rif",dmem);
#0 boot_iaddr=0;
#0 boot_daddr=0;
#330 processor_select = 36;
#0 $readmemh("./app/tile36.instr.rif",imem);
#0 $readmemh("./app/tile36.data.rif",dmem);
#0 boot_iaddr=0;
#0 boot_daddr=0;
#330 processor_select = 37;
#0 $readmemh("./app/tile37.instr.rif",imem);
#0 $readmemh("./app/tile37.data.rif",dmem);
#0 boot_iaddr=0;
#0 boot_daddr=0;
#330 processor_select = 38;
#0 $readmemh("./app/tile38.instr.rif",imem);
#0 $readmemh("./app/tile38.data.rif",dmem);
#0 boot_iaddr=0;
#0 boot_daddr=0;
#330 processor_select = 39;
#0 $readmemh("./app/tile39.instr.rif",imem);
#0 $readmemh("./app/tile39.data.rif",dmem);
#0 boot_iaddr=0;
#0 boot_daddr=0;
#330 processor_select = 40;
#0 $readmemh("./app/tile40.instr.rif",imem);
#0 $readmemh("./app/tile40.data.rif",dmem);
#0 boot_iaddr=0;
#0 boot_daddr=0;
#330 processor_select = 41;
#0 $readmemh("./app/tile41.instr.rif",imem);
#0 $readmemh("./app/tile41.data.rif",dmem);
#0 boot_iaddr=0;
#0 boot_daddr=0;
#330 processor_select = 42;
#0 $readmemh("./app/tile42.instr.rif",imem);
#0 $readmemh("./app/tile42.data.rif",dmem);
#0 boot_iaddr=0;
#0 boot_daddr=0;
#330 processor_select = 43;
#0 $readmemh("./app/tile43.instr.rif",imem);
#0 $readmemh("./app/tile43.data.rif",dmem);
#0 boot_iaddr=0;
#0 boot_daddr=0;
#330 processor_select = 44;
#0 $readmemh("./app/tile44.instr.rif",imem);
#0 $readmemh("./app/tile44.data.rif",dmem);
#0 boot_iaddr=0;
#0 boot_daddr=0;
#330 processor_select = 45;
#0 $readmemh("./app/tile45.instr.rif",imem);
#0 $readmemh("./app/tile45.data.rif",dmem);
#0 boot_iaddr=0;
#0 boot_daddr=0;
#330 processor_select = 46;
#0 $readmemh("./app/tile46.instr.rif",imem);
#0 $readmemh("./app/tile46.data.rif",dmem);
#0 boot_iaddr=0;
#0 boot_daddr=0;
#330 processor_select = 47;
#0 $readmemh("./app/tile47.instr.rif",imem);
#0 $readmemh("./app/tile47.data.rif",dmem);
#0 boot_iaddr=0;
#0 boot_daddr=0;
#330 processor_select = 48;
#0 $readmemh("./app/tile48.instr.rif",imem);
#0 $readmemh("./app/tile48.data.rif",dmem);
#0 boot_iaddr=0;
#0 boot_daddr=0;
#330 processor_select = 49;
#0 $readmemh("./app/tile49.instr.rif",imem);
#0 $readmemh("./app/tile49.data.rif",dmem);
#0 boot_iaddr=0;
#0 boot_daddr=0;
#330 processor_select = 50;
#0 $readmemh("./app/tile50.instr.rif",imem);
#0 $readmemh("./app/tile50.data.rif",dmem);
#0 boot_iaddr=0;
#0 boot_daddr=0;
#330 processor_select = 51;
#0 $readmemh("./app/tile51.instr.rif",imem);
#0 $readmemh("./app/tile51.data.rif",dmem);
#0 boot_iaddr=0;
#0 boot_daddr=0;
#330 processor_select = 52;
#0 $readmemh("./app/tile52.instr.rif",imem);
#0 $readmemh("./app/tile52.data.rif",dmem);
#0 boot_iaddr=0;
#0 boot_daddr=0;
#330 processor_select = 53;
#0 $readmemh("./app/tile53.instr.rif",imem);
#0 $readmemh("./app/tile53.data.rif",dmem);
#0 boot_iaddr=0;
#0 boot_daddr=0;
#330 processor_select = 54;
#0 $readmemh("./app/tile54.instr.rif",imem);
#0 $readmemh("./app/tile54.data.rif",dmem);
#0 boot_iaddr=0;
#0 boot_daddr=0;
#330 processor_select = 55;
#0 $readmemh("./app/tile55.instr.rif",imem);
#0 $readmemh("./app/tile55.data.rif",dmem);
#0 boot_iaddr=0;
#0 boot_daddr=0;
#330 processor_select = 56;
#0 $readmemh("./app/tile56.instr.rif",imem);
#0 $readmemh("./app/tile56.data.rif",dmem);
#0 boot_iaddr=0;
#0 boot_daddr=0;
#330 processor_select = 57;
#0 $readmemh("./app/tile57.instr.rif",imem);
#0 $readmemh("./app/tile57.data.rif",dmem);
#0 boot_iaddr=0;
#0 boot_daddr=0;
#330 processor_select = 58;
#0 $readmemh("./app/tile58.instr.rif",imem);
#0 $readmemh("./app/tile58.data.rif",dmem);
#0 boot_iaddr=0;
#0 boot_daddr=0;
#330 processor_select = 59;
#0 $readmemh("./app/tile59.instr.rif",imem);
#0 $readmemh("./app/tile59.data.rif",dmem);
#0 boot_iaddr=0;
#0 boot_daddr=0;
#330 processor_select = 60;
#0 $readmemh("./app/tile60.instr.rif",imem);
#0 $readmemh("./app/tile60.data.rif",dmem);
#0 boot_iaddr=0;
#0 boot_daddr=0;
#330 processor_select = 61;
#0 $readmemh("./app/tile61.instr.rif",imem);
#0 $readmemh("./app/tile61.data.rif",dmem);
#0 boot_iaddr=0;
#0 boot_daddr=0;
#330 processor_select = 62;
#0 $readmemh("./app/tile62.instr.rif",imem);
#0 $readmemh("./app/tile62.data.rif",dmem);
#0 boot_iaddr=0;
#0 boot_daddr=0;
#330 processor_select = 63;
#0 $readmemh("./app/tile63.instr.rif",imem);
#0 $readmemh("./app/tile63.data.rif",dmem);
#0 boot_iaddr=0;
#0 boot_daddr=0;
#330 processor_select = 64;
#0 $readmemh("./app/tile64.instr.rif",imem);
#0 $readmemh("./app/tile64.data.rif",dmem);
#0 boot_iaddr=0;
#0 boot_daddr=0;
#330 processor_select = 65;
#0 $readmemh("./app/tile65.instr.rif",imem);
#0 $readmemh("./app/tile65.data.rif",dmem);
#0 boot_iaddr=0;
#0 boot_daddr=0;
#330 processor_select = 66;
#0 $readmemh("./app/tile66.instr.rif",imem);
#0 $readmemh("./app/tile66.data.rif",dmem);
#0 boot_iaddr=0;
#0 boot_daddr=0;
#330 processor_select = 67;
#0 $readmemh("./app/tile67.instr.rif",imem);
#0 $readmemh("./app/tile67.data.rif",dmem);
#0 boot_iaddr=0;
#0 boot_daddr=0;
#330 processor_select = 68;
#0 $readmemh("./app/tile68.instr.rif",imem);
#0 $readmemh("./app/tile68.data.rif",dmem);
#0 boot_iaddr=0;
#0 boot_daddr=0;
#330 processor_select = 69;
#0 $readmemh("./app/tile69.instr.rif",imem);
#0 $readmemh("./app/tile69.data.rif",dmem);
#0 boot_iaddr=0;
#0 boot_daddr=0;
#330 processor_select = 70;
#0 $readmemh("./app/tile70.instr.rif",imem);
#0 $readmemh("./app/tile70.data.rif",dmem);
#0 boot_iaddr=0;
#0 boot_daddr=0;
#330 processor_select = 71;
#0 $readmemh("./app/tile71.instr.rif",imem);
#0 $readmemh("./app/tile71.data.rif",dmem);
#0 boot_iaddr=0;
#0 boot_daddr=0;
#330 processor_select = 72;
#0 $readmemh("./app/tile72.instr.rif",imem);
#0 $readmemh("./app/tile72.data.rif",dmem);
#0 boot_iaddr=0;
#0 boot_daddr=0;
#330 processor_select = 73;
#0 $readmemh("./app/tile73.instr.rif",imem);
#0 $readmemh("./app/tile73.data.rif",dmem);
#0 boot_iaddr=0;
#0 boot_daddr=0;
#330 processor_select = 74;
#0 $readmemh("./app/tile74.instr.rif",imem);
#0 $readmemh("./app/tile74.data.rif",dmem);
#0 boot_iaddr=0;
#0 boot_daddr=0;
#330 processor_select = 75;
#0 $readmemh("./app/tile75.instr.rif",imem);
#0 $readmemh("./app/tile75.data.rif",dmem);
#0 boot_iaddr=0;
#0 boot_daddr=0;
#330 processor_select = 76;
#0 $readmemh("./app/tile76.instr.rif",imem);
#0 $readmemh("./app/tile76.data.rif",dmem);
#0 boot_iaddr=0;
#0 boot_daddr=0;
#330 processor_select = 77;
#0 $readmemh("./app/tile77.instr.rif",imem);
#0 $readmemh("./app/tile77.data.rif",dmem);
#0 boot_iaddr=0;
#0 boot_daddr=0;
#330 processor_select = 78;
#0 $readmemh("./app/tile78.instr.rif",imem);
#0 $readmemh("./app/tile78.data.rif",dmem);
#0 boot_iaddr=0;
#0 boot_daddr=0;
#330 processor_select = 79;
#0 $readmemh("./app/tile79.instr.rif",imem);
#0 $readmemh("./app/tile79.data.rif",dmem);
#0 boot_iaddr=0;
#0 boot_daddr=0;
#330 processor_select = 80;
#0 $readmemh("./app/tile80.instr.rif",imem);
#0 $readmemh("./app/tile80.data.rif",dmem);
#0 boot_iaddr=0;
#0 boot_daddr=0;
#330 processor_select = 81;
#0 $readmemh("./app/tile81.instr.rif",imem);
#0 $readmemh("./app/tile81.data.rif",dmem);
#0 boot_iaddr=0;
#0 boot_daddr=0;
#330 processor_select = 82;
#0 $readmemh("./app/tile82.instr.rif",imem);
#0 $readmemh("./app/tile82.data.rif",dmem);
#0 boot_iaddr=0;
#0 boot_daddr=0;
#330 processor_select = 83;
#0 $readmemh("./app/tile83.instr.rif",imem);
#0 $readmemh("./app/tile83.data.rif",dmem);
#0 boot_iaddr=0;
#0 boot_daddr=0;
#330 processor_select = 84;
#0 $readmemh("./app/tile84.instr.rif",imem);
#0 $readmemh("./app/tile84.data.rif",dmem);
#0 boot_iaddr=0;
#0 boot_daddr=0;
#330 processor_select = 85;
#0 $readmemh("./app/tile85.instr.rif",imem);
#0 $readmemh("./app/tile85.data.rif",dmem);
#0 boot_iaddr=0;
#0 boot_daddr=0;
#330 processor_select = 86;
#0 $readmemh("./app/tile86.instr.rif",imem);
#0 $readmemh("./app/tile86.data.rif",dmem);
#0 boot_iaddr=0;
#0 boot_daddr=0;
#330 processor_select = 87;
#0 $readmemh("./app/tile87.instr.rif",imem);
#0 $readmemh("./app/tile87.data.rif",dmem);
#0 boot_iaddr=0;
#0 boot_daddr=0;
#330 processor_select = 88;
#0 $readmemh("./app/tile88.instr.rif",imem);
#0 $readmemh("./app/tile88.data.rif",dmem);
#0 boot_iaddr=0;
#0 boot_daddr=0;
#330 processor_select = 89;
#0 $readmemh("./app/tile89.instr.rif",imem);
#0 $readmemh("./app/tile89.data.rif",dmem);
#0 boot_iaddr=0;
#0 boot_daddr=0;
#330 processor_select = 90;
end
/**************** Boot loader ********************/
always@(posedge clk)
begin
if (~resetn)
boot_iaddr<=boot_iaddr+1;
if (~resetn)
boot_daddr<=boot_daddr+1;
end
assign boot_idata=imem[boot_iaddr];
assign boot_ddata=dmem[boot_daddr];
endmodule |
module diffeq_paj_convert (Xinport, Yinport, Uinport, Aport, DXport, Xoutport, Youtport, Uoutport, CLK, reset);
input[31:0] Xinport;
input[31:0] Yinport;
input[31:0] Uinport;
input[31:0] Aport;
input[31:0] DXport;
input CLK;
input reset;
output[31:0] Xoutport;
output[31:0] Youtport;
output[31:0] Uoutport;
reg[31:0] Xoutport;
reg[31:0] Youtport;
reg[31:0] Uoutport;
reg[31:0] x_var;
reg[31:0] y_var;
reg[31:0] u_var;
wire[31:0] temp;
reg looping;
assign temp = u_var * DXport;
always @(posedge CLK)
begin
if (reset == 1'b1)
begin
looping <= 1'b0;
x_var <= 0;
y_var <= 0;
u_var <= 0;
end
else
if (looping == 1'b0)
begin
x_var <= Xinport;
y_var <= Yinport;
u_var <= Uinport;
looping <= 1'b1;
end
else if (x_var < Aport)
begin
u_var <= (u_var - (temp/*u_var * DXport*/ * 3 * x_var)) - (DXport * 3 * y_var);
y_var <= y_var + temp;//(u_var * DXport);
x_var <= x_var + DXport;
looping <= looping;
end
else
begin
Xoutport <= x_var ;
Youtport <= y_var ;
Uoutport <= u_var ;
looping <= 1'b0;
end
end
endmodule
|
/*--------------------------------------------------------------------------
--------------------------------------------------------------------------
-- File Name : diffeq.v
-- Author(s) : P. Sridhar
-- Affiliation : Laboratory for Digital Design Environments
-- Department of Electrical & Computer Engineering
-- University of Cincinnati
-- Date Created : June 1991.
-- Introduction : Behavioral description of a differential equation
-- solver written in a synthesizable subset of VHDL.
-- Source : Written in HardwareC by Rajesh Gupta, Stanford Univ.
-- Obtained from the Highlevel Synthesis Workshop
-- Repository.
--
-- Modified For Synthesis by Jay(anta) Roy, University of Cincinnati.
-- Date Modified : Sept, 91.
--
-- Disclaimer : This comes with absolutely no guarantees of any
-- kind (just stating the obvious ...)
--
-- Acknowledgement : The Distributed Synthesis Systems research at
-- the Laboratory for Digital Design Environments,
-- University of Cincinnati, is sponsored in part
-- by the Defense Advanced Research Projects Agency
-- under order number 7056 monitored by the Federal
-- Bureau of Investigation under contract number
-- J-FBI-89-094.
--
--------------------------------------------------------------------------
-------------------------------------------------------------------------*/
module diffeq_f_systemC(aport, dxport, xport, yport, uport, clk, reset);
input clk;
input reset;
input [31:0]aport;
input [31:0]dxport;
output [31:0]xport;
output [31:0]yport;
output [31:0]uport;
reg [31:0]xport;
reg [31:0]yport;
reg [31:0]uport;
wire [31:0]temp;
assign temp = uport * dxport;
always @(posedge clk )
begin
if (reset == 1'b1)
begin
xport <= 0;
yport <= 0;
uport <= 0;
end
else
if (xport < aport)
begin
xport <= xport + dxport;
yport <= yport + temp;//(uport * dxport);
uport <= (uport - (temp/*(uport * dxport)*/ * (5 * xport))) - (dxport * (3 * yport));
end
end
endmodule
|
`include "DMA_DEFINE.vh"
`ifdef DMA_HAVE_AHB1
`ifdef DMA_HAVE_BRIDGE
module dma_ahbdec
(
haddr,
c0dmabs,
`ifdef DMA_HAVE_CH1
c1dmabs,
`endif
`ifdef DMA_HAVE_CH2
c2dmabs,
`endif
`ifdef DMA_HAVE_CH3
c3dmabs,
`endif
`ifdef DMA_HAVE_CH4
c4dmabs,
`endif
`ifdef DMA_HAVE_CH5
c5dmabs,
`endif
`ifdef DMA_HAVE_CH6
c6dmabs,
`endif
`ifdef DMA_HAVE_CH7
c7dmabs,
`endif
c0brbs,
`ifdef DMA_HAVE_CH1
c1brbs,
`endif
`ifdef DMA_HAVE_CH2
c2brbs,
`endif
`ifdef DMA_HAVE_CH3
c3brbs,
`endif
`ifdef DMA_HAVE_CH4
c4brbs,
`endif
`ifdef DMA_HAVE_CH5
c5brbs,
`endif
`ifdef DMA_HAVE_CH6
c6brbs,
`endif
`ifdef DMA_HAVE_CH7
c7brbs,
`endif
hsel_dma,
hsel_br
);
input [`DMA_HADDR_WIDTH-1:0] haddr;
input [31:16] c0brbs;
`ifdef DMA_HAVE_CH1
input [31:16] c1brbs;
`endif
`ifdef DMA_HAVE_CH2
input [31:16] c2brbs;
`endif
`ifdef DMA_HAVE_CH3
input [31:16] c3brbs;
`endif
`ifdef DMA_HAVE_CH4
input [31:16] c4brbs;
`endif
`ifdef DMA_HAVE_CH5
input [31:16] c5brbs;
`endif
`ifdef DMA_HAVE_CH6
input [31:16] c6brbs;
`endif
`ifdef DMA_HAVE_CH7
input [31:16] c7brbs;
`endif
input [31:16] c0dmabs;
`ifdef DMA_HAVE_CH1
input [31:16] c1dmabs;
`endif
`ifdef DMA_HAVE_CH2
input [31:16] c2dmabs;
`endif
`ifdef DMA_HAVE_CH3
input [31:16] c3dmabs;
`endif
`ifdef DMA_HAVE_CH4
input [31:16] c4dmabs;
`endif
`ifdef DMA_HAVE_CH5
input [31:16] c5dmabs;
`endif
`ifdef DMA_HAVE_CH6
input [31:16] c6dmabs;
`endif
`ifdef DMA_HAVE_CH7
input [31:16] c7dmabs;
`endif
output [`DMA_MAX_CHNO-1:0] hsel_dma;
output [`DMA_MAX_CHNO-1:0] hsel_br;
reg [3:0] c0dmamsk;
`ifdef DMA_HAVE_CH1
reg [3:0] c1dmamsk;
`endif
`ifdef DMA_HAVE_CH2
reg [3:0] c2dmamsk;
`endif
`ifdef DMA_HAVE_CH3
reg [3:0] c3dmamsk;
`endif
`ifdef DMA_HAVE_CH4
reg [3:0] c4dmamsk;
`endif
`ifdef DMA_HAVE_CH5
reg [3:0] c5dmamsk;
`endif
`ifdef DMA_HAVE_CH6
reg [3:0] c6dmamsk;
`endif
`ifdef DMA_HAVE_CH7
reg [3:0] c7dmamsk;
`endif
reg [3:0] c0brmsk;
`ifdef DMA_HAVE_CH1
reg [3:0] c1brmsk;
`endif
`ifdef DMA_HAVE_CH2
reg [3:0] c2brmsk;
`endif
`ifdef DMA_HAVE_CH3
reg [3:0] c3brmsk;
`endif
`ifdef DMA_HAVE_CH4
reg [3:0] c4brmsk;
`endif
`ifdef DMA_HAVE_CH5
reg [3:0] c5brmsk;
`endif
`ifdef DMA_HAVE_CH6
reg [3:0] c6brmsk;
`endif
`ifdef DMA_HAVE_CH7
reg [3:0] c7brmsk;
`endif
always @(c0dmabs)
case(c0dmabs[19:16])
'b0000: c0dmamsk = 'b0000;
'b0001: c0dmamsk = 'b0001;
'b0010: c0dmamsk = 'b0011;
'b0011: c0dmamsk = 'b0111;
default: c0dmamsk = 'b1111;
endcase
`ifdef DMA_HAVE_CH1
always @(c1dmabs)
case(c1dmabs[19:16])
'b0000: c1dmamsk = 'b0000;
'b0001: c1dmamsk = 'b0001;
'b0010: c1dmamsk = 'b0011;
'b0011: c1dmamsk = 'b0111;
default: c1dmamsk = 'b1111;
endcase
`endif
`ifdef DMA_HAVE_CH2
always @(c2dmabs)
case(c2dmabs[19:16])
'b0000: c2dmamsk = 'b0000;
'b0001: c2dmamsk = 'b0001;
'b0010: c2dmamsk = 'b0011;
'b0011: c2dmamsk = 'b0111;
default: c2dmamsk = 'b1111;
endcase
`endif
`ifdef DMA_HAVE_CH3
always @(c3dmabs)
case(c3dmabs[19:16])
'b0000: c3dmamsk = 'b0000;
'b0001: c3dmamsk = 'b0001;
'b0010: c3dmamsk = 'b0011;
'b0011: c3dmamsk = 'b0111;
default: c3dmamsk = 'b1111;
endcase
`endif
`ifdef DMA_HAVE_CH4
always @(c4dmabs)
case(c4dmabs[19:16])
'b0000: c4dmamsk = 'b0000;
'b0001: c4dmamsk = 'b0001;
'b0010: c4dmamsk = 'b0011;
'b0011: c4dmamsk = 'b0111;
default: c4dmamsk = 'b1111;
endcase
`endif
`ifdef DMA_HAVE_CH5
always @(c5dmabs)
case(c5dmabs[19:16])
'b0000: c5dmamsk = 'b0000;
'b0001: c5dmamsk = 'b0001;
'b0010: c5dmamsk = 'b0011;
'b0011: c5dmamsk = 'b0111;
default: c5dmamsk = 'b1111;
endcase
`endif
`ifdef DMA_HAVE_CH6
always @(c6dmabs)
case(c6dmabs[19:16])
'b0000: c6dmamsk = 'b0000;
'b0001: c6dmamsk = 'b0001;
'b0010: c6dmamsk = 'b0011;
'b0011: c6dmamsk = 'b0111;
default: c6dmamsk = 'b1111;
endcase
`endif
`ifdef DMA_HAVE_CH7
always @(c7dmabs)
case(c7dmabs[19:16])
'b0000: c7dmamsk = 'b0000;
'b0001: c7dmamsk = 'b0001;
'b0010: c7dmamsk = 'b0011;
'b0011: c7dmamsk = 'b0111;
default: c7dmamsk = 'b1111;
endcase
`endif
always @(c0brbs)
case(c0brbs[19:16])
'b0000: c0brmsk = 'b0000;
'b0001: c0brmsk = 'b0001;
'b0010: c0brmsk = 'b0011;
'b0011: c0brmsk = 'b0111;
default: c0brmsk = 'b1111;
endcase
`ifdef DMA_HAVE_CH1
always @(c1brbs)
case(c1brbs[19:16])
'b0000: c1brmsk = 'b0000;
'b0001: c1brmsk = 'b0001;
'b0010: c1brmsk = 'b0011;
'b0011: c1brmsk = 'b0111;
default: c1brmsk = 'b1111;
endcase
`endif
`ifdef DMA_HAVE_CH2
always @(c2brbs)
case(c2brbs[19:16])
'b0000: c2brmsk = 'b0000;
'b0001: c2brmsk = 'b0001;
'b0010: c2brmsk = 'b0011;
'b0011: c2brmsk = 'b0111;
default: c2brmsk = 'b1111;
endcase
`endif
`ifdef DMA_HAVE_CH3
always @(c3brbs)
case(c3brbs[19:16])
'b0000: c3brmsk = 'b0000;
'b0001: c3brmsk = 'b0001;
'b0010: c3brmsk = 'b0011;
'b0011: c3brmsk = 'b0111;
default: c3brmsk = 'b1111;
endcase
`endif
`ifdef DMA_HAVE_CH4
always @(c4brbs)
case(c4brbs[19:16])
'b0000: c4brmsk = 'b0000;
'b0001: c4brmsk = 'b0001;
'b0010: c4brmsk = 'b0011;
'b0011: c4brmsk = 'b0111;
default: c4brmsk = 'b1111;
endcase
`endif
`ifdef DMA_HAVE_CH5
always @(c5brbs)
case(c5brbs[19:16])
'b0000: c5brmsk = 'b0000;
'b0001: c5brmsk = 'b0001;
'b0010: c5brmsk = 'b0011;
'b0011: c5brmsk = 'b0111;
default: c5brmsk = 'b1111;
endcase
`endif
`ifdef DMA_HAVE_CH6
always @(c6brbs)
case(c6brbs[19:16])
'b0000: c6brmsk = 'b0000;
'b0001: c6brmsk = 'b0001;
'b0010: c6brmsk = 'b0011;
'b0011: c6brmsk = 'b0111;
default: c6brmsk = 'b1111;
endcase
`endif
`ifdef DMA_HAVE_CH7
always @(c7brbs)
case(c7brbs[19:16])
'b0000: c7brmsk = 'b0000;
'b0001: c7brmsk = 'b0001;
'b0010: c7brmsk = 'b0011;
'b0011: c7brmsk = 'b0111;
default: c7brmsk = 'b1111;
endcase
`endif
wire c0dmaen_h = (haddr[31:24] == c0dmabs[31:24]);
wire c0dmaen_l = ((haddr[23:20]|c0dmamsk[3:0]) == (c0dmabs[23:20]|c0dmamsk[3:0]));
assign hsel_dma[0] = c0dmaen_h&c0dmaen_l;
`ifdef DMA_HAVE_CH1
wire c1dmaen_h = (haddr[31:24] == c1dmabs[31:24]);
wire c1dmaen_l = ((haddr[23:20]|c1dmamsk[3:0]) == (c1dmabs[23:20]|c1dmamsk[3:0]));
assign hsel_dma[1] = c1dmaen_h&c1dmaen_l;
`endif
`ifdef DMA_HAVE_CH2
wire c2dmaen_h = (haddr[31:24] == c2dmabs[31:24]);
wire c2dmaen_l = ((haddr[23:20]|c2dmamsk[3:0]) == (c2dmabs[23:20]|c2dmamsk[3:0]));
assign hsel_dma[2] = c2dmaen_h&c2dmaen_l;
`endif
`ifdef DMA_HAVE_CH3
wire c3dmaen_h = (haddr[31:24] == c3dmabs[31:24]);
wire c3dmaen_l = ((haddr[23:20]|c3dmamsk[3:0]) == (c3dmabs[23:20]|c3dmamsk[3:0]));
assign hsel_dma[3] = c3dmaen_h&c3dmaen_l;
`endif
`ifdef DMA_HAVE_CH4
wire c4dmaen_h = (haddr[31:24] == c4dmabs[31:24]);
wire c4dmaen_l = ((haddr[23:20]|c4dmamsk[3:0]) == (c4dmabs[23:20]|c4dmamsk[3:0]));
assign hsel_dma[4] = c4dmaen_h&c4dmaen_l;
`endif
`ifdef DMA_HAVE_CH5
wire c5dmaen_h = (haddr[31:24] == c5dmabs[31:24]);
wire c5dmaen_l = ((haddr[23:20]|c5dmamsk[3:0]) == (c5dmabs[23:20]|c5dmamsk[3:0]));
assign hsel_dma[5] = c5dmaen_h&c5dmaen_l;
`endif
`ifdef DMA_HAVE_CH6
wire c6dmaen_h = (haddr[31:24] == c6dmabs[31:24]);
wire c6dmaen_l = ((haddr[23:20]|c6dmamsk[3:0]) == (c6dmabs[23:20]|c6dmamsk[3:0]));
assign hsel_dma[6] = c6dmaen_h&c6dmaen_l;
`endif
`ifdef DMA_HAVE_CH7
wire c7dmaen_h = (haddr[31:24] == c7dmabs[31:24]);
wire c7dmaen_l = ((haddr[23:20]|c7dmamsk[3:0]) == (c7dmabs[23:20]|c7dmamsk[3:0]));
assign hsel_dma[7] = c7dmaen_h&c7dmaen_l;
`endif
wire c0bren_h = (haddr[31:24] == c0brbs[31:24]);
wire c0bren_l = ((haddr[23:20]|c0brmsk[3:0]) == (c0brbs[23:20]|c0brmsk[3:0]));
assign hsel_br[0] = c0bren_h&c0bren_l;
`ifdef DMA_HAVE_CH1
wire c1bren_h = (haddr[31:24] == c1brbs[31:24]);
wire c1bren_l = ((haddr[23:20]|c1brmsk[3:0]) == (c1brbs[23:20]|c1brmsk[3:0]));
assign hsel_br[1] = c1bren_h&c1bren_l;
`endif
`ifdef DMA_HAVE_CH2
wire c2bren_h = (haddr[31:24] == c2brbs[31:24]);
wire c2bren_l = ((haddr[23:20]|c2brmsk[3:0]) == (c2brbs[23:20]|c2brmsk[3:0]));
assign hsel_br[2] = c2bren_h&c2bren_l;
`endif
`ifdef DMA_HAVE_CH3
wire c3bren_h = (haddr[31:24] == c3brbs[31:24]);
wire c3bren_l = ((haddr[23:20]|c3brmsk[3:0]) == (c3brbs[23:20]|c3brmsk[3:0]));
assign hsel_br[3] = c3bren_h&c3bren_l;
`endif
`ifdef DMA_HAVE_CH4
wire c4bren_h = (haddr[31:24] == c4brbs[31:24]);
wire c4bren_l = ((haddr[23:20]|c4brmsk[3:0]) == (c4brbs[23:20]|c4brmsk[3:0]));
assign hsel_br[4] = c4bren_h&c4bren_l;
`endif
`ifdef DMA_HAVE_CH5
wire c5bren_h = (haddr[31:24] == c5brbs[31:24]);
wire c5bren_l = ((haddr[23:20]|c5brmsk[3:0]) == (c5brbs[23:20]|c5brmsk[3:0]));
assign hsel_br[5] = c5bren_h&c5bren_l;
`endif
`ifdef DMA_HAVE_CH6
wire c6bren_h = (haddr[31:24] == c6brbs[31:24]);
wire c6bren_l = ((haddr[23:20]|c6brmsk[3:0]) == (c6brbs[23:20]|c6brmsk[3:0]));
assign hsel_br[6] = c6bren_h&c6bren_l;
`endif
`ifdef DMA_HAVE_CH7
wire c7bren_h = (haddr[31:24] == c7brbs[31:24]);
wire c7bren_l = ((haddr[23:20]|c7brmsk[3:0]) == (c7brbs[23:20]|c7brmsk[3:0]));
assign hsel_br[7] = c7bren_h&c7bren_l;
`endif
endmodule
`endif
`endif
|
`include "DMA_DEFINE.vh"
module dma_ahbmst
(
HCLK,
HRSTn,
arb_chcsr,
`ifdef DMA_HAVE_LINKLIST
arb_chllp,
`endif
arb_chsad,
arb_chdad,
arb_chabt,
`ifdef DMA_HAVE_AHB1
`ifdef DMA_HAVE_BRIDGE
slv_br_req,
slv_br_ad,
slv_br_dt,
slv_br_wr,
slv_br_sz,
slv_br_pt,
br_req_qf,
`endif
`endif
ff_dto,
bst_eq0,bst_eq1, bst_eq2,
tsz_eq0,tsz_eq1, tsz_eq2,
de_st,
de_err_notify,
de_err_st,
`ifdef DMA_HAVE_LINKLIST
de_mllp,
`endif
pack_en,
pack_end,
unpack_en,
upk_cnteq0,
upk_cnteq1,
ff_eq1,ff_eq2,ff_1ltfl,ff_2ltfl,ff_geth,
ff_empty, ff_q_full,
`ifdef DMA_HAVE_LINKLIST
st_llp0t3,
`endif
dst_m,src_m,
dst_a,src_a,
dst_e,src_e,
dst_wid_wd, src_wid_wd,
dst_wid_hw, src_wid_hw,
dst_wid_bt, src_wid_bt,
mx_is_dst, mx_is_src,
`ifdef DMA_HAVE_LINKLIST
mx_is_llp,
`endif
mx_arb_src, mx_arb_dst,
m1_src2br,
m0_m1_same,
`ifdef DMA_HAVE_BRIDGE
mx_arb_br,
`endif
fwdtsb0, fwdtsb1, fwdtsb2, fwdtsb3,
m0endian,
m1endian,
mx_ad1t0x,
mx_updad,
mx_rdto,
mx_cp,
mx_tr_sq,
mx_rp_err,
mx_rp_rty,
mx_dt_st,
mx_dtp,
mx_dma_had_a_rty,
mx_dma_err_ok,
hrdatai,
hreadyini,
hrespi,
haddro,
htranso,
hwriteo,
hsizeo,
hproto,
hbursto,
hwdatao,
hgranti,
hreqo
);
input HCLK;
input HRSTn;
input [`DMA_CHCSR_WIDTH-1:0] arb_chcsr;
`ifdef DMA_HAVE_LINKLIST
input [`DMA_HADDR_WIDTH-1:0] arb_chllp;
`endif
input [`DMA_HADDR_WIDTH-1:0] arb_chsad;
input [`DMA_HADDR_WIDTH-1:0] arb_chdad;
input arb_chabt;
`ifdef DMA_HAVE_AHB1
`ifdef DMA_HAVE_BRIDGE
input slv_br_req;
input [`DMA_HADDR_WIDTH-1:0] slv_br_ad;
input [`DMA_HDATA_WIDTH-1:0] slv_br_dt;
input slv_br_wr;
input [`DMA_HSIZE_WIDTH-1:0] slv_br_sz;
input [`DMA_HPROT_WIDTH-1:0] slv_br_pt;
input br_req_qf;
`endif
`endif
input [`DMA_HDATA_WIDTH-1:0] ff_dto;
input bst_eq0,bst_eq1, bst_eq2;
input tsz_eq0,tsz_eq1, tsz_eq2;
input [10:0] de_st;
input de_err_notify;
input de_err_st;
`ifdef DMA_HAVE_LINKLIST
input [`DMA_HADDR_WIDTH-1:2] de_mllp;
`endif
input pack_en;
input pack_end;
input unpack_en;
input upk_cnteq1;
input upk_cnteq0;
input ff_eq1,ff_eq2,ff_1ltfl,ff_2ltfl,ff_geth;
input ff_empty,ff_q_full;
`ifdef DMA_HAVE_LINKLIST
input st_llp0t3;
`endif
input dst_m,src_m;
input dst_a,src_a;
input dst_e,src_e;
input dst_wid_wd, src_wid_wd;
input dst_wid_hw, src_wid_hw;
input dst_wid_bt, src_wid_bt;
input mx_is_dst, mx_is_src;
`ifdef DMA_HAVE_LINKLIST
input mx_is_llp;
`endif
input mx_arb_src, mx_arb_dst;
input m1_src2br;
input m0_m1_same;
`ifdef DMA_HAVE_BRIDGE
input mx_arb_br;
`endif
input [1:0] fwdtsb0,fwdtsb1,fwdtsb2,fwdtsb3;
input m0endian;
input m1endian;
output [1:0] mx_ad1t0x;
output [`DMA_HADDR_WIDTH-1:0] mx_updad;
output [`DMA_HDATA_WIDTH-1:0] mx_rdto;
output mx_cp;
output mx_tr_sq;
output mx_rp_err;
output mx_rp_rty;
output mx_dt_st;
output mx_dtp;
output mx_dma_had_a_rty;
output mx_dma_err_ok;
input [`DMA_HDATA_WIDTH-1:0] hrdatai;
input hreadyini;
input [`DMA_HRESP_WIDTH-1:0] hrespi;
output [`DMA_HADDR_WIDTH-1:0] haddro;
output [`DMA_HTRANS_WIDTH-1:0] htranso;
output hwriteo;
output [`DMA_HSIZE_WIDTH-1:0] hsizeo;
output [`DMA_HPROT_WIDTH-1:0] hproto;
output [`DMA_HBURST_WIDTH-1:0] hbursto;
output [`DMA_HDATA_WIDTH-1:0] hwdatao;
input hgranti;
output hreqo;
parameter THIS_IS_M1 = 1;
parameter MX_ST_IDLE = `DMA_HTRANS_IDLE,
MX_ST_NS = `DMA_HTRANS_NONSEQ,
MX_ST_SQ = `DMA_HTRANS_SEQ;
parameter MX_DT_IDLE = 3'b001,
MX_DT_DT = 3'b010,
MX_DT_LT = 3'b100;
reg mx_dt_st;
reg m0_m1_diff_tx;
reg [`DMA_HTRANS_WIDTH-1:0] mx_cmd_st, mx_cmd_ns;
wire st_idle,st_rd,st_lr,st_rd_end,st_lw,st_update;
`ifdef DMA_HAVE_LINKLIST
wire st_llp0,st_llp1,st_llp2,st_llp3,st_llp4;
`else
wire mx_is_llp = 1'b0;
wire st_llp0t3 = 1'b0;
`endif
wire mx_tr_idle,mx_tr_ns,mx_tr_sq;
wire mx_rp_err,mx_rp_rty;
wire src_is_sgl,dst_is_sgl;
wire mx_idle2ns;
wire mx_ns2idle, mx_ns2sq;
wire mx_sq2idle;
wire rd2wr, wr2rd;
wire sel_dst_wid;
wire sel_src_wid;
wire sel_br_sz;
wire [`DMA_HPROT_WIDTH-1:0] mux_prot;
wire [`DMA_HBURST_WIDTH-1:0] mux_bst;
wire [`DMA_HDATA_WIDTH-1:0] mux_wdt;
wire ad_sel_inc, ad_sel_br;
wire ad_sel_llp;
wire ad_sel_dst;
wire ad_sel_src;
`ifdef DMA_HAVE_BRIDGE
`else
wire br_req_qf = 1'b0;
wire mx_arb_br = 0;
`endif
wire sel_adm4, sel_adm2, sel_adm1, sel_adeq;
wire sel_ada1, sel_ada2, sel_ada4;
wire [`DMA_HADDR_WIDTH-1:0] ad_inc;
wire mx_rdy;
wire cx_1k;
wire hbsel_sgl;
wire mx_cmd;
wire req_bgn, req_end;
wire src_e_dst;
`ifdef DMA_HAVE_AHB1
`ifdef DMA_HAVE_BRIDGE
wire br_req_raw;
`endif
`endif
wire [`DMA_HDATA_WIDTH-1:0] mx_rdto;
wire [`DMA_HTRANS_WIDTH-1:0] htranso;
wire [`DMA_HSIZE_WIDTH-1:0] hsizeq;
reg [`DMA_HSIZE_WIDTH-1:0] hsizep;
reg [`DMA_HSIZE_WIDTH-1:0] hsizeo;
reg hwriteo;
reg [`DMA_HBURST_WIDTH-1:0] hbursto;
reg [`DMA_HPROT_WIDTH-1:0] hproto;
reg [`DMA_HADDR_WIDTH-1:0] haddro;
reg [`DMA_HDATA_WIDTH-1:0] hwdatao;
reg [`DMA_HADDR_WIDTH-1:0] mux_ad;
reg hreqo;
reg mx_dtp;
reg [1:0] mx_ad1t0x;
assign st_idle = de_st[0];
assign st_rd = de_st[1];
assign st_lr = de_st[2];
assign st_rd_end = de_st[3];
assign st_lw = de_st[4];
assign st_update = de_st[5];
`ifdef DMA_HAVE_LINKLIST
assign st_llp0 = de_st[6];
assign st_llp1 = de_st[7];
assign st_llp2 = de_st[8];
assign st_llp3 = de_st[9];
assign st_llp4 = de_st[10];
`endif
assign mx_tr_idle = (htranso==`DMA_HTRANS_IDLE);
assign mx_tr_ns = (htranso==`DMA_HTRANS_NONSEQ);
assign mx_tr_sq = (htranso==`DMA_HTRANS_SEQ);
assign mx_cp = htranso[1];
assign mx_rp_err = (hrespi==`DMA_HRESP_ERROR);
assign mx_rp_rty = hrespi[1];
assign src_is_sgl = (src_m|src_e);
assign dst_is_sgl = (dst_m|dst_e);
assign cx_1k = (&haddro[9:2] &
(hsizeo[1]|
(~hsizeo[1]&hsizeo[0]&haddro[1])|
(~hsizeo[1]&~hsizeo[0]&haddro[1]&haddro[0])));
wire cmd_bgn = !mx_dma_err_ok&!(m1_src2br&THIS_IS_M1)&
((ad_sel_dst&~ff_empty) |
(ad_sel_src&~tsz_eq0&~bst_eq0&~ff_q_full)
`ifdef DMA_HAVE_LINKLIST
| (mx_is_llp & st_llp0t3)
`endif
)
`ifdef DMA_HAVE_AHB1
`ifdef DMA_HAVE_BRIDGE
| (THIS_IS_M1&br_req_qf&mx_arb_br)
`endif
`endif
;
assign mx_idle2ns = ~st_update & ~mx_dtp& cmd_bgn & hgranti & ~mx_cp &
~de_err_st & mx_rdy;
wire ns_end = ((mx_arb_dst&mx_is_dst&
((ff_eq1&upk_cnteq0)|dst_is_sgl)) |
(mx_arb_src&mx_is_src&
((bst_eq2|tsz_eq2|ff_1ltfl)|src_is_sgl)) |
`ifdef DMA_HAVE_AHB1
`ifdef DMA_HAVE_BRIDGE
THIS_IS_M1 & slv_br_req |
`endif
`endif
`ifdef DMA_HAVE_LINKLIST
mx_is_llp & st_llp3 |
`endif
cx_1k |
~hgranti);
assign mx_ns2idle = ns_end |
mx_rp_rty |
mx_rp_err |
de_err_notify |
de_err_st;
assign mx_ns2sq = ~ns_end;
wire sq_end = (mx_is_dst & mx_arb_dst &
((ff_eq2 & ~unpack_en)|(ff_eq1 & upk_cnteq1))) |
(mx_is_src & mx_arb_src &
((bst_eq2|tsz_eq2) |
(ff_2ltfl & ~pack_en)|
(ff_1ltfl & (pack_end|mx_rdy) ))) |
`ifdef DMA_HAVE_AHB1
`ifdef DMA_HAVE_BRIDGE
THIS_IS_M1 & slv_br_req |
`endif
`endif
`ifdef DMA_HAVE_LINKLIST
(mx_is_llp & st_llp2) |
`endif
cx_1k |
~hgranti;
assign mx_sq2idle = sq_end |
mx_rp_rty |
mx_rp_err |
de_err_notify |
de_err_st;
always @(mx_cmd_st or mx_idle2ns or mx_ns2idle or mx_ns2sq or
mx_sq2idle )
case(mx_cmd_st)
MX_ST_IDLE: if(mx_idle2ns)
mx_cmd_ns = MX_ST_NS;
else
mx_cmd_ns = MX_ST_IDLE;
MX_ST_NS: if(mx_ns2idle)
mx_cmd_ns = MX_ST_IDLE;
else if(mx_ns2sq)
mx_cmd_ns = MX_ST_SQ;
else
mx_cmd_ns = MX_ST_NS;
MX_ST_SQ: if(mx_sq2idle)
mx_cmd_ns = MX_ST_IDLE;
else
mx_cmd_ns = MX_ST_SQ;
default: mx_cmd_ns = mx_cmd_st;
endcase
always @(posedge HCLK or negedge HRSTn)
if(~HRSTn)
mx_cmd_st <= MX_ST_IDLE;
else
mx_cmd_st <= mx_cmd_ns;
assign htranso = mx_cmd_st;
always @(posedge HCLK or negedge HRSTn)
if(~HRSTn)
mx_dtp <= 1'b0;
else if(mx_rdy)
mx_dtp <= htranso[1];
wire dt_stwe = hreadyini&(hrespi[1]|hrespi[0]);
wire dt_stin = htranso[1]&~(hrespi[1]|hrespi[0]);
always @(posedge HCLK or negedge HRSTn)
if(~HRSTn)
mx_dt_st <= 1'b0;
else
mx_dt_st <= dt_stin & dt_stwe;
assign rd2wr = (!(THIS_IS_M1&mx_arb_br) & mx_is_dst &
((~mx_is_src&m0_m1_diff_tx) |
st_rd_end))
`ifdef DMA_HAVE_AHB1
`ifdef DMA_HAVE_BRIDGE
| (THIS_IS_M1 &
mx_arb_br & slv_br_wr)
`endif
`endif
;
assign wr2rd = (!(THIS_IS_M1&mx_arb_br) & mx_is_src &
st_rd)
`ifdef DMA_HAVE_LINKLIST
| (!(THIS_IS_M1&mx_arb_br) & mx_is_llp &
st_llp0t3)
`endif
`ifdef DMA_HAVE_AHB1
`ifdef DMA_HAVE_BRIDGE
| (THIS_IS_M1 &
mx_arb_br & ~slv_br_wr)
`endif
`endif
;
always @(posedge HCLK or negedge HRSTn)
if(~HRSTn)
hwriteo <= `DMA_DRW_READ;
else if(rd2wr&mx_rdy)
hwriteo <= `DMA_DRW_WRITE;
else if(wr2rd&mx_rdy)
hwriteo <= `DMA_DRW_READ;
assign sel_dst_wid = ad_sel_dst & mx_is_dst;
assign sel_src_wid = ad_sel_src & mx_is_src;
assign sel_br_sz = THIS_IS_M1 & mx_arb_br;
`ifdef DMA_HAVE_AHB1
`ifdef DMA_HAVE_BRIDGE
`else
wire [`DMA_HSIZE_WIDTH-1:0] slv_br_sz = 0;
`endif
`else
wire [`DMA_HSIZE_WIDTH-1:0] slv_br_sz = 0;
`endif
always @(sel_dst_wid or sel_src_wid or mx_is_llp or
arb_chcsr or hsizeo)
case({sel_dst_wid, sel_src_wid, mx_is_llp})
3'b001: hsizep = `DMA_HSIZE_WORD;
3'b010: hsizep = arb_chcsr[`DMA_CHCSR_SWID];
3'b100: hsizep = arb_chcsr[`DMA_CHCSR_DWID];
default: hsizep = hsizeo;
endcase
`ifdef DMA_HAVE_BRIDGE
assign hsizeq = (sel_br_sz) ? slv_br_sz : hsizep;
`else
assign hsizeq = hsizep;
`endif
always @(posedge HCLK or negedge HRSTn)
if(~HRSTn)
hsizeo <= `DMA_HSIZE_WORD;
else if(mx_idle2ns)
hsizeo <= hsizeq;
`ifdef DMA_HAVE_AHB1
`ifdef DMA_HAVE_BRIDGE
assign mux_prot = (THIS_IS_M1&mx_arb_br)? slv_br_pt :
{arb_chcsr[`DMA_CHCSR_PR3],
arb_chcsr[`DMA_CHCSR_PR2],
arb_chcsr[`DMA_CHCSR_PR1],
1'b0};
`else
assign mux_prot = {arb_chcsr[`DMA_CHCSR_PR3],
arb_chcsr[`DMA_CHCSR_PR2],
arb_chcsr[`DMA_CHCSR_PR1],
1'b0};
`endif
`else
assign mux_prot = {arb_chcsr[`DMA_CHCSR_PR3],
arb_chcsr[`DMA_CHCSR_PR2],
arb_chcsr[`DMA_CHCSR_PR1],
1'b0};
`endif
always @(posedge HCLK or negedge HRSTn)
if(~HRSTn)
hproto <= 4'b0;
else if(mx_rdy)
hproto <= mux_prot;
assign hbsel_sgl = ~st_llp0t3&((mx_arb_src&src_is_sgl) |
(mx_arb_dst&dst_is_sgl))
`ifdef DMA_HAVE_AHB1
`ifdef DMA_HAVE_BRIDGE
| (THIS_IS_M1&mx_arb_br)
`endif
`endif
;
assign mux_bst = hbsel_sgl ? `DMA_HBURST_SINGLE : `DMA_HBURST_INCR;
always @(posedge HCLK or negedge HRSTn)
if(~HRSTn)
hbursto <= `DMA_HBURST_INCR;
else if(mx_idle2ns)
hbursto <= mux_bst;
reg [7:0] fxdtb0,fxdtb1,fxdtb2,fxdtb3;
wire mxendian = (THIS_IS_M1&m1endian)|(~THIS_IS_M1&m0endian);
wire hsizeo_hw = (hsizeo==3'h1);
wire hsizeo_bt = (hsizeo==3'h0);
wire tro_hw = mxendian&hsizeo_hw;
wire tro_bt = mxendian&hsizeo_bt;
always @(fwdtsb0 or ff_dto)
case(fwdtsb0)
2'b00: fxdtb0 = ff_dto[7:0];
2'b01: fxdtb0 = ff_dto[15:8];
2'b10: fxdtb0 = ff_dto[23:16];
2'b11: fxdtb0 = ff_dto[31:24];
endcase
always @(fwdtsb1 or ff_dto)
case(fwdtsb1)
2'b00: fxdtb1 = ff_dto[7:0];
2'b01: fxdtb1 = ff_dto[15:8];
2'b10: fxdtb1 = ff_dto[23:16];
2'b11: fxdtb1 = ff_dto[31:24];
endcase
always @(fwdtsb2 or ff_dto)
case(fwdtsb2)
2'b00: fxdtb2 = ff_dto[7:0];
2'b01: fxdtb2 = ff_dto[15:8];
2'b10: fxdtb2 = ff_dto[23:16];
2'b11: fxdtb2 = ff_dto[31:24];
endcase
always @(fwdtsb3 or ff_dto)
case(fwdtsb3)
2'b00: fxdtb3 = ff_dto[7:0];
2'b01: fxdtb3 = ff_dto[15:8];
2'b10: fxdtb3 = ff_dto[23:16];
2'b11: fxdtb3 = ff_dto[31:24];
endcase
`ifdef DMA_HAVE_AHB1
`ifdef DMA_HAVE_BRIDGE
assign mux_wdt = (mx_arb_dst? {fxdtb3,fxdtb2,fxdtb1,fxdtb0} : slv_br_dt);
`else
assign mux_wdt = {fxdtb3,fxdtb2,fxdtb1,fxdtb0};
`endif
`else
assign mux_wdt = {fxdtb3,fxdtb2,fxdtb1,fxdtb0};
`endif
assign mx_cmd = mx_cp&mx_rdy;
always @(posedge HCLK or negedge HRSTn)
if(~HRSTn)
hwdatao <= 'h0;
else if(mx_cmd)
hwdatao <= mux_wdt;
assign ad_sel_inc = mx_cp&!ad_sel_br;
`ifdef DMA_HAVE_BRIDGE
assign ad_sel_br = (THIS_IS_M1&mx_arb_br);
`else
assign ad_sel_br = 1'b0;
`endif
`ifdef DMA_HAVE_LINKLIST
assign ad_sel_llp = (mx_is_llp&st_llp0t3);
`else
assign ad_sel_llp = 0;
`endif
always@(posedge HCLK or negedge HRSTn)
if(~HRSTn)
m0_m1_diff_tx <= 0;
else if(st_update)
m0_m1_diff_tx <= 0;
else if(!m0_m1_same&st_rd&(ff_geth|(tsz_eq0|bst_eq0)))
m0_m1_diff_tx <= 1;
assign ad_sel_dst = mx_is_dst&(m0_m1_diff_tx|st_rd_end|st_lw);
assign ad_sel_src = mx_is_src&((!m0_m1_same&st_rd)|(st_rd|st_lr));
/* Daniel Modified 7/31/2003
assign ad_sel_dst = mx_is_dst&((~mx_is_src&ff_geth)|
st_rd_end|st_lw);
assign ad_sel_src = mx_is_src&(st_rd|st_lr);
*/
wire [31:0] arb_chsad_masked = {arb_chsad[31:2],arb_chsad[1]&~hsizep[1],arb_chsad[0]&~(hsizep[0]|hsizep[1])};
wire [31:0] arb_chdad_masked = {arb_chdad[31:2],arb_chdad[1]&~hsizep[1],arb_chdad[0]&~(hsizep[0]|hsizep[1])};
always @(ad_sel_inc
`ifdef DMA_HAVE_LINKLIST
or ad_sel_llp
`endif
or ad_sel_dst
or ad_sel_src or ad_inc
`ifdef DMA_HAVE_LINKLIST
or de_mllp
`endif
or arb_chdad_masked or arb_chsad_masked or haddro
or ad_sel_br
`ifdef DMA_HAVE_AHB1
`ifdef DMA_HAVE_BRIDGE
or slv_br_ad
`endif
`endif
)
casex({ad_sel_inc,ad_sel_br,ad_sel_llp,ad_sel_dst,ad_sel_src})
5'b1xxxx: mux_ad = ad_inc;
`ifdef DMA_HAVE_AHB1
`ifdef DMA_HAVE_BRIDGE
5'b01xxx: mux_ad = slv_br_ad;
`endif
`endif
`ifdef DMA_HAVE_LINKLIST
5'b001xx: mux_ad = {de_mllp,2'b0};
`endif
5'b0001x: mux_ad = arb_chdad_masked;
5'b00001: mux_ad = arb_chsad_masked;
default: mux_ad = haddro;
endcase
always @(posedge HCLK or negedge HRSTn)
if(~HRSTn)
haddro <= 32'b0;
else if(mx_idle2ns & mx_cmd)
haddro <= mux_ad;
assign sel_adm4 = (mx_arb_dst & dst_m & dst_wid_wd) |
(mx_arb_src & src_m & src_wid_wd);
assign sel_adm2 = (mx_arb_dst & dst_m & dst_wid_hw) |
(mx_arb_src & src_m & src_wid_hw);
assign sel_adm1 = (mx_arb_dst & dst_m & dst_wid_bt) |
(mx_arb_src & src_m & src_wid_bt);
assign sel_adeq = (mx_arb_dst & dst_e) |
(mx_arb_src & src_e);
assign sel_ada1 = (mx_arb_dst & dst_a & dst_wid_bt) |
(mx_arb_src & src_a & src_wid_bt);
assign sel_ada2 = (mx_arb_dst & dst_a & dst_wid_hw) |
(mx_arb_src & src_a & src_wid_hw);
assign sel_ada4 = (mx_arb_dst & dst_a & dst_wid_wd) |
(mx_arb_src & src_a & src_wid_wd)
`ifdef DMA_HAVE_LINKLIST
| st_llp0t3
`endif
;
reg [2:0] inc_sel, inc_selx;
always @(sel_adeq or sel_ada1 or sel_ada2 or sel_ada4 or
sel_adm1 or sel_adm2 or sel_adm4)
case({sel_adeq,sel_ada1,sel_ada2,sel_ada4,
sel_adm1,sel_adm2,sel_adm4})
7'b100_0000: inc_sel = 0;
7'b010_0000: inc_sel = 1;
7'b001_0000: inc_sel = 2;
7'b000_1000: inc_sel = 3;
7'b000_0100: inc_sel = 4;
7'b000_0010: inc_sel = 5;
7'b000_0001: inc_sel = 6;
default: inc_sel = 0;
endcase
`ifdef DMA_HAVE_LINKLIST
wire [2:0] inc_sel1 = st_llp0t3 ? 3 : inc_sel;
`else
wire [2:0] inc_sel1 = inc_sel;
`endif
always @(posedge HCLK)
inc_selx <= inc_sel1;
parameter ADD_CENTER = 16;
wire [ADD_CENTER:0] ad_add_lo;
wire [31:ADD_CENTER] add_hia1;
wire [31:ADD_CENTER] add_him1;
wire [31:ADD_CENTER] add_hi;
wire ad_add_cf;
reg [ADD_CENTER:0] ad_addin2;
reg add_cfx;
reg adin_is_neg;
always @(inc_selx)
case(inc_selx)
0: ad_addin2 = 0;
1: ad_addin2 = 1;
2: ad_addin2 = 2;
3: ad_addin2 = 4;
4: ad_addin2 = -1;
5: ad_addin2 = -2;
6: ad_addin2 = -4;
default: ad_addin2 = 0;
endcase
assign ad_add_lo = {1'b0, haddro[ADD_CENTER-1:0]} +
ad_addin2;
assign ad_add_cf = ad_add_lo[ADD_CENTER];
assign ad_inc = {haddro[31:ADD_CENTER], ad_add_lo[ADD_CENTER-1:0]};
always @(posedge HCLK or negedge HRSTn)
if(~HRSTn)
add_cfx <= 'h0;
else
add_cfx <= ad_add_cf & mx_cmd;
always @(posedge HCLK or negedge HRSTn)
if(~HRSTn)
adin_is_neg <= 'h0;
else if(mx_cmd)
adin_is_neg <= ad_addin2[ADD_CENTER];
assign add_hia1 = haddro[31:ADD_CENTER]+1;
assign add_him1 = haddro[31:ADD_CENTER]-1;
assign add_hi = add_cfx ? (adin_is_neg? add_hia1 : add_him1) :
haddro[31:ADD_CENTER];
assign mx_updad = {add_hi,haddro[ADD_CENTER-1:0]};
always @(posedge HCLK or negedge HRSTn)
if(~HRSTn)
mx_ad1t0x <= 'h0;
else if(mx_cmd)
mx_ad1t0x <= haddro[1:0];
wire [7:0] mx_rdtb0 = (tro_hw)? hrdatai[23:16] :
(tro_bt)? hrdatai[31:24] : hrdatai[7:0];
wire [7:0] mx_rdtb1 = (tro_hw)? hrdatai[31:24] :
(tro_bt)? hrdatai[23:16] : hrdatai[15:8];
wire [7:0] mx_rdtb2 = (tro_hw)? hrdatai[7:0] :
(tro_bt)? hrdatai[15:8] : hrdatai[23:16];
wire [7:0] mx_rdtb3 = (tro_hw)? hrdatai[15:8] :
(tro_bt)? hrdatai[7:0] : hrdatai[31:24];
assign mx_rdto = {mx_rdtb3,mx_rdtb2,mx_rdtb1,mx_rdtb0};
assign mx_rdy = hreadyini;
assign req_bgn = cmd_bgn;
assign src_e_dst = mx_is_src & mx_is_dst;
`ifdef DMA_HAVE_AHB1
`ifdef DMA_HAVE_BRIDGE
assign br_req_raw = (slv_br_req&(st_idle|st_update)&htranso[1]);
`endif
`endif
assign req_end =
`ifdef DMA_HAVE_AHB1
`ifdef DMA_HAVE_BRIDGE
(br_req_raw) |
`endif
`endif
st_update |
(mx_is_src&~mx_is_dst&(bst_eq0|tsz_eq0)&
(st_rd|st_rd_end|st_lw)) |
(mx_is_dst&~mx_is_src&st_update);
always @(posedge HCLK or negedge HRSTn)
if(~HRSTn)
hreqo <= 1'b0;
else if(~hreqo&req_bgn)
hreqo <= 1'b1;
else if(hreqo&req_end)
hreqo <= 1'b0;
reg mx_dma_had_a_rty;
reg de_err_notify_d;
always @(posedge HCLK or negedge HRSTn)
if(~HRSTn)
de_err_notify_d <= 0;
else if(st_update)
de_err_notify_d <= 0;
else if(mx_rdy)
de_err_notify_d <= de_err_notify;
always @(posedge HCLK or negedge HRSTn)
if(~HRSTn)
mx_dma_had_a_rty <= 1'b0;
else if(!(THIS_IS_M1&mx_arb_br)&mx_dt_st&mx_rp_rty)
mx_dma_had_a_rty <= 1'b1;
else if(!(THIS_IS_M1&mx_arb_br)&(mx_dt_st&mx_rdy|mx_rp_err))
mx_dma_had_a_rty <= 1'b0;
wire mx_dma_err1 = de_err_notify&!mx_dma_had_a_rty&!(mx_cp|mx_dtp);
/*
reg mx_dma_err1;
wire mx_err_no_rty = de_err_notify &!mx_arb_br&mx_cp&!(mx_rp_rty|mx_dma_had_a_rty) |
de_err_notify_d&!mx_arb_br&!(mx_rp_rty|mx_dma_had_a_rty);
wire mx_err_rty_ok = de_err_notify &mx_dma_had_a_rty&!mx_arb_br&mx_dt_st&mx_rdy;
wire mx_dma_err1_cl = st_update;
always @(posedge HCLK or negedge HRSTn)
if(~HRSTn)
mx_dma_err1 <= 0;
else if(mx_dma_err1_cl)
mx_dma_err1 <= 0;
else if(mx_err_no_rty | mx_err_rty_ok)
mx_dma_err1 <= 1;
*/
/*
always @(posedge HCLK or negedge HRSTn)
if(~HRSTn)
mx_dma_err_occur <= 1'b0;
else if(!mx_dma_err_occur&mx_dt_st&!(THIS_IS_M1&mx_arb_br)&mx_rp_err)
mx_dma_err_occur <= 1'b1;
else if(mx_dma_err_occur&st_update)
mx_dma_err_occur <= 1'b0;
assign mx_dma_err_ok = mx_dma_err_occur | mx_dma_err1;
*/
assign mx_dma_err_ok = mx_dma_err1;
endmodule
|
`include "DMA_DEFINE.vh"
`ifdef DMA_HAVE_AHB1
`ifdef DMA_HAVE_BRIDGE
module dma_ahbmux
(
HCLK,
HRSTn,
htrans,
hsel_dma,
hsel_br,
hrdt0_dma,
hrp0_dma,
hrdy0_dma,
`ifdef DMA_HAVE_CH1
hrdt1_dma,
hrp1_dma,
hrdy1_dma,
`endif
`ifdef DMA_HAVE_CH2
hrdt2_dma,
hrp2_dma,
hrdy2_dma,
`endif
`ifdef DMA_HAVE_CH3
hrdt3_dma,
hrp3_dma,
hrdy3_dma,
`endif
`ifdef DMA_HAVE_CH4
hrdt4_dma,
hrp4_dma,
hrdy4_dma,
`endif
`ifdef DMA_HAVE_CH5
hrdt5_dma,
hrp5_dma,
hrdy5_dma,
`endif
`ifdef DMA_HAVE_CH6
hrdt6_dma,
hrp6_dma,
hrdy6_dma,
`endif
`ifdef DMA_HAVE_CH7
hrdt7_dma,
hrp7_dma,
hrdy7_dma,
`endif
hrdt0_br,
hrp0_br,
hrdy0_br,
`ifdef DMA_HAVE_CH1
hrdt1_br,
hrp1_br,
hrdy1_br,
`endif
`ifdef DMA_HAVE_CH2
hrdt2_br,
hrp2_br,
hrdy2_br,
`endif
`ifdef DMA_HAVE_CH3
hrdt3_br,
hrp3_br,
hrdy3_br,
`endif
`ifdef DMA_HAVE_CH4
hrdt4_br,
hrp4_br,
hrdy4_br,
`endif
`ifdef DMA_HAVE_CH5
hrdt5_br,
hrp5_br,
hrdy5_br,
`endif
`ifdef DMA_HAVE_CH6
hrdt6_br,
hrp6_br,
hrdy6_br,
`endif
`ifdef DMA_HAVE_CH7
hrdt7_br,
hrp7_br,
hrdy7_br,
`endif
hrdata,
hresp,
hreadyin
);
input HCLK;
input HRSTn;
input [`DMA_HTRANS_WIDTH-1:0] htrans;
input [`DMA_MAX_CHNO-1:0] hsel_dma;
input [`DMA_MAX_CHNO-1:0] hsel_br;
input [`DMA_HDATA_WIDTH-1:0] hrdt0_dma;
input [`DMA_HRESP_WIDTH-1:0] hrp0_dma;
input hrdy0_dma;
`ifdef DMA_HAVE_CH1
input [`DMA_HDATA_WIDTH-1:0] hrdt1_dma;
input [`DMA_HRESP_WIDTH-1:0] hrp1_dma;
input hrdy1_dma;
`endif
`ifdef DMA_HAVE_CH2
input [`DMA_HDATA_WIDTH-1:0] hrdt2_dma;
input [`DMA_HRESP_WIDTH-1:0] hrp2_dma;
input hrdy2_dma;
`endif
`ifdef DMA_HAVE_CH3
input [`DMA_HDATA_WIDTH-1:0] hrdt3_dma;
input [`DMA_HRESP_WIDTH-1:0] hrp3_dma;
input hrdy3_dma;
`endif
`ifdef DMA_HAVE_CH4
input [`DMA_HDATA_WIDTH-1:0] hrdt4_dma;
input [`DMA_HRESP_WIDTH-1:0] hrp4_dma;
input hrdy4_dma;
`endif
`ifdef DMA_HAVE_CH5
input [`DMA_HDATA_WIDTH-1:0] hrdt5_dma;
input [`DMA_HRESP_WIDTH-1:0] hrp5_dma;
input hrdy5_dma;
`endif
`ifdef DMA_HAVE_CH6
input [`DMA_HDATA_WIDTH-1:0] hrdt6_dma;
input [`DMA_HRESP_WIDTH-1:0] hrp6_dma;
input hrdy6_dma;
`endif
`ifdef DMA_HAVE_CH7
input [`DMA_HDATA_WIDTH-1:0] hrdt7_dma;
input [`DMA_HRESP_WIDTH-1:0] hrp7_dma;
input hrdy7_dma;
`endif
input [`DMA_HDATA_WIDTH-1:0] hrdt0_br;
input [`DMA_HRESP_WIDTH-1:0] hrp0_br;
input hrdy0_br;
`ifdef DMA_HAVE_CH1
input [`DMA_HDATA_WIDTH-1:0] hrdt1_br;
input [`DMA_HRESP_WIDTH-1:0] hrp1_br;
input hrdy1_br;
`endif
`ifdef DMA_HAVE_CH2
input [`DMA_HDATA_WIDTH-1:0] hrdt2_br;
input [`DMA_HRESP_WIDTH-1:0] hrp2_br;
input hrdy2_br;
`endif
`ifdef DMA_HAVE_CH3
input [`DMA_HDATA_WIDTH-1:0] hrdt3_br;
input [`DMA_HRESP_WIDTH-1:0] hrp3_br;
input hrdy3_br;
`endif
`ifdef DMA_HAVE_CH4
input [`DMA_HDATA_WIDTH-1:0] hrdt4_br;
input [`DMA_HRESP_WIDTH-1:0] hrp4_br;
input hrdy4_br;
`endif
`ifdef DMA_HAVE_CH5
input [`DMA_HDATA_WIDTH-1:0] hrdt5_br;
input [`DMA_HRESP_WIDTH-1:0] hrp5_br;
input hrdy5_br;
`endif
`ifdef DMA_HAVE_CH6
input [`DMA_HDATA_WIDTH-1:0] hrdt6_br;
input [`DMA_HRESP_WIDTH-1:0] hrp6_br;
input hrdy6_br;
`endif
`ifdef DMA_HAVE_CH7
input [`DMA_HDATA_WIDTH-1:0] hrdt7_br;
input [`DMA_HRESP_WIDTH-1:0] hrp7_br;
input hrdy7_br;
`endif
output [`DMA_HDATA_WIDTH-1:0] hrdata;
output [`DMA_HRESP_WIDTH-1:0] hresp;
output hreadyin;
wire htr_idle;
wire mux_sel_dma;
wire [`DMA_M1SNO_WIDTH-1:0] mux_noi;
wire mux_no_we;
reg [`DMA_M1SNO_WIDTH-2:0] muxd_noi, muxb_noi;
reg [`DMA_M1SNO_WIDTH-1:0] mux_no;
reg [`DMA_HDATA_WIDTH-1:0] hrdti;
reg [`DMA_HRESP_WIDTH-1:0] hrpi;
reg hrdyi;
assign htr_idle = (htrans == `DMA_HTRANS_IDLE);
always @(hsel_dma)
case(hsel_dma)
'b00000001: muxd_noi = 0;
`ifdef DMA_HAVE_CH1
'b00000010: muxd_noi = 1;
`endif
`ifdef DMA_HAVE_CH2
'b00000100: muxd_noi = 2;
`endif
`ifdef DMA_HAVE_CH3
'b00001000: muxd_noi = 3;
`endif
`ifdef DMA_HAVE_CH4
'b00010000: muxd_noi = 4;
`endif
`ifdef DMA_HAVE_CH5
'b00100000: muxd_noi = 5;
`endif
`ifdef DMA_HAVE_CH6
'b01000000: muxd_noi = 6;
`endif
`ifdef DMA_HAVE_CH7
'b10000000: muxd_noi = 7;
`endif
default: muxd_noi = 0;
endcase
always @(hsel_br)
case(hsel_br)
'b00000001: muxb_noi = 0;
`ifdef DMA_HAVE_CH1
'b00000010: muxb_noi = 1;
`endif
`ifdef DMA_HAVE_CH2
'b00000100: muxb_noi = 2;
`endif
`ifdef DMA_HAVE_CH3
'b00001000: muxb_noi = 3;
`endif
`ifdef DMA_HAVE_CH4
'b00010000: muxb_noi = 4;
`endif
`ifdef DMA_HAVE_CH5
'b00100000: muxb_noi = 5;
`endif
`ifdef DMA_HAVE_CH6
'b01000000: muxb_noi = 6;
`endif
`ifdef DMA_HAVE_CH7
'b10000000: muxb_noi = 7;
`endif
default: muxb_noi = 0;
endcase
assign mux_sel_dma = |hsel_dma;
assign mux_noi = mux_sel_dma? {1'b0,muxd_noi} : {1'b1,muxb_noi};
assign mux_no_we = ~htr_idle&hreadyin;
always @(posedge HCLK or negedge HRSTn)
if(~HRSTn)
mux_no <= 0;
else if(mux_no_we)
mux_no <= mux_noi;
reg hrmxnof;
wire hsel_df = ~((|hsel_dma) | (|hsel_br));
always @(posedge HCLK or negedge HRSTn)
if(~HRSTn)
hrmxnof <= 1'b1;
else if(hreadyin)
hrmxnof <= hsel_df;
wire df_cmd = ~htr_idle&hsel_df;
wire [`DMA_HRESP_WIDTH-1:0] hrp_dfi = df_cmd? `DMA_HRESP_ERROR : `DMA_HRESP_OK;
reg hrdy_df;
reg [`DMA_HRESP_WIDTH-1:0] hrp_df;
always @(posedge HCLK or negedge HRSTn)
if(~HRSTn)
hrdy_df <= 1'b1;
else if(hreadyin)
hrdy_df <= ~df_cmd;
else if(~hrdy_df)
hrdy_df <= 1'b1;
always @(posedge HCLK or negedge HRSTn)
if(~HRSTn)
hrp_df <= `DMA_HRESP_OK;
else if(hreadyin)
hrp_df <= hrp_dfi;
always @(mux_no or hrdt0_dma
`ifdef DMA_HAVE_CH1
or hrdt1_dma
`endif
`ifdef DMA_HAVE_CH2
or hrdt2_dma
`endif
`ifdef DMA_HAVE_CH3
or hrdt3_dma
`endif
`ifdef DMA_HAVE_CH4
or hrdt4_dma
`endif
`ifdef DMA_HAVE_CH5
or hrdt5_dma
`endif
`ifdef DMA_HAVE_CH6
or hrdt6_dma
`endif
`ifdef DMA_HAVE_CH7
or hrdt7_dma
`endif
or hrdt0_br
`ifdef DMA_HAVE_CH1
or hrdt1_br
`endif
`ifdef DMA_HAVE_CH2
or hrdt2_br
`endif
`ifdef DMA_HAVE_CH3
or hrdt3_br
`endif
`ifdef DMA_HAVE_CH4
or hrdt4_br
`endif
`ifdef DMA_HAVE_CH5
or hrdt5_br
`endif
`ifdef DMA_HAVE_CH6
or hrdt6_br
`endif
`ifdef DMA_HAVE_CH7
or hrdt7_br
`endif
)
case(mux_no)
'h0: hrdti = hrdt0_dma;
`ifdef DMA_HAVE_CH1
'h1: hrdti = hrdt1_dma;
`endif
`ifdef DMA_HAVE_CH2
'h2: hrdti = hrdt2_dma;
`endif
`ifdef DMA_HAVE_CH3
'h3: hrdti = hrdt3_dma;
`endif
`ifdef DMA_HAVE_CH4
'h4: hrdti = hrdt4_dma;
`endif
`ifdef DMA_HAVE_CH5
'h5: hrdti = hrdt5_dma;
`endif
`ifdef DMA_HAVE_CH6
'h6: hrdti = hrdt6_dma;
`endif
`ifdef DMA_HAVE_CH7
'h7: hrdti = hrdt7_dma;
`endif
'h8: hrdti = hrdt0_br;
`ifdef DMA_HAVE_CH1
'h9: hrdti = hrdt1_br;
`endif
`ifdef DMA_HAVE_CH2
'ha: hrdti = hrdt2_br;
`endif
`ifdef DMA_HAVE_CH3
'hb: hrdti = hrdt3_br;
`endif
`ifdef DMA_HAVE_CH4
'hc: hrdti = hrdt4_br;
`endif
`ifdef DMA_HAVE_CH5
'hd: hrdti = hrdt5_br;
`endif
`ifdef DMA_HAVE_CH6
'he: hrdti = hrdt6_br;
`endif
`ifdef DMA_HAVE_CH7
'hf: hrdti = hrdt7_br;
`endif
default: hrdti = hrdt0_dma;
endcase
assign hrdata = hrdti;
always @(mux_no or hrp0_dma
`ifdef DMA_HAVE_CH1
or hrp1_dma
`endif
`ifdef DMA_HAVE_CH2
or hrp2_dma
`endif
`ifdef DMA_HAVE_CH3
or hrp3_dma
`endif
`ifdef DMA_HAVE_CH4
or hrp4_dma
`endif
`ifdef DMA_HAVE_CH5
or hrp5_dma
`endif
`ifdef DMA_HAVE_CH6
or hrp6_dma
`endif
`ifdef DMA_HAVE_CH7
or hrp7_dma
`endif
or hrp0_br
`ifdef DMA_HAVE_CH1
or hrp1_br
`endif
`ifdef DMA_HAVE_CH2
or hrp2_br
`endif
`ifdef DMA_HAVE_CH3
or hrp3_br
`endif
`ifdef DMA_HAVE_CH4
or hrp4_br
`endif
`ifdef DMA_HAVE_CH5
or hrp5_br
`endif
`ifdef DMA_HAVE_CH6
or hrp6_br
`endif
`ifdef DMA_HAVE_CH7
or hrp7_br
`endif
)
case(mux_no)
'h0: hrpi = hrp0_dma;
`ifdef DMA_HAVE_CH1
'h1: hrpi = hrp1_dma;
`endif
`ifdef DMA_HAVE_CH2
'h2: hrpi = hrp2_dma;
`endif
`ifdef DMA_HAVE_CH3
'h3: hrpi = hrp3_dma;
`endif
`ifdef DMA_HAVE_CH4
'h4: hrpi = hrp4_dma;
`endif
`ifdef DMA_HAVE_CH5
'h5: hrpi = hrp5_dma;
`endif
`ifdef DMA_HAVE_CH6
'h6: hrpi = hrp6_dma;
`endif
`ifdef DMA_HAVE_CH7
'h7: hrpi = hrp7_dma;
`endif
'h8: hrpi = hrp0_br;
`ifdef DMA_HAVE_CH1
'h9: hrpi = hrp1_br;
`endif
`ifdef DMA_HAVE_CH2
'ha: hrpi = hrp2_br;
`endif
`ifdef DMA_HAVE_CH3
'hb: hrpi = hrp3_br;
`endif
`ifdef DMA_HAVE_CH4
'hc: hrpi = hrp4_br;
`endif
`ifdef DMA_HAVE_CH5
'hd: hrpi = hrp5_br;
`endif
`ifdef DMA_HAVE_CH6
'he: hrpi = hrp6_br;
`endif
`ifdef DMA_HAVE_CH7
'hf: hrpi = hrp7_br;
`endif
default: hrpi = hrp0_dma;
endcase
assign hresp = hrmxnof ? hrp_df : hrpi;
always @(mux_no or hrdy0_dma
`ifdef DMA_HAVE_CH1
or hrdy1_dma
`endif
`ifdef DMA_HAVE_CH2
or hrdy2_dma
`endif
`ifdef DMA_HAVE_CH3
or hrdy3_dma
`endif
`ifdef DMA_HAVE_CH4
or hrdy4_dma
`endif
`ifdef DMA_HAVE_CH5
or hrdy5_dma
`endif
`ifdef DMA_HAVE_CH6
or hrdy6_dma
`endif
`ifdef DMA_HAVE_CH7
or hrdy7_dma
`endif
or hrdy0_br
`ifdef DMA_HAVE_CH1
or hrdy1_br
`endif
`ifdef DMA_HAVE_CH2
or hrdy2_br
`endif
`ifdef DMA_HAVE_CH3
or hrdy3_br
`endif
`ifdef DMA_HAVE_CH4
or hrdy4_br
`endif
`ifdef DMA_HAVE_CH5
or hrdy5_br
`endif
`ifdef DMA_HAVE_CH6
or hrdy6_br
`endif
`ifdef DMA_HAVE_CH7
or hrdy7_br
`endif
)
case(mux_no)
'h0: hrdyi = hrdy0_dma;
`ifdef DMA_HAVE_CH1
'h1: hrdyi = hrdy1_dma;
`endif
`ifdef DMA_HAVE_CH2
'h2: hrdyi = hrdy2_dma;
`endif
`ifdef DMA_HAVE_CH3
'h3: hrdyi = hrdy3_dma;
`endif
`ifdef DMA_HAVE_CH4
'h4: hrdyi = hrdy4_dma;
`endif
`ifdef DMA_HAVE_CH5
'h5: hrdyi = hrdy5_dma;
`endif
`ifdef DMA_HAVE_CH6
'h6: hrdyi = hrdy6_dma;
`endif
`ifdef DMA_HAVE_CH7
'h7: hrdyi = hrdy7_dma;
`endif
'h8: hrdyi = hrdy0_br;
`ifdef DMA_HAVE_CH1
'h9: hrdyi = hrdy1_br;
`endif
`ifdef DMA_HAVE_CH2
'ha: hrdyi = hrdy2_br;
`endif
`ifdef DMA_HAVE_CH3
'hb: hrdyi = hrdy3_br;
`endif
`ifdef DMA_HAVE_CH4
'hc: hrdyi = hrdy4_br;
`endif
`ifdef DMA_HAVE_CH5
'hd: hrdyi = hrdy5_br;
`endif
`ifdef DMA_HAVE_CH6
'he: hrdyi = hrdy6_br;
`endif
`ifdef DMA_HAVE_CH7
'hf: hrdyi = hrdy7_br;
`endif
default: hrdyi = hrdy0_dma;
endcase
assign hreadyin = hrmxnof ? hrdy_df : hrdyi;
endmodule
`endif
`endif
|
`include "DMA_DEFINE.vh"
module dma_ahbslv
(
HCLK,
HRSTn,
hreadyin,
hsel_reg,
`ifdef DMA_HAVE_AHB1
`ifdef DMA_HAVE_BRIDGE
hsel_br,
`endif
`endif
htrans,
hsize,
hprot,
hwrite,
haddr,
hwdata,
hresp_reg,
hreadyout_reg,
hrdata_reg,
`ifdef DMA_HAVE_AHB1
`ifdef DMA_HAVE_BRIDGE
hresp_br,
hreadyout_br,
hrdata_br,
`endif
`endif
rf_dti,
`ifdef DMA_HAVE_AHB1
`ifdef DMA_HAVE_BRIDGE
de_arb_br,
`endif
`endif
m0endian,
m1endian,
m1_dt_st,
`ifdef DMA_HAVE_AHB1
`ifdef DMA_HAVE_BRIDGE
h1trans,
h1rdata,
h1readyin,
h1resp,
`endif
`endif
slv_ado,
slv_ad_d1o,
slv_dto,
slv_szo,
slv_sz_d1o,
slv_pt_d1o,
slv_wr_d1o,
slv_rf_req
`ifdef DMA_HAVE_AHB1
`ifdef DMA_HAVE_BRIDGE
,
slv_br_req,
slv_br_dto,
slv_brst_cmd,
slv_brst_mscd
`endif
`endif
);
input HCLK;
input HRSTn;
input hreadyin;
input hsel_reg;
`ifdef DMA_HAVE_AHB1
`ifdef DMA_HAVE_BRIDGE
input hsel_br;
`endif
`endif
input [`DMA_HTRANS_WIDTH-1:0] htrans;
input [`DMA_HSIZE_WIDTH-1:0] hsize;
input [`DMA_HPROT_WIDTH-1:0] hprot;
input hwrite;
input [`DMA_HADDR_WIDTH-1:0] haddr;
input [`DMA_HDATA_WIDTH-1:0] hwdata;
output [`DMA_HRESP_WIDTH-1:0] hresp_reg;
output hreadyout_reg;
output [`DMA_HDATA_WIDTH-1:0] hrdata_reg;
`ifdef DMA_HAVE_AHB1
`ifdef DMA_HAVE_BRIDGE
output [`DMA_HRESP_WIDTH-1:0] hresp_br;
output hreadyout_br;
output [`DMA_HDATA_WIDTH-1:0] hrdata_br;
`endif
`endif
input [`DMA_HDATA_WIDTH-1:0] rf_dti;
`ifdef DMA_HAVE_AHB1
`ifdef DMA_HAVE_BRIDGE
input de_arb_br;
`endif
`endif
input m0endian;
input m1endian;
input m1_dt_st;
`ifdef DMA_HAVE_AHB1
`ifdef DMA_HAVE_BRIDGE
input [`DMA_HTRANS_WIDTH-1:0] h1trans;
input [`DMA_HDATA_WIDTH-1:0] h1rdata;
input h1readyin;
input [`DMA_HRESP_WIDTH-1:0] h1resp;
`endif
`endif
output [`DMA_HADDR_WIDTH-1:0] slv_ado;
output [`DMA_HADDR_WIDTH-1:0] slv_ad_d1o;
output [`DMA_HDATA_WIDTH-1:0] slv_dto;
output [`DMA_HSIZE_WIDTH-1:0] slv_szo;
output [`DMA_HSIZE_WIDTH-1:0] slv_sz_d1o;
output [`DMA_HPROT_WIDTH-1:0] slv_pt_d1o;
output slv_wr_d1o;
output slv_rf_req;
`ifdef DMA_HAVE_AHB1
`ifdef DMA_HAVE_BRIDGE
output slv_br_req;
output [`DMA_HDATA_WIDTH-1:0] slv_br_dto;
output slv_brst_cmd;
output slv_brst_mscd;
`endif
`endif
wire slv_rf_req;
wire ad_d1_we;
wire reg_rdy_wait;
reg [`DMA_HADDR_WIDTH-1:0] slv_ad_d1o;
reg [`DMA_HSIZE_WIDTH-1:0] slv_sz_d1o;
reg [`DMA_HPROT_WIDTH-1:0] slv_pt_d1o;
reg slv_wr_d1o;
reg hreadyout_reg;
reg [`DMA_HDATA_WIDTH-1:0] hrdata_reg;
`ifdef DMA_HAVE_AHB1
`ifdef DMA_HAVE_BRIDGE
wire brst_cmd,brst_ms_cmd;
wire br_rdy0_p;
reg slv_br_req;
reg hreadyout_br;
reg [`DMA_HRESP_WIDTH-1:0] hresp_br;
reg [`DMA_HDATA_WIDTH-1:0] hrdata_br;
`endif
`endif
wire hrdy_to_1,hrp_br_err,hrp_br_rty;
wire m1_br_end;
wire htr_ns = (htrans == `DMA_HTRANS_NONSEQ);
wire htr_sq = (htrans == `DMA_HTRANS_SEQ);
assign slv_rf_req = (hsel_reg & hreadyin & htrans[1]);
assign slv_ado = haddr;
`ifdef DMA_HAVE_AHB1
`ifdef DMA_HAVE_BRIDGE
assign ad_d1_we = (hsel_br|hsel_reg) & htrans[1] & hreadyin;
`else
assign ad_d1_we = hsel_reg & htrans[1] & hreadyin;
`endif
`else
assign ad_d1_we = hsel_reg & htrans[1] & hreadyin;
`endif
always @(posedge HCLK or negedge HRSTn)
if(~HRSTn)
begin
slv_ad_d1o <= 'h0;
slv_sz_d1o <= 'h0;
slv_pt_d1o <= 'h0;
end
else if(ad_d1_we)
begin
slv_ad_d1o <= haddr;
slv_sz_d1o <= hsize;
slv_pt_d1o <= hprot;
end
always @(posedge HCLK or negedge HRSTn)
if(~HRSTn)
slv_wr_d1o <= 0;
else if(ad_d1_we)
slv_wr_d1o <= hwrite;
wire hsize_l_hw = (slv_sz_d1o==3'h1);
wire hsize_l_bt = (slv_sz_d1o==3'h0);
wire tr_l_hw = m0endian&hsize_l_hw;
wire tr_l_bt = m0endian&hsize_l_bt;
wire [7:0] s_rgdtb0 = (tr_l_hw)? hwdata[23:16] :
(tr_l_bt)? hwdata[31:24] : hwdata[7:0];
wire [7:0] s_rgdtb1 = (tr_l_hw)? hwdata[31:24] :
(tr_l_bt)? hwdata[23:16] : hwdata[15:8];
wire [7:0] s_rgdtb2 = (tr_l_hw)? hwdata[7:0] :
(tr_l_bt)? hwdata[15:8] : hwdata[23:16];
wire [7:0] s_rgdtb3 = (tr_l_hw)? hwdata[15:8] :
(tr_l_bt)? hwdata[7:0] : hwdata[31:24];
assign slv_dto = {s_rgdtb3,s_rgdtb2,s_rgdtb1,s_rgdtb0};
assign slv_szo = hsize;
assign reg_rdy_wait = slv_rf_req & hwrite & ( haddr[8:2] == slv_ad_d1o[8:2] );
always @(posedge HCLK or negedge HRSTn)
if(~HRSTn)
hreadyout_reg <= 1'b1;
else if(reg_rdy_wait)
hreadyout_reg <= 1'b0;
else
hreadyout_reg <= 1'b1;
assign hresp_reg = `DMA_HRESP_OK;
wire hrdt_we = hsel_reg&htrans[1];
wire hsize_hw = (hsize==3'h1);
wire hsize_bt = (hsize==3'h0);
wire tr_hw = m0endian&hsize_hw;
wire tr_bt = m0endian&hsize_bt;
wire [7:0] hrdtgb0 = (tr_hw)? rf_dti[23:16] :
(tr_bt)? rf_dti[31:24] : rf_dti[7:0];
wire [7:0] hrdtgb1 = (tr_hw)? rf_dti[31:24] :
(tr_bt)? rf_dti[23:16] : rf_dti[15:8];
wire [7:0] hrdtgb2 = (tr_hw)? rf_dti[7:0] :
(tr_bt)? rf_dti[15:8] : rf_dti[23:16];
wire [7:0] hrdtgb3 = (tr_hw)? rf_dti[15:8] :
(tr_bt)? rf_dti[7:0] : rf_dti[31:24];
always @(posedge HCLK or negedge HRSTn)
if(~HRSTn)
hrdata_reg <= 'h0;
else if(hrdt_we)
hrdata_reg <= {hrdtgb3,hrdtgb2,hrdtgb1,hrdtgb0};
`ifdef DMA_HAVE_AHB1
`ifdef DMA_HAVE_BRIDGE
wire h1rp_err = (h1resp==`DMA_HRESP_ERROR);
wire br_req_bgn = hsel_br & htr_ns & hreadyin;
wire br_req_end = brst_ms_cmd | m1_br_end;
always @(posedge HCLK or negedge HRSTn)
if(~HRSTn)
slv_br_req <= 1'b0;
else if(br_req_bgn)
slv_br_req <= 1'b1;
else if(br_req_end)
slv_br_req <= 1'b0;
wire m1_tr_ns = (h1trans == `DMA_HTRANS_NONSEQ);
wire m1_br_cmd = de_arb_br&m1_tr_ns&h1readyin&slv_br_req;
assign m1_br_end = (m1_dt_st&h1readyin)|h1rp_err;
parameter BR_IDLE = 3'b001,
BR_CMD = 3'b010,
BR_MS_CMD = 3'b100;
reg [2:0] br_st, br_ns;
assign brst_cmd = br_st[1];
assign brst_ms_cmd = br_st[2];
always @(br_st or br_req_bgn or m1_br_cmd or m1_br_end)
case(br_st)
BR_IDLE: if(br_req_bgn) br_ns = BR_CMD;
else br_ns = BR_IDLE;
BR_CMD: if(m1_br_cmd) br_ns = BR_MS_CMD;
else br_ns = BR_CMD;
BR_MS_CMD:if(m1_br_end) br_ns = BR_IDLE;
else br_ns = BR_MS_CMD;
default: br_ns = BR_IDLE;
endcase
always @(posedge HCLK or negedge HRSTn)
if(~HRSTn)
br_st <= BR_IDLE;
else
br_st <= br_ns;
wire bst_rty = hsel_br&htr_sq&hreadyout_br;
assign br_rdy0_p = br_req_bgn | brst_cmd | bst_rty;
assign hrp_br_err = (hresp_br == `DMA_HRESP_ERROR);
assign hrp_br_rty = (hresp_br == `DMA_HRESP_RETRY);
assign hrdy_to_1 = (((hrp_br_err|hrp_br_rty)&!hreadyout_br)|
(brst_ms_cmd&(m1_dt_st&h1readyin)));
always @(posedge HCLK or negedge HRSTn)
if(~HRSTn)
hreadyout_br <= 1'b1;
else if(br_rdy0_p)
hreadyout_br <= 1'b0;
else if(brst_ms_cmd)
hreadyout_br <= h1readyin;
else if(hrdy_to_1)
hreadyout_br <= 1'b1;
else
hreadyout_br <= hreadyout_br;
always @(posedge HCLK or negedge HRSTn)
if(~HRSTn)
hresp_br <= `DMA_HRESP_OK;
else if(bst_rty)
hresp_br <= `DMA_HRESP_RETRY;
else if(brst_ms_cmd)
hresp_br <= h1resp;
else if(hreadyout_br)
hresp_br <= `DMA_HRESP_OK;
wire cv_endn = m0endian^m1endian;
wire cv_endn_l_hw = cv_endn&hsize_l_hw;
wire cv_endn_l_bt = cv_endn&hsize_l_bt;
wire [7:0] s_brdtb0 = (cv_endn_l_hw)? hwdata[23:16] :
(cv_endn_l_bt)? hwdata[31:24] : hwdata[7:0];
wire [7:0] s_brdtb1 = (cv_endn_l_hw)? hwdata[31:24] :
(cv_endn_l_bt)? hwdata[23:16] : hwdata[15:8];
wire [7:0] s_brdtb2 = (cv_endn_l_hw)? hwdata[7:0] :
(cv_endn_l_bt)? hwdata[15:8] : hwdata[23:16];
wire [7:0] s_brdtb3 = (cv_endn_l_hw)? hwdata[15:8] :
(cv_endn_l_bt)? hwdata[7:0] : hwdata[31:24];
assign slv_br_dto = {s_brdtb3,s_brdtb2,s_brdtb1,s_brdtb0};
wire [7:0] h1rdtib0 = (cv_endn_l_hw)? h1rdata[23:16] :
(cv_endn_l_bt)? h1rdata[31:24] : h1rdata[7:0];
wire [7:0] h1rdtib1 = (cv_endn_l_hw)? h1rdata[31:24] :
(cv_endn_l_bt)? h1rdata[23:16] : h1rdata[15:8];
wire [7:0] h1rdtib2 = (cv_endn_l_hw)? h1rdata[7:0] :
(cv_endn_l_bt)? h1rdata[15:8] : h1rdata[23:16];
wire [7:0] h1rdtib3 = (cv_endn_l_hw)? h1rdata[15:8] :
(cv_endn_l_bt)? h1rdata[7:0] : h1rdata[31:24];
always @(posedge HCLK or negedge HRSTn)
if(~HRSTn)
hrdata_br <= 'h0;
else if(brst_ms_cmd)
hrdata_br <= {h1rdtib3,h1rdtib2,h1rdtib1,h1rdtib0};
assign slv_brst_mscd = brst_ms_cmd;
assign slv_brst_cmd = brst_cmd;
`endif
`endif
endmodule
|
`include "DMA_DEFINE.vh"
module dma_chrf
(
HCLK,
HRSTn,
be_d1,
chcsr_we,
chcfg_we,
chsad_we,
chdad_we,
`ifdef DMA_HAVE_LINKLIST
chllp_we,
`endif
chtsz_we,
slv_wdti,
de_sad_we,
de_dad_we,
`ifdef DMA_HAVE_LINKLIST
de_llp_we,
`endif
de_tsz_we,
de_en_clr,
de_csr_we,
`ifdef DMA_HAVE_LINKLIST
de_llpen_we,
`endif
de_sad,
de_dad,
`ifdef DMA_HAVE_LINKLIST
de_llp,
`endif
de_tsz,
de_csr,
`ifdef DMA_HAVE_LINKLIST
de_llpen,
de_err_notify,
tsz_eq0,
`endif
de_busy,
de_st_idle,
de_st_upd,
de_st_llp0,
arb_ch_sel,
chcsr,
chcfg,
chsad,
chdad,
`ifdef DMA_HAVE_LINKLIST
chllp,
`endif
chtsz,
chabt,
`ifdef DMA_HAVE_LINKLIST
chllpen
`endif
);
input HCLK;
input HRSTn;
input [3:0] be_d1;
input chcsr_we;
input chcfg_we;
input chsad_we;
input chdad_we;
`ifdef DMA_HAVE_LINKLIST
input chllp_we;
`endif
input chtsz_we;
input [`DMA_HDATA_WIDTH-1:0] slv_wdti;
input de_sad_we;
input de_dad_we;
`ifdef DMA_HAVE_LINKLIST
input de_llp_we;
`endif
input de_tsz_we;
input de_en_clr;
input de_csr_we;
`ifdef DMA_HAVE_LINKLIST
input de_llpen_we;
`endif
input [`DMA_HADDR_WIDTH-1:0] de_sad;
input [`DMA_HADDR_WIDTH-1:0] de_dad;
`ifdef DMA_HAVE_LINKLIST
input [`DMA_HADDR_WIDTH-1:0] de_llp;
`endif
input [`DMA_CHSZ_WIDTH-1:0] de_tsz;
input [`DMA_HDATA_WIDTH-1:0] de_csr;
`ifdef DMA_HAVE_LINKLIST
input de_llpen;
input de_err_notify;
input tsz_eq0;
`endif
input de_busy;
input de_st_idle;
input de_st_upd;
input de_st_llp0;
input [`DMA_CHNO_WIDTH-1:0] arb_ch_sel;
output [`DMA_CHCSR_WIDTH-1:0] chcsr;
output [`DMA_CHCFG_WIDTH-1:0] chcfg;
output [`DMA_HADDR_WIDTH-1:0] chsad;
output [`DMA_HADDR_WIDTH-1:0] chdad;
`ifdef DMA_HAVE_LINKLIST
output [`DMA_HADDR_WIDTH-1:0] chllp;
`endif
output [`DMA_CHSZ_WIDTH-1:0] chtsz;
output chabt;
`ifdef DMA_HAVE_LINKLIST
output chllpen;
`endif
parameter CH_NO = 0;
wire this_ch;
wire chabt_set;
wire chcsr_b0we_qf;
reg int_tc_msk;
reg [1:0] chpri;
reg dreqmode;
reg prot3, prot2, prot1;
reg [2:0] src_sz;
reg autold;
reg [2:0] swidth;
reg [2:0] dwidth;
reg mode;
reg sad_ctl1, sad_ctl0;
reg dad_ctl1, dad_ctl0;
reg src_sel, dst_sel;
reg ch_en;
reg int_abt_msk;
reg int_err_msk;
reg int_tc1_msk;
reg [`DMA_HADDR_WIDTH-1:0] chsad,chdad;
`ifdef DMA_HAVE_LINKLIST
reg [`DMA_HADDR_WIDTH-1:0] chllp;
`endif
reg [`DMA_CHSZ_WIDTH-1:0] chtsz;
reg chabt;
`ifdef DMA_HAVE_LINKLIST
reg chllpen;
`endif
assign this_ch = (arb_ch_sel == CH_NO);
`ifdef DMA_HAVE_LINKLIST
wire chllp_on_set,chllp_on_clr,chllp_cnt_clr,chllp_cnt_inc;
reg chllp_on;
reg [3:0] chllp_cnt;
wire chllpen_clr = (this_ch&(de_err_notify|chabt)&de_st_upd) |
(chabt&(de_st_idle|(!de_st_idle&!this_ch)));
always @(posedge HCLK or negedge HRSTn)
if(~HRSTn)
chllpen <= 'b0;
else if(this_ch&ch_en&de_llpen_we&~(de_err_notify|chabt))
chllpen <= de_llpen;
else if(chllpen_clr)
chllpen <= 1'b0;
assign chllp_on_set = !chllp_on & ch_en & (|chllp[31:2]);
assign chllp_on_clr = chllp_on & !ch_en;
always @(posedge HCLK or negedge HRSTn)
if(~HRSTn)
chllp_on <= 1'b0;
else if(chllp_on_set)
chllp_on <= 1'b1;
else if(chllp_on_clr)
chllp_on <= 1'b0;
assign chllp_cnt_clr = !ch_en&chcsr_b0we_qf&slv_wdti[0];
assign chllp_cnt_inc = chllp_on&de_st_upd&this_ch&
(tsz_eq0|de_err_notify|chabt);
always @(posedge HCLK or negedge HRSTn)
if(~HRSTn)
chllp_cnt <= 0;
else if(chllp_cnt_clr)
chllp_cnt <= 0;
else if(chllp_cnt_inc)
chllp_cnt <= chllp_cnt + 1;
`else
wire chllp_cnt;
assign chllp_cnt = 0;
`endif
wire chcsr_b0we = chcsr_we & be_d1[0];
wire chcsr_b1we = chcsr_we & be_d1[1];
wire chcsr_b2we = chcsr_we & be_d1[2];
wire chcsr_b3we = chcsr_we & be_d1[3];
always @(posedge HCLK or negedge HRSTn)
begin
if(~HRSTn)
int_tc_msk <= 1'b0;
else
begin
if(chcsr_b3we&~chabt_set)
int_tc_msk <= slv_wdti[31];
else if(this_ch&de_csr_we)
int_tc_msk <= de_csr[28];
end
end
always @(posedge HCLK or negedge HRSTn)
if(~HRSTn)
chpri <= 2'b0;
else if(chcsr_b2we&~chabt_set)
chpri <= slv_wdti[23:22];
always @(posedge HCLK or negedge HRSTn)
if(~HRSTn)
dreqmode <= 1'b0;
else if(chcsr_b3we&~chabt_set)
dreqmode <= slv_wdti[24];
always @(posedge HCLK or negedge HRSTn)
if(~HRSTn)
begin
prot3 <= 1'b0;
prot2 <= 1'b0;
prot1 <= 1'b0;
end
else if(chcsr_b2we&~chabt_set)
begin
prot3 <= slv_wdti[21];
prot2 <= slv_wdti[20];
prot1 <= slv_wdti[19];
end
always @(posedge HCLK or negedge HRSTn)
if(~HRSTn)
src_sz <= 3'b0;
else if(chcsr_b2we&~chabt_set)
src_sz <= slv_wdti[18:16];
wire chabt_clr =
chabt&((!de_st_idle&((this_ch&de_st_upd)| !this_ch)) |
de_st_upd |
de_st_idle);
assign chabt_set = chcsr_b2we & slv_wdti[15];
always @(posedge HCLK or negedge HRSTn)
if(~HRSTn)
chabt <= 1'b0;
else if(chcsr_b2we)
chabt <= slv_wdti[15];
else if(chabt_clr)
chabt <= 1'b0;
always @(posedge HCLK or negedge HRSTn)
if(~HRSTn)
autold <= 1'b0;
else if(chcsr_b1we&~chabt_set)
autold <= slv_wdti[14];
always @(posedge HCLK or negedge HRSTn)
if(~HRSTn)
swidth <= 3'b010;
else if(chcsr_b1we&~chabt_set)
swidth <= slv_wdti[13:11];
else if(this_ch&de_csr_we)
swidth <= de_csr[27:25];
always @(posedge HCLK or negedge HRSTn)
if(~HRSTn)
dwidth <= 3'b010;
else if(chcsr_b1we&~chabt_set)
dwidth <= slv_wdti[10:8];
else if(this_ch&de_csr_we)
dwidth <= de_csr[24:22];
always @(posedge HCLK or negedge HRSTn)
if(~HRSTn)
mode <= 1'b0;
else if(chcsr_b0we_qf)
mode <= slv_wdti[7];
always @(posedge HCLK or negedge HRSTn)
if(~HRSTn)
begin
sad_ctl1 <= 1'b0;
sad_ctl0 <= 1'b0;
dad_ctl1 <= 1'b0;
dad_ctl0 <= 1'b0;
src_sel <= 1'b0;
dst_sel <= 1'b0;
end
else if(chcsr_b0we_qf)
begin
sad_ctl1 <= slv_wdti[6];
sad_ctl0 <= slv_wdti[5];
dad_ctl1 <= slv_wdti[4];
dad_ctl0 <= slv_wdti[3];
src_sel <= slv_wdti[2];
dst_sel <= slv_wdti[1];
end
else if(this_ch&de_csr_we)
begin
sad_ctl1 <= de_csr[21];
sad_ctl0 <= de_csr[20];
dad_ctl1 <= de_csr[19];
dad_ctl0 <= de_csr[18];
src_sel <= de_csr[17];
dst_sel <= de_csr[16];
end
wire chen_declr = ((this_ch&de_en_clr) |
(chabt&(de_st_idle|(!de_st_idle&!this_ch))));
assign chcsr_b0we_qf = chcsr_b0we&~chabt_set;
always @(posedge HCLK or negedge HRSTn)
if(~HRSTn)
ch_en <= 1'b0;
else if(chcsr_b0we_qf)
ch_en <= slv_wdti[0];
else if(chen_declr)
ch_en <= 1'b0;
wire chcfg_b0we = chcfg_we & be_d1[0];
always @(posedge HCLK or negedge HRSTn)
if(~HRSTn)
begin
int_abt_msk <= 1'b1;
int_err_msk <= 1'b1;
int_tc1_msk <= 1'b1;
end
else if(chcfg_b0we)
begin
int_abt_msk <= slv_wdti[2];
int_err_msk <= slv_wdti[1];
int_tc1_msk <= slv_wdti[0];
end
wire chsad_b0we = chsad_we & be_d1[0];
wire chsad_b1we = chsad_we & be_d1[1];
wire chsad_b2we = chsad_we & be_d1[2];
wire chsad_b3we = chsad_we & be_d1[3];
wire chsad_dewe = this_ch & de_sad_we;
always @(posedge HCLK or negedge HRSTn)
if(~HRSTn)
chsad[7:0] <= 'h0;
else if(chsad_b0we)
chsad[7:0] <= slv_wdti[7:0];
else if(chsad_dewe)
chsad[7:0] <= de_sad[7:0];
always @(posedge HCLK or negedge HRSTn)
if(~HRSTn)
chsad[15:8] <= 'h0;
else if(chsad_b1we)
chsad[15:8] <= slv_wdti[15:8];
else if(chsad_dewe)
chsad[15:8] <= de_sad[15:8];
always @(posedge HCLK or negedge HRSTn)
if(~HRSTn)
chsad[23:16] <= 'h0;
else if(chsad_b2we)
chsad[23:16] <= slv_wdti[23:16];
else if(chsad_dewe)
chsad[23:16] <= de_sad[23:16];
always @(posedge HCLK or negedge HRSTn)
if(~HRSTn)
chsad[31:24] <= 'h0;
else if(chsad_b3we)
chsad[31:24] <= slv_wdti[31:24];
else if(chsad_dewe)
chsad[31:24] <= de_sad[31:24];
wire chdad_b0we = chdad_we & be_d1[0];
wire chdad_b1we = chdad_we & be_d1[1];
wire chdad_b2we = chdad_we & be_d1[2];
wire chdad_b3we = chdad_we & be_d1[3];
wire chdad_dewe = this_ch & de_dad_we;
always @(posedge HCLK or negedge HRSTn)
if(~HRSTn)
chdad[7:0] <= 'h0;
else if(chdad_b0we)
chdad[7:0] <= slv_wdti[7:0];
else if(chdad_dewe)
chdad[7:0] <= de_dad[7:0];
always @(posedge HCLK or negedge HRSTn)
if(~HRSTn)
chdad[15:8] <= 'h0;
else if(chdad_b1we)
chdad[15:8] <= slv_wdti[15:8];
else if(chdad_dewe)
chdad[15:8] <= de_dad[15:8];
always @(posedge HCLK or negedge HRSTn)
if(~HRSTn)
chdad[23:16] <= 'h0;
else if(chdad_b2we)
chdad[23:16] <= slv_wdti[23:16];
else if(chdad_dewe)
chdad[23:16] <= de_dad[23:16];
always @(posedge HCLK or negedge HRSTn)
if(~HRSTn)
chdad[31:24] <= 'h0;
else if(chdad_b3we)
chdad[31:24] <= slv_wdti[31:24];
else if(chdad_dewe)
chdad[31:24] <= de_dad[31:24];
`ifdef DMA_HAVE_LINKLIST
wire chllp_b0we = chllp_we & be_d1[0];
wire chllp_b1we = chllp_we & be_d1[1];
wire chllp_b2we = chllp_we & be_d1[2];
wire chllp_b3we = chllp_we & be_d1[3];
wire chllp_dewe = this_ch & de_llp_we;
always @(posedge HCLK or negedge HRSTn)
if(~HRSTn)
chllp[7:0] <= 8'b0;
else if(chllp_b0we)
chllp[7:0] <= slv_wdti[7:0];
else if(chllp_dewe)
chllp[7:0] <= de_llp[7:0];
always @(posedge HCLK or negedge HRSTn)
if(~HRSTn)
chllp[15:8] <= 8'b0;
else if(chllp_b1we)
chllp[15:8] <= slv_wdti[15:8];
else if(chllp_dewe)
chllp[15:8] <= de_llp[15:8];
always @(posedge HCLK or negedge HRSTn)
if(~HRSTn)
chllp[23:16] <= 8'b0;
else if(chllp_b2we)
chllp[23:16] <= slv_wdti[23:16];
else if(chllp_dewe)
chllp[23:16] <= de_llp[23:16];
always @(posedge HCLK or negedge HRSTn)
if(~HRSTn)
chllp[31:24] <= 8'b0;
else if(chllp_b3we)
chllp[31:24] <= slv_wdti[31:24];
else if(chllp_dewe)
chllp[31:24] <= de_llp[31:24];
`endif
wire chtsz_b0we = chtsz_we & be_d1[0];
wire chtsz_b1we = chtsz_we & be_d1[1];
wire chtsz_dewe = this_ch & de_tsz_we;
always @(posedge HCLK or negedge HRSTn)
if(~HRSTn)
chtsz[7:0] <= 'h0;
else if(chtsz_b0we)
chtsz[7:0] <= slv_wdti[7:0];
else if(chtsz_dewe)
chtsz[7:0] <= de_tsz[7:0];
always @(posedge HCLK or negedge HRSTn)
if(~HRSTn)
chtsz[`DMA_CHSZ_WIDTH-1:8] <= 'h0;
else if(chtsz_b1we)
chtsz[`DMA_CHSZ_WIDTH-1:8] <= slv_wdti[`DMA_CHSZ_WIDTH-1:8];
else if(chtsz_dewe)
chtsz[`DMA_CHSZ_WIDTH-1:8] <= de_tsz[`DMA_CHSZ_WIDTH-1:8];
assign chcsr = {int_tc_msk, 6'b0, dreqmode,
chpri, prot3, prot2, prot1, src_sz,
chabt, autold, swidth, dwidth,
mode, sad_ctl1, sad_ctl0, dad_ctl1, dad_ctl0,
src_sel, dst_sel, ch_en};
wire chbusy = this_ch & de_busy;
assign chcfg = {8'b0, 4'b0, chllp_cnt, 7'b0, chbusy,
5'b0, int_abt_msk, int_err_msk, int_tc1_msk};
endmodule
|
`include "DMA_DEFINE.vh"
module dma_chsel
(
HCLK, HRSTn,
dma_req, dma_ack, dma_tc,
csr, sync,
de_err_notify,
c0csr, c0cfg, c0sad, c0dad,
`ifdef DMA_HAVE_LINKLIST
c0llp,
`endif
c0tsz, c0abt,
`ifdef DMA_HAVE_LINKLIST
c0llpen,
`endif
`ifdef DMA_HAVE_CH1
c1csr, c1cfg, c1sad, c1dad,
`ifdef DMA_HAVE_LINKLIST
c1llp,
`endif
c1tsz, c1abt,
`ifdef DMA_HAVE_LINKLIST
c1llpen,
`endif
`endif
`ifdef DMA_HAVE_CH2
c2csr, c2cfg, c2sad, c2dad,
`ifdef DMA_HAVE_LINKLIST
c2llp,
`endif
c2tsz, c2abt,
`ifdef DMA_HAVE_LINKLIST
c2llpen,
`endif
`endif
`ifdef DMA_HAVE_CH3
c3csr, c3cfg, c3sad, c3dad,
`ifdef DMA_HAVE_LINKLIST
c3llp,
`endif
c3tsz, c3abt,
`ifdef DMA_HAVE_LINKLIST
c3llpen,
`endif
`endif
`ifdef DMA_HAVE_CH4
c4csr, c4cfg, c4sad, c4dad,
`ifdef DMA_HAVE_LINKLIST
c4llp,
`endif
c4tsz, c4abt,
`ifdef DMA_HAVE_LINKLIST
c4llpen,
`endif
`endif
`ifdef DMA_HAVE_CH5
c5csr, c5cfg, c5sad, c5dad,
`ifdef DMA_HAVE_LINKLIST
c5llp,
`endif
c5tsz, c5abt,
`ifdef DMA_HAVE_LINKLIST
c5llpen,
`endif
`endif
`ifdef DMA_HAVE_CH6
c6csr, c6cfg, c6sad, c6dad,
`ifdef DMA_HAVE_LINKLIST
c6llp,
`endif
c6tsz, c6abt,
`ifdef DMA_HAVE_LINKLIST
c6llpen,
`endif
`endif
`ifdef DMA_HAVE_CH7
c7csr, c7cfg, c7sad, c7dad,
`ifdef DMA_HAVE_LINKLIST
c7llp,
`endif
c7tsz, c7abt,
`ifdef DMA_HAVE_LINKLIST
c7llpen,
`endif
`endif
arb_ch_sel,
arb_chcsr, arb_chsad, arb_chdad,
`ifdef DMA_HAVE_LINKLIST
arb_chllp,
`endif
arb_chtsz, arb_chabt,
`ifdef DMA_HAVE_LINKLIST
arb_chllpen,
`endif
arb_abt_any,
de_ack,
de_stup,
de_st_idle,
de_abt_on_idle,
tsz_eq0,
arb_req
);
input HCLK, HRSTn;
input [`DMA_MAX_CHNO-1:0] dma_req;
output [`DMA_MAX_CHNO-1:0] dma_ack;
output [`DMA_MAX_CHNO-1:0] dma_tc;
input [`DMA_CSR_WIDTH-1:0] csr;
input [`DMA_MAX_CHNO-1:0] sync;
input de_err_notify;
input [`DMA_CHCSR_WIDTH-1:0] c0csr;
input [`DMA_CHCFG_WIDTH-1:0] c0cfg;
input [`DMA_HADDR_WIDTH-1:0] c0sad;
input [`DMA_HADDR_WIDTH-1:0] c0dad;
`ifdef DMA_HAVE_LINKLIST
input [`DMA_HADDR_WIDTH-1:0] c0llp;
`endif
input [`DMA_CHSZ_WIDTH-1:0] c0tsz;
input c0abt;
`ifdef DMA_HAVE_LINKLIST
input c0llpen;
`endif
`ifdef DMA_HAVE_CH1
input [`DMA_CHCSR_WIDTH-1:0] c1csr;
input [`DMA_CHCFG_WIDTH-1:0] c1cfg;
input [`DMA_HADDR_WIDTH-1:0] c1sad;
input [`DMA_HADDR_WIDTH-1:0] c1dad;
`ifdef DMA_HAVE_LINKLIST
input [`DMA_HADDR_WIDTH-1:0] c1llp;
`endif
input [`DMA_CHSZ_WIDTH-1:0] c1tsz;
input c1abt;
`ifdef DMA_HAVE_LINKLIST
input c1llpen;
`endif
`endif
`ifdef DMA_HAVE_CH2
input [`DMA_CHCSR_WIDTH-1:0] c2csr;
input [`DMA_CHCFG_WIDTH-1:0] c2cfg;
input [`DMA_HADDR_WIDTH-1:0] c2sad;
input [`DMA_HADDR_WIDTH-1:0] c2dad;
`ifdef DMA_HAVE_LINKLIST
input [`DMA_HADDR_WIDTH-1:0] c2llp;
`endif
input [`DMA_CHSZ_WIDTH-1:0] c2tsz;
input c2abt;
`ifdef DMA_HAVE_LINKLIST
input c2llpen;
`endif
`endif
`ifdef DMA_HAVE_CH3
input [`DMA_CHCSR_WIDTH-1:0] c3csr;
input [`DMA_CHCFG_WIDTH-1:0] c3cfg;
input [`DMA_HADDR_WIDTH-1:0] c3sad;
input [`DMA_HADDR_WIDTH-1:0] c3dad;
`ifdef DMA_HAVE_LINKLIST
input [`DMA_HADDR_WIDTH-1:0] c3llp;
`endif
input [`DMA_CHSZ_WIDTH-1:0] c3tsz;
input c3abt;
`ifdef DMA_HAVE_LINKLIST
input c3llpen;
`endif
`endif
`ifdef DMA_HAVE_CH4
input [`DMA_CHCSR_WIDTH-1:0] c4csr;
input [`DMA_CHCFG_WIDTH-1:0] c4cfg;
input [`DMA_HADDR_WIDTH-1:0] c4sad;
input [`DMA_HADDR_WIDTH-1:0] c4dad;
`ifdef DMA_HAVE_LINKLIST
input [`DMA_HADDR_WIDTH-1:0] c4llp;
`endif
input [`DMA_CHSZ_WIDTH-1:0] c4tsz;
input c4abt;
`ifdef DMA_HAVE_LINKLIST
input c4llpen;
`endif
`endif
`ifdef DMA_HAVE_CH5
input [`DMA_CHCSR_WIDTH-1:0] c5csr;
input [`DMA_CHCFG_WIDTH-1:0] c5cfg;
input [`DMA_HADDR_WIDTH-1:0] c5sad;
input [`DMA_HADDR_WIDTH-1:0] c5dad;
`ifdef DMA_HAVE_LINKLIST
input [`DMA_HADDR_WIDTH-1:0] c5llp;
`endif
input [`DMA_CHSZ_WIDTH-1:0] c5tsz;
input c5abt;
`ifdef DMA_HAVE_LINKLIST
input c5llpen;
`endif
`endif
`ifdef DMA_HAVE_CH6
input [`DMA_CHCSR_WIDTH-1:0] c6csr;
input [`DMA_CHCFG_WIDTH-1:0] c6cfg;
input [`DMA_HADDR_WIDTH-1:0] c6sad;
input [`DMA_HADDR_WIDTH-1:0] c6dad;
`ifdef DMA_HAVE_LINKLIST
input [`DMA_HADDR_WIDTH-1:0] c6llp;
`endif
input [`DMA_CHSZ_WIDTH-1:0] c6tsz;
input c6abt;
`ifdef DMA_HAVE_LINKLIST
input c6llpen;
`endif
`endif
`ifdef DMA_HAVE_CH7
input [`DMA_CHCSR_WIDTH-1:0] c7csr;
input [`DMA_CHCFG_WIDTH-1:0] c7cfg;
input [`DMA_HADDR_WIDTH-1:0] c7sad;
input [`DMA_HADDR_WIDTH-1:0] c7dad;
`ifdef DMA_HAVE_LINKLIST
input [`DMA_HADDR_WIDTH-1:0] c7llp;
`endif
input [`DMA_CHSZ_WIDTH-1:0] c7tsz;
input c7abt;
`ifdef DMA_HAVE_LINKLIST
input c7llpen;
`endif
`endif
output [`DMA_CHCSR_WIDTH-1:0] arb_chcsr;
output [`DMA_HADDR_WIDTH-1:0] arb_chsad;
output [`DMA_HADDR_WIDTH-1:0] arb_chdad;
`ifdef DMA_HAVE_LINKLIST
output [`DMA_HADDR_WIDTH-1:0] arb_chllp;
`endif
output [`DMA_CHSZ_WIDTH-1:0] arb_chtsz;
output arb_chabt;
`ifdef DMA_HAVE_LINKLIST
output arb_chllpen;
`endif
output arb_abt_any;
output [`DMA_CHNO_WIDTH-1:0] arb_ch_sel;
input de_ack;
input de_stup;
input de_st_idle;
input de_abt_on_idle;
input tsz_eq0;
output arb_req;
wire [`DMA_PRI_WIDTH-1:0] ch0pri, ch1pri, ch2pri, ch3pri;
wire [`DMA_PRI_WIDTH-1:0] ch4pri, ch5pri, ch6pri, ch7pri;
wire [`DMA_MAX_CHNO-1:0] abnormal;
wire [`DMA_MAX_CHNO-1:0] dma_reqs;
wire [`DMA_MAX_CHNO-1:0] hwvld_req;
wire [`DMA_MAX_CHNO-1:0] vld_req;
wire [`DMA_PRI_LEVEL-1:0] chfpri_nx;
wire vld_req_any;
wire [`DMA_MAX_CHNO-1:0] dmaack_nx;
wire [`DMA_MAX_CHNO-1:0] dmatc_nx;
wire [`DMA_MAX_CHNO-1:0] vld_req_p0, vld_req_p1;
wire [`DMA_MAX_CHNO-1:0] vld_req_p2, vld_req_p3;
wire [`DMA_CHNO_WIDTH-1:0] gnt_p0, gnt_p1, gnt_p2, gnt_p3;
wire next_ch;
wire ch_sel0,ch_sel1,ch_sel2,ch_sel3;
wire ch_sel4,ch_sel5,ch_sel6,ch_sel7;
wire dma_tc_st1;
reg [`DMA_PRI_LEVEL-1:0] ch0fpri;
`ifdef DMA_HAVE_CH1
reg [`DMA_PRI_LEVEL-1:0] ch1fpri;
`endif
`ifdef DMA_HAVE_CH2
reg [`DMA_PRI_LEVEL-1:0] ch2fpri;
`endif
`ifdef DMA_HAVE_CH3
reg [`DMA_PRI_LEVEL-1:0] ch3fpri;
`endif
`ifdef DMA_HAVE_CH4
reg [`DMA_PRI_LEVEL-1:0] ch4fpri;
`endif
`ifdef DMA_HAVE_CH5
reg [`DMA_PRI_LEVEL-1:0] ch5fpri;
`endif
`ifdef DMA_HAVE_CH6
reg [`DMA_PRI_LEVEL-1:0] ch6fpri;
`endif
`ifdef DMA_HAVE_CH7
reg [`DMA_PRI_LEVEL-1:0] ch7fpri;
`endif
reg [`DMA_PRI_WIDTH-1:0] fix_pri_sel;
reg [`DMA_CHNO_WIDTH-1:0] arb_ch_sel;
reg vld_req_any_d1;
reg [`DMA_MAX_CHNO-1:0] dma_reqd1,dma_reqd2;
reg [`DMA_MAX_CHNO-1:0] dma_ack;
reg [`DMA_MAX_CHNO-1:0] dma_tc;
reg [`DMA_CHCSR_WIDTH-8:0] arb_chcsr_reg;
reg [`DMA_CHCSR_WIDTH-1:0] arb_chcsri;
reg [`DMA_HADDR_WIDTH-1:0] arb_chsad;
reg [`DMA_HADDR_WIDTH-1:0] arb_chdad;
`ifdef DMA_HAVE_LINKLIST
reg [`DMA_HADDR_WIDTH-1:0] arb_chllp;
`endif
reg [`DMA_CHSZ_WIDTH-1:0] arb_chtsz;
reg arb_chabt;
`ifdef DMA_HAVE_LINKLIST
reg arb_chllpen;
`endif
reg arb_req,de_stup_d1;
assign ch0pri = c0csr[`DMA_CHCSR_PRI];
`ifdef DMA_HAVE_CH1
assign ch1pri = c1csr[`DMA_CHCSR_PRI];
`endif
`ifdef DMA_HAVE_CH2
assign ch2pri = c2csr[`DMA_CHCSR_PRI];
`endif
`ifdef DMA_HAVE_CH3
assign ch3pri = c3csr[`DMA_CHCSR_PRI];
`endif
`ifdef DMA_HAVE_CH4
assign ch4pri = c4csr[`DMA_CHCSR_PRI];
`endif
`ifdef DMA_HAVE_CH5
assign ch5pri = c5csr[`DMA_CHCSR_PRI];
`endif
`ifdef DMA_HAVE_CH6
assign ch6pri = c6csr[`DMA_CHCSR_PRI];
`endif
`ifdef DMA_HAVE_CH7
assign ch7pri = c7csr[`DMA_CHCSR_PRI];
`endif
always @(posedge HCLK)
begin
dma_reqd1[0] <= dma_req[0];
`ifdef DMA_HAVE_CH1
dma_reqd1[1] <= dma_req[1];
`endif
`ifdef DMA_HAVE_CH2
dma_reqd1[2] <= dma_req[2];
`endif
`ifdef DMA_HAVE_CH3
dma_reqd1[3] <= dma_req[3];
`endif
`ifdef DMA_HAVE_CH4
dma_reqd1[4] <= dma_req[4];
`endif
`ifdef DMA_HAVE_CH5
dma_reqd1[5] <= dma_req[5];
`endif
`ifdef DMA_HAVE_CH6
dma_reqd1[6] <= dma_req[6];
`endif
`ifdef DMA_HAVE_CH7
dma_reqd1[7] <= dma_req[7];
`endif
end
always @(posedge HCLK)
begin
dma_reqd2[0] <= sync[0] & dma_reqd1[0];
`ifdef DMA_HAVE_CH1
dma_reqd2[1] <= sync[1] & dma_reqd1[1];
`endif
`ifdef DMA_HAVE_CH2
dma_reqd2[2] <= sync[2] & dma_reqd1[2];
`endif
`ifdef DMA_HAVE_CH3
dma_reqd2[3] <= sync[3] & dma_reqd1[3];
`endif
`ifdef DMA_HAVE_CH4
dma_reqd2[4] <= sync[4] & dma_reqd1[4];
`endif
`ifdef DMA_HAVE_CH5
dma_reqd2[5] <= sync[5] & dma_reqd1[5];
`endif
`ifdef DMA_HAVE_CH6
dma_reqd2[6] <= sync[6] & dma_reqd1[6];
`endif
`ifdef DMA_HAVE_CH7
dma_reqd2[7] <= sync[7] & dma_reqd1[7];
`endif
end
assign dma_reqs[0] = sync[0]? dma_reqd2[0] : dma_reqd1[0];
`ifdef DMA_HAVE_CH1
assign dma_reqs[1] = sync[1]? dma_reqd2[1] : dma_reqd1[1];
`endif
`ifdef DMA_HAVE_CH2
assign dma_reqs[2] = sync[2]? dma_reqd2[2] : dma_reqd1[2];
`endif
`ifdef DMA_HAVE_CH3
assign dma_reqs[3] = sync[3]? dma_reqd2[3] : dma_reqd1[3];
`endif
`ifdef DMA_HAVE_CH4
assign dma_reqs[4] = sync[4]? dma_reqd2[4] : dma_reqd1[4];
`endif
`ifdef DMA_HAVE_CH5
assign dma_reqs[5] = sync[5]? dma_reqd2[5] : dma_reqd1[5];
`endif
`ifdef DMA_HAVE_CH6
assign dma_reqs[6] = sync[6]? dma_reqd2[6] : dma_reqd1[6];
`endif
`ifdef DMA_HAVE_CH7
assign dma_reqs[7] = sync[7]? dma_reqd2[7] : dma_reqd1[7];
`endif
assign hwvld_req[0] = dma_reqs[0] & ~dma_ack[0] & !((arb_ch_sel==0) & de_ack);
`ifdef DMA_HAVE_CH1
assign hwvld_req[1] = dma_reqs[1] & ~dma_ack[1] & !((arb_ch_sel==1) & de_ack);
`endif
`ifdef DMA_HAVE_CH2
assign hwvld_req[2] = dma_reqs[2] & ~dma_ack[2] & !((arb_ch_sel==2) & de_ack);
`endif
`ifdef DMA_HAVE_CH3
assign hwvld_req[3] = dma_reqs[3] & ~dma_ack[3] & !((arb_ch_sel==3) & de_ack);
`endif
`ifdef DMA_HAVE_CH4
assign hwvld_req[4] = dma_reqs[4] & ~dma_ack[4] & !((arb_ch_sel==4) & de_ack);
`endif
`ifdef DMA_HAVE_CH5
assign hwvld_req[5] = dma_reqs[5] & ~dma_ack[5] & !((arb_ch_sel==5) & de_ack);
`endif
`ifdef DMA_HAVE_CH6
assign hwvld_req[6] = dma_reqs[6] & ~dma_ack[6] & !((arb_ch_sel==6) & de_ack);
`endif
`ifdef DMA_HAVE_CH7
assign hwvld_req[7] = dma_reqs[7] & ~dma_ack[7] & !((arb_ch_sel==7) & de_ack);
`endif
assign vld_req[0] = csr[0]&c0csr[`DMA_CHCSR_EN]&~abnormal[0]&(~c0csr[`DMA_CHCSR_MOD] |
(c0csr[`DMA_CHCSR_MOD]&hwvld_req[0]));
`ifdef DMA_HAVE_CH1
assign vld_req[1] = csr[0]&c1csr[`DMA_CHCSR_EN]&~abnormal[1]&(~c1csr[`DMA_CHCSR_MOD] |
(c1csr[`DMA_CHCSR_MOD]&hwvld_req[1]));
`endif
`ifdef DMA_HAVE_CH2
assign vld_req[2] = csr[0]&c2csr[`DMA_CHCSR_EN]&~abnormal[2]&(~c2csr[`DMA_CHCSR_MOD] |
(c2csr[`DMA_CHCSR_MOD]&hwvld_req[2]));
`endif
`ifdef DMA_HAVE_CH3
assign vld_req[3] = csr[0]&c3csr[`DMA_CHCSR_EN]&~abnormal[3]&(~c3csr[`DMA_CHCSR_MOD] |
(c3csr[`DMA_CHCSR_MOD]&hwvld_req[3]));
`endif
`ifdef DMA_HAVE_CH4
assign vld_req[4] = csr[0]&c4csr[`DMA_CHCSR_EN]&~abnormal[4]&(~c4csr[`DMA_CHCSR_MOD] |
(c4csr[`DMA_CHCSR_MOD]&hwvld_req[4]));
`endif
`ifdef DMA_HAVE_CH5
assign vld_req[5] = csr[0]&c5csr[`DMA_CHCSR_EN]&~abnormal[5]&(~c5csr[`DMA_CHCSR_MOD] |
(c5csr[`DMA_CHCSR_MOD]&hwvld_req[5]));
`endif
`ifdef DMA_HAVE_CH6
assign vld_req[6] = csr[0]&c6csr[`DMA_CHCSR_EN]&~abnormal[6]&(~c6csr[`DMA_CHCSR_MOD] |
(c6csr[`DMA_CHCSR_MOD]&hwvld_req[6]));
`endif
`ifdef DMA_HAVE_CH7
assign vld_req[7] = csr[0]&c7csr[`DMA_CHCSR_EN]&~abnormal[7]&(~c7csr[`DMA_CHCSR_MOD] |
(c7csr[`DMA_CHCSR_MOD]&hwvld_req[7]));
`endif
reg [3:0] ch0fprii;
always @(ch0pri)
case(ch0pri)
'h0: ch0fprii = 'b0001;
'h1: ch0fprii = 'b0010;
'h2: ch0fprii = 'b0100;
default: ch0fprii = 'b1000;
endcase
always @(vld_req or ch0fprii)
if(~vld_req[0])
ch0fpri = 'b0001;
else
ch0fpri = ch0fprii;
`ifdef DMA_HAVE_CH1
reg [3:0] ch1fprii;
always @(ch1pri)
case(ch1pri)
'h0: ch1fprii = 'b0001;
'h1: ch1fprii = 'b0010;
'h2: ch1fprii = 'b0100;
default: ch1fprii = 'b1000;
endcase
always @(vld_req or ch1fprii)
if(~vld_req[1])
ch1fpri = 'b0001;
else
ch1fpri = ch1fprii;
`endif
`ifdef DMA_HAVE_CH2
reg [3:0] ch2fprii;
always @(ch2pri)
case(ch2pri)
'h0: ch2fprii = 'b0001;
'h1: ch2fprii = 'b0010;
'h2: ch2fprii = 'b0100;
default: ch2fprii = 'b1000;
endcase
always @(vld_req or ch2fprii)
if(~vld_req[2])
ch2fpri = 'b0001;
else
ch2fpri = ch2fprii;
`endif
`ifdef DMA_HAVE_CH3
reg [3:0] ch3fprii;
always @(ch3pri)
case(ch3pri)
'h0: ch3fprii = 'b0001;
'h1: ch3fprii = 'b0010;
'h2: ch3fprii = 'b0100;
default: ch3fprii = 'b1000;
endcase
always @(vld_req or ch3fprii)
if(~vld_req[3])
ch3fpri = 'b0001;
else
ch3fpri = ch3fprii;
`endif
`ifdef DMA_HAVE_CH4
reg [3:0] ch4fprii;
always @(ch4pri)
case(ch4pri)
'h0: ch4fprii = 'b0001;
'h1: ch4fprii = 'b0010;
'h2: ch4fprii = 'b0100;
default: ch4fprii = 'b1000;
endcase
always @(vld_req or ch4fprii)
if(~vld_req[4])
ch4fpri = 'b0001;
else
ch4fpri = ch4fprii;
`endif
`ifdef DMA_HAVE_CH5
reg [3:0] ch5fprii;
always @(ch5pri)
case(ch5pri)
'h0: ch5fprii = 'b0001;
'h1: ch5fprii = 'b0010;
'h2: ch5fprii = 'b0100;
default: ch5fprii = 'b1000;
endcase
always @(vld_req or ch5fprii)
if(~vld_req[5])
ch5fpri = 'b0001;
else
ch5fpri = ch5fprii;
`endif
`ifdef DMA_HAVE_CH6
reg [3:0] ch6fprii;
always @(ch6pri)
case(ch6pri)
'h0: ch6fprii = 'b0001;
'h1: ch6fprii = 'b0010;
'h2: ch6fprii = 'b0100;
default: ch6fprii = 'b1000;
endcase
always @(vld_req or ch6fprii)
if(~vld_req[6])
ch6fpri = 'b0001;
else
ch6fpri = ch6fprii;
`endif
`ifdef DMA_HAVE_CH7
reg [3:0] ch7fprii;
always @(ch7pri)
case(ch7pri)
'h0: ch7fprii = 'b0001;
'h1: ch7fprii = 'b0010;
'h2: ch7fprii = 'b0100;
default: ch7fprii = 'b1000;
endcase
always @(vld_req or ch7fprii)
if(~vld_req[7])
ch7fpri = 'b0001;
else
ch7fpri = ch7fprii;
`endif
assign chfpri_nx = ch0fpri
`ifdef DMA_HAVE_CH1
| ch1fpri
`endif
`ifdef DMA_HAVE_CH2
| ch2fpri
`endif
`ifdef DMA_HAVE_CH3
| ch3fpri
`endif
`ifdef DMA_HAVE_CH4
| ch4fpri
`endif
`ifdef DMA_HAVE_CH5
| ch5fpri
`endif
`ifdef DMA_HAVE_CH6
| ch6fpri
`endif
`ifdef DMA_HAVE_CH7
| ch7fpri
`endif
;
reg [1:0] fix_pri_sx;
always @(chfpri_nx)
if (chfpri_nx[3]) fix_pri_sx = 'h3;
else if (chfpri_nx[2]) fix_pri_sx = 'h2;
else if (chfpri_nx[1]) fix_pri_sx = 'h1;
else fix_pri_sx = 'h0;
always @(posedge HCLK or negedge HRSTn)
if(~HRSTn)
fix_pri_sel <= 'h0;
else if(next_ch)
fix_pri_sel <= fix_pri_sx;
always @(fix_pri_sel or gnt_p0 or gnt_p1 or gnt_p2 or
gnt_p3)
case(fix_pri_sel)
'h0: arb_ch_sel = gnt_p0;
'h1: arb_ch_sel = gnt_p1;
'h2: arb_ch_sel = gnt_p2;
'h3: arb_ch_sel = gnt_p3;
endcase
assign vld_req_any = (| vld_req);
always @(posedge HCLK or negedge HRSTn)
if(~HRSTn)
vld_req_any_d1 <= 'b0;
else
vld_req_any_d1 <= vld_req_any;
wire vld_req_any1s = vld_req_any&~vld_req_any_d1;
/*
always @(posedge HCLK or negedge HRSTn)
if(~HRSTn)
arb_req <= 1'b0;
else if(~arb_req&~de_stup_d1&vld_req_any)
arb_req <= 1'b1;
else if(arb_req&de_stup)
arb_req <= 1'b0;
*/
always @(posedge HCLK or negedge HRSTn)
if(~HRSTn)
arb_req <= 1'b0;
else if(de_abt_on_idle|(arb_req&de_stup))
arb_req <= 1'b0;
else if(~arb_req&~de_stup_d1&vld_req_any)
arb_req <= 1'b1;
always @(posedge HCLK or negedge HRSTn)
if(~HRSTn)
de_stup_d1 <= 0;
else
de_stup_d1 <= de_stup;
assign next_ch = (vld_req_any1s&de_st_idle) |
de_stup_d1|de_abt_on_idle;
assign abnormal[0] = de_err_notify | c0abt;
assign dmaack_nx[0] = (~dma_ack[0] & ch_sel0 & c0csr[`DMA_CHCSR_MOD] & de_ack & ~abnormal[0]) |
(dma_ack[0] & dma_reqs[0]);
`ifdef DMA_HAVE_CH1
assign abnormal[1] = de_err_notify | c1abt;
assign dmaack_nx[1] = (~dma_ack[1] & ch_sel1 & c1csr[`DMA_CHCSR_MOD] & de_ack & ~abnormal[1]) |
(dma_ack[1] & dma_reqs[1]);
`endif
`ifdef DMA_HAVE_CH2
assign abnormal[2] = de_err_notify | c2abt;
assign dmaack_nx[2] = (~dma_ack[2] & ch_sel2 & c2csr[`DMA_CHCSR_MOD] & de_ack & ~abnormal[2]) |
(dma_ack[2] & dma_reqs[2]);
`endif
`ifdef DMA_HAVE_CH3
assign abnormal[3] = de_err_notify | c3abt;
assign dmaack_nx[3] = (~dma_ack[3] & ch_sel3 & c3csr[`DMA_CHCSR_MOD] & de_ack & ~abnormal[3]) |
(dma_ack[3] & dma_reqs[3]);
`endif
`ifdef DMA_HAVE_CH4
assign abnormal[4] = de_err_notify | c4abt;
assign dmaack_nx[4] = (~dma_ack[4] & ch_sel4 & c4csr[`DMA_CHCSR_MOD] & de_ack & ~abnormal[4]) |
(dma_ack[4] & dma_reqs[4]);
`endif
`ifdef DMA_HAVE_CH5
assign abnormal[5] = de_err_notify | c5abt;
assign dmaack_nx[5] = (~dma_ack[5] & ch_sel5 & c5csr[`DMA_CHCSR_MOD] & de_ack & ~abnormal[5]) |
(dma_ack[5] & dma_reqs[5]);
`endif
`ifdef DMA_HAVE_CH6
assign abnormal[6] = de_err_notify | c6abt;
assign dmaack_nx[6] = (~dma_ack[6] & ch_sel6 & c6csr[`DMA_CHCSR_MOD] & de_ack & ~abnormal[6]) |
(dma_ack[6] & dma_reqs[6]);
`endif
`ifdef DMA_HAVE_CH7
assign abnormal[7] = de_err_notify | c7abt;
assign dmaack_nx[7] = (~dma_ack[7] & ch_sel7 & c7csr[`DMA_CHCSR_MOD] & de_ack & ~abnormal[7]) |
(dma_ack[7] & dma_reqs[7]);
`endif
always @(posedge HCLK or negedge HRSTn)
if(~HRSTn)
dma_ack[0] <= 1'b0;
else
dma_ack[0] <= dmaack_nx[0];
`ifdef DMA_HAVE_CH1
always @(posedge HCLK or negedge HRSTn)
if(~HRSTn)
dma_ack[1] <= 1'b0;
else
dma_ack[1] <= dmaack_nx[1];
`endif
`ifdef DMA_HAVE_CH2
always @(posedge HCLK or negedge HRSTn)
if(~HRSTn)
dma_ack[2] <= 1'b0;
else
dma_ack[2] <= dmaack_nx[2];
`endif
`ifdef DMA_HAVE_CH3
always @(posedge HCLK or negedge HRSTn)
if(~HRSTn)
dma_ack[3] <= 1'b0;
else
dma_ack[3] <= dmaack_nx[3];
`endif
`ifdef DMA_HAVE_CH4
always @(posedge HCLK or negedge HRSTn)
if(~HRSTn)
dma_ack[4] <= 1'b0;
else
dma_ack[4] <= dmaack_nx[4];
`endif
`ifdef DMA_HAVE_CH5
always @(posedge HCLK or negedge HRSTn)
if(~HRSTn)
dma_ack[5] <= 1'b0;
else
dma_ack[5] <= dmaack_nx[5];
`endif
`ifdef DMA_HAVE_CH6
always @(posedge HCLK or negedge HRSTn)
if(~HRSTn)
dma_ack[6] <= 1'b0;
else
dma_ack[6] <= dmaack_nx[6];
`endif
`ifdef DMA_HAVE_CH7
always @(posedge HCLK or negedge HRSTn)
if(~HRSTn)
dma_ack[7] <= 1'b0;
else
dma_ack[7] <= dmaack_nx[7];
`endif
assign ch_sel0 = (arb_ch_sel == 0);
`ifdef DMA_HAVE_CH1
assign ch_sel1 = (arb_ch_sel == 1);
`endif
`ifdef DMA_HAVE_CH2
assign ch_sel2 = (arb_ch_sel == 2);
`endif
`ifdef DMA_HAVE_CH3
assign ch_sel3 = (arb_ch_sel == 3);
`endif
`ifdef DMA_HAVE_CH4
assign ch_sel4 = (arb_ch_sel == 4);
`endif
`ifdef DMA_HAVE_CH5
assign ch_sel5 = (arb_ch_sel == 5);
`endif
`ifdef DMA_HAVE_CH6
assign ch_sel6 = (arb_ch_sel == 6);
`endif
`ifdef DMA_HAVE_CH7
assign ch_sel7 = (arb_ch_sel == 7);
`endif
/*
assign dmatc_nx[0] = (~dma_tc[0] & ch_sel0 & c0csr[`DMA_CHCSR_MOD] & de_tc_st) |
(dma_tc[0] & dma_reqs[0]);
`ifdef DMA_HAVE_CH1
assign dmatc_nx[1] = (~dma_tc[1] & ch_sel1 & c1csr[`DMA_CHCSR_MOD] & de_tc_st) |
(dma_tc[1] & dma_reqs[1]);
`endif
`ifdef DMA_HAVE_CH2
assign dmatc_nx[2] = (~dma_tc[2] & ch_sel2 & c2csr[`DMA_CHCSR_MOD] & de_tc_st) |
(dma_tc[2] & dma_reqs[2]);
`endif
`ifdef DMA_HAVE_CH3
assign dmatc_nx[3] = (~dma_tc[3] & ch_sel3 & c3csr[`DMA_CHCSR_MOD] & de_tc_st) |
(dma_tc[3] & dma_reqs[3]);
`endif
`ifdef DMA_HAVE_CH4
assign dmatc_nx[4] = (~dma_tc[4] & ch_sel4 & c4csr[`DMA_CHCSR_MOD] & de_tc_st) |
(dma_tc[4] & dma_reqs[4]);
`endif
`ifdef DMA_HAVE_CH5
assign dmatc_nx[5] = (~dma_tc[5] & ch_sel5 & c5csr[`DMA_CHCSR_MOD] & de_tc_st) |
(dma_tc[5] & dma_reqs[5]);
`endif
`ifdef DMA_HAVE_CH6
assign dmatc_nx[6] = (~dma_tc[6] & ch_sel6 & c6csr[`DMA_CHCSR_MOD] & de_tc_st) |
(dma_tc[6] & dma_reqs[6]);
`endif
`ifdef DMA_HAVE_CH7
assign dmatc_nx[7] = (~dma_tc[7] & ch_sel7 & c7csr[`DMA_CHCSR_MOD] & de_tc_st) |
(dma_tc[7] & dma_reqs[7]);
`endif
*/
assign dma_tc_st1 = de_ack & tsz_eq0;
assign dmatc_nx[0] = (~dma_tc[0] & ch_sel0 & c0csr[`DMA_CHCSR_MOD] & dma_tc_st1 & ~abnormal[0]) |
(dma_tc[0] & dma_reqs[0]);
`ifdef DMA_HAVE_CH1
assign dmatc_nx[1] = (~dma_tc[1] & ch_sel1 & c1csr[`DMA_CHCSR_MOD] & dma_tc_st1 & ~abnormal[1]) |
(dma_tc[1] & dma_reqs[1]);
`endif
`ifdef DMA_HAVE_CH2
assign dmatc_nx[2] = (~dma_tc[2] & ch_sel2 & c2csr[`DMA_CHCSR_MOD] & dma_tc_st1 & ~abnormal[2]) |
(dma_tc[2] & dma_reqs[2]);
`endif
`ifdef DMA_HAVE_CH3
assign dmatc_nx[3] = (~dma_tc[3] & ch_sel3 & c3csr[`DMA_CHCSR_MOD] & dma_tc_st1 & ~abnormal[3]) |
(dma_tc[3] & dma_reqs[3]);
`endif
`ifdef DMA_HAVE_CH4
assign dmatc_nx[4] = (~dma_tc[4] & ch_sel4 & c4csr[`DMA_CHCSR_MOD] & dma_tc_st1 & ~abnormal[4]) |
(dma_tc[4] & dma_reqs[4]);
`endif
`ifdef DMA_HAVE_CH5
assign dmatc_nx[5] = (~dma_tc[5] & ch_sel5 & c5csr[`DMA_CHCSR_MOD] & dma_tc_st1 & ~abnormal[5]) |
(dma_tc[5] & dma_reqs[5]);
`endif
`ifdef DMA_HAVE_CH6
assign dmatc_nx[6] = (~dma_tc[6] & ch_sel6 & c6csr[`DMA_CHCSR_MOD] & dma_tc_st1 & ~abnormal[6]) |
(dma_tc[6] & dma_reqs[6]);
`endif
`ifdef DMA_HAVE_CH7
assign dmatc_nx[7] = (~dma_tc[7] & ch_sel7 & c7csr[`DMA_CHCSR_MOD] & dma_tc_st1 & ~abnormal[7]) |
(dma_tc[7] & dma_reqs[7]);
`endif
always @(posedge HCLK or negedge HRSTn)
if(~HRSTn)
dma_tc[0] <= 1'b0;
else
dma_tc[0] <= dmatc_nx[0];
`ifdef DMA_HAVE_CH1
always @(posedge HCLK or negedge HRSTn)
if(~HRSTn)
dma_tc[1] <= 1'b0;
else
dma_tc[1] <= dmatc_nx[1];
`endif
`ifdef DMA_HAVE_CH2
always @(posedge HCLK or negedge HRSTn)
if(~HRSTn)
dma_tc[2] <= 1'b0;
else
dma_tc[2] <= dmatc_nx[2];
`endif
`ifdef DMA_HAVE_CH3
always @(posedge HCLK or negedge HRSTn)
if(~HRSTn)
dma_tc[3] <= 1'b0;
else
dma_tc[3] <= dmatc_nx[3];
`endif
`ifdef DMA_HAVE_CH4
always @(posedge HCLK or negedge HRSTn)
if(~HRSTn)
dma_tc[4] <= 1'b0;
else
dma_tc[4] <= dmatc_nx[4];
`endif
`ifdef DMA_HAVE_CH5
always @(posedge HCLK or negedge HRSTn)
if(~HRSTn)
dma_tc[5] <= 1'b0;
else
dma_tc[5] <= dmatc_nx[5];
`endif
`ifdef DMA_HAVE_CH6
always @(posedge HCLK or negedge HRSTn)
if(~HRSTn)
dma_tc[6] <= 1'b0;
else
dma_tc[6] <= dmatc_nx[6];
`endif
`ifdef DMA_HAVE_CH7
always @(posedge HCLK or negedge HRSTn)
if(~HRSTn)
dma_tc[7] <= 1'b0;
else
dma_tc[7] <= dmatc_nx[7];
`endif
always @(arb_ch_sel or c0csr
`ifdef DMA_HAVE_CH1
or c1csr
`endif
`ifdef DMA_HAVE_CH2
or c2csr
`endif
`ifdef DMA_HAVE_CH3
or c3csr
`endif
`ifdef DMA_HAVE_CH4
or c4csr
`endif
`ifdef DMA_HAVE_CH5
or c5csr
`endif
`ifdef DMA_HAVE_CH6
or c6csr
`endif
`ifdef DMA_HAVE_CH7
or c7csr
`endif
)
case(arb_ch_sel)
3'h0: arb_chcsri = c0csr;
`ifdef DMA_HAVE_CH1
3'h1: arb_chcsri = c1csr;
`endif
`ifdef DMA_HAVE_CH2
3'h2: arb_chcsri = c2csr;
`endif
`ifdef DMA_HAVE_CH3
3'h3: arb_chcsri = c3csr;
`endif
`ifdef DMA_HAVE_CH4
3'h4: arb_chcsri = c4csr;
`endif
`ifdef DMA_HAVE_CH5
3'h5: arb_chcsri = c5csr;
`endif
`ifdef DMA_HAVE_CH6
3'h6: arb_chcsri = c6csr;
`endif
`ifdef DMA_HAVE_CH7
3'h7: arb_chcsri = c7csr;
`endif
default:
arb_chcsri = 0;
endcase
always @(posedge HCLK or negedge HRSTn)
if(~HRSTn)
arb_chcsr_reg <= 0;
else
arb_chcsr_reg <= {arb_chcsri[31],arb_chcsri[24:16],arb_chcsri[14:0]};
wire [`DMA_CHCSR_WIDTH-1:0] arb_chcsr = {arb_chcsr_reg[24],6'b0,arb_chcsr_reg[23:15],1'b0,arb_chcsr_reg[14:0]};
always @(arb_ch_sel or c0sad
`ifdef DMA_HAVE_CH1
or c1sad
`endif
`ifdef DMA_HAVE_CH2
or c2sad
`endif
`ifdef DMA_HAVE_CH3
or c3sad
`endif
`ifdef DMA_HAVE_CH4
or c4sad
`endif
`ifdef DMA_HAVE_CH5
or c5sad
`endif
`ifdef DMA_HAVE_CH6
or c6sad
`endif
`ifdef DMA_HAVE_CH7
or c7sad
`endif
)
case(arb_ch_sel)
3'h0: arb_chsad = c0sad;
`ifdef DMA_HAVE_CH1
3'h1: arb_chsad = c1sad;
`endif
`ifdef DMA_HAVE_CH2
3'h2: arb_chsad = c2sad;
`endif
`ifdef DMA_HAVE_CH3
3'h3: arb_chsad = c3sad;
`endif
`ifdef DMA_HAVE_CH4
3'h4: arb_chsad = c4sad;
`endif
`ifdef DMA_HAVE_CH5
3'h5: arb_chsad = c5sad;
`endif
`ifdef DMA_HAVE_CH6
3'h6: arb_chsad = c6sad;
`endif
`ifdef DMA_HAVE_CH7
3'h7: arb_chsad = c7sad;
`endif
default: arb_chsad = 0;
endcase
always @(arb_ch_sel or c0dad
`ifdef DMA_HAVE_CH1
or c1dad
`endif
`ifdef DMA_HAVE_CH2
or c2dad
`endif
`ifdef DMA_HAVE_CH3
or c3dad
`endif
`ifdef DMA_HAVE_CH4
or c4dad
`endif
`ifdef DMA_HAVE_CH5
or c5dad
`endif
`ifdef DMA_HAVE_CH6
or c6dad
`endif
`ifdef DMA_HAVE_CH7
or c7dad
`endif
)
case(arb_ch_sel)
3'h0: arb_chdad = c0dad;
`ifdef DMA_HAVE_CH1
3'h1: arb_chdad = c1dad;
`endif
`ifdef DMA_HAVE_CH2
3'h2: arb_chdad = c2dad;
`endif
`ifdef DMA_HAVE_CH3
3'h3: arb_chdad = c3dad;
`endif
`ifdef DMA_HAVE_CH4
3'h4: arb_chdad = c4dad;
`endif
`ifdef DMA_HAVE_CH5
3'h5: arb_chdad = c5dad;
`endif
`ifdef DMA_HAVE_CH6
3'h6: arb_chdad = c6dad;
`endif
`ifdef DMA_HAVE_CH7
3'h7: arb_chdad = c7dad;
`endif
default: arb_chdad = 0;
endcase
`ifdef DMA_HAVE_LINKLIST
always @(arb_ch_sel or c0llp
`ifdef DMA_HAVE_CH1
or c1llp
`endif
`ifdef DMA_HAVE_CH2
or c2llp
`endif
`ifdef DMA_HAVE_CH3
or c3llp
`endif
`ifdef DMA_HAVE_CH4
or c4llp
`endif
`ifdef DMA_HAVE_CH5
or c5llp
`endif
`ifdef DMA_HAVE_CH6
or c6llp
`endif
`ifdef DMA_HAVE_CH7
or c7llp
`endif
)
case(arb_ch_sel)
3'h0: arb_chllp = c0llp;
`ifdef DMA_HAVE_CH1
3'h1: arb_chllp = c1llp;
`endif
`ifdef DMA_HAVE_CH2
3'h2: arb_chllp = c2llp;
`endif
`ifdef DMA_HAVE_CH3
3'h3: arb_chllp = c3llp;
`endif
`ifdef DMA_HAVE_CH4
3'h4: arb_chllp = c4llp;
`endif
`ifdef DMA_HAVE_CH5
3'h5: arb_chllp = c5llp;
`endif
`ifdef DMA_HAVE_CH6
3'h6: arb_chllp = c6llp;
`endif
`ifdef DMA_HAVE_CH7
3'h7: arb_chllp = c7llp;
`endif
default: arb_chllp = 0;
endcase
`endif
always @(arb_ch_sel or c0tsz
`ifdef DMA_HAVE_CH1
or c1tsz
`endif
`ifdef DMA_HAVE_CH2
or c2tsz
`endif
`ifdef DMA_HAVE_CH3
or c3tsz
`endif
`ifdef DMA_HAVE_CH4
or c4tsz
`endif
`ifdef DMA_HAVE_CH5
or c5tsz
`endif
`ifdef DMA_HAVE_CH6
or c6tsz
`endif
`ifdef DMA_HAVE_CH7
or c7tsz
`endif
)
case(arb_ch_sel)
3'h0: arb_chtsz = c0tsz;
`ifdef DMA_HAVE_CH1
3'h1: arb_chtsz = c1tsz;
`endif
`ifdef DMA_HAVE_CH2
3'h2: arb_chtsz = c2tsz;
`endif
`ifdef DMA_HAVE_CH3
3'h3: arb_chtsz = c3tsz;
`endif
`ifdef DMA_HAVE_CH4
3'h4: arb_chtsz = c4tsz;
`endif
`ifdef DMA_HAVE_CH5
3'h5: arb_chtsz = c5tsz;
`endif
`ifdef DMA_HAVE_CH6
3'h6: arb_chtsz = c6tsz;
`endif
`ifdef DMA_HAVE_CH7
3'h7: arb_chtsz = c7tsz;
`endif
default: arb_chtsz = 0;
endcase
assign arb_abt_any = c0abt
`ifdef DMA_HAVE_CH1
| c1abt
`endif
`ifdef DMA_HAVE_CH2
| c2abt
`endif
`ifdef DMA_HAVE_CH3
| c3abt
`endif
`ifdef DMA_HAVE_CH4
| c4abt
`endif
`ifdef DMA_HAVE_CH5
| c5abt
`endif
`ifdef DMA_HAVE_CH6
| c6abt
`endif
`ifdef DMA_HAVE_CH7
| c7abt
`endif
;
always @(arb_ch_sel or c0abt
`ifdef DMA_HAVE_CH1
or c1abt
`endif
`ifdef DMA_HAVE_CH2
or c2abt
`endif
`ifdef DMA_HAVE_CH3
or c3abt
`endif
`ifdef DMA_HAVE_CH4
or c4abt
`endif
`ifdef DMA_HAVE_CH5
or c5abt
`endif
`ifdef DMA_HAVE_CH6
or c6abt
`endif
`ifdef DMA_HAVE_CH7
or c7abt
`endif
)
case(arb_ch_sel)
3'h0: arb_chabt = c0abt;
`ifdef DMA_HAVE_CH1
3'h1: arb_chabt = c1abt;
`endif
`ifdef DMA_HAVE_CH2
3'h2: arb_chabt = c2abt;
`endif
`ifdef DMA_HAVE_CH3
3'h3: arb_chabt = c3abt;
`endif
`ifdef DMA_HAVE_CH4
3'h4: arb_chabt = c4abt;
`endif
`ifdef DMA_HAVE_CH5
3'h5: arb_chabt = c5abt;
`endif
`ifdef DMA_HAVE_CH6
3'h6: arb_chabt = c6abt;
`endif
`ifdef DMA_HAVE_CH7
3'h7: arb_chabt = c7abt;
`endif
default: arb_chabt = 0;
endcase
`ifdef DMA_HAVE_LINKLIST
always @(arb_ch_sel or c0llpen
`ifdef DMA_HAVE_CH1
or c1llpen
`endif
`ifdef DMA_HAVE_CH2
or c2llpen
`endif
`ifdef DMA_HAVE_CH3
or c3llpen
`endif
`ifdef DMA_HAVE_CH4
or c4llpen
`endif
`ifdef DMA_HAVE_CH5
or c5llpen
`endif
`ifdef DMA_HAVE_CH6
or c6llpen
`endif
`ifdef DMA_HAVE_CH7
or c7llpen
`endif
)
case(arb_ch_sel)
3'h0: arb_chllpen = c0llpen;
`ifdef DMA_HAVE_CH1
3'h1: arb_chllpen = c1llpen;
`endif
`ifdef DMA_HAVE_CH2
3'h2: arb_chllpen = c2llpen;
`endif
`ifdef DMA_HAVE_CH3
3'h3: arb_chllpen = c3llpen;
`endif
`ifdef DMA_HAVE_CH4
3'h4: arb_chllpen = c4llpen;
`endif
`ifdef DMA_HAVE_CH5
3'h5: arb_chllpen = c5llpen;
`endif
`ifdef DMA_HAVE_CH6
3'h6: arb_chllpen = c6llpen;
`endif
`ifdef DMA_HAVE_CH7
3'h7: arb_chllpen = c7llpen;
`endif
default: arb_chllpen = 0;
endcase
`endif
assign vld_req_p0[0] = vld_req[0] & (ch0pri=='h0);
`ifdef DMA_HAVE_CH1
assign vld_req_p0[1] = vld_req[1] & (ch1pri=='h0);
`endif
`ifdef DMA_HAVE_CH2
assign vld_req_p0[2] = vld_req[2] & (ch2pri=='h0);
`endif
`ifdef DMA_HAVE_CH3
assign vld_req_p0[3] = vld_req[3] & (ch3pri=='h0);
`endif
`ifdef DMA_HAVE_CH4
assign vld_req_p0[4] = vld_req[4] & (ch4pri=='h0);
`endif
`ifdef DMA_HAVE_CH5
assign vld_req_p0[5] = vld_req[5] & (ch5pri=='h0);
`endif
`ifdef DMA_HAVE_CH6
assign vld_req_p0[6] = vld_req[6] & (ch6pri=='h0);
`endif
`ifdef DMA_HAVE_CH7
assign vld_req_p0[7] = vld_req[7] & (ch7pri=='h0);
`endif
assign vld_req_p1[0] = vld_req[0] & (ch0pri=='h1);
`ifdef DMA_HAVE_CH1
assign vld_req_p1[1] = vld_req[1] & (ch1pri=='h1);
`endif
`ifdef DMA_HAVE_CH2
assign vld_req_p1[2] = vld_req[2] & (ch2pri=='h1);
`endif
`ifdef DMA_HAVE_CH3
assign vld_req_p1[3] = vld_req[3] & (ch3pri=='h1);
`endif
`ifdef DMA_HAVE_CH4
assign vld_req_p1[4] = vld_req[4] & (ch4pri=='h1);
`endif
`ifdef DMA_HAVE_CH5
assign vld_req_p1[5] = vld_req[5] & (ch5pri=='h1);
`endif
`ifdef DMA_HAVE_CH6
assign vld_req_p1[6] = vld_req[6] & (ch6pri=='h1);
`endif
`ifdef DMA_HAVE_CH7
assign vld_req_p1[7] = vld_req[7] & (ch7pri=='h1);
`endif
assign vld_req_p2[0] = vld_req[0] & (ch0pri=='h2);
`ifdef DMA_HAVE_CH1
assign vld_req_p2[1] = vld_req[1] & (ch1pri=='h2);
`endif
`ifdef DMA_HAVE_CH2
assign vld_req_p2[2] = vld_req[2] & (ch2pri=='h2);
`endif
`ifdef DMA_HAVE_CH3
assign vld_req_p2[3] = vld_req[3] & (ch3pri=='h2);
`endif
`ifdef DMA_HAVE_CH4
assign vld_req_p2[4] = vld_req[4] & (ch4pri=='h2);
`endif
`ifdef DMA_HAVE_CH5
assign vld_req_p2[5] = vld_req[5] & (ch5pri=='h2);
`endif
`ifdef DMA_HAVE_CH6
assign vld_req_p2[6] = vld_req[6] & (ch6pri=='h2);
`endif
`ifdef DMA_HAVE_CH7
assign vld_req_p2[7] = vld_req[7] & (ch7pri=='h2);
`endif
assign vld_req_p3[0] = vld_req[0] & (ch0pri=='h3);
`ifdef DMA_HAVE_CH1
assign vld_req_p3[1] = vld_req[1] & (ch1pri=='h3);
`endif
`ifdef DMA_HAVE_CH2
assign vld_req_p3[2] = vld_req[2] & (ch2pri=='h3);
`endif
`ifdef DMA_HAVE_CH3
assign vld_req_p3[3] = vld_req[3] & (ch3pri=='h3);
`endif
`ifdef DMA_HAVE_CH4
assign vld_req_p3[4] = vld_req[4] & (ch4pri=='h3);
`endif
`ifdef DMA_HAVE_CH5
assign vld_req_p3[5] = vld_req[5] & (ch5pri=='h3);
`endif
`ifdef DMA_HAVE_CH6
assign vld_req_p3[6] = vld_req[6] & (ch6pri=='h3);
`endif
`ifdef DMA_HAVE_CH7
assign vld_req_p3[7] = vld_req[7] & (ch7pri=='h3);
`endif
dma_rrarb dma_rrarb0(
.HCLK(HCLK),
.HRSTn(HRSTn),
.vld_req(vld_req_p0),
.gnt_chno(gnt_p0),
.next_ch(next_ch)
);
dma_rrarb dma_rrarb1(
.HCLK(HCLK),
.HRSTn(HRSTn),
.vld_req(vld_req_p1),
.gnt_chno(gnt_p1),
.next_ch(next_ch)
);
dma_rrarb dma_rrarb2(
.HCLK(HCLK),
.HRSTn(HRSTn),
.vld_req(vld_req_p2),
.gnt_chno(gnt_p2),
.next_ch(next_ch)
);
dma_rrarb dma_rrarb3(
.HCLK(HCLK),
.HRSTn(HRSTn),
.vld_req(vld_req_p3),
.gnt_chno(gnt_p3),
.next_ch(next_ch)
);
endmodule
|
`include "DMA_DEFINE.vh"
module dma_ctlrf
(
HCLK,
HRSTn,
slv_ad,
slv_ad_d1,
slv_wdti,
slv_sz,
slv_wr_d1,
slv_rf_sel,
de_st_idle,
de_st_upd,
de_st_llp0,
de_sad_we,
de_dad_we,
`ifdef DMA_HAVE_LINKLIST
de_llp_we,
`endif
de_tsz_we,
de_en_clr,
`ifdef DMA_HAVE_LINKLIST
de_csr_we,
de_llpen_we,
`endif
de_err_notify,
tsz_eq0,
de_tc_st,
de_sad,
de_dad,
`ifdef DMA_HAVE_LINKLIST
de_llp,
`endif
de_tsz,
de_csr,
`ifdef DMA_HAVE_LINKLIST
de_llpen,
`endif
de_busy,
arb_ch_sel,
rf_cherr,
rf_dto,
dmaint, dmaint_tc, dmaint_err, csr, sync,
err,
c0csr, c0cfg, c0sad, c0dad,
`ifdef DMA_HAVE_LINKLIST
c0llp,
`endif
c0tsz,
`ifdef DMA_HAVE_AHB1
`ifdef DMA_HAVE_BRIDGE
c0dmabs, c0brbs,
`endif
`endif
`ifdef DMA_HAVE_LINKLIST
c0llpen,
`endif
c0abt
`ifdef DMA_HAVE_CH1
,c1csr, c1cfg, c1sad, c1dad,
`ifdef DMA_HAVE_LINKLIST
c1llp,
`endif
c1tsz,
`ifdef DMA_HAVE_AHB1
`ifdef DMA_HAVE_BRIDGE
c1dmabs, c1brbs,
`endif
`endif
`ifdef DMA_HAVE_LINKLIST
c1llpen,
`endif
c1abt
`endif
`ifdef DMA_HAVE_CH2
,c2csr, c2cfg, c2sad, c2dad,
`ifdef DMA_HAVE_LINKLIST
c2llp,
`endif
c2tsz,
`ifdef DMA_HAVE_AHB1
`ifdef DMA_HAVE_BRIDGE
c2dmabs, c2brbs,
`endif
`endif
`ifdef DMA_HAVE_LINKLIST
c2llpen,
`endif
c2abt
`endif
`ifdef DMA_HAVE_CH3
,c3csr, c3cfg, c3sad, c3dad,
`ifdef DMA_HAVE_LINKLIST
c3llp,
`endif
c3tsz,
`ifdef DMA_HAVE_AHB1
`ifdef DMA_HAVE_BRIDGE
c3dmabs, c3brbs,
`endif
`endif
`ifdef DMA_HAVE_LINKLIST
c3llpen,
`endif
c3abt
`endif
`ifdef DMA_HAVE_CH4
,c4csr, c4cfg, c4sad, c4dad,
`ifdef DMA_HAVE_LINKLIST
c4llp,
`endif
c4tsz,
`ifdef DMA_HAVE_AHB1
`ifdef DMA_HAVE_BRIDGE
c4dmabs, c4brbs,
`endif
`endif
`ifdef DMA_HAVE_LINKLIST
c4llpen,
`endif
c4abt
`endif
`ifdef DMA_HAVE_CH5
,c5csr, c5cfg, c5sad, c5dad,
`ifdef DMA_HAVE_LINKLIST
c5llp,
`endif
c5tsz,
`ifdef DMA_HAVE_AHB1
`ifdef DMA_HAVE_BRIDGE
c5dmabs, c5brbs,
`endif
`endif
`ifdef DMA_HAVE_LINKLIST
c5llpen,
`endif
c5abt
`endif
`ifdef DMA_HAVE_CH6
,c6csr, c6cfg, c6sad, c6dad,
`ifdef DMA_HAVE_LINKLIST
c6llp,
`endif
c6tsz,
`ifdef DMA_HAVE_AHB1
`ifdef DMA_HAVE_BRIDGE
c6dmabs, c6brbs,
`endif
`endif
`ifdef DMA_HAVE_LINKLIST
c6llpen,
`endif
c6abt
`endif
`ifdef DMA_HAVE_CH7
,c7csr, c7cfg, c7sad, c7dad,
`ifdef DMA_HAVE_LINKLIST
c7llp,
`endif
c7tsz,
`ifdef DMA_HAVE_AHB1
`ifdef DMA_HAVE_BRIDGE
c7dmabs, c7brbs,
`endif
`endif
`ifdef DMA_HAVE_LINKLIST
c7llpen,
`endif
c7abt
`endif
);
input HCLK;
input HRSTn;
input [`DMA_HADDR_WIDTH-1:0] slv_ad;
input [`DMA_HADDR_WIDTH-1:0] slv_ad_d1;
input [`DMA_HDATA_WIDTH-1:0] slv_wdti;
input [`DMA_HSIZE_WIDTH-1:0] slv_sz;
input slv_wr_d1;
input slv_rf_sel;
input de_st_idle;
input de_st_upd;
input de_st_llp0;
input de_sad_we;
input de_dad_we;
`ifdef DMA_HAVE_LINKLIST
input de_llp_we;
`endif
input de_tsz_we;
input de_en_clr;
`ifdef DMA_HAVE_LINKLIST
input de_csr_we;
input de_llpen_we;
`endif
input de_err_notify;
input tsz_eq0;
input de_tc_st;
input [`DMA_HADDR_WIDTH-1:0] de_sad;
input [`DMA_HADDR_WIDTH-1:0] de_dad;
`ifdef DMA_HAVE_LINKLIST
input [`DMA_HADDR_WIDTH-1:0] de_llp;
`endif
input [`DMA_CHSZ_WIDTH-1:0] de_tsz;
input [`DMA_HDATA_WIDTH-1:0] de_csr;
`ifdef DMA_HAVE_LINKLIST
input de_llpen;
`endif
input de_busy;
input [`DMA_CHNO_WIDTH-1:0] arb_ch_sel;
output rf_cherr;
output [`DMA_HDATA_WIDTH-1:0] rf_dto;
output dmaint;
output dmaint_tc;
output dmaint_err;
output [`DMA_CSR_WIDTH-1:0] csr;
output [`DMA_MAX_CHNO-1:0] sync;
output [`DMA_MAX_CHNO-1:0] err;
output [`DMA_CHCSR_WIDTH-1:0] c0csr;
output [`DMA_CHCFG_WIDTH-1:0] c0cfg;
output [`DMA_HADDR_WIDTH-1:0] c0sad;
output [`DMA_HADDR_WIDTH-1:0] c0dad;
`ifdef DMA_HAVE_LINKLIST
output [`DMA_HADDR_WIDTH-1:0] c0llp;
`endif
output [`DMA_CHSZ_WIDTH-1:0] c0tsz;
`ifdef DMA_HAVE_AHB1
`ifdef DMA_HAVE_BRIDGE
output [31:16] c0dmabs;
output [31:16] c0brbs;
`endif
`endif
output c0abt;
`ifdef DMA_HAVE_LINKLIST
output c0llpen;
`endif
`ifdef DMA_HAVE_CH1
output [`DMA_CHCSR_WIDTH-1:0] c1csr;
output [`DMA_CHCFG_WIDTH-1:0] c1cfg;
output [`DMA_HADDR_WIDTH-1:0] c1sad;
output [`DMA_HADDR_WIDTH-1:0] c1dad;
`ifdef DMA_HAVE_LINKLIST
output [`DMA_HADDR_WIDTH-1:0] c1llp;
`endif
output [`DMA_CHSZ_WIDTH-1:0] c1tsz;
`ifdef DMA_HAVE_AHB1
`ifdef DMA_HAVE_BRIDGE
output [31:16] c1dmabs;
output [31:16] c1brbs;
`endif
`endif
output c1abt;
`ifdef DMA_HAVE_LINKLIST
output c1llpen;
`endif
`endif
`ifdef DMA_HAVE_CH2
output [`DMA_CHCSR_WIDTH-1:0] c2csr;
output [`DMA_CHCFG_WIDTH-1:0] c2cfg;
output [`DMA_HADDR_WIDTH-1:0] c2sad;
output [`DMA_HADDR_WIDTH-1:0] c2dad;
`ifdef DMA_HAVE_LINKLIST
output [`DMA_HADDR_WIDTH-1:0] c2llp;
`endif
output [`DMA_CHSZ_WIDTH-1:0] c2tsz;
`ifdef DMA_HAVE_AHB1
`ifdef DMA_HAVE_BRIDGE
output [31:16] c2dmabs;
output [31:16] c2brbs;
`endif
`endif
output c2abt;
`ifdef DMA_HAVE_LINKLIST
output c2llpen;
`endif
`endif
`ifdef DMA_HAVE_CH3
output [`DMA_CHCSR_WIDTH-1:0] c3csr;
output [`DMA_CHCFG_WIDTH-1:0] c3cfg;
output [`DMA_HADDR_WIDTH-1:0] c3sad;
output [`DMA_HADDR_WIDTH-1:0] c3dad;
`ifdef DMA_HAVE_LINKLIST
output [`DMA_HADDR_WIDTH-1:0] c3llp;
`endif
output [`DMA_CHSZ_WIDTH-1:0] c3tsz;
`ifdef DMA_HAVE_AHB1
`ifdef DMA_HAVE_BRIDGE
output [31:16] c3dmabs;
output [31:16] c3brbs;
`endif
`endif
output c3abt;
`ifdef DMA_HAVE_LINKLIST
output c3llpen;
`endif
`endif
`ifdef DMA_HAVE_CH4
output [`DMA_CHCSR_WIDTH-1:0] c4csr;
output [`DMA_CHCFG_WIDTH-1:0] c4cfg;
output [`DMA_HADDR_WIDTH-1:0] c4sad;
output [`DMA_HADDR_WIDTH-1:0] c4dad;
`ifdef DMA_HAVE_LINKLIST
output [`DMA_HADDR_WIDTH-1:0] c4llp;
`endif
output [`DMA_CHSZ_WIDTH-1:0] c4tsz;
`ifdef DMA_HAVE_AHB1
`ifdef DMA_HAVE_BRIDGE
output [31:16] c4dmabs;
output [31:16] c4brbs;
`endif
`endif
output c4abt;
`ifdef DMA_HAVE_LINKLIST
output c4llpen;
`endif
`endif
`ifdef DMA_HAVE_CH5
output [`DMA_CHCSR_WIDTH-1:0] c5csr;
output [`DMA_CHCFG_WIDTH-1:0] c5cfg;
output [`DMA_HADDR_WIDTH-1:0] c5sad;
output [`DMA_HADDR_WIDTH-1:0] c5dad;
`ifdef DMA_HAVE_LINKLIST
output [`DMA_HADDR_WIDTH-1:0] c5llp;
`endif
output [`DMA_CHSZ_WIDTH-1:0] c5tsz;
`ifdef DMA_HAVE_AHB1
`ifdef DMA_HAVE_BRIDGE
output [31:16] c5dmabs;
output [31:16] c5brbs;
`endif
`endif
output c5abt;
`ifdef DMA_HAVE_LINKLIST
output c5llpen;
`endif
`endif
`ifdef DMA_HAVE_CH6
output [`DMA_CHCSR_WIDTH-1:0] c6csr;
output [`DMA_CHCFG_WIDTH-1:0] c6cfg;
output [`DMA_HADDR_WIDTH-1:0] c6sad;
output [`DMA_HADDR_WIDTH-1:0] c6dad;
`ifdef DMA_HAVE_LINKLIST
output [`DMA_HADDR_WIDTH-1:0] c6llp;
`endif
output [`DMA_CHSZ_WIDTH-1:0] c6tsz;
`ifdef DMA_HAVE_AHB1
`ifdef DMA_HAVE_BRIDGE
output [31:16] c6dmabs;
output [31:16] c6brbs;
`endif
`endif
output c6abt;
`ifdef DMA_HAVE_LINKLIST
output c6llpen;
`endif
`endif
`ifdef DMA_HAVE_CH7
output [`DMA_CHCSR_WIDTH-1:0] c7csr;
output [`DMA_CHCFG_WIDTH-1:0] c7cfg;
output [`DMA_HADDR_WIDTH-1:0] c7sad;
output [`DMA_HADDR_WIDTH-1:0] c7dad;
`ifdef DMA_HAVE_LINKLIST
output [`DMA_HADDR_WIDTH-1:0] c7llp;
`endif
output [`DMA_CHSZ_WIDTH-1:0] c7tsz;
`ifdef DMA_HAVE_AHB1
`ifdef DMA_HAVE_BRIDGE
output [31:16] c7dmabs;
output [31:16] c7brbs;
`endif
`endif
output c7abt;
`ifdef DMA_HAVE_LINKLIST
output c7llpen;
`endif
`endif
wire be0,be1,be2,be3;
wire dma_chrfsel;
wire sel_tc_clr;
wire sel_err_clr;
wire sel_csr, csr_we;
wire sel_sync, sync_we;
wire [`DMA_MAX_CHNO-1:0] tc_clr;
wire [`DMA_MAX_CHNO-1:0] tc_st;
wire [`DMA_MAX_CHNO-1:0] err_clr;
wire [`DMA_MAX_CHNO-1:0] abt_clr;
wire [`DMA_MAX_CHNO-1:0] err_st;
wire [`DMA_MAX_CHNO-1:0] abt_st;
wire [7:0] ch_en;
wire [7:0] ch_busy;
wire [`DMA_MAX_CHNO-1:0] int;
wire [`DMA_MAX_CHNO-1:0] int_tc;
wire [`DMA_MAX_CHNO-1:0] int_err;
wire [`DMA_MAX_CHNO-1:0] int_abt;
wire intin,inttcin,interrin,intabtin;
wire c0csr_we, c0cfg_we, c0sad_we, c0dad_we;
`ifdef DMA_HAVE_LINKLIST
wire c0llp_we;
`endif
wire c0tsz_we;
wire c0abt;
`ifdef DMA_HAVE_AHB1
`ifdef DMA_HAVE_BRIDGE
wire c0dbs_we;
wire c0bbs_we;
`endif
`endif
`ifdef DMA_HAVE_CH1
wire c1csr_we, c1cfg_we, c1sad_we, c1dad_we;
`ifdef DMA_HAVE_LINKLIST
wire c1llp_we;
`endif
wire c1tsz_we;
wire c1abt;
`ifdef DMA_HAVE_AHB1
`ifdef DMA_HAVE_BRIDGE
wire c1dbs_we;
wire c1bbs_we;
`endif
`endif
`endif
`ifdef DMA_HAVE_CH2
wire c2csr_we, c2cfg_we, c2sad_we, c2dad_we;
`ifdef DMA_HAVE_LINKLIST
wire c2llp_we;
`endif
wire c2tsz_we;
wire c2abt;
`ifdef DMA_HAVE_AHB1
`ifdef DMA_HAVE_BRIDGE
wire c2dbs_we;
wire c2bbs_we;
`endif
`endif
`endif
`ifdef DMA_HAVE_CH3
wire c3csr_we, c3cfg_we, c3sad_we, c3dad_we;
`ifdef DMA_HAVE_LINKLIST
wire c3llp_we;
`endif
wire c3tsz_we;
wire c3abt;
`ifdef DMA_HAVE_AHB1
`ifdef DMA_HAVE_BRIDGE
wire c3dbs_we;
wire c3bbs_we;
`endif
`endif
`endif
`ifdef DMA_HAVE_CH4
wire c4csr_we, c4cfg_we, c4sad_we, c4dad_we;
`ifdef DMA_HAVE_LINKLIST
wire c4llp_we;
`endif
wire c4tsz_we;
wire c4abt;
`ifdef DMA_HAVE_AHB1
`ifdef DMA_HAVE_BRIDGE
wire c4dbs_we;
wire c4bbs_we;
`endif
`endif
`endif
`ifdef DMA_HAVE_CH5
wire c5csr_we, c5cfg_we, c5sad_we, c5dad_we;
`ifdef DMA_HAVE_LINKLIST
wire c5llp_we;
`endif
wire c5tsz_we;
wire c5abt;
`ifdef DMA_HAVE_AHB1
`ifdef DMA_HAVE_BRIDGE
wire c5dbs_we;
wire c5bbs_we;
`endif
`endif
`endif
`ifdef DMA_HAVE_CH6
wire c6csr_we, c6cfg_we, c6sad_we, c6dad_we;
`ifdef DMA_HAVE_LINKLIST
wire c6llp_we;
`endif
wire c6tsz_we;
wire c6abt;
`ifdef DMA_HAVE_AHB1
`ifdef DMA_HAVE_BRIDGE
wire c6dbs_we;
wire c6bbs_we;
`endif
`endif
`endif
`ifdef DMA_HAVE_CH7
wire c7csr_we, c7cfg_we, c7sad_we, c7dad_we;
`ifdef DMA_HAVE_LINKLIST
wire c7llp_we;
`endif
wire c7tsz_we;
wire c7abt;
`ifdef DMA_HAVE_AHB1
`ifdef DMA_HAVE_BRIDGE
wire c7dbs_we;
wire c7bbs_we;
`endif
`endif
`endif
wire sel_c0csr, sel_c0cfg, sel_c0sad, sel_c0dad;
`ifdef DMA_HAVE_LINKLIST
wire sel_c0llp;
`endif
wire sel_c0tsz;
`ifdef DMA_HAVE_AHB1
`ifdef DMA_HAVE_BRIDGE
wire sel_c0dbs;
wire sel_c0bbs;
`endif
`endif
`ifdef DMA_HAVE_CH1
wire sel_c1csr, sel_c1cfg, sel_c1sad, sel_c1dad;
`ifdef DMA_HAVE_LINKLIST
wire sel_c1llp;
`endif
wire sel_c1tsz;
`ifdef DMA_HAVE_AHB1
`ifdef DMA_HAVE_BRIDGE
wire sel_c1dbs;
wire sel_c1bbs;
`endif
`endif
`endif
`ifdef DMA_HAVE_CH2
wire sel_c2csr, sel_c2cfg, sel_c2sad, sel_c2dad;
`ifdef DMA_HAVE_LINKLIST
wire sel_c2llp;
`endif
wire sel_c2tsz;
`ifdef DMA_HAVE_AHB1
`ifdef DMA_HAVE_BRIDGE
wire sel_c2dbs;
wire sel_c2bbs;
`endif
`endif
`endif
`ifdef DMA_HAVE_CH3
wire sel_c3csr, sel_c3cfg, sel_c3sad, sel_c3dad;
`ifdef DMA_HAVE_LINKLIST
wire sel_c3llp;
`endif
wire sel_c3tsz;
`ifdef DMA_HAVE_AHB1
`ifdef DMA_HAVE_BRIDGE
wire sel_c3dbs;
wire sel_c3bbs;
`endif
`endif
`endif
`ifdef DMA_HAVE_CH4
wire sel_c4csr, sel_c4cfg, sel_c4sad, sel_c4dad;
`ifdef DMA_HAVE_LINKLIST
wire sel_c4llp;
`endif
wire sel_c4tsz;
`ifdef DMA_HAVE_AHB1
`ifdef DMA_HAVE_BRIDGE
wire sel_c4dbs;
wire sel_c4bbs;
`endif
`endif
`endif
`ifdef DMA_HAVE_CH5
wire sel_c5csr, sel_c5cfg, sel_c5sad, sel_c5dad;
`ifdef DMA_HAVE_LINKLIST
wire sel_c5llp;
`endif
wire sel_c5tsz;
`ifdef DMA_HAVE_AHB1
`ifdef DMA_HAVE_BRIDGE
wire sel_c5dbs;
wire sel_c5bbs;
`endif
`endif
`endif
`ifdef DMA_HAVE_CH6
wire sel_c6csr, sel_c6cfg, sel_c6sad, sel_c6dad;
`ifdef DMA_HAVE_LINKLIST
wire sel_c6llp;
`endif
wire sel_c6tsz;
`ifdef DMA_HAVE_AHB1
`ifdef DMA_HAVE_BRIDGE
wire sel_c6dbs;
wire sel_c6bbs;
`endif
`endif
`endif
`ifdef DMA_HAVE_CH7
wire sel_c7csr, sel_c7cfg, sel_c7sad, sel_c7dad;
`ifdef DMA_HAVE_LINKLIST
wire sel_c7llp;
`endif
wire sel_c7tsz;
`ifdef DMA_HAVE_AHB1
`ifdef DMA_HAVE_BRIDGE
wire sel_c7dbs;
wire sel_c7bbs;
`endif
`endif
`endif
`ifdef DMA_HAVE_LINKLIST
`else
wire de_csr_we = 0;
`endif
`ifdef DMA_HAVE_AHB1
`ifdef DMA_HAVE_BRIDGE
reg [31:16] mux_dbs;
reg [31:16] mux_bbs;
`endif
`endif
reg [31:0] mux_ms;
reg [31:0] mux_gl;
reg [`DMA_HDATA_WIDTH-1:0] mux_ch;
reg [`DMA_HDATA_WIDTH-1:0] mux_c0l,mux_c0h;
`ifdef DMA_HAVE_CH1
reg [`DMA_HDATA_WIDTH-1:0] mux_c1l,mux_c1h;
`endif
`ifdef DMA_HAVE_CH2
reg [`DMA_HDATA_WIDTH-1:0] mux_c2l,mux_c2h;
`endif
`ifdef DMA_HAVE_CH3
reg [`DMA_HDATA_WIDTH-1:0] mux_c3l,mux_c3h;
`endif
`ifdef DMA_HAVE_CH4
reg [`DMA_HDATA_WIDTH-1:0] mux_c4l,mux_c4h;
`endif
`ifdef DMA_HAVE_CH5
reg [`DMA_HDATA_WIDTH-1:0] mux_c5l,mux_c5h;
`endif
`ifdef DMA_HAVE_CH6
reg [`DMA_HDATA_WIDTH-1:0] mux_c6l,mux_c6h;
`endif
`ifdef DMA_HAVE_CH7
reg [`DMA_HDATA_WIDTH-1:0] mux_c7l,mux_c7h;
`endif
reg dmaint;
reg dmaint_tc;
reg dmaint_err;
reg [`DMA_MAX_CHNO-1:0] err;
reg [`DMA_MAX_CHNO-1:0] abt;
reg [`DMA_MAX_CHNO-1:0] tc;
reg m1end;
reg m0end;
reg dmacen;
reg [`DMA_MAX_CHNO-1:0] sync;
reg [3:0] be_d1;
reg rf_sel_d1;
reg rf_cherr;
wire [`DMA_CHCSR_WIDTH-1:0] c0csr;
wire [`DMA_CHCFG_WIDTH-1:0] c0cfg;
wire [`DMA_HADDR_WIDTH-1:0] c0sad;
wire [`DMA_HADDR_WIDTH-1:0] c0dad;
`ifdef DMA_HAVE_LINKLIST
wire [`DMA_HADDR_WIDTH-1:0] c0llp;
`endif
wire [`DMA_CHSZ_WIDTH-1:0] c0tsz;
`ifdef DMA_HAVE_AHB1
`ifdef DMA_HAVE_BRIDGE
reg [31:16] c0dmabs;
reg [31:16] c0brbs;
`endif
`endif
wire [`DMA_CHCSR_WIDTH-1:0] c1csr;
wire [`DMA_CHCFG_WIDTH-1:0] c1cfg;
`ifdef DMA_HAVE_CH1
wire [`DMA_HADDR_WIDTH-1:0] c1sad;
wire [`DMA_HADDR_WIDTH-1:0] c1dad;
`ifdef DMA_HAVE_LINKLIST
wire [`DMA_HADDR_WIDTH-1:0] c1llp;
`endif
wire [`DMA_CHSZ_WIDTH-1:0] c1tsz;
`ifdef DMA_HAVE_AHB1
`ifdef DMA_HAVE_BRIDGE
reg [31:16] c1dmabs;
reg [31:16] c1brbs;
`endif
`endif
`endif
wire [`DMA_CHCSR_WIDTH-1:0] c2csr;
wire [`DMA_CHCFG_WIDTH-1:0] c2cfg;
`ifdef DMA_HAVE_CH2
wire [`DMA_HADDR_WIDTH-1:0] c2sad;
wire [`DMA_HADDR_WIDTH-1:0] c2dad;
`ifdef DMA_HAVE_LINKLIST
wire [`DMA_HADDR_WIDTH-1:0] c2llp;
`endif
wire [`DMA_CHSZ_WIDTH-1:0] c2tsz;
`ifdef DMA_HAVE_AHB1
`ifdef DMA_HAVE_BRIDGE
reg [31:16] c2dmabs;
reg [31:16] c2brbs;
`endif
`endif
`endif
wire [`DMA_CHCSR_WIDTH-1:0] c3csr;
wire [`DMA_CHCFG_WIDTH-1:0] c3cfg;
`ifdef DMA_HAVE_CH3
wire [`DMA_HADDR_WIDTH-1:0] c3sad;
wire [`DMA_HADDR_WIDTH-1:0] c3dad;
`ifdef DMA_HAVE_LINKLIST
wire [`DMA_HADDR_WIDTH-1:0] c3llp;
`endif
wire [`DMA_CHSZ_WIDTH-1:0] c3tsz;
`ifdef DMA_HAVE_AHB1
`ifdef DMA_HAVE_BRIDGE
reg [31:16] c3dmabs;
reg [31:16] c3brbs;
`endif
`endif
`endif
wire [`DMA_CHCSR_WIDTH-1:0] c4csr;
wire [`DMA_CHCFG_WIDTH-1:0] c4cfg;
`ifdef DMA_HAVE_CH4
wire [`DMA_HADDR_WIDTH-1:0] c4sad;
wire [`DMA_HADDR_WIDTH-1:0] c4dad;
`ifdef DMA_HAVE_LINKLIST
wire [`DMA_HADDR_WIDTH-1:0] c4llp;
`endif
wire [`DMA_CHSZ_WIDTH-1:0] c4tsz;
`ifdef DMA_HAVE_AHB1
`ifdef DMA_HAVE_BRIDGE
reg [31:16] c4dmabs;
reg [31:16] c4brbs;
`endif
`endif
`endif
wire [`DMA_CHCSR_WIDTH-1:0] c5csr;
wire [`DMA_CHCFG_WIDTH-1:0] c5cfg;
`ifdef DMA_HAVE_CH5
wire [`DMA_HADDR_WIDTH-1:0] c5sad;
wire [`DMA_HADDR_WIDTH-1:0] c5dad;
`ifdef DMA_HAVE_LINKLIST
wire [`DMA_HADDR_WIDTH-1:0] c5llp;
`endif
wire [`DMA_CHSZ_WIDTH-1:0] c5tsz;
`ifdef DMA_HAVE_AHB1
`ifdef DMA_HAVE_BRIDGE
reg [31:16] c5dmabs;
reg [31:16] c5brbs;
`endif
`endif
`endif
wire [`DMA_CHCSR_WIDTH-1:0] c6csr;
wire [`DMA_CHCFG_WIDTH-1:0] c6cfg;
`ifdef DMA_HAVE_CH6
wire [`DMA_HADDR_WIDTH-1:0] c6sad;
wire [`DMA_HADDR_WIDTH-1:0] c6dad;
`ifdef DMA_HAVE_LINKLIST
wire [`DMA_HADDR_WIDTH-1:0] c6llp;
`endif
wire [`DMA_CHSZ_WIDTH-1:0] c6tsz;
`ifdef DMA_HAVE_AHB1
`ifdef DMA_HAVE_BRIDGE
reg [31:16] c6dmabs;
reg [31:16] c6brbs;
`endif
`endif
`endif
wire [`DMA_CHCSR_WIDTH-1:0] c7csr;
wire [`DMA_CHCFG_WIDTH-1:0] c7cfg;
`ifdef DMA_HAVE_CH7
wire [`DMA_HADDR_WIDTH-1:0] c7sad;
wire [`DMA_HADDR_WIDTH-1:0] c7dad;
`ifdef DMA_HAVE_LINKLIST
wire [`DMA_HADDR_WIDTH-1:0] c7llp;
`endif
wire [`DMA_CHSZ_WIDTH-1:0] c7tsz;
`ifdef DMA_HAVE_AHB1
`ifdef DMA_HAVE_BRIDGE
reg [31:16] c7dmabs;
reg [31:16] c7brbs;
`endif
`endif
`endif
assign be0 = ((slv_sz == `DMA_HSIZE_BYTE)&~slv_ad[1]&~slv_ad[0]) |
((slv_sz == `DMA_HSIZE_HALFWORD)&~slv_ad[1]) |
(slv_sz == `DMA_HSIZE_WORD);
assign be1 = ((slv_sz == `DMA_HSIZE_BYTE)&~slv_ad[1]&slv_ad[0]) |
((slv_sz == `DMA_HSIZE_HALFWORD)&~slv_ad[1]) |
(slv_sz == `DMA_HSIZE_WORD);
assign be2 = ((slv_sz == `DMA_HSIZE_BYTE)&slv_ad[1]&~slv_ad[0]) |
((slv_sz == `DMA_HSIZE_HALFWORD)&slv_ad[1]) |
(slv_sz == `DMA_HSIZE_WORD);
assign be3 = ((slv_sz == `DMA_HSIZE_BYTE)&slv_ad[1]&slv_ad[0]) |
((slv_sz == `DMA_HSIZE_HALFWORD)&slv_ad[1]) |
(slv_sz == `DMA_HSIZE_WORD);
assign dma_chrfsel = (slv_ad[8]);
assign rf_dto = dma_chrfsel? mux_ch : mux_ms;
always @(slv_ad or mux_gl
`ifdef DMA_HAVE_AHB1
`ifdef DMA_HAVE_BRIDGE
or mux_dbs or mux_bbs
`endif
`endif
)
case(slv_ad[7:6])
2'b00: mux_ms = {mux_gl};
`ifdef DMA_HAVE_AHB1
`ifdef DMA_HAVE_BRIDGE
2'b01: mux_ms = {mux_dbs,16'b0};
2'b10: mux_ms = {mux_bbs,16'b0};
`endif
`endif
default: mux_ms = 32'bx;
endcase
always @(slv_ad or int or int_tc or int_err or tc or
err or ch_en or ch_busy or csr or sync or int_abt or abt)
case(slv_ad[5:2])
4'h0: mux_gl = {{{32-`DMA_MAX_CHNO}{1'b0}},int};
4'h1: mux_gl = {{{32-`DMA_MAX_CHNO}{1'b0}},int_tc};
4'h3: mux_gl = {{{16-`DMA_MAX_CHNO}{1'b0}},int_abt,{{16-`DMA_MAX_CHNO}{1'b0}},int_err};
4'h5: mux_gl = {{{32-`DMA_MAX_CHNO}{1'b0}},tc};
4'h6: mux_gl = {{{16-`DMA_MAX_CHNO}{1'b0}},abt, {{16-`DMA_MAX_CHNO}{1'b0}},err};
4'h7: mux_gl = {24'b0,ch_en};
4'h8: mux_gl = {24'b0,ch_busy};
4'h9: mux_gl = {{{32-`DMA_CSR_WIDTH}{1'b0}},csr};
4'ha: mux_gl = {{{32-`DMA_MAX_CHNO}{1'b0}},sync};
default: mux_gl = 'hx;
endcase
`ifdef DMA_HAVE_AHB1
`ifdef DMA_HAVE_BRIDGE
always @(slv_ad or c0dmabs
`ifdef DMA_HAVE_CH1
or c1dmabs
`endif
`ifdef DMA_HAVE_CH2
or c2dmabs
`endif
`ifdef DMA_HAVE_CH3
or c3dmabs
`endif
`ifdef DMA_HAVE_CH4
or c4dmabs
`endif
`ifdef DMA_HAVE_CH5
or c5dmabs
`endif
`ifdef DMA_HAVE_CH6
or c6dmabs
`endif
`ifdef DMA_HAVE_CH7
or c7dmabs
`endif
)
case(slv_ad[4:2])
3'h0: mux_dbs = c0dmabs;
`ifdef DMA_HAVE_CH1
3'h1: mux_dbs = c1dmabs;
`endif
`ifdef DMA_HAVE_CH2
3'h2: mux_dbs = c2dmabs;
`endif
`ifdef DMA_HAVE_CH3
3'h3: mux_dbs = c3dmabs;
`endif
`ifdef DMA_HAVE_CH4
3'h4: mux_dbs = c4dmabs;
`endif
`ifdef DMA_HAVE_CH5
3'h5: mux_dbs = c5dmabs;
`endif
`ifdef DMA_HAVE_CH6
3'h6: mux_dbs = c6dmabs;
`endif
`ifdef DMA_HAVE_CH7
3'h7: mux_dbs = c7dmabs;
`endif
default: mux_dbs = 'hx;
endcase
always @(slv_ad or c0brbs
`ifdef DMA_HAVE_CH1
or c1brbs
`endif
`ifdef DMA_HAVE_CH2
or c2brbs
`endif
`ifdef DMA_HAVE_CH3
or c3brbs
`endif
`ifdef DMA_HAVE_CH4
or c4brbs
`endif
`ifdef DMA_HAVE_CH5
or c5brbs
`endif
`ifdef DMA_HAVE_CH6
or c6brbs
`endif
`ifdef DMA_HAVE_CH7
or c7brbs
`endif
)
case(slv_ad[4:2])
3'h0: mux_bbs = c0brbs;
`ifdef DMA_HAVE_CH1
3'h1: mux_bbs = c1brbs;
`endif
`ifdef DMA_HAVE_CH2
3'h2: mux_bbs = c2brbs;
`endif
`ifdef DMA_HAVE_CH3
3'h3: mux_bbs = c3brbs;
`endif
`ifdef DMA_HAVE_CH4
3'h4: mux_bbs = c4brbs;
`endif
`ifdef DMA_HAVE_CH5
3'h5: mux_bbs = c5brbs;
`endif
`ifdef DMA_HAVE_CH6
3'h6: mux_bbs = c6brbs;
`endif
`ifdef DMA_HAVE_CH7
3'h7: mux_bbs = c7brbs;
`endif
default: mux_bbs = 'hx;
endcase
`endif
`endif
always @(slv_ad or mux_c0l or mux_c0h
`ifdef DMA_HAVE_CH1
or mux_c1l or mux_c1h
`endif
`ifdef DMA_HAVE_CH2
or mux_c2l or mux_c2h
`endif
`ifdef DMA_HAVE_CH3
or mux_c3l or mux_c3h
`endif
`ifdef DMA_HAVE_CH4
or mux_c4l or mux_c4h
`endif
`ifdef DMA_HAVE_CH5
or mux_c5l or mux_c5h
`endif
`ifdef DMA_HAVE_CH6
or mux_c6l or mux_c6h
`endif
`ifdef DMA_HAVE_CH7
or mux_c7l or mux_c7h
`endif
)
case(slv_ad[7:4])
4'h0: mux_ch = mux_c0l;
4'h1: mux_ch = mux_c0h;
`ifdef DMA_HAVE_CH1
4'h2: mux_ch = mux_c1l;
4'h3: mux_ch = mux_c1h;
`endif
`ifdef DMA_HAVE_CH2
4'h4: mux_ch = mux_c2l;
4'h5: mux_ch = mux_c2h;
`endif
`ifdef DMA_HAVE_CH3
4'h6: mux_ch = mux_c3l;
4'h7: mux_ch = mux_c3h;
`endif
`ifdef DMA_HAVE_CH4
4'h8: mux_ch = mux_c4l;
4'h9: mux_ch = mux_c4h;
`endif
`ifdef DMA_HAVE_CH5
4'ha: mux_ch = mux_c5l;
4'hb: mux_ch = mux_c5h;
`endif
`ifdef DMA_HAVE_CH6
4'hc: mux_ch = mux_c6l;
4'hd: mux_ch = mux_c6h;
`endif
`ifdef DMA_HAVE_CH7
4'he: mux_ch = mux_c7l;
4'hf: mux_ch = mux_c7h;
`endif
default: mux_ch = 'hx;
endcase
always @(slv_ad or c0csr or c0cfg or c0sad or c0dad)
case(slv_ad[3:2])
2'h0: mux_c0l = c0csr;
2'h1: mux_c0l = c0cfg;
2'h2: mux_c0l = c0sad;
2'h3: mux_c0l = c0dad;
endcase
always @(slv_ad
`ifdef DMA_HAVE_LINKLIST
or c0llp
`endif
or c0tsz)
case(slv_ad[3:2])
`ifdef DMA_HAVE_LINKLIST
2'h0: mux_c0h = c0llp;
`endif
2'h1: mux_c0h = c0tsz;
default: mux_c0h = 'hx;
endcase
`ifdef DMA_HAVE_CH1
always @(slv_ad or c1csr or c1cfg or c1sad or c1dad)
case(slv_ad[3:2])
2'h0: mux_c1l = c1csr;
2'h1: mux_c1l = c1cfg;
2'h2: mux_c1l = c1sad;
2'h3: mux_c1l = c1dad;
endcase
always @(slv_ad
`ifdef DMA_HAVE_LINKLIST
or c1llp
`endif
or c1tsz)
case(slv_ad[3:2])
`ifdef DMA_HAVE_LINKLIST
2'h0: mux_c1h = c1llp;
`endif
2'h1: mux_c1h = c1tsz;
default: mux_c1h = 'hx;
endcase
`endif
`ifdef DMA_HAVE_CH2
always @(slv_ad or c2csr or c2cfg or c2sad or c2dad)
case(slv_ad[3:2])
2'h0: mux_c2l = c2csr;
2'h1: mux_c2l = c2cfg;
2'h2: mux_c2l = c2sad;
2'h3: mux_c2l = c2dad;
endcase
always @(slv_ad
`ifdef DMA_HAVE_LINKLIST
or c2llp
`endif
or c2tsz)
case(slv_ad[3:2])
`ifdef DMA_HAVE_LINKLIST
2'h0: mux_c2h = c2llp;
`endif
2'h1: mux_c2h = c2tsz;
default: mux_c2h = 'hx;
endcase
`endif
`ifdef DMA_HAVE_CH3
always @(slv_ad or c3csr or c3cfg or c3sad or c3dad)
case(slv_ad[3:2])
2'h0: mux_c3l = c3csr;
2'h1: mux_c3l = c3cfg;
2'h2: mux_c3l = c3sad;
2'h3: mux_c3l = c3dad;
endcase
always @(slv_ad
`ifdef DMA_HAVE_LINKLIST
or c3llp
`endif
or c3tsz)
case(slv_ad[3:2])
`ifdef DMA_HAVE_LINKLIST
2'h0: mux_c3h = c3llp;
`endif
2'h1: mux_c3h = c3tsz;
default: mux_c3h = 'hx;
endcase
`endif
`ifdef DMA_HAVE_CH4
always @(slv_ad or c4csr or c4cfg or c4sad or c4dad)
case(slv_ad[3:2])
2'h0: mux_c4l = c4csr;
2'h1: mux_c4l = c4cfg;
2'h2: mux_c4l = c4sad;
2'h3: mux_c4l = c4dad;
endcase
always @(slv_ad
`ifdef DMA_HAVE_LINKLIST
or c4llp
`endif
or c4tsz)
case(slv_ad[3:2])
`ifdef DMA_HAVE_LINKLIST
2'h0: mux_c4h = c4llp;
`endif
2'h1: mux_c4h = c4tsz;
default: mux_c4h = 'hx;
endcase
`endif
`ifdef DMA_HAVE_CH5
always @(slv_ad or c5csr or c5cfg or c5sad or c5dad)
case(slv_ad[3:2])
2'h0: mux_c5l = c5csr;
2'h1: mux_c5l = c5cfg;
2'h2: mux_c5l = c5sad;
2'h3: mux_c5l = c5dad;
endcase
always @(slv_ad
`ifdef DMA_HAVE_LINKLIST
or c5llp
`endif
or c5tsz)
case(slv_ad[3:2])
`ifdef DMA_HAVE_LINKLIST
2'h0: mux_c5h = c5llp;
`endif
2'h1: mux_c5h = c5tsz;
default: mux_c5h = 'hx;
endcase
`endif
`ifdef DMA_HAVE_CH6
always @(slv_ad or c6csr or c6cfg or c6sad or c6dad)
case(slv_ad[3:2])
2'h0: mux_c6l = c6csr;
2'h1: mux_c6l = c6cfg;
2'h2: mux_c6l = c6sad;
2'h3: mux_c6l = c6dad;
endcase
always @(slv_ad
`ifdef DMA_HAVE_LINKLIST
or c6llp
`endif
or c6tsz)
case(slv_ad[3:2])
`ifdef DMA_HAVE_LINKLIST
2'h0: mux_c6h = c6llp;
`endif
2'h1: mux_c6h = c6tsz;
default: mux_c6h = 'hx;
endcase
`endif
`ifdef DMA_HAVE_CH7
always @(slv_ad or c7csr or c7cfg or c7sad or c7dad)
case(slv_ad[3:2])
2'h0: mux_c7l = c7csr;
2'h1: mux_c7l = c7cfg;
2'h2: mux_c7l = c7sad;
2'h3: mux_c7l = c7dad;
endcase
always @(slv_ad
`ifdef DMA_HAVE_LINKLIST
or c7llp
`endif
or c7tsz)
case(slv_ad[3:2])
`ifdef DMA_HAVE_LINKLIST
2'h0: mux_c7h = c7llp;
`endif
2'h1: mux_c7h = c7tsz;
default: mux_c7h = 'hx;
endcase
`endif
always @(posedge HCLK)
be_d1 <= {be3, be2, be1, be0};
always @(posedge HCLK or negedge HRSTn)
if(~HRSTn)
rf_sel_d1 <= 1'b0;
else
rf_sel_d1 <= slv_rf_sel;
assign sel_tc_clr = (slv_ad_d1[8:2] == 7'h2)&rf_sel_d1;
assign sel_err_clr = (slv_ad_d1[8:2] == 7'h4)&rf_sel_d1;
assign sel_csr = (slv_ad_d1[8:2] == 7'h9)&rf_sel_d1;
assign sel_sync = (slv_ad_d1[8:2] == 7'ha)&rf_sel_d1;
`ifdef DMA_HAVE_AHB1
`ifdef DMA_HAVE_BRIDGE
assign sel_c0dbs = (slv_ad_d1[8:2] == 7'h10)&rf_sel_d1;
assign sel_c0bbs = (slv_ad_d1[8:2] == 7'h20)&rf_sel_d1;
assign c0dbs_we = (slv_wr_d1&sel_c0dbs);
assign c0bbs_we = (slv_wr_d1&sel_c0bbs);
`ifdef DMA_HAVE_CH1
assign sel_c1dbs = (slv_ad_d1[8:2] == 7'h11)&rf_sel_d1;
assign sel_c1bbs = (slv_ad_d1[8:2] == 7'h21)&rf_sel_d1;
assign c1dbs_we = (slv_wr_d1&sel_c1dbs);
assign c1bbs_we = (slv_wr_d1&sel_c1bbs);
`endif
`ifdef DMA_HAVE_CH2
assign sel_c2dbs = (slv_ad_d1[8:2] == 7'h12)&rf_sel_d1;
assign sel_c2bbs = (slv_ad_d1[8:2] == 7'h22)&rf_sel_d1;
assign c2dbs_we = (slv_wr_d1&sel_c2dbs);
assign c2bbs_we = (slv_wr_d1&sel_c2bbs);
`endif
`ifdef DMA_HAVE_CH3
assign sel_c3dbs = (slv_ad_d1[8:2] == 7'h13)&rf_sel_d1;
assign sel_c3bbs = (slv_ad_d1[8:2] == 7'h23)&rf_sel_d1;
assign c3dbs_we = (slv_wr_d1&sel_c3dbs);
assign c3bbs_we = (slv_wr_d1&sel_c3bbs);
`endif
`ifdef DMA_HAVE_CH4
assign sel_c4dbs = (slv_ad_d1[8:2] == 7'h14)&rf_sel_d1;
assign sel_c4bbs = (slv_ad_d1[8:2] == 7'h24)&rf_sel_d1;
assign c4dbs_we = (slv_wr_d1&sel_c4dbs);
assign c4bbs_we = (slv_wr_d1&sel_c4bbs);
`endif
`ifdef DMA_HAVE_CH5
assign sel_c5dbs = (slv_ad_d1[8:2] == 7'h15)&rf_sel_d1;
assign sel_c5bbs = (slv_ad_d1[8:2] == 7'h25)&rf_sel_d1;
assign c5dbs_we = (slv_wr_d1&sel_c5dbs);
assign c5bbs_we = (slv_wr_d1&sel_c5bbs);
`endif
`ifdef DMA_HAVE_CH6
assign sel_c6dbs = (slv_ad_d1[8:2] == 7'h16)&rf_sel_d1;
assign sel_c6bbs = (slv_ad_d1[8:2] == 7'h26)&rf_sel_d1;
assign c6dbs_we = (slv_wr_d1&sel_c6dbs);
assign c6bbs_we = (slv_wr_d1&sel_c6bbs);
`endif
`ifdef DMA_HAVE_CH7
assign sel_c7dbs = (slv_ad_d1[8:2] == 7'h17)&rf_sel_d1;
assign sel_c7bbs = (slv_ad_d1[8:2] == 7'h27)&rf_sel_d1;
assign c7dbs_we = (slv_wr_d1&sel_c7dbs);
assign c7bbs_we = (slv_wr_d1&sel_c7bbs);
`endif
`endif
`endif
assign sel_c0csr = (slv_ad_d1[8:2] == 7'h40)&rf_sel_d1;
assign sel_c0cfg = (slv_ad_d1[8:2] == 7'h41)&rf_sel_d1;
assign sel_c0sad = (slv_ad_d1[8:2] == 7'h42)&rf_sel_d1;
assign sel_c0dad = (slv_ad_d1[8:2] == 7'h43)&rf_sel_d1;
`ifdef DMA_HAVE_LINKLIST
assign sel_c0llp = (slv_ad_d1[8:2] == 7'h44)&rf_sel_d1;
`endif
assign sel_c0tsz = (slv_ad_d1[8:2] == 7'h45)&rf_sel_d1;
assign c0csr_we = (slv_wr_d1&sel_c0csr);
assign c0cfg_we = (slv_wr_d1&sel_c0cfg);
assign c0sad_we = (slv_wr_d1&sel_c0sad);
assign c0dad_we = (slv_wr_d1&sel_c0dad);
`ifdef DMA_HAVE_LINKLIST
assign c0llp_we = (slv_wr_d1&sel_c0llp);
`endif
assign c0tsz_we = (slv_wr_d1&sel_c0tsz);
`ifdef DMA_HAVE_CH1
assign sel_c1csr = (slv_ad_d1[8:2] == 7'h48)&rf_sel_d1;
assign sel_c1cfg = (slv_ad_d1[8:2] == 7'h49)&rf_sel_d1;
assign sel_c1sad = (slv_ad_d1[8:2] == 7'h4a)&rf_sel_d1;
assign sel_c1dad = (slv_ad_d1[8:2] == 7'h4b)&rf_sel_d1;
`ifdef DMA_HAVE_LINKLIST
assign sel_c1llp = (slv_ad_d1[8:2] == 7'h4c)&rf_sel_d1;
`endif
assign sel_c1tsz = (slv_ad_d1[8:2] == 7'h4d)&rf_sel_d1;
assign c1csr_we = (slv_wr_d1&sel_c1csr);
assign c1cfg_we = (slv_wr_d1&sel_c1cfg);
assign c1sad_we = (slv_wr_d1&sel_c1sad);
assign c1dad_we = (slv_wr_d1&sel_c1dad);
`ifdef DMA_HAVE_LINKLIST
assign c1llp_we = (slv_wr_d1&sel_c1llp);
`endif
assign c1tsz_we = (slv_wr_d1&sel_c1tsz);
`endif
`ifdef DMA_HAVE_CH2
assign sel_c2csr = (slv_ad_d1[8:2] == 7'h50)&rf_sel_d1;
assign sel_c2cfg = (slv_ad_d1[8:2] == 7'h51)&rf_sel_d1;
assign sel_c2sad = (slv_ad_d1[8:2] == 7'h52)&rf_sel_d1;
assign sel_c2dad = (slv_ad_d1[8:2] == 7'h53)&rf_sel_d1;
`ifdef DMA_HAVE_LINKLIST
assign sel_c2llp = (slv_ad_d1[8:2] == 7'h54)&rf_sel_d1;
`endif
assign sel_c2tsz = (slv_ad_d1[8:2] == 7'h55)&rf_sel_d1;
assign c2csr_we = (slv_wr_d1&sel_c2csr);
assign c2cfg_we = (slv_wr_d1&sel_c2cfg);
assign c2sad_we = (slv_wr_d1&sel_c2sad);
assign c2dad_we = (slv_wr_d1&sel_c2dad);
`ifdef DMA_HAVE_LINKLIST
assign c2llp_we = (slv_wr_d1&sel_c2llp);
`endif
assign c2tsz_we = (slv_wr_d1&sel_c2tsz);
`endif
`ifdef DMA_HAVE_CH3
assign sel_c3csr = (slv_ad_d1[8:2] == 7'h58)&rf_sel_d1;
assign sel_c3cfg = (slv_ad_d1[8:2] == 7'h59)&rf_sel_d1;
assign sel_c3sad = (slv_ad_d1[8:2] == 7'h5a)&rf_sel_d1;
assign sel_c3dad = (slv_ad_d1[8:2] == 7'h5b)&rf_sel_d1;
`ifdef DMA_HAVE_LINKLIST
assign sel_c3llp = (slv_ad_d1[8:2] == 7'h5c)&rf_sel_d1;
`endif
assign sel_c3tsz = (slv_ad_d1[8:2] == 7'h5d)&rf_sel_d1;
assign c3csr_we = (slv_wr_d1&sel_c3csr);
assign c3cfg_we = (slv_wr_d1&sel_c3cfg);
assign c3sad_we = (slv_wr_d1&sel_c3sad);
assign c3dad_we = (slv_wr_d1&sel_c3dad);
`ifdef DMA_HAVE_LINKLIST
assign c3llp_we = (slv_wr_d1&sel_c3llp);
`endif
assign c3tsz_we = (slv_wr_d1&sel_c3tsz);
`endif
`ifdef DMA_HAVE_CH4
assign sel_c4csr = (slv_ad_d1[8:2] == 7'h60)&rf_sel_d1;
assign sel_c4cfg = (slv_ad_d1[8:2] == 7'h61)&rf_sel_d1;
assign sel_c4sad = (slv_ad_d1[8:2] == 7'h62)&rf_sel_d1;
assign sel_c4dad = (slv_ad_d1[8:2] == 7'h63)&rf_sel_d1;
`ifdef DMA_HAVE_LINKLIST
assign sel_c4llp = (slv_ad_d1[8:2] == 7'h64)&rf_sel_d1;
`endif
assign sel_c4tsz = (slv_ad_d1[8:2] == 7'h65)&rf_sel_d1;
assign c4csr_we = (slv_wr_d1&sel_c4csr);
assign c4cfg_we = (slv_wr_d1&sel_c4cfg);
assign c4sad_we = (slv_wr_d1&sel_c4sad);
assign c4dad_we = (slv_wr_d1&sel_c4dad);
`ifdef DMA_HAVE_LINKLIST
assign c4llp_we = (slv_wr_d1&sel_c4llp);
`endif
assign c4tsz_we = (slv_wr_d1&sel_c4tsz);
`endif
`ifdef DMA_HAVE_CH5
assign sel_c5csr = (slv_ad_d1[8:2] == 7'h68)&rf_sel_d1;
assign sel_c5cfg = (slv_ad_d1[8:2] == 7'h69)&rf_sel_d1;
assign sel_c5sad = (slv_ad_d1[8:2] == 7'h6a)&rf_sel_d1;
assign sel_c5dad = (slv_ad_d1[8:2] == 7'h6b)&rf_sel_d1;
`ifdef DMA_HAVE_LINKLIST
assign sel_c5llp = (slv_ad_d1[8:2] == 7'h6c)&rf_sel_d1;
`endif
assign sel_c5tsz = (slv_ad_d1[8:2] == 7'h6d)&rf_sel_d1;
assign c5csr_we = (slv_wr_d1&sel_c5csr);
assign c5cfg_we = (slv_wr_d1&sel_c5cfg);
assign c5sad_we = (slv_wr_d1&sel_c5sad);
assign c5dad_we = (slv_wr_d1&sel_c5dad);
`ifdef DMA_HAVE_LINKLIST
assign c5llp_we = (slv_wr_d1&sel_c5llp);
`endif
assign c5tsz_we = (slv_wr_d1&sel_c5tsz);
`endif
`ifdef DMA_HAVE_CH6
assign sel_c6csr = (slv_ad_d1[8:2] == 7'h70)&rf_sel_d1;
assign sel_c6cfg = (slv_ad_d1[8:2] == 7'h71)&rf_sel_d1;
assign sel_c6sad = (slv_ad_d1[8:2] == 7'h72)&rf_sel_d1;
assign sel_c6dad = (slv_ad_d1[8:2] == 7'h73)&rf_sel_d1;
`ifdef DMA_HAVE_LINKLIST
assign sel_c6llp = (slv_ad_d1[8:2] == 7'h74)&rf_sel_d1;
`endif
assign sel_c6tsz = (slv_ad_d1[8:2] == 7'h75)&rf_sel_d1;
assign c6csr_we = (slv_wr_d1&sel_c6csr);
assign c6cfg_we = (slv_wr_d1&sel_c6cfg);
assign c6sad_we = (slv_wr_d1&sel_c6sad);
assign c6dad_we = (slv_wr_d1&sel_c6dad);
`ifdef DMA_HAVE_LINKLIST
assign c6llp_we = (slv_wr_d1&sel_c6llp);
`endif
assign c6tsz_we = (slv_wr_d1&sel_c6tsz);
`endif
`ifdef DMA_HAVE_CH7
assign sel_c7csr = (slv_ad_d1[8:2] == 7'h78)&rf_sel_d1;
assign sel_c7cfg = (slv_ad_d1[8:2] == 7'h79)&rf_sel_d1;
assign sel_c7sad = (slv_ad_d1[8:2] == 7'h7a)&rf_sel_d1;
assign sel_c7dad = (slv_ad_d1[8:2] == 7'h7b)&rf_sel_d1;
`ifdef DMA_HAVE_LINKLIST
assign sel_c7llp = (slv_ad_d1[8:2] == 7'h7c)&rf_sel_d1;
`endif
assign sel_c7tsz = (slv_ad_d1[8:2] == 7'h7d)&rf_sel_d1;
assign c7csr_we = (slv_wr_d1&sel_c7csr);
assign c7cfg_we = (slv_wr_d1&sel_c7cfg);
assign c7sad_we = (slv_wr_d1&sel_c7sad);
assign c7dad_we = (slv_wr_d1&sel_c7dad);
`ifdef DMA_HAVE_LINKLIST
assign c7llp_we = (slv_wr_d1&sel_c7llp);
`endif
assign c7tsz_we = (slv_wr_d1&sel_c7tsz);
`endif
assign tc_clr = (slv_wr_d1&be_d1[0]&sel_tc_clr) ? slv_wdti[7:0] : 8'b0;
assign err_clr = (slv_wr_d1&be_d1[0]&sel_err_clr) ? slv_wdti[7:0] : 8'b0;
assign abt_clr = (slv_wr_d1&be_d1[2]&sel_err_clr) ? slv_wdti[23:16] : 8'b0;
assign csr_we = (slv_wr_d1&be_d1[0]&sel_csr);
assign sync_we = (slv_wr_d1&be_d1[0]&sel_sync);
always @(posedge HCLK or negedge HRSTn)
if(~HRSTn)
dmaint <= 'h0;
else
dmaint <= intin;
always @(posedge HCLK or negedge HRSTn)
if(~HRSTn)
dmaint_tc <= 'h0;
else
dmaint_tc <= inttcin;
always @(posedge HCLK or negedge HRSTn)
if(~HRSTn)
dmaint_err <= 'h0;
else
dmaint_err <= interrin;
assign intin = inttcin | interrin | intabtin;
assign inttcin = | int_tc;
assign interrin = | int_err;
assign intabtin = | int_abt;
assign int = int_tc | int_err | int_abt;
assign int_tc[0] = ~c0cfg[`DMA_CHCFG_INTTC]&tc[0];
assign int_err[0] = ~c0cfg[`DMA_CHCFG_INTERR]&err[0];
assign int_abt[0] = ~c0cfg[`DMA_CHCFG_INTABT]&abt[0];
`ifdef DMA_HAVE_CH1
assign int_tc[1] = ~c1cfg[`DMA_CHCFG_INTTC]&tc[1];
assign int_err[1] = ~c1cfg[`DMA_CHCFG_INTERR]&err[1];
assign int_abt[1] = ~c1cfg[`DMA_CHCFG_INTABT]&abt[1];
`endif
`ifdef DMA_HAVE_CH2
assign int_tc[2] = ~c2cfg[`DMA_CHCFG_INTTC]&tc[2];
assign int_err[2] = ~c2cfg[`DMA_CHCFG_INTERR]&err[2];
assign int_abt[2] = ~c2cfg[`DMA_CHCFG_INTABT]&abt[2];
`endif
`ifdef DMA_HAVE_CH3
assign int_tc[3] = ~c3cfg[`DMA_CHCFG_INTTC]&tc[3];
assign int_err[3] = ~c3cfg[`DMA_CHCFG_INTERR]&err[3];
assign int_abt[3] = ~c3cfg[`DMA_CHCFG_INTABT]&abt[3];
`endif
`ifdef DMA_HAVE_CH4
assign int_tc[4] = ~c4cfg[`DMA_CHCFG_INTTC]&tc[4];
assign int_err[4] = ~c4cfg[`DMA_CHCFG_INTERR]&err[4];
assign int_abt[4] = ~c4cfg[`DMA_CHCFG_INTABT]&abt[4];
`endif
`ifdef DMA_HAVE_CH5
assign int_tc[5] = ~c5cfg[`DMA_CHCFG_INTTC]&tc[5];
assign int_err[5] = ~c5cfg[`DMA_CHCFG_INTERR]&err[5];
assign int_abt[5] = ~c5cfg[`DMA_CHCFG_INTABT]&abt[5];
`endif
`ifdef DMA_HAVE_CH6
assign int_tc[6] = ~c6cfg[`DMA_CHCFG_INTTC]&tc[6];
assign int_err[6] = ~c6cfg[`DMA_CHCFG_INTERR]&err[6];
assign int_abt[6] = ~c6cfg[`DMA_CHCFG_INTABT]&abt[6];
`endif
`ifdef DMA_HAVE_CH7
assign int_tc[7] = ~c7cfg[`DMA_CHCFG_INTTC]&tc[7];
assign int_err[7] = ~c7cfg[`DMA_CHCFG_INTERR]&err[7];
assign int_abt[7] = ~c7cfg[`DMA_CHCFG_INTABT]&abt[7];
`endif
assign tc_st[0] = (arb_ch_sel == 0)&de_tc_st&~c0csr[`DMA_CHCSR_INTTC];
`ifdef DMA_HAVE_CH1
assign tc_st[1] = (arb_ch_sel == 1)&de_tc_st&~c1csr[`DMA_CHCSR_INTTC];
`endif
`ifdef DMA_HAVE_CH2
assign tc_st[2] = (arb_ch_sel == 2)&de_tc_st&~c2csr[`DMA_CHCSR_INTTC];
`endif
`ifdef DMA_HAVE_CH3
assign tc_st[3] = (arb_ch_sel == 3)&de_tc_st&~c3csr[`DMA_CHCSR_INTTC];
`endif
`ifdef DMA_HAVE_CH4
assign tc_st[4] = (arb_ch_sel == 4)&de_tc_st&~c4csr[`DMA_CHCSR_INTTC];
`endif
`ifdef DMA_HAVE_CH5
assign tc_st[5] = (arb_ch_sel == 5)&de_tc_st&~c5csr[`DMA_CHCSR_INTTC];
`endif
`ifdef DMA_HAVE_CH6
assign tc_st[6] = (arb_ch_sel == 6)&de_tc_st&~c6csr[`DMA_CHCSR_INTTC];
`endif
`ifdef DMA_HAVE_CH7
assign tc_st[7] = (arb_ch_sel == 7)&de_tc_st&~c7csr[`DMA_CHCSR_INTTC];
`endif
always @(posedge HCLK or negedge HRSTn)
if(~HRSTn)
tc[0] <= 1'b0;
else if(tc_st[0])
tc[0] <= 1'b1;
else if(tc_clr[0])
tc[0] <= 1'b0;
`ifdef DMA_HAVE_CH1
always @(posedge HCLK or negedge HRSTn)
if(~HRSTn)
tc[1] <= 1'b0;
else if(tc_st[1])
tc[1] <= 1'b1;
else if(tc_clr[1])
tc[1] <= 1'b0;
`endif
`ifdef DMA_HAVE_CH2
always @(posedge HCLK or negedge HRSTn)
if(~HRSTn)
tc[2] <= 1'b0;
else if(tc_st[2])
tc[2] <= 1'b1;
else if(tc_clr[2])
tc[2] <= 1'b0;
`endif
`ifdef DMA_HAVE_CH3
always @(posedge HCLK or negedge HRSTn)
if(~HRSTn)
tc[3] <= 1'b0;
else if(tc_st[3])
tc[3] <= 1'b1;
else if(tc_clr[3])
tc[3] <= 1'b0;
`endif
`ifdef DMA_HAVE_CH4
always @(posedge HCLK or negedge HRSTn)
if(~HRSTn)
tc[4] <= 1'b0;
else if(tc_st[4])
tc[4] <= 1'b1;
else if(tc_clr[4])
tc[4] <= 1'b0;
`endif
`ifdef DMA_HAVE_CH5
always @(posedge HCLK or negedge HRSTn)
if(~HRSTn)
tc[5] <= 1'b0;
else if(tc_st[5])
tc[5] <= 1'b1;
else if(tc_clr[5])
tc[5] <= 1'b0;
`endif
`ifdef DMA_HAVE_CH6
always @(posedge HCLK or negedge HRSTn)
if(~HRSTn)
tc[6] <= 1'b0;
else if(tc_st[6])
tc[6] <= 1'b1;
else if(tc_clr[6])
tc[6] <= 1'b0;
`endif
`ifdef DMA_HAVE_CH7
always @(posedge HCLK or negedge HRSTn)
if(~HRSTn)
tc[7] <= 1'b0;
else if(tc_st[7])
tc[7] <= 1'b1;
else if(tc_clr[7])
tc[7] <= 1'b0;
`endif
/*
always @(arb_ch_sel or err)
case(arb_ch_sel)
0: rf_cherr = err[0];
`ifdef DMA_HAVE_CH1
1: rf_cherr = err[1];
`endif
`ifdef DMA_HAVE_CH2
2: rf_cherr = err[2];
`endif
`ifdef DMA_HAVE_CH3
3: rf_cherr = err[3];
`endif
`ifdef DMA_HAVE_CH4
4: rf_cherr = err[4];
`endif
`ifdef DMA_HAVE_CH5
5: rf_cherr = err[5];
`endif
`ifdef DMA_HAVE_CH6
6: rf_cherr = err[6];
`endif
`ifdef DMA_HAVE_CH7
7: rf_cherr = err[7];
`endif
default:
rf_cherr = 0;
endcase
*/
assign err_st[0] = (arb_ch_sel == 0)&(de_err_notify&de_st_upd);
assign abt_st[0] = (arb_ch_sel == 0)&(c0abt&de_st_upd) |
c0abt&((arb_ch_sel != 0) | de_st_idle);
`ifdef DMA_HAVE_CH1
assign err_st[1] = (arb_ch_sel == 1)&(de_err_notify&de_st_upd);
assign abt_st[1] = (arb_ch_sel == 1)&(c1abt&de_st_upd) |
c1abt&((arb_ch_sel != 1) | de_st_idle);
`endif
`ifdef DMA_HAVE_CH2
assign err_st[2] = (arb_ch_sel == 2)&(de_err_notify&de_st_upd);
assign abt_st[2] = (arb_ch_sel == 2)&(c2abt&de_st_upd) |
c2abt&((arb_ch_sel != 2) | de_st_idle);
`endif
`ifdef DMA_HAVE_CH3
assign err_st[3] = (arb_ch_sel == 3)&(de_err_notify&de_st_upd);
assign abt_st[3] = (arb_ch_sel == 3)&(c3abt&de_st_upd) |
c3abt&((arb_ch_sel != 3) | de_st_idle);
`endif
`ifdef DMA_HAVE_CH4
assign err_st[4] = (arb_ch_sel == 4)&(de_err_notify&de_st_upd);
assign abt_st[4] = (arb_ch_sel == 4)&(c4abt&de_st_upd) |
c4abt&((arb_ch_sel != 4) | de_st_idle);
`endif
`ifdef DMA_HAVE_CH5
assign err_st[5] = (arb_ch_sel == 5)&(de_err_notify&de_st_upd);
assign abt_st[5] = (arb_ch_sel == 5)&(c5abt&de_st_upd) |
c5abt&((arb_ch_sel != 5) | de_st_idle);
`endif
`ifdef DMA_HAVE_CH6
assign err_st[6] = (arb_ch_sel == 6)&(de_err_notify&de_st_upd);
assign abt_st[6] = (arb_ch_sel == 6)&(c6abt&de_st_upd) |
c6abt&((arb_ch_sel != 6) | de_st_idle);
`endif
`ifdef DMA_HAVE_CH7
assign err_st[7] = (arb_ch_sel == 7)&(de_err_notify&de_st_upd);
assign abt_st[7] = (arb_ch_sel == 7)&(c7abt&de_st_upd) |
c7abt&((arb_ch_sel != 7) | de_st_idle);
`endif
always @(posedge HCLK or negedge HRSTn)
if(~HRSTn)
err[0] <= 1'b0;
else if(err_st[0])
err[0] <= 1'b1;
else if(err_clr[0])
err[0] <= 1'b0;
always @(posedge HCLK or negedge HRSTn)
if(~HRSTn)
abt[0] <= 1'b0;
else if(abt_st[0])
abt[0] <= 1'b1;
else if(abt_clr[0])
abt[0] <= 1'b0;
`ifdef DMA_HAVE_CH1
always @(posedge HCLK or negedge HRSTn)
if(~HRSTn)
err[1] <= 1'b0;
else if(err_st[1])
err[1] <= 1'b1;
else if(err_clr[1])
err[1] <= 1'b0;
always @(posedge HCLK or negedge HRSTn)
if(~HRSTn)
abt[1] <= 1'b0;
else if(abt_st[1])
abt[1] <= 1'b1;
else if(abt_clr[1])
abt[1] <= 1'b0;
`endif
`ifdef DMA_HAVE_CH2
always @(posedge HCLK or negedge HRSTn)
if(~HRSTn)
err[2] <= 1'b0;
else if(err_st[2])
err[2] <= 1'b1;
else if(err_clr[2])
err[2] <= 1'b0;
always @(posedge HCLK or negedge HRSTn)
if(~HRSTn)
abt[2] <= 1'b0;
else if(abt_st[2])
abt[2] <= 1'b1;
else if(abt_clr[2])
abt[2] <= 1'b0;
`endif
`ifdef DMA_HAVE_CH3
always @(posedge HCLK or negedge HRSTn)
if(~HRSTn)
err[3] <= 1'b0;
else if(err_st[3])
err[3] <= 1'b1;
else if(err_clr[3])
err[3] <= 1'b0;
always @(posedge HCLK or negedge HRSTn)
if(~HRSTn)
abt[3] <= 1'b0;
else if(abt_st[3])
abt[3] <= 1'b1;
else if(abt_clr[3])
abt[3] <= 1'b0;
`endif
`ifdef DMA_HAVE_CH4
always @(posedge HCLK or negedge HRSTn)
if(~HRSTn)
err[4] <= 1'b0;
else if(err_st[4])
err[4] <= 1'b1;
else if(err_clr[4])
err[4] <= 1'b0;
always @(posedge HCLK or negedge HRSTn)
if(~HRSTn)
abt[4] <= 1'b0;
else if(abt_st[4])
abt[4] <= 1'b1;
else if(abt_clr[4])
abt[4] <= 1'b0;
`endif
`ifdef DMA_HAVE_CH5
always @(posedge HCLK or negedge HRSTn)
if(~HRSTn)
err[5] <= 1'b0;
else if(err_st[5])
err[5] <= 1'b1;
else if(err_clr[5])
err[5] <= 1'b0;
always @(posedge HCLK or negedge HRSTn)
if(~HRSTn)
abt[5] <= 1'b0;
else if(abt_st[5])
abt[5] <= 1'b1;
else if(abt_clr[5])
abt[5] <= 1'b0;
`endif
`ifdef DMA_HAVE_CH6
always @(posedge HCLK or negedge HRSTn)
if(~HRSTn)
err[6] <= 1'b0;
else if(err_st[6])
err[6] <= 1'b1;
else if(err_clr[6])
err[6] <= 1'b0;
always @(posedge HCLK or negedge HRSTn)
if(~HRSTn)
abt[6] <= 1'b0;
else if(abt_st[6])
abt[6] <= 1'b1;
else if(abt_clr[6])
abt[6] <= 1'b0;
`endif
`ifdef DMA_HAVE_CH7
always @(posedge HCLK or negedge HRSTn)
if(~HRSTn)
err[7] <= 1'b0;
else if(err_st[7])
err[7] <= 1'b1;
else if(err_clr[7])
err[7] <= 1'b0;
always @(posedge HCLK or negedge HRSTn)
if(~HRSTn)
abt[7] <= 1'b0;
else if(abt_st[7])
abt[7] <= 1'b1;
else if(abt_clr[7])
abt[7] <= 1'b0;
`endif
assign ch_en = {c7csr[0],c6csr[0],c5csr[0],c4csr[0],c3csr[0],
c2csr[0],c1csr[0],c0csr[0]};
assign ch_busy = {c7cfg[`DMA_CHBUSY],c6cfg[`DMA_CHBUSY],
c5cfg[`DMA_CHBUSY],c4cfg[`DMA_CHBUSY],
c3cfg[`DMA_CHBUSY],c2cfg[`DMA_CHBUSY],
c1cfg[`DMA_CHBUSY],c0cfg[`DMA_CHBUSY]};
wire csr_b0we = csr_we & be_d1[0];
always @(posedge HCLK or negedge HRSTn)
if(~HRSTn)
m1end <= 1'b0;
else if(csr_b0we)
m1end <= slv_wdti[2];
always @(posedge HCLK or negedge HRSTn)
if(~HRSTn)
m0end <= 1'b0;
else if(csr_b0we)
m0end <= slv_wdti[1];
always @(posedge HCLK or negedge HRSTn)
if(~HRSTn)
dmacen <= 1'b0;
else if(csr_b0we)
dmacen <= slv_wdti[0];
assign csr = { m1end, m0end, dmacen};
wire sync_b0we = sync_we & be_d1[0];
always @(posedge HCLK or negedge HRSTn)
if(~HRSTn)
sync <= 'b0;
else if(sync_b0we)
sync <= slv_wdti[`DMA_MAX_CHNO-1:0];
`ifdef DMA_HAVE_AHB1
`ifdef DMA_HAVE_BRIDGE
wire c0dbs_b2we = c0dbs_we & be_d1[2];
wire c0dbs_b3we = c0dbs_we & be_d1[3];
always @(posedge HCLK or negedge HRSTn)
if(~HRSTn)
c0dmabs[23:16] <= 'h0;
else if(c0dbs_b2we)
c0dmabs[23:16] <= slv_wdti[23:16];
always @(posedge HCLK or negedge HRSTn)
if(~HRSTn)
c0dmabs[31:24] <= 'h0;
else if(c0dbs_b3we)
c0dmabs[31:24] <= slv_wdti[31:24];
`ifdef DMA_HAVE_CH1
wire c1dbs_b2we = c1dbs_we & be_d1[2];
wire c1dbs_b3we = c1dbs_we & be_d1[3];
always @(posedge HCLK or negedge HRSTn)
if(~HRSTn)
c1dmabs[23:16] <= 'h0;
else if(c1dbs_b2we)
c1dmabs[23:16] <= slv_wdti[23:16];
always @(posedge HCLK or negedge HRSTn)
if(~HRSTn)
c1dmabs[31:24] <= 'h0;
else if(c1dbs_b3we)
c1dmabs[31:24] <= slv_wdti[31:24];
`endif
`ifdef DMA_HAVE_CH2
wire c2dbs_b2we = c2dbs_we & be_d1[2];
wire c2dbs_b3we = c2dbs_we & be_d1[3];
always @(posedge HCLK or negedge HRSTn)
if(~HRSTn)
c2dmabs[23:16] <= 'h0;
else if(c2dbs_b2we)
c2dmabs[23:16] <= slv_wdti[23:16];
always @(posedge HCLK or negedge HRSTn)
if(~HRSTn)
c2dmabs[31:24] <= 'h0;
else if(c2dbs_b3we)
c2dmabs[31:24] <= slv_wdti[31:24];
`endif
`ifdef DMA_HAVE_CH3
wire c3dbs_b2we = c3dbs_we & be_d1[2];
wire c3dbs_b3we = c3dbs_we & be_d1[3];
always @(posedge HCLK or negedge HRSTn)
if(~HRSTn)
c3dmabs[23:16] <= 'h0;
else if(c3dbs_b2we)
c3dmabs[23:16] <= slv_wdti[23:16];
always @(posedge HCLK or negedge HRSTn)
if(~HRSTn)
c3dmabs[31:24] <= 'h0;
else if(c3dbs_b3we)
c3dmabs[31:24] <= slv_wdti[31:24];
`endif
`ifdef DMA_HAVE_CH4
wire c4dbs_b2we = c4dbs_we & be_d1[2];
wire c4dbs_b3we = c4dbs_we & be_d1[3];
always @(posedge HCLK or negedge HRSTn)
if(~HRSTn)
c4dmabs[23:16] <= 'h0;
else if(c4dbs_b2we)
c4dmabs[23:16] <= slv_wdti[23:16];
always @(posedge HCLK or negedge HRSTn)
if(~HRSTn)
c4dmabs[31:24] <= 'h0;
else if(c4dbs_b3we)
c4dmabs[31:24] <= slv_wdti[31:24];
`endif
`ifdef DMA_HAVE_CH5
wire c5dbs_b2we = c5dbs_we & be_d1[2];
wire c5dbs_b3we = c5dbs_we & be_d1[3];
always @(posedge HCLK or negedge HRSTn)
if(~HRSTn)
c5dmabs[23:16] <= 'h0;
else if(c5dbs_b2we)
c5dmabs[23:16] <= slv_wdti[23:16];
always @(posedge HCLK or negedge HRSTn)
if(~HRSTn)
c5dmabs[31:24] <= 'h0;
else if(c5dbs_b3we)
c5dmabs[31:24] <= slv_wdti[31:24];
`endif
`ifdef DMA_HAVE_CH6
wire c6dbs_b2we = c6dbs_we & be_d1[2];
wire c6dbs_b3we = c6dbs_we & be_d1[3];
always @(posedge HCLK or negedge HRSTn)
if(~HRSTn)
c6dmabs[23:16] <= 'h0;
else if(c6dbs_b2we)
c6dmabs[23:16] <= slv_wdti[23:16];
always @(posedge HCLK or negedge HRSTn)
if(~HRSTn)
c6dmabs[31:24] <= 'h0;
else if(c6dbs_b3we)
c6dmabs[31:24] <= slv_wdti[31:24];
`endif
`ifdef DMA_HAVE_CH7
wire c7dbs_b2we = c7dbs_we & be_d1[2];
wire c7dbs_b3we = c7dbs_we & be_d1[3];
always @(posedge HCLK or negedge HRSTn)
if(~HRSTn)
c7dmabs[23:16] <= 'h0;
else if(c7dbs_b2we)
c7dmabs[23:16] <= slv_wdti[23:16];
always @(posedge HCLK or negedge HRSTn)
if(~HRSTn)
c7dmabs[31:24] <= 'h0;
else if(c7dbs_b3we)
c7dmabs[31:24] <= slv_wdti[31:24];
`endif
wire c0bbs_b2we = c0bbs_we & be_d1[2];
wire c0bbs_b3we = c0bbs_we & be_d1[3];
always @(posedge HCLK or negedge HRSTn)
if(~HRSTn)
c0brbs[23:16] <= 'h0;
else if(c0bbs_b2we)
c0brbs[23:16] <= slv_wdti[23:16];
always @(posedge HCLK or negedge HRSTn)
if(~HRSTn)
c0brbs[31:24] <= 'h0;
else if(c0bbs_b3we)
c0brbs[31:24] <= slv_wdti[31:24];
`ifdef DMA_HAVE_CH1
wire c1bbs_b2we = c1bbs_we & be_d1[2];
wire c1bbs_b3we = c1bbs_we & be_d1[3];
always @(posedge HCLK or negedge HRSTn)
if(~HRSTn)
c1brbs[23:16] <= 'h0;
else if(c1bbs_b2we)
c1brbs[23:16] <= slv_wdti[23:16];
always @(posedge HCLK or negedge HRSTn)
if(~HRSTn)
c1brbs[31:24] <= 'h0;
else if(c1bbs_b3we)
c1brbs[31:24] <= slv_wdti[31:24];
`endif
`ifdef DMA_HAVE_CH2
wire c2bbs_b2we = c2bbs_we & be_d1[2];
wire c2bbs_b3we = c2bbs_we & be_d1[3];
always @(posedge HCLK or negedge HRSTn)
if(~HRSTn)
c2brbs[23:16] <= 'h0;
else if(c2bbs_b2we)
c2brbs[23:16] <= slv_wdti[23:16];
always @(posedge HCLK or negedge HRSTn)
if(~HRSTn)
c2brbs[31:24] <= 'h0;
else if(c2bbs_b3we)
c2brbs[31:24] <= slv_wdti[31:24];
`endif
`ifdef DMA_HAVE_CH3
wire c3bbs_b2we = c3bbs_we & be_d1[2];
wire c3bbs_b3we = c3bbs_we & be_d1[3];
always @(posedge HCLK or negedge HRSTn)
if(~HRSTn)
c3brbs[23:16] <= 'h0;
else if(c3bbs_b2we)
c3brbs[23:16] <= slv_wdti[23:16];
always @(posedge HCLK or negedge HRSTn)
if(~HRSTn)
c3brbs[31:24] <= 'h0;
else if(c3bbs_b3we)
c3brbs[31:24] <= slv_wdti[31:24];
`endif
`ifdef DMA_HAVE_CH4
wire c4bbs_b2we = c4bbs_we & be_d1[2];
wire c4bbs_b3we = c4bbs_we & be_d1[3];
always @(posedge HCLK or negedge HRSTn)
if(~HRSTn)
c4brbs[23:16] <= 'h0;
else if(c4bbs_b2we)
c4brbs[23:16] <= slv_wdti[23:16];
always @(posedge HCLK or negedge HRSTn)
if(~HRSTn)
c4brbs[31:24] <= 'h0;
else if(c4bbs_b3we)
c4brbs[31:24] <= slv_wdti[31:24];
`endif
`ifdef DMA_HAVE_CH5
wire c5bbs_b2we = c5bbs_we & be_d1[2];
wire c5bbs_b3we = c5bbs_we & be_d1[3];
always @(posedge HCLK or negedge HRSTn)
if(~HRSTn)
c5brbs[23:16] <= 'h0;
else if(c5bbs_b2we)
c5brbs[23:16] <= slv_wdti[23:16];
always @(posedge HCLK or negedge HRSTn)
if(~HRSTn)
c5brbs[31:24] <= 'h0;
else if(c5bbs_b3we)
c5brbs[31:24] <= slv_wdti[31:24];
`endif
`ifdef DMA_HAVE_CH6
wire c6bbs_b2we = c6bbs_we & be_d1[2];
wire c6bbs_b3we = c6bbs_we & be_d1[3];
always @(posedge HCLK or negedge HRSTn)
if(~HRSTn)
c6brbs[23:16] <= 'h0;
else if(c6bbs_b2we)
c6brbs[23:16] <= slv_wdti[23:16];
always @(posedge HCLK or negedge HRSTn)
if(~HRSTn)
c6brbs[31:24] <= 'h0;
else if(c6bbs_b3we)
c6brbs[31:24] <= slv_wdti[31:24];
`endif
`ifdef DMA_HAVE_CH7
wire c7bbs_b2we = c7bbs_we & be_d1[2];
wire c7bbs_b3we = c7bbs_we & be_d1[3];
always @(posedge HCLK or negedge HRSTn)
if(~HRSTn)
c7brbs[23:16] <= 'h0;
else if(c7bbs_b2we)
c7brbs[23:16] <= slv_wdti[23:16];
always @(posedge HCLK or negedge HRSTn)
if(~HRSTn)
c7brbs[31:24] <= 'h0;
else if(c7bbs_b3we)
c7brbs[31:24] <= slv_wdti[31:24];
`endif
`endif
`endif
dma_chrf #(0) c0_rf(
.HCLK(HCLK),
.HRSTn(HRSTn),
.be_d1(be_d1),
.chcsr_we(c0csr_we),
.chcfg_we(c0cfg_we),
.chsad_we(c0sad_we),
.chdad_we(c0dad_we),
`ifdef DMA_HAVE_LINKLIST
.chllp_we(c0llp_we),
`endif
.chtsz_we(c0tsz_we),
.slv_wdti(slv_wdti),
.de_sad_we(de_sad_we),
.de_dad_we(de_dad_we),
`ifdef DMA_HAVE_LINKLIST
.de_llp_we(de_llp_we),
`endif
.de_tsz_we(de_tsz_we),
.de_en_clr(de_en_clr),
.de_csr_we(de_csr_we),
`ifdef DMA_HAVE_LINKLIST
.de_llpen_we(de_llpen_we),
`endif
.de_sad(de_sad),
.de_dad(de_dad),
`ifdef DMA_HAVE_LINKLIST
.de_llp(de_llp),
`endif
.de_tsz(de_tsz),
.de_csr(de_csr),
`ifdef DMA_HAVE_LINKLIST
.de_llpen(de_llpen),
.de_err_notify(de_err_notify),
.tsz_eq0(tsz_eq0),
`endif
.de_busy(de_busy),
.de_st_idle(de_st_idle),
.de_st_upd(de_st_upd),
.de_st_llp0(de_st_llp0),
.arb_ch_sel(arb_ch_sel),
.chcsr(c0csr),
.chcfg(c0cfg),
.chsad(c0sad),
.chdad(c0dad),
`ifdef DMA_HAVE_LINKLIST
.chllp(c0llp),
`endif
.chtsz(c0tsz),
`ifdef DMA_HAVE_LINKLIST
.chllpen(c0llpen),
`endif
.chabt(c0abt)
);
`ifdef DMA_HAVE_CH1
dma_chrf #(1) c1_rf(
.HCLK(HCLK),
.HRSTn(HRSTn),
.be_d1(be_d1),
.chcsr_we(c1csr_we),
.chcfg_we(c1cfg_we),
.chsad_we(c1sad_we),
.chdad_we(c1dad_we),
`ifdef DMA_HAVE_LINKLIST
.chllp_we(c1llp_we),
`endif
.chtsz_we(c1tsz_we),
.slv_wdti(slv_wdti),
.de_sad_we(de_sad_we),
.de_dad_we(de_dad_we),
`ifdef DMA_HAVE_LINKLIST
.de_llp_we(de_llp_we),
`endif
.de_tsz_we(de_tsz_we),
.de_en_clr(de_en_clr),
.de_csr_we(de_csr_we),
`ifdef DMA_HAVE_LINKLIST
.de_llpen_we(de_llpen_we),
`endif
.de_sad(de_sad),
.de_dad(de_dad),
`ifdef DMA_HAVE_LINKLIST
.de_llp(de_llp),
`endif
.de_tsz(de_tsz),
.de_csr(de_csr),
`ifdef DMA_HAVE_LINKLIST
.de_llpen(de_llpen),
.de_err_notify(de_err_notify),
.tsz_eq0(tsz_eq0),
`endif
.de_busy(de_busy),
.de_st_idle(de_st_idle),
.de_st_upd(de_st_upd),
.de_st_llp0(de_st_llp0),
.arb_ch_sel(arb_ch_sel),
.chcsr(c1csr),
.chcfg(c1cfg),
.chsad(c1sad),
.chdad(c1dad),
`ifdef DMA_HAVE_LINKLIST
.chllp(c1llp),
`endif
.chtsz(c1tsz),
`ifdef DMA_HAVE_LINKLIST
.chllpen(c1llpen),
`endif
.chabt(c1abt)
);
`else
assign c1csr[0] = 0;
assign c1cfg[`DMA_CHBUSY] = 0;
`endif
`ifdef DMA_HAVE_CH2
dma_chrf #(2) c2_rf(
.HCLK(HCLK),
.HRSTn(HRSTn),
.be_d1(be_d1),
.chcsr_we(c2csr_we),
.chcfg_we(c2cfg_we),
.chsad_we(c2sad_we),
.chdad_we(c2dad_we),
`ifdef DMA_HAVE_LINKLIST
.chllp_we(c2llp_we),
`endif
.chtsz_we(c2tsz_we),
.slv_wdti(slv_wdti),
.de_sad_we(de_sad_we),
.de_dad_we(de_dad_we),
`ifdef DMA_HAVE_LINKLIST
.de_llp_we(de_llp_we),
`endif
.de_tsz_we(de_tsz_we),
.de_en_clr(de_en_clr),
.de_csr_we(de_csr_we),
`ifdef DMA_HAVE_LINKLIST
.de_llpen_we(de_llpen_we),
`endif
.de_sad(de_sad),
.de_dad(de_dad),
`ifdef DMA_HAVE_LINKLIST
.de_llp(de_llp),
`endif
.de_tsz(de_tsz),
.de_csr(de_csr),
`ifdef DMA_HAVE_LINKLIST
.de_llpen(de_llpen),
.de_err_notify(de_err_notify),
.tsz_eq0(tsz_eq0),
`endif
.de_busy(de_busy),
.de_st_idle(de_st_idle),
.de_st_upd(de_st_upd),
.de_st_llp0(de_st_llp0),
.arb_ch_sel(arb_ch_sel),
.chcsr(c2csr),
.chcfg(c2cfg),
.chsad(c2sad),
.chdad(c2dad),
`ifdef DMA_HAVE_LINKLIST
.chllp(c2llp),
`endif
.chtsz(c2tsz),
`ifdef DMA_HAVE_LINKLIST
.chllpen(c2llpen),
`endif
.chabt(c2abt)
);
`else
assign c2csr[0] = 0;
assign c2cfg[`DMA_CHBUSY] = 0;
`endif
`ifdef DMA_HAVE_CH3
dma_chrf #(3) c3_rf(
.HCLK(HCLK),
.HRSTn(HRSTn),
.be_d1(be_d1),
.chcsr_we(c3csr_we),
.chcfg_we(c3cfg_we),
.chsad_we(c3sad_we),
.chdad_we(c3dad_we),
`ifdef DMA_HAVE_LINKLIST
.chllp_we(c3llp_we),
`endif
.chtsz_we(c3tsz_we),
.slv_wdti(slv_wdti),
.de_sad_we(de_sad_we),
.de_dad_we(de_dad_we),
`ifdef DMA_HAVE_LINKLIST
.de_llp_we(de_llp_we),
`endif
.de_tsz_we(de_tsz_we),
.de_en_clr(de_en_clr),
.de_csr_we(de_csr_we),
`ifdef DMA_HAVE_LINKLIST
.de_llpen_we(de_llpen_we),
`endif
.de_sad(de_sad),
.de_dad(de_dad),
`ifdef DMA_HAVE_LINKLIST
.de_llp(de_llp),
`endif
.de_tsz(de_tsz),
.de_csr(de_csr),
`ifdef DMA_HAVE_LINKLIST
.de_llpen(de_llpen),
.de_err_notify(de_err_notify),
.tsz_eq0(tsz_eq0),
`endif
.de_busy(de_busy),
.de_st_idle(de_st_idle),
.de_st_upd(de_st_upd),
.de_st_llp0(de_st_llp0),
.arb_ch_sel(arb_ch_sel),
.chcsr(c3csr),
.chcfg(c3cfg),
.chsad(c3sad),
.chdad(c3dad),
`ifdef DMA_HAVE_LINKLIST
.chllp(c3llp),
`endif
.chtsz(c3tsz),
`ifdef DMA_HAVE_LINKLIST
.chllpen(c3llpen),
`endif
.chabt(c3abt)
);
`else
assign c3csr[0] = 0;
assign c3cfg[`DMA_CHBUSY] = 0;
`endif
`ifdef DMA_HAVE_CH4
dma_chrf #(4) c4_rf(
.HCLK(HCLK),
.HRSTn(HRSTn),
.be_d1(be_d1),
.chcsr_we(c4csr_we),
.chcfg_we(c4cfg_we),
.chsad_we(c4sad_we),
.chdad_we(c4dad_we),
`ifdef DMA_HAVE_LINKLIST
.chllp_we(c4llp_we),
`endif
.chtsz_we(c4tsz_we),
.slv_wdti(slv_wdti),
.de_sad_we(de_sad_we),
.de_dad_we(de_dad_we),
`ifdef DMA_HAVE_LINKLIST
.de_llp_we(de_llp_we),
`endif
.de_tsz_we(de_tsz_we),
.de_en_clr(de_en_clr),
.de_csr_we(de_csr_we),
`ifdef DMA_HAVE_LINKLIST
.de_llpen_we(de_llpen_we),
`endif
.de_sad(de_sad),
.de_dad(de_dad),
`ifdef DMA_HAVE_LINKLIST
.de_llp(de_llp),
`endif
.de_tsz(de_tsz),
.de_csr(de_csr),
`ifdef DMA_HAVE_LINKLIST
.de_llpen(de_llpen),
.de_err_notify(de_err_notify),
.tsz_eq0(tsz_eq0),
`endif
.de_busy(de_busy),
.de_st_idle(de_st_idle),
.de_st_upd(de_st_upd),
.de_st_llp0(de_st_llp0),
.arb_ch_sel(arb_ch_sel),
.chcsr(c4csr),
.chcfg(c4cfg),
.chsad(c4sad),
.chdad(c4dad),
`ifdef DMA_HAVE_LINKLIST
.chllp(c4llp),
`endif
.chtsz(c4tsz),
`ifdef DMA_HAVE_LINKLIST
.chllpen(c4llpen),
`endif
.chabt(c4abt)
);
`else
assign c4csr[0] = 0;
assign c4cfg[`DMA_CHBUSY] = 0;
`endif
`ifdef DMA_HAVE_CH5
dma_chrf #(5) c5_rf(
.HCLK(HCLK),
.HRSTn(HRSTn),
.be_d1(be_d1),
.chcsr_we(c5csr_we),
.chcfg_we(c5cfg_we),
.chsad_we(c5sad_we),
.chdad_we(c5dad_we),
`ifdef DMA_HAVE_LINKLIST
.chllp_we(c5llp_we),
`endif
.chtsz_we(c5tsz_we),
.slv_wdti(slv_wdti),
.de_sad_we(de_sad_we),
.de_dad_we(de_dad_we),
`ifdef DMA_HAVE_LINKLIST
.de_llp_we(de_llp_we),
`endif
.de_tsz_we(de_tsz_we),
.de_en_clr(de_en_clr),
.de_csr_we(de_csr_we),
`ifdef DMA_HAVE_LINKLIST
.de_llpen_we(de_llpen_we),
`endif
.de_sad(de_sad),
.de_dad(de_dad),
`ifdef DMA_HAVE_LINKLIST
.de_llp(de_llp),
`endif
.de_tsz(de_tsz),
.de_csr(de_csr),
`ifdef DMA_HAVE_LINKLIST
.de_llpen(de_llpen),
.de_err_notify(de_err_notify),
.tsz_eq0(tsz_eq0),
`endif
.de_busy(de_busy),
.de_st_idle(de_st_idle),
.de_st_upd(de_st_upd),
.de_st_llp0(de_st_llp0),
.arb_ch_sel(arb_ch_sel),
.chcsr(c5csr),
.chcfg(c5cfg),
.chsad(c5sad),
.chdad(c5dad),
`ifdef DMA_HAVE_LINKLIST
.chllp(c5llp),
`endif
.chtsz(c5tsz),
`ifdef DMA_HAVE_LINKLIST
.chllpen(c5llpen),
`endif
.chabt(c5abt)
);
`else
assign c5csr[0] = 0;
assign c5cfg[`DMA_CHBUSY] = 0;
`endif
`ifdef DMA_HAVE_CH6
dma_chrf #(6) c6_rf(
.HCLK(HCLK),
.HRSTn(HRSTn),
.be_d1(be_d1),
.chcsr_we(c6csr_we),
.chcfg_we(c6cfg_we),
.chsad_we(c6sad_we),
.chdad_we(c6dad_we),
`ifdef DMA_HAVE_LINKLIST
.chllp_we(c6llp_we),
`endif
.chtsz_we(c6tsz_we),
.slv_wdti(slv_wdti),
.de_sad_we(de_sad_we),
.de_dad_we(de_dad_we),
`ifdef DMA_HAVE_LINKLIST
.de_llp_we(de_llp_we),
`endif
.de_tsz_we(de_tsz_we),
.de_en_clr(de_en_clr),
.de_csr_we(de_csr_we),
`ifdef DMA_HAVE_LINKLIST
.de_llpen_we(de_llpen_we),
`endif
.de_sad(de_sad),
.de_dad(de_dad),
`ifdef DMA_HAVE_LINKLIST
.de_llp(de_llp),
`endif
.de_tsz(de_tsz),
.de_csr(de_csr),
`ifdef DMA_HAVE_LINKLIST
.de_llpen(de_llpen),
.de_err_notify(de_err_notify),
.tsz_eq0(tsz_eq0),
`endif
.de_busy(de_busy),
.de_st_idle(de_st_idle),
.de_st_upd(de_st_upd),
.de_st_llp0(de_st_llp0),
.arb_ch_sel(arb_ch_sel),
.chcsr(c6csr),
.chcfg(c6cfg),
.chsad(c6sad),
.chdad(c6dad),
`ifdef DMA_HAVE_LINKLIST
.chllp(c6llp),
`endif
.chtsz(c6tsz),
`ifdef DMA_HAVE_LINKLIST
.chllpen(c6llpen),
`endif
.chabt(c6abt)
);
`else
assign c6csr[0] = 0;
assign c6cfg[`DMA_CHBUSY] = 0;
`endif
`ifdef DMA_HAVE_CH7
dma_chrf #(7) c7_rf(
.HCLK(HCLK),
.HRSTn(HRSTn),
.be_d1(be_d1),
.chcsr_we(c7csr_we),
.chcfg_we(c7cfg_we),
.chsad_we(c7sad_we),
.chdad_we(c7dad_we),
`ifdef DMA_HAVE_LINKLIST
.chllp_we(c7llp_we),
`endif
.chtsz_we(c7tsz_we),
.slv_wdti(slv_wdti),
.de_sad_we(de_sad_we),
.de_dad_we(de_dad_we),
`ifdef DMA_HAVE_LINKLIST
.de_llp_we(de_llp_we),
`endif
.de_tsz_we(de_tsz_we),
.de_en_clr(de_en_clr),
.de_csr_we(de_csr_we),
`ifdef DMA_HAVE_LINKLIST
.de_llpen_we(de_llpen_we),
`endif
.de_sad(de_sad),
.de_dad(de_dad),
`ifdef DMA_HAVE_LINKLIST
.de_llp(de_llp),
`endif
.de_tsz(de_tsz),
.de_csr(de_csr),
`ifdef DMA_HAVE_LINKLIST
.de_llpen(de_llpen),
.de_err_notify(de_err_notify),
.tsz_eq0(tsz_eq0),
`endif
.de_busy(de_busy),
.de_st_idle(de_st_idle),
.de_st_upd(de_st_upd),
.de_st_llp0(de_st_llp0),
.arb_ch_sel(arb_ch_sel),
.chcsr(c7csr),
.chcfg(c7cfg),
.chsad(c7sad),
.chdad(c7dad),
`ifdef DMA_HAVE_LINKLIST
.chllp(c7llp),
`endif
.chtsz(c7tsz),
`ifdef DMA_HAVE_LINKLIST
.chllpen(c7llpen),
`endif
.chabt(c7abt)
);
`else
assign c7csr[0] = 0;
assign c7cfg[`DMA_CHBUSY] = 0;
`endif
endmodule
|
`include "DMA_DEFINE.vh"
module dma_engine
(
HCLK,
HRSTn,
de_st,
de_err_notify,
`ifdef DMA_HAVE_LINKLIST
st_llp0t3,
`endif
dst_m,src_m,
dst_a,src_a,
dst_e,src_e,
dst_wid_wd, src_wid_wd,
dst_wid_hw, src_wid_hw,
dst_wid_bt, src_wid_bt,
bst_eq0,bst_eq1, bst_eq2,
tsz_eq0,tsz_eq1, tsz_eq2,
cv8t32,
cv8t16,
cv16t32,
cvtp2,
pack_en,
pack_end,
unpack_en,
upk_cnteq0,
upk_cnteq1,
fwdtsb0,
fwdtsb1,
fwdtsb2,
fwdtsb3,
m0_ad1t0x,
m0_updad,
m0_rdy,
m0_rdt,
m0_cp,
m0_tr_sq,
m0_rp_err,
m0_rp_rty,
m0_dt_st,
m0_dma_err_ok,
m0_is_dst,
m0_is_src,
`ifdef DMA_HAVE_LINKLIST
m0_is_llp,
`endif
m0_arb_src,
m0_arb_dst,
`ifdef DMA_HAVE_AHB1
m1_ad1t0x,
m1_updad,
m1_rdy,
m1_rdt,
m1_cp,
m1_tr_sq,
m1_rp_err,
m1_rp_rty,
m1_dt_st,
m1_dtp,
m1_dma_had_a_rty,
m1_dma_err_ok,
m1_is_dst,
m1_is_src,
`ifdef DMA_HAVE_LINKLIST
m1_is_llp,
`endif
m1_arb_src,
m1_arb_dst,
m1_src2br,
m0_m1_same,
`endif
`ifdef DMA_HAVE_AHB1
`ifdef DMA_HAVE_BRIDGE
m1_arb_br,
slv_br_req,
slv_brst_cmd,
slv_brst_mscd,
br_req_qf,
`endif
`endif
ff_eq1,
ff_eq2,
ff_2ltfl,
ff_1ltfl,
ff_part_wd,
ff_cbe,
ff_cnv_q_vld,
ff_wr,
de_ff_push,
de_ff_pop,
de_ff_ahead,
de_ff_flush,
de_ff_clear,
de_ff_ini,
de_ff_ado,
de_ff_dto,
arb_req,
arb_chcsr,
`ifdef DMA_HAVE_LINKLIST
arb_chllp,
`endif
arb_chtsz,
`ifdef DMA_HAVE_LINKLIST
arb_chllpen,
`endif
de_ack,
de_tc_st,
rf_cherr,
arb_chabt,
arb_abt_any,
de_sad,
de_dad,
`ifdef DMA_HAVE_LINKLIST
de_llp,
de_mllp,
`endif
de_tsz,
de_csr,
`ifdef DMA_HAVE_LINKLIST
de_llpen,
`endif
de_busy,
de_sad_we,
de_dad_we,
de_tsz_we,
`ifdef DMA_HAVE_LINKLIST
de_llp_we,
de_csr_we,
de_llpen_we,
`endif
de_en_clr,
de_abt_on_idle,
de_err_st
);
input HCLK;
input HRSTn;
output [10:0] de_st;
output de_err_notify;
`ifdef DMA_HAVE_LINKLIST
output st_llp0t3;
`endif
output dst_m,src_m;
output dst_a,src_a;
output dst_e,src_e;
output dst_wid_wd, src_wid_wd;
output dst_wid_hw, src_wid_hw;
output dst_wid_bt, src_wid_bt;
output bst_eq0,bst_eq1, bst_eq2;
output tsz_eq0,tsz_eq1, tsz_eq2;
output cv8t32;
output cv8t16;
output cv16t32;
output cvtp2;
output pack_en;
output pack_end;
output unpack_en;
output upk_cnteq0;
output upk_cnteq1;
output [1:0] fwdtsb0;
output [1:0] fwdtsb1;
output [1:0] fwdtsb2;
output [1:0] fwdtsb3;
input [1:0] m0_ad1t0x;
input [`DMA_HADDR_WIDTH-1:0] m0_updad;
input m0_rdy;
input [`DMA_HDATA_WIDTH-1:0] m0_rdt;
input m0_cp;
input m0_tr_sq;
input m0_rp_err;
input m0_rp_rty;
input m0_dt_st;
input m0_dma_err_ok;
output m0_is_dst;
output m0_is_src;
`ifdef DMA_HAVE_LINKLIST
output m0_is_llp;
`endif
output m0_arb_src;
output m0_arb_dst;
`ifdef DMA_HAVE_AHB1
input [1:0] m1_ad1t0x;
input [`DMA_HADDR_WIDTH-1:0] m1_updad;
input m1_rdy;
input [`DMA_HDATA_WIDTH-1:0] m1_rdt;
input m1_cp;
input m1_tr_sq;
input m1_rp_err;
input m1_rp_rty;
input m1_dt_st;
input m1_dtp;
input m1_dma_had_a_rty;
input m1_dma_err_ok;
output m1_is_dst;
output m1_is_src;
`ifdef DMA_HAVE_LINKLIST
output m1_is_llp;
`endif
output m1_arb_src;
output m1_arb_dst;
output m1_src2br;
output m0_m1_same;
`ifdef DMA_HAVE_BRIDGE
output m1_arb_br;
input slv_br_req;
input slv_brst_cmd;
input slv_brst_mscd;
output br_req_qf;
`endif
`endif
input ff_eq1;
input ff_eq2;
input ff_2ltfl;
input ff_1ltfl;
input ff_part_wd;
input [3:0] ff_cbe;
input ff_cnv_q_vld;
input ff_wr;
output de_ff_push;
output de_ff_pop;
output de_ff_ahead;
output de_ff_flush;
output de_ff_clear;
output de_ff_ini;
output [1:0] de_ff_ado;
output [`DMA_HDATA_WIDTH-1:0] de_ff_dto;
input arb_req;
input [`DMA_CHCSR_WIDTH-1:0] arb_chcsr;
`ifdef DMA_HAVE_LINKLIST
input [`DMA_HADDR_WIDTH-1:0] arb_chllp;
`endif
input [`DMA_CHSZ_WIDTH-1:0] arb_chtsz;
`ifdef DMA_HAVE_LINKLIST
input arb_chllpen;
`endif
output de_ack;
output de_tc_st;
input rf_cherr;
input arb_chabt;
input arb_abt_any;
output [`DMA_HADDR_WIDTH-1:0] de_sad;
output [`DMA_HADDR_WIDTH-1:0] de_dad;
`ifdef DMA_HAVE_LINKLIST
output [`DMA_HADDR_WIDTH-1:0] de_llp;
output [`DMA_HADDR_WIDTH-1:2] de_mllp;
`endif
output [`DMA_CHSZ_WIDTH-1:0] de_tsz;
output [`DMA_HDATA_WIDTH-1:0] de_csr;
`ifdef DMA_HAVE_LINKLIST
output de_llpen;
`endif
output de_busy;
output de_sad_we;
output de_dad_we;
output de_tsz_we;
`ifdef DMA_HAVE_LINKLIST
output de_llp_we;
output de_csr_we;
output de_llpen_we;
`endif
output de_en_clr;
output de_abt_on_idle;
output de_err_st;
parameter
DE_ST_IDLE = 11'b000_0000_0001,
DE_ST_RD = 11'b000_0000_0010,
DE_ST_LR = 11'b000_0000_0100,
DE_ST_RDEND = 11'b000_0000_1000,
DE_ST_LW = 11'b000_0001_0000,
DE_ST_UPDATE = 11'b000_0010_0000,
DE_ST_LLP0 = 11'b000_0100_0000,
DE_ST_LLP1 = 11'b000_1000_0000,
DE_ST_LLP2 = 11'b001_0000_0000,
DE_ST_LLP3 = 11'b010_0000_0000,
DE_ST_LLP4 = 11'b100_0000_0000;
reg [10:0] de_st, de_nx_st;
reg de_err_notify;
reg de_ff_flush_d1;
reg st_ed1s;
wire st_idle, st_rd, st_rd_end, st_update;
wire st_lr, st_lw, st_llp0, st_llp1, st_llp2;
wire st_llp3, st_llp4;
wire arb_req_qf;
wire mp_err;
wire llp_on;
wire st_llp0t3,st_llp0t4;
wire st_rd_bgn;
wire st_ed2lw_s1,st_ed2lw_s20,st_ed2lw_s21;
wire st_len0_bgn;
wire st_rd2lr;
wire st_lr2up;
wire st_lr2ed;
wire st_llp_bgn;
wire st_llp_adv;
wire m0_vld_dtp;
wire m1_vld_dtp;
wire pack_en;
wire pack_end;
wire unpack_en;
wire upk_cnteq0,upk_cnteq1;
wire uptp8;
wire cv32t8;
wire cv32t16;
wire cv16t8;
wire cv8t32;
wire cv8t16;
wire cv16t32;
wire m0_is_src;
wire m1_is_src;
wire m0_is_dst;
wire m1_is_dst;
wire m0_is_id,m0_id_ns;
wire m1_is_id,m1_id_ns;
wire m0_m1_same;
wire m0_isOidOlp, m1_isOidOlp;
reg m1_is_llp;
wire m0_src2dst;
wire m0_dst2src;
wire m0_arb_src;
wire m0_arb_dst;
wire m1_src2dst;
wire m1_dst2src;
wire m1_src2br;
wire m1_dst2br;
wire m1_brs2src,m1_brs2dst;
wire m1_brd2src,m1_brd2dst,m1_err_or_rdy;
wire m1_arb_src;
wire m1_arb_dst;
wire m1_arb_brs;
wire m1_arb_brd;
wire m1_arb_br;
wire [`DMA_HDATA_WIDTH-1:0] mp_dt;
wire tsz_upd;
wire bst_upd;
wire sad_upd;
wire dad_upd;
wire [`DMA_HADDR_WIDTH-1:0] upd_sad;
wire [`DMA_HADDR_WIDTH-1:0] upd_dad;
wire de_ack;
wire src_wid_wd;
wire src_wid_hw;
wire src_wid_bt;
wire dst_wid_wd;
wire dst_wid_hw;
wire dst_wid_bt;
wire dst_m;
wire src_m;
wire dst_a;
wire src_a;
wire dst_e;
wire src_e;
wire arb_chtsz_eq0;
wire tsz_eq0;
wire tsz_eq1;
wire tsz_eq2;
wire bst_eq0;
wire bst_eq1;
wire bst_eq2;
wire br_req_qf;
wire m0_err,m1_err,m1_dma_err;
wire st_rd_1s;
wire llp_dprdy;
wire fsm_end;
`ifdef DMA_HAVE_AHB1
`else
wire [1:0] m1_ad1t0x ='b0;
wire [`DMA_HADDR_WIDTH-1:0] m1_updad ='b0;
wire m1_rdy ='b0;
wire [`DMA_HDATA_WIDTH-1:0] m1_rdt ='b0;
wire m1_cp ='b0;
wire m1_tr_sq ='b0;
wire m1_rp_err ='b0;
wire m1_rp_rty ='b0;
wire m1_dt_st ='b0;
wire slv_br_req ='b0;
wire slv_brst_cmd ='b0;
wire slv_brst_mscd ='b0;
`endif
reg m0_is_llp;
reg m0_arb_st;
reg [1:0] m1_arb_st,m1_arb_ns;
reg [`DMA_BSTCNT_WIDTH-1:0] bst_cnt;
reg [`DMA_CHSZ_WIDTH-1:0] tsz_cnt;
reg [1:0] upk_cnt0,upk_cnt1,upk_cnt_ii;
wire [1:0] upk_cnt_i;
assign st_idle = de_st[0];
assign st_rd = de_st[1];
assign st_lr = de_st[2];
assign st_rd_end = de_st[3];
assign st_lw = de_st[4];
assign st_update = de_st[5];
assign st_llp0 = de_st[6];
assign st_llp1 = de_st[7];
assign st_llp2 = de_st[8];
assign st_llp3 = de_st[9];
assign st_llp4 = de_st[10];
`ifdef DMA_HAVE_LINKLIST
assign llp_on = (|arb_chllp[31:2]&tsz_eq0);
`else
assign llp_on = 0;
`endif
`ifdef DMA_HAVE_LINKLIST
assign st_llp0t3 = st_llp0|st_llp1|st_llp2|st_llp3;
`endif
`ifdef DMA_HAVE_LINKLIST
assign st_llp0t4 = st_llp0t3|st_llp4;
`else
assign st_llp0t4 = 0;
`endif
`ifdef DMA_HAVE_LINKLIST
assign de_llpen_we = (st_update);
assign de_llpen = (llp_on);
wire de_mllp_we = st_idle&st_llp_bgn;
wire [`DMA_HADDR_WIDTH-1:2] upd_llp;
reg [`DMA_HADDR_WIDTH-1:2] de_mllp;
assign upd_llp = (m0_is_llp? m0_updad[31:2] : m1_updad[31:2]);
always @(posedge HCLK or negedge HRSTn)
if(~HRSTn)
de_mllp <= 'h0;
else if(de_mllp_we)
de_mllp <= arb_chllp[31:2];
else if(llp_dprdy)
de_mllp <= upd_llp;
`endif
wire de_err_ok;
wire md_rdy = (m0_is_dst&m0_rdy)|
(m1_is_dst&m1_rdy);
`ifdef DMA_HAVE_BRIDGE
wire m1_arb_src_dp = m1_arb_src;
wire m1_arb_dst_dp = m1_arb_dst;
`else
wire m1_arb_src_dp = m1_arb_src;
wire m1_arb_dst_dp = m1_arb_dst;
`endif
wire src_dprdy = (m0_is_src&m0_arb_src&m0_vld_dtp&m0_rdy)|
(m1_is_src&m1_arb_src_dp&m1_vld_dtp&m1_rdy);
wire dst_dprdy = (m0_is_dst&m0_arb_dst&m0_vld_dtp&m0_rdy)|
(m1_is_dst&m1_arb_dst_dp&m1_vld_dtp&m1_rdy);
wire s_d_dprdy = src_dprdy | dst_dprdy;
wire src_cprdy = (m0_is_src&m0_arb_src&m0_cp&m0_rdy)|
(m1_is_src&m1_arb_src&m1_cp&m1_rdy);
wire dst_cprdy = (m0_is_dst&m0_arb_dst&m0_cp&m0_rdy)|
(m1_is_dst&m1_arb_dst&m1_cp&m1_rdy);
wire dst_rty = (m0_is_dst&m0_arb_dst&m0_rp_rty&m0_vld_dtp)|
(m1_is_dst&m1_arb_dst&m1_rp_rty&m1_vld_dtp);
`ifdef DMA_HAVE_LINKLIST
assign llp_dprdy = (m0_is_llp&m0_vld_dtp&m0_rdy)|
(m1_is_llp&~m1_arb_br&m1_vld_dtp&m1_rdy);
`else
assign llp_dprdy = 1;
`endif
/*
assign ms_err = (m0_is_src&m0_arb_src&m0_err)|
(m1_is_src&m1_arb_src&m1_err);
assign md_err = (m0_is_dst&m0_arb_dst&m0_err)|
(m1_is_dst&m1_arb_dst&m1_err);
*/
`ifdef DMA_HAVE_LINKLIST
assign mp_err = (m0_is_llp&m0_err)|
(m1_is_llp&~m1_arb_br&m1_err);
`else
assign mp_err = 0;
`endif
assign de_abt_on_idle = st_idle&arb_abt_any;
assign arb_req_qf = arb_req&~de_abt_on_idle;
`ifdef DMA_HAVE_LINKLIST
`else
wire arb_chllpen = 0;
`endif
assign st_llp_bgn = (arb_req_qf&arb_chllpen);
assign st_rd_bgn = (arb_req_qf&~arb_chllpen);
assign st_len0_bgn = (arb_req_qf&~arb_chllpen&arb_chtsz_eq0);
assign st_rd2lr = m0_m1_same&(
((bst_eq2|tsz_eq2|(ff_2ltfl&~pack_en))&
src_dprdy) |
((bst_eq1|tsz_eq1)&src_cprdy) |
(ff_1ltfl&(pack_en&ff_cnv_q_vld)));
/*
assign st_rd2lr = ((bst_eq2|tsz_eq2|(ff_2ltfl&~pack_en))&
src_dprdy) |
((bst_eq1|tsz_eq1)&src_cprdy) |
(ff_1ltfl&(pack_en&ff_cnv_q_vld));
*/
assign st_lr2ed = src_dprdy;
assign st_lr2up = (de_err_ok);
wire st_rd2up = de_err_ok |
(!m0_m1_same&(bst_eq0|tsz_eq0)&!de_ff_flush_d1&!ff_wr&st_ed2lw_s20&dst_dprdy);
wire st_ed1swe = st_lr&st_lr2ed;
always @(posedge HCLK or negedge HRSTn)
if(~HRSTn)
st_ed1s <= 1'b1;
else if(st_ed1swe)
st_ed1s <= 1'b0;
else if(~st_ed1s)
st_ed1s <= 1'b1;
assign st_ed2lw_s1 = (((ff_eq1&~unpack_en)|(ff_eq2&upk_cnteq1))&dst_dprdy);
assign st_ed2lw_s20 = (ff_eq2&(~unpack_en|upk_cnteq0));
assign st_ed2lw_s21 = (st_ed2lw_s20&dst_cprdy);
wire st_ed2lw = st_ed1s & st_ed2lw_s1 & st_ed2lw_s21;
wire st_ed2up = (de_err_ok);
wire st_lw2rd = ~(bst_eq0|tsz_eq0) | dst_dprdy;
assign fsm_end = (bst_eq0|tsz_eq0)&ff_eq2&dst_dprdy;
wire st_lw2up = fsm_end |
arb_chabt |
s_d_dprdy |
de_err_ok;
assign m0_vld_dtp = m0_dt_st;
assign m1_vld_dtp = m1_dt_st;
`ifdef DMA_HAVE_LINKLIST
assign st_llp_adv = llp_dprdy;
wire st_llp2up = (mp_err);
`endif
always @(posedge HCLK or negedge HRSTn)
if(~HRSTn) de_st <= DE_ST_IDLE;
else de_st <= de_nx_st;
always @(de_st or st_rd_bgn or st_len0_bgn
or st_rd2up or st_rd2lr or st_lr2ed
or st_lr2up or st_lw2rd or st_ed2up
or st_ed2lw or st_lw2up
`ifdef DMA_HAVE_LINKLIST
or st_llp_bgn
or st_llp2up
or st_llp_adv
`endif
)
case(de_st)
DE_ST_IDLE:
if(st_len0_bgn)
de_nx_st = DE_ST_UPDATE;
else if(st_rd_bgn)
de_nx_st = DE_ST_RD;
`ifdef DMA_HAVE_LINKLIST
else if(st_llp_bgn)
de_nx_st = DE_ST_LLP0;
`endif
else
de_nx_st = DE_ST_IDLE;
DE_ST_RD:
if(st_rd2up)
de_nx_st = DE_ST_UPDATE;
else if(st_rd2lr)
de_nx_st = DE_ST_LR;
else
de_nx_st = DE_ST_RD;
DE_ST_LR:
if(st_lr2up)
de_nx_st = DE_ST_UPDATE;
else if(st_lr2ed)
de_nx_st = DE_ST_RDEND;
else
de_nx_st = DE_ST_LR;
DE_ST_RDEND:
if(st_ed2up)
de_nx_st = DE_ST_UPDATE;
else if(st_ed2lw)
de_nx_st = DE_ST_LW;
else
de_nx_st = DE_ST_RDEND;
DE_ST_LW:
if(st_lw2up)
de_nx_st = DE_ST_UPDATE;
else if(st_lw2rd)
de_nx_st = DE_ST_RD;
else
de_nx_st = DE_ST_LW;
DE_ST_UPDATE:
de_nx_st = DE_ST_IDLE;
`ifdef DMA_HAVE_LINKLIST
DE_ST_LLP0:
if(st_llp2up)
de_nx_st = DE_ST_UPDATE;
else if(st_llp_adv)
de_nx_st = DE_ST_LLP1;
else
de_nx_st = DE_ST_LLP0;
DE_ST_LLP1:
if(st_llp2up)
de_nx_st = DE_ST_UPDATE;
else if(st_llp_adv)
de_nx_st = DE_ST_LLP2;
else
de_nx_st = DE_ST_LLP1;
DE_ST_LLP2:
if(st_llp2up)
de_nx_st = DE_ST_UPDATE;
else if(st_llp_adv)
de_nx_st = DE_ST_LLP3;
else
de_nx_st = DE_ST_LLP2;
DE_ST_LLP3:
if(st_llp2up)
de_nx_st = DE_ST_UPDATE;
else if(st_llp_adv)
de_nx_st = DE_ST_LLP4;
else
de_nx_st = DE_ST_LLP3;
DE_ST_LLP4:
de_nx_st = DE_ST_RD;
`endif
default:
de_nx_st = DE_ST_IDLE;
endcase
assign de_busy = ~st_idle;
assign cv32t8 = (arb_chcsr[12]&~arb_chcsr[9]&~arb_chcsr[8]);
assign cv32t16 = (arb_chcsr[12]&arb_chcsr[8]);
assign cv16t8 = (arb_chcsr[11]&~arb_chcsr[9]&~arb_chcsr[8]);
assign cv8t32 = (~arb_chcsr[12]&~arb_chcsr[11]&arb_chcsr[9]&~arb_chcsr[5]);
assign cv8t16 = (~arb_chcsr[12]&~arb_chcsr[11]&arb_chcsr[8]&~arb_chcsr[5]);
assign cv16t32 = (arb_chcsr[11]&arb_chcsr[9]&~arb_chcsr[5]);
assign cvtp2 = ((~arb_chcsr[12]&~arb_chcsr[11]&arb_chcsr[8])|
(arb_chcsr[11]&arb_chcsr[9]))&
~arb_chcsr[5];
assign uptp8 = (arb_chcsr[11]|arb_chcsr[12])&(~arb_chcsr[9]&~arb_chcsr[8]);
assign pack_en = ((~arb_chcsr[12]&arb_chcsr[9])|
(~arb_chcsr[12]&~arb_chcsr[11]&arb_chcsr[8]))&
~arb_chcsr[5];
assign pack_end = ((ff_cbe[2]&cv8t32)|(~ff_cbe[3]&cvtp2));
assign unpack_en = (arb_chcsr[12]&~arb_chcsr[9])|
(arb_chcsr[11]&~arb_chcsr[9]&~arb_chcsr[8]);
assign m0_is_src = ~arb_chcsr[`DMA_CHCSR_SRC];
assign m1_is_src = arb_chcsr[`DMA_CHCSR_SRC];
assign m0_is_dst = ~arb_chcsr[`DMA_CHCSR_DST];
assign m1_is_dst = arb_chcsr[`DMA_CHCSR_DST];
assign m0_is_id = m0_is_src&m0_is_dst;
assign m0_id_ns = m0_is_dst&~m0_is_src;
assign m1_is_id = m1_is_src&m1_is_dst;
assign m1_id_ns = m1_is_dst&~m1_is_src;
`ifdef DMA_HAVE_AHB1
assign m0_m1_same = (m0_is_src&m0_is_dst)|
(m1_is_src&m1_is_dst);
`else
assign m0_m1_same = 1;
wire m1_dtp = 0;
wire m1_dma_had_a_rty = 0;
`endif
assign m0_isOidOlp = m0_is_src|m0_is_dst|m0_is_llp;
assign m1_isOidOlp = m1_is_src|m1_is_dst|m1_is_llp;
`ifdef DMA_HAVE_LINKLIST
always @(posedge HCLK or negedge HRSTn)
if(~HRSTn)
m0_is_llp <= 'h0;
else if(st_llp0)
m0_is_llp <= ~arb_chllp[0];
else if(st_llp4|st_update)
m0_is_llp <= 'h0;
always @(posedge HCLK or negedge HRSTn)
if(~HRSTn)
m1_is_llp <= 'h0;
else if(st_llp0)
m1_is_llp <= arb_chllp[0];
else if(st_llp4|st_update)
m1_is_llp <= 'h0;
`endif
assign m0_src2dst = (st_rd&m0_id_ns)|(st_lr&m0_vld_dtp&m0_is_id&m0_rdy);
assign m0_dst2src = (st_lw&m0_vld_dtp&m0_is_id&m0_rdy) | st_update;
assign m0_arb_src = ~m0_arb_st;
assign m0_arb_dst = m0_arb_st;
always @(posedge HCLK or negedge HRSTn)
if(~HRSTn)
m0_arb_st <= 1'b0;
else if(m0_src2dst)
m0_arb_st <= 1'b1;
else if(m0_dst2src)
m0_arb_st <= 1'b0;
assign m1_src2dst = (st_rd&m1_id_ns)|(st_lr&m1_vld_dtp&m1_is_id&m1_rdy);
assign m1_dst2src = (st_lw&m1_vld_dtp&m1_is_id&m1_rdy) | st_update;
`ifdef DMA_HAVE_BRIDGE
/*
assign m1_src2br = br_req_qf&((!(m1_cp&!m1_vld_dtp))&
(!m1_vld_dtp&m1_rdy));
assign m1_dst2br = br_req_qf&((!(m1_cp&!m1_vld_dtp))&
(!m1_vld_dtp&m1_rdy));
*/
assign m1_src2br = br_req_qf&!(m1_cp|m1_dtp)&!m1_dma_had_a_rty;
assign m1_dst2br = m1_src2br;
/*
assign m1_src2br = br_req_qf&(!(m1_cp&!m1_dtp))&
((!m1_dtp&m1_rdy)|
(!m1_cp&!m1_dtp));
assign m1_dst2br = br_req_qf&(!(m1_cp&!m1_dtp))&
((!m1_dtp&m1_rdy)|
(!m1_cp&!m1_dtp));
*/
assign m1_err_or_rdy = (m1_err|(m1_vld_dtp&m1_rdy));
assign m1_brd2src = slv_brst_mscd&(st_update|st_idle|st_llp0t4|
(st_rd&m1_is_src))&m1_err_or_rdy;
assign m1_brs2dst = slv_brst_mscd&(st_rd&m1_id_ns)&m1_err_or_rdy;
assign m1_brs2src = slv_brst_mscd&m1_err_or_rdy;
assign m1_brd2dst = slv_brst_mscd&m1_err_or_rdy;
`else
assign m1_src2br = 0;
assign m1_dst2br = 0;
assign m1_err_or_rdy = 0;
assign m1_brs2src = 0;
assign m1_brd2dst = 0;
`endif
assign m1_arb_src = (m1_arb_st == 2'b00);
assign m1_arb_dst = (m1_arb_st == 2'b01);
`ifdef DMA_HAVE_BRIDGE
assign m1_arb_brs = (m1_arb_st == 2'b10);
assign m1_arb_brd = (m1_arb_st == 2'b11);
`endif
`ifdef DMA_HAVE_BRIDGE
assign m1_arb_br = m1_arb_st[1];
`else
assign m1_arb_br = 0;
`endif
/* Daniel Modified 8/19/2003
always @(posedge HCLK or negedge HRSTn)
if(~HRSTn)
m1_arb_st <= 2'b00;
`ifdef DMA_HAVE_BRIDGE
else if(m1_arb_src&m1_src2br)
m1_arb_st <= 2'b10;
else if(m1_arb_brs&m1_br2src)
m1_arb_st <= 2'b00;
else if(m1_arb_dst&m1_dst2br)
m1_arb_st <= 2'b11;
else if(m1_arb_brd&m1_brd2src)
m1_arb_st <= 2'b00;
else if(m1_arb_brd&m1_br2dst)
m1_arb_st <= 2'b01;
`endif
else if(m1_arb_src&m1_src2dst)
m1_arb_st <= 2'b01;
else if(m1_arb_dst&m1_dst2src)
m1_arb_st <= 2'b00;
*/
parameter
M1_ARB_SRC = 2'b00,
M1_ARB_DST = 2'b01,
M1_ARB_BS = 2'b10,
M1_ARB_BD = 2'b11;
always @(posedge HCLK or negedge HRSTn)
if(~HRSTn)
m1_arb_st <= M1_ARB_SRC;
else
m1_arb_st <= m1_arb_ns;
always @(m1_arb_st
`ifdef DMA_HAVE_BRIDGE
or m1_src2br or m1_dst2br or m1_brs2dst or m1_brs2src
or m1_brd2src or m1_brd2dst
`endif
or m1_src2dst or m1_dst2src)
case(m1_arb_st)
M1_ARB_SRC: begin
`ifdef DMA_HAVE_BRIDGE
if(m1_src2br) m1_arb_ns = M1_ARB_BS;
else
`endif
if(m1_src2dst) m1_arb_ns = M1_ARB_DST;
else m1_arb_ns = M1_ARB_SRC;
end
M1_ARB_DST: begin
`ifdef DMA_HAVE_BRIDGE
if(m1_dst2br) m1_arb_ns = M1_ARB_BD;
else
`endif
if(m1_dst2src) m1_arb_ns = M1_ARB_SRC;
else m1_arb_ns = M1_ARB_DST;
end
`ifdef DMA_HAVE_BRIDGE
M1_ARB_BS: begin
if(m1_brs2dst) m1_arb_ns = M1_ARB_DST;
else if(m1_brs2src) m1_arb_ns = M1_ARB_SRC;
else m1_arb_ns = M1_ARB_BS;
end
M1_ARB_BD: begin
if(m1_brd2src) m1_arb_ns = M1_ARB_SRC;
else if(m1_brd2dst) m1_arb_ns = M1_ARB_DST;
else m1_arb_ns = M1_ARB_BD;
end
`endif
default:
m1_arb_ns = M1_ARB_SRC;
endcase
`ifdef DMA_HAVE_BRIDGE
assign br_req_qf = slv_br_req;
`endif
assign de_ff_ado = m0_is_src? m0_ad1t0x : m1_ad1t0x;
assign de_ff_push = ~st_idle&~st_llp0t4&src_dprdy;
assign de_ff_ahead = (((m0_is_dst&m0_tr_sq)|(m1_is_dst&m1_tr_sq))&upk_cnteq0);
assign de_ff_dto = (m0_is_src & m0_arb_src)? m0_rdt : m1_rdt;
assign de_ff_pop = (dst_dprdy&(~unpack_en|upk_cnteq0));
assign de_ff_flush = ((m0_m1_same&st_rd_end)|(!m0_m1_same))
& (bst_eq0 | tsz_eq0) & ff_part_wd;
always @(posedge HCLK or negedge HRSTn)
if(~HRSTn)
de_ff_flush_d1 <= 1'b0;
else
de_ff_flush_d1 <= de_ff_flush;
assign de_ff_clear = st_update;
assign de_ff_ini = st_rd_1s;
assign tsz_upd = src_dprdy;
assign bst_upd = src_dprdy;
assign sad_upd = src_dprdy;
assign dad_upd = dst_dprdy;
assign upd_sad = (m0_is_src? m0_updad : m1_updad);
assign upd_dad = (m0_is_dst? m0_updad : m1_updad);
wire [`DMA_CHSZ_WIDTH-1:0] upd_tsz = (tsz_cnt - 1);
`ifdef DMA_HAVE_LINKLIST
assign mp_dt = m0_is_llp? m0_rdt : m1_rdt;
`endif
`ifdef DMA_HAVE_LINKLIST
assign de_csr = mp_dt;
`endif
assign de_sad =
`ifdef DMA_HAVE_LINKLIST
st_llp0? mp_dt :
`endif
upd_sad;
assign de_dad =
`ifdef DMA_HAVE_LINKLIST
st_llp1? mp_dt :
`endif
upd_dad;
`ifdef DMA_HAVE_LINKLIST
assign de_llp = mp_dt;
`endif
assign de_tsz =
`ifdef DMA_HAVE_LINKLIST
st_llp3? mp_dt[`DMA_CHSZ_WIDTH-1:0]:
`endif
upd_tsz;
assign de_sad_we =
`ifdef DMA_HAVE_LINKLIST
(st_llp0&llp_dprdy)|
`endif
(~st_llp0t4&sad_upd);
assign de_dad_we =
`ifdef DMA_HAVE_LINKLIST
(st_llp1&llp_dprdy)|
`endif
(~st_llp0t4&dad_upd);
`ifdef DMA_HAVE_LINKLIST
assign de_llp_we = (st_llp2&llp_dprdy);
assign de_csr_we = (st_llp3&llp_dprdy);
`endif
assign de_tsz_we =
`ifdef DMA_HAVE_LINKLIST
(st_llp3&llp_dprdy)|
`endif
(~st_llp0t4&tsz_upd);
assign m0_err = m0_vld_dtp&m0_rp_err;
assign m1_err = m1_vld_dtp&m1_rp_err;
assign m1_dma_err= m1_err&~m1_arb_br;
assign de_en_clr = (st_update&(arb_chabt|
de_err_notify|
(~de_err_notify&tsz_eq0&~llp_on)
)
);
assign de_tc_st = (st_update&tsz_eq0&~de_err_notify);
assign de_err_st = m0_err|m1_dma_err;
always @(posedge HCLK or negedge HRSTn)
if(~HRSTn)
de_err_notify <= 1'b0;
else if(de_err_st)
de_err_notify <= 1'b1;
else if(st_update)
de_err_notify <= 1'b0;
`ifdef DMA_HAVE_AHB1
assign de_err_ok = de_err_notify & (!m0_isOidOlp|m0_dma_err_ok) &
(!m1_isOidOlp|m1_dma_err_ok);
`else
assign de_err_ok = de_err_notify & m0_dma_err_ok;
`endif
assign de_ack = st_update;
reg st_rd_msk;
reg [`DMA_BSTCNT_WIDTH-1:0] bst_cntin;
always @(posedge HCLK or negedge HRSTn)
if(~HRSTn)
st_rd_msk <= 1'b1;
else if(st_rd_msk&st_rd)
st_rd_msk <= 1'b0;
else if(~st_rd_msk&st_update)
st_rd_msk <= 1'b1;
assign st_rd_1s = st_rd & st_rd_msk;
always @(arb_chcsr)
case(arb_chcsr[`DMA_CHCSR_SSZ])
3'b000: bst_cntin = 'b0_0000_0001;
3'b001: bst_cntin = 'b0_0000_0100;
3'b010: bst_cntin = 'b0_0000_1000;
3'b011: bst_cntin = 'b0_0001_0000;
3'b100: bst_cntin = 'b0_0010_0000;
3'b101: bst_cntin = 'b0_0100_0000;
3'b110: bst_cntin = 'b0_1000_0000;
3'b111: bst_cntin = 'b1_0000_0000;
endcase
always @(posedge HCLK or negedge HRSTn)
if(~HRSTn)
bst_cnt <= 0;
else if(st_rd_1s)
bst_cnt <= bst_cntin;
else if(bst_upd)
bst_cnt <= bst_cnt-1;
wire tsz_ini = st_rd_1s;
always @(posedge HCLK or negedge HRSTn)
if(~HRSTn)
tsz_cnt <= 0;
else if(tsz_ini)
tsz_cnt <= arb_chtsz;
else if(tsz_upd)
tsz_cnt <= upd_tsz;
/*
When de_st is UPDATE state and total size reach 0,
DMAEN bit(on the csr register) will clear.
When terminal count(de_tc), write done register(and asserts INTERRUPT if enabled).
When burst length is reached, de_ack asserted then DMAC_ACK asserted.
When error(m0_rp_err|m1_rp_err and not bridge request) occured, latch and go to
UPDATE state as soon as possible. Set the ERR bit on Cn_Str. Set DMAEN bit
to 0.
When channel abort bit(ABT) is set, dma engine enters UPDATE state as soon as
possible and clear FIFO.
*/
wire cvupt2 = cv32t16|cv16t8;
wire ld_upk_cnt0 = st_rd_1s;
wire rl_upk_cnt0 = ((upk_cnt0==0)&dst_cprdy)|
dst_rty;
wire upk_cnt0_go = dst_cprdy;
wire upk_cnt1_go = dst_dprdy;
assign upk_cnteq0 = (upk_cnt1 == 0);
assign upk_cnteq1 = (upk_cnt1 == 1);
wire [1:0] upk_cnt0_fix = {upk_cnt0[1]^dst_m,upk_cnt0[0]^dst_m};
wire [1:0] fwdtsb0 = {((cv32t8&~upk_cnt0_fix[1])|(cv32t16&~upk_cnt0_fix[0])),
((uptp8&~upk_cnt0_fix[0])|~uptp8)};
wire [1:0] fwdtsb1 = {(((cv32t8&~upk_cnt0_fix[1])|(cv32t16&~upk_cnt0_fix[0]))|(~(cv32t8|cv32t16)&~cv16t8)),
(uptp8&~upk_cnt0_fix[0])};
wire [1:0] fwdtsb2 = {((cv32t8&~upk_cnt0_fix[1])|(cv32t16&~upk_cnt0_fix[0])),
(uptp8&~upk_cnt0_fix[0])};
wire [1:0] fwdtsb3 = {(((cv32t8&~upk_cnt0_fix[1])|(cv32t16&~upk_cnt0_fix[0]))|(~(cv32t8|cv32t16)&~cv16t8)),
((uptp8&~upk_cnt0_fix[0])|~uptp8)};
always @(cv32t8 or cvupt2)
case({cv32t8, cvupt2})
2'b01: upk_cnt_ii = 'b01;
2'b10: upk_cnt_ii = 'b11;
default:upk_cnt_ii = 'b00;
endcase
assign upk_cnt_i = dst_rty? upk_cnt1 : upk_cnt_ii;
always @(posedge HCLK or negedge HRSTn)
if(~HRSTn)
upk_cnt0 <= 'b0;
else if(ld_upk_cnt0)
upk_cnt0 <= upk_cnt_i;
else if(rl_upk_cnt0)
upk_cnt0 <= upk_cnt_i;
else if(upk_cnt0_go)
upk_cnt0 <= upk_cnt0 - 1;
always @(posedge HCLK or negedge HRSTn)
if(~HRSTn)
upk_cnt1 <= 'b0;
else if(ld_upk_cnt0)
upk_cnt1 <= upk_cnt_i;
else if(upk_cnt1_go)
upk_cnt1 <= upk_cnt0;
assign src_wid_wd = (arb_chcsr[`DMA_CHCSR_SWID] == `DMA_HSIZE_WORD);
assign src_wid_hw = (arb_chcsr[`DMA_CHCSR_SWID] == `DMA_HSIZE_HALFWORD);
assign src_wid_bt = (arb_chcsr[`DMA_CHCSR_SWID] == `DMA_HSIZE_BYTE);
assign dst_wid_wd = (arb_chcsr[`DMA_CHCSR_DWID] == `DMA_HSIZE_WORD);
assign dst_wid_hw = (arb_chcsr[`DMA_CHCSR_DWID] == `DMA_HSIZE_HALFWORD);
assign dst_wid_bt = (arb_chcsr[`DMA_CHCSR_DWID] == `DMA_HSIZE_BYTE);
assign dst_m = (~arb_chcsr[4]&
arb_chcsr[3]);
assign src_m = (~arb_chcsr[6]&
arb_chcsr[5]);
assign dst_a = (~arb_chcsr[4]&
~arb_chcsr[3]);
assign src_a = (~arb_chcsr[6]&
~arb_chcsr[5]);
assign dst_e = arb_chcsr[4];
assign src_e = arb_chcsr[6];
assign arb_chtsz_eq0 = (arb_chtsz == 0);
assign tsz_eq0 = (tsz_cnt == 0);
assign tsz_eq1 = (tsz_cnt == 1);
assign tsz_eq2 = (tsz_cnt == 2);
assign bst_eq0 = (bst_cnt[`DMA_BSTCNT_WIDTH-1:0] == 0);
assign bst_eq1 = (bst_cnt[`DMA_BSTCNT_WIDTH-1:0] == 1);
assign bst_eq2 = (bst_cnt[`DMA_BSTCNT_WIDTH-1:0] == 2);
endmodule
|
`include "DMA_DEFINE.vh"
module dma_fifo
(
HCLK,
HRSTn,
push,
pop,
look_ahead,
flush,
clear,
de_ff_ini,
pack_en,
swid16,
swid32,
cvtp2,
cv8t16,
cv8t32,
cv16t32,
adi,
dti,
ff_dto,
ff_empty,
ff_eq1,
ff_eq2,
ff_geth,
ff_2ltfl,
ff_1ltfl,
ff_q_full,
ff_part_wd,
ff_cbe,
ff_cnv_q_vld,
ff_wr
);
input HCLK;
input HRSTn;
input push;
input pop;
input look_ahead;
input flush;
input clear;
input de_ff_ini;
input pack_en;
input swid16;
input swid32;
input cvtp2;
input cv8t16;
input cv8t32;
input cv16t32;
input [1:0] adi;
input [`DMA_HDATA_WIDTH-1:0] dti;
output [`DMA_HDATA_WIDTH-1:0] ff_dto;
output ff_empty;
output ff_eq1;
output ff_eq2;
output ff_geth;
output ff_2ltfl;
output ff_1ltfl;
output ff_q_full;
output ff_part_wd;
output [3:0] ff_cbe;
output ff_cnv_q_vld;
output ff_wr;
reg part_wd;
reg ram_wrq;
reg [7:0] cnv_bt0,cnv_bt1,cnv_bt2,cnv_bt3;
reg ram_wr;
reg [`DMA_FF_ADD_WIDTH-1:0] ff_fram_wado;
reg [`DMA_FF_ADD_WIDTH-1:0] ff_fram_radx;
reg [`DMA_FF_CNT_WIDTH-1:0] ff_cnt;
wire last_bt,ram_wr_nx,ram_wrx,ff_wr;
wire push_qualify,pop_qualify;
wire ram_wr_qualify,ram_wrq_qualify,ram_wrq_nx;
assign push_qualify = push & ~clear;
assign pop_qualify = pop & ~clear;
wire cb0i_sel1 = adi[1]&~swid32;
wire cb0i_sel0 = adi[0]&~swid16&~swid32;
wire cb1i_sel1 = adi[1]&~swid32;
wire cb1i_sel0 = adi[0]|swid16|swid32;
wire cb2i_sel1 = adi[1]|swid32;
wire cb2i_sel0 = adi[0]&~swid16&~swid32;
wire cb3i_sel1 = adi[1]|swid32;
wire cb3i_sel0 = adi[0]|swid16|swid32;
reg [7:0] cb0i,cb1i,cb2i,cb3i;
wire ff_empty = (ff_cnt == 0);
wire ff_eq1 = (ff_cnt == 1);
wire ff_eq2 = (ff_cnt == 2);
wire ff_geth = (ff_cnt > `DMA_FF_TH);
wire ff_2ltfl = (ff_cnt > (`DMA_FF_DEP - 2));
wire ff_1ltfl = (ff_cnt > (`DMA_FF_DEP - 1));
wire ff_full = (ff_cnt == `DMA_FF_DEP);
assign ff_q_full = ram_wrq_nx;
always @(cb0i_sel1 or cb0i_sel0 or dti)
case({cb0i_sel1,cb0i_sel0})
2'b00: cb0i = dti[7:0];
2'b01: cb0i = dti[15:8];
2'b10: cb0i = dti[23:16];
2'b11: cb0i = dti[31:24];
endcase
always @(cb1i_sel1 or cb1i_sel0 or dti)
case({cb1i_sel1,cb1i_sel0})
2'b00: cb1i = dti[7:0];
2'b01: cb1i = dti[15:8];
2'b10: cb1i = dti[23:16];
2'b11: cb1i = dti[31:24];
endcase
always @(cb2i_sel1 or cb2i_sel0 or dti)
case({cb2i_sel1,cb2i_sel0})
2'b00: cb2i = dti[7:0];
2'b01: cb2i = dti[15:8];
2'b10: cb2i = dti[23:16];
2'b11: cb2i = dti[31:24];
endcase
always @(cb3i_sel1 or cb3i_sel0 or dti)
case({cb3i_sel1,cb3i_sel0})
2'b00: cb3i = dti[7:0];
2'b01: cb3i = dti[15:8];
2'b10: cb3i = dti[23:16];
2'b11: cb3i = dti[31:24];
endcase
reg [3:0] cbe_ini,cbe;
reg ff_cnv_q_vld;
always @(cv8t32 or cv8t16 or cv16t32)
case({cv8t32,cv8t16,cv16t32})
3'b001: cbe_ini = 4'b0010;
3'b010: cbe_ini = 4'b0110;
3'b100: cbe_ini = 4'b0111;
default: cbe_ini = 4'b1111;
endcase
wire cbe0_nx = (cvtp2&~cbe[0])|(cv8t32&cbe[3])|~pack_en;
wire cbe1_nx = (cvtp2&~cbe[1])|(cv8t32&cbe[0])|~pack_en;
wire cbe2_nx = (cvtp2&~cbe[2])|(cv8t32&cbe[1])|~pack_en;
wire cbe3_nx = (cvtp2&~cbe[3])|(cv8t32&cbe[2])|~pack_en;
always @(posedge HCLK or negedge HRSTn)
if(~HRSTn)
cbe <= 4'b0;
else if(de_ff_ini)
cbe <= cbe_ini;
else if(push_qualify)
cbe <= {cbe3_nx,cbe2_nx,cbe1_nx,cbe0_nx};
assign ff_cbe = cbe;
wire cnv_b0_en = cbe[0] & push_qualify;
wire cnv_b1_en = cbe[1] & push_qualify;
wire cnv_b2_en = cbe[2] & push_qualify;
wire cnv_b3_en = cbe[3] & push_qualify;
always @(posedge HCLK or negedge HRSTn)
if(~HRSTn)
cnv_bt0 <= 'h0;
else if(cnv_b0_en)
cnv_bt0 <= cb0i;
always @(posedge HCLK or negedge HRSTn)
if(~HRSTn)
cnv_bt1 <= 'h0;
else if(cnv_b1_en)
cnv_bt1 <= cb1i;
always @(posedge HCLK or negedge HRSTn)
if(~HRSTn)
cnv_bt2 <= 'h0;
else if(cnv_b2_en)
cnv_bt2 <= cb2i;
always @(posedge HCLK or negedge HRSTn)
if(~HRSTn)
cnv_bt3 <= 'h0;
else if(cnv_b3_en)
cnv_bt3 <= cb3i;
always @(posedge HCLK or negedge HRSTn)
if(~HRSTn)
ff_cnv_q_vld <= 0;
else if(de_ff_ini)
ff_cnv_q_vld <= 0;
else if(ram_wr_nx & !ff_wr)
ff_cnv_q_vld <= 1;
else if(!ram_wr_nx & ff_wr)
ff_cnv_q_vld <= 0;
assign last_bt = cbe[3];
assign ram_wr_nx = last_bt&push_qualify;
always @(posedge HCLK or negedge HRSTn)
if (~HRSTn)
ram_wr <= 'b0;
else
ram_wr <= ram_wr_nx;
assign ram_wr_qualify = ram_wr &~clear;
assign ram_wrq_qualify = ram_wrq&~clear;
assign ram_wrq_nx = ~clear&(((ram_wr_qualify|flush)&ff_full)|(ram_wrq_qualify&ff_full));
always @(posedge HCLK or negedge HRSTn)
if (~HRSTn)
ram_wrq <= 'b0;
else
ram_wrq <= ram_wrq_nx;
assign ram_wrx = (ram_wr_qualify|flush|ram_wrq_qualify)&~ff_full;
wire part_wd_st = ~part_wd&pack_en&push_qualify&!last_bt&!ff_wr;
wire part_wd_cl = part_wd &(!push_qualify&ff_wr);
always @(posedge HCLK or negedge HRSTn)
if(~HRSTn)
part_wd <= 'b0;
else if(clear)
part_wd <= 'b0;
else if(part_wd_st)
part_wd <= 'b1;
else if(part_wd_cl)
part_wd <= 'b0;
/*
always @(posedge HCLK or negedge HRSTn)
if(~HRSTn)
part_wd <= 'b0;
else if(part_wd_st)
part_wd <= 'b1;
else if(part_wd_cl)
part_wd <= 'b0;
*/
assign ff_part_wd = part_wd;
assign ff_wr = ram_wrx;
wire ff_rd = pop_qualify;
wire [`DMA_HDATA_WIDTH-1:0] ff_fram_dto = {cnv_bt3,cnv_bt2,cnv_bt1,cnv_bt0};
wire [`DMA_FF_ADD_WIDTH-1:0] ff_fram_rado;
always @(posedge HCLK or negedge HRSTn)
if(~HRSTn)
ff_fram_wado <= 'b0;
else if(clear)
ff_fram_wado <= 'b0;
else if(ff_wr)
ff_fram_wado <= ff_fram_wado + 1;
always @(posedge HCLK or negedge HRSTn)
if(~HRSTn)
ff_fram_radx <= 'b0;
else if(clear)
ff_fram_radx <= 'b0;
else if(ff_rd)
ff_fram_radx <= ff_fram_radx + 1;
assign ff_fram_rado = ff_fram_radx + look_ahead;
always @(posedge HCLK or negedge HRSTn)
if(~HRSTn)
ff_cnt <= 'b0;
else if(clear)
ff_cnt <= 'b0;
else if(ff_wr&~ff_rd)
ff_cnt <= ff_cnt + 1;
else if(ff_rd&~ff_wr)
ff_cnt <= ff_cnt - 1;
wire ff_fram_wr_n = ~ff_wr;
wire [`DMA_HDATA_WIDTH-1:0] fram_ff_dto;
ff_ram u_ff_ram (
.clk(HCLK), .rst_n(HRSTn), .cs_n(1'b0), .wr_n(ff_fram_wr_n),
.rd_addr(ff_fram_rado), .wr_addr(ff_fram_wado),
.data_in(ff_fram_dto), .data_out(fram_ff_dto) );
assign ff_dto = ff_empty? {cnv_bt3,cnv_bt2,cnv_bt1,cnv_bt0} : fram_ff_dto;
endmodule
module ff_ram
(
clk,
rst_n,
cs_n,
wr_n,
rd_addr,
wr_addr,
data_in,
data_out
);
input clk,rst_n;
input cs_n,wr_n;
input [`DMA_FF_ADD_WIDTH-1:0] rd_addr;
input [`DMA_FF_ADD_WIDTH-1:0] wr_addr;
input [`DMA_HDATA_WIDTH-1:0] data_in;
output [`DMA_HDATA_WIDTH-1:0] data_out;
wire we;
reg [`DMA_HDATA_WIDTH-1:0] ram_dt [`DMA_FF_DEP-1:0];
assign we = ~cs_n & ~wr_n;
always @(posedge clk)
if(we)
ram_dt[wr_addr] <= data_in;
assign data_out = ram_dt[rd_addr];
/*
DW_ram_r_w_s_dff #(`DMA_HDATA_WIDTH, `DMA_FF_DEP, DMA_DWRAM_SYN_RST)
U_FRAM ( .clk(HCLK), .rst_n(HRSTn), .cs_n(1'b1), .wr_n(ff_fram_wr_n),
.rd_addr(ff_fram_rado), .wr_addr(ff_fram_wado),
.data_in(ff_fram_dto), .data_out(fram_ff_dto) );
*/
endmodule
|
`include "DMA_DEFINE.vh"
module dma_rrarb
(
HCLK,
HRSTn,
vld_req,
gnt_chno,
next_ch
);
input HCLK;
input HRSTn;
input [`DMA_MAX_CHNO-1:0] vld_req;
output [`DMA_CHNO_WIDTH-1:0] gnt_chno;
input next_ch;
parameter
grant0 = 'h0,
grant1 = 'h1,
grant2 = 'h2,
grant3 = 'h3,
grant4 = 'h4,
grant5 = 'h5,
grant6 = 'h6,
grant7 = 'h7
;
reg [`DMA_CHNO_WIDTH-1:0] state, next_state;
assign gnt_chno = state;
always@(posedge HCLK or negedge HRSTn)
if(!HRSTn) state <= grant0;
else state <= next_state;
always@(state or vld_req or next_ch)
begin
case(state)
grant0:
if(next_ch)
begin
`ifdef DMA_HAVE_CH1
if(vld_req[1]) next_state = grant1;
else
`endif
`ifdef DMA_HAVE_CH2
if(vld_req[2]) next_state = grant2;
else
`endif
`ifdef DMA_HAVE_CH3
if(vld_req[3]) next_state = grant3;
else
`endif
`ifdef DMA_HAVE_CH4
if(vld_req[4]) next_state = grant4;
else
`endif
`ifdef DMA_HAVE_CH5
if(vld_req[5]) next_state = grant5;
else
`endif
`ifdef DMA_HAVE_CH6
if(vld_req[6]) next_state = grant6;
else
`endif
`ifdef DMA_HAVE_CH7
if(vld_req[7]) next_state = grant7;
else
`endif
next_state = state;
end
else next_state = state;
`ifdef DMA_HAVE_CH1
grant1:
if(next_ch)
begin
`ifdef DMA_HAVE_CH2
if(vld_req[2]) next_state = grant2;
else
`endif
`ifdef DMA_HAVE_CH3
if(vld_req[3]) next_state = grant3;
else
`endif
`ifdef DMA_HAVE_CH4
if(vld_req[4]) next_state = grant4;
else
`endif
`ifdef DMA_HAVE_CH5
if(vld_req[5]) next_state = grant5;
else
`endif
`ifdef DMA_HAVE_CH6
if(vld_req[6]) next_state = grant6;
else
`endif
`ifdef DMA_HAVE_CH7
if(vld_req[7]) next_state = grant7;
else
`endif
if(vld_req[0]) next_state = grant0;
else next_state = state;
end
else next_state = state;
`endif
`ifdef DMA_HAVE_CH2
grant2:
if(next_ch)
begin
`ifdef DMA_HAVE_CH3
if(vld_req[3]) next_state = grant3;
else
`endif
`ifdef DMA_HAVE_CH4
if(vld_req[4]) next_state = grant4;
else
`endif
`ifdef DMA_HAVE_CH5
if(vld_req[5]) next_state = grant5;
else
`endif
`ifdef DMA_HAVE_CH6
if(vld_req[6]) next_state = grant6;
else
`endif
`ifdef DMA_HAVE_CH7
if(vld_req[7]) next_state = grant7;
else
`endif
if(vld_req[0]) next_state = grant0;
else if(vld_req[1]) next_state = grant1;
else next_state = state;
end
else next_state = state;
`endif
`ifdef DMA_HAVE_CH3
grant3:
if(next_ch)
begin
`ifdef DMA_HAVE_CH4
if(vld_req[4]) next_state = grant4;
else
`endif
`ifdef DMA_HAVE_CH5
if(vld_req[5]) next_state = grant5;
else
`endif
`ifdef DMA_HAVE_CH6
if(vld_req[6]) next_state = grant6;
else
`endif
`ifdef DMA_HAVE_CH7
if(vld_req[7]) next_state = grant7;
else
`endif
if(vld_req[0]) next_state = grant0;
else if(vld_req[1]) next_state = grant1;
else if(vld_req[2]) next_state = grant2;
else next_state = state;
end
else next_state = state;
`endif
`ifdef DMA_HAVE_CH4
grant4:
if(next_ch)
begin
`ifdef DMA_HAVE_CH5
if(vld_req[5]) next_state = grant5;
else
`endif
`ifdef DMA_HAVE_CH6
if(vld_req[6]) next_state = grant6;
else
`endif
`ifdef DMA_HAVE_CH7
if(vld_req[7]) next_state = grant7;
else
`endif
if(vld_req[0]) next_state = grant0;
else if(vld_req[1]) next_state = grant1;
else if(vld_req[2]) next_state = grant2;
else if(vld_req[3]) next_state = grant3;
else next_state = state;
end
else next_state = state;
`endif
`ifdef DMA_HAVE_CH5
grant5:
if(next_ch)
begin
`ifdef DMA_HAVE_CH6
if(vld_req[6]) next_state = grant6;
else
`endif
`ifdef DMA_HAVE_CH7
if(vld_req[7]) next_state = grant7;
else
`endif
if(vld_req[0]) next_state = grant0;
else if(vld_req[1]) next_state = grant1;
else if(vld_req[2]) next_state = grant2;
else if(vld_req[3]) next_state = grant3;
else if(vld_req[4]) next_state = grant4;
else next_state = state;
end
else next_state = state;
`endif
`ifdef DMA_HAVE_CH6
grant6:
if(next_ch)
begin
`ifdef DMA_HAVE_CH7
if(vld_req[7]) next_state = grant7;
else
`endif
if(vld_req[0]) next_state = grant0;
else if(vld_req[1]) next_state = grant1;
else if(vld_req[2]) next_state = grant2;
else if(vld_req[3]) next_state = grant3;
else if(vld_req[4]) next_state = grant4;
else if(vld_req[5]) next_state = grant5;
else next_state = state;
end
else next_state = state;
`endif
`ifdef DMA_HAVE_CH7
grant7:
if(next_ch)
begin
if(vld_req[0]) next_state = grant0;
else if(vld_req[1]) next_state = grant1;
else if(vld_req[2]) next_state = grant2;
else if(vld_req[3]) next_state = grant3;
else if(vld_req[4]) next_state = grant4;
else if(vld_req[5]) next_state = grant5;
else if(vld_req[6]) next_state = grant6;
else next_state = state;
end
else next_state = state;
`endif
endcase
end
endmodule
|
`include "DMA_DEFINE.vh"
module dma_top
(
HCLK,
HRSTn,
h0addr,
h0trans,
h0write,
h0size,
h0prot,
h0lock,
h0burst,
h0wdata,
h0rdata,
h0readyin,
h0resp,
`ifdef DMA_HAVE_AHB1
`ifdef DMA_HAVE_BRIDGE
h1addr,
h1trans,
h1write,
h1size,
h1prot,
h1burst,
h1wdata,
h1readyin,
h1sel_dma,
h1sel_br,
h1rdt0_dma,
`ifdef DMA_HAVE_CH1
h1rdt1_dma,
`endif
`ifdef DMA_HAVE_CH2
h1rdt2_dma,
`endif
`ifdef DMA_HAVE_CH3
h1rdt3_dma,
`endif
`ifdef DMA_HAVE_CH4
h1rdt4_dma,
`endif
`ifdef DMA_HAVE_CH5
h1rdt5_dma,
`endif
`ifdef DMA_HAVE_CH6
h1rdt6_dma,
`endif
`ifdef DMA_HAVE_CH7
h1rdt7_dma,
`endif
h1rp0_dma,
`ifdef DMA_HAVE_CH1
h1rp1_dma,
`endif
`ifdef DMA_HAVE_CH2
h1rp2_dma,
`endif
`ifdef DMA_HAVE_CH3
h1rp3_dma,
`endif
`ifdef DMA_HAVE_CH4
h1rp4_dma,
`endif
`ifdef DMA_HAVE_CH5
h1rp5_dma,
`endif
`ifdef DMA_HAVE_CH6
h1rp6_dma,
`endif
`ifdef DMA_HAVE_CH7
h1rp7_dma,
`endif
h1rdy0_dma,
`ifdef DMA_HAVE_CH1
h1rdy1_dma,
`endif
`ifdef DMA_HAVE_CH2
h1rdy2_dma,
`endif
`ifdef DMA_HAVE_CH3
h1rdy3_dma,
`endif
`ifdef DMA_HAVE_CH4
h1rdy4_dma,
`endif
`ifdef DMA_HAVE_CH5
h1rdy5_dma,
`endif
`ifdef DMA_HAVE_CH6
h1rdy6_dma,
`endif
`ifdef DMA_HAVE_CH7
h1rdy7_dma,
`endif
h1rdt0_br,
`ifdef DMA_HAVE_CH1
h1rdt1_br,
`endif
`ifdef DMA_HAVE_CH2
h1rdt2_br,
`endif
`ifdef DMA_HAVE_CH3
h1rdt3_br,
`endif
`ifdef DMA_HAVE_CH4
h1rdt4_br,
`endif
`ifdef DMA_HAVE_CH5
h1rdt5_br,
`endif
`ifdef DMA_HAVE_CH6
h1rdt6_br,
`endif
`ifdef DMA_HAVE_CH7
h1rdt7_br,
`endif
h1rp0_br,
`ifdef DMA_HAVE_CH1
h1rp1_br,
`endif
`ifdef DMA_HAVE_CH2
h1rp2_br,
`endif
`ifdef DMA_HAVE_CH3
h1rp3_br,
`endif
`ifdef DMA_HAVE_CH4
h1rp4_br,
`endif
`ifdef DMA_HAVE_CH5
h1rp5_br,
`endif
`ifdef DMA_HAVE_CH6
h1rp6_br,
`endif
`ifdef DMA_HAVE_CH7
h1rp7_br,
`endif
h1rdy0_br,
`ifdef DMA_HAVE_CH1
h1rdy1_br,
`endif
`ifdef DMA_HAVE_CH2
h1rdy2_br,
`endif
`ifdef DMA_HAVE_CH3
h1rdy3_br,
`endif
`ifdef DMA_HAVE_CH4
h1rdy4_br,
`endif
`ifdef DMA_HAVE_CH5
h1rdy5_br,
`endif
`ifdef DMA_HAVE_CH6
h1rdy6_br,
`endif
`ifdef DMA_HAVE_CH7
h1rdy7_br,
`endif
`else
h1addr,
h1trans,
h1write,
h1size,
h1prot,
h1lock,
h1burst,
h1wdata,
h1rdata,
h1readyin,
h1resp,
`endif
`endif
haddr,
hwrite,
hsize,
hburst,
htrans,
hprot,
hwdata,
hreadyin,
hsel_reg,
hrdata_reg,
hreadyout_reg,
hresp_reg,
`ifdef DMA_HAVE_AHB1
`ifdef DMA_HAVE_BRIDGE
hsel_br,
hrdata_br,
hreadyout_br,
hresp_br,
`endif
`endif
h0req,
h0grant,
`ifdef DMA_HAVE_AHB1
`ifdef DMA_HAVE_BRIDGE
`else
h1req,
h1grant,
`endif
`endif
dmaint,
dmaint_tc,
dmaint_err,
dma_req,
dma_ack,
dma_tc
);
input HCLK;
input HRSTn;
output [`DMA_HADDR_WIDTH-1:0] h0addr;
output [`DMA_HTRANS_WIDTH-1:0] h0trans;
output h0write;
output [`DMA_HSIZE_WIDTH-1:0] h0size;
output [`DMA_HPROT_WIDTH-1:0] h0prot;
output h0lock;
output [`DMA_HBURST_WIDTH-1:0] h0burst;
output [`DMA_HDATA_WIDTH-1:0] h0wdata;
input [`DMA_HDATA_WIDTH-1:0] h0rdata;
input h0readyin;
input [`DMA_HRESP_WIDTH-1:0] h0resp;
`ifdef DMA_HAVE_AHB1
`ifdef DMA_HAVE_BRIDGE
output [`DMA_HADDR_WIDTH-1:0] h1addr;
output [`DMA_HTRANS_WIDTH-1:0] h1trans;
output h1write;
output [`DMA_HSIZE_WIDTH-1:0] h1size;
output [`DMA_HPROT_WIDTH-1:0] h1prot;
output [`DMA_HBURST_WIDTH-1:0] h1burst;
output [`DMA_HDATA_WIDTH-1:0] h1wdata;
output h1readyin;
output [`DMA_MAX_CHNO-1:0] h1sel_dma;
output [`DMA_MAX_CHNO-1:0] h1sel_br;
input [`DMA_HDATA_WIDTH-1:0] h1rdt0_dma;
`ifdef DMA_HAVE_CH1
input [`DMA_HDATA_WIDTH-1:0] h1rdt1_dma;
`endif
`ifdef DMA_HAVE_CH2
input [`DMA_HDATA_WIDTH-1:0] h1rdt2_dma;
`endif
`ifdef DMA_HAVE_CH3
input [`DMA_HDATA_WIDTH-1:0] h1rdt3_dma;
`endif
`ifdef DMA_HAVE_CH4
input [`DMA_HDATA_WIDTH-1:0] h1rdt4_dma;
`endif
`ifdef DMA_HAVE_CH5
input [`DMA_HDATA_WIDTH-1:0] h1rdt5_dma;
`endif
`ifdef DMA_HAVE_CH6
input [`DMA_HDATA_WIDTH-1:0] h1rdt6_dma;
`endif
`ifdef DMA_HAVE_CH7
input [`DMA_HDATA_WIDTH-1:0] h1rdt7_dma;
`endif
input [`DMA_HRESP_WIDTH-1:0] h1rp0_dma;
`ifdef DMA_HAVE_CH1
input [`DMA_HRESP_WIDTH-1:0] h1rp1_dma;
`endif
`ifdef DMA_HAVE_CH2
input [`DMA_HRESP_WIDTH-1:0] h1rp2_dma;
`endif
`ifdef DMA_HAVE_CH3
input [`DMA_HRESP_WIDTH-1:0] h1rp3_dma;
`endif
`ifdef DMA_HAVE_CH4
input [`DMA_HRESP_WIDTH-1:0] h1rp4_dma;
`endif
`ifdef DMA_HAVE_CH5
input [`DMA_HRESP_WIDTH-1:0] h1rp5_dma;
`endif
`ifdef DMA_HAVE_CH6
input [`DMA_HRESP_WIDTH-1:0] h1rp6_dma;
`endif
`ifdef DMA_HAVE_CH7
input [`DMA_HRESP_WIDTH-1:0] h1rp7_dma;
`endif
input h1rdy0_dma;
`ifdef DMA_HAVE_CH1
input h1rdy1_dma;
`endif
`ifdef DMA_HAVE_CH2
input h1rdy2_dma;
`endif
`ifdef DMA_HAVE_CH3
input h1rdy3_dma;
`endif
`ifdef DMA_HAVE_CH4
input h1rdy4_dma;
`endif
`ifdef DMA_HAVE_CH5
input h1rdy5_dma;
`endif
`ifdef DMA_HAVE_CH6
input h1rdy6_dma;
`endif
`ifdef DMA_HAVE_CH7
input h1rdy7_dma;
`endif
input [`DMA_HDATA_WIDTH-1:0] h1rdt0_br;
`ifdef DMA_HAVE_CH1
input [`DMA_HDATA_WIDTH-1:0] h1rdt1_br;
`endif
`ifdef DMA_HAVE_CH2
input [`DMA_HDATA_WIDTH-1:0] h1rdt2_br;
`endif
`ifdef DMA_HAVE_CH3
input [`DMA_HDATA_WIDTH-1:0] h1rdt3_br;
`endif
`ifdef DMA_HAVE_CH4
input [`DMA_HDATA_WIDTH-1:0] h1rdt4_br;
`endif
`ifdef DMA_HAVE_CH5
input [`DMA_HDATA_WIDTH-1:0] h1rdt5_br;
`endif
`ifdef DMA_HAVE_CH6
input [`DMA_HDATA_WIDTH-1:0] h1rdt6_br;
`endif
`ifdef DMA_HAVE_CH7
input [`DMA_HDATA_WIDTH-1:0] h1rdt7_br;
`endif
input [`DMA_HRESP_WIDTH-1:0] h1rp0_br;
`ifdef DMA_HAVE_CH1
input [`DMA_HRESP_WIDTH-1:0] h1rp1_br;
`endif
`ifdef DMA_HAVE_CH2
input [`DMA_HRESP_WIDTH-1:0] h1rp2_br;
`endif
`ifdef DMA_HAVE_CH3
input [`DMA_HRESP_WIDTH-1:0] h1rp3_br;
`endif
`ifdef DMA_HAVE_CH4
input [`DMA_HRESP_WIDTH-1:0] h1rp4_br;
`endif
`ifdef DMA_HAVE_CH5
input [`DMA_HRESP_WIDTH-1:0] h1rp5_br;
`endif
`ifdef DMA_HAVE_CH6
input [`DMA_HRESP_WIDTH-1:0] h1rp6_br;
`endif
`ifdef DMA_HAVE_CH7
input [`DMA_HRESP_WIDTH-1:0] h1rp7_br;
`endif
input h1rdy0_br;
`ifdef DMA_HAVE_CH1
input h1rdy1_br;
`endif
`ifdef DMA_HAVE_CH2
input h1rdy2_br;
`endif
`ifdef DMA_HAVE_CH3
input h1rdy3_br;
`endif
`ifdef DMA_HAVE_CH4
input h1rdy4_br;
`endif
`ifdef DMA_HAVE_CH5
input h1rdy5_br;
`endif
`ifdef DMA_HAVE_CH6
input h1rdy6_br;
`endif
`ifdef DMA_HAVE_CH7
input h1rdy7_br;
`endif
`else
output [`DMA_HADDR_WIDTH-1:0] h1addr;
output [`DMA_HTRANS_WIDTH-1:0] h1trans;
output h1write;
output [`DMA_HSIZE_WIDTH-1:0] h1size;
output [`DMA_HPROT_WIDTH-1:0] h1prot;
output h1lock;
output [`DMA_HBURST_WIDTH-1:0] h1burst;
output [`DMA_HDATA_WIDTH-1:0] h1wdata;
input [`DMA_HDATA_WIDTH-1:0] h1rdata;
input h1readyin;
input [`DMA_HRESP_WIDTH-1:0] h1resp;
`endif
`endif
input [`DMA_HADDR_WIDTH-1:0] haddr;
input hwrite;
input [`DMA_HSIZE_WIDTH-1:0] hsize;
input [`DMA_HBURST_WIDTH-1:0] hburst;
input [`DMA_HTRANS_WIDTH-1:0] htrans;
input [`DMA_HPROT_WIDTH-1:0] hprot;
input [`DMA_HDATA_WIDTH-1:0] hwdata;
input hreadyin;
input hsel_reg;
output [`DMA_HDATA_WIDTH-1:0] hrdata_reg;
output hreadyout_reg;
output [`DMA_HRESP_WIDTH-1:0] hresp_reg;
`ifdef DMA_HAVE_AHB1
`ifdef DMA_HAVE_BRIDGE
input hsel_br;
output [`DMA_HDATA_WIDTH-1:0] hrdata_br;
output hreadyout_br;
output [`DMA_HRESP_WIDTH-1:0] hresp_br;
`endif
`endif
output h0req;
input h0grant;
`ifdef DMA_HAVE_AHB1
`ifdef DMA_HAVE_BRIDGE
`else
output h1req;
input h1grant;
`endif
`endif
output dmaint;
output dmaint_tc;
output dmaint_err;
input [`DMA_MAX_CHNO-1:0] dma_req;
output [`DMA_MAX_CHNO-1:0] dma_ack;
output [`DMA_MAX_CHNO-1:0] dma_tc;
`ifdef DMA_HAVE_AHB1
`ifdef DMA_HAVE_BRIDGE
wire h1grant = 1;
`else
assign h1lock = 1'b0;
`endif
`else
wire m1_cp;
wire m1_tr_sq;
wire m1_rp_err;
wire m1_rp_rty;
`endif
assign h0lock = 1'b0;
wire [10:0] de_st;
wire [1:0] m0_ad1t0x;
wire [`DMA_HADDR_WIDTH-1:0] m0_updad;
wire [`DMA_HDATA_WIDTH-1:0] m0_rdt;
wire m0_dt_st;
wire [1:0] m1_ad1t0x;
wire [`DMA_HADDR_WIDTH-1:0] m1_updad;
wire m1_dt_st;
wire [`DMA_HDATA_WIDTH-1:0] m1_rdt;
wire [`DMA_HADDR_WIDTH-1:0] h0addr;
wire [`DMA_HTRANS_WIDTH-1:0] h0trans;
wire h0write;
wire [`DMA_HPROT_WIDTH-1:0] h0prot;
wire [`DMA_HBURST_WIDTH-1:0] h0burst;
wire [`DMA_HDATA_WIDTH-1:0] h0wdata;
wire [`DMA_HADDR_WIDTH-1:0] h1addr;
wire [`DMA_HTRANS_WIDTH-1:0] h1trans;
wire h1write;
wire [`DMA_HPROT_WIDTH-1:0] h1prot;
wire [`DMA_HBURST_WIDTH-1:0] h1burst;
wire [`DMA_HDATA_WIDTH-1:0] h1wdata;
wire [`DMA_HADDR_WIDTH-1:0] de_sad;
wire [`DMA_HADDR_WIDTH-1:0] de_dad;
wire [`DMA_CHSZ_WIDTH-1:0] de_tsz;
`ifdef DMA_HAVE_LINKLIST
wire [`DMA_HADDR_WIDTH-1:0] de_llp;
wire [`DMA_HADDR_WIDTH-1:2] de_mllp;
`endif
wire [`DMA_HDATA_WIDTH-1:0] de_csr;
wire [`DMA_HADDR_WIDTH-1:0] haddr;
wire [`DMA_HDATA_WIDTH-1:0] hwdata;
wire [`DMA_HTRANS_WIDTH-1:0] htrans;
wire [`DMA_HSIZE_WIDTH-1:0] hsize;
wire [`DMA_HBURST_WIDTH-1:0] hburst;
wire [`DMA_HPROT_WIDTH-1:0] hprot;
wire [`DMA_HRESP_WIDTH-1:0] hresp_rf;
wire [`DMA_HRESP_WIDTH-1:0] hresp_br;
wire [`DMA_HDATA_WIDTH-1:0] hrdata_rf;
wire [`DMA_HDATA_WIDTH-1:0] hrdata_br;
wire [`DMA_HDATA_WIDTH-1:0] h1rdata;
wire h1readyin;
wire [`DMA_HRESP_WIDTH-1:0] h1resp;
wire [`DMA_HADDR_WIDTH-1:0] slv_ad;
wire [`DMA_HADDR_WIDTH-1:0] slv_ad_d1;
wire [`DMA_HDATA_WIDTH-1:0] slv_dt;
wire [`DMA_HSIZE_WIDTH-1:0] slv_sz;
wire [`DMA_HSIZE_WIDTH-1:0] slv_sz_d1;
wire [`DMA_HPROT_WIDTH-1:0] slv_pt_d1;
wire [`DMA_HDATA_WIDTH-1:0] slv_br_dt;
wire [1:0] de_ff_ado;
wire [`DMA_HDATA_WIDTH-1:0] de_ff_dto;
wire [`DMA_HDATA_WIDTH-1:0] ff_dto;
wire [3:0] ff_cbe;
wire ff_cnv_q_vld;
wire [`DMA_HDATA_WIDTH-1:0] rf_dto;
wire [`DMA_CSR_WIDTH-1:0] csr;
wire [`DMA_MAX_CHNO-1:0] sync;
wire [`DMA_CHCSR_WIDTH-1:0] c0csr;
wire [`DMA_CHCFG_WIDTH-1:0] c0cfg;
wire [`DMA_HADDR_WIDTH-1:0] c0sad;
wire [`DMA_HADDR_WIDTH-1:0] c0dad;
wire [`DMA_HADDR_WIDTH-1:0] c0llp;
wire [`DMA_CHSZ_WIDTH-1:0] c0tsz;
wire [31:16] c0dmabs;
wire [31:16] c0brbs;
wire [`DMA_CHCSR_WIDTH-1:0] c1csr;
wire [`DMA_CHCFG_WIDTH-1:0] c1cfg;
wire [`DMA_HADDR_WIDTH-1:0] c1sad;
wire [`DMA_HADDR_WIDTH-1:0] c1dad;
wire [`DMA_HADDR_WIDTH-1:0] c1llp;
wire [`DMA_CHSZ_WIDTH-1:0] c1tsz;
wire [31:16] c1dmabs;
wire [31:16] c1brbs;
wire [`DMA_CHCSR_WIDTH-1:0] c2csr;
wire [`DMA_CHCFG_WIDTH-1:0] c2cfg;
wire [`DMA_HADDR_WIDTH-1:0] c2sad;
wire [`DMA_HADDR_WIDTH-1:0] c2dad;
wire [`DMA_HADDR_WIDTH-1:0] c2llp;
wire [`DMA_CHSZ_WIDTH-1:0] c2tsz;
wire [31:16] c2dmabs;
wire [31:16] c2brbs;
wire [`DMA_CHCSR_WIDTH-1:0] c3csr;
wire [`DMA_CHCFG_WIDTH-1:0] c3cfg;
wire [`DMA_HADDR_WIDTH-1:0] c3sad;
wire [`DMA_HADDR_WIDTH-1:0] c3dad;
wire [`DMA_HADDR_WIDTH-1:0] c3llp;
wire [`DMA_CHSZ_WIDTH-1:0] c3tsz;
wire [31:16] c3dmabs;
wire [31:16] c3brbs;
wire [`DMA_CHCSR_WIDTH-1:0] c4csr;
wire [`DMA_CHCFG_WIDTH-1:0] c4cfg;
wire [`DMA_HADDR_WIDTH-1:0] c4sad;
wire [`DMA_HADDR_WIDTH-1:0] c4dad;
wire [`DMA_HADDR_WIDTH-1:0] c4llp;
wire [`DMA_CHSZ_WIDTH-1:0] c4tsz;
wire [31:16] c4dmabs;
wire [31:16] c4brbs;
wire [`DMA_CHCSR_WIDTH-1:0] c5csr;
wire [`DMA_CHCFG_WIDTH-1:0] c5cfg;
wire [`DMA_HADDR_WIDTH-1:0] c5sad;
wire [`DMA_HADDR_WIDTH-1:0] c5dad;
wire [`DMA_HADDR_WIDTH-1:0] c5llp;
wire [`DMA_CHSZ_WIDTH-1:0] c5tsz;
wire [31:16] c5dmabs;
wire [31:16] c5brbs;
wire [`DMA_CHCSR_WIDTH-1:0] c6csr;
wire [`DMA_CHCFG_WIDTH-1:0] c6cfg;
wire [`DMA_HADDR_WIDTH-1:0] c6sad;
wire [`DMA_HADDR_WIDTH-1:0] c6dad;
wire [`DMA_HADDR_WIDTH-1:0] c6llp;
wire [`DMA_CHSZ_WIDTH-1:0] c6tsz;
wire [31:16] c6dmabs;
wire [31:16] c6brbs;
wire [`DMA_CHCSR_WIDTH-1:0] c7csr;
wire [`DMA_CHCFG_WIDTH-1:0] c7cfg;
wire [`DMA_HADDR_WIDTH-1:0] c7sad;
wire [`DMA_HADDR_WIDTH-1:0] c7dad;
wire [`DMA_HADDR_WIDTH-1:0] c7llp;
wire [`DMA_CHSZ_WIDTH-1:0] c7tsz;
wire [31:16] c7dmabs;
wire [31:16] c7brbs;
wire [`DMA_CHCSR_WIDTH-1:0] arb_chcsr;
wire [`DMA_HADDR_WIDTH-1:0] arb_chsad;
wire [`DMA_HADDR_WIDTH-1:0] arb_chdad;
wire [`DMA_HADDR_WIDTH-1:0] arb_chllp;
wire [`DMA_CHSZ_WIDTH-1:0] arb_chtsz;
wire [`DMA_CHNO_WIDTH-1:0] arb_ch_sel;
wire [1:0] fwdtsb0,fwdtsb1,fwdtsb2,fwdtsb3;
wire [`DMA_MAX_CHNO-1:0] err;
dma_engine de
(
.HCLK(HCLK),
.HRSTn(HRSTn),
.de_st(de_st),
.de_err_notify(de_err_notify),
`ifdef DMA_HAVE_LINKLIST
.st_llp0t3(st_llp0t3),
`endif
.dst_m(dst_m),
.src_m(src_m),
.dst_a(dst_a),
.src_a(src_a),
.dst_e(dst_e),
.src_e(src_e),
.dst_wid_wd(dst_wid_wd),
.src_wid_wd(src_wid_wd),
.dst_wid_hw(dst_wid_hw),
.src_wid_hw(src_wid_hw),
.dst_wid_bt(dst_wid_bt),
.src_wid_bt(src_wid_bt),
.bst_eq0(bst_eq0),
.bst_eq1(bst_eq1),
.bst_eq2(bst_eq2),
.tsz_eq0(tsz_eq0),
.tsz_eq1(tsz_eq1),
.tsz_eq2(tsz_eq2),
.cv8t32(cv8t32),
.cv8t16(cv8t16),
.cv16t32(cv16t32),
.cvtp2(cvtp2),
.pack_en(pack_en),
.pack_end(pack_end),
.unpack_en(unpack_en),
.upk_cnteq0(upk_cnteq0),
.upk_cnteq1(upk_cnteq1),
.fwdtsb0(fwdtsb0),
.fwdtsb1(fwdtsb1),
.fwdtsb2(fwdtsb2),
.fwdtsb3(fwdtsb3),
.m0_ad1t0x(m0_ad1t0x),
.m0_updad(m0_updad),
.m0_rdy(h0readyin),
.m0_rdt(m0_rdt),
.m0_cp(m0_cp),
.m0_tr_sq(m0_tr_sq),
.m0_rp_err(m0_rp_err),
.m0_rp_rty(m0_rp_rty),
.m0_dt_st(m0_dt_st),
.m0_dma_err_ok(m0_dma_err_ok),
.m0_is_dst(m0_is_dst),
.m0_is_src(m0_is_src),
`ifdef DMA_HAVE_LINKLIST
.m0_is_llp(m0_is_llp),
`endif
.m0_arb_src(m0_arb_src),
.m0_arb_dst(m0_arb_dst),
`ifdef DMA_HAVE_AHB1
.m1_ad1t0x(m1_ad1t0x),
.m1_updad(m1_updad),
.m1_rdy(h1readyin),
.m1_rdt(m1_rdt),
.m1_cp(m1_cp),
.m1_tr_sq(m1_tr_sq),
.m1_rp_err(m1_rp_err),
.m1_rp_rty(m1_rp_rty),
.m1_dt_st(m1_dt_st),
.m1_dtp(m1_dtp),
.m1_dma_had_a_rty(m1_dma_had_a_rty),
.m1_dma_err_ok(m1_dma_err_ok),
.m1_is_dst(m1_is_dst),
.m1_is_src(m1_is_src),
`ifdef DMA_HAVE_LINKLIST
.m1_is_llp(m1_is_llp),
`endif
.m1_arb_src(m1_arb_src),
.m1_arb_dst(m1_arb_dst),
.m1_src2br(m1_src2br),
.m0_m1_same(m0_m1_same),
`endif
`ifdef DMA_HAVE_AHB1
`ifdef DMA_HAVE_BRIDGE
.m1_arb_br(m1_arb_br),
.slv_br_req(slv_br_req),
.slv_brst_cmd(slv_brst_cmd),
.slv_brst_mscd(slv_brst_mscd),
.br_req_qf(br_req_qf),
`endif
`endif
.ff_eq1(ff_eq1),
.ff_eq2(ff_eq2),
.ff_2ltfl(ff_2ltfl),
.ff_1ltfl(ff_1ltfl),
.ff_part_wd(ff_part_wd),
.ff_cbe(ff_cbe),
.ff_cnv_q_vld(ff_cnv_q_vld),
.ff_wr(ff_wr),
.de_ff_push(de_ff_push),
.de_ff_pop(de_ff_pop),
.de_ff_ahead(de_ff_ahead),
.de_ff_flush(de_ff_flush),
.de_ff_clear(de_ff_clear),
.de_ff_ini(de_ff_ini),
.de_ff_ado(de_ff_ado),
.de_ff_dto(de_ff_dto),
.arb_req(arb_req),
.arb_chcsr(arb_chcsr),
`ifdef DMA_HAVE_LINKLIST
.arb_chllp(arb_chllp),
`endif
.arb_chtsz(arb_chtsz),
`ifdef DMA_HAVE_LINKLIST
.arb_chllpen(arb_chllpen),
`endif
.de_ack(de_ack),
.de_tc_st(de_tc_st),
.rf_cherr(rf_cherr),
.arb_chabt(arb_chabt),
.arb_abt_any(arb_abt_any),
.de_sad(de_sad),
.de_dad(de_dad),
`ifdef DMA_HAVE_LINKLIST
.de_llp(de_llp),
.de_mllp(de_mllp),
`endif
.de_tsz(de_tsz),
.de_csr(de_csr),
`ifdef DMA_HAVE_LINKLIST
.de_llpen(de_llpen),
`endif
.de_busy(de_busy),
.de_sad_we(de_sad_we),
.de_dad_we(de_dad_we),
.de_tsz_we(de_tsz_we),
`ifdef DMA_HAVE_LINKLIST
.de_llp_we(de_llp_we),
.de_csr_we(de_csr_we),
.de_llpen_we(de_llpen_we),
`endif
.de_en_clr(de_en_clr),
.de_abt_on_idle(de_abt_on_idle),
.de_err_st(de_err_st)
);
dma_ahbmst #(0) ahb_mst0
(
.HCLK(HCLK),
.HRSTn(HRSTn),
.arb_chcsr(arb_chcsr),
`ifdef DMA_HAVE_LINKLIST
.arb_chllp(arb_chllp),
`endif
.arb_chsad(arb_chsad),
.arb_chdad(arb_chdad),
.arb_chabt(arb_chabt),
`ifdef DMA_HAVE_AHB1
`ifdef DMA_HAVE_BRIDGE
.slv_br_req(1'b0),
.slv_br_ad(slv_ad_d1),
.slv_br_dt(slv_br_dt),
.slv_br_wr(slv_wr_d1),
.slv_br_sz(slv_sz_d1),
.slv_br_pt(slv_pt_d1),
.br_req_qf(br_req_qf),
`endif
`endif
.ff_dto(ff_dto),
.bst_eq0(bst_eq0),
.bst_eq1(bst_eq1),
.bst_eq2(bst_eq2),
.tsz_eq0(tsz_eq0),
.tsz_eq1(tsz_eq1),
.tsz_eq2(tsz_eq2),
.de_st(de_st),
.de_err_notify(de_err_notify),
.de_err_st(de_err_st),
`ifdef DMA_HAVE_LINKLIST
.de_mllp(de_mllp),
`endif
.pack_en(pack_en),
.pack_end(pack_end),
.unpack_en(unpack_en),
.upk_cnteq0(upk_cnteq0),
.upk_cnteq1(upk_cnteq1),
.ff_eq1(ff_eq1),
.ff_eq2(ff_eq2),
.ff_1ltfl(ff_1ltfl),
.ff_2ltfl(ff_2ltfl),
.ff_geth(ff_geth),
.ff_q_full(ff_q_full),
.ff_empty(ff_empty),
`ifdef DMA_HAVE_LINKLIST
.st_llp0t3(st_llp0t3),
`endif
.dst_m(dst_m),
.src_m(src_m),
.dst_a(dst_a),
.src_a(src_a),
.dst_e(dst_e),
.src_e(src_e),
.dst_wid_wd(dst_wid_wd),
.src_wid_wd(src_wid_wd),
.dst_wid_hw(dst_wid_hw),
.src_wid_hw(src_wid_hw),
.dst_wid_bt(dst_wid_bt),
.src_wid_bt(src_wid_bt),
.mx_is_dst(m0_is_dst),
.mx_is_src(m0_is_src),
`ifdef DMA_HAVE_LINKLIST
.mx_is_llp(m0_is_llp),
`endif
.mx_arb_src(m0_arb_src),
.mx_arb_dst(m0_arb_dst),
`ifdef DMA_HAVE_AHB1
.m1_src2br(m1_src2br),
.m0_m1_same(m0_m1_same),
`else
.m1_src2br(1'b0),
.m0_m1_same(1'b1),
`endif
`ifdef DMA_HAVE_BRIDGE
.mx_arb_br(1'b0),
`endif
.fwdtsb0(fwdtsb0),
.fwdtsb1(fwdtsb1),
.fwdtsb2(fwdtsb2),
.fwdtsb3(fwdtsb3),
.m0endian(csr[1]),
.m1endian(csr[2]),
.mx_ad1t0x(m0_ad1t0x),
.mx_updad(m0_updad),
.mx_rdto(m0_rdt),
.mx_cp(m0_cp),
.mx_tr_sq(m0_tr_sq),
.mx_rp_err(m0_rp_err),
.mx_rp_rty(m0_rp_rty),
.mx_dt_st(m0_dt_st),
.mx_dtp(),
.mx_dma_had_a_rty(),
.mx_dma_err_ok(m0_dma_err_ok),
.hrdatai(h0rdata),
.hreadyini(h0readyin),
.hrespi(h0resp),
.haddro(h0addr),
.htranso(h0trans),
.hwriteo(h0write),
.hsizeo(h0size),
.hproto(h0prot),
.hbursto(h0burst),
.hwdatao(h0wdata),
.hgranti(h0grant),
.hreqo(h0req)
);
`ifdef DMA_HAVE_AHB1
dma_ahbmst #(1) ahb_mst1
(
.HCLK(HCLK),
.HRSTn(HRSTn),
.arb_chcsr(arb_chcsr),
`ifdef DMA_HAVE_LINKLIST
.arb_chllp(arb_chllp),
`endif
.arb_chsad(arb_chsad),
.arb_chdad(arb_chdad),
.arb_chabt(arb_chabt),
`ifdef DMA_HAVE_BRIDGE
.slv_br_req(slv_br_req),
.slv_br_ad(slv_ad_d1),
.slv_br_dt(slv_br_dt),
.slv_br_wr(slv_wr_d1),
.slv_br_sz(slv_sz_d1),
.slv_br_pt(slv_pt_d1),
.br_req_qf(br_req_qf),
`endif
.ff_dto(ff_dto),
.bst_eq0(bst_eq0),
.bst_eq1(bst_eq1),
.bst_eq2(bst_eq2),
.tsz_eq0(tsz_eq0),
.tsz_eq1(tsz_eq1),
.tsz_eq2(tsz_eq2),
.de_st(de_st),
.de_err_notify(de_err_notify),
.de_err_st(de_err_st),
`ifdef DMA_HAVE_LINKLIST
.de_mllp(de_mllp),
`endif
.pack_en(pack_en),
.pack_end(pack_end),
.unpack_en(unpack_en),
.upk_cnteq0(upk_cnteq0),
.upk_cnteq1(upk_cnteq1),
.ff_eq1(ff_eq1),
.ff_eq2(ff_eq2),
.ff_1ltfl(ff_1ltfl),
.ff_2ltfl(ff_2ltfl),
.ff_geth(ff_geth),
.ff_q_full(ff_q_full),
.ff_empty(ff_empty),
`ifdef DMA_HAVE_LINKLIST
.st_llp0t3(st_llp0t3),
`endif
.dst_m(dst_m),
.src_m(src_m),
.dst_a(dst_a),
.src_a(src_a),
.dst_e(dst_e),
.src_e(src_e),
.dst_wid_wd(dst_wid_wd),
.src_wid_wd(src_wid_wd),
.dst_wid_hw(dst_wid_hw),
.src_wid_hw(src_wid_hw),
.dst_wid_bt(dst_wid_bt),
.src_wid_bt(src_wid_bt),
.mx_is_dst(m1_is_dst),
.mx_is_src(m1_is_src),
`ifdef DMA_HAVE_LINKLIST
.mx_is_llp(m1_is_llp),
`endif
.mx_arb_src(m1_arb_src),
.mx_arb_dst(m1_arb_dst),
`ifdef DMA_HAVE_AHB1
.m1_src2br(m1_src2br),
.m0_m1_same(m0_m1_same),
`else
.m1_src2br(1'b0),
.m0_m1_same(1'b1),
`endif
`ifdef DMA_HAVE_BRIDGE
.mx_arb_br(m1_arb_br),
`endif
.fwdtsb0(fwdtsb0),
.fwdtsb1(fwdtsb1),
.fwdtsb2(fwdtsb2),
.fwdtsb3(fwdtsb3),
.m0endian(csr[1]),
.m1endian(csr[2]),
.mx_updad(m1_updad),
.mx_ad1t0x(m1_ad1t0x),
.mx_rdto(m1_rdt),
.mx_cp(m1_cp),
.mx_tr_sq(m1_tr_sq),
.mx_rp_err(m1_rp_err),
.mx_rp_rty(m1_rp_rty),
.mx_dt_st(m1_dt_st),
.mx_dtp(m1_dtp),
.mx_dma_had_a_rty(m1_dma_had_a_rty),
.mx_dma_err_ok(m1_dma_err_ok),
.hrdatai(h1rdata),
.hreadyini(h1readyin),
.hrespi(h1resp),
.haddro(h1addr),
.htranso(h1trans),
.hwriteo(h1write),
.hsizeo(h1size),
.hproto(h1prot),
.hbursto(h1burst),
.hwdatao(h1wdata),
.hgranti(h1grant),
.hreqo(h1req)
);
`else
assign m1_cp = 0;
assign m1_tr_sq = 0;
assign m1_rp_err = 0;
assign m1_rp_rty = 0;
`endif
dma_fifo dma_fifo(
.HCLK(HCLK),
.HRSTn(HRSTn),
.push(de_ff_push),
.pop(de_ff_pop),
.look_ahead(de_ff_ahead),
.flush(de_ff_flush),
.clear(de_ff_clear),
.de_ff_ini(de_ff_ini),
.pack_en(pack_en),
.swid16(arb_chcsr[11]),
.swid32(arb_chcsr[12]),
.cvtp2(cvtp2),
.cv8t16(cv8t16),
.cv8t32(cv8t32),
.cv16t32(cv16t32),
.adi(de_ff_ado),
.dti(de_ff_dto),
.ff_dto(ff_dto),
.ff_empty(ff_empty),
.ff_eq1(ff_eq1),
.ff_eq2(ff_eq2),
.ff_geth(ff_geth),
.ff_2ltfl(ff_2ltfl),
.ff_1ltfl(ff_1ltfl),
.ff_q_full(ff_q_full),
.ff_part_wd(ff_part_wd),
.ff_cbe(ff_cbe),
.ff_cnv_q_vld(ff_cnv_q_vld),
.ff_wr(ff_wr)
);
dma_ctlrf ctl_rf
(
.HCLK(HCLK),
.HRSTn(HRSTn),
.slv_ad(slv_ad),
.slv_ad_d1(slv_ad_d1),
.slv_wdti(slv_dt),
.slv_sz(slv_sz),
.slv_wr_d1(slv_wr_d1),
.slv_rf_sel(slv_rf_req),
.de_st_idle(de_st[0]),
.de_st_upd(de_st[5]),
.de_st_llp0(de_st[6]),
.de_sad_we(de_sad_we),
.de_dad_we(de_dad_we),
`ifdef DMA_HAVE_LINKLIST
.de_llp_we(de_llp_we),
`endif
.de_tsz_we(de_tsz_we),
.de_en_clr(de_en_clr),
`ifdef DMA_HAVE_LINKLIST
.de_csr_we(de_csr_we),
.de_llpen_we(de_llpen_we),
`endif
.de_err_notify(de_err_notify),
.tsz_eq0(tsz_eq0),
.de_tc_st(de_tc_st),
.de_sad(de_sad),
.de_dad(de_dad),
`ifdef DMA_HAVE_LINKLIST
.de_llp(de_llp),
`endif
.de_tsz(de_tsz),
.de_csr(de_csr),
`ifdef DMA_HAVE_LINKLIST
.de_llpen(de_llpen),
`endif
.de_busy(de_busy),
.arb_ch_sel(arb_ch_sel),
.rf_cherr(rf_cherr),
.rf_dto(rf_dto),
.dmaint(dmaint),
.dmaint_tc(dmaint_tc),
.dmaint_err(dmaint_err),
.csr(csr),
.sync(sync),
.err(err),
.c0csr(c0csr),
.c0cfg(c0cfg),
.c0sad(c0sad),
.c0dad(c0dad),
`ifdef DMA_HAVE_LINKLIST
.c0llp(c0llp),
`endif
.c0tsz(c0tsz),
`ifdef DMA_HAVE_AHB1
`ifdef DMA_HAVE_BRIDGE
.c0dmabs(c0dmabs),
.c0brbs(c0brbs),
`endif
`endif
`ifdef DMA_HAVE_LINKLIST
.c0llpen(c0llpen),
`endif
.c0abt(c0abt)
`ifdef DMA_HAVE_CH1
,.c1csr(c1csr),
.c1cfg(c1cfg),
.c1sad(c1sad),
.c1dad(c1dad),
`ifdef DMA_HAVE_LINKLIST
.c1llp(c1llp),
`endif
.c1tsz(c1tsz),
`ifdef DMA_HAVE_AHB1
`ifdef DMA_HAVE_BRIDGE
.c1dmabs(c1dmabs),
.c1brbs(c1brbs),
`endif
`endif
`ifdef DMA_HAVE_LINKLIST
.c1llpen(c1llpen),
`endif
.c1abt(c1abt)
`endif
`ifdef DMA_HAVE_CH2
,.c2csr(c2csr),
.c2cfg(c2cfg),
.c2sad(c2sad),
.c2dad(c2dad),
`ifdef DMA_HAVE_LINKLIST
.c2llp(c2llp),
`endif
.c2tsz(c2tsz),
`ifdef DMA_HAVE_AHB1
`ifdef DMA_HAVE_BRIDGE
.c2dmabs(c2dmabs),
.c2brbs(c2brbs),
`endif
`endif
`ifdef DMA_HAVE_LINKLIST
.c2llpen(c2llpen),
`endif
.c2abt(c2abt)
`endif
`ifdef DMA_HAVE_CH3
,.c3csr(c3csr),
.c3cfg(c3cfg),
.c3sad(c3sad),
.c3dad(c3dad),
`ifdef DMA_HAVE_LINKLIST
.c3llp(c3llp),
`endif
.c3tsz(c3tsz),
`ifdef DMA_HAVE_AHB1
`ifdef DMA_HAVE_BRIDGE
.c3dmabs(c3dmabs),
.c3brbs(c3brbs),
`endif
`endif
`ifdef DMA_HAVE_LINKLIST
.c3llpen(c3llpen),
`endif
.c3abt(c3abt)
`endif
`ifdef DMA_HAVE_CH4
,.c4csr(c4csr),
.c4cfg(c4cfg),
.c4sad(c4sad),
.c4dad(c4dad),
`ifdef DMA_HAVE_LINKLIST
.c4llp(c4llp),
`endif
.c4tsz(c4tsz),
`ifdef DMA_HAVE_AHB1
`ifdef DMA_HAVE_BRIDGE
.c4dmabs(c4dmabs),
.c4brbs(c4brbs),
`endif
`endif
`ifdef DMA_HAVE_LINKLIST
.c4llpen(c4llpen),
`endif
.c4abt(c4abt)
`endif
`ifdef DMA_HAVE_CH5
,.c5csr(c5csr),
.c5cfg(c5cfg),
.c5sad(c5sad),
.c5dad(c5dad),
`ifdef DMA_HAVE_LINKLIST
.c5llp(c5llp),
`endif
.c5tsz(c5tsz),
`ifdef DMA_HAVE_AHB1
`ifdef DMA_HAVE_BRIDGE
.c5dmabs(c5dmabs),
.c5brbs(c5brbs),
`endif
`endif
`ifdef DMA_HAVE_LINKLIST
.c5llpen(c5llpen),
`endif
.c5abt(c5abt)
`endif
`ifdef DMA_HAVE_CH6
,.c6csr(c6csr),
.c6cfg(c6cfg),
.c6sad(c6sad),
.c6dad(c6dad),
`ifdef DMA_HAVE_LINKLIST
.c6llp(c6llp),
`endif
.c6tsz(c6tsz),
`ifdef DMA_HAVE_AHB1
`ifdef DMA_HAVE_BRIDGE
.c6dmabs(c6dmabs),
.c6brbs(c6brbs),
`endif
`endif
`ifdef DMA_HAVE_LINKLIST
.c6llpen(c6llpen),
`endif
.c6abt(c6abt)
`endif
`ifdef DMA_HAVE_CH7
,.c7csr(c7csr),
.c7cfg(c7cfg),
.c7sad(c7sad),
.c7dad(c7dad),
`ifdef DMA_HAVE_LINKLIST
.c7llp(c7llp),
`endif
.c7tsz(c7tsz),
`ifdef DMA_HAVE_AHB1
`ifdef DMA_HAVE_BRIDGE
.c7dmabs(c7dmabs),
.c7brbs(c7brbs),
`endif
`endif
`ifdef DMA_HAVE_LINKLIST
.c7llpen(c7llpen),
`endif
.c7abt(c7abt)
`endif
);
dma_chsel ch_sel(
.HCLK(HCLK),
.HRSTn(HRSTn),
.dma_req(dma_req),
.dma_ack(dma_ack),
.dma_tc(dma_tc),
.csr(csr), .sync(sync),
.de_err_notify(de_err_notify),
.c0csr(c0csr), .c0cfg(c0cfg), .c0sad(c0sad),
.c0dad(c0dad),
`ifdef DMA_HAVE_LINKLIST
.c0llp(c0llp),
`endif
.c0tsz(c0tsz),
.c0abt(c0abt),
`ifdef DMA_HAVE_LINKLIST
.c0llpen(c0llpen),
`endif
`ifdef DMA_HAVE_CH1
.c1csr(c1csr), .c1cfg(c1cfg), .c1sad(c1sad),
.c1dad(c1dad),
`ifdef DMA_HAVE_LINKLIST
.c1llp(c1llp),
`endif
.c1tsz(c1tsz),
.c1abt(c1abt),
`ifdef DMA_HAVE_LINKLIST
.c1llpen(c1llpen),
`endif
`endif
`ifdef DMA_HAVE_CH2
.c2csr(c2csr), .c2cfg(c2cfg), .c2sad(c2sad),
.c2dad(c2dad),
`ifdef DMA_HAVE_LINKLIST
.c2llp(c2llp),
`endif
.c2tsz(c2tsz),
.c2abt(c2abt),
`ifdef DMA_HAVE_LINKLIST
.c2llpen(c2llpen),
`endif
`endif
`ifdef DMA_HAVE_CH3
.c3csr(c3csr), .c3cfg(c3cfg), .c3sad(c3sad),
.c3dad(c3dad),
`ifdef DMA_HAVE_LINKLIST
.c3llp(c3llp),
`endif
.c3tsz(c3tsz),
.c3abt(c3abt),
`ifdef DMA_HAVE_LINKLIST
.c3llpen(c3llpen),
`endif
`endif
`ifdef DMA_HAVE_CH4
.c4csr(c4csr), .c4cfg(c4cfg), .c4sad(c4sad),
.c4dad(c4dad),
`ifdef DMA_HAVE_LINKLIST
.c4llp(c4llp),
`endif
.c4tsz(c4tsz),
.c4abt(c4abt),
`ifdef DMA_HAVE_LINKLIST
.c4llpen(c4llpen),
`endif
`endif
`ifdef DMA_HAVE_CH5
.c5csr(c5csr), .c5cfg(c5cfg), .c5sad(c5sad),
.c5dad(c5dad),
`ifdef DMA_HAVE_LINKLIST
.c5llp(c5llp),
`endif
.c5tsz(c5tsz),
.c5abt(c5abt),
`ifdef DMA_HAVE_LINKLIST
.c5llpen(c5llpen),
`endif
`endif
`ifdef DMA_HAVE_CH6
.c6csr(c6csr), .c6cfg(c6cfg), .c6sad(c6sad),
.c6dad(c6dad),
`ifdef DMA_HAVE_LINKLIST
.c6llp(c6llp),
`endif
.c6tsz(c6tsz),
.c6abt(c6abt),
`ifdef DMA_HAVE_LINKLIST
.c6llpen(c6llpen),
`endif
`endif
`ifdef DMA_HAVE_CH7
.c7csr(c7csr), .c7cfg(c7cfg), .c7sad(c7sad),
.c7dad(c7dad),
`ifdef DMA_HAVE_LINKLIST
.c7llp(c7llp),
`endif
.c7tsz(c7tsz),
.c7abt(c7abt),
`ifdef DMA_HAVE_LINKLIST
.c7llpen(c7llpen),
`endif
`endif
.arb_ch_sel(arb_ch_sel),
.arb_chcsr(arb_chcsr),
.arb_chsad(arb_chsad),
.arb_chdad(arb_chdad),
`ifdef DMA_HAVE_LINKLIST
.arb_chllp(arb_chllp),
`endif
.arb_chtsz(arb_chtsz),
.arb_chabt(arb_chabt),
`ifdef DMA_HAVE_LINKLIST
.arb_chllpen(arb_chllpen),
`endif
.arb_abt_any(arb_abt_any),
.de_ack(de_ack),
.de_stup(de_st[5]),
.de_st_idle(de_st[0]),
.de_abt_on_idle(de_abt_on_idle),
.tsz_eq0(tsz_eq0),
.arb_req(arb_req)
);
dma_ahbslv ahb_slv(
.HCLK(HCLK),
.HRSTn(HRSTn),
.hreadyin(hreadyin),
.hsel_reg(hsel_reg),
`ifdef DMA_HAVE_AHB1
`ifdef DMA_HAVE_BRIDGE
.hsel_br(hsel_br),
`endif
`endif
.htrans(htrans),
.hsize(hsize),
.hprot(hprot),
.hwrite(hwrite),
.haddr(haddr),
.hwdata(hwdata),
.hresp_reg(hresp_reg),
.hreadyout_reg(hreadyout_reg),
.hrdata_reg(hrdata_reg),
`ifdef DMA_HAVE_AHB1
`ifdef DMA_HAVE_BRIDGE
.hresp_br(hresp_br),
.hreadyout_br(hreadyout_br),
.hrdata_br(hrdata_br),
`endif
`endif
.rf_dti(rf_dto),
`ifdef DMA_HAVE_AHB1
`ifdef DMA_HAVE_BRIDGE
.de_arb_br(m1_arb_br),
`endif
`endif
.m0endian(csr[1]),
.m1endian(csr[2]),
.m1_dt_st(m1_dt_st),
`ifdef DMA_HAVE_AHB1
`ifdef DMA_HAVE_BRIDGE
.h1trans(h1trans),
.h1rdata(h1rdata),
.h1readyin(h1readyin),
.h1resp(h1resp),
`endif
`endif
.slv_ado(slv_ad),
.slv_ad_d1o(slv_ad_d1),
.slv_dto(slv_dt),
.slv_szo(slv_sz),
.slv_sz_d1o(slv_sz_d1),
.slv_pt_d1o(slv_pt_d1),
.slv_wr_d1o(slv_wr_d1),
.slv_rf_req(slv_rf_req)
`ifdef DMA_HAVE_AHB1
`ifdef DMA_HAVE_BRIDGE
,
.slv_br_req(slv_br_req),
.slv_br_dto(slv_br_dt),
.slv_brst_cmd(slv_brst_cmd),
.slv_brst_mscd(slv_brst_mscd)
`endif
`endif
);
`ifdef DMA_HAVE_AHB1
`ifdef DMA_HAVE_BRIDGE
dma_ahbdec m1_decoder(
.haddr(h1addr),
.c0dmabs(c0dmabs),
`ifdef DMA_HAVE_CH1
.c1dmabs(c1dmabs),
`endif
`ifdef DMA_HAVE_CH2
.c2dmabs(c2dmabs),
`endif
`ifdef DMA_HAVE_CH3
.c3dmabs(c3dmabs),
`endif
`ifdef DMA_HAVE_CH4
.c4dmabs(c4dmabs),
`endif
`ifdef DMA_HAVE_CH5
.c5dmabs(c5dmabs),
`endif
`ifdef DMA_HAVE_CH6
.c6dmabs(c6dmabs),
`endif
`ifdef DMA_HAVE_CH7
.c7dmabs(c7dmabs),
`endif
.c0brbs(c0brbs),
`ifdef DMA_HAVE_CH1
.c1brbs(c1brbs),
`endif
`ifdef DMA_HAVE_CH2
.c2brbs(c2brbs),
`endif
`ifdef DMA_HAVE_CH3
.c3brbs(c3brbs),
`endif
`ifdef DMA_HAVE_CH4
.c4brbs(c4brbs),
`endif
`ifdef DMA_HAVE_CH5
.c5brbs(c5brbs),
`endif
`ifdef DMA_HAVE_CH6
.c6brbs(c6brbs),
`endif
`ifdef DMA_HAVE_CH7
.c7brbs(c7brbs),
`endif
.hsel_dma(h1sel_dma),
.hsel_br (h1sel_br)
);
dma_ahbmux m1_mux(
.HCLK(HCLK),
.HRSTn(HRSTn),
.htrans(h1trans),
.hsel_dma(h1sel_dma),
.hsel_br (h1sel_br),
.hrdt0_dma(h1rdt0_dma),
`ifdef DMA_HAVE_CH1
.hrdt1_dma(h1rdt1_dma),
`endif
`ifdef DMA_HAVE_CH2
.hrdt2_dma(h1rdt2_dma),
`endif
`ifdef DMA_HAVE_CH3
.hrdt3_dma(h1rdt3_dma),
`endif
`ifdef DMA_HAVE_CH4
.hrdt4_dma(h1rdt4_dma),
`endif
`ifdef DMA_HAVE_CH5
.hrdt5_dma(h1rdt5_dma),
`endif
`ifdef DMA_HAVE_CH6
.hrdt6_dma(h1rdt6_dma),
`endif
`ifdef DMA_HAVE_CH7
.hrdt7_dma(h1rdt7_dma),
`endif
.hrp0_dma(h1rp0_dma),
`ifdef DMA_HAVE_CH1
.hrp1_dma(h1rp1_dma),
`endif
`ifdef DMA_HAVE_CH2
.hrp2_dma(h1rp2_dma),
`endif
`ifdef DMA_HAVE_CH3
.hrp3_dma(h1rp3_dma),
`endif
`ifdef DMA_HAVE_CH4
.hrp4_dma(h1rp4_dma),
`endif
`ifdef DMA_HAVE_CH5
.hrp5_dma(h1rp5_dma),
`endif
`ifdef DMA_HAVE_CH6
.hrp6_dma(h1rp6_dma),
`endif
`ifdef DMA_HAVE_CH7
.hrp7_dma(h1rp7_dma),
`endif
.hrdy0_dma(h1rdy0_dma),
`ifdef DMA_HAVE_CH1
.hrdy1_dma(h1rdy1_dma),
`endif
`ifdef DMA_HAVE_CH2
.hrdy2_dma(h1rdy2_dma),
`endif
`ifdef DMA_HAVE_CH3
.hrdy3_dma(h1rdy3_dma),
`endif
`ifdef DMA_HAVE_CH4
.hrdy4_dma(h1rdy4_dma),
`endif
`ifdef DMA_HAVE_CH5
.hrdy5_dma(h1rdy5_dma),
`endif
`ifdef DMA_HAVE_CH6
.hrdy6_dma(h1rdy6_dma),
`endif
`ifdef DMA_HAVE_CH7
.hrdy7_dma(h1rdy7_dma),
`endif
.hrdt0_br(h1rdt0_br),
`ifdef DMA_HAVE_CH1
.hrdt1_br(h1rdt1_br),
`endif
`ifdef DMA_HAVE_CH2
.hrdt2_br(h1rdt2_br),
`endif
`ifdef DMA_HAVE_CH3
.hrdt3_br(h1rdt3_br),
`endif
`ifdef DMA_HAVE_CH4
.hrdt4_br(h1rdt4_br),
`endif
`ifdef DMA_HAVE_CH5
.hrdt5_br(h1rdt5_br),
`endif
`ifdef DMA_HAVE_CH6
.hrdt6_br(h1rdt6_br),
`endif
`ifdef DMA_HAVE_CH7
.hrdt7_br(h1rdt7_br),
`endif
.hrp0_br(h1rp0_br),
`ifdef DMA_HAVE_CH1
.hrp1_br(h1rp1_br),
`endif
`ifdef DMA_HAVE_CH2
.hrp2_br(h1rp2_br),
`endif
`ifdef DMA_HAVE_CH3
.hrp3_br(h1rp3_br),
`endif
`ifdef DMA_HAVE_CH4
.hrp4_br(h1rp4_br),
`endif
`ifdef DMA_HAVE_CH5
.hrp5_br(h1rp5_br),
`endif
`ifdef DMA_HAVE_CH6
.hrp6_br(h1rp6_br),
`endif
`ifdef DMA_HAVE_CH7
.hrp7_br(h1rp7_br),
`endif
.hrdy0_br(h1rdy0_br),
`ifdef DMA_HAVE_CH1
.hrdy1_br(h1rdy1_br),
`endif
`ifdef DMA_HAVE_CH2
.hrdy2_br(h1rdy2_br),
`endif
`ifdef DMA_HAVE_CH3
.hrdy3_br(h1rdy3_br),
`endif
`ifdef DMA_HAVE_CH4
.hrdy4_br(h1rdy4_br),
`endif
`ifdef DMA_HAVE_CH5
.hrdy5_br(h1rdy5_br),
`endif
`ifdef DMA_HAVE_CH6
.hrdy6_br(h1rdy6_br),
`endif
`ifdef DMA_HAVE_CH7
.hrdy7_br(h1rdy7_br),
`endif
.hrdata(h1rdata),
.hresp(h1resp),
.hreadyin(h1readyin)
);
`endif
`endif
endmodule
|
`include "../include/x_def.v"
module BDMA (/* ---------- Inputs : ---------- */
BSreqx, BSack,
X_MMAP, X_BMODE, T_ED, T_RSTn,
GRST, PM_bdry_sel,
ENS12, ECS12, ENS13, ECS13,
ENS14, ECS14, ENS0,
DSPCLK, CM_rd, PMDin,
DMDin,
BOOT, GO_STEAL,
BCNT_we, BCTL_we, BOVL_we, BIAD_we,
BEAD_we, selBCNT, selBCTL, selBOVL,
selBIAD, selBEAD,
`ifdef FD_DFT
SCAN_TEST,
`endif
BDMWR_cyc, BPMWR_cyc, BDMRD_cyc,
BPMRD_cyc, BSreq,
BDMAmode, BMpage, BEAD,
BWdataBUF, BDIR, BWRn,
BWend,
BDMA_end, BDMA_boot, BCM_cyc, BCMRD_cyc,
BRdataBUF, BOVL, BM_cyc,
T_BDMA, BPM_cyc, BDM_cyc,
BIAD, BRST,
BDMAmmio, bdmaDMD_oe, bdmaPMD_oe
);
input [23:0] CM_rd;
input [15:0] PMDin;
input [15:0] DMDin;
input [7:0] T_ED;
input X_MMAP,
X_BMODE,
GO_STEAL,
PM_bdry_sel,
T_RSTn,
GRST,
BSreqx,
BSack,
ENS12,
ECS12,
ENS13,
ECS13,
ENS14,
ECS14,
ENS0,
DSPCLK,
BOOT,
BCNT_we,
BCTL_we,
BOVL_we,
BIAD_we,
BEAD_we,
selBCNT,
selBCTL,
selBOVL,
selBIAD,
selBEAD;
`ifdef FD_DFT
input SCAN_TEST;
`endif
output [23:0] BRdataBUF;
output [7:0] BWdataBUF;
output [15:0] BDMAmmio;
output [13:0] BEAD, BIAD;
output [7:0] BMpage;
output [11:0] BOVL;
output BDMAmode,
BDMA_boot,
BDMA_end,
BSreq,
BDIR,
BWRn,
BDMWR_cyc,
BPMWR_cyc,
BDMRD_cyc,
BPMRD_cyc,
BCMRD_cyc,
bdmaDMD_oe,
bdmaPMD_oe,
BCM_cyc,
BPM_cyc,
BDM_cyc,
T_BDMA,
BRST,
BM_cyc,
BWend;
reg BDMA_boot, BDMAmode, BSreq, BMcyc_del, BM_cyc,
BWRn, WRlat, DM_2nd, BRST_s2;
reg [23:0] BRdataBUF;
reg [7:0] BWdataBUF;
reg [15:0] BCTL;
reg [13:0] BWCOUNT, BIAD, BEAD;
reg [11:0] BOVL;
reg [1:0] CMcnt;
wire BDMA_end, BDIR, RDlat, set_BSreq,
BDM_en, BPM_en, rst_BSreq, BDMACLK,
BCM_en, BPCM_en, BCM_cyc,
pullH_WR, BPM_cyc, BDM_cyc,
load_BRH, BWcnt_end,
load_BRM, load_BRL, load_BWH, load_BWM,
load_BWL, BRDcyc, Word_OK, BCMRD_cyc, BPMRD_cyc,
CMWord_OK, PMWord_OK, CMcnteq0, CMcnteq1,
CMcnteq2, BDMRD_cyc, DMWord_OK, DM_fullW,
MSB_align, LSB_align, T_BDMA, BRST_s1, BRST,
BCMWR_cyc, BPMWR_cyc, BDMWR_cyc, BWRcyc, BM_begin,
bdmaDMD_oe, bdmaPMD_oe;
wire selCM, selPM;
reg [23:0] BWdataBUF_h;
wire [15:0] BDMAmmio;
wire [7:0] BMpage;
wire [4:0] BMWAIT;
`ifdef FD_GTCLK
`ifdef FD_DFT
GTECH_OR2 utm0 (.Z(BDMACLK_enb), .A(BDMAmode), .B(SCAN_TEST));
GtCLK_OR_NOT ckBDMA (.Z(BDMACLK), .B(BDMACLK_enb), .A(DSPCLK));
`else
GtCLK_OR_NOT ckBDMA (.Z(BDMACLK), .B(BDMAmode), .A(DSPCLK));
`endif
`else
assign #`da BDMACLK = DSPCLK;
`endif
`ifdef FD_DFT
reg RST_pin_h, RST_h;
wire RST_pin, RST;
always @(posedge DSPCLK) RST_pin_h <= #`db !T_RSTn;
always @(posedge DSPCLK) RST_h <= #`db GRST;
assign RST_pin = SCAN_TEST ? !T_RSTn : RST_pin_h;
assign RST = SCAN_TEST ? GRST : RST_h;
`else
reg RST_pin, RST;
always @(posedge DSPCLK) RST_pin <= #`db !T_RSTn;
always @(posedge DSPCLK) RST <= #`db GRST;
`endif
always @(posedge DSPCLK or posedge RST) begin
if(RST) BDMAmode <= #`db 1'b0;
else if (BDMA_end) BDMAmode <= #`db 1'b0;
else BDMAmode <= #`db |{BWCOUNT[13:0]};
end
always @(posedge DSPCLK or posedge RST_pin)
if (RST_pin) BDMA_boot <= #`db !(X_MMAP || X_BMODE);
else if (BDMA_end) BDMA_boot <= #`db 1'b0;
assign #`da BDMA_end = Word_OK && (BWCOUNT == 13'h1);
always @(posedge DSPCLK)
BM_cyc <= #`db ENS12 | ENS13 | ENS14;
always @(posedge DSPCLK) BMcyc_del <= #`db BM_cyc;
assign #`da BM_begin = BM_cyc && !BMcyc_del;
always @(posedge DSPCLK or posedge RST_pin) begin
if(RST_pin)
BWCOUNT[13:0] <= #`db {8'b0, !(X_MMAP || X_BMODE), 5'b0};
else if (BCNT_we) BWCOUNT[13:0] <= #`db DMDin[13:0];
else if (Word_OK) BWCOUNT[13:0] <= #`db BWCOUNT[13:0] - 1;
end
always @(posedge DSPCLK or posedge RST) begin
if(RST) BCTL[15:0] <= #`db 16'h00f8;
else if (BCTL_we) BCTL[15:0] <= #`db (DMDin[7:4] == 4'h0) ?
{DMDin[15:8], 4'b1111, DMDin[3:0]} :
DMDin[15:0];
end
assign #`d0 BDIR = BCTL[2];
assign #`da BMpage[7:0] = BCTL[15:8];
always @(posedge DSPCLK or posedge RST) begin
if(RST) BOVL[11:0] <= #`db 12'h0;
else if (BOVL_we) BOVL[11:0] <= #`db DMDin[11:0];
end
assign #`da BDM_en = |{BCTL[1:0]} && BDMAmode && BM_cyc;
assign #`da selCM = PM_bdry_sel ? (BIAD[13] == 1'b0) :
!(BIAD[13:12] == 2'b11);
assign #`da selPM = PM_bdry_sel ? (BIAD[13] == 1'b1) :
(BIAD[13:12] == 2'b11);
assign #`da BPM_en = !(|{BCTL[1:0]}) && selPM && BDMAmode && BM_cyc;
assign #`da BCM_en = !(|{BCTL[1:0]}) && selCM && BDMAmode && BM_cyc;
assign #`da BPCM_en = BPM_en || BCM_en;
wire BWcnt_en, BWcnt_clr, BWend;
reg [4:0] BWcnt;
assign #`da BMWAIT[4:0] = BDIR ? {BCTL[7:4], 1'b1} : {1'b1, BCTL[7:4]};
assign #`da BWend = (BWcnt[4:0] == BMWAIT[4:0]);
assign #`da BWcnt_en = ECS12 && !BSreq;
assign #`da BWcnt_clr = ENS0;
always @(posedge DSPCLK or posedge RST) begin
if (RST) BWcnt[4:0] <= #`db 5'h0;
else if (BWcnt_clr) BWcnt[4:0] <= #`db 5'h0;
else if (BWcnt_en) BWcnt[4:0] <= #`db BWcnt + 1;
end
assign #`da BWcnt_end = (ECS13 || ECS14) && ENS0;
always @(posedge DSPCLK or posedge RST) begin
if (RST) BIAD[13:0] <= #`db 14'b0;
else if(BIAD_we) BIAD[13:0] <= #`db DMDin[13:0];
else if(Word_OK) BIAD[13:0] <= #`db BIAD[13:0] + 1;
end
always @(posedge DSPCLK or posedge RST) begin
if (RST) BEAD[13:0] <= #`db 14'h0;
else if(BEAD_we) BEAD[13:0] <= #`db DMDin[13:0];
else if(BWcnt_end) BEAD[13:0] <= #`db BEAD[13:0] +
{BPM_en && CMcnteq1,
!(BPM_en && CMcnteq1)};
end
assign #`da pullH_WR = BDIR && (BWcnt == BCTL[7:4] + 3);
always @(posedge BDMACLK or posedge RST) begin
if (RST) BWRn <= #`db 1'b1;
else if(pullH_WR) BWRn <= #`db 1'b1;
else if(WRlat) BWRn <= #`db 1'b0;
end
assign #`da set_BSreq = BDIR && BDMAmode ? BM_begin && BWRcyc :
RDlat && BRDcyc;
`ifdef FD_DFT
wire rst_BSreq_h;
assign #`da rst_BSreq_h = (RST || BSack);
assign #`da rst_BSreq = SCAN_TEST ? RST : rst_BSreq_h;
`else
assign #`da rst_BSreq = RST || BSack;
`endif
always @(posedge DSPCLK or posedge rst_BSreq) begin
if(rst_BSreq) BSreq <= #`db 1'b0;
else if (set_BSreq) BSreq <= #`db 1'b1;
end
assign #`da RDlat = (BWcnt == BMWAIT[4:0]) && !BDIR;
assign #`da load_BRH = RDlat && BPCM_en && CMcnteq0;
assign #`da load_BRM = RDlat && ((BPCM_en && CMcnteq1) ||
(DM_fullW && !DM_2nd) ||
MSB_align) ;
assign #`da load_BRL = RDlat && ((BCM_en && CMcnteq2) ||
(DM_fullW && DM_2nd) ||
LSB_align) ;
always @(posedge BDMACLK) begin
if (load_BRH) BRdataBUF[23:16] <= #`db T_ED[7:0];
else if (load_BRM) BRdataBUF[15: 8] <= #`db T_ED[7:0];
else if (load_BRL) BRdataBUF[ 7: 0] <= #`db T_ED[7:0];
else if (LSB_align) BRdataBUF[15: 8] <= #`db 8'h0;
else if (MSB_align) BRdataBUF[ 7: 0] <= #`db 8'h0;
end
always @(posedge BDMACLK) WRlat <= #`db (BWcnt == 5'h3) && BDIR && BM_cyc;
always @(posedge BDMACLK) begin
if(BSack) BWdataBUF_h[23:0] <= #`db {24{BCMWR_cyc}} & CM_rd[23:0] |
{{16{BPMWR_cyc}} & PMDin[15:0], 8'b0} |
{8'b0, {16{BDMWR_cyc}} & DMDin[15:0]} ;
end
assign #`da load_BWH = WRlat && BPCM_en && CMcnteq0;
assign #`da load_BWM = WRlat && ((BPCM_en && CMcnteq1) ||
(DM_fullW && !DM_2nd) ||
MSB_align) ;
assign #`da load_BWL = WRlat && ((BCM_en && CMcnteq2) ||
(DM_fullW && DM_2nd) ||
LSB_align) ;
always @(posedge BDMACLK) begin
if (load_BWH) BWdataBUF[7:0] <= #`db BWdataBUF_h[23:16];
else if (load_BWM) BWdataBUF[7:0] <= #`db BWdataBUF_h[15:8];
else if (load_BWL) BWdataBUF[7:0] <= #`db BWdataBUF_h[7:0];
end
assign #`da BRDcyc = BSreq || BCMRD_cyc || BPMRD_cyc || BDMRD_cyc ;
assign #`da BWRcyc = BCMWR_cyc || BPMWR_cyc || BDMWR_cyc;
assign #`da Word_OK = CMWord_OK || PMWord_OK || DMWord_OK;
assign #`da BCMRD_cyc = BCM_en && CMcnteq2 && !BDIR;
assign #`da BPMRD_cyc = BPM_en && CMcnteq1 && !BDIR;
assign #`da BCMWR_cyc = BCM_en && CMcnteq0 && BDIR;
assign #`da BPMWR_cyc = BPM_en && CMcnteq0 && BDIR;
assign #`da BCM_cyc = BCMRD_cyc || BCMWR_cyc;
assign #`da BPM_cyc = BPMRD_cyc || BPMWR_cyc;
assign #`da CMWord_OK = BWcnt_end && BCM_en && CMcnteq2;
assign #`da PMWord_OK = BWcnt_end && BPM_en && CMcnteq1;
always @(posedge BDMACLK or posedge RST) begin
if (RST) CMcnt[1:0] <= #`db 2'h0;
else if (CMWord_OK || PMWord_OK)
CMcnt[1:0] <= #`db 2'h0;
else if (BWcnt_end && BPCM_en)
CMcnt[1:0] <= #`db CMcnt[1:0] + 1;
end
assign #`da CMcnteq0 = (CMcnt[1:0] == 2'h0);
assign #`da CMcnteq1 = (CMcnt[1:0] == 2'h1);
assign #`da CMcnteq2 = (CMcnt[1:0] == 2'h2);
assign #`da BDM_cyc = BDMRD_cyc || BDMWR_cyc;
assign #`da BDMRD_cyc = !BDIR && BDM_en && (BCTL[1] ? 1'b1 : DM_2nd);
assign #`da BDMWR_cyc = BDIR && BDM_en && (BCTL[1] ? 1'b1 : !DM_2nd);
assign #`da DMWord_OK = BDM_en && (BCTL[1] ? BWcnt_end : DM_2nd && BWcnt_end) ;
always @(posedge BDMACLK or posedge RST ) begin
if (RST) DM_2nd <= #`db 1'b0;
else if (BWcnt_end && BDM_en) DM_2nd <= #`db !DM_2nd;
end
assign #`da DM_fullW = !BCTL[1] && BCTL[0];
assign #`da MSB_align = BCTL[1] && !BCTL[0];
assign #`da LSB_align = BCTL[1] && BCTL[0];
assign #`da bdmaDMD_oe = BSreqx && BDMRD_cyc && GO_STEAL;
assign #`da bdmaPMD_oe = BSreqx && BPMRD_cyc && GO_STEAL;
assign #`da T_BDMA = BDMA_end && !BOOT;
assign #`da BRST_s1 = BCTL[3] && BDMA_end;
always @(posedge DSPCLK or posedge RST)
if (RST) BRST_s2 <= #`db 1'b0;
else BRST_s2 <= #`db BRST_s1;
assign #`da BRST = BRST_s1 || BRST_s2;
assign #`da BDMAmmio = {16{selBEAD}} & {2'b0, BEAD[13:0]} |
{16{selBIAD}} & {2'b0, BIAD[13:0]} |
{16{selBCTL}} & BCTL[15:0] |
{16{selBCNT}} & {2'b0, BWCOUNT[13:0]} |
{16{selBOVL}} & {4'b0, BOVL[11:0]};
endmodule
|
`include "../include/x_def.v"
module BTB (/* ------------ Inputs : ------------- */
/*T_RST,*/ DSPCLK,
PPclr_h, GO_F, GO_D, GO_E, GO_C, IFA_nx[4:0],
IFA[13:0], EXA[13:0], Bterr_E, Taddr_E[13:0],
RTS_R, RTS_Ed, BR_Ed,
Ctrue,
TB_EN,
BTB_rd[25:0],
RTB_rd[11:0],
`ifdef FD_DFT
SCAN_TEST,
`endif
BTB_ra[4:0], BTB_wa[4:0], BTB_wd[25:0], BTB_web,
/*RTB_wd[11:0],*/ RTB_web,
BTaken_I, RTaken_I, PTaken_R, PTaken_E);
input [25:0] BTB_rd;
input [4:0] IFA_nx;
input [13:0] IFA,
EXA,
Taddr_E;
input [11:0] RTB_rd;
input /*T_RST,*/
DSPCLK,
PPclr_h,
GO_F,
GO_D,
GO_E,
GO_C,
Bterr_E,
Ctrue,
RTS_R, RTS_Ed,
BR_Ed,
TB_EN;
`ifdef FD_DFT
input SCAN_TEST;
`endif
output [4:0] BTB_wa,
BTB_ra;
output [25:0] BTB_wd;
output BTB_web,
RTB_web,
BTaken_I,
RTaken_I,
PTaken_R,
PTaken_E;
reg [8:0] Btag_R, Rtag_R;
reg [4:0] BTB_wa_d1;
reg [1:0] BTB_wd_d1;
reg [1:0] Bh_R, Rh_R,
nh_E;
reg [13:0] Bt_R;
reg [25:0] Dor_E,
Bwd_E;
reg RST,
Bv_R, Bhit_R, Rhit_R, PTaken_R,
Rv_R, Bhit_E, Rhit_E, PTaken_E,
BRTBwcyc, BTaken_R, BTaken_E;
wire [8:0] Btag_I, Rtag_I;
wire [4:0] BTB_ra_d1;
wire [1:0] Bh_I, Rh_I;
wire [13:0] Bt_I;
wire [25:0] Dor_R,
nEntry, Rwd_E, BRwd_E;
wire Bv_I, Rv_I,
Bhit_Ii, Rhit_Ii,
Bhit_I, Rhit_I,
Bwe_h, Rwe_h, Conf_I;
`ifdef FD_GTCLK
`ifdef FD_DFT
GTECH_NOR2 utm1 (.Z(BTBCLK_enb_dft), .A(TB_EN), .B(SCAN_TEST));
GTECH_NOR2 uk1 (.Z(BTBCLK_), .A(DSPCLK), .B(BTBCLK_enb_dft));
`else
GTECH_NOT uk0 (.Z(TB_EN_), .A(TB_EN));
GTECH_NOR2 uk1 (.Z(BTBCLK_), .A(DSPCLK), .B(TB_EN_));
`endif
GtCLK_NOT ckBTB (.Z(BTBCLK), .A(BTBCLK_));
`else
wire BTBCLK=DSPCLK;
`endif
assign #`d0 {Btag_I[8:0], Bv_I, Bt_I[13:0] } = BTB_rd[25:2];
assign #`d0 {Rtag_I[8:0], Rv_I } = RTB_rd[11:2];
assign #`d0 Bh_I[1:0] = Conf_I ? BTB_wd_d1[1:0] : BTB_rd[1:0];
assign #`d0 Rh_I[1:0] = Conf_I ? BTB_wd_d1[1:0] : RTB_rd[1:0];
assign #`da Bhit_Ii = (IFA[13:5] == Btag_I[8:0]) && Bv_I;
assign #`da Rhit_Ii = (IFA[13:5] == Rtag_I[8:0]) && Rv_I;
assign #`da Bhit_I = Bhit_Ii && !Conf_I;
assign #`da Rhit_I = Rhit_Ii && !Conf_I;
assign #`da BTaken_I = Bhit_I && (|{Bh_I[1:0]});
assign #`da RTaken_I = Rhit_I && (|{Rh_I[1:0]});
assign #`da Conf_I = !TB_EN ||
(BTB_ra_d1[4:0] == BTB_wa_d1[4:0]) && BRTBwcyc;
always @(posedge BTBCLK) begin
if (PPclr_h) begin
Bhit_R <= #`db 1'b0;
Rhit_R <= #`db 1'b0;
BTaken_R <= #`db 1'b0;
end
`ifdef FD_GTCLK
else if (GO_D) begin
`else
else if (GO_D & TB_EN) begin
`endif
Bhit_R <= #`db Bhit_I;
Rhit_R <= #`db Rhit_I;
BTaken_R <= #`db BTaken_I;
end
end
always @(posedge DSPCLK)
if (PPclr_h)
PTaken_R <= #`db 1'b0;
else if (GO_D)
PTaken_R <= #`db BTaken_I || RTaken_I;
always @(posedge BTBCLK) begin
`ifdef FD_GTCLK
if (GO_D) begin
`else
if (GO_D & TB_EN) begin
`endif
Btag_R[8:0] <= #`db Btag_I[8:0];
Bv_R <= #`db Bv_I;
Bh_R[1:0] <= #`db Bh_I[1:0];
Bt_R[13:0] <= #`db Bt_I[13:0];
Rtag_R[8:0] <= #`db Rtag_I[8:0];
Rv_R <= #`db Rv_I;
Rh_R[1:0] <= #`db Rh_I[1:0];
end
end
assign #`da Dor_R[25:0] = RTS_R ? {Rtag_R, Rv_R, 14'b0, Rh_R}
: {Btag_R, Bv_R, Bt_R, Bh_R};
always @(posedge BTBCLK) begin
if (PPclr_h) begin
Bhit_E <= #`db 1'b0;
Rhit_E <= #`db 1'b0;
BTaken_E <= #`db 1'b0;
end
`ifdef FD_GTCLK
else if (GO_E) begin
`else
else if (GO_E & TB_EN) begin
`endif
Bhit_E <= #`db Bhit_R;
Rhit_E <= #`db Rhit_R;
BTaken_E <= #`db BTaken_R;
end
end
always @(posedge DSPCLK)
if (PPclr_h)
PTaken_E <= #`db 1'b0;
else if (GO_E)
PTaken_E <= #`db PTaken_R;
always @(posedge BTBCLK) begin
`ifdef FD_GTCLK
if (GO_E) Dor_E[25:0] <= #`db Dor_R[25:0];
`else
if (GO_E & TB_EN) Dor_E[25:0] <= #`db Dor_R[25:0];
`endif
end
assign #`da Bwe_h = (Bhit_E || Ctrue) && BR_Ed && GO_C;
assign #`da Rwe_h = (Rhit_E || Ctrue) && RTS_Ed && GO_C;
assign #`da nEntry[25:0] = {EXA[13:5], 1'b1, Taddr_E[13:0], nh_E[1:0]};
always @(Bhit_E or BTaken_E or Ctrue or Bterr_E or nEntry or
nh_E or Taddr_E or Dor_E) begin
casex ({Bhit_E, BTaken_E, Ctrue, Bterr_E})
4'b0xxx : Bwd_E[25:0] <= #`da nEntry[25:0];
4'b100x : Bwd_E[25:0] <= #`da {Dor_E[25:2], nh_E[1:0]};
4'b101x : Bwd_E[25:0] <= #`da {Dor_E[25:16], Taddr_E[13:0], nh_E[1:0]};
4'b110x : Bwd_E[25:0] <= #`da {Dor_E[25:2], nh_E[1:0]};
4'b1110 : Bwd_E[25:0] <= #`da {Dor_E[25:2], nh_E[1:0]};
4'b1111 : Bwd_E[25:0] <= #`da {Dor_E[25:16], Taddr_E[13:0], nh_E[1:0]};
default : Bwd_E[25:0] <= #`da Dor_E[25:0];
endcase
end
assign #`da Rwd_E[25:0] = Rhit_E ? {Dor_E[25:2], nh_E[1:0]}
: {EXA[13:5], 1'b1, 14'b0, nh_E[1:0]};
assign #`da BRwd_E[25:0] = BR_Ed ? Bwd_E[25:0] : Rwd_E[25:0];
parameter SN = 2'h0,
WN = 2'h1,
WT = 2'h2,
ST = 2'h3;
wire [1:0] Dor_E_temp = Dor_E[1:0];
always @(Dor_E_temp or Ctrue) begin
nh_E[1:0] <= #`da WN;
case (Dor_E_temp)
SN : nh_E[1:0] <= #`da Ctrue ? WN : SN;
WN : nh_E[1:0] <= #`da Ctrue ? WT : SN;
WT : nh_E[1:0] <= #`da Ctrue ? ST : WN;
ST : nh_E[1:0] <= #`da Ctrue ? ST : WT;
endcase
end
always @(posedge BTBCLK) begin
`ifdef FD_GTCLK
`else
if(TB_EN)
`endif
BRTBwcyc <= #`db Bwe_h || Rwe_h;
end
always @(posedge BTBCLK) begin
`ifdef FD_GTCLK
if (GO_C) begin
`else
if (GO_C & TB_EN) begin
`endif
BTB_wa_d1[4:0] <= #`db EXA[4:0];
BTB_wd_d1[1:0] <= #`db BTB_wd[1:0];
end
end
assign #`d0 BTB_ra_d1[4:0] = IFA[4:0];
assign #`da BTB_web = !Bwe_h;
assign #`da RTB_web = !Rwe_h;
assign #`da BTB_wd[25:0] = BRwd_E[25:0];
assign #`da BTB_wa[4:0] = EXA[4:0];
assign #`da BTB_ra[4:0] = GO_F ? IFA_nx : IFA[4:0];
endmodule
|
`include "../include/x_def.v"
module BTBmem (clk, wa[4:0], web, cs, wd[25:0], ra[4:0], rd[25:0]
`ifdef FD_DFT
, SCAN_TEST);
`else
);
`endif
input [4:0] wa,
ra;
input [25:0] wd;
input clk,
cs,
web;
`ifdef FD_DFT
input SCAN_TEST;
`endif
output [25:0] rd;
SW10201A I0 ( .A0(ra[0]),
.A1(ra[1]),
.A2(ra[2]),
.A3(ra[3]),
.A4(ra[4]),
.B0(wa[0]),
.B1(wa[1]),
.B2(wa[2]),
.B3(wa[3]),
.B4(wa[4]),
.CKA(clk),
.CKB(clk),
.CSA(cs),
.CSB(cs),
.DI0(wd[0]),
.DI1(wd[1]),
.DI2(wd[2]),
.DI3(wd[3]),
.DI4(wd[4]),
.DI5(wd[5]),
.DI6(wd[6]),
.DI7(wd[7]),
.DI8(wd[8]),
.DI9(wd[9]),
.DI10(wd[10]),
.DI11(wd[11]),
.DI12(wd[12]),
.DI13(wd[13]),
.DI14(wd[14]),
.DI15(wd[15]),
.DI16(wd[16]),
.DI17(wd[17]),
.DI18(wd[18]),
.DI19(wd[19]),
.DI20(wd[20]),
.DI21(wd[21]),
.DI22(wd[22]),
.DI23(wd[23]),
.DI24(wd[24]),
.DI25(wd[25]),
.DO0(rd[0]),
.DO1(rd[1]),
.DO2(rd[2]),
.DO3(rd[3]),
.DO4(rd[4]),
.DO5(rd[5]),
.DO6(rd[6]),
.DO7(rd[7]),
.DO8(rd[8]),
.DO9(rd[9]),
.DO10(rd[10]),
.DO11(rd[11]),
.DO12(rd[12]),
.DO13(rd[13]),
.DO14(rd[14]),
.DO15(rd[15]),
.DO16(rd[16]),
.DO17(rd[17]),
.DO18(rd[18]),
.DO19(rd[19]),
.DO20(rd[20]),
.DO21(rd[21]),
.DO22(rd[22]),
.DO23(rd[23]),
.DO24(rd[24]),
.DO25(rd[25]),
`ifdef FD_DFT
.OE(!SCAN_TEST),
`else
.OE(1'b1),
`endif
.WEB(web)
);
endmodule
|
`include "../include/x_def.v"
module RTBmem (clk, wa[4:0], web, cs, wd[11:0], ra[4:0], rd[11:0]
`ifdef FD_DFT
, SCAN_TEST);
`else
);
`endif
input [4:0] wa,
ra;
input [11:0] wd;
input clk,
cs,
web;
`ifdef FD_DFT
input SCAN_TEST;
`endif
output [11:0] rd;
SW10200C I0 ( .A0(ra[0]),
.A1(ra[1]),
.A2(ra[2]),
.A3(ra[3]),
.A4(ra[4]),
.B0(wa[0]),
.B1(wa[1]),
.B2(wa[2]),
.B3(wa[3]),
.B4(wa[4]),
.CKA(clk),
.CKB(clk),
.CSA(cs),
.CSB(cs),
.DI0(wd[0]),
.DI1(wd[1]),
.DI2(wd[2]),
.DI3(wd[3]),
.DI4(wd[4]),
.DI5(wd[5]),
.DI6(wd[6]),
.DI7(wd[7]),
.DI8(wd[8]),
.DI9(wd[9]),
.DI10(wd[10]),
.DI11(wd[11]),
.DO0(rd[0]),
.DO1(rd[1]),
.DO2(rd[2]),
.DO3(rd[3]),
.DO4(rd[4]),
.DO5(rd[5]),
.DO6(rd[6]),
.DO7(rd[7]),
.DO8(rd[8]),
.DO9(rd[9]),
.DO10(rd[10]),
.DO11(rd[11]),
`ifdef FD_DFT
.OE(!SCAN_TEST),
`else
.OE(1'b1),
`endif
.WEB(web)
);
endmodule
|
`define del 1
`include "../include/x_def.v"
module CLA15 (/* IN */ A, B, Cin,
/* OUT */ SUM);
input [15:1] A, B;
input Cin;
output [15:1] SUM;
wire [15:1] P, G, PS;
wire GS;
assign P[15:1] = A[15:1] | B[15:1];
assign G[15:1] = A[15:1] & B[15:1];
assign PS[15:1] = A[15:1] ^ B[15:1];
assign GS = Cin ? (G[1] | P[1]) : G[1];
wire [7:1] G1;
assign G1[1] = G[2] | (P[2] & GS );
assign G1[2] = G[4] | (P[4] & G[3] );
assign G1[3] = G[6] | (P[6] & G[5] );
assign G1[4] = G[8] | (P[8] & G[7] );
assign G1[5] = G[10] | (P[10] & G[9] );
assign G1[6] = G[12] | (P[12] & G[11]);
assign G1[7] = G[14] | (P[14] & G[13]);
wire [7:1] P1;
assign P1[1] = P[2] & P[1];
assign P1[2] = P[4] & P[3];
assign P1[3] = P[6] & P[5];
assign P1[4] = P[8] & P[7];
assign P1[5] = P[10] & P[9];
assign P1[6] = P[12] & P[11];
assign P1[7] = P[14] & P[13];
wire [4:1] G2;
assign G2[1] = G1[2] | (P1[2] & G1[1]);
assign G2[2] = G1[4] | (P1[4] & G1[3]);
assign G2[3] = G1[6] | (P1[6] & G1[5]);
assign G2[4] = G[15] | (P[15] & G1[7]);
wire [4:1] P2;
assign P2[1] = P1[2] & P1[1];
assign P2[2] = P1[4] & P1[3];
assign P2[3] = P1[6] & P1[5];
assign P2[4] = P[15] & P1[7];
wire [2:1] G3;
assign G3[1] = G2[2] | (P2[2] & G2[1]);
assign G3[2] = G2[4] | (P2[4] & G2[3]);
wire [2:1] P3;
assign P3[1] = P2[2] & P2[1];
assign P3[2] = P2[4] & P2[3];
wire C14, C13, C12, C11, C10;
wire C9, C8, C7, C6, C5;
wire C4, C3, C2, C1;
wire T1, T2, T3, T4, T5;
assign #`db C1 = GS;
assign #`db C2 = G1[1];
assign #`db C3 = G[3] | (G1[1] & P[3]);
assign #`db C4 = G2[1];
assign #`db C5 = G[5] | (G2[1] & P[5] );
assign #`db C6 = G1[3] | (G2[1] & P1[3]);
assign #`db C7 = G[7] | ( C6 & P[7] );
assign #`db C8 = G3[1];
assign #`db C9 = G[9] | (G3[1] & P[9] );
assign #`db C10 = G1[5] | (G3[1] & P1[5]);
assign #`db T1 = G[11] | (G1[5] & P[11]);
assign #`db C11 = T1 | (G3[1] & P[11] & P1[5]);
assign #`db C12 = G2[3] | (G3[1] & P2[3]);
assign #`db T2 = G[13] | (G2[3] & P[13]);
assign #`db C13 = T2 | (G3[1] & P2[3] & P[13]);
assign #`db T3 = G1[7] | (G2[3] & P1[7]);
assign #`db C14 = T3 | (G3[1] & P2[3] & P1[7]);
wire [15:1] SUM;
assign #`db SUM[1] = Cin ^ PS[1] ;
assign #`db SUM[2] = C1 ^ PS[2] ;
assign #`db SUM[3] = C2 ^ PS[3] ;
assign #`db SUM[4] = C3 ^ PS[4] ;
assign #`db SUM[5] = C4 ^ PS[5] ;
assign #`db SUM[6] = C5 ^ PS[6] ;
assign #`db SUM[7] = C6 ^ PS[7] ;
assign #`db SUM[8] = C7 ^ PS[8] ;
assign #`db SUM[9] = C8 ^ PS[9] ;
assign #`db SUM[10] = C9 ^ PS[10];
assign #`db SUM[11] = C10 ^ PS[11];
assign #`db SUM[12] = C11 ^ PS[12];
assign #`db SUM[13] = C12 ^ PS[13];
assign #`db SUM[14] = C13 ^ PS[14];
assign #`db SUM[15] = C14 ^ PS[15];
endmodule
|
`define del 1
`include "../include/x_def.v"
module CLA15_0 (/* IN */ A, B, Cin,
/* OUT */ SUM);
input [15:1] A, B;
input Cin;
output [15:1] SUM;
wire [15:1] P, G, PS;
wire GS;
assign P[15:1] = A[15:1] | B[15:1];
assign G[15:1] = A[15:1] & B[15:1];
assign PS[15:1] = A[15:1] ^ B[15:1];
assign GS = Cin ? (G[1] | P[1]) : G[1];
wire [7:1] G1;
assign G1[1] = G[2] | (P[2] & GS );
assign G1[2] = G[4] | (P[4] & G[3] );
assign G1[3] = G[6] | (P[6] & G[5] );
assign G1[4] = G[8] | (P[8] & G[7] );
assign G1[5] = G[10] | (P[10] & G[9] );
assign G1[6] = G[12] | (P[12] & G[11]);
assign G1[7] = G[14] | (P[14] & G[13]);
wire [7:1] P1;
assign P1[1] = P[2] & P[1];
assign P1[2] = P[4] & P[3];
assign P1[3] = P[6] & P[5];
assign P1[4] = P[8] & P[7];
assign P1[5] = P[10] & P[9];
assign P1[6] = P[12] & P[11];
assign P1[7] = P[14] & P[13];
wire [4:1] G2;
assign G2[1] = G1[2] | (P1[2] & G1[1]);
assign G2[2] = G1[4] | (P1[4] & G1[3]);
assign G2[3] = G1[6] | (P1[6] & G1[5]);
assign G2[4] = G[15] | (P[15] & G1[7]);
wire [4:1] P2;
assign P2[1] = P1[2] & P1[1];
assign P2[2] = P1[4] & P1[3];
assign P2[3] = P1[6] & P1[5];
assign P2[4] = P[15] & P1[7];
wire [2:1] G3;
assign G3[1] = G2[2] | (P2[2] & G2[1]);
assign G3[2] = G2[4] | (P2[4] & G2[3]);
wire [2:1] P3;
assign P3[1] = P2[2] & P2[1];
assign P3[2] = P2[4] & P2[3];
wire C14, C13, C12, C11, C10;
wire C9, C8, C7, C6, C5;
wire C4, C3, C2, C1;
wire T1, T2, T3, T4, T5;
assign #`db C1 = GS;
assign #`db C2 = G1[1];
assign #`db C3 = G[3] | (G1[1] & P[3]);
assign #`db C4 = G2[1];
assign #`db C5 = G[5] | (G2[1] & P[5] );
assign #`db C6 = G1[3] | (G2[1] & P1[3]);
assign #`db C7 = G[7] | ( C6 & P[7] );
assign #`db C8 = G3[1];
assign #`db C9 = G[9] | (G3[1] & P[9] );
assign #`db C10 = G1[5] | (G3[1] & P1[5]);
assign #`db T1 = G[11] | (G1[5] & P[11]);
assign #`db C11 = T1 | (G3[1] & P[11] & P1[5]);
assign #`db C12 = G2[3] | (G3[1] & P2[3]);
assign #`db T2 = G[13] | (G2[3] & P[13]);
assign #`db C13 = T2 | (G3[1] & P2[3] & P[13]);
assign #`db T3 = G1[7] | (G2[3] & P1[7]);
assign #`db C14 = T3 | (G3[1] & P2[3] & P1[7]);
wire [15:1] SUM;
assign #`db SUM[1] = Cin ^ PS[1] ;
assign #`db SUM[2] = C1 ^ PS[2] ;
assign #`db SUM[3] = C2 ^ PS[3] ;
assign #`db SUM[4] = C3 ^ PS[4] ;
assign #`db SUM[5] = C4 ^ PS[5] ;
assign #`db SUM[6] = C5 ^ PS[6] ;
assign #`db SUM[7] = C6 ^ PS[7] ;
assign #`db SUM[8] = C7 ^ PS[8] ;
assign #`db SUM[9] = C8 ^ PS[9] ;
assign #`db SUM[10] = C9 ^ PS[10];
assign #`db SUM[11] = C10 ^ PS[11];
assign #`db SUM[12] = C11 ^ PS[12];
assign #`db SUM[13] = C12 ^ PS[13];
assign #`db SUM[14] = C13 ^ PS[14];
assign #`db SUM[15] = C14 ^ PS[15];
endmodule
|
module CSA_d (/* IN */ INa, INb, INc,
SUM, COUT);
input INa, INb, INc;
output SUM, COUT;
wire TMP;
assign TMP = INa^ INb;
assign SUM = TMP ^ INc;
assign COUT = (INa & INb) | (INb & INc) | (INc & INa);
endmodule
|
/*--------------------------------------------------------------*/
/*--------------------------------------------------------------*/
/*--------------------------------------------------------------*/
/*--------------------------------------------------------------*/
`include "../include/x_def.v"
module DAG(/*------------------- Inputs ------------------------*/
DSPCLK, T_RST, GO_E, GO_C, EX_en, STBY,
MTIreg_E, MTLreg_E, MTMreg_E,
MFIreg_E, MFLreg_E, MFMreg_E,
MFDAG1_E, Post1_E, imAddr_R, DAG1D_R, DAG2D_R,
DAG1_EN, DOUBLE_R, idBR_R, Post2_E, MFDAG2_E,
DAG2_EN, DAG2P_R, DMAen_R,
IRE, IR,
MSTAT1, redoSTI_h, redoEX_h, PwriteI_Eg, DwriteI_Eg,
accPM_E, redoM_h,
STEAL, T0Sreqx, T1Sreqx, R0Sreqx, R1Sreqx,
SREQ, T0sack, T1sack, R0sack, R1sack,
R0IREG, R1IREG, T0IREG, T1IREG,
R0MREG, R1MREG, T0MREG, T1MREG,
DSreqx, BOOT, DCTL,
DMDid,
BSreqx, BPM_cyc, BDM_cyc, BIAD, BM_cyc,
ECYC,
`ifdef FD_DFT
SCAN_TEST,
`endif
T0wrap, T1wrap, R0wrap, R1wrap,
DMA_R, DMA, PMA_R, PMA,
DMAin, PMAin, dagDMD_do);
input [13:0] BIAD;
input BSreqx,
BPM_cyc,
BDM_cyc,
BM_cyc,
ECYC;
input DSPCLK,
T_RST;
input GO_E;
input GO_C;
input EX_en;
input MFDAG1_E;
input MFDAG2_E;
input Post1_E;
input Post2_E;
input imAddr_R;
input DAG1D_R;
input DAG2D_R;
input DAG1_EN;
input DAG2_EN;
input DOUBLE_R;
input idBR_R;
input MSTAT1;
input redoSTI_h;
input redoEX_h;
input redoM_h;
input PwriteI_Eg;
input DwriteI_Eg;
input accPM_E;
input STEAL;
input T0Sreqx;
input T1Sreqx;
input R0Sreqx;
input R1Sreqx;
input SREQ;
input T0sack;
input T1sack;
input R0sack;
input R1sack;
input DSreqx;
input BOOT;
input STBY;
input [7:0] MTIreg_E;
input [7:0] MTLreg_E;
input [7:0] MTMreg_E;
input [7:0] MFIreg_E;
input [7:0] MFLreg_E;
input [7:0] MFMreg_E;
input [2:0] R0IREG;
input [2:0] R1IREG;
input [2:0] T0IREG;
input [2:0] T1IREG;
input [1:0] R0MREG;
input [1:0] R1MREG;
input [1:0] T0MREG;
input [1:0] T1MREG;
input [15:0] DMDid;
input [14:0] DCTL;
input [17:0] IR;
input [3:0] IRE;
input DAG2P_R, DMAen_R;
`ifdef FD_DFT
input SCAN_TEST;
`endif
output T0wrap, T1wrap, R0wrap, R1wrap;
output [13:0] DMA_R, DMA, DMAin;
output [13:0] PMA_R, PMA, PMAin;
output [15:0] dagDMD_do;
/*------------------------------------------------------------------------------*/
wire [13:0] I1, L1, M1;
wire [13:0] I2, L2, M2;
wire [13:0] newI1, newI2;
wire [13:0] STA_C, IS_R2;
wire [2:0] STEALI_R, STEALM_R, STEALI_E;
wire SPreqx, Sackx, sel_PMA, sel_PMAR;
wire [15:0] dag1DMD_do, dag2DMD_do;
wire [13:0] I7_4, I_R7_4;
wire ldI7_4, ldI_R7_4;
assign dagDMD_do[15:0] = dag1DMD_do[15:0] | dag2DMD_do[15:0];
ILM1REG ilm1reg (/* IN */
DSPCLK, T_RST, GO_C, GO_E, EX_en, Post1_E, IR[17:0], IRE[3:0],
MTIreg_E[3:0], newI1[13:0], MTLreg_E[3:0],
MTMreg_E[3:0], MFIreg_E[3:0], MFLreg_E[3:0],
MFMreg_E[3:0], MSTAT1, MFDAG1_E,
DAG1D_R, DAG2D_R, imAddr_R, redoSTI_h, redoEX_h,
PwriteI_Eg, DwriteI_Eg, STEAL, T0Sreqx, T1Sreqx, R0Sreqx, R1Sreqx,
R0IREG[2:0], R1IREG[2:0], T0IREG[2:0], T1IREG[2:0],
R0MREG[1:0], R1MREG[1:0], T0MREG[1:0], T1MREG[1:0],
DSreqx, BOOT, STBY, redoM_h, accPM_E, SREQ,
PMA_R[13:0], PMA[13:0], DCTL[14:0], IS_R2[13:0],
T0sack, T1sack, R0sack, R1sack, DAG1_EN, newI2[13:0],
ldI7_4, ldI_R7_4, I7_4[13:0], I_R7_4[13:0],
Post2_E, DMAen_R,
BSreqx, BDM_cyc, BIAD[13:0], BM_cyc, ECYC,
`ifdef FD_DFT
SCAN_TEST,
`endif
I1[13:0], L1[13:0], M1[13:0], STEALI_R[2:0], STEALM_R[1:0],
STEALI_E[2:0], SPreqx, DMA_R[13:0], DMA[13:0], DMAin[13:0],
STA_C[13:0], sel_PMA, sel_PMAR, Sackx, DMDid[13:0],
dag1DMD_do[15:0]);
MODULO1 modulo1 (/* OUT */
newI1[13:0], T0wrap, T1wrap, R0wrap, R1wrap,
T0sack, T1sack, R0sack, R1sack, STEALI_E[2], wrap2,
DSPCLK, I1[13:0], M1[13:0], L1[13:0]);
ILM2REG ilm2reg (/* IN */
DSPCLK, T_RST, GO_E, GO_C, EX_en, DOUBLE_R, idBR_R, Post2_E,
MTIreg_E[7:4], MTLreg_E[7:4], MTMreg_E[7:4],
MFIreg_E[7:4], MFLreg_E[7:4], MFMreg_E[7:4],
newI2[13:0], IR[7:0], MFDAG2_E,
STEALI_R[2:0], STEALM_R[1:0], STEALI_E[2:0],
STEAL, SPreqx, redoM_h, STBY, redoSTI_h, sel_PMA, sel_PMAR,
DSreqx, BOOT, DCTL[14:0], STA_C[13:0], Sackx, DAG2_EN, DAG2P_R,
BSreqx, BPM_cyc, BIAD[13:0], BM_cyc, ECYC,
`ifdef FD_DFT
SCAN_TEST,
`endif
I2[13:0], L2[13:0], M2[13:0], PMA_R[13:0],
PMA[13:0], PMAin[13:0], IS_R2[13:0],
ldI7_4, ldI_R7_4, I7_4[13:0], I_R7_4[13:0],
DMDid[13:0], dag2DMD_do[15:0]);
MODULO2 modulo2 (/* OUT */
newI2[13:0], wrap2,
I2[13:0], M2[13:0], L2[13:0]);
endmodule
|
`define del 1
`include "../include/x_def.v"
module ILM1REG(/* IN */
DSPCLK, T_RST, GO_C, GO_E, EX_en, Post1_E, IR, IRE,
MTIreg_E, newI1, MTLreg_E,
MTMreg_E, MFIreg_E, MFLreg_E,
MFMreg_E, MSTAT1, MFDAG1_E,
DAG1D_R, DAG2D_R, immAddr_R, redoSTI_h, redoEX_h,
PwriteI_Eg, DwriteI_Eg, STEAL, T0Sreqx, T1Sreqx, R0Sreqx, R1Sreqx,
R0IREG, R1IREG, T0IREG, T1IREG,
R0MREG, R1MREG, T0MREG, T1MREG,
DSreqx, BOOT, STBY, redoM_h, accPM_E, SREQ,
DAG2A_R, PMA, DCTL, IS_R2,
T0sack, T1sack, R0sack, R1sack, DAG1_EN, newI2,
ldI7_4, ldI_R7_4, I7_4, I_R7_4,
Post2_E, DMAen_R,
BSreqx, BDM_cyc, BIAD, BM_cyc, ECYC,
`ifdef FD_DFT
SCAN_TEST,
`endif
I, L, M, STEALI_R, STEALM_R,
STEALI_E, SPreqx, DMA_R, DMA, DMAin,
STA_C, sel_PMA, sel_PMAR, Sackx,
DMDin, DMD);
/*----------------------------------------------*/
/*----------------------------------------------*/
input [13:0] BIAD;
input BSreqx, BDM_cyc, BM_cyc, ECYC;
input DSPCLK, T_RST, GO_C, GO_E, EX_en, Post1_E;
input [3:0] MTIreg_E, MTLreg_E, MTMreg_E;
input [13:0] newI1;
input [17:0] IR;
input [3:0] IRE;
input [3:0] MFIreg_E, MFLreg_E, MFMreg_E;
input MSTAT1, MFDAG1_E, immAddr_R;
input DAG1D_R, DAG2D_R, STEAL, DMAen_R;
input redoSTI_h, redoEX_h, PwriteI_Eg, DwriteI_Eg;
input T0Sreqx, T1Sreqx, R0Sreqx, R1Sreqx, redoM_h;
input [2:0] R0IREG, R1IREG, T0IREG, T1IREG;
input [1:0] R0MREG, R1MREG, T0MREG, T1MREG;
input DSreqx, BOOT, STBY, accPM_E;
input SREQ;
input [14:0] DCTL;
input [13:0] DAG2A_R;
input [13:0] PMA;
input [13:0] IS_R2;
input [13:0] newI2;
input T0sack, T1sack, R0sack, R1sack;
input DAG1_EN, Post2_E;
input ldI7_4, ldI_R7_4;
input [13:0] I7_4, I_R7_4;
`ifdef FD_DFT
input SCAN_TEST;
`endif
/*----------------------------------------------*/
/*----------------------------------------------*/
output [13:0] I, L, M;
output [13:0] DMA, DMA_R, DMAin;
output [13:0] STA_C;
output [2:0] STEALI_R, STEALI_E;
output [1:0] STEALM_R;
output SPreqx, sel_PMA, sel_PMAR;
output Sackx;
/*----------------------------------------------*/
/*----------------------------------------------*/
input [13:0] DMDin;
output [15:0] DMD;
`ifdef FD_DFT
reg RST_o;
wire RST;
always @(posedge DSPCLK) RST_o <= #`db T_RST;
assign RST = SCAN_TEST ? T_RST : RST_o;
`else
reg RST;
always @(posedge DSPCLK) RST <= #`db T_RST;
`endif
/*----------------------------------------------*/
/*----------------------------------------------*/
wire sel_STAC, sel_DMAR, sel_DMA, sel_BDMA;
assign sel_STAC = redoSTI_h;
assign sel_DMAR = !SREQ && !DwriteI_Eg && GO_E;
assign sel_DMA = !SREQ && DwriteI_Eg && GO_E
|| redoEX_h;
assign sel_PMAR = !SREQ && !PwriteI_Eg && GO_E;
assign sel_PMA = !SREQ && PwriteI_Eg && GO_E
|| redoEX_h;
/*----------------------------------------------*/
/*----------------------------------------------*/
wire SPreqx = T0Sreqx || T1Sreqx || R0Sreqx || R1Sreqx;
wire Sackx = T0sack || T1sack || R0sack || R1sack;
/*----------------------------------------------*/
/*----------------------------------------------*/
wire [2:0] STEALI_R;
wire [1:0] STEALM_R;
wire [13:0] Iin;
reg [2:0] STEALI_E;
reg [1:0] STEALM_E;
assign STEALI_R[2:0] = {3{T0Sreqx}} & T0IREG[2:0]
| {3{T1Sreqx}} & T1IREG[2:0]
| {3{R0Sreqx}} & R0IREG[2:0]
| {3{R1Sreqx}} & R1IREG[2:0];
assign STEALM_R[1:0] = {2{T0Sreqx}} & T0MREG[1:0]
| {2{T1Sreqx}} & T1MREG[1:0]
| {2{R0Sreqx}} & R0MREG[1:0]
| {2{R1Sreqx}} & R1MREG[1:0];
/*------------------------------------------------------*/
/*------------------------------------------------------*/
always @(posedge DSPCLK)
if (SREQ) STEALI_E[2:0] <= #`db STEALI_R[2:0];
assign #`db Iin[13:0] = (Post1_E | Sackx) ? newI1[13:0] : DMDin[13:0];
wire [1:0] updateI0, updateI1, updateI2, updateI3;
wire CLKI0enb, CLKI1enb, CLKI2enb, CLKI3enb;
wire [3:0] ldI;
wire [13:0] I0, I1, I2, I3;
assign updateI0[1] = Sackx && (STEALI_E[2:0] == 3'b000);
assign updateI0[0] = !Sackx && Post1_E && (IRE[3:2] == 2'b00) && EX_en;
assign updateI1[1] = Sackx && (STEALI_E[2:0] == 3'b001);
assign updateI1[0] = !Sackx && Post1_E && (IRE[3:2] == 2'b01) && EX_en;
assign updateI2[1] = Sackx && (STEALI_E[2:0] == 3'b010);
assign updateI2[0] = !Sackx && Post1_E && (IRE[3:2] == 2'b10) && EX_en;
assign updateI3[1] = Sackx && (STEALI_E[2:0] == 3'b011);
assign updateI3[0] = !Sackx && Post1_E && (IRE[3:2] == 2'b11) && EX_en;
assign CLKI0enb = !((MTIreg_E[0] && EX_en) || updateI0[1] || updateI0[0]);
assign CLKI1enb = !((MTIreg_E[1] && EX_en) || updateI1[1] || updateI1[0]);
assign CLKI2enb = !((MTIreg_E[2] && EX_en) || updateI2[1] || updateI2[0]);
assign CLKI3enb = !((MTIreg_E[3] && EX_en) || updateI3[1] || updateI3[0]);
assign ldI[0] = (MTIreg_E[0] && EX_en && GO_C)
|| (updateI0[0] && EX_en && GO_C) || updateI0[1];
assign ldI[1] = (MTIreg_E[1] && EX_en && GO_C)
|| (updateI1[0] && EX_en && GO_C) || updateI1[1];
assign ldI[2] = (MTIreg_E[2] && EX_en && GO_C)
|| (updateI2[0] && EX_en && GO_C) || updateI2[1];
assign ldI[3] = (MTIreg_E[3] && EX_en && GO_C)
|| (updateI3[0] && EX_en && GO_C) || updateI3[1];
`ifdef FD_DFT
REG14L I0_we(DSPCLK, RST, CLKI0enb, ldI[0], Iin[13:0], I0[13:0], SCAN_TEST);
REG14L I1_we(DSPCLK, RST, CLKI1enb, ldI[1], Iin[13:0], I1[13:0], SCAN_TEST);
REG14L I2_we(DSPCLK, RST, CLKI2enb, ldI[2], Iin[13:0], I2[13:0], SCAN_TEST);
REG14L I3_we(DSPCLK, RST, CLKI3enb, ldI[3], Iin[13:0], I3[13:0], SCAN_TEST);
`else
REG14L I0_we(DSPCLK, RST, CLKI0enb, ldI[0], Iin[13:0], I0[13:0]);
REG14L I1_we(DSPCLK, RST, CLKI1enb, ldI[1], Iin[13:0], I1[13:0]);
REG14L I2_we(DSPCLK, RST, CLKI2enb, ldI[2], Iin[13:0], I2[13:0]);
REG14L I3_we(DSPCLK, RST, CLKI3enb, ldI[3], Iin[13:0], I3[13:0]);
`endif
/*----------------------------------------------*/
/*----------------------------------------------*/
wire CLKL0enb, CLKL1enb, CLKL2enb, CLKL3enb;
wire [3:0] ldL;
wire [13:0] L0, L1, L2, L3;
assign CLKL0enb = !(MTLreg_E[0] && EX_en);
assign CLKL1enb = !(MTLreg_E[1] && EX_en);
assign CLKL2enb = !(MTLreg_E[2] && EX_en);
assign CLKL3enb = !(MTLreg_E[3] && EX_en);
assign ldL[0] = MTLreg_E[0] && EX_en && GO_C;
assign ldL[1] = MTLreg_E[1] && EX_en && GO_C;
assign ldL[2] = MTLreg_E[2] && EX_en && GO_C;
assign ldL[3] = MTLreg_E[3] && EX_en && GO_C;
`ifdef FD_DFT
REG14L L0_we(DSPCLK, RST, CLKL0enb, ldL[0], DMDin[13:0], L0[13:0], SCAN_TEST);
REG14L L1_we(DSPCLK, RST, CLKL1enb, ldL[1], DMDin[13:0], L1[13:0], SCAN_TEST);
REG14L L2_we(DSPCLK, RST, CLKL2enb, ldL[2], DMDin[13:0], L2[13:0], SCAN_TEST);
REG14L L3_we(DSPCLK, RST, CLKL3enb, ldL[3], DMDin[13:0], L3[13:0], SCAN_TEST);
`else
REG14L L0_we(DSPCLK, RST, CLKL0enb, ldL[0], DMDin[13:0], L0[13:0]);
REG14L L1_we(DSPCLK, RST, CLKL1enb, ldL[1], DMDin[13:0], L1[13:0]);
REG14L L2_we(DSPCLK, RST, CLKL2enb, ldL[2], DMDin[13:0], L2[13:0]);
REG14L L3_we(DSPCLK, RST, CLKL3enb, ldL[3], DMDin[13:0], L3[13:0]);
`endif
/*----------------------------------------------*/
/*----------------------------------------------*/
wire CLKM0enb, CLKM1enb, CLKM2enb, CLKM3enb;
wire [3:0] ldM;
wire [13:0] M0, M1, M2, M3;
assign CLKM0enb = !(MTMreg_E[0] && EX_en);
assign CLKM1enb = !(MTMreg_E[1] && EX_en);
assign CLKM2enb = !(MTMreg_E[2] && EX_en);
assign CLKM3enb = !(MTMreg_E[3] && EX_en);
assign ldM[0] = MTMreg_E[0] && EX_en && GO_C;
assign ldM[1] = MTMreg_E[1] && EX_en && GO_C;
assign ldM[2] = MTMreg_E[2] && EX_en && GO_C;
assign ldM[3] = MTMreg_E[3] && EX_en && GO_C;
`ifdef FD_DFT
REG14L M0_we(DSPCLK, RST, CLKM0enb, ldM[0], DMDin[13:0], M0[13:0], SCAN_TEST);
REG14L M1_we(DSPCLK, RST, CLKM1enb, ldM[1], DMDin[13:0], M1[13:0], SCAN_TEST);
REG14L M2_we(DSPCLK, RST, CLKM2enb, ldM[2], DMDin[13:0], M2[13:0], SCAN_TEST);
REG14L M3_we(DSPCLK, RST, CLKM3enb, ldM[3], DMDin[13:0], M3[13:0], SCAN_TEST);
`else
REG14L M0_we(DSPCLK, RST, CLKM0enb, ldM[0], DMDin[13:0], M0[13:0]);
REG14L M1_we(DSPCLK, RST, CLKM1enb, ldM[1], DMDin[13:0], M1[13:0]);
REG14L M2_we(DSPCLK, RST, CLKM2enb, ldM[2], DMDin[13:0], M2[13:0]);
REG14L M3_we(DSPCLK, RST, CLKM3enb, ldM[3], DMDin[13:0], M3[13:0]);
`endif
/*----------------------------------------------*/
/*----------------------------------------------*/
wire [13:0] Iout;
wire [1:0] ISEL;
wire [13:0] I_D;
assign ISEL[1:0] = redoM_h ? IRE[3:2]
: SPreqx ? STEALI_R[1:0] : IR[3:2] ;
assign I_D[13:0] = {14{(ISEL[1:0] == 2'b00) && !ldI[0]}} & I0[13:0] |
{14{(ISEL[1:0] == 2'b01) && !ldI[1]}} & I1[13:0] |
{14{(ISEL[1:0] == 2'b10) && !ldI[2]}} & I2[13:0] |
{14{(ISEL[1:0] == 2'b11) && !ldI[3]}} & I3[13:0] |
{14{(ISEL[1:0] == 2'b00) && ldI[0]}} & Iin[13:0] |
{14{(ISEL[1:0] == 2'b01) && ldI[1]}} & Iin[13:0] |
{14{(ISEL[1:0] == 2'b10) && ldI[2]}} & Iin[13:0] |
{14{(ISEL[1:0] == 2'b11) && ldI[3]}} & Iin[13:0] ;
`ifdef FD_RTL_SIM
wire [13:0] I_R;
wire [13:0] IS_R1;
wire [13:0] IS_R;
assign I_R[13:0] = {14{(IR[3:2] == 2'b00) && !ldI[0]}} & I0[13:0] |
{14{(IR[3:2] == 2'b01) && !ldI[1]}} & I1[13:0] |
{14{(IR[3:2] == 2'b10) && !ldI[2]}} & I2[13:0] |
{14{(IR[3:2] == 2'b11) && !ldI[3]}} & I3[13:0] |
{14{(IR[3:2] == 2'b00) && ldI[0]}} & Iin[13:0] |
{14{(IR[3:2] == 2'b01) && ldI[1]}} & Iin[13:0] |
{14{(IR[3:2] == 2'b10) && ldI[2]}} & Iin[13:0] |
{14{(IR[3:2] == 2'b11) && ldI[3]}} & Iin[13:0] ;
assign IS_R1[13:0] = {14{(STEALI_R[2:0] == 3'b000) && !ldI[0]}} & I0[13:0] |
{14{(STEALI_R[2:0] == 3'b001) && !ldI[1]}} & I1[13:0] |
{14{(STEALI_R[2:0] == 3'b010) && !ldI[2]}} & I2[13:0] |
{14{(STEALI_R[2:0] == 3'b011) && !ldI[3]}} & I3[13:0] |
{14{(STEALI_R[2:0] == 3'b000) && ldI[0]}} & Iin[13:0] |
{14{(STEALI_R[2:0] == 3'b001) && ldI[1]}} & Iin[13:0] |
{14{(STEALI_R[2:0] == 3'b010) && ldI[2]}} & Iin[13:0] |
{14{(STEALI_R[2:0] == 3'b011) && ldI[3]}} & Iin[13:0] ;
assign IS_R[13:0] = IS_R1[13:0] | IS_R2[13:0];
`else
wire [13:0] I_R3_0;
wire ldI_R3_0;
wire [13:0] IS_R3_0;
wire ldIS_R3_0;
wire [13:0] I3_0;
wire ldI3_0;
assign I_R3_0[13:0] = {14{(IR[3:2] == 2'b00) && !ldI[0]}} & I0[13:0] |
{14{(IR[3:2] == 2'b01) && !ldI[1]}} & I1[13:0] |
{14{(IR[3:2] == 2'b10) && !ldI[2]}} & I2[13:0] |
{14{(IR[3:2] == 2'b11) && !ldI[3]}} & I3[13:0] ;
assign ldI_R3_0 = (IR[3:2] == 2'b00) && ldI[0] ||
(IR[3:2] == 2'b01) && ldI[1] ||
(IR[3:2] == 2'b10) && ldI[2] ||
(IR[3:2] == 2'b11) && ldI[3] ;
assign IS_R3_0[13:0] = {14{(STEALI_R[2:0] == 3'b000) && !ldI[0]}} & I0[13:0] |
{14{(STEALI_R[2:0] == 3'b001) && !ldI[1]}} & I1[13:0] |
{14{(STEALI_R[2:0] == 3'b010) && !ldI[2]}} & I2[13:0] |
{14{(STEALI_R[2:0] == 3'b011) && !ldI[3]}} & I3[13:0] ;
assign ldIS_R3_0 = (STEALI_R[2:0] == 3'b000) && ldI[0] ||
(STEALI_R[2:0] == 3'b001) && ldI[1] ||
(STEALI_R[2:0] == 3'b010) && ldI[2] ||
(STEALI_R[2:0] == 3'b011) && ldI[3] ;
assign ldI3_0 = SPreqx ? ldIS_R3_0 : ldI_R3_0;
assign I3_0[13:0] = SPreqx ? IS_R3_0[13:0] : I_R3_0[13:0];
`endif
assign Iout[13:0] = {14{MFIreg_E[0]}} & I0[13:0] |
{14{MFIreg_E[1]}} & I1[13:0] |
{14{MFIreg_E[2]}} & I2[13:0] |
{14{MFIreg_E[3]}} & I3[13:0] ;
/*----------------------------------------------*/
/*----------------------------------------------*/
wire [13:0] Lout;
wire [13:0] L_D;
assign L_D[13:0] = {14{(ISEL[1:0] == 2'b00) && !ldL[0]}} & L0[13:0] |
{14{(ISEL[1:0] == 2'b01) && !ldL[1]}} & L1[13:0] |
{14{(ISEL[1:0] == 2'b10) && !ldL[2]}} & L2[13:0] |
{14{(ISEL[1:0] == 2'b11) && !ldL[3]}} & L3[13:0] |
{14{(ISEL[1:0] == 2'b00) & ldL[0]}} & DMDin[13:0] |
{14{(ISEL[1:0] == 2'b01) & ldL[1]}} & DMDin[13:0] |
{14{(ISEL[1:0] == 2'b10) & ldL[2]}} & DMDin[13:0] |
{14{(ISEL[1:0] == 2'b11) & ldL[3]}} & DMDin[13:0] ;
assign Lout[13:0] = {14{MFLreg_E[0]}} & L0[13:0] |
{14{MFLreg_E[1]}} & L1[13:0] |
{14{MFLreg_E[2]}} & L2[13:0] |
{14{MFLreg_E[3]}} & L3[13:0];
/*----------------------------------------------*/
/*----------------------------------------------*/
wire [13:0] M_D;
wire [13:0] Mout;
wire [1:0] MSEL;
assign MSEL[1:0] = redoM_h ? IRE[1:0]
: SPreqx ? STEALM_R[1:0] : IR[1:0];
assign M_D[13:0] = {14{(MSEL[1:0] == 2'b00) && !ldM[0]}} & M0[13:0] |
{14{(MSEL[1:0] == 2'b01) && !ldM[1]}} & M1[13:0] |
{14{(MSEL[1:0] == 2'b10) && !ldM[2]}} & M2[13:0] |
{14{(MSEL[1:0] == 2'b11) && !ldM[3]}} & M3[13:0] |
{14{(MSEL[1:0] == 2'b00) && ldM[0]}} & DMDin[13:0] |
{14{(MSEL[1:0] == 2'b01) && ldM[1]}} & DMDin[13:0] |
{14{(MSEL[1:0] == 2'b10) && ldM[2]}} & DMDin[13:0] |
{14{(MSEL[1:0] == 2'b11) && ldM[3]}} & DMDin[13:0] ;
assign Mout[13:0] = {14{MFMreg_E[0]}} & M0[13:0] |
{14{MFMreg_E[1]}} & M1[13:0] |
{14{MFMreg_E[2]}} & M2[13:0] |
{14{MFMreg_E[3]}} & M3[13:0] ;
/*----------------------------------------------*/
/*----------------------------------------------*/
wire [15:0] DAG1out;
assign DAG1out[15:14] = {2{Mout[13]}};
assign DAG1out[13:0] = Iout[13:0] |
Lout[13:0] |
Mout[13:0];
assign #2 DMD[15:0] = {16{MFDAG1_E}} & DAG1out[15:0];
/*----------------------------------------------*/
/*----------------------------------------------*/
`ifdef FD_RTL_SIM
wire [13:0] BREVI_R;
wire [13:0] DAG1A_R;
assign BREVI_R[13:0] =
{I_R[0], I_R[1], I_R[2], I_R[3], I_R[4], I_R[5], I_R[6],
I_R[7], I_R[8], I_R[9], I_R[10], I_R[11], I_R[12], I_R[13]};
assign DAG1A_R[13:0] = MSTAT1 ? BREVI_R[13:0] : I_R[13:0];
`else
`endif
/*------------------------------------------------------------------------------*/
/*------------------------------------------------------------------------------*/
/*------------------------------------------------------------------------------*/
wire sel_ISR;
wire sel_DCTL;
wire [13:0] DMA_R;
wire CLKSTACenb, STACen;
wire [13:0] STA_C;
wire [13:0] STACin;
assign STACin[13:0] = accPM_E ? PMA[13:0] : DMA[13:0];
assign CLKSTACenb = !(T0Sreqx || R0Sreqx || T1Sreqx || R1Sreqx || DSreqx || BSreqx);
assign STACen = (GO_E || STEAL || STBY || BOOT || BM_cyc && ECYC) && GO_C &&
(T0Sreqx || R0Sreqx || T1Sreqx || R1Sreqx || DSreqx || BSreqx);
`ifdef FD_DFT
REG14L STAC_pi(DSPCLK, RST, CLKSTACenb, STACen, STACin[13:0], STA_C[13:0], SCAN_TEST);
`else
REG14L STAC_pi(DSPCLK, RST, CLKSTACenb, STACen, STACin[13:0], STA_C[13:0]);
`endif
wire CLKDMAenb;
wire [13:0] DMA;
assign CLKDMAenb = !DMAen_R;
`ifdef FD_DFT
REG14L DMA_pi(DSPCLK, RST, CLKDMAenb, GO_E, DMA_R[13:0], DMA[13:0], SCAN_TEST);
`else
REG14L DMA_pi(DSPCLK, RST, CLKDMAenb, GO_E, DMA_R[13:0], DMA[13:0]);
`endif
`ifdef FD_RTL_SIM
assign #`db DMA_R[13:0] = {14{DAG1D_R}} & DAG1A_R[13:0]
| {14{DAG2D_R}} & DAG2A_R[13:0]
| {14{immAddr_R}} & IR[17:4];
`else
reg dmars2, dmars1, dmars0;
wire [6:0] DMARCOND;
wire [13:0] DMAROT;
assign DMAROT[13:0] = {14{(!ldI_R7_4) & DAG2D_R}} & I_R7_4[13:0]
| {14{immAddr_R}} & IR[17:4];
assign DMARCOND[6:0] = {(Post1_E || Sackx), ldI_R3_0, MSTAT1, (Post2_E || Sackx), ldI_R7_4, DAG1D_R, DAG2D_R};
always @(DMARCOND)
begin
casex (DMARCOND)
7'b011xx10 : {dmars2, dmars1, dmars0} = 3'b000;
7'b010xx10 : {dmars2, dmars1, dmars0} = 3'b001;
7'b111xx10 : {dmars2, dmars1, dmars0} = 3'b010;
7'b110xx10 : {dmars2, dmars1, dmars0} = 3'b011;
7'bx01xx10 : {dmars2, dmars1, dmars0} = 3'b100;
7'bx00xx10 : {dmars2, dmars1, dmars0} = 3'b101;
7'bxxx0101 : {dmars2, dmars1, dmars0} = 3'b001;
7'bxxx1101 : {dmars2, dmars1, dmars0} = 3'b110;
7'bxxxx001 : {dmars2, dmars1, dmars0} = 3'b111;
7'bxxxxx00 : {dmars2, dmars1, dmars0} = 3'b111;
default : {dmars2, dmars1, dmars0} = 3'b111;
endcase
end
GTECH_MUX8 dmar13(.D0(DMDin[0]), .D1(DMDin[13]), .D2(newI1[0]), .D3(newI1[13]),
.D4(I_R3_0[0]), .D5(I_R3_0[13]), .D6(newI2[13]), .D7(DMAROT[13]),
.C(dmars2), .B(dmars1), .A(dmars0), .Z(DMA_R[13]));
GTECH_MUX8 dmar12(.D0(DMDin[1]), .D1(DMDin[12]), .D2(newI1[1]), .D3(newI1[12]),
.D4(I_R3_0[1]), .D5(I_R3_0[12]), .D6(newI2[12]), .D7(DMAROT[12]),
.C(dmars2), .B(dmars1), .A(dmars0), .Z(DMA_R[12]));
GTECH_MUX8 dmar11(.D0(DMDin[2]), .D1(DMDin[11]), .D2(newI1[2]), .D3(newI1[11]),
.D4(I_R3_0[2]), .D5(I_R3_0[11]), .D6(newI2[11]), .D7(DMAROT[11]),
.C(dmars2), .B(dmars1), .A(dmars0), .Z(DMA_R[11]));
GTECH_MUX8 dmar10(.D0(DMDin[3]), .D1(DMDin[10]), .D2(newI1[3]), .D3(newI1[10]),
.D4(I_R3_0[3]), .D5(I_R3_0[10]), .D6(newI2[10]), .D7(DMAROT[10]),
.C(dmars2), .B(dmars1), .A(dmars0), .Z(DMA_R[10]));
GTECH_MUX8 dmar09(.D0(DMDin[4]), .D1(DMDin[9]), .D2(newI1[4]), .D3(newI1[9]),
.D4(I_R3_0[4]), .D5(I_R3_0[9]), .D6(newI2[9]), .D7(DMAROT[9]),
.C(dmars2), .B(dmars1), .A(dmars0), .Z(DMA_R[9]));
GTECH_MUX8 dmar08(.D0(DMDin[5]), .D1(DMDin[8]), .D2(newI1[5]), .D3(newI1[8]),
.D4(I_R3_0[5]), .D5(I_R3_0[8]), .D6(newI2[8]), .D7(DMAROT[8]),
.C(dmars2), .B(dmars1), .A(dmars0), .Z(DMA_R[8]));
GTECH_MUX8 dmar07(.D0(DMDin[6]), .D1(DMDin[7]), .D2(newI1[6]), .D3(newI1[7]),
.D4(I_R3_0[6]), .D5(I_R3_0[7]), .D6(newI2[7]), .D7(DMAROT[7]),
.C(dmars2), .B(dmars1), .A(dmars0), .Z(DMA_R[7]));
GTECH_MUX8 dmar06(.D0(DMDin[7]), .D1(DMDin[6]), .D2(newI1[7]), .D3(newI1[6]),
.D4(I_R3_0[7]), .D5(I_R3_0[6]), .D6(newI2[6]), .D7(DMAROT[6]),
.C(dmars2), .B(dmars1), .A(dmars0), .Z(DMA_R[6]));
GTECH_MUX8 dmar05(.D0(DMDin[8]), .D1(DMDin[5]), .D2(newI1[8]), .D3(newI1[5]),
.D4(I_R3_0[8]), .D5(I_R3_0[5]), .D6(newI2[5]), .D7(DMAROT[5]),
.C(dmars2), .B(dmars1), .A(dmars0), .Z(DMA_R[5]));
GTECH_MUX8 dmar04(.D0(DMDin[9]), .D1(DMDin[4]), .D2(newI1[9]), .D3(newI1[4]),
.D4(I_R3_0[9]), .D5(I_R3_0[4]), .D6(newI2[4]), .D7(DMAROT[4]),
.C(dmars2), .B(dmars1), .A(dmars0), .Z(DMA_R[4]));
GTECH_MUX8 dmar03(.D0(DMDin[10]), .D1(DMDin[3]), .D2(newI1[10]), .D3(newI1[3]),
.D4(I_R3_0[10]), .D5(I_R3_0[3]), .D6(newI2[3]), .D7(DMAROT[3]),
.C(dmars2), .B(dmars1), .A(dmars0), .Z(DMA_R[3]));
GTECH_MUX8 dmar02(.D0(DMDin[11]), .D1(DMDin[2]), .D2(newI1[11]), .D3(newI1[2]),
.D4(I_R3_0[11]), .D5(I_R3_0[2]), .D6(newI2[2]), .D7(DMAROT[2]),
.C(dmars2), .B(dmars1), .A(dmars0), .Z(DMA_R[2]));
GTECH_MUX8 dmar01(.D0(DMDin[12]), .D1(DMDin[1]), .D2(newI1[12]), .D3(newI1[1]),
.D4(I_R3_0[12]), .D5(I_R3_0[1]), .D6(newI2[1]), .D7(DMAROT[1]),
.C(dmars2), .B(dmars1), .A(dmars0), .Z(DMA_R[1]));
GTECH_MUX8 dmar00(.D0(DMDin[13]), .D1(DMDin[0]), .D2(newI1[13]), .D3(newI1[0]),
.D4(I_R3_0[13]), .D5(I_R3_0[0]), .D6(newI2[0]), .D7(DMAROT[0]),
.C(dmars2), .B(dmars1), .A(dmars0), .Z(DMA_R[0]));
`endif
assign sel_ISR = SPreqx && (GO_E || STEAL || STBY);
assign sel_DCTL = DSreqx && DCTL[14] && (GO_E || STEAL || BOOT || STBY);
assign sel_BDMA = BSreqx && BDM_cyc && (GO_E || STEAL || BOOT || STBY || BM_cyc && ECYC);
`ifdef FD_RTL_SIM
assign #`db DMAin = sel_BDMA ? BIAD[13:0] :
{14{sel_ISR}} & IS_R[13:0]
| {14{sel_DCTL}} & DCTL[13:0]
| {14{sel_STAC}} & STA_C[13:0]
| {14{sel_DMAR}} & DMA_R[13:0]
| {14{sel_DMA}} & DMA[13:0] ;
`else
reg dmas2, dmas1, dmas0;
wire [8:0] DMACOND;
wire [13:0] DMAOT;
assign DMAOT[13:0] = sel_BDMA ? BIAD[13:0] :
{14{sel_DCTL}} & DCTL[13:0]
| {14{sel_STAC}} & STA_C[13:0]
| {14{sel_DMA}} & DMA[13:0]
| {14{sel_DMAR && DAG2D_R}} & I7_4[13:0]
| {14{sel_DMAR && DAG1D_R}} & I3_0[13:0]
| {14{sel_DMAR && immAddr_R}} & IR[17:4];
assign DMACOND[8:0] = {(Post1_E || Sackx), ldI3_0, MSTAT1, (Post2_E || Sackx),
ldI7_4, sel_ISR, sel_DMAR, DAG1D_R, DAG2D_R};
always @(DMACOND)
begin
casex (DMACOND)
9'b01xxx1xxx : {dmas2, dmas1, dmas0} = 3'b000;
9'b11xxx1xxx : {dmas2, dmas1, dmas0} = 3'b001;
9'bx0xx01xxx : {dmas2, dmas1, dmas0} = 3'b010;
9'b011xxx11x : {dmas2, dmas1, dmas0} = 3'b011;
9'b010xxx11x : {dmas2, dmas1, dmas0} = 3'b000;
9'b111xxx11x : {dmas2, dmas1, dmas0} = 3'b100;
9'b110xxx11x : {dmas2, dmas1, dmas0} = 3'b001;
9'bx01xxx11x : {dmas2, dmas1, dmas0} = 3'b101;
9'bx00xxx11x : {dmas2, dmas1, dmas0} = 3'b111;
9'bxxx011xxx : {dmas2, dmas1, dmas0} = 3'b000;
9'bxxx111xxx : {dmas2, dmas1, dmas0} = 3'b110;
9'bxxx01x1x1 : {dmas2, dmas1, dmas0} = 3'b000;
9'bxxx11x1x1 : {dmas2, dmas1, dmas0} = 3'b110;
9'bxxxx0x1x1 : {dmas2, dmas1, dmas0} = 3'b111;
9'bxxxxx00xx : {dmas2, dmas1, dmas0} = 3'b111;
9'bxxxxxx100 : {dmas2, dmas1, dmas0} = 3'b111;
default : {dmas2, dmas1, dmas0} = 3'b111;
endcase
end
wire [13:0] ISR;
assign ISR[13:0] = I3_0[13:0] | I7_4[13:0];
GTECH_MUX8 dma13(.D0(DMDin[13]), .D1(newI1[13]), .D2(ISR[13]), .D3(DMDin[0]),
.D4(newI1[0]), .D5(I3_0[0]), .D6(newI2[13]), .D7(DMAOT[13]),
.C(dmas2), .B(dmas1), .A(dmas0), .Z(DMAin[13]));
GTECH_MUX8 dma12(.D0(DMDin[12]), .D1(newI1[12]), .D2(ISR[12]), .D3(DMDin[1]),
.D4(newI1[1]), .D5(I3_0[1]), .D6(newI2[12]), .D7(DMAOT[12]),
.C(dmas2), .B(dmas1), .A(dmas0), .Z(DMAin[12]));
GTECH_MUX8 dma11(.D0(DMDin[11]), .D1(newI1[11]), .D2(ISR[11]), .D3(DMDin[2]),
.D4(newI1[2]), .D5(I3_0[2]), .D6(newI2[11]), .D7(DMAOT[11]),
.C(dmas2), .B(dmas1), .A(dmas0), .Z(DMAin[11]));
GTECH_MUX8 dma10(.D0(DMDin[10]), .D1(newI1[10]), .D2(ISR[10]), .D3(DMDin[3]),
.D4(newI1[3]), .D5(I3_0[3]), .D6(newI2[10]), .D7(DMAOT[10]),
.C(dmas2), .B(dmas1), .A(dmas0), .Z(DMAin[10]));
GTECH_MUX8 dma09(.D0(DMDin[9]), .D1(newI1[9]), .D2(ISR[9]), .D3(DMDin[4]),
.D4(newI1[4]), .D5(I3_0[4]), .D6(newI2[9]), .D7(DMAOT[9]),
.C(dmas2), .B(dmas1), .A(dmas0), .Z(DMAin[9]));
GTECH_MUX8 dma08(.D0(DMDin[8]), .D1(newI1[8]), .D2(ISR[8]), .D3(DMDin[5]),
.D4(newI1[5]), .D5(I3_0[5]), .D6(newI2[8]), .D7(DMAOT[8]),
.C(dmas2), .B(dmas1), .A(dmas0), .Z(DMAin[8]));
GTECH_MUX8 dma07(.D0(DMDin[7]), .D1(newI1[7]), .D2(ISR[7]), .D3(DMDin[6]),
.D4(newI1[6]), .D5(I3_0[6]), .D6(newI2[7]), .D7(DMAOT[7]),
.C(dmas2), .B(dmas1), .A(dmas0), .Z(DMAin[7]));
GTECH_MUX8 dma06(.D0(DMDin[6]), .D1(newI1[6]), .D2(ISR[6]), .D3(DMDin[7]),
.D4(newI1[7]), .D5(I3_0[7]), .D6(newI2[6]), .D7(DMAOT[6]),
.C(dmas2), .B(dmas1), .A(dmas0), .Z(DMAin[6]));
GTECH_MUX8 dma05(.D0(DMDin[5]), .D1(newI1[5]), .D2(ISR[5]), .D3(DMDin[8]),
.D4(newI1[8]), .D5(I3_0[8]), .D6(newI2[5]), .D7(DMAOT[5]),
.C(dmas2), .B(dmas1), .A(dmas0), .Z(DMAin[5]));
GTECH_MUX8 dma04(.D0(DMDin[4]), .D1(newI1[4]), .D2(ISR[4]), .D3(DMDin[9]),
.D4(newI1[9]), .D5(I3_0[9]), .D6(newI2[4]), .D7(DMAOT[4]),
.C(dmas2), .B(dmas1), .A(dmas0), .Z(DMAin[4]));
GTECH_MUX8 dma03(.D0(DMDin[3]), .D1(newI1[3]), .D2(ISR[3]), .D3(DMDin[10]),
.D4(newI1[10]), .D5(I3_0[10]), .D6(newI2[3]), .D7(DMAOT[3]),
.C(dmas2), .B(dmas1), .A(dmas0), .Z(DMAin[3]));
GTECH_MUX8 dma02(.D0(DMDin[2]), .D1(newI1[2]), .D2(ISR[2]), .D3(DMDin[11]),
.D4(newI1[11]), .D5(I3_0[11]), .D6(newI2[2]), .D7(DMAOT[2]),
.C(dmas2), .B(dmas1), .A(dmas0), .Z(DMAin[2]));
GTECH_MUX8 dma01(.D0(DMDin[1]), .D1(newI1[1]), .D2(ISR[1]), .D3(DMDin[12]),
.D4(newI1[12]), .D5(I3_0[12]), .D6(newI2[1]), .D7(DMAOT[1]),
.C(dmas2), .B(dmas1), .A(dmas0), .Z(DMAin[1]));
GTECH_MUX8 dma00(.D0(DMDin[0]), .D1(newI1[0]), .D2(ISR[0]), .D3(DMDin[13]),
.D4(newI1[13]), .D5(I3_0[13]), .D6(newI2[0]), .D7(DMAOT[0]),
.C(dmas2), .B(dmas1), .A(dmas0), .Z(DMAin[0]));
`endif
/*----------------------------------------------*/
/*----------------------------------------------*/
`ifdef FD_LR
wire [13:0] I, L, M;
wire CLKPIenb, CLKPLenb, CLKPMenb;
wire PIen, PLen, PMen;
assign CLKPIenb = !(DAG1_EN || redoM_h || SPreqx);
assign CLKPLenb = !(DAG1_EN || redoM_h || SPreqx);
assign CLKPMenb = !(DAG1_EN || redoM_h || SPreqx);
assign PIen = GO_E || redoM_h || sel_ISR;
assign PLen = GO_E || redoM_h || sel_ISR;
assign PMen = GO_E || redoM_h || sel_ISR;
`ifdef FD_DFT
REG14L pien(DSPCLK, RST, CLKPIenb, PIen, I_D[13:0], I[13:0], SCAN_TEST);
REG14L plen(DSPCLK, RST, CLKPLenb, PLen, L_D[13:0], L[13:0], SCAN_TEST);
REG14L pmen(DSPCLK, RST, CLKPMenb, PMen, M_D[13:0], M[13:0], SCAN_TEST);
`else
REG14L pien(DSPCLK, RST, CLKPIenb, PIen, I_D[13:0], I[13:0]);
REG14L plen(DSPCLK, RST, CLKPLenb, PLen, L_D[13:0], L[13:0]);
REG14L pmen(DSPCLK, RST, CLKPMenb, PMen, M_D[13:0], M[13:0]);
`endif
`else
reg [13:0] I, L, M;
always @(posedge DSPCLK or posedge RST)
if (RST) I[13:0] <= #`db 14'b0;
else if (GO_E & DAG1_EN | redoM_h | sel_ISR) I[13:0] <= #`db I_D[13:0];
always @(posedge DSPCLK or posedge RST)
if (RST) L[13:0] <= #`db 14'b0;
else if (GO_E & DAG1_EN | redoM_h | sel_ISR) L[13:0] <= #`db L_D[13:0];
always @(posedge DSPCLK or posedge RST)
if (RST) M[13:0] <= #`db 14'b0;
else if (GO_E & DAG1_EN | redoM_h | sel_ISR) M[13:0] <= #`db M_D[13:0];
`endif
endmodule
|
`define del 1
`include "../include/x_def.v"
module ILM2REG (/* IN */
DSPCLK, T_RST, GO_E, GO_C, EX_en, DOUBLE_R, IDJUMP_D, Post2_E,
MTIreg_E, MTLreg_E, MTMreg_E,
MFIreg_E, MFLreg_E, MFMreg_E,
newI2, IR, MFDAG2_E,
STEALI_R, STEALM_R, STEALI_E,
STEAL, SPreqx, redoM_h, STBY, sel_STAC, sel_PMA, sel_PMAR,
DSreqx, BOOT, DCTL, STA_C, Sackx, DAG2_EN, DAG2P_R,
BSreqx, BPM_cyc, BIAD, BM_cyc, ECYC,
`ifdef FD_DFT
SCAN_TEST,
`endif
I, L, M, PMA_R,
PMA, PMAin, IS_R2, ldI7_4,
ldI_R7_4, I7_4, I_R7_4,
DMDin, DMD);
/*----------------------------------------------*/
/*----------------------------------------------*/
input [13:0] BIAD;
input BSreqx, BPM_cyc, BM_cyc, ECYC;
input DSPCLK, T_RST, GO_E, GO_C, EX_en, DOUBLE_R;
input IDJUMP_D, Post2_E;
input [7:4] MTIreg_E, MTLreg_E, MTMreg_E;
input [7:4] MFIreg_E, MFLreg_E, MFMreg_E;
input MFDAG2_E;
input [13:0] newI2;
input [7:0] IR;
input [2:0] STEALI_R, STEALI_E;
input [1:0] STEALM_R;
input STEAL, SPreqx, redoM_h;
input STBY, DSreqx, Sackx, BOOT;
input sel_STAC, sel_PMAR, sel_PMA;
input [13:0] STA_C;
input [14:0] DCTL;
input DAG2_EN;
input DAG2P_R;
`ifdef FD_DFT
input SCAN_TEST;
`endif
/*----------------------------------------------*/
/*----------------------------------------------*/
output [13:0] I, L, M;
output [13:0] PMA_R, PMA, PMAin;
output [13:0] IS_R2;
output ldI7_4, ldI_R7_4;
output [13:0] I7_4, I_R7_4;
/*----------------------------------------------*/
/*----------------------------------------------*/
input [13:0] DMDin;
output [15:0] DMD;
`ifdef FD_DFT
reg RST_o;
wire RST;
always @(posedge DSPCLK) RST_o <= #`db T_RST;
assign RST = SCAN_TEST ? T_RST : RST_o;
`else
reg RST;
always @(posedge DSPCLK) RST <= #`db T_RST;
`endif
/*----------------------------------------------*/
/*----------------------------------------------*/
wire [1:0] IL_R;
wire [13:0] Iin;
reg [1:0] IL_E;
assign #`db IL_R[1:0] = (DOUBLE_R | IDJUMP_D) ? IR[7:6] : IR[3:2];
assign Iin[13:0] = (Post2_E | Sackx) ? newI2[13:0] : DMDin[13:0];
always @(posedge DSPCLK)
if (GO_E) IL_E[1:0] <= #`db IL_R[1:0];
/*----------------------------------------------*/
wire [1:0] updateI4, updateI5, updateI6, updateI7;
wire CLKI4enb, CLKI5enb, CLKI6enb, CLKI7enb;
wire [7:4] ldI;
wire [13:0] I4, I5, I6, I7;
assign updateI4[1] = Sackx && (STEALI_E[2:0] == 3'b100);
assign updateI4[0] = !Sackx && Post2_E && (IL_E[1:0] == 2'b00) && EX_en;
assign updateI5[1] = Sackx && (STEALI_E[2:0] == 3'b101);
assign updateI5[0] = !Sackx && Post2_E && (IL_E[1:0] == 2'b01) && EX_en;
assign updateI6[1] = Sackx && (STEALI_E[2:0] == 3'b110);
assign updateI6[0] = !Sackx && Post2_E && (IL_E[1:0] == 2'b10) && EX_en;
assign updateI7[1] = Sackx && (STEALI_E[2:0] == 3'b111);
assign updateI7[0] = !Sackx && Post2_E && (IL_E[1:0] == 2'b11) && EX_en;
assign CLKI4enb = !((MTIreg_E[4] && EX_en) || updateI4[1] || updateI4[0]);
assign CLKI5enb = !((MTIreg_E[5] && EX_en) || updateI5[1] || updateI5[0]);
assign CLKI6enb = !((MTIreg_E[6] && EX_en) || updateI6[1] || updateI6[0]);
assign CLKI7enb = !((MTIreg_E[7] && EX_en) || updateI7[1] || updateI7[0]);
assign ldI[4] = (MTIreg_E[4] && EX_en && GO_C)
|| (updateI4[0] && EX_en && GO_C) || updateI4[1];
assign ldI[5] = (MTIreg_E[5] && EX_en && GO_C)
|| (updateI5[0] && EX_en && GO_C) || updateI5[1];
assign ldI[6] = (MTIreg_E[6] && EX_en && GO_C)
|| (updateI6[0] && EX_en && GO_C) || updateI6[1];
assign ldI[7] = (MTIreg_E[7] && EX_en && GO_C)
|| (updateI7[0] && EX_en && GO_C) || updateI7[1];
`ifdef FD_DFT
REG14L I4_we(DSPCLK, RST, CLKI4enb, ldI[4], Iin[13:0], I4[13:0], SCAN_TEST);
REG14L I5_we(DSPCLK, RST, CLKI5enb, ldI[5], Iin[13:0], I5[13:0], SCAN_TEST);
REG14L I6_we(DSPCLK, RST, CLKI6enb, ldI[6], Iin[13:0], I6[13:0], SCAN_TEST);
REG14L I7_we(DSPCLK, RST, CLKI7enb, ldI[7], Iin[13:0], I7[13:0], SCAN_TEST);
`else
REG14L I4_we(DSPCLK, RST, CLKI4enb, ldI[4], Iin[13:0], I4[13:0]);
REG14L I5_we(DSPCLK, RST, CLKI5enb, ldI[5], Iin[13:0], I5[13:0]);
REG14L I6_we(DSPCLK, RST, CLKI6enb, ldI[6], Iin[13:0], I6[13:0]);
REG14L I7_we(DSPCLK, RST, CLKI7enb, ldI[7], Iin[13:0], I7[13:0]);
`endif
/*----------------------------------------------*/
/*----------------------------------------------*/
wire CLKL4enb, CLKL5enb, CLKL6enb, CLKL7enb;
wire [7:4] ldL;
wire [13:0] L4, L5, L6, L7;
assign CLKL4enb = !(MTLreg_E[4] && EX_en);
assign CLKL5enb = !(MTLreg_E[5] && EX_en);
assign CLKL6enb = !(MTLreg_E[6] && EX_en);
assign CLKL7enb = !(MTLreg_E[7] && EX_en);
assign ldL[4] = MTLreg_E[4] && EX_en && GO_C;
assign ldL[5] = MTLreg_E[5] && EX_en && GO_C;
assign ldL[6] = MTLreg_E[6] && EX_en && GO_C;
assign ldL[7] = MTLreg_E[7] && EX_en && GO_C;
`ifdef FD_DFT
REG14L L4_we(DSPCLK, RST, CLKL4enb, ldL[4], DMDin[13:0], L4[13:0], SCAN_TEST);
REG14L L5_we(DSPCLK, RST, CLKL5enb, ldL[5], DMDin[13:0], L5[13:0], SCAN_TEST);
REG14L L6_we(DSPCLK, RST, CLKL6enb, ldL[6], DMDin[13:0], L6[13:0], SCAN_TEST);
REG14L L7_we(DSPCLK, RST, CLKL7enb, ldL[7], DMDin[13:0], L7[13:0], SCAN_TEST);
`else
REG14L L4_we(DSPCLK, RST, CLKL4enb, ldL[4], DMDin[13:0], L4[13:0]);
REG14L L5_we(DSPCLK, RST, CLKL5enb, ldL[5], DMDin[13:0], L5[13:0]);
REG14L L6_we(DSPCLK, RST, CLKL6enb, ldL[6], DMDin[13:0], L6[13:0]);
REG14L L7_we(DSPCLK, RST, CLKL7enb, ldL[7], DMDin[13:0], L7[13:0]);
`endif
/*----------------------------------------------*/
/*----------------------------------------------*/
wire CLKM4enb, CLKM5enb, CLKM6enb, CLKM7enb;
wire [7:4] ldM;
wire [13:0] M4, M5, M6, M7;
assign CLKM4enb = !(MTMreg_E[4] && EX_en);
assign CLKM5enb = !(MTMreg_E[5] && EX_en);
assign CLKM6enb = !(MTMreg_E[6] && EX_en);
assign CLKM7enb = !(MTMreg_E[7] && EX_en);
assign ldM[4] = MTMreg_E[4] && EX_en && GO_C;
assign ldM[5] = MTMreg_E[5] && EX_en && GO_C;
assign ldM[6] = MTMreg_E[6] && EX_en && GO_C;
assign ldM[7] = MTMreg_E[7] && EX_en && GO_C;
`ifdef FD_DFT
REG14L M4_we(DSPCLK, RST, CLKM4enb, ldM[4], DMDin[13:0], M4[13:0], SCAN_TEST);
REG14L M5_we(DSPCLK, RST, CLKM5enb, ldM[5], DMDin[13:0], M5[13:0], SCAN_TEST);
REG14L M6_we(DSPCLK, RST, CLKM6enb, ldM[6], DMDin[13:0], M6[13:0], SCAN_TEST);
REG14L M7_we(DSPCLK, RST, CLKM7enb, ldM[7], DMDin[13:0], M7[13:0], SCAN_TEST);
`else
REG14L M4_we(DSPCLK, RST, CLKM4enb, ldM[4], DMDin[13:0], M4[13:0]);
REG14L M5_we(DSPCLK, RST, CLKM5enb, ldM[5], DMDin[13:0], M5[13:0]);
REG14L M6_we(DSPCLK, RST, CLKM6enb, ldM[6], DMDin[13:0], M6[13:0]);
REG14L M7_we(DSPCLK, RST, CLKM7enb, ldM[7], DMDin[13:0], M7[13:0]);
`endif
/*----------------------------------------------*/
/*----------------------------------------------*/
wire [13:0] Iout;
wire [13:0] I_R;
wire [13:0] I_D;
wire [1:0] ILSEL;
assign #`db ILSEL[1:0] = redoM_h ? IL_E[1:0]
: SPreqx ? STEALI_R[1:0] : IL_R[1:0];
assign #`db I_D[13:0] = {14{(ILSEL[1:0] == 2'b00) && !ldI[4]}} & I4[13:0] |
{14{(ILSEL[1:0] == 2'b01) && !ldI[5]}} & I5[13:0] |
{14{(ILSEL[1:0] == 2'b10) && !ldI[6]}} & I6[13:0] |
{14{(ILSEL[1:0] == 2'b11) && !ldI[7]}} & I7[13:0] |
{14{(ILSEL[1:0] == 2'b00) && ldI[4]}} & Iin[13:0] |
{14{(ILSEL[1:0] == 2'b01) && ldI[5]}} & Iin[13:0] |
{14{(ILSEL[1:0] == 2'b10) && ldI[6]}} & Iin[13:0] |
{14{(ILSEL[1:0] == 2'b11) && ldI[7]}} & Iin[13:0] ;
`ifdef FD_RTL_SIM
assign #`db I_R[13:0] = {14{(IL_R[1:0] == 2'b00) && !ldI[4]}} & I4[13:0] |
{14{(IL_R[1:0] == 2'b01) && !ldI[5]}} & I5[13:0] |
{14{(IL_R[1:0] == 2'b10) && !ldI[6]}} & I6[13:0] |
{14{(IL_R[1:0] == 2'b11) && !ldI[7]}} & I7[13:0] |
{14{(IL_R[1:0] == 2'b00) && ldI[4]}} & Iin[13:0] |
{14{(IL_R[1:0] == 2'b01) && ldI[5]}} & Iin[13:0] |
{14{(IL_R[1:0] == 2'b10) && ldI[6]}} & Iin[13:0] |
{14{(IL_R[1:0] == 2'b11) && ldI[7]}} & Iin[13:0] ;
assign #`db IS_R2[13:0] = {14{(STEALI_R[2:0] == 3'b100) && !ldI[4]}} & I4[13:0] |
{14{(STEALI_R[2:0] == 3'b101) && !ldI[5]}} & I5[13:0] |
{14{(STEALI_R[2:0] == 3'b110) && !ldI[6]}} & I6[13:0] |
{14{(STEALI_R[2:0] == 3'b111) && !ldI[7]}} & I7[13:0] |
{14{(STEALI_R[2:0] == 3'b100) && ldI[4]}} & Iin[13:0] |
{14{(STEALI_R[2:0] == 3'b101) && ldI[5]}} & Iin[13:0] |
{14{(STEALI_R[2:0] == 3'b110) && ldI[6]}} & Iin[13:0] |
{14{(STEALI_R[2:0] == 3'b111) && ldI[7]}} & Iin[13:0] ;
`else
wire ldI7_4, ldI_R7_4, ldIS_R7_4;
wire [13:0] I7_4, I_R7_4, IS_R7_4;
assign ldI_R7_4 = (IL_R[1:0] == 2'b00) && ldI[4] ||
(IL_R[1:0] == 2'b01) && ldI[5] ||
(IL_R[1:0] == 2'b10) && ldI[6] ||
(IL_R[1:0] == 2'b11) && ldI[7] ;
assign I_R7_4[13:0] = {14{(IL_R[1:0] == 2'b00) && !ldI[4]}} & I4[13:0] |
{14{(IL_R[1:0] == 2'b01) && !ldI[5]}} & I5[13:0] |
{14{(IL_R[1:0] == 2'b10) && !ldI[6]}} & I6[13:0] |
{14{(IL_R[1:0] == 2'b11) && !ldI[7]}} & I7[13:0] ;
assign ldIS_R7_4 = (STEALI_R[2:0] == 3'b100) && ldI[4] ||
(STEALI_R[2:0] == 3'b101) && ldI[5] ||
(STEALI_R[2:0] == 3'b110) && ldI[6] ||
(STEALI_R[2:0] == 3'b111) && ldI[7] ;
assign IS_R7_4[13:0] = {14{(STEALI_R[2:0] == 3'b100) && !ldI[4]}} & I4[13:0] |
{14{(STEALI_R[2:0] == 3'b101) && !ldI[5]}} & I5[13:0] |
{14{(STEALI_R[2:0] == 3'b110) && !ldI[6]}} & I6[13:0] |
{14{(STEALI_R[2:0] == 3'b111) && !ldI[7]}} & I7[13:0] ;
assign ldI7_4 = SPreqx ? ldIS_R7_4 : ldI_R7_4;
assign I7_4[13:0] = SPreqx ? IS_R7_4[13:0] : I_R7_4[13:0];
`endif
assign #`db Iout[13:0] = {14{MFIreg_E[4]}} & I4[13:0] |
{14{MFIreg_E[5]}} & I5[13:0] |
{14{MFIreg_E[6]}} & I6[13:0] |
{14{MFIreg_E[7]}} & I7[13:0] ;
/*----------------------------------------------*/
/*----------------------------------------------*/
wire [13:0] Lout;
wire [13:0] L_D;
assign #`db L_D[13:0] = {14{(ILSEL[1:0] == 2'b00) && !ldL[4]}} & L4[13:0] |
{14{(ILSEL[1:0] == 2'b01) && !ldL[5]}} & L5[13:0] |
{14{(ILSEL[1:0] == 2'b10) && !ldL[6]}} & L6[13:0] |
{14{(ILSEL[1:0] == 2'b11) && !ldL[7]}} & L7[13:0] |
{14{(ILSEL[1:0] == 2'b00) && ldL[4]}} & DMDin[13:0] |
{14{(ILSEL[1:0] == 2'b01) && ldL[5]}} & DMDin[13:0] |
{14{(ILSEL[1:0] == 2'b10) && ldL[6]}} & DMDin[13:0] |
{14{(ILSEL[1:0] == 2'b11) && ldL[7]}} & DMDin[13:0] ;
assign #`db Lout[13:0] = {14{MFLreg_E[4]}} & L4[13:0] |
{14{MFLreg_E[5]}} & L5[13:0] |
{14{MFLreg_E[6]}} & L6[13:0] |
{14{MFLreg_E[7]}} & L7[13:0];
/************************************************/
/************************************************/
wire [1:0] M_R;
wire [13:0] Mout;
wire [13:0] M_D;
wire [1:0] MSEL;
reg [1:0] M_E;
assign #`db M_R[1:0] = DOUBLE_R ? IR[5:4] : IR[1:0];
always @(posedge DSPCLK or posedge RST)
if (RST) M_E[1:0] <= #`db 2'b0;
else if (GO_E) M_E[1:0] <= #`db M_R[1:0];
assign #`db MSEL[1:0] = redoM_h ? M_E[1:0]
: SPreqx ? STEALM_R[1:0] : M_R[1:0];
assign #`db M_D[13:0] = {14{(MSEL[1:0] == 2'b00) && !ldM[4]}} & M4[13:0] |
{14{(MSEL[1:0] == 2'b01) && !ldM[5]}} & M5[13:0] |
{14{(MSEL[1:0] == 2'b10) && !ldM[6]}} & M6[13:0] |
{14{(MSEL[1:0] == 2'b11) && !ldM[7]}} & M7[13:0] |
{14{(MSEL[1:0] == 2'b00) && ldM[4]}} & DMDin[13:0] |
{14{(MSEL[1:0] == 2'b01) && ldM[5]}} & DMDin[13:0] |
{14{(MSEL[1:0] == 2'b10) && ldM[6]}} & DMDin[13:0] |
{14{(MSEL[1:0] == 2'b11) && ldM[7]}} & DMDin[13:0] ;
assign #`db Mout[13:0] = {14{MFMreg_E[4]}} & M4[13:0] |
{14{MFMreg_E[5]}} & M5[13:0] |
{14{MFMreg_E[6]}} & M6[13:0] |
{14{MFMreg_E[7]}} & M7[13:0];
/*----------------------------------------------*/
/*----------------------------------------------*/
wire [15:0] DAG2out;
assign DAG2out[15:14] = {2{Mout[13]}};
assign DAG2out[13:0] = Iout[13:0] |
Lout[13:0] |
Mout[13:0] ;
assign #2 DMD[15:0] = {16{MFDAG2_E}} & DAG2out[15:0];
/*----------------------------------------------*/
wire sel_ISR;
wire sel_DCTL;
wire sel_BDMA;
wire [13:0] PMA_R;
wire [13:0] PMAin;
`ifdef FD_RTL_SIM
assign PMA_R[13:0] = I_R[13:0];
`else
wire pmars1, pmars0;
assign pmars1 = Post2_E || Sackx;
assign pmars0 = ldI_R7_4;
GTECH_MUX4 pmar13(.D0(I_R7_4[13]), .D1(DMDin[13]), .D2(I_R7_4[13]), .D3(newI2[13]),
.B(pmars1), .A(pmars0), .Z(PMA_R[13]));
GTECH_MUX4 pmar12(.D0(I_R7_4[12]), .D1(DMDin[12]), .D2(I_R7_4[12]), .D3(newI2[12]),
.B(pmars1), .A(pmars0), .Z(PMA_R[12]));
GTECH_MUX4 pmar11(.D0(I_R7_4[11]), .D1(DMDin[11]), .D2(I_R7_4[11]), .D3(newI2[11]),
.B(pmars1), .A(pmars0), .Z(PMA_R[11]));
GTECH_MUX4 pmar10(.D0(I_R7_4[10]), .D1(DMDin[10]), .D2(I_R7_4[10]), .D3(newI2[10]),
.B(pmars1), .A(pmars0), .Z(PMA_R[10]));
GTECH_MUX4 pmar09(.D0(I_R7_4[9]), .D1(DMDin[9]), .D2(I_R7_4[9]), .D3(newI2[9]),
.B(pmars1), .A(pmars0), .Z(PMA_R[9]));
GTECH_MUX4 pmar08(.D0(I_R7_4[8]), .D1(DMDin[8]), .D2(I_R7_4[8]), .D3(newI2[8]),
.B(pmars1), .A(pmars0), .Z(PMA_R[8]));
GTECH_MUX4 pmar07(.D0(I_R7_4[7]), .D1(DMDin[7]), .D2(I_R7_4[7]), .D3(newI2[7]),
.B(pmars1), .A(pmars0), .Z(PMA_R[7]));
GTECH_MUX4 pmar06(.D0(I_R7_4[6]), .D1(DMDin[6]), .D2(I_R7_4[6]), .D3(newI2[6]),
.B(pmars1), .A(pmars0), .Z(PMA_R[6]));
GTECH_MUX4 pmar05(.D0(I_R7_4[5]), .D1(DMDin[5]), .D2(I_R7_4[5]), .D3(newI2[5]),
.B(pmars1), .A(pmars0), .Z(PMA_R[5]));
GTECH_MUX4 pmar04(.D0(I_R7_4[4]), .D1(DMDin[4]), .D2(I_R7_4[4]), .D3(newI2[4]),
.B(pmars1), .A(pmars0), .Z(PMA_R[4]));
GTECH_MUX4 pmar03(.D0(I_R7_4[3]), .D1(DMDin[3]), .D2(I_R7_4[3]), .D3(newI2[3]),
.B(pmars1), .A(pmars0), .Z(PMA_R[3]));
GTECH_MUX4 pmar02(.D0(I_R7_4[2]), .D1(DMDin[2]), .D2(I_R7_4[2]), .D3(newI2[2]),
.B(pmars1), .A(pmars0), .Z(PMA_R[2]));
GTECH_MUX4 pmar01(.D0(I_R7_4[1]), .D1(DMDin[1]), .D2(I_R7_4[1]), .D3(newI2[1]),
.B(pmars1), .A(pmars0), .Z(PMA_R[1]));
GTECH_MUX4 pmar00(.D0(I_R7_4[0]), .D1(DMDin[0]), .D2(I_R7_4[0]), .D3(newI2[0]),
.B(pmars1), .A(pmars0), .Z(PMA_R[0]));
`endif
wire CLKPMAenb;
wire [13:0] PMA;
assign CLKPMAenb = !DAG2P_R;
`ifdef FD_DFT
REG14L PMA_pi(DSPCLK, RST, CLKPMAenb, GO_E, PMA_R[13:0], PMA[13:0], SCAN_TEST);
`else
REG14L PMA_pi(DSPCLK, RST, CLKPMAenb, GO_E, PMA_R[13:0], PMA[13:0]);
`endif
assign sel_ISR = SPreqx && (GO_E || STEAL || STBY);
assign sel_DCTL = DSreqx && !DCTL[14] && (GO_E || STEAL || STBY || BOOT);
assign sel_BDMA = BSreqx && BPM_cyc && (GO_E || STEAL || STBY || BOOT || BM_cyc && ECYC);
`ifdef FD_RTL_SIM
assign PMAin[13:0] = sel_BDMA ? BIAD[13:0] :
{14{sel_ISR}} & IS_R2[13:0]
| {14{sel_DCTL}} & DCTL[13:0]
| {14{sel_STAC}} & STA_C[13:0]
| {14{sel_PMAR}} & PMA_R[13:0]
| {14{sel_PMA}} & PMA[13:0];
`else
wire [13:0] PMAOT;
wire [4:0] PMACOND;
wire [13:0] PMAin_mux1;
reg pmas2, pmas1, pmas0;
assign PMAOT[13:0] = sel_BDMA ? BIAD[13:0] :
{14{sel_DCTL}} & DCTL[13:0]
| {14{sel_STAC}} & STA_C[13:0]
| {14{sel_PMA}} & PMA[13:0];
assign PMACOND[4:0] = {(Post2_E || Sackx), ldI_R7_4, ldIS_R7_4, sel_PMAR, sel_ISR};
always @(PMACOND)
begin
casex (PMACOND)
5'b01x1x : {pmas2, pmas1, pmas0} = 3'b1xx;
5'b11x1x : {pmas2, pmas1, pmas0} = 3'b000;
5'bx0x1x : {pmas2, pmas1, pmas0} = 3'b001;
5'b1x1x1 : {pmas2, pmas1, pmas0} = 3'b000;
5'b0x1x1 : {pmas2, pmas1, pmas0} = 3'b1xx;
5'bxx0x1 : {pmas2, pmas1, pmas0} = 3'b010;
5'bxxx00 : {pmas2, pmas1, pmas0} = 3'b011;
endcase
end
GTECH_MUX4 pma1_13(.D0(newI2[13]), .D1(I_R7_4[13]), .D2(IS_R7_4[13]), .D3(PMAOT[13]),
.B(pmas1), .A(pmas0), .Z(PMAin_mux1[13]));
GTECH_MUX4 pma1_12(.D0(newI2[12]), .D1(I_R7_4[12]), .D2(IS_R7_4[12]), .D3(PMAOT[12]),
.B(pmas1), .A(pmas0), .Z(PMAin_mux1[12]));
GTECH_MUX4 pma1_11(.D0(newI2[11]), .D1(I_R7_4[11]), .D2(IS_R7_4[11]), .D3(PMAOT[11]),
.B(pmas1), .A(pmas0), .Z(PMAin_mux1[11]));
GTECH_MUX4 pma1_10(.D0(newI2[10]), .D1(I_R7_4[10]), .D2(IS_R7_4[10]), .D3(PMAOT[10]),
.B(pmas1), .A(pmas0), .Z(PMAin_mux1[10]));
GTECH_MUX4 pma1_09(.D0(newI2[9]), .D1(I_R7_4[9]), .D2(IS_R7_4[9]), .D3(PMAOT[9]),
.B(pmas1), .A(pmas0), .Z(PMAin_mux1[9]));
GTECH_MUX4 pma1_08(.D0(newI2[8]), .D1(I_R7_4[8]), .D2(IS_R7_4[8]), .D3(PMAOT[8]),
.B(pmas1), .A(pmas0), .Z(PMAin_mux1[8]));
GTECH_MUX4 pma1_07(.D0(newI2[7]), .D1(I_R7_4[7]), .D2(IS_R7_4[7]), .D3(PMAOT[7]),
.B(pmas1), .A(pmas0), .Z(PMAin_mux1[7]));
GTECH_MUX4 pma1_06(.D0(newI2[6]), .D1(I_R7_4[6]), .D2(IS_R7_4[6]), .D3(PMAOT[6]),
.B(pmas1), .A(pmas0), .Z(PMAin_mux1[6]));
GTECH_MUX4 pma1_05(.D0(newI2[5]), .D1(I_R7_4[5]), .D2(IS_R7_4[5]), .D3(PMAOT[5]),
.B(pmas1), .A(pmas0), .Z(PMAin_mux1[5]));
GTECH_MUX4 pma1_04(.D0(newI2[4]), .D1(I_R7_4[4]), .D2(IS_R7_4[4]), .D3(PMAOT[4]),
.B(pmas1), .A(pmas0), .Z(PMAin_mux1[4]));
GTECH_MUX4 pma1_03(.D0(newI2[3]), .D1(I_R7_4[3]), .D2(IS_R7_4[3]), .D3(PMAOT[3]),
.B(pmas1), .A(pmas0), .Z(PMAin_mux1[3]));
GTECH_MUX4 pma1_02(.D0(newI2[2]), .D1(I_R7_4[2]), .D2(IS_R7_4[2]), .D3(PMAOT[2]),
.B(pmas1), .A(pmas0), .Z(PMAin_mux1[2]));
GTECH_MUX4 pma1_01(.D0(newI2[1]), .D1(I_R7_4[1]), .D2(IS_R7_4[1]), .D3(PMAOT[1]),
.B(pmas1), .A(pmas0), .Z(PMAin_mux1[1]));
GTECH_MUX4 pma1_00(.D0(newI2[0]), .D1(I_R7_4[0]), .D2(IS_R7_4[0]), .D3(PMAOT[0]),
.B(pmas1), .A(pmas0), .Z(PMAin_mux1[0]));
GTECH_MUX2 pma13(.A(PMAin_mux1[13]), .B(DMDin[13]),
.S(pmas2), .Z(PMAin[13]));
GTECH_MUX2 pma12(.A(PMAin_mux1[12]), .B(DMDin[12]),
.S(pmas2), .Z(PMAin[12]));
GTECH_MUX2 pma11(.A(PMAin_mux1[11]), .B(DMDin[11]),
.S(pmas2), .Z(PMAin[11]));
GTECH_MUX2 pma10(.A(PMAin_mux1[10]), .B(DMDin[10]),
.S(pmas2), .Z(PMAin[10]));
GTECH_MUX2 pma09(.A(PMAin_mux1[9]), .B(DMDin[9]),
.S(pmas2), .Z(PMAin[9]));
GTECH_MUX2 pma08(.A(PMAin_mux1[8]), .B(DMDin[8]),
.S(pmas2), .Z(PMAin[8]));
GTECH_MUX2 pma07(.A(PMAin_mux1[7]), .B(DMDin[7]),
.S(pmas2), .Z(PMAin[7]));
GTECH_MUX2 pma06(.A(PMAin_mux1[6]), .B(DMDin[6]),
.S(pmas2), .Z(PMAin[6]));
GTECH_MUX2 pma05(.A(PMAin_mux1[5]), .B(DMDin[5]),
.S(pmas2), .Z(PMAin[5]));
GTECH_MUX2 pma04(.A(PMAin_mux1[4]), .B(DMDin[4]),
.S(pmas2), .Z(PMAin[4]));
GTECH_MUX2 pma03(.A(PMAin_mux1[3]), .B(DMDin[3]),
.S(pmas2), .Z(PMAin[3]));
GTECH_MUX2 pma02(.A(PMAin_mux1[2]), .B(DMDin[2]),
.S(pmas2), .Z(PMAin[2]));
GTECH_MUX2 pma01(.A(PMAin_mux1[1]), .B(DMDin[1]),
.S(pmas2), .Z(PMAin[1]));
GTECH_MUX2 pma00(.A(PMAin_mux1[0]), .B(DMDin[0]),
.S(pmas2), .Z(PMAin[0]));
`endif
/*----------------------------------------------*/
/*----------------------------------------------*/
`ifdef FD_LR
wire [13:0] I, L, M;
wire CLKPIenb, CLKPLenb, CLKPMenb;
wire PIen, PLen, PMen;
assign CLKPIenb = !(DAG2_EN || redoM_h || SPreqx);
assign CLKPLenb = !(DAG2_EN || redoM_h || SPreqx);
assign CLKPMenb = !(DAG2_EN || redoM_h || SPreqx);
assign PIen = GO_E || redoM_h || sel_ISR;
assign PLen = GO_E || redoM_h || sel_ISR;
assign PMen = GO_E || redoM_h || sel_ISR;
`ifdef FD_DFT
REG14L pien(DSPCLK, RST, CLKPIenb, PIen, I_D[13:0], I[13:0], SCAN_TEST);
REG14L plen(DSPCLK, RST, CLKPLenb, PLen, L_D[13:0], L[13:0], SCAN_TEST);
REG14L pmen(DSPCLK, RST, CLKPMenb, PMen, M_D[13:0], M[13:0], SCAN_TEST);
`else
REG14L pien(DSPCLK, RST, CLKPIenb, PIen, I_D[13:0], I[13:0]);
REG14L plen(DSPCLK, RST, CLKPLenb, PLen, L_D[13:0], L[13:0]);
REG14L pmen(DSPCLK, RST, CLKPMenb, PMen, M_D[13:0], M[13:0]);
`endif
`else
reg [13:0] I, L, M;
always @(posedge DSPCLK or posedge RST)
if (RST) I[13:0] <= #`db 14'b0;
else if (GO_E & DAG2_EN | redoM_h | sel_ISR) I[13:0] <= #`db I_D[13:0];
always @(posedge DSPCLK or posedge RST)
if (RST) L[13:0] <= #`db 14'b0;
else if (GO_E & DAG2_EN | redoM_h | sel_ISR) L[13:0] <= #`db L_D[13:0];
always @(posedge DSPCLK or posedge RST)
if (RST) M[13:0] <= #`db 14'b0;
else if (GO_E & DAG2_EN | redoM_h | sel_ISR) M[13:0] <= #`db M_D[13:0];
`endif
endmodule
|
`define del 1
`include "../include/x_def.v"
module DLPN (/* IN */ L,
/* OUT */ PB, Pa);
input [13:0] L;
output [13:0] PB, Pa;
reg [13:0] Lp, Ln;
reg Sb;
always @( L )
begin
casex( L )
14'b1????????????? : Lp[13:0] = 14'b11111111111111;
14'b01???????????? : Lp[13:0] = 14'b01111111111111;
14'b001??????????? : Lp[13:0] = 14'b00111111111111;
14'b0001?????????? : Lp[13:0] = 14'b00011111111111;
14'b00001????????? : Lp[13:0] = 14'b00001111111111;
14'b000001???????? : Lp[13:0] = 14'b00000111111111;
14'b0000001??????? : Lp[13:0] = 14'b00000011111111;
14'b00000001?????? : Lp[13:0] = 14'b00000001111111;
14'b000000001????? : Lp[13:0] = 14'b00000000111111;
14'b0000000001???? : Lp[13:0] = 14'b00000000011111;
14'b00000000001??? : Lp[13:0] = 14'b00000000001111;
14'b000000000001?? : Lp[13:0] = 14'b00000000000111;
14'b0000000000001? : Lp[13:0] = 14'b00000000000011;
14'b00000000000001 : Lp[13:0] = 14'b00000000000001;
14'b00000000000000 : Lp[13:0] = 14'b00000000000000;
endcase
end
always @( L )
begin
casex( L )
14'b?????????????1 : Ln[13:0] = 14'b11111111111111;
14'b????????????10 : Ln[13:0] = 14'b11111111111110;
14'b???????????100 : Ln[13:0] = 14'b11111111111100;
14'b??????????1000 : Ln[13:0] = 14'b11111111111000;
14'b?????????10000 : Ln[13:0] = 14'b11111111110000;
14'b????????100000 : Ln[13:0] = 14'b11111111100000;
14'b???????1000000 : Ln[13:0] = 14'b11111111000000;
14'b??????10000000 : Ln[13:0] = 14'b11111110000000;
14'b?????100000000 : Ln[13:0] = 14'b11111100000000;
14'b????1000000000 : Ln[13:0] = 14'b11111000000000;
14'b???10000000000 : Ln[13:0] = 14'b11110000000000;
14'b??100000000000 : Ln[13:0] = 14'b11100000000000;
14'b?1000000000000 : Ln[13:0] = 14'b11000000000000;
14'b10000000000000 : Ln[13:0] = 14'b10000000000000;
14'b00000000000000 : Ln[13:0] = 14'b00000000000000;
endcase
end
always @( L )
begin
case( L )
14'b00000000000000 : Sb = 0;
14'b00000000000001 : Sb = 0;
14'b00000000000010 : Sb = 0;
14'b00000000000100 : Sb = 0;
14'b00000000001000 : Sb = 0;
14'b00000000010000 : Sb = 0;
14'b00000000100000 : Sb = 0;
14'b00000001000000 : Sb = 0;
14'b00000010000000 : Sb = 0;
14'b00000100000000 : Sb = 0;
14'b00001000000000 : Sb = 0;
14'b00010000000000 : Sb = 0;
14'b00100000000000 : Sb = 0;
14'b01000000000000 : Sb = 0;
14'b10000000000000 : Sb = 0;
default : Sb = 1;
endcase
end
//
//
assign #`da PB[13:0] = Sb ? ~Lp[13:0] : Ln[13:0];
assign #`da Pa[13:0] = Sb ? Lp[13:0] : ~Ln[13:0];
endmodule
|
`define del 1
`include "../include/x_def.v"
module MODULO1 (/* OUT */ newI, T0wrap, T1wrap, R0wrap, R1wrap,
T0sack, T1sack, R0sack, R1sack, STEAL_IE2, wrap2,
DSPCLK, I, M, L);
/********************************/
/********************************/
input [13:0] I;
input [13:0] M;
input [13:0] L;
input T0sack;
input T1sack;
input R0sack;
input R1sack;
input STEAL_IE2;
input wrap2;
input DSPCLK;
/********************************/
/********************************/
output [13:0] newI;
output T0wrap;
output T1wrap;
output R0wrap;
output R1wrap;
wire [13:0] PB, Pa;
reg [13:0] Lp, Ln;
reg Sb;
always @( L )
begin
casex( L )
14'b1????????????? : Lp[13:0] = 14'b11111111111111;
14'b01???????????? : Lp[13:0] = 14'b01111111111111;
14'b001??????????? : Lp[13:0] = 14'b00111111111111;
14'b0001?????????? : Lp[13:0] = 14'b00011111111111;
14'b00001????????? : Lp[13:0] = 14'b00001111111111;
14'b000001???????? : Lp[13:0] = 14'b00000111111111;
14'b0000001??????? : Lp[13:0] = 14'b00000011111111;
14'b00000001?????? : Lp[13:0] = 14'b00000001111111;
14'b000000001????? : Lp[13:0] = 14'b00000000111111;
14'b0000000001???? : Lp[13:0] = 14'b00000000011111;
14'b00000000001??? : Lp[13:0] = 14'b00000000001111;
14'b000000000001?? : Lp[13:0] = 14'b00000000000111;
14'b0000000000001? : Lp[13:0] = 14'b00000000000011;
14'b00000000000001 : Lp[13:0] = 14'b00000000000001;
14'b00000000000000 : Lp[13:0] = 14'b00000000000000;
default : Lp[13:0] = 14'b00000000000000;
endcase
end
always @( L )
begin
casex( L )
14'b?????????????1 : Ln[13:0] = 14'b11111111111111;
14'b????????????10 : Ln[13:0] = 14'b11111111111110;
14'b???????????100 : Ln[13:0] = 14'b11111111111100;
14'b??????????1000 : Ln[13:0] = 14'b11111111111000;
14'b?????????10000 : Ln[13:0] = 14'b11111111110000;
14'b????????100000 : Ln[13:0] = 14'b11111111100000;
14'b???????1000000 : Ln[13:0] = 14'b11111111000000;
14'b??????10000000 : Ln[13:0] = 14'b11111110000000;
14'b?????100000000 : Ln[13:0] = 14'b11111100000000;
14'b????1000000000 : Ln[13:0] = 14'b11111000000000;
14'b???10000000000 : Ln[13:0] = 14'b11110000000000;
14'b??100000000000 : Ln[13:0] = 14'b11100000000000;
14'b?1000000000000 : Ln[13:0] = 14'b11000000000000;
14'b10000000000000 : Ln[13:0] = 14'b10000000000000;
14'b00000000000000 : Ln[13:0] = 14'b00000000000000;
default : Ln[13:0] = 14'b00000000000000;
endcase
end
always @( L )
begin
case( L )
14'b00000000000000 : Sb = 0;
14'b00000000000001 : Sb = 0;
14'b00000000000010 : Sb = 0;
14'b00000000000100 : Sb = 0;
14'b00000000001000 : Sb = 0;
14'b00000000010000 : Sb = 0;
14'b00000000100000 : Sb = 0;
14'b00000001000000 : Sb = 0;
14'b00000010000000 : Sb = 0;
14'b00000100000000 : Sb = 0;
14'b00001000000000 : Sb = 0;
14'b00010000000000 : Sb = 0;
14'b00100000000000 : Sb = 0;
14'b01000000000000 : Sb = 0;
14'b10000000000000 : Sb = 0;
default : Sb = 1;
endcase
end
assign #`da PB[13:0] = Sb ? ~Lp[13:0] : Ln[13:0];
assign #`da Pa[13:0] = Sb ? Lp[13:0] : ~Ln[13:0];
/****************************************/
/****************************************/
wire [13:0] B, a;
assign B[13:0] = I[13:0] & PB[13:0];
assign a[13:0] = I[13:0] & Pa[13:0];
/******************************************/
/******************************************/
wire [14:0] Lx, Mx, ax;
assign Lx[14:0] = M[13] ? {1'b0, L[13:0]} : {1'b1, ~L[13:0]};
assign Mx[14:0] = {M[13], M[13:0]};
assign ax[14:0] = {1'b0, a[13:0]};
wire [15:1] P_a, G_a, PS_a;
wire GS_a;
wire Cin_a = 1'b0;
assign P_a[15:1] = ax[14:0] | Mx[14:0];
assign G_a[15:1] = ax[14:0] & Mx[14:0];
assign PS_a[15:1] = ax[14:0] ^ Mx[14:0];
assign GS_a = Cin_a ? (G_a[1] | P_a[1]) : G_a[1];
/****************************************/
/****************************************/
wire [7:1] G1_a;
assign G1_a[1] = G_a[2] | (P_a[2] & GS_a );
assign G1_a[2] = G_a[4] | (P_a[4] & G_a[3] );
assign G1_a[3] = G_a[6] | (P_a[6] & G_a[5] );
assign G1_a[4] = G_a[8] | (P_a[8] & G_a[7] );
assign G1_a[5] = G_a[10] | (P_a[10] & G_a[9] );
assign G1_a[6] = G_a[12] | (P_a[12] & G_a[11]);
assign G1_a[7] = G_a[14] | (P_a[14] & G_a[13]);
/****************************************/
/****************************************/
wire [7:1] P1_a;
assign P1_a[1] = P_a[2] & P_a[1];
assign P1_a[2] = P_a[4] & P_a[3];
assign P1_a[3] = P_a[6] & P_a[5];
assign P1_a[4] = P_a[8] & P_a[7];
assign P1_a[5] = P_a[10] & P_a[9];
assign P1_a[6] = P_a[12] & P_a[11];
assign P1_a[7] = P_a[14] & P_a[13];
/****************************************/
/****************************************/
wire [4:1] G2_a;
assign G2_a[1] = G1_a[2] | (P1_a[2] & G1_a[1]);
assign G2_a[2] = G1_a[4] | (P1_a[4] & G1_a[3]);
assign G2_a[3] = G1_a[6] | (P1_a[6] & G1_a[5]);
assign G2_a[4] = G_a[15] | (P_a[15] & G1_a[7]);
/****************************************/
/****************************************/
wire [4:1] P2_a;
assign P2_a[1] = P1_a[2] & P1_a[1];
assign P2_a[2] = P1_a[4] & P1_a[3];
assign P2_a[3] = P1_a[6] & P1_a[5];
assign P2_a[4] = P_a[15] & P1_a[7];
/****************************************/
/****************************************/
wire [2:1] G3_a;
assign G3_a[1] = G2_a[2] | (P2_a[2] & G2_a[1]);
assign G3_a[2] = G2_a[4] | (P2_a[4] & G2_a[3]);
/****************************************/
/****************************************/
wire [2:1] P3_a;
assign P3_a[1] = P2_a[2] & P2_a[1];
assign P3_a[2] = P2_a[4] & P2_a[3];
/****************************************/
/****************************************/
wire C14_a, C13_a, C12_a, C11_a, C10_a;
wire C9_a, C8_a, C7_a, C6_a, C5_a;
wire C4_a, C3_a, C2_a, C1_a;
wire T1_a, T2_a, T3_a, T4_a, T5_a;
assign #`db C1_a = GS_a;
assign #`db C2_a = G1_a[1];
assign #`db C3_a = G_a[3] | (G1_a[1] & P_a[3]);
assign #`db C4_a = G2_a[1];
assign #`db C5_a = G_a[5] | (G2_a[1] & P_a[5] );
assign #`db C6_a = G1_a[3] | (G2_a[1] & P1_a[3]);
assign #`db C7_a = G_a[7] | ( C6_a & P_a[7] );
assign #`db C8_a = G3_a[1];
assign #`db C9_a = G_a[9] | (G3_a[1] & P_a[9] );
assign #`db C10_a = G1_a[5] | (G3_a[1] & P1_a[5]);
assign #`db T1_a = G_a[11] | (G1_a[5] & P_a[11]);
assign #`db C11_a = T1_a | (G3_a[1] & P_a[11] & P1_a[5]);
assign #`db C12_a = G2_a[3] | (G3_a[1] & P2_a[3]);
assign #`db T2_a = G_a[13] | (G2_a[3] & P_a[13]);
assign #`db C13_a = T2_a | (G3_a[1] & P2_a[3] & P_a[13]);
assign #`db T3_a = G1_a[7] | (G2_a[3] & P1_a[7]);
assign #`db C14_a = T3_a | (G3_a[1] & P2_a[3] & P1_a[7]);
/********************************/
/********************************/
wire [14:0] aM;
assign #`db aM[0] = Cin_a ^ PS_a[1] ;
assign #`db aM[1] = C1_a ^ PS_a[2] ;
assign #`db aM[2] = C2_a ^ PS_a[3] ;
assign #`db aM[3] = C3_a ^ PS_a[4] ;
assign #`db aM[4] = C4_a ^ PS_a[5] ;
assign #`db aM[5] = C5_a ^ PS_a[6] ;
assign #`db aM[6] = C6_a ^ PS_a[7] ;
assign #`db aM[7] = C7_a ^ PS_a[8] ;
assign #`db aM[8] = C8_a ^ PS_a[9] ;
assign #`db aM[9] = C9_a ^ PS_a[10];
assign #`db aM[10] = C10_a ^ PS_a[11];
assign #`db aM[11] = C11_a ^ PS_a[12];
assign #`db aM[12] = C12_a ^ PS_a[13];
assign #`db aM[13] = C13_a ^ PS_a[14];
assign #`db aM[14] = C14_a ^ PS_a[15];
wire [14:0] aML, SO, CO;
CSA_d b0( ax[0], Mx[0], Lx[0], SO[0], CO[0] );
CSA_d b1( ax[1], Mx[1], Lx[1], SO[1], CO[1] );
CSA_d b2( ax[2], Mx[2], Lx[2], SO[2], CO[2] );
CSA_d b3( ax[3], Mx[3], Lx[3], SO[3], CO[3] );
CSA_d b4( ax[4], Mx[4], Lx[4], SO[4], CO[4] );
CSA_d b5( ax[5], Mx[5], Lx[5], SO[5], CO[5] );
CSA_d b6( ax[6], Mx[6], Lx[6], SO[6], CO[6] );
CSA_d b7( ax[7], Mx[7], Lx[7], SO[7], CO[7] );
CSA_d b8( ax[8], Mx[8], Lx[8], SO[8], CO[8] );
CSA_d b9( ax[9], Mx[9], Lx[9], SO[9], CO[9] );
CSA_d b10(ax[10], Mx[10], Lx[10], SO[10], CO[10] );
CSA_d b11(ax[11], Mx[11], Lx[11], SO[11], CO[11] );
CSA_d b12(ax[12], Mx[12], Lx[12], SO[12], CO[12] );
CSA_d b13(ax[13], Mx[13], Lx[13], SO[13], CO[13] );
CSA_d b14(ax[14], Mx[14], Lx[14], SO[14], CO[14] );
wire [14:0] CO_e = {CO[13:0], 1'b0};
wire Cin_b = ~M[13];
wire [15:1] P_b, G_b, PS_b;
wire GS_b;
assign P_b[15:1] = SO[14:0] | CO_e[14:0];
assign G_b[15:1] = SO[14:0] & CO_e[14:0];
assign PS_b[15:1] = SO[14:0] ^ CO_e[14:0];
assign GS_b = Cin_b ? (G_b[1] | P_b[1]) : G_b[1];
/****************************************/
/****************************************/
wire [7:1] G1_b;
assign G1_b[1] = G_b[2] | (P_b[2] & GS_b );
assign G1_b[2] = G_b[4] | (P_b[4] & G_b[3] );
assign G1_b[3] = G_b[6] | (P_b[6] & G_b[5] );
assign G1_b[4] = G_b[8] | (P_b[8] & G_b[7] );
assign G1_b[5] = G_b[10] | (P_b[10] & G_b[9] );
assign G1_b[6] = G_b[12] | (P_b[12] & G_b[11]);
assign G1_b[7] = G_b[14] | (P_b[14] & G_b[13]);
/****************************************/
/****************************************/
wire [7:1] P1_b;
assign P1_b[1] = P_b[2] & P_b[1];
assign P1_b[2] = P_b[4] & P_b[3];
assign P1_b[3] = P_b[6] & P_b[5];
assign P1_b[4] = P_b[8] & P_b[7];
assign P1_b[5] = P_b[10] & P_b[9];
assign P1_b[6] = P_b[12] & P_b[11];
assign P1_b[7] = P_b[14] & P_b[13];
/****************************************/
/****************************************/
wire [4:1] G2_b;
assign G2_b[1] = G1_b[2] | (P1_b[2] & G1_b[1]);
assign G2_b[2] = G1_b[4] | (P1_b[4] & G1_b[3]);
assign G2_b[3] = G1_b[6] | (P1_b[6] & G1_b[5]);
assign G2_b[4] = G_b[15] | (P_b[15] & G1_b[7]);
/****************************************/
/****************************************/
wire [4:1] P2_b;
assign P2_b[1] = P1_b[2] & P1_b[1];
assign P2_b[2] = P1_b[4] & P1_b[3];
assign P2_b[3] = P1_b[6] & P1_b[5];
assign P2_b[4] = P_b[15] & P1_b[7];
/****************************************/
/****************************************/
wire [2:1] G3_b;
assign G3_b[1] = G2_b[2] | (P2_b[2] & G2_b[1]);
assign G3_b[2] = G2_b[4] | (P2_b[4] & G2_b[3]);
/****************************************/
/****************************************/
wire [2:1] P3_b;
assign P3_b[1] = P2_b[2] & P2_b[1];
assign P3_b[2] = P2_b[4] & P2_b[3];
/****************************************/
/****************************************/
wire C14_b, C13_b, C12_b, C11_b, C10_b;
wire C9_b, C8_b, C7_b, C6_b, C5_b;
wire C4_b, C3_b, C2_b, C1_b;
wire T1_b, T2_b, T3_b, T4_b, T5_b;
assign #`db C1_b = GS_b;
assign #`db C2_b = G1_b[1];
assign #`db C3_b = G_b[3] | (G1_b[1] & P_b[3]);
assign #`db C4_b = G2_b[1];
assign #`db C5_b = G_b[5] | (G2_b[1] & P_b[5] );
assign #`db C6_b = G1_b[3] | (G2_b[1] & P1_b[3]);
assign #`db C7_b = G_b[7] | ( C6_b & P_b[7] );
assign #`db C8_b = G3_b[1];
assign #`db C9_b = G_b[9] | (G3_b[1] & P_b[9] );
assign #`db C10_b = G1_b[5] | (G3_b[1] & P1_b[5]);
assign #`db T1_b = G_b[11] | (G1_b[5] & P_b[11]);
assign #`db C11_b = T1_b | (G3_b[1] & P_b[11] & P1_b[5]);
assign #`db C12_b = G2_b[3] | (G3_b[1] & P2_b[3]);
assign #`db T2_b = G_b[13] | (G2_b[3] & P_b[13]);
assign #`db C13_b = T2_b | (G3_b[1] & P2_b[3] & P_b[13]);
assign #`db T3_b = G1_b[7] | (G2_b[3] & P1_b[7]);
assign #`db C14_b = T3_b | (G3_b[1] & P2_b[3] & P1_b[7]);
/********************************/
/********************************/
assign #`db aML[0] = Cin_b ^ PS_b[1] ;
assign #`db aML[1] = C1_b ^ PS_b[2] ;
assign #`db aML[2] = C2_b ^ PS_b[3] ;
assign #`db aML[3] = C3_b ^ PS_b[4] ;
assign #`db aML[4] = C4_b ^ PS_b[5] ;
assign #`db aML[5] = C5_b ^ PS_b[6] ;
assign #`db aML[6] = C6_b ^ PS_b[7] ;
assign #`db aML[7] = C7_b ^ PS_b[8] ;
assign #`db aML[8] = C8_b ^ PS_b[9] ;
assign #`db aML[9] = C9_b ^ PS_b[10];
assign #`db aML[10] = C10_b ^ PS_b[11];
assign #`db aML[11] = C11_b ^ PS_b[12];
assign #`db aML[12] = C12_b ^ PS_b[13];
assign #`db aML[13] = C13_b ^ PS_b[14];
assign #`db aML[14] = C14_b ^ PS_b[15];
wire [13:0] na;
assign #`da na[13:0] = M[13] ? (aM[14] ? aML[13:0] : aM[13:0])
: (aML[14] ? aM[13:0] : aML[13:0]);
assign #`da newI[13:0] = B[13:0] | na[13:0];
wire ALLZerob;
wire wrap1;
assign #`da ALLZerob = ~(L == 0);
assign #`da wrap1 = ~(~(M[13] & aM[14] & ALLZerob) & (M[13] | aML[14] | (~ALLZerob)));
wire wrap = STEAL_IE2 ? wrap2 : wrap1;
reg T0wrap, T1wrap, R0wrap, R1wrap;
always @(posedge DSPCLK) T0wrap <= #`da T0sack & wrap;
always @(posedge DSPCLK) T1wrap <= #`da T1sack & wrap;
always @(posedge DSPCLK) R0wrap <= #`da R0sack & wrap;
always @(posedge DSPCLK) R1wrap <= #`da R1sack & wrap;
endmodule
|
`define del 1
`include "../include/x_def.v"
module MODULO2 (/* OUT */ newI, wrap,
I, M, L);
/********************************/
/********************************/
input [13:0] I;
input [13:0] M;
input [13:0] L;
/********************************/
/********************************/
output [13:0] newI;
output wrap;
wire [13:0] PB, Pa;
reg [13:0] Lp, Ln;
reg Sb;
always @( L )
begin
casex( L )
14'b1????????????? : Lp[13:0] = 14'b11111111111111;
14'b01???????????? : Lp[13:0] = 14'b01111111111111;
14'b001??????????? : Lp[13:0] = 14'b00111111111111;
14'b0001?????????? : Lp[13:0] = 14'b00011111111111;
14'b00001????????? : Lp[13:0] = 14'b00001111111111;
14'b000001???????? : Lp[13:0] = 14'b00000111111111;
14'b0000001??????? : Lp[13:0] = 14'b00000011111111;
14'b00000001?????? : Lp[13:0] = 14'b00000001111111;
14'b000000001????? : Lp[13:0] = 14'b00000000111111;
14'b0000000001???? : Lp[13:0] = 14'b00000000011111;
14'b00000000001??? : Lp[13:0] = 14'b00000000001111;
14'b000000000001?? : Lp[13:0] = 14'b00000000000111;
14'b0000000000001? : Lp[13:0] = 14'b00000000000011;
14'b00000000000001 : Lp[13:0] = 14'b00000000000001;
14'b00000000000000 : Lp[13:0] = 14'b00000000000000;
default : Lp[13:0] = 14'b00000000000000;
endcase
end
always @( L )
begin
casex( L )
14'b?????????????1 : Ln[13:0] = 14'b11111111111111;
14'b????????????10 : Ln[13:0] = 14'b11111111111110;
14'b???????????100 : Ln[13:0] = 14'b11111111111100;
14'b??????????1000 : Ln[13:0] = 14'b11111111111000;
14'b?????????10000 : Ln[13:0] = 14'b11111111110000;
14'b????????100000 : Ln[13:0] = 14'b11111111100000;
14'b???????1000000 : Ln[13:0] = 14'b11111111000000;
14'b??????10000000 : Ln[13:0] = 14'b11111110000000;
14'b?????100000000 : Ln[13:0] = 14'b11111100000000;
14'b????1000000000 : Ln[13:0] = 14'b11111000000000;
14'b???10000000000 : Ln[13:0] = 14'b11110000000000;
14'b??100000000000 : Ln[13:0] = 14'b11100000000000;
14'b?1000000000000 : Ln[13:0] = 14'b11000000000000;
14'b10000000000000 : Ln[13:0] = 14'b10000000000000;
14'b00000000000000 : Ln[13:0] = 14'b00000000000000;
default : Ln[13:0] = 14'b00000000000000;
endcase
end
always @( L )
begin
case( L )
14'b00000000000000 : Sb = 0;
14'b00000000000001 : Sb = 0;
14'b00000000000010 : Sb = 0;
14'b00000000000100 : Sb = 0;
14'b00000000001000 : Sb = 0;
14'b00000000010000 : Sb = 0;
14'b00000000100000 : Sb = 0;
14'b00000001000000 : Sb = 0;
14'b00000010000000 : Sb = 0;
14'b00000100000000 : Sb = 0;
14'b00001000000000 : Sb = 0;
14'b00010000000000 : Sb = 0;
14'b00100000000000 : Sb = 0;
14'b01000000000000 : Sb = 0;
14'b10000000000000 : Sb = 0;
default : Sb = 1;
endcase
end
assign #`da PB[13:0] = Sb ? ~Lp[13:0] : Ln[13:0];
assign #`da Pa[13:0] = Sb ? Lp[13:0] : ~Ln[13:0];
/****************************************/
/****************************************/
wire [13:0] B, a;
assign B[13:0] = I[13:0] & PB[13:0];
assign a[13:0] = I[13:0] & Pa[13:0];
/******************************************/
/******************************************/
wire [14:0] Lx, Mx, ax;
assign Lx[14:0] = M[13] ? {1'b0, L[13:0]} : {1'b1, ~L[13:0]};
assign Mx[14:0] = {M[13], M[13:0]};
assign ax[14:0] = {1'b0, a[13:0]};
wire [14:0] aM;
wire [15:1] P_a, G_a, PS_a;
wire GS_a;
wire Cin_a = 1'b0;
assign P_a[15:1] = ax[14:0] | Mx[14:0];
assign G_a[15:1] = ax[14:0] & Mx[14:0];
assign PS_a[15:1] = ax[14:0] ^ Mx[14:0];
assign GS_a = Cin_a ? (G_a[1] | P_a[1]) : G_a[1];
/****************************************/
/****************************************/
wire [7:1] G1_a;
assign G1_a[1] = G_a[2] | (P_a[2] & GS_a );
assign G1_a[2] = G_a[4] | (P_a[4] & G_a[3] );
assign G1_a[3] = G_a[6] | (P_a[6] & G_a[5] );
assign G1_a[4] = G_a[8] | (P_a[8] & G_a[7] );
assign G1_a[5] = G_a[10] | (P_a[10] & G_a[9] );
assign G1_a[6] = G_a[12] | (P_a[12] & G_a[11]);
assign G1_a[7] = G_a[14] | (P_a[14] & G_a[13]);
/****************************************/
/****************************************/
wire [7:1] P1_a;
assign P1_a[1] = P_a[2] & P_a[1];
assign P1_a[2] = P_a[4] & P_a[3];
assign P1_a[3] = P_a[6] & P_a[5];
assign P1_a[4] = P_a[8] & P_a[7];
assign P1_a[5] = P_a[10] & P_a[9];
assign P1_a[6] = P_a[12] & P_a[11];
assign P1_a[7] = P_a[14] & P_a[13];
/****************************************/
/****************************************/
wire [4:1] G2_a;
assign G2_a[1] = G1_a[2] | (P1_a[2] & G1_a[1]);
assign G2_a[2] = G1_a[4] | (P1_a[4] & G1_a[3]);
assign G2_a[3] = G1_a[6] | (P1_a[6] & G1_a[5]);
assign G2_a[4] = G_a[15] | (P_a[15] & G1_a[7]);
/****************************************/
/****************************************/
wire [4:1] P2_a;
assign P2_a[1] = P1_a[2] & P1_a[1];
assign P2_a[2] = P1_a[4] & P1_a[3];
assign P2_a[3] = P1_a[6] & P1_a[5];
assign P2_a[4] = P_a[15] & P1_a[7];
/****************************************/
/****************************************/
wire [2:1] G3_a;
assign G3_a[1] = G2_a[2] | (P2_a[2] & G2_a[1]);
assign G3_a[2] = G2_a[4] | (P2_a[4] & G2_a[3]);
/****************************************/
/****************************************/
wire [2:1] P3_a;
assign P3_a[1] = P2_a[2] & P2_a[1];
assign P3_a[2] = P2_a[4] & P2_a[3];
/****************************************/
/****************************************/
wire C14_a, C13_a, C12_a, C11_a, C10_a;
wire C9_a, C8_a, C7_a, C6_a, C5_a;
wire C4_a, C3_a, C2_a, C1_a;
wire T1_a, T2_a, T3_a, T4_a, T5_a;
assign #`db C1_a = GS_a;
assign #`db C2_a = G1_a[1];
assign #`db C3_a = G_a[3] | (G1_a[1] & P_a[3]);
assign #`db C4_a = G2_a[1];
assign #`db C5_a = G_a[5] | (G2_a[1] & P_a[5] );
assign #`db C6_a = G1_a[3] | (G2_a[1] & P1_a[3]);
assign #`db C7_a = G_a[7] | ( C6_a & P_a[7] );
assign #`db C8_a = G3_a[1];
assign #`db C9_a = G_a[9] | (G3_a[1] & P_a[9] );
assign #`db C10_a = G1_a[5] | (G3_a[1] & P1_a[5]);
assign #`db T1_a = G_a[11] | (G1_a[5] & P_a[11]);
assign #`db C11_a = T1_a | (G3_a[1] & P_a[11] & P1_a[5]);
assign #`db C12_a = G2_a[3] | (G3_a[1] & P2_a[3]);
assign #`db T2_a = G_a[13] | (G2_a[3] & P_a[13]);
assign #`db C13_a = T2_a | (G3_a[1] & P2_a[3] & P_a[13]);
assign #`db T3_a = G1_a[7] | (G2_a[3] & P1_a[7]);
assign #`db C14_a = T3_a | (G3_a[1] & P2_a[3] & P1_a[7]);
/********************************/
/********************************/
assign #`db aM[0] = Cin_a ^ PS_a[1] ;
assign #`db aM[1] = C1_a ^ PS_a[2] ;
assign #`db aM[2] = C2_a ^ PS_a[3] ;
assign #`db aM[3] = C3_a ^ PS_a[4] ;
assign #`db aM[4] = C4_a ^ PS_a[5] ;
assign #`db aM[5] = C5_a ^ PS_a[6] ;
assign #`db aM[6] = C6_a ^ PS_a[7] ;
assign #`db aM[7] = C7_a ^ PS_a[8] ;
assign #`db aM[8] = C8_a ^ PS_a[9] ;
assign #`db aM[9] = C9_a ^ PS_a[10];
assign #`db aM[10] = C10_a ^ PS_a[11];
assign #`db aM[11] = C11_a ^ PS_a[12];
assign #`db aM[12] = C12_a ^ PS_a[13];
assign #`db aM[13] = C13_a ^ PS_a[14];
assign #`db aM[14] = C14_a ^ PS_a[15];
wire [14:0] aML, SO, CO;
CSA_d b0( ax[0], Mx[0], Lx[0], SO[0], CO[0] );
CSA_d b1( ax[1], Mx[1], Lx[1], SO[1], CO[1] );
CSA_d b2( ax[2], Mx[2], Lx[2], SO[2], CO[2] );
CSA_d b3( ax[3], Mx[3], Lx[3], SO[3], CO[3] );
CSA_d b4( ax[4], Mx[4], Lx[4], SO[4], CO[4] );
CSA_d b5( ax[5], Mx[5], Lx[5], SO[5], CO[5] );
CSA_d b6( ax[6], Mx[6], Lx[6], SO[6], CO[6] );
CSA_d b7( ax[7], Mx[7], Lx[7], SO[7], CO[7] );
CSA_d b8( ax[8], Mx[8], Lx[8], SO[8], CO[8] );
CSA_d b9( ax[9], Mx[9], Lx[9], SO[9], CO[9] );
CSA_d b10(ax[10], Mx[10], Lx[10], SO[10], CO[10] );
CSA_d b11(ax[11], Mx[11], Lx[11], SO[11], CO[11] );
CSA_d b12(ax[12], Mx[12], Lx[12], SO[12], CO[12] );
CSA_d b13(ax[13], Mx[13], Lx[13], SO[13], CO[13] );
CSA_d b14(ax[14], Mx[14], Lx[14], SO[14], CO[14] );
wire [14:0] CO_e = {CO[13:0], 1'b0};
wire Cin_b = ~M[13];
wire [15:1] P_b, G_b, PS_b;
wire GS_b;
assign P_b[15:1] = SO[14:0] | CO_e[14:0];
assign G_b[15:1] = SO[14:0] & CO_e[14:0];
assign PS_b[15:1] = SO[14:0] ^ CO_e[14:0];
assign GS_b = Cin_b ? (G_b[1] | P_b[1]) : G_b[1];
/****************************************/
/****************************************/
wire [7:1] G1_b;
assign G1_b[1] = G_b[2] | (P_b[2] & GS_b );
assign G1_b[2] = G_b[4] | (P_b[4] & G_b[3] );
assign G1_b[3] = G_b[6] | (P_b[6] & G_b[5] );
assign G1_b[4] = G_b[8] | (P_b[8] & G_b[7] );
assign G1_b[5] = G_b[10] | (P_b[10] & G_b[9] );
assign G1_b[6] = G_b[12] | (P_b[12] & G_b[11]);
assign G1_b[7] = G_b[14] | (P_b[14] & G_b[13]);
/****************************************/
/****************************************/
wire [7:1] P1_b;
assign P1_b[1] = P_b[2] & P_b[1];
assign P1_b[2] = P_b[4] & P_b[3];
assign P1_b[3] = P_b[6] & P_b[5];
assign P1_b[4] = P_b[8] & P_b[7];
assign P1_b[5] = P_b[10] & P_b[9];
assign P1_b[6] = P_b[12] & P_b[11];
assign P1_b[7] = P_b[14] & P_b[13];
/****************************************/
/****************************************/
wire [4:1] G2_b;
assign G2_b[1] = G1_b[2] | (P1_b[2] & G1_b[1]);
assign G2_b[2] = G1_b[4] | (P1_b[4] & G1_b[3]);
assign G2_b[3] = G1_b[6] | (P1_b[6] & G1_b[5]);
assign G2_b[4] = G_b[15] | (P_b[15] & G1_b[7]);
/****************************************/
/****************************************/
wire [4:1] P2_b;
assign P2_b[1] = P1_b[2] & P1_b[1];
assign P2_b[2] = P1_b[4] & P1_b[3];
assign P2_b[3] = P1_b[6] & P1_b[5];
assign P2_b[4] = P_b[15] & P1_b[7];
/****************************************/
/****************************************/
wire [2:1] G3_b;
assign G3_b[1] = G2_b[2] | (P2_b[2] & G2_b[1]);
assign G3_b[2] = G2_b[4] | (P2_b[4] & G2_b[3]);
/****************************************/
/****************************************/
wire [2:1] P3_b;
assign P3_b[1] = P2_b[2] & P2_b[1];
assign P3_b[2] = P2_b[4] & P2_b[3];
/****************************************/
/****************************************/
wire C14_b, C13_b, C12_b, C11_b, C10_b;
wire C9_b, C8_b, C7_b, C6_b, C5_b;
wire C4_b, C3_b, C2_b, C1_b;
wire T1_b, T2_b, T3_b, T4_b, T5_b;
assign #`db C1_b = GS_b;
assign #`db C2_b = G1_b[1];
assign #`db C3_b = G_b[3] | (G1_b[1] & P_b[3]);
assign #`db C4_b = G2_b[1];
assign #`db C5_b = G_b[5] | (G2_b[1] & P_b[5] );
assign #`db C6_b = G1_b[3] | (G2_b[1] & P1_b[3]);
assign #`db C7_b = G_b[7] | ( C6_b & P_b[7] );
assign #`db C8_b = G3_b[1];
assign #`db C9_b = G_b[9] | (G3_b[1] & P_b[9] );
assign #`db C10_b = G1_b[5] | (G3_b[1] & P1_b[5]);
assign #`db T1_b = G_b[11] | (G1_b[5] & P_b[11]);
assign #`db C11_b = T1_b | (G3_b[1] & P_b[11] & P1_b[5]);
assign #`db C12_b = G2_b[3] | (G3_b[1] & P2_b[3]);
assign #`db T2_b = G_b[13] | (G2_b[3] & P_b[13]);
assign #`db C13_b = T2_b | (G3_b[1] & P2_b[3] & P_b[13]);
assign #`db T3_b = G1_b[7] | (G2_b[3] & P1_b[7]);
assign #`db C14_b = T3_b | (G3_b[1] & P2_b[3] & P1_b[7]);
/********************************/
/********************************/
assign #`db aML[0] = Cin_b ^ PS_b[1] ;
assign #`db aML[1] = C1_b ^ PS_b[2] ;
assign #`db aML[2] = C2_b ^ PS_b[3] ;
assign #`db aML[3] = C3_b ^ PS_b[4] ;
assign #`db aML[4] = C4_b ^ PS_b[5] ;
assign #`db aML[5] = C5_b ^ PS_b[6] ;
assign #`db aML[6] = C6_b ^ PS_b[7] ;
assign #`db aML[7] = C7_b ^ PS_b[8] ;
assign #`db aML[8] = C8_b ^ PS_b[9] ;
assign #`db aML[9] = C9_b ^ PS_b[10];
assign #`db aML[10] = C10_b ^ PS_b[11];
assign #`db aML[11] = C11_b ^ PS_b[12];
assign #`db aML[12] = C12_b ^ PS_b[13];
assign #`db aML[13] = C13_b ^ PS_b[14];
assign #`db aML[14] = C14_b ^ PS_b[15];
wire [14:0] na;
assign na[13:0] = M[13] ? (aM[14] ? aML[13:0] : aM[13:0])
: (aML[14] ? aM[13:0] : aML[13:0]);
assign newI[13:0] = B[13:0] | na[13:0];
wire [14:0] MLx;
wire ALLZerob;
assign #`db ALLZerob = ~(L == 0);
assign #`db wrap = ~(~(M[13] & aM[14] & ALLZerob) & (M[13] | aML[14] | (~ALLZerob)));
endmodule
|
`include "../include/x_def.v"
module DEC (/* ---------- Inputs ---------- */
T_RST, DSPCLK, CM_rd,
`ifdef FD_DFT
SCAN_TEST,
`endif
PPclr_h, GO_D, GO_E, GO_C, Prderr_Eg,
/*TRAP_Eg,*/ ICE_ST, redoSTI_h,
MV, Ctrue,
Upd_IR, SPC, SBP_EN, /*HALT_Eg,*/ enTYP3,
IR, IREo, EX_en, EX_enc, Dummy_E,
Dummy_R, DU_R, dBR_R, idBR_R, RET_R, RTS_R,
EXIT_E, DU_Eg, Call_Ed, RTI_Ed, RTS_Ed, BR_Ed,
RET_Ed, Nseq_Ed, IDLE_Eg, MACdep_Eg, MTCNTR_Eg,
MTOWRCNTR_Eg, MTtoppcs_Eg, MTIMASK_Eg, MTICNTL_Eg,
MTIFC_Eg, MTMSTAT_Eg, MFPSQ_E, MFtoppcs_Eg,
MFIMASK_E, MFICNTL_E, MFSSTAT_E, MFMSTAT_E,
MFCNTR_E, Stkctl_Eg, Modctl_Eg, MpopLP_Eg,
imm16_E, imm14_E, Long_Eg, Nrti_Ed,
ALUop_E, cdAM_E, MTAX0_E, MTAX1_E, MTAY0_E,
MTAY1_E, MTAR_E, MTASTAT_E, MFAX0_E, MFAX1_E,
MFAY0_E, MFAY1_E, MFAR_E, MFASTAT_E, MFALU_E,
pMFALU_E, DIVQ_E, DIVS_E, updAR_E, updAF_E,
ALUop_R, type9, DIVQ_R, DIVS_R,
MACop_E, satMR_Eg, Rbyp_Rg, Xbyp_Rg, Ybyp_Rg,
MTMX0_Eg, MTMX1_Eg, MTMY0_Eg, MTMY1_Eg, MTMR0_Eg,
MTMR1_Eg, MTMR2_Eg, MFMX0_E, MFMX1_E, MFMY0_E,
MFMY1_E, MFMR0_E, MFMR1_E, MFMR2_E, MFMAC_E,
pMFMAC_E, updMR_E, updMF_E, Squ_Rx,
MACop_R,
SHTop_E, imSHT_E, MTSI_E, MTSE_E, MTSR0_E,
MTSR1_E, MTSB_E, MFSI_E, MFSE_E, MFSR0_E, MFSR1_E,
MFSB_E, MFSHT_E, pMFSHT_E, updSR0_Eg, updSR1_Eg,
updSR_E,
MTIreg_E, MTLreg_E, MTMreg_E,
MFIreg_E, MFLreg_E, MFMreg_E,
MFDAG1_E, MFDAG2_E, accPM_E, Double_R, Double_E,
Post1_E, Post2_E, DAG1D_R, DAG2D_R, imAddr_R,
DAG1_EN, DAG2_EN, DAG2P_R, DMAen_R,
Pread_R, Pwrite_R, Dread_R, Dwrite_R, IOcmd_R,
IOread_R, IOwrite_R, IDLE_R, MTPMOVL_E, MTDMOVL_E,
MFPMOVL_E, MFDMOVL_E,
MFSPT_E, MFRX0_E, MFTX0_E, MFRX1_E, MFTX1_E, MTRX0_E,
MTTX0_E, MTRX1_E, MTTX1_E,
SBP_R, MFIDR_E, MTIDR_Eg, nNOP_Eg, accCM_R, accCM_E,
wrCM_R, /*wrCM_E,*/ rdCM_E);
input [23:0] CM_rd,
SPC;
input T_RST,
DSPCLK,
PPclr_h,
GO_D,
GO_E,
GO_C,
ICE_ST,
redoSTI_h,
SBP_EN,
MV,
Ctrue,
Prderr_Eg,
enTYP3,
Upd_IR;
`ifdef FD_DFT
input SCAN_TEST;
`endif
output [23:0] IR;
output [19:0] IREo;
output [7:0] MTIreg_E,
MTLreg_E,
MTMreg_E,
MFIreg_E,
MFLreg_E,
MFMreg_E;
output
Dummy_R,
Dummy_E,
EX_en,
EX_enc,
Long_Eg,
DU_R, DU_Eg,
dBR_R,
idBR_R,
RET_R,
RTS_R,
EXIT_E,
Call_Ed,
RTI_Ed,
RTS_Ed,
BR_Ed,
RET_Ed,
Nseq_Ed,
Nrti_Ed,
IDLE_R, IDLE_Eg,
MACdep_Eg,
MTCNTR_Eg,
MTOWRCNTR_Eg,
MTtoppcs_Eg,
MTIMASK_Eg,
MTICNTL_Eg,
MTIFC_Eg,
MTMSTAT_Eg,
MFPSQ_E,
MFtoppcs_Eg,
MFIMASK_E,
MFICNTL_E,
MFSSTAT_E,
MFMSTAT_E,
MFCNTR_E,
imm16_E,
imm14_E,
Stkctl_Eg,
Modctl_Eg,
MpopLP_Eg,
ALUop_E,
ALUop_R,
cdAM_E,
DIVQ_R,
DIVS_R,
DIVQ_E,
DIVS_E,
type9,
MTAX0_E,
MTAX1_E,
MTAY0_E,
MTAY1_E,
MTAR_E,
MTASTAT_E,
MFAX0_E,
MFAX1_E,
MFAY0_E,
MFAY1_E,
MFAR_E,
MFASTAT_E,
MFALU_E,
pMFALU_E,
updAR_E,
updAF_E,
MACop_E,
MACop_R,
satMR_Eg,
Rbyp_Rg,
Xbyp_Rg,
Ybyp_Rg,
MTMX0_Eg,
MTMX1_Eg,
MTMY0_Eg,
MTMY1_Eg,
MTMR0_Eg,
MTMR1_Eg,
MTMR2_Eg,
MFMX0_E,
MFMX1_E,
MFMY0_E,
MFMY1_E,
MFMR0_E,
MFMR1_E,
MFMR2_E,
MFMAC_E,
pMFMAC_E,
updMR_E,
updMF_E,
Squ_Rx,
SHTop_E,
imSHT_E,
MTSI_E,
MTSE_E,
MTSR0_E,
MTSR1_E,
MTSB_E,
MFSI_E,
MFSE_E,
MFSR0_E,
MFSR1_E,
MFSB_E,
MFSHT_E,
pMFSHT_E,
updSR0_Eg,
updSR1_Eg,
updSR_E,
MFDAG1_E,
MFDAG2_E,
accPM_E,
Double_R, Double_E,
Post1_E,
Post2_E,
imAddr_R,
DAG1D_R,
DAG2D_R,
DMAen_R,
Pread_R,
Pwrite_R,
Dread_R,
Dwrite_R,
IOcmd_R,
IOread_R,
IOwrite_R,
SBP_R,
nNOP_Eg,
MFIDR_E,
MTIDR_Eg;
output MFRX0_E, MFTX0_E, MFRX1_E, MFTX1_E,
MTRX0_E, MTTX0_E, MTRX1_E, MTTX1_E,
MFSPT_E, MFPMOVL_E, MFDMOVL_E, MTPMOVL_E,
MTDMOVL_E, accCM_R, accCM_E, wrCM_R,
/*wrCM_E,*/ rdCM_E;
output DAG1_EN, DAG2_EN, DAG2P_R;
reg [23:0] IR, IRE;
reg [7:0] MFIreg_E, MFLreg_E, MFMreg_E,
MTIreg_E, MTLreg_E, MTMreg_E;
reg MFMSTAT_E, MFSSTAT_E, MFIMASK_E, MFICNTL_E, MFCNTR_E,
MFtoppcs_Eg, MTMSTAT_Eg, MTIMASK_Eg, MTICNTL_Eg,
MTCNTR_Eg, MTIFC_Eg, MTOWRCNTR_Eg, MTtoppcs_Eg,
Modctl_Eg, Stkctl_Eg, DU_Eg, MpopLP_Eg, Nseq_Ed,
RET_Ed, BR_Ed, Call_Ed, RTI_Ed, RTS_Ed, IDLE_Eg,
updCTL_E, MACdep_Eg, MFASTAT_E, MFAX0_E, MFAX1_E,
MFAY0_E, MFAY1_E, MFAR_E, MFMX0_E, MFMX1_E, MFMY0_E,
MFMY1_E, MFMR0_E, MFMR1_E, MFMR2_E, MFSI_E, MFSB_E,
MFSE_E, MFSR0_E, MFSR1_E, MTAX0_E, MTAX1_E, MTAY0_E,
MTAY1_E, MTAR_E, MTASTAT_E, MTMX0_E, MTMX1_E, MTMY0_E,
MTMY1_E, MTMR0_E, MTMR1_E, MTMR2_E, MTSI_E, MTSE_E,
MTSR0_E, MTSR1_E, MTSB_E, accPM_E, Double_E, Post1_E,
Post2_E, DIVQ_E, DIVS_E, imSHT_E, updMR_E, updMF_E,
updAR_E, updAF_E, updSR_E, Usecond_E, Dummy_E, Dummy_C,
Prderr_Cg, DU_Cg, cdAM_E, satMR_E, imm16_E,
imm14_E, NOP_E, MTIDR_E, MFIDR_E, EXIT_E, Long_Eg,
Long_Cg, Nrti_Ed, MFPSQ_Ei, MFSPT_Ei, MFDAG1_Ei,
MFDAG2_Ei, MFMAC_Ei, MFALU_Ei, MFSHT_Ei, pMFMAC_Ei,
pMFALU_Ei, pMFSHT_Ei;
reg MFRX0_E, MFTX0_E, MFRX1_E, MFTX1_E, MTRX0_E, MTTX0_E,
MTRX1_E, MTTX1_E, MTPMOVL_E, MTDMOVL_E,
MFPMOVL_E, MFDMOVL_E, accCM_E, rdCM_E ;
reg MFPSQ_Ci, MFSPT_Ci, MFDAG1_Ci, MFDAG2_Ci, MFALU_Ci,
MFMAC_Ci, MFSHT_Ci, pMFALU_Ci, pMFMAC_Ci, pMFSHT_Ci;
reg SHTop_E, MACop_E, ALUop_E;
wire [31:1] Typ;
wire [7:0] MFIreg_R, MFLreg_R, MFMreg_R,
MTIreg_R, MTMreg_R, MTLreg_R;
wire [2:0] MACxop_R;
wire [3:0] MACyop_R, SF_R;
wire [4:0] AMF_R;
wire [5:0] dcreg_R, screg_R, ddreg_R, sdreg_R;
wire MTcreg_R, MFcreg_R, MTASTAT_R, MTMSTAT_R, MTIMASK_R,
MTICNTL_R, MTCNTR_R, MTSB_R, MTIFC_R, MTOWRCNTR_R,
MTtoppcs_R, MFASTAT_R, MFMSTAT_R, MFSSTAT_R, MFIMASK_R,
MFICNTL_R, MFSB_R, MFPX_R, MTdreg_R, MFdreg_R, MTAX0_R,
MTAX1_R, MTMX0_R, MTMX1_R, MTAY0_R, MTAY1_R, MTMY0_R,
MTMY1_R, MTSI_R, MTSE_R, MTAR_R, MTMR0_R, MTMR1_R,
MTMR2_R, MTSR0_R, MTSR1_R, MFAX0_R, MFAX1_R, MFMX0_R,
MFMX1_R, MFAY0_R, MFAY1_R, MFMY0_R, MFMY1_R, MFSI_R,
MFSE_R, MFAR_R, MFMR0_R, MFMR1_R, MFMR2_R, MFSR0_R,
MFSR1_R, Post1_R, Post2_R, Usecond_R, MpopLP_R,
Stkctl_R, Nseq_R, BR_R, Call_R, RTI_R, RTS_R,
Modctl_R, ALUop_R, MACop_R, SHTop_R;
wire MXeqMX0_R, MXeqMX1_R, MXeqAR_R, MXeqMR0_R, MXeqMR1_R,
MXeqMR2_R, MXeqSR0_R, MXeqSR1_R, MXeqMR_R, MYeqMX0_R,
MYeqMX1_R, MYeqAR_R, MYeqMR0_R, MYeqMR1_R, MYeqMR2_R,
MYeqSR0_R, MYeqSR1_R, MYeqMY0_R, MYeqMY1_R, MYeqMF_R,
MYeq0_R, MYeqMR_R, satMR_R, updMR_R, updMF_R, updAR_R,
updAF_R, updSR_R, savMR0_Eg, savMR1_Eg, savMR2_Eg,
MACdep_Rg, MFtoppcs_R, MFCNTR_R, Squ_R,
imm16_R, imm14_R, MFIDR_R, MTIDR_R, EXIT_R, CKtrue,
Long_R, Nrti_R,
MFPSQ_R, MFDAG1_R,
MFDAG2_R, MFALU_R, MFMAC_R, MFSHT_R, mtPMD_R, MFSPT_R;
wire MFRX0_R, MFTX0_R, MFRX1_R, MFTX1_R, MTRX0_R, MTTX0_R,
MTRX1_R, MTTX1_R, MTPMOVL_R, MTDMOVL_R, MFPMOVL_R,
MFDMOVL_R, accCM_R, rdCM_R, wrCM_R;
wire updMR_Eg, updMF_Eg, updAR_Eg, updAF_Eg;
`ifdef FD_DFT
reg PPclr_o, RST_o;
wire PPclr, RST;
always @(posedge DSPCLK) begin
PPclr_o <= #`db T_RST || PPclr_h;
RST_o <= #`db T_RST;
end
assign PPclr = SCAN_TEST ? T_RST : PPclr_o;
assign RST = SCAN_TEST ? T_RST : RST_o;
`else
reg PPclr, RST;
always @(posedge DSPCLK) begin
PPclr <= #`db T_RST || PPclr_h;
RST <= #`db T_RST;
end
`endif
always @(posedge DSPCLK or posedge RST) begin
if (RST) IR[23:0] <= #`db 24'b0;
else if (GO_D) IR[23:0] <= #`db CM_rd[23:0];
else if (Upd_IR) IR[23:0] <= #`db SPC[23:0];
end
always @(posedge DSPCLK or posedge RST) begin
if (RST) IRE[23:0] <= #`db 24'b0;
else if (GO_E) IRE[23:0] <= #`db IR[23:0];
end
assign #`d0 IREo[19:0] = IRE[19:0];
assign #`da Long_R = MFtoppcs_R || MTtoppcs_R || DU_R ||
Stkctl_R || MTIMASK_R || MTMSTAT_R ||
MTASTAT_R ||
Modctl_R && (IR[13] || IR[7] || IR[5]) ||
MTPMOVL_R || MTDMOVL_R;
always @(posedge DSPCLK) begin
if (PPclr_h) Long_Eg <= #`db 1'b0;
else if (GO_E) Long_Eg <= #`db Long_R && !Dummy_R;
end
always @(posedge DSPCLK) begin
if (PPclr_h) Long_Cg <= #`db 1'b0;
else if (GO_C) Long_Cg <= #`db Long_Eg;
end
assign #`da imm16_R = Typ[2] || Typ[6];
assign #`d0 imm14_R = Typ[7];
assign #`da Typ[2] = (IR[23:22]== 2'b11);
assign #`da Typ[1] = (IR[23:21]== 3'b101);
assign #`da Typ[4] = (IR[23:21]== 3'b100) && enTYP3;
assign #`da accCM_R = (IR[23:21]== 3'b100) && !enTYP3;
assign #`da Typ[3] = (IR[23:21]== 3'b011);
assign #`da Typ[6] = (IR[23:20]== 4'b0101);
assign #`da Typ[5] = (IR[23:20]== 4'b0100);
assign #`da Typ[8] = (IR[23:20]== 4'b0011);
assign #`da Typ[7] = (IR[23:19]== 5'b0010_1);
assign #`da Typ[9] = (IR[23:19]== 5'b0010_0);
assign #`da Typ[11] = (IR[23:19]== 5'b0001_1);
assign #`da Typ[10] = (IR[23:18]== 6'b0001_01);
assign #`da Typ[13] = (IR[23:17]== 7'b0001_001);
assign #`da Typ[12] = (IR[23:16]== 8'b0001_0001);
assign #`da Typ[15] = (IR[23:16]== 8'b0001_0000);
assign #`da Typ[14] = (IR[23:16]== 8'b0000_1111);
assign #`da Typ[17] = (IR[23:16]== 8'b0000_1110);
assign #`da Typ[16] = (IR[23:16]== 8'b0000_1101);
assign #`da Typ[19] = (IR[23:16]== 8'b0000_1100);
assign #`da Typ[18] = (IR[23:16]== 8'b0000_1011);
assign #`da Typ[21] = (IR[23:16]== 8'b0000_1010);
assign #`da Typ[20] = (IR[23:16]== 8'b0000_1001);
assign #`da Typ[23] = (IR[23:16]== 8'b0000_1000);
assign #`da Typ[22] = (IR[23:16]== 8'b0000_0111);
assign #`da Typ[25] = (IR[23:16]== 8'b0000_0110);
assign #`da Typ[24] = (IR[23:16]== 8'b0000_0101);
assign #`da Typ[27] = (IR[23:16]== 8'b0000_0100);
assign #`da Typ[26] = (IR[23:16]== 8'b0000_0011);
assign #`da Typ[29] = (IR[23:15]== 9'b0000_0010_0);
assign #`da Typ[28] = (IR[23:16]== 8'b0000_0001);
assign #`da Typ[31] = (IR[23:16]== 8'b0000_0000);
assign #`da Typ[30] = (IR[23:15]== 9'b0000_0010_1);
assign #`da rdCM_R = accCM_R && !IR[20];
assign #`da wrCM_R = accCM_R && IR[20];
always @(posedge DSPCLK or posedge PPclr_h) begin
if (PPclr_h) begin
accCM_E <= #`db 1'b0;
rdCM_E <= #`db 1'b0;
end
else if (GO_E) begin
accCM_E <= #`db accCM_R;
rdCM_E <= #`db rdCM_R;
end
end
assign #`da MTcreg_R = (Typ[3] && !IR[20]) || Typ[7] || Typ[17];
assign #`da dcreg_R[5:0] = Typ[17] ? {IR[11:10], IR[7:4]}
: {IR[19:18], IR[3:0]};
assign #`da MFcreg_R = (Typ[3] && IR[20]) || Typ[17];
assign #`da screg_R[5:0] = Typ[17] ? {IR[9:8], IR[3:0]}
: {IR[19:18], IR[3:0]};
assign #`da MTASTAT_R = MTcreg_R && (dcreg_R == 6'h30);
assign #`da MTMSTAT_R = MTcreg_R && (dcreg_R == 6'h31);
assign #`da MTIMASK_R = MTcreg_R && (dcreg_R == 6'h33);
assign #`da MTICNTL_R = MTcreg_R && (dcreg_R == 6'h34);
assign #`da MTCNTR_R = MTcreg_R && (dcreg_R == 6'h35);
assign #`da MTSB_R = MTcreg_R && (dcreg_R == 6'h36);
assign #`da MTRX0_R = MTcreg_R && (dcreg_R == 6'h38);
assign #`da MTTX0_R = MTcreg_R && (dcreg_R == 6'h39);
assign #`da MTRX1_R = MTcreg_R && (dcreg_R == 6'h3a);
assign #`da MTTX1_R = MTcreg_R && (dcreg_R == 6'h3b);
assign #`da MTIFC_R = MTcreg_R && (dcreg_R == 6'h3c);
assign #`da MTOWRCNTR_R = MTcreg_R && (dcreg_R == 6'h3d);
assign #`da MTtoppcs_R = MTcreg_R && (dcreg_R == 6'h3f);
assign #`da MTIreg_R[0] = MTcreg_R && (dcreg_R == 6'h10);
assign #`da MTIreg_R[1] = MTcreg_R && (dcreg_R == 6'h11);
assign #`da MTIreg_R[2] = MTcreg_R && (dcreg_R == 6'h12);
assign #`da MTIreg_R[3] = MTcreg_R && (dcreg_R == 6'h13);
assign #`da MTMreg_R[0] = MTcreg_R && (dcreg_R == 6'h14);
assign #`da MTMreg_R[1] = MTcreg_R && (dcreg_R == 6'h15);
assign #`da MTMreg_R[2] = MTcreg_R && (dcreg_R == 6'h16);
assign #`da MTMreg_R[3] = MTcreg_R && (dcreg_R == 6'h17);
assign #`da MTLreg_R[0] = MTcreg_R && (dcreg_R == 6'h18);
assign #`da MTLreg_R[1] = MTcreg_R && (dcreg_R == 6'h19);
assign #`da MTLreg_R[2] = MTcreg_R && (dcreg_R == 6'h1a);
assign #`da MTLreg_R[3] = MTcreg_R && (dcreg_R == 6'h1b);
assign #`da MTIDR_R = MTcreg_R && (dcreg_R == 6'h1c);
assign #`da MTPMOVL_R = MTcreg_R && (dcreg_R == 6'h1e);
assign #`da MTDMOVL_R = MTcreg_R && (dcreg_R == 6'h1f);
assign #`da MTIreg_R[4] = MTcreg_R && (dcreg_R == 6'h20);
assign #`da MTIreg_R[5] = MTcreg_R && (dcreg_R == 6'h21);
assign #`da MTIreg_R[6] = MTcreg_R && (dcreg_R == 6'h22);
assign #`da MTIreg_R[7] = MTcreg_R && (dcreg_R == 6'h23);
assign #`da MTMreg_R[4] = MTcreg_R && (dcreg_R == 6'h24);
assign #`da MTMreg_R[5] = MTcreg_R && (dcreg_R == 6'h25);
assign #`da MTMreg_R[6] = MTcreg_R && (dcreg_R == 6'h26);
assign #`da MTMreg_R[7] = MTcreg_R && (dcreg_R == 6'h27);
assign #`da MTLreg_R[4] = MTcreg_R && (dcreg_R == 6'h28);
assign #`da MTLreg_R[5] = MTcreg_R && (dcreg_R == 6'h29);
assign #`da MTLreg_R[6] = MTcreg_R && (dcreg_R == 6'h2a);
assign #`da MTLreg_R[7] = MTcreg_R && (dcreg_R == 6'h2b);
assign #`da MFASTAT_R = MFcreg_R && (screg_R == 6'h30);
assign #`da MFMSTAT_R = MFcreg_R && (screg_R == 6'h31);
assign #`da MFSSTAT_R = MFcreg_R && (screg_R == 6'h32);
assign #`da MFIMASK_R = MFcreg_R && (screg_R == 6'h33);
assign #`da MFICNTL_R = MFcreg_R && (screg_R == 6'h34);
assign #`da MFCNTR_R = MFcreg_R && (screg_R == 6'h35);
assign #`da MFSB_R = MFcreg_R && (screg_R == 6'h36);
assign #`da MFPX_R = MFcreg_R && (screg_R == 6'h37);
assign #`da MFRX0_R = MFcreg_R && (screg_R == 6'h38);
assign #`da MFTX0_R = MFcreg_R && (screg_R == 6'h39);
assign #`da MFRX1_R = MFcreg_R && (screg_R == 6'h3a);
assign #`da MFTX1_R = MFcreg_R && (screg_R == 6'h3b);
assign #`da MFtoppcs_R = MFcreg_R && (screg_R == 6'h3f);
assign #`da MFIreg_R[0] = MFcreg_R && (screg_R == 6'h10);
assign #`da MFIreg_R[1] = MFcreg_R && (screg_R == 6'h11);
assign #`da MFIreg_R[2] = MFcreg_R && (screg_R == 6'h12);
assign #`da MFIreg_R[3] = MFcreg_R && (screg_R == 6'h13);
assign #`da MFMreg_R[0] = MFcreg_R && (screg_R == 6'h14);
assign #`da MFMreg_R[1] = MFcreg_R && (screg_R == 6'h15);
assign #`da MFMreg_R[2] = MFcreg_R && (screg_R == 6'h16);
assign #`da MFMreg_R[3] = MFcreg_R && (screg_R == 6'h17);
assign #`da MFLreg_R[0] = MFcreg_R && (screg_R == 6'h18);
assign #`da MFLreg_R[1] = MFcreg_R && (screg_R == 6'h19);
assign #`da MFLreg_R[2] = MFcreg_R && (screg_R == 6'h1a);
assign #`da MFLreg_R[3] = MFcreg_R && (screg_R == 6'h1b);
assign #`da MFIDR_R = MFcreg_R && (screg_R == 6'h1c);
assign #`da MFPMOVL_R = MFcreg_R && (screg_R == 6'h1e);
assign #`da MFDMOVL_R = MFcreg_R && (screg_R == 6'h1f);
assign #`da MFIreg_R[4] = MFcreg_R && (screg_R == 6'h20);
assign #`da MFIreg_R[5] = MFcreg_R && (screg_R == 6'h21);
assign #`da MFIreg_R[6] = MFcreg_R && (screg_R == 6'h22);
assign #`da MFIreg_R[7] = MFcreg_R && (screg_R == 6'h23);
assign #`da MFMreg_R[4] = MFcreg_R && (screg_R == 6'h24);
assign #`da MFMreg_R[5] = MFcreg_R && (screg_R == 6'h25);
assign #`da MFMreg_R[6] = MFcreg_R && (screg_R == 6'h26);
assign #`da MFMreg_R[7] = MFcreg_R && (screg_R == 6'h27);
assign #`da MFLreg_R[4] = MFcreg_R && (screg_R == 6'h28);
assign #`da MFLreg_R[5] = MFcreg_R && (screg_R == 6'h29);
assign #`da MFLreg_R[6] = MFcreg_R && (screg_R == 6'h2a);
assign #`da MFLreg_R[7] = MFcreg_R && (screg_R == 6'h2b);
assign #`da MTdreg_R = Typ[3] && !IR[20] ||
Typ[7] || Typ[17] ||
(Typ[4] || Typ[5]) && !IR[19] ||
Typ[6] || Typ[8] || Typ[14] ||
(Typ[12] || Typ[13] || Typ[29]) && !IR[15];
assign #`da ddreg_R[5:4] = {2{Typ[3] || Typ[7]}} & IR[19:18] |
{2{Typ[17]}} & IR[11:10];
assign #`da ddreg_R[3:0] = (Typ[3] || Typ[6] || Typ[7] || Typ[29])
? IR[3:0] : IR[7:4];
assign #`da MFdreg_R = Typ[8] || Typ[14] || Typ[17] ||
Typ[3] && IR[20] ||
(Typ[4] || Typ[5]) && IR[19] ||
(Typ[12] || Typ[13] || Typ[29]) && IR[15];
assign #`da sdreg_R[5:4] = {2{Typ[3]}} & IR[19:18] |
{2{Typ[17]}} & IR[9:8];
assign #`da sdreg_R[3:0] = (Typ[3] || Typ[8] || Typ[14] ||
Typ[17] || Typ[29]) ? IR[3:0] : IR[7:4];
assign #`da mtPMD_R = Typ[5] || Typ[13];
assign #`da MTAX0_R = MTdreg_R && (ddreg_R == 6'h0) ||
Typ[1] && (IR[19:18] == 2'b00);
assign #`da MTAX1_R = MTdreg_R && (ddreg_R == 6'h1) ||
Typ[1] && (IR[19:18] == 2'b01);
assign #`da MTMX0_R = MTdreg_R && (ddreg_R == 6'h2) ||
Typ[1] && (IR[19:18] == 2'b10);
assign #`da MTMX1_R = MTdreg_R && (ddreg_R == 6'h3) ||
Typ[1] && (IR[19:18] == 2'b11);
assign #`da MTAY0_R = MTdreg_R && (ddreg_R == 6'h4) ||
Typ[1] && (IR[21:20] == 2'b00);
assign #`da MTAY1_R = MTdreg_R && (ddreg_R == 6'h5) ||
Typ[1] && (IR[21:20] == 2'b01);
assign #`da MTMY0_R = MTdreg_R && (ddreg_R == 6'h6) ||
Typ[1] && (IR[21:20] == 2'b10);
assign #`da MTMY1_R = MTdreg_R && (ddreg_R == 6'h7) ||
Typ[1] && (IR[21:20] == 2'b11);
assign #`da MTSI_R = MTdreg_R && (ddreg_R == 6'h8);
assign #`da MTSE_R = MTdreg_R && (ddreg_R == 6'h9);
assign #`da MTAR_R = MTdreg_R && (ddreg_R == 6'ha);
assign #`da MTMR0_R = MTdreg_R && (ddreg_R == 6'hb);
assign #`da MTMR1_R = MTdreg_R && (ddreg_R == 6'hc);
assign #`da MTMR2_R = MTdreg_R && (ddreg_R == 6'hd);
assign #`da MTSR0_R = MTdreg_R && (ddreg_R == 6'he);
assign #`da MTSR1_R = MTdreg_R && (ddreg_R == 6'hf);
assign #`da MFAX0_R = MFdreg_R && (sdreg_R == 6'h0);
assign #`da MFAX1_R = MFdreg_R && (sdreg_R == 6'h1);
assign #`da MFMX0_R = MFdreg_R && (sdreg_R == 6'h2);
assign #`da MFMX1_R = MFdreg_R && (sdreg_R == 6'h3);
assign #`da MFAY0_R = MFdreg_R && (sdreg_R == 6'h4);
assign #`da MFAY1_R = MFdreg_R && (sdreg_R == 6'h5);
assign #`da MFMY0_R = MFdreg_R && (sdreg_R == 6'h6);
assign #`da MFMY1_R = MFdreg_R && (sdreg_R == 6'h7);
assign #`da MFSI_R = MFdreg_R && (sdreg_R == 6'h8);
assign #`da MFSE_R = MFdreg_R && (sdreg_R == 6'h9);
assign #`da MFAR_R = MFdreg_R && (sdreg_R == 6'ha);
assign #`da MFMR0_R = MFdreg_R && (sdreg_R == 6'hb);
assign #`da MFMR1_R = MFdreg_R && (sdreg_R == 6'hc);
assign #`da MFMR2_R = MFdreg_R && (sdreg_R == 6'hd);
assign #`da MFSR0_R = MFdreg_R && (sdreg_R == 6'he);
assign #`da MFSR1_R = MFdreg_R && (sdreg_R == 6'hf);
assign #`d0 Double_R = Typ[1];
assign #`da Post1_R = Typ[1] ||
Typ[21] && !IR[4] ||
Typ[12] && !IR[16] ||
(Typ[2] || Typ[4]) && !IR[20];
assign #`da Post2_R = Typ[1] || Typ[5] || Typ[13] ||
Typ[12] && IR[16] ||
Typ[21] && IR[4] ||
(Typ[2] || Typ[4]) && IR[20];
assign #`d0 imAddr_R = Typ[3];
assign #`da DAG1D_R = Typ[1] ||
(Typ[2] || Typ[4]) && !IR[20] ||
Typ[12] && !IR[16];
assign #`da DAG2D_R = (Typ[2] || Typ[4]) && IR[20] ||
Typ[12] && IR[16];
assign #`da DMAen_R = Typ[1] || Typ[2] || Typ[3] || Typ[4] || Typ[12];
assign #`da DAG2P_R = Typ[1] || Typ[5] || Typ[13];
assign #`da Pread_R = Typ[1] ||
Typ[5] && !IR[19] ||
Typ[13] && !IR[15];
assign #`da Pwrite_R = Typ[5] && IR[19] ||
Typ[13] && IR[15];
assign #`da Dread_R = Typ[1] ||
Typ[3] && !IR[20] ||
Typ[4] && !IR[19] ||
Typ[12] && !IR[15];
assign #`da Dwrite_R = Typ[2] ||
Typ[3] && IR[20] ||
Typ[4] && IR[19] ||
Typ[12] && IR[15];
assign #`da IOcmd_R = Typ[29];
assign #`da IOread_R = Typ[29] && !IR[15];
assign #`da IOwrite_R = Typ[29] && IR[15];
assign #`da Usecond_R = Typ[9] ||
Typ[10] ||
Typ[16] ||
Typ[19] ||
RET_R ||
Typ[28];
assign #`d0 Modctl_R = Typ[18];
assign #`d0 Stkctl_R = Typ[26];
assign #`da MpopLP_R = Stkctl_R && IR[3];
assign #`d0 DU_R = Typ[11];
assign #`da Nseq_R = Typ[10] || Typ[19] || RET_R;
assign #`da Nrti_R = Typ[10] || Typ[19] || RTS_R;
assign #`da BR_R = Typ[10] || Typ[19];
assign #`d0 dBR_R = Typ[10];
assign #`d0 idBR_R = Typ[19];
assign #`da Call_R = Typ[10] && IR[18] ||
Typ[19] && IR[4];
assign #`d0 AMF_R[4:0] = IR[17:13];
assign #`d0 SF_R[3:0] = IR[14:11];
assign #`da ALUop_R = AMF_R[4] &&
(Typ[1] || Typ[4] || Typ[5] || Typ[8] || Typ[9]);
assign #`da MACop_R = !AMF_R[4] && (|{AMF_R[3:0]}) &&
(Typ[1] || Typ[4] || Typ[5] || Typ[8] || Typ[9]);
assign #`da Squ_Rx = Typ[9] && IR[4];
assign #`da Squ_R = !AMF_R[4] && (|{AMF_R[3:0]}) && Typ[9] && IR[4];
assign #`da SHTop_R = Typ[12] || Typ[13] || Typ[14] || Typ[15] || Typ[16];
assign #`d0 MACxop_R[2:0] = IR[10:8];
assign #`da MACyop_R[3:0] = Squ_R ? {1'b1, IR[10:8]}
: {2'b0, IR[12:11]};
assign #`da MXeqMX0_R = MACxop_R[2:0] == 3'b000;
assign #`da MXeqMX1_R = MACxop_R[2:0] == 3'b001;
assign #`da MXeqAR_R = MACxop_R[2:0] == 3'b010;
assign #`da MXeqMR0_R = MACxop_R[2:0] == 3'b011;
assign #`da MXeqMR1_R = MACxop_R[2:0] == 3'b100;
assign #`da MXeqMR2_R = MACxop_R[2:0] == 3'b101;
assign #`da MXeqSR0_R = MACxop_R[2:0] == 3'b110;
assign #`da MXeqSR1_R = MACxop_R[2:0] == 3'b111;
assign #`da MXeqMR_R = MXeqMR0_R || MXeqMR1_R || MXeqMR2_R;
assign #`da MYeqMX0_R = MACyop_R[3:0] == 4'b1000;
assign #`da MYeqMX1_R = MACyop_R[3:0] == 4'b1001;
assign #`da MYeqAR_R = MACyop_R[3:0] == 4'b1010;
assign #`da MYeqMR0_R = MACyop_R[3:0] == 4'b1011;
assign #`da MYeqMR1_R = MACyop_R[3:0] == 4'b1100;
assign #`da MYeqMR2_R = MACyop_R[3:0] == 4'b1101;
assign #`da MYeqSR0_R = MACyop_R[3:0] == 4'b1110;
assign #`da MYeqSR1_R = MACyop_R[3:0] == 4'b1111;
assign #`da MYeqMY0_R = MACyop_R[3:0] == 4'b0000;
assign #`da MYeqMY1_R = MACyop_R[3:0] == 4'b0001;
assign #`da MYeqMF_R = MACyop_R[3:0] == 4'b0010;
assign #`da MYeq0_R = MACyop_R[3:0] == 4'b0011;
assign #`da MYeqMR_R = MYeqMR0_R || MYeqMR1_R || MYeqMR2_R;
assign #`d0 satMR_R = Typ[25];
assign #`da updMR_R = MACop_R && (!IR[18] || Double_R);
assign #`da updMF_R = MACop_R && ( IR[18] && !Double_R);
assign #`da updAR_R = ALUop_R && (!IR[18] || Double_R);
assign #`da updAF_R = ALUop_R && ( IR[18] && !Double_R);
assign #`da updSR_R = SHTop_R && (SF_R[3:2] != 2'b11);
assign #`da satMR_Eg = satMR_E && EX_en && MV;
assign #`da updMR_Eg = updMR_E && EX_enc;
assign #`da updMF_Eg = updMF_E && EX_enc;
assign #`da MTMR0_Eg = MTMR0_E && EX_en;
assign #`da MTMR1_Eg = MTMR1_E && EX_en;
assign #`da MTMR2_Eg = MTMR2_E && EX_en;
assign #`da MTMX0_Eg = MTMX0_E && EX_en;
assign #`da MTMX1_Eg = MTMX1_E && EX_en;
assign #`da MTMY0_Eg = MTMY0_E && EX_en;
assign #`da MTMY1_Eg = MTMY1_E && EX_en;
assign #`da savMR0_Eg = satMR_Eg || MTMR0_Eg;
assign #`da savMR1_Eg = satMR_Eg || MTMR1_Eg;
assign #`da savMR2_Eg = satMR_Eg || MTMR1_Eg || MTMR2_Eg;
assign #`da updAR_Eg = updAR_E && EX_enc || MTAR_E && EX_en;
assign #`da updAF_Eg = updAF_E && EX_enc;
assign #`da updSR0_Eg = updSR_E && EX_enc || MTSR0_E && EX_en;
assign #`da updSR1_Eg = updSR_E && EX_enc || MTSR1_E && EX_en;
assign #`da MACdep_Rg = MACop_R && (updMF_Eg && MYeqMF_R ||
updMR_Eg && (MXeqMR_R || MYeqMR_R));
assign #`da Xbyp_Rg = MACop_R && (MTMX0_Eg && MXeqMX0_R ||
MTMX1_Eg && MXeqMX1_R);
assign #`da Ybyp_Rg = MACop_R && (
MTMY0_Eg && MYeqMY0_R ||
MTMY1_Eg && MYeqMY1_R);
assign #`da Rbyp_Rg = MACop_R && (savMR2_Eg && (MXeqMR2_R || MYeqMR2_R) ||
savMR1_Eg && (MXeqMR1_R || MYeqMR1_R) ||
savMR0_Eg && (MXeqMR0_R || MYeqMR0_R) ||
updAR_Eg && (MXeqAR_R || MYeqAR_R) ||
updSR1_Eg && (MXeqSR1_R || MYeqSR1_R) ||
updSR0_Eg && (MXeqSR0_R || MYeqSR0_R));
assign #`da Dummy_R = Prderr_Eg | Prderr_Cg | Long_Eg | Long_Cg;
always @ (posedge DSPCLK or posedge PPclr) begin
if (PPclr) Dummy_E <= #`db 1'b0;
else if (GO_E) Dummy_E <= #`db Dummy_R;
end
always @ (posedge DSPCLK or posedge PPclr) begin
if (PPclr) begin
Prderr_Cg <= #`db 1'b0;
Dummy_C <= #`db 1'b0;
end
else
if (GO_C) begin
Prderr_Cg <= #`db Prderr_Eg;
Dummy_C <= #`db Dummy_E;
end
end
assign #`da CKtrue = !Usecond_E || Ctrue;
assign #`da EX_en = !Dummy_E;
assign #`da EX_enc = !Dummy_E && CKtrue;
assign #`da MFPSQ_R = |{MFMSTAT_R, MFSSTAT_R, MFIMASK_R,
MFICNTL_R, MFCNTR_R, MFtoppcs_R,
MFPMOVL_R, MFDMOVL_R, imm16_R,
imm14_R, MFIDR_R};
assign #`da MFDAG1_R = |{MFIreg_R[3:0], MFLreg_R[3:0],
MFMreg_R[3:0], MFPX_R};
assign #`da MFDAG2_R = |{MFIreg_R[7:4], MFLreg_R[7:4],
MFMreg_R[7:4]};
assign #`da MFALU_R = |{MFASTAT_R, MFAX0_R, MFAX1_R, MFAY0_R,
MFAY1_R, MFAR_R};
assign #`da MFMAC_R = |{MFMX0_R, MFMX1_R, MFMY0_R, MFMY1_R,
MFMR0_R, MFMR1_R, MFMR2_R};
assign #`da MFSHT_R = |{MFSI_R, MFSB_R, MFSE_R, MFSR0_R, MFSR1_R};
assign #`da MFSPT_R = |{MFRX0_R, MFRX1_R, MFTX0_R, MFTX1_R};
assign #`da MFPSQ_E = !redoSTI_h && MFPSQ_Ei;
assign #`da MFSPT_E = !redoSTI_h && MFSPT_Ei;
assign #`da MFDAG1_E = !redoSTI_h && MFDAG1_Ei;
assign #`da MFDAG2_E = !redoSTI_h && MFDAG2_Ei;
assign #`da MFALU_E = !redoSTI_h && MFALU_Ei;
assign #`da MFMAC_E = !redoSTI_h && MFMAC_Ei;
assign #`da MFSHT_E = !redoSTI_h && MFSHT_Ei;
assign #`da pMFALU_E = !redoSTI_h && pMFALU_Ei;
assign #`da pMFMAC_E = !redoSTI_h && pMFMAC_Ei;
assign #`da pMFSHT_E = !redoSTI_h && pMFSHT_Ei;
always @(posedge DSPCLK or posedge PPclr) begin
if (PPclr) begin
MFPSQ_Ei <= #`db 1'b0;
MFSPT_Ei <= #`db 1'b0;
MFDAG1_Ei <= #`db 1'b0;
MFDAG2_Ei <= #`db 1'b0;
MFALU_Ei <= #`db 1'b0;
MFMAC_Ei <= #`db 1'b0;
MFSHT_Ei <= #`db 1'b0;
pMFALU_Ei <= #`db 1'b0;
pMFMAC_Ei <= #`db 1'b0;
pMFSHT_Ei <= #`db 1'b0;
end
else if (GO_E) begin
MFPSQ_Ei <= #`db MFPSQ_R;
MFSPT_Ei <= #`db MFSPT_R;
MFDAG1_Ei <= #`db MFDAG1_R;
MFDAG2_Ei <= #`db MFDAG2_R;
MFALU_Ei <= #`db MFALU_R && !mtPMD_R;
MFMAC_Ei <= #`db MFMAC_R && !mtPMD_R ;
MFSHT_Ei <= #`db MFSHT_R && !mtPMD_R;
pMFALU_Ei <= #`db MFALU_R && mtPMD_R;
pMFMAC_Ei <= #`db MFMAC_R && mtPMD_R;
pMFSHT_Ei <= #`db MFSHT_R && mtPMD_R;
end
end
always @(posedge DSPCLK) begin
if (PPclr) begin
MFPSQ_Ci <= #`db 1'b0;
MFSPT_Ci <= #`db 1'b0;
MFDAG1_Ci <= #`db 1'b0;
MFDAG2_Ci <= #`db 1'b0;
MFALU_Ci <= #`db 1'b0;
MFMAC_Ci <= #`db 1'b0;
MFSHT_Ci <= #`db 1'b0;
pMFALU_Ci <= #`db 1'b0;
pMFMAC_Ci <= #`db 1'b0;
pMFSHT_Ci <= #`db 1'b0;
end
else if (GO_C) begin
MFPSQ_Ci <= #`db MFPSQ_Ei;
MFSPT_Ci <= #`db MFSPT_Ei;
MFDAG1_Ci <= #`db MFDAG1_Ei;
MFDAG2_Ci <= #`db MFDAG2_Ei;
MFALU_Ci <= #`db MFALU_Ei;
MFMAC_Ci <= #`db MFMAC_Ei;
MFSHT_Ci <= #`db MFSHT_Ei;
pMFALU_Ci <= #`db pMFALU_Ei;
pMFMAC_Ci <= #`db pMFMAC_Ei;
pMFSHT_Ci <= #`db pMFSHT_Ei;
end
end
always @(posedge DSPCLK) begin
if (GO_E) begin
MFMSTAT_E <= #`db MFMSTAT_R;
MFSSTAT_E <= #`db MFSSTAT_R;
MFIMASK_E <= #`db MFIMASK_R;
MFICNTL_E <= #`db MFICNTL_R;
MFCNTR_E <= #`db MFCNTR_R;
imm16_E <= #`db imm16_R;
imm14_E <= #`db imm14_R;
MFRX0_E <= #`db MFRX0_R;
MFTX0_E <= #`db MFTX0_R;
MFRX1_E <= #`db MFRX1_R;
MFTX1_E <= #`db MFTX1_R;
end
end
always @(posedge DSPCLK) begin
if (GO_E) begin
MFASTAT_E <= #`db MFASTAT_R;
MFAX0_E <= #`db MFAX0_R;
MFAX1_E <= #`db MFAX1_R;
MFAY0_E <= #`db MFAY0_R;
MFAY1_E <= #`db MFAY1_R;
MFAR_E <= #`db MFAR_R;
MFMX0_E <= #`db MFMX0_R;
MFMX1_E <= #`db MFMX1_R;
MFMY0_E <= #`db MFMY0_R;
MFMY1_E <= #`db MFMY1_R;
MFMR0_E <= #`db MFMR0_R;
MFMR1_E <= #`db MFMR1_R;
MFMR2_E <= #`db MFMR2_R;
MFSI_E <= #`db MFSI_R;
MFSB_E <= #`db MFSB_R;
MFSE_E <= #`db MFSE_R;
MFSR0_E <= #`db MFSR0_R;
MFSR1_E <= #`db MFSR1_R;
MFIreg_E[7:0] <= #`db MFIreg_R[7:0];
MFLreg_E[7:0] <= #`db MFLreg_R[7:0];
MFMreg_E[7:0] <= #`db MFMreg_R[7:0];
MFIDR_E <= #`db MFIDR_R;
MFPMOVL_E <= #`db MFPMOVL_R;
MFDMOVL_E <= #`db MFDMOVL_R;
end
end
always @(posedge DSPCLK) begin
if (PPclr_h) begin
Usecond_E <= #`db 1'b0;
MTMSTAT_Eg <= #`db 1'b0;
MTIMASK_Eg <= #`db 1'b0;
MTICNTL_Eg <= #`db 1'b0;
MTCNTR_Eg <= #`db 1'b0;
MTIFC_Eg <= #`db 1'b0;
MTOWRCNTR_Eg <= #`db 1'b0;
MTtoppcs_Eg <= #`db 1'b0;
MFtoppcs_Eg <= #`db 1'b0;
Modctl_Eg <= #`db 1'b0;
Stkctl_Eg <= #`db 1'b0;
DU_Eg <= #`db 1'b0;
MpopLP_Eg <= #`db 1'b0;
Nseq_Ed <= #`db 1'b0;
Nrti_Ed <= #`db 1'b0;
RET_Ed <= #`db 1'b0;
BR_Ed <= #`db 1'b0;
Call_Ed <= #`db 1'b0;
RTI_Ed <= #`db 1'b0;
RTS_Ed <= #`db 1'b0;
IDLE_Eg <= #`db 1'b0;
MACdep_Eg <= #`db 1'b0;
MTRX0_E <= #`db 1'b0;
MTTX0_E <= #`db 1'b0;
MTRX1_E <= #`db 1'b0;
MTTX1_E <= #`db 1'b0;
end
else if (GO_E) begin
Usecond_E <= #`db Usecond_R;
MTMSTAT_Eg <= #`db MTMSTAT_R && !Dummy_R;
MTIMASK_Eg <= #`db MTIMASK_R && !Dummy_R;
MTICNTL_Eg <= #`db MTICNTL_R && !Dummy_R;
MTCNTR_Eg <= #`db MTCNTR_R && !Dummy_R;
MTIFC_Eg <= #`db MTIFC_R && !Dummy_R;
MTOWRCNTR_Eg <= #`db MTOWRCNTR_R && !Dummy_R;
MTtoppcs_Eg <= #`db MTtoppcs_R && !Dummy_R;
MFtoppcs_Eg <= #`db MFtoppcs_R && !Dummy_R;
Modctl_Eg <= #`db Modctl_R && !Dummy_R;
Stkctl_Eg <= #`db Stkctl_R && !Dummy_R;
DU_Eg <= #`db DU_R && !Dummy_R;
MpopLP_Eg <= #`db MpopLP_R && !Dummy_R;
Nseq_Ed <= #`db Nseq_R && !Dummy_R;
Nrti_Ed <= #`db Nrti_R && !Dummy_R;
RET_Ed <= #`db RET_R && !Dummy_R;
BR_Ed <= #`db BR_R && !Dummy_R;
Call_Ed <= #`db Call_R && !Dummy_R;
RTI_Ed <= #`db RTI_R && !Dummy_R;
RTS_Ed <= #`db RTS_R && !Dummy_R;
IDLE_Eg <= #`db IDLE_R && !Dummy_R;
MACdep_Eg <= #`db MACdep_Rg;
MTRX0_E <= #`db MTRX0_R;
MTTX0_E <= #`db MTTX0_R;
MTRX1_E <= #`db MTRX1_R;
MTTX1_E <= #`db MTTX1_R;
end
end
always @(posedge DSPCLK) begin
if (PPclr_h) begin
ALUop_E <= #`db 1'b0;
updAR_E <= #`db 1'b0;
updAF_E <= #`db 1'b0;
DIVQ_E <= #`db 1'b0;
DIVS_E <= #`db 1'b0;
MTAX0_E <= #`db 1'b0;
MTAX1_E <= #`db 1'b0;
MTAY0_E <= #`db 1'b0;
MTAY1_E <= #`db 1'b0;
MTAR_E <= #`db 1'b0;
MTASTAT_E <= #`db 1'b0;
MACop_E <= #`db 1'b0;
satMR_E <= #`db 1'b0;
updMR_E <= #`db 1'b0;
updMF_E <= #`db 1'b0;
cdAM_E <= #`db 1'b0;
MTMX0_E <= #`db 1'b0;
MTMX1_E <= #`db 1'b0;
MTMY0_E <= #`db 1'b0;
MTMY1_E <= #`db 1'b0;
MTMR0_E <= #`db 1'b0;
MTMR1_E <= #`db 1'b0;
MTMR2_E <= #`db 1'b0;
SHTop_E <= #`db 1'b0;
updSR_E <= #`db 1'b0;
imSHT_E <= #`db 1'b0;
MTSI_E <= #`db 1'b0;
MTSE_E <= #`db 1'b0;
MTSR0_E <= #`db 1'b0;
MTSR1_E <= #`db 1'b0;
MTSB_E <= #`db 1'b0;
accPM_E <= #`db 1'b0;
Double_E <= #`db 1'b0;
Post1_E <= #`db 1'b0;
Post2_E <= #`db 1'b0;
MTIreg_E[7:0] <= #`db 8'b0;
MTLreg_E[7:0] <= #`db 8'b0;
MTMreg_E[7:0] <= #`db 8'b0;
MTIDR_E <= #`db 1'b0;
MTPMOVL_E <= #`db 1'b0;
MTDMOVL_E <= #`db 1'b0;
end
else if (GO_E) begin
ALUop_E <= #`db ALUop_R;
updAR_E <= #`db updAR_R;
updAF_E <= #`db updAF_R;
DIVQ_E <= #`db Typ[23];
DIVS_E <= #`db Typ[24];
MTAX0_E <= #`db MTAX0_R;
MTAX1_E <= #`db MTAX1_R;
MTAY0_E <= #`db MTAY0_R;
MTAY1_E <= #`db MTAY1_R;
MTAR_E <= #`db MTAR_R;
MTASTAT_E <= #`db MTASTAT_R;
MACop_E <= #`db MACop_R;
satMR_E <= #`db satMR_R;
updMR_E <= #`db updMR_R;
updMF_E <= #`db updMF_R;
cdAM_E <= #`db Typ[9];
MTMX0_E <= #`db MTMX0_R;
MTMX1_E <= #`db MTMX1_R;
MTMY0_E <= #`db MTMY0_R;
MTMY1_E <= #`db MTMY1_R;
MTMR0_E <= #`db MTMR0_R;
MTMR1_E <= #`db MTMR1_R;
MTMR2_E <= #`db MTMR2_R;
SHTop_E <= #`db SHTop_R;
updSR_E <= #`db updSR_R;
imSHT_E <= #`db Typ[15];
MTSI_E <= #`db MTSI_R;
MTSE_E <= #`db MTSE_R;
MTSR0_E <= #`db MTSR0_R;
MTSR1_E <= #`db MTSR1_R;
MTSB_E <= #`db MTSB_R;
accPM_E <= #`db Typ[5] || Typ[13];
Double_E <= #`db Double_R;
Post1_E <= #`db Post1_R;
Post2_E <= #`db Post2_R;
MTIreg_E[7:0] <= #`db MTIreg_R[7:0];
MTLreg_E[7:0] <= #`db MTLreg_R[7:0];
MTMreg_E[7:0] <= #`db MTMreg_R[7:0];
MTIDR_E <= #`db MTIDR_R;
MTPMOVL_E <= #`db MTPMOVL_R;
MTDMOVL_E <= #`db MTDMOVL_R;
end
end
always @(posedge DSPCLK) begin
if (PPclr_h) begin
DU_Cg <= #`db 1'b0;
end
else if (GO_C) begin
DU_Cg <= #`db DU_Eg;
end
end
assign #`da nNOP_Eg = !NOP_E && EX_enc;
assign #`da MTIDR_Eg = MTIDR_E && EX_en;
assign #`d0 EXIT_R = Typ[20] && ICE_ST;
assign #`d0 RET_R = Typ[20] && !ICE_ST;
assign #`da RTI_R = Typ[20] && IR[4] && !ICE_ST;
assign #`da RTS_R = Typ[20] && !IR[4] && !ICE_ST;
assign #`d0 IDLE_R = Typ[31] && !IR[4];
assign #`d0 SBP_R = Typ[31] && IR[4] && SBP_EN;
always @(posedge DSPCLK) begin
if (PPclr_h) begin
EXIT_E <= #`db 1'b0;
NOP_E <= #`db 1'b0;
end
else if (GO_E) begin
EXIT_E <= #`db EXIT_R;
NOP_E <= #`db Typ[30];
end
end
wire DAG1_EN, DAG2_EN;
assign DAG1_EN = Typ[1] || (Typ[2] && (!IR[20])) || (Typ[4] && (!IR[20]))
|| (Typ[12] && (!IR[16])) || (Typ[21] && (!IR[4]));
assign DAG2_EN = Typ[1] || (Typ[2] && IR[20]) || (Typ[4] && IR[20])
|| Typ[5] || (Typ[12] && IR[16]) || Typ[13] || (Typ[21] && IR[4]);
assign type9 = Typ[9];
assign DIVQ_R = Typ[23];
assign DIVS_R = Typ[24];
endmodule
|
module DSP_CORE_top (
CMAinx, CM_rd0, CM_rd1, CM_rd2, CM_rd3, CM_rd4, CM_rd5, CM_rd6,
CM_rd7, CM_rdm, CM_wd, DMAinx, DM_rd0, DM_rd1, DM_rd2, DM_rd3,
DM_rd4, DM_rd5, DM_rd6, DM_rd7, DM_rdm, DM_wd, EA_do, ED_do, IAD_do,
PIO_oe, PIO_out, PMAinx, PM_rd0, PM_rd1, PM_rd2, PM_rd3, PM_rd4,
PM_rd5, PM_rd6, PM_rd7, PM_wd, T_EA, T_ED, T_IAD, T_PIOin, T_TMODE,
VC_SI, VC_SO, BGn, BMSn, CLKO, CMSn, CM_cs, CM_oe, CM_web, CMo_cs0,
CMo_cs1, CMo_cs2, CMo_cs3, CMo_cs4, CMo_cs5, CMo_cs6, CMo_cs7,
CMo_oe0, CMo_oe1, CMo_oe2, CMo_oe3, CMo_oe4, CMo_oe5, CMo_oe6,
CMo_oe7, DMSn, DM_cs, DM_oe, DMo_cs0, DMo_cs1, DMo_cs2, DMo_cs3,
DMo_cs4, DMo_cs5, DMo_cs6, DMo_cs7, DMo_oe0, DMo_oe1, DMo_oe2,
DMo_oe3, DMo_oe4, DMo_oe5, DMo_oe6, DMo_oe7, DMo_web, DSPCLK_cm0,
DSPCLK_cm1, DSPCLK_cm2, DSPCLK_dm0, DSPCLK_dm1, DSPCLK_dm2,
DSPCLK_pm0, DSPCLK_pm1, DSPCLK_pm2, EA_oe, ECMA_EN, ECMSn,
ED_oe_14_8, ED_oe_15, ED_oe_7_0, IACKn, IAD_oe, IDo, IDoe, IOSn,
IRFS0, IRFS1, ISCLK0, ISCLK1, ITFS0, ITFS1, PMSn, PM_bdry_sel,
PMo_cs0, PMo_cs1, PMo_cs2, PMo_cs3, PMo_cs4, PMo_cs5, PMo_cs6,
PMo_cs7, PMo_oe0, PMo_oe1, PMo_oe2, PMo_oe3, PMo_oe4, PMo_oe5,
PMo_oe6, PMo_oe7, PMo_web, PWDACK, RDn, RFS0, RFS1, SCLK0, SCLK1,
TCLK, TC_RESET, TC_SHIFT, TC_SI, TC_SO, TC_UPDATE, TD0, TD1,
TEST_CLK, TEST_RST, TFS0, TFS1, T_BMODE, T_BRn, T_CLKI_OSC,
T_CLKI_PLL, T_GOICE, T_IAL, T_ICE_RSTn, T_ICK, T_ID, T_IMS, T_IRDn,
T_IRQ0n, T_IRQ1n, T_IRQ2n, T_IRQE0n, T_IRQE1n, T_IRQL1n, T_ISn,
T_IWRn, T_MMAP, T_PWDn, T_RD0, T_RD1, T_RFS0, T_RFS1, T_RSTn,
T_SCLK0, T_SCLK1, T_Sel_PLL, T_TFS0, T_TFS1, VC_SHIFT, WP_CLK,
WP_SI, WP_SO, WRn, XTALoffn, DSPCLK_insert_buf_i, DSPCLK_insert_buf_o
);
input DSPCLK_insert_buf_i;
output DSPCLK_insert_buf_o;
input [23:0] CM_rd0;
input [23:0] CM_rd1;
input [23:0] CM_rd2;
input [23:0] CM_rd3;
input [23:0] CM_rd4;
input [23:0] CM_rd5;
input [23:0] CM_rd6;
input [23:0] CM_rd7;
input [23:0] CM_rdm;
input [15:0] DM_rd0;
input [15:0] DM_rd1;
input [15:0] DM_rd2;
input [15:0] DM_rd3;
input [15:0] DM_rd4;
input [15:0] DM_rd5;
input [15:0] DM_rd6;
input [15:0] DM_rd7;
input [15:0] DM_rdm;
input [15:0] PM_rd0;
input [15:0] PM_rd1;
input [15:0] PM_rd2;
input [15:0] PM_rd3;
input [15:0] PM_rd4;
input [15:0] PM_rd5;
input [15:0] PM_rd6;
input [15:0] PM_rd7;
input [7:0] T_EA;
input [15:0] T_ED;
input [15:0] T_IAD;
input [11:0] T_PIOin;
input [1:0] T_TMODE;
input [7:0] VC_SI;
input PM_bdry_sel;
input TCLK;
input TC_RESET;
input TC_SHIFT;
input TC_SI;
input TC_UPDATE;
input TEST_CLK;
input TEST_RST;
input T_BMODE;
input T_BRn;
input T_CLKI_OSC;
input T_CLKI_PLL;
input T_GOICE;
input T_IAL;
input T_ICE_RSTn;
input T_ICK;
input T_ID;
input T_IMS;
input T_IRDn;
input T_IRQ0n;
input T_IRQ1n;
input T_IRQ2n;
input T_IRQE0n;
input T_IRQE1n;
input T_IRQL1n;
input T_ISn;
input T_IWRn;
input T_MMAP;
input T_PWDn;
input T_RD0;
input T_RD1;
input T_RFS0;
input T_RFS1;
input T_RSTn;
input T_SCLK0;
input T_SCLK1;
input T_Sel_PLL;
input T_TFS0;
input T_TFS1;
input VC_SHIFT;
input WP_CLK;
input WP_SI;
output [13:0] CMAinx;
output [23:0] CM_wd;
output [13:0] DMAinx;
output [15:0] DM_wd;
output [14:0] EA_do;
output [15:0] ED_do;
output [15:0] IAD_do;
output [11:0] PIO_oe;
output [11:0] PIO_out;
output [13:0] PMAinx;
output [15:0] PM_wd;
output [7:0] VC_SO;
output BGn;
output BMSn;
output CLKO;
output CMSn;
output CM_cs;
output CM_oe;
output CM_web;
output CMo_cs0;
output CMo_cs1;
output CMo_cs2;
output CMo_cs3;
output CMo_cs4;
output CMo_cs5;
output CMo_cs6;
output CMo_cs7;
output CMo_oe0;
output CMo_oe1;
output CMo_oe2;
output CMo_oe3;
output CMo_oe4;
output CMo_oe5;
output CMo_oe6;
output CMo_oe7;
output DMSn;
output DM_cs;
output DM_oe;
output DMo_cs0;
output DMo_cs1;
output DMo_cs2;
output DMo_cs3;
output DMo_cs4;
output DMo_cs5;
output DMo_cs6;
output DMo_cs7;
output DMo_oe0;
output DMo_oe1;
output DMo_oe2;
output DMo_oe3;
output DMo_oe4;
output DMo_oe5;
output DMo_oe6;
output DMo_oe7;
output DMo_web;
output DSPCLK_cm0;
output DSPCLK_cm1;
output DSPCLK_cm2;
output DSPCLK_dm0;
output DSPCLK_dm1;
output DSPCLK_dm2;
output DSPCLK_pm0;
output DSPCLK_pm1;
output DSPCLK_pm2;
output EA_oe;
output ECMA_EN;
output ECMSn;
output ED_oe_14_8;
output ED_oe_15;
output ED_oe_7_0;
output IACKn;
output IAD_oe;
output IDo;
output IDoe;
output IOSn;
output IRFS0;
output IRFS1;
output ISCLK0;
output ISCLK1;
output ITFS0;
output ITFS1;
output PMSn;
output PMo_cs0;
output PMo_cs1;
output PMo_cs2;
output PMo_cs3;
output PMo_cs4;
output PMo_cs5;
output PMo_cs6;
output PMo_cs7;
output PMo_oe0;
output PMo_oe1;
output PMo_oe2;
output PMo_oe3;
output PMo_oe4;
output PMo_oe5;
output PMo_oe6;
output PMo_oe7;
output PMo_web;
output PWDACK;
output RDn;
output RFS0;
output RFS1;
output SCLK0;
output SCLK1;
output TC_SO;
output TD0;
output TD1;
output TFS0;
output TFS1;
output WP_SO;
output WRn;
output XTALoffn;
wire [13:0] core_CMAinx;
wire [23:0] core_CM_rd0;
wire [23:0] core_CM_rd1;
wire [23:0] core_CM_rd2;
wire [23:0] core_CM_rd3;
wire [23:0] core_CM_rd4;
wire [23:0] core_CM_rd5;
wire [23:0] core_CM_rd6;
wire [23:0] core_CM_rd7;
wire [23:0] core_CM_rdm;
wire [23:0] core_CM_wd;
wire [13:0] core_DMAinx;
wire [15:0] core_DM_rd0;
wire [15:0] core_DM_rd1;
wire [15:0] core_DM_rd2;
wire [15:0] core_DM_rd3;
wire [15:0] core_DM_rd4;
wire [15:0] core_DM_rd5;
wire [15:0] core_DM_rd6;
wire [15:0] core_DM_rd7;
wire [15:0] core_DM_rdm;
wire [15:0] core_DM_wd;
wire [14:0] core_EA_do;
wire [15:0] core_ED_do;
wire [15:0] core_IAD_do;
wire [11:0] core_PIO_oe;
wire [11:0] core_PIO_out;
wire [13:0] core_PMAinx;
wire [15:0] core_PM_rd0;
wire [15:0] core_PM_rd1;
wire [15:0] core_PM_rd2;
wire [15:0] core_PM_rd3;
wire [15:0] core_PM_rd4;
wire [15:0] core_PM_rd5;
wire [15:0] core_PM_rd6;
wire [15:0] core_PM_rd7;
wire [15:0] core_PM_wd;
wire [7:0] core_T_EA;
wire [15:0] core_T_ED;
wire [15:0] core_T_IAD;
wire [11:0] core_T_PIOin;
wire [1:0] core_T_TMODE;
wire SCANIN1, SCANIN2, SCANIN3, SCANIN4, SCANIN5, SCANIN6, SCANIN7,
SCANIN8, SCANOUT1, SCANOUT2, SCANOUT3, SCANOUT4, SCANOUT5, SCANOUT6,
SCANOUT7, SCANOUT8, SCAN_ENABLE, SCAN_SHIFT, SCAN_TEST,
VC_SCANMODE, core_BGn, core_BMSn, core_CLKO, core_CMSn, core_CM_cs,
core_CM_oe, core_CM_web, core_CMo_cs0, core_CMo_cs1, core_CMo_cs2,
core_CMo_cs3, core_CMo_cs4, core_CMo_cs5, core_CMo_cs6,
core_CMo_cs7, core_CMo_oe0, core_CMo_oe1, core_CMo_oe2,
core_CMo_oe3, core_CMo_oe4, core_CMo_oe5, core_CMo_oe6,
core_CMo_oe7, core_DMSn, core_DM_cs, core_DM_oe, core_DMo_cs0,
core_DMo_cs1, core_DMo_cs2, core_DMo_cs3, core_DMo_cs4,
core_DMo_cs5, core_DMo_cs6, core_DMo_cs7, core_DMo_oe0,
core_DMo_oe1, core_DMo_oe2, core_DMo_oe3, core_DMo_oe4,
core_DMo_oe5, core_DMo_oe6, core_DMo_oe7, core_DMo_web,
core_DSPCLK_cm0, core_DSPCLK_cm1, core_DSPCLK_cm2, core_DSPCLK_dm0,
core_DSPCLK_dm1, core_DSPCLK_dm2, core_DSPCLK_pm0, core_DSPCLK_pm1,
core_DSPCLK_pm2, core_EA_oe, core_ECMA_EN, core_ECMSn,
core_ED_oe_14_8, core_ED_oe_15, core_ED_oe_7_0, core_IACKn,
core_IAD_oe, core_IDo, core_IDoe, core_IOSn, core_IRFS0, core_IRFS1,
core_ISCLK0, core_ISCLK1, core_ITFS0, core_ITFS1, core_PMSn,
core_PM_bdry_sel, core_PMo_cs0, core_PMo_cs1, core_PMo_cs2,
core_PMo_cs3, core_PMo_cs4, core_PMo_cs5, core_PMo_cs6,
core_PMo_cs7, core_PMo_oe0, core_PMo_oe1, core_PMo_oe2,
core_PMo_oe3, core_PMo_oe4, core_PMo_oe5, core_PMo_oe6,
core_PMo_oe7, core_PMo_web, core_PWDACK, core_RDn, core_RFS0,
core_RFS1, core_SCLK0, core_SCLK1, core_TD0, core_TD1, core_TFS0,
core_TFS1, core_T_BMODE, core_T_BRn, core_T_CLKI_OSC,
core_T_CLKI_PLL, core_T_GOICE, core_T_IAL, core_T_ICE_RSTn,
core_T_ICK, core_T_ID, core_T_IMS, core_T_IRDn, core_T_IRQ0n,
core_T_IRQ1n, core_T_IRQ2n, core_T_IRQE0n, core_T_IRQE1n,
core_T_IRQL1n, core_T_ISn, core_T_IWRn, core_T_MMAP, core_T_PWDn,
core_T_RD0, core_T_RD1, core_T_RFS0, core_T_RFS1, core_T_RSTn,
core_T_SCLK0, core_T_SCLK1, core_T_Sel_PLL, core_T_TFS0,
core_T_TFS1, core_WRn, core_XTALoffn;
//DSP_CORE CORE (
DSP_CORE dsp_core (
.BGn(core_BGn), .BMSn(core_BMSn), .CLKO(core_CLKO), .CMAinx(core_CMAinx),
.CMSn(core_CMSn), .CM_cs(core_CM_cs), .CM_oe(core_CM_oe),
.CM_rd0(core_CM_rd0), .CM_rd1(core_CM_rd1), .CM_rd2(core_CM_rd2),
.CM_rd3(core_CM_rd3), .CM_rd4(core_CM_rd4), .CM_rd5(core_CM_rd5),
.CM_rd6(core_CM_rd6), .CM_rd7(core_CM_rd7), .CM_rdm(core_CM_rdm),
.CM_wd(core_CM_wd), .CM_web(core_CM_web), .CMo_cs0(core_CMo_cs0),
.CMo_cs1(core_CMo_cs1), .CMo_cs2(core_CMo_cs2), .CMo_cs3(core_CMo_cs3),
.CMo_cs4(core_CMo_cs4), .CMo_cs5(core_CMo_cs5), .CMo_cs6(core_CMo_cs6),
.CMo_cs7(core_CMo_cs7), .CMo_oe0(core_CMo_oe0), .CMo_oe1(core_CMo_oe1),
.CMo_oe2(core_CMo_oe2), .CMo_oe3(core_CMo_oe3), .CMo_oe4(core_CMo_oe4),
.CMo_oe5(core_CMo_oe5), .CMo_oe6(core_CMo_oe6), .CMo_oe7(core_CMo_oe7),
.DMAinx(core_DMAinx), .DMSn(core_DMSn), .DM_cs(core_DM_cs),
.DM_oe(core_DM_oe), .DM_rd0(core_DM_rd0), .DM_rd1(core_DM_rd1),
.DM_rd2(core_DM_rd2), .DM_rd3(core_DM_rd3), .DM_rd4(core_DM_rd4),
.DM_rd5(core_DM_rd5), .DM_rd6(core_DM_rd6), .DM_rd7(core_DM_rd7),
.DM_rdm(core_DM_rdm), .DM_wd(core_DM_wd), .DMo_cs0(core_DMo_cs0),
.DMo_cs1(core_DMo_cs1), .DMo_cs2(core_DMo_cs2), .DMo_cs3(core_DMo_cs3),
.DMo_cs4(core_DMo_cs4), .DMo_cs5(core_DMo_cs5), .DMo_cs6(core_DMo_cs6),
.DMo_cs7(core_DMo_cs7), .DMo_oe0(core_DMo_oe0), .DMo_oe1(core_DMo_oe1),
.DMo_oe2(core_DMo_oe2), .DMo_oe3(core_DMo_oe3), .DMo_oe4(core_DMo_oe4),
.DMo_oe5(core_DMo_oe5), .DMo_oe6(core_DMo_oe6), .DMo_oe7(core_DMo_oe7),
.DMo_web(core_DMo_web), .DSPCLK_cm0(core_DSPCLK_cm0),
.DSPCLK_cm1(core_DSPCLK_cm1), .DSPCLK_cm2(core_DSPCLK_cm2),
.DSPCLK_dm0(core_DSPCLK_dm0), .DSPCLK_dm1(core_DSPCLK_dm1),
.DSPCLK_dm2(core_DSPCLK_dm2), .DSPCLK_pm0(core_DSPCLK_pm0),
.DSPCLK_pm1(core_DSPCLK_pm1), .DSPCLK_pm2(core_DSPCLK_pm2),
.EA_do(core_EA_do), .EA_oe(core_EA_oe), .ECMA_EN(core_ECMA_EN),
.ECMSn(core_ECMSn), .ED_do(core_ED_do), .ED_oe_14_8(core_ED_oe_14_8),
.ED_oe_15(core_ED_oe_15), .ED_oe_7_0(core_ED_oe_7_0), .IACKn(core_IACKn),
.IAD_do(core_IAD_do), .IAD_oe(core_IAD_oe), .IDo(core_IDo),
.IDoe(core_IDoe), .IOSn(core_IOSn), .IRFS0(core_IRFS0), .IRFS1(core_IRFS1),
.ISCLK0(core_ISCLK0), .ISCLK1(core_ISCLK1), .ITFS0(core_ITFS0),
.ITFS1(core_ITFS1), .PIO_oe(core_PIO_oe), .PIO_out(core_PIO_out),
.PMAinx(core_PMAinx), .PMSn(core_PMSn), .PM_bdry_sel(core_PM_bdry_sel),
.PM_rd0(core_PM_rd0), .PM_rd1(core_PM_rd1), .PM_rd2(core_PM_rd2),
.PM_rd3(core_PM_rd3), .PM_rd4(core_PM_rd4), .PM_rd5(core_PM_rd5),
.PM_rd6(core_PM_rd6), .PM_rd7(core_PM_rd7), .PM_wd(core_PM_wd),
.PMo_cs0(core_PMo_cs0), .PMo_cs1(core_PMo_cs1), .PMo_cs2(core_PMo_cs2),
.PMo_cs3(core_PMo_cs3), .PMo_cs4(core_PMo_cs4), .PMo_cs5(core_PMo_cs5),
.PMo_cs6(core_PMo_cs6), .PMo_cs7(core_PMo_cs7), .PMo_oe0(core_PMo_oe0),
.PMo_oe1(core_PMo_oe1), .PMo_oe2(core_PMo_oe2), .PMo_oe3(core_PMo_oe3),
.PMo_oe4(core_PMo_oe4), .PMo_oe5(core_PMo_oe5), .PMo_oe6(core_PMo_oe6),
.PMo_oe7(core_PMo_oe7), .PMo_web(core_PMo_web), .PWDACK(core_PWDACK),
.RDn(core_RDn), .RFS0(core_RFS0), .RFS1(core_RFS1), .SCANIN1(SCANIN1),
.SCANIN2(SCANIN2), .SCANIN3(SCANIN3), .SCANIN4(SCANIN4), .SCANIN5(SCANIN5),
.SCANIN6(SCANIN6), .SCANIN7(SCANIN7), .SCANIN8(SCANIN8),
.SCANOUT1(SCANOUT1), .SCANOUT2(SCANOUT2), .SCANOUT3(SCANOUT3),
.SCANOUT4(SCANOUT4), .SCANOUT5(SCANOUT5), .SCANOUT6(SCANOUT6),
.SCANOUT7(SCANOUT7), .SCANOUT8(SCANOUT8), .SCAN_ENABLE(SCAN_ENABLE),
.SCAN_TEST(SCAN_TEST), .SCLK0(core_SCLK0), .SCLK1(core_SCLK1),
.TD0(core_TD0), .TD1(core_TD1), .TFS0(core_TFS0), .TFS1(core_TFS1),
.T_BMODE(core_T_BMODE), .T_BRn(core_T_BRn), .T_CLKI_OSC(core_T_CLKI_OSC),
.T_CLKI_PLL(core_T_CLKI_PLL), .T_EA(core_T_EA), .T_ED(core_T_ED),
.T_GOICE(core_T_GOICE), .T_IAD(core_T_IAD), .T_IAL(core_T_IAL),
.T_ICE_RSTn(core_T_ICE_RSTn), .T_ICK(core_T_ICK), .T_ID(core_T_ID),
.T_IMS(core_T_IMS), .T_IRDn(core_T_IRDn), .T_IRQ0n(core_T_IRQ0n),
.T_IRQ1n(core_T_IRQ1n), .T_IRQ2n(core_T_IRQ2n), .T_IRQE0n(core_T_IRQE0n),
.T_IRQE1n(core_T_IRQE1n), .T_IRQL1n(core_T_IRQL1n), .T_ISn(core_T_ISn),
.T_IWRn(core_T_IWRn), .T_MMAP(core_T_MMAP), .T_PIOin(core_T_PIOin),
.T_PWDn(core_T_PWDn), .T_RD0(core_T_RD0), .T_RD1(core_T_RD1),
.T_RFS0(core_T_RFS0), .T_RFS1(core_T_RFS1), .T_RSTn(core_T_RSTn),
.T_SCLK0(core_T_SCLK0), .T_SCLK1(core_T_SCLK1), .T_Sel_PLL(core_T_Sel_PLL),
.T_TFS0(core_T_TFS0), .T_TFS1(core_T_TFS1), .T_TMODE(core_T_TMODE),
.WRn(core_WRn), .XTALoffn(core_XTALoffn),
.DSPCLK_insert_buf_i(DSPCLK_insert_buf_i),
.DSPCLK_insert_buf_o(DSPCLK_insert_buf_o)
);
DSP_CORE_wrapper WRAPPER (
.BGn(BGn), .BMSn(BMSn), .CLKO(CLKO), .CMAinx(CMAinx), .CMSn(CMSn),
.CM_cs(CM_cs), .CM_oe(CM_oe), .CM_rd0(CM_rd0), .CM_rd1(CM_rd1),
.CM_rd2(CM_rd2), .CM_rd3(CM_rd3), .CM_rd4(CM_rd4), .CM_rd5(CM_rd5),
.CM_rd6(CM_rd6), .CM_rd7(CM_rd7), .CM_rdm(CM_rdm), .CM_wd(CM_wd),
.CM_web(CM_web), .CMo_cs0(CMo_cs0), .CMo_cs1(CMo_cs1), .CMo_cs2(CMo_cs2),
.CMo_cs3(CMo_cs3), .CMo_cs4(CMo_cs4), .CMo_cs5(CMo_cs5), .CMo_cs6(CMo_cs6),
.CMo_cs7(CMo_cs7), .CMo_oe0(CMo_oe0), .CMo_oe1(CMo_oe1), .CMo_oe2(CMo_oe2),
.CMo_oe3(CMo_oe3), .CMo_oe4(CMo_oe4), .CMo_oe5(CMo_oe5), .CMo_oe6(CMo_oe6),
.CMo_oe7(CMo_oe7), .DMAinx(DMAinx), .DMSn(DMSn), .DM_cs(DM_cs),
.DM_oe(DM_oe), .DM_rd0(DM_rd0), .DM_rd1(DM_rd1), .DM_rd2(DM_rd2),
.DM_rd3(DM_rd3), .DM_rd4(DM_rd4), .DM_rd5(DM_rd5), .DM_rd6(DM_rd6),
.DM_rd7(DM_rd7), .DM_rdm(DM_rdm), .DM_wd(DM_wd), .DMo_cs0(DMo_cs0),
.DMo_cs1(DMo_cs1), .DMo_cs2(DMo_cs2), .DMo_cs3(DMo_cs3), .DMo_cs4(DMo_cs4),
.DMo_cs5(DMo_cs5), .DMo_cs6(DMo_cs6), .DMo_cs7(DMo_cs7), .DMo_oe0(DMo_oe0),
.DMo_oe1(DMo_oe1), .DMo_oe2(DMo_oe2), .DMo_oe3(DMo_oe3), .DMo_oe4(DMo_oe4),
.DMo_oe5(DMo_oe5), .DMo_oe6(DMo_oe6), .DMo_oe7(DMo_oe7), .DMo_web(DMo_web),
.DSPCLK_cm0(DSPCLK_cm0), .DSPCLK_cm1(DSPCLK_cm1), .DSPCLK_cm2(DSPCLK_cm2),
.DSPCLK_dm0(DSPCLK_dm0), .DSPCLK_dm1(DSPCLK_dm1), .DSPCLK_dm2(DSPCLK_dm2),
.DSPCLK_pm0(DSPCLK_pm0), .DSPCLK_pm1(DSPCLK_pm1), .DSPCLK_pm2(DSPCLK_pm2),
.EA_do(EA_do), .EA_oe(EA_oe), .ECMA_EN(ECMA_EN), .ECMSn(ECMSn),
.ED_do(ED_do), .ED_oe_14_8(ED_oe_14_8), .ED_oe_15(ED_oe_15),
.ED_oe_7_0(ED_oe_7_0), .IACKn(IACKn), .IAD_do(IAD_do), .IAD_oe(IAD_oe),
.IDo(IDo), .IDoe(IDoe), .IOSn(IOSn), .IRFS0(IRFS0), .IRFS1(IRFS1),
.ISCLK0(ISCLK0), .ISCLK1(ISCLK1), .ITFS0(ITFS0), .ITFS1(ITFS1),
.PIO_oe(PIO_oe), .PIO_out(PIO_out), .PMAinx(PMAinx), .PMSn(PMSn),
.PM_bdry_sel(PM_bdry_sel), .PM_rd0(PM_rd0), .PM_rd1(PM_rd1),
.PM_rd2(PM_rd2), .PM_rd3(PM_rd3), .PM_rd4(PM_rd4), .PM_rd5(PM_rd5),
.PM_rd6(PM_rd6), .PM_rd7(PM_rd7), .PM_wd(PM_wd), .PMo_cs0(PMo_cs0),
.PMo_cs1(PMo_cs1), .PMo_cs2(PMo_cs2), .PMo_cs3(PMo_cs3), .PMo_cs4(PMo_cs4),
.PMo_cs5(PMo_cs5), .PMo_cs6(PMo_cs6), .PMo_cs7(PMo_cs7), .PMo_oe0(PMo_oe0),
.PMo_oe1(PMo_oe1), .PMo_oe2(PMo_oe2), .PMo_oe3(PMo_oe3), .PMo_oe4(PMo_oe4),
.PMo_oe5(PMo_oe5), .PMo_oe6(PMo_oe6), .PMo_oe7(PMo_oe7), .PMo_web(PMo_web),
.PWDACK(PWDACK), .RDn(RDn), .RFS0(RFS0), .RFS1(RFS1), .SCANOUT1(SCANOUT1),
.SCANOUT2(SCANOUT2), .SCANOUT3(SCANOUT3), .SCANOUT4(SCANOUT4),
.SCANOUT5(SCANOUT5), .SCANOUT6(SCANOUT6), .SCANOUT7(SCANOUT7),
.SCANOUT8(SCANOUT8), .SCAN_SHIFT(SCAN_SHIFT), .SCLK0(SCLK0), .SCLK1(SCLK1),
.TCLK(TCLK), .TC_RESET(TC_RESET), .TC_SHIFT(TC_SHIFT), .TC_SI(TC_SI),
.TC_SO(TC_SO), .TC_UPDATE(TC_UPDATE), .TD0(TD0), .TD1(TD1),
.TEST_CLK(TEST_CLK), .TFS0(TFS0), .TFS1(TFS1), .T_BMODE(T_BMODE),
.T_BRn(T_BRn), .T_CLKI_PLL(T_CLKI_PLL), .T_EA(T_EA), .T_ED(T_ED),
.T_GOICE(T_GOICE), .T_IAD(T_IAD), .T_IAL(T_IAL), .T_ICE_RSTn(T_ICE_RSTn),
.T_ID(T_ID), .T_IMS(T_IMS), .T_IRDn(T_IRDn), .T_IRQ0n(T_IRQ0n),
.T_IRQ1n(T_IRQ1n), .T_IRQ2n(T_IRQ2n), .T_IRQE0n(T_IRQE0n),
.T_IRQE1n(T_IRQE1n), .T_IRQL1n(T_IRQL1n), .T_ISn(T_ISn), .T_IWRn(T_IWRn),
.T_MMAP(T_MMAP), .T_PIOin(T_PIOin), .T_PWDn(T_PWDn), .T_RD0(T_RD0),
.T_RD1(T_RD1), .T_RFS0(T_RFS0), .T_RFS1(T_RFS1), .T_Sel_PLL(T_Sel_PLL),
.T_TFS0(T_TFS0), .T_TFS1(T_TFS1), .T_TMODE(T_TMODE),
.VC_SCANMODE(VC_SCANMODE), .VC_SHIFT(VC_SHIFT), .VC_SI(VC_SI),
.VC_SO(VC_SO), .WP_CLK(WP_CLK), .WP_SI(WP_SI), .WP_SO(WP_SO), .WRn(WRn),
.XTALoffn(XTALoffn), .core_BGn(core_BGn), .core_BMSn(core_BMSn),
.core_CLKO(core_CLKO), .core_CMAinx(core_CMAinx), .core_CMSn(core_CMSn),
.core_CM_cs(core_CM_cs), .core_CM_oe(core_CM_oe), .core_CM_rd0(core_CM_rd0),
.core_CM_rd1(core_CM_rd1), .core_CM_rd2(core_CM_rd2),
.core_CM_rd3(core_CM_rd3), .core_CM_rd4(core_CM_rd4),
.core_CM_rd5(core_CM_rd5), .core_CM_rd6(core_CM_rd6),
.core_CM_rd7(core_CM_rd7), .core_CM_rdm(core_CM_rdm),
.core_CM_wd(core_CM_wd), .core_CM_web(core_CM_web),
.core_CMo_cs0(core_CMo_cs0), .core_CMo_cs1(core_CMo_cs1),
.core_CMo_cs2(core_CMo_cs2), .core_CMo_cs3(core_CMo_cs3),
.core_CMo_cs4(core_CMo_cs4), .core_CMo_cs5(core_CMo_cs5),
.core_CMo_cs6(core_CMo_cs6), .core_CMo_cs7(core_CMo_cs7),
.core_CMo_oe0(core_CMo_oe0), .core_CMo_oe1(core_CMo_oe1),
.core_CMo_oe2(core_CMo_oe2), .core_CMo_oe3(core_CMo_oe3),
.core_CMo_oe4(core_CMo_oe4), .core_CMo_oe5(core_CMo_oe5),
.core_CMo_oe6(core_CMo_oe6), .core_CMo_oe7(core_CMo_oe7),
.core_DMAinx(core_DMAinx), .core_DMSn(core_DMSn), .core_DM_cs(core_DM_cs),
.core_DM_oe(core_DM_oe), .core_DM_rd0(core_DM_rd0),
.core_DM_rd1(core_DM_rd1), .core_DM_rd2(core_DM_rd2),
.core_DM_rd3(core_DM_rd3), .core_DM_rd4(core_DM_rd4),
.core_DM_rd5(core_DM_rd5), .core_DM_rd6(core_DM_rd6),
.core_DM_rd7(core_DM_rd7), .core_DM_rdm(core_DM_rdm),
.core_DM_wd(core_DM_wd), .core_DMo_cs0(core_DMo_cs0),
.core_DMo_cs1(core_DMo_cs1), .core_DMo_cs2(core_DMo_cs2),
.core_DMo_cs3(core_DMo_cs3), .core_DMo_cs4(core_DMo_cs4),
.core_DMo_cs5(core_DMo_cs5), .core_DMo_cs6(core_DMo_cs6),
.core_DMo_cs7(core_DMo_cs7), .core_DMo_oe0(core_DMo_oe0),
.core_DMo_oe1(core_DMo_oe1), .core_DMo_oe2(core_DMo_oe2),
.core_DMo_oe3(core_DMo_oe3), .core_DMo_oe4(core_DMo_oe4),
.core_DMo_oe5(core_DMo_oe5), .core_DMo_oe6(core_DMo_oe6),
.core_DMo_oe7(core_DMo_oe7), .core_DMo_web(core_DMo_web),
.core_DSPCLK_cm0(core_DSPCLK_cm0), .core_DSPCLK_cm1(core_DSPCLK_cm1),
.core_DSPCLK_cm2(core_DSPCLK_cm2), .core_DSPCLK_dm0(core_DSPCLK_dm0),
.core_DSPCLK_dm1(core_DSPCLK_dm1), .core_DSPCLK_dm2(core_DSPCLK_dm2),
.core_DSPCLK_pm0(core_DSPCLK_pm0), .core_DSPCLK_pm1(core_DSPCLK_pm1),
.core_DSPCLK_pm2(core_DSPCLK_pm2), .core_EA_do(core_EA_do),
.core_EA_oe(core_EA_oe), .core_ECMA_EN(core_ECMA_EN),
.core_ECMSn(core_ECMSn), .core_ED_do(core_ED_do),
.core_ED_oe_14_8(core_ED_oe_14_8), .core_ED_oe_15(core_ED_oe_15),
.core_ED_oe_7_0(core_ED_oe_7_0), .core_IACKn(core_IACKn),
.core_IAD_do(core_IAD_do), .core_IAD_oe(core_IAD_oe), .core_IDo(core_IDo),
.core_IDoe(core_IDoe), .core_IOSn(core_IOSn), .core_IRFS0(core_IRFS0),
.core_IRFS1(core_IRFS1), .core_ISCLK0(core_ISCLK0),
.core_ISCLK1(core_ISCLK1), .core_ITFS0(core_ITFS0), .core_ITFS1(core_ITFS1),
.core_PIO_oe(core_PIO_oe), .core_PIO_out(core_PIO_out),
.core_PMAinx(core_PMAinx), .core_PMSn(core_PMSn),
.core_PM_bdry_sel(core_PM_bdry_sel), .core_PM_rd0(core_PM_rd0),
.core_PM_rd1(core_PM_rd1), .core_PM_rd2(core_PM_rd2),
.core_PM_rd3(core_PM_rd3), .core_PM_rd4(core_PM_rd4),
.core_PM_rd5(core_PM_rd5), .core_PM_rd6(core_PM_rd6),
.core_PM_rd7(core_PM_rd7), .core_PM_wd(core_PM_wd),
.core_PMo_cs0(core_PMo_cs0), .core_PMo_cs1(core_PMo_cs1),
.core_PMo_cs2(core_PMo_cs2), .core_PMo_cs3(core_PMo_cs3),
.core_PMo_cs4(core_PMo_cs4), .core_PMo_cs5(core_PMo_cs5),
.core_PMo_cs6(core_PMo_cs6), .core_PMo_cs7(core_PMo_cs7),
.core_PMo_oe0(core_PMo_oe0), .core_PMo_oe1(core_PMo_oe1),
.core_PMo_oe2(core_PMo_oe2), .core_PMo_oe3(core_PMo_oe3),
.core_PMo_oe4(core_PMo_oe4), .core_PMo_oe5(core_PMo_oe5),
.core_PMo_oe6(core_PMo_oe6), .core_PMo_oe7(core_PMo_oe7),
.core_PMo_web(core_PMo_web), .core_PWDACK(core_PWDACK), .core_RDn(core_RDn),
.core_RFS0(core_RFS0), .core_RFS1(core_RFS1), .core_SCLK0(core_SCLK0),
.core_SCLK1(core_SCLK1), .core_TD0(core_TD0), .core_TD1(core_TD1),
.core_TFS0(core_TFS0), .core_TFS1(core_TFS1), .core_T_BMODE(core_T_BMODE),
.core_T_BRn(core_T_BRn), .core_T_CLKI_PLL(core_T_CLKI_PLL),
.core_T_EA(core_T_EA), .core_T_ED(core_T_ED), .core_T_GOICE(core_T_GOICE),
.core_T_IAD(core_T_IAD), .core_T_IAL(core_T_IAL),
.core_T_ICE_RSTn(core_T_ICE_RSTn), .core_T_ID(core_T_ID),
.core_T_IMS(core_T_IMS), .core_T_IRDn(core_T_IRDn),
.core_T_IRQ0n(core_T_IRQ0n), .core_T_IRQ1n(core_T_IRQ1n),
.core_T_IRQ2n(core_T_IRQ2n), .core_T_IRQE0n(core_T_IRQE0n),
.core_T_IRQE1n(core_T_IRQE1n), .core_T_IRQL1n(core_T_IRQL1n),
.core_T_ISn(core_T_ISn), .core_T_IWRn(core_T_IWRn),
.core_T_MMAP(core_T_MMAP), .core_T_PIOin(core_T_PIOin),
.core_T_PWDn(core_T_PWDn), .core_T_RD0(core_T_RD0), .core_T_RD1(core_T_RD1),
.core_T_RFS0(core_T_RFS0), .core_T_RFS1(core_T_RFS1),
.core_T_Sel_PLL(core_T_Sel_PLL), .core_T_TFS0(core_T_TFS0),
.core_T_TFS1(core_T_TFS1), .core_T_TMODE(core_T_TMODE), .core_WRn(core_WRn),
.core_XTALoffn(core_XTALoffn)
);
assign SCANIN1 = VC_SI[0];
assign SCANIN2 = VC_SI[1];
assign SCANIN3 = VC_SI[2];
assign SCANIN4 = VC_SI[3];
assign SCANIN5 = VC_SI[4];
assign SCANIN6 = VC_SI[5];
assign SCANIN7 = VC_SI[6];
assign SCANIN8 = VC_SI[7];
assign SCAN_ENABLE = SCAN_SHIFT;
assign SCAN_TEST = VC_SCANMODE;
assign core_T_CLKI_OSC = (VC_SCANMODE) ? TEST_CLK : T_CLKI_OSC;
assign core_T_ICK = (VC_SCANMODE) ? TEST_CLK : T_ICK;
assign core_T_RSTn = (VC_SCANMODE) ? ~TEST_RST : T_RSTn;
assign core_T_SCLK0 = (VC_SCANMODE) ? TEST_CLK : T_SCLK0;
assign core_T_SCLK1 = (VC_SCANMODE) ? TEST_CLK : T_SCLK1;
endmodule
module DSP_CORE_wrapper (
CMAinx, CM_rd0, CM_rd1, CM_rd2, CM_rd3, CM_rd4, CM_rd5, CM_rd6,
CM_rd7, CM_rdm, CM_wd, DMAinx, DM_rd0, DM_rd1, DM_rd2, DM_rd3,
DM_rd4, DM_rd5, DM_rd6, DM_rd7, DM_rdm, DM_wd, EA_do, ED_do, IAD_do,
PIO_oe, PIO_out, PMAinx, PM_rd0, PM_rd1, PM_rd2, PM_rd3, PM_rd4,
PM_rd5, PM_rd6, PM_rd7, PM_wd, T_EA, T_ED, T_IAD, T_PIOin, T_TMODE,
VC_SI, VC_SO, core_CMAinx, core_CM_rd0, core_CM_rd1, core_CM_rd2,
core_CM_rd3, core_CM_rd4, core_CM_rd5, core_CM_rd6, core_CM_rd7,
core_CM_rdm, core_CM_wd, core_DMAinx, core_DM_rd0, core_DM_rd1,
core_DM_rd2, core_DM_rd3, core_DM_rd4, core_DM_rd5, core_DM_rd6,
core_DM_rd7, core_DM_rdm, core_DM_wd, core_EA_do, core_ED_do,
core_IAD_do, core_PIO_oe, core_PIO_out, core_PMAinx, core_PM_rd0,
core_PM_rd1, core_PM_rd2, core_PM_rd3, core_PM_rd4, core_PM_rd5,
core_PM_rd6, core_PM_rd7, core_PM_wd, core_T_EA, core_T_ED,
core_T_IAD, core_T_PIOin, core_T_TMODE, BGn, BMSn, CLKO, CMSn,
CM_cs, CM_oe, CM_web, CMo_cs0, CMo_cs1, CMo_cs2, CMo_cs3, CMo_cs4,
CMo_cs5, CMo_cs6, CMo_cs7, CMo_oe0, CMo_oe1, CMo_oe2, CMo_oe3,
CMo_oe4, CMo_oe5, CMo_oe6, CMo_oe7, DMSn, DM_cs, DM_oe, DMo_cs0,
DMo_cs1, DMo_cs2, DMo_cs3, DMo_cs4, DMo_cs5, DMo_cs6, DMo_cs7,
DMo_oe0, DMo_oe1, DMo_oe2, DMo_oe3, DMo_oe4, DMo_oe5, DMo_oe6,
DMo_oe7, DMo_web, DSPCLK_cm0, DSPCLK_cm1, DSPCLK_cm2, DSPCLK_dm0,
DSPCLK_dm1, DSPCLK_dm2, DSPCLK_pm0, DSPCLK_pm1, DSPCLK_pm2, EA_oe,
ECMA_EN, ECMSn, ED_oe_14_8, ED_oe_15, ED_oe_7_0, IACKn, IAD_oe, IDo,
IDoe, IOSn, IRFS0, IRFS1, ISCLK0, ISCLK1, ITFS0, ITFS1, PMSn,
PM_bdry_sel, PMo_cs0, PMo_cs1, PMo_cs2, PMo_cs3, PMo_cs4, PMo_cs5,
PMo_cs6, PMo_cs7, PMo_oe0, PMo_oe1, PMo_oe2, PMo_oe3, PMo_oe4,
PMo_oe5, PMo_oe6, PMo_oe7, PMo_web, PWDACK, RDn, RFS0, RFS1,
SCANOUT1, SCANOUT2, SCANOUT3, SCANOUT4, SCANOUT5, SCANOUT6,
SCANOUT7, SCANOUT8, SCAN_SHIFT, SCLK0, SCLK1, TCLK, TC_RESET,
TC_SHIFT, TC_SI, TC_SO, TC_UPDATE, TD0, TD1, TEST_CLK, TFS0, TFS1,
T_BMODE, T_BRn, T_CLKI_PLL, T_GOICE, T_IAL, T_ICE_RSTn, T_ID, T_IMS,
T_IRDn, T_IRQ0n, T_IRQ1n, T_IRQ2n, T_IRQE0n, T_IRQE1n, T_IRQL1n,
T_ISn, T_IWRn, T_MMAP, T_PWDn, T_RD0, T_RD1, T_RFS0, T_RFS1,
T_Sel_PLL, T_TFS0, T_TFS1, VC_SCANMODE, VC_SHIFT, WP_CLK, WP_SI,
WP_SO, WRn, XTALoffn, core_BGn, core_BMSn, core_CLKO, core_CMSn,
core_CM_cs, core_CM_oe, core_CM_web, core_CMo_cs0, core_CMo_cs1,
core_CMo_cs2, core_CMo_cs3, core_CMo_cs4, core_CMo_cs5,
core_CMo_cs6, core_CMo_cs7, core_CMo_oe0, core_CMo_oe1,
core_CMo_oe2, core_CMo_oe3, core_CMo_oe4, core_CMo_oe5,
core_CMo_oe6, core_CMo_oe7, core_DMSn, core_DM_cs, core_DM_oe,
core_DMo_cs0, core_DMo_cs1, core_DMo_cs2, core_DMo_cs3,
core_DMo_cs4, core_DMo_cs5, core_DMo_cs6, core_DMo_cs7,
core_DMo_oe0, core_DMo_oe1, core_DMo_oe2, core_DMo_oe3,
core_DMo_oe4, core_DMo_oe5, core_DMo_oe6, core_DMo_oe7,
core_DMo_web, core_DSPCLK_cm0, core_DSPCLK_cm1, core_DSPCLK_cm2,
core_DSPCLK_dm0, core_DSPCLK_dm1, core_DSPCLK_dm2, core_DSPCLK_pm0,
core_DSPCLK_pm1, core_DSPCLK_pm2, core_EA_oe, core_ECMA_EN,
core_ECMSn, core_ED_oe_14_8, core_ED_oe_15, core_ED_oe_7_0,
core_IACKn, core_IAD_oe, core_IDo, core_IDoe, core_IOSn, core_IRFS0,
core_IRFS1, core_ISCLK0, core_ISCLK1, core_ITFS0, core_ITFS1,
core_PMSn, core_PM_bdry_sel, core_PMo_cs0, core_PMo_cs1,
core_PMo_cs2, core_PMo_cs3, core_PMo_cs4, core_PMo_cs5,
core_PMo_cs6, core_PMo_cs7, core_PMo_oe0, core_PMo_oe1,
core_PMo_oe2, core_PMo_oe3, core_PMo_oe4, core_PMo_oe5,
core_PMo_oe6, core_PMo_oe7, core_PMo_web, core_PWDACK, core_RDn,
core_RFS0, core_RFS1, core_SCLK0, core_SCLK1, core_TD0, core_TD1,
core_TFS0, core_TFS1, core_T_BMODE, core_T_BRn, core_T_CLKI_PLL,
core_T_GOICE, core_T_IAL, core_T_ICE_RSTn, core_T_ID, core_T_IMS,
core_T_IRDn, core_T_IRQ0n, core_T_IRQ1n, core_T_IRQ2n,
core_T_IRQE0n, core_T_IRQE1n, core_T_IRQL1n, core_T_ISn,
core_T_IWRn, core_T_MMAP, core_T_PWDn, core_T_RD0, core_T_RD1,
core_T_RFS0, core_T_RFS1, core_T_Sel_PLL, core_T_TFS0, core_T_TFS1,
core_WRn, core_XTALoffn
);
input [23:0] CM_rd0;
input [23:0] CM_rd1;
input [23:0] CM_rd2;
input [23:0] CM_rd3;
input [23:0] CM_rd4;
input [23:0] CM_rd5;
input [23:0] CM_rd6;
input [23:0] CM_rd7;
input [23:0] CM_rdm;
input [15:0] DM_rd0;
input [15:0] DM_rd1;
input [15:0] DM_rd2;
input [15:0] DM_rd3;
input [15:0] DM_rd4;
input [15:0] DM_rd5;
input [15:0] DM_rd6;
input [15:0] DM_rd7;
input [15:0] DM_rdm;
input [15:0] PM_rd0;
input [15:0] PM_rd1;
input [15:0] PM_rd2;
input [15:0] PM_rd3;
input [15:0] PM_rd4;
input [15:0] PM_rd5;
input [15:0] PM_rd6;
input [15:0] PM_rd7;
input [7:0] T_EA;
input [15:0] T_ED;
input [15:0] T_IAD;
input [11:0] T_PIOin;
input [1:0] T_TMODE;
input [7:0] VC_SI;
input [13:0] core_CMAinx;
input [23:0] core_CM_wd;
input [13:0] core_DMAinx;
input [15:0] core_DM_wd;
input [14:0] core_EA_do;
input [15:0] core_ED_do;
input [15:0] core_IAD_do;
input [11:0] core_PIO_oe;
input [11:0] core_PIO_out;
input [13:0] core_PMAinx;
input [15:0] core_PM_wd;
input PM_bdry_sel;
input SCANOUT1;
input SCANOUT2;
input SCANOUT3;
input SCANOUT4;
input SCANOUT5;
input SCANOUT6;
input SCANOUT7;
input SCANOUT8;
input TCLK;
input TC_RESET;
input TC_SHIFT;
input TC_SI;
input TC_UPDATE;
input TEST_CLK;
input T_BMODE;
input T_BRn;
input T_CLKI_PLL;
input T_GOICE;
input T_IAL;
input T_ICE_RSTn;
input T_ID;
input T_IMS;
input T_IRDn;
input T_IRQ0n;
input T_IRQ1n;
input T_IRQ2n;
input T_IRQE0n;
input T_IRQE1n;
input T_IRQL1n;
input T_ISn;
input T_IWRn;
input T_MMAP;
input T_PWDn;
input T_RD0;
input T_RD1;
input T_RFS0;
input T_RFS1;
input T_Sel_PLL;
input T_TFS0;
input T_TFS1;
input VC_SHIFT;
input WP_CLK;
input WP_SI;
input core_BGn;
input core_BMSn;
input core_CLKO;
input core_CMSn;
input core_CM_cs;
input core_CM_oe;
input core_CM_web;
input core_CMo_cs0;
input core_CMo_cs1;
input core_CMo_cs2;
input core_CMo_cs3;
input core_CMo_cs4;
input core_CMo_cs5;
input core_CMo_cs6;
input core_CMo_cs7;
input core_CMo_oe0;
input core_CMo_oe1;
input core_CMo_oe2;
input core_CMo_oe3;
input core_CMo_oe4;
input core_CMo_oe5;
input core_CMo_oe6;
input core_CMo_oe7;
input core_DMSn;
input core_DM_cs;
input core_DM_oe;
input core_DMo_cs0;
input core_DMo_cs1;
input core_DMo_cs2;
input core_DMo_cs3;
input core_DMo_cs4;
input core_DMo_cs5;
input core_DMo_cs6;
input core_DMo_cs7;
input core_DMo_oe0;
input core_DMo_oe1;
input core_DMo_oe2;
input core_DMo_oe3;
input core_DMo_oe4;
input core_DMo_oe5;
input core_DMo_oe6;
input core_DMo_oe7;
input core_DMo_web;
input core_DSPCLK_cm0;
input core_DSPCLK_cm1;
input core_DSPCLK_cm2;
input core_DSPCLK_dm0;
input core_DSPCLK_dm1;
input core_DSPCLK_dm2;
input core_DSPCLK_pm0;
input core_DSPCLK_pm1;
input core_DSPCLK_pm2;
input core_EA_oe;
input core_ECMA_EN;
input core_ECMSn;
input core_ED_oe_14_8;
input core_ED_oe_15;
input core_ED_oe_7_0;
input core_IACKn;
input core_IAD_oe;
input core_IDo;
input core_IDoe;
input core_IOSn;
input core_IRFS0;
input core_IRFS1;
input core_ISCLK0;
input core_ISCLK1;
input core_ITFS0;
input core_ITFS1;
input core_PMSn;
input core_PMo_cs0;
input core_PMo_cs1;
input core_PMo_cs2;
input core_PMo_cs3;
input core_PMo_cs4;
input core_PMo_cs5;
input core_PMo_cs6;
input core_PMo_cs7;
input core_PMo_oe0;
input core_PMo_oe1;
input core_PMo_oe2;
input core_PMo_oe3;
input core_PMo_oe4;
input core_PMo_oe5;
input core_PMo_oe6;
input core_PMo_oe7;
input core_PMo_web;
input core_PWDACK;
input core_RDn;
input core_RFS0;
input core_RFS1;
input core_SCLK0;
input core_SCLK1;
input core_TD0;
input core_TD1;
input core_TFS0;
input core_TFS1;
input core_WRn;
input core_XTALoffn;
output [13:0] CMAinx;
output [23:0] CM_wd;
output [13:0] DMAinx;
output [15:0] DM_wd;
output [14:0] EA_do;
output [15:0] ED_do;
output [15:0] IAD_do;
output [11:0] PIO_oe;
output [11:0] PIO_out;
output [13:0] PMAinx;
output [15:0] PM_wd;
output [7:0] VC_SO;
output [23:0] core_CM_rd0;
output [23:0] core_CM_rd1;
output [23:0] core_CM_rd2;
output [23:0] core_CM_rd3;
output [23:0] core_CM_rd4;
output [23:0] core_CM_rd5;
output [23:0] core_CM_rd6;
output [23:0] core_CM_rd7;
output [23:0] core_CM_rdm;
output [15:0] core_DM_rd0;
output [15:0] core_DM_rd1;
output [15:0] core_DM_rd2;
output [15:0] core_DM_rd3;
output [15:0] core_DM_rd4;
output [15:0] core_DM_rd5;
output [15:0] core_DM_rd6;
output [15:0] core_DM_rd7;
output [15:0] core_DM_rdm;
output [15:0] core_PM_rd0;
output [15:0] core_PM_rd1;
output [15:0] core_PM_rd2;
output [15:0] core_PM_rd3;
output [15:0] core_PM_rd4;
output [15:0] core_PM_rd5;
output [15:0] core_PM_rd6;
output [15:0] core_PM_rd7;
output [7:0] core_T_EA;
output [15:0] core_T_ED;
output [15:0] core_T_IAD;
output [11:0] core_T_PIOin;
output [1:0] core_T_TMODE;
output BGn;
output BMSn;
output CLKO;
output CMSn;
output CM_cs;
output CM_oe;
output CM_web;
output CMo_cs0;
output CMo_cs1;
output CMo_cs2;
output CMo_cs3;
output CMo_cs4;
output CMo_cs5;
output CMo_cs6;
output CMo_cs7;
output CMo_oe0;
output CMo_oe1;
output CMo_oe2;
output CMo_oe3;
output CMo_oe4;
output CMo_oe5;
output CMo_oe6;
output CMo_oe7;
output DMSn;
output DM_cs;
output DM_oe;
output DMo_cs0;
output DMo_cs1;
output DMo_cs2;
output DMo_cs3;
output DMo_cs4;
output DMo_cs5;
output DMo_cs6;
output DMo_cs7;
output DMo_oe0;
output DMo_oe1;
output DMo_oe2;
output DMo_oe3;
output DMo_oe4;
output DMo_oe5;
output DMo_oe6;
output DMo_oe7;
output DMo_web;
output DSPCLK_cm0;
output DSPCLK_cm1;
output DSPCLK_cm2;
output DSPCLK_dm0;
output DSPCLK_dm1;
output DSPCLK_dm2;
output DSPCLK_pm0;
output DSPCLK_pm1;
output DSPCLK_pm2;
output EA_oe;
output ECMA_EN;
output ECMSn;
output ED_oe_14_8;
output ED_oe_15;
output ED_oe_7_0;
output IACKn;
output IAD_oe;
output IDo;
output IDoe;
output IOSn;
output IRFS0;
output IRFS1;
output ISCLK0;
output ISCLK1;
output ITFS0;
output ITFS1;
output PMSn;
output PMo_cs0;
output PMo_cs1;
output PMo_cs2;
output PMo_cs3;
output PMo_cs4;
output PMo_cs5;
output PMo_cs6;
output PMo_cs7;
output PMo_oe0;
output PMo_oe1;
output PMo_oe2;
output PMo_oe3;
output PMo_oe4;
output PMo_oe5;
output PMo_oe6;
output PMo_oe7;
output PMo_web;
output PWDACK;
output RDn;
output RFS0;
output RFS1;
output SCAN_SHIFT;
output SCLK0;
output SCLK1;
output TC_SO;
output TD0;
output TD1;
output TFS0;
output TFS1;
output VC_SCANMODE;
output WP_SO;
output WRn;
output XTALoffn;
output core_PM_bdry_sel;
output core_T_BMODE;
output core_T_BRn;
output core_T_CLKI_PLL;
output core_T_GOICE;
output core_T_IAL;
output core_T_ICE_RSTn;
output core_T_ID;
output core_T_IMS;
output core_T_IRDn;
output core_T_IRQ0n;
output core_T_IRQ1n;
output core_T_IRQ2n;
output core_T_IRQE0n;
output core_T_IRQE1n;
output core_T_IRQL1n;
output core_T_ISn;
output core_T_IWRn;
output core_T_MMAP;
output core_T_PWDn;
output core_T_RD0;
output core_T_RD1;
output core_T_RFS0;
output core_T_RFS1;
output core_T_Sel_PLL;
output core_T_TFS0;
output core_T_TFS1;
wire VC_SO_BYPASS_0, VC_SO_BYPASS_1, VC_SO_BYPASS_2, VC_SO_BYPASS_3,
VC_SO_BYPASS_4, VC_SO_BYPASS_5, VC_SO_BYPASS_6, VC_SO_BYPASS_7,
VC_SO_MAS_IN_0, WP_BP, WP_HOLD_IN, WP_HOLD_OUT, WP_SHIFT,
WP_SO_BYPASS, WP_SO_beforeskew;
DSP_CORE_tcb TCB (
.SCAN_SHIFT(SCAN_SHIFT), .TCLK(TCLK), .TC_RESET(TC_RESET),
.TC_SHIFT(TC_SHIFT), .TC_SI(TC_SI), .TC_SO(TC_SO), .TC_UPDATE(TC_UPDATE),
.VC_SCANMODE(VC_SCANMODE), .VC_SHIFT(VC_SHIFT), .WP_BP(WP_BP),
.WP_HOLD_IN(WP_HOLD_IN), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_bypass_reg VC_SI_BYPASS_0 (
.SI(VC_SI[0]), .SO_BYPASS(VC_SO_BYPASS_0), .TCLK(TEST_CLK)
);
DSP_CORE_vsia_tst_bypass_reg VC_SI_BYPASS_1 (
.SI(VC_SI[1]), .SO_BYPASS(VC_SO_BYPASS_1), .TCLK(TEST_CLK)
);
DSP_CORE_vsia_tst_bypass_reg VC_SI_BYPASS_2 (
.SI(VC_SI[2]), .SO_BYPASS(VC_SO_BYPASS_2), .TCLK(TEST_CLK)
);
DSP_CORE_vsia_tst_bypass_reg VC_SI_BYPASS_3 (
.SI(VC_SI[3]), .SO_BYPASS(VC_SO_BYPASS_3), .TCLK(TEST_CLK)
);
DSP_CORE_vsia_tst_bypass_reg VC_SI_BYPASS_4 (
.SI(VC_SI[4]), .SO_BYPASS(VC_SO_BYPASS_4), .TCLK(TEST_CLK)
);
DSP_CORE_vsia_tst_bypass_reg VC_SI_BYPASS_5 (
.SI(VC_SI[5]), .SO_BYPASS(VC_SO_BYPASS_5), .TCLK(TEST_CLK)
);
DSP_CORE_vsia_tst_bypass_reg VC_SI_BYPASS_6 (
.SI(VC_SI[6]), .SO_BYPASS(VC_SO_BYPASS_6), .TCLK(TEST_CLK)
);
DSP_CORE_vsia_tst_bypass_reg VC_SI_BYPASS_7 (
.SI(VC_SI[7]), .SO_BYPASS(VC_SO_BYPASS_7), .TCLK(TEST_CLK)
);
DSP_CORE_vsia_tst_mas VC_SO_MAS_0 (
.SO(VC_SO[0]), .SO_BYPASS(VC_SO_BYPASS_0), .SO_beforeskew(VC_SO_MAS_IN_0),
.TCLK(TEST_CLK), .WP_BP(WP_BP)
);
DSP_CORE_vsia_tst_mas VC_SO_MAS_1 (
.SO(VC_SO[1]), .SO_BYPASS(VC_SO_BYPASS_1), .SO_beforeskew(SCANOUT2),
.TCLK(TEST_CLK), .WP_BP(WP_BP)
);
DSP_CORE_vsia_tst_mas VC_SO_MAS_2 (
.SO(VC_SO[2]), .SO_BYPASS(VC_SO_BYPASS_2), .SO_beforeskew(SCANOUT3),
.TCLK(TEST_CLK), .WP_BP(WP_BP)
);
DSP_CORE_vsia_tst_mas VC_SO_MAS_3 (
.SO(VC_SO[3]), .SO_BYPASS(VC_SO_BYPASS_3), .SO_beforeskew(SCANOUT4),
.TCLK(TEST_CLK), .WP_BP(WP_BP)
);
DSP_CORE_vsia_tst_mas VC_SO_MAS_4 (
.SO(VC_SO[4]), .SO_BYPASS(VC_SO_BYPASS_4), .SO_beforeskew(SCANOUT5),
.TCLK(TEST_CLK), .WP_BP(WP_BP)
);
DSP_CORE_vsia_tst_mas VC_SO_MAS_5 (
.SO(VC_SO[5]), .SO_BYPASS(VC_SO_BYPASS_5), .SO_beforeskew(SCANOUT6),
.TCLK(TEST_CLK), .WP_BP(WP_BP)
);
DSP_CORE_vsia_tst_mas VC_SO_MAS_6 (
.SO(VC_SO[6]), .SO_BYPASS(VC_SO_BYPASS_6), .SO_beforeskew(SCANOUT7),
.TCLK(TEST_CLK), .WP_BP(WP_BP)
);
DSP_CORE_vsia_tst_mas VC_SO_MAS_7 (
.SO(VC_SO[7]), .SO_BYPASS(VC_SO_BYPASS_7), .SO_beforeskew(SCANOUT8),
.TCLK(TEST_CLK), .WP_BP(WP_BP)
);
DSP_CORE_wpreg WPREG (
.BGn(BGn), .BMSn(BMSn), .CLKO(CLKO), .CMAinx(CMAinx), .CMSn(CMSn),
.CM_cs(CM_cs), .CM_oe(CM_oe), .CM_rd0(CM_rd0), .CM_rd1(CM_rd1),
.CM_rd2(CM_rd2), .CM_rd3(CM_rd3), .CM_rd4(CM_rd4), .CM_rd5(CM_rd5),
.CM_rd6(CM_rd6), .CM_rd7(CM_rd7), .CM_rdm(CM_rdm), .CM_wd(CM_wd),
.CM_web(CM_web), .CMo_cs0(CMo_cs0), .CMo_cs1(CMo_cs1), .CMo_cs2(CMo_cs2),
.CMo_cs3(CMo_cs3), .CMo_cs4(CMo_cs4), .CMo_cs5(CMo_cs5), .CMo_cs6(CMo_cs6),
.CMo_cs7(CMo_cs7), .CMo_oe0(CMo_oe0), .CMo_oe1(CMo_oe1), .CMo_oe2(CMo_oe2),
.CMo_oe3(CMo_oe3), .CMo_oe4(CMo_oe4), .CMo_oe5(CMo_oe5), .CMo_oe6(CMo_oe6),
.CMo_oe7(CMo_oe7), .DMAinx(DMAinx), .DMSn(DMSn), .DM_cs(DM_cs),
.DM_oe(DM_oe), .DM_rd0(DM_rd0), .DM_rd1(DM_rd1), .DM_rd2(DM_rd2),
.DM_rd3(DM_rd3), .DM_rd4(DM_rd4), .DM_rd5(DM_rd5), .DM_rd6(DM_rd6),
.DM_rd7(DM_rd7), .DM_rdm(DM_rdm), .DM_wd(DM_wd), .DMo_cs0(DMo_cs0),
.DMo_cs1(DMo_cs1), .DMo_cs2(DMo_cs2), .DMo_cs3(DMo_cs3), .DMo_cs4(DMo_cs4),
.DMo_cs5(DMo_cs5), .DMo_cs6(DMo_cs6), .DMo_cs7(DMo_cs7), .DMo_oe0(DMo_oe0),
.DMo_oe1(DMo_oe1), .DMo_oe2(DMo_oe2), .DMo_oe3(DMo_oe3), .DMo_oe4(DMo_oe4),
.DMo_oe5(DMo_oe5), .DMo_oe6(DMo_oe6), .DMo_oe7(DMo_oe7), .DMo_web(DMo_web),
.DSPCLK_cm0(DSPCLK_cm0), .DSPCLK_cm1(DSPCLK_cm1), .DSPCLK_cm2(DSPCLK_cm2),
.DSPCLK_dm0(DSPCLK_dm0), .DSPCLK_dm1(DSPCLK_dm1), .DSPCLK_dm2(DSPCLK_dm2),
.DSPCLK_pm0(DSPCLK_pm0), .DSPCLK_pm1(DSPCLK_pm1), .DSPCLK_pm2(DSPCLK_pm2),
.EA_do(EA_do), .EA_oe(EA_oe), .ECMA_EN(ECMA_EN), .ECMSn(ECMSn),
.ED_do(ED_do), .ED_oe_14_8(ED_oe_14_8), .ED_oe_15(ED_oe_15),
.ED_oe_7_0(ED_oe_7_0), .IACKn(IACKn), .IAD_do(IAD_do), .IAD_oe(IAD_oe),
.IDo(IDo), .IDoe(IDoe), .IOSn(IOSn), .IRFS0(IRFS0), .IRFS1(IRFS1),
.ISCLK0(ISCLK0), .ISCLK1(ISCLK1), .ITFS0(ITFS0), .ITFS1(ITFS1),
.PIO_oe(PIO_oe), .PIO_out(PIO_out), .PMAinx(PMAinx), .PMSn(PMSn),
.PM_bdry_sel(PM_bdry_sel), .PM_rd0(PM_rd0), .PM_rd1(PM_rd1),
.PM_rd2(PM_rd2), .PM_rd3(PM_rd3), .PM_rd4(PM_rd4), .PM_rd5(PM_rd5),
.PM_rd6(PM_rd6), .PM_rd7(PM_rd7), .PM_wd(PM_wd), .PMo_cs0(PMo_cs0),
.PMo_cs1(PMo_cs1), .PMo_cs2(PMo_cs2), .PMo_cs3(PMo_cs3), .PMo_cs4(PMo_cs4),
.PMo_cs5(PMo_cs5), .PMo_cs6(PMo_cs6), .PMo_cs7(PMo_cs7), .PMo_oe0(PMo_oe0),
.PMo_oe1(PMo_oe1), .PMo_oe2(PMo_oe2), .PMo_oe3(PMo_oe3), .PMo_oe4(PMo_oe4),
.PMo_oe5(PMo_oe5), .PMo_oe6(PMo_oe6), .PMo_oe7(PMo_oe7), .PMo_web(PMo_web),
.PWDACK(PWDACK), .RDn(RDn), .RFS0(RFS0), .RFS1(RFS1), .SCLK0(SCLK0),
.SCLK1(SCLK1), .TD0(TD0), .TD1(TD1), .TFS0(TFS0), .TFS1(TFS1),
.T_BMODE(T_BMODE), .T_BRn(T_BRn), .T_CLKI_PLL(T_CLKI_PLL), .T_EA(T_EA),
.T_ED(T_ED), .T_GOICE(T_GOICE), .T_IAD(T_IAD), .T_IAL(T_IAL),
.T_ICE_RSTn(T_ICE_RSTn), .T_ID(T_ID), .T_IMS(T_IMS), .T_IRDn(T_IRDn),
.T_IRQ0n(T_IRQ0n), .T_IRQ1n(T_IRQ1n), .T_IRQ2n(T_IRQ2n),
.T_IRQE0n(T_IRQE0n), .T_IRQE1n(T_IRQE1n), .T_IRQL1n(T_IRQL1n),
.T_ISn(T_ISn), .T_IWRn(T_IWRn), .T_MMAP(T_MMAP), .T_PIOin(T_PIOin),
.T_PWDn(T_PWDn), .T_RD0(T_RD0), .T_RD1(T_RD1), .T_RFS0(T_RFS0),
.T_RFS1(T_RFS1), .T_Sel_PLL(T_Sel_PLL), .T_TFS0(T_TFS0), .T_TFS1(T_TFS1),
.T_TMODE(T_TMODE), .WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN),
.WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT), .WP_SI(WP_SI),
.WP_SO_beforeskew(WP_SO_beforeskew), .WRn(WRn), .XTALoffn(XTALoffn),
.core_BGn(core_BGn), .core_BMSn(core_BMSn), .core_CLKO(core_CLKO),
.core_CMAinx(core_CMAinx), .core_CMSn(core_CMSn), .core_CM_cs(core_CM_cs),
.core_CM_oe(core_CM_oe), .core_CM_rd0(core_CM_rd0),
.core_CM_rd1(core_CM_rd1), .core_CM_rd2(core_CM_rd2),
.core_CM_rd3(core_CM_rd3), .core_CM_rd4(core_CM_rd4),
.core_CM_rd5(core_CM_rd5), .core_CM_rd6(core_CM_rd6),
.core_CM_rd7(core_CM_rd7), .core_CM_rdm(core_CM_rdm),
.core_CM_wd(core_CM_wd), .core_CM_web(core_CM_web),
.core_CMo_cs0(core_CMo_cs0), .core_CMo_cs1(core_CMo_cs1),
.core_CMo_cs2(core_CMo_cs2), .core_CMo_cs3(core_CMo_cs3),
.core_CMo_cs4(core_CMo_cs4), .core_CMo_cs5(core_CMo_cs5),
.core_CMo_cs6(core_CMo_cs6), .core_CMo_cs7(core_CMo_cs7),
.core_CMo_oe0(core_CMo_oe0), .core_CMo_oe1(core_CMo_oe1),
.core_CMo_oe2(core_CMo_oe2), .core_CMo_oe3(core_CMo_oe3),
.core_CMo_oe4(core_CMo_oe4), .core_CMo_oe5(core_CMo_oe5),
.core_CMo_oe6(core_CMo_oe6), .core_CMo_oe7(core_CMo_oe7),
.core_DMAinx(core_DMAinx), .core_DMSn(core_DMSn), .core_DM_cs(core_DM_cs),
.core_DM_oe(core_DM_oe), .core_DM_rd0(core_DM_rd0),
.core_DM_rd1(core_DM_rd1), .core_DM_rd2(core_DM_rd2),
.core_DM_rd3(core_DM_rd3), .core_DM_rd4(core_DM_rd4),
.core_DM_rd5(core_DM_rd5), .core_DM_rd6(core_DM_rd6),
.core_DM_rd7(core_DM_rd7), .core_DM_rdm(core_DM_rdm),
.core_DM_wd(core_DM_wd), .core_DMo_cs0(core_DMo_cs0),
.core_DMo_cs1(core_DMo_cs1), .core_DMo_cs2(core_DMo_cs2),
.core_DMo_cs3(core_DMo_cs3), .core_DMo_cs4(core_DMo_cs4),
.core_DMo_cs5(core_DMo_cs5), .core_DMo_cs6(core_DMo_cs6),
.core_DMo_cs7(core_DMo_cs7), .core_DMo_oe0(core_DMo_oe0),
.core_DMo_oe1(core_DMo_oe1), .core_DMo_oe2(core_DMo_oe2),
.core_DMo_oe3(core_DMo_oe3), .core_DMo_oe4(core_DMo_oe4),
.core_DMo_oe5(core_DMo_oe5), .core_DMo_oe6(core_DMo_oe6),
.core_DMo_oe7(core_DMo_oe7), .core_DMo_web(core_DMo_web),
.core_DSPCLK_cm0(core_DSPCLK_cm0), .core_DSPCLK_cm1(core_DSPCLK_cm1),
.core_DSPCLK_cm2(core_DSPCLK_cm2), .core_DSPCLK_dm0(core_DSPCLK_dm0),
.core_DSPCLK_dm1(core_DSPCLK_dm1), .core_DSPCLK_dm2(core_DSPCLK_dm2),
.core_DSPCLK_pm0(core_DSPCLK_pm0), .core_DSPCLK_pm1(core_DSPCLK_pm1),
.core_DSPCLK_pm2(core_DSPCLK_pm2), .core_EA_do(core_EA_do),
.core_EA_oe(core_EA_oe), .core_ECMA_EN(core_ECMA_EN),
.core_ECMSn(core_ECMSn), .core_ED_do(core_ED_do),
.core_ED_oe_14_8(core_ED_oe_14_8), .core_ED_oe_15(core_ED_oe_15),
.core_ED_oe_7_0(core_ED_oe_7_0), .core_IACKn(core_IACKn),
.core_IAD_do(core_IAD_do), .core_IAD_oe(core_IAD_oe), .core_IDo(core_IDo),
.core_IDoe(core_IDoe), .core_IOSn(core_IOSn), .core_IRFS0(core_IRFS0),
.core_IRFS1(core_IRFS1), .core_ISCLK0(core_ISCLK0),
.core_ISCLK1(core_ISCLK1), .core_ITFS0(core_ITFS0), .core_ITFS1(core_ITFS1),
.core_PIO_oe(core_PIO_oe), .core_PIO_out(core_PIO_out),
.core_PMAinx(core_PMAinx), .core_PMSn(core_PMSn),
.core_PM_bdry_sel(core_PM_bdry_sel), .core_PM_rd0(core_PM_rd0),
.core_PM_rd1(core_PM_rd1), .core_PM_rd2(core_PM_rd2),
.core_PM_rd3(core_PM_rd3), .core_PM_rd4(core_PM_rd4),
.core_PM_rd5(core_PM_rd5), .core_PM_rd6(core_PM_rd6),
.core_PM_rd7(core_PM_rd7), .core_PM_wd(core_PM_wd),
.core_PMo_cs0(core_PMo_cs0), .core_PMo_cs1(core_PMo_cs1),
.core_PMo_cs2(core_PMo_cs2), .core_PMo_cs3(core_PMo_cs3),
.core_PMo_cs4(core_PMo_cs4), .core_PMo_cs5(core_PMo_cs5),
.core_PMo_cs6(core_PMo_cs6), .core_PMo_cs7(core_PMo_cs7),
.core_PMo_oe0(core_PMo_oe0), .core_PMo_oe1(core_PMo_oe1),
.core_PMo_oe2(core_PMo_oe2), .core_PMo_oe3(core_PMo_oe3),
.core_PMo_oe4(core_PMo_oe4), .core_PMo_oe5(core_PMo_oe5),
.core_PMo_oe6(core_PMo_oe6), .core_PMo_oe7(core_PMo_oe7),
.core_PMo_web(core_PMo_web), .core_PWDACK(core_PWDACK), .core_RDn(core_RDn),
.core_RFS0(core_RFS0), .core_RFS1(core_RFS1), .core_SCLK0(core_SCLK0),
.core_SCLK1(core_SCLK1), .core_TD0(core_TD0), .core_TD1(core_TD1),
.core_TFS0(core_TFS0), .core_TFS1(core_TFS1), .core_T_BMODE(core_T_BMODE),
.core_T_BRn(core_T_BRn), .core_T_CLKI_PLL(core_T_CLKI_PLL),
.core_T_EA(core_T_EA), .core_T_ED(core_T_ED), .core_T_GOICE(core_T_GOICE),
.core_T_IAD(core_T_IAD), .core_T_IAL(core_T_IAL),
.core_T_ICE_RSTn(core_T_ICE_RSTn), .core_T_ID(core_T_ID),
.core_T_IMS(core_T_IMS), .core_T_IRDn(core_T_IRDn),
.core_T_IRQ0n(core_T_IRQ0n), .core_T_IRQ1n(core_T_IRQ1n),
.core_T_IRQ2n(core_T_IRQ2n), .core_T_IRQE0n(core_T_IRQE0n),
.core_T_IRQE1n(core_T_IRQE1n), .core_T_IRQL1n(core_T_IRQL1n),
.core_T_ISn(core_T_ISn), .core_T_IWRn(core_T_IWRn),
.core_T_MMAP(core_T_MMAP), .core_T_PIOin(core_T_PIOin),
.core_T_PWDn(core_T_PWDn), .core_T_RD0(core_T_RD0), .core_T_RD1(core_T_RD1),
.core_T_RFS0(core_T_RFS0), .core_T_RFS1(core_T_RFS1),
.core_T_Sel_PLL(core_T_Sel_PLL), .core_T_TFS0(core_T_TFS0),
.core_T_TFS1(core_T_TFS1), .core_T_TMODE(core_T_TMODE), .core_WRn(core_WRn),
.core_XTALoffn(core_XTALoffn)
);
DSP_CORE_vsia_tst_bypass_reg WP_SI_BYPASS (
.SI(WP_SI), .SO_BYPASS(WP_SO_BYPASS), .TCLK(WP_CLK)
);
DSP_CORE_vsia_tst_mas WP_SO_MAS (
.SO(WP_SO), .SO_BYPASS(WP_SO_BYPASS), .SO_beforeskew(WP_SO_beforeskew),
.TCLK(WP_CLK), .WP_BP(WP_BP)
);
assign VC_SO_MAS_IN_0 = SCANOUT1;
endmodule
module DSP_CORE_tcb (
SCAN_SHIFT, TCLK, TC_RESET, TC_SHIFT, TC_SI, TC_SO, TC_UPDATE,
VC_SCANMODE, VC_SHIFT, WP_BP, WP_HOLD_IN, WP_HOLD_OUT, WP_SHIFT
);
input TCLK;
input TC_RESET;
input TC_SHIFT;
input TC_SI;
input TC_UPDATE;
input VC_SHIFT;
output SCAN_SHIFT;
output TC_SO;
output VC_SCANMODE;
output WP_BP;
output WP_HOLD_IN;
output WP_HOLD_OUT;
output WP_SHIFT;
wire WP_SHIFTMODE, tcb_s_0, tcb_s_1, tcb_s_2, tcb_s_3, tcb_s_4, tcb_s_5;
DSP_CORE_vsia_tst_antiskew TC_SO_antiskew (
.SI(tcb_s_5), .SO(TC_SO), .TCLK(TCLK)
);
DSP_CORE_vsia_tst_tcb_cell tcb_TCB_VC_SCANMODE (
.DO(VC_SCANMODE), .SI(tcb_s_4), .SO(tcb_s_5), .TCLK(TCLK),
.TC_RESET(TC_RESET), .TC_SHIFT(TC_SHIFT), .TC_UPDATE(TC_UPDATE)
);
DSP_CORE_vsia_tst_tcb_cell tcb_TCB_WP_BP (
.DO(WP_BP), .SI(tcb_s_2), .SO(tcb_s_3), .TCLK(TCLK), .TC_RESET(TC_RESET),
.TC_SHIFT(TC_SHIFT), .TC_UPDATE(TC_UPDATE)
);
DSP_CORE_vsia_tst_tcb_cell tcb_TCB_WP_HOLD_IN (
.DO(WP_HOLD_IN), .SI(tcb_s_0), .SO(tcb_s_1), .TCLK(TCLK),
.TC_RESET(TC_RESET), .TC_SHIFT(TC_SHIFT), .TC_UPDATE(TC_UPDATE)
);
DSP_CORE_vsia_tst_tcb_cell tcb_TCB_WP_HOLD_OUT (
.DO(WP_HOLD_OUT), .SI(tcb_s_1), .SO(tcb_s_2), .TCLK(TCLK),
.TC_RESET(TC_RESET), .TC_SHIFT(TC_SHIFT), .TC_UPDATE(TC_UPDATE)
);
DSP_CORE_vsia_tst_tcb_cell tcb_TCB_WP_SHIFTMODE (
.DO(WP_SHIFTMODE), .SI(tcb_s_3), .SO(tcb_s_4), .TCLK(TCLK),
.TC_RESET(TC_RESET), .TC_SHIFT(TC_SHIFT), .TC_UPDATE(TC_UPDATE)
);
assign SCAN_SHIFT = VC_SCANMODE & VC_SHIFT;
assign WP_SHIFT = WP_SHIFTMODE & VC_SHIFT;
assign tcb_s_0 = TC_SI;
endmodule
module DSP_CORE_wpreg (
CMAinx, CM_rd0, CM_rd1, CM_rd2, CM_rd3, CM_rd4, CM_rd5, CM_rd6,
CM_rd7, CM_rdm, CM_wd, DMAinx, DM_rd0, DM_rd1, DM_rd2, DM_rd3,
DM_rd4, DM_rd5, DM_rd6, DM_rd7, DM_rdm, DM_wd, EA_do, ED_do, IAD_do,
PIO_oe, PIO_out, PMAinx, PM_rd0, PM_rd1, PM_rd2, PM_rd3, PM_rd4,
PM_rd5, PM_rd6, PM_rd7, PM_wd, T_EA, T_ED, T_IAD, T_PIOin, T_TMODE,
core_CMAinx, core_CM_rd0, core_CM_rd1, core_CM_rd2, core_CM_rd3,
core_CM_rd4, core_CM_rd5, core_CM_rd6, core_CM_rd7, core_CM_rdm,
core_CM_wd, core_DMAinx, core_DM_rd0, core_DM_rd1, core_DM_rd2,
core_DM_rd3, core_DM_rd4, core_DM_rd5, core_DM_rd6, core_DM_rd7,
core_DM_rdm, core_DM_wd, core_EA_do, core_ED_do, core_IAD_do,
core_PIO_oe, core_PIO_out, core_PMAinx, core_PM_rd0, core_PM_rd1,
core_PM_rd2, core_PM_rd3, core_PM_rd4, core_PM_rd5, core_PM_rd6,
core_PM_rd7, core_PM_wd, core_T_EA, core_T_ED, core_T_IAD,
core_T_PIOin, core_T_TMODE, BGn, BMSn, CLKO, CMSn, CM_cs, CM_oe,
CM_web, CMo_cs0, CMo_cs1, CMo_cs2, CMo_cs3, CMo_cs4, CMo_cs5,
CMo_cs6, CMo_cs7, CMo_oe0, CMo_oe1, CMo_oe2, CMo_oe3, CMo_oe4,
CMo_oe5, CMo_oe6, CMo_oe7, DMSn, DM_cs, DM_oe, DMo_cs0, DMo_cs1,
DMo_cs2, DMo_cs3, DMo_cs4, DMo_cs5, DMo_cs6, DMo_cs7, DMo_oe0,
DMo_oe1, DMo_oe2, DMo_oe3, DMo_oe4, DMo_oe5, DMo_oe6, DMo_oe7,
DMo_web, DSPCLK_cm0, DSPCLK_cm1, DSPCLK_cm2, DSPCLK_dm0, DSPCLK_dm1,
DSPCLK_dm2, DSPCLK_pm0, DSPCLK_pm1, DSPCLK_pm2, EA_oe, ECMA_EN,
ECMSn, ED_oe_14_8, ED_oe_15, ED_oe_7_0, IACKn, IAD_oe, IDo, IDoe,
IOSn, IRFS0, IRFS1, ISCLK0, ISCLK1, ITFS0, ITFS1, PMSn, PM_bdry_sel,
PMo_cs0, PMo_cs1, PMo_cs2, PMo_cs3, PMo_cs4, PMo_cs5, PMo_cs6,
PMo_cs7, PMo_oe0, PMo_oe1, PMo_oe2, PMo_oe3, PMo_oe4, PMo_oe5,
PMo_oe6, PMo_oe7, PMo_web, PWDACK, RDn, RFS0, RFS1, SCLK0, SCLK1,
TD0, TD1, TFS0, TFS1, T_BMODE, T_BRn, T_CLKI_PLL, T_GOICE, T_IAL,
T_ICE_RSTn, T_ID, T_IMS, T_IRDn, T_IRQ0n, T_IRQ1n, T_IRQ2n,
T_IRQE0n, T_IRQE1n, T_IRQL1n, T_ISn, T_IWRn, T_MMAP, T_PWDn, T_RD0,
T_RD1, T_RFS0, T_RFS1, T_Sel_PLL, T_TFS0, T_TFS1, WP_CLK,
WP_HOLD_IN, WP_HOLD_OUT, WP_SHIFT, WP_SI, WP_SO_beforeskew, WRn,
XTALoffn, core_BGn, core_BMSn, core_CLKO, core_CMSn, core_CM_cs,
core_CM_oe, core_CM_web, core_CMo_cs0, core_CMo_cs1, core_CMo_cs2,
core_CMo_cs3, core_CMo_cs4, core_CMo_cs5, core_CMo_cs6,
core_CMo_cs7, core_CMo_oe0, core_CMo_oe1, core_CMo_oe2,
core_CMo_oe3, core_CMo_oe4, core_CMo_oe5, core_CMo_oe6,
core_CMo_oe7, core_DMSn, core_DM_cs, core_DM_oe, core_DMo_cs0,
core_DMo_cs1, core_DMo_cs2, core_DMo_cs3, core_DMo_cs4,
core_DMo_cs5, core_DMo_cs6, core_DMo_cs7, core_DMo_oe0,
core_DMo_oe1, core_DMo_oe2, core_DMo_oe3, core_DMo_oe4,
core_DMo_oe5, core_DMo_oe6, core_DMo_oe7, core_DMo_web,
core_DSPCLK_cm0, core_DSPCLK_cm1, core_DSPCLK_cm2, core_DSPCLK_dm0,
core_DSPCLK_dm1, core_DSPCLK_dm2, core_DSPCLK_pm0, core_DSPCLK_pm1,
core_DSPCLK_pm2, core_EA_oe, core_ECMA_EN, core_ECMSn,
core_ED_oe_14_8, core_ED_oe_15, core_ED_oe_7_0, core_IACKn,
core_IAD_oe, core_IDo, core_IDoe, core_IOSn, core_IRFS0, core_IRFS1,
core_ISCLK0, core_ISCLK1, core_ITFS0, core_ITFS1, core_PMSn,
core_PM_bdry_sel, core_PMo_cs0, core_PMo_cs1, core_PMo_cs2,
core_PMo_cs3, core_PMo_cs4, core_PMo_cs5, core_PMo_cs6,
core_PMo_cs7, core_PMo_oe0, core_PMo_oe1, core_PMo_oe2,
core_PMo_oe3, core_PMo_oe4, core_PMo_oe5, core_PMo_oe6,
core_PMo_oe7, core_PMo_web, core_PWDACK, core_RDn, core_RFS0,
core_RFS1, core_SCLK0, core_SCLK1, core_TD0, core_TD1, core_TFS0,
core_TFS1, core_T_BMODE, core_T_BRn, core_T_CLKI_PLL, core_T_GOICE,
core_T_IAL, core_T_ICE_RSTn, core_T_ID, core_T_IMS, core_T_IRDn,
core_T_IRQ0n, core_T_IRQ1n, core_T_IRQ2n, core_T_IRQE0n,
core_T_IRQE1n, core_T_IRQL1n, core_T_ISn, core_T_IWRn, core_T_MMAP,
core_T_PWDn, core_T_RD0, core_T_RD1, core_T_RFS0, core_T_RFS1,
core_T_Sel_PLL, core_T_TFS0, core_T_TFS1, core_WRn, core_XTALoffn
);
input [23:0] CM_rd0;
input [23:0] CM_rd1;
input [23:0] CM_rd2;
input [23:0] CM_rd3;
input [23:0] CM_rd4;
input [23:0] CM_rd5;
input [23:0] CM_rd6;
input [23:0] CM_rd7;
input [23:0] CM_rdm;
input [15:0] DM_rd0;
input [15:0] DM_rd1;
input [15:0] DM_rd2;
input [15:0] DM_rd3;
input [15:0] DM_rd4;
input [15:0] DM_rd5;
input [15:0] DM_rd6;
input [15:0] DM_rd7;
input [15:0] DM_rdm;
input [15:0] PM_rd0;
input [15:0] PM_rd1;
input [15:0] PM_rd2;
input [15:0] PM_rd3;
input [15:0] PM_rd4;
input [15:0] PM_rd5;
input [15:0] PM_rd6;
input [15:0] PM_rd7;
input [7:0] T_EA;
input [15:0] T_ED;
input [15:0] T_IAD;
input [11:0] T_PIOin;
input [1:0] T_TMODE;
input [13:0] core_CMAinx;
input [23:0] core_CM_wd;
input [13:0] core_DMAinx;
input [15:0] core_DM_wd;
input [14:0] core_EA_do;
input [15:0] core_ED_do;
input [15:0] core_IAD_do;
input [11:0] core_PIO_oe;
input [11:0] core_PIO_out;
input [13:0] core_PMAinx;
input [15:0] core_PM_wd;
input PM_bdry_sel;
input T_BMODE;
input T_BRn;
input T_CLKI_PLL;
input T_GOICE;
input T_IAL;
input T_ICE_RSTn;
input T_ID;
input T_IMS;
input T_IRDn;
input T_IRQ0n;
input T_IRQ1n;
input T_IRQ2n;
input T_IRQE0n;
input T_IRQE1n;
input T_IRQL1n;
input T_ISn;
input T_IWRn;
input T_MMAP;
input T_PWDn;
input T_RD0;
input T_RD1;
input T_RFS0;
input T_RFS1;
input T_Sel_PLL;
input T_TFS0;
input T_TFS1;
input WP_CLK;
input WP_HOLD_IN;
input WP_HOLD_OUT;
input WP_SHIFT;
input WP_SI;
input core_BGn;
input core_BMSn;
input core_CLKO;
input core_CMSn;
input core_CM_cs;
input core_CM_oe;
input core_CM_web;
input core_CMo_cs0;
input core_CMo_cs1;
input core_CMo_cs2;
input core_CMo_cs3;
input core_CMo_cs4;
input core_CMo_cs5;
input core_CMo_cs6;
input core_CMo_cs7;
input core_CMo_oe0;
input core_CMo_oe1;
input core_CMo_oe2;
input core_CMo_oe3;
input core_CMo_oe4;
input core_CMo_oe5;
input core_CMo_oe6;
input core_CMo_oe7;
input core_DMSn;
input core_DM_cs;
input core_DM_oe;
input core_DMo_cs0;
input core_DMo_cs1;
input core_DMo_cs2;
input core_DMo_cs3;
input core_DMo_cs4;
input core_DMo_cs5;
input core_DMo_cs6;
input core_DMo_cs7;
input core_DMo_oe0;
input core_DMo_oe1;
input core_DMo_oe2;
input core_DMo_oe3;
input core_DMo_oe4;
input core_DMo_oe5;
input core_DMo_oe6;
input core_DMo_oe7;
input core_DMo_web;
input core_DSPCLK_cm0;
input core_DSPCLK_cm1;
input core_DSPCLK_cm2;
input core_DSPCLK_dm0;
input core_DSPCLK_dm1;
input core_DSPCLK_dm2;
input core_DSPCLK_pm0;
input core_DSPCLK_pm1;
input core_DSPCLK_pm2;
input core_EA_oe;
input core_ECMA_EN;
input core_ECMSn;
input core_ED_oe_14_8;
input core_ED_oe_15;
input core_ED_oe_7_0;
input core_IACKn;
input core_IAD_oe;
input core_IDo;
input core_IDoe;
input core_IOSn;
input core_IRFS0;
input core_IRFS1;
input core_ISCLK0;
input core_ISCLK1;
input core_ITFS0;
input core_ITFS1;
input core_PMSn;
input core_PMo_cs0;
input core_PMo_cs1;
input core_PMo_cs2;
input core_PMo_cs3;
input core_PMo_cs4;
input core_PMo_cs5;
input core_PMo_cs6;
input core_PMo_cs7;
input core_PMo_oe0;
input core_PMo_oe1;
input core_PMo_oe2;
input core_PMo_oe3;
input core_PMo_oe4;
input core_PMo_oe5;
input core_PMo_oe6;
input core_PMo_oe7;
input core_PMo_web;
input core_PWDACK;
input core_RDn;
input core_RFS0;
input core_RFS1;
input core_SCLK0;
input core_SCLK1;
input core_TD0;
input core_TD1;
input core_TFS0;
input core_TFS1;
input core_WRn;
input core_XTALoffn;
output [13:0] CMAinx;
output [23:0] CM_wd;
output [13:0] DMAinx;
output [15:0] DM_wd;
output [14:0] EA_do;
output [15:0] ED_do;
output [15:0] IAD_do;
output [11:0] PIO_oe;
output [11:0] PIO_out;
output [13:0] PMAinx;
output [15:0] PM_wd;
output [23:0] core_CM_rd0;
output [23:0] core_CM_rd1;
output [23:0] core_CM_rd2;
output [23:0] core_CM_rd3;
output [23:0] core_CM_rd4;
output [23:0] core_CM_rd5;
output [23:0] core_CM_rd6;
output [23:0] core_CM_rd7;
output [23:0] core_CM_rdm;
output [15:0] core_DM_rd0;
output [15:0] core_DM_rd1;
output [15:0] core_DM_rd2;
output [15:0] core_DM_rd3;
output [15:0] core_DM_rd4;
output [15:0] core_DM_rd5;
output [15:0] core_DM_rd6;
output [15:0] core_DM_rd7;
output [15:0] core_DM_rdm;
output [15:0] core_PM_rd0;
output [15:0] core_PM_rd1;
output [15:0] core_PM_rd2;
output [15:0] core_PM_rd3;
output [15:0] core_PM_rd4;
output [15:0] core_PM_rd5;
output [15:0] core_PM_rd6;
output [15:0] core_PM_rd7;
output [7:0] core_T_EA;
output [15:0] core_T_ED;
output [15:0] core_T_IAD;
output [11:0] core_T_PIOin;
output [1:0] core_T_TMODE;
output BGn;
output BMSn;
output CLKO;
output CMSn;
output CM_cs;
output CM_oe;
output CM_web;
output CMo_cs0;
output CMo_cs1;
output CMo_cs2;
output CMo_cs3;
output CMo_cs4;
output CMo_cs5;
output CMo_cs6;
output CMo_cs7;
output CMo_oe0;
output CMo_oe1;
output CMo_oe2;
output CMo_oe3;
output CMo_oe4;
output CMo_oe5;
output CMo_oe6;
output CMo_oe7;
output DMSn;
output DM_cs;
output DM_oe;
output DMo_cs0;
output DMo_cs1;
output DMo_cs2;
output DMo_cs3;
output DMo_cs4;
output DMo_cs5;
output DMo_cs6;
output DMo_cs7;
output DMo_oe0;
output DMo_oe1;
output DMo_oe2;
output DMo_oe3;
output DMo_oe4;
output DMo_oe5;
output DMo_oe6;
output DMo_oe7;
output DMo_web;
output DSPCLK_cm0;
output DSPCLK_cm1;
output DSPCLK_cm2;
output DSPCLK_dm0;
output DSPCLK_dm1;
output DSPCLK_dm2;
output DSPCLK_pm0;
output DSPCLK_pm1;
output DSPCLK_pm2;
output EA_oe;
output ECMA_EN;
output ECMSn;
output ED_oe_14_8;
output ED_oe_15;
output ED_oe_7_0;
output IACKn;
output IAD_oe;
output IDo;
output IDoe;
output IOSn;
output IRFS0;
output IRFS1;
output ISCLK0;
output ISCLK1;
output ITFS0;
output ITFS1;
output PMSn;
output PMo_cs0;
output PMo_cs1;
output PMo_cs2;
output PMo_cs3;
output PMo_cs4;
output PMo_cs5;
output PMo_cs6;
output PMo_cs7;
output PMo_oe0;
output PMo_oe1;
output PMo_oe2;
output PMo_oe3;
output PMo_oe4;
output PMo_oe5;
output PMo_oe6;
output PMo_oe7;
output PMo_web;
output PWDACK;
output RDn;
output RFS0;
output RFS1;
output SCLK0;
output SCLK1;
output TD0;
output TD1;
output TFS0;
output TFS1;
output WP_SO_beforeskew;
output WRn;
output XTALoffn;
output core_PM_bdry_sel;
output core_T_BMODE;
output core_T_BRn;
output core_T_CLKI_PLL;
output core_T_GOICE;
output core_T_IAL;
output core_T_ICE_RSTn;
output core_T_ID;
output core_T_IMS;
output core_T_IRDn;
output core_T_IRQ0n;
output core_T_IRQ1n;
output core_T_IRQ2n;
output core_T_IRQE0n;
output core_T_IRQE1n;
output core_T_IRQL1n;
output core_T_ISn;
output core_T_IWRn;
output core_T_MMAP;
output core_T_PWDn;
output core_T_RD0;
output core_T_RD1;
output core_T_RFS0;
output core_T_RFS1;
output core_T_Sel_PLL;
output core_T_TFS0;
output core_T_TFS1;
wire wp_s_0, wp_s_1, wp_s_10, wp_s_100, wp_s_101, wp_s_102, wp_s_103,
wp_s_104, wp_s_105, wp_s_106, wp_s_107, wp_s_108, wp_s_109, wp_s_11,
wp_s_110, wp_s_111, wp_s_112, wp_s_113, wp_s_114, wp_s_115,
wp_s_116, wp_s_117, wp_s_118, wp_s_119, wp_s_12, wp_s_120, wp_s_121,
wp_s_122, wp_s_123, wp_s_124, wp_s_125, wp_s_126, wp_s_127,
wp_s_128, wp_s_129, wp_s_13, wp_s_130, wp_s_131, wp_s_132, wp_s_133,
wp_s_134, wp_s_135, wp_s_136, wp_s_137, wp_s_138, wp_s_139,
wp_s_14, wp_s_140, wp_s_141, wp_s_142, wp_s_143, wp_s_144, wp_s_145,
wp_s_146, wp_s_147, wp_s_148, wp_s_149, wp_s_15, wp_s_150,
wp_s_151, wp_s_152, wp_s_153, wp_s_154, wp_s_155, wp_s_156,
wp_s_157, wp_s_158, wp_s_159, wp_s_16, wp_s_160, wp_s_161, wp_s_162,
wp_s_163, wp_s_164, wp_s_165, wp_s_166, wp_s_167, wp_s_168,
wp_s_169, wp_s_17, wp_s_170, wp_s_171, wp_s_172, wp_s_173, wp_s_174,
wp_s_175, wp_s_176, wp_s_177, wp_s_178, wp_s_179, wp_s_18,
wp_s_180, wp_s_181, wp_s_182, wp_s_183, wp_s_184, wp_s_185,
wp_s_186, wp_s_187, wp_s_188, wp_s_189, wp_s_19, wp_s_190, wp_s_191,
wp_s_192, wp_s_193, wp_s_194, wp_s_195, wp_s_196, wp_s_197,
wp_s_198, wp_s_199, wp_s_2, wp_s_20, wp_s_200, wp_s_201, wp_s_202,
wp_s_203, wp_s_204, wp_s_205, wp_s_206, wp_s_207, wp_s_208,
wp_s_209, wp_s_21, wp_s_210, wp_s_211, wp_s_212, wp_s_213, wp_s_214,
wp_s_215, wp_s_216, wp_s_217, wp_s_218, wp_s_219, wp_s_22,
wp_s_220, wp_s_221, wp_s_222, wp_s_223, wp_s_224, wp_s_225,
wp_s_226, wp_s_227, wp_s_228, wp_s_229, wp_s_23, wp_s_230, wp_s_231,
wp_s_232, wp_s_233, wp_s_234, wp_s_235, wp_s_236, wp_s_237,
wp_s_238, wp_s_239, wp_s_24, wp_s_240, wp_s_241, wp_s_242, wp_s_243,
wp_s_244, wp_s_245, wp_s_246, wp_s_247, wp_s_248, wp_s_249,
wp_s_25, wp_s_250, wp_s_251, wp_s_252, wp_s_253, wp_s_254, wp_s_255,
wp_s_256, wp_s_257, wp_s_258, wp_s_259, wp_s_26, wp_s_260,
wp_s_261, wp_s_262, wp_s_263, wp_s_264, wp_s_265, wp_s_266,
wp_s_267, wp_s_268, wp_s_269, wp_s_27, wp_s_270, wp_s_271, wp_s_272,
wp_s_273, wp_s_274, wp_s_275, wp_s_276, wp_s_277, wp_s_278,
wp_s_279, wp_s_28, wp_s_280, wp_s_281, wp_s_282, wp_s_283, wp_s_284,
wp_s_285, wp_s_286, wp_s_287, wp_s_288, wp_s_289, wp_s_29,
wp_s_290, wp_s_291, wp_s_292, wp_s_293, wp_s_294, wp_s_295,
wp_s_296, wp_s_297, wp_s_298, wp_s_299, wp_s_3, wp_s_30, wp_s_300,
wp_s_301, wp_s_302, wp_s_303, wp_s_304, wp_s_305, wp_s_306,
wp_s_307, wp_s_308, wp_s_309, wp_s_31, wp_s_310, wp_s_311, wp_s_312,
wp_s_313, wp_s_314, wp_s_315, wp_s_316, wp_s_317, wp_s_318,
wp_s_319, wp_s_32, wp_s_320, wp_s_321, wp_s_322, wp_s_323, wp_s_324,
wp_s_325, wp_s_326, wp_s_327, wp_s_328, wp_s_329, wp_s_33,
wp_s_330, wp_s_331, wp_s_332, wp_s_333, wp_s_334, wp_s_335,
wp_s_336, wp_s_337, wp_s_338, wp_s_339, wp_s_34, wp_s_340, wp_s_341,
wp_s_342, wp_s_343, wp_s_344, wp_s_345, wp_s_346, wp_s_347,
wp_s_348, wp_s_349, wp_s_35, wp_s_350, wp_s_351, wp_s_352, wp_s_353,
wp_s_354, wp_s_355, wp_s_356, wp_s_357, wp_s_358, wp_s_359,
wp_s_36, wp_s_360, wp_s_361, wp_s_362, wp_s_363, wp_s_364, wp_s_365,
wp_s_366, wp_s_367, wp_s_368, wp_s_369, wp_s_37, wp_s_370,
wp_s_371, wp_s_372, wp_s_373, wp_s_374, wp_s_375, wp_s_376,
wp_s_377, wp_s_378, wp_s_379, wp_s_38, wp_s_380, wp_s_381, wp_s_382,
wp_s_383, wp_s_384, wp_s_385, wp_s_386, wp_s_387, wp_s_388,
wp_s_389, wp_s_39, wp_s_390, wp_s_391, wp_s_392, wp_s_393, wp_s_394,
wp_s_395, wp_s_396, wp_s_397, wp_s_398, wp_s_399, wp_s_4, wp_s_40,
wp_s_400, wp_s_401, wp_s_402, wp_s_403, wp_s_404, wp_s_405,
wp_s_406, wp_s_407, wp_s_408, wp_s_409, wp_s_41, wp_s_410, wp_s_411,
wp_s_412, wp_s_413, wp_s_414, wp_s_415, wp_s_416, wp_s_417,
wp_s_418, wp_s_419, wp_s_42, wp_s_420, wp_s_421, wp_s_422, wp_s_423,
wp_s_424, wp_s_425, wp_s_426, wp_s_427, wp_s_428, wp_s_429,
wp_s_43, wp_s_430, wp_s_431, wp_s_432, wp_s_433, wp_s_434, wp_s_435,
wp_s_436, wp_s_437, wp_s_438, wp_s_439, wp_s_44, wp_s_440,
wp_s_441, wp_s_442, wp_s_443, wp_s_444, wp_s_445, wp_s_446,
wp_s_447, wp_s_448, wp_s_449, wp_s_45, wp_s_450, wp_s_451, wp_s_452,
wp_s_453, wp_s_454, wp_s_455, wp_s_456, wp_s_457, wp_s_458,
wp_s_459, wp_s_46, wp_s_460, wp_s_461, wp_s_462, wp_s_463, wp_s_464,
wp_s_465, wp_s_466, wp_s_467, wp_s_468, wp_s_469, wp_s_47,
wp_s_470, wp_s_471, wp_s_472, wp_s_473, wp_s_474, wp_s_475,
wp_s_476, wp_s_477, wp_s_478, wp_s_479, wp_s_48, wp_s_480, wp_s_481,
wp_s_482, wp_s_483, wp_s_484, wp_s_485, wp_s_486, wp_s_487,
wp_s_488, wp_s_489, wp_s_49, wp_s_490, wp_s_491, wp_s_492, wp_s_493,
wp_s_494, wp_s_495, wp_s_496, wp_s_497, wp_s_498, wp_s_499, wp_s_5,
wp_s_50, wp_s_500, wp_s_501, wp_s_502, wp_s_503, wp_s_504,
wp_s_505, wp_s_506, wp_s_507, wp_s_508, wp_s_509, wp_s_51, wp_s_510,
wp_s_511, wp_s_512, wp_s_513, wp_s_514, wp_s_515, wp_s_516,
wp_s_517, wp_s_518, wp_s_519, wp_s_52, wp_s_520, wp_s_521, wp_s_522,
wp_s_523, wp_s_524, wp_s_525, wp_s_526, wp_s_527, wp_s_528,
wp_s_529, wp_s_53, wp_s_530, wp_s_531, wp_s_532, wp_s_533, wp_s_534,
wp_s_535, wp_s_536, wp_s_537, wp_s_538, wp_s_539, wp_s_54,
wp_s_540, wp_s_541, wp_s_542, wp_s_543, wp_s_544, wp_s_545,
wp_s_546, wp_s_547, wp_s_548, wp_s_549, wp_s_55, wp_s_550, wp_s_551,
wp_s_552, wp_s_553, wp_s_554, wp_s_555, wp_s_556, wp_s_557,
wp_s_558, wp_s_559, wp_s_56, wp_s_560, wp_s_561, wp_s_562, wp_s_563,
wp_s_564, wp_s_565, wp_s_566, wp_s_567, wp_s_568, wp_s_569,
wp_s_57, wp_s_570, wp_s_571, wp_s_572, wp_s_573, wp_s_574, wp_s_575,
wp_s_576, wp_s_577, wp_s_578, wp_s_579, wp_s_58, wp_s_580,
wp_s_581, wp_s_582, wp_s_583, wp_s_584, wp_s_585, wp_s_586,
wp_s_587, wp_s_588, wp_s_589, wp_s_59, wp_s_590, wp_s_591, wp_s_592,
wp_s_593, wp_s_594, wp_s_595, wp_s_596, wp_s_597, wp_s_598,
wp_s_599, wp_s_6, wp_s_60, wp_s_600, wp_s_601, wp_s_602, wp_s_603,
wp_s_604, wp_s_605, wp_s_606, wp_s_607, wp_s_608, wp_s_609, wp_s_61,
wp_s_610, wp_s_611, wp_s_612, wp_s_613, wp_s_614, wp_s_615,
wp_s_616, wp_s_617, wp_s_618, wp_s_619, wp_s_62, wp_s_620, wp_s_621,
wp_s_622, wp_s_623, wp_s_624, wp_s_625, wp_s_626, wp_s_627,
wp_s_628, wp_s_629, wp_s_63, wp_s_630, wp_s_631, wp_s_632, wp_s_633,
wp_s_634, wp_s_635, wp_s_636, wp_s_637, wp_s_638, wp_s_639,
wp_s_64, wp_s_640, wp_s_641, wp_s_642, wp_s_643, wp_s_644, wp_s_645,
wp_s_646, wp_s_647, wp_s_648, wp_s_649, wp_s_65, wp_s_650,
wp_s_651, wp_s_652, wp_s_653, wp_s_654, wp_s_655, wp_s_656,
wp_s_657, wp_s_658, wp_s_659, wp_s_66, wp_s_660, wp_s_661, wp_s_662,
wp_s_663, wp_s_664, wp_s_665, wp_s_666, wp_s_667, wp_s_668,
wp_s_669, wp_s_67, wp_s_670, wp_s_671, wp_s_672, wp_s_673, wp_s_674,
wp_s_675, wp_s_676, wp_s_677, wp_s_678, wp_s_679, wp_s_68,
wp_s_680, wp_s_681, wp_s_682, wp_s_683, wp_s_684, wp_s_685,
wp_s_686, wp_s_687, wp_s_688, wp_s_689, wp_s_69, wp_s_690, wp_s_691,
wp_s_692, wp_s_693, wp_s_694, wp_s_695, wp_s_696, wp_s_697,
wp_s_698, wp_s_699, wp_s_7, wp_s_70, wp_s_700, wp_s_701, wp_s_702,
wp_s_703, wp_s_704, wp_s_705, wp_s_706, wp_s_707, wp_s_708,
wp_s_709, wp_s_71, wp_s_710, wp_s_711, wp_s_712, wp_s_713, wp_s_714,
wp_s_715, wp_s_716, wp_s_717, wp_s_718, wp_s_719, wp_s_72,
wp_s_720, wp_s_721, wp_s_722, wp_s_723, wp_s_724, wp_s_725,
wp_s_726, wp_s_727, wp_s_728, wp_s_729, wp_s_73, wp_s_730, wp_s_731,
wp_s_732, wp_s_733, wp_s_734, wp_s_735, wp_s_736, wp_s_737,
wp_s_738, wp_s_739, wp_s_74, wp_s_740, wp_s_741, wp_s_742, wp_s_743,
wp_s_744, wp_s_745, wp_s_746, wp_s_747, wp_s_748, wp_s_749,
wp_s_75, wp_s_750, wp_s_751, wp_s_752, wp_s_753, wp_s_754, wp_s_755,
wp_s_756, wp_s_757, wp_s_758, wp_s_759, wp_s_76, wp_s_760,
wp_s_761, wp_s_762, wp_s_763, wp_s_764, wp_s_765, wp_s_766,
wp_s_767, wp_s_768, wp_s_769, wp_s_77, wp_s_770, wp_s_771, wp_s_772,
wp_s_773, wp_s_774, wp_s_775, wp_s_776, wp_s_777, wp_s_778,
wp_s_779, wp_s_78, wp_s_780, wp_s_781, wp_s_782, wp_s_783, wp_s_784,
wp_s_785, wp_s_786, wp_s_787, wp_s_788, wp_s_789, wp_s_79,
wp_s_790, wp_s_791, wp_s_792, wp_s_793, wp_s_794, wp_s_795,
wp_s_796, wp_s_797, wp_s_798, wp_s_799, wp_s_8, wp_s_80, wp_s_800,
wp_s_801, wp_s_802, wp_s_803, wp_s_804, wp_s_805, wp_s_806,
wp_s_807, wp_s_808, wp_s_809, wp_s_81, wp_s_810, wp_s_811, wp_s_812,
wp_s_813, wp_s_814, wp_s_815, wp_s_816, wp_s_817, wp_s_818,
wp_s_819, wp_s_82, wp_s_820, wp_s_821, wp_s_822, wp_s_823, wp_s_824,
wp_s_825, wp_s_826, wp_s_827, wp_s_828, wp_s_829, wp_s_83,
wp_s_830, wp_s_831, wp_s_832, wp_s_833, wp_s_834, wp_s_835,
wp_s_836, wp_s_837, wp_s_84, wp_s_85, wp_s_86, wp_s_87, wp_s_88,
wp_s_89, wp_s_9, wp_s_90, wp_s_91, wp_s_92, wp_s_93, wp_s_94,
wp_s_95, wp_s_96, wp_s_97, wp_s_98, wp_s_99;
DSP_CORE_vsia_tst_wp_cell_out WC_BGn (
.Func_out(BGn), .SI(wp_s_581), .SO(wp_s_582), .VCO(core_BGn),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_BMSn (
.Func_out(BMSn), .SI(wp_s_587), .SO(wp_s_588), .VCO(core_BMSn),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_CLKO (
.Func_out(CLKO), .SI(wp_s_578), .SO(wp_s_579), .VCO(core_CLKO),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_CMAinx_0_ (
.Func_out(CMAinx[0]), .SI(wp_s_812), .SO(wp_s_813), .VCO(core_CMAinx[0]),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_CMAinx_10_ (
.Func_out(CMAinx[10]), .SI(wp_s_802), .SO(wp_s_803), .VCO(core_CMAinx[10]),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_CMAinx_11_ (
.Func_out(CMAinx[11]), .SI(wp_s_801), .SO(wp_s_802), .VCO(core_CMAinx[11]),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_CMAinx_12_ (
.Func_out(CMAinx[12]), .SI(wp_s_800), .SO(wp_s_801), .VCO(core_CMAinx[12]),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_CMAinx_13_ (
.Func_out(CMAinx[13]), .SI(wp_s_799), .SO(wp_s_800), .VCO(core_CMAinx[13]),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_CMAinx_1_ (
.Func_out(CMAinx[1]), .SI(wp_s_811), .SO(wp_s_812), .VCO(core_CMAinx[1]),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_CMAinx_2_ (
.Func_out(CMAinx[2]), .SI(wp_s_810), .SO(wp_s_811), .VCO(core_CMAinx[2]),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_CMAinx_3_ (
.Func_out(CMAinx[3]), .SI(wp_s_809), .SO(wp_s_810), .VCO(core_CMAinx[3]),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_CMAinx_4_ (
.Func_out(CMAinx[4]), .SI(wp_s_808), .SO(wp_s_809), .VCO(core_CMAinx[4]),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_CMAinx_5_ (
.Func_out(CMAinx[5]), .SI(wp_s_807), .SO(wp_s_808), .VCO(core_CMAinx[5]),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_CMAinx_6_ (
.Func_out(CMAinx[6]), .SI(wp_s_806), .SO(wp_s_807), .VCO(core_CMAinx[6]),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_CMAinx_7_ (
.Func_out(CMAinx[7]), .SI(wp_s_805), .SO(wp_s_806), .VCO(core_CMAinx[7]),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_CMAinx_8_ (
.Func_out(CMAinx[8]), .SI(wp_s_804), .SO(wp_s_805), .VCO(core_CMAinx[8]),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_CMAinx_9_ (
.Func_out(CMAinx[9]), .SI(wp_s_803), .SO(wp_s_804), .VCO(core_CMAinx[9]),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_CMSn (
.Func_out(CMSn), .SI(wp_s_586), .SO(wp_s_587), .VCO(core_CMSn),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_CM_cs (
.Func_out(CM_cs), .SI(wp_s_720), .SO(wp_s_721), .VCO(core_CM_cs),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_CM_oe (
.Func_out(CM_oe), .SI(wp_s_730), .SO(wp_s_731), .VCO(core_CM_oe),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_CM_rd0_0_ (
.Func_in(CM_rd0[0]), .SI(wp_s_400), .SO(wp_s_401), .VCI(core_CM_rd0[0]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_CM_rd0_10_ (
.Func_in(CM_rd0[10]), .SI(wp_s_390), .SO(wp_s_391), .VCI(core_CM_rd0[10]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_CM_rd0_11_ (
.Func_in(CM_rd0[11]), .SI(wp_s_389), .SO(wp_s_390), .VCI(core_CM_rd0[11]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_CM_rd0_12_ (
.Func_in(CM_rd0[12]), .SI(wp_s_388), .SO(wp_s_389), .VCI(core_CM_rd0[12]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_CM_rd0_13_ (
.Func_in(CM_rd0[13]), .SI(wp_s_387), .SO(wp_s_388), .VCI(core_CM_rd0[13]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_CM_rd0_14_ (
.Func_in(CM_rd0[14]), .SI(wp_s_386), .SO(wp_s_387), .VCI(core_CM_rd0[14]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_CM_rd0_15_ (
.Func_in(CM_rd0[15]), .SI(wp_s_385), .SO(wp_s_386), .VCI(core_CM_rd0[15]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_CM_rd0_16_ (
.Func_in(CM_rd0[16]), .SI(wp_s_384), .SO(wp_s_385), .VCI(core_CM_rd0[16]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_CM_rd0_17_ (
.Func_in(CM_rd0[17]), .SI(wp_s_383), .SO(wp_s_384), .VCI(core_CM_rd0[17]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_CM_rd0_18_ (
.Func_in(CM_rd0[18]), .SI(wp_s_382), .SO(wp_s_383), .VCI(core_CM_rd0[18]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_CM_rd0_19_ (
.Func_in(CM_rd0[19]), .SI(wp_s_381), .SO(wp_s_382), .VCI(core_CM_rd0[19]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_CM_rd0_1_ (
.Func_in(CM_rd0[1]), .SI(wp_s_399), .SO(wp_s_400), .VCI(core_CM_rd0[1]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_CM_rd0_20_ (
.Func_in(CM_rd0[20]), .SI(wp_s_380), .SO(wp_s_381), .VCI(core_CM_rd0[20]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_CM_rd0_21_ (
.Func_in(CM_rd0[21]), .SI(wp_s_379), .SO(wp_s_380), .VCI(core_CM_rd0[21]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_CM_rd0_22_ (
.Func_in(CM_rd0[22]), .SI(wp_s_378), .SO(wp_s_379), .VCI(core_CM_rd0[22]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_CM_rd0_23_ (
.Func_in(CM_rd0[23]), .SI(wp_s_377), .SO(wp_s_378), .VCI(core_CM_rd0[23]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_CM_rd0_2_ (
.Func_in(CM_rd0[2]), .SI(wp_s_398), .SO(wp_s_399), .VCI(core_CM_rd0[2]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_CM_rd0_3_ (
.Func_in(CM_rd0[3]), .SI(wp_s_397), .SO(wp_s_398), .VCI(core_CM_rd0[3]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_CM_rd0_4_ (
.Func_in(CM_rd0[4]), .SI(wp_s_396), .SO(wp_s_397), .VCI(core_CM_rd0[4]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_CM_rd0_5_ (
.Func_in(CM_rd0[5]), .SI(wp_s_395), .SO(wp_s_396), .VCI(core_CM_rd0[5]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_CM_rd0_6_ (
.Func_in(CM_rd0[6]), .SI(wp_s_394), .SO(wp_s_395), .VCI(core_CM_rd0[6]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_CM_rd0_7_ (
.Func_in(CM_rd0[7]), .SI(wp_s_393), .SO(wp_s_394), .VCI(core_CM_rd0[7]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_CM_rd0_8_ (
.Func_in(CM_rd0[8]), .SI(wp_s_392), .SO(wp_s_393), .VCI(core_CM_rd0[8]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_CM_rd0_9_ (
.Func_in(CM_rd0[9]), .SI(wp_s_391), .SO(wp_s_392), .VCI(core_CM_rd0[9]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_CM_rd1_0_ (
.Func_in(CM_rd1[0]), .SI(wp_s_424), .SO(wp_s_425), .VCI(core_CM_rd1[0]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_CM_rd1_10_ (
.Func_in(CM_rd1[10]), .SI(wp_s_414), .SO(wp_s_415), .VCI(core_CM_rd1[10]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_CM_rd1_11_ (
.Func_in(CM_rd1[11]), .SI(wp_s_413), .SO(wp_s_414), .VCI(core_CM_rd1[11]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_CM_rd1_12_ (
.Func_in(CM_rd1[12]), .SI(wp_s_412), .SO(wp_s_413), .VCI(core_CM_rd1[12]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_CM_rd1_13_ (
.Func_in(CM_rd1[13]), .SI(wp_s_411), .SO(wp_s_412), .VCI(core_CM_rd1[13]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_CM_rd1_14_ (
.Func_in(CM_rd1[14]), .SI(wp_s_410), .SO(wp_s_411), .VCI(core_CM_rd1[14]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_CM_rd1_15_ (
.Func_in(CM_rd1[15]), .SI(wp_s_409), .SO(wp_s_410), .VCI(core_CM_rd1[15]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_CM_rd1_16_ (
.Func_in(CM_rd1[16]), .SI(wp_s_408), .SO(wp_s_409), .VCI(core_CM_rd1[16]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_CM_rd1_17_ (
.Func_in(CM_rd1[17]), .SI(wp_s_407), .SO(wp_s_408), .VCI(core_CM_rd1[17]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_CM_rd1_18_ (
.Func_in(CM_rd1[18]), .SI(wp_s_406), .SO(wp_s_407), .VCI(core_CM_rd1[18]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_CM_rd1_19_ (
.Func_in(CM_rd1[19]), .SI(wp_s_405), .SO(wp_s_406), .VCI(core_CM_rd1[19]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_CM_rd1_1_ (
.Func_in(CM_rd1[1]), .SI(wp_s_423), .SO(wp_s_424), .VCI(core_CM_rd1[1]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_CM_rd1_20_ (
.Func_in(CM_rd1[20]), .SI(wp_s_404), .SO(wp_s_405), .VCI(core_CM_rd1[20]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_CM_rd1_21_ (
.Func_in(CM_rd1[21]), .SI(wp_s_403), .SO(wp_s_404), .VCI(core_CM_rd1[21]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_CM_rd1_22_ (
.Func_in(CM_rd1[22]), .SI(wp_s_402), .SO(wp_s_403), .VCI(core_CM_rd1[22]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_CM_rd1_23_ (
.Func_in(CM_rd1[23]), .SI(wp_s_401), .SO(wp_s_402), .VCI(core_CM_rd1[23]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_CM_rd1_2_ (
.Func_in(CM_rd1[2]), .SI(wp_s_422), .SO(wp_s_423), .VCI(core_CM_rd1[2]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_CM_rd1_3_ (
.Func_in(CM_rd1[3]), .SI(wp_s_421), .SO(wp_s_422), .VCI(core_CM_rd1[3]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_CM_rd1_4_ (
.Func_in(CM_rd1[4]), .SI(wp_s_420), .SO(wp_s_421), .VCI(core_CM_rd1[4]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_CM_rd1_5_ (
.Func_in(CM_rd1[5]), .SI(wp_s_419), .SO(wp_s_420), .VCI(core_CM_rd1[5]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_CM_rd1_6_ (
.Func_in(CM_rd1[6]), .SI(wp_s_418), .SO(wp_s_419), .VCI(core_CM_rd1[6]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_CM_rd1_7_ (
.Func_in(CM_rd1[7]), .SI(wp_s_417), .SO(wp_s_418), .VCI(core_CM_rd1[7]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_CM_rd1_8_ (
.Func_in(CM_rd1[8]), .SI(wp_s_416), .SO(wp_s_417), .VCI(core_CM_rd1[8]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_CM_rd1_9_ (
.Func_in(CM_rd1[9]), .SI(wp_s_415), .SO(wp_s_416), .VCI(core_CM_rd1[9]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_CM_rd2_0_ (
.Func_in(CM_rd2[0]), .SI(wp_s_448), .SO(wp_s_449), .VCI(core_CM_rd2[0]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_CM_rd2_10_ (
.Func_in(CM_rd2[10]), .SI(wp_s_438), .SO(wp_s_439), .VCI(core_CM_rd2[10]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_CM_rd2_11_ (
.Func_in(CM_rd2[11]), .SI(wp_s_437), .SO(wp_s_438), .VCI(core_CM_rd2[11]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_CM_rd2_12_ (
.Func_in(CM_rd2[12]), .SI(wp_s_436), .SO(wp_s_437), .VCI(core_CM_rd2[12]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_CM_rd2_13_ (
.Func_in(CM_rd2[13]), .SI(wp_s_435), .SO(wp_s_436), .VCI(core_CM_rd2[13]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_CM_rd2_14_ (
.Func_in(CM_rd2[14]), .SI(wp_s_434), .SO(wp_s_435), .VCI(core_CM_rd2[14]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_CM_rd2_15_ (
.Func_in(CM_rd2[15]), .SI(wp_s_433), .SO(wp_s_434), .VCI(core_CM_rd2[15]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_CM_rd2_16_ (
.Func_in(CM_rd2[16]), .SI(wp_s_432), .SO(wp_s_433), .VCI(core_CM_rd2[16]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_CM_rd2_17_ (
.Func_in(CM_rd2[17]), .SI(wp_s_431), .SO(wp_s_432), .VCI(core_CM_rd2[17]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_CM_rd2_18_ (
.Func_in(CM_rd2[18]), .SI(wp_s_430), .SO(wp_s_431), .VCI(core_CM_rd2[18]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_CM_rd2_19_ (
.Func_in(CM_rd2[19]), .SI(wp_s_429), .SO(wp_s_430), .VCI(core_CM_rd2[19]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_CM_rd2_1_ (
.Func_in(CM_rd2[1]), .SI(wp_s_447), .SO(wp_s_448), .VCI(core_CM_rd2[1]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_CM_rd2_20_ (
.Func_in(CM_rd2[20]), .SI(wp_s_428), .SO(wp_s_429), .VCI(core_CM_rd2[20]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_CM_rd2_21_ (
.Func_in(CM_rd2[21]), .SI(wp_s_427), .SO(wp_s_428), .VCI(core_CM_rd2[21]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_CM_rd2_22_ (
.Func_in(CM_rd2[22]), .SI(wp_s_426), .SO(wp_s_427), .VCI(core_CM_rd2[22]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_CM_rd2_23_ (
.Func_in(CM_rd2[23]), .SI(wp_s_425), .SO(wp_s_426), .VCI(core_CM_rd2[23]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_CM_rd2_2_ (
.Func_in(CM_rd2[2]), .SI(wp_s_446), .SO(wp_s_447), .VCI(core_CM_rd2[2]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_CM_rd2_3_ (
.Func_in(CM_rd2[3]), .SI(wp_s_445), .SO(wp_s_446), .VCI(core_CM_rd2[3]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_CM_rd2_4_ (
.Func_in(CM_rd2[4]), .SI(wp_s_444), .SO(wp_s_445), .VCI(core_CM_rd2[4]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_CM_rd2_5_ (
.Func_in(CM_rd2[5]), .SI(wp_s_443), .SO(wp_s_444), .VCI(core_CM_rd2[5]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_CM_rd2_6_ (
.Func_in(CM_rd2[6]), .SI(wp_s_442), .SO(wp_s_443), .VCI(core_CM_rd2[6]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_CM_rd2_7_ (
.Func_in(CM_rd2[7]), .SI(wp_s_441), .SO(wp_s_442), .VCI(core_CM_rd2[7]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_CM_rd2_8_ (
.Func_in(CM_rd2[8]), .SI(wp_s_440), .SO(wp_s_441), .VCI(core_CM_rd2[8]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_CM_rd2_9_ (
.Func_in(CM_rd2[9]), .SI(wp_s_439), .SO(wp_s_440), .VCI(core_CM_rd2[9]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_CM_rd3_0_ (
.Func_in(CM_rd3[0]), .SI(wp_s_472), .SO(wp_s_473), .VCI(core_CM_rd3[0]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_CM_rd3_10_ (
.Func_in(CM_rd3[10]), .SI(wp_s_462), .SO(wp_s_463), .VCI(core_CM_rd3[10]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_CM_rd3_11_ (
.Func_in(CM_rd3[11]), .SI(wp_s_461), .SO(wp_s_462), .VCI(core_CM_rd3[11]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_CM_rd3_12_ (
.Func_in(CM_rd3[12]), .SI(wp_s_460), .SO(wp_s_461), .VCI(core_CM_rd3[12]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_CM_rd3_13_ (
.Func_in(CM_rd3[13]), .SI(wp_s_459), .SO(wp_s_460), .VCI(core_CM_rd3[13]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_CM_rd3_14_ (
.Func_in(CM_rd3[14]), .SI(wp_s_458), .SO(wp_s_459), .VCI(core_CM_rd3[14]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_CM_rd3_15_ (
.Func_in(CM_rd3[15]), .SI(wp_s_457), .SO(wp_s_458), .VCI(core_CM_rd3[15]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_CM_rd3_16_ (
.Func_in(CM_rd3[16]), .SI(wp_s_456), .SO(wp_s_457), .VCI(core_CM_rd3[16]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_CM_rd3_17_ (
.Func_in(CM_rd3[17]), .SI(wp_s_455), .SO(wp_s_456), .VCI(core_CM_rd3[17]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_CM_rd3_18_ (
.Func_in(CM_rd3[18]), .SI(wp_s_454), .SO(wp_s_455), .VCI(core_CM_rd3[18]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_CM_rd3_19_ (
.Func_in(CM_rd3[19]), .SI(wp_s_453), .SO(wp_s_454), .VCI(core_CM_rd3[19]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_CM_rd3_1_ (
.Func_in(CM_rd3[1]), .SI(wp_s_471), .SO(wp_s_472), .VCI(core_CM_rd3[1]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_CM_rd3_20_ (
.Func_in(CM_rd3[20]), .SI(wp_s_452), .SO(wp_s_453), .VCI(core_CM_rd3[20]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_CM_rd3_21_ (
.Func_in(CM_rd3[21]), .SI(wp_s_451), .SO(wp_s_452), .VCI(core_CM_rd3[21]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_CM_rd3_22_ (
.Func_in(CM_rd3[22]), .SI(wp_s_450), .SO(wp_s_451), .VCI(core_CM_rd3[22]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_CM_rd3_23_ (
.Func_in(CM_rd3[23]), .SI(wp_s_449), .SO(wp_s_450), .VCI(core_CM_rd3[23]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_CM_rd3_2_ (
.Func_in(CM_rd3[2]), .SI(wp_s_470), .SO(wp_s_471), .VCI(core_CM_rd3[2]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_CM_rd3_3_ (
.Func_in(CM_rd3[3]), .SI(wp_s_469), .SO(wp_s_470), .VCI(core_CM_rd3[3]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_CM_rd3_4_ (
.Func_in(CM_rd3[4]), .SI(wp_s_468), .SO(wp_s_469), .VCI(core_CM_rd3[4]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_CM_rd3_5_ (
.Func_in(CM_rd3[5]), .SI(wp_s_467), .SO(wp_s_468), .VCI(core_CM_rd3[5]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_CM_rd3_6_ (
.Func_in(CM_rd3[6]), .SI(wp_s_466), .SO(wp_s_467), .VCI(core_CM_rd3[6]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_CM_rd3_7_ (
.Func_in(CM_rd3[7]), .SI(wp_s_465), .SO(wp_s_466), .VCI(core_CM_rd3[7]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_CM_rd3_8_ (
.Func_in(CM_rd3[8]), .SI(wp_s_464), .SO(wp_s_465), .VCI(core_CM_rd3[8]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_CM_rd3_9_ (
.Func_in(CM_rd3[9]), .SI(wp_s_463), .SO(wp_s_464), .VCI(core_CM_rd3[9]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_CM_rd4_0_ (
.Func_in(CM_rd4[0]), .SI(wp_s_496), .SO(wp_s_497), .VCI(core_CM_rd4[0]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_CM_rd4_10_ (
.Func_in(CM_rd4[10]), .SI(wp_s_486), .SO(wp_s_487), .VCI(core_CM_rd4[10]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_CM_rd4_11_ (
.Func_in(CM_rd4[11]), .SI(wp_s_485), .SO(wp_s_486), .VCI(core_CM_rd4[11]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_CM_rd4_12_ (
.Func_in(CM_rd4[12]), .SI(wp_s_484), .SO(wp_s_485), .VCI(core_CM_rd4[12]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_CM_rd4_13_ (
.Func_in(CM_rd4[13]), .SI(wp_s_483), .SO(wp_s_484), .VCI(core_CM_rd4[13]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_CM_rd4_14_ (
.Func_in(CM_rd4[14]), .SI(wp_s_482), .SO(wp_s_483), .VCI(core_CM_rd4[14]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_CM_rd4_15_ (
.Func_in(CM_rd4[15]), .SI(wp_s_481), .SO(wp_s_482), .VCI(core_CM_rd4[15]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_CM_rd4_16_ (
.Func_in(CM_rd4[16]), .SI(wp_s_480), .SO(wp_s_481), .VCI(core_CM_rd4[16]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_CM_rd4_17_ (
.Func_in(CM_rd4[17]), .SI(wp_s_479), .SO(wp_s_480), .VCI(core_CM_rd4[17]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_CM_rd4_18_ (
.Func_in(CM_rd4[18]), .SI(wp_s_478), .SO(wp_s_479), .VCI(core_CM_rd4[18]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_CM_rd4_19_ (
.Func_in(CM_rd4[19]), .SI(wp_s_477), .SO(wp_s_478), .VCI(core_CM_rd4[19]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_CM_rd4_1_ (
.Func_in(CM_rd4[1]), .SI(wp_s_495), .SO(wp_s_496), .VCI(core_CM_rd4[1]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_CM_rd4_20_ (
.Func_in(CM_rd4[20]), .SI(wp_s_476), .SO(wp_s_477), .VCI(core_CM_rd4[20]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_CM_rd4_21_ (
.Func_in(CM_rd4[21]), .SI(wp_s_475), .SO(wp_s_476), .VCI(core_CM_rd4[21]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_CM_rd4_22_ (
.Func_in(CM_rd4[22]), .SI(wp_s_474), .SO(wp_s_475), .VCI(core_CM_rd4[22]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_CM_rd4_23_ (
.Func_in(CM_rd4[23]), .SI(wp_s_473), .SO(wp_s_474), .VCI(core_CM_rd4[23]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_CM_rd4_2_ (
.Func_in(CM_rd4[2]), .SI(wp_s_494), .SO(wp_s_495), .VCI(core_CM_rd4[2]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_CM_rd4_3_ (
.Func_in(CM_rd4[3]), .SI(wp_s_493), .SO(wp_s_494), .VCI(core_CM_rd4[3]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_CM_rd4_4_ (
.Func_in(CM_rd4[4]), .SI(wp_s_492), .SO(wp_s_493), .VCI(core_CM_rd4[4]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_CM_rd4_5_ (
.Func_in(CM_rd4[5]), .SI(wp_s_491), .SO(wp_s_492), .VCI(core_CM_rd4[5]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_CM_rd4_6_ (
.Func_in(CM_rd4[6]), .SI(wp_s_490), .SO(wp_s_491), .VCI(core_CM_rd4[6]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_CM_rd4_7_ (
.Func_in(CM_rd4[7]), .SI(wp_s_489), .SO(wp_s_490), .VCI(core_CM_rd4[7]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_CM_rd4_8_ (
.Func_in(CM_rd4[8]), .SI(wp_s_488), .SO(wp_s_489), .VCI(core_CM_rd4[8]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_CM_rd4_9_ (
.Func_in(CM_rd4[9]), .SI(wp_s_487), .SO(wp_s_488), .VCI(core_CM_rd4[9]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_CM_rd5_0_ (
.Func_in(CM_rd5[0]), .SI(wp_s_520), .SO(wp_s_521), .VCI(core_CM_rd5[0]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_CM_rd5_10_ (
.Func_in(CM_rd5[10]), .SI(wp_s_510), .SO(wp_s_511), .VCI(core_CM_rd5[10]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_CM_rd5_11_ (
.Func_in(CM_rd5[11]), .SI(wp_s_509), .SO(wp_s_510), .VCI(core_CM_rd5[11]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_CM_rd5_12_ (
.Func_in(CM_rd5[12]), .SI(wp_s_508), .SO(wp_s_509), .VCI(core_CM_rd5[12]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_CM_rd5_13_ (
.Func_in(CM_rd5[13]), .SI(wp_s_507), .SO(wp_s_508), .VCI(core_CM_rd5[13]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_CM_rd5_14_ (
.Func_in(CM_rd5[14]), .SI(wp_s_506), .SO(wp_s_507), .VCI(core_CM_rd5[14]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_CM_rd5_15_ (
.Func_in(CM_rd5[15]), .SI(wp_s_505), .SO(wp_s_506), .VCI(core_CM_rd5[15]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_CM_rd5_16_ (
.Func_in(CM_rd5[16]), .SI(wp_s_504), .SO(wp_s_505), .VCI(core_CM_rd5[16]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_CM_rd5_17_ (
.Func_in(CM_rd5[17]), .SI(wp_s_503), .SO(wp_s_504), .VCI(core_CM_rd5[17]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_CM_rd5_18_ (
.Func_in(CM_rd5[18]), .SI(wp_s_502), .SO(wp_s_503), .VCI(core_CM_rd5[18]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_CM_rd5_19_ (
.Func_in(CM_rd5[19]), .SI(wp_s_501), .SO(wp_s_502), .VCI(core_CM_rd5[19]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_CM_rd5_1_ (
.Func_in(CM_rd5[1]), .SI(wp_s_519), .SO(wp_s_520), .VCI(core_CM_rd5[1]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_CM_rd5_20_ (
.Func_in(CM_rd5[20]), .SI(wp_s_500), .SO(wp_s_501), .VCI(core_CM_rd5[20]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_CM_rd5_21_ (
.Func_in(CM_rd5[21]), .SI(wp_s_499), .SO(wp_s_500), .VCI(core_CM_rd5[21]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_CM_rd5_22_ (
.Func_in(CM_rd5[22]), .SI(wp_s_498), .SO(wp_s_499), .VCI(core_CM_rd5[22]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_CM_rd5_23_ (
.Func_in(CM_rd5[23]), .SI(wp_s_497), .SO(wp_s_498), .VCI(core_CM_rd5[23]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_CM_rd5_2_ (
.Func_in(CM_rd5[2]), .SI(wp_s_518), .SO(wp_s_519), .VCI(core_CM_rd5[2]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_CM_rd5_3_ (
.Func_in(CM_rd5[3]), .SI(wp_s_517), .SO(wp_s_518), .VCI(core_CM_rd5[3]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_CM_rd5_4_ (
.Func_in(CM_rd5[4]), .SI(wp_s_516), .SO(wp_s_517), .VCI(core_CM_rd5[4]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_CM_rd5_5_ (
.Func_in(CM_rd5[5]), .SI(wp_s_515), .SO(wp_s_516), .VCI(core_CM_rd5[5]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_CM_rd5_6_ (
.Func_in(CM_rd5[6]), .SI(wp_s_514), .SO(wp_s_515), .VCI(core_CM_rd5[6]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_CM_rd5_7_ (
.Func_in(CM_rd5[7]), .SI(wp_s_513), .SO(wp_s_514), .VCI(core_CM_rd5[7]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_CM_rd5_8_ (
.Func_in(CM_rd5[8]), .SI(wp_s_512), .SO(wp_s_513), .VCI(core_CM_rd5[8]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_CM_rd5_9_ (
.Func_in(CM_rd5[9]), .SI(wp_s_511), .SO(wp_s_512), .VCI(core_CM_rd5[9]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_CM_rd6_0_ (
.Func_in(CM_rd6[0]), .SI(wp_s_544), .SO(wp_s_545), .VCI(core_CM_rd6[0]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_CM_rd6_10_ (
.Func_in(CM_rd6[10]), .SI(wp_s_534), .SO(wp_s_535), .VCI(core_CM_rd6[10]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_CM_rd6_11_ (
.Func_in(CM_rd6[11]), .SI(wp_s_533), .SO(wp_s_534), .VCI(core_CM_rd6[11]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_CM_rd6_12_ (
.Func_in(CM_rd6[12]), .SI(wp_s_532), .SO(wp_s_533), .VCI(core_CM_rd6[12]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_CM_rd6_13_ (
.Func_in(CM_rd6[13]), .SI(wp_s_531), .SO(wp_s_532), .VCI(core_CM_rd6[13]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_CM_rd6_14_ (
.Func_in(CM_rd6[14]), .SI(wp_s_530), .SO(wp_s_531), .VCI(core_CM_rd6[14]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_CM_rd6_15_ (
.Func_in(CM_rd6[15]), .SI(wp_s_529), .SO(wp_s_530), .VCI(core_CM_rd6[15]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_CM_rd6_16_ (
.Func_in(CM_rd6[16]), .SI(wp_s_528), .SO(wp_s_529), .VCI(core_CM_rd6[16]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_CM_rd6_17_ (
.Func_in(CM_rd6[17]), .SI(wp_s_527), .SO(wp_s_528), .VCI(core_CM_rd6[17]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_CM_rd6_18_ (
.Func_in(CM_rd6[18]), .SI(wp_s_526), .SO(wp_s_527), .VCI(core_CM_rd6[18]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_CM_rd6_19_ (
.Func_in(CM_rd6[19]), .SI(wp_s_525), .SO(wp_s_526), .VCI(core_CM_rd6[19]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_CM_rd6_1_ (
.Func_in(CM_rd6[1]), .SI(wp_s_543), .SO(wp_s_544), .VCI(core_CM_rd6[1]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_CM_rd6_20_ (
.Func_in(CM_rd6[20]), .SI(wp_s_524), .SO(wp_s_525), .VCI(core_CM_rd6[20]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_CM_rd6_21_ (
.Func_in(CM_rd6[21]), .SI(wp_s_523), .SO(wp_s_524), .VCI(core_CM_rd6[21]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_CM_rd6_22_ (
.Func_in(CM_rd6[22]), .SI(wp_s_522), .SO(wp_s_523), .VCI(core_CM_rd6[22]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_CM_rd6_23_ (
.Func_in(CM_rd6[23]), .SI(wp_s_521), .SO(wp_s_522), .VCI(core_CM_rd6[23]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_CM_rd6_2_ (
.Func_in(CM_rd6[2]), .SI(wp_s_542), .SO(wp_s_543), .VCI(core_CM_rd6[2]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_CM_rd6_3_ (
.Func_in(CM_rd6[3]), .SI(wp_s_541), .SO(wp_s_542), .VCI(core_CM_rd6[3]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_CM_rd6_4_ (
.Func_in(CM_rd6[4]), .SI(wp_s_540), .SO(wp_s_541), .VCI(core_CM_rd6[4]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_CM_rd6_5_ (
.Func_in(CM_rd6[5]), .SI(wp_s_539), .SO(wp_s_540), .VCI(core_CM_rd6[5]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_CM_rd6_6_ (
.Func_in(CM_rd6[6]), .SI(wp_s_538), .SO(wp_s_539), .VCI(core_CM_rd6[6]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_CM_rd6_7_ (
.Func_in(CM_rd6[7]), .SI(wp_s_537), .SO(wp_s_538), .VCI(core_CM_rd6[7]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_CM_rd6_8_ (
.Func_in(CM_rd6[8]), .SI(wp_s_536), .SO(wp_s_537), .VCI(core_CM_rd6[8]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_CM_rd6_9_ (
.Func_in(CM_rd6[9]), .SI(wp_s_535), .SO(wp_s_536), .VCI(core_CM_rd6[9]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_CM_rd7_0_ (
.Func_in(CM_rd7[0]), .SI(wp_s_568), .SO(wp_s_569), .VCI(core_CM_rd7[0]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_CM_rd7_10_ (
.Func_in(CM_rd7[10]), .SI(wp_s_558), .SO(wp_s_559), .VCI(core_CM_rd7[10]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_CM_rd7_11_ (
.Func_in(CM_rd7[11]), .SI(wp_s_557), .SO(wp_s_558), .VCI(core_CM_rd7[11]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_CM_rd7_12_ (
.Func_in(CM_rd7[12]), .SI(wp_s_556), .SO(wp_s_557), .VCI(core_CM_rd7[12]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_CM_rd7_13_ (
.Func_in(CM_rd7[13]), .SI(wp_s_555), .SO(wp_s_556), .VCI(core_CM_rd7[13]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_CM_rd7_14_ (
.Func_in(CM_rd7[14]), .SI(wp_s_554), .SO(wp_s_555), .VCI(core_CM_rd7[14]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_CM_rd7_15_ (
.Func_in(CM_rd7[15]), .SI(wp_s_553), .SO(wp_s_554), .VCI(core_CM_rd7[15]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_CM_rd7_16_ (
.Func_in(CM_rd7[16]), .SI(wp_s_552), .SO(wp_s_553), .VCI(core_CM_rd7[16]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_CM_rd7_17_ (
.Func_in(CM_rd7[17]), .SI(wp_s_551), .SO(wp_s_552), .VCI(core_CM_rd7[17]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_CM_rd7_18_ (
.Func_in(CM_rd7[18]), .SI(wp_s_550), .SO(wp_s_551), .VCI(core_CM_rd7[18]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_CM_rd7_19_ (
.Func_in(CM_rd7[19]), .SI(wp_s_549), .SO(wp_s_550), .VCI(core_CM_rd7[19]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_CM_rd7_1_ (
.Func_in(CM_rd7[1]), .SI(wp_s_567), .SO(wp_s_568), .VCI(core_CM_rd7[1]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_CM_rd7_20_ (
.Func_in(CM_rd7[20]), .SI(wp_s_548), .SO(wp_s_549), .VCI(core_CM_rd7[20]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_CM_rd7_21_ (
.Func_in(CM_rd7[21]), .SI(wp_s_547), .SO(wp_s_548), .VCI(core_CM_rd7[21]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_CM_rd7_22_ (
.Func_in(CM_rd7[22]), .SI(wp_s_546), .SO(wp_s_547), .VCI(core_CM_rd7[22]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_CM_rd7_23_ (
.Func_in(CM_rd7[23]), .SI(wp_s_545), .SO(wp_s_546), .VCI(core_CM_rd7[23]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_CM_rd7_2_ (
.Func_in(CM_rd7[2]), .SI(wp_s_566), .SO(wp_s_567), .VCI(core_CM_rd7[2]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_CM_rd7_3_ (
.Func_in(CM_rd7[3]), .SI(wp_s_565), .SO(wp_s_566), .VCI(core_CM_rd7[3]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_CM_rd7_4_ (
.Func_in(CM_rd7[4]), .SI(wp_s_564), .SO(wp_s_565), .VCI(core_CM_rd7[4]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_CM_rd7_5_ (
.Func_in(CM_rd7[5]), .SI(wp_s_563), .SO(wp_s_564), .VCI(core_CM_rd7[5]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_CM_rd7_6_ (
.Func_in(CM_rd7[6]), .SI(wp_s_562), .SO(wp_s_563), .VCI(core_CM_rd7[6]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_CM_rd7_7_ (
.Func_in(CM_rd7[7]), .SI(wp_s_561), .SO(wp_s_562), .VCI(core_CM_rd7[7]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_CM_rd7_8_ (
.Func_in(CM_rd7[8]), .SI(wp_s_560), .SO(wp_s_561), .VCI(core_CM_rd7[8]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_CM_rd7_9_ (
.Func_in(CM_rd7[9]), .SI(wp_s_559), .SO(wp_s_560), .VCI(core_CM_rd7[9]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_CM_rdm_0_ (
.Func_in(CM_rdm[0]), .SI(wp_s_376), .SO(wp_s_377), .VCI(core_CM_rdm[0]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_CM_rdm_10_ (
.Func_in(CM_rdm[10]), .SI(wp_s_366), .SO(wp_s_367), .VCI(core_CM_rdm[10]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_CM_rdm_11_ (
.Func_in(CM_rdm[11]), .SI(wp_s_365), .SO(wp_s_366), .VCI(core_CM_rdm[11]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_CM_rdm_12_ (
.Func_in(CM_rdm[12]), .SI(wp_s_364), .SO(wp_s_365), .VCI(core_CM_rdm[12]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_CM_rdm_13_ (
.Func_in(CM_rdm[13]), .SI(wp_s_363), .SO(wp_s_364), .VCI(core_CM_rdm[13]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_CM_rdm_14_ (
.Func_in(CM_rdm[14]), .SI(wp_s_362), .SO(wp_s_363), .VCI(core_CM_rdm[14]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_CM_rdm_15_ (
.Func_in(CM_rdm[15]), .SI(wp_s_361), .SO(wp_s_362), .VCI(core_CM_rdm[15]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_CM_rdm_16_ (
.Func_in(CM_rdm[16]), .SI(wp_s_360), .SO(wp_s_361), .VCI(core_CM_rdm[16]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_CM_rdm_17_ (
.Func_in(CM_rdm[17]), .SI(wp_s_359), .SO(wp_s_360), .VCI(core_CM_rdm[17]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_CM_rdm_18_ (
.Func_in(CM_rdm[18]), .SI(wp_s_358), .SO(wp_s_359), .VCI(core_CM_rdm[18]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_CM_rdm_19_ (
.Func_in(CM_rdm[19]), .SI(wp_s_357), .SO(wp_s_358), .VCI(core_CM_rdm[19]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_CM_rdm_1_ (
.Func_in(CM_rdm[1]), .SI(wp_s_375), .SO(wp_s_376), .VCI(core_CM_rdm[1]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_CM_rdm_20_ (
.Func_in(CM_rdm[20]), .SI(wp_s_356), .SO(wp_s_357), .VCI(core_CM_rdm[20]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_CM_rdm_21_ (
.Func_in(CM_rdm[21]), .SI(wp_s_355), .SO(wp_s_356), .VCI(core_CM_rdm[21]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_CM_rdm_22_ (
.Func_in(CM_rdm[22]), .SI(wp_s_354), .SO(wp_s_355), .VCI(core_CM_rdm[22]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_CM_rdm_23_ (
.Func_in(CM_rdm[23]), .SI(wp_s_353), .SO(wp_s_354), .VCI(core_CM_rdm[23]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_CM_rdm_2_ (
.Func_in(CM_rdm[2]), .SI(wp_s_374), .SO(wp_s_375), .VCI(core_CM_rdm[2]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_CM_rdm_3_ (
.Func_in(CM_rdm[3]), .SI(wp_s_373), .SO(wp_s_374), .VCI(core_CM_rdm[3]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_CM_rdm_4_ (
.Func_in(CM_rdm[4]), .SI(wp_s_372), .SO(wp_s_373), .VCI(core_CM_rdm[4]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_CM_rdm_5_ (
.Func_in(CM_rdm[5]), .SI(wp_s_371), .SO(wp_s_372), .VCI(core_CM_rdm[5]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_CM_rdm_6_ (
.Func_in(CM_rdm[6]), .SI(wp_s_370), .SO(wp_s_371), .VCI(core_CM_rdm[6]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_CM_rdm_7_ (
.Func_in(CM_rdm[7]), .SI(wp_s_369), .SO(wp_s_370), .VCI(core_CM_rdm[7]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_CM_rdm_8_ (
.Func_in(CM_rdm[8]), .SI(wp_s_368), .SO(wp_s_369), .VCI(core_CM_rdm[8]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_CM_rdm_9_ (
.Func_in(CM_rdm[9]), .SI(wp_s_367), .SO(wp_s_368), .VCI(core_CM_rdm[9]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_CM_wd_0_ (
.Func_out(CM_wd[0]), .SI(wp_s_836), .SO(wp_s_837), .VCO(core_CM_wd[0]),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_CM_wd_10_ (
.Func_out(CM_wd[10]), .SI(wp_s_826), .SO(wp_s_827), .VCO(core_CM_wd[10]),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_CM_wd_11_ (
.Func_out(CM_wd[11]), .SI(wp_s_825), .SO(wp_s_826), .VCO(core_CM_wd[11]),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_CM_wd_12_ (
.Func_out(CM_wd[12]), .SI(wp_s_824), .SO(wp_s_825), .VCO(core_CM_wd[12]),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_CM_wd_13_ (
.Func_out(CM_wd[13]), .SI(wp_s_823), .SO(wp_s_824), .VCO(core_CM_wd[13]),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_CM_wd_14_ (
.Func_out(CM_wd[14]), .SI(wp_s_822), .SO(wp_s_823), .VCO(core_CM_wd[14]),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_CM_wd_15_ (
.Func_out(CM_wd[15]), .SI(wp_s_821), .SO(wp_s_822), .VCO(core_CM_wd[15]),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_CM_wd_16_ (
.Func_out(CM_wd[16]), .SI(wp_s_820), .SO(wp_s_821), .VCO(core_CM_wd[16]),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_CM_wd_17_ (
.Func_out(CM_wd[17]), .SI(wp_s_819), .SO(wp_s_820), .VCO(core_CM_wd[17]),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_CM_wd_18_ (
.Func_out(CM_wd[18]), .SI(wp_s_818), .SO(wp_s_819), .VCO(core_CM_wd[18]),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_CM_wd_19_ (
.Func_out(CM_wd[19]), .SI(wp_s_817), .SO(wp_s_818), .VCO(core_CM_wd[19]),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_CM_wd_1_ (
.Func_out(CM_wd[1]), .SI(wp_s_835), .SO(wp_s_836), .VCO(core_CM_wd[1]),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_CM_wd_20_ (
.Func_out(CM_wd[20]), .SI(wp_s_816), .SO(wp_s_817), .VCO(core_CM_wd[20]),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_CM_wd_21_ (
.Func_out(CM_wd[21]), .SI(wp_s_815), .SO(wp_s_816), .VCO(core_CM_wd[21]),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_CM_wd_22_ (
.Func_out(CM_wd[22]), .SI(wp_s_814), .SO(wp_s_815), .VCO(core_CM_wd[22]),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_CM_wd_23_ (
.Func_out(CM_wd[23]), .SI(wp_s_813), .SO(wp_s_814), .VCO(core_CM_wd[23]),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_CM_wd_2_ (
.Func_out(CM_wd[2]), .SI(wp_s_834), .SO(wp_s_835), .VCO(core_CM_wd[2]),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_CM_wd_3_ (
.Func_out(CM_wd[3]), .SI(wp_s_833), .SO(wp_s_834), .VCO(core_CM_wd[3]),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_CM_wd_4_ (
.Func_out(CM_wd[4]), .SI(wp_s_832), .SO(wp_s_833), .VCO(core_CM_wd[4]),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_CM_wd_5_ (
.Func_out(CM_wd[5]), .SI(wp_s_831), .SO(wp_s_832), .VCO(core_CM_wd[5]),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_CM_wd_6_ (
.Func_out(CM_wd[6]), .SI(wp_s_830), .SO(wp_s_831), .VCO(core_CM_wd[6]),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_CM_wd_7_ (
.Func_out(CM_wd[7]), .SI(wp_s_829), .SO(wp_s_830), .VCO(core_CM_wd[7]),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_CM_wd_8_ (
.Func_out(CM_wd[8]), .SI(wp_s_828), .SO(wp_s_829), .VCO(core_CM_wd[8]),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_CM_wd_9_ (
.Func_out(CM_wd[9]), .SI(wp_s_827), .SO(wp_s_828), .VCO(core_CM_wd[9]),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_CM_web (
.Func_out(CM_web), .SI(wp_s_729), .SO(wp_s_730), .VCO(core_CM_web),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_CMo_cs0 (
.Func_out(CMo_cs0), .SI(wp_s_721), .SO(wp_s_722), .VCO(core_CMo_cs0),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_CMo_cs1 (
.Func_out(CMo_cs1), .SI(wp_s_722), .SO(wp_s_723), .VCO(core_CMo_cs1),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_CMo_cs2 (
.Func_out(CMo_cs2), .SI(wp_s_723), .SO(wp_s_724), .VCO(core_CMo_cs2),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_CMo_cs3 (
.Func_out(CMo_cs3), .SI(wp_s_724), .SO(wp_s_725), .VCO(core_CMo_cs3),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_CMo_cs4 (
.Func_out(CMo_cs4), .SI(wp_s_725), .SO(wp_s_726), .VCO(core_CMo_cs4),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_CMo_cs5 (
.Func_out(CMo_cs5), .SI(wp_s_726), .SO(wp_s_727), .VCO(core_CMo_cs5),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_CMo_cs6 (
.Func_out(CMo_cs6), .SI(wp_s_727), .SO(wp_s_728), .VCO(core_CMo_cs6),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_CMo_cs7 (
.Func_out(CMo_cs7), .SI(wp_s_728), .SO(wp_s_729), .VCO(core_CMo_cs7),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_CMo_oe0 (
.Func_out(CMo_oe0), .SI(wp_s_731), .SO(wp_s_732), .VCO(core_CMo_oe0),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_CMo_oe1 (
.Func_out(CMo_oe1), .SI(wp_s_732), .SO(wp_s_733), .VCO(core_CMo_oe1),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_CMo_oe2 (
.Func_out(CMo_oe2), .SI(wp_s_733), .SO(wp_s_734), .VCO(core_CMo_oe2),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_CMo_oe3 (
.Func_out(CMo_oe3), .SI(wp_s_734), .SO(wp_s_735), .VCO(core_CMo_oe3),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_CMo_oe4 (
.Func_out(CMo_oe4), .SI(wp_s_735), .SO(wp_s_736), .VCO(core_CMo_oe4),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_CMo_oe5 (
.Func_out(CMo_oe5), .SI(wp_s_736), .SO(wp_s_737), .VCO(core_CMo_oe5),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_CMo_oe6 (
.Func_out(CMo_oe6), .SI(wp_s_737), .SO(wp_s_738), .VCO(core_CMo_oe6),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_CMo_oe7 (
.Func_out(CMo_oe7), .SI(wp_s_738), .SO(wp_s_739), .VCO(core_CMo_oe7),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_DMAinx_0_ (
.Func_out(DMAinx[0]), .SI(wp_s_798), .SO(wp_s_799), .VCO(core_DMAinx[0]),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_DMAinx_10_ (
.Func_out(DMAinx[10]), .SI(wp_s_788), .SO(wp_s_789), .VCO(core_DMAinx[10]),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_DMAinx_11_ (
.Func_out(DMAinx[11]), .SI(wp_s_787), .SO(wp_s_788), .VCO(core_DMAinx[11]),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_DMAinx_12_ (
.Func_out(DMAinx[12]), .SI(wp_s_786), .SO(wp_s_787), .VCO(core_DMAinx[12]),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_DMAinx_13_ (
.Func_out(DMAinx[13]), .SI(wp_s_785), .SO(wp_s_786), .VCO(core_DMAinx[13]),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_DMAinx_1_ (
.Func_out(DMAinx[1]), .SI(wp_s_797), .SO(wp_s_798), .VCO(core_DMAinx[1]),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_DMAinx_2_ (
.Func_out(DMAinx[2]), .SI(wp_s_796), .SO(wp_s_797), .VCO(core_DMAinx[2]),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_DMAinx_3_ (
.Func_out(DMAinx[3]), .SI(wp_s_795), .SO(wp_s_796), .VCO(core_DMAinx[3]),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_DMAinx_4_ (
.Func_out(DMAinx[4]), .SI(wp_s_794), .SO(wp_s_795), .VCO(core_DMAinx[4]),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_DMAinx_5_ (
.Func_out(DMAinx[5]), .SI(wp_s_793), .SO(wp_s_794), .VCO(core_DMAinx[5]),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_DMAinx_6_ (
.Func_out(DMAinx[6]), .SI(wp_s_792), .SO(wp_s_793), .VCO(core_DMAinx[6]),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_DMAinx_7_ (
.Func_out(DMAinx[7]), .SI(wp_s_791), .SO(wp_s_792), .VCO(core_DMAinx[7]),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_DMAinx_8_ (
.Func_out(DMAinx[8]), .SI(wp_s_790), .SO(wp_s_791), .VCO(core_DMAinx[8]),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_DMAinx_9_ (
.Func_out(DMAinx[9]), .SI(wp_s_789), .SO(wp_s_790), .VCO(core_DMAinx[9]),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_DMSn (
.Func_out(DMSn), .SI(wp_s_584), .SO(wp_s_585), .VCO(core_DMSn),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_DM_cs (
.Func_out(DM_cs), .SI(wp_s_701), .SO(wp_s_702), .VCO(core_DM_cs),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_DM_oe (
.Func_out(DM_oe), .SI(wp_s_711), .SO(wp_s_712), .VCO(core_DM_oe),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_DM_rd0_0_ (
.Func_in(DM_rd0[0]), .SI(wp_s_240), .SO(wp_s_241), .VCI(core_DM_rd0[0]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_DM_rd0_10_ (
.Func_in(DM_rd0[10]), .SI(wp_s_230), .SO(wp_s_231), .VCI(core_DM_rd0[10]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_DM_rd0_11_ (
.Func_in(DM_rd0[11]), .SI(wp_s_229), .SO(wp_s_230), .VCI(core_DM_rd0[11]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_DM_rd0_12_ (
.Func_in(DM_rd0[12]), .SI(wp_s_228), .SO(wp_s_229), .VCI(core_DM_rd0[12]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_DM_rd0_13_ (
.Func_in(DM_rd0[13]), .SI(wp_s_227), .SO(wp_s_228), .VCI(core_DM_rd0[13]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_DM_rd0_14_ (
.Func_in(DM_rd0[14]), .SI(wp_s_226), .SO(wp_s_227), .VCI(core_DM_rd0[14]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_DM_rd0_15_ (
.Func_in(DM_rd0[15]), .SI(wp_s_225), .SO(wp_s_226), .VCI(core_DM_rd0[15]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_DM_rd0_1_ (
.Func_in(DM_rd0[1]), .SI(wp_s_239), .SO(wp_s_240), .VCI(core_DM_rd0[1]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_DM_rd0_2_ (
.Func_in(DM_rd0[2]), .SI(wp_s_238), .SO(wp_s_239), .VCI(core_DM_rd0[2]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_DM_rd0_3_ (
.Func_in(DM_rd0[3]), .SI(wp_s_237), .SO(wp_s_238), .VCI(core_DM_rd0[3]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_DM_rd0_4_ (
.Func_in(DM_rd0[4]), .SI(wp_s_236), .SO(wp_s_237), .VCI(core_DM_rd0[4]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_DM_rd0_5_ (
.Func_in(DM_rd0[5]), .SI(wp_s_235), .SO(wp_s_236), .VCI(core_DM_rd0[5]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_DM_rd0_6_ (
.Func_in(DM_rd0[6]), .SI(wp_s_234), .SO(wp_s_235), .VCI(core_DM_rd0[6]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_DM_rd0_7_ (
.Func_in(DM_rd0[7]), .SI(wp_s_233), .SO(wp_s_234), .VCI(core_DM_rd0[7]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_DM_rd0_8_ (
.Func_in(DM_rd0[8]), .SI(wp_s_232), .SO(wp_s_233), .VCI(core_DM_rd0[8]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_DM_rd0_9_ (
.Func_in(DM_rd0[9]), .SI(wp_s_231), .SO(wp_s_232), .VCI(core_DM_rd0[9]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_DM_rd1_0_ (
.Func_in(DM_rd1[0]), .SI(wp_s_256), .SO(wp_s_257), .VCI(core_DM_rd1[0]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_DM_rd1_10_ (
.Func_in(DM_rd1[10]), .SI(wp_s_246), .SO(wp_s_247), .VCI(core_DM_rd1[10]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_DM_rd1_11_ (
.Func_in(DM_rd1[11]), .SI(wp_s_245), .SO(wp_s_246), .VCI(core_DM_rd1[11]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_DM_rd1_12_ (
.Func_in(DM_rd1[12]), .SI(wp_s_244), .SO(wp_s_245), .VCI(core_DM_rd1[12]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_DM_rd1_13_ (
.Func_in(DM_rd1[13]), .SI(wp_s_243), .SO(wp_s_244), .VCI(core_DM_rd1[13]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_DM_rd1_14_ (
.Func_in(DM_rd1[14]), .SI(wp_s_242), .SO(wp_s_243), .VCI(core_DM_rd1[14]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_DM_rd1_15_ (
.Func_in(DM_rd1[15]), .SI(wp_s_241), .SO(wp_s_242), .VCI(core_DM_rd1[15]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_DM_rd1_1_ (
.Func_in(DM_rd1[1]), .SI(wp_s_255), .SO(wp_s_256), .VCI(core_DM_rd1[1]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_DM_rd1_2_ (
.Func_in(DM_rd1[2]), .SI(wp_s_254), .SO(wp_s_255), .VCI(core_DM_rd1[2]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_DM_rd1_3_ (
.Func_in(DM_rd1[3]), .SI(wp_s_253), .SO(wp_s_254), .VCI(core_DM_rd1[3]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_DM_rd1_4_ (
.Func_in(DM_rd1[4]), .SI(wp_s_252), .SO(wp_s_253), .VCI(core_DM_rd1[4]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_DM_rd1_5_ (
.Func_in(DM_rd1[5]), .SI(wp_s_251), .SO(wp_s_252), .VCI(core_DM_rd1[5]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_DM_rd1_6_ (
.Func_in(DM_rd1[6]), .SI(wp_s_250), .SO(wp_s_251), .VCI(core_DM_rd1[6]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_DM_rd1_7_ (
.Func_in(DM_rd1[7]), .SI(wp_s_249), .SO(wp_s_250), .VCI(core_DM_rd1[7]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_DM_rd1_8_ (
.Func_in(DM_rd1[8]), .SI(wp_s_248), .SO(wp_s_249), .VCI(core_DM_rd1[8]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_DM_rd1_9_ (
.Func_in(DM_rd1[9]), .SI(wp_s_247), .SO(wp_s_248), .VCI(core_DM_rd1[9]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_DM_rd2_0_ (
.Func_in(DM_rd2[0]), .SI(wp_s_272), .SO(wp_s_273), .VCI(core_DM_rd2[0]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_DM_rd2_10_ (
.Func_in(DM_rd2[10]), .SI(wp_s_262), .SO(wp_s_263), .VCI(core_DM_rd2[10]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_DM_rd2_11_ (
.Func_in(DM_rd2[11]), .SI(wp_s_261), .SO(wp_s_262), .VCI(core_DM_rd2[11]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_DM_rd2_12_ (
.Func_in(DM_rd2[12]), .SI(wp_s_260), .SO(wp_s_261), .VCI(core_DM_rd2[12]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_DM_rd2_13_ (
.Func_in(DM_rd2[13]), .SI(wp_s_259), .SO(wp_s_260), .VCI(core_DM_rd2[13]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_DM_rd2_14_ (
.Func_in(DM_rd2[14]), .SI(wp_s_258), .SO(wp_s_259), .VCI(core_DM_rd2[14]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_DM_rd2_15_ (
.Func_in(DM_rd2[15]), .SI(wp_s_257), .SO(wp_s_258), .VCI(core_DM_rd2[15]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_DM_rd2_1_ (
.Func_in(DM_rd2[1]), .SI(wp_s_271), .SO(wp_s_272), .VCI(core_DM_rd2[1]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_DM_rd2_2_ (
.Func_in(DM_rd2[2]), .SI(wp_s_270), .SO(wp_s_271), .VCI(core_DM_rd2[2]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_DM_rd2_3_ (
.Func_in(DM_rd2[3]), .SI(wp_s_269), .SO(wp_s_270), .VCI(core_DM_rd2[3]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_DM_rd2_4_ (
.Func_in(DM_rd2[4]), .SI(wp_s_268), .SO(wp_s_269), .VCI(core_DM_rd2[4]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_DM_rd2_5_ (
.Func_in(DM_rd2[5]), .SI(wp_s_267), .SO(wp_s_268), .VCI(core_DM_rd2[5]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_DM_rd2_6_ (
.Func_in(DM_rd2[6]), .SI(wp_s_266), .SO(wp_s_267), .VCI(core_DM_rd2[6]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_DM_rd2_7_ (
.Func_in(DM_rd2[7]), .SI(wp_s_265), .SO(wp_s_266), .VCI(core_DM_rd2[7]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_DM_rd2_8_ (
.Func_in(DM_rd2[8]), .SI(wp_s_264), .SO(wp_s_265), .VCI(core_DM_rd2[8]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_DM_rd2_9_ (
.Func_in(DM_rd2[9]), .SI(wp_s_263), .SO(wp_s_264), .VCI(core_DM_rd2[9]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_DM_rd3_0_ (
.Func_in(DM_rd3[0]), .SI(wp_s_288), .SO(wp_s_289), .VCI(core_DM_rd3[0]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_DM_rd3_10_ (
.Func_in(DM_rd3[10]), .SI(wp_s_278), .SO(wp_s_279), .VCI(core_DM_rd3[10]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_DM_rd3_11_ (
.Func_in(DM_rd3[11]), .SI(wp_s_277), .SO(wp_s_278), .VCI(core_DM_rd3[11]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_DM_rd3_12_ (
.Func_in(DM_rd3[12]), .SI(wp_s_276), .SO(wp_s_277), .VCI(core_DM_rd3[12]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_DM_rd3_13_ (
.Func_in(DM_rd3[13]), .SI(wp_s_275), .SO(wp_s_276), .VCI(core_DM_rd3[13]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_DM_rd3_14_ (
.Func_in(DM_rd3[14]), .SI(wp_s_274), .SO(wp_s_275), .VCI(core_DM_rd3[14]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_DM_rd3_15_ (
.Func_in(DM_rd3[15]), .SI(wp_s_273), .SO(wp_s_274), .VCI(core_DM_rd3[15]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_DM_rd3_1_ (
.Func_in(DM_rd3[1]), .SI(wp_s_287), .SO(wp_s_288), .VCI(core_DM_rd3[1]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_DM_rd3_2_ (
.Func_in(DM_rd3[2]), .SI(wp_s_286), .SO(wp_s_287), .VCI(core_DM_rd3[2]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_DM_rd3_3_ (
.Func_in(DM_rd3[3]), .SI(wp_s_285), .SO(wp_s_286), .VCI(core_DM_rd3[3]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_DM_rd3_4_ (
.Func_in(DM_rd3[4]), .SI(wp_s_284), .SO(wp_s_285), .VCI(core_DM_rd3[4]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_DM_rd3_5_ (
.Func_in(DM_rd3[5]), .SI(wp_s_283), .SO(wp_s_284), .VCI(core_DM_rd3[5]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_DM_rd3_6_ (
.Func_in(DM_rd3[6]), .SI(wp_s_282), .SO(wp_s_283), .VCI(core_DM_rd3[6]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_DM_rd3_7_ (
.Func_in(DM_rd3[7]), .SI(wp_s_281), .SO(wp_s_282), .VCI(core_DM_rd3[7]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_DM_rd3_8_ (
.Func_in(DM_rd3[8]), .SI(wp_s_280), .SO(wp_s_281), .VCI(core_DM_rd3[8]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_DM_rd3_9_ (
.Func_in(DM_rd3[9]), .SI(wp_s_279), .SO(wp_s_280), .VCI(core_DM_rd3[9]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_DM_rd4_0_ (
.Func_in(DM_rd4[0]), .SI(wp_s_304), .SO(wp_s_305), .VCI(core_DM_rd4[0]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_DM_rd4_10_ (
.Func_in(DM_rd4[10]), .SI(wp_s_294), .SO(wp_s_295), .VCI(core_DM_rd4[10]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_DM_rd4_11_ (
.Func_in(DM_rd4[11]), .SI(wp_s_293), .SO(wp_s_294), .VCI(core_DM_rd4[11]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_DM_rd4_12_ (
.Func_in(DM_rd4[12]), .SI(wp_s_292), .SO(wp_s_293), .VCI(core_DM_rd4[12]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_DM_rd4_13_ (
.Func_in(DM_rd4[13]), .SI(wp_s_291), .SO(wp_s_292), .VCI(core_DM_rd4[13]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_DM_rd4_14_ (
.Func_in(DM_rd4[14]), .SI(wp_s_290), .SO(wp_s_291), .VCI(core_DM_rd4[14]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_DM_rd4_15_ (
.Func_in(DM_rd4[15]), .SI(wp_s_289), .SO(wp_s_290), .VCI(core_DM_rd4[15]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_DM_rd4_1_ (
.Func_in(DM_rd4[1]), .SI(wp_s_303), .SO(wp_s_304), .VCI(core_DM_rd4[1]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_DM_rd4_2_ (
.Func_in(DM_rd4[2]), .SI(wp_s_302), .SO(wp_s_303), .VCI(core_DM_rd4[2]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_DM_rd4_3_ (
.Func_in(DM_rd4[3]), .SI(wp_s_301), .SO(wp_s_302), .VCI(core_DM_rd4[3]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_DM_rd4_4_ (
.Func_in(DM_rd4[4]), .SI(wp_s_300), .SO(wp_s_301), .VCI(core_DM_rd4[4]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_DM_rd4_5_ (
.Func_in(DM_rd4[5]), .SI(wp_s_299), .SO(wp_s_300), .VCI(core_DM_rd4[5]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_DM_rd4_6_ (
.Func_in(DM_rd4[6]), .SI(wp_s_298), .SO(wp_s_299), .VCI(core_DM_rd4[6]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_DM_rd4_7_ (
.Func_in(DM_rd4[7]), .SI(wp_s_297), .SO(wp_s_298), .VCI(core_DM_rd4[7]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_DM_rd4_8_ (
.Func_in(DM_rd4[8]), .SI(wp_s_296), .SO(wp_s_297), .VCI(core_DM_rd4[8]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_DM_rd4_9_ (
.Func_in(DM_rd4[9]), .SI(wp_s_295), .SO(wp_s_296), .VCI(core_DM_rd4[9]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_DM_rd5_0_ (
.Func_in(DM_rd5[0]), .SI(wp_s_320), .SO(wp_s_321), .VCI(core_DM_rd5[0]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_DM_rd5_10_ (
.Func_in(DM_rd5[10]), .SI(wp_s_310), .SO(wp_s_311), .VCI(core_DM_rd5[10]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_DM_rd5_11_ (
.Func_in(DM_rd5[11]), .SI(wp_s_309), .SO(wp_s_310), .VCI(core_DM_rd5[11]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_DM_rd5_12_ (
.Func_in(DM_rd5[12]), .SI(wp_s_308), .SO(wp_s_309), .VCI(core_DM_rd5[12]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_DM_rd5_13_ (
.Func_in(DM_rd5[13]), .SI(wp_s_307), .SO(wp_s_308), .VCI(core_DM_rd5[13]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_DM_rd5_14_ (
.Func_in(DM_rd5[14]), .SI(wp_s_306), .SO(wp_s_307), .VCI(core_DM_rd5[14]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_DM_rd5_15_ (
.Func_in(DM_rd5[15]), .SI(wp_s_305), .SO(wp_s_306), .VCI(core_DM_rd5[15]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_DM_rd5_1_ (
.Func_in(DM_rd5[1]), .SI(wp_s_319), .SO(wp_s_320), .VCI(core_DM_rd5[1]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_DM_rd5_2_ (
.Func_in(DM_rd5[2]), .SI(wp_s_318), .SO(wp_s_319), .VCI(core_DM_rd5[2]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_DM_rd5_3_ (
.Func_in(DM_rd5[3]), .SI(wp_s_317), .SO(wp_s_318), .VCI(core_DM_rd5[3]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_DM_rd5_4_ (
.Func_in(DM_rd5[4]), .SI(wp_s_316), .SO(wp_s_317), .VCI(core_DM_rd5[4]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_DM_rd5_5_ (
.Func_in(DM_rd5[5]), .SI(wp_s_315), .SO(wp_s_316), .VCI(core_DM_rd5[5]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_DM_rd5_6_ (
.Func_in(DM_rd5[6]), .SI(wp_s_314), .SO(wp_s_315), .VCI(core_DM_rd5[6]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_DM_rd5_7_ (
.Func_in(DM_rd5[7]), .SI(wp_s_313), .SO(wp_s_314), .VCI(core_DM_rd5[7]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_DM_rd5_8_ (
.Func_in(DM_rd5[8]), .SI(wp_s_312), .SO(wp_s_313), .VCI(core_DM_rd5[8]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_DM_rd5_9_ (
.Func_in(DM_rd5[9]), .SI(wp_s_311), .SO(wp_s_312), .VCI(core_DM_rd5[9]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_DM_rd6_0_ (
.Func_in(DM_rd6[0]), .SI(wp_s_336), .SO(wp_s_337), .VCI(core_DM_rd6[0]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_DM_rd6_10_ (
.Func_in(DM_rd6[10]), .SI(wp_s_326), .SO(wp_s_327), .VCI(core_DM_rd6[10]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_DM_rd6_11_ (
.Func_in(DM_rd6[11]), .SI(wp_s_325), .SO(wp_s_326), .VCI(core_DM_rd6[11]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_DM_rd6_12_ (
.Func_in(DM_rd6[12]), .SI(wp_s_324), .SO(wp_s_325), .VCI(core_DM_rd6[12]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_DM_rd6_13_ (
.Func_in(DM_rd6[13]), .SI(wp_s_323), .SO(wp_s_324), .VCI(core_DM_rd6[13]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_DM_rd6_14_ (
.Func_in(DM_rd6[14]), .SI(wp_s_322), .SO(wp_s_323), .VCI(core_DM_rd6[14]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_DM_rd6_15_ (
.Func_in(DM_rd6[15]), .SI(wp_s_321), .SO(wp_s_322), .VCI(core_DM_rd6[15]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_DM_rd6_1_ (
.Func_in(DM_rd6[1]), .SI(wp_s_335), .SO(wp_s_336), .VCI(core_DM_rd6[1]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_DM_rd6_2_ (
.Func_in(DM_rd6[2]), .SI(wp_s_334), .SO(wp_s_335), .VCI(core_DM_rd6[2]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_DM_rd6_3_ (
.Func_in(DM_rd6[3]), .SI(wp_s_333), .SO(wp_s_334), .VCI(core_DM_rd6[3]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_DM_rd6_4_ (
.Func_in(DM_rd6[4]), .SI(wp_s_332), .SO(wp_s_333), .VCI(core_DM_rd6[4]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_DM_rd6_5_ (
.Func_in(DM_rd6[5]), .SI(wp_s_331), .SO(wp_s_332), .VCI(core_DM_rd6[5]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_DM_rd6_6_ (
.Func_in(DM_rd6[6]), .SI(wp_s_330), .SO(wp_s_331), .VCI(core_DM_rd6[6]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_DM_rd6_7_ (
.Func_in(DM_rd6[7]), .SI(wp_s_329), .SO(wp_s_330), .VCI(core_DM_rd6[7]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_DM_rd6_8_ (
.Func_in(DM_rd6[8]), .SI(wp_s_328), .SO(wp_s_329), .VCI(core_DM_rd6[8]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_DM_rd6_9_ (
.Func_in(DM_rd6[9]), .SI(wp_s_327), .SO(wp_s_328), .VCI(core_DM_rd6[9]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_DM_rd7_0_ (
.Func_in(DM_rd7[0]), .SI(wp_s_352), .SO(wp_s_353), .VCI(core_DM_rd7[0]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_DM_rd7_10_ (
.Func_in(DM_rd7[10]), .SI(wp_s_342), .SO(wp_s_343), .VCI(core_DM_rd7[10]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_DM_rd7_11_ (
.Func_in(DM_rd7[11]), .SI(wp_s_341), .SO(wp_s_342), .VCI(core_DM_rd7[11]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_DM_rd7_12_ (
.Func_in(DM_rd7[12]), .SI(wp_s_340), .SO(wp_s_341), .VCI(core_DM_rd7[12]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_DM_rd7_13_ (
.Func_in(DM_rd7[13]), .SI(wp_s_339), .SO(wp_s_340), .VCI(core_DM_rd7[13]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_DM_rd7_14_ (
.Func_in(DM_rd7[14]), .SI(wp_s_338), .SO(wp_s_339), .VCI(core_DM_rd7[14]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_DM_rd7_15_ (
.Func_in(DM_rd7[15]), .SI(wp_s_337), .SO(wp_s_338), .VCI(core_DM_rd7[15]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_DM_rd7_1_ (
.Func_in(DM_rd7[1]), .SI(wp_s_351), .SO(wp_s_352), .VCI(core_DM_rd7[1]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_DM_rd7_2_ (
.Func_in(DM_rd7[2]), .SI(wp_s_350), .SO(wp_s_351), .VCI(core_DM_rd7[2]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_DM_rd7_3_ (
.Func_in(DM_rd7[3]), .SI(wp_s_349), .SO(wp_s_350), .VCI(core_DM_rd7[3]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_DM_rd7_4_ (
.Func_in(DM_rd7[4]), .SI(wp_s_348), .SO(wp_s_349), .VCI(core_DM_rd7[4]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_DM_rd7_5_ (
.Func_in(DM_rd7[5]), .SI(wp_s_347), .SO(wp_s_348), .VCI(core_DM_rd7[5]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_DM_rd7_6_ (
.Func_in(DM_rd7[6]), .SI(wp_s_346), .SO(wp_s_347), .VCI(core_DM_rd7[6]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_DM_rd7_7_ (
.Func_in(DM_rd7[7]), .SI(wp_s_345), .SO(wp_s_346), .VCI(core_DM_rd7[7]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_DM_rd7_8_ (
.Func_in(DM_rd7[8]), .SI(wp_s_344), .SO(wp_s_345), .VCI(core_DM_rd7[8]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_DM_rd7_9_ (
.Func_in(DM_rd7[9]), .SI(wp_s_343), .SO(wp_s_344), .VCI(core_DM_rd7[9]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_DM_rdm_0_ (
.Func_in(DM_rdm[0]), .SI(wp_s_224), .SO(wp_s_225), .VCI(core_DM_rdm[0]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_DM_rdm_10_ (
.Func_in(DM_rdm[10]), .SI(wp_s_214), .SO(wp_s_215), .VCI(core_DM_rdm[10]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_DM_rdm_11_ (
.Func_in(DM_rdm[11]), .SI(wp_s_213), .SO(wp_s_214), .VCI(core_DM_rdm[11]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_DM_rdm_12_ (
.Func_in(DM_rdm[12]), .SI(wp_s_212), .SO(wp_s_213), .VCI(core_DM_rdm[12]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_DM_rdm_13_ (
.Func_in(DM_rdm[13]), .SI(wp_s_211), .SO(wp_s_212), .VCI(core_DM_rdm[13]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_DM_rdm_14_ (
.Func_in(DM_rdm[14]), .SI(wp_s_210), .SO(wp_s_211), .VCI(core_DM_rdm[14]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_DM_rdm_15_ (
.Func_in(DM_rdm[15]), .SI(wp_s_209), .SO(wp_s_210), .VCI(core_DM_rdm[15]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_DM_rdm_1_ (
.Func_in(DM_rdm[1]), .SI(wp_s_223), .SO(wp_s_224), .VCI(core_DM_rdm[1]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_DM_rdm_2_ (
.Func_in(DM_rdm[2]), .SI(wp_s_222), .SO(wp_s_223), .VCI(core_DM_rdm[2]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_DM_rdm_3_ (
.Func_in(DM_rdm[3]), .SI(wp_s_221), .SO(wp_s_222), .VCI(core_DM_rdm[3]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_DM_rdm_4_ (
.Func_in(DM_rdm[4]), .SI(wp_s_220), .SO(wp_s_221), .VCI(core_DM_rdm[4]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_DM_rdm_5_ (
.Func_in(DM_rdm[5]), .SI(wp_s_219), .SO(wp_s_220), .VCI(core_DM_rdm[5]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_DM_rdm_6_ (
.Func_in(DM_rdm[6]), .SI(wp_s_218), .SO(wp_s_219), .VCI(core_DM_rdm[6]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_DM_rdm_7_ (
.Func_in(DM_rdm[7]), .SI(wp_s_217), .SO(wp_s_218), .VCI(core_DM_rdm[7]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_DM_rdm_8_ (
.Func_in(DM_rdm[8]), .SI(wp_s_216), .SO(wp_s_217), .VCI(core_DM_rdm[8]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_DM_rdm_9_ (
.Func_in(DM_rdm[9]), .SI(wp_s_215), .SO(wp_s_216), .VCI(core_DM_rdm[9]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_DM_wd_0_ (
.Func_out(DM_wd[0]), .SI(wp_s_770), .SO(wp_s_771), .VCO(core_DM_wd[0]),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_DM_wd_10_ (
.Func_out(DM_wd[10]), .SI(wp_s_760), .SO(wp_s_761), .VCO(core_DM_wd[10]),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_DM_wd_11_ (
.Func_out(DM_wd[11]), .SI(wp_s_759), .SO(wp_s_760), .VCO(core_DM_wd[11]),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_DM_wd_12_ (
.Func_out(DM_wd[12]), .SI(wp_s_758), .SO(wp_s_759), .VCO(core_DM_wd[12]),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_DM_wd_13_ (
.Func_out(DM_wd[13]), .SI(wp_s_757), .SO(wp_s_758), .VCO(core_DM_wd[13]),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_DM_wd_14_ (
.Func_out(DM_wd[14]), .SI(wp_s_756), .SO(wp_s_757), .VCO(core_DM_wd[14]),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_DM_wd_15_ (
.Func_out(DM_wd[15]), .SI(wp_s_755), .SO(wp_s_756), .VCO(core_DM_wd[15]),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_DM_wd_1_ (
.Func_out(DM_wd[1]), .SI(wp_s_769), .SO(wp_s_770), .VCO(core_DM_wd[1]),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_DM_wd_2_ (
.Func_out(DM_wd[2]), .SI(wp_s_768), .SO(wp_s_769), .VCO(core_DM_wd[2]),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_DM_wd_3_ (
.Func_out(DM_wd[3]), .SI(wp_s_767), .SO(wp_s_768), .VCO(core_DM_wd[3]),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_DM_wd_4_ (
.Func_out(DM_wd[4]), .SI(wp_s_766), .SO(wp_s_767), .VCO(core_DM_wd[4]),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_DM_wd_5_ (
.Func_out(DM_wd[5]), .SI(wp_s_765), .SO(wp_s_766), .VCO(core_DM_wd[5]),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_DM_wd_6_ (
.Func_out(DM_wd[6]), .SI(wp_s_764), .SO(wp_s_765), .VCO(core_DM_wd[6]),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_DM_wd_7_ (
.Func_out(DM_wd[7]), .SI(wp_s_763), .SO(wp_s_764), .VCO(core_DM_wd[7]),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_DM_wd_8_ (
.Func_out(DM_wd[8]), .SI(wp_s_762), .SO(wp_s_763), .VCO(core_DM_wd[8]),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_DM_wd_9_ (
.Func_out(DM_wd[9]), .SI(wp_s_761), .SO(wp_s_762), .VCO(core_DM_wd[9]),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_DMo_cs0 (
.Func_out(DMo_cs0), .SI(wp_s_702), .SO(wp_s_703), .VCO(core_DMo_cs0),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_DMo_cs1 (
.Func_out(DMo_cs1), .SI(wp_s_703), .SO(wp_s_704), .VCO(core_DMo_cs1),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_DMo_cs2 (
.Func_out(DMo_cs2), .SI(wp_s_704), .SO(wp_s_705), .VCO(core_DMo_cs2),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_DMo_cs3 (
.Func_out(DMo_cs3), .SI(wp_s_705), .SO(wp_s_706), .VCO(core_DMo_cs3),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_DMo_cs4 (
.Func_out(DMo_cs4), .SI(wp_s_706), .SO(wp_s_707), .VCO(core_DMo_cs4),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_DMo_cs5 (
.Func_out(DMo_cs5), .SI(wp_s_707), .SO(wp_s_708), .VCO(core_DMo_cs5),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_DMo_cs6 (
.Func_out(DMo_cs6), .SI(wp_s_708), .SO(wp_s_709), .VCO(core_DMo_cs6),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_DMo_cs7 (
.Func_out(DMo_cs7), .SI(wp_s_709), .SO(wp_s_710), .VCO(core_DMo_cs7),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_DMo_oe0 (
.Func_out(DMo_oe0), .SI(wp_s_712), .SO(wp_s_713), .VCO(core_DMo_oe0),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_DMo_oe1 (
.Func_out(DMo_oe1), .SI(wp_s_713), .SO(wp_s_714), .VCO(core_DMo_oe1),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_DMo_oe2 (
.Func_out(DMo_oe2), .SI(wp_s_714), .SO(wp_s_715), .VCO(core_DMo_oe2),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_DMo_oe3 (
.Func_out(DMo_oe3), .SI(wp_s_715), .SO(wp_s_716), .VCO(core_DMo_oe3),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_DMo_oe4 (
.Func_out(DMo_oe4), .SI(wp_s_716), .SO(wp_s_717), .VCO(core_DMo_oe4),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_DMo_oe5 (
.Func_out(DMo_oe5), .SI(wp_s_717), .SO(wp_s_718), .VCO(core_DMo_oe5),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_DMo_oe6 (
.Func_out(DMo_oe6), .SI(wp_s_718), .SO(wp_s_719), .VCO(core_DMo_oe6),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_DMo_oe7 (
.Func_out(DMo_oe7), .SI(wp_s_719), .SO(wp_s_720), .VCO(core_DMo_oe7),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_DMo_web (
.Func_out(DMo_web), .SI(wp_s_710), .SO(wp_s_711), .VCO(core_DMo_web),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_DSPCLK_cm0 (
.Func_out(DSPCLK_cm0), .SI(wp_s_569), .SO(wp_s_570), .VCO(core_DSPCLK_cm0),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_DSPCLK_cm1 (
.Func_out(DSPCLK_cm1), .SI(wp_s_570), .SO(wp_s_571), .VCO(core_DSPCLK_cm1),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_DSPCLK_cm2 (
.Func_out(DSPCLK_cm2), .SI(wp_s_571), .SO(wp_s_572), .VCO(core_DSPCLK_cm2),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_DSPCLK_dm0 (
.Func_out(DSPCLK_dm0), .SI(wp_s_575), .SO(wp_s_576), .VCO(core_DSPCLK_dm0),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_DSPCLK_dm1 (
.Func_out(DSPCLK_dm1), .SI(wp_s_576), .SO(wp_s_577), .VCO(core_DSPCLK_dm1),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_DSPCLK_dm2 (
.Func_out(DSPCLK_dm2), .SI(wp_s_577), .SO(wp_s_578), .VCO(core_DSPCLK_dm2),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_DSPCLK_pm0 (
.Func_out(DSPCLK_pm0), .SI(wp_s_572), .SO(wp_s_573), .VCO(core_DSPCLK_pm0),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_DSPCLK_pm1 (
.Func_out(DSPCLK_pm1), .SI(wp_s_573), .SO(wp_s_574), .VCO(core_DSPCLK_pm1),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_DSPCLK_pm2 (
.Func_out(DSPCLK_pm2), .SI(wp_s_574), .SO(wp_s_575), .VCO(core_DSPCLK_pm2),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_EA_do_0_ (
.Func_out(EA_do[0]), .SI(wp_s_625), .SO(wp_s_626), .VCO(core_EA_do[0]),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_EA_do_10_ (
.Func_out(EA_do[10]), .SI(wp_s_615), .SO(wp_s_616), .VCO(core_EA_do[10]),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_EA_do_11_ (
.Func_out(EA_do[11]), .SI(wp_s_614), .SO(wp_s_615), .VCO(core_EA_do[11]),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_EA_do_12_ (
.Func_out(EA_do[12]), .SI(wp_s_613), .SO(wp_s_614), .VCO(core_EA_do[12]),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_EA_do_13_ (
.Func_out(EA_do[13]), .SI(wp_s_612), .SO(wp_s_613), .VCO(core_EA_do[13]),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_EA_do_14_ (
.Func_out(EA_do[14]), .SI(wp_s_611), .SO(wp_s_612), .VCO(core_EA_do[14]),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_EA_do_1_ (
.Func_out(EA_do[1]), .SI(wp_s_624), .SO(wp_s_625), .VCO(core_EA_do[1]),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_EA_do_2_ (
.Func_out(EA_do[2]), .SI(wp_s_623), .SO(wp_s_624), .VCO(core_EA_do[2]),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_EA_do_3_ (
.Func_out(EA_do[3]), .SI(wp_s_622), .SO(wp_s_623), .VCO(core_EA_do[3]),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_EA_do_4_ (
.Func_out(EA_do[4]), .SI(wp_s_621), .SO(wp_s_622), .VCO(core_EA_do[4]),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_EA_do_5_ (
.Func_out(EA_do[5]), .SI(wp_s_620), .SO(wp_s_621), .VCO(core_EA_do[5]),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_EA_do_6_ (
.Func_out(EA_do[6]), .SI(wp_s_619), .SO(wp_s_620), .VCO(core_EA_do[6]),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_EA_do_7_ (
.Func_out(EA_do[7]), .SI(wp_s_618), .SO(wp_s_619), .VCO(core_EA_do[7]),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_EA_do_8_ (
.Func_out(EA_do[8]), .SI(wp_s_617), .SO(wp_s_618), .VCO(core_EA_do[8]),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_EA_do_9_ (
.Func_out(EA_do[9]), .SI(wp_s_616), .SO(wp_s_617), .VCO(core_EA_do[9]),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_EA_oe (
.Func_out(EA_oe), .SI(wp_s_582), .SO(wp_s_583), .VCO(core_EA_oe),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_ECMA_EN (
.Func_out(ECMA_EN), .SI(wp_s_594), .SO(wp_s_595), .VCO(core_ECMA_EN),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_ECMSn (
.Func_out(ECMSn), .SI(wp_s_593), .SO(wp_s_594), .VCO(core_ECMSn),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_ED_do_0_ (
.Func_out(ED_do[0]), .SI(wp_s_610), .SO(wp_s_611), .VCO(core_ED_do[0]),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_ED_do_10_ (
.Func_out(ED_do[10]), .SI(wp_s_600), .SO(wp_s_601), .VCO(core_ED_do[10]),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_ED_do_11_ (
.Func_out(ED_do[11]), .SI(wp_s_599), .SO(wp_s_600), .VCO(core_ED_do[11]),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_ED_do_12_ (
.Func_out(ED_do[12]), .SI(wp_s_598), .SO(wp_s_599), .VCO(core_ED_do[12]),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_ED_do_13_ (
.Func_out(ED_do[13]), .SI(wp_s_597), .SO(wp_s_598), .VCO(core_ED_do[13]),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_ED_do_14_ (
.Func_out(ED_do[14]), .SI(wp_s_596), .SO(wp_s_597), .VCO(core_ED_do[14]),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_ED_do_15_ (
.Func_out(ED_do[15]), .SI(wp_s_595), .SO(wp_s_596), .VCO(core_ED_do[15]),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_ED_do_1_ (
.Func_out(ED_do[1]), .SI(wp_s_609), .SO(wp_s_610), .VCO(core_ED_do[1]),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_ED_do_2_ (
.Func_out(ED_do[2]), .SI(wp_s_608), .SO(wp_s_609), .VCO(core_ED_do[2]),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_ED_do_3_ (
.Func_out(ED_do[3]), .SI(wp_s_607), .SO(wp_s_608), .VCO(core_ED_do[3]),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_ED_do_4_ (
.Func_out(ED_do[4]), .SI(wp_s_606), .SO(wp_s_607), .VCO(core_ED_do[4]),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_ED_do_5_ (
.Func_out(ED_do[5]), .SI(wp_s_605), .SO(wp_s_606), .VCO(core_ED_do[5]),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_ED_do_6_ (
.Func_out(ED_do[6]), .SI(wp_s_604), .SO(wp_s_605), .VCO(core_ED_do[6]),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_ED_do_7_ (
.Func_out(ED_do[7]), .SI(wp_s_603), .SO(wp_s_604), .VCO(core_ED_do[7]),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_ED_do_8_ (
.Func_out(ED_do[8]), .SI(wp_s_602), .SO(wp_s_603), .VCO(core_ED_do[8]),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_ED_do_9_ (
.Func_out(ED_do[9]), .SI(wp_s_601), .SO(wp_s_602), .VCO(core_ED_do[9]),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_ED_oe_14_8 (
.Func_out(ED_oe_14_8), .SI(wp_s_591), .SO(wp_s_592), .VCO(core_ED_oe_14_8),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_ED_oe_15 (
.Func_out(ED_oe_15), .SI(wp_s_590), .SO(wp_s_591), .VCO(core_ED_oe_15),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_ED_oe_7_0 (
.Func_out(ED_oe_7_0), .SI(wp_s_592), .SO(wp_s_593), .VCO(core_ED_oe_7_0),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_IACKn (
.Func_out(IACKn), .SI(wp_s_640), .SO(wp_s_641), .VCO(core_IACKn),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_IAD_do_0_ (
.Func_out(IAD_do[0]), .SI(wp_s_657), .SO(wp_s_658), .VCO(core_IAD_do[0]),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_IAD_do_10_ (
.Func_out(IAD_do[10]), .SI(wp_s_647), .SO(wp_s_648), .VCO(core_IAD_do[10]),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_IAD_do_11_ (
.Func_out(IAD_do[11]), .SI(wp_s_646), .SO(wp_s_647), .VCO(core_IAD_do[11]),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_IAD_do_12_ (
.Func_out(IAD_do[12]), .SI(wp_s_645), .SO(wp_s_646), .VCO(core_IAD_do[12]),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_IAD_do_13_ (
.Func_out(IAD_do[13]), .SI(wp_s_644), .SO(wp_s_645), .VCO(core_IAD_do[13]),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_IAD_do_14_ (
.Func_out(IAD_do[14]), .SI(wp_s_643), .SO(wp_s_644), .VCO(core_IAD_do[14]),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_IAD_do_15_ (
.Func_out(IAD_do[15]), .SI(wp_s_642), .SO(wp_s_643), .VCO(core_IAD_do[15]),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_IAD_do_1_ (
.Func_out(IAD_do[1]), .SI(wp_s_656), .SO(wp_s_657), .VCO(core_IAD_do[1]),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_IAD_do_2_ (
.Func_out(IAD_do[2]), .SI(wp_s_655), .SO(wp_s_656), .VCO(core_IAD_do[2]),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_IAD_do_3_ (
.Func_out(IAD_do[3]), .SI(wp_s_654), .SO(wp_s_655), .VCO(core_IAD_do[3]),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_IAD_do_4_ (
.Func_out(IAD_do[4]), .SI(wp_s_653), .SO(wp_s_654), .VCO(core_IAD_do[4]),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_IAD_do_5_ (
.Func_out(IAD_do[5]), .SI(wp_s_652), .SO(wp_s_653), .VCO(core_IAD_do[5]),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_IAD_do_6_ (
.Func_out(IAD_do[6]), .SI(wp_s_651), .SO(wp_s_652), .VCO(core_IAD_do[6]),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_IAD_do_7_ (
.Func_out(IAD_do[7]), .SI(wp_s_650), .SO(wp_s_651), .VCO(core_IAD_do[7]),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_IAD_do_8_ (
.Func_out(IAD_do[8]), .SI(wp_s_649), .SO(wp_s_650), .VCO(core_IAD_do[8]),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_IAD_do_9_ (
.Func_out(IAD_do[9]), .SI(wp_s_648), .SO(wp_s_649), .VCO(core_IAD_do[9]),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_IAD_oe (
.Func_out(IAD_oe), .SI(wp_s_641), .SO(wp_s_642), .VCO(core_IAD_oe),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_IDo (
.Func_out(IDo), .SI(wp_s_682), .SO(wp_s_683), .VCO(core_IDo),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_IDoe (
.Func_out(IDoe), .SI(wp_s_683), .SO(wp_s_684), .VCO(core_IDoe),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_IOSn (
.Func_out(IOSn), .SI(wp_s_585), .SO(wp_s_586), .VCO(core_IOSn),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_IRFS0 (
.Func_out(IRFS0), .SI(wp_s_633), .SO(wp_s_634), .VCO(core_IRFS0),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_IRFS1 (
.Func_out(IRFS1), .SI(wp_s_637), .SO(wp_s_638), .VCO(core_IRFS1),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_ISCLK0 (
.Func_out(ISCLK0), .SI(wp_s_629), .SO(wp_s_630), .VCO(core_ISCLK0),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_ISCLK1 (
.Func_out(ISCLK1), .SI(wp_s_631), .SO(wp_s_632), .VCO(core_ISCLK1),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_ITFS0 (
.Func_out(ITFS0), .SI(wp_s_635), .SO(wp_s_636), .VCO(core_ITFS0),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_ITFS1 (
.Func_out(ITFS1), .SI(wp_s_639), .SO(wp_s_640), .VCO(core_ITFS1),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_PIO_oe_0_ (
.Func_out(PIO_oe[0]), .SI(wp_s_669), .SO(wp_s_670), .VCO(core_PIO_oe[0]),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_PIO_oe_10_ (
.Func_out(PIO_oe[10]), .SI(wp_s_659), .SO(wp_s_660), .VCO(core_PIO_oe[10]),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_PIO_oe_11_ (
.Func_out(PIO_oe[11]), .SI(wp_s_658), .SO(wp_s_659), .VCO(core_PIO_oe[11]),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_PIO_oe_1_ (
.Func_out(PIO_oe[1]), .SI(wp_s_668), .SO(wp_s_669), .VCO(core_PIO_oe[1]),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_PIO_oe_2_ (
.Func_out(PIO_oe[2]), .SI(wp_s_667), .SO(wp_s_668), .VCO(core_PIO_oe[2]),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_PIO_oe_3_ (
.Func_out(PIO_oe[3]), .SI(wp_s_666), .SO(wp_s_667), .VCO(core_PIO_oe[3]),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_PIO_oe_4_ (
.Func_out(PIO_oe[4]), .SI(wp_s_665), .SO(wp_s_666), .VCO(core_PIO_oe[4]),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_PIO_oe_5_ (
.Func_out(PIO_oe[5]), .SI(wp_s_664), .SO(wp_s_665), .VCO(core_PIO_oe[5]),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_PIO_oe_6_ (
.Func_out(PIO_oe[6]), .SI(wp_s_663), .SO(wp_s_664), .VCO(core_PIO_oe[6]),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_PIO_oe_7_ (
.Func_out(PIO_oe[7]), .SI(wp_s_662), .SO(wp_s_663), .VCO(core_PIO_oe[7]),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_PIO_oe_8_ (
.Func_out(PIO_oe[8]), .SI(wp_s_661), .SO(wp_s_662), .VCO(core_PIO_oe[8]),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_PIO_oe_9_ (
.Func_out(PIO_oe[9]), .SI(wp_s_660), .SO(wp_s_661), .VCO(core_PIO_oe[9]),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_PIO_out_0_ (
.Func_out(PIO_out[0]), .SI(wp_s_681), .SO(wp_s_682), .VCO(core_PIO_out[0]),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_PIO_out_10_ (
.Func_out(PIO_out[10]), .SI(wp_s_671), .SO(wp_s_672), .VCO(core_PIO_out[10]),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_PIO_out_11_ (
.Func_out(PIO_out[11]), .SI(wp_s_670), .SO(wp_s_671), .VCO(core_PIO_out[11]),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_PIO_out_1_ (
.Func_out(PIO_out[1]), .SI(wp_s_680), .SO(wp_s_681), .VCO(core_PIO_out[1]),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_PIO_out_2_ (
.Func_out(PIO_out[2]), .SI(wp_s_679), .SO(wp_s_680), .VCO(core_PIO_out[2]),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_PIO_out_3_ (
.Func_out(PIO_out[3]), .SI(wp_s_678), .SO(wp_s_679), .VCO(core_PIO_out[3]),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_PIO_out_4_ (
.Func_out(PIO_out[4]), .SI(wp_s_677), .SO(wp_s_678), .VCO(core_PIO_out[4]),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_PIO_out_5_ (
.Func_out(PIO_out[5]), .SI(wp_s_676), .SO(wp_s_677), .VCO(core_PIO_out[5]),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_PIO_out_6_ (
.Func_out(PIO_out[6]), .SI(wp_s_675), .SO(wp_s_676), .VCO(core_PIO_out[6]),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_PIO_out_7_ (
.Func_out(PIO_out[7]), .SI(wp_s_674), .SO(wp_s_675), .VCO(core_PIO_out[7]),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_PIO_out_8_ (
.Func_out(PIO_out[8]), .SI(wp_s_673), .SO(wp_s_674), .VCO(core_PIO_out[8]),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_PIO_out_9_ (
.Func_out(PIO_out[9]), .SI(wp_s_672), .SO(wp_s_673), .VCO(core_PIO_out[9]),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_PMAinx_0_ (
.Func_out(PMAinx[0]), .SI(wp_s_784), .SO(wp_s_785), .VCO(core_PMAinx[0]),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_PMAinx_10_ (
.Func_out(PMAinx[10]), .SI(wp_s_774), .SO(wp_s_775), .VCO(core_PMAinx[10]),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_PMAinx_11_ (
.Func_out(PMAinx[11]), .SI(wp_s_773), .SO(wp_s_774), .VCO(core_PMAinx[11]),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_PMAinx_12_ (
.Func_out(PMAinx[12]), .SI(wp_s_772), .SO(wp_s_773), .VCO(core_PMAinx[12]),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_PMAinx_13_ (
.Func_out(PMAinx[13]), .SI(wp_s_771), .SO(wp_s_772), .VCO(core_PMAinx[13]),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_PMAinx_1_ (
.Func_out(PMAinx[1]), .SI(wp_s_783), .SO(wp_s_784), .VCO(core_PMAinx[1]),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_PMAinx_2_ (
.Func_out(PMAinx[2]), .SI(wp_s_782), .SO(wp_s_783), .VCO(core_PMAinx[2]),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_PMAinx_3_ (
.Func_out(PMAinx[3]), .SI(wp_s_781), .SO(wp_s_782), .VCO(core_PMAinx[3]),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_PMAinx_4_ (
.Func_out(PMAinx[4]), .SI(wp_s_780), .SO(wp_s_781), .VCO(core_PMAinx[4]),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_PMAinx_5_ (
.Func_out(PMAinx[5]), .SI(wp_s_779), .SO(wp_s_780), .VCO(core_PMAinx[5]),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_PMAinx_6_ (
.Func_out(PMAinx[6]), .SI(wp_s_778), .SO(wp_s_779), .VCO(core_PMAinx[6]),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_PMAinx_7_ (
.Func_out(PMAinx[7]), .SI(wp_s_777), .SO(wp_s_778), .VCO(core_PMAinx[7]),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_PMAinx_8_ (
.Func_out(PMAinx[8]), .SI(wp_s_776), .SO(wp_s_777), .VCO(core_PMAinx[8]),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_PMAinx_9_ (
.Func_out(PMAinx[9]), .SI(wp_s_775), .SO(wp_s_776), .VCO(core_PMAinx[9]),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_PMSn (
.Func_out(PMSn), .SI(wp_s_583), .SO(wp_s_584), .VCO(core_PMSn),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_PM_bdry_sel (
.Func_in(PM_bdry_sel), .SI(wp_s_32), .SO(wp_s_33), .VCI(core_PM_bdry_sel),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_PM_rd0_0_ (
.Func_in(PM_rd0[0]), .SI(wp_s_96), .SO(wp_s_97), .VCI(core_PM_rd0[0]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_PM_rd0_10_ (
.Func_in(PM_rd0[10]), .SI(wp_s_86), .SO(wp_s_87), .VCI(core_PM_rd0[10]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_PM_rd0_11_ (
.Func_in(PM_rd0[11]), .SI(wp_s_85), .SO(wp_s_86), .VCI(core_PM_rd0[11]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_PM_rd0_12_ (
.Func_in(PM_rd0[12]), .SI(wp_s_84), .SO(wp_s_85), .VCI(core_PM_rd0[12]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_PM_rd0_13_ (
.Func_in(PM_rd0[13]), .SI(wp_s_83), .SO(wp_s_84), .VCI(core_PM_rd0[13]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_PM_rd0_14_ (
.Func_in(PM_rd0[14]), .SI(wp_s_82), .SO(wp_s_83), .VCI(core_PM_rd0[14]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_PM_rd0_15_ (
.Func_in(PM_rd0[15]), .SI(wp_s_81), .SO(wp_s_82), .VCI(core_PM_rd0[15]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_PM_rd0_1_ (
.Func_in(PM_rd0[1]), .SI(wp_s_95), .SO(wp_s_96), .VCI(core_PM_rd0[1]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_PM_rd0_2_ (
.Func_in(PM_rd0[2]), .SI(wp_s_94), .SO(wp_s_95), .VCI(core_PM_rd0[2]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_PM_rd0_3_ (
.Func_in(PM_rd0[3]), .SI(wp_s_93), .SO(wp_s_94), .VCI(core_PM_rd0[3]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_PM_rd0_4_ (
.Func_in(PM_rd0[4]), .SI(wp_s_92), .SO(wp_s_93), .VCI(core_PM_rd0[4]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_PM_rd0_5_ (
.Func_in(PM_rd0[5]), .SI(wp_s_91), .SO(wp_s_92), .VCI(core_PM_rd0[5]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_PM_rd0_6_ (
.Func_in(PM_rd0[6]), .SI(wp_s_90), .SO(wp_s_91), .VCI(core_PM_rd0[6]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_PM_rd0_7_ (
.Func_in(PM_rd0[7]), .SI(wp_s_89), .SO(wp_s_90), .VCI(core_PM_rd0[7]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_PM_rd0_8_ (
.Func_in(PM_rd0[8]), .SI(wp_s_88), .SO(wp_s_89), .VCI(core_PM_rd0[8]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_PM_rd0_9_ (
.Func_in(PM_rd0[9]), .SI(wp_s_87), .SO(wp_s_88), .VCI(core_PM_rd0[9]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_PM_rd1_0_ (
.Func_in(PM_rd1[0]), .SI(wp_s_112), .SO(wp_s_113), .VCI(core_PM_rd1[0]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_PM_rd1_10_ (
.Func_in(PM_rd1[10]), .SI(wp_s_102), .SO(wp_s_103), .VCI(core_PM_rd1[10]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_PM_rd1_11_ (
.Func_in(PM_rd1[11]), .SI(wp_s_101), .SO(wp_s_102), .VCI(core_PM_rd1[11]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_PM_rd1_12_ (
.Func_in(PM_rd1[12]), .SI(wp_s_100), .SO(wp_s_101), .VCI(core_PM_rd1[12]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_PM_rd1_13_ (
.Func_in(PM_rd1[13]), .SI(wp_s_99), .SO(wp_s_100), .VCI(core_PM_rd1[13]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_PM_rd1_14_ (
.Func_in(PM_rd1[14]), .SI(wp_s_98), .SO(wp_s_99), .VCI(core_PM_rd1[14]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_PM_rd1_15_ (
.Func_in(PM_rd1[15]), .SI(wp_s_97), .SO(wp_s_98), .VCI(core_PM_rd1[15]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_PM_rd1_1_ (
.Func_in(PM_rd1[1]), .SI(wp_s_111), .SO(wp_s_112), .VCI(core_PM_rd1[1]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_PM_rd1_2_ (
.Func_in(PM_rd1[2]), .SI(wp_s_110), .SO(wp_s_111), .VCI(core_PM_rd1[2]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_PM_rd1_3_ (
.Func_in(PM_rd1[3]), .SI(wp_s_109), .SO(wp_s_110), .VCI(core_PM_rd1[3]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_PM_rd1_4_ (
.Func_in(PM_rd1[4]), .SI(wp_s_108), .SO(wp_s_109), .VCI(core_PM_rd1[4]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_PM_rd1_5_ (
.Func_in(PM_rd1[5]), .SI(wp_s_107), .SO(wp_s_108), .VCI(core_PM_rd1[5]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_PM_rd1_6_ (
.Func_in(PM_rd1[6]), .SI(wp_s_106), .SO(wp_s_107), .VCI(core_PM_rd1[6]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_PM_rd1_7_ (
.Func_in(PM_rd1[7]), .SI(wp_s_105), .SO(wp_s_106), .VCI(core_PM_rd1[7]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_PM_rd1_8_ (
.Func_in(PM_rd1[8]), .SI(wp_s_104), .SO(wp_s_105), .VCI(core_PM_rd1[8]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_PM_rd1_9_ (
.Func_in(PM_rd1[9]), .SI(wp_s_103), .SO(wp_s_104), .VCI(core_PM_rd1[9]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_PM_rd2_0_ (
.Func_in(PM_rd2[0]), .SI(wp_s_128), .SO(wp_s_129), .VCI(core_PM_rd2[0]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_PM_rd2_10_ (
.Func_in(PM_rd2[10]), .SI(wp_s_118), .SO(wp_s_119), .VCI(core_PM_rd2[10]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_PM_rd2_11_ (
.Func_in(PM_rd2[11]), .SI(wp_s_117), .SO(wp_s_118), .VCI(core_PM_rd2[11]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_PM_rd2_12_ (
.Func_in(PM_rd2[12]), .SI(wp_s_116), .SO(wp_s_117), .VCI(core_PM_rd2[12]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_PM_rd2_13_ (
.Func_in(PM_rd2[13]), .SI(wp_s_115), .SO(wp_s_116), .VCI(core_PM_rd2[13]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_PM_rd2_14_ (
.Func_in(PM_rd2[14]), .SI(wp_s_114), .SO(wp_s_115), .VCI(core_PM_rd2[14]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_PM_rd2_15_ (
.Func_in(PM_rd2[15]), .SI(wp_s_113), .SO(wp_s_114), .VCI(core_PM_rd2[15]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_PM_rd2_1_ (
.Func_in(PM_rd2[1]), .SI(wp_s_127), .SO(wp_s_128), .VCI(core_PM_rd2[1]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_PM_rd2_2_ (
.Func_in(PM_rd2[2]), .SI(wp_s_126), .SO(wp_s_127), .VCI(core_PM_rd2[2]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_PM_rd2_3_ (
.Func_in(PM_rd2[3]), .SI(wp_s_125), .SO(wp_s_126), .VCI(core_PM_rd2[3]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_PM_rd2_4_ (
.Func_in(PM_rd2[4]), .SI(wp_s_124), .SO(wp_s_125), .VCI(core_PM_rd2[4]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_PM_rd2_5_ (
.Func_in(PM_rd2[5]), .SI(wp_s_123), .SO(wp_s_124), .VCI(core_PM_rd2[5]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_PM_rd2_6_ (
.Func_in(PM_rd2[6]), .SI(wp_s_122), .SO(wp_s_123), .VCI(core_PM_rd2[6]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_PM_rd2_7_ (
.Func_in(PM_rd2[7]), .SI(wp_s_121), .SO(wp_s_122), .VCI(core_PM_rd2[7]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_PM_rd2_8_ (
.Func_in(PM_rd2[8]), .SI(wp_s_120), .SO(wp_s_121), .VCI(core_PM_rd2[8]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_PM_rd2_9_ (
.Func_in(PM_rd2[9]), .SI(wp_s_119), .SO(wp_s_120), .VCI(core_PM_rd2[9]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_PM_rd3_0_ (
.Func_in(PM_rd3[0]), .SI(wp_s_144), .SO(wp_s_145), .VCI(core_PM_rd3[0]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_PM_rd3_10_ (
.Func_in(PM_rd3[10]), .SI(wp_s_134), .SO(wp_s_135), .VCI(core_PM_rd3[10]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_PM_rd3_11_ (
.Func_in(PM_rd3[11]), .SI(wp_s_133), .SO(wp_s_134), .VCI(core_PM_rd3[11]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_PM_rd3_12_ (
.Func_in(PM_rd3[12]), .SI(wp_s_132), .SO(wp_s_133), .VCI(core_PM_rd3[12]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_PM_rd3_13_ (
.Func_in(PM_rd3[13]), .SI(wp_s_131), .SO(wp_s_132), .VCI(core_PM_rd3[13]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_PM_rd3_14_ (
.Func_in(PM_rd3[14]), .SI(wp_s_130), .SO(wp_s_131), .VCI(core_PM_rd3[14]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_PM_rd3_15_ (
.Func_in(PM_rd3[15]), .SI(wp_s_129), .SO(wp_s_130), .VCI(core_PM_rd3[15]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_PM_rd3_1_ (
.Func_in(PM_rd3[1]), .SI(wp_s_143), .SO(wp_s_144), .VCI(core_PM_rd3[1]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_PM_rd3_2_ (
.Func_in(PM_rd3[2]), .SI(wp_s_142), .SO(wp_s_143), .VCI(core_PM_rd3[2]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_PM_rd3_3_ (
.Func_in(PM_rd3[3]), .SI(wp_s_141), .SO(wp_s_142), .VCI(core_PM_rd3[3]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_PM_rd3_4_ (
.Func_in(PM_rd3[4]), .SI(wp_s_140), .SO(wp_s_141), .VCI(core_PM_rd3[4]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_PM_rd3_5_ (
.Func_in(PM_rd3[5]), .SI(wp_s_139), .SO(wp_s_140), .VCI(core_PM_rd3[5]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_PM_rd3_6_ (
.Func_in(PM_rd3[6]), .SI(wp_s_138), .SO(wp_s_139), .VCI(core_PM_rd3[6]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_PM_rd3_7_ (
.Func_in(PM_rd3[7]), .SI(wp_s_137), .SO(wp_s_138), .VCI(core_PM_rd3[7]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_PM_rd3_8_ (
.Func_in(PM_rd3[8]), .SI(wp_s_136), .SO(wp_s_137), .VCI(core_PM_rd3[8]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_PM_rd3_9_ (
.Func_in(PM_rd3[9]), .SI(wp_s_135), .SO(wp_s_136), .VCI(core_PM_rd3[9]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_PM_rd4_0_ (
.Func_in(PM_rd4[0]), .SI(wp_s_160), .SO(wp_s_161), .VCI(core_PM_rd4[0]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_PM_rd4_10_ (
.Func_in(PM_rd4[10]), .SI(wp_s_150), .SO(wp_s_151), .VCI(core_PM_rd4[10]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_PM_rd4_11_ (
.Func_in(PM_rd4[11]), .SI(wp_s_149), .SO(wp_s_150), .VCI(core_PM_rd4[11]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_PM_rd4_12_ (
.Func_in(PM_rd4[12]), .SI(wp_s_148), .SO(wp_s_149), .VCI(core_PM_rd4[12]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_PM_rd4_13_ (
.Func_in(PM_rd4[13]), .SI(wp_s_147), .SO(wp_s_148), .VCI(core_PM_rd4[13]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_PM_rd4_14_ (
.Func_in(PM_rd4[14]), .SI(wp_s_146), .SO(wp_s_147), .VCI(core_PM_rd4[14]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_PM_rd4_15_ (
.Func_in(PM_rd4[15]), .SI(wp_s_145), .SO(wp_s_146), .VCI(core_PM_rd4[15]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_PM_rd4_1_ (
.Func_in(PM_rd4[1]), .SI(wp_s_159), .SO(wp_s_160), .VCI(core_PM_rd4[1]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_PM_rd4_2_ (
.Func_in(PM_rd4[2]), .SI(wp_s_158), .SO(wp_s_159), .VCI(core_PM_rd4[2]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_PM_rd4_3_ (
.Func_in(PM_rd4[3]), .SI(wp_s_157), .SO(wp_s_158), .VCI(core_PM_rd4[3]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_PM_rd4_4_ (
.Func_in(PM_rd4[4]), .SI(wp_s_156), .SO(wp_s_157), .VCI(core_PM_rd4[4]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_PM_rd4_5_ (
.Func_in(PM_rd4[5]), .SI(wp_s_155), .SO(wp_s_156), .VCI(core_PM_rd4[5]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_PM_rd4_6_ (
.Func_in(PM_rd4[6]), .SI(wp_s_154), .SO(wp_s_155), .VCI(core_PM_rd4[6]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_PM_rd4_7_ (
.Func_in(PM_rd4[7]), .SI(wp_s_153), .SO(wp_s_154), .VCI(core_PM_rd4[7]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_PM_rd4_8_ (
.Func_in(PM_rd4[8]), .SI(wp_s_152), .SO(wp_s_153), .VCI(core_PM_rd4[8]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_PM_rd4_9_ (
.Func_in(PM_rd4[9]), .SI(wp_s_151), .SO(wp_s_152), .VCI(core_PM_rd4[9]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_PM_rd5_0_ (
.Func_in(PM_rd5[0]), .SI(wp_s_176), .SO(wp_s_177), .VCI(core_PM_rd5[0]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_PM_rd5_10_ (
.Func_in(PM_rd5[10]), .SI(wp_s_166), .SO(wp_s_167), .VCI(core_PM_rd5[10]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_PM_rd5_11_ (
.Func_in(PM_rd5[11]), .SI(wp_s_165), .SO(wp_s_166), .VCI(core_PM_rd5[11]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_PM_rd5_12_ (
.Func_in(PM_rd5[12]), .SI(wp_s_164), .SO(wp_s_165), .VCI(core_PM_rd5[12]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_PM_rd5_13_ (
.Func_in(PM_rd5[13]), .SI(wp_s_163), .SO(wp_s_164), .VCI(core_PM_rd5[13]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_PM_rd5_14_ (
.Func_in(PM_rd5[14]), .SI(wp_s_162), .SO(wp_s_163), .VCI(core_PM_rd5[14]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_PM_rd5_15_ (
.Func_in(PM_rd5[15]), .SI(wp_s_161), .SO(wp_s_162), .VCI(core_PM_rd5[15]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_PM_rd5_1_ (
.Func_in(PM_rd5[1]), .SI(wp_s_175), .SO(wp_s_176), .VCI(core_PM_rd5[1]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_PM_rd5_2_ (
.Func_in(PM_rd5[2]), .SI(wp_s_174), .SO(wp_s_175), .VCI(core_PM_rd5[2]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_PM_rd5_3_ (
.Func_in(PM_rd5[3]), .SI(wp_s_173), .SO(wp_s_174), .VCI(core_PM_rd5[3]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_PM_rd5_4_ (
.Func_in(PM_rd5[4]), .SI(wp_s_172), .SO(wp_s_173), .VCI(core_PM_rd5[4]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_PM_rd5_5_ (
.Func_in(PM_rd5[5]), .SI(wp_s_171), .SO(wp_s_172), .VCI(core_PM_rd5[5]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_PM_rd5_6_ (
.Func_in(PM_rd5[6]), .SI(wp_s_170), .SO(wp_s_171), .VCI(core_PM_rd5[6]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_PM_rd5_7_ (
.Func_in(PM_rd5[7]), .SI(wp_s_169), .SO(wp_s_170), .VCI(core_PM_rd5[7]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_PM_rd5_8_ (
.Func_in(PM_rd5[8]), .SI(wp_s_168), .SO(wp_s_169), .VCI(core_PM_rd5[8]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_PM_rd5_9_ (
.Func_in(PM_rd5[9]), .SI(wp_s_167), .SO(wp_s_168), .VCI(core_PM_rd5[9]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_PM_rd6_0_ (
.Func_in(PM_rd6[0]), .SI(wp_s_192), .SO(wp_s_193), .VCI(core_PM_rd6[0]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_PM_rd6_10_ (
.Func_in(PM_rd6[10]), .SI(wp_s_182), .SO(wp_s_183), .VCI(core_PM_rd6[10]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_PM_rd6_11_ (
.Func_in(PM_rd6[11]), .SI(wp_s_181), .SO(wp_s_182), .VCI(core_PM_rd6[11]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_PM_rd6_12_ (
.Func_in(PM_rd6[12]), .SI(wp_s_180), .SO(wp_s_181), .VCI(core_PM_rd6[12]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_PM_rd6_13_ (
.Func_in(PM_rd6[13]), .SI(wp_s_179), .SO(wp_s_180), .VCI(core_PM_rd6[13]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_PM_rd6_14_ (
.Func_in(PM_rd6[14]), .SI(wp_s_178), .SO(wp_s_179), .VCI(core_PM_rd6[14]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_PM_rd6_15_ (
.Func_in(PM_rd6[15]), .SI(wp_s_177), .SO(wp_s_178), .VCI(core_PM_rd6[15]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_PM_rd6_1_ (
.Func_in(PM_rd6[1]), .SI(wp_s_191), .SO(wp_s_192), .VCI(core_PM_rd6[1]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_PM_rd6_2_ (
.Func_in(PM_rd6[2]), .SI(wp_s_190), .SO(wp_s_191), .VCI(core_PM_rd6[2]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_PM_rd6_3_ (
.Func_in(PM_rd6[3]), .SI(wp_s_189), .SO(wp_s_190), .VCI(core_PM_rd6[3]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_PM_rd6_4_ (
.Func_in(PM_rd6[4]), .SI(wp_s_188), .SO(wp_s_189), .VCI(core_PM_rd6[4]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_PM_rd6_5_ (
.Func_in(PM_rd6[5]), .SI(wp_s_187), .SO(wp_s_188), .VCI(core_PM_rd6[5]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_PM_rd6_6_ (
.Func_in(PM_rd6[6]), .SI(wp_s_186), .SO(wp_s_187), .VCI(core_PM_rd6[6]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_PM_rd6_7_ (
.Func_in(PM_rd6[7]), .SI(wp_s_185), .SO(wp_s_186), .VCI(core_PM_rd6[7]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_PM_rd6_8_ (
.Func_in(PM_rd6[8]), .SI(wp_s_184), .SO(wp_s_185), .VCI(core_PM_rd6[8]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_PM_rd6_9_ (
.Func_in(PM_rd6[9]), .SI(wp_s_183), .SO(wp_s_184), .VCI(core_PM_rd6[9]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_PM_rd7_0_ (
.Func_in(PM_rd7[0]), .SI(wp_s_208), .SO(wp_s_209), .VCI(core_PM_rd7[0]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_PM_rd7_10_ (
.Func_in(PM_rd7[10]), .SI(wp_s_198), .SO(wp_s_199), .VCI(core_PM_rd7[10]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_PM_rd7_11_ (
.Func_in(PM_rd7[11]), .SI(wp_s_197), .SO(wp_s_198), .VCI(core_PM_rd7[11]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_PM_rd7_12_ (
.Func_in(PM_rd7[12]), .SI(wp_s_196), .SO(wp_s_197), .VCI(core_PM_rd7[12]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_PM_rd7_13_ (
.Func_in(PM_rd7[13]), .SI(wp_s_195), .SO(wp_s_196), .VCI(core_PM_rd7[13]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_PM_rd7_14_ (
.Func_in(PM_rd7[14]), .SI(wp_s_194), .SO(wp_s_195), .VCI(core_PM_rd7[14]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_PM_rd7_15_ (
.Func_in(PM_rd7[15]), .SI(wp_s_193), .SO(wp_s_194), .VCI(core_PM_rd7[15]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_PM_rd7_1_ (
.Func_in(PM_rd7[1]), .SI(wp_s_207), .SO(wp_s_208), .VCI(core_PM_rd7[1]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_PM_rd7_2_ (
.Func_in(PM_rd7[2]), .SI(wp_s_206), .SO(wp_s_207), .VCI(core_PM_rd7[2]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_PM_rd7_3_ (
.Func_in(PM_rd7[3]), .SI(wp_s_205), .SO(wp_s_206), .VCI(core_PM_rd7[3]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_PM_rd7_4_ (
.Func_in(PM_rd7[4]), .SI(wp_s_204), .SO(wp_s_205), .VCI(core_PM_rd7[4]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_PM_rd7_5_ (
.Func_in(PM_rd7[5]), .SI(wp_s_203), .SO(wp_s_204), .VCI(core_PM_rd7[5]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_PM_rd7_6_ (
.Func_in(PM_rd7[6]), .SI(wp_s_202), .SO(wp_s_203), .VCI(core_PM_rd7[6]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_PM_rd7_7_ (
.Func_in(PM_rd7[7]), .SI(wp_s_201), .SO(wp_s_202), .VCI(core_PM_rd7[7]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_PM_rd7_8_ (
.Func_in(PM_rd7[8]), .SI(wp_s_200), .SO(wp_s_201), .VCI(core_PM_rd7[8]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_PM_rd7_9_ (
.Func_in(PM_rd7[9]), .SI(wp_s_199), .SO(wp_s_200), .VCI(core_PM_rd7[9]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_PM_wd_0_ (
.Func_out(PM_wd[0]), .SI(wp_s_754), .SO(wp_s_755), .VCO(core_PM_wd[0]),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_PM_wd_10_ (
.Func_out(PM_wd[10]), .SI(wp_s_744), .SO(wp_s_745), .VCO(core_PM_wd[10]),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_PM_wd_11_ (
.Func_out(PM_wd[11]), .SI(wp_s_743), .SO(wp_s_744), .VCO(core_PM_wd[11]),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_PM_wd_12_ (
.Func_out(PM_wd[12]), .SI(wp_s_742), .SO(wp_s_743), .VCO(core_PM_wd[12]),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_PM_wd_13_ (
.Func_out(PM_wd[13]), .SI(wp_s_741), .SO(wp_s_742), .VCO(core_PM_wd[13]),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_PM_wd_14_ (
.Func_out(PM_wd[14]), .SI(wp_s_740), .SO(wp_s_741), .VCO(core_PM_wd[14]),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_PM_wd_15_ (
.Func_out(PM_wd[15]), .SI(wp_s_739), .SO(wp_s_740), .VCO(core_PM_wd[15]),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_PM_wd_1_ (
.Func_out(PM_wd[1]), .SI(wp_s_753), .SO(wp_s_754), .VCO(core_PM_wd[1]),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_PM_wd_2_ (
.Func_out(PM_wd[2]), .SI(wp_s_752), .SO(wp_s_753), .VCO(core_PM_wd[2]),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_PM_wd_3_ (
.Func_out(PM_wd[3]), .SI(wp_s_751), .SO(wp_s_752), .VCO(core_PM_wd[3]),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_PM_wd_4_ (
.Func_out(PM_wd[4]), .SI(wp_s_750), .SO(wp_s_751), .VCO(core_PM_wd[4]),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_PM_wd_5_ (
.Func_out(PM_wd[5]), .SI(wp_s_749), .SO(wp_s_750), .VCO(core_PM_wd[5]),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_PM_wd_6_ (
.Func_out(PM_wd[6]), .SI(wp_s_748), .SO(wp_s_749), .VCO(core_PM_wd[6]),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_PM_wd_7_ (
.Func_out(PM_wd[7]), .SI(wp_s_747), .SO(wp_s_748), .VCO(core_PM_wd[7]),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_PM_wd_8_ (
.Func_out(PM_wd[8]), .SI(wp_s_746), .SO(wp_s_747), .VCO(core_PM_wd[8]),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_PM_wd_9_ (
.Func_out(PM_wd[9]), .SI(wp_s_745), .SO(wp_s_746), .VCO(core_PM_wd[9]),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_PMo_cs0 (
.Func_out(PMo_cs0), .SI(wp_s_684), .SO(wp_s_685), .VCO(core_PMo_cs0),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_PMo_cs1 (
.Func_out(PMo_cs1), .SI(wp_s_685), .SO(wp_s_686), .VCO(core_PMo_cs1),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_PMo_cs2 (
.Func_out(PMo_cs2), .SI(wp_s_686), .SO(wp_s_687), .VCO(core_PMo_cs2),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_PMo_cs3 (
.Func_out(PMo_cs3), .SI(wp_s_687), .SO(wp_s_688), .VCO(core_PMo_cs3),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_PMo_cs4 (
.Func_out(PMo_cs4), .SI(wp_s_688), .SO(wp_s_689), .VCO(core_PMo_cs4),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_PMo_cs5 (
.Func_out(PMo_cs5), .SI(wp_s_689), .SO(wp_s_690), .VCO(core_PMo_cs5),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_PMo_cs6 (
.Func_out(PMo_cs6), .SI(wp_s_690), .SO(wp_s_691), .VCO(core_PMo_cs6),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_PMo_cs7 (
.Func_out(PMo_cs7), .SI(wp_s_691), .SO(wp_s_692), .VCO(core_PMo_cs7),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_PMo_oe0 (
.Func_out(PMo_oe0), .SI(wp_s_693), .SO(wp_s_694), .VCO(core_PMo_oe0),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_PMo_oe1 (
.Func_out(PMo_oe1), .SI(wp_s_694), .SO(wp_s_695), .VCO(core_PMo_oe1),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_PMo_oe2 (
.Func_out(PMo_oe2), .SI(wp_s_695), .SO(wp_s_696), .VCO(core_PMo_oe2),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_PMo_oe3 (
.Func_out(PMo_oe3), .SI(wp_s_696), .SO(wp_s_697), .VCO(core_PMo_oe3),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_PMo_oe4 (
.Func_out(PMo_oe4), .SI(wp_s_697), .SO(wp_s_698), .VCO(core_PMo_oe4),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_PMo_oe5 (
.Func_out(PMo_oe5), .SI(wp_s_698), .SO(wp_s_699), .VCO(core_PMo_oe5),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_PMo_oe6 (
.Func_out(PMo_oe6), .SI(wp_s_699), .SO(wp_s_700), .VCO(core_PMo_oe6),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_PMo_oe7 (
.Func_out(PMo_oe7), .SI(wp_s_700), .SO(wp_s_701), .VCO(core_PMo_oe7),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_PMo_web (
.Func_out(PMo_web), .SI(wp_s_692), .SO(wp_s_693), .VCO(core_PMo_web),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_PWDACK (
.Func_out(PWDACK), .SI(wp_s_580), .SO(wp_s_581), .VCO(core_PWDACK),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_RDn (
.Func_out(RDn), .SI(wp_s_588), .SO(wp_s_589), .VCO(core_RDn),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_RFS0 (
.Func_out(RFS0), .SI(wp_s_632), .SO(wp_s_633), .VCO(core_RFS0),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_RFS1 (
.Func_out(RFS1), .SI(wp_s_636), .SO(wp_s_637), .VCO(core_RFS1),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_SCLK0 (
.Func_out(SCLK0), .SI(wp_s_628), .SO(wp_s_629), .VCO(core_SCLK0),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_SCLK1 (
.Func_out(SCLK1), .SI(wp_s_630), .SO(wp_s_631), .VCO(core_SCLK1),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_TD0 (
.Func_out(TD0), .SI(wp_s_626), .SO(wp_s_627), .VCO(core_TD0),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_TD1 (
.Func_out(TD1), .SI(wp_s_627), .SO(wp_s_628), .VCO(core_TD1),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_TFS0 (
.Func_out(TFS0), .SI(wp_s_634), .SO(wp_s_635), .VCO(core_TFS0),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_TFS1 (
.Func_out(TFS1), .SI(wp_s_638), .SO(wp_s_639), .VCO(core_TFS1),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_T_BMODE (
.Func_in(T_BMODE), .SI(wp_s_1), .SO(wp_s_2), .VCI(core_T_BMODE),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_T_BRn (
.Func_in(T_BRn), .SI(wp_s_34), .SO(wp_s_35), .VCI(core_T_BRn),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_T_CLKI_PLL (
.Func_in(T_CLKI_PLL), .SI(wp_s_3), .SO(wp_s_4), .VCI(core_T_CLKI_PLL),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_T_EA_0_ (
.Func_in(T_EA[0]), .SI(wp_s_31), .SO(wp_s_32), .VCI(core_T_EA[0]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_T_EA_1_ (
.Func_in(T_EA[1]), .SI(wp_s_30), .SO(wp_s_31), .VCI(core_T_EA[1]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_T_EA_2_ (
.Func_in(T_EA[2]), .SI(wp_s_29), .SO(wp_s_30), .VCI(core_T_EA[2]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_T_EA_3_ (
.Func_in(T_EA[3]), .SI(wp_s_28), .SO(wp_s_29), .VCI(core_T_EA[3]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_T_EA_4_ (
.Func_in(T_EA[4]), .SI(wp_s_27), .SO(wp_s_28), .VCI(core_T_EA[4]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_T_EA_5_ (
.Func_in(T_EA[5]), .SI(wp_s_26), .SO(wp_s_27), .VCI(core_T_EA[5]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_T_EA_6_ (
.Func_in(T_EA[6]), .SI(wp_s_25), .SO(wp_s_26), .VCI(core_T_EA[6]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_T_EA_7_ (
.Func_in(T_EA[7]), .SI(wp_s_24), .SO(wp_s_25), .VCI(core_T_EA[7]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_T_ED_0_ (
.Func_in(T_ED[0]), .SI(wp_s_23), .SO(wp_s_24), .VCI(core_T_ED[0]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_T_ED_10_ (
.Func_in(T_ED[10]), .SI(wp_s_13), .SO(wp_s_14), .VCI(core_T_ED[10]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_T_ED_11_ (
.Func_in(T_ED[11]), .SI(wp_s_12), .SO(wp_s_13), .VCI(core_T_ED[11]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_T_ED_12_ (
.Func_in(T_ED[12]), .SI(wp_s_11), .SO(wp_s_12), .VCI(core_T_ED[12]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_T_ED_13_ (
.Func_in(T_ED[13]), .SI(wp_s_10), .SO(wp_s_11), .VCI(core_T_ED[13]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_T_ED_14_ (
.Func_in(T_ED[14]), .SI(wp_s_9), .SO(wp_s_10), .VCI(core_T_ED[14]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_T_ED_15_ (
.Func_in(T_ED[15]), .SI(wp_s_8), .SO(wp_s_9), .VCI(core_T_ED[15]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_T_ED_1_ (
.Func_in(T_ED[1]), .SI(wp_s_22), .SO(wp_s_23), .VCI(core_T_ED[1]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_T_ED_2_ (
.Func_in(T_ED[2]), .SI(wp_s_21), .SO(wp_s_22), .VCI(core_T_ED[2]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_T_ED_3_ (
.Func_in(T_ED[3]), .SI(wp_s_20), .SO(wp_s_21), .VCI(core_T_ED[3]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_T_ED_4_ (
.Func_in(T_ED[4]), .SI(wp_s_19), .SO(wp_s_20), .VCI(core_T_ED[4]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_T_ED_5_ (
.Func_in(T_ED[5]), .SI(wp_s_18), .SO(wp_s_19), .VCI(core_T_ED[5]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_T_ED_6_ (
.Func_in(T_ED[6]), .SI(wp_s_17), .SO(wp_s_18), .VCI(core_T_ED[6]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_T_ED_7_ (
.Func_in(T_ED[7]), .SI(wp_s_16), .SO(wp_s_17), .VCI(core_T_ED[7]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_T_ED_8_ (
.Func_in(T_ED[8]), .SI(wp_s_15), .SO(wp_s_16), .VCI(core_T_ED[8]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_T_ED_9_ (
.Func_in(T_ED[9]), .SI(wp_s_14), .SO(wp_s_15), .VCI(core_T_ED[9]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_T_GOICE (
.Func_in(T_GOICE), .SI(wp_s_5), .SO(wp_s_6), .VCI(core_T_GOICE),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_T_IAD_0_ (
.Func_in(T_IAD[0]), .SI(wp_s_66), .SO(wp_s_67), .VCI(core_T_IAD[0]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_T_IAD_10_ (
.Func_in(T_IAD[10]), .SI(wp_s_56), .SO(wp_s_57), .VCI(core_T_IAD[10]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_T_IAD_11_ (
.Func_in(T_IAD[11]), .SI(wp_s_55), .SO(wp_s_56), .VCI(core_T_IAD[11]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_T_IAD_12_ (
.Func_in(T_IAD[12]), .SI(wp_s_54), .SO(wp_s_55), .VCI(core_T_IAD[12]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_T_IAD_13_ (
.Func_in(T_IAD[13]), .SI(wp_s_53), .SO(wp_s_54), .VCI(core_T_IAD[13]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_T_IAD_14_ (
.Func_in(T_IAD[14]), .SI(wp_s_52), .SO(wp_s_53), .VCI(core_T_IAD[14]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_T_IAD_15_ (
.Func_in(T_IAD[15]), .SI(wp_s_51), .SO(wp_s_52), .VCI(core_T_IAD[15]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_T_IAD_1_ (
.Func_in(T_IAD[1]), .SI(wp_s_65), .SO(wp_s_66), .VCI(core_T_IAD[1]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_T_IAD_2_ (
.Func_in(T_IAD[2]), .SI(wp_s_64), .SO(wp_s_65), .VCI(core_T_IAD[2]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_T_IAD_3_ (
.Func_in(T_IAD[3]), .SI(wp_s_63), .SO(wp_s_64), .VCI(core_T_IAD[3]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_T_IAD_4_ (
.Func_in(T_IAD[4]), .SI(wp_s_62), .SO(wp_s_63), .VCI(core_T_IAD[4]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_T_IAD_5_ (
.Func_in(T_IAD[5]), .SI(wp_s_61), .SO(wp_s_62), .VCI(core_T_IAD[5]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_T_IAD_6_ (
.Func_in(T_IAD[6]), .SI(wp_s_60), .SO(wp_s_61), .VCI(core_T_IAD[6]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_T_IAD_7_ (
.Func_in(T_IAD[7]), .SI(wp_s_59), .SO(wp_s_60), .VCI(core_T_IAD[7]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_T_IAD_8_ (
.Func_in(T_IAD[8]), .SI(wp_s_58), .SO(wp_s_59), .VCI(core_T_IAD[8]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_T_IAD_9_ (
.Func_in(T_IAD[9]), .SI(wp_s_57), .SO(wp_s_58), .VCI(core_T_IAD[9]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_T_IAL (
.Func_in(T_IAL), .SI(wp_s_50), .SO(wp_s_51), .VCI(core_T_IAL),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_T_ICE_RSTn (
.Func_in(T_ICE_RSTn), .SI(wp_s_0), .SO(wp_s_1), .VCI(core_T_ICE_RSTn),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_T_ID (
.Func_in(T_ID), .SI(wp_s_80), .SO(wp_s_81), .VCI(core_T_ID), .WP_CLK(WP_CLK),
.WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_T_IMS (
.Func_in(T_IMS), .SI(wp_s_79), .SO(wp_s_80), .VCI(core_T_IMS),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_T_IRDn (
.Func_in(T_IRDn), .SI(wp_s_47), .SO(wp_s_48), .VCI(core_T_IRDn),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_T_IRQ0n (
.Func_in(T_IRQ0n), .SI(wp_s_37), .SO(wp_s_38), .VCI(core_T_IRQ0n),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_T_IRQ1n (
.Func_in(T_IRQ1n), .SI(wp_s_36), .SO(wp_s_37), .VCI(core_T_IRQ1n),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_T_IRQ2n (
.Func_in(T_IRQ2n), .SI(wp_s_35), .SO(wp_s_36), .VCI(core_T_IRQ2n),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_T_IRQE0n (
.Func_in(T_IRQE0n), .SI(wp_s_40), .SO(wp_s_41), .VCI(core_T_IRQE0n),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_T_IRQE1n (
.Func_in(T_IRQE1n), .SI(wp_s_39), .SO(wp_s_40), .VCI(core_T_IRQE1n),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_T_IRQL1n (
.Func_in(T_IRQL1n), .SI(wp_s_38), .SO(wp_s_39), .VCI(core_T_IRQL1n),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_T_ISn (
.Func_in(T_ISn), .SI(wp_s_49), .SO(wp_s_50), .VCI(core_T_ISn),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_T_IWRn (
.Func_in(T_IWRn), .SI(wp_s_48), .SO(wp_s_49), .VCI(core_T_IWRn),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_T_MMAP (
.Func_in(T_MMAP), .SI(wp_s_2), .SO(wp_s_3), .VCI(core_T_MMAP),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_T_PIOin_0_ (
.Func_in(T_PIOin[0]), .SI(wp_s_78), .SO(wp_s_79), .VCI(core_T_PIOin[0]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_T_PIOin_10_ (
.Func_in(T_PIOin[10]), .SI(wp_s_68), .SO(wp_s_69), .VCI(core_T_PIOin[10]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_T_PIOin_11_ (
.Func_in(T_PIOin[11]), .SI(wp_s_67), .SO(wp_s_68), .VCI(core_T_PIOin[11]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_T_PIOin_1_ (
.Func_in(T_PIOin[1]), .SI(wp_s_77), .SO(wp_s_78), .VCI(core_T_PIOin[1]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_T_PIOin_2_ (
.Func_in(T_PIOin[2]), .SI(wp_s_76), .SO(wp_s_77), .VCI(core_T_PIOin[2]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_T_PIOin_3_ (
.Func_in(T_PIOin[3]), .SI(wp_s_75), .SO(wp_s_76), .VCI(core_T_PIOin[3]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_T_PIOin_4_ (
.Func_in(T_PIOin[4]), .SI(wp_s_74), .SO(wp_s_75), .VCI(core_T_PIOin[4]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_T_PIOin_5_ (
.Func_in(T_PIOin[5]), .SI(wp_s_73), .SO(wp_s_74), .VCI(core_T_PIOin[5]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_T_PIOin_6_ (
.Func_in(T_PIOin[6]), .SI(wp_s_72), .SO(wp_s_73), .VCI(core_T_PIOin[6]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_T_PIOin_7_ (
.Func_in(T_PIOin[7]), .SI(wp_s_71), .SO(wp_s_72), .VCI(core_T_PIOin[7]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_T_PIOin_8_ (
.Func_in(T_PIOin[8]), .SI(wp_s_70), .SO(wp_s_71), .VCI(core_T_PIOin[8]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_T_PIOin_9_ (
.Func_in(T_PIOin[9]), .SI(wp_s_69), .SO(wp_s_70), .VCI(core_T_PIOin[9]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_T_PWDn (
.Func_in(T_PWDn), .SI(wp_s_33), .SO(wp_s_34), .VCI(core_T_PWDn),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_T_RD0 (
.Func_in(T_RD0), .SI(wp_s_41), .SO(wp_s_42), .VCI(core_T_RD0),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_T_RD1 (
.Func_in(T_RD1), .SI(wp_s_42), .SO(wp_s_43), .VCI(core_T_RD1),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_T_RFS0 (
.Func_in(T_RFS0), .SI(wp_s_43), .SO(wp_s_44), .VCI(core_T_RFS0),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_T_RFS1 (
.Func_in(T_RFS1), .SI(wp_s_45), .SO(wp_s_46), .VCI(core_T_RFS1),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_T_Sel_PLL (
.Func_in(T_Sel_PLL), .SI(wp_s_4), .SO(wp_s_5), .VCI(core_T_Sel_PLL),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_T_TFS0 (
.Func_in(T_TFS0), .SI(wp_s_44), .SO(wp_s_45), .VCI(core_T_TFS0),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_T_TFS1 (
.Func_in(T_TFS1), .SI(wp_s_46), .SO(wp_s_47), .VCI(core_T_TFS1),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_T_TMODE_0_ (
.Func_in(T_TMODE[0]), .SI(wp_s_7), .SO(wp_s_8), .VCI(core_T_TMODE[0]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_in WC_T_TMODE_1_ (
.Func_in(T_TMODE[1]), .SI(wp_s_6), .SO(wp_s_7), .VCI(core_T_TMODE[1]),
.WP_CLK(WP_CLK), .WP_HOLD_IN(WP_HOLD_IN), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_WRn (
.Func_out(WRn), .SI(wp_s_589), .SO(wp_s_590), .VCO(core_WRn),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
DSP_CORE_vsia_tst_wp_cell_out WC_XTALoffn (
.Func_out(XTALoffn), .SI(wp_s_579), .SO(wp_s_580), .VCO(core_XTALoffn),
.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .WP_SHIFT(WP_SHIFT)
);
assign WP_SO_beforeskew = wp_s_837;
assign wp_s_0 = WP_SI;
endmodule
module DSP_CORE_vsia_tst_wp_cell_in (
Func_in, SI, VCI, SO,
WP_SHIFT, WP_HOLD_IN,
WP_CLK
);
//data
input Func_in;
input SI;
output VCI;
output SO;
//control
input WP_SHIFT;
input WP_HOLD_IN;
//clock
input WP_CLK;
reg SO;
assign VCI = (WP_HOLD_IN) ? SO : Func_in;
always @(posedge WP_CLK) begin
SO <= (WP_SHIFT) ? SI : VCI;
end
endmodule
module DSP_CORE_vsia_tst_wp_cell_out (
VCO, SI, Func_out, SO,
WP_SHIFT, WP_HOLD_OUT,
WP_CLK
);
//data
input VCO;
input SI;
output Func_out;
output SO;
//control
input WP_SHIFT;
input WP_HOLD_OUT;
//clock
input WP_CLK;
reg SO;
assign Func_out = (WP_HOLD_OUT) ? SO : VCO;
always @(posedge WP_CLK) begin
SO <= (WP_SHIFT) ? SI : Func_out;
end
endmodule
module DSP_CORE_vsia_tst_tcb_cell (
SI, SO, DO,
TC_SHIFT, TC_UPDATE, TC_RESET,
TCLK
);
//data I/O
input SI;
output SO;
output DO;
//control signals
input TC_SHIFT;
input TC_UPDATE;
input TC_RESET;
//clock
input TCLK;
reg SO, DO;
always @(posedge TCLK or posedge TC_RESET) begin
if(TC_RESET)
SO <= 1'b0;
else
SO <= (TC_SHIFT) ? SI : SO;
end
always @(posedge TCLK or posedge TC_RESET) begin
if(TC_RESET)
DO <= 1'b0;
else
DO <= (TC_UPDATE) ? SO : DO;
end
endmodule
module DSP_CORE_vsia_tst_tcb_cell_capture (
SI, DI, SO, DO,
TC_SHIFT, TC_UPDATE, TC_CAPTURE, TC_RESET,
TCLK
);
//data I/O
input SI;
input DI;
output SO;
output DO;
//control signals
input TC_SHIFT;
input TC_UPDATE;
input TC_CAPTURE;
input TC_RESET;
//clock
input TCLK;
reg SO, DO;
always @(posedge TCLK or posedge TC_RESET) begin
if(TC_RESET)
SO <= 1'b0;
else
SO <= (TC_CAPTURE) ? DI : (TC_SHIFT) ? SI : SO;
end
always @(posedge TCLK or posedge TC_RESET) begin
if(TC_RESET)
DO <= 1'b0;
else
DO <= (TC_UPDATE) ? SO : DO;
end
endmodule
module DSP_CORE_vsia_tst_bypass_reg (
SI, SO_BYPASS,
TCLK
);
//data I/O
input SI;
output SO_BYPASS;
//clock
input TCLK;
reg SO_BYPASS;
always @(posedge TCLK) begin
SO_BYPASS <= SI;
end
endmodule
module DSP_CORE_vsia_tst_antiskew (
SI, SO,
TCLK
);
input SI;
output SO;
input TCLK;
reg SO;
always @(TCLK or SI) begin
if(~TCLK)
SO <= SI;
end
endmodule
module DSP_CORE_vsia_tst_mas (
SO_BYPASS, SO_beforeskew, SO,
WP_BP, TCLK
);
//data I/O
input SO_BYPASS; //wp_reg bypass
input SO_beforeskew;
output SO;
//control
input WP_BP;
input TCLK;
reg SO;
always @(TCLK or SO_BYPASS or SO_beforeskew or WP_BP) begin
if(~TCLK)
SO <= (WP_BP) ? SO_BYPASS : SO_beforeskew;
end
endmodule
module DSP_CORE_vsia_tst_hold_cell (
IN, OUT, TCLK, RST_L
);
input IN;
output OUT;
input TCLK;
input RST_L;
reg OUT;
always @(posedge TCLK or negedge RST_L) begin
if(RST_L == 0)
OUT <= 0;
else
OUT <= IN | OUT;
end
endmodule
module DSP_CORE_vsia_tst_capture_cell (
SI, DI, SO,
SEL, TCLK
);
input SI;
input DI;
output SO;
input SEL;
input TCLK;
reg SO;
always @(posedge TCLK) begin
SO <= (SEL) ? SI : DI;
end
endmodule
module DSP_CORE_vsia_tst_control_cell (
SI, SO, SEL,
TCLK
);
input SI;
input SEL;
output SO;
input TCLK;
reg SO;
always @(posedge TCLK) begin
SO <= (SEL) ? SI : SO;
end
endmodule
|
/*--------------------------------------------------------------*/
/*--------------------------------------------------------------*/
/*--------------------------------------------------------------*/
/*--------------------------------------------------------------*/
`define del 1
`include "../include/x_def.v"
module EA_ALU(/*------------------ Inputs -------------------*/
DSPCLK, GO_E, GO_C, EX_en, EX_enc,
R_in_E,
condAM_E, DIVQ_E, DIVS_E, DOUBLE_E,
MTAR_E, MTAX0_E, MTAX1_E, MTAY0_E, MTAY1_E, BYPASSR_D,
MFAR_E, MFAX0_E, MFAX1_E, MFAY0_E, MFAY1_E, MFASTAT_E,
MFALU_E, pMFALU_E, accPM_E, GO_MAC, ALUop_E, updAR_E,
updAF_E, ALUop_R, type9, T_RST, DIVQ_R, DIVS_R,
Xop_D, YY_D, CC_D, BO_D,
Xop_E, Yop_E, CC_E, BO_E,
AMF_D,
SHADOW, satAR,
ASTAT,
`ifdef FD_DFT
SCAN_TEST,
`endif
R_alu_E, R_alu_D,
updateALU, updateDIV, ABS, ASin, AQin, ACin,
AVin, ANin, AZin,
DMDin, DMDalu, PMDin, PMDalu);
input DSPCLK, GO_E, GO_C, EX_en, EX_enc;
input [15:0] R_in_E;
input condAM_E, DIVQ_E, DIVS_E, DIVQ_R, DIVS_R, DOUBLE_E;
input MTAR_E, MTAX0_E, MTAX1_E, MTAY0_E, MTAY1_E, BYPASSR_D;
input MFAR_E, MFAX0_E, MFAX1_E, MFAY0_E, MFAY1_E, MFASTAT_E;
input [2:0] Xop_D, Xop_E;
input [4:0] AMF_D;
input [1:0] YY_D, CC_D, BO_D, Yop_E, CC_E, BO_E;
input SHADOW, satAR;
input MFALU_E, pMFALU_E, accPM_E;
input GO_MAC;
input [7:0] ASTAT;
input ALUop_E, updAR_E, updAF_E;
input ALUop_R, type9, T_RST;
`ifdef FD_DFT
input SCAN_TEST;
`endif
output [15:0] R_alu_E, R_alu_D;
output updateALU, updateDIV;
output ABS, ASin, AQin, ACin, AVin, ANin, AZin;
input [15:0] DMDin;
output [15:0] DMDalu;
input [15:0] PMDin;
output [15:0] PMDalu;
/*------------------------------------------*/
wire X15, Y15, cout, ovf_, zeroAX, zeroAY;
wire selAX, updateDIV, selAY, selAF, invAX;
wire invAY, Rstore_AR_E, qin, selCT;
wire updateAX0s, updateAX1r, updateAX1s;
wire updateAY0r, updateAY0s, updateAY1r;
wire updateAY1s, updateAFr, updateAFs;
wire updateARr, updateARs, updateAX0r;
wire K, L, ADD, Cin;
wire [15:0] ALU, CONST_E, X, Y;
EA_DEC ea_dec(/* In */
DSPCLK, GO_E, GO_C, EX_en, EX_enc,
condAM_E, DIVQ_E, DIVS_E, SHADOW,
MTAX0_E, MTAX1_E, MTAY0_E, MTAY1_E, X15, Y15,
cout, ovf_, satAR, ASTAT[5], ASTAT[3], Xop_D[2:0], Xop_E[2:0], Yop_E[1:0],
YY_D[1:0], CC_D[1:0], BO_D[1:0], CC_E[1:0], BO_E[1:0],
AMF_D[4:0], ALU[15:0], ALUop_E, updAR_E, updAF_E,
MTAR_E, ALUop_R, type9, T_RST, DIVQ_R, DIVS_R,
`ifdef FD_DFT
SCAN_TEST,
`endif
Rstore_AR_D, Rstore_AR_E, updateALU, updateDIV, updateAFr,
updateAFs, updateARr, updateARs, updateAX0r, updateAX0s,
updateAX1r, updateAX1s, updateAY0r, updateAY0s, updateAY1r,
updateAY1s, ABS, zeroAX, invAX, zeroAY, invAY, Cin, selAX,
selAY, selAF, selCT, K, L, ADD, ASin, AQin, ACin, AVin, ANin,
AZin, qin, CONST_E[15:0]);
EA_REG ea_reg(/* IN */
DSPCLK, SHADOW, Xop_E[0], zeroAX, zeroAY,
selAX, DOUBLE_E, updateDIV, Yop_E[0], ACin, AVin, satAR,
selAY, updateAX0r, updateAX0s, updateAX1r,
updateAX1s, updateAY0r, updateAY0s, updateAY1r,
updateAY1s, updateAFr, updateAFs, MTAR_E,
updateARr, updateARs, MFAX0_E, MFAX1_E, R_in_E[15:0],
MFAY0_E, MFAY1_E, MFAR_E, MFASTAT_E, ALU[15:0], selAF,
invAX, invAY, Rstore_AR_D, Rstore_AR_E, qin,
ASTAT[7:0], selCT, CONST_E[15:0], BYPASSR_D, MFALU_E,
pMFALU_E, accPM_E, GO_MAC, EX_enc, GO_C,
`ifdef FD_DFT
SCAN_TEST,
`endif
X[15:0], Y[15:0], X15, Y15, R_alu_E[15:0], R_alu_D[15:0],
DMDin[15:0], DMDalu[15:0], PMDin[15:0], PMDalu[15:0]);
EA_CORE ea_core(K, L, ADD, Cin, X, Y, cout, ovf_, ALU);
endmodule
|
`define del 1
`include "../include/x_def.v"
module EA_CORE (K, L, ADD, Cin, X, Y, cout, ovf_, ALU);
/********************************/
/********************************/
input K, L, ADD, Cin;
input [16:1] X, Y;
/********************************/
/********************************/
output cout, ovf_;
output [16:1] ALU;
/***********************************/
/***********************************/
wire [16:1] P, G, AL;
assign P[16:1] = X[16:1] | Y[16:1];
assign G[16:1] = X[16:1] & Y[16:1];
wire K_ = ~K;
assign #`da AL = ( (X[16:1] & Y[16:1]) & {16{K_}} ) |
( (X[16:1] ^ Y[16:1]) & {16{L}} ) ;
wire [8:1] G1;
wire GS;
assign GS = Cin ? (G[1] | P[2]) : G[1];
assign G1[1] = G[2] | (P[1] & GS);
assign G1[2] = G[4] | (P[6] & G[3]);
assign G1[3] = G[6] | (P[4] & G[5]);
assign G1[4] = G[8] | (P[8] & G[7]);
assign G1[5] = G[10] | (P[12] & G[9]);
assign G1[6] = G[12] | (P[10] & G[11]);
assign G1[7] = G[14] | (P[16] & G[13]);
assign G1[8] = G[16] | (P[14] & G[15]);
wire [8:1] P1;
assign P1[1] = P[2] & P[1];
assign P1[2] = P[4] & P[3];
assign P1[3] = P[6] & P[5];
assign P1[4] = P[8] & P[7];
assign P1[5] = P[10] & P[9];
assign P1[6] = P[12] & P[11];
assign P1[7] = P[14] & P[13];
assign P1[8] = P[16] & P[15];
wire [4:1] G2;
assign G2[1] = G1[2] | (P1[2] & G1[1]);
assign G2[2] = G1[4] | (P1[4] & G1[3]);
assign G2[3] = G1[6] | (P1[6] & G1[5]);
assign G2[4] = G1[8] | (P1[8] & G1[7]);
wire [4:1] P2;
assign P2[1] = P1[2] & P1[1];
assign P2[2] = P1[4] & P1[3];
assign P2[3] = P1[6] & P1[5];
assign P2[4] = P1[8] & P1[7];
wire [2:1] G3;
assign G3[1] = G2[2] | (P2[2] & G2[1]);
assign G3[2] = G2[4] | (P2[4] & G2[3]);
wire [2:1] P3;
assign P3[1] = P2[2] & P2[1];
assign P3[2] = P2[4] & P2[3];
wire G4 = G3[2] | (P3[2] & G3[1]);
wire P4 = P3[2] & P3[1];
wire C16, C15, C14, C13;
wire C12, C11, C10, C9;
wire C8, C7, C6, C5;
wire C4, C3, C2, C1;
wire t1, t2, t3, t4, t5;
assign #`da C1 = GS;
assign #`da C2 = G1[1];
assign #`da C3 = G[3] | (G1[1] & P[3]);
assign #`da C4 = G2[1];
assign #`da C5 = G[5] | (G2[1] & P[5]);
assign #`da C6 = G1[3] | (G2[1] & P1[3]);
assign #`da C7 = G[7] | (C6 & P[7]);
assign #`da C8 = G3[1];
assign #`da C9 = G[9] | (G3[1] & P[9]);
assign #`da C10 = G1[5] | (G3[1] & P1[5]);
assign t1 = G[11] | (G1[5] & P[11]);
assign #`da C11 = t1 | (G3[1] & P[11] & P1[5]);
assign #`da C12 = G2[3] | (G3[1] & P2[3]);
assign t2 = G[13] | (G2[3] & P[13]);
assign #`da C13 = t2 | (G3[1] & P2[3] & P[13]);
assign t3 = G1[7] | (G2[3] & P1[7]);
assign #`da C14 = t3 | (G3[1] & P2[3] & P1[7]);
assign t4 = G[15] | (G1[7] & P[15]);
assign t5 = t4 | (G2[3] & P1[7] & P[15]);
assign #`da C15 = t5 | (G3[1] & P2[3] & P1[7] & P[15]);
assign #`da C16 = G4;
assign #`db ALU[1] = (Cin & ADD) ^ AL[1];
assign #`db ALU[2] = (C1 & ADD) ^ AL[2];
assign #`db ALU[3] = (C2 & ADD) ^ AL[3];
assign #`db ALU[4] = (C3 & ADD) ^ AL[4];
assign #`db ALU[5] = (C4 & ADD) ^ AL[5];
assign #`db ALU[6] = (C5 & ADD) ^ AL[6];
assign #`db ALU[7] = (C6 & ADD) ^ AL[7];
assign #`db ALU[8] = (C7 & ADD) ^ AL[8];
assign #`db ALU[9] = (C8 & ADD) ^ AL[9];
assign #`db ALU[10] = (C9 & ADD) ^ AL[10];
assign #`db ALU[11] = (C10 & ADD) ^ AL[11];
assign #`db ALU[12] = (C11 & ADD) ^ AL[12];
assign #`db ALU[13] = (C12 & ADD) ^ AL[13];
assign #`db ALU[14] = (C13 & ADD) ^ AL[14];
assign #`db ALU[15] = (C14 & ADD) ^ AL[15];
assign #`db ALU[16] = (C15 & ADD) ^ AL[16];
assign #`db cout = C16;
/********************************/
/********************************/
wire ovf_;
assign #`da ovf_ =!((X[16] == Y[16]) && (X[16] != (C15 ^ X[16] ^ Y[16])));
endmodule
|
/*--------------------------------------------------------------*/
/*--------------------------------------------------------------*/
/*--------------------------------------------------------------*/
/*--------------------------------------------------------------*/
module EA_DEC(/* In */
DSPCLK, GO_E, GO_C, EX_en, EX_enc,
condAM_E, DIVQ_E, DIVS_E, SHADOW,
MTAX0_E, MTAX1_E, MTAY0_E, MTAY1_E, X15, Y15,
cout, ovf_, satAR, AQ, AC,Xop_D, Xop_E, Yop_E,
YY_D, CC_D, BO_D, CC_E, BO_E,
AMF_D, ALU, ALUop_E, updAR_E, updAF_E,
MTAR_E, ALUop_R, type9, T_RST, DIVQ_R, DIVS_R,
`ifdef FD_DFT
SCAN_TEST,
`endif
Rstore_AR_D, Rstore_AR_E, updateALU, updateDIV, updateAFr,
updateAFs, updateARr, updateARs, updateAX0r, updateAX0s,
updateAX1r, updateAX1s, updateAY0r, updateAY0s, updateAY1r,
updateAY1s, ABS, zeroAX, invAX, zeroAY, invAY, Cin, selAX,
selAY, selAF, selCT, K, L, ADD, ASin, AQin, ACin, AVin, ANin,
AZin, qin, CONST_E);
/*------------------------------*/
/*------------------------------*/
input DSPCLK, GO_E, GO_C;
input EX_en, EX_enc;
input [2:0] Xop_D, Xop_E;
input [1:0] Yop_E;
input [1:0] YY_D, CC_D, BO_D;
input [1:0] CC_E, BO_E;
input [4:0] AMF_D;
input condAM_E;
input DIVQ_E, DIVS_E;
input SHADOW;
input MTAX0_E, MTAX1_E;
input MTAY0_E, MTAY1_E, X15, Y15;
input [15:0] ALU;
input cout, ovf_, satAR;
input AQ, AC;
input ALUop_E, updAR_E, updAF_E;
input MTAR_E, ALUop_R;
input type9, T_RST, DIVQ_R, DIVS_R;
`ifdef FD_DFT
input SCAN_TEST;
`endif
/*------------------------------*/
/*------------------------------*/
output Rstore_AR_D, Rstore_AR_E;
output [15:0] CONST_E;
output updateALU, updateDIV;
output updateAFr, updateAFs;
output updateARr, updateARs;
output updateAX0r, updateAX0s;
output updateAX1r, updateAX1s;
output updateAY0r, updateAY0s;
output updateAY1r, updateAY1s;
output ABS, zeroAX, invAX;
output zeroAY, invAY, Cin;
output selAX, selAY, selAF;
output selCT, K, L, ADD;
output ASin, AQin, ACin;
output AVin, ANin, AZin, qin;
/*----------------------------------------------*/
/*----------------------------------------------*/
reg [4:0] AMF_E;
always @(posedge DSPCLK or posedge T_RST)
begin
if (T_RST) AMF_E[4:0] <= #1 5'b0;
else if (GO_E && (ALUop_R || DIVQ_R || DIVS_R))
AMF_E[4:0] <= #1 AMF_D[4:0];
end
/*----------------------------------------------*/
/*----------------------------------------------*/
wire Rstore_AR_D;
wire Rstore_AR_E;
assign Rstore_AR_D = (Xop_D[2:0] == 3'b010);
assign Rstore_AR_E = (Xop_E[2:0] == 3'b010);
/*----------------------------------------------*/
/*----------------------------------------------*/
wire [1:0] YY_D, CC_D, BO_D;
reg [15:0] CONST_D;
always @(YY_D or CC_D or BO_D)
begin
case ({YY_D, CC_D, BO_D})
6'b00_00_01 : CONST_D[15:0] = 16'h0001;
6'b00_01_01 : CONST_D[15:0] = 16'h0002;
6'b00_10_01 : CONST_D[15:0] = 16'h0004;
6'b00_11_01 : CONST_D[15:0] = 16'h0008;
6'b01_00_01 : CONST_D[15:0] = 16'h0010;
6'b01_01_01 : CONST_D[15:0] = 16'h0020;
6'b01_10_01 : CONST_D[15:0] = 16'h0040;
6'b01_11_01 : CONST_D[15:0] = 16'h0080;
6'b10_00_01 : CONST_D[15:0] = 16'h0100;
6'b10_01_01 : CONST_D[15:0] = 16'h0200;
6'b10_10_01 : CONST_D[15:0] = 16'h0400;
6'b10_11_01 : CONST_D[15:0] = 16'h0800;
6'b11_00_01 : CONST_D[15:0] = 16'h1000;
6'b11_01_01 : CONST_D[15:0] = 16'h2000;
6'b11_10_01 : CONST_D[15:0] = 16'h4000;
6'b11_11_01 : CONST_D[15:0] = 16'h8000;
6'b00_00_11 : CONST_D[15:0] = 16'hfffe;
6'b00_01_11 : CONST_D[15:0] = 16'hfffd;
6'b00_10_11 : CONST_D[15:0] = 16'hfffb;
6'b00_11_11 : CONST_D[15:0] = 16'hfff7;
6'b01_00_11 : CONST_D[15:0] = 16'hffef;
6'b01_01_11 : CONST_D[15:0] = 16'hffdf;
6'b01_10_11 : CONST_D[15:0] = 16'hffbf;
6'b01_11_11 : CONST_D[15:0] = 16'hff7f;
6'b10_00_11 : CONST_D[15:0] = 16'hfeff;
6'b10_01_11 : CONST_D[15:0] = 16'hfdff;
6'b10_10_11 : CONST_D[15:0] = 16'hfbff;
6'b10_11_11 : CONST_D[15:0] = 16'hf7ff;
6'b11_00_11 : CONST_D[15:0] = 16'hefff;
6'b11_01_11 : CONST_D[15:0] = 16'hdfff;
6'b11_10_11 : CONST_D[15:0] = 16'hbfff;
6'b11_11_11 : CONST_D[15:0] = 16'h7fff;
default : CONST_D[15:0] = 16'h0000;
endcase
end
wire CLKCTenb;
assign CLKCTenb = !(AMF_D[4] && type9 && ({CC_D[1:0], BO_D[1:0]} !=4'b0000));
`ifdef FD_DFT
REG16L piconst(DSPCLK, CLKCTenb, GO_E, CONST_D[15:0], CONST_E[15:0], SCAN_TEST);
`else
REG16L piconst(DSPCLK, CLKCTenb, GO_E, CONST_D[15:0], CONST_E[15:0]);
`endif
/*----------------------------------------------*/
/*----------------------------------------------*/
wire updateALU, updateDIV;
assign updateAX0r = !SHADOW && MTAX0_E && EX_en;
assign updateAX0s = SHADOW && MTAX0_E && EX_en;
assign updateAX1r = !SHADOW && MTAX1_E && EX_en;
assign updateAX1s = SHADOW && MTAX1_E && EX_en;
assign updateAY0r = !SHADOW && (MTAY0_E || DIVQ_E || DIVS_E) && EX_en;
assign updateAY0s = SHADOW && (MTAY0_E || DIVQ_E || DIVS_E) && EX_en;
assign updateAY1r = !SHADOW && MTAY1_E && EX_en;
assign updateAY1s = SHADOW && MTAY1_E && EX_en;
assign updateAFr = !SHADOW && (DIVQ_E || DIVS_E || updAF_E);
assign updateAFs = SHADOW && (DIVQ_E || DIVS_E || updAF_E);
assign updateARr = !SHADOW && (MTAR_E || updAR_E);
assign updateARs = SHADOW && (MTAR_E || updAR_E);
assign updateALU = ALUop_E && EX_enc;
assign updateDIV = (DIVQ_E || DIVS_E) & EX_en;
/*----------------------------------------------*/
/*----------------------------------------------*/
assign ABS = (AMF_E[4:0] == 5'b11111);
assign zeroAX = (AMF_E[3:0] == 4'h0)
| (AMF_E[3:0] == 4'h1)
| (AMF_E[3:0] == 4'h4)
| (AMF_E[3:0] == 4'h5)
| (!DIVQ_E && (AMF_E[3:0] == 4'h8))
| (!(ALUop_E || DIVQ_E || DIVS_E));
`ifdef FD_RTL_SIM
assign invAX = (DIVQ_E & (!AQ))
| (AMF_E[3:0] == 4'hb)
| (!DIVQ_E & (AMF_E[3:0] == 4'h8))
| (AMF_E[3:0] == 4'h9)
| (AMF_E[3:0] == 4'ha)
| ((AMF_E[3:0] == 4'hf) && X15)
| (!(ALUop_E || DIVQ_E || DIVS_E));
`else
wire invAX1, invAX0;
assign invAX1 = (DIVQ_E & (!AQ))
| (AMF_E[3:0] == 4'hb)
| (!DIVQ_E & (AMF_E[3:0] == 4'h8))
| (AMF_E[3:0] == 4'h9)
| (AMF_E[3:0] == 4'ha)
| (AMF_E[3:0] == 4'hf)
| (!(ALUop_E || DIVQ_E || DIVS_E));
assign invAX0 = (DIVQ_E & (!AQ))
| (AMF_E[3:0] == 4'hb)
| (!DIVQ_E & (AMF_E[3:0] == 4'h8))
| (AMF_E[3:0] == 4'h9)
| (AMF_E[3:0] == 4'ha)
| (!(ALUop_E || DIVQ_E || DIVS_E));
GTECH_MUX2 invx_sel(.A(invAX0), .B(invAX1), .S(X15), .Z(invAX));
`endif
assign zeroAY = (AMF_E[3:0] == 4'hb)
| (AMF_E[3:0] == 4'hf)
| (!(ALUop_E || DIVQ_E || DIVS_E));
assign invAY = (AMF_E[3:0] == 4'h5)
| (AMF_E[3:0] == 4'h6)
| (AMF_E[3:0] == 4'h7)
| (AMF_E[3:0] == 4'h4)
| (!(ALUop_E || DIVQ_E || DIVS_E));
`ifdef FD_RTL_SIM
assign Cin = (DIVQ_E && (!AQ))
| (AMF_E[3:0] == 4'h1)
| ((AMF_E[3:0] == 4'h2) && AC)
| (AMF_E[3:0] == 4'h5)
| ((AMF_E[3:0] == 4'h6) && AC)
| (AMF_E[3:0] == 4'h7)
| (AMF_E[3:0] == 4'h9)
| ((AMF_E[3:0] == 4'ha) && AC)
| ((AMF_E[3:0] == 4'hf) && X15)
| (!(ALUop_E || DIVQ_E || DIVS_E));
`else
wire Cin1, Cin0;
assign Cin1 = (DIVQ_E && (!AQ))
| (AMF_E[3:0] == 4'h1)
| ((AMF_E[3:0] == 4'h2) && AC)
| (AMF_E[3:0] == 4'h5)
| ((AMF_E[3:0] == 4'h6) && AC)
| (AMF_E[3:0] == 4'h7)
| (AMF_E[3:0] == 4'h9)
| ((AMF_E[3:0] == 4'ha) && AC)
| (AMF_E[3:0] == 4'hf)
| (!(ALUop_E || DIVQ_E || DIVS_E));
assign Cin0 = (DIVQ_E && (!AQ))
| (AMF_E[3:0] == 4'h1)
| ((AMF_E[3:0] == 4'h2) && AC)
| (AMF_E[3:0] == 4'h5)
| ((AMF_E[3:0] == 4'h6) && AC)
| (AMF_E[3:0] == 4'h7)
| (AMF_E[3:0] == 4'h9)
| ((AMF_E[3:0] == 4'ha) && AC)
| (!(ALUop_E || DIVS_E || DIVQ_E));
GTECH_MUX2 cin_sel(.A(Cin0), .B(Cin1), .S(X15), .Z(Cin));
`endif
assign selAX = (Xop_E[2:1] == 2'b00);
assign selAY = (~Yop_E[1]);
assign selAF = (Yop_E[1:0] == 2'b10);
assign selCT = (~({CC_E[1:0], BO_E[1:0]} == 4'b0000)) & condAM_E;
/*------------------------------------------------------*/
/*------------------------------------------------------*/
reg K, L, ADD;
wire [3:0] AMF_E_temp = AMF_E[3:0];
always @(AMF_E_temp) begin
case ( AMF_E_temp )
4'b1100 : {K, L, ADD} = 3'b000;
4'b1101 : {K, L, ADD} = 3'b010;
4'b1110 : {K, L, ADD} = 3'b110;
default : {K, L, ADD} = 3'b111;
endcase
end
assign ASin = X15;
/*------------------------------------------------------*/
/*------------------------------------------------------*/
assign AQin = DIVS_E ? (X15 ^ Y15) : (X15 ^ ALU[15]);
/*------------------------------------------------------*/
/*------------------------------------------------------*/
assign ACin = ADD && cout;
assign AVin = ADD && (!ovf_);
/*------------------------------------------------------*/
/*------------------------------------------------------*/
assign ANin = (ALU[15] ^ (satAR && AVin));
assign AZin = (ALU[15:0] == 16'h0000);
assign qin = DIVS_E ? AQin : ~AQin;
endmodule
|
/*----------------------------------------------*/
/*----------------------------------------------*/
/*----------------------------------------------*/
/*----------------------------------------------*/
`define del 1
`include "../include/x_def.v"
module EA_REG (/* IN */
DSPCLK, SHADOW, Xop0_E, zeroAX, zeroAY,
selAX, DOUBLE_E, updateDIV, Yop0_E, ACin, AVin, satAR,
selAY, updateAX0r, updateAX0s, updateAX1r,
updateAX1s, updateAY0r, updateAY0s, updateAY1r,
updateAY1s, updateAFr, updateAFs, MTAR_E,
updateARr, updateARs, MFAX0_E, MFAX1_E, R_in_E,
MFAY0_E, MFAY1_E, MFAR_E, MFASTAT_E, ALU, selAF,
invAX, invAY, Rstore_AR_D, Rstore_AR_E, qin,
ASTAT, selCT, CONST_E, BYPASSR_D, MFALU_E,
pMFALU_E, accPM_E, GO_MAC, EX_enc, GO_C,
`ifdef FD_DFT
SCAN_TEST,
`endif
X, Y, X15, Y15, R_alu_E, R_alu_D,
DMDin, DMDalu, PMDin, PMDalu);
/********************************/
/********************************/
input DSPCLK, SHADOW, Xop0_E, zeroAX, zeroAY, selAX;
input DOUBLE_E, updateDIV, ACin, AVin, satAR, selAY, Yop0_E;
input updateAX0r, updateAX0s, updateAX1r, updateAX1s;
input updateAY0r, updateAY0s, updateAY1r, updateAY1s;
input updateAFr, updateAFs, MTAR_E, updateARr;
input updateARs, MFAX0_E, MFAX1_E;
input MFASTAT_E, MFAY0_E, MFAY1_E;
input MFAR_E, invAX, invAY, selAF;
input [15:0] ALU;
input [7:0] ASTAT;
input Rstore_AR_D;
input Rstore_AR_E;
input qin;
input [15:0] R_in_E;
input selCT, BYPASSR_D;
input [15:0] CONST_E;
input MFALU_E, pMFALU_E, accPM_E;
input GO_MAC, EX_enc, GO_C;
`ifdef FD_DFT
input SCAN_TEST;
`endif
/********************************/
/********************************/
output [15:0] X, Y, R_alu_E, R_alu_D;
output X15, Y15;
/********************************/
/********************************/
input [15:0] DMDin;
output [15:0] DMDalu;
input [15:0] PMDin;
output [15:0] PMDalu;
wire [15:0] DMDin1;
DMDbuf DMDIN_BUF(DMDin[15:0], DMDin1[15:0]);
wire [15:0] Xin;
assign Xin[15:0] = accPM_E ? PMDin[15:0] : DMDin1[15:0];
wire [15:0] AX0r, AX0s, AX1r, AX1s;
wire CLKAX0renb, CLKAX1renb, CLKAX0senb, CLKAX1senb;
assign CLKAX0renb = !updateAX0r;
assign CLKAX0senb = !updateAX0s;
assign CLKAX1renb = !updateAX1r;
assign CLKAX1senb = !updateAX1s;
`ifdef FD_DFT
REG16L ax0rwe(DSPCLK, CLKAX0renb, GO_C, Xin[15:0], AX0r[15:0], SCAN_TEST);
REG16L ax0swe(DSPCLK, CLKAX0senb, GO_C, Xin[15:0], AX0s[15:0], SCAN_TEST);
REG16L ax1rwe(DSPCLK, CLKAX1renb, GO_C, Xin[15:0], AX1r[15:0], SCAN_TEST);
REG16L ax1swe(DSPCLK, CLKAX1senb, GO_C, Xin[15:0], AX1s[15:0], SCAN_TEST);
`else
REG16L ax0rwe(DSPCLK, CLKAX0renb, GO_C, Xin[15:0], AX0r[15:0]);
REG16L ax0swe(DSPCLK, CLKAX0senb, GO_C, Xin[15:0], AX0s[15:0]);
REG16L ax1rwe(DSPCLK, CLKAX1renb, GO_C, Xin[15:0], AX1r[15:0]);
REG16L ax1swe(DSPCLK, CLKAX1senb, GO_C, Xin[15:0], AX1s[15:0]);
`endif
wire [15:0] AX0, AX1, AX;
assign AX0[15:0] = SHADOW ? AX0s[15:0] : AX0r[15:0];
assign AX1[15:0] = SHADOW ? AX1s[15:0] : AX1r[15:0];
assign AX[15:0] = Xop0_E ? AX1[15:0] : AX0[15:0];
wire [15:0] X, A, A_t;
assign A[15:0] = selAX ? AX[15:0] : R_in_E[15:0];
assign A_t[15:0] = zeroAX ? 16'b0 : A[15:0];
assign X15 = A[15];
assign X[15:0] = invAX ? ~A_t[15:0] : A_t[15:0];
wire [15:0] AY0, AY0in, AYin;
assign AYin[15:0] = (DOUBLE_E | accPM_E) ? PMDin[15:0] : DMDin1[15:0];
assign AY0in[15:0] = updateDIV ? {AY0[14:0], qin} : AYin[15:0];
/*-----------------------------------------------*/
wire [15:0] AY0r, AY1r, AY0s, AY1s;
wire CLKAY0renb, CLKAY1renb, CLKAY0senb, CLKAY1senb;
assign CLKAY0renb = !updateAY0r;
assign CLKAY1renb = !updateAY1r;
assign CLKAY0senb = !updateAY0s;
assign CLKAY1senb = !updateAY1s;
`ifdef FD_DFT
REG16L ay0rwe(DSPCLK, CLKAY0renb, GO_C, AY0in[15:0], AY0r[15:0], SCAN_TEST);
REG16L ay0swe(DSPCLK, CLKAY0senb, GO_C, AY0in[15:0], AY0s[15:0], SCAN_TEST);
REG16L ay1rwe(DSPCLK, CLKAY1renb, GO_C, AYin[15:0], AY1r[15:0], SCAN_TEST);
REG16L ay1swe(DSPCLK, CLKAY1senb, GO_C, AYin[15:0], AY1s[15:0], SCAN_TEST);
`else
REG16L ay0rwe(DSPCLK, CLKAY0renb, GO_C, AY0in[15:0], AY0r[15:0]);
REG16L ay0swe(DSPCLK, CLKAY0senb, GO_C, AY0in[15:0], AY0s[15:0]);
REG16L ay1rwe(DSPCLK, CLKAY1renb, GO_C, AYin[15:0], AY1r[15:0]);
REG16L ay1swe(DSPCLK, CLKAY1senb, GO_C, AYin[15:0], AY1s[15:0]);
`endif
/*------------------------------------------------*/
wire [15:0] AY, AY1;
assign AY0[15:0] = SHADOW ? AY0s[15:0] : AY0r[15:0];
assign AY1[15:0] = SHADOW ? AY1s[15:0] : AY1r[15:0];
assign AY[15:0] = Yop0_E ? AY1[15:0] : AY0[15:0];
wire [15:0] AFin;
assign AFin[15:0] = updateDIV ? ({ALU[14:0], AY0[15]}) : ALU[15:0];
wire [15:0] AFr, AFs;
wire CLKAFrenb, CLKAFsenb;
wire AFrwe, AFswe;
assign CLKAFrenb = !updateAFr;
assign CLKAFsenb = !updateAFs;
assign AFrwe = GO_C && EX_enc;
assign AFswe = GO_C && EX_enc;
`ifdef FD_DFT
REG16L afrwe(DSPCLK, CLKAFrenb, AFrwe, AFin[15:0], AFr[15:0], SCAN_TEST);
REG16L afswe(DSPCLK, CLKAFsenb, AFswe, AFin[15:0], AFs[15:0], SCAN_TEST);
`else
REG16L afrwe(DSPCLK, CLKAFrenb, AFrwe, AFin[15:0], AFr[15:0]);
REG16L afswe(DSPCLK, CLKAFsenb, AFswe, AFin[15:0], AFs[15:0]);
`endif
/*----------------------------------------------*/
wire [15:0] AF;
assign AF[15:0] = SHADOW ? AFs[15:0] : AFr[15:0];
wire [15:0] Y, B, B_t;
assign #`db B[15:0] = selCT ? CONST_E[15:0] :
selAY ? AY[15:0] :
selAF ? AF[15:0] : 0 ;
assign #`db B_t[15:0] = zeroAY ? 16'b0 : B[15:0];
assign Y15 = B[15];
assign #`db Y[15:0] = invAY ? ~B_t[15:0] : B_t[15:0];
wire [15:0] ARin, SATin;
assign SATin[15:0] = ACin ? 16'h8000 : 16'h7fff;
assign ARin[15:0] = MTAR_E ? Xin[15:0] :
(AVin && satAR) ? SATin[15:0] : ALU[15:0];
wire [15:0] ARr, ARs;
wire CLKARrenb, CLKARsenb;
wire ARrwe, ARswe;
assign CLKARrenb = !updateARr;
assign CLKARsenb = !updateARs;
assign ARrwe = GO_C && EX_enc;
assign ARswe = GO_C && EX_enc;
`ifdef FD_DFT
REG16L arrwe(DSPCLK, CLKARrenb, ARrwe, ARin[15:0], ARr[15:0], SCAN_TEST);
REG16L arswe(DSPCLK, CLKARsenb, ARswe, ARin[15:0], ARs[15:0], SCAN_TEST);
`else
REG16L arrwe(DSPCLK, CLKARrenb, ARrwe, ARin[15:0], ARr[15:0]);
REG16L arswe(DSPCLK, CLKARsenb, ARswe, ARin[15:0], ARs[15:0]);
`endif
/*------------------------------------------------*/
wire [15:0] AR;
assign AR[15:0] = SHADOW ? ARs[15:0] : ARr[15:0];
/**********************************/
/**********************************/
wire [15:0] ALUout;
assign #`da ALUout[15:0] = ({16{MFAX0_E}} & AX0[15:0]) |
({16{MFAX1_E}} & AX1[15:0]) |
({16{MFAY0_E}} & AY0[15:0]) |
({16{MFAY1_E}} & AY1[15:0]) |
({16{MFAR_E}} & AR[15:0]) |
({16{MFASTAT_E}} & {8'b0, ASTAT[7:0]});
assign DMDalu[15:0] = {16{MFALU_E}} & ALUout[15:0];
assign PMDalu[15:0] = {16{pMFALU_E}} & ALUout[15:0];
/**********************************/
/**********************************/
wire [15:0] R_alu_in_D;
assign #`da R_alu_in_D[15:0] = {16{Rstore_AR_D & BYPASSR_D & ~GO_MAC & ~MTAR_E & AVin & satAR}} & SATin[15:0]
| {16{(Rstore_AR_D & ~BYPASSR_D & ~GO_MAC) | (Rstore_AR_E & GO_MAC)}} & AR[15:0];
assign #`da R_alu_D[15:0] = {16{Rstore_AR_D & BYPASSR_D & ~GO_MAC & MTAR_E & accPM_E}} & PMDin[15:0]
| {16{Rstore_AR_D & BYPASSR_D & ~GO_MAC & MTAR_E & ~accPM_E}} & DMDin[15:0]
| {16{Rstore_AR_D & BYPASSR_D & ~GO_MAC & ~MTAR_E & ~(AVin & satAR)}} & ALU[15:0]
| R_alu_in_D[15:0];
assign R_alu_E[15:0] = {16{Rstore_AR_E}} & AR[15:0];
endmodule
|
/*--------------------------------------------------------------*/
/*--------------------------------------------------------------*/
/*--------------------------------------------------------------*/
/*--------------------------------------------------------------*/
module EU(/*--------------- Inputs ---------------*/
DSPCLK, T_RST, GO_E, GO_C, EX_en, EX_enc,
condAM_E, DIVQ_E, DIVS_E, DOUBLE_E,
MTAR_E, MTAX0_E, MTAX1_E, MTAY0_E, MTAY1_E, BYPASSR_D,
MFAR_E, MFAX0_E, MFAX1_E, MFAY0_E, MFAY1_E, MFASTAT_E,
MTMX0_Eg, MTMX1_Eg, MTMY0_Eg, MTMY1_Eg, MTMR0_Eg,
MTMR1_Eg, MTMR2_Eg, MFMX0_E, MFMX1_E, MFMY0_E, MFMY1_E,
MFMR0_E, MFMR1_E, MFMR2_E, BYPASSMY_D, MTASTAT_E,
MTSI_E, MTSB_E, MTSE_E,
MTSR0_E, MTSR1_E, MFSI_E, MFSB_E, MFSE_E, MFSR1_E,
MFSR0_E, SIMM_E, BYPASSMX_D, MFALU_E, MFMAC_E, MFSHT_E,
pMFALU_E, pMFMAC_E, pMFSHT_E, accPM_E, Sq_R, GO_MAC,
updSR0_Eg, updSR1_Eg, SHTop_E, satMR_Eg, MACop_E, updMF_E,
updMR_E, ALUop_E, updAR_E, updAF_E, ALUop_R, type9,
updSR_E, MACop_R, DIVQ_R, DIVS_R,
IR, IRE,
TERM_R,
SHADOW, satAR, FracMode, CE, MSTAT2,
pop_ASTAT_E, pop_ASTAT_DATA_E,
RSTtext_h,
BIASRND,
`ifdef FD_DFT
SCAN_TEST,
`endif
ASTAT, CONDok_C, TERMok_C,
DMDin, DMD, PMDin, PMD);
input [17:0] IR;
input [14:0] IRE;
input DSPCLK;
input T_RST;
input GO_E;
input GO_C;
input EX_en;
input EX_enc;
input MTAX0_E;
input MTAX1_E;
input MTAY0_E;
input MTAY1_E;
input MTMX0_Eg;
input MTMX1_Eg;
input MTMY0_Eg;
input MTMY1_Eg;
input MTAR_E;
input MTMR0_Eg;
input MTMR1_Eg;
input MTMR2_Eg;
input MTSI_E;
input MTSE_E;
input MTSR0_E;
input MTSR1_E;
input MTSB_E;
input MTASTAT_E;
input MFAX0_E;
input MFAX1_E;
input MFAY0_E;
input MFAY1_E;
input MFAR_E;
input MFMX0_E;
input MFMX1_E;
input MFMY0_E;
input MFMY1_E;
input MFMR0_E;
input MFMR1_E;
input MFMR2_E;
input MFSI_E;
input MFSE_E;
input MFSR1_E;
input MFSR0_E;
input MFSB_E;
input MFASTAT_E;
input condAM_E;
input DIVQ_R;
input DIVS_R;
input DIVQ_E;
input DIVS_E;
input DOUBLE_E;
input SIMM_E;
input BYPASSR_D;
input BYPASSMX_D;
input BYPASSMY_D;
input CE;
input SHADOW;
input MSTAT2;
input satAR;
input FracMode;
input pop_ASTAT_E;
input RSTtext_h;
input updSR0_Eg;
input updSR1_Eg;
input SHTop_E;
input satMR_Eg;
input MACop_E;
input updMF_E;
input updMR_E;
input ALUop_E;
input updAR_E;
input updAF_E;
input ALUop_R;
input MACop_R;
input type9;
input updSR_E;
input MFALU_E;
input MFSHT_E;
input MFMAC_E;
input pMFALU_E;
input pMFMAC_E;
input pMFSHT_E;
input accPM_E;
input Sq_R;
input GO_MAC;
input [7:0] pop_ASTAT_DATA_E;
input [3:0] TERM_R;
input BIASRND;
`ifdef FD_DFT
input SCAN_TEST;
`endif
output [7:0] ASTAT;
output CONDok_C;
output TERMok_C;
input [15:0] DMDin;
output [15:0] DMD;
input [15:0] PMDin;
output [15:0] PMD;
wire [2:0] Xop_D = IR[10:8];
wire [1:0] Yop_D = IR[12:11];
wire [1:0] CC_D = IR[7:6];
wire [1:0] BO_D = IR[5:4];
wire [2:0] Xop_E = IRE[10:8];
wire [1:0] Yop_E = IRE[12:11];
wire [4:0] AMF_D = IR[17:13];
wire [3:2] SF_E = IRE[14:13];
wire [3:0] COND_R = IR[3:0];
/*------------------------------------------*/
wire [15:0] R_alu_E, R_alu_D, R_sht_E, R_sht_D;
wire [15:0] R_mac_E, R_mac_D, R_in_E, R_in_D;
wire [15:0] DMDalu, DMDsht, DMDmac;
wire [15:0] PMDalu, PMDsht, PMDmac;
wire updateDIV, updateALU, updateSS, updateMV;
wire ABS, ASin, AQin, ACin, MVin;
wire AVin, ANin, AZin, SSin;
assign R_in_D[15:0] = R_alu_D | R_sht_D | R_mac_D;
assign R_in_E[15:0] = R_alu_E | R_sht_E | R_mac_E;
assign DMD[15:0] = DMDalu[15:0] | DMDsht[15:0] | DMDmac[15:0];
assign PMD[15:0] = PMDalu[15:0] | PMDsht[15:0] | PMDmac[15:0];
EA_ALU ea_alu(/*------------------ Inputs -------------------*/
DSPCLK, GO_E, GO_C, EX_en, EX_enc,
R_in_E[15:0],
condAM_E, DIVQ_E, DIVS_E, DOUBLE_E,
MTAR_E, MTAX0_E, MTAX1_E, MTAY0_E, MTAY1_E, BYPASSR_D,
MFAR_E, MFAX0_E, MFAX1_E, MFAY0_E, MFAY1_E, MFASTAT_E,
MFALU_E, pMFALU_E, accPM_E, GO_MAC, ALUop_E, updAR_E,
updAF_E, ALUop_R, type9, T_RST, DIVQ_R, DIVS_R,
Xop_D[2:0], Yop_D[1:0], CC_D[1:0], BO_D[1:0],
Xop_E[2:0], Yop_E[1:0], IRE[7:6], IRE[5:4],
AMF_D[4:0],
SHADOW, satAR,
ASTAT[7:0],
`ifdef FD_DFT
SCAN_TEST,
`endif
R_alu_E[15:0], R_alu_D[15:0],
updateALU, updateDIV, ABS, ASin, AQin, ACin,
AVin, ANin, AZin,
DMDin[15:0], DMDalu[15:0], PMDin[15:0], PMDalu[15:0]);
ES_SHT es_sht(/*---------------- Inputs ---------------*/
DSPCLK, GO_C, EX_en, EX_enc, R_in_E[15:0],
{SF_E[3:2], Yop_E[1:0]}, IRE[7:0], Xop_D[2:0], Xop_E[2:0],
SHADOW,
MTSI_E, MTSB_E, MTSE_E,
MTSR0_E, MTSR1_E, MFSI_E, MFSB_E, MFSE_E,
MFSR1_E, MFSR0_E, SIMM_E, BYPASSR_D, MFSHT_E,
pMFSHT_E, accPM_E, GO_MAC, updSR0_Eg, updSR1_Eg,
SHTop_E, updSR_E,
ASTAT[3], ASTAT[2], ASTAT[7],
`ifdef FD_DFT
SCAN_TEST,
`endif
R_sht_E[15:0], R_sht_D[15:0],
SSin, updateSS,
DMDin[15:0], DMDsht[15:0], PMDin[15:0], PMDsht[15:0]);
EM_MAC em_mac(/*---------------------- Input ----------------------*/
DSPCLK, GO_E, GO_C, EX_enc,
R_in_D[15:0],
satMR_Eg, MACop_E, updMF_E, updMR_E, DOUBLE_E,
MTMX0_Eg, MTMX1_Eg, MTMY0_Eg, MTMY1_Eg,
MTMR0_Eg, MTMR1_Eg, MTMR2_Eg, MFMX0_E,
MFMX1_E, MFMY0_E, MFMY1_E, MFMR0_E,
MFMR1_E, MFMR2_E, BYPASSMX_D, BYPASSMY_D, BYPASSR_D,
pMFMAC_E, MFMAC_E, accPM_E, Sq_R, GO_MAC, MACop_R,
Xop_D[2:0], Xop_E[2:0], Yop_D[1:0], Yop_E[1:0],
AMF_D[3:0],
SHADOW, ~FracMode,
BIASRND,
`ifdef FD_DFT
SCAN_TEST,
`endif
R_mac_E[15:0], R_mac_D[15:0],
updateMV, MVin,
DMDin[15:0], DMDmac[15:0], PMDin[15:0], PMDmac[15:0]);
EC_CUN ec_cun(/*--------------------- Input ---------------------*/
DSPCLK, GO_E, GO_C, EX_en, T_RST, DMDin[7:0],
`ifdef FD_DFT
SCAN_TEST,
`endif
updateALU, updateDIV, ABS, AZin,
ANin, AVin, ACin, ASin, AQin,
MTASTAT_E,
updateSS, SSin,
updateMV, MVin,
COND_R[3:0], TERM_R[3:0],
pop_ASTAT_E, pop_ASTAT_DATA_E[7:0], CE, MSTAT2,
RSTtext_h,
CONDok_C, TERMok_C,
ASTAT[7:0]);
endmodule
|
`include "../include/x_def.v"
module EC_CUN(/*--------------------- Input ---------------------*/
DSPCLK, GO_E, GO_C, EX_en, T_RST, DMDin,
`ifdef FD_DFT
SCAN_TEST,
`endif
updateALU, updateDIV, ABS, AZin,
ANin, AVin, ACin, ASin, AQin,
MTASTAT_E,
updateSS, SSin,
updateMV, MVin,
COND_R, TERM_R,
pop_ASTAT, pop_DATA, CE, MSTAT2,
RSTtext_h,
CONDok_C, TERMok_C,
ASTAT);
input DSPCLK, GO_E, GO_C, EX_en, T_RST;
input [7:0] DMDin;
input updateALU, updateDIV, ABS, AZin;
input ANin, AVin, ACin, ASin, AQin;
input MTASTAT_E, updateSS, SSin;
input updateMV, MVin;
input [3:0] COND_R, TERM_R;
input pop_ASTAT, CE;
input MSTAT2;
input [7:0] pop_DATA;
input RSTtext_h;
`ifdef FD_DFT
input SCAN_TEST;
`endif
output CONDok_C;
output TERMok_C;
output [7:0] ASTAT;
`ifdef FD_DFT
wire T_RSTi_h = T_RST | RSTtext_h;
wire T_RSTi = SCAN_TEST ? T_RST : T_RSTi_h;
`else
wire T_RSTi = T_RST | RSTtext_h;
`endif
reg [3:0] COND_E, TERM_E;
always @(posedge DSPCLK) begin
if (T_RSTi) begin
COND_E[3:0] <= #`da 4'b0;
TERM_E[3:0] <= #`da 4'b0;
end
else
if (GO_E) begin
COND_E[3:0] <= #`da COND_R[3:0];
TERM_E[3:0] <= #`da TERM_R[3:0];
end
end
wire update_AZ, update_AN, update_AV;
wire update_AC, update_AS, update_AQ;
wire update_MV, update_SS;
wire AZi, ANi, AVi, ACi, ASi, AQi, MVi, SSi;
reg AZ, AN, AV, AC, AS, AQ, MV, SS;
assign update_AZ = (updateALU | (MTASTAT_E & EX_en) | pop_ASTAT) & GO_C;
assign update_AN = (updateALU | (MTASTAT_E & EX_en) | pop_ASTAT) & GO_C;
assign update_AV = (updateALU | (MTASTAT_E & EX_en) | pop_ASTAT) & GO_C;
assign update_AC = (updateALU | (MTASTAT_E & EX_en) | pop_ASTAT) & GO_C;
assign update_AS = ((ABS & updateALU) | (MTASTAT_E & EX_en) | pop_ASTAT) & GO_C;
assign update_AQ = (updateDIV | (MTASTAT_E & EX_en) | pop_ASTAT) & GO_C;
assign update_MV = (updateMV | (MTASTAT_E & EX_en) | pop_ASTAT) & GO_C;
assign update_SS = (updateSS | (MTASTAT_E & EX_en) | pop_ASTAT) & GO_C;
assign AZi = (updateALU & AZin) | (MTASTAT_E & DMDin[0]) | (pop_ASTAT & pop_DATA[0]);
assign ANi = (updateALU & ANin) | (MTASTAT_E & DMDin[1]) | (pop_ASTAT & pop_DATA[1]);
assign AVi = (updateALU & (AVin | AV & MSTAT2)) | (MTASTAT_E & DMDin[2]) | (pop_ASTAT & pop_DATA[2]);
assign ACi = (updateALU & ACin) | (MTASTAT_E & DMDin[3]) | (pop_ASTAT & pop_DATA[3]);
assign ASi = (updateALU & ABS & ASin) | (MTASTAT_E & DMDin[4]) | (pop_ASTAT & pop_DATA[4]);
assign AQi = (updateDIV & AQin) | (MTASTAT_E & DMDin[5]) | (pop_ASTAT & pop_DATA[5]);
assign MVi = (updateMV & MVin) | (MTASTAT_E & DMDin[6]) | (pop_ASTAT & pop_DATA[6]);
assign SSi = (updateSS & SSin) | (MTASTAT_E & DMDin[7]) | (pop_ASTAT & pop_DATA[7]);
always @(posedge DSPCLK) begin
if (T_RSTi) AZ <= #`da 1'b0;
else
if (update_AZ) AZ <= #`da AZi;
end
always @(posedge DSPCLK) begin
if (T_RSTi) AN <= #`da 1'b0;
else
if (update_AN) AN <= #`da ANi;
end
always @(posedge DSPCLK) begin
if (T_RSTi) AV <= #`da 1'b0;
else
if (update_AV) AV <= #`da AVi;
end
always @(posedge DSPCLK) begin
if (T_RSTi) AC <= #`da 1'b0;
else
if (update_AC) AC <= #`da ACi;
end
always @(posedge DSPCLK) begin
if (T_RSTi) AS <= #`da 1'b0;
else
if (update_AS) AS <= #`da ASi;
end
always @(posedge DSPCLK) begin
if (T_RSTi) AQ <= #`da 1'b0;
else
if (update_AQ) AQ <= #`da AQi;
end
always @(posedge DSPCLK) begin
if (T_RSTi) SS <= #`da 1'b0;
else
if (update_SS) SS <= #`da SSi;
end
reg updateMV_C;
reg MVi_pre_C;
wire MVi_C;
wire update_MV_C;
always @(posedge DSPCLK)
if (GO_C) updateMV_C <= #`da updateMV ;
always @(posedge DSPCLK)
if (GO_C) MVi_pre_C <= #`da (MTASTAT_E & DMDin[6]) | (pop_ASTAT & pop_DATA[6]);
assign MVi_C = MVi_pre_C | updateMV_C & MVin;
HALFP mven(T_RST,
DSPCLK,
update_MV,
`ifdef FD_DFT
SCAN_TEST,
`endif
update_MV_C);
always @(update_MV_C or T_RSTi or MVi_C) begin
if(T_RSTi) MV <= #`da 1'b0;
else
if (update_MV_C) MV <= #`da MVi_C;
end
assign ASTAT[7:0] = {SS, MV, AQ, AS, AC, AV, AN, AZ};
wire pre_condOK_E1;
wire pre_condOK_E2;
wire pre_condOK_E3;
wire pre_condOK_E;
wire condOK_E1;
wire condOK_E2;
wire condOK_E;
assign #`da pre_condOK_E1 = (COND_R[3:0] == 4'h4) & (ANi != AVi)
| (COND_R[3:0] == 4'h5) & !(ANi != AVi)
| (COND_R[3:0] == 4'h6) & AVi
| (COND_R[3:0] == 4'h7) & !AVi
| (COND_R[3:0] == 4'h8) & ACi
| (COND_R[3:0] == 4'h9) & !ACi;
assign #`da pre_condOK_E2 = (COND_R[3:0] == 4'ha) & ASi
| (COND_R[3:0] == 4'hb) & !ASi;
assign #`da pre_condOK_E3 = (COND_R[3:0] == 4'hf);
assign #`da pre_condOK_E = (pre_condOK_E1 & update_AZ)
| (pre_condOK_E2 & update_AS)
| pre_condOK_E3
| condOK_E;
assign #`da condOK_E1 = (COND_R[3:0] == 4'h4) & (AN != AV)
| (COND_R[3:0] == 4'h5) & !(AN != AV)
| (COND_R[3:0] == 4'h6) & AV
| (COND_R[3:0] == 4'h7) & !AV
| (COND_R[3:0] == 4'h8) & AC
| (COND_R[3:0] == 4'h9) & !AC;
assign #`da condOK_E2 = (COND_R[3:0] == 4'ha) & AS
| (COND_R[3:0] == 4'hb) & !AS;
assign #`da condOK_E = (condOK_E1 & ~update_AZ)
| (condOK_E2 & ~update_AS)
| pre_condOK_E3;
reg condOK_CE;
always @(posedge DSPCLK) begin
if (T_RST) condOK_CE <= #`da 1'b0;
else if (GO_E)
condOK_CE <= #`da pre_condOK_E;
end
`ifdef FD_RTL_SIM
wire condOK_C;
assign #`da condOK_C = condOK_CE
| (COND_E[3:0] == 4'h0) & AZ
| (COND_E[3:0] == 4'h1) & !AZ
| (COND_E[3:0] == 4'h2) & !((AN != AV) | AZ)
| (COND_E[3:0] == 4'h3) & ((AN != AV) | AZ)
| (COND_E[3:0] == 4'hc) & MV
| (COND_E[3:0] == 4'hd) & !MV
| (COND_E[3:0] == 4'he) & !CE;
assign CONDok_C = condOK_C;
`else
wire condOK_C_MV0;
wire condOK_C_MV1;
wire condOK_CB;
assign #`da condOK_C_MV0 = condOK_CE
| (COND_E[3:0] == 4'h0) & AZ
| (COND_E[3:0] == 4'h1) & !AZ
| (COND_E[3:0] == 4'h2) & !((AN != AV) | AZ)
| (COND_E[3:0] == 4'h3) & ((AN != AV) | AZ)
| (COND_E[3:0] == 4'hd)
| (COND_E[3:0] == 4'he) & !CE;
assign #`da condOK_C_MV1 = condOK_CE
| (COND_E[3:0] == 4'h0) & AZ
| (COND_E[3:0] == 4'h1) & !AZ
| (COND_E[3:0] == 4'h2) & !((AN != AV) | AZ)
| (COND_E[3:0] == 4'h3) & ((AN != AV) | AZ)
| (COND_E[3:0] == 4'hc)
| (COND_E[3:0] == 4'he) & !CE;
GTECH_MUXI2 cell3(.A(condOK_C_MV0), .B(condOK_C_MV1), .S(MV), .Z(condOK_CB));
GTECH_NOT cell4(.A(condOK_CB), .Z(CONDok_C));
`endif
/*------------------------------------------------------*/
wire pre_termOK_E1;
wire pre_termOK_E2;
wire pre_termOK_E;
wire termOK_E1;
wire termOK_E2;
wire termOK_E;
assign #`da pre_termOK_E1 = (TERM_R[3:0] == 4'h4) & !(ANi != AVi)
| (TERM_R[3:0] == 4'h5) & (ANi != AVi)
| (TERM_R[3:0] == 4'h6) & !AVi
| (TERM_R[3:0] == 4'h7) & AVi
| (TERM_R[3:0] == 4'h8) & !ACi
| (TERM_R[3:0] == 4'h9) & ACi;
assign #`da pre_termOK_E2 = (TERM_R[3:0] == 4'ha) & !ASi
| (TERM_R[3:0] == 4'hb) & ASi;
assign #`da pre_termOK_E = (pre_termOK_E1 & update_AZ)
| (pre_termOK_E2 & update_AS)
| termOK_E;
assign #`da termOK_E1 = (TERM_R[3:0] == 4'h4) & !(AN != AV)
| (TERM_R[3:0] == 4'h5) & (AN != AV)
| (TERM_R[3:0] == 4'h6) & !AV
| (TERM_R[3:0] == 4'h7) & AV
| (TERM_R[3:0] == 4'h8) & !AC
| (TERM_R[3:0] == 4'h9) & AC;
assign #`da termOK_E2 = (TERM_R[3:0] == 4'ha) & !AS
| (TERM_R[3:0] == 4'hb) & AS;
assign #`da termOK_E = (termOK_E1 & ~update_AZ)
| (termOK_E2 & ~update_AS);
reg termOK_CE;
always @(posedge DSPCLK) begin
if (T_RST) termOK_CE <= #`da 1'b0;
else if (GO_E)
termOK_CE <= #`da pre_termOK_E;
end
`ifdef FD_RTL_SIM
wire termOK_C;
assign #`da termOK_C = termOK_CE
| (TERM_E[3:0] == 4'h0) & !AZ
| (TERM_E[3:0] == 4'h1) & AZ
| (TERM_E[3:0] == 4'h2) & ((AN != AV) | AZ)
| (TERM_E[3:0] == 4'h3) & !((AN != AV) | AZ)
| (TERM_E[3:0] == 4'hc) & !MV
| (TERM_E[3:0] == 4'hd) & MV
| (TERM_E[3:0] == 4'he) & CE;
assign TERMok_C = termOK_C;
`else
wire termOK_C_MV0;
wire termOK_C_MV1;
wire termOK_CB;
assign #`da termOK_C_MV0 = termOK_CE
| (TERM_E[3:0] == 4'h0) & !AZ
| (TERM_E[3:0] == 4'h1) & AZ
| (TERM_E[3:0] == 4'h2) & ((AN != AV) | AZ)
| (TERM_E[3:0] == 4'h3) & !((AN != AV) | AZ)
| (TERM_E[3:0] == 4'hc)
| (TERM_E[3:0] == 4'he) & CE;
assign #`da termOK_C_MV1 = termOK_CE
| (TERM_E[3:0] == 4'h0) & !AZ
| (TERM_E[3:0] == 4'h1) & AZ
| (TERM_E[3:0] == 4'h2) & ((AN != AV) | AZ)
| (TERM_E[3:0] == 4'h3) & !((AN != AV) | AZ)
| (TERM_E[3:0] == 4'hd)
| (TERM_E[3:0] == 4'he) & CE;
GTECH_MUXI2 cell1(.A(termOK_C_MV0), .B(termOK_C_MV1), .S(MV), .Z(termOK_CB));
GTECH_NOT cell2(.A(termOK_CB), .Z(TERMok_C));
`endif
endmodule
|
`include "../include/x_def.v"
module EM_CLA36 (/* IN */
SUM_E, CRY_E, MLSB_E,
MR00_E, FracMode_E, rnd_E, mzero_E, BIASRND,
/* OUT */
MACin_E);
input [37:1] SUM_E;
input [37:1] CRY_E;
input [2:0] MLSB_E;
input MR00_E;
input FracMode_E;
input rnd_E;
input mzero_E;
input BIASRND;
/****************************************/
/* Output declaration */
/****************************************/
output [39:0] MACin_E;
wire [37:1] PS;
assign PS[37:1] = SUM_E[37:1] ^ CRY_E[37:1];
wire [37:1] P, G;
assign P[36:1] = CRY_E[36:1] | SUM_E[36:1]; // Propagate Signal
assign G[36:1] = CRY_E[36:1] & SUM_E[36:1]; // Generate Signal
wire [18:1] G1;
assign G1[1] = G[2] | (G[1] & P[2]);
//
assign G1[2] = G[4] | (G[3] & P[4]);
//
assign G1[3] = G[6] | (G[5] & P[6]);
//
assign G1[4] = G[8] | (G[7] & P[8]);
//
assign G1[5] = G[10] | (G[9] & P[10]);
//
assign G1[6] = G[12] | (G[11] & P[12]);
//
assign G1[7] = G[14] | (G[13] & P[14]);
//
assign G1[8] = G[16] | (G[15] & P[16]);
//
assign G1[9] = G[18] | (G[17] & P[18]);
//
assign G1[10] = G[20] | (G[19] & P[20]);
//
assign G1[11] = G[22] | (G[21] & P[22]);
//
assign G1[12] = G[24] | (G[23] & P[24]);
//
assign G1[13] = G[26] | (G[25] & P[26]);
//
assign G1[14] = G[28] | (G[27] & P[28]);
//
assign G1[15] = G[30] | (G[29] & P[30]);
//
assign G1[16] = G[32] | (G[31] & P[32]);
//
assign G1[17] = G[34] | (G[33] & P[34]);
//
assign G1[18] = G[36] | (G[35] & P[36]);
//
//
wire [18:1] P1;
assign P1[1] = P[2] & P[1];
//
assign P1[2] = P[4] & P[3];
//
assign P1[3] = P[6] & P[5];
//
assign P1[4] = P[8] & P[7];
//
assign P1[5] = P[10] & P[9];
//
assign P1[6] = P[12] & P[11];
//
assign P1[7] = P[14] & P[13];
//
assign P1[8] = P[16] & P[15];
//
assign P1[9] = P[18] & P[17];
//
assign P1[10] = P[20] & P[19];
//
assign P1[11] = P[22] & P[21];
//
assign P1[12] = P[24] & P[23];
//
assign P1[13] = P[26] & P[25];
//
assign P1[14] = P[28] & P[27];
//
assign P1[15] = P[30] & P[29];
//
assign P1[16] = P[32] & P[31];
//
assign P1[17] = P[34] & P[33];
//
assign P1[18] = P[36] & P[35];
//
//
wire [9:1] G2;
assign G2[1] = G1[2] | (G1[1] & P1[2]);
//
assign G2[2] = G1[4] | (G1[3] & P1[4]);
//
assign G2[3] = G1[6] | (G1[5] & P1[6]);
//
assign G2[4] = G1[8] | (G1[7] & P1[8]);
//
assign G2[5] = G1[10] | (G1[9] & P1[10]);
//
assign G2[6] = G1[12] | (G1[11] & P1[12]);
//
assign G2[7] = G1[14] | (G1[13] & P1[14]);
//
assign G2[8] = G1[16] | (G1[15] & P1[16]);
//
assign G2[9] = G1[18] | (G1[17] & P1[18]);
//
//
wire [9:1] P2;
assign P2[1] = P1[2] & P1[1];
//
assign P2[2] = P1[4] & P1[3];
//
assign P2[3] = P1[6] & P1[5];
//
assign P2[4] = P1[8] & P1[7];
//
assign P2[5] = P1[10] & P1[9];
//
assign P2[6] = P1[12] & P1[11];
//
assign P2[7] = P1[14] & P1[13];
//
assign P2[8] = P1[16] & P1[15];
//
assign P2[9] = P1[18] & P1[17];
//
//
wire [3:1] G3;
assign G3[1] = G2[3] | (G2[2] & P2[3]) | (G2[1] & P2[3] & P2[2]);
//
assign G3[2] = G2[6] | (G2[5] & P2[6]) | (G2[4] & P2[6] & P2[5]);
//
assign G3[3] = G2[9] | (G2[8] & P2[9]) | (G2[7] & P2[9] & P2[8]);
//
//
wire [3:1] P3;
assign P3[1] = P2[3] & P2[2] & P2[1];
//
assign P3[2] = P2[6] & P2[5] & P2[4];
//
assign P3[3] = P2[9] & P2[8] & P2[7];
//
//
wire C36;
assign C36 = G3[3] | (G3[2] & P3[3]) | (G3[1] & P3[3] & P3[2]);
//
//
wire P4 = P3[3] & P3[2] & P3[1];
//
//
wire C35, C34, C33, C32, C31;
wire C30, C29, C28, C27, C26;
wire C25, C24, C23, C22, C21;
wire C20, C19, C18, C17, C16;
wire C15, C14, C13, C12, C11;
wire C10, C9, C8, C7, C6;
wire C5, C4, C3, C2, C1;
assign #`db C1 = G[1];
//
assign #`db C2 = G1[1];
//
assign #`db C3 = G[3] | (G1[1] & P[3]);
//
assign #`db C4 = G2[1];
//
assign #`db C5 = G[5] | (G2[1] & P[5]);
//
assign #`db C6 = G1[3] | (G2[1] & P1[3]);
//
assign #`db C7 = G[7] | (G1[3] & P[7]) | (G2[1] & P1[3] & P[7]);
//
assign #`db C8 = G2[2] | (G2[1] & P2[2]);
//
assign #`db C9 = G[9] | (G2[2] & P[9]) | (G2[1] & P2[2] & P[9]);
//
assign #`db C10 = G1[5] | (G2[2] & P1[5]) | (G2[1] & P2[2] & P1[5]);
//
assign #`db C11 = G[11] | (C10 & P[11]);
//
assign #`db C12 = G3[1];
//
assign #`db C13 = G[13] | G3[1] & P[13];
//
assign #`db C14 = G1[7] | (G3[1] & P1[7]);
//
assign #`db C15 = G[15] | (G1[7] & P[15]) | (G3[1] & P1[7] & P[15]);
//
assign #`db C16 = G2[4] | (G3[1] & P2[4]);
//
assign #`db C17 = G[17] | (G2[4] & P[17]) | (G3[1] & P2[4] & P[17]);
//
assign #`db C18 = G1[9] | (G2[4] & P1[9]) | (G3[1] & P2[4] & P1[9]);
//
assign #`db C19 = G[19] | (C18 & P[19]);
//
assign #`db C20 = G2[5] | (G2[4] & P2[5]) | (G3[1] & P2[4] & P2[5]);
//
assign #`db C21 = G[21] | (C20 & P[21]);
//
assign #`db C22 = G1[11] | (C20 & P1[11]);
//
assign #`db C23 = G[23] | (C22 & P[23]);
//
assign #`db C24 = G3[2] | (G3[1] & P3[2]);
//
assign #`db C25 = G[25] | (C24 & P[25]);
//
assign #`db C26 = G1[13] | (C24 & P1[13]);
//
assign #`db C27 = G[27] | (C26 & P[27]);
//
assign #`db C28 = G2[7] | (G3[2] & P2[7]) | (G3[1] & P2[7] & P3[2]);
//
assign #`db C29 = G[29] | (C28 & P[29]);
//
assign #`db C30 = G1[15] | (C29 & P1[15]);
//
assign #`db C31 = G[31] | (G1[15] & P[31]) | (C29 & P1[15] & P[31]);
//
assign #`db C32 = G2[8] | (G2[7] & P2[8]) | (G3[2] & P2[7] & P2[8]) | (G3[1] & P3[2] & P2[7] & P2[8]);
//
assign #`db C33 = G[33] | (C32 & P[33]);
//
assign #`db C34 = G1[17] | (C32 & P1[17]);
//
assign #`db C35 = G[35] | (G1[17] & P[35]) | (C32 & P1[17] & P[35]);
//
//
//
wire [39:0] Morig;
assign #`db Morig[3] = PS[1];
//
assign #`db Morig[4] = C1 ? (~PS[2]) : PS[2];
//
assign #`db Morig[5] = C2 ? (~PS[3]) : PS[3];
//
assign #`db Morig[6] = C3 ? (~PS[4]) : PS[4];
//
assign #`db Morig[7] = C4 ? (~PS[5]) : PS[5];
//
assign #`db Morig[8] = C5 ? (~PS[6]) : PS[6];
//
assign #`db Morig[9] = C6 ? (~PS[7]) : PS[7];
//
assign #`db Morig[10] = C7 ? (~PS[8]) : PS[8];
//
assign #`db Morig[11] = C8 ? (~PS[9]) : PS[9];
//
assign #`db Morig[12] = C9 ? (~PS[10]) : PS[10];
//
assign #`db Morig[13] = C10 ? (~PS[11]) : PS[11];
//
assign #`db Morig[14] = C11 ? (~PS[12]) : PS[12];
//
assign #`db Morig[15] = C12 ? (~PS[13]) : PS[13];
//
assign #`db Morig[16] = C13 ? (~PS[14]) : PS[14];
//
assign #`db Morig[17] = C14 ? (~PS[15]) : PS[15];
//
assign #`db Morig[18] = C15 ? (~PS[16]) : PS[16];
//
assign #`db Morig[19] = C16 ? (~PS[17]) : PS[17];
//
assign #`db Morig[20] = C17 ? (~PS[18]) : PS[18];
//
assign #`db Morig[21] = C18 ? (~PS[19]) : PS[19];
//
assign #`db Morig[22] = C19 ? (~PS[20]) : PS[20];
//
assign #`db Morig[23] = C20 ? (~PS[21]) : PS[21];
//
assign #`db Morig[24] = C21 ? (~PS[22]) : PS[22];
//
assign #`db Morig[25] = C22 ? (~PS[23]) : PS[23];
//
assign #`db Morig[26] = C23 ? (~PS[24]) : PS[24];
//
assign #`db Morig[27] = C24 ? (~PS[25]) : PS[25];
//
assign #`db Morig[28] = C25 ? (~PS[26]) : PS[26];
//
assign #`db Morig[29] = C26 ? (~PS[27]) : PS[27];
//
assign #`db Morig[30] = C27 ? (~PS[28]) : PS[28];
//
assign #`db Morig[31] = C28 ? (~PS[29]) : PS[29];
//
assign #`db Morig[32] = C29 ? (~PS[30]) : PS[30];
//
assign #`db Morig[33] = C30 ? (~PS[31]) : PS[31];
//
assign #`db Morig[34] = C31 ? (~PS[32]) : PS[32];
//
assign #`db Morig[35] = C32 ? (~PS[33]) : PS[33];
//
assign #`db Morig[36] = C33 ? (~PS[34]) : PS[34];
//
assign #`db Morig[37] = C34 ? (~PS[35]) : PS[35];
//
assign #`db Morig[38] = C35 ? (~PS[36]) : PS[36];
//
assign #`db Morig[39] = C36 ? (~PS[37]) : PS[37];
//
//
wire MR0_0;
assign MR0_0 = (MR00_E & (~mzero_E));
assign Morig[2:0] = MLSB_E[2:0];
wire [39:0] Mshft;
assign Mshft[39:0] = FracMode_E ? {Morig[38:0], MR0_0} : Morig[39:0];
wire MR_ZERO_0_15;
assign MR_ZERO_0_15 = (|Mshft[15:0]); // The LSB 16-bits == 0
wire rnd16;
assign rnd16 = (BIASRND | (!rnd_E) | MR_ZERO_0_15) & Mshft[16];
assign #2 MACin_E[39:0] = {Mshft[39:17], rnd16, Mshft[15:0]};
endmodule
|
`include "../include/x_def.v"
module EM_ARRAY(/* IN */
Cin_E, MRb_E, MRa_E,
P0_E, P1_E, P2_E,
P3_E, P4_E, P5_E,
P6_E, P7_E, P8_E,
/* OUT */
MLSB_E, SUM_E, CRY_E);
/*----------------------------------------------*/
input [16:0] Cin_E;
input [39:14] MRb_E;
input [15:0] MRa_E;
input [17:0] P0_E;
input [19:2] P1_E;
input [21:4] P2_E;
input [23:6] P3_E;
input [25:8] P4_E;
input [27:10] P5_E;
input [29:12] P6_E;
input [31:14] P7_E;
input [32:16] P8_E;
/*----------------------------------------------*/
output [2:0] MLSB_E;
output [39:3] SUM_E;
output [39:3] CRY_E;
wire [39:0] CSA10_i0 = {23'b0, Cin_E[16:0]};
wire [39:0] CSA10_i1 = {24'b0, MRa_E[15:0]};
wire [39:0] CSA10_i2 = {{22{P0_E[17]}}, P0_E[17:0]};
wire [39:0] S1_0;
wire [39:1] C1_0;
assign S1_0[39:0] = CSA10_i0[39:0] ^ CSA10_i1[39:0] ^ CSA10_i2[39:0];
assign C1_0[39:1] = CSA10_i0[38:0] & CSA10_i1[38:0]
| CSA10_i1[38:0] & CSA10_i2[38:0]
| CSA10_i2[38:0] & CSA10_i0[38:0];
wire [39:2] CSA11_i0 = {{20{P1_E[19]}}, P1_E[19:2]};
wire [39:2] CSA11_i1 = {{18{P2_E[21]}}, P2_E[21:4], 2'b0};
wire [39:2] CSA11_i2 = {{16{P3_E[23]}}, P3_E[23:6], 4'b0};
wire [39:2] S1_1;
wire [39:3] C1_1;
assign S1_1[39:2] = CSA11_i0[39:2] ^ CSA11_i1[39:2] ^ CSA11_i2[39:2];
assign C1_1[39:3] = CSA11_i0[38:2] & CSA11_i1[38:2]
| CSA11_i1[38:2] & CSA11_i2[38:2]
| CSA11_i2[38:2] & CSA11_i0[38:2];
wire [39:8] CSA12_i0 = {{14{P4_E[25]}}, P4_E[25:8]};
wire [39:8] CSA12_i1 = {{12{P5_E[27]}}, P5_E[27:10], 2'b0};
wire [39:8] CSA12_i2 = {{10{P6_E[29]}}, P6_E[29:12], 4'b0};
wire [39:8] S1_2;
wire [39:9] C1_2;
assign S1_2[39:8] = CSA12_i0[39:8] ^ CSA12_i1[39:8] ^ CSA12_i2[39:8];
assign C1_2[39:9] = CSA12_i0[38:8] & CSA12_i1[38:8]
| CSA12_i1[38:8] & CSA12_i2[38:8]
| CSA12_i2[38:8] & CSA12_i0[38:8];
wire [39:14] CSA13_i0 = {{8{P7_E[31]}}, P7_E[31:14]};
wire [39:14] CSA13_i1 = {{7{P8_E[32]}}, P8_E[32:16], 2'b0};
wire [39:14] CSA13_i2 = MRb_E[39:14];
wire [39:14] S1_3;
wire [39:15] C1_3;
assign S1_3[39:14] = CSA13_i0[39:14] ^ CSA13_i1[39:14] ^ CSA13_i2[39:14];
assign C1_3[39:15] = CSA13_i0[38:14] & CSA13_i1[38:14]
| CSA13_i1[38:14] & CSA13_i2[38:14]
| CSA13_i2[38:14] & CSA13_i0[38:14];
wire [39:1] CSA20_i0 = S1_0[39:1];
wire [39:1] CSA20_i1 = C1_0[39:1];
wire [39:1] CSA20_i2 = {S1_1[39:2], 1'b0};
wire [39:1] CSA20_i3 = {C1_1[39:3], 2'b0};
wire [39:1] G2_0;
wire [39:1] H2_0;
wire [39:1] P2_0;
wire [39:1] S2_0;
wire [39:2] C2_0;
assign G2_0[39:1] = ((CSA20_i0[39:1] | CSA20_i1[39:1])
& (CSA20_i2[39:1] | CSA20_i3[39:1]));
assign H2_0[39:1] = ~((CSA20_i0[39:1] & CSA20_i1[39:1])
| (CSA20_i2[39:1] & CSA20_i3[39:1]));
assign P2_0[39:1] = CSA20_i0[39:1] ^ CSA20_i1[39:1]
^ CSA20_i2[39:1] ^ CSA20_i3[39:1];
assign S2_0[39:1] = ~((P2_0[39:1] & {G2_0[38:1], 1'b0})
| (~P2_0[39:1] & ~{G2_0[38:1], 1'b0}));
assign C2_0[39:2] = ~((P2_0[38:1] & ~{G2_0[37:1], 1'b0})
| (~P2_0[38:1] & H2_0[38:1]));
wire [39:8] CSA21_i0 = S1_2[39:8];
wire [39:8] CSA21_i1 = {C1_2[39:9], 1'b0};
wire [39:8] CSA21_i2 = {S1_3[39:14], 6'b0};
wire [39:8] CSA21_i3 = {C1_3[39:15], 7'b0};
wire [39:8] G2_1;
wire [39:8] H2_1;
wire [39:8] P2_1;
wire [39:8] S2_1;
wire [39:9] C2_1;
assign G2_1[39:8] = ((CSA21_i0[39:8] | CSA21_i1[39:8])
& (CSA21_i2[39:8] | CSA21_i3[39:8]));
assign H2_1[39:8] = ~((CSA21_i0[39:8] & CSA21_i1[39:8])
| (CSA21_i2[39:8] & CSA21_i3[39:8]));
assign P2_1[39:8] = CSA21_i0[39:8] ^ CSA21_i1[39:8]
^ CSA21_i2[39:8] ^ CSA21_i3[39:8];
assign S2_1[39:8] = ~((P2_1[39:8] & {G2_1[38:8], 1'b0})
| (~P2_1[39:8] & ~{G2_1[38:8], 1'b0}));
assign C2_1[39:9] = ~((P2_1[38:8] & ~{G2_1[37:8], 1'b0})
| (~P2_1[38:8] & H2_1[38:8]));
wire [39:2] CSA30_i0 = S2_0[39:2];
wire [39:2] CSA30_i1 = C2_0[39:2];
wire [39:2] CSA30_i2 = {S2_1[39:8], 6'b0};
wire [39:2] CSA30_i3 = {C2_1[39:9], 7'b0};
wire [39:2] G3_0;
wire [39:2] H3_0;
wire [39:2] P3_0;
wire [39:2] S3_0;
wire [39:3] C3_0;
assign G3_0[39:2] = ((CSA30_i0[39:2] | CSA30_i1[39:2])
& (CSA30_i2[39:2] | CSA30_i3[39:2]));
assign H3_0[39:2] = ~((CSA30_i0[39:2] & CSA30_i1[39:2])
| (CSA30_i2[39:2] & CSA30_i3[39:2]));
assign P3_0[39:2] = CSA30_i0[39:2] ^ CSA30_i1[39:2]
^ CSA30_i2[39:2] ^ CSA30_i3[39:2];
assign S3_0[39:2] = ~((P3_0[39:2] & {G3_0[38:2], 1'b0})
| (~P3_0[39:2] & ~{G3_0[38:2], 1'b0}));
assign C3_0[39:3] = ~((P3_0[38:2] & ~{G3_0[37:2], 1'b0})
| (~P3_0[38:2] & H3_0[38:2]));
wire [2:0] MLSB_E;
wire [39:3] SUM_E;
wire [39:3] CRY_E;
assign #`da MLSB_E[2:0] = {S3_0[2], S2_0[1], S1_0[0]};
assign #`da SUM_E[39:3] = S3_0[39:3];
assign #`da CRY_E[39:3] = C3_0[39:3];
endmodule
|
/*--------------------------------------------------------------*/
/*--------------------------------------------------------------*/
/*--------------------------------------------------------------*/
/*--------------------------------------------------------------*/
`include "../include/x_def.v"
module EM_CORE(/* IN */
unsignX_E, unsignY_E, FracMode_E,
mzero_E, msub1_E, rnd_E,
MXOP_E, MYOP_E, MR2di, MR1di,
MR0di, msub2_E, msub3_E, msub4_E, msub5_E,
msub6_E, msub7_E, msub8_E, MACop_E, BIASRND,
MACin);
input unsignX_E, unsignY_E, msub1_E;
input FracMode_E, mzero_E, rnd_E;
input [15:0] MXOP_E;
input [15:0] MYOP_E;
input [7:0] MR2di;
input [15:0] MR1di;
input [15:0] MR0di;
input msub2_E;
input msub3_E;
input msub4_E;
input msub5_E;
input msub6_E;
input msub7_E;
input msub8_E;
input MACop_E;
input BIASRND;
output [39:0] MACin;
wire [16:0] Cin_E;
wire [39:14] MRb_E;
wire [15:0] MRa_E;
wire [17:0] P0_E;
wire [19:2] P1_E;
wire [21:4] P2_E;
wire [23:6] P3_E;
wire [25:8] P4_E;
wire [27:10] P5_E;
wire [29:12] P6_E;
wire [31:14] P7_E;
wire [32:16] P8_E;
wire X16, Y16;
wire mzero_0, mzero_1;
wire [17:0] X1p, X2p;
wire [17:0] X1m, X2m;
wire [7:0] MR2;
wire [15:0] MR1, MR0;
assign X16 = (~unsignX_E) & MXOP_E[15];
assign Y16 = (~unsignY_E) & MYOP_E[15];
assign X1p[17:0] = {X16, X16, MXOP_E[15:0]};
assign X2p[17:0] = {X1p[16:0], 1'b0};
assign X1m[17:0] = ~X1p[17:0];
assign X2m[17:0] = {X1m[16:0], 1'b0};
assign MR2[7:0] = MR2di[7:0] & {8{MACop_E}};
assign MR1[15:0] = MR1di[15:0] & {16{MACop_E}};
assign MR0[15:0] = MR0di[15:0] & {16{MACop_E}};
assign mzero_0 = FracMode_E && rnd_E;
assign mzero_1 = (~FracMode_E) && rnd_E;
assign MRa_E[15:0] = mzero_E ? 16'b0 :
FracMode_E ? {1'b0, MR0[15:1]} : MR0[15:0];
assign MRb_E[39:14] = mzero_E ? {24'b0, mzero_1, mzero_0} :
FracMode_E ? {MR2[7], MR2[7:0], MR1[15:0], rnd_E} :
{MR2[7:0], MR1[15:0], rnd_E, 1'b0};
/*--------------------------------------------------------------*/
/*--------------------------------------------------------------*/
wire P0_1p, P0_2p, P0_1m, P0_2m;
wire P1_1p, P1_2p, P1_1m, P1_2m;
wire P2_1p, P2_2p, P2_1m, P2_2m;
wire P3_1p, P3_2p, P3_1m, P3_2m;
wire P4_1p, P4_2p, P4_1m, P4_2m;
wire P5_1p, P5_2p, P5_1m, P5_2m;
wire P6_1p, P6_2p, P6_1m, P6_2m;
wire P7_1p, P7_2p, P7_1m, P7_2m;
wire P8_1p, P8_1m;
PSEL P0_sel(msub1_E, {MYOP_E[1:0], 1'b0}, P0_1p, P0_2p, P0_1m, P0_2m);
PSEL P1_sel(msub2_E, MYOP_E[3:1], P1_1p, P1_2p, P1_1m, P1_2m);
PSEL P2_sel(msub3_E, MYOP_E[5:3], P2_1p, P2_2p, P2_1m, P2_2m);
PSEL P3_sel(msub4_E, MYOP_E[7:5], P3_1p, P3_2p, P3_1m, P3_2m);
PSEL P4_sel(msub5_E, MYOP_E[9:7], P4_1p, P4_2p, P4_1m, P4_2m);
PSEL P5_sel(msub6_E, MYOP_E[11:9], P5_1p, P5_2p, P5_1m, P5_2m);
PSEL P6_sel(msub7_E, MYOP_E[13:11], P6_1p, P6_2p, P6_1m, P6_2m);
PSEL P7_sel(msub8_E, MYOP_E[15:13], P7_1p, P7_2p, P7_1m, P7_2m);
/*--------------------------------------------------------------*/
/*--------------------------------------------------------------*/
assign P8_1p = unsignY_E & MYOP_E[15] & (~msub1_E);
assign P8_1m = unsignY_E & MYOP_E[15] & msub2_E;
/*--------------------------------------------------------------*/
/*--------------------------------------------------------------*/
assign Cin_E[16:0] = {P8_1m, P7_2m, P7_1m, P6_2m, P6_1m, P5_2m, P5_1m,
P4_2m, P4_1m, P3_2m, P3_1m, P2_2m, P2_1m, P1_2m,
P1_1m, P0_2m, P0_1m};
PPART P0_part(P0_1p, P0_2p, P0_1m, P0_2m,
X1p, X2p, X1m, X2m, P0_E[17:0]);
PPART P1_part(P1_1p, P1_2p, P1_1m, P1_2m,
X1p, X2p, X1m, X2m, P1_E[19:2]);
PPART P2_part(P2_1p, P2_2p, P2_1m, P2_2m,
X1p, X2p, X1m, X2m, P2_E[21:4]);
PPART p3_part(P3_1p, P3_2p, P3_1m, P3_2m,
X1p, X2p, X1m, X2m, P3_E[23:6]);
PPART p4_part(P4_1p, P4_2p, P4_1m, P4_2m,
X1p, X2p, X1m, X2m, P4_E[25:8]);
PPART p5_part(P5_1p, P5_2p, P5_1m, P5_2m,
X1p, X2p, X1m, X2m, P5_E[27:10]);
PPART p6_part(P6_1p, P6_2p, P6_1m, P6_2m,
X1p, X2p, X1m, X2m, P6_E[29:12]);
PPART p7_part(P7_1p, P7_2p, P7_1m, P7_2m,
X1p, X2p, X1m, X2m, P7_E[31:14]);
assign P8_E[32:16] = ({17{P8_1p}} & X1p[16:0]) | {17{P8_1m}} & X1m[16:0];
wire [2:0] MLSB_E;
wire [39:3] SUM_E;
wire [39:3] CRY_E;
wire [39:0] CSA10_i0 = {23'b0, Cin_E[16:0]};
wire [39:0] CSA10_i1 = {24'b0, MRa_E[15:0]};
wire [39:0] CSA10_i2 = {{22{P0_E[17]}}, P0_E[17:0]};
wire [39:0] S1_0;
wire [39:1] C1_0;
assign S1_0[39:0] = CSA10_i0[39:0] ^ CSA10_i1[39:0] ^ CSA10_i2[39:0];
assign C1_0[39:1] = CSA10_i0[38:0] & CSA10_i1[38:0]
| CSA10_i1[38:0] & CSA10_i2[38:0]
| CSA10_i2[38:0] & CSA10_i0[38:0];
wire [39:2] CSA11_i0 = {{20{P1_E[19]}}, P1_E[19:2]};
wire [39:2] CSA11_i1 = {{18{P2_E[21]}}, P2_E[21:4], 2'b0};
wire [39:2] CSA11_i2 = {{16{P3_E[23]}}, P3_E[23:6], 4'b0};
wire [39:2] S1_1;
wire [39:3] C1_1;
assign S1_1[39:2] = CSA11_i0[39:2] ^ CSA11_i1[39:2] ^ CSA11_i2[39:2];
assign C1_1[39:3] = CSA11_i0[38:2] & CSA11_i1[38:2]
| CSA11_i1[38:2] & CSA11_i2[38:2]
| CSA11_i2[38:2] & CSA11_i0[38:2];
wire [39:8] CSA12_i0 = {{14{P4_E[25]}}, P4_E[25:8]};
wire [39:8] CSA12_i1 = {{12{P5_E[27]}}, P5_E[27:10], 2'b0};
wire [39:8] CSA12_i2 = {{10{P6_E[29]}}, P6_E[29:12], 4'b0};
wire [39:8] S1_2;
wire [39:9] C1_2;
assign S1_2[39:8] = CSA12_i0[39:8] ^ CSA12_i1[39:8] ^ CSA12_i2[39:8];
assign C1_2[39:9] = CSA12_i0[38:8] & CSA12_i1[38:8]
| CSA12_i1[38:8] & CSA12_i2[38:8]
| CSA12_i2[38:8] & CSA12_i0[38:8];
wire [39:14] CSA13_i0 = {{8{P7_E[31]}}, P7_E[31:14]};
wire [39:14] CSA13_i1 = {{7{P8_E[32]}}, P8_E[32:16], 2'b0};
wire [39:14] CSA13_i2 = MRb_E[39:14];
wire [39:14] S1_3;
wire [39:15] C1_3;
assign S1_3[39:14] = CSA13_i0[39:14] ^ CSA13_i1[39:14] ^ CSA13_i2[39:14];
assign C1_3[39:15] = CSA13_i0[38:14] & CSA13_i1[38:14]
| CSA13_i1[38:14] & CSA13_i2[38:14]
| CSA13_i2[38:14] & CSA13_i0[38:14];
wire [39:1] CSA20_i0 = S1_0[39:1];
wire [39:1] CSA20_i1 = C1_0[39:1];
wire [39:1] CSA20_i2 = {S1_1[39:2], 1'b0};
wire [39:1] CSA20_i3 = {C1_1[39:3], 2'b0};
wire [39:1] G2_0;
wire [39:1] H2_0;
wire [39:1] P2_0;
wire [39:1] S2_0;
wire [39:2] C2_0;
assign G2_0[39:1] = ((CSA20_i0[39:1] | CSA20_i1[39:1])
& (CSA20_i2[39:1] | CSA20_i3[39:1]));
assign H2_0[39:1] = ~((CSA20_i0[39:1] & CSA20_i1[39:1])
| (CSA20_i2[39:1] & CSA20_i3[39:1]));
assign P2_0[39:1] = CSA20_i0[39:1] ^ CSA20_i1[39:1]
^ CSA20_i2[39:1] ^ CSA20_i3[39:1];
assign S2_0[39:1] = ~((P2_0[39:1] & {G2_0[38:1], 1'b0})
| (~P2_0[39:1] & ~{G2_0[38:1], 1'b0}));
assign C2_0[39:2] = ~((P2_0[38:1] & ~{G2_0[37:1], 1'b0})
| (~P2_0[38:1] & H2_0[38:1]));
wire [39:8] CSA21_i0 = S1_2[39:8];
wire [39:8] CSA21_i1 = {C1_2[39:9], 1'b0};
wire [39:8] CSA21_i2 = {S1_3[39:14], 6'b0};
wire [39:8] CSA21_i3 = {C1_3[39:15], 7'b0};
wire [39:8] G2_1;
wire [39:8] H2_1;
wire [39:8] P2_1;
wire [39:8] S2_1;
wire [39:9] C2_1;
assign G2_1[39:8] = ((CSA21_i0[39:8] | CSA21_i1[39:8])
& (CSA21_i2[39:8] | CSA21_i3[39:8]));
assign H2_1[39:8] = ~((CSA21_i0[39:8] & CSA21_i1[39:8])
| (CSA21_i2[39:8] & CSA21_i3[39:8]));
assign P2_1[39:8] = CSA21_i0[39:8] ^ CSA21_i1[39:8]
^ CSA21_i2[39:8] ^ CSA21_i3[39:8];
assign S2_1[39:8] = ~((P2_1[39:8] & {G2_1[38:8], 1'b0})
| (~P2_1[39:8] & ~{G2_1[38:8], 1'b0}));
assign C2_1[39:9] = ~((P2_1[38:8] & ~{G2_1[37:8], 1'b0})
| (~P2_1[38:8] & H2_1[38:8]));
wire [39:2] CSA30_i0 = S2_0[39:2];
wire [39:2] CSA30_i1 = C2_0[39:2];
wire [39:2] CSA30_i2 = {S2_1[39:8], 6'b0};
wire [39:2] CSA30_i3 = {C2_1[39:9], 7'b0};
wire [39:2] G3_0;
wire [39:2] H3_0;
wire [39:2] P3_0;
wire [39:2] S3_0;
wire [39:3] C3_0;
assign G3_0[39:2] = ((CSA30_i0[39:2] | CSA30_i1[39:2])
& (CSA30_i2[39:2] | CSA30_i3[39:2]));
assign H3_0[39:2] = ~((CSA30_i0[39:2] & CSA30_i1[39:2])
| (CSA30_i2[39:2] & CSA30_i3[39:2]));
assign P3_0[39:2] = CSA30_i0[39:2] ^ CSA30_i1[39:2]
^ CSA30_i2[39:2] ^ CSA30_i3[39:2];
assign S3_0[39:2] = ~((P3_0[39:2] & {G3_0[38:2], 1'b0})
| (~P3_0[39:2] & ~{G3_0[38:2], 1'b0}));
assign C3_0[39:3] = ~((P3_0[38:2] & ~{G3_0[37:2], 1'b0})
| (~P3_0[38:2] & H3_0[38:2]));
assign #`da MLSB_E[2:0] = {S3_0[2], S2_0[1], S1_0[0]};
assign #`da SUM_E[39:3] = S3_0[39:3];
assign #`da CRY_E[39:3] = C3_0[39:3];
wire [37:1] PS;
assign PS[37:1] = SUM_E[39:3] ^ CRY_E[39:3];
wire [37:1] P, G;
assign P[36:1] = CRY_E[38:3] | SUM_E[38:3];
assign G[36:1] = CRY_E[38:3] & SUM_E[38:3];
wire [18:1] G1;
assign G1[1] = G[2] | (G[1] & P[2]);
assign G1[2] = G[4] | (G[3] & P[4]);
assign G1[3] = G[6] | (G[5] & P[6]);
assign G1[4] = G[8] | (G[7] & P[8]);
assign G1[5] = G[10] | (G[9] & P[10]);
assign G1[6] = G[12] | (G[11] & P[12]);
assign G1[7] = G[14] | (G[13] & P[14]);
assign G1[8] = G[16] | (G[15] & P[16]);
assign G1[9] = G[18] | (G[17] & P[18]);
assign G1[10] = G[20] | (G[19] & P[20]);
assign G1[11] = G[22] | (G[21] & P[22]);
assign G1[12] = G[24] | (G[23] & P[24]);
assign G1[13] = G[26] | (G[25] & P[26]);
assign G1[14] = G[28] | (G[27] & P[28]);
assign G1[15] = G[30] | (G[29] & P[30]);
assign G1[16] = G[32] | (G[31] & P[32]);
assign G1[17] = G[34] | (G[33] & P[34]);
assign G1[18] = G[36] | (G[35] & P[36]);
wire [18:1] P1;
assign P1[1] = P[2] & P[1];
assign P1[2] = P[4] & P[3];
assign P1[3] = P[6] & P[5];
assign P1[4] = P[8] & P[7];
assign P1[5] = P[10] & P[9];
assign P1[6] = P[12] & P[11];
assign P1[7] = P[14] & P[13];
assign P1[8] = P[16] & P[15];
assign P1[9] = P[18] & P[17];
assign P1[10] = P[20] & P[19];
assign P1[11] = P[22] & P[21];
assign P1[12] = P[24] & P[23];
assign P1[13] = P[26] & P[25];
assign P1[14] = P[28] & P[27];
assign P1[15] = P[30] & P[29];
assign P1[16] = P[32] & P[31];
assign P1[17] = P[34] & P[33];
assign P1[18] = P[36] & P[35];
wire [9:1] G2;
assign G2[1] = G1[2] | (G1[1] & P1[2]);
assign G2[2] = G1[4] | (G1[3] & P1[4]);
assign G2[3] = G1[6] | (G1[5] & P1[6]);
assign G2[4] = G1[8] | (G1[7] & P1[8]);
assign G2[5] = G1[10] | (G1[9] & P1[10]);
assign G2[6] = G1[12] | (G1[11] & P1[12]);
assign G2[7] = G1[14] | (G1[13] & P1[14]);
assign G2[8] = G1[16] | (G1[15] & P1[16]);
assign G2[9] = G1[18] | (G1[17] & P1[18]);
wire [9:1] P2;
assign P2[1] = P1[2] & P1[1];
assign P2[2] = P1[4] & P1[3];
assign P2[3] = P1[6] & P1[5];
assign P2[4] = P1[8] & P1[7];
assign P2[5] = P1[10] & P1[9];
assign P2[6] = P1[12] & P1[11];
assign P2[7] = P1[14] & P1[13];
assign P2[8] = P1[16] & P1[15];
assign P2[9] = P1[18] & P1[17];
wire [3:1] G3;
assign G3[1] = G2[3] | (G2[2] & P2[3]) | (G2[1] & P2[3] & P2[2]);
assign G3[2] = G2[6] | (G2[5] & P2[6]) | (G2[4] & P2[6] & P2[5]);
assign G3[3] = G2[9] | (G2[8] & P2[9]) | (G2[7] & P2[9] & P2[8]);
wire [3:1] P3;
assign P3[1] = P2[3] & P2[2] & P2[1];
assign P3[2] = P2[6] & P2[5] & P2[4];
assign P3[3] = P2[9] & P2[8] & P2[7];
wire C36;
assign C36 = G3[3] | (G3[2] & P3[3]) | (G3[1] & P3[3] & P3[2]);
wire P4 = P3[3] & P3[2] & P3[1];
wire C35, C34, C33, C32, C31;
wire C30, C29, C28, C27, C26;
wire C25, C24, C23, C22, C21;
wire C20, C19, C18, C17, C16;
wire C15, C14, C13, C12, C11;
wire C10, C9, C8, C7, C6;
wire C5, C4, C3, C2, C1;
assign #`db C1 = G[1];
assign #`db C2 = G1[1];
assign #`db C3 = G[3] | (G1[1] & P[3]);
assign #`db C4 = G2[1];
assign #`db C5 = G[5] | (G2[1] & P[5]);
assign #`db C6 = G1[3] | (G2[1] & P1[3]);
assign #`db C7 = G[7] | (G1[3] & P[7]) | (G2[1] & P1[3] & P[7]);
assign #`db C8 = G2[2] | (G2[1] & P2[2]);
assign #`db C9 = G[9] | (G2[2] & P[9]) | (G2[1] & P2[2] & P[9]);
assign #`db C10 = G1[5] | (G2[2] & P1[5]) | (G2[1] & P2[2] & P1[5]);
assign #`db C11 = G[11] | (C10 & P[11]);
assign #`db C12 = G3[1];
assign #`db C13 = G[13] | G3[1] & P[13];
assign #`db C14 = G1[7] | (G3[1] & P1[7]);
assign #`db C15 = G[15] | (G1[7] & P[15]) | (G3[1] & P1[7] & P[15]);
assign #`db C16 = G2[4] | (G3[1] & P2[4]);
assign #`db C17 = G[17] | (G2[4] & P[17]) | (G3[1] & P2[4] & P[17]);
assign #`db C18 = G1[9] | (G2[4] & P1[9]) | (G3[1] & P2[4] & P1[9]);
assign #`db C19 = G[19] | (C18 & P[19]);
assign #`db C20 = G2[5] | (G2[4] & P2[5]) | (G3[1] & P2[4] & P2[5]);
assign #`db C21 = G[21] | (C20 & P[21]);
assign #`db C22 = G1[11] | (C20 & P1[11]);
assign #`db C23 = G[23] | (C22 & P[23]);
assign #`db C24 = G3[2] | (G3[1] & P3[2]);
assign #`db C25 = G[25] | (C24 & P[25]);
assign #`db C26 = G1[13] | (C24 & P1[13]);
assign #`db C27 = G[27] | (C26 & P[27]);
assign #`db C28 = G2[7] | (G3[2] & P2[7]) | (G3[1] & P2[7] & P3[2]);
assign #`db C29 = G[29] | (C28 & P[29]);
assign #`db C30 = G1[15] | (C29 & P1[15]);
assign #`db C31 = G[31] | (G1[15] & P[31]) | (C29 & P1[15] & P[31]);
assign #`db C32 = G2[8] | (G2[7] & P2[8]) | (G3[2] & P2[7] & P2[8]) | (G3[1] & P3[2] & P2[7] & P2[8]);
assign #`db C33 = G[33] | (C32 & P[33]);
assign #`db C34 = G1[17] | (C32 & P1[17]);
assign #`db C35 = G[35] | (G1[17] & P[35]) | (C32 & P1[17] & P[35]);
wire [39:0] Morig;
assign #`db Morig[3] = PS[1];
assign #`db Morig[4] = C1 ? (~PS[2]) : PS[2];
assign #`db Morig[5] = C2 ? (~PS[3]) : PS[3];
assign #`db Morig[6] = C3 ? (~PS[4]) : PS[4];
assign #`db Morig[7] = C4 ? (~PS[5]) : PS[5];
assign #`db Morig[8] = C5 ? (~PS[6]) : PS[6];
assign #`db Morig[9] = C6 ? (~PS[7]) : PS[7];
assign #`db Morig[10] = C7 ? (~PS[8]) : PS[8];
assign #`db Morig[11] = C8 ? (~PS[9]) : PS[9];
assign #`db Morig[12] = C9 ? (~PS[10]) : PS[10];
assign #`db Morig[13] = C10 ? (~PS[11]) : PS[11];
assign #`db Morig[14] = C11 ? (~PS[12]) : PS[12];
assign #`db Morig[15] = C12 ? (~PS[13]) : PS[13];
assign #`db Morig[16] = C13 ? (~PS[14]) : PS[14];
assign #`db Morig[17] = C14 ? (~PS[15]) : PS[15];
assign #`db Morig[18] = C15 ? (~PS[16]) : PS[16];
assign #`db Morig[19] = C16 ? (~PS[17]) : PS[17];
assign #`db Morig[20] = C17 ? (~PS[18]) : PS[18];
assign #`db Morig[21] = C18 ? (~PS[19]) : PS[19];
assign #`db Morig[22] = C19 ? (~PS[20]) : PS[20];
assign #`db Morig[23] = C20 ? (~PS[21]) : PS[21];
assign #`db Morig[24] = C21 ? (~PS[22]) : PS[22];
assign #`db Morig[25] = C22 ? (~PS[23]) : PS[23];
assign #`db Morig[26] = C23 ? (~PS[24]) : PS[24];
assign #`db Morig[27] = C24 ? (~PS[25]) : PS[25];
assign #`db Morig[28] = C25 ? (~PS[26]) : PS[26];
assign #`db Morig[29] = C26 ? (~PS[27]) : PS[27];
assign #`db Morig[30] = C27 ? (~PS[28]) : PS[28];
assign #`db Morig[31] = C28 ? (~PS[29]) : PS[29];
assign #`db Morig[32] = C29 ? (~PS[30]) : PS[30];
assign #`db Morig[33] = C30 ? (~PS[31]) : PS[31];
assign #`db Morig[34] = C31 ? (~PS[32]) : PS[32];
assign #`db Morig[35] = C32 ? (~PS[33]) : PS[33];
assign #`db Morig[36] = C33 ? (~PS[34]) : PS[34];
assign #`db Morig[37] = C34 ? (~PS[35]) : PS[35];
assign #`db Morig[38] = C35 ? (~PS[36]) : PS[36];
assign #`db Morig[39] = C36 ? (~PS[37]) : PS[37];
wire MR0_0;
assign MR0_0 = (MR0di[0] & (~mzero_E));
assign Morig[2:0] = MLSB_E[2:0];
wire [39:0] Mshft;
assign Mshft[39:0] = FracMode_E ? {Morig[38:0], MR0_0} : Morig[39:0];
wire MR_ZERO_0_15;
assign MR_ZERO_0_15 = (|Mshft[15:0]);
wire rnd16;
assign rnd16 = (BIASRND | (!rnd_E) | MR_ZERO_0_15) & Mshft[16];
assign #2 MACin[39:0] = {Mshft[39:17], rnd16, Mshft[15:0]};
endmodule
|
/*------------------------------------------------------*/
/*------------------------------------------------------*/
/*------------------------------------------------------*/
/*------------------------------------------------------*/
module EM_DEC(/* IN */
Xop_D, Xop_E, Yop_D, Yop_E, AMF_D,
EX_enc, GO_C, SHADOW,
MTMX0_Eg, MTMX1_Eg, MTMY0_Eg, MTMY1_Eg, BYPASSMX_D,
BYPASSMY_D, GO_MAC, DSPCLK, GO_E, MACop_E,
updMF_E, updMR_E, MACop_R,
`ifdef FD_DFT
SCAN_TEST,
`endif
updateMX0s, updateMX0r, updateMX1s, updateMX1r, updateMRs,
updateMY0s, updateMY0r, updateMY1s, updateMY1r, updateMRr,
selMY_D, selMX_D, zeroMY_D, msub1_E, mzero_E,
rnd_E, unsignX_E, unsignY_E, updateMFs, updateMFr,
Rstore_MR0_D, Rstore_MR1_D, Rstore_MR2_D, Rstore_MR0_E,
Rstore_MR1_E, Rstore_MR2_E, updateMV, MXBy_R,
MYBy_R, msub2_E, msub3_E,
msub4_E, msub5_E, msub6_E, msub7_E, msub8_E);
input [2:0] Xop_D, Xop_E;
input [1:0] Yop_D, Yop_E;
input [3:0] AMF_D;
input EX_enc, GO_C;
input SHADOW;
input MACop_E, MTMX0_Eg;
input MTMX1_Eg, MTMY0_Eg, MTMY1_Eg;
input BYPASSMX_D, BYPASSMY_D;
input GO_MAC;
input DSPCLK, GO_E;
input updMF_E, updMR_E;
input MACop_R;
`ifdef FD_DFT
input SCAN_TEST;
`endif
output updateMX0s, updateMX0r, updateMX1s;
output updateMX1r, updateMY0s, updateMY0r;
output updateMY1s, updateMY1r;
output selMY_D, selMX_D;
output zeroMY_D, msub1_E;
output mzero_E, rnd_E;
output unsignX_E, unsignY_E;
output updateMFs, updateMFr;
output Rstore_MR0_D, Rstore_MR1_D;
output Rstore_MR2_D, Rstore_MR0_E;
output Rstore_MR1_E, Rstore_MR2_E;
output updateMV, updateMRr, updateMRs;
output MXBy_R, MYBy_R;
output msub2_E, msub3_E, msub4_E, msub5_E;
output msub6_E, msub7_E, msub8_E;
/*----------------------------------------------*/
/*----------------------------------------------*/
/*----------------------------------------------*/
wire selMX_D, selMY_D;
assign selMX_D = GO_MAC ? (Xop_E[2:1] == 2'b00)
: (Xop_D[2:1] == 2'b00);
assign selMY_D = GO_MAC ? (Yop_E[1] == 1'b0)
: (Yop_D[1] == 1'b0);
assign zeroMY_D = GO_MAC ? (Yop_E[1:0] == 2'b11)
: (Yop_D[1:0] == 2'b11);
/*----------------------------------------------*/
/*----------------------------------------------*/
wire msub_D;
wire mzero_D;
wire rnd_D;
assign msub_D = (AMF_D[3:0] == 4'b0011) | (AMF_D[3:2] == 2'b11);
assign mzero_D = (AMF_D[3:0] == 4'b0001) | (AMF_D[3:2] == 2'b01);
assign rnd_D = (AMF_D[3:2] == 2'b00);
assign MXBy_R = BYPASSMX_D & ~GO_MAC;
assign MYBy_R = BYPASSMY_D & ~GO_MAC;
wire msub1_E, msub2_E, msub3_E;
wire msub4_E, msub5_E, msub6_E;
wire msub7_E, msub8_E, unsignY_E;
wire mzero_E, rnd_E, unsignX_E;
wire CLKEMCOREenb;
wire [11:0] EMCOREdi, EMCOREdo;
wire unsignX_D, unsignY_D;
assign unsignX_D = AMF_D[1] && (!rnd_D);
assign unsignY_D = AMF_D[0] && (!rnd_D);
assign CLKEMCOREenb = !MACop_R;
assign EMCOREdi[11:0] = {{8{msub_D}}, unsignX_D, unsignY_D, mzero_D, rnd_D};
assign {msub1_E, msub2_E, msub3_E, msub4_E, msub5_E, msub6_E, msub7_E, msub8_E,
unsignX_E, unsignY_E, mzero_E, rnd_E} = EMCOREdo[11:0];
`ifdef FD_DFT
REG12L emcorepi(DSPCLK, CLKEMCOREenb, GO_E, EMCOREdi[11:0], EMCOREdo[11:0], SCAN_TEST);
`else
REG12L emcorepi(DSPCLK, CLKEMCOREenb, GO_E, EMCOREdi[11:0], EMCOREdo[11:0]);
`endif
/*----------------------------------------------*/
/*----------------------------------------------*/
assign updateMX0r = !SHADOW && MTMX0_Eg;
assign updateMX0s = SHADOW && MTMX0_Eg;
assign updateMX1r = !SHADOW && MTMX1_Eg;
assign updateMX1s = SHADOW && MTMX1_Eg;
assign updateMY0r = !SHADOW && MTMY0_Eg;
assign updateMY0s = SHADOW && MTMY0_Eg;
assign updateMY1r = !SHADOW && MTMY1_Eg;
assign updateMY1s = SHADOW && MTMY1_Eg;
assign updateMFr = !SHADOW && updMF_E;
assign updateMFs = SHADOW && updMF_E;
assign updateMRr = !SHADOW && updMR_E;
assign updateMRs = SHADOW && updMR_E;
/*----------------------------------------------*/
/*----------------------------------------------*/
assign updateMV = MACop_E && EX_enc;
/*----------------------------------------------*/
/*----------------------------------------------*/
assign Rstore_MR0_D = (Xop_D[2:0] == 3'b011);
assign Rstore_MR1_D = (Xop_D[2:0] == 3'b100);
assign Rstore_MR2_D = (Xop_D[2:0] == 3'b101);
assign Rstore_MR0_E = (Xop_E[2:0] == 3'b011);
assign Rstore_MR1_E = (Xop_E[2:0] == 3'b100);
assign Rstore_MR2_E = (Xop_E[2:0] == 3'b101);
endmodule
|
/*----------------------------------------------*/
/*----------------------------------------------*/
/*----------------------------------------------*/
/*----------------------------------------------*/
module EM_MAC (/*---------------------- Input ----------------------*/
DSPCLK, GO_E, GO_C, EX_enc,
R_in_D,
satMR_Eg, MACop_E, updMF_E, updMR_E, DOUBLE_E,
MTMX0_Eg, MTMX1_Eg, MTMY0_Eg, MTMY1_Eg,
MTMR0_Eg, MTMR1_Eg, MTMR2_Eg, MFMX0_E,
MFMX1_E, MFMY0_E, MFMY1_E, MFMR0_E,
MFMR1_E, MFMR2_E, BYPASSMX_D, BYPASSMY_D, BYPASSR_D,
pMFMAC_E, MFMAC_E, accPM_E, Sq_R, GO_MAC, MACop_R,
Xop_D, Xop_E, Yop_D, Yop_E,
AMF_D,
SHADOW, FracMode_E,
BIASRND,
`ifdef FD_DFT
SCAN_TEST,
`endif
R_mac_E, R_mac_D,
updateMV, MVin,
DMDin, DMDmac, PMDin, PMDmac);
input DSPCLK, GO_E, GO_C, EX_enc;
input [15:0] R_in_D;
input DOUBLE_E;
input MTMX0_Eg, MTMX1_Eg, MTMY0_Eg;
input MTMY1_Eg, MTMR0_Eg, MTMR1_Eg, MTMR2_Eg;
input MFMX0_E, MFMX1_E, MFMY0_E, MFMY1_E;
input MFMR0_E, MFMR1_E, MFMR2_E, BYPASSMX_D;
input BYPASSMY_D, BYPASSR_D;
input [2:0] Xop_D, Xop_E;
input [1:0] Yop_D, Yop_E;
input [3:0] AMF_D;
input SHADOW, FracMode_E;
input pMFMAC_E, MFMAC_E;
input accPM_E;
input Sq_R, GO_MAC;
input satMR_Eg, MACop_E;
input updMF_E, updMR_E;
input MACop_R;
input BIASRND;
`ifdef FD_DFT
input SCAN_TEST;
`endif
output updateMV;
output MVin;
output [15:0] R_mac_E, R_mac_D;
input [15:0] DMDin;
output [15:0] DMDmac;
input [15:0] PMDin;
output [15:0] PMDmac;
/*-----------------------------------------------*/
wire updateMX0s, updateMX0r, updateMX1s, updateMX1r;
wire updateMY0s, updateMY0r, updateMY1s, updateMY1r;
wire updateMRs, updateMRr, selMY_D, selMX_D, zeroMY_D;
wire msub1_E, mzero_E, rnd_E;
wire unsignX_E, unsignY_E, updateMFs, updateMFr;
wire Rstore_MR0_D, Rstore_MR1_D, Rstore_MR2_D;
wire Rstore_MR0_E, Rstore_MR1_E, Rstore_MR2_E;
wire MXBy_R, MYBy_R;
wire msub2_E, msub3_E, msub4_E, msub5_E;
wire msub6_E, msub7_E, msub8_E;
EM_DEC em_dec(/* IN */
Xop_D[2:0], Xop_E[2:0], Yop_D[1:0], Yop_E[1:0], AMF_D[3:0],
EX_enc, GO_C, SHADOW,
MTMX0_Eg, MTMX1_Eg, MTMY0_Eg, MTMY1_Eg, BYPASSMX_D,
BYPASSMY_D, GO_MAC, DSPCLK, GO_E,
MACop_E, updMF_E, updMR_E, MACop_R,
`ifdef FD_DFT
SCAN_TEST,
`endif
updateMX0s, updateMX0r, updateMX1s, updateMX1r, updateMRs,
updateMY0s, updateMY0r, updateMY1s, updateMY1r, updateMRr,
selMY_D, selMX_D, zeroMY_D, msub1_E, mzero_E,
rnd_E, unsignX_E, unsignY_E, updateMFs, updateMFr,
Rstore_MR0_D, Rstore_MR1_D, Rstore_MR2_D, Rstore_MR0_E,
Rstore_MR1_E, Rstore_MR2_E, updateMV, MXBy_R,
MYBy_R, msub2_E, msub3_E,
msub4_E, msub5_E, msub6_E, msub7_E, msub8_E);
/*------------------------------------------------*/
wire [15:0] MXOP_E, MYOP_E;
wire [39:0] MACin;
wire [15:0] MR0, MR1;
wire [7:0] MR2;
wire [8:0] MRovf;
EM_REG em_reg(/* IN */
DSPCLK, SHADOW, GO_C, GO_E, DOUBLE_E,
updateMX0r, updateMX0s, updateMX1r, updateMX1s,
updateMY0s, updateMY0r, updateMY1s, updateMY1r,
MACin[39:0], updateMFs, updateMFr, satMR_Eg,
MTMR0_Eg, MTMR1_Eg, MTMR2_Eg, updateMRs, updateMRr,
MFMX0_E, MFMX1_E, MFMY0_E, MFMY1_E, MFMR0_E,
MFMR1_E, MFMR2_E, Xop_E[0], Xop_D[0], Yop_E[0], Yop_D[0], BYPASSR_D,
selMX_D, R_in_D[15:0], zeroMY_D, selMY_D,
Rstore_MR0_D, Rstore_MR1_D, Rstore_MR2_D, Rstore_MR0_E,
Rstore_MR1_E, Rstore_MR2_E, MFMAC_E, pMFMAC_E, accPM_E, Sq_R, GO_MAC,
MXBy_R, MYBy_R, MACop_R, MACop_E, EX_enc,
`ifdef FD_DFT
SCAN_TEST,
`endif
MXOP_E[15:0], MYOP_E[15:0], MR0[15:0], MR1[15:0], MR2[7:0],
R_mac_D[15:0], R_mac_E[15:0], MRovf[8:0],
DMDin[15:0], DMDmac[15:0], PMDin[15:0], PMDmac[15:0]);
/*-------------------------------------------------*/
EM_CORE em_core(/* IN */
unsignX_E, unsignY_E, FracMode_E,
mzero_E, msub1_E, rnd_E,
MXOP_E[15:0], MYOP_E[15:0], MR2[7:0],
MR1[15:0], MR0[15:0], msub2_E, msub3_E,
msub4_E, msub5_E, msub6_E, msub7_E, msub8_E,
MACop_E, BIASRND,
MACin[39:0]);
/*-------------------------------------------------*/
EM_MVOVF em_mvovf(/* IN */
MRovf[8:0],
MVin);
endmodule
|
`include "../include/x_def.v"
module EM_MVOVF(/* IN */
MRovf_C,
MVin_C);
/*------------------------------*/
/*------------------------------*/
input [8:0] MRovf_C;
/*------------------------------*/
/*------------------------------*/
output MVin_C;
assign #`da MVin_C = ~((MRovf_C[8:0] == 9'b000_000_000)
| (MRovf_C[8:0] == 9'b111_111_111));
endmodule
|
`include "../include/x_def.v"
module PSEL (/* IN */
msub, Y,
P_1p, P_2p, P_1m, P_2m);
input msub;
input [2:0] Y;
output P_1p;
output P_2p;
output P_1m;
output P_2m;
wire P_1pi, P_2pi, P_1mi, P_2mi;
assign P_1pi = (!Y[2]) & (Y[1] ^ Y[0]);
assign P_2pi = (!Y[2]) & (Y[1] & Y[0]);
assign P_1mi = Y[2] & (Y[1] ^ Y[0]);
assign P_2mi = Y[2] & (~(Y[1] | Y[0]));
assign #`da P_1p = msub ? P_1mi : P_1pi;
assign #`da P_2p = msub ? P_2mi : P_2pi;
assign #`da P_1m = msub ? P_1pi : P_1mi;
assign #`da P_2m = msub ? P_2pi : P_2mi;
endmodule
/*--------------------------------------------------------------*/
module PPART(/* IN */ PX_1p, PX_2p, PX_1m, PX_2m,
PX1p, PX2p, PX1m, PX2m,
PX[17:0]);
input PX_1p, PX_2p, PX_1m, PX_2m;
input [17:0] PX1p;
input [17:0] PX2p;
input [17:0] PX1m;
input [17:0] PX2m;
output [17:0] PX;
assign #`da PX[17:0] = ({18{PX_1p}} & PX1p[17:0]) |
({18{PX_2p}} & PX2p[17:0]) |
({18{PX_1m}} & PX1m[17:0]) |
({18{PX_2m}} & PX2m[17:0]) ;
endmodule
|
/*--------------------------------------------------------------*/
/*--------------------------------------------------------------*/
/*--------------------------------------------------------------*/
module EM_REG(/* In */
DSPCLK, SHADOW, GO_C, GO_E, DOUBLE_E,
updateMX0r, updateMX0s, updateMX1r, updateMX1s,
updateMY0s, updateMY0r, updateMY1s, updateMY1r,
MACin, updateMFs, updateMFr, satMR_Eg,
MTMR0_Eg, MTMR1_Eg, MTMR2_Eg, updateMRs, updateMRr,
MFMX0_E, MFMX1_E, MFMY0_E, MFMY1_E, MFMR0_E,
MFMR1_E, MFMR2_E, Xop0_E, Xop0_D, Yop0_E, Yop0_D, BYPASSR_D,
selMX_D, R_in_D, zeroMY_D, selMY_D,
Rstore_MR0_D, Rstore_MR1_D, Rstore_MR2_D, Rstore_MR0_E,
Rstore_MR1_E, Rstore_MR2_E, MFMAC_E, pMFMAC_E, accPM_E, Sq_R,
GO_MAC, MXBy_R, MYBy_R, MACop_R, MACop_E, EX_enc,
`ifdef FD_DFT
SCAN_TEST,
`endif
MXOP_E, MYOP_E, MR0, MR1, MR2,
R_mac_D, R_mac_E, MRovf,
DMDin, DMDmac, PMDin, PMDmac);
input DSPCLK, SHADOW, GO_C, DOUBLE_E, GO_E;
input updateMX0r, updateMX0s, updateMX1r, updateMX1s;
input updateMY0s, updateMY0r, updateMY1s, updateMY1r;
input updateMFs, updateMFr, satMR_Eg, updateMRs, updateMRr;
input [39:0] MACin;
input MTMR0_Eg, MTMR1_Eg, MTMR2_Eg;
input MFMX0_E, MFMX1_E, MFMY0_E, MFMY1_E, MFMR0_E;
input MFMR1_E, MFMR2_E;
input Xop0_D, Yop0_D, BYPASSR_D, selMX_D;
input zeroMY_D, selMY_D;
input Rstore_MR0_D, Rstore_MR1_D, Rstore_MR2_D;
input Rstore_MR0_E, Rstore_MR1_E, Rstore_MR2_E;
input [15:0] R_in_D;
input MFMAC_E, pMFMAC_E, accPM_E, Sq_R;
input GO_MAC, MXBy_R, MYBy_R;
input Xop0_E, Yop0_E;
input MACop_R, MACop_E, EX_enc;
`ifdef FD_DFT
input SCAN_TEST;
`endif
output [15:0] MXOP_E, MYOP_E;
output [15:0] MR0, MR1;
output [7:0] MR2;
output [8:0] MRovf;
output [15:0] R_mac_D, R_mac_E;
input [15:0] DMDin;
output [15:0] DMDmac;
input [15:0] PMDin;
output [15:0] PMDmac;
wire [15:0] DMDin1;
DMDbuf DMDIN_BUF(DMDin[15:0], DMDin1[15:0]);
wire [15:0] Xin;
assign Xin[15:0] = accPM_E ? PMDin[15:0] : DMDin1[15:0];
wire [15:0] MX0r, MX0s, MX1r, MX1s;
wire CLKMX0renb, CLKMX0senb, CLKMX1renb, CLKMX1senb;
assign CLKMX0renb = !updateMX0r;
assign CLKMX0senb = !updateMX0s;
assign CLKMX1renb = !updateMX1r;
assign CLKMX1senb = !updateMX1s;
`ifdef FD_DFT
REG16L mx0rwe(DSPCLK, CLKMX0renb, GO_C, Xin[15:0], MX0r[15:0], SCAN_TEST);
REG16L mx0swe(DSPCLK, CLKMX0senb, GO_C, Xin[15:0], MX0s[15:0], SCAN_TEST);
REG16L mx1rwe(DSPCLK, CLKMX1renb, GO_C, Xin[15:0], MX1r[15:0], SCAN_TEST);
REG16L mx1swe(DSPCLK, CLKMX1senb, GO_C, Xin[15:0], MX1s[15:0], SCAN_TEST);
`else
REG16L mx0rwe(DSPCLK, CLKMX0renb, GO_C, Xin[15:0], MX0r[15:0]);
REG16L mx0swe(DSPCLK, CLKMX0senb, GO_C, Xin[15:0], MX0s[15:0]);
REG16L mx1rwe(DSPCLK, CLKMX1renb, GO_C, Xin[15:0], MX1r[15:0]);
REG16L mx1swe(DSPCLK, CLKMX1senb, GO_C, Xin[15:0], MX1s[15:0]);
`endif
/*----------------------------------------------*/
wire [15:0] MX0;
wire [15:0] MX1;
wire [15:0] MX_D;
wire sel_XOP;
wire sel_YOP;
assign sel_XOP = GO_MAC ? Xop0_E : Xop0_D;
assign sel_YOP = GO_MAC ? Yop0_E : Yop0_D;
assign MX0[15:0] = SHADOW ? MX0s[15:0] : MX0r[15:0];
assign MX1[15:0] = SHADOW ? MX1s[15:0] : MX1r[15:0];
assign MX_D[15:0] = MXBy_R ? Xin[15:0] :
sel_XOP ? MX1[15:0] : MX0[15:0];
/*----------------------------------------------*/
/*----------------------------------------------*/
wire [15:0] MXOP_E;
wire CLKMXOPenb;
wire MXOPwe;
wire [15:0] MXOPDI2;
assign CLKMXOPenb = !(MACop_E || MACop_R);
assign MXOPwe = !selMX_D && (GO_MAC || GO_E);
assign MXOPDI2[15:0] = ((GO_MAC && MACop_E) || (GO_E && MACop_R)) ? MX_D[15:0] : MXOP_E[15:0];
`ifdef FD_DFT
REG2D16L mxopwe(DSPCLK, CLKMXOPenb, MXOPwe, R_in_D[15:0], MXOPDI2[15:0], MXOP_E[15:0], SCAN_TEST);
`else
REG2D16L mxopwe(DSPCLK, CLKMXOPenb, MXOPwe, R_in_D[15:0], MXOPDI2[15:0], MXOP_E[15:0]);
`endif
wire [15:0] Yin;
assign Yin[15:0] = (DOUBLE_E | accPM_E) ? PMDin[15:0] : DMDin[15:0];
wire [15:0] MY0r, MY0s, MY1r, MY1s;
wire CLKMY0renb, CLKMY0senb, CLKMY1renb, CLKMY1senb;
assign CLKMY0renb = !updateMY0r;
assign CLKMY0senb = !updateMY0s;
assign CLKMY1renb = !updateMY1r;
assign CLKMY1senb = !updateMY1s;
`ifdef FD_DFT
REG16L my0rwe(DSPCLK, CLKMY0renb, GO_C, Yin[15:0], MY0r[15:0], SCAN_TEST);
REG16L my0swe(DSPCLK, CLKMY0senb, GO_C, Yin[15:0], MY0s[15:0], SCAN_TEST);
REG16L my1rwe(DSPCLK, CLKMY1renb, GO_C, Yin[15:0], MY1r[15:0], SCAN_TEST);
REG16L my1swe(DSPCLK, CLKMY1senb, GO_C, Yin[15:0], MY1s[15:0], SCAN_TEST);
`else
REG16L my0rwe(DSPCLK, CLKMY0renb, GO_C, Yin[15:0], MY0r[15:0]);
REG16L my0swe(DSPCLK, CLKMY0senb, GO_C, Yin[15:0], MY0s[15:0]);
REG16L my1rwe(DSPCLK, CLKMY1renb, GO_C, Yin[15:0], MY1r[15:0]);
REG16L my1swe(DSPCLK, CLKMY1senb, GO_C, Yin[15:0], MY1s[15:0]);
`endif
wire [15:0] MY0;
wire [15:0] MY1;
wire [15:0] MF;
wire [15:0] MY;
wire [15:0] MX;
wire [15:0] MYOP_D;
wire [15:0] MFs, MFr;
assign MY0[15:0] = SHADOW ? MY0s[15:0] : MY0r[15:0];
assign MY1[15:0] = SHADOW ? MY1s[15:0] : MY1r[15:0];
assign MF[15:0] = SHADOW ? MFs[15:0] : MFr[15:0];
assign MY[15:0] = sel_YOP ? MY1[15:0] : MY0[15:0];
assign MX[15:0] = sel_XOP ? MX1[15:0] : MX0[15:0];
wire Sq_D;
reg Sq_E;
always @(posedge DSPCLK)
if (GO_E) Sq_E <= Sq_R;
assign Sq_D = GO_MAC ? Sq_E : Sq_R;
wire [15:0] MYOP_in_D;
assign MYOP_in_D[15:0] = {16{~MYBy_R & zeroMY_D & (GO_MAC | GO_E)}} & {16'h0000}
| {16{~MYBy_R & ~zeroMY_D & Sq_D & selMX_D & ~MXBy_R & (GO_MAC | GO_E)}} & MX[15:0]
| {16{~MYBy_R & ~zeroMY_D & ~Sq_D & selMY_D & (GO_MAC | GO_E)}} & MY[15:0]
| {16{~MYBy_R & ~zeroMY_D & ~Sq_D & ~selMY_D & (GO_MAC | GO_E)}} & MF[15:0]
| {16{~(GO_MAC | GO_E)}} & MYOP_E[15:0];
`ifdef FD_RTL_SIM
assign MYOP_D[15:0] = {16{MYBy_R & GO_E}} & Yin[15:0]
| {16{~MYBy_R & ~zeroMY_D & Sq_D & selMX_D & MXBy_R & GO_E}} & Xin[15:0]
| MYOP_in_D[15:0];
`else
wire my_s1, my_s0;
assign my_s1 = MYBy_R & (DOUBLE_E | accPM_E) & GO_E
| ~MYBy_R & ~zeroMY_D & Sq_D & selMX_D & MXBy_R & accPM_E & (GO_MAC | GO_E);
assign my_s0 = MYBy_R & ~(DOUBLE_E | accPM_E) & GO_E
| ~MYBy_R & ~zeroMY_D & Sq_D & selMX_D & MXBy_R & ~accPM_E & (GO_MAC | GO_E);
GTECH_MUX4 my_d0( .Z(MYOP_D[0]), .B(my_s1), .A(my_s0), .D0(MYOP_in_D[0]), .D1(DMDin[0]),
.D2(PMDin[0]), .D3(MYOP_in_D[0]) );
GTECH_MUX4 my_d1( .Z(MYOP_D[1]), .B(my_s1), .A(my_s0), .D0(MYOP_in_D[1]), .D1(DMDin[1]),
.D2(PMDin[1]), .D3(MYOP_in_D[1]) );
GTECH_MUX4 my_d2( .Z(MYOP_D[2]), .B(my_s1), .A(my_s0), .D0(MYOP_in_D[2]), .D1(DMDin[2]),
.D2(PMDin[2]), .D3(MYOP_in_D[2]) );
GTECH_MUX4 my_d3( .Z(MYOP_D[3]), .B(my_s1), .A(my_s0), .D0(MYOP_in_D[3]), .D1(DMDin[3]),
.D2(PMDin[3]), .D3(MYOP_in_D[3]) );
GTECH_MUX4 my_d4( .Z(MYOP_D[4]), .B(my_s1), .A(my_s0), .D0(MYOP_in_D[4]), .D1(DMDin[4]),
.D2(PMDin[4]), .D3(MYOP_in_D[4]) );
GTECH_MUX4 my_d5( .Z(MYOP_D[5]), .B(my_s1), .A(my_s0), .D0(MYOP_in_D[5]), .D1(DMDin[5]),
.D2(PMDin[5]), .D3(MYOP_in_D[5]) );
GTECH_MUX4 my_d6( .Z(MYOP_D[6]), .B(my_s1), .A(my_s0), .D0(MYOP_in_D[6]), .D1(DMDin[6]),
.D2(PMDin[6]), .D3(MYOP_in_D[6]) );
GTECH_MUX4 my_d7( .Z(MYOP_D[7]), .B(my_s1), .A(my_s0), .D0(MYOP_in_D[7]), .D1(DMDin[7]),
.D2(PMDin[7]), .D3(MYOP_in_D[7]) );
GTECH_MUX4 my_d8( .Z(MYOP_D[8]), .B(my_s1), .A(my_s0), .D0(MYOP_in_D[8]), .D1(DMDin[8]),
.D2(PMDin[8]), .D3(MYOP_in_D[8]) );
GTECH_MUX4 my_d9( .Z(MYOP_D[9]), .B(my_s1), .A(my_s0), .D0(MYOP_in_D[9]), .D1(DMDin[9]),
.D2(PMDin[9]), .D3(MYOP_in_D[9]) );
GTECH_MUX4 my_d10( .Z(MYOP_D[10]), .B(my_s1), .A(my_s0), .D0(MYOP_in_D[10]), .D1(DMDin[10]),
.D2(PMDin[10]), .D3(MYOP_in_D[10]) );
GTECH_MUX4 my_d11( .Z(MYOP_D[11]), .B(my_s1), .A(my_s0), .D0(MYOP_in_D[11]), .D1(DMDin[11]),
.D2(PMDin[11]), .D3(MYOP_in_D[11]) );
GTECH_MUX4 my_d12( .Z(MYOP_D[12]), .B(my_s1), .A(my_s0), .D0(MYOP_in_D[12]), .D1(DMDin[12]),
.D2(PMDin[12]), .D3(MYOP_in_D[12]) );
GTECH_MUX4 my_d13( .Z(MYOP_D[13]), .B(my_s1), .A(my_s0), .D0(MYOP_in_D[13]), .D1(DMDin[13]),
.D2(PMDin[13]), .D3(MYOP_in_D[13]) );
GTECH_MUX4 my_d14( .Z(MYOP_D[14]), .B(my_s1), .A(my_s0), .D0(MYOP_in_D[14]), .D1(DMDin[14]),
.D2(PMDin[14]), .D3(MYOP_in_D[14]) );
GTECH_MUX4 my_d15( .Z(MYOP_D[15]), .B(my_s1), .A(my_s0), .D0(MYOP_in_D[15]), .D1(DMDin[15]),
.D2(PMDin[15]), .D3(MYOP_in_D[15]) );
`endif
/*--------------------------------------------*/
/*--------------------------------------------*/
wire [15:0] MYOP_E;
wire CLKMYOPenb;
wire MYOPwe;
assign CLKMYOPenb = !(MACop_R || MACop_E);
assign MYOPwe = (!MYBy_R) && (!zeroMY_D) && Sq_D && (!selMX_D) && (GO_MAC || GO_E);
`ifdef FD_DFT
REG2D16L myopwe(DSPCLK, CLKMYOPenb, MYOPwe, R_in_D[15:0], MYOP_D[15:0], MYOP_E[15:0], SCAN_TEST);
`else
REG2D16L myopwe(DSPCLK, CLKMYOPenb, MYOPwe, R_in_D[15:0], MYOP_D[15:0], MYOP_E[15:0]);
`endif
/*--------------------------------------------*/
wire CLKMFsenb, CLKMFrenb;
wire MFrwe, MFswe;
assign CLKMFsenb = !updateMFs;
assign CLKMFrenb = !updateMFr;
assign MFrwe = GO_C && EX_enc;
assign MFswe = GO_C && EX_enc;
`ifdef FD_DFT
REG16L mfswe(DSPCLK, CLKMFsenb, MFswe, MACin[31:16], MFs[15:0], SCAN_TEST);
REG16L mfrwe(DSPCLK, CLKMFrenb, MFrwe, MACin[31:16], MFr[15:0], SCAN_TEST);
`else
REG16L mfswe(DSPCLK, CLKMFsenb, MFswe, MACin[31:16], MFs[15:0]);
REG16L mfrwe(DSPCLK, CLKMFrenb, MFrwe, MACin[31:16], MFr[15:0]);
`endif
wire [15:0] MR0r, MR0s, MR1r, MR1s;
wire [7:0] MR2r, MR2s;
wire [15:0] MR0rin, MR0sin, MR1rin, MR1sin;
wire [7:0] MR2rin, MR2sin;
assign MR0rin[15:0] = satMR_Eg & !SHADOW & GO_C ? (MR2r[7] ? 16'h0000 : 16'hffff) :
MTMR0_Eg & !SHADOW & GO_C ? Xin[15:0] :
MR0r[15:0];
assign MR0sin[15:0] = satMR_Eg & SHADOW & GO_C ? (MR2s[7] ? 16'h0000 : 16'hffff) :
MTMR0_Eg & SHADOW & GO_C ? Xin[15:0] :
MR0s[15:0];
assign MR1rin[15:0] = satMR_Eg & !SHADOW & GO_C ? {MR2r[7], {MR2r[7] ? 15'h0000 : 15'h7fff}} :
MTMR1_Eg & !SHADOW & GO_C ? Xin[15:0] :
MR1r[15:0];
assign MR1sin[15:0] = satMR_Eg & SHADOW & GO_C ? {MR2s[7], {MR2s[7] ? 15'h0000 : 15'h7fff}} :
MTMR1_Eg & SHADOW & GO_C ? Xin[15:0] :
MR1s[15:0];
assign MR2rin[7:0] = satMR_Eg & !SHADOW & GO_C ? (MR2r[7] ? 8'hff : 8'h00) :
MTMR1_Eg & !SHADOW & GO_C ? {8{Xin[15]}} :
MTMR2_Eg & !SHADOW & GO_C ? Xin[7:0] :
MR2r[7:0];
assign MR2sin[7:0] = satMR_Eg & SHADOW & GO_C ? (MR2s[7] ? 8'hff : 8'h00) :
MTMR1_Eg & SHADOW & GO_C ? {8{Xin[15]}} :
MTMR2_Eg & SHADOW & GO_C ? Xin[7:0] :
MR2s[7:0];
wire [8:0] MRovf;
wire CLKovfenb;
wire MRovfwe;
assign CLKovfenb = !MACop_E;
assign MRovfwe = GO_C && EX_enc;
`ifdef FD_DFT
REG9L mrovfwe(DSPCLK, CLKovfenb, MRovfwe, MACin[39:31], MRovf[8:0], SCAN_TEST);
`else
REG9L mrovfwe(DSPCLK, CLKovfenb, MRovfwe, MACin[39:31], MRovf[8:0]);
`endif
wire updateMR0r, updateMR1r, updateMR2r;
wire updateMR0s, updateMR1s, updateMR2s;
wire CLKmr0renb, CLKmr0senb, CLKmr1renb;
wire CLKmr1senb, CLKmr2renb, CLKmr2senb;
wire MR0r_we, MR1r_we, MR2r_we;
wire MR0s_we, MR1s_we, MR2s_we;
assign updateMR0r = !SHADOW && (satMR_Eg || MTMR0_Eg);
assign updateMR1r = !SHADOW && (satMR_Eg || MTMR1_Eg);
assign updateMR2r = !SHADOW && (satMR_Eg || MTMR1_Eg || MTMR2_Eg);
assign updateMR0s = SHADOW && (satMR_Eg || MTMR0_Eg);
assign updateMR1s = SHADOW && (satMR_Eg || MTMR1_Eg);
assign updateMR2s = SHADOW && (satMR_Eg || MTMR1_Eg || MTMR2_Eg);
assign CLKmr0renb = !(updateMRr || updateMR0r);
assign CLKmr1renb = !(updateMRr || updateMR1r);
assign CLKmr2renb = !(updateMRr || updateMR2r);
assign CLKmr0senb = !(updateMRs || updateMR0s);
assign CLKmr1senb = !(updateMRs || updateMR1s);
assign CLKmr2senb = !(updateMRs || updateMR2s);
assign MR0r_we = updateMRr && GO_C && EX_enc;
assign MR1r_we = updateMRr && GO_C && EX_enc;
assign MR2r_we = updateMRr && GO_C && EX_enc;
assign MR0s_we = updateMRs && GO_C && EX_enc;
assign MR1s_we = updateMRs && GO_C && EX_enc;
assign MR2s_we = updateMRs && GO_C && EX_enc;
`ifdef FD_DFT
REG2D16L mr0rwe(DSPCLK, CLKmr0renb, MR0r_we, MACin[15:0], MR0rin[15:0], MR0r[15:0], SCAN_TEST);
REG2D16L mr0swe(DSPCLK, CLKmr0senb, MR0s_we, MACin[15:0], MR0sin[15:0], MR0s[15:0], SCAN_TEST);
REG2D16L mr1rwe(DSPCLK, CLKmr1renb, MR1r_we, MACin[31:16], MR1rin[15:0], MR1r[15:0], SCAN_TEST);
REG2D16L mr1swe(DSPCLK, CLKmr1senb, MR1s_we, MACin[31:16], MR1sin[15:0], MR1s[15:0], SCAN_TEST);
REG2D8L mr2rwe(DSPCLK, CLKmr2renb, MR2r_we, MACin[39:32], MR2rin[7:0], MR2r[7:0], SCAN_TEST);
REG2D8L mr2swe(DSPCLK, CLKmr2senb, MR2s_we, MACin[39:32], MR2sin[7:0], MR2s[7:0], SCAN_TEST);
`else
REG2D16L mr0rwe(DSPCLK, CLKmr0renb, MR0r_we, MACin[15:0], MR0rin[15:0], MR0r[15:0]);
REG2D16L mr0swe(DSPCLK, CLKmr0senb, MR0s_we, MACin[15:0], MR0sin[15:0], MR0s[15:0]);
REG2D16L mr1rwe(DSPCLK, CLKmr1renb, MR1r_we, MACin[31:16], MR1rin[15:0], MR1r[15:0]);
REG2D16L mr1swe(DSPCLK, CLKmr1senb, MR1s_we, MACin[31:16], MR1sin[15:0], MR1s[15:0]);
REG2D8L mr2rwe(DSPCLK, CLKmr2renb, MR2r_we, MACin[39:32], MR2rin[7:0], MR2r[7:0]);
REG2D8L mr2swe(DSPCLK, CLKmr2senb, MR2s_we, MACin[39:32], MR2sin[7:0], MR2s[7:0]);
`endif
wire [15:0] MR1, MR0;
wire [7:0] MR2;
assign MR2[7:0] = SHADOW ? MR2s[7:0] : MR2r[7:0];
assign MR1[15:0] = SHADOW ? MR1s[15:0] : MR1r[15:0];
assign MR0[15:0] = SHADOW ? MR0s[15:0] : MR0r[15:0];
/*--------------------------------------*/
/*--------------------------------------*/
wire [7:0] MR2_D;
wire [15:0] R_mac_in_D;
assign R_mac_in_D[15:0] = {16{Rstore_MR0_D & BYPASSR_D & ~GO_MAC & satMR_Eg}} & {16{~MR2[7]}}
| {16{Rstore_MR0_D & ~BYPASSR_D & ~GO_MAC}} & MR0[15:0]
| {16{Rstore_MR0_E & GO_MAC}} & MR0[15:0]
| {16{Rstore_MR1_D & BYPASSR_D & ~GO_MAC & satMR_Eg}} & {MR2[7], {15{~MR2[7]}}}
| {16{Rstore_MR1_D & ~BYPASSR_D & ~GO_MAC}} & MR1[15:0]
| {16{Rstore_MR1_E & GO_MAC}} & MR1[15:0]
| {16{Rstore_MR2_D & BYPASSR_D & ~GO_MAC & satMR_Eg}} & {16{MR2[7]}}
| {16{Rstore_MR2_D & ~BYPASSR_D & ~GO_MAC}} & {{8{MR2[7]}}, MR2[7:0]}
| {16{Rstore_MR2_E & GO_MAC}} & {{8{MR2[7]}}, MR2[7:0]};
`ifdef FD_RTL_SIM
assign R_mac_D[15:0] = {16{BYPASSR_D & ~GO_MAC & accPM_E & ((Rstore_MR0_D & MTMR0_Eg)
| (Rstore_MR1_D & MTMR1_Eg))}} & {PMDin[15:0]}
| {16{BYPASSR_D & ~GO_MAC & ~accPM_E & ((Rstore_MR0_D & MTMR0_Eg)
| (Rstore_MR1_D & MTMR1_Eg))}} & {DMDin[15:0]}
| {16{Rstore_MR2_D & BYPASSR_D & ~GO_MAC & MTMR1_Eg}} & {16{Xin[15]}}
| {16{Rstore_MR2_D & BYPASSR_D & ~GO_MAC & MTMR2_Eg & accPM_E}} & {{8{PMDin[7]}}, PMDin[7:0]}
| {16{Rstore_MR2_D & BYPASSR_D & ~GO_MAC & MTMR2_Eg & ~accPM_E}} & {{8{DMDin[7]}}, DMDin[7:0]}
| R_mac_in_D[15:0];
`else
wire [4:0] SEL_mac_D;
reg s0, s1, s2;
assign SEL_mac_D[4] = BYPASSR_D & ~GO_MAC & accPM_E & ((Rstore_MR0_D & MTMR0_Eg) | (Rstore_MR1_D & MTMR1_Eg));
assign SEL_mac_D[3] = BYPASSR_D & ~GO_MAC & ~accPM_E & ((Rstore_MR0_D & MTMR0_Eg) | (Rstore_MR1_D & MTMR1_Eg));
assign SEL_mac_D[2] = Rstore_MR2_D & BYPASSR_D & ~GO_MAC & MTMR1_Eg;
assign SEL_mac_D[1] = Rstore_MR2_D & BYPASSR_D & ~GO_MAC & MTMR2_Eg & accPM_E;
assign SEL_mac_D[0] = Rstore_MR2_D & BYPASSR_D & ~GO_MAC & MTMR2_Eg & ~accPM_E;
always @(SEL_mac_D)
begin
case (SEL_mac_D)
5'b10000 : {s2, s1, s0} = 3'b000;
5'b01000 : {s2, s1, s0} = 3'b001;
5'b00100 : {s2, s1, s0} = 3'b010;
5'b00010 : {s2, s1, s0} = 3'b011;
5'b00001 : {s2, s1, s0} = 3'b100;
5'b00000 : {s2, s1, s0} = 3'b101;
endcase
end
GTECH_MUX8 mac_d15(.D0(PMDin[15]), .D1(DMDin[15]), .D2(Xin[15]), .D3(PMDin[7]), .D4(DMDin[7]),
.D5(R_mac_in_D[15]), .D6(1'b0), .D7(1'b0),
.C(s2), .B(s1), .A(s0), .Z(R_mac_D[15]));
GTECH_MUX8 mac_d14(.D0(PMDin[14]), .D1(DMDin[14]), .D2(Xin[15]), .D3(PMDin[7]), .D4(DMDin[7]),
.D5(R_mac_in_D[14]), .D6(1'b0), .D7(1'b0),
.C(s2), .B(s1), .A(s0), .Z(R_mac_D[14]));
GTECH_MUX8 mac_d13(.D0(PMDin[13]), .D1(DMDin[13]), .D2(Xin[15]), .D3(PMDin[7]), .D4(DMDin[7]),
.D5(R_mac_in_D[13]), .D6(1'b0), .D7(1'b0),
.C(s2), .B(s1), .A(s0), .Z(R_mac_D[13]));
GTECH_MUX8 mac_d12(.D0(PMDin[12]), .D1(DMDin[12]), .D2(Xin[15]), .D3(PMDin[7]), .D4(DMDin[7]),
.D5(R_mac_in_D[12]), .D6(1'b0), .D7(1'b0),
.C(s2), .B(s1), .A(s0), .Z(R_mac_D[12]));
GTECH_MUX8 mac_d11(.D0(PMDin[11]), .D1(DMDin[11]), .D2(Xin[15]), .D3(PMDin[7]), .D4(DMDin[7]),
.D5(R_mac_in_D[11]), .D6(1'b0), .D7(1'b0),
.C(s2), .B(s1), .A(s0), .Z(R_mac_D[11]));
GTECH_MUX8 mac_d10(.D0(PMDin[10]), .D1(DMDin[10]), .D2(Xin[15]), .D3(PMDin[7]), .D4(DMDin[7]),
.D5(R_mac_in_D[10]), .D6(1'b0), .D7(1'b0),
.C(s2), .B(s1), .A(s0), .Z(R_mac_D[10]));
GTECH_MUX8 mac_d9(.D0(PMDin[9]), .D1(DMDin[9]), .D2(Xin[15]), .D3(PMDin[7]), .D4(DMDin[7]),
.D5(R_mac_in_D[9]), .D6(1'b0), .D7(1'b0),
.C(s2), .B(s1), .A(s0), .Z(R_mac_D[9]));
GTECH_MUX8 mac_d8(.D0(PMDin[8]), .D1(DMDin[8]), .D2(Xin[15]), .D3(PMDin[7]), .D4(DMDin[7]),
.D5(R_mac_in_D[8]), .D6(1'b0), .D7(1'b0),
.C(s2), .B(s1), .A(s0), .Z(R_mac_D[8]));
GTECH_MUX8 mac_d7(.D0(PMDin[7]), .D1(DMDin[7]), .D2(Xin[15]), .D3(PMDin[7]), .D4(DMDin[7]),
.D5(R_mac_in_D[7]), .D6(1'b0), .D7(1'b0),
.C(s2), .B(s1), .A(s0), .Z(R_mac_D[7]));
GTECH_MUX8 mac_d6(.D0(PMDin[6]), .D1(DMDin[6]), .D2(Xin[15]), .D3(PMDin[6]), .D4(DMDin[6]),
.D5(R_mac_in_D[6]), .D6(1'b0), .D7(1'b0),
.C(s2), .B(s1), .A(s0), .Z(R_mac_D[6]));
GTECH_MUX8 mac_d5(.D0(PMDin[5]), .D1(DMDin[5]), .D2(Xin[15]), .D3(PMDin[5]), .D4(DMDin[5]),
.D5(R_mac_in_D[5]), .D6(1'b0), .D7(1'b0),
.C(s2), .B(s1), .A(s0), .Z(R_mac_D[5]));
GTECH_MUX8 mac_d4(.D0(PMDin[4]), .D1(DMDin[4]), .D2(Xin[15]), .D3(PMDin[4]), .D4(DMDin[4]),
.D5(R_mac_in_D[4]), .D6(1'b0), .D7(1'b0),
.C(s2), .B(s1), .A(s0), .Z(R_mac_D[4]));
GTECH_MUX8 mac_d3(.D0(PMDin[3]), .D1(DMDin[3]), .D2(Xin[15]), .D3(PMDin[3]), .D4(DMDin[3]),
.D5(R_mac_in_D[3]), .D6(1'b0), .D7(1'b0),
.C(s2), .B(s1), .A(s0), .Z(R_mac_D[3]));
GTECH_MUX8 mac_d2(.D0(PMDin[2]), .D1(DMDin[2]), .D2(Xin[15]), .D3(PMDin[2]), .D4(DMDin[2]),
.D5(R_mac_in_D[2]), .D6(1'b0), .D7(1'b0),
.C(s2), .B(s1), .A(s0), .Z(R_mac_D[2]));
GTECH_MUX8 mac_d1(.D0(PMDin[1]), .D1(DMDin[1]), .D2(Xin[15]), .D3(PMDin[1]), .D4(DMDin[1]),
.D5(R_mac_in_D[1]), .D6(1'b0), .D7(1'b0),
.C(s2), .B(s1), .A(s0), .Z(R_mac_D[1]));
GTECH_MUX8 mac_d0(.D0(PMDin[0]), .D1(DMDin[0]), .D2(Xin[15]), .D3(PMDin[0]), .D4(DMDin[0]),
.D5(R_mac_in_D[0]), .D6(1'b0), .D7(1'b0),
.C(s2), .B(s1), .A(s0), .Z(R_mac_D[0]));
`endif
assign R_mac_E[15:0] = {16{Rstore_MR0_E}} & MR0[15:0]
| {16{Rstore_MR1_E}} & MR1[15:0]
| {16{Rstore_MR2_E}} & {{8{MR2[7]}}, MR2[7:0]} ;
/*--------------------------------------*/
/*--------------------------------------*/
wire [15:0] MACout;
assign MACout[15:0] = {16{MFMX0_E}} & MX0[15:0]
| {16{MFMX1_E}} & MX1[15:0]
| {16{MFMY0_E}} & MY0[15:0]
| {16{MFMY1_E}} & MY1[15:0]
| {16{MFMR0_E}} & MR0[15:0]
| {16{MFMR1_E}} & MR1[15:0]
| {16{MFMR2_E}} & {{8{MR2[7]}}, MR2[7:0]};
assign DMDmac[15:0] = {16{MFMAC_E}} & MACout[15:0];
assign PMDmac[15:0] = {16{pMFMAC_E}} & MACout[15:0];
endmodule
|
/*--------------------------------------------------------------*/
/*--------------------------------------------------------------*/
/*--------------------------------------------------------------*/
/*--------------------------------------------------------------*/
`define del 1
module ES_ARRAY (/* IN */
SINdi, SR1, SR0, SF_E, IRE,
SE, XIdi, NORM, SIMM_E, SHTop_E,
SO_H, SO_L);
/*****************************************************************/
/*****************************************************************/
input [15:0] SINdi;
input [15:0] SR1, SR0;
input [3:0] SF_E;
input [7:0] IRE;
input [7:0] SE;
input XIdi;
input NORM;
input SIMM_E;
input SHTop_E;
/*****************************************************************/
/*****************************************************************/
output [15:0] SO_H, SO_L;
/*****************************************************************/
/*****************************************************************/
wire [7:0] N_SE;
wire [7:0] SAMdi;
wire [7:0] SAM;
assign #`del N_SE[7:0] = ~SE[7:0] + 1;
assign #`del SAMdi[7:0] = NORM ? N_SE[7:0] :
SIMM_E ? IRE[7:0] : SE[7:0] ;
assign #`del SAM[7:0] = SAMdi[7:0] & {8{SHTop_E && (!(SF_E[3:2] == 2'b11))}};
/*****************************************************************/
/*****************************************************************/
wire LO;
wire XI;
wire ARYop_E;
wire [15:0] SIN;
assign ARYop_E = SHTop_E && (!(SF_E[3:2] == 2'b11));
assign LO = SF_E[1] && ARYop_E;
assign XI = XIdi && ARYop_E;
assign SIN[15:0] = SINdi[15:0] & {16{ARYop_E}};
reg [31:0] SO;
always @(SAM or SIN or XI or LO)
begin
casex ({LO, SAM})
/*****************************************************************/
/*****************************************************************/
9'b0_01xxxxxx : SO[31:0] = 32'b0;
9'b0_001xxxxx : SO[31:0] = 32'b0;
9'b0_0001xxxx : SO[31:0] = 32'b0;
9'b0_00001111 : SO[31:0] = {SIN[0], 31'b0};
9'b0_00001110 : SO[31:0] = {SIN[1:0], 30'b0};
9'b0_00001101 : SO[31:0] = {SIN[2:0], 29'b0};
9'b0_00001100 : SO[31:0] = {SIN[3:0], 28'b0};
9'b0_00001011 : SO[31:0] = {SIN[4:0], 27'b0};
9'b0_00001010 : SO[31:0] = {SIN[5:0], 26'b0};
9'b0_00001001 : SO[31:0] = {SIN[6:0], 25'b0};
9'b0_00001000 : SO[31:0] = {SIN[7:0], 24'b0};
9'b0_00000111 : SO[31:0] = {SIN[8:0], 23'b0};
9'b0_00000110 : SO[31:0] = {SIN[9:0], 22'b0};
9'b0_00000101 : SO[31:0] = {SIN[10:0], 21'b0};
9'b0_00000100 : SO[31:0] = {SIN[11:0], 20'b0};
9'b0_00000011 : SO[31:0] = {SIN[12:0], 19'b0};
9'b0_00000010 : SO[31:0] = {SIN[13:0], 18'b0};
9'b0_00000001 : SO[31:0] = {SIN[14:0], 17'b0};
9'b0_00000000 : SO[31:0] = {SIN[15:0], 16'b0};
9'b0_11111111 : SO[31:0] = {XI, SIN[15:0], 15'b0};
9'b0_11111110 : SO[31:0] = {{2{XI}}, SIN[15:0], 14'b0};
9'b0_11111101 : SO[31:0] = {{3{XI}}, SIN[15:0], 13'b0};
9'b0_11111100 : SO[31:0] = {{4{XI}}, SIN[15:0], 12'b0};
9'b0_11111011 : SO[31:0] = {{5{XI}}, SIN[15:0], 11'b0};
9'b0_11111010 : SO[31:0] = {{6{XI}}, SIN[15:0], 10'b0};
9'b0_11111001 : SO[31:0] = {{7{XI}}, SIN[15:0], 9'b0};
9'b0_11111000 : SO[31:0] = {{8{XI}}, SIN[15:0], 8'b0};
9'b0_11110111 : SO[31:0] = {{9{XI}}, SIN[15:0], 7'b0};
9'b0_11110110 : SO[31:0] = {{10{XI}}, SIN[15:0], 6'b0};
9'b0_11110101 : SO[31:0] = {{11{XI}}, SIN[15:0], 5'b0};
9'b0_11110100 : SO[31:0] = {{12{XI}}, SIN[15:0], 4'b0};
9'b0_11110011 : SO[31:0] = {{13{XI}}, SIN[15:0], 3'b0};
9'b0_11110010 : SO[31:0] = {{14{XI}}, SIN[15:0], 2'b0};
9'b0_11110001 : SO[31:0] = {{15{XI}}, SIN[15:0], 1'b0};
9'b0_11110000 : SO[31:0] = {{16{XI}}, SIN[15:0]};
9'b0_11101111 : SO[31:0] = {{17{XI}}, SIN[15:1]};
9'b0_11101110 : SO[31:0] = {{18{XI}}, SIN[15:2]};
9'b0_11101101 : SO[31:0] = {{19{XI}}, SIN[15:3]};
9'b0_11101100 : SO[31:0] = {{20{XI}}, SIN[15:4]};
9'b0_11101011 : SO[31:0] = {{21{XI}}, SIN[15:5]};
9'b0_11101010 : SO[31:0] = {{22{XI}}, SIN[15:6]};
9'b0_11101001 : SO[31:0] = {{23{XI}}, SIN[15:7]};
9'b0_11101000 : SO[31:0] = {{24{XI}}, SIN[15:8]};
9'b0_11100111 : SO[31:0] = {{25{XI}}, SIN[15:9]};
9'b0_11100110 : SO[31:0] = {{26{XI}}, SIN[15:10]};
9'b0_11100101 : SO[31:0] = {{27{XI}}, SIN[15:11]};
9'b0_11100100 : SO[31:0] = {{28{XI}}, SIN[15:12]};
9'b0_11100011 : SO[31:0] = {{29{XI}}, SIN[15:13]};
9'b0_11100010 : SO[31:0] = {{30{XI}}, SIN[15:14]};
9'b0_11100001 : SO[31:0] = {{31{XI}}, SIN[15]};
9'b0_11100000 : SO[31:0] = {32{XI}};
9'b0_110xxxxx : SO[31:0] = {32{XI}};
9'b0_10xxxxxx : SO[31:0] = {32{XI}};
/****************************************************************/
/****************************************************************/
9'b1_01xxxxxx : SO[31:0] = 32'b0;
9'b1_001xxxxx : SO[31:0] = 32'b0;
9'b1_00011111 : SO[31:0] = {SIN[0], 31'b0};
9'b1_00011110 : SO[31:0] = {SIN[1:0], 30'b0};
9'b1_00011101 : SO[31:0] = {SIN[2:0], 29'b0};
9'b1_00011100 : SO[31:0] = {SIN[3:0], 28'b0};
9'b1_00011011 : SO[31:0] = {SIN[4:0], 27'b0};
9'b1_00011010 : SO[31:0] = {SIN[5:0], 26'b0};
9'b1_00011001 : SO[31:0] = {SIN[6:0], 25'b0};
9'b1_00011000 : SO[31:0] = {SIN[7:0], 24'b0};
9'b1_00010111 : SO[31:0] = {SIN[8:0], 23'b0};
9'b1_00010110 : SO[31:0] = {SIN[9:0], 22'b0};
9'b1_00010101 : SO[31:0] = {SIN[10:0], 21'b0};
9'b1_00010100 : SO[31:0] = {SIN[11:0], 20'b0};
9'b1_00010011 : SO[31:0] = {SIN[12:0], 19'b0};
9'b1_00010010 : SO[31:0] = {SIN[13:0], 18'b0};
9'b1_00010001 : SO[31:0] = {SIN[14:0], 17'b0};
9'b1_00010000 : SO[31:0] = {SIN[15:0], 16'b0};
9'b1_00001111 : SO[31:0] = {XI, SIN[15:0], 15'b0};
9'b1_00001110 : SO[31:0] = {{2{XI}}, SIN[15:0], 14'b0};
9'b1_00001101 : SO[31:0] = {{3{XI}}, SIN[15:0], 13'b0};
9'b1_00001100 : SO[31:0] = {{4{XI}}, SIN[15:0], 12'b0};
9'b1_00001011 : SO[31:0] = {{5{XI}}, SIN[15:0], 11'b0};
9'b1_00001010 : SO[31:0] = {{6{XI}}, SIN[15:0], 10'b0};
9'b1_00001001 : SO[31:0] = {{7{XI}}, SIN[15:0], 9'b0};
9'b1_00001000 : SO[31:0] = {{8{XI}}, SIN[15:0], 8'b0};
9'b1_00000111 : SO[31:0] = {{9{XI}}, SIN[15:0], 7'b0};
9'b1_00000110 : SO[31:0] = {{10{XI}}, SIN[15:0], 6'b0};
9'b1_00000101 : SO[31:0] = {{11{XI}}, SIN[15:0], 5'b0};
9'b1_00000100 : SO[31:0] = {{12{XI}}, SIN[15:0], 4'b0};
9'b1_00000011 : SO[31:0] = {{13{XI}}, SIN[15:0], 3'b0};
9'b1_00000010 : SO[31:0] = {{14{XI}}, SIN[15:0], 2'b0};
9'b1_00000001 : SO[31:0] = {{15{XI}}, SIN[15:0], 1'b0};
9'b1_00000000 : SO[31:0] = {{16{XI}}, SIN[15:0]};
9'b1_11111111 : SO[31:0] = {{17{XI}}, SIN[15:1]};
9'b1_11111110 : SO[31:0] = {{18{XI}}, SIN[15:2]};
9'b1_11111101 : SO[31:0] = {{19{XI}}, SIN[15:3]};
9'b1_11111100 : SO[31:0] = {{20{XI}}, SIN[15:4]};
9'b1_11111011 : SO[31:0] = {{21{XI}}, SIN[15:5]};
9'b1_11111010 : SO[31:0] = {{22{XI}}, SIN[15:6]};
9'b1_11111001 : SO[31:0] = {{23{XI}}, SIN[15:7]};
9'b1_11111000 : SO[31:0] = {{24{XI}}, SIN[15:8]};
9'b1_11110111 : SO[31:0] = {{25{XI}}, SIN[15:9]};
9'b1_11110110 : {SO[20:0],SO[31:21]} = {{26{XI}}, SIN[15:10]};
9'b1_11110101 : SO[31:0] = {{27{XI}}, SIN[15:11]};
9'b1_11110100 : SO[31:0] = {{28{XI}}, SIN[15:12]};
9'b1_11110011 : SO[31:0] = {{29{XI}}, SIN[15:13]};
9'b1_11110010 : SO[31:0] = {{30{XI}}, SIN[15:14]};
9'b1_11110001 : SO[31:0] = {{31{XI}}, SIN[15]};
9'b1_11110000 : SO[31:0] = {32{XI}};
9'b1_1110xxxx : SO[31:0] = {32{XI}};
9'b1_110xxxxx : SO[31:0] = {32{XI}};
9'b1_10xxxxxx : SO[31:0] = {32{XI}};
endcase
end
/**************************************************/
/**************************************************/
wire ORop;
wire [31:0] FB_SR;
assign ORop = SF_E[0];
assign #`del FB_SR[31:0] = {32{ORop}} & {SR1[15:0], SR0[15:0]};
assign #`del SO_H[15:0] = FB_SR[31:16] | SO[31:16];
assign #`del SO_L[15:0] = FB_SR[15:0] | SO[15:0] ;
endmodule
|
/*--------------------------------------------------------------*/
/*--------------------------------------------------------------*/
/*--------------------------------------------------------------*/
/*--------------------------------------------------------------*/
`define del 1
module ES_DEC(/* IN */
GO_C, EX_en, EX_enc, EXPGTSB, SEf1,
SHADOW, SF_E, MTSI_E, MTSB_E, MTSE_E, updSR0_Eg,
updSR1_Eg, SIN15, AC, AV, SHTop_E, MTSR0_E, MTSR1_E, updSR_E,
updateSIr, updateSIs, updateSBr, updateSBs, updateSEr,
updateSEs, updateSR0r, updateSR0s, updateSR1r, updateSR1s,
updateSS, DBE, HIX, LO, XI, NORM);
/*--------------------------------------*/
/*--------------------------------------*/
input GO_C, EX_en , EX_enc;
input EXPGTSB, SEf1, SHADOW;
input [3:0] SF_E;
input MTSI_E, MTSB_E, MTSE_E, updSR0_Eg;
input updSR1_Eg, SIN15, AC, AV;
input SHTop_E, MTSR0_E, MTSR1_E;
input updSR_E;
/*--------------------------------------*/
/*--------------------------------------*/
output updateSIr, updateSIs, updateSBr, updateSBs;
output updateSEr, updateSEs, updateSR0r, updateSR0s;
output updateSR1r, updateSR1s, updateSS;
output DBE, HIX, LO, XI, NORM;
/*------------------------------------------------------*/
/*------------------------------------------------------*/
wire updateSHT, updateSB, updateSE;
assign updateSHT = SHTop_E & EX_enc;
assign #`del updateSB = updateSHT & DBE & EXPGTSB;
assign #`del updateSE = updateSHT & ((SF_E[3:1] == 3'b110)
| ((SF_E[3:0] == 4'b1110) & SEf1));
assign #`del updateSS = updateSHT && (SF_E[3:1] == 3'b110);
/*------------------------------------------------------*/
/*------------------------------------------------------*/
wire updateSIr, updateSIs, updateSBr, updateSBs;
wire updateSEr, updateSEs, updateSR0r, updateSR0s;
wire updateSR1r, updateSR1s;
assign updateSIr = !SHADOW && MTSI_E && EX_en;
assign updateSIs = SHADOW && MTSI_E && EX_en;
assign updateSBr = !SHADOW && (MTSB_E && EX_en || updateSB) && GO_C;
assign updateSBs = SHADOW && (MTSB_E && EX_en || updateSB) && GO_C;
assign updateSEr = !SHADOW && (MTSE_E || (SHTop_E &&
((SF_E[3:1] == 3'b110) || ((SF_E[3:0] == 4'b1110) && SEf1))));
assign updateSEs = SHADOW && (MTSE_E || (SHTop_E &&
((SF_E[3:1] == 3'b110) || ((SF_E[3:0] == 4'b1110) && SEf1))));
assign updateSR0r = !SHADOW && (MTSR0_E || updSR_E);
assign updateSR0s = SHADOW && (MTSR0_E || updSR_E);
assign updateSR1r = !SHADOW && (MTSR1_E || updSR_E);
assign updateSR1s = SHADOW && (MTSR1_E || updSR_E);
/*--------------------------------------*/
/*--------------------------------------*/
assign HIX = (SF_E[1:0] == 2'b01);
assign LO = (SF_E[1:0] == 2'b10);
/*--------------------------------------*/
/*--------------------------------------*/
wire ASHIFT;
assign #`del DBE = (SF_E[3:0] == 4'hf) ;
assign #`del NORM = (SF_E[3:2] == 2'b10);
assign #`del ASHIFT = (SF_E[3:2] == 2'b01);
/****************************************/
/****************************************/
assign XI = (SIN15 && ASHIFT) ||
(AC && AV && NORM && (~SF_E[1]));
endmodule
|
/*--------------------------------------------------------------*/
/*--------------------------------------------------------------*/
/*--------------------------------------------------------------*/
/*--------------------------------------------------------------*/
`define del 1
module ES_EXP (/* IN */
SINdi, SB, DBE, HIX, LO,
SS, AV, SHTop_E, SF_E,
EXP, SSin, EXPGTSB);
/*----------------------------------------------*/
/*----------------------------------------------*/
input [15:0] SINdi;
input [4:0] SB;
input DBE;
input HIX, LO;
input SS, AV;
input SHTop_E;
input [3:2] SF_E;
/************************************************/
/************************************************/
output [5:0] EXP;
output SSin;
output EXPGTSB;
/************************************************/
/************************************************/
wire egts;
assign egts = (EXP[3:0] > SB[3:0]);
assign #`del EXPGTSB = DBE && (((~EXP[4]) && SB[4]) ||
(( EXP[4] == SB[4] ) && egts));
/************************************************/
/************************************************/
wire LOin;
wire CASEA, CASEB, CASEC;
wire [13:0] TMP;
wire [15:0] SIN;
assign SIN[15:0] = SINdi[15:0] & {16{SHTop_E && (SF_E[3:2] == 2'b11)}};
assign SSin = ((AV && HIX) != SINdi[15]);
assign LOin = LO && SHTop_E && (SF_E[3:2] == 2'b11);
assign CASEA = AV && HIX && SHTop_E && (SF_E[3:2] == 2'b11);
assign CASEB = (SS != SIN[15]) && LOin;
assign CASEC = (SIN[15] != SIN[14]);
assign TMP[13:0] = SIN[15] ? (~SIN[13:0]) : SIN[13:0];
reg [5:0] EXPin;
wire [5:0] EXP;
assign #`del EXP[5:0] = CASEA ? 6'b000001 :
CASEB ? 6'b110001 : EXPin[5:0];
always @(CASEA or CASEB or CASEC or TMP or LOin)
begin
casex ({LOin, CASEC, TMP[13:0]})
/********************************************************/
/********************************************************/
16'b11xxxxxxxxxxxxxx : EXPin[5:0] = 6'b110000;
16'b01xxxxxxxxxxxxxx : EXPin[5:0] = 6'b000000;
16'b101xxxxxxxxxxxxx : EXPin[5:0] = 6'b101111;
16'b1001xxxxxxxxxxxx : EXPin[5:0] = 6'b101110;
16'b10001xxxxxxxxxxx : EXPin[5:0] = 6'b101101;
16'b100001xxxxxxxxxx : EXPin[5:0] = 6'b101100;
16'b1000001xxxxxxxxx : EXPin[5:0] = 6'b101011;
16'b10000001xxxxxxxx : EXPin[5:0] = 6'b101010;
16'b100000001xxxxxxx : EXPin[5:0] = 6'b101001;
16'b1000000001xxxxxx : EXPin[5:0] = 6'b101000;
16'b10000000001xxxxx : EXPin[5:0] = 6'b100111;
16'b100000000001xxxx : EXPin[5:0] = 6'b100110;
16'b1000000000001xxx : EXPin[5:0] = 6'b100101;
16'b10000000000001xx : EXPin[5:0] = 6'b100100;
16'b100000000000001x : EXPin[5:0] = 6'b100011;
16'b1000000000000001 : EXPin[5:0] = 6'b100010;
16'b1000000000000000 : EXPin[5:0] = 6'b100001;
16'b001xxxxxxxxxxxxx : EXPin[5:0] = 6'b111111;
16'b0001xxxxxxxxxxxx : EXPin[5:0] = 6'b111110;
16'b00001xxxxxxxxxxx : EXPin[5:0] = 6'b111101;
16'b000001xxxxxxxxxx : EXPin[5:0] = 6'b111100;
16'b0000001xxxxxxxxx : EXPin[5:0] = 6'b111011;
16'b00000001xxxxxxxx : EXPin[5:0] = 6'b111010;
16'b000000001xxxxxxx : EXPin[5:0] = 6'b111001;
16'b0000000001xxxxxx : EXPin[5:0] = 6'b111000;
16'b00000000001xxxxx : EXPin[5:0] = 6'b110111;
16'b000000000001xxxx : EXPin[5:0] = 6'b110110;
16'b0000000000001xxx : EXPin[5:0] = 6'b110101;
16'b00000000000001xx : EXPin[5:0] = 6'b110100;
16'b000000000000001x : EXPin[5:0] = 6'b110011;
16'b0000000000000001 : EXPin[5:0] = 6'b110010;
16'b0000000000000000 : EXPin[5:0] = 6'b110001;
endcase
end
endmodule
|
/*--------------------------------------------------------------*/
/*--------------------------------------------------------------*/
/*--------------------------------------------------------------*/
/*--------------------------------------------------------------*/
`define del 1
module ES_REG(/* IN */
DSPCLK, SHADOW, EXP, Xop_D, Xop_E,
SO_L, SO_H, MTSB_E, MTSE_E,
MTSR1_E, MTSR0_E, R_in_E, updateSIr, updateSIs,
updateSBr, updateSBs, updateSEr, updateSEs,
updateSR1r, updateSR1s, updateSR0r, updateSR0s,
MFSI_E, MFSB_E, MFSE_E, MFSR1_E, MFSR0_E, BYPASSR_D, MFSHT_E,
pMFSHT_E, accPM_E, GO_MAC, EX_enc, GO_C,
`ifdef FD_DFT
SCAN_TEST,
`endif
SEf1, SIN, SE, SB, SR0, SR1,
R_sht_E, R_sht_D,
DMDin, DMDsht, PMDin, PMDsht);
/*----------------------------------------------*/
/*----------------------------------------------*/
input DSPCLK;
input SHADOW, MTSB_E, MTSE_E, MTSR0_E, MTSR1_E;
input [5:0] EXP;
input [2:0] Xop_E, Xop_D;
input [15:0] SO_L, SO_H;
input updateSIr, updateSBr, updateSEr, updateSR1r, updateSR0r;
input updateSIs, updateSBs, updateSEs, updateSR1s, updateSR0s;
input MFSI_E, MFSB_E, MFSE_E, MFSR1_E, MFSR0_E, BYPASSR_D;
input [15:0] R_in_E;
input MFSHT_E, pMFSHT_E, accPM_E;
input GO_MAC, EX_enc, GO_C;
`ifdef FD_DFT
input SCAN_TEST;
`endif
/*----------------------------------------------*/
/*----------------------------------------------*/
output SEf1;
output [15:0] SIN;
output [7:0] SE;
output [4:0] SB;
output [15:0] SR0, SR1;
output [15:0] R_sht_E, R_sht_D;
/*----------------------------------------------*/
/*----------------------------------------------*/
input [15:0] DMDin;
output [15:0] DMDsht;
input [15:0] PMDin;
output [15:0] PMDsht;
wire [15:0] DMDin1;
DMDbuf DMDIN_BUF(DMDin[15:0], DMDin1[15:0]);
/*----------------------------------------------*/
/*----------------------------------------------*/
wire [15:0] SSin;
assign SSin[15:0] = accPM_E ? PMDin[15:0] : DMDin1[15:0];
wire [15:0] SIr, SIs;
wire CLKSIrenb, CLKSIsenb;
assign CLKSIrenb = !updateSIr;
assign CLKSIsenb = !updateSIs;
`ifdef FD_DFT
REG16L sirwe(DSPCLK, CLKSIrenb, GO_C, SSin[15:0], SIr[15:0], SCAN_TEST);
REG16L siswe(DSPCLK, CLKSIsenb, GO_C, SSin[15:0], SIs[15:0], SCAN_TEST);
`else
REG16L sirwe(DSPCLK, CLKSIrenb, GO_C, SSin[15:0], SIr[15:0]);
REG16L siswe(DSPCLK, CLKSIsenb, GO_C, SSin[15:0], SIs[15:0]);
`endif
wire [4:0] SBin;
wire [7:0] SEin;
assign #`del SBin[4:0] = MTSB_E ? DMDin1[4:0] : EXP[4:0];
assign #2 SEin[7:0] = MTSE_E ? SSin[7:0] : {EXP[5], EXP[5], EXP[5:0]};
reg [4:0] SBr, SBs;
always @(posedge DSPCLK)
if (updateSBr) SBr[4:0] = #`del SBin[4:0];
always @(posedge DSPCLK)
if (updateSBs) SBs[4:0] = #`del SBin[4:0];
wire [7:0] SEr, SEs;
wire CLKSErenb, CLKSEsenb;
wire SErwe, SEswe;
assign CLKSErenb = !updateSEr;
assign CLKSEsenb = !updateSEs;
assign SErwe = GO_C && EX_enc;
assign SEswe = GO_C && EX_enc;
`ifdef FD_DFT
REG8L serwe(DSPCLK, CLKSErenb, SErwe, SEin[7:0], SEr[7:0], SCAN_TEST);
REG8L seswe(DSPCLK, CLKSEsenb, SEswe, SEin[7:0], SEs[7:0], SCAN_TEST);
`else
REG8L serwe(DSPCLK, CLKSErenb, SErwe, SEin[7:0], SEr[7:0]);
REG8L seswe(DSPCLK, CLKSEsenb, SEswe, SEin[7:0], SEs[7:0]);
`endif
wire [15:0] SR0in;
assign #2 SR0in[15:0] = MTSR0_E ? SSin[15:0] : SO_L[15:0];
wire [15:0] SR0r, SR0s;
wire SR0rwe, SR0swe;
wire CLKSR0renb, CLKSR0senb;
assign SR0rwe = GO_C && EX_enc;
assign SR0swe = GO_C && EX_enc;
assign CLKSR0renb = !updateSR0r;
assign CLKSR0senb = !updateSR0s;
`ifdef FD_DFT
REG16L sr0rwe(DSPCLK, CLKSR0renb, SR0rwe, SR0in[15:0], SR0r[15:0], SCAN_TEST);
REG16L sr0swe(DSPCLK, CLKSR0senb, SR0swe, SR0in[15:0], SR0s[15:0], SCAN_TEST);
`else
REG16L sr0rwe(DSPCLK, CLKSR0renb, SR0rwe, SR0in[15:0], SR0r[15:0]);
REG16L sr0swe(DSPCLK, CLKSR0senb, SR0swe, SR0in[15:0], SR0s[15:0]);
`endif
wire [15:0] SR1in;
assign #2 SR1in[15:0] = MTSR1_E ? SSin[15:0] : SO_H[15:0];
wire [15:0] SR1r, SR1s;
wire SR1rwe, SR1swe;
wire CLKSR1renb, CLKSR1senb;
assign CLKSR1renb = !updateSR1r;
assign CLKSR1senb = !updateSR1s;
assign SR1rwe = GO_C && EX_enc;
assign SR1swe = GO_C && EX_enc;
`ifdef FD_DFT
REG16L sr1rwe(DSPCLK, CLKSR1renb, SR1rwe, SR1in[15:0], SR1r[15:0], SCAN_TEST);
REG16L sr1swe(DSPCLK, CLKSR1senb, SR1swe, SR1in[15:0], SR1s[15:0], SCAN_TEST);
`else
REG16L sr1rwe(DSPCLK, CLKSR1renb, SR1rwe, SR1in[15:0], SR1r[15:0]);
REG16L sr1swe(DSPCLK, CLKSR1senb, SR1swe, SR1in[15:0], SR1s[15:0]);
`endif
/*----------------------------------------------*/
/*----------------------------------------------*/
wire [15:0] SI, SIout;
assign SI[15:0] = SHADOW ? SIs[15:0] : SIr[15:0];
assign SIout[15:0] = {16{MFSI_E}} & SI[15:0];
wire [15:0] SBout;
assign SB[4:0] = SHADOW ? SBs[4:0] : SBr[4:0];
assign SBout[15:0] = {16{MFSB_E}} & {{11{SB[4]}}, SB[4:0]};
wire [15:0] SEout;
assign SE[7:0] = SHADOW ? SEs[7:0] : SEr[7:0];
assign SEout[15:0] = {16{MFSE_E}} & {{8{SE[7]}}, SE[7:0]};
assign SEf1 = (SE[7:0] == 8'b11110001);
wire [15:0] SR0out;
assign SR0[15:0] = SHADOW ? SR0s[15:0] : SR0r[15:0];
assign SR0out[15:0] = {16{MFSR0_E}} & SR0[15:0];
wire [15:0] SR1out;
assign SR1[15:0] = SHADOW ? SR1s[15:0] : SR1r[15:0];
assign SR1out[15:0] = {16{MFSR1_E}} & SR1[15:0];
wire [15:0] SHTout;
assign SHTout[15:0] = SIout[15:0] | SBout[15:0] | SEout[15:0] |
SR0out[15:0] | SR1out[15:0];
assign DMDsht[15:0] = {16{MFSHT_E}} & SHTout[15:0];
assign PMDsht[15:0] = {16{pMFSHT_E}} & SHTout[15:0];
wire [15:0] SR_E;
wire Rstore_SR_E, Rstore_SR_D;
assign Rstore_SR_E = (Xop_E[2:1] == 2'b11);
assign Rstore_SR_D = (Xop_D[2:1] == 2'b11);
assign SR_E[15:0] = Xop_E[0] ? SR1[15:0] : SR0[15:0];
wire [15:0] R_sht_in_D = {16{Rstore_SR_D & ~GO_MAC & ~BYPASSR_D & Xop_D[0]}} & SR1[15:0]
| {16{Rstore_SR_D & ~GO_MAC & ~BYPASSR_D & ~Xop_D[0]}} & SR0[15:0]
| {16{Rstore_SR_E & GO_MAC & Xop_E[0]}} & SR1[15:0]
| {16{Rstore_SR_E & GO_MAC & ~Xop_E[0]}} & SR0[15:0]
| {16{(Rstore_SR_D & ~GO_MAC & BYPASSR_D & ~MTSR1_E & Xop_D[0])}} & SO_H[15:0]
| {16{(Rstore_SR_D & ~GO_MAC & BYPASSR_D & ~MTSR0_E & ~Xop_D[0])}} & SO_L[15:0];
assign R_sht_D[15:0] = {16{(Rstore_SR_D & ~GO_MAC & BYPASSR_D & accPM_E & ((MTSR1_E & Xop_D[0])
|(MTSR0_E & ~Xop_D[0])))}} & PMDin[15:0]
| {16{(Rstore_SR_D & ~GO_MAC & BYPASSR_D & ~accPM_E & ((MTSR1_E & Xop_D[0])
|(MTSR0_E & ~Xop_D[0])))}} & DMDin[15:0]
| R_sht_in_D[15:0];
assign R_sht_E[15:0] = {16{Rstore_SR_E}} & SR_E[15:0];
wire selSI;
assign selSI = (Xop_E[2:1] == 00);
assign SIN[15:0] = selSI ? SI[15:0] : R_in_E[15:0];
endmodule
|
/*--------------------------------------------------------------*/
/*--------------------------------------------------------------*/
/*--------------------------------------------------------------*/
/*--------------------------------------------------------------*/
`define del 1
module ES_SHT(/*---------------- Inputs ---------------*/
DSPCLK, GO_C, EX_en, EX_enc, R_in_E,
SF_E, IRE, Xop_D, Xop_E,
SHADOW,
MTSI_E, MTSB_E, MTSE_E,
MTSR0_E, MTSR1_E, MFSI_E, MFSB_E, MFSE_E,
MFSR1_E, MFSR0_E, SIMM_E, BYPASSR_D, MFSHT_E,
pMFSHT_E, accPM_E, GO_MAC, updSR0_Eg, updSR1_Eg,
SHTop_E, updSR_E,
AC, AV, SS,
`ifdef FD_DFT
SCAN_TEST,
`endif
R_sht_E, R_sht_D,
SSin, updateSS,
DMDin, DMDsht, PMDin, PMDsht);
input DSPCLK, GO_C, EX_en, EX_enc;
input SHADOW;
input MTSI_E, MTSB_E, MTSE_E, MTSR0_E;
input MTSR1_E, MFSI_E, MFSB_E, MFSE_E, BYPASSR_D;
input MFSR1_E, MFSR0_E, SIMM_E, AC, AV, SS;
input [15:0] R_in_E;
input [3:0] SF_E;
input [7:0] IRE;
input [2:0] Xop_D, Xop_E;
input MFSHT_E, pMFSHT_E, accPM_E, GO_MAC;
input updSR0_Eg, updSR1_Eg, SHTop_E;
input updSR_E;
`ifdef FD_DFT
input SCAN_TEST;
`endif
output SSin, updateSS;
output [15:0] R_sht_E, R_sht_D;
input [15:0] DMDin;
output [15:0] DMDsht;
input [15:0] PMDin;
output [15:0] PMDsht;
/*-----------------------------------------------*/
wire EXPGTSB, SEf1, updateSIr, updateSIs;
wire updateSBr, updateSBs, updateSEr, updateSEs;
wire updateSR0s, updateSR0r, updateSR1r, updateSR1s;
wire HIX, LO, XI, NORM;
wire [4:0] SB;
wire [5:0] EXP;
wire [7:0] SE;
wire [15:0] SO_H, SO_L, SIN;
wire [15:0] SR0, SR1;
ES_DEC es_dec(/* IN */
GO_C, EX_en, EX_enc, EXPGTSB, SEf1,
SHADOW, SF_E[3:0], MTSI_E, MTSB_E, MTSE_E, updSR0_Eg,
updSR1_Eg, SIN[15], AC, AV, SHTop_E, MTSR0_E, MTSR1_E, updSR_E,
updateSIr, updateSIs, updateSBr, updateSBs, updateSEr,
updateSEs, updateSR0r, updateSR0s, updateSR1r, updateSR1s,
updateSS, DBE, HIX, LO, XI, NORM);
ES_REG es_reg(/* IN */
DSPCLK, SHADOW, EXP[5:0], Xop_D[2:0], Xop_E[2:0],
SO_L[15:0], SO_H[15:0], MTSB_E, MTSE_E,
MTSR1_E, MTSR0_E, R_in_E[15:0], updateSIr, updateSIs,
updateSBr, updateSBs, updateSEr, updateSEs,
updateSR1r, updateSR1s, updateSR0r, updateSR0s,
MFSI_E, MFSB_E, MFSE_E, MFSR1_E, MFSR0_E, BYPASSR_D, MFSHT_E,
pMFSHT_E, accPM_E, GO_MAC, EX_enc, GO_C,
`ifdef FD_DFT
SCAN_TEST,
`endif
SEf1, SIN[15:0], SE[7:0], SB[4:0], SR0[15:0], SR1[15:0],
R_sht_E[15:0], R_sht_D[15:0],
DMDin[15:0], DMDsht[15:0], PMDin[15:0], PMDsht[15:0]);
ES_EXP es_exp(/* IN */
SIN[15:0], SB[4:0], DBE, HIX, LO,
SS, AV, SHTop_E, SF_E[3:2],
EXP[5:0], SSin, EXPGTSB);
ES_ARRAY er_array(/* IN */
SIN[15:0], SR1[15:0], SR0[15:0], SF_E[3:0], IRE[7:0],
SE[7:0], XI, NORM, SIMM_E, SHTop_E,
SO_H[15:0], SO_L[15:0]);
endmodule
|
`include "../include/x_def.v"
module SICE (/* ------------ Inputs : ------------- */
T_PWRONn, ICK, IMS, DSPCLK, CM_rd,
DMD, T_GOICE, PM_bdry_sel,
enTRAP_RL,
GO_F, GO_E, GO_C, ICE_ST, DRA,
EXA, HALTclr_h,
GOICEclr_h, GOICEdis,
PMOVL_dsp, DMOVL_dsp,
IR, Dummy_R, nNOP_Eg, MTIDR_Eg,
SBP_R, readCM_E,
BGn, PMA, DMA, EXTC_Eg,
accPM_Eg, accDM_Eg,
eRDY,
BRST, IACKn,
`ifdef FD_DFT
SCAN_TEST,
`endif
GRST, GO_Fx, GO_Ex, GO_Cx, HALT_E,
IRR, IDR, GOICE, GOICE_syn,
ICE_wakeup,
Upd_IR, SPC, SBP_EN, enTYP3,
T_ID, IDo, IDoe,
EX_en, selIVER,
SICEmmio );
input [15:0] DMD;
input [13:0] DRA,
EXA,
PMA,
DMA;
input [23:0] IR,
CM_rd;
input [7:0] PMOVL_dsp;
input [3:0] DMOVL_dsp;
input T_ID,
T_GOICE,
T_PWRONn,
PM_bdry_sel,
DSPCLK,
ICK,
IMS,
GO_F,
GO_E,
GO_C,
Dummy_R,
HALTclr_h,
GOICEclr_h,
GOICEdis,
ICE_ST,
nNOP_Eg,
SBP_R,
readCM_E,
MTIDR_Eg,
BGn,
EXTC_Eg,
eRDY,
accPM_Eg,
accDM_Eg,
enTRAP_RL;
input BRST, IACKn;
`ifdef FD_DFT
input SCAN_TEST;
`endif
input EX_en, selIVER;
output [15:0] SICEmmio;
output [23:0] SPC;
output [13:0] IRR;
output [23:0] IDR;
output IDo,
IDoe,
GRST,
GO_Fx,
GO_Ex,
GO_Cx,
HALT_E,
GOICE,
GOICE_syn,
SBP_EN,
Upd_IR,
enTYP3,
ICE_wakeup;
reg [2:0] ICS,
INS;
wire [23:0] IDR;
reg [3:0] IAR;
reg [2:0] ITR;
reg [13:0] IRR;
reg [18:0] DBR1, DBR2;
reg [17:0] IBR1, IBR2, IMR1, IMR2,
DMR1, DMR2;
reg [23:0] SPC;
reg [23:0] SPC_do;
reg IDo, OE, IRST, GOICE_1, GOICE_2, GO_NXi, UpdDR_si, CMRW;
reg IDONE, GO_NX, UpdDR_sd1, UpdDR_sd2, GOICE_syn,
HALT_E, IDLE_d1, IDLE_d2;
wire GOICE;
wire [3:0] IAR_di;
wire [5:0] ICR;
wire [5:0] ISR;
wire [13:0] IRR_di;
wire [23:0] IDR_di;
wire [23:0] SPC_di;
wire ICKg;
wire IAR_we, equICR, equIDR, equIR, equITR, equIRR,
equIBR1, equIBR2, equIMR1, equIMR2, equDBR1,
equDBR2, equDMR1, equDMR2, SPC_we, Upd_DR, ICR_we,
IDR_we, SBP_EN, ITR_we, IDR_enb,
DSPwe, IRR_we, IBR1_we, IBR2_we, IMR1_we, IMR2_we,
DBR1_we, DBR2_we, DMR1_we, DMR2_we, IBP1_R,
IBP2_R, IBP_R, DBP1_R, DBP2_R, DBP3_R, DBP4_R,
DBP_R, HALT_R, T_PWRON, MGNT, PRST;
wire [17:0] COVL_DRA, POVL_PMA, DOVL_DMA;
reg [23:0] ICYC, IIRC;
reg ICYC_en, ICYC_clr;
wire [14:0] IVER;
wire ICYCclk, ICYC_cn, ICYC_full,
IIRC_cn, ICYC_we,
IIRC_we, equICYC, equIIRC;
`ifdef FD_DFT
wire CLR_I, CLR_M, GOclr;
`else
reg CLR_I, CLR_M, GOclr;
`endif
wire MDONE = eRDY;
wire EMC = EXTC_Eg;
assign #`da T_PWRON = !T_PWRONn;
assign #`da PRST = T_PWRON;
reg [1:0] RCS, RNS;
reg IRST_syn, PRST_syn;
reg RST_req;
wire RST_gnt,
GRST;
parameter R_IDLE = 2'b00,
R_WAIT_GNT = 2'b01,
R_RST_1 = 2'b10,
R_RST_2 = 2'b11;
always @(posedge DSPCLK) begin
IRST_syn <= #`db IRST;
PRST_syn <= #`db PRST;
end
always @(posedge DSPCLK or posedge GRST)
if(GRST) RST_req <= #`db 1'b0;
else RST_req <= #`db BRST || IRST_syn;
assign RST_gnt = !IACKn;
always @(RCS or RST_req or RST_gnt) begin
case(RCS)
R_IDLE : if(RST_req)
RNS = R_WAIT_GNT;
else
RNS = R_IDLE;
R_WAIT_GNT : if(RST_gnt)
RNS = R_RST_1;
else
RNS = R_WAIT_GNT;
R_RST_1 : RNS = R_RST_2;
R_RST_2 : RNS = R_IDLE;
default : RNS = R_IDLE;
endcase
end
always @(posedge DSPCLK or posedge PRST)
if(PRST) RCS <= #`db 2'b0;
else RCS <= #`db RNS;
`ifdef FD_GTCLK
`ifdef FD_DFT
wire GRST_h = (RCS==R_RST_1) || (RCS==R_RST_2) || PRST_syn;
GTECH_MUXI2 grsti(.A(GRST_h), .B(PRST), .S(SCAN_TEST), .Z(GRST_));
GtCLK_NOT grst (.Z(GRST), .A(GRST_));
`else
wire GRST_h = (RCS==R_RST_1) || (RCS==R_RST_2) || PRST_syn;
GtCLK_NOT grsti(.Z(GRST_), .A(GRST_h));
GtCLK_NOT grst (.Z(GRST), .A(GRST_));
`endif
`else
assign GRST = (RCS[1] == R_RST_1[1] && RCS[0] == R_RST_1[0]) || (RCS[1] == R_RST_2[1] && RCS[0] == R_RST_2[0]) || PRST_syn;
//wire GRST = (RCS==R_RST_1) || (RCS==R_RST_2) || PRST_syn;
`endif
assign #`da GO_Fx = GO_F || GO_NX;
assign #`da GO_Ex = GO_E || GO_NX;
assign #`da GO_Cx = GO_C || GO_NX;
assign #`da MGNT = !BGn;
parameter Idle = 3'h0,
Sel_D = 3'h1,
Sel_A = 3'h2,
Shift_Ai = 3'h3,
WriteD = 3'h4,
Shift_Di = 3'h5,
ReadD = 3'h6,
Shift_Do = 3'h7;
always @(ICS or IMS) begin
INS[2:0] <= #`da Idle;
case (ICS)
Idle : INS <= #`da IMS ? Idle : Sel_D;
Sel_D : INS <= #`da IMS ? Sel_A : WriteD;
Sel_A : INS <= #`da IMS ? Idle : Shift_Ai;
Shift_Ai : INS <= #`da IMS ? WriteD : Shift_Ai;
WriteD : INS <= #`da IMS ? ReadD : Shift_Di;
Shift_Di : INS <= #`da IMS ? Idle : Shift_Di;
ReadD : INS <= #`da IMS ? Idle : Shift_Do;
Shift_Do : INS <= #`da IMS ? ReadD : Shift_Do;
endcase
end
always @(posedge ICK) begin
if (T_PWRON) ICS[2:0] <= #`da Idle;
else ICS[2:0] <= #`da INS[2:0];
end
always @(posedge ICK) begin
IDLE_d1 <= #`db (ICS == Idle);
IDLE_d2 <= #`db IDLE_d1;
end
`ifdef FD_GTCLK
GTECH_NOR3 uck0 (.Z(IDLE_d0), .A(ICS[0]), .B(ICS[1]), .C(ICS[2]));
GtCLK_AND3 uck1 (.Z(ICK_dis), .A(IDLE_d0), .B(IDLE_d1), .C(IDLE_d2));
`ifdef FD_DFT
GTECH_AND_NOT utm0 (.Z(ICK_dis_dft), .A(ICK_dis), .B(SCAN_TEST));
GTECH_NOR2 uck2 (.Z(ICKg_), .A(ICK), .B(ICK_dis_dft));
GtCLK_NOT ckICKg (.Z(ICKg), .A(ICKg_));
`else
GTECH_NOR2 uck2 (.Z(ICKg_), .A(ICK), .B(ICK_dis));
GtCLK_NOT ckICKg (.Z(ICKg), .A(ICKg_));
`endif
`else
wire ICKg_en=!((ICS == Idle) && IDLE_d1 && IDLE_d2);
assign #`da ICKg = ICK;
`endif
assign #`da IAR_we = (INS == Shift_Ai);
assign #`da IAR_di[3:0] = {T_ID,IAR[3:1]};
always @(posedge ICKg or posedge PRST) begin
if (PRST) IAR[3:0] <= #`db 4'b0;
`ifdef FD_FPGA
else if (IAR_we & ICKg_en) IAR[3:0] <= #`db IAR_di[3:0];
`else
else if (IAR_we) IAR[3:0] <= #`db IAR_di[3:0];
`endif
end
assign #`da equICR = IAR == 4'h1;
assign #`da equIDR = IAR == 4'h2;
assign #`da equIR = IAR == 4'h3;
assign #`da equITR = IAR == 4'h4;
assign #`da equIRR = IAR == 4'h5;
assign #`da equICYC = IAR == 4'h6;
assign #`da equIIRC = IAR == 4'h7;
assign #`da equIBR1 = IAR == 4'h8;
assign #`da equIBR2 = IAR == 4'h9;
assign #`da equIMR1 = IAR == 4'ha;
assign #`da equIMR2 = IAR == 4'hb;
assign #`da equDBR1 = IAR == 4'hc;
assign #`da equDBR2 = IAR == 4'hd;
assign #`da equDMR1 = IAR == 4'he;
assign #`da equDMR2 = IAR == 4'hf;
assign #`da SPC_we = (INS == Shift_Di) ||
(INS == ReadD) ||
(INS == Shift_Do);
always @(IAR or ISR or ICR or IDR or
IR or ITR or IRR or IBR1 or
IBR2 or IMR1 or IMR2 or
DBR1 or DBR2 or DMR1 or
DMR2 or ICYC or IIRC or IVER) begin
case (IAR)
4'h0 : SPC_do[23:0] <= #`da {ISR[5:0], IVER[7:0], 10'b0};
4'h1 : SPC_do[23:0] <= #`da {ICR[5:0], 18'b0};
4'h2 : SPC_do[23:0] <= #`da IDR[23:0];
4'h3 : SPC_do[23:0] <= #`da IR[23:0];
4'h4 : SPC_do[23:0] <= #`da {11'h7ff, ITR[2:0], 10'b0};
4'h5 : SPC_do[23:0] <= #`da {IRR[13:0], 10'b0};
4'h6 : SPC_do[23:0] <= #`da ICYC[23:0];
4'h7 : SPC_do[23:0] <= #`da IIRC[23:0];
4'h8 : SPC_do[23:0] <= #`da {IBR1[17:0], 6'b0};
4'h9 : SPC_do[23:0] <= #`da {IBR2[17:0], 6'b0};
4'ha : SPC_do[23:0] <= #`da {IMR1[17:0], 6'b0};
4'hb : SPC_do[23:0] <= #`da {IMR2[17:0], 6'b0};
4'hc : SPC_do[23:0] <= #`da {DBR1[18:0], 5'b0};
4'hd : SPC_do[23:0] <= #`da {DBR2[18:0], 5'b0};
4'he : SPC_do[23:0] <= #`da {DMR1[17:0], 6'b0};
4'hf : SPC_do[23:0] <= #`da {DMR2[17:0], 6'b0};
default :
SPC_do[23:0] <= #`da {ISR[5:0], 18'b0};
endcase
end
assign #`da SPC_di[23:0] = (INS == ReadD) ? SPC_do[23:0] :
(INS == Shift_Do) ? {SPC[22:0], 1'b0}
: {T_ID,SPC[23:1]};
always @(posedge ICKg)
`ifdef FD_FPGA
if (SPC_we & ICKg_en) SPC[23:0] <= #`db SPC_di[23:0];
`else
if (SPC_we) SPC[23:0] <= #`db SPC_di[23:0];
`endif
always @(negedge ICKg)
`ifdef FD_FPGA
if(ICKg_en) IDo <= #`db SPC[23];
`else
IDo <= #`db SPC[23];
`endif
always @(posedge ICKg)
`ifdef FD_FPGA
if(ICKg_en) OE <= #`db (INS == ReadD) || (INS == Shift_Do);
`else
OE <= #`db (INS == ReadD) || (INS == Shift_Do);
`endif
assign #`da IDoe = OE && !IMS;
assign #`d0 ISR[5:0] = {MDONE, IDONE, 1'b0, EMC, MGNT, ICE_ST};
always @(posedge DSPCLK or posedge CLR_I) begin
if (CLR_I) IDONE <= #`db 1'b0;
else if (GO_Cx) IDONE <= #`db nNOP_Eg;
end
assign #`da ICYC_we = Upd_DR && equICYC;
assign #`da IIRC_we = Upd_DR && equIIRC;
always @(posedge ICKg or posedge PRST) begin
if (PRST) ICYC_en <= #`db 1'b0;
else if (ICYC_we) ICYC_en <= #`db SPC[23];
end
reg ICYC_en_syn;
always @(posedge DSPCLK) ICYC_en_syn <= #`db ICYC_en;
always @(posedge ICKg or posedge PRST) begin
if (PRST) ICYC_clr <= #`db 1'b0;
else if (ICYC_clr) ICYC_clr <= #`db 1'b0;
else if (IIRC_we) ICYC_clr <= #`db SPC[23];
end
`ifdef FD_GTCLK
`ifdef FD_DFT
GTECH_NOR2 ui0 (.Z(ICYC_en_syn_dft), .A(ICYC_en_syn), .B(SCAN_TEST));
GtCLK_OR2 ckICYC (.Z(ICYCclk), .A(DSPCLK), .B(ICYC_en_syn_dft));
`else
GtCLK_OR_NOT ckICYC (.Z(ICYCclk), .A(DSPCLK), .B(ICYC_en_syn));
`endif
`else
assign ICYCclk = DSPCLK | ~ICYC_en_syn;
`endif
assign #`da ICYC_full = &{ICYC[23:0]};
assign #`da ICYC_cn = !(ICE_ST || ICYC_full);
`ifdef FD_DFT
wire ICYC_rst_h = ICYC_clr || GRST;
wire ICYC_rst = SCAN_TEST ? GRST : ICYC_rst_h;
`else
wire ICYC_rst = ICYC_clr || GRST;
`endif
always @(posedge ICYCclk or posedge ICYC_rst) begin
if(ICYC_rst) ICYC[23:0] <= #`db 24'b0;
else if(ICYC_cn) ICYC[23:0] <= #`db ICYC + 1'b1;
end
assign #`da IIRC_cn = ICYC_cn && EX_en && GO_C;
always @(posedge ICYCclk or posedge ICYC_rst) begin
if(ICYC_rst) IIRC[23:0] <= #`db 24'b0;
else if(IIRC_cn) IIRC[23:0] <= #`db IIRC + 1'b1;
end
assign IVER[14:0] = {PM_bdry_sel, 1'b0, 1'b0,
1'b1, 1'b0, 1'b1, 1'b1,
1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1};
assign SICEmmio = {16{selIVER}} & {ICYC_en, IVER[14:0]};
assign #`d0 ICR[5:0] = {CMRW, CLR_M, CLR_I, GO_NX, GOICE, IRST};
assign #`da Upd_DR = (ICS == Shift_Di) && (INS == Idle);
assign #`da ICR_we = Upd_DR && equICR;
assign #`da enTYP3 = !(ICE_ST && CMRW);
always @(posedge ICKg or posedge PRST) begin
if (PRST) IRST <= #`db 0;
`ifdef FD_FPGA
else if (IRST & ICKg_en) IRST <= #`db 0;
else if (ICR_we & ICKg_en) IRST <= #`db SPC[18];
`else
else if (IRST) IRST <= #`db 0;
else if (ICR_we) IRST <= #`db SPC[18];
`endif
end
always @(posedge ICKg or posedge PRST) begin
if (PRST) GOICE_1 <= #`db 0;
`ifdef FD_FPGA
else if (ICR_we & ICKg_en) GOICE_1 <= #`db SPC[19];
`else
else if (ICR_we) GOICE_1 <= #`db SPC[19];
`endif
end
always @(posedge ICK or posedge PRST) begin
if (PRST) GOICE_2 <= #`db 0;
else GOICE_2 <= #`db T_GOICE;
end
assign #`da GOICE = GOICE_1 || GOICE_2;
reg GOICE_s1;
always @(posedge ICKg or posedge PRST)
if (PRST) GOICE_s1 <= #`db 0;
else GOICE_s1 <= #`db GOICE;
assign #`da ICE_wakeup = GOICE && !GOICE_s1;
always @(posedge ICKg or posedge GOclr) begin
if (GOclr) GO_NXi <= #`db 0;
`ifdef FD_FPGA
else if (ICR_we & ICKg_en) GO_NXi <= #`db SPC[20];
`else
else if (ICR_we) GO_NXi <= #`db SPC[20];
`endif
end
always @(posedge DSPCLK or posedge PRST)
if(PRST) GO_NX <= #`db 1'b0;
else GO_NX <= #`db GO_NXi;
`ifdef FD_DFT
reg GOclr_h;
always @(negedge DSPCLK or posedge PRST)
if(PRST) GOclr_h <= #`db 1'b1;
else GOclr_h <= #`db GO_NX;
assign GOclr = SCAN_TEST ? PRST : GOclr_h;
`else
always @(negedge DSPCLK or posedge PRST)
if(PRST) GOclr <= #`db 1'b1;
else GOclr <= #`db GO_NX;
`endif
`ifdef FD_DFT
reg CLR_I_h;
always @(posedge ICKg or posedge PRST) begin
if (PRST) CLR_I_h <= #`db 0;
else if (CLR_I_h) CLR_I_h <= #`db 0;
else if (ICR_we) CLR_I_h <= #`db SPC[21];
end
assign CLR_I = SCAN_TEST ? PRST : CLR_I_h;
`else
always @(posedge ICKg or posedge PRST) begin
if (PRST) CLR_I <= #`db 0;
`ifdef FD_FPGA
else if (CLR_I & ICKg_en) CLR_I <= #`db 0;
else if (ICR_we & ICKg_en) CLR_I <= #`db SPC[21];
`else
else if (CLR_I) CLR_I <= #`db 0;
else if (ICR_we) CLR_I <= #`db SPC[21];
`endif
end
`endif
`ifdef FD_DFT
reg CLR_M_h;
always @(posedge ICKg or posedge PRST) begin
if (PRST) CLR_M_h <= #`db 0;
else if (CLR_M_h) CLR_M_h <= #`db 0;
else if (ICR_we) CLR_M_h <= #`db SPC[22];
end
assign CLR_M = SCAN_TEST ? PRST : CLR_M_h;
`else
always @(posedge ICKg or posedge PRST) begin
if (PRST) CLR_M <= #`db 0;
`ifdef FD_FPGA
else if (CLR_M & ICKg_en) CLR_M <= #`db 0;
else if (ICR_we & ICKg_en) CLR_M <= #`db SPC[22];
`else
else if (CLR_M) CLR_M <= #`db 0;
else if (ICR_we) CLR_M <= #`db SPC[22];
`endif
end
`endif
always @(posedge ICKg or posedge PRST) begin
if (PRST) CMRW <= #`db 0;
`ifdef FD_FPGA
else if (ICR_we & ICKg_en) CMRW <= #`db SPC[23];
`else
else if (ICR_we) CMRW <= #`db SPC[23];
`endif
end
assign #`da IDR_we = equIDR && DSPwe ||
readCM_E && GO_Cx ||
MTIDR_Eg && GO_Cx;
assign #`da IDR_di[23:0] = {24{equIDR && DSPwe}} & SPC[23:0] |
{24{readCM_E}} & CM_rd[23:0] |
{24{MTIDR_Eg}} & {8'b0, DMD[15:0]};
`ifdef FD_GTCLK
GTECH_NOT uck4 (.Z(UpdDR_sd2_), .A(UpdDR_sd2));
GTECH_AND2 uck5_1 (.Z(IDR_enbi_1), .A(UpdDR_sd1), .B(UpdDR_sd2_));
GTECH_NOR3 uck5 (.Z(IDR_enbi), .A(readCM_E), .B(MTIDR_Eg), .C(IDR_enbi_1));
GtCLK_BUF uck6 (.Z(IDR_enb), .A(IDR_enbi));
`else
assign IDR_enb = !(MTIDR_Eg || readCM_E || !(UpdDR_sd1 && UpdDR_sd2));
`endif
`ifdef FD_DFT
REG12L idr0_reg (DSPCLK, IDR_enb, IDR_we, IDR_di[11:0], IDR[11:0], SCAN_TEST);
REG12L idr1_reg (DSPCLK, IDR_enb, IDR_we, IDR_di[23:12], IDR[23:12], SCAN_TEST);
`else
REG12L idr0_reg (DSPCLK, IDR_enb, IDR_we, IDR_di[11:0], IDR[11:0]);
REG12L idr1_reg (DSPCLK, IDR_enb, IDR_we, IDR_di[23:12], IDR[23:12]);
`endif
assign #`da Upd_IR = equIR && DSPwe;
assign #`d0 SBP_EN = ITR[0];
assign #`da ITR_we = Upd_DR && equITR;
always @(posedge ICKg or posedge PRST) begin
if (PRST) ITR[2:0] <= #`db 3'b0;
`ifdef FD_FPGA
else if (ITR_we & ICKg_en) ITR[2:0] <= #`db SPC[12:10];
`else
else if (ITR_we) ITR[2:0] <= #`db SPC[12:10];
`endif
end
always @(posedge ICKg)
`ifdef FD_FPGA
if(ICKg_en) UpdDR_si <= #`db Upd_DR;
`else
UpdDR_si <= #`db Upd_DR;
`endif
always @(posedge DSPCLK) begin
UpdDR_sd1 <= #`db UpdDR_si;
UpdDR_sd2 <= #`db UpdDR_sd1;
end
assign #`da DSPwe = UpdDR_sd1 && !UpdDR_sd2;
assign #`da IRR_we = equIRR && DSPwe ||
HALTclr_h;
assign IRR_di[13:0] = HALTclr_h ? EXA[13:0] : SPC[23:10];
always @(posedge DSPCLK)
if (IRR_we) IRR[13:0] <= #`db IRR_di[13:0];
assign #`da IBR1_we = Upd_DR && equIBR1;
assign #`da IBR2_we = Upd_DR && equIBR2;
assign #`da IMR1_we = Upd_DR && equIMR1;
assign #`da IMR2_we = Upd_DR && equIMR2;
`ifdef FD_FPGA
always @(posedge ICKg) if (IBR1_we & ICKg_en) IBR1[17:0] <= #`db SPC[23:6];
always @(posedge ICKg) if (IBR2_we & ICKg_en) IBR2[17:0] <= #`db SPC[23:6];
`else
always @(posedge ICKg) if (IBR1_we) IBR1[17:0] <= #`db SPC[23:6];
always @(posedge ICKg) if (IBR2_we) IBR2[17:0] <= #`db SPC[23:6];
`endif
always @(posedge ICKg or posedge PRST) begin
if (PRST) IMR1[17:0] <= #`db 18'h0;
`ifdef FD_FPGA
else if (IMR1_we & ICKg_en) IMR1[17:0] <= #`db SPC[23:6];
`else
else if (IMR1_we) IMR1[17:0] <= #`db SPC[23:6];
`endif
end
always @(posedge ICKg or posedge PRST) begin
if (PRST) IMR2[17:0] <= #`db 18'h0;
`ifdef FD_FPGA
else if (IMR2_we & ICKg_en) IMR2[17:0] <= #`db SPC[23:6];
`else
else if (IMR2_we) IMR2[17:0] <= #`db SPC[23:6];
`endif
end
assign #`da COVL_DRA[17:0] = {PMOVL_dsp[3:0], DRA[13:0]};
assign #`da IBP1_R = IMR1[17] && !(COVL_DRA[17] ^ IBR1[17]) &&
((COVL_DRA[16:0] | IMR1[16:0]) ==
(IBR1[16:0] | IMR1[16:0]));
assign #`da IBP2_R = IMR2[17] && !(COVL_DRA[17] ^ IBR2[17]) &&
((COVL_DRA[16:0] | IMR2[16:0]) ==
(IBR2[16:0] | IMR2[16:0]));
assign #`da IBP_R = IBP1_R || IBP2_R;
assign #`da DBR1_we = Upd_DR && equDBR1;
assign #`da DBR2_we = Upd_DR && equDBR2;
assign #`da DMR1_we = Upd_DR && equDMR1;
assign #`da DMR2_we = Upd_DR && equDMR2;
`ifdef FD_FPGA
always @(posedge ICKg) if (DBR1_we & ICKg_en) DBR1[18:0] <= #`db SPC[23:5];
always @(posedge ICKg) if (DBR2_we & ICKg_en) DBR2[18:0] <= #`db SPC[23:5];
`else
always @(posedge ICKg) if (DBR1_we) DBR1[18:0] <= #`db SPC[23:5];
always @(posedge ICKg) if (DBR2_we) DBR2[18:0] <= #`db SPC[23:5];
`endif
always @(posedge ICKg or posedge PRST) begin
if (PRST) DMR1[17:0] <= #`db 18'h0;
`ifdef FD_FPGA
else if (DMR1_we & ICKg_en) DMR1[17:0] <= #`db SPC[23:6];
`else
else if (DMR1_we) DMR1[17:0] <= #`db SPC[23:6];
`endif
end
always @(posedge ICKg or posedge PRST) begin
if (PRST) DMR2[17:0] <= #`db 18'h0;
`ifdef FD_FPGA
else if (DMR2_we & ICKg_en) DMR2[17:0] <= #`db SPC[23:6];
`else
else if (DMR2_we) DMR2[17:0] <= #`db SPC[23:6];
`endif
end
assign #`da POVL_PMA[17:0] = {PMOVL_dsp[7:4], PMA[13:0]};
assign #`da DBP1_R = accPM_Eg && DMR1[17] && !DBR1[18] &&
!(POVL_PMA[17] ^ DBR1[17]) &&
((POVL_PMA[16:0] | DMR1[16:0]) ==
(DBR1[16:0] | DMR1[16:0]));
assign #`da DBP2_R = accPM_Eg && DMR2[17] && !DBR2[18] &&
!(POVL_PMA[17] ^ DBR2[17]) &&
((POVL_PMA[16:0] | DMR2[16:0]) ==
(DBR2[16:0] | DMR2[16:0]));
assign #`da DOVL_DMA[17:0] = {DMOVL_dsp[3:0], DMA[13:0]};
assign #`da DBP3_R = accDM_Eg && DMR1[17] && DBR1[18] &&
!(DOVL_DMA[17] ^ DBR1[17]) &&
((DOVL_DMA[16:0] | DMR1[16:0]) ==
(DBR1[16:0] | DMR1[16:0]));
assign #`da DBP4_R = accDM_Eg && DMR2[17] && DBR2[18] &&
!(DOVL_DMA[17] ^ DBR2[17]) &&
((DOVL_DMA[16:0] | DMR2[16:0]) ==
(DBR2[16:0] | DMR2[16:0]));
assign #`da DBP_R = DBP1_R || DBP2_R || DBP3_R || DBP4_R;
always @(posedge DSPCLK) begin
if (GOICEclr_h) GOICE_syn <= #`db 1'b0;
else GOICE_syn <= #`db GOICE && enTRAP_RL;
end
assign #`da HALT_R = SBP_R ||
IBP_R && ITR[1] ||
DBP_R && ITR[2] ||
GOICE_syn && !GOICEdis;
always @(posedge DSPCLK) begin
if (GOICEclr_h || T_PWRON) HALT_E <= #`db 1'b0;
else if (!HALT_E && GO_E ) HALT_E <= #`db HALT_R & !Dummy_R;
end
endmodule
|
module SPARSER (/* In */ RSTn, ICK, nSTBx, nAufdx,
/* Out */ Busy, IMS,
/* IO */ PPD[7:0], ID);
//verisureoff
input RSTn,
ICK,
nSTBx,
nAufdx;
output Busy,
IMS;
inout ID;
inout [7:0] PPD;
reg [3:0] CS, NS;
reg [7:0] CMD,
WDext0,
WDext1,
WDext2,
WDext3;
reg [1:0] WDcnt,
RDcnt;
reg [4:0] SCNTR;
reg [31:0] RDext;
reg Prdy_WA, Prdy_WD, Prdy_RD,
Busy, IMS, ID_oe, IDo, Srdy;
wire [31:0] WDexts;
wire [7:0] PPDo;
wire TRstart, savWD, savWD0, savWD1,
savWD2, savWD3, PPD_oe, RDup,
Sinc, RST;
IDEBN dnSTB (ICK, nSTBx, nSTB);
IDEBN dnAufd (ICK, nAufdx, nAufd);
assign #`da RST = !RSTn;
always @(CS[3:0] or nSTB or nAufd or CMD[7:6] or Srdy) begin
NS <= #`da 4'h0;
case (CS)
4'h0 : NS <= #`da nSTB ? 4'h0 : 4'h1;
4'h1 : NS <= #`da nAufd ? 4'h1 : 4'h2;
4'h2 : casex ({nAufd, CMD[7:6]})
3'b0xx : NS <= #`da 4'h2;
3'b10x : NS <= #`da 4'h3;
3'b110 : NS <= #`da 4'h4;
3'b111 : NS <= #`da 4'h7;
endcase
4'h3 : NS <= #`da nSTB ? 4'h6 : 4'h3;
4'h4 : casex ({nSTB, nAufd})
2'b00 : NS <= #`da 4'h5;
2'b01 : NS <= #`da 4'h4;
2'b1x : NS <= #`da 4'h6;
endcase
4'h5 : NS <= #`da nAufd ? 4'h4 : 4'h5;
4'h6 : NS <= #`da Srdy ? 4'h0 : 4'h6;
4'h7 : NS <= #`da Srdy ? 4'h8 : 4'h7;
4'h8 : casex ({nSTB, nAufd})
2'b00 : NS <= #`da 4'h9;
2'b01 : NS <= #`da 4'h8;
2'b1x : NS <= #`da 4'h0;
endcase
4'h9 : NS <= #`da nAufd ? 4'h8 : 4'h9;
endcase
end
/* --- State piping --- */
always @(posedge ICK or posedge RST) begin
if (RST) CS <= #`db 4'h0;
else CS <= #`db NS;
end
/*
-------- Important control signals of main S.M : --------
- Prdy_WA : parallel side ready for WRIAR
- Prdy_WD : parallel side ready for WRIDR
- Prdy_RD : parallel side ready for RDIDR
- TRstart : Start of running main S.M,
the following registers shall be cleared on TRstart :
> RDext[31:0],
> WDext0[7:0] ~ WDext3[7:0],
> SCNTR[4:0] (shift-counter),
> WDcnt[1:0] (counting data bytes of WRIDR)
> RDcnt[1:0] (counting data bytes of RDIDR)
*/
always @(posedge ICK or posedge RST) begin
if (RST) begin
Prdy_WA <= #`db 1'b0;
Prdy_WD <= #`db 1'b0;
Prdy_RD <= #`db 1'b0;
end
else begin
Prdy_WA <= #`db (CS == 4'h3) && (NS == 4'h6);
Prdy_WD <= #`db (CS == 4'h4) && (NS == 4'h6);
Prdy_RD <= #`db (CS == 4'h2) && (NS == 4'h7);
end
end
assign #`da TRstart = (CS == 4'h1) && (NS == 4'h2);
always @(posedge ICK or posedge RST) begin
if (RST) Busy <= #`db 1'b0;
else if ((NS == 1) || (NS == 9)) Busy <= #`db 1'b1;
else if ((NS == 0) || (NS == 8)) Busy <= #`db 1'b0;
end
always @(posedge ICK) if (TRstart) CMD[7:0] <= #`db PPD[7:0];
assign #`d0 WDexts = {WDext3, WDext2, WDext1, WDext0}; // total 32-bit
assign #`da savWD = (CS == 4'h4) && (NS == 4'h5);
assign #`da savWD0 = savWD && (WDcnt == 2'h0);
assign #`da savWD1 = savWD && (WDcnt == 2'h1);
assign #`da savWD2 = savWD && (WDcnt == 2'h2);
assign #`da savWD3 = savWD && (WDcnt == 2'h3);
always @(posedge ICK)
if (TRstart) WDext0[7:0] <= #`db 8'h0;
else if (savWD0) WDext0[7:0] <= #`db PPD[7:0];
always @(posedge ICK)
if (TRstart) WDext1[7:0] <= #`db 8'h0;
else if (savWD1) WDext1[7:0] <= #`db PPD[7:0];
always @(posedge ICK)
if (TRstart) WDext2[7:0] <= #`db 8'h0;
else if (savWD2) WDext2[7:0] <= #`db PPD[7:0];
always @(posedge ICK)
if (TRstart) WDext3[7:0] <= #`db 8'h0;
else if (savWD3) WDext3[7:0] <= #`db PPD[7:0];
always @(posedge ICK) begin
if (TRstart) WDcnt[1:0] <= #`db 2'h0;
else if (savWD) WDcnt[1:0] <= #`db WDcnt +1;
end
// Parallel data bus (PPD[7:0] :
assign #`d0 PPD_oe = (CS == 4'h9);
assign #`da PPDo[7:0] = (RDcnt[1:0] == 2'h0) ? RDext[7:0] :
(RDcnt[1:0] == 2'h1) ? RDext[15:8] :
(RDcnt[1:0] == 2'h2) ? RDext[23:16] :
RDext[31:24] ;
assign #`da PPD[7:0] = PPD_oe? PPDo[7:0] : 8'bz;
assign #`da RDup = (CS == 4'h9) && (NS == 4'h8);
always @(posedge ICK) begin
if (TRstart) RDcnt[1:0] <= #`db 2'h0;
else if (RDup) RDcnt[1:0] <= #`db RDcnt +1;
end
WRIAR uwriar (/* In */ RST, ICK, Prdy_WA, eqLen,
/* Out */ WA_IMSi, WA_SCNTRup, WA_IDoe_h, WA_Srdy_h);
WRIDR uwridr (/* In */ RST, ICK, Prdy_WD, eqLen,
/* Out */ WD_IMSi, WD_SCNTRup, WD_IDoe_h, WD_Srdy_h);
RDIDR urdidr (/* In */ RST, ICK, Prdy_RD, eqLen,
/* Out */ RD_IMSi, RD_SCNTRup, savID, RD_Srdy_h);
assign #`da Sinc = WA_SCNTRup || WD_SCNTRup || RD_SCNTRup;
always @(posedge ICK) begin
if (TRstart) SCNTR[4:0] <= #`db 5'b0;
else if (Sinc) SCNTR[4:0] <= #`db SCNTR +1;
end
assign #`da eqLen = SCNTR[4:0] == (CMD[7] ? CMD[4:0] : 5'h3);
always @(negedge ICK) IMS <= #`db WA_IMSi && WD_IMSi && RD_IMSi;
always @(posedge ICK) ID_oe <= #`db WA_IDoe_h || WD_IDoe_h;
always @(negedge ICK) IDo <= #`db CMD[7] ? WDexts[SCNTR] // !WRIAR
: CMD[SCNTR[1:0]]; // WRIAR
assign #`da ID = ID_oe ? IDo : 1'bz;
always @(posedge ICK) begin
if (TRstart) RDext <= #`db 32'b0;
else if (savID) RDext <= #`db {RDext[30:0], ID};
end
// Srdy :
always @(posedge ICK or posedge RST) begin
if (RST) Srdy <= #`db 1'b0;
else Srdy <= #`db WA_Srdy_h || WD_Srdy_h || RD_Srdy_h;
end
//verisureon
endmodule
|
module WRIAR (/* In */ RST, ICK, Prdy, eqLen,
/* Out */ IMSi, SCNTRup, IDoe_h, Srdy_h);
input RST,
ICK,
Prdy,
eqLen;
output IMSi,
SCNTRup,
IDoe_h,
Srdy_h;
reg [2:0] CS, NS;
parameter Idle = 3'b0,
Start = 3'h1,
Sel_D = 3'h2,
Sel_A = 3'h3,
Sht_Ai = 3'h4,
Shtend = 3'h5,
DWR = 3'h6,
DRD = 3'h7;
always @(CS[2:0] or Prdy or eqLen) begin
NS <= #`da Idle;
case (CS)
Idle : NS <= #`da Prdy ? Start : Idle;
Start : NS <= #`da Sel_D;
Sel_D : NS <= #`da Sel_A;
Sel_A : NS <= #`da Sht_Ai;
Sht_Ai : NS <= #`da eqLen ? Shtend : Sht_Ai;
Shtend : NS <= #`da DWR;
DWR : NS <= #`da DRD;
DRD : NS <= #`da Idle;
endcase
end
assign #`da Srdy_h = (NS == DRD);
assign #`da IMSi = !((CS == Start) || (CS == Sel_A) || (CS == Sht_Ai));
// assign #`da Sht_en = (NS == Sel_A) || (NS == Sht_Ai);
assign #`da IDoe_h = (NS == Sel_A) || (NS == Sht_Ai) || (NS == Shtend);
// assign #`da ldSCNTR = (NS == Start);
assign #`da SCNTRup = (NS == Sht_Ai);
always @(posedge ICK or posedge RST) begin
if (RST) begin
// wrIARcyc <= #`db 1'b0;
CS <= #`db 3'b0;
end
else begin
// wrIARcyc <= #`db NS != Idle;
CS <= #`db NS;
end
end
endmodule
module WRIDR (/* In */ RST, ICK, Prdy, eqLen,
/* Out */ IMSi, SCNTRup, IDoe_h, Srdy_h);
input RST,
ICK,
Prdy,
eqLen;
output IMSi,
SCNTRup,
IDoe_h,
Srdy_h;
reg [2:0] CS, NS;
parameter Idle = 3'b0,
Start = 3'h1,
Sel_D = 3'h2,
DWR = 3'h3,
Sht_Di = 3'h4,
Shtend = 3'h5;
always @(CS[2:0] or Prdy or eqLen) begin
NS <= #`da Idle;
case (CS)
Idle : NS <= #`da Prdy ? Start : Idle;
Start : NS <= #`da Sel_D;
Sel_D : NS <= #`da DWR;
DWR : NS <= #`da Sht_Di;
Sht_Di : NS <= #`da eqLen ? Shtend : Sht_Di;
Shtend : NS <= #`da Idle;
endcase
end
assign #`da Srdy_h = (CS == Shtend);
assign #`da IMSi = (CS == Idle) || (CS == Shtend);
// assign #`da Sht_en = (NS == DWR) || (NS == Sht_Di);
assign #`da IDoe_h = (NS == DWR ) || (NS == Sht_Di) || (NS == Shtend);
// assign #`da ldSCNTR = (NS == Start);
assign #`da SCNTRup = (NS == Sht_Di);
/* --- State piping --- */
always @(posedge ICK or posedge RST) begin
if (RST) begin
// wrIDRcyc <= #`db 1'b0;
CS <= #`db 3'b0;
end
else begin
// wrIDRcyc <= #`db NS != Idle;
CS <= #`db NS;
end
end
endmodule
module RDIDR (/* In */ RST, ICK, Prdy, eqLen,
/* Out */ IMSi, SCNTRup, savID, Srdy_h);
input RST,
ICK,
Prdy,
eqLen;
output IMSi,
savID,
SCNTRup,
Srdy_h;
reg [2:0] CS, NS;
parameter Idle = 3'b0,
Start = 3'h1,
Sel_D = 3'h2,
DWR = 3'h3,
DRD1 = 3'h4,
Sht_Do = 3'h5,
Shtend = 3'h6,
DRD2 = 3'h7;
always @(CS[2:0] or Prdy or eqLen) begin
NS <= #`da Idle;
case (CS)
Idle : NS <= #`da Prdy ? Start : Idle;
Start : NS <= #`da Sel_D;
Sel_D : NS <= #`da DWR;
DWR : NS <= #`da DRD1;
DRD1 : NS <= #`da Sht_Do;
Sht_Do : NS <= #`da eqLen ? Shtend : Sht_Do;
Shtend : NS <= #`da DRD2;
DRD2 : NS <= #`da Idle;
endcase
end
assign #`da Srdy_h = (NS == DRD2);
assign #`da IMSi = !((CS == Start) || (CS == Sel_D) ||
(CS == DRD1) || (CS == Sht_Do));
assign #`da savID = (NS == Sht_Do) || (NS == Shtend);
// assign #`da ldSCNTR = (NS == Start);
assign #`da SCNTRup = (NS == Sht_Do);
always @(posedge ICK or posedge RST) begin
if (RST) begin
// rdIDRcyc <= #`db 1'b0;
CS <= #`db 3'b0;
end
else begin
// rdIDRcyc <= #`db NS != Idle;
CS <= #`db NS;
end
end
endmodule
|
`include "../include/x_def.v"
module IDMA (/* -------- Inputs : --------- */
X_IRDn, X_IWRn, X_ISn, X_IAL, X_BMODE, X_MMAP,
selECM, PM_bdry_sel,
STBY, Awake_h,
T_RSTn, GRST, DSPCLK, GO_Fx, GO_Ex, IDLE_ST_h,
ICE_ST_h, ICE_ST, DMDin,PMOVL_dsp,
DMOVL_dsp, CMAin, redoIF_h,
DWWAIT, DRWAIT, DCTL_wei, DOVL_wei,
MMR_web,
STEAL, DSack, DSreqx,
IDR, accCM_R, accCM_E, wrCM_R,
BDMA_end, BDMA_boot, BCMRD_cyc,
BOVL, BRdataBUF, BCM_cyc,
BSreqx, BM_cyc, ECYC,
`ifdef FD_DFT
SCAN_TEST,
`endif
IACKn,
BOOT, DCTL, DOVL,
PMOVL, DMOVL,
idmaDMD_oe, idmaPMD_oe, idmaPMD_do,
DSreq, DWRcyc, PWRcyc, DRDcyc, PRDcyc,
CM_cs, CM_web, CM_oe,
CMo_cs0, CMo_cs1, CMo_cs2, CMo_cs3, CMo_cs4,
CMo_cs5, CMo_cs6, CMo_cs7,
CMo_oe0, CMo_oe1, CMo_oe2, CMo_oe3,
CMo_oe4, CMo_oe5, CMo_oe6, CMo_oe7,
T_IAD, IAD_do, IAD_oe,
PMDin, CM_rd, CM_wd,
GO_STEAL);
input [23:0] BRdataBUF;
input [11:0] BOVL;
input BDMA_end,
BDMA_boot,
BCMRD_cyc,
BCM_cyc,
BSreqx,
BM_cyc,
ECYC,
PM_bdry_sel;
input [13:12] CMAin;
input [15:0] DMDin,
T_IAD;
input [7:0] PMOVL_dsp;
input [3:0] DMOVL_dsp;
input [2:0] DWWAIT,
DRWAIT;
input [23:0] IDR;
input T_RSTn,
GRST,
DSPCLK,
selECM,
STBY,
Awake_h,
X_BMODE,
X_MMAP,
X_IRDn,
X_IWRn,
X_ISn,
X_IAL,
redoIF_h,
GO_Fx,
GO_Ex,
IDLE_ST_h,
ICE_ST_h,
ICE_ST,
DCTL_wei,
DOVL_wei,
STEAL,
DSack,
DSreqx,
accCM_R, accCM_E,
wrCM_R,
MMR_web;
`ifdef FD_DFT
input SCAN_TEST;
`endif
output [15:0] idmaPMD_do,
IAD_do;
output [14:0] DCTL;
output [11:0] DOVL;
output [3:0] PMOVL,
DMOVL;
output BOOT,
IACKn,
DSreq,
DWRcyc,
PWRcyc,
DRDcyc,
PRDcyc,
CM_web,
CM_oe,
CMo_oe0, CMo_oe1,
CMo_oe2, CMo_oe3,
CMo_oe4, CMo_oe5,
CMo_oe6, CMo_oe7,
CM_cs,
CMo_cs0, CMo_cs1,
CMo_cs2, CMo_cs3,
CMo_cs4, CMo_cs5,
CMo_cs6, CMo_cs7,
idmaDMD_oe,
idmaPMD_oe,
IAD_oe,
GO_STEAL;
input [23:0] CM_rd;
output [23:0] CM_wd;
input [15:0] PMDin;
reg [2:0] RDcnt, WRcnt;
reg [7:0] DTMP_L;
reg [14:0] DCTL;
reg [11:0] DOVL;
reg [15:0] IADi, DTMP_H;
reg ISn, IAL, IRDn, IWRn, IACKn, PM_1st,
PCrd_1st, RDcyc, WRcyc, DSreq, WRtrue,
RDCMD, WRCMD, RDCMD_d1, WRCMD_d1, IDMA_boot;
wire [3:0] CMOVL;
wire [7:0] DTMP_Ldi;
wire [14:0] DCTL_di;
wire [11:0] DOVL_di;
wire [15:0] DTMP_Hdi;
wire [13:0] IDMAA;
wire GO_CMA;
wire RDendi, WRendi, RDend, WRend, PCRDcyc, PRDcyc,
CWRcyc, CRDcyc, DRDcyc, PCWRcyc, DWRcyc, sPM_1st,
tPM_1st, tPCrd_1st, RDcnteq0, WRcnteq0, DCTL_we,
DOVL_we, ldDCTL_ext, ldDOVL_ext, IDMcyc,
sDSreq, ldRDcnt, dnRDcnt, ldWRcnt, dnWRcnt,
ldDTMP_ext, upDCTL, ldDTMP_H, ldDTMP_L, selPM,
selCM, CM_we_h, RDbeg, WRbeg, GO_STEAL, GO_DSreq,
PCrd_end, IDMA_end;
wire CMcs_en, CMcs_nx, CMcs0_nx, CMcs1_nx, CMcs2_nx,
CMcs3_nx, CMcs4_nx, CMcs5_nx, CMcs6_nx, CMcs7_nx, GO_CMcs, REGCLK,
DMACLK;
`ifdef FD_GTCLK
GTECH_NOT uck0 (.Z(MMR_we), .A(MMR_web));
GtCLK_NOR3 uck1 (.Z(REGCLK_enb), .A(IAL), .B(IACKn), .C(MMR_we));
GTECH_NOT uck3 (.Z(IACKn_), .A(IACKn));
GtCLK_AND3 uck4 (.Z(DMACLK_enb), .A(IRDn), .B(IWRn), .C(IACKn_));
`ifdef FD_DFT
GTECH_AND_NOT utm0 (.Z(REGCLK_enb_dft), .A(REGCLK_enb), .B(SCAN_TEST));
GTECH_NOR2 uck2 (.Z(REGCLK_), .A(DSPCLK), .B(REGCLK_enb_dft));
GTECH_AND_NOT utm1 (.Z(DMACLK_enb_dft), .A(DMACLK_enb), .B(SCAN_TEST));
GTECH_NOR2 uck5 (.Z(DMACLK_), .A(DSPCLK), .B(DMACLK_enb_dft));
`else
GTECH_NOR2 uck2 (.Z(REGCLK_), .A(DSPCLK), .B(REGCLK_enb));
GTECH_NOR2 uck5 (.Z(DMACLK_), .A(DSPCLK), .B(DMACLK_enb));
`endif
GtCLK_NOT ckREGCLK (.Z(REGCLK), .A(REGCLK_));
GtCLK_NOT ckDMACLK (.Z(DMACLK), .A(DMACLK_));
`else
wire REGCLK_en = !(!IAL && !IACKn && MMR_web);
wire DMACLK_en = !(IRDn && IWRn && !IACKn);
assign #`da REGCLK = DSPCLK ;
assign #`da DMACLK = DSPCLK ;
`endif
always @(posedge DSPCLK)
if (!X_ISn) IADi[15:0] <= #`db T_IAD[15:0];
`ifdef FD_DFT
reg RST_pin_h, RST_h;
wire RST_pin, RST;
always @(posedge DSPCLK) RST_pin_h <= #`db !T_RSTn;
always @(posedge DSPCLK) RST_h <= #`db GRST;
assign RST_pin = SCAN_TEST ? !T_RSTn : RST_pin_h;
assign RST = SCAN_TEST ? GRST : RST_h;
`else
reg RST_pin, RST;
always @(posedge DSPCLK) RST_pin <= #`db !T_RSTn;
always @(posedge DSPCLK) RST <= #`db GRST;
`endif
always @(posedge DSPCLK) begin
ISn <= #`db X_ISn;
IAL <= #`db X_IAL;
IRDn <= #`db X_IRDn;
IWRn <= #`db X_IWRn;
end
always @(posedge DSPCLK) begin
RDCMD <= #`db !(X_ISn || X_IRDn);
WRCMD <= #`db !(X_ISn || X_IWRn);
RDCMD_d1 <= #`db RDCMD;
WRCMD_d1 <= #`db WRCMD;
end
assign #`da RDbeg = RDCMD && !RDCMD_d1;
assign #`da WRbeg = WRCMD && !WRCMD_d1;
assign #`da PCrd_end = !RDCMD && RDCMD_d1;
always @(posedge DSPCLK or posedge RST) begin
if (RST) IACKn <= #`db 1'b0;
else begin
if (RDbeg || WRbeg) IACKn <= #`db 1'b1;
if (RDend || WRend) IACKn <= #`db 1'b0;
end
end
assign #`da IAD_do[15:0]
= ICE_ST ? 16'ha4a4 : (IDMcyc || PCrd_1st) ? DTMP_H[15:0] : {8'b0, DTMP_L[7:0]};
assign #`da IAD_oe = RDCMD || RDcyc;
assign #`da ldDCTL_ext = IAL && !ISn && !IADi[15];
assign #`da ldDOVL_ext = IAL && !ISn && IADi[15];
assign #`da DCTL_we = ldDCTL_ext || DCTL_wei;
assign #`da DOVL_we = ldDOVL_ext || DOVL_wei;
assign #`da upDCTL = (RDend || WRend) && (IDMcyc || !PM_1st);
assign #`da DCTL_di[14:0] = IAL ? IADi[14:0] : DMDin[14:0];
assign #`da DOVL_di[11:0] = IAL ? IADi[11:0] : DMDin[11:0];
always @(posedge REGCLK or posedge RST) begin
if (RST) DCTL[14] <= #`db 1'b0;
`ifdef FD_GTCLK
else if (DCTL_we) DCTL[14] <= #`db DCTL_di[14];
`else
else if (DCTL_we & REGCLK_en) DCTL[14] <= #`db DCTL_di[14];
`endif
end
always @(posedge REGCLK or posedge RST) begin
if (RST) DCTL[13:0] <= #`db 14'b0;
`ifdef FD_GTCLK
else if (DCTL_we) DCTL[13:0] <= #`db DCTL_di[13:0];
else if (upDCTL) DCTL[13:0] <= #`db DCTL[13:0] + 1;
`else
else if (DCTL_we & REGCLK_en) DCTL[13:0] <= #`db DCTL_di[13:0];
else if (upDCTL & REGCLK_en) DCTL[13:0] <= #`db DCTL[13:0] + 1;
`endif
end
assign #`d0 IDMcyc = DCTL[14];
assign #`d0 IDMAA[13:0] = DCTL[13:0];
always @(posedge REGCLK or posedge RST) begin
if (RST) DOVL[11:0] <= #`db 12'b0;
`ifdef FD_GTCLK
else if (DOVL_we) DOVL[11:0] <= #`db DOVL_di[11:0];
`else
else if (DOVL_we & REGCLK_en) DOVL[11:0] <= #`db DOVL_di[11:0];
`endif
end
assign #`da RDendi = !(IDMcyc || PM_1st) ? RDcnteq0
: DSack;
assign #`da RDend = RDendi && RDcyc;
always @(posedge DSPCLK or posedge RST) begin
if (RST) RDcyc <= #`db 1'b0;
else if (RDbeg) RDcyc <= #`db 1'b1;
else if (RDendi) RDcyc <= #`db 1'b0;
end
assign #`da DRDcyc = RDcyc && IDMcyc;
assign #`da PCRDcyc = RDcyc && !IDMcyc;
assign #`da PRDcyc = PCRDcyc && selPM;
assign #`da CRDcyc = PCRDcyc && selCM;
assign #`da ldRDcnt = RDbeg && !IDMcyc && !PM_1st;
assign #`da dnRDcnt = PCRDcyc && !PM_1st;
always @(posedge DMACLK or posedge RST) begin
if (RST) RDcnt[2:0] <= #`db 3'h7;
`ifdef FD_GTCLK
else if (ldRDcnt) RDcnt[2:0] <= #`db DRWAIT[2:0];
else if (dnRDcnt) RDcnt[2:0] <= #`db RDcnt - 1;
`else
else if (ldRDcnt & DMACLK_en) RDcnt[2:0] <= #`db DRWAIT[2:0];
else if (dnRDcnt & DMACLK_en) RDcnt[2:0] <= #`db RDcnt - 1;
`endif
end
assign #`da RDcnteq0 = (RDcnt[2:0] == 3'b0);
assign #`da WRendi = !IDMcyc && PM_1st ? WRcnteq0
: DSack;
assign #`da WRend = WRendi && WRcyc;
always @(posedge DSPCLK or posedge RST) begin
if (RST) WRcyc <= #`db 1'b0;
else if (WRbeg) WRcyc <= #`db 1'b1;
else if (WRendi) WRcyc <= #`db 1'b0;
end
assign #`da DWRcyc = WRcyc && IDMcyc;
assign #`da PCWRcyc = WRcyc && !IDMcyc;
assign #`da PWRcyc = PCWRcyc && selPM;
assign #`da CWRcyc = PCWRcyc && selCM;
assign #`da ldDTMP_ext = WRtrue && !ISn && !IWRn;
always @(posedge DSPCLK or posedge RST) begin
if (RST) WRtrue <= #`db 1'b0;
else if (WRbeg) WRtrue <= #`db 1'b1;
else if (WRcnteq0) WRtrue <= #`db 1'b0;
end
assign #`da ldWRcnt = WRbeg;
assign #`da dnWRcnt = WRtrue;
always @(posedge DMACLK or posedge RST) begin
if (RST) WRcnt[2:0] <= #`db 3'h7;
`ifdef FD_GTCLK
else if (ldWRcnt) WRcnt[2:0] <= #`db DWWAIT[2:0];
else if (dnWRcnt) WRcnt[2:0] <= #`db WRcnt - 1;
`else
else if (ldWRcnt & DMACLK_en) WRcnt[2:0] <= #`db DWWAIT[2:0];
else if (dnWRcnt & DMACLK_en) WRcnt[2:0] <= #`db WRcnt - 1;
`endif
end
assign #`da WRcnteq0 = (WRcnt[2:0] == 3'b0);
assign #`da ldDTMP_H = (RDend || ldDTMP_ext) && (IDMcyc || PM_1st);
assign #`da DTMP_Hdi[15:0]
= DRDcyc ? DMDin[15:0] :
PRDcyc ? PMDin[15:0] :
CRDcyc ? CM_rd[23:8]
: IADi[15:0];
always @(posedge DSPCLK)
if (ldDTMP_H) DTMP_H[15:0] <= #`db DTMP_Hdi[15:0];
assign #`da ldDTMP_L = !IDMcyc && (PM_1st ? RDend : ldDTMP_ext);
assign #`da DTMP_Ldi[7:0]
= PRDcyc ? 8'b0 :
CRDcyc ? CM_rd[7:0]
: IADi[7:0];
always @(posedge DMACLK)
`ifdef FD_GTCLK
if (ldDTMP_L) DTMP_L[7:0] <= #`db DTMP_Ldi[7:0];
`else
if (ldDTMP_L & DMACLK_en) DTMP_L[7:0] <= #`db DTMP_Ldi[7:0];
`endif
assign #`da IDMA_end = (IDMAA == 14'b0) && WRend && !(IDMcyc || PM_1st);
always @(posedge DSPCLK or posedge RST_pin) begin
if (RST_pin) IDMA_boot <= #`db !X_MMAP && X_BMODE;
else if (IDMA_end) IDMA_boot <= #`db 1'b0;
end
assign #`da BOOT = BDMA_boot || IDMA_boot;
assign #`da sPM_1st = DCTL_we || DOVL_we;
assign #`da tPM_1st = (WRend || RDend) && !IDMcyc;
always @(posedge DSPCLK or posedge RST) begin
if (RST) PM_1st <= #`db 1'b1;
else if (sPM_1st) PM_1st <= #`db 1'b1;
else if (tPM_1st) PM_1st <= #`db !PM_1st;
end
assign #`da tPCrd_1st = PCrd_end && !IDMcyc;
always @(posedge DSPCLK or posedge RST) begin
if (RST) PCrd_1st <= #`db 1'b1;
else if (sPM_1st) PCrd_1st <= #`db 1'b1;
else if (tPCrd_1st) PCrd_1st <= #`db !PCrd_1st;
end
Delaya d1 (DSack, delDSack);
assign #`da sDSreq = RDbeg && IDMcyc ||
RDbeg && !IDMcyc && PM_1st ||
WRcnteq0 && DWRcyc ||
WRcnteq0 && PCWRcyc && !PM_1st;
`ifdef FD_DFT
wire rDSreq_h = (RST || delDSack);
wire rDSreq = SCAN_TEST ? RST : rDSreq_h;
`else
wire rDSreq = RST || delDSack;
`endif
always @(posedge DSPCLK or posedge rDSreq) begin
if (rDSreq) DSreq <= #`db 1'b0;
else if (sDSreq) DSreq <= #`db 1'b1;
end
assign #`da GO_DSreq = DSreqx & GO_STEAL;
assign #`da CMOVL[3:0] = GO_DSreq ? DOVL[3:0] :
BSreqx ? BOVL[3:0] : PMOVL_dsp[3:0];
assign #`da PMOVL[3:0] = GO_DSreq ? DOVL[11:8] :
BSreqx ? BOVL[11:8] : PMOVL_dsp[7:4];
assign #`da DMOVL[3:0] = GO_DSreq ? DOVL[7:4] :
BSreqx ? BOVL[7:4] : DMOVL_dsp[3:0];
assign #`da GO_STEAL = GO_Ex || STEAL || BOOT || STBY || BM_cyc && ECYC;
assign #`da idmaDMD_oe = DSreqx && DWRcyc && GO_STEAL;
assign #`da idmaPMD_oe = DSreqx && PWRcyc && GO_STEAL;
assign #`d0 idmaPMD_do[15:0] = DTMP_H[15:0];
`ifdef FD_DFT
assign #`da CMcs_en = !(IDLE_ST_h && !Awake_h && !(DSreqx || BSreqx) ||
ICE_ST_h && !(accCM_R || accCM_E))
&& !selECM && !SCAN_TEST;
`else
assign #`da CMcs_en = !(IDLE_ST_h && !Awake_h && !(DSreqx || BSreqx) ||
ICE_ST_h && !(accCM_R || accCM_E))
&& !selECM ;
`endif
assign #`da GO_CMA = GO_Fx || STEAL || STBY || BOOT || redoIF_h || BM_cyc && ECYC;
assign #`da GO_CMcs = GO_CMA || IDLE_ST_h || ICE_ST_h;
wire CM_rgn, CMo_rgn;
assign #`da CM_rgn = PM_bdry_sel ? (CMAin[13:12] == 2'b00) :
(CMAin[13] == 1'b0);
assign #`da CMo_rgn = PM_bdry_sel ? (CMAin[13:12] == 2'b01) :
(CMAin[13:12] == 2'b10);
assign #`da CMcs_nx = CM_rgn && CMcs_en;
assign #`da CMcs0_nx = (CMo_rgn && (CMOVL[3:0] == 4'h0)) && CMcs_en;
assign #`da CMcs1_nx = (CMo_rgn && (CMOVL[3:0] == 4'h1)) && CMcs_en;
assign #`da CMcs2_nx = (CMo_rgn && (CMOVL[3:0] == 4'h2)) && CMcs_en;
assign #`da CMcs3_nx = (CMo_rgn && (CMOVL[3:0] == 4'h3)) && CMcs_en;
assign #`da CMcs4_nx = (CMo_rgn && (CMOVL[3:0] == 4'h4)) && CMcs_en;
assign #`da CMcs5_nx = (CMo_rgn && (CMOVL[3:0] == 4'h5)) && CMcs_en;
assign #`da CMcs6_nx = (CMo_rgn && (CMOVL[3:0] == 4'h6)) && CMcs_en;
assign #`da CMcs7_nx = (CMo_rgn && (CMOVL[3:0] == 4'h7)) && CMcs_en;
assign #`da CM_cs = CMcs_nx && GO_CMcs ;
assign #`da CMo_cs0 = CMcs0_nx && GO_CMcs ;
assign #`da CMo_cs1 = CMcs1_nx && GO_CMcs ;
assign #`da CMo_cs2 = CMcs2_nx && GO_CMcs ;
assign #`da CMo_cs3 = CMcs3_nx && GO_CMcs ;
assign #`da CMo_cs4 = CMcs4_nx && GO_CMcs ;
assign #`da CMo_cs5 = CMcs5_nx && GO_CMcs ;
assign #`da CMo_cs6 = CMcs6_nx && GO_CMcs ;
assign #`da CMo_cs7 = CMcs7_nx && GO_CMcs ;
reg CM_oe, CMo_oe0, CMo_oe1, CMo_oe2, CMo_oe3,
CMo_oe4, CMo_oe5, CMo_oe6, CMo_oe7;
always @(posedge DSPCLK)
begin
CM_oe <=#`db CMcs_nx && GO_CMcs;
CMo_oe0 <=#`db CMcs0_nx && GO_CMcs;
CMo_oe1 <=#`db CMcs1_nx && GO_CMcs;
CMo_oe2 <=#`db CMcs2_nx && GO_CMcs;
CMo_oe3 <=#`db CMcs3_nx && GO_CMcs;
CMo_oe4 <=#`db CMcs4_nx && GO_CMcs;
CMo_oe5 <=#`db CMcs5_nx && GO_CMcs;
CMo_oe6 <=#`db CMcs6_nx && GO_CMcs;
CMo_oe7 <=#`db CMcs7_nx && GO_CMcs;
end
assign #`da CM_wd[23:0] = DSreqx ? {DTMP_H[15:0], DTMP_L[7:0]} :
BSreqx && BCMRD_cyc ? BRdataBUF[23:0] : IDR[23:0];
assign #`da CM_we_h = ICE_ST_h ? wrCM_R && GO_Ex
: GO_STEAL && (selCM && DSreqx && CWRcyc ||
BCMRD_cyc && BSreqx );
assign #`d0 CM_web = !CM_we_h;
assign #`da selCM = PM_bdry_sel ? (IDMAA[13] == 1'b0) :
!(IDMAA[13:12] == 2'b11);
assign #`da selPM = PM_bdry_sel ? (IDMAA[13] == 1'b1) :
(IDMAA[13:12] == 2'b11);
endmodule
|
module CM4k (datai[23:0], datao[23:0], addr[13:0], cs, web, oe, ck);
output [23:0] datao;
input [23:0] datai;
input [13:0] addr;
input cs,
web,
oe,
ck;
SH208018 I ( .A0(addr[0]),
.A1(addr[1]),
.A2(addr[2]),
.A3(addr[3]),
.A4(addr[4]),
.A5(addr[5]),
.A6(addr[6]),
.A7(addr[7]),
.A8(addr[8]),
.A9(addr[9]),
.A10(addr[10]),
.A11(addr[11]),
.CK(ck),
.CS(cs),
.DI0(datai[0]),
.DI1(datai[1]),
.DI2(datai[2]),
.DI3(datai[3]),
.DI4(datai[4]),
.DI5(datai[5]),
.DI6(datai[6]),
.DI7(datai[7]),
.DI8(datai[8]),
.DI9(datai[9]),
.DI10(datai[10]),
.DI11(datai[11]),
.DI12(datai[12]),
.DI13(datai[13]),
.DI14(datai[14]),
.DI15(datai[15]),
.DI16(datai[16]),
.DI17(datai[17]),
.DI18(datai[18]),
.DI19(datai[19]),
.DI20(datai[20]),
.DI21(datai[21]),
.DI22(datai[22]),
.DI23(datai[23]),
.DO0(datao[0]),
.DO1(datao[1]),
.DO2(datao[2]),
.DO3(datao[3]),
.DO4(datao[4]),
.DO5(datao[5]),
.DO6(datao[6]),
.DO7(datao[7]),
.DO8(datao[8]),
.DO9(datao[9]),
.DO10(datao[10]),
.DO11(datao[11]),
.DO12(datao[12]),
.DO13(datao[13]),
.DO14(datao[14]),
.DO15(datao[15]),
.DO16(datao[16]),
.DO17(datao[17]),
.DO18(datao[18]),
.DO19(datao[19]),
.DO20(datao[20]),
.DO21(datao[21]),
.DO22(datao[22]),
.DO23(datao[23]),
.OE(oe),
.WEB(web)
);
endmodule
|
module CM8k (datai[23:0], datao[23:0], addr[13:0], cs, web, oe, ck);
output [23:0] datao;
input [23:0] datai;
input [13:0] addr;
input cs,
web,
oe,
ck;
SH210018 I( .A0(addr[0]),
.A1(addr[1]),
.A2(addr[2]),
.A3(addr[3]),
.A4(addr[4]),
.A5(addr[5]),
.A6(addr[6]),
.A7(addr[7]),
.A8(addr[8]),
.A9(addr[9]),
.A10(addr[10]),
.A11(addr[11]),
.A12(addr[12]),
.CK(ck),
.CS(cs),
.DI0(datai[0]),
.DI1(datai[1]),
.DI2(datai[2]),
.DI3(datai[3]),
.DI4(datai[4]),
.DI5(datai[5]),
.DI6(datai[6]),
.DI7(datai[7]),
.DI8(datai[8]),
.DI9(datai[9]),
.DI10(datai[10]),
.DI11(datai[11]),
.DI12(datai[12]),
.DI13(datai[13]),
.DI14(datai[14]),
.DI15(datai[15]),
.DI16(datai[16]),
.DI17(datai[17]),
.DI18(datai[18]),
.DI19(datai[19]),
.DI20(datai[20]),
.DI21(datai[21]),
.DI22(datai[22]),
.DI23(datai[23]),
.DO0(datao[0]),
.DO1(datao[1]),
.DO2(datao[2]),
.DO3(datao[3]),
.DO4(datao[4]),
.DO5(datao[5]),
.DO6(datao[6]),
.DO7(datao[7]),
.DO8(datao[8]),
.DO9(datao[9]),
.DO10(datao[10]),
.DO11(datao[11]),
.DO12(datao[12]),
.DO13(datao[13]),
.DO14(datao[14]),
.DO15(datao[15]),
.DO16(datao[16]),
.DO17(datao[17]),
.DO18(datao[18]),
.DO19(datao[19]),
.DO20(datao[20]),
.DO21(datao[21]),
.DO22(datao[22]),
.DO23(datao[23]),
.OE(oe),
.WEB(web)
);
endmodule
|
module DM8k (datai[15:0], datao[15:0], addr[13:0], cs, web, oe, ck);
output [15:0] datao;
input [15:0] datai;
input [13:0] addr;
input cs,
web,
oe,
ck;
SH308010 I0( .A0(addr[0]),
.A1(addr[1]),
.A2(addr[2]),
.A3(addr[3]),
.A4(addr[4]),
.A5(addr[5]),
.A6(addr[6]),
.A7(addr[7]),
.A8(addr[8]),
.A9(addr[9]),
.A10(addr[10]),
.A11(addr[11]),
.A12(addr[12]),
.CK(ck),
.CS(cs),
.DI0(datai[0]),
.DI1(datai[1]),
.DI2(datai[2]),
.DI3(datai[3]),
.DI4(datai[4]),
.DI5(datai[5]),
.DI6(datai[6]),
.DI7(datai[7]),
.DI8(datai[8]),
.DI9(datai[9]),
.DI10(datai[10]),
.DI11(datai[11]),
.DI12(datai[12]),
.DI13(datai[13]),
.DI14(datai[14]),
.DI15(datai[15]),
.DO0(datao[0]),
.DO1(datao[1]),
.DO2(datao[2]),
.DO3(datao[3]),
.DO4(datao[4]),
.DO5(datao[5]),
.DO6(datao[6]),
.DO7(datao[7]),
.DO8(datao[8]),
.DO9(datao[9]),
.DO10(datao[10]),
.DO11(datao[11]),
.DO12(datao[12]),
.DO13(datao[13]),
.DO14(datao[14]),
.DO15(datao[15]),
.OE(oe),
.WEB(web)
);
endmodule
|
module ECM32kx24 (data[23:0], addr[14:0], cs_, we_, oe_);
inout [23:0] data;
input [14:0] addr;
input cs_,
we_,
oe_;
parameter taa=10;
reg [23:0] cells['h7fff:0];
wire WR = cs_ | we_;
wire OE = !(cs_ | oe_);
initial begin : initialize
integer i;
for (i=0; i<='h7fff; i=i+1)
cells[i] = 24'h0;
end
always @(posedge WR) cells[addr] = data;
assign #taa data = OE ? cells[addr] : 24'hz;
wire [23:0] ecm000 = cells[0];
wire [23:0] ecm001 = cells[1];
wire [23:0] ecm002 = cells[2];
wire [23:0] ecm003 = cells[3];
endmodule
|
module EDM8k (data[15:0], addr[12:0], cs_, we_, oe_);
inout [15:0] data;
input [12:0] addr;
input cs_,
we_,
oe_;
reg [15:0] cells[13'h1fff:13'h0];
wire WR = cs_ | we_;
wire OE = !(cs_ | oe_);
initial begin : initialize
integer i;
for (i=13'h0; i<=13'h1fff; i=i+1)
cells[i] = 16'h0;
end
always @(posedge WR) cells[addr] = data;
assign data = OE ? cells[addr] : 16'hz;
wire [15:0] edm1000 = cells[13'h0bd0];
wire [15:0] edm1001 = cells[13'h0bd1];
wire [15:0] edm1002 = cells[13'h0bd2];
wire [15:0] edm1003 = cells[13'h0bd3];
endmodule
|
module EEPROM ( A[17:0], IO[7:0], CEn, OEn, WEn );
input [17:0] A;
input OEn, CEn, WEn;
inout [7:0] IO;
reg [7:0] cells [262143:0];
reg [262143:0] Ai;
reg [7:0] DO;
assign IO = !(CEn || OEn) ? DO : 8'bz;
always @( A[17:0] or OEn or CEn)
if (!(OEn || CEn))
DO <= #25 cells[A];
always @(posedge WEn)
if ((OEn == 1'b1) && (CEn == 1'b0))
cells[A] <= IO[7:0];
wire [7:0] mem0 = cells['h220];
wire [7:0] mem1 = cells['h221];
wire [7:0] mem2 = cells['h222];
wire [7:0] mem3 = cells['h200];
wire [7:0] mem4 = cells['h191];
wire [7:0] mem5 = cells['h192];
endmodule
|
module EIO2k (data[15:0], addr[10:0], cs_, we_, oe_);
inout [15:0] data;
input [10:0] addr;
input cs_,
we_,
oe_;
reg [15:0] cells[11'h7ff : 11'h0];
wire WR = cs_ | we_;
wire OE = !(cs_ | oe_);
initial begin : initialize
integer i;
for (i=11'h0; i<=11'h7ff; i=i+1)
cells[i] = 16'h0;
end
always @(posedge WR) cells[addr] = data;
assign data = OE ? cells[addr] : 16'hz;
endmodule
|
module EM4K (data[15:0], addr[11:0], cs_, we_, oe_);
inout [15:0] data;
input [11:0] addr;
input cs_,
we_,
oe_;
reg [15:0] cells[14'h0fff:14'h0];
wire WR = cs_ | we_;
wire OE = !(cs_ | oe_);
initial begin : initialize
integer i;
for (i=14'h0; i<=14'hfff; i=i+1)
cells[i] = 16'h0;
end
always @(posedge WR) cells[addr] = data;
assign data = OE ? cells[addr] : 16'hz;
wire [15:0] epm0 = cells[14'h30];
wire [15:0] epm1 = cells[14'h31];
wire [15:0] epm2 = cells[14'h32];
wire [15:0] epm3 = cells[14'h33];
endmodule
|
module EM8K (data[15:0], addr[12:0], cs_, we_, oe_);
inout [15:0] data;
input [12:0] addr;
input cs_,
we_,
oe_;
reg [15:0] cells[13'h1fff:13'h0];
wire WR = cs_ | we_;
wire OE = !(cs_ | oe_);
initial begin : initialize
integer i;
for (i=13'h0; i<=13'h1fff; i=i+1)
cells[i] = 16'h0;
end
always @(posedge WR) cells[addr] = data;
assign data = OE ? cells[addr] : 16'hz;
wire [15:0] edm1000 = cells[13'h0bd0];
wire [15:0] edm1001 = cells[13'h0bd1];
wire [15:0] edm1002 = cells[13'h0bd2];
wire [15:0] edm1003 = cells[13'h0bd3];
endmodule
|
module PM4k (datai[15:0], datao[15:0], addr[13:0], cs, web, oe, ck);
output [15:0] datao;
input [15:0] datai;
input [13:0] addr;
input cs,
web,
oe,
ck;
SH304010 I0( .A0(addr[0]),
.A1(addr[1]),
.A2(addr[2]),
.A3(addr[3]),
.A4(addr[4]),
.A5(addr[5]),
.A6(addr[6]),
.A7(addr[7]),
.A8(addr[8]),
.A9(addr[9]),
.A10(addr[10]),
.A11(addr[11]),
.CK(ck),
.CS(cs),
.DI0(datai[0]),
.DI1(datai[1]),
.DI2(datai[2]),
.DI3(datai[3]),
.DI4(datai[4]),
.DI5(datai[5]),
.DI6(datai[6]),
.DI7(datai[7]),
.DI8(datai[8]),
.DI9(datai[9]),
.DI10(datai[10]),
.DI11(datai[11]),
.DI12(datai[12]),
.DI13(datai[13]),
.DI14(datai[14]),
.DI15(datai[15]),
.DO0(datao[0]),
.DO1(datao[1]),
.DO2(datao[2]),
.DO3(datao[3]),
.DO4(datao[4]),
.DO5(datao[5]),
.DO6(datao[6]),
.DO7(datao[7]),
.DO8(datao[8]),
.DO9(datao[9]),
.DO10(datao[10]),
.DO11(datao[11]),
.DO12(datao[12]),
.DO13(datao[13]),
.DO14(datao[14]),
.DO15(datao[15]),
.OE(oe),
.WEB(web)
);
endmodule
|
`include "../include/x_def.v"
module GtCLK_OR_NOT ( Z, A, B );
input A, B;
output Z;
GTECH_OR_NOT Gtclk1 (.Z(Z), .B(B), .A(A));
endmodule
module GtCLK_NOT ( Z, A );
input A;
output Z;
GTECH_NOT Gtclk1 (.Z(Z), .A(A));
endmodule
module GtCLK_AND3 ( Z, A, B, C );
input A, B, C;
output Z;
GTECH_AND3 Gtclk1 (.Z(Z), .A(A), .B(B), .C(C));
endmodule
module GtCLK_BUF ( Z, A );
input A;
output Z;
GTECH_BUF Gtclk1 (.Z(Z), .A(A));
endmodule
module GtCLK_NOR3 ( Z, A, B, C );
input A, B, C;
output Z;
GTECH_NOR3 Gtclk1 (.Z(Z), .A(A), .B(B), .C(C));
endmodule
module GtCLK_NOR2 ( Z, A, B );
input A, B;
output Z;
GTECH_NOR2 Gtclk1 (.Z(Z), .A(A), .B(B));
endmodule
module GtCLK_MUX2 ( Z, A, B, S );
input A, B, S;
output Z;
GTECH_MUX2 Gtclk1 (.Z(Z), .S(S), .A(A), .B(B));
endmodule
module GtCLK_OA21 ( Z, A, B, C );
input A, B, C;
output Z;
GTECH_OA21 Gtclk1 (.Z(Z), .C(C), .A(A), .B(B));
endmodule
module GtCLK_OR2 ( Z, A, B );
input A, B;
output Z;
GTECH_OR2 Gtclk1 (.Z(Z), .A(A), .B(B));
endmodule
module GtCLK_NAND2 ( Z, A, B );
input A, B;
output Z;
GTECH_NAND2 Gtclk1 (.Z(Z), .A(A), .B(B));
endmodule
module GtCLK_NAND3 ( Z, A, B, C );
input A, B, C;
output Z;
GTECH_NAND3 Gtclk1 (.Z(Z), .A(A), .B(B), .C(C));
endmodule
module GtCLK_FJK3 ( Q, QN, CP, CD, SD, J, K);
input CP, CD, SD, J, K;
output Q, QN;
GTECH_FJK3 STDCLK_reg (.Q(Q), .QN(QN), .CP(CP), .CD(CD),
.SD(SD), .J(J), .K(K));
endmodule
|
`include "../include/x_def.v"
module DMDbuf (I, O);
input [15:0] I;
output [15:0] O;
assign O = I;
endmodule
module MAbufx (I, O);
input [13:0] I;
output [13:0] O;
assign O = I;
endmodule
`ifdef FD_DFT
module REG8L (CK, CKenb, WBen, DI, DO, SCAN_TEST);
input CK, CKenb, WBen, SCAN_TEST;
`else
module REG8L (CK, CKenb, WBen, DI, DO);
input CK, CKenb, WBen;
`endif
input [7:0] DI;
output [7:0] DO;
reg [7:0] DO;
`ifdef FD_GTCLK
`ifdef FD_DFT
GTECH_AND_NOT utm0 (.A(CKenb), .B(SCAN_TEST), .Z(CKenb_dft));
OR2LC uu0(.O(CLK), .I1(CK), .I2(CKenb_dft));
`else
OR2LC uu0(.O(CLK), .I1(CK), .I2(CKenb));
`endif
always @(posedge CLK)
if (WBen) DO[7:0] <= #`db DI[7:0];
`else
always @(posedge CK)
if (WBen && !CKenb) DO[7:0] <= #`db DI[7:0];
`endif
endmodule
`ifdef FD_DFT
module REG9L (CK, CKenb, WBen, DI, DO, SCAN_TEST);
input CK, CKenb, WBen, SCAN_TEST;
`else
module REG9L (CK, CKenb, WBen, DI, DO);
input CK, CKenb, WBen;
`endif
input [8:0] DI;
output [8:0] DO;
reg [8:0] DO;
`ifdef FD_GTCLK
`ifdef FD_DFT
GTECH_AND_NOT utm0 (.A(CKenb), .B(SCAN_TEST), .Z(CKenb_dft));
OR2LC uu0(.O(CLK), .I1(CK), .I2(CKenb_dft));
`else
OR2LC uu0(.O(CLK), .I1(CK), .I2(CKenb));
`endif
always @(posedge CLK)
if (WBen) DO[8:0] <= #`db DI[8:0];
`else
always @(posedge CK)
if (WBen && !CKenb) DO[8:0] <= #`db DI[8:0];
`endif
endmodule
`ifdef FD_DFT
module REG12L (CK, CKenb, WBen, DI, DO, SCAN_TEST);
input CK, CKenb, WBen, SCAN_TEST;
`else
module REG12L (CK, CKenb, WBen, DI, DO);
input CK, CKenb, WBen;
`endif
input [11:0] DI;
output [11:0] DO;
reg [11:0] DO;
`ifdef FD_GTCLK
`ifdef FD_DFT
GTECH_AND_NOT utm0 (.A(CKenb), .B(SCAN_TEST), .Z(CKenb_dft));
OR2LC uu1 (.O(CLK), .I1(CK), .I2(CKenb_dft));
`else
OR2LC uu1 (.O(CLK), .I1(CK), .I2(CKenb));
`endif
always @(posedge CLK)
if (WBen) DO[11:0] <= #`db DI[11:0];
`else
always @(posedge CK)
if (WBen && !CKenb) DO[11:0] <= #`db DI[11:0];
`endif
endmodule
`ifdef FD_DFT
module REG14L (CK, RST, CKenb, WBen, DI, DO, SCAN_TEST);
input CK, RST, CKenb, WBen, SCAN_TEST;
`else
module REG14L (CK, RST, CKenb, WBen, DI, DO);
input CK, RST, CKenb, WBen;
`endif
input [13:0] DI;
output [13:0] DO;
`ifdef FD_GTCLK
`ifdef FD_DFT
GTECH_AND_NOT utm0 (.A(CKenb), .B(SCAN_TEST), .Z(CKenb_dft));
OR2LC uu0(.O(CLK), .I1(CK), .I2(CKenb_dft));
`else
OR2LC uu0(.O(CLK), .I1(CK), .I2(CKenb));
`endif
reg [13:0] DO;
always @(posedge CLK or posedge RST)
if (RST) DO[13:0] <= #`db 14'b0;
else if (WBen) DO[13:0] <= #`db DI[13:0];
`else
reg [13:0] DO;
always @(posedge CK or posedge RST)
if (RST) DO[13:0] <= #`db 14'b0;
else if (WBen && !CKenb) DO[13:0] <= #`db DI[13:0];
`endif
endmodule
`ifdef FD_DFT
module REG16L (CK, CKenb, WBen, DI, DO, SCAN_TEST);
input CK, CKenb, WBen, SCAN_TEST;
`else
module REG16L (CK, CKenb, WBen, DI, DO);
input CK, CKenb, WBen;
`endif
input [15:0] DI;
output [15:0] DO;
`ifdef FD_GTCLK
`ifdef FD_DFT
GTECH_AND_NOT utm0 (.A(CKenb), .B(SCAN_TEST), .Z(CKenb_dft));
OR2LC uu0(.O(CLK), .I1(CK), .I2(CKenb_dft));
`else
OR2LC uu0(.O(CLK), .I1(CK), .I2(CKenb));
`endif
reg [15:0] DO;
always @(posedge CLK)
if (WBen) DO[15:0] <= #`db DI[15:0];
`else
reg [15:0] DO;
always @(posedge CK)
if (WBen && !CKenb) DO[15:0] <= #`db DI[15:0];
`endif
endmodule
`ifdef FD_DFT
module REG4LC (CK, CKenb, WBen, DI, DO, CLR, SCAN_TEST);
input CK, CKenb, WBen, CLR, SCAN_TEST;
`else
module REG4LC (CK, CKenb, WBen, DI, DO, CLR);
input CK, CKenb, WBen, CLR;
`endif
input [3:0] DI;
output [3:0] DO;
reg [3:0] DO;
`ifdef FD_GTCLK
`ifdef FD_DFT
GTECH_AND_NOT utm0 (.A(CKenb), .B(SCAN_TEST), .Z(CKenb_dft));
OR2LC uu1 (.O(CLK), .I1(CK), .I2(CKenb_dft));
`else
OR2LC uu1 (.O(CLK), .I1(CK), .I2(CKenb));
`endif
always @(posedge CLK or posedge CLR)
if (CLR) DO[3:0] <= #`db 4'b0;
else if (WBen) DO[3:0] <= #`db DI[3:0];
`else
always @(posedge CK or posedge CLR)
if (CLR) DO[3:0] <= #`db 4'b0;
else if (WBen && !CKenb) DO[3:0] <= #`db DI[3:0];
`endif
endmodule
`ifdef FD_DFT
module REG5LC (CK, CKenb, WBen, DI, DO, CLR, SCAN_TEST);
input CK, CKenb, WBen, CLR, SCAN_TEST;
`else
module REG5LC (CK, CKenb, WBen, DI, DO, CLR);
input CK, CKenb, WBen, CLR;
`endif
input [4:0] DI;
output [4:0] DO;
reg [4:0] DO;
`ifdef FD_GTCLK
`ifdef FD_DFT
GTECH_AND_NOT utm0 (.A(CKenb), .B(SCAN_TEST), .Z(CKenb_dft));
OR2LC uu1 (.O(CLK), .I1(CK), .I2(CKenb_dft));
`else
OR2LC uu1 (.O(CLK), .I1(CK), .I2(CKenb));
`endif
always @(posedge CLK or posedge CLR)
if (CLR) DO[4:0] <= #`db 5'b0;
else if (WBen) DO[4:0] <= #`db DI[4:0];
`else
always @(posedge CK or posedge CLR)
if (CLR) DO[4:0] <= #`db 5'b0;
else if (WBen && !CKenb) DO[4:0] <= #`db DI[4:0];
`endif
endmodule
`ifdef FD_DFT
module REG7LC (CK, CKenb, WBen, DI, DO, CLR, SCAN_TEST);
input CK, CKenb, WBen, CLR, SCAN_TEST;
`else
module REG7LC (CK, CKenb, WBen, DI, DO, CLR);
input CK, CKenb, WBen, CLR;
`endif
input [6:0] DI;
output [6:0] DO;
reg [6:0] DO;
`ifdef FD_GTCLK
`ifdef FD_DFT
GTECH_AND_NOT utm0 (.A(CKenb), .B(SCAN_TEST), .Z(CKenb_dft));
OR2LC uu1 (.O(CLK), .I1(CK), .I2(CKenb_dft));
`else
OR2LC uu1 (.O(CLK), .I1(CK), .I2(CKenb));
`endif
always @(posedge CLK or posedge CLR)
if (CLR) DO[6:0] <= #`db 7'b0;
else if (WBen) DO[6:0] <= #`db DI[6:0];
`else
always @(posedge CK or posedge CLR)
if (CLR) DO[6:0] <= #`db 7'b0;
else if (WBen && !CKenb) DO[6:0] <= #`db DI[6:0];
`endif
endmodule
`ifdef FD_DFT
module REG8LCI (CK, CKenb, WBen, DI, DO, CLR, SCAN_TEST);
input CK, CKenb, WBen, CLR, SCAN_TEST;
`else
module REG8LCI (CK, CKenb, WBen, DI, DO, CLR);
input CK, CKenb, WBen, CLR;
`endif
input [7:0] DI;
output [7:0] DO;
reg [7:0] DO;
`ifdef FD_GTCLK
`ifdef FD_DFT
GTECH_AND_NOT utm0 (.A(CKenb), .B(SCAN_TEST), .Z(CKenb_dft));
OR2LC uu1 (.O(CLK), .I1(CK), .I2(CKenb_dft));
`else
OR2LC uu1 (.O(CLK), .I1(CK), .I2(CKenb));
`endif
always @(posedge CLK or posedge CLR)
if (CLR) DO[7:0] <= #`db 8'b01010101;
else if (WBen) DO[7:0] <= #`db DI[7:0];
`else
always @(posedge CK or posedge CLR)
if (CLR) DO[7:0] <= #`db 8'b01010101;
else if (WBen && !CKenb) DO[7:0] <= #`db DI[7:0];
`endif
endmodule
`ifdef FD_DFT
module REG9LC (CK, CKenb, WBen, DI, DO, CLR, SCAN_TEST);
input CK, CKenb, WBen, CLR, SCAN_TEST;
`else
module REG9LC (CK, CKenb, WBen, DI, DO, CLR);
input CK, CKenb, WBen, CLR;
`endif
input [8:0] DI;
output [8:0] DO;
reg [8:0] DO;
`ifdef FD_GTCLK
`ifdef FD_DFT
GTECH_AND_NOT utm0 (.A(CKenb), .B(SCAN_TEST), .Z(CKenb_dft));
OR2LC uu1 (.O(CLK), .I1(CK), .I2(CKenb_dft));
`else
OR2LC uu1 (.O(CLK), .I1(CK), .I2(CKenb));
`endif
always @(posedge CLK or posedge CLR)
if (CLR) DO[8:0] <= #`db 9'b0;
else if (WBen) DO[8:0] <= #`db DI[8:0];
`else
always @(posedge CK or posedge CLR)
if (CLR) DO[8:0] <= #`db 9'b0;
else if (WBen && !CKenb) DO[8:0] <= #`db DI[8:0];
`endif
endmodule
`ifdef FD_DFT
module REG11LC (CK, CKenb, WBen, DI, DO, CLR, SCAN_TEST);
input CK, CKenb, WBen, CLR, SCAN_TEST;
`else
module REG11LC (CK, CKenb, WBen, DI, DO, CLR);
input CK, CKenb, WBen, CLR;
`endif
input [10:0] DI;
output [10:0] DO;
reg [10:0] DO;
`ifdef FD_GTCLK
GTECH_NOT uu0 (.Z(CLR_), .A(CLR));
`ifdef FD_DFT
GTECH_AND_NOT utm0 (.A(CKenb), .B(SCAN_TEST), .Z(CKenb_dft));
OR2LC uu1 (.O(CLK), .I1(CK), .I2(CKenb_dft));
`else
OR2LC uu1 (.O(CLK), .I1(CK), .I2(CKenb));
`endif
always @(posedge CLK or posedge CLR)
if (CLR) DO[10:0] <= #`db 11'b0;
else if (WBen) DO[10:0] <= #`db DI[10:0];
`else
always @(posedge CK or posedge CLR)
if (CLR) DO[10:0] <= #`db 11'b0;
else if (WBen && !CKenb) DO[10:0] <= #`db DI[10:0];
`endif
endmodule
`ifdef FD_DFT
module REG12LC (CK, CKenb, WBen, DI, DO, CLR, SCAN_TEST);
input CK, CKenb, WBen, CLR, SCAN_TEST;
`else
module REG12LC (CK, CKenb, WBen, DI, DO, CLR);
input CK, CKenb, WBen, CLR;
`endif
input [11:0] DI;
output [11:0] DO;
reg [11:0] DO;
`ifdef FD_GTCLK
GTECH_NOT uu0 (.Z(CLR_), .A(CLR));
`ifdef FD_DFT
GTECH_AND_NOT utm0 (.A(CKenb), .B(SCAN_TEST), .Z(CKenb_dft));
OR2LC uu1 (.O(CLK), .I1(CK), .I2(CKenb_dft));
`else
OR2LC uu1 (.O(CLK), .I1(CK), .I2(CKenb));
`endif
always @(posedge CLK or posedge CLR)
if (CLR) DO[11:0] <= #`db 12'b0;
else if (WBen) DO[11:0] <= #`db DI[11:0];
`else
always @(posedge CK or posedge CLR)
if (CLR) DO[11:0] <= #`db 12'b0;
else if (WBen && !CKenb) DO[11:0] <= #`db DI[11:0];
`endif
endmodule
`ifdef FD_DFT
module REG14LC (CK, CKenb, WBen, DI, DO, CLR, SCAN_TEST);
input CK, CKenb, WBen, CLR, SCAN_TEST;
`else
module REG14LC (CK, CKenb, WBen, DI, DO, CLR);
input CK, CKenb, WBen, CLR;
`endif
input [13:0] DI;
output [13:0] DO;
`ifdef FD_GTCLK
`ifdef FD_DFT
GTECH_AND_NOT utm0 (.A(CKenb), .B(SCAN_TEST), .Z(CKenb_dft));
OR2LC uu1 (.O(CLK), .I1(CK), .I2(CKenb_dft));
`else
OR2LC uu1 (.O(CLK), .I1(CK), .I2(CKenb));
`endif
reg [13:0] DO;
always @(posedge CLK or posedge CLR)
if (CLR) DO[13:0] <= #`db 14'b0;
else if (WBen) DO[13:0] <= #`db DI[13:0];
`else
reg [13:0] DO;
always @(posedge CK or posedge CLR)
if (CLR) DO[13:0] <= #`db 14'b0;
else if (WBen && !CKenb) DO[13:0] <= #`db DI[13:0];
`endif
endmodule
`ifdef FD_DFT
module REG16LC (CK, CKenb, WBen, DI, DO, CLR, SCAN_TEST);
input CK, CKenb, WBen, CLR, SCAN_TEST;
`else
module REG16LC (CK, CKenb, WBen, DI, DO, CLR);
input CK, CKenb, WBen, CLR;
`endif
input [15:0] DI;
output [15:0] DO;
reg [15:0] DO;
`ifdef FD_GTCLK
`ifdef FD_DFT
GTECH_AND_NOT utm0 (.A(CKenb), .B(SCAN_TEST), .Z(CKenb_dft));
OR2LC uu1 (.O(CLK), .I1(CK), .I2(CKenb_dft));
`else
OR2LC uu1 (.O(CLK), .I1(CK), .I2(CKenb));
`endif
always @(posedge CLK or posedge CLR)
if (CLR) DO[15:0] <= #`db 16'b0;
else if (WBen) DO[15:0] <= #`db DI[15:0];
`else
always @(posedge CK or posedge CLR)
if (CLR) DO[15:0] <= #`db 16'b0;
else if (WBen && !CKenb) DO[15:0] <= #`db DI[15:0];
`endif
endmodule
`ifdef FD_DFT
module REG2D8L (CK, CKenb, WBen, DI1, DI2, DO, SCAN_TEST);
input CK, CKenb, WBen, SCAN_TEST;
`else
module REG2D8L (CK, CKenb, WBen, DI1, DI2, DO);
input CK, CKenb, WBen;
`endif
input [7:0] DI1, DI2 ;
output [7:0] DO;
reg [7:0] DO;
`ifdef FD_GTCLK
`ifdef FD_DFT
GTECH_AND_NOT utm0 (.A(CKenb), .B(SCAN_TEST), .Z(CKenb_dft));
OR2LC uu0(.O(CLK), .I1(CK), .I2(CKenb_dft));
`else
OR2LC uu0(.O(CLK), .I1(CK), .I2(CKenb));
`endif
always @(posedge CLK) begin
if (WBen) DO[7:0] <= #`db DI1[7:0];
else DO[7:0] <= #`db DI2[7:0];
end
`else
always @(posedge CK) begin
if (WBen && !CKenb) DO[7:0] <= #`db DI1[7:0];
else if(!CKenb) DO[7:0] <= #`db DI2[7:0];
end
`endif
endmodule
`ifdef FD_DFT
module REG2D16L (CK, CKenb, WBen, DI1, DI2, DO, SCAN_TEST);
input CK, CKenb, WBen, SCAN_TEST;
`else
module REG2D16L (CK, CKenb, WBen, DI1, DI2, DO);
input CK, CKenb, WBen;
`endif
input [15:0] DI1, DI2;
output [15:0] DO;
reg [15:0] DO;
`ifdef FD_GTCLK
`ifdef FD_DFT
GTECH_AND_NOT utm0 (.A(CKenb), .B(SCAN_TEST), .Z(CKenb_dft));
OR2LC uu0(.O(CLK), .I1(CK), .I2(CKenb_dft));
`else
OR2LC uu0(.O(CLK), .I1(CK), .I2(CKenb));
`endif
always @(posedge CLK) begin
if (WBen) DO[15:0] <= #`db DI1[15:0];
else DO[15:0] <= #`db DI2[15:0];
end
`else
always @(posedge CK) begin
if (WBen && !CKenb) DO[15:0] <= #`db DI1[15:0];
else if(!CKenb) DO[15:0] <= #`db DI2[15:0];
end
`endif
endmodule
`ifdef FD_DFT
module SREG16MC (CK, CKenb, WBen, DI, DO, CLR, SCAN_TEST);
input CK, CKenb, WBen, CLR, SCAN_TEST;
`else
module SREG16MC (CK, CKenb, WBen, DI, DO, CLR);
input CK, CKenb, WBen, CLR;
`endif
input [15:0] DI;
output [15:0] DO;
reg [15:0] DO;
`ifdef FD_GTCLK
`ifdef FD_DFT
GTECH_AND_NOT utm0 (.A(CKenb), .B(SCAN_TEST), .Z(CKenb_dft));
OR2LC uu1 (.O(CLK), .I1(CK), .I2(CKenb_dft));
`else
OR2LC uu1 (.O(CLK), .I1(CK), .I2(CKenb));
`endif
always @(posedge CLK or posedge CLR)
if (CLR) DO[15:0] <= #`db 16'h0800;
else if (WBen) DO[15:0] <= #`db DI[15:0];
`else
always @(posedge CK or posedge CLR)
if (CLR) DO[15:0] <= #`db 16'h0800;
else if (WBen && !CKenb) DO[15:0] <= #`db DI[15:0];
`endif
endmodule
`ifdef FD_DFT
module MREG16MC (CK, CKenb, WBen, DI, DO, CLR, SCAN_TEST);
input CK, CKenb, WBen, CLR, SCAN_TEST;
`else
module MREG16MC (CK, CKenb, WBen, DI, DO, CLR);
input CK, CKenb, WBen, CLR;
`endif
input [15:0] DI;
output [15:0] DO;
reg [15:0] DO;
`ifdef FD_GTCLK
`ifdef FD_DFT
GTECH_AND_NOT utm0 (.A(CKenb), .B(SCAN_TEST), .Z(CKenb_dft));
OR2LC uu1 (.O(CLK), .I1(CK), .I2(CKenb_dft));
`else
OR2LC uu1 (.O(CLK), .I1(CK), .I2(CKenb));
`endif
always @(posedge CLK or posedge CLR)
if (CLR) DO[15:0] <= #`db {2'h3, 4'h0, 3'h7, 3'h7, 4'hf};
else if (WBen) DO[15:0] <= #`db DI[15:0];
`else
always @(posedge CK or posedge CLR)
if (CLR) DO[15:0] <= #`db {2'h3, 4'h0, 3'h7, 3'h7, 4'hf};
else if (WBen && !CKenb) DO[15:0] <= #`db DI[15:0];
`endif
endmodule
`ifdef FD_DFT
module EREG15LC (CK, CKenb, WBen, DI, DO, CLR, SCAN_TEST);
input CK, CKenb, WBen, CLR, SCAN_TEST;
`else
module EREG15LC (CK, CKenb, WBen, DI, DO, CLR);
input CK, CKenb, WBen, CLR;
`endif
input [14:0] DI;
output [14:0] DO;
reg [14:0] DO;
`ifdef FD_GTCLK
`ifdef FD_DFT
GTECH_AND_NOT utm0 (.A(CKenb), .B(SCAN_TEST), .Z(CKenb_dft));
OR2LC uu1 (.O(CLK), .I1(CK), .I2(CKenb_dft));
`else
OR2LC uu1 (.O(CLK), .I1(CK), .I2(CKenb));
`endif
always @(posedge CLK or posedge CLR)
if (CLR) DO[14:0] <= #`db 15'h7fff;
else if (WBen) DO[14:0] <= #`db DI[14:0];
`else
always @(posedge CK or posedge CLR)
if (CLR) DO[14:0] <= #`db 15'h7fff;
else if (WBen && !CKenb) DO[14:0] <= #`db DI[14:0];
`endif
endmodule
module IDEBN (SCLK, IN, OUT);
input SCLK, IN;
output OUT;
reg IN_syn, OUT;
wire OUT_di;
always @(posedge SCLK)
begin
IN_syn <= #1 IN;
OUT <= #1 OUT_di;
end
assign OUT_di = OUT ? (IN | IN_syn) : (IN & IN_syn);
endmodule
module Delaya (i, o);
input i;
output o;
Delbufx u1 (.I(i), .O(o));
endmodule
module Oneshot (i, o);
input i;
output o;
wire deli;
wire del1, del2, del3, del4, del5, del6, del7, del8, del9;
Delbufx Delbuf1 (i,del1);
Delbufx Delbuf2 (del1,del2);
Delbufx Delbuf3 (del2,del3);
Delbufx Delbuf4 (del3,del4);
Delbufx Delbuf5 (del4,del5);
Delbufx Delbuf6 (del5,del6);
Delbufx Delbuf7 (del6,del7);
Delbufx Delbuf8 (del7,del8);
Delbufx Delbuf9 (del8,del9);
Delbufx Delbufa (del9,deli);
assign #`da o = i && !deli;
endmodule
module Delbufx (I, O);
input I;
output O;
assign #0.1 O = I;
endmodule
module HALFP (RST,
CLK,
IN,
`ifdef FD_DFT
SCAN_TEST,
`endif
WEP1);
input RST, CLK, IN;
`ifdef FD_DFT
input SCAN_TEST;
`endif
output WEP1;
reg FFout;
wire FFout_d, CLR, CLK_;
wire FFout_d1, FFout_d2, FFout_d3, FFout_d4;
assign #`db CLK_ = ~CLK;
always @(posedge CLK or posedge CLR)
if (CLR) FFout <= #`db 1'b0;
else FFout <= #`db IN;
Delbufx Delbuf1 (FFout,FFout_d1);
Delbufx Delbuf2 (FFout_d1,FFout_d2);
Delbufx Delbuf3 (FFout_d2,FFout_d3);
Delbufx Delbuf4 (FFout_d3,FFout_d);
Delbufx Delbuf0 (FFout_d1,WEP1);
`ifdef FD_DFT
wire CLR_h = RST | (CLK_ & FFout_d);
assign CLR = SCAN_TEST ? RST : CLR_h;
`else
assign #`da CLR = RST | (CLK_ & FFout_d);
`endif
endmodule
module OR2LC(I1, I2, O);
input I1, I2;
output O;
GtCLK_NOR2 U0 (.A (I2 ),.B (I1 ),.Z (N1));
GtCLK_NOT U1 (.Z (O),.A (N1));
endmodule
|
`include "../include/x_def.v"
module EMC (/* ------------ Inputs : ------------- */
DSPCLK, T_RST, PPclr_h, DMD, selECM,
PM_bdry_sel,
GO_Fx, GO_Ex, GO_EC, ECYC, BGn, PMOVL_dsp,
DMOVL_dsp, Dummy_E,
IOaddr, Double_E, accCM_E, rdCM_E,
DMA, PMA, WSCR_we, WSCR_ext_we, EXTC_Eg,
Pread_Ei, Pwrite_Ei, Dread_Ei, Dwrite_Ei,
IOcmd_Ei, IOread_Ei, IOwrite_Ei, MMR_web,
CMAin, ECMAWAITi,
IDR,
T_EA, T_ED,
PMDin,
CM_rd,
BDMAmode, BMpage,
BDIR, BWdataBUF, BWRn, BEAD,
BSreq, BSack, BWend,
`ifdef FD_DFT
SCAN_TEST,
`endif
EA_oe, EA_do, ED_oe, ED_do,
PMSn, DMSn, IOSn, BMSn,
CMSn, RDn, WRn, ECMSn, ECMA_EN,
eRDY,
WSCR, WSCR_ext, emcDMD_oe, emcDMD_do,
emcPMD_oe, emcPMD_do,
CM_rdata,
ENS12, ECS12, ENS13, ECS13, ENS14,
ECS14, ENS0, BMcs
);
input [13:0] BEAD;
input [7:0] BMpage,
BWdataBUF;
input BDMAmode,
BDIR,
BWRn,
BSreq,
BSack,
BWend;
input [7:0] PMOVL_dsp;
input [3:0] DMOVL_dsp;
input [1:0] ECMAWAITi;
input [7:0] T_EA;
input [15:0] T_ED,
DMD;
input [13:0] PMA,
DMA,
CMAin;
input [23:0] IDR,
CM_rd;
input [10:0] IOaddr;
input DSPCLK,
PPclr_h,
PM_bdry_sel,
T_RST,
GO_Fx,
GO_Ex,
GO_EC,
selECM,
ECYC,
BGn,
EXTC_Eg,
Dummy_E,
Pread_Ei,
Pwrite_Ei,
Dread_Ei,
Dwrite_Ei,
IOcmd_Ei,
IOread_Ei,
IOwrite_Ei,
Double_E,
accCM_E,
rdCM_E,
WSCR_we,
WSCR_ext_we,
MMR_web;
`ifdef FD_DFT
input SCAN_TEST;
`endif
output [23:0] CM_rdata;
output [15:0] emcDMD_do,
emcPMD_do;
output [14:0] WSCR;
output [7:0] WSCR_ext;
output [14:0] EA_do;
output [15:0] ED_do;
output ED_oe,
EA_oe,
ECMA_EN,
ECMSn,
PMSn,
DMSn,
IOSn,
CMSn,
RDn,
WRn,
eRDY,
emcPMD_oe,
emcDMD_oe;
output BMSn,
ENS12,
ECS12,
ENS13,
ECS13,
ENS14,
ECS14,
ENS0,
BMcs;
input [15:0] PMDin;
wire [14:0] WSCR;
reg [3:0] ECS, ENS;
reg [15:0] ED_do_h;
reg [13:0] ECMA;
reg [23:0] ECMDreg;
reg [15:0] PMDreg, DMDreg;
reg [5:0] RWcnt;
reg IOcst, PMcst, DMcst, ED_oei,
selPMDi, selDMDi, RDn, WRn_h, eRDY, PMDoe,
DMDoe, EXTC_Eg_syn, ECMcs, ECMA_EN;
wire IOcs, PMcs, DMcs, selPMD, selDMD;
wire [15:0] ED_do;
wire [5:0] RWcnt_ref;
wire [5:0] DMWAIT, PMWAIT, IOWAIT;
wire [3:0] ECMAWAIT;
wire [7:0] WSCR_ext;
wire selEDM, selEDMg,
GO_EDM;
wire RWend, RWcnt_en, RWcnt_clr, selEPM, IOext,
IOcs_nx, IOcs_clr, PMcs_nx, PMcs_clr,
PMDoe_clr, DMDoe_clr, DMcs_nx, DMcs_clr,
selPMD_h, selDMD_h, selECMD_h, ED_oe_h, RD_h,
WR_h, PMDlat, DMDlat, eRDY_h, CMcs, CMDlat, WRn;
wire ENS0, ENS1, ENS2, ENS3, ENS4, ENS5, ENS6, ENS8, ENS9, ENS10, ENS11, ENS12,
ENS13, ENS14;
wire ECS0, ECS1, ECS2, ECS3, ECS5, ECS6, ECS8, ECS9, ECS10, ECS11, ECS12, ECS13,
ECS14;
wire BMSn;
reg BMcs;
wire EMCLK1, EMCLK2, ECMCLK1, ECMCLK2;
`ifdef FD_DFT
reg RST_o, PPclr_o;
wire RST, PPclr;
always @(posedge DSPCLK) begin
RST_o <= #`db T_RST;
PPclr_o <= #`db T_RST || PPclr_h && !BDMAmode;
end
assign RST = SCAN_TEST ? T_RST : RST_o;
assign PPclr = SCAN_TEST ? T_RST : PPclr_o;
`else
reg RST, PPclr;
always @(posedge DSPCLK) begin
RST <= #`db T_RST;
PPclr <= #`db T_RST || PPclr_h && !BDMAmode;
end
`endif
always @(posedge DSPCLK) EXTC_Eg_syn <= #`db EXTC_Eg;
`ifdef FD_GTCLK
GtCLK_NOR2 uu0 (.Z(CKenb), .A(EXTC_Eg), .B(EXTC_Eg_syn));
`ifdef FD_DFT
GTECH_AND_NOT utm0 (.Z(CKenb_dft), .A(CKenb), .B(SCAN_TEST));
GTECH_NOR2 uu1 (.Z(EMCLKb), .A(DSPCLK), .B(CKenb_dft));
GTECH_NOR2 utm1 (.Z(selECMb), .A(selECM), .B(SCAN_TEST));
GTECH_NOR2 uu5 (.Z(ECMCLKb), .A(DSPCLK), .B(selECMb));
`else
GTECH_NOR2 uu1 (.Z(EMCLKb), .A(DSPCLK), .B(CKenb));
GTECH_NOT uu4 (.Z(selECMb), .A(selECM));
GTECH_NOR2 uu5 (.Z(ECMCLKb), .A(DSPCLK), .B(selECMb));
`endif
GtCLK_NOT ckEMCLK1 (.Z(EMCLK1), .A(EMCLKb));
GtCLK_NOT ckEMCLK2 (.Z(EMCLK2), .A(EMCLKb));
GtCLK_NOT ckECMCLK1 (.Z(ECMCLK1), .A(ECMCLKb));
GtCLK_NOT ckECMCLK2 (.Z(ECMCLK2), .A(ECMCLKb));
`else
wire EMCLK_en=EXTC_Eg || EXTC_Eg_syn;
assign EMCLK1 = DSPCLK ;
assign EMCLK2 = DSPCLK ;
assign ECMCLK1 = DSPCLK ;
assign ECMCLK2 = DSPCLK ;
`endif
`ifdef FD_DFT
EREG15LC WSCRreg (DSPCLK, MMR_web, WSCR_we, DMD[14:0], WSCR[14:0], RST, SCAN_TEST);
`else
EREG15LC WSCRreg (DSPCLK, MMR_web, WSCR_we, DMD[14:0], WSCR[14:0], RST);
`endif
`ifdef FD_DFT
REG8LCI WSCRext_reg (DSPCLK, MMR_web, WSCR_ext_we, DMD[7:0], WSCR_ext[7:0], RST, SCAN_TEST);
`else
REG8LCI WSCRext_reg (DSPCLK, MMR_web, WSCR_ext_we, DMD[7:0], WSCR_ext[7:0], RST);
`endif
assign #`d0 DMWAIT[5:0] = {WSCR_ext[7:6], WSCR[11:8]};
assign #`d0 PMWAIT[5:0] = {WSCR_ext[5:4], WSCR[7:4]};
assign #`d0 IOWAIT[5:0] = {WSCR_ext[3:2], WSCR[3:0]};
assign #`d0 ECMAWAIT[3:0] = {WSCR_ext[1:0], ECMAWAITi[1:0]};
assign #`da selEDMg = Double_E && selEDM;
always @(ECS or eRDY or ECYC or RWend or PMcst or DMcst or IOcst or
selEDMg or selECM or BDMAmode or BSreq or BSack or BWend) begin
ENS <= #`da 4'h0;
case (ECS)
4'h0 : casex ({eRDY, ECYC, PMcst, DMcst|IOcst, selECM, BDMAmode})
6'b1xxxxx : ENS <= #`da 4'h0;
6'b011xxx : ENS <= #`da 4'h1;
6'b0101xx : ENS <= #`da 4'h5;
6'b01001x : ENS <= #`da 4'h8;
6'b000001 : ENS <= #`da 4'hc;
6'b000000 : ENS <= #`da 4'h0;
default : ENS <= #`da 4'h0;
endcase
4'h1 : casex ({RWend, selEDMg})
2'b0x : ENS <= #`da 4'h1;
2'b10 : ENS <= #`da 4'h2;
2'b11 : ENS <= #`da 4'h3;
default : ENS <= #`da 4'h1;
endcase
4'h2 : ENS <= #`da selECM ? 4'h8: 4'h0;
4'h3 : ENS <= #`da 4'h4;
4'h4 : ENS <= #`da 4'h5;
4'h5 : ENS <= #`da RWend ? 4'h6 : 4'h5;
4'h6 : ENS <= #`da selECM ? 4'h8: 4'h0;
4'h8 : ENS <= #`da RWend ? 4'h9: 4'h8;
4'h9 : ENS <= #`da RWend ? 4'ha: 4'h9;
4'ha : ENS <= #`da RWend ? 4'hb: 4'ha;
4'hb : ENS <= #`da 4'h0;
4'hc : ENS <= #`da BWend ? 4'hd : 4'hc;
4'hd : ENS <= #`da BSreq ? 4'he : 4'h0;
4'he : ENS <= #`da BSack ? 4'h0 : 4'he;
default : ENS <= #`da 4'h0;
endcase
end
always @(posedge DSPCLK or posedge PPclr) begin
if (PPclr) ECS <= #`db 4'h0;
else ECS <= #`db ENS;
end
assign ENS0 = ENS==4'h0;
assign ENS1 = ENS==4'h1;
assign ENS2 = ENS==4'h2;
assign ENS3 = ENS==4'h3;
assign ENS4 = ENS==4'h4;
assign ENS5 = ENS==4'h5;
assign ENS6 = ENS==4'h6;
assign ENS8 = ENS==4'h8;
assign ENS9 = ENS==4'h9;
assign ENS10 = ENS==4'ha;
assign ENS11 = ENS==4'hb;
assign ENS12 = ENS==4'hc;
assign ENS13 = ENS==4'hd;
assign ENS14 = ENS==4'he;
assign ECS0 = ECS==4'h0;
assign ECS1 = ECS==4'h1;
assign ECS2 = ECS==4'h2;
assign ECS3 = ECS==4'h3;
assign ECS5 = ECS==4'h5;
assign ECS6 = ECS==4'h6;
assign ECS8 = ECS==4'h8;
assign ECS9 = ECS==4'h9;
assign ECS10 = ECS==4'ha;
assign ECS11 = ECS==4'hb;
assign ECS12 = ECS==4'hc;
assign ECS13 = ECS==4'hd;
assign ECS14 = ECS==4'he;
assign #`da RWend = (RWcnt[5:0] == RWcnt_ref[5:0]);
assign #`da RWcnt_ref[5:0] = PMcst ? PMWAIT[5:0] :
DMcst ? DMWAIT[5:0] :
IOcst ? IOWAIT[5:0] :
{2'b0, ECMAWAIT[3:0]};
assign #`da RWcnt_en = ECS1 || ECS5 || ECS8 || ECS9 || ECS10;
assign #`da RWcnt_clr = ENS0 || ENS3 || ENS8 & !ECS8 || ENS9 & !ECS9 ||
ENS10 &! ECS10 ;
always @(posedge DSPCLK) begin
if (RWcnt_clr) RWcnt[5:0] <= #`db 6'h0;
else if (RWcnt_en) RWcnt[5:0] <= #`db RWcnt + 1;
end
wire PM_rgn;
assign #`da PM_rgn = PM_bdry_sel ? PMA[13] : &{PMA[13:12]};
assign #`da selEPM = PM_rgn && PMOVL_dsp[7];
assign #`da selEDM = !DMA[13] && DMOVL_dsp[3];
assign #`da IOext = IOcmd_Ei;
assign #`da IOcs_nx = IOext && EXTC_Eg;
assign #`da IOcs_clr = ECS6;
always @(posedge EMCLK1 or posedge PPclr) begin
if (PPclr) IOcst <= #`db 0;
`ifdef FD_GTCLK
else if (GO_EC) IOcst <= #`db IOcs_nx;
else if (IOcs_clr) IOcst <= #`db 0;
`else
else if (GO_EC & EMCLK_en) IOcst <= #`db IOcs_nx;
else if (IOcs_clr & EMCLK_en) IOcst <= #`db 0;
`endif
end
assign #`da IOcs = IOcst && (ENS5 || ECS5 || ECS6);
assign #`da PMcs_nx = selEPM && EXTC_Eg && (Pread_Ei || Pwrite_Ei);
assign #`da PMcs_clr = ECS2 || ECS3;
always @(posedge EMCLK1 or posedge PPclr) begin
if (PPclr) PMcst <= #`db 0;
`ifdef FD_GTCLK
else if (GO_EC) PMcst <= #`db PMcs_nx;
else if (PMcs_clr) PMcst <= #`db 0;
`else
else if (GO_EC & EMCLK_en) PMcst <= #`db PMcs_nx;
else if (PMcs_clr & EMCLK_en) PMcst <= #`db 0;
`endif
end
assign #`da PMcs = ENS1 | ECS1 | ECS2;
assign #`da DMcs_nx = selEDM && EXTC_Eg && (Dread_Ei || Dwrite_Ei);
assign #`da GO_EDM = (Double_E && selEPM) ? ENS4 : GO_EC;
assign #`da DMcs_clr = ECS6;
always @(posedge EMCLK1 or posedge PPclr) begin
if (PPclr) DMcst <= #`db 0;
`ifdef FD_GTCLK
else if (GO_EDM) DMcst <= #`db DMcs_nx;
else if (DMcs_clr) DMcst <= #`db 0;
`else
else if (GO_EDM & EMCLK_en) DMcst <= #`db DMcs_nx;
else if (DMcs_clr & EMCLK_en) DMcst <= #`db 0;
`endif
end
assign #`da DMcs = DMcst && (ENS5 || ECS5 || ECS6);
always @(posedge ECMCLK1 or posedge PPclr)
if (PPclr) ECMcs <= #`db 0;
`ifdef FD_GTCLK
else if(ENS8) ECMcs <= #`db 1;
else if(ECS11) ECMcs <= #`db 0;
`else
else if(ENS8 & selECM) ECMcs <= #`db 1;
else if(ECS11 & selECM) ECMcs <= #`db 0;
`endif
always @(posedge ECMCLK1)
`ifdef FD_GTCLK
if(ENS8) ECMA[13:0] <= #`db CMAin[13:0];
`else
if(ENS8 & selECM) ECMA[13:0] <= #`db CMAin[13:0];
`endif
always @(posedge DSPCLK) BMcs <= #`db ENS12 || ENS13 || ENS14;
assign #`da selPMD_h = Pwrite_Ei && (ECS1 || ENS1);
assign #`da selDMD_h = Dwrite_Ei && (ECS5 || ENS5) ||
IOwrite_Ei && (ECS5 || ENS5);
assign #`da selECMD_h = !rdCM_E && accCM_E && (ECS10 || ENS10);
assign #`da ED_oe_h = selPMD_h || selDMD_h || selECMD_h;
always @(posedge DSPCLK)
begin
ED_oei <= #`db ED_oe_h;
selPMDi <= #`db selPMD_h;
selDMDi <= #`db selDMD_h;
end
assign #`da selPMD = selPMDi && PMcs;
assign #`da selDMD = selDMDi && (DMcs || IOcs);
assign #`da ED_oe = ED_oei && BGn;
wire [15:0] IDR_L = IDR[15:0];
always @(selPMD or selDMD or PMDin or DMD
or IDR_L)
case({selPMD,selDMD})
2'b10: ED_do_h[15:0] = PMDin[15:0];
2'b01: ED_do_h[15:0] = DMD[15:0];
default: ED_do_h[15:0] = IDR_L;
endcase
assign #`da ED_do[15] = ED_do_h[15];
assign #`da ED_do[14:8] = {7{ED_oe}} & ED_do_h[14:8] | {7{BMcs}} & BMpage[7:1];
assign #`da ED_do[7:0] = {8{ED_oe}} & ED_do_h[7:0] | {8{BMcs & BDIR}} & BWdataBUF[7:0];
assign #`da EA_oe = (PMcs || DMcs || IOcs || BMcs || ECS8 || ECS9 ||
(ECS10|ECS11) && !rdCM_E && accCM_E) && BGn ;
wire [14:0] PMEA = PM_bdry_sel ? {PMOVL_dsp[5:4], PMA[12:0]} :
{PMOVL_dsp[6:4], PMA[11:0]};
reg [14:12] ECMAo_PM8K, ECMAo_PM4K;
always @(PMOVL_dsp or CMAin or ECMA)
casex({PMOVL_dsp[3:0], CMAin[13:12]})
6'bxxxx00 : ECMAo_PM8K[14:12] = 3'b000;
6'b000001 : ECMAo_PM8K[14:12] = {2'b00, ECMA[12]};
6'b000101 : ECMAo_PM8K[14:12] = 3'b010;
6'b001001 : ECMAo_PM8K[14:12] = 3'b011;
6'b001101 : ECMAo_PM8K[14:12] = 3'b100;
6'b010001 : ECMAo_PM8K[14:12] = 3'b101;
6'b010101 : ECMAo_PM8K[14:12] = 3'b110;
6'b011001 : ECMAo_PM8K[14:12] = 3'b111;
default : ECMAo_PM8K[14:12] = 3'b000;
endcase
always @(PMOVL_dsp or CMAin or ECMA)
casex({PMOVL_dsp[3:0], CMAin[13:12]})
6'bxxxx0x : ECMAo_PM4K[14:12] = {2'b00, ECMA[12]};
6'b000010 : ECMAo_PM4K[14:12] = 3'b010;
6'b000110 : ECMAo_PM4K[14:12] = 3'b011;
6'b001010 : ECMAo_PM4K[14:12] = 3'b100;
6'b001110 : ECMAo_PM4K[14:12] = 3'b101;
6'b010010 : ECMAo_PM4K[14:12] = 3'b110;
6'b010110 : ECMAo_PM4K[14:12] = 3'b111;
default : ECMAo_PM4K[14:12] = {2'b00, ECMA[12]};
endcase
wire [14:12] ECMAo = PM_bdry_sel ? ECMAo_PM8K[14:12] : ECMAo_PM4K[14:12];
assign #`da EA_do[14:0]
= BMcs ? {BMpage[0], BEAD[13:0]} :
{15{PMcs}} & PMEA[14:0] |
{15{DMcs}} & {DMOVL_dsp[1], DMOVL_dsp[0], DMA[12:0]} |
{15{IOcs}} & {4'b0, IOaddr[10:0]} |
{15{ECMcs & !(ECS10|ECS11)}} & {ECMAo[14:12], ECMA[11:0]} |
{15{ECMcs & (ECS10|ECS11)}} & {ECMAo[14:12], ECMA[11:8],
IDR[23:16]};
assign #`da CMcs = PMcs && WSCR[12] ||
DMcs && WSCR[13] ||
IOcs && WSCR[14];
assign #`da PMSn = !PMcs;
assign #`da DMSn = !DMcs;
assign #`da IOSn = !IOcs;
assign #`da ECMSn = !ECMcs;
assign #`da CMSn = !CMcs;
assign #`da BMSn = !BMcs;
assign #`da RD_h = ENS12 && !BDIR || !ENS12 && (
Pread_Ei && ENS1 ||
Dread_Ei && ENS5 ||
IOread_Ei && ENS5 ||
ENS10 && !(!rdCM_E && accCM_E));
assign #`da WR_h = Pwrite_Ei && ENS1 ||
Dwrite_Ei && ENS5 ||
IOwrite_Ei && ENS5 ||
ENS10 && !rdCM_E && accCM_E;
always @(posedge DSPCLK)
begin
RDn <= #`db !RD_h;
WRn_h <= #`db !WR_h;
end
assign #`da WRn = BMcs ? BWRn : WRn_h;
always @(posedge ECMCLK1)
`ifdef FD_GTCLK
if(ENS8) ECMA_EN <= #`db 1'b0;
`else
if(ENS8 & selECM) ECMA_EN <= #`db 1'b0;
`endif
else ECMA_EN <= #`db 1'b1;
assign #`da PMDlat = Pread_Ei && PMcs && ECS1 && RWend;
always @(posedge EMCLK1)
`ifdef FD_GTCLK
if (PMDlat) PMDreg[15:0] <= #`db T_ED[15:0];
`else
if (PMDlat & EMCLK_en) PMDreg[15:0] <= #`db T_ED[15:0];
`endif
assign #`da PMDoe_clr = GO_Ex && PMDoe;
always @(posedge EMCLK2 or posedge PPclr) begin
if (PPclr) PMDoe <= #`db 0;
`ifdef FD_GTCLK
else if (GO_EC) PMDoe <= #`db selEPM && EXTC_Eg && Pread_Ei;
else if (PMDoe_clr) PMDoe <= #`db 0;
`else
else if (GO_EC & EMCLK_en) PMDoe <= #`db selEPM && EXTC_Eg && Pread_Ei;
else if (PMDoe_clr & EMCLK_en) PMDoe <= #`db 0;
`endif
end
assign #`d0 emcPMD_oe = PMDoe;
assign #`d0 emcPMD_do[15:0] = PMDreg[15:0];
assign #`da DMDlat = (Dread_Ei || IOread_Ei) && (DMcs || IOcs) &&
ECS5 && RWend;
always @(posedge EMCLK2)
`ifdef FD_GTCLK
if (DMDlat) DMDreg[15:0] <= #`db T_ED[15:0];
`else
if (DMDlat & EMCLK_en) DMDreg[15:0] <= #`db T_ED[15:0];
`endif
assign #`da DMDoe_clr = GO_Ex && DMDoe;
always @(posedge EMCLK2 or posedge PPclr)
if (PPclr) DMDoe <= #`db 1'b0;
`ifdef FD_GTCLK
else if (GO_EDM) DMDoe <= #`db (Dread_Ei && selEDM) || IOread_Ei;
else if (DMDoe_clr) DMDoe <= #`db 0;
`else
else if (GO_EDM & EMCLK_en) DMDoe <= #`db (Dread_Ei && selEDM) || IOread_Ei;
else if (DMDoe_clr & EMCLK_en) DMDoe <= #`db 0;
`endif
assign #`d0 emcDMD_oe = DMDoe;
assign #`d0 emcDMD_do[15:0] = DMDreg[15:0];
assign CMDlat = ECS10 & RWend;
always @(posedge ECMCLK2)
`ifdef FD_GTCLK
if(CMDlat) ECMDreg[23:0] <= #`db {T_EA[7:0], T_ED[15:0]};
`else
if(CMDlat & selECM) ECMDreg[23:0] <= #`db {T_EA[7:0], T_ED[15:0]};
`endif
assign CM_rdata[23:0] = selECM ? ECMDreg[23:0] : CM_rd[23:0];
assign #`da eRDY_h = selECM ? ENS11 : (ENS2 || ENS6) ;
always @(posedge DSPCLK or posedge PPclr) begin
if(PPclr) eRDY <= 0;
else if (~eRDY) eRDY <= #`db eRDY_h;
else if (GO_Fx) eRDY <= #`db 0;
end
endmodule
|
`include "../include/x_def.v"
module MEMC (/* ------------ Inputs : ------------- */
DSPCLK, T_RST, STBY, DMD,
PPclr_h, GO_Ex, GO_Cx,
redoM_h, redoSTI_h, redoLD_h, IDLE_ST,
DMOVL_dsp, PMOVL_dsp,
Pread_R, Pwrite_R, Dread_R, Dwrite_R,
IOcmd_R, IOread_R, IOwrite_R, Dummy_R,
Dummy_E,
DMA_R, PMA_R, DMA,
DMAin, PMAin,
SREQ, STEAL, DMSreqx_wr, PMSreqx_wr,
DMSreqx_rd, PMSreqx_rd,
BOOT, PMOVL, DMOVL,
DSreqx, DRDcyc,
selECM,
BM_cyc, ECYC,
`ifdef FD_DFT
SCAN_TEST,
`endif
PM_bdry_sel,
SP0_EN, selAUTO0, selFSDIV0, selSCLKDIV0,
selSCTL0, selMWORD0, AUTO0_we, FSDIV0_we,
SCLKDIV0_we, SCTL0_we, MWORD0_we,
SP1_EN, selAUTO1, selFSDIV1, selSCLKDIV1,
selSCTL1, selMWORD1, AUTO1_we, FSDIV1_we,
SCLKDIV1_we, SCTL1_we, MWORD1_we,
selPFTYPE, selPDATA, selPIMASK, selPINT,
PFTYPE_we, PDATA_we, PIMASK_we, PINT_we,
selTPERIOD, selTCOUNT, selTSCALE,
TPERIOD_we, TCOUNT_we, TSCALE_we,
Pread_E, Pwrite_E, Dread_E, Dwrite_E,
IOcmd_E, IOread_E, IOwrite_E, WSCR_we, WSCR_ext_we,
selWSCR, selWSCR_ext, EXTC_Eg, ECMWAIT, ECMAWAIT,
selCKR, CKR_we,
DWWAIT, DRWAIT, selDCTL, selDOVL,
DCTL_we, DOVL_we,
selSYSR, ldSREG_E, MMR_web,
TB_EN,
DwriteI_Eg, PwriteI_Eg, STI_Cg, LDaST_Eg,
BIASRND,
accPM_Eg, accDM_Eg,
PMo_cs0, PMo_cs1,
PMo_cs2, PMo_cs3,
PMo_cs4, PMo_cs5,
PMo_cs6, PMo_cs7,
PMo_web,
PMo_oe0, PMo_oe1,
PMo_oe2, PMo_oe3,
PMo_oe4, PMo_oe5,
PMo_oe6, PMo_oe7,
DM_cs,
DMo_cs0, DMo_cs1,
DMo_cs2, DMo_cs3,
DMo_cs4, DMo_cs5,
DMo_cs6, DMo_cs7,
DMo_web,
DM_oe,
DMo_oe0, DMo_oe1,
DMo_oe2, DMo_oe3,
DMo_oe4, DMo_oe5,
DMo_oe6, DMo_oe7,
selBIAD, selBEAD, selBCTL, selBCNT, selBOVL,
BCNT_we, BCTL_we, BOVL_we, BIAD_we, BEAD_we,
selIVER
);
input PM_bdry_sel;
input BM_cyc,
ECYC;
input DSreqx,
DRDcyc;
input [3:0] DMOVL_dsp;
input [7:4] PMOVL_dsp;
input [3:0] PMOVL,
DMOVL;
input [15:0] DMD;
input [13:5] DMA_R,
DMAin;
input [13:12] PMA_R,
PMAin;
input [13:0] DMA;
input DSPCLK,
T_RST,
PPclr_h,
GO_Ex,
GO_Cx,
Dummy_R,
Dummy_E,
STBY,
BOOT,
redoSTI_h,
redoLD_h,
IDLE_ST,
redoM_h,
Pread_R,
Pwrite_R,
Dread_R,
Dwrite_R,
IOcmd_R,
IOread_R,
IOwrite_R,
STEAL,
SREQ,
selECM,
PMSreqx_wr,
DMSreqx_wr,
PMSreqx_rd,
DMSreqx_rd;
`ifdef FD_DFT
input SCAN_TEST;
`endif
output [3:0] ECMWAIT;
output [1:0] ECMAWAIT;
output [2:0] DWWAIT,
DRWAIT;
output SP0_EN,
SP1_EN,
TB_EN,
BIASRND,
EXTC_Eg,
Pread_E,
Pwrite_E,
Dread_E,
Dwrite_E,
IOcmd_E,
IOread_E,
IOwrite_E,
accPM_Eg,
accDM_Eg,
MMR_web,
PMo_cs0,
PMo_cs1,
PMo_cs2,
PMo_cs3,
PMo_cs4,
PMo_cs5,
PMo_cs6,
PMo_cs7,
PMo_web,
PMo_oe0,
PMo_oe1,
PMo_oe2,
PMo_oe3,
PMo_oe4,
PMo_oe5,
PMo_oe6,
PMo_oe7,
DM_cs,
DMo_cs0,
DMo_cs1,
DMo_cs2,
DMo_cs3,
DMo_cs4,
DMo_cs5,
DMo_cs6,
DMo_cs7,
DMo_web,
DM_oe,
DMo_oe0,
DMo_oe1,
DMo_oe2,
DMo_oe3,
DMo_oe4,
DMo_oe5,
DMo_oe6,
DMo_oe7,
selIVER;
output
ldSREG_E,
DwriteI_Eg, PwriteI_Eg, STI_Cg,
LDaST_Eg,
selWSCR, selWSCR_ext, selAUTO0, selAUTO1, selFSDIV0,
selFSDIV1, selSCLKDIV0, selSCLKDIV1,
selSCTL0, selSCTL1, selMWORD0, selMWORD1,
selPFTYPE, selPDATA, selPIMASK, selPINT,
selTPERIOD, selTCOUNT, selTSCALE, selDCTL,
selDOVL, selCKR, selSYSR,
AUTO0_we, AUTO1_we, FSDIV0_we, FSDIV1_we,
SCLKDIV0_we, SCLKDIV1_we, SCTL0_we, SCTL1_we,
MWORD0_we, MWORD1_we, PFTYPE_we, PDATA_we,
PIMASK_we, PINT_we, TPERIOD_we, TCOUNT_we,
TSCALE_we, DCTL_we, DOVL_we, WSCR_we, WSCR_ext_we,
CKR_we;
output selBIAD, selBEAD, selBCTL, selBCNT, selBOVL,
BCNT_we, BCTL_we, BOVL_we, BIAD_we, BEAD_we;
wire [15:0] SYSR;
reg MMR_web;
reg IOcmd_E, IOread_E, IOwrite_E;
reg Dread_E, Dwrite_E, Pread_E,
Pwrite_E, Dwrite_C, Pwrite_C, ldSREG_E,
EXTC_E, EXTC_Eg, accPM_E, accDM_E, selMIO_E,
STI_Cg, LDaST_Eg;
wire RST, PMcyc, DMcyc, SYSR_we, Dread_R,
Dwrite_R, Pwrite_R, IOcmd_R,
DMo_cs0_nx, DMo_cs1_nx, DMo_oe0_nx,
DMo_oe1_nx, DMo_we_h0, DMo_we_h1,
PMo_cs0_nx, PMo_cs1_nx, PMo_oe0_nx,
PMo_oe1_nx, PMo_we_h0, PMo_we_h1,
Dwrite_Eng, EXTC_R, GO_STEAL,
ldSREG_R, EX_en, selMIO_R,
wrMMIOen_R;
wire Dread_Eh, Pread_Eh, Dwrite_Ch, Pwrite_Ch,
reLOAD, reSTORE;
wire MMIO_E, PwriteI_E, DwriteI_E, LDaST_Rg;
assign #`d0 RST = T_RST;
`ifdef FD_DFT
reg PPclr_o;
wire PPclr;
always @(posedge DSPCLK) begin
PPclr_o <= #`db T_RST || PPclr_h;
end
assign PPclr = SCAN_TEST ? T_RST : PPclr_o;
`else
reg PPclr;
always @(posedge DSPCLK) begin
PPclr <= #`db T_RST || PPclr_h;
end
`endif
assign #`da EX_en = !Dummy_E;
wire PM_rgn,
DM_rgn,
DM_main,
PM_page0,
PM_page1,
PM_page2,
PM_page3,
PM_page4,
PM_page5,
PM_page6,
PM_page7,
DM_page0,
DM_page1,
DM_page2,
DM_page3,
DM_page4,
DM_page5,
DM_page6,
DM_page7;
assign PM_rgn = PM_bdry_sel ? PMAin[13] :
(PMAin[13:12] == 2'b11);
assign #`da PM_page0 = PM_rgn && (PMOVL[3:0] == 4'h0);
assign #`da PM_page1 = PM_rgn && (PMOVL[3:0] == 4'h1);
assign #`da PM_page2 = PM_rgn && (PMOVL[3:0] == 4'h2);
assign #`da PM_page3 = PM_rgn && (PMOVL[3:0] == 4'h3);
assign #`da PM_page4 = PM_rgn && (PMOVL[3:0] == 4'h4);
assign #`da PM_page5 = PM_rgn && (PMOVL[3:0] == 4'h5);
assign #`da PM_page6 = PM_rgn && (PMOVL[3:0] == 4'h6);
assign #`da PM_page7 = PM_rgn && (PMOVL[3:0] == 4'h7);
assign #`da PMcyc = PM_page0 || PM_page1 || PM_page2 || PM_page3 ||
PM_page4 || PM_page5 || PM_page6 || PM_page7;
assign #`da DM_rgn = !DMAin[13];
assign #`da DM_main = DMAin[13] && !(DMAin[13:5] == 9'h1ff);
assign #`da DM_page0 = DM_rgn && (DMOVL[3:0] == 4'h0);
assign #`da DM_page1 = DM_rgn && (DMOVL[3:0] == 4'h1);
assign #`da DM_page2 = DM_rgn && (DMOVL[3:0] == 4'h2);
assign #`da DM_page3 = DM_rgn && (DMOVL[3:0] == 4'h3);
assign #`da DM_page4 = DM_rgn && (DMOVL[3:0] == 4'h4);
assign #`da DM_page5 = DM_rgn && (DMOVL[3:0] == 4'h5);
assign #`da DM_page6 = DM_rgn && (DMOVL[3:0] == 4'h6);
assign #`da DM_page7 = DM_rgn && (DMOVL[3:0] == 4'h7);
assign #`da DMcyc = DM_main || DM_page0 || DM_page1 || DM_page2 || DM_page3 ||
DM_page4 || DM_page5 || DM_page6 || DM_page7;
wire PM_brdy_R,
DM_brdy_R;
assign #`da PM_brdy_R = (PM_bdry_sel == 2'b00) ? (PMA_R[13:12] == 2'b11) :
(PM_bdry_sel == 2'b01) ? (PMA_R[13] == 1'b1) :
1'b1;
assign #`da DM_brdy_R = !DMA_R[13];
assign #`da EXTC_R = PM_brdy_R && PMOVL_dsp[7] && (Pread_R || Pwrite_R) ||
DM_brdy_R && DMOVL_dsp[3] && (Dread_R || Dwrite_R) ||
IOcmd_R;
always @(posedge DSPCLK or posedge PPclr) begin
if (PPclr) begin
EXTC_E <= #`db 0;
EXTC_Eg <= #`db selECM;
end
else if (GO_Ex) begin
EXTC_E <= #`db EXTC_R;
EXTC_Eg <= #`db EXTC_R && !Dummy_R || selECM;
end
end
assign #`d0 ECMAWAIT[1:0] = SYSR[15:14];
assign #`d0 {TB_EN, SP0_EN, SP1_EN, BIASRND} = SYSR[13:10];
assign #`d0 DWWAIT[2:0] = SYSR[9:7];
assign #`d0 DRWAIT[2:0] = SYSR[6:4];
assign #`d0 ECMWAIT[3:0] = SYSR[3:0];
`ifdef FD_DFT
MREG16MC usysr (DSPCLK, MMR_web, SYSR_we, DMD[15:0], SYSR[15:0], RST, SCAN_TEST);
`else
MREG16MC usysr (DSPCLK, MMR_web, SYSR_we, DMD[15:0], SYSR[15:0], RST);
`endif
assign #`da GO_STEAL = GO_Ex || STEAL || BOOT || STBY || BM_cyc && ECYC;
always @(posedge DSPCLK or posedge PPclr) begin
if (PPclr) begin
Dread_E <= #`db 1'b0;
Dwrite_E <= #`db 1'b0;
Pread_E <= #`db 1'b0;
Pwrite_E <= #`db 1'b0;
IOcmd_E <= #`db 1'b0;
IOread_E <= #`db 1'b0;
IOwrite_E <= #`db 1'b0;
end
else if (GO_Ex) begin
Dread_E <= #`db Dread_R && !Dummy_R;
Dwrite_E <= #`db Dwrite_R && !Dummy_R;
Pread_E <= #`db Pread_R && !Dummy_R;
Pwrite_E <= #`db Pwrite_R && !Dummy_R;
IOcmd_E <= #`db IOcmd_R && !Dummy_R;
IOread_E <= #`db IOread_R && !Dummy_R;
IOwrite_E <= #`db IOwrite_R && !Dummy_R;
end
end
assign #`da wrMMIOen_R = Dwrite_R && (DMA_R[13:5] == 9'h1ff);
always @(posedge DSPCLK or posedge PPclr)
if (PPclr) MMR_web <= #`db 1'b1;
else if (GO_Ex) MMR_web <= #`db !wrMMIOen_R;
always @(posedge DSPCLK or posedge PPclr) begin
if (PPclr) begin
Dwrite_C <= #`db 1'b0;
Pwrite_C <= #`db 1'b0;
end
else if (GO_Cx) begin
Dwrite_C <= #`db Dwrite_E;
Pwrite_C <= #`db Pwrite_E;
end
else if (IDLE_ST) begin
Dwrite_C <= #`db 1'b0;
Pwrite_C <= #`db 1'b0;
end
end
assign #`da reLOAD = redoLD_h || redoM_h;
assign #`da reSTORE = redoSTI_h;
assign #`da Pread_Eh = GO_Ex ? (Pread_R && !Dummy_R && !PwriteI_Eg && !SREQ) : Pread_E;
assign #`da Dread_Eh = GO_Ex ? (Dread_R && !Dummy_R && !DwriteI_Eg && !SREQ) : Dread_E;
assign #`da Pwrite_Ch = GO_Cx ? (PwriteI_E && !SREQ) : Pwrite_C;
assign #`da Dwrite_Ch = GO_Cx ? (DwriteI_E && !SREQ) : Dwrite_C;
always @(posedge DSPCLK or posedge PPclr) begin
if (PPclr) begin
accDM_E <= #`db 1'b0;
accPM_E <= #`db 1'b0;
end
else if (GO_Ex) begin
accDM_E <= #`db Dread_R || Dwrite_R;
accPM_E <= #`db Pread_R || Pwrite_R;
end
end
assign accDM_Eg = accDM_E && !Dummy_E;
assign accPM_Eg = accPM_E && !Dummy_E;
assign #`da Dwrite_Eng = Dwrite_E && EX_en && GO_Cx;
assign #`da SYSR_we = Dwrite_Eng && (DMA[13:0] == `pSYSR);
assign #`da CKR_we = Dwrite_Eng && (DMA[13:0] == `pCKR);
assign #`da WSCR_we = Dwrite_Eng && (DMA[13:0] == `pWSCR);
assign #`da WSCR_ext_we = Dwrite_Eng && (DMA[13:0] == `pWSCR_ext);
assign #`da DCTL_we = Dwrite_Eng && (DMA[13:0] == `pDCTL);
assign #`da DOVL_we = Dwrite_Eng && (DMA[13:0] == `pDOVL);
assign #`da AUTO0_we = Dwrite_Eng && (DMA == `pAUTO0);
assign #`da FSDIV0_we = Dwrite_Eng && (DMA == `pFSDIV0);
assign #`da SCLKDIV0_we = Dwrite_Eng && (DMA == `pSCLKDIV0);
assign #`da SCTL0_we = Dwrite_Eng && (DMA == `pSCTL0);
assign #`da MWORD0_we = Dwrite_Eng && (DMA == `pMWORD0);
assign #`da AUTO1_we = Dwrite_Eng && (DMA == `pAUTO1);
assign #`da FSDIV1_we = Dwrite_Eng && (DMA == `pFSDIV1);
assign #`da SCLKDIV1_we = Dwrite_Eng && (DMA == `pSCLKDIV1);
assign #`da SCTL1_we = Dwrite_Eng && (DMA == `pSCTL1);
assign #`da MWORD1_we = Dwrite_Eng && (DMA == `pMWORD1);
assign #`da PFTYPE_we = Dwrite_Eng && (DMA == `pPFTYPE);
assign #`da PDATA_we = Dwrite_Eng && (DMA == `pPDATA);
assign #`da PIMASK_we = Dwrite_Eng && (DMA == `pPIMASK);
assign #`da PINT_we = Dwrite_Eng && (DMA == `pPINT);
assign #`da TPERIOD_we = Dwrite_Eng && (DMA == `pTPERIOD);
assign #`da TCOUNT_we = Dwrite_Eng && (DMA == `pTCOUNT);
assign #`da TSCALE_we = Dwrite_Eng && (DMA == `pTSCALE);
assign #`da BCNT_we = Dwrite_Eng && (DMA == `pBCNT);
assign #`da BIAD_we = Dwrite_Eng && (DMA == `pBIAD);
assign #`da BEAD_we = Dwrite_Eng && (DMA == `pBEAD);
assign #`da BCTL_we = Dwrite_Eng && (DMA == `pBCTL);
assign #`da BOVL_we = Dwrite_Eng && (DMA == `pBOVL);
assign #`da selIVER = selMIO_E && (DMA[4:0] == 5'h0a);
assign #`da ldSREG_R = (Dread_Eh || DSreqx && DRDcyc) && (DMAin[13:5] == 9'h1ff);
assign #`da selMIO_R = (DMAin[13:5] == 9'h1ff);
assign #`da selSYSR = selMIO_E && (DMA[4:0] == 5'h1f);
assign #`da selCKR = selMIO_E && (DMA[4:0] == 5'h1a);
assign #`da selWSCR = selMIO_E && (DMA[4:0] == 5'h1e);
assign #`da selWSCR_ext = selMIO_E && (DMA[4:0] == 5'h0b);
assign #`da selDCTL = selMIO_E && (DMA[4:0] == 5'h0);
assign #`da selDOVL = selMIO_E && (DMA[4:0] == 5'h19);
assign #`da selAUTO0 = selMIO_E && (DMA[4:0] == 5'h13);
assign #`da selFSDIV0 = selMIO_E && (DMA[4:0] == 5'h14);
assign #`da selSCLKDIV0 = selMIO_E && (DMA[4:0] == 5'h15);
assign #`da selSCTL0 = selMIO_E && (DMA[4:0] == 5'h16);
assign #`da selMWORD0 = selMIO_E && (DMA[4:0] == 5'h17);
assign #`da selAUTO1 = selMIO_E && (DMA[4:0] == 5'h0f);
assign #`da selFSDIV1 = selMIO_E && (DMA[4:0] == 5'h10);
assign #`da selSCLKDIV1 = selMIO_E && (DMA[4:0] == 5'h11);
assign #`da selSCTL1 = selMIO_E && (DMA[4:0] == 5'h12);
assign #`da selMWORD1 = selMIO_E && (DMA[4:0] == 5'h18);
assign #`da selPFTYPE = selMIO_E && (DMA[4:0] == 5'h06);
assign #`da selPDATA = selMIO_E && (DMA[4:0] == 5'h05);
assign #`da selPIMASK = selMIO_E && (DMA[4:0] == 5'h07);
assign #`da selPINT = selMIO_E && (DMA[4:0] == 5'h08);
assign #`da selTPERIOD = selMIO_E && (DMA[4:0] == 5'h1d);
assign #`da selTCOUNT = selMIO_E && (DMA[4:0] == 5'h1c);
assign #`da selTSCALE = selMIO_E && (DMA[4:0] == 5'h1b);
assign #`da selBIAD = selMIO_E && (DMA == `pBIAD);
assign #`da selBEAD = selMIO_E && (DMA == `pBEAD);
assign #`da selBCTL = selMIO_E && (DMA == `pBCTL);
assign #`da selBCNT = selMIO_E && (DMA == `pBCNT);
assign #`da selBOVL = selMIO_E && (DMA == `pBOVL);
always @(posedge DSPCLK or posedge PPclr)
begin
if (PPclr) begin
ldSREG_E <= #`db 1'b0;
end
else if (GO_Ex || reLOAD) begin
ldSREG_E <= #`db ldSREG_R;
end
end
always @(posedge DSPCLK)
if (GO_Ex || reLOAD) selMIO_E <= #`db selMIO_R;
wire DMcs_en,
DMoe_en;
`ifdef FD_DFT
assign #`da DMcs_en = !SCAN_TEST &&
((Dread_Eh || Dwrite_Ch) ||
(DMSreqx_rd || DMSreqx_wr) && GO_STEAL);
`else
assign #`da DMcs_en = (Dread_Eh || Dwrite_Ch) ||
(DMSreqx_rd || DMSreqx_wr) && GO_STEAL;
`endif
assign #`da DM_cs = DM_main && DMcs_en;
assign #`da DMo_cs0 = DM_page0 && DMcs_en;
assign #`da DMo_cs1 = DM_page1 && DMcs_en;
assign #`da DMo_cs2 = DM_page2 && DMcs_en;
assign #`da DMo_cs3 = DM_page3 && DMcs_en;
assign #`da DMo_cs4 = DM_page4 && DMcs_en;
assign #`da DMo_cs5 = DM_page5 && DMcs_en;
assign #`da DMo_cs6 = DM_page6 && DMcs_en;
assign #`da DMo_cs7 = DM_page7 && DMcs_en;
assign #`da DMoe_en = (Dread_Eh || DMSreqx_rd && GO_STEAL);
`ifdef FD_DFT
reg DM_oe_h, DMo_oe0_h, DMo_oe1_h, DMo_oe2_h, DMo_oe3_h,
DMo_oe4_h, DMo_oe5_h, DMo_oe6_h, DMo_oe7_h;
wire DM_oe, DMo_oe0, DMo_oe1, DMo_oe2, DMo_oe3,
DMo_oe4, DMo_oe5, DMo_oe6, DMo_oe7;
always @(posedge DSPCLK)
begin
DM_oe_h <= #`db DM_main && DMoe_en;
DMo_oe0_h <= #`db DM_page0 && DMoe_en ;
DMo_oe1_h <= #`db DM_page1 && DMoe_en ;
DMo_oe2_h <= #`db DM_page2 && DMoe_en ;
DMo_oe3_h <= #`db DM_page3 && DMoe_en ;
DMo_oe4_h <= #`db DM_page4 && DMoe_en ;
DMo_oe5_h <= #`db DM_page5 && DMoe_en ;
DMo_oe6_h <= #`db DM_page6 && DMoe_en ;
DMo_oe7_h <= #`db DM_page7 && DMoe_en ;
end
assign DM_oe = DM_oe_h && !SCAN_TEST;
assign DMo_oe0 = DMo_oe0_h && !SCAN_TEST;
assign DMo_oe1 = DMo_oe1_h && !SCAN_TEST;
assign DMo_oe2 = DMo_oe2_h && !SCAN_TEST;
assign DMo_oe3 = DMo_oe3_h && !SCAN_TEST;
assign DMo_oe4 = DMo_oe4_h && !SCAN_TEST;
assign DMo_oe5 = DMo_oe5_h && !SCAN_TEST;
assign DMo_oe6 = DMo_oe6_h && !SCAN_TEST;
assign DMo_oe7 = DMo_oe7_h && !SCAN_TEST;
`else
reg DM_oe, DMo_oe0, DMo_oe1, DMo_oe2, DMo_oe3,
DMo_oe4, DMo_oe5, DMo_oe6, DMo_oe7;
always @(posedge DSPCLK)
begin
DM_oe <= #`db DM_main && DMoe_en ;
DMo_oe0 <= #`db DM_page0 && DMoe_en ;
DMo_oe1 <= #`db DM_page1 && DMoe_en ;
DMo_oe2 <= #`db DM_page2 && DMoe_en ;
DMo_oe3 <= #`db DM_page3 && DMoe_en ;
DMo_oe4 <= #`db DM_page4 && DMoe_en ;
DMo_oe5 <= #`db DM_page5 && DMoe_en ;
DMo_oe6 <= #`db DM_page6 && DMoe_en ;
DMo_oe7 <= #`db DM_page7 && DMoe_en ;
end
`endif
assign #`da DMo_we_h0 = DMcyc && Dwrite_Ch &&
(GO_Cx && !Dummy_E || redoSTI_h);
assign #`da DMo_we_h1 = DMcyc && DMSreqx_wr && GO_STEAL;
assign #`da DMo_web = !(DMo_we_h0 || DMo_we_h1);
wire PMcs_en,
PMoe_en;
`ifdef FD_DFT
assign #`da PMcs_en = !SCAN_TEST &&
((Pread_Eh || Pwrite_Ch) ||
(PMSreqx_rd || PMSreqx_wr) && GO_STEAL);
`else
assign #`da PMcs_en = (Pread_Eh || Pwrite_Ch) ||
(PMSreqx_rd || PMSreqx_wr) && GO_STEAL;
`endif
assign #`da PMo_cs0 = PM_page0 && PMcs_en;
assign #`da PMo_cs1 = PM_page1 && PMcs_en;
assign #`da PMo_cs2 = PM_page2 && PMcs_en;
assign #`da PMo_cs3 = PM_page3 && PMcs_en;
assign #`da PMo_cs4 = PM_page4 && PMcs_en;
assign #`da PMo_cs5 = PM_page5 && PMcs_en;
assign #`da PMo_cs6 = PM_page6 && PMcs_en;
assign #`da PMo_cs7 = PM_page7 && PMcs_en;
assign #`da PMoe_en = (Pread_Eh || PMSreqx_rd && GO_STEAL);
`ifdef FD_DFT
reg PMo_oe0_h, PMo_oe1_h, PMo_oe2_h, PMo_oe3_h,
PMo_oe4_h, PMo_oe5_h, PMo_oe6_h, PMo_oe7_h;
wire PMo_oe0, PMo_oe1, PMo_oe2, PMo_oe3,
PMo_oe4, PMo_oe5, PMo_oe6, PMo_oe7;
always @(posedge DSPCLK)
begin
PMo_oe0_h <= #`db PM_page0 && PMoe_en ;
PMo_oe1_h <= #`db PM_page1 && PMoe_en ;
PMo_oe2_h <= #`db PM_page2 && PMoe_en ;
PMo_oe3_h <= #`db PM_page3 && PMoe_en ;
PMo_oe4_h <= #`db PM_page4 && PMoe_en ;
PMo_oe5_h <= #`db PM_page5 && PMoe_en ;
PMo_oe6_h <= #`db PM_page6 && PMoe_en ;
PMo_oe7_h <= #`db PM_page7 && PMoe_en ;
end
assign PMo_oe0 = PMo_oe0_h && !SCAN_TEST;
assign PMo_oe1 = PMo_oe1_h && !SCAN_TEST;
assign PMo_oe2 = PMo_oe2_h && !SCAN_TEST;
assign PMo_oe3 = PMo_oe3_h && !SCAN_TEST;
assign PMo_oe4 = PMo_oe4_h && !SCAN_TEST;
assign PMo_oe5 = PMo_oe5_h && !SCAN_TEST;
assign PMo_oe6 = PMo_oe6_h && !SCAN_TEST;
assign PMo_oe7 = PMo_oe7_h && !SCAN_TEST;
`else
reg PMo_oe0, PMo_oe1, PMo_oe2, PMo_oe3,
PMo_oe4, PMo_oe5, PMo_oe6, PMo_oe7;
always @(posedge DSPCLK)
begin
PMo_oe0 <= #`db PM_page0 && PMoe_en ;
PMo_oe1 <= #`db PM_page1 && PMoe_en ;
PMo_oe2 <= #`db PM_page2 && PMoe_en ;
PMo_oe3 <= #`db PM_page3 && PMoe_en ;
PMo_oe4 <= #`db PM_page4 && PMoe_en ;
PMo_oe5 <= #`db PM_page5 && PMoe_en ;
PMo_oe6 <= #`db PM_page6 && PMoe_en ;
PMo_oe7 <= #`db PM_page7 && PMoe_en ;
end
`endif
assign #`da PMo_we_h0 = PMcyc && Pwrite_Ch &&
(GO_Ex && !Dummy_E || redoSTI_h);
assign #`da PMo_we_h1 = PMcyc && PMSreqx_wr && GO_STEAL ;
assign #`da PMo_web = !(PMo_we_h0 || PMo_we_h1);
assign #`da MMIO_E = (DMA[13:5] == 9'h1ff);
assign #`da PwriteI_E = Pwrite_E && !EXTC_E ;
assign #`da DwriteI_E = Dwrite_E && !EXTC_E && !MMIO_E;
assign #`da PwriteI_Eg = Pwrite_E && !EXTC_E && !Dummy_E;
assign #`da DwriteI_Eg = Dwrite_E && !EXTC_E && !MMIO_E && !Dummy_E;
assign #`da LDaST_Rg = !(Dummy_E || Dummy_R) &&
((PwriteI_E && Pread_R) || (DwriteI_E && Dread_R));
always @(posedge DSPCLK or posedge PPclr) begin
if (PPclr) LDaST_Eg <= #`db 1'b0;
else if (GO_Ex) LDaST_Eg <= #`db LDaST_Rg;
end
always @(posedge DSPCLK or posedge PPclr) begin
if (PPclr) STI_Cg <= #`db 1'b0;
else if (GO_Cx) STI_Cg <= #`db DwriteI_Eg || PwriteI_Eg;
end
endmodule
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