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`include "../include/x_def.v"
module PIO(
DSPCLK, T_RST, DMD, PIO_IN,
selPMASK, selPINT, selPFTYPE, selPFDATA,
PMASK_we, PINT_we, PFTYPE_we, PFDATA_we,
MMR_web,
`ifdef FD_DFT
SCAN_TEST,
`endif
PIO_INTn, PIO_DMD, PIO_EN, PIO_OUT);
input DSPCLK;
input T_RST;
input selPMASK;
input selPINT;
input selPFTYPE;
input selPFDATA;
input PMASK_we;
input PINT_we;
input PFTYPE_we;
input PFDATA_we;
input [11:0] PIO_IN;
input [15:0] DMD;
input MMR_web;
`ifdef FD_DFT
input SCAN_TEST;
`endif
output PIO_INTn;
output [15:0] PIO_DMD;
output [11:0] PIO_OUT;
output [11:0] PIO_EN;
/*-----------------------------------------------------*/
wire [11:0] PIO_IN;
wire [11:0] PIO_OUT;
wire [11:0] PIO_EN;
/*------------------------------------------------------*/
/*------------------------------------------------------*/
/*------------------------------------------------------*/
/*------------------------------------------------------*/
/*------------------------------------------------------*/
wire [11:0] PMASK;
`ifdef FD_DFT
REG12LC pmask_reg(DSPCLK, MMR_web, PMASK_we, {DMD[15:12], DMD[7:0]}, PMASK[11:0],
T_RST, SCAN_TEST);
`else
REG12LC pmask_reg(DSPCLK, MMR_web, PMASK_we, {DMD[15:12], DMD[7:0]}, PMASK[11:0], T_RST);
`endif
/*-----------------------------------------------------*/
wire [11:0] PFTYPE;
`ifdef FD_DFT
REG12LC pftype_reg(DSPCLK, MMR_web, PFTYPE_we, {DMD[15:12], DMD[7:0]}, PFTYPE[11:0],
T_RST, SCAN_TEST);
`else
REG12LC pftype_reg(DSPCLK, MMR_web, PFTYPE_we, {DMD[15:12], DMD[7:0]}, PFTYPE[11:0], T_RST);
`endif
/*-----------------------------------------------------*/
`ifdef FD_GTCLK
`ifdef FD_DFT
GTECH_AND3 uk00 (.Z(CKenb0_dft), .A(MMR_web), .B(PFTYPE[0]), .C(PFTYPE[1]));
GTECH_AND3 uk10 (.Z(CKenb1_dft), .A(MMR_web), .B(PFTYPE[2]), .C(PFTYPE[3]));
GTECH_AND3 uk20 (.Z(CKenb2_dft), .A(MMR_web), .B(PFTYPE[4]), .C(PFTYPE[5]));
GTECH_AND3 uk30 (.Z(CKenb3_dft), .A(MMR_web), .B(PFTYPE[6]), .C(PFTYPE[7]));
GTECH_AND3 uk40 (.Z(CKenb4_dft), .A(MMR_web), .B(PFTYPE[8]), .C(PFTYPE[9]));
GTECH_AND3 uk50 (.Z(CKenb5_dft), .A(MMR_web), .B(PFTYPE[10]), .C(PFTYPE[11]));
GTECH_AND_NOT utm0 (.Z(CKenb0), .A(CKenb0_dft), .B(SCAN_TEST));
GTECH_AND_NOT utm1 (.Z(CKenb1), .A(CKenb1_dft), .B(SCAN_TEST));
GTECH_AND_NOT utm2 (.Z(CKenb2), .A(CKenb2_dft), .B(SCAN_TEST));
GTECH_AND_NOT utm3 (.Z(CKenb3), .A(CKenb3_dft), .B(SCAN_TEST));
GTECH_AND_NOT utm4 (.Z(CKenb4), .A(CKenb4_dft), .B(SCAN_TEST));
GTECH_AND_NOT utm5 (.Z(CKenb5), .A(CKenb5_dft), .B(SCAN_TEST));
`else
GTECH_AND3 uk00 (.Z(CKenb0), .A(MMR_web), .B(PFTYPE[0]), .C(PFTYPE[1]));
GTECH_AND3 uk10 (.Z(CKenb1), .A(MMR_web), .B(PFTYPE[2]), .C(PFTYPE[3]));
GTECH_AND3 uk20 (.Z(CKenb2), .A(MMR_web), .B(PFTYPE[4]), .C(PFTYPE[5]));
GTECH_AND3 uk30 (.Z(CKenb3), .A(MMR_web), .B(PFTYPE[6]), .C(PFTYPE[7]));
GTECH_AND3 uk40 (.Z(CKenb4), .A(MMR_web), .B(PFTYPE[8]), .C(PFTYPE[9]));
GTECH_AND3 uk50 (.Z(CKenb5), .A(MMR_web), .B(PFTYPE[10]), .C(PFTYPE[11]));
`endif
GTECH_NOR2 uk01 (.Z(PIOCLK0_), .A(DSPCLK), .B(CKenb0));
GtCLK_NOT ckPIOCLK0 (.Z(PIOCLK0), .A(PIOCLK0_));
GTECH_NOR2 uk11 (.Z(PIOCLK1_), .A(DSPCLK), .B(CKenb1));
GtCLK_NOT ckPIOCLK1 (.Z(PIOCLK1), .A(PIOCLK1_));
GTECH_NOR2 uk21 (.Z(PIOCLK2_), .A(DSPCLK), .B(CKenb2));
GtCLK_NOT ckPIOCLK2 (.Z(PIOCLK2), .A(PIOCLK2_));
GTECH_NOR2 uk31 (.Z(PIOCLK3_), .A(DSPCLK), .B(CKenb3));
GtCLK_NOT ckPIOCLK3 (.Z(PIOCLK3), .A(PIOCLK3_));
GTECH_NOR2 uk41 (.Z(PIOCLK4_), .A(DSPCLK), .B(CKenb4));
GtCLK_NOT ckPIOCLK4 (.Z(PIOCLK4), .A(PIOCLK4_));
GTECH_NOR2 uk51 (.Z(PIOCLK5_), .A(DSPCLK), .B(CKenb5));
GtCLK_NOT ckPIOCLK5 (.Z(PIOCLK5), .A(PIOCLK5_));
`else
wire PIOCLK0_en=!(MMR_web & PFTYPE[0] & PFTYPE[1]);
wire PIOCLK1_en=!(MMR_web & PFTYPE[2] & PFTYPE[3]);
wire PIOCLK2_en=!(MMR_web & PFTYPE[4] & PFTYPE[5]);
wire PIOCLK3_en=!(MMR_web & PFTYPE[6] & PFTYPE[7]);
wire PIOCLK4_en=!(MMR_web & PFTYPE[8] & PFTYPE[9]);
wire PIOCLK5_en=!(MMR_web & PFTYPE[10] & PFTYPE[11]);
wire PIOCLK0=DSPCLK;
wire PIOCLK1=DSPCLK;
wire PIOCLK2=DSPCLK;
wire PIOCLK3=DSPCLK;
wire PIOCLK4=DSPCLK;
wire PIOCLK5=DSPCLK;
`endif
reg [11:0] PFDATA;
reg [11:0] PIO_RES;
always @(posedge PIOCLK5 or posedge T_RST)
begin
if (T_RST)
PFDATA[11] <= #1 1'b0;
`ifdef FD_GTCLK
else if (!PFTYPE[11])
PFDATA[11] <= #1 PIO_RES[11];
else if (PFDATA_we)
PFDATA[11] <= #1 DMD[15];
else
PFDATA[11] <= #1 PFDATA[11];
`else
else if (!PFTYPE[11] & PIOCLK5_en)
PFDATA[11] <= #1 PIO_RES[11];
else if (PFDATA_we & PIOCLK5_en)
PFDATA[11] <= #1 DMD[15];
else if(PIOCLK5_en)
PFDATA[11] <= #1 PFDATA[11];
`endif
end
always @(posedge PIOCLK5 or posedge T_RST)
begin
if (T_RST)
PFDATA[10] <= #1 1'b0;
`ifdef FD_GTCLK
else if (!PFTYPE[10])
PFDATA[10] <= #1 PIO_RES[10];
else if (PFDATA_we)
PFDATA[10] <= #1 DMD[14];
else
PFDATA[10] <= #1 PFDATA[10];
`else
else if (!PFTYPE[10] & PIOCLK5_en)
PFDATA[10] <= #1 PIO_RES[10];
else if (PFDATA_we & PIOCLK5_en)
PFDATA[10] <= #1 DMD[14];
else if(PIOCLK5_en)
PFDATA[10] <= #1 PFDATA[10];
`endif
end
always @(posedge PIOCLK4 or posedge T_RST)
begin
if (T_RST)
PFDATA[9] <= #1 1'b0;
`ifdef FD_GTCLK
else if (!PFTYPE[9])
PFDATA[9] <= #1 PIO_RES[9];
else if (PFDATA_we)
PFDATA[9] <= #1 DMD[13];
else
PFDATA[9] <= #1 PFDATA[9];
`else
else if (!PFTYPE[9] & PIOCLK4_en)
PFDATA[9] <= #1 PIO_RES[9];
else if (PFDATA_we & PIOCLK4_en)
PFDATA[9] <= #1 DMD[13];
else if(PIOCLK4_en)
PFDATA[9] <= #1 PFDATA[9];
`endif
end
always @(posedge PIOCLK4 or posedge T_RST)
begin
if (T_RST)
PFDATA[8] <= #1 1'b0;
`ifdef FD_GTCLK
else if (!PFTYPE[8])
PFDATA[8] <= #1 PIO_RES[8];
else if (PFDATA_we)
PFDATA[8] <= #1 DMD[12];
else
PFDATA[8] <= #1 PFDATA[8];
`else
else if (!PFTYPE[8] & PIOCLK4_en)
PFDATA[8] <= #1 PIO_RES[8];
else if (PFDATA_we & PIOCLK4_en)
PFDATA[8] <= #1 DMD[12];
else if(PIOCLK4_en)
PFDATA[8] <= #1 PFDATA[8];
`endif
end
always @(posedge PIOCLK3 or posedge T_RST)
begin
if (T_RST)
PFDATA[7] <= #1 1'b0;
`ifdef FD_GTCLK
else if (!PFTYPE[7])
PFDATA[7] <= #1 PIO_RES[7];
else if (PFDATA_we)
PFDATA[7] <= #1 DMD[7];
else
PFDATA[7] <= #1 PFDATA[7];
`else
else if (!PFTYPE[7] & PIOCLK3_en)
PFDATA[7] <= #1 PIO_RES[7];
else if (PFDATA_we & PIOCLK3_en)
PFDATA[7] <= #1 DMD[7];
else if(PIOCLK3_en)
PFDATA[7] <= #1 PFDATA[7];
`endif
end
always @(posedge PIOCLK3 or posedge T_RST)
begin
if (T_RST)
PFDATA[6] <= #1 1'b0;
`ifdef FD_GTCLK
else if (!PFTYPE[6])
PFDATA[6] <= #1 PIO_RES[6];
else if (PFDATA_we)
PFDATA[6] <= #1 DMD[6];
else
PFDATA[6] <= #1 PFDATA[6];
`else
else if (!PFTYPE[6] & PIOCLK3_en)
PFDATA[6] <= #1 PIO_RES[6];
else if (PFDATA_we & PIOCLK3_en)
PFDATA[6] <= #1 DMD[6];
else if(PIOCLK3_en)
PFDATA[6] <= #1 PFDATA[6];
`endif
end
always @(posedge PIOCLK2 or posedge T_RST)
begin
if (T_RST)
PFDATA[5] <= #1 1'b0;
`ifdef FD_GTCLK
else if (!PFTYPE[5])
PFDATA[5] <= #1 PIO_RES[5];
else if (PFDATA_we)
PFDATA[5] <= #1 DMD[5];
else
PFDATA[5] <= #1 PFDATA[5];
`else
else if (!PFTYPE[5] & PIOCLK2_en)
PFDATA[5] <= #1 PIO_RES[5];
else if (PFDATA_we & PIOCLK2_en)
PFDATA[5] <= #1 DMD[5];
else if(PIOCLK2_en)
PFDATA[5] <= #1 PFDATA[5];
`endif
end
always @(posedge PIOCLK2 or posedge T_RST)
begin
if (T_RST)
PFDATA[4] <= #1 1'b0;
`ifdef FD_GTCLK
else if (!PFTYPE[4])
PFDATA[4] <= #1 PIO_RES[4];
else if (PFDATA_we)
PFDATA[4] <= #1 DMD[4];
else
PFDATA[4] <= #1 PFDATA[4];
`else
else if (!PFTYPE[4] & PIOCLK2_en)
PFDATA[4] <= #1 PIO_RES[4];
else if (PFDATA_we & PIOCLK2_en)
PFDATA[4] <= #1 DMD[4];
else if(PIOCLK2_en)
PFDATA[4] <= #1 PFDATA[4];
`endif
end
always @(posedge PIOCLK1 or posedge T_RST)
begin
if (T_RST)
PFDATA[3] <= #1 1'b0;
`ifdef FD_GTCLK
else if (!PFTYPE[3])
PFDATA[3] <= #1 PIO_RES[3];
else if (PFDATA_we)
PFDATA[3] <= #1 DMD[3];
else
PFDATA[3] <= #1 PFDATA[3];
`else
else if (!PFTYPE[3] & PIOCLK1_en)
PFDATA[3] <= #1 PIO_RES[3];
else if (PFDATA_we & PIOCLK1_en)
PFDATA[3] <= #1 DMD[3];
else if(PIOCLK1_en)
PFDATA[3] <= #1 PFDATA[3];
`endif
end
always @(posedge PIOCLK1 or posedge T_RST)
begin
if (T_RST)
PFDATA[2] <= #1 1'b0;
`ifdef FD_GTCLK
else if (!PFTYPE[2])
PFDATA[2] <= #1 PIO_RES[2];
else if (PFDATA_we)
PFDATA[2] <= #1 DMD[2];
else
PFDATA[2] <= #1 PFDATA[2];
`else
else if (!PFTYPE[2] & PIOCLK1_en)
PFDATA[2] <= #1 PIO_RES[2];
else if (PFDATA_we & PIOCLK1_en)
PFDATA[2] <= #1 DMD[2];
else if(PIOCLK1_en)
PFDATA[2] <= #1 PFDATA[2];
`endif
end
always @(posedge PIOCLK0 or posedge T_RST)
begin
if (T_RST)
PFDATA[1] <= #1 1'b0;
`ifdef FD_GTCLK
else if (!PFTYPE[1])
PFDATA[1] <= #1 PIO_RES[1];
else if (PFDATA_we)
PFDATA[1] <= #1 DMD[1];
else
PFDATA[1] <= #1 PFDATA[1];
`else
else if (!PFTYPE[1] & PIOCLK0_en)
PFDATA[1] <= #1 PIO_RES[1];
else if (PFDATA_we & PIOCLK0_en)
PFDATA[1] <= #1 DMD[1];
else if(PIOCLK0_en)
PFDATA[1] <= #1 PFDATA[1];
`endif
end
always @(posedge PIOCLK0 or posedge T_RST)
begin
if (T_RST)
PFDATA[0] <= #1 1'b0;
`ifdef FD_GTCLK
else if (!PFTYPE[0])
PFDATA[0] <= #1 PIO_RES[0];
else if (PFDATA_we)
PFDATA[0] <= #1 DMD[0];
else
PFDATA[0] <= #1 PFDATA[0];
`else
else if (!PFTYPE[0] & PIOCLK0_en)
PFDATA[0] <= #1 PIO_RES[0];
else if (PFDATA_we & PIOCLK0_en)
PFDATA[0] <= #1 DMD[0];
else if(PIOCLK0_en)
PFDATA[0] <= #1 PFDATA[0];
`endif
end
/*-----------------------------------------------------------*/
/*--------------------------------------*/
/*--------------------------------------*/
reg [11:0] PIO_IN_P;
wire [11:0] PIO_RES_in;
wire [11:0] PIO_RES0;
wire [11:0] PIO_RES1;
always @(posedge PIOCLK5)
`ifdef FD_GTCLK
`else
if(PIOCLK5_en)
`endif
PIO_IN_P[11] <= #`da PIO_IN[11];
always @(posedge PIOCLK5)
`ifdef FD_GTCLK
`else
if(PIOCLK5_en)
`endif
PIO_IN_P[10] <= #`da PIO_IN[10];
always @(posedge PIOCLK4)
`ifdef FD_GTCLK
`else
if(PIOCLK4_en)
`endif
PIO_IN_P[9] <= #`da PIO_IN[9];
always @(posedge PIOCLK4)
`ifdef FD_GTCLK
`else
if(PIOCLK4_en)
`endif
PIO_IN_P[8] <= #`da PIO_IN[8];
always @(posedge PIOCLK3)
`ifdef FD_GTCLK
`else
if(PIOCLK3_en)
`endif
PIO_IN_P[7] <= #`da PIO_IN[7];
always @(posedge PIOCLK3)
`ifdef FD_GTCLK
`else
if(PIOCLK3_en)
`endif
PIO_IN_P[6] <= #`da PIO_IN[6];
always @(posedge PIOCLK2)
`ifdef FD_GTCLK
`else
if(PIOCLK2_en)
`endif
PIO_IN_P[5] <= #`da PIO_IN[5];
always @(posedge PIOCLK2)
`ifdef FD_GTCLK
`else
if(PIOCLK2_en)
`endif
PIO_IN_P[4] <= #`da PIO_IN[4];
always @(posedge PIOCLK1)
`ifdef FD_GTCLK
`else
if(PIOCLK1_en)
`endif
PIO_IN_P[3] <= #`da PIO_IN[3];
always @(posedge PIOCLK1)
`ifdef FD_GTCLK
`else
if(PIOCLK1_en)
`endif
PIO_IN_P[2] <= #`da PIO_IN[2];
always @(posedge PIOCLK0)
`ifdef FD_GTCLK
`else
if(PIOCLK0_en)
`endif
PIO_IN_P[1] <= #`da PIO_IN[1];
always @(posedge PIOCLK0)
`ifdef FD_GTCLK
`else
if(PIOCLK0_en)
`endif
PIO_IN_P[0] <= #`da PIO_IN[0];
assign PIO_RES0[11:0] = PIO_IN[11:0] & PIO_IN_P[11:0];
assign PIO_RES1[11:0] = PIO_IN[11:0] | PIO_IN_P[11:0];
assign PIO_RES_in[11] = PIO_RES[11] ? PIO_RES1[11] : PIO_RES0[11];
assign PIO_RES_in[10] = PIO_RES[10] ? PIO_RES1[10] : PIO_RES0[10];
assign PIO_RES_in[9] = PIO_RES[9] ? PIO_RES1[9] : PIO_RES0[9];
assign PIO_RES_in[8] = PIO_RES[8] ? PIO_RES1[8] : PIO_RES0[8];
assign PIO_RES_in[7] = PIO_RES[7] ? PIO_RES1[7] : PIO_RES0[7];
assign PIO_RES_in[6] = PIO_RES[6] ? PIO_RES1[6] : PIO_RES0[6];
assign PIO_RES_in[5] = PIO_RES[5] ? PIO_RES1[5] : PIO_RES0[5];
assign PIO_RES_in[4] = PIO_RES[4] ? PIO_RES1[4] : PIO_RES0[4];
assign PIO_RES_in[3] = PIO_RES[3] ? PIO_RES1[3] : PIO_RES0[3];
assign PIO_RES_in[2] = PIO_RES[2] ? PIO_RES1[2] : PIO_RES0[2];
assign PIO_RES_in[1] = PIO_RES[1] ? PIO_RES1[1] : PIO_RES0[1];
assign PIO_RES_in[0] = PIO_RES[0] ? PIO_RES1[0] : PIO_RES0[0];
always @(posedge PIOCLK0 or posedge T_RST)
if (T_RST)
PIO_RES[1:0] <= #1 2'b0;
`ifdef FD_GTCLK
else
`else
else if(PIOCLK0_en)
`endif
PIO_RES[1:0] <= PIO_RES_in[1:0];
always @(posedge PIOCLK1 or posedge T_RST)
if (T_RST)
PIO_RES[3:2] <= #1 2'b0;
`ifdef FD_GTCLK
else
`else
else if(PIOCLK1_en)
`endif
PIO_RES[3:2] <= PIO_RES_in[3:2];
always @(posedge PIOCLK2 or posedge T_RST)
if (T_RST)
PIO_RES[5:4] <= #1 2'b0;
`ifdef FD_GTCLK
else
`else
else if(PIOCLK2_en)
`endif
PIO_RES[5:4] <= PIO_RES_in[5:4];
always @(posedge PIOCLK3 or posedge T_RST)
if (T_RST)
PIO_RES[7:6] <= #1 2'b0;
`ifdef FD_GTCLK
else
`else
else if(PIOCLK3_en)
`endif
PIO_RES[7:6] <= PIO_RES_in[7:6];
always @(posedge PIOCLK4 or posedge T_RST)
if (T_RST)
PIO_RES[9:8] <= #1 2'b0;
`ifdef FD_GTCLK
else
`else
else if(PIOCLK4_en)
`endif
PIO_RES[9:8] <= PIO_RES_in[9:8];
always @(posedge PIOCLK5 or posedge T_RST)
if (T_RST)
PIO_RES[11:10] <= #1 2'b0;
`ifdef FD_GTCLK
else
`else
else if(PIOCLK5_en)
`endif
PIO_RES[11:10] <= PIO_RES_in[11:10];
/*--------------------------------------*/
/*--------------------------------------*/
reg [11:0] PIO_RES_OUT;
reg [11:0] PINT;
wire [11:0] PINT_in;
wire [11:0] PIO_RES_T;
always @(posedge PIOCLK0)
`ifdef FD_GTCLK
`else
if(PIOCLK0_en)
`endif
PIO_RES_OUT[1:0] <= #1 PIO_RES[1:0];
always @(posedge PIOCLK1)
`ifdef FD_GTCLK
`else
if(PIOCLK1_en)
`endif
PIO_RES_OUT[3:2] <= #1 PIO_RES[3:2];
always @(posedge PIOCLK2)
`ifdef FD_GTCLK
`else
if(PIOCLK2_en)
`endif
PIO_RES_OUT[5:4] <= #1 PIO_RES[5:4];
always @(posedge PIOCLK3)
`ifdef FD_GTCLK
`else
if(PIOCLK3_en)
`endif
PIO_RES_OUT[7:6] <= #1 PIO_RES[7:6];
always @(posedge PIOCLK4)
`ifdef FD_GTCLK
`else
if(PIOCLK4_en)
`endif
PIO_RES_OUT[9:8] <= #1 PIO_RES[9:8];
always @(posedge PIOCLK5)
`ifdef FD_GTCLK
`else
if(PIOCLK5_en)
`endif
PIO_RES_OUT[11:10] <= #1 PIO_RES[11:10];
assign PIO_RES_T[11:0] = PIO_RES[11:0] ^ PIO_RES_OUT[11:0];
assign PINT_in[11] = PIO_RES_T[11] & (~PFTYPE[11]) & PMASK[11] ? 1'b1 : PINT[11];
assign PINT_in[10] = PIO_RES_T[10] & (~PFTYPE[10]) & PMASK[10] ? 1'b1 : PINT[10];
assign PINT_in[9] = PIO_RES_T[9] & (~PFTYPE[9]) & PMASK[9] ? 1'b1 : PINT[9];
assign PINT_in[8] = PIO_RES_T[8] & (~PFTYPE[8]) & PMASK[8] ? 1'b1 : PINT[8];
assign PINT_in[7] = PIO_RES_T[7] & (~PFTYPE[7]) & PMASK[7] ? 1'b1 : PINT[7];
assign PINT_in[6] = PIO_RES_T[6] & (~PFTYPE[6]) & PMASK[6] ? 1'b1 : PINT[6];
assign PINT_in[5] = PIO_RES_T[5] & (~PFTYPE[5]) & PMASK[5] ? 1'b1 : PINT[5];
assign PINT_in[4] = PIO_RES_T[4] & (~PFTYPE[4]) & PMASK[4] ? 1'b1 : PINT[4];
assign PINT_in[3] = PIO_RES_T[3] & (~PFTYPE[3]) & PMASK[3] ? 1'b1 : PINT[3];
assign PINT_in[2] = PIO_RES_T[2] & (~PFTYPE[2]) & PMASK[2] ? 1'b1 : PINT[2];
assign PINT_in[1] = PIO_RES_T[1] & (~PFTYPE[1]) & PMASK[1] ? 1'b1 : PINT[1];
assign PINT_in[0] = PIO_RES_T[0] & (~PFTYPE[0]) & PMASK[0] ? 1'b1 : PINT[0];
always @(posedge DSPCLK or posedge T_RST)
begin
if (T_RST)
PINT[11:0] <= #1 12'b0;
else if (PINT_we)
PINT[11:0] <= #1 {DMD[15:12], DMD[7:0]};
else
PINT[11:0] <= #1 PINT_in[11:0];
end
/*--------------------------------------*/
/*--------------------------------------*/
wire PIO_INTn;
assign PIO_INTn = ~(|(PMASK[11:0] & PINT[11:0]));
/*-----------------------------------------------------------------*/
/*--------------------------------------*/
/*--------------------------------------*/
assign PIO_OUT[11:0] = PFDATA[11:0];
assign PIO_EN[11:0] = PFTYPE[11:0];
/*-----------------------------------------------------------------*/
/*--------------------------------------*/
/*--------------------------------------*/
assign PIO_DMD[15:0] = ({16{selPMASK}} & {PMASK[11:8], 4'b0, PMASK[7:0]})
| ({16{selPINT}} & {PINT[11:8], 4'b0, PINT[7:0]})
| ({16{selPFTYPE}} & {PFTYPE[11:8], 4'b0, PFTYPE[7:0]})
| ({16{selPFDATA}} & {PFDATA[11:8], 4'b0, PFDATA[7:0]});
endmodule
|
`include "../include/x_def.v"
module CNTstk (/* in */ T_RST, DSPCLK, CNTin, PushCNT_EN, PopCNT_EN,
CNS_CKenb,
`ifdef FD_DFT
SCAN_TEST,
`endif
TopCNT, CNT_full, CNT_empty, CNT_has1);
input [13:0] CNTin;
input T_RST, DSPCLK, PushCNT_EN, PopCNT_EN, CNS_CKenb;
`ifdef FD_DFT
input SCAN_TEST;
`endif
output [13:0] TopCNT;
output CNT_empty,
CNT_full,
CNT_has1;
reg [2:0] ptr;
wire [13:0] stkin;
wire [2:0] ptr_in, ptr_p, ptr_m;
wire [1:0] WA, RA;
wire WE;
wire pop, push;
`ifdef FD_GTCLK
`ifdef FD_DFT
GTECH_AND_NOT utm1 (.Z(CNS_CKenb_dft), .A(CNS_CKenb), .B(SCAN_TEST));
GTECH_NOR2 uk0 (.Z(CNSCLK_), .A(DSPCLK), .B(CNS_CKenb_dft));
GtCLK_NOT ckCNSCLK (.Z(CNSCLK), .A(CNSCLK_));
`else
GTECH_NOR2 uk0 (.Z(CNSCLK_), .A(DSPCLK), .B(CNS_CKenb));
GtCLK_NOT ckCNSCLK (.Z(CNSCLK), .A(CNSCLK_));
`endif
`else
wire CNSCLK_en=!CNS_CKenb;
wire CNSCLK = DSPCLK;
`endif
assign push = PushCNT_EN && !CNT_full;
assign pop = PopCNT_EN && !CNT_empty;
assign stkin[13:0] = CNTin[13:0];
assign ptr_p[2:0] = ptr[2:0] + 1'b1;
assign ptr_m[2:0] = ptr[2:0] - 1'b1;
assign ptr_in[2:0] = push ? ptr_p[2:0] : ptr_m[2:0];
always @(posedge CNSCLK or posedge T_RST) begin
if (T_RST) ptr[2:0] <= #1 3'b111;
`ifdef FD_GTCLK
else if (push || pop) ptr[2:0] <= #1 ptr_in[2:0];
`else
else if ((push || pop) & CNSCLK_en) ptr[2:0] <= #1 ptr_in[2:0];
`endif
end
assign CNT_empty = ptr[2];
assign CNT_full = (ptr[2:0] == 3'h3);
assign CNT_has1 = (ptr[2:0] == 3'h0);
`ifdef FD_GTCLK
assign WE = push;
`else
assign WE = push & CNSCLK_en;
`endif
assign WA[1:0] = ptr_p[1:0];
assign RA[1:0] = ptr[1:0];
CNTS4x14 cnts4x14 (CNSCLK, WE, WA[1:0], stkin[13:0], RA[1:0],
TopCNT[13:0]);
endmodule
module CNTS4x14 (CNSCLK, WE, WA[1:0], stkin[13:0], RA[1:0], TopCNT[13:0]);
output [13:0] TopCNT;
input [13:0] stkin;
input [1:0] RA, WA;
input CNSCLK, WE;
reg [13:0] CNTcell[3:0];
wire [13:0] TopCNT;
always @(posedge CNSCLK)
if (WE) CNTcell[WA] <= #1 stkin[13:0];
assign TopCNT[13:0] = CNTcell[RA];
wire [13:0] cntstk0 = CNTcell[0];
wire [13:0] cntstk1 = CNTcell[1];
wire [13:0] cntstk2 = CNTcell[2];
wire [13:0] cntstk3 = CNTcell[3];
endmodule
|
`include "../include/x_def.v"
module LPstk (/* in */ T_RST, DSPCLK, LPin, PushLP_EN, PopLP_EN,
LPS_CKenb,
`ifdef FD_DFT
SCAN_TEST,
`endif
TopLP, LP_full, LP_empty, LP_has1);
input [21:0] LPin;
input T_RST, DSPCLK, PushLP_EN, PopLP_EN, LPS_CKenb;
`ifdef FD_DFT
input SCAN_TEST;
`endif
output [21:0] TopLP;
output LP_empty,
LP_full,
LP_has1;
reg [2:0] ptr;
wire [21:0] stkin;
wire [2:0] ptr_in, ptr_p, ptr_m;
wire [1:0] WA, RA;
wire WE;
wire pop, push;
`ifdef FD_GTCLK
`ifdef FD_DFT
GTECH_AND_NOT utm1 (.Z(LPS_CKenb_dft), .A(LPS_CKenb), .B(SCAN_TEST));
GTECH_NOR2 uk0 (.Z(LPSCLK_), .A(DSPCLK), .B(LPS_CKenb_dft));
GtCLK_NOT ckLPSCLK (.Z(LPSCLK), .A(LPSCLK_));
`else
GTECH_NOR2 uk0 (.Z(LPSCLK_), .A(DSPCLK), .B(LPS_CKenb));
GtCLK_NOT ckLPSCLK (.Z(LPSCLK), .A(LPSCLK_));
`endif
`else
wire LPSCLK_en=!LPS_CKenb;
wire LPSCLK = DSPCLK;
`endif
assign push = PushLP_EN && !LP_full;
assign pop = PopLP_EN && !LP_empty;
assign stkin[21:0] = LPin[21:0];
assign ptr_p[2:0] = ptr[2:0] + 1'b1;
assign ptr_m[2:0] = ptr[2:0] - 1'b1;
assign ptr_in[2:0] = push ? ptr_p[2:0] : ptr_m[2:0];
always @(posedge LPSCLK or posedge T_RST) begin
if (T_RST) ptr[2:0] <= #1 3'b111;
`ifdef FD_GTCLK
else if (push || pop) ptr[2:0] <= #1 ptr_in[2:0];
`else
else if ((push || pop) & LPSCLK_en) ptr[2:0] <= #1 ptr_in[2:0];
`endif
end
assign LP_empty = ptr[2];
assign LP_full = (ptr[2:0] == 3'h3);
assign LP_has1 = (ptr[2:0] == 3'h0);
`ifdef FD_GTCLK
assign WE = push;
`else
assign WE = push & LPSCLK_en;
`endif
assign WA[1:0] = ptr_p[1:0];
assign RA[1:0] = ptr[1:0];
LPS4x22 lps4x22 (LPSCLK, WE, WA[1:0], stkin[21:0], RA[1:0],
TopLP[21:0]);
endmodule
module LPS4x22 (LPSCLK, WE, WA[1:0], stkin[21:0], RA[1:0], TopLP[21:0]);
output [21:0] TopLP;
input [21:0] stkin;
input [1:0] RA, WA;
input LPSCLK, WE;
reg [21:0] LPcell[3:0];
wire [21:0] TopLP;
always @(posedge LPSCLK)
if (WE) LPcell[WA] <= #1 stkin[21:0];
assign TopLP[21:0] = LPcell[RA];
wire [21:0] lpstk0 = LPcell[0];
wire [21:0] lpstk1 = LPcell[1];
wire [21:0] lpstk2 = LPcell[2];
wire [21:0] lpstk3 = LPcell[3];
endmodule
|
`include "../include/x_def.v"
module PCstk (/* in */ T_RST, DSPCLK, PCin, PushPC_EN, PopPC_EN,
PCS_CKenb,
`ifdef FD_DFT
SCAN_TEST,
`endif
TopPC, nTopPC, PC_full, PC_empty,
PC_has1);
input [13:0] PCin;
input T_RST, DSPCLK, PushPC_EN, PopPC_EN, PCS_CKenb;
`ifdef FD_DFT
input SCAN_TEST;
`endif
output [13:0] TopPC,
nTopPC;
output PC_empty,
PC_full,
PC_has1;
reg [4:0] ptr;
wire [13:0] stkin;
wire [4:0] ptr_in, ptr_p, ptr_m;
wire [3:0] WA, RA, RA_m;
wire WE;
wire pop, push;
`ifdef FD_GTCLK
`ifdef FD_DFT
GTECH_AND_NOT utm1 (.Z(PCS_CKenb_dft), .A(PCS_CKenb), .B(SCAN_TEST));
GTECH_NOR2 uk0 (.Z(PCSCLK_), .A(DSPCLK), .B(PCS_CKenb_dft));
GtCLK_NOT ckPCSCLK (.Z(PCSCLK), .A(PCSCLK_));
`else
GTECH_NOR2 uk0 (.Z(PCSCLK_), .A(DSPCLK), .B(PCS_CKenb));
GtCLK_NOT ckPCSCLK (.Z(PCSCLK), .A(PCSCLK_));
`endif
`else
wire PCSCLK_en = !PCS_CKenb;
wire PCSCLK = DSPCLK;
`endif
assign #`da push = PushPC_EN && !PC_full;
assign #`da pop = PopPC_EN && !PC_empty;
assign #`d0 stkin[13:0] = PCin[13:0];
assign #`da ptr_p[4:0] = ptr[4:0] + 1'b1;
assign #`da ptr_m[4:0] = ptr[4:0] - 1'b1;
assign #`da ptr_in[4:0] = push ? ptr_p[4:0] : ptr_m[4:0];
always @(posedge PCSCLK or posedge T_RST) begin
if (T_RST) ptr[4:0] <= #`db 5'b11111;
`ifdef FD_GTCLK
else if (push || pop) ptr[4:0] <= #`db ptr_in[4:0];
`else
else if ((push || pop) & PCSCLK_en) ptr[4:0] <= #`db ptr_in[4:0];
`endif
end
assign #`d0 PC_empty = ptr[4];
assign #`da PC_full = (ptr[4:0] == 5'hf);
assign #`da PC_has1 = (ptr[4:0] == 5'h0);
`ifdef FD_GTCLK
assign #`d0 WE = push;
`else
assign #`d0 WE = push & PCSCLK_en;
`endif
assign #`da WA[3:0] = ptr_p[3:0];
assign #`da RA[3:0] = ptr[3:0];
assign #`da RA_m[3:0] = ptr_m[3:0];
PCS16x14 cnts16x14 (PCSCLK, WE, WA[3:0], stkin[13:0], RA[3:0], RA_m[3:0],
TopPC[13:0], nTopPC[13:0]);
endmodule
module PCS16x14 (PCSCLK, WE, WA[3:0], stkin[13:0], RA[3:0], RA_m[3:0],
TopPC[13:0], nTopPC[13:0]);
output [13:0] TopPC, nTopPC;
input [13:0] stkin;
input [3:0] RA, RA_m, WA;
input PCSCLK, WE;
reg [13:0] PCcell[15:0];
reg [13:0] TopPC, nTopPC;
always @(posedge PCSCLK)
if (WE) PCcell[WA] <= #`db stkin[13:0];
always @(RA)
case(RA)
4'b0000 : TopPC = PCcell[4'b0000];
4'b0001 : TopPC = PCcell[4'b0001];
4'b0010 : TopPC = PCcell[4'b0010];
4'b0011 : TopPC = PCcell[4'b0011];
4'b0100 : TopPC = PCcell[4'b0100];
4'b0101 : TopPC = PCcell[4'b0101];
4'b0110 : TopPC = PCcell[4'b0110];
4'b0111 : TopPC = PCcell[4'b0111];
4'b1000 : TopPC = PCcell[4'b1000];
4'b1001 : TopPC = PCcell[4'b1001];
4'b1010 : TopPC = PCcell[4'b1010];
4'b1011 : TopPC = PCcell[4'b1011];
4'b1100 : TopPC = PCcell[4'b1100];
4'b1101 : TopPC = PCcell[4'b1101];
4'b1110 : TopPC = PCcell[4'b1110];
4'b1111 : TopPC = PCcell[4'b1111];
default : TopPC = PCcell[4'b0000];
endcase
always @(RA_m)
case(RA_m)
4'b0000 : nTopPC = PCcell[4'b0000];
4'b0001 : nTopPC = PCcell[4'b0001];
4'b0010 : nTopPC = PCcell[4'b0010];
4'b0011 : nTopPC = PCcell[4'b0011];
4'b0100 : nTopPC = PCcell[4'b0100];
4'b0101 : nTopPC = PCcell[4'b0101];
4'b0110 : nTopPC = PCcell[4'b0110];
4'b0111 : nTopPC = PCcell[4'b0111];
4'b1000 : nTopPC = PCcell[4'b1000];
4'b1001 : nTopPC = PCcell[4'b1001];
4'b1010 : nTopPC = PCcell[4'b1010];
4'b1011 : nTopPC = PCcell[4'b1011];
4'b1100 : nTopPC = PCcell[4'b1100];
4'b1101 : nTopPC = PCcell[4'b1101];
4'b1110 : nTopPC = PCcell[4'b1110];
4'b1111 : nTopPC = PCcell[4'b1111];
default : nTopPC = PCcell[4'b0000];
endcase
wire [13:0] pcstk0 = PCcell[0];
wire [13:0] pcstk1 = PCcell[1];
wire [13:0] pcstk2 = PCcell[2];
wire [13:0] pcstk3 = PCcell[3];
wire [13:0] pcstk4 = PCcell[4];
wire [13:0] pcstk5 = PCcell[5];
wire [13:0] pcstk6 = PCcell[6];
wire [13:0] pcstk7 = PCcell[7];
wire [13:0] pcstk8 = PCcell[8];
wire [13:0] pcstk9 = PCcell[9];
wire [13:0] pcstk10 = PCcell[10];
wire [13:0] pcstk11 = PCcell[11];
wire [13:0] pcstk12 = PCcell[12];
wire [13:0] pcstk13 = PCcell[13];
wire [13:0] pcstk14 = PCcell[14];
wire [13:0] pcstk15 = PCcell[15];
endmodule
|
`include "../include/x_def.v"
module PSQ (/* ------------ Inputs : ------------- */
T_RST, DSPCLK, X_PWDn, X_IRQ2n, X_IRQL1n,
X_IRQL0n, X_IRQE1n, X_IRQE0n, X_IRQ1n, X_IRQ0n,
T_IST0, T_ISR0, T_IST1, T_ISR1, T_ITMR, IR,
DMDin,
RSTtext_h, Awake, enTRAP_RL, STBY,
IRE, EX_en, Dummy_R, dBR_R, idBR_R, RET_R,
DU_Eg, Call_Ed, RTI_Ed, BR_Ed, EXIT_E, RET_Ed,
Nseq_Ed, IDLE_Eg, MACdep_Eg, LDaST_Eg, MTCNTR_Eg,
MTOWRCNTR_Eg, MTtoppcs_Eg, MTIMASK_Eg, MTICNTL_Eg,
MTIFC_Eg, MTMSTAT_Eg, MFPSQ_E, MFtoppcs_Eg,
MFIMASK_E, MFICNTL_E, MFSSTAT_E, MFMSTAT_E,
MFCNTR_E, Stkctl_Eg, Modctl_Eg, MpopLP_Eg, imm16_E,
imm14_E, MFIDR_E, Long_Eg, Nrti_Ed, MTPMOVL_E,
MTDMOVL_E, MFPMOVL_E, MFDMOVL_E, accCM_R, accCM_E,
Bt_I, BTaken_I, RTaken_I, PTaken_R, PTaken_E,
DAG2A_D,
Ctrue, Ttrue, ASTAT,
SP1_EN, BRn, eRDY, EXTC_Eg, STI_Cg,
BOOT, STEAL, SREQ, IDMA_A, DSreqx,
GO_Fx, GO_Ex, GO_Cx, IRR, IDR, HALT_Eg,
GOICE_syn,
PDFORCE,
BIAD, T_BDMA, BSreqx,
`ifdef FD_DFT
SCAN_TEST,
`endif
GO_F, GO_D, GO_E, GO_C, PPclr_h, MSTAT,
ICE_ST_h, ICE_ST, IDLE_ST_h, IDLE_ST, TRAP_Eg,
redoM_h, redoSTI_h, redoLD_h, redoEX_h, TRAP_R,
TRAP_R_L, Prderr_Eg,
Bterr_E, Taddr_E, IFA_nxo,
CE, VpopST_Eg, popASTATo, Term, GO_MAC,
BGn, IFA,
PMOVL, DMOVL, redoIF_h,
GO_EC, ECYC,
CMAin,
HALTclr_h, GOICEclr_h, GOICEdis,
DRA, EXA,
psqDMD_do);
input [13:0] BIAD;
input
T_BDMA,
DSreqx,
BSreqx;
input [15:0] DMDin;
input [7:0] ASTAT;
input [13:0] DAG2A_D,
IRR,
Bt_I,
IDMA_A;
input [15:0] IDR;
input [17:4] IR;
input [19:0] IRE;
input T_RST,
DSPCLK,
Dummy_R,
Long_Eg,
accCM_R, accCM_E,
GO_Fx,
GO_Ex,
GO_Cx,
EX_en,
Ctrue,
Ttrue,
RSTtext_h,
PDFORCE,
STBY,
Awake,
enTRAP_RL,
BTaken_I,
RTaken_I,
PTaken_E,
PTaken_R,
BRn,
eRDY,
STI_Cg,
EXTC_Eg,
BOOT,
STEAL,
SREQ,
IDLE_Eg,
GOICE_syn,
HALT_Eg,
EXIT_E,
MACdep_Eg,
LDaST_Eg,
SP1_EN,
X_PWDn,
X_IRQ2n,
X_IRQL1n,
X_IRQL0n,
X_IRQE1n,
X_IRQE0n,
X_IRQ1n,
X_IRQ0n,
T_IST0,
T_ISR0,
T_IST1,
T_ISR1,
T_ITMR,
DU_Eg,
RTI_Ed,
RET_Ed,
RET_R,
dBR_R,
idBR_R,
BR_Ed,
Call_Ed,
Nseq_Ed,
Nrti_Ed,
MTCNTR_Eg,
MTOWRCNTR_Eg,
MTIMASK_Eg,
MTICNTL_Eg,
MTIFC_Eg,
MTMSTAT_Eg,
MTtoppcs_Eg,
MTPMOVL_E,
MTDMOVL_E,
MFPSQ_E,
MFtoppcs_Eg,
MFIMASK_E,
MFICNTL_E,
MFSSTAT_E,
MFMSTAT_E,
MFCNTR_E,
MFPMOVL_E,
MFDMOVL_E,
imm16_E,
imm14_E,
MFIDR_E,
Stkctl_Eg,
Modctl_Eg,
MpopLP_Eg;
`ifdef FD_DFT
input SCAN_TEST;
`endif
output [7:0] PMOVL;
output [3:0] DMOVL;
output [6:0] MSTAT;
output [7:0] popASTATo;
output [3:0] Term;
output [4:0] IFA_nxo;
output [13:0] IFA,
CMAin,
DRA,
EXA,
Taddr_E;
output PPclr_h,
HALTclr_h,
GOICEclr_h,
GOICEdis,
GO_F,
GO_D,
GO_E,
GO_C,
redoIF_h,
Prderr_Eg,
Bterr_E,
GO_EC,
ECYC,
ICE_ST_h,
ICE_ST,
IDLE_ST_h,
IDLE_ST,
TRAP_R,
TRAP_R_L,
TRAP_Eg,
GO_MAC,
CE,
VpopST_Eg,
BGn,
redoSTI_h,
redoLD_h,
redoEX_h,
redoM_h;
output [15:0] psqDMD_do;
reg [15:0] PCS;
reg [9:0] IMASK;
reg [7:0] SSTAT;
reg [15:0] IFC;
reg [13:0] IFA,
DRA,
EXA,
Taddr_Eb;
reg [12:0] Iflag;
reg [10:0] Iact_E;
reg CNTRval,
TRAP_R_L,
CE, Eqend_D, Eqend_Ed, MREQ, MGNT, PCS2or3;
reg T_PWRDN, T_IRQ2p, T_IRQL1p, T_IRQL0p, T_IRQE1,
T_IRQE0, T_IRQ1p, T_IRQ0p, T_PWRDN_s1,
T_IRQ2_s1, T_IRQE1_s1, T_IRQE0_s1, T_IRQ1_s1,
T_IRQ0_s1, ECYC;
reg TRAP_Eg, INT_en;
wire T_IRQ2, T_IRQL1, T_IRQL0, T_IRQ1, T_IRQ0;
wire [15:0] PNS;
wire [13:0] IFA_nx,
Naddr_I,
Naddr_E,
CNTR_m1,
CNTR,
CNTR_nx,
CNTin,
PCin, nTopPC, TopPC, TopCNT,
Taddr_Rb;
wire [4:0] ICNTL;
wire [6:0] MSTAT;
wire [15:0] DMD_do;
wire [21:0] LPin, TopLP;
wire [24:0] STin, TopST;
wire [3:0] IVA;
wire [12:0] Irqx, Irqi;
wire [10:0] Iact_R, Iact_Ri;
wire [9:0] IMASK_nx1, IMASK_nx2;
wire [6:0] MC_nx, MSTAT_nx;
wire Sel_IF, Sel_IVA, Sel_EXA, Sel_nTP, Sel_TPC,
Sel_PTA, Sel_RTA, PushPC_EN, PopPC_Eg, PopPC_EN,
PushLP_EN, PopLP_Eg, PopLP_EN, PushST_EN, PopST_Eg,
PopST_EN, PushCNT_Eg, PopCNT_Eg, PushCNT_EN,
PopCNT_EN, VpopST_Eg, LP_empty, Eqend_I, Eqend_Eg,
LPend_Eg, LTaken_Eg, Inest, IRQ0edge, IRQ1edge,
IRQ2edge, condCE, termCE, LPonCE, BRonCE,
testCE, LdCNTR_Eg, IMASK_we1, IMASK_we2, CNTR_we,
PMOVL_weh, PMOVL_wel, DMOVL_we, ICNTL_we, IFC_we,
MSTAT_we, GP2_Eg, GP4_Eg, exitIDLE;
wire sIflag12, sIflag11, sIflag10, sIflag9, sIflag6,
sIflag5, sIflag4, sIflag3, sIflag2, sIflag1, sIflag0;
wire rIflag12, rIflag11, rIflag10, rIflag9, rIflag6,
rIflag5, rIflag4, rIflag3, rIflag2, rIflag1, rIflag0;
wire updCNT_EN, updLP_EN, updST_EN, updPC_EN, accCM;
wire [13:0] Taddr_E0, Taddr_E1, accCM_Ain;
wire Sel_IFA, Bterr_E0, Bterr_E1;
wire Prderr00, Prderr01, Prderr10, Prderr11;
wire PCSpush_CKenb, PCSpop_CKenb, LPSpush_CKenb, LPSpop_CKenb,
STSpush_CKenb, STSpop_CKenb, CNSpush_CKenb, CNSpop_CKenb,
PCS_CKenb, LPS_CKenb, STS_CKenb, CNS_CKenb, CNTR_CKenb,
ICNTL_CKenb, MSTAT_CKenb, PMOVL_CKenb, DMOVL_CKenb;
function [13:0] Incr14;
input [13:0] A;
begin
Incr14 = A + 1;
end
endfunction
function [13:0] Decr14;
input [13:0] A;
begin
Decr14 = A - 1;
end
endfunction
`ifdef FD_DFT
reg RST_o, PPclr_o, SRST_o;
wire RST, PPclr, SRST;
always @(posedge DSPCLK) begin
RST_o <= #`db T_RST;
PPclr_o <= #`db T_RST || PPclr_h;
SRST_o <= #`db T_RST || RSTtext_h;
end
assign RST = SCAN_TEST ? T_RST : RST_o;
assign PPclr = SCAN_TEST ? T_RST : PPclr_o;
assign SRST = SCAN_TEST ? T_RST : SRST_o;
`else
reg RST, PPclr, SRST;
always @(posedge DSPCLK) begin
RST <= #`db T_RST;
PPclr <= #`db T_RST || PPclr_h;
SRST <= #`db T_RST || RSTtext_h;
end
`endif
wire MTPMOVL_Eg = MTPMOVL_E && EX_en;
wire MTDMOVL_Eg = MTDMOVL_E && EX_en;
wire Call_Eg = Call_Ed && Ctrue;
wire RTI_Eg = RTI_Ed && Ctrue;
wire BR_Eg = BR_Ed && Ctrue;
wire RET_Eg = RET_Ed && Ctrue;
wire Nseq_Eg = Nseq_Ed && Ctrue;
wire Taken_Eg = Nseq_Eg;
`ifdef FD_RTL_SIM
assign #`da Bterr_E = (DRA[13:0] != Taddr_E[13:0]);
`else
assign #`da Bterr_E0 = (DRA[13:0] != Taddr_E0[13:0]);
assign #`da Bterr_E1 = (DRA[13:0] != Taddr_E1[13:0]);
GTECH_MUX2 uu0 (.Z(Bterr_E), .S(Ctrue), .A(Bterr_E0), .B(Bterr_E1));
`endif
`ifdef FD_RTL_SIM
assign #`da Prderr_Eg = ((Nrti_Ed && Ctrue) != (PTaken_E && EX_en)) ||
Nrti_Ed && Ctrue && Bterr_E ||
RTI_Ed && Ctrue ||
Eqend_Eg && Ttrue ||
Eqend_Eg && !Ttrue && Bterr_E;
`else
assign #`da Prderr00 = PTaken_E && EX_en ||
Eqend_Ed && !IDLE_Eg && Bterr_E0;
assign #`da Prderr01 = PTaken_E && EX_en ||
Eqend_Ed && !IDLE_Eg;
assign #`da Prderr10 = (Nrti_Ed != (PTaken_E && EX_en)) ||
Nrti_Ed && Bterr_E1 ||
RTI_Ed ||
Eqend_Ed && !IDLE_Eg && !Nseq_Ed && Bterr_E1;
assign #`da Prderr11 = (Nrti_Ed != (PTaken_E && EX_en)) ||
Nrti_Ed && Bterr_E1 ||
RTI_Ed ||
Eqend_Ed && !IDLE_Eg && !Nseq_Ed;
GTECH_MUX4 uu1 (.Z(Prderr_Eg), .B(Ctrue), .A(Ttrue),
.D0(Prderr00), .D1(Prderr01), .D2(Prderr10), .D3(Prderr11));
`endif
always @(posedge DSPCLK or posedge RST) begin
if (RST) MREQ <= #`db 0;
else if (GO_E || PCS[10]) MREQ <= #`db !BRn;
else if (PNS[0]|PNS[6]) MREQ <= #`db 0;
end
always @(posedge DSPCLK or posedge RST) begin
if (RST) MGNT <= #`db 0;
else MGNT <= #`db MREQ & !(PNS[10]|PNS[6]);
end
assign #`da BGn = !MGNT;
assign #`da GP2_Eg = STEAL || TRAP_Eg || HALT_Eg || IDLE_Eg;
assign #`da GP4_Eg = MACdep_Eg || LDaST_Eg || EXTC_Eg;
assign #`da PNS[0] = PCS[1] && (SRST || BOOT) ||
PCS2or3 && !STEAL && TRAP_Eg ||
PCS[2] && EXIT_E ||
PCS[12] && TRAP_Eg;
assign #`da PNS[1] = PCS[1] && !(SRST || BOOT) && !EXTC_Eg ||
PCS[14] && eRDY;
assign #`da PNS[2] = PCS[2] && !EXTC_Eg ||
PCS[15] && eRDY;
assign #`da PNS[3] = PCS2or3 && !GP2_Eg && !MREQ && !GP4_Eg ||
PCS[4] && exitIDLE ||
PCS[5] && !EXTC_Eg ||
PCS[6] && !EXTC_Eg ||
PCS[10] && eRDY ||
PCS[11] && !MGNT && !MACdep_Eg && !EXTC_Eg ||
PCS[12] && !GP2_Eg && !MREQ && !MACdep_Eg && !EXTC_Eg;
assign #`da PNS[4] = PCS2or3 && !STEAL && !TRAP_Eg && HALT_Eg ||
PCS[11] && !TRAP_Eg && HALT_Eg;
assign #`da PNS[5] = PCS[5] ||
PCS[6] && !EXIT_E;
assign #`da PNS[6] = PCS2or3 && !STEAL && !TRAP_Eg && !HALT_Eg
&& IDLE_Eg ||
PCS[6] && !exitIDLE ||
PCS[2] && !TRAP_Eg && !HALT_Eg && IDLE_Eg;
assign #`da PNS[7] = PCS2or3 && STEAL ||
PCS[4] && STEAL ;
assign #`da PNS[8] = PCS2or3 && !GP2_Eg && !MREQ && MACdep_Eg ||
PCS[10] && !MGNT && MACdep_Eg ||
PCS[11] && !GP2_Eg && !MREQ && MACdep_Eg;
assign #`da PNS[9] = PCS2or3 && !GP2_Eg && !MREQ && LDaST_Eg;
assign #`da PNS[10] = PCS2or3 && !GP2_Eg && !MREQ && !MACdep_Eg
&& !LDaST_Eg && EXTC_Eg ||
PCS[7] && EXTC_Eg ||
PCS[8] && EXTC_Eg ||
PCS[1] && !eRDY ||
PCS[11] && !MGNT && !MACdep_Eg && EXTC_Eg ||
PCS[12] && !GP2_Eg && !MREQ && !MACdep_Eg && EXTC_Eg;
assign #`da PNS[11] = PCS[0] && !(SRST || BOOT) && MREQ ||
PCS[1] && MREQ ||
PCS2or3 && !GP2_Eg && MREQ ||
PCS[10] && MGNT ||
PCS[13] && !GP2_Eg && MREQ;
assign #`da PNS[12] = PCS[5] && !STEAL && !STI_Cg ||
PCS[11];
assign #`da PNS[13] = PCS[7] && !STEAL && STI_Cg;
assign #`da PNS[14] = PCS[10] && !(SRST || BOOT) && EXTC_Eg ||
PCS[1] && !eRDY;
assign #`da PNS[15] = PCS[1] && EXTC_Eg ||
PCS[12] && !eRDY;
always @(posedge DSPCLK or posedge SRST) begin
if (SRST) begin
PCS[15:0] <= #`db 16'h1;
PCS2or3 <= #`db 1'b0;
end
else begin
PCS[15:0] <= #`db PNS[15:0];
PCS2or3 <= #`db PNS[2] || PNS[3];
end
end
assign #`da GO_F = PNS[0] || PNS[4] || PNS[2] || PNS[3] ;
assign #`da GO_D = PNS[1] || PNS[2] || PNS[3] ;
assign #`da GO_E = PNS[2] || PNS[3] ;
assign #`da GO_C = PNS[3] ;
`ifdef FD_DFT
wire PPclr_h_h = (PNS[0] || PNS[4]);
assign PPclr_h = SCAN_TEST ? T_RST : PPclr_h_h;
`else
assign #`da PPclr_h = PNS[0] || PNS[4];
`endif
assign #`da HALTclr_h = PNS[3];
assign #`da GOICEclr_h = PNS[0] || PNS[2] || PNS[5];
assign #`da GOICEdis = PCS[0] || PCS[1] || PCS[15];
assign #`d0 GO_MAC = PNS[8];
assign #`d0 redoM_h = PNS[12];
assign #`d0 redoSTI_h = PNS[13];
assign #`d0 redoLD_h = PNS[8] || PNS[9] ;
assign #`da redoIF_h = |{PNS[12:8], PNS[14]};
assign #`da redoEX_h = PNS[5] || redoIF_h;
assign #`da IDLE_ST_h = PNS[4];
assign #`da ICE_ST_h = PNS[6];
assign #`d0 IDLE_ST = PCS[7];
assign #`d0 ICE_ST = PCS[3];
always @(posedge DSPCLK) begin
if (PPclr_h || GO_Ex) ECYC <= #`db 1'b0;
else ECYC <= #`db ICE_ST ? EXTC_Eg : (PNS[10] || PNS[14]|| PNS[15]);
end
assign #`d0 GO_EC = !ECYC && (ICE_ST ? EXTC_Eg : PNS[10]);
assign #`da Sel_IF = !(TRAP_Eg || IDLE_ST || EXIT_E ||
Long_Eg || Prderr_Eg);
assign #`da Sel_IVA = SRST || BOOT || TRAP_Eg;
assign #`da Sel_EXA = IDLE_ST ||
Long_Eg && !Eqend_Eg ||
Prderr_Eg && !(Nseq_Ed && Ctrue) &&
(!Eqend_Eg || Ttrue);
assign #`da Sel_TPC = Long_Eg && Eqend_Eg && !Ttrue ||
Prderr_Eg && !(Nseq_Ed && Ctrue) &&
(Eqend_Eg && !Ttrue) ||
Sel_IF && RTaken_I ||
Sel_IF && Eqend_I && (!RET_R || !PTaken_R);
assign #`da Sel_nTP = Sel_IF && Eqend_I && (RET_R && PTaken_R);
assign #`da Sel_RTA = Prderr_Eg && Ctrue && Nseq_Ed;
assign #`da Sel_PTA = Sel_IF && BTaken_I;
assign #`da Naddr_I[13:0] = Incr14(IFA[13:0]);
assign #`da Naddr_E[13:0] = Incr14(EXA[13:0]);
assign IFA_nxo[4:0]=IFA_nx[4:0];
`ifdef FD_RTL_SIM
assign #`da IFA_nx[13:0] = Sel_IVA ? {8'b0, IVA[3:0], 2'b0} :
EXIT_E ? IRR[13:0] :
Sel_EXA ? Naddr_E[13:0] :
Sel_TPC ? TopPC[13:0] :
Sel_nTP ? nTopPC[13:0] :
Sel_RTA ? Taddr_E[13:0] :
Sel_PTA ? Bt_I[13:0] : Naddr_I;
`else
assign #`da Sel_IFA = !(TRAP_Eg || SRST || BOOT ||
IDLE_ST || EXIT_E || Prderr_Eg ||
Eqend_I || BTaken_I || RTaken_I) &&
!(Long_Eg && !(Eqend_Eg && Ttrue));
assign #`da IFA_nx[13:0] = {14{ Sel_IFA}} & Naddr_I[13:0] |
{14{ Sel_IVA}} & {8'b0, IVA[3:0], 2'b0} |
{14{!Sel_IVA && EXIT_E}} & IRR[13:0] |
{14{!Sel_IVA && Sel_EXA}} & Naddr_E[13:0] |
{14{!Sel_IVA && Sel_TPC}} & TopPC[13:0] |
{14{!Sel_IVA && Sel_nTP}} & nTopPC[13:0] |
{14{!Sel_IVA && Sel_RTA}} & Taddr_E[13:0] |
{14{!Sel_IVA && Sel_PTA}} & Bt_I[13:0];
`endif
always @(posedge DSPCLK) if (GO_F) IFA[13:0] <= #`db IFA_nx[13:0];
always @(posedge DSPCLK) if (GO_D) DRA[13:0] <= #`db IFA[13:0];
always @(posedge DSPCLK) if (GO_E) EXA[13:0] <= #`db DRA[13:0];
assign #`da accCM = accCM_R || accCM_E;
assign #`da accCM_Ain[13:0] = GO_Ex ? IR[17:4] : IRE[17:4];
`ifdef FD_RTL_SIM
assign #`da CMAin[13:0] = SREQ ? ( DSreqx ? IDMA_A[13:0] :
{14{BSreqx}} & BIAD[13:0] ) :
accCM ? accCM_Ain[13:0] :
GO_Fx ? IFA_nx[13:0] : IFA[13:0];
`else
wire [13:0] CMAin1 = SREQ ? ( DSreqx ? IDMA_A[13:0] :
{14{BSreqx}} & BIAD[13:0] ) :
accCM ? accCM_Ain[13:0] : IFA[13:0];
wire selIFA_nx = GO_Fx & !(SREQ|accCM);
GTECH_MUX2 cmx0 ( .Z(CMAin[0]), .S(selIFA_nx), .A(CMAin1[0]), .B(IFA_nx[0]) );
GTECH_MUX2 cmx1 ( .Z(CMAin[1]), .S(selIFA_nx), .A(CMAin1[1]), .B(IFA_nx[1]) );
GTECH_MUX2 cmx2 ( .Z(CMAin[2]), .S(selIFA_nx), .A(CMAin1[2]), .B(IFA_nx[2]) );
GTECH_MUX2 cmx3 ( .Z(CMAin[3]), .S(selIFA_nx), .A(CMAin1[3]), .B(IFA_nx[3]) );
GTECH_MUX2 cmx4 ( .Z(CMAin[4]), .S(selIFA_nx), .A(CMAin1[4]), .B(IFA_nx[4]) );
GTECH_MUX2 cmx5 ( .Z(CMAin[5]), .S(selIFA_nx), .A(CMAin1[5]), .B(IFA_nx[5]) );
GTECH_MUX2 cmx6 ( .Z(CMAin[6]), .S(selIFA_nx), .A(CMAin1[6]), .B(IFA_nx[6]) );
GTECH_MUX2 cmx7 ( .Z(CMAin[7]), .S(selIFA_nx), .A(CMAin1[7]), .B(IFA_nx[7]) );
GTECH_MUX2 cmx8 ( .Z(CMAin[8]), .S(selIFA_nx), .A(CMAin1[8]), .B(IFA_nx[8]) );
GTECH_MUX2 cmx9 ( .Z(CMAin[9]), .S(selIFA_nx), .A(CMAin1[9]), .B(IFA_nx[9]) );
GTECH_MUX2 cmx10( .Z(CMAin[10]), .S(selIFA_nx), .A(CMAin1[10]), .B(IFA_nx[10]));
GTECH_MUX2 cmx11( .Z(CMAin[11]), .S(selIFA_nx), .A(CMAin1[11]), .B(IFA_nx[11]));
GTECH_MUX2 cmx12( .Z(CMAin[12]), .S(selIFA_nx), .A(CMAin1[12]), .B(IFA_nx[12]));
GTECH_MUXI2 cmx13( .Z(CMAin13_), .S(selIFA_nx), .A(CMAin1[13]), .B(IFA_nx[13]));
GTECH_NOT inv13( .Z(CMAin[13]), .A(CMAin13_));
`endif
assign #`da Taddr_Rb[13:0] = {14{dBR_R}} & IR[17:4] |
{14{idBR_R}} & DAG2A_D[13:0];
assign #`da Taddr_E[13:0] = BR_Eg ? Taddr_Eb[13:0] : TopPC[13:0];
`ifdef FD_RTL_SIM
`else
assign #`da Taddr_E0[13:0] = TopPC[13:0];
assign #`da Taddr_E1[13:0] = BR_Ed ? Taddr_Eb[13:0] : TopPC[13:0];
`endif
always @(posedge DSPCLK)
if (GO_E) Taddr_Eb[13:0] <= #`db Taddr_Rb[13:0];
assign #`da Eqend_I = ({PMOVL[3:0], IFA[13:0]} == TopLP[21:4]) & !LP_empty;
always @(posedge DSPCLK) begin
if (PPclr_h) Eqend_D <= #`db 1'b0;
else if (GO_D) Eqend_D <= #`db Eqend_I;
end
always @(posedge DSPCLK) begin
if (PPclr_h) Eqend_Ed <= #`db 1'b0;
else if (GO_E) Eqend_Ed <= #`db Eqend_D && !Dummy_R;
end
assign #`da Eqend_Eg = Eqend_Ed && !IDLE_Eg && !(Nseq_Ed && Ctrue);
assign #`da LPend_Eg = Eqend_Eg && Ttrue;
assign #`da LTaken_Eg = Eqend_Eg && !Ttrue;
assign #`da updPC_EN = PushPC_EN || PopPC_EN;
assign #`da PushPC_EN = TRAP_Eg && PNS[0] ||
(Call_Eg || DU_Eg || MTtoppcs_Eg) && GO_Cx;
assign #`da PopPC_Eg = RET_Eg || LPend_Eg || MFtoppcs_Eg ||
(Stkctl_Eg && IRE[4]);
assign #`da PopPC_EN = PopPC_Eg && GO_Cx;
assign #`da PCin[13:0] = TRAP_Eg ? EXA[13:0] :
MTtoppcs_Eg ? DMDin[13:0] : Naddr_E[13:0];
assign #`da PCSpush_CKenb = !(TRAP_Eg || Call_Ed || DU_Eg || MTtoppcs_Eg);
assign #`da PCSpop_CKenb = !(RET_Ed || Eqend_Ed || MFtoppcs_Eg ||
Stkctl_Eg && IRE[4]);
assign #`da PCS_CKenb = PCSpush_CKenb && PCSpop_CKenb;
PCstk pcstk (/* in */ SRST, DSPCLK, PCin[13:0], PushPC_EN, PopPC_EN,
PCS_CKenb,
`ifdef FD_DFT
SCAN_TEST,
`endif
TopPC[13:0], nTopPC[13:0], PC_full, PC_empty,
PC_has1);
assign #`da updLP_EN = (DU_Eg || LPend_Eg || MpopLP_Eg) && GO_Cx;
assign #`da PushLP_EN = DU_Eg && GO_Cx;
assign #`da PopLP_Eg = LPend_Eg || MpopLP_Eg;
assign #`da PopLP_EN = PopLP_Eg && GO_Cx;
assign #`d0 LPin[21:0] = {IRE[17:0], PMOVL[3:0]};
assign #`da LPSpush_CKenb = !DU_Eg;
assign #`da LPSpop_CKenb = !(Eqend_Ed || MpopLP_Eg);
assign #`da LPS_CKenb = LPSpush_CKenb && LPSpop_CKenb;
LPstk lpstk (/* in */ SRST, DSPCLK, LPin[21:0], PushLP_EN, PopLP_EN,
LPS_CKenb,
`ifdef FD_DFT
SCAN_TEST,
`endif
TopLP[21:0], LP_full, LP_empty, LP_has1);
assign #`da updST_EN = TRAP_Eg && PNS[0] ||
RTI_Eg && GO_Cx ||
(Stkctl_Eg && IRE[1]) && GO_Cx;
assign #`da PushST_EN = (TRAP_Eg && PNS[0]) ||
(Stkctl_Eg && IRE[1] && !IRE[0] && GO_Cx);
assign #`da PopST_Eg = RTI_Eg || (Stkctl_Eg && IRE[1] && IRE[0]);
assign #`da PopST_EN = PopST_Eg && GO_Cx;
assign #`d0 STin[24:0] = {IMASK[9:0], MSTAT[6:0], ASTAT[7:0]};
assign #`d0 popASTATo[7:0] = TopST[7:0];
assign #`da STSpush_CKenb = !(TRAP_Eg || Stkctl_Eg && IRE[1] && !IRE[0]);
assign #`da STSpop_CKenb = !(RTI_Ed || Stkctl_Eg && IRE[1] && IRE[0]);
assign #`da STS_CKenb = STSpush_CKenb && STSpop_CKenb;
STstk ststk (/* in */ SRST, DSPCLK, STin[24:0], PushST_EN, PopST_EN,
STS_CKenb,
`ifdef FD_DFT
SCAN_TEST,
`endif
TopST[24:0], ST_full, ST_empty, ST_has1);
assign #`d0 Term[3:0] = TopLP[3:0];
assign #`da condCE = (IRE[3:0] == 4'he);
assign #`da termCE = (Term[3:0] == 4'he);
assign #`da LPonCE = Eqend_Eg && termCE;
assign #`da BRonCE = BR_Ed && condCE;
assign #`da testCE = BRonCE || LPonCE;
assign #`da PushCNT_Eg = MTCNTR_Eg && CNTRval;
assign #`da PopCNT_Eg = LPend_Eg && termCE ||
BR_Ed && CE && condCE ||
Stkctl_Eg && IRE[2];
assign #`da PushCNT_EN = PushCNT_Eg && GO_Cx;
assign #`da PopCNT_EN = PopCNT_Eg && GO_Cx;
assign #`da updCNT_EN = PushCNT_EN || PopCNT_EN;
assign #`da CNTin[13:0] = CNTR[13:0];
assign #`da CNSpush_CKenb = !PushCNT_Eg;
assign #`da CNSpop_CKenb = !(Eqend_Ed ||
BR_Ed && condCE ||
Stkctl_Eg && IRE[2]);
assign #`da CNS_CKenb = CNSpush_CKenb && CNSpop_CKenb;
CNTstk cntstk (/* in */ SRST, DSPCLK, CNTin[13:0], PushCNT_EN,
PopCNT_EN, CNS_CKenb,
`ifdef FD_DFT
SCAN_TEST,
`endif
TopCNT[13:0], CNT_full, CNT_empty, CNT_has1);
always @(posedge DSPCLK or posedge SRST) begin
if (SRST) CNTRval <= #`db 1'b0;
else if (LdCNTR_Eg && GO_Cx) CNTRval <= #`db 1'b1;
else if (PopCNT_EN && CNT_empty) CNTRval <= #`db 1'b0;
end
assign #`da LdCNTR_Eg = MTCNTR_Eg || MTOWRCNTR_Eg;
assign #`da CNTR_we = (LdCNTR_Eg ||
testCE ||
Stkctl_Eg && IRE[2]) && GO_Cx;
assign #`da CNTR_m1[13:0] = Decr14(CNTR[13:0]);
assign #`da CNTR_nx[13:0] = LdCNTR_Eg ? DMDin[13:0] :
(PopCNT_Eg & !CNT_empty) ? TopCNT[13:0] :
CNTR_m1[13:0];
assign #`da CNTR_CKenb = !(LdCNTR_Eg || BRonCE || Eqend_Ed ||
Stkctl_Eg && IRE[2]);
always @(posedge DSPCLK or posedge SRST) begin
if (SRST) begin
CE <= #`db 1'b0;
end
else if (CNTR_we) begin
CE <= #`db CNTR_nx[13:0] == 14'h1;
end
end
`ifdef FD_DFT
REG14LC CNTR_reg (DSPCLK, CNTR_CKenb, CNTR_we,
CNTR_nx[13:0], CNTR[13:0], SRST, SCAN_TEST);
`else
REG14LC CNTR_reg (DSPCLK, CNTR_CKenb, CNTR_we,
CNTR_nx[13:0], CNTR[13:0], SRST);
`endif
assign #`da VpopST_Eg = PopST_Eg && !ST_empty;
assign #`da IMASK_we1 = PNS[0] && !ICE_ST;
assign #`da IMASK_we2 = (MTIMASK_Eg || VpopST_Eg) && GO_Cx;
always @(posedge DSPCLK or posedge SRST) begin
if (SRST) IMASK[9:0] <= #`db 10'b0;
else if (IMASK_we1) IMASK[9:0] <= #`db IMASK_nx1[9:0];
else if (IMASK_we2) IMASK[9:0] <= #`db IMASK_nx2[9:0];
end
assign #`da IMASK_nx1[9:0]
= {10{!Inest || Iact_E[10] || Iact_E[9]}} & 10'b0 |
{10{ Inest && Iact_E[8]}} & {IMASK[9], 9'b0} |
{10{ Inest && Iact_E[7]}} & {IMASK[9:8], 8'b0} |
{10{ Inest && Iact_E[6]}} & {IMASK[9:7], 7'b0} |
{10{ Inest && Iact_E[5]}} & {IMASK[9:6], 6'b0} |
{10{ Inest && Iact_E[4]}} & {IMASK[9:5], 5'b0} |
{10{ Inest && Iact_E[3]}} & {IMASK[9:4], 4'b0} |
{10{ Inest && Iact_E[2]}} & {IMASK[9:3], 3'b0} |
{10{ Inest && Iact_E[1]}} & {IMASK[9:2], 2'b0} |
{10{ Inest && Iact_E[0]}} & {IMASK[9:1], 1'b0};
assign #`da IMASK_nx2[9:0] = MTIMASK_Eg ? DMDin[9:0] : TopST[24:15];
assign #`da ICNTL_we = MTICNTL_Eg && GO_Cx;
assign #`da ICNTL_CKenb = !MTICNTL_Eg;
`ifdef FD_DFT
REG5LC ICNTL_reg (DSPCLK, ICNTL_CKenb, ICNTL_we,
{DMDin[4], 1'b0, DMDin[2:0]}, ICNTL[4:0], RST, SCAN_TEST);
`else
REG5LC ICNTL_reg (DSPCLK, ICNTL_CKenb, ICNTL_we,
{DMDin[4], 1'b0, DMDin[2:0]}, ICNTL[4:0], RST);
`endif
assign #`da IFC_we = MTIFC_Eg && GO_Cx;
always @(posedge DSPCLK or posedge RST) begin
if (RST) IFC[1] <= #`db 1'b0;
else if (IFC_we) IFC[1] <= #`db DMDin[0];
else if (IFC[0]) IFC[1] <= #`db 1'b0;
end
always @(posedge DSPCLK or posedge RST) begin
if (RST) IFC[0] <= #`db 1'b0;
else if (IFC_we) IFC[0] <= #`db DMDin[1];
else if (IFC[1]) IFC[0] <= #`db 1'b0;
end
always @(posedge DSPCLK or posedge RST) begin
if (RST) IFC[3] <= #`db 1'b0;
else if (IFC_we) IFC[3] <= #`db DMDin[2];
else if (IFC[2]) IFC[3] <= #`db 1'b0;
end
always @(posedge DSPCLK or posedge RST) begin
if (RST) IFC[2] <= #`db 1'b0;
else if (IFC_we) IFC[2] <= #`db DMDin[3];
else if (IFC[3]) IFC[2] <= #`db 1'b0;
end
always @(posedge DSPCLK or posedge RST) begin
if (RST) IFC[5] <= #`db 1'b0;
else if (IFC_we) IFC[5] <= #`db DMDin[4];
else if (IFC[4]) IFC[5] <= #`db 1'b0;
end
always @(posedge DSPCLK or posedge RST) begin
if (RST) IFC[4] <= #`db 1'b0;
else if (IFC_we) IFC[4] <= #`db DMDin[5];
else if (IFC[5]) IFC[4] <= #`db 1'b0;
end
always @(posedge DSPCLK or posedge RST) begin
if (RST) IFC[7] <= #`db 1'b0;
else if (IFC_we) IFC[7] <= #`db DMDin[6];
else if (IFC[6]) IFC[7] <= #`db 1'b0;
end
always @(posedge DSPCLK or posedge RST) begin
if (RST) IFC[6] <= #`db 1'b0;
else if (IFC_we) IFC[6] <= #`db DMDin[7];
else if (IFC[7]) IFC[6] <= #`db 1'b0;
end
always @(posedge DSPCLK or posedge RST) begin
if (RST) IFC[9] <= #`db 1'b0;
else if (IFC_we) IFC[9] <= #`db DMDin[8];
else if (IFC[8]) IFC[9] <= #`db 1'b0;
end
always @(posedge DSPCLK or posedge RST) begin
if (RST) IFC[8] <= #`db 1'b0;
else if (IFC_we) IFC[8] <= #`db DMDin[9];
else if (IFC[9]) IFC[8] <= #`db 1'b0;
end
always @(posedge DSPCLK or posedge RST) begin
if (RST) IFC[11] <= #`db 1'b0;
else if (IFC_we) IFC[11] <= #`db DMDin[10];
else if (IFC[10]) IFC[11] <= #`db 1'b0;
end
always @(posedge DSPCLK or posedge RST) begin
if (RST) IFC[10] <= #`db 1'b0;
else if (IFC_we) IFC[10] <= #`db DMDin[11];
else if (IFC[11]) IFC[10] <= #`db 1'b0;
end
always @(posedge DSPCLK or posedge RST) begin
if (RST) IFC[12] <= #`db 1'b0;
else if (IFC_we) IFC[12] <= #`db DMDin[12];
else if (IFC[12]) IFC[12] <= #`db 1'b0;
end
always @(posedge DSPCLK or posedge RST) begin
if (RST) IFC[13] <= #`db 1'b0;
else if (IFC_we) IFC[13] <= #`db DMDin[13];
else if (IFC[13]) IFC[13] <= #`db 1'b0;
end
always @(posedge DSPCLK or posedge RST) begin
if (RST) IFC[14] <= #`db 1'b0;
else if (IFC_we) IFC[14] <= #`db DMDin[14];
else if (IFC[14]) IFC[14] <= #`db 1'b0;
end
always @(posedge DSPCLK or posedge RST) begin
if (RST) IFC[15] <= #`db 1'b0;
else if (IFC_we) IFC[15] <= #`db DMDin[15];
else if (IFC[15]) IFC[15] <= #`db 1'b0;
end
assign #`da MSTAT_we = (MTMSTAT_Eg || VpopST_Eg || Modctl_Eg) && GO_Cx;
assign #`da MSTAT_CKenb = !(MTMSTAT_Eg || Modctl_Eg || RTI_Ed ||
Stkctl_Eg && IRE[1] && IRE[0]);
assign #`da MC_nx[0] = IRE[7] ? IRE[4] : MSTAT[0];
assign #`da MC_nx[1] = IRE[5] ? IRE[6] : MSTAT[1];
assign #`da MC_nx[2] = IRE[9] ? IRE[8] : MSTAT[2];
assign #`da MC_nx[3] = IRE[13] ? IRE[10] : MSTAT[3];
assign #`da MC_nx[4] = IRE[11] ? IRE[12] : MSTAT[4];
assign #`da MC_nx[5] = IRE[15] ? IRE[14] : MSTAT[5];
assign #`da MC_nx[6] = IRE[3] ? IRE[2] : MSTAT[6];
assign #`da MSTAT_nx[6:0] = MTMSTAT_Eg ? DMDin[6:0] :
Modctl_Eg ? MC_nx[6:0] : TopST[14:8];
`ifdef FD_DFT
REG7LC MSTAT_reg (DSPCLK, MSTAT_CKenb, MSTAT_we,
MSTAT_nx[6:0], MSTAT[6:0], RST, SCAN_TEST);
`else
REG7LC MSTAT_reg (DSPCLK, MSTAT_CKenb, MSTAT_we,
MSTAT_nx[6:0], MSTAT[6:0], RST);
`endif
always @(posedge DSPCLK or posedge SRST) begin
if (SRST) SSTAT[0] <= #`db 1'b1;
else if (updPC_EN) SSTAT[0] <= #`db PopPC_EN && (PC_has1|PC_empty);
end
always @(posedge DSPCLK or posedge SRST) begin
if (SRST) SSTAT[1] <= #`db 1'b0;
else if (PushPC_EN & !SSTAT[1]) SSTAT[1] <= #`db PC_full;
end
always @(posedge DSPCLK or posedge SRST) begin
if (SRST) SSTAT[2] <= #`db 1'b1;
else if (updCNT_EN) SSTAT[2] <= #`db PopCNT_EN && (CNT_has1|CNT_empty);
end
always @(posedge DSPCLK or posedge SRST) begin
if (SRST) SSTAT[3] <= #`db 1'b0;
else if (PushCNT_EN & !SSTAT[3]) SSTAT[3] <= #`db CNT_full;
end
always @(posedge DSPCLK or posedge SRST) begin
if (SRST) SSTAT[4] <= #`db 1'b1;
else if (updST_EN) SSTAT[4] <= #`db PopST_EN && (ST_has1|ST_empty);
end
always @(posedge DSPCLK or posedge SRST) begin
if (SRST) SSTAT[5] <= #`db 1'b0;
else if (PushST_EN & !SSTAT[5]) SSTAT[5] <= #`db ST_full;
end
always @(posedge DSPCLK or posedge SRST) begin
if (SRST) SSTAT[6] <= #`db 1'b1;
else if (updLP_EN) SSTAT[6] <= #`db PopLP_EN && (LP_has1|LP_empty);
end
always @(posedge DSPCLK or posedge SRST) begin
if (SRST) SSTAT[7] <= #`db 1'b0;
else if (PushLP_EN & !SSTAT[7]) SSTAT[7] <= #`db LP_full;
end
assign #`da PMOVL_weh = MTPMOVL_Eg && GO_Cx && !(&{DMDin[7:4]});
assign #`da PMOVL_wel = MTPMOVL_Eg && GO_Cx && !(&{DMDin[3:0]});
assign #`da DMOVL_we = MTDMOVL_Eg && GO_Cx;
assign #`d0 PMOVL_CKenb = !MTPMOVL_E;
assign #`da DMOVL_CKenb = !MTDMOVL_E;
`ifdef FD_DFT
REG4LC PMOVL_regh (DSPCLK, PMOVL_CKenb, PMOVL_weh,
DMDin[7:4], PMOVL[7:4], RST, SCAN_TEST);
REG4LC PMOVL_regl (DSPCLK, PMOVL_CKenb, PMOVL_wel,
DMDin[3:0], PMOVL[3:0], RST, SCAN_TEST);
REG4LC DMOVL_reg (DSPCLK, DMOVL_CKenb, DMOVL_we,
DMDin[3:0], DMOVL[3:0], RST, SCAN_TEST);
`else
REG4LC PMOVL_regh (DSPCLK, PMOVL_CKenb, PMOVL_weh,
DMDin[7:4], PMOVL[7:4], RST);
REG4LC PMOVL_regl (DSPCLK, PMOVL_CKenb, PMOVL_wel,
DMDin[3:0], PMOVL[3:0], RST);
REG4LC DMOVL_reg (DSPCLK, DMOVL_CKenb, DMOVL_we,
DMDin[3:0], DMOVL[3:0], RST);
`endif
assign #`da DMD_do[15:0] = {16{MFIMASK_E}} & {6'b0, IMASK[9:0]} |
{16{MFSSTAT_E}} & {8'b0, SSTAT[7:0]} |
{16{MFMSTAT_E}} & {9'b0, MSTAT[6:0]} |
{16{MFICNTL_E}} & {11'b0, ICNTL[4:0]} |
{16{MFCNTR_E}} & {2'b0, CNTR[13:0]} |
{16{MFtoppcs_Eg}} & {2'b0, TopPC[13:0]} |
{16{MFPMOVL_E}} & {8'b0, PMOVL[7:0]} |
{16{MFDMOVL_E}} & {12'b0, DMOVL[3:0]} |
{16{MFIDR_E}} & IDR[15:0] |
{16{imm16_E}} & IRE[19:4] |
{16{imm14_E}} & {{2{IRE[17]}}, IRE[17:4]};
assign #`da psqDMD_do[15:0] = {16{MFPSQ_E}} & DMD_do[15:0];
assign #`d0 Inest = ICNTL[4];
assign #`d0 {IRQ2edge, IRQ1edge, IRQ0edge} = ICNTL[2:0];
always @(posedge DSPCLK) begin
T_PWRDN <= #`db !X_PWDn;
T_IRQ2p <= #`db !X_IRQ2n;
T_IRQL1p <= #`db !X_IRQL1n;
T_IRQL0p <= #`db !X_IRQL0n;
T_IRQE1 <= #`db !X_IRQE1n;
T_IRQE0 <= #`db !X_IRQE0n;
T_IRQ1p <= #`db !X_IRQ1n;
T_IRQ0p <= #`db !X_IRQ0n;
end
IDEBN irq2_de (DSPCLK, T_IRQ2p, T_IRQ2);
IDEBN irq1_de (DSPCLK, T_IRQ1p, T_IRQ1);
IDEBN irq0_de (DSPCLK, T_IRQ0p, T_IRQ0);
IDEBN irql1_de (DSPCLK, T_IRQL1p, T_IRQL1);
IDEBN irql0_de (DSPCLK, T_IRQL0p, T_IRQL0);
assign #`d0 Irqx[12:0] = {T_IRQ1, T_IRQ0,
T_PWRDN, T_IRQ2, T_IRQL1, T_IRQL0, T_IST0,
T_ISR0, T_IRQE1, T_BDMA, T_IST1, T_ISR1,
T_ITMR};
always @(posedge DSPCLK) begin
T_PWRDN_s1 <= #`db T_PWRDN;
T_IRQ2_s1 <= #`db T_IRQ2;
T_IRQE1_s1 <= #`db T_IRQE1;
T_IRQ1_s1 <= #`db T_IRQ1;
T_IRQ0_s1 <= #`db T_IRQ0;
T_IRQE0_s1 <= #`db T_IRQE0;
end
assign #`da Irqi[12] = T_IRQ1 && (!T_IRQ1_s1 || !IRQ1edge);
assign #`da Irqi[11] = T_IRQ0 && (!T_IRQ0_s1 || !IRQ0edge);
assign #`da Irqi[10] = T_PWRDN && !T_PWRDN_s1;
assign #`da Irqi[9] = T_IRQ2 && (!T_IRQ2_s1 || !IRQ2edge);
assign #`da Irqi[4] = T_IRQE1 && !T_IRQE1_s1;
assign #`da Irqi[3] = Irqx[3] || !Irqx[3] && (T_IRQE0 && !T_IRQE0_s1);
assign #`da Irqi[8:5] = Irqx[8:5];
assign #`da Irqi[2:0] = Irqx[2:0];
assign #`da sIflag12 = (Irqi[12] || IFC[10] && IRQ1edge) && !SP1_EN;
assign #`da rIflag12 = PPclr_h && Iact_E[2] ||
IFC[2] && IRQ1edge;
always @(posedge DSPCLK or posedge SRST) begin
if(SRST) Iflag[12] <= #`db 1'b0;
else if(!IRQ1edge) Iflag[12] <= #`db Irqi[12];
else if(rIflag12) Iflag[12] <= #`db 1'b0;
else if(sIflag12) Iflag[12] <= #`db 1'b1;
end
assign #`da sIflag11 = (Irqi[11] || IFC[9] && IRQ0edge) && !SP1_EN;
assign #`da rIflag11 = PPclr_h && Iact_E[1] ||
IFC[1] && IRQ0edge;
always @(posedge DSPCLK or posedge SRST) begin
if(SRST) Iflag[11] <= #`db 1'b0;
else if(!IRQ0edge) Iflag[11] <= #`db Irqi[11];
else if(rIflag11) Iflag[11] <= #`db 1'b0;
else if(sIflag11) Iflag[11] <= #`db 1'b1;
end
assign #`da sIflag10 = Irqi[10] || PDFORCE;
assign #`da rIflag10 = PPclr_h && Iact_E[10];
always @(posedge DSPCLK or posedge SRST) begin
if(SRST) Iflag[10] <= #`db 1'b0;
else if(rIflag10) Iflag[10] <= #`db 1'b0;
else if(sIflag10) Iflag[10] <= #`db 1'b1;
end
assign #`da sIflag9 = Irqi[9] || IFC[15] && IRQ2edge;
assign #`da rIflag9 = PPclr_h && Iact_E[9] ||
IFC[7] && IRQ2edge;
always @(posedge DSPCLK or posedge SRST) begin
if(SRST) Iflag[9] <= #`db 1'b0;
else if(!IRQ2edge) Iflag[9] <= #`db Irqi[9];
else if(rIflag9) Iflag[9] <= #`db 1'b0;
else if(sIflag9) Iflag[9] <= #`db 1'b1;
end
always @(posedge DSPCLK or posedge SRST) begin
if(SRST) Iflag[8:7] <= #`db 2'b0;
else Iflag[8:7] <= #`db Irqi[8:7];
end
assign #`da sIflag6 = Irqi[6] || IFC[14];
assign #`da rIflag6 = PPclr_h && Iact_E[6] || IFC[6];
always @(posedge DSPCLK or posedge SRST) begin
if(SRST) Iflag[6] <= #`db 1'b0;
else if(rIflag6) Iflag[6] <= #`db 1'b0;
else if(sIflag6) Iflag[6] <= #`db 1'b1;
end
assign #`da sIflag5 = Irqi[5] || IFC[13];
assign #`da rIflag5 = PPclr_h && Iact_E[5] || IFC[5];
always @(posedge DSPCLK or posedge SRST) begin
if(SRST) Iflag[5] <= #`db 1'b0;
else if(rIflag5) Iflag[5] <= #`db 1'b0;
else if(sIflag5) Iflag[5] <= #`db 1'b1;
end
assign #`da sIflag4 = Irqi[4] || IFC[12];
assign #`da rIflag4 = PPclr_h && Iact_E[4] || IFC[4];
always @(posedge DSPCLK or posedge SRST) begin
if(SRST) Iflag[4] <= #`db 1'b0;
else if(rIflag4) Iflag[4] <= #`db 1'b0;
else if(sIflag4) Iflag[4] <= #`db 1'b1;
end
assign #`da sIflag3 = Irqi[3] || IFC[11];
assign #`da rIflag3 = PPclr_h && Iact_E[3] || IFC[3];
always @(posedge DSPCLK or posedge SRST) begin
if(SRST) Iflag[3] <= #`db 1'b0;
else if(rIflag3) Iflag[3] <= #`db 1'b0;
else if(sIflag3) Iflag[3] <= #`db 1'b1;
end
assign #`da sIflag2 = (Irqi[2] || IFC[10]) && SP1_EN;
assign #`da rIflag2 = PPclr_h && Iact_E[2] || IFC[2];
always @(posedge DSPCLK or posedge SRST) begin
if(SRST) Iflag[2] <= #`db 1'b0;
else if(rIflag2) Iflag[2] <= #`db 1'b0;
else if(sIflag2) Iflag[2] <= #`db 1'b1;
end
assign #`da sIflag1 = (Irqi[1] || IFC[9]) && SP1_EN;
assign #`da rIflag1 = PPclr_h && Iact_E[1] || IFC[1];
always @(posedge DSPCLK or posedge SRST) begin
if(SRST) Iflag[1] <= #`db 1'b0;
else if(rIflag1) Iflag[1] <= #`db 1'b0;
else if(sIflag1) Iflag[1] <= #`db 1'b1;
end
assign #`da sIflag0 = Irqi[0] || IFC[8];
assign #`da rIflag0 = PPclr_h && Iact_E[0] || IFC[0];
always @(posedge DSPCLK or posedge SRST) begin
if(SRST) Iflag[0] <= #`db 1'b0;
else if(rIflag0) Iflag[0] <= #`db 1'b0;
else if(sIflag0) Iflag[0] <= #`db 1'b1;
end
always @(posedge DSPCLK or posedge SRST) begin
if(SRST) INT_en <= #`db 1'b1;
else if(GO_Cx & Stkctl_Eg & IRE[6]) INT_en <= #`db IRE[5];
end
assign #`da Iact_Ri[1] = (SP1_EN ? Iflag[1] : Iflag[11]) &&
(IMASK[1] && !ICE_ST);
assign #`da Iact_Ri[2] = (SP1_EN ? Iflag[2] : Iflag[12]) &&
(IMASK[2] && !ICE_ST);
assign #`da Iact_Ri[0] = Iflag[3] && (IMASK[0] && !ICE_ST);
assign #`da Iact_Ri[3] = Iflag[0] && (IMASK[3] && !ICE_ST);
assign #`da Iact_Ri[4] = Iflag[5] && (IMASK[4] && !ICE_ST);
assign #`da Iact_Ri[5] = Iflag[4] && (IMASK[5] && !ICE_ST);
assign #`da Iact_Ri[6] = Iflag[7] && (IMASK[6] && !ICE_ST);
assign #`da Iact_Ri[7] = Iflag[6] && (IMASK[7] && !ICE_ST);
assign #`da Iact_Ri[8] = Iflag[9] && (IMASK[8] && !ICE_ST);
assign #`da Iact_Ri[9] = Iflag[8] && (IMASK[9] && !ICE_ST);
assign #`da Iact_Ri[10] = Iflag[10] && !ICE_ST;
assign #`da TRAP_R = |{Iact_Ri[10:0]};
assign #`da Iact_R[0] = Iact_Ri[0] && !(|{Iact_Ri[10:1]});
assign #`da Iact_R[1] = Iact_Ri[1] && !(|{Iact_Ri[10:2]});
assign #`da Iact_R[2] = Iact_Ri[2] && !(|{Iact_Ri[10:3]});
assign #`da Iact_R[3] = Iact_Ri[3] && !(|{Iact_Ri[10:4]});
assign #`da Iact_R[4] = Iact_Ri[4] && !(|{Iact_Ri[10:5]});
assign #`da Iact_R[5] = Iact_Ri[5] && !(|{Iact_Ri[10:6]});
assign #`da Iact_R[6] = Iact_Ri[6] && !(|{Iact_Ri[10:7]});
assign #`da Iact_R[7] = Iact_Ri[7] && !(|{Iact_Ri[10:8]});
assign #`da Iact_R[8] = Iact_Ri[8] && !(|{Iact_Ri[10:9]});
assign #`da Iact_R[9] = Iact_Ri[9] && !(|{Iact_Ri[10]});
assign #`da Iact_R[10] = Iact_Ri[10];
always @(posedge DSPCLK or posedge PPclr) begin
if(PPclr) TRAP_R_L <= #`db 1'b0;
else TRAP_R_L <= #`db TRAP_R && enTRAP_RL;
end
always @(posedge DSPCLK or posedge PPclr) begin
if(PPclr) begin
Iact_E[10:0] <= #`db 11'b0;
TRAP_Eg <= #`db 1'b0;
end
else if(GO_E & INT_en) begin
Iact_E[10:0] <= #`db Iact_R[10:0];
TRAP_Eg <= #`db (IDLE_ST ? TRAP_R_L : TRAP_R) && !Dummy_R;
end
end
assign #`da exitIDLE = STBY ? (TRAP_R_L || GOICE_syn) : Awake;
assign #`da IVA[3:0] = (SRST || BOOT) ? 4'b0000 :
({4{Iact_E[10]}} & 4'b1011 |
{4{Iact_E[8]}} & 4'b0001 |
{4{Iact_E[9]}} & 4'b0010 |
{4{Iact_E[6]}} & 4'b0011 |
{4{Iact_E[7]}} & 4'b0100 |
{4{Iact_E[4]}} & 4'b0101 |
{4{Iact_E[5]}} & 4'b0110 |
{4{Iact_E[2]}} & 4'b0111 |
{4{Iact_E[3]}} & 4'b1000 |
{4{Iact_E[0]}} & 4'b1001 |
{4{Iact_E[1]}} & 4'b1010);
endmodule
|
`include "../include/x_def.v"
module STstk (/* in */ T_RST, DSPCLK, STin, PushST_EN, PopST_EN,
STS_CKenb,
`ifdef FD_DFT
SCAN_TEST,
`endif
TopST, ST_full, ST_empty, ST_has1);
input [24:0] STin;
input T_RST, DSPCLK, PushST_EN, PopST_EN, STS_CKenb;
`ifdef FD_DFT
input SCAN_TEST;
`endif
output [24:0] TopST;
output ST_empty,
ST_full,
ST_has1;
reg [2:0] ptr;
wire [24:0] stkin;
wire [2:0] ptr_in, ptr_p, ptr_m;
wire [2:0] WA, RA;
wire WE;
wire pop, push;
`ifdef FD_GTCLK
`ifdef FD_DFT
GTECH_AND_NOT utm1 (.Z(STS_CKenb_dft), .A(STS_CKenb), .B(SCAN_TEST));
GTECH_NOR2 uk0 (.Z(STSCLK_), .A(DSPCLK), .B(STS_CKenb_dft));
GtCLK_NOT ckSTSCLK (.Z(STSCLK), .A(STSCLK_));
`else
GTECH_NOR2 uk0 (.Z(STSCLK_), .A(DSPCLK), .B(STS_CKenb));
GtCLK_NOT ckSTSCLK (.Z(STSCLK), .A(STSCLK_));
`endif
`else
wire STSCLK_en=!STS_CKenb;
wire STSCLK = DSPCLK;
`endif
assign push = PushST_EN && !ST_full;
assign pop = PopST_EN && !ST_empty;
assign stkin[24:0] = STin[24:0];
assign ptr_p[2:0] = ptr[2:0] + 1'b1;
assign ptr_m[2:0] = ptr[2:0] - 1'b1;
assign ptr_in[2:0] = push ? ptr_p[2:0] : ptr_m[2:0];
always @(posedge STSCLK or posedge T_RST) begin
if (T_RST) ptr[2:0] <= #1 3'b111;
`ifdef FD_GTCLK
else if (push || pop) ptr[2:0] <= #1 ptr_in[2:0];
`else
else if ((push || pop) & STSCLK_en) ptr[2:0] <= #1 ptr_in[2:0];
`endif
end
assign ST_empty = (ptr[2:0] == 3'h7);
assign ST_full = (ptr[2:0] == 3'h6);
assign ST_has1 = (ptr[2:0] == 3'h0);
`ifdef FD_GTCLK
assign WE = push;
`else
assign WE = push & STSCLK_en;
`endif
assign WA[2:0] = ptr_p[2:0];
assign RA[2:0] = ptr[2:0];
STS7x23 sts7x23 (STSCLK, WE, WA[2:0], stkin[24:0], RA[2:0],
TopST[24:0]);
endmodule
module STS7x23 (STSCLK, WE, WA[2:0], stkin[24:0], RA[2:0], TopST[24:0]);
output [24:0] TopST;
input [24:0] stkin;
input [2:0] RA, WA;
input STSCLK, WE;
reg [24:0] STcell[6:0];
wire [24:0] TopST;
always @(posedge STSCLK)
if (WE) STcell[WA] <= #1 stkin[24:0];
assign TopST[24:0] = STcell[RA];
wire [24:0] ststk0 = STcell[0];
wire [24:0] ststk1 = STcell[1];
wire [24:0] ststk2 = STcell[2];
wire [24:0] ststk3 = STcell[3];
wire [24:0] ststk4 = STcell[4];
wire [24:0] ststk5 = STcell[5];
wire [24:0] ststk6 = STcell[6];
endmodule
|
`include "../include/x_def.v"
module AUTOctl (/* -------- Inputs : --------- */
T_RST, DSPCLK, GO_Ex, MFRX0_E, MFTX0_E,
MFRX1_E, MFTX1_E, MFSPT_E,
ICE_ST,
STBY,
DSreqi, DWRcyc, PWRcyc, /*CWRcyc,*/
DRDcyc, PRDcyc, /*CRDcyc,*/ BOOT,
T0Sreqi, R0Sreqi, RX0, TX0,
T1Sreqi, R1Sreqi, RX1, TX1,
BSreqi, BDMRD_cyc, BDMWR_cyc, BPMRD_cyc,
BPMWR_cyc, BM_cyc, ECYC,
`ifdef FD_DFT
SCAN_TEST,
`endif
STEAL, SREQ,
DMSreqx_wr, PMSreqx_wr, /*CMSreqx_wr,*/
DMSreqx_rd, PMSreqx_rd, /*CMSreqx_rd,*/
DSack, DSreqx,
T0Sreqx, R0Sreqx, T0Sack, R0Sack,
T1Sreqx, R1Sreqx, T1Sack, R1Sack,
spt0DMD_oe, spt1DMD_oe,
BSack, BSreqx,
autoDMD_do);
`ifdef FD_DFT
input SCAN_TEST;
`endif
input BSreqi,
BDMRD_cyc,
BDMWR_cyc,
BPMRD_cyc,
BPMWR_cyc,
BM_cyc,
ECYC;
input [15:0] RX0, RX1, TX0, TX1;
input T_RST,
DSPCLK,
GO_Ex,
STBY,
BOOT,
ICE_ST,
T0Sreqi,
R0Sreqi,
T1Sreqi,
R1Sreqi,
DSreqi,
DWRcyc,
PWRcyc,
DRDcyc,
PRDcyc;
input MFRX0_E, MFTX0_E, MFRX1_E,
MFTX1_E, MFSPT_E;
output STEAL,
SREQ,
T0Sack,
R0Sack,
T1Sack,
R1Sack,
DSack,
DSreqx,
T0Sreqx,
R0Sreqx,
T1Sreqx,
R1Sreqx,
spt0DMD_oe,
spt1DMD_oe,
PMSreqx_wr,
DMSreqx_wr,
PMSreqx_rd,
DMSreqx_rd,
BSack,
BSreqx;
output [15:0] autoDMD_do;
reg STEAL, DSack, T0Sack, R0Sack, T1Sack, R1Sack, BSack;
wire [15:0] DMD_do;
wire T0Sreqx, R0Sreqx, T1Sreqx, R1Sreqx, GO_SPT;
wire T0Sreq, R0Sreq, T1Sreq, R1Sreq, DSreq;
wire BSreq, BSreqx, SREQ_bdma;
assign #`da T0Sreq = T0Sreqi && !ICE_ST;
assign #`da R0Sreq = R0Sreqi && !ICE_ST;
assign #`da T1Sreq = T1Sreqi && !ICE_ST;
assign #`da R1Sreq = R1Sreqi && !ICE_ST;
assign #`da DSreq = DSreqi;
assign #`da BSreq = BSreqi && !ICE_ST;
assign #`da DMD_do[15:0] = {16{MFRX0_E}} & RX0[15:0] |
{16{MFTX0_E}} & TX0[15:0] |
{16{MFRX1_E}} & RX1[15:0] |
{16{MFTX1_E}} & TX1[15:0];
assign #`da autoDMD_do[15:0] = {16{MFSPT_E}} & DMD_do[15:0];
`ifdef FD_DFT
reg RST_h;
wire RST;
always @(posedge DSPCLK) RST_h <= #`db T_RST;
assign RST = SCAN_TEST ? T_RST : RST_h;
`else
reg RST;
always @(posedge DSPCLK) RST <= #`db T_RST;
`endif
assign #`da GO_SPT = GO_Ex || STEAL || STBY || BM_cyc && ECYC;
assign #`da SREQ = (GO_SPT || BOOT) && (
T0Sreq ||
R0Sreq ||
T1Sreq ||
R1Sreq ||
DSreq ||
BSreq);
always @(posedge DSPCLK or posedge RST)
begin
if (RST) STEAL <= #`db 1'b0;
else STEAL <= #`db SREQ;
end
assign #`da T0Sreqx = T0Sreq;
assign #`da R0Sreqx = R0Sreq && !T0Sreq;
assign #`da T1Sreqx = T1Sreq && !(T0Sreq || R0Sreq);
assign #`da R1Sreqx = R1Sreq && !(T0Sreq || R0Sreq || T1Sreq);
assign #`da DSreqx = DSreq && !(T0Sreq || R0Sreq || T1Sreq || R1Sreq);
assign #`da BSreqx = BSreq && !(T0Sreq || R0Sreq || T1Sreq || R1Sreq || DSreq);
always @(posedge DSPCLK or posedge RST)
begin
if (RST) T0Sack <= #`db 1'b0;
else if (T0Sack) T0Sack <= #`db 1'b0;
else if (GO_SPT) T0Sack <= #`db T0Sreqx;
end
always @(posedge DSPCLK or posedge RST)
begin
if (RST) R0Sack <= #`db 1'b0;
else if (R0Sack) R0Sack <= #`db 1'b0;
else if (GO_SPT) R0Sack <= #`db R0Sreqx;
end
always @(posedge DSPCLK or posedge RST)
begin
if (RST) T1Sack <= #`db 1'b0;
else if (T1Sack) T1Sack <= #`db 1'b0;
else if (GO_SPT) T1Sack <= #`db T1Sreqx;
end
always @(posedge DSPCLK or posedge RST)
begin
if (RST) R1Sack <= #`db 1'b0;
else if (R1Sack) R1Sack <= #`db 1'b0;
else if (GO_SPT) R1Sack <= #`db R1Sreqx;
end
assign #`da spt0DMD_oe = R0Sreqx && GO_SPT;
assign #`da spt1DMD_oe = R1Sreqx && GO_SPT;
always @(posedge DSPCLK or posedge RST)
begin
if (RST) DSack <= #`db 1'b0;
else if (DSack) DSack <= #`db 1'b0;
else if (GO_SPT || BOOT || ICE_ST)
DSack <= #`db DSreqx;
end
always @(posedge DSPCLK or posedge RST)
begin
if (RST) BSack <= #`db 1'b0;
else if (BSack) BSack <= #`db 1'b0;
else if (GO_SPT || BOOT) BSack <= #`db BSreqx;
end
assign #`da DMSreqx_wr =
R0Sreqx ||
R1Sreqx ||
DSreqx && DWRcyc ||
BSreqx && BDMRD_cyc;
assign #`da DMSreqx_rd = T0Sreqx ||
T1Sreqx ||
DSreqx && DRDcyc ||
BSreqx && BDMWR_cyc;
assign #`da PMSreqx_wr =
DSreqx && PWRcyc ||
BSreqx && BPMRD_cyc;
assign #`da PMSreqx_rd = DSreqx && PRDcyc ||
BSreqx && BPMWR_cyc;
endmodule
|
module COMPAND (/* in */ DTYPE0, RX0, TX0,
expRX0, logTX0);
input [1:0] DTYPE0;
input [15:0] RX0,
TX0;
output [15:0] expRX0;
output [7:0] logTX0;
EXPAND exp (/* in */ RX0[15:0], DTYPE0[1:0],
expRX0[15:0]);
COMPRESS log (/* in */ TX0[15:0], DTYPE0[0],
logTX0[7:0]);
endmodule
|
`include "../include/x_def.v"
module COMPRESS (/* in */ TX, alaw,
logTX);
input [15:0] TX;
input alaw;
output [7:0] logTX;
wire [12:1] newin;
wire [3:0] q;
wire [2:0] sc;
wire [14:0] magi, mag;
wire mover,ovf,negmax;
assign #`da magi[14:0] = TX[15] ? (~TX[14:0] + 1'b1) : TX[14:0];
assign #`da {ovf,mag[12:0]} = magi[12:0] + (alaw ? 1'b0 : 6'd33);
assign #`da mag[14:13] = magi[14:13];
assign #`da negmax = TX[15] & (~|magi[14:0]);
assign #`da mover = (|mag[14:13]) || alaw && mag[12] || ovf || negmax;
assign #`da newin[12:1] = mover ? {12'hfc0} :
alaw ? mag[11:0] :
mag[12:1];
wire [1:0] sc0, sc1;
cpen4 P1 (sc1[1:0], nzero1, newin[12:9]);
cpen4 P0 (sc0[1:0], nzero0, newin[8:5]);
assign #`da sc[1:0] = nzero1 ? sc1[1:0] :
nzero0 ? sc0[1:0] : 2'b11;
cpen2 P2 (nzero, sc[2], {nzero1, nzero0});
wire [3:0] as_;
wire shift7, shift6, shift5, shift4, shift3, shift2, shift1, shift0;
assign #`da q[3:0] = alaw && (!nzero || shift7) ? ~newin[5:2]
: as_[3:0];
assign #`da shift0 = (sc[2:0] == 3'd0);
assign #`da shift1 = (sc[2:0] == 3'd1);
assign #`da shift2 = (sc[2:0] == 3'd2);
assign #`da shift3 = (sc[2:0] == 3'd3);
assign #`da shift4 = (sc[2:0] == 3'd4);
assign #`da shift5 = (sc[2:0] == 3'd5);
assign #`da shift6 = (sc[2:0] == 3'd6);
assign #`da shift7 = (sc[2:0] == 3'd7);
assign #`da as_[3:0] = shift0 ? ~newin[11:8] :
shift1 ? ~newin[10:7] :
shift2 ? ~newin[9:6] :
shift3 ? ~newin[8:5] :
shift4 ? ~newin[7:4] :
shift5 ? ~newin[6:3] :
shift6 ? ~newin[5:2] :
shift7 ? ~newin[4:1] : 4'bx;
assign #`da logTX[7] = !TX[15];
assign #`da logTX[6] = sc[2];
assign #`da logTX[5] = alaw ? !sc[1] : sc[1];
assign #`da logTX[4] = sc[0];
assign #`da logTX[3] = alaw ? !q[3] : q[3];
assign #`da logTX[2] = q[2];
assign #`da logTX[1] = alaw ? !q[1] : q[1];
assign #`da logTX[0] = q[0];
endmodule
module cpen4 (e[1:0], nz, w[3:0]);
output [1:0] e;
output nz;
input [3:0] w;
assign #`da nz = |w[3:0];
assign #`da e[0] = (w[3:2] == 2'b01) || (w[3:0] == 4'b0001);
assign #`da e[1] = (w[3:2] == 2'b00);
endmodule
module cpen2 (nzero, sc, in[1:0]);
output nzero,
sc;
input [1:0] in;
assign #`da sc = (in[1] == 1'b0);
assign #`da nzero = (in[1:0] != 2'b0);
endmodule
|
`include "../include/x_def.v"
module EXPAND (/* in */ RX, DTYPE0,
expRX);
input [15:0] RX;
input [1:0] DTYPE0;
output [15:0] expRX;
wire [15:0] RX;
wire [12:0] as;
wire [7:0] newin;
wire alaw = DTYPE0[0];
wire expand = DTYPE0[1];
wire nzero;
assign #`da newin[7] = RX[7];
assign #`da newin[6] = RX[6];
assign #`da newin[5] = alaw ? !RX[5] : RX[5];
assign #`da newin[4] = RX[4];
assign #`da newin[3] = alaw ? !RX[3] : RX[3];
assign #`da newin[2] = RX[2];
assign #`da newin[1] = alaw ? !RX[1] : RX[1];
assign #`da newin[0] = RX[0];
assign #`da nzero = ~newin[7] & (&newin[6:0]);
wire [12:0] aso;
wire shift0, shift1, shift2, shift3, shift4, shift5, shift6, shift7;
assign #`da shift0 = (newin[6:4] == 3'd7);
assign #`da shift1 = (newin[6:4] == 3'd6);
assign #`da shift2 = (newin[6:4] == 3'd5);
assign #`da shift3 = (newin[6:4] == 3'd4);
assign #`da shift4 = (newin[6:4] == 3'd3);
assign #`da shift5 = (newin[6:4] == 3'd2);
assign #`da shift6 = (newin[6:4] == 3'd1);
assign #`da shift7 = (newin[6:4] == 3'd0);
assign #`da aso[12:0] = shift7 ? ~{1'b0, newin[3:0], 8'b01111111} :
shift6 ? ~{2'b10, newin[3:0], 7'b0111111} :
shift5 ? ~{3'b110, newin[3:0], 6'b011111} :
shift4 ? ~{4'b1110, newin[3:0], 5'b01111} :
shift3 ? ~{5'b11110, newin[3:0], 4'b0111} :
shift2 ? ~{6'b111110, newin[3:0], 3'b011} :
shift1 ? ~{7'b1111110, newin[3:0], 2'b01} :
shift0 ? ~{8'b11111110, newin[3:0], 1'b0} :
13'bx;
assign #`da as[12:0] = alaw && shift0 ? {aso[12:6], 1'b0, aso[4:0]} :
alaw && !shift0 ? {1'b0, aso[12:1]} :
aso[12:0];
wire [12:0] tc, asp;
assign #`da asp[12:0] = alaw ? as[12:0] : as[12:0] - 6'd33;
assign #`da tc[12:0] = newin[7] ? asp[12:0] : (~asp[12:0] + 1'b1);
assign expRX[15:0] = expand ?
(alaw ? {newin[7] ? 4'b0000 : 4'b1111, tc[11:0]} :
{newin[7]|nzero ? 3'b000 : 3'b111, tc[12:0]}) :
RX[15:0];
endmodule
|
`include "../include/x_def.v"
module RXctl0 (/* in */ RST, DSPCLK, GO_Cx, EX_en, SCLKg3_, SCLKg4,
SP_EN, RFSsm, RD, RSack, Rwrap, SLEN,
MWORD, RBUF, expRX, MTRX_E,
DTYPE, DMD, FSi_set,
`ifdef FD_DFT
SCAN_TEST,
`endif
RSreq, ISR, RX, SLOT1_EXT);
`ifdef FD_DFT
input SCAN_TEST;
`endif
input [1:0] DTYPE;
input [4:0] SLEN;
input [15:0] MWORD;
input [15:0] expRX,
DMD;
input RST,
DSPCLK,
GO_Cx,
EX_en,
SCLKg3_, SCLKg4,
SP_EN,
RFSsm,
RD,
RSack,
Rwrap,
RBUF,
MTRX_E;
input FSi_set;
output [15:0] RX;
output RSreq,
ISR;
output [3:2] SLOT1_EXT;
reg [15:0] RX,
RXSHT;
reg [2:0] RCS, RNS;
reg [4:0] Bcnt;
reg [7:0] Wcnt;
reg a_sync1, a_sync2, b_sync1;
reg ldRX_spt, ldRX_cmp, RSreq, sht2nd, ISRa;
reg TAG_SLOT;
wire [15:0] RX_di, RXSHT_di;
wire ldBcnt, ldWcnt, Bcnteq0, Wcnteq0, Wcnt_dn;
wire ldRXSHT, rawRX_we, RX_we, sRSreq, rRSreq,
ldRX_spt1, zeroext, AUlaw_en;
assign #`da zeroext = !(|{DTYPE[1:0]});
assign #`da AUlaw_en = DTYPE[1];
parameter RX_idle = 3'b001,
RX_shift = 3'b010,
RX_wstart = 3'b100;
always @(RCS or RFSsm or Bcnteq0 or Wcnteq0)
begin
case (RCS)
RX_idle : RNS <= #`da RFSsm ? RX_shift : RX_idle;
RX_shift : begin
if (Bcnteq0)
RNS <= #`da Wcnteq0 ? RX_idle : RX_wstart;
else
RNS <= #`da RX_shift;
end
RX_wstart : RNS <= #`da RX_shift;
default : RNS <= #`da RX_idle;
endcase
end
`ifdef FD_DFT
wire rst_SP_EN_h = !SP_EN ;
wire rst_SP_EN = SCAN_TEST ? RST : rst_SP_EN_h;
`else
wire rst_SP_EN = !SP_EN;
`endif
always @(posedge SCLKg4 or posedge rst_SP_EN) begin
if (rst_SP_EN) RCS <= #`db 3'b001;
else RCS <= #`db RNS;
end
always @(posedge SCLKg4) begin
sht2nd <= #`db (RCS != RX_shift) && (RNS == RX_shift);
end
assign #`da ldBcnt = RNS[0] || RNS[2];
assign #`da Bcnteq0 = !(|Bcnt[4:0]);
always @(posedge SCLKg4)
TAG_SLOT <= #`db MWORD[14] && FSi_set;
always @(posedge SCLKg4 or posedge rst_SP_EN) begin
if (rst_SP_EN) Bcnt[4:0] <= #`db 5'b0;
else if (TAG_SLOT) Bcnt[4:0] <= #`db 5'hf;
else if (ldBcnt) Bcnt[4:0] <= #`db SLEN[4:0];
else Bcnt[4:0] <= #`db Bcnt[4:0] - 1;
end
assign #`da ldWcnt = RNS[0];
assign #`da Wcnt_dn = RNS[2];
assign #`da Wcnteq0 = !(|Wcnt[7:0]);
always @(posedge SCLKg4 or posedge rst_SP_EN) begin
if (rst_SP_EN) Wcnt[7:0] <= #`db 8'b0;
else if (ldWcnt) Wcnt[7:0] <= #`db MWORD[7:0];
else if (Wcnt_dn) Wcnt[7:0] <= #`db Wcnt[7:0] - 1;
end
wire ldLMcnt, LMcnteq0;
reg [4:0] LMcnt;
assign #`da ldLMcnt = RNS[0] || RNS[2];
assign #`da LMcnteq0 = !(|LMcnt[4:0]);
always @(posedge SCLKg4 or posedge rst_SP_EN) begin
if (rst_SP_EN) LMcnt[4:0] <= #`db 5'b0;
else if (ldLMcnt) LMcnt[4:0] <= #`db 5'h10;
else if (LMcnteq0) LMcnt[4:0] <= #`db 5'b0;
else LMcnt[4:0] <= #`db LMcnt[4:0] - 1;
end
wire [3:2] ST_SLOT1_EXT;
reg [3:2] SLOT1_EXT;
assign #`da ST_SLOT1_EXT[3] = (Wcnt == 'd11 && Bcnt == 'd3) ;
assign #`da ST_SLOT1_EXT[2] = (Wcnt == 'd11 && Bcnt == 'd2) ;
always @(posedge SCLKg4 or posedge RST ) begin
if (RST) SLOT1_EXT[3] <= #`db 1'b0;
else if (ST_SLOT1_EXT[3]) SLOT1_EXT[3] <= #`db RD;
else SLOT1_EXT[3] <= #`db SLOT1_EXT[3];
end
always @(posedge SCLKg4 or posedge RST ) begin
if (RST) SLOT1_EXT[2] <= #`db 1'b0;
else if (ST_SLOT1_EXT[2]) SLOT1_EXT[2] <= #`db RD;
else SLOT1_EXT[2] <= #`db SLOT1_EXT[2];
end
assign #`da ldRXSHT = !LMcnteq0 && (RFSsm || !RCS[0]);
assign #`da RXSHT_di[15:0] = sht2nd ? (zeroext ? {14'b0, RXSHT[0], RD}
: {{15{RXSHT[0]}}, RD})
: {RXSHT[14:0], RD};
always @(posedge SCLKg3_)
if (ldRXSHT) RXSHT[15:0] <= #`db RXSHT_di[15:0];
assign #`da rawRX_we = MTRX_E && EX_en && GO_Cx ||
ldRX_spt1;
assign #`da RX_we = rawRX_we ||
ldRX_cmp;
assign #`da RX_di = ldRX_spt1 ? RXSHT[15:0] :
ldRX_cmp ? expRX[15:0] : DMD[15:0];
always @(posedge DSPCLK)
if (RX_we) RX[15:0] <= #`db RX_di;
always @(posedge SCLKg3_) ldRX_spt <= #`db RCS[1] && !RNS[1];
always @(posedge DSPCLK) begin
a_sync1 <= #`db ldRX_spt;
a_sync2 <= #`db a_sync1;
end
assign #`da ldRX_spt1 = a_sync1 && !a_sync2;
always @(posedge DSPCLK) begin
b_sync1 <= #`db rawRX_we;
ldRX_cmp <= #`db b_sync1;
end
Delaya d1 (RSack, delRSack);
`ifdef FD_DFT
wire rRSreq_h = (RST || delRSack);
assign rRSreq = SCAN_TEST ? RST : rRSreq_h;
`else
assign #`da rRSreq = RST || delRSack;
`endif
assign #`da sRSreq = SP_EN && RBUF && (AUlaw_en ? ldRX_cmp : rawRX_we);
always @(posedge DSPCLK or posedge rRSreq) begin
if (rRSreq) RSreq <= #`db 1'b0;
else if (sRSreq) RSreq <= #`db 1'b1;
end
always @(posedge DSPCLK)
ISRa <= #`db SP_EN && (AUlaw_en ? ldRX_cmp : ldRX_spt1);
assign #`da ISR = RBUF ? Rwrap : ISRa;
endmodule
|
`include "../include/x_def.v"
module SCFG0 (/* in */ RST, DSPCLK, SP_EN, FSDIV, SCLKDIV,
ISCLK, FSD, FSW, ITFS, IRFS, INVTFS, INVRFS,
SLEN, INVxSCLK, AC97_MODE, MWORD_13,
`ifdef FD_DFT
SCAN_TEST,
`endif
SP_ENg, RFSsm, TFSsm, SCLKg3_, SCLKg4, SCLKg5,
SCLKg6, FSi_set,
SCLKo, T_SCLK, RFSi, T_RFS, TFSi, T_TFS);
input [15:0] FSDIV,
SCLKDIV;
input [4:0] SLEN;
input [1:0] FSD;
input RST,
DSPCLK,
SP_EN,
ISCLK,
FSW,
ITFS,
IRFS,
INVTFS,
INVRFS,
INVxSCLK,
T_SCLK,
T_RFS,
T_TFS;
input AC97_MODE;
input MWORD_13;
`ifdef FD_DFT
input SCAN_TEST;
`endif
output SCLKo,
RFSi,
TFSi,
SP_ENg,
SCLKg3_, SCLKg4,
SCLKg5, SCLKg6,
RFSsm,
TFSsm;
output FSi_set;
reg [15:0] SCLKi_cnt, FSi_cnt;
reg FSi, RFSg_d1, RFSg_d2, RFSg_d3, TFSg_d1,
TFSg_d2, TFSg_d3, FS_s1, FS_s2, SP_ENg;
reg SP_ENg_D1;
wire SCLKi_chg, FSi_clr, RFSgi, TFSgi, SCLKo,
RFSg, TFSg, FSfall, SCLKg, SCLKg1, SCLKg2;
wire FIRST_FS, T_SCLKi;
wire SCLKin;
reg SCLKi_enb;
always @(posedge DSPCLK) SCLKi_enb <= #`db !((SP_ENg || SP_EN) && ISCLK);
`ifdef FD_GTCLK
`ifdef FD_DFT
wire SCLKi_enb_dft;
GTECH_AND_NOT utm1 (.Z(SCLKi_enb_dft), .A(SCLKi_enb), .B(SCAN_TEST));
GtCLK_NOR2 uck0 (.Z(SCLKin_), .A(DSPCLK), .B(SCLKi_enb_dft));
GtCLK_NOT ckSCLKin (.Z(SCLKin), .A(SCLKin_));
`else
GtCLK_NOR2 uck0 (.Z(SCLKin_), .A(DSPCLK), .B(SCLKi_enb));
GtCLK_NOT ckSCLKin (.Z(SCLKin), .A(SCLKin_));
`endif
`else
assign #`d0 SCLKin = DSPCLK;
`endif
assign #`da SCLKi_chg = (SCLKi_cnt[15:0] == SCLKDIV[15:0]) || !SP_ENg;
always @(posedge SCLKin or posedge RST) begin
if (RST) SCLKi_cnt[15:0] <= #`db 16'b0;
else if (SCLKi_chg) SCLKi_cnt[15:0] <= #`db 16'b0;
else SCLKi_cnt[15:0] <= #`db SCLKi_cnt + 1;
end
reg SCLKi_h;
wire SCLKi;
always @(posedge SCLKin or posedge RST) begin
if (RST) SCLKi_h <= #`db 1'b0;
else if (SCLKi_chg) SCLKi_h <= #`db !SCLKi;
end
assign SCLKi = SCLKi_h;
assign #`da SCLKo = INVxSCLK ^ SCLKi;
`ifdef FD_DFT
assign #`da T_SCLKi = SCAN_TEST ? T_SCLK : INVxSCLK ^ T_SCLK;
`else
assign #`da T_SCLKi = INVxSCLK ^ T_SCLK;
`endif
`ifdef FD_FPGA
`ifdef FD_EVB
wire SCLKgi;
assign #`da SCLKgi = ISCLK ? SCLKi : T_SCLKi;
BUFG sclk0 (.I(SCLKgi), .O(SCLKg));
`else
assign #`da SCLKg = ISCLK ? SCLKi : T_SCLKi;
`endif
assign #`da SCLKg1 = SCLKg;
assign #`da SCLKg2 = SCLKg;
assign #`da SCLKg3_ = !SCLKg;
assign #`da SCLKg4 = SCLKg;
assign #`da SCLKg5 = SCLKg;
assign #`da SCLKg6 = SCLKg;
`else
`ifdef FD_DFT
wire ISCLK_dft;
assign ISCLK_dft = ISCLK && !SCAN_TEST;
GtCLK_MUX2 uu0 (.Z(SCLKg), .S(ISCLK_dft), .A(T_SCLKi), .B(SCLKi));
`else
GtCLK_MUX2 uu0 (.Z(SCLKg), .S(ISCLK), .A(T_SCLKi), .B(SCLKi));
`endif
GtCLK_NOT uu1 (.Z(SCLKga_), .A(SCLKg));
GtCLK_NOT uu2 (.Z(SCLKg3_), .A(SCLKg));
GtCLK_NOT uu3 (.Z(SCLKgc_), .A(SCLKg));
GtCLK_NOT uu4 (.Z(SCLKg1), .A(SCLKga_));
GtCLK_NOT uu5 (.Z(SCLKg2), .A(SCLKga_));
GtCLK_NOT uu6 (.Z(SCLKg4), .A(SCLKg3_));
GtCLK_NOT uu7 (.Z(SCLKg5), .A(SCLKgc_));
GtCLK_NOT uu8 (.Z(SCLKg6), .A(SCLKgc_));
`endif
assign #`da FSi_set = SP_ENg && SP_EN && ((FSi_cnt[15:0] == FSDIV[15:0])
|| !(IRFS || ITFS));
always @(posedge SCLKg1 or posedge RST) begin
if (RST) FSi_cnt[15:0] <= #`db 16'b0;
else if ( FIRST_FS) FSi_cnt[15:0] <= #`db FSDIV[15:0];
else if ( FSi_set) FSi_cnt[15:0] <= #`db 16'b0;
else if ( SP_ENg ) FSi_cnt[15:0] <= #`db FSi_cnt + 1;
else FSi_cnt[15:0] <= #`db FSi_cnt;
end
assign #`da FSi_clr = !FSW ||
(FSi_cnt[4:0] == SLEN[4:0]) ||
(AC97_MODE && FSi_cnt[4:0] == 'hf) ||
!SP_ENg;
always @(posedge SCLKg2 or posedge RST) begin
if (RST) FSi <= #`db 1'b0;
else if (FSi && FSi_clr) FSi <= #`db 1'b0;
else if (FSi_set) FSi <= #`db 1'b1;
end
wire AC97_RST;
assign #`da AC97_RST = AC97_MODE && MWORD_13;
assign #`da RFSi = FSi ^ INVRFS || AC97_RST;
assign #`da TFSi = FSi ^ INVTFS || AC97_RST;
assign #2.0 RFSgi = INVRFS ^ (IRFS ? RFSi : T_RFS);
assign #2.0 TFSgi = INVTFS ^ (ITFS ? TFSi : T_TFS);
always @(posedge SCLKg2 or posedge RST) begin
if (RST) SP_ENg <= #`db 0;
else SP_ENg <= #`db SP_EN;
end
always @(posedge SCLKg2) begin
SP_ENg_D1 <= #`db SP_ENg;
end
reg RFSgi_d, TFSgi_d;
always @(posedge SCLKg2 or posedge RST) begin
if (RST) RFSgi_d <= 1'b0;
else RFSgi_d <= RFSgi;
end
always @(posedge SCLKg2 or posedge RST) begin
if (RST) TFSgi_d <= #`db 1'b0;
else TFSgi_d <= #`db TFSgi;
end
assign #`da RFSg = SP_ENg && RFSgi && !RFSgi_d;
assign #`da TFSg = SP_ENg && TFSgi && !TFSgi_d;
assign #`da FIRST_FS = !SP_ENg_D1 && SP_ENg;
always @(posedge SCLKg2 or posedge RST) begin
if (RST) begin
RFSg_d1 <= #`db 1'b0;
RFSg_d2 <= #`db 1'b0;
RFSg_d3 <= #`db 1'b0;
TFSg_d1 <= #`db 1'b0;
TFSg_d2 <= #`db 1'b0;
TFSg_d3 <= #`db 1'b0;
end
else begin
RFSg_d1 <= #`db RFSg;
RFSg_d2 <= #`db RFSg_d1;
RFSg_d3 <= #`db RFSg_d2;
TFSg_d1 <= #`db TFSg;
TFSg_d2 <= #`db TFSg_d1;
TFSg_d3 <= #`db TFSg_d2;
end
end
assign #`da RFSsm = (FSD[1:0] == 2'b00) ? RFSg :
(FSD[1:0] == 2'b01) ? RFSg_d1 :
(FSD[1:0] == 2'b10) ? RFSg_d2 : RFSg_d3;
assign #`da TFSsm = (FSD[1:0] == 2'b00) ? TFSg :
(FSD[1:0] == 2'b01) ? TFSg_d1 :
(FSD[1:0] == 2'b10) ? TFSg_d2 : TFSg_d3;
endmodule
|
`include "../include/x_def.v"
module SCreg0 (/* in */ RST, DSPCLK, selAUTO, selFSDIV, selSCLKDIV,
selSCTL, selMWORD, AUTO_we, FSDIV_we, SCLKDIV_we,
SCTL_we, MWORD_we, DMD, MMR_web,
SLOT1_EXT, SLOT_NUM,
`ifdef FD_DFT
`endif
TIREG, TMREG, RIREG, RMREG,
TBUF, RBUF, FSDIV, SCLKDIV, LOOP,
ISCLK, FSD, FSW, ITFS, IRFS, INVTFS, INVRFS,
DTYPE, SLEN, MWORD, XTALDIS,
XTALDELAY, PDFORCE, PUCR, DMD_do, SLEN_ex,
INVxSCLK);
input [15:0] DMD;
input RST,
DSPCLK,
selAUTO,
selFSDIV,
selSCLKDIV,
selSCTL,
selMWORD,
AUTO_we,
FSDIV_we,
SCLKDIV_we,
SCTL_we,
MWORD_we,
MMR_web;
input [3:0] SLOT_NUM;
input [3:2] SLOT1_EXT;
`ifdef FD_DFT
input SCAN_TEST;
`endif
output [2:0] TIREG,
RIREG;
output [1:0] TMREG,
RMREG;
output [15:0] FSDIV,
SCLKDIV,
DMD_do;
output [1:0] FSD,
DTYPE;
output [4:0] SLEN;
output [15:0] MWORD;
output TBUF,
RBUF,
LOOP,
ISCLK,
FSW,
ITFS,
IRFS,
INVTFS,
INVRFS,
XTALDIS,
XTALDELAY,
PDFORCE,
SLEN_ex,
INVxSCLK,
PUCR;
wire [11:0] DMD_MW;
wire [15:0] DMD_SCTL, DMD_FSDIV;
wire [15:0] MWORD;
wire [15:0] FSDIV, SCLKDIV, SCTL;
wire [11:0] AUTO_b;
wire [11:0] MW_OUT;
reg [15:12] AUTO_a;
wire [15:0] AUTO;
wire SPbas_R, SPidx_R;
wire SLEN_ex, INVxSCLK;
wire AC97_PSET, FSDIV_we_PSET, SCTL_we_PSET, MWORD_we_PSET;
wire [15:0] AC97_FSDIV = `AC97_FSDIV;
wire [15:0] AC97_SCTL = `AC97_SCTL;
wire [11:0] AC97_MWORD = `AC97_MWORD;
assign #`da AC97_PSET = MWORD_we && DMD[14];
assign #`da FSDIV_we_PSET = FSDIV_we || AC97_PSET;
assign #`da SCTL_we_PSET = SCTL_we || AC97_PSET;
assign #`da MWORD_we_PSET = MWORD_we || AC97_PSET;
wire [15:0] MWORD_RD;
wire AC97_MODE = MWORD[14];
assign #`da MWORD_RD[15:0] = !AC97_MODE ? {MWORD[15:13], 5'b0, MWORD[7:0]} :
{MWORD[15:14], SLOT1_EXT[3:2], SLOT_NUM[3:0], MWORD[7:0]};
assign #`da DMD_do[15:0] = {16{selAUTO}} & AUTO[15:0] |
{16{selFSDIV}} & FSDIV[15:0] |
{16{selSCLKDIV}} & SCLKDIV[15:0] |
{16{selSCTL}} & SCTL[15:0] |
{16{selMWORD}} & MWORD_RD[15:0];
assign #`da AUTO[15:0] = {AUTO_a[15:12], AUTO_b[11:0]};
always @(posedge DSPCLK or posedge RST)
begin
if (RST)
begin
AUTO_a[15:14] <= #`db 2'b0;
AUTO_a[12] <= #`db 1'b0;
end
else if (AUTO_we)
begin
AUTO_a[15:14] <= #`db DMD[15:14];
AUTO_a[12] <= #`db DMD[12];
end
end
always @(posedge DSPCLK or posedge RST) begin
if (RST) AUTO_a[13] <= #`db 1'b0;
else if (AUTO_we) AUTO_a[13] <= #`db DMD[13];
else if (AUTO_a[13]) AUTO_a[13] <= #`db 1'b0;
end
`ifdef FD_DFT
REG12LC AUTOreg (DSPCLK, MMR_web, AUTO_we, DMD[11:0], AUTO_b[11:0], RST, SCAN_TEST);
`else
REG12LC AUTOreg (DSPCLK, MMR_web, AUTO_we, DMD[11:0], AUTO_b[11:0], RST);
`endif
assign #`d0 XTALDIS = AUTO[15];
assign #`d0 XTALDELAY = AUTO[14];
assign #`d0 PDFORCE = AUTO[13];
assign #`d0 PUCR = AUTO[12];
assign #`d0 {TIREG[2:0], TMREG[1:0], RIREG[2:0],
RMREG[1:0], TBUF, RBUF} = AUTO[11:0];
assign #`d0 DMD_FSDIV[15:0] = AC97_PSET ? AC97_FSDIV : DMD[15:0];
`ifdef FD_DFT
REG16LC FSDIVreg (DSPCLK, MMR_web, FSDIV_we_PSET, DMD_FSDIV[15:0], FSDIV[15:0], RST, SCAN_TEST);
`else
REG16LC FSDIVreg (DSPCLK, MMR_web, FSDIV_we_PSET, DMD_FSDIV[15:0], FSDIV[15:0], RST);
`endif
`ifdef FD_DFT
REG16LC SCLKDIVreg (DSPCLK, MMR_web, SCLKDIV_we, DMD[15:0],
SCLKDIV[15:0], RST, SCAN_TEST);
`else
REG16LC SCLKDIVreg (DSPCLK, MMR_web, SCLKDIV_we, DMD[15:0],
SCLKDIV[15:0], RST);
`endif
assign #`d0 DMD_SCTL[15:0] = AC97_PSET ? AC97_SCTL : DMD[15:0];
`ifdef FD_DFT
SREG16MC SCTLreg (DSPCLK, MMR_web, SCTL_we_PSET, DMD_SCTL[15:0], SCTL[15:0], RST, SCAN_TEST);
`else
SREG16MC SCTLreg (DSPCLK, MMR_web, SCTL_we_PSET, DMD_SCTL[15:0], SCTL[15:0], RST);
`endif
assign #`d0 LOOP = SCTL[15];
assign #`d0 ISCLK = SCTL[14];
assign #`da INVxSCLK = SCTL[13];
assign #`d0 FSD[1:0] = SCTL[12:11];
assign #`d0 FSW = SCTL[10];
assign #`d0 ITFS = SCTL[9];
assign #`d0 IRFS = SCTL[8];
assign #`d0 INVTFS = SCTL[7];
assign #`d0 INVRFS = SCTL[6];
assign #`d0 DTYPE[1:0] = SCTL[5:4];
assign #`d0 SLEN_ex = MWORD[15];
assign #`d0 SLEN[4:0] = {SLEN_ex, SCTL[3:0]};
assign #`d0 DMD_MW[10:0] = AC97_PSET ? AC97_MWORD | {2'b0,DMD[13],8'b0} :
{DMD[15:13], DMD[7:0]};
assign #`d0 MWORD[15:0] = {MW_OUT[10:8], 5'b0, MW_OUT[7:0]};
`ifdef FD_DFT
REG11LC MWORDreg (DSPCLK, MMR_web, MWORD_we_PSET, DMD_MW[10:0], MW_OUT[10:0], RST, SCAN_TEST);
`else
REG11LC MWORDreg (DSPCLK, MMR_web, MWORD_we_PSET, DMD_MW[10:0], MW_OUT[10:0], RST);
`endif
endmodule
|
`include "../include/x_def.v"
module SPORT0 (/* -------- Inputs : --------- */
RDx,
T_RST, DSPCLK, GO_Cx, EX_en, MTTX_E,
MTRX_E, Twrap, Rwrap, DMD,
SP_EN, selAUTO, selFSDIV, selSCLKDIV,
selSCTL, selMWORD, AUTO_we, FSDIV_we,
SCLKDIV_we, SCTL_we, MWORD_we, MMR_web,
TSack, RSack,
`ifdef FD_DFT
SCAN_TEST,
`endif
TDx,
ISR, IST, TIREG, TMREG,
RIREG, RMREG, PDFORCE,
XTALDIS, XTALDELAY, PUCR,
TSreq, RSreq, RX, TX,
DMD_do,
SCLKo, T_SCLK, ISCLK,
RFSi, T_RFS, IRFS,
TFSi, T_TFS, ITFS);
input [15:0] DMD;
input RDx,
T_RST,
DSPCLK,
GO_Cx,
EX_en,
SP_EN,
selAUTO,
selFSDIV,
selSCLKDIV,
selSCTL,
selMWORD,
AUTO_we,
FSDIV_we,
SCLKDIV_we,
SCTL_we,
MWORD_we,
MTTX_E,
MTRX_E,
Twrap,
Rwrap,
TSack,
RSack,
T_SCLK,
T_RFS,
T_TFS,
MMR_web;
`ifdef FD_DFT
input SCAN_TEST;
`endif
output [15:0] RX, TX,
DMD_do;
output [2:0] TIREG,
RIREG;
output [1:0] TMREG,
RMREG;
output TDx,
ISR,
IST,
TSreq,
RSreq,
XTALDIS,
XTALDELAY,
PDFORCE,
PUCR,
ISCLK,
SCLKo,
IRFS,
RFSi,
ITFS,
TFSi;
wire [15:0] expRX, FSDIV, SCLKDIV, DMDin;
wire [15:0] MWORD;
wire [7:0] logTX;
wire [4:0] SLEN;
wire [1:0] FSD, DTYPE;
wire [3:2] SLOT1_EXT;
wire [3:0] SLOT_NUM;
SPGLUE0 glue (/* in */ T_RST, DSPCLK, LOOP, TD, RDx,
`ifdef FD_DFT
SCAN_TEST,
`endif
RST, RD, TDx);
SCreg0 regs (/* in */ RST, DSPCLK, selAUTO, selFSDIV, selSCLKDIV,
selSCTL, selMWORD, AUTO_we, FSDIV_we, SCLKDIV_we,
SCTL_we, MWORD_we, DMDin[15:0], MMR_web,
SLOT1_EXT[3:2], SLOT_NUM[3:0],
`ifdef FD_DFT
SCAN_TEST,
`endif
TIREG[2:0], TMREG[1:0], RIREG[2:0], RMREG[1:0],
TBUF, RBUF, FSDIV[15:0], SCLKDIV[15:0], LOOP,
ISCLK, FSD[1:0], FSW, ITFS, IRFS, INVTFS, INVRFS,
DTYPE[1:0], SLEN[4:0], MWORD[15:0], XTALDIS,
XTALDELAY, PDFORCE, PUCR, DMD_do[15:0], SLEN_ex,
INVxSCLK);
SCFG0 cfg (/* in */ RST, DSPCLK, SP_EN, FSDIV[15:0], SCLKDIV[15:0],
ISCLK, FSD[1:0], FSW, ITFS, IRFS, INVTFS, INVRFS,
SLEN[4:0], INVxSCLK, MWORD[14], MWORD[13],
`ifdef FD_DFT
SCAN_TEST,
`endif
SP_ENg, RFSsm, TFSsm, SCLKg3_, SCLKg4, SCLKg5,
SCLKg6, FSi_set,
SCLKo, T_SCLK, RFSi, T_RFS, TFSi, T_TFS);
TXctl0 txctl (/* in */ RST, DSPCLK, GO_Cx, EX_en, SCLKg5, SCLKg6,
SP_EN, SP_ENg, TFSsm, TSack, Twrap, SLEN[4:0],
MWORD[15:0], TBUF, logTX[7:0], MTTX_E,
DMDin[15:0], DTYPE[1], SLEN_ex, FSi_set,
`ifdef FD_DFT
SCAN_TEST,
`endif
TD, TSreq, IST, TX[15:0], SLOT_NUM[3:0]);
RXctl0 rxctl (/* in */ RST, DSPCLK, GO_Cx, EX_en, SCLKg3_, SCLKg4,
SP_ENg, RFSsm, RD, RSack, Rwrap, SLEN[4:0],
MWORD[15:0], RBUF, expRX[15:0], MTRX_E,
DTYPE[1:0], DMDin[15:0], FSi_set,
`ifdef FD_DFT
SCAN_TEST,
`endif
RSreq, ISR, RX[15:0], SLOT1_EXT[3:2]);
COMPAND cmpd (/* in */ DTYPE[1:0], RX[15:0], TX[15:0],
expRX[15:0], logTX[7:0]);
DMDbuf DMDIN_BUF(DMD[15:0], DMDin[15:0]);
endmodule
module SPGLUE0 (/* in */ T_RST, DSPCLK, LOOP, TD, RDx,
`ifdef FD_DFT
SCAN_TEST,
`endif
RST, RD, TDx);
`ifdef FD_DFT
input SCAN_TEST;
`endif
input T_RST, DSPCLK, LOOP, TD, RDx;
output RST, RD, TDx;
`ifdef FD_DFT
reg RST_h;
wire RST;
always @(posedge DSPCLK) RST_h <= #`db T_RST;
assign RST = SCAN_TEST ? T_RST : RST_h;
`else
reg RST;
always @(posedge DSPCLK) RST <= #`db T_RST;
`endif
assign #`da RD = LOOP ? TD : RDx;
assign #`da TDx = LOOP ? 1'b0 : TD;
endmodule
|
`include "../include/x_def.v"
module TXctl0 (/* in */ RST, DSPCLK, GO_Cx, EX_en, SCLKg5, SCLKg6,
SP_EN, SP_ENg, TFSsm, TSack, Twrap, SLEN,
MWORD, TBUF, logTX, MTTX_E,
DMD, AUlaw_en, SLEN_ex, FSi_set,
`ifdef FD_DFT
SCAN_TEST,
`endif
TD, TSreq, IST, TX, SLOT_NUM);
`ifdef FD_DFT
input SCAN_TEST;
`endif
input [4:0] SLEN;
input [15:0] MWORD;
input [7:0] logTX;
input [15:0] DMD;
input RST,
DSPCLK,
GO_Cx,
EX_en,
SCLKg5, SCLKg6,
SP_EN,
SP_ENg,
SLEN_ex,
TFSsm,
TSack,
Twrap,
TBUF,
MTTX_E,
AUlaw_en;
input FSi_set;
output [15:0] TX;
output TD,
TSreq,
IST;
output [3:0] SLOT_NUM;
reg [15:0] TX,
TXSHT;
reg [2:0] TCS, TNS;
reg [4:0] Bcnt;
reg [7:0] Wcnt;
reg b_sync1, c_sync1, c_sync2, ldTX_cmp, TSreqi,
TSreq, ISTai;
reg TAG_SLOT;
wire [15:0] TX_di, TXSHT_di;
wire ldBcnt, ldWcnt, Bcnteq0, Wcnteq0, Wcnt_dn;
wire rawTX_we, TX_we, ISTa, sTSreq, rTSreq;
parameter TX_idle = 3'b001,
TX_shift = 3'b010,
TX_wstart = 3'b100;
always @(TCS or TFSsm or Bcnteq0 or Wcnteq0)
begin
case (TCS)
TX_idle : TNS <= #`da TFSsm ? TX_shift : TX_idle;
TX_shift : begin
if (Bcnteq0)
TNS <= #`da Wcnteq0 ? TX_idle : TX_wstart;
else
TNS <= #`da TX_shift;
end
TX_wstart : TNS <= #`da TX_shift;
default : TNS <= #`da TX_idle;
endcase
end
`ifdef FD_DFT
wire rst_SP_ENg_h = !SP_ENg ;
wire rst_SP_ENg = SCAN_TEST ? RST : rst_SP_ENg_h;
`else
wire rst_SP_ENg = !SP_ENg;
`endif
always @(posedge SCLKg5 or posedge rst_SP_ENg) begin
if (rst_SP_ENg) TCS <= #`db 3'b001;
else TCS <= #`db TNS;
end
assign #`da ldBcnt = TNS[0] || TNS[2];
assign #`da Bcnteq0 = !(|Bcnt[4:0]);
always @(posedge SCLKg5)
TAG_SLOT <= #`db MWORD[14] && FSi_set;
always @(posedge SCLKg5 or posedge rst_SP_ENg) begin
if (rst_SP_ENg) Bcnt[4:0] <= #`db 5'b0;
else if (TAG_SLOT) Bcnt[4:0] <= #`db 5'hf;
else if (ldBcnt) Bcnt[4:0] <= #`db SLEN[4:0];
else Bcnt[4:0] <= #`db Bcnt[4:0] - 1;
end
assign #`da ldWcnt = TNS[0];
assign #`da Wcnt_dn = TNS[2];
assign #`da Wcnteq0 = !(|Wcnt[7:0]);
assign #`da SLOT_NUM[3:0] = Wcnt[3:0];
always @(posedge SCLKg5 or posedge rst_SP_ENg) begin
if (rst_SP_ENg) Wcnt[7:0] <= #`db 8'b0;
else if (ldWcnt) Wcnt[7:0] <= #`db MWORD[7:0];
else if (Wcnt_dn) Wcnt[7:0] <= #`db Wcnt[7:0] - 1;
end
assign #`da TXSHT_di[15:0] = TNS[1] ? {TXSHT[14:0], 1'b0}
: TX[15:0];
always @(posedge SCLKg6) TXSHT[15:0] <= #`db TXSHT_di[15:0];
wire [3:0] slen_msb = SLEN[3:0];
assign #`d0 TD = SLEN_ex ? TXSHT[15] : TXSHT[slen_msb];
assign #`da rawTX_we = MTTX_E && EX_en && GO_Cx ||
TSack;
assign #`da TX_we = rawTX_we ||
ldTX_cmp;
assign #`da TX_di = ldTX_cmp ? {{8{logTX[7]}}, logTX[7:0]} : DMD[15:0];
always @(posedge DSPCLK) if (TX_we) TX[15:0] <= #`db TX_di;
always @(posedge DSPCLK) begin
b_sync1 <= #`db rawTX_we;
ldTX_cmp <= #`db b_sync1 && AUlaw_en/* && SP_EN*/;
end
Delaya d1 (TSack, delTSack);
reg SP_EN_D1;
wire SP_EN_1T;
always @(posedge DSPCLK) SP_EN_D1 <= #`db SP_EN;
assign #`da SP_EN_1T = SP_EN && !SP_EN_D1;
`ifdef FD_DFT
wire rTSreq_h = (RST || delTSack);
assign rTSreq = SCAN_TEST ? RST : rTSreq_h;
`else
assign #`da rTSreq = RST || delTSack;
`endif
assign #`da sTSreq = SP_ENg && TBUF && !TCS[1] && TNS[1];
always @(posedge SCLKg5 or posedge rTSreq) begin
if (rTSreq) TSreqi <= #`db 1'b0;
else if (sTSreq) TSreqi <= #`db 1'b1;
end
always @(posedge DSPCLK or posedge rTSreq) begin
if (rTSreq) TSreq <= #`db 1'b0;
else TSreq <= #`db TSreqi || (SP_EN_1T && MWORD[14]);
end
always @(posedge SCLKg5 or posedge RST)
if (RST) ISTai <= #`db 1'b0;
else ISTai <= #`db SP_ENg && (!TCS[1] && TNS[1]);
always @(posedge DSPCLK) begin
c_sync1 <= #`db ISTai;
c_sync2 <= #`db c_sync1;
end
assign #`da ISTa = c_sync1 && !c_sync2;
assign #`da IST = TBUF ? Twrap : ISTa;
endmodule
|
`include "../include/x_def.v"
module RXctl1 (/* in */ RST, DSPCLK, GO_Cx, EX_en, SCLKg3_, SCLKg4,
SP_EN, RFSsm, RD, RSack, Rwrap, SLEN,
MWORD, RBUF, FSi_set,
/*expRX[15:0],*/ MTRX_E, DTYPE, DMD,
`ifdef FD_DFT
SCAN_TEST,
`endif
RSreq, ISR, RX, SLOT1_EXT);
`ifdef FD_DFT
input SCAN_TEST;
`endif
input [1:0] DTYPE;
input [4:0] SLEN;
input [15:0] MWORD;
input [15:0] DMD;
input RST,
DSPCLK,
GO_Cx,
EX_en,
SCLKg3_, SCLKg4,
SP_EN,
RFSsm,
RD,
RSack,
Rwrap,
RBUF,
MTRX_E;
input FSi_set;
output [15:0] RX;
output RSreq,
ISR;
output [3:2] SLOT1_EXT;
reg [15:0] RX,
RXSHT;
reg [2:0] RCS, RNS;
reg [4:0] Bcnt;
reg [7:0] Wcnt;
reg a_sync1, a_sync2, b_sync1;
reg ldRX_spt, ldRX_cmp, RSreq, sht2nd, ISRa;
reg TAG_SLOT;
wire [15:0] RX_di, RXSHT_di;
wire ldBcnt, ldWcnt, Bcnteq0, Wcnteq0, Wcnt_dn;
wire ldRXSHT, rawRX_we, RX_we, sRSreq, rRSreq,
ldRX_spt1, zeroext, AUlaw_en;
assign #`da zeroext = !(|{DTYPE[1:0]});
assign #`da AUlaw_en = DTYPE[1];
parameter RX_idle = 3'b001,
RX_shift = 3'b010,
RX_wstart = 3'b100;
always @(RCS or RFSsm or Bcnteq0 or Wcnteq0)
begin
case (RCS)
RX_idle : RNS <= #`da RFSsm ? RX_shift : RX_idle;
RX_shift : begin
if (Bcnteq0)
RNS <= #`da Wcnteq0 ? RX_idle : RX_wstart;
else
RNS <= #`da RX_shift;
end
RX_wstart : RNS <= #`da RX_shift;
default : RNS <= #`da RX_idle;
endcase
end
`ifdef FD_DFT
wire rst_SP_EN_h = !SP_EN;
wire rst_SP_EN = SCAN_TEST ? RST : rst_SP_EN_h;
`else
wire rst_SP_EN = !SP_EN;
`endif
always @(posedge SCLKg4 or posedge rst_SP_EN) begin
if (rst_SP_EN) RCS <= #`db 3'b001;
else RCS <= #`db RNS;
end
always @(posedge SCLKg4) begin
sht2nd <= #`db (RCS != RX_shift) && (RNS == RX_shift);
end
assign #`da ldBcnt = RNS[0] || RNS[2];
assign #`da Bcnteq0 = !(|Bcnt[4:0]);
always @(posedge SCLKg4)
TAG_SLOT <= #`db MWORD[14] && FSi_set;
always @(posedge SCLKg4 or posedge rst_SP_EN) begin
if (rst_SP_EN) Bcnt[4:0] <= #`db 5'b0;
else if (TAG_SLOT) Bcnt[4:0] <= #`db 5'hf;
else if (ldBcnt) Bcnt[4:0] <= #`db SLEN[4:0];
else Bcnt[4:0] <= #`db Bcnt[4:0] - 1;
end
assign #`da ldWcnt = RNS[0];
assign #`da Wcnt_dn = RNS[2];
assign #`da Wcnteq0 = !(|Wcnt[7:0]);
always @(posedge SCLKg4 or posedge rst_SP_EN) begin
if (rst_SP_EN) Wcnt[7:0] <= #`db 8'b0;
else if (ldWcnt) Wcnt[7:0] <= #`db MWORD[7:0];
else if (Wcnt_dn) Wcnt[7:0] <= #`db Wcnt[7:0] - 1;
end
wire ldLMcnt, LMcnteq0;
reg [4:0] LMcnt;
assign #`da ldLMcnt = RNS[0] || RNS[2];
assign #`da LMcnteq0 = !(|LMcnt[4:0]);
always @(posedge SCLKg4 or posedge rst_SP_EN) begin
if (rst_SP_EN) LMcnt[4:0] <= #`db 5'b0;
else if (ldLMcnt) LMcnt[4:0] <= #`db 5'h10;
else if (LMcnteq0) LMcnt[4:0] <= #`db 5'b0;
else LMcnt[4:0] <= #`db LMcnt[4:0] - 1;
end
wire [3:2] ST_SLOT1_EXT;
reg [3:2] SLOT1_EXT;
assign #`da ST_SLOT1_EXT[3] = (Wcnt == 'd11 && Bcnt == 'd3) ;
assign #`da ST_SLOT1_EXT[2] = (Wcnt == 'd11 && Bcnt == 'd2) ;
always @(posedge SCLKg4 or posedge RST ) begin
if (RST) SLOT1_EXT[3] <= #`db 1'b0;
else if (ST_SLOT1_EXT[3]) SLOT1_EXT[3] <= #`db RD;
else SLOT1_EXT[3] <= #`db SLOT1_EXT[3];
end
always @(posedge SCLKg4 or posedge RST ) begin
if (RST) SLOT1_EXT[2] <= #`db 1'b0;
else if (ST_SLOT1_EXT[2]) SLOT1_EXT[2] <= #`db RD;
else SLOT1_EXT[2] <= #`db SLOT1_EXT[2];
end
assign #`da ldRXSHT = !LMcnteq0 && (RFSsm || !RCS[0]);
assign #`da RXSHT_di[15:0] = sht2nd ? (zeroext ? {14'b0, RXSHT[0], RD}
: {{15{RXSHT[0]}}, RD})
: {RXSHT[14:0], RD};
always @(posedge SCLKg3_)
if (ldRXSHT) RXSHT[15:0] <= #`db RXSHT_di[15:0];
assign #`da rawRX_we = MTRX_E && EX_en && GO_Cx ||
ldRX_spt1;
assign #`da RX_we = rawRX_we;
assign #`da RX_di = ldRX_spt1 ? RXSHT[15:0] : DMD[15:0];
always @(posedge DSPCLK)
if (RX_we) RX[15:0] <= #`db RX_di;
always @(posedge SCLKg3_) ldRX_spt <= #`db RCS[1] && !RNS[1];
always @(posedge DSPCLK) begin
a_sync1 <= #`db ldRX_spt;
a_sync2 <= #`db a_sync1;
end
assign #`da ldRX_spt1 = a_sync1 && !a_sync2;
Delaya d1 (RSack, delRSack);
assign #`da sRSreq = SP_EN && RBUF && rawRX_we;
`ifdef FD_DFT
wire rRSreq_h = (RST || delRSack);
assign rRSreq = SCAN_TEST ? RST : rRSreq_h;
`else
assign #`da rRSreq = RST || delRSack;
`endif
always @(posedge DSPCLK or posedge rRSreq) begin
if (rRSreq) RSreq <= #`db 1'b0;
else if (sRSreq) RSreq <= #`db 1'b1;
end
always @(posedge DSPCLK)
ISRa <= #`db SP_EN && ldRX_spt1;
assign #`da ISR = RBUF ? Rwrap : ISRa;
endmodule
|
`include "../include/x_def.v"
module SCFG1 (/* in */ RST, DSPCLK, SP_EN, FSDIV, SCLKDIV,
ISCLK, FSD, FSW, ITFS, IRFS, INVTFS, INVRFS,
SLEN, INVxSCLK, AC97_MODE, MWORD_13,
`ifdef FD_DFT
SCAN_TEST,
`endif
SP_ENg, RFSsm, TFSsm, SCLKg3_, SCLKg4, SCLKg5,
SCLKg6, FSi_set,
SCLKo, T_SCLK, RFSi, T_RFS, TFSi, T_TFS);
input [15:0] FSDIV,
SCLKDIV;
input [4:0] SLEN;
input [1:0] FSD;
input RST,
DSPCLK,
SP_EN,
ISCLK,
FSW,
ITFS,
IRFS,
INVTFS,
INVRFS,
T_SCLK,
T_RFS,
T_TFS,
INVxSCLK;
input AC97_MODE;
input MWORD_13;
`ifdef FD_DFT
input SCAN_TEST;
`endif
output SCLKo,
RFSi,
TFSi,
SP_ENg,
SCLKg3_, SCLKg4,
SCLKg5, SCLKg6,
RFSsm,
TFSsm;
output FSi_set;
reg [15:0] SCLKi_cnt, FSi_cnt;
reg FSi, RFSg_d1, RFSg_d2, RFSg_d3, TFSg_d1,
TFSg_d2, TFSg_d3, FS_s1, FS_s2, SP_ENg;
reg SP_ENg_D1;
wire SCLKi_chg, FSi_set, FSi_clr, RFSgi, TFSgi,
RFSg, TFSg, FSfall, SCLKg, SCLKg1, SCLKg2;
wire FIRST_FS, T_SCLKi;
wire SCLKin;
reg SCLKi_enb;
always @(posedge DSPCLK) SCLKi_enb <= #`db !((SP_ENg || SP_EN) && ISCLK);
`ifdef FD_GTCLK
`ifdef FD_DFT
wire SCLKi_enb_dft;
GTECH_AND_NOT utm0 (.Z(SCLKi_enb_dft), .A(SCLKi_enb), .B(SCAN_TEST));
GtCLK_NOR2 uck0 (.Z(SCLKin_), .A(DSPCLK), .B(SCLKi_enb_dft));
GtCLK_NOT ckSCLKin (.Z(SCLKin), .A(SCLKin_));
`else
GtCLK_NOR2 uck0 (.Z(SCLKin_), .A(DSPCLK), .B(SCLKi_enb));
GtCLK_NOT ckSCLKin (.Z(SCLKin), .A(SCLKin_));
`endif
`else
assign #`d0 SCLKin = DSPCLK;
`endif
assign #`da SCLKi_chg = (SCLKi_cnt[15:0] == SCLKDIV[15:0]) || !SP_ENg;
always @(posedge SCLKin or posedge RST) begin
if (RST) SCLKi_cnt[15:0] <= #`db 16'b0;
else if (SCLKi_chg) SCLKi_cnt[15:0] <= #`db 16'b0;
else SCLKi_cnt[15:0] <= #`db SCLKi_cnt + 1;
end
reg SCLKi_h;
wire SCLKi;
always @(posedge SCLKin or posedge RST) begin
if (RST) SCLKi_h <= #`db 1'b0;
else if (SCLKi_chg) SCLKi_h <= #`db !SCLKi;
end
assign SCLKi = SCLKi_h;
assign #`da SCLKo = INVxSCLK ^ SCLKi;
`ifdef FD_DFT
assign #`da T_SCLKi = SCAN_TEST ? T_SCLK : INVxSCLK ^ T_SCLK;
`else
assign #`da T_SCLKi = INVxSCLK ^ T_SCLK;
`endif
`ifdef FD_FPGA
`ifdef FD_EVB
wire SCLKgi;
assign #`da SCLKgi = ISCLK ? SCLKi : T_SCLKi;
BUFG sclk1 (.I(SCLKgi), .O(SCLKg));
`else
assign #`da SCLKg = ISCLK ? SCLKi : T_SCLKi;
`endif
assign #`da SCLKg1 = SCLKg;
assign #`da SCLKg2 = SCLKg;
assign #`da SCLKg3_ = !SCLKg;
assign #`da SCLKg4 = SCLKg;
assign #`da SCLKg5 = SCLKg;
assign #`da SCLKg6 = SCLKg;
`else
`ifdef FD_DFT
wire ISCLK_dft;
assign ISCLK_dft = ISCLK && !SCAN_TEST;
GtCLK_MUX2 uu0 (.Z(SCLKg), .S(ISCLK_dft), .A(T_SCLKi), .B(SCLKi));
`else
GtCLK_MUX2 uu0 (.Z(SCLKg), .S(ISCLK), .A(T_SCLKi), .B(SCLKi));
`endif
GtCLK_NOT uu1 (.Z(SCLKga_), .A(SCLKg));
GtCLK_NOT uu2 (.Z(SCLKg3_), .A(SCLKg));
GtCLK_NOT uu3 (.Z(SCLKgc_), .A(SCLKg));
GtCLK_NOT uu4 (.Z(SCLKg1), .A(SCLKga_));
GtCLK_NOT uu5 (.Z(SCLKg2), .A(SCLKga_));
GtCLK_NOT uu6 (.Z(SCLKg4), .A(SCLKg3_));
GtCLK_NOT uu7 (.Z(SCLKg5), .A(SCLKgc_));
GtCLK_NOT uu8 (.Z(SCLKg6), .A(SCLKgc_));
`endif
assign #`da FSi_set = SP_ENg && SP_EN && ((FSi_cnt[15:0] == FSDIV[15:0])
|| !(IRFS || ITFS));
always @(posedge SCLKg1 or posedge RST) begin
if (RST) FSi_cnt[15:0] <= #`db 16'b0;
else if ( FIRST_FS) FSi_cnt[15:0] <= #`db FSDIV[15:0];
else if ( FSi_set) FSi_cnt[15:0] <= #`db 16'b0;
else if ( SP_ENg ) FSi_cnt[15:0] <= #`db FSi_cnt + 1;
else FSi_cnt[15:0] <= #`db FSi_cnt;
end
assign #`da FSi_clr = !FSW ||
(FSi_cnt[4:0] == SLEN[4:0]) ||
(AC97_MODE && FSi_cnt[4:0] == 'hf)
|| !SP_ENg;
always @(posedge SCLKg2 or posedge RST) begin
if (RST) FSi <= #`db 1'b0;
else if (FSi && FSi_clr) FSi <= #`db 1'b0;
else if (FSi_set) FSi <= #`db 1'b1;
end
wire AC97_RST;
assign #`da AC97_RST = AC97_MODE && MWORD_13;
assign #`da RFSi = FSi ^ INVRFS || AC97_RST;
assign #`da TFSi = FSi ^ INVTFS || AC97_RST;
assign #2 RFSgi = INVRFS ^ (IRFS ? RFSi : T_RFS);
assign #2 TFSgi = INVTFS ^ (ITFS ? TFSi : T_TFS);
assign #`da FSfall = !FS_s1 && FS_s2;
always @(posedge SCLKg2 or posedge RST) begin
if (RST) SP_ENg <= #`db 0;
else SP_ENg <= #`db SP_EN;
end
always @(posedge SCLKg2) begin
SP_ENg_D1 <= #`db SP_ENg;
end
reg RFSgi_d, TFSgi_d;
always @(posedge SCLKg2 or posedge RST) begin
if (RST) RFSgi_d <= 1'b0;
else RFSgi_d <= RFSgi;
end
always @(posedge SCLKg2 or posedge RST) begin
if (RST) TFSgi_d <= 1'b0;
else TFSgi_d <= TFSgi;
end
assign #`da RFSg = SP_ENg && RFSgi && !RFSgi_d;
assign #`da TFSg = SP_ENg && TFSgi && !TFSgi_d;
assign #`da FIRST_FS = !SP_ENg_D1 && SP_ENg;
always @(posedge SCLKg2 or posedge RST) begin
if (RST) begin
RFSg_d1 <= #`db 1'b0;
RFSg_d2 <= #`db 1'b0;
RFSg_d3 <= #`db 1'b0;
TFSg_d1 <= #`db 1'b0;
TFSg_d2 <= #`db 1'b0;
TFSg_d3 <= #`db 1'b0;
end
else begin
RFSg_d1 <= #`db RFSg;
RFSg_d2 <= #`db RFSg_d1;
RFSg_d3 <= #`db RFSg_d2;
TFSg_d1 <= #`db TFSg;
TFSg_d2 <= #`db TFSg_d1;
TFSg_d3 <= #`db TFSg_d2;
end
end
assign #`da RFSsm = (FSD[1:0] == 2'b00) ? RFSg :
(FSD[1:0] == 2'b01) ? RFSg_d1 :
(FSD[1:0] == 2'b10) ? RFSg_d2 : RFSg_d3;
assign #`da TFSsm = (FSD[1:0] == 2'b00) ? TFSg :
(FSD[1:0] == 2'b01) ? TFSg_d1 :
(FSD[1:0] == 2'b10) ? TFSg_d2 : TFSg_d3;
endmodule
|
`include "../include/x_def.v"
module SCreg1 (/* in */ RST, DSPCLK, selAUTO, selFSDIV, selSCLKDIV,
selSCTL, selMWORD, AUTO_we, FSDIV_we, SCLKDIV_we,
SCTL_we, MWORD_we, DMD, MMR_web,
SLOT1_EXT, SLOT_NUM,
`ifdef FD_DFT
SCAN_TEST,
`endif
TIREG, TMREG, RIREG, RMREG,
TBUF, RBUF, FSDIV, SCLKDIV, LOOP,
ISCLK, FSD, FSW, ITFS, IRFS, INVTFS, INVRFS,
DTYPE, SLEN, MWORD, DMD_do,
SLEN_ex, INVxSCLK);
input [15:0] DMD;
input RST,
DSPCLK,
selAUTO,
selFSDIV,
selSCLKDIV,
selSCTL,
selMWORD,
AUTO_we,
FSDIV_we,
SCLKDIV_we,
SCTL_we,
MWORD_we,
MMR_web;
input [3:0] SLOT_NUM;
input [3:2] SLOT1_EXT;
`ifdef FD_DFT
input SCAN_TEST;
`endif
output [2:0] TIREG,
RIREG;
output [1:0] TMREG,
RMREG;
output [15:0] FSDIV,
SCLKDIV,
DMD_do;
output [1:0] FSD,
DTYPE;
output [4:0] SLEN;
output [15:0] MWORD;
output TBUF,
RBUF,
LOOP,
ISCLK,
FSW,
SLEN_ex,
INVxSCLK,
ITFS,
IRFS,
INVTFS,
INVRFS;
wire [11:0] DMD_MW;
wire [15:0] DMD_SCTL, DMD_FSDIV;
wire [15:0] MWORD;
wire [15:0] FSDIV, SCLKDIV, SCTL;
wire [11:0] AUTO_b;
wire [11:0] MW_OUT;
reg [15:12] AUTO_a;
wire [15:0] AUTO;
wire SPbas_R, SPidx_R;
wire SLEN_ex, INVxSCLK;
wire AC97_PSET, FSDIV_we_PSET, SCTL_we_PSET, MWORD_we_PSET;
wire [15:0] AC97_FSDIV = `AC97_FSDIV;
wire [15:0] AC97_SCTL = `AC97_SCTL;
wire [11:0] AC97_MWORD = `AC97_MWORD;
assign #`da AC97_PSET = MWORD_we && DMD[14];
assign #`da FSDIV_we_PSET = FSDIV_we || AC97_PSET;
assign #`da SCTL_we_PSET = SCTL_we || AC97_PSET;
assign #`da MWORD_we_PSET = MWORD_we || AC97_PSET;
wire [15:0] MWORD_RD;
wire AC97_MODE = MWORD[14];
assign #`da MWORD_RD[15:0] = !AC97_MODE ? {MWORD[15:13], 5'b0, MWORD[7:0]} :
{MWORD[15:14], SLOT1_EXT[3:2], SLOT_NUM[3:0], MWORD[7:0]};
assign #`da DMD_do[15:0] = {16{selAUTO}} & {4'b0, AUTO[11:0]} |
{16{selFSDIV}} & FSDIV[15:0] |
{16{selSCLKDIV}} & SCLKDIV[15:0] |
{16{selSCTL}} & SCTL[15:0] |
{16{selMWORD}} & MWORD_RD[15:0];
`ifdef FD_DFT
REG12LC AUTOreg (DSPCLK, MMR_web, AUTO_we, DMD[11:0], AUTO[11:0], RST, SCAN_TEST);
`else
REG12LC AUTOreg (DSPCLK, MMR_web, AUTO_we, DMD[11:0], AUTO[11:0], RST);
`endif
assign #`d0 {TIREG[2:0], TMREG[1:0], RIREG[2:0],
RMREG[1:0], TBUF, RBUF} = AUTO[11:0];
assign #`d0 DMD_FSDIV[15:0] = AC97_PSET ? AC97_FSDIV : DMD[15:0];
`ifdef FD_DFT
REG16LC FSDIVreg (DSPCLK, MMR_web, FSDIV_we_PSET, DMD_FSDIV[15:0], FSDIV[15:0], RST, SCAN_TEST);
`else
REG16LC FSDIVreg (DSPCLK, MMR_web, FSDIV_we_PSET, DMD_FSDIV[15:0], FSDIV[15:0], RST);
`endif
`ifdef FD_DFT
REG16LC SCLKDIVreg (DSPCLK, MMR_web, SCLKDIV_we, DMD[15:0],
SCLKDIV[15:0], RST, SCAN_TEST);
`else
REG16LC SCLKDIVreg (DSPCLK, MMR_web, SCLKDIV_we, DMD[15:0],
SCLKDIV[15:0], RST);
`endif
assign #`d0 DMD_SCTL[15:0] = AC97_PSET ? AC97_SCTL : DMD[15:0];
`ifdef FD_DFT
SREG16MC SCTLreg (DSPCLK, MMR_web, SCTL_we_PSET, DMD_SCTL[15:0], SCTL[15:0], RST, SCAN_TEST);
`else
SREG16MC SCTLreg (DSPCLK, MMR_web, SCTL_we_PSET, DMD_SCTL[15:0], SCTL[15:0], RST);
`endif
assign #`d0 LOOP = SCTL[15];
assign #`d0 ISCLK = SCTL[14];
assign #`d0 INVxSCLK = SCTL[13];
assign #`d0 FSD[1:0] = SCTL[12:11];
assign #`d0 FSW = SCTL[10];
assign #`d0 ITFS = SCTL[9];
assign #`d0 IRFS = SCTL[8];
assign #`d0 INVTFS = SCTL[7];
assign #`d0 INVRFS = SCTL[6];
assign #`d0 DTYPE[1:0] = SCTL[5:4];
assign #`d0 SLEN_ex = MWORD[15];
assign #`d0 SLEN[4:0] = {SLEN_ex, SCTL[3:0]};
assign #`d0 DMD_MW[10:0] = AC97_PSET ? AC97_MWORD | {2'b0,DMD[13],8'b0} :
{DMD[15:13], DMD[7:0]};
assign #`d0 MWORD[15:0] = {MW_OUT[10:8], 5'b0, MW_OUT[7:0]};
`ifdef FD_DFT
REG11LC MWORDreg (DSPCLK, MMR_web, MWORD_we_PSET, DMD_MW[10:0], MW_OUT[10:0], RST, SCAN_TEST);
`else
REG11LC MWORDreg (DSPCLK, MMR_web, MWORD_we_PSET, DMD_MW[10:0], MW_OUT[10:0], RST);
`endif
endmodule
|
`include "../include/x_def.v"
module SPORT1 (/* -------- Inputs : --------- */
RDx,
T_RST, DSPCLK, GO_Cx, EX_en, MTTX_E,
MTRX_E, Twrap, Rwrap, DMD,
SP_EN, selAUTO, selFSDIV, selSCLKDIV,
selSCTL, selMWORD, AUTO_we, FSDIV_we,
SCLKDIV_we, SCTL_we, MWORD_we, MMR_web,
TSack, RSack,
`ifdef FD_DFT
SCAN_TEST,
`endif
TDx,
ISR, IST, TIREG, TMREG,
RIREG, RMREG,
TSreq, RSreq, RX, TX,
DMD_do,
SCLKo, T_SCLK, ISCLK,
RFSi, T_RFS, IRFS,
TFSi, T_TFS, ITFS);
input [15:0] DMD;
input RDx,
T_RST,
DSPCLK,
GO_Cx,
EX_en,
SP_EN,
selAUTO,
selFSDIV,
selSCLKDIV,
selSCTL,
selMWORD,
AUTO_we,
FSDIV_we,
SCLKDIV_we,
SCTL_we,
MWORD_we,
MTTX_E,
MTRX_E,
Twrap,
Rwrap,
TSack,
RSack,
T_SCLK,
T_RFS,
T_TFS,
MMR_web;
`ifdef FD_DFT
input SCAN_TEST;
`endif
output [15:0] RX, TX,
DMD_do;
output [2:0] TIREG,
RIREG;
output [1:0] TMREG,
RMREG;
output TDx,
ISR,
IST,
TSreq,
RSreq,
ISCLK,
SCLKo,
IRFS,
RFSi,
ITFS,
TFSi;
wire [15:0] FSDIV, SCLKDIV, DMDin;
wire [15:0] MWORD;
wire [4:0] SLEN;
wire [1:0] FSD, DTYPE;
wire [3:2] SLOT1_EXT;
wire [3:0] SLOT_NUM;
SPGLUE1 glue (/* in */ T_RST, DSPCLK, LOOP, TD, RDx,
`ifdef FD_DFT
SCAN_TEST,
`endif
RST, RD, TDx);
SCreg1 regs (/* in */ RST, DSPCLK, selAUTO, selFSDIV, selSCLKDIV,
selSCTL, selMWORD, AUTO_we, FSDIV_we, SCLKDIV_we,
SCTL_we, MWORD_we, DMDin[15:0], MMR_web,
SLOT1_EXT[3:2], SLOT_NUM[3:0],
`ifdef FD_DFT
SCAN_TEST,
`endif
TIREG[2:0], TMREG[1:0], RIREG[2:0], RMREG[1:0],
TBUF, RBUF, FSDIV[15:0], SCLKDIV[15:0], LOOP,
ISCLK, FSD[1:0], FSW, ITFS, IRFS, INVTFS, INVRFS,
DTYPE[1:0], SLEN[4:0], MWORD[15:0], DMD_do[15:0],
SLEN_ex, INVxSCLK);
SCFG1 cfg (/* in */ RST, DSPCLK, SP_EN, FSDIV[15:0], SCLKDIV[15:0],
ISCLK, FSD[1:0], FSW, ITFS, IRFS, INVTFS, INVRFS,
SLEN[4:0], INVxSCLK, MWORD[14], MWORD[13],
`ifdef FD_DFT
SCAN_TEST,
`endif
SP_ENg, RFSsm, TFSsm, SCLKg3_, SCLKg4, SCLKg5,
SCLKg6, FSi_set,
SCLKo, T_SCLK, RFSi, T_RFS, TFSi, T_TFS);
TXctl1 txctl (/* in */ RST, DSPCLK, GO_Cx, EX_en, SCLKg5, SCLKg6,
SP_EN ,SP_ENg, TFSsm, TSack, Twrap, SLEN[4:0],
MWORD[15:0], TBUF, SLEN_ex, FSi_set,
/*logTX[7:0],*/ MTTX_E, DMDin[15:0],
`ifdef FD_DFT
SCAN_TEST,
`endif
TD, TSreq, IST, TX[15:0], SLOT_NUM[3:0]);
RXctl1 rxctl (/* in */ RST, DSPCLK, GO_Cx, EX_en, SCLKg3_, SCLKg4,
SP_ENg, RFSsm, RD, RSack, Rwrap, SLEN[4:0],
MWORD[15:0], RBUF, FSi_set,
/*expRX[15:0],*/ MTRX_E, DTYPE[1:0], DMDin[15:0],
`ifdef FD_DFT
SCAN_TEST,
`endif
RSreq, ISR, RX[15:0], SLOT1_EXT[3:2]);
`ifdef FD_synthesis
GTECH_BUF uu0 (.Z(DMDin[0]), .A(DMD[0]));
GTECH_BUF uu1 (.Z(DMDin[1]), .A(DMD[1]));
GTECH_BUF uu2 (.Z(DMDin[2]), .A(DMD[2]));
GTECH_BUF uu3 (.Z(DMDin[3]), .A(DMD[3]));
GTECH_BUF uu4 (.Z(DMDin[4]), .A(DMD[4]));
GTECH_BUF uu5 (.Z(DMDin[5]), .A(DMD[5]));
GTECH_BUF uu6 (.Z(DMDin[6]), .A(DMD[6]));
GTECH_BUF uu7 (.Z(DMDin[7]), .A(DMD[7]));
GTECH_BUF uu8 (.Z(DMDin[8]), .A(DMD[8]));
GTECH_BUF uu9 (.Z(DMDin[9]), .A(DMD[9]));
GTECH_BUF uu10 (.Z(DMDin[10]), .A(DMD[10]));
GTECH_BUF uu11 (.Z(DMDin[11]), .A(DMD[11]));
GTECH_BUF uu12 (.Z(DMDin[12]), .A(DMD[12]));
GTECH_BUF uu13 (.Z(DMDin[13]), .A(DMD[13]));
GTECH_BUF uu14 (.Z(DMDin[14]), .A(DMD[14]));
GTECH_BUF uu15 (.Z(DMDin[15]), .A(DMD[15]));
`else
assign DMDin[15:0] = DMD[15:0];
`endif
endmodule
module SPGLUE1 (/* in */ T_RST, DSPCLK, LOOP, TD, RDx,
`ifdef FD_DFT
SCAN_TEST,
`endif
RST, RD, TDx);
`ifdef FD_DFT
input SCAN_TEST;
`endif
input T_RST, DSPCLK, LOOP, TD, RDx;
output RST, RD, TDx;
`ifdef FD_DFT
reg RST_h;
wire RST;
always @(posedge DSPCLK) RST_h <= #`db T_RST;
assign RST = SCAN_TEST ? T_RST : RST_h;
`else
reg RST;
always @(posedge DSPCLK) RST <= #`db T_RST;
`endif
assign #`da RD = LOOP ? TD : RDx;
assign #`da TDx = LOOP ? 1'b0 : TD;
endmodule
|
`include "../include/x_def.v"
module TXctl1 (/* in */ RST, DSPCLK, GO_Cx, EX_en, SCLKg5, SCLKg6,
SP_EN, SP_ENg, TFSsm, TSack, Twrap, SLEN,
MWORD, TBUF, SLEN_ex, FSi_set,
/*logTX[7:0],*/ MTTX_E, DMD,
`ifdef FD_DFT
SCAN_TEST,
`endif
TD, TSreq, IST, TX, SLOT_NUM);
`ifdef FD_DFT
input SCAN_TEST;
`endif
input [4:0] SLEN;
input [15:0] MWORD;
input [15:0] DMD;
input RST,
DSPCLK,
GO_Cx,
EX_en,
SCLKg5, SCLKg6,
SP_EN,
SP_ENg,
SLEN_ex,
TFSsm,
TSack,
Twrap,
TBUF,
MTTX_E;
input FSi_set;
output [15:0] TX;
output TD,
TSreq,
IST;
output [3:0] SLOT_NUM;
reg [15:0] TX,
TXSHT;
reg [2:0] TCS, TNS;
reg [4:0] Bcnt;
reg [7:0] Wcnt;
reg b_sync1, c_sync1, c_sync2, ldTX_cmp, TSreqi,
TSreq, ISTai;
reg TAG_SLOT;
wire [15:0] TX_di, TXSHT_di;
wire ldBcnt, ldWcnt, Bcnteq0, Wcnteq0, Wcnt_dn;
wire rawTX_we, TX_we, ISTa, sTSreq, rTSreq;
parameter TX_idle = 3'b001,
TX_shift = 3'b010,
TX_wstart = 3'b100;
always @(TCS or TFSsm or Bcnteq0 or Wcnteq0)
begin
case (TCS)
TX_idle : TNS <= #`da TFSsm ? TX_shift : TX_idle;
TX_shift : begin
if (Bcnteq0)
TNS <= #`da Wcnteq0 ? TX_idle : TX_wstart;
else
TNS <= #`da TX_shift;
end
TX_wstart : TNS <= #`da TX_shift;
default : TNS <= #`da TX_idle;
endcase
end
`ifdef FD_DFT
wire rst_SP_ENg_h = !SP_ENg && !SCAN_TEST;
wire rst_SP_ENg = SCAN_TEST ? RST : rst_SP_ENg_h;
`else
wire rst_SP_ENg = !SP_ENg;
`endif
always @(posedge SCLKg5 or posedge rst_SP_ENg) begin
if (rst_SP_ENg) TCS <= #`db 3'b001;
else TCS <= #`db TNS;
end
assign #`da ldBcnt = TNS[0] || TNS[2];
assign #`da Bcnteq0 = !(|Bcnt[4:0]);
always @(posedge SCLKg5)
TAG_SLOT <= #`db MWORD[14] && FSi_set;
always @(posedge SCLKg5 or posedge rst_SP_ENg) begin
if (rst_SP_ENg) Bcnt[4:0] <= #`db 5'b0;
else if (TAG_SLOT) Bcnt[4:0] <= #`db 5'hf;
else if (ldBcnt) Bcnt[4:0] <= #`db SLEN[4:0];
else Bcnt[4:0] <= #`db Bcnt[4:0] - 1;
end
assign #`da ldWcnt = TNS[0];
assign #`da Wcnt_dn = TNS[2];
assign #`da Wcnteq0 = !(|Wcnt[7:0]);
assign #`da SLOT_NUM[3:0] = Wcnt[3:0];
always @(posedge SCLKg5 or posedge rst_SP_ENg) begin
if (rst_SP_ENg) Wcnt[7:0] <= #`db 8'b0;
else if (ldWcnt) Wcnt[7:0] <= #`db MWORD[7:0];
else if (Wcnt_dn) Wcnt[7:0] <= #`db Wcnt[7:0] - 1;
end
assign #`da TXSHT_di[15:0] = TNS[1] ? {TXSHT[14:0], 1'b0}
: TX[15:0];
always @(posedge SCLKg6) TXSHT[15:0] <= #`db TXSHT_di[15:0];
wire [3:0] slen_msb = SLEN[3:0];
assign #`d0 TD = SLEN_ex ? TXSHT[15] : TXSHT[slen_msb];
assign #`da rawTX_we = MTTX_E && EX_en && GO_Cx ||
TSack;
assign #`da TX_we = rawTX_we;
assign #`da TX_di = DMD[15:0];
always @(posedge DSPCLK) if (TX_we) TX[15:0] <= #`db TX_di;
Delaya d1 (TSack, delTSack);
reg SP_EN_D1;
wire SP_EN_1T;
always @(posedge DSPCLK) SP_EN_D1 <= #`db SP_EN;
assign #`da SP_EN_1T = SP_EN && !SP_EN_D1;
`ifdef FD_DFT
wire rTSreq_h = (RST || delTSack);
assign rTSreq = SCAN_TEST ? RST : rTSreq_h;
`else
assign #`da rTSreq = RST || delTSack;
`endif
assign #`da sTSreq = SP_ENg && TBUF && !TCS[1] && TNS[1];
always @(posedge SCLKg5 or posedge rTSreq) begin
if (rTSreq) TSreqi <= #`db 1'b0;
else if (sTSreq) TSreqi <= #`db 1'b1;
end
always @(posedge DSPCLK or posedge rTSreq) begin
if (rTSreq) TSreq <= #`db 1'b0;
else TSreq <= #`db TSreqi || SP_EN_1T && MWORD[14];
end
always @(posedge SCLKg5 or posedge RST)
if (RST) ISTai <= #`db 1'b0;
else ISTai <= #`db SP_ENg && (!TCS[1] && TNS[1]);
always @(posedge DSPCLK) begin
c_sync1 <= #`db ISTai;
c_sync2 <= #`db c_sync1;
end
assign #`da ISTa = c_sync1 && !c_sync2;
assign #`da IST = TBUF ? Twrap : ISTa;
endmodule
|
/*----------------------------------------------------------------------*/
/*----------------------------------------------------------------------*/
/*--------------------------------------------------------------*/
/*--------------------------------------------------------------*/
/*--------------------------------------------------------------*/
/*--------------------------------------------------------------*/
module TM(/*----------- Input from I/O pads ---------------*/
TMCLK, DSPCLK, T_RST, TMODE, DMD,
selTSR, selTCR, selTPR, TSR_we, TCR_we,
TPR_we, MSTAT5, TMOUT, MMR_web,
ICE_ST,
`ifdef FD_DFT
SCAN_TEST,
`endif
TINT);
/*--------------------------------------------------------*/
input [15:0] DMD;
input TMCLK;
input DSPCLK;
input T_RST;
input selTSR;
input selTCR;
input selTPR;
input MSTAT5;
input TSR_we;
input TCR_we;
input TPR_we;
input TMODE;
input MMR_web;
input ICE_ST;
`ifdef FD_DFT
input SCAN_TEST;
`endif
output [15:0] TMOUT;
output TINT;
/*---------------------------------------------------------*/
reg WR_TSR_p, WR_TCR_p;
always @(posedge DSPCLK)
begin
WR_TSR_p <= #1 TSR_we;
WR_TCR_p <= #1 TCR_we;
end
/*-------------------------------------------------------*/
wire [7:0] TSR;
wire CLKsel;
wire [15:0] TCR;
wire [15:0] TPR;
`ifdef FD_DFT
REG9LC tsr_reg(DSPCLK, MMR_web, TSR_we, {DMD[15], DMD[7:0]}, {CLKsel, TSR[7:0]},
T_RST, SCAN_TEST);
REG16LC tcr_reg(DSPCLK, MMR_web, TCR_we, DMD[15:0], TCR[15:0], T_RST, SCAN_TEST);
REG16LC tpr_reg(DSPCLK, MMR_web, TPR_we, DMD[15:0], TPR[15:0], T_RST, SCAN_TEST);
`else
REG9LC tsr_reg(DSPCLK, MMR_web, TSR_we, {DMD[15], DMD[7:0]}, {CLKsel, TSR[7:0]}, T_RST);
REG16LC tcr_reg(DSPCLK, MMR_web, TCR_we, DMD[15:0], TCR[15:0], T_RST);
REG16LC tpr_reg(DSPCLK, MMR_web, TPR_we, DMD[15:0], TPR[15:0], T_RST);
`endif
wire WR_TCR_TMP, WR_TSR_TMP;
`ifdef FD_GTCLK
`ifdef FD_DFT
GTECH_AND_NOT uu0 (.Z(CLKsel_dft), .A(CLKsel), .B(SCAN_TEST));
GtCLK_MUX2 uk2 (.Z(TIMERCLK), .A(DSPCLK), .B(TMCLK), .S(CLKsel_dft));
`else
GtCLK_MUX2 uk2 (.Z(TIMERCLK), .A(DSPCLK), .B(TMCLK), .S(CLKsel));
`endif
`ifdef FD_DFT
GTECH_NOR3 uk3 (.Z(TIMERCLKenb), .A(MSTAT5), .B(WR_TCR_TMP), .C(WR_TSR_TMP));
GTECH_AND_NOT utm1 (.Z(TIMERCLKenb_dft), .A(TIMERCLKenb), .B(SCAN_TEST));
GtCLK_NOR2 uk4 (.Z(TIMERCLKg_), .A(TIMERCLK), .B(TIMERCLKenb_dft));
`else
GTECH_NOR3 uk3 (.Z(TIMERCLKenb), .A(MSTAT5), .B(WR_TCR_TMP), .C(WR_TSR_TMP));
GtCLK_NOR2 uk4 (.Z(TIMERCLKg_), .A(TIMERCLK), .B(TIMERCLKenb));
`endif
GtCLK_NOT ckTIMERCLKg (.Z(TIMERCLKg), .A(TIMERCLKg_));
`else
wire TIMERCLK = CLKsel ? TMCLK : DSPCLK;
wire TIMERCLKg=TIMERCLK;
`endif
/*----------------------------------------------------------*/
reg WR_TSR_TMP_GEN1;
reg WR_TSR_TMP_GEN2;
reg WR_TSR_KEEP_TO_TMCLK_p;
wire WR_TSR_RST;
always @(posedge TIMERCLK)
WR_TSR_TMP_GEN1 <= #1 WR_TSR_KEEP_TO_TMCLK_p;
always @(posedge TIMERCLK)
WR_TSR_TMP_GEN2 <= #1 WR_TSR_TMP_GEN1;
assign WR_TSR_TMP = TMODE ? 1'b0 : WR_TSR_TMP_GEN1 & ~WR_TSR_TMP_GEN2;
`ifdef FD_DFT
wire WR_TSR_RST_h = (T_RST | WR_TSR_TMP);
assign WR_TSR_RST = SCAN_TEST ? T_RST : WR_TSR_RST_h;
`else
assign WR_TSR_RST = T_RST | WR_TSR_TMP;
`endif
always @(posedge DSPCLK or posedge WR_TSR_RST)
begin
if (WR_TSR_RST)
WR_TSR_KEEP_TO_TMCLK_p <= #1 1'b0;
else if (WR_TSR_p)
WR_TSR_KEEP_TO_TMCLK_p <= #1 1'b1;
end
/*------------------------------------------------------------*/
wire TSREQ0, RELOAD_TSR;
reg [7:0] TSR_TMP;
assign TSREQ0 = (TSR_TMP[7:0] == 8'h0);
assign RELOAD_TSR = TMODE ? 1'b0
: MSTAT5 ? TSREQ0 : 1'b1;
wire [3:0] TSR_SUM0, TSR_SUM1;
wire [7:0] TSR_TMPin;
wire SCo0, SCi0;
assign {SCo0, TSR_SUM0[3:0]} = TSR_TMP[3:0] + 4'b1111;
assign SCi0 = TMODE ? 1'b0 : SCo0;
assign TSR_SUM1[3:0] = TSR_TMP[7:4] + SCi0 + 4'b1111;
assign TSR_TMPin[7:0] = {TSR_SUM1[3:0], TSR_SUM0[3:0]};
always @(posedge TIMERCLKg or posedge T_RST)
begin
if (T_RST)
TSR_TMP[7:0] <= #1 8'h0;
else if (WR_TSR_TMP)
TSR_TMP[7:0] <= #1 TSR[7:0];
else if (RELOAD_TSR)
TSR_TMP[7:0] <= #1 TSR[7:0];
else if(!ICE_ST)
TSR_TMP[7:0] <= #1 TSR_TMPin[7:0];
end
/*-------------------------------------------------------------*/
wire TCREQ0, RELOAD_TCR;
wire RELOAD_TCR_TMP;
wire TINT_SET;
reg TINT_SET_L;
reg TINT_GEN1;
reg TINT_GEN2;
reg MSTAT5_syn;
reg [15:0] TCR_TMP;
assign TCREQ0 = (TCR_TMP[15:0] == 16'h0);
assign RELOAD_TCR = TMODE ? 1'b0
: MSTAT5 ? TCREQ0 : 1'b0;
assign RELOAD_TCR_TMP = TMODE ? 1'b0
: MSTAT5 ? ~TSREQ0 : 1'b1;
assign TINT_SET = MSTAT5_syn & ~(WR_TCR_TMP | WR_TSR_TMP) & TCREQ0;
always @(posedge TIMERCLKg or posedge T_RST)
begin
if (T_RST)
MSTAT5_syn <=#1 1'b0;
else
MSTAT5_syn <=#1 MSTAT5;
end
always @(posedge TIMERCLKg or posedge T_RST)
begin
if (T_RST)
TINT_SET_L <= #1 1'b0;
else if (TINT_SET)
TINT_SET_L <= #1 1'b1;
else
TINT_SET_L <= #1 1'b0;
end
always @(posedge DSPCLK or posedge T_RST)
begin
if (T_RST)
TINT_GEN1 <= #1 1'b0;
else
TINT_GEN1 <= #1 TINT_SET_L;
end
always @(posedge DSPCLK or posedge T_RST)
begin
if (T_RST)
TINT_GEN2 <= #1 1'b0;
else
TINT_GEN2 <= #1 TINT_GEN1;
end
assign TINT = TMODE ? 1'b0 : TINT_GEN2 & ~TINT_GEN1;
/*---------------------------------------------------------------*/
reg WR_TCR_TMP_GEN1;
reg WR_TCR_TMP_GEN2;
reg WR_TCR_KEEP_TO_TMCLK_p;
wire WR_TCR_RST;
always @(posedge TIMERCLK)
WR_TCR_TMP_GEN1 <= #1 WR_TCR_KEEP_TO_TMCLK_p;
always @(posedge TIMERCLK)
WR_TCR_TMP_GEN2 <= #1 WR_TCR_TMP_GEN1;
assign WR_TCR_TMP = TMODE ? 1'b0 : WR_TCR_TMP_GEN1 & ~WR_TCR_TMP_GEN2;
`ifdef FD_DFT
wire WR_TCR_RST_h = T_RST | WR_TCR_TMP;
assign WR_TCR_RST = SCAN_TEST ? T_RST : WR_TCR_RST_h;
`else
assign WR_TCR_RST = T_RST | WR_TCR_TMP;
`endif
always @(posedge DSPCLK or posedge WR_TCR_RST)
begin
if (WR_TCR_RST)
WR_TCR_KEEP_TO_TMCLK_p <= #1 1'b0;
else if (WR_TCR_p)
WR_TCR_KEEP_TO_TMCLK_p <= #1 1'b1;
end
/*---------------------------------------------------------------*/
wire [3:0] TCR_SUM0, TCR_SUM1;
wire [3:0] TCR_SUM2, TCR_SUM3;
wire [15:0] TCR_TMPin;
wire RCo0, RCo1, RCo2;
wire RCi0, RCi1, RCi2;
assign {RCo0, TCR_SUM0[3:0]} = TCR_TMP[3:0] + 4'b1111 ;
assign RCi0 = TMODE ? 1'b0 : RCo0;
assign {RCo1, TCR_SUM1[3:0]} = TCR_TMP[7:4] + RCi0 + 4'b1111;
assign RCi1 = TMODE ? 1'b0 : RCo1;
assign {RCo2, TCR_SUM2[3:0]} = TCR_TMP[11:8] + RCi1 + 4'b1111;
assign RCi2 = TMODE ? 1'b0 : RCo2;
assign TCR_SUM3[3:0] = TCR_TMP[15:12] + RCi2 + 4'b1111;
assign TCR_TMPin[15:0] = {TCR_SUM3[3:0], TCR_SUM2[3:0], TCR_SUM1[3:0], TCR_SUM0[3:0]};
always @(posedge TIMERCLKg or posedge T_RST)
begin
if (T_RST)
TCR_TMP[15:0] <= #1 16'b0;
else if (WR_TCR_TMP)
TCR_TMP[15:0] <= #1 TCR[15:0];
else if (RELOAD_TCR)
TCR_TMP[15:0] <= #1 TPR[15:0];
else if (RELOAD_TCR_TMP)
TCR_TMP[15:0] <= #1 TCR_TMP[15:0];
else if(!ICE_ST)
TCR_TMP[15:0] <= #1 TCR_TMPin[15:0];
end
/*--------------------------------------------------------------*/
wire [15:0] TCR_OUT;
assign TCR_OUT[15:0] = TCR_TMP[15:0];
assign TMOUT[15:0] = {16{selTSR}} & {CLKsel, 7'b0, {TSR[7:0]}}
| {16{selTCR}} & TCR_OUT[15:0]
| {16{selTPR}} & TPR[15:0];
endmodule
|
`include "../include/x_def.v"
module CLKC (/* -------- Inputs : --------- */
P_RSTn, HRST, OSCin, X_PWDn, TMODE,
DMD,
IDLE_ST_h, IDLE_ST, IRE, GOICE,
ICE_wakeup, TRAP_R, TRAP_R_L,
CKR_we, MMR_web, TB_EN,
XTALDIS, XTALDELAY, PUCR,
`ifdef FD_DFT
SCAN_TEST,
`endif
RSTtext_h,
`ifdef FD_EVB
CORECLK, PERICLK,
`else
DSPCLK,
`endif
DSPCLK_cm0, DSPCLK_cm1, DSPCLK_cm2,
DSPCLK_pm0, DSPCLK_pm1, DSPCLK_pm2,
DSPCLK_dm0, DSPCLK_dm1, DSPCLK_dm2,
PWDACK, CLKO,
Awake_h, Awake, enTRAP_RL, STBY, PWRDn,
XTALoffn,
CKR);
input [3:0] IRE;
input [15:0] DMD;
input P_RSTn,
HRST,
OSCin,
X_PWDn,
TMODE,
IDLE_ST_h,
IDLE_ST,
CKR_we,
MMR_web,
TB_EN,
GOICE,
TRAP_R,
TRAP_R_L,
XTALDIS,
XTALDELAY,
PUCR,
ICE_wakeup;
`ifdef FD_DFT
input SCAN_TEST;
`endif
output [15:0] CKR;
output RSTtext_h,
DSPCLK_cm0,
DSPCLK_cm1,
DSPCLK_cm2,
DSPCLK_pm0,
DSPCLK_pm1,
DSPCLK_pm2,
DSPCLK_dm0,
DSPCLK_dm1,
DSPCLK_dm2,
PWDACK,
PWRDn,
STBY,
CLKO,
XTALoffn,
Awake_h, Awake,
enTRAP_RL;
`ifdef FD_EVB
output CORECLK, PERICLK;
`else
output DSPCLK;
`endif
wire [15:0] CKR;
wire [11:0] OSCNTR;
reg [10:0] STDcnt;
reg [4:0] PSEL;
reg [6:0] OUTcnt;
reg CLKOUT, SIDLE_s1, SIDLE_s2,
SlowDn, SlowDn_s1, SlowDn_s2, STBY,
SLEEP, DSPoff, OSCoff_set, OSCoff,
Cnt128, Cnt4096, Cnt4096_s1, Cnt4096_s2,
PWDACK, RSTtext, Awake;
wire [6:0] Num128;
wire [11:0] Num4096;
wire STDchg, OUTchg, SlowDn_ini, stSlowDn,
STBY_set, PWDrise, SLEEP_set, SLEEP_clr,
OSCNTR_ena, OSCNTR_clr, Cnt128_set,
Cnt4096_set, PRST, ONCLK, DSPCLKi,
SRST, crSlowDn,
selSTDCLK, OSC, STDCLKi;
`ifdef FD_DFT
assign #`da PWRDn = !(SlowDn || SLEEP) && TB_EN && !SCAN_TEST;
`else
assign #`da PWRDn = !(SlowDn || SLEEP) && TB_EN;
`endif
assign #`da XTALoffn = !OSCoff || PRST;
assign #`da selSTDCLK = SlowDn && !PRST;
`ifdef FD_FPGA
reg STDCLK;
assign OSC = !OSCin;
assign ONCLK = OSC;
assign #`da DSPCLKi = selSTDCLK ? STDCLK : ONCLK;
assign #`da DSPCLK = DSPCLKi || DSPoff && !PRST;
`ifdef FD_EVB
BUFG clkcm0 (.O(DSPCLK_cm0), .I(DSPCLK));
BUFG clkcm1 (.O(DSPCLK_cm1), .I(DSPCLK));
BUFG clkcm2 (.O(DSPCLK_cm2), .I(DSPCLK));
BUFG clkpm0 (.O(DSPCLK_pm0), .I(DSPCLK));
BUFG clkpm1 (.O(DSPCLK_pm1), .I(DSPCLK));
assign DSPCLK_pm2 = DSPCLK_pm1;
BUFG clkdm0 (.O(DSPCLK_dm0), .I(DSPCLK));
BUFG clkdm1 (.O(DSPCLK_dm1), .I(DSPCLK));
assign DSPCLK_dm2 = DSPCLK_dm1;
BUFG coreclk (.O(CORECLK), .I(DSPCLK));
BUFG periclk (.O(PERICLK), .I(DSPCLK));
`else
assign DSPCLK_cm0 = DSPCLK;
assign DSPCLK_cm1 = DSPCLK;
assign DSPCLK_cm2 = DSPCLK;
assign DSPCLK_dm0 = DSPCLK;
assign DSPCLK_dm1 = DSPCLK;
assign DSPCLK_dm2 = DSPCLK;
assign DSPCLK_pm0 = DSPCLK;
assign DSPCLK_pm1 = DSPCLK;
assign DSPCLK_pm2 = DSPCLK;
`endif
`else
GtCLK_NOT ckOSC (.Z(OSC), .A(OSCin));
GtCLK_BUF ckONCLK (.Z(ONCLK), .A(OSC));
`ifdef FD_DFT
wire selSTDCLK_dft;
GTECH_AND_NOT uck1 (.Z(selSTDCLK_dft), .A(selSTDCLK), .B(SCAN_TEST));
GtCLK_MUX2 ckDSPCLKi (.Z(DSPCLKi), .S(selSTDCLK_dft), .A(ONCLK), .B(STDCLK));
GTECH_AND_NOT uck2 (.Z(DSPoffx), .A(DSPoff), .B(PRST));
GTECH_AND_NOT uck3 (.Z(DSPoffx_dft), .A(DSPoffx), .B(SCAN_TEST));
GTECH_NOR2 uck4 (.Z(DSPCLKn), .A(DSPCLKi), .B(DSPoffx_dft));
`else
GtCLK_MUX2 ckDSPCLKi (.Z(DSPCLKi), .S(selSTDCLK), .A(ONCLK), .B(STDCLK));
GTECH_AND_NOT uck2 (.Z(DSPoffx), .A(DSPoff), .B(PRST));
GTECH_NOR2 uck4 (.Z(DSPCLKn), .A(DSPCLKi), .B(DSPoffx));
`endif
GtCLK_NOT ckDSPCLK (.Z(DSPCLK), .A(DSPCLKn));
GtCLK_NOT ckDSPCLK_cm0 (.Z(DSPCLK_cm0), .A(DSPCLKn));
GtCLK_NOT ckDSPCLK_cm1 (.Z(DSPCLK_cm1), .A(DSPCLKn));
GtCLK_NOT ckDSPCLK_cm2 (.Z(DSPCLK_cm2), .A(DSPCLKn));
GtCLK_NOT ckDSPCLK_pm0 (.Z(DSPCLK_pm0), .A(DSPCLKn));
GtCLK_NOT ckDSPCLK_pm1 (.Z(DSPCLK_pm1), .A(DSPCLKn));
GtCLK_NOT ckDSPCLK_pm2 (.Z(DSPCLK_pm2), .A(DSPCLKn));
GtCLK_NOT ckDSPCLK_dm0 (.Z(DSPCLK_dm0), .A(DSPCLKn));
GtCLK_NOT ckDSPCLK_dm1 (.Z(DSPCLK_dm1), .A(DSPCLKn));
GtCLK_NOT ckDSPCLK_dm2 (.Z(DSPCLK_dm2), .A(DSPCLKn));
`endif
`ifdef FD_DFT
assign #`da PRST = !P_RSTn && !SCAN_TEST;
`else
assign #`da PRST = !P_RSTn;
`endif
always @(posedge DSPCLK) RSTtext <= #`db RSTtext_h;
assign #`da SRST = HRST || RSTtext;
wire ARST;
`ifdef FD_DFT
wire ARST_h = (PRST || RSTtext);
assign ARST = SCAN_TEST ? HRST : ARST_h;
`else
assign #`da ARST = PRST || RSTtext;
`endif
reg [1:0] CTR_cnt;
wire CTR_en, CTR_reset;
always @(posedge ONCLK or posedge PRST)
if(PRST) CTR_cnt <= #`db 2'b0;
else if(CTR_en) CTR_cnt <= #`db CTR_cnt + 1;
assign #`da CTR_en = !(&{CTR_cnt[1:0]});
assign #`d0 CTR_reset = CTR_en;
`ifdef FD_DFT
REG16LC ckr_reg(DSPCLK, MMR_web, CKR_we, DMD[15:0], CKR[15:0], PRST, SCAN_TEST);
`else
REG16LC ckr_reg(DSPCLK, MMR_web, CKR_we, DMD[15:0], CKR[15:0], PRST);
`endif
assign #`da STDchg = (STDcnt[10:3]== CKR[7:0]);
assign #`da OUTchg = (OUTcnt[6:0] == CKR[14:8]);
`ifdef FD_FPGA
assign #`da STDCLKi = ONCLK && (STBY || SIDLE_s2);
`else
`ifdef FD_DFT
wire STDCLKi_enb_dft = STBY || SIDLE_s2 || SCAN_TEST;
GTECH_AND2 ckSTDCLKi (.Z(STDCLKi), .A(ONCLK), .B(STDCLKi_enb_dft));
`else
GtCLK_OA21 ckSTDCLKi (.Z(STDCLKi), .C(ONCLK), .A(STBY), .B(SIDLE_s2));
`endif
`endif
always @(posedge STDCLKi or posedge PRST) begin
if (PRST) STDcnt[10:0] <= #`db 11'b0;
else if (STDchg) STDcnt[10:0] <= #`db 11'b0;
else STDcnt[10:0] <= #`db STDcnt + 1;
end
`ifdef FD_FPGA
always @(posedge STDCLKi or posedge PRST) begin
if (PRST) STDCLK <= #`db 1'b0;
else if (STDchg) STDCLK <= #`db !STDCLK;
end
`else
GTECH_NOT STDCLK_u1 (.Z(PRSTB), .A(PRST));
`ifdef FD_DFT
GtCLK_FJK3 ckSTDCLK_h (.Q(STDCLK_h), .QN(), .CP(STDCLKi), .CD(PRSTB), .SD(1'b1),
.J(STDchg), .K(STDchg));
GTECH_MUX2 ckSTDCLK (.Z(STDCLK), .A(STDCLK_h), .B(STDCLKi), .S(SCAN_TEST));
`else
GtCLK_FJK3 ckSTDCLK (.Q(STDCLK), .QN(), .CP(STDCLKi), .CD(PRSTB), .SD(1'b1),
.J(STDchg), .K(STDchg));
`endif
`endif
`ifdef FD_FPGA
wire OUTCK = DSPCLK | CKR[15];
`else
`ifdef FD_DFT
wire OUTCK_en_dft = CKR[15] && !SCAN_TEST;
GtCLK_OR2 ckOUTCK (.Z(OUTCK), .A(DSPCLK), .B(OUTCK_en_dft));
`else
GtCLK_OR2 ckOUTCK (.Z(OUTCK), .A(DSPCLK), .B(CKR[15]));
`endif
`endif
always @(posedge OUTCK or posedge PRST) begin
if (PRST) OUTcnt[6:0] <= #`db 7'b0;
else if (OUTchg) OUTcnt[6:0] <= #`db 7'b0;
else OUTcnt[6:0] <= #`db OUTcnt + 1;
end
always @(posedge OUTCK or posedge PRST) begin
if (PRST) CLKOUT <= #`db 1'b0;
else if (OUTchg) CLKOUT <= #`db !CLKOUT;
end
assign #`da CLKO = CLKOUT && !CKR[15];
assign #`da SlowDn_ini = SIDLE_s1 && !SIDLE_s2;
`ifdef FD_DFT
wire clr_SIDLE_s1, clr_SIDLE_s1_h;
assign clr_SIDLE_s1_h = (ARST || CTR_reset);
assign clr_SIDLE_s1 = SCAN_TEST ? HRST : clr_SIDLE_s1_h;
`else
wire clr_SIDLE_s1;
assign #`da clr_SIDLE_s1 = ARST || CTR_reset;
`endif
always @(posedge ONCLK or posedge clr_SIDLE_s1)
if(clr_SIDLE_s1)
SIDLE_s1 <= #`db 0;
else if(SIDLE_s1 | !SIDLE_s2)
SIDLE_s1 <= #`db IDLE_ST;
always @(posedge STDCLK or posedge ARST)
if(ARST) begin
SIDLE_s2 <= #`db 0;
end
else begin
SIDLE_s2 <= #`db SIDLE_s1;
end
assign #`da stSlowDn = SlowDn_ini && (|{IRE[2:0]});
assign #`da crSlowDn = (TRAP_R || GOICE) ;
always @(posedge STDCLKi or posedge ARST) begin
if (ARST) SlowDn <= #`db 1'b0;
else if (crSlowDn) SlowDn <= #`db 1'b0;
else if (stSlowDn) SlowDn <= #`db STBY;
end
always @(posedge ONCLK) begin
SlowDn_s1 <= #`db SlowDn;
SlowDn_s2 <= #`db SlowDn_s1;
end
assign #`da enTRAP_RL = !(SlowDn || SlowDn_s1 || SlowDn_s2);
wire STBY_clr;
assign #`da STBY_set = IDLE_ST_h && !IRE[3];
`ifdef FD_DFT
wire STBY_clr_h = (RSTtext || CTR_reset);
assign STBY_clr = SCAN_TEST ? HRST : STBY_clr_h;
`else
assign #`da STBY_clr = RSTtext || CTR_reset;
`endif
always @(posedge DSPCLK or posedge STBY_clr) begin
if (STBY_clr) STBY <= #`db 1'b0;
else if (!IDLE_ST) STBY <= #`db STBY_set;
else if (TRAP_R_L) STBY <= #`db 1'b0;
end
Oneshot pwdr (X_PWDn, PWDrise);
assign #`da SLEEP_set = IDLE_ST_h && IRE[3];
`ifdef FD_DFT
wire SLEEP_clr_h = (SRST || PWDrise || ICE_wakeup || CTR_reset);
assign SLEEP_clr = SCAN_TEST ? HRST : SLEEP_clr_h;
`else
assign #`da SLEEP_clr = SRST || PWDrise || ICE_wakeup || CTR_reset;
`endif
always @(posedge DSPCLK or posedge SLEEP_clr) begin
if (SLEEP_clr) SLEEP <= #`db 1'b0;
else if (!IDLE_ST) SLEEP <= #`db SLEEP_set;
end
always @(posedge DSPCLKi or posedge ARST) begin
if (ARST) DSPoff <= #`db 0;
else if (DSPoff) DSPoff <= #`db !Cnt4096;
else DSPoff <= #`db SLEEP;
end
always @(posedge OSC)
OSCoff_set <= #`db DSPoff && SLEEP && XTALDIS;
wire OSCoff_clr;
`ifdef FD_DFT
wire OSCoff_clr_h = (PRST || ICE_wakeup || PWDrise);
assign OSCoff_clr = SCAN_TEST ? HRST : OSCoff_clr_h;
`else
assign #`da OSCoff_clr = PRST || ICE_wakeup || PWDrise;
`endif
always @(posedge OSC or posedge OSCoff_clr) begin
if (OSCoff_clr) OSCoff <= #`db 0;
else if (!OSCoff) OSCoff <= #`db OSCoff_set && SLEEP;
end
always @(posedge DSPCLK or posedge HRST) begin
if (HRST) PWDACK <= #`db 1'b0;
else if (!IDLE_ST) PWDACK <= #`db SLEEP_set;
else if (Awake) PWDACK <= #`db 1'b0;
end
wire OSCNTR_enb;
wire [11:0] OSCNTR_nx;
`ifdef FD_FPGA
assign #`da OSCNTR_ena = PWDACK && !SLEEP && IDLE_ST;
assign #`da OSCNTR_enb = !OSCNTR_ena;
`else
GTECH_NOT uck5 (.Z(SLEEPb), .A(SLEEP));
GTECH_AND3 uck6 (.Z(OSCNTR_ena), .A(PWDACK), .B(SLEEPb), .C(IDLE_ST));
GtCLK_NAND3 uck7 (.Z(OSCNTR_enb), .A(PWDACK), .B(SLEEPb), .C(IDLE_ST));
`endif
`ifdef FD_DFT
wire OSCNTR_clr_h = (ARST || Awake);
assign OSCNTR_clr = SCAN_TEST ? HRST : OSCNTR_clr_h;
`else
assign #`da OSCNTR_clr = ARST || Awake;
`endif
assign #`da OSCNTR_nx[11:0] = OSCNTR[11:0] + 1;
`ifdef FD_DFT
REG12LC oscntr_reg(OSC, OSCNTR_enb, OSCNTR_ena, OSCNTR_nx, OSCNTR[11:0],
OSCNTR_clr, SCAN_TEST);
`else
REG12LC oscntr_reg(OSC, OSCNTR_enb, OSCNTR_ena, OSCNTR_nx, OSCNTR[11:0],
OSCNTR_clr);
`endif
assign #`da Num128[6:0] = TMODE ? 7'hf : 7'h7f;
assign #`da Num4096[11:0] = TMODE ? 12'h1f : 12'hfff;
assign Cnt128_set = XTALDIS ? (OSCNTR[6:0] == Num128)
: (OSCNTR[11:0] != 12'h0);
always @(posedge OSC or posedge ARST) begin
if (ARST) Cnt128 <= #`db 0;
else if (Awake) Cnt128 <= #`db 0;
else if (!Cnt128) Cnt128 <= Cnt128_set;
end
assign #`da Cnt4096_set
= (XTALDIS && XTALDELAY) ? (OSCNTR[11:0] == Num4096)
: Cnt128;
always @(posedge OSC or posedge ARST) begin
if (ARST) Cnt4096 <= #`db 0;
else if (Awake) Cnt4096 <= #`db 0;
else if (!Cnt4096) Cnt4096 <= Cnt4096_set;
end
assign #`da Awake_h = Cnt4096_s1 && Cnt4096_s2;
always @(posedge DSPCLK or posedge PRST)
if(PRST) begin
Cnt4096_s1 <= #`db 1'b0;
Cnt4096_s2 <= #`db 1'b0;
Awake <= #`db 1'b0;
end
else begin
Cnt4096_s1 <= #`db Cnt4096;
Cnt4096_s2 <= #`db Cnt4096_s1;
Awake <= #`db Awake_h;
end
assign #`da RSTtext_h = Cnt4096 && Cnt4096_s2 && PUCR;
endmodule
|
`include "../include/x_def.v"
module CORE (/* ------------ Inputs ----------*/
DSPCLK, X_PWDn, X_IRQ2n, X_IRQL1n,
X_IRQL0n, X_IRQE1n, X_IRQE0n, X_IRQ1n,
X_IRQ0n, T_IST0, T_ISR0, T_IST1, T_ISR1,
T_ITMR, X_BRn, eRDY, EXTC_Eg, LDaST_Eg,
DwriteI_Eg, PwriteI_Eg, STI_Cg,
RSTtext_h, Awake, enTRAP_RL, STBY, PWRDn,
T_RST, GO_Fx, GO_Ex, GO_Cx, HALT_Eg,
IRR, IDR, Upd_IR, SPC,
SBP_EN, GOICE_syn, enTYP3,
TB_EN, SP1_EN, BIASRND,
T0Sreqx, R0Sreqx, T0sack, R0sack,
T1Sreqx, R1Sreqx, T1sack, R1sack,
STEAL, SREQ,
BOOT, DSreqx, DCTL,
T1IREG, T1MREG, R1IREG,
R1MREG, T0IREG, T0MREG,
R0IREG, R0MREG, PDFORCE,
CM_rd,
BIAD, /*BRST*/ BSreqx,
T_BDMA, BPM_cyc, BDM_cyc, BM_cyc,
`ifdef FD_DFT
SCAN_TEST,
`endif
GO_F, GO_E, GO_C, ICE_ST_h, ICE_ST, DRA,
EXA, HALTclr_h, GOICEclr_h,
GOICEdis, PPclr_h, BGn, MSTAT5, redoM_h,
redoSTI_h, redoLD_h, redoIF_h,
IR, Dummy_R, Dummy_E, nNOP_Eg, MTIDR_Eg,
SBP_R, Pread_R, Pwrite_R, Dread_R, Dwrite_R,
IOcmd_R, IOread_R, IOwrite_R, IDLE_R, EX_en,
CMAin,
IREo, GO_EC, ECYC, Double_E, PMOVL,
DMOVL,
MFSPT_E, MFRX0_E, MFTX0_E, MFRX1_E, MFTX1_E,
MTRX0_E, MTTX0_E, MTRX1_E, MTTX1_E,
DMA_R, DMA, DMAin,
PMA_R, PMA, PMAin,
T0wrap, T1wrap, R0wrap, R1wrap,
TRAP_R, TRAP_R_L, IDLE_ST_h, IDLE_ST,
accCM_R, accCM_E, wrCM_R, /*wrCM_E,*/ rdCM_E,
DMDix, DMDid, PMDin,
psqDMD_do, dagDMD_do,
euDMD_do, euPMD_do);
input [13:0] BIAD;
input BSreqx,
BPM_cyc,
BDM_cyc,
BM_cyc,
T_BDMA;
input [15:0] DMDix,
DMDid;
input [14:0] DCTL;
input BOOT,
RSTtext_h,
PWRDn,
STBY,
Awake,
enTRAP_RL,
STEAL,
SREQ,
DSreqx,
T0Sreqx,
R0Sreqx,
T1Sreqx,
R1Sreqx,
PDFORCE,
GOICE_syn,
enTYP3;
input T_RST, DSPCLK, X_PWDn, X_IRQ2n,
X_IRQL1n, X_IRQL0n, X_IRQE1n, X_IRQE0n,
X_IRQ1n, X_IRQ0n, T_IST0, T_ISR0,
T_IST1, T_ISR1, T_ITMR;
input DwriteI_Eg, PwriteI_Eg, STI_Cg,
LDaST_Eg;
input TB_EN, SP1_EN, BIASRND, X_BRn, eRDY, EXTC_Eg;
input GO_Fx, GO_Ex, GO_Cx, HALT_Eg, Upd_IR, SBP_EN;
input T0sack, R0sack, T1sack, R1sack;
input [23:0] CM_rd, SPC;
input [13:0] IRR;
input [15:0] IDR;
input [2:0] T1IREG;
input [1:0] T1MREG;
input [2:0] R1IREG;
input [1:0] R1MREG;
input [2:0] T0IREG;
input [1:0] T0MREG;
input [2:0] R0IREG;
input [1:0] R0MREG;
`ifdef FD_DFT
input SCAN_TEST;
`endif
output [15:0] psqDMD_do,
dagDMD_do,
euDMD_do,
euPMD_do;
output [7:0] PMOVL;
output [3:0] DMOVL;
output [14:0] IREo;
output TRAP_R,
TRAP_R_L,
IDLE_ST_h,
IDLE_ST,
GO_EC,
ECYC,
rdCM_E,
wrCM_R, /*wrCM_E,*/
accCM_R, accCM_E,
IOcmd_R,
IOread_R,
IOwrite_R,
Double_E,
redoIF_h,
redoSTI_h,
redoLD_h,
redoM_h;
output MFSPT_E, MFRX0_E, MFTX0_E, MFRX1_E,
MFTX1_E, MTRX0_E, MTTX0_E, MTRX1_E,
MTTX1_E;
output GO_F, GO_E, GO_C, ICE_ST_h, ICE_ST;
output HALTclr_h, GOICEclr_h;
output GOICEdis, PPclr_h, BGn;
output Dummy_R, Dummy_E, nNOP_Eg, MTIDR_Eg,
SBP_R;
output Pread_R, Pwrite_R, Dread_R, Dwrite_R;
output IDLE_R, EX_en;
output T0wrap, T1wrap, R0wrap, R1wrap;
output [13:0] CMAin, DRA, EXA;
output [23:0] IR;
output [13:0] DMA_R, PMA_R;
output [13:0] DMA, PMA;
output [13:0] DMAin, PMAin;
output MSTAT5;
input [15:0] PMDin;
/*-------------------------------------------*/
wire PPclr_h, GO_E, GO_C, Prderr_Eg, TRAP_Eg;
wire EXIT_E, MFIDR_E, HALT_Eg;
wire Ctrue, EX_en, EX_enc, Dummy_E, DU_R, dBR_R;
wire idBR_R, RET_R;
wire MACdep_Eg;
wire MFPSQ_E, MFIMASK_E;
wire MFICNTL_E, MFSSTAT_E, MFCNTR_E;
wire Ttrue, GO_F, GO_D;
wire CE, VpopST_Eg, cdAM_E, DIVQ_E, MFMSTAT;
wire DIVS_E, MTAR_E, MTAX0_E, MTAX1_E, MTAY0_E;
wire MTAY1_E, Rbyp_Rg, Xbyp_Rg, MFAR_E, MFAX0_E;
wire MFAX1_E, MFAY0_E, MFAY1_E, MFASTAT_E;
wire MFMX0_E, MFMX1_E, MFMY0_E, MFMY1_E, MFMR0_E, MFMR1_E;
wire MFMR2_E, MTASTAT_E, MTSI_E, MTSB_E;
wire MTSE_E, MTSR0_E, MTSR1_E, MFSI_E, MFSB_E, MFSE_E;
wire MFSR1_E, MFSR0_E, imSHT_E, MFDAG1_E, Post1_E;
wire accPM_E, Post2_E, MFDAG2_E;
wire Double_R, DAG1D_R, DAG2D_R, imAddr_R;
wire [7:0] MTIreg_E, MTLreg_E, MTMreg_E;
wire [7:0] MFIreg_E, MFLreg_E, MFMreg_E;
wire [19:0] IRE;
wire [7:0] ASTAT;
wire [6:0] MSTAT;
wire [13:0] IFA, Taddr_E;
wire [7:0] popASTATo;
wire [3:0] Term;
wire Squ_Rx, GO_MAC;
wire imm16_E, imm14_E;
wire [4:0] BTB_wa;
wire [25:0] BTB_wd, BTB_rd;
wire [11:0] RTB_wd, RTB_rd;
wire [13:0] Bt_I;
wire DAG1_EN, DAG2_EN;
wire [4:0] IFA_nx, BTB_ra;
wire [13:0] DMA, DMAin;
wire [13:0] PMA, PMAin;
assign #`d0 MSTAT5 = MSTAT[5];
assign #`d0 IREo[14:0] = IRE[14:0];
assign #`d0 Bt_I[13:0] = BTB_rd[15:2];
assign #`d0 RTB_wd[11:0] = {BTB_wd[25:16], BTB_wd[1:0]};
DEC c_dec (/* ---------- Inputs ---------- */
T_RST, DSPCLK, CM_rd[23:0],
`ifdef FD_DFT
SCAN_TEST,
`endif
PPclr_h, GO_D, GO_Ex, GO_Cx, Prderr_Eg,
/*TRAP_Eg,*/ ICE_ST, redoSTI_h,
ASTAT[6], Ctrue,
Upd_IR, SPC[23:0], SBP_EN, /*HALT_Eg,*/ enTYP3,
IR[23:0], IRE[19:0], EX_en, EX_enc, Dummy_E,
Dummy_R, DU_R, dBR_R, idBR_R, RET_R, RTS_R,
EXIT_E, DU_Eg, Call_Ed, RTI_Ed, RTS_Ed, BR_Ed,
RET_Ed, Nseq_Ed, IDLE_Eg, MACdep_Eg, MTCNTR_Eg,
MTOWRCNTR_Eg, MTtoppcs_Eg, MTIMASK_Eg, MTICNTL_Eg,
MTIFC_Eg, MTMSTAT_Eg, MFPSQ_E, MFtoppcs_Eg,
MFIMASK_E, MFICNTL_E, MFSSTAT_E, MFMSTAT_E,
MFCNTR_E, Stkctl_Eg, Modctl_Eg, MpopLP_Eg,
imm16_E,imm14_E, Long_Eg, Nrti_Ed,
ALUop_E, cdAM_E, MTAX0_E, MTAX1_E, MTAY0_E,
MTAY1_E, MTAR_E, MTASTAT_E, MFAX0_E, MFAX1_E,
MFAY0_E, MFAY1_E, MFAR_E, MFASTAT_E, MFALU_E,
pMFALU_E, DIVQ_E, DIVS_E, updAR_E, updAF_E,
ALUop_R, type9, DIVQ_R, DIVS_R,
MACop_E, satMR_Eg, Rbyp_Rg, Xbyp_Rg, Ybyp_Rg,
MTMX0_Eg, MTMX1_Eg, MTMY0_Eg, MTMY1_Eg, MTMR0_Eg,
MTMR1_Eg, MTMR2_Eg, MFMX0_E, MFMX1_E, MFMY0_E,
MFMY1_E, MFMR0_E, MFMR1_E, MFMR2_E, MFMAC_E,
pMFMAC_E, updMR_E, updMF_E, Squ_Rx,
MACop_R,
SHTop_E, imSHT_E, MTSI_E, MTSE_E, MTSR0_E,
MTSR1_E, MTSB_E, MFSI_E, MFSE_E, MFSR0_E, MFSR1_E,
MFSB_E, MFSHT_E, pMFSHT_E, updSR0_Eg, updSR1_Eg,
updSR_E,
MTIreg_E[7:0], MTLreg_E[7:0], MTMreg_E[7:0],
MFIreg_E[7:0], MFLreg_E[7:0], MFMreg_E[7:0],
MFDAG1_E, MFDAG2_E, accPM_E, Double_R, Double_E,
Post1_E, Post2_E, DAG1D_R, DAG2D_R, imAddr_R,
DAG1_EN, DAG2_EN, DAG2P_R, DMAen_R,
Pread_R, Pwrite_R, Dread_R, Dwrite_R, IOcmd_R,
IOread_R, IOwrite_R, IDLE_R, MTPMOVL_E, MTDMOVL_E,
MFPMOVL_E, MFDMOVL_E,
MFSPT_E, MFRX0_E, MFTX0_E, MFRX1_E, MFTX1_E, MTRX0_E,
MTTX0_E, MTRX1_E, MTTX1_E,
SBP_R, MFIDR_E, MTIDR_Eg, nNOP_Eg, accCM_R, accCM_E,
wrCM_R, /*wrCM_E,*/ rdCM_E
);
PSQ c_psq (/* ------------ Inputs : ------------- */
T_RST, DSPCLK, X_PWDn, X_IRQ2n, X_IRQL1n,
X_IRQL0n, X_IRQE1n, X_IRQE0n, X_IRQ1n, X_IRQ0n,
T_IST0, T_ISR0, T_IST1, T_ISR1, T_ITMR, IR[17:4],
DMDix[15:0],
RSTtext_h, Awake, enTRAP_RL, STBY,
IRE[19:0], EX_en, Dummy_R, dBR_R, idBR_R, RET_R,
DU_Eg, Call_Ed, RTI_Ed, BR_Ed, EXIT_E, RET_Ed,
Nseq_Ed, IDLE_Eg, MACdep_Eg, LDaST_Eg, MTCNTR_Eg,
MTOWRCNTR_Eg, MTtoppcs_Eg, MTIMASK_Eg, MTICNTL_Eg,
MTIFC_Eg, MTMSTAT_Eg, MFPSQ_E, MFtoppcs_Eg,
MFIMASK_E, MFICNTL_E, MFSSTAT_E, MFMSTAT_E,
MFCNTR_E, Stkctl_Eg, Modctl_Eg, MpopLP_Eg, imm16_E,
imm14_E, MFIDR_E, Long_Eg, Nrti_Ed, MTPMOVL_E,
MTDMOVL_E, MFPMOVL_E, MFDMOVL_E, accCM_R, accCM_E,
Bt_I[13:0], BTaken_I, RTaken_I, PTaken_R, PTaken_E,
PMA_R[13:0],
Ctrue, Ttrue, ASTAT[7:0],
SP1_EN, X_BRn, eRDY, EXTC_Eg, STI_Cg,
BOOT, STEAL, SREQ, DCTL[13:0], DSreqx,
GO_Fx, GO_Ex, GO_Cx, IRR[13:0], IDR[15:0], HALT_Eg,
GOICE_syn,
PDFORCE,
BIAD[13:0], /*BRST,*/ T_BDMA, BSreqx,
`ifdef FD_DFT
SCAN_TEST,
`endif
GO_F, GO_D, GO_E, GO_C, PPclr_h, MSTAT[6:0],
ICE_ST_h, ICE_ST, IDLE_ST_h, IDLE_ST, TRAP_Eg,
redoM_h, redoSTI_h, redoLD_h, redoEX_h, TRAP_R,
TRAP_R_L, Prderr_Eg,
Bterr_E, Taddr_E[13:0], IFA_nx[4:0],
CE, VpopST_Eg, popASTATo[7:0], Term[3:0], GO_MAC,
BGn, IFA[13:0],
PMOVL[7:0], DMOVL[3:0], redoIF_h,
GO_EC, ECYC,
CMAin[13:0],
HALTclr_h, GOICEclr_h, GOICEdis,
DRA[13:0], EXA[13:0],
psqDMD_do[15:0]);
BTB c_btb (/* ------------ Inputs : ------------- */
/*T_RST,*/ DSPCLK,
PPclr_h, GO_F, GO_D, GO_Ex, GO_Cx, IFA_nx[4:0],
IFA[13:0], EXA[13:0], Bterr_E, Taddr_E[13:0],
RTS_R, RTS_Ed, BR_Ed,
Ctrue,
TB_EN,
BTB_rd[25:0],
RTB_rd[11:0],
`ifdef FD_DFT
SCAN_TEST,
`endif
BTB_ra[4:0], BTB_wa[4:0], BTB_wd[25:0], BTB_web,
/*RTB_wd[11:0],*/ RTB_web,
BTaken_I, RTaken_I, PTaken_R, PTaken_E);
BTBmem ds32x26 (DSPCLK, BTB_wa[4:0], BTB_web, PWRDn, BTB_wd[25:0],
BTB_ra[4:0], BTB_rd[25:0]
`ifdef FD_DFT
,SCAN_TEST);
`else
);
`endif
RTBmem ds32x12 (DSPCLK, BTB_wa[4:0], RTB_web, PWRDn, RTB_wd[11:0],
BTB_ra[4:0], RTB_rd[11:0]
`ifdef FD_DFT
, SCAN_TEST);
`else
);
`endif
EU eu(/*--------------- Inputs ---------------*/
DSPCLK, T_RST, GO_Ex, GO_Cx, EX_en, EX_enc,
cdAM_E, DIVQ_E, DIVS_E, Double_E,
MTAR_E, MTAX0_E, MTAX1_E, MTAY0_E, MTAY1_E, Rbyp_Rg,
MFAR_E, MFAX0_E, MFAX1_E, MFAY0_E, MFAY1_E, MFASTAT_E,
MTMX0_Eg, MTMX1_Eg, MTMY0_Eg, MTMY1_Eg, MTMR0_Eg,
MTMR1_Eg, MTMR2_Eg, MFMX0_E, MFMX1_E, MFMY0_E, MFMY1_E,
MFMR0_E, MFMR1_E, MFMR2_E, Ybyp_Rg, MTASTAT_E,
MTSI_E, MTSB_E, MTSE_E,
MTSR0_E, MTSR1_E, MFSI_E, MFSB_E, MFSE_E, MFSR1_E,
MFSR0_E, imSHT_E, Xbyp_Rg, MFALU_E, MFMAC_E, MFSHT_E,
pMFALU_E, pMFMAC_E, pMFSHT_E, accPM_E, Squ_Rx, GO_MAC,
updSR0_Eg, updSR1_Eg, SHTop_E, satMR_Eg, MACop_E, updMF_E,
updMR_E, ALUop_E, updAR_E, updAF_E, ALUop_R, type9,
updSR_E, MACop_R, DIVQ_R, DIVS_R,
IR[17:0], IRE[14:0],
Term[3:0],
MSTAT[0], MSTAT[3], MSTAT[4], CE, MSTAT[2],
VpopST_Eg, popASTATo[7:0], RSTtext_h,
BIASRND,
`ifdef FD_DFT
SCAN_TEST,
`endif
ASTAT[7:0], Ctrue, Ttrue,
DMDid[15:0], euDMD_do[15:0], PMDin[15:0], euPMD_do[15:0]);
DAG dag(/* ----------------- Inputs ------------------*/
DSPCLK, T_RST, GO_Ex, GO_Cx, EX_en, STBY,
MTIreg_E[7:0], MTLreg_E[7:0], MTMreg_E[7:0],
MFIreg_E[7:0], MFLreg_E[7:0], MFMreg_E[7:0],
MFDAG1_E, Post1_E, imAddr_R, DAG1D_R, DAG2D_R,
DAG1_EN, Double_R, idBR_R, Post2_E, MFDAG2_E,
DAG2_EN, DAG2P_R, DMAen_R,
IRE[3:0], IR[17:0],
MSTAT[1], redoSTI_h, redoEX_h, PwriteI_Eg, DwriteI_Eg,
accPM_E, redoM_h,
STEAL, T0Sreqx, T1Sreqx, R0Sreqx, R1Sreqx,
SREQ, T0sack, T1sack, R0sack, R1sack,
R0IREG[2:0], R1IREG[2:0], T0IREG[2:0], T1IREG[2:0],
R0MREG[1:0], R1MREG[1:0], T0MREG[1:0], T1MREG[1:0],
DSreqx, BOOT, DCTL[14:0],
DMDid[15:0],
BSreqx, BPM_cyc, BDM_cyc, BIAD[13:0], BM_cyc,
ECYC,
`ifdef FD_DFT
SCAN_TEST,
`endif
T0wrap, T1wrap, R0wrap, R1wrap,
DMA_R[13:0], DMA[13:0], PMA_R[13:0], PMA[13:0],
DMAin[13:0], PMAin[13:0], dagDMD_do[15:0]);
endmodule
|
module DSP_CORE
(
T_RSTn,
T_ICE_RSTn,
T_BMODE,
T_MMAP,
T_TMODE,
T_CLKI_PLL,
T_CLKI_OSC,
T_Sel_PLL,
`ifdef FD_FPGA
`else
DSPCLK_insert_buf_i,
`endif
T_ED,
T_EA,
T_PWDn,
T_IRQ2n,
T_IRQ1n,
T_IRQ0n,
T_IRQL1n,
T_IRQE1n,
T_IRQE0n,
T_BRn,
T_RD0,
T_RD1,
T_SCLK0,
T_SCLK1,
T_RFS0,
T_TFS0,
T_RFS1,
T_TFS1,
T_IRDn,
T_IWRn,
T_ISn,
T_IAL,
T_IAD,
T_PIOin,
T_ICK,
T_IMS,
T_ID,
T_GOICE,
PM_bdry_sel,
PM_rd0,
PM_rd1,
PM_rd2,
PM_rd3,
PM_rd4,
PM_rd5,
PM_rd6,
PM_rd7,
DM_rdm,
DM_rd0,
DM_rd1,
DM_rd2,
DM_rd3,
DM_rd4,
DM_rd5,
DM_rd6,
DM_rd7,
CM_rdm,
CM_rd0,
CM_rd1,
CM_rd2,
CM_rd3,
CM_rd4,
CM_rd5,
CM_rd6,
CM_rd7,
`ifdef FD_DFT
SCANIN1,
SCANIN2,
SCANIN3,
SCANIN4,
SCANIN5,
SCANIN6,
SCANIN7,
SCANIN8,
SCAN_TEST,
SCAN_ENABLE,
`endif
DSPCLK_cm0,
DSPCLK_cm1,
DSPCLK_cm2,
DSPCLK_pm0,
DSPCLK_pm1,
DSPCLK_pm2,
DSPCLK_dm0,
DSPCLK_dm1,
DSPCLK_dm2,
CLKO,
PWDACK,
XTALoffn,
`ifdef FD_FPGA
`else
DSPCLK_insert_buf_o,
`endif
BGn,
EA_oe,
EA_do,
PMSn,
DMSn,
BMSn,
IOSn,
CMSn,
RDn,
WRn,
ED_oe_15,
ED_oe_14_8,
ED_oe_7_0,
ED_do,
ECMSn,
ECMA_EN,
TD0,
TD1,
SCLK0,
ISCLK0,
SCLK1,
ISCLK1,
RFS0,
IRFS0,
TFS0,
ITFS0,
RFS1,
IRFS1,
TFS1,
ITFS1,
IACKn,
IAD_oe,
IAD_do,
PIO_oe,
PIO_out,
IDo,
IDoe,
PMo_cs0,
PMo_cs1,
PMo_cs2,
PMo_cs3,
PMo_cs4,
PMo_cs5,
PMo_cs6,
PMo_cs7,
PMo_web,
PMo_oe0,
PMo_oe1,
PMo_oe2,
PMo_oe3,
PMo_oe4,
PMo_oe5,
PMo_oe6,
PMo_oe7,
PM_wd,
PMAinx,
DM_cs,
DMo_cs0,
DMo_cs1,
DMo_cs2,
DMo_cs3,
DMo_cs4,
DMo_cs5,
DMo_cs6,
DMo_cs7,
DMo_web,
DM_oe,
DMo_oe0,
DMo_oe1,
DMo_oe2,
DMo_oe3,
DMo_oe4,
DMo_oe5,
DMo_oe6,
DMo_oe7,
DM_wd,
DMAinx,
CM_cs,
CMo_cs0,
CMo_cs1,
CMo_cs2,
CMo_cs3,
CMo_cs4,
CMo_cs5,
CMo_cs6,
CMo_cs7,
CM_web,
CM_oe,
CMo_oe0,
CMo_oe1,
CMo_oe2,
CMo_oe3,
CMo_oe4,
CMo_oe5,
CMo_oe6,
CMo_oe7,
CM_wd,
CMAinx
`ifdef FD_DFT
,
SCANOUT1,
SCANOUT2,
SCANOUT3,
SCANOUT4,
SCANOUT5,
SCANOUT6,
SCANOUT7,
SCANOUT8
`endif
);
input T_RSTn,
T_ICE_RSTn,
T_BMODE,
T_MMAP,
T_CLKI_PLL,
T_CLKI_OSC,
T_Sel_PLL,
T_GOICE;
`ifdef FD_FPGA
`else
input DSPCLK_insert_buf_i;
`endif
input [1:0] T_TMODE;
input [15:0] T_ED;
input [7:0] T_EA;
input PM_bdry_sel,
T_PWDn,
T_BRn,
T_IRQ2n,
T_IRQ1n,
T_IRQ0n,
T_IRQL1n,
T_IRQE1n,
T_IRQE0n,
T_RD0,
T_RD1,
T_SCLK0,
T_SCLK1,
T_RFS0,
T_TFS0,
T_RFS1,
T_TFS1,
T_IRDn,
T_IWRn,
T_ISn,
T_IAL;
input [15:0] T_IAD;
input [11:0] T_PIOin;
input T_ICK,
T_IMS,
T_ID;
input [15:0] PM_rd0,
PM_rd1,
PM_rd2,
PM_rd3,
PM_rd4,
PM_rd5,
PM_rd6,
PM_rd7,
DM_rdm,
DM_rd0,
DM_rd1,
DM_rd2,
DM_rd3,
DM_rd4,
DM_rd5,
DM_rd6,
DM_rd7;
input [23:0] CM_rdm,
CM_rd0,
CM_rd1,
CM_rd2,
CM_rd3,
CM_rd4,
CM_rd5,
CM_rd6,
CM_rd7;
`ifdef FD_DFT
input
SCANIN1,
SCANIN2,
SCANIN3,
SCANIN4,
SCANIN5,
SCANIN6,
SCANIN7,
SCANIN8,
SCAN_TEST,
SCAN_ENABLE;
`endif
output DSPCLK_cm0,
DSPCLK_cm1,
DSPCLK_cm2,
DSPCLK_pm0,
DSPCLK_pm1,
DSPCLK_pm2,
DSPCLK_dm0,
DSPCLK_dm1,
DSPCLK_dm2,
CLKO,
XTALoffn,
PWDACK,
BGn,
EA_oe,
PMSn,
DMSn,
IOSn,
CMSn,
BMSn,
RDn,
WRn,
ED_oe_15,
ED_oe_14_8,
ED_oe_7_0,
ECMSn,
ECMA_EN;
output [15:0] ED_do;
output [14:0] EA_do;
`ifdef FD_FPGA
`else
output DSPCLK_insert_buf_o;
`endif
output TD0,
TD1,
SCLK0,
ISCLK0,
SCLK1,
ISCLK1,
RFS0,
IRFS0,
TFS0,
ITFS0,
RFS1,
IRFS1,
TFS1,
ITFS1;
output IACKn,
IAD_oe;
output [15:0] IAD_do;
output [11:0] PIO_oe,
PIO_out;
output IDo,
IDoe;
output
PMo_cs0,
PMo_cs1,
PMo_cs2,
PMo_cs3,
PMo_cs4,
PMo_cs5,
PMo_cs6,
PMo_cs7,
PMo_web,
PMo_oe0,
PMo_oe1,
PMo_oe2,
PMo_oe3,
PMo_oe4,
PMo_oe5,
PMo_oe6,
PMo_oe7,
DM_cs,
DMo_cs0,
DMo_cs1,
DMo_cs2,
DMo_cs3,
DMo_cs4,
DMo_cs5,
DMo_cs6,
DMo_cs7,
DMo_web,
DM_oe,
DMo_oe0,
DMo_oe1,
DMo_oe2,
DMo_oe3,
DMo_oe4,
DMo_oe5,
DMo_oe6,
DMo_oe7,
CM_cs,
CMo_cs0,
CMo_cs1,
CMo_cs2,
CMo_cs3,
CMo_cs4,
CMo_cs5,
CMo_cs6,
CMo_cs7,
CM_web,
CM_oe,
CMo_oe0,
CMo_oe1,
CMo_oe2,
CMo_oe3,
CMo_oe4,
CMo_oe5,
CMo_oe6,
CMo_oe7;
output [15:0] PM_wd,
DM_wd;
output [13:0] PMAinx,
DMAinx,
CMAinx;
output [23:0] CM_wd;
`ifdef FD_DFT
output
SCANOUT1,
SCANOUT2,
SCANOUT3,
SCANOUT4,
SCANOUT5,
SCANOUT6,
SCANOUT7,
SCANOUT8;
`endif
wire [23:0] CM_wd;
wire [15:0] PM_wd, DM_wd;
wire [7:0] PMOVL_dsp;
wire [3:0] DMOVL_dsp, PMOVL, DMOVL;
wire [23:0] IR;
wire [13:0] DRA, EXA, CMAin, CMAinx;
wire [13:0] IRR;
wire [15:0] RX0, RX1, TX0, TX1;
wire [13:0] DMA_R, PMA_R;
wire [13:0] DMA, PMA;
wire [13:0] DMAin, PMAin, DMAinx, PMAinx;
wire [14:0] EA_do;
wire [11:0] DOVL;
wire [14:0] DCTL, WSCR;
wire [15:0] CKR, SPT0_do, SPT1_do, PIO_do, TMR_do,
emcDMD_do, emcPMD_do, idmaPMD_do, SICEmmio,
autoDMD_do, T_ED, ED_do, T_IAD, IAD_do;
wire [7:0] T_EA, WSCR_ext;
wire [23:0] SPC, IDR;
wire [2:0] T0IREG, R0IREG, T1IREG, R1IREG;
wire [1:0] T0MREG, R0MREG, T1MREG, R1MREG, ECMAWAIT;
wire [2:0] DWWAIT, DRWAIT;
wire [3:0] ECMWAIT;
wire [11:0] T_PIOin, PIO_out, PIO_oe;
wire T_IPIOn, DSPCLK, TB_EN, SP0_EN, SP1_EN,
XTALoffn, BIASRND;
wire [15:0] psqDMD_do, dagDMD_do, euDMD_do,
euPMD_do;
wire [23:0] BRdataBUF;
wire [15:0] BDMAmmio;
wire [13:0] BIAD, BEAD;
wire [7:0] BMpage, BWdataBUF;
wire [11:0] BOVL;
wire [23:0] CM_rd, CM_rdata;
wire [15:0] PM_rd0, PM_rd1, DM_rd0,
DM_rd1, PMDin, DMDin;
wire [14:0] IREo;
wire [10:0] IOaddr = IREo[14:4];
wire [15:0] SYSRo = {ECMAWAIT[1:0], TB_EN, SP0_EN, SP1_EN, BIASRND,
DWWAIT[2:0], DRWAIT[2:0], ECMWAIT[3:0]};
wire T_IRQL0n = T_IPIOn;
wire CM_oe = 1'b1;
wire CMo_oe0 = 1'b1;
wire CMo_oe1 = 1'b1;
wire CMo_oe2 = 1'b1;
wire CMo_oe3 = 1'b1;
wire CMo_oe4 = 1'b1;
wire CMo_oe5 = 1'b1;
wire CMo_oe6 = 1'b1;
wire CMo_oe7 = 1'b1;
wire DM_oe = 1'b1;
wire DMo_oe0 = 1'b1;
wire DMo_oe1 = 1'b1;
wire DMo_oe2 = 1'b1;
wire DMo_oe3 = 1'b1;
wire DMo_oe4 = 1'b1;
wire DMo_oe5 = 1'b1;
wire DMo_oe6 = 1'b1;
wire DMo_oe7 = 1'b1;
wire PMo_oe0 = 1'b1;
wire PMo_oe1 = 1'b1;
wire PMo_oe2 = 1'b1;
wire PMo_oe3 = 1'b1;
wire PMo_oe4 = 1'b1;
wire PMo_oe5 = 1'b1;
wire PMo_oe6 = 1'b1;
wire PMo_oe7 = 1'b1;
Glogic glog (/* input */
T_RSTn,
T_ICE_RSTn,
T_CLKI_PLL,
T_CLKI_OSC,
T_Sel_PLL,
XTALoffn,
ED_oe,
BMcs,
BDIR,
T_TMODE[1:0],
`ifdef FD_DFT
SCAN_TEST,
`endif
P_RSTn,
T_CLKI,
T_selECM,
TMODE,
ED_oe_15,
ED_oe_14_8,
ED_oe_7_0);
CLKC clkc (/* -------- Inputs : --------- */
P_RSTn, GRST, T_CLKI, T_PWDn, TMODE,
DMDin[15:0],
IDLE_ST_h, IDLE_ST, IREo[3:0], GOICE,
ICE_wakeup, TRAP_R, TRAP_R_L,
CKR_we, MMR_web, TB_EN,
XTALDIS, XTALDELAY, PUCR,
`ifdef FD_DFT
SCAN_TEST,
`endif
RSTtext_h,
`ifdef FD_EVB
CORECLK, PERICLK,
`else
DSPCLK,
`endif
DSPCLK_cm0, DSPCLK_cm1, DSPCLK_cm2,
DSPCLK_pm0, DSPCLK_pm1, DSPCLK_pm2,
DSPCLK_dm0, DSPCLK_dm1, DSPCLK_dm2,
PWDACK, CLKO,
Awake_h, Awake, enTRAP_RL, STBY, PWRDn,
XTALoffn,
CKR[15:0]);
CORE core (/* ------------ Inputs ----------*/
`ifdef FD_EVB
CORECLK,
`else
DSPCLK,
`endif
T_PWDn, T_IRQ2n, T_IRQL1n,
T_IRQL0n, T_IRQE1n, T_IRQE0n, T_IRQ1n,
T_IRQ0n, T_IST0, T_ISR0, T_IST1, T_ISR1,
T_ITMR, T_BRn, eRDY, EXTC_Eg, LDaST_Eg,
DwriteI_Eg, PwriteI_Eg, STI_Cg,
RSTtext_h, Awake, enTRAP_RL, STBY, PWRDn,
GRST, GO_Fx, GO_Ex, GO_Cx, HALT_Eg,
IRR[13:0], IDR[15:0], Upd_IR, SPC[23:0],
SBP_EN, GOICE_syn, enTYP3,
TB_EN, SP1_EN, BIASRND,
T0Sreqx, R0Sreqx, T0Sack, R0Sack,
T1Sreqx, R1Sreqx, T1Sack, R1Sack,
STEAL, SREQ,
BOOT, DSreqx, DCTL[14:0],
T1IREG[2:0], T1MREG[1:0], R1IREG[2:0],
R1MREG[1:0], T0IREG[2:0], T0MREG[1:0],
R0IREG[2:0], R0MREG[1:0], PDFORCE,
CM_rdata[23:0],
BIAD[13:0], /*BRST,*/ BSreqx,
T_BDMA, BPM_cyc, BDM_cyc, BM_cyc,
`ifdef FD_DFT
SCAN_TEST,
`endif
GO_F, GO_E, GO_C, ICE_ST_h, ICE_ST, DRA[13:0],
EXA[13:0], HALTclr_h, GOICEclr_h,
GOICEdis, PPclr_h, BGn, MSTAT5, redoM_h,
redoSTI_h, redoLD_h, redoIF_h,
IR[23:0], Dummy_R, Dummy_E, nNOP_Eg, MTIDR_Eg,
SBP_R, Pread_R, Pwrite_R, Dread_R, Dwrite_R,
IOcmd_R, IOread_R, IOwrite_R, IDLE_R, EX_en,
CMAin[13:0],
IREo[14:0], GO_EC, ECYC, Double_E, PMOVL_dsp[7:0],
DMOVL_dsp[3:0],
MFSPT_E, MFRX0_E, MFTX0_E, MFRX1_E, MFTX1_E,
MTRX0_E, MTTX0_E, MTRX1_E, MTTX1_E,
DMA_R[13:0], DMA[13:0], DMAin[13:0],
PMA_R[13:0], PMA[13:0], PMAin[13:0],
T0wrap, T1wrap, R0wrap, R1wrap,
TRAP_R, TRAP_R_L, IDLE_ST_h, IDLE_ST,
accCM_R, accCM_E, wrCM_R, /*wrCM_E,*/ rdCM_E,
DMDin[15:0], DMDin[15:0], PMDin[15:0],
psqDMD_do[15:0], dagDMD_do[15:0],
euDMD_do[15:0], euPMD_do[15:0]);
MEMC memc (/* ------------ Inputs : ------------- */
`ifdef FD_EVB
PERICLK,
`else
DSPCLK,
`endif
GRST, STBY, DMDin[15:0],
PPclr_h, GO_Ex, GO_Cx,
redoM_h, redoSTI_h, redoLD_h, IDLE_ST,
DMOVL_dsp[3:0], PMOVL_dsp[7:4],
Pread_R, Pwrite_R, Dread_R, Dwrite_R,
IOcmd_R, IOread_R, IOwrite_R, Dummy_R,
Dummy_E,
DMA_R[13:5], PMA_R[13:12], DMA[13:0],
DMAin[13:5], PMAin[13:12],
SREQ, STEAL, DMSreqx_wr, PMSreqx_wr,
DMSreqx_rd, PMSreqx_rd,
BOOT, PMOVL[3:0], DMOVL[3:0],
DSreqx, DRDcyc,
T_selECM,
BM_cyc, ECYC,
`ifdef FD_DFT
SCAN_TEST,
`endif
PM_bdry_sel,
SP0_EN, selAUTO0, selFSDIV0, selSCLKDIV0,
selSCTL0, selMWORD0, AUTO0_we, FSDIV0_we,
SCLKDIV0_we, SCTL0_we, MWORD0_we,
SP1_EN, selAUTO1, selFSDIV1, selSCLKDIV1,
selSCTL1, selMWORD1, AUTO1_we, FSDIV1_we,
SCLKDIV1_we, SCTL1_we, MWORD1_we,
selPFTYPE, selPDATA, selPIMASK, selPINT,
PFTYPE_we, PDATA_we, PIMASK_we, PINT_we,
selTPERIOD, selTCOUNT, selTSCALE,
TPERIOD_we, TCOUNT_we, TSCALE_we,
Pread_Ei, Pwrite_Ei, Dread_Ei, Dwrite_Ei,
IOcmd_Ei, IOread_Ei, IOwrite_Ei, WSCR_we, WSCR_ext_we,
selWSCR, selWSCR_ext, EXTC_Eg, ECMWAIT[3:0], ECMAWAIT[1:0],
selCKR, CKR_we,
DWWAIT[2:0], DRWAIT[2:0], selDCTL, selDOVL,
DCTL_we, DOVL_we,
selSYSR, ldSREG_E, MMR_web,
TB_EN,
DwriteI_Eg, PwriteI_Eg, STI_Cg, LDaST_Eg,
BIASRND,
accPM_Eg, accDM_Eg,
PMo_cs0, PMo_cs1,
PMo_cs2, PMo_cs3,
PMo_cs4, PMo_cs5,
PMo_cs6, PMo_cs7,
PMo_web,
PMo_oe0_K, PMo_oe1_K,
PMo_oe2_K, PMo_oe3_K,
PMo_oe4_K, PMo_oe5_K,
PMo_oe6_K, PMo_oe7_K,
DM_cs,
DMo_cs0, DMo_cs1,
DMo_cs2, DMo_cs3,
DMo_cs4, DMo_cs5,
DMo_cs6, DMo_cs7,
DMo_web,
DM_oe_K,
DMo_oe0_K, DMo_oe1_K,
DMo_oe2_K, DMo_oe3_K,
DMo_oe4_K, DMo_oe5_K,
DMo_oe6_K, DMo_oe7_K,
selBIAD, selBEAD, selBCTL, selBCNT, selBOVL,
BCNT_we, BCTL_we, BOVL_we, BIAD_we, BEAD_we,
selIVER
);
EMC emc (/* ------------ Inputs : ------------- */
`ifdef FD_EVB
PERICLK,
`else
DSPCLK,
`endif
GRST, PPclr_h, DMDin[15:0], T_selECM,
PM_bdry_sel,
GO_Fx, GO_Ex, GO_EC, ECYC, BGn, PMOVL_dsp[7:0],
DMOVL_dsp[3:0], Dummy_E,
IOaddr[10:0], Double_E, accCM_E, rdCM_E,
DMA[13:0], PMA[13:0], WSCR_we, WSCR_ext_we, EXTC_Eg,
Pread_Ei, Pwrite_Ei, Dread_Ei, Dwrite_Ei,
IOcmd_Ei, IOread_Ei, IOwrite_Ei, MMR_web,
CMAin[13:0], ECMAWAIT[1:0],
IDR[23:0],
T_EA[7:0], T_ED[15:0],
PMDin[15:0],
CM_rd[23:0],
BDMAmode, BMpage[7:0],
BDIR, BWdataBUF[7:0], BWRn, BEAD[13:0],
BSreq, BSack, BWend,
`ifdef FD_DFT
SCAN_TEST,
`endif
EA_oe, EA_do[14:0], ED_oe, ED_do[15:0],
PMSn, DMSn, IOSn, BMSn,
CMSn, RDn, WRn, ECMSn, ECMA_EN,
eRDY,
WSCR[14:0], WSCR_ext[7:0], emcDMD_oe, emcDMD_do[15:0],
emcPMD_oe, emcPMD_do[15:0],
CM_rdata[23:0],
ENS12, ECS12, ENS13, ECS13, ENS14,
ECS14, ENS0, BMcs
);
IDMA idma (/* -------- Inputs : --------- */
T_IRDn, T_IWRn, T_ISn, T_IAL, T_BMODE, T_MMAP,
T_selECM, PM_bdry_sel,
STBY, Awake_h,
P_RSTn, GRST,
`ifdef FD_EVB
PERICLK,
`else
DSPCLK,
`endif
GO_Fx, GO_Ex, IDLE_ST_h,
ICE_ST_h, ICE_ST, DMDin[15:0], PMOVL_dsp[7:0],
DMOVL_dsp[3:0], CMAin[13:12], redoIF_h,
DWWAIT[2:0], DRWAIT[2:0], DCTL_we, DOVL_we,
MMR_web,
STEAL, DSack, DSreqx,
IDR[23:0], accCM_R, accCM_E, wrCM_R,
BDMA_end, BDMA_boot, BCMRD_cyc,
BOVL[11:0], BRdataBUF[23:0], BCM_cyc,
BSreqx, BM_cyc, ECYC,
`ifdef FD_DFT
SCAN_TEST,
`endif
IACKn,
BOOT, DCTL[14:0], DOVL[11:0],
PMOVL[3:0], DMOVL[3:0],
idmaDMD_oe, idmaPMD_oe, idmaPMD_do[15:0],
DSreq, DWRcyc, PWRcyc, DRDcyc, PRDcyc,
CM_cs, CM_web, CM_oe_K,
CMo_cs0, CMo_cs1, CMo_cs2, CMo_cs3, CMo_cs4,
CMo_cs5, CMo_cs6, CMo_cs7,
CMo_oe0_K, CMo_oe1_K, CMo_oe2_K, CMo_oe3_K,
CMo_oe4_K, CMo_oe5_K, CMo_oe6_K, CMo_oe7_K,
T_IAD[15:0], IAD_do[15:0], IAD_oe,
PMDin[15:0], CM_rd[23:0], CM_wd[23:0],
GO_STEAL);
SPORT0 sport0 (/* -------- Inputs : --------- */
T_RD0,
GRST,
`ifdef FD_EVB
PERICLK,
`else
DSPCLK,
`endif
GO_Cx, EX_en, MTTX0_E,
MTRX0_E, T0wrap, R0wrap, DMDin[15:0],
SP0_EN, selAUTO0, selFSDIV0, selSCLKDIV0,
selSCTL0, selMWORD0, AUTO0_we, FSDIV0_we,
SCLKDIV0_we, SCTL0_we, MWORD0_we, MMR_web,
T0Sack, R0Sack,
`ifdef FD_DFT
SCAN_TEST,
`endif
TD0,
T_ISR0, T_IST0, T0IREG[2:0], T0MREG[1:0],
R0IREG[2:0], R0MREG[1:0], PDFORCE,
XTALDIS, XTALDELAY, PUCR,
T0Sreq, R0Sreq, RX0[15:0], TX0[15:0],
SPT0_do[15:0],
SCLK0, T_SCLK0, ISCLK0,
RFS0, T_RFS0, IRFS0,
TFS0, T_TFS0, ITFS0);
SPORT1 sport1 (/* -------- Inputs : --------- */
T_RD1,
GRST,
`ifdef FD_EVB
PERICLK,
`else
DSPCLK,
`endif
GO_Cx, EX_en, MTTX1_E,
MTRX1_E, T1wrap, R1wrap, DMDin[15:0],
SP1_EN, selAUTO1, selFSDIV1, selSCLKDIV1,
selSCTL1, selMWORD1, AUTO1_we, FSDIV1_we,
SCLKDIV1_we, SCTL1_we, MWORD1_we, MMR_web,
T1Sack, R1Sack,
`ifdef FD_DFT
SCAN_TEST,
`endif
TD1,
T_ISR1, T_IST1, T1IREG[2:0], T1MREG[1:0],
R1IREG[2:0], R1MREG[1:0],
T1Sreq, R1Sreq, RX1[15:0], TX1[15:0],
SPT1_do[15:0],
SCLK1, T_SCLK1, ISCLK1,
RFS1, T_RFS1, IRFS1,
TFS1, T_TFS1, ITFS1);
AUTOctl auctl (/* -------- Inputs : --------- */
GRST,
`ifdef FD_EVB
PERICLK,
`else
DSPCLK,
`endif
GO_E, MFRX0_E,
MFTX0_E, MFRX1_E, MFTX1_E, MFSPT_E,
ICE_ST,
STBY,
DSreq, DWRcyc, PWRcyc, /*CWRcyc,*/
DRDcyc, PRDcyc, /*CRDcyc,*/ BOOT,
T0Sreq, R0Sreq, RX0[15:0], TX0[15:0],
T1Sreq, R1Sreq, RX1[15:0], TX1[15:0],
BSreq, BDMRD_cyc, BDMWR_cyc, BPMRD_cyc,
BPMWR_cyc, BM_cyc, ECYC,
`ifdef FD_DFT
SCAN_TEST,
`endif
STEAL, SREQ,
DMSreqx_wr, PMSreqx_wr, /*CMSreqx_wr,*/
DMSreqx_rd, PMSreqx_rd, /*CMSreqx_rd,*/
DSack, DSreqx,
T0Sreqx, R0Sreqx, T0Sack, R0Sack,
T1Sreqx, R1Sreqx, T1Sack, R1Sack,
spt0DMD_oe, spt1DMD_oe,
BSack, BSreqx,
autoDMD_do[15:0]);
`ifdef FD_EVB
BUFG ick(.O(T_ICKi), .I(T_ICK));
`endif
SICE sice (/* ------------ Inputs : ------------- */
P_RSTn,
`ifdef FD_EVB
T_ICKi,
`else
T_ICK,
`endif
T_IMS,
`ifdef FD_EVB
CORECLK,
`else
DSPCLK,
`endif
CM_rdata[23:0],
DMDin[15:0], T_GOICE, PM_bdry_sel,
enTRAP_RL,
GO_F, GO_E, GO_C, ICE_ST, DRA[13:0],
EXA[13:0], HALTclr_h,
GOICEclr_h, GOICEdis,
PMOVL_dsp[7:0], DMOVL_dsp[3:0],
IR[23:0], Dummy_R, nNOP_Eg, MTIDR_Eg,
SBP_R, rdCM_E,
BGn, PMA[13:0], DMA[13:0], EXTC_Eg,
accPM_Eg, accDM_Eg,
eRDY,
BRST, IACKn,
`ifdef FD_DFT
SCAN_TEST,
`endif
GRST, GO_Fx, GO_Ex, GO_Cx, HALT_Eg,
IRR[13:0], IDR[23:0], GOICE, GOICE_syn,
ICE_wakeup,
Upd_IR, SPC[23:0], SBP_EN, enTYP3,
T_ID, IDo, IDoe,
EX_en, selIVER,
SICEmmio[15:0]
);
PIO pio (/*------------- Input from IO Pads ------------*/
`ifdef FD_EVB
PERICLK,
`else
DSPCLK,
`endif
GRST, DMDin[15:0], T_PIOin[11:0],
selPIMASK, selPINT, selPFTYPE, selPDATA,
PIMASK_we, PINT_we, PFTYPE_we, PDATA_we,
MMR_web,
`ifdef FD_DFT
SCAN_TEST,
`endif
T_IPIOn, PIO_do[15:0], PIO_oe[11:0], PIO_out[11:0]);
TM tm(/*----------------- Inputs -------------------*/
T_CLKI,
`ifdef FD_EVB
PERICLK,
`else
DSPCLK,
`endif
GRST, TMODE, DMDin[15:0],
selTSCALE, selTCOUNT, selTPERIOD,
TSCALE_we, TCOUNT_we, TPERIOD_we, MSTAT5,
TMR_do[15:0], MMR_web,
ICE_ST,
`ifdef FD_DFT
SCAN_TEST,
`endif
T_ITMR);
REGo regout (/* -------- Inputs : --------- */
DM_rdm[15:0],
DM_rd0[15:0], DM_rd1[15:0],
DM_rd2[15:0], DM_rd3[15:0],
DM_rd4[15:0], DM_rd5[15:0],
DM_rd6[15:0], DM_rd7[15:0],
PM_rd0[15:0], PM_rd1[15:0],
PM_rd2[15:0], PM_rd3[15:0],
PM_rd4[15:0], PM_rd5[15:0],
PM_rd6[15:0], PM_rd7[15:0],
CM_rdm[23:0],
CM_rd0[23:0], CM_rd1[23:0],
CM_rd2[23:0], CM_rd3[23:0],
CM_rd4[23:0], CM_rd5[23:0],
CM_rd6[23:0], CM_rd7[23:0],
`ifdef FD_EVB
PERICLK,
`else
DSPCLK,
`endif
GO_Cx, redoSTI_h, Pwrite_Ei,
psqDMD_do[15:0], dagDMD_do[15:0],
euDMD_do[15:0], euPMD_do[15:0],
CKR[15:0],
SPT0_do[15:0], RX0[15:0],
SPT1_do[15:0], RX1[15:0],
PIO_do[15:0],
TMR_do[15:0],
DCTL[14:0], DOVL[11:0], idmaPMD_oe,
idmaDMD_oe, idmaPMD_do[15:0],
SREQ, spt0DMD_oe, spt1DMD_oe,
autoDMD_do[15:0],
WSCR[14:0], WSCR_ext[7:0], emcDMD_oe, emcDMD_do[15:0],
emcPMD_oe, emcPMD_do[15:0],
SYSRo[15:0], ldSREG_E, selSYSR, selCKR,
selDCTL, selDOVL, selWSCR, selWSCR_ext,
DM_oe_K,
DMo_oe0_K, DMo_oe1_K,
DMo_oe2_K, DMo_oe3_K,
DMo_oe4_K, DMo_oe5_K,
DMo_oe6_K, DMo_oe7_K,
PMo_oe0_K, PMo_oe1_K,
PMo_oe2_K, PMo_oe3_K,
PMo_oe4_K, PMo_oe5_K,
PMo_oe6_K, PMo_oe7_K,
CM_oe_K,
CMo_oe0_K, CMo_oe1_K,
CMo_oe2_K, CMo_oe3_K,
CMo_oe4_K, CMo_oe5_K,
CMo_oe6_K, CMo_oe7_K,
BRdataBUF[23:0], bdmaDMD_oe,
BDMAmmio[15:0], bdmaPMD_oe,
DM_wd[15:0], DMDin[15:0], PM_wd[15:0],
PMDin[15:0], CM_rd[23:0], SICEmmio[15:0]);
BDMA bdma (/* ---------- Inputs : ---------- */
BSreqx, BSack,
T_MMAP, T_BMODE, T_ED[7:0], P_RSTn,
GRST, PM_bdry_sel,
ENS12, ECS12, ENS13, ECS13,
ENS14, ECS14, ENS0,
`ifdef FD_EVB
PERICLK,
`else
DSPCLK,
`endif
CM_rd[23:0], PMDin[15:0],
DMDin[15:0],
BOOT, GO_STEAL,
BCNT_we, BCTL_we, BOVL_we, BIAD_we,
BEAD_we, selBCNT, selBCTL, selBOVL,
selBIAD, selBEAD,
`ifdef FD_DFT
SCAN_TEST,
`endif
BDMWR_cyc, BPMWR_cyc, BDMRD_cyc,
BPMRD_cyc, BSreq,
BDMAmode, BMpage[7:0], BEAD[13:0],
BWdataBUF[7:0], BDIR, BWRn,
BWend,
BDMA_end, BDMA_boot, BCM_cyc, BCMRD_cyc,
BRdataBUF[23:0], BOVL[11:0], BM_cyc,
T_BDMA, BPM_cyc, BDM_cyc,
BIAD[13:0], BRST,
BDMAmmio[15:0], bdmaDMD_oe, bdmaPMD_oe
);
`ifdef FD_EVB
assign #`db CMAinx[13:0] = CMAin[13:0];
assign #`db DMAinx[13:0] = DMAin[13:0];
assign #`db PMAinx[13:0] = PMAin[13:0];
`else
MAbufx bufc (CMAin[13:0], CMAinx[13:0]);
MAbufx bufd (DMAin[13:0], DMAinx[13:0]);
MAbufx bufp (PMAin[13:0], PMAinx[13:0]);
`endif
endmodule
|
`include "../include/x_def.v"
module Glogic(/* input */
T_RSTn,
T_ICE_RSTn,
T_CLKI_PLL,
T_CLKI_OSC,
T_Sel_PLL,
XTALoffn,
ED_oe,
BMcs,
BDIR,
T_TMODE,
`ifdef FD_DFT
SCAN_TEST,
`endif
P_RSTn,
T_CLKI,
T_selECM,
TMODE,
ED_oe_15,
ED_oe_14_8,
ED_oe_7_0
);
input [1:0] T_TMODE;
input T_RSTn,
ED_oe,
BMcs,
BDIR,
T_ICE_RSTn,
T_CLKI_PLL,
T_CLKI_OSC,
T_Sel_PLL,
XTALoffn;
`ifdef FD_DFT
input SCAN_TEST;
`endif
output P_RSTn,
T_CLKI,
T_selECM,
TMODE,
ED_oe_15,
ED_oe_14_8,
ED_oe_7_0;
wire T_CLKI_SRC;
`ifdef FD_DFT
assign P_RSTn = SCAN_TEST ? T_RSTn : T_RSTn && T_ICE_RSTn;
`else
assign P_RSTn = T_RSTn && T_ICE_RSTn;
`endif
`ifdef FD_DFT
wire T_Sel_PLL_dft;
wire XTALoffn_dft;
assign T_Sel_PLL_dft = T_Sel_PLL && !SCAN_TEST;
assign T_CLKI_SRC = T_Sel_PLL_dft ? T_CLKI_PLL : T_CLKI_OSC;
assign XTALoffn_dft = XTALoffn || SCAN_TEST;
GtCLK_NAND2 ckT_CLKI (.Z(T_CLKI), .A(T_CLKI_SRC), .B(XTALoffn_dft));
`else
assign T_CLKI_SRC = T_Sel_PLL ? T_CLKI_PLL : T_CLKI_OSC;
`ifdef FD_FPGA
assign T_CLKI = !(T_CLKI_SRC && XTALoffn);
`else
GtCLK_NAND2 ckT_CLKI (.Z(T_CLKI), .A(T_CLKI_SRC), .B(XTALoffn));
`endif
`endif
assign T_selECM = T_TMODE[1];
assign TMODE = T_TMODE[0];
assign ED_oe_15 = ED_oe;
assign ED_oe_14_8 = ED_oe || BMcs;
assign ED_oe_7_0 = ED_oe || BMcs && BDIR;
endmodule
|
module MUX_IO(
D_CLKI_OSC,
D_RSTn,
D_ICK,
D_IRQ2n,
D_IRQL1n,
D_IRQE1n,
D_IRQE0n,
D_RD0,
D_RD1,
D_IAD_di,
`ifdef FD_DFT
D_DFT_en,
`endif
`ifdef FD_DFT
WP_SO,
TC_SO,
VC_SO,
`endif
TD0,
TD1,
IAD_oe,
IAD_do,
D_TD0,
D_TD1,
D_IAD_do,
IAD_oex,
T_CLKI_OSC,
T_RSTn,
T_ICK,
T_IRQ2n,
T_IRQL1n,
T_IRQE1n,
T_IRQE0n,
T_RD0,
T_RD1,
PM_bdry_sel,
T_IAD
`ifdef FD_DFT
,
TEST_CLK,
TEST_RST,
TCLK,
VC_SHIFT,
TC_UPDATE,
TC_SHIFT,
TC_SI,
WP_SI,
WP_CLK,
TC_RESET,
VC_SI
`endif
);
input D_CLKI_OSC,
D_RSTn,
D_ICK,
D_IRQ2n,
D_IRQL1n,
D_IRQE1n,
D_IRQE0n,
D_RD0,
D_RD1;
input [15:0] D_IAD_di;
`ifdef FD_DFT
input D_DFT_en;
`endif
`ifdef FD_DFT
input WP_SO,
TC_SO;
input [7:0] VC_SO;
`endif
input TD0,
TD1,
IAD_oe;
input [15:0] IAD_do;
output D_TD0,
D_TD1,
IAD_oex;
output [15:0] D_IAD_do;
output T_CLKI_OSC,
T_RSTn,
T_ICK,
T_IRQ2n,
T_IRQL1n,
T_IRQE1n,
T_IRQE0n,
T_RD0,
T_RD1,
PM_bdry_sel;
output [15:0] T_IAD;
`ifdef FD_DFT
output TEST_CLK,
TEST_RST,
TCLK,
VC_SHIFT,
TC_UPDATE,
TC_SHIFT,
TC_SI,
WP_SI,
WP_CLK,
TC_RESET;
output [7:0] VC_SI;
`endif
`ifdef FD_DFT
assign T_CLKI_OSC = !D_DFT_en && D_CLKI_OSC;
assign TEST_CLK = D_DFT_en && D_CLKI_OSC;
assign T_RSTn = !D_DFT_en && D_RSTn;
assign TEST_RST = D_DFT_en && D_RSTn;
assign T_ICK = !D_DFT_en && D_ICK;
assign TCLK = D_DFT_en && D_ICK;
assign T_IRQ2n = !D_DFT_en && D_IRQ2n;
assign VC_SHIFT = D_DFT_en && D_IRQ2n;
assign T_IRQL1n = !D_DFT_en && D_IRQL1n;
assign TC_UPDATE = D_DFT_en && D_IRQL1n;
assign T_IRQE1n = !D_DFT_en && D_IRQE1n;
assign TC_SHIFT = D_DFT_en && D_IRQE1n;
assign T_IRQE0n = !D_DFT_en && D_IRQE0n;
assign TC_SI = D_DFT_en && D_IRQE0n;
assign T_RD0 = !D_DFT_en && D_RD0;
assign WP_SI = D_DFT_en && D_RD0;
assign T_RD1 = !D_DFT_en && D_RD1;
assign WP_CLK = D_DFT_en && D_RD1;
assign TC_RESET = !D_RSTn;
`else
assign T_RSTn = D_RSTn;
assign T_CLKI_OSC = D_CLKI_OSC;
assign T_IRQ2n = D_IRQ2n;
assign T_IRQL1n = D_IRQL1n;
assign T_IRQE1n = D_IRQE1n;
assign T_IRQE0n = D_IRQE0n;
assign T_RD0 = D_RD0;
assign T_RD1 = D_RD1;
assign T_ICK = D_ICK;
`endif
`ifdef FD_DFT
assign D_TD0 = D_DFT_en ? WP_SO : TD0;
assign D_TD1 = D_DFT_en ? TC_SO : TD1;
`else
assign D_TD0 = TD0;
assign D_TD1 = TD1;
`endif
`ifdef FD_DFT
assign D_IAD_do[15:8] = D_DFT_en ? VC_SO[7:0] : IAD_do[15:8];
assign D_IAD_do[7:0] = IAD_do[7:0];
assign IAD_oex = IAD_oe || D_DFT_en;
assign T_IAD[15:8] = D_IAD_di[15:8];
assign T_IAD[7] = !D_DFT_en && D_IAD_di[7];
assign VC_SI[7] = D_DFT_en && D_IAD_di[7];
assign T_IAD[6] = !D_DFT_en && D_IAD_di[6];
assign VC_SI[6] = D_DFT_en && D_IAD_di[6];
assign T_IAD[5] = !D_DFT_en && D_IAD_di[5];
assign VC_SI[5] = D_DFT_en && D_IAD_di[5];
assign T_IAD[4] = !D_DFT_en && D_IAD_di[4];
assign VC_SI[4] = D_DFT_en && D_IAD_di[4];
assign T_IAD[3] = !D_DFT_en && D_IAD_di[3];
assign VC_SI[3] = D_DFT_en && D_IAD_di[3];
assign T_IAD[2] = !D_DFT_en && D_IAD_di[2];
assign VC_SI[2] = D_DFT_en && D_IAD_di[2];
assign T_IAD[1] = !D_DFT_en && D_IAD_di[1];
assign VC_SI[1] = D_DFT_en && D_IAD_di[1];
assign T_IAD[0] = !D_DFT_en && D_IAD_di[0];
assign VC_SI[0] = D_DFT_en && D_IAD_di[0];
`else
assign D_IAD_do[15:0] = IAD_do[15:0];
assign IAD_oex = IAD_oe;
assign T_IAD[15:0] = D_IAD_di[15:0];
`endif
`ifdef FD_PM8K
assign PM_bdry_sel = 1'b1;
`else
assign PM_bdry_sel = 1'b0;
`endif
endmodule
|
`include "../include/x_def.v"
/* ---------------------------------------------------------------------- */
/* FTC218x top module ( 02-02-2000 BY LCJ) */
/* ---------------------------------------------------------------------- */
module PINs (/* Input pins : (21) : */
/* glb */ X_RSTn, X_BMODE, X_TMODE[1:0], X_PLLsel[3:0],
X_MMAP,
/* core */ X_PWDn, X_IRQ2n, /*X_IRQ1n, X_IRQ0n,*/
X_IRQL1n, X_IRQE1n, X_IRQE0n, X_BRn,
/* spt */ X_RD0, X_RD1,
/* idma */ X_IRDn, X_IWRn, X_ISn, X_IAL,
/* sice */ X_ICK, X_IMS,
/* -------- Outputs : (27) -------- */
/* glb */ X_CLKO, X_PWDACK,
/* memc */ X_BGn, /*X_BGHn,*/ X_EA[14:0], X_PMSn,
X_DMSn, X_IOSn, /*X_CMSn,*/ X_RDn, X_WRn,
X_ECMSn, X_ECMA_EN,
/* spt */ X_TD0, X_TD1,
/* idma */ X_IACKn,
/* bdma */ X_BMSn,
/* -------- Inouts : (51) -------- */
/* xtal */ X_CLKI, XTAL,
/* emem */ X_ED[15:0],
/* spt */ X_SCLK0, X_RFS0, X_TFS0,
X_SCLK1, X_RFS1, X_TFS1,
/* idma */ X_IAD[15:0],
/* pio */ X_PIO[7:0],
/* sice */ X_ID,
/* ------------------------------------ */
/* Internal signals : */
/* ------------------------------------ */
/* outputs : */
/* glb */ T_RSTn, T_CLKI, T_BMODE, T_PLLsel[3:0],
T_TMODE, T_ED[15:0], T_EA[7:0],
T_selECM,
/* core */ T_PWDn, T_IRQ2n, T_IRQ1n, T_IRQ0n,
T_IRQL1n, T_IRQE1n, T_IRQE0n, T_BRn,
/* spt */ T_RD0, T_RD1, T_SCLK0, T_SCLK1, T_RFS0,
T_TFS0, T_RFS1, T_TFS1,
/* idma */ T_IRDn, T_IWRn, T_ISn, T_IAL, T_IAD[15:0],
/* pio */ T_PIOin[11:0],
/* sice */ T_ICK, T_IMS, T_ID,
/* inputs : */
/* clkc */ CLKO, PWDACK, XTALoffn,
/* emc */ BGn, EA_oe, EA_do[14:0], PMSn, DMSn, BMSn,
IOSn, CMSn, RDn, WRn, ED_oe, ED_do[15:0],
ECMSn, ECMA_EN,
/* spt */ TD0, TD1, SCLK0, ISCLK0, SCLK1, ISCLK1,
RFS0, IRFS0, TFS0, ITFS0, RFS1, IRFS1,
TFS1, ITFS1,
/* idma */ IACKn, IAD_oe, IAD_do[15:0], T_MMAP,
/* pio */ PIO_oe[11:0], PIO_out[11:0],
/* sice */ IDo, IDoe,
/* bdma */ BMcs, BDIR);
input BMcs, BDIR;
input [3:0] X_PLLsel;
input [1:0] X_TMODE;
input X_RSTn, X_BMODE, X_MMAP, X_PWDn, X_IRQ2n,
/*X_IRQ1n, X_IRQ0n,*/ X_IRQL1n, X_IRQE1n, X_IRQE0n,
X_BRn, X_RD0, X_RD1, X_IRDn,
X_IWRn, X_ISn, X_IAL, X_ICK, X_IMS;
inout [14:0] X_EA;
output X_CLKO, X_PWDACK,
X_BGn, X_PMSn, X_DMSn, X_IOSn, /*X_CMSn,*/ X_ECMSn, X_ECMA_EN,
X_RDn, X_WRn, X_TD0, X_TD1, X_IACKn, X_BMSn;
input X_CLKI;
inout XTAL;
inout [15:0] X_ED, X_IAD;
inout [7:0] X_PIO;
inout X_SCLK0, X_SCLK1, X_RFS0, X_TFS0, X_RFS1, X_TFS1,
X_ID;
input [14:0] EA_do;
input [11:0] PIO_oe, PIO_out;
input [15:0] ED_do, IAD_do;
input CLKO, PWDACK, BGn, EA_oe, PMSn, DMSn, BMSn, IOSn,
CMSn, RDn, WRn, TD0, TD1, IACKn, ED_oe, ECMSn, ECMA_EN,
IAD_oe, SCLK0, ISCLK0, SCLK1, ISCLK1, RFS0,
IRFS0, TFS0, ITFS0, RFS1, IRFS1, TFS1, ITFS1,
IDo, IDoe, XTALoffn;
output [15:0] T_ED, T_IAD;
output [7:0] T_EA;
output [11:0] T_PIOin;
output [3:0] T_PLLsel;
output T_RSTn, T_CLKI, T_BMODE, T_MMAP, T_TMODE,
T_PWDn, T_IRQ2n, T_IRQ1n, T_IRQ0n,
T_IRQL1n, T_IRQE1n, T_IRQE0n, T_BRn,
T_RD0, T_RD1, T_IRDn, T_IWRn, T_ISn,
T_IAL, T_ICK, T_IMS, T_SCLK0, T_SCLK1,
T_RFS0, T_TFS0, T_RFS1, T_TFS1, T_ID, T_selECM;
/* reserved pins : */
/* ------ Connecting Crystal (2 (ESD) pads) : ------ */
/* ---------------------------------------------------- */
/* Retarget to 0.18um, by Henry Hu 2001/07/17 */
/* Original(0.35um) Current(0.18um) */
/* XSCIOM5 UROSCAHB */
/* ---------------------------------------------------- */
/* ---------------------------------------------------- */
/* Retarget to 0.13um, by Steven Lin 2001/10/22 */
/* Original(0.18um) Current(0.13um) */
/* UROSCAHB XOSCAHB */
/* ---------------------------------------------------- */
XOSCAHB ckio (.IO(XTAL), .I(X_CLKI), .E(XTALoffn), .O(T_CLKI), .FEB(1'b0), .EB(1'b0), .S0(1'b0), .S1(1'b1));
/* ---------------- inputs : ---------------- */
/* ---------------------------------------------------- */
/* Retarget to 0.18um, by Henry Hu 2001/07/17 */
/* Original(0.35um) Current(0.18um) */
/* XC XFAB */
/* ---------------------------------------------------- */
/* ---------------------------------------------------- */
/* Retarget to 0.13um, by Steven Lin 2001/10/22 */
/* Original(0.18um) Current(0.13um) */
/* XFAB XFMB */
/* ---------------------------------------------------- */
XFMB in1 (.O(T_PLLsel[3]), .I(X_PLLsel[3]), .PU(1'b0), .PD(1'b0), .SMT(1'b0));
XFMB in2 (.O(T_PLLsel[2]), .I(X_PLLsel[2]), .PU(1'b0), .PD(1'b0), .SMT(1'b0));
XFMB in3 (.O(T_PLLsel[1]), .I(X_PLLsel[1]), .PU(1'b0), .PD(1'b0), .SMT(1'b0));
XFMB in4 (.O(T_PLLsel[0]), .I(X_PLLsel[0]), .PU(1'b0), .PD(1'b0), .SMT(1'b0));
XFMB in5 (.O(T_RSTn), .I(X_RSTn), .PU(1'b0), .PD(1'b0), .SMT(1'b0));
XFMB in6 (.O(T_ICK), .I(X_ICK), .PU(1'b0), .PD(1'b0), .SMT(1'b0));
XFMB in7 (.O(T_IMS), .I(X_IMS), .PU(1'b0), .PD(1'b0), .SMT(1'b0));
XFMB in8 (.O(T_BMODE), .I(X_BMODE), .PU(1'b0), .PD(1'b0), .SMT(1'b0));
XFMB in9 (.O(T_TMODE), .I(X_TMODE[0]), .PU(1'b0), .PD(1'b0), .SMT(1'b0));
XFMB in12 (.O(T_selECM), .I(X_TMODE[1]), .PU(1'b0), .PD(1'b0), .SMT(1'b0));
XFMB in10 (.O(T_PWDn), .I(X_PWDn), .PU(1'b0), .PD(1'b0), .SMT(1'b0));
XFMB in11 (.O(T_IRQ2n), .I(X_IRQ2n), .PU(1'b0), .PD(1'b0), .SMT(1'b0));
XFMB in14 (.O(T_IRQL1n), .I(X_IRQL1n), .PU(1'b0), .PD(1'b0), .SMT(1'b0));
XFMB in15 (.O(T_IRQE1n), .I(X_IRQE1n), .PU(1'b0), .PD(1'b0), .SMT(1'b0));
XFMB in16 (.O(T_IRQE0n), .I(X_IRQE0n), .PU(1'b0), .PD(1'b0), .SMT(1'b0));
XFMB in17 (.O(T_BRn), .I(X_BRn), .PU(1'b0), .PD(1'b0), .SMT(1'b0));
XFMB in18 (.O(T_RD0), .I(X_RD0), .PU(1'b0), .PD(1'b0), .SMT(1'b0));
XFMB in19 (.O(T_RD1), .I(X_RD1), .PU(1'b0), .PD(1'b0), .SMT(1'b0));
XFMB in20 (.O(T_ISn), .I(X_ISn), .PU(1'b0), .PD(1'b0), .SMT(1'b0));
XFMB in21 (.O(T_IRDn), .I(X_IRDn), .PU(1'b0), .PD(1'b0), .SMT(1'b0));
XFMB in22 (.O(T_IWRn), .I(X_IWRn), .PU(1'b0), .PD(1'b0), .SMT(1'b0));
XFMB in23 (.O(T_IAL), .I(X_IAL), .PU(1'b0), .PD(1'b0), .SMT(1'b0));
XFMB in24 (.O(T_MMAP), .I(X_MMAP), .PU(1'b0), .PD(1'b0), .SMT(1'b0));
INVGSS uu12 (.O(T_IRQ1n), .I(1'b0));
INVGSS uu13 (.O(T_IRQ0n), .I(1'b0));
/* ---------------- outputs : ---------------- */
BUFJSS uu0 (.O(BGnx), .I(BGn));
/* ---------------------------------------------------- */
/* Retarget to 0.18um, by Henry Hu 2001/07/17 */
/* Original(0.35um) Current(0.18um) */
/* YC04T YFA2GSB */
/* YC04A YFA2GSB */
/* ---------------------------------------------------- */
/* ---------------------------------------------------- */
/* Retarget to 0.13um, by Steven Lin 2001/10/22 */
/* Original(0.18um) Current(0.13um) */
/* YFA2GSB YFA28SB */
/* ---------------------------------------------------- */
YFA28SB out1 (.O(X_CLKO), .I(CLKO), .E(1'b1), .E2(1'b1), .E4(1'b0), .SR(1'b0));
YFA28SB out2 (.O(X_PWDACK), .I(PWDACK), .E(1'b1), .E2(1'b1), .E4(1'b0), .SR(1'b0));
YFA28SB out3 (.O(X_BGn), .I(BGn), .E(1'b1), .E2(1'b1), .E4(1'b0), .SR(1'b0));
YFA28SB out4 (.O(X_EA[14]), .I(EA_do[14]), .E(BGnx), .E2(1'b1), .E4(1'b0), .SR(1'b0));
YFA28SB out5 (.O(X_EA[13]), .I(EA_do[13]), .E(BGnx), .E2(1'b1), .E4(1'b0), .SR(1'b0));
YFA28SB out6 (.O(X_EA[12]), .I(EA_do[12]), .E(BGnx), .E2(1'b1), .E4(1'b0), .SR(1'b0));
YFA28SB out7 (.O(X_EA[11]), .I(EA_do[11]), .E(BGnx), .E2(1'b1), .E4(1'b0), .SR(1'b0));
YFA28SB out8 (.O(X_EA[10]), .I(EA_do[10]), .E(BGnx), .E2(1'b1), .E4(1'b0), .SR(1'b0));
YFA28SB out9 (.O(X_EA[9]), .I(EA_do[9]), .E(BGnx), .E2(1'b1), .E4(1'b0), .SR(1'b0));
YFA28SB out10 (.O(X_EA[8]), .I(EA_do[8]), .E(BGnx), .E2(1'b1), .E4(1'b0), .SR(1'b0));
YFA28SB out19 (.O(X_PMSn), .I(PMSn), .E(BGnx), .E2(1'b1), .E4(1'b0), .SR(1'b0));
YFA28SB out20 (.O(X_DMSn), .I(DMSn), .E(BGnx), .E2(1'b1), .E4(1'b0), .SR(1'b0));
YFA28SB out30 (.O(X_BMSn), .I(BMSn), .E(BGnx), .E2(1'b1), .E4(1'b0), .SR(1'b0));
YFA28SB out21 (.O(X_IOSn), .I(IOSn), .E(BGnx), .E2(1'b1), .E4(1'b0), .SR(1'b0));
YFA28SB out23 (.O(X_RDn), .I(RDn), .E(BGnx), .E2(1'b1), .E4(1'b0), .SR(1'b0));
YFA28SB out24 (.O(X_WRn), .I(WRn), .E(BGnx), .E2(1'b1), .E4(1'b0), .SR(1'b0));
YFA28SB out25 (.O(X_TD0), .I(TD0), .E(1'b1), .E2(1'b1), .E4(1'b0), .SR(1'b0));
YFA28SB out26 (.O(X_TD1), .I(TD1), .E(1'b1), .E2(1'b1), .E4(1'b0), .SR(1'b0));
YFA28SB out27 (.O(X_IACKn), .I(IACKn), .E(1'b1), .E2(1'b1), .E4(1'b0), .SR(1'b0));
YFA28SB out28 (.O(X_ECMSn), .I(ECMSn), .E(BGnx), .E2(1'b1), .E4(1'b0), .SR(1'b0));
YFA28SB out29 (.O(X_ECMA_EN), .I(ECMA_EN), .E(BGnx), .E2(1'b1), .E4(1'b0), .SR(1'b0));
/* ---------------- inouts : ---------------- */
BUFJSS uu2 (.O(IAD_oex), .I(IAD_oe));
BUFJSS uu3 (.O(EA_oex), .I(EA_oe));
OR2HSS xeds1 (.O(XED_S1), .I1(ED_oe), .I2(BMcs));
AO12JSS xeds2 (.O(XED_S2), .A1(ED_oe), .B1(BMcs), .B2(BDIR));
/* ---------------------------------------------------- */
/* Retarget to 0.18um, by Henry Hu 2001/07/17 */
/* Original(0.35um) Current(0.18um) */
/* ZCC04A ZFA2GSB */
/* ---------------------------------------------------- */
/* ---------------------------------------------------- */
/* Retarget to 0.13um, by Steven Lin 2001/10/22 */
/* Original(0.18um) Current(0.13um) */
/* ZFA2GSB ZFMA28SB */
/* ---------------------------------------------------- */
ZFMA28SB io1 (.IO(X_ED[15]), .O(T_ED[15]), .I(ED_do[15]), .E(ED_oe), .E4(1'b0), .E2(1'b1), .SMT(1'b0), .PU(1'b0), .PD(1'b0), .SR(1'b0));
ZFMA28SB io2 (.IO(X_ED[14]), .O(T_ED[14]), .I(ED_do[14]), .E(XED_S1), .E4(1'b0), .E2(1'b1), .SMT(1'b0), .PU(1'b0), .PD(1'b0), .SR(1'b0));
ZFMA28SB io3 (.IO(X_ED[13]), .O(T_ED[13]), .I(ED_do[13]), .E(XED_S1), .E4(1'b0), .E2(1'b1), .SMT(1'b0), .PU(1'b0), .PD(1'b0), .SR(1'b0));
ZFMA28SB io4 (.IO(X_ED[12]), .O(T_ED[12]), .I(ED_do[12]), .E(XED_S1), .E4(1'b0), .E2(1'b1), .SMT(1'b0), .PU(1'b0), .PD(1'b0), .SR(1'b0));
ZFMA28SB io5 (.IO(X_ED[11]), .O(T_ED[11]), .I(ED_do[11]), .E(XED_S1), .E4(1'b0), .E2(1'b1), .SMT(1'b0), .PU(1'b0), .PD(1'b0), .SR(1'b0));
ZFMA28SB io6 (.IO(X_ED[10]), .O(T_ED[10]), .I(ED_do[10]), .E(XED_S1), .E4(1'b0), .E2(1'b1), .SMT(1'b0), .PU(1'b0), .PD(1'b0), .SR(1'b0));
ZFMA28SB io7 (.IO(X_ED[9]), .O(T_ED[9]), .I(ED_do[9]), .E(XED_S1), .E4(1'b0), .E2(1'b1), .SMT(1'b0), .PU(1'b0), .PD(1'b0), .SR(1'b0));
ZFMA28SB io8 (.IO(X_ED[8]), .O(T_ED[8]), .I(ED_do[8]), .E(XED_S1), .E4(1'b0), .E2(1'b1), .SMT(1'b0), .PU(1'b0), .PD(1'b0), .SR(1'b0));
ZFMA28SB io9 (.IO(X_ED[7]), .O(T_ED[7]), .I(ED_do[7]), .E(XED_S2), .E4(1'b0), .E2(1'b1), .SMT(1'b0), .PU(1'b0), .PD(1'b0), .SR(1'b0));
ZFMA28SB io10 (.IO(X_ED[6]), .O(T_ED[6]), .I(ED_do[6]), .E(XED_S2), .E4(1'b0), .E2(1'b1), .SMT(1'b0), .PU(1'b0), .PD(1'b0), .SR(1'b0));
ZFMA28SB io11 (.IO(X_ED[5]), .O(T_ED[5]), .I(ED_do[5]), .E(XED_S2), .E4(1'b0), .E2(1'b1), .SMT(1'b0), .PU(1'b0), .PD(1'b0), .SR(1'b0));
ZFMA28SB io12 (.IO(X_ED[4]), .O(T_ED[4]), .I(ED_do[4]), .E(XED_S2), .E4(1'b0), .E2(1'b1), .SMT(1'b0), .PU(1'b0), .PD(1'b0), .SR(1'b0));
ZFMA28SB io13 (.IO(X_ED[3]), .O(T_ED[3]), .I(ED_do[3]), .E(XED_S2), .E4(1'b0), .E2(1'b1), .SMT(1'b0), .PU(1'b0), .PD(1'b0), .SR(1'b0));
ZFMA28SB io14 (.IO(X_ED[2]), .O(T_ED[2]), .I(ED_do[2]), .E(XED_S2), .E4(1'b0), .E2(1'b1), .SMT(1'b0), .PU(1'b0), .PD(1'b0), .SR(1'b0));
ZFMA28SB io15 (.IO(X_ED[1]), .O(T_ED[1]), .I(ED_do[1]), .E(XED_S2), .E4(1'b0), .E2(1'b1), .SMT(1'b0), .PU(1'b0), .PD(1'b0), .SR(1'b0));
ZFMA28SB io16 (.IO(X_ED[0]), .O(T_ED[0]), .I(ED_do[0]), .E(XED_S2), .E4(1'b0), .E2(1'b1), .SMT(1'b0), .PU(1'b0), .PD(1'b0), .SR(1'b0));
ZFMA28SB io17 (.IO(X_SCLK0), .O(T_SCLK0), .I(SCLK0), .E(ISCLK0), .E4(1'b0), .E2(1'b1), .SMT(1'b0), .PU(1'b0), .PD(1'b0), .SR(1'b0));
ZFMA28SB io18 (.IO(X_RFS0), .O(T_RFS0), .I(RFS0), .E(IRFS0), .E4(1'b0), .E2(1'b1), .SMT(1'b0), .PU(1'b0), .PD(1'b0), .SR(1'b0));
ZFMA28SB io19 (.IO(X_TFS0), .O(T_TFS0), .I(TFS0), .E(ITFS0), .E4(1'b0), .E2(1'b1), .SMT(1'b0), .PU(1'b0), .PD(1'b0), .SR(1'b0));
ZFMA28SB io20 (.IO(X_SCLK1), .O(T_SCLK1), .I(SCLK1), .E(ISCLK1), .E4(1'b0), .E2(1'b1), .SMT(1'b0), .PU(1'b0), .PD(1'b0), .SR(1'b0));
ZFMA28SB io21 (.IO(X_RFS1), .O(T_RFS1), .I(RFS1), .E(IRFS1), .E4(1'b0), .E2(1'b1), .SMT(1'b0), .PU(1'b0), .PD(1'b0), .SR(1'b0));
ZFMA28SB io22 (.IO(X_TFS1), .O(T_TFS1), .I(TFS1), .E(ITFS1), .E4(1'b0), .E2(1'b1), .SMT(1'b0), .PU(1'b0), .PD(1'b0), .SR(1'b0));
ZFMA28SB io23 (.IO(X_IAD[15]), .O(T_IAD[15]), .I(IAD_do[15]), .E(IAD_oex), .E4(1'b0), .E2(1'b1), .SMT(1'b0), .PU(1'b0), .PD(1'b0), .SR(1'b0));
ZFMA28SB io24 (.IO(X_IAD[14]), .O(T_IAD[14]), .I(IAD_do[14]), .E(IAD_oex), .E4(1'b0), .E2(1'b1), .SMT(1'b0), .PU(1'b0), .PD(1'b0), .SR(1'b0));
ZFMA28SB io25 (.IO(X_IAD[13]), .O(T_IAD[13]), .I(IAD_do[13]), .E(IAD_oex), .E4(1'b0), .E2(1'b1), .SMT(1'b0), .PU(1'b0), .PD(1'b0), .SR(1'b0));
ZFMA28SB io26 (.IO(X_IAD[12]), .O(T_IAD[12]), .I(IAD_do[12]), .E(IAD_oex), .E4(1'b0), .E2(1'b1), .SMT(1'b0), .PU(1'b0), .PD(1'b0), .SR(1'b0));
ZFMA28SB io27 (.IO(X_IAD[11]), .O(T_IAD[11]), .I(IAD_do[11]), .E(IAD_oex), .E4(1'b0), .E2(1'b1), .SMT(1'b0), .PU(1'b0), .PD(1'b0), .SR(1'b0));
ZFMA28SB io28 (.IO(X_IAD[10]), .O(T_IAD[10]), .I(IAD_do[10]), .E(IAD_oex), .E4(1'b0), .E2(1'b1), .SMT(1'b0), .PU(1'b0), .PD(1'b0), .SR(1'b0));
ZFMA28SB io29 (.IO(X_IAD[9]), .O(T_IAD[9]), .I(IAD_do[9]), .E(IAD_oex), .E4(1'b0), .E2(1'b1), .SMT(1'b0), .PU(1'b0), .PD(1'b0), .SR(1'b0));
ZFMA28SB io30 (.IO(X_IAD[8]), .O(T_IAD[8]), .I(IAD_do[8]), .E(IAD_oex), .E4(1'b0), .E2(1'b1), .SMT(1'b0), .PU(1'b0), .PD(1'b0), .SR(1'b0));
ZFMA28SB io31 (.IO(X_IAD[7]), .O(T_IAD[7]), .I(IAD_do[7]), .E(IAD_oex), .E4(1'b0), .E2(1'b1), .SMT(1'b0), .PU(1'b0), .PD(1'b0), .SR(1'b0));
ZFMA28SB io32 (.IO(X_IAD[6]), .O(T_IAD[6]), .I(IAD_do[6]), .E(IAD_oex), .E4(1'b0), .E2(1'b1), .SMT(1'b0), .PU(1'b0), .PD(1'b0), .SR(1'b0));
ZFMA28SB io33 (.IO(X_IAD[5]), .O(T_IAD[5]), .I(IAD_do[5]), .E(IAD_oex), .E4(1'b0), .E2(1'b1), .SMT(1'b0), .PU(1'b0), .PD(1'b0), .SR(1'b0));
ZFMA28SB io34 (.IO(X_IAD[4]), .O(T_IAD[4]), .I(IAD_do[4]), .E(IAD_oex), .E4(1'b0), .E2(1'b1), .SMT(1'b0), .PU(1'b0), .PD(1'b0), .SR(1'b0));
ZFMA28SB io35 (.IO(X_IAD[3]), .O(T_IAD[3]), .I(IAD_do[3]), .E(IAD_oex), .E4(1'b0), .E2(1'b1), .SMT(1'b0), .PU(1'b0), .PD(1'b0), .SR(1'b0));
ZFMA28SB io36 (.IO(X_IAD[2]), .O(T_IAD[2]), .I(IAD_do[2]), .E(IAD_oex), .E4(1'b0), .E2(1'b1), .SMT(1'b0), .PU(1'b0), .PD(1'b0), .SR(1'b0));
ZFMA28SB io37 (.IO(X_IAD[1]), .O(T_IAD[1]), .I(IAD_do[1]), .E(IAD_oex), .E4(1'b0), .E2(1'b1), .SMT(1'b0), .PU(1'b0), .PD(1'b0), .SR(1'b0));
ZFMA28SB io38 (.IO(X_IAD[0]), .O(T_IAD[0]), .I(IAD_do[0]), .E(IAD_oex), .E4(1'b0), .E2(1'b1), .SMT(1'b0), .PU(1'b0), .PD(1'b0), .SR(1'b0));
ZFMA28SB io39 (.IO(X_ID), .O(T_ID), .I(IDo), .E(IDoe), .E4(1'b0), .E2(1'b1), .SMT(1'b0), .PU(1'b0), .PD(1'b0), .SR(1'b0));
/*
ZFMA28SB io40 (.IO(X_PIO[11]), .O(T_PIOin[11]), .I(PIO_out[11]), .E(PIO_oe[11]), .E4(1'b0), .E2(1'b1), .SMT(1'b0), .PU(1'b0), .PD(1'b0), .SR(1'b0));
ZFMA28SB io41 (.IO(X_PIO[10]), .O(T_PIOin[10]), .I(PIO_out[10]), .E(PIO_oe[10]), .E4(1'b0), .E2(1'b1), .SMT(1'b0), .PU(1'b0), .PD(1'b0), .SR(1'b0));
ZFMA28SB io42 (.IO(X_PIO[9]), .O(T_PIOin[9]), .I(PIO_out[9]), .E(PIO_oe[9]), .E4(1'b0), .E2(1'b1), .SMT(1'b0), .PU(1'b0), .PD(1'b0), .SR(1'b0));
ZFMA28SB io43 (.IO(X_PIO[8]), .O(T_PIOin[8]), .I(PIO_out[8]), .E(PIO_oe[8]), .E4(1'b0), .E2(1'b1), .SMT(1'b0), .PU(1'b0), .PD(1'b0), .SR(1'b0));
*/
INVHSS uu40 (.O(T_PIOin[11]), .I(1'b1));
INVHSS uu41 (.O(T_PIOin[10]), .I(1'b1));
INVHSS uu42 (.O(T_PIOin[9]), .I(1'b1));
INVHSS uu43 (.O(T_PIOin[8]), .I(1'b1));
ZFMA28SB io44 (.IO(X_PIO[7]), .O(T_PIOin[7]), .I(PIO_out[7]), .E(PIO_oe[7]), .E4(1'b0), .E2(1'b1), .SMT(1'b0), .PU(1'b0), .PD(1'b0), .SR(1'b0));
ZFMA28SB io45 (.IO(X_PIO[6]), .O(T_PIOin[6]), .I(PIO_out[6]), .E(PIO_oe[6]), .E4(1'b0), .E2(1'b1), .SMT(1'b0), .PU(1'b0), .PD(1'b0), .SR(1'b0));
ZFMA28SB io46 (.IO(X_PIO[5]), .O(T_PIOin[5]), .I(PIO_out[5]), .E(PIO_oe[5]), .E4(1'b0), .E2(1'b1), .SMT(1'b0), .PU(1'b0), .PD(1'b0), .SR(1'b0));
ZFMA28SB io47 (.IO(X_PIO[4]), .O(T_PIOin[4]), .I(PIO_out[4]), .E(PIO_oe[4]), .E4(1'b0), .E2(1'b1), .SMT(1'b0), .PU(1'b0), .PD(1'b0), .SR(1'b0));
ZFMA28SB io48 (.IO(X_PIO[3]), .O(T_PIOin[3]), .I(PIO_out[3]), .E(PIO_oe[3]), .E4(1'b0), .E2(1'b1), .SMT(1'b0), .PU(1'b0), .PD(1'b0), .SR(1'b0));
ZFMA28SB io49 (.IO(X_PIO[2]), .O(T_PIOin[2]), .I(PIO_out[2]), .E(PIO_oe[2]), .E4(1'b0), .E2(1'b1), .SMT(1'b0), .PU(1'b0), .PD(1'b0), .SR(1'b0));
ZFMA28SB io50 (.IO(X_PIO[1]), .O(T_PIOin[1]), .I(PIO_out[1]), .E(PIO_oe[1]), .E4(1'b0), .E2(1'b1), .SMT(1'b0), .PU(1'b0), .PD(1'b0), .SR(1'b0));
ZFMA28SB io51 (.IO(X_PIO[0]), .O(T_PIOin[0]), .I(PIO_out[0]), .E(PIO_oe[0]), .E4(1'b0), .E2(1'b1), .SMT(1'b0), .PU(1'b0), .PD(1'b0), .SR(1'b0));
ZFMA28SB io52 (.IO(X_EA[7]), .O(T_EA[7]), .I(EA_do[7]), .E(EA_oex), .E4(1'b0), .E2(1'b1), .SMT(1'b0), .PU(1'b0), .PD(1'b0), .SR(1'b0));
ZFMA28SB io53 (.IO(X_EA[6]), .O(T_EA[6]), .I(EA_do[6]), .E(EA_oex), .E4(1'b0), .E2(1'b1), .SMT(1'b0), .PU(1'b0), .PD(1'b0), .SR(1'b0));
ZFMA28SB io54 (.IO(X_EA[5]), .O(T_EA[5]), .I(EA_do[5]), .E(EA_oex), .E4(1'b0), .E2(1'b1), .SMT(1'b0), .PU(1'b0), .PD(1'b0), .SR(1'b0));
ZFMA28SB io55 (.IO(X_EA[4]), .O(T_EA[4]), .I(EA_do[4]), .E(EA_oex), .E4(1'b0), .E2(1'b1), .SMT(1'b0), .PU(1'b0), .PD(1'b0), .SR(1'b0));
ZFMA28SB io56 (.IO(X_EA[3]), .O(T_EA[3]), .I(EA_do[3]), .E(EA_oex), .E4(1'b0), .E2(1'b1), .SMT(1'b0), .PU(1'b0), .PD(1'b0), .SR(1'b0));
ZFMA28SB io57 (.IO(X_EA[2]), .O(T_EA[2]), .I(EA_do[2]), .E(EA_oex), .E4(1'b0), .E2(1'b1), .SMT(1'b0), .PU(1'b0), .PD(1'b0), .SR(1'b0));
ZFMA28SB io58 (.IO(X_EA[1]), .O(T_EA[1]), .I(EA_do[1]), .E(EA_oex), .E4(1'b0), .E2(1'b1), .SMT(1'b0), .PU(1'b0), .PD(1'b0), .SR(1'b0));
ZFMA28SB io59 (.IO(X_EA[0]), .O(T_EA[0]), .I(EA_do[0]), .E(EA_oex), .E4(1'b0), .E2(1'b1), .SMT(1'b0), .PU(1'b0), .PD(1'b0), .SR(1'b0));
endmodule
|
`include "../include/x_def.v"
/* ---------------------------------------------------------------------- */
/* FTC218x top module ( 02-02-2000 BY LCJ) */
/* ---------------------------------------------------------------------- */
module PINs (/* Input pins : (21) : */
/* glb */ X_RSTn, X_ICE_RSTn, X_BMODE, X_TMODE[1:0],
X_PLLsel[3:0], X_MMAP, X_GOICE,
/* core */ X_PWDn, X_IRQ2n, /*X_IRQ1n, X_IRQ0n,*/
X_IRQL1n, X_IRQE1n, X_IRQE0n, X_BRn,
/* spt */ X_RD0, X_RD1,
/* idma */ X_IRDn, X_IWRn, X_ISn, X_IAL,
/* sice */ X_ICK, X_IMS,
/* -------- Outputs : (27) -------- */
/* glb */ X_CLKO, X_PWDACK,
/* memc */ X_BGn, /*X_BGHn, X_EA[14:0],*/
X_EA_U[14:8], X_EA[7:0], X_PMSn,
X_DMSn, X_IOSn, /*X_CMSn,*/ X_RDn, X_WRn,
X_ECMSn, X_ECMA_EN,
/* spt */ X_TD0, X_TD1,
/* idma */ X_IACKn,
/* bdma */ X_BMSn,
/* -------- Inouts : (51) -------- */
/* xtal */ X_CLKI, XTAL,
/* emem */ X_ED[15:0],
/* spt */ X_SCLK0, X_RFS0, X_TFS0,
X_SCLK1, X_RFS1, X_TFS1,
/* idma */ X_IAD[15:0],
/* pio */ X_PIO[7:0],
/* sice */ X_ID,
/* ------------------------------------ */
/* Internal signals : */
/* ------------------------------------ */
/* outputs : */
/* glb */ T_RSTn, T_CLKI, T_BMODE, T_PLLsel[3:0],
T_TMODE, T_ED[15:0], T_EA[7:0],
T_selECM, T_GOICE,
/* core */ T_PWDn, T_IRQ2n, T_IRQ1n, T_IRQ0n,
T_IRQL1n, T_IRQE1n, T_IRQE0n, T_BRn,
/* spt */ T_RD0, T_RD1, T_SCLK0, T_SCLK1, T_RFS0,
T_TFS0, T_RFS1, T_TFS1,
/* idma */ T_IRDn, T_IWRn, T_ISn, T_IAL, T_IAD[15:0],
/* pio */ T_PIOin[11:0],
/* sice */ T_ICK, T_IMS, T_ID,
/* inputs : */
/* clkc */ CLKO, PWDACK, XTALoffn,
/* emc */ BGn, EA_oe, EA_do[14:0], PMSn, DMSn, BMSn,
IOSn, CMSn, RDn, WRn, ED_oe, ED_do[15:0],
ECMSn, ECMA_EN,
/* spt */ TD0, TD1, SCLK0, ISCLK0, SCLK1, ISCLK1,
RFS0, IRFS0, TFS0, ITFS0, RFS1, IRFS1,
TFS1, ITFS1,
/* idma */ IACKn, IAD_oe, IAD_do[15:0], T_MMAP,
/* pio */ PIO_oe[11:0], PIO_out[11:0],
/* sice */ IDo, IDoe,
/* bdma */ BMcs, BDIR);
input BMcs, BDIR;
input [3:0] X_PLLsel;
input [1:0] X_TMODE;
input X_RSTn, X_BMODE, X_MMAP, X_PWDn, X_IRQ2n,
/*X_IRQ1n, X_IRQ0n,*/ X_IRQL1n, X_IRQE1n, X_IRQE0n,
X_BRn, X_RD0, X_RD1, X_IRDn, X_GOICE, X_ICE_RSTn,
X_IWRn, X_ISn, X_IAL, X_ICK, X_IMS;
output [14:8] X_EA_U;
inout [7:0] X_EA;
output X_CLKO, X_PWDACK,
X_BGn, X_PMSn, X_DMSn, X_IOSn, /*X_CMSn,*/ X_ECMSn, X_ECMA_EN,
X_RDn, X_WRn, X_TD0, X_TD1, X_IACKn, X_BMSn;
input X_CLKI;
inout XTAL;
inout [15:0] X_ED, X_IAD;
inout [7:0] X_PIO;
inout X_SCLK0, X_SCLK1, X_RFS0, X_TFS0, X_RFS1, X_TFS1,
X_ID;
input [14:0] EA_do;
input [11:0] PIO_oe, PIO_out;
input [15:0] ED_do, IAD_do;
input CLKO, PWDACK, BGn, EA_oe, PMSn, DMSn, BMSn, IOSn,
CMSn, RDn, WRn, TD0, TD1, IACKn, ED_oe, ECMSn, ECMA_EN,
IAD_oe, SCLK0, ISCLK0, SCLK1, ISCLK1, RFS0,
IRFS0, TFS0, ITFS0, RFS1, IRFS1, TFS1, ITFS1,
IDo, IDoe, XTALoffn;
output [15:0] T_ED, T_IAD;
output [7:0] T_EA;
output [11:0] T_PIOin;
output [3:0] T_PLLsel;
output T_RSTn, T_CLKI, T_BMODE, T_MMAP, T_TMODE,
T_PWDn, T_IRQ2n, T_IRQ1n, T_IRQ0n,
T_IRQL1n, T_IRQE1n, T_IRQE0n, T_BRn,
T_RD0, T_RD1, T_IRDn, T_IWRn, T_ISn,
T_IAL, T_ICK, T_IMS, T_SCLK0, T_SCLK1, T_GOICE,
T_RFS0, T_TFS0, T_RFS1, T_TFS1, T_ID, T_selECM;
/* reserved pins : */
/* ------ Connecting Crystal (2 (ESD) pads) : ------ */
UROSCAHB ckio (.IO(XTAL), .I(X_CLKI), .E(XTALoffn), .O(T_CLKI), .FEB(1'b0), .EB(1'b0), .S0(1'b1), .S1(1'b0));
/* ---------------- inputs : ---------------- */
XFAB in1 (.O(T_PLLsel[3]), .I(X_PLLsel[3]), .PU(1'b0), .PD(1'b0), .SMT(1'b0));
XFAB in2 (.O(T_PLLsel[2]), .I(X_PLLsel[2]), .PU(1'b0), .PD(1'b0), .SMT(1'b0));
XFAB in3 (.O(T_PLLsel[1]), .I(X_PLLsel[1]), .PU(1'b0), .PD(1'b0), .SMT(1'b0));
XFAB in4 (.O(T_PLLsel[0]), .I(X_PLLsel[0]), .PU(1'b0), .PD(1'b0), .SMT(1'b0));
XFAB in5a (.O(T_RSTn_1), .I(X_RSTn), .PU(1'b1), .PD(1'b0), .SMT(1'b0));
XFAB in5b (.O(T_RSTn_2), .I(X_ICE_RSTn), .PU(1'b1), .PD(1'b0), .SMT(1'b0));
XFAB in6 (.O(T_ICK), .I(X_ICK), .PU(1'b0), .PD(1'b0), .SMT(1'b0));
XFAB in7 (.O(T_IMS), .I(X_IMS), .PU(1'b0), .PD(1'b0), .SMT(1'b0));
XFAB in8 (.O(T_BMODE), .I(X_BMODE), .PU(1'b0), .PD(1'b0), .SMT(1'b0));
XFAB in9 (.O(T_TMODE), .I(X_TMODE[0]), .PU(1'b0), .PD(1'b0), .SMT(1'b0));
XFAB in12 (.O(T_selECM), .I(X_TMODE[1]), .PU(1'b0), .PD(1'b0), .SMT(1'b0));
XFAB in10 (.O(T_PWDn), .I(X_PWDn), .PU(1'b1), .PD(1'b0), .SMT(1'b0));
XFAB in11 (.O(T_IRQ2n), .I(X_IRQ2n), .PU(1'b1), .PD(1'b0), .SMT(1'b0));
XFAB in14 (.O(T_IRQL1n), .I(X_IRQL1n), .PU(1'b1), .PD(1'b0), .SMT(1'b0));
XFAB in15 (.O(T_IRQE1n), .I(X_IRQE1n), .PU(1'b1), .PD(1'b0), .SMT(1'b0));
XFAB in16 (.O(T_IRQE0n), .I(X_IRQE0n), .PU(1'b1), .PD(1'b0), .SMT(1'b0));
XFAB in17 (.O(T_BRn), .I(X_BRn), .PU(1'b1), .PD(1'b0), .SMT(1'b0));
XFAB in18 (.O(T_RD0), .I(X_RD0), .PU(1'b0), .PD(1'b0), .SMT(1'b0));
XFAB in19 (.O(T_RD1), .I(X_RD1), .PU(1'b0), .PD(1'b0), .SMT(1'b0));
XFAB in20 (.O(T_ISn), .I(X_ISn), .PU(1'b0), .PD(1'b0), .SMT(1'b0));
XFAB in21 (.O(T_IRDn), .I(X_IRDn), .PU(1'b1), .PD(1'b0), .SMT(1'b0));
XFAB in22 (.O(T_IWRn), .I(X_IWRn), .PU(1'b1), .PD(1'b0), .SMT(1'b0));
XFAB in23 (.O(T_IAL), .I(X_IAL), .PU(1'b0), .PD(1'b1), .SMT(1'b0));
XFAB in24 (.O(T_MMAP), .I(X_MMAP), .PU(1'b0), .PD(1'b0), .SMT(1'b0));
XFAB in25 (.O(T_GOICE), .I(X_GOICE), .PU(1'b0), .PD(1'b1), .SMT(1'b0));
INV1 uu12 (.O(T_IRQ1n), .I(1'b0));
INV1 uu13 (.O(T_IRQ0n), .I(1'b0));
AN2P rstn (.O(T_RSTn), .I1(T_RSTn_1), .I2(T_RSTn_2));
/* ---------------- outputs : ---------------- */
BUF4 uu0 (.O(BGnx), .I(BGn));
/* ---------------------------------------------------- */
/* Retarget to 0.18um, by Henry Hu 2001/07/17 */
/* Original(0.35um) Current(0.18um) */
/* YC04T YFA2GSB */
/* YC04A YFA2GSB */
/* ---------------------------------------------------- */
YFA2GSB out1 (.O(X_CLKO), .I(CLKO), .E(1'b1), .E2(1'b1), .E4(1'b1), .E8(1'b0), .SR(1'b0));
YFA2GSB out2 (.O(X_PWDACK), .I(PWDACK), .E(1'b1), .E2(1'b1), .E4(1'b1), .E8(1'b0), .SR(1'b0));
YFA2GSB out3 (.O(X_BGn), .I(BGn), .E(1'b1), .E2(1'b1), .E4(1'b1), .E8(1'b0), .SR(1'b0));
YFA2GSB out4 (.O(X_EA_U[14]), .I(EA_do[14]), .E(BGnx), .E2(1'b1), .E4(1'b1), .E8(1'b0), .SR(1'b0));
YFA2GSB out5 (.O(X_EA_U[13]), .I(EA_do[13]), .E(BGnx), .E2(1'b1), .E4(1'b1), .E8(1'b0), .SR(1'b0));
YFA2GSB out6 (.O(X_EA_U[12]), .I(EA_do[12]), .E(BGnx), .E2(1'b1), .E4(1'b1), .E8(1'b0), .SR(1'b0));
YFA2GSB out7 (.O(X_EA_U[11]), .I(EA_do[11]), .E(BGnx), .E2(1'b1), .E4(1'b1), .E8(1'b0), .SR(1'b0));
YFA2GSB out8 (.O(X_EA_U[10]), .I(EA_do[10]), .E(BGnx), .E2(1'b1), .E4(1'b1), .E8(1'b0), .SR(1'b0));
YFA2GSB out9 (.O(X_EA_U[9]), .I(EA_do[9]), .E(BGnx), .E2(1'b1), .E4(1'b1), .E8(1'b0), .SR(1'b0));
YFA2GSB out10 (.O(X_EA_U[8]), .I(EA_do[8]), .E(BGnx), .E2(1'b1), .E4(1'b1), .E8(1'b0), .SR(1'b0));
YFA2GSB out19 (.O(X_PMSn), .I(PMSn), .E(BGnx), .E2(1'b1), .E4(1'b1), .E8(1'b0), .SR(1'b0));
YFA2GSB out20 (.O(X_DMSn), .I(DMSn), .E(BGnx), .E2(1'b1), .E4(1'b1), .E8(1'b0), .SR(1'b0));
YFA2GSB out30 (.O(X_BMSn), .I(BMSn), .E(BGnx), .E2(1'b1), .E4(1'b1), .E8(1'b0), .SR(1'b0));
YFA2GSB out21 (.O(X_IOSn), .I(IOSn), .E(BGnx), .E2(1'b1), .E4(1'b1), .E8(1'b0), .SR(1'b0));
YFA2GSB out23 (.O(X_RDn), .I(RDn), .E(BGnx), .E2(1'b1), .E4(1'b1), .E8(1'b0), .SR(1'b0));
YFA2GSB out24 (.O(X_WRn), .I(WRn), .E(BGnx), .E2(1'b1), .E4(1'b1), .E8(1'b0), .SR(1'b0));
YFA2GSB out25 (.O(X_TD0), .I(TD0), .E(1'b1), .E2(1'b1), .E4(1'b1), .E8(1'b0), .SR(1'b0));
YFA2GSB out26 (.O(X_TD1), .I(TD1), .E(1'b1), .E2(1'b1), .E4(1'b1), .E8(1'b0), .SR(1'b0));
YFA2GSB out27 (.O(X_IACKn), .I(IACKn), .E(1'b1), .E2(1'b1), .E4(1'b1), .E8(1'b0), .SR(1'b0));
YFA2GSB out28 (.O(X_ECMSn), .I(ECMSn), .E(BGnx), .E2(1'b1), .E4(1'b1), .E8(1'b0), .SR(1'b0));
YFA2GSB out29 (.O(X_ECMA_EN), .I(ECMA_EN), .E(BGnx), .E2(1'b1), .E4(1'b1), .E8(1'b0), .SR(1'b0));
/* ---------------- inouts : ---------------- */
BUF4 uu2 (.O(IAD_oex), .I(IAD_oe));
BUF4 uu3 (.O(EA_oex), .I(EA_oe));
OR2P xeds1 (.O(XED_S1), .I1(ED_oe), .I2(BMcs));
AO12P xeds2 (.O(XED_S2), .A1(ED_oe), .B1(BMcs), .B2(BDIR));
/* ---------------------------------------------------- */
/* Retarget to 0.18um, by Henry Hu 2001/07/17 */
/* Original(0.35um) Current(0.18um) */
/* ZCC04A ZFA2GSB */
/* ---------------------------------------------------- */
ZFA2GSB io1 (.IO(X_ED[15]), .O(T_ED[15]), .I(ED_do[15]), .E(ED_oe), .E8(1'b0), .E4(1'b1), .E2(1'b1), .SMT(1'b0), .PU(1'b0), .PD(1'b0), .SR(1'b0));
ZFA2GSB io2 (.IO(X_ED[14]), .O(T_ED[14]), .I(ED_do[14]), .E(XED_S1), .E8(1'b0), .E4(1'b1), .E2(1'b1), .SMT(1'b0), .PU(1'b0), .PD(1'b0), .SR(1'b0));
ZFA2GSB io3 (.IO(X_ED[13]), .O(T_ED[13]), .I(ED_do[13]), .E(XED_S1), .E8(1'b0), .E4(1'b1), .E2(1'b1), .SMT(1'b0), .PU(1'b0), .PD(1'b0), .SR(1'b0));
ZFA2GSB io4 (.IO(X_ED[12]), .O(T_ED[12]), .I(ED_do[12]), .E(XED_S1), .E8(1'b0), .E4(1'b1), .E2(1'b1), .SMT(1'b0), .PU(1'b0), .PD(1'b0), .SR(1'b0));
ZFA2GSB io5 (.IO(X_ED[11]), .O(T_ED[11]), .I(ED_do[11]), .E(XED_S1), .E8(1'b0), .E4(1'b1), .E2(1'b1), .SMT(1'b0), .PU(1'b0), .PD(1'b0), .SR(1'b0));
ZFA2GSB io6 (.IO(X_ED[10]), .O(T_ED[10]), .I(ED_do[10]), .E(XED_S1), .E8(1'b0), .E4(1'b1), .E2(1'b1), .SMT(1'b0), .PU(1'b0), .PD(1'b0), .SR(1'b0));
ZFA2GSB io7 (.IO(X_ED[9]), .O(T_ED[9]), .I(ED_do[9]), .E(XED_S1), .E8(1'b0), .E4(1'b1), .E2(1'b1), .SMT(1'b0), .PU(1'b0), .PD(1'b0), .SR(1'b0));
ZFA2GSB io8 (.IO(X_ED[8]), .O(T_ED[8]), .I(ED_do[8]), .E(XED_S1), .E8(1'b0), .E4(1'b1), .E2(1'b1), .SMT(1'b0), .PU(1'b0), .PD(1'b0), .SR(1'b0));
ZFA2GSB io9 (.IO(X_ED[7]), .O(T_ED[7]), .I(ED_do[7]), .E(XED_S2), .E8(1'b0), .E4(1'b1), .E2(1'b1), .SMT(1'b0), .PU(1'b0), .PD(1'b0), .SR(1'b0));
ZFA2GSB io10 (.IO(X_ED[6]), .O(T_ED[6]), .I(ED_do[6]), .E(XED_S2), .E8(1'b0), .E4(1'b1), .E2(1'b1), .SMT(1'b0), .PU(1'b0), .PD(1'b0), .SR(1'b0));
ZFA2GSB io11 (.IO(X_ED[5]), .O(T_ED[5]), .I(ED_do[5]), .E(XED_S2), .E8(1'b0), .E4(1'b1), .E2(1'b1), .SMT(1'b0), .PU(1'b0), .PD(1'b0), .SR(1'b0));
ZFA2GSB io12 (.IO(X_ED[4]), .O(T_ED[4]), .I(ED_do[4]), .E(XED_S2), .E8(1'b0), .E4(1'b1), .E2(1'b1), .SMT(1'b0), .PU(1'b0), .PD(1'b0), .SR(1'b0));
ZFA2GSB io13 (.IO(X_ED[3]), .O(T_ED[3]), .I(ED_do[3]), .E(XED_S2), .E8(1'b0), .E4(1'b1), .E2(1'b1), .SMT(1'b0), .PU(1'b0), .PD(1'b0), .SR(1'b0));
ZFA2GSB io14 (.IO(X_ED[2]), .O(T_ED[2]), .I(ED_do[2]), .E(XED_S2), .E8(1'b0), .E4(1'b1), .E2(1'b1), .SMT(1'b0), .PU(1'b0), .PD(1'b0), .SR(1'b0));
ZFA2GSB io15 (.IO(X_ED[1]), .O(T_ED[1]), .I(ED_do[1]), .E(XED_S2), .E8(1'b0), .E4(1'b1), .E2(1'b1), .SMT(1'b0), .PU(1'b0), .PD(1'b0), .SR(1'b0));
ZFA2GSB io16 (.IO(X_ED[0]), .O(T_ED[0]), .I(ED_do[0]), .E(XED_S2), .E8(1'b0), .E4(1'b1), .E2(1'b1), .SMT(1'b0), .PU(1'b0), .PD(1'b0), .SR(1'b0));
ZFA2GSB io17 (.IO(X_SCLK0), .O(T_SCLK0), .I(SCLK0), .E(ISCLK0), .E8(1'b0), .E4(1'b1), .E2(1'b1), .SMT(1'b0), .PU(1'b0), .PD(1'b0), .SR(1'b0));
ZFA2GSB io18 (.IO(X_RFS0), .O(T_RFS0), .I(RFS0), .E(IRFS0), .E8(1'b0), .E4(1'b1), .E2(1'b1), .SMT(1'b0), .PU(1'b0), .PD(1'b0), .SR(1'b0));
ZFA2GSB io19 (.IO(X_TFS0), .O(T_TFS0), .I(TFS0), .E(ITFS0), .E8(1'b0), .E4(1'b1), .E2(1'b1), .SMT(1'b0), .PU(1'b0), .PD(1'b0), .SR(1'b0));
ZFA2GSB io20 (.IO(X_SCLK1), .O(T_SCLK1), .I(SCLK1), .E(ISCLK1), .E8(1'b0), .E4(1'b1), .E2(1'b1), .SMT(1'b0), .PU(1'b0), .PD(1'b0), .SR(1'b0));
ZFA2GSB io21 (.IO(X_RFS1), .O(T_RFS1), .I(RFS1), .E(IRFS1), .E8(1'b0), .E4(1'b1), .E2(1'b1), .SMT(1'b0), .PU(1'b0), .PD(1'b0), .SR(1'b0));
ZFA2GSB io22 (.IO(X_TFS1), .O(T_TFS1), .I(TFS1), .E(ITFS1), .E8(1'b0), .E4(1'b1), .E2(1'b1), .SMT(1'b0), .PU(1'b0), .PD(1'b0), .SR(1'b0));
ZFA2GSB io23 (.IO(X_IAD[15]), .O(T_IAD[15]), .I(IAD_do[15]), .E(IAD_oex), .E8(1'b0), .E4(1'b1), .E2(1'b1), .SMT(1'b0), .PU(1'b0), .PD(1'b0), .SR(1'b0));
ZFA2GSB io24 (.IO(X_IAD[14]), .O(T_IAD[14]), .I(IAD_do[14]), .E(IAD_oex), .E8(1'b0), .E4(1'b1), .E2(1'b1), .SMT(1'b0), .PU(1'b0), .PD(1'b0), .SR(1'b0));
ZFA2GSB io25 (.IO(X_IAD[13]), .O(T_IAD[13]), .I(IAD_do[13]), .E(IAD_oex), .E8(1'b0), .E4(1'b1), .E2(1'b1), .SMT(1'b0), .PU(1'b0), .PD(1'b0), .SR(1'b0));
ZFA2GSB io26 (.IO(X_IAD[12]), .O(T_IAD[12]), .I(IAD_do[12]), .E(IAD_oex), .E8(1'b0), .E4(1'b1), .E2(1'b1), .SMT(1'b0), .PU(1'b0), .PD(1'b0), .SR(1'b0));
ZFA2GSB io27 (.IO(X_IAD[11]), .O(T_IAD[11]), .I(IAD_do[11]), .E(IAD_oex), .E8(1'b0), .E4(1'b1), .E2(1'b1), .SMT(1'b0), .PU(1'b0), .PD(1'b0), .SR(1'b0));
ZFA2GSB io28 (.IO(X_IAD[10]), .O(T_IAD[10]), .I(IAD_do[10]), .E(IAD_oex), .E8(1'b0), .E4(1'b1), .E2(1'b1), .SMT(1'b0), .PU(1'b0), .PD(1'b0), .SR(1'b0));
ZFA2GSB io29 (.IO(X_IAD[9]), .O(T_IAD[9]), .I(IAD_do[9]), .E(IAD_oex), .E8(1'b0), .E4(1'b1), .E2(1'b1), .SMT(1'b0), .PU(1'b0), .PD(1'b0), .SR(1'b0));
ZFA2GSB io30 (.IO(X_IAD[8]), .O(T_IAD[8]), .I(IAD_do[8]), .E(IAD_oex), .E8(1'b0), .E4(1'b1), .E2(1'b1), .SMT(1'b0), .PU(1'b0), .PD(1'b0), .SR(1'b0));
ZFA2GSB io31 (.IO(X_IAD[7]), .O(T_IAD[7]), .I(IAD_do[7]), .E(IAD_oex), .E8(1'b0), .E4(1'b1), .E2(1'b1), .SMT(1'b0), .PU(1'b0), .PD(1'b0), .SR(1'b0));
ZFA2GSB io32 (.IO(X_IAD[6]), .O(T_IAD[6]), .I(IAD_do[6]), .E(IAD_oex), .E8(1'b0), .E4(1'b1), .E2(1'b1), .SMT(1'b0), .PU(1'b0), .PD(1'b0), .SR(1'b0));
ZFA2GSB io33 (.IO(X_IAD[5]), .O(T_IAD[5]), .I(IAD_do[5]), .E(IAD_oex), .E8(1'b0), .E4(1'b1), .E2(1'b1), .SMT(1'b0), .PU(1'b0), .PD(1'b0), .SR(1'b0));
ZFA2GSB io34 (.IO(X_IAD[4]), .O(T_IAD[4]), .I(IAD_do[4]), .E(IAD_oex), .E8(1'b0), .E4(1'b1), .E2(1'b1), .SMT(1'b0), .PU(1'b0), .PD(1'b0), .SR(1'b0));
ZFA2GSB io35 (.IO(X_IAD[3]), .O(T_IAD[3]), .I(IAD_do[3]), .E(IAD_oex), .E8(1'b0), .E4(1'b1), .E2(1'b1), .SMT(1'b0), .PU(1'b0), .PD(1'b0), .SR(1'b0));
ZFA2GSB io36 (.IO(X_IAD[2]), .O(T_IAD[2]), .I(IAD_do[2]), .E(IAD_oex), .E8(1'b0), .E4(1'b1), .E2(1'b1), .SMT(1'b0), .PU(1'b0), .PD(1'b0), .SR(1'b0));
ZFA2GSB io37 (.IO(X_IAD[1]), .O(T_IAD[1]), .I(IAD_do[1]), .E(IAD_oex), .E8(1'b0), .E4(1'b1), .E2(1'b1), .SMT(1'b0), .PU(1'b0), .PD(1'b0), .SR(1'b0));
ZFA2GSB io38 (.IO(X_IAD[0]), .O(T_IAD[0]), .I(IAD_do[0]), .E(IAD_oex), .E8(1'b0), .E4(1'b1), .E2(1'b1), .SMT(1'b0), .PU(1'b0), .PD(1'b0), .SR(1'b0));
ZFA2GSB io39 (.IO(X_ID), .O(T_ID), .I(IDo), .E(IDoe), .E8(1'b0), .E4(1'b1), .E2(1'b1), .SMT(1'b0), .PU(1'b0), .PD(1'b0), .SR(1'b0));
/*
ZFA2GSB io40 (.IO(X_PIO[11]), .O(T_PIOin[11]), .I(PIO_out[11]), .E(PIO_oe[11]), .E8(1'b0), .E4(1'b1), .E2(1'b1), .SMT(1'b0), .PU(1'b0), .PD(1'b0), .SR(1'b0));
ZFA2GSB io41 (.IO(X_PIO[10]), .O(T_PIOin[10]), .I(PIO_out[10]), .E(PIO_oe[10]), .E8(1'b0), .E4(1'b1), .E2(1'b1), .SMT(1'b0), .PU(1'b0), .PD(1'b0), .SR(1'b0));
ZFA2GSB io42 (.IO(X_PIO[9]), .O(T_PIOin[9]), .I(PIO_out[9]), .E(PIO_oe[9]), .E8(1'b0), .E4(1'b1), .E2(1'b1), .SMT(1'b0), .PU(1'b0), .PD(1'b0), .SR(1'b0));
ZFA2GSB io43 (.IO(X_PIO[8]), .O(T_PIOin[8]), .I(PIO_out[8]), .E(PIO_oe[8]), .E8(1'b0), .E4(1'b1), .E2(1'b1), .SMT(1'b0), .PU(1'b0), .PD(1'b0), .SR(1'b0));
*/
INV2 uu40 (.O(T_PIOin[11]), .I(1'b1));
INV2 uu41 (.O(T_PIOin[10]), .I(1'b1));
INV2 uu42 (.O(T_PIOin[9]), .I(1'b1));
INV2 uu43 (.O(T_PIOin[8]), .I(1'b1));
ZFA2GSB io44 (.IO(X_PIO[7]), .O(T_PIOin[7]), .I(PIO_out[7]), .E(PIO_oe[7]), .E8(1'b0), .E4(1'b1), .E2(1'b1), .SMT(1'b0), .PU(1'b0), .PD(1'b0), .SR(1'b0));
ZFA2GSB io45 (.IO(X_PIO[6]), .O(T_PIOin[6]), .I(PIO_out[6]), .E(PIO_oe[6]), .E8(1'b0), .E4(1'b1), .E2(1'b1), .SMT(1'b0), .PU(1'b0), .PD(1'b0), .SR(1'b0));
ZFA2GSB io46 (.IO(X_PIO[5]), .O(T_PIOin[5]), .I(PIO_out[5]), .E(PIO_oe[5]), .E8(1'b0), .E4(1'b1), .E2(1'b1), .SMT(1'b0), .PU(1'b0), .PD(1'b0), .SR(1'b0));
ZFA2GSB io47 (.IO(X_PIO[4]), .O(T_PIOin[4]), .I(PIO_out[4]), .E(PIO_oe[4]), .E8(1'b0), .E4(1'b1), .E2(1'b1), .SMT(1'b0), .PU(1'b0), .PD(1'b0), .SR(1'b0));
ZFA2GSB io48 (.IO(X_PIO[3]), .O(T_PIOin[3]), .I(PIO_out[3]), .E(PIO_oe[3]), .E8(1'b0), .E4(1'b1), .E2(1'b1), .SMT(1'b0), .PU(1'b0), .PD(1'b0), .SR(1'b0));
ZFA2GSB io49 (.IO(X_PIO[2]), .O(T_PIOin[2]), .I(PIO_out[2]), .E(PIO_oe[2]), .E8(1'b0), .E4(1'b1), .E2(1'b1), .SMT(1'b0), .PU(1'b0), .PD(1'b0), .SR(1'b0));
ZFA2GSB io50 (.IO(X_PIO[1]), .O(T_PIOin[1]), .I(PIO_out[1]), .E(PIO_oe[1]), .E8(1'b0), .E4(1'b1), .E2(1'b1), .SMT(1'b0), .PU(1'b0), .PD(1'b0), .SR(1'b0));
ZFA2GSB io51 (.IO(X_PIO[0]), .O(T_PIOin[0]), .I(PIO_out[0]), .E(PIO_oe[0]), .E8(1'b0), .E4(1'b1), .E2(1'b1), .SMT(1'b0), .PU(1'b0), .PD(1'b0), .SR(1'b0));
ZFA2GSB io52 (.IO(X_EA[7]), .O(T_EA[7]), .I(EA_do[7]), .E(EA_oex), .E8(1'b0), .E4(1'b1), .E2(1'b1), .SMT(1'b0), .PU(1'b0), .PD(1'b0), .SR(1'b0));
ZFA2GSB io53 (.IO(X_EA[6]), .O(T_EA[6]), .I(EA_do[6]), .E(EA_oex), .E8(1'b0), .E4(1'b1), .E2(1'b1), .SMT(1'b0), .PU(1'b0), .PD(1'b0), .SR(1'b0));
ZFA2GSB io54 (.IO(X_EA[5]), .O(T_EA[5]), .I(EA_do[5]), .E(EA_oex), .E8(1'b0), .E4(1'b1), .E2(1'b1), .SMT(1'b0), .PU(1'b0), .PD(1'b0), .SR(1'b0));
ZFA2GSB io55 (.IO(X_EA[4]), .O(T_EA[4]), .I(EA_do[4]), .E(EA_oex), .E8(1'b0), .E4(1'b1), .E2(1'b1), .SMT(1'b0), .PU(1'b0), .PD(1'b0), .SR(1'b0));
ZFA2GSB io56 (.IO(X_EA[3]), .O(T_EA[3]), .I(EA_do[3]), .E(EA_oex), .E8(1'b0), .E4(1'b1), .E2(1'b1), .SMT(1'b0), .PU(1'b0), .PD(1'b0), .SR(1'b0));
ZFA2GSB io57 (.IO(X_EA[2]), .O(T_EA[2]), .I(EA_do[2]), .E(EA_oex), .E8(1'b0), .E4(1'b1), .E2(1'b1), .SMT(1'b0), .PU(1'b0), .PD(1'b0), .SR(1'b0));
ZFA2GSB io58 (.IO(X_EA[1]), .O(T_EA[1]), .I(EA_do[1]), .E(EA_oex), .E8(1'b0), .E4(1'b1), .E2(1'b1), .SMT(1'b0), .PU(1'b0), .PD(1'b0), .SR(1'b0));
ZFA2GSB io59 (.IO(X_EA[0]), .O(T_EA[0]), .I(EA_do[0]), .E(EA_oex), .E8(1'b0), .E4(1'b1), .E2(1'b1), .SMT(1'b0), .PU(1'b0), .PD(1'b0), .SR(1'b0));
endmodule
|
`include "../include/x_def.v"
/* ---------------------------------------------------------------------- */
/* FTC218x top module ( 02-02-2000 BY LCJ) */
/* ---------------------------------------------------------------------- */
module PINs (/* Input pins : (21) : */
/* glb */ X_RSTn, X_ICE_RSTn, X_BMODE, X_TMODE[1:0],
X_PLLsel[3:0], X_MMAP, X_GOICE,
/* core */ X_PWDn, X_IRQ2n, /*X_IRQ1n, X_IRQ0n,*/
X_IRQL1n, X_IRQE1n, X_IRQE0n, X_BRn,
/* spt */ X_RD0, X_RD1,
/* idma */ X_IRDn, X_IWRn, X_ISn, X_IAL,
/* sice */ X_ICK, X_IMS,
/* -------- Outputs : (27) -------- */
/* glb */ X_CLKO, X_PWDACK,
/* memc */ X_BGn, /*X_BGHn, X_EA[14:0],*/
X_EA_U[14:8], X_EA[7:0], X_PMSn,
X_DMSn, X_IOSn, /*X_CMSn,*/ X_RDn, X_WRn,
X_ECMSn, X_ECMA_EN,
/* spt */ X_TD0, X_TD1,
/* idma */ X_IACKn,
/* bdma */ X_BMSn,
/* -------- Inouts : (51) -------- */
/* xtal */ X_CLKI, XTAL,
/* emem */ X_ED[15:0],
/* spt */ X_SCLK0, X_RFS0, X_TFS0,
X_SCLK1, X_RFS1, X_TFS1,
/* idma */ X_IAD[15:0],
/* pio */ X_PIO[7:0],
/* sice */ X_ID,
/* ------------------------------------ */
/* Internal signals : */
/* ------------------------------------ */
/* outputs : */
/* glb */ T_RSTn, T_CLKI, T_BMODE, T_PLLsel[3:0],
T_TMODE, T_ED[15:0], T_EA[7:0],
T_selECM, T_GOICE,
/* core */ T_PWDn, T_IRQ2n, T_IRQ1n, T_IRQ0n,
T_IRQL1n, T_IRQE1n, T_IRQE0n, T_BRn,
/* spt */ T_RD0, T_RD1, T_SCLK0, T_SCLK1, T_RFS0,
T_TFS0, T_RFS1, T_TFS1,
/* idma */ T_IRDn, T_IWRn, T_ISn, T_IAL, T_IAD[15:0],
/* pio */ T_PIOin[11:0],
/* sice */ T_ICK, T_IMS, T_ID,
/* inputs : */
/* clkc */ CLKO, PWDACK, XTALoffn,
/* emc */ BGn, EA_oe, EA_do[14:0], PMSn, DMSn, BMSn,
IOSn, CMSn, RDn, WRn, ED_oe, ED_do[15:0],
ECMSn, ECMA_EN,
/* spt */ TD0, TD1, SCLK0, ISCLK0, SCLK1, ISCLK1,
RFS0, IRFS0, TFS0, ITFS0, RFS1, IRFS1,
TFS1, ITFS1,
/* idma */ IACKn, IAD_oe, IAD_do[15:0], T_MMAP,
/* pio */ PIO_oe[11:0], PIO_out[11:0],
/* sice */ IDo, IDoe,
/* bdma */ BMcs, BDIR);
input BMcs, BDIR;
input [3:0] X_PLLsel;
input [1:0] X_TMODE;
input X_RSTn, X_ICE_RSTn, X_BMODE, X_MMAP, X_PWDn, X_IRQ2n,
/*X_IRQ1n, X_IRQ0n,*/ X_IRQL1n, X_IRQE1n, X_IRQE0n,
X_BRn, X_RD0, X_RD1, X_IRDn, X_GOICE,
X_IWRn, X_ISn, X_IAL, X_ICK, X_IMS;
output [14:8] X_EA_U;
inout [7:0] X_EA;
output X_CLKO, X_PWDACK,
X_BGn, X_PMSn, X_DMSn, X_IOSn, /*X_CMSn,*/ X_ECMSn, X_ECMA_EN,
X_RDn, X_WRn, X_TD0, X_TD1, X_IACKn, X_BMSn;
input X_CLKI;
inout XTAL;
inout [15:0] X_ED, X_IAD;
inout [7:0] X_PIO;
inout X_SCLK0, X_SCLK1, X_RFS0, X_TFS0, X_RFS1, X_TFS1,
X_ID;
input [14:0] EA_do;
input [11:0] PIO_oe, PIO_out;
input [15:0] ED_do, IAD_do;
input CLKO, PWDACK, BGn, EA_oe, PMSn, DMSn, BMSn, IOSn,
CMSn, RDn, WRn, TD0, TD1, IACKn, ED_oe, ECMSn, ECMA_EN,
IAD_oe, SCLK0, ISCLK0, SCLK1, ISCLK1, RFS0,
IRFS0, TFS0, ITFS0, RFS1, IRFS1, TFS1, ITFS1,
IDo, IDoe, XTALoffn;
output [15:0] T_ED, T_IAD;
output [7:0] T_EA;
output [11:0] T_PIOin;
output [3:0] T_PLLsel;
output T_RSTn, T_CLKI, T_BMODE, T_MMAP, T_TMODE,
T_PWDn, T_IRQ2n, T_IRQ1n, T_IRQ0n,
T_IRQL1n, T_IRQE1n, T_IRQE0n, T_BRn,
T_RD0, T_RD1, T_IRDn, T_IWRn, T_ISn, T_GOICE,
T_IAL, T_ICK, T_IMS, T_SCLK0, T_SCLK1,
T_RFS0, T_TFS0, T_RFS1, T_TFS1, T_ID, T_selECM;
/* reserved pins : */
/* ------ Connecting Crystal (2 (ESD) pads) : ------ */
XSCIOM5 ckio (.IO(XTAL), .I(X_CLKI), .E(XTALoffn), .O(T_CLKI), .FEB(1'b0));
/* ---------------- inputs : ---------------- */
XC in1 (.O(T_PLLsel[3]), .I(X_PLLsel[3]));
XC in2 (.O(T_PLLsel[2]), .I(X_PLLsel[2]));
XC in3 (.O(T_PLLsel[1]), .I(X_PLLsel[1]));
XC in4 (.O(T_PLLsel[0]), .I(X_PLLsel[0]));
XCU8 in5 (.O(T_RSTn_1), .I(X_RSTn));
XCU8 in5_ (.O(T_RSTn_2), .I(X_ICE_RSTn));
XC in6 (.O(T_ICK), .I(X_ICK));
XC in7 (.O(T_IMS), .I(X_IMS));
XC in8 (.O(T_BMODE), .I(X_BMODE));
XC in9 (.O(T_TMODE), .I(X_TMODE[0]));
XC in12 (.O(T_selECM), .I(X_TMODE[1]));
XC in10 (.O(T_PWDn), .I(X_PWDn));
XCU8 in11 (.O(T_IRQ2n), .I(X_IRQ2n));
XCU8 in14 (.O(T_IRQL1n), .I(X_IRQL1n));
XCU8 in15 (.O(T_IRQE1n), .I(X_IRQE1n));
XCU8 in16 (.O(T_IRQE0n), .I(X_IRQE0n));
XCU8 in17 (.O(T_BRn), .I(X_BRn));
XC in18 (.O(T_RD0), .I(X_RD0));
XC in19 (.O(T_RD1), .I(X_RD1));
XCU8 in20 (.O(T_ISn), .I(X_ISn));
XCU8 in21 (.O(T_IRDn), .I(X_IRDn));
XCU8 in22 (.O(T_IWRn), .I(X_IWRn));
XCD8 in23 (.O(T_IAL), .I(X_IAL));
XC in24 (.O(T_MMAP), .I(X_MMAP));
XCD8 in25 (.O(T_GOICE), .I(X_GOICE));
INV1 uu12 (.O(T_IRQ1n), .I(1'b0));
INV1 uu13 (.O(T_IRQ0n), .I(1'b0));
AN2P uu14 (.O(T_RSTn), .I1(T_RSTn_1), .I2(T_RSTn_2));
/* ---------------- outputs : ---------------- */
BUF4 uu0 (.O(BGnx), .I(BGn));
YC04T out1 (.O(X_CLKO), .I(CLKO), .E(1'b1));
YC04A out2 (.O(X_PWDACK), .I(PWDACK), .E(1'b1));
YC04A out3 (.O(X_BGn), .I(BGn), .E(1'b1));
YC04A out4 (.O(X_EA_U[14]), .I(EA_do[14]), .E(BGnx));
YC04A out5 (.O(X_EA_U[13]), .I(EA_do[13]), .E(BGnx));
YC04A out6 (.O(X_EA_U[12]), .I(EA_do[12]), .E(BGnx));
YC04A out7 (.O(X_EA_U[11]), .I(EA_do[11]), .E(BGnx));
YC04A out8 (.O(X_EA_U[10]), .I(EA_do[10]), .E(BGnx));
YC04A out9 (.O(X_EA_U[9]), .I(EA_do[9]), .E(BGnx));
YC04A out10 (.O(X_EA_U[8]), .I(EA_do[8]), .E(BGnx));
YC04A out19 (.O(X_PMSn), .I(PMSn), .E(BGnx));
YC04A out20 (.O(X_DMSn), .I(DMSn), .E(BGnx));
YC04A out30 (.O(X_BMSn), .I(BMSn), .E(BGnx));
YC04A out21 (.O(X_IOSn), .I(IOSn), .E(BGnx));
YC04A out23 (.O(X_RDn), .I(RDn), .E(BGnx));
YC04A out24 (.O(X_WRn), .I(WRn), .E(BGnx));
YC04T out25 (.O(X_TD0), .I(TD0), .E(1'b1));
YC04T out26 (.O(X_TD1), .I(TD1), .E(1'b1));
YC04T out27 (.O(X_IACKn), .I(IACKn), .E(1'b1));
YC04A out28 (.O(X_ECMSn), .I(ECMSn), .E(BGnx));
YC04A out29 (.O(X_ECMA_EN), .I(ECMA_EN), .E(BGnx));
/* ---------------- inouts : ---------------- */
BUF4 uu2 (.O(IAD_oex), .I(IAD_oe));
BUF4 uu3 (.O(EA_oex), .I(EA_oe));
OR2P xeds1 (.O(XED_S1), .I1(ED_oe), .I2(BMcs));
AO12P xeds2 (.O(XED_S2), .A1(ED_oe), .B1(BMcs), .B2(BDIR));
ZCC04A io1 (.IO(X_ED[15]), .O(T_ED[15]), .I(ED_do[15]), .E(ED_oe));
ZCC04A io2 (.IO(X_ED[14]), .O(T_ED[14]), .I(ED_do[14]), .E(XED_S1));
ZCC04A io3 (.IO(X_ED[13]), .O(T_ED[13]), .I(ED_do[13]), .E(XED_S1));
ZCC04A io4 (.IO(X_ED[12]), .O(T_ED[12]), .I(ED_do[12]), .E(XED_S1));
ZCC04A io5 (.IO(X_ED[11]), .O(T_ED[11]), .I(ED_do[11]), .E(XED_S1));
ZCC04A io6 (.IO(X_ED[10]), .O(T_ED[10]), .I(ED_do[10]), .E(XED_S1));
ZCC04A io7 (.IO(X_ED[9]), .O(T_ED[9]), .I(ED_do[9]), .E(XED_S1));
ZCC04A io8 (.IO(X_ED[8]), .O(T_ED[8]), .I(ED_do[8]), .E(XED_S1));
ZCC04A io9 (.IO(X_ED[7]), .O(T_ED[7]), .I(ED_do[7]), .E(XED_S2));
ZCC04A io10 (.IO(X_ED[6]), .O(T_ED[6]), .I(ED_do[6]), .E(XED_S2));
ZCC04A io11 (.IO(X_ED[5]), .O(T_ED[5]), .I(ED_do[5]), .E(XED_S2));
ZCC04A io12 (.IO(X_ED[4]), .O(T_ED[4]), .I(ED_do[4]), .E(XED_S2));
ZCC04A io13 (.IO(X_ED[3]), .O(T_ED[3]), .I(ED_do[3]), .E(XED_S2));
ZCC04A io14 (.IO(X_ED[2]), .O(T_ED[2]), .I(ED_do[2]), .E(XED_S2));
ZCC04A io15 (.IO(X_ED[1]), .O(T_ED[1]), .I(ED_do[1]), .E(XED_S2));
ZCC04A io16 (.IO(X_ED[0]), .O(T_ED[0]), .I(ED_do[0]), .E(XED_S2));
ZCC04A io17 (.IO(X_SCLK0), .O(T_SCLK0), .I(SCLK0), .E(ISCLK0));
ZCC04A io18 (.IO(X_RFS0), .O(T_RFS0), .I(RFS0), .E(IRFS0));
ZCC04A io19 (.IO(X_TFS0), .O(T_TFS0), .I(TFS0), .E(ITFS0));
ZCC04A io20 (.IO(X_SCLK1), .O(T_SCLK1), .I(SCLK1), .E(ISCLK1));
ZCC04A io21 (.IO(X_RFS1), .O(T_RFS1), .I(RFS1), .E(IRFS1));
ZCC04A io22 (.IO(X_TFS1), .O(T_TFS1), .I(TFS1), .E(ITFS1));
ZCC04A io23 (.IO(X_IAD[15]), .O(T_IAD[15]), .I(IAD_do[15]), .E(IAD_oex));
ZCC04A io24 (.IO(X_IAD[14]), .O(T_IAD[14]), .I(IAD_do[14]), .E(IAD_oex));
ZCC04A io25 (.IO(X_IAD[13]), .O(T_IAD[13]), .I(IAD_do[13]), .E(IAD_oex));
ZCC04A io26 (.IO(X_IAD[12]), .O(T_IAD[12]), .I(IAD_do[12]), .E(IAD_oex));
ZCC04A io27 (.IO(X_IAD[11]), .O(T_IAD[11]), .I(IAD_do[11]), .E(IAD_oex));
ZCC04A io28 (.IO(X_IAD[10]), .O(T_IAD[10]), .I(IAD_do[10]), .E(IAD_oex));
ZCC04A io29 (.IO(X_IAD[9]), .O(T_IAD[9]), .I(IAD_do[9]), .E(IAD_oex));
ZCC04A io30 (.IO(X_IAD[8]), .O(T_IAD[8]), .I(IAD_do[8]), .E(IAD_oex));
ZCC04A io31 (.IO(X_IAD[7]), .O(T_IAD[7]), .I(IAD_do[7]), .E(IAD_oex));
ZCC04A io32 (.IO(X_IAD[6]), .O(T_IAD[6]), .I(IAD_do[6]), .E(IAD_oex));
ZCC04A io33 (.IO(X_IAD[5]), .O(T_IAD[5]), .I(IAD_do[5]), .E(IAD_oex));
ZCC04A io34 (.IO(X_IAD[4]), .O(T_IAD[4]), .I(IAD_do[4]), .E(IAD_oex));
ZCC04A io35 (.IO(X_IAD[3]), .O(T_IAD[3]), .I(IAD_do[3]), .E(IAD_oex));
ZCC04A io36 (.IO(X_IAD[2]), .O(T_IAD[2]), .I(IAD_do[2]), .E(IAD_oex));
ZCC04A io37 (.IO(X_IAD[1]), .O(T_IAD[1]), .I(IAD_do[1]), .E(IAD_oex));
ZCC04A io38 (.IO(X_IAD[0]), .O(T_IAD[0]), .I(IAD_do[0]), .E(IAD_oex));
ZCC04A io39 (.IO(X_ID), .O(T_ID), .I(IDo), .E(IDoe));
/*
ZCC04A io40 (.IO(X_PIO[11]), .O(T_PIOin[11]), .I(PIO_out[11]), .E(PIO_oe[11]));
ZCC04A io41 (.IO(X_PIO[10]), .O(T_PIOin[10]), .I(PIO_out[10]), .E(PIO_oe[10]));
ZCC04A io42 (.IO(X_PIO[9]), .O(T_PIOin[9]), .I(PIO_out[9]), .E(PIO_oe[9]));
ZCC04A io43 (.IO(X_PIO[8]), .O(T_PIOin[8]), .I(PIO_out[8]), .E(PIO_oe[8]));
*/
INV2 uu40 (.O(T_PIOin[11]), .I(1'b1));
INV2 uu41 (.O(T_PIOin[10]), .I(1'b1));
INV2 uu42 (.O(T_PIOin[9]), .I(1'b1));
INV2 uu43 (.O(T_PIOin[8]), .I(1'b1));
ZCC04A io44 (.IO(X_PIO[7]), .O(T_PIOin[7]), .I(PIO_out[7]), .E(PIO_oe[7]));
ZCC04A io45 (.IO(X_PIO[6]), .O(T_PIOin[6]), .I(PIO_out[6]), .E(PIO_oe[6]));
ZCC04A io46 (.IO(X_PIO[5]), .O(T_PIOin[5]), .I(PIO_out[5]), .E(PIO_oe[5]));
ZCC04A io47 (.IO(X_PIO[4]), .O(T_PIOin[4]), .I(PIO_out[4]), .E(PIO_oe[4]));
ZCC04A io48 (.IO(X_PIO[3]), .O(T_PIOin[3]), .I(PIO_out[3]), .E(PIO_oe[3]));
ZCC04A io49 (.IO(X_PIO[2]), .O(T_PIOin[2]), .I(PIO_out[2]), .E(PIO_oe[2]));
ZCC04A io50 (.IO(X_PIO[1]), .O(T_PIOin[1]), .I(PIO_out[1]), .E(PIO_oe[1]));
ZCC04A io51 (.IO(X_PIO[0]), .O(T_PIOin[0]), .I(PIO_out[0]), .E(PIO_oe[0]));
ZCC04A io52 (.IO(X_EA[7]), .O(T_EA[7]), .I(EA_do[7]), .E(EA_oex));
ZCC04A io53 (.IO(X_EA[6]), .O(T_EA[6]), .I(EA_do[6]), .E(EA_oex));
ZCC04A io54 (.IO(X_EA[5]), .O(T_EA[5]), .I(EA_do[5]), .E(EA_oex));
ZCC04A io55 (.IO(X_EA[4]), .O(T_EA[4]), .I(EA_do[4]), .E(EA_oex));
ZCC04A io56 (.IO(X_EA[3]), .O(T_EA[3]), .I(EA_do[3]), .E(EA_oex));
ZCC04A io57 (.IO(X_EA[2]), .O(T_EA[2]), .I(EA_do[2]), .E(EA_oex));
ZCC04A io58 (.IO(X_EA[1]), .O(T_EA[1]), .I(EA_do[1]), .E(EA_oex));
ZCC04A io59 (.IO(X_EA[0]), .O(T_EA[0]), .I(EA_do[0]), .E(EA_oex));
endmodule
|
`include "../include/x_def.v"
module PINs (/* ------- Inputs : --------- */
X_CLKI,
X_RSTn,
X_ICE_RSTn,
X_BMODE,
X_TMODE,
X_PLLsel,
X_MMAP,
X_GOICE,
X_PWDn,
X_IRQ2n,
X_IRQL1n,
X_IRQE1n,
X_IRQE0n,
X_BRn,
X_RD0,
X_RD1,
X_IRDn,
X_IWRn,
X_ISn,
X_IAL,
X_ICK,
X_IMS,
`ifdef FD_DFT
X_DFT_en,
`endif
X_CLKO,
X_PWDACK,
X_BGn,
X_EA_U,
X_EA,
X_PMSn,
X_DMSn,
X_IOSn,
X_RDn,
X_WRn,
X_ECMSn,
X_ECMA_EN,
X_TD0,
X_TD1,
X_IACKn,
X_BMSn,
`ifdef FD_EVB
`else
XTAL,
`endif
X_ED,
X_SCLK0,
X_RFS0,
X_TFS0,
X_SCLK1,
X_RFS1,
X_TFS1,
X_IAD,
X_PIO,
X_ID,
D_RSTn,
T_ICE_RSTn,
T_BMODE,
T_MMAP,
T_TMODE,
D_CLKI_OSC,
T_PLLsel,
T_ED,
T_EA,
T_PWDn,
D_IRQ2n,
T_IRQ1n,
T_IRQ0n,
D_IRQL1n,
D_IRQE1n,
D_IRQE0n,
T_BRn,
D_RD0,
D_RD1,
T_SCLK0,
T_SCLK1,
T_RFS0,
T_TFS0,
T_RFS1,
T_TFS1,
T_IRDn,
T_IWRn,
T_ISn,
T_IAL,
D_IAD_di,
T_PIOin,
D_ICK,
T_IMS,
T_ID,
T_GOICE,
`ifdef FD_DFT
D_DFT_en,
`endif
CLKO,
PWDACK,
XTALoffn,
BGn,
EA_oe,
EA_do,
PMSn,
DMSn,
BMSn,
IOSn,
RDn,
WRn,
ED_oe_15,
ED_oe_14_8,
ED_oe_7_0,
ED_do,
ECMSn,
ECMA_EN,
D_TD0,
D_TD1,
SCLK0,
ISCLK0,
SCLK1,
ISCLK1,
RFS0,
IRFS0,
TFS0,
ITFS0,
RFS1,
IRFS1,
TFS1,
ITFS1,
IACKn,
IAD_oex,
D_IAD_do,
PIO_oe,
PIO_out,
IDo,
IDoe
);
input X_CLKI,
X_RSTn,
X_ICE_RSTn,
X_BMODE;
input[1:0]
X_TMODE;
input[3:0]
X_PLLsel;
input X_MMAP,
X_GOICE,
X_PWDn,
X_IRQ2n,
X_IRQL1n,
X_IRQE1n,
X_IRQE0n,
X_BRn,
X_RD0,
X_RD1,
X_IRDn,
X_IWRn,
X_ISn,
X_IAL,
X_ICK,
X_IMS,
CLKO,
PWDACK,
BGn,
EA_oe;
input[14:0]
EA_do;
input PMSn,
DMSn,
BMSn,
IOSn,
RDn,
WRn,
ED_oe_15,
ED_oe_14_8,
ED_oe_7_0;
input[15:0]
ED_do;
input ECMSn,
ECMA_EN,
D_TD0,
D_TD1,
SCLK0,
ISCLK0,
SCLK1,
ISCLK1,
RFS0,
IRFS0,
TFS0,
ITFS0,
RFS1,
IRFS1,
TFS1,
ITFS1,
IACKn,
XTALoffn,
IAD_oex;
input[15:0]
D_IAD_do;
input[11:0]
PIO_oe,
PIO_out;
input IDo,
IDoe;
`ifdef FD_DFT
input X_DFT_en;
`endif
output X_CLKO,
X_PWDACK,
X_BGn;
output[14:8]
X_EA_U;
inout [7:0]
X_EA;
output X_PMSn,
X_DMSn,
X_IOSn,
X_RDn,
X_WRn,
X_ECMSn,
X_ECMA_EN,
X_TD0,
X_TD1,
X_IACKn,
X_BMSn;
output D_RSTn,
T_ICE_RSTn,
T_BMODE,
T_MMAP;
output[1:0] T_TMODE;
output D_CLKI_OSC;
output[3:0] T_PLLsel;
output[15:0]T_ED;
output[7:0] T_EA;
output T_PWDn,
D_IRQ2n,
T_IRQ1n,
T_IRQ0n,
D_IRQL1n,
D_IRQE1n,
D_IRQE0n,
T_BRn,
D_RD0,
D_RD1,
T_SCLK0,
T_SCLK1,
T_RFS0,
T_TFS0,
T_RFS1,
T_TFS1,
T_IRDn,
T_IWRn,
T_ISn,
T_IAL;
output[15:0] D_IAD_di;
output[11:0] T_PIOin;
output D_ICK,
T_IMS,
T_ID,
T_GOICE;
`ifdef FD_DFT
output D_DFT_en;
`endif
`ifdef FD_EVB
`else
inout XTAL;
`endif
inout[15:0] X_ED;
inout X_SCLK0,
X_RFS0,
X_TFS0,
X_SCLK1,
X_RFS1,
X_TFS1;
inout[15:0] X_IAD;
inout[7:0] X_PIO;
inout X_ID;
`ifdef FD_DFT
assign D_DFT_en = X_DFT_en;
`endif
assign D_RSTn = X_RSTn;
assign D_CLKI_OSC = X_CLKI;
assign D_IRQ2n = X_IRQ2n;
assign D_IRQL1n = X_IRQL1n;
assign D_IRQE1n = X_IRQE1n;
assign D_IRQE0n = X_IRQE0n;
assign D_RD0 = X_RD0;
assign D_RD1 = X_RD1;
assign D_ICK = X_ICK;
assign T_PLLsel[3:0] = X_PLLsel[3:0];
assign T_ICE_RSTn = X_ICE_RSTn;
assign T_BMODE = X_BMODE;
assign T_TMODE[1:0] = X_TMODE[1:0];
assign T_PWDn = X_PWDn;
`ifdef FD_EVB
assign T_IRQ1n = 1'b1;
assign T_IRQ0n = 1'b1;
`else
pullup(T_IRQ1n);
pullup(T_IRQ0n);
`endif
assign T_IRDn = X_IRDn;
assign T_IWRn = X_IWRn;
assign T_ISn = X_ISn;
assign T_IAL = X_IAL;
assign T_MMAP = X_MMAP;
assign T_GOICE = X_GOICE;
assign T_IMS = X_IMS;
assign T_BRn = X_BRn;
assign X_CLKO = CLKO;
assign X_PWDACK = PWDACK;
assign X_BGn = BGn;
assign X_EA_U[14:8] = BGn ? EA_do[14:8] : 7'bz;
assign X_PMSn = BGn ? PMSn : 1'bz;
assign X_DMSn = BGn ? DMSn : 1'bz;
assign X_IOSn = BGn ? IOSn : 1'bz;
assign X_BMSn = BGn ? BMSn : 1'bz;
assign X_ECMSn = BGn ? ECMSn : 1'bz;
assign X_ECMA_EN = BGn ? ECMA_EN : 1'bz;
assign X_RDn = BGn ? RDn : 1'bz;
assign X_WRn = BGn ? WRn : 1'bz;
assign X_IACKn = IACKn;
assign X_TD0 = D_TD0;
assign X_TD1 = D_TD1;
assign X_EA[7:0] = EA_oe ? EA_do[7:0] : 8'bz;
assign T_EA[7:0] = X_EA[7:0];
assign X_ED[15] = ED_oe_15 ? ED_do[15] : 1'bz;
assign X_ED[14:8] = ED_oe_14_8 ? ED_do[14:8] : 7'bz;
assign X_ED[7:0] = ED_oe_7_0 ? ED_do[7:0] : 8'bz;
assign T_ED[15:0] = X_ED[15:0];
assign X_SCLK0 = ISCLK0 ? SCLK0 : 1'bz;
assign T_SCLK0 = X_SCLK0;
assign X_RFS0 = IRFS0 ? RFS0 : 1'bz;
assign T_RFS0 = X_RFS0;
assign X_TFS0 = ITFS0 ? TFS0 : 1'bz;
assign T_TFS0 = X_TFS0;
assign X_SCLK1 = ISCLK1 ? SCLK1 : 1'bz;
assign T_SCLK1 = X_SCLK1;
assign X_RFS1 = IRFS1 ? RFS1 : 1'bz;
assign T_RFS1 = X_RFS1;
assign X_TFS1 = ITFS1 ? TFS1 : 1'bz;
assign T_TFS1 = X_TFS1;
assign X_IAD[15:0] = IAD_oex ? D_IAD_do[15:0] : 16'bz;
assign D_IAD_di[15:0] = X_IAD[15:0];
assign X_ID = IDoe ? IDo : 1'bz;
assign T_ID = X_ID;
assign T_PIOin[11] = 1'b0;
assign T_PIOin[10] = 1'b0;
assign T_PIOin[9] = 1'b0;
assign T_PIOin[8] = 1'b0;
assign T_PIOin[7:0] = X_PIO[7:0];
assign X_PIO[7] = PIO_oe[7] ? PIO_out[7] : 1'bz;
assign X_PIO[6] = PIO_oe[6] ? PIO_out[6] : 1'bz;
assign X_PIO[5] = PIO_oe[5] ? PIO_out[5] : 1'bz;
assign X_PIO[4] = PIO_oe[4] ? PIO_out[4] : 1'bz;
assign X_PIO[3] = PIO_oe[3] ? PIO_out[3] : 1'bz;
assign X_PIO[2] = PIO_oe[2] ? PIO_out[2] : 1'bz;
assign X_PIO[1] = PIO_oe[1] ? PIO_out[1] : 1'bz;
assign X_PIO[0] = PIO_oe[0] ? PIO_out[0] : 1'bz;
endmodule
|
`include "../include/x_def.v"
module REGo (/* -------- Inputs : --------- */
DM_rdm,
DM_rd0, DM_rd1,
DM_rd2, DM_rd3,
DM_rd4, DM_rd5,
DM_rd6, DM_rd7,
PM_rd0, PM_rd1,
PM_rd2, PM_rd3,
PM_rd4, PM_rd5,
PM_rd6, PM_rd7,
CM_rdm,
CM_rd0, CM_rd1,
CM_rd2, CM_rd3,
CM_rd4, CM_rd5,
CM_rd6, CM_rd7,
DSPCLK, GO_Cx, redoSTI_h, Pwrite_Ei,
psqDMD_do, dagDMD_do,
euDMD_do, euPMD_do,
CKR,
SPT0_do, RX0,
SPT1_do, RX1,
PIO_do,
TMR_do,
DCTL, DOVL, idmaPMD_oe,
idmaDMD_oe, idmaPMD_do,
SREQ, spt0DMD_oe, spt1DMD_oe,
autoDMD_do,
WSCR, WSCR_ext, emcDMD_oe, emcDMD_do,
emcPMD_oe, emcPMD_do,
SYSRo, ldSREG_E, selSYSR, selCKR,
selDCTL, selDOVL, selWSCR, selWSCR_ext,
DM_oe,
DMo_oe0, DMo_oe1,
DMo_oe2, DMo_oe3,
DMo_oe4, DMo_oe5,
DMo_oe6, DMo_oe7,
PMo_oe0, PMo_oe1,
PMo_oe2, PMo_oe3,
PMo_oe4, PMo_oe5,
PMo_oe6, PMo_oe7,
CM_oe,
CMo_oe0, CMo_oe1,
CMo_oe2, CMo_oe3,
CMo_oe4, CMo_oe5,
CMo_oe6, CMo_oe7,
BRdataBUF, bdmaDMD_oe,
BDMAmmio, bdmaPMD_oe,
DM_wd, DMDin, PM_wd,
PMDin, CM_rd, SICEmmio);
input [23:0] BRdataBUF;
input [15:0] BDMAmmio;
input bdmaDMD_oe,
bdmaPMD_oe;
input [15:0] SICEmmio;
input [15:0] PM_rd0,
PM_rd1,
PM_rd2,
PM_rd3,
PM_rd4,
PM_rd5,
PM_rd6,
PM_rd7,
DM_rdm,
DM_rd0,
DM_rd1,
DM_rd2,
DM_rd3,
DM_rd4,
DM_rd5,
DM_rd6,
DM_rd7,
psqDMD_do,
dagDMD_do,
euDMD_do,
euPMD_do,
autoDMD_do,
emcDMD_do,
emcPMD_do,
idmaPMD_do;
input [23:0] CM_rdm,
CM_rd0,
CM_rd1,
CM_rd2,
CM_rd3,
CM_rd4,
CM_rd5,
CM_rd6,
CM_rd7;
input [15:0] CKR, SPT0_do, SPT1_do,
PIO_do, TMR_do, RX0, RX1;
input [11:0] DOVL;
input [14:0] DCTL, WSCR;
input [15:0] SYSRo;
input [7:0] WSCR_ext;
input DSPCLK,
GO_Cx,
SREQ,
redoSTI_h,
Pwrite_Ei,
emcDMD_oe, emcPMD_oe,
idmaDMD_oe,
idmaPMD_oe,
ldSREG_E,
selCKR, selSYSR, selDCTL, selDOVL,
selWSCR, selWSCR_ext, spt0DMD_oe, spt1DMD_oe;
input PMo_oe0,
PMo_oe1,
PMo_oe2,
PMo_oe3,
PMo_oe4,
PMo_oe5,
PMo_oe6,
PMo_oe7,
DM_oe,
DMo_oe0,
DMo_oe1,
DMo_oe2,
DMo_oe3,
DMo_oe4,
DMo_oe5,
DMo_oe6,
DMo_oe7,
CM_oe,
CMo_oe0,
CMo_oe1,
CMo_oe2,
CMo_oe3,
CMo_oe4,
CMo_oe5,
CMo_oe6,
CMo_oe7;
output [15:0] DM_wd, PM_wd,
DMDin, PMDin;
output [23:0] CM_rd;
reg [15:0] STD_C;
wire [15:0] SREG_do, DMDsteal, DM_wd0i, DM_wd0,
PM_wd0, mmioDMD_do, redoSTI_do;
wire bdmaDMD_oe, bdmaPMD_oe, DMDsteal_oe;
assign #`da SREG_do[15:0] = {16{selCKR}} & CKR[15:0] |
SPT0_do[15:0] |
SPT1_do[15:0] |
{16{selSYSR}}& SYSRo[15:0] |
PIO_do[15:0] |
TMR_do[15:0] |
{16{selDCTL}} & {1'b0, DCTL[14:0]} |
{16{selDOVL}} & {4'b0, DOVL[11:0]} |
{16{selWSCR}} & {1'b0, WSCR[14:0]} |
{16{selWSCR_ext}} & {8'b0, WSCR_ext[7:0]} |
BDMAmmio[15:0] |
SICEmmio[15:0];
assign #`da mmioDMD_do[15:0] = {16{ldSREG_E}} & SREG_do[15:0];
assign #`da DMDsteal_oe = idmaDMD_oe || spt0DMD_oe || spt1DMD_oe || bdmaDMD_oe;
assign #`da DMDsteal[15:0] = {16{idmaDMD_oe}} & idmaPMD_do[15:0] |
{16{spt0DMD_oe}} & RX0[15:0] |
{16{spt1DMD_oe}} & RX1[15:0] |
{16{bdmaDMD_oe}} & BRdataBUF[15:0];
always @(posedge DSPCLK)
begin
if (SREQ && GO_Cx)
STD_C[15:0] <= #`db Pwrite_Ei ? euPMD_do[15:0] : DM_wd0i[15:0];
end
assign #`da redoSTI_do[15:0] = {16{redoSTI_h}} & STD_C[15:0];
assign #`da PM_wd0[15:0] = euPMD_do[15:0] | redoSTI_do[15:0];
assign #`da PM_wd[15:0] = idmaPMD_oe ? idmaPMD_do[15:0] :
bdmaPMD_oe ? BRdataBUF[23:8] : PM_wd0[15:0];
reg[15:0] PMDin_rd;
wire [7:0] PMo_oe = {PMo_oe0, PMo_oe1, PMo_oe2, PMo_oe3, PMo_oe4, PMo_oe5, PMo_oe6, PMo_oe7};
always @(PM_rd0 or PM_rd1 or PM_rd2 or PM_rd3 or PM_rd4 or PM_rd5 or PM_rd6 or PM_rd7 or
PMo_oe) begin
case(PMo_oe)
8'b10000000 : PMDin_rd[15:0] = PM_rd0[15:0];
8'b01000000 : PMDin_rd[15:0] = PM_rd1[15:0];
8'b00100000 : PMDin_rd[15:0] = PM_rd2[15:0];
8'b00010000 : PMDin_rd[15:0] = PM_rd3[15:0];
8'b00001000 : PMDin_rd[15:0] = PM_rd4[15:0];
8'b00000100 : PMDin_rd[15:0] = PM_rd5[15:0];
8'b00000010 : PMDin_rd[15:0] = PM_rd6[15:0];
8'b00000001 : PMDin_rd[15:0] = PM_rd7[15:0];
default : PMDin_rd[15:0] = PM_rd0[15:0];
endcase
end
assign PMDin[15:0] = |{PMo_oe[7:0]} ? PMDin_rd[15:0] :
emcPMD_oe ? emcPMD_do[15:0] : euPMD_do[15:0];
assign #`da DM_wd0i[15:0] = autoDMD_do[15:0] |
mmioDMD_do[15:0] |
psqDMD_do[15:0] |
dagDMD_do[15:0] |
euDMD_do[15:0];
assign #`da DM_wd0[15:0] = DM_wd0i[15:0] | redoSTI_do[15:0];
assign #`da DM_wd[15:0] = DMDsteal_oe ? DMDsteal[15:0] : DM_wd0[15:0];
reg[15:0] DMDin_rd;
wire [8:0] DMo_oe = {DM_oe, DMo_oe0, DMo_oe1, DMo_oe2, DMo_oe3, DMo_oe4,
DMo_oe5, DMo_oe6, DMo_oe7};
always @(DM_rdm or DM_rd0 or DM_rd1 or DM_rd2 or DM_rd3 or DM_rd4 or DM_rd5 or DM_rd6 or DM_rd7 or
DMo_oe) begin
case(DMo_oe)
9'b100000000 : DMDin_rd[15:0] = DM_rdm[15:0];
9'b010000000 : DMDin_rd[15:0] = DM_rd0[15:0];
9'b001000000 : DMDin_rd[15:0] = DM_rd1[15:0];
9'b000100000 : DMDin_rd[15:0] = DM_rd2[15:0];
9'b000010000 : DMDin_rd[15:0] = DM_rd3[15:0];
9'b000001000 : DMDin_rd[15:0] = DM_rd4[15:0];
9'b000000100 : DMDin_rd[15:0] = DM_rd5[15:0];
9'b000000010 : DMDin_rd[15:0] = DM_rd6[15:0];
9'b000000001 : DMDin_rd[15:0] = DM_rd7[15:0];
default : DMDin_rd[15:0] = DM_rd0[15:0];
endcase
end
assign #`da DMDin[15:0] = |{DMo_oe[8:0]} ? DMDin_rd[15:0] :
emcDMD_oe ? emcDMD_do[15:0] : DM_wd0[15:0];
reg[23:0] CM_rd;
wire [8:0] CMo_oe = {CM_oe, CMo_oe0, CMo_oe1, CMo_oe2, CMo_oe3, CMo_oe4,
CMo_oe5, CMo_oe6, CMo_oe7};
always @(CM_rdm or CM_rd0 or CM_rd1 or CM_rd2 or CM_rd3 or CM_rd4 or CM_rd5 or CM_rd6 or CM_rd7 or
CMo_oe) begin
case(CMo_oe)
9'b100000000 : CM_rd[23:0] = CM_rdm[23:0];
9'b010000000 : CM_rd[23:0] = CM_rd0[23:0];
9'b001000000 : CM_rd[23:0] = CM_rd1[23:0];
9'b000100000 : CM_rd[23:0] = CM_rd2[23:0];
9'b000010000 : CM_rd[23:0] = CM_rd3[23:0];
9'b000001000 : CM_rd[23:0] = CM_rd4[23:0];
9'b000000100 : CM_rd[23:0] = CM_rd5[23:0];
9'b000000010 : CM_rd[23:0] = CM_rd6[23:0];
9'b000000001 : CM_rd[23:0] = CM_rd7[23:0];
default : CM_rd[23:0] = CM_rdm[23:0];
endcase
end
endmodule
|
`include "../include/x_def.v"
module TOP (/* -------- Inputs : --------- */
X_CLKI,
X_RSTn,
X_ICE_RSTn,
X_BMODE,
X_MMAP,
X_TMODE,
X_PLLsel,
X_GOICE,
X_PWDn,
X_IRQ2n,
X_IRQL1n,
X_IRQE1n,
X_IRQE0n,
X_BRn,
X_RD0,
X_RD1,
X_IRDn,
X_IWRn,
X_ISn,
X_IAL,
X_ICK,
X_IMS,
`ifdef FD_DFT
X_DFT_en,
`endif
X_CLKO,
X_PWDACK,
X_BGn,
X_EA_U,
X_EA,
X_PMSn,
X_DMSn,
X_IOSn,
X_RDn,
X_WRn,
X_ECMSn,
X_ECMA_EN,
X_TD0,
X_TD1,
X_IACKn,
X_BMSn,
`ifdef FD_EVB
`else
XTAL,
`endif
X_ED,
X_SCLK0,
X_RFS0,
X_TFS0,
X_SCLK1,
X_RFS1,
X_TFS1,
X_IAD,
X_PIO[7],
X_PIO[6],
X_PIO[5],
X_PIO[4],
X_PIO[3],
X_PIO[2],
X_PIO[1],
X_PIO[0],
X_ID
);
input [3:0] X_PLLsel;
input [1:0] X_TMODE;
input X_RSTn,
X_ICE_RSTn,
X_GOICE,
X_BMODE,
X_MMAP,
X_PWDn,
X_IRQ2n,
X_IRQL1n,
X_IRQE1n,
X_IRQE0n,
X_BRn,
X_RD0,
X_RD1,
X_IRDn,
X_IWRn,
X_ISn,
X_IAL,
X_ICK,
X_IMS;
`ifdef FD_DFT
input X_DFT_en;
`endif
output [14:8] X_EA_U;
inout [7:0] X_EA;
output X_CLKO,
X_PWDACK,
X_BGn,
X_PMSn,
X_DMSn,
X_IOSn,
X_BMSn,
X_ECMSn,
X_ECMA_EN,
X_RDn,
X_WRn,
X_TD0,
X_TD1,
X_IACKn;
input X_CLKI;
`ifdef FD_EVB
`else
inout XTAL;
`endif
inout [15:0] X_ED,
X_IAD;
inout [7:0] X_PIO;
inout X_SCLK0, X_SCLK1,
X_RFS0, X_RFS1,
X_TFS0, X_TFS1,
X_ID;
wire [15:0] D_IAD_do,
IAD_do,
T_IAD,
ED_do,
D_IAD_di,
T_ED;
wire [14:0] EA_do;
wire [11:0] PIO_oe,
PIO_out,
T_PIOin;
wire [1:0] T_TMODE;
wire [3:0] T_PLLsel;
wire [7:0] T_EA;
wire [7:0] VC_SI, VC_SO;
wire [13:0] PMAinx;
wire [15:0] PM_rd0,
PM_rd1,
PM_rd2,
PM_rd3,
PM_rd4,
PM_rd5,
PM_rd6,
PM_rd7,
PM_wd;
wire [13:0] CMAinx;
wire [23:0] CM_rdm,
CM_rd0,
CM_rd1,
CM_rd2,
CM_rd3,
CM_rd4,
CM_rd5,
CM_rd6,
CM_rd7,
CM_wd;
wire [13:0] DMAinx;
wire [15:0] DM_rdm,
DM_rd0,
DM_rd1,
DM_rd2,
DM_rd3,
DM_rd4,
DM_rd5,
DM_rd6,
DM_rd7,
DM_wd;
wire T_CLKI_SRC;
PINs pins (/* ------- Inputs : --------- */
X_CLKI,
X_RSTn,
X_ICE_RSTn,
X_BMODE,
X_TMODE[1:0],
X_PLLsel[3:0],
X_MMAP,
X_GOICE,
X_PWDn,
X_IRQ2n,
X_IRQL1n,
X_IRQE1n,
X_IRQE0n,
X_BRn,
X_RD0,
X_RD1,
X_IRDn,
X_IWRn,
X_ISn,
X_IAL,
X_ICK,
X_IMS,
`ifdef FD_DFT
X_DFT_en,
`endif
X_CLKO,
X_PWDACK,
X_BGn,
X_EA_U[14:8],
X_EA[7:0],
X_PMSn,
X_DMSn,
X_IOSn,
X_RDn,
X_WRn,
X_ECMSn,
X_ECMA_EN,
X_TD0,
X_TD1,
X_IACKn,
X_BMSn,
`ifdef FD_EVB
`else
XTAL,
`endif
X_ED[15:0],
X_SCLK0,
X_RFS0,
X_TFS0,
X_SCLK1,
X_RFS1,
X_TFS1,
X_IAD[15:0],
X_PIO[7:0],
X_ID,
D_RSTn,
T_ICE_RSTn,
T_BMODE,
T_MMAP,
T_TMODE,
D_CLKI_OSC,
T_PLLsel,
T_ED,
T_EA,
T_PWDn,
D_IRQ2n,
T_IRQ1n,
T_IRQ0n,
D_IRQL1n,
D_IRQE1n,
D_IRQE0n,
T_BRn,
D_RD0,
D_RD1,
T_SCLK0,
T_SCLK1,
T_RFS0,
T_TFS0,
T_RFS1,
T_TFS1,
T_IRDn,
T_IWRn,
T_ISn,
T_IAL,
D_IAD_di[15:0],
T_PIOin,
D_ICK,
T_IMS,
T_ID,
T_GOICE,
`ifdef FD_DFT
D_DFT_en,
`endif
CLKO,
PWDACK,
XTALoffn,
BGn,
EA_oe,
EA_do[14:0],
PMSn,
DMSn,
BMSn,
IOSn,
RDn,
WRn,
ED_oe_15,
ED_oe_14_8,
ED_oe_7_0,
ED_do[15:0],
ECMSn,
ECMA_EN,
D_TD0,
D_TD1,
SCLK0,
ISCLK0,
SCLK1,
ISCLK1,
RFS0,
IRFS0,
TFS0,
ITFS0,
RFS1,
IRFS1,
TFS1,
ITFS1,
IACKn,
IAD_oex,
D_IAD_do[15:0],
PIO_oe[11:0],
PIO_out[11:0],
IDo,
IDoe
);
MUX_IO mux_io(
D_CLKI_OSC,
D_RSTn,
D_ICK,
D_IRQ2n,
D_IRQL1n,
D_IRQE1n,
D_IRQE0n,
D_RD0,
D_RD1,
D_IAD_di,
`ifdef FD_DFT
D_DFT_en,
`endif
`ifdef FD_DFT
WP_SO,
TC_SO,
VC_SO,
`endif
TD0,
TD1,
IAD_oe,
IAD_do,
D_TD0,
D_TD1,
D_IAD_do,
IAD_oex,
T_CLKI_OSC,
T_RSTn,
T_ICK,
T_IRQ2n,
T_IRQL1n,
T_IRQE1n,
T_IRQE0n,
T_RD0,
T_RD1,
PM_bdry_sel,
T_IAD
`ifdef FD_DFT
,
TEST_CLK,
TEST_RST,
TCLK,
VC_SHIFT,
TC_UPDATE,
TC_SHIFT,
TC_SI,
WP_SI,
WP_CLK,
TC_RESET,
VC_SI
`endif
);
`ifdef FD_DFT
DSP_CORE_top
`else
DSP_CORE
`endif
dsp (
.T_RSTn(T_RSTn),
.T_ICE_RSTn(T_ICE_RSTn),
.T_BMODE(T_BMODE),
.T_MMAP(T_MMAP),
.T_TMODE(T_TMODE[1:0]),
.T_CLKI_PLL(T_CLKI_PLL),
.T_CLKI_OSC(T_CLKI_OSC),
.T_Sel_PLL(T_Sel_PLL),
`ifdef FD_FPGA
`else
.DSPCLK_insert_buf_i(DSPCLK_insert_buf_o),
`endif
.T_ED(T_ED[15:0]),
.T_EA(T_EA[7:0]),
.T_PWDn(T_PWDn),
.T_IRQ2n(T_IRQ2n),
.T_IRQ1n(T_IRQ1n),
.T_IRQ0n(T_IRQ0n),
.T_IRQL1n(T_IRQL1n),
.T_IRQE1n(T_IRQE1n),
.T_IRQE0n(T_IRQE0n),
.T_BRn(T_BRn),
.T_RD0(T_RD0),
.T_RD1(T_RD1),
.T_SCLK0(T_SCLK0),
.T_SCLK1(T_SCLK1),
.T_RFS0(T_RFS0),
.T_TFS0(T_TFS0),
.T_RFS1(T_RFS1),
.T_TFS1(T_TFS1),
.T_IRDn(T_IRDn),
.T_IWRn(T_IWRn),
.T_ISn(T_ISn),
.T_IAL(T_IAL),
.T_IAD(T_IAD),
.T_PIOin(T_PIOin[11:0]),
.T_ICK(T_ICK),
.T_IMS(T_IMS),
.T_ID(T_ID),
.T_GOICE(T_GOICE),
.PM_bdry_sel(PM_bdry_sel),
.PM_rd0(PM_rd0[15:0]),
.PM_rd1(PM_rd1[15:0]),
.PM_rd2(PM_rd2[15:0]),
.PM_rd3(PM_rd3[15:0]),
.PM_rd4(PM_rd4[15:0]),
.PM_rd5(PM_rd5[15:0]),
.PM_rd6(PM_rd6[15:0]),
.PM_rd7(PM_rd7[15:0]),
.DM_rdm(DM_rdm[15:0]),
.DM_rd0(DM_rd0[15:0]),
.DM_rd1(DM_rd1[15:0]),
.DM_rd2(DM_rd2[15:0]),
.DM_rd3(DM_rd3[15:0]),
.DM_rd4(DM_rd4[15:0]),
.DM_rd5(DM_rd5[15:0]),
.DM_rd6(DM_rd6[15:0]),
.DM_rd7(DM_rd7[15:0]),
.CM_rdm(CM_rdm[23:0]),
.CM_rd0(CM_rd0[23:0]),
.CM_rd1(CM_rd1[23:0]),
.CM_rd2(CM_rd2[23:0]),
.CM_rd3(CM_rd3[23:0]),
.CM_rd4(CM_rd4[23:0]),
.CM_rd5(CM_rd5[23:0]),
.CM_rd6(CM_rd6[23:0]),
.CM_rd7(CM_rd7[23:0]),
`ifdef FD_DFT
.VC_SI(VC_SI[7:0]),
.TCLK(TCLK),
.TC_UPDATE(TC_UPDATE),
.TC_SHIFT(TC_SHIFT),
.TC_RESET(TC_RESET),
.VC_SHIFT(VC_SHIFT),
.TC_SI(TC_SI),
.TEST_CLK(TEST_CLK),
.TEST_RST(TEST_RST),
.WP_SI(WP_SI),
.WP_CLK(WP_CLK),
`endif
`ifdef FD_FPGA
`else
.DSPCLK_insert_buf_o(DSPCLK_insert_buf_o),
`endif
.DSPCLK_cm0(DSPCLK_cm0),
.DSPCLK_cm1(DSPCLK_cm1),
.DSPCLK_cm2(DSPCLK_cm2),
.DSPCLK_pm0(DSPCLK_pm0),
.DSPCLK_pm1(DSPCLK_pm1),
.DSPCLK_pm2(DSPCLK_pm2),
.DSPCLK_dm0(DSPCLK_dm0),
.DSPCLK_dm1(DSPCLK_dm1),
.DSPCLK_dm2(DSPCLK_dm2),
.CLKO(CLKO),
.PWDACK(PWDACK),
.XTALoffn(XTALoffn),
.BGn(BGn),
.EA_oe(EA_oe),
.EA_do(EA_do[14:0]),
.PMSn(PMSn),
.DMSn(DMSn),
.BMSn(BMSn),
.IOSn(IOSn),
.CMSn(CMSn),
.RDn(RDn),
.WRn(WRn),
.ED_oe_15(ED_oe_15),
.ED_oe_14_8(ED_oe_14_8),
.ED_oe_7_0(ED_oe_7_0),
.ED_do(ED_do[15:0]),
.ECMSn(ECMSn),
.ECMA_EN(ECMA_EN),
.TD0(TD0),
.TD1(TD1),
.SCLK0(SCLK0),
.ISCLK0(ISCLK0),
.SCLK1(SCLK1),
.ISCLK1(ISCLK1),
.RFS0(RFS0),
.IRFS0(IRFS0),
.TFS0(TFS0),
.ITFS0(ITFS0),
.RFS1(RFS1),
.IRFS1(IRFS1),
.TFS1(TFS1),
.ITFS1(ITFS1),
.IACKn(IACKn),
.IAD_oe(IAD_oe),
.IAD_do(IAD_do[15:0]),
.PIO_oe(PIO_oe[11:0]),
.PIO_out(PIO_out[11:0]),
.IDo(IDo),
.IDoe(IDoe),
.PMo_cs0(PMo_cs0),
.PMo_cs1(PMo_cs1),
.PMo_cs2(PMo_cs2),
.PMo_cs3(PMo_cs3),
.PMo_cs4(PMo_cs4),
.PMo_cs5(PMo_cs5),
.PMo_cs6(PMo_cs6),
.PMo_cs7(PMo_cs7),
.PMo_web(PMo_web),
.PMo_oe0(PMo_oe0),
.PMo_oe1(PMo_oe1),
.PMo_oe2(PMo_oe2),
.PMo_oe3(PMo_oe3),
.PMo_oe4(PMo_oe4),
.PMo_oe5(PMo_oe5),
.PMo_oe6(PMo_oe6),
.PMo_oe7(PMo_oe7),
.PM_wd(PM_wd[15:0]),
.PMAinx(PMAinx[13:0]),
.DM_cs(DM_cs),
.DMo_cs0(DMo_cs0),
.DMo_cs1(DMo_cs1),
.DMo_cs2(DMo_cs2),
.DMo_cs3(DMo_cs3),
.DMo_cs4(DMo_cs4),
.DMo_cs5(DMo_cs5),
.DMo_cs6(DMo_cs6),
.DMo_cs7(DMo_cs7),
.DMo_web(DMo_web),
.DM_oe(DM_oe),
.DMo_oe0(DMo_oe0),
.DMo_oe1(DMo_oe1),
.DMo_oe2(DMo_oe2),
.DMo_oe3(DMo_oe3),
.DMo_oe4(DMo_oe4),
.DMo_oe5(DMo_oe5),
.DMo_oe6(DMo_oe6),
.DMo_oe7(DMo_oe7),
.DM_wd(DM_wd[15:0]),
.DMAinx(DMAinx[13:0]),
.CM_cs(CM_cs),
.CMo_cs0(CMo_cs0),
.CMo_cs1(CMo_cs1),
.CMo_cs2(CMo_cs2),
.CMo_cs3(CMo_cs3),
.CMo_cs4(CMo_cs4),
.CMo_cs5(CMo_cs5),
.CMo_cs6(CMo_cs6),
.CMo_cs7(CMo_cs7),
.CM_web(CM_web),
.CM_oe(CM_oe),
.CMo_oe0(CMo_oe0),
.CMo_oe1(CMo_oe1),
.CMo_oe2(CMo_oe2),
.CMo_oe3(CMo_oe3),
.CMo_oe4(CMo_oe4),
.CMo_oe5(CMo_oe5),
.CMo_oe6(CMo_oe6),
.CMo_oe7(CMo_oe7),
.CM_wd(CM_wd[23:0]),
.CMAinx(CMAinx[13:0])
`ifdef FD_DFT
,
.VC_SO(VC_SO[7:0]),
.WP_SO(WP_SO),
.TC_SO(TC_SO)
`endif
);
`ifdef FD_EVB
`else
PLL pll (
.T_PLLsel(T_PLLsel[3:0]),
.CLKI(T_CLKI_OSC),
.CLKO(T_CLKI_PLL),
.PDN(XTALoffn),
.Sel_PLL(T_Sel_PLL)
);
`endif
`ifdef FD_EVB
CM8K
cmm (.addr(CMAinx[12:0]),
.wd(CM_wd[23:0]),
.cs(CM_cs),
.oe(1'b1),
.rd(CM_rdm[23:0]),
.web(CM_web),
.clk(DSPCLK_cm0)
);
CMo4K
cm0 (.addr(CMAinx[11:0]),
.wd(CM_wd[23:0]),
.cs(CMo_cs0),
.oe(1'b1),
.rd(CM_rd0[23:0]),
.web(CM_web),
.clk(DSPCLK_cm0)
);
CMo4K
cm1 (.addr(CMAinx[11:0]),
.wd(CM_wd[23:0]),
.cs(CMo_cs1),
.oe(1'b1),
.rd(CM_rd1[23:0]),
.web(CM_web),
.clk(DSPCLK_cm1)
);
CMo4K
cm2 (.addr(CMAinx[11:0]),
.wd(CM_wd[23:0]),
.cs(CMo_cs2),
.oe(1'b1),
.rd(CM_rd2[23:0]),
.web(CM_web),
.clk(DSPCLK_cm1)
);
CMo4K
cm3 (.addr(CMAinx[11:0]),
.wd(CM_wd[23:0]),
.cs(CMo_cs3),
.oe(1'b1),
.rd(CM_rd3[23:0]),
.web(CM_web),
.clk(DSPCLK_cm2)
);
PMo4K
pm0 (.addr(PMAinx[11:0]),
.wd(PM_wd[15:0]),
.cs(PMo_cs0),
.oe(1'b1),
.rd(PM_rd0[15:0]),
.web(PMo_web),
.clk(DSPCLK_pm0)
);
PMo4K
pm1 (.addr(PMAinx[11:0]),
.wd(PM_wd[15:0]),
.cs(PMo_cs1),
.oe(1'b1),
.rd(PM_rd1[15:0]),
.web(PMo_web),
.clk(DSPCLK_pm1)
);
DMo8K
dm0 (.addr(DMAinx[12:0]),
.wd(DM_wd[15:0]),
.cs(DMo_cs0),
.oe(1'b1),
.rd(DM_rd0[15:0]),
.web(DMo_web),
.clk(DSPCLK_dm0)
);
`else
`ifdef FD_PM8K
SU210010
`else
SU208010
`endif
pm0 (.A0(PMAinx[0]),
.A1(PMAinx[1]),
.A2(PMAinx[2]),
.A3(PMAinx[3]),
.A4(PMAinx[4]),
.A5(PMAinx[5]),
.A6(PMAinx[6]),
.A7(PMAinx[7]),
.A8(PMAinx[8]),
.A9(PMAinx[9]),
.A10(PMAinx[10]),
.A11(PMAinx[11]),
`ifdef FD_PM8K
.A12(PMAinx[12]),
`endif
.DO0(PM_rd0[0]),
.DO1(PM_rd0[1]),
.DO2(PM_rd0[2]),
.DO3(PM_rd0[3]),
.DO4(PM_rd0[4]),
.DO5(PM_rd0[5]),
.DO6(PM_rd0[6]),
.DO7(PM_rd0[7]),
.DO8(PM_rd0[8]),
.DO9(PM_rd0[9]),
.DO10(PM_rd0[10]),
.DO11(PM_rd0[11]),
.DO12(PM_rd0[12]),
.DO13(PM_rd0[13]),
.DO14(PM_rd0[14]),
.DO15(PM_rd0[15]),
.DI0(PM_wd[0]),
.DI1(PM_wd[1]),
.DI2(PM_wd[2]),
.DI3(PM_wd[3]),
.DI4(PM_wd[4]),
.DI5(PM_wd[5]),
.DI6(PM_wd[6]),
.DI7(PM_wd[7]),
.DI8(PM_wd[8]),
.DI9(PM_wd[9]),
.DI10(PM_wd[10]),
.DI11(PM_wd[11]),
.DI12(PM_wd[12]),
.DI13(PM_wd[13]),
.DI14(PM_wd[14]),
.DI15(PM_wd[15]),
.CK(DSPCLK_pm0),
.WEB(PMo_web),
.CS(PMo_cs0),
.OE(1'b1)
);
`ifdef FD_PM8K
SU210010
`else
SU208010
`endif
pm1 (.A0(PMAinx[0]),
.A1(PMAinx[1]),
.A2(PMAinx[2]),
.A3(PMAinx[3]),
.A4(PMAinx[4]),
.A5(PMAinx[5]),
.A6(PMAinx[6]),
.A7(PMAinx[7]),
.A8(PMAinx[8]),
.A9(PMAinx[9]),
.A10(PMAinx[10]),
.A11(PMAinx[11]),
`ifdef FD_PM8K
.A12(PMAinx[12]),
`endif
.DO0(PM_rd1[0]),
.DO1(PM_rd1[1]),
.DO2(PM_rd1[2]),
.DO3(PM_rd1[3]),
.DO4(PM_rd1[4]),
.DO5(PM_rd1[5]),
.DO6(PM_rd1[6]),
.DO7(PM_rd1[7]),
.DO8(PM_rd1[8]),
.DO9(PM_rd1[9]),
.DO10(PM_rd1[10]),
.DO11(PM_rd1[11]),
.DO12(PM_rd1[12]),
.DO13(PM_rd1[13]),
.DO14(PM_rd1[14]),
.DO15(PM_rd1[15]),
.DI0(PM_wd[0]),
.DI1(PM_wd[1]),
.DI2(PM_wd[2]),
.DI3(PM_wd[3]),
.DI4(PM_wd[4]),
.DI5(PM_wd[5]),
.DI6(PM_wd[6]),
.DI7(PM_wd[7]),
.DI8(PM_wd[8]),
.DI9(PM_wd[9]),
.DI10(PM_wd[10]),
.DI11(PM_wd[11]),
.DI12(PM_wd[12]),
.DI13(PM_wd[13]),
.DI14(PM_wd[14]),
.DI15(PM_wd[15]),
.CK(DSPCLK_pm0),
.WEB(PMo_web),
.CS(PMo_cs1),
.OE(PMo_oe1)
);
`ifdef FD_PM8K
SU210010
`else
SU208010
`endif
pm2 (.A0(PMAinx[0]),
.A1(PMAinx[1]),
.A2(PMAinx[2]),
.A3(PMAinx[3]),
.A4(PMAinx[4]),
.A5(PMAinx[5]),
.A6(PMAinx[6]),
.A7(PMAinx[7]),
.A8(PMAinx[8]),
.A9(PMAinx[9]),
.A10(PMAinx[10]),
.A11(PMAinx[11]),
`ifdef FD_PM8K
.A12(PMAinx[12]),
`endif
.DO0(PM_rd2[0]),
.DO1(PM_rd2[1]),
.DO2(PM_rd2[2]),
.DO3(PM_rd2[3]),
.DO4(PM_rd2[4]),
.DO5(PM_rd2[5]),
.DO6(PM_rd2[6]),
.DO7(PM_rd2[7]),
.DO8(PM_rd2[8]),
.DO9(PM_rd2[9]),
.DO10(PM_rd2[10]),
.DO11(PM_rd2[11]),
.DO12(PM_rd2[12]),
.DO13(PM_rd2[13]),
.DO14(PM_rd2[14]),
.DO15(PM_rd2[15]),
.DI0(PM_wd[0]),
.DI1(PM_wd[1]),
.DI2(PM_wd[2]),
.DI3(PM_wd[3]),
.DI4(PM_wd[4]),
.DI5(PM_wd[5]),
.DI6(PM_wd[6]),
.DI7(PM_wd[7]),
.DI8(PM_wd[8]),
.DI9(PM_wd[9]),
.DI10(PM_wd[10]),
.DI11(PM_wd[11]),
.DI12(PM_wd[12]),
.DI13(PM_wd[13]),
.DI14(PM_wd[14]),
.DI15(PM_wd[15]),
.CK(DSPCLK_pm0),
.WEB(PMo_web),
.CS(PMo_cs2),
.OE(PMo_oe2)
);
`ifdef FD_PM8K
SU210010
`else
SU208010
`endif
pm3 (.A0(PMAinx[0]),
.A1(PMAinx[1]),
.A2(PMAinx[2]),
.A3(PMAinx[3]),
.A4(PMAinx[4]),
.A5(PMAinx[5]),
.A6(PMAinx[6]),
.A7(PMAinx[7]),
.A8(PMAinx[8]),
.A9(PMAinx[9]),
.A10(PMAinx[10]),
.A11(PMAinx[11]),
`ifdef FD_PM8K
.A12(PMAinx[12]),
`endif
.DO0(PM_rd3[0]),
.DO1(PM_rd3[1]),
.DO2(PM_rd3[2]),
.DO3(PM_rd3[3]),
.DO4(PM_rd3[4]),
.DO5(PM_rd3[5]),
.DO6(PM_rd3[6]),
.DO7(PM_rd3[7]),
.DO8(PM_rd3[8]),
.DO9(PM_rd3[9]),
.DO10(PM_rd3[10]),
.DO11(PM_rd3[11]),
.DO12(PM_rd3[12]),
.DO13(PM_rd3[13]),
.DO14(PM_rd3[14]),
.DO15(PM_rd3[15]),
.DI0(PM_wd[0]),
.DI1(PM_wd[1]),
.DI2(PM_wd[2]),
.DI3(PM_wd[3]),
.DI4(PM_wd[4]),
.DI5(PM_wd[5]),
.DI6(PM_wd[6]),
.DI7(PM_wd[7]),
.DI8(PM_wd[8]),
.DI9(PM_wd[9]),
.DI10(PM_wd[10]),
.DI11(PM_wd[11]),
.DI12(PM_wd[12]),
.DI13(PM_wd[13]),
.DI14(PM_wd[14]),
.DI15(PM_wd[15]),
.CK(DSPCLK_pm1),
.WEB(PMo_web),
.CS(PMo_cs3),
.OE(PMo_oe3)
);
`ifdef FD_PM8K
SU210010
`else
SU208010
`endif
pm4 (.A0(PMAinx[0]),
.A1(PMAinx[1]),
.A2(PMAinx[2]),
.A3(PMAinx[3]),
.A4(PMAinx[4]),
.A5(PMAinx[5]),
.A6(PMAinx[6]),
.A7(PMAinx[7]),
.A8(PMAinx[8]),
.A9(PMAinx[9]),
.A10(PMAinx[10]),
.A11(PMAinx[11]),
`ifdef FD_PM8K
.A12(PMAinx[12]),
`endif
.DO0(PM_rd4[0]),
.DO1(PM_rd4[1]),
.DO2(PM_rd4[2]),
.DO3(PM_rd4[3]),
.DO4(PM_rd4[4]),
.DO5(PM_rd4[5]),
.DO6(PM_rd4[6]),
.DO7(PM_rd4[7]),
.DO8(PM_rd4[8]),
.DO9(PM_rd4[9]),
.DO10(PM_rd4[10]),
.DO11(PM_rd4[11]),
.DO12(PM_rd4[12]),
.DO13(PM_rd4[13]),
.DO14(PM_rd4[14]),
.DO15(PM_rd4[15]),
.DI0(PM_wd[0]),
.DI1(PM_wd[1]),
.DI2(PM_wd[2]),
.DI3(PM_wd[3]),
.DI4(PM_wd[4]),
.DI5(PM_wd[5]),
.DI6(PM_wd[6]),
.DI7(PM_wd[7]),
.DI8(PM_wd[8]),
.DI9(PM_wd[9]),
.DI10(PM_wd[10]),
.DI11(PM_wd[11]),
.DI12(PM_wd[12]),
.DI13(PM_wd[13]),
.DI14(PM_wd[14]),
.DI15(PM_wd[15]),
.CK(DSPCLK_pm1),
.WEB(PMo_web),
.CS(PMo_cs4),
.OE(PMo_oe4)
);
`ifdef FD_PM8K
SU210010
`else
SU208010
`endif
pm5 (.A0(PMAinx[0]),
.A1(PMAinx[1]),
.A2(PMAinx[2]),
.A3(PMAinx[3]),
.A4(PMAinx[4]),
.A5(PMAinx[5]),
.A6(PMAinx[6]),
.A7(PMAinx[7]),
.A8(PMAinx[8]),
.A9(PMAinx[9]),
.A10(PMAinx[10]),
.A11(PMAinx[11]),
`ifdef FD_PM8K
.A12(PMAinx[12]),
`endif
.DO0(PM_rd5[0]),
.DO1(PM_rd5[1]),
.DO2(PM_rd5[2]),
.DO3(PM_rd5[3]),
.DO4(PM_rd5[4]),
.DO5(PM_rd5[5]),
.DO6(PM_rd5[6]),
.DO7(PM_rd5[7]),
.DO8(PM_rd5[8]),
.DO9(PM_rd5[9]),
.DO10(PM_rd5[10]),
.DO11(PM_rd5[11]),
.DO12(PM_rd5[12]),
.DO13(PM_rd5[13]),
.DO14(PM_rd5[14]),
.DO15(PM_rd5[15]),
.DI0(PM_wd[0]),
.DI1(PM_wd[1]),
.DI2(PM_wd[2]),
.DI3(PM_wd[3]),
.DI4(PM_wd[4]),
.DI5(PM_wd[5]),
.DI6(PM_wd[6]),
.DI7(PM_wd[7]),
.DI8(PM_wd[8]),
.DI9(PM_wd[9]),
.DI10(PM_wd[10]),
.DI11(PM_wd[11]),
.DI12(PM_wd[12]),
.DI13(PM_wd[13]),
.DI14(PM_wd[14]),
.DI15(PM_wd[15]),
.CK(DSPCLK_pm1),
.WEB(PMo_web),
.CS(PMo_cs5),
.OE(PMo_oe5)
);
`ifdef FD_PM8K
SU210010
`else
SU208010
`endif
pm6 (.A0(PMAinx[0]),
.A1(PMAinx[1]),
.A2(PMAinx[2]),
.A3(PMAinx[3]),
.A4(PMAinx[4]),
.A5(PMAinx[5]),
.A6(PMAinx[6]),
.A7(PMAinx[7]),
.A8(PMAinx[8]),
.A9(PMAinx[9]),
.A10(PMAinx[10]),
.A11(PMAinx[11]),
`ifdef FD_PM8K
.A12(PMAinx[12]),
`endif
.DO0(PM_rd6[0]),
.DO1(PM_rd6[1]),
.DO2(PM_rd6[2]),
.DO3(PM_rd6[3]),
.DO4(PM_rd6[4]),
.DO5(PM_rd6[5]),
.DO6(PM_rd6[6]),
.DO7(PM_rd6[7]),
.DO8(PM_rd6[8]),
.DO9(PM_rd6[9]),
.DO10(PM_rd6[10]),
.DO11(PM_rd6[11]),
.DO12(PM_rd6[12]),
.DO13(PM_rd6[13]),
.DO14(PM_rd6[14]),
.DO15(PM_rd6[15]),
.DI0(PM_wd[0]),
.DI1(PM_wd[1]),
.DI2(PM_wd[2]),
.DI3(PM_wd[3]),
.DI4(PM_wd[4]),
.DI5(PM_wd[5]),
.DI6(PM_wd[6]),
.DI7(PM_wd[7]),
.DI8(PM_wd[8]),
.DI9(PM_wd[9]),
.DI10(PM_wd[10]),
.DI11(PM_wd[11]),
.DI12(PM_wd[12]),
.DI13(PM_wd[13]),
.DI14(PM_wd[14]),
.DI15(PM_wd[15]),
.CK(DSPCLK_pm2),
.WEB(PMo_web),
.CS(PMo_cs6),
.OE(PMo_oe6)
);
`ifdef FD_PM8K
SU210010
`else
SU208010
`endif
pm7 (.A0(PMAinx[0]),
.A1(PMAinx[1]),
.A2(PMAinx[2]),
.A3(PMAinx[3]),
.A4(PMAinx[4]),
.A5(PMAinx[5]),
.A6(PMAinx[6]),
.A7(PMAinx[7]),
.A8(PMAinx[8]),
.A9(PMAinx[9]),
.A10(PMAinx[10]),
.A11(PMAinx[11]),
`ifdef FD_PM8K
.A12(PMAinx[12]),
`endif
.DO0(PM_rd7[0]),
.DO1(PM_rd7[1]),
.DO2(PM_rd7[2]),
.DO3(PM_rd7[3]),
.DO4(PM_rd7[4]),
.DO5(PM_rd7[5]),
.DO6(PM_rd7[6]),
.DO7(PM_rd7[7]),
.DO8(PM_rd7[8]),
.DO9(PM_rd7[9]),
.DO10(PM_rd7[10]),
.DO11(PM_rd7[11]),
.DO12(PM_rd7[12]),
.DO13(PM_rd7[13]),
.DO14(PM_rd7[14]),
.DO15(PM_rd7[15]),
.DI0(PM_wd[0]),
.DI1(PM_wd[1]),
.DI2(PM_wd[2]),
.DI3(PM_wd[3]),
.DI4(PM_wd[4]),
.DI5(PM_wd[5]),
.DI6(PM_wd[6]),
.DI7(PM_wd[7]),
.DI8(PM_wd[8]),
.DI9(PM_wd[9]),
.DI10(PM_wd[10]),
.DI11(PM_wd[11]),
.DI12(PM_wd[12]),
.DI13(PM_wd[13]),
.DI14(PM_wd[14]),
.DI15(PM_wd[15]),
.CK(DSPCLK_pm2),
.WEB(PMo_web),
.CS(PMo_cs7),
.OE(PMo_oe7)
);
`ifdef FD_PM8K
SU208018
`else
SU210018
`endif
cmm (.A0(CMAinx[0]),
.A1(CMAinx[1]),
.A2(CMAinx[2]),
.A3(CMAinx[3]),
.A4(CMAinx[4]),
.A5(CMAinx[5]),
.A6(CMAinx[6]),
.A7(CMAinx[7]),
.A8(CMAinx[8]),
.A9(CMAinx[9]),
.A10(CMAinx[10]),
.A11(CMAinx[11]),
`ifdef FD_PM8K
`else
.A12(CMAinx[12]),
`endif
.DO0(CM_rdm[0]),
.DO1(CM_rdm[1]),
.DO2(CM_rdm[2]),
.DO3(CM_rdm[3]),
.DO4(CM_rdm[4]),
.DO5(CM_rdm[5]),
.DO6(CM_rdm[6]),
.DO7(CM_rdm[7]),
.DO8(CM_rdm[8]),
.DO9(CM_rdm[9]),
.DO10(CM_rdm[10]),
.DO11(CM_rdm[11]),
.DO12(CM_rdm[12]),
.DO13(CM_rdm[13]),
.DO14(CM_rdm[14]),
.DO15(CM_rdm[15]),
.DO16(CM_rdm[16]),
.DO17(CM_rdm[17]),
.DO18(CM_rdm[18]),
.DO19(CM_rdm[19]),
.DO20(CM_rdm[20]),
.DO21(CM_rdm[21]),
.DO22(CM_rdm[22]),
.DO23(CM_rdm[23]),
.DI0(CM_wd[0]),
.DI1(CM_wd[1]),
.DI2(CM_wd[2]),
.DI3(CM_wd[3]),
.DI4(CM_wd[4]),
.DI5(CM_wd[5]),
.DI6(CM_wd[6]),
.DI7(CM_wd[7]),
.DI8(CM_wd[8]),
.DI9(CM_wd[9]),
.DI10(CM_wd[10]),
.DI11(CM_wd[11]),
.DI12(CM_wd[12]),
.DI13(CM_wd[13]),
.DI14(CM_wd[14]),
.DI15(CM_wd[15]),
.DI16(CM_wd[16]),
.DI17(CM_wd[17]),
.DI18(CM_wd[18]),
.DI19(CM_wd[19]),
.DI20(CM_wd[20]),
.DI21(CM_wd[21]),
.DI22(CM_wd[22]),
.DI23(CM_wd[23]),
.CK(DSPCLK_cm0),
.WEB(CM_web),
.CS(CM_cs),
.OE(1'b1)
);
SU208018
cm0 (.A0(CMAinx[0]),
.A1(CMAinx[1]),
.A2(CMAinx[2]),
.A3(CMAinx[3]),
.A4(CMAinx[4]),
.A5(CMAinx[5]),
.A6(CMAinx[6]),
.A7(CMAinx[7]),
.A8(CMAinx[8]),
.A9(CMAinx[9]),
.A10(CMAinx[10]),
.A11(CMAinx[11]),
.DO0(CM_rd0[0]),
.DO1(CM_rd0[1]),
.DO2(CM_rd0[2]),
.DO3(CM_rd0[3]),
.DO4(CM_rd0[4]),
.DO5(CM_rd0[5]),
.DO6(CM_rd0[6]),
.DO7(CM_rd0[7]),
.DO8(CM_rd0[8]),
.DO9(CM_rd0[9]),
.DO10(CM_rd0[10]),
.DO11(CM_rd0[11]),
.DO12(CM_rd0[12]),
.DO13(CM_rd0[13]),
.DO14(CM_rd0[14]),
.DO15(CM_rd0[15]),
.DO16(CM_rd0[16]),
.DO17(CM_rd0[17]),
.DO18(CM_rd0[18]),
.DO19(CM_rd0[19]),
.DO20(CM_rd0[20]),
.DO21(CM_rd0[21]),
.DO22(CM_rd0[22]),
.DO23(CM_rd0[23]),
.DI0(CM_wd[0]),
.DI1(CM_wd[1]),
.DI2(CM_wd[2]),
.DI3(CM_wd[3]),
.DI4(CM_wd[4]),
.DI5(CM_wd[5]),
.DI6(CM_wd[6]),
.DI7(CM_wd[7]),
.DI8(CM_wd[8]),
.DI9(CM_wd[9]),
.DI10(CM_wd[10]),
.DI11(CM_wd[11]),
.DI12(CM_wd[12]),
.DI13(CM_wd[13]),
.DI14(CM_wd[14]),
.DI15(CM_wd[15]),
.DI16(CM_wd[16]),
.DI17(CM_wd[17]),
.DI18(CM_wd[18]),
.DI19(CM_wd[19]),
.DI20(CM_wd[20]),
.DI21(CM_wd[21]),
.DI22(CM_wd[22]),
.DI23(CM_wd[23]),
.CK(DSPCLK_cm0),
.WEB(CM_web),
.CS(CMo_cs0),
.OE(CMo_oe0)
);
SU208018
cm1 (.A0(CMAinx[0]),
.A1(CMAinx[1]),
.A2(CMAinx[2]),
.A3(CMAinx[3]),
.A4(CMAinx[4]),
.A5(CMAinx[5]),
.A6(CMAinx[6]),
.A7(CMAinx[7]),
.A8(CMAinx[8]),
.A9(CMAinx[9]),
.A10(CMAinx[10]),
.A11(CMAinx[11]),
.DO0(CM_rd1[0]),
.DO1(CM_rd1[1]),
.DO2(CM_rd1[2]),
.DO3(CM_rd1[3]),
.DO4(CM_rd1[4]),
.DO5(CM_rd1[5]),
.DO6(CM_rd1[6]),
.DO7(CM_rd1[7]),
.DO8(CM_rd1[8]),
.DO9(CM_rd1[9]),
.DO10(CM_rd1[10]),
.DO11(CM_rd1[11]),
.DO12(CM_rd1[12]),
.DO13(CM_rd1[13]),
.DO14(CM_rd1[14]),
.DO15(CM_rd1[15]),
.DO16(CM_rd1[16]),
.DO17(CM_rd1[17]),
.DO18(CM_rd1[18]),
.DO19(CM_rd1[19]),
.DO20(CM_rd1[20]),
.DO21(CM_rd1[21]),
.DO22(CM_rd1[22]),
.DO23(CM_rd1[23]),
.DI0(CM_wd[0]),
.DI1(CM_wd[1]),
.DI2(CM_wd[2]),
.DI3(CM_wd[3]),
.DI4(CM_wd[4]),
.DI5(CM_wd[5]),
.DI6(CM_wd[6]),
.DI7(CM_wd[7]),
.DI8(CM_wd[8]),
.DI9(CM_wd[9]),
.DI10(CM_wd[10]),
.DI11(CM_wd[11]),
.DI12(CM_wd[12]),
.DI13(CM_wd[13]),
.DI14(CM_wd[14]),
.DI15(CM_wd[15]),
.DI16(CM_wd[16]),
.DI17(CM_wd[17]),
.DI18(CM_wd[18]),
.DI19(CM_wd[19]),
.DI20(CM_wd[20]),
.DI21(CM_wd[21]),
.DI22(CM_wd[22]),
.DI23(CM_wd[23]),
.CK(DSPCLK_cm0),
.WEB(CM_web),
.CS(CMo_cs1),
.OE(CMo_oe1)
);
SU208018
cm2 (.A0(CMAinx[0]),
.A1(CMAinx[1]),
.A2(CMAinx[2]),
.A3(CMAinx[3]),
.A4(CMAinx[4]),
.A5(CMAinx[5]),
.A6(CMAinx[6]),
.A7(CMAinx[7]),
.A8(CMAinx[8]),
.A9(CMAinx[9]),
.A10(CMAinx[10]),
.A11(CMAinx[11]),
.DO0(CM_rd2[0]),
.DO1(CM_rd2[1]),
.DO2(CM_rd2[2]),
.DO3(CM_rd2[3]),
.DO4(CM_rd2[4]),
.DO5(CM_rd2[5]),
.DO6(CM_rd2[6]),
.DO7(CM_rd2[7]),
.DO8(CM_rd2[8]),
.DO9(CM_rd2[9]),
.DO10(CM_rd2[10]),
.DO11(CM_rd2[11]),
.DO12(CM_rd2[12]),
.DO13(CM_rd2[13]),
.DO14(CM_rd2[14]),
.DO15(CM_rd2[15]),
.DO16(CM_rd2[16]),
.DO17(CM_rd2[17]),
.DO18(CM_rd2[18]),
.DO19(CM_rd2[19]),
.DO20(CM_rd2[20]),
.DO21(CM_rd2[21]),
.DO22(CM_rd2[22]),
.DO23(CM_rd2[23]),
.DI0(CM_wd[0]),
.DI1(CM_wd[1]),
.DI2(CM_wd[2]),
.DI3(CM_wd[3]),
.DI4(CM_wd[4]),
.DI5(CM_wd[5]),
.DI6(CM_wd[6]),
.DI7(CM_wd[7]),
.DI8(CM_wd[8]),
.DI9(CM_wd[9]),
.DI10(CM_wd[10]),
.DI11(CM_wd[11]),
.DI12(CM_wd[12]),
.DI13(CM_wd[13]),
.DI14(CM_wd[14]),
.DI15(CM_wd[15]),
.DI16(CM_wd[16]),
.DI17(CM_wd[17]),
.DI18(CM_wd[18]),
.DI19(CM_wd[19]),
.DI20(CM_wd[20]),
.DI21(CM_wd[21]),
.DI22(CM_wd[22]),
.DI23(CM_wd[23]),
.CK(DSPCLK_cm1),
.WEB(CM_web),
.CS(CMo_cs2),
.OE(CMo_oe2)
);
SU208018
cm3 (.A0(CMAinx[0]),
.A1(CMAinx[1]),
.A2(CMAinx[2]),
.A3(CMAinx[3]),
.A4(CMAinx[4]),
.A5(CMAinx[5]),
.A6(CMAinx[6]),
.A7(CMAinx[7]),
.A8(CMAinx[8]),
.A9(CMAinx[9]),
.A10(CMAinx[10]),
.A11(CMAinx[11]),
.DO0(CM_rd3[0]),
.DO1(CM_rd3[1]),
.DO2(CM_rd3[2]),
.DO3(CM_rd3[3]),
.DO4(CM_rd3[4]),
.DO5(CM_rd3[5]),
.DO6(CM_rd3[6]),
.DO7(CM_rd3[7]),
.DO8(CM_rd3[8]),
.DO9(CM_rd3[9]),
.DO10(CM_rd3[10]),
.DO11(CM_rd3[11]),
.DO12(CM_rd3[12]),
.DO13(CM_rd3[13]),
.DO14(CM_rd3[14]),
.DO15(CM_rd3[15]),
.DO16(CM_rd3[16]),
.DO17(CM_rd3[17]),
.DO18(CM_rd3[18]),
.DO19(CM_rd3[19]),
.DO20(CM_rd3[20]),
.DO21(CM_rd3[21]),
.DO22(CM_rd3[22]),
.DO23(CM_rd3[23]),
.DI0(CM_wd[0]),
.DI1(CM_wd[1]),
.DI2(CM_wd[2]),
.DI3(CM_wd[3]),
.DI4(CM_wd[4]),
.DI5(CM_wd[5]),
.DI6(CM_wd[6]),
.DI7(CM_wd[7]),
.DI8(CM_wd[8]),
.DI9(CM_wd[9]),
.DI10(CM_wd[10]),
.DI11(CM_wd[11]),
.DI12(CM_wd[12]),
.DI13(CM_wd[13]),
.DI14(CM_wd[14]),
.DI15(CM_wd[15]),
.DI16(CM_wd[16]),
.DI17(CM_wd[17]),
.DI18(CM_wd[18]),
.DI19(CM_wd[19]),
.DI20(CM_wd[20]),
.DI21(CM_wd[21]),
.DI22(CM_wd[22]),
.DI23(CM_wd[23]),
.CK(DSPCLK_cm1),
.WEB(CM_web),
.CS(CMo_cs3),
.OE(CMo_oe3)
);
SU208018
cm4 (.A0(CMAinx[0]),
.A1(CMAinx[1]),
.A2(CMAinx[2]),
.A3(CMAinx[3]),
.A4(CMAinx[4]),
.A5(CMAinx[5]),
.A6(CMAinx[6]),
.A7(CMAinx[7]),
.A8(CMAinx[8]),
.A9(CMAinx[9]),
.A10(CMAinx[10]),
.A11(CMAinx[11]),
.DO0(CM_rd4[0]),
.DO1(CM_rd4[1]),
.DO2(CM_rd4[2]),
.DO3(CM_rd4[3]),
.DO4(CM_rd4[4]),
.DO5(CM_rd4[5]),
.DO6(CM_rd4[6]),
.DO7(CM_rd4[7]),
.DO8(CM_rd4[8]),
.DO9(CM_rd4[9]),
.DO10(CM_rd4[10]),
.DO11(CM_rd4[11]),
.DO12(CM_rd4[12]),
.DO13(CM_rd4[13]),
.DO14(CM_rd4[14]),
.DO15(CM_rd4[15]),
.DO16(CM_rd4[16]),
.DO17(CM_rd4[17]),
.DO18(CM_rd4[18]),
.DO19(CM_rd4[19]),
.DO20(CM_rd4[20]),
.DO21(CM_rd4[21]),
.DO22(CM_rd4[22]),
.DO23(CM_rd4[23]),
.DI0(CM_wd[0]),
.DI1(CM_wd[1]),
.DI2(CM_wd[2]),
.DI3(CM_wd[3]),
.DI4(CM_wd[4]),
.DI5(CM_wd[5]),
.DI6(CM_wd[6]),
.DI7(CM_wd[7]),
.DI8(CM_wd[8]),
.DI9(CM_wd[9]),
.DI10(CM_wd[10]),
.DI11(CM_wd[11]),
.DI12(CM_wd[12]),
.DI13(CM_wd[13]),
.DI14(CM_wd[14]),
.DI15(CM_wd[15]),
.DI16(CM_wd[16]),
.DI17(CM_wd[17]),
.DI18(CM_wd[18]),
.DI19(CM_wd[19]),
.DI20(CM_wd[20]),
.DI21(CM_wd[21]),
.DI22(CM_wd[22]),
.DI23(CM_wd[23]),
.CK(DSPCLK_cm1),
.WEB(CM_web),
.CS(CMo_cs4),
.OE(CMo_oe4)
);
SU208018
cm5 (.A0(CMAinx[0]),
.A1(CMAinx[1]),
.A2(CMAinx[2]),
.A3(CMAinx[3]),
.A4(CMAinx[4]),
.A5(CMAinx[5]),
.A6(CMAinx[6]),
.A7(CMAinx[7]),
.A8(CMAinx[8]),
.A9(CMAinx[9]),
.A10(CMAinx[10]),
.A11(CMAinx[11]),
.DO0(CM_rd5[0]),
.DO1(CM_rd5[1]),
.DO2(CM_rd5[2]),
.DO3(CM_rd5[3]),
.DO4(CM_rd5[4]),
.DO5(CM_rd5[5]),
.DO6(CM_rd5[6]),
.DO7(CM_rd5[7]),
.DO8(CM_rd5[8]),
.DO9(CM_rd5[9]),
.DO10(CM_rd5[10]),
.DO11(CM_rd5[11]),
.DO12(CM_rd5[12]),
.DO13(CM_rd5[13]),
.DO14(CM_rd5[14]),
.DO15(CM_rd5[15]),
.DO16(CM_rd5[16]),
.DO17(CM_rd5[17]),
.DO18(CM_rd5[18]),
.DO19(CM_rd5[19]),
.DO20(CM_rd5[20]),
.DO21(CM_rd5[21]),
.DO22(CM_rd5[22]),
.DO23(CM_rd5[23]),
.DI0(CM_wd[0]),
.DI1(CM_wd[1]),
.DI2(CM_wd[2]),
.DI3(CM_wd[3]),
.DI4(CM_wd[4]),
.DI5(CM_wd[5]),
.DI6(CM_wd[6]),
.DI7(CM_wd[7]),
.DI8(CM_wd[8]),
.DI9(CM_wd[9]),
.DI10(CM_wd[10]),
.DI11(CM_wd[11]),
.DI12(CM_wd[12]),
.DI13(CM_wd[13]),
.DI14(CM_wd[14]),
.DI15(CM_wd[15]),
.DI16(CM_wd[16]),
.DI17(CM_wd[17]),
.DI18(CM_wd[18]),
.DI19(CM_wd[19]),
.DI20(CM_wd[20]),
.DI21(CM_wd[21]),
.DI22(CM_wd[22]),
.DI23(CM_wd[23]),
.CK(DSPCLK_cm2),
.WEB(CM_web),
.CS(CMo_cs5),
.OE(CMo_oe5)
);
SU208018
cm6 (.A0(CMAinx[0]),
.A1(CMAinx[1]),
.A2(CMAinx[2]),
.A3(CMAinx[3]),
.A4(CMAinx[4]),
.A5(CMAinx[5]),
.A6(CMAinx[6]),
.A7(CMAinx[7]),
.A8(CMAinx[8]),
.A9(CMAinx[9]),
.A10(CMAinx[10]),
.A11(CMAinx[11]),
.DO0(CM_rd6[0]),
.DO1(CM_rd6[1]),
.DO2(CM_rd6[2]),
.DO3(CM_rd6[3]),
.DO4(CM_rd6[4]),
.DO5(CM_rd6[5]),
.DO6(CM_rd6[6]),
.DO7(CM_rd6[7]),
.DO8(CM_rd6[8]),
.DO9(CM_rd6[9]),
.DO10(CM_rd6[10]),
.DO11(CM_rd6[11]),
.DO12(CM_rd6[12]),
.DO13(CM_rd6[13]),
.DO14(CM_rd6[14]),
.DO15(CM_rd6[15]),
.DO16(CM_rd6[16]),
.DO17(CM_rd6[17]),
.DO18(CM_rd6[18]),
.DO19(CM_rd6[19]),
.DO20(CM_rd6[20]),
.DO21(CM_rd6[21]),
.DO22(CM_rd6[22]),
.DO23(CM_rd6[23]),
.DI0(CM_wd[0]),
.DI1(CM_wd[1]),
.DI2(CM_wd[2]),
.DI3(CM_wd[3]),
.DI4(CM_wd[4]),
.DI5(CM_wd[5]),
.DI6(CM_wd[6]),
.DI7(CM_wd[7]),
.DI8(CM_wd[8]),
.DI9(CM_wd[9]),
.DI10(CM_wd[10]),
.DI11(CM_wd[11]),
.DI12(CM_wd[12]),
.DI13(CM_wd[13]),
.DI14(CM_wd[14]),
.DI15(CM_wd[15]),
.DI16(CM_wd[16]),
.DI17(CM_wd[17]),
.DI18(CM_wd[18]),
.DI19(CM_wd[19]),
.DI20(CM_wd[20]),
.DI21(CM_wd[21]),
.DI22(CM_wd[22]),
.DI23(CM_wd[23]),
.CK(DSPCLK_cm2),
.WEB(CM_web),
.CS(CMo_cs6),
.OE(CMo_oe6)
);
SU208018
cm7 (.A0(CMAinx[0]),
.A1(CMAinx[1]),
.A2(CMAinx[2]),
.A3(CMAinx[3]),
.A4(CMAinx[4]),
.A5(CMAinx[5]),
.A6(CMAinx[6]),
.A7(CMAinx[7]),
.A8(CMAinx[8]),
.A9(CMAinx[9]),
.A10(CMAinx[10]),
.A11(CMAinx[11]),
.DO0(CM_rd7[0]),
.DO1(CM_rd7[1]),
.DO2(CM_rd7[2]),
.DO3(CM_rd7[3]),
.DO4(CM_rd7[4]),
.DO5(CM_rd7[5]),
.DO6(CM_rd7[6]),
.DO7(CM_rd7[7]),
.DO8(CM_rd7[8]),
.DO9(CM_rd7[9]),
.DO10(CM_rd7[10]),
.DO11(CM_rd7[11]),
.DO12(CM_rd7[12]),
.DO13(CM_rd7[13]),
.DO14(CM_rd7[14]),
.DO15(CM_rd7[15]),
.DO16(CM_rd7[16]),
.DO17(CM_rd7[17]),
.DO18(CM_rd7[18]),
.DO19(CM_rd7[19]),
.DO20(CM_rd7[20]),
.DO21(CM_rd7[21]),
.DO22(CM_rd7[22]),
.DO23(CM_rd7[23]),
.DI0(CM_wd[0]),
.DI1(CM_wd[1]),
.DI2(CM_wd[2]),
.DI3(CM_wd[3]),
.DI4(CM_wd[4]),
.DI5(CM_wd[5]),
.DI6(CM_wd[6]),
.DI7(CM_wd[7]),
.DI8(CM_wd[8]),
.DI9(CM_wd[9]),
.DI10(CM_wd[10]),
.DI11(CM_wd[11]),
.DI12(CM_wd[12]),
.DI13(CM_wd[13]),
.DI14(CM_wd[14]),
.DI15(CM_wd[15]),
.DI16(CM_wd[16]),
.DI17(CM_wd[17]),
.DI18(CM_wd[18]),
.DI19(CM_wd[19]),
.DI20(CM_wd[20]),
.DI21(CM_wd[21]),
.DI22(CM_wd[22]),
.DI23(CM_wd[23]),
.CK(DSPCLK_cm2),
.WEB(CM_web),
.CS(CMo_cs7),
.OE(CMo_oe7)
);
SU20E010
dmm (.A0(DMAinx[0]),
.A1(DMAinx[1]),
.A2(DMAinx[2]),
.A3(DMAinx[3]),
.A4(DMAinx[4]),
.A5(DMAinx[5]),
.A6(DMAinx[6]),
.A7(DMAinx[7]),
.A8(DMAinx[8]),
.A9(DMAinx[9]),
.A10(DMAinx[10]),
.A11(DMAinx[11]),
.A12(DMAinx[12]),
.DO0(DM_rdm[0]),
.DO1(DM_rdm[1]),
.DO2(DM_rdm[2]),
.DO3(DM_rdm[3]),
.DO4(DM_rdm[4]),
.DO5(DM_rdm[5]),
.DO6(DM_rdm[6]),
.DO7(DM_rdm[7]),
.DO8(DM_rdm[8]),
.DO9(DM_rdm[9]),
.DO10(DM_rdm[10]),
.DO11(DM_rdm[11]),
.DO12(DM_rdm[12]),
.DO13(DM_rdm[13]),
.DO14(DM_rdm[14]),
.DO15(DM_rdm[15]),
.DI0(DM_wd[0]),
.DI1(DM_wd[1]),
.DI2(DM_wd[2]),
.DI3(DM_wd[3]),
.DI4(DM_wd[4]),
.DI5(DM_wd[5]),
.DI6(DM_wd[6]),
.DI7(DM_wd[7]),
.DI8(DM_wd[8]),
.DI9(DM_wd[9]),
.DI10(DM_wd[10]),
.DI11(DM_wd[11]),
.DI12(DM_wd[12]),
.DI13(DM_wd[13]),
.DI14(DM_wd[14]),
.DI15(DM_wd[15]),
.CK(DSPCLK_dm0),
.WEB(DMo_web),
.CS(DM_cs),
.OE(DM_oe)
);
SU210010
dm0 (.A0(DMAinx[0]),
.A1(DMAinx[1]),
.A2(DMAinx[2]),
.A3(DMAinx[3]),
.A4(DMAinx[4]),
.A5(DMAinx[5]),
.A6(DMAinx[6]),
.A7(DMAinx[7]),
.A8(DMAinx[8]),
.A9(DMAinx[9]),
.A10(DMAinx[10]),
.A11(DMAinx[11]),
.A12(DMAinx[12]),
.DO0(DM_rd0[0]),
.DO1(DM_rd0[1]),
.DO2(DM_rd0[2]),
.DO3(DM_rd0[3]),
.DO4(DM_rd0[4]),
.DO5(DM_rd0[5]),
.DO6(DM_rd0[6]),
.DO7(DM_rd0[7]),
.DO8(DM_rd0[8]),
.DO9(DM_rd0[9]),
.DO10(DM_rd0[10]),
.DO11(DM_rd0[11]),
.DO12(DM_rd0[12]),
.DO13(DM_rd0[13]),
.DO14(DM_rd0[14]),
.DO15(DM_rd0[15]),
.DI0(DM_wd[0]),
.DI1(DM_wd[1]),
.DI2(DM_wd[2]),
.DI3(DM_wd[3]),
.DI4(DM_wd[4]),
.DI5(DM_wd[5]),
.DI6(DM_wd[6]),
.DI7(DM_wd[7]),
.DI8(DM_wd[8]),
.DI9(DM_wd[9]),
.DI10(DM_wd[10]),
.DI11(DM_wd[11]),
.DI12(DM_wd[12]),
.DI13(DM_wd[13]),
.DI14(DM_wd[14]),
.DI15(DM_wd[15]),
.CK(DSPCLK_dm0),
.WEB(DMo_web),
.CS(DMo_cs0),
.OE(1'b1)
);
SU210010
dm1 (.A0(DMAinx[0]),
.A1(DMAinx[1]),
.A2(DMAinx[2]),
.A3(DMAinx[3]),
.A4(DMAinx[4]),
.A5(DMAinx[5]),
.A6(DMAinx[6]),
.A7(DMAinx[7]),
.A8(DMAinx[8]),
.A9(DMAinx[9]),
.A10(DMAinx[10]),
.A11(DMAinx[11]),
.A12(DMAinx[12]),
.DO0(DM_rd1[0]),
.DO1(DM_rd1[1]),
.DO2(DM_rd1[2]),
.DO3(DM_rd1[3]),
.DO4(DM_rd1[4]),
.DO5(DM_rd1[5]),
.DO6(DM_rd1[6]),
.DO7(DM_rd1[7]),
.DO8(DM_rd1[8]),
.DO9(DM_rd1[9]),
.DO10(DM_rd1[10]),
.DO11(DM_rd1[11]),
.DO12(DM_rd1[12]),
.DO13(DM_rd1[13]),
.DO14(DM_rd1[14]),
.DO15(DM_rd1[15]),
.DI0(DM_wd[0]),
.DI1(DM_wd[1]),
.DI2(DM_wd[2]),
.DI3(DM_wd[3]),
.DI4(DM_wd[4]),
.DI5(DM_wd[5]),
.DI6(DM_wd[6]),
.DI7(DM_wd[7]),
.DI8(DM_wd[8]),
.DI9(DM_wd[9]),
.DI10(DM_wd[10]),
.DI11(DM_wd[11]),
.DI12(DM_wd[12]),
.DI13(DM_wd[13]),
.DI14(DM_wd[14]),
.DI15(DM_wd[15]),
.CK(DSPCLK_dm0),
.WEB(DMo_web),
.CS(DMo_cs1),
.OE(DMo_oe1)
);
SU210010
dm2 (.A0(DMAinx[0]),
.A1(DMAinx[1]),
.A2(DMAinx[2]),
.A3(DMAinx[3]),
.A4(DMAinx[4]),
.A5(DMAinx[5]),
.A6(DMAinx[6]),
.A7(DMAinx[7]),
.A8(DMAinx[8]),
.A9(DMAinx[9]),
.A10(DMAinx[10]),
.A11(DMAinx[11]),
.A12(DMAinx[12]),
.DO0(DM_rd2[0]),
.DO1(DM_rd2[1]),
.DO2(DM_rd2[2]),
.DO3(DM_rd2[3]),
.DO4(DM_rd2[4]),
.DO5(DM_rd2[5]),
.DO6(DM_rd2[6]),
.DO7(DM_rd2[7]),
.DO8(DM_rd2[8]),
.DO9(DM_rd2[9]),
.DO10(DM_rd2[10]),
.DO11(DM_rd2[11]),
.DO12(DM_rd2[12]),
.DO13(DM_rd2[13]),
.DO14(DM_rd2[14]),
.DO15(DM_rd2[15]),
.DI0(DM_wd[0]),
.DI1(DM_wd[1]),
.DI2(DM_wd[2]),
.DI3(DM_wd[3]),
.DI4(DM_wd[4]),
.DI5(DM_wd[5]),
.DI6(DM_wd[6]),
.DI7(DM_wd[7]),
.DI8(DM_wd[8]),
.DI9(DM_wd[9]),
.DI10(DM_wd[10]),
.DI11(DM_wd[11]),
.DI12(DM_wd[12]),
.DI13(DM_wd[13]),
.DI14(DM_wd[14]),
.DI15(DM_wd[15]),
.CK(DSPCLK_dm1),
.WEB(DMo_web),
.CS(DMo_cs2),
.OE(DMo_oe2)
);
SU210010
dm3 (.A0(DMAinx[0]),
.A1(DMAinx[1]),
.A2(DMAinx[2]),
.A3(DMAinx[3]),
.A4(DMAinx[4]),
.A5(DMAinx[5]),
.A6(DMAinx[6]),
.A7(DMAinx[7]),
.A8(DMAinx[8]),
.A9(DMAinx[9]),
.A10(DMAinx[10]),
.A11(DMAinx[11]),
.A12(DMAinx[12]),
.DO0(DM_rd3[0]),
.DO1(DM_rd3[1]),
.DO2(DM_rd3[2]),
.DO3(DM_rd3[3]),
.DO4(DM_rd3[4]),
.DO5(DM_rd3[5]),
.DO6(DM_rd3[6]),
.DO7(DM_rd3[7]),
.DO8(DM_rd3[8]),
.DO9(DM_rd3[9]),
.DO10(DM_rd3[10]),
.DO11(DM_rd3[11]),
.DO12(DM_rd3[12]),
.DO13(DM_rd3[13]),
.DO14(DM_rd3[14]),
.DO15(DM_rd3[15]),
.DI0(DM_wd[0]),
.DI1(DM_wd[1]),
.DI2(DM_wd[2]),
.DI3(DM_wd[3]),
.DI4(DM_wd[4]),
.DI5(DM_wd[5]),
.DI6(DM_wd[6]),
.DI7(DM_wd[7]),
.DI8(DM_wd[8]),
.DI9(DM_wd[9]),
.DI10(DM_wd[10]),
.DI11(DM_wd[11]),
.DI12(DM_wd[12]),
.DI13(DM_wd[13]),
.DI14(DM_wd[14]),
.DI15(DM_wd[15]),
.CK(DSPCLK_dm1),
.WEB(DMo_web),
.CS(DMo_cs3),
.OE(DMo_oe3)
);
SU210010
dm4 (.A0(DMAinx[0]),
.A1(DMAinx[1]),
.A2(DMAinx[2]),
.A3(DMAinx[3]),
.A4(DMAinx[4]),
.A5(DMAinx[5]),
.A6(DMAinx[6]),
.A7(DMAinx[7]),
.A8(DMAinx[8]),
.A9(DMAinx[9]),
.A10(DMAinx[10]),
.A11(DMAinx[11]),
.A12(DMAinx[12]),
.DO0(DM_rd4[0]),
.DO1(DM_rd4[1]),
.DO2(DM_rd4[2]),
.DO3(DM_rd4[3]),
.DO4(DM_rd4[4]),
.DO5(DM_rd4[5]),
.DO6(DM_rd4[6]),
.DO7(DM_rd4[7]),
.DO8(DM_rd4[8]),
.DO9(DM_rd4[9]),
.DO10(DM_rd4[10]),
.DO11(DM_rd4[11]),
.DO12(DM_rd4[12]),
.DO13(DM_rd4[13]),
.DO14(DM_rd4[14]),
.DO15(DM_rd4[15]),
.DI0(DM_wd[0]),
.DI1(DM_wd[1]),
.DI2(DM_wd[2]),
.DI3(DM_wd[3]),
.DI4(DM_wd[4]),
.DI5(DM_wd[5]),
.DI6(DM_wd[6]),
.DI7(DM_wd[7]),
.DI8(DM_wd[8]),
.DI9(DM_wd[9]),
.DI10(DM_wd[10]),
.DI11(DM_wd[11]),
.DI12(DM_wd[12]),
.DI13(DM_wd[13]),
.DI14(DM_wd[14]),
.DI15(DM_wd[15]),
.CK(DSPCLK_dm1),
.WEB(DMo_web),
.CS(DMo_cs4),
.OE(DMo_oe4)
);
SU210010
dm5 (.A0(DMAinx[0]),
.A1(DMAinx[1]),
.A2(DMAinx[2]),
.A3(DMAinx[3]),
.A4(DMAinx[4]),
.A5(DMAinx[5]),
.A6(DMAinx[6]),
.A7(DMAinx[7]),
.A8(DMAinx[8]),
.A9(DMAinx[9]),
.A10(DMAinx[10]),
.A11(DMAinx[11]),
.A12(DMAinx[12]),
.DO0(DM_rd5[0]),
.DO1(DM_rd5[1]),
.DO2(DM_rd5[2]),
.DO3(DM_rd5[3]),
.DO4(DM_rd5[4]),
.DO5(DM_rd5[5]),
.DO6(DM_rd5[6]),
.DO7(DM_rd5[7]),
.DO8(DM_rd5[8]),
.DO9(DM_rd5[9]),
.DO10(DM_rd5[10]),
.DO11(DM_rd5[11]),
.DO12(DM_rd5[12]),
.DO13(DM_rd5[13]),
.DO14(DM_rd5[14]),
.DO15(DM_rd5[15]),
.DI0(DM_wd[0]),
.DI1(DM_wd[1]),
.DI2(DM_wd[2]),
.DI3(DM_wd[3]),
.DI4(DM_wd[4]),
.DI5(DM_wd[5]),
.DI6(DM_wd[6]),
.DI7(DM_wd[7]),
.DI8(DM_wd[8]),
.DI9(DM_wd[9]),
.DI10(DM_wd[10]),
.DI11(DM_wd[11]),
.DI12(DM_wd[12]),
.DI13(DM_wd[13]),
.DI14(DM_wd[14]),
.DI15(DM_wd[15]),
.CK(DSPCLK_dm2),
.WEB(DMo_web),
.CS(DMo_cs5),
.OE(DMo_oe5)
);
SU210010
dm6 (.A0(DMAinx[0]),
.A1(DMAinx[1]),
.A2(DMAinx[2]),
.A3(DMAinx[3]),
.A4(DMAinx[4]),
.A5(DMAinx[5]),
.A6(DMAinx[6]),
.A7(DMAinx[7]),
.A8(DMAinx[8]),
.A9(DMAinx[9]),
.A10(DMAinx[10]),
.A11(DMAinx[11]),
.A12(DMAinx[12]),
.DO0(DM_rd6[0]),
.DO1(DM_rd6[1]),
.DO2(DM_rd6[2]),
.DO3(DM_rd6[3]),
.DO4(DM_rd6[4]),
.DO5(DM_rd6[5]),
.DO6(DM_rd6[6]),
.DO7(DM_rd6[7]),
.DO8(DM_rd6[8]),
.DO9(DM_rd6[9]),
.DO10(DM_rd6[10]),
.DO11(DM_rd6[11]),
.DO12(DM_rd6[12]),
.DO13(DM_rd6[13]),
.DO14(DM_rd6[14]),
.DO15(DM_rd6[15]),
.DI0(DM_wd[0]),
.DI1(DM_wd[1]),
.DI2(DM_wd[2]),
.DI3(DM_wd[3]),
.DI4(DM_wd[4]),
.DI5(DM_wd[5]),
.DI6(DM_wd[6]),
.DI7(DM_wd[7]),
.DI8(DM_wd[8]),
.DI9(DM_wd[9]),
.DI10(DM_wd[10]),
.DI11(DM_wd[11]),
.DI12(DM_wd[12]),
.DI13(DM_wd[13]),
.DI14(DM_wd[14]),
.DI15(DM_wd[15]),
.CK(DSPCLK_dm2),
.WEB(DMo_web),
.CS(DMo_cs6),
.OE(DMo_oe6)
);
SU210010
dm7 (.A0(DMAinx[0]),
.A1(DMAinx[1]),
.A2(DMAinx[2]),
.A3(DMAinx[3]),
.A4(DMAinx[4]),
.A5(DMAinx[5]),
.A6(DMAinx[6]),
.A7(DMAinx[7]),
.A8(DMAinx[8]),
.A9(DMAinx[9]),
.A10(DMAinx[10]),
.A11(DMAinx[11]),
.A12(DMAinx[12]),
.DO0(DM_rd7[0]),
.DO1(DM_rd7[1]),
.DO2(DM_rd7[2]),
.DO3(DM_rd7[3]),
.DO4(DM_rd7[4]),
.DO5(DM_rd7[5]),
.DO6(DM_rd7[6]),
.DO7(DM_rd7[7]),
.DO8(DM_rd7[8]),
.DO9(DM_rd7[9]),
.DO10(DM_rd7[10]),
.DO11(DM_rd7[11]),
.DO12(DM_rd7[12]),
.DO13(DM_rd7[13]),
.DO14(DM_rd7[14]),
.DO15(DM_rd7[15]),
.DI0(DM_wd[0]),
.DI1(DM_wd[1]),
.DI2(DM_wd[2]),
.DI3(DM_wd[3]),
.DI4(DM_wd[4]),
.DI5(DM_wd[5]),
.DI6(DM_wd[6]),
.DI7(DM_wd[7]),
.DI8(DM_wd[8]),
.DI9(DM_wd[9]),
.DI10(DM_wd[10]),
.DI11(DM_wd[11]),
.DI12(DM_wd[12]),
.DI13(DM_wd[13]),
.DI14(DM_wd[14]),
.DI15(DM_wd[15]),
.CK(DSPCLK_dm2),
.WEB(DMo_web),
.CS(DMo_cs7),
.OE(DMo_oe7)
);
endmodule
|
`timescale 1ns/10ps
`define d0 0
`define da 0.2
`define db 0.5
`define pCKR 14'h3ffa
`define pSYSR 14'h3fff
`define pWSCR 14'h3ffe
`define pWSCR_ext 14'h3feb
`define pAUTO0 14'h3ff3
`define pFSDIV0 14'h3ff4
`define pSCLKDIV0 14'h3ff5
`define pSCTL0 14'h3ff6
`define pMWORD0 14'h3ff7
`define pAUTO1 14'h3fef
`define pFSDIV1 14'h3ff0
`define pSCLKDIV1 14'h3ff1
`define pSCTL1 14'h3ff2
`define pMWORD1 14'h3ff8
`define pDCTL 14'h3fe0
`define pDOVL 14'h3ff9
`define pPFTYPE 14'h3fe6
`define pPDATA 14'h3fe5
`define pPIMASK 14'h3fe7
`define pPINT 14'h3fe8
`define pTPERIOD 14'h3ffd
`define pTCOUNT 14'h3ffc
`define pTSCALE 14'h3ffb
`define pBIAD 14'h3fe1
`define pBEAD 14'h3fe2
`define pBCTL 14'h3fe3
`define pBCNT 14'h3fe4
`define pBOVL 14'h3fe9
`define AC97_SCTL 'h0f03
`define AC97_FSDIV 'h00ff
`define AC97_MWORD 'h60c
|
/*******************************************************************************
(C) Copyright 2002,2003 Faraday Technology Corp. All Rights Reserved.
This source code is an unpublished work belongs to Faraday Technology
Corp. It is considered a trade secret and is not to be divulged or
used by parties who have not received written authorization from
Faraday Technology Corp.
|-----------------------------------------------------------------------------|
Verilog Behavior Simulation Model
Synchronous 2-Port SRAM
Module Name : SW10200C
Words : 32
Bits : 12
Byte-Write : 1
Output Loading : 0.1
|-----------------------------------------------------------------------------|
Notice on usage: Fixed delay or timing data are given in this model.
It supports SDF back-annotation, please generate SDF file
by EDA tools to get the accurate timing.
|-----------------------------------------------------------------------------|
Library : FS90A_B
Memaker : v4.5.1
Compiler : swmemgen 1.0
Template revison : 1.1
Date : Tue Jul 29 09:57:34 CST 2003
Editor : Jony
*******************************************************************************/
module SW10200C (A0,A1,A2,A3,A4,B0,B1,B2,B3,
B4,DO0,DO1,DO2,DO3,DO4,DO5,DO6,DO7,DO8,
DO9,DO10,DO11,DI0,DI1,DI2,DI3,DI4,DI5,DI6,
DI7,DI8,DI9,DI10,DI11,CKA,CKB,WEB,CSA,CSB,OE);
output DO0,DO1,DO2,DO3,DO4,DO5,DO6,DO7,DO8,
DO9,DO10,DO11;
input DI0,DI1,DI2,DI3,DI4,DI5,DI6,DI7,DI8,
DI9,DI10,DI11;
input A0,A1,A2,A3,A4;
input B0,B1,B2,B3,B4;
input OE;
input WEB;
input CKA;
input CKB;
input CSA;
input CSB;
endmodule
|
/*******************************************************************************
(C) Copyright 2002,2003 Faraday Technology Corp. All Rights Reserved.
This source code is an unpublished work belongs to Faraday Technology
Corp. It is considered a trade secret and is not to be divulged or
used by parties who have not received written authorization from
Faraday Technology Corp.
|-----------------------------------------------------------------------------|
Verilog Behavior Simulation Model
Synchronous 2-Port SRAM
Module Name : SW10201A
Words : 32
Bits : 26
Byte-Write : 1
Output Loading : 0.1
|-----------------------------------------------------------------------------|
Notice on usage: Fixed delay or timing data are given in this model.
It supports SDF back-annotation, please generate SDF file
by EDA tools to get the accurate timing.
|-----------------------------------------------------------------------------|
Library : FS90A_B
Memaker : v4.5.1
Compiler : swmemgen 1.0
Template revison : 1.1
Date : Tue Jul 29 09:57:06 CST 2003
Editor : Jony
*******************************************************************************/
module SW10201A (A0,A1,A2,A3,A4,B0,B1,B2,B3,
B4,DO0,DO1,DO2,DO3,DO4,DO5,DO6,DO7,DO8,
DO9,DO10,DO11,DO12,DO13,DO14,DO15,DO16,DO17,DO18,
DO19,DO20,DO21,DO22,DO23,DO24,DO25,DI0,DI1,DI2,
DI3,DI4,DI5,DI6,DI7,DI8,DI9,DI10,DI11,DI12,
DI13,DI14,DI15,DI16,DI17,DI18,DI19,DI20,DI21,DI22,
DI23,DI24,DI25,CKA,CKB,WEB,CSA,CSB,OE);
output DO0,DO1,DO2,DO3,DO4,DO5,DO6,DO7,DO8,
DO9,DO10,DO11,DO12,DO13,DO14,DO15,DO16,DO17,DO18,
DO19,DO20,DO21,DO22,DO23,DO24,DO25;
input DI0,DI1,DI2,DI3,DI4,DI5,DI6,DI7,DI8,
DI9,DI10,DI11,DI12,DI13,DI14,DI15,DI16,DI17,DI18,
DI19,DI20,DI21,DI22,DI23,DI24,DI25;
input A0,A1,A2,A3,A4;
input B0,B1,B2,B3,B4;
input OE;
input WEB;
input CKA;
input CKB;
input CSA;
input CSB;
endmodule
|
// megafunction wizard: %ALTMULT_ADD%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: ALTMULT_ADD
// ============================================================
// File Name: dsp_shift_megafn.v
// Megafunction Name(s):
// ALTMULT_ADD
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 12.0 Build 178 05/31/2012 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2012 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module dsp_shift_megafn (
clock0,
dataa_0,
datab_0,
rotate,
shift_right,
result);
input clock0;
input [31:0] dataa_0;
input [31:0] datab_0;
input rotate;
input shift_right;
output [31:0] result;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock0;
tri0 [31:0] dataa_0;
tri0 [31:0] datab_0;
tri0 rotate;
tri0 shift_right;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [31:0] sub_wire0;
wire [31:0] result = sub_wire0[31:0];
altmult_add ALTMULT_ADD_component (
.clock0 (clock0),
.datab (datab_0),
.dataa (dataa_0),
.rotate (rotate),
.shift_right (shift_right),
.result (sub_wire0),
.accum_sload (1'b0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.aclr2 (1'b0),
.aclr3 (1'b0),
.addnsub1 (1'b1),
.addnsub1_round (1'b0),
.addnsub3 (1'b1),
.addnsub3_round (1'b0),
.chainin (1'b0),
.chainout_round (1'b0),
.chainout_sat_overflow (),
.chainout_saturate (1'b0),
.clock1 (1'b1),
.clock2 (1'b1),
.clock3 (1'b1),
.coefsel0 ({3{1'b0}}),
.coefsel1 ({3{1'b0}}),
.coefsel2 ({3{1'b0}}),
.coefsel3 ({3{1'b0}}),
.datac ({22{1'b0}}),
.ena0 (1'b1),
.ena1 (1'b1),
.ena2 (1'b1),
.ena3 (1'b1),
.mult01_round (1'b0),
.mult01_saturation (1'b0),
.mult0_is_saturated (),
.mult1_is_saturated (),
.mult23_round (1'b0),
.mult23_saturation (1'b0),
.mult2_is_saturated (),
.mult3_is_saturated (),
.output_round (1'b0),
.output_saturate (1'b0),
.overflow (),
.scanina ({32{1'b0}}),
.scaninb ({32{1'b0}}),
.scanouta (),
.scanoutb (),
.signa (1'b0),
.signb (1'b0),
.sourcea (1'b0),
.sourceb (1'b0),
.zero_chainout (1'b0),
.zero_loopback (1'b0));
defparam
ALTMULT_ADD_component.accumulator = "NO",
ALTMULT_ADD_component.addnsub_multiplier_aclr1 = "UNUSED",
ALTMULT_ADD_component.addnsub_multiplier_pipeline_aclr1 = "UNUSED",
ALTMULT_ADD_component.addnsub_multiplier_pipeline_register1 = "CLOCK0",
ALTMULT_ADD_component.addnsub_multiplier_register1 = "CLOCK0",
ALTMULT_ADD_component.chainout_adder = "NO",
ALTMULT_ADD_component.chainout_register = "UNREGISTERED",
ALTMULT_ADD_component.dedicated_multiplier_circuitry = "YES",
ALTMULT_ADD_component.input_aclr_a0 = "UNUSED",
ALTMULT_ADD_component.input_aclr_b0 = "UNUSED",
ALTMULT_ADD_component.input_register_a0 = "CLOCK0",
ALTMULT_ADD_component.input_register_b0 = "CLOCK0",
ALTMULT_ADD_component.input_source_a0 = "DATAA",
ALTMULT_ADD_component.input_source_b0 = "DATAB",
ALTMULT_ADD_component.intended_device_family = "Stratix IV",
ALTMULT_ADD_component.lpm_type = "altmult_add",
ALTMULT_ADD_component.multiplier1_direction = "ADD",
ALTMULT_ADD_component.multiplier_aclr0 = "UNUSED",
ALTMULT_ADD_component.multiplier_register0 = "CLOCK0",
ALTMULT_ADD_component.number_of_multipliers = 1,
ALTMULT_ADD_component.output_aclr = "UNUSED",
ALTMULT_ADD_component.output_register = "CLOCK0",
ALTMULT_ADD_component.port_addnsub1 = "PORT_UNUSED",
ALTMULT_ADD_component.port_signa = "PORT_UNUSED",
ALTMULT_ADD_component.port_signb = "PORT_UNUSED",
ALTMULT_ADD_component.representation_a = "UNSIGNED",
ALTMULT_ADD_component.representation_b = "UNSIGNED",
ALTMULT_ADD_component.rotate_aclr = "UNUSED",
ALTMULT_ADD_component.rotate_output_aclr = "UNUSED",
ALTMULT_ADD_component.rotate_output_register = "CLOCK0",
ALTMULT_ADD_component.rotate_pipeline_aclr = "UNUSED",
ALTMULT_ADD_component.rotate_pipeline_register = "CLOCK0",
ALTMULT_ADD_component.rotate_register = "CLOCK0",
ALTMULT_ADD_component.shift_mode = "VARIABLE",
ALTMULT_ADD_component.shift_right_aclr = "UNUSED",
ALTMULT_ADD_component.shift_right_output_aclr = "UNUSED",
ALTMULT_ADD_component.shift_right_output_register = "CLOCK0",
ALTMULT_ADD_component.shift_right_pipeline_aclr = "UNUSED",
ALTMULT_ADD_component.shift_right_pipeline_register = "CLOCK0",
ALTMULT_ADD_component.shift_right_register = "CLOCK0",
ALTMULT_ADD_component.signed_aclr_a = "UNUSED",
ALTMULT_ADD_component.signed_aclr_b = "UNUSED",
ALTMULT_ADD_component.signed_pipeline_aclr_a = "UNUSED",
ALTMULT_ADD_component.signed_pipeline_aclr_b = "UNUSED",
ALTMULT_ADD_component.signed_pipeline_register_a = "CLOCK0",
ALTMULT_ADD_component.signed_pipeline_register_b = "CLOCK0",
ALTMULT_ADD_component.signed_register_a = "CLOCK0",
ALTMULT_ADD_component.signed_register_b = "CLOCK0",
ALTMULT_ADD_component.width_a = 32,
ALTMULT_ADD_component.width_b = 32,
ALTMULT_ADD_component.width_chainin = 1,
ALTMULT_ADD_component.width_result = 32,
ALTMULT_ADD_component.zero_chainout_output_aclr = "UNUSED",
ALTMULT_ADD_component.zero_chainout_output_register = "CLOCK0",
ALTMULT_ADD_component.zero_loopback_aclr = "UNUSED",
ALTMULT_ADD_component.zero_loopback_output_aclr = "UNUSED",
ALTMULT_ADD_component.zero_loopback_output_register = "CLOCK0",
ALTMULT_ADD_component.zero_loopback_pipeline_aclr = "UNUSED",
ALTMULT_ADD_component.zero_loopback_pipeline_register = "CLOCK0",
ALTMULT_ADD_component.zero_loopback_register = "CLOCK0";
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ACCUM_DIRECTION STRING "Add"
// Retrieval info: PRIVATE: ACCUM_SLOAD_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ACCUM_SLOAD_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ACCUM_SLOAD_PIPE_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ACCUM_SLOAD_PIPE_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ACCUM_SLOAD_PIPE_REG STRING "1"
// Retrieval info: PRIVATE: ACCUM_SLOAD_REG STRING "1"
// Retrieval info: PRIVATE: ADDNSUB1_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ADDNSUB1_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ADDNSUB1_PIPE_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ADDNSUB1_PIPE_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ADDNSUB1_PIPE_REG STRING "1"
// Retrieval info: PRIVATE: ADDNSUB1_REG STRING "1"
// Retrieval info: PRIVATE: ADDNSUB3_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ADDNSUB3_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ADDNSUB3_PIPE_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ADDNSUB3_PIPE_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ADDNSUB3_PIPE_REG STRING "1"
// Retrieval info: PRIVATE: ADDNSUB3_REG STRING "1"
// Retrieval info: PRIVATE: ADD_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: ALL_REG_ACLR NUMERIC "0"
// Retrieval info: PRIVATE: A_ACLR_SRC_MULT0 NUMERIC "3"
// Retrieval info: PRIVATE: A_CLK_SRC_MULT0 NUMERIC "0"
// Retrieval info: PRIVATE: B_ACLR_SRC_MULT0 NUMERIC "3"
// Retrieval info: PRIVATE: B_CLK_SRC_MULT0 NUMERIC "0"
// Retrieval info: PRIVATE: CHAINOUT_OUTPUT_ACLR NUMERIC "3"
// Retrieval info: PRIVATE: CHAINOUT_OUTPUT_REG STRING "0"
// Retrieval info: PRIVATE: CHAINOUT_OUTPUT_REGISTER NUMERIC "0"
// Retrieval info: PRIVATE: CHAINOUT_OUTPUT_REGISTERED NUMERIC "0"
// Retrieval info: PRIVATE: CHAS_ZERO_CHAINOUT NUMERIC "0"
// Retrieval info: PRIVATE: HAS_ACCUMULATOR NUMERIC "0"
// Retrieval info: PRIVATE: HAS_ACUMM_SLOAD NUMERIC "0"
// Retrieval info: PRIVATE: HAS_CHAININ_PORT NUMERIC "0"
// Retrieval info: PRIVATE: HAS_CHAINOUT_ADDER NUMERIC "0"
// Retrieval info: PRIVATE: HAS_LOOPBACK NUMERIC "0"
// Retrieval info: PRIVATE: HAS_MAC STRING "0"
// Retrieval info: PRIVATE: HAS_SAT_ROUND STRING "0"
// Retrieval info: PRIVATE: HAS_ZERO_LOOPBACK NUMERIC "0"
// Retrieval info: PRIVATE: IMPL_STYLE_DEDICATED NUMERIC "1"
// Retrieval info: PRIVATE: IMPL_STYLE_DEFAULT NUMERIC "0"
// Retrieval info: PRIVATE: IMPL_STYLE_LCELL NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
// Retrieval info: PRIVATE: MULT_REGA0 NUMERIC "1"
// Retrieval info: PRIVATE: MULT_REGB0 NUMERIC "1"
// Retrieval info: PRIVATE: MULT_REGOUT0 NUMERIC "1"
// Retrieval info: PRIVATE: NUM_MULT STRING "1"
// Retrieval info: PRIVATE: OP1 STRING "Add"
// Retrieval info: PRIVATE: OP3 STRING "Add"
// Retrieval info: PRIVATE: OUTPUT_EXTRA_LAT NUMERIC "0"
// Retrieval info: PRIVATE: OUTPUT_REG_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: OUTPUT_REG_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: Q_ACLR_SRC_MULT0 NUMERIC "3"
// Retrieval info: PRIVATE: Q_CLK_SRC_MULT0 NUMERIC "0"
// Retrieval info: PRIVATE: REG_OUT NUMERIC "1"
// Retrieval info: PRIVATE: RNFORMAT STRING "32"
// Retrieval info: PRIVATE: ROTATE_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ROTATE_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ROTATE_OUT_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ROTATE_OUT_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ROTATE_OUT_REG STRING "1"
// Retrieval info: PRIVATE: ROTATE_PIPE_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ROTATE_PIPE_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ROTATE_PIPE_REG STRING "1"
// Retrieval info: PRIVATE: ROTATE_REG STRING "1"
// Retrieval info: PRIVATE: RQFORMAT STRING "Q1.15"
// Retrieval info: PRIVATE: RTS_WIDTH STRING "32"
// Retrieval info: PRIVATE: SAME_CONFIG NUMERIC "1"
// Retrieval info: PRIVATE: SAME_CONTROL_SRC_A0 NUMERIC "1"
// Retrieval info: PRIVATE: SAME_CONTROL_SRC_B0 NUMERIC "1"
// Retrieval info: PRIVATE: SCANOUTA NUMERIC "0"
// Retrieval info: PRIVATE: SCANOUTB NUMERIC "0"
// Retrieval info: PRIVATE: SHIFTOUTA_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: SHIFTOUTA_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: SHIFTOUTA_REG STRING "0"
// Retrieval info: PRIVATE: SHIFT_RIGHT_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: SHIFT_RIGHT_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: SHIFT_RIGHT_OUT_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: SHIFT_RIGHT_OUT_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: SHIFT_RIGHT_OUT_REG STRING "1"
// Retrieval info: PRIVATE: SHIFT_RIGHT_PIPE_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: SHIFT_RIGHT_PIPE_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: SHIFT_RIGHT_PIPE_REG STRING "1"
// Retrieval info: PRIVATE: SHIFT_RIGHT_REG STRING "1"
// Retrieval info: PRIVATE: SHIFT_ROTATE_MODE STRING "Variable"
// Retrieval info: PRIVATE: SIGNA STRING "UNSIGNED"
// Retrieval info: PRIVATE: SIGNA_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: SIGNA_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: SIGNA_PIPE_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: SIGNA_PIPE_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: SIGNA_PIPE_REG STRING "1"
// Retrieval info: PRIVATE: SIGNA_REG STRING "1"
// Retrieval info: PRIVATE: SIGNB STRING "UNSIGNED"
// Retrieval info: PRIVATE: SIGNB_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: SIGNB_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: SIGNB_PIPE_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: SIGNB_PIPE_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: SIGNB_PIPE_REG STRING "1"
// Retrieval info: PRIVATE: SIGNB_REG STRING "1"
// Retrieval info: PRIVATE: SRCA0 STRING "Multiplier input"
// Retrieval info: PRIVATE: SRCB0 STRING "Multiplier input"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: WIDTHA STRING "32"
// Retrieval info: PRIVATE: WIDTHB STRING "32"
// Retrieval info: PRIVATE: ZERO_CHAINOUT_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ZERO_CHAINOUT_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_CHAINOUT_REG STRING "0"
// Retrieval info: PRIVATE: ZERO_LOOPBACK_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ZERO_LOOPBACK_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_LOOPBACK_OUT_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ZERO_LOOPBACK_OUT_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_LOOPBACK_OUT_REG STRING "1"
// Retrieval info: PRIVATE: ZERO_LOOPBACK_PIPE_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ZERO_LOOPBACK_PIPE_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_LOOPBACK_PIPE_REG STRING "1"
// Retrieval info: PRIVATE: ZERO_LOOPBACK_REG STRING "1"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ACCUMULATOR STRING "NO"
// Retrieval info: CONSTANT: ADDNSUB_MULTIPLIER_ACLR1 STRING "UNUSED"
// Retrieval info: CONSTANT: ADDNSUB_MULTIPLIER_PIPELINE_ACLR1 STRING "UNUSED"
// Retrieval info: CONSTANT: ADDNSUB_MULTIPLIER_PIPELINE_REGISTER1 STRING "CLOCK0"
// Retrieval info: CONSTANT: ADDNSUB_MULTIPLIER_REGISTER1 STRING "CLOCK0"
// Retrieval info: CONSTANT: CHAINOUT_ADDER STRING "NO"
// Retrieval info: CONSTANT: CHAINOUT_REGISTER STRING "UNREGISTERED"
// Retrieval info: CONSTANT: DEDICATED_MULTIPLIER_CIRCUITRY STRING "YES"
// Retrieval info: CONSTANT: INPUT_ACLR_A0 STRING "UNUSED"
// Retrieval info: CONSTANT: INPUT_ACLR_B0 STRING "UNUSED"
// Retrieval info: CONSTANT: INPUT_REGISTER_A0 STRING "CLOCK0"
// Retrieval info: CONSTANT: INPUT_REGISTER_B0 STRING "CLOCK0"
// Retrieval info: CONSTANT: INPUT_SOURCE_A0 STRING "DATAA"
// Retrieval info: CONSTANT: INPUT_SOURCE_B0 STRING "DATAB"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altmult_add"
// Retrieval info: CONSTANT: MULTIPLIER1_DIRECTION STRING "ADD"
// Retrieval info: CONSTANT: MULTIPLIER_ACLR0 STRING "UNUSED"
// Retrieval info: CONSTANT: MULTIPLIER_REGISTER0 STRING "CLOCK0"
// Retrieval info: CONSTANT: NUMBER_OF_MULTIPLIERS NUMERIC "1"
// Retrieval info: CONSTANT: OUTPUT_ACLR STRING "UNUSED"
// Retrieval info: CONSTANT: OUTPUT_REGISTER STRING "CLOCK0"
// Retrieval info: CONSTANT: PORT_ADDNSUB1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SIGNA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SIGNB STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: REPRESENTATION_A STRING "UNSIGNED"
// Retrieval info: CONSTANT: REPRESENTATION_B STRING "UNSIGNED"
// Retrieval info: CONSTANT: ROTATE_ACLR STRING "UNUSED"
// Retrieval info: CONSTANT: ROTATE_OUTPUT_ACLR STRING "UNUSED"
// Retrieval info: CONSTANT: ROTATE_OUTPUT_REGISTER STRING "CLOCK0"
// Retrieval info: CONSTANT: ROTATE_PIPELINE_ACLR STRING "UNUSED"
// Retrieval info: CONSTANT: ROTATE_PIPELINE_REGISTER STRING "CLOCK0"
// Retrieval info: CONSTANT: ROTATE_REGISTER STRING "CLOCK0"
// Retrieval info: CONSTANT: SHIFT_MODE STRING "VARIABLE"
// Retrieval info: CONSTANT: SHIFT_RIGHT_ACLR STRING "UNUSED"
// Retrieval info: CONSTANT: SHIFT_RIGHT_OUTPUT_ACLR STRING "UNUSED"
// Retrieval info: CONSTANT: SHIFT_RIGHT_OUTPUT_REGISTER STRING "CLOCK0"
// Retrieval info: CONSTANT: SHIFT_RIGHT_PIPELINE_ACLR STRING "UNUSED"
// Retrieval info: CONSTANT: SHIFT_RIGHT_PIPELINE_REGISTER STRING "CLOCK0"
// Retrieval info: CONSTANT: SHIFT_RIGHT_REGISTER STRING "CLOCK0"
// Retrieval info: CONSTANT: SIGNED_ACLR_A STRING "UNUSED"
// Retrieval info: CONSTANT: SIGNED_ACLR_B STRING "UNUSED"
// Retrieval info: CONSTANT: SIGNED_PIPELINE_ACLR_A STRING "UNUSED"
// Retrieval info: CONSTANT: SIGNED_PIPELINE_ACLR_B STRING "UNUSED"
// Retrieval info: CONSTANT: SIGNED_PIPELINE_REGISTER_A STRING "CLOCK0"
// Retrieval info: CONSTANT: SIGNED_PIPELINE_REGISTER_B STRING "CLOCK0"
// Retrieval info: CONSTANT: SIGNED_REGISTER_A STRING "CLOCK0"
// Retrieval info: CONSTANT: SIGNED_REGISTER_B STRING "CLOCK0"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "32"
// Retrieval info: CONSTANT: WIDTH_B NUMERIC "32"
// Retrieval info: CONSTANT: WIDTH_CHAININ NUMERIC "1"
// Retrieval info: CONSTANT: WIDTH_RESULT NUMERIC "32"
// Retrieval info: CONSTANT: ZERO_CHAINOUT_OUTPUT_ACLR STRING "UNUSED"
// Retrieval info: CONSTANT: ZERO_CHAINOUT_OUTPUT_REGISTER STRING "CLOCK0"
// Retrieval info: CONSTANT: ZERO_LOOPBACK_ACLR STRING "UNUSED"
// Retrieval info: CONSTANT: ZERO_LOOPBACK_OUTPUT_ACLR STRING "UNUSED"
// Retrieval info: CONSTANT: ZERO_LOOPBACK_OUTPUT_REGISTER STRING "CLOCK0"
// Retrieval info: CONSTANT: ZERO_LOOPBACK_PIPELINE_ACLR STRING "UNUSED"
// Retrieval info: CONSTANT: ZERO_LOOPBACK_PIPELINE_REGISTER STRING "CLOCK0"
// Retrieval info: CONSTANT: ZERO_LOOPBACK_REGISTER STRING "CLOCK0"
// Retrieval info: USED_PORT: clock0 0 0 0 0 INPUT VCC "clock0"
// Retrieval info: USED_PORT: dataa_0 0 0 32 0 INPUT GND "dataa_0[31..0]"
// Retrieval info: USED_PORT: datab_0 0 0 32 0 INPUT GND "datab_0[31..0]"
// Retrieval info: USED_PORT: result 0 0 32 0 OUTPUT GND "result[31..0]"
// Retrieval info: USED_PORT: rotate 0 0 0 0 INPUT GND "rotate"
// Retrieval info: USED_PORT: shift_right 0 0 0 0 INPUT GND "shift_right"
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock0 0 0 0 0
// Retrieval info: CONNECT: @dataa 0 0 32 0 dataa_0 0 0 32 0
// Retrieval info: CONNECT: @datab 0 0 32 0 datab_0 0 0 32 0
// Retrieval info: CONNECT: @rotate 0 0 0 0 rotate 0 0 0 0
// Retrieval info: CONNECT: @shift_right 0 0 0 0 shift_right 0 0 0 0
// Retrieval info: CONNECT: result 0 0 32 0 @result 0 0 32 0
// Retrieval info: GEN_FILE: TYPE_NORMAL dsp_shift_megafn.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL dsp_shift_megafn.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL dsp_shift_megafn.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL dsp_shift_megafn.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL dsp_shift_megafn_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL dsp_shift_megafn_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
// megafunction wizard: %ALTMULT_ADD%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: ALTMULT_ADD
// ============================================================
// File Name: dsp_shift_megafn.v
// Megafunction Name(s):
// ALTMULT_ADD
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 12.0 Build 178 05/31/2012 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2012 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module dsp_shift_megafn (
clock0,
dataa_0,
datab_0,
rotate,
shift_right,
result);
input clock0;
input [31:0] dataa_0;
input [31:0] datab_0;
input rotate;
input shift_right;
output [31:0] result;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock0;
tri0 [31:0] dataa_0;
tri0 [31:0] datab_0;
tri0 rotate;
tri0 shift_right;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ACCUM_DIRECTION STRING "Add"
// Retrieval info: PRIVATE: ACCUM_SLOAD_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ACCUM_SLOAD_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ACCUM_SLOAD_PIPE_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ACCUM_SLOAD_PIPE_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ACCUM_SLOAD_PIPE_REG STRING "1"
// Retrieval info: PRIVATE: ACCUM_SLOAD_REG STRING "1"
// Retrieval info: PRIVATE: ADDNSUB1_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ADDNSUB1_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ADDNSUB1_PIPE_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ADDNSUB1_PIPE_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ADDNSUB1_PIPE_REG STRING "1"
// Retrieval info: PRIVATE: ADDNSUB1_REG STRING "1"
// Retrieval info: PRIVATE: ADDNSUB3_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ADDNSUB3_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ADDNSUB3_PIPE_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ADDNSUB3_PIPE_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ADDNSUB3_PIPE_REG STRING "1"
// Retrieval info: PRIVATE: ADDNSUB3_REG STRING "1"
// Retrieval info: PRIVATE: ADD_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: ALL_REG_ACLR NUMERIC "0"
// Retrieval info: PRIVATE: A_ACLR_SRC_MULT0 NUMERIC "3"
// Retrieval info: PRIVATE: A_CLK_SRC_MULT0 NUMERIC "0"
// Retrieval info: PRIVATE: B_ACLR_SRC_MULT0 NUMERIC "3"
// Retrieval info: PRIVATE: B_CLK_SRC_MULT0 NUMERIC "0"
// Retrieval info: PRIVATE: CHAINOUT_OUTPUT_ACLR NUMERIC "3"
// Retrieval info: PRIVATE: CHAINOUT_OUTPUT_REG STRING "0"
// Retrieval info: PRIVATE: CHAINOUT_OUTPUT_REGISTER NUMERIC "0"
// Retrieval info: PRIVATE: CHAINOUT_OUTPUT_REGISTERED NUMERIC "0"
// Retrieval info: PRIVATE: CHAS_ZERO_CHAINOUT NUMERIC "0"
// Retrieval info: PRIVATE: HAS_ACCUMULATOR NUMERIC "0"
// Retrieval info: PRIVATE: HAS_ACUMM_SLOAD NUMERIC "0"
// Retrieval info: PRIVATE: HAS_CHAININ_PORT NUMERIC "0"
// Retrieval info: PRIVATE: HAS_CHAINOUT_ADDER NUMERIC "0"
// Retrieval info: PRIVATE: HAS_LOOPBACK NUMERIC "0"
// Retrieval info: PRIVATE: HAS_MAC STRING "0"
// Retrieval info: PRIVATE: HAS_SAT_ROUND STRING "0"
// Retrieval info: PRIVATE: HAS_ZERO_LOOPBACK NUMERIC "0"
// Retrieval info: PRIVATE: IMPL_STYLE_DEDICATED NUMERIC "1"
// Retrieval info: PRIVATE: IMPL_STYLE_DEFAULT NUMERIC "0"
// Retrieval info: PRIVATE: IMPL_STYLE_LCELL NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
// Retrieval info: PRIVATE: MULT_REGA0 NUMERIC "1"
// Retrieval info: PRIVATE: MULT_REGB0 NUMERIC "1"
// Retrieval info: PRIVATE: MULT_REGOUT0 NUMERIC "1"
// Retrieval info: PRIVATE: NUM_MULT STRING "1"
// Retrieval info: PRIVATE: OP1 STRING "Add"
// Retrieval info: PRIVATE: OP3 STRING "Add"
// Retrieval info: PRIVATE: OUTPUT_EXTRA_LAT NUMERIC "0"
// Retrieval info: PRIVATE: OUTPUT_REG_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: OUTPUT_REG_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: Q_ACLR_SRC_MULT0 NUMERIC "3"
// Retrieval info: PRIVATE: Q_CLK_SRC_MULT0 NUMERIC "0"
// Retrieval info: PRIVATE: REG_OUT NUMERIC "1"
// Retrieval info: PRIVATE: RNFORMAT STRING "32"
// Retrieval info: PRIVATE: ROTATE_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ROTATE_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ROTATE_OUT_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ROTATE_OUT_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ROTATE_OUT_REG STRING "1"
// Retrieval info: PRIVATE: ROTATE_PIPE_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ROTATE_PIPE_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ROTATE_PIPE_REG STRING "1"
// Retrieval info: PRIVATE: ROTATE_REG STRING "1"
// Retrieval info: PRIVATE: RQFORMAT STRING "Q1.15"
// Retrieval info: PRIVATE: RTS_WIDTH STRING "32"
// Retrieval info: PRIVATE: SAME_CONFIG NUMERIC "1"
// Retrieval info: PRIVATE: SAME_CONTROL_SRC_A0 NUMERIC "1"
// Retrieval info: PRIVATE: SAME_CONTROL_SRC_B0 NUMERIC "1"
// Retrieval info: PRIVATE: SCANOUTA NUMERIC "0"
// Retrieval info: PRIVATE: SCANOUTB NUMERIC "0"
// Retrieval info: PRIVATE: SHIFTOUTA_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: SHIFTOUTA_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: SHIFTOUTA_REG STRING "0"
// Retrieval info: PRIVATE: SHIFT_RIGHT_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: SHIFT_RIGHT_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: SHIFT_RIGHT_OUT_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: SHIFT_RIGHT_OUT_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: SHIFT_RIGHT_OUT_REG STRING "1"
// Retrieval info: PRIVATE: SHIFT_RIGHT_PIPE_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: SHIFT_RIGHT_PIPE_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: SHIFT_RIGHT_PIPE_REG STRING "1"
// Retrieval info: PRIVATE: SHIFT_RIGHT_REG STRING "1"
// Retrieval info: PRIVATE: SHIFT_ROTATE_MODE STRING "Variable"
// Retrieval info: PRIVATE: SIGNA STRING "UNSIGNED"
// Retrieval info: PRIVATE: SIGNA_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: SIGNA_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: SIGNA_PIPE_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: SIGNA_PIPE_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: SIGNA_PIPE_REG STRING "1"
// Retrieval info: PRIVATE: SIGNA_REG STRING "1"
// Retrieval info: PRIVATE: SIGNB STRING "UNSIGNED"
// Retrieval info: PRIVATE: SIGNB_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: SIGNB_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: SIGNB_PIPE_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: SIGNB_PIPE_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: SIGNB_PIPE_REG STRING "1"
// Retrieval info: PRIVATE: SIGNB_REG STRING "1"
// Retrieval info: PRIVATE: SRCA0 STRING "Multiplier input"
// Retrieval info: PRIVATE: SRCB0 STRING "Multiplier input"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: WIDTHA STRING "32"
// Retrieval info: PRIVATE: WIDTHB STRING "32"
// Retrieval info: PRIVATE: ZERO_CHAINOUT_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ZERO_CHAINOUT_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_CHAINOUT_REG STRING "0"
// Retrieval info: PRIVATE: ZERO_LOOPBACK_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ZERO_LOOPBACK_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_LOOPBACK_OUT_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ZERO_LOOPBACK_OUT_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_LOOPBACK_OUT_REG STRING "1"
// Retrieval info: PRIVATE: ZERO_LOOPBACK_PIPE_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ZERO_LOOPBACK_PIPE_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_LOOPBACK_PIPE_REG STRING "1"
// Retrieval info: PRIVATE: ZERO_LOOPBACK_REG STRING "1"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ACCUMULATOR STRING "NO"
// Retrieval info: CONSTANT: ADDNSUB_MULTIPLIER_ACLR1 STRING "UNUSED"
// Retrieval info: CONSTANT: ADDNSUB_MULTIPLIER_PIPELINE_ACLR1 STRING "UNUSED"
// Retrieval info: CONSTANT: ADDNSUB_MULTIPLIER_PIPELINE_REGISTER1 STRING "CLOCK0"
// Retrieval info: CONSTANT: ADDNSUB_MULTIPLIER_REGISTER1 STRING "CLOCK0"
// Retrieval info: CONSTANT: CHAINOUT_ADDER STRING "NO"
// Retrieval info: CONSTANT: CHAINOUT_REGISTER STRING "UNREGISTERED"
// Retrieval info: CONSTANT: DEDICATED_MULTIPLIER_CIRCUITRY STRING "YES"
// Retrieval info: CONSTANT: INPUT_ACLR_A0 STRING "UNUSED"
// Retrieval info: CONSTANT: INPUT_ACLR_B0 STRING "UNUSED"
// Retrieval info: CONSTANT: INPUT_REGISTER_A0 STRING "CLOCK0"
// Retrieval info: CONSTANT: INPUT_REGISTER_B0 STRING "CLOCK0"
// Retrieval info: CONSTANT: INPUT_SOURCE_A0 STRING "DATAA"
// Retrieval info: CONSTANT: INPUT_SOURCE_B0 STRING "DATAB"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altmult_add"
// Retrieval info: CONSTANT: MULTIPLIER1_DIRECTION STRING "ADD"
// Retrieval info: CONSTANT: MULTIPLIER_ACLR0 STRING "UNUSED"
// Retrieval info: CONSTANT: MULTIPLIER_REGISTER0 STRING "CLOCK0"
// Retrieval info: CONSTANT: NUMBER_OF_MULTIPLIERS NUMERIC "1"
// Retrieval info: CONSTANT: OUTPUT_ACLR STRING "UNUSED"
// Retrieval info: CONSTANT: OUTPUT_REGISTER STRING "CLOCK0"
// Retrieval info: CONSTANT: PORT_ADDNSUB1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SIGNA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SIGNB STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: REPRESENTATION_A STRING "UNSIGNED"
// Retrieval info: CONSTANT: REPRESENTATION_B STRING "UNSIGNED"
// Retrieval info: CONSTANT: ROTATE_ACLR STRING "UNUSED"
// Retrieval info: CONSTANT: ROTATE_OUTPUT_ACLR STRING "UNUSED"
// Retrieval info: CONSTANT: ROTATE_OUTPUT_REGISTER STRING "CLOCK0"
// Retrieval info: CONSTANT: ROTATE_PIPELINE_ACLR STRING "UNUSED"
// Retrieval info: CONSTANT: ROTATE_PIPELINE_REGISTER STRING "CLOCK0"
// Retrieval info: CONSTANT: ROTATE_REGISTER STRING "CLOCK0"
// Retrieval info: CONSTANT: SHIFT_MODE STRING "VARIABLE"
// Retrieval info: CONSTANT: SHIFT_RIGHT_ACLR STRING "UNUSED"
// Retrieval info: CONSTANT: SHIFT_RIGHT_OUTPUT_ACLR STRING "UNUSED"
// Retrieval info: CONSTANT: SHIFT_RIGHT_OUTPUT_REGISTER STRING "CLOCK0"
// Retrieval info: CONSTANT: SHIFT_RIGHT_PIPELINE_ACLR STRING "UNUSED"
// Retrieval info: CONSTANT: SHIFT_RIGHT_PIPELINE_REGISTER STRING "CLOCK0"
// Retrieval info: CONSTANT: SHIFT_RIGHT_REGISTER STRING "CLOCK0"
// Retrieval info: CONSTANT: SIGNED_ACLR_A STRING "UNUSED"
// Retrieval info: CONSTANT: SIGNED_ACLR_B STRING "UNUSED"
// Retrieval info: CONSTANT: SIGNED_PIPELINE_ACLR_A STRING "UNUSED"
// Retrieval info: CONSTANT: SIGNED_PIPELINE_ACLR_B STRING "UNUSED"
// Retrieval info: CONSTANT: SIGNED_PIPELINE_REGISTER_A STRING "CLOCK0"
// Retrieval info: CONSTANT: SIGNED_PIPELINE_REGISTER_B STRING "CLOCK0"
// Retrieval info: CONSTANT: SIGNED_REGISTER_A STRING "CLOCK0"
// Retrieval info: CONSTANT: SIGNED_REGISTER_B STRING "CLOCK0"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "32"
// Retrieval info: CONSTANT: WIDTH_B NUMERIC "32"
// Retrieval info: CONSTANT: WIDTH_CHAININ NUMERIC "1"
// Retrieval info: CONSTANT: WIDTH_RESULT NUMERIC "32"
// Retrieval info: CONSTANT: ZERO_CHAINOUT_OUTPUT_ACLR STRING "UNUSED"
// Retrieval info: CONSTANT: ZERO_CHAINOUT_OUTPUT_REGISTER STRING "CLOCK0"
// Retrieval info: CONSTANT: ZERO_LOOPBACK_ACLR STRING "UNUSED"
// Retrieval info: CONSTANT: ZERO_LOOPBACK_OUTPUT_ACLR STRING "UNUSED"
// Retrieval info: CONSTANT: ZERO_LOOPBACK_OUTPUT_REGISTER STRING "CLOCK0"
// Retrieval info: CONSTANT: ZERO_LOOPBACK_PIPELINE_ACLR STRING "UNUSED"
// Retrieval info: CONSTANT: ZERO_LOOPBACK_PIPELINE_REGISTER STRING "CLOCK0"
// Retrieval info: CONSTANT: ZERO_LOOPBACK_REGISTER STRING "CLOCK0"
// Retrieval info: USED_PORT: clock0 0 0 0 0 INPUT VCC "clock0"
// Retrieval info: USED_PORT: dataa_0 0 0 32 0 INPUT GND "dataa_0[31..0]"
// Retrieval info: USED_PORT: datab_0 0 0 32 0 INPUT GND "datab_0[31..0]"
// Retrieval info: USED_PORT: result 0 0 32 0 OUTPUT GND "result[31..0]"
// Retrieval info: USED_PORT: rotate 0 0 0 0 INPUT GND "rotate"
// Retrieval info: USED_PORT: shift_right 0 0 0 0 INPUT GND "shift_right"
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock0 0 0 0 0
// Retrieval info: CONNECT: @dataa 0 0 32 0 dataa_0 0 0 32 0
// Retrieval info: CONNECT: @datab 0 0 32 0 datab_0 0 0 32 0
// Retrieval info: CONNECT: @rotate 0 0 0 0 rotate 0 0 0 0
// Retrieval info: CONNECT: @shift_right 0 0 0 0 shift_right 0 0 0 0
// Retrieval info: CONNECT: result 0 0 32 0 @result 0 0 32 0
// Retrieval info: GEN_FILE: TYPE_NORMAL dsp_shift_megafn.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL dsp_shift_megafn.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL dsp_shift_megafn.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL dsp_shift_megafn.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL dsp_shift_megafn_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL dsp_shift_megafn_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
dsp_shift_megafn dsp_shift_megafn_inst (
.clock0 ( clock0_sig ),
.dataa_0 ( dataa_0_sig ),
.datab_0 ( datab_0_sig ),
.rotate ( rotate_sig ),
.shift_right ( shift_right_sig ),
.result ( result_sig )
);
|
// Quartus II Verilog Template
// Barrel shifter
module barrel_shifter
#(parameter M=8, parameter N=2**M)
(
input [N-1:0] data,
input [M-1:0] distance,
input clk, enable, shift_left,
output reg [N-1:0] sr_out
);
// Declare temporary registers
reg [2*N-1:0] tmp;
// Shift/rotate in the specified direction and
// by the specified amount
always @ (posedge clk)
begin
tmp = {data,data};
if (enable == 1'b1)
if (shift_left)
begin
tmp = tmp << distance;
sr_out <= tmp[2*N-1:N];
end
else
begin
tmp = tmp >> distance;
sr_out <= tmp[N-1:0];
end
end
endmodule
|
// Quartus II Verilog Template
// One-bit wide, N-bit long shift register
module basic_shift_register
#(parameter N=256)
(
input clk, enable,
input sr_in,
output sr_out
);
// Declare the shift register
reg [N-1:0] sr;
// Shift everything over, load the incoming bit
always @ (posedge clk)
begin
if (enable == 1'b1)
begin
sr[N-1:1] <= sr[N-2:0];
sr[0] <= sr_in;
end
end
// Catch the outgoing bit
assign sr_out = sr[N-1];
endmodule
|
// Quartus II Verilog Template
// One-bit wide, N-bit long shift register with asynchronous reset
module basic_shift_register_asynchronous_reset
#(parameter N=256)
(
input clk, enable, reset,
input sr_in,
output sr_out
);
// Declare the shift register
reg [N-1:0] sr;
// Shift everything over, load the incoming bit
always @ (posedge clk or posedge reset)
begin
if (reset == 1'b1)
begin
// Load N zeros
sr <= {N{1'b0}};
end
else if (enable == 1'b1)
begin
sr[N-1:1] <= sr[N-2:0];
sr[0] <= sr_in;
end
end
// Catch the outgoing bit
assign sr_out = sr[N-1];
endmodule
|
// Quartus II Verilog Template
// Basic 64-stage shift register with multiple taps
module basic_shift_register_with_multiple_taps
#(parameter WIDTH=8, parameter LENGTH=64)
(
input clk, enable,
input [WIDTH-1:0] sr_in,
output [WIDTH-1:0] sr_tap_one, sr_tap_two, sr_tap_three, sr_out
);
// Declare the shift register
reg [WIDTH-1:0] sr [LENGTH-1:0];
// Declare an iterator
integer n;
always @ (posedge clk)
begin
if (enable == 1'b1)
begin
// Shift everything over, load the incoming data
for (n = LENGTH-1; n>0; n = n-1)
begin
sr[n] <= sr[n-1];
end
// Shift one position in
sr[0] <= sr_in;
end
end
assign sr_tap_one = sr[LENGTH/4-1];
assign sr_tap_two = sr[LENGTH/2-1];
assign sr_tap_three = sr[3*LENGTH/4-1];
// Catch the outgoing data
assign sr_out = sr[LENGTH-1];
endmodule
|
// Quartus II Verilog Template
// Binary counter
module binary_counter
#(parameter WIDTH=64)
(
input clk, enable, reset,
output reg [WIDTH-1:0] count
);
// Reset if needed, or increment if counting is enabled
always @ (posedge clk or posedge reset)
begin
if (reset)
count <= 0;
else if (enable == 1'b1)
count <= count + 1;
end
endmodule
|
// Quartus II Verilog Template
// Binary up/down counter
module binary_up_down_counter
#(parameter WIDTH=64)
(
input clk, enable, count_up, reset,
output reg [WIDTH-1:0] count
);
// Reset if needed, increment or decrement if counting is enabled
always @ (posedge clk or posedge reset)
begin
if (reset)
count <= 0;
else if (enable == 1'b1)
count <= count + (count_up ? 1 : -1);
end
endmodule
|
// Quartus II Verilog Template
// Binary up/down counter with saturation
module binary_up_down_counter_with_saturation
#(parameter WIDTH=32)
(
input clk, enable, count_up, reset,
output reg [WIDTH-1:0] count
);
reg [WIDTH-1:0] direction;
reg [WIDTH-1:0] limit;
// Reset if needed, increment or decrement if counter is not saturated
always @ (posedge clk or posedge reset)
begin
if (reset)
count <= 0;
else if (enable == 1'b1)
begin
if (count_up)
begin
direction <= 1;
limit <= {WIDTH{1'b1}}; // max value is all 1's
end
else
begin
direction <= -1;
limit <= {WIDTH{1'b0}};
end
if (count != limit)
count <= count + direction;
end
end
endmodule
|
module dsp_shift
#(parameter INPUT_WIDTH=32, parameter OUTPUT_WIDTH=32)
(
input clk, rotate, shift_right,
input [INPUT_WIDTH-1:0] dataa, datab,
output [OUTPUT_WIDTH-1:0] result
);
dsp_shift_megafn dsp_shift_megafn_inst (
.clock0 ( clk ),
.dataa_0 ( dataa ),
.datab_0 ( datab ),
.rotate ( rotate ),
.shift_right ( shift_right ),
.result ( result )
);
endmodule
|
`define SHIFT 1
`define BARREL_SHIFTER 1
`define ADD 1
`define COUNT 1
`define MULT 1
`define ACCUMULATE 1
`define SUM_OF 1
module dsp_test (
// Input Ports
input clk_1,
input enable,
input reset,
input aclr,
input sr_in,
input cin,
input add_sub,
input sload,
input [7:0] distance,
input [6:0] sel,
input [35:0] in_data_a,
input [35:0] in_data_b,
input [17:0] in_data_c,
input [17:0] in_data_d,
input [17:0] in_data_e,
input [17:0] in_data_f,
input [17:0] in_data_g,
input [17:0] in_data_h,
input [31:0] barrel_shifter_in,
// Output Ports
output [31:0] barrel_shifter_out,
output reg [71:0] data_out_a,
output reg [35:0] data_out_b,
output reg [7:0] data_out_c,
output reg [7:0] data_out_d
);
wire out_data_a_000;
wire out_data_a_001;
wire [7:0] out_data_a_003;
wire [7:0] out_data_b_003;
wire [7:0] out_data_c_003;
wire [7:0] out_data_d_003;
wire [16:0] out_data_a_004;
wire [16:0] out_data_a_004a;
wire [16:0] out_data_a_005;
wire [16:0] out_data_a_006;
wire [15:0] out_data_a_007;
wire [63:0] out_data_a_008;
wire [63:0] out_data_a_009;
wire [31:0] out_data_a_010;
wire [7:0] out_data_a_011;
wire [15:0] out_data_a_012;
wire [23:0] out_data_a_013;
wire [35:0] out_data_a_014;
wire [17:0] out_data_a_015;
wire [35:0] out_data_a_016;
wire [35:0] out_data_b_016;
wire [15:0] out_data_a_017a;
wire [17:0] out_data_a_017b;
wire [35:0] out_data_a_017c;
wire [23:0] out_data_a_018a;
wire [71:0] out_data_a_018b;
wire [43:0] out_data_a_019;
wire [31:0] out_data_a_020;
wire [37:0] out_data_a_021;
wire [32:0] out_data_a_022;
wire [37:0] out_data_a_023;
wire [37:0] out_data_a_024;
wire [54:0] out_data_a_025;
wire [43:0] out_data_a_026;
wire [35:0] out_data_a_027;
wire [43:0] out_data_a_028;
wire [17:0] out_data_b_028;
wire [31:0] out_data_a_029;
//Massive Mux to prevent outputs from being optimized away
/* Output select mux */
always@(*) begin
case(sel)
0: begin
data_out_a <= out_data_a_003;
data_out_b <= out_data_b_003;
data_out_c <= out_data_c_003;
data_out_d <= out_data_d_003;
end
1: begin
data_out_a <= out_data_a_004;
data_out_b <= 0;
data_out_c <= 0;
data_out_d <= 0;
end
2: begin
data_out_a <= out_data_a_004a;
data_out_b <= 0;
data_out_c <= 0;
data_out_d <= 0;
end
3: begin
data_out_a <= out_data_a_005;
data_out_b <= 0;
data_out_c <= 0;
data_out_d <= 0;
end
4: begin
data_out_a <= out_data_a_006;
data_out_b <= 0;
data_out_c <= 0;
data_out_d <= 0;
end
5: begin
data_out_a <= out_data_a_007;
data_out_b <= 0;
data_out_c <= 0;
data_out_d <= 0;
end
6: begin
data_out_a <= out_data_a_008;
data_out_b <= 0;
data_out_c <= 0;
data_out_d <= 0;
end
7: begin
data_out_a <= out_data_a_009;
data_out_b <= 0;
data_out_c <= 0;
data_out_d <= 0;
end
8: begin
data_out_a <= out_data_a_010;
data_out_b <= 0;
data_out_c <= 0;
data_out_d <= 0;
end
9: begin
data_out_a <= out_data_a_011;
data_out_b <= 0;
data_out_c <= 0;
data_out_d <= 0;
end
10: begin
data_out_a <= out_data_a_012;
data_out_b <= 0;
data_out_c <= 0;
data_out_d <= 0;
end
11: begin
data_out_a <= out_data_a_013;
data_out_b <= 0;
data_out_c <= 0;
data_out_d <= 0;
end
12: begin
data_out_a <= out_data_a_014;
data_out_b <= 0;
data_out_c <= 0;
data_out_d <= 0;
end
13: begin
data_out_a <= out_data_a_015;
data_out_b <= 0;
data_out_c <= 0;
data_out_d <= 0;
end
14: begin
data_out_a <= out_data_a_016;
data_out_b <= out_data_b_016;
data_out_c <= 0;
data_out_d <= 0;
end
15: begin
data_out_a <= out_data_a_017a;
data_out_b <= 0;
data_out_c <= 0;
data_out_d <= 0;
end
16: begin
data_out_a <= out_data_a_017b;
data_out_b <= 0;
data_out_c <= 0;
data_out_d <= 0;
end
17: begin
data_out_a <= out_data_a_017c;
data_out_b <= 0;
data_out_c <= 0;
data_out_d <= 0;
end
18: begin
data_out_a <= out_data_a_018a;
data_out_b <= 0;
data_out_c <= 0;
data_out_d <= 0;
end
19: begin
data_out_a <= out_data_a_018b;
data_out_b <= 0;
data_out_c <= 0;
data_out_d <= 0;
end
20: begin
data_out_a <= out_data_a_019;
data_out_b <= 0;
data_out_c <= 0;
data_out_d <= 0;
end
21: begin
data_out_a <= out_data_a_020;
data_out_b <= 0;
data_out_c <= 0;
data_out_d <= 0;
end
22: begin
data_out_a <= out_data_a_021;
data_out_b <= 0;
data_out_c <= 0;
data_out_d <= 0;
end
23: begin
data_out_a <= out_data_a_022;
data_out_b <= 0;
data_out_c <= 0;
data_out_d <= 0;
end
24: begin
data_out_a <= out_data_a_023;
data_out_b <= 0;
data_out_c <= 0;
data_out_d <= 0;
end
25: begin
data_out_a <= out_data_a_024;
data_out_b <= 0;
data_out_c <= 0;
data_out_d <= 0;
end
26: begin
data_out_a <= out_data_a_000;
data_out_b <= 0;
data_out_c <= 0;
data_out_d <= 0;
end
27: begin
data_out_a <= out_data_a_001;
data_out_b <= 0;
data_out_c <= 0;
data_out_d <= 0;
end
28: begin
data_out_a <= out_data_a_025;
data_out_b <= 0;
data_out_c <= 0;
data_out_d <= 0;
end
29: begin
data_out_a <= out_data_a_026;
data_out_b <= 0;
data_out_c <= 0;
data_out_d <= 0;
end
30: begin
data_out_a <= out_data_a_027;
data_out_b <= 0;
data_out_c <= 0;
data_out_d <= 0;
end
31: begin
data_out_a <= out_data_a_028;
data_out_b <= out_data_b_028;
data_out_c <= 0;
data_out_d <= 0;
end
32: begin
data_out_a <= out_data_a_029;
data_out_b <= 0;
data_out_c <= 0;
data_out_d <= 0;
end
default: begin
data_out_a <= 0;
data_out_b <= 0;
data_out_c <= 0;
data_out_d <= 0;
end
endcase
end
// Module Item(s)
`ifdef SHIFT
basic_shift_register #(.N(256)) inst000 (
.clk (clk_1),
.enable (enable),
.sr_in (sr_in),
.sr_out (out_data_a_000)
);
`ifdef BARREL_SHIFTER
basic_shift_register_asynchronous_reset #(.N(256)) inst001 (
.clk (clk_1),
.enable (enable),
.reset (reset),
.sr_in (sr_in),
.sr_out (out_data_a_001)
);
`endif //BARREL_SHIFTER
barrel_shifter #(.M(8), .N(32)) inst002 (
.data (barrel_shifter_in),
.distance (distance),
.clk (clk_1),
.enable (enable),
.shift_left (sr_in),
.sr_out (barrel_shifter_out)
);
basic_shift_register_with_multiple_taps #(.WIDTH(8), .LENGTH(64)) inst003 (
.clk (clk_1),
.enable (enable),
.sr_in (in_data_a[7:0]),
.sr_tap_one (out_data_a_003),
.sr_tap_two (out_data_b_003),
.sr_tap_three (out_data_c_003),
.sr_out (out_data_d_003)
);
scanouta_chain inst028 (
.clk (clk_1),
.dataa (in_data_a[17:0]),
.datab (in_data_b[17:0]),
.datac (in_data_c[17:0]),
.datad (in_data_d[17:0]),
.datae (in_data_e[17:0]),
.dataout (out_data_a_028),
.shiftouta (out_data_b_028)
);
dsp_shift inst029 (
.clk(clk_1),
.rotate(in_data_c[0]),
.shift_right(in_data_c[1]),
.dataa(in_data_a[31:0]),
.datab(in_data_b[31:0]),
.result(out_data_a_029),
);
`endif //SHIFT
`ifdef ADD
signed_adder #(.WIDTH(16)) inst004(
.dataa (in_data_a[15:0]),
.datab (in_data_b[15:0]),
.cin (cin),
.result (out_data_a_004[16:0])
);
unsigned_adder #(.WIDTH(16)) inst004a(
.dataa (in_data_a[15:0]),
.datab (in_data_b[15:0]),
.cin (cin),
.result (out_data_a_004a[16:0])
);
signed_adder_subtractor #(.WIDTH(16)) inst005 (
.dataa (in_data_a[15:0]),
.datab (in_data_b[15:0]),
.add_sub (add_sub), // if this is 1, add; else subtract
.clk (clk_1),
.result (out_data_a_005[16:0])
);
unsigned_adder_subtractor #(.WIDTH(16)) inst006 (
.dataa (in_data_a[15:0]),
.datab (in_data_b[15:0]),
.add_sub (add_sub), // if this is 1, add; else subtract
.clk (clk_1),
.result (out_data_a_006[16:0])
);
pipelined_binary_adder_tree #(.WIDTH(16)) inst007 (
.A (in_data_a[15:0]),
.B (in_data_b[15:0]),
.C (in_data_c[15:0]),
.D (in_data_d[15:0]),
.E (in_data_e[15:0]),
.clk (clk_1),
.out (out_data_a_007[15:0])
);
`endif //ADD
`ifdef COUNT
binary_counter #(.WIDTH(64)) inst008 (
.clk (clk_1),
.enable (enable),
.reset (reset),
.count (out_data_a_008[63:0])
);
binary_up_down_counter #(.WIDTH(64)) inst009 (
.clk(clk_1),
.enable(enable),
.count_up(enable),
.reset(reset),
.count(out_data_a_009[63:0])
);
binary_up_down_counter_with_saturation #(.WIDTH(32)) inst010 (
.clk (clk_1),
.enable (enable),
.count_up (enable),
.reset (reset),
.count (out_data_a_010[31:0])
);
gray_counter #(.WIDTH(8)) inst011 (
.clk (clk_1),
.enable (enable),
.reset (reset),
.gray_count (out_data_a_011[7:0])
);
`endif //COUNT
`ifdef MULT
unsigned_multiply #(.WIDTH(8)) inst012 (
.dataa (in_data_a[7:0]),
.datab (in_data_b[7:0]),
.dataout (out_data_a_012[15:0])
);
signed_multiply #(.WIDTH(12)) inst013 (
.dataa (in_data_a[11:0]),
.datab (in_data_b[11:0]),
.dataout (out_data_a_013[23:0])
);
unsigned_multiply_with_input_and_output_registers #(.WIDTH(18)) inst014 (
.clk (clk_1),
.dataa (in_data_a[17:0]),
.datab (in_data_b[17:0]),
.dataout (out_data_a_014[35:0])
);
signed_multiply_with_input_and_output_registers #(.WIDTH(9)) inst015 (
.clk (clk_1),
.dataa (in_data_a[8:0]),
.datab (in_data_b[8:0]),
.dataout (out_data_a_015[17:0])
);
multiplier_for_complex_numbers #(.WIDTH(18)) inst016 (
.clk (clk_1),
.ena (enable),
.dataa_real (in_data_a[17:0]),
.dataa_img (in_data_b[17:0]),
.datab_real (in_data_c[17:0]),
.datab_img (in_data_d[17:0]),
.dataout_real (out_data_a_016[35:0]),
.dataout_img (out_data_b_016[35:0])
);
two_mult_loopback inst027 (
.clk(clk_1),
.dataa(in_data_a[17:0]),
.datab(in_data_b[17:0]),
.datac(in_data_c[17:0]),
.dataout(out_data_a_027)
);
`ifdef ACCUMULATE
unsigned_multiply_accumulate #(.WIDTH(8)) inst017a (
.clk (clk_1),
.aclr (aclr),
.clken (enable),
.sload (sload),
.dataa (in_data_a[7:0]),
.datab (in_data_a[7:0]),
.adder_out (out_data_a_017a[15:0])
);
unsigned_multiply_accumulate #(.WIDTH(9)) inst017b (
.clk (clk_1),
.aclr (aclr),
.clken (enable),
.sload (sload),
.dataa (in_data_a[8:0]),
.datab (in_data_a[8:0]),
.adder_out (out_data_a_017b[17:0])
);
unsigned_multiply_accumulate #(.WIDTH(18)) inst017c (
.clk (clk_1),
.aclr (aclr),
.clken (enable),
.sload (sload),
.dataa (in_data_a[17:0]),
.datab (in_data_a[17:0]),
.adder_out (out_data_a_017c[35:0])
);
signed_multiply_accumulate #(.WIDTH(12)) inst018a (
.clk (clk_1),
.aclr (aclr),
.clken (enable),
.sload (sload),
.dataa (in_data_a[11:0]),
.datab (in_data_a[11:0]),
.adder_out (out_data_a_018a[23:0])
);
signed_multiply_accumulate #(.WIDTH(36)) inst018b (
.clk (clk_1),
.aclr (aclr),
.clken (enable),
.sload (sload),
.dataa (in_data_a[35:0]),
.datab (in_data_a[35:0]),
.adder_out (out_data_a_018b[71:0])
);
`ifdef SUM_OF
sum_of_four_multiply_accumulate #(.INPUT_WIDTH(18), .OUTPUT_WIDTH(44)) inst019(
.clk (clk_1),
.ena (enable),
.dataa (in_data_a[17:0]),
.datab (in_data_b[17:0]),
.datac (in_data_c[17:0]),
.datad (in_data_d[17:0]),
.datae (in_data_e[17:0]),
.dataf (in_data_f[17:0]),
.datag (in_data_g[17:0]),
.datah (in_data_h[17:0]),
.dataout (out_data_a_019[43:0])
);
sum_of_four_multiply_accumulate_with_asynchronous_reset #(.INPUT_WIDTH(9), .OUTPUT_WIDTH(32)) inst020(
.clk (clk_1),
.ena (enable),
.aclr (aclr),
.dataa (in_data_a[8:0]),
.datab (in_data_b[8:0]),
.datac (in_data_c[8:0]),
.datad (in_data_d[8:0]),
.datae (in_data_e[8:0]),
.dataf (in_data_f[8:0]),
.datag (in_data_g[8:0]),
.datah (in_data_h[8:0]),
.dataout (out_data_a_020[31:0])
);
`endif //SUM_OF
`endif //ACCUMULATE
`ifdef SUM_OF
sum_of_four_multipliers #(.WIDTH(18)) inst021 (
.clk (clk_1),
.ena (enable),
.dataa (in_data_a[17:0]),
.datab (in_data_b[17:0]),
.datac (in_data_c[17:0]),
.datad (in_data_d[17:0]),
.datae (in_data_e[17:0]),
.dataf (in_data_f[17:0]),
.datag (in_data_g[17:0]),
.datah (in_data_h[17:0]),
.dataout (out_data_a_021[37:0])
);
sum_of_two_multipliers_pipeline #(.WIDTH(16)) inst022 (
.clock (clk_1),
.aclr (aclr),
.dataa (in_data_a[15:0]),
.datab (in_data_b[15:0]),
.datac (in_data_c[15:0]),
.datad (in_data_d[15:0]),
.result (out_data_a_022[32:0])
);
sum_of_four_multipliers_scan_chain #(.WIDTH(18)) inst023 (
.clk (clk_1),
.ena (enable),
.dataa (in_data_a[17:0]),
.datab0 (in_data_b[17:0]),
.datab1 (in_data_c[17:0]),
.datab2 (in_data_d[17:0]),
.datab3 (in_data_e[17:0]),
.dataout (out_data_a_023[37:0])
);
sum_of_eight_multipliers_chainout #(.WIDTH(18)) inst024 (
.clk (clk_1),
.ena (enable),
.a0 (in_data_h[17:0]),
.a1 (in_data_g[17:0]),
.a2 (in_data_f[17:0]),
.a3 (in_data_e[17:0]),
.a4 (in_data_d[17:0]),
.a5 (in_data_c[17:0]),
.a6 (in_data_b[17:0]),
.a7 (in_data_a[17:0]),
.b0 (in_data_a[17:0]),
.b1 (in_data_b[17:0]),
.b2 (in_data_c[17:0]),
.b3 (in_data_d[17:0]),
.b4 (in_data_e[17:0]),
.b5 (in_data_f[17:0]),
.b6 (in_data_g[17:0]),
.b7 (in_data_h[17:0]),
.dataout (out_data_a_024[37:0])
);
sum_of_two_multipliers_wide_datapath #(.WIDTH_A(36), .WIDTH_B(18)) inst025 (
.clk (clk_1),
.ena (enable),
.a0 (in_data_a[35:0]),
.a1 (in_data_b[35:0]),
.b0 (in_data_c[17:0]),
.b1 (in_data_d[17:0]),
.dataout (out_data_a_025[54:0])
);
sum_of_four_multiply_accumulate_chainout inst026 (
.clk (clk_1),
.dataa (in_data_a[17:0]),
.datab (in_data_a[17:0]),
.datac (in_data_a[17:0]),
.datad (in_data_a[17:0]),
.datae (in_data_a[17:0]),
.dataf (in_data_a[17:0]),
.datag (in_data_a[17:0]),
.datah (in_data_a[17:0]),
.dataout (out_data_a_026)
);
`endif //SUM_OF
`endif //MULT
endmodule
|
// Quartus II Verilog Template
// Gray counter
module gray_counter
#(parameter WIDTH=8)
(
input clk, enable, reset,
output reg [WIDTH-1:0] gray_count
);
// Implementation:
// There's an imaginary bit in the counter, at q[-1], that resets to 1
// (unlike the rest of the bits of the counter) and flips every clock cycle.
// The decision of whether to flip any non-imaginary bit in the counter
// depends solely on the bits below it, down to the imaginary bit. It flips
// only if all these bits, taken together, match the pattern 10* (a one
// followed by any number of zeros).
// Almost every non-imaginary bit has a submodule instance that sets the
// bit based on the values of the lower-order bits, as described above.
// The rules have to differ slightly for the most significant bit or else
// the counter would saturate at it's highest value, 1000...0.
// q is the counter, plus the imaginary bit
reg q [WIDTH-1:-1];
// no_ones_below[x] = 1 iff there are no 1's in q below q[x]
reg no_ones_below [WIDTH-1:-1];
// q_msb is a modification to make the msb logic work
reg q_msb;
integer i, j, k;
always @ (posedge reset or posedge clk)
begin
if (reset)
begin
// Resetting involves setting the imaginary bit to 1
q[-1] <= 1;
for (i = 0; i <= WIDTH-1; i = i + 1)
q[i] <= 0;
end
else if (enable)
begin
// Toggle the imaginary bit
q[-1] <= ~q[-1];
for (i = 0; i < WIDTH-1; i = i + 1)
begin
// Flip q[i] if lower bits are a 1 followed by all 0's
q[i] <= q[i] ^ (q[i-1] & no_ones_below[i-1]);
end
q[WIDTH-1] <= q[WIDTH-1] ^ (q_msb & no_ones_below[WIDTH-2]);
end
end
always @(*)
begin
// There are never any 1's beneath the lowest bit
no_ones_below[-1] <= 1;
for (j = 0; j < WIDTH-1; j = j + 1)
no_ones_below[j] <= no_ones_below[j-1] & ~q[j-1];
q_msb <= q[WIDTH-1] | q[WIDTH-2];
// Copy over everything but the imaginary bit
for (k = 0; k < WIDTH; k = k + 1)
gray_count[k] <= q[k];
end
endmodule
|
// Quartus II Verilog Template
// Multiplier for complex numbers
module multiplier_for_complex_numbers
#(parameter WIDTH=18)
(
input clk, ena,
input signed [WIDTH-1:0] dataa_real, dataa_img,
input signed [WIDTH-1:0] datab_real, datab_img,
output reg signed [2*WIDTH-1:0] dataout_real, dataout_img
);
always @ (posedge clk)
begin
if (ena == 1)
begin
dataout_real = dataa_real * datab_real - dataa_img * datab_img;
dataout_img = dataa_real * datab_img + datab_real * dataa_img;
end
end
endmodule
|
// Quartus II Verilog Template
// Pipelined binary adder tree
module pipelined_binary_adder_tree
#(parameter WIDTH=16)
(
input [WIDTH-1:0] A, B, C, D, E,
input clk,
output [WIDTH-1:0] out
);
wire [WIDTH-1:0] sum1, sum2, sum3, sum4;
reg [WIDTH-1:0] sumreg1, sumreg2, sumreg3, sumreg4;
always @ (posedge clk)
begin
sumreg1 <= sum1;
sumreg2 <= sum2;
sumreg3 <= sum3;
sumreg4 <= sum4;
end
// 2-bit additions
assign sum1 = A + B;
assign sum2 = C + D;
assign sum3 = sumreg1 + sumreg2;
assign sum4 = sumreg3 + E;
assign out = sumreg4;
endmodule
|
module scanouta_chain
#(parameter INPUT_WIDTH=18, parameter OUTPUT_WIDTH=44)
(
input clk,
input [INPUT_WIDTH-1:0] dataa, datab, datac, datad, datae,
output [OUTPUT_WIDTH-1:0] dataout,
output [INPUT_WIDTH-1:0] shiftouta
);
scanout_chain_megafn scanout_chain_megafn_inst (
.clock0 ( clk ),
.dataa_0 ( dataa ),
.datab_0 ( datab ),
.datab_1 ( datac ),
.datab_2 ( datad ),
.datab_3 ( datate ),
.result ( dataout ),
.shiftouta ( shiftouta )
);
endmodule
|
// Quartus II Verilog Template
// Signed adder
module signed_adder
#(parameter WIDTH=16)
(
input signed [WIDTH-1:0] dataa,
input signed [WIDTH-1:0] datab,
input cin,
output [WIDTH:0] result
);
assign result = dataa + datab + cin;
endmodule
|
// Quartus II Verilog Template
// Signed adder/subtractor
module signed_adder_subtractor
#(parameter WIDTH=16)
(
input signed [WIDTH-1:0] dataa,
input signed [WIDTH-1:0] datab,
input add_sub, // if this is 1, add; else subtract
input clk,
output reg [WIDTH:0] result
);
always @ (posedge clk)
begin
if (add_sub)
result <= dataa + datab;
else
result <= dataa - datab;
end
endmodule
|
// Quartus II Verilog Template
// Signed multiply
module signed_multiply
#(parameter WIDTH=8)
(
input signed [WIDTH-1:0] dataa,
input signed [WIDTH-1:0] datab,
output [2*WIDTH-1:0] dataout
);
assign dataout = dataa * datab;
endmodule
|
// Quartus II Verilog Template
// Signed multiply-accumulate
module signed_multiply_accumulate
#(parameter WIDTH=8)
(
input clk, aclr, clken, sload,
input signed [WIDTH-1:0] dataa,
input signed [WIDTH-1:0] datab,
output reg signed [2*WIDTH-1:0] adder_out
);
// Declare registers and wires
reg signed [WIDTH-1:0] dataa_reg, datab_reg;
reg sload_reg;
reg signed [2*WIDTH-1:0] old_result;
wire signed [2*WIDTH-1:0] multa;
// Store the results of the operations on the current data
assign multa = dataa_reg * datab_reg;
// Store (or clear) old results
always @ (adder_out, sload_reg)
begin
if (sload_reg)
old_result <= 0;
else
old_result <= adder_out;
end
// Clear or update data, as appropriate
always @ (posedge clk or posedge aclr)
begin
if (aclr)
begin
dataa_reg <= 0;
datab_reg <= 0;
sload_reg <= 0;
adder_out <= 0;
end
else if (clken)
begin
dataa_reg <= dataa;
datab_reg <= datab;
sload_reg <= sload;
adder_out <= old_result + multa;
end
end
endmodule
|
// Quartus II Verilog Template
// Signed multiply with input and output registers
module signed_multiply_with_input_and_output_registers
#(parameter WIDTH=8)
(
input clk,
input signed [WIDTH-1:0] dataa,
input signed [WIDTH-1:0] datab,
output reg signed [2*WIDTH-1:0] dataout
);
// Declare input and output registers
reg signed [WIDTH-1:0] dataa_reg;
reg signed [WIDTH-1:0] datab_reg;
wire signed [2*WIDTH-1:0] mult_out;
// Store the result of the multiply
assign mult_out = dataa_reg * datab_reg;
// Update data
always @ (posedge clk)
begin
dataa_reg <= dataa;
datab_reg <= datab;
dataout <= mult_out;
end
endmodule
|
// Quartus II Verilog Template
// Sum of eight multipliers in chainout mode
module sum_of_eight_multipliers_chainout
#(parameter WIDTH=18)
(
input clk, ena,
input [WIDTH-1:0] a0, a1, a2, a3, a4, a5, a6, a7,
input [WIDTH-1:0] b0, b1, b2, b3, b4, b5, b6, b7,
output reg [2*WIDTH+1:0] dataout
);
// Declare wires
wire [2*WIDTH+1:0] sum1, sum2;
// Store the results of the first two sums
assign sum1 = (a0 * b0 + a1 * b1) + (a2 * b2 + a3 * b3);
assign sum2 = (a4 * b4 + a5 * b5) + (a6 * b6 + a7 * b7);
always @ (posedge clk)
begin
if (ena == 1)
begin
dataout <= sum1 + sum2;
end
end
endmodule
|
// Quartus II Verilog Template
// Sum of four multipliers
module sum_of_four_multipliers
#(parameter WIDTH=18)
(
input clk, ena,
input [WIDTH-1:0] dataa, datab, datac, datad,
input [WIDTH-1:0] datae, dataf, datag, datah,
output reg [2*WIDTH+1:0] dataout
);
always @ (posedge clk)
begin
if (ena == 1)
begin
dataout <= (dataa * datab + datac * datad) + (datae * dataf + datag * datah);
end
end
endmodule
|
// Quartus II Verilog Template
// Sum of four multipliers in scan chain mode
module sum_of_four_multipliers_scan_chain
#(parameter WIDTH=18)
(
input clk, ena,
input [WIDTH-1:0] dataa,
input [WIDTH-1:0] datab0, datab1, datab2, datab3,
output reg [2*WIDTH+1:0] dataout
);
// Four scan chain registers
reg [WIDTH-1:0] a0, a1, a2, a3;
always @ (posedge clk)
begin
if (ena == 1)
begin
// The scan chain (which mimics the behavior of a shift register)
a0 <= dataa;
a1 <= a0;
a2 <= a1;
a3 <= a2;
// The order of the operands is important for correct inference
dataout <= (a3 * datab3 + a2 * datab2) + (a1 * datab1 + a0 * datab0);
end
end
endmodule
|
// Quartus II Verilog Template
// Sum-of-four multiply-accumulate
// For use with the Stratix III device family
module sum_of_four_multiply_accumulate
#(parameter INPUT_WIDTH=18, parameter OUTPUT_WIDTH=44)
(
input clk, ena,
input [INPUT_WIDTH-1:0] dataa, datab, datac, datad,
input [INPUT_WIDTH-1:0] datae, dataf, datag, datah,
output reg [OUTPUT_WIDTH-1:0] dataout
);
// Each product can be up to 2*INPUT_WIDTH bits wide.
// The sum of four of these products can be up to 2 bits wider.
wire [2*INPUT_WIDTH+1:0] mult_sum;
// Store the results of the operations on the current inputs
assign mult_sum = (dataa * datab + datac * datad) + (datae * dataf + datag * datah);
// Store the value of the accumulation
always @ (posedge clk)
begin
if (ena == 1)
begin
dataout <= dataout + mult_sum;
end
end
endmodule
|
module sum_of_four_multiply_accumulate_chainout
#(parameter INPUT_WIDTH=18, parameter OUTPUT_WIDTH=44)
(
input clk,
input [INPUT_WIDTH-1:0] dataa, datab, datac, datad,
input [INPUT_WIDTH-1:0] datae, dataf, datag, datah,
output [OUTPUT_WIDTH-1:0] dataout
);
wire [OUTPUT_WIDTH-1:0] chain_intermediate;
mult_accum_chain mult_accum_chain_inst0 (
.chainin (/*unconnected*/),
.clock0 ( clk ),
.dataa_0 ( dataa),
.dataa_1 ( datab),
.dataa_2 ( datac),
.dataa_3 ( datad),
.datab_0 ( datae),
.datab_1 ( dataf),
.datab_2 ( datag),
.datab_3 ( datah),
.result ( chain_intermediate )
);
mult_accum_chain mult_accum_chain_inst1 (
.chainin ( chain_intermediate ),
.clock0 ( clk ),
.dataa_0 ( datae),
.dataa_1 ( datab),
.dataa_2 ( datah),
.dataa_3 ( datad),
.datab_0 ( dataa),
.datab_1 ( dataf),
.datab_2 ( datag),
.datab_3 ( datac),
.result ( dataout)
);
endmodule
|
// Quartus II Verilog Template
// Sum-of-four multiply-accumulate with asynchronous reset
// For use with the Stratix III device family
module sum_of_four_multiply_accumulate_with_asynchronous_reset
#(parameter INPUT_WIDTH=18, parameter OUTPUT_WIDTH=44)
(
input clk, ena, aclr,
input [INPUT_WIDTH-1:0] dataa, datab, datac, datad,
input [INPUT_WIDTH-1:0] datae, dataf, datag, datah,
output reg [OUTPUT_WIDTH-1:0] dataout
);
// Each product can be up to 2*INPUT_WIDTH bits wide.
// The sum of four of these products can be up to 2 bits wider.
wire [2*INPUT_WIDTH+1:0] mult_sum;
// Store the results of the operations on the current inputs
assign mult_sum = (dataa * datab + datac * datad) + (datae * dataf + datag * datah);
// Store the value of the accumulation
always @ (posedge clk)
begin
if (ena == 1)
begin
dataout <= ((aclr == 1) ? 0 : dataout) + mult_sum;
end
end
endmodule
|
// Quartus II Verilog Template
// Sum of two multipliers with pipeline registers
module sum_of_two_multipliers_pipeline
#(parameter WIDTH=16)
(
input clock, aclr,
input [WIDTH-1:0] dataa, datab, datac, datad,
output reg [2*WIDTH:0] result
);
reg [WIDTH-1:0] dataa_reg, datab_reg, datac_reg, datad_reg;
reg [2*WIDTH-1:0] mult0_result, mult1_result;
always @ (posedge clock or posedge aclr) begin
if (aclr) begin
dataa_reg <= {(WIDTH){1'b0}};
datab_reg <= {(WIDTH){1'b0}};
datac_reg <= {(WIDTH){1'b0}};
datad_reg <= {(WIDTH){1'b0}};
mult0_result <= {(2*WIDTH){1'b0}};
mult1_result <= {(2*WIDTH){1'b0}};
result <= {(2*WIDTH+1){1'b0}};
end
else begin
dataa_reg <= dataa;
datab_reg <= datab;
datac_reg <= datac;
datad_reg <= datad;
mult0_result <= dataa_reg * datab_reg;
mult1_result <= datac_reg * datad_reg;
result <= mult0_result + mult1_result;
end
end
endmodule
|
// Quartus II Verilog Template
// Sum of two multipliers with a wide datapath
module sum_of_two_multipliers_wide_datapath
#(parameter WIDTH_A=36, WIDTH_B=18)
(
input clk, ena,
input [WIDTH_A-1:0] a0, a1,
input [WIDTH_B-1:0] b0, b1,
output reg [WIDTH_A+WIDTH_B:0] dataout
);
always @ (posedge clk)
begin
if (ena == 1)
begin
dataout <= a0 * b0 + a1 * b1;
end
end
endmodule
|
module two_mult_loopback
#(parameter INPUT_WIDTH=18, parameter OUTPUT_WIDTH=36)
(
input clk,
input [INPUT_WIDTH-1:0] dataa, datab, datac,
output [OUTPUT_WIDTH-1:0] dataout
);
mult_loopback mult_loopback_inst (
.clock0 ( clk ),
.dataa_0 ( dataa),
.dataa_1 ( datab),
.datab_1 ( datac),
.result ( dataout)
);
endmodule
|
// Quartus II Verilog Template
// Unsigned Adder
module unsigned_adder
#(parameter WIDTH=16)
(
input [WIDTH-1:0] dataa,
input [WIDTH-1:0] datab,
input cin,
output [WIDTH:0] result
);
assign result = dataa + datab + cin;
endmodule
|
// Quartus II Verilog Template
// Unsigned Adder/Subtractor
module unsigned_adder_subtractor
#(parameter WIDTH=16)
(
input [WIDTH-1:0] dataa,
input [WIDTH-1:0] datab,
input add_sub, // if this is 1, add; else subtract
input clk,
output reg [WIDTH:0] result
);
always @ (posedge clk)
begin
if (add_sub)
result <= dataa + datab;
else
result <= dataa - datab;
end
endmodule
|
// Quartus II Verilog Template
// Unsigned multiply
module unsigned_multiply
#(parameter WIDTH=5)
(
input [WIDTH-1:0] dataa,
input [WIDTH-1:0] datab,
output [2*WIDTH-1:0] dataout
);
assign dataout = dataa * datab;
endmodule
|
// Quartus II Verilog Template
// Unsigned multiply-accumulate
module unsigned_multiply_accumulate
#(parameter WIDTH=8)
(
input clk, aclr, clken, sload,
input [WIDTH-1:0] dataa,
input [WIDTH-1:0] datab,
output reg [2*WIDTH-1:0] adder_out
);
// Declare registers and wires
reg [WIDTH-1:0] dataa_reg, datab_reg;
reg sload_reg;
reg [2*WIDTH-1:0] old_result;
wire [2*WIDTH-1:0] multa;
// Store the results of the operations on the current data
assign multa = dataa_reg * datab_reg;
// Store the value of the accumulation (or clear it)
always @ (adder_out, sload_reg)
begin
if (sload_reg)
old_result <= 0;
else
old_result <= adder_out;
end
// Clear or update data, as appropriate
always @ (posedge clk or posedge aclr)
begin
if (aclr)
begin
dataa_reg <= 0;
datab_reg <= 0;
sload_reg <= 0;
adder_out <= 0;
end
else if (clken)
begin
dataa_reg <= dataa;
datab_reg <= datab;
sload_reg <= sload;
adder_out <= old_result + multa;
end
end
endmodule
|
// Quartus II Verilog Template
// Unsigned multiply with input and output registers
module unsigned_multiply_with_input_and_output_registers
#(parameter WIDTH=8)
(
input clk,
input [WIDTH-1:0] dataa,
input [WIDTH-1:0] datab,
output reg [2*WIDTH-1:0] dataout
);
// Declare input and output registers
reg [WIDTH-1:0] dataa_reg;
reg [WIDTH-1:0] datab_reg;
wire [2*WIDTH-1:0] mult_out;
// Store the result of the multiply
assign mult_out = dataa_reg * datab_reg;
// Update data
always @ (posedge clk)
begin
dataa_reg <= dataa;
datab_reg <= datab;
dataout <= mult_out;
end
endmodule
|
// megafunction wizard: %ALTMULT_ADD%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: ALTMULT_ADD
// ============================================================
// File Name: dsp_shift_megafn.v
// Megafunction Name(s):
// ALTMULT_ADD
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 12.0 Build 178 05/31/2012 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2012 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module dsp_shift_megafn (
clock0,
dataa_0,
datab_0,
rotate,
shift_right,
result);
input clock0;
input [31:0] dataa_0;
input [31:0] datab_0;
input rotate;
input shift_right;
output [31:0] result;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock0;
tri0 [31:0] dataa_0;
tri0 [31:0] datab_0;
tri0 rotate;
tri0 shift_right;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [31:0] sub_wire0;
wire [31:0] result = sub_wire0[31:0];
altmult_add ALTMULT_ADD_component (
.clock0 (clock0),
.datab (datab_0),
.dataa (dataa_0),
.rotate (rotate),
.shift_right (shift_right),
.result (sub_wire0),
.accum_sload (1'b0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.aclr2 (1'b0),
.aclr3 (1'b0),
.addnsub1 (1'b1),
.addnsub1_round (1'b0),
.addnsub3 (1'b1),
.addnsub3_round (1'b0),
.chainin (1'b0),
.chainout_round (1'b0),
.chainout_sat_overflow (),
.chainout_saturate (1'b0),
.clock1 (1'b1),
.clock2 (1'b1),
.clock3 (1'b1),
.coefsel0 ({3{1'b0}}),
.coefsel1 ({3{1'b0}}),
.coefsel2 ({3{1'b0}}),
.coefsel3 ({3{1'b0}}),
.datac ({22{1'b0}}),
.ena0 (1'b1),
.ena1 (1'b1),
.ena2 (1'b1),
.ena3 (1'b1),
.mult01_round (1'b0),
.mult01_saturation (1'b0),
.mult0_is_saturated (),
.mult1_is_saturated (),
.mult23_round (1'b0),
.mult23_saturation (1'b0),
.mult2_is_saturated (),
.mult3_is_saturated (),
.output_round (1'b0),
.output_saturate (1'b0),
.overflow (),
.scanina ({32{1'b0}}),
.scaninb ({32{1'b0}}),
.scanouta (),
.scanoutb (),
.signa (1'b0),
.signb (1'b0),
.sourcea (1'b0),
.sourceb (1'b0),
.zero_chainout (1'b0),
.zero_loopback (1'b0));
defparam
ALTMULT_ADD_component.accumulator = "NO",
ALTMULT_ADD_component.addnsub_multiplier_aclr1 = "UNUSED",
ALTMULT_ADD_component.addnsub_multiplier_pipeline_aclr1 = "UNUSED",
ALTMULT_ADD_component.addnsub_multiplier_pipeline_register1 = "CLOCK0",
ALTMULT_ADD_component.addnsub_multiplier_register1 = "CLOCK0",
ALTMULT_ADD_component.chainout_adder = "NO",
ALTMULT_ADD_component.chainout_register = "UNREGISTERED",
ALTMULT_ADD_component.dedicated_multiplier_circuitry = "YES",
ALTMULT_ADD_component.input_aclr_a0 = "UNUSED",
ALTMULT_ADD_component.input_aclr_b0 = "UNUSED",
ALTMULT_ADD_component.input_register_a0 = "CLOCK0",
ALTMULT_ADD_component.input_register_b0 = "CLOCK0",
ALTMULT_ADD_component.input_source_a0 = "DATAA",
ALTMULT_ADD_component.input_source_b0 = "DATAB",
ALTMULT_ADD_component.intended_device_family = "Stratix IV",
ALTMULT_ADD_component.lpm_type = "altmult_add",
ALTMULT_ADD_component.multiplier1_direction = "ADD",
ALTMULT_ADD_component.multiplier_aclr0 = "UNUSED",
ALTMULT_ADD_component.multiplier_register0 = "CLOCK0",
ALTMULT_ADD_component.number_of_multipliers = 1,
ALTMULT_ADD_component.output_aclr = "UNUSED",
ALTMULT_ADD_component.output_register = "CLOCK0",
ALTMULT_ADD_component.port_addnsub1 = "PORT_UNUSED",
ALTMULT_ADD_component.port_signa = "PORT_UNUSED",
ALTMULT_ADD_component.port_signb = "PORT_UNUSED",
ALTMULT_ADD_component.representation_a = "UNSIGNED",
ALTMULT_ADD_component.representation_b = "UNSIGNED",
ALTMULT_ADD_component.rotate_aclr = "UNUSED",
ALTMULT_ADD_component.rotate_output_aclr = "UNUSED",
ALTMULT_ADD_component.rotate_output_register = "CLOCK0",
ALTMULT_ADD_component.rotate_pipeline_aclr = "UNUSED",
ALTMULT_ADD_component.rotate_pipeline_register = "CLOCK0",
ALTMULT_ADD_component.rotate_register = "CLOCK0",
ALTMULT_ADD_component.shift_mode = "VARIABLE",
ALTMULT_ADD_component.shift_right_aclr = "UNUSED",
ALTMULT_ADD_component.shift_right_output_aclr = "UNUSED",
ALTMULT_ADD_component.shift_right_output_register = "CLOCK0",
ALTMULT_ADD_component.shift_right_pipeline_aclr = "UNUSED",
ALTMULT_ADD_component.shift_right_pipeline_register = "CLOCK0",
ALTMULT_ADD_component.shift_right_register = "CLOCK0",
ALTMULT_ADD_component.signed_aclr_a = "UNUSED",
ALTMULT_ADD_component.signed_aclr_b = "UNUSED",
ALTMULT_ADD_component.signed_pipeline_aclr_a = "UNUSED",
ALTMULT_ADD_component.signed_pipeline_aclr_b = "UNUSED",
ALTMULT_ADD_component.signed_pipeline_register_a = "CLOCK0",
ALTMULT_ADD_component.signed_pipeline_register_b = "CLOCK0",
ALTMULT_ADD_component.signed_register_a = "CLOCK0",
ALTMULT_ADD_component.signed_register_b = "CLOCK0",
ALTMULT_ADD_component.width_a = 32,
ALTMULT_ADD_component.width_b = 32,
ALTMULT_ADD_component.width_chainin = 1,
ALTMULT_ADD_component.width_result = 32,
ALTMULT_ADD_component.zero_chainout_output_aclr = "UNUSED",
ALTMULT_ADD_component.zero_chainout_output_register = "CLOCK0",
ALTMULT_ADD_component.zero_loopback_aclr = "UNUSED",
ALTMULT_ADD_component.zero_loopback_output_aclr = "UNUSED",
ALTMULT_ADD_component.zero_loopback_output_register = "CLOCK0",
ALTMULT_ADD_component.zero_loopback_pipeline_aclr = "UNUSED",
ALTMULT_ADD_component.zero_loopback_pipeline_register = "CLOCK0",
ALTMULT_ADD_component.zero_loopback_register = "CLOCK0";
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ACCUM_DIRECTION STRING "Add"
// Retrieval info: PRIVATE: ACCUM_SLOAD_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ACCUM_SLOAD_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ACCUM_SLOAD_PIPE_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ACCUM_SLOAD_PIPE_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ACCUM_SLOAD_PIPE_REG STRING "1"
// Retrieval info: PRIVATE: ACCUM_SLOAD_REG STRING "1"
// Retrieval info: PRIVATE: ADDNSUB1_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ADDNSUB1_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ADDNSUB1_PIPE_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ADDNSUB1_PIPE_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ADDNSUB1_PIPE_REG STRING "1"
// Retrieval info: PRIVATE: ADDNSUB1_REG STRING "1"
// Retrieval info: PRIVATE: ADDNSUB3_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ADDNSUB3_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ADDNSUB3_PIPE_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ADDNSUB3_PIPE_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ADDNSUB3_PIPE_REG STRING "1"
// Retrieval info: PRIVATE: ADDNSUB3_REG STRING "1"
// Retrieval info: PRIVATE: ADD_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: ALL_REG_ACLR NUMERIC "0"
// Retrieval info: PRIVATE: A_ACLR_SRC_MULT0 NUMERIC "3"
// Retrieval info: PRIVATE: A_CLK_SRC_MULT0 NUMERIC "0"
// Retrieval info: PRIVATE: B_ACLR_SRC_MULT0 NUMERIC "3"
// Retrieval info: PRIVATE: B_CLK_SRC_MULT0 NUMERIC "0"
// Retrieval info: PRIVATE: CHAINOUT_OUTPUT_ACLR NUMERIC "3"
// Retrieval info: PRIVATE: CHAINOUT_OUTPUT_REG STRING "0"
// Retrieval info: PRIVATE: CHAINOUT_OUTPUT_REGISTER NUMERIC "0"
// Retrieval info: PRIVATE: CHAINOUT_OUTPUT_REGISTERED NUMERIC "0"
// Retrieval info: PRIVATE: CHAS_ZERO_CHAINOUT NUMERIC "0"
// Retrieval info: PRIVATE: HAS_ACCUMULATOR NUMERIC "0"
// Retrieval info: PRIVATE: HAS_ACUMM_SLOAD NUMERIC "0"
// Retrieval info: PRIVATE: HAS_CHAININ_PORT NUMERIC "0"
// Retrieval info: PRIVATE: HAS_CHAINOUT_ADDER NUMERIC "0"
// Retrieval info: PRIVATE: HAS_LOOPBACK NUMERIC "0"
// Retrieval info: PRIVATE: HAS_MAC STRING "0"
// Retrieval info: PRIVATE: HAS_SAT_ROUND STRING "0"
// Retrieval info: PRIVATE: HAS_ZERO_LOOPBACK NUMERIC "0"
// Retrieval info: PRIVATE: IMPL_STYLE_DEDICATED NUMERIC "1"
// Retrieval info: PRIVATE: IMPL_STYLE_DEFAULT NUMERIC "0"
// Retrieval info: PRIVATE: IMPL_STYLE_LCELL NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
// Retrieval info: PRIVATE: MULT_REGA0 NUMERIC "1"
// Retrieval info: PRIVATE: MULT_REGB0 NUMERIC "1"
// Retrieval info: PRIVATE: MULT_REGOUT0 NUMERIC "1"
// Retrieval info: PRIVATE: NUM_MULT STRING "1"
// Retrieval info: PRIVATE: OP1 STRING "Add"
// Retrieval info: PRIVATE: OP3 STRING "Add"
// Retrieval info: PRIVATE: OUTPUT_EXTRA_LAT NUMERIC "0"
// Retrieval info: PRIVATE: OUTPUT_REG_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: OUTPUT_REG_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: Q_ACLR_SRC_MULT0 NUMERIC "3"
// Retrieval info: PRIVATE: Q_CLK_SRC_MULT0 NUMERIC "0"
// Retrieval info: PRIVATE: REG_OUT NUMERIC "1"
// Retrieval info: PRIVATE: RNFORMAT STRING "32"
// Retrieval info: PRIVATE: ROTATE_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ROTATE_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ROTATE_OUT_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ROTATE_OUT_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ROTATE_OUT_REG STRING "1"
// Retrieval info: PRIVATE: ROTATE_PIPE_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ROTATE_PIPE_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ROTATE_PIPE_REG STRING "1"
// Retrieval info: PRIVATE: ROTATE_REG STRING "1"
// Retrieval info: PRIVATE: RQFORMAT STRING "Q1.15"
// Retrieval info: PRIVATE: RTS_WIDTH STRING "32"
// Retrieval info: PRIVATE: SAME_CONFIG NUMERIC "1"
// Retrieval info: PRIVATE: SAME_CONTROL_SRC_A0 NUMERIC "1"
// Retrieval info: PRIVATE: SAME_CONTROL_SRC_B0 NUMERIC "1"
// Retrieval info: PRIVATE: SCANOUTA NUMERIC "0"
// Retrieval info: PRIVATE: SCANOUTB NUMERIC "0"
// Retrieval info: PRIVATE: SHIFTOUTA_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: SHIFTOUTA_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: SHIFTOUTA_REG STRING "0"
// Retrieval info: PRIVATE: SHIFT_RIGHT_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: SHIFT_RIGHT_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: SHIFT_RIGHT_OUT_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: SHIFT_RIGHT_OUT_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: SHIFT_RIGHT_OUT_REG STRING "1"
// Retrieval info: PRIVATE: SHIFT_RIGHT_PIPE_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: SHIFT_RIGHT_PIPE_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: SHIFT_RIGHT_PIPE_REG STRING "1"
// Retrieval info: PRIVATE: SHIFT_RIGHT_REG STRING "1"
// Retrieval info: PRIVATE: SHIFT_ROTATE_MODE STRING "Variable"
// Retrieval info: PRIVATE: SIGNA STRING "UNSIGNED"
// Retrieval info: PRIVATE: SIGNA_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: SIGNA_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: SIGNA_PIPE_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: SIGNA_PIPE_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: SIGNA_PIPE_REG STRING "1"
// Retrieval info: PRIVATE: SIGNA_REG STRING "1"
// Retrieval info: PRIVATE: SIGNB STRING "UNSIGNED"
// Retrieval info: PRIVATE: SIGNB_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: SIGNB_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: SIGNB_PIPE_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: SIGNB_PIPE_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: SIGNB_PIPE_REG STRING "1"
// Retrieval info: PRIVATE: SIGNB_REG STRING "1"
// Retrieval info: PRIVATE: SRCA0 STRING "Multiplier input"
// Retrieval info: PRIVATE: SRCB0 STRING "Multiplier input"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: WIDTHA STRING "32"
// Retrieval info: PRIVATE: WIDTHB STRING "32"
// Retrieval info: PRIVATE: ZERO_CHAINOUT_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ZERO_CHAINOUT_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_CHAINOUT_REG STRING "0"
// Retrieval info: PRIVATE: ZERO_LOOPBACK_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ZERO_LOOPBACK_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_LOOPBACK_OUT_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ZERO_LOOPBACK_OUT_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_LOOPBACK_OUT_REG STRING "1"
// Retrieval info: PRIVATE: ZERO_LOOPBACK_PIPE_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ZERO_LOOPBACK_PIPE_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_LOOPBACK_PIPE_REG STRING "1"
// Retrieval info: PRIVATE: ZERO_LOOPBACK_REG STRING "1"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ACCUMULATOR STRING "NO"
// Retrieval info: CONSTANT: ADDNSUB_MULTIPLIER_ACLR1 STRING "UNUSED"
// Retrieval info: CONSTANT: ADDNSUB_MULTIPLIER_PIPELINE_ACLR1 STRING "UNUSED"
// Retrieval info: CONSTANT: ADDNSUB_MULTIPLIER_PIPELINE_REGISTER1 STRING "CLOCK0"
// Retrieval info: CONSTANT: ADDNSUB_MULTIPLIER_REGISTER1 STRING "CLOCK0"
// Retrieval info: CONSTANT: CHAINOUT_ADDER STRING "NO"
// Retrieval info: CONSTANT: CHAINOUT_REGISTER STRING "UNREGISTERED"
// Retrieval info: CONSTANT: DEDICATED_MULTIPLIER_CIRCUITRY STRING "YES"
// Retrieval info: CONSTANT: INPUT_ACLR_A0 STRING "UNUSED"
// Retrieval info: CONSTANT: INPUT_ACLR_B0 STRING "UNUSED"
// Retrieval info: CONSTANT: INPUT_REGISTER_A0 STRING "CLOCK0"
// Retrieval info: CONSTANT: INPUT_REGISTER_B0 STRING "CLOCK0"
// Retrieval info: CONSTANT: INPUT_SOURCE_A0 STRING "DATAA"
// Retrieval info: CONSTANT: INPUT_SOURCE_B0 STRING "DATAB"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altmult_add"
// Retrieval info: CONSTANT: MULTIPLIER1_DIRECTION STRING "ADD"
// Retrieval info: CONSTANT: MULTIPLIER_ACLR0 STRING "UNUSED"
// Retrieval info: CONSTANT: MULTIPLIER_REGISTER0 STRING "CLOCK0"
// Retrieval info: CONSTANT: NUMBER_OF_MULTIPLIERS NUMERIC "1"
// Retrieval info: CONSTANT: OUTPUT_ACLR STRING "UNUSED"
// Retrieval info: CONSTANT: OUTPUT_REGISTER STRING "CLOCK0"
// Retrieval info: CONSTANT: PORT_ADDNSUB1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SIGNA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SIGNB STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: REPRESENTATION_A STRING "UNSIGNED"
// Retrieval info: CONSTANT: REPRESENTATION_B STRING "UNSIGNED"
// Retrieval info: CONSTANT: ROTATE_ACLR STRING "UNUSED"
// Retrieval info: CONSTANT: ROTATE_OUTPUT_ACLR STRING "UNUSED"
// Retrieval info: CONSTANT: ROTATE_OUTPUT_REGISTER STRING "CLOCK0"
// Retrieval info: CONSTANT: ROTATE_PIPELINE_ACLR STRING "UNUSED"
// Retrieval info: CONSTANT: ROTATE_PIPELINE_REGISTER STRING "CLOCK0"
// Retrieval info: CONSTANT: ROTATE_REGISTER STRING "CLOCK0"
// Retrieval info: CONSTANT: SHIFT_MODE STRING "VARIABLE"
// Retrieval info: CONSTANT: SHIFT_RIGHT_ACLR STRING "UNUSED"
// Retrieval info: CONSTANT: SHIFT_RIGHT_OUTPUT_ACLR STRING "UNUSED"
// Retrieval info: CONSTANT: SHIFT_RIGHT_OUTPUT_REGISTER STRING "CLOCK0"
// Retrieval info: CONSTANT: SHIFT_RIGHT_PIPELINE_ACLR STRING "UNUSED"
// Retrieval info: CONSTANT: SHIFT_RIGHT_PIPELINE_REGISTER STRING "CLOCK0"
// Retrieval info: CONSTANT: SHIFT_RIGHT_REGISTER STRING "CLOCK0"
// Retrieval info: CONSTANT: SIGNED_ACLR_A STRING "UNUSED"
// Retrieval info: CONSTANT: SIGNED_ACLR_B STRING "UNUSED"
// Retrieval info: CONSTANT: SIGNED_PIPELINE_ACLR_A STRING "UNUSED"
// Retrieval info: CONSTANT: SIGNED_PIPELINE_ACLR_B STRING "UNUSED"
// Retrieval info: CONSTANT: SIGNED_PIPELINE_REGISTER_A STRING "CLOCK0"
// Retrieval info: CONSTANT: SIGNED_PIPELINE_REGISTER_B STRING "CLOCK0"
// Retrieval info: CONSTANT: SIGNED_REGISTER_A STRING "CLOCK0"
// Retrieval info: CONSTANT: SIGNED_REGISTER_B STRING "CLOCK0"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "32"
// Retrieval info: CONSTANT: WIDTH_B NUMERIC "32"
// Retrieval info: CONSTANT: WIDTH_CHAININ NUMERIC "1"
// Retrieval info: CONSTANT: WIDTH_RESULT NUMERIC "32"
// Retrieval info: CONSTANT: ZERO_CHAINOUT_OUTPUT_ACLR STRING "UNUSED"
// Retrieval info: CONSTANT: ZERO_CHAINOUT_OUTPUT_REGISTER STRING "CLOCK0"
// Retrieval info: CONSTANT: ZERO_LOOPBACK_ACLR STRING "UNUSED"
// Retrieval info: CONSTANT: ZERO_LOOPBACK_OUTPUT_ACLR STRING "UNUSED"
// Retrieval info: CONSTANT: ZERO_LOOPBACK_OUTPUT_REGISTER STRING "CLOCK0"
// Retrieval info: CONSTANT: ZERO_LOOPBACK_PIPELINE_ACLR STRING "UNUSED"
// Retrieval info: CONSTANT: ZERO_LOOPBACK_PIPELINE_REGISTER STRING "CLOCK0"
// Retrieval info: CONSTANT: ZERO_LOOPBACK_REGISTER STRING "CLOCK0"
// Retrieval info: USED_PORT: clock0 0 0 0 0 INPUT VCC "clock0"
// Retrieval info: USED_PORT: dataa_0 0 0 32 0 INPUT GND "dataa_0[31..0]"
// Retrieval info: USED_PORT: datab_0 0 0 32 0 INPUT GND "datab_0[31..0]"
// Retrieval info: USED_PORT: result 0 0 32 0 OUTPUT GND "result[31..0]"
// Retrieval info: USED_PORT: rotate 0 0 0 0 INPUT GND "rotate"
// Retrieval info: USED_PORT: shift_right 0 0 0 0 INPUT GND "shift_right"
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock0 0 0 0 0
// Retrieval info: CONNECT: @dataa 0 0 32 0 dataa_0 0 0 32 0
// Retrieval info: CONNECT: @datab 0 0 32 0 datab_0 0 0 32 0
// Retrieval info: CONNECT: @rotate 0 0 0 0 rotate 0 0 0 0
// Retrieval info: CONNECT: @shift_right 0 0 0 0 shift_right 0 0 0 0
// Retrieval info: CONNECT: result 0 0 32 0 @result 0 0 32 0
// Retrieval info: GEN_FILE: TYPE_NORMAL dsp_shift_megafn.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL dsp_shift_megafn.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL dsp_shift_megafn.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL dsp_shift_megafn.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL dsp_shift_megafn_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL dsp_shift_megafn_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
// megafunction wizard: %ALTMULT_ADD%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: ALTMULT_ADD
// ============================================================
// File Name: dsp_shift_megafn.v
// Megafunction Name(s):
// ALTMULT_ADD
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 12.0 Build 178 05/31/2012 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2012 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module dsp_shift_megafn (
clock0,
dataa_0,
datab_0,
rotate,
shift_right,
result);
input clock0;
input [31:0] dataa_0;
input [31:0] datab_0;
input rotate;
input shift_right;
output [31:0] result;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock0;
tri0 [31:0] dataa_0;
tri0 [31:0] datab_0;
tri0 rotate;
tri0 shift_right;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ACCUM_DIRECTION STRING "Add"
// Retrieval info: PRIVATE: ACCUM_SLOAD_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ACCUM_SLOAD_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ACCUM_SLOAD_PIPE_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ACCUM_SLOAD_PIPE_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ACCUM_SLOAD_PIPE_REG STRING "1"
// Retrieval info: PRIVATE: ACCUM_SLOAD_REG STRING "1"
// Retrieval info: PRIVATE: ADDNSUB1_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ADDNSUB1_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ADDNSUB1_PIPE_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ADDNSUB1_PIPE_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ADDNSUB1_PIPE_REG STRING "1"
// Retrieval info: PRIVATE: ADDNSUB1_REG STRING "1"
// Retrieval info: PRIVATE: ADDNSUB3_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ADDNSUB3_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ADDNSUB3_PIPE_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ADDNSUB3_PIPE_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ADDNSUB3_PIPE_REG STRING "1"
// Retrieval info: PRIVATE: ADDNSUB3_REG STRING "1"
// Retrieval info: PRIVATE: ADD_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: ALL_REG_ACLR NUMERIC "0"
// Retrieval info: PRIVATE: A_ACLR_SRC_MULT0 NUMERIC "3"
// Retrieval info: PRIVATE: A_CLK_SRC_MULT0 NUMERIC "0"
// Retrieval info: PRIVATE: B_ACLR_SRC_MULT0 NUMERIC "3"
// Retrieval info: PRIVATE: B_CLK_SRC_MULT0 NUMERIC "0"
// Retrieval info: PRIVATE: CHAINOUT_OUTPUT_ACLR NUMERIC "3"
// Retrieval info: PRIVATE: CHAINOUT_OUTPUT_REG STRING "0"
// Retrieval info: PRIVATE: CHAINOUT_OUTPUT_REGISTER NUMERIC "0"
// Retrieval info: PRIVATE: CHAINOUT_OUTPUT_REGISTERED NUMERIC "0"
// Retrieval info: PRIVATE: CHAS_ZERO_CHAINOUT NUMERIC "0"
// Retrieval info: PRIVATE: HAS_ACCUMULATOR NUMERIC "0"
// Retrieval info: PRIVATE: HAS_ACUMM_SLOAD NUMERIC "0"
// Retrieval info: PRIVATE: HAS_CHAININ_PORT NUMERIC "0"
// Retrieval info: PRIVATE: HAS_CHAINOUT_ADDER NUMERIC "0"
// Retrieval info: PRIVATE: HAS_LOOPBACK NUMERIC "0"
// Retrieval info: PRIVATE: HAS_MAC STRING "0"
// Retrieval info: PRIVATE: HAS_SAT_ROUND STRING "0"
// Retrieval info: PRIVATE: HAS_ZERO_LOOPBACK NUMERIC "0"
// Retrieval info: PRIVATE: IMPL_STYLE_DEDICATED NUMERIC "1"
// Retrieval info: PRIVATE: IMPL_STYLE_DEFAULT NUMERIC "0"
// Retrieval info: PRIVATE: IMPL_STYLE_LCELL NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
// Retrieval info: PRIVATE: MULT_REGA0 NUMERIC "1"
// Retrieval info: PRIVATE: MULT_REGB0 NUMERIC "1"
// Retrieval info: PRIVATE: MULT_REGOUT0 NUMERIC "1"
// Retrieval info: PRIVATE: NUM_MULT STRING "1"
// Retrieval info: PRIVATE: OP1 STRING "Add"
// Retrieval info: PRIVATE: OP3 STRING "Add"
// Retrieval info: PRIVATE: OUTPUT_EXTRA_LAT NUMERIC "0"
// Retrieval info: PRIVATE: OUTPUT_REG_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: OUTPUT_REG_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: Q_ACLR_SRC_MULT0 NUMERIC "3"
// Retrieval info: PRIVATE: Q_CLK_SRC_MULT0 NUMERIC "0"
// Retrieval info: PRIVATE: REG_OUT NUMERIC "1"
// Retrieval info: PRIVATE: RNFORMAT STRING "32"
// Retrieval info: PRIVATE: ROTATE_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ROTATE_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ROTATE_OUT_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ROTATE_OUT_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ROTATE_OUT_REG STRING "1"
// Retrieval info: PRIVATE: ROTATE_PIPE_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ROTATE_PIPE_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ROTATE_PIPE_REG STRING "1"
// Retrieval info: PRIVATE: ROTATE_REG STRING "1"
// Retrieval info: PRIVATE: RQFORMAT STRING "Q1.15"
// Retrieval info: PRIVATE: RTS_WIDTH STRING "32"
// Retrieval info: PRIVATE: SAME_CONFIG NUMERIC "1"
// Retrieval info: PRIVATE: SAME_CONTROL_SRC_A0 NUMERIC "1"
// Retrieval info: PRIVATE: SAME_CONTROL_SRC_B0 NUMERIC "1"
// Retrieval info: PRIVATE: SCANOUTA NUMERIC "0"
// Retrieval info: PRIVATE: SCANOUTB NUMERIC "0"
// Retrieval info: PRIVATE: SHIFTOUTA_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: SHIFTOUTA_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: SHIFTOUTA_REG STRING "0"
// Retrieval info: PRIVATE: SHIFT_RIGHT_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: SHIFT_RIGHT_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: SHIFT_RIGHT_OUT_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: SHIFT_RIGHT_OUT_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: SHIFT_RIGHT_OUT_REG STRING "1"
// Retrieval info: PRIVATE: SHIFT_RIGHT_PIPE_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: SHIFT_RIGHT_PIPE_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: SHIFT_RIGHT_PIPE_REG STRING "1"
// Retrieval info: PRIVATE: SHIFT_RIGHT_REG STRING "1"
// Retrieval info: PRIVATE: SHIFT_ROTATE_MODE STRING "Variable"
// Retrieval info: PRIVATE: SIGNA STRING "UNSIGNED"
// Retrieval info: PRIVATE: SIGNA_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: SIGNA_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: SIGNA_PIPE_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: SIGNA_PIPE_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: SIGNA_PIPE_REG STRING "1"
// Retrieval info: PRIVATE: SIGNA_REG STRING "1"
// Retrieval info: PRIVATE: SIGNB STRING "UNSIGNED"
// Retrieval info: PRIVATE: SIGNB_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: SIGNB_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: SIGNB_PIPE_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: SIGNB_PIPE_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: SIGNB_PIPE_REG STRING "1"
// Retrieval info: PRIVATE: SIGNB_REG STRING "1"
// Retrieval info: PRIVATE: SRCA0 STRING "Multiplier input"
// Retrieval info: PRIVATE: SRCB0 STRING "Multiplier input"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: WIDTHA STRING "32"
// Retrieval info: PRIVATE: WIDTHB STRING "32"
// Retrieval info: PRIVATE: ZERO_CHAINOUT_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ZERO_CHAINOUT_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_CHAINOUT_REG STRING "0"
// Retrieval info: PRIVATE: ZERO_LOOPBACK_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ZERO_LOOPBACK_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_LOOPBACK_OUT_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ZERO_LOOPBACK_OUT_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_LOOPBACK_OUT_REG STRING "1"
// Retrieval info: PRIVATE: ZERO_LOOPBACK_PIPE_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ZERO_LOOPBACK_PIPE_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_LOOPBACK_PIPE_REG STRING "1"
// Retrieval info: PRIVATE: ZERO_LOOPBACK_REG STRING "1"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ACCUMULATOR STRING "NO"
// Retrieval info: CONSTANT: ADDNSUB_MULTIPLIER_ACLR1 STRING "UNUSED"
// Retrieval info: CONSTANT: ADDNSUB_MULTIPLIER_PIPELINE_ACLR1 STRING "UNUSED"
// Retrieval info: CONSTANT: ADDNSUB_MULTIPLIER_PIPELINE_REGISTER1 STRING "CLOCK0"
// Retrieval info: CONSTANT: ADDNSUB_MULTIPLIER_REGISTER1 STRING "CLOCK0"
// Retrieval info: CONSTANT: CHAINOUT_ADDER STRING "NO"
// Retrieval info: CONSTANT: CHAINOUT_REGISTER STRING "UNREGISTERED"
// Retrieval info: CONSTANT: DEDICATED_MULTIPLIER_CIRCUITRY STRING "YES"
// Retrieval info: CONSTANT: INPUT_ACLR_A0 STRING "UNUSED"
// Retrieval info: CONSTANT: INPUT_ACLR_B0 STRING "UNUSED"
// Retrieval info: CONSTANT: INPUT_REGISTER_A0 STRING "CLOCK0"
// Retrieval info: CONSTANT: INPUT_REGISTER_B0 STRING "CLOCK0"
// Retrieval info: CONSTANT: INPUT_SOURCE_A0 STRING "DATAA"
// Retrieval info: CONSTANT: INPUT_SOURCE_B0 STRING "DATAB"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altmult_add"
// Retrieval info: CONSTANT: MULTIPLIER1_DIRECTION STRING "ADD"
// Retrieval info: CONSTANT: MULTIPLIER_ACLR0 STRING "UNUSED"
// Retrieval info: CONSTANT: MULTIPLIER_REGISTER0 STRING "CLOCK0"
// Retrieval info: CONSTANT: NUMBER_OF_MULTIPLIERS NUMERIC "1"
// Retrieval info: CONSTANT: OUTPUT_ACLR STRING "UNUSED"
// Retrieval info: CONSTANT: OUTPUT_REGISTER STRING "CLOCK0"
// Retrieval info: CONSTANT: PORT_ADDNSUB1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SIGNA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SIGNB STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: REPRESENTATION_A STRING "UNSIGNED"
// Retrieval info: CONSTANT: REPRESENTATION_B STRING "UNSIGNED"
// Retrieval info: CONSTANT: ROTATE_ACLR STRING "UNUSED"
// Retrieval info: CONSTANT: ROTATE_OUTPUT_ACLR STRING "UNUSED"
// Retrieval info: CONSTANT: ROTATE_OUTPUT_REGISTER STRING "CLOCK0"
// Retrieval info: CONSTANT: ROTATE_PIPELINE_ACLR STRING "UNUSED"
// Retrieval info: CONSTANT: ROTATE_PIPELINE_REGISTER STRING "CLOCK0"
// Retrieval info: CONSTANT: ROTATE_REGISTER STRING "CLOCK0"
// Retrieval info: CONSTANT: SHIFT_MODE STRING "VARIABLE"
// Retrieval info: CONSTANT: SHIFT_RIGHT_ACLR STRING "UNUSED"
// Retrieval info: CONSTANT: SHIFT_RIGHT_OUTPUT_ACLR STRING "UNUSED"
// Retrieval info: CONSTANT: SHIFT_RIGHT_OUTPUT_REGISTER STRING "CLOCK0"
// Retrieval info: CONSTANT: SHIFT_RIGHT_PIPELINE_ACLR STRING "UNUSED"
// Retrieval info: CONSTANT: SHIFT_RIGHT_PIPELINE_REGISTER STRING "CLOCK0"
// Retrieval info: CONSTANT: SHIFT_RIGHT_REGISTER STRING "CLOCK0"
// Retrieval info: CONSTANT: SIGNED_ACLR_A STRING "UNUSED"
// Retrieval info: CONSTANT: SIGNED_ACLR_B STRING "UNUSED"
// Retrieval info: CONSTANT: SIGNED_PIPELINE_ACLR_A STRING "UNUSED"
// Retrieval info: CONSTANT: SIGNED_PIPELINE_ACLR_B STRING "UNUSED"
// Retrieval info: CONSTANT: SIGNED_PIPELINE_REGISTER_A STRING "CLOCK0"
// Retrieval info: CONSTANT: SIGNED_PIPELINE_REGISTER_B STRING "CLOCK0"
// Retrieval info: CONSTANT: SIGNED_REGISTER_A STRING "CLOCK0"
// Retrieval info: CONSTANT: SIGNED_REGISTER_B STRING "CLOCK0"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "32"
// Retrieval info: CONSTANT: WIDTH_B NUMERIC "32"
// Retrieval info: CONSTANT: WIDTH_CHAININ NUMERIC "1"
// Retrieval info: CONSTANT: WIDTH_RESULT NUMERIC "32"
// Retrieval info: CONSTANT: ZERO_CHAINOUT_OUTPUT_ACLR STRING "UNUSED"
// Retrieval info: CONSTANT: ZERO_CHAINOUT_OUTPUT_REGISTER STRING "CLOCK0"
// Retrieval info: CONSTANT: ZERO_LOOPBACK_ACLR STRING "UNUSED"
// Retrieval info: CONSTANT: ZERO_LOOPBACK_OUTPUT_ACLR STRING "UNUSED"
// Retrieval info: CONSTANT: ZERO_LOOPBACK_OUTPUT_REGISTER STRING "CLOCK0"
// Retrieval info: CONSTANT: ZERO_LOOPBACK_PIPELINE_ACLR STRING "UNUSED"
// Retrieval info: CONSTANT: ZERO_LOOPBACK_PIPELINE_REGISTER STRING "CLOCK0"
// Retrieval info: CONSTANT: ZERO_LOOPBACK_REGISTER STRING "CLOCK0"
// Retrieval info: USED_PORT: clock0 0 0 0 0 INPUT VCC "clock0"
// Retrieval info: USED_PORT: dataa_0 0 0 32 0 INPUT GND "dataa_0[31..0]"
// Retrieval info: USED_PORT: datab_0 0 0 32 0 INPUT GND "datab_0[31..0]"
// Retrieval info: USED_PORT: result 0 0 32 0 OUTPUT GND "result[31..0]"
// Retrieval info: USED_PORT: rotate 0 0 0 0 INPUT GND "rotate"
// Retrieval info: USED_PORT: shift_right 0 0 0 0 INPUT GND "shift_right"
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock0 0 0 0 0
// Retrieval info: CONNECT: @dataa 0 0 32 0 dataa_0 0 0 32 0
// Retrieval info: CONNECT: @datab 0 0 32 0 datab_0 0 0 32 0
// Retrieval info: CONNECT: @rotate 0 0 0 0 rotate 0 0 0 0
// Retrieval info: CONNECT: @shift_right 0 0 0 0 shift_right 0 0 0 0
// Retrieval info: CONNECT: result 0 0 32 0 @result 0 0 32 0
// Retrieval info: GEN_FILE: TYPE_NORMAL dsp_shift_megafn.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL dsp_shift_megafn.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL dsp_shift_megafn.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL dsp_shift_megafn.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL dsp_shift_megafn_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL dsp_shift_megafn_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
dsp_shift_megafn dsp_shift_megafn_inst (
.clock0 ( clock0_sig ),
.dataa_0 ( dataa_0_sig ),
.datab_0 ( datab_0_sig ),
.rotate ( rotate_sig ),
.shift_right ( shift_right_sig ),
.result ( result_sig )
);
|
// megafunction wizard: %ALTMULT_ACCUM (MAC)%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altmult_add
// ============================================================
// File Name: mult_accum_chain.v
// Megafunction Name(s):
// altmult_add
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 12.0 Build 178 05/31/2012 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2012 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module mult_accum_chain (
chainin,
clock0,
dataa_0,
dataa_1,
dataa_2,
dataa_3,
datab_0,
datab_1,
datab_2,
datab_3,
result);
input [43:0] chainin;
input clock0;
input [17:0] dataa_0;
input [17:0] dataa_1;
input [17:0] dataa_2;
input [17:0] dataa_3;
input [17:0] datab_0;
input [17:0] datab_1;
input [17:0] datab_2;
input [17:0] datab_3;
output [43:0] result;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 [43:0] chainin;
tri1 clock0;
tri0 [17:0] dataa_0;
tri0 [17:0] dataa_1;
tri0 [17:0] dataa_2;
tri0 [17:0] dataa_3;
tri0 [17:0] datab_0;
tri0 [17:0] datab_1;
tri0 [17:0] datab_2;
tri0 [17:0] datab_3;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [43:0] sub_wire0;
wire [17:0] sub_wire10 = dataa_3[17:0];
wire [17:0] sub_wire9 = dataa_2[17:0];
wire [17:0] sub_wire8 = dataa_1[17:0];
wire [17:0] sub_wire5 = datab_3[17:0];
wire [17:0] sub_wire4 = datab_2[17:0];
wire [17:0] sub_wire3 = datab_1[17:0];
wire [43:0] result = sub_wire0[43:0];
wire [17:0] sub_wire1 = datab_0[17:0];
wire [71:0] sub_wire2 = {sub_wire5, sub_wire4, sub_wire3, sub_wire1};
wire [17:0] sub_wire6 = dataa_0[17:0];
wire [71:0] sub_wire7 = {sub_wire10, sub_wire9, sub_wire8, sub_wire6};
altmult_add altmult_add_component (
.chainin (chainin),
.clock0 (clock0),
.datab (sub_wire2),
.dataa (sub_wire7),
.result (sub_wire0),
.accum_sload (1'b0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.aclr2 (1'b0),
.aclr3 (1'b0),
.addnsub1 (1'b1),
.addnsub1_round (1'b0),
.addnsub3 (1'b1),
.addnsub3_round (1'b0),
.chainout_round (1'b0),
.chainout_sat_overflow (),
.chainout_saturate (1'b0),
.clock1 (1'b1),
.clock2 (1'b1),
.clock3 (1'b1),
.coefsel0 ({3{1'b0}}),
.coefsel1 ({3{1'b0}}),
.coefsel2 ({3{1'b0}}),
.coefsel3 ({3{1'b0}}),
.datac ({88{1'b0}}),
.ena0 (1'b1),
.ena1 (1'b1),
.ena2 (1'b1),
.ena3 (1'b1),
.mult01_round (1'b0),
.mult01_saturation (1'b0),
.mult0_is_saturated (),
.mult1_is_saturated (),
.mult23_round (1'b0),
.mult23_saturation (1'b0),
.mult2_is_saturated (),
.mult3_is_saturated (),
.output_round (1'b0),
.output_saturate (1'b0),
.overflow (),
.rotate (1'b0),
.scanina ({18{1'b0}}),
.scaninb ({18{1'b0}}),
.scanouta (),
.scanoutb (),
.shift_right (1'b0),
.signa (1'b0),
.signb (1'b0),
.sourcea ({4{1'b0}}),
.sourceb ({4{1'b0}}),
.zero_chainout (1'b0),
.zero_loopback (1'b0));
defparam
altmult_add_component.accumulator = "YES",
altmult_add_component.accum_direction = "ADD",
altmult_add_component.addnsub_multiplier_aclr1 = "UNUSED",
altmult_add_component.addnsub_multiplier_aclr3 = "UNUSED",
altmult_add_component.addnsub_multiplier_pipeline_aclr1 = "UNUSED",
altmult_add_component.addnsub_multiplier_pipeline_aclr3 = "UNUSED",
altmult_add_component.addnsub_multiplier_pipeline_register1 = "CLOCK0",
altmult_add_component.addnsub_multiplier_pipeline_register3 = "CLOCK0",
altmult_add_component.addnsub_multiplier_register1 = "CLOCK0",
altmult_add_component.addnsub_multiplier_register3 = "CLOCK0",
altmult_add_component.chainout_aclr = "UNUSED",
altmult_add_component.chainout_adder = "YES",
altmult_add_component.chainout_register = "CLOCK0",
altmult_add_component.dedicated_multiplier_circuitry = "YES",
altmult_add_component.input_aclr_a0 = "UNUSED",
altmult_add_component.input_aclr_a1 = "UNUSED",
altmult_add_component.input_aclr_a2 = "UNUSED",
altmult_add_component.input_aclr_a3 = "UNUSED",
altmult_add_component.input_aclr_b0 = "UNUSED",
altmult_add_component.input_aclr_b1 = "UNUSED",
altmult_add_component.input_aclr_b2 = "UNUSED",
altmult_add_component.input_aclr_b3 = "UNUSED",
altmult_add_component.input_register_a0 = "CLOCK0",
altmult_add_component.input_register_a1 = "CLOCK0",
altmult_add_component.input_register_a2 = "CLOCK0",
altmult_add_component.input_register_a3 = "CLOCK0",
altmult_add_component.input_register_b0 = "CLOCK0",
altmult_add_component.input_register_b1 = "CLOCK0",
altmult_add_component.input_register_b2 = "CLOCK0",
altmult_add_component.input_register_b3 = "CLOCK0",
altmult_add_component.input_source_a0 = "DATAA",
altmult_add_component.input_source_a1 = "DATAA",
altmult_add_component.input_source_a2 = "DATAA",
altmult_add_component.input_source_a3 = "DATAA",
altmult_add_component.input_source_b0 = "DATAB",
altmult_add_component.input_source_b1 = "DATAB",
altmult_add_component.input_source_b2 = "DATAB",
altmult_add_component.input_source_b3 = "DATAB",
altmult_add_component.intended_device_family = "Stratix IV",
altmult_add_component.lpm_type = "altmult_add",
altmult_add_component.multiplier1_direction = "ADD",
altmult_add_component.multiplier3_direction = "ADD",
altmult_add_component.multiplier_aclr0 = "UNUSED",
altmult_add_component.multiplier_aclr1 = "UNUSED",
altmult_add_component.multiplier_aclr2 = "UNUSED",
altmult_add_component.multiplier_aclr3 = "UNUSED",
altmult_add_component.multiplier_register0 = "CLOCK0",
altmult_add_component.multiplier_register1 = "CLOCK0",
altmult_add_component.multiplier_register2 = "CLOCK0",
altmult_add_component.multiplier_register3 = "CLOCK0",
altmult_add_component.number_of_multipliers = 4,
altmult_add_component.output_aclr = "UNUSED",
altmult_add_component.output_register = "CLOCK0",
altmult_add_component.port_addnsub1 = "PORT_UNUSED",
altmult_add_component.port_addnsub3 = "PORT_UNUSED",
altmult_add_component.port_signa = "PORT_UNUSED",
altmult_add_component.port_signb = "PORT_UNUSED",
altmult_add_component.representation_a = "SIGNED",
altmult_add_component.representation_b = "SIGNED",
altmult_add_component.signed_aclr_a = "UNUSED",
altmult_add_component.signed_aclr_b = "UNUSED",
altmult_add_component.signed_pipeline_aclr_a = "UNUSED",
altmult_add_component.signed_pipeline_aclr_b = "UNUSED",
altmult_add_component.signed_pipeline_register_a = "CLOCK0",
altmult_add_component.signed_pipeline_register_b = "CLOCK0",
altmult_add_component.signed_register_a = "CLOCK0",
altmult_add_component.signed_register_b = "CLOCK0",
altmult_add_component.width_a = 18,
altmult_add_component.width_b = 18,
altmult_add_component.width_chainin = 44,
altmult_add_component.width_result = 44,
altmult_add_component.zero_chainout_output_aclr = "UNUSED",
altmult_add_component.zero_chainout_output_register = "CLOCK0",
altmult_add_component.zero_loopback_aclr = "UNUSED",
altmult_add_component.zero_loopback_output_aclr = "UNUSED",
altmult_add_component.zero_loopback_output_register = "CLOCK0",
altmult_add_component.zero_loopback_pipeline_aclr = "UNUSED",
altmult_add_component.zero_loopback_pipeline_register = "CLOCK0",
altmult_add_component.zero_loopback_register = "CLOCK0";
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ACCUM_DIRECTION STRING "Add"
// Retrieval info: PRIVATE: ACCUM_SLOAD NUMERIC "0"
// Retrieval info: PRIVATE: ACCUM_SLOAD_ACLR NUMERIC "3"
// Retrieval info: PRIVATE: ACCUM_SLOAD_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ACCUM_SLOAD_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ACCUM_SLOAD_PIPELINE_ACLR NUMERIC "3"
// Retrieval info: PRIVATE: ACCUM_SLOAD_PIPELINE_REG NUMERIC "1"
// Retrieval info: PRIVATE: ACCUM_SLOAD_PIPELINE_REG_INDEX NUMERIC "0"
// Retrieval info: PRIVATE: ACCUM_SLOAD_PIPE_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ACCUM_SLOAD_PIPE_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ACCUM_SLOAD_PIPE_REG STRING "1"
// Retrieval info: PRIVATE: ACCUM_SLOAD_REG NUMERIC "1"
// Retrieval info: PRIVATE: ACCUM_SLOAD_REG_INDEX NUMERIC "0"
// Retrieval info: PRIVATE: ACCUM_SLOAD_UPPER_DATA NUMERIC "0"
// Retrieval info: PRIVATE: ACCUM_SLOAD_UPPER_DATA_ACLR NUMERIC "3"
// Retrieval info: PRIVATE: ACCUM_SLOAD_UPPER_DATA_PIPELINE_ACLR NUMERIC "3"
// Retrieval info: PRIVATE: ACCUM_SLOAD_UPPER_DATA_PIPELINE_REG NUMERIC "0"
// Retrieval info: PRIVATE: ACCUM_SLOAD_UPPER_DATA_REG NUMERIC "0"
// Retrieval info: PRIVATE: ADDNSUB1_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ADDNSUB1_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ADDNSUB1_PIPE_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ADDNSUB1_PIPE_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ADDNSUB1_PIPE_REG STRING "1"
// Retrieval info: PRIVATE: ADDNSUB1_REG STRING "1"
// Retrieval info: PRIVATE: ADDNSUB3_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ADDNSUB3_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ADDNSUB3_PIPE_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ADDNSUB3_PIPE_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ADDNSUB3_PIPE_REG STRING "1"
// Retrieval info: PRIVATE: ADDNSUB3_REG STRING "1"
// Retrieval info: PRIVATE: ADD_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: ALL_REG_ACLR NUMERIC "0"
// Retrieval info: PRIVATE: A_ACLR_SRC_MULT0 NUMERIC "3"
// Retrieval info: PRIVATE: A_CLK_SRC_MULT0 NUMERIC "0"
// Retrieval info: PRIVATE: B_ACLR_SRC_MULT0 NUMERIC "3"
// Retrieval info: PRIVATE: B_CLK_SRC_MULT0 NUMERIC "0"
// Retrieval info: PRIVATE: CHAINOUT_OUTPUT_ACLR NUMERIC "3"
// Retrieval info: PRIVATE: CHAINOUT_OUTPUT_REG STRING "1"
// Retrieval info: PRIVATE: CHAINOUT_OUTPUT_REGISTER NUMERIC "0"
// Retrieval info: PRIVATE: CHAINOUT_OUTPUT_REGISTERED NUMERIC "1"
// Retrieval info: PRIVATE: CHAS_ZERO_CHAINOUT NUMERIC "0"
// Retrieval info: PRIVATE: EXTRA_MULTIPLIER_LATENCY NUMERIC "0"
// Retrieval info: PRIVATE: HAS_ACCUMULATOR NUMERIC "1"
// Retrieval info: PRIVATE: HAS_ACUMM_SLOAD NUMERIC "0"
// Retrieval info: PRIVATE: HAS_CHAININ_PORT NUMERIC "1"
// Retrieval info: PRIVATE: HAS_CHAINOUT_ADDER NUMERIC "1"
// Retrieval info: PRIVATE: HAS_LOOPBACK NUMERIC "0"
// Retrieval info: PRIVATE: HAS_MAC STRING "1"
// Retrieval info: PRIVATE: HAS_SAT_ROUND STRING "0"
// Retrieval info: PRIVATE: HAS_ZERO_LOOPBACK NUMERIC "0"
// Retrieval info: PRIVATE: IMPL_STYLE_DEDICATED NUMERIC "1"
// Retrieval info: PRIVATE: IMPL_STYLE_DEFAULT NUMERIC "0"
// Retrieval info: PRIVATE: IMPL_STYLE_LCELL NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
// Retrieval info: PRIVATE: MULT_LATENCY NUMERIC "0"
// Retrieval info: PRIVATE: MULT_REGA0 NUMERIC "1"
// Retrieval info: PRIVATE: MULT_REGB0 NUMERIC "1"
// Retrieval info: PRIVATE: MULT_REGOUT0 NUMERIC "1"
// Retrieval info: PRIVATE: NUM_MULT STRING "4"
// Retrieval info: PRIVATE: OP1 STRING "Add"
// Retrieval info: PRIVATE: OP3 STRING "Add"
// Retrieval info: PRIVATE: OUTPUT_EXTRA_LAT NUMERIC "0"
// Retrieval info: PRIVATE: OUTPUT_REG_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: OUTPUT_REG_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW NUMERIC "0"
// Retrieval info: PRIVATE: Q_ACLR_SRC_MULT0 NUMERIC "3"
// Retrieval info: PRIVATE: Q_CLK_SRC_MULT0 NUMERIC "0"
// Retrieval info: PRIVATE: REG_OUT NUMERIC "1"
// Retrieval info: PRIVATE: RNFORMAT STRING "44"
// Retrieval info: PRIVATE: ROTATE_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ROTATE_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ROTATE_OUT_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ROTATE_OUT_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ROTATE_OUT_REG STRING "1"
// Retrieval info: PRIVATE: ROTATE_PIPE_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ROTATE_PIPE_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ROTATE_PIPE_REG STRING "1"
// Retrieval info: PRIVATE: ROTATE_REG STRING "1"
// Retrieval info: PRIVATE: ROUND3_CHAINOUT_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ROUND3_CHAINOUT_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ROUND3_CHAINOUT_MODE STRING "Enabled"
// Retrieval info: PRIVATE: ROUND3_CHAINOUT_OUT_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ROUND3_CHAINOUT_OUT_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ROUND3_CHAINOUT_OUT_REG STRING "1"
// Retrieval info: PRIVATE: ROUND3_CHAINOUT_PIPE_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ROUND3_CHAINOUT_PIPE_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ROUND3_CHAINOUT_PIPE_REG STRING "1"
// Retrieval info: PRIVATE: ROUND3_CHAINOUT_REG STRING "1"
// Retrieval info: PRIVATE: ROUND3_FRAC_WIDTH NUMERIC "23"
// Retrieval info: PRIVATE: ROUND3_OUTPUT_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ROUND3_OUTPUT_CHAINOUT_TYPE STRING "Nearest Integer"
// Retrieval info: PRIVATE: ROUND3_OUTPUT_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ROUND3_OUTPUT_MODE STRING "Disabled"
// Retrieval info: PRIVATE: ROUND3_OUTPUT_PIPE_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ROUND3_OUTPUT_PIPE_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ROUND3_OUTPUT_PIPE_REG STRING "1"
// Retrieval info: PRIVATE: ROUND3_OUTPUT_REG STRING "1"
// Retrieval info: PRIVATE: RQFORMAT STRING "Q1.30"
// Retrieval info: PRIVATE: RTS_WIDTH STRING "44"
// Retrieval info: PRIVATE: SAME_CONFIG NUMERIC "1"
// Retrieval info: PRIVATE: SAME_CONTROL_SRC_A0 NUMERIC "1"
// Retrieval info: PRIVATE: SAME_CONTROL_SRC_B0 NUMERIC "1"
// Retrieval info: PRIVATE: SAT3_CHAINOUT_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: SAT3_CHAINOUT_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: SAT3_CHAINOUT_MODE STRING "Enabled"
// Retrieval info: PRIVATE: SAT3_CHAINOUT_OUT_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: SAT3_CHAINOUT_OUT_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: SAT3_CHAINOUT_OVERFLOW NUMERIC "1"
// Retrieval info: PRIVATE: SAT3_CHAINOUT_PIPE_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: SAT3_CHAINOUT_PIPE_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: SAT3_CHAINOUT_PIPE_REG STRING "1"
// Retrieval info: PRIVATE: SAT3_CHAINOUT_REG STRING "1"
// Retrieval info: PRIVATE: SAT3_FRAC_WIDTH NUMERIC "1"
// Retrieval info: PRIVATE: SAT3_OUTPUT_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: SAT3_OUTPUT_CHAINOUT_TYPE STRING "Asymmetric"
// Retrieval info: PRIVATE: SAT3_OUTPUT_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: SAT3_OUTPUT_MODE STRING "Enabled"
// Retrieval info: PRIVATE: SAT3_OUTPUT_OVERFLOW NUMERIC "1"
// Retrieval info: PRIVATE: SAT3_OUTPUT_PIPE_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: SAT3_OUTPUT_PIPE_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: SAT3_OUTPUT_PIPE_REG STRING "1"
// Retrieval info: PRIVATE: SAT3_OUTPUT_REG STRING "1"
// Retrieval info: PRIVATE: SCANOUTA NUMERIC "0"
// Retrieval info: PRIVATE: SCANOUTB NUMERIC "0"
// Retrieval info: PRIVATE: SHIFTOUTA_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: SHIFTOUTA_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: SHIFTOUTA_REG STRING "0"
// Retrieval info: PRIVATE: SHIFT_RIGHT_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: SHIFT_RIGHT_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: SHIFT_RIGHT_OUT_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: SHIFT_RIGHT_OUT_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: SHIFT_RIGHT_OUT_REG STRING "1"
// Retrieval info: PRIVATE: SHIFT_RIGHT_PIPE_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: SHIFT_RIGHT_PIPE_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: SHIFT_RIGHT_PIPE_REG STRING "1"
// Retrieval info: PRIVATE: SHIFT_RIGHT_REG STRING "1"
// Retrieval info: PRIVATE: SHIFT_ROTATE_MODE STRING "None"
// Retrieval info: PRIVATE: SIGNA STRING "SIGNED"
// Retrieval info: PRIVATE: SIGNA_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: SIGNA_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: SIGNA_PIPE_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: SIGNA_PIPE_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: SIGNA_PIPE_REG STRING "1"
// Retrieval info: PRIVATE: SIGNA_REG STRING "1"
// Retrieval info: PRIVATE: SIGNB STRING "SIGNED"
// Retrieval info: PRIVATE: SIGNB_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: SIGNB_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: SIGNB_PIPE_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: SIGNB_PIPE_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: SIGNB_PIPE_REG STRING "1"
// Retrieval info: PRIVATE: SIGNB_REG STRING "1"
// Retrieval info: PRIVATE: SRCA0 STRING "Multiplier input"
// Retrieval info: PRIVATE: SRCB0 STRING "Multiplier input"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: WIDTHA STRING "18"
// Retrieval info: PRIVATE: WIDTHB STRING "18"
// Retrieval info: PRIVATE: WIDTH_UPPER_DATA NUMERIC "1"
// Retrieval info: PRIVATE: ZERO_CHAINOUT_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ZERO_CHAINOUT_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_CHAINOUT_REG STRING "0"
// Retrieval info: PRIVATE: ZERO_LOOPBACK_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ZERO_LOOPBACK_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_LOOPBACK_OUT_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ZERO_LOOPBACK_OUT_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_LOOPBACK_OUT_REG STRING "1"
// Retrieval info: PRIVATE: ZERO_LOOPBACK_PIPE_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ZERO_LOOPBACK_PIPE_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_LOOPBACK_PIPE_REG STRING "1"
// Retrieval info: PRIVATE: ZERO_LOOPBACK_REG STRING "1"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ACCUMULATOR STRING "YES"
// Retrieval info: CONSTANT: ACCUM_DIRECTION STRING "ADD"
// Retrieval info: CONSTANT: ADDNSUB_MULTIPLIER_ACLR1 STRING "UNUSED"
// Retrieval info: CONSTANT: ADDNSUB_MULTIPLIER_ACLR3 STRING "UNUSED"
// Retrieval info: CONSTANT: ADDNSUB_MULTIPLIER_PIPELINE_ACLR1 STRING "UNUSED"
// Retrieval info: CONSTANT: ADDNSUB_MULTIPLIER_PIPELINE_ACLR3 STRING "UNUSED"
// Retrieval info: CONSTANT: ADDNSUB_MULTIPLIER_PIPELINE_REGISTER1 STRING "CLOCK0"
// Retrieval info: CONSTANT: ADDNSUB_MULTIPLIER_PIPELINE_REGISTER3 STRING "CLOCK0"
// Retrieval info: CONSTANT: ADDNSUB_MULTIPLIER_REGISTER1 STRING "CLOCK0"
// Retrieval info: CONSTANT: ADDNSUB_MULTIPLIER_REGISTER3 STRING "CLOCK0"
// Retrieval info: CONSTANT: CHAINOUT_ACLR STRING "UNUSED"
// Retrieval info: CONSTANT: CHAINOUT_ADDER STRING "YES"
// Retrieval info: CONSTANT: CHAINOUT_REGISTER STRING "CLOCK0"
// Retrieval info: CONSTANT: DEDICATED_MULTIPLIER_CIRCUITRY STRING "YES"
// Retrieval info: CONSTANT: INPUT_ACLR_A0 STRING "UNUSED"
// Retrieval info: CONSTANT: INPUT_ACLR_A1 STRING "UNUSED"
// Retrieval info: CONSTANT: INPUT_ACLR_A2 STRING "UNUSED"
// Retrieval info: CONSTANT: INPUT_ACLR_A3 STRING "UNUSED"
// Retrieval info: CONSTANT: INPUT_ACLR_B0 STRING "UNUSED"
// Retrieval info: CONSTANT: INPUT_ACLR_B1 STRING "UNUSED"
// Retrieval info: CONSTANT: INPUT_ACLR_B2 STRING "UNUSED"
// Retrieval info: CONSTANT: INPUT_ACLR_B3 STRING "UNUSED"
// Retrieval info: CONSTANT: INPUT_REGISTER_A0 STRING "CLOCK0"
// Retrieval info: CONSTANT: INPUT_REGISTER_A1 STRING "CLOCK0"
// Retrieval info: CONSTANT: INPUT_REGISTER_A2 STRING "CLOCK0"
// Retrieval info: CONSTANT: INPUT_REGISTER_A3 STRING "CLOCK0"
// Retrieval info: CONSTANT: INPUT_REGISTER_B0 STRING "CLOCK0"
// Retrieval info: CONSTANT: INPUT_REGISTER_B1 STRING "CLOCK0"
// Retrieval info: CONSTANT: INPUT_REGISTER_B2 STRING "CLOCK0"
// Retrieval info: CONSTANT: INPUT_REGISTER_B3 STRING "CLOCK0"
// Retrieval info: CONSTANT: INPUT_SOURCE_A0 STRING "DATAA"
// Retrieval info: CONSTANT: INPUT_SOURCE_A1 STRING "DATAA"
// Retrieval info: CONSTANT: INPUT_SOURCE_A2 STRING "DATAA"
// Retrieval info: CONSTANT: INPUT_SOURCE_A3 STRING "DATAA"
// Retrieval info: CONSTANT: INPUT_SOURCE_B0 STRING "DATAB"
// Retrieval info: CONSTANT: INPUT_SOURCE_B1 STRING "DATAB"
// Retrieval info: CONSTANT: INPUT_SOURCE_B2 STRING "DATAB"
// Retrieval info: CONSTANT: INPUT_SOURCE_B3 STRING "DATAB"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altmult_add"
// Retrieval info: CONSTANT: MULTIPLIER1_DIRECTION STRING "ADD"
// Retrieval info: CONSTANT: MULTIPLIER3_DIRECTION STRING "ADD"
// Retrieval info: CONSTANT: MULTIPLIER_ACLR0 STRING "UNUSED"
// Retrieval info: CONSTANT: MULTIPLIER_ACLR1 STRING "UNUSED"
// Retrieval info: CONSTANT: MULTIPLIER_ACLR2 STRING "UNUSED"
// Retrieval info: CONSTANT: MULTIPLIER_ACLR3 STRING "UNUSED"
// Retrieval info: CONSTANT: MULTIPLIER_REGISTER0 STRING "CLOCK0"
// Retrieval info: CONSTANT: MULTIPLIER_REGISTER1 STRING "CLOCK0"
// Retrieval info: CONSTANT: MULTIPLIER_REGISTER2 STRING "CLOCK0"
// Retrieval info: CONSTANT: MULTIPLIER_REGISTER3 STRING "CLOCK0"
// Retrieval info: CONSTANT: NUMBER_OF_MULTIPLIERS NUMERIC "4"
// Retrieval info: CONSTANT: OUTPUT_ACLR STRING "UNUSED"
// Retrieval info: CONSTANT: OUTPUT_REGISTER STRING "CLOCK0"
// Retrieval info: CONSTANT: PORT_ADDNSUB1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_ADDNSUB3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SIGNA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SIGNB STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: REPRESENTATION_A STRING "SIGNED"
// Retrieval info: CONSTANT: REPRESENTATION_B STRING "SIGNED"
// Retrieval info: CONSTANT: SIGNED_ACLR_A STRING "UNUSED"
// Retrieval info: CONSTANT: SIGNED_ACLR_B STRING "UNUSED"
// Retrieval info: CONSTANT: SIGNED_PIPELINE_ACLR_A STRING "UNUSED"
// Retrieval info: CONSTANT: SIGNED_PIPELINE_ACLR_B STRING "UNUSED"
// Retrieval info: CONSTANT: SIGNED_PIPELINE_REGISTER_A STRING "CLOCK0"
// Retrieval info: CONSTANT: SIGNED_PIPELINE_REGISTER_B STRING "CLOCK0"
// Retrieval info: CONSTANT: SIGNED_REGISTER_A STRING "CLOCK0"
// Retrieval info: CONSTANT: SIGNED_REGISTER_B STRING "CLOCK0"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "18"
// Retrieval info: CONSTANT: WIDTH_B NUMERIC "18"
// Retrieval info: CONSTANT: WIDTH_CHAININ NUMERIC "44"
// Retrieval info: CONSTANT: WIDTH_RESULT NUMERIC "44"
// Retrieval info: CONSTANT: ZERO_CHAINOUT_OUTPUT_ACLR STRING "UNUSED"
// Retrieval info: CONSTANT: ZERO_CHAINOUT_OUTPUT_REGISTER STRING "CLOCK0"
// Retrieval info: CONSTANT: ZERO_LOOPBACK_ACLR STRING "UNUSED"
// Retrieval info: CONSTANT: ZERO_LOOPBACK_OUTPUT_ACLR STRING "UNUSED"
// Retrieval info: CONSTANT: ZERO_LOOPBACK_OUTPUT_REGISTER STRING "CLOCK0"
// Retrieval info: CONSTANT: ZERO_LOOPBACK_PIPELINE_ACLR STRING "UNUSED"
// Retrieval info: CONSTANT: ZERO_LOOPBACK_PIPELINE_REGISTER STRING "CLOCK0"
// Retrieval info: CONSTANT: ZERO_LOOPBACK_REGISTER STRING "CLOCK0"
// Retrieval info: USED_PORT: chainin 0 0 44 0 INPUT GND "chainin[43..0]"
// Retrieval info: USED_PORT: clock0 0 0 0 0 INPUT VCC "clock0"
// Retrieval info: USED_PORT: dataa_0 0 0 18 0 INPUT GND "dataa_0[17..0]"
// Retrieval info: USED_PORT: dataa_1 0 0 18 0 INPUT GND "dataa_1[17..0]"
// Retrieval info: USED_PORT: dataa_2 0 0 18 0 INPUT GND "dataa_2[17..0]"
// Retrieval info: USED_PORT: dataa_3 0 0 18 0 INPUT GND "dataa_3[17..0]"
// Retrieval info: USED_PORT: datab_0 0 0 18 0 INPUT GND "datab_0[17..0]"
// Retrieval info: USED_PORT: datab_1 0 0 18 0 INPUT GND "datab_1[17..0]"
// Retrieval info: USED_PORT: datab_2 0 0 18 0 INPUT GND "datab_2[17..0]"
// Retrieval info: USED_PORT: datab_3 0 0 18 0 INPUT GND "datab_3[17..0]"
// Retrieval info: USED_PORT: result 0 0 44 0 OUTPUT GND "result[43..0]"
// Retrieval info: CONNECT: @chainin 0 0 44 0 chainin 0 0 44 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock0 0 0 0 0
// Retrieval info: CONNECT: @dataa 0 0 18 0 dataa_0 0 0 18 0
// Retrieval info: CONNECT: @dataa 0 0 18 18 dataa_1 0 0 18 0
// Retrieval info: CONNECT: @dataa 0 0 18 36 dataa_2 0 0 18 0
// Retrieval info: CONNECT: @dataa 0 0 18 54 dataa_3 0 0 18 0
// Retrieval info: CONNECT: @datab 0 0 18 0 datab_0 0 0 18 0
// Retrieval info: CONNECT: @datab 0 0 18 18 datab_1 0 0 18 0
// Retrieval info: CONNECT: @datab 0 0 18 36 datab_2 0 0 18 0
// Retrieval info: CONNECT: @datab 0 0 18 54 datab_3 0 0 18 0
// Retrieval info: CONNECT: result 0 0 44 0 @result 0 0 44 0
// Retrieval info: GEN_FILE: TYPE_NORMAL mult_accum_chain.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL mult_accum_chain.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL mult_accum_chain.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL mult_accum_chain.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL mult_accum_chain_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL mult_accum_chain_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
// megafunction wizard: %ALTMULT_ACCUM (MAC)%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altmult_add
// ============================================================
// File Name: mult_accum_chain.v
// Megafunction Name(s):
// altmult_add
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 12.0 Build 178 05/31/2012 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2012 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module mult_accum_chain (
chainin,
clock0,
dataa_0,
dataa_1,
dataa_2,
dataa_3,
datab_0,
datab_1,
datab_2,
datab_3,
result);
input [43:0] chainin;
input clock0;
input [17:0] dataa_0;
input [17:0] dataa_1;
input [17:0] dataa_2;
input [17:0] dataa_3;
input [17:0] datab_0;
input [17:0] datab_1;
input [17:0] datab_2;
input [17:0] datab_3;
output [43:0] result;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 [43:0] chainin;
tri1 clock0;
tri0 [17:0] dataa_0;
tri0 [17:0] dataa_1;
tri0 [17:0] dataa_2;
tri0 [17:0] dataa_3;
tri0 [17:0] datab_0;
tri0 [17:0] datab_1;
tri0 [17:0] datab_2;
tri0 [17:0] datab_3;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ACCUM_DIRECTION STRING "Add"
// Retrieval info: PRIVATE: ACCUM_SLOAD NUMERIC "0"
// Retrieval info: PRIVATE: ACCUM_SLOAD_ACLR NUMERIC "3"
// Retrieval info: PRIVATE: ACCUM_SLOAD_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ACCUM_SLOAD_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ACCUM_SLOAD_PIPELINE_ACLR NUMERIC "3"
// Retrieval info: PRIVATE: ACCUM_SLOAD_PIPELINE_REG NUMERIC "1"
// Retrieval info: PRIVATE: ACCUM_SLOAD_PIPELINE_REG_INDEX NUMERIC "0"
// Retrieval info: PRIVATE: ACCUM_SLOAD_PIPE_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ACCUM_SLOAD_PIPE_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ACCUM_SLOAD_PIPE_REG STRING "1"
// Retrieval info: PRIVATE: ACCUM_SLOAD_REG NUMERIC "1"
// Retrieval info: PRIVATE: ACCUM_SLOAD_REG_INDEX NUMERIC "0"
// Retrieval info: PRIVATE: ACCUM_SLOAD_UPPER_DATA NUMERIC "0"
// Retrieval info: PRIVATE: ACCUM_SLOAD_UPPER_DATA_ACLR NUMERIC "3"
// Retrieval info: PRIVATE: ACCUM_SLOAD_UPPER_DATA_PIPELINE_ACLR NUMERIC "3"
// Retrieval info: PRIVATE: ACCUM_SLOAD_UPPER_DATA_PIPELINE_REG NUMERIC "0"
// Retrieval info: PRIVATE: ACCUM_SLOAD_UPPER_DATA_REG NUMERIC "0"
// Retrieval info: PRIVATE: ADDNSUB1_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ADDNSUB1_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ADDNSUB1_PIPE_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ADDNSUB1_PIPE_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ADDNSUB1_PIPE_REG STRING "1"
// Retrieval info: PRIVATE: ADDNSUB1_REG STRING "1"
// Retrieval info: PRIVATE: ADDNSUB3_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ADDNSUB3_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ADDNSUB3_PIPE_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ADDNSUB3_PIPE_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ADDNSUB3_PIPE_REG STRING "1"
// Retrieval info: PRIVATE: ADDNSUB3_REG STRING "1"
// Retrieval info: PRIVATE: ADD_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: ALL_REG_ACLR NUMERIC "0"
// Retrieval info: PRIVATE: A_ACLR_SRC_MULT0 NUMERIC "3"
// Retrieval info: PRIVATE: A_CLK_SRC_MULT0 NUMERIC "0"
// Retrieval info: PRIVATE: B_ACLR_SRC_MULT0 NUMERIC "3"
// Retrieval info: PRIVATE: B_CLK_SRC_MULT0 NUMERIC "0"
// Retrieval info: PRIVATE: CHAINOUT_OUTPUT_ACLR NUMERIC "3"
// Retrieval info: PRIVATE: CHAINOUT_OUTPUT_REG STRING "1"
// Retrieval info: PRIVATE: CHAINOUT_OUTPUT_REGISTER NUMERIC "0"
// Retrieval info: PRIVATE: CHAINOUT_OUTPUT_REGISTERED NUMERIC "1"
// Retrieval info: PRIVATE: CHAS_ZERO_CHAINOUT NUMERIC "0"
// Retrieval info: PRIVATE: EXTRA_MULTIPLIER_LATENCY NUMERIC "0"
// Retrieval info: PRIVATE: HAS_ACCUMULATOR NUMERIC "1"
// Retrieval info: PRIVATE: HAS_ACUMM_SLOAD NUMERIC "0"
// Retrieval info: PRIVATE: HAS_CHAININ_PORT NUMERIC "1"
// Retrieval info: PRIVATE: HAS_CHAINOUT_ADDER NUMERIC "1"
// Retrieval info: PRIVATE: HAS_LOOPBACK NUMERIC "0"
// Retrieval info: PRIVATE: HAS_MAC STRING "1"
// Retrieval info: PRIVATE: HAS_SAT_ROUND STRING "0"
// Retrieval info: PRIVATE: HAS_ZERO_LOOPBACK NUMERIC "0"
// Retrieval info: PRIVATE: IMPL_STYLE_DEDICATED NUMERIC "1"
// Retrieval info: PRIVATE: IMPL_STYLE_DEFAULT NUMERIC "0"
// Retrieval info: PRIVATE: IMPL_STYLE_LCELL NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
// Retrieval info: PRIVATE: MULT_LATENCY NUMERIC "0"
// Retrieval info: PRIVATE: MULT_REGA0 NUMERIC "1"
// Retrieval info: PRIVATE: MULT_REGB0 NUMERIC "1"
// Retrieval info: PRIVATE: MULT_REGOUT0 NUMERIC "1"
// Retrieval info: PRIVATE: NUM_MULT STRING "4"
// Retrieval info: PRIVATE: OP1 STRING "Add"
// Retrieval info: PRIVATE: OP3 STRING "Add"
// Retrieval info: PRIVATE: OUTPUT_EXTRA_LAT NUMERIC "0"
// Retrieval info: PRIVATE: OUTPUT_REG_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: OUTPUT_REG_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW NUMERIC "0"
// Retrieval info: PRIVATE: Q_ACLR_SRC_MULT0 NUMERIC "3"
// Retrieval info: PRIVATE: Q_CLK_SRC_MULT0 NUMERIC "0"
// Retrieval info: PRIVATE: REG_OUT NUMERIC "1"
// Retrieval info: PRIVATE: RNFORMAT STRING "44"
// Retrieval info: PRIVATE: ROTATE_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ROTATE_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ROTATE_OUT_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ROTATE_OUT_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ROTATE_OUT_REG STRING "1"
// Retrieval info: PRIVATE: ROTATE_PIPE_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ROTATE_PIPE_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ROTATE_PIPE_REG STRING "1"
// Retrieval info: PRIVATE: ROTATE_REG STRING "1"
// Retrieval info: PRIVATE: ROUND3_CHAINOUT_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ROUND3_CHAINOUT_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ROUND3_CHAINOUT_MODE STRING "Enabled"
// Retrieval info: PRIVATE: ROUND3_CHAINOUT_OUT_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ROUND3_CHAINOUT_OUT_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ROUND3_CHAINOUT_OUT_REG STRING "1"
// Retrieval info: PRIVATE: ROUND3_CHAINOUT_PIPE_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ROUND3_CHAINOUT_PIPE_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ROUND3_CHAINOUT_PIPE_REG STRING "1"
// Retrieval info: PRIVATE: ROUND3_CHAINOUT_REG STRING "1"
// Retrieval info: PRIVATE: ROUND3_FRAC_WIDTH NUMERIC "23"
// Retrieval info: PRIVATE: ROUND3_OUTPUT_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ROUND3_OUTPUT_CHAINOUT_TYPE STRING "Nearest Integer"
// Retrieval info: PRIVATE: ROUND3_OUTPUT_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ROUND3_OUTPUT_MODE STRING "Disabled"
// Retrieval info: PRIVATE: ROUND3_OUTPUT_PIPE_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ROUND3_OUTPUT_PIPE_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ROUND3_OUTPUT_PIPE_REG STRING "1"
// Retrieval info: PRIVATE: ROUND3_OUTPUT_REG STRING "1"
// Retrieval info: PRIVATE: RQFORMAT STRING "Q1.30"
// Retrieval info: PRIVATE: RTS_WIDTH STRING "44"
// Retrieval info: PRIVATE: SAME_CONFIG NUMERIC "1"
// Retrieval info: PRIVATE: SAME_CONTROL_SRC_A0 NUMERIC "1"
// Retrieval info: PRIVATE: SAME_CONTROL_SRC_B0 NUMERIC "1"
// Retrieval info: PRIVATE: SAT3_CHAINOUT_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: SAT3_CHAINOUT_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: SAT3_CHAINOUT_MODE STRING "Enabled"
// Retrieval info: PRIVATE: SAT3_CHAINOUT_OUT_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: SAT3_CHAINOUT_OUT_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: SAT3_CHAINOUT_OVERFLOW NUMERIC "1"
// Retrieval info: PRIVATE: SAT3_CHAINOUT_PIPE_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: SAT3_CHAINOUT_PIPE_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: SAT3_CHAINOUT_PIPE_REG STRING "1"
// Retrieval info: PRIVATE: SAT3_CHAINOUT_REG STRING "1"
// Retrieval info: PRIVATE: SAT3_FRAC_WIDTH NUMERIC "1"
// Retrieval info: PRIVATE: SAT3_OUTPUT_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: SAT3_OUTPUT_CHAINOUT_TYPE STRING "Asymmetric"
// Retrieval info: PRIVATE: SAT3_OUTPUT_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: SAT3_OUTPUT_MODE STRING "Enabled"
// Retrieval info: PRIVATE: SAT3_OUTPUT_OVERFLOW NUMERIC "1"
// Retrieval info: PRIVATE: SAT3_OUTPUT_PIPE_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: SAT3_OUTPUT_PIPE_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: SAT3_OUTPUT_PIPE_REG STRING "1"
// Retrieval info: PRIVATE: SAT3_OUTPUT_REG STRING "1"
// Retrieval info: PRIVATE: SCANOUTA NUMERIC "0"
// Retrieval info: PRIVATE: SCANOUTB NUMERIC "0"
// Retrieval info: PRIVATE: SHIFTOUTA_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: SHIFTOUTA_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: SHIFTOUTA_REG STRING "0"
// Retrieval info: PRIVATE: SHIFT_RIGHT_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: SHIFT_RIGHT_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: SHIFT_RIGHT_OUT_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: SHIFT_RIGHT_OUT_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: SHIFT_RIGHT_OUT_REG STRING "1"
// Retrieval info: PRIVATE: SHIFT_RIGHT_PIPE_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: SHIFT_RIGHT_PIPE_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: SHIFT_RIGHT_PIPE_REG STRING "1"
// Retrieval info: PRIVATE: SHIFT_RIGHT_REG STRING "1"
// Retrieval info: PRIVATE: SHIFT_ROTATE_MODE STRING "None"
// Retrieval info: PRIVATE: SIGNA STRING "SIGNED"
// Retrieval info: PRIVATE: SIGNA_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: SIGNA_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: SIGNA_PIPE_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: SIGNA_PIPE_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: SIGNA_PIPE_REG STRING "1"
// Retrieval info: PRIVATE: SIGNA_REG STRING "1"
// Retrieval info: PRIVATE: SIGNB STRING "SIGNED"
// Retrieval info: PRIVATE: SIGNB_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: SIGNB_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: SIGNB_PIPE_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: SIGNB_PIPE_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: SIGNB_PIPE_REG STRING "1"
// Retrieval info: PRIVATE: SIGNB_REG STRING "1"
// Retrieval info: PRIVATE: SRCA0 STRING "Multiplier input"
// Retrieval info: PRIVATE: SRCB0 STRING "Multiplier input"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: WIDTHA STRING "18"
// Retrieval info: PRIVATE: WIDTHB STRING "18"
// Retrieval info: PRIVATE: WIDTH_UPPER_DATA NUMERIC "1"
// Retrieval info: PRIVATE: ZERO_CHAINOUT_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ZERO_CHAINOUT_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_CHAINOUT_REG STRING "0"
// Retrieval info: PRIVATE: ZERO_LOOPBACK_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ZERO_LOOPBACK_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_LOOPBACK_OUT_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ZERO_LOOPBACK_OUT_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_LOOPBACK_OUT_REG STRING "1"
// Retrieval info: PRIVATE: ZERO_LOOPBACK_PIPE_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ZERO_LOOPBACK_PIPE_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_LOOPBACK_PIPE_REG STRING "1"
// Retrieval info: PRIVATE: ZERO_LOOPBACK_REG STRING "1"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ACCUMULATOR STRING "YES"
// Retrieval info: CONSTANT: ACCUM_DIRECTION STRING "ADD"
// Retrieval info: CONSTANT: ADDNSUB_MULTIPLIER_ACLR1 STRING "UNUSED"
// Retrieval info: CONSTANT: ADDNSUB_MULTIPLIER_ACLR3 STRING "UNUSED"
// Retrieval info: CONSTANT: ADDNSUB_MULTIPLIER_PIPELINE_ACLR1 STRING "UNUSED"
// Retrieval info: CONSTANT: ADDNSUB_MULTIPLIER_PIPELINE_ACLR3 STRING "UNUSED"
// Retrieval info: CONSTANT: ADDNSUB_MULTIPLIER_PIPELINE_REGISTER1 STRING "CLOCK0"
// Retrieval info: CONSTANT: ADDNSUB_MULTIPLIER_PIPELINE_REGISTER3 STRING "CLOCK0"
// Retrieval info: CONSTANT: ADDNSUB_MULTIPLIER_REGISTER1 STRING "CLOCK0"
// Retrieval info: CONSTANT: ADDNSUB_MULTIPLIER_REGISTER3 STRING "CLOCK0"
// Retrieval info: CONSTANT: CHAINOUT_ACLR STRING "UNUSED"
// Retrieval info: CONSTANT: CHAINOUT_ADDER STRING "YES"
// Retrieval info: CONSTANT: CHAINOUT_REGISTER STRING "CLOCK0"
// Retrieval info: CONSTANT: DEDICATED_MULTIPLIER_CIRCUITRY STRING "YES"
// Retrieval info: CONSTANT: INPUT_ACLR_A0 STRING "UNUSED"
// Retrieval info: CONSTANT: INPUT_ACLR_A1 STRING "UNUSED"
// Retrieval info: CONSTANT: INPUT_ACLR_A2 STRING "UNUSED"
// Retrieval info: CONSTANT: INPUT_ACLR_A3 STRING "UNUSED"
// Retrieval info: CONSTANT: INPUT_ACLR_B0 STRING "UNUSED"
// Retrieval info: CONSTANT: INPUT_ACLR_B1 STRING "UNUSED"
// Retrieval info: CONSTANT: INPUT_ACLR_B2 STRING "UNUSED"
// Retrieval info: CONSTANT: INPUT_ACLR_B3 STRING "UNUSED"
// Retrieval info: CONSTANT: INPUT_REGISTER_A0 STRING "CLOCK0"
// Retrieval info: CONSTANT: INPUT_REGISTER_A1 STRING "CLOCK0"
// Retrieval info: CONSTANT: INPUT_REGISTER_A2 STRING "CLOCK0"
// Retrieval info: CONSTANT: INPUT_REGISTER_A3 STRING "CLOCK0"
// Retrieval info: CONSTANT: INPUT_REGISTER_B0 STRING "CLOCK0"
// Retrieval info: CONSTANT: INPUT_REGISTER_B1 STRING "CLOCK0"
// Retrieval info: CONSTANT: INPUT_REGISTER_B2 STRING "CLOCK0"
// Retrieval info: CONSTANT: INPUT_REGISTER_B3 STRING "CLOCK0"
// Retrieval info: CONSTANT: INPUT_SOURCE_A0 STRING "DATAA"
// Retrieval info: CONSTANT: INPUT_SOURCE_A1 STRING "DATAA"
// Retrieval info: CONSTANT: INPUT_SOURCE_A2 STRING "DATAA"
// Retrieval info: CONSTANT: INPUT_SOURCE_A3 STRING "DATAA"
// Retrieval info: CONSTANT: INPUT_SOURCE_B0 STRING "DATAB"
// Retrieval info: CONSTANT: INPUT_SOURCE_B1 STRING "DATAB"
// Retrieval info: CONSTANT: INPUT_SOURCE_B2 STRING "DATAB"
// Retrieval info: CONSTANT: INPUT_SOURCE_B3 STRING "DATAB"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altmult_add"
// Retrieval info: CONSTANT: MULTIPLIER1_DIRECTION STRING "ADD"
// Retrieval info: CONSTANT: MULTIPLIER3_DIRECTION STRING "ADD"
// Retrieval info: CONSTANT: MULTIPLIER_ACLR0 STRING "UNUSED"
// Retrieval info: CONSTANT: MULTIPLIER_ACLR1 STRING "UNUSED"
// Retrieval info: CONSTANT: MULTIPLIER_ACLR2 STRING "UNUSED"
// Retrieval info: CONSTANT: MULTIPLIER_ACLR3 STRING "UNUSED"
// Retrieval info: CONSTANT: MULTIPLIER_REGISTER0 STRING "CLOCK0"
// Retrieval info: CONSTANT: MULTIPLIER_REGISTER1 STRING "CLOCK0"
// Retrieval info: CONSTANT: MULTIPLIER_REGISTER2 STRING "CLOCK0"
// Retrieval info: CONSTANT: MULTIPLIER_REGISTER3 STRING "CLOCK0"
// Retrieval info: CONSTANT: NUMBER_OF_MULTIPLIERS NUMERIC "4"
// Retrieval info: CONSTANT: OUTPUT_ACLR STRING "UNUSED"
// Retrieval info: CONSTANT: OUTPUT_REGISTER STRING "CLOCK0"
// Retrieval info: CONSTANT: PORT_ADDNSUB1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_ADDNSUB3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SIGNA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SIGNB STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: REPRESENTATION_A STRING "SIGNED"
// Retrieval info: CONSTANT: REPRESENTATION_B STRING "SIGNED"
// Retrieval info: CONSTANT: SIGNED_ACLR_A STRING "UNUSED"
// Retrieval info: CONSTANT: SIGNED_ACLR_B STRING "UNUSED"
// Retrieval info: CONSTANT: SIGNED_PIPELINE_ACLR_A STRING "UNUSED"
// Retrieval info: CONSTANT: SIGNED_PIPELINE_ACLR_B STRING "UNUSED"
// Retrieval info: CONSTANT: SIGNED_PIPELINE_REGISTER_A STRING "CLOCK0"
// Retrieval info: CONSTANT: SIGNED_PIPELINE_REGISTER_B STRING "CLOCK0"
// Retrieval info: CONSTANT: SIGNED_REGISTER_A STRING "CLOCK0"
// Retrieval info: CONSTANT: SIGNED_REGISTER_B STRING "CLOCK0"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "18"
// Retrieval info: CONSTANT: WIDTH_B NUMERIC "18"
// Retrieval info: CONSTANT: WIDTH_CHAININ NUMERIC "44"
// Retrieval info: CONSTANT: WIDTH_RESULT NUMERIC "44"
// Retrieval info: CONSTANT: ZERO_CHAINOUT_OUTPUT_ACLR STRING "UNUSED"
// Retrieval info: CONSTANT: ZERO_CHAINOUT_OUTPUT_REGISTER STRING "CLOCK0"
// Retrieval info: CONSTANT: ZERO_LOOPBACK_ACLR STRING "UNUSED"
// Retrieval info: CONSTANT: ZERO_LOOPBACK_OUTPUT_ACLR STRING "UNUSED"
// Retrieval info: CONSTANT: ZERO_LOOPBACK_OUTPUT_REGISTER STRING "CLOCK0"
// Retrieval info: CONSTANT: ZERO_LOOPBACK_PIPELINE_ACLR STRING "UNUSED"
// Retrieval info: CONSTANT: ZERO_LOOPBACK_PIPELINE_REGISTER STRING "CLOCK0"
// Retrieval info: CONSTANT: ZERO_LOOPBACK_REGISTER STRING "CLOCK0"
// Retrieval info: USED_PORT: chainin 0 0 44 0 INPUT GND "chainin[43..0]"
// Retrieval info: USED_PORT: clock0 0 0 0 0 INPUT VCC "clock0"
// Retrieval info: USED_PORT: dataa_0 0 0 18 0 INPUT GND "dataa_0[17..0]"
// Retrieval info: USED_PORT: dataa_1 0 0 18 0 INPUT GND "dataa_1[17..0]"
// Retrieval info: USED_PORT: dataa_2 0 0 18 0 INPUT GND "dataa_2[17..0]"
// Retrieval info: USED_PORT: dataa_3 0 0 18 0 INPUT GND "dataa_3[17..0]"
// Retrieval info: USED_PORT: datab_0 0 0 18 0 INPUT GND "datab_0[17..0]"
// Retrieval info: USED_PORT: datab_1 0 0 18 0 INPUT GND "datab_1[17..0]"
// Retrieval info: USED_PORT: datab_2 0 0 18 0 INPUT GND "datab_2[17..0]"
// Retrieval info: USED_PORT: datab_3 0 0 18 0 INPUT GND "datab_3[17..0]"
// Retrieval info: USED_PORT: result 0 0 44 0 OUTPUT GND "result[43..0]"
// Retrieval info: CONNECT: @chainin 0 0 44 0 chainin 0 0 44 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock0 0 0 0 0
// Retrieval info: CONNECT: @dataa 0 0 18 0 dataa_0 0 0 18 0
// Retrieval info: CONNECT: @dataa 0 0 18 18 dataa_1 0 0 18 0
// Retrieval info: CONNECT: @dataa 0 0 18 36 dataa_2 0 0 18 0
// Retrieval info: CONNECT: @dataa 0 0 18 54 dataa_3 0 0 18 0
// Retrieval info: CONNECT: @datab 0 0 18 0 datab_0 0 0 18 0
// Retrieval info: CONNECT: @datab 0 0 18 18 datab_1 0 0 18 0
// Retrieval info: CONNECT: @datab 0 0 18 36 datab_2 0 0 18 0
// Retrieval info: CONNECT: @datab 0 0 18 54 datab_3 0 0 18 0
// Retrieval info: CONNECT: result 0 0 44 0 @result 0 0 44 0
// Retrieval info: GEN_FILE: TYPE_NORMAL mult_accum_chain.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL mult_accum_chain.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL mult_accum_chain.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL mult_accum_chain.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL mult_accum_chain_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL mult_accum_chain_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
mult_accum_chain mult_accum_chain_inst (
.chainin ( chainin_sig ),
.clock0 ( clock0_sig ),
.dataa_0 ( dataa_0_sig ),
.dataa_1 ( dataa_1_sig ),
.dataa_2 ( dataa_2_sig ),
.dataa_3 ( dataa_3_sig ),
.datab_0 ( datab_0_sig ),
.datab_1 ( datab_1_sig ),
.datab_2 ( datab_2_sig ),
.datab_3 ( datab_3_sig ),
.result ( result_sig )
);
|
// megafunction wizard: %ALTMULT_ADD%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: ALTMULT_ADD
// ============================================================
// File Name: mult_loopback.v
// Megafunction Name(s):
// ALTMULT_ADD
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 12.0 Build 178 05/31/2012 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2012 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module mult_loopback (
clock0,
dataa_0,
dataa_1,
datab_1,
result);
input clock0;
input [17:0] dataa_0;
input [17:0] dataa_1;
input [17:0] datab_1;
output [35:0] result;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock0;
tri0 [17:0] dataa_0;
tri0 [17:0] dataa_1;
tri0 [17:0] datab_1;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [35:0] sub_wire0;
wire [17:0] sub_wire6 = 18'h0;
wire [17:0] sub_wire3 = dataa_1[17:0];
wire [35:0] result = sub_wire0[35:0];
wire [17:0] sub_wire1 = dataa_0[17:0];
wire [35:0] sub_wire2 = {sub_wire3, sub_wire1};
wire [17:0] sub_wire4 = datab_1[17:0];
wire [35:0] sub_wire5 = {sub_wire6, sub_wire4};
altmult_add ALTMULT_ADD_component (
.clock0 (clock0),
.dataa (sub_wire2),
.datab (sub_wire5),
.result (sub_wire0),
.accum_sload (1'b0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.aclr2 (1'b0),
.aclr3 (1'b0),
.addnsub1 (1'b1),
.addnsub1_round (1'b0),
.addnsub3 (1'b1),
.addnsub3_round (1'b0),
.chainin (1'b0),
.chainout_round (1'b0),
.chainout_sat_overflow (),
.chainout_saturate (1'b0),
.clock1 (1'b1),
.clock2 (1'b1),
.clock3 (1'b1),
.coefsel0 ({3{1'b0}}),
.coefsel1 ({3{1'b0}}),
.coefsel2 ({3{1'b0}}),
.coefsel3 ({3{1'b0}}),
.datac ({44{1'b0}}),
.ena0 (1'b1),
.ena1 (1'b1),
.ena2 (1'b1),
.ena3 (1'b1),
.mult01_round (1'b0),
.mult01_saturation (1'b0),
.mult0_is_saturated (),
.mult1_is_saturated (),
.mult23_round (1'b0),
.mult23_saturation (1'b0),
.mult2_is_saturated (),
.mult3_is_saturated (),
.output_round (1'b0),
.output_saturate (1'b0),
.overflow (),
.rotate (1'b0),
.scanina ({18{1'b0}}),
.scaninb ({18{1'b0}}),
.scanouta (),
.scanoutb (),
.shift_right (1'b0),
.signa (1'b0),
.signb (1'b0),
.sourcea ({2{1'b0}}),
.sourceb ({2{1'b0}}),
.zero_chainout (1'b0),
.zero_loopback (1'b0));
defparam
ALTMULT_ADD_component.accumulator = "NO",
ALTMULT_ADD_component.addnsub_multiplier_aclr1 = "UNUSED",
ALTMULT_ADD_component.addnsub_multiplier_pipeline_aclr1 = "UNUSED",
ALTMULT_ADD_component.addnsub_multiplier_pipeline_register1 = "CLOCK0",
ALTMULT_ADD_component.addnsub_multiplier_register1 = "CLOCK0",
ALTMULT_ADD_component.chainout_adder = "NO",
ALTMULT_ADD_component.chainout_register = "UNREGISTERED",
ALTMULT_ADD_component.dedicated_multiplier_circuitry = "YES",
ALTMULT_ADD_component.input_aclr_a0 = "UNUSED",
ALTMULT_ADD_component.input_aclr_a1 = "UNUSED",
ALTMULT_ADD_component.input_aclr_b0 = "UNUSED",
ALTMULT_ADD_component.input_aclr_b1 = "UNUSED",
ALTMULT_ADD_component.input_register_a0 = "CLOCK0",
ALTMULT_ADD_component.input_register_a1 = "CLOCK0",
ALTMULT_ADD_component.input_register_b0 = "CLOCK0",
ALTMULT_ADD_component.input_register_b1 = "CLOCK0",
ALTMULT_ADD_component.input_source_a0 = "DATAA",
ALTMULT_ADD_component.input_source_a1 = "DATAA",
ALTMULT_ADD_component.input_source_b0 = "LOOPBACK",
ALTMULT_ADD_component.input_source_b1 = "DATAB",
ALTMULT_ADD_component.intended_device_family = "Stratix IV",
ALTMULT_ADD_component.lpm_type = "altmult_add",
ALTMULT_ADD_component.multiplier1_direction = "ADD",
ALTMULT_ADD_component.multiplier_aclr0 = "UNUSED",
ALTMULT_ADD_component.multiplier_aclr1 = "UNUSED",
ALTMULT_ADD_component.multiplier_register0 = "CLOCK0",
ALTMULT_ADD_component.multiplier_register1 = "CLOCK0",
ALTMULT_ADD_component.number_of_multipliers = 2,
ALTMULT_ADD_component.output_aclr = "UNUSED",
ALTMULT_ADD_component.output_register = "CLOCK0",
ALTMULT_ADD_component.output_rounding = "NO",
ALTMULT_ADD_component.output_round_aclr = "UNUSED",
ALTMULT_ADD_component.output_round_pipeline_aclr = "UNUSED",
ALTMULT_ADD_component.output_round_pipeline_register = "CLOCK0",
ALTMULT_ADD_component.output_round_register = "CLOCK0",
ALTMULT_ADD_component.output_round_type = "NEAREST_INTEGER",
ALTMULT_ADD_component.output_saturate_aclr = "UNUSED",
ALTMULT_ADD_component.output_saturate_pipeline_aclr = "UNUSED",
ALTMULT_ADD_component.output_saturate_pipeline_register = "CLOCK0",
ALTMULT_ADD_component.output_saturate_register = "CLOCK0",
ALTMULT_ADD_component.output_saturate_type = "SYMMETRIC",
ALTMULT_ADD_component.output_saturation = "NO",
ALTMULT_ADD_component.port_addnsub1 = "PORT_UNUSED",
ALTMULT_ADD_component.port_output_is_overflow = "PORT_UNUSED",
ALTMULT_ADD_component.port_signa = "PORT_UNUSED",
ALTMULT_ADD_component.port_signb = "PORT_UNUSED",
ALTMULT_ADD_component.representation_a = "SIGNED",
ALTMULT_ADD_component.representation_b = "SIGNED",
ALTMULT_ADD_component.signed_aclr_a = "UNUSED",
ALTMULT_ADD_component.signed_aclr_b = "UNUSED",
ALTMULT_ADD_component.signed_pipeline_aclr_a = "UNUSED",
ALTMULT_ADD_component.signed_pipeline_aclr_b = "UNUSED",
ALTMULT_ADD_component.signed_pipeline_register_a = "CLOCK0",
ALTMULT_ADD_component.signed_pipeline_register_b = "CLOCK0",
ALTMULT_ADD_component.signed_register_a = "CLOCK0",
ALTMULT_ADD_component.signed_register_b = "CLOCK0",
ALTMULT_ADD_component.width_a = 18,
ALTMULT_ADD_component.width_b = 18,
ALTMULT_ADD_component.width_chainin = 1,
ALTMULT_ADD_component.width_msb = 18,
ALTMULT_ADD_component.width_result = 36,
ALTMULT_ADD_component.width_saturate_sign = 2,
ALTMULT_ADD_component.zero_chainout_output_aclr = "UNUSED",
ALTMULT_ADD_component.zero_chainout_output_register = "CLOCK0",
ALTMULT_ADD_component.zero_loopback_aclr = "UNUSED",
ALTMULT_ADD_component.zero_loopback_output_aclr = "UNUSED",
ALTMULT_ADD_component.zero_loopback_output_register = "CLOCK0",
ALTMULT_ADD_component.zero_loopback_pipeline_aclr = "UNUSED",
ALTMULT_ADD_component.zero_loopback_pipeline_register = "CLOCK0",
ALTMULT_ADD_component.zero_loopback_register = "CLOCK0";
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ACCUM_DIRECTION STRING "Add"
// Retrieval info: PRIVATE: ACCUM_SLOAD_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ACCUM_SLOAD_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ACCUM_SLOAD_PIPE_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ACCUM_SLOAD_PIPE_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ACCUM_SLOAD_PIPE_REG STRING "1"
// Retrieval info: PRIVATE: ACCUM_SLOAD_REG STRING "1"
// Retrieval info: PRIVATE: ADDNSUB1_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ADDNSUB1_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ADDNSUB1_PIPE_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ADDNSUB1_PIPE_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ADDNSUB1_PIPE_REG STRING "1"
// Retrieval info: PRIVATE: ADDNSUB1_REG STRING "1"
// Retrieval info: PRIVATE: ADDNSUB3_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ADDNSUB3_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ADDNSUB3_PIPE_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ADDNSUB3_PIPE_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ADDNSUB3_PIPE_REG STRING "1"
// Retrieval info: PRIVATE: ADDNSUB3_REG STRING "1"
// Retrieval info: PRIVATE: ADD_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: ALL_REG_ACLR NUMERIC "0"
// Retrieval info: PRIVATE: A_ACLR_SRC_MULT0 NUMERIC "3"
// Retrieval info: PRIVATE: A_CLK_SRC_MULT0 NUMERIC "0"
// Retrieval info: PRIVATE: B_ACLR_SRC_MULT0 NUMERIC "3"
// Retrieval info: PRIVATE: B_CLK_SRC_MULT0 NUMERIC "0"
// Retrieval info: PRIVATE: CHAINOUT_OUTPUT_ACLR NUMERIC "3"
// Retrieval info: PRIVATE: CHAINOUT_OUTPUT_REG STRING "0"
// Retrieval info: PRIVATE: CHAINOUT_OUTPUT_REGISTER NUMERIC "0"
// Retrieval info: PRIVATE: CHAINOUT_OUTPUT_REGISTERED NUMERIC "0"
// Retrieval info: PRIVATE: CHAS_ZERO_CHAINOUT NUMERIC "0"
// Retrieval info: PRIVATE: HAS_ACCUMULATOR NUMERIC "0"
// Retrieval info: PRIVATE: HAS_ACUMM_SLOAD NUMERIC "0"
// Retrieval info: PRIVATE: HAS_CHAININ_PORT NUMERIC "0"
// Retrieval info: PRIVATE: HAS_CHAINOUT_ADDER NUMERIC "0"
// Retrieval info: PRIVATE: HAS_LOOPBACK NUMERIC "1"
// Retrieval info: PRIVATE: HAS_MAC STRING "0"
// Retrieval info: PRIVATE: HAS_SAT_ROUND STRING "1"
// Retrieval info: PRIVATE: HAS_ZERO_LOOPBACK NUMERIC "0"
// Retrieval info: PRIVATE: IMPL_STYLE_DEDICATED NUMERIC "1"
// Retrieval info: PRIVATE: IMPL_STYLE_DEFAULT NUMERIC "0"
// Retrieval info: PRIVATE: IMPL_STYLE_LCELL NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
// Retrieval info: PRIVATE: MULT_REGA0 NUMERIC "1"
// Retrieval info: PRIVATE: MULT_REGB0 NUMERIC "1"
// Retrieval info: PRIVATE: MULT_REGOUT0 NUMERIC "1"
// Retrieval info: PRIVATE: NUM_MULT STRING "2"
// Retrieval info: PRIVATE: OP1 STRING "Add"
// Retrieval info: PRIVATE: OP3 STRING "Add"
// Retrieval info: PRIVATE: OUTPUT_EXTRA_LAT NUMERIC "0"
// Retrieval info: PRIVATE: OUTPUT_REG_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: OUTPUT_REG_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: Q_ACLR_SRC_MULT0 NUMERIC "3"
// Retrieval info: PRIVATE: Q_CLK_SRC_MULT0 NUMERIC "0"
// Retrieval info: PRIVATE: REG_OUT NUMERIC "1"
// Retrieval info: PRIVATE: RNFORMAT STRING "36"
// Retrieval info: PRIVATE: ROTATE_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ROTATE_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ROTATE_OUT_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ROTATE_OUT_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ROTATE_OUT_REG STRING "1"
// Retrieval info: PRIVATE: ROTATE_PIPE_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ROTATE_PIPE_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ROTATE_PIPE_REG STRING "1"
// Retrieval info: PRIVATE: ROTATE_REG STRING "1"
// Retrieval info: PRIVATE: ROUND3_CHAINOUT_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ROUND3_CHAINOUT_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ROUND3_CHAINOUT_MODE STRING "Enabled"
// Retrieval info: PRIVATE: ROUND3_CHAINOUT_OUT_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ROUND3_CHAINOUT_OUT_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ROUND3_CHAINOUT_OUT_REG STRING "0"
// Retrieval info: PRIVATE: ROUND3_CHAINOUT_PIPE_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ROUND3_CHAINOUT_PIPE_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ROUND3_CHAINOUT_PIPE_REG STRING "1"
// Retrieval info: PRIVATE: ROUND3_CHAINOUT_REG STRING "1"
// Retrieval info: PRIVATE: ROUND3_FRAC_WIDTH NUMERIC "18"
// Retrieval info: PRIVATE: ROUND3_OUTPUT_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ROUND3_OUTPUT_CHAINOUT_TYPE STRING "Nearest Integer"
// Retrieval info: PRIVATE: ROUND3_OUTPUT_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ROUND3_OUTPUT_MODE STRING "Disabled"
// Retrieval info: PRIVATE: ROUND3_OUTPUT_PIPE_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ROUND3_OUTPUT_PIPE_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ROUND3_OUTPUT_PIPE_REG STRING "1"
// Retrieval info: PRIVATE: ROUND3_OUTPUT_REG STRING "1"
// Retrieval info: PRIVATE: RQFORMAT STRING "Q1.15"
// Retrieval info: PRIVATE: RTS_WIDTH STRING "36"
// Retrieval info: PRIVATE: SAME_CONFIG NUMERIC "1"
// Retrieval info: PRIVATE: SAME_CONTROL_SRC_A0 NUMERIC "1"
// Retrieval info: PRIVATE: SAME_CONTROL_SRC_B0 NUMERIC "1"
// Retrieval info: PRIVATE: SAT3_CHAINOUT_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: SAT3_CHAINOUT_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: SAT3_CHAINOUT_MODE STRING "Enabled"
// Retrieval info: PRIVATE: SAT3_CHAINOUT_OUT_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: SAT3_CHAINOUT_OUT_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: SAT3_CHAINOUT_PIPE_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: SAT3_CHAINOUT_PIPE_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: SAT3_CHAINOUT_PIPE_REG STRING "1"
// Retrieval info: PRIVATE: SAT3_CHAINOUT_REG STRING "1"
// Retrieval info: PRIVATE: SAT3_FRAC_WIDTH NUMERIC "2"
// Retrieval info: PRIVATE: SAT3_OUTPUT_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: SAT3_OUTPUT_CHAINOUT_TYPE STRING "Symmetric"
// Retrieval info: PRIVATE: SAT3_OUTPUT_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: SAT3_OUTPUT_MODE STRING "Disabled"
// Retrieval info: PRIVATE: SAT3_OUTPUT_OVERFLOW NUMERIC "0"
// Retrieval info: PRIVATE: SAT3_OUTPUT_PIPE_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: SAT3_OUTPUT_PIPE_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: SAT3_OUTPUT_PIPE_REG STRING "1"
// Retrieval info: PRIVATE: SAT3_OUTPUT_REG STRING "1"
// Retrieval info: PRIVATE: SCANOUTA NUMERIC "0"
// Retrieval info: PRIVATE: SCANOUTB NUMERIC "0"
// Retrieval info: PRIVATE: SHIFTOUTA_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: SHIFTOUTA_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: SHIFTOUTA_REG STRING "0"
// Retrieval info: PRIVATE: SHIFT_RIGHT_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: SHIFT_RIGHT_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: SHIFT_RIGHT_OUT_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: SHIFT_RIGHT_OUT_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: SHIFT_RIGHT_OUT_REG STRING "1"
// Retrieval info: PRIVATE: SHIFT_RIGHT_PIPE_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: SHIFT_RIGHT_PIPE_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: SHIFT_RIGHT_PIPE_REG STRING "1"
// Retrieval info: PRIVATE: SHIFT_RIGHT_REG STRING "1"
// Retrieval info: PRIVATE: SHIFT_ROTATE_MODE STRING "None"
// Retrieval info: PRIVATE: SIGNA STRING "SIGNED"
// Retrieval info: PRIVATE: SIGNA_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: SIGNA_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: SIGNA_PIPE_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: SIGNA_PIPE_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: SIGNA_PIPE_REG STRING "1"
// Retrieval info: PRIVATE: SIGNA_REG STRING "1"
// Retrieval info: PRIVATE: SIGNB STRING "SIGNED"
// Retrieval info: PRIVATE: SIGNB_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: SIGNB_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: SIGNB_PIPE_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: SIGNB_PIPE_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: SIGNB_PIPE_REG STRING "1"
// Retrieval info: PRIVATE: SIGNB_REG STRING "1"
// Retrieval info: PRIVATE: SRCA0 STRING "Multiplier input"
// Retrieval info: PRIVATE: SRCB0 STRING "Multiplier input"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: WIDTHA STRING "18"
// Retrieval info: PRIVATE: WIDTHB STRING "18"
// Retrieval info: PRIVATE: ZERO_CHAINOUT_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ZERO_CHAINOUT_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_CHAINOUT_REG STRING "0"
// Retrieval info: PRIVATE: ZERO_LOOPBACK_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ZERO_LOOPBACK_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_LOOPBACK_OUT_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ZERO_LOOPBACK_OUT_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_LOOPBACK_OUT_REG STRING "1"
// Retrieval info: PRIVATE: ZERO_LOOPBACK_PIPE_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ZERO_LOOPBACK_PIPE_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_LOOPBACK_PIPE_REG STRING "1"
// Retrieval info: PRIVATE: ZERO_LOOPBACK_REG STRING "1"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ACCUMULATOR STRING "NO"
// Retrieval info: CONSTANT: ADDNSUB_MULTIPLIER_ACLR1 STRING "UNUSED"
// Retrieval info: CONSTANT: ADDNSUB_MULTIPLIER_PIPELINE_ACLR1 STRING "UNUSED"
// Retrieval info: CONSTANT: ADDNSUB_MULTIPLIER_PIPELINE_REGISTER1 STRING "CLOCK0"
// Retrieval info: CONSTANT: ADDNSUB_MULTIPLIER_REGISTER1 STRING "CLOCK0"
// Retrieval info: CONSTANT: CHAINOUT_ADDER STRING "NO"
// Retrieval info: CONSTANT: CHAINOUT_REGISTER STRING "UNREGISTERED"
// Retrieval info: CONSTANT: DEDICATED_MULTIPLIER_CIRCUITRY STRING "YES"
// Retrieval info: CONSTANT: INPUT_ACLR_A0 STRING "UNUSED"
// Retrieval info: CONSTANT: INPUT_ACLR_A1 STRING "UNUSED"
// Retrieval info: CONSTANT: INPUT_ACLR_B0 STRING "UNUSED"
// Retrieval info: CONSTANT: INPUT_ACLR_B1 STRING "UNUSED"
// Retrieval info: CONSTANT: INPUT_REGISTER_A0 STRING "CLOCK0"
// Retrieval info: CONSTANT: INPUT_REGISTER_A1 STRING "CLOCK0"
// Retrieval info: CONSTANT: INPUT_REGISTER_B0 STRING "CLOCK0"
// Retrieval info: CONSTANT: INPUT_REGISTER_B1 STRING "CLOCK0"
// Retrieval info: CONSTANT: INPUT_SOURCE_A0 STRING "DATAA"
// Retrieval info: CONSTANT: INPUT_SOURCE_A1 STRING "DATAA"
// Retrieval info: CONSTANT: INPUT_SOURCE_B0 STRING "LOOPBACK"
// Retrieval info: CONSTANT: INPUT_SOURCE_B1 STRING "DATAB"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altmult_add"
// Retrieval info: CONSTANT: MULTIPLIER1_DIRECTION STRING "ADD"
// Retrieval info: CONSTANT: MULTIPLIER_ACLR0 STRING "UNUSED"
// Retrieval info: CONSTANT: MULTIPLIER_ACLR1 STRING "UNUSED"
// Retrieval info: CONSTANT: MULTIPLIER_REGISTER0 STRING "CLOCK0"
// Retrieval info: CONSTANT: MULTIPLIER_REGISTER1 STRING "CLOCK0"
// Retrieval info: CONSTANT: NUMBER_OF_MULTIPLIERS NUMERIC "2"
// Retrieval info: CONSTANT: OUTPUT_ACLR STRING "UNUSED"
// Retrieval info: CONSTANT: OUTPUT_REGISTER STRING "CLOCK0"
// Retrieval info: CONSTANT: OUTPUT_ROUNDING STRING "NO"
// Retrieval info: CONSTANT: OUTPUT_ROUND_ACLR STRING "UNUSED"
// Retrieval info: CONSTANT: OUTPUT_ROUND_PIPELINE_ACLR STRING "UNUSED"
// Retrieval info: CONSTANT: OUTPUT_ROUND_PIPELINE_REGISTER STRING "CLOCK0"
// Retrieval info: CONSTANT: OUTPUT_ROUND_REGISTER STRING "CLOCK0"
// Retrieval info: CONSTANT: OUTPUT_ROUND_TYPE STRING "NEAREST_INTEGER"
// Retrieval info: CONSTANT: OUTPUT_SATURATE_ACLR STRING "UNUSED"
// Retrieval info: CONSTANT: OUTPUT_SATURATE_PIPELINE_ACLR STRING "UNUSED"
// Retrieval info: CONSTANT: OUTPUT_SATURATE_PIPELINE_REGISTER STRING "CLOCK0"
// Retrieval info: CONSTANT: OUTPUT_SATURATE_REGISTER STRING "CLOCK0"
// Retrieval info: CONSTANT: OUTPUT_SATURATE_TYPE STRING "SYMMETRIC"
// Retrieval info: CONSTANT: OUTPUT_SATURATION STRING "NO"
// Retrieval info: CONSTANT: PORT_ADDNSUB1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_OUTPUT_IS_OVERFLOW STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SIGNA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SIGNB STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: REPRESENTATION_A STRING "SIGNED"
// Retrieval info: CONSTANT: REPRESENTATION_B STRING "SIGNED"
// Retrieval info: CONSTANT: SIGNED_ACLR_A STRING "UNUSED"
// Retrieval info: CONSTANT: SIGNED_ACLR_B STRING "UNUSED"
// Retrieval info: CONSTANT: SIGNED_PIPELINE_ACLR_A STRING "UNUSED"
// Retrieval info: CONSTANT: SIGNED_PIPELINE_ACLR_B STRING "UNUSED"
// Retrieval info: CONSTANT: SIGNED_PIPELINE_REGISTER_A STRING "CLOCK0"
// Retrieval info: CONSTANT: SIGNED_PIPELINE_REGISTER_B STRING "CLOCK0"
// Retrieval info: CONSTANT: SIGNED_REGISTER_A STRING "CLOCK0"
// Retrieval info: CONSTANT: SIGNED_REGISTER_B STRING "CLOCK0"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "18"
// Retrieval info: CONSTANT: WIDTH_B NUMERIC "18"
// Retrieval info: CONSTANT: WIDTH_CHAININ NUMERIC "1"
// Retrieval info: CONSTANT: WIDTH_MSB NUMERIC "18"
// Retrieval info: CONSTANT: WIDTH_RESULT NUMERIC "36"
// Retrieval info: CONSTANT: WIDTH_SATURATE_SIGN NUMERIC "2"
// Retrieval info: CONSTANT: ZERO_CHAINOUT_OUTPUT_ACLR STRING "UNUSED"
// Retrieval info: CONSTANT: ZERO_CHAINOUT_OUTPUT_REGISTER STRING "CLOCK0"
// Retrieval info: CONSTANT: ZERO_LOOPBACK_ACLR STRING "UNUSED"
// Retrieval info: CONSTANT: ZERO_LOOPBACK_OUTPUT_ACLR STRING "UNUSED"
// Retrieval info: CONSTANT: ZERO_LOOPBACK_OUTPUT_REGISTER STRING "CLOCK0"
// Retrieval info: CONSTANT: ZERO_LOOPBACK_PIPELINE_ACLR STRING "UNUSED"
// Retrieval info: CONSTANT: ZERO_LOOPBACK_PIPELINE_REGISTER STRING "CLOCK0"
// Retrieval info: CONSTANT: ZERO_LOOPBACK_REGISTER STRING "CLOCK0"
// Retrieval info: USED_PORT: clock0 0 0 0 0 INPUT VCC "clock0"
// Retrieval info: USED_PORT: dataa_0 0 0 18 0 INPUT GND "dataa_0[17..0]"
// Retrieval info: USED_PORT: dataa_1 0 0 18 0 INPUT GND "dataa_1[17..0]"
// Retrieval info: USED_PORT: datab_1 0 0 18 0 INPUT GND "datab_1[17..0]"
// Retrieval info: USED_PORT: result 0 0 36 0 OUTPUT GND "result[35..0]"
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock0 0 0 0 0
// Retrieval info: CONNECT: @dataa 0 0 18 0 dataa_0 0 0 18 0
// Retrieval info: CONNECT: @dataa 0 0 18 18 dataa_1 0 0 18 0
// Retrieval info: CONNECT: @datab 0 0 18 18 GND 0 0 18 0
// Retrieval info: CONNECT: @datab 0 0 18 0 datab_1 0 0 18 0
// Retrieval info: CONNECT: result 0 0 36 0 @result 0 0 36 0
// Retrieval info: GEN_FILE: TYPE_NORMAL mult_loopback.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL mult_loopback.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL mult_loopback.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL mult_loopback.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL mult_loopback_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL mult_loopback_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
// megafunction wizard: %ALTMULT_ADD%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: ALTMULT_ADD
// ============================================================
// File Name: mult_loopback.v
// Megafunction Name(s):
// ALTMULT_ADD
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 12.0 Build 178 05/31/2012 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2012 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module mult_loopback (
clock0,
dataa_0,
dataa_1,
datab_1,
result);
input clock0;
input [17:0] dataa_0;
input [17:0] dataa_1;
input [17:0] datab_1;
output [35:0] result;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock0;
tri0 [17:0] dataa_0;
tri0 [17:0] dataa_1;
tri0 [17:0] datab_1;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ACCUM_DIRECTION STRING "Add"
// Retrieval info: PRIVATE: ACCUM_SLOAD_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ACCUM_SLOAD_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ACCUM_SLOAD_PIPE_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ACCUM_SLOAD_PIPE_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ACCUM_SLOAD_PIPE_REG STRING "1"
// Retrieval info: PRIVATE: ACCUM_SLOAD_REG STRING "1"
// Retrieval info: PRIVATE: ADDNSUB1_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ADDNSUB1_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ADDNSUB1_PIPE_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ADDNSUB1_PIPE_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ADDNSUB1_PIPE_REG STRING "1"
// Retrieval info: PRIVATE: ADDNSUB1_REG STRING "1"
// Retrieval info: PRIVATE: ADDNSUB3_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ADDNSUB3_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ADDNSUB3_PIPE_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ADDNSUB3_PIPE_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ADDNSUB3_PIPE_REG STRING "1"
// Retrieval info: PRIVATE: ADDNSUB3_REG STRING "1"
// Retrieval info: PRIVATE: ADD_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: ALL_REG_ACLR NUMERIC "0"
// Retrieval info: PRIVATE: A_ACLR_SRC_MULT0 NUMERIC "3"
// Retrieval info: PRIVATE: A_CLK_SRC_MULT0 NUMERIC "0"
// Retrieval info: PRIVATE: B_ACLR_SRC_MULT0 NUMERIC "3"
// Retrieval info: PRIVATE: B_CLK_SRC_MULT0 NUMERIC "0"
// Retrieval info: PRIVATE: CHAINOUT_OUTPUT_ACLR NUMERIC "3"
// Retrieval info: PRIVATE: CHAINOUT_OUTPUT_REG STRING "0"
// Retrieval info: PRIVATE: CHAINOUT_OUTPUT_REGISTER NUMERIC "0"
// Retrieval info: PRIVATE: CHAINOUT_OUTPUT_REGISTERED NUMERIC "0"
// Retrieval info: PRIVATE: CHAS_ZERO_CHAINOUT NUMERIC "0"
// Retrieval info: PRIVATE: HAS_ACCUMULATOR NUMERIC "0"
// Retrieval info: PRIVATE: HAS_ACUMM_SLOAD NUMERIC "0"
// Retrieval info: PRIVATE: HAS_CHAININ_PORT NUMERIC "0"
// Retrieval info: PRIVATE: HAS_CHAINOUT_ADDER NUMERIC "0"
// Retrieval info: PRIVATE: HAS_LOOPBACK NUMERIC "1"
// Retrieval info: PRIVATE: HAS_MAC STRING "0"
// Retrieval info: PRIVATE: HAS_SAT_ROUND STRING "1"
// Retrieval info: PRIVATE: HAS_ZERO_LOOPBACK NUMERIC "0"
// Retrieval info: PRIVATE: IMPL_STYLE_DEDICATED NUMERIC "1"
// Retrieval info: PRIVATE: IMPL_STYLE_DEFAULT NUMERIC "0"
// Retrieval info: PRIVATE: IMPL_STYLE_LCELL NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
// Retrieval info: PRIVATE: MULT_REGA0 NUMERIC "1"
// Retrieval info: PRIVATE: MULT_REGB0 NUMERIC "1"
// Retrieval info: PRIVATE: MULT_REGOUT0 NUMERIC "1"
// Retrieval info: PRIVATE: NUM_MULT STRING "2"
// Retrieval info: PRIVATE: OP1 STRING "Add"
// Retrieval info: PRIVATE: OP3 STRING "Add"
// Retrieval info: PRIVATE: OUTPUT_EXTRA_LAT NUMERIC "0"
// Retrieval info: PRIVATE: OUTPUT_REG_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: OUTPUT_REG_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: Q_ACLR_SRC_MULT0 NUMERIC "3"
// Retrieval info: PRIVATE: Q_CLK_SRC_MULT0 NUMERIC "0"
// Retrieval info: PRIVATE: REG_OUT NUMERIC "1"
// Retrieval info: PRIVATE: RNFORMAT STRING "36"
// Retrieval info: PRIVATE: ROTATE_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ROTATE_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ROTATE_OUT_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ROTATE_OUT_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ROTATE_OUT_REG STRING "1"
// Retrieval info: PRIVATE: ROTATE_PIPE_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ROTATE_PIPE_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ROTATE_PIPE_REG STRING "1"
// Retrieval info: PRIVATE: ROTATE_REG STRING "1"
// Retrieval info: PRIVATE: ROUND3_CHAINOUT_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ROUND3_CHAINOUT_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ROUND3_CHAINOUT_MODE STRING "Enabled"
// Retrieval info: PRIVATE: ROUND3_CHAINOUT_OUT_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ROUND3_CHAINOUT_OUT_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ROUND3_CHAINOUT_OUT_REG STRING "0"
// Retrieval info: PRIVATE: ROUND3_CHAINOUT_PIPE_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ROUND3_CHAINOUT_PIPE_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ROUND3_CHAINOUT_PIPE_REG STRING "1"
// Retrieval info: PRIVATE: ROUND3_CHAINOUT_REG STRING "1"
// Retrieval info: PRIVATE: ROUND3_FRAC_WIDTH NUMERIC "18"
// Retrieval info: PRIVATE: ROUND3_OUTPUT_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ROUND3_OUTPUT_CHAINOUT_TYPE STRING "Nearest Integer"
// Retrieval info: PRIVATE: ROUND3_OUTPUT_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ROUND3_OUTPUT_MODE STRING "Disabled"
// Retrieval info: PRIVATE: ROUND3_OUTPUT_PIPE_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ROUND3_OUTPUT_PIPE_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ROUND3_OUTPUT_PIPE_REG STRING "1"
// Retrieval info: PRIVATE: ROUND3_OUTPUT_REG STRING "1"
// Retrieval info: PRIVATE: RQFORMAT STRING "Q1.15"
// Retrieval info: PRIVATE: RTS_WIDTH STRING "36"
// Retrieval info: PRIVATE: SAME_CONFIG NUMERIC "1"
// Retrieval info: PRIVATE: SAME_CONTROL_SRC_A0 NUMERIC "1"
// Retrieval info: PRIVATE: SAME_CONTROL_SRC_B0 NUMERIC "1"
// Retrieval info: PRIVATE: SAT3_CHAINOUT_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: SAT3_CHAINOUT_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: SAT3_CHAINOUT_MODE STRING "Enabled"
// Retrieval info: PRIVATE: SAT3_CHAINOUT_OUT_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: SAT3_CHAINOUT_OUT_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: SAT3_CHAINOUT_PIPE_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: SAT3_CHAINOUT_PIPE_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: SAT3_CHAINOUT_PIPE_REG STRING "1"
// Retrieval info: PRIVATE: SAT3_CHAINOUT_REG STRING "1"
// Retrieval info: PRIVATE: SAT3_FRAC_WIDTH NUMERIC "2"
// Retrieval info: PRIVATE: SAT3_OUTPUT_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: SAT3_OUTPUT_CHAINOUT_TYPE STRING "Symmetric"
// Retrieval info: PRIVATE: SAT3_OUTPUT_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: SAT3_OUTPUT_MODE STRING "Disabled"
// Retrieval info: PRIVATE: SAT3_OUTPUT_OVERFLOW NUMERIC "0"
// Retrieval info: PRIVATE: SAT3_OUTPUT_PIPE_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: SAT3_OUTPUT_PIPE_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: SAT3_OUTPUT_PIPE_REG STRING "1"
// Retrieval info: PRIVATE: SAT3_OUTPUT_REG STRING "1"
// Retrieval info: PRIVATE: SCANOUTA NUMERIC "0"
// Retrieval info: PRIVATE: SCANOUTB NUMERIC "0"
// Retrieval info: PRIVATE: SHIFTOUTA_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: SHIFTOUTA_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: SHIFTOUTA_REG STRING "0"
// Retrieval info: PRIVATE: SHIFT_RIGHT_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: SHIFT_RIGHT_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: SHIFT_RIGHT_OUT_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: SHIFT_RIGHT_OUT_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: SHIFT_RIGHT_OUT_REG STRING "1"
// Retrieval info: PRIVATE: SHIFT_RIGHT_PIPE_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: SHIFT_RIGHT_PIPE_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: SHIFT_RIGHT_PIPE_REG STRING "1"
// Retrieval info: PRIVATE: SHIFT_RIGHT_REG STRING "1"
// Retrieval info: PRIVATE: SHIFT_ROTATE_MODE STRING "None"
// Retrieval info: PRIVATE: SIGNA STRING "SIGNED"
// Retrieval info: PRIVATE: SIGNA_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: SIGNA_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: SIGNA_PIPE_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: SIGNA_PIPE_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: SIGNA_PIPE_REG STRING "1"
// Retrieval info: PRIVATE: SIGNA_REG STRING "1"
// Retrieval info: PRIVATE: SIGNB STRING "SIGNED"
// Retrieval info: PRIVATE: SIGNB_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: SIGNB_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: SIGNB_PIPE_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: SIGNB_PIPE_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: SIGNB_PIPE_REG STRING "1"
// Retrieval info: PRIVATE: SIGNB_REG STRING "1"
// Retrieval info: PRIVATE: SRCA0 STRING "Multiplier input"
// Retrieval info: PRIVATE: SRCB0 STRING "Multiplier input"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: WIDTHA STRING "18"
// Retrieval info: PRIVATE: WIDTHB STRING "18"
// Retrieval info: PRIVATE: ZERO_CHAINOUT_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ZERO_CHAINOUT_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_CHAINOUT_REG STRING "0"
// Retrieval info: PRIVATE: ZERO_LOOPBACK_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ZERO_LOOPBACK_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_LOOPBACK_OUT_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ZERO_LOOPBACK_OUT_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_LOOPBACK_OUT_REG STRING "1"
// Retrieval info: PRIVATE: ZERO_LOOPBACK_PIPE_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ZERO_LOOPBACK_PIPE_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_LOOPBACK_PIPE_REG STRING "1"
// Retrieval info: PRIVATE: ZERO_LOOPBACK_REG STRING "1"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ACCUMULATOR STRING "NO"
// Retrieval info: CONSTANT: ADDNSUB_MULTIPLIER_ACLR1 STRING "UNUSED"
// Retrieval info: CONSTANT: ADDNSUB_MULTIPLIER_PIPELINE_ACLR1 STRING "UNUSED"
// Retrieval info: CONSTANT: ADDNSUB_MULTIPLIER_PIPELINE_REGISTER1 STRING "CLOCK0"
// Retrieval info: CONSTANT: ADDNSUB_MULTIPLIER_REGISTER1 STRING "CLOCK0"
// Retrieval info: CONSTANT: CHAINOUT_ADDER STRING "NO"
// Retrieval info: CONSTANT: CHAINOUT_REGISTER STRING "UNREGISTERED"
// Retrieval info: CONSTANT: DEDICATED_MULTIPLIER_CIRCUITRY STRING "YES"
// Retrieval info: CONSTANT: INPUT_ACLR_A0 STRING "UNUSED"
// Retrieval info: CONSTANT: INPUT_ACLR_A1 STRING "UNUSED"
// Retrieval info: CONSTANT: INPUT_ACLR_B0 STRING "UNUSED"
// Retrieval info: CONSTANT: INPUT_ACLR_B1 STRING "UNUSED"
// Retrieval info: CONSTANT: INPUT_REGISTER_A0 STRING "CLOCK0"
// Retrieval info: CONSTANT: INPUT_REGISTER_A1 STRING "CLOCK0"
// Retrieval info: CONSTANT: INPUT_REGISTER_B0 STRING "CLOCK0"
// Retrieval info: CONSTANT: INPUT_REGISTER_B1 STRING "CLOCK0"
// Retrieval info: CONSTANT: INPUT_SOURCE_A0 STRING "DATAA"
// Retrieval info: CONSTANT: INPUT_SOURCE_A1 STRING "DATAA"
// Retrieval info: CONSTANT: INPUT_SOURCE_B0 STRING "LOOPBACK"
// Retrieval info: CONSTANT: INPUT_SOURCE_B1 STRING "DATAB"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altmult_add"
// Retrieval info: CONSTANT: MULTIPLIER1_DIRECTION STRING "ADD"
// Retrieval info: CONSTANT: MULTIPLIER_ACLR0 STRING "UNUSED"
// Retrieval info: CONSTANT: MULTIPLIER_ACLR1 STRING "UNUSED"
// Retrieval info: CONSTANT: MULTIPLIER_REGISTER0 STRING "CLOCK0"
// Retrieval info: CONSTANT: MULTIPLIER_REGISTER1 STRING "CLOCK0"
// Retrieval info: CONSTANT: NUMBER_OF_MULTIPLIERS NUMERIC "2"
// Retrieval info: CONSTANT: OUTPUT_ACLR STRING "UNUSED"
// Retrieval info: CONSTANT: OUTPUT_REGISTER STRING "CLOCK0"
// Retrieval info: CONSTANT: OUTPUT_ROUNDING STRING "NO"
// Retrieval info: CONSTANT: OUTPUT_ROUND_ACLR STRING "UNUSED"
// Retrieval info: CONSTANT: OUTPUT_ROUND_PIPELINE_ACLR STRING "UNUSED"
// Retrieval info: CONSTANT: OUTPUT_ROUND_PIPELINE_REGISTER STRING "CLOCK0"
// Retrieval info: CONSTANT: OUTPUT_ROUND_REGISTER STRING "CLOCK0"
// Retrieval info: CONSTANT: OUTPUT_ROUND_TYPE STRING "NEAREST_INTEGER"
// Retrieval info: CONSTANT: OUTPUT_SATURATE_ACLR STRING "UNUSED"
// Retrieval info: CONSTANT: OUTPUT_SATURATE_PIPELINE_ACLR STRING "UNUSED"
// Retrieval info: CONSTANT: OUTPUT_SATURATE_PIPELINE_REGISTER STRING "CLOCK0"
// Retrieval info: CONSTANT: OUTPUT_SATURATE_REGISTER STRING "CLOCK0"
// Retrieval info: CONSTANT: OUTPUT_SATURATE_TYPE STRING "SYMMETRIC"
// Retrieval info: CONSTANT: OUTPUT_SATURATION STRING "NO"
// Retrieval info: CONSTANT: PORT_ADDNSUB1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_OUTPUT_IS_OVERFLOW STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SIGNA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SIGNB STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: REPRESENTATION_A STRING "SIGNED"
// Retrieval info: CONSTANT: REPRESENTATION_B STRING "SIGNED"
// Retrieval info: CONSTANT: SIGNED_ACLR_A STRING "UNUSED"
// Retrieval info: CONSTANT: SIGNED_ACLR_B STRING "UNUSED"
// Retrieval info: CONSTANT: SIGNED_PIPELINE_ACLR_A STRING "UNUSED"
// Retrieval info: CONSTANT: SIGNED_PIPELINE_ACLR_B STRING "UNUSED"
// Retrieval info: CONSTANT: SIGNED_PIPELINE_REGISTER_A STRING "CLOCK0"
// Retrieval info: CONSTANT: SIGNED_PIPELINE_REGISTER_B STRING "CLOCK0"
// Retrieval info: CONSTANT: SIGNED_REGISTER_A STRING "CLOCK0"
// Retrieval info: CONSTANT: SIGNED_REGISTER_B STRING "CLOCK0"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "18"
// Retrieval info: CONSTANT: WIDTH_B NUMERIC "18"
// Retrieval info: CONSTANT: WIDTH_CHAININ NUMERIC "1"
// Retrieval info: CONSTANT: WIDTH_MSB NUMERIC "18"
// Retrieval info: CONSTANT: WIDTH_RESULT NUMERIC "36"
// Retrieval info: CONSTANT: WIDTH_SATURATE_SIGN NUMERIC "2"
// Retrieval info: CONSTANT: ZERO_CHAINOUT_OUTPUT_ACLR STRING "UNUSED"
// Retrieval info: CONSTANT: ZERO_CHAINOUT_OUTPUT_REGISTER STRING "CLOCK0"
// Retrieval info: CONSTANT: ZERO_LOOPBACK_ACLR STRING "UNUSED"
// Retrieval info: CONSTANT: ZERO_LOOPBACK_OUTPUT_ACLR STRING "UNUSED"
// Retrieval info: CONSTANT: ZERO_LOOPBACK_OUTPUT_REGISTER STRING "CLOCK0"
// Retrieval info: CONSTANT: ZERO_LOOPBACK_PIPELINE_ACLR STRING "UNUSED"
// Retrieval info: CONSTANT: ZERO_LOOPBACK_PIPELINE_REGISTER STRING "CLOCK0"
// Retrieval info: CONSTANT: ZERO_LOOPBACK_REGISTER STRING "CLOCK0"
// Retrieval info: USED_PORT: clock0 0 0 0 0 INPUT VCC "clock0"
// Retrieval info: USED_PORT: dataa_0 0 0 18 0 INPUT GND "dataa_0[17..0]"
// Retrieval info: USED_PORT: dataa_1 0 0 18 0 INPUT GND "dataa_1[17..0]"
// Retrieval info: USED_PORT: datab_1 0 0 18 0 INPUT GND "datab_1[17..0]"
// Retrieval info: USED_PORT: result 0 0 36 0 OUTPUT GND "result[35..0]"
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock0 0 0 0 0
// Retrieval info: CONNECT: @dataa 0 0 18 0 dataa_0 0 0 18 0
// Retrieval info: CONNECT: @dataa 0 0 18 18 dataa_1 0 0 18 0
// Retrieval info: CONNECT: @datab 0 0 18 18 GND 0 0 18 0
// Retrieval info: CONNECT: @datab 0 0 18 0 datab_1 0 0 18 0
// Retrieval info: CONNECT: result 0 0 36 0 @result 0 0 36 0
// Retrieval info: GEN_FILE: TYPE_NORMAL mult_loopback.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL mult_loopback.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL mult_loopback.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL mult_loopback.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL mult_loopback_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL mult_loopback_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
mult_loopback mult_loopback_inst (
.clock0 ( clock0_sig ),
.dataa_0 ( dataa_0_sig ),
.dataa_1 ( dataa_1_sig ),
.datab_1 ( datab_1_sig ),
.result ( result_sig )
);
|
// megafunction wizard: %ALTMULT_ACCUM (MAC)%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altmult_add
// ============================================================
// File Name: scanout_chain_megafn.v
// Megafunction Name(s):
// altmult_add
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 12.0 Build 178 05/31/2012 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2012 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module scanout_chain_megafn (
clock0,
dataa_0,
datab_0,
datab_1,
datab_2,
datab_3,
result,
shiftouta);
input clock0;
input [17:0] dataa_0;
input [17:0] datab_0;
input [17:0] datab_1;
input [17:0] datab_2;
input [17:0] datab_3;
output [43:0] result;
output [17:0] shiftouta;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock0;
tri0 [17:0] dataa_0;
tri0 [17:0] datab_0;
tri0 [17:0] datab_1;
tri0 [17:0] datab_2;
tri0 [17:0] datab_3;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [43:0] sub_wire0;
wire [17:0] sub_wire1;
wire [17:0] sub_wire9 = 18'h0;
wire [17:0] sub_wire6 = datab_3[17:0];
wire [17:0] sub_wire5 = datab_2[17:0];
wire [17:0] sub_wire4 = datab_1[17:0];
wire [43:0] result = sub_wire0[43:0];
wire [17:0] shiftouta = sub_wire1[17:0];
wire [17:0] sub_wire2 = datab_0[17:0];
wire [71:0] sub_wire3 = {sub_wire6, sub_wire5, sub_wire4, sub_wire2};
wire [17:0] sub_wire7 = dataa_0[17:0];
wire [71:0] sub_wire8 = {sub_wire9, sub_wire9, sub_wire9, sub_wire7};
altmult_add altmult_add_component (
.clock0 (clock0),
.datab (sub_wire3),
.dataa (sub_wire8),
.result (sub_wire0),
.scanouta (sub_wire1),
.accum_sload (1'b0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.aclr2 (1'b0),
.aclr3 (1'b0),
.addnsub1 (1'b1),
.addnsub1_round (1'b0),
.addnsub3 (1'b1),
.addnsub3_round (1'b0),
.chainin (1'b0),
.chainout_round (1'b0),
.chainout_sat_overflow (),
.chainout_saturate (1'b0),
.clock1 (1'b1),
.clock2 (1'b1),
.clock3 (1'b1),
.coefsel0 ({3{1'b0}}),
.coefsel1 ({3{1'b0}}),
.coefsel2 ({3{1'b0}}),
.coefsel3 ({3{1'b0}}),
.datac ({88{1'b0}}),
.ena0 (1'b1),
.ena1 (1'b1),
.ena2 (1'b1),
.ena3 (1'b1),
.mult01_round (1'b0),
.mult01_saturation (1'b0),
.mult0_is_saturated (),
.mult1_is_saturated (),
.mult23_round (1'b0),
.mult23_saturation (1'b0),
.mult2_is_saturated (),
.mult3_is_saturated (),
.output_round (1'b0),
.output_saturate (1'b0),
.overflow (),
.rotate (1'b0),
.scanina ({18{1'b0}}),
.scaninb ({18{1'b0}}),
.scanoutb (),
.shift_right (1'b0),
.signa (1'b0),
.signb (1'b0),
.sourcea ({4{1'b0}}),
.sourceb ({4{1'b0}}),
.zero_chainout (1'b0),
.zero_loopback (1'b0));
defparam
altmult_add_component.accumulator = "YES",
altmult_add_component.accum_direction = "ADD",
altmult_add_component.addnsub_multiplier_aclr1 = "UNUSED",
altmult_add_component.addnsub_multiplier_aclr3 = "UNUSED",
altmult_add_component.addnsub_multiplier_pipeline_aclr1 = "UNUSED",
altmult_add_component.addnsub_multiplier_pipeline_aclr3 = "UNUSED",
altmult_add_component.addnsub_multiplier_pipeline_register1 = "CLOCK0",
altmult_add_component.addnsub_multiplier_pipeline_register3 = "CLOCK0",
altmult_add_component.addnsub_multiplier_register1 = "CLOCK0",
altmult_add_component.addnsub_multiplier_register3 = "CLOCK0",
altmult_add_component.chainout_adder = "NO",
altmult_add_component.chainout_register = "UNREGISTERED",
altmult_add_component.dedicated_multiplier_circuitry = "YES",
altmult_add_component.input_aclr_a0 = "UNUSED",
altmult_add_component.input_aclr_a1 = "UNUSED",
altmult_add_component.input_aclr_a2 = "UNUSED",
altmult_add_component.input_aclr_a3 = "UNUSED",
altmult_add_component.input_aclr_b0 = "UNUSED",
altmult_add_component.input_aclr_b1 = "UNUSED",
altmult_add_component.input_aclr_b2 = "UNUSED",
altmult_add_component.input_aclr_b3 = "UNUSED",
altmult_add_component.input_register_a0 = "CLOCK0",
altmult_add_component.input_register_a1 = "CLOCK0",
altmult_add_component.input_register_a2 = "CLOCK0",
altmult_add_component.input_register_a3 = "CLOCK0",
altmult_add_component.input_register_b0 = "CLOCK0",
altmult_add_component.input_register_b1 = "CLOCK0",
altmult_add_component.input_register_b2 = "CLOCK0",
altmult_add_component.input_register_b3 = "CLOCK0",
altmult_add_component.input_source_a0 = "DATAA",
altmult_add_component.input_source_a1 = "SCANA",
altmult_add_component.input_source_a2 = "SCANA",
altmult_add_component.input_source_a3 = "SCANA",
altmult_add_component.input_source_b0 = "DATAB",
altmult_add_component.input_source_b1 = "DATAB",
altmult_add_component.input_source_b2 = "DATAB",
altmult_add_component.input_source_b3 = "DATAB",
altmult_add_component.intended_device_family = "Stratix IV",
altmult_add_component.lpm_type = "altmult_add",
altmult_add_component.multiplier1_direction = "ADD",
altmult_add_component.multiplier3_direction = "ADD",
altmult_add_component.multiplier_aclr0 = "UNUSED",
altmult_add_component.multiplier_aclr1 = "UNUSED",
altmult_add_component.multiplier_aclr2 = "UNUSED",
altmult_add_component.multiplier_aclr3 = "UNUSED",
altmult_add_component.multiplier_register0 = "CLOCK0",
altmult_add_component.multiplier_register1 = "CLOCK0",
altmult_add_component.multiplier_register2 = "CLOCK0",
altmult_add_component.multiplier_register3 = "CLOCK0",
altmult_add_component.number_of_multipliers = 4,
altmult_add_component.output_aclr = "UNUSED",
altmult_add_component.output_register = "CLOCK0",
altmult_add_component.output_round_type = "NEAREST_INTEGER",
altmult_add_component.output_saturate_aclr = "UNUSED",
altmult_add_component.output_saturate_pipeline_aclr = "UNUSED",
altmult_add_component.output_saturate_pipeline_register = "CLOCK0",
altmult_add_component.output_saturate_register = "CLOCK0",
altmult_add_component.output_saturate_type = "SYMMETRIC",
altmult_add_component.output_saturation = "YES",
altmult_add_component.port_addnsub1 = "PORT_UNUSED",
altmult_add_component.port_addnsub3 = "PORT_UNUSED",
altmult_add_component.port_signa = "PORT_UNUSED",
altmult_add_component.port_signb = "PORT_UNUSED",
altmult_add_component.representation_a = "SIGNED",
altmult_add_component.representation_b = "SIGNED",
altmult_add_component.scanouta_register = "UNREGISTERED",
altmult_add_component.signed_aclr_a = "UNUSED",
altmult_add_component.signed_aclr_b = "UNUSED",
altmult_add_component.signed_pipeline_aclr_a = "UNUSED",
altmult_add_component.signed_pipeline_aclr_b = "UNUSED",
altmult_add_component.signed_pipeline_register_a = "CLOCK0",
altmult_add_component.signed_pipeline_register_b = "CLOCK0",
altmult_add_component.signed_register_a = "CLOCK0",
altmult_add_component.signed_register_b = "CLOCK0",
altmult_add_component.width_a = 18,
altmult_add_component.width_b = 18,
altmult_add_component.width_chainin = 1,
altmult_add_component.width_msb = 44,
altmult_add_component.width_result = 44,
altmult_add_component.width_saturate_sign = 1,
altmult_add_component.zero_chainout_output_aclr = "UNUSED",
altmult_add_component.zero_chainout_output_register = "CLOCK0",
altmult_add_component.zero_loopback_aclr = "UNUSED",
altmult_add_component.zero_loopback_output_aclr = "UNUSED",
altmult_add_component.zero_loopback_output_register = "CLOCK0",
altmult_add_component.zero_loopback_pipeline_aclr = "UNUSED",
altmult_add_component.zero_loopback_pipeline_register = "CLOCK0",
altmult_add_component.zero_loopback_register = "CLOCK0";
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ACCUM_DIRECTION STRING "Add"
// Retrieval info: PRIVATE: ACCUM_SLOAD NUMERIC "0"
// Retrieval info: PRIVATE: ACCUM_SLOAD_ACLR NUMERIC "3"
// Retrieval info: PRIVATE: ACCUM_SLOAD_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ACCUM_SLOAD_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ACCUM_SLOAD_PIPELINE_ACLR NUMERIC "3"
// Retrieval info: PRIVATE: ACCUM_SLOAD_PIPELINE_REG NUMERIC "1"
// Retrieval info: PRIVATE: ACCUM_SLOAD_PIPELINE_REG_INDEX NUMERIC "0"
// Retrieval info: PRIVATE: ACCUM_SLOAD_PIPE_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ACCUM_SLOAD_PIPE_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ACCUM_SLOAD_PIPE_REG STRING "1"
// Retrieval info: PRIVATE: ACCUM_SLOAD_REG NUMERIC "1"
// Retrieval info: PRIVATE: ACCUM_SLOAD_REG_INDEX NUMERIC "0"
// Retrieval info: PRIVATE: ACCUM_SLOAD_UPPER_DATA NUMERIC "0"
// Retrieval info: PRIVATE: ACCUM_SLOAD_UPPER_DATA_ACLR NUMERIC "3"
// Retrieval info: PRIVATE: ACCUM_SLOAD_UPPER_DATA_PIPELINE_ACLR NUMERIC "3"
// Retrieval info: PRIVATE: ACCUM_SLOAD_UPPER_DATA_PIPELINE_REG NUMERIC "0"
// Retrieval info: PRIVATE: ACCUM_SLOAD_UPPER_DATA_REG NUMERIC "0"
// Retrieval info: PRIVATE: ADDNSUB1_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ADDNSUB1_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ADDNSUB1_PIPE_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ADDNSUB1_PIPE_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ADDNSUB1_PIPE_REG STRING "1"
// Retrieval info: PRIVATE: ADDNSUB1_REG STRING "1"
// Retrieval info: PRIVATE: ADDNSUB3_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ADDNSUB3_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ADDNSUB3_PIPE_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ADDNSUB3_PIPE_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ADDNSUB3_PIPE_REG STRING "1"
// Retrieval info: PRIVATE: ADDNSUB3_REG STRING "1"
// Retrieval info: PRIVATE: ADD_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: ALL_REG_ACLR NUMERIC "0"
// Retrieval info: PRIVATE: A_ACLR_SRC_MULT0 NUMERIC "3"
// Retrieval info: PRIVATE: A_CLK_SRC_MULT0 NUMERIC "0"
// Retrieval info: PRIVATE: B_ACLR_SRC_MULT0 NUMERIC "3"
// Retrieval info: PRIVATE: B_CLK_SRC_MULT0 NUMERIC "0"
// Retrieval info: PRIVATE: CHAINOUT_OUTPUT_ACLR NUMERIC "3"
// Retrieval info: PRIVATE: CHAINOUT_OUTPUT_REG STRING "0"
// Retrieval info: PRIVATE: CHAINOUT_OUTPUT_REGISTER NUMERIC "0"
// Retrieval info: PRIVATE: CHAINOUT_OUTPUT_REGISTERED NUMERIC "0"
// Retrieval info: PRIVATE: CHAS_ZERO_CHAINOUT NUMERIC "0"
// Retrieval info: PRIVATE: EXTRA_MULTIPLIER_LATENCY NUMERIC "0"
// Retrieval info: PRIVATE: HAS_ACCUMULATOR NUMERIC "1"
// Retrieval info: PRIVATE: HAS_ACUMM_SLOAD NUMERIC "0"
// Retrieval info: PRIVATE: HAS_CHAININ_PORT NUMERIC "0"
// Retrieval info: PRIVATE: HAS_CHAINOUT_ADDER NUMERIC "0"
// Retrieval info: PRIVATE: HAS_LOOPBACK NUMERIC "0"
// Retrieval info: PRIVATE: HAS_MAC STRING "1"
// Retrieval info: PRIVATE: HAS_SAT_ROUND STRING "1"
// Retrieval info: PRIVATE: HAS_ZERO_LOOPBACK NUMERIC "0"
// Retrieval info: PRIVATE: IMPL_STYLE_DEDICATED NUMERIC "1"
// Retrieval info: PRIVATE: IMPL_STYLE_DEFAULT NUMERIC "0"
// Retrieval info: PRIVATE: IMPL_STYLE_LCELL NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
// Retrieval info: PRIVATE: MULT_LATENCY NUMERIC "0"
// Retrieval info: PRIVATE: MULT_REGA0 NUMERIC "1"
// Retrieval info: PRIVATE: MULT_REGB0 NUMERIC "1"
// Retrieval info: PRIVATE: MULT_REGOUT0 NUMERIC "1"
// Retrieval info: PRIVATE: NUM_MULT STRING "4"
// Retrieval info: PRIVATE: OP1 STRING "Add"
// Retrieval info: PRIVATE: OP3 STRING "Add"
// Retrieval info: PRIVATE: OUTPUT_EXTRA_LAT NUMERIC "0"
// Retrieval info: PRIVATE: OUTPUT_REG_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: OUTPUT_REG_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW NUMERIC "0"
// Retrieval info: PRIVATE: Q_ACLR_SRC_MULT0 NUMERIC "3"
// Retrieval info: PRIVATE: Q_CLK_SRC_MULT0 NUMERIC "0"
// Retrieval info: PRIVATE: REG_OUT NUMERIC "1"
// Retrieval info: PRIVATE: RNFORMAT STRING "44"
// Retrieval info: PRIVATE: ROTATE_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ROTATE_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ROTATE_OUT_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ROTATE_OUT_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ROTATE_OUT_REG STRING "1"
// Retrieval info: PRIVATE: ROTATE_PIPE_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ROTATE_PIPE_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ROTATE_PIPE_REG STRING "1"
// Retrieval info: PRIVATE: ROTATE_REG STRING "1"
// Retrieval info: PRIVATE: ROUND3_CHAINOUT_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ROUND3_CHAINOUT_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ROUND3_CHAINOUT_MODE STRING "Disabled"
// Retrieval info: PRIVATE: ROUND3_CHAINOUT_OUT_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ROUND3_CHAINOUT_OUT_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ROUND3_CHAINOUT_OUT_REG STRING "0"
// Retrieval info: PRIVATE: ROUND3_CHAINOUT_PIPE_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ROUND3_CHAINOUT_PIPE_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ROUND3_CHAINOUT_PIPE_REG STRING "1"
// Retrieval info: PRIVATE: ROUND3_CHAINOUT_REG STRING "1"
// Retrieval info: PRIVATE: ROUND3_FRAC_WIDTH NUMERIC "23"
// Retrieval info: PRIVATE: ROUND3_OUTPUT_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ROUND3_OUTPUT_CHAINOUT_TYPE STRING "Nearest Integer"
// Retrieval info: PRIVATE: ROUND3_OUTPUT_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ROUND3_OUTPUT_MODE STRING "Disabled"
// Retrieval info: PRIVATE: ROUND3_OUTPUT_PIPE_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ROUND3_OUTPUT_PIPE_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ROUND3_OUTPUT_PIPE_REG STRING "1"
// Retrieval info: PRIVATE: ROUND3_OUTPUT_REG STRING "1"
// Retrieval info: PRIVATE: RQFORMAT STRING "Q1.30"
// Retrieval info: PRIVATE: RTS_WIDTH STRING "44"
// Retrieval info: PRIVATE: SAME_CONFIG NUMERIC "1"
// Retrieval info: PRIVATE: SAME_CONTROL_SRC_A0 NUMERIC "1"
// Retrieval info: PRIVATE: SAME_CONTROL_SRC_B0 NUMERIC "1"
// Retrieval info: PRIVATE: SAT3_CHAINOUT_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: SAT3_CHAINOUT_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: SAT3_CHAINOUT_MODE STRING "Enabled"
// Retrieval info: PRIVATE: SAT3_CHAINOUT_OUT_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: SAT3_CHAINOUT_OUT_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: SAT3_CHAINOUT_PIPE_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: SAT3_CHAINOUT_PIPE_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: SAT3_CHAINOUT_PIPE_REG STRING "1"
// Retrieval info: PRIVATE: SAT3_CHAINOUT_REG STRING "1"
// Retrieval info: PRIVATE: SAT3_FRAC_WIDTH NUMERIC "1"
// Retrieval info: PRIVATE: SAT3_OUTPUT_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: SAT3_OUTPUT_CHAINOUT_TYPE STRING "Symmetric"
// Retrieval info: PRIVATE: SAT3_OUTPUT_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: SAT3_OUTPUT_MODE STRING "Enabled"
// Retrieval info: PRIVATE: SAT3_OUTPUT_OVERFLOW NUMERIC "0"
// Retrieval info: PRIVATE: SAT3_OUTPUT_PIPE_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: SAT3_OUTPUT_PIPE_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: SAT3_OUTPUT_PIPE_REG STRING "1"
// Retrieval info: PRIVATE: SAT3_OUTPUT_REG STRING "1"
// Retrieval info: PRIVATE: SCANOUTA NUMERIC "1"
// Retrieval info: PRIVATE: SCANOUTB NUMERIC "0"
// Retrieval info: PRIVATE: SHIFTOUTA_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: SHIFTOUTA_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: SHIFTOUTA_REG STRING "0"
// Retrieval info: PRIVATE: SHIFT_RIGHT_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: SHIFT_RIGHT_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: SHIFT_RIGHT_OUT_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: SHIFT_RIGHT_OUT_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: SHIFT_RIGHT_OUT_REG STRING "1"
// Retrieval info: PRIVATE: SHIFT_RIGHT_PIPE_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: SHIFT_RIGHT_PIPE_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: SHIFT_RIGHT_PIPE_REG STRING "1"
// Retrieval info: PRIVATE: SHIFT_RIGHT_REG STRING "1"
// Retrieval info: PRIVATE: SHIFT_ROTATE_MODE STRING "None"
// Retrieval info: PRIVATE: SIGNA STRING "SIGNED"
// Retrieval info: PRIVATE: SIGNA_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: SIGNA_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: SIGNA_PIPE_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: SIGNA_PIPE_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: SIGNA_PIPE_REG STRING "1"
// Retrieval info: PRIVATE: SIGNA_REG STRING "1"
// Retrieval info: PRIVATE: SIGNB STRING "SIGNED"
// Retrieval info: PRIVATE: SIGNB_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: SIGNB_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: SIGNB_PIPE_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: SIGNB_PIPE_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: SIGNB_PIPE_REG STRING "1"
// Retrieval info: PRIVATE: SIGNB_REG STRING "1"
// Retrieval info: PRIVATE: SRCA0 STRING "Shiftin input"
// Retrieval info: PRIVATE: SRCB0 STRING "Multiplier input"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: WIDTHA STRING "18"
// Retrieval info: PRIVATE: WIDTHB STRING "18"
// Retrieval info: PRIVATE: WIDTH_UPPER_DATA NUMERIC "1"
// Retrieval info: PRIVATE: ZERO_CHAINOUT_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ZERO_CHAINOUT_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_CHAINOUT_REG STRING "0"
// Retrieval info: PRIVATE: ZERO_LOOPBACK_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ZERO_LOOPBACK_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_LOOPBACK_OUT_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ZERO_LOOPBACK_OUT_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_LOOPBACK_OUT_REG STRING "1"
// Retrieval info: PRIVATE: ZERO_LOOPBACK_PIPE_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ZERO_LOOPBACK_PIPE_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_LOOPBACK_PIPE_REG STRING "1"
// Retrieval info: PRIVATE: ZERO_LOOPBACK_REG STRING "1"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ACCUMULATOR STRING "YES"
// Retrieval info: CONSTANT: ACCUM_DIRECTION STRING "ADD"
// Retrieval info: CONSTANT: ADDNSUB_MULTIPLIER_ACLR1 STRING "UNUSED"
// Retrieval info: CONSTANT: ADDNSUB_MULTIPLIER_ACLR3 STRING "UNUSED"
// Retrieval info: CONSTANT: ADDNSUB_MULTIPLIER_PIPELINE_ACLR1 STRING "UNUSED"
// Retrieval info: CONSTANT: ADDNSUB_MULTIPLIER_PIPELINE_ACLR3 STRING "UNUSED"
// Retrieval info: CONSTANT: ADDNSUB_MULTIPLIER_PIPELINE_REGISTER1 STRING "CLOCK0"
// Retrieval info: CONSTANT: ADDNSUB_MULTIPLIER_PIPELINE_REGISTER3 STRING "CLOCK0"
// Retrieval info: CONSTANT: ADDNSUB_MULTIPLIER_REGISTER1 STRING "CLOCK0"
// Retrieval info: CONSTANT: ADDNSUB_MULTIPLIER_REGISTER3 STRING "CLOCK0"
// Retrieval info: CONSTANT: CHAINOUT_ADDER STRING "NO"
// Retrieval info: CONSTANT: CHAINOUT_REGISTER STRING "UNREGISTERED"
// Retrieval info: CONSTANT: DEDICATED_MULTIPLIER_CIRCUITRY STRING "YES"
// Retrieval info: CONSTANT: INPUT_ACLR_A0 STRING "UNUSED"
// Retrieval info: CONSTANT: INPUT_ACLR_A1 STRING "UNUSED"
// Retrieval info: CONSTANT: INPUT_ACLR_A2 STRING "UNUSED"
// Retrieval info: CONSTANT: INPUT_ACLR_A3 STRING "UNUSED"
// Retrieval info: CONSTANT: INPUT_ACLR_B0 STRING "UNUSED"
// Retrieval info: CONSTANT: INPUT_ACLR_B1 STRING "UNUSED"
// Retrieval info: CONSTANT: INPUT_ACLR_B2 STRING "UNUSED"
// Retrieval info: CONSTANT: INPUT_ACLR_B3 STRING "UNUSED"
// Retrieval info: CONSTANT: INPUT_REGISTER_A0 STRING "CLOCK0"
// Retrieval info: CONSTANT: INPUT_REGISTER_A1 STRING "CLOCK0"
// Retrieval info: CONSTANT: INPUT_REGISTER_A2 STRING "CLOCK0"
// Retrieval info: CONSTANT: INPUT_REGISTER_A3 STRING "CLOCK0"
// Retrieval info: CONSTANT: INPUT_REGISTER_B0 STRING "CLOCK0"
// Retrieval info: CONSTANT: INPUT_REGISTER_B1 STRING "CLOCK0"
// Retrieval info: CONSTANT: INPUT_REGISTER_B2 STRING "CLOCK0"
// Retrieval info: CONSTANT: INPUT_REGISTER_B3 STRING "CLOCK0"
// Retrieval info: CONSTANT: INPUT_SOURCE_A0 STRING "DATAA"
// Retrieval info: CONSTANT: INPUT_SOURCE_A1 STRING "SCANA"
// Retrieval info: CONSTANT: INPUT_SOURCE_A2 STRING "SCANA"
// Retrieval info: CONSTANT: INPUT_SOURCE_A3 STRING "SCANA"
// Retrieval info: CONSTANT: INPUT_SOURCE_B0 STRING "DATAB"
// Retrieval info: CONSTANT: INPUT_SOURCE_B1 STRING "DATAB"
// Retrieval info: CONSTANT: INPUT_SOURCE_B2 STRING "DATAB"
// Retrieval info: CONSTANT: INPUT_SOURCE_B3 STRING "DATAB"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altmult_add"
// Retrieval info: CONSTANT: MULTIPLIER1_DIRECTION STRING "ADD"
// Retrieval info: CONSTANT: MULTIPLIER3_DIRECTION STRING "ADD"
// Retrieval info: CONSTANT: MULTIPLIER_ACLR0 STRING "UNUSED"
// Retrieval info: CONSTANT: MULTIPLIER_ACLR1 STRING "UNUSED"
// Retrieval info: CONSTANT: MULTIPLIER_ACLR2 STRING "UNUSED"
// Retrieval info: CONSTANT: MULTIPLIER_ACLR3 STRING "UNUSED"
// Retrieval info: CONSTANT: MULTIPLIER_REGISTER0 STRING "CLOCK0"
// Retrieval info: CONSTANT: MULTIPLIER_REGISTER1 STRING "CLOCK0"
// Retrieval info: CONSTANT: MULTIPLIER_REGISTER2 STRING "CLOCK0"
// Retrieval info: CONSTANT: MULTIPLIER_REGISTER3 STRING "CLOCK0"
// Retrieval info: CONSTANT: NUMBER_OF_MULTIPLIERS NUMERIC "4"
// Retrieval info: CONSTANT: OUTPUT_ACLR STRING "UNUSED"
// Retrieval info: CONSTANT: OUTPUT_REGISTER STRING "CLOCK0"
// Retrieval info: CONSTANT: OUTPUT_ROUND_TYPE STRING "NEAREST_INTEGER"
// Retrieval info: CONSTANT: OUTPUT_SATURATE_ACLR STRING "UNUSED"
// Retrieval info: CONSTANT: OUTPUT_SATURATE_PIPELINE_ACLR STRING "UNUSED"
// Retrieval info: CONSTANT: OUTPUT_SATURATE_PIPELINE_REGISTER STRING "CLOCK0"
// Retrieval info: CONSTANT: OUTPUT_SATURATE_REGISTER STRING "CLOCK0"
// Retrieval info: CONSTANT: OUTPUT_SATURATE_TYPE STRING "SYMMETRIC"
// Retrieval info: CONSTANT: OUTPUT_SATURATION STRING "YES"
// Retrieval info: CONSTANT: PORT_ADDNSUB1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_ADDNSUB3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SIGNA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SIGNB STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: REPRESENTATION_A STRING "SIGNED"
// Retrieval info: CONSTANT: REPRESENTATION_B STRING "SIGNED"
// Retrieval info: CONSTANT: SCANOUTA_REGISTER STRING "UNREGISTERED"
// Retrieval info: CONSTANT: SIGNED_ACLR_A STRING "UNUSED"
// Retrieval info: CONSTANT: SIGNED_ACLR_B STRING "UNUSED"
// Retrieval info: CONSTANT: SIGNED_PIPELINE_ACLR_A STRING "UNUSED"
// Retrieval info: CONSTANT: SIGNED_PIPELINE_ACLR_B STRING "UNUSED"
// Retrieval info: CONSTANT: SIGNED_PIPELINE_REGISTER_A STRING "CLOCK0"
// Retrieval info: CONSTANT: SIGNED_PIPELINE_REGISTER_B STRING "CLOCK0"
// Retrieval info: CONSTANT: SIGNED_REGISTER_A STRING "CLOCK0"
// Retrieval info: CONSTANT: SIGNED_REGISTER_B STRING "CLOCK0"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "18"
// Retrieval info: CONSTANT: WIDTH_B NUMERIC "18"
// Retrieval info: CONSTANT: WIDTH_CHAININ NUMERIC "1"
// Retrieval info: CONSTANT: WIDTH_MSB NUMERIC "44"
// Retrieval info: CONSTANT: WIDTH_RESULT NUMERIC "44"
// Retrieval info: CONSTANT: WIDTH_SATURATE_SIGN NUMERIC "1"
// Retrieval info: CONSTANT: ZERO_CHAINOUT_OUTPUT_ACLR STRING "UNUSED"
// Retrieval info: CONSTANT: ZERO_CHAINOUT_OUTPUT_REGISTER STRING "CLOCK0"
// Retrieval info: CONSTANT: ZERO_LOOPBACK_ACLR STRING "UNUSED"
// Retrieval info: CONSTANT: ZERO_LOOPBACK_OUTPUT_ACLR STRING "UNUSED"
// Retrieval info: CONSTANT: ZERO_LOOPBACK_OUTPUT_REGISTER STRING "CLOCK0"
// Retrieval info: CONSTANT: ZERO_LOOPBACK_PIPELINE_ACLR STRING "UNUSED"
// Retrieval info: CONSTANT: ZERO_LOOPBACK_PIPELINE_REGISTER STRING "CLOCK0"
// Retrieval info: CONSTANT: ZERO_LOOPBACK_REGISTER STRING "CLOCK0"
// Retrieval info: USED_PORT: clock0 0 0 0 0 INPUT VCC "clock0"
// Retrieval info: USED_PORT: dataa_0 0 0 18 0 INPUT GND "dataa_0[17..0]"
// Retrieval info: USED_PORT: datab_0 0 0 18 0 INPUT GND "datab_0[17..0]"
// Retrieval info: USED_PORT: datab_1 0 0 18 0 INPUT GND "datab_1[17..0]"
// Retrieval info: USED_PORT: datab_2 0 0 18 0 INPUT GND "datab_2[17..0]"
// Retrieval info: USED_PORT: datab_3 0 0 18 0 INPUT GND "datab_3[17..0]"
// Retrieval info: USED_PORT: result 0 0 44 0 OUTPUT GND "result[43..0]"
// Retrieval info: USED_PORT: shiftouta 0 0 18 0 OUTPUT GND "shiftouta[17..0]"
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock0 0 0 0 0
// Retrieval info: CONNECT: @dataa 0 0 18 18 GND 0 0 18 0
// Retrieval info: CONNECT: @dataa 0 0 18 36 GND 0 0 18 0
// Retrieval info: CONNECT: @dataa 0 0 18 54 GND 0 0 18 0
// Retrieval info: CONNECT: @dataa 0 0 18 0 dataa_0 0 0 18 0
// Retrieval info: CONNECT: @datab 0 0 18 0 datab_0 0 0 18 0
// Retrieval info: CONNECT: @datab 0 0 18 18 datab_1 0 0 18 0
// Retrieval info: CONNECT: @datab 0 0 18 36 datab_2 0 0 18 0
// Retrieval info: CONNECT: @datab 0 0 18 54 datab_3 0 0 18 0
// Retrieval info: CONNECT: result 0 0 44 0 @result 0 0 44 0
// Retrieval info: CONNECT: shiftouta 0 0 18 0 @scanouta 0 0 18 0
// Retrieval info: GEN_FILE: TYPE_NORMAL scanout_chain_megafn.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL scanout_chain_megafn.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL scanout_chain_megafn.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL scanout_chain_megafn.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL scanout_chain_megafn_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL scanout_chain_megafn_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
// megafunction wizard: %ALTMULT_ACCUM (MAC)%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altmult_add
// ============================================================
// File Name: scanout_chain_megafn.v
// Megafunction Name(s):
// altmult_add
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 12.0 Build 178 05/31/2012 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2012 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module scanout_chain_megafn (
clock0,
dataa_0,
datab_0,
datab_1,
datab_2,
datab_3,
result,
shiftouta);
input clock0;
input [17:0] dataa_0;
input [17:0] datab_0;
input [17:0] datab_1;
input [17:0] datab_2;
input [17:0] datab_3;
output [43:0] result;
output [17:0] shiftouta;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock0;
tri0 [17:0] dataa_0;
tri0 [17:0] datab_0;
tri0 [17:0] datab_1;
tri0 [17:0] datab_2;
tri0 [17:0] datab_3;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ACCUM_DIRECTION STRING "Add"
// Retrieval info: PRIVATE: ACCUM_SLOAD NUMERIC "0"
// Retrieval info: PRIVATE: ACCUM_SLOAD_ACLR NUMERIC "3"
// Retrieval info: PRIVATE: ACCUM_SLOAD_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ACCUM_SLOAD_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ACCUM_SLOAD_PIPELINE_ACLR NUMERIC "3"
// Retrieval info: PRIVATE: ACCUM_SLOAD_PIPELINE_REG NUMERIC "1"
// Retrieval info: PRIVATE: ACCUM_SLOAD_PIPELINE_REG_INDEX NUMERIC "0"
// Retrieval info: PRIVATE: ACCUM_SLOAD_PIPE_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ACCUM_SLOAD_PIPE_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ACCUM_SLOAD_PIPE_REG STRING "1"
// Retrieval info: PRIVATE: ACCUM_SLOAD_REG NUMERIC "1"
// Retrieval info: PRIVATE: ACCUM_SLOAD_REG_INDEX NUMERIC "0"
// Retrieval info: PRIVATE: ACCUM_SLOAD_UPPER_DATA NUMERIC "0"
// Retrieval info: PRIVATE: ACCUM_SLOAD_UPPER_DATA_ACLR NUMERIC "3"
// Retrieval info: PRIVATE: ACCUM_SLOAD_UPPER_DATA_PIPELINE_ACLR NUMERIC "3"
// Retrieval info: PRIVATE: ACCUM_SLOAD_UPPER_DATA_PIPELINE_REG NUMERIC "0"
// Retrieval info: PRIVATE: ACCUM_SLOAD_UPPER_DATA_REG NUMERIC "0"
// Retrieval info: PRIVATE: ADDNSUB1_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ADDNSUB1_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ADDNSUB1_PIPE_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ADDNSUB1_PIPE_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ADDNSUB1_PIPE_REG STRING "1"
// Retrieval info: PRIVATE: ADDNSUB1_REG STRING "1"
// Retrieval info: PRIVATE: ADDNSUB3_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ADDNSUB3_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ADDNSUB3_PIPE_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ADDNSUB3_PIPE_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ADDNSUB3_PIPE_REG STRING "1"
// Retrieval info: PRIVATE: ADDNSUB3_REG STRING "1"
// Retrieval info: PRIVATE: ADD_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: ALL_REG_ACLR NUMERIC "0"
// Retrieval info: PRIVATE: A_ACLR_SRC_MULT0 NUMERIC "3"
// Retrieval info: PRIVATE: A_CLK_SRC_MULT0 NUMERIC "0"
// Retrieval info: PRIVATE: B_ACLR_SRC_MULT0 NUMERIC "3"
// Retrieval info: PRIVATE: B_CLK_SRC_MULT0 NUMERIC "0"
// Retrieval info: PRIVATE: CHAINOUT_OUTPUT_ACLR NUMERIC "3"
// Retrieval info: PRIVATE: CHAINOUT_OUTPUT_REG STRING "0"
// Retrieval info: PRIVATE: CHAINOUT_OUTPUT_REGISTER NUMERIC "0"
// Retrieval info: PRIVATE: CHAINOUT_OUTPUT_REGISTERED NUMERIC "0"
// Retrieval info: PRIVATE: CHAS_ZERO_CHAINOUT NUMERIC "0"
// Retrieval info: PRIVATE: EXTRA_MULTIPLIER_LATENCY NUMERIC "0"
// Retrieval info: PRIVATE: HAS_ACCUMULATOR NUMERIC "1"
// Retrieval info: PRIVATE: HAS_ACUMM_SLOAD NUMERIC "0"
// Retrieval info: PRIVATE: HAS_CHAININ_PORT NUMERIC "0"
// Retrieval info: PRIVATE: HAS_CHAINOUT_ADDER NUMERIC "0"
// Retrieval info: PRIVATE: HAS_LOOPBACK NUMERIC "0"
// Retrieval info: PRIVATE: HAS_MAC STRING "1"
// Retrieval info: PRIVATE: HAS_SAT_ROUND STRING "1"
// Retrieval info: PRIVATE: HAS_ZERO_LOOPBACK NUMERIC "0"
// Retrieval info: PRIVATE: IMPL_STYLE_DEDICATED NUMERIC "1"
// Retrieval info: PRIVATE: IMPL_STYLE_DEFAULT NUMERIC "0"
// Retrieval info: PRIVATE: IMPL_STYLE_LCELL NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
// Retrieval info: PRIVATE: MULT_LATENCY NUMERIC "0"
// Retrieval info: PRIVATE: MULT_REGA0 NUMERIC "1"
// Retrieval info: PRIVATE: MULT_REGB0 NUMERIC "1"
// Retrieval info: PRIVATE: MULT_REGOUT0 NUMERIC "1"
// Retrieval info: PRIVATE: NUM_MULT STRING "4"
// Retrieval info: PRIVATE: OP1 STRING "Add"
// Retrieval info: PRIVATE: OP3 STRING "Add"
// Retrieval info: PRIVATE: OUTPUT_EXTRA_LAT NUMERIC "0"
// Retrieval info: PRIVATE: OUTPUT_REG_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: OUTPUT_REG_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW NUMERIC "0"
// Retrieval info: PRIVATE: Q_ACLR_SRC_MULT0 NUMERIC "3"
// Retrieval info: PRIVATE: Q_CLK_SRC_MULT0 NUMERIC "0"
// Retrieval info: PRIVATE: REG_OUT NUMERIC "1"
// Retrieval info: PRIVATE: RNFORMAT STRING "44"
// Retrieval info: PRIVATE: ROTATE_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ROTATE_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ROTATE_OUT_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ROTATE_OUT_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ROTATE_OUT_REG STRING "1"
// Retrieval info: PRIVATE: ROTATE_PIPE_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ROTATE_PIPE_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ROTATE_PIPE_REG STRING "1"
// Retrieval info: PRIVATE: ROTATE_REG STRING "1"
// Retrieval info: PRIVATE: ROUND3_CHAINOUT_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ROUND3_CHAINOUT_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ROUND3_CHAINOUT_MODE STRING "Disabled"
// Retrieval info: PRIVATE: ROUND3_CHAINOUT_OUT_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ROUND3_CHAINOUT_OUT_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ROUND3_CHAINOUT_OUT_REG STRING "0"
// Retrieval info: PRIVATE: ROUND3_CHAINOUT_PIPE_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ROUND3_CHAINOUT_PIPE_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ROUND3_CHAINOUT_PIPE_REG STRING "1"
// Retrieval info: PRIVATE: ROUND3_CHAINOUT_REG STRING "1"
// Retrieval info: PRIVATE: ROUND3_FRAC_WIDTH NUMERIC "23"
// Retrieval info: PRIVATE: ROUND3_OUTPUT_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ROUND3_OUTPUT_CHAINOUT_TYPE STRING "Nearest Integer"
// Retrieval info: PRIVATE: ROUND3_OUTPUT_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ROUND3_OUTPUT_MODE STRING "Disabled"
// Retrieval info: PRIVATE: ROUND3_OUTPUT_PIPE_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ROUND3_OUTPUT_PIPE_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ROUND3_OUTPUT_PIPE_REG STRING "1"
// Retrieval info: PRIVATE: ROUND3_OUTPUT_REG STRING "1"
// Retrieval info: PRIVATE: RQFORMAT STRING "Q1.30"
// Retrieval info: PRIVATE: RTS_WIDTH STRING "44"
// Retrieval info: PRIVATE: SAME_CONFIG NUMERIC "1"
// Retrieval info: PRIVATE: SAME_CONTROL_SRC_A0 NUMERIC "1"
// Retrieval info: PRIVATE: SAME_CONTROL_SRC_B0 NUMERIC "1"
// Retrieval info: PRIVATE: SAT3_CHAINOUT_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: SAT3_CHAINOUT_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: SAT3_CHAINOUT_MODE STRING "Enabled"
// Retrieval info: PRIVATE: SAT3_CHAINOUT_OUT_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: SAT3_CHAINOUT_OUT_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: SAT3_CHAINOUT_PIPE_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: SAT3_CHAINOUT_PIPE_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: SAT3_CHAINOUT_PIPE_REG STRING "1"
// Retrieval info: PRIVATE: SAT3_CHAINOUT_REG STRING "1"
// Retrieval info: PRIVATE: SAT3_FRAC_WIDTH NUMERIC "1"
// Retrieval info: PRIVATE: SAT3_OUTPUT_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: SAT3_OUTPUT_CHAINOUT_TYPE STRING "Symmetric"
// Retrieval info: PRIVATE: SAT3_OUTPUT_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: SAT3_OUTPUT_MODE STRING "Enabled"
// Retrieval info: PRIVATE: SAT3_OUTPUT_OVERFLOW NUMERIC "0"
// Retrieval info: PRIVATE: SAT3_OUTPUT_PIPE_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: SAT3_OUTPUT_PIPE_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: SAT3_OUTPUT_PIPE_REG STRING "1"
// Retrieval info: PRIVATE: SAT3_OUTPUT_REG STRING "1"
// Retrieval info: PRIVATE: SCANOUTA NUMERIC "1"
// Retrieval info: PRIVATE: SCANOUTB NUMERIC "0"
// Retrieval info: PRIVATE: SHIFTOUTA_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: SHIFTOUTA_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: SHIFTOUTA_REG STRING "0"
// Retrieval info: PRIVATE: SHIFT_RIGHT_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: SHIFT_RIGHT_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: SHIFT_RIGHT_OUT_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: SHIFT_RIGHT_OUT_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: SHIFT_RIGHT_OUT_REG STRING "1"
// Retrieval info: PRIVATE: SHIFT_RIGHT_PIPE_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: SHIFT_RIGHT_PIPE_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: SHIFT_RIGHT_PIPE_REG STRING "1"
// Retrieval info: PRIVATE: SHIFT_RIGHT_REG STRING "1"
// Retrieval info: PRIVATE: SHIFT_ROTATE_MODE STRING "None"
// Retrieval info: PRIVATE: SIGNA STRING "SIGNED"
// Retrieval info: PRIVATE: SIGNA_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: SIGNA_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: SIGNA_PIPE_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: SIGNA_PIPE_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: SIGNA_PIPE_REG STRING "1"
// Retrieval info: PRIVATE: SIGNA_REG STRING "1"
// Retrieval info: PRIVATE: SIGNB STRING "SIGNED"
// Retrieval info: PRIVATE: SIGNB_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: SIGNB_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: SIGNB_PIPE_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: SIGNB_PIPE_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: SIGNB_PIPE_REG STRING "1"
// Retrieval info: PRIVATE: SIGNB_REG STRING "1"
// Retrieval info: PRIVATE: SRCA0 STRING "Shiftin input"
// Retrieval info: PRIVATE: SRCB0 STRING "Multiplier input"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: WIDTHA STRING "18"
// Retrieval info: PRIVATE: WIDTHB STRING "18"
// Retrieval info: PRIVATE: WIDTH_UPPER_DATA NUMERIC "1"
// Retrieval info: PRIVATE: ZERO_CHAINOUT_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ZERO_CHAINOUT_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_CHAINOUT_REG STRING "0"
// Retrieval info: PRIVATE: ZERO_LOOPBACK_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ZERO_LOOPBACK_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_LOOPBACK_OUT_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ZERO_LOOPBACK_OUT_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_LOOPBACK_OUT_REG STRING "1"
// Retrieval info: PRIVATE: ZERO_LOOPBACK_PIPE_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ZERO_LOOPBACK_PIPE_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_LOOPBACK_PIPE_REG STRING "1"
// Retrieval info: PRIVATE: ZERO_LOOPBACK_REG STRING "1"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ACCUMULATOR STRING "YES"
// Retrieval info: CONSTANT: ACCUM_DIRECTION STRING "ADD"
// Retrieval info: CONSTANT: ADDNSUB_MULTIPLIER_ACLR1 STRING "UNUSED"
// Retrieval info: CONSTANT: ADDNSUB_MULTIPLIER_ACLR3 STRING "UNUSED"
// Retrieval info: CONSTANT: ADDNSUB_MULTIPLIER_PIPELINE_ACLR1 STRING "UNUSED"
// Retrieval info: CONSTANT: ADDNSUB_MULTIPLIER_PIPELINE_ACLR3 STRING "UNUSED"
// Retrieval info: CONSTANT: ADDNSUB_MULTIPLIER_PIPELINE_REGISTER1 STRING "CLOCK0"
// Retrieval info: CONSTANT: ADDNSUB_MULTIPLIER_PIPELINE_REGISTER3 STRING "CLOCK0"
// Retrieval info: CONSTANT: ADDNSUB_MULTIPLIER_REGISTER1 STRING "CLOCK0"
// Retrieval info: CONSTANT: ADDNSUB_MULTIPLIER_REGISTER3 STRING "CLOCK0"
// Retrieval info: CONSTANT: CHAINOUT_ADDER STRING "NO"
// Retrieval info: CONSTANT: CHAINOUT_REGISTER STRING "UNREGISTERED"
// Retrieval info: CONSTANT: DEDICATED_MULTIPLIER_CIRCUITRY STRING "YES"
// Retrieval info: CONSTANT: INPUT_ACLR_A0 STRING "UNUSED"
// Retrieval info: CONSTANT: INPUT_ACLR_A1 STRING "UNUSED"
// Retrieval info: CONSTANT: INPUT_ACLR_A2 STRING "UNUSED"
// Retrieval info: CONSTANT: INPUT_ACLR_A3 STRING "UNUSED"
// Retrieval info: CONSTANT: INPUT_ACLR_B0 STRING "UNUSED"
// Retrieval info: CONSTANT: INPUT_ACLR_B1 STRING "UNUSED"
// Retrieval info: CONSTANT: INPUT_ACLR_B2 STRING "UNUSED"
// Retrieval info: CONSTANT: INPUT_ACLR_B3 STRING "UNUSED"
// Retrieval info: CONSTANT: INPUT_REGISTER_A0 STRING "CLOCK0"
// Retrieval info: CONSTANT: INPUT_REGISTER_A1 STRING "CLOCK0"
// Retrieval info: CONSTANT: INPUT_REGISTER_A2 STRING "CLOCK0"
// Retrieval info: CONSTANT: INPUT_REGISTER_A3 STRING "CLOCK0"
// Retrieval info: CONSTANT: INPUT_REGISTER_B0 STRING "CLOCK0"
// Retrieval info: CONSTANT: INPUT_REGISTER_B1 STRING "CLOCK0"
// Retrieval info: CONSTANT: INPUT_REGISTER_B2 STRING "CLOCK0"
// Retrieval info: CONSTANT: INPUT_REGISTER_B3 STRING "CLOCK0"
// Retrieval info: CONSTANT: INPUT_SOURCE_A0 STRING "DATAA"
// Retrieval info: CONSTANT: INPUT_SOURCE_A1 STRING "SCANA"
// Retrieval info: CONSTANT: INPUT_SOURCE_A2 STRING "SCANA"
// Retrieval info: CONSTANT: INPUT_SOURCE_A3 STRING "SCANA"
// Retrieval info: CONSTANT: INPUT_SOURCE_B0 STRING "DATAB"
// Retrieval info: CONSTANT: INPUT_SOURCE_B1 STRING "DATAB"
// Retrieval info: CONSTANT: INPUT_SOURCE_B2 STRING "DATAB"
// Retrieval info: CONSTANT: INPUT_SOURCE_B3 STRING "DATAB"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altmult_add"
// Retrieval info: CONSTANT: MULTIPLIER1_DIRECTION STRING "ADD"
// Retrieval info: CONSTANT: MULTIPLIER3_DIRECTION STRING "ADD"
// Retrieval info: CONSTANT: MULTIPLIER_ACLR0 STRING "UNUSED"
// Retrieval info: CONSTANT: MULTIPLIER_ACLR1 STRING "UNUSED"
// Retrieval info: CONSTANT: MULTIPLIER_ACLR2 STRING "UNUSED"
// Retrieval info: CONSTANT: MULTIPLIER_ACLR3 STRING "UNUSED"
// Retrieval info: CONSTANT: MULTIPLIER_REGISTER0 STRING "CLOCK0"
// Retrieval info: CONSTANT: MULTIPLIER_REGISTER1 STRING "CLOCK0"
// Retrieval info: CONSTANT: MULTIPLIER_REGISTER2 STRING "CLOCK0"
// Retrieval info: CONSTANT: MULTIPLIER_REGISTER3 STRING "CLOCK0"
// Retrieval info: CONSTANT: NUMBER_OF_MULTIPLIERS NUMERIC "4"
// Retrieval info: CONSTANT: OUTPUT_ACLR STRING "UNUSED"
// Retrieval info: CONSTANT: OUTPUT_REGISTER STRING "CLOCK0"
// Retrieval info: CONSTANT: OUTPUT_ROUND_TYPE STRING "NEAREST_INTEGER"
// Retrieval info: CONSTANT: OUTPUT_SATURATE_ACLR STRING "UNUSED"
// Retrieval info: CONSTANT: OUTPUT_SATURATE_PIPELINE_ACLR STRING "UNUSED"
// Retrieval info: CONSTANT: OUTPUT_SATURATE_PIPELINE_REGISTER STRING "CLOCK0"
// Retrieval info: CONSTANT: OUTPUT_SATURATE_REGISTER STRING "CLOCK0"
// Retrieval info: CONSTANT: OUTPUT_SATURATE_TYPE STRING "SYMMETRIC"
// Retrieval info: CONSTANT: OUTPUT_SATURATION STRING "YES"
// Retrieval info: CONSTANT: PORT_ADDNSUB1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_ADDNSUB3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SIGNA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SIGNB STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: REPRESENTATION_A STRING "SIGNED"
// Retrieval info: CONSTANT: REPRESENTATION_B STRING "SIGNED"
// Retrieval info: CONSTANT: SCANOUTA_REGISTER STRING "UNREGISTERED"
// Retrieval info: CONSTANT: SIGNED_ACLR_A STRING "UNUSED"
// Retrieval info: CONSTANT: SIGNED_ACLR_B STRING "UNUSED"
// Retrieval info: CONSTANT: SIGNED_PIPELINE_ACLR_A STRING "UNUSED"
// Retrieval info: CONSTANT: SIGNED_PIPELINE_ACLR_B STRING "UNUSED"
// Retrieval info: CONSTANT: SIGNED_PIPELINE_REGISTER_A STRING "CLOCK0"
// Retrieval info: CONSTANT: SIGNED_PIPELINE_REGISTER_B STRING "CLOCK0"
// Retrieval info: CONSTANT: SIGNED_REGISTER_A STRING "CLOCK0"
// Retrieval info: CONSTANT: SIGNED_REGISTER_B STRING "CLOCK0"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "18"
// Retrieval info: CONSTANT: WIDTH_B NUMERIC "18"
// Retrieval info: CONSTANT: WIDTH_CHAININ NUMERIC "1"
// Retrieval info: CONSTANT: WIDTH_MSB NUMERIC "44"
// Retrieval info: CONSTANT: WIDTH_RESULT NUMERIC "44"
// Retrieval info: CONSTANT: WIDTH_SATURATE_SIGN NUMERIC "1"
// Retrieval info: CONSTANT: ZERO_CHAINOUT_OUTPUT_ACLR STRING "UNUSED"
// Retrieval info: CONSTANT: ZERO_CHAINOUT_OUTPUT_REGISTER STRING "CLOCK0"
// Retrieval info: CONSTANT: ZERO_LOOPBACK_ACLR STRING "UNUSED"
// Retrieval info: CONSTANT: ZERO_LOOPBACK_OUTPUT_ACLR STRING "UNUSED"
// Retrieval info: CONSTANT: ZERO_LOOPBACK_OUTPUT_REGISTER STRING "CLOCK0"
// Retrieval info: CONSTANT: ZERO_LOOPBACK_PIPELINE_ACLR STRING "UNUSED"
// Retrieval info: CONSTANT: ZERO_LOOPBACK_PIPELINE_REGISTER STRING "CLOCK0"
// Retrieval info: CONSTANT: ZERO_LOOPBACK_REGISTER STRING "CLOCK0"
// Retrieval info: USED_PORT: clock0 0 0 0 0 INPUT VCC "clock0"
// Retrieval info: USED_PORT: dataa_0 0 0 18 0 INPUT GND "dataa_0[17..0]"
// Retrieval info: USED_PORT: datab_0 0 0 18 0 INPUT GND "datab_0[17..0]"
// Retrieval info: USED_PORT: datab_1 0 0 18 0 INPUT GND "datab_1[17..0]"
// Retrieval info: USED_PORT: datab_2 0 0 18 0 INPUT GND "datab_2[17..0]"
// Retrieval info: USED_PORT: datab_3 0 0 18 0 INPUT GND "datab_3[17..0]"
// Retrieval info: USED_PORT: result 0 0 44 0 OUTPUT GND "result[43..0]"
// Retrieval info: USED_PORT: shiftouta 0 0 18 0 OUTPUT GND "shiftouta[17..0]"
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock0 0 0 0 0
// Retrieval info: CONNECT: @dataa 0 0 18 18 GND 0 0 18 0
// Retrieval info: CONNECT: @dataa 0 0 18 36 GND 0 0 18 0
// Retrieval info: CONNECT: @dataa 0 0 18 54 GND 0 0 18 0
// Retrieval info: CONNECT: @dataa 0 0 18 0 dataa_0 0 0 18 0
// Retrieval info: CONNECT: @datab 0 0 18 0 datab_0 0 0 18 0
// Retrieval info: CONNECT: @datab 0 0 18 18 datab_1 0 0 18 0
// Retrieval info: CONNECT: @datab 0 0 18 36 datab_2 0 0 18 0
// Retrieval info: CONNECT: @datab 0 0 18 54 datab_3 0 0 18 0
// Retrieval info: CONNECT: result 0 0 44 0 @result 0 0 44 0
// Retrieval info: CONNECT: shiftouta 0 0 18 0 @scanouta 0 0 18 0
// Retrieval info: GEN_FILE: TYPE_NORMAL scanout_chain_megafn.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL scanout_chain_megafn.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL scanout_chain_megafn.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL scanout_chain_megafn.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL scanout_chain_megafn_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL scanout_chain_megafn_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
scanout_chain_megafn scanout_chain_megafn_inst (
.clock0 ( clock0_sig ),
.dataa_0 ( dataa_0_sig ),
.datab_0 ( datab_0_sig ),
.datab_1 ( datab_1_sig ),
.datab_2 ( datab_2_sig ),
.datab_3 ( datab_3_sig ),
.result ( result_sig ),
.shiftouta ( shiftouta_sig )
);
|
// ==============================================================
// File generated by AutoESL - High-Level Synthesis System (C, C++, SystemC)
// Version: 2011.1
// Copyright (C) 2011 Xilinx Inc. All rights reserved.
//
// ==============================================================
/*-----------------------------------------------------------------------
-- AESL_FPSim_pkg.v:
-- Floating point simulation model for verilog.
--
-----------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Single precision units.
-- FAdd, FSub, FAddSub, FMul, FDiv, FSqrt
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Double precision units.
-- DAdd, DSub, DAddSub, DMul, DDiv, DSqrt
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Single precision units.
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Single precision Add.
-------------------------------------------------------------------------------
*/
module ACMP_fadd_comb(din0, din1, dout);
parameter ID = 0;
parameter NUM_STAGE = 13;
parameter din0_WIDTH = 32;
parameter din1_WIDTH = 32;
parameter dout_WIDTH = 32;
input[din0_WIDTH-1:0] din0;
input[din1_WIDTH-1:0] din1;
output[dout_WIDTH-1:0] dout;
AESL_WP_FAdd #(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH)
ACMP_FAdd_U (
.clk(1'b1),
.reset(1'b1),
.ce(1'b1),
.din0(din0),
.din1(din1),
.dout(dout));
endmodule
module ACMP_fadd(clk, reset, ce, din0, din1, dout);
parameter ID = 0;
parameter NUM_STAGE = 13;
parameter din0_WIDTH = 32;
parameter din1_WIDTH = 32;
parameter dout_WIDTH = 32;
input clk, reset, ce;
input[din0_WIDTH-1:0] din0;
input[din1_WIDTH-1:0] din1;
output[dout_WIDTH-1:0] dout;
AESL_WP_FAdd #(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH)
ACMP_FAdd_U (
.clk(clk),
.reset(reset),
.ce(ce),
.din0(din0),
.din1(din1),
.dout(dout));
endmodule
/*
-------------------------------------------------------------------------------
-- Single precision Sub.
-------------------------------------------------------------------------------
*/
module ACMP_fsub_comb (din0, din1, dout);
parameter ID = 0;
parameter NUM_STAGE = 13;
parameter din0_WIDTH = 32;
parameter din1_WIDTH = 32;
parameter dout_WIDTH = 32;
input[din0_WIDTH-1:0] din0;
input[din1_WIDTH-1:0] din1;
output[dout_WIDTH-1:0] dout;
AESL_WP_FSub #(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH)
ACMP_FSub_U(
.clk(1'b1),
.reset(1'b1),
.ce(1'b1),
.din0(din0),
.din1(din1),
.dout(dout));
endmodule
module ACMP_fsub(clk, reset, ce, din0, din1, dout);
parameter ID = 0;
parameter NUM_STAGE = 13;
parameter din0_WIDTH = 32;
parameter din1_WIDTH = 32;
parameter dout_WIDTH = 32;
input clk, reset, ce;
input[din0_WIDTH-1:0] din0;
input[din1_WIDTH-1:0] din1;
output[dout_WIDTH-1:0] dout;
AESL_WP_FSub #(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH)
ACMP_FSub_U(
.clk(clk),
.reset(reset),
.ce(ce),
.din0(din0),
.din1(din1),
.dout(dout));
endmodule
/*
-------------------------------------------------------------------------------
-- Single precision AddSub.
-------------------------------------------------------------------------------
*/
module ACMP_faddfsub_comb(opcode, din0, din1, dout);
parameter ID = 0;
parameter NUM_STAGE = 13;
parameter din0_WIDTH = 32;
parameter din1_WIDTH = 32;
parameter dout_WIDTH = 32;
input[1:0] opcode;
input[din0_WIDTH-1:0] din0;
input[din1_WIDTH-1:0] din1;
output[dout_WIDTH-1:0] dout;
AESL_WP_FAddFSub
#(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH)
ACMP_FAddFSub_U(
.clk(1'b1),
.reset(1'b1),
.ce(1'b1),
.opcode(opcode),
.din0(din0),
.din1(din1),
.dout(dout));
endmodule
module ACMP_faddfsub(clk, reset, ce, opcode, din0, din1, dout);
parameter ID = 0;
parameter NUM_STAGE = 13;
parameter din0_WIDTH = 32;
parameter din1_WIDTH = 32;
parameter dout_WIDTH = 32;
input clk, reset, ce;
input[1:0] opcode;
input[din0_WIDTH-1:0] din0;
input[din1_WIDTH-1:0] din1;
output[dout_WIDTH-1:0] dout;
AESL_WP_FAddFSub
#(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH)
ACMP_FAddFSub_U(
.clk(clk),
.reset(reset),
.ce(ce),
.opcode(opcode),
.din0(din0),
.din1(din1),
.dout(dout));
endmodule
module ACMP_fmul_comb(din0, din1, dout);
parameter ID = 0;
parameter NUM_STAGE = 13;
parameter din0_WIDTH = 32;
parameter din1_WIDTH = 32;
parameter dout_WIDTH = 32;
input[din0_WIDTH-1:0] din0;
input[din1_WIDTH-1:0] din1;
output[dout_WIDTH-1:0] dout;
AESL_WP_FMul
#(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH)
ACMP_FMul_U(
.clk(1'b1),
.reset(1'b1),
.ce(1'b1),
.din0(din0),
.din1(din1),
.dout(dout));
endmodule
module ACMP_fmul(clk, reset, ce, din0, din1, dout);
parameter ID = 0;
parameter NUM_STAGE = 13;
parameter din0_WIDTH = 32;
parameter din1_WIDTH = 32;
parameter dout_WIDTH = 32;
input clk, reset, ce;
input[din0_WIDTH-1:0] din0;
input[din1_WIDTH-1:0] din1;
output[dout_WIDTH-1:0] dout;
AESL_WP_FMul
#(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH)
ACMP_FMul_U(
.clk(clk),
.reset(reset),
.ce(ce),
.din0(din0),
.din1(din1),
.dout(dout));
endmodule
module ACMP_fdiv_comb(din0, din1, dout);
parameter ID = 0;
parameter NUM_STAGE = 13;
parameter din0_WIDTH = 32;
parameter din1_WIDTH = 32;
parameter dout_WIDTH = 32;
input[din0_WIDTH-1:0] din0;
input[din1_WIDTH-1:0] din1;
output[dout_WIDTH-1:0] dout;
AESL_WP_FDiv
#(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH)
ACMP_FDiv_U(
.clk(1'b1),
.reset(1'b1),
.ce(1'b1),
.din0(din0),
.din1(din1),
.dout(dout));
endmodule
module ACMP_fdiv(clk, reset, ce, din0, din1, dout);
parameter ID = 0;
parameter NUM_STAGE = 13;
parameter din0_WIDTH = 32;
parameter din1_WIDTH = 32;
parameter dout_WIDTH = 32;
input clk, reset, ce;
input[din0_WIDTH-1:0] din0;
input[din1_WIDTH-1:0] din1;
output[dout_WIDTH-1:0] dout;
AESL_WP_FDiv
#(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH)
ACMP_FDiv_U(
.clk(clk),
.reset(reset),
.ce(ce),
.din0(din0),
.din1(din1),
.dout(dout));
endmodule
module ACMP_fsqrt_comb (din0, din1, dout);
parameter ID = 0;
parameter NUM_STAGE = 13;
parameter din0_WIDTH = 32;
parameter din1_WIDTH = 32;
parameter dout_WIDTH = 32;
input[din0_WIDTH-1:0] din0;
input[din1_WIDTH-1:0] din1;
output[dout_WIDTH-1:0] dout;
AESL_WP_FSqrt
#(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH)
ACMP_FSqrt_U(
.clk(1'b1),
.reset(1'b1),
.ce(1'b1),
.din0(din0),
.din1(din1),
.dout(dout));
endmodule
module ACMP_fsqrt(clk, reset, ce, din0, din1, dout);
parameter ID = 0;
parameter NUM_STAGE = 13;
parameter din0_WIDTH = 32;
parameter din1_WIDTH = 32;
parameter dout_WIDTH = 32;
input clk, reset, ce;
input[din0_WIDTH-1:0] din0;
input[din1_WIDTH-1:0] din1;
output[dout_WIDTH-1:0] dout;
AESL_WP_FSqrt
#(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH)
ACMP_FSqrt_U(
.clk(clk),
.reset(reset),
.ce(ce),
.din0(din0),
.din1(din1),
.dout(dout));
endmodule
/*
-------------------------------------------------------------------------------
-- Double precision
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Double precision ADD
-------------------------------------------------------------------------------
*/
module ACMP_dadd_comb(din0, din1, dout);
parameter ID = 0;
parameter NUM_STAGE = 13;
parameter din0_WIDTH = 64;
parameter din1_WIDTH = 64;
parameter dout_WIDTH = 64;
input[din0_WIDTH-1:0] din0;
input[din1_WIDTH-1:0] din1;
output[dout_WIDTH-1:0] dout;
AESL_WP_DAdd
#(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH)
ACMP_DAdd_U(
.clk(1'b1),
.reset(1'b1),
.ce(1'b1),
.din0(din0),
.din1(din1),
.dout(dout));
endmodule
module ACMP_dadd(clk, reset, ce, din0, din1, dout);
parameter ID = 0;
parameter NUM_STAGE = 13;
parameter din0_WIDTH = 64;
parameter din1_WIDTH = 64;
parameter dout_WIDTH = 64;
input clk, reset, ce;
input[din0_WIDTH-1:0] din0;
input[din1_WIDTH-1:0] din1;
output[dout_WIDTH-1:0] dout;
AESL_WP_DAdd
#(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH)
ACMP_DAdd_U(
.clk(clk),
.reset(reset),
.ce(ce),
.din0(din0),
.din1(din1),
.dout(dout));
endmodule
/*
-------------------------------------------------------------------------------
-- Double precision Sub
-------------------------------------------------------------------------------
*/
module ACMP_dsub_comb(din0, din1, dout);
parameter ID = 0;
parameter NUM_STAGE = 13;
parameter din0_WIDTH = 64;
parameter din1_WIDTH = 64;
parameter dout_WIDTH = 64;
input[din0_WIDTH-1:0] din0;
input[din1_WIDTH-1:0] din1;
output[dout_WIDTH-1:0] dout;
AESL_WP_DSub
#(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH)
ACMP_DSub_U(
.clk(1'b1),
.reset(1'b1),
.ce(1'b1),
.din0(din0),
.din1(din1),
.dout(dout));
endmodule
module ACMP_dsub(clk, reset, ce, din0, din1, dout);
parameter ID = 0;
parameter NUM_STAGE = 13;
parameter din0_WIDTH = 64;
parameter din1_WIDTH = 64;
parameter dout_WIDTH = 64;
input clk, reset, ce;
input[din0_WIDTH-1:0] din0;
input[din1_WIDTH-1:0] din1;
output[dout_WIDTH-1:0] dout;
AESL_WP_DSub
#(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH)
ACMP_DSub_U(
.clk(clk),
.reset(reset),
.ce(ce),
.din0(din0),
.din1(din1),
.dout(dout));
endmodule
/*
-------------------------------------------------------------------------------
-- Double precision AddSub
-------------------------------------------------------------------------------
*/
module ACMP_dadddsub_comb(opcode, din0, din1, dout);
parameter ID = 0;
parameter NUM_STAGE = 13;
parameter din0_WIDTH = 64;
parameter din1_WIDTH = 64;
parameter dout_WIDTH = 64;
input[1:0] opcode;
input[din0_WIDTH-1:0] din0;
input[din1_WIDTH-1:0] din1;
output[dout_WIDTH-1:0] dout;
AESL_WP_DAddDSub
#(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH)
ACMP_DAddDSub_U(
.clk(1'b1),
.reset(1'b1),
.ce(1'b1),
.opcode(opcode),
.din0(din0),
.din1(din1),
.dout(dout));
endmodule
module ACMP_dadddsub(clk, reset, ce, opcode, din0, din1, dout);
parameter ID = 0;
parameter NUM_STAGE = 13;
parameter din0_WIDTH = 64;
parameter din1_WIDTH = 64;
parameter dout_WIDTH = 64;
input clk, reset, ce;
input[1:0] opcode;
input[din0_WIDTH-1:0] din0;
input[din1_WIDTH-1:0] din1;
output[dout_WIDTH-1:0] dout;
AESL_WP_DAddDSub
#(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH)
ACMP_DAddDSub_U(
.clk(clk),
.reset(reset),
.ce(ce),
.opcode(opcode),
.din0(din0),
.din1(din1),
.dout(dout));
endmodule
module ACMP_dmul_comb(din0, din1, dout);
parameter ID = 0;
parameter NUM_STAGE = 13;
parameter din0_WIDTH = 64;
parameter din1_WIDTH = 64;
parameter dout_WIDTH = 64;
input[din0_WIDTH-1:0] din0;
input[din1_WIDTH-1:0] din1;
output[dout_WIDTH-1:0] dout;
AESL_WP_DMul
#(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH)
ACMP_DMul_U(
.clk(1'b1),
.reset(1'b1),
.ce(1'b1),
.din0(din0),
.din1(din1),
.dout(dout));
endmodule
module ACMP_dmul(clk, reset, ce, din0, din1, dout);
parameter ID = 0;
parameter NUM_STAGE = 13;
parameter din0_WIDTH = 64;
parameter din1_WIDTH = 64;
parameter dout_WIDTH = 64;
input clk, reset, ce;
input[din0_WIDTH-1:0] din0;
input[din1_WIDTH-1:0] din1;
output[dout_WIDTH-1:0] dout;
AESL_WP_DMul
#(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH)
ACMP_DMul_U(
.clk(clk),
.reset(reset),
.ce(ce),
.din0(din0),
.din1(din1),
.dout(dout));
endmodule
module ACMP_ddiv_comb(din0, din1, dout);
parameter ID = 0;
parameter NUM_STAGE = 13;
parameter din0_WIDTH = 64;
parameter din1_WIDTH = 64;
parameter dout_WIDTH = 64;
input[din0_WIDTH-1:0] din0;
input[din1_WIDTH-1:0] din1;
output[dout_WIDTH-1:0] dout;
AESL_WP_DDiv
#(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH)
ACMP_DDiv_U(
.clk(1'b1),
.reset(1'b1),
.ce(1'b1),
.din0(din0),
.din1(din1),
.dout(dout));
endmodule
module ACMP_ddiv(clk, reset, ce, din0, din1, dout);
parameter ID = 0;
parameter NUM_STAGE = 13;
parameter din0_WIDTH = 64;
parameter din1_WIDTH = 64;
parameter dout_WIDTH = 64;
input clk, reset, ce;
input[din0_WIDTH-1:0] din0;
input[din1_WIDTH-1:0] din1;
output[dout_WIDTH-1:0] dout;
AESL_WP_DDiv
#(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH)
ACMP_DDiv_U(
.clk(clk),
.reset(reset),
.ce(ce),
.din0(din0),
.din1(din1),
.dout(dout));
endmodule
module ACMP_dsqrt_comb(din0, din1, dout);
parameter ID = 0;
parameter NUM_STAGE = 13;
parameter din0_WIDTH = 64;
parameter din1_WIDTH = 64;
parameter dout_WIDTH = 64;
input[din0_WIDTH-1:0] din0;
input[din1_WIDTH-1:0] din1;
output[dout_WIDTH-1:0] dout;
AESL_WP_DSqrt
#(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH)
ACMP_DSqrt_U(
.clk(1'b1),
.reset(1'b1),
.ce(1'b1),
.din0(din0),
.din1(din1),
.dout(dout));
endmodule
module ACMP_dsqrt(clk, reset, ce, din0, din1, dout);
parameter ID = 0;
parameter NUM_STAGE = 13;
parameter din0_WIDTH = 64;
parameter din1_WIDTH = 64;
parameter dout_WIDTH = 64;
input clk, reset, ce;
input[din0_WIDTH-1:0] din0;
input[din1_WIDTH-1:0] din1;
output[dout_WIDTH-1:0] dout;
AESL_WP_DSqrt
#(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH)
ACMP_DSqrt_U(
.clk(clk),
.reset(reset),
.ce(ce),
.din0(din0),
.din1(din1),
.dout(dout));
endmodule
/*
-------------------------------------------------------------------------------
-- Single precision Cmp (Comparator)
-------------------------------------------------------------------------------
-- Predicate values:
-- FCMP_FALSE = 0, ///< 0 0 0 0 Always false (always folded)
-- FCMP_OEQ = 1, ///< 0 0 0 1 True if ordered and equal
-- FCMP_OGT = 2, ///< 0 0 1 0 True if ordered and greater than
-- FCMP_OGE = 3, ///< 0 0 1 1 True if ordered and greater than or equal
-- FCMP_OLT = 4, ///< 0 1 0 0 True if ordered and less than
-- FCMP_OLE = 5, ///< 0 1 0 1 True if ordered and less than or equal
-- FCMP_ONE = 6, ///< 0 1 1 0 True if ordered and operands are unequal
-- FCMP_ORD = 7, ///< 0 1 1 1 True if ordered (no nans)
-- FCMP_UNO = 8, ///< 1 0 0 0 True if unordered: isnan(X) | isnan(Y)
-- FCMP_UEQ = 9, ///< 1 0 0 1 True if unordered or equal
-- FCMP_UGT =10, ///< 1 0 1 0 True if unordered or greater than
-- FCMP_UGE =11, ///< 1 0 1 1 True if unordered, greater than, or equal
-- FCMP_ULT =12, ///< 1 1 0 0 True if unordered or less than
-- FCMP_ULE =13, ///< 1 1 0 1 True if unordered, less than, or equal
-- FCMP_UNE =14, ///< 1 1 1 0 True if unordered or not equal
-- FCMP_TRUE =15, ///< 1 1 1 1 Always true (always folded)
*/
module ACMP_fcmp_comb(opcode, din0, din1, dout);
parameter ID = 0;
parameter NUM_STAGE = 12;
parameter din0_WIDTH = 32;
parameter din1_WIDTH = 32;
parameter dout_WIDTH = 1;
input[4:0] opcode;
input[din0_WIDTH-1:0] din0;
input[din1_WIDTH-1:0] din1;
output[0:0] dout;
AESL_WP_FCmp
#(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH)
ACMP_FCmp_U(
.clk(1'b1),
.reset(1'b1),
.ce(1'b1),
.opcode(opcode),
.din0(din0),
.din1(din1),
.dout(dout));
endmodule
module ACMP_fcmp(clk, reset, ce, opcode, din0, din1, dout);
parameter ID = 0;
parameter NUM_STAGE = 12;
parameter din0_WIDTH = 32;
parameter din1_WIDTH = 32;
parameter dout_WIDTH = 1;
input clk;
input reset, ce;
input[4:0] opcode;
input[din0_WIDTH-1:0] din0;
input[din1_WIDTH-1:0] din1;
output[0:0] dout;
AESL_WP_FCmp
#(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH)
ACMP_FCmp_U(
.clk(clk),
.reset(reset),
.ce(ce),
.opcode(opcode),
.din0(din0),
.din1(din1),
.dout(dout));
endmodule
/*
-------------------------------------------------------------------------------
-- Double precision Cmp (Comparator)
-------------------------------------------------------------------------------
-- Predicate values:
-- FCMP_FALSE = 0, ///< 0 0 0 0 Always false (always folded)
-- FCMP_OEQ = 1, ///< 0 0 0 1 True if ordered and equal
-- FCMP_OGT = 2, ///< 0 0 1 0 True if ordered and greater than
-- FCMP_OGE = 3, ///< 0 0 1 1 True if ordered and greater than or equal
-- FCMP_OLT = 4, ///< 0 1 0 0 True if ordered and less than
-- FCMP_OLE = 5, ///< 0 1 0 1 True if ordered and less than or equal
-- FCMP_ONE = 6, ///< 0 1 1 0 True if ordered and operands are unequal
-- FCMP_ORD = 7, ///< 0 1 1 1 True if ordered (no nans)
-- FCMP_UNO = 8, ///< 1 0 0 0 True if unordered: isnan(X) | isnan(Y)
-- FCMP_UEQ = 9, ///< 1 0 0 1 True if unordered or equal
-- FCMP_UGT =10, ///< 1 0 1 0 True if unordered or greater than
-- FCMP_UGE =11, ///< 1 0 1 1 True if unordered, greater than, or equal
-- FCMP_ULT =12, ///< 1 1 0 0 True if unordered or less than
-- FCMP_ULE =13, ///< 1 1 0 1 True if unordered, less than, or equal
-- FCMP_UNE =14, ///< 1 1 1 0 True if unordered or not equal
-- FCMP_TRUE =15, ///< 1 1 1 1 Always true (always folded)
*/
module ACMP_dcmp_comb(opcode, din0, din1, dout);
parameter ID = 0;
parameter NUM_STAGE = 12;
parameter din0_WIDTH = 64;
parameter din1_WIDTH = 64;
parameter dout_WIDTH = 1;
input[4:0] opcode;
input[din0_WIDTH-1:0] din0;
input[din1_WIDTH-1:0] din1;
output[0:0] dout;
AESL_WP_DCmp
#(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH)
ACMP_DCmp_U(
.clk(1'b1),
.reset(1'b1),
.ce(1'b1),
.opcode(opcode),
.din0(din0),
.din1(din1),
.dout(dout));
endmodule
module ACMP_dcmp(clk, reset, ce, opcode, din0, din1, dout);
parameter ID = 0;
parameter NUM_STAGE = 12;
parameter din0_WIDTH = 64;
parameter din1_WIDTH = 64;
parameter dout_WIDTH = 1;
input clk;
input reset, ce;
input[4:0] opcode;
input[din0_WIDTH-1:0] din0;
input[din1_WIDTH-1:0] din1;
output[0:0] dout;
AESL_WP_DCmp
#(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH)
ACMP_DCmp_U(
.clk(clk),
.reset(reset),
.ce(ce),
.opcode(opcode),
.din0(din0),
.din1(din1),
.dout(dout));
endmodule
/*
-------------------------------------------------------------------------------
-- Single precision to int32
-------------------------------------------------------------------------------
*/
module ACMP_fptosi_comb(din0, dout);
parameter ID = 0;
parameter NUM_STAGE = 12;
parameter din0_WIDTH = 32;
parameter dout_WIDTH = 32;
input[din0_WIDTH-1:0] din0;
output[dout_WIDTH-1:0] dout;
AESL_WP_SPToSI
#(NUM_STAGE, din0_WIDTH, dout_WIDTH)
ACMP_SPToSI_U(
.clk(1'b1),
.reset(1'b1),
.ce(1'b1),
.din0(din0),
.dout(dout));
endmodule
module ACMP_fptosi(clk, reset, ce, din0, dout);
parameter ID = 0;
parameter NUM_STAGE = 12;
parameter din0_WIDTH = 32;
parameter dout_WIDTH = 32;
input clk;
input reset, ce;
input[din0_WIDTH-1:0] din0;
output[dout_WIDTH-1:0] dout;
AESL_WP_SPToSI
#(NUM_STAGE, din0_WIDTH, dout_WIDTH)
ACMP_SPToSI_U(
.clk(clk),
.reset(reset),
.ce(ce),
.din0(din0),
.dout(dout));
endmodule
/*
-------------------------------------------------------------------------------
-- Double precision to int32
-------------------------------------------------------------------------------
*/
module ACMP_dptosi_comb(din0, dout);
parameter ID = 0;
parameter NUM_STAGE = 12;
parameter din0_WIDTH = 64;
parameter dout_WIDTH = 32;
input[din0_WIDTH-1:0] din0;
output[dout_WIDTH-1:0] dout;
AESL_WP_DPToSI
#(NUM_STAGE, din0_WIDTH, dout_WIDTH)
ACMP_DPToSI_U(
.clk(1'b1),
.reset(1'b1),
.ce(1'b1),
.din0(din0),
.dout(dout));
endmodule
module ACMP_dptosi(clk, reset, ce, din0, dout);
parameter ID = 0;
parameter NUM_STAGE = 12;
parameter din0_WIDTH = 64;
parameter dout_WIDTH = 32;
input clk;
input reset, ce;
input[din0_WIDTH-1:0] din0;
output[dout_WIDTH-1:0] dout;
AESL_WP_DPToSI
#(NUM_STAGE, din0_WIDTH, dout_WIDTH)
ACMP_DPToSI_U(
.clk(clk),
.reset(reset),
.ce(ce),
.din0(din0),
.dout(dout));
endmodule
/*
-------------------------------------------------------------------------------
-- Int32 to single precision
-------------------------------------------------------------------------------
*/
module ACMP_sitofp_comb(din0, dout);
parameter ID = 0;
parameter NUM_STAGE = 12;
parameter din0_WIDTH = 32;
parameter dout_WIDTH = 64;
input[din0_WIDTH-1:0] din0;
output[dout_WIDTH-1:0] dout;
AESL_WP_SIToSP
#(NUM_STAGE, din0_WIDTH, dout_WIDTH)
ACMP_SIToDP_U(
.clk(1'b1),
.reset(1'b1),
.ce(1'b1),
.din0(din0),
.dout(dout));
endmodule
module ACMP_sitofp(clk, reset, ce, din0, dout);
parameter ID = 0;
parameter NUM_STAGE = 12;
parameter din0_WIDTH = 32;
parameter dout_WIDTH = 64;
input clk;
input reset, ce;
input[din0_WIDTH-1:0] din0;
output[dout_WIDTH-1:0] dout;
AESL_WP_SIToSP
#(NUM_STAGE, din0_WIDTH, dout_WIDTH)
ACMP_SIToDP_U(
.clk(clk),
.reset(reset),
.ce(ce),
.din0(din0),
.dout(dout));
endmodule
/*
-------------------------------------------------------------------------------
-- Int32 to double precision
-------------------------------------------------------------------------------
*/
module ACMP_sitodp_comb(din0, dout);
parameter ID = 0;
parameter NUM_STAGE = 12;
parameter din0_WIDTH = 32;
parameter dout_WIDTH = 64;
input[din0_WIDTH-1:0] din0;
output[dout_WIDTH-1:0] dout;
AESL_WP_SIToDP
#(NUM_STAGE, din0_WIDTH, dout_WIDTH)
ACMP_SIToDP_U(
.clk(1'b1),
.reset(1'b1),
.ce(1'b1),
.din0(din0),
.dout(dout));
endmodule
module ACMP_sitodp(clk, reset, ce, din0, dout);
parameter ID = 0;
parameter NUM_STAGE = 12;
parameter din0_WIDTH = 32;
parameter dout_WIDTH = 64;
input clk;
input reset, ce;
input[din0_WIDTH-1:0] din0;
output[dout_WIDTH-1:0] dout;
AESL_WP_SIToDP
#(NUM_STAGE, din0_WIDTH, dout_WIDTH)
ACMP_SIToDP_U(
.clk(clk),
.reset(reset),
.ce(ce),
.din0(din0),
.dout(dout));
endmodule
/*
-------------------------------------------------------------------------------
-- Single precision to uint32
-------------------------------------------------------------------------------
*/
module ACMP_fptoui_comb(din0, dout);
parameter ID = 0;
parameter NUM_STAGE = 12;
parameter din0_WIDTH = 32;
parameter dout_WIDTH = 32;
input[din0_WIDTH-1:0] din0;
output[dout_WIDTH-1:0] dout;
AESL_WP_SPToUI
#(NUM_STAGE, din0_WIDTH, dout_WIDTH)
ACMP_SPToUI_U(
.clk(1'b1),
.reset(1'b1),
.ce(1'b1),
.din0(din0),
.dout(dout));
endmodule
module ACMP_fptoui(clk, reset, ce, din0, dout);
parameter ID = 0;
parameter NUM_STAGE = 12;
parameter din0_WIDTH = 32;
parameter dout_WIDTH = 32;
input clk;
input reset, ce;
input[din0_WIDTH-1:0] din0;
output[dout_WIDTH-1:0] dout;
AESL_WP_SPToUI
#(NUM_STAGE, din0_WIDTH, dout_WIDTH)
ACMP_SPToUI_U(
.clk(clk),
.reset(reset),
.ce(ce),
.din0(din0),
.dout(dout));
endmodule
/*
-------------------------------------------------------------------------------
-- Double precision to uint32
-------------------------------------------------------------------------------
*/
module ACMP_dptoui_comb(din0, dout);
parameter ID = 0;
parameter NUM_STAGE = 12;
parameter din0_WIDTH = 64;
parameter dout_WIDTH = 32;
input[din0_WIDTH-1:0] din0;
output[dout_WIDTH-1:0] dout;
AESL_WP_DPToUI
#(NUM_STAGE, din0_WIDTH, dout_WIDTH)
ACMP_DPToUI_U(
.clk(1'b1),
.reset(1'b1),
.ce(1'b1),
.din0(din0),
.dout(dout));
endmodule
module ACMP_dptoui(clk, reset, ce, din0, dout);
parameter ID = 0;
parameter NUM_STAGE = 12;
parameter din0_WIDTH = 64;
parameter dout_WIDTH = 32;
input clk;
input reset, ce;
input[din0_WIDTH-1:0] din0;
output[dout_WIDTH-1:0] dout;
AESL_WP_DPToUI
#(NUM_STAGE, din0_WIDTH, dout_WIDTH)
ACMP_DPToUI_U(
.clk(clk),
.reset(reset),
.ce(ce),
.din0(din0),
.dout(dout));
endmodule
/*
-------------------------------------------------------------------------------
-- uInt32 to single precision
-------------------------------------------------------------------------------
*/
module ACMP_uitofp_comb(din0, dout);
parameter ID = 0;
parameter NUM_STAGE = 12;
parameter din0_WIDTH = 32;
parameter dout_WIDTH = 64;
input[din0_WIDTH-1:0] din0;
output[dout_WIDTH-1:0] dout;
AESL_WP_UIToSP
#(NUM_STAGE, din0_WIDTH, dout_WIDTH)
ACMP_UIToSP_U(
.clk(1'b1),
.reset(1'b1),
.ce(1'b1),
.din0(din0),
.dout(dout));
endmodule
module ACMP_uitofp(clk, reset, ce, din0, dout);
parameter ID = 0;
parameter NUM_STAGE = 12;
parameter din0_WIDTH = 32;
parameter dout_WIDTH = 64;
input clk;
input reset, ce;
input[din0_WIDTH-1:0] din0;
output[dout_WIDTH-1:0] dout;
AESL_WP_UIToSP
#(NUM_STAGE, din0_WIDTH, dout_WIDTH)
ACMP_UIToSP_U(
.clk(clk),
.reset(reset),
.ce(ce),
.din0(din0),
.dout(dout));
endmodule
/*
-------------------------------------------------------------------------------
-- uInt32 to double precision
-------------------------------------------------------------------------------
*/
module ACMP_uitodp_comb(din0, dout);
parameter ID = 0;
parameter NUM_STAGE = 12;
parameter din0_WIDTH = 32;
parameter dout_WIDTH = 64;
input[din0_WIDTH-1:0] din0;
output[dout_WIDTH-1:0] dout;
AESL_WP_UIToDP
#(NUM_STAGE, din0_WIDTH, dout_WIDTH)
ACMP_UIToDP_U(
.clk(1'b1),
.reset(1'b1),
.ce(1'b1),
.din0(din0),
.dout(dout));
endmodule
module ACMP_uitodp(clk, reset, ce, din0, dout);
parameter ID = 0;
parameter NUM_STAGE = 12;
parameter din0_WIDTH = 32;
parameter dout_WIDTH = 64;
input clk;
input reset, ce;
input[din0_WIDTH-1:0] din0;
output[dout_WIDTH-1:0] dout;
AESL_WP_UIToDP
#(NUM_STAGE, din0_WIDTH, dout_WIDTH)
ACMP_UIToDP_U(
.clk(clk),
.reset(reset),
.ce(ce),
.din0(din0),
.dout(dout));
endmodule
/*
-------------------------------------------------------------------------------
-- single to double precision
-------------------------------------------------------------------------------
*/
module ACMP_fpext_comb(din0, dout);
parameter ID = 0;
parameter NUM_STAGE = 12;
parameter din0_WIDTH = 32;
parameter dout_WIDTH = 64;
input[din0_WIDTH-1:0] din0;
output[dout_WIDTH-1:0] dout;
AESL_WP_SPToDP
#(NUM_STAGE, din0_WIDTH, dout_WIDTH)
ACMP_fpext_U(
.clk(1'b1),
.reset(1'b1),
.ce(1'b1),
.din0(din0),
.dout(dout));
endmodule
module ACMP_fpext(clk, reset, ce, din0, dout);
parameter ID = 0;
parameter NUM_STAGE = 12;
parameter din0_WIDTH = 32;
parameter dout_WIDTH = 64;
input clk;
input reset, ce;
input[din0_WIDTH-1:0] din0;
output[dout_WIDTH-1:0] dout;
AESL_WP_SPToDP
#(NUM_STAGE, din0_WIDTH, dout_WIDTH)
ACMP_fpext_U(
.clk(clk),
.reset(reset),
.ce(ce),
.din0(din0),
.dout(dout));
endmodule
/*
-------------------------------------------------------------------------------
-- double to single precision
-------------------------------------------------------------------------------
*/
module ACMP_fptrunc_comb(din0, dout);
parameter ID = 0;
parameter NUM_STAGE = 12;
parameter din0_WIDTH = 32;
parameter dout_WIDTH = 64;
input[din0_WIDTH-1:0] din0;
output[dout_WIDTH-1:0] dout;
AESL_WP_DPToSP
#(NUM_STAGE, din0_WIDTH, dout_WIDTH)
ACMP_fptrunc_U(
.clk(1'b1),
.reset(1'b1),
.ce(1'b1),
.din0(din0),
.dout(dout));
endmodule
module ACMP_fptrunc(clk, reset, ce, din0, dout);
parameter ID = 0;
parameter NUM_STAGE = 12;
parameter din0_WIDTH = 32;
parameter dout_WIDTH = 64;
input clk;
input reset, ce;
input[din0_WIDTH-1:0] din0;
output[dout_WIDTH-1:0] dout;
AESL_WP_DPToSP
#(NUM_STAGE, din0_WIDTH, dout_WIDTH)
ACMP_fptrunc_U(
.clk(clk),
.reset(reset),
.ce(ce),
.din0(din0),
.dout(dout));
endmodule
|
// ==============================================================
// RTL generated by AutoESL - High-Level Synthesis System (C, C++, SystemC)
// Version: 2011.1
// Copyright (C) 2011 Xilinx Inc. All rights reserved.
//
// ===========================================================
`timescale 1 ns / 1 ps
module jacobiansPoseComposition (
ap_clk,
ap_rst,
ap_start,
ap_done,
ap_idle,
X_x,
X_y,
X_z,
X_qr,
X_qx,
X_qy,
X_qz,
U_x,
U_y,
U_z,
U_qr,
U_qx,
U_qy,
U_qz,
df_dx_address0,
df_dx_ce0,
df_dx_we0,
df_dx_d0,
df_dx_q0,
df_dx_address1,
df_dx_ce1,
df_dx_we1,
df_dx_d1,
df_dx_q1,
out_X_oplus_U_x_address0,
out_X_oplus_U_x_ce0,
out_X_oplus_U_x_we0,
out_X_oplus_U_x_d0,
out_X_oplus_U_x_q0,
out_X_oplus_U_x_address1,
out_X_oplus_U_x_ce1,
out_X_oplus_U_x_we1,
out_X_oplus_U_x_d1,
out_X_oplus_U_x_q1,
out_X_oplus_U_y_address0,
out_X_oplus_U_y_ce0,
out_X_oplus_U_y_we0,
out_X_oplus_U_y_d0,
out_X_oplus_U_y_q0,
out_X_oplus_U_y_address1,
out_X_oplus_U_y_ce1,
out_X_oplus_U_y_we1,
out_X_oplus_U_y_d1,
out_X_oplus_U_y_q1,
out_X_oplus_U_z_address0,
out_X_oplus_U_z_ce0,
out_X_oplus_U_z_we0,
out_X_oplus_U_z_d0,
out_X_oplus_U_z_q0,
out_X_oplus_U_z_address1,
out_X_oplus_U_z_ce1,
out_X_oplus_U_z_we1,
out_X_oplus_U_z_d1,
out_X_oplus_U_z_q1,
out_X_oplus_U_qr_address0,
out_X_oplus_U_qr_ce0,
out_X_oplus_U_qr_we0,
out_X_oplus_U_qr_d0,
out_X_oplus_U_qr_q0,
out_X_oplus_U_qr_address1,
out_X_oplus_U_qr_ce1,
out_X_oplus_U_qr_we1,
out_X_oplus_U_qr_d1,
out_X_oplus_U_qr_q1,
out_X_oplus_U_qx_address0,
out_X_oplus_U_qx_ce0,
out_X_oplus_U_qx_we0,
out_X_oplus_U_qx_d0,
out_X_oplus_U_qx_q0,
out_X_oplus_U_qx_address1,
out_X_oplus_U_qx_ce1,
out_X_oplus_U_qx_we1,
out_X_oplus_U_qx_d1,
out_X_oplus_U_qx_q1,
out_X_oplus_U_qy_address0,
out_X_oplus_U_qy_ce0,
out_X_oplus_U_qy_we0,
out_X_oplus_U_qy_d0,
out_X_oplus_U_qy_q0,
out_X_oplus_U_qy_address1,
out_X_oplus_U_qy_ce1,
out_X_oplus_U_qy_we1,
out_X_oplus_U_qy_d1,
out_X_oplus_U_qy_q1,
out_X_oplus_U_qz_address0,
out_X_oplus_U_qz_ce0,
out_X_oplus_U_qz_we0,
out_X_oplus_U_qz_d0,
out_X_oplus_U_qz_q0,
out_X_oplus_U_qz_address1,
out_X_oplus_U_qz_ce1,
out_X_oplus_U_qz_we1,
out_X_oplus_U_qz_d1,
out_X_oplus_U_qz_q1
);
input ap_clk;
input ap_rst;
input ap_start;
output ap_done;
output ap_idle;
input [31:0] X_x;
input [31:0] X_y;
input [31:0] X_z;
input [31:0] X_qr;
input [31:0] X_qx;
input [31:0] X_qy;
input [31:0] X_qz;
input [31:0] U_x;
input [31:0] U_y;
input [31:0] U_z;
input [31:0] U_qr;
input [31:0] U_qx;
input [31:0] U_qy;
input [31:0] U_qz;
output [4:0] df_dx_address0;
output df_dx_ce0;
output df_dx_we0;
output [31:0] df_dx_d0;
input [31:0] df_dx_q0;
output [4:0] df_dx_address1;
output df_dx_ce1;
output df_dx_we1;
output [31:0] df_dx_d1;
input [31:0] df_dx_q1;
output [0:0] out_X_oplus_U_x_address0;
output out_X_oplus_U_x_ce0;
output out_X_oplus_U_x_we0;
output [31:0] out_X_oplus_U_x_d0;
input [31:0] out_X_oplus_U_x_q0;
output [0:0] out_X_oplus_U_x_address1;
output out_X_oplus_U_x_ce1;
output out_X_oplus_U_x_we1;
output [31:0] out_X_oplus_U_x_d1;
input [31:0] out_X_oplus_U_x_q1;
output [0:0] out_X_oplus_U_y_address0;
output out_X_oplus_U_y_ce0;
output out_X_oplus_U_y_we0;
output [31:0] out_X_oplus_U_y_d0;
input [31:0] out_X_oplus_U_y_q0;
output [0:0] out_X_oplus_U_y_address1;
output out_X_oplus_U_y_ce1;
output out_X_oplus_U_y_we1;
output [31:0] out_X_oplus_U_y_d1;
input [31:0] out_X_oplus_U_y_q1;
output [0:0] out_X_oplus_U_z_address0;
output out_X_oplus_U_z_ce0;
output out_X_oplus_U_z_we0;
output [31:0] out_X_oplus_U_z_d0;
input [31:0] out_X_oplus_U_z_q0;
output [0:0] out_X_oplus_U_z_address1;
output out_X_oplus_U_z_ce1;
output out_X_oplus_U_z_we1;
output [31:0] out_X_oplus_U_z_d1;
input [31:0] out_X_oplus_U_z_q1;
output [0:0] out_X_oplus_U_qr_address0;
output out_X_oplus_U_qr_ce0;
output out_X_oplus_U_qr_we0;
output [31:0] out_X_oplus_U_qr_d0;
input [31:0] out_X_oplus_U_qr_q0;
output [0:0] out_X_oplus_U_qr_address1;
output out_X_oplus_U_qr_ce1;
output out_X_oplus_U_qr_we1;
output [31:0] out_X_oplus_U_qr_d1;
input [31:0] out_X_oplus_U_qr_q1;
output [0:0] out_X_oplus_U_qx_address0;
output out_X_oplus_U_qx_ce0;
output out_X_oplus_U_qx_we0;
output [31:0] out_X_oplus_U_qx_d0;
input [31:0] out_X_oplus_U_qx_q0;
output [0:0] out_X_oplus_U_qx_address1;
output out_X_oplus_U_qx_ce1;
output out_X_oplus_U_qx_we1;
output [31:0] out_X_oplus_U_qx_d1;
input [31:0] out_X_oplus_U_qx_q1;
output [0:0] out_X_oplus_U_qy_address0;
output out_X_oplus_U_qy_ce0;
output out_X_oplus_U_qy_we0;
output [31:0] out_X_oplus_U_qy_d0;
input [31:0] out_X_oplus_U_qy_q0;
output [0:0] out_X_oplus_U_qy_address1;
output out_X_oplus_U_qy_ce1;
output out_X_oplus_U_qy_we1;
output [31:0] out_X_oplus_U_qy_d1;
input [31:0] out_X_oplus_U_qy_q1;
output [0:0] out_X_oplus_U_qz_address0;
output out_X_oplus_U_qz_ce0;
output out_X_oplus_U_qz_we0;
output [31:0] out_X_oplus_U_qz_d0;
input [31:0] out_X_oplus_U_qz_q0;
output [0:0] out_X_oplus_U_qz_address1;
output out_X_oplus_U_qz_ce1;
output out_X_oplus_U_qz_we1;
output [31:0] out_X_oplus_U_qz_d1;
input [31:0] out_X_oplus_U_qz_q1;
reg ap_done;
reg ap_idle;
reg[4:0] df_dx_address0;
reg df_dx_ce0;
reg df_dx_we0;
reg[31:0] df_dx_d0;
reg[4:0] df_dx_address1;
reg df_dx_ce1;
reg df_dx_we1;
reg[31:0] df_dx_d1;
reg out_X_oplus_U_x_ce0;
reg out_X_oplus_U_x_we0;
reg out_X_oplus_U_y_ce0;
reg out_X_oplus_U_y_we0;
reg out_X_oplus_U_z_ce0;
reg out_X_oplus_U_z_we0;
reg out_X_oplus_U_qr_ce0;
reg out_X_oplus_U_qr_we0;
reg out_X_oplus_U_qx_ce0;
reg out_X_oplus_U_qx_we0;
reg out_X_oplus_U_qy_ce0;
reg out_X_oplus_U_qy_we0;
reg out_X_oplus_U_qz_ce0;
reg out_X_oplus_U_qz_we0;
reg [6:0] ap_CS_fsm;
wire [31:0] grp_fu_634_p2;
reg [31:0] reg_795;
wire [31:0] grp_fu_640_p2;
reg [31:0] reg_829;
wire [31:0] grp_fu_555_p2;
reg [31:0] reg_850;
wire [31:0] grp_fu_560_p2;
reg [31:0] reg_869;
reg [31:0] reg_889;
reg [31:0] reg_903;
reg [31:0] reg_931;
reg [31:0] reg_943;
reg [31:0] reg_954;
wire [31:0] grp_fu_566_p2;
reg [31:0] reg_961;
reg [31:0] reg_976;
wire [31:0] grp_fu_571_p2;
reg [31:0] reg_983;
reg [31:0] reg_990;
reg [31:0] reg_999;
reg [31:0] reg_1006;
reg [31:0] reg_1013;
wire [31:0] grp_fu_652_p2;
reg [31:0] reg_1019;
reg [31:0] reg_1038;
reg [31:0] reg_1047;
wire [31:0] grp_fu_658_p2;
reg [31:0] reg_1057;
wire [31:0] grp_fu_663_p2;
reg [31:0] reg_1072;
wire [31:0] grp_fu_668_p2;
reg [31:0] reg_1085;
wire [31:0] grp_fu_673_p2;
reg [31:0] reg_1098;
wire [31:0] grp_fu_678_p2;
reg [31:0] reg_1110;
wire [31:0] grp_fu_683_p2;
reg [31:0] reg_1123;
reg [31:0] reg_1136;
reg [31:0] reg_1144;
reg [31:0] reg_1152;
wire [31:0] grp_fu_583_p2;
reg [31:0] reg_1157;
reg [31:0] reg_1167;
wire [31:0] grp_fu_588_p2;
reg [31:0] reg_1178;
wire [31:0] grp_fu_592_p2;
reg [31:0] reg_1186;
wire [31:0] grp_fu_596_p2;
reg [31:0] reg_1194;
wire [31:0] grp_fu_692_p2;
reg [31:0] reg_1201;
wire [31:0] grp_fu_600_p2;
reg [31:0] reg_1212;
wire [31:0] grp_fu_696_p2;
reg [31:0] reg_1220;
wire [31:0] grp_fu_701_p2;
reg [31:0] reg_1231;
wire [31:0] grp_fu_705_p2;
reg [31:0] reg_1242;
wire [31:0] grp_fu_709_p2;
reg [31:0] reg_1252;
reg [31:0] reg_1261;
wire [31:0] grp_fu_604_p2;
reg [31:0] reg_1270;
wire [31:0] grp_fu_608_p2;
reg [31:0] reg_1277;
wire [31:0] grp_fu_612_p2;
reg [31:0] reg_1284;
reg [31:0] reg_1291;
wire [31:0] grp_fu_714_p2;
reg [31:0] reg_1299;
wire [31:0] grp_fu_718_p2;
reg [31:0] reg_1307;
wire [31:0] grp_fu_722_p2;
reg [31:0] reg_1315;
wire [31:0] grp_fu_727_p2;
reg [31:0] reg_1325;
wire [31:0] grp_fu_732_p2;
reg [31:0] reg_1335;
wire [31:0] grp_fu_737_p2;
reg [31:0] reg_1345;
wire [31:0] grp_fu_742_p2;
reg [31:0] reg_1355;
wire [31:0] grp_fu_747_p2;
reg [31:0] reg_1365;
reg [31:0] reg_1375;
reg [31:0] reg_1383;
reg [31:0] reg_1394;
reg [31:0] reg_1403;
reg [31:0] reg_1414;
reg [31:0] reg_1425;
reg [31:0] reg_1435;
reg [31:0] reg_1444;
reg [31:0] reg_1454;
reg [31:0] reg_1460;
reg [31:0] reg_1467;
reg [31:0] reg_1473;
reg [31:0] reg_1479;
reg [31:0] reg_1485;
wire [31:0] grp_fu_755_p2;
reg [31:0] reg_1491;
wire [31:0] grp_fu_759_p2;
reg [31:0] reg_1497;
wire [31:0] grp_fu_763_p2;
reg [31:0] reg_1503;
wire [31:0] grp_fu_767_p2;
reg [31:0] reg_1509;
wire [31:0] grp_fu_771_p2;
reg [31:0] reg_1515;
reg [31:0] reg_1521;
reg [31:0] reg_1530;
reg [31:0] reg_1536;
reg [31:0] reg_1542;
reg [31:0] reg_1547;
reg [31:0] reg_1552;
reg [31:0] reg_1557;
reg [31:0] reg_1562;
reg [31:0] reg_1567;
reg [31:0] reg_1572;
wire [31:0] grp_fu_618_p2;
reg [31:0] reg_1577;
wire [31:0] grp_fu_622_p2;
reg [31:0] reg_1583;
wire [31:0] grp_fu_626_p2;
reg [31:0] reg_1589;
wire [31:0] grp_fu_630_p2;
reg [31:0] reg_1595;
reg [31:0] tmp_reg_1756;
reg [31:0] tmp_48_reg_1776;
reg [31:0] X_plus_U_qz_reg_1782;
reg [31:0] tmp_4_reg_1793;
reg [30:0] tmp_53_reg_1799;
wire [31:0] tmp1_i1_fu_1624_p1;
reg [31:0] tmp1_i1_reg_1804;
reg [30:0] tmp_52_reg_1809;
wire [31:0] tmp1_i_fu_1652_p1;
reg [31:0] tmp1_i_reg_1838;
reg [31:0] tmp_27_reg_1869;
reg [31:0] tmp_163_reg_1876;
reg [31:0] tmp_169_reg_1881;
reg [31:0] tmp_42_reg_1886;
reg [31:0] tmp_43_reg_1894;
reg [31:0] tmp_239_reg_1902;
reg [31:0] tmp_253_reg_1907;
reg [31:0] tmp_281_reg_1912;
wire [31:0] grp_fu_775_p2;
reg [31:0] tmp_324_reg_1917;
wire [31:0] grp_fu_779_p2;
reg [31:0] tmp_330_reg_1922;
wire [31:0] grp_fu_783_p2;
reg [31:0] tmp_331_reg_1927;
wire [31:0] grp_fu_787_p2;
reg [31:0] tmp_337_reg_1932;
wire [31:0] grp_fu_791_p2;
reg [31:0] tmp_338_reg_1937;
reg [31:0] grp_fu_555_p0;
reg [31:0] grp_fu_555_p1;
reg [31:0] grp_fu_560_p0;
reg [31:0] grp_fu_560_p1;
reg [31:0] grp_fu_566_p0;
reg [31:0] grp_fu_566_p1;
reg [31:0] grp_fu_571_p0;
reg [31:0] grp_fu_571_p1;
reg [31:0] grp_fu_583_p0;
reg [31:0] grp_fu_583_p1;
reg [31:0] grp_fu_588_p0;
reg [31:0] grp_fu_588_p1;
reg [31:0] grp_fu_592_p0;
reg [31:0] grp_fu_592_p1;
reg [31:0] grp_fu_596_p0;
reg [31:0] grp_fu_596_p1;
reg [31:0] grp_fu_600_p0;
reg [31:0] grp_fu_600_p1;
reg [31:0] grp_fu_604_p0;
reg [31:0] grp_fu_604_p1;
reg [31:0] grp_fu_608_p0;
reg [31:0] grp_fu_608_p1;
reg [31:0] grp_fu_612_p0;
reg [31:0] grp_fu_612_p1;
reg [31:0] grp_fu_618_p0;
reg [31:0] grp_fu_618_p1;
reg [31:0] grp_fu_622_p0;
reg [31:0] grp_fu_622_p1;
reg [31:0] grp_fu_626_p0;
reg [31:0] grp_fu_626_p1;
reg [31:0] grp_fu_630_p0;
reg [31:0] grp_fu_630_p1;
reg [31:0] grp_fu_634_p0;
reg [31:0] grp_fu_634_p1;
reg [31:0] grp_fu_640_p0;
reg [31:0] grp_fu_640_p1;
reg [31:0] grp_fu_652_p0;
reg [31:0] grp_fu_652_p1;
reg [31:0] grp_fu_658_p0;
reg [31:0] grp_fu_658_p1;
reg [31:0] grp_fu_663_p0;
reg [31:0] grp_fu_663_p1;
reg [31:0] grp_fu_668_p0;
reg [31:0] grp_fu_668_p1;
reg [31:0] grp_fu_673_p0;
reg [31:0] grp_fu_673_p1;
reg [31:0] grp_fu_678_p0;
reg [31:0] grp_fu_678_p1;
reg [31:0] grp_fu_683_p0;
reg [31:0] grp_fu_683_p1;
reg [31:0] grp_fu_692_p0;
reg [31:0] grp_fu_692_p1;
reg [31:0] grp_fu_696_p0;
reg [31:0] grp_fu_696_p1;
reg [31:0] grp_fu_701_p0;
reg [31:0] grp_fu_701_p1;
reg [31:0] grp_fu_705_p0;
reg [31:0] grp_fu_705_p1;
reg [31:0] grp_fu_709_p0;
reg [31:0] grp_fu_709_p1;
reg [31:0] grp_fu_714_p0;
reg [31:0] grp_fu_714_p1;
reg [31:0] grp_fu_718_p0;
reg [31:0] grp_fu_718_p1;
reg [31:0] grp_fu_722_p0;
reg [31:0] grp_fu_722_p1;
reg [31:0] grp_fu_727_p0;
reg [31:0] grp_fu_727_p1;
reg [31:0] grp_fu_732_p0;
reg [31:0] grp_fu_732_p1;
reg [31:0] grp_fu_737_p0;
reg [31:0] grp_fu_737_p1;
reg [31:0] grp_fu_742_p0;
reg [31:0] grp_fu_742_p1;
reg [31:0] grp_fu_747_p0;
reg [31:0] grp_fu_747_p1;
reg [31:0] grp_fu_755_p0;
reg [31:0] grp_fu_755_p1;
reg [31:0] grp_fu_759_p0;
reg [31:0] grp_fu_759_p1;
reg [31:0] grp_fu_763_p0;
reg [31:0] grp_fu_763_p1;
reg [31:0] grp_fu_767_p0;
reg [31:0] grp_fu_767_p1;
reg [31:0] grp_fu_771_p0;
reg [31:0] grp_fu_771_p1;
wire [31:0] grp_fu_775_p0;
wire [31:0] grp_fu_775_p1;
wire [31:0] grp_fu_779_p0;
wire [31:0] grp_fu_779_p1;
wire [31:0] grp_fu_783_p0;
wire [31:0] grp_fu_783_p1;
wire [31:0] grp_fu_787_p0;
wire [31:0] grp_fu_787_p1;
wire [31:0] grp_fu_791_p0;
wire [31:0] grp_fu_791_p1;
wire [31:0] i_3_fu_1601_p1;
wire [31:0] i_fu_1618_p1;
wire [31:0] i_fu_1618_p2;
wire [31:0] i_2_fu_1629_p1;
wire [31:0] i_1_fu_1646_p1;
wire [31:0] i_1_fu_1646_p2;
reg [1:0] grp_fu_555_opcode;
wire grp_fu_555_ce;
reg [1:0] grp_fu_560_opcode;
wire grp_fu_560_ce;
reg [1:0] grp_fu_566_opcode;
wire grp_fu_566_ce;
reg [1:0] grp_fu_571_opcode;
wire grp_fu_571_ce;
reg [1:0] grp_fu_583_opcode;
wire grp_fu_583_ce;
reg [1:0] grp_fu_588_opcode;
wire grp_fu_588_ce;
wire grp_fu_592_ce;
wire grp_fu_596_ce;
wire grp_fu_600_ce;
wire grp_fu_604_ce;
wire grp_fu_608_ce;
wire grp_fu_612_ce;
wire grp_fu_618_ce;
wire grp_fu_622_ce;
wire grp_fu_626_ce;
wire grp_fu_630_ce;
wire grp_fu_634_ce;
wire grp_fu_640_ce;
wire grp_fu_652_ce;
wire grp_fu_658_ce;
wire grp_fu_663_ce;
wire grp_fu_668_ce;
wire grp_fu_673_ce;
wire grp_fu_678_ce;
wire grp_fu_683_ce;
wire grp_fu_692_ce;
wire grp_fu_696_ce;
wire grp_fu_701_ce;
wire grp_fu_705_ce;
wire grp_fu_709_ce;
wire grp_fu_714_ce;
wire grp_fu_718_ce;
wire grp_fu_722_ce;
wire grp_fu_727_ce;
wire grp_fu_732_ce;
wire grp_fu_737_ce;
wire grp_fu_742_ce;
wire grp_fu_747_ce;
wire grp_fu_755_ce;
wire grp_fu_759_ce;
wire grp_fu_763_ce;
wire grp_fu_767_ce;
wire grp_fu_771_ce;
wire grp_fu_775_ce;
wire grp_fu_779_ce;
wire grp_fu_783_ce;
wire grp_fu_787_ce;
wire grp_fu_791_ce;
reg [6:0] ap_NS_fsm;
parameter ap_const_logic_1 = 1'b1;
parameter ap_const_logic_0 = 1'b0;
parameter ap_ST_st0_fsm_0 = 7'b0000000;
parameter ap_ST_st1_fsm_1 = 7'b0000001;
parameter ap_ST_st2_fsm_2 = 7'b0000010;
parameter ap_ST_st3_fsm_3 = 7'b0000011;
parameter ap_ST_st4_fsm_4 = 7'b0000100;
parameter ap_ST_st5_fsm_5 = 7'b0000101;
parameter ap_ST_st6_fsm_6 = 7'b0000110;
parameter ap_ST_st7_fsm_7 = 7'b0000111;
parameter ap_ST_st8_fsm_8 = 7'b0001000;
parameter ap_ST_st9_fsm_9 = 7'b0001001;
parameter ap_ST_st10_fsm_10 = 7'b0001010;
parameter ap_ST_st11_fsm_11 = 7'b0001011;
parameter ap_ST_st12_fsm_12 = 7'b0001100;
parameter ap_ST_st13_fsm_13 = 7'b0001101;
parameter ap_ST_st14_fsm_14 = 7'b0001110;
parameter ap_ST_st15_fsm_15 = 7'b0001111;
parameter ap_ST_st16_fsm_16 = 7'b0010000;
parameter ap_ST_st17_fsm_17 = 7'b0010001;
parameter ap_ST_st18_fsm_18 = 7'b0010010;
parameter ap_ST_st19_fsm_19 = 7'b0010011;
parameter ap_ST_st20_fsm_20 = 7'b0010100;
parameter ap_ST_st21_fsm_21 = 7'b0010101;
parameter ap_ST_st22_fsm_22 = 7'b0010110;
parameter ap_ST_st23_fsm_23 = 7'b0010111;
parameter ap_ST_st24_fsm_24 = 7'b0011000;
parameter ap_ST_st25_fsm_25 = 7'b0011001;
parameter ap_ST_st26_fsm_26 = 7'b0011010;
parameter ap_ST_st27_fsm_27 = 7'b0011011;
parameter ap_ST_st28_fsm_28 = 7'b0011100;
parameter ap_ST_st29_fsm_29 = 7'b0011101;
parameter ap_ST_st30_fsm_30 = 7'b0011110;
parameter ap_ST_st31_fsm_31 = 7'b0011111;
parameter ap_ST_st32_fsm_32 = 7'b0100000;
parameter ap_ST_st33_fsm_33 = 7'b0100001;
parameter ap_ST_st34_fsm_34 = 7'b0100010;
parameter ap_ST_st35_fsm_35 = 7'b0100011;
parameter ap_ST_st36_fsm_36 = 7'b0100100;
parameter ap_ST_st37_fsm_37 = 7'b0100101;
parameter ap_ST_st38_fsm_38 = 7'b0100110;
parameter ap_ST_st39_fsm_39 = 7'b0100111;
parameter ap_ST_st40_fsm_40 = 7'b0101000;
parameter ap_ST_st41_fsm_41 = 7'b0101001;
parameter ap_ST_st42_fsm_42 = 7'b0101010;
parameter ap_ST_st43_fsm_43 = 7'b0101011;
parameter ap_ST_st44_fsm_44 = 7'b0101100;
parameter ap_ST_st45_fsm_45 = 7'b0101101;
parameter ap_ST_st46_fsm_46 = 7'b0101110;
parameter ap_ST_st47_fsm_47 = 7'b0101111;
parameter ap_ST_st48_fsm_48 = 7'b0110000;
parameter ap_ST_st49_fsm_49 = 7'b0110001;
parameter ap_ST_st50_fsm_50 = 7'b0110010;
parameter ap_ST_st51_fsm_51 = 7'b0110011;
parameter ap_ST_st52_fsm_52 = 7'b0110100;
parameter ap_ST_st53_fsm_53 = 7'b0110101;
parameter ap_ST_st54_fsm_54 = 7'b0110110;
parameter ap_ST_st55_fsm_55 = 7'b0110111;
parameter ap_ST_st56_fsm_56 = 7'b0111000;
parameter ap_ST_st57_fsm_57 = 7'b0111001;
parameter ap_ST_st58_fsm_58 = 7'b0111010;
parameter ap_ST_st59_fsm_59 = 7'b0111011;
parameter ap_ST_st60_fsm_60 = 7'b0111100;
parameter ap_ST_st61_fsm_61 = 7'b0111101;
parameter ap_ST_st62_fsm_62 = 7'b0111110;
parameter ap_ST_st63_fsm_63 = 7'b0111111;
parameter ap_ST_st64_fsm_64 = 7'b1000000;
parameter ap_ST_st65_fsm_65 = 7'b1000001;
parameter ap_ST_st66_fsm_66 = 7'b1000010;
parameter ap_ST_st67_fsm_67 = 7'b1000011;
parameter ap_ST_st68_fsm_68 = 7'b1000100;
parameter ap_ST_st69_fsm_69 = 7'b1000101;
parameter ap_ST_st70_fsm_70 = 7'b1000110;
parameter ap_ST_st71_fsm_71 = 7'b1000111;
parameter ap_ST_st72_fsm_72 = 7'b1001000;
parameter ap_ST_st73_fsm_73 = 7'b1001001;
parameter ap_ST_st74_fsm_74 = 7'b1001010;
parameter ap_ST_st75_fsm_75 = 7'b1001011;
parameter ap_ST_st76_fsm_76 = 7'b1001100;
parameter ap_ST_st77_fsm_77 = 7'b1001101;
parameter ap_ST_st78_fsm_78 = 7'b1001110;
parameter ap_const_lv64_0 = 64'b0000000000000000000000000000000000000000000000000000000000000000;
parameter ap_const_lv64_1 = 64'b0000000000000000000000000000000000000000000000000000000000000001;
parameter ap_const_lv64_2 = 64'b0000000000000000000000000000000000000000000000000000000000000010;
parameter ap_const_lv64_3 = 64'b0000000000000000000000000000000000000000000000000000000000000011;
parameter ap_const_lv64_4 = 64'b0000000000000000000000000000000000000000000000000000000000000100;
parameter ap_const_lv64_5 = 64'b0000000000000000000000000000000000000000000000000000000000000101;
parameter ap_const_lv64_6 = 64'b0000000000000000000000000000000000000000000000000000000000000110;
parameter ap_const_lv64_7 = 64'b0000000000000000000000000000000000000000000000000000000000000111;
parameter ap_const_lv64_8 = 64'b0000000000000000000000000000000000000000000000000000000000001000;
parameter ap_const_lv64_9 = 64'b0000000000000000000000000000000000000000000000000000000000001001;
parameter ap_const_lv64_A = 64'b0000000000000000000000000000000000000000000000000000000000001010;
parameter ap_const_lv64_B = 64'b0000000000000000000000000000000000000000000000000000000000001011;
parameter ap_const_lv64_C = 64'b0000000000000000000000000000000000000000000000000000000000001100;
parameter ap_const_lv64_D = 64'b0000000000000000000000000000000000000000000000000000000000001101;
parameter ap_const_lv64_E = 64'b0000000000000000000000000000000000000000000000000000000000001110;
parameter ap_const_lv64_F = 64'b0000000000000000000000000000000000000000000000000000000000001111;
parameter ap_const_lv64_10 = 64'b0000000000000000000000000000000000000000000000000000000000010000;
parameter ap_const_lv64_11 = 64'b0000000000000000000000000000000000000000000000000000000000010001;
parameter ap_const_lv64_12 = 64'b0000000000000000000000000000000000000000000000000000000000010010;
parameter ap_const_lv64_13 = 64'b0000000000000000000000000000000000000000000000000000000000010011;
parameter ap_const_lv64_14 = 64'b0000000000000000000000000000000000000000000000000000000000010100;
parameter ap_const_lv64_15 = 64'b0000000000000000000000000000000000000000000000000000000000010101;
parameter ap_const_lv64_16 = 64'b0000000000000000000000000000000000000000000000000000000000010110;
parameter ap_const_lv64_17 = 64'b0000000000000000000000000000000000000000000000000000000000010111;
parameter ap_const_lv64_18 = 64'b0000000000000000000000000000000000000000000000000000000000011000;
parameter ap_const_lv64_19 = 64'b0000000000000000000000000000000000000000000000000000000000011001;
parameter ap_const_lv64_1A = 64'b0000000000000000000000000000000000000000000000000000000000011010;
parameter ap_const_lv64_1B = 64'b0000000000000000000000000000000000000000000000000000000000011011;
parameter ap_const_lv32_80000000 = 32'b10000000000000000000000000000000;
parameter ap_const_lv32_3FC00000 = 32'b00111111110000000000000000000000;
parameter ap_const_lv32_3F000000 = 32'b00111111000000000000000000000000;
parameter ap_const_lv32_40000000 = 32'b01000000000000000000000000000000;
parameter ap_const_lv32_C0000000 = 32'b11000000000000000000000000000000;
parameter ap_const_lv32_1 = 32'b00000000000000000000000000000001;
parameter ap_const_lv32_1F = 32'b00000000000000000000000000011111;
parameter ap_const_lv32_5F3759D5 = 32'b01011111001101110101100111010101;
parameter ap_const_lv2_0 = 2'b00;
parameter ap_const_lv2_1 = 2'b01;
parameter ap_const_lv1_0 = 1'b0;
parameter ap_const_lv32_0 = 32'b00000000000000000000000000000000;
parameter ap_true = 1'b1;
jacobiansPoseComposition_grp_fu_555_ACMP_faddfsub_1 #(
.ID( 1 ),
.NUM_STAGE( 4 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
jacobiansPoseComposition_grp_fu_555_ACMP_faddfsub_1_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_555_p0 ),
.din1( grp_fu_555_p1 ),
.opcode( grp_fu_555_opcode ),
.ce( grp_fu_555_ce ),
.dout( grp_fu_555_p2 )
);
jacobiansPoseComposition_grp_fu_560_ACMP_faddfsub_2 #(
.ID( 2 ),
.NUM_STAGE( 4 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
jacobiansPoseComposition_grp_fu_560_ACMP_faddfsub_2_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_560_p0 ),
.din1( grp_fu_560_p1 ),
.opcode( grp_fu_560_opcode ),
.ce( grp_fu_560_ce ),
.dout( grp_fu_560_p2 )
);
jacobiansPoseComposition_grp_fu_566_ACMP_faddfsub_3 #(
.ID( 3 ),
.NUM_STAGE( 4 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
jacobiansPoseComposition_grp_fu_566_ACMP_faddfsub_3_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_566_p0 ),
.din1( grp_fu_566_p1 ),
.opcode( grp_fu_566_opcode ),
.ce( grp_fu_566_ce ),
.dout( grp_fu_566_p2 )
);
jacobiansPoseComposition_grp_fu_571_ACMP_faddfsub_4 #(
.ID( 4 ),
.NUM_STAGE( 4 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
jacobiansPoseComposition_grp_fu_571_ACMP_faddfsub_4_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_571_p0 ),
.din1( grp_fu_571_p1 ),
.opcode( grp_fu_571_opcode ),
.ce( grp_fu_571_ce ),
.dout( grp_fu_571_p2 )
);
jacobiansPoseComposition_grp_fu_583_ACMP_faddfsub_5 #(
.ID( 5 ),
.NUM_STAGE( 4 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
jacobiansPoseComposition_grp_fu_583_ACMP_faddfsub_5_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_583_p0 ),
.din1( grp_fu_583_p1 ),
.opcode( grp_fu_583_opcode ),
.ce( grp_fu_583_ce ),
.dout( grp_fu_583_p2 )
);
jacobiansPoseComposition_grp_fu_588_ACMP_faddfsub_6 #(
.ID( 6 ),
.NUM_STAGE( 4 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
jacobiansPoseComposition_grp_fu_588_ACMP_faddfsub_6_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_588_p0 ),
.din1( grp_fu_588_p1 ),
.opcode( grp_fu_588_opcode ),
.ce( grp_fu_588_ce ),
.dout( grp_fu_588_p2 )
);
jacobiansPoseComposition_grp_fu_592_ACMP_fadd_7 #(
.ID( 7 ),
.NUM_STAGE( 4 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
jacobiansPoseComposition_grp_fu_592_ACMP_fadd_7_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_592_p0 ),
.din1( grp_fu_592_p1 ),
.ce( grp_fu_592_ce ),
.dout( grp_fu_592_p2 )
);
jacobiansPoseComposition_grp_fu_596_ACMP_fadd_8 #(
.ID( 8 ),
.NUM_STAGE( 4 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
jacobiansPoseComposition_grp_fu_596_ACMP_fadd_8_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_596_p0 ),
.din1( grp_fu_596_p1 ),
.ce( grp_fu_596_ce ),
.dout( grp_fu_596_p2 )
);
jacobiansPoseComposition_grp_fu_600_ACMP_fadd_9 #(
.ID( 9 ),
.NUM_STAGE( 4 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
jacobiansPoseComposition_grp_fu_600_ACMP_fadd_9_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_600_p0 ),
.din1( grp_fu_600_p1 ),
.ce( grp_fu_600_ce ),
.dout( grp_fu_600_p2 )
);
jacobiansPoseComposition_grp_fu_604_ACMP_fadd_10 #(
.ID( 10 ),
.NUM_STAGE( 4 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
jacobiansPoseComposition_grp_fu_604_ACMP_fadd_10_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_604_p0 ),
.din1( grp_fu_604_p1 ),
.ce( grp_fu_604_ce ),
.dout( grp_fu_604_p2 )
);
jacobiansPoseComposition_grp_fu_608_ACMP_fadd_11 #(
.ID( 11 ),
.NUM_STAGE( 4 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
jacobiansPoseComposition_grp_fu_608_ACMP_fadd_11_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_608_p0 ),
.din1( grp_fu_608_p1 ),
.ce( grp_fu_608_ce ),
.dout( grp_fu_608_p2 )
);
jacobiansPoseComposition_grp_fu_612_ACMP_fadd_12 #(
.ID( 12 ),
.NUM_STAGE( 4 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
jacobiansPoseComposition_grp_fu_612_ACMP_fadd_12_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_612_p0 ),
.din1( grp_fu_612_p1 ),
.ce( grp_fu_612_ce ),
.dout( grp_fu_612_p2 )
);
jacobiansPoseComposition_grp_fu_618_ACMP_fadd_13 #(
.ID( 13 ),
.NUM_STAGE( 4 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
jacobiansPoseComposition_grp_fu_618_ACMP_fadd_13_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_618_p0 ),
.din1( grp_fu_618_p1 ),
.ce( grp_fu_618_ce ),
.dout( grp_fu_618_p2 )
);
jacobiansPoseComposition_grp_fu_622_ACMP_fadd_14 #(
.ID( 14 ),
.NUM_STAGE( 4 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
jacobiansPoseComposition_grp_fu_622_ACMP_fadd_14_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_622_p0 ),
.din1( grp_fu_622_p1 ),
.ce( grp_fu_622_ce ),
.dout( grp_fu_622_p2 )
);
jacobiansPoseComposition_grp_fu_626_ACMP_fadd_15 #(
.ID( 15 ),
.NUM_STAGE( 4 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
jacobiansPoseComposition_grp_fu_626_ACMP_fadd_15_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_626_p0 ),
.din1( grp_fu_626_p1 ),
.ce( grp_fu_626_ce ),
.dout( grp_fu_626_p2 )
);
jacobiansPoseComposition_grp_fu_630_ACMP_fadd_16 #(
.ID( 16 ),
.NUM_STAGE( 4 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
jacobiansPoseComposition_grp_fu_630_ACMP_fadd_16_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_630_p0 ),
.din1( grp_fu_630_p1 ),
.ce( grp_fu_630_ce ),
.dout( grp_fu_630_p2 )
);
jacobiansPoseComposition_grp_fu_634_ACMP_fmul_17 #(
.ID( 17 ),
.NUM_STAGE( 4 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
jacobiansPoseComposition_grp_fu_634_ACMP_fmul_17_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_634_p0 ),
.din1( grp_fu_634_p1 ),
.ce( grp_fu_634_ce ),
.dout( grp_fu_634_p2 )
);
jacobiansPoseComposition_grp_fu_640_ACMP_fmul_18 #(
.ID( 18 ),
.NUM_STAGE( 4 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
jacobiansPoseComposition_grp_fu_640_ACMP_fmul_18_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_640_p0 ),
.din1( grp_fu_640_p1 ),
.ce( grp_fu_640_ce ),
.dout( grp_fu_640_p2 )
);
jacobiansPoseComposition_grp_fu_652_ACMP_fmul_19 #(
.ID( 19 ),
.NUM_STAGE( 4 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
jacobiansPoseComposition_grp_fu_652_ACMP_fmul_19_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_652_p0 ),
.din1( grp_fu_652_p1 ),
.ce( grp_fu_652_ce ),
.dout( grp_fu_652_p2 )
);
jacobiansPoseComposition_grp_fu_658_ACMP_fmul_20 #(
.ID( 20 ),
.NUM_STAGE( 4 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
jacobiansPoseComposition_grp_fu_658_ACMP_fmul_20_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_658_p0 ),
.din1( grp_fu_658_p1 ),
.ce( grp_fu_658_ce ),
.dout( grp_fu_658_p2 )
);
jacobiansPoseComposition_grp_fu_663_ACMP_fmul_21 #(
.ID( 21 ),
.NUM_STAGE( 4 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
jacobiansPoseComposition_grp_fu_663_ACMP_fmul_21_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_663_p0 ),
.din1( grp_fu_663_p1 ),
.ce( grp_fu_663_ce ),
.dout( grp_fu_663_p2 )
);
jacobiansPoseComposition_grp_fu_668_ACMP_fmul_22 #(
.ID( 22 ),
.NUM_STAGE( 4 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
jacobiansPoseComposition_grp_fu_668_ACMP_fmul_22_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_668_p0 ),
.din1( grp_fu_668_p1 ),
.ce( grp_fu_668_ce ),
.dout( grp_fu_668_p2 )
);
jacobiansPoseComposition_grp_fu_673_ACMP_fmul_23 #(
.ID( 23 ),
.NUM_STAGE( 4 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
jacobiansPoseComposition_grp_fu_673_ACMP_fmul_23_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_673_p0 ),
.din1( grp_fu_673_p1 ),
.ce( grp_fu_673_ce ),
.dout( grp_fu_673_p2 )
);
jacobiansPoseComposition_grp_fu_678_ACMP_fmul_24 #(
.ID( 24 ),
.NUM_STAGE( 4 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
jacobiansPoseComposition_grp_fu_678_ACMP_fmul_24_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_678_p0 ),
.din1( grp_fu_678_p1 ),
.ce( grp_fu_678_ce ),
.dout( grp_fu_678_p2 )
);
jacobiansPoseComposition_grp_fu_683_ACMP_fmul_25 #(
.ID( 25 ),
.NUM_STAGE( 4 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
jacobiansPoseComposition_grp_fu_683_ACMP_fmul_25_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_683_p0 ),
.din1( grp_fu_683_p1 ),
.ce( grp_fu_683_ce ),
.dout( grp_fu_683_p2 )
);
jacobiansPoseComposition_grp_fu_692_ACMP_fmul_26 #(
.ID( 26 ),
.NUM_STAGE( 4 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
jacobiansPoseComposition_grp_fu_692_ACMP_fmul_26_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_692_p0 ),
.din1( grp_fu_692_p1 ),
.ce( grp_fu_692_ce ),
.dout( grp_fu_692_p2 )
);
jacobiansPoseComposition_grp_fu_696_ACMP_fmul_27 #(
.ID( 27 ),
.NUM_STAGE( 4 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
jacobiansPoseComposition_grp_fu_696_ACMP_fmul_27_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_696_p0 ),
.din1( grp_fu_696_p1 ),
.ce( grp_fu_696_ce ),
.dout( grp_fu_696_p2 )
);
jacobiansPoseComposition_grp_fu_701_ACMP_fmul_28 #(
.ID( 28 ),
.NUM_STAGE( 4 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
jacobiansPoseComposition_grp_fu_701_ACMP_fmul_28_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_701_p0 ),
.din1( grp_fu_701_p1 ),
.ce( grp_fu_701_ce ),
.dout( grp_fu_701_p2 )
);
jacobiansPoseComposition_grp_fu_705_ACMP_fmul_29 #(
.ID( 29 ),
.NUM_STAGE( 4 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
jacobiansPoseComposition_grp_fu_705_ACMP_fmul_29_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_705_p0 ),
.din1( grp_fu_705_p1 ),
.ce( grp_fu_705_ce ),
.dout( grp_fu_705_p2 )
);
jacobiansPoseComposition_grp_fu_709_ACMP_fmul_30 #(
.ID( 30 ),
.NUM_STAGE( 4 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
jacobiansPoseComposition_grp_fu_709_ACMP_fmul_30_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_709_p0 ),
.din1( grp_fu_709_p1 ),
.ce( grp_fu_709_ce ),
.dout( grp_fu_709_p2 )
);
jacobiansPoseComposition_grp_fu_714_ACMP_fmul_31 #(
.ID( 31 ),
.NUM_STAGE( 4 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
jacobiansPoseComposition_grp_fu_714_ACMP_fmul_31_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_714_p0 ),
.din1( grp_fu_714_p1 ),
.ce( grp_fu_714_ce ),
.dout( grp_fu_714_p2 )
);
jacobiansPoseComposition_grp_fu_718_ACMP_fmul_32 #(
.ID( 32 ),
.NUM_STAGE( 4 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
jacobiansPoseComposition_grp_fu_718_ACMP_fmul_32_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_718_p0 ),
.din1( grp_fu_718_p1 ),
.ce( grp_fu_718_ce ),
.dout( grp_fu_718_p2 )
);
jacobiansPoseComposition_grp_fu_722_ACMP_fmul_33 #(
.ID( 33 ),
.NUM_STAGE( 4 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
jacobiansPoseComposition_grp_fu_722_ACMP_fmul_33_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_722_p0 ),
.din1( grp_fu_722_p1 ),
.ce( grp_fu_722_ce ),
.dout( grp_fu_722_p2 )
);
jacobiansPoseComposition_grp_fu_727_ACMP_fmul_34 #(
.ID( 34 ),
.NUM_STAGE( 4 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
jacobiansPoseComposition_grp_fu_727_ACMP_fmul_34_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_727_p0 ),
.din1( grp_fu_727_p1 ),
.ce( grp_fu_727_ce ),
.dout( grp_fu_727_p2 )
);
jacobiansPoseComposition_grp_fu_732_ACMP_fmul_35 #(
.ID( 35 ),
.NUM_STAGE( 4 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
jacobiansPoseComposition_grp_fu_732_ACMP_fmul_35_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_732_p0 ),
.din1( grp_fu_732_p1 ),
.ce( grp_fu_732_ce ),
.dout( grp_fu_732_p2 )
);
jacobiansPoseComposition_grp_fu_737_ACMP_fmul_36 #(
.ID( 36 ),
.NUM_STAGE( 4 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
jacobiansPoseComposition_grp_fu_737_ACMP_fmul_36_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_737_p0 ),
.din1( grp_fu_737_p1 ),
.ce( grp_fu_737_ce ),
.dout( grp_fu_737_p2 )
);
jacobiansPoseComposition_grp_fu_742_ACMP_fmul_37 #(
.ID( 37 ),
.NUM_STAGE( 4 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
jacobiansPoseComposition_grp_fu_742_ACMP_fmul_37_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_742_p0 ),
.din1( grp_fu_742_p1 ),
.ce( grp_fu_742_ce ),
.dout( grp_fu_742_p2 )
);
jacobiansPoseComposition_grp_fu_747_ACMP_fmul_38 #(
.ID( 38 ),
.NUM_STAGE( 4 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
jacobiansPoseComposition_grp_fu_747_ACMP_fmul_38_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_747_p0 ),
.din1( grp_fu_747_p1 ),
.ce( grp_fu_747_ce ),
.dout( grp_fu_747_p2 )
);
jacobiansPoseComposition_grp_fu_755_ACMP_fmul_39 #(
.ID( 39 ),
.NUM_STAGE( 4 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
jacobiansPoseComposition_grp_fu_755_ACMP_fmul_39_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_755_p0 ),
.din1( grp_fu_755_p1 ),
.ce( grp_fu_755_ce ),
.dout( grp_fu_755_p2 )
);
jacobiansPoseComposition_grp_fu_759_ACMP_fmul_40 #(
.ID( 40 ),
.NUM_STAGE( 4 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
jacobiansPoseComposition_grp_fu_759_ACMP_fmul_40_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_759_p0 ),
.din1( grp_fu_759_p1 ),
.ce( grp_fu_759_ce ),
.dout( grp_fu_759_p2 )
);
jacobiansPoseComposition_grp_fu_763_ACMP_fmul_41 #(
.ID( 41 ),
.NUM_STAGE( 4 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
jacobiansPoseComposition_grp_fu_763_ACMP_fmul_41_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_763_p0 ),
.din1( grp_fu_763_p1 ),
.ce( grp_fu_763_ce ),
.dout( grp_fu_763_p2 )
);
jacobiansPoseComposition_grp_fu_767_ACMP_fmul_42 #(
.ID( 42 ),
.NUM_STAGE( 4 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
jacobiansPoseComposition_grp_fu_767_ACMP_fmul_42_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_767_p0 ),
.din1( grp_fu_767_p1 ),
.ce( grp_fu_767_ce ),
.dout( grp_fu_767_p2 )
);
jacobiansPoseComposition_grp_fu_771_ACMP_fmul_43 #(
.ID( 43 ),
.NUM_STAGE( 4 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
jacobiansPoseComposition_grp_fu_771_ACMP_fmul_43_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_771_p0 ),
.din1( grp_fu_771_p1 ),
.ce( grp_fu_771_ce ),
.dout( grp_fu_771_p2 )
);
jacobiansPoseComposition_grp_fu_775_ACMP_fmul_44 #(
.ID( 44 ),
.NUM_STAGE( 4 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
jacobiansPoseComposition_grp_fu_775_ACMP_fmul_44_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_775_p0 ),
.din1( grp_fu_775_p1 ),
.ce( grp_fu_775_ce ),
.dout( grp_fu_775_p2 )
);
jacobiansPoseComposition_grp_fu_779_ACMP_fmul_45 #(
.ID( 45 ),
.NUM_STAGE( 4 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
jacobiansPoseComposition_grp_fu_779_ACMP_fmul_45_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_779_p0 ),
.din1( grp_fu_779_p1 ),
.ce( grp_fu_779_ce ),
.dout( grp_fu_779_p2 )
);
jacobiansPoseComposition_grp_fu_783_ACMP_fmul_46 #(
.ID( 46 ),
.NUM_STAGE( 4 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
jacobiansPoseComposition_grp_fu_783_ACMP_fmul_46_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_783_p0 ),
.din1( grp_fu_783_p1 ),
.ce( grp_fu_783_ce ),
.dout( grp_fu_783_p2 )
);
jacobiansPoseComposition_grp_fu_787_ACMP_fmul_47 #(
.ID( 47 ),
.NUM_STAGE( 4 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
jacobiansPoseComposition_grp_fu_787_ACMP_fmul_47_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_787_p0 ),
.din1( grp_fu_787_p1 ),
.ce( grp_fu_787_ce ),
.dout( grp_fu_787_p2 )
);
jacobiansPoseComposition_grp_fu_791_ACMP_fmul_48 #(
.ID( 48 ),
.NUM_STAGE( 4 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
jacobiansPoseComposition_grp_fu_791_ACMP_fmul_48_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_791_p0 ),
.din1( grp_fu_791_p1 ),
.ce( grp_fu_791_ce ),
.dout( grp_fu_791_p2 )
);
/// ap_CS_fsm assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_CS_fsm
if (ap_rst == 1'b1) begin
ap_CS_fsm <= ap_ST_st0_fsm_0;
end else begin
ap_CS_fsm <= ap_NS_fsm;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_ST_st14_fsm_14 == ap_CS_fsm)) begin
X_plus_U_qz_reg_1782 <= grp_fu_555_p2;
end
if (((ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm))) begin
reg_1006 <= grp_fu_555_p2;
end
if (((ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st22_fsm_22 == ap_CS_fsm))) begin
reg_1013 <= grp_fu_571_p2;
end
if (((ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm))) begin
reg_1019 <= grp_fu_652_p2;
end
if (((ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm))) begin
reg_1038 <= grp_fu_566_p2;
end
if (((ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm))) begin
reg_1047 <= grp_fu_652_p2;
end
if (((ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm))) begin
reg_1057 <= grp_fu_658_p2;
end
if (((ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm))) begin
reg_1072 <= grp_fu_663_p2;
end
if (((ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm))) begin
reg_1085 <= grp_fu_668_p2;
end
if (((ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm))) begin
reg_1098 <= grp_fu_673_p2;
end
if (((ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm))) begin
reg_1110 <= grp_fu_678_p2;
end
if (((ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm))) begin
reg_1123 <= grp_fu_683_p2;
end
if (((ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm))) begin
reg_1136 <= grp_fu_560_p2;
end
if (((ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm))) begin
reg_1144 <= grp_fu_566_p2;
end
if (((ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm))) begin
reg_1152 <= grp_fu_571_p2;
end
if (((ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm))) begin
reg_1157 <= grp_fu_583_p2;
end
if (((ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm))) begin
reg_1167 <= grp_fu_663_p2;
end
if (((ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm))) begin
reg_1178 <= grp_fu_588_p2;
end
if (((ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm))) begin
reg_1186 <= grp_fu_592_p2;
end
if (((ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm))) begin
reg_1194 <= grp_fu_596_p2;
end
if (((ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm))) begin
reg_1201 <= grp_fu_692_p2;
end
if (((ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm))) begin
reg_1212 <= grp_fu_600_p2;
end
if (((ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm))) begin
reg_1220 <= grp_fu_696_p2;
end
if (((ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm))) begin
reg_1231 <= grp_fu_701_p2;
end
if (((ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm))) begin
reg_1242 <= grp_fu_705_p2;
end
if (((ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm))) begin
reg_1252 <= grp_fu_709_p2;
end
if (((ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm))) begin
reg_1261 <= grp_fu_673_p2;
end
if (((ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm))) begin
reg_1270 <= grp_fu_604_p2;
end
if (((ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm))) begin
reg_1277 <= grp_fu_608_p2;
end
if (((ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm))) begin
reg_1284 <= grp_fu_612_p2;
end
if (((ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm))) begin
reg_1291 <= grp_fu_583_p2;
end
if (((ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm))) begin
reg_1299 <= grp_fu_714_p2;
end
if (((ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm))) begin
reg_1307 <= grp_fu_718_p2;
end
if (((ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm))) begin
reg_1315 <= grp_fu_722_p2;
end
if (((ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm))) begin
reg_1325 <= grp_fu_727_p2;
end
if (((ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm))) begin
reg_1335 <= grp_fu_732_p2;
end
if (((ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm))) begin
reg_1345 <= grp_fu_737_p2;
end
if (((ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm))) begin
reg_1355 <= grp_fu_742_p2;
end
if (((ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm))) begin
reg_1365 <= grp_fu_747_p2;
end
if (((ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm))) begin
reg_1375 <= grp_fu_658_p2;
end
if (((ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm))) begin
reg_1383 <= grp_fu_668_p2;
end
if (((ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm))) begin
reg_1394 <= grp_fu_678_p2;
end
if (((ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm))) begin
reg_1403 <= grp_fu_683_p2;
end
if (((ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm))) begin
reg_1414 <= grp_fu_692_p2;
end
if (((ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm))) begin
reg_1425 <= grp_fu_696_p2;
end
if (((ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm))) begin
reg_1435 <= grp_fu_701_p2;
end
if (((ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm))) begin
reg_1444 <= grp_fu_705_p2;
end
if (((ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm))) begin
reg_1454 <= grp_fu_696_p2;
end
if (((ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm))) begin
reg_1460 <= grp_fu_701_p2;
end
if (((ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm))) begin
reg_1467 <= grp_fu_705_p2;
end
if (((ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm))) begin
reg_1473 <= grp_fu_709_p2;
end
if (((ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm))) begin
reg_1479 <= grp_fu_714_p2;
end
if (((ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm))) begin
reg_1485 <= grp_fu_718_p2;
end
if (((ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm))) begin
reg_1491 <= grp_fu_755_p2;
end
if (((ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm))) begin
reg_1497 <= grp_fu_759_p2;
end
if (((ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm))) begin
reg_1503 <= grp_fu_763_p2;
end
if (((ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm))) begin
reg_1509 <= grp_fu_767_p2;
end
if (((ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm))) begin
reg_1515 <= grp_fu_771_p2;
end
if (((ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm))) begin
reg_1521 <= grp_fu_709_p2;
end
if (((ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm))) begin
reg_1530 <= grp_fu_658_p2;
end
if (((ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm))) begin
reg_1536 <= grp_fu_678_p2;
end
if (((ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm))) begin
reg_1542 <= grp_fu_588_p2;
end
if (((ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm))) begin
reg_1547 <= grp_fu_592_p2;
end
if (((ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm))) begin
reg_1552 <= grp_fu_596_p2;
end
if (((ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm))) begin
reg_1557 <= grp_fu_600_p2;
end
if (((ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm))) begin
reg_1562 <= grp_fu_604_p2;
end
if (((ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm))) begin
reg_1567 <= grp_fu_608_p2;
end
if (((ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm))) begin
reg_1572 <= grp_fu_612_p2;
end
if (((ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm))) begin
reg_1577 <= grp_fu_618_p2;
end
if (((ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm))) begin
reg_1583 <= grp_fu_622_p2;
end
if (((ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm))) begin
reg_1589 <= grp_fu_626_p2;
end
if (((ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm))) begin
reg_1595 <= grp_fu_630_p2;
end
if (((ap_ST_st4_fsm_4 == ap_CS_fsm) | (ap_ST_st12_fsm_12 == ap_CS_fsm) | (ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm))) begin
reg_795 <= grp_fu_634_p2;
end
if (((ap_ST_st4_fsm_4 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm))) begin
reg_829 <= grp_fu_640_p2;
end
if (((ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st6_fsm_6 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm))) begin
reg_850 <= grp_fu_555_p2;
end
if (((ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st6_fsm_6 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm))) begin
reg_869 <= grp_fu_560_p2;
end
if (((ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st8_fsm_8 == ap_CS_fsm) | (ap_ST_st16_fsm_16 == ap_CS_fsm))) begin
reg_889 <= grp_fu_555_p2;
end
if (((ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st8_fsm_8 == ap_CS_fsm) | (ap_ST_st14_fsm_14 == ap_CS_fsm) | (ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm))) begin
reg_903 <= grp_fu_634_p2;
end
if (((ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st10_fsm_10 == ap_CS_fsm))) begin
reg_931 <= grp_fu_555_p2;
end
if (((ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st10_fsm_10 == ap_CS_fsm))) begin
reg_943 <= grp_fu_640_p2;
end
if (((ap_ST_st12_fsm_12 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm))) begin
reg_954 <= grp_fu_560_p2;
end
if (((ap_ST_st12_fsm_12 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm))) begin
reg_961 <= grp_fu_566_p2;
end
if (((ap_ST_st14_fsm_14 == ap_CS_fsm) | (ap_ST_st22_fsm_22 == ap_CS_fsm))) begin
reg_976 <= grp_fu_560_p2;
end
if (((ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st16_fsm_16 == ap_CS_fsm))) begin
reg_983 <= grp_fu_571_p2;
end
if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm))) begin
reg_990 <= grp_fu_560_p2;
end
if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st22_fsm_22 == ap_CS_fsm))) begin
reg_999 <= grp_fu_566_p2;
end
if ((ap_ST_st29_fsm_29 == ap_CS_fsm)) begin
tmp1_i1_reg_1804 <= i_fu_1618_p2;
end
if ((ap_ST_st35_fsm_35 == ap_CS_fsm)) begin
tmp1_i_reg_1838 <= i_1_fu_1646_p2;
end
if ((ap_ST_st52_fsm_52 == ap_CS_fsm)) begin
tmp_163_reg_1876 <= grp_fu_683_p2;
end
if ((ap_ST_st52_fsm_52 == ap_CS_fsm)) begin
tmp_169_reg_1881 <= grp_fu_692_p2;
end
if ((ap_ST_st58_fsm_58 == ap_CS_fsm)) begin
tmp_239_reg_1902 <= grp_fu_652_p2;
end
if ((ap_ST_st58_fsm_58 == ap_CS_fsm)) begin
tmp_253_reg_1907 <= grp_fu_673_p2;
end
if ((ap_ST_st46_fsm_46 == ap_CS_fsm)) begin
tmp_27_reg_1869 <= grp_fu_571_p2;
end
if ((ap_ST_st58_fsm_58 == ap_CS_fsm)) begin
tmp_281_reg_1912 <= grp_fu_714_p2;
end
if ((ap_ST_st58_fsm_58 == ap_CS_fsm)) begin
tmp_324_reg_1917 <= grp_fu_775_p2;
end
if ((ap_ST_st58_fsm_58 == ap_CS_fsm)) begin
tmp_330_reg_1922 <= grp_fu_779_p2;
end
if ((ap_ST_st58_fsm_58 == ap_CS_fsm)) begin
tmp_331_reg_1927 <= grp_fu_783_p2;
end
if ((ap_ST_st58_fsm_58 == ap_CS_fsm)) begin
tmp_337_reg_1932 <= grp_fu_787_p2;
end
if ((ap_ST_st58_fsm_58 == ap_CS_fsm)) begin
tmp_338_reg_1937 <= grp_fu_791_p2;
end
if ((ap_ST_st54_fsm_54 == ap_CS_fsm)) begin
tmp_42_reg_1886 <= grp_fu_714_p2;
end
if ((ap_ST_st54_fsm_54 == ap_CS_fsm)) begin
tmp_43_reg_1894 <= grp_fu_718_p2;
end
if ((ap_ST_st12_fsm_12 == ap_CS_fsm)) begin
tmp_48_reg_1776 <= grp_fu_555_p2;
end
if ((ap_ST_st18_fsm_18 == ap_CS_fsm)) begin
tmp_4_reg_1793 <= grp_fu_555_p2;
end
if ((ap_ST_st31_fsm_31 == ap_CS_fsm)) begin
tmp_52_reg_1809 <= {{i_2_fu_1629_p1[ap_const_lv32_1F : ap_const_lv32_1]}};
end
if ((ap_ST_st25_fsm_25 == ap_CS_fsm)) begin
tmp_53_reg_1799 <= {{i_3_fu_1601_p1[ap_const_lv32_1F : ap_const_lv32_1]}};
end
if ((ap_ST_st10_fsm_10 == ap_CS_fsm)) begin
tmp_reg_1756 <= grp_fu_634_p2;
end
end
/// ap_NS_fsm assign process. ///
always @ (ap_start or ap_CS_fsm)
begin
if (((ap_ST_st78_fsm_78 == ap_CS_fsm) & ~(ap_const_logic_1 == ap_start))) begin
ap_NS_fsm = ap_ST_st0_fsm_0;
end else if ((ap_ST_st77_fsm_77 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st78_fsm_78;
end else if ((ap_ST_st76_fsm_76 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st77_fsm_77;
end else if ((ap_ST_st75_fsm_75 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st76_fsm_76;
end else if ((ap_ST_st74_fsm_74 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st75_fsm_75;
end else if ((ap_ST_st73_fsm_73 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st74_fsm_74;
end else if ((ap_ST_st72_fsm_72 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st73_fsm_73;
end else if ((ap_ST_st71_fsm_71 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st72_fsm_72;
end else if ((ap_ST_st70_fsm_70 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st71_fsm_71;
end else if ((ap_ST_st69_fsm_69 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st70_fsm_70;
end else if ((ap_ST_st68_fsm_68 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st69_fsm_69;
end else if ((ap_ST_st67_fsm_67 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st68_fsm_68;
end else if ((ap_ST_st66_fsm_66 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st67_fsm_67;
end else if ((ap_ST_st65_fsm_65 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st66_fsm_66;
end else if ((ap_ST_st64_fsm_64 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st65_fsm_65;
end else if ((ap_ST_st63_fsm_63 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st64_fsm_64;
end else if ((ap_ST_st62_fsm_62 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st63_fsm_63;
end else if ((ap_ST_st61_fsm_61 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st62_fsm_62;
end else if ((ap_ST_st60_fsm_60 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st61_fsm_61;
end else if ((ap_ST_st59_fsm_59 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st60_fsm_60;
end else if ((ap_ST_st58_fsm_58 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st59_fsm_59;
end else if ((ap_ST_st57_fsm_57 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st58_fsm_58;
end else if ((ap_ST_st56_fsm_56 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st57_fsm_57;
end else if ((ap_ST_st55_fsm_55 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st56_fsm_56;
end else if ((ap_ST_st54_fsm_54 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st55_fsm_55;
end else if ((ap_ST_st53_fsm_53 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st54_fsm_54;
end else if ((ap_ST_st52_fsm_52 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st53_fsm_53;
end else if ((ap_ST_st51_fsm_51 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st52_fsm_52;
end else if ((ap_ST_st50_fsm_50 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st51_fsm_51;
end else if ((ap_ST_st49_fsm_49 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st50_fsm_50;
end else if ((ap_ST_st48_fsm_48 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st49_fsm_49;
end else if ((ap_ST_st47_fsm_47 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st48_fsm_48;
end else if ((ap_ST_st46_fsm_46 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st47_fsm_47;
end else if ((ap_ST_st45_fsm_45 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st46_fsm_46;
end else if ((ap_ST_st44_fsm_44 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st45_fsm_45;
end else if ((ap_ST_st43_fsm_43 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st44_fsm_44;
end else if ((ap_ST_st42_fsm_42 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st43_fsm_43;
end else if ((ap_ST_st41_fsm_41 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st42_fsm_42;
end else if ((ap_ST_st40_fsm_40 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st41_fsm_41;
end else if ((ap_ST_st39_fsm_39 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st40_fsm_40;
end else if ((ap_ST_st38_fsm_38 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st39_fsm_39;
end else if ((ap_ST_st37_fsm_37 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st38_fsm_38;
end else if ((ap_ST_st36_fsm_36 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st37_fsm_37;
end else if ((ap_ST_st35_fsm_35 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st36_fsm_36;
end else if ((ap_ST_st34_fsm_34 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st35_fsm_35;
end else if ((ap_ST_st33_fsm_33 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st34_fsm_34;
end else if ((ap_ST_st32_fsm_32 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st33_fsm_33;
end else if ((ap_ST_st31_fsm_31 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st32_fsm_32;
end else if ((ap_ST_st30_fsm_30 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st31_fsm_31;
end else if ((ap_ST_st29_fsm_29 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st30_fsm_30;
end else if ((ap_ST_st28_fsm_28 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st29_fsm_29;
end else if ((ap_ST_st27_fsm_27 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st28_fsm_28;
end else if ((ap_ST_st26_fsm_26 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st27_fsm_27;
end else if ((ap_ST_st25_fsm_25 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st26_fsm_26;
end else if ((ap_ST_st24_fsm_24 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st25_fsm_25;
end else if ((ap_ST_st23_fsm_23 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st24_fsm_24;
end else if ((ap_ST_st22_fsm_22 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st23_fsm_23;
end else if ((ap_ST_st21_fsm_21 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st22_fsm_22;
end else if ((ap_ST_st20_fsm_20 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st21_fsm_21;
end else if ((ap_ST_st19_fsm_19 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st20_fsm_20;
end else if ((ap_ST_st18_fsm_18 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st19_fsm_19;
end else if ((ap_ST_st17_fsm_17 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st18_fsm_18;
end else if ((ap_ST_st16_fsm_16 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st17_fsm_17;
end else if ((ap_ST_st15_fsm_15 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st16_fsm_16;
end else if ((ap_ST_st14_fsm_14 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st15_fsm_15;
end else if ((ap_ST_st13_fsm_13 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st14_fsm_14;
end else if ((ap_ST_st12_fsm_12 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st13_fsm_13;
end else if ((ap_ST_st11_fsm_11 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st12_fsm_12;
end else if ((ap_ST_st10_fsm_10 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st11_fsm_11;
end else if ((ap_ST_st9_fsm_9 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st10_fsm_10;
end else if ((ap_ST_st8_fsm_8 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st9_fsm_9;
end else if ((ap_ST_st7_fsm_7 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st8_fsm_8;
end else if ((ap_ST_st6_fsm_6 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st7_fsm_7;
end else if ((ap_ST_st5_fsm_5 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st6_fsm_6;
end else if ((ap_ST_st4_fsm_4 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st5_fsm_5;
end else if ((ap_ST_st3_fsm_3 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st4_fsm_4;
end else if ((ap_ST_st2_fsm_2 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st3_fsm_3;
end else if ((ap_ST_st1_fsm_1 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st2_fsm_2;
end else if ((((ap_ST_st0_fsm_0 == ap_CS_fsm) & (ap_const_logic_1 == ap_start)) | ((ap_ST_st78_fsm_78 == ap_CS_fsm) & (ap_const_logic_1 == ap_start)))) begin
ap_NS_fsm = ap_ST_st1_fsm_1;
end else begin
ap_NS_fsm = ap_CS_fsm;
end
end
/// ap_done assign process. ///
always @ (ap_CS_fsm)
begin
if ((ap_ST_st78_fsm_78 == ap_CS_fsm)) begin
ap_done = ap_const_logic_1;
end else begin
ap_done = ap_const_logic_0;
end
end
/// ap_idle assign process. ///
always @ (ap_CS_fsm)
begin
if ((ap_ST_st0_fsm_0 == ap_CS_fsm)) begin
ap_idle = ap_const_logic_1;
end else begin
ap_idle = ap_const_logic_0;
end
end
/// df_dx_address0 assign process. ///
always @ (ap_CS_fsm)
begin
if ((ap_ST_st78_fsm_78 == ap_CS_fsm)) begin
df_dx_address0 = ap_const_lv64_1A;
end else if ((ap_ST_st77_fsm_77 == ap_CS_fsm)) begin
df_dx_address0 = ap_const_lv64_18;
end else if ((ap_ST_st76_fsm_76 == ap_CS_fsm)) begin
df_dx_address0 = ap_const_lv64_16;
end else if ((ap_ST_st75_fsm_75 == ap_CS_fsm)) begin
df_dx_address0 = ap_const_lv64_14;
end else if ((ap_ST_st74_fsm_74 == ap_CS_fsm)) begin
df_dx_address0 = ap_const_lv64_12;
end else if ((ap_ST_st73_fsm_73 == ap_CS_fsm)) begin
df_dx_address0 = ap_const_lv64_10;
end else if ((ap_ST_st72_fsm_72 == ap_CS_fsm)) begin
df_dx_address0 = ap_const_lv64_E;
end else if ((ap_ST_st71_fsm_71 == ap_CS_fsm)) begin
df_dx_address0 = ap_const_lv64_C;
end else if ((ap_ST_st70_fsm_70 == ap_CS_fsm)) begin
df_dx_address0 = ap_const_lv64_A;
end else if ((ap_ST_st69_fsm_69 == ap_CS_fsm)) begin
df_dx_address0 = ap_const_lv64_8;
end else if ((ap_ST_st68_fsm_68 == ap_CS_fsm)) begin
df_dx_address0 = ap_const_lv64_6;
end else if ((ap_ST_st67_fsm_67 == ap_CS_fsm)) begin
df_dx_address0 = ap_const_lv64_4;
end else if ((ap_ST_st66_fsm_66 == ap_CS_fsm)) begin
df_dx_address0 = ap_const_lv64_2;
end else if ((ap_ST_st65_fsm_65 == ap_CS_fsm)) begin
df_dx_address0 = ap_const_lv64_0;
end else begin
df_dx_address0 = ap_const_lv64_1A;
end
end
/// df_dx_address1 assign process. ///
always @ (ap_CS_fsm)
begin
if ((ap_ST_st78_fsm_78 == ap_CS_fsm)) begin
df_dx_address1 = ap_const_lv64_1B;
end else if ((ap_ST_st77_fsm_77 == ap_CS_fsm)) begin
df_dx_address1 = ap_const_lv64_19;
end else if ((ap_ST_st76_fsm_76 == ap_CS_fsm)) begin
df_dx_address1 = ap_const_lv64_17;
end else if ((ap_ST_st75_fsm_75 == ap_CS_fsm)) begin
df_dx_address1 = ap_const_lv64_15;
end else if ((ap_ST_st74_fsm_74 == ap_CS_fsm)) begin
df_dx_address1 = ap_const_lv64_13;
end else if ((ap_ST_st73_fsm_73 == ap_CS_fsm)) begin
df_dx_address1 = ap_const_lv64_11;
end else if ((ap_ST_st72_fsm_72 == ap_CS_fsm)) begin
df_dx_address1 = ap_const_lv64_F;
end else if ((ap_ST_st71_fsm_71 == ap_CS_fsm)) begin
df_dx_address1 = ap_const_lv64_D;
end else if ((ap_ST_st70_fsm_70 == ap_CS_fsm)) begin
df_dx_address1 = ap_const_lv64_B;
end else if ((ap_ST_st69_fsm_69 == ap_CS_fsm)) begin
df_dx_address1 = ap_const_lv64_9;
end else if ((ap_ST_st68_fsm_68 == ap_CS_fsm)) begin
df_dx_address1 = ap_const_lv64_7;
end else if ((ap_ST_st67_fsm_67 == ap_CS_fsm)) begin
df_dx_address1 = ap_const_lv64_5;
end else if ((ap_ST_st66_fsm_66 == ap_CS_fsm)) begin
df_dx_address1 = ap_const_lv64_3;
end else if ((ap_ST_st65_fsm_65 == ap_CS_fsm)) begin
df_dx_address1 = ap_const_lv64_1;
end else begin
df_dx_address1 = ap_const_lv64_1B;
end
end
/// df_dx_ce0 assign process. ///
always @ (ap_CS_fsm)
begin
if (((ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st65_fsm_65 == ap_CS_fsm) | (ap_ST_st67_fsm_67 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st69_fsm_69 == ap_CS_fsm) | (ap_ST_st71_fsm_71 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st73_fsm_73 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st75_fsm_75 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st77_fsm_77 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm))) begin
df_dx_ce0 = ap_const_logic_1;
end else begin
df_dx_ce0 = ap_const_logic_0;
end
end
/// df_dx_ce1 assign process. ///
always @ (ap_CS_fsm)
begin
if (((ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st65_fsm_65 == ap_CS_fsm) | (ap_ST_st67_fsm_67 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st69_fsm_69 == ap_CS_fsm) | (ap_ST_st71_fsm_71 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st73_fsm_73 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st75_fsm_75 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st77_fsm_77 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm))) begin
df_dx_ce1 = ap_const_logic_1;
end else begin
df_dx_ce1 = ap_const_logic_0;
end
end
/// df_dx_d0 assign process. ///
always @ (ap_CS_fsm or reg_850 or reg_889 or reg_961 or reg_999 or reg_1157 or reg_1186 or reg_1212 or reg_1277 or reg_1577 or reg_1589)
begin
if ((ap_ST_st78_fsm_78 == ap_CS_fsm)) begin
df_dx_d0 = reg_1589;
end else if ((ap_ST_st77_fsm_77 == ap_CS_fsm)) begin
df_dx_d0 = reg_1577;
end else if ((ap_ST_st72_fsm_72 == ap_CS_fsm)) begin
df_dx_d0 = reg_961;
end else if ((ap_ST_st71_fsm_71 == ap_CS_fsm)) begin
df_dx_d0 = reg_850;
end else if (((ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm))) begin
df_dx_d0 = reg_1277;
end else if (((ap_ST_st69_fsm_69 == ap_CS_fsm) | (ap_ST_st75_fsm_75 == ap_CS_fsm))) begin
df_dx_d0 = reg_1212;
end else if (((ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm))) begin
df_dx_d0 = reg_1186;
end else if (((ap_ST_st67_fsm_67 == ap_CS_fsm) | (ap_ST_st73_fsm_73 == ap_CS_fsm))) begin
df_dx_d0 = reg_1157;
end else if ((ap_ST_st66_fsm_66 == ap_CS_fsm)) begin
df_dx_d0 = reg_999;
end else if ((ap_ST_st65_fsm_65 == ap_CS_fsm)) begin
df_dx_d0 = reg_889;
end else begin
df_dx_d0 = reg_1589;
end
end
/// df_dx_d1 assign process. ///
always @ (ap_CS_fsm or reg_869 or reg_983 or reg_1178 or reg_1194 or reg_1270 or reg_1284 or reg_1583 or reg_1595)
begin
if ((ap_ST_st78_fsm_78 == ap_CS_fsm)) begin
df_dx_d1 = reg_1595;
end else if ((ap_ST_st77_fsm_77 == ap_CS_fsm)) begin
df_dx_d1 = reg_1583;
end else if (((ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm))) begin
df_dx_d1 = reg_1284;
end else if (((ap_ST_st69_fsm_69 == ap_CS_fsm) | (ap_ST_st75_fsm_75 == ap_CS_fsm))) begin
df_dx_d1 = reg_1270;
end else if (((ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm))) begin
df_dx_d1 = reg_1194;
end else if (((ap_ST_st67_fsm_67 == ap_CS_fsm) | (ap_ST_st73_fsm_73 == ap_CS_fsm))) begin
df_dx_d1 = reg_1178;
end else if (((ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm))) begin
df_dx_d1 = reg_983;
end else if (((ap_ST_st65_fsm_65 == ap_CS_fsm) | (ap_ST_st71_fsm_71 == ap_CS_fsm))) begin
df_dx_d1 = reg_869;
end else begin
df_dx_d1 = reg_1595;
end
end
/// df_dx_we0 assign process. ///
always @ (ap_CS_fsm)
begin
if (((ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st65_fsm_65 == ap_CS_fsm) | (ap_ST_st67_fsm_67 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st69_fsm_69 == ap_CS_fsm) | (ap_ST_st71_fsm_71 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st73_fsm_73 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st75_fsm_75 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st77_fsm_77 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm))) begin
df_dx_we0 = ap_const_logic_1;
end else begin
df_dx_we0 = ap_const_logic_0;
end
end
/// df_dx_we1 assign process. ///
always @ (ap_CS_fsm)
begin
if (((ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st65_fsm_65 == ap_CS_fsm) | (ap_ST_st67_fsm_67 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st69_fsm_69 == ap_CS_fsm) | (ap_ST_st71_fsm_71 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st73_fsm_73 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st75_fsm_75 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st77_fsm_77 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm))) begin
df_dx_we1 = ap_const_logic_1;
end else begin
df_dx_we1 = ap_const_logic_0;
end
end
/// grp_fu_555_opcode assign process. ///
always @ (ap_CS_fsm)
begin
if (((ap_ST_st33_fsm_33 == ap_CS_fsm) | (ap_ST_st43_fsm_43 == ap_CS_fsm) | (ap_ST_st51_fsm_51 == ap_CS_fsm))) begin
grp_fu_555_opcode = ap_const_lv2_1;
end else if (((ap_ST_st3_fsm_3 == ap_CS_fsm) | (ap_ST_st5_fsm_5 == ap_CS_fsm) | (ap_ST_st7_fsm_7 == ap_CS_fsm) | (ap_ST_st9_fsm_9 == ap_CS_fsm) | (ap_ST_st11_fsm_11 == ap_CS_fsm) | (ap_ST_st37_fsm_37 == ap_CS_fsm) | (ap_ST_st41_fsm_41 == ap_CS_fsm) | (ap_ST_st67_fsm_67 == ap_CS_fsm) | (ap_ST_st13_fsm_13 == ap_CS_fsm) | (ap_ST_st15_fsm_15 == ap_CS_fsm) | (ap_ST_st19_fsm_19 == ap_CS_fsm) | (ap_ST_st45_fsm_45 == ap_CS_fsm) | (ap_ST_st53_fsm_53 == ap_CS_fsm) | (ap_ST_st57_fsm_57 == ap_CS_fsm) | (ap_ST_st59_fsm_59 == ap_CS_fsm) | (ap_ST_st61_fsm_61 == ap_CS_fsm) | (ap_ST_st63_fsm_63 == ap_CS_fsm))) begin
grp_fu_555_opcode = ap_const_lv2_0;
end else begin
grp_fu_555_opcode = ap_const_lv2_1;
end
end
/// grp_fu_555_p0 assign process. ///
always @ (ap_CS_fsm or X_x or X_qr or X_qy or X_qz or reg_795 or reg_850 or reg_889 or reg_903 or reg_931 or reg_976 or reg_1038 or reg_1057 or tmp_48_reg_1776 or tmp_4_reg_1793)
begin
if ((ap_ST_st67_fsm_67 == ap_CS_fsm)) begin
grp_fu_555_p0 = reg_850;
end else if ((ap_ST_st63_fsm_63 == ap_CS_fsm)) begin
grp_fu_555_p0 = reg_931;
end else if ((ap_ST_st59_fsm_59 == ap_CS_fsm)) begin
grp_fu_555_p0 = reg_903;
end else if ((ap_ST_st53_fsm_53 == ap_CS_fsm)) begin
grp_fu_555_p0 = reg_1057;
end else if ((ap_ST_st45_fsm_45 == ap_CS_fsm)) begin
grp_fu_555_p0 = reg_1038;
end else if ((ap_ST_st43_fsm_43 == ap_CS_fsm)) begin
grp_fu_555_p0 = ap_const_lv32_3FC00000;
end else if ((ap_ST_st37_fsm_37 == ap_CS_fsm)) begin
grp_fu_555_p0 = X_x;
end else if (((ap_ST_st33_fsm_33 == ap_CS_fsm) | (ap_ST_st51_fsm_51 == ap_CS_fsm))) begin
grp_fu_555_p0 = ap_const_lv32_80000000;
end else if ((ap_ST_st19_fsm_19 == ap_CS_fsm)) begin
grp_fu_555_p0 = tmp_4_reg_1793;
end else if ((ap_ST_st15_fsm_15 == ap_CS_fsm)) begin
grp_fu_555_p0 = reg_976;
end else if ((ap_ST_st13_fsm_13 == ap_CS_fsm)) begin
grp_fu_555_p0 = tmp_48_reg_1776;
end else if ((ap_ST_st11_fsm_11 == ap_CS_fsm)) begin
grp_fu_555_p0 = X_qz;
end else if (((ap_ST_st9_fsm_9 == ap_CS_fsm) | (ap_ST_st57_fsm_57 == ap_CS_fsm) | (ap_ST_st61_fsm_61 == ap_CS_fsm))) begin
grp_fu_555_p0 = reg_889;
end else if ((ap_ST_st7_fsm_7 == ap_CS_fsm)) begin
grp_fu_555_p0 = X_qy;
end else if (((ap_ST_st5_fsm_5 == ap_CS_fsm) | (ap_ST_st41_fsm_41 == ap_CS_fsm))) begin
grp_fu_555_p0 = reg_795;
end else if ((ap_ST_st3_fsm_3 == ap_CS_fsm)) begin
grp_fu_555_p0 = X_qr;
end else begin
grp_fu_555_p0 = ap_const_lv32_3FC00000;
end
end
/// grp_fu_555_p1 assign process. ///
always @ (ap_CS_fsm or X_qr or U_x or U_qr or U_qx or U_qy or U_qz or reg_795 or reg_829 or reg_903 or reg_943 or reg_1057 or reg_1072 or reg_1098)
begin
if ((ap_ST_st59_fsm_59 == ap_CS_fsm)) begin
grp_fu_555_p1 = reg_943;
end else if ((ap_ST_st57_fsm_57 == ap_CS_fsm)) begin
grp_fu_555_p1 = reg_1057;
end else if ((ap_ST_st53_fsm_53 == ap_CS_fsm)) begin
grp_fu_555_p1 = reg_1072;
end else if ((ap_ST_st51_fsm_51 == ap_CS_fsm)) begin
grp_fu_555_p1 = U_qx;
end else if ((ap_ST_st45_fsm_45 == ap_CS_fsm)) begin
grp_fu_555_p1 = reg_1098;
end else if ((ap_ST_st37_fsm_37 == ap_CS_fsm)) begin
grp_fu_555_p1 = U_x;
end else if ((ap_ST_st33_fsm_33 == ap_CS_fsm)) begin
grp_fu_555_p1 = X_qr;
end else if (((ap_ST_st67_fsm_67 == ap_CS_fsm) | (ap_ST_st13_fsm_13 == ap_CS_fsm) | (ap_ST_st19_fsm_19 == ap_CS_fsm) | (ap_ST_st61_fsm_61 == ap_CS_fsm))) begin
grp_fu_555_p1 = reg_795;
end else if ((ap_ST_st11_fsm_11 == ap_CS_fsm)) begin
grp_fu_555_p1 = U_qz;
end else if (((ap_ST_st9_fsm_9 == ap_CS_fsm) | (ap_ST_st15_fsm_15 == ap_CS_fsm) | (ap_ST_st43_fsm_43 == ap_CS_fsm) | (ap_ST_st63_fsm_63 == ap_CS_fsm))) begin
grp_fu_555_p1 = reg_903;
end else if ((ap_ST_st7_fsm_7 == ap_CS_fsm)) begin
grp_fu_555_p1 = U_qy;
end else if (((ap_ST_st5_fsm_5 == ap_CS_fsm) | (ap_ST_st41_fsm_41 == ap_CS_fsm))) begin
grp_fu_555_p1 = reg_829;
end else if ((ap_ST_st3_fsm_3 == ap_CS_fsm)) begin
grp_fu_555_p1 = U_qr;
end else begin
grp_fu_555_p1 = U_x;
end
end
/// grp_fu_560_opcode assign process. ///
always @ (ap_CS_fsm)
begin
if (((ap_ST_st33_fsm_33 == ap_CS_fsm) | (ap_ST_st43_fsm_43 == ap_CS_fsm) | (ap_ST_st51_fsm_51 == ap_CS_fsm))) begin
grp_fu_560_opcode = ap_const_lv2_1;
end else if (((ap_ST_st3_fsm_3 == ap_CS_fsm) | (ap_ST_st9_fsm_9 == ap_CS_fsm) | (ap_ST_st11_fsm_11 == ap_CS_fsm) | (ap_ST_st37_fsm_37 == ap_CS_fsm) | (ap_ST_st41_fsm_41 == ap_CS_fsm) | (ap_ST_st67_fsm_67 == ap_CS_fsm) | (ap_ST_st13_fsm_13 == ap_CS_fsm) | (ap_ST_st15_fsm_15 == ap_CS_fsm) | (ap_ST_st19_fsm_19 == ap_CS_fsm) | (ap_ST_st45_fsm_45 == ap_CS_fsm) | (ap_ST_st53_fsm_53 == ap_CS_fsm) | (ap_ST_st57_fsm_57 == ap_CS_fsm) | (ap_ST_st59_fsm_59 == ap_CS_fsm) | (ap_ST_st61_fsm_61 == ap_CS_fsm) | (ap_ST_st63_fsm_63 == ap_CS_fsm))) begin
grp_fu_560_opcode = ap_const_lv2_0;
end else begin
grp_fu_560_opcode = ap_const_lv2_1;
end
end
/// grp_fu_560_p0 assign process. ///
always @ (ap_CS_fsm or X_y or X_qx or reg_829 or reg_869 or reg_943 or reg_954 or reg_990 or reg_1019 or reg_1085 or reg_1277 or tmp_reg_1756 or tmp_239_reg_1902)
begin
if (((ap_ST_st67_fsm_67 == ap_CS_fsm) | (ap_ST_st61_fsm_61 == ap_CS_fsm))) begin
grp_fu_560_p0 = reg_869;
end else if ((ap_ST_st59_fsm_59 == ap_CS_fsm)) begin
grp_fu_560_p0 = tmp_239_reg_1902;
end else if ((ap_ST_st53_fsm_53 == ap_CS_fsm)) begin
grp_fu_560_p0 = reg_1085;
end else if ((ap_ST_st45_fsm_45 == ap_CS_fsm)) begin
grp_fu_560_p0 = reg_1277;
end else if ((ap_ST_st41_fsm_41 == ap_CS_fsm)) begin
grp_fu_560_p0 = reg_1019;
end else if ((ap_ST_st37_fsm_37 == ap_CS_fsm)) begin
grp_fu_560_p0 = X_y;
end else if (((ap_ST_st33_fsm_33 == ap_CS_fsm) | (ap_ST_st43_fsm_43 == ap_CS_fsm) | (ap_ST_st51_fsm_51 == ap_CS_fsm))) begin
grp_fu_560_p0 = ap_const_lv32_80000000;
end else if ((ap_ST_st19_fsm_19 == ap_CS_fsm)) begin
grp_fu_560_p0 = reg_990;
end else if ((ap_ST_st15_fsm_15 == ap_CS_fsm)) begin
grp_fu_560_p0 = reg_943;
end else if (((ap_ST_st13_fsm_13 == ap_CS_fsm) | (ap_ST_st57_fsm_57 == ap_CS_fsm) | (ap_ST_st63_fsm_63 == ap_CS_fsm))) begin
grp_fu_560_p0 = reg_954;
end else if ((ap_ST_st11_fsm_11 == ap_CS_fsm)) begin
grp_fu_560_p0 = tmp_reg_1756;
end else if ((ap_ST_st9_fsm_9 == ap_CS_fsm)) begin
grp_fu_560_p0 = reg_829;
end else if ((ap_ST_st3_fsm_3 == ap_CS_fsm)) begin
grp_fu_560_p0 = X_qx;
end else begin
grp_fu_560_p0 = ap_const_lv32_80000000;
end
end
/// grp_fu_560_p1 assign process. ///
always @ (ap_CS_fsm or X_qy or U_y or U_qx or U_qy or reg_795 or reg_829 or reg_850 or reg_903 or reg_943 or reg_1057 or reg_1072 or reg_1098 or reg_1252 or reg_1530)
begin
if (((ap_ST_st67_fsm_67 == ap_CS_fsm) | (ap_ST_st61_fsm_61 == ap_CS_fsm))) begin
grp_fu_560_p1 = reg_829;
end else if ((ap_ST_st59_fsm_59 == ap_CS_fsm)) begin
grp_fu_560_p1 = reg_1530;
end else if ((ap_ST_st57_fsm_57 == ap_CS_fsm)) begin
grp_fu_560_p1 = reg_1072;
end else if ((ap_ST_st53_fsm_53 == ap_CS_fsm)) begin
grp_fu_560_p1 = reg_1098;
end else if ((ap_ST_st51_fsm_51 == ap_CS_fsm)) begin
grp_fu_560_p1 = U_qy;
end else if ((ap_ST_st45_fsm_45 == ap_CS_fsm)) begin
grp_fu_560_p1 = reg_1252;
end else if ((ap_ST_st43_fsm_43 == ap_CS_fsm)) begin
grp_fu_560_p1 = reg_850;
end else if ((ap_ST_st41_fsm_41 == ap_CS_fsm)) begin
grp_fu_560_p1 = reg_1057;
end else if ((ap_ST_st37_fsm_37 == ap_CS_fsm)) begin
grp_fu_560_p1 = U_y;
end else if ((ap_ST_st33_fsm_33 == ap_CS_fsm)) begin
grp_fu_560_p1 = X_qy;
end else if (((ap_ST_st13_fsm_13 == ap_CS_fsm) | (ap_ST_st19_fsm_19 == ap_CS_fsm))) begin
grp_fu_560_p1 = reg_795;
end else if (((ap_ST_st11_fsm_11 == ap_CS_fsm) | (ap_ST_st63_fsm_63 == ap_CS_fsm))) begin
grp_fu_560_p1 = reg_943;
end else if (((ap_ST_st9_fsm_9 == ap_CS_fsm) | (ap_ST_st15_fsm_15 == ap_CS_fsm))) begin
grp_fu_560_p1 = reg_903;
end else if ((ap_ST_st3_fsm_3 == ap_CS_fsm)) begin
grp_fu_560_p1 = U_qx;
end else begin
grp_fu_560_p1 = U_y;
end
end
/// grp_fu_566_opcode assign process. ///
always @ (ap_CS_fsm)
begin
if (((ap_ST_st33_fsm_33 == ap_CS_fsm) | (ap_ST_st43_fsm_43 == ap_CS_fsm) | (ap_ST_st51_fsm_51 == ap_CS_fsm))) begin
grp_fu_566_opcode = ap_const_lv2_1;
end else if (((ap_ST_st9_fsm_9 == ap_CS_fsm) | (ap_ST_st37_fsm_37 == ap_CS_fsm) | (ap_ST_st41_fsm_41 == ap_CS_fsm) | (ap_ST_st67_fsm_67 == ap_CS_fsm) | (ap_ST_st13_fsm_13 == ap_CS_fsm) | (ap_ST_st15_fsm_15 == ap_CS_fsm) | (ap_ST_st19_fsm_19 == ap_CS_fsm) | (ap_ST_st53_fsm_53 == ap_CS_fsm) | (ap_ST_st57_fsm_57 == ap_CS_fsm) | (ap_ST_st59_fsm_59 == ap_CS_fsm) | (ap_ST_st61_fsm_61 == ap_CS_fsm) | (ap_ST_st63_fsm_63 == ap_CS_fsm))) begin
grp_fu_566_opcode = ap_const_lv2_0;
end else begin
grp_fu_566_opcode = ap_const_lv2_1;
end
end
/// grp_fu_566_p0 assign process. ///
always @ (ap_CS_fsm or X_z or reg_795 or reg_961 or reg_999 or reg_1110 or reg_1167 or tmp_reg_1756)
begin
if ((ap_ST_st53_fsm_53 == ap_CS_fsm)) begin
grp_fu_566_p0 = reg_1110;
end else if (((ap_ST_st41_fsm_41 == ap_CS_fsm) | (ap_ST_st59_fsm_59 == ap_CS_fsm))) begin
grp_fu_566_p0 = reg_1167;
end else if ((ap_ST_st37_fsm_37 == ap_CS_fsm)) begin
grp_fu_566_p0 = X_z;
end else if (((ap_ST_st33_fsm_33 == ap_CS_fsm) | (ap_ST_st43_fsm_43 == ap_CS_fsm) | (ap_ST_st51_fsm_51 == ap_CS_fsm))) begin
grp_fu_566_p0 = ap_const_lv32_80000000;
end else if (((ap_ST_st19_fsm_19 == ap_CS_fsm) | (ap_ST_st57_fsm_57 == ap_CS_fsm) | (ap_ST_st61_fsm_61 == ap_CS_fsm))) begin
grp_fu_566_p0 = reg_999;
end else if ((ap_ST_st15_fsm_15 == ap_CS_fsm)) begin
grp_fu_566_p0 = tmp_reg_1756;
end else if (((ap_ST_st67_fsm_67 == ap_CS_fsm) | (ap_ST_st13_fsm_13 == ap_CS_fsm) | (ap_ST_st63_fsm_63 == ap_CS_fsm))) begin
grp_fu_566_p0 = reg_961;
end else if ((ap_ST_st9_fsm_9 == ap_CS_fsm)) begin
grp_fu_566_p0 = reg_795;
end else begin
grp_fu_566_p0 = ap_const_lv32_80000000;
end
end
/// grp_fu_566_p1 assign process. ///
always @ (ap_CS_fsm or X_qz or U_z or U_qz or reg_795 or reg_869 or reg_903 or reg_1019 or reg_1047 or reg_1085 or reg_1383 or tmp_163_reg_1876)
begin
if ((ap_ST_st63_fsm_63 == ap_CS_fsm)) begin
grp_fu_566_p1 = reg_1047;
end else if (((ap_ST_st67_fsm_67 == ap_CS_fsm) | (ap_ST_st61_fsm_61 == ap_CS_fsm))) begin
grp_fu_566_p1 = reg_1019;
end else if ((ap_ST_st59_fsm_59 == ap_CS_fsm)) begin
grp_fu_566_p1 = reg_1383;
end else if ((ap_ST_st53_fsm_53 == ap_CS_fsm)) begin
grp_fu_566_p1 = tmp_163_reg_1876;
end else if ((ap_ST_st51_fsm_51 == ap_CS_fsm)) begin
grp_fu_566_p1 = U_qz;
end else if ((ap_ST_st43_fsm_43 == ap_CS_fsm)) begin
grp_fu_566_p1 = reg_869;
end else if (((ap_ST_st41_fsm_41 == ap_CS_fsm) | (ap_ST_st57_fsm_57 == ap_CS_fsm))) begin
grp_fu_566_p1 = reg_1085;
end else if ((ap_ST_st37_fsm_37 == ap_CS_fsm)) begin
grp_fu_566_p1 = U_z;
end else if ((ap_ST_st33_fsm_33 == ap_CS_fsm)) begin
grp_fu_566_p1 = X_qz;
end else if (((ap_ST_st13_fsm_13 == ap_CS_fsm) | (ap_ST_st19_fsm_19 == ap_CS_fsm))) begin
grp_fu_566_p1 = reg_795;
end else if (((ap_ST_st9_fsm_9 == ap_CS_fsm) | (ap_ST_st15_fsm_15 == ap_CS_fsm))) begin
grp_fu_566_p1 = reg_903;
end else begin
grp_fu_566_p1 = tmp_163_reg_1876;
end
end
/// grp_fu_571_opcode assign process. ///
always @ (ap_CS_fsm)
begin
if (((ap_ST_st37_fsm_37 == ap_CS_fsm) | (ap_ST_st43_fsm_43 == ap_CS_fsm))) begin
grp_fu_571_opcode = ap_const_lv2_1;
end else if (((ap_ST_st41_fsm_41 == ap_CS_fsm) | (ap_ST_st67_fsm_67 == ap_CS_fsm) | (ap_ST_st13_fsm_13 == ap_CS_fsm) | (ap_ST_st19_fsm_19 == ap_CS_fsm) | (ap_ST_st53_fsm_53 == ap_CS_fsm) | (ap_ST_st57_fsm_57 == ap_CS_fsm) | (ap_ST_st59_fsm_59 == ap_CS_fsm) | (ap_ST_st61_fsm_61 == ap_CS_fsm) | (ap_ST_st63_fsm_63 == ap_CS_fsm))) begin
grp_fu_571_opcode = ap_const_lv2_0;
end else begin
grp_fu_571_opcode = ap_const_lv2_1;
end
end
/// grp_fu_571_p0 assign process. ///
always @ (ap_CS_fsm or reg_889 or reg_976 or reg_983 or reg_1013 or reg_1178 or tmp_169_reg_1881 or tmp_253_reg_1907)
begin
if ((ap_ST_st63_fsm_63 == ap_CS_fsm)) begin
grp_fu_571_p0 = reg_1013;
end else if ((ap_ST_st59_fsm_59 == ap_CS_fsm)) begin
grp_fu_571_p0 = tmp_253_reg_1907;
end else if (((ap_ST_st67_fsm_67 == ap_CS_fsm) | (ap_ST_st57_fsm_57 == ap_CS_fsm) | (ap_ST_st61_fsm_61 == ap_CS_fsm))) begin
grp_fu_571_p0 = reg_983;
end else if ((ap_ST_st53_fsm_53 == ap_CS_fsm)) begin
grp_fu_571_p0 = tmp_169_reg_1881;
end else if ((ap_ST_st43_fsm_43 == ap_CS_fsm)) begin
grp_fu_571_p0 = ap_const_lv32_80000000;
end else if ((ap_ST_st41_fsm_41 == ap_CS_fsm)) begin
grp_fu_571_p0 = reg_1178;
end else if ((ap_ST_st37_fsm_37 == ap_CS_fsm)) begin
grp_fu_571_p0 = ap_const_lv32_3FC00000;
end else if ((ap_ST_st19_fsm_19 == ap_CS_fsm)) begin
grp_fu_571_p0 = reg_976;
end else if ((ap_ST_st13_fsm_13 == ap_CS_fsm)) begin
grp_fu_571_p0 = reg_889;
end else begin
grp_fu_571_p0 = ap_const_lv32_3FC00000;
end
end
/// grp_fu_571_p1 assign process. ///
always @ (ap_CS_fsm or reg_795 or reg_931 or reg_1057 or reg_1098 or reg_1110 or reg_1454 or reg_1530 or reg_1536)
begin
if ((ap_ST_st63_fsm_63 == ap_CS_fsm)) begin
grp_fu_571_p1 = reg_1530;
end else if (((ap_ST_st67_fsm_67 == ap_CS_fsm) | (ap_ST_st61_fsm_61 == ap_CS_fsm))) begin
grp_fu_571_p1 = reg_1057;
end else if ((ap_ST_st59_fsm_59 == ap_CS_fsm)) begin
grp_fu_571_p1 = reg_1536;
end else if ((ap_ST_st57_fsm_57 == ap_CS_fsm)) begin
grp_fu_571_p1 = reg_1098;
end else if ((ap_ST_st53_fsm_53 == ap_CS_fsm)) begin
grp_fu_571_p1 = reg_1454;
end else if ((ap_ST_st43_fsm_43 == ap_CS_fsm)) begin
grp_fu_571_p1 = reg_931;
end else if ((ap_ST_st41_fsm_41 == ap_CS_fsm)) begin
grp_fu_571_p1 = reg_1110;
end else if (((ap_ST_st37_fsm_37 == ap_CS_fsm) | (ap_ST_st13_fsm_13 == ap_CS_fsm) | (ap_ST_st19_fsm_19 == ap_CS_fsm))) begin
grp_fu_571_p1 = reg_795;
end else begin
grp_fu_571_p1 = reg_1536;
end
end
/// grp_fu_583_opcode assign process. ///
always @ (ap_CS_fsm)
begin
if (((ap_ST_st37_fsm_37 == ap_CS_fsm) | (ap_ST_st41_fsm_41 == ap_CS_fsm) | (ap_ST_st43_fsm_43 == ap_CS_fsm))) begin
grp_fu_583_opcode = ap_const_lv2_1;
end else if (((ap_ST_st67_fsm_67 == ap_CS_fsm) | (ap_ST_st53_fsm_53 == ap_CS_fsm) | (ap_ST_st57_fsm_57 == ap_CS_fsm) | (ap_ST_st59_fsm_59 == ap_CS_fsm) | (ap_ST_st61_fsm_61 == ap_CS_fsm) | (ap_ST_st63_fsm_63 == ap_CS_fsm))) begin
grp_fu_583_opcode = ap_const_lv2_0;
end else begin
grp_fu_583_opcode = ap_const_lv2_1;
end
end
/// grp_fu_583_p0 assign process. ///
always @ (ap_CS_fsm or reg_1072 or reg_1157 or reg_1291 or reg_1403 or reg_1460)
begin
if (((ap_ST_st67_fsm_67 == ap_CS_fsm) | (ap_ST_st63_fsm_63 == ap_CS_fsm))) begin
grp_fu_583_p0 = reg_1291;
end else if ((ap_ST_st59_fsm_59 == ap_CS_fsm)) begin
grp_fu_583_p0 = reg_1403;
end else if (((ap_ST_st57_fsm_57 == ap_CS_fsm) | (ap_ST_st61_fsm_61 == ap_CS_fsm))) begin
grp_fu_583_p0 = reg_1157;
end else if ((ap_ST_st53_fsm_53 == ap_CS_fsm)) begin
grp_fu_583_p0 = reg_1460;
end else if ((ap_ST_st41_fsm_41 == ap_CS_fsm)) begin
grp_fu_583_p0 = reg_1072;
end else if (((ap_ST_st37_fsm_37 == ap_CS_fsm) | (ap_ST_st43_fsm_43 == ap_CS_fsm))) begin
grp_fu_583_p0 = ap_const_lv32_80000000;
end else begin
grp_fu_583_p0 = ap_const_lv32_80000000;
end
end
/// grp_fu_583_p1 assign process. ///
always @ (ap_CS_fsm or X_qx or reg_1072 or reg_1110 or reg_1167 or reg_1414 or reg_1467 or X_plus_U_qz_reg_1782)
begin
if ((ap_ST_st63_fsm_63 == ap_CS_fsm)) begin
grp_fu_583_p1 = reg_1167;
end else if (((ap_ST_st67_fsm_67 == ap_CS_fsm) | (ap_ST_st61_fsm_61 == ap_CS_fsm))) begin
grp_fu_583_p1 = reg_1072;
end else if ((ap_ST_st59_fsm_59 == ap_CS_fsm)) begin
grp_fu_583_p1 = reg_1414;
end else if ((ap_ST_st53_fsm_53 == ap_CS_fsm)) begin
grp_fu_583_p1 = reg_1467;
end else if ((ap_ST_st43_fsm_43 == ap_CS_fsm)) begin
grp_fu_583_p1 = X_plus_U_qz_reg_1782;
end else if (((ap_ST_st41_fsm_41 == ap_CS_fsm) | (ap_ST_st57_fsm_57 == ap_CS_fsm))) begin
grp_fu_583_p1 = reg_1110;
end else if ((ap_ST_st37_fsm_37 == ap_CS_fsm)) begin
grp_fu_583_p1 = X_qx;
end else begin
grp_fu_583_p1 = X_plus_U_qz_reg_1782;
end
end
/// grp_fu_588_opcode assign process. ///
always @ (ap_CS_fsm)
begin
if (((ap_ST_st37_fsm_37 == ap_CS_fsm) | (ap_ST_st41_fsm_41 == ap_CS_fsm))) begin
grp_fu_588_opcode = ap_const_lv2_1;
end else if (((ap_ST_st67_fsm_67 == ap_CS_fsm) | (ap_ST_st53_fsm_53 == ap_CS_fsm) | (ap_ST_st57_fsm_57 == ap_CS_fsm) | (ap_ST_st59_fsm_59 == ap_CS_fsm) | (ap_ST_st61_fsm_61 == ap_CS_fsm) | (ap_ST_st63_fsm_63 == ap_CS_fsm))) begin
grp_fu_588_opcode = ap_const_lv2_0;
end else begin
grp_fu_588_opcode = ap_const_lv2_1;
end
end
/// grp_fu_588_p0 assign process. ///
always @ (ap_CS_fsm or reg_1047 or reg_1178 or reg_1186 or reg_1454 or reg_1473 or reg_1542)
begin
if (((ap_ST_st67_fsm_67 == ap_CS_fsm) | (ap_ST_st63_fsm_63 == ap_CS_fsm))) begin
grp_fu_588_p0 = reg_1542;
end else if ((ap_ST_st59_fsm_59 == ap_CS_fsm)) begin
grp_fu_588_p0 = reg_1454;
end else if (((ap_ST_st57_fsm_57 == ap_CS_fsm) | (ap_ST_st61_fsm_61 == ap_CS_fsm))) begin
grp_fu_588_p0 = reg_1178;
end else if ((ap_ST_st53_fsm_53 == ap_CS_fsm)) begin
grp_fu_588_p0 = reg_1473;
end else if ((ap_ST_st41_fsm_41 == ap_CS_fsm)) begin
grp_fu_588_p0 = reg_1186;
end else if ((ap_ST_st37_fsm_37 == ap_CS_fsm)) begin
grp_fu_588_p0 = reg_1047;
end else begin
grp_fu_588_p0 = reg_1542;
end
end
/// grp_fu_588_p1 assign process. ///
always @ (ap_CS_fsm or reg_1057 or reg_1085 or reg_1098 or reg_1123 or reg_1383 or reg_1460 or reg_1479)
begin
if ((ap_ST_st63_fsm_63 == ap_CS_fsm)) begin
grp_fu_588_p1 = reg_1383;
end else if (((ap_ST_st67_fsm_67 == ap_CS_fsm) | (ap_ST_st61_fsm_61 == ap_CS_fsm))) begin
grp_fu_588_p1 = reg_1085;
end else if ((ap_ST_st59_fsm_59 == ap_CS_fsm)) begin
grp_fu_588_p1 = reg_1460;
end else if ((ap_ST_st57_fsm_57 == ap_CS_fsm)) begin
grp_fu_588_p1 = reg_1123;
end else if ((ap_ST_st53_fsm_53 == ap_CS_fsm)) begin
grp_fu_588_p1 = reg_1479;
end else if ((ap_ST_st41_fsm_41 == ap_CS_fsm)) begin
grp_fu_588_p1 = reg_1098;
end else if ((ap_ST_st37_fsm_37 == ap_CS_fsm)) begin
grp_fu_588_p1 = reg_1057;
end else begin
grp_fu_588_p1 = reg_1479;
end
end
/// grp_fu_592_p0 assign process. ///
always @ (ap_CS_fsm or reg_1085 or reg_1123 or reg_1186 or reg_1444 or reg_1485 or reg_1547)
begin
if (((ap_ST_st67_fsm_67 == ap_CS_fsm) | (ap_ST_st63_fsm_63 == ap_CS_fsm))) begin
grp_fu_592_p0 = reg_1547;
end else if ((ap_ST_st59_fsm_59 == ap_CS_fsm)) begin
grp_fu_592_p0 = reg_1444;
end else if (((ap_ST_st57_fsm_57 == ap_CS_fsm) | (ap_ST_st61_fsm_61 == ap_CS_fsm))) begin
grp_fu_592_p0 = reg_1186;
end else if ((ap_ST_st53_fsm_53 == ap_CS_fsm)) begin
grp_fu_592_p0 = reg_1485;
end else if ((ap_ST_st41_fsm_41 == ap_CS_fsm)) begin
grp_fu_592_p0 = reg_1123;
end else if ((ap_ST_st37_fsm_37 == ap_CS_fsm)) begin
grp_fu_592_p0 = reg_1085;
end else begin
grp_fu_592_p0 = reg_1547;
end
end
/// grp_fu_592_p1 assign process. ///
always @ (ap_CS_fsm or reg_1057 or reg_1098 or reg_1201 or reg_1261 or reg_1315 or reg_1521)
begin
if ((ap_ST_st63_fsm_63 == ap_CS_fsm)) begin
grp_fu_592_p1 = reg_1261;
end else if ((ap_ST_st59_fsm_59 == ap_CS_fsm)) begin
grp_fu_592_p1 = reg_1521;
end else if ((ap_ST_st57_fsm_57 == ap_CS_fsm)) begin
grp_fu_592_p1 = reg_1201;
end else if ((ap_ST_st53_fsm_53 == ap_CS_fsm)) begin
grp_fu_592_p1 = reg_1315;
end else if ((ap_ST_st41_fsm_41 == ap_CS_fsm)) begin
grp_fu_592_p1 = reg_1057;
end else if (((ap_ST_st37_fsm_37 == ap_CS_fsm) | (ap_ST_st67_fsm_67 == ap_CS_fsm) | (ap_ST_st61_fsm_61 == ap_CS_fsm))) begin
grp_fu_592_p1 = reg_1098;
end else begin
grp_fu_592_p1 = reg_1521;
end
end
/// grp_fu_596_p0 assign process. ///
always @ (ap_CS_fsm or reg_1110 or reg_1194 or reg_1325 or reg_1552 or tmp_281_reg_1912)
begin
if (((ap_ST_st67_fsm_67 == ap_CS_fsm) | (ap_ST_st63_fsm_63 == ap_CS_fsm))) begin
grp_fu_596_p0 = reg_1552;
end else if ((ap_ST_st59_fsm_59 == ap_CS_fsm)) begin
grp_fu_596_p0 = tmp_281_reg_1912;
end else if ((ap_ST_st53_fsm_53 == ap_CS_fsm)) begin
grp_fu_596_p0 = reg_1325;
end else if (((ap_ST_st41_fsm_41 == ap_CS_fsm) | (ap_ST_st57_fsm_57 == ap_CS_fsm) | (ap_ST_st61_fsm_61 == ap_CS_fsm))) begin
grp_fu_596_p0 = reg_1194;
end else if ((ap_ST_st37_fsm_37 == ap_CS_fsm)) begin
grp_fu_596_p0 = reg_1110;
end else begin
grp_fu_596_p0 = tmp_281_reg_1912;
end
end
/// grp_fu_596_p1 assign process. ///
always @ (ap_CS_fsm or reg_829 or reg_1110 or reg_1123 or reg_1220 or reg_1335 or reg_1485 or reg_1536)
begin
if ((ap_ST_st63_fsm_63 == ap_CS_fsm)) begin
grp_fu_596_p1 = reg_1536;
end else if (((ap_ST_st67_fsm_67 == ap_CS_fsm) | (ap_ST_st61_fsm_61 == ap_CS_fsm))) begin
grp_fu_596_p1 = reg_1110;
end else if ((ap_ST_st59_fsm_59 == ap_CS_fsm)) begin
grp_fu_596_p1 = reg_1485;
end else if ((ap_ST_st57_fsm_57 == ap_CS_fsm)) begin
grp_fu_596_p1 = reg_1220;
end else if ((ap_ST_st53_fsm_53 == ap_CS_fsm)) begin
grp_fu_596_p1 = reg_1335;
end else if ((ap_ST_st41_fsm_41 == ap_CS_fsm)) begin
grp_fu_596_p1 = reg_829;
end else if ((ap_ST_st37_fsm_37 == ap_CS_fsm)) begin
grp_fu_596_p1 = reg_1123;
end else begin
grp_fu_596_p1 = reg_1536;
end
end
/// grp_fu_600_p0 assign process. ///
always @ (ap_CS_fsm or reg_1072 or reg_1201 or reg_1212 or reg_1315 or reg_1345 or reg_1557)
begin
if (((ap_ST_st67_fsm_67 == ap_CS_fsm) | (ap_ST_st63_fsm_63 == ap_CS_fsm))) begin
grp_fu_600_p0 = reg_1557;
end else if ((ap_ST_st59_fsm_59 == ap_CS_fsm)) begin
grp_fu_600_p0 = reg_1315;
end else if (((ap_ST_st57_fsm_57 == ap_CS_fsm) | (ap_ST_st61_fsm_61 == ap_CS_fsm))) begin
grp_fu_600_p0 = reg_1212;
end else if ((ap_ST_st53_fsm_53 == ap_CS_fsm)) begin
grp_fu_600_p0 = reg_1345;
end else if ((ap_ST_st41_fsm_41 == ap_CS_fsm)) begin
grp_fu_600_p0 = reg_1201;
end else if ((ap_ST_st37_fsm_37 == ap_CS_fsm)) begin
grp_fu_600_p0 = reg_1072;
end else begin
grp_fu_600_p0 = reg_1557;
end
end
/// grp_fu_600_p1 assign process. ///
always @ (ap_CS_fsm or reg_1057 or reg_1085 or reg_1123 or reg_1231 or reg_1325 or reg_1355 or reg_1403)
begin
if ((ap_ST_st63_fsm_63 == ap_CS_fsm)) begin
grp_fu_600_p1 = reg_1403;
end else if (((ap_ST_st67_fsm_67 == ap_CS_fsm) | (ap_ST_st61_fsm_61 == ap_CS_fsm))) begin
grp_fu_600_p1 = reg_1123;
end else if ((ap_ST_st59_fsm_59 == ap_CS_fsm)) begin
grp_fu_600_p1 = reg_1325;
end else if ((ap_ST_st57_fsm_57 == ap_CS_fsm)) begin
grp_fu_600_p1 = reg_1231;
end else if ((ap_ST_st53_fsm_53 == ap_CS_fsm)) begin
grp_fu_600_p1 = reg_1355;
end else if ((ap_ST_st41_fsm_41 == ap_CS_fsm)) begin
grp_fu_600_p1 = reg_1085;
end else if ((ap_ST_st37_fsm_37 == ap_CS_fsm)) begin
grp_fu_600_p1 = reg_1057;
end else begin
grp_fu_600_p1 = reg_1403;
end
end
/// grp_fu_604_p0 assign process. ///
always @ (ap_CS_fsm or reg_1212 or reg_1270 or reg_1335 or reg_1365 or reg_1562)
begin
if (((ap_ST_st67_fsm_67 == ap_CS_fsm) | (ap_ST_st63_fsm_63 == ap_CS_fsm))) begin
grp_fu_604_p0 = reg_1562;
end else if ((ap_ST_st59_fsm_59 == ap_CS_fsm)) begin
grp_fu_604_p0 = reg_1335;
end else if (((ap_ST_st57_fsm_57 == ap_CS_fsm) | (ap_ST_st61_fsm_61 == ap_CS_fsm))) begin
grp_fu_604_p0 = reg_1270;
end else if ((ap_ST_st53_fsm_53 == ap_CS_fsm)) begin
grp_fu_604_p0 = reg_1365;
end else if ((ap_ST_st41_fsm_41 == ap_CS_fsm)) begin
grp_fu_604_p0 = reg_1212;
end else begin
grp_fu_604_p0 = reg_1562;
end
end
/// grp_fu_604_p1 assign process. ///
always @ (ap_CS_fsm or reg_1201 or reg_1220 or reg_1345 or reg_1414 or reg_1467 or reg_1491)
begin
if ((ap_ST_st63_fsm_63 == ap_CS_fsm)) begin
grp_fu_604_p1 = reg_1414;
end else if (((ap_ST_st67_fsm_67 == ap_CS_fsm) | (ap_ST_st61_fsm_61 == ap_CS_fsm))) begin
grp_fu_604_p1 = reg_1201;
end else if ((ap_ST_st59_fsm_59 == ap_CS_fsm)) begin
grp_fu_604_p1 = reg_1345;
end else if ((ap_ST_st57_fsm_57 == ap_CS_fsm)) begin
grp_fu_604_p1 = reg_1467;
end else if ((ap_ST_st53_fsm_53 == ap_CS_fsm)) begin
grp_fu_604_p1 = reg_1491;
end else if ((ap_ST_st41_fsm_41 == ap_CS_fsm)) begin
grp_fu_604_p1 = reg_1220;
end else begin
grp_fu_604_p1 = reg_1491;
end
end
/// grp_fu_608_p0 assign process. ///
always @ (ap_CS_fsm or reg_1231 or reg_1277 or reg_1355 or reg_1497 or reg_1567)
begin
if (((ap_ST_st67_fsm_67 == ap_CS_fsm) | (ap_ST_st63_fsm_63 == ap_CS_fsm))) begin
grp_fu_608_p0 = reg_1567;
end else if ((ap_ST_st59_fsm_59 == ap_CS_fsm)) begin
grp_fu_608_p0 = reg_1355;
end else if (((ap_ST_st57_fsm_57 == ap_CS_fsm) | (ap_ST_st61_fsm_61 == ap_CS_fsm))) begin
grp_fu_608_p0 = reg_1277;
end else if ((ap_ST_st53_fsm_53 == ap_CS_fsm)) begin
grp_fu_608_p0 = reg_1497;
end else if ((ap_ST_st41_fsm_41 == ap_CS_fsm)) begin
grp_fu_608_p0 = reg_1231;
end else begin
grp_fu_608_p0 = reg_1567;
end
end
/// grp_fu_608_p1 assign process. ///
always @ (ap_CS_fsm or reg_1220 or reg_1242 or reg_1365 or reg_1425 or reg_1473 or reg_1503)
begin
if ((ap_ST_st63_fsm_63 == ap_CS_fsm)) begin
grp_fu_608_p1 = reg_1425;
end else if (((ap_ST_st67_fsm_67 == ap_CS_fsm) | (ap_ST_st61_fsm_61 == ap_CS_fsm))) begin
grp_fu_608_p1 = reg_1220;
end else if ((ap_ST_st59_fsm_59 == ap_CS_fsm)) begin
grp_fu_608_p1 = reg_1365;
end else if ((ap_ST_st57_fsm_57 == ap_CS_fsm)) begin
grp_fu_608_p1 = reg_1473;
end else if ((ap_ST_st53_fsm_53 == ap_CS_fsm)) begin
grp_fu_608_p1 = reg_1503;
end else if ((ap_ST_st41_fsm_41 == ap_CS_fsm)) begin
grp_fu_608_p1 = reg_1242;
end else begin
grp_fu_608_p1 = reg_1503;
end
end
/// grp_fu_612_p0 assign process. ///
always @ (ap_CS_fsm or reg_1123 or reg_1284 or reg_1491 or reg_1509 or reg_1572)
begin
if (((ap_ST_st67_fsm_67 == ap_CS_fsm) | (ap_ST_st63_fsm_63 == ap_CS_fsm))) begin
grp_fu_612_p0 = reg_1572;
end else if ((ap_ST_st59_fsm_59 == ap_CS_fsm)) begin
grp_fu_612_p0 = reg_1491;
end else if (((ap_ST_st57_fsm_57 == ap_CS_fsm) | (ap_ST_st61_fsm_61 == ap_CS_fsm))) begin
grp_fu_612_p0 = reg_1284;
end else if ((ap_ST_st53_fsm_53 == ap_CS_fsm)) begin
grp_fu_612_p0 = reg_1509;
end else if ((ap_ST_st41_fsm_41 == ap_CS_fsm)) begin
grp_fu_612_p0 = reg_1123;
end else begin
grp_fu_612_p0 = reg_1572;
end
end
/// grp_fu_612_p1 assign process. ///
always @ (ap_CS_fsm or reg_1019 or reg_1231 or reg_1460 or reg_1479 or reg_1497 or reg_1515)
begin
if ((ap_ST_st63_fsm_63 == ap_CS_fsm)) begin
grp_fu_612_p1 = reg_1460;
end else if (((ap_ST_st67_fsm_67 == ap_CS_fsm) | (ap_ST_st61_fsm_61 == ap_CS_fsm))) begin
grp_fu_612_p1 = reg_1231;
end else if ((ap_ST_st59_fsm_59 == ap_CS_fsm)) begin
grp_fu_612_p1 = reg_1497;
end else if ((ap_ST_st57_fsm_57 == ap_CS_fsm)) begin
grp_fu_612_p1 = reg_1479;
end else if ((ap_ST_st53_fsm_53 == ap_CS_fsm)) begin
grp_fu_612_p1 = reg_1515;
end else if ((ap_ST_st41_fsm_41 == ap_CS_fsm)) begin
grp_fu_612_p1 = reg_1019;
end else begin
grp_fu_612_p1 = reg_1515;
end
end
/// grp_fu_618_p0 assign process. ///
always @ (ap_CS_fsm or reg_1503 or reg_1577)
begin
if (((ap_ST_st67_fsm_67 == ap_CS_fsm) | (ap_ST_st63_fsm_63 == ap_CS_fsm))) begin
grp_fu_618_p0 = reg_1577;
end else if ((ap_ST_st59_fsm_59 == ap_CS_fsm)) begin
grp_fu_618_p0 = reg_1503;
end else begin
grp_fu_618_p0 = reg_1577;
end
end
/// grp_fu_618_p1 assign process. ///
always @ (ap_CS_fsm or reg_1242 or reg_1509)
begin
if (((ap_ST_st67_fsm_67 == ap_CS_fsm) | (ap_ST_st63_fsm_63 == ap_CS_fsm))) begin
grp_fu_618_p1 = reg_1242;
end else if ((ap_ST_st59_fsm_59 == ap_CS_fsm)) begin
grp_fu_618_p1 = reg_1509;
end else begin
grp_fu_618_p1 = reg_1509;
end
end
/// grp_fu_622_p0 assign process. ///
always @ (ap_CS_fsm or reg_1515 or reg_1583)
begin
if (((ap_ST_st67_fsm_67 == ap_CS_fsm) | (ap_ST_st63_fsm_63 == ap_CS_fsm))) begin
grp_fu_622_p0 = reg_1583;
end else if ((ap_ST_st59_fsm_59 == ap_CS_fsm)) begin
grp_fu_622_p0 = reg_1515;
end else begin
grp_fu_622_p0 = reg_1583;
end
end
/// grp_fu_622_p1 assign process. ///
always @ (ap_CS_fsm or reg_1252 or tmp_324_reg_1917)
begin
if (((ap_ST_st67_fsm_67 == ap_CS_fsm) | (ap_ST_st63_fsm_63 == ap_CS_fsm))) begin
grp_fu_622_p1 = reg_1252;
end else if ((ap_ST_st59_fsm_59 == ap_CS_fsm)) begin
grp_fu_622_p1 = tmp_324_reg_1917;
end else begin
grp_fu_622_p1 = tmp_324_reg_1917;
end
end
/// grp_fu_626_p0 assign process. ///
always @ (ap_CS_fsm or reg_1589 or tmp_330_reg_1922)
begin
if (((ap_ST_st67_fsm_67 == ap_CS_fsm) | (ap_ST_st63_fsm_63 == ap_CS_fsm))) begin
grp_fu_626_p0 = reg_1589;
end else if ((ap_ST_st59_fsm_59 == ap_CS_fsm)) begin
grp_fu_626_p0 = tmp_330_reg_1922;
end else begin
grp_fu_626_p0 = tmp_330_reg_1922;
end
end
/// grp_fu_626_p1 assign process. ///
always @ (ap_CS_fsm or reg_1299 or tmp_331_reg_1927)
begin
if (((ap_ST_st67_fsm_67 == ap_CS_fsm) | (ap_ST_st63_fsm_63 == ap_CS_fsm))) begin
grp_fu_626_p1 = reg_1299;
end else if ((ap_ST_st59_fsm_59 == ap_CS_fsm)) begin
grp_fu_626_p1 = tmp_331_reg_1927;
end else begin
grp_fu_626_p1 = tmp_331_reg_1927;
end
end
/// grp_fu_630_p0 assign process. ///
always @ (ap_CS_fsm or reg_1595 or tmp_337_reg_1932)
begin
if (((ap_ST_st67_fsm_67 == ap_CS_fsm) | (ap_ST_st63_fsm_63 == ap_CS_fsm))) begin
grp_fu_630_p0 = reg_1595;
end else if ((ap_ST_st59_fsm_59 == ap_CS_fsm)) begin
grp_fu_630_p0 = tmp_337_reg_1932;
end else begin
grp_fu_630_p0 = tmp_337_reg_1932;
end
end
/// grp_fu_630_p1 assign process. ///
always @ (ap_CS_fsm or reg_1307 or tmp_338_reg_1937)
begin
if (((ap_ST_st67_fsm_67 == ap_CS_fsm) | (ap_ST_st63_fsm_63 == ap_CS_fsm))) begin
grp_fu_630_p1 = reg_1307;
end else if ((ap_ST_st59_fsm_59 == ap_CS_fsm)) begin
grp_fu_630_p1 = tmp_338_reg_1937;
end else begin
grp_fu_630_p1 = tmp_338_reg_1937;
end
end
/// grp_fu_634_p0 assign process. ///
always @ (ap_CS_fsm or X_qr or X_qy or X_qz or U_y or reg_795 or reg_850 or reg_889 or reg_903 or reg_931 or reg_954 or reg_976 or reg_1006 or reg_1047 or reg_1152 or reg_1375 or X_plus_U_qz_reg_1782)
begin
if ((ap_ST_st63_fsm_63 == ap_CS_fsm)) begin
grp_fu_634_p0 = reg_1375;
end else if ((ap_ST_st59_fsm_59 == ap_CS_fsm)) begin
grp_fu_634_p0 = reg_1047;
end else if ((ap_ST_st51_fsm_51 == ap_CS_fsm)) begin
grp_fu_634_p0 = reg_976;
end else if ((ap_ST_st45_fsm_45 == ap_CS_fsm)) begin
grp_fu_634_p0 = reg_954;
end else if (((ap_ST_st41_fsm_41 == ap_CS_fsm) | (ap_ST_st53_fsm_53 == ap_CS_fsm))) begin
grp_fu_634_p0 = reg_1152;
end else if ((ap_ST_st37_fsm_37 == ap_CS_fsm)) begin
grp_fu_634_p0 = U_y;
end else if (((ap_ST_st25_fsm_25 == ap_CS_fsm) | (ap_ST_st29_fsm_29 == ap_CS_fsm) | (ap_ST_st33_fsm_33 == ap_CS_fsm) | (ap_ST_st57_fsm_57 == ap_CS_fsm))) begin
grp_fu_634_p0 = reg_795;
end else if (((ap_ST_st47_fsm_47 == ap_CS_fsm) | (ap_ST_st23_fsm_23 == ap_CS_fsm))) begin
grp_fu_634_p0 = reg_1006;
end else if (((ap_ST_st31_fsm_31 == ap_CS_fsm) | (ap_ST_st35_fsm_35 == ap_CS_fsm) | (ap_ST_st21_fsm_21 == ap_CS_fsm) | (ap_ST_st27_fsm_27 == ap_CS_fsm) | (ap_ST_st39_fsm_39 == ap_CS_fsm) | (ap_ST_st55_fsm_55 == ap_CS_fsm))) begin
grp_fu_634_p0 = reg_903;
end else if (((ap_ST_st17_fsm_17 == ap_CS_fsm) | (ap_ST_st49_fsm_49 == ap_CS_fsm))) begin
grp_fu_634_p0 = reg_889;
end else if ((ap_ST_st15_fsm_15 == ap_CS_fsm)) begin
grp_fu_634_p0 = X_plus_U_qz_reg_1782;
end else if ((ap_ST_st11_fsm_11 == ap_CS_fsm)) begin
grp_fu_634_p0 = reg_931;
end else if ((ap_ST_st9_fsm_9 == ap_CS_fsm)) begin
grp_fu_634_p0 = X_qz;
end else if ((ap_ST_st7_fsm_7 == ap_CS_fsm)) begin
grp_fu_634_p0 = reg_850;
end else if ((ap_ST_st5_fsm_5 == ap_CS_fsm)) begin
grp_fu_634_p0 = X_qy;
end else if ((ap_ST_st1_fsm_1 == ap_CS_fsm)) begin
grp_fu_634_p0 = X_qr;
end else begin
grp_fu_634_p0 = U_y;
end
end
/// grp_fu_634_p1 assign process. ///
always @ (ap_CS_fsm or X_qr or X_qy or X_qz or U_qr or U_qy or U_qz or reg_795 or reg_850 or reg_889 or reg_903 or reg_931 or reg_1006 or reg_1038 or reg_1242 or X_plus_U_qz_reg_1782 or tmp1_i1_fu_1624_p1 or tmp1_i1_reg_1804 or tmp1_i_fu_1652_p1 or tmp1_i_reg_1838)
begin
if ((ap_ST_st63_fsm_63 == ap_CS_fsm)) begin
grp_fu_634_p1 = U_qz;
end else if ((ap_ST_st59_fsm_59 == ap_CS_fsm)) begin
grp_fu_634_p1 = U_qy;
end else if ((ap_ST_st57_fsm_57 == ap_CS_fsm)) begin
grp_fu_634_p1 = reg_1242;
end else if ((ap_ST_st55_fsm_55 == ap_CS_fsm)) begin
grp_fu_634_p1 = U_qr;
end else if ((ap_ST_st51_fsm_51 == ap_CS_fsm)) begin
grp_fu_634_p1 = reg_903;
end else if (((ap_ST_st53_fsm_53 == ap_CS_fsm) | (ap_ST_st49_fsm_49 == ap_CS_fsm))) begin
grp_fu_634_p1 = ap_const_lv32_40000000;
end else if ((ap_ST_st45_fsm_45 == ap_CS_fsm)) begin
grp_fu_634_p1 = reg_795;
end else if (((ap_ST_st47_fsm_47 == ap_CS_fsm) | (ap_ST_st39_fsm_39 == ap_CS_fsm))) begin
grp_fu_634_p1 = tmp1_i_reg_1838;
end else if ((ap_ST_st37_fsm_37 == ap_CS_fsm)) begin
grp_fu_634_p1 = reg_1038;
end else if ((ap_ST_st35_fsm_35 == ap_CS_fsm)) begin
grp_fu_634_p1 = tmp1_i_fu_1652_p1;
end else if (((ap_ST_st33_fsm_33 == ap_CS_fsm) | (ap_ST_st41_fsm_41 == ap_CS_fsm))) begin
grp_fu_634_p1 = tmp1_i1_reg_1804;
end else if ((ap_ST_st29_fsm_29 == ap_CS_fsm)) begin
grp_fu_634_p1 = tmp1_i1_fu_1624_p1;
end else if (((ap_ST_st25_fsm_25 == ap_CS_fsm) | (ap_ST_st31_fsm_31 == ap_CS_fsm))) begin
grp_fu_634_p1 = ap_const_lv32_3F000000;
end else if (((ap_ST_st23_fsm_23 == ap_CS_fsm) | (ap_ST_st27_fsm_27 == ap_CS_fsm))) begin
grp_fu_634_p1 = reg_1006;
end else if (((ap_ST_st17_fsm_17 == ap_CS_fsm) | (ap_ST_st21_fsm_21 == ap_CS_fsm))) begin
grp_fu_634_p1 = reg_889;
end else if ((ap_ST_st15_fsm_15 == ap_CS_fsm)) begin
grp_fu_634_p1 = X_plus_U_qz_reg_1782;
end else if ((ap_ST_st11_fsm_11 == ap_CS_fsm)) begin
grp_fu_634_p1 = reg_931;
end else if ((ap_ST_st9_fsm_9 == ap_CS_fsm)) begin
grp_fu_634_p1 = X_qz;
end else if ((ap_ST_st7_fsm_7 == ap_CS_fsm)) begin
grp_fu_634_p1 = reg_850;
end else if ((ap_ST_st5_fsm_5 == ap_CS_fsm)) begin
grp_fu_634_p1 = X_qy;
end else if ((ap_ST_st1_fsm_1 == ap_CS_fsm)) begin
grp_fu_634_p1 = X_qr;
end else begin
grp_fu_634_p1 = ap_const_lv32_40000000;
end
end
/// grp_fu_640_p0 assign process. ///
always @ (ap_CS_fsm or X_qx or X_qy or X_qz or reg_795 or reg_829 or reg_869 or reg_943 or reg_1047 or reg_1186 or reg_1194 or reg_1375)
begin
if ((ap_ST_st63_fsm_63 == ap_CS_fsm)) begin
grp_fu_640_p0 = reg_1375;
end else if ((ap_ST_st59_fsm_59 == ap_CS_fsm)) begin
grp_fu_640_p0 = reg_1047;
end else if ((ap_ST_st57_fsm_57 == ap_CS_fsm)) begin
grp_fu_640_p0 = reg_795;
end else if ((ap_ST_st53_fsm_53 == ap_CS_fsm)) begin
grp_fu_640_p0 = reg_1194;
end else if (((ap_ST_st51_fsm_51 == ap_CS_fsm) | (ap_ST_st55_fsm_55 == ap_CS_fsm))) begin
grp_fu_640_p0 = reg_943;
end else if ((ap_ST_st49_fsm_49 == ap_CS_fsm)) begin
grp_fu_640_p0 = reg_1186;
end else if ((ap_ST_st45_fsm_45 == ap_CS_fsm)) begin
grp_fu_640_p0 = reg_829;
end else if (((ap_ST_st33_fsm_33 == ap_CS_fsm) | (ap_ST_st37_fsm_37 == ap_CS_fsm))) begin
grp_fu_640_p0 = X_qy;
end else if ((ap_ST_st29_fsm_29 == ap_CS_fsm)) begin
grp_fu_640_p0 = X_qz;
end else if (((ap_ST_st7_fsm_7 == ap_CS_fsm) | (ap_ST_st47_fsm_47 == ap_CS_fsm))) begin
grp_fu_640_p0 = reg_869;
end else if (((ap_ST_st1_fsm_1 == ap_CS_fsm) | (ap_ST_st41_fsm_41 == ap_CS_fsm))) begin
grp_fu_640_p0 = X_qx;
end else begin
grp_fu_640_p0 = X_qz;
end
end
/// grp_fu_640_p1 assign process. ///
always @ (ap_CS_fsm or X_qx or U_z or U_qx or U_qy or reg_795 or reg_869 or reg_889 or reg_903 or reg_961 or reg_1136 or reg_1252)
begin
if ((ap_ST_st63_fsm_63 == ap_CS_fsm)) begin
grp_fu_640_p1 = U_qy;
end else if ((ap_ST_st59_fsm_59 == ap_CS_fsm)) begin
grp_fu_640_p1 = reg_961;
end else if ((ap_ST_st57_fsm_57 == ap_CS_fsm)) begin
grp_fu_640_p1 = reg_1252;
end else if ((ap_ST_st55_fsm_55 == ap_CS_fsm)) begin
grp_fu_640_p1 = U_qx;
end else if ((ap_ST_st51_fsm_51 == ap_CS_fsm)) begin
grp_fu_640_p1 = reg_903;
end else if (((ap_ST_st53_fsm_53 == ap_CS_fsm) | (ap_ST_st49_fsm_49 == ap_CS_fsm))) begin
grp_fu_640_p1 = ap_const_lv32_40000000;
end else if ((ap_ST_st47_fsm_47 == ap_CS_fsm)) begin
grp_fu_640_p1 = reg_1136;
end else if ((ap_ST_st45_fsm_45 == ap_CS_fsm)) begin
grp_fu_640_p1 = reg_795;
end else if ((ap_ST_st41_fsm_41 == ap_CS_fsm)) begin
grp_fu_640_p1 = reg_889;
end else if ((ap_ST_st37_fsm_37 == ap_CS_fsm)) begin
grp_fu_640_p1 = U_z;
end else if (((ap_ST_st29_fsm_29 == ap_CS_fsm) | (ap_ST_st33_fsm_33 == ap_CS_fsm))) begin
grp_fu_640_p1 = ap_const_lv32_C0000000;
end else if ((ap_ST_st7_fsm_7 == ap_CS_fsm)) begin
grp_fu_640_p1 = reg_869;
end else if ((ap_ST_st1_fsm_1 == ap_CS_fsm)) begin
grp_fu_640_p1 = X_qx;
end else begin
grp_fu_640_p1 = ap_const_lv32_C0000000;
end
end
/// grp_fu_652_p0 assign process. ///
always @ (ap_CS_fsm or X_qx or X_qy or reg_795 or reg_829 or reg_903 or reg_931 or reg_954 or reg_1019 or reg_1047 or reg_1284 or reg_1375)
begin
if ((ap_ST_st63_fsm_63 == ap_CS_fsm)) begin
grp_fu_652_p0 = reg_1375;
end else if ((ap_ST_st57_fsm_57 == ap_CS_fsm)) begin
grp_fu_652_p0 = reg_795;
end else if ((ap_ST_st55_fsm_55 == ap_CS_fsm)) begin
grp_fu_652_p0 = reg_903;
end else if ((ap_ST_st53_fsm_53 == ap_CS_fsm)) begin
grp_fu_652_p0 = reg_1284;
end else if (((ap_ST_st51_fsm_51 == ap_CS_fsm) | (ap_ST_st59_fsm_59 == ap_CS_fsm))) begin
grp_fu_652_p0 = reg_1047;
end else if ((ap_ST_st49_fsm_49 == ap_CS_fsm)) begin
grp_fu_652_p0 = reg_954;
end else if ((ap_ST_st47_fsm_47 == ap_CS_fsm)) begin
grp_fu_652_p0 = reg_931;
end else if ((ap_ST_st45_fsm_45 == ap_CS_fsm)) begin
grp_fu_652_p0 = reg_1019;
end else if (((ap_ST_st37_fsm_37 == ap_CS_fsm) | (ap_ST_st41_fsm_41 == ap_CS_fsm))) begin
grp_fu_652_p0 = X_qy;
end else if ((ap_ST_st33_fsm_33 == ap_CS_fsm)) begin
grp_fu_652_p0 = reg_829;
end else if ((ap_ST_st29_fsm_29 == ap_CS_fsm)) begin
grp_fu_652_p0 = X_qx;
end else begin
grp_fu_652_p0 = X_qy;
end
end
/// grp_fu_652_p1 assign process. ///
always @ (ap_CS_fsm or U_x or U_y or U_qr or reg_795 or reg_850 or reg_889 or reg_903 or reg_1136 or reg_1299)
begin
if ((ap_ST_st59_fsm_59 == ap_CS_fsm)) begin
grp_fu_652_p1 = U_qr;
end else if ((ap_ST_st57_fsm_57 == ap_CS_fsm)) begin
grp_fu_652_p1 = reg_1299;
end else if (((ap_ST_st63_fsm_63 == ap_CS_fsm) | (ap_ST_st55_fsm_55 == ap_CS_fsm))) begin
grp_fu_652_p1 = reg_850;
end else if ((ap_ST_st51_fsm_51 == ap_CS_fsm)) begin
grp_fu_652_p1 = reg_903;
end else if (((ap_ST_st53_fsm_53 == ap_CS_fsm) | (ap_ST_st49_fsm_49 == ap_CS_fsm))) begin
grp_fu_652_p1 = ap_const_lv32_40000000;
end else if ((ap_ST_st47_fsm_47 == ap_CS_fsm)) begin
grp_fu_652_p1 = reg_1136;
end else if ((ap_ST_st45_fsm_45 == ap_CS_fsm)) begin
grp_fu_652_p1 = reg_795;
end else if ((ap_ST_st41_fsm_41 == ap_CS_fsm)) begin
grp_fu_652_p1 = reg_889;
end else if ((ap_ST_st37_fsm_37 == ap_CS_fsm)) begin
grp_fu_652_p1 = U_y;
end else if ((ap_ST_st33_fsm_33 == ap_CS_fsm)) begin
grp_fu_652_p1 = U_x;
end else if ((ap_ST_st29_fsm_29 == ap_CS_fsm)) begin
grp_fu_652_p1 = ap_const_lv32_C0000000;
end else begin
grp_fu_652_p1 = ap_const_lv32_C0000000;
end
end
/// grp_fu_658_p0 assign process. ///
always @ (ap_CS_fsm or X_qr or X_qz or reg_795 or reg_943 or reg_1047 or reg_1057 or reg_1315 or reg_1375 or X_plus_U_qz_reg_1782)
begin
if ((ap_ST_st59_fsm_59 == ap_CS_fsm)) begin
grp_fu_658_p0 = reg_1047;
end else if ((ap_ST_st55_fsm_55 == ap_CS_fsm)) begin
grp_fu_658_p0 = reg_943;
end else if (((ap_ST_st53_fsm_53 == ap_CS_fsm) | (ap_ST_st57_fsm_57 == ap_CS_fsm))) begin
grp_fu_658_p0 = reg_795;
end else if (((ap_ST_st51_fsm_51 == ap_CS_fsm) | (ap_ST_st63_fsm_63 == ap_CS_fsm))) begin
grp_fu_658_p0 = reg_1375;
end else if ((ap_ST_st49_fsm_49 == ap_CS_fsm)) begin
grp_fu_658_p0 = reg_1315;
end else if ((ap_ST_st47_fsm_47 == ap_CS_fsm)) begin
grp_fu_658_p0 = X_plus_U_qz_reg_1782;
end else if ((ap_ST_st45_fsm_45 == ap_CS_fsm)) begin
grp_fu_658_p0 = reg_1057;
end else if (((ap_ST_st37_fsm_37 == ap_CS_fsm) | (ap_ST_st41_fsm_41 == ap_CS_fsm))) begin
grp_fu_658_p0 = X_qz;
end else if ((ap_ST_st33_fsm_33 == ap_CS_fsm)) begin
grp_fu_658_p0 = X_qr;
end else begin
grp_fu_658_p0 = X_plus_U_qz_reg_1782;
end
end
/// grp_fu_658_p1 assign process. ///
always @ (ap_CS_fsm or U_y or U_z or U_qr or U_qx or reg_795 or reg_889 or reg_903 or reg_1123 or reg_1136 or reg_1307)
begin
if ((ap_ST_st59_fsm_59 == ap_CS_fsm)) begin
grp_fu_658_p1 = U_qx;
end else if ((ap_ST_st57_fsm_57 == ap_CS_fsm)) begin
grp_fu_658_p1 = reg_1307;
end else if (((ap_ST_st63_fsm_63 == ap_CS_fsm) | (ap_ST_st55_fsm_55 == ap_CS_fsm))) begin
grp_fu_658_p1 = U_qr;
end else if ((ap_ST_st53_fsm_53 == ap_CS_fsm)) begin
grp_fu_658_p1 = reg_1123;
end else if ((ap_ST_st51_fsm_51 == ap_CS_fsm)) begin
grp_fu_658_p1 = reg_903;
end else if ((ap_ST_st47_fsm_47 == ap_CS_fsm)) begin
grp_fu_658_p1 = reg_1136;
end else if (((ap_ST_st45_fsm_45 == ap_CS_fsm) | (ap_ST_st49_fsm_49 == ap_CS_fsm))) begin
grp_fu_658_p1 = reg_795;
end else if ((ap_ST_st41_fsm_41 == ap_CS_fsm)) begin
grp_fu_658_p1 = reg_889;
end else if ((ap_ST_st37_fsm_37 == ap_CS_fsm)) begin
grp_fu_658_p1 = U_z;
end else if ((ap_ST_st33_fsm_33 == ap_CS_fsm)) begin
grp_fu_658_p1 = U_y;
end else begin
grp_fu_658_p1 = U_z;
end
end
/// grp_fu_663_p0 assign process. ///
always @ (ap_CS_fsm or X_qr or X_qz or reg_795 or reg_829 or reg_850 or reg_903 or reg_1072 or reg_1167 or reg_1261 or reg_1325 or reg_1394)
begin
if ((ap_ST_st63_fsm_63 == ap_CS_fsm)) begin
grp_fu_663_p0 = reg_1394;
end else if ((ap_ST_st59_fsm_59 == ap_CS_fsm)) begin
grp_fu_663_p0 = reg_1261;
end else if ((ap_ST_st55_fsm_55 == ap_CS_fsm)) begin
grp_fu_663_p0 = reg_903;
end else if ((ap_ST_st53_fsm_53 == ap_CS_fsm)) begin
grp_fu_663_p0 = reg_795;
end else if ((ap_ST_st51_fsm_51 == ap_CS_fsm)) begin
grp_fu_663_p0 = reg_1167;
end else if ((ap_ST_st49_fsm_49 == ap_CS_fsm)) begin
grp_fu_663_p0 = reg_1325;
end else if ((ap_ST_st47_fsm_47 == ap_CS_fsm)) begin
grp_fu_663_p0 = reg_850;
end else if ((ap_ST_st45_fsm_45 == ap_CS_fsm)) begin
grp_fu_663_p0 = reg_1072;
end else if ((ap_ST_st41_fsm_41 == ap_CS_fsm)) begin
grp_fu_663_p0 = X_qr;
end else if (((ap_ST_st37_fsm_37 == ap_CS_fsm) | (ap_ST_st57_fsm_57 == ap_CS_fsm))) begin
grp_fu_663_p0 = reg_829;
end else if ((ap_ST_st33_fsm_33 == ap_CS_fsm)) begin
grp_fu_663_p0 = X_qz;
end else begin
grp_fu_663_p0 = X_qz;
end
end
/// grp_fu_663_p1 assign process. ///
always @ (ap_CS_fsm or U_x or U_qy or U_qz or reg_795 or reg_869 or reg_903 or reg_1072 or reg_1144 or reg_1157 or reg_1201 or reg_1242)
begin
if ((ap_ST_st63_fsm_63 == ap_CS_fsm)) begin
grp_fu_663_p1 = U_qz;
end else if ((ap_ST_st59_fsm_59 == ap_CS_fsm)) begin
grp_fu_663_p1 = U_qy;
end else if ((ap_ST_st57_fsm_57 == ap_CS_fsm)) begin
grp_fu_663_p1 = reg_1242;
end else if ((ap_ST_st55_fsm_55 == ap_CS_fsm)) begin
grp_fu_663_p1 = reg_869;
end else if ((ap_ST_st53_fsm_53 == ap_CS_fsm)) begin
grp_fu_663_p1 = reg_1201;
end else if ((ap_ST_st51_fsm_51 == ap_CS_fsm)) begin
grp_fu_663_p1 = reg_903;
end else if ((ap_ST_st49_fsm_49 == ap_CS_fsm)) begin
grp_fu_663_p1 = reg_1072;
end else if ((ap_ST_st47_fsm_47 == ap_CS_fsm)) begin
grp_fu_663_p1 = reg_1144;
end else if ((ap_ST_st45_fsm_45 == ap_CS_fsm)) begin
grp_fu_663_p1 = reg_795;
end else if ((ap_ST_st41_fsm_41 == ap_CS_fsm)) begin
grp_fu_663_p1 = reg_1157;
end else if (((ap_ST_st33_fsm_33 == ap_CS_fsm) | (ap_ST_st37_fsm_37 == ap_CS_fsm))) begin
grp_fu_663_p1 = U_x;
end else begin
grp_fu_663_p1 = U_x;
end
end
/// grp_fu_668_p0 assign process. ///
always @ (ap_CS_fsm or X_qx or X_qy or reg_795 or reg_829 or reg_931 or reg_943 or reg_961 or reg_999 or reg_1261 or reg_1315 or reg_1394)
begin
if ((ap_ST_st63_fsm_63 == ap_CS_fsm)) begin
grp_fu_668_p0 = reg_1394;
end else if ((ap_ST_st59_fsm_59 == ap_CS_fsm)) begin
grp_fu_668_p0 = reg_1261;
end else if ((ap_ST_st57_fsm_57 == ap_CS_fsm)) begin
grp_fu_668_p0 = reg_829;
end else if ((ap_ST_st55_fsm_55 == ap_CS_fsm)) begin
grp_fu_668_p0 = reg_943;
end else if ((ap_ST_st53_fsm_53 == ap_CS_fsm)) begin
grp_fu_668_p0 = reg_795;
end else if ((ap_ST_st51_fsm_51 == ap_CS_fsm)) begin
grp_fu_668_p0 = reg_999;
end else if ((ap_ST_st49_fsm_49 == ap_CS_fsm)) begin
grp_fu_668_p0 = reg_1315;
end else if ((ap_ST_st47_fsm_47 == ap_CS_fsm)) begin
grp_fu_668_p0 = reg_931;
end else if ((ap_ST_st45_fsm_45 == ap_CS_fsm)) begin
grp_fu_668_p0 = reg_961;
end else if ((ap_ST_st37_fsm_37 == ap_CS_fsm)) begin
grp_fu_668_p0 = X_qx;
end else if (((ap_ST_st33_fsm_33 == ap_CS_fsm) | (ap_ST_st41_fsm_41 == ap_CS_fsm))) begin
grp_fu_668_p0 = X_qy;
end else begin
grp_fu_668_p0 = X_qy;
end
end
/// grp_fu_668_p1 assign process. ///
always @ (ap_CS_fsm or U_x or U_y or U_qy or U_qz or reg_795 or reg_829 or reg_903 or reg_961 or reg_1144 or reg_1157 or reg_1220 or reg_1252)
begin
if ((ap_ST_st63_fsm_63 == ap_CS_fsm)) begin
grp_fu_668_p1 = U_qy;
end else if ((ap_ST_st59_fsm_59 == ap_CS_fsm)) begin
grp_fu_668_p1 = reg_961;
end else if ((ap_ST_st57_fsm_57 == ap_CS_fsm)) begin
grp_fu_668_p1 = reg_1252;
end else if ((ap_ST_st55_fsm_55 == ap_CS_fsm)) begin
grp_fu_668_p1 = U_qz;
end else if ((ap_ST_st53_fsm_53 == ap_CS_fsm)) begin
grp_fu_668_p1 = reg_1220;
end else if ((ap_ST_st51_fsm_51 == ap_CS_fsm)) begin
grp_fu_668_p1 = reg_903;
end else if ((ap_ST_st49_fsm_49 == ap_CS_fsm)) begin
grp_fu_668_p1 = reg_829;
end else if ((ap_ST_st47_fsm_47 == ap_CS_fsm)) begin
grp_fu_668_p1 = reg_1144;
end else if ((ap_ST_st45_fsm_45 == ap_CS_fsm)) begin
grp_fu_668_p1 = reg_795;
end else if ((ap_ST_st41_fsm_41 == ap_CS_fsm)) begin
grp_fu_668_p1 = reg_1157;
end else if ((ap_ST_st37_fsm_37 == ap_CS_fsm)) begin
grp_fu_668_p1 = U_y;
end else if ((ap_ST_st33_fsm_33 == ap_CS_fsm)) begin
grp_fu_668_p1 = U_x;
end else begin
grp_fu_668_p1 = U_x;
end
end
/// grp_fu_673_p0 assign process. ///
always @ (ap_CS_fsm or X_qr or X_qz or reg_795 or reg_829 or reg_903 or reg_1019 or reg_1085 or reg_1261 or reg_1325 or reg_1383 or reg_1394 or X_plus_U_qz_reg_1782)
begin
if ((ap_ST_st63_fsm_63 == ap_CS_fsm)) begin
grp_fu_673_p0 = reg_1394;
end else if ((ap_ST_st59_fsm_59 == ap_CS_fsm)) begin
grp_fu_673_p0 = reg_1261;
end else if ((ap_ST_st57_fsm_57 == ap_CS_fsm)) begin
grp_fu_673_p0 = reg_829;
end else if ((ap_ST_st55_fsm_55 == ap_CS_fsm)) begin
grp_fu_673_p0 = reg_903;
end else if ((ap_ST_st53_fsm_53 == ap_CS_fsm)) begin
grp_fu_673_p0 = reg_795;
end else if ((ap_ST_st51_fsm_51 == ap_CS_fsm)) begin
grp_fu_673_p0 = reg_1383;
end else if ((ap_ST_st49_fsm_49 == ap_CS_fsm)) begin
grp_fu_673_p0 = reg_1325;
end else if ((ap_ST_st47_fsm_47 == ap_CS_fsm)) begin
grp_fu_673_p0 = X_plus_U_qz_reg_1782;
end else if ((ap_ST_st45_fsm_45 == ap_CS_fsm)) begin
grp_fu_673_p0 = reg_1085;
end else if ((ap_ST_st41_fsm_41 == ap_CS_fsm)) begin
grp_fu_673_p0 = X_qz;
end else if ((ap_ST_st37_fsm_37 == ap_CS_fsm)) begin
grp_fu_673_p0 = X_qr;
end else if ((ap_ST_st33_fsm_33 == ap_CS_fsm)) begin
grp_fu_673_p0 = reg_1019;
end else begin
grp_fu_673_p0 = X_plus_U_qz_reg_1782;
end
end
/// grp_fu_673_p1 assign process. ///
always @ (ap_CS_fsm or U_y or U_z or U_qr or reg_795 or reg_850 or reg_903 or reg_961 or reg_1085 or reg_1144 or reg_1157 or reg_1231 or reg_1299)
begin
if ((ap_ST_st63_fsm_63 == ap_CS_fsm)) begin
grp_fu_673_p1 = reg_850;
end else if ((ap_ST_st59_fsm_59 == ap_CS_fsm)) begin
grp_fu_673_p1 = U_qr;
end else if ((ap_ST_st57_fsm_57 == ap_CS_fsm)) begin
grp_fu_673_p1 = reg_1299;
end else if ((ap_ST_st55_fsm_55 == ap_CS_fsm)) begin
grp_fu_673_p1 = reg_961;
end else if ((ap_ST_st53_fsm_53 == ap_CS_fsm)) begin
grp_fu_673_p1 = reg_1231;
end else if ((ap_ST_st51_fsm_51 == ap_CS_fsm)) begin
grp_fu_673_p1 = reg_903;
end else if ((ap_ST_st49_fsm_49 == ap_CS_fsm)) begin
grp_fu_673_p1 = reg_1085;
end else if ((ap_ST_st47_fsm_47 == ap_CS_fsm)) begin
grp_fu_673_p1 = reg_1144;
end else if ((ap_ST_st45_fsm_45 == ap_CS_fsm)) begin
grp_fu_673_p1 = reg_795;
end else if ((ap_ST_st41_fsm_41 == ap_CS_fsm)) begin
grp_fu_673_p1 = reg_1157;
end else if ((ap_ST_st37_fsm_37 == ap_CS_fsm)) begin
grp_fu_673_p1 = U_z;
end else if ((ap_ST_st33_fsm_33 == ap_CS_fsm)) begin
grp_fu_673_p1 = U_y;
end else begin
grp_fu_673_p1 = U_z;
end
end
/// grp_fu_678_p0 assign process. ///
always @ (ap_CS_fsm or X_qr or X_qx or reg_829 or reg_850 or reg_943 or reg_1261 or reg_1315 or reg_1394)
begin
if ((ap_ST_st63_fsm_63 == ap_CS_fsm)) begin
grp_fu_678_p0 = reg_1394;
end else if ((ap_ST_st55_fsm_55 == ap_CS_fsm)) begin
grp_fu_678_p0 = reg_943;
end else if (((ap_ST_st53_fsm_53 == ap_CS_fsm) | (ap_ST_st57_fsm_57 == ap_CS_fsm))) begin
grp_fu_678_p0 = reg_829;
end else if ((ap_ST_st49_fsm_49 == ap_CS_fsm)) begin
grp_fu_678_p0 = reg_1315;
end else if ((ap_ST_st47_fsm_47 == ap_CS_fsm)) begin
grp_fu_678_p0 = reg_850;
end else if (((ap_ST_st45_fsm_45 == ap_CS_fsm) | (ap_ST_st51_fsm_51 == ap_CS_fsm) | (ap_ST_st59_fsm_59 == ap_CS_fsm))) begin
grp_fu_678_p0 = reg_1261;
end else if ((ap_ST_st37_fsm_37 == ap_CS_fsm)) begin
grp_fu_678_p0 = X_qx;
end else if (((ap_ST_st33_fsm_33 == ap_CS_fsm) | (ap_ST_st41_fsm_41 == ap_CS_fsm))) begin
grp_fu_678_p0 = X_qr;
end else begin
grp_fu_678_p0 = X_qr;
end
end
/// grp_fu_678_p1 assign process. ///
always @ (ap_CS_fsm or U_x or U_z or U_qr or U_qx or reg_795 or reg_869 or reg_903 or reg_990 or reg_1019 or reg_1123 or reg_1307 or tmp_27_reg_1869)
begin
if ((ap_ST_st63_fsm_63 == ap_CS_fsm)) begin
grp_fu_678_p1 = U_qr;
end else if ((ap_ST_st59_fsm_59 == ap_CS_fsm)) begin
grp_fu_678_p1 = U_qx;
end else if ((ap_ST_st57_fsm_57 == ap_CS_fsm)) begin
grp_fu_678_p1 = reg_1307;
end else if ((ap_ST_st55_fsm_55 == ap_CS_fsm)) begin
grp_fu_678_p1 = reg_869;
end else if ((ap_ST_st53_fsm_53 == ap_CS_fsm)) begin
grp_fu_678_p1 = reg_1123;
end else if ((ap_ST_st51_fsm_51 == ap_CS_fsm)) begin
grp_fu_678_p1 = reg_903;
end else if ((ap_ST_st49_fsm_49 == ap_CS_fsm)) begin
grp_fu_678_p1 = reg_1019;
end else if ((ap_ST_st47_fsm_47 == ap_CS_fsm)) begin
grp_fu_678_p1 = tmp_27_reg_1869;
end else if ((ap_ST_st45_fsm_45 == ap_CS_fsm)) begin
grp_fu_678_p1 = reg_795;
end else if ((ap_ST_st41_fsm_41 == ap_CS_fsm)) begin
grp_fu_678_p1 = reg_990;
end else if ((ap_ST_st37_fsm_37 == ap_CS_fsm)) begin
grp_fu_678_p1 = U_z;
end else if ((ap_ST_st33_fsm_33 == ap_CS_fsm)) begin
grp_fu_678_p1 = U_x;
end else begin
grp_fu_678_p1 = tmp_27_reg_1869;
end
end
/// grp_fu_683_p0 assign process. ///
always @ (ap_CS_fsm or X_qx or reg_829 or reg_869 or reg_1019 or reg_1110 or reg_1167 or reg_1325 or reg_1394 or reg_1425 or reg_1435)
begin
if ((ap_ST_st63_fsm_63 == ap_CS_fsm)) begin
grp_fu_683_p0 = reg_1435;
end else if ((ap_ST_st59_fsm_59 == ap_CS_fsm)) begin
grp_fu_683_p0 = reg_1425;
end else if ((ap_ST_st57_fsm_57 == ap_CS_fsm)) begin
grp_fu_683_p0 = reg_1019;
end else if ((ap_ST_st55_fsm_55 == ap_CS_fsm)) begin
grp_fu_683_p0 = reg_1167;
end else if ((ap_ST_st51_fsm_51 == ap_CS_fsm)) begin
grp_fu_683_p0 = reg_1394;
end else if ((ap_ST_st49_fsm_49 == ap_CS_fsm)) begin
grp_fu_683_p0 = reg_1325;
end else if ((ap_ST_st47_fsm_47 == ap_CS_fsm)) begin
grp_fu_683_p0 = reg_869;
end else if ((ap_ST_st45_fsm_45 == ap_CS_fsm)) begin
grp_fu_683_p0 = reg_1110;
end else if (((ap_ST_st37_fsm_37 == ap_CS_fsm) | (ap_ST_st41_fsm_41 == ap_CS_fsm))) begin
grp_fu_683_p0 = X_qx;
end else if (((ap_ST_st33_fsm_33 == ap_CS_fsm) | (ap_ST_st53_fsm_53 == ap_CS_fsm))) begin
grp_fu_683_p0 = reg_829;
end else begin
grp_fu_683_p0 = X_qx;
end
end
/// grp_fu_683_p1 assign process. ///
always @ (ap_CS_fsm or U_x or U_y or U_qr or U_qy or U_qz or reg_795 or reg_903 or reg_990 or reg_1098 or reg_1201 or reg_1242 or tmp_27_reg_1869)
begin
if ((ap_ST_st63_fsm_63 == ap_CS_fsm)) begin
grp_fu_683_p1 = U_qz;
end else if ((ap_ST_st59_fsm_59 == ap_CS_fsm)) begin
grp_fu_683_p1 = U_qy;
end else if ((ap_ST_st57_fsm_57 == ap_CS_fsm)) begin
grp_fu_683_p1 = reg_1242;
end else if ((ap_ST_st55_fsm_55 == ap_CS_fsm)) begin
grp_fu_683_p1 = U_qr;
end else if ((ap_ST_st53_fsm_53 == ap_CS_fsm)) begin
grp_fu_683_p1 = reg_1201;
end else if ((ap_ST_st51_fsm_51 == ap_CS_fsm)) begin
grp_fu_683_p1 = reg_903;
end else if ((ap_ST_st49_fsm_49 == ap_CS_fsm)) begin
grp_fu_683_p1 = reg_1098;
end else if ((ap_ST_st47_fsm_47 == ap_CS_fsm)) begin
grp_fu_683_p1 = tmp_27_reg_1869;
end else if ((ap_ST_st45_fsm_45 == ap_CS_fsm)) begin
grp_fu_683_p1 = reg_795;
end else if ((ap_ST_st41_fsm_41 == ap_CS_fsm)) begin
grp_fu_683_p1 = reg_990;
end else if ((ap_ST_st37_fsm_37 == ap_CS_fsm)) begin
grp_fu_683_p1 = U_x;
end else if ((ap_ST_st33_fsm_33 == ap_CS_fsm)) begin
grp_fu_683_p1 = U_y;
end else begin
grp_fu_683_p1 = tmp_27_reg_1869;
end
end
/// grp_fu_692_p0 assign process. ///
always @ (ap_CS_fsm or X_qz or U_x or reg_829 or reg_1019 or reg_1123 or reg_1315 or reg_1383 or reg_1403 or reg_1425 or reg_1435 or X_plus_U_qz_reg_1782)
begin
if ((ap_ST_st63_fsm_63 == ap_CS_fsm)) begin
grp_fu_692_p0 = reg_1435;
end else if ((ap_ST_st59_fsm_59 == ap_CS_fsm)) begin
grp_fu_692_p0 = reg_1425;
end else if ((ap_ST_st57_fsm_57 == ap_CS_fsm)) begin
grp_fu_692_p0 = reg_1019;
end else if ((ap_ST_st55_fsm_55 == ap_CS_fsm)) begin
grp_fu_692_p0 = reg_1383;
end else if ((ap_ST_st53_fsm_53 == ap_CS_fsm)) begin
grp_fu_692_p0 = reg_829;
end else if ((ap_ST_st51_fsm_51 == ap_CS_fsm)) begin
grp_fu_692_p0 = reg_1403;
end else if ((ap_ST_st49_fsm_49 == ap_CS_fsm)) begin
grp_fu_692_p0 = reg_1315;
end else if ((ap_ST_st47_fsm_47 == ap_CS_fsm)) begin
grp_fu_692_p0 = X_plus_U_qz_reg_1782;
end else if ((ap_ST_st45_fsm_45 == ap_CS_fsm)) begin
grp_fu_692_p0 = reg_1123;
end else if ((ap_ST_st41_fsm_41 == ap_CS_fsm)) begin
grp_fu_692_p0 = X_qz;
end else if ((ap_ST_st37_fsm_37 == ap_CS_fsm)) begin
grp_fu_692_p0 = U_x;
end else begin
grp_fu_692_p0 = U_x;
end
end
/// grp_fu_692_p1 assign process. ///
always @ (ap_CS_fsm or U_qx or U_qy or reg_795 or reg_903 or reg_961 or reg_990 or reg_1057 or reg_1220 or reg_1252 or tmp_27_reg_1869)
begin
if ((ap_ST_st63_fsm_63 == ap_CS_fsm)) begin
grp_fu_692_p1 = U_qy;
end else if ((ap_ST_st59_fsm_59 == ap_CS_fsm)) begin
grp_fu_692_p1 = reg_961;
end else if ((ap_ST_st57_fsm_57 == ap_CS_fsm)) begin
grp_fu_692_p1 = reg_1252;
end else if ((ap_ST_st55_fsm_55 == ap_CS_fsm)) begin
grp_fu_692_p1 = U_qx;
end else if ((ap_ST_st53_fsm_53 == ap_CS_fsm)) begin
grp_fu_692_p1 = reg_1220;
end else if ((ap_ST_st51_fsm_51 == ap_CS_fsm)) begin
grp_fu_692_p1 = reg_903;
end else if ((ap_ST_st49_fsm_49 == ap_CS_fsm)) begin
grp_fu_692_p1 = reg_1057;
end else if ((ap_ST_st47_fsm_47 == ap_CS_fsm)) begin
grp_fu_692_p1 = tmp_27_reg_1869;
end else if ((ap_ST_st45_fsm_45 == ap_CS_fsm)) begin
grp_fu_692_p1 = reg_795;
end else if (((ap_ST_st37_fsm_37 == ap_CS_fsm) | (ap_ST_st41_fsm_41 == ap_CS_fsm))) begin
grp_fu_692_p1 = reg_990;
end else begin
grp_fu_692_p1 = tmp_27_reg_1869;
end
end
/// grp_fu_696_p0 assign process. ///
always @ (ap_CS_fsm or X_qr or reg_829 or reg_850 or reg_983 or reg_1013 or reg_1019 or reg_1167 or reg_1325 or reg_1425 or reg_1435)
begin
if ((ap_ST_st63_fsm_63 == ap_CS_fsm)) begin
grp_fu_696_p0 = reg_1435;
end else if ((ap_ST_st59_fsm_59 == ap_CS_fsm)) begin
grp_fu_696_p0 = reg_1425;
end else if ((ap_ST_st55_fsm_55 == ap_CS_fsm)) begin
grp_fu_696_p0 = reg_1167;
end else if ((ap_ST_st53_fsm_53 == ap_CS_fsm)) begin
grp_fu_696_p0 = reg_829;
end else if ((ap_ST_st51_fsm_51 == ap_CS_fsm)) begin
grp_fu_696_p0 = reg_1013;
end else if ((ap_ST_st49_fsm_49 == ap_CS_fsm)) begin
grp_fu_696_p0 = reg_1325;
end else if ((ap_ST_st47_fsm_47 == ap_CS_fsm)) begin
grp_fu_696_p0 = reg_850;
end else if ((ap_ST_st45_fsm_45 == ap_CS_fsm)) begin
grp_fu_696_p0 = reg_983;
end else if ((ap_ST_st41_fsm_41 == ap_CS_fsm)) begin
grp_fu_696_p0 = X_qr;
end else if (((ap_ST_st37_fsm_37 == ap_CS_fsm) | (ap_ST_st57_fsm_57 == ap_CS_fsm))) begin
grp_fu_696_p0 = reg_1019;
end else begin
grp_fu_696_p0 = X_qr;
end
end
/// grp_fu_696_p1 assign process. ///
always @ (ap_CS_fsm or U_z or U_qr or reg_795 or reg_850 or reg_903 or reg_1038 or reg_1110 or reg_1231 or reg_1291 or reg_1299)
begin
if ((ap_ST_st59_fsm_59 == ap_CS_fsm)) begin
grp_fu_696_p1 = U_qr;
end else if ((ap_ST_st57_fsm_57 == ap_CS_fsm)) begin
grp_fu_696_p1 = reg_1299;
end else if (((ap_ST_st63_fsm_63 == ap_CS_fsm) | (ap_ST_st55_fsm_55 == ap_CS_fsm))) begin
grp_fu_696_p1 = reg_850;
end else if ((ap_ST_st53_fsm_53 == ap_CS_fsm)) begin
grp_fu_696_p1 = reg_1231;
end else if ((ap_ST_st51_fsm_51 == ap_CS_fsm)) begin
grp_fu_696_p1 = reg_903;
end else if ((ap_ST_st49_fsm_49 == ap_CS_fsm)) begin
grp_fu_696_p1 = reg_1110;
end else if ((ap_ST_st47_fsm_47 == ap_CS_fsm)) begin
grp_fu_696_p1 = reg_1291;
end else if ((ap_ST_st45_fsm_45 == ap_CS_fsm)) begin
grp_fu_696_p1 = reg_795;
end else if ((ap_ST_st41_fsm_41 == ap_CS_fsm)) begin
grp_fu_696_p1 = reg_1038;
end else if ((ap_ST_st37_fsm_37 == ap_CS_fsm)) begin
grp_fu_696_p1 = U_z;
end else begin
grp_fu_696_p1 = U_z;
end
end
/// grp_fu_701_p0 assign process. ///
always @ (ap_CS_fsm or X_qx or U_x or reg_869 or reg_1019 or reg_1201 or reg_1335 or reg_1383 or reg_1414 or reg_1425 or reg_1435)
begin
if ((ap_ST_st63_fsm_63 == ap_CS_fsm)) begin
grp_fu_701_p0 = reg_1435;
end else if ((ap_ST_st59_fsm_59 == ap_CS_fsm)) begin
grp_fu_701_p0 = reg_1425;
end else if ((ap_ST_st55_fsm_55 == ap_CS_fsm)) begin
grp_fu_701_p0 = reg_1383;
end else if (((ap_ST_st53_fsm_53 == ap_CS_fsm) | (ap_ST_st57_fsm_57 == ap_CS_fsm))) begin
grp_fu_701_p0 = reg_1019;
end else if ((ap_ST_st51_fsm_51 == ap_CS_fsm)) begin
grp_fu_701_p0 = reg_1414;
end else if ((ap_ST_st49_fsm_49 == ap_CS_fsm)) begin
grp_fu_701_p0 = reg_1335;
end else if ((ap_ST_st47_fsm_47 == ap_CS_fsm)) begin
grp_fu_701_p0 = reg_869;
end else if ((ap_ST_st45_fsm_45 == ap_CS_fsm)) begin
grp_fu_701_p0 = reg_1201;
end else if ((ap_ST_st41_fsm_41 == ap_CS_fsm)) begin
grp_fu_701_p0 = X_qx;
end else if ((ap_ST_st37_fsm_37 == ap_CS_fsm)) begin
grp_fu_701_p0 = U_x;
end else begin
grp_fu_701_p0 = U_x;
end
end
/// grp_fu_701_p1 assign process. ///
always @ (ap_CS_fsm or U_qr or U_qx or reg_795 or reg_889 or reg_903 or reg_1038 or reg_1123 or reg_1291 or reg_1307)
begin
if ((ap_ST_st59_fsm_59 == ap_CS_fsm)) begin
grp_fu_701_p1 = U_qx;
end else if ((ap_ST_st57_fsm_57 == ap_CS_fsm)) begin
grp_fu_701_p1 = reg_1307;
end else if (((ap_ST_st63_fsm_63 == ap_CS_fsm) | (ap_ST_st55_fsm_55 == ap_CS_fsm))) begin
grp_fu_701_p1 = U_qr;
end else if ((ap_ST_st53_fsm_53 == ap_CS_fsm)) begin
grp_fu_701_p1 = reg_1123;
end else if ((ap_ST_st51_fsm_51 == ap_CS_fsm)) begin
grp_fu_701_p1 = reg_903;
end else if ((ap_ST_st47_fsm_47 == ap_CS_fsm)) begin
grp_fu_701_p1 = reg_1291;
end else if (((ap_ST_st45_fsm_45 == ap_CS_fsm) | (ap_ST_st49_fsm_49 == ap_CS_fsm))) begin
grp_fu_701_p1 = reg_795;
end else if ((ap_ST_st41_fsm_41 == ap_CS_fsm)) begin
grp_fu_701_p1 = reg_1038;
end else if ((ap_ST_st37_fsm_37 == ap_CS_fsm)) begin
grp_fu_701_p1 = reg_889;
end else begin
grp_fu_701_p1 = U_qr;
end
end
/// grp_fu_705_p0 assign process. ///
always @ (ap_CS_fsm or X_qy or X_qz or reg_931 or reg_1019 or reg_1167 or reg_1220 or reg_1345 or reg_1425 or tmp_42_reg_1886 or tmp_43_reg_1894)
begin
if ((ap_ST_st63_fsm_63 == ap_CS_fsm)) begin
grp_fu_705_p0 = tmp_43_reg_1894;
end else if ((ap_ST_st59_fsm_59 == ap_CS_fsm)) begin
grp_fu_705_p0 = tmp_42_reg_1886;
end else if ((ap_ST_st55_fsm_55 == ap_CS_fsm)) begin
grp_fu_705_p0 = reg_1167;
end else if ((ap_ST_st53_fsm_53 == ap_CS_fsm)) begin
grp_fu_705_p0 = reg_1019;
end else if ((ap_ST_st51_fsm_51 == ap_CS_fsm)) begin
grp_fu_705_p0 = reg_1425;
end else if ((ap_ST_st49_fsm_49 == ap_CS_fsm)) begin
grp_fu_705_p0 = reg_1345;
end else if ((ap_ST_st47_fsm_47 == ap_CS_fsm)) begin
grp_fu_705_p0 = reg_931;
end else if ((ap_ST_st45_fsm_45 == ap_CS_fsm)) begin
grp_fu_705_p0 = reg_1220;
end else if ((ap_ST_st41_fsm_41 == ap_CS_fsm)) begin
grp_fu_705_p0 = X_qy;
end else if ((ap_ST_st37_fsm_37 == ap_CS_fsm)) begin
grp_fu_705_p0 = X_qz;
end else begin
grp_fu_705_p0 = tmp_43_reg_1894;
end
end
/// grp_fu_705_p1 assign process. ///
always @ (ap_CS_fsm or U_y or U_qy or U_qz or reg_795 or reg_869 or reg_903 or reg_1038 or reg_1072 or reg_1201 or reg_1291)
begin
if ((ap_ST_st63_fsm_63 == ap_CS_fsm)) begin
grp_fu_705_p1 = U_qz;
end else if ((ap_ST_st59_fsm_59 == ap_CS_fsm)) begin
grp_fu_705_p1 = U_qy;
end else if ((ap_ST_st55_fsm_55 == ap_CS_fsm)) begin
grp_fu_705_p1 = reg_869;
end else if ((ap_ST_st53_fsm_53 == ap_CS_fsm)) begin
grp_fu_705_p1 = reg_1201;
end else if ((ap_ST_st51_fsm_51 == ap_CS_fsm)) begin
grp_fu_705_p1 = reg_903;
end else if ((ap_ST_st49_fsm_49 == ap_CS_fsm)) begin
grp_fu_705_p1 = reg_1072;
end else if ((ap_ST_st47_fsm_47 == ap_CS_fsm)) begin
grp_fu_705_p1 = reg_1291;
end else if ((ap_ST_st45_fsm_45 == ap_CS_fsm)) begin
grp_fu_705_p1 = reg_795;
end else if ((ap_ST_st41_fsm_41 == ap_CS_fsm)) begin
grp_fu_705_p1 = reg_1038;
end else if ((ap_ST_st37_fsm_37 == ap_CS_fsm)) begin
grp_fu_705_p1 = U_y;
end else begin
grp_fu_705_p1 = U_y;
end
end
/// grp_fu_709_p0 assign process. ///
always @ (ap_CS_fsm or reg_829 or reg_1019 or reg_1231 or reg_1335 or reg_1383 or reg_1435 or tmp_42_reg_1886 or tmp_43_reg_1894)
begin
if ((ap_ST_st63_fsm_63 == ap_CS_fsm)) begin
grp_fu_709_p0 = tmp_43_reg_1894;
end else if ((ap_ST_st59_fsm_59 == ap_CS_fsm)) begin
grp_fu_709_p0 = tmp_42_reg_1886;
end else if ((ap_ST_st55_fsm_55 == ap_CS_fsm)) begin
grp_fu_709_p0 = reg_1383;
end else if ((ap_ST_st53_fsm_53 == ap_CS_fsm)) begin
grp_fu_709_p0 = reg_1019;
end else if ((ap_ST_st51_fsm_51 == ap_CS_fsm)) begin
grp_fu_709_p0 = reg_1435;
end else if ((ap_ST_st49_fsm_49 == ap_CS_fsm)) begin
grp_fu_709_p0 = reg_1335;
end else if ((ap_ST_st45_fsm_45 == ap_CS_fsm)) begin
grp_fu_709_p0 = reg_1231;
end else if ((ap_ST_st37_fsm_37 == ap_CS_fsm)) begin
grp_fu_709_p0 = reg_829;
end else begin
grp_fu_709_p0 = tmp_43_reg_1894;
end
end
/// grp_fu_709_p1 assign process. ///
always @ (ap_CS_fsm or U_z or U_qy or U_qz or reg_795 or reg_829 or reg_903 or reg_961 or reg_1220)
begin
if ((ap_ST_st63_fsm_63 == ap_CS_fsm)) begin
grp_fu_709_p1 = U_qy;
end else if ((ap_ST_st59_fsm_59 == ap_CS_fsm)) begin
grp_fu_709_p1 = reg_961;
end else if ((ap_ST_st55_fsm_55 == ap_CS_fsm)) begin
grp_fu_709_p1 = U_qz;
end else if ((ap_ST_st53_fsm_53 == ap_CS_fsm)) begin
grp_fu_709_p1 = reg_1220;
end else if ((ap_ST_st51_fsm_51 == ap_CS_fsm)) begin
grp_fu_709_p1 = reg_903;
end else if ((ap_ST_st49_fsm_49 == ap_CS_fsm)) begin
grp_fu_709_p1 = reg_829;
end else if ((ap_ST_st45_fsm_45 == ap_CS_fsm)) begin
grp_fu_709_p1 = reg_795;
end else if ((ap_ST_st37_fsm_37 == ap_CS_fsm)) begin
grp_fu_709_p1 = U_z;
end else begin
grp_fu_709_p1 = U_z;
end
end
/// grp_fu_714_p0 assign process. ///
always @ (ap_CS_fsm or reg_1019 or reg_1167 or reg_1242 or reg_1345 or reg_1444 or tmp_42_reg_1886 or tmp_43_reg_1894)
begin
if ((ap_ST_st63_fsm_63 == ap_CS_fsm)) begin
grp_fu_714_p0 = tmp_43_reg_1894;
end else if ((ap_ST_st59_fsm_59 == ap_CS_fsm)) begin
grp_fu_714_p0 = tmp_42_reg_1886;
end else if ((ap_ST_st55_fsm_55 == ap_CS_fsm)) begin
grp_fu_714_p0 = reg_1167;
end else if ((ap_ST_st53_fsm_53 == ap_CS_fsm)) begin
grp_fu_714_p0 = reg_1019;
end else if ((ap_ST_st51_fsm_51 == ap_CS_fsm)) begin
grp_fu_714_p0 = reg_1444;
end else if ((ap_ST_st49_fsm_49 == ap_CS_fsm)) begin
grp_fu_714_p0 = reg_1345;
end else if ((ap_ST_st45_fsm_45 == ap_CS_fsm)) begin
grp_fu_714_p0 = reg_1242;
end else begin
grp_fu_714_p0 = tmp_43_reg_1894;
end
end
/// grp_fu_714_p1 assign process. ///
always @ (ap_CS_fsm or U_qr or reg_795 or reg_850 or reg_903 or reg_961 or reg_1085 or reg_1231)
begin
if ((ap_ST_st63_fsm_63 == ap_CS_fsm)) begin
grp_fu_714_p1 = reg_850;
end else if ((ap_ST_st59_fsm_59 == ap_CS_fsm)) begin
grp_fu_714_p1 = U_qr;
end else if ((ap_ST_st55_fsm_55 == ap_CS_fsm)) begin
grp_fu_714_p1 = reg_961;
end else if ((ap_ST_st53_fsm_53 == ap_CS_fsm)) begin
grp_fu_714_p1 = reg_1231;
end else if ((ap_ST_st51_fsm_51 == ap_CS_fsm)) begin
grp_fu_714_p1 = reg_903;
end else if ((ap_ST_st49_fsm_49 == ap_CS_fsm)) begin
grp_fu_714_p1 = reg_1085;
end else if ((ap_ST_st45_fsm_45 == ap_CS_fsm)) begin
grp_fu_714_p1 = reg_795;
end else begin
grp_fu_714_p1 = U_qr;
end
end
/// grp_fu_718_p0 assign process. ///
always @ (ap_CS_fsm or reg_1335 or reg_1383 or tmp_48_reg_1776 or tmp_4_reg_1793 or tmp_42_reg_1886 or tmp_43_reg_1894)
begin
if ((ap_ST_st63_fsm_63 == ap_CS_fsm)) begin
grp_fu_718_p0 = tmp_43_reg_1894;
end else if ((ap_ST_st59_fsm_59 == ap_CS_fsm)) begin
grp_fu_718_p0 = tmp_42_reg_1886;
end else if ((ap_ST_st55_fsm_55 == ap_CS_fsm)) begin
grp_fu_718_p0 = reg_1383;
end else if ((ap_ST_st51_fsm_51 == ap_CS_fsm)) begin
grp_fu_718_p0 = tmp_4_reg_1793;
end else if ((ap_ST_st49_fsm_49 == ap_CS_fsm)) begin
grp_fu_718_p0 = reg_1335;
end else if ((ap_ST_st45_fsm_45 == ap_CS_fsm)) begin
grp_fu_718_p0 = tmp_48_reg_1776;
end else begin
grp_fu_718_p0 = tmp_43_reg_1894;
end
end
/// grp_fu_718_p1 assign process. ///
always @ (ap_CS_fsm or U_qr or U_qx or reg_795 or reg_869 or reg_903 or reg_1019)
begin
if ((ap_ST_st63_fsm_63 == ap_CS_fsm)) begin
grp_fu_718_p1 = U_qr;
end else if ((ap_ST_st59_fsm_59 == ap_CS_fsm)) begin
grp_fu_718_p1 = U_qx;
end else if ((ap_ST_st55_fsm_55 == ap_CS_fsm)) begin
grp_fu_718_p1 = reg_869;
end else if ((ap_ST_st51_fsm_51 == ap_CS_fsm)) begin
grp_fu_718_p1 = reg_903;
end else if ((ap_ST_st49_fsm_49 == ap_CS_fsm)) begin
grp_fu_718_p1 = reg_1019;
end else if ((ap_ST_st45_fsm_45 == ap_CS_fsm)) begin
grp_fu_718_p1 = reg_795;
end else begin
grp_fu_718_p1 = U_qr;
end
end
/// grp_fu_722_p0 assign process. ///
always @ (ap_CS_fsm or reg_889 or reg_1345 or reg_1403)
begin
if ((ap_ST_st55_fsm_55 == ap_CS_fsm)) begin
grp_fu_722_p0 = reg_1403;
end else if ((ap_ST_st49_fsm_49 == ap_CS_fsm)) begin
grp_fu_722_p0 = reg_1345;
end else if ((ap_ST_st45_fsm_45 == ap_CS_fsm)) begin
grp_fu_722_p0 = reg_889;
end else begin
grp_fu_722_p0 = reg_1403;
end
end
/// grp_fu_722_p1 assign process. ///
always @ (ap_CS_fsm or U_qr or reg_1098)
begin
if ((ap_ST_st55_fsm_55 == ap_CS_fsm)) begin
grp_fu_722_p1 = U_qr;
end else if ((ap_ST_st49_fsm_49 == ap_CS_fsm)) begin
grp_fu_722_p1 = reg_1098;
end else if ((ap_ST_st45_fsm_45 == ap_CS_fsm)) begin
grp_fu_722_p1 = ap_const_lv32_40000000;
end else begin
grp_fu_722_p1 = ap_const_lv32_40000000;
end
end
/// grp_fu_727_p0 assign process. ///
always @ (ap_CS_fsm or reg_990 or reg_1335 or reg_1414)
begin
if ((ap_ST_st55_fsm_55 == ap_CS_fsm)) begin
grp_fu_727_p0 = reg_1414;
end else if ((ap_ST_st49_fsm_49 == ap_CS_fsm)) begin
grp_fu_727_p0 = reg_1335;
end else if ((ap_ST_st45_fsm_45 == ap_CS_fsm)) begin
grp_fu_727_p0 = reg_990;
end else begin
grp_fu_727_p0 = reg_1414;
end
end
/// grp_fu_727_p1 assign process. ///
always @ (ap_CS_fsm or U_qx or reg_1057)
begin
if ((ap_ST_st55_fsm_55 == ap_CS_fsm)) begin
grp_fu_727_p1 = U_qx;
end else if ((ap_ST_st49_fsm_49 == ap_CS_fsm)) begin
grp_fu_727_p1 = reg_1057;
end else if ((ap_ST_st45_fsm_45 == ap_CS_fsm)) begin
grp_fu_727_p1 = ap_const_lv32_40000000;
end else begin
grp_fu_727_p1 = ap_const_lv32_40000000;
end
end
/// grp_fu_732_p0 assign process. ///
always @ (ap_CS_fsm or reg_1157 or reg_1345 or reg_1403)
begin
if ((ap_ST_st55_fsm_55 == ap_CS_fsm)) begin
grp_fu_732_p0 = reg_1403;
end else if ((ap_ST_st49_fsm_49 == ap_CS_fsm)) begin
grp_fu_732_p0 = reg_1345;
end else if ((ap_ST_st45_fsm_45 == ap_CS_fsm)) begin
grp_fu_732_p0 = reg_1157;
end else begin
grp_fu_732_p0 = reg_1403;
end
end
/// grp_fu_732_p1 assign process. ///
always @ (ap_CS_fsm or reg_850 or reg_1110)
begin
if ((ap_ST_st55_fsm_55 == ap_CS_fsm)) begin
grp_fu_732_p1 = reg_850;
end else if ((ap_ST_st49_fsm_49 == ap_CS_fsm)) begin
grp_fu_732_p1 = reg_1110;
end else if ((ap_ST_st45_fsm_45 == ap_CS_fsm)) begin
grp_fu_732_p1 = ap_const_lv32_40000000;
end else begin
grp_fu_732_p1 = ap_const_lv32_40000000;
end
end
/// grp_fu_737_p0 assign process. ///
always @ (ap_CS_fsm or reg_1178 or reg_1355 or reg_1414)
begin
if ((ap_ST_st55_fsm_55 == ap_CS_fsm)) begin
grp_fu_737_p0 = reg_1414;
end else if ((ap_ST_st49_fsm_49 == ap_CS_fsm)) begin
grp_fu_737_p0 = reg_1355;
end else if ((ap_ST_st45_fsm_45 == ap_CS_fsm)) begin
grp_fu_737_p0 = reg_1178;
end else begin
grp_fu_737_p0 = reg_1414;
end
end
/// grp_fu_737_p1 assign process. ///
always @ (ap_CS_fsm or U_qr or reg_795)
begin
if ((ap_ST_st55_fsm_55 == ap_CS_fsm)) begin
grp_fu_737_p1 = U_qr;
end else if ((ap_ST_st49_fsm_49 == ap_CS_fsm)) begin
grp_fu_737_p1 = reg_795;
end else if ((ap_ST_st45_fsm_45 == ap_CS_fsm)) begin
grp_fu_737_p1 = ap_const_lv32_40000000;
end else begin
grp_fu_737_p1 = ap_const_lv32_40000000;
end
end
/// grp_fu_742_p0 assign process. ///
always @ (ap_CS_fsm or reg_1212 or reg_1365 or reg_1403)
begin
if ((ap_ST_st55_fsm_55 == ap_CS_fsm)) begin
grp_fu_742_p0 = reg_1403;
end else if ((ap_ST_st49_fsm_49 == ap_CS_fsm)) begin
grp_fu_742_p0 = reg_1365;
end else if ((ap_ST_st45_fsm_45 == ap_CS_fsm)) begin
grp_fu_742_p0 = reg_1212;
end else begin
grp_fu_742_p0 = reg_1403;
end
end
/// grp_fu_742_p1 assign process. ///
always @ (ap_CS_fsm or reg_869 or reg_1072)
begin
if ((ap_ST_st55_fsm_55 == ap_CS_fsm)) begin
grp_fu_742_p1 = reg_869;
end else if ((ap_ST_st49_fsm_49 == ap_CS_fsm)) begin
grp_fu_742_p1 = reg_1072;
end else if ((ap_ST_st45_fsm_45 == ap_CS_fsm)) begin
grp_fu_742_p1 = ap_const_lv32_40000000;
end else begin
grp_fu_742_p1 = ap_const_lv32_40000000;
end
end
/// grp_fu_747_p0 assign process. ///
always @ (ap_CS_fsm or reg_1270 or reg_1355 or reg_1414)
begin
if ((ap_ST_st55_fsm_55 == ap_CS_fsm)) begin
grp_fu_747_p0 = reg_1414;
end else if ((ap_ST_st49_fsm_49 == ap_CS_fsm)) begin
grp_fu_747_p0 = reg_1355;
end else if ((ap_ST_st45_fsm_45 == ap_CS_fsm)) begin
grp_fu_747_p0 = reg_1270;
end else begin
grp_fu_747_p0 = reg_1414;
end
end
/// grp_fu_747_p1 assign process. ///
always @ (ap_CS_fsm or U_qz or reg_829)
begin
if ((ap_ST_st55_fsm_55 == ap_CS_fsm)) begin
grp_fu_747_p1 = U_qz;
end else if ((ap_ST_st49_fsm_49 == ap_CS_fsm)) begin
grp_fu_747_p1 = reg_829;
end else if ((ap_ST_st45_fsm_45 == ap_CS_fsm)) begin
grp_fu_747_p1 = ap_const_lv32_40000000;
end else begin
grp_fu_747_p1 = ap_const_lv32_40000000;
end
end
/// grp_fu_755_p0 assign process. ///
always @ (ap_CS_fsm or reg_1365 or reg_1403)
begin
if ((ap_ST_st55_fsm_55 == ap_CS_fsm)) begin
grp_fu_755_p0 = reg_1403;
end else if ((ap_ST_st49_fsm_49 == ap_CS_fsm)) begin
grp_fu_755_p0 = reg_1365;
end else begin
grp_fu_755_p0 = reg_1403;
end
end
/// grp_fu_755_p1 assign process. ///
always @ (ap_CS_fsm or reg_961 or reg_1085)
begin
if ((ap_ST_st55_fsm_55 == ap_CS_fsm)) begin
grp_fu_755_p1 = reg_961;
end else if ((ap_ST_st49_fsm_49 == ap_CS_fsm)) begin
grp_fu_755_p1 = reg_1085;
end else begin
grp_fu_755_p1 = reg_1085;
end
end
/// grp_fu_759_p0 assign process. ///
always @ (ap_CS_fsm or reg_1355 or reg_1414)
begin
if ((ap_ST_st55_fsm_55 == ap_CS_fsm)) begin
grp_fu_759_p0 = reg_1414;
end else if ((ap_ST_st49_fsm_49 == ap_CS_fsm)) begin
grp_fu_759_p0 = reg_1355;
end else begin
grp_fu_759_p0 = reg_1414;
end
end
/// grp_fu_759_p1 assign process. ///
always @ (ap_CS_fsm or reg_869 or reg_1019)
begin
if ((ap_ST_st55_fsm_55 == ap_CS_fsm)) begin
grp_fu_759_p1 = reg_869;
end else if ((ap_ST_st49_fsm_49 == ap_CS_fsm)) begin
grp_fu_759_p1 = reg_1019;
end else begin
grp_fu_759_p1 = reg_1019;
end
end
/// grp_fu_763_p0 assign process. ///
always @ (ap_CS_fsm or reg_1365 or reg_1444)
begin
if ((ap_ST_st55_fsm_55 == ap_CS_fsm)) begin
grp_fu_763_p0 = reg_1444;
end else if ((ap_ST_st49_fsm_49 == ap_CS_fsm)) begin
grp_fu_763_p0 = reg_1365;
end else begin
grp_fu_763_p0 = reg_1444;
end
end
/// grp_fu_763_p1 assign process. ///
always @ (ap_CS_fsm or U_qr or reg_1098)
begin
if ((ap_ST_st55_fsm_55 == ap_CS_fsm)) begin
grp_fu_763_p1 = U_qr;
end else if ((ap_ST_st49_fsm_49 == ap_CS_fsm)) begin
grp_fu_763_p1 = reg_1098;
end else begin
grp_fu_763_p1 = U_qr;
end
end
/// grp_fu_767_p0 assign process. ///
always @ (ap_CS_fsm or reg_1355 or reg_1521)
begin
if ((ap_ST_st55_fsm_55 == ap_CS_fsm)) begin
grp_fu_767_p0 = reg_1521;
end else if ((ap_ST_st49_fsm_49 == ap_CS_fsm)) begin
grp_fu_767_p0 = reg_1355;
end else begin
grp_fu_767_p0 = reg_1521;
end
end
/// grp_fu_767_p1 assign process. ///
always @ (ap_CS_fsm or U_qx or reg_1057)
begin
if ((ap_ST_st55_fsm_55 == ap_CS_fsm)) begin
grp_fu_767_p1 = U_qx;
end else if ((ap_ST_st49_fsm_49 == ap_CS_fsm)) begin
grp_fu_767_p1 = reg_1057;
end else begin
grp_fu_767_p1 = U_qx;
end
end
/// grp_fu_771_p0 assign process. ///
always @ (ap_CS_fsm or reg_1365 or reg_1444)
begin
if ((ap_ST_st55_fsm_55 == ap_CS_fsm)) begin
grp_fu_771_p0 = reg_1444;
end else if ((ap_ST_st49_fsm_49 == ap_CS_fsm)) begin
grp_fu_771_p0 = reg_1365;
end else begin
grp_fu_771_p0 = reg_1444;
end
end
/// grp_fu_771_p1 assign process. ///
always @ (ap_CS_fsm or reg_850 or reg_1110)
begin
if ((ap_ST_st55_fsm_55 == ap_CS_fsm)) begin
grp_fu_771_p1 = reg_850;
end else if ((ap_ST_st49_fsm_49 == ap_CS_fsm)) begin
grp_fu_771_p1 = reg_1110;
end else begin
grp_fu_771_p1 = reg_1110;
end
end
/// out_X_oplus_U_qr_ce0 assign process. ///
always @ (ap_CS_fsm)
begin
if ((ap_ST_st47_fsm_47 == ap_CS_fsm)) begin
out_X_oplus_U_qr_ce0 = ap_const_logic_1;
end else begin
out_X_oplus_U_qr_ce0 = ap_const_logic_0;
end
end
/// out_X_oplus_U_qr_we0 assign process. ///
always @ (ap_CS_fsm)
begin
if ((ap_ST_st47_fsm_47 == ap_CS_fsm)) begin
out_X_oplus_U_qr_we0 = ap_const_logic_1;
end else begin
out_X_oplus_U_qr_we0 = ap_const_logic_0;
end
end
/// out_X_oplus_U_qx_ce0 assign process. ///
always @ (ap_CS_fsm)
begin
if ((ap_ST_st47_fsm_47 == ap_CS_fsm)) begin
out_X_oplus_U_qx_ce0 = ap_const_logic_1;
end else begin
out_X_oplus_U_qx_ce0 = ap_const_logic_0;
end
end
/// out_X_oplus_U_qx_we0 assign process. ///
always @ (ap_CS_fsm)
begin
if ((ap_ST_st47_fsm_47 == ap_CS_fsm)) begin
out_X_oplus_U_qx_we0 = ap_const_logic_1;
end else begin
out_X_oplus_U_qx_we0 = ap_const_logic_0;
end
end
/// out_X_oplus_U_qy_ce0 assign process. ///
always @ (ap_CS_fsm)
begin
if ((ap_ST_st47_fsm_47 == ap_CS_fsm)) begin
out_X_oplus_U_qy_ce0 = ap_const_logic_1;
end else begin
out_X_oplus_U_qy_ce0 = ap_const_logic_0;
end
end
/// out_X_oplus_U_qy_we0 assign process. ///
always @ (ap_CS_fsm)
begin
if ((ap_ST_st47_fsm_47 == ap_CS_fsm)) begin
out_X_oplus_U_qy_we0 = ap_const_logic_1;
end else begin
out_X_oplus_U_qy_we0 = ap_const_logic_0;
end
end
/// out_X_oplus_U_qz_ce0 assign process. ///
always @ (ap_CS_fsm)
begin
if ((ap_ST_st47_fsm_47 == ap_CS_fsm)) begin
out_X_oplus_U_qz_ce0 = ap_const_logic_1;
end else begin
out_X_oplus_U_qz_ce0 = ap_const_logic_0;
end
end
/// out_X_oplus_U_qz_we0 assign process. ///
always @ (ap_CS_fsm)
begin
if ((ap_ST_st47_fsm_47 == ap_CS_fsm)) begin
out_X_oplus_U_qz_we0 = ap_const_logic_1;
end else begin
out_X_oplus_U_qz_we0 = ap_const_logic_0;
end
end
/// out_X_oplus_U_x_ce0 assign process. ///
always @ (ap_CS_fsm)
begin
if ((ap_ST_st41_fsm_41 == ap_CS_fsm)) begin
out_X_oplus_U_x_ce0 = ap_const_logic_1;
end else begin
out_X_oplus_U_x_ce0 = ap_const_logic_0;
end
end
/// out_X_oplus_U_x_we0 assign process. ///
always @ (ap_CS_fsm)
begin
if ((ap_ST_st41_fsm_41 == ap_CS_fsm)) begin
out_X_oplus_U_x_we0 = ap_const_logic_1;
end else begin
out_X_oplus_U_x_we0 = ap_const_logic_0;
end
end
/// out_X_oplus_U_y_ce0 assign process. ///
always @ (ap_CS_fsm)
begin
if ((ap_ST_st41_fsm_41 == ap_CS_fsm)) begin
out_X_oplus_U_y_ce0 = ap_const_logic_1;
end else begin
out_X_oplus_U_y_ce0 = ap_const_logic_0;
end
end
/// out_X_oplus_U_y_we0 assign process. ///
always @ (ap_CS_fsm)
begin
if ((ap_ST_st41_fsm_41 == ap_CS_fsm)) begin
out_X_oplus_U_y_we0 = ap_const_logic_1;
end else begin
out_X_oplus_U_y_we0 = ap_const_logic_0;
end
end
/// out_X_oplus_U_z_ce0 assign process. ///
always @ (ap_CS_fsm)
begin
if ((ap_ST_st41_fsm_41 == ap_CS_fsm)) begin
out_X_oplus_U_z_ce0 = ap_const_logic_1;
end else begin
out_X_oplus_U_z_ce0 = ap_const_logic_0;
end
end
/// out_X_oplus_U_z_we0 assign process. ///
always @ (ap_CS_fsm)
begin
if ((ap_ST_st41_fsm_41 == ap_CS_fsm)) begin
out_X_oplus_U_z_we0 = ap_const_logic_1;
end else begin
out_X_oplus_U_z_we0 = ap_const_logic_0;
end
end
assign grp_fu_555_ce = ap_const_logic_1;
assign grp_fu_560_ce = ap_const_logic_1;
assign grp_fu_566_ce = ap_const_logic_1;
assign grp_fu_571_ce = ap_const_logic_1;
assign grp_fu_583_ce = ap_const_logic_1;
assign grp_fu_588_ce = ap_const_logic_1;
assign grp_fu_592_ce = ap_const_logic_1;
assign grp_fu_596_ce = ap_const_logic_1;
assign grp_fu_600_ce = ap_const_logic_1;
assign grp_fu_604_ce = ap_const_logic_1;
assign grp_fu_608_ce = ap_const_logic_1;
assign grp_fu_612_ce = ap_const_logic_1;
assign grp_fu_618_ce = ap_const_logic_1;
assign grp_fu_622_ce = ap_const_logic_1;
assign grp_fu_626_ce = ap_const_logic_1;
assign grp_fu_630_ce = ap_const_logic_1;
assign grp_fu_634_ce = ap_const_logic_1;
assign grp_fu_640_ce = ap_const_logic_1;
assign grp_fu_652_ce = ap_const_logic_1;
assign grp_fu_658_ce = ap_const_logic_1;
assign grp_fu_663_ce = ap_const_logic_1;
assign grp_fu_668_ce = ap_const_logic_1;
assign grp_fu_673_ce = ap_const_logic_1;
assign grp_fu_678_ce = ap_const_logic_1;
assign grp_fu_683_ce = ap_const_logic_1;
assign grp_fu_692_ce = ap_const_logic_1;
assign grp_fu_696_ce = ap_const_logic_1;
assign grp_fu_701_ce = ap_const_logic_1;
assign grp_fu_705_ce = ap_const_logic_1;
assign grp_fu_709_ce = ap_const_logic_1;
assign grp_fu_714_ce = ap_const_logic_1;
assign grp_fu_718_ce = ap_const_logic_1;
assign grp_fu_722_ce = ap_const_logic_1;
assign grp_fu_727_ce = ap_const_logic_1;
assign grp_fu_732_ce = ap_const_logic_1;
assign grp_fu_737_ce = ap_const_logic_1;
assign grp_fu_742_ce = ap_const_logic_1;
assign grp_fu_747_ce = ap_const_logic_1;
assign grp_fu_755_ce = ap_const_logic_1;
assign grp_fu_759_ce = ap_const_logic_1;
assign grp_fu_763_ce = ap_const_logic_1;
assign grp_fu_767_ce = ap_const_logic_1;
assign grp_fu_771_ce = ap_const_logic_1;
assign grp_fu_775_ce = ap_const_logic_1;
assign grp_fu_775_p0 = reg_1521;
assign grp_fu_775_p1 = U_qr;
assign grp_fu_779_ce = ap_const_logic_1;
assign grp_fu_779_p0 = reg_1444;
assign grp_fu_779_p1 = reg_869;
assign grp_fu_783_ce = ap_const_logic_1;
assign grp_fu_783_p0 = reg_1521;
assign grp_fu_783_p1 = U_qz;
assign grp_fu_787_ce = ap_const_logic_1;
assign grp_fu_787_p0 = reg_1444;
assign grp_fu_787_p1 = reg_961;
assign grp_fu_791_ce = ap_const_logic_1;
assign grp_fu_791_p0 = reg_1521;
assign grp_fu_791_p1 = reg_869;
assign i_1_fu_1646_p1 = {{1{tmp_52_reg_1809[30]}}, {tmp_52_reg_1809}};
assign i_1_fu_1646_p2 = (ap_const_lv32_5F3759D5 - i_1_fu_1646_p1);
assign i_2_fu_1629_p1 = reg_903;
assign i_3_fu_1601_p1 = reg_795;
assign i_fu_1618_p1 = {{1{tmp_53_reg_1799[30]}}, {tmp_53_reg_1799}};
assign i_fu_1618_p2 = (ap_const_lv32_5F3759D5 - i_fu_1618_p1);
assign out_X_oplus_U_qr_address0 = ap_const_lv64_0;
assign out_X_oplus_U_qr_address1 = ap_const_lv1_0;
assign out_X_oplus_U_qr_ce1 = ap_const_logic_0;
assign out_X_oplus_U_qr_d0 = reg_850;
assign out_X_oplus_U_qr_d1 = ap_const_lv32_0;
assign out_X_oplus_U_qr_we1 = ap_const_logic_0;
assign out_X_oplus_U_qx_address0 = ap_const_lv64_0;
assign out_X_oplus_U_qx_address1 = ap_const_lv1_0;
assign out_X_oplus_U_qx_ce1 = ap_const_logic_0;
assign out_X_oplus_U_qx_d0 = reg_869;
assign out_X_oplus_U_qx_d1 = ap_const_lv32_0;
assign out_X_oplus_U_qx_we1 = ap_const_logic_0;
assign out_X_oplus_U_qy_address0 = ap_const_lv64_0;
assign out_X_oplus_U_qy_address1 = ap_const_lv1_0;
assign out_X_oplus_U_qy_ce1 = ap_const_logic_0;
assign out_X_oplus_U_qy_d0 = reg_931;
assign out_X_oplus_U_qy_d1 = ap_const_lv32_0;
assign out_X_oplus_U_qy_we1 = ap_const_logic_0;
assign out_X_oplus_U_qz_address0 = ap_const_lv64_0;
assign out_X_oplus_U_qz_address1 = ap_const_lv1_0;
assign out_X_oplus_U_qz_ce1 = ap_const_logic_0;
assign out_X_oplus_U_qz_d0 = X_plus_U_qz_reg_1782;
assign out_X_oplus_U_qz_d1 = ap_const_lv32_0;
assign out_X_oplus_U_qz_we1 = ap_const_logic_0;
assign out_X_oplus_U_x_address0 = ap_const_lv64_0;
assign out_X_oplus_U_x_address1 = ap_const_lv1_0;
assign out_X_oplus_U_x_ce1 = ap_const_logic_0;
assign out_X_oplus_U_x_d0 = reg_1006;
assign out_X_oplus_U_x_d1 = ap_const_lv32_0;
assign out_X_oplus_U_x_we1 = ap_const_logic_0;
assign out_X_oplus_U_y_address0 = ap_const_lv64_0;
assign out_X_oplus_U_y_address1 = ap_const_lv1_0;
assign out_X_oplus_U_y_ce1 = ap_const_logic_0;
assign out_X_oplus_U_y_d0 = reg_1136;
assign out_X_oplus_U_y_d1 = ap_const_lv32_0;
assign out_X_oplus_U_y_we1 = ap_const_logic_0;
assign out_X_oplus_U_z_address0 = ap_const_lv64_0;
assign out_X_oplus_U_z_address1 = ap_const_lv1_0;
assign out_X_oplus_U_z_ce1 = ap_const_logic_0;
assign out_X_oplus_U_z_d0 = reg_1144;
assign out_X_oplus_U_z_d1 = ap_const_lv32_0;
assign out_X_oplus_U_z_we1 = ap_const_logic_0;
assign tmp1_i1_fu_1624_p1 = i_fu_1618_p2;
assign tmp1_i_fu_1652_p1 = i_1_fu_1646_p2;
endmodule //jacobiansPoseComposition
|
// ==============================================================
// File generated by AutoESL - High-Level Synthesis System (C, C++, SystemC)
// Version: 2011.1
// Copyright (C) 2011 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module jacobiansPoseComposition_grp_fu_555_ACMP_faddfsub_1(
clk,
reset,
ce,
din0,
din1,
opcode,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
input[2 - 1:0] opcode;
output[dout_WIDTH - 1:0] dout;
ACMP_faddfsub #(
.ID( ID ),
.NUM_STAGE( 4 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_faddfsub_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ),
.opcode( opcode ));
endmodule
|
// ==============================================================
// File generated by AutoESL - High-Level Synthesis System (C, C++, SystemC)
// Version: 2011.1
// Copyright (C) 2011 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module jacobiansPoseComposition_grp_fu_560_ACMP_faddfsub_2(
clk,
reset,
ce,
din0,
din1,
opcode,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
input[2 - 1:0] opcode;
output[dout_WIDTH - 1:0] dout;
ACMP_faddfsub #(
.ID( ID ),
.NUM_STAGE( 4 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_faddfsub_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ),
.opcode( opcode ));
endmodule
|
// ==============================================================
// File generated by AutoESL - High-Level Synthesis System (C, C++, SystemC)
// Version: 2011.1
// Copyright (C) 2011 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module jacobiansPoseComposition_grp_fu_566_ACMP_faddfsub_3(
clk,
reset,
ce,
din0,
din1,
opcode,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
input[2 - 1:0] opcode;
output[dout_WIDTH - 1:0] dout;
ACMP_faddfsub #(
.ID( ID ),
.NUM_STAGE( 4 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_faddfsub_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ),
.opcode( opcode ));
endmodule
|
// ==============================================================
// File generated by AutoESL - High-Level Synthesis System (C, C++, SystemC)
// Version: 2011.1
// Copyright (C) 2011 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module jacobiansPoseComposition_grp_fu_571_ACMP_faddfsub_4(
clk,
reset,
ce,
din0,
din1,
opcode,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
input[2 - 1:0] opcode;
output[dout_WIDTH - 1:0] dout;
ACMP_faddfsub #(
.ID( ID ),
.NUM_STAGE( 4 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_faddfsub_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ),
.opcode( opcode ));
endmodule
|
// ==============================================================
// File generated by AutoESL - High-Level Synthesis System (C, C++, SystemC)
// Version: 2011.1
// Copyright (C) 2011 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module jacobiansPoseComposition_grp_fu_583_ACMP_faddfsub_5(
clk,
reset,
ce,
din0,
din1,
opcode,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
input[2 - 1:0] opcode;
output[dout_WIDTH - 1:0] dout;
ACMP_faddfsub #(
.ID( ID ),
.NUM_STAGE( 4 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_faddfsub_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ),
.opcode( opcode ));
endmodule
|
// ==============================================================
// File generated by AutoESL - High-Level Synthesis System (C, C++, SystemC)
// Version: 2011.1
// Copyright (C) 2011 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module jacobiansPoseComposition_grp_fu_588_ACMP_faddfsub_6(
clk,
reset,
ce,
din0,
din1,
opcode,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
input[2 - 1:0] opcode;
output[dout_WIDTH - 1:0] dout;
ACMP_faddfsub #(
.ID( ID ),
.NUM_STAGE( 4 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_faddfsub_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ),
.opcode( opcode ));
endmodule
|
// ==============================================================
// File generated by AutoESL - High-Level Synthesis System (C, C++, SystemC)
// Version: 2011.1
// Copyright (C) 2011 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module jacobiansPoseComposition_grp_fu_592_ACMP_fadd_7(
clk,
reset,
ce,
din0,
din1,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
output[dout_WIDTH - 1:0] dout;
ACMP_fadd #(
.ID( ID ),
.NUM_STAGE( 4 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_fadd_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ));
endmodule
|
// ==============================================================
// File generated by AutoESL - High-Level Synthesis System (C, C++, SystemC)
// Version: 2011.1
// Copyright (C) 2011 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module jacobiansPoseComposition_grp_fu_596_ACMP_fadd_8(
clk,
reset,
ce,
din0,
din1,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
output[dout_WIDTH - 1:0] dout;
ACMP_fadd #(
.ID( ID ),
.NUM_STAGE( 4 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_fadd_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ));
endmodule
|
// ==============================================================
// File generated by AutoESL - High-Level Synthesis System (C, C++, SystemC)
// Version: 2011.1
// Copyright (C) 2011 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module jacobiansPoseComposition_grp_fu_600_ACMP_fadd_9(
clk,
reset,
ce,
din0,
din1,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
output[dout_WIDTH - 1:0] dout;
ACMP_fadd #(
.ID( ID ),
.NUM_STAGE( 4 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_fadd_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ));
endmodule
|
// ==============================================================
// File generated by AutoESL - High-Level Synthesis System (C, C++, SystemC)
// Version: 2011.1
// Copyright (C) 2011 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module jacobiansPoseComposition_grp_fu_604_ACMP_fadd_10(
clk,
reset,
ce,
din0,
din1,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
output[dout_WIDTH - 1:0] dout;
ACMP_fadd #(
.ID( ID ),
.NUM_STAGE( 4 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_fadd_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ));
endmodule
|
// ==============================================================
// File generated by AutoESL - High-Level Synthesis System (C, C++, SystemC)
// Version: 2011.1
// Copyright (C) 2011 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module jacobiansPoseComposition_grp_fu_608_ACMP_fadd_11(
clk,
reset,
ce,
din0,
din1,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
output[dout_WIDTH - 1:0] dout;
ACMP_fadd #(
.ID( ID ),
.NUM_STAGE( 4 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_fadd_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ));
endmodule
|
// ==============================================================
// File generated by AutoESL - High-Level Synthesis System (C, C++, SystemC)
// Version: 2011.1
// Copyright (C) 2011 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module jacobiansPoseComposition_grp_fu_612_ACMP_fadd_12(
clk,
reset,
ce,
din0,
din1,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
output[dout_WIDTH - 1:0] dout;
ACMP_fadd #(
.ID( ID ),
.NUM_STAGE( 4 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_fadd_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ));
endmodule
|
// ==============================================================
// File generated by AutoESL - High-Level Synthesis System (C, C++, SystemC)
// Version: 2011.1
// Copyright (C) 2011 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module jacobiansPoseComposition_grp_fu_618_ACMP_fadd_13(
clk,
reset,
ce,
din0,
din1,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
output[dout_WIDTH - 1:0] dout;
ACMP_fadd #(
.ID( ID ),
.NUM_STAGE( 4 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_fadd_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ));
endmodule
|
// ==============================================================
// File generated by AutoESL - High-Level Synthesis System (C, C++, SystemC)
// Version: 2011.1
// Copyright (C) 2011 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module jacobiansPoseComposition_grp_fu_622_ACMP_fadd_14(
clk,
reset,
ce,
din0,
din1,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
output[dout_WIDTH - 1:0] dout;
ACMP_fadd #(
.ID( ID ),
.NUM_STAGE( 4 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_fadd_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ));
endmodule
|
// ==============================================================
// File generated by AutoESL - High-Level Synthesis System (C, C++, SystemC)
// Version: 2011.1
// Copyright (C) 2011 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module jacobiansPoseComposition_grp_fu_626_ACMP_fadd_15(
clk,
reset,
ce,
din0,
din1,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
output[dout_WIDTH - 1:0] dout;
ACMP_fadd #(
.ID( ID ),
.NUM_STAGE( 4 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_fadd_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ));
endmodule
|
// ==============================================================
// File generated by AutoESL - High-Level Synthesis System (C, C++, SystemC)
// Version: 2011.1
// Copyright (C) 2011 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module jacobiansPoseComposition_grp_fu_630_ACMP_fadd_16(
clk,
reset,
ce,
din0,
din1,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
output[dout_WIDTH - 1:0] dout;
ACMP_fadd #(
.ID( ID ),
.NUM_STAGE( 4 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_fadd_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ));
endmodule
|
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