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//////////////////////////////////////////////////////////////////////
//// ////
//// eth_spram_256x32.v ////
//// ////
//// This file is part of the Ethernet IP core project ////
//// http://www.opencores.org/projects/ethmac/ ////
//// ////
//// Author(s): ////
//// - Igor Mohor ([email protected]) ////
//// ////
//// All additional information is available in the Readme.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001, 2002 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: eth_spram_256x32.v,v $
// Revision 1.10 2005/02/21 12:48:07 igorm
// Warning fixes.
//
// Revision 1.9 2003/12/05 12:43:06 tadejm
// Corrected address mismatch for xilinx RAMB4_S8 model which has wider address than RAMB4_S16.
//
// Revision 1.8 2003/12/04 14:59:13 simons
// Lapsus fixed (!we -> ~we).
//
// Revision 1.7 2003/11/12 18:24:59 tadejm
// WISHBONE slave changed and tested from only 32-bit accesss to byte access.
//
// Revision 1.6 2003/10/17 07:46:15 markom
// mbist signals updated according to newest convention
//
// Revision 1.5 2003/08/14 16:42:58 simons
// Artisan ram instance added.
//
// Revision 1.4 2002/10/18 17:04:20 tadejm
// Changed BIST scan signals.
//
// Revision 1.3 2002/10/10 16:29:30 mohor
// BIST added.
//
// Revision 1.2 2002/09/23 18:24:31 mohor
// ETH_VIRTUAL_SILICON_RAM supported (for ASIC implementation).
//
// Revision 1.1 2002/07/23 16:36:09 mohor
// ethernet spram added. So far a generic ram and xilinx RAMB4 are used.
//
//
//
`include "eth_defines.v"
`include "timescale.v"
module eth_spram_256x32(
// Generic synchronous single-port RAM interface
clk, rst, ce, we, oe, addr, di, do
`ifdef ETH_BIST
,
// debug chain signals
mbist_si_i, // bist scan serial in
mbist_so_o, // bist scan serial out
mbist_ctrl_i // bist chain shift control
`endif
);
//
// Generic synchronous single-port RAM interface
//
input clk; // Clock, rising edge
input rst; // Reset, active high
input ce; // Chip enable input, active high
input [3:0] we; // Write enable input, active high
input oe; // Output enable input, active high
input [7:0] addr; // address bus inputs
input [31:0] di; // input data bus
output [31:0] do; // output data bus
`ifdef ETH_BIST
input mbist_si_i; // bist scan serial in
output mbist_so_o; // bist scan serial out
input [`ETH_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i; // bist chain shift control
`endif
`ifdef ETH_XILINX_RAMB4
/*RAMB4_S16 ram0
(
.DO (do[15:0]),
.ADDR (addr),
.DI (di[15:0]),
.EN (ce),
.CLK (clk),
.WE (we),
.RST (rst)
);
RAMB4_S16 ram1
(
.DO (do[31:16]),
.ADDR (addr),
.DI (di[31:16]),
.EN (ce),
.CLK (clk),
.WE (we),
.RST (rst)
);*/
RAMB4_S8 ram0
(
.DO (do[7:0]),
.ADDR ({1'b0, addr}),
.DI (di[7:0]),
.EN (ce),
.CLK (clk),
.WE (we[0]),
.RST (rst)
);
RAMB4_S8 ram1
(
.DO (do[15:8]),
.ADDR ({1'b0, addr}),
.DI (di[15:8]),
.EN (ce),
.CLK (clk),
.WE (we[1]),
.RST (rst)
);
RAMB4_S8 ram2
(
.DO (do[23:16]),
.ADDR ({1'b0, addr}),
.DI (di[23:16]),
.EN (ce),
.CLK (clk),
.WE (we[2]),
.RST (rst)
);
RAMB4_S8 ram3
(
.DO (do[31:24]),
.ADDR ({1'b0, addr}),
.DI (di[31:24]),
.EN (ce),
.CLK (clk),
.WE (we[3]),
.RST (rst)
);
`else // !ETH_XILINX_RAMB4
`ifdef ETH_VIRTUAL_SILICON_RAM
`ifdef ETH_BIST
//vs_hdsp_256x32_bist ram0_bist
vs_hdsp_256x32_bw_bist ram0_bist
`else
//vs_hdsp_256x32 ram0
vs_hdsp_256x32_bw ram0
`endif
(
.CK (clk),
.CEN (!ce),
.WEN (~we),
.OEN (!oe),
.ADR (addr),
.DI (di),
.DOUT (do)
`ifdef ETH_BIST
,
// debug chain signals
.mbist_si_i (mbist_si_i),
.mbist_so_o (mbist_so_o),
.mbist_ctrl_i (mbist_ctrl_i)
`endif
);
`else // !ETH_VIRTUAL_SILICON_RAM
`ifdef ETH_ARTISAN_RAM
`ifdef ETH_BIST
//art_hssp_256x32_bist ram0_bist
art_hssp_256x32_bw_bist ram0_bist
`else
//art_hssp_256x32 ram0
art_hssp_256x32_bw ram0
`endif
(
.CLK (clk),
.CEN (!ce),
.WEN (~we),
.OEN (!oe),
.A (addr),
.D (di),
.Q (do)
`ifdef ETH_BIST
,
// debug chain signals
.mbist_si_i (mbist_si_i),
.mbist_so_o (mbist_so_o),
.mbist_ctrl_i (mbist_ctrl_i)
`endif
);
`else // !ETH_ARTISAN_RAM
`ifdef ETH_ALTERA_ALTSYNCRAM
altera_spram_256x32 altera_spram_256x32_inst
(
.address (addr),
.wren (ce & we),
.clock (clk),
.data (di),
.q (do)
); //exemplar attribute altera_spram_256x32_inst NOOPT TRUE
`else // !ETH_ALTERA_ALTSYNCRAM
//
// Generic single-port synchronous RAM model
//
//
// Generic RAM's registers and wires
//
reg [ 7: 0] mem0 [255:0]; // RAM content
reg [15: 8] mem1 [255:0]; // RAM content
reg [23:16] mem2 [255:0]; // RAM content
reg [31:24] mem3 [255:0]; // RAM content
wire [31:0] q; // RAM output
reg [7:0] raddr; // RAM read address
//
// Data output drivers
//
assign do = (oe & ce) ? q : {32{1'bz}};
//
// RAM read and write
//
// read operation
always@(posedge clk)
if (ce) // && !we)
raddr <= #1 addr; // read address needs to be registered to read clock
assign #1 q = rst ? {32{1'b0}} : {mem3[raddr], mem2[raddr], mem1[raddr], mem0[raddr]};
// write operation
always@(posedge clk)
begin
if (ce && we[3])
mem3[addr] <= #1 di[31:24];
if (ce && we[2])
mem2[addr] <= #1 di[23:16];
if (ce && we[1])
mem1[addr] <= #1 di[15: 8];
if (ce && we[0])
mem0[addr] <= #1 di[ 7: 0];
end
// Task prints range of memory
// *** Remember that tasks are non reentrant, don't call this task in parallel for multiple instantiations.
task print_ram;
input [7:0] start;
input [7:0] finish;
integer rnum;
begin
for (rnum=start;rnum<=finish;rnum=rnum+1)
$display("Addr %h = %0h %0h %0h %0h",rnum,mem3[rnum],mem2[rnum],mem1[rnum],mem0[rnum]);
end
endtask
`endif // !ETH_ALTERA_ALTSYNCRAM
`endif // !ETH_ARTISAN_RAM
`endif // !ETH_VIRTUAL_SILICON_RAM
`endif // !ETH_XILINX_RAMB4
endmodule
|
//////////////////////////////////////////////////////////////////////
//// ////
//// eth_top.v ////
//// ////
//// This file is part of the Ethernet IP core project ////
//// http://www.opencores.org/projects/ethmac/ ////
//// ////
//// Author(s): ////
//// - Igor Mohor ([email protected]) ////
//// ////
//// All additional information is available in the Readme.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001, 2002 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: eth_top.v,v $
// Revision 1.52 2005/03/21 20:07:18 igorm
// Some small fixes + some troubles fixed.
//
// Revision 1.51 2005/02/21 11:13:17 igorm
// Defer indication fixed.
//
// Revision 1.50 2004/04/26 15:26:23 igorm
// - Bug connected to the TX_BD_NUM_Wr signal fixed (bug came in with the
// previous update of the core.
// - TxBDAddress is set to 0 after the TX is enabled in the MODER register.
// - RxBDAddress is set to r_TxBDNum<<1 after the RX is enabled in the MODER
// register. (thanks to Mathias and Torbjorn)
// - Multicast reception was fixed. Thanks to Ulrich Gries
//
// Revision 1.49 2003/11/12 18:24:59 tadejm
// WISHBONE slave changed and tested from only 32-bit accesss to byte access.
//
// Revision 1.48 2003/10/17 07:46:16 markom
// mbist signals updated according to newest convention
//
// Revision 1.47 2003/10/06 15:43:45 knguyen
// Update RxEnSync only when mrxdv_pad_i is inactive (LOW).
//
// Revision 1.46 2003/01/30 13:30:22 tadejm
// Defer indication changed.
//
// Revision 1.45 2003/01/22 13:49:26 tadejm
// When control packets were received, they were ignored in some cases.
//
// Revision 1.44 2003/01/21 12:09:40 mohor
// When receiving normal data frame and RxFlow control was switched on, RXB
// interrupt was not set.
//
// Revision 1.43 2002/11/22 01:57:06 mohor
// Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort
// synchronized.
//
// Revision 1.42 2002/11/21 00:09:19 mohor
// TPauseRq synchronized to tx_clk.
//
// Revision 1.41 2002/11/19 18:13:49 mohor
// r_MiiMRst is not used for resetting the MIIM module. wb_rst used instead.
//
// Revision 1.40 2002/11/19 17:34:25 mohor
// AddressMiss status is connecting to the Rx BD. AddressMiss is identifying
// that a frame was received because of the promiscous mode.
//
// Revision 1.39 2002/11/18 17:31:55 mohor
// wb_rst_i is used for MIIM reset.
//
// Revision 1.38 2002/11/14 18:37:20 mohor
// r_Rst signal does not reset any module any more and is removed from the design.
//
// Revision 1.37 2002/11/13 22:25:36 tadejm
// All modules are reset with wb_rst instead of the r_Rst. Exception is MII module.
//
// Revision 1.36 2002/10/18 17:04:20 tadejm
// Changed BIST scan signals.
//
// Revision 1.35 2002/10/11 13:36:58 mohor
// Typo error fixed. (When using Bist)
//
// Revision 1.34 2002/10/10 16:49:50 mohor
// Signals for WISHBONE B3 compliant interface added.
//
// Revision 1.33 2002/10/10 16:29:30 mohor
// BIST added.
//
// Revision 1.32 2002/09/20 17:12:58 mohor
// CsMiss added. When address between 0x800 and 0xfff is accessed within
// Ethernet Core, error acknowledge is generated.
//
// Revision 1.31 2002/09/12 14:50:17 mohor
// CarrierSenseLost bug fixed when operating in full duplex mode.
//
// Revision 1.30 2002/09/10 10:35:23 mohor
// Ethernet debug registers removed.
//
// Revision 1.29 2002/09/09 13:03:13 mohor
// Error acknowledge is generated when accessing BDs and RST bit in the
// MODER register (r_Rst) is set.
//
// Revision 1.28 2002/09/04 18:44:10 mohor
// Signals related to the control frames connected. Debug registers reg1, 2, 3, 4
// connected.
//
// Revision 1.27 2002/07/25 18:15:37 mohor
// RxAbort changed. Packets received with MRxErr (from PHY) are also
// aborted.
//
// Revision 1.26 2002/07/17 18:51:50 mohor
// EXTERNAL_DMA removed. External DMA not supported.
//
// Revision 1.25 2002/05/03 10:15:50 mohor
// Outputs registered. Reset changed for eth_wishbone module.
//
// Revision 1.24 2002/04/22 14:15:42 mohor
// Wishbone signals are registered when ETH_REGISTERED_OUTPUTS is
// selected in eth_defines.v
//
// Revision 1.23 2002/03/25 13:33:53 mohor
// md_padoen_o changed to md_padoe_o. Signal was always active high, just
// name was incorrect.
//
// Revision 1.22 2002/02/26 16:59:54 mohor
// Small fixes for external/internal DMA missmatches.
//
// Revision 1.21 2002/02/26 16:21:00 mohor
// Interrupts changed in the top file
//
// Revision 1.20 2002/02/18 10:40:17 mohor
// Small fixes.
//
// Revision 1.19 2002/02/16 14:03:44 mohor
// Registered trimmed. Unused registers removed.
//
// Revision 1.18 2002/02/16 13:06:33 mohor
// EXTERNAL_DMA used instead of WISHBONE_DMA.
//
// Revision 1.17 2002/02/16 07:15:27 mohor
// Testbench fixed, code simplified, unused signals removed.
//
// Revision 1.16 2002/02/15 13:49:39 mohor
// RxAbort is connected differently.
//
// Revision 1.15 2002/02/15 11:38:26 mohor
// Changes that were lost when updating from 1.11 to 1.14 fixed.
//
// Revision 1.14 2002/02/14 20:19:11 billditt
// Modified for Address Checking,
// addition of eth_addrcheck.v
//
// Revision 1.13 2002/02/12 17:03:03 mohor
// HASH0 and HASH1 registers added. Registers address width was
// changed to 8 bits.
//
// Revision 1.12 2002/02/11 09:18:22 mohor
// Tx status is written back to the BD.
//
// Revision 1.11 2002/02/08 16:21:54 mohor
// Rx status is written back to the BD.
//
// Revision 1.10 2002/02/06 14:10:21 mohor
// non-DMA host interface added. Select the right configutation in eth_defines.
//
// Revision 1.9 2002/01/23 10:28:16 mohor
// Link in the header changed.
//
// Revision 1.8 2001/12/05 15:00:16 mohor
// RX_BD_NUM changed to TX_BD_NUM (holds number of TX descriptors
// instead of the number of RX descriptors).
//
// Revision 1.7 2001/12/05 10:45:59 mohor
// ETH_RX_BD_ADR register deleted. ETH_RX_BD_NUM is used instead.
//
// Revision 1.6 2001/10/19 11:24:29 mohor
// Number of addresses (wb_adr_i) minimized.
//
// Revision 1.5 2001/10/19 08:43:51 mohor
// eth_timescale.v changed to timescale.v This is done because of the
// simulation of the few cores in a one joined project.
//
// Revision 1.4 2001/10/18 12:07:11 mohor
// Status signals changed, Adress decoding changed, interrupt controller
// added.
//
// Revision 1.3 2001/09/24 15:02:56 mohor
// Defines changed (All precede with ETH_). Small changes because some
// tools generate warnings when two operands are together. Synchronization
// between two clocks domains in eth_wishbonedma.v is changed (due to ASIC
// demands).
//
// Revision 1.2 2001/08/15 14:03:59 mohor
// Signal names changed on the top level for easier pad insertion (ASIC).
//
// Revision 1.1 2001/08/06 14:44:29 mohor
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
// Include files fixed to contain no path.
// File names and module names changed ta have a eth_ prologue in the name.
// File eth_timescale.v is used to define timescale
// All pin names on the top module are changed to contain _I, _O or _OE at the end.
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
// and Mdo_OE. The bidirectional signal must be created on the top level. This
// is done due to the ASIC tools.
//
// Revision 1.2 2001/08/02 09:25:31 mohor
// Unconnected signals are now connected.
//
// Revision 1.1 2001/07/30 21:23:42 mohor
// Directory structure changed. Files checked and joind together.
//
//
//
//
`include "eth_defines.v"
`include "timescale.v"
module eth_top
(
// WISHBONE common
wb_clk_i, wb_rst_i, wb_dat_i, wb_dat_o,
// WISHBONE slave
wb_adr_i, wb_sel_i, wb_we_i, wb_cyc_i, wb_stb_i, wb_ack_o, wb_err_o,
// WISHBONE master
m_wb_adr_o, m_wb_sel_o, m_wb_we_o,
m_wb_dat_o, m_wb_dat_i, m_wb_cyc_o,
m_wb_stb_o, m_wb_ack_i, m_wb_err_i,
`ifdef ETH_WISHBONE_B3
m_wb_cti_o, m_wb_bte_o,
`endif
//TX
mtx_clk_pad_i, mtxd_pad_o, mtxen_pad_o, mtxerr_pad_o,
//RX
mrx_clk_pad_i, mrxd_pad_i, mrxdv_pad_i, mrxerr_pad_i, mcoll_pad_i, mcrs_pad_i,
// MIIM
mdc_pad_o, md_pad_i, md_pad_o, md_padoe_o,
int_o
// Bist
`ifdef ETH_BIST
,
// debug chain signals
mbist_si_i, // bist scan serial in
mbist_so_o, // bist scan serial out
mbist_ctrl_i // bist chain shift control
`endif
);
parameter Tp = 1;
// WISHBONE common
input wb_clk_i; // WISHBONE clock
input wb_rst_i; // WISHBONE reset
input [31:0] wb_dat_i; // WISHBONE data input
output [31:0] wb_dat_o; // WISHBONE data output
output wb_err_o; // WISHBONE error output
// WISHBONE slave
input [11:2] wb_adr_i; // WISHBONE address input
input [3:0] wb_sel_i; // WISHBONE byte select input
input wb_we_i; // WISHBONE write enable input
input wb_cyc_i; // WISHBONE cycle input
input wb_stb_i; // WISHBONE strobe input
output wb_ack_o; // WISHBONE acknowledge output
// WISHBONE master
output [31:0] m_wb_adr_o;
output [3:0] m_wb_sel_o;
output m_wb_we_o;
input [31:0] m_wb_dat_i;
output [31:0] m_wb_dat_o;
output m_wb_cyc_o;
output m_wb_stb_o;
input m_wb_ack_i;
input m_wb_err_i;
wire [29:0] m_wb_adr_tmp;
`ifdef ETH_WISHBONE_B3
output [2:0] m_wb_cti_o; // Cycle Type Identifier
output [1:0] m_wb_bte_o; // Burst Type Extension
`endif
// Tx
input mtx_clk_pad_i; // Transmit clock (from PHY)
output [3:0] mtxd_pad_o; // Transmit nibble (to PHY)
output mtxen_pad_o; // Transmit enable (to PHY)
output mtxerr_pad_o; // Transmit error (to PHY)
// Rx
input mrx_clk_pad_i; // Receive clock (from PHY)
input [3:0] mrxd_pad_i; // Receive nibble (from PHY)
input mrxdv_pad_i; // Receive data valid (from PHY)
input mrxerr_pad_i; // Receive data error (from PHY)
// Common Tx and Rx
input mcoll_pad_i; // Collision (from PHY)
input mcrs_pad_i; // Carrier sense (from PHY)
// MII Management interface
input md_pad_i; // MII data input (from I/O cell)
output mdc_pad_o; // MII Management data clock (to PHY)
output md_pad_o; // MII data output (to I/O cell)
output md_padoe_o; // MII data output enable (to I/O cell)
output int_o; // Interrupt output
// Bist
`ifdef ETH_BIST
input mbist_si_i; // bist scan serial in
output mbist_so_o; // bist scan serial out
input [`ETH_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i; // bist chain shift control
`endif
wire [7:0] r_ClkDiv;
wire r_MiiNoPre;
wire [15:0] r_CtrlData;
wire [4:0] r_FIAD;
wire [4:0] r_RGAD;
wire r_WCtrlData;
wire r_RStat;
wire r_ScanStat;
wire NValid_stat;
wire Busy_stat;
wire LinkFail;
wire [15:0] Prsd; // Read Status Data (data read from the PHY)
wire WCtrlDataStart;
wire RStatStart;
wire UpdateMIIRX_DATAReg;
wire TxStartFrm;
wire TxEndFrm;
wire TxUsedData;
wire [7:0] TxData;
wire TxRetry;
wire TxAbort;
wire TxUnderRun;
wire TxDone;
reg WillSendControlFrame_sync1;
reg WillSendControlFrame_sync2;
reg WillSendControlFrame_sync3;
reg RstTxPauseRq;
reg TxPauseRq_sync1;
reg TxPauseRq_sync2;
reg TxPauseRq_sync3;
reg TPauseRq;
// Connecting Miim module
eth_miim miim1
(
.Clk(wb_clk_i), .Reset(wb_rst_i), .Divider(r_ClkDiv),
.NoPre(r_MiiNoPre), .CtrlData(r_CtrlData), .Rgad(r_RGAD),
.Fiad(r_FIAD), .WCtrlData(r_WCtrlData), .RStat(r_RStat),
.ScanStat(r_ScanStat), .Mdi(md_pad_i), .Mdo(md_pad_o),
.MdoEn(md_padoe_o), .Mdc(mdc_pad_o), .Busy(Busy_stat),
.Prsd(Prsd), .LinkFail(LinkFail), .Nvalid(NValid_stat),
.WCtrlDataStart(WCtrlDataStart), .RStatStart(RStatStart), .UpdateMIIRX_DATAReg(UpdateMIIRX_DATAReg)
);
wire [3:0] RegCs; // Connected to registers
wire [31:0] RegDataOut; // Multiplexed to wb_dat_o
wire r_RecSmall; // Receive small frames
wire r_LoopBck; // Loopback
wire r_TxEn; // Tx Enable
wire r_RxEn; // Rx Enable
wire MRxDV_Lb; // Muxed MII receive data valid
wire MRxErr_Lb; // Muxed MII Receive Error
wire [3:0] MRxD_Lb; // Muxed MII Receive Data
wire Transmitting; // Indication that TxEthMAC is transmitting
wire r_HugEn; // Huge packet enable
wire r_DlyCrcEn; // Delayed CRC enabled
wire [15:0] r_MaxFL; // Maximum frame length
wire [15:0] r_MinFL; // Minimum frame length
wire ShortFrame;
wire DribbleNibble; // Extra nibble received
wire ReceivedPacketTooBig; // Received packet is too big
wire [47:0] r_MAC; // MAC address
wire LoadRxStatus; // Rx status was loaded
wire [31:0] r_HASH0; // HASH table, lower 4 bytes
wire [31:0] r_HASH1; // HASH table, upper 4 bytes
wire [7:0] r_TxBDNum; // Receive buffer descriptor number
wire [6:0] r_IPGT; //
wire [6:0] r_IPGR1; //
wire [6:0] r_IPGR2; //
wire [5:0] r_CollValid; //
wire [15:0] r_TxPauseTV; // Transmit PAUSE value
wire r_TxPauseRq; // Transmit PAUSE request
wire [3:0] r_MaxRet; //
wire r_NoBckof; //
wire r_ExDfrEn; //
wire r_TxFlow; // Tx flow control enable
wire r_IFG; // Minimum interframe gap for incoming packets
wire TxB_IRQ; // Interrupt Tx Buffer
wire TxE_IRQ; // Interrupt Tx Error
wire RxB_IRQ; // Interrupt Rx Buffer
wire RxE_IRQ; // Interrupt Rx Error
wire Busy_IRQ; // Interrupt Busy (lack of buffers)
//wire DWord;
wire ByteSelected;
wire BDAck;
wire [31:0] BD_WB_DAT_O; // wb_dat_o that comes from the Wishbone module (for buffer descriptors read/write)
wire [3:0] BDCs; // Buffer descriptor CS
wire CsMiss; // When access to the address between 0x800 and 0xfff occurs, acknowledge is set
// but data is not valid.
wire r_Pad;
wire r_CrcEn;
wire r_FullD;
wire r_Pro;
wire r_Bro;
wire r_NoPre;
wire r_RxFlow;
wire r_PassAll;
wire TxCtrlEndFrm;
wire StartTxDone;
wire SetPauseTimer;
wire TxUsedDataIn;
wire TxDoneIn;
wire TxAbortIn;
wire PerPacketPad;
wire PadOut;
wire PerPacketCrcEn;
wire CrcEnOut;
wire TxStartFrmOut;
wire TxEndFrmOut;
wire ReceivedPauseFrm;
wire ControlFrmAddressOK;
wire RxStatusWriteLatched_sync2;
wire LateCollision;
wire DeferIndication;
wire LateCollLatched;
wire DeferLatched;
wire RstDeferLatched;
wire CarrierSenseLost;
wire temp_wb_ack_o;
wire [31:0] temp_wb_dat_o;
wire temp_wb_err_o;
`ifdef ETH_REGISTERED_OUTPUTS
reg temp_wb_ack_o_reg;
reg [31:0] temp_wb_dat_o_reg;
reg temp_wb_err_o_reg;
`endif
//assign DWord = &wb_sel_i;
assign ByteSelected = |wb_sel_i;
assign RegCs[3] = wb_stb_i & wb_cyc_i & ByteSelected & ~wb_adr_i[11] & ~wb_adr_i[10] & wb_sel_i[3]; // 0x0 - 0x3FF
assign RegCs[2] = wb_stb_i & wb_cyc_i & ByteSelected & ~wb_adr_i[11] & ~wb_adr_i[10] & wb_sel_i[2]; // 0x0 - 0x3FF
assign RegCs[1] = wb_stb_i & wb_cyc_i & ByteSelected & ~wb_adr_i[11] & ~wb_adr_i[10] & wb_sel_i[1]; // 0x0 - 0x3FF
assign RegCs[0] = wb_stb_i & wb_cyc_i & ByteSelected & ~wb_adr_i[11] & ~wb_adr_i[10] & wb_sel_i[0]; // 0x0 - 0x3FF
assign BDCs[3] = wb_stb_i & wb_cyc_i & ByteSelected & ~wb_adr_i[11] & wb_adr_i[10] & wb_sel_i[3]; // 0x400 - 0x7FF
assign BDCs[2] = wb_stb_i & wb_cyc_i & ByteSelected & ~wb_adr_i[11] & wb_adr_i[10] & wb_sel_i[2]; // 0x400 - 0x7FF
assign BDCs[1] = wb_stb_i & wb_cyc_i & ByteSelected & ~wb_adr_i[11] & wb_adr_i[10] & wb_sel_i[1]; // 0x400 - 0x7FF
assign BDCs[0] = wb_stb_i & wb_cyc_i & ByteSelected & ~wb_adr_i[11] & wb_adr_i[10] & wb_sel_i[0]; // 0x400 - 0x7FF
assign CsMiss = wb_stb_i & wb_cyc_i & ByteSelected & wb_adr_i[11]; // 0x800 - 0xfFF
assign temp_wb_dat_o = ((|RegCs) & ~wb_we_i)? RegDataOut : BD_WB_DAT_O;
assign temp_wb_err_o = wb_stb_i & wb_cyc_i & (~ByteSelected | CsMiss);
`ifdef ETH_REGISTERED_OUTPUTS
assign wb_ack_o = temp_wb_ack_o_reg;
assign wb_dat_o[31:0] = temp_wb_dat_o_reg;
assign wb_err_o = temp_wb_err_o_reg;
`else
assign wb_ack_o = temp_wb_ack_o;
assign wb_dat_o[31:0] = temp_wb_dat_o;
assign wb_err_o = temp_wb_err_o;
`endif
`ifdef ETH_AVALON_BUS
// As Avalon has no corresponding "error" signal, I (erroneously) will
// send an ack to Avalon, even when accessing undefined memory. This
// is a grey area in Avalon vs. Wishbone specs: My understanding
// is that Avalon expects all memory addressable by the addr bus feeding
// a slave to be, at the very minimum, readable.
assign temp_wb_ack_o = (|RegCs) | BDAck | CsMiss;
`else // WISHBONE
assign temp_wb_ack_o = (|RegCs) | BDAck;
`endif
`ifdef ETH_REGISTERED_OUTPUTS
always @ (posedge wb_clk_i or posedge wb_rst_i)
begin
if(wb_rst_i)
begin
temp_wb_ack_o_reg <=#Tp 1'b0;
temp_wb_dat_o_reg <=#Tp 32'h0;
temp_wb_err_o_reg <=#Tp 1'b0;
end
else
begin
temp_wb_ack_o_reg <=#Tp temp_wb_ack_o & ~temp_wb_ack_o_reg;
temp_wb_dat_o_reg <=#Tp temp_wb_dat_o;
temp_wb_err_o_reg <=#Tp temp_wb_err_o & ~temp_wb_err_o_reg;
end
end
`endif
// Connecting Ethernet registers
eth_registers ethreg1
(
.DataIn(wb_dat_i), .Address(wb_adr_i[9:2]), .Rw(wb_we_i),
.Cs(RegCs), .Clk(wb_clk_i), .Reset(wb_rst_i),
.DataOut(RegDataOut), .r_RecSmall(r_RecSmall),
.r_Pad(r_Pad), .r_HugEn(r_HugEn), .r_CrcEn(r_CrcEn),
.r_DlyCrcEn(r_DlyCrcEn), .r_FullD(r_FullD),
.r_ExDfrEn(r_ExDfrEn), .r_NoBckof(r_NoBckof), .r_LoopBck(r_LoopBck),
.r_IFG(r_IFG), .r_Pro(r_Pro), .r_Iam(),
.r_Bro(r_Bro), .r_NoPre(r_NoPre), .r_TxEn(r_TxEn),
.r_RxEn(r_RxEn), .Busy_IRQ(Busy_IRQ), .RxE_IRQ(RxE_IRQ),
.RxB_IRQ(RxB_IRQ), .TxE_IRQ(TxE_IRQ), .TxB_IRQ(TxB_IRQ),
.r_IPGT(r_IPGT),
.r_IPGR1(r_IPGR1), .r_IPGR2(r_IPGR2), .r_MinFL(r_MinFL),
.r_MaxFL(r_MaxFL), .r_MaxRet(r_MaxRet), .r_CollValid(r_CollValid),
.r_TxFlow(r_TxFlow), .r_RxFlow(r_RxFlow), .r_PassAll(r_PassAll),
.r_MiiNoPre(r_MiiNoPre), .r_ClkDiv(r_ClkDiv),
.r_WCtrlData(r_WCtrlData), .r_RStat(r_RStat), .r_ScanStat(r_ScanStat),
.r_RGAD(r_RGAD), .r_FIAD(r_FIAD), .r_CtrlData(r_CtrlData),
.NValid_stat(NValid_stat), .Busy_stat(Busy_stat),
.LinkFail(LinkFail), .r_MAC(r_MAC), .WCtrlDataStart(WCtrlDataStart),
.RStatStart(RStatStart), .UpdateMIIRX_DATAReg(UpdateMIIRX_DATAReg), .Prsd(Prsd),
.r_TxBDNum(r_TxBDNum), .int_o(int_o),
.r_HASH0(r_HASH0), .r_HASH1(r_HASH1), .r_TxPauseRq(r_TxPauseRq),
.r_TxPauseTV(r_TxPauseTV), .RstTxPauseRq(RstTxPauseRq), .TxCtrlEndFrm(TxCtrlEndFrm),
.StartTxDone(StartTxDone), .TxClk(mtx_clk_pad_i), .RxClk(mrx_clk_pad_i),
.SetPauseTimer(SetPauseTimer)
);
wire [7:0] RxData;
wire RxValid;
wire RxStartFrm;
wire RxEndFrm;
wire RxAbort;
wire WillTransmit; // Will transmit (to RxEthMAC)
wire ResetCollision; // Reset Collision (for synchronizing collision)
wire [7:0] TxDataOut; // Transmit Packet Data (to TxEthMAC)
wire WillSendControlFrame;
wire ReceiveEnd;
wire ReceivedPacketGood;
wire ReceivedLengthOK;
wire InvalidSymbol;
wire LatchedCrcError;
wire RxLateCollision;
wire [3:0] RetryCntLatched;
wire [3:0] RetryCnt;
wire StartTxAbort;
wire MaxCollisionOccured;
wire RetryLimit;
wire StatePreamble;
wire [1:0] StateData;
// Connecting MACControl
eth_maccontrol maccontrol1
(
.MTxClk(mtx_clk_pad_i), .TPauseRq(TPauseRq),
.TxPauseTV(r_TxPauseTV), .TxDataIn(TxData),
.TxStartFrmIn(TxStartFrm), .TxEndFrmIn(TxEndFrm),
.TxUsedDataIn(TxUsedDataIn), .TxDoneIn(TxDoneIn),
.TxAbortIn(TxAbortIn), .MRxClk(mrx_clk_pad_i),
.RxData(RxData), .RxValid(RxValid),
.RxStartFrm(RxStartFrm), .RxEndFrm(RxEndFrm),
.ReceiveEnd(ReceiveEnd), .ReceivedPacketGood(ReceivedPacketGood),
.TxFlow(r_TxFlow),
.RxFlow(r_RxFlow), .DlyCrcEn(r_DlyCrcEn),
.MAC(r_MAC), .PadIn(r_Pad | PerPacketPad),
.PadOut(PadOut), .CrcEnIn(r_CrcEn | PerPacketCrcEn),
.CrcEnOut(CrcEnOut), .TxReset(wb_rst_i),
.RxReset(wb_rst_i), .ReceivedLengthOK(ReceivedLengthOK),
.TxDataOut(TxDataOut), .TxStartFrmOut(TxStartFrmOut),
.TxEndFrmOut(TxEndFrmOut), .TxUsedDataOut(TxUsedData),
.TxDoneOut(TxDone), .TxAbortOut(TxAbort),
.WillSendControlFrame(WillSendControlFrame), .TxCtrlEndFrm(TxCtrlEndFrm),
.ReceivedPauseFrm(ReceivedPauseFrm), .ControlFrmAddressOK(ControlFrmAddressOK),
.SetPauseTimer(SetPauseTimer),
.RxStatusWriteLatched_sync2(RxStatusWriteLatched_sync2), .r_PassAll(r_PassAll)
);
wire TxCarrierSense; // Synchronized CarrierSense (to Tx clock)
wire Collision; // Synchronized Collision
reg CarrierSense_Tx1;
reg CarrierSense_Tx2;
reg Collision_Tx1;
reg Collision_Tx2;
reg RxEnSync; // Synchronized Receive Enable
reg WillTransmit_q;
reg WillTransmit_q2;
// Muxed MII receive data valid
assign MRxDV_Lb = r_LoopBck? mtxen_pad_o : mrxdv_pad_i & RxEnSync;
// Muxed MII Receive Error
assign MRxErr_Lb = r_LoopBck? mtxerr_pad_o : mrxerr_pad_i & RxEnSync;
// Muxed MII Receive Data
assign MRxD_Lb[3:0] = r_LoopBck? mtxd_pad_o[3:0] : mrxd_pad_i[3:0];
// Connecting TxEthMAC
eth_txethmac txethmac1
(
.MTxClk(mtx_clk_pad_i), .Reset(wb_rst_i), .CarrierSense(TxCarrierSense),
.Collision(Collision), .TxData(TxDataOut), .TxStartFrm(TxStartFrmOut),
.TxUnderRun(TxUnderRun), .TxEndFrm(TxEndFrmOut), .Pad(PadOut),
.MinFL(r_MinFL), .CrcEn(CrcEnOut), .FullD(r_FullD),
.HugEn(r_HugEn), .DlyCrcEn(r_DlyCrcEn), .IPGT(r_IPGT),
.IPGR1(r_IPGR1), .IPGR2(r_IPGR2), .CollValid(r_CollValid),
.MaxRet(r_MaxRet), .NoBckof(r_NoBckof), .ExDfrEn(r_ExDfrEn),
.MaxFL(r_MaxFL), .MTxEn(mtxen_pad_o), .MTxD(mtxd_pad_o),
.MTxErr(mtxerr_pad_o), .TxUsedData(TxUsedDataIn), .TxDone(TxDoneIn),
.TxRetry(TxRetry), .TxAbort(TxAbortIn), .WillTransmit(WillTransmit),
.ResetCollision(ResetCollision), .RetryCnt(RetryCnt), .StartTxDone(StartTxDone),
.StartTxAbort(StartTxAbort), .MaxCollisionOccured(MaxCollisionOccured), .LateCollision(LateCollision),
.DeferIndication(DeferIndication), .StatePreamble(StatePreamble), .StateData(StateData)
);
wire [15:0] RxByteCnt;
wire RxByteCntEq0;
wire RxByteCntGreat2;
wire RxByteCntMaxFrame;
wire RxCrcError;
wire RxStateIdle;
wire RxStatePreamble;
wire RxStateSFD;
wire [1:0] RxStateData;
wire AddressMiss;
// Connecting RxEthMAC
eth_rxethmac rxethmac1
(
.MRxClk(mrx_clk_pad_i), .MRxDV(MRxDV_Lb), .MRxD(MRxD_Lb),
.Transmitting(Transmitting), .HugEn(r_HugEn), .DlyCrcEn(r_DlyCrcEn),
.MaxFL(r_MaxFL), .r_IFG(r_IFG), .Reset(wb_rst_i),
.RxData(RxData), .RxValid(RxValid), .RxStartFrm(RxStartFrm),
.RxEndFrm(RxEndFrm), .ByteCnt(RxByteCnt),
.ByteCntEq0(RxByteCntEq0), .ByteCntGreat2(RxByteCntGreat2), .ByteCntMaxFrame(RxByteCntMaxFrame),
.CrcError(RxCrcError), .StateIdle(RxStateIdle), .StatePreamble(RxStatePreamble),
.StateSFD(RxStateSFD), .StateData(RxStateData),
.MAC(r_MAC), .r_Pro(r_Pro), .r_Bro(r_Bro),
.r_HASH0(r_HASH0), .r_HASH1(r_HASH1), .RxAbort(RxAbort),
.AddressMiss(AddressMiss), .PassAll(r_PassAll), .ControlFrmAddressOK(ControlFrmAddressOK)
);
// MII Carrier Sense Synchronization
always @ (posedge mtx_clk_pad_i or posedge wb_rst_i)
begin
if(wb_rst_i)
begin
CarrierSense_Tx1 <= #Tp 1'b0;
CarrierSense_Tx2 <= #Tp 1'b0;
end
else
begin
CarrierSense_Tx1 <= #Tp mcrs_pad_i;
CarrierSense_Tx2 <= #Tp CarrierSense_Tx1;
end
end
assign TxCarrierSense = ~r_FullD & CarrierSense_Tx2;
// MII Collision Synchronization
always @ (posedge mtx_clk_pad_i or posedge wb_rst_i)
begin
if(wb_rst_i)
begin
Collision_Tx1 <= #Tp 1'b0;
Collision_Tx2 <= #Tp 1'b0;
end
else
begin
Collision_Tx1 <= #Tp mcoll_pad_i;
if(ResetCollision)
Collision_Tx2 <= #Tp 1'b0;
else
if(Collision_Tx1)
Collision_Tx2 <= #Tp 1'b1;
end
end
// Synchronized Collision
assign Collision = ~r_FullD & Collision_Tx2;
// Delayed WillTransmit
always @ (posedge mrx_clk_pad_i)
begin
WillTransmit_q <= #Tp WillTransmit;
WillTransmit_q2 <= #Tp WillTransmit_q;
end
assign Transmitting = ~r_FullD & WillTransmit_q2;
// Synchronized Receive Enable
always @ (posedge mrx_clk_pad_i or posedge wb_rst_i)
begin
if(wb_rst_i)
RxEnSync <= #Tp 1'b0;
else
if(~mrxdv_pad_i)
RxEnSync <= #Tp r_RxEn;
end
// Synchronizing WillSendControlFrame to WB_CLK;
always @ (posedge wb_clk_i or posedge wb_rst_i)
begin
if(wb_rst_i)
WillSendControlFrame_sync1 <= 1'b0;
else
WillSendControlFrame_sync1 <=#Tp WillSendControlFrame;
end
always @ (posedge wb_clk_i or posedge wb_rst_i)
begin
if(wb_rst_i)
WillSendControlFrame_sync2 <= 1'b0;
else
WillSendControlFrame_sync2 <=#Tp WillSendControlFrame_sync1;
end
always @ (posedge wb_clk_i or posedge wb_rst_i)
begin
if(wb_rst_i)
WillSendControlFrame_sync3 <= 1'b0;
else
WillSendControlFrame_sync3 <=#Tp WillSendControlFrame_sync2;
end
always @ (posedge wb_clk_i or posedge wb_rst_i)
begin
if(wb_rst_i)
RstTxPauseRq <= 1'b0;
else
RstTxPauseRq <=#Tp WillSendControlFrame_sync2 & ~WillSendControlFrame_sync3;
end
// TX Pause request Synchronization
always @ (posedge mtx_clk_pad_i or posedge wb_rst_i)
begin
if(wb_rst_i)
begin
TxPauseRq_sync1 <= #Tp 1'b0;
TxPauseRq_sync2 <= #Tp 1'b0;
TxPauseRq_sync3 <= #Tp 1'b0;
end
else
begin
TxPauseRq_sync1 <= #Tp (r_TxPauseRq & r_TxFlow);
TxPauseRq_sync2 <= #Tp TxPauseRq_sync1;
TxPauseRq_sync3 <= #Tp TxPauseRq_sync2;
end
end
always @ (posedge mtx_clk_pad_i or posedge wb_rst_i)
begin
if(wb_rst_i)
TPauseRq <= #Tp 1'b0;
else
TPauseRq <= #Tp TxPauseRq_sync2 & (~TxPauseRq_sync3);
end
wire LatchedMRxErr;
reg RxAbort_latch;
reg RxAbort_sync1;
reg RxAbort_wb;
reg RxAbortRst_sync1;
reg RxAbortRst;
// Synchronizing RxAbort to the WISHBONE clock
always @ (posedge mrx_clk_pad_i or posedge wb_rst_i)
begin
if(wb_rst_i)
RxAbort_latch <= #Tp 1'b0;
else if(RxAbort | (ShortFrame & ~r_RecSmall) | LatchedMRxErr & ~InvalidSymbol | (ReceivedPauseFrm & (~r_PassAll)))
RxAbort_latch <= #Tp 1'b1;
else if(RxAbortRst)
RxAbort_latch <= #Tp 1'b0;
end
always @ (posedge wb_clk_i or posedge wb_rst_i)
begin
if(wb_rst_i)
begin
RxAbort_sync1 <= #Tp 1'b0;
RxAbort_wb <= #Tp 1'b0;
RxAbort_wb <= #Tp 1'b0;
end
else
begin
RxAbort_sync1 <= #Tp RxAbort_latch;
RxAbort_wb <= #Tp RxAbort_sync1;
end
end
always @ (posedge mrx_clk_pad_i or posedge wb_rst_i)
begin
if(wb_rst_i)
begin
RxAbortRst_sync1 <= #Tp 1'b0;
RxAbortRst <= #Tp 1'b0;
end
else
begin
RxAbortRst_sync1 <= #Tp RxAbort_wb;
RxAbortRst <= #Tp RxAbortRst_sync1;
end
end
// Connecting Wishbone module
eth_wishbone wishbone
(
.WB_CLK_I(wb_clk_i), .WB_DAT_I(wb_dat_i),
.WB_DAT_O(BD_WB_DAT_O),
// WISHBONE slave
.WB_ADR_I(wb_adr_i[9:2]), .WB_WE_I(wb_we_i),
.BDCs(BDCs), .WB_ACK_O(BDAck),
.Reset(wb_rst_i),
// WISHBONE master
.m_wb_adr_o(m_wb_adr_tmp), .m_wb_sel_o(m_wb_sel_o), .m_wb_we_o(m_wb_we_o),
.m_wb_dat_i(m_wb_dat_i), .m_wb_dat_o(m_wb_dat_o), .m_wb_cyc_o(m_wb_cyc_o),
.m_wb_stb_o(m_wb_stb_o), .m_wb_ack_i(m_wb_ack_i), .m_wb_err_i(m_wb_err_i),
`ifdef ETH_WISHBONE_B3
.m_wb_cti_o(m_wb_cti_o), .m_wb_bte_o(m_wb_bte_o),
`endif
//TX
.MTxClk(mtx_clk_pad_i), .TxStartFrm(TxStartFrm), .TxEndFrm(TxEndFrm),
.TxUsedData(TxUsedData), .TxData(TxData),
.TxRetry(TxRetry), .TxAbort(TxAbort), .TxUnderRun(TxUnderRun),
.TxDone(TxDone),
.PerPacketCrcEn(PerPacketCrcEn), .PerPacketPad(PerPacketPad),
// Register
.r_TxEn(r_TxEn), .r_RxEn(r_RxEn), .r_TxBDNum(r_TxBDNum),
.r_RxFlow(r_RxFlow), .r_PassAll(r_PassAll),
//RX
.MRxClk(mrx_clk_pad_i), .RxData(RxData), .RxValid(RxValid),
.RxStartFrm(RxStartFrm), .RxEndFrm(RxEndFrm),
.Busy_IRQ(Busy_IRQ), .RxE_IRQ(RxE_IRQ), .RxB_IRQ(RxB_IRQ),
.TxE_IRQ(TxE_IRQ), .TxB_IRQ(TxB_IRQ),
.RxAbort(RxAbort_wb), .RxStatusWriteLatched_sync2(RxStatusWriteLatched_sync2),
.InvalidSymbol(InvalidSymbol), .LatchedCrcError(LatchedCrcError), .RxLength(RxByteCnt),
.RxLateCollision(RxLateCollision), .ShortFrame(ShortFrame), .DribbleNibble(DribbleNibble),
.ReceivedPacketTooBig(ReceivedPacketTooBig), .LoadRxStatus(LoadRxStatus), .RetryCntLatched(RetryCntLatched),
.RetryLimit(RetryLimit), .LateCollLatched(LateCollLatched), .DeferLatched(DeferLatched),
.RstDeferLatched(RstDeferLatched),
.CarrierSenseLost(CarrierSenseLost),.ReceivedPacketGood(ReceivedPacketGood), .AddressMiss(AddressMiss),
.ReceivedPauseFrm(ReceivedPauseFrm)
`ifdef ETH_BIST
,
.mbist_si_i (mbist_si_i),
.mbist_so_o (mbist_so_o),
.mbist_ctrl_i (mbist_ctrl_i)
`endif
);
assign m_wb_adr_o = {m_wb_adr_tmp, 2'h0};
// Connecting MacStatus module
eth_macstatus macstatus1
(
.MRxClk(mrx_clk_pad_i), .Reset(wb_rst_i),
.ReceiveEnd(ReceiveEnd), .ReceivedPacketGood(ReceivedPacketGood), .ReceivedLengthOK(ReceivedLengthOK),
.RxCrcError(RxCrcError), .MRxErr(MRxErr_Lb), .MRxDV(MRxDV_Lb),
.RxStateSFD(RxStateSFD), .RxStateData(RxStateData), .RxStatePreamble(RxStatePreamble),
.RxStateIdle(RxStateIdle), .Transmitting(Transmitting), .RxByteCnt(RxByteCnt),
.RxByteCntEq0(RxByteCntEq0), .RxByteCntGreat2(RxByteCntGreat2), .RxByteCntMaxFrame(RxByteCntMaxFrame),
.InvalidSymbol(InvalidSymbol),
.MRxD(MRxD_Lb), .LatchedCrcError(LatchedCrcError), .Collision(mcoll_pad_i),
.CollValid(r_CollValid), .RxLateCollision(RxLateCollision), .r_RecSmall(r_RecSmall),
.r_MinFL(r_MinFL), .r_MaxFL(r_MaxFL), .ShortFrame(ShortFrame),
.DribbleNibble(DribbleNibble), .ReceivedPacketTooBig(ReceivedPacketTooBig), .r_HugEn(r_HugEn),
.LoadRxStatus(LoadRxStatus), .RetryCnt(RetryCnt), .StartTxDone(StartTxDone),
.StartTxAbort(StartTxAbort), .RetryCntLatched(RetryCntLatched), .MTxClk(mtx_clk_pad_i),
.MaxCollisionOccured(MaxCollisionOccured), .RetryLimit(RetryLimit), .LateCollision(LateCollision),
.LateCollLatched(LateCollLatched), .DeferIndication(DeferIndication), .DeferLatched(DeferLatched),
.RstDeferLatched(RstDeferLatched),
.TxStartFrm(TxStartFrmOut), .StatePreamble(StatePreamble), .StateData(StateData),
.CarrierSense(CarrierSense_Tx2), .CarrierSenseLost(CarrierSenseLost), .TxUsedData(TxUsedDataIn),
.LatchedMRxErr(LatchedMRxErr), .Loopback(r_LoopBck), .r_FullD(r_FullD)
);
endmodule
|
//////////////////////////////////////////////////////////////////////
//// ////
//// eth_transmitcontrol.v ////
//// ////
//// This file is part of the Ethernet IP core project ////
//// http://www.opencores.org/projects/ethmac/ ////
//// ////
//// Author(s): ////
//// - Igor Mohor ([email protected]) ////
//// ////
//// All additional information is avaliable in the Readme.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: eth_transmitcontrol.v,v $
// Revision 1.6 2002/11/21 00:16:14 mohor
// When TxUsedData and CtrlMux occur at the same time, byte counter needs
// to be incremented by 2. Signal IncrementByteCntBy2 added for that reason.
//
// Revision 1.5 2002/11/19 17:37:32 mohor
// When control frame (PAUSE) was sent, status was written in the
// eth_wishbone module and both TXB and TXC interrupts were set. Fixed.
// Only TXC interrupt is set.
//
// Revision 1.4 2002/01/23 10:28:16 mohor
// Link in the header changed.
//
// Revision 1.3 2001/10/19 08:43:51 mohor
// eth_timescale.v changed to timescale.v This is done because of the
// simulation of the few cores in a one joined project.
//
// Revision 1.2 2001/09/11 14:17:00 mohor
// Few little NCSIM warnings fixed.
//
// Revision 1.1 2001/08/06 14:44:29 mohor
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
// Include files fixed to contain no path.
// File names and module names changed ta have a eth_ prologue in the name.
// File eth_timescale.v is used to define timescale
// All pin names on the top module are changed to contain _I, _O or _OE at the end.
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
// and Mdo_OE. The bidirectional signal must be created on the top level. This
// is done due to the ASIC tools.
//
// Revision 1.1 2001/07/30 21:23:42 mohor
// Directory structure changed. Files checked and joind together.
//
// Revision 1.1 2001/07/03 12:51:54 mohor
// Initial release of the MAC Control module.
//
//
//
//
//
//
`include "timescale.v"
module eth_transmitcontrol (MTxClk, TxReset, TxUsedDataIn, TxUsedDataOut, TxDoneIn, TxAbortIn,
TxStartFrmIn, TPauseRq, TxUsedDataOutDetected, TxFlow, DlyCrcEn,
TxPauseTV, MAC, TxCtrlStartFrm, TxCtrlEndFrm, SendingCtrlFrm, CtrlMux,
ControlData, WillSendControlFrame, BlockTxDone
);
parameter Tp = 1;
input MTxClk;
input TxReset;
input TxUsedDataIn;
input TxUsedDataOut;
input TxDoneIn;
input TxAbortIn;
input TxStartFrmIn;
input TPauseRq;
input TxUsedDataOutDetected;
input TxFlow;
input DlyCrcEn;
input [15:0] TxPauseTV;
input [47:0] MAC;
output TxCtrlStartFrm;
output TxCtrlEndFrm;
output SendingCtrlFrm;
output CtrlMux;
output [7:0] ControlData;
output WillSendControlFrame;
output BlockTxDone;
reg SendingCtrlFrm;
reg CtrlMux;
reg WillSendControlFrame;
reg [3:0] DlyCrcCnt;
reg [5:0] ByteCnt;
reg ControlEnd_q;
reg [7:0] MuxedCtrlData;
reg TxCtrlStartFrm;
reg TxCtrlStartFrm_q;
reg TxCtrlEndFrm;
reg [7:0] ControlData;
reg TxUsedDataIn_q;
reg BlockTxDone;
wire IncrementDlyCrcCnt;
wire ResetByteCnt;
wire IncrementByteCnt;
wire ControlEnd;
wire IncrementByteCntBy2;
wire EnableCnt;
// A command for Sending the control frame is active (latched)
always @ (posedge MTxClk or posedge TxReset)
begin
if(TxReset)
WillSendControlFrame <= #Tp 1'b0;
else
if(TxCtrlEndFrm & CtrlMux)
WillSendControlFrame <= #Tp 1'b0;
else
if(TPauseRq & TxFlow)
WillSendControlFrame <= #Tp 1'b1;
end
// Generation of the transmit control packet start frame
always @ (posedge MTxClk or posedge TxReset)
begin
if(TxReset)
TxCtrlStartFrm <= #Tp 1'b0;
else
if(TxUsedDataIn_q & CtrlMux)
TxCtrlStartFrm <= #Tp 1'b0;
else
if(WillSendControlFrame & ~TxUsedDataOut & (TxDoneIn | TxAbortIn | TxStartFrmIn | (~TxUsedDataOutDetected)))
TxCtrlStartFrm <= #Tp 1'b1;
end
// Generation of the transmit control packet end frame
always @ (posedge MTxClk or posedge TxReset)
begin
if(TxReset)
TxCtrlEndFrm <= #Tp 1'b0;
else
if(ControlEnd | ControlEnd_q)
TxCtrlEndFrm <= #Tp 1'b1;
else
TxCtrlEndFrm <= #Tp 1'b0;
end
// Generation of the multiplexer signal (controls muxes for switching between
// normal and control packets)
always @ (posedge MTxClk or posedge TxReset)
begin
if(TxReset)
CtrlMux <= #Tp 1'b0;
else
if(WillSendControlFrame & ~TxUsedDataOut)
CtrlMux <= #Tp 1'b1;
else
if(TxDoneIn)
CtrlMux <= #Tp 1'b0;
end
// Generation of the Sending Control Frame signal (enables padding and CRC)
always @ (posedge MTxClk or posedge TxReset)
begin
if(TxReset)
SendingCtrlFrm <= #Tp 1'b0;
else
if(WillSendControlFrame & TxCtrlStartFrm)
SendingCtrlFrm <= #Tp 1'b1;
else
if(TxDoneIn)
SendingCtrlFrm <= #Tp 1'b0;
end
always @ (posedge MTxClk or posedge TxReset)
begin
if(TxReset)
TxUsedDataIn_q <= #Tp 1'b0;
else
TxUsedDataIn_q <= #Tp TxUsedDataIn;
end
// Generation of the signal that will block sending the Done signal to the eth_wishbone module
// While sending the control frame
always @ (posedge MTxClk or posedge TxReset)
begin
if(TxReset)
BlockTxDone <= #Tp 1'b0;
else
if(TxCtrlStartFrm)
BlockTxDone <= #Tp 1'b1;
else
if(TxStartFrmIn)
BlockTxDone <= #Tp 1'b0;
end
always @ (posedge MTxClk)
begin
ControlEnd_q <= #Tp ControlEnd;
TxCtrlStartFrm_q <= #Tp TxCtrlStartFrm;
end
assign IncrementDlyCrcCnt = CtrlMux & TxUsedDataIn & ~DlyCrcCnt[2];
// Delayed CRC counter
always @ (posedge MTxClk or posedge TxReset)
begin
if(TxReset)
DlyCrcCnt <= #Tp 4'h0;
else
if(ResetByteCnt)
DlyCrcCnt <= #Tp 4'h0;
else
if(IncrementDlyCrcCnt)
DlyCrcCnt <= #Tp DlyCrcCnt + 1'b1;
end
assign ResetByteCnt = TxReset | (~TxCtrlStartFrm & (TxDoneIn | TxAbortIn));
assign IncrementByteCnt = CtrlMux & (TxCtrlStartFrm & ~TxCtrlStartFrm_q & ~TxUsedDataIn | TxUsedDataIn & ~ControlEnd);
assign IncrementByteCntBy2 = CtrlMux & TxCtrlStartFrm & (~TxCtrlStartFrm_q) & TxUsedDataIn; // When TxUsedDataIn and CtrlMux are set at the same time
assign EnableCnt = (~DlyCrcEn | DlyCrcEn & (&DlyCrcCnt[1:0]));
// Byte counter
always @ (posedge MTxClk or posedge TxReset)
begin
if(TxReset)
ByteCnt <= #Tp 6'h0;
else
if(ResetByteCnt)
ByteCnt <= #Tp 6'h0;
else
if(IncrementByteCntBy2 & EnableCnt)
ByteCnt <= #Tp (ByteCnt[5:0] ) + 2'h2;
else
if(IncrementByteCnt & EnableCnt)
ByteCnt <= #Tp (ByteCnt[5:0] ) + 1'b1;
end
assign ControlEnd = ByteCnt[5:0] == 6'h22;
// Control data generation (goes to the TxEthMAC module)
always @ (ByteCnt or DlyCrcEn or MAC or TxPauseTV or DlyCrcCnt)
begin
case(ByteCnt)
6'h0: if(~DlyCrcEn | DlyCrcEn & (&DlyCrcCnt[1:0]))
MuxedCtrlData[7:0] = 8'h01; // Reserved Multicast Address
else
MuxedCtrlData[7:0] = 8'h0;
6'h2: MuxedCtrlData[7:0] = 8'h80;
6'h4: MuxedCtrlData[7:0] = 8'hC2;
6'h6: MuxedCtrlData[7:0] = 8'h00;
6'h8: MuxedCtrlData[7:0] = 8'h00;
6'hA: MuxedCtrlData[7:0] = 8'h01;
6'hC: MuxedCtrlData[7:0] = MAC[47:40];
6'hE: MuxedCtrlData[7:0] = MAC[39:32];
6'h10: MuxedCtrlData[7:0] = MAC[31:24];
6'h12: MuxedCtrlData[7:0] = MAC[23:16];
6'h14: MuxedCtrlData[7:0] = MAC[15:8];
6'h16: MuxedCtrlData[7:0] = MAC[7:0];
6'h18: MuxedCtrlData[7:0] = 8'h88; // Type/Length
6'h1A: MuxedCtrlData[7:0] = 8'h08;
6'h1C: MuxedCtrlData[7:0] = 8'h00; // Opcode
6'h1E: MuxedCtrlData[7:0] = 8'h01;
6'h20: MuxedCtrlData[7:0] = TxPauseTV[15:8]; // Pause timer value
6'h22: MuxedCtrlData[7:0] = TxPauseTV[7:0];
default: MuxedCtrlData[7:0] = 8'h0;
endcase
end
// Latched Control data
always @ (posedge MTxClk or posedge TxReset)
begin
if(TxReset)
ControlData[7:0] <= #Tp 8'h0;
else
if(~ByteCnt[0])
ControlData[7:0] <= #Tp MuxedCtrlData[7:0];
end
endmodule
|
//////////////////////////////////////////////////////////////////////
//// ////
//// eth_txcounters.v ////
//// ////
//// This file is part of the Ethernet IP core project ////
//// http://www.opencores.org/projects/ethmac/ ////
//// ////
//// Author(s): ////
//// - Igor Mohor ([email protected]) ////
//// - Novan Hartadi ([email protected]) ////
//// - Mahmud Galela ([email protected]) ////
//// ////
//// All additional information is avaliable in the Readme.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: eth_txcounters.v,v $
// Revision 1.6 2005/02/21 11:25:27 igorm
// Delayed CRC fixed.
//
// Revision 1.5 2002/04/22 14:54:14 mohor
// FCS should not be included in NibbleMinFl.
//
// Revision 1.4 2002/01/23 10:28:16 mohor
// Link in the header changed.
//
// Revision 1.3 2001/10/19 08:43:51 mohor
// eth_timescale.v changed to timescale.v This is done because of the
// simulation of the few cores in a one joined project.
//
// Revision 1.2 2001/09/11 14:17:00 mohor
// Few little NCSIM warnings fixed.
//
// Revision 1.1 2001/08/06 14:44:29 mohor
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
// Include files fixed to contain no path.
// File names and module names changed ta have a eth_ prologue in the name.
// File eth_timescale.v is used to define timescale
// All pin names on the top module are changed to contain _I, _O or _OE at the end.
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
// and Mdo_OE. The bidirectional signal must be created on the top level. This
// is done due to the ASIC tools.
//
// Revision 1.1 2001/07/30 21:23:42 mohor
// Directory structure changed. Files checked and joind together.
//
// Revision 1.4 2001/06/27 21:27:45 mohor
// Few typos fixed.
//
// Revision 1.2 2001/06/19 10:38:07 mohor
// Minor changes in header.
//
// Revision 1.1 2001/06/19 10:27:57 mohor
// TxEthMAC initial release.
//
//
//
`include "timescale.v"
module eth_txcounters (StatePreamble, StateIPG, StateData, StatePAD, StateFCS, StateJam,
StateBackOff, StateDefer, StateIdle, StartDefer, StartIPG, StartFCS,
StartJam, StartBackoff, TxStartFrm, MTxClk, Reset, MinFL, MaxFL, HugEn,
ExDfrEn, PacketFinished_q, DlyCrcEn, StateSFD, ByteCnt, NibCnt,
ExcessiveDefer, NibCntEq7, NibCntEq15, MaxFrame, NibbleMinFl, DlyCrcCnt
);
parameter Tp = 1;
input MTxClk; // Tx clock
input Reset; // Reset
input StatePreamble; // Preamble state
input StateIPG; // IPG state
input [1:0] StateData; // Data state
input StatePAD; // PAD state
input StateFCS; // FCS state
input StateJam; // Jam state
input StateBackOff; // Backoff state
input StateDefer; // Defer state
input StateIdle; // Idle state
input StateSFD; // SFD state
input StartDefer; // Defer state will be activated in next clock
input StartIPG; // IPG state will be activated in next clock
input StartFCS; // FCS state will be activated in next clock
input StartJam; // Jam state will be activated in next clock
input StartBackoff; // Backoff state will be activated in next clock
input TxStartFrm; // Tx start frame
input [15:0] MinFL; // Minimum frame length (in bytes)
input [15:0] MaxFL; // Miximum frame length (in bytes)
input HugEn; // Pakets bigger then MaxFL enabled
input ExDfrEn; // Excessive deferral enabled
input PacketFinished_q;
input DlyCrcEn; // Delayed CRC enabled
output [15:0] ByteCnt; // Byte counter
output [15:0] NibCnt; // Nibble counter
output ExcessiveDefer; // Excessive Deferral occuring
output NibCntEq7; // Nibble counter is equal to 7
output NibCntEq15; // Nibble counter is equal to 15
output MaxFrame; // Maximum frame occured
output NibbleMinFl; // Nibble counter is greater than the minimum frame length
output [2:0] DlyCrcCnt; // Delayed CRC Count
wire ExcessiveDeferCnt;
wire ResetNibCnt;
wire IncrementNibCnt;
wire ResetByteCnt;
wire IncrementByteCnt;
wire ByteCntMax;
reg [15:0] NibCnt;
reg [15:0] ByteCnt;
reg [2:0] DlyCrcCnt;
assign IncrementNibCnt = StateIPG | StatePreamble | (|StateData) | StatePAD
| StateFCS | StateJam | StateBackOff | StateDefer & ~ExcessiveDefer & TxStartFrm;
assign ResetNibCnt = StateDefer & ExcessiveDefer & ~TxStartFrm | StatePreamble & NibCntEq15
| StateJam & NibCntEq7 | StateIdle | StartDefer | StartIPG | StartFCS | StartJam;
// Nibble Counter
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
NibCnt <= #Tp 16'h0;
else
begin
if(ResetNibCnt)
NibCnt <= #Tp 16'h0;
else
if(IncrementNibCnt)
NibCnt <= #Tp NibCnt + 1'b1;
end
end
assign NibCntEq7 = &NibCnt[2:0];
assign NibCntEq15 = &NibCnt[3:0];
assign NibbleMinFl = NibCnt >= (((MinFL-3'h4)<<1) -1); // FCS should not be included in NibbleMinFl
assign ExcessiveDeferCnt = NibCnt[13:0] == 16'h17b7;
assign ExcessiveDefer = NibCnt[13:0] == 16'h17b7 & ~ExDfrEn; // 6071 nibbles
assign IncrementByteCnt = StateData[1] & ~ByteCntMax
| StateBackOff & (&NibCnt[6:0])
| (StatePAD | StateFCS) & NibCnt[0] & ~ByteCntMax;
assign ResetByteCnt = StartBackoff | StateIdle & TxStartFrm | PacketFinished_q;
// Transmit Byte Counter
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
ByteCnt[15:0] <= #Tp 16'h0;
else
begin
if(ResetByteCnt)
ByteCnt[15:0] <= #Tp 16'h0;
else
if(IncrementByteCnt)
ByteCnt[15:0] <= #Tp ByteCnt[15:0] + 1'b1;
end
end
assign MaxFrame = ByteCnt[15:0] == MaxFL[15:0] & ~HugEn;
assign ByteCntMax = &ByteCnt[15:0];
// Delayed CRC counter
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
DlyCrcCnt <= #Tp 3'h0;
else
begin
if(StateData[1] & DlyCrcCnt == 3'h4 | StartJam | PacketFinished_q)
DlyCrcCnt <= #Tp 3'h0;
else
if(DlyCrcEn & (StateSFD | StateData[1] & (|DlyCrcCnt[2:0])))
DlyCrcCnt <= #Tp DlyCrcCnt + 1'b1;
end
end
endmodule
|
//////////////////////////////////////////////////////////////////////
//// ////
//// eth_txethmac.v ////
/// ////
//// This file is part of the Ethernet IP core project ////
//// http://www.opencores.org/projects/ethmac/ ////
//// ////
//// Author(s): ////
//// - Igor Mohor ([email protected]) ////
//// - Novan Hartadi ([email protected]) ////
//// - Mahmud Galela ([email protected]) ////
//// ////
//// All additional information is avaliable in the Readme.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: eth_txethmac.v,v $
// Revision 1.9 2005/02/21 11:25:28 igorm
// Delayed CRC fixed.
//
// Revision 1.8 2003/01/30 13:33:24 mohor
// When padding was enabled and crc disabled, frame was not ended correctly.
//
// Revision 1.7 2002/02/26 16:24:01 mohor
// RetryCntLatched was unused and removed from design
//
// Revision 1.6 2002/02/22 12:56:35 mohor
// Retry is not activated when a Tx Underrun occured
//
// Revision 1.5 2002/02/11 09:18:22 mohor
// Tx status is written back to the BD.
//
// Revision 1.4 2002/01/23 10:28:16 mohor
// Link in the header changed.
//
// Revision 1.3 2001/10/19 08:43:51 mohor
// eth_timescale.v changed to timescale.v This is done because of the
// simulation of the few cores in a one joined project.
//
// Revision 1.2 2001/09/11 14:17:00 mohor
// Few little NCSIM warnings fixed.
//
// Revision 1.1 2001/08/06 14:44:29 mohor
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
// Include files fixed to contain no path.
// File names and module names changed ta have a eth_ prologue in the name.
// File eth_timescale.v is used to define timescale
// All pin names on the top module are changed to contain _I, _O or _OE at the end.
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
// and Mdo_OE. The bidirectional signal must be created on the top level. This
// is done due to the ASIC tools.
//
// Revision 1.1 2001/07/30 21:23:42 mohor
// Directory structure changed. Files checked and joind together.
//
// Revision 1.3 2001/06/19 18:16:40 mohor
// TxClk changed to MTxClk (as discribed in the documentation).
// Crc changed so only one file can be used instead of two.
//
// Revision 1.2 2001/06/19 10:38:08 mohor
// Minor changes in header.
//
// Revision 1.1 2001/06/19 10:27:58 mohor
// TxEthMAC initial release.
//
//
//
`include "timescale.v"
module eth_txethmac (MTxClk, Reset, TxStartFrm, TxEndFrm, TxUnderRun, TxData, CarrierSense,
Collision, Pad, CrcEn, FullD, HugEn, DlyCrcEn, MinFL, MaxFL, IPGT,
IPGR1, IPGR2, CollValid, MaxRet, NoBckof, ExDfrEn,
MTxD, MTxEn, MTxErr, TxDone, TxRetry, TxAbort, TxUsedData, WillTransmit,
ResetCollision, RetryCnt, StartTxDone, StartTxAbort, MaxCollisionOccured,
LateCollision, DeferIndication, StatePreamble, StateData
);
parameter Tp = 1;
input MTxClk; // Transmit clock (from PHY)
input Reset; // Reset
input TxStartFrm; // Transmit packet start frame
input TxEndFrm; // Transmit packet end frame
input TxUnderRun; // Transmit packet under-run
input [7:0] TxData; // Transmit packet data byte
input CarrierSense; // Carrier sense (synchronized)
input Collision; // Collision (synchronized)
input Pad; // Pad enable (from register)
input CrcEn; // Crc enable (from register)
input FullD; // Full duplex (from register)
input HugEn; // Huge packets enable (from register)
input DlyCrcEn; // Delayed Crc enabled (from register)
input [15:0] MinFL; // Minimum frame length (from register)
input [15:0] MaxFL; // Maximum frame length (from register)
input [6:0] IPGT; // Back to back transmit inter packet gap parameter (from register)
input [6:0] IPGR1; // Non back to back transmit inter packet gap parameter IPGR1 (from register)
input [6:0] IPGR2; // Non back to back transmit inter packet gap parameter IPGR2 (from register)
input [5:0] CollValid; // Valid collision window (from register)
input [3:0] MaxRet; // Maximum retry number (from register)
input NoBckof; // No backoff (from register)
input ExDfrEn; // Excessive defferal enable (from register)
output [3:0] MTxD; // Transmit nibble (to PHY)
output MTxEn; // Transmit enable (to PHY)
output MTxErr; // Transmit error (to PHY)
output TxDone; // Transmit packet done (to RISC)
output TxRetry; // Transmit packet retry (to RISC)
output TxAbort; // Transmit packet abort (to RISC)
output TxUsedData; // Transmit packet used data (to RISC)
output WillTransmit; // Will transmit (to RxEthMAC)
output ResetCollision; // Reset Collision (for synchronizing collision)
output [3:0] RetryCnt; // Latched Retry Counter for tx status purposes
output StartTxDone;
output StartTxAbort;
output MaxCollisionOccured;
output LateCollision;
output DeferIndication;
output StatePreamble;
output [1:0] StateData;
reg [3:0] MTxD;
reg MTxEn;
reg MTxErr;
reg TxDone;
reg TxRetry;
reg TxAbort;
reg TxUsedData;
reg WillTransmit;
reg ColWindow;
reg StopExcessiveDeferOccured;
reg [3:0] RetryCnt;
reg [3:0] MTxD_d;
reg StatusLatch;
reg PacketFinished_q;
reg PacketFinished;
wire ExcessiveDeferOccured;
wire StartIPG;
wire StartPreamble;
wire [1:0] StartData;
wire StartFCS;
wire StartJam;
wire StartDefer;
wire StartBackoff;
wire StateDefer;
wire StateIPG;
wire StateIdle;
wire StatePAD;
wire StateFCS;
wire StateJam;
wire StateJam_q;
wire StateBackOff;
wire StateSFD;
wire StartTxRetry;
wire UnderRun;
wire TooBig;
wire [31:0] Crc;
wire CrcError;
wire [2:0] DlyCrcCnt;
wire [15:0] NibCnt;
wire NibCntEq7;
wire NibCntEq15;
wire NibbleMinFl;
wire ExcessiveDefer;
wire [15:0] ByteCnt;
wire MaxFrame;
wire RetryMax;
wire RandomEq0;
wire RandomEqByteCnt;
wire PacketFinished_d;
assign ResetCollision = ~(StatePreamble | (|StateData) | StatePAD | StateFCS);
assign ExcessiveDeferOccured = TxStartFrm & StateDefer & ExcessiveDefer & ~StopExcessiveDeferOccured;
assign StartTxDone = ~Collision & (StateFCS & NibCntEq7 | StateData[1] & TxEndFrm & (~Pad | Pad & NibbleMinFl) & ~CrcEn);
assign UnderRun = StateData[0] & TxUnderRun & ~Collision;
assign TooBig = ~Collision & MaxFrame & (StateData[0] & ~TxUnderRun | StateFCS);
// assign StartTxRetry = StartJam & (ColWindow & ~RetryMax);
assign StartTxRetry = StartJam & (ColWindow & ~RetryMax) & ~UnderRun;
assign LateCollision = StartJam & ~ColWindow & ~UnderRun;
assign MaxCollisionOccured = StartJam & ColWindow & RetryMax;
assign StateSFD = StatePreamble & NibCntEq15;
assign StartTxAbort = TooBig | UnderRun | ExcessiveDeferOccured | LateCollision | MaxCollisionOccured;
// StopExcessiveDeferOccured
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
StopExcessiveDeferOccured <= #Tp 1'b0;
else
begin
if(~TxStartFrm)
StopExcessiveDeferOccured <= #Tp 1'b0;
else
if(ExcessiveDeferOccured)
StopExcessiveDeferOccured <= #Tp 1'b1;
end
end
// Collision Window
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
ColWindow <= #Tp 1'b1;
else
begin
if(~Collision & ByteCnt[5:0] == CollValid[5:0] & (StateData[1] | StatePAD & NibCnt[0] | StateFCS & NibCnt[0]))
ColWindow <= #Tp 1'b0;
else
if(StateIdle | StateIPG)
ColWindow <= #Tp 1'b1;
end
end
// Start Window
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
StatusLatch <= #Tp 1'b0;
else
begin
if(~TxStartFrm)
StatusLatch <= #Tp 1'b0;
else
if(ExcessiveDeferOccured | StateIdle)
StatusLatch <= #Tp 1'b1;
end
end
// Transmit packet used data
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
TxUsedData <= #Tp 1'b0;
else
TxUsedData <= #Tp |StartData;
end
// Transmit packet done
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
TxDone <= #Tp 1'b0;
else
begin
if(TxStartFrm & ~StatusLatch)
TxDone <= #Tp 1'b0;
else
if(StartTxDone)
TxDone <= #Tp 1'b1;
end
end
// Transmit packet retry
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
TxRetry <= #Tp 1'b0;
else
begin
if(TxStartFrm & ~StatusLatch)
TxRetry <= #Tp 1'b0;
else
if(StartTxRetry)
TxRetry <= #Tp 1'b1;
end
end
// Transmit packet abort
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
TxAbort <= #Tp 1'b0;
else
begin
if(TxStartFrm & ~StatusLatch & ~ExcessiveDeferOccured)
TxAbort <= #Tp 1'b0;
else
if(StartTxAbort)
TxAbort <= #Tp 1'b1;
end
end
// Retry counter
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
RetryCnt[3:0] <= #Tp 4'h0;
else
begin
if(ExcessiveDeferOccured | UnderRun | TooBig | StartTxDone | TxUnderRun
| StateJam & NibCntEq7 & (~ColWindow | RetryMax))
RetryCnt[3:0] <= #Tp 4'h0;
else
if(StateJam & NibCntEq7 & ColWindow & (RandomEq0 | NoBckof) | StateBackOff & RandomEqByteCnt)
RetryCnt[3:0] <= #Tp RetryCnt[3:0] + 1'b1;
end
end
assign RetryMax = RetryCnt[3:0] == MaxRet[3:0];
// Transmit nibble
always @ (StatePreamble or StateData or StateData or StateFCS or StateJam or StateSFD or TxData or
Crc or NibCntEq15)
begin
if(StateData[0])
MTxD_d[3:0] = TxData[3:0]; // Lower nibble
else
if(StateData[1])
MTxD_d[3:0] = TxData[7:4]; // Higher nibble
else
if(StateFCS)
MTxD_d[3:0] = {~Crc[28], ~Crc[29], ~Crc[30], ~Crc[31]}; // Crc
else
if(StateJam)
MTxD_d[3:0] = 4'h9; // Jam pattern
else
if(StatePreamble)
if(NibCntEq15)
MTxD_d[3:0] = 4'hd; // SFD
else
MTxD_d[3:0] = 4'h5; // Preamble
else
MTxD_d[3:0] = 4'h0;
end
// Transmit Enable
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
MTxEn <= #Tp 1'b0;
else
MTxEn <= #Tp StatePreamble | (|StateData) | StatePAD | StateFCS | StateJam;
end
// Transmit nibble
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
MTxD[3:0] <= #Tp 4'h0;
else
MTxD[3:0] <= #Tp MTxD_d[3:0];
end
// Transmit error
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
MTxErr <= #Tp 1'b0;
else
MTxErr <= #Tp TooBig | UnderRun;
end
// WillTransmit
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
WillTransmit <= #Tp 1'b0;
else
WillTransmit <= #Tp StartPreamble | StatePreamble | (|StateData) | StatePAD | StateFCS | StateJam;
end
assign PacketFinished_d = StartTxDone | TooBig | UnderRun | LateCollision | MaxCollisionOccured | ExcessiveDeferOccured;
// Packet finished
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
begin
PacketFinished <= #Tp 1'b0;
PacketFinished_q <= #Tp 1'b0;
end
else
begin
PacketFinished <= #Tp PacketFinished_d;
PacketFinished_q <= #Tp PacketFinished;
end
end
// Connecting module Counters
eth_txcounters txcounters1 (.StatePreamble(StatePreamble), .StateIPG(StateIPG), .StateData(StateData),
.StatePAD(StatePAD), .StateFCS(StateFCS), .StateJam(StateJam), .StateBackOff(StateBackOff),
.StateDefer(StateDefer), .StateIdle(StateIdle), .StartDefer(StartDefer), .StartIPG(StartIPG),
.StartFCS(StartFCS), .StartJam(StartJam), .TxStartFrm(TxStartFrm), .MTxClk(MTxClk),
.Reset(Reset), .MinFL(MinFL), .MaxFL(MaxFL), .HugEn(HugEn), .ExDfrEn(ExDfrEn),
.PacketFinished_q(PacketFinished_q), .DlyCrcEn(DlyCrcEn), .StartBackoff(StartBackoff),
.StateSFD(StateSFD), .ByteCnt(ByteCnt), .NibCnt(NibCnt), .ExcessiveDefer(ExcessiveDefer),
.NibCntEq7(NibCntEq7), .NibCntEq15(NibCntEq15), .MaxFrame(MaxFrame), .NibbleMinFl(NibbleMinFl),
.DlyCrcCnt(DlyCrcCnt)
);
// Connecting module StateM
eth_txstatem txstatem1 (.MTxClk(MTxClk), .Reset(Reset), .ExcessiveDefer(ExcessiveDefer), .CarrierSense(CarrierSense),
.NibCnt(NibCnt[6:0]), .IPGT(IPGT), .IPGR1(IPGR1), .IPGR2(IPGR2), .FullD(FullD),
.TxStartFrm(TxStartFrm), .TxEndFrm(TxEndFrm), .TxUnderRun(TxUnderRun), .Collision(Collision),
.UnderRun(UnderRun), .StartTxDone(StartTxDone), .TooBig(TooBig), .NibCntEq7(NibCntEq7),
.NibCntEq15(NibCntEq15), .MaxFrame(MaxFrame), .Pad(Pad), .CrcEn(CrcEn),
.NibbleMinFl(NibbleMinFl), .RandomEq0(RandomEq0), .ColWindow(ColWindow), .RetryMax(RetryMax),
.NoBckof(NoBckof), .RandomEqByteCnt(RandomEqByteCnt), .StateIdle(StateIdle),
.StateIPG(StateIPG), .StatePreamble(StatePreamble), .StateData(StateData), .StatePAD(StatePAD),
.StateFCS(StateFCS), .StateJam(StateJam), .StateJam_q(StateJam_q), .StateBackOff(StateBackOff),
.StateDefer(StateDefer), .StartFCS(StartFCS), .StartJam(StartJam), .StartBackoff(StartBackoff),
.StartDefer(StartDefer), .DeferIndication(DeferIndication), .StartPreamble(StartPreamble), .StartData(StartData), .StartIPG(StartIPG)
);
wire Enable_Crc;
wire [3:0] Data_Crc;
wire Initialize_Crc;
assign Enable_Crc = ~StateFCS;
assign Data_Crc[0] = StateData[0]? TxData[3] : StateData[1]? TxData[7] : 1'b0;
assign Data_Crc[1] = StateData[0]? TxData[2] : StateData[1]? TxData[6] : 1'b0;
assign Data_Crc[2] = StateData[0]? TxData[1] : StateData[1]? TxData[5] : 1'b0;
assign Data_Crc[3] = StateData[0]? TxData[0] : StateData[1]? TxData[4] : 1'b0;
assign Initialize_Crc = StateIdle | StatePreamble | (|DlyCrcCnt);
// Connecting module Crc
eth_crc txcrc (.Clk(MTxClk), .Reset(Reset), .Data(Data_Crc), .Enable(Enable_Crc), .Initialize(Initialize_Crc),
.Crc(Crc), .CrcError(CrcError)
);
// Connecting module Random
eth_random random1 (.MTxClk(MTxClk), .Reset(Reset), .StateJam(StateJam), .StateJam_q(StateJam_q), .RetryCnt(RetryCnt),
.NibCnt(NibCnt), .ByteCnt(ByteCnt[9:0]), .RandomEq0(RandomEq0), .RandomEqByteCnt(RandomEqByteCnt));
endmodule
|
//////////////////////////////////////////////////////////////////////
//// ////
//// eth_txstatem.v ////
//// ////
//// This file is part of the Ethernet IP core project ////
//// http://www.opencores.org/projects/ethmac/ ////
//// ////
//// Author(s): ////
//// - Igor Mohor ([email protected]) ////
//// - Novan Hartadi ([email protected]) ////
//// - Mahmud Galela ([email protected]) ////
//// ////
//// All additional information is avaliable in the Readme.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: eth_txstatem.v,v $
// Revision 1.6 2003/01/30 13:29:08 tadejm
// Defer indication changed.
//
// Revision 1.5 2002/10/30 12:54:50 mohor
// State machine goes from idle to the defer state when CarrierSense is 1. FCS (CRC appending) fixed to check the CrcEn bit also when padding is necessery.
//
// Revision 1.4 2002/01/23 10:28:16 mohor
// Link in the header changed.
//
// Revision 1.3 2001/10/19 08:43:51 mohor
// eth_timescale.v changed to timescale.v This is done because of the
// simulation of the few cores in a one joined project.
//
// Revision 1.2 2001/09/11 14:17:00 mohor
// Few little NCSIM warnings fixed.
//
// Revision 1.1 2001/08/06 14:44:29 mohor
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
// Include files fixed to contain no path.
// File names and module names changed ta have a eth_ prologue in the name.
// File eth_timescale.v is used to define timescale
// All pin names on the top module are changed to contain _I, _O or _OE at the end.
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
// and Mdo_OE. The bidirectional signal must be created on the top level. This
// is done due to the ASIC tools.
//
// Revision 1.1 2001/07/30 21:23:42 mohor
// Directory structure changed. Files checked and joind together.
//
// Revision 1.3 2001/06/19 18:16:40 mohor
// TxClk changed to MTxClk (as discribed in the documentation).
// Crc changed so only one file can be used instead of two.
//
// Revision 1.2 2001/06/19 10:38:07 mohor
// Minor changes in header.
//
// Revision 1.1 2001/06/19 10:27:57 mohor
// TxEthMAC initial release.
//
//
//
//
`include "timescale.v"
module eth_txstatem (MTxClk, Reset, ExcessiveDefer, CarrierSense, NibCnt, IPGT, IPGR1,
IPGR2, FullD, TxStartFrm, TxEndFrm, TxUnderRun, Collision, UnderRun,
StartTxDone, TooBig, NibCntEq7, NibCntEq15, MaxFrame, Pad, CrcEn,
NibbleMinFl, RandomEq0, ColWindow, RetryMax, NoBckof, RandomEqByteCnt,
StateIdle, StateIPG, StatePreamble, StateData, StatePAD, StateFCS,
StateJam, StateJam_q, StateBackOff, StateDefer, StartFCS, StartJam,
StartBackoff, StartDefer, DeferIndication, StartPreamble, StartData, StartIPG
);
parameter Tp = 1;
input MTxClk;
input Reset;
input ExcessiveDefer;
input CarrierSense;
input [6:0] NibCnt;
input [6:0] IPGT;
input [6:0] IPGR1;
input [6:0] IPGR2;
input FullD;
input TxStartFrm;
input TxEndFrm;
input TxUnderRun;
input Collision;
input UnderRun;
input StartTxDone;
input TooBig;
input NibCntEq7;
input NibCntEq15;
input MaxFrame;
input Pad;
input CrcEn;
input NibbleMinFl;
input RandomEq0;
input ColWindow;
input RetryMax;
input NoBckof;
input RandomEqByteCnt;
output StateIdle; // Idle state
output StateIPG; // IPG state
output StatePreamble; // Preamble state
output [1:0] StateData; // Data state
output StatePAD; // PAD state
output StateFCS; // FCS state
output StateJam; // Jam state
output StateJam_q; // Delayed Jam state
output StateBackOff; // Backoff state
output StateDefer; // Defer state
output StartFCS; // FCS state will be activated in next clock
output StartJam; // Jam state will be activated in next clock
output StartBackoff; // Backoff state will be activated in next clock
output StartDefer; // Defer state will be activated in next clock
output DeferIndication;
output StartPreamble; // Preamble state will be activated in next clock
output [1:0] StartData; // Data state will be activated in next clock
output StartIPG; // IPG state will be activated in next clock
wire StartIdle; // Idle state will be activated in next clock
wire StartPAD; // PAD state will be activated in next clock
reg StateIdle;
reg StateIPG;
reg StatePreamble;
reg [1:0] StateData;
reg StatePAD;
reg StateFCS;
reg StateJam;
reg StateJam_q;
reg StateBackOff;
reg StateDefer;
reg Rule1;
// Defining the next state
assign StartIPG = StateDefer & ~ExcessiveDefer & ~CarrierSense;
assign StartIdle = StateIPG & (Rule1 & NibCnt[6:0] >= IPGT | ~Rule1 & NibCnt[6:0] >= IPGR2);
assign StartPreamble = StateIdle & TxStartFrm & ~CarrierSense;
assign StartData[0] = ~Collision & (StatePreamble & NibCntEq15 | StateData[1] & ~TxEndFrm);
assign StartData[1] = ~Collision & StateData[0] & ~TxUnderRun & ~MaxFrame;
assign StartPAD = ~Collision & StateData[1] & TxEndFrm & Pad & ~NibbleMinFl;
assign StartFCS = ~Collision & StateData[1] & TxEndFrm & (~Pad | Pad & NibbleMinFl) & CrcEn
| ~Collision & StatePAD & NibbleMinFl & CrcEn;
assign StartJam = (Collision | UnderRun) & ((StatePreamble & NibCntEq15) | (|StateData[1:0]) | StatePAD | StateFCS);
assign StartBackoff = StateJam & ~RandomEq0 & ColWindow & ~RetryMax & NibCntEq7 & ~NoBckof;
assign StartDefer = StateIPG & ~Rule1 & CarrierSense & NibCnt[6:0] <= IPGR1 & NibCnt[6:0] != IPGR2
| StateIdle & CarrierSense
| StateJam & NibCntEq7 & (NoBckof | RandomEq0 | ~ColWindow | RetryMax)
| StateBackOff & (TxUnderRun | RandomEqByteCnt)
| StartTxDone | TooBig;
assign DeferIndication = StateIdle & CarrierSense;
// Tx State Machine
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
begin
StateIPG <= #Tp 1'b0;
StateIdle <= #Tp 1'b0;
StatePreamble <= #Tp 1'b0;
StateData[1:0] <= #Tp 2'b0;
StatePAD <= #Tp 1'b0;
StateFCS <= #Tp 1'b0;
StateJam <= #Tp 1'b0;
StateJam_q <= #Tp 1'b0;
StateBackOff <= #Tp 1'b0;
StateDefer <= #Tp 1'b1;
end
else
begin
StateData[1:0] <= #Tp StartData[1:0];
StateJam_q <= #Tp StateJam;
if(StartDefer | StartIdle)
StateIPG <= #Tp 1'b0;
else
if(StartIPG)
StateIPG <= #Tp 1'b1;
if(StartDefer | StartPreamble)
StateIdle <= #Tp 1'b0;
else
if(StartIdle)
StateIdle <= #Tp 1'b1;
if(StartData[0] | StartJam)
StatePreamble <= #Tp 1'b0;
else
if(StartPreamble)
StatePreamble <= #Tp 1'b1;
if(StartFCS | StartJam)
StatePAD <= #Tp 1'b0;
else
if(StartPAD)
StatePAD <= #Tp 1'b1;
if(StartJam | StartDefer)
StateFCS <= #Tp 1'b0;
else
if(StartFCS)
StateFCS <= #Tp 1'b1;
if(StartBackoff | StartDefer)
StateJam <= #Tp 1'b0;
else
if(StartJam)
StateJam <= #Tp 1'b1;
if(StartDefer)
StateBackOff <= #Tp 1'b0;
else
if(StartBackoff)
StateBackOff <= #Tp 1'b1;
if(StartIPG)
StateDefer <= #Tp 1'b0;
else
if(StartDefer)
StateDefer <= #Tp 1'b1;
end
end
// This sections defines which interpack gap rule to use
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
Rule1 <= #Tp 1'b0;
else
begin
if(StateIdle | StateBackOff)
Rule1 <= #Tp 1'b0;
else
if(StatePreamble | FullD)
Rule1 <= #Tp 1'b1;
end
end
endmodule
|
//////////////////////////////////////////////////////////////////////
//// ////
//// eth_wishbone.v ////
//// ////
//// This file is part of the Ethernet IP core project ////
//// http://www.opencores.org/projects/ethmac/ ////
//// ////
//// Author(s): ////
//// - Igor Mohor ([email protected]) ////
//// ////
//// All additional information is available in the Readme.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001, 2002 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: eth_wishbone.v,v $
// Revision 1.58 2005/03/21 20:07:18 igorm
// Some small fixes + some troubles fixed.
//
// Revision 1.57 2005/02/21 11:35:33 igorm
// Defer indication fixed.
//
// Revision 1.56 2004/04/30 10:30:00 igorm
// Accidently deleted line put back.
//
// Revision 1.55 2004/04/26 15:26:23 igorm
// - Bug connected to the TX_BD_NUM_Wr signal fixed (bug came in with the
// previous update of the core.
// - TxBDAddress is set to 0 after the TX is enabled in the MODER register.
// - RxBDAddress is set to r_TxBDNum<<1 after the RX is enabled in the MODER
// register. (thanks to Mathias and Torbjorn)
// - Multicast reception was fixed. Thanks to Ulrich Gries
//
// Revision 1.54 2003/11/12 18:24:59 tadejm
// WISHBONE slave changed and tested from only 32-bit accesss to byte access.
//
// Revision 1.53 2003/10/17 07:46:17 markom
// mbist signals updated according to newest convention
//
// Revision 1.52 2003/01/30 14:51:31 mohor
// Reset has priority in some flipflops.
//
// Revision 1.51 2003/01/30 13:36:22 mohor
// A new bug (entered with previous update) fixed. When abort occured sometimes
// data transmission was blocked.
//
// Revision 1.50 2003/01/22 13:49:26 tadejm
// When control packets were received, they were ignored in some cases.
//
// Revision 1.49 2003/01/21 12:09:40 mohor
// When receiving normal data frame and RxFlow control was switched on, RXB
// interrupt was not set.
//
// Revision 1.48 2003/01/20 12:05:26 mohor
// When in full duplex, transmit was sometimes blocked. Fixed.
//
// Revision 1.47 2002/11/22 13:26:21 mohor
// Registers RxStatusWrite_rck and RxStatusWriteLatched were not used
// anywhere. Removed.
//
// Revision 1.46 2002/11/22 01:57:06 mohor
// Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort
// synchronized.
//
// Revision 1.45 2002/11/19 17:33:34 mohor
// AddressMiss status is connecting to the Rx BD. AddressMiss is identifying
// that a frame was received because of the promiscous mode.
//
// Revision 1.44 2002/11/13 22:21:40 tadejm
// RxError is not generated when small frame reception is enabled and small
// frames are received.
//
// Revision 1.43 2002/10/18 20:53:34 mohor
// case changed to casex.
//
// Revision 1.42 2002/10/18 17:04:20 tadejm
// Changed BIST scan signals.
//
// Revision 1.41 2002/10/18 15:42:09 tadejm
// Igor added WB burst support and repaired BUG when handling TX under-run and retry.
//
// Revision 1.40 2002/10/14 16:07:02 mohor
// TxStatus is written after last access to the TX fifo is finished (in case of abort
// or retry). TxDone is fixed.
//
// Revision 1.39 2002/10/11 15:35:20 mohor
// txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v file,
// TxDone and TxRetry are generated after the current WISHBONE access is
// finished.
//
// Revision 1.38 2002/10/10 16:29:30 mohor
// BIST added.
//
// Revision 1.37 2002/09/11 14:18:46 mohor
// Sometimes both RxB_IRQ and RxE_IRQ were activated. Bug fixed.
//
// Revision 1.36 2002/09/10 13:48:46 mohor
// Reception is possible after RxPointer is read and not after BD is read. For
// that reason RxBDReady is changed to RxReady.
// Busy_IRQ interrupt connected. When there is no RxBD ready and frame
// comes, interrupt is generated.
//
// Revision 1.35 2002/09/10 10:35:23 mohor
// Ethernet debug registers removed.
//
// Revision 1.34 2002/09/08 16:31:49 mohor
// Async reset for WB_ACK_O removed (when core was in reset, it was
// impossible to access BDs).
// RxPointers and TxPointers names changed to be more descriptive.
// TxUnderRun synchronized.
//
// Revision 1.33 2002/09/04 18:47:57 mohor
// Debug registers reg1, 2, 3, 4 connected. Synchronization of many signals
// changed (bugs fixed). Access to un-alligned buffers fixed. RxAbort signal
// was not used OK.
//
// Revision 1.32 2002/08/14 19:31:48 mohor
// Register TX_BD_NUM is changed so it contains value of the Tx buffer descriptors. No
// need to multiply or devide any more.
//
// Revision 1.31 2002/07/25 18:29:01 mohor
// WriteRxDataToMemory signal changed so end of frame (when last word is
// written to fifo) is changed.
//
// Revision 1.30 2002/07/23 15:28:31 mohor
// Ram , used for BDs changed from generic_spram to eth_spram_256x32.
//
// Revision 1.29 2002/07/20 00:41:32 mohor
// ShiftEnded synchronization changed.
//
// Revision 1.28 2002/07/18 16:11:46 mohor
// RxBDAddress takes `ETH_TX_BD_NUM_DEF value after reset.
//
// Revision 1.27 2002/07/11 02:53:20 mohor
// RxPointer bug fixed.
//
// Revision 1.26 2002/07/10 13:12:38 mohor
// Previous bug wasn't succesfully removed. Now fixed.
//
// Revision 1.25 2002/07/09 23:53:24 mohor
// Master state machine had a bug when switching from master write to
// master read.
//
// Revision 1.24 2002/07/09 20:44:41 mohor
// m_wb_cyc_o signal released after every single transfer.
//
// Revision 1.23 2002/05/03 10:15:50 mohor
// Outputs registered. Reset changed for eth_wishbone module.
//
// Revision 1.22 2002/04/24 08:52:19 mohor
// Compiler directives added. Tx and Rx fifo size incremented. A "late collision"
// bug fixed.
//
// Revision 1.21 2002/03/29 16:18:11 lampret
// Small typo fixed.
//
// Revision 1.20 2002/03/25 16:19:12 mohor
// Any address can be used for Tx and Rx BD pointers. Address does not need
// to be aligned.
//
// Revision 1.19 2002/03/19 12:51:50 mohor
// Comments in Slovene language removed.
//
// Revision 1.18 2002/03/19 12:46:52 mohor
// casex changed with case, fifo reset changed.
//
// Revision 1.17 2002/03/09 16:08:45 mohor
// rx_fifo was not always cleared ok. Fixed.
//
// Revision 1.16 2002/03/09 13:51:20 mohor
// Status was not latched correctly sometimes. Fixed.
//
// Revision 1.15 2002/03/08 06:56:46 mohor
// Big Endian problem when sending frames fixed.
//
// Revision 1.14 2002/03/02 19:12:40 mohor
// Byte ordering changed (Big Endian used). casex changed with case because
// Xilinx Foundation had problems. Tested in HW. It WORKS.
//
// Revision 1.13 2002/02/26 16:59:55 mohor
// Small fixes for external/internal DMA missmatches.
//
// Revision 1.12 2002/02/26 16:22:07 mohor
// Interrupts changed
//
// Revision 1.11 2002/02/15 17:07:39 mohor
// Status was not written correctly when frames were discarted because of
// address mismatch.
//
// Revision 1.10 2002/02/15 12:17:39 mohor
// RxStartFrm cleared when abort or retry comes.
//
// Revision 1.9 2002/02/15 11:59:10 mohor
// Changes that were lost when updating from 1.5 to 1.8 fixed.
//
// Revision 1.8 2002/02/14 20:54:33 billditt
// Addition of new module eth_addrcheck.v
//
// Revision 1.7 2002/02/12 17:03:47 mohor
// RxOverRun added to statuses.
//
// Revision 1.6 2002/02/11 09:18:22 mohor
// Tx status is written back to the BD.
//
// Revision 1.5 2002/02/08 16:21:54 mohor
// Rx status is written back to the BD.
//
// Revision 1.4 2002/02/06 14:10:21 mohor
// non-DMA host interface added. Select the right configutation in eth_defines.
//
// Revision 1.3 2002/02/05 16:44:39 mohor
// Both rx and tx part are finished. Tested with wb_clk_i between 10 and 200
// MHz. Statuses, overrun, control frame transmission and reception still need
// to be fixed.
//
// Revision 1.2 2002/02/01 12:46:51 mohor
// Tx part finished. TxStatus needs to be fixed. Pause request needs to be
// added.
//
// Revision 1.1 2002/01/23 10:47:59 mohor
// Initial version. Equals to eth_wishbonedma.v at this moment.
//
//
//
`include "eth_defines.v"
`include "timescale.v"
module eth_wishbone
(
// WISHBONE common
WB_CLK_I, WB_DAT_I, WB_DAT_O,
// WISHBONE slave
WB_ADR_I, WB_WE_I, WB_ACK_O,
BDCs,
Reset,
// WISHBONE master
m_wb_adr_o, m_wb_sel_o, m_wb_we_o,
m_wb_dat_o, m_wb_dat_i, m_wb_cyc_o,
m_wb_stb_o, m_wb_ack_i, m_wb_err_i,
`ifdef ETH_WISHBONE_B3
m_wb_cti_o, m_wb_bte_o,
`endif
//TX
MTxClk, TxStartFrm, TxEndFrm, TxUsedData, TxData,
TxRetry, TxAbort, TxUnderRun, TxDone, PerPacketCrcEn,
PerPacketPad,
//RX
MRxClk, RxData, RxValid, RxStartFrm, RxEndFrm, RxAbort, RxStatusWriteLatched_sync2,
// Register
r_TxEn, r_RxEn, r_TxBDNum, r_RxFlow, r_PassAll,
// Interrupts
TxB_IRQ, TxE_IRQ, RxB_IRQ, RxE_IRQ, Busy_IRQ,
// Rx Status
InvalidSymbol, LatchedCrcError, RxLateCollision, ShortFrame, DribbleNibble,
ReceivedPacketTooBig, RxLength, LoadRxStatus, ReceivedPacketGood, AddressMiss,
ReceivedPauseFrm,
// Tx Status
RetryCntLatched, RetryLimit, LateCollLatched, DeferLatched, RstDeferLatched, CarrierSenseLost
// Bist
`ifdef ETH_BIST
,
// debug chain signals
mbist_si_i, // bist scan serial in
mbist_so_o, // bist scan serial out
mbist_ctrl_i // bist chain shift control
`endif
);
parameter Tp = 1;
// WISHBONE common
input WB_CLK_I; // WISHBONE clock
input [31:0] WB_DAT_I; // WISHBONE data input
output [31:0] WB_DAT_O; // WISHBONE data output
// WISHBONE slave
input [9:2] WB_ADR_I; // WISHBONE address input
input WB_WE_I; // WISHBONE write enable input
input [3:0] BDCs; // Buffer descriptors are selected
output WB_ACK_O; // WISHBONE acknowledge output
// WISHBONE master
output [29:0] m_wb_adr_o; //
output [3:0] m_wb_sel_o; //
output m_wb_we_o; //
output [31:0] m_wb_dat_o; //
output m_wb_cyc_o; //
output m_wb_stb_o; //
input [31:0] m_wb_dat_i; //
input m_wb_ack_i; //
input m_wb_err_i; //
`ifdef ETH_WISHBONE_B3
output [2:0] m_wb_cti_o; // Cycle Type Identifier
output [1:0] m_wb_bte_o; // Burst Type Extension
reg [2:0] m_wb_cti_o; // Cycle Type Identifier
`endif
input Reset; // Reset signal
// Rx Status signals
input InvalidSymbol; // Invalid symbol was received during reception in 100 Mbps mode
input LatchedCrcError; // CRC error
input RxLateCollision; // Late collision occured while receiving frame
input ShortFrame; // Frame shorter then the minimum size (r_MinFL) was received while small packets are enabled (r_RecSmall)
input DribbleNibble; // Extra nibble received
input ReceivedPacketTooBig;// Received packet is bigger than r_MaxFL
input [15:0] RxLength; // Length of the incoming frame
input LoadRxStatus; // Rx status was loaded
input ReceivedPacketGood;// Received packet's length and CRC are good
input AddressMiss; // When a packet is received AddressMiss status is written to the Rx BD
input r_RxFlow;
input r_PassAll;
input ReceivedPauseFrm;
// Tx Status signals
input [3:0] RetryCntLatched; // Latched Retry Counter
input RetryLimit; // Retry limit reached (Retry Max value + 1 attempts were made)
input LateCollLatched; // Late collision occured
input DeferLatched; // Defer indication (Frame was defered before sucessfully sent)
output RstDeferLatched;
input CarrierSenseLost; // Carrier Sense was lost during the frame transmission
// Tx
input MTxClk; // Transmit clock (from PHY)
input TxUsedData; // Transmit packet used data
input TxRetry; // Transmit packet retry
input TxAbort; // Transmit packet abort
input TxDone; // Transmission ended
output TxStartFrm; // Transmit packet start frame
output TxEndFrm; // Transmit packet end frame
output [7:0] TxData; // Transmit packet data byte
output TxUnderRun; // Transmit packet under-run
output PerPacketCrcEn; // Per packet crc enable
output PerPacketPad; // Per packet pading
// Rx
input MRxClk; // Receive clock (from PHY)
input [7:0] RxData; // Received data byte (from PHY)
input RxValid; //
input RxStartFrm; //
input RxEndFrm; //
input RxAbort; // This signal is set when address doesn't match.
output RxStatusWriteLatched_sync2;
//Register
input r_TxEn; // Transmit enable
input r_RxEn; // Receive enable
input [7:0] r_TxBDNum; // Receive buffer descriptor number
// Interrupts
output TxB_IRQ;
output TxE_IRQ;
output RxB_IRQ;
output RxE_IRQ;
output Busy_IRQ;
// Bist
`ifdef ETH_BIST
input mbist_si_i; // bist scan serial in
output mbist_so_o; // bist scan serial out
input [`ETH_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i; // bist chain shift control
`endif
reg TxB_IRQ;
reg TxE_IRQ;
reg RxB_IRQ;
reg RxE_IRQ;
reg TxStartFrm;
reg TxEndFrm;
reg [7:0] TxData;
reg TxUnderRun;
reg TxUnderRun_wb;
reg TxBDRead;
wire TxStatusWrite;
reg [1:0] TxValidBytesLatched;
reg [15:0] TxLength;
reg [15:0] LatchedTxLength;
reg [14:11] TxStatus;
reg [14:13] RxStatus;
reg TxStartFrm_wb;
reg TxRetry_wb;
reg TxAbort_wb;
reg TxDone_wb;
reg TxDone_wb_q;
reg TxAbort_wb_q;
reg TxRetry_wb_q;
reg TxRetryPacket;
reg TxRetryPacket_NotCleared;
reg TxDonePacket;
reg TxDonePacket_NotCleared;
reg TxAbortPacket;
reg TxAbortPacket_NotCleared;
reg RxBDReady;
reg RxReady;
reg TxBDReady;
reg RxBDRead;
reg [31:0] TxDataLatched;
reg [1:0] TxByteCnt;
reg LastWord;
reg ReadTxDataFromFifo_tck;
reg BlockingTxStatusWrite;
reg BlockingTxBDRead;
reg Flop;
reg [7:1] TxBDAddress;
reg [7:1] RxBDAddress;
reg TxRetrySync1;
reg TxAbortSync1;
reg TxDoneSync1;
reg TxAbort_q;
reg TxRetry_q;
reg TxUsedData_q;
reg [31:0] RxDataLatched2;
reg [31:8] RxDataLatched1; // Big Endian Byte Ordering
reg [1:0] RxValidBytes;
reg [1:0] RxByteCnt;
reg LastByteIn;
reg ShiftWillEnd;
reg WriteRxDataToFifo;
reg [15:0] LatchedRxLength;
reg RxAbortLatched;
reg ShiftEnded;
reg RxOverrun;
reg [3:0] BDWrite; // BD Write Enable for access from WISHBONE side
reg BDRead; // BD Read access from WISHBONE side
wire [31:0] RxBDDataIn; // Rx BD data in
wire [31:0] TxBDDataIn; // Tx BD data in
reg TxEndFrm_wb;
wire TxRetryPulse;
wire TxDonePulse;
wire TxAbortPulse;
wire StartRxBDRead;
wire StartTxBDRead;
wire TxIRQEn;
wire WrapTxStatusBit;
wire RxIRQEn;
wire WrapRxStatusBit;
wire [1:0] TxValidBytes;
wire [7:1] TempTxBDAddress;
wire [7:1] TempRxBDAddress;
wire RxStatusWrite;
wire RxBufferFull;
wire RxBufferAlmostEmpty;
wire RxBufferEmpty;
reg WB_ACK_O;
wire [8:0] RxStatusIn;
reg [8:0] RxStatusInLatched;
reg WbEn, WbEn_q;
reg RxEn, RxEn_q;
reg TxEn, TxEn_q;
reg r_TxEn_q;
reg r_RxEn_q;
wire ram_ce;
wire [3:0] ram_we;
wire ram_oe;
reg [7:0] ram_addr;
reg [31:0] ram_di;
wire [31:0] ram_do;
wire StartTxPointerRead;
reg TxPointerRead;
reg TxEn_needed;
reg RxEn_needed;
wire StartRxPointerRead;
reg RxPointerRead;
`ifdef ETH_WISHBONE_B3
assign m_wb_bte_o = 2'b00; // Linear burst
`endif
assign m_wb_stb_o = m_wb_cyc_o;
always @ (posedge WB_CLK_I)
begin
WB_ACK_O <=#Tp (|BDWrite) & WbEn & WbEn_q | BDRead & WbEn & ~WbEn_q;
end
assign WB_DAT_O = ram_do;
// Generic synchronous single-port RAM interface
eth_spram_256x32 bd_ram (
.clk(WB_CLK_I), .rst(Reset), .ce(ram_ce), .we(ram_we), .oe(ram_oe), .addr(ram_addr), .di(ram_di), .do(ram_do)
`ifdef ETH_BIST
,
.mbist_si_i (mbist_si_i),
.mbist_so_o (mbist_so_o),
.mbist_ctrl_i (mbist_ctrl_i)
`endif
);
assign ram_ce = 1'b1;
assign ram_we = (BDWrite & {4{(WbEn & WbEn_q)}}) | {4{(TxStatusWrite | RxStatusWrite)}};
assign ram_oe = BDRead & WbEn & WbEn_q | TxEn & TxEn_q & (TxBDRead | TxPointerRead) | RxEn & RxEn_q & (RxBDRead | RxPointerRead);
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
TxEn_needed <=#Tp 1'b0;
else
if(~TxBDReady & r_TxEn & WbEn & ~WbEn_q)
TxEn_needed <=#Tp 1'b1;
else
if(TxPointerRead & TxEn & TxEn_q)
TxEn_needed <=#Tp 1'b0;
end
// Enabling access to the RAM for three devices.
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
begin
WbEn <=#Tp 1'b1;
RxEn <=#Tp 1'b0;
TxEn <=#Tp 1'b0;
ram_addr <=#Tp 8'h0;
ram_di <=#Tp 32'h0;
BDRead <=#Tp 1'b0;
BDWrite <=#Tp 1'b0;
end
else
begin
// Switching between three stages depends on enable signals
case ({WbEn_q, RxEn_q, TxEn_q, RxEn_needed, TxEn_needed}) // synopsys parallel_case
5'b100_10, 5'b100_11 :
begin
WbEn <=#Tp 1'b0;
RxEn <=#Tp 1'b1; // wb access stage and r_RxEn is enabled
TxEn <=#Tp 1'b0;
ram_addr <=#Tp {RxBDAddress, RxPointerRead};
ram_di <=#Tp RxBDDataIn;
end
5'b100_01 :
begin
WbEn <=#Tp 1'b0;
RxEn <=#Tp 1'b0;
TxEn <=#Tp 1'b1; // wb access stage, r_RxEn is disabled but r_TxEn is enabled
ram_addr <=#Tp {TxBDAddress, TxPointerRead};
ram_di <=#Tp TxBDDataIn;
end
5'b010_00, 5'b010_10 :
begin
WbEn <=#Tp 1'b1; // RxEn access stage and r_TxEn is disabled
RxEn <=#Tp 1'b0;
TxEn <=#Tp 1'b0;
ram_addr <=#Tp WB_ADR_I[9:2];
ram_di <=#Tp WB_DAT_I;
BDWrite <=#Tp BDCs[3:0] & {4{WB_WE_I}};
BDRead <=#Tp (|BDCs) & ~WB_WE_I;
end
5'b010_01, 5'b010_11 :
begin
WbEn <=#Tp 1'b0;
RxEn <=#Tp 1'b0;
TxEn <=#Tp 1'b1; // RxEn access stage and r_TxEn is enabled
ram_addr <=#Tp {TxBDAddress, TxPointerRead};
ram_di <=#Tp TxBDDataIn;
end
5'b001_00, 5'b001_01, 5'b001_10, 5'b001_11 :
begin
WbEn <=#Tp 1'b1; // TxEn access stage (we always go to wb access stage)
RxEn <=#Tp 1'b0;
TxEn <=#Tp 1'b0;
ram_addr <=#Tp WB_ADR_I[9:2];
ram_di <=#Tp WB_DAT_I;
BDWrite <=#Tp BDCs[3:0] & {4{WB_WE_I}};
BDRead <=#Tp (|BDCs) & ~WB_WE_I;
end
5'b100_00 :
begin
WbEn <=#Tp 1'b0; // WbEn access stage and there is no need for other stages. WbEn needs to be switched off for a bit
end
5'b000_00 :
begin
WbEn <=#Tp 1'b1; // Idle state. We go to WbEn access stage.
RxEn <=#Tp 1'b0;
TxEn <=#Tp 1'b0;
ram_addr <=#Tp WB_ADR_I[9:2];
ram_di <=#Tp WB_DAT_I;
BDWrite <=#Tp BDCs[3:0] & {4{WB_WE_I}};
BDRead <=#Tp (|BDCs) & ~WB_WE_I;
end
endcase
end
end
// Delayed stage signals
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
begin
WbEn_q <=#Tp 1'b0;
RxEn_q <=#Tp 1'b0;
TxEn_q <=#Tp 1'b0;
r_TxEn_q <=#Tp 1'b0;
r_RxEn_q <=#Tp 1'b0;
end
else
begin
WbEn_q <=#Tp WbEn;
RxEn_q <=#Tp RxEn;
TxEn_q <=#Tp TxEn;
r_TxEn_q <=#Tp r_TxEn;
r_RxEn_q <=#Tp r_RxEn;
end
end
// Changes for tx occur every second clock. Flop is used for this manner.
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
Flop <=#Tp 1'b0;
else
if(TxDone | TxAbort | TxRetry_q)
Flop <=#Tp 1'b0;
else
if(TxUsedData)
Flop <=#Tp ~Flop;
end
wire ResetTxBDReady;
assign ResetTxBDReady = TxDonePulse | TxAbortPulse | TxRetryPulse;
// Latching READY status of the Tx buffer descriptor
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
TxBDReady <=#Tp 1'b0;
else
if(TxEn & TxEn_q & TxBDRead)
TxBDReady <=#Tp ram_do[15] & (ram_do[31:16] > 4); // TxBDReady is sampled only once at the beginning.
else // Only packets larger then 4 bytes are transmitted.
if(ResetTxBDReady)
TxBDReady <=#Tp 1'b0;
end
// Reading the Tx buffer descriptor
assign StartTxBDRead = (TxRetryPacket_NotCleared | TxStatusWrite) & ~BlockingTxBDRead & ~TxBDReady;
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
TxBDRead <=#Tp 1'b1;
else
if(StartTxBDRead)
TxBDRead <=#Tp 1'b1;
else
if(TxBDReady)
TxBDRead <=#Tp 1'b0;
end
// Reading Tx BD pointer
assign StartTxPointerRead = TxBDRead & TxBDReady;
// Reading Tx BD Pointer
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
TxPointerRead <=#Tp 1'b0;
else
if(StartTxPointerRead)
TxPointerRead <=#Tp 1'b1;
else
if(TxEn_q)
TxPointerRead <=#Tp 1'b0;
end
// Writing status back to the Tx buffer descriptor
assign TxStatusWrite = (TxDonePacket_NotCleared | TxAbortPacket_NotCleared) & TxEn & TxEn_q & ~BlockingTxStatusWrite;
// Status writing must occur only once. Meanwhile it is blocked.
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
BlockingTxStatusWrite <=#Tp 1'b0;
else
if(~TxDone_wb & ~TxAbort_wb)
BlockingTxStatusWrite <=#Tp 1'b0;
else
if(TxStatusWrite)
BlockingTxStatusWrite <=#Tp 1'b1;
end
reg BlockingTxStatusWrite_sync1;
reg BlockingTxStatusWrite_sync2;
reg BlockingTxStatusWrite_sync3;
// Synchronizing BlockingTxStatusWrite to MTxClk
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
BlockingTxStatusWrite_sync1 <=#Tp 1'b0;
else
BlockingTxStatusWrite_sync1 <=#Tp BlockingTxStatusWrite;
end
// Synchronizing BlockingTxStatusWrite to MTxClk
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
BlockingTxStatusWrite_sync2 <=#Tp 1'b0;
else
BlockingTxStatusWrite_sync2 <=#Tp BlockingTxStatusWrite_sync1;
end
// Synchronizing BlockingTxStatusWrite to MTxClk
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
BlockingTxStatusWrite_sync3 <=#Tp 1'b0;
else
BlockingTxStatusWrite_sync3 <=#Tp BlockingTxStatusWrite_sync2;
end
assign RstDeferLatched = BlockingTxStatusWrite_sync2 & ~BlockingTxStatusWrite_sync3;
// TxBDRead state is activated only once.
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
BlockingTxBDRead <=#Tp 1'b0;
else
if(StartTxBDRead)
BlockingTxBDRead <=#Tp 1'b1;
else
if(~StartTxBDRead & ~TxBDReady)
BlockingTxBDRead <=#Tp 1'b0;
end
// Latching status from the tx buffer descriptor
// Data is avaliable one cycle after the access is started (at that time signal TxEn is not active)
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
TxStatus <=#Tp 4'h0;
else
if(TxEn & TxEn_q & TxBDRead)
TxStatus <=#Tp ram_do[14:11];
end
reg ReadTxDataFromMemory;
wire WriteRxDataToMemory;
reg MasterWbTX;
reg MasterWbRX;
reg [29:0] m_wb_adr_o;
reg m_wb_cyc_o;
reg [3:0] m_wb_sel_o;
reg m_wb_we_o;
wire TxLengthEq0;
wire TxLengthLt4;
reg BlockingIncrementTxPointer;
reg [31:2] TxPointerMSB;
reg [1:0] TxPointerLSB;
reg [1:0] TxPointerLSB_rst;
reg [31:2] RxPointerMSB;
reg [1:0] RxPointerLSB_rst;
wire RxBurstAcc;
wire RxWordAcc;
wire RxHalfAcc;
wire RxByteAcc;
//Latching length from the buffer descriptor;
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
TxLength <=#Tp 16'h0;
else
if(TxEn & TxEn_q & TxBDRead)
TxLength <=#Tp ram_do[31:16];
else
if(MasterWbTX & m_wb_ack_i)
begin
if(TxLengthLt4)
TxLength <=#Tp 16'h0;
else
if(TxPointerLSB_rst==2'h0)
TxLength <=#Tp TxLength - 3'h4; // Length is subtracted at the data request
else
if(TxPointerLSB_rst==2'h1)
TxLength <=#Tp TxLength - 3'h3; // Length is subtracted at the data request
else
if(TxPointerLSB_rst==2'h2)
TxLength <=#Tp TxLength - 3'h2; // Length is subtracted at the data request
else
if(TxPointerLSB_rst==2'h3)
TxLength <=#Tp TxLength - 3'h1; // Length is subtracted at the data request
end
end
//Latching length from the buffer descriptor;
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
LatchedTxLength <=#Tp 16'h0;
else
if(TxEn & TxEn_q & TxBDRead)
LatchedTxLength <=#Tp ram_do[31:16];
end
assign TxLengthEq0 = TxLength == 0;
assign TxLengthLt4 = TxLength < 4;
reg cyc_cleared;
reg IncrTxPointer;
// Latching Tx buffer pointer from buffer descriptor. Only 30 MSB bits are latched
// because TxPointerMSB is only used for word-aligned accesses.
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
TxPointerMSB <=#Tp 30'h0;
else
if(TxEn & TxEn_q & TxPointerRead)
TxPointerMSB <=#Tp ram_do[31:2];
else
if(IncrTxPointer & ~BlockingIncrementTxPointer)
TxPointerMSB <=#Tp TxPointerMSB + 1'b1; // TxPointer is word-aligned
end
// Latching 2 MSB bits of the buffer descriptor. Since word accesses are performed,
// valid data does not necesserly start at byte 0 (could be byte 0, 1, 2 or 3). This
// signals are used for proper selection of the start byte (TxData and TxByteCnt) are
// set by this two bits.
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
TxPointerLSB[1:0] <=#Tp 0;
else
if(TxEn & TxEn_q & TxPointerRead)
TxPointerLSB[1:0] <=#Tp ram_do[1:0];
end
// Latching 2 MSB bits of the buffer descriptor.
// After the read access, TxLength needs to be decremented for the number of the valid
// bytes (1 to 4 bytes are valid in the first word). After the first read all bytes are
// valid so this two bits are reset to zero.
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
TxPointerLSB_rst[1:0] <=#Tp 0;
else
if(TxEn & TxEn_q & TxPointerRead)
TxPointerLSB_rst[1:0] <=#Tp ram_do[1:0];
else
if(MasterWbTX & m_wb_ack_i) // After first access pointer is word alligned
TxPointerLSB_rst[1:0] <=#Tp 0;
end
reg [3:0] RxByteSel;
wire MasterAccessFinished;
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
BlockingIncrementTxPointer <=#Tp 0;
else
if(MasterAccessFinished)
BlockingIncrementTxPointer <=#Tp 0;
else
if(IncrTxPointer)
BlockingIncrementTxPointer <=#Tp 1'b1;
end
wire TxBufferAlmostFull;
wire TxBufferFull;
wire TxBufferEmpty;
wire TxBufferAlmostEmpty;
wire SetReadTxDataFromMemory;
reg BlockReadTxDataFromMemory;
assign SetReadTxDataFromMemory = TxEn & TxEn_q & TxPointerRead;
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
ReadTxDataFromMemory <=#Tp 1'b0;
else
if(TxLengthEq0 | TxAbortPulse | TxRetryPulse)
ReadTxDataFromMemory <=#Tp 1'b0;
else
if(SetReadTxDataFromMemory)
ReadTxDataFromMemory <=#Tp 1'b1;
end
reg tx_burst_en;
reg rx_burst_en;
wire ReadTxDataFromMemory_2 = ReadTxDataFromMemory & ~BlockReadTxDataFromMemory;
wire tx_burst = ReadTxDataFromMemory_2 & tx_burst_en;
wire [31:0] TxData_wb;
wire ReadTxDataFromFifo_wb;
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
BlockReadTxDataFromMemory <=#Tp 1'b0;
else
if((TxBufferAlmostFull | TxLength <= 4)& MasterWbTX & (~cyc_cleared) & (!(TxAbortPacket_NotCleared | TxRetryPacket_NotCleared)))
BlockReadTxDataFromMemory <=#Tp 1'b1;
else
if(ReadTxDataFromFifo_wb | TxDonePacket | TxAbortPacket | TxRetryPacket)
BlockReadTxDataFromMemory <=#Tp 1'b0;
end
assign MasterAccessFinished = m_wb_ack_i | m_wb_err_i;
wire [`ETH_TX_FIFO_CNT_WIDTH-1:0] txfifo_cnt;
wire [`ETH_RX_FIFO_CNT_WIDTH-1:0] rxfifo_cnt;
reg [`ETH_BURST_CNT_WIDTH-1:0] tx_burst_cnt;
reg [`ETH_BURST_CNT_WIDTH-1:0] rx_burst_cnt;
wire rx_burst;
wire enough_data_in_rxfifo_for_burst;
wire enough_data_in_rxfifo_for_burst_plus1;
// Enabling master wishbone access to the memory for two devices TX and RX.
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
begin
MasterWbTX <=#Tp 1'b0;
MasterWbRX <=#Tp 1'b0;
m_wb_adr_o <=#Tp 30'h0;
m_wb_cyc_o <=#Tp 1'b0;
m_wb_we_o <=#Tp 1'b0;
m_wb_sel_o <=#Tp 4'h0;
cyc_cleared<=#Tp 1'b0;
tx_burst_cnt<=#Tp 0;
rx_burst_cnt<=#Tp 0;
IncrTxPointer<=#Tp 1'b0;
tx_burst_en<=#Tp 1'b1;
rx_burst_en<=#Tp 1'b0;
`ifdef ETH_WISHBONE_B3
m_wb_cti_o <=#Tp 3'b0;
`endif
end
else
begin
// Switching between two stages depends on enable signals
casex ({MasterWbTX, MasterWbRX, ReadTxDataFromMemory_2, WriteRxDataToMemory, MasterAccessFinished, cyc_cleared, tx_burst, rx_burst}) // synopsys parallel_case
8'b00_10_00_10, // Idle and MRB needed
8'b10_1x_10_1x, // MRB continues
8'b10_10_01_10, // Clear (previously MR) and MRB needed
8'b01_1x_01_1x : // Clear (previously MW) and MRB needed
begin
MasterWbTX <=#Tp 1'b1; // tx burst
MasterWbRX <=#Tp 1'b0;
m_wb_cyc_o <=#Tp 1'b1;
m_wb_we_o <=#Tp 1'b0;
m_wb_sel_o <=#Tp 4'hf;
cyc_cleared<=#Tp 1'b0;
IncrTxPointer<=#Tp 1'b1;
tx_burst_cnt <=#Tp tx_burst_cnt+3'h1;
if(tx_burst_cnt==0)
m_wb_adr_o <=#Tp TxPointerMSB;
else
m_wb_adr_o <=#Tp m_wb_adr_o+1'b1;
if(tx_burst_cnt==(`ETH_BURST_LENGTH-1))
begin
tx_burst_en<=#Tp 1'b0;
`ifdef ETH_WISHBONE_B3
m_wb_cti_o <=#Tp 3'b111;
`endif
end
else
begin
`ifdef ETH_WISHBONE_B3
m_wb_cti_o <=#Tp 3'b010;
`endif
end
end
8'b00_x1_00_x1, // Idle and MWB needed
8'b01_x1_10_x1, // MWB continues
8'b01_01_01_01, // Clear (previously MW) and MWB needed
8'b10_x1_01_x1 : // Clear (previously MR) and MWB needed
begin
MasterWbTX <=#Tp 1'b0; // rx burst
MasterWbRX <=#Tp 1'b1;
m_wb_cyc_o <=#Tp 1'b1;
m_wb_we_o <=#Tp 1'b1;
m_wb_sel_o <=#Tp RxByteSel;
IncrTxPointer<=#Tp 1'b0;
cyc_cleared<=#Tp 1'b0;
rx_burst_cnt <=#Tp rx_burst_cnt+3'h1;
if(rx_burst_cnt==0)
m_wb_adr_o <=#Tp RxPointerMSB;
else
m_wb_adr_o <=#Tp m_wb_adr_o+1'b1;
if(rx_burst_cnt==(`ETH_BURST_LENGTH-1))
begin
rx_burst_en<=#Tp 1'b0;
`ifdef ETH_WISHBONE_B3
m_wb_cti_o <=#Tp 3'b111;
`endif
end
else
begin
`ifdef ETH_WISHBONE_B3
m_wb_cti_o <=#Tp 3'b010;
`endif
end
end
8'b00_x1_00_x0 : // idle and MW is needed (data write to rx buffer)
begin
MasterWbTX <=#Tp 1'b0;
MasterWbRX <=#Tp 1'b1;
m_wb_adr_o <=#Tp RxPointerMSB;
m_wb_cyc_o <=#Tp 1'b1;
m_wb_we_o <=#Tp 1'b1;
m_wb_sel_o <=#Tp RxByteSel;
IncrTxPointer<=#Tp 1'b0;
end
8'b00_10_00_00 : // idle and MR is needed (data read from tx buffer)
begin
MasterWbTX <=#Tp 1'b1;
MasterWbRX <=#Tp 1'b0;
m_wb_adr_o <=#Tp TxPointerMSB;
m_wb_cyc_o <=#Tp 1'b1;
m_wb_we_o <=#Tp 1'b0;
m_wb_sel_o <=#Tp 4'hf;
IncrTxPointer<=#Tp 1'b1;
end
8'b10_10_01_00, // MR and MR is needed (data read from tx buffer)
8'b01_1x_01_0x : // MW and MR is needed (data read from tx buffer)
begin
MasterWbTX <=#Tp 1'b1;
MasterWbRX <=#Tp 1'b0;
m_wb_adr_o <=#Tp TxPointerMSB;
m_wb_cyc_o <=#Tp 1'b1;
m_wb_we_o <=#Tp 1'b0;
m_wb_sel_o <=#Tp 4'hf;
cyc_cleared<=#Tp 1'b0;
IncrTxPointer<=#Tp 1'b1;
end
8'b01_01_01_00, // MW and MW needed (data write to rx buffer)
8'b10_x1_01_x0 : // MR and MW is needed (data write to rx buffer)
begin
MasterWbTX <=#Tp 1'b0;
MasterWbRX <=#Tp 1'b1;
m_wb_adr_o <=#Tp RxPointerMSB;
m_wb_cyc_o <=#Tp 1'b1;
m_wb_we_o <=#Tp 1'b1;
m_wb_sel_o <=#Tp RxByteSel;
cyc_cleared<=#Tp 1'b0;
IncrTxPointer<=#Tp 1'b0;
end
8'b01_01_10_00, // MW and MW needed (cycle is cleared between previous and next access)
8'b01_1x_10_x0, // MW and MW or MR or MRB needed (cycle is cleared between previous and next access)
8'b10_10_10_00, // MR and MR needed (cycle is cleared between previous and next access)
8'b10_x1_10_0x : // MR and MR or MW or MWB (cycle is cleared between previous and next access)
begin
m_wb_cyc_o <=#Tp 1'b0; // whatever and master read or write is needed. We need to clear m_wb_cyc_o before next access is started
cyc_cleared<=#Tp 1'b1;
IncrTxPointer<=#Tp 1'b0;
tx_burst_cnt<=#Tp 0;
tx_burst_en<=#Tp txfifo_cnt<(`ETH_TX_FIFO_DEPTH-`ETH_BURST_LENGTH) & (TxLength>(`ETH_BURST_LENGTH*4+4));
rx_burst_cnt<=#Tp 0;
rx_burst_en<=#Tp MasterWbRX ? enough_data_in_rxfifo_for_burst_plus1 : enough_data_in_rxfifo_for_burst; // Counter is not decremented, yet, so plus1 is used.
`ifdef ETH_WISHBONE_B3
m_wb_cti_o <=#Tp 3'b0;
`endif
end
8'bxx_00_10_00, // whatever and no master read or write is needed (ack or err comes finishing previous access)
8'bxx_00_01_00 : // Between cyc_cleared request was cleared
begin
MasterWbTX <=#Tp 1'b0;
MasterWbRX <=#Tp 1'b0;
m_wb_cyc_o <=#Tp 1'b0;
cyc_cleared<=#Tp 1'b0;
IncrTxPointer<=#Tp 1'b0;
rx_burst_cnt<=#Tp 0;
rx_burst_en<=#Tp MasterWbRX ? enough_data_in_rxfifo_for_burst_plus1 : enough_data_in_rxfifo_for_burst; // Counter is not decremented, yet, so plus1 is used.
`ifdef ETH_WISHBONE_B3
m_wb_cti_o <=#Tp 3'b0;
`endif
end
8'b00_00_00_00: // whatever and no master read or write is needed (ack or err comes finishing previous access)
begin
tx_burst_cnt<=#Tp 0;
tx_burst_en<=#Tp txfifo_cnt<(`ETH_TX_FIFO_DEPTH-`ETH_BURST_LENGTH) & (TxLength>(`ETH_BURST_LENGTH*4+4));
end
default: // Don't touch
begin
MasterWbTX <=#Tp MasterWbTX;
MasterWbRX <=#Tp MasterWbRX;
m_wb_cyc_o <=#Tp m_wb_cyc_o;
m_wb_sel_o <=#Tp m_wb_sel_o;
IncrTxPointer<=#Tp IncrTxPointer;
end
endcase
end
end
wire TxFifoClear;
assign TxFifoClear = (TxAbortPacket | TxRetryPacket);
eth_fifo #(`ETH_TX_FIFO_DATA_WIDTH, `ETH_TX_FIFO_DEPTH, `ETH_TX_FIFO_CNT_WIDTH)
tx_fifo ( .data_in(m_wb_dat_i), .data_out(TxData_wb),
.clk(WB_CLK_I), .reset(Reset),
.write(MasterWbTX & m_wb_ack_i), .read(ReadTxDataFromFifo_wb & ~TxBufferEmpty),
.clear(TxFifoClear), .full(TxBufferFull),
.almost_full(TxBufferAlmostFull), .almost_empty(TxBufferAlmostEmpty),
.empty(TxBufferEmpty), .cnt(txfifo_cnt)
);
reg StartOccured;
reg TxStartFrm_sync1;
reg TxStartFrm_sync2;
reg TxStartFrm_syncb1;
reg TxStartFrm_syncb2;
// Start: Generation of the TxStartFrm_wb which is then synchronized to the MTxClk
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
TxStartFrm_wb <=#Tp 1'b0;
else
if(TxBDReady & ~StartOccured & (TxBufferFull | TxLengthEq0))
TxStartFrm_wb <=#Tp 1'b1;
else
if(TxStartFrm_syncb2)
TxStartFrm_wb <=#Tp 1'b0;
end
// StartOccured: TxStartFrm_wb occurs only ones at the beginning. Then it's blocked.
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
StartOccured <=#Tp 1'b0;
else
if(TxStartFrm_wb)
StartOccured <=#Tp 1'b1;
else
if(ResetTxBDReady)
StartOccured <=#Tp 1'b0;
end
// Synchronizing TxStartFrm_wb to MTxClk
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
TxStartFrm_sync1 <=#Tp 1'b0;
else
TxStartFrm_sync1 <=#Tp TxStartFrm_wb;
end
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
TxStartFrm_sync2 <=#Tp 1'b0;
else
TxStartFrm_sync2 <=#Tp TxStartFrm_sync1;
end
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
TxStartFrm_syncb1 <=#Tp 1'b0;
else
TxStartFrm_syncb1 <=#Tp TxStartFrm_sync2;
end
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
TxStartFrm_syncb2 <=#Tp 1'b0;
else
TxStartFrm_syncb2 <=#Tp TxStartFrm_syncb1;
end
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
TxStartFrm <=#Tp 1'b0;
else
if(TxStartFrm_sync2)
TxStartFrm <=#Tp 1'b1;
else
if(TxUsedData_q | ~TxStartFrm_sync2 & (TxRetry & (~TxRetry_q) | TxAbort & (~TxAbort_q)))
TxStartFrm <=#Tp 1'b0;
end
// End: Generation of the TxStartFrm_wb which is then synchronized to the MTxClk
// TxEndFrm_wb: indicator of the end of frame
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
TxEndFrm_wb <=#Tp 1'b0;
else
if(TxLengthEq0 & TxBufferAlmostEmpty & TxUsedData)
TxEndFrm_wb <=#Tp 1'b1;
else
if(TxRetryPulse | TxDonePulse | TxAbortPulse)
TxEndFrm_wb <=#Tp 1'b0;
end
// Marks which bytes are valid within the word.
assign TxValidBytes = TxLengthLt4 ? TxLength[1:0] : 2'b0;
reg LatchValidBytes;
reg LatchValidBytes_q;
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
LatchValidBytes <=#Tp 1'b0;
else
if(TxLengthLt4 & TxBDReady)
LatchValidBytes <=#Tp 1'b1;
else
LatchValidBytes <=#Tp 1'b0;
end
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
LatchValidBytes_q <=#Tp 1'b0;
else
LatchValidBytes_q <=#Tp LatchValidBytes;
end
// Latching valid bytes
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
TxValidBytesLatched <=#Tp 2'h0;
else
if(LatchValidBytes & ~LatchValidBytes_q)
TxValidBytesLatched <=#Tp TxValidBytes;
else
if(TxRetryPulse | TxDonePulse | TxAbortPulse)
TxValidBytesLatched <=#Tp 2'h0;
end
assign TxIRQEn = TxStatus[14];
assign WrapTxStatusBit = TxStatus[13];
assign PerPacketPad = TxStatus[12];
assign PerPacketCrcEn = TxStatus[11];
assign RxIRQEn = RxStatus[14];
assign WrapRxStatusBit = RxStatus[13];
// Temporary Tx and Rx buffer descriptor address
assign TempTxBDAddress[7:1] = {7{ TxStatusWrite & ~WrapTxStatusBit}} & (TxBDAddress + 1'b1) ; // Tx BD increment or wrap (last BD)
assign TempRxBDAddress[7:1] = {7{ WrapRxStatusBit}} & (r_TxBDNum[6:0]) | // Using first Rx BD
{7{~WrapRxStatusBit}} & (RxBDAddress + 1'b1) ; // Using next Rx BD (incremenrement address)
// Latching Tx buffer descriptor address
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
TxBDAddress <=#Tp 7'h0;
else if (r_TxEn & (~r_TxEn_q))
TxBDAddress <=#Tp 7'h0;
else if (TxStatusWrite)
TxBDAddress <=#Tp TempTxBDAddress;
end
// Latching Rx buffer descriptor address
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
RxBDAddress <=#Tp 7'h0;
else if(r_RxEn & (~r_RxEn_q))
RxBDAddress <=#Tp r_TxBDNum[6:0];
else if(RxStatusWrite)
RxBDAddress <=#Tp TempRxBDAddress;
end
wire [8:0] TxStatusInLatched = {TxUnderRun, RetryCntLatched[3:0], RetryLimit, LateCollLatched, DeferLatched, CarrierSenseLost};
assign RxBDDataIn = {LatchedRxLength, 1'b0, RxStatus, 4'h0, RxStatusInLatched};
assign TxBDDataIn = {LatchedTxLength, 1'b0, TxStatus, 2'h0, TxStatusInLatched};
// Signals used for various purposes
assign TxRetryPulse = TxRetry_wb & ~TxRetry_wb_q;
assign TxDonePulse = TxDone_wb & ~TxDone_wb_q;
assign TxAbortPulse = TxAbort_wb & ~TxAbort_wb_q;
// Generating delayed signals
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
begin
TxAbort_q <=#Tp 1'b0;
TxRetry_q <=#Tp 1'b0;
TxUsedData_q <=#Tp 1'b0;
end
else
begin
TxAbort_q <=#Tp TxAbort;
TxRetry_q <=#Tp TxRetry;
TxUsedData_q <=#Tp TxUsedData;
end
end
// Generating delayed signals
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
begin
TxDone_wb_q <=#Tp 1'b0;
TxAbort_wb_q <=#Tp 1'b0;
TxRetry_wb_q <=#Tp 1'b0;
end
else
begin
TxDone_wb_q <=#Tp TxDone_wb;
TxAbort_wb_q <=#Tp TxAbort_wb;
TxRetry_wb_q <=#Tp TxRetry_wb;
end
end
reg TxAbortPacketBlocked;
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
TxAbortPacket <=#Tp 1'b0;
else
if(TxAbort_wb & (~tx_burst_en) & MasterWbTX & MasterAccessFinished & (~TxAbortPacketBlocked) |
TxAbort_wb & (~MasterWbTX) & (~TxAbortPacketBlocked))
TxAbortPacket <=#Tp 1'b1;
else
TxAbortPacket <=#Tp 1'b0;
end
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
TxAbortPacket_NotCleared <=#Tp 1'b0;
else
if(TxEn & TxEn_q & TxAbortPacket_NotCleared)
TxAbortPacket_NotCleared <=#Tp 1'b0;
else
if(TxAbort_wb & (~tx_burst_en) & MasterWbTX & MasterAccessFinished & (~TxAbortPacketBlocked) |
TxAbort_wb & (~MasterWbTX) & (~TxAbortPacketBlocked))
TxAbortPacket_NotCleared <=#Tp 1'b1;
end
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
TxAbortPacketBlocked <=#Tp 1'b0;
else
if(!TxAbort_wb & TxAbort_wb_q)
TxAbortPacketBlocked <=#Tp 1'b0;
else
if(TxAbortPacket)
TxAbortPacketBlocked <=#Tp 1'b1;
end
reg TxRetryPacketBlocked;
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
TxRetryPacket <=#Tp 1'b0;
else
if(TxRetry_wb & !tx_burst_en & MasterWbTX & MasterAccessFinished & !TxRetryPacketBlocked |
TxRetry_wb & !MasterWbTX & !TxRetryPacketBlocked)
TxRetryPacket <=#Tp 1'b1;
else
TxRetryPacket <=#Tp 1'b0;
end
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
TxRetryPacket_NotCleared <=#Tp 1'b0;
else
if(StartTxBDRead)
TxRetryPacket_NotCleared <=#Tp 1'b0;
else
if(TxRetry_wb & !tx_burst_en & MasterWbTX & MasterAccessFinished & !TxRetryPacketBlocked |
TxRetry_wb & !MasterWbTX & !TxRetryPacketBlocked)
TxRetryPacket_NotCleared <=#Tp 1'b1;
end
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
TxRetryPacketBlocked <=#Tp 1'b0;
else
if(!TxRetry_wb & TxRetry_wb_q)
TxRetryPacketBlocked <=#Tp 1'b0;
else
if(TxRetryPacket)
TxRetryPacketBlocked <=#Tp 1'b1;
end
reg TxDonePacketBlocked;
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
TxDonePacket <=#Tp 1'b0;
else
if(TxDone_wb & !tx_burst_en & MasterWbTX & MasterAccessFinished & !TxDonePacketBlocked |
TxDone_wb & !MasterWbTX & !TxDonePacketBlocked)
TxDonePacket <=#Tp 1'b1;
else
TxDonePacket <=#Tp 1'b0;
end
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
TxDonePacket_NotCleared <=#Tp 1'b0;
else
if(TxEn & TxEn_q & TxDonePacket_NotCleared)
TxDonePacket_NotCleared <=#Tp 1'b0;
else
if(TxDone_wb & !tx_burst_en & MasterWbTX & MasterAccessFinished & (~TxDonePacketBlocked) |
TxDone_wb & !MasterWbTX & (~TxDonePacketBlocked))
TxDonePacket_NotCleared <=#Tp 1'b1;
end
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
TxDonePacketBlocked <=#Tp 1'b0;
else
if(!TxDone_wb & TxDone_wb_q)
TxDonePacketBlocked <=#Tp 1'b0;
else
if(TxDonePacket)
TxDonePacketBlocked <=#Tp 1'b1;
end
// Indication of the last word
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
LastWord <=#Tp 1'b0;
else
if((TxEndFrm | TxAbort | TxRetry) & Flop)
LastWord <=#Tp 1'b0;
else
if(TxUsedData & Flop & TxByteCnt == 2'h3)
LastWord <=#Tp TxEndFrm_wb;
end
// Tx end frame generation
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
TxEndFrm <=#Tp 1'b0;
else
if(Flop & TxEndFrm | TxAbort | TxRetry_q)
TxEndFrm <=#Tp 1'b0;
else
if(Flop & LastWord)
begin
case (TxValidBytesLatched) // synopsys parallel_case
1 : TxEndFrm <=#Tp TxByteCnt == 2'h0;
2 : TxEndFrm <=#Tp TxByteCnt == 2'h1;
3 : TxEndFrm <=#Tp TxByteCnt == 2'h2;
0 : TxEndFrm <=#Tp TxByteCnt == 2'h3;
default : TxEndFrm <=#Tp 1'b0;
endcase
end
end
// Tx data selection (latching)
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
TxData <=#Tp 0;
else
if(TxStartFrm_sync2 & ~TxStartFrm)
case(TxPointerLSB) // synopsys parallel_case
2'h0 : TxData <=#Tp TxData_wb[31:24]; // Big Endian Byte Ordering
2'h1 : TxData <=#Tp TxData_wb[23:16]; // Big Endian Byte Ordering
2'h2 : TxData <=#Tp TxData_wb[15:08]; // Big Endian Byte Ordering
2'h3 : TxData <=#Tp TxData_wb[07:00]; // Big Endian Byte Ordering
endcase
else
if(TxStartFrm & TxUsedData & TxPointerLSB==2'h3)
TxData <=#Tp TxData_wb[31:24]; // Big Endian Byte Ordering
else
if(TxUsedData & Flop)
begin
case(TxByteCnt) // synopsys parallel_case
0 : TxData <=#Tp TxDataLatched[31:24]; // Big Endian Byte Ordering
1 : TxData <=#Tp TxDataLatched[23:16];
2 : TxData <=#Tp TxDataLatched[15:8];
3 : TxData <=#Tp TxDataLatched[7:0];
endcase
end
end
// Latching tx data
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
TxDataLatched[31:0] <=#Tp 32'h0;
else
if(TxStartFrm_sync2 & ~TxStartFrm | TxUsedData & Flop & TxByteCnt == 2'h3 | TxStartFrm & TxUsedData & Flop & TxByteCnt == 2'h0)
TxDataLatched[31:0] <=#Tp TxData_wb[31:0];
end
// Tx under run
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
TxUnderRun_wb <=#Tp 1'b0;
else
if(TxAbortPulse)
TxUnderRun_wb <=#Tp 1'b0;
else
if(TxBufferEmpty & ReadTxDataFromFifo_wb)
TxUnderRun_wb <=#Tp 1'b1;
end
reg TxUnderRun_sync1;
// Tx under run
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
TxUnderRun_sync1 <=#Tp 1'b0;
else
if(TxUnderRun_wb)
TxUnderRun_sync1 <=#Tp 1'b1;
else
if(BlockingTxStatusWrite_sync2)
TxUnderRun_sync1 <=#Tp 1'b0;
end
// Tx under run
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
TxUnderRun <=#Tp 1'b0;
else
if(BlockingTxStatusWrite_sync2)
TxUnderRun <=#Tp 1'b0;
else
if(TxUnderRun_sync1)
TxUnderRun <=#Tp 1'b1;
end
// Tx Byte counter
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
TxByteCnt <=#Tp 2'h0;
else
if(TxAbort_q | TxRetry_q)
TxByteCnt <=#Tp 2'h0;
else
if(TxStartFrm & ~TxUsedData)
case(TxPointerLSB) // synopsys parallel_case
2'h0 : TxByteCnt <=#Tp 2'h1;
2'h1 : TxByteCnt <=#Tp 2'h2;
2'h2 : TxByteCnt <=#Tp 2'h3;
2'h3 : TxByteCnt <=#Tp 2'h0;
endcase
else
if(TxUsedData & Flop)
TxByteCnt <=#Tp TxByteCnt + 1'b1;
end
// Start: Generation of the ReadTxDataFromFifo_tck signal and synchronization to the WB_CLK_I
reg ReadTxDataFromFifo_sync1;
reg ReadTxDataFromFifo_sync2;
reg ReadTxDataFromFifo_sync3;
reg ReadTxDataFromFifo_syncb1;
reg ReadTxDataFromFifo_syncb2;
reg ReadTxDataFromFifo_syncb3;
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
ReadTxDataFromFifo_tck <=#Tp 1'b0;
else
if(TxStartFrm_sync2 & ~TxStartFrm | TxUsedData & Flop & TxByteCnt == 2'h3 & ~LastWord | TxStartFrm & TxUsedData & Flop & TxByteCnt == 2'h0)
ReadTxDataFromFifo_tck <=#Tp 1'b1;
else
if(ReadTxDataFromFifo_syncb2 & ~ReadTxDataFromFifo_syncb3)
ReadTxDataFromFifo_tck <=#Tp 1'b0;
end
// Synchronizing TxStartFrm_wb to MTxClk
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
ReadTxDataFromFifo_sync1 <=#Tp 1'b0;
else
ReadTxDataFromFifo_sync1 <=#Tp ReadTxDataFromFifo_tck;
end
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
ReadTxDataFromFifo_sync2 <=#Tp 1'b0;
else
ReadTxDataFromFifo_sync2 <=#Tp ReadTxDataFromFifo_sync1;
end
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
ReadTxDataFromFifo_syncb1 <=#Tp 1'b0;
else
ReadTxDataFromFifo_syncb1 <=#Tp ReadTxDataFromFifo_sync2;
end
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
ReadTxDataFromFifo_syncb2 <=#Tp 1'b0;
else
ReadTxDataFromFifo_syncb2 <=#Tp ReadTxDataFromFifo_syncb1;
end
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
ReadTxDataFromFifo_syncb3 <=#Tp 1'b0;
else
ReadTxDataFromFifo_syncb3 <=#Tp ReadTxDataFromFifo_syncb2;
end
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
ReadTxDataFromFifo_sync3 <=#Tp 1'b0;
else
ReadTxDataFromFifo_sync3 <=#Tp ReadTxDataFromFifo_sync2;
end
assign ReadTxDataFromFifo_wb = ReadTxDataFromFifo_sync2 & ~ReadTxDataFromFifo_sync3;
// End: Generation of the ReadTxDataFromFifo_tck signal and synchronization to the WB_CLK_I
// Synchronizing TxRetry signal (synchronized to WISHBONE clock)
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
TxRetrySync1 <=#Tp 1'b0;
else
TxRetrySync1 <=#Tp TxRetry;
end
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
TxRetry_wb <=#Tp 1'b0;
else
TxRetry_wb <=#Tp TxRetrySync1;
end
// Synchronized TxDone_wb signal (synchronized to WISHBONE clock)
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
TxDoneSync1 <=#Tp 1'b0;
else
TxDoneSync1 <=#Tp TxDone;
end
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
TxDone_wb <=#Tp 1'b0;
else
TxDone_wb <=#Tp TxDoneSync1;
end
// Synchronizing TxAbort signal (synchronized to WISHBONE clock)
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
TxAbortSync1 <=#Tp 1'b0;
else
TxAbortSync1 <=#Tp TxAbort;
end
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
TxAbort_wb <=#Tp 1'b0;
else
TxAbort_wb <=#Tp TxAbortSync1;
end
reg RxAbortSync1;
reg RxAbortSync2;
reg RxAbortSync3;
reg RxAbortSync4;
reg RxAbortSyncb1;
reg RxAbortSyncb2;
assign StartRxBDRead = RxStatusWrite | RxAbortSync3 & ~RxAbortSync4 | r_RxEn & ~r_RxEn_q;
// Reading the Rx buffer descriptor
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
RxBDRead <=#Tp 1'b0;
else
if(StartRxBDRead & ~RxReady)
RxBDRead <=#Tp 1'b1;
else
if(RxBDReady)
RxBDRead <=#Tp 1'b0;
end
// Reading of the next receive buffer descriptor starts after reception status is
// written to the previous one.
// Latching READY status of the Rx buffer descriptor
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
RxBDReady <=#Tp 1'b0;
else
if(RxPointerRead)
RxBDReady <=#Tp 1'b0;
else
if(RxEn & RxEn_q & RxBDRead)
RxBDReady <=#Tp ram_do[15]; // RxBDReady is sampled only once at the beginning
end
// Latching Rx buffer descriptor status
// Data is avaliable one cycle after the access is started (at that time signal RxEn is not active)
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
RxStatus <=#Tp 2'h0;
else
if(RxEn & RxEn_q & RxBDRead)
RxStatus <=#Tp ram_do[14:13];
end
// RxReady generation
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
RxReady <=#Tp 1'b0;
else
if(ShiftEnded | RxAbortSync2 & ~RxAbortSync3 | ~r_RxEn & r_RxEn_q)
RxReady <=#Tp 1'b0;
else
if(RxEn & RxEn_q & RxPointerRead)
RxReady <=#Tp 1'b1;
end
// Reading Rx BD pointer
assign StartRxPointerRead = RxBDRead & RxBDReady;
// Reading Tx BD Pointer
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
RxPointerRead <=#Tp 1'b0;
else
if(StartRxPointerRead)
RxPointerRead <=#Tp 1'b1;
else
if(RxEn & RxEn_q)
RxPointerRead <=#Tp 1'b0;
end
//Latching Rx buffer pointer from buffer descriptor;
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
RxPointerMSB <=#Tp 30'h0;
else
if(RxEn & RxEn_q & RxPointerRead)
RxPointerMSB <=#Tp ram_do[31:2];
else
if(MasterWbRX & m_wb_ack_i)
RxPointerMSB <=#Tp RxPointerMSB + 1'b1; // Word access (always word access. m_wb_sel_o are used for selecting bytes)
end
//Latching last addresses from buffer descriptor (used as byte-half-word indicator);
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
RxPointerLSB_rst[1:0] <=#Tp 0;
else
if(MasterWbRX & m_wb_ack_i) // After first write all RxByteSel are active
RxPointerLSB_rst[1:0] <=#Tp 0;
else
if(RxEn & RxEn_q & RxPointerRead)
RxPointerLSB_rst[1:0] <=#Tp ram_do[1:0];
end
always @ (RxPointerLSB_rst)
begin
case(RxPointerLSB_rst[1:0]) // synopsys parallel_case
2'h0 : RxByteSel[3:0] = 4'hf;
2'h1 : RxByteSel[3:0] = 4'h7;
2'h2 : RxByteSel[3:0] = 4'h3;
2'h3 : RxByteSel[3:0] = 4'h1;
endcase
end
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
RxEn_needed <=#Tp 1'b0;
else
if(~RxReady & r_RxEn & WbEn & ~WbEn_q)
RxEn_needed <=#Tp 1'b1;
else
if(RxPointerRead & RxEn & RxEn_q)
RxEn_needed <=#Tp 1'b0;
end
// Reception status is written back to the buffer descriptor after the end of frame is detected.
assign RxStatusWrite = ShiftEnded & RxEn & RxEn_q;
reg RxEnableWindow;
// Indicating that last byte is being reveived
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
LastByteIn <=#Tp 1'b0;
else
if(ShiftWillEnd & (&RxByteCnt) | RxAbort)
LastByteIn <=#Tp 1'b0;
else
if(RxValid & RxReady & RxEndFrm & ~(&RxByteCnt) & RxEnableWindow)
LastByteIn <=#Tp 1'b1;
end
reg ShiftEnded_rck;
reg ShiftEndedSync1;
reg ShiftEndedSync2;
reg ShiftEndedSync3;
reg ShiftEndedSync_c1;
reg ShiftEndedSync_c2;
wire StartShiftWillEnd;
assign StartShiftWillEnd = LastByteIn | RxValid & RxEndFrm & (&RxByteCnt) & RxEnableWindow;
// Indicating that data reception will end
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
ShiftWillEnd <=#Tp 1'b0;
else
if(ShiftEnded_rck | RxAbort)
ShiftWillEnd <=#Tp 1'b0;
else
if(StartShiftWillEnd)
ShiftWillEnd <=#Tp 1'b1;
end
// Receive byte counter
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
RxByteCnt <=#Tp 2'h0;
else
if(ShiftEnded_rck | RxAbort)
RxByteCnt <=#Tp 2'h0;
else
if(RxValid & RxStartFrm & RxReady)
case(RxPointerLSB_rst) // synopsys parallel_case
2'h0 : RxByteCnt <=#Tp 2'h1;
2'h1 : RxByteCnt <=#Tp 2'h2;
2'h2 : RxByteCnt <=#Tp 2'h3;
2'h3 : RxByteCnt <=#Tp 2'h0;
endcase
else
if(RxValid & RxEnableWindow & RxReady | LastByteIn)
RxByteCnt <=#Tp RxByteCnt + 1'b1;
end
// Indicates how many bytes are valid within the last word
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
RxValidBytes <=#Tp 2'h1;
else
if(RxValid & RxStartFrm)
case(RxPointerLSB_rst) // synopsys parallel_case
2'h0 : RxValidBytes <=#Tp 2'h1;
2'h1 : RxValidBytes <=#Tp 2'h2;
2'h2 : RxValidBytes <=#Tp 2'h3;
2'h3 : RxValidBytes <=#Tp 2'h0;
endcase
else
if(RxValid & ~LastByteIn & ~RxStartFrm & RxEnableWindow)
RxValidBytes <=#Tp RxValidBytes + 1'b1;
end
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
RxDataLatched1 <=#Tp 24'h0;
else
if(RxValid & RxReady & ~LastByteIn)
if(RxStartFrm)
begin
case(RxPointerLSB_rst) // synopsys parallel_case
2'h0: RxDataLatched1[31:24] <=#Tp RxData; // Big Endian Byte Ordering
2'h1: RxDataLatched1[23:16] <=#Tp RxData;
2'h2: RxDataLatched1[15:8] <=#Tp RxData;
2'h3: RxDataLatched1 <=#Tp RxDataLatched1;
endcase
end
else if (RxEnableWindow)
begin
case(RxByteCnt) // synopsys parallel_case
2'h0: RxDataLatched1[31:24] <=#Tp RxData; // Big Endian Byte Ordering
2'h1: RxDataLatched1[23:16] <=#Tp RxData;
2'h2: RxDataLatched1[15:8] <=#Tp RxData;
2'h3: RxDataLatched1 <=#Tp RxDataLatched1;
endcase
end
end
wire SetWriteRxDataToFifo;
// Assembling data that will be written to the rx_fifo
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
RxDataLatched2 <=#Tp 32'h0;
else
if(SetWriteRxDataToFifo & ~ShiftWillEnd)
RxDataLatched2 <=#Tp {RxDataLatched1[31:8], RxData}; // Big Endian Byte Ordering
else
if(SetWriteRxDataToFifo & ShiftWillEnd)
case(RxValidBytes) // synopsys parallel_case
0 : RxDataLatched2 <=#Tp {RxDataLatched1[31:8], RxData}; // Big Endian Byte Ordering
1 : RxDataLatched2 <=#Tp {RxDataLatched1[31:24], 24'h0};
2 : RxDataLatched2 <=#Tp {RxDataLatched1[31:16], 16'h0};
3 : RxDataLatched2 <=#Tp {RxDataLatched1[31:8], 8'h0};
endcase
end
reg WriteRxDataToFifoSync1;
reg WriteRxDataToFifoSync2;
reg WriteRxDataToFifoSync3;
// Indicating start of the reception process
assign SetWriteRxDataToFifo = (RxValid & RxReady & ~RxStartFrm & RxEnableWindow & (&RxByteCnt)) |
(RxValid & RxReady & RxStartFrm & (&RxPointerLSB_rst)) |
(ShiftWillEnd & LastByteIn & (&RxByteCnt));
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
WriteRxDataToFifo <=#Tp 1'b0;
else
if(SetWriteRxDataToFifo & ~RxAbort)
WriteRxDataToFifo <=#Tp 1'b1;
else
if(WriteRxDataToFifoSync2 | RxAbort)
WriteRxDataToFifo <=#Tp 1'b0;
end
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
WriteRxDataToFifoSync1 <=#Tp 1'b0;
else
if(WriteRxDataToFifo)
WriteRxDataToFifoSync1 <=#Tp 1'b1;
else
WriteRxDataToFifoSync1 <=#Tp 1'b0;
end
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
WriteRxDataToFifoSync2 <=#Tp 1'b0;
else
WriteRxDataToFifoSync2 <=#Tp WriteRxDataToFifoSync1;
end
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
WriteRxDataToFifoSync3 <=#Tp 1'b0;
else
WriteRxDataToFifoSync3 <=#Tp WriteRxDataToFifoSync2;
end
wire WriteRxDataToFifo_wb;
assign WriteRxDataToFifo_wb = WriteRxDataToFifoSync2 & ~WriteRxDataToFifoSync3;
reg LatchedRxStartFrm;
reg SyncRxStartFrm;
reg SyncRxStartFrm_q;
reg SyncRxStartFrm_q2;
wire RxFifoReset;
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
LatchedRxStartFrm <=#Tp 0;
else
if(RxStartFrm & ~SyncRxStartFrm_q)
LatchedRxStartFrm <=#Tp 1;
else
if(SyncRxStartFrm_q)
LatchedRxStartFrm <=#Tp 0;
end
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
SyncRxStartFrm <=#Tp 0;
else
if(LatchedRxStartFrm)
SyncRxStartFrm <=#Tp 1;
else
SyncRxStartFrm <=#Tp 0;
end
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
SyncRxStartFrm_q <=#Tp 0;
else
SyncRxStartFrm_q <=#Tp SyncRxStartFrm;
end
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
SyncRxStartFrm_q2 <=#Tp 0;
else
SyncRxStartFrm_q2 <=#Tp SyncRxStartFrm_q;
end
assign RxFifoReset = SyncRxStartFrm_q & ~SyncRxStartFrm_q2;
eth_fifo #(`ETH_RX_FIFO_DATA_WIDTH, `ETH_RX_FIFO_DEPTH, `ETH_RX_FIFO_CNT_WIDTH)
rx_fifo (.data_in(RxDataLatched2), .data_out(m_wb_dat_o),
.clk(WB_CLK_I), .reset(Reset),
.write(WriteRxDataToFifo_wb & ~RxBufferFull), .read(MasterWbRX & m_wb_ack_i),
.clear(RxFifoReset), .full(RxBufferFull),
.almost_full(), .almost_empty(RxBufferAlmostEmpty),
.empty(RxBufferEmpty), .cnt(rxfifo_cnt)
);
assign enough_data_in_rxfifo_for_burst = rxfifo_cnt>=`ETH_BURST_LENGTH;
assign enough_data_in_rxfifo_for_burst_plus1 = rxfifo_cnt>`ETH_BURST_LENGTH;
assign WriteRxDataToMemory = ~RxBufferEmpty;
assign rx_burst = rx_burst_en & WriteRxDataToMemory;
// Generation of the end-of-frame signal
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
ShiftEnded_rck <=#Tp 1'b0;
else
if(~RxAbort & SetWriteRxDataToFifo & StartShiftWillEnd)
ShiftEnded_rck <=#Tp 1'b1;
else
if(RxAbort | ShiftEndedSync_c1 & ShiftEndedSync_c2)
ShiftEnded_rck <=#Tp 1'b0;
end
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
ShiftEndedSync1 <=#Tp 1'b0;
else
ShiftEndedSync1 <=#Tp ShiftEnded_rck;
end
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
ShiftEndedSync2 <=#Tp 1'b0;
else
ShiftEndedSync2 <=#Tp ShiftEndedSync1;
end
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
ShiftEndedSync3 <=#Tp 1'b0;
else
if(ShiftEndedSync1 & ~ShiftEndedSync2)
ShiftEndedSync3 <=#Tp 1'b1;
else
if(ShiftEnded)
ShiftEndedSync3 <=#Tp 1'b0;
end
// Generation of the end-of-frame signal
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
ShiftEnded <=#Tp 1'b0;
else
if(ShiftEndedSync3 & MasterWbRX & m_wb_ack_i & RxBufferAlmostEmpty & ~ShiftEnded)
ShiftEnded <=#Tp 1'b1;
else
if(RxStatusWrite)
ShiftEnded <=#Tp 1'b0;
end
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
ShiftEndedSync_c1 <=#Tp 1'b0;
else
ShiftEndedSync_c1 <=#Tp ShiftEndedSync2;
end
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
ShiftEndedSync_c2 <=#Tp 1'b0;
else
ShiftEndedSync_c2 <=#Tp ShiftEndedSync_c1;
end
// Generation of the end-of-frame signal
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
RxEnableWindow <=#Tp 1'b0;
else
if(RxStartFrm)
RxEnableWindow <=#Tp 1'b1;
else
if(RxEndFrm | RxAbort)
RxEnableWindow <=#Tp 1'b0;
end
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
RxAbortSync1 <=#Tp 1'b0;
else
RxAbortSync1 <=#Tp RxAbortLatched;
end
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
RxAbortSync2 <=#Tp 1'b0;
else
RxAbortSync2 <=#Tp RxAbortSync1;
end
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
RxAbortSync3 <=#Tp 1'b0;
else
RxAbortSync3 <=#Tp RxAbortSync2;
end
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
RxAbortSync4 <=#Tp 1'b0;
else
RxAbortSync4 <=#Tp RxAbortSync3;
end
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
RxAbortSyncb1 <=#Tp 1'b0;
else
RxAbortSyncb1 <=#Tp RxAbortSync2;
end
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
RxAbortSyncb2 <=#Tp 1'b0;
else
RxAbortSyncb2 <=#Tp RxAbortSyncb1;
end
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
RxAbortLatched <=#Tp 1'b0;
else
if(RxAbortSyncb2)
RxAbortLatched <=#Tp 1'b0;
else
if(RxAbort)
RxAbortLatched <=#Tp 1'b1;
end
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
LatchedRxLength[15:0] <=#Tp 16'h0;
else
if(LoadRxStatus)
LatchedRxLength[15:0] <=#Tp RxLength[15:0];
end
assign RxStatusIn = {ReceivedPauseFrm, AddressMiss, RxOverrun, InvalidSymbol, DribbleNibble, ReceivedPacketTooBig, ShortFrame, LatchedCrcError, RxLateCollision};
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
RxStatusInLatched <=#Tp 'h0;
else
if(LoadRxStatus)
RxStatusInLatched <=#Tp RxStatusIn;
end
// Rx overrun
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
RxOverrun <=#Tp 1'b0;
else
if(RxStatusWrite)
RxOverrun <=#Tp 1'b0;
else
if(RxBufferFull & WriteRxDataToFifo_wb)
RxOverrun <=#Tp 1'b1;
end
wire TxError;
assign TxError = TxUnderRun | RetryLimit | LateCollLatched | CarrierSenseLost;
wire RxError;
// ShortFrame (RxStatusInLatched[2]) can not set an error because short frames
// are aborted when signal r_RecSmall is set to 0 in MODER register.
// AddressMiss is identifying that a frame was received because of the promiscous
// mode and is not an error
assign RxError = (|RxStatusInLatched[6:3]) | (|RxStatusInLatched[1:0]);
reg RxStatusWriteLatched;
reg RxStatusWriteLatched_sync1;
reg RxStatusWriteLatched_sync2;
reg RxStatusWriteLatched_syncb1;
reg RxStatusWriteLatched_syncb2;
// Latching and synchronizing RxStatusWrite signal. This signal is used for clearing the ReceivedPauseFrm signal
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
RxStatusWriteLatched <=#Tp 1'b0;
else
if(RxStatusWriteLatched_syncb2)
RxStatusWriteLatched <=#Tp 1'b0;
else
if(RxStatusWrite)
RxStatusWriteLatched <=#Tp 1'b1;
end
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
begin
RxStatusWriteLatched_sync1 <=#Tp 1'b0;
RxStatusWriteLatched_sync2 <=#Tp 1'b0;
end
else
begin
RxStatusWriteLatched_sync1 <=#Tp RxStatusWriteLatched;
RxStatusWriteLatched_sync2 <=#Tp RxStatusWriteLatched_sync1;
end
end
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
begin
RxStatusWriteLatched_syncb1 <=#Tp 1'b0;
RxStatusWriteLatched_syncb2 <=#Tp 1'b0;
end
else
begin
RxStatusWriteLatched_syncb1 <=#Tp RxStatusWriteLatched_sync2;
RxStatusWriteLatched_syncb2 <=#Tp RxStatusWriteLatched_syncb1;
end
end
// Tx Done Interrupt
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
TxB_IRQ <=#Tp 1'b0;
else
if(TxStatusWrite & TxIRQEn)
TxB_IRQ <=#Tp ~TxError;
else
TxB_IRQ <=#Tp 1'b0;
end
// Tx Error Interrupt
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
TxE_IRQ <=#Tp 1'b0;
else
if(TxStatusWrite & TxIRQEn)
TxE_IRQ <=#Tp TxError;
else
TxE_IRQ <=#Tp 1'b0;
end
// Rx Done Interrupt
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
RxB_IRQ <=#Tp 1'b0;
else
if(RxStatusWrite & RxIRQEn & ReceivedPacketGood & (~ReceivedPauseFrm | ReceivedPauseFrm & r_PassAll & (~r_RxFlow)))
RxB_IRQ <=#Tp (~RxError);
else
RxB_IRQ <=#Tp 1'b0;
end
// Rx Error Interrupt
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
RxE_IRQ <=#Tp 1'b0;
else
if(RxStatusWrite & RxIRQEn & (~ReceivedPauseFrm | ReceivedPauseFrm & r_PassAll & (~r_RxFlow)))
RxE_IRQ <=#Tp RxError;
else
RxE_IRQ <=#Tp 1'b0;
end
// Busy Interrupt
reg Busy_IRQ_rck;
reg Busy_IRQ_sync1;
reg Busy_IRQ_sync2;
reg Busy_IRQ_sync3;
reg Busy_IRQ_syncb1;
reg Busy_IRQ_syncb2;
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
Busy_IRQ_rck <=#Tp 1'b0;
else
if(RxValid & RxStartFrm & ~RxReady)
Busy_IRQ_rck <=#Tp 1'b1;
else
if(Busy_IRQ_syncb2)
Busy_IRQ_rck <=#Tp 1'b0;
end
always @ (posedge WB_CLK_I)
begin
Busy_IRQ_sync1 <=#Tp Busy_IRQ_rck;
Busy_IRQ_sync2 <=#Tp Busy_IRQ_sync1;
Busy_IRQ_sync3 <=#Tp Busy_IRQ_sync2;
end
always @ (posedge MRxClk)
begin
Busy_IRQ_syncb1 <=#Tp Busy_IRQ_sync2;
Busy_IRQ_syncb2 <=#Tp Busy_IRQ_syncb1;
end
assign Busy_IRQ = Busy_IRQ_sync2 & ~Busy_IRQ_sync3;
endmodule
|
//////////////////////////////////////////////////////////////////////
//// ////
//// timescale.v ////
//// ////
//// This file is part of the Ethernet IP core project ////
//// http://www.opencores.org/projects/ethmac/ ////
//// ////
//// Author(s): ////
//// - Igor Mohor ([email protected]) ////
//// ////
//// All additional information is avaliable in the Readme.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: timescale.v,v $
// Revision 1.3 2002/01/23 10:28:16 mohor
// Link in the header changed.
//
// Revision 1.2 2001/10/19 11:36:31 mohor
// Log file added.
//
//
//
`timescale 1ns / 1ns
|
module xilinx_dist_ram_16x32
(
data_out,
we,
data_in,
read_address,
write_address,
wclk
);
output [31:0] data_out;
input we, wclk;
input [31:0] data_in;
input [3:0] write_address, read_address;
wire [3:0] waddr = write_address ;
wire [3:0] raddr = read_address ;
RAM16X1D ram00 (.DPO(data_out[0]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[0]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we));
RAM16X1D ram01 (.DPO(data_out[1]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[1]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we));
RAM16X1D ram02 (.DPO(data_out[2]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[2]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we));
RAM16X1D ram03 (.DPO(data_out[3]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[3]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we));
RAM16X1D ram04 (.DPO(data_out[4]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[4]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we));
RAM16X1D ram05 (.DPO(data_out[5]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[5]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we));
RAM16X1D ram06 (.DPO(data_out[6]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[6]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we));
RAM16X1D ram07 (.DPO(data_out[7]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[7]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we));
RAM16X1D ram08 (.DPO(data_out[8]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[8]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we));
RAM16X1D ram09 (.DPO(data_out[9]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[9]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we));
RAM16X1D ram10 (.DPO(data_out[10]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[10]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we));
RAM16X1D ram11 (.DPO(data_out[11]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[11]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we));
RAM16X1D ram12 (.DPO(data_out[12]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[12]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we));
RAM16X1D ram13 (.DPO(data_out[13]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[13]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we));
RAM16X1D ram14 (.DPO(data_out[14]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[14]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we));
RAM16X1D ram15 (.DPO(data_out[15]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[15]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we));
RAM16X1D ram16 (.DPO(data_out[16]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[16]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we));
RAM16X1D ram17 (.DPO(data_out[17]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[17]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we));
RAM16X1D ram18 (.DPO(data_out[18]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[18]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we));
RAM16X1D ram19 (.DPO(data_out[19]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[19]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we));
RAM16X1D ram20 (.DPO(data_out[20]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[20]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we));
RAM16X1D ram21 (.DPO(data_out[21]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[21]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we));
RAM16X1D ram22 (.DPO(data_out[22]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[22]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we));
RAM16X1D ram23 (.DPO(data_out[23]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[23]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we));
RAM16X1D ram24 (.DPO(data_out[24]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[24]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we));
RAM16X1D ram25 (.DPO(data_out[25]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[25]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we));
RAM16X1D ram26 (.DPO(data_out[26]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[26]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we));
RAM16X1D ram27 (.DPO(data_out[27]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[27]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we));
RAM16X1D ram28 (.DPO(data_out[28]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[28]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we));
RAM16X1D ram29 (.DPO(data_out[29]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[29]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we));
RAM16X1D ram30 (.DPO(data_out[30]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[30]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we));
RAM16X1D ram31 (.DPO(data_out[31]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[31]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we));
endmodule
|
// megafunction wizard: %ALTMULT_ADD%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: ALTMULT_ADD
// ============================================================
// File Name: dsp_2mult_add.v
// Megafunction Name(s):
// ALTMULT_ADD
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 12.1 Build 177 11/07/2012 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2012 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module dsp_2mult_add (
clock0,
dataa_0,
dataa_1,
datab_0,
datab_1,
ena0,
result);
input clock0;
input [16:0] dataa_0;
input [16:0] dataa_1;
input [15:0] datab_0;
input [15:0] datab_1;
input ena0;
output [34:0] result;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock0;
tri0 [16:0] dataa_0;
tri0 [16:0] dataa_1;
tri0 [15:0] datab_0;
tri0 [15:0] datab_1;
tri1 ena0;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [34:0] sub_wire0;
wire [16:0] sub_wire6 = dataa_1[16:0];
wire [15:0] sub_wire3 = datab_1[15:0];
wire [34:0] result = sub_wire0[34:0];
wire [15:0] sub_wire1 = datab_0[15:0];
wire [31:0] sub_wire2 = {sub_wire3, sub_wire1};
wire [16:0] sub_wire4 = dataa_0[16:0];
wire [33:0] sub_wire5 = {sub_wire6, sub_wire4};
altmult_add ALTMULT_ADD_component (
.clock0 (clock0),
.datab (sub_wire2),
.ena0 (ena0),
.dataa (sub_wire5),
.result (sub_wire0),
.accum_sload (1'b0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.aclr2 (1'b0),
.aclr3 (1'b0),
.addnsub1 (1'b1),
.addnsub1_round (1'b0),
.addnsub3 (1'b1),
.addnsub3_round (1'b0),
.chainin (1'b0),
.chainout_round (1'b0),
.chainout_sat_overflow (),
.chainout_saturate (1'b0),
.clock1 (1'b1),
.clock2 (1'b1),
.clock3 (1'b1),
.coefsel0 ({3{1'b0}}),
.coefsel1 ({3{1'b0}}),
.coefsel2 ({3{1'b0}}),
.coefsel3 ({3{1'b0}}),
.datac ({44{1'b0}}),
.ena1 (1'b1),
.ena2 (1'b1),
.ena3 (1'b1),
.mult01_round (1'b0),
.mult01_saturation (1'b0),
.mult0_is_saturated (),
.mult1_is_saturated (),
.mult23_round (1'b0),
.mult23_saturation (1'b0),
.mult2_is_saturated (),
.mult3_is_saturated (),
.output_round (1'b0),
.output_saturate (1'b0),
.overflow (),
.rotate (1'b0),
.scanina ({17{1'b0}}),
.scaninb ({16{1'b0}}),
.scanouta (),
.scanoutb (),
.shift_right (1'b0),
.signa (1'b0),
.signb (1'b0),
.sourcea ({2{1'b0}}),
.sourceb ({2{1'b0}}),
.zero_chainout (1'b0),
.zero_loopback (1'b0));
defparam
ALTMULT_ADD_component.accumulator = "NO",
ALTMULT_ADD_component.addnsub_multiplier_aclr1 = "UNUSED",
ALTMULT_ADD_component.addnsub_multiplier_pipeline_aclr1 = "UNUSED",
ALTMULT_ADD_component.addnsub_multiplier_pipeline_register1 = "CLOCK0",
ALTMULT_ADD_component.addnsub_multiplier_register1 = "CLOCK0",
ALTMULT_ADD_component.chainout_adder = "NO",
ALTMULT_ADD_component.chainout_register = "UNREGISTERED",
ALTMULT_ADD_component.dedicated_multiplier_circuitry = "YES",
ALTMULT_ADD_component.input_aclr_a0 = "UNUSED",
ALTMULT_ADD_component.input_aclr_a1 = "UNUSED",
ALTMULT_ADD_component.input_aclr_b0 = "UNUSED",
ALTMULT_ADD_component.input_aclr_b1 = "UNUSED",
ALTMULT_ADD_component.input_register_a0 = "CLOCK0",
ALTMULT_ADD_component.input_register_a1 = "CLOCK0",
ALTMULT_ADD_component.input_register_b0 = "CLOCK0",
ALTMULT_ADD_component.input_register_b1 = "CLOCK0",
ALTMULT_ADD_component.input_source_a0 = "DATAA",
ALTMULT_ADD_component.input_source_a1 = "DATAA",
ALTMULT_ADD_component.input_source_b0 = "DATAB",
ALTMULT_ADD_component.input_source_b1 = "DATAB",
ALTMULT_ADD_component.intended_device_family = "Stratix IV",
ALTMULT_ADD_component.lpm_type = "altmult_add",
ALTMULT_ADD_component.multiplier1_direction = "ADD",
ALTMULT_ADD_component.multiplier_aclr0 = "UNUSED",
ALTMULT_ADD_component.multiplier_aclr1 = "UNUSED",
ALTMULT_ADD_component.multiplier_register0 = "CLOCK0",
ALTMULT_ADD_component.multiplier_register1 = "CLOCK0",
ALTMULT_ADD_component.number_of_multipliers = 2,
ALTMULT_ADD_component.output_aclr = "UNUSED",
ALTMULT_ADD_component.output_register = "CLOCK0",
ALTMULT_ADD_component.port_addnsub1 = "PORT_UNUSED",
ALTMULT_ADD_component.port_signa = "PORT_UNUSED",
ALTMULT_ADD_component.port_signb = "PORT_UNUSED",
ALTMULT_ADD_component.representation_a = "SIGNED",
ALTMULT_ADD_component.representation_b = "SIGNED",
ALTMULT_ADD_component.signed_aclr_a = "UNUSED",
ALTMULT_ADD_component.signed_aclr_b = "UNUSED",
ALTMULT_ADD_component.signed_pipeline_aclr_a = "UNUSED",
ALTMULT_ADD_component.signed_pipeline_aclr_b = "UNUSED",
ALTMULT_ADD_component.signed_pipeline_register_a = "CLOCK0",
ALTMULT_ADD_component.signed_pipeline_register_b = "CLOCK0",
ALTMULT_ADD_component.signed_register_a = "CLOCK0",
ALTMULT_ADD_component.signed_register_b = "CLOCK0",
ALTMULT_ADD_component.width_a = 17,
ALTMULT_ADD_component.width_b = 16,
ALTMULT_ADD_component.width_chainin = 1,
ALTMULT_ADD_component.width_result = 35,
ALTMULT_ADD_component.zero_chainout_output_register = "UNREGISTERED",
ALTMULT_ADD_component.zero_loopback_aclr = "UNUSED",
ALTMULT_ADD_component.zero_loopback_output_aclr = "UNUSED",
ALTMULT_ADD_component.zero_loopback_output_register = "CLOCK0",
ALTMULT_ADD_component.zero_loopback_pipeline_aclr = "UNUSED",
ALTMULT_ADD_component.zero_loopback_pipeline_register = "CLOCK0",
ALTMULT_ADD_component.zero_loopback_register = "CLOCK0";
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ACCUM_DIRECTION STRING "Add"
// Retrieval info: PRIVATE: ACCUM_SLOAD_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ACCUM_SLOAD_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ACCUM_SLOAD_PIPE_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ACCUM_SLOAD_PIPE_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ACCUM_SLOAD_PIPE_REG STRING "1"
// Retrieval info: PRIVATE: ACCUM_SLOAD_REG STRING "1"
// Retrieval info: PRIVATE: ADDNSUB1_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ADDNSUB1_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ADDNSUB1_PIPE_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ADDNSUB1_PIPE_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ADDNSUB1_PIPE_REG STRING "1"
// Retrieval info: PRIVATE: ADDNSUB1_REG STRING "1"
// Retrieval info: PRIVATE: ADDNSUB3_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ADDNSUB3_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ADDNSUB3_PIPE_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ADDNSUB3_PIPE_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ADDNSUB3_PIPE_REG STRING "1"
// Retrieval info: PRIVATE: ADDNSUB3_REG STRING "1"
// Retrieval info: PRIVATE: ADD_ENABLE NUMERIC "1"
// Retrieval info: PRIVATE: ALL_REG_ACLR NUMERIC "0"
// Retrieval info: PRIVATE: A_ACLR_SRC_MULT0 NUMERIC "3"
// Retrieval info: PRIVATE: A_CLK_SRC_MULT0 NUMERIC "0"
// Retrieval info: PRIVATE: B_ACLR_SRC_MULT0 NUMERIC "3"
// Retrieval info: PRIVATE: B_CLK_SRC_MULT0 NUMERIC "0"
// Retrieval info: PRIVATE: CHAINOUT_OUTPUT_ACLR NUMERIC "3"
// Retrieval info: PRIVATE: CHAINOUT_OUTPUT_REG STRING "0"
// Retrieval info: PRIVATE: CHAINOUT_OUTPUT_REGISTER NUMERIC "0"
// Retrieval info: PRIVATE: CHAINOUT_OUTPUT_REGISTERED NUMERIC "0"
// Retrieval info: PRIVATE: CHAS_ZERO_CHAINOUT NUMERIC "0"
// Retrieval info: PRIVATE: HAS_ACCUMULATOR NUMERIC "0"
// Retrieval info: PRIVATE: HAS_ACUMM_SLOAD NUMERIC "0"
// Retrieval info: PRIVATE: HAS_CHAININ_PORT NUMERIC "0"
// Retrieval info: PRIVATE: HAS_CHAINOUT_ADDER NUMERIC "0"
// Retrieval info: PRIVATE: HAS_LOOPBACK NUMERIC "0"
// Retrieval info: PRIVATE: HAS_MAC STRING "0"
// Retrieval info: PRIVATE: HAS_SAT_ROUND STRING "0"
// Retrieval info: PRIVATE: HAS_ZERO_LOOPBACK NUMERIC "0"
// Retrieval info: PRIVATE: IMPL_STYLE_DEDICATED NUMERIC "1"
// Retrieval info: PRIVATE: IMPL_STYLE_DEFAULT NUMERIC "0"
// Retrieval info: PRIVATE: IMPL_STYLE_LCELL NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
// Retrieval info: PRIVATE: MULT_REGA0 NUMERIC "1"
// Retrieval info: PRIVATE: MULT_REGB0 NUMERIC "1"
// Retrieval info: PRIVATE: MULT_REGOUT0 NUMERIC "1"
// Retrieval info: PRIVATE: NUM_MULT STRING "2"
// Retrieval info: PRIVATE: OP1 STRING "Add"
// Retrieval info: PRIVATE: OP3 STRING "Add"
// Retrieval info: PRIVATE: OUTPUT_EXTRA_LAT NUMERIC "0"
// Retrieval info: PRIVATE: OUTPUT_REG_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: OUTPUT_REG_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: Q_ACLR_SRC_MULT0 NUMERIC "3"
// Retrieval info: PRIVATE: Q_CLK_SRC_MULT0 NUMERIC "0"
// Retrieval info: PRIVATE: REG_OUT NUMERIC "1"
// Retrieval info: PRIVATE: RNFORMAT STRING "35"
// Retrieval info: PRIVATE: ROTATE_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ROTATE_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ROTATE_OUT_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ROTATE_OUT_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ROTATE_OUT_REG STRING "1"
// Retrieval info: PRIVATE: ROTATE_PIPE_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ROTATE_PIPE_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ROTATE_PIPE_REG STRING "1"
// Retrieval info: PRIVATE: ROTATE_REG STRING "1"
// Retrieval info: PRIVATE: ROUND3_CHAINOUT_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ROUND3_CHAINOUT_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ROUND3_CHAINOUT_MODE STRING "Enabled"
// Retrieval info: PRIVATE: ROUND3_CHAINOUT_OUT_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ROUND3_CHAINOUT_OUT_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ROUND3_CHAINOUT_OUT_REG STRING "1"
// Retrieval info: PRIVATE: ROUND3_CHAINOUT_PIPE_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ROUND3_CHAINOUT_PIPE_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ROUND3_CHAINOUT_PIPE_REG STRING "1"
// Retrieval info: PRIVATE: ROUND3_CHAINOUT_REG STRING "1"
// Retrieval info: PRIVATE: ROUND3_FRAC_WIDTH NUMERIC "27"
// Retrieval info: PRIVATE: ROUND3_OUTPUT_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ROUND3_OUTPUT_CHAINOUT_TYPE STRING "Nearest Integer"
// Retrieval info: PRIVATE: ROUND3_OUTPUT_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ROUND3_OUTPUT_MODE STRING "Disabled"
// Retrieval info: PRIVATE: ROUND3_OUTPUT_PIPE_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ROUND3_OUTPUT_PIPE_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ROUND3_OUTPUT_PIPE_REG STRING "1"
// Retrieval info: PRIVATE: ROUND3_OUTPUT_REG STRING "1"
// Retrieval info: PRIVATE: RQFORMAT STRING "Q1.15"
// Retrieval info: PRIVATE: RTS_WIDTH STRING "35"
// Retrieval info: PRIVATE: SAME_CONFIG NUMERIC "1"
// Retrieval info: PRIVATE: SAME_CONTROL_SRC_A0 NUMERIC "1"
// Retrieval info: PRIVATE: SAME_CONTROL_SRC_B0 NUMERIC "1"
// Retrieval info: PRIVATE: SAT3_CHAINOUT_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: SAT3_CHAINOUT_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: SAT3_CHAINOUT_MODE STRING "Enabled"
// Retrieval info: PRIVATE: SAT3_CHAINOUT_OUT_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: SAT3_CHAINOUT_OUT_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: SAT3_CHAINOUT_PIPE_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: SAT3_CHAINOUT_PIPE_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: SAT3_CHAINOUT_PIPE_REG STRING "1"
// Retrieval info: PRIVATE: SAT3_CHAINOUT_REG STRING "1"
// Retrieval info: PRIVATE: SAT3_FRAC_WIDTH NUMERIC "5"
// Retrieval info: PRIVATE: SAT3_OUTPUT_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: SAT3_OUTPUT_CHAINOUT_TYPE STRING "Asymmetric"
// Retrieval info: PRIVATE: SAT3_OUTPUT_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: SAT3_OUTPUT_MODE STRING "Enabled"
// Retrieval info: PRIVATE: SAT3_OUTPUT_OVERFLOW NUMERIC "0"
// Retrieval info: PRIVATE: SAT3_OUTPUT_PIPE_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: SAT3_OUTPUT_PIPE_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: SAT3_OUTPUT_PIPE_REG STRING "1"
// Retrieval info: PRIVATE: SAT3_OUTPUT_REG STRING "1"
// Retrieval info: PRIVATE: SCANOUTA NUMERIC "0"
// Retrieval info: PRIVATE: SCANOUTB NUMERIC "0"
// Retrieval info: PRIVATE: SHIFTOUTA_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: SHIFTOUTA_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: SHIFTOUTA_REG STRING "0"
// Retrieval info: PRIVATE: SHIFT_RIGHT_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: SHIFT_RIGHT_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: SHIFT_RIGHT_OUT_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: SHIFT_RIGHT_OUT_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: SHIFT_RIGHT_OUT_REG STRING "1"
// Retrieval info: PRIVATE: SHIFT_RIGHT_PIPE_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: SHIFT_RIGHT_PIPE_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: SHIFT_RIGHT_PIPE_REG STRING "1"
// Retrieval info: PRIVATE: SHIFT_RIGHT_REG STRING "1"
// Retrieval info: PRIVATE: SHIFT_ROTATE_MODE STRING "None"
// Retrieval info: PRIVATE: SIGNA STRING "SIGNED"
// Retrieval info: PRIVATE: SIGNA_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: SIGNA_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: SIGNA_PIPE_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: SIGNA_PIPE_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: SIGNA_PIPE_REG STRING "1"
// Retrieval info: PRIVATE: SIGNA_REG STRING "1"
// Retrieval info: PRIVATE: SIGNB STRING "SIGNED"
// Retrieval info: PRIVATE: SIGNB_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: SIGNB_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: SIGNB_PIPE_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: SIGNB_PIPE_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: SIGNB_PIPE_REG STRING "1"
// Retrieval info: PRIVATE: SIGNB_REG STRING "1"
// Retrieval info: PRIVATE: SRCA0 STRING "Multiplier input"
// Retrieval info: PRIVATE: SRCB0 STRING "Multiplier input"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: WIDTHA STRING "17"
// Retrieval info: PRIVATE: WIDTHB STRING "16"
// Retrieval info: PRIVATE: ZERO_CHAINOUT_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ZERO_CHAINOUT_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_CHAINOUT_REG STRING "0"
// Retrieval info: PRIVATE: ZERO_LOOPBACK_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ZERO_LOOPBACK_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_LOOPBACK_OUT_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ZERO_LOOPBACK_OUT_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_LOOPBACK_OUT_REG STRING "1"
// Retrieval info: PRIVATE: ZERO_LOOPBACK_PIPE_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ZERO_LOOPBACK_PIPE_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_LOOPBACK_PIPE_REG STRING "1"
// Retrieval info: PRIVATE: ZERO_LOOPBACK_REG STRING "1"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ACCUMULATOR STRING "NO"
// Retrieval info: CONSTANT: ADDNSUB_MULTIPLIER_ACLR1 STRING "UNUSED"
// Retrieval info: CONSTANT: ADDNSUB_MULTIPLIER_PIPELINE_ACLR1 STRING "UNUSED"
// Retrieval info: CONSTANT: ADDNSUB_MULTIPLIER_PIPELINE_REGISTER1 STRING "CLOCK0"
// Retrieval info: CONSTANT: ADDNSUB_MULTIPLIER_REGISTER1 STRING "CLOCK0"
// Retrieval info: CONSTANT: CHAINOUT_ADDER STRING "NO"
// Retrieval info: CONSTANT: CHAINOUT_REGISTER STRING "UNREGISTERED"
// Retrieval info: CONSTANT: DEDICATED_MULTIPLIER_CIRCUITRY STRING "YES"
// Retrieval info: CONSTANT: INPUT_ACLR_A0 STRING "UNUSED"
// Retrieval info: CONSTANT: INPUT_ACLR_A1 STRING "UNUSED"
// Retrieval info: CONSTANT: INPUT_ACLR_B0 STRING "UNUSED"
// Retrieval info: CONSTANT: INPUT_ACLR_B1 STRING "UNUSED"
// Retrieval info: CONSTANT: INPUT_REGISTER_A0 STRING "CLOCK0"
// Retrieval info: CONSTANT: INPUT_REGISTER_A1 STRING "CLOCK0"
// Retrieval info: CONSTANT: INPUT_REGISTER_B0 STRING "CLOCK0"
// Retrieval info: CONSTANT: INPUT_REGISTER_B1 STRING "CLOCK0"
// Retrieval info: CONSTANT: INPUT_SOURCE_A0 STRING "DATAA"
// Retrieval info: CONSTANT: INPUT_SOURCE_A1 STRING "DATAA"
// Retrieval info: CONSTANT: INPUT_SOURCE_B0 STRING "DATAB"
// Retrieval info: CONSTANT: INPUT_SOURCE_B1 STRING "DATAB"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altmult_add"
// Retrieval info: CONSTANT: MULTIPLIER1_DIRECTION STRING "ADD"
// Retrieval info: CONSTANT: MULTIPLIER_ACLR0 STRING "UNUSED"
// Retrieval info: CONSTANT: MULTIPLIER_ACLR1 STRING "UNUSED"
// Retrieval info: CONSTANT: MULTIPLIER_REGISTER0 STRING "CLOCK0"
// Retrieval info: CONSTANT: MULTIPLIER_REGISTER1 STRING "CLOCK0"
// Retrieval info: CONSTANT: NUMBER_OF_MULTIPLIERS NUMERIC "2"
// Retrieval info: CONSTANT: OUTPUT_ACLR STRING "UNUSED"
// Retrieval info: CONSTANT: OUTPUT_REGISTER STRING "CLOCK0"
// Retrieval info: CONSTANT: PORT_ADDNSUB1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SIGNA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SIGNB STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: REPRESENTATION_A STRING "SIGNED"
// Retrieval info: CONSTANT: REPRESENTATION_B STRING "SIGNED"
// Retrieval info: CONSTANT: SIGNED_ACLR_A STRING "UNUSED"
// Retrieval info: CONSTANT: SIGNED_ACLR_B STRING "UNUSED"
// Retrieval info: CONSTANT: SIGNED_PIPELINE_ACLR_A STRING "UNUSED"
// Retrieval info: CONSTANT: SIGNED_PIPELINE_ACLR_B STRING "UNUSED"
// Retrieval info: CONSTANT: SIGNED_PIPELINE_REGISTER_A STRING "CLOCK0"
// Retrieval info: CONSTANT: SIGNED_PIPELINE_REGISTER_B STRING "CLOCK0"
// Retrieval info: CONSTANT: SIGNED_REGISTER_A STRING "CLOCK0"
// Retrieval info: CONSTANT: SIGNED_REGISTER_B STRING "CLOCK0"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "17"
// Retrieval info: CONSTANT: WIDTH_B NUMERIC "16"
// Retrieval info: CONSTANT: WIDTH_CHAININ NUMERIC "1"
// Retrieval info: CONSTANT: WIDTH_RESULT NUMERIC "35"
// Retrieval info: CONSTANT: ZERO_CHAINOUT_OUTPUT_REGISTER STRING "UNREGISTERED"
// Retrieval info: CONSTANT: ZERO_LOOPBACK_ACLR STRING "UNUSED"
// Retrieval info: CONSTANT: ZERO_LOOPBACK_OUTPUT_ACLR STRING "UNUSED"
// Retrieval info: CONSTANT: ZERO_LOOPBACK_OUTPUT_REGISTER STRING "CLOCK0"
// Retrieval info: CONSTANT: ZERO_LOOPBACK_PIPELINE_ACLR STRING "UNUSED"
// Retrieval info: CONSTANT: ZERO_LOOPBACK_PIPELINE_REGISTER STRING "CLOCK0"
// Retrieval info: CONSTANT: ZERO_LOOPBACK_REGISTER STRING "CLOCK0"
// Retrieval info: USED_PORT: clock0 0 0 0 0 INPUT VCC "clock0"
// Retrieval info: USED_PORT: dataa_0 0 0 17 0 INPUT GND "dataa_0[16..0]"
// Retrieval info: USED_PORT: dataa_1 0 0 17 0 INPUT GND "dataa_1[16..0]"
// Retrieval info: USED_PORT: datab_0 0 0 16 0 INPUT GND "datab_0[15..0]"
// Retrieval info: USED_PORT: datab_1 0 0 16 0 INPUT GND "datab_1[15..0]"
// Retrieval info: USED_PORT: ena0 0 0 0 0 INPUT VCC "ena0"
// Retrieval info: USED_PORT: result 0 0 35 0 OUTPUT GND "result[34..0]"
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock0 0 0 0 0
// Retrieval info: CONNECT: @dataa 0 0 17 0 dataa_0 0 0 17 0
// Retrieval info: CONNECT: @dataa 0 0 17 17 dataa_1 0 0 17 0
// Retrieval info: CONNECT: @datab 0 0 16 0 datab_0 0 0 16 0
// Retrieval info: CONNECT: @datab 0 0 16 16 datab_1 0 0 16 0
// Retrieval info: CONNECT: @ena0 0 0 0 0 ena0 0 0 0 0
// Retrieval info: CONNECT: result 0 0 35 0 @result 0 0 35 0
// Retrieval info: GEN_FILE: TYPE_NORMAL dsp_2mult_add.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL dsp_2mult_add.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL dsp_2mult_add.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL dsp_2mult_add.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL dsp_2mult_add_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL dsp_2mult_add_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
// megafunction wizard: %ALTMULT_ADD%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: ALTMULT_ADD
// ============================================================
// File Name: dsp_2mult_add.v
// Megafunction Name(s):
// ALTMULT_ADD
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 12.1 Build 177 11/07/2012 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2012 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module dsp_2mult_add (
clock0,
dataa_0,
dataa_1,
datab_0,
datab_1,
ena0,
result);
input clock0;
input [16:0] dataa_0;
input [16:0] dataa_1;
input [15:0] datab_0;
input [15:0] datab_1;
input ena0;
output [34:0] result;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock0;
tri0 [16:0] dataa_0;
tri0 [16:0] dataa_1;
tri0 [15:0] datab_0;
tri0 [15:0] datab_1;
tri1 ena0;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ACCUM_DIRECTION STRING "Add"
// Retrieval info: PRIVATE: ACCUM_SLOAD_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ACCUM_SLOAD_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ACCUM_SLOAD_PIPE_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ACCUM_SLOAD_PIPE_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ACCUM_SLOAD_PIPE_REG STRING "1"
// Retrieval info: PRIVATE: ACCUM_SLOAD_REG STRING "1"
// Retrieval info: PRIVATE: ADDNSUB1_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ADDNSUB1_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ADDNSUB1_PIPE_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ADDNSUB1_PIPE_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ADDNSUB1_PIPE_REG STRING "1"
// Retrieval info: PRIVATE: ADDNSUB1_REG STRING "1"
// Retrieval info: PRIVATE: ADDNSUB3_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ADDNSUB3_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ADDNSUB3_PIPE_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ADDNSUB3_PIPE_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ADDNSUB3_PIPE_REG STRING "1"
// Retrieval info: PRIVATE: ADDNSUB3_REG STRING "1"
// Retrieval info: PRIVATE: ADD_ENABLE NUMERIC "1"
// Retrieval info: PRIVATE: ALL_REG_ACLR NUMERIC "0"
// Retrieval info: PRIVATE: A_ACLR_SRC_MULT0 NUMERIC "3"
// Retrieval info: PRIVATE: A_CLK_SRC_MULT0 NUMERIC "0"
// Retrieval info: PRIVATE: B_ACLR_SRC_MULT0 NUMERIC "3"
// Retrieval info: PRIVATE: B_CLK_SRC_MULT0 NUMERIC "0"
// Retrieval info: PRIVATE: CHAINOUT_OUTPUT_ACLR NUMERIC "3"
// Retrieval info: PRIVATE: CHAINOUT_OUTPUT_REG STRING "0"
// Retrieval info: PRIVATE: CHAINOUT_OUTPUT_REGISTER NUMERIC "0"
// Retrieval info: PRIVATE: CHAINOUT_OUTPUT_REGISTERED NUMERIC "0"
// Retrieval info: PRIVATE: CHAS_ZERO_CHAINOUT NUMERIC "0"
// Retrieval info: PRIVATE: HAS_ACCUMULATOR NUMERIC "0"
// Retrieval info: PRIVATE: HAS_ACUMM_SLOAD NUMERIC "0"
// Retrieval info: PRIVATE: HAS_CHAININ_PORT NUMERIC "0"
// Retrieval info: PRIVATE: HAS_CHAINOUT_ADDER NUMERIC "0"
// Retrieval info: PRIVATE: HAS_LOOPBACK NUMERIC "0"
// Retrieval info: PRIVATE: HAS_MAC STRING "0"
// Retrieval info: PRIVATE: HAS_SAT_ROUND STRING "0"
// Retrieval info: PRIVATE: HAS_ZERO_LOOPBACK NUMERIC "0"
// Retrieval info: PRIVATE: IMPL_STYLE_DEDICATED NUMERIC "1"
// Retrieval info: PRIVATE: IMPL_STYLE_DEFAULT NUMERIC "0"
// Retrieval info: PRIVATE: IMPL_STYLE_LCELL NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
// Retrieval info: PRIVATE: MULT_REGA0 NUMERIC "1"
// Retrieval info: PRIVATE: MULT_REGB0 NUMERIC "1"
// Retrieval info: PRIVATE: MULT_REGOUT0 NUMERIC "1"
// Retrieval info: PRIVATE: NUM_MULT STRING "2"
// Retrieval info: PRIVATE: OP1 STRING "Add"
// Retrieval info: PRIVATE: OP3 STRING "Add"
// Retrieval info: PRIVATE: OUTPUT_EXTRA_LAT NUMERIC "0"
// Retrieval info: PRIVATE: OUTPUT_REG_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: OUTPUT_REG_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: Q_ACLR_SRC_MULT0 NUMERIC "3"
// Retrieval info: PRIVATE: Q_CLK_SRC_MULT0 NUMERIC "0"
// Retrieval info: PRIVATE: REG_OUT NUMERIC "1"
// Retrieval info: PRIVATE: RNFORMAT STRING "35"
// Retrieval info: PRIVATE: ROTATE_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ROTATE_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ROTATE_OUT_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ROTATE_OUT_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ROTATE_OUT_REG STRING "1"
// Retrieval info: PRIVATE: ROTATE_PIPE_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ROTATE_PIPE_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ROTATE_PIPE_REG STRING "1"
// Retrieval info: PRIVATE: ROTATE_REG STRING "1"
// Retrieval info: PRIVATE: ROUND3_CHAINOUT_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ROUND3_CHAINOUT_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ROUND3_CHAINOUT_MODE STRING "Enabled"
// Retrieval info: PRIVATE: ROUND3_CHAINOUT_OUT_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ROUND3_CHAINOUT_OUT_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ROUND3_CHAINOUT_OUT_REG STRING "1"
// Retrieval info: PRIVATE: ROUND3_CHAINOUT_PIPE_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ROUND3_CHAINOUT_PIPE_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ROUND3_CHAINOUT_PIPE_REG STRING "1"
// Retrieval info: PRIVATE: ROUND3_CHAINOUT_REG STRING "1"
// Retrieval info: PRIVATE: ROUND3_FRAC_WIDTH NUMERIC "27"
// Retrieval info: PRIVATE: ROUND3_OUTPUT_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ROUND3_OUTPUT_CHAINOUT_TYPE STRING "Nearest Integer"
// Retrieval info: PRIVATE: ROUND3_OUTPUT_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ROUND3_OUTPUT_MODE STRING "Disabled"
// Retrieval info: PRIVATE: ROUND3_OUTPUT_PIPE_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ROUND3_OUTPUT_PIPE_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ROUND3_OUTPUT_PIPE_REG STRING "1"
// Retrieval info: PRIVATE: ROUND3_OUTPUT_REG STRING "1"
// Retrieval info: PRIVATE: RQFORMAT STRING "Q1.15"
// Retrieval info: PRIVATE: RTS_WIDTH STRING "35"
// Retrieval info: PRIVATE: SAME_CONFIG NUMERIC "1"
// Retrieval info: PRIVATE: SAME_CONTROL_SRC_A0 NUMERIC "1"
// Retrieval info: PRIVATE: SAME_CONTROL_SRC_B0 NUMERIC "1"
// Retrieval info: PRIVATE: SAT3_CHAINOUT_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: SAT3_CHAINOUT_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: SAT3_CHAINOUT_MODE STRING "Enabled"
// Retrieval info: PRIVATE: SAT3_CHAINOUT_OUT_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: SAT3_CHAINOUT_OUT_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: SAT3_CHAINOUT_PIPE_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: SAT3_CHAINOUT_PIPE_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: SAT3_CHAINOUT_PIPE_REG STRING "1"
// Retrieval info: PRIVATE: SAT3_CHAINOUT_REG STRING "1"
// Retrieval info: PRIVATE: SAT3_FRAC_WIDTH NUMERIC "5"
// Retrieval info: PRIVATE: SAT3_OUTPUT_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: SAT3_OUTPUT_CHAINOUT_TYPE STRING "Asymmetric"
// Retrieval info: PRIVATE: SAT3_OUTPUT_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: SAT3_OUTPUT_MODE STRING "Enabled"
// Retrieval info: PRIVATE: SAT3_OUTPUT_OVERFLOW NUMERIC "0"
// Retrieval info: PRIVATE: SAT3_OUTPUT_PIPE_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: SAT3_OUTPUT_PIPE_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: SAT3_OUTPUT_PIPE_REG STRING "1"
// Retrieval info: PRIVATE: SAT3_OUTPUT_REG STRING "1"
// Retrieval info: PRIVATE: SCANOUTA NUMERIC "0"
// Retrieval info: PRIVATE: SCANOUTB NUMERIC "0"
// Retrieval info: PRIVATE: SHIFTOUTA_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: SHIFTOUTA_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: SHIFTOUTA_REG STRING "0"
// Retrieval info: PRIVATE: SHIFT_RIGHT_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: SHIFT_RIGHT_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: SHIFT_RIGHT_OUT_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: SHIFT_RIGHT_OUT_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: SHIFT_RIGHT_OUT_REG STRING "1"
// Retrieval info: PRIVATE: SHIFT_RIGHT_PIPE_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: SHIFT_RIGHT_PIPE_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: SHIFT_RIGHT_PIPE_REG STRING "1"
// Retrieval info: PRIVATE: SHIFT_RIGHT_REG STRING "1"
// Retrieval info: PRIVATE: SHIFT_ROTATE_MODE STRING "None"
// Retrieval info: PRIVATE: SIGNA STRING "SIGNED"
// Retrieval info: PRIVATE: SIGNA_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: SIGNA_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: SIGNA_PIPE_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: SIGNA_PIPE_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: SIGNA_PIPE_REG STRING "1"
// Retrieval info: PRIVATE: SIGNA_REG STRING "1"
// Retrieval info: PRIVATE: SIGNB STRING "SIGNED"
// Retrieval info: PRIVATE: SIGNB_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: SIGNB_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: SIGNB_PIPE_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: SIGNB_PIPE_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: SIGNB_PIPE_REG STRING "1"
// Retrieval info: PRIVATE: SIGNB_REG STRING "1"
// Retrieval info: PRIVATE: SRCA0 STRING "Multiplier input"
// Retrieval info: PRIVATE: SRCB0 STRING "Multiplier input"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: WIDTHA STRING "17"
// Retrieval info: PRIVATE: WIDTHB STRING "16"
// Retrieval info: PRIVATE: ZERO_CHAINOUT_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ZERO_CHAINOUT_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_CHAINOUT_REG STRING "0"
// Retrieval info: PRIVATE: ZERO_LOOPBACK_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ZERO_LOOPBACK_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_LOOPBACK_OUT_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ZERO_LOOPBACK_OUT_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_LOOPBACK_OUT_REG STRING "1"
// Retrieval info: PRIVATE: ZERO_LOOPBACK_PIPE_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ZERO_LOOPBACK_PIPE_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_LOOPBACK_PIPE_REG STRING "1"
// Retrieval info: PRIVATE: ZERO_LOOPBACK_REG STRING "1"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ACCUMULATOR STRING "NO"
// Retrieval info: CONSTANT: ADDNSUB_MULTIPLIER_ACLR1 STRING "UNUSED"
// Retrieval info: CONSTANT: ADDNSUB_MULTIPLIER_PIPELINE_ACLR1 STRING "UNUSED"
// Retrieval info: CONSTANT: ADDNSUB_MULTIPLIER_PIPELINE_REGISTER1 STRING "CLOCK0"
// Retrieval info: CONSTANT: ADDNSUB_MULTIPLIER_REGISTER1 STRING "CLOCK0"
// Retrieval info: CONSTANT: CHAINOUT_ADDER STRING "NO"
// Retrieval info: CONSTANT: CHAINOUT_REGISTER STRING "UNREGISTERED"
// Retrieval info: CONSTANT: DEDICATED_MULTIPLIER_CIRCUITRY STRING "YES"
// Retrieval info: CONSTANT: INPUT_ACLR_A0 STRING "UNUSED"
// Retrieval info: CONSTANT: INPUT_ACLR_A1 STRING "UNUSED"
// Retrieval info: CONSTANT: INPUT_ACLR_B0 STRING "UNUSED"
// Retrieval info: CONSTANT: INPUT_ACLR_B1 STRING "UNUSED"
// Retrieval info: CONSTANT: INPUT_REGISTER_A0 STRING "CLOCK0"
// Retrieval info: CONSTANT: INPUT_REGISTER_A1 STRING "CLOCK0"
// Retrieval info: CONSTANT: INPUT_REGISTER_B0 STRING "CLOCK0"
// Retrieval info: CONSTANT: INPUT_REGISTER_B1 STRING "CLOCK0"
// Retrieval info: CONSTANT: INPUT_SOURCE_A0 STRING "DATAA"
// Retrieval info: CONSTANT: INPUT_SOURCE_A1 STRING "DATAA"
// Retrieval info: CONSTANT: INPUT_SOURCE_B0 STRING "DATAB"
// Retrieval info: CONSTANT: INPUT_SOURCE_B1 STRING "DATAB"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altmult_add"
// Retrieval info: CONSTANT: MULTIPLIER1_DIRECTION STRING "ADD"
// Retrieval info: CONSTANT: MULTIPLIER_ACLR0 STRING "UNUSED"
// Retrieval info: CONSTANT: MULTIPLIER_ACLR1 STRING "UNUSED"
// Retrieval info: CONSTANT: MULTIPLIER_REGISTER0 STRING "CLOCK0"
// Retrieval info: CONSTANT: MULTIPLIER_REGISTER1 STRING "CLOCK0"
// Retrieval info: CONSTANT: NUMBER_OF_MULTIPLIERS NUMERIC "2"
// Retrieval info: CONSTANT: OUTPUT_ACLR STRING "UNUSED"
// Retrieval info: CONSTANT: OUTPUT_REGISTER STRING "CLOCK0"
// Retrieval info: CONSTANT: PORT_ADDNSUB1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SIGNA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SIGNB STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: REPRESENTATION_A STRING "SIGNED"
// Retrieval info: CONSTANT: REPRESENTATION_B STRING "SIGNED"
// Retrieval info: CONSTANT: SIGNED_ACLR_A STRING "UNUSED"
// Retrieval info: CONSTANT: SIGNED_ACLR_B STRING "UNUSED"
// Retrieval info: CONSTANT: SIGNED_PIPELINE_ACLR_A STRING "UNUSED"
// Retrieval info: CONSTANT: SIGNED_PIPELINE_ACLR_B STRING "UNUSED"
// Retrieval info: CONSTANT: SIGNED_PIPELINE_REGISTER_A STRING "CLOCK0"
// Retrieval info: CONSTANT: SIGNED_PIPELINE_REGISTER_B STRING "CLOCK0"
// Retrieval info: CONSTANT: SIGNED_REGISTER_A STRING "CLOCK0"
// Retrieval info: CONSTANT: SIGNED_REGISTER_B STRING "CLOCK0"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "17"
// Retrieval info: CONSTANT: WIDTH_B NUMERIC "16"
// Retrieval info: CONSTANT: WIDTH_CHAININ NUMERIC "1"
// Retrieval info: CONSTANT: WIDTH_RESULT NUMERIC "35"
// Retrieval info: CONSTANT: ZERO_CHAINOUT_OUTPUT_REGISTER STRING "UNREGISTERED"
// Retrieval info: CONSTANT: ZERO_LOOPBACK_ACLR STRING "UNUSED"
// Retrieval info: CONSTANT: ZERO_LOOPBACK_OUTPUT_ACLR STRING "UNUSED"
// Retrieval info: CONSTANT: ZERO_LOOPBACK_OUTPUT_REGISTER STRING "CLOCK0"
// Retrieval info: CONSTANT: ZERO_LOOPBACK_PIPELINE_ACLR STRING "UNUSED"
// Retrieval info: CONSTANT: ZERO_LOOPBACK_PIPELINE_REGISTER STRING "CLOCK0"
// Retrieval info: CONSTANT: ZERO_LOOPBACK_REGISTER STRING "CLOCK0"
// Retrieval info: USED_PORT: clock0 0 0 0 0 INPUT VCC "clock0"
// Retrieval info: USED_PORT: dataa_0 0 0 17 0 INPUT GND "dataa_0[16..0]"
// Retrieval info: USED_PORT: dataa_1 0 0 17 0 INPUT GND "dataa_1[16..0]"
// Retrieval info: USED_PORT: datab_0 0 0 16 0 INPUT GND "datab_0[15..0]"
// Retrieval info: USED_PORT: datab_1 0 0 16 0 INPUT GND "datab_1[15..0]"
// Retrieval info: USED_PORT: ena0 0 0 0 0 INPUT VCC "ena0"
// Retrieval info: USED_PORT: result 0 0 35 0 OUTPUT GND "result[34..0]"
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock0 0 0 0 0
// Retrieval info: CONNECT: @dataa 0 0 17 0 dataa_0 0 0 17 0
// Retrieval info: CONNECT: @dataa 0 0 17 17 dataa_1 0 0 17 0
// Retrieval info: CONNECT: @datab 0 0 16 0 datab_0 0 0 16 0
// Retrieval info: CONNECT: @datab 0 0 16 16 datab_1 0 0 16 0
// Retrieval info: CONNECT: @ena0 0 0 0 0 ena0 0 0 0 0
// Retrieval info: CONNECT: result 0 0 35 0 @result 0 0 35 0
// Retrieval info: GEN_FILE: TYPE_NORMAL dsp_2mult_add.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL dsp_2mult_add.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL dsp_2mult_add.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL dsp_2mult_add.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL dsp_2mult_add_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL dsp_2mult_add_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
dsp_2mult_add dsp_2mult_add_inst (
.clock0 ( clock0_sig ),
.dataa_0 ( dataa_0_sig ),
.dataa_1 ( dataa_1_sig ),
.datab_0 ( datab_0_sig ),
.datab_1 ( datab_1_sig ),
.ena0 ( ena0_sig ),
.result ( result_sig )
);
|
// megafunction wizard: %ALTMULT_ADD%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: ALTMULT_ADD
// ============================================================
// File Name: dsp_4mult_add.v
// Megafunction Name(s):
// ALTMULT_ADD
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 12.1 Build 177 11/07/2012 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2012 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module dsp_4mult_add (
chainin,
clock0,
dataa_0,
dataa_1,
dataa_2,
dataa_3,
datab_0,
datab_1,
datab_2,
datab_3,
ena0,
result);
input [43:0] chainin;
input clock0;
input [16:0] dataa_0;
input [16:0] dataa_1;
input [16:0] dataa_2;
input [16:0] dataa_3;
input [15:0] datab_0;
input [15:0] datab_1;
input [15:0] datab_2;
input [15:0] datab_3;
input ena0;
output [43:0] result;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 [43:0] chainin;
tri1 clock0;
tri0 [16:0] dataa_0;
tri0 [16:0] dataa_1;
tri0 [16:0] dataa_2;
tri0 [16:0] dataa_3;
tri0 [15:0] datab_0;
tri0 [15:0] datab_1;
tri0 [15:0] datab_2;
tri0 [15:0] datab_3;
tri1 ena0;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [43:0] sub_wire0;
wire [16:0] sub_wire10 = dataa_3[16:0];
wire [16:0] sub_wire9 = dataa_2[16:0];
wire [16:0] sub_wire8 = dataa_1[16:0];
wire [15:0] sub_wire5 = datab_3[15:0];
wire [15:0] sub_wire4 = datab_2[15:0];
wire [15:0] sub_wire3 = datab_1[15:0];
wire [43:0] result = sub_wire0[43:0];
wire [15:0] sub_wire1 = datab_0[15:0];
wire [63:0] sub_wire2 = {sub_wire5, sub_wire4, sub_wire3, sub_wire1};
wire [16:0] sub_wire6 = dataa_0[16:0];
wire [67:0] sub_wire7 = {sub_wire10, sub_wire9, sub_wire8, sub_wire6};
altmult_add ALTMULT_ADD_component (
.chainin (chainin),
.clock0 (clock0),
.datab (sub_wire2),
.ena0 (ena0),
.dataa (sub_wire7),
.result (sub_wire0),
.accum_sload (1'b0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.aclr2 (1'b0),
.aclr3 (1'b0),
.addnsub1 (1'b1),
.addnsub1_round (1'b0),
.addnsub3 (1'b1),
.addnsub3_round (1'b0),
.chainout_round (1'b0),
.chainout_sat_overflow (),
.chainout_saturate (1'b0),
.clock1 (1'b1),
.clock2 (1'b1),
.clock3 (1'b1),
.coefsel0 ({3{1'b0}}),
.coefsel1 ({3{1'b0}}),
.coefsel2 ({3{1'b0}}),
.coefsel3 ({3{1'b0}}),
.datac ({88{1'b0}}),
.ena1 (1'b1),
.ena2 (1'b1),
.ena3 (1'b1),
.mult01_round (1'b0),
.mult01_saturation (1'b0),
.mult0_is_saturated (),
.mult1_is_saturated (),
.mult23_round (1'b0),
.mult23_saturation (1'b0),
.mult2_is_saturated (),
.mult3_is_saturated (),
.output_round (1'b0),
.output_saturate (1'b0),
.overflow (),
.rotate (1'b0),
.scanina ({17{1'b0}}),
.scaninb ({16{1'b0}}),
.scanouta (),
.scanoutb (),
.shift_right (1'b0),
.signa (1'b0),
.signb (1'b0),
.sourcea ({4{1'b0}}),
.sourceb ({4{1'b0}}),
.zero_chainout (1'b0),
.zero_loopback (1'b0));
defparam
ALTMULT_ADD_component.accumulator = "NO",
ALTMULT_ADD_component.addnsub_multiplier_aclr1 = "UNUSED",
ALTMULT_ADD_component.addnsub_multiplier_aclr3 = "UNUSED",
ALTMULT_ADD_component.addnsub_multiplier_pipeline_aclr1 = "UNUSED",
ALTMULT_ADD_component.addnsub_multiplier_pipeline_aclr3 = "UNUSED",
ALTMULT_ADD_component.addnsub_multiplier_pipeline_register1 = "CLOCK0",
ALTMULT_ADD_component.addnsub_multiplier_pipeline_register3 = "CLOCK0",
ALTMULT_ADD_component.addnsub_multiplier_register1 = "CLOCK0",
ALTMULT_ADD_component.addnsub_multiplier_register3 = "CLOCK0",
ALTMULT_ADD_component.chainout_aclr = "UNUSED",
ALTMULT_ADD_component.chainout_adder = "YES",
ALTMULT_ADD_component.chainout_register = "CLOCK0",
ALTMULT_ADD_component.dedicated_multiplier_circuitry = "YES",
ALTMULT_ADD_component.input_aclr_a0 = "UNUSED",
ALTMULT_ADD_component.input_aclr_a1 = "UNUSED",
ALTMULT_ADD_component.input_aclr_a2 = "UNUSED",
ALTMULT_ADD_component.input_aclr_a3 = "UNUSED",
ALTMULT_ADD_component.input_aclr_b0 = "UNUSED",
ALTMULT_ADD_component.input_aclr_b1 = "UNUSED",
ALTMULT_ADD_component.input_aclr_b2 = "UNUSED",
ALTMULT_ADD_component.input_aclr_b3 = "UNUSED",
ALTMULT_ADD_component.input_register_a0 = "CLOCK0",
ALTMULT_ADD_component.input_register_a1 = "CLOCK0",
ALTMULT_ADD_component.input_register_a2 = "CLOCK0",
ALTMULT_ADD_component.input_register_a3 = "CLOCK0",
ALTMULT_ADD_component.input_register_b0 = "CLOCK0",
ALTMULT_ADD_component.input_register_b1 = "CLOCK0",
ALTMULT_ADD_component.input_register_b2 = "CLOCK0",
ALTMULT_ADD_component.input_register_b3 = "CLOCK0",
ALTMULT_ADD_component.input_source_a0 = "DATAA",
ALTMULT_ADD_component.input_source_a1 = "DATAA",
ALTMULT_ADD_component.input_source_a2 = "DATAA",
ALTMULT_ADD_component.input_source_a3 = "DATAA",
ALTMULT_ADD_component.input_source_b0 = "DATAB",
ALTMULT_ADD_component.input_source_b1 = "DATAB",
ALTMULT_ADD_component.input_source_b2 = "DATAB",
ALTMULT_ADD_component.input_source_b3 = "DATAB",
ALTMULT_ADD_component.intended_device_family = "Stratix IV",
ALTMULT_ADD_component.lpm_type = "altmult_add",
ALTMULT_ADD_component.multiplier1_direction = "ADD",
ALTMULT_ADD_component.multiplier3_direction = "ADD",
ALTMULT_ADD_component.multiplier_aclr0 = "UNUSED",
ALTMULT_ADD_component.multiplier_aclr1 = "UNUSED",
ALTMULT_ADD_component.multiplier_aclr2 = "UNUSED",
ALTMULT_ADD_component.multiplier_aclr3 = "UNUSED",
ALTMULT_ADD_component.multiplier_register0 = "CLOCK0",
ALTMULT_ADD_component.multiplier_register1 = "CLOCK0",
ALTMULT_ADD_component.multiplier_register2 = "CLOCK0",
ALTMULT_ADD_component.multiplier_register3 = "CLOCK0",
ALTMULT_ADD_component.number_of_multipliers = 4,
ALTMULT_ADD_component.output_aclr = "UNUSED",
ALTMULT_ADD_component.output_register = "CLOCK0",
ALTMULT_ADD_component.port_addnsub1 = "PORT_UNUSED",
ALTMULT_ADD_component.port_addnsub3 = "PORT_UNUSED",
ALTMULT_ADD_component.port_signa = "PORT_UNUSED",
ALTMULT_ADD_component.port_signb = "PORT_UNUSED",
ALTMULT_ADD_component.representation_a = "SIGNED",
ALTMULT_ADD_component.representation_b = "SIGNED",
ALTMULT_ADD_component.signed_aclr_a = "UNUSED",
ALTMULT_ADD_component.signed_aclr_b = "UNUSED",
ALTMULT_ADD_component.signed_pipeline_aclr_a = "UNUSED",
ALTMULT_ADD_component.signed_pipeline_aclr_b = "UNUSED",
ALTMULT_ADD_component.signed_pipeline_register_a = "CLOCK0",
ALTMULT_ADD_component.signed_pipeline_register_b = "CLOCK0",
ALTMULT_ADD_component.signed_register_a = "CLOCK0",
ALTMULT_ADD_component.signed_register_b = "CLOCK0",
ALTMULT_ADD_component.width_a = 17,
ALTMULT_ADD_component.width_b = 16,
ALTMULT_ADD_component.width_chainin = 44,
ALTMULT_ADD_component.width_result = 44,
ALTMULT_ADD_component.zero_chainout_output_register = "UNREGISTERED",
ALTMULT_ADD_component.zero_loopback_aclr = "UNUSED",
ALTMULT_ADD_component.zero_loopback_output_aclr = "UNUSED",
ALTMULT_ADD_component.zero_loopback_output_register = "CLOCK0",
ALTMULT_ADD_component.zero_loopback_pipeline_aclr = "UNUSED",
ALTMULT_ADD_component.zero_loopback_pipeline_register = "CLOCK0",
ALTMULT_ADD_component.zero_loopback_register = "CLOCK0";
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ACCUM_DIRECTION STRING "Add"
// Retrieval info: PRIVATE: ACCUM_SLOAD_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ACCUM_SLOAD_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ACCUM_SLOAD_PIPE_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ACCUM_SLOAD_PIPE_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ACCUM_SLOAD_PIPE_REG STRING "1"
// Retrieval info: PRIVATE: ACCUM_SLOAD_REG STRING "1"
// Retrieval info: PRIVATE: ADDNSUB1_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ADDNSUB1_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ADDNSUB1_PIPE_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ADDNSUB1_PIPE_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ADDNSUB1_PIPE_REG STRING "1"
// Retrieval info: PRIVATE: ADDNSUB1_REG STRING "1"
// Retrieval info: PRIVATE: ADDNSUB3_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ADDNSUB3_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ADDNSUB3_PIPE_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ADDNSUB3_PIPE_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ADDNSUB3_PIPE_REG STRING "1"
// Retrieval info: PRIVATE: ADDNSUB3_REG STRING "1"
// Retrieval info: PRIVATE: ADD_ENABLE NUMERIC "1"
// Retrieval info: PRIVATE: ALL_REG_ACLR NUMERIC "0"
// Retrieval info: PRIVATE: A_ACLR_SRC_MULT0 NUMERIC "3"
// Retrieval info: PRIVATE: A_CLK_SRC_MULT0 NUMERIC "0"
// Retrieval info: PRIVATE: B_ACLR_SRC_MULT0 NUMERIC "3"
// Retrieval info: PRIVATE: B_CLK_SRC_MULT0 NUMERIC "0"
// Retrieval info: PRIVATE: CHAINOUT_OUTPUT_ACLR NUMERIC "3"
// Retrieval info: PRIVATE: CHAINOUT_OUTPUT_REG STRING "1"
// Retrieval info: PRIVATE: CHAINOUT_OUTPUT_REGISTER NUMERIC "0"
// Retrieval info: PRIVATE: CHAINOUT_OUTPUT_REGISTERED NUMERIC "1"
// Retrieval info: PRIVATE: CHAS_ZERO_CHAINOUT NUMERIC "0"
// Retrieval info: PRIVATE: HAS_ACCUMULATOR NUMERIC "0"
// Retrieval info: PRIVATE: HAS_ACUMM_SLOAD NUMERIC "0"
// Retrieval info: PRIVATE: HAS_CHAININ_PORT NUMERIC "1"
// Retrieval info: PRIVATE: HAS_CHAINOUT_ADDER NUMERIC "1"
// Retrieval info: PRIVATE: HAS_LOOPBACK NUMERIC "0"
// Retrieval info: PRIVATE: HAS_MAC STRING "0"
// Retrieval info: PRIVATE: HAS_SAT_ROUND STRING "0"
// Retrieval info: PRIVATE: HAS_ZERO_LOOPBACK NUMERIC "0"
// Retrieval info: PRIVATE: IMPL_STYLE_DEDICATED NUMERIC "1"
// Retrieval info: PRIVATE: IMPL_STYLE_DEFAULT NUMERIC "0"
// Retrieval info: PRIVATE: IMPL_STYLE_LCELL NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
// Retrieval info: PRIVATE: MULT_REGA0 NUMERIC "1"
// Retrieval info: PRIVATE: MULT_REGB0 NUMERIC "1"
// Retrieval info: PRIVATE: MULT_REGOUT0 NUMERIC "1"
// Retrieval info: PRIVATE: NUM_MULT STRING "4"
// Retrieval info: PRIVATE: OP1 STRING "Add"
// Retrieval info: PRIVATE: OP3 STRING "Add"
// Retrieval info: PRIVATE: OUTPUT_EXTRA_LAT NUMERIC "0"
// Retrieval info: PRIVATE: OUTPUT_REG_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: OUTPUT_REG_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: Q_ACLR_SRC_MULT0 NUMERIC "3"
// Retrieval info: PRIVATE: Q_CLK_SRC_MULT0 NUMERIC "0"
// Retrieval info: PRIVATE: REG_OUT NUMERIC "1"
// Retrieval info: PRIVATE: RNFORMAT STRING "44"
// Retrieval info: PRIVATE: ROTATE_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ROTATE_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ROTATE_OUT_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ROTATE_OUT_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ROTATE_OUT_REG STRING "1"
// Retrieval info: PRIVATE: ROTATE_PIPE_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ROTATE_PIPE_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ROTATE_PIPE_REG STRING "1"
// Retrieval info: PRIVATE: ROTATE_REG STRING "1"
// Retrieval info: PRIVATE: ROUND3_CHAINOUT_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ROUND3_CHAINOUT_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ROUND3_CHAINOUT_MODE STRING "Enabled"
// Retrieval info: PRIVATE: ROUND3_CHAINOUT_OUT_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ROUND3_CHAINOUT_OUT_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ROUND3_CHAINOUT_OUT_REG STRING "1"
// Retrieval info: PRIVATE: ROUND3_CHAINOUT_PIPE_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ROUND3_CHAINOUT_PIPE_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ROUND3_CHAINOUT_PIPE_REG STRING "1"
// Retrieval info: PRIVATE: ROUND3_CHAINOUT_REG STRING "1"
// Retrieval info: PRIVATE: ROUND3_FRAC_WIDTH NUMERIC "27"
// Retrieval info: PRIVATE: ROUND3_OUTPUT_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ROUND3_OUTPUT_CHAINOUT_TYPE STRING "Nearest Integer"
// Retrieval info: PRIVATE: ROUND3_OUTPUT_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ROUND3_OUTPUT_MODE STRING "Disabled"
// Retrieval info: PRIVATE: ROUND3_OUTPUT_PIPE_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ROUND3_OUTPUT_PIPE_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ROUND3_OUTPUT_PIPE_REG STRING "1"
// Retrieval info: PRIVATE: ROUND3_OUTPUT_REG STRING "1"
// Retrieval info: PRIVATE: RQFORMAT STRING "Q1.15"
// Retrieval info: PRIVATE: RTS_WIDTH STRING "44"
// Retrieval info: PRIVATE: SAME_CONFIG NUMERIC "1"
// Retrieval info: PRIVATE: SAME_CONTROL_SRC_A0 NUMERIC "1"
// Retrieval info: PRIVATE: SAME_CONTROL_SRC_B0 NUMERIC "1"
// Retrieval info: PRIVATE: SAT3_CHAINOUT_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: SAT3_CHAINOUT_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: SAT3_CHAINOUT_MODE STRING "Enabled"
// Retrieval info: PRIVATE: SAT3_CHAINOUT_OUT_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: SAT3_CHAINOUT_OUT_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: SAT3_CHAINOUT_OVERFLOW NUMERIC "0"
// Retrieval info: PRIVATE: SAT3_CHAINOUT_PIPE_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: SAT3_CHAINOUT_PIPE_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: SAT3_CHAINOUT_PIPE_REG STRING "1"
// Retrieval info: PRIVATE: SAT3_CHAINOUT_REG STRING "1"
// Retrieval info: PRIVATE: SAT3_FRAC_WIDTH NUMERIC "2"
// Retrieval info: PRIVATE: SAT3_OUTPUT_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: SAT3_OUTPUT_CHAINOUT_TYPE STRING "Asymmetric"
// Retrieval info: PRIVATE: SAT3_OUTPUT_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: SAT3_OUTPUT_MODE STRING "Enabled"
// Retrieval info: PRIVATE: SAT3_OUTPUT_OVERFLOW NUMERIC "0"
// Retrieval info: PRIVATE: SAT3_OUTPUT_PIPE_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: SAT3_OUTPUT_PIPE_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: SAT3_OUTPUT_PIPE_REG STRING "1"
// Retrieval info: PRIVATE: SAT3_OUTPUT_REG STRING "1"
// Retrieval info: PRIVATE: SCANOUTA NUMERIC "0"
// Retrieval info: PRIVATE: SCANOUTB NUMERIC "0"
// Retrieval info: PRIVATE: SHIFTOUTA_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: SHIFTOUTA_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: SHIFTOUTA_REG STRING "0"
// Retrieval info: PRIVATE: SHIFT_RIGHT_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: SHIFT_RIGHT_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: SHIFT_RIGHT_OUT_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: SHIFT_RIGHT_OUT_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: SHIFT_RIGHT_OUT_REG STRING "1"
// Retrieval info: PRIVATE: SHIFT_RIGHT_PIPE_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: SHIFT_RIGHT_PIPE_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: SHIFT_RIGHT_PIPE_REG STRING "1"
// Retrieval info: PRIVATE: SHIFT_RIGHT_REG STRING "1"
// Retrieval info: PRIVATE: SHIFT_ROTATE_MODE STRING "None"
// Retrieval info: PRIVATE: SIGNA STRING "SIGNED"
// Retrieval info: PRIVATE: SIGNA_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: SIGNA_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: SIGNA_PIPE_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: SIGNA_PIPE_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: SIGNA_PIPE_REG STRING "1"
// Retrieval info: PRIVATE: SIGNA_REG STRING "1"
// Retrieval info: PRIVATE: SIGNB STRING "SIGNED"
// Retrieval info: PRIVATE: SIGNB_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: SIGNB_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: SIGNB_PIPE_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: SIGNB_PIPE_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: SIGNB_PIPE_REG STRING "1"
// Retrieval info: PRIVATE: SIGNB_REG STRING "1"
// Retrieval info: PRIVATE: SRCA0 STRING "Multiplier input"
// Retrieval info: PRIVATE: SRCB0 STRING "Multiplier input"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: WIDTHA STRING "17"
// Retrieval info: PRIVATE: WIDTHB STRING "16"
// Retrieval info: PRIVATE: ZERO_CHAINOUT_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ZERO_CHAINOUT_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_CHAINOUT_REG STRING "0"
// Retrieval info: PRIVATE: ZERO_LOOPBACK_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ZERO_LOOPBACK_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_LOOPBACK_OUT_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ZERO_LOOPBACK_OUT_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_LOOPBACK_OUT_REG STRING "1"
// Retrieval info: PRIVATE: ZERO_LOOPBACK_PIPE_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ZERO_LOOPBACK_PIPE_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_LOOPBACK_PIPE_REG STRING "1"
// Retrieval info: PRIVATE: ZERO_LOOPBACK_REG STRING "1"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ACCUMULATOR STRING "NO"
// Retrieval info: CONSTANT: ADDNSUB_MULTIPLIER_ACLR1 STRING "UNUSED"
// Retrieval info: CONSTANT: ADDNSUB_MULTIPLIER_ACLR3 STRING "UNUSED"
// Retrieval info: CONSTANT: ADDNSUB_MULTIPLIER_PIPELINE_ACLR1 STRING "UNUSED"
// Retrieval info: CONSTANT: ADDNSUB_MULTIPLIER_PIPELINE_ACLR3 STRING "UNUSED"
// Retrieval info: CONSTANT: ADDNSUB_MULTIPLIER_PIPELINE_REGISTER1 STRING "CLOCK0"
// Retrieval info: CONSTANT: ADDNSUB_MULTIPLIER_PIPELINE_REGISTER3 STRING "CLOCK0"
// Retrieval info: CONSTANT: ADDNSUB_MULTIPLIER_REGISTER1 STRING "CLOCK0"
// Retrieval info: CONSTANT: ADDNSUB_MULTIPLIER_REGISTER3 STRING "CLOCK0"
// Retrieval info: CONSTANT: CHAINOUT_ACLR STRING "UNUSED"
// Retrieval info: CONSTANT: CHAINOUT_ADDER STRING "YES"
// Retrieval info: CONSTANT: CHAINOUT_REGISTER STRING "CLOCK0"
// Retrieval info: CONSTANT: DEDICATED_MULTIPLIER_CIRCUITRY STRING "YES"
// Retrieval info: CONSTANT: INPUT_ACLR_A0 STRING "UNUSED"
// Retrieval info: CONSTANT: INPUT_ACLR_A1 STRING "UNUSED"
// Retrieval info: CONSTANT: INPUT_ACLR_A2 STRING "UNUSED"
// Retrieval info: CONSTANT: INPUT_ACLR_A3 STRING "UNUSED"
// Retrieval info: CONSTANT: INPUT_ACLR_B0 STRING "UNUSED"
// Retrieval info: CONSTANT: INPUT_ACLR_B1 STRING "UNUSED"
// Retrieval info: CONSTANT: INPUT_ACLR_B2 STRING "UNUSED"
// Retrieval info: CONSTANT: INPUT_ACLR_B3 STRING "UNUSED"
// Retrieval info: CONSTANT: INPUT_REGISTER_A0 STRING "CLOCK0"
// Retrieval info: CONSTANT: INPUT_REGISTER_A1 STRING "CLOCK0"
// Retrieval info: CONSTANT: INPUT_REGISTER_A2 STRING "CLOCK0"
// Retrieval info: CONSTANT: INPUT_REGISTER_A3 STRING "CLOCK0"
// Retrieval info: CONSTANT: INPUT_REGISTER_B0 STRING "CLOCK0"
// Retrieval info: CONSTANT: INPUT_REGISTER_B1 STRING "CLOCK0"
// Retrieval info: CONSTANT: INPUT_REGISTER_B2 STRING "CLOCK0"
// Retrieval info: CONSTANT: INPUT_REGISTER_B3 STRING "CLOCK0"
// Retrieval info: CONSTANT: INPUT_SOURCE_A0 STRING "DATAA"
// Retrieval info: CONSTANT: INPUT_SOURCE_A1 STRING "DATAA"
// Retrieval info: CONSTANT: INPUT_SOURCE_A2 STRING "DATAA"
// Retrieval info: CONSTANT: INPUT_SOURCE_A3 STRING "DATAA"
// Retrieval info: CONSTANT: INPUT_SOURCE_B0 STRING "DATAB"
// Retrieval info: CONSTANT: INPUT_SOURCE_B1 STRING "DATAB"
// Retrieval info: CONSTANT: INPUT_SOURCE_B2 STRING "DATAB"
// Retrieval info: CONSTANT: INPUT_SOURCE_B3 STRING "DATAB"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altmult_add"
// Retrieval info: CONSTANT: MULTIPLIER1_DIRECTION STRING "ADD"
// Retrieval info: CONSTANT: MULTIPLIER3_DIRECTION STRING "ADD"
// Retrieval info: CONSTANT: MULTIPLIER_ACLR0 STRING "UNUSED"
// Retrieval info: CONSTANT: MULTIPLIER_ACLR1 STRING "UNUSED"
// Retrieval info: CONSTANT: MULTIPLIER_ACLR2 STRING "UNUSED"
// Retrieval info: CONSTANT: MULTIPLIER_ACLR3 STRING "UNUSED"
// Retrieval info: CONSTANT: MULTIPLIER_REGISTER0 STRING "CLOCK0"
// Retrieval info: CONSTANT: MULTIPLIER_REGISTER1 STRING "CLOCK0"
// Retrieval info: CONSTANT: MULTIPLIER_REGISTER2 STRING "CLOCK0"
// Retrieval info: CONSTANT: MULTIPLIER_REGISTER3 STRING "CLOCK0"
// Retrieval info: CONSTANT: NUMBER_OF_MULTIPLIERS NUMERIC "4"
// Retrieval info: CONSTANT: OUTPUT_ACLR STRING "UNUSED"
// Retrieval info: CONSTANT: OUTPUT_REGISTER STRING "CLOCK0"
// Retrieval info: CONSTANT: PORT_ADDNSUB1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_ADDNSUB3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SIGNA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SIGNB STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: REPRESENTATION_A STRING "SIGNED"
// Retrieval info: CONSTANT: REPRESENTATION_B STRING "SIGNED"
// Retrieval info: CONSTANT: SIGNED_ACLR_A STRING "UNUSED"
// Retrieval info: CONSTANT: SIGNED_ACLR_B STRING "UNUSED"
// Retrieval info: CONSTANT: SIGNED_PIPELINE_ACLR_A STRING "UNUSED"
// Retrieval info: CONSTANT: SIGNED_PIPELINE_ACLR_B STRING "UNUSED"
// Retrieval info: CONSTANT: SIGNED_PIPELINE_REGISTER_A STRING "CLOCK0"
// Retrieval info: CONSTANT: SIGNED_PIPELINE_REGISTER_B STRING "CLOCK0"
// Retrieval info: CONSTANT: SIGNED_REGISTER_A STRING "CLOCK0"
// Retrieval info: CONSTANT: SIGNED_REGISTER_B STRING "CLOCK0"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "17"
// Retrieval info: CONSTANT: WIDTH_B NUMERIC "16"
// Retrieval info: CONSTANT: WIDTH_CHAININ NUMERIC "44"
// Retrieval info: CONSTANT: WIDTH_RESULT NUMERIC "44"
// Retrieval info: CONSTANT: ZERO_CHAINOUT_OUTPUT_REGISTER STRING "UNREGISTERED"
// Retrieval info: CONSTANT: ZERO_LOOPBACK_ACLR STRING "UNUSED"
// Retrieval info: CONSTANT: ZERO_LOOPBACK_OUTPUT_ACLR STRING "UNUSED"
// Retrieval info: CONSTANT: ZERO_LOOPBACK_OUTPUT_REGISTER STRING "CLOCK0"
// Retrieval info: CONSTANT: ZERO_LOOPBACK_PIPELINE_ACLR STRING "UNUSED"
// Retrieval info: CONSTANT: ZERO_LOOPBACK_PIPELINE_REGISTER STRING "CLOCK0"
// Retrieval info: CONSTANT: ZERO_LOOPBACK_REGISTER STRING "CLOCK0"
// Retrieval info: USED_PORT: chainin 0 0 44 0 INPUT GND "chainin[43..0]"
// Retrieval info: USED_PORT: clock0 0 0 0 0 INPUT VCC "clock0"
// Retrieval info: USED_PORT: dataa_0 0 0 17 0 INPUT GND "dataa_0[16..0]"
// Retrieval info: USED_PORT: dataa_1 0 0 17 0 INPUT GND "dataa_1[16..0]"
// Retrieval info: USED_PORT: dataa_2 0 0 17 0 INPUT GND "dataa_2[16..0]"
// Retrieval info: USED_PORT: dataa_3 0 0 17 0 INPUT GND "dataa_3[16..0]"
// Retrieval info: USED_PORT: datab_0 0 0 16 0 INPUT GND "datab_0[15..0]"
// Retrieval info: USED_PORT: datab_1 0 0 16 0 INPUT GND "datab_1[15..0]"
// Retrieval info: USED_PORT: datab_2 0 0 16 0 INPUT GND "datab_2[15..0]"
// Retrieval info: USED_PORT: datab_3 0 0 16 0 INPUT GND "datab_3[15..0]"
// Retrieval info: USED_PORT: ena0 0 0 0 0 INPUT VCC "ena0"
// Retrieval info: USED_PORT: result 0 0 44 0 OUTPUT GND "result[43..0]"
// Retrieval info: CONNECT: @chainin 0 0 44 0 chainin 0 0 44 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock0 0 0 0 0
// Retrieval info: CONNECT: @dataa 0 0 17 0 dataa_0 0 0 17 0
// Retrieval info: CONNECT: @dataa 0 0 17 17 dataa_1 0 0 17 0
// Retrieval info: CONNECT: @dataa 0 0 17 34 dataa_2 0 0 17 0
// Retrieval info: CONNECT: @dataa 0 0 17 51 dataa_3 0 0 17 0
// Retrieval info: CONNECT: @datab 0 0 16 0 datab_0 0 0 16 0
// Retrieval info: CONNECT: @datab 0 0 16 16 datab_1 0 0 16 0
// Retrieval info: CONNECT: @datab 0 0 16 32 datab_2 0 0 16 0
// Retrieval info: CONNECT: @datab 0 0 16 48 datab_3 0 0 16 0
// Retrieval info: CONNECT: @ena0 0 0 0 0 ena0 0 0 0 0
// Retrieval info: CONNECT: result 0 0 44 0 @result 0 0 44 0
// Retrieval info: GEN_FILE: TYPE_NORMAL dsp_4mult_add.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL dsp_4mult_add.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL dsp_4mult_add.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL dsp_4mult_add.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL dsp_4mult_add_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL dsp_4mult_add_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
// megafunction wizard: %ALTMULT_ADD%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: ALTMULT_ADD
// ============================================================
// File Name: dsp_4mult_add.v
// Megafunction Name(s):
// ALTMULT_ADD
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 12.1 Build 177 11/07/2012 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2012 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module dsp_4mult_add (
chainin,
clock0,
dataa_0,
dataa_1,
dataa_2,
dataa_3,
datab_0,
datab_1,
datab_2,
datab_3,
ena0,
result);
input [43:0] chainin;
input clock0;
input [16:0] dataa_0;
input [16:0] dataa_1;
input [16:0] dataa_2;
input [16:0] dataa_3;
input [15:0] datab_0;
input [15:0] datab_1;
input [15:0] datab_2;
input [15:0] datab_3;
input ena0;
output [43:0] result;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 [43:0] chainin;
tri1 clock0;
tri0 [16:0] dataa_0;
tri0 [16:0] dataa_1;
tri0 [16:0] dataa_2;
tri0 [16:0] dataa_3;
tri0 [15:0] datab_0;
tri0 [15:0] datab_1;
tri0 [15:0] datab_2;
tri0 [15:0] datab_3;
tri1 ena0;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ACCUM_DIRECTION STRING "Add"
// Retrieval info: PRIVATE: ACCUM_SLOAD_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ACCUM_SLOAD_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ACCUM_SLOAD_PIPE_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ACCUM_SLOAD_PIPE_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ACCUM_SLOAD_PIPE_REG STRING "1"
// Retrieval info: PRIVATE: ACCUM_SLOAD_REG STRING "1"
// Retrieval info: PRIVATE: ADDNSUB1_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ADDNSUB1_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ADDNSUB1_PIPE_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ADDNSUB1_PIPE_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ADDNSUB1_PIPE_REG STRING "1"
// Retrieval info: PRIVATE: ADDNSUB1_REG STRING "1"
// Retrieval info: PRIVATE: ADDNSUB3_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ADDNSUB3_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ADDNSUB3_PIPE_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ADDNSUB3_PIPE_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ADDNSUB3_PIPE_REG STRING "1"
// Retrieval info: PRIVATE: ADDNSUB3_REG STRING "1"
// Retrieval info: PRIVATE: ADD_ENABLE NUMERIC "1"
// Retrieval info: PRIVATE: ALL_REG_ACLR NUMERIC "0"
// Retrieval info: PRIVATE: A_ACLR_SRC_MULT0 NUMERIC "3"
// Retrieval info: PRIVATE: A_CLK_SRC_MULT0 NUMERIC "0"
// Retrieval info: PRIVATE: B_ACLR_SRC_MULT0 NUMERIC "3"
// Retrieval info: PRIVATE: B_CLK_SRC_MULT0 NUMERIC "0"
// Retrieval info: PRIVATE: CHAINOUT_OUTPUT_ACLR NUMERIC "3"
// Retrieval info: PRIVATE: CHAINOUT_OUTPUT_REG STRING "1"
// Retrieval info: PRIVATE: CHAINOUT_OUTPUT_REGISTER NUMERIC "0"
// Retrieval info: PRIVATE: CHAINOUT_OUTPUT_REGISTERED NUMERIC "1"
// Retrieval info: PRIVATE: CHAS_ZERO_CHAINOUT NUMERIC "0"
// Retrieval info: PRIVATE: HAS_ACCUMULATOR NUMERIC "0"
// Retrieval info: PRIVATE: HAS_ACUMM_SLOAD NUMERIC "0"
// Retrieval info: PRIVATE: HAS_CHAININ_PORT NUMERIC "1"
// Retrieval info: PRIVATE: HAS_CHAINOUT_ADDER NUMERIC "1"
// Retrieval info: PRIVATE: HAS_LOOPBACK NUMERIC "0"
// Retrieval info: PRIVATE: HAS_MAC STRING "0"
// Retrieval info: PRIVATE: HAS_SAT_ROUND STRING "0"
// Retrieval info: PRIVATE: HAS_ZERO_LOOPBACK NUMERIC "0"
// Retrieval info: PRIVATE: IMPL_STYLE_DEDICATED NUMERIC "1"
// Retrieval info: PRIVATE: IMPL_STYLE_DEFAULT NUMERIC "0"
// Retrieval info: PRIVATE: IMPL_STYLE_LCELL NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
// Retrieval info: PRIVATE: MULT_REGA0 NUMERIC "1"
// Retrieval info: PRIVATE: MULT_REGB0 NUMERIC "1"
// Retrieval info: PRIVATE: MULT_REGOUT0 NUMERIC "1"
// Retrieval info: PRIVATE: NUM_MULT STRING "4"
// Retrieval info: PRIVATE: OP1 STRING "Add"
// Retrieval info: PRIVATE: OP3 STRING "Add"
// Retrieval info: PRIVATE: OUTPUT_EXTRA_LAT NUMERIC "0"
// Retrieval info: PRIVATE: OUTPUT_REG_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: OUTPUT_REG_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: Q_ACLR_SRC_MULT0 NUMERIC "3"
// Retrieval info: PRIVATE: Q_CLK_SRC_MULT0 NUMERIC "0"
// Retrieval info: PRIVATE: REG_OUT NUMERIC "1"
// Retrieval info: PRIVATE: RNFORMAT STRING "44"
// Retrieval info: PRIVATE: ROTATE_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ROTATE_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ROTATE_OUT_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ROTATE_OUT_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ROTATE_OUT_REG STRING "1"
// Retrieval info: PRIVATE: ROTATE_PIPE_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ROTATE_PIPE_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ROTATE_PIPE_REG STRING "1"
// Retrieval info: PRIVATE: ROTATE_REG STRING "1"
// Retrieval info: PRIVATE: ROUND3_CHAINOUT_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ROUND3_CHAINOUT_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ROUND3_CHAINOUT_MODE STRING "Enabled"
// Retrieval info: PRIVATE: ROUND3_CHAINOUT_OUT_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ROUND3_CHAINOUT_OUT_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ROUND3_CHAINOUT_OUT_REG STRING "1"
// Retrieval info: PRIVATE: ROUND3_CHAINOUT_PIPE_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ROUND3_CHAINOUT_PIPE_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ROUND3_CHAINOUT_PIPE_REG STRING "1"
// Retrieval info: PRIVATE: ROUND3_CHAINOUT_REG STRING "1"
// Retrieval info: PRIVATE: ROUND3_FRAC_WIDTH NUMERIC "27"
// Retrieval info: PRIVATE: ROUND3_OUTPUT_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ROUND3_OUTPUT_CHAINOUT_TYPE STRING "Nearest Integer"
// Retrieval info: PRIVATE: ROUND3_OUTPUT_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ROUND3_OUTPUT_MODE STRING "Disabled"
// Retrieval info: PRIVATE: ROUND3_OUTPUT_PIPE_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ROUND3_OUTPUT_PIPE_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ROUND3_OUTPUT_PIPE_REG STRING "1"
// Retrieval info: PRIVATE: ROUND3_OUTPUT_REG STRING "1"
// Retrieval info: PRIVATE: RQFORMAT STRING "Q1.15"
// Retrieval info: PRIVATE: RTS_WIDTH STRING "44"
// Retrieval info: PRIVATE: SAME_CONFIG NUMERIC "1"
// Retrieval info: PRIVATE: SAME_CONTROL_SRC_A0 NUMERIC "1"
// Retrieval info: PRIVATE: SAME_CONTROL_SRC_B0 NUMERIC "1"
// Retrieval info: PRIVATE: SAT3_CHAINOUT_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: SAT3_CHAINOUT_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: SAT3_CHAINOUT_MODE STRING "Enabled"
// Retrieval info: PRIVATE: SAT3_CHAINOUT_OUT_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: SAT3_CHAINOUT_OUT_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: SAT3_CHAINOUT_OVERFLOW NUMERIC "0"
// Retrieval info: PRIVATE: SAT3_CHAINOUT_PIPE_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: SAT3_CHAINOUT_PIPE_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: SAT3_CHAINOUT_PIPE_REG STRING "1"
// Retrieval info: PRIVATE: SAT3_CHAINOUT_REG STRING "1"
// Retrieval info: PRIVATE: SAT3_FRAC_WIDTH NUMERIC "2"
// Retrieval info: PRIVATE: SAT3_OUTPUT_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: SAT3_OUTPUT_CHAINOUT_TYPE STRING "Asymmetric"
// Retrieval info: PRIVATE: SAT3_OUTPUT_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: SAT3_OUTPUT_MODE STRING "Enabled"
// Retrieval info: PRIVATE: SAT3_OUTPUT_OVERFLOW NUMERIC "0"
// Retrieval info: PRIVATE: SAT3_OUTPUT_PIPE_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: SAT3_OUTPUT_PIPE_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: SAT3_OUTPUT_PIPE_REG STRING "1"
// Retrieval info: PRIVATE: SAT3_OUTPUT_REG STRING "1"
// Retrieval info: PRIVATE: SCANOUTA NUMERIC "0"
// Retrieval info: PRIVATE: SCANOUTB NUMERIC "0"
// Retrieval info: PRIVATE: SHIFTOUTA_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: SHIFTOUTA_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: SHIFTOUTA_REG STRING "0"
// Retrieval info: PRIVATE: SHIFT_RIGHT_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: SHIFT_RIGHT_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: SHIFT_RIGHT_OUT_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: SHIFT_RIGHT_OUT_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: SHIFT_RIGHT_OUT_REG STRING "1"
// Retrieval info: PRIVATE: SHIFT_RIGHT_PIPE_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: SHIFT_RIGHT_PIPE_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: SHIFT_RIGHT_PIPE_REG STRING "1"
// Retrieval info: PRIVATE: SHIFT_RIGHT_REG STRING "1"
// Retrieval info: PRIVATE: SHIFT_ROTATE_MODE STRING "None"
// Retrieval info: PRIVATE: SIGNA STRING "SIGNED"
// Retrieval info: PRIVATE: SIGNA_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: SIGNA_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: SIGNA_PIPE_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: SIGNA_PIPE_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: SIGNA_PIPE_REG STRING "1"
// Retrieval info: PRIVATE: SIGNA_REG STRING "1"
// Retrieval info: PRIVATE: SIGNB STRING "SIGNED"
// Retrieval info: PRIVATE: SIGNB_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: SIGNB_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: SIGNB_PIPE_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: SIGNB_PIPE_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: SIGNB_PIPE_REG STRING "1"
// Retrieval info: PRIVATE: SIGNB_REG STRING "1"
// Retrieval info: PRIVATE: SRCA0 STRING "Multiplier input"
// Retrieval info: PRIVATE: SRCB0 STRING "Multiplier input"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: WIDTHA STRING "17"
// Retrieval info: PRIVATE: WIDTHB STRING "16"
// Retrieval info: PRIVATE: ZERO_CHAINOUT_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ZERO_CHAINOUT_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_CHAINOUT_REG STRING "0"
// Retrieval info: PRIVATE: ZERO_LOOPBACK_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ZERO_LOOPBACK_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_LOOPBACK_OUT_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ZERO_LOOPBACK_OUT_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_LOOPBACK_OUT_REG STRING "1"
// Retrieval info: PRIVATE: ZERO_LOOPBACK_PIPE_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ZERO_LOOPBACK_PIPE_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_LOOPBACK_PIPE_REG STRING "1"
// Retrieval info: PRIVATE: ZERO_LOOPBACK_REG STRING "1"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ACCUMULATOR STRING "NO"
// Retrieval info: CONSTANT: ADDNSUB_MULTIPLIER_ACLR1 STRING "UNUSED"
// Retrieval info: CONSTANT: ADDNSUB_MULTIPLIER_ACLR3 STRING "UNUSED"
// Retrieval info: CONSTANT: ADDNSUB_MULTIPLIER_PIPELINE_ACLR1 STRING "UNUSED"
// Retrieval info: CONSTANT: ADDNSUB_MULTIPLIER_PIPELINE_ACLR3 STRING "UNUSED"
// Retrieval info: CONSTANT: ADDNSUB_MULTIPLIER_PIPELINE_REGISTER1 STRING "CLOCK0"
// Retrieval info: CONSTANT: ADDNSUB_MULTIPLIER_PIPELINE_REGISTER3 STRING "CLOCK0"
// Retrieval info: CONSTANT: ADDNSUB_MULTIPLIER_REGISTER1 STRING "CLOCK0"
// Retrieval info: CONSTANT: ADDNSUB_MULTIPLIER_REGISTER3 STRING "CLOCK0"
// Retrieval info: CONSTANT: CHAINOUT_ACLR STRING "UNUSED"
// Retrieval info: CONSTANT: CHAINOUT_ADDER STRING "YES"
// Retrieval info: CONSTANT: CHAINOUT_REGISTER STRING "CLOCK0"
// Retrieval info: CONSTANT: DEDICATED_MULTIPLIER_CIRCUITRY STRING "YES"
// Retrieval info: CONSTANT: INPUT_ACLR_A0 STRING "UNUSED"
// Retrieval info: CONSTANT: INPUT_ACLR_A1 STRING "UNUSED"
// Retrieval info: CONSTANT: INPUT_ACLR_A2 STRING "UNUSED"
// Retrieval info: CONSTANT: INPUT_ACLR_A3 STRING "UNUSED"
// Retrieval info: CONSTANT: INPUT_ACLR_B0 STRING "UNUSED"
// Retrieval info: CONSTANT: INPUT_ACLR_B1 STRING "UNUSED"
// Retrieval info: CONSTANT: INPUT_ACLR_B2 STRING "UNUSED"
// Retrieval info: CONSTANT: INPUT_ACLR_B3 STRING "UNUSED"
// Retrieval info: CONSTANT: INPUT_REGISTER_A0 STRING "CLOCK0"
// Retrieval info: CONSTANT: INPUT_REGISTER_A1 STRING "CLOCK0"
// Retrieval info: CONSTANT: INPUT_REGISTER_A2 STRING "CLOCK0"
// Retrieval info: CONSTANT: INPUT_REGISTER_A3 STRING "CLOCK0"
// Retrieval info: CONSTANT: INPUT_REGISTER_B0 STRING "CLOCK0"
// Retrieval info: CONSTANT: INPUT_REGISTER_B1 STRING "CLOCK0"
// Retrieval info: CONSTANT: INPUT_REGISTER_B2 STRING "CLOCK0"
// Retrieval info: CONSTANT: INPUT_REGISTER_B3 STRING "CLOCK0"
// Retrieval info: CONSTANT: INPUT_SOURCE_A0 STRING "DATAA"
// Retrieval info: CONSTANT: INPUT_SOURCE_A1 STRING "DATAA"
// Retrieval info: CONSTANT: INPUT_SOURCE_A2 STRING "DATAA"
// Retrieval info: CONSTANT: INPUT_SOURCE_A3 STRING "DATAA"
// Retrieval info: CONSTANT: INPUT_SOURCE_B0 STRING "DATAB"
// Retrieval info: CONSTANT: INPUT_SOURCE_B1 STRING "DATAB"
// Retrieval info: CONSTANT: INPUT_SOURCE_B2 STRING "DATAB"
// Retrieval info: CONSTANT: INPUT_SOURCE_B3 STRING "DATAB"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altmult_add"
// Retrieval info: CONSTANT: MULTIPLIER1_DIRECTION STRING "ADD"
// Retrieval info: CONSTANT: MULTIPLIER3_DIRECTION STRING "ADD"
// Retrieval info: CONSTANT: MULTIPLIER_ACLR0 STRING "UNUSED"
// Retrieval info: CONSTANT: MULTIPLIER_ACLR1 STRING "UNUSED"
// Retrieval info: CONSTANT: MULTIPLIER_ACLR2 STRING "UNUSED"
// Retrieval info: CONSTANT: MULTIPLIER_ACLR3 STRING "UNUSED"
// Retrieval info: CONSTANT: MULTIPLIER_REGISTER0 STRING "CLOCK0"
// Retrieval info: CONSTANT: MULTIPLIER_REGISTER1 STRING "CLOCK0"
// Retrieval info: CONSTANT: MULTIPLIER_REGISTER2 STRING "CLOCK0"
// Retrieval info: CONSTANT: MULTIPLIER_REGISTER3 STRING "CLOCK0"
// Retrieval info: CONSTANT: NUMBER_OF_MULTIPLIERS NUMERIC "4"
// Retrieval info: CONSTANT: OUTPUT_ACLR STRING "UNUSED"
// Retrieval info: CONSTANT: OUTPUT_REGISTER STRING "CLOCK0"
// Retrieval info: CONSTANT: PORT_ADDNSUB1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_ADDNSUB3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SIGNA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SIGNB STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: REPRESENTATION_A STRING "SIGNED"
// Retrieval info: CONSTANT: REPRESENTATION_B STRING "SIGNED"
// Retrieval info: CONSTANT: SIGNED_ACLR_A STRING "UNUSED"
// Retrieval info: CONSTANT: SIGNED_ACLR_B STRING "UNUSED"
// Retrieval info: CONSTANT: SIGNED_PIPELINE_ACLR_A STRING "UNUSED"
// Retrieval info: CONSTANT: SIGNED_PIPELINE_ACLR_B STRING "UNUSED"
// Retrieval info: CONSTANT: SIGNED_PIPELINE_REGISTER_A STRING "CLOCK0"
// Retrieval info: CONSTANT: SIGNED_PIPELINE_REGISTER_B STRING "CLOCK0"
// Retrieval info: CONSTANT: SIGNED_REGISTER_A STRING "CLOCK0"
// Retrieval info: CONSTANT: SIGNED_REGISTER_B STRING "CLOCK0"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "17"
// Retrieval info: CONSTANT: WIDTH_B NUMERIC "16"
// Retrieval info: CONSTANT: WIDTH_CHAININ NUMERIC "44"
// Retrieval info: CONSTANT: WIDTH_RESULT NUMERIC "44"
// Retrieval info: CONSTANT: ZERO_CHAINOUT_OUTPUT_REGISTER STRING "UNREGISTERED"
// Retrieval info: CONSTANT: ZERO_LOOPBACK_ACLR STRING "UNUSED"
// Retrieval info: CONSTANT: ZERO_LOOPBACK_OUTPUT_ACLR STRING "UNUSED"
// Retrieval info: CONSTANT: ZERO_LOOPBACK_OUTPUT_REGISTER STRING "CLOCK0"
// Retrieval info: CONSTANT: ZERO_LOOPBACK_PIPELINE_ACLR STRING "UNUSED"
// Retrieval info: CONSTANT: ZERO_LOOPBACK_PIPELINE_REGISTER STRING "CLOCK0"
// Retrieval info: CONSTANT: ZERO_LOOPBACK_REGISTER STRING "CLOCK0"
// Retrieval info: USED_PORT: chainin 0 0 44 0 INPUT GND "chainin[43..0]"
// Retrieval info: USED_PORT: clock0 0 0 0 0 INPUT VCC "clock0"
// Retrieval info: USED_PORT: dataa_0 0 0 17 0 INPUT GND "dataa_0[16..0]"
// Retrieval info: USED_PORT: dataa_1 0 0 17 0 INPUT GND "dataa_1[16..0]"
// Retrieval info: USED_PORT: dataa_2 0 0 17 0 INPUT GND "dataa_2[16..0]"
// Retrieval info: USED_PORT: dataa_3 0 0 17 0 INPUT GND "dataa_3[16..0]"
// Retrieval info: USED_PORT: datab_0 0 0 16 0 INPUT GND "datab_0[15..0]"
// Retrieval info: USED_PORT: datab_1 0 0 16 0 INPUT GND "datab_1[15..0]"
// Retrieval info: USED_PORT: datab_2 0 0 16 0 INPUT GND "datab_2[15..0]"
// Retrieval info: USED_PORT: datab_3 0 0 16 0 INPUT GND "datab_3[15..0]"
// Retrieval info: USED_PORT: ena0 0 0 0 0 INPUT VCC "ena0"
// Retrieval info: USED_PORT: result 0 0 44 0 OUTPUT GND "result[43..0]"
// Retrieval info: CONNECT: @chainin 0 0 44 0 chainin 0 0 44 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock0 0 0 0 0
// Retrieval info: CONNECT: @dataa 0 0 17 0 dataa_0 0 0 17 0
// Retrieval info: CONNECT: @dataa 0 0 17 17 dataa_1 0 0 17 0
// Retrieval info: CONNECT: @dataa 0 0 17 34 dataa_2 0 0 17 0
// Retrieval info: CONNECT: @dataa 0 0 17 51 dataa_3 0 0 17 0
// Retrieval info: CONNECT: @datab 0 0 16 0 datab_0 0 0 16 0
// Retrieval info: CONNECT: @datab 0 0 16 16 datab_1 0 0 16 0
// Retrieval info: CONNECT: @datab 0 0 16 32 datab_2 0 0 16 0
// Retrieval info: CONNECT: @datab 0 0 16 48 datab_3 0 0 16 0
// Retrieval info: CONNECT: @ena0 0 0 0 0 ena0 0 0 0 0
// Retrieval info: CONNECT: result 0 0 44 0 @result 0 0 44 0
// Retrieval info: GEN_FILE: TYPE_NORMAL dsp_4mult_add.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL dsp_4mult_add.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL dsp_4mult_add.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL dsp_4mult_add.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL dsp_4mult_add_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL dsp_4mult_add_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
dsp_4mult_add dsp_4mult_add_inst (
.chainin ( chainin_sig ),
.clock0 ( clock0_sig ),
.dataa_0 ( dataa_0_sig ),
.dataa_1 ( dataa_1_sig ),
.dataa_2 ( dataa_2_sig ),
.dataa_3 ( dataa_3_sig ),
.datab_0 ( datab_0_sig ),
.datab_1 ( datab_1_sig ),
.datab_2 ( datab_2_sig ),
.datab_3 ( datab_3_sig ),
.ena0 ( ena0_sig ),
.result ( result_sig )
);
|
// megafunction wizard: %LPM_ADD_SUB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: LPM_ADD_SUB
// ============================================================
// File Name: input_adder.v
// Megafunction Name(s):
// LPM_ADD_SUB
//
// Simulation Library Files(s):
// lpm
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 12.1 Build 177 11/07/2012 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2012 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module input_adder (
clken,
clock,
dataa,
datab,
result);
input clken;
input clock;
input [15:0] dataa;
input [15:0] datab;
output [15:0] result;
wire [15:0] sub_wire0;
wire [15:0] result = sub_wire0[15:0];
lpm_add_sub LPM_ADD_SUB_component (
.clock (clock),
.datab (datab),
.clken (clken),
.dataa (dataa),
.result (sub_wire0)
// synopsys translate_off
,
.aclr (),
.add_sub (),
.cin (),
.cout (),
.overflow ()
// synopsys translate_on
);
defparam
LPM_ADD_SUB_component.lpm_direction = "ADD",
LPM_ADD_SUB_component.lpm_hint = "ONE_INPUT_IS_CONSTANT=NO,CIN_USED=NO",
LPM_ADD_SUB_component.lpm_pipeline = 1,
LPM_ADD_SUB_component.lpm_representation = "SIGNED",
LPM_ADD_SUB_component.lpm_type = "LPM_ADD_SUB",
LPM_ADD_SUB_component.lpm_width = 16;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: CarryIn NUMERIC "0"
// Retrieval info: PRIVATE: CarryOut NUMERIC "0"
// Retrieval info: PRIVATE: ConstantA NUMERIC "0"
// Retrieval info: PRIVATE: ConstantB NUMERIC "0"
// Retrieval info: PRIVATE: Function NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
// Retrieval info: PRIVATE: LPM_PIPELINE NUMERIC "1"
// Retrieval info: PRIVATE: Latency NUMERIC "1"
// Retrieval info: PRIVATE: Overflow NUMERIC "0"
// Retrieval info: PRIVATE: RadixA NUMERIC "10"
// Retrieval info: PRIVATE: RadixB NUMERIC "10"
// Retrieval info: PRIVATE: Representation NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: ValidCtA NUMERIC "0"
// Retrieval info: PRIVATE: ValidCtB NUMERIC "0"
// Retrieval info: PRIVATE: WhichConstant NUMERIC "0"
// Retrieval info: PRIVATE: aclr NUMERIC "0"
// Retrieval info: PRIVATE: clken NUMERIC "1"
// Retrieval info: PRIVATE: nBit NUMERIC "16"
// Retrieval info: PRIVATE: new_diagram STRING "1"
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
// Retrieval info: CONSTANT: LPM_DIRECTION STRING "ADD"
// Retrieval info: CONSTANT: LPM_HINT STRING "ONE_INPUT_IS_CONSTANT=NO,CIN_USED=NO"
// Retrieval info: CONSTANT: LPM_PIPELINE NUMERIC "1"
// Retrieval info: CONSTANT: LPM_REPRESENTATION STRING "SIGNED"
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_ADD_SUB"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16"
// Retrieval info: USED_PORT: clken 0 0 0 0 INPUT NODEFVAL "clken"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
// Retrieval info: USED_PORT: dataa 0 0 16 0 INPUT NODEFVAL "dataa[15..0]"
// Retrieval info: USED_PORT: datab 0 0 16 0 INPUT NODEFVAL "datab[15..0]"
// Retrieval info: USED_PORT: result 0 0 16 0 OUTPUT NODEFVAL "result[15..0]"
// Retrieval info: CONNECT: @clken 0 0 0 0 clken 0 0 0 0
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @dataa 0 0 16 0 dataa 0 0 16 0
// Retrieval info: CONNECT: @datab 0 0 16 0 datab 0 0 16 0
// Retrieval info: CONNECT: result 0 0 16 0 @result 0 0 16 0
// Retrieval info: GEN_FILE: TYPE_NORMAL input_adder.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL input_adder.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL input_adder.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL input_adder.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL input_adder_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL input_adder_bb.v TRUE
// Retrieval info: LIB_FILE: lpm
|
// megafunction wizard: %LPM_ADD_SUB%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: LPM_ADD_SUB
// ============================================================
// File Name: input_adder.v
// Megafunction Name(s):
// LPM_ADD_SUB
//
// Simulation Library Files(s):
// lpm
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 12.1 Build 177 11/07/2012 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2012 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module input_adder (
clken,
clock,
dataa,
datab,
result);
input clken;
input clock;
input [15:0] dataa;
input [15:0] datab;
output [15:0] result;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: CarryIn NUMERIC "0"
// Retrieval info: PRIVATE: CarryOut NUMERIC "0"
// Retrieval info: PRIVATE: ConstantA NUMERIC "0"
// Retrieval info: PRIVATE: ConstantB NUMERIC "0"
// Retrieval info: PRIVATE: Function NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
// Retrieval info: PRIVATE: LPM_PIPELINE NUMERIC "1"
// Retrieval info: PRIVATE: Latency NUMERIC "1"
// Retrieval info: PRIVATE: Overflow NUMERIC "0"
// Retrieval info: PRIVATE: RadixA NUMERIC "10"
// Retrieval info: PRIVATE: RadixB NUMERIC "10"
// Retrieval info: PRIVATE: Representation NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: ValidCtA NUMERIC "0"
// Retrieval info: PRIVATE: ValidCtB NUMERIC "0"
// Retrieval info: PRIVATE: WhichConstant NUMERIC "0"
// Retrieval info: PRIVATE: aclr NUMERIC "0"
// Retrieval info: PRIVATE: clken NUMERIC "1"
// Retrieval info: PRIVATE: nBit NUMERIC "16"
// Retrieval info: PRIVATE: new_diagram STRING "1"
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
// Retrieval info: CONSTANT: LPM_DIRECTION STRING "ADD"
// Retrieval info: CONSTANT: LPM_HINT STRING "ONE_INPUT_IS_CONSTANT=NO,CIN_USED=NO"
// Retrieval info: CONSTANT: LPM_PIPELINE NUMERIC "1"
// Retrieval info: CONSTANT: LPM_REPRESENTATION STRING "SIGNED"
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_ADD_SUB"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16"
// Retrieval info: USED_PORT: clken 0 0 0 0 INPUT NODEFVAL "clken"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
// Retrieval info: USED_PORT: dataa 0 0 16 0 INPUT NODEFVAL "dataa[15..0]"
// Retrieval info: USED_PORT: datab 0 0 16 0 INPUT NODEFVAL "datab[15..0]"
// Retrieval info: USED_PORT: result 0 0 16 0 OUTPUT NODEFVAL "result[15..0]"
// Retrieval info: CONNECT: @clken 0 0 0 0 clken 0 0 0 0
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @dataa 0 0 16 0 dataa 0 0 16 0
// Retrieval info: CONNECT: @datab 0 0 16 0 datab 0 0 16 0
// Retrieval info: CONNECT: result 0 0 16 0 @result 0 0 16 0
// Retrieval info: GEN_FILE: TYPE_NORMAL input_adder.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL input_adder.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL input_adder.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL input_adder.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL input_adder_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL input_adder_bb.v TRUE
// Retrieval info: LIB_FILE: lpm
|
input_adder input_adder_inst (
.clken ( clken_sig ),
.clock ( clock_sig ),
.dataa ( dataa_sig ),
.datab ( datab_sig ),
.result ( result_sig )
);
|
// megafunction wizard: %LPM_ADD_SUB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: LPM_ADD_SUB
// ============================================================
// File Name: output_adder.v
// Megafunction Name(s):
// LPM_ADD_SUB
//
// Simulation Library Files(s):
// lpm
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 12.1 Build 177 11/07/2012 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2012 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module output_adder (
clken,
clock,
dataa,
datab,
result);
input clken;
input clock;
input [15:0] dataa;
input [15:0] datab;
output [15:0] result;
wire [15:0] sub_wire0;
wire [15:0] result = sub_wire0[15:0];
lpm_add_sub LPM_ADD_SUB_component (
.clock (clock),
.datab (datab),
.clken (clken),
.dataa (dataa),
.result (sub_wire0)
// synopsys translate_off
,
.aclr (),
.add_sub (),
.cin (),
.cout (),
.overflow ()
// synopsys translate_on
);
defparam
LPM_ADD_SUB_component.lpm_direction = "ADD",
LPM_ADD_SUB_component.lpm_hint = "ONE_INPUT_IS_CONSTANT=NO,CIN_USED=NO",
LPM_ADD_SUB_component.lpm_pipeline = 2,
LPM_ADD_SUB_component.lpm_representation = "SIGNED",
LPM_ADD_SUB_component.lpm_type = "LPM_ADD_SUB",
LPM_ADD_SUB_component.lpm_width = 16;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: CarryIn NUMERIC "0"
// Retrieval info: PRIVATE: CarryOut NUMERIC "0"
// Retrieval info: PRIVATE: ConstantA NUMERIC "0"
// Retrieval info: PRIVATE: ConstantB NUMERIC "0"
// Retrieval info: PRIVATE: Function NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
// Retrieval info: PRIVATE: LPM_PIPELINE NUMERIC "2"
// Retrieval info: PRIVATE: Latency NUMERIC "1"
// Retrieval info: PRIVATE: Overflow NUMERIC "0"
// Retrieval info: PRIVATE: RadixA NUMERIC "10"
// Retrieval info: PRIVATE: RadixB NUMERIC "10"
// Retrieval info: PRIVATE: Representation NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: ValidCtA NUMERIC "0"
// Retrieval info: PRIVATE: ValidCtB NUMERIC "0"
// Retrieval info: PRIVATE: WhichConstant NUMERIC "0"
// Retrieval info: PRIVATE: aclr NUMERIC "0"
// Retrieval info: PRIVATE: clken NUMERIC "1"
// Retrieval info: PRIVATE: nBit NUMERIC "16"
// Retrieval info: PRIVATE: new_diagram STRING "1"
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
// Retrieval info: CONSTANT: LPM_DIRECTION STRING "ADD"
// Retrieval info: CONSTANT: LPM_HINT STRING "ONE_INPUT_IS_CONSTANT=NO,CIN_USED=NO"
// Retrieval info: CONSTANT: LPM_PIPELINE NUMERIC "2"
// Retrieval info: CONSTANT: LPM_REPRESENTATION STRING "SIGNED"
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_ADD_SUB"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16"
// Retrieval info: USED_PORT: clken 0 0 0 0 INPUT NODEFVAL "clken"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
// Retrieval info: USED_PORT: dataa 0 0 16 0 INPUT NODEFVAL "dataa[15..0]"
// Retrieval info: USED_PORT: datab 0 0 16 0 INPUT NODEFVAL "datab[15..0]"
// Retrieval info: USED_PORT: result 0 0 16 0 OUTPUT NODEFVAL "result[15..0]"
// Retrieval info: CONNECT: @clken 0 0 0 0 clken 0 0 0 0
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @dataa 0 0 16 0 dataa 0 0 16 0
// Retrieval info: CONNECT: @datab 0 0 16 0 datab 0 0 16 0
// Retrieval info: CONNECT: result 0 0 16 0 @result 0 0 16 0
// Retrieval info: GEN_FILE: TYPE_NORMAL output_adder.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL output_adder.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL output_adder.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL output_adder.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL output_adder_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL output_adder_bb.v TRUE
// Retrieval info: LIB_FILE: lpm
|
// megafunction wizard: %LPM_ADD_SUB%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: LPM_ADD_SUB
// ============================================================
// File Name: output_adder.v
// Megafunction Name(s):
// LPM_ADD_SUB
//
// Simulation Library Files(s):
// lpm
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 12.1 Build 177 11/07/2012 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2012 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module output_adder (
clken,
clock,
dataa,
datab,
result);
input clken;
input clock;
input [15:0] dataa;
input [15:0] datab;
output [15:0] result;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: CarryIn NUMERIC "0"
// Retrieval info: PRIVATE: CarryOut NUMERIC "0"
// Retrieval info: PRIVATE: ConstantA NUMERIC "0"
// Retrieval info: PRIVATE: ConstantB NUMERIC "0"
// Retrieval info: PRIVATE: Function NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
// Retrieval info: PRIVATE: LPM_PIPELINE NUMERIC "2"
// Retrieval info: PRIVATE: Latency NUMERIC "1"
// Retrieval info: PRIVATE: Overflow NUMERIC "0"
// Retrieval info: PRIVATE: RadixA NUMERIC "10"
// Retrieval info: PRIVATE: RadixB NUMERIC "10"
// Retrieval info: PRIVATE: Representation NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: ValidCtA NUMERIC "0"
// Retrieval info: PRIVATE: ValidCtB NUMERIC "0"
// Retrieval info: PRIVATE: WhichConstant NUMERIC "0"
// Retrieval info: PRIVATE: aclr NUMERIC "0"
// Retrieval info: PRIVATE: clken NUMERIC "1"
// Retrieval info: PRIVATE: nBit NUMERIC "16"
// Retrieval info: PRIVATE: new_diagram STRING "1"
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
// Retrieval info: CONSTANT: LPM_DIRECTION STRING "ADD"
// Retrieval info: CONSTANT: LPM_HINT STRING "ONE_INPUT_IS_CONSTANT=NO,CIN_USED=NO"
// Retrieval info: CONSTANT: LPM_PIPELINE NUMERIC "2"
// Retrieval info: CONSTANT: LPM_REPRESENTATION STRING "SIGNED"
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_ADD_SUB"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16"
// Retrieval info: USED_PORT: clken 0 0 0 0 INPUT NODEFVAL "clken"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
// Retrieval info: USED_PORT: dataa 0 0 16 0 INPUT NODEFVAL "dataa[15..0]"
// Retrieval info: USED_PORT: datab 0 0 16 0 INPUT NODEFVAL "datab[15..0]"
// Retrieval info: USED_PORT: result 0 0 16 0 OUTPUT NODEFVAL "result[15..0]"
// Retrieval info: CONNECT: @clken 0 0 0 0 clken 0 0 0 0
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @dataa 0 0 16 0 dataa 0 0 16 0
// Retrieval info: CONNECT: @datab 0 0 16 0 datab 0 0 16 0
// Retrieval info: CONNECT: result 0 0 16 0 @result 0 0 16 0
// Retrieval info: GEN_FILE: TYPE_NORMAL output_adder.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL output_adder.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL output_adder.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL output_adder.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL output_adder_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL output_adder_bb.v TRUE
// Retrieval info: LIB_FILE: lpm
|
output_adder output_adder_inst (
.clken ( clken_sig ),
.clock ( clock_sig ),
.dataa ( dataa_sig ),
.datab ( datab_sig ),
.result ( result_sig )
);
|
// megafunction wizard: %ALTMULT_ADD%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: ALTMULT_ADD
// ============================================================
// File Name: dsp_2mult_add.v
// Megafunction Name(s):
// ALTMULT_ADD
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 12.1 Build 177 11/07/2012 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2012 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module dsp_2mult_add (
clock0,
dataa_0,
dataa_1,
datab_0,
datab_1,
ena0,
result);
input clock0;
input [16:0] dataa_0;
input [16:0] dataa_1;
input [15:0] datab_0;
input [15:0] datab_1;
input ena0;
output [34:0] result;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock0;
tri0 [16:0] dataa_0;
tri0 [16:0] dataa_1;
tri0 [15:0] datab_0;
tri0 [15:0] datab_1;
tri1 ena0;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [34:0] sub_wire0;
wire [16:0] sub_wire6 = dataa_1[16:0];
wire [15:0] sub_wire3 = datab_1[15:0];
wire [34:0] result = sub_wire0[34:0];
wire [15:0] sub_wire1 = datab_0[15:0];
wire [31:0] sub_wire2 = {sub_wire3, sub_wire1};
wire [16:0] sub_wire4 = dataa_0[16:0];
wire [33:0] sub_wire5 = {sub_wire6, sub_wire4};
altmult_add ALTMULT_ADD_component (
.clock0 (clock0),
.datab (sub_wire2),
.ena0 (ena0),
.dataa (sub_wire5),
.result (sub_wire0),
.accum_sload (1'b0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.aclr2 (1'b0),
.aclr3 (1'b0),
.addnsub1 (1'b1),
.addnsub1_round (1'b0),
.addnsub3 (1'b1),
.addnsub3_round (1'b0),
.chainin (1'b0),
.chainout_round (1'b0),
.chainout_sat_overflow (),
.chainout_saturate (1'b0),
.clock1 (1'b1),
.clock2 (1'b1),
.clock3 (1'b1),
.coefsel0 ({3{1'b0}}),
.coefsel1 ({3{1'b0}}),
.coefsel2 ({3{1'b0}}),
.coefsel3 ({3{1'b0}}),
.datac ({44{1'b0}}),
.ena1 (1'b1),
.ena2 (1'b1),
.ena3 (1'b1),
.mult01_round (1'b0),
.mult01_saturation (1'b0),
.mult0_is_saturated (),
.mult1_is_saturated (),
.mult23_round (1'b0),
.mult23_saturation (1'b0),
.mult2_is_saturated (),
.mult3_is_saturated (),
.output_round (1'b0),
.output_saturate (1'b0),
.overflow (),
.rotate (1'b0),
.scanina ({17{1'b0}}),
.scaninb ({16{1'b0}}),
.scanouta (),
.scanoutb (),
.shift_right (1'b0),
.signa (1'b0),
.signb (1'b0),
.sourcea ({2{1'b0}}),
.sourceb ({2{1'b0}}),
.zero_chainout (1'b0),
.zero_loopback (1'b0));
defparam
ALTMULT_ADD_component.accumulator = "NO",
ALTMULT_ADD_component.addnsub_multiplier_aclr1 = "UNUSED",
ALTMULT_ADD_component.addnsub_multiplier_pipeline_aclr1 = "UNUSED",
ALTMULT_ADD_component.addnsub_multiplier_pipeline_register1 = "CLOCK0",
ALTMULT_ADD_component.addnsub_multiplier_register1 = "CLOCK0",
ALTMULT_ADD_component.chainout_adder = "NO",
ALTMULT_ADD_component.chainout_register = "UNREGISTERED",
ALTMULT_ADD_component.dedicated_multiplier_circuitry = "YES",
ALTMULT_ADD_component.input_aclr_a0 = "UNUSED",
ALTMULT_ADD_component.input_aclr_a1 = "UNUSED",
ALTMULT_ADD_component.input_aclr_b0 = "UNUSED",
ALTMULT_ADD_component.input_aclr_b1 = "UNUSED",
ALTMULT_ADD_component.input_register_a0 = "CLOCK0",
ALTMULT_ADD_component.input_register_a1 = "CLOCK0",
ALTMULT_ADD_component.input_register_b0 = "CLOCK0",
ALTMULT_ADD_component.input_register_b1 = "CLOCK0",
ALTMULT_ADD_component.input_source_a0 = "DATAA",
ALTMULT_ADD_component.input_source_a1 = "DATAA",
ALTMULT_ADD_component.input_source_b0 = "DATAB",
ALTMULT_ADD_component.input_source_b1 = "DATAB",
ALTMULT_ADD_component.intended_device_family = "Stratix IV",
ALTMULT_ADD_component.lpm_type = "altmult_add",
ALTMULT_ADD_component.multiplier1_direction = "ADD",
ALTMULT_ADD_component.multiplier_aclr0 = "UNUSED",
ALTMULT_ADD_component.multiplier_aclr1 = "UNUSED",
ALTMULT_ADD_component.multiplier_register0 = "CLOCK0",
ALTMULT_ADD_component.multiplier_register1 = "CLOCK0",
ALTMULT_ADD_component.number_of_multipliers = 2,
ALTMULT_ADD_component.output_aclr = "UNUSED",
ALTMULT_ADD_component.output_register = "CLOCK0",
ALTMULT_ADD_component.port_addnsub1 = "PORT_UNUSED",
ALTMULT_ADD_component.port_signa = "PORT_UNUSED",
ALTMULT_ADD_component.port_signb = "PORT_UNUSED",
ALTMULT_ADD_component.representation_a = "SIGNED",
ALTMULT_ADD_component.representation_b = "SIGNED",
ALTMULT_ADD_component.signed_aclr_a = "UNUSED",
ALTMULT_ADD_component.signed_aclr_b = "UNUSED",
ALTMULT_ADD_component.signed_pipeline_aclr_a = "UNUSED",
ALTMULT_ADD_component.signed_pipeline_aclr_b = "UNUSED",
ALTMULT_ADD_component.signed_pipeline_register_a = "CLOCK0",
ALTMULT_ADD_component.signed_pipeline_register_b = "CLOCK0",
ALTMULT_ADD_component.signed_register_a = "CLOCK0",
ALTMULT_ADD_component.signed_register_b = "CLOCK0",
ALTMULT_ADD_component.width_a = 17,
ALTMULT_ADD_component.width_b = 16,
ALTMULT_ADD_component.width_chainin = 1,
ALTMULT_ADD_component.width_result = 35,
ALTMULT_ADD_component.zero_chainout_output_register = "UNREGISTERED",
ALTMULT_ADD_component.zero_loopback_aclr = "UNUSED",
ALTMULT_ADD_component.zero_loopback_output_aclr = "UNUSED",
ALTMULT_ADD_component.zero_loopback_output_register = "CLOCK0",
ALTMULT_ADD_component.zero_loopback_pipeline_aclr = "UNUSED",
ALTMULT_ADD_component.zero_loopback_pipeline_register = "CLOCK0",
ALTMULT_ADD_component.zero_loopback_register = "CLOCK0";
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ACCUM_DIRECTION STRING "Add"
// Retrieval info: PRIVATE: ACCUM_SLOAD_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ACCUM_SLOAD_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ACCUM_SLOAD_PIPE_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ACCUM_SLOAD_PIPE_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ACCUM_SLOAD_PIPE_REG STRING "1"
// Retrieval info: PRIVATE: ACCUM_SLOAD_REG STRING "1"
// Retrieval info: PRIVATE: ADDNSUB1_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ADDNSUB1_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ADDNSUB1_PIPE_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ADDNSUB1_PIPE_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ADDNSUB1_PIPE_REG STRING "1"
// Retrieval info: PRIVATE: ADDNSUB1_REG STRING "1"
// Retrieval info: PRIVATE: ADDNSUB3_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ADDNSUB3_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ADDNSUB3_PIPE_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ADDNSUB3_PIPE_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ADDNSUB3_PIPE_REG STRING "1"
// Retrieval info: PRIVATE: ADDNSUB3_REG STRING "1"
// Retrieval info: PRIVATE: ADD_ENABLE NUMERIC "1"
// Retrieval info: PRIVATE: ALL_REG_ACLR NUMERIC "0"
// Retrieval info: PRIVATE: A_ACLR_SRC_MULT0 NUMERIC "3"
// Retrieval info: PRIVATE: A_CLK_SRC_MULT0 NUMERIC "0"
// Retrieval info: PRIVATE: B_ACLR_SRC_MULT0 NUMERIC "3"
// Retrieval info: PRIVATE: B_CLK_SRC_MULT0 NUMERIC "0"
// Retrieval info: PRIVATE: CHAINOUT_OUTPUT_ACLR NUMERIC "3"
// Retrieval info: PRIVATE: CHAINOUT_OUTPUT_REG STRING "0"
// Retrieval info: PRIVATE: CHAINOUT_OUTPUT_REGISTER NUMERIC "0"
// Retrieval info: PRIVATE: CHAINOUT_OUTPUT_REGISTERED NUMERIC "0"
// Retrieval info: PRIVATE: CHAS_ZERO_CHAINOUT NUMERIC "0"
// Retrieval info: PRIVATE: HAS_ACCUMULATOR NUMERIC "0"
// Retrieval info: PRIVATE: HAS_ACUMM_SLOAD NUMERIC "0"
// Retrieval info: PRIVATE: HAS_CHAININ_PORT NUMERIC "0"
// Retrieval info: PRIVATE: HAS_CHAINOUT_ADDER NUMERIC "0"
// Retrieval info: PRIVATE: HAS_LOOPBACK NUMERIC "0"
// Retrieval info: PRIVATE: HAS_MAC STRING "0"
// Retrieval info: PRIVATE: HAS_SAT_ROUND STRING "0"
// Retrieval info: PRIVATE: HAS_ZERO_LOOPBACK NUMERIC "0"
// Retrieval info: PRIVATE: IMPL_STYLE_DEDICATED NUMERIC "1"
// Retrieval info: PRIVATE: IMPL_STYLE_DEFAULT NUMERIC "0"
// Retrieval info: PRIVATE: IMPL_STYLE_LCELL NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
// Retrieval info: PRIVATE: MULT_REGA0 NUMERIC "1"
// Retrieval info: PRIVATE: MULT_REGB0 NUMERIC "1"
// Retrieval info: PRIVATE: MULT_REGOUT0 NUMERIC "1"
// Retrieval info: PRIVATE: NUM_MULT STRING "2"
// Retrieval info: PRIVATE: OP1 STRING "Add"
// Retrieval info: PRIVATE: OP3 STRING "Add"
// Retrieval info: PRIVATE: OUTPUT_EXTRA_LAT NUMERIC "0"
// Retrieval info: PRIVATE: OUTPUT_REG_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: OUTPUT_REG_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: Q_ACLR_SRC_MULT0 NUMERIC "3"
// Retrieval info: PRIVATE: Q_CLK_SRC_MULT0 NUMERIC "0"
// Retrieval info: PRIVATE: REG_OUT NUMERIC "1"
// Retrieval info: PRIVATE: RNFORMAT STRING "35"
// Retrieval info: PRIVATE: ROTATE_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ROTATE_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ROTATE_OUT_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ROTATE_OUT_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ROTATE_OUT_REG STRING "1"
// Retrieval info: PRIVATE: ROTATE_PIPE_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ROTATE_PIPE_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ROTATE_PIPE_REG STRING "1"
// Retrieval info: PRIVATE: ROTATE_REG STRING "1"
// Retrieval info: PRIVATE: ROUND3_CHAINOUT_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ROUND3_CHAINOUT_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ROUND3_CHAINOUT_MODE STRING "Enabled"
// Retrieval info: PRIVATE: ROUND3_CHAINOUT_OUT_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ROUND3_CHAINOUT_OUT_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ROUND3_CHAINOUT_OUT_REG STRING "1"
// Retrieval info: PRIVATE: ROUND3_CHAINOUT_PIPE_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ROUND3_CHAINOUT_PIPE_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ROUND3_CHAINOUT_PIPE_REG STRING "1"
// Retrieval info: PRIVATE: ROUND3_CHAINOUT_REG STRING "1"
// Retrieval info: PRIVATE: ROUND3_FRAC_WIDTH NUMERIC "27"
// Retrieval info: PRIVATE: ROUND3_OUTPUT_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ROUND3_OUTPUT_CHAINOUT_TYPE STRING "Nearest Integer"
// Retrieval info: PRIVATE: ROUND3_OUTPUT_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ROUND3_OUTPUT_MODE STRING "Disabled"
// Retrieval info: PRIVATE: ROUND3_OUTPUT_PIPE_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ROUND3_OUTPUT_PIPE_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ROUND3_OUTPUT_PIPE_REG STRING "1"
// Retrieval info: PRIVATE: ROUND3_OUTPUT_REG STRING "1"
// Retrieval info: PRIVATE: RQFORMAT STRING "Q1.15"
// Retrieval info: PRIVATE: RTS_WIDTH STRING "35"
// Retrieval info: PRIVATE: SAME_CONFIG NUMERIC "1"
// Retrieval info: PRIVATE: SAME_CONTROL_SRC_A0 NUMERIC "1"
// Retrieval info: PRIVATE: SAME_CONTROL_SRC_B0 NUMERIC "1"
// Retrieval info: PRIVATE: SAT3_CHAINOUT_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: SAT3_CHAINOUT_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: SAT3_CHAINOUT_MODE STRING "Enabled"
// Retrieval info: PRIVATE: SAT3_CHAINOUT_OUT_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: SAT3_CHAINOUT_OUT_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: SAT3_CHAINOUT_PIPE_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: SAT3_CHAINOUT_PIPE_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: SAT3_CHAINOUT_PIPE_REG STRING "1"
// Retrieval info: PRIVATE: SAT3_CHAINOUT_REG STRING "1"
// Retrieval info: PRIVATE: SAT3_FRAC_WIDTH NUMERIC "5"
// Retrieval info: PRIVATE: SAT3_OUTPUT_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: SAT3_OUTPUT_CHAINOUT_TYPE STRING "Asymmetric"
// Retrieval info: PRIVATE: SAT3_OUTPUT_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: SAT3_OUTPUT_MODE STRING "Enabled"
// Retrieval info: PRIVATE: SAT3_OUTPUT_OVERFLOW NUMERIC "0"
// Retrieval info: PRIVATE: SAT3_OUTPUT_PIPE_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: SAT3_OUTPUT_PIPE_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: SAT3_OUTPUT_PIPE_REG STRING "1"
// Retrieval info: PRIVATE: SAT3_OUTPUT_REG STRING "1"
// Retrieval info: PRIVATE: SCANOUTA NUMERIC "0"
// Retrieval info: PRIVATE: SCANOUTB NUMERIC "0"
// Retrieval info: PRIVATE: SHIFTOUTA_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: SHIFTOUTA_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: SHIFTOUTA_REG STRING "0"
// Retrieval info: PRIVATE: SHIFT_RIGHT_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: SHIFT_RIGHT_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: SHIFT_RIGHT_OUT_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: SHIFT_RIGHT_OUT_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: SHIFT_RIGHT_OUT_REG STRING "1"
// Retrieval info: PRIVATE: SHIFT_RIGHT_PIPE_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: SHIFT_RIGHT_PIPE_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: SHIFT_RIGHT_PIPE_REG STRING "1"
// Retrieval info: PRIVATE: SHIFT_RIGHT_REG STRING "1"
// Retrieval info: PRIVATE: SHIFT_ROTATE_MODE STRING "None"
// Retrieval info: PRIVATE: SIGNA STRING "SIGNED"
// Retrieval info: PRIVATE: SIGNA_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: SIGNA_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: SIGNA_PIPE_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: SIGNA_PIPE_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: SIGNA_PIPE_REG STRING "1"
// Retrieval info: PRIVATE: SIGNA_REG STRING "1"
// Retrieval info: PRIVATE: SIGNB STRING "SIGNED"
// Retrieval info: PRIVATE: SIGNB_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: SIGNB_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: SIGNB_PIPE_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: SIGNB_PIPE_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: SIGNB_PIPE_REG STRING "1"
// Retrieval info: PRIVATE: SIGNB_REG STRING "1"
// Retrieval info: PRIVATE: SRCA0 STRING "Multiplier input"
// Retrieval info: PRIVATE: SRCB0 STRING "Multiplier input"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: WIDTHA STRING "17"
// Retrieval info: PRIVATE: WIDTHB STRING "16"
// Retrieval info: PRIVATE: ZERO_CHAINOUT_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ZERO_CHAINOUT_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_CHAINOUT_REG STRING "0"
// Retrieval info: PRIVATE: ZERO_LOOPBACK_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ZERO_LOOPBACK_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_LOOPBACK_OUT_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ZERO_LOOPBACK_OUT_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_LOOPBACK_OUT_REG STRING "1"
// Retrieval info: PRIVATE: ZERO_LOOPBACK_PIPE_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ZERO_LOOPBACK_PIPE_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_LOOPBACK_PIPE_REG STRING "1"
// Retrieval info: PRIVATE: ZERO_LOOPBACK_REG STRING "1"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ACCUMULATOR STRING "NO"
// Retrieval info: CONSTANT: ADDNSUB_MULTIPLIER_ACLR1 STRING "UNUSED"
// Retrieval info: CONSTANT: ADDNSUB_MULTIPLIER_PIPELINE_ACLR1 STRING "UNUSED"
// Retrieval info: CONSTANT: ADDNSUB_MULTIPLIER_PIPELINE_REGISTER1 STRING "CLOCK0"
// Retrieval info: CONSTANT: ADDNSUB_MULTIPLIER_REGISTER1 STRING "CLOCK0"
// Retrieval info: CONSTANT: CHAINOUT_ADDER STRING "NO"
// Retrieval info: CONSTANT: CHAINOUT_REGISTER STRING "UNREGISTERED"
// Retrieval info: CONSTANT: DEDICATED_MULTIPLIER_CIRCUITRY STRING "YES"
// Retrieval info: CONSTANT: INPUT_ACLR_A0 STRING "UNUSED"
// Retrieval info: CONSTANT: INPUT_ACLR_A1 STRING "UNUSED"
// Retrieval info: CONSTANT: INPUT_ACLR_B0 STRING "UNUSED"
// Retrieval info: CONSTANT: INPUT_ACLR_B1 STRING "UNUSED"
// Retrieval info: CONSTANT: INPUT_REGISTER_A0 STRING "CLOCK0"
// Retrieval info: CONSTANT: INPUT_REGISTER_A1 STRING "CLOCK0"
// Retrieval info: CONSTANT: INPUT_REGISTER_B0 STRING "CLOCK0"
// Retrieval info: CONSTANT: INPUT_REGISTER_B1 STRING "CLOCK0"
// Retrieval info: CONSTANT: INPUT_SOURCE_A0 STRING "DATAA"
// Retrieval info: CONSTANT: INPUT_SOURCE_A1 STRING "DATAA"
// Retrieval info: CONSTANT: INPUT_SOURCE_B0 STRING "DATAB"
// Retrieval info: CONSTANT: INPUT_SOURCE_B1 STRING "DATAB"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altmult_add"
// Retrieval info: CONSTANT: MULTIPLIER1_DIRECTION STRING "ADD"
// Retrieval info: CONSTANT: MULTIPLIER_ACLR0 STRING "UNUSED"
// Retrieval info: CONSTANT: MULTIPLIER_ACLR1 STRING "UNUSED"
// Retrieval info: CONSTANT: MULTIPLIER_REGISTER0 STRING "CLOCK0"
// Retrieval info: CONSTANT: MULTIPLIER_REGISTER1 STRING "CLOCK0"
// Retrieval info: CONSTANT: NUMBER_OF_MULTIPLIERS NUMERIC "2"
// Retrieval info: CONSTANT: OUTPUT_ACLR STRING "UNUSED"
// Retrieval info: CONSTANT: OUTPUT_REGISTER STRING "CLOCK0"
// Retrieval info: CONSTANT: PORT_ADDNSUB1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SIGNA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SIGNB STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: REPRESENTATION_A STRING "SIGNED"
// Retrieval info: CONSTANT: REPRESENTATION_B STRING "SIGNED"
// Retrieval info: CONSTANT: SIGNED_ACLR_A STRING "UNUSED"
// Retrieval info: CONSTANT: SIGNED_ACLR_B STRING "UNUSED"
// Retrieval info: CONSTANT: SIGNED_PIPELINE_ACLR_A STRING "UNUSED"
// Retrieval info: CONSTANT: SIGNED_PIPELINE_ACLR_B STRING "UNUSED"
// Retrieval info: CONSTANT: SIGNED_PIPELINE_REGISTER_A STRING "CLOCK0"
// Retrieval info: CONSTANT: SIGNED_PIPELINE_REGISTER_B STRING "CLOCK0"
// Retrieval info: CONSTANT: SIGNED_REGISTER_A STRING "CLOCK0"
// Retrieval info: CONSTANT: SIGNED_REGISTER_B STRING "CLOCK0"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "17"
// Retrieval info: CONSTANT: WIDTH_B NUMERIC "16"
// Retrieval info: CONSTANT: WIDTH_CHAININ NUMERIC "1"
// Retrieval info: CONSTANT: WIDTH_RESULT NUMERIC "35"
// Retrieval info: CONSTANT: ZERO_CHAINOUT_OUTPUT_REGISTER STRING "UNREGISTERED"
// Retrieval info: CONSTANT: ZERO_LOOPBACK_ACLR STRING "UNUSED"
// Retrieval info: CONSTANT: ZERO_LOOPBACK_OUTPUT_ACLR STRING "UNUSED"
// Retrieval info: CONSTANT: ZERO_LOOPBACK_OUTPUT_REGISTER STRING "CLOCK0"
// Retrieval info: CONSTANT: ZERO_LOOPBACK_PIPELINE_ACLR STRING "UNUSED"
// Retrieval info: CONSTANT: ZERO_LOOPBACK_PIPELINE_REGISTER STRING "CLOCK0"
// Retrieval info: CONSTANT: ZERO_LOOPBACK_REGISTER STRING "CLOCK0"
// Retrieval info: USED_PORT: clock0 0 0 0 0 INPUT VCC "clock0"
// Retrieval info: USED_PORT: dataa_0 0 0 17 0 INPUT GND "dataa_0[16..0]"
// Retrieval info: USED_PORT: dataa_1 0 0 17 0 INPUT GND "dataa_1[16..0]"
// Retrieval info: USED_PORT: datab_0 0 0 16 0 INPUT GND "datab_0[15..0]"
// Retrieval info: USED_PORT: datab_1 0 0 16 0 INPUT GND "datab_1[15..0]"
// Retrieval info: USED_PORT: ena0 0 0 0 0 INPUT VCC "ena0"
// Retrieval info: USED_PORT: result 0 0 35 0 OUTPUT GND "result[34..0]"
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock0 0 0 0 0
// Retrieval info: CONNECT: @dataa 0 0 17 0 dataa_0 0 0 17 0
// Retrieval info: CONNECT: @dataa 0 0 17 17 dataa_1 0 0 17 0
// Retrieval info: CONNECT: @datab 0 0 16 0 datab_0 0 0 16 0
// Retrieval info: CONNECT: @datab 0 0 16 16 datab_1 0 0 16 0
// Retrieval info: CONNECT: @ena0 0 0 0 0 ena0 0 0 0 0
// Retrieval info: CONNECT: result 0 0 35 0 @result 0 0 35 0
// Retrieval info: GEN_FILE: TYPE_NORMAL dsp_2mult_add.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL dsp_2mult_add.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL dsp_2mult_add.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL dsp_2mult_add.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL dsp_2mult_add_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL dsp_2mult_add_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
// megafunction wizard: %ALTMULT_ADD%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: ALTMULT_ADD
// ============================================================
// File Name: dsp_2mult_add.v
// Megafunction Name(s):
// ALTMULT_ADD
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 12.1 Build 177 11/07/2012 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2012 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module dsp_2mult_add (
clock0,
dataa_0,
dataa_1,
datab_0,
datab_1,
ena0,
result);
input clock0;
input [16:0] dataa_0;
input [16:0] dataa_1;
input [15:0] datab_0;
input [15:0] datab_1;
input ena0;
output [34:0] result;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock0;
tri0 [16:0] dataa_0;
tri0 [16:0] dataa_1;
tri0 [15:0] datab_0;
tri0 [15:0] datab_1;
tri1 ena0;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ACCUM_DIRECTION STRING "Add"
// Retrieval info: PRIVATE: ACCUM_SLOAD_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ACCUM_SLOAD_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ACCUM_SLOAD_PIPE_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ACCUM_SLOAD_PIPE_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ACCUM_SLOAD_PIPE_REG STRING "1"
// Retrieval info: PRIVATE: ACCUM_SLOAD_REG STRING "1"
// Retrieval info: PRIVATE: ADDNSUB1_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ADDNSUB1_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ADDNSUB1_PIPE_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ADDNSUB1_PIPE_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ADDNSUB1_PIPE_REG STRING "1"
// Retrieval info: PRIVATE: ADDNSUB1_REG STRING "1"
// Retrieval info: PRIVATE: ADDNSUB3_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ADDNSUB3_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ADDNSUB3_PIPE_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ADDNSUB3_PIPE_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ADDNSUB3_PIPE_REG STRING "1"
// Retrieval info: PRIVATE: ADDNSUB3_REG STRING "1"
// Retrieval info: PRIVATE: ADD_ENABLE NUMERIC "1"
// Retrieval info: PRIVATE: ALL_REG_ACLR NUMERIC "0"
// Retrieval info: PRIVATE: A_ACLR_SRC_MULT0 NUMERIC "3"
// Retrieval info: PRIVATE: A_CLK_SRC_MULT0 NUMERIC "0"
// Retrieval info: PRIVATE: B_ACLR_SRC_MULT0 NUMERIC "3"
// Retrieval info: PRIVATE: B_CLK_SRC_MULT0 NUMERIC "0"
// Retrieval info: PRIVATE: CHAINOUT_OUTPUT_ACLR NUMERIC "3"
// Retrieval info: PRIVATE: CHAINOUT_OUTPUT_REG STRING "0"
// Retrieval info: PRIVATE: CHAINOUT_OUTPUT_REGISTER NUMERIC "0"
// Retrieval info: PRIVATE: CHAINOUT_OUTPUT_REGISTERED NUMERIC "0"
// Retrieval info: PRIVATE: CHAS_ZERO_CHAINOUT NUMERIC "0"
// Retrieval info: PRIVATE: HAS_ACCUMULATOR NUMERIC "0"
// Retrieval info: PRIVATE: HAS_ACUMM_SLOAD NUMERIC "0"
// Retrieval info: PRIVATE: HAS_CHAININ_PORT NUMERIC "0"
// Retrieval info: PRIVATE: HAS_CHAINOUT_ADDER NUMERIC "0"
// Retrieval info: PRIVATE: HAS_LOOPBACK NUMERIC "0"
// Retrieval info: PRIVATE: HAS_MAC STRING "0"
// Retrieval info: PRIVATE: HAS_SAT_ROUND STRING "0"
// Retrieval info: PRIVATE: HAS_ZERO_LOOPBACK NUMERIC "0"
// Retrieval info: PRIVATE: IMPL_STYLE_DEDICATED NUMERIC "1"
// Retrieval info: PRIVATE: IMPL_STYLE_DEFAULT NUMERIC "0"
// Retrieval info: PRIVATE: IMPL_STYLE_LCELL NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
// Retrieval info: PRIVATE: MULT_REGA0 NUMERIC "1"
// Retrieval info: PRIVATE: MULT_REGB0 NUMERIC "1"
// Retrieval info: PRIVATE: MULT_REGOUT0 NUMERIC "1"
// Retrieval info: PRIVATE: NUM_MULT STRING "2"
// Retrieval info: PRIVATE: OP1 STRING "Add"
// Retrieval info: PRIVATE: OP3 STRING "Add"
// Retrieval info: PRIVATE: OUTPUT_EXTRA_LAT NUMERIC "0"
// Retrieval info: PRIVATE: OUTPUT_REG_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: OUTPUT_REG_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: Q_ACLR_SRC_MULT0 NUMERIC "3"
// Retrieval info: PRIVATE: Q_CLK_SRC_MULT0 NUMERIC "0"
// Retrieval info: PRIVATE: REG_OUT NUMERIC "1"
// Retrieval info: PRIVATE: RNFORMAT STRING "35"
// Retrieval info: PRIVATE: ROTATE_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ROTATE_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ROTATE_OUT_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ROTATE_OUT_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ROTATE_OUT_REG STRING "1"
// Retrieval info: PRIVATE: ROTATE_PIPE_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ROTATE_PIPE_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ROTATE_PIPE_REG STRING "1"
// Retrieval info: PRIVATE: ROTATE_REG STRING "1"
// Retrieval info: PRIVATE: ROUND3_CHAINOUT_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ROUND3_CHAINOUT_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ROUND3_CHAINOUT_MODE STRING "Enabled"
// Retrieval info: PRIVATE: ROUND3_CHAINOUT_OUT_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ROUND3_CHAINOUT_OUT_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ROUND3_CHAINOUT_OUT_REG STRING "1"
// Retrieval info: PRIVATE: ROUND3_CHAINOUT_PIPE_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ROUND3_CHAINOUT_PIPE_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ROUND3_CHAINOUT_PIPE_REG STRING "1"
// Retrieval info: PRIVATE: ROUND3_CHAINOUT_REG STRING "1"
// Retrieval info: PRIVATE: ROUND3_FRAC_WIDTH NUMERIC "27"
// Retrieval info: PRIVATE: ROUND3_OUTPUT_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ROUND3_OUTPUT_CHAINOUT_TYPE STRING "Nearest Integer"
// Retrieval info: PRIVATE: ROUND3_OUTPUT_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ROUND3_OUTPUT_MODE STRING "Disabled"
// Retrieval info: PRIVATE: ROUND3_OUTPUT_PIPE_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ROUND3_OUTPUT_PIPE_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ROUND3_OUTPUT_PIPE_REG STRING "1"
// Retrieval info: PRIVATE: ROUND3_OUTPUT_REG STRING "1"
// Retrieval info: PRIVATE: RQFORMAT STRING "Q1.15"
// Retrieval info: PRIVATE: RTS_WIDTH STRING "35"
// Retrieval info: PRIVATE: SAME_CONFIG NUMERIC "1"
// Retrieval info: PRIVATE: SAME_CONTROL_SRC_A0 NUMERIC "1"
// Retrieval info: PRIVATE: SAME_CONTROL_SRC_B0 NUMERIC "1"
// Retrieval info: PRIVATE: SAT3_CHAINOUT_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: SAT3_CHAINOUT_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: SAT3_CHAINOUT_MODE STRING "Enabled"
// Retrieval info: PRIVATE: SAT3_CHAINOUT_OUT_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: SAT3_CHAINOUT_OUT_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: SAT3_CHAINOUT_PIPE_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: SAT3_CHAINOUT_PIPE_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: SAT3_CHAINOUT_PIPE_REG STRING "1"
// Retrieval info: PRIVATE: SAT3_CHAINOUT_REG STRING "1"
// Retrieval info: PRIVATE: SAT3_FRAC_WIDTH NUMERIC "5"
// Retrieval info: PRIVATE: SAT3_OUTPUT_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: SAT3_OUTPUT_CHAINOUT_TYPE STRING "Asymmetric"
// Retrieval info: PRIVATE: SAT3_OUTPUT_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: SAT3_OUTPUT_MODE STRING "Enabled"
// Retrieval info: PRIVATE: SAT3_OUTPUT_OVERFLOW NUMERIC "0"
// Retrieval info: PRIVATE: SAT3_OUTPUT_PIPE_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: SAT3_OUTPUT_PIPE_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: SAT3_OUTPUT_PIPE_REG STRING "1"
// Retrieval info: PRIVATE: SAT3_OUTPUT_REG STRING "1"
// Retrieval info: PRIVATE: SCANOUTA NUMERIC "0"
// Retrieval info: PRIVATE: SCANOUTB NUMERIC "0"
// Retrieval info: PRIVATE: SHIFTOUTA_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: SHIFTOUTA_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: SHIFTOUTA_REG STRING "0"
// Retrieval info: PRIVATE: SHIFT_RIGHT_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: SHIFT_RIGHT_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: SHIFT_RIGHT_OUT_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: SHIFT_RIGHT_OUT_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: SHIFT_RIGHT_OUT_REG STRING "1"
// Retrieval info: PRIVATE: SHIFT_RIGHT_PIPE_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: SHIFT_RIGHT_PIPE_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: SHIFT_RIGHT_PIPE_REG STRING "1"
// Retrieval info: PRIVATE: SHIFT_RIGHT_REG STRING "1"
// Retrieval info: PRIVATE: SHIFT_ROTATE_MODE STRING "None"
// Retrieval info: PRIVATE: SIGNA STRING "SIGNED"
// Retrieval info: PRIVATE: SIGNA_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: SIGNA_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: SIGNA_PIPE_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: SIGNA_PIPE_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: SIGNA_PIPE_REG STRING "1"
// Retrieval info: PRIVATE: SIGNA_REG STRING "1"
// Retrieval info: PRIVATE: SIGNB STRING "SIGNED"
// Retrieval info: PRIVATE: SIGNB_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: SIGNB_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: SIGNB_PIPE_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: SIGNB_PIPE_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: SIGNB_PIPE_REG STRING "1"
// Retrieval info: PRIVATE: SIGNB_REG STRING "1"
// Retrieval info: PRIVATE: SRCA0 STRING "Multiplier input"
// Retrieval info: PRIVATE: SRCB0 STRING "Multiplier input"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: WIDTHA STRING "17"
// Retrieval info: PRIVATE: WIDTHB STRING "16"
// Retrieval info: PRIVATE: ZERO_CHAINOUT_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ZERO_CHAINOUT_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_CHAINOUT_REG STRING "0"
// Retrieval info: PRIVATE: ZERO_LOOPBACK_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ZERO_LOOPBACK_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_LOOPBACK_OUT_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ZERO_LOOPBACK_OUT_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_LOOPBACK_OUT_REG STRING "1"
// Retrieval info: PRIVATE: ZERO_LOOPBACK_PIPE_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ZERO_LOOPBACK_PIPE_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_LOOPBACK_PIPE_REG STRING "1"
// Retrieval info: PRIVATE: ZERO_LOOPBACK_REG STRING "1"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ACCUMULATOR STRING "NO"
// Retrieval info: CONSTANT: ADDNSUB_MULTIPLIER_ACLR1 STRING "UNUSED"
// Retrieval info: CONSTANT: ADDNSUB_MULTIPLIER_PIPELINE_ACLR1 STRING "UNUSED"
// Retrieval info: CONSTANT: ADDNSUB_MULTIPLIER_PIPELINE_REGISTER1 STRING "CLOCK0"
// Retrieval info: CONSTANT: ADDNSUB_MULTIPLIER_REGISTER1 STRING "CLOCK0"
// Retrieval info: CONSTANT: CHAINOUT_ADDER STRING "NO"
// Retrieval info: CONSTANT: CHAINOUT_REGISTER STRING "UNREGISTERED"
// Retrieval info: CONSTANT: DEDICATED_MULTIPLIER_CIRCUITRY STRING "YES"
// Retrieval info: CONSTANT: INPUT_ACLR_A0 STRING "UNUSED"
// Retrieval info: CONSTANT: INPUT_ACLR_A1 STRING "UNUSED"
// Retrieval info: CONSTANT: INPUT_ACLR_B0 STRING "UNUSED"
// Retrieval info: CONSTANT: INPUT_ACLR_B1 STRING "UNUSED"
// Retrieval info: CONSTANT: INPUT_REGISTER_A0 STRING "CLOCK0"
// Retrieval info: CONSTANT: INPUT_REGISTER_A1 STRING "CLOCK0"
// Retrieval info: CONSTANT: INPUT_REGISTER_B0 STRING "CLOCK0"
// Retrieval info: CONSTANT: INPUT_REGISTER_B1 STRING "CLOCK0"
// Retrieval info: CONSTANT: INPUT_SOURCE_A0 STRING "DATAA"
// Retrieval info: CONSTANT: INPUT_SOURCE_A1 STRING "DATAA"
// Retrieval info: CONSTANT: INPUT_SOURCE_B0 STRING "DATAB"
// Retrieval info: CONSTANT: INPUT_SOURCE_B1 STRING "DATAB"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altmult_add"
// Retrieval info: CONSTANT: MULTIPLIER1_DIRECTION STRING "ADD"
// Retrieval info: CONSTANT: MULTIPLIER_ACLR0 STRING "UNUSED"
// Retrieval info: CONSTANT: MULTIPLIER_ACLR1 STRING "UNUSED"
// Retrieval info: CONSTANT: MULTIPLIER_REGISTER0 STRING "CLOCK0"
// Retrieval info: CONSTANT: MULTIPLIER_REGISTER1 STRING "CLOCK0"
// Retrieval info: CONSTANT: NUMBER_OF_MULTIPLIERS NUMERIC "2"
// Retrieval info: CONSTANT: OUTPUT_ACLR STRING "UNUSED"
// Retrieval info: CONSTANT: OUTPUT_REGISTER STRING "CLOCK0"
// Retrieval info: CONSTANT: PORT_ADDNSUB1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SIGNA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SIGNB STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: REPRESENTATION_A STRING "SIGNED"
// Retrieval info: CONSTANT: REPRESENTATION_B STRING "SIGNED"
// Retrieval info: CONSTANT: SIGNED_ACLR_A STRING "UNUSED"
// Retrieval info: CONSTANT: SIGNED_ACLR_B STRING "UNUSED"
// Retrieval info: CONSTANT: SIGNED_PIPELINE_ACLR_A STRING "UNUSED"
// Retrieval info: CONSTANT: SIGNED_PIPELINE_ACLR_B STRING "UNUSED"
// Retrieval info: CONSTANT: SIGNED_PIPELINE_REGISTER_A STRING "CLOCK0"
// Retrieval info: CONSTANT: SIGNED_PIPELINE_REGISTER_B STRING "CLOCK0"
// Retrieval info: CONSTANT: SIGNED_REGISTER_A STRING "CLOCK0"
// Retrieval info: CONSTANT: SIGNED_REGISTER_B STRING "CLOCK0"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "17"
// Retrieval info: CONSTANT: WIDTH_B NUMERIC "16"
// Retrieval info: CONSTANT: WIDTH_CHAININ NUMERIC "1"
// Retrieval info: CONSTANT: WIDTH_RESULT NUMERIC "35"
// Retrieval info: CONSTANT: ZERO_CHAINOUT_OUTPUT_REGISTER STRING "UNREGISTERED"
// Retrieval info: CONSTANT: ZERO_LOOPBACK_ACLR STRING "UNUSED"
// Retrieval info: CONSTANT: ZERO_LOOPBACK_OUTPUT_ACLR STRING "UNUSED"
// Retrieval info: CONSTANT: ZERO_LOOPBACK_OUTPUT_REGISTER STRING "CLOCK0"
// Retrieval info: CONSTANT: ZERO_LOOPBACK_PIPELINE_ACLR STRING "UNUSED"
// Retrieval info: CONSTANT: ZERO_LOOPBACK_PIPELINE_REGISTER STRING "CLOCK0"
// Retrieval info: CONSTANT: ZERO_LOOPBACK_REGISTER STRING "CLOCK0"
// Retrieval info: USED_PORT: clock0 0 0 0 0 INPUT VCC "clock0"
// Retrieval info: USED_PORT: dataa_0 0 0 17 0 INPUT GND "dataa_0[16..0]"
// Retrieval info: USED_PORT: dataa_1 0 0 17 0 INPUT GND "dataa_1[16..0]"
// Retrieval info: USED_PORT: datab_0 0 0 16 0 INPUT GND "datab_0[15..0]"
// Retrieval info: USED_PORT: datab_1 0 0 16 0 INPUT GND "datab_1[15..0]"
// Retrieval info: USED_PORT: ena0 0 0 0 0 INPUT VCC "ena0"
// Retrieval info: USED_PORT: result 0 0 35 0 OUTPUT GND "result[34..0]"
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock0 0 0 0 0
// Retrieval info: CONNECT: @dataa 0 0 17 0 dataa_0 0 0 17 0
// Retrieval info: CONNECT: @dataa 0 0 17 17 dataa_1 0 0 17 0
// Retrieval info: CONNECT: @datab 0 0 16 0 datab_0 0 0 16 0
// Retrieval info: CONNECT: @datab 0 0 16 16 datab_1 0 0 16 0
// Retrieval info: CONNECT: @ena0 0 0 0 0 ena0 0 0 0 0
// Retrieval info: CONNECT: result 0 0 35 0 @result 0 0 35 0
// Retrieval info: GEN_FILE: TYPE_NORMAL dsp_2mult_add.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL dsp_2mult_add.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL dsp_2mult_add.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL dsp_2mult_add.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL dsp_2mult_add_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL dsp_2mult_add_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
dsp_2mult_add dsp_2mult_add_inst (
.clock0 ( clock0_sig ),
.dataa_0 ( dataa_0_sig ),
.dataa_1 ( dataa_1_sig ),
.datab_0 ( datab_0_sig ),
.datab_1 ( datab_1_sig ),
.ena0 ( ena0_sig ),
.result ( result_sig )
);
|
// megafunction wizard: %ALTMULT_ADD%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: ALTMULT_ADD
// ============================================================
// File Name: dsp_4mult_add.v
// Megafunction Name(s):
// ALTMULT_ADD
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 12.1 Build 177 11/07/2012 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2012 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module dsp_4mult_add (
chainin,
clock0,
dataa_0,
dataa_1,
dataa_2,
dataa_3,
datab_0,
datab_1,
datab_2,
datab_3,
ena0,
result);
input [43:0] chainin;
input clock0;
input [16:0] dataa_0;
input [16:0] dataa_1;
input [16:0] dataa_2;
input [16:0] dataa_3;
input [15:0] datab_0;
input [15:0] datab_1;
input [15:0] datab_2;
input [15:0] datab_3;
input ena0;
output [43:0] result;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 [43:0] chainin;
tri1 clock0;
tri0 [16:0] dataa_0;
tri0 [16:0] dataa_1;
tri0 [16:0] dataa_2;
tri0 [16:0] dataa_3;
tri0 [15:0] datab_0;
tri0 [15:0] datab_1;
tri0 [15:0] datab_2;
tri0 [15:0] datab_3;
tri1 ena0;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [43:0] sub_wire0;
wire [16:0] sub_wire10 = dataa_3[16:0];
wire [16:0] sub_wire9 = dataa_2[16:0];
wire [16:0] sub_wire8 = dataa_1[16:0];
wire [15:0] sub_wire5 = datab_3[15:0];
wire [15:0] sub_wire4 = datab_2[15:0];
wire [15:0] sub_wire3 = datab_1[15:0];
wire [43:0] result = sub_wire0[43:0];
wire [15:0] sub_wire1 = datab_0[15:0];
wire [63:0] sub_wire2 = {sub_wire5, sub_wire4, sub_wire3, sub_wire1};
wire [16:0] sub_wire6 = dataa_0[16:0];
wire [67:0] sub_wire7 = {sub_wire10, sub_wire9, sub_wire8, sub_wire6};
altmult_add ALTMULT_ADD_component (
.chainin (chainin),
.clock0 (clock0),
.datab (sub_wire2),
.ena0 (ena0),
.dataa (sub_wire7),
.result (sub_wire0),
.accum_sload (1'b0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.aclr2 (1'b0),
.aclr3 (1'b0),
.addnsub1 (1'b1),
.addnsub1_round (1'b0),
.addnsub3 (1'b1),
.addnsub3_round (1'b0),
.chainout_round (1'b0),
.chainout_sat_overflow (),
.chainout_saturate (1'b0),
.clock1 (1'b1),
.clock2 (1'b1),
.clock3 (1'b1),
.coefsel0 ({3{1'b0}}),
.coefsel1 ({3{1'b0}}),
.coefsel2 ({3{1'b0}}),
.coefsel3 ({3{1'b0}}),
.datac ({88{1'b0}}),
.ena1 (1'b1),
.ena2 (1'b1),
.ena3 (1'b1),
.mult01_round (1'b0),
.mult01_saturation (1'b0),
.mult0_is_saturated (),
.mult1_is_saturated (),
.mult23_round (1'b0),
.mult23_saturation (1'b0),
.mult2_is_saturated (),
.mult3_is_saturated (),
.output_round (1'b0),
.output_saturate (1'b0),
.overflow (),
.rotate (1'b0),
.scanina ({17{1'b0}}),
.scaninb ({16{1'b0}}),
.scanouta (),
.scanoutb (),
.shift_right (1'b0),
.signa (1'b0),
.signb (1'b0),
.sourcea ({4{1'b0}}),
.sourceb ({4{1'b0}}),
.zero_chainout (1'b0),
.zero_loopback (1'b0));
defparam
ALTMULT_ADD_component.accumulator = "NO",
ALTMULT_ADD_component.addnsub_multiplier_aclr1 = "UNUSED",
ALTMULT_ADD_component.addnsub_multiplier_aclr3 = "UNUSED",
ALTMULT_ADD_component.addnsub_multiplier_pipeline_aclr1 = "UNUSED",
ALTMULT_ADD_component.addnsub_multiplier_pipeline_aclr3 = "UNUSED",
ALTMULT_ADD_component.addnsub_multiplier_pipeline_register1 = "CLOCK0",
ALTMULT_ADD_component.addnsub_multiplier_pipeline_register3 = "CLOCK0",
ALTMULT_ADD_component.addnsub_multiplier_register1 = "CLOCK0",
ALTMULT_ADD_component.addnsub_multiplier_register3 = "CLOCK0",
ALTMULT_ADD_component.chainout_aclr = "UNUSED",
ALTMULT_ADD_component.chainout_adder = "YES",
ALTMULT_ADD_component.chainout_register = "CLOCK0",
ALTMULT_ADD_component.dedicated_multiplier_circuitry = "YES",
ALTMULT_ADD_component.input_aclr_a0 = "UNUSED",
ALTMULT_ADD_component.input_aclr_a1 = "UNUSED",
ALTMULT_ADD_component.input_aclr_a2 = "UNUSED",
ALTMULT_ADD_component.input_aclr_a3 = "UNUSED",
ALTMULT_ADD_component.input_aclr_b0 = "UNUSED",
ALTMULT_ADD_component.input_aclr_b1 = "UNUSED",
ALTMULT_ADD_component.input_aclr_b2 = "UNUSED",
ALTMULT_ADD_component.input_aclr_b3 = "UNUSED",
ALTMULT_ADD_component.input_register_a0 = "CLOCK0",
ALTMULT_ADD_component.input_register_a1 = "CLOCK0",
ALTMULT_ADD_component.input_register_a2 = "CLOCK0",
ALTMULT_ADD_component.input_register_a3 = "CLOCK0",
ALTMULT_ADD_component.input_register_b0 = "CLOCK0",
ALTMULT_ADD_component.input_register_b1 = "CLOCK0",
ALTMULT_ADD_component.input_register_b2 = "CLOCK0",
ALTMULT_ADD_component.input_register_b3 = "CLOCK0",
ALTMULT_ADD_component.input_source_a0 = "DATAA",
ALTMULT_ADD_component.input_source_a1 = "DATAA",
ALTMULT_ADD_component.input_source_a2 = "DATAA",
ALTMULT_ADD_component.input_source_a3 = "DATAA",
ALTMULT_ADD_component.input_source_b0 = "DATAB",
ALTMULT_ADD_component.input_source_b1 = "DATAB",
ALTMULT_ADD_component.input_source_b2 = "DATAB",
ALTMULT_ADD_component.input_source_b3 = "DATAB",
ALTMULT_ADD_component.intended_device_family = "Stratix IV",
ALTMULT_ADD_component.lpm_type = "altmult_add",
ALTMULT_ADD_component.multiplier1_direction = "ADD",
ALTMULT_ADD_component.multiplier3_direction = "ADD",
ALTMULT_ADD_component.multiplier_aclr0 = "UNUSED",
ALTMULT_ADD_component.multiplier_aclr1 = "UNUSED",
ALTMULT_ADD_component.multiplier_aclr2 = "UNUSED",
ALTMULT_ADD_component.multiplier_aclr3 = "UNUSED",
ALTMULT_ADD_component.multiplier_register0 = "CLOCK0",
ALTMULT_ADD_component.multiplier_register1 = "CLOCK0",
ALTMULT_ADD_component.multiplier_register2 = "CLOCK0",
ALTMULT_ADD_component.multiplier_register3 = "CLOCK0",
ALTMULT_ADD_component.number_of_multipliers = 4,
ALTMULT_ADD_component.output_aclr = "UNUSED",
ALTMULT_ADD_component.output_register = "CLOCK0",
ALTMULT_ADD_component.port_addnsub1 = "PORT_UNUSED",
ALTMULT_ADD_component.port_addnsub3 = "PORT_UNUSED",
ALTMULT_ADD_component.port_signa = "PORT_UNUSED",
ALTMULT_ADD_component.port_signb = "PORT_UNUSED",
ALTMULT_ADD_component.representation_a = "SIGNED",
ALTMULT_ADD_component.representation_b = "SIGNED",
ALTMULT_ADD_component.signed_aclr_a = "UNUSED",
ALTMULT_ADD_component.signed_aclr_b = "UNUSED",
ALTMULT_ADD_component.signed_pipeline_aclr_a = "UNUSED",
ALTMULT_ADD_component.signed_pipeline_aclr_b = "UNUSED",
ALTMULT_ADD_component.signed_pipeline_register_a = "CLOCK0",
ALTMULT_ADD_component.signed_pipeline_register_b = "CLOCK0",
ALTMULT_ADD_component.signed_register_a = "CLOCK0",
ALTMULT_ADD_component.signed_register_b = "CLOCK0",
ALTMULT_ADD_component.width_a = 17,
ALTMULT_ADD_component.width_b = 16,
ALTMULT_ADD_component.width_chainin = 44,
ALTMULT_ADD_component.width_result = 44,
ALTMULT_ADD_component.zero_chainout_output_register = "UNREGISTERED",
ALTMULT_ADD_component.zero_loopback_aclr = "UNUSED",
ALTMULT_ADD_component.zero_loopback_output_aclr = "UNUSED",
ALTMULT_ADD_component.zero_loopback_output_register = "CLOCK0",
ALTMULT_ADD_component.zero_loopback_pipeline_aclr = "UNUSED",
ALTMULT_ADD_component.zero_loopback_pipeline_register = "CLOCK0",
ALTMULT_ADD_component.zero_loopback_register = "CLOCK0";
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ACCUM_DIRECTION STRING "Add"
// Retrieval info: PRIVATE: ACCUM_SLOAD_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ACCUM_SLOAD_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ACCUM_SLOAD_PIPE_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ACCUM_SLOAD_PIPE_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ACCUM_SLOAD_PIPE_REG STRING "1"
// Retrieval info: PRIVATE: ACCUM_SLOAD_REG STRING "1"
// Retrieval info: PRIVATE: ADDNSUB1_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ADDNSUB1_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ADDNSUB1_PIPE_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ADDNSUB1_PIPE_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ADDNSUB1_PIPE_REG STRING "1"
// Retrieval info: PRIVATE: ADDNSUB1_REG STRING "1"
// Retrieval info: PRIVATE: ADDNSUB3_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ADDNSUB3_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ADDNSUB3_PIPE_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ADDNSUB3_PIPE_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ADDNSUB3_PIPE_REG STRING "1"
// Retrieval info: PRIVATE: ADDNSUB3_REG STRING "1"
// Retrieval info: PRIVATE: ADD_ENABLE NUMERIC "1"
// Retrieval info: PRIVATE: ALL_REG_ACLR NUMERIC "0"
// Retrieval info: PRIVATE: A_ACLR_SRC_MULT0 NUMERIC "3"
// Retrieval info: PRIVATE: A_CLK_SRC_MULT0 NUMERIC "0"
// Retrieval info: PRIVATE: B_ACLR_SRC_MULT0 NUMERIC "3"
// Retrieval info: PRIVATE: B_CLK_SRC_MULT0 NUMERIC "0"
// Retrieval info: PRIVATE: CHAINOUT_OUTPUT_ACLR NUMERIC "3"
// Retrieval info: PRIVATE: CHAINOUT_OUTPUT_REG STRING "1"
// Retrieval info: PRIVATE: CHAINOUT_OUTPUT_REGISTER NUMERIC "0"
// Retrieval info: PRIVATE: CHAINOUT_OUTPUT_REGISTERED NUMERIC "1"
// Retrieval info: PRIVATE: CHAS_ZERO_CHAINOUT NUMERIC "0"
// Retrieval info: PRIVATE: HAS_ACCUMULATOR NUMERIC "0"
// Retrieval info: PRIVATE: HAS_ACUMM_SLOAD NUMERIC "0"
// Retrieval info: PRIVATE: HAS_CHAININ_PORT NUMERIC "1"
// Retrieval info: PRIVATE: HAS_CHAINOUT_ADDER NUMERIC "1"
// Retrieval info: PRIVATE: HAS_LOOPBACK NUMERIC "0"
// Retrieval info: PRIVATE: HAS_MAC STRING "0"
// Retrieval info: PRIVATE: HAS_SAT_ROUND STRING "0"
// Retrieval info: PRIVATE: HAS_ZERO_LOOPBACK NUMERIC "0"
// Retrieval info: PRIVATE: IMPL_STYLE_DEDICATED NUMERIC "1"
// Retrieval info: PRIVATE: IMPL_STYLE_DEFAULT NUMERIC "0"
// Retrieval info: PRIVATE: IMPL_STYLE_LCELL NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
// Retrieval info: PRIVATE: MULT_REGA0 NUMERIC "1"
// Retrieval info: PRIVATE: MULT_REGB0 NUMERIC "1"
// Retrieval info: PRIVATE: MULT_REGOUT0 NUMERIC "1"
// Retrieval info: PRIVATE: NUM_MULT STRING "4"
// Retrieval info: PRIVATE: OP1 STRING "Add"
// Retrieval info: PRIVATE: OP3 STRING "Add"
// Retrieval info: PRIVATE: OUTPUT_EXTRA_LAT NUMERIC "0"
// Retrieval info: PRIVATE: OUTPUT_REG_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: OUTPUT_REG_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: Q_ACLR_SRC_MULT0 NUMERIC "3"
// Retrieval info: PRIVATE: Q_CLK_SRC_MULT0 NUMERIC "0"
// Retrieval info: PRIVATE: REG_OUT NUMERIC "1"
// Retrieval info: PRIVATE: RNFORMAT STRING "44"
// Retrieval info: PRIVATE: ROTATE_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ROTATE_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ROTATE_OUT_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ROTATE_OUT_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ROTATE_OUT_REG STRING "1"
// Retrieval info: PRIVATE: ROTATE_PIPE_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ROTATE_PIPE_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ROTATE_PIPE_REG STRING "1"
// Retrieval info: PRIVATE: ROTATE_REG STRING "1"
// Retrieval info: PRIVATE: ROUND3_CHAINOUT_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ROUND3_CHAINOUT_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ROUND3_CHAINOUT_MODE STRING "Enabled"
// Retrieval info: PRIVATE: ROUND3_CHAINOUT_OUT_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ROUND3_CHAINOUT_OUT_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ROUND3_CHAINOUT_OUT_REG STRING "1"
// Retrieval info: PRIVATE: ROUND3_CHAINOUT_PIPE_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ROUND3_CHAINOUT_PIPE_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ROUND3_CHAINOUT_PIPE_REG STRING "1"
// Retrieval info: PRIVATE: ROUND3_CHAINOUT_REG STRING "1"
// Retrieval info: PRIVATE: ROUND3_FRAC_WIDTH NUMERIC "27"
// Retrieval info: PRIVATE: ROUND3_OUTPUT_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ROUND3_OUTPUT_CHAINOUT_TYPE STRING "Nearest Integer"
// Retrieval info: PRIVATE: ROUND3_OUTPUT_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ROUND3_OUTPUT_MODE STRING "Disabled"
// Retrieval info: PRIVATE: ROUND3_OUTPUT_PIPE_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ROUND3_OUTPUT_PIPE_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ROUND3_OUTPUT_PIPE_REG STRING "1"
// Retrieval info: PRIVATE: ROUND3_OUTPUT_REG STRING "1"
// Retrieval info: PRIVATE: RQFORMAT STRING "Q1.15"
// Retrieval info: PRIVATE: RTS_WIDTH STRING "44"
// Retrieval info: PRIVATE: SAME_CONFIG NUMERIC "1"
// Retrieval info: PRIVATE: SAME_CONTROL_SRC_A0 NUMERIC "1"
// Retrieval info: PRIVATE: SAME_CONTROL_SRC_B0 NUMERIC "1"
// Retrieval info: PRIVATE: SAT3_CHAINOUT_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: SAT3_CHAINOUT_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: SAT3_CHAINOUT_MODE STRING "Enabled"
// Retrieval info: PRIVATE: SAT3_CHAINOUT_OUT_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: SAT3_CHAINOUT_OUT_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: SAT3_CHAINOUT_OVERFLOW NUMERIC "0"
// Retrieval info: PRIVATE: SAT3_CHAINOUT_PIPE_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: SAT3_CHAINOUT_PIPE_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: SAT3_CHAINOUT_PIPE_REG STRING "1"
// Retrieval info: PRIVATE: SAT3_CHAINOUT_REG STRING "1"
// Retrieval info: PRIVATE: SAT3_FRAC_WIDTH NUMERIC "2"
// Retrieval info: PRIVATE: SAT3_OUTPUT_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: SAT3_OUTPUT_CHAINOUT_TYPE STRING "Asymmetric"
// Retrieval info: PRIVATE: SAT3_OUTPUT_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: SAT3_OUTPUT_MODE STRING "Enabled"
// Retrieval info: PRIVATE: SAT3_OUTPUT_OVERFLOW NUMERIC "0"
// Retrieval info: PRIVATE: SAT3_OUTPUT_PIPE_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: SAT3_OUTPUT_PIPE_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: SAT3_OUTPUT_PIPE_REG STRING "1"
// Retrieval info: PRIVATE: SAT3_OUTPUT_REG STRING "1"
// Retrieval info: PRIVATE: SCANOUTA NUMERIC "0"
// Retrieval info: PRIVATE: SCANOUTB NUMERIC "0"
// Retrieval info: PRIVATE: SHIFTOUTA_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: SHIFTOUTA_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: SHIFTOUTA_REG STRING "0"
// Retrieval info: PRIVATE: SHIFT_RIGHT_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: SHIFT_RIGHT_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: SHIFT_RIGHT_OUT_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: SHIFT_RIGHT_OUT_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: SHIFT_RIGHT_OUT_REG STRING "1"
// Retrieval info: PRIVATE: SHIFT_RIGHT_PIPE_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: SHIFT_RIGHT_PIPE_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: SHIFT_RIGHT_PIPE_REG STRING "1"
// Retrieval info: PRIVATE: SHIFT_RIGHT_REG STRING "1"
// Retrieval info: PRIVATE: SHIFT_ROTATE_MODE STRING "None"
// Retrieval info: PRIVATE: SIGNA STRING "SIGNED"
// Retrieval info: PRIVATE: SIGNA_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: SIGNA_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: SIGNA_PIPE_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: SIGNA_PIPE_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: SIGNA_PIPE_REG STRING "1"
// Retrieval info: PRIVATE: SIGNA_REG STRING "1"
// Retrieval info: PRIVATE: SIGNB STRING "SIGNED"
// Retrieval info: PRIVATE: SIGNB_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: SIGNB_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: SIGNB_PIPE_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: SIGNB_PIPE_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: SIGNB_PIPE_REG STRING "1"
// Retrieval info: PRIVATE: SIGNB_REG STRING "1"
// Retrieval info: PRIVATE: SRCA0 STRING "Multiplier input"
// Retrieval info: PRIVATE: SRCB0 STRING "Multiplier input"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: WIDTHA STRING "17"
// Retrieval info: PRIVATE: WIDTHB STRING "16"
// Retrieval info: PRIVATE: ZERO_CHAINOUT_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ZERO_CHAINOUT_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_CHAINOUT_REG STRING "0"
// Retrieval info: PRIVATE: ZERO_LOOPBACK_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ZERO_LOOPBACK_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_LOOPBACK_OUT_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ZERO_LOOPBACK_OUT_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_LOOPBACK_OUT_REG STRING "1"
// Retrieval info: PRIVATE: ZERO_LOOPBACK_PIPE_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ZERO_LOOPBACK_PIPE_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_LOOPBACK_PIPE_REG STRING "1"
// Retrieval info: PRIVATE: ZERO_LOOPBACK_REG STRING "1"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ACCUMULATOR STRING "NO"
// Retrieval info: CONSTANT: ADDNSUB_MULTIPLIER_ACLR1 STRING "UNUSED"
// Retrieval info: CONSTANT: ADDNSUB_MULTIPLIER_ACLR3 STRING "UNUSED"
// Retrieval info: CONSTANT: ADDNSUB_MULTIPLIER_PIPELINE_ACLR1 STRING "UNUSED"
// Retrieval info: CONSTANT: ADDNSUB_MULTIPLIER_PIPELINE_ACLR3 STRING "UNUSED"
// Retrieval info: CONSTANT: ADDNSUB_MULTIPLIER_PIPELINE_REGISTER1 STRING "CLOCK0"
// Retrieval info: CONSTANT: ADDNSUB_MULTIPLIER_PIPELINE_REGISTER3 STRING "CLOCK0"
// Retrieval info: CONSTANT: ADDNSUB_MULTIPLIER_REGISTER1 STRING "CLOCK0"
// Retrieval info: CONSTANT: ADDNSUB_MULTIPLIER_REGISTER3 STRING "CLOCK0"
// Retrieval info: CONSTANT: CHAINOUT_ACLR STRING "UNUSED"
// Retrieval info: CONSTANT: CHAINOUT_ADDER STRING "YES"
// Retrieval info: CONSTANT: CHAINOUT_REGISTER STRING "CLOCK0"
// Retrieval info: CONSTANT: DEDICATED_MULTIPLIER_CIRCUITRY STRING "YES"
// Retrieval info: CONSTANT: INPUT_ACLR_A0 STRING "UNUSED"
// Retrieval info: CONSTANT: INPUT_ACLR_A1 STRING "UNUSED"
// Retrieval info: CONSTANT: INPUT_ACLR_A2 STRING "UNUSED"
// Retrieval info: CONSTANT: INPUT_ACLR_A3 STRING "UNUSED"
// Retrieval info: CONSTANT: INPUT_ACLR_B0 STRING "UNUSED"
// Retrieval info: CONSTANT: INPUT_ACLR_B1 STRING "UNUSED"
// Retrieval info: CONSTANT: INPUT_ACLR_B2 STRING "UNUSED"
// Retrieval info: CONSTANT: INPUT_ACLR_B3 STRING "UNUSED"
// Retrieval info: CONSTANT: INPUT_REGISTER_A0 STRING "CLOCK0"
// Retrieval info: CONSTANT: INPUT_REGISTER_A1 STRING "CLOCK0"
// Retrieval info: CONSTANT: INPUT_REGISTER_A2 STRING "CLOCK0"
// Retrieval info: CONSTANT: INPUT_REGISTER_A3 STRING "CLOCK0"
// Retrieval info: CONSTANT: INPUT_REGISTER_B0 STRING "CLOCK0"
// Retrieval info: CONSTANT: INPUT_REGISTER_B1 STRING "CLOCK0"
// Retrieval info: CONSTANT: INPUT_REGISTER_B2 STRING "CLOCK0"
// Retrieval info: CONSTANT: INPUT_REGISTER_B3 STRING "CLOCK0"
// Retrieval info: CONSTANT: INPUT_SOURCE_A0 STRING "DATAA"
// Retrieval info: CONSTANT: INPUT_SOURCE_A1 STRING "DATAA"
// Retrieval info: CONSTANT: INPUT_SOURCE_A2 STRING "DATAA"
// Retrieval info: CONSTANT: INPUT_SOURCE_A3 STRING "DATAA"
// Retrieval info: CONSTANT: INPUT_SOURCE_B0 STRING "DATAB"
// Retrieval info: CONSTANT: INPUT_SOURCE_B1 STRING "DATAB"
// Retrieval info: CONSTANT: INPUT_SOURCE_B2 STRING "DATAB"
// Retrieval info: CONSTANT: INPUT_SOURCE_B3 STRING "DATAB"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altmult_add"
// Retrieval info: CONSTANT: MULTIPLIER1_DIRECTION STRING "ADD"
// Retrieval info: CONSTANT: MULTIPLIER3_DIRECTION STRING "ADD"
// Retrieval info: CONSTANT: MULTIPLIER_ACLR0 STRING "UNUSED"
// Retrieval info: CONSTANT: MULTIPLIER_ACLR1 STRING "UNUSED"
// Retrieval info: CONSTANT: MULTIPLIER_ACLR2 STRING "UNUSED"
// Retrieval info: CONSTANT: MULTIPLIER_ACLR3 STRING "UNUSED"
// Retrieval info: CONSTANT: MULTIPLIER_REGISTER0 STRING "CLOCK0"
// Retrieval info: CONSTANT: MULTIPLIER_REGISTER1 STRING "CLOCK0"
// Retrieval info: CONSTANT: MULTIPLIER_REGISTER2 STRING "CLOCK0"
// Retrieval info: CONSTANT: MULTIPLIER_REGISTER3 STRING "CLOCK0"
// Retrieval info: CONSTANT: NUMBER_OF_MULTIPLIERS NUMERIC "4"
// Retrieval info: CONSTANT: OUTPUT_ACLR STRING "UNUSED"
// Retrieval info: CONSTANT: OUTPUT_REGISTER STRING "CLOCK0"
// Retrieval info: CONSTANT: PORT_ADDNSUB1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_ADDNSUB3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SIGNA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SIGNB STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: REPRESENTATION_A STRING "SIGNED"
// Retrieval info: CONSTANT: REPRESENTATION_B STRING "SIGNED"
// Retrieval info: CONSTANT: SIGNED_ACLR_A STRING "UNUSED"
// Retrieval info: CONSTANT: SIGNED_ACLR_B STRING "UNUSED"
// Retrieval info: CONSTANT: SIGNED_PIPELINE_ACLR_A STRING "UNUSED"
// Retrieval info: CONSTANT: SIGNED_PIPELINE_ACLR_B STRING "UNUSED"
// Retrieval info: CONSTANT: SIGNED_PIPELINE_REGISTER_A STRING "CLOCK0"
// Retrieval info: CONSTANT: SIGNED_PIPELINE_REGISTER_B STRING "CLOCK0"
// Retrieval info: CONSTANT: SIGNED_REGISTER_A STRING "CLOCK0"
// Retrieval info: CONSTANT: SIGNED_REGISTER_B STRING "CLOCK0"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "17"
// Retrieval info: CONSTANT: WIDTH_B NUMERIC "16"
// Retrieval info: CONSTANT: WIDTH_CHAININ NUMERIC "44"
// Retrieval info: CONSTANT: WIDTH_RESULT NUMERIC "44"
// Retrieval info: CONSTANT: ZERO_CHAINOUT_OUTPUT_REGISTER STRING "UNREGISTERED"
// Retrieval info: CONSTANT: ZERO_LOOPBACK_ACLR STRING "UNUSED"
// Retrieval info: CONSTANT: ZERO_LOOPBACK_OUTPUT_ACLR STRING "UNUSED"
// Retrieval info: CONSTANT: ZERO_LOOPBACK_OUTPUT_REGISTER STRING "CLOCK0"
// Retrieval info: CONSTANT: ZERO_LOOPBACK_PIPELINE_ACLR STRING "UNUSED"
// Retrieval info: CONSTANT: ZERO_LOOPBACK_PIPELINE_REGISTER STRING "CLOCK0"
// Retrieval info: CONSTANT: ZERO_LOOPBACK_REGISTER STRING "CLOCK0"
// Retrieval info: USED_PORT: chainin 0 0 44 0 INPUT GND "chainin[43..0]"
// Retrieval info: USED_PORT: clock0 0 0 0 0 INPUT VCC "clock0"
// Retrieval info: USED_PORT: dataa_0 0 0 17 0 INPUT GND "dataa_0[16..0]"
// Retrieval info: USED_PORT: dataa_1 0 0 17 0 INPUT GND "dataa_1[16..0]"
// Retrieval info: USED_PORT: dataa_2 0 0 17 0 INPUT GND "dataa_2[16..0]"
// Retrieval info: USED_PORT: dataa_3 0 0 17 0 INPUT GND "dataa_3[16..0]"
// Retrieval info: USED_PORT: datab_0 0 0 16 0 INPUT GND "datab_0[15..0]"
// Retrieval info: USED_PORT: datab_1 0 0 16 0 INPUT GND "datab_1[15..0]"
// Retrieval info: USED_PORT: datab_2 0 0 16 0 INPUT GND "datab_2[15..0]"
// Retrieval info: USED_PORT: datab_3 0 0 16 0 INPUT GND "datab_3[15..0]"
// Retrieval info: USED_PORT: ena0 0 0 0 0 INPUT VCC "ena0"
// Retrieval info: USED_PORT: result 0 0 44 0 OUTPUT GND "result[43..0]"
// Retrieval info: CONNECT: @chainin 0 0 44 0 chainin 0 0 44 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock0 0 0 0 0
// Retrieval info: CONNECT: @dataa 0 0 17 0 dataa_0 0 0 17 0
// Retrieval info: CONNECT: @dataa 0 0 17 17 dataa_1 0 0 17 0
// Retrieval info: CONNECT: @dataa 0 0 17 34 dataa_2 0 0 17 0
// Retrieval info: CONNECT: @dataa 0 0 17 51 dataa_3 0 0 17 0
// Retrieval info: CONNECT: @datab 0 0 16 0 datab_0 0 0 16 0
// Retrieval info: CONNECT: @datab 0 0 16 16 datab_1 0 0 16 0
// Retrieval info: CONNECT: @datab 0 0 16 32 datab_2 0 0 16 0
// Retrieval info: CONNECT: @datab 0 0 16 48 datab_3 0 0 16 0
// Retrieval info: CONNECT: @ena0 0 0 0 0 ena0 0 0 0 0
// Retrieval info: CONNECT: result 0 0 44 0 @result 0 0 44 0
// Retrieval info: GEN_FILE: TYPE_NORMAL dsp_4mult_add.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL dsp_4mult_add.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL dsp_4mult_add.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL dsp_4mult_add.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL dsp_4mult_add_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL dsp_4mult_add_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
// megafunction wizard: %ALTMULT_ADD%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: ALTMULT_ADD
// ============================================================
// File Name: dsp_4mult_add.v
// Megafunction Name(s):
// ALTMULT_ADD
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 12.1 Build 177 11/07/2012 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2012 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module dsp_4mult_add (
chainin,
clock0,
dataa_0,
dataa_1,
dataa_2,
dataa_3,
datab_0,
datab_1,
datab_2,
datab_3,
ena0,
result);
input [43:0] chainin;
input clock0;
input [16:0] dataa_0;
input [16:0] dataa_1;
input [16:0] dataa_2;
input [16:0] dataa_3;
input [15:0] datab_0;
input [15:0] datab_1;
input [15:0] datab_2;
input [15:0] datab_3;
input ena0;
output [43:0] result;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 [43:0] chainin;
tri1 clock0;
tri0 [16:0] dataa_0;
tri0 [16:0] dataa_1;
tri0 [16:0] dataa_2;
tri0 [16:0] dataa_3;
tri0 [15:0] datab_0;
tri0 [15:0] datab_1;
tri0 [15:0] datab_2;
tri0 [15:0] datab_3;
tri1 ena0;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ACCUM_DIRECTION STRING "Add"
// Retrieval info: PRIVATE: ACCUM_SLOAD_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ACCUM_SLOAD_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ACCUM_SLOAD_PIPE_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ACCUM_SLOAD_PIPE_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ACCUM_SLOAD_PIPE_REG STRING "1"
// Retrieval info: PRIVATE: ACCUM_SLOAD_REG STRING "1"
// Retrieval info: PRIVATE: ADDNSUB1_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ADDNSUB1_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ADDNSUB1_PIPE_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ADDNSUB1_PIPE_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ADDNSUB1_PIPE_REG STRING "1"
// Retrieval info: PRIVATE: ADDNSUB1_REG STRING "1"
// Retrieval info: PRIVATE: ADDNSUB3_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ADDNSUB3_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ADDNSUB3_PIPE_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ADDNSUB3_PIPE_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ADDNSUB3_PIPE_REG STRING "1"
// Retrieval info: PRIVATE: ADDNSUB3_REG STRING "1"
// Retrieval info: PRIVATE: ADD_ENABLE NUMERIC "1"
// Retrieval info: PRIVATE: ALL_REG_ACLR NUMERIC "0"
// Retrieval info: PRIVATE: A_ACLR_SRC_MULT0 NUMERIC "3"
// Retrieval info: PRIVATE: A_CLK_SRC_MULT0 NUMERIC "0"
// Retrieval info: PRIVATE: B_ACLR_SRC_MULT0 NUMERIC "3"
// Retrieval info: PRIVATE: B_CLK_SRC_MULT0 NUMERIC "0"
// Retrieval info: PRIVATE: CHAINOUT_OUTPUT_ACLR NUMERIC "3"
// Retrieval info: PRIVATE: CHAINOUT_OUTPUT_REG STRING "1"
// Retrieval info: PRIVATE: CHAINOUT_OUTPUT_REGISTER NUMERIC "0"
// Retrieval info: PRIVATE: CHAINOUT_OUTPUT_REGISTERED NUMERIC "1"
// Retrieval info: PRIVATE: CHAS_ZERO_CHAINOUT NUMERIC "0"
// Retrieval info: PRIVATE: HAS_ACCUMULATOR NUMERIC "0"
// Retrieval info: PRIVATE: HAS_ACUMM_SLOAD NUMERIC "0"
// Retrieval info: PRIVATE: HAS_CHAININ_PORT NUMERIC "1"
// Retrieval info: PRIVATE: HAS_CHAINOUT_ADDER NUMERIC "1"
// Retrieval info: PRIVATE: HAS_LOOPBACK NUMERIC "0"
// Retrieval info: PRIVATE: HAS_MAC STRING "0"
// Retrieval info: PRIVATE: HAS_SAT_ROUND STRING "0"
// Retrieval info: PRIVATE: HAS_ZERO_LOOPBACK NUMERIC "0"
// Retrieval info: PRIVATE: IMPL_STYLE_DEDICATED NUMERIC "1"
// Retrieval info: PRIVATE: IMPL_STYLE_DEFAULT NUMERIC "0"
// Retrieval info: PRIVATE: IMPL_STYLE_LCELL NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
// Retrieval info: PRIVATE: MULT_REGA0 NUMERIC "1"
// Retrieval info: PRIVATE: MULT_REGB0 NUMERIC "1"
// Retrieval info: PRIVATE: MULT_REGOUT0 NUMERIC "1"
// Retrieval info: PRIVATE: NUM_MULT STRING "4"
// Retrieval info: PRIVATE: OP1 STRING "Add"
// Retrieval info: PRIVATE: OP3 STRING "Add"
// Retrieval info: PRIVATE: OUTPUT_EXTRA_LAT NUMERIC "0"
// Retrieval info: PRIVATE: OUTPUT_REG_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: OUTPUT_REG_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: Q_ACLR_SRC_MULT0 NUMERIC "3"
// Retrieval info: PRIVATE: Q_CLK_SRC_MULT0 NUMERIC "0"
// Retrieval info: PRIVATE: REG_OUT NUMERIC "1"
// Retrieval info: PRIVATE: RNFORMAT STRING "44"
// Retrieval info: PRIVATE: ROTATE_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ROTATE_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ROTATE_OUT_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ROTATE_OUT_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ROTATE_OUT_REG STRING "1"
// Retrieval info: PRIVATE: ROTATE_PIPE_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ROTATE_PIPE_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ROTATE_PIPE_REG STRING "1"
// Retrieval info: PRIVATE: ROTATE_REG STRING "1"
// Retrieval info: PRIVATE: ROUND3_CHAINOUT_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ROUND3_CHAINOUT_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ROUND3_CHAINOUT_MODE STRING "Enabled"
// Retrieval info: PRIVATE: ROUND3_CHAINOUT_OUT_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ROUND3_CHAINOUT_OUT_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ROUND3_CHAINOUT_OUT_REG STRING "1"
// Retrieval info: PRIVATE: ROUND3_CHAINOUT_PIPE_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ROUND3_CHAINOUT_PIPE_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ROUND3_CHAINOUT_PIPE_REG STRING "1"
// Retrieval info: PRIVATE: ROUND3_CHAINOUT_REG STRING "1"
// Retrieval info: PRIVATE: ROUND3_FRAC_WIDTH NUMERIC "27"
// Retrieval info: PRIVATE: ROUND3_OUTPUT_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ROUND3_OUTPUT_CHAINOUT_TYPE STRING "Nearest Integer"
// Retrieval info: PRIVATE: ROUND3_OUTPUT_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ROUND3_OUTPUT_MODE STRING "Disabled"
// Retrieval info: PRIVATE: ROUND3_OUTPUT_PIPE_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ROUND3_OUTPUT_PIPE_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ROUND3_OUTPUT_PIPE_REG STRING "1"
// Retrieval info: PRIVATE: ROUND3_OUTPUT_REG STRING "1"
// Retrieval info: PRIVATE: RQFORMAT STRING "Q1.15"
// Retrieval info: PRIVATE: RTS_WIDTH STRING "44"
// Retrieval info: PRIVATE: SAME_CONFIG NUMERIC "1"
// Retrieval info: PRIVATE: SAME_CONTROL_SRC_A0 NUMERIC "1"
// Retrieval info: PRIVATE: SAME_CONTROL_SRC_B0 NUMERIC "1"
// Retrieval info: PRIVATE: SAT3_CHAINOUT_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: SAT3_CHAINOUT_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: SAT3_CHAINOUT_MODE STRING "Enabled"
// Retrieval info: PRIVATE: SAT3_CHAINOUT_OUT_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: SAT3_CHAINOUT_OUT_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: SAT3_CHAINOUT_OVERFLOW NUMERIC "0"
// Retrieval info: PRIVATE: SAT3_CHAINOUT_PIPE_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: SAT3_CHAINOUT_PIPE_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: SAT3_CHAINOUT_PIPE_REG STRING "1"
// Retrieval info: PRIVATE: SAT3_CHAINOUT_REG STRING "1"
// Retrieval info: PRIVATE: SAT3_FRAC_WIDTH NUMERIC "2"
// Retrieval info: PRIVATE: SAT3_OUTPUT_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: SAT3_OUTPUT_CHAINOUT_TYPE STRING "Asymmetric"
// Retrieval info: PRIVATE: SAT3_OUTPUT_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: SAT3_OUTPUT_MODE STRING "Enabled"
// Retrieval info: PRIVATE: SAT3_OUTPUT_OVERFLOW NUMERIC "0"
// Retrieval info: PRIVATE: SAT3_OUTPUT_PIPE_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: SAT3_OUTPUT_PIPE_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: SAT3_OUTPUT_PIPE_REG STRING "1"
// Retrieval info: PRIVATE: SAT3_OUTPUT_REG STRING "1"
// Retrieval info: PRIVATE: SCANOUTA NUMERIC "0"
// Retrieval info: PRIVATE: SCANOUTB NUMERIC "0"
// Retrieval info: PRIVATE: SHIFTOUTA_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: SHIFTOUTA_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: SHIFTOUTA_REG STRING "0"
// Retrieval info: PRIVATE: SHIFT_RIGHT_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: SHIFT_RIGHT_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: SHIFT_RIGHT_OUT_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: SHIFT_RIGHT_OUT_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: SHIFT_RIGHT_OUT_REG STRING "1"
// Retrieval info: PRIVATE: SHIFT_RIGHT_PIPE_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: SHIFT_RIGHT_PIPE_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: SHIFT_RIGHT_PIPE_REG STRING "1"
// Retrieval info: PRIVATE: SHIFT_RIGHT_REG STRING "1"
// Retrieval info: PRIVATE: SHIFT_ROTATE_MODE STRING "None"
// Retrieval info: PRIVATE: SIGNA STRING "SIGNED"
// Retrieval info: PRIVATE: SIGNA_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: SIGNA_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: SIGNA_PIPE_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: SIGNA_PIPE_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: SIGNA_PIPE_REG STRING "1"
// Retrieval info: PRIVATE: SIGNA_REG STRING "1"
// Retrieval info: PRIVATE: SIGNB STRING "SIGNED"
// Retrieval info: PRIVATE: SIGNB_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: SIGNB_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: SIGNB_PIPE_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: SIGNB_PIPE_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: SIGNB_PIPE_REG STRING "1"
// Retrieval info: PRIVATE: SIGNB_REG STRING "1"
// Retrieval info: PRIVATE: SRCA0 STRING "Multiplier input"
// Retrieval info: PRIVATE: SRCB0 STRING "Multiplier input"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: WIDTHA STRING "17"
// Retrieval info: PRIVATE: WIDTHB STRING "16"
// Retrieval info: PRIVATE: ZERO_CHAINOUT_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ZERO_CHAINOUT_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_CHAINOUT_REG STRING "0"
// Retrieval info: PRIVATE: ZERO_LOOPBACK_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ZERO_LOOPBACK_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_LOOPBACK_OUT_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ZERO_LOOPBACK_OUT_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_LOOPBACK_OUT_REG STRING "1"
// Retrieval info: PRIVATE: ZERO_LOOPBACK_PIPE_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ZERO_LOOPBACK_PIPE_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_LOOPBACK_PIPE_REG STRING "1"
// Retrieval info: PRIVATE: ZERO_LOOPBACK_REG STRING "1"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ACCUMULATOR STRING "NO"
// Retrieval info: CONSTANT: ADDNSUB_MULTIPLIER_ACLR1 STRING "UNUSED"
// Retrieval info: CONSTANT: ADDNSUB_MULTIPLIER_ACLR3 STRING "UNUSED"
// Retrieval info: CONSTANT: ADDNSUB_MULTIPLIER_PIPELINE_ACLR1 STRING "UNUSED"
// Retrieval info: CONSTANT: ADDNSUB_MULTIPLIER_PIPELINE_ACLR3 STRING "UNUSED"
// Retrieval info: CONSTANT: ADDNSUB_MULTIPLIER_PIPELINE_REGISTER1 STRING "CLOCK0"
// Retrieval info: CONSTANT: ADDNSUB_MULTIPLIER_PIPELINE_REGISTER3 STRING "CLOCK0"
// Retrieval info: CONSTANT: ADDNSUB_MULTIPLIER_REGISTER1 STRING "CLOCK0"
// Retrieval info: CONSTANT: ADDNSUB_MULTIPLIER_REGISTER3 STRING "CLOCK0"
// Retrieval info: CONSTANT: CHAINOUT_ACLR STRING "UNUSED"
// Retrieval info: CONSTANT: CHAINOUT_ADDER STRING "YES"
// Retrieval info: CONSTANT: CHAINOUT_REGISTER STRING "CLOCK0"
// Retrieval info: CONSTANT: DEDICATED_MULTIPLIER_CIRCUITRY STRING "YES"
// Retrieval info: CONSTANT: INPUT_ACLR_A0 STRING "UNUSED"
// Retrieval info: CONSTANT: INPUT_ACLR_A1 STRING "UNUSED"
// Retrieval info: CONSTANT: INPUT_ACLR_A2 STRING "UNUSED"
// Retrieval info: CONSTANT: INPUT_ACLR_A3 STRING "UNUSED"
// Retrieval info: CONSTANT: INPUT_ACLR_B0 STRING "UNUSED"
// Retrieval info: CONSTANT: INPUT_ACLR_B1 STRING "UNUSED"
// Retrieval info: CONSTANT: INPUT_ACLR_B2 STRING "UNUSED"
// Retrieval info: CONSTANT: INPUT_ACLR_B3 STRING "UNUSED"
// Retrieval info: CONSTANT: INPUT_REGISTER_A0 STRING "CLOCK0"
// Retrieval info: CONSTANT: INPUT_REGISTER_A1 STRING "CLOCK0"
// Retrieval info: CONSTANT: INPUT_REGISTER_A2 STRING "CLOCK0"
// Retrieval info: CONSTANT: INPUT_REGISTER_A3 STRING "CLOCK0"
// Retrieval info: CONSTANT: INPUT_REGISTER_B0 STRING "CLOCK0"
// Retrieval info: CONSTANT: INPUT_REGISTER_B1 STRING "CLOCK0"
// Retrieval info: CONSTANT: INPUT_REGISTER_B2 STRING "CLOCK0"
// Retrieval info: CONSTANT: INPUT_REGISTER_B3 STRING "CLOCK0"
// Retrieval info: CONSTANT: INPUT_SOURCE_A0 STRING "DATAA"
// Retrieval info: CONSTANT: INPUT_SOURCE_A1 STRING "DATAA"
// Retrieval info: CONSTANT: INPUT_SOURCE_A2 STRING "DATAA"
// Retrieval info: CONSTANT: INPUT_SOURCE_A3 STRING "DATAA"
// Retrieval info: CONSTANT: INPUT_SOURCE_B0 STRING "DATAB"
// Retrieval info: CONSTANT: INPUT_SOURCE_B1 STRING "DATAB"
// Retrieval info: CONSTANT: INPUT_SOURCE_B2 STRING "DATAB"
// Retrieval info: CONSTANT: INPUT_SOURCE_B3 STRING "DATAB"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altmult_add"
// Retrieval info: CONSTANT: MULTIPLIER1_DIRECTION STRING "ADD"
// Retrieval info: CONSTANT: MULTIPLIER3_DIRECTION STRING "ADD"
// Retrieval info: CONSTANT: MULTIPLIER_ACLR0 STRING "UNUSED"
// Retrieval info: CONSTANT: MULTIPLIER_ACLR1 STRING "UNUSED"
// Retrieval info: CONSTANT: MULTIPLIER_ACLR2 STRING "UNUSED"
// Retrieval info: CONSTANT: MULTIPLIER_ACLR3 STRING "UNUSED"
// Retrieval info: CONSTANT: MULTIPLIER_REGISTER0 STRING "CLOCK0"
// Retrieval info: CONSTANT: MULTIPLIER_REGISTER1 STRING "CLOCK0"
// Retrieval info: CONSTANT: MULTIPLIER_REGISTER2 STRING "CLOCK0"
// Retrieval info: CONSTANT: MULTIPLIER_REGISTER3 STRING "CLOCK0"
// Retrieval info: CONSTANT: NUMBER_OF_MULTIPLIERS NUMERIC "4"
// Retrieval info: CONSTANT: OUTPUT_ACLR STRING "UNUSED"
// Retrieval info: CONSTANT: OUTPUT_REGISTER STRING "CLOCK0"
// Retrieval info: CONSTANT: PORT_ADDNSUB1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_ADDNSUB3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SIGNA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SIGNB STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: REPRESENTATION_A STRING "SIGNED"
// Retrieval info: CONSTANT: REPRESENTATION_B STRING "SIGNED"
// Retrieval info: CONSTANT: SIGNED_ACLR_A STRING "UNUSED"
// Retrieval info: CONSTANT: SIGNED_ACLR_B STRING "UNUSED"
// Retrieval info: CONSTANT: SIGNED_PIPELINE_ACLR_A STRING "UNUSED"
// Retrieval info: CONSTANT: SIGNED_PIPELINE_ACLR_B STRING "UNUSED"
// Retrieval info: CONSTANT: SIGNED_PIPELINE_REGISTER_A STRING "CLOCK0"
// Retrieval info: CONSTANT: SIGNED_PIPELINE_REGISTER_B STRING "CLOCK0"
// Retrieval info: CONSTANT: SIGNED_REGISTER_A STRING "CLOCK0"
// Retrieval info: CONSTANT: SIGNED_REGISTER_B STRING "CLOCK0"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "17"
// Retrieval info: CONSTANT: WIDTH_B NUMERIC "16"
// Retrieval info: CONSTANT: WIDTH_CHAININ NUMERIC "44"
// Retrieval info: CONSTANT: WIDTH_RESULT NUMERIC "44"
// Retrieval info: CONSTANT: ZERO_CHAINOUT_OUTPUT_REGISTER STRING "UNREGISTERED"
// Retrieval info: CONSTANT: ZERO_LOOPBACK_ACLR STRING "UNUSED"
// Retrieval info: CONSTANT: ZERO_LOOPBACK_OUTPUT_ACLR STRING "UNUSED"
// Retrieval info: CONSTANT: ZERO_LOOPBACK_OUTPUT_REGISTER STRING "CLOCK0"
// Retrieval info: CONSTANT: ZERO_LOOPBACK_PIPELINE_ACLR STRING "UNUSED"
// Retrieval info: CONSTANT: ZERO_LOOPBACK_PIPELINE_REGISTER STRING "CLOCK0"
// Retrieval info: CONSTANT: ZERO_LOOPBACK_REGISTER STRING "CLOCK0"
// Retrieval info: USED_PORT: chainin 0 0 44 0 INPUT GND "chainin[43..0]"
// Retrieval info: USED_PORT: clock0 0 0 0 0 INPUT VCC "clock0"
// Retrieval info: USED_PORT: dataa_0 0 0 17 0 INPUT GND "dataa_0[16..0]"
// Retrieval info: USED_PORT: dataa_1 0 0 17 0 INPUT GND "dataa_1[16..0]"
// Retrieval info: USED_PORT: dataa_2 0 0 17 0 INPUT GND "dataa_2[16..0]"
// Retrieval info: USED_PORT: dataa_3 0 0 17 0 INPUT GND "dataa_3[16..0]"
// Retrieval info: USED_PORT: datab_0 0 0 16 0 INPUT GND "datab_0[15..0]"
// Retrieval info: USED_PORT: datab_1 0 0 16 0 INPUT GND "datab_1[15..0]"
// Retrieval info: USED_PORT: datab_2 0 0 16 0 INPUT GND "datab_2[15..0]"
// Retrieval info: USED_PORT: datab_3 0 0 16 0 INPUT GND "datab_3[15..0]"
// Retrieval info: USED_PORT: ena0 0 0 0 0 INPUT VCC "ena0"
// Retrieval info: USED_PORT: result 0 0 44 0 OUTPUT GND "result[43..0]"
// Retrieval info: CONNECT: @chainin 0 0 44 0 chainin 0 0 44 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock0 0 0 0 0
// Retrieval info: CONNECT: @dataa 0 0 17 0 dataa_0 0 0 17 0
// Retrieval info: CONNECT: @dataa 0 0 17 17 dataa_1 0 0 17 0
// Retrieval info: CONNECT: @dataa 0 0 17 34 dataa_2 0 0 17 0
// Retrieval info: CONNECT: @dataa 0 0 17 51 dataa_3 0 0 17 0
// Retrieval info: CONNECT: @datab 0 0 16 0 datab_0 0 0 16 0
// Retrieval info: CONNECT: @datab 0 0 16 16 datab_1 0 0 16 0
// Retrieval info: CONNECT: @datab 0 0 16 32 datab_2 0 0 16 0
// Retrieval info: CONNECT: @datab 0 0 16 48 datab_3 0 0 16 0
// Retrieval info: CONNECT: @ena0 0 0 0 0 ena0 0 0 0 0
// Retrieval info: CONNECT: result 0 0 44 0 @result 0 0 44 0
// Retrieval info: GEN_FILE: TYPE_NORMAL dsp_4mult_add.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL dsp_4mult_add.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL dsp_4mult_add.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL dsp_4mult_add.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL dsp_4mult_add_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL dsp_4mult_add_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
dsp_4mult_add dsp_4mult_add_inst (
.chainin ( chainin_sig ),
.clock0 ( clock0_sig ),
.dataa_0 ( dataa_0_sig ),
.dataa_1 ( dataa_1_sig ),
.dataa_2 ( dataa_2_sig ),
.dataa_3 ( dataa_3_sig ),
.datab_0 ( datab_0_sig ),
.datab_1 ( datab_1_sig ),
.datab_2 ( datab_2_sig ),
.datab_3 ( datab_3_sig ),
.ena0 ( ena0_sig ),
.result ( result_sig )
);
|
// megafunction wizard: %LPM_ADD_SUB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: LPM_ADD_SUB
// ============================================================
// File Name: input_adder.v
// Megafunction Name(s):
// LPM_ADD_SUB
//
// Simulation Library Files(s):
// lpm
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 12.1 Build 177 11/07/2012 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2012 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module input_adder (
clken,
clock,
dataa,
datab,
result);
input clken;
input clock;
input [15:0] dataa;
input [15:0] datab;
output [15:0] result;
wire [15:0] sub_wire0;
wire [15:0] result = sub_wire0[15:0];
lpm_add_sub LPM_ADD_SUB_component (
.clock (clock),
.datab (datab),
.clken (clken),
.dataa (dataa),
.result (sub_wire0)
// synopsys translate_off
,
.aclr (),
.add_sub (),
.cin (),
.cout (),
.overflow ()
// synopsys translate_on
);
defparam
LPM_ADD_SUB_component.lpm_direction = "ADD",
LPM_ADD_SUB_component.lpm_hint = "ONE_INPUT_IS_CONSTANT=NO,CIN_USED=NO",
LPM_ADD_SUB_component.lpm_pipeline = 1,
LPM_ADD_SUB_component.lpm_representation = "SIGNED",
LPM_ADD_SUB_component.lpm_type = "LPM_ADD_SUB",
LPM_ADD_SUB_component.lpm_width = 16;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: CarryIn NUMERIC "0"
// Retrieval info: PRIVATE: CarryOut NUMERIC "0"
// Retrieval info: PRIVATE: ConstantA NUMERIC "0"
// Retrieval info: PRIVATE: ConstantB NUMERIC "0"
// Retrieval info: PRIVATE: Function NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
// Retrieval info: PRIVATE: LPM_PIPELINE NUMERIC "1"
// Retrieval info: PRIVATE: Latency NUMERIC "1"
// Retrieval info: PRIVATE: Overflow NUMERIC "0"
// Retrieval info: PRIVATE: RadixA NUMERIC "10"
// Retrieval info: PRIVATE: RadixB NUMERIC "10"
// Retrieval info: PRIVATE: Representation NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: ValidCtA NUMERIC "0"
// Retrieval info: PRIVATE: ValidCtB NUMERIC "0"
// Retrieval info: PRIVATE: WhichConstant NUMERIC "0"
// Retrieval info: PRIVATE: aclr NUMERIC "0"
// Retrieval info: PRIVATE: clken NUMERIC "1"
// Retrieval info: PRIVATE: nBit NUMERIC "16"
// Retrieval info: PRIVATE: new_diagram STRING "1"
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
// Retrieval info: CONSTANT: LPM_DIRECTION STRING "ADD"
// Retrieval info: CONSTANT: LPM_HINT STRING "ONE_INPUT_IS_CONSTANT=NO,CIN_USED=NO"
// Retrieval info: CONSTANT: LPM_PIPELINE NUMERIC "1"
// Retrieval info: CONSTANT: LPM_REPRESENTATION STRING "SIGNED"
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_ADD_SUB"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16"
// Retrieval info: USED_PORT: clken 0 0 0 0 INPUT NODEFVAL "clken"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
// Retrieval info: USED_PORT: dataa 0 0 16 0 INPUT NODEFVAL "dataa[15..0]"
// Retrieval info: USED_PORT: datab 0 0 16 0 INPUT NODEFVAL "datab[15..0]"
// Retrieval info: USED_PORT: result 0 0 16 0 OUTPUT NODEFVAL "result[15..0]"
// Retrieval info: CONNECT: @clken 0 0 0 0 clken 0 0 0 0
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @dataa 0 0 16 0 dataa 0 0 16 0
// Retrieval info: CONNECT: @datab 0 0 16 0 datab 0 0 16 0
// Retrieval info: CONNECT: result 0 0 16 0 @result 0 0 16 0
// Retrieval info: GEN_FILE: TYPE_NORMAL input_adder.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL input_adder.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL input_adder.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL input_adder.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL input_adder_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL input_adder_bb.v TRUE
// Retrieval info: LIB_FILE: lpm
|
// megafunction wizard: %LPM_ADD_SUB%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: LPM_ADD_SUB
// ============================================================
// File Name: input_adder.v
// Megafunction Name(s):
// LPM_ADD_SUB
//
// Simulation Library Files(s):
// lpm
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 12.1 Build 177 11/07/2012 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2012 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module input_adder (
clken,
clock,
dataa,
datab,
result);
input clken;
input clock;
input [15:0] dataa;
input [15:0] datab;
output [15:0] result;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: CarryIn NUMERIC "0"
// Retrieval info: PRIVATE: CarryOut NUMERIC "0"
// Retrieval info: PRIVATE: ConstantA NUMERIC "0"
// Retrieval info: PRIVATE: ConstantB NUMERIC "0"
// Retrieval info: PRIVATE: Function NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
// Retrieval info: PRIVATE: LPM_PIPELINE NUMERIC "1"
// Retrieval info: PRIVATE: Latency NUMERIC "1"
// Retrieval info: PRIVATE: Overflow NUMERIC "0"
// Retrieval info: PRIVATE: RadixA NUMERIC "10"
// Retrieval info: PRIVATE: RadixB NUMERIC "10"
// Retrieval info: PRIVATE: Representation NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: ValidCtA NUMERIC "0"
// Retrieval info: PRIVATE: ValidCtB NUMERIC "0"
// Retrieval info: PRIVATE: WhichConstant NUMERIC "0"
// Retrieval info: PRIVATE: aclr NUMERIC "0"
// Retrieval info: PRIVATE: clken NUMERIC "1"
// Retrieval info: PRIVATE: nBit NUMERIC "16"
// Retrieval info: PRIVATE: new_diagram STRING "1"
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
// Retrieval info: CONSTANT: LPM_DIRECTION STRING "ADD"
// Retrieval info: CONSTANT: LPM_HINT STRING "ONE_INPUT_IS_CONSTANT=NO,CIN_USED=NO"
// Retrieval info: CONSTANT: LPM_PIPELINE NUMERIC "1"
// Retrieval info: CONSTANT: LPM_REPRESENTATION STRING "SIGNED"
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_ADD_SUB"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16"
// Retrieval info: USED_PORT: clken 0 0 0 0 INPUT NODEFVAL "clken"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
// Retrieval info: USED_PORT: dataa 0 0 16 0 INPUT NODEFVAL "dataa[15..0]"
// Retrieval info: USED_PORT: datab 0 0 16 0 INPUT NODEFVAL "datab[15..0]"
// Retrieval info: USED_PORT: result 0 0 16 0 OUTPUT NODEFVAL "result[15..0]"
// Retrieval info: CONNECT: @clken 0 0 0 0 clken 0 0 0 0
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @dataa 0 0 16 0 dataa 0 0 16 0
// Retrieval info: CONNECT: @datab 0 0 16 0 datab 0 0 16 0
// Retrieval info: CONNECT: result 0 0 16 0 @result 0 0 16 0
// Retrieval info: GEN_FILE: TYPE_NORMAL input_adder.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL input_adder.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL input_adder.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL input_adder.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL input_adder_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL input_adder_bb.v TRUE
// Retrieval info: LIB_FILE: lpm
|
input_adder input_adder_inst (
.clken ( clken_sig ),
.clock ( clock_sig ),
.dataa ( dataa_sig ),
.datab ( datab_sig ),
.result ( result_sig )
);
|
// megafunction wizard: %LPM_ADD_SUB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: LPM_ADD_SUB
// ============================================================
// File Name: output_adder.v
// Megafunction Name(s):
// LPM_ADD_SUB
//
// Simulation Library Files(s):
// lpm
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 12.1 Build 177 11/07/2012 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2012 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module output_adder (
clken,
clock,
dataa,
datab,
result);
input clken;
input clock;
input [15:0] dataa;
input [15:0] datab;
output [15:0] result;
wire [15:0] sub_wire0;
wire [15:0] result = sub_wire0[15:0];
lpm_add_sub LPM_ADD_SUB_component (
.clock (clock),
.datab (datab),
.clken (clken),
.dataa (dataa),
.result (sub_wire0)
// synopsys translate_off
,
.aclr (),
.add_sub (),
.cin (),
.cout (),
.overflow ()
// synopsys translate_on
);
defparam
LPM_ADD_SUB_component.lpm_direction = "ADD",
LPM_ADD_SUB_component.lpm_hint = "ONE_INPUT_IS_CONSTANT=NO,CIN_USED=NO",
LPM_ADD_SUB_component.lpm_pipeline = 2,
LPM_ADD_SUB_component.lpm_representation = "SIGNED",
LPM_ADD_SUB_component.lpm_type = "LPM_ADD_SUB",
LPM_ADD_SUB_component.lpm_width = 16;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: CarryIn NUMERIC "0"
// Retrieval info: PRIVATE: CarryOut NUMERIC "0"
// Retrieval info: PRIVATE: ConstantA NUMERIC "0"
// Retrieval info: PRIVATE: ConstantB NUMERIC "0"
// Retrieval info: PRIVATE: Function NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
// Retrieval info: PRIVATE: LPM_PIPELINE NUMERIC "2"
// Retrieval info: PRIVATE: Latency NUMERIC "1"
// Retrieval info: PRIVATE: Overflow NUMERIC "0"
// Retrieval info: PRIVATE: RadixA NUMERIC "10"
// Retrieval info: PRIVATE: RadixB NUMERIC "10"
// Retrieval info: PRIVATE: Representation NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: ValidCtA NUMERIC "0"
// Retrieval info: PRIVATE: ValidCtB NUMERIC "0"
// Retrieval info: PRIVATE: WhichConstant NUMERIC "0"
// Retrieval info: PRIVATE: aclr NUMERIC "0"
// Retrieval info: PRIVATE: clken NUMERIC "1"
// Retrieval info: PRIVATE: nBit NUMERIC "16"
// Retrieval info: PRIVATE: new_diagram STRING "1"
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
// Retrieval info: CONSTANT: LPM_DIRECTION STRING "ADD"
// Retrieval info: CONSTANT: LPM_HINT STRING "ONE_INPUT_IS_CONSTANT=NO,CIN_USED=NO"
// Retrieval info: CONSTANT: LPM_PIPELINE NUMERIC "2"
// Retrieval info: CONSTANT: LPM_REPRESENTATION STRING "SIGNED"
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_ADD_SUB"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16"
// Retrieval info: USED_PORT: clken 0 0 0 0 INPUT NODEFVAL "clken"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
// Retrieval info: USED_PORT: dataa 0 0 16 0 INPUT NODEFVAL "dataa[15..0]"
// Retrieval info: USED_PORT: datab 0 0 16 0 INPUT NODEFVAL "datab[15..0]"
// Retrieval info: USED_PORT: result 0 0 16 0 OUTPUT NODEFVAL "result[15..0]"
// Retrieval info: CONNECT: @clken 0 0 0 0 clken 0 0 0 0
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @dataa 0 0 16 0 dataa 0 0 16 0
// Retrieval info: CONNECT: @datab 0 0 16 0 datab 0 0 16 0
// Retrieval info: CONNECT: result 0 0 16 0 @result 0 0 16 0
// Retrieval info: GEN_FILE: TYPE_NORMAL output_adder.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL output_adder.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL output_adder.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL output_adder.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL output_adder_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL output_adder_bb.v TRUE
// Retrieval info: LIB_FILE: lpm
|
// megafunction wizard: %LPM_ADD_SUB%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: LPM_ADD_SUB
// ============================================================
// File Name: output_adder.v
// Megafunction Name(s):
// LPM_ADD_SUB
//
// Simulation Library Files(s):
// lpm
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 12.1 Build 177 11/07/2012 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2012 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module output_adder (
clken,
clock,
dataa,
datab,
result);
input clken;
input clock;
input [15:0] dataa;
input [15:0] datab;
output [15:0] result;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: CarryIn NUMERIC "0"
// Retrieval info: PRIVATE: CarryOut NUMERIC "0"
// Retrieval info: PRIVATE: ConstantA NUMERIC "0"
// Retrieval info: PRIVATE: ConstantB NUMERIC "0"
// Retrieval info: PRIVATE: Function NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
// Retrieval info: PRIVATE: LPM_PIPELINE NUMERIC "2"
// Retrieval info: PRIVATE: Latency NUMERIC "1"
// Retrieval info: PRIVATE: Overflow NUMERIC "0"
// Retrieval info: PRIVATE: RadixA NUMERIC "10"
// Retrieval info: PRIVATE: RadixB NUMERIC "10"
// Retrieval info: PRIVATE: Representation NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: ValidCtA NUMERIC "0"
// Retrieval info: PRIVATE: ValidCtB NUMERIC "0"
// Retrieval info: PRIVATE: WhichConstant NUMERIC "0"
// Retrieval info: PRIVATE: aclr NUMERIC "0"
// Retrieval info: PRIVATE: clken NUMERIC "1"
// Retrieval info: PRIVATE: nBit NUMERIC "16"
// Retrieval info: PRIVATE: new_diagram STRING "1"
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
// Retrieval info: CONSTANT: LPM_DIRECTION STRING "ADD"
// Retrieval info: CONSTANT: LPM_HINT STRING "ONE_INPUT_IS_CONSTANT=NO,CIN_USED=NO"
// Retrieval info: CONSTANT: LPM_PIPELINE NUMERIC "2"
// Retrieval info: CONSTANT: LPM_REPRESENTATION STRING "SIGNED"
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_ADD_SUB"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16"
// Retrieval info: USED_PORT: clken 0 0 0 0 INPUT NODEFVAL "clken"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
// Retrieval info: USED_PORT: dataa 0 0 16 0 INPUT NODEFVAL "dataa[15..0]"
// Retrieval info: USED_PORT: datab 0 0 16 0 INPUT NODEFVAL "datab[15..0]"
// Retrieval info: USED_PORT: result 0 0 16 0 OUTPUT NODEFVAL "result[15..0]"
// Retrieval info: CONNECT: @clken 0 0 0 0 clken 0 0 0 0
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @dataa 0 0 16 0 dataa 0 0 16 0
// Retrieval info: CONNECT: @datab 0 0 16 0 datab 0 0 16 0
// Retrieval info: CONNECT: result 0 0 16 0 @result 0 0 16 0
// Retrieval info: GEN_FILE: TYPE_NORMAL output_adder.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL output_adder.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL output_adder.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL output_adder.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL output_adder_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL output_adder_bb.v TRUE
// Retrieval info: LIB_FILE: lpm
|
output_adder output_adder_inst (
.clken ( clken_sig ),
.clock ( clock_sig ),
.dataa ( dataa_sig ),
.datab ( datab_sig ),
.result ( result_sig )
);
|
module fir (
input wire clk, // clock_reset.clk
input wire reset_n, // clock_reset_reset.reset_n
input wire [7:0] ast_sink_data, // avalon_streaming_sink.data
output wire ast_sink_ready, // .ready
input wire ast_sink_valid, // .valid
output wire [21:0] ast_source_data, // avalon_streaming_source.data
output wire ast_source_valid, // .valid
output wire [1:0] ast_source_error // .error
);
fir_filter filter_1 (
clk, // clock_reset.clk
reset_n, // clock_reset_reset.reset_n
ast_sink_data, // avalon_streaming_sink.data
ast_sink_ready, // .ready
ast_sink_valid, // .valid
ast_source_data, // avalon_streaming_source.data
ast_source_valid, // .valid
ast_source_error // .error
);
endmodule
|
// megafunction wizard: %FIR Compiler II v11.0%
// GENERATION: XML
// fir_filter.v
//
`timescale 1 ps / 1 ps
module fir_filter (
input wire clk, // clock_reset.clk
input wire reset_n, // clock_reset_reset.reset_n
input wire [7:0] ast_sink_data, // avalon_streaming_sink.data
output wire ast_sink_ready, // .ready
input wire ast_sink_valid, // .valid
output wire [21:0] ast_source_data, // avalon_streaming_source.data
output wire ast_source_valid, // .valid
output wire [1:0] ast_source_error // .error
);
fir_filter_0002 fir_filter_inst (
.clk (clk), // clock_reset.clk
.reset_n (reset_n), // clock_reset_reset.reset_n
.ast_sink_data (ast_sink_data), // avalon_streaming_sink.data
.ast_sink_ready (ast_sink_ready), // .ready
.ast_sink_valid (ast_sink_valid), // .valid
.ast_source_data (ast_source_data), // avalon_streaming_source.data
.ast_source_valid (ast_source_valid), // .valid
.ast_source_error (ast_source_error) // .error
);
endmodule
// Retrieval info: <?xml version="1.0"?>
//<!--
// Generated by Altera MegaWizard Launcher Utility version 1.0
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
// ************************************************************
// Copyright (C) 1991-2011 Altera Corporation
// Any megafunction design, and related net list (encrypted or decrypted),
// support information, device programming or simulation file, and any other
// associated documentation or information provided by Altera or a partner
// under Altera's Megafunction Partnership Program may be used only to
// program PLD devices (but not masked PLD devices) from Altera. Any other
// use of such megafunction design, net list, support information, device
// programming or simulation file, or any other related documentation or
// information is prohibited for any other purpose, including, but not
// limited to modification, reverse engineering, de-compiling, or use with
// any other silicon devices, unless such use is explicitly licensed under
// a separate agreement with Altera or a megafunction partner. Title to
// the intellectual property, including patents, copyrights, trademarks,
// trade secrets, or maskworks, embodied in any such megafunction design,
// net list, support information, device programming or simulation file, or
// any other related documentation or information provided by Altera or a
// megafunction partner, remains with Altera, the megafunction partner, or
// their respective licensors. No other licenses, including any licenses
// needed under any third party's intellectual property, are provided herein.
//-->
// Retrieval info: <instance entity-name="altera_fir_compiler_ii" version="11.0" >
// Retrieval info: <generic name="deviceFamily" value="Stratix IV" />
// Retrieval info: <generic name="filterType" value="Single Rate" />
// Retrieval info: <generic name="interpFactor" value="1" />
// Retrieval info: <generic name="decimFactor" value="1" />
// Retrieval info: <generic name="L_bandsFilter" value="All taps" />
// Retrieval info: <generic name="clockRate" value="100" />
// Retrieval info: <generic name="clockSlack" value="0" />
// Retrieval info: <generic name="speedGrade" value="Medium" />
// Retrieval info: <generic name="coeffReload" value="false" />
// Retrieval info: <generic name="baseAddress" value="0" />
// Retrieval info: <generic name="readWriteMode" value="Read/Write" />
// Retrieval info: <generic name="backPressure" value="false" />
// Retrieval info: <generic name="symmetryMode" value="Non Symmetry" />
// Retrieval info: <generic name="delayRAMBlockThreshold" value="20" />
// Retrieval info: <generic name="dualMemDistRAMThreshold" value="1280" />
// Retrieval info: <generic name="mRAMThreshold" value="1000000" />
// Retrieval info: <generic name="hardMultiplierThreshold" value="-1" />
// Retrieval info: <generic name="inputRate" value="100" />
// Retrieval info: <generic name="inputChannelNum" value="1" />
// Retrieval info: <generic name="inputType" value="Signed Binary" />
// Retrieval info: <generic name="inputBitWidth" value="8" />
// Retrieval info: <generic name="inputFracBitWidth" value="0" />
// Retrieval info: <generic name="coeffSetRealValue" value="0.0176663,0.013227,0.0,-0.0149911,-0.0227152,-0.0172976,0.0,0.0204448,0.0318046,0.0249882,0.0,-0.0321283,-0.0530093,-0.04498,0.0,0.0749693,0.159034,0.224907,0.249809,0.224907,0.159034,0.0749693,0.0,-0.04498,-0.0530093,-0.0321283,0.0,0.0249882,0.0318046,0.0204448,0.0,-0.0172976,-0.0227152,-0.0149911,0.0,0.013227,0.0176663" />
// Retrieval info: <generic name="coeffType" value="Signed Binary" />
// Retrieval info: <generic name="coeffBitWidth" value="8" />
// Retrieval info: <generic name="coeffFracBitWidth" value="0" />
// Retrieval info: <generic name="outType" value="Signed Binary" />
// Retrieval info: <generic name="outMSBRound" value="Saturating" />
// Retrieval info: <generic name="outMsbBitRem" value="0" />
// Retrieval info: <generic name="outLSBRound" value="Rounding" />
// Retrieval info: <generic name="outLsbBitRem" value="0" />
// Retrieval info: <generic name="resoureEstimation" value="1000,1200,10" />
// Retrieval info: <generic name="bankCount" value="1" />
// Retrieval info: <generic name="bankDisplay" value="0" />
// Retrieval info: </instance>
// IPFS_FILES : fir_filter.vo
// RELATED_FILES: fir_filter.v, altera_avalon_sc_fifo.v, auk_dspip_avalon_streaming_controller_hpfir.vhd, auk_dspip_avalon_streaming_sink_hpfir.vhd, auk_dspip_avalon_streaming_source_hpfir.vhd, auk_dspip_roundsat_hpfir.vhd, auk_dspip_math_pkg_hpfir.vhd, auk_dspip_lib_pkg_hpfir.vhd, fir_filter_0002_rtl.vhd, fir_filter_0002_ast.vhd, fir_filter_0002.vhd
|
// -----------------------------------------------------------
// Legal Notice: (C)2007 Altera Corporation. All rights reserved. Your
// use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any
// output files any of the foregoing (including device programming or
// simulation files), and any associated documentation or information are
// expressly subject to the terms and conditions of the Altera Program
// License Subscription Agreement or other applicable license agreement,
// including, without limitation, that your use is for the sole purpose
// of programming logic devices manufactured by Altera and sold by Altera
// or its authorized distributors. Please refer to the applicable
// agreement for further details.
//
// Description: Single clock Avalon-ST FIFO.
// -----------------------------------------------------------
`timescale 1 ns / 1 ns
module altera_avalon_sc_fifo
#(
// --------------------------------------------------
// Parameters
// --------------------------------------------------
parameter SYMBOLS_PER_BEAT = 1,
parameter BITS_PER_SYMBOL = 8,
parameter FIFO_DEPTH = 16,
parameter CHANNEL_WIDTH = 0,
parameter ERROR_WIDTH = 0,
parameter USE_PACKETS = 0,
parameter USE_FILL_LEVEL = 0,
parameter USE_STORE_FORWARD = 0,
parameter USE_ALMOST_FULL_IF = 0,
parameter USE_ALMOST_EMPTY_IF = 0,
// --------------------------------------------------
// Empty latency is defined as the number of cycles
// required for a write to deassert the empty flag.
// For example, a latency of 1 means that the empty
// flag is deasserted on the cycle after a write.
//
// Another way to think of it is the latency for a
// write to propagate to the output.
//
// An empty latency of 0 implies lookahead, which is
// only implemented for the register-based FIFO.
// --------------------------------------------------
parameter EMPTY_LATENCY = 3,
parameter USE_MEMORY_BLOCKS = 1,
// --------------------------------------------------
// Internal Parameters
// --------------------------------------------------
parameter DATA_WIDTH = SYMBOLS_PER_BEAT * BITS_PER_SYMBOL,
parameter EMPTY_WIDTH = log2ceil(SYMBOLS_PER_BEAT)
)
(
// --------------------------------------------------
// Ports
// --------------------------------------------------
input clk,
input reset,
input [DATA_WIDTH-1: 0] in_data,
input in_valid,
input in_startofpacket,
input in_endofpacket,
input [((EMPTY_WIDTH>0) ? (EMPTY_WIDTH-1):0) : 0] in_empty,
input [((ERROR_WIDTH>0) ? (ERROR_WIDTH-1):0) : 0] in_error,
input [((CHANNEL_WIDTH>0) ? (CHANNEL_WIDTH-1):0): 0] in_channel,
output in_ready,
output [DATA_WIDTH-1 : 0] out_data,
output reg out_valid,
output out_startofpacket,
output out_endofpacket,
output [((EMPTY_WIDTH>0) ? (EMPTY_WIDTH-1):0) : 0] out_empty,
output [((ERROR_WIDTH>0) ? (ERROR_WIDTH-1):0) : 0] out_error,
output [((CHANNEL_WIDTH>0) ? (CHANNEL_WIDTH-1):0): 0] out_channel,
input out_ready,
input [(USE_STORE_FORWARD ? 2 : 1) : 0] csr_address,
input csr_write,
input csr_read,
input [31 : 0] csr_writedata,
output reg [31 : 0] csr_readdata,
output wire almost_full_data,
output wire almost_empty_data
);
// --------------------------------------------------
// Local Parameters
// --------------------------------------------------
localparam ADDR_WIDTH = log2ceil(FIFO_DEPTH);
localparam DEPTH = FIFO_DEPTH;
localparam PKT_SIGNALS_WIDTH = 2 + EMPTY_WIDTH;
localparam PAYLOAD_WIDTH = (USE_PACKETS == 1) ?
2 + EMPTY_WIDTH + DATA_WIDTH + ERROR_WIDTH + CHANNEL_WIDTH:
DATA_WIDTH + ERROR_WIDTH + CHANNEL_WIDTH;
// --------------------------------------------------
// Internal Signals
// --------------------------------------------------
genvar i;
reg [PAYLOAD_WIDTH-1 : 0] mem [DEPTH-1 : 0];
reg [ADDR_WIDTH-1 : 0] wr_ptr;
reg [ADDR_WIDTH-1 : 0] rd_ptr;
reg [DEPTH-1 : 0] mem_used;
wire [ADDR_WIDTH-1 : 0] next_wr_ptr;
wire [ADDR_WIDTH-1 : 0] next_rd_ptr;
wire [ADDR_WIDTH-1 : 0] incremented_wr_ptr;
wire [ADDR_WIDTH-1 : 0] incremented_rd_ptr;
wire [ADDR_WIDTH-1 : 0] mem_rd_ptr;
wire read;
wire write;
reg empty;
reg next_empty;
reg full;
reg next_full;
wire [PKT_SIGNALS_WIDTH-1 : 0] in_packet_signals;
wire [PKT_SIGNALS_WIDTH-1 : 0] out_packet_signals;
wire [PAYLOAD_WIDTH-1 : 0] in_payload;
reg [PAYLOAD_WIDTH-1 : 0] internal_out_payload;
reg [PAYLOAD_WIDTH-1 : 0] out_payload;
reg internal_out_valid;
wire internal_out_ready;
reg [ADDR_WIDTH : 0] fifo_fill_level;
reg [ADDR_WIDTH : 0] fill_level;
reg [ADDR_WIDTH-1 : 0] sop_ptr = 0;
reg [23:0] almost_full_threshold;
reg [23:0] almost_empty_threshold;
reg [23:0] cut_through_threshold;
reg [15:0] pkt_cnt;
reg [15:0] pkt_cnt_r;
reg [15:0] pkt_cnt_plusone;
reg [15:0] pkt_cnt_minusone;
reg drop_on_error_en;
reg error_in_pkt;
reg pkt_has_started;
reg sop_has_left_fifo;
reg fifo_too_small_r;
reg pkt_cnt_eq_zero;
reg pkt_cnt_eq_one;
reg pkt_cnt_changed;
wire wait_for_threshold;
reg pkt_mode;
wire wait_for_pkt;
wire ok_to_forward;
wire in_pkt_eop_arrive;
wire out_pkt_leave;
wire in_pkt_start;
wire in_pkt_error;
wire drop_on_error;
wire fifo_too_small;
wire out_pkt_sop_leave;
wire [31:0] max_fifo_size;
reg fifo_fill_level_lt_cut_through_threshold;
// --------------------------------------------------
// Define Payload
//
// Icky part where we decide which signals form the
// payload to the FIFO with generate blocks.
// --------------------------------------------------
generate
if (EMPTY_WIDTH > 0) begin
assign in_packet_signals = {in_startofpacket, in_endofpacket, in_empty};
assign {out_startofpacket, out_endofpacket, out_empty} = out_packet_signals;
end
else begin
assign out_empty = in_error;
assign in_packet_signals = {in_startofpacket, in_endofpacket};
assign {out_startofpacket, out_endofpacket} = out_packet_signals;
end
endgenerate
generate
if (USE_PACKETS) begin
if (ERROR_WIDTH > 0) begin
if (CHANNEL_WIDTH > 0) begin
assign in_payload = {in_packet_signals, in_data, in_error, in_channel};
assign {out_packet_signals, out_data, out_error, out_channel} = out_payload;
end
else begin
assign out_channel = in_channel;
assign in_payload = {in_packet_signals, in_data, in_error};
assign {out_packet_signals, out_data, out_error} = out_payload;
end
end
else begin
assign out_error = in_error;
if (CHANNEL_WIDTH > 0) begin
assign in_payload = {in_packet_signals, in_data, in_channel};
assign {out_packet_signals, out_data, out_channel} = out_payload;
end
else begin
assign out_channel = in_channel;
assign in_payload = {in_packet_signals, in_data};
assign {out_packet_signals, out_data} = out_payload;
end
end
end
else begin
assign out_packet_signals = 0;
if (ERROR_WIDTH > 0) begin
if (CHANNEL_WIDTH > 0) begin
assign in_payload = {in_data, in_error, in_channel};
assign {out_data, out_error, out_channel} = out_payload;
end
else begin
assign out_channel = in_channel;
assign in_payload = {in_data, in_error};
assign {out_data, out_error} = out_payload;
end
end
else begin
assign out_error = in_error;
if (CHANNEL_WIDTH > 0) begin
assign in_payload = {in_data, in_channel};
assign {out_data, out_channel} = out_payload;
end
else begin
assign out_channel = in_channel;
assign in_payload = in_data;
assign out_data = out_payload;
end
end
end
endgenerate
// --------------------------------------------------
// Memory-based FIFO storage
//
// To allow a ready latency of 0, the read index is
// obtained from the next read pointer and memory
// outputs are unregistered.
//
// If the empty latency is 1, we infer bypass logic
// around the memory so writes propagate to the
// outputs on the next cycle.
//
// Do not change the way this is coded: Quartus needs
// a perfect match to the template, and any attempt to
// refactor the two always blocks into one will break
// memory inference.
// --------------------------------------------------
generate if (USE_MEMORY_BLOCKS == 1) begin
if (EMPTY_LATENCY == 1) begin
always @(posedge clk) begin
if (in_valid && in_ready)
mem[wr_ptr] = in_payload;
internal_out_payload = mem[mem_rd_ptr];
end
end else begin
always @(posedge clk) begin
if (in_valid && in_ready)
mem[wr_ptr] <= in_payload;
internal_out_payload <= mem[mem_rd_ptr];
end
end
assign mem_rd_ptr = next_rd_ptr;
end else begin
// --------------------------------------------------
// Register-based FIFO storage
//
// Uses a shift register as the storage element. Each
// shift register slot has a bit which indicates if
// the slot is occupied (credit to Sam H for the idea).
// The occupancy bits are contiguous and start from the
// lsb, so 0000, 0001, 0011, 0111, 1111 for a 4-deep
// FIFO.
//
// Each slot is enabled during a read or when it
// is unoccupied. New data is always written to every
// going-to-be-empty slot (we keep track of which ones
// are actually useful with the occupancy bits). On a
// read we shift occupied slots.
//
// The exception is the last slot, which always gets
// new data when it is unoccupied.
// --------------------------------------------------
for (i = 0; i < DEPTH-1; i = i + 1) begin : shift_reg
always @(posedge clk or posedge reset) begin
if (reset) begin
mem[i] <= 0;
end
else if (read || !mem_used[i]) begin
if (!mem_used[i+1])
mem[i] <= in_payload;
else
mem[i] <= mem[i+1];
end
end
end
always @(posedge clk, posedge reset) begin
if (reset) begin
mem[DEPTH-1] <= 0;
end
else begin
if (!mem_used[DEPTH-1])
mem[DEPTH-1] <= in_payload;
if (DEPTH == 1) begin
if (write)
mem[DEPTH-1] <= in_payload;
end
end
end
end
endgenerate
assign read = internal_out_ready && internal_out_valid && ok_to_forward;
assign write = in_ready && in_valid;
// --------------------------------------------------
// Pointer Management
// --------------------------------------------------
generate if (USE_MEMORY_BLOCKS == 1) begin
assign incremented_wr_ptr = wr_ptr + 1'b1;
assign incremented_rd_ptr = rd_ptr + 1'b1;
assign next_wr_ptr = drop_on_error ? sop_ptr : write ? incremented_wr_ptr : wr_ptr;
assign next_rd_ptr = (read) ? incremented_rd_ptr : rd_ptr;
always @(posedge clk or posedge reset) begin
if (reset) begin
wr_ptr <= 0;
rd_ptr <= 0;
end
else begin
wr_ptr <= next_wr_ptr;
rd_ptr <= next_rd_ptr;
end
end
end else begin
// --------------------------------------------------
// Shift Register Occupancy Bits
//
// Consider a 4-deep FIFO with 2 entries: 0011
// On a read and write, do not modify the bits.
// On a write, left-shift the bits to get 0111.
// On a read, right-shift the bits to get 0001.
//
// Also, on a write we set bit0 (the head), while
// clearing the tail on a read.
// --------------------------------------------------
always @(posedge clk or posedge reset) begin
if (reset) begin
mem_used[0] <= 0;
end
else begin
if (write ^ read) begin
if (read) begin
if (DEPTH > 1)
mem_used[0] <= mem_used[1];
else
mem_used[0] <= 0;
end
if (write)
mem_used[0] <= 1;
end
end
end
if (DEPTH > 1) begin
always @(posedge clk or posedge reset) begin
if (reset) begin
mem_used[DEPTH-1] <= 0;
end
else begin
if (write ^ read) begin
mem_used[DEPTH-1] <= 0;
if (write)
mem_used[DEPTH-1] <= mem_used[DEPTH-2];
end
end
end
end
for (i = 1; i < DEPTH-1; i = i + 1) begin : storage_logic
always @(posedge clk, posedge reset) begin
if (reset) begin
mem_used[i] <= 0;
end
else begin
if (write ^ read) begin
if (read)
mem_used[i] <= mem_used[i+1];
if (write)
mem_used[i] <= mem_used[i-1];
end
end
end
end
end
endgenerate
// --------------------------------------------------
// Memory FIFO Status Management
//
// Generates the full and empty signals from the
// pointers. The FIFO is full when the next write
// pointer will be equal to the read pointer after
// a write. Reading from a FIFO clears full.
//
// The FIFO is empty when the next read pointer will
// be equal to the write pointer after a read. Writing
// to a FIFO clears empty.
//
// A simultaneous read and write must not change any of
// the empty or full flags unless there is a drop on error event.
// --------------------------------------------------
generate if (USE_MEMORY_BLOCKS == 1) begin
always @* begin
next_full = full;
next_empty = empty;
if (read && !write) begin
next_full = 1'b0;
if (incremented_rd_ptr == wr_ptr)
next_empty = 1'b1;
end
if (write && !read) begin
if (!drop_on_error)
next_empty = 1'b0;
else if (sop_ptr == rd_ptr) // drop on error and only 1 pkt in fifo
next_empty = 1'b1;
if (incremented_wr_ptr == rd_ptr && !drop_on_error)
next_full = 1'b1;
end
if (write && read && drop_on_error) begin
if (sop_ptr == next_rd_ptr)
next_empty = 1'b1;
end
end
always @(posedge clk or posedge reset) begin
if (reset) begin
empty <= 1;
full <= 0;
end
else begin
empty <= next_empty;
full <= next_full;
end
end
end else begin
// --------------------------------------------------
// Register FIFO Status Management
//
// Full when the tail occupancy bit is 1. Empty when
// the head occupancy bit is 0.
// --------------------------------------------------
always @* begin
full = mem_used[DEPTH-1];
empty = !mem_used[0];
// ------------------------------------------
// For a single slot FIFO, reading clears the
// full status immediately.
// ------------------------------------------
if (DEPTH == 1)
full = mem_used[0] && !read;
internal_out_payload = mem[0];
// ------------------------------------------
// Writes clear empty immediately for lookahead modes.
// Note that we use in_valid instead of write to avoid
// combinational loops (in lookahead mode, qualifying
// with in_ready is meaningless).
//
// In a 1-deep FIFO, a possible combinational loop runs
// from write -> out_valid -> out_ready -> write
// ------------------------------------------
if (EMPTY_LATENCY == 0) begin
empty = !mem_used[0] && !in_valid;
if (!mem_used[0] && in_valid)
internal_out_payload = in_payload;
end
end
end
endgenerate
// --------------------------------------------------
// Avalon-ST Signals
//
// The in_ready signal is straightforward.
//
// To match memory latency when empty latency > 1,
// out_valid assertions must be delayed by one clock
// cycle.
//
// Note: out_valid deassertions must not be delayed or
// the FIFO will underflow.
// --------------------------------------------------
assign in_ready = !full;
assign internal_out_ready = out_ready || !out_valid;
generate if (EMPTY_LATENCY > 1) begin
always @(posedge clk or posedge reset) begin
if (reset)
internal_out_valid <= 0;
else begin
internal_out_valid <= !empty & ok_to_forward & ~drop_on_error;
if (read) begin
if (incremented_rd_ptr == wr_ptr)
internal_out_valid <= 1'b0;
end
end
end
end else begin
always @* begin
internal_out_valid = !empty & ok_to_forward;
end
end
endgenerate
// --------------------------------------------------
// Single Output Pipeline Stage
//
// This output pipeline stage is enabled if the FIFO's
// empty latency is set to 3 (default). It is disabled
// for all other allowed latencies.
//
// Reason: The memory outputs are unregistered, so we have to
// register the output or fmax will drop if combinatorial
// logic is present on the output datapath.
//
// Q: The Avalon-ST spec says that I have to register my outputs
// But isn't the memory counted as a register?
// A: The path from the address lookup to the memory output is
// slow. Registering the memory outputs is a good idea.
//
// The registers get packed into the memory by the fitter
// which means minimal resources are consumed (the result
// is a altsyncram with registered outputs, available on
// all modern Altera devices).
//
// This output stage acts as an extra slot in the FIFO,
// and complicates the fill level.
// --------------------------------------------------
generate if (EMPTY_LATENCY == 3) begin
always @(posedge clk or posedge reset) begin
if (reset) begin
out_valid <= 0;
out_payload <= 0;
end
else begin
if (internal_out_ready) begin
out_valid <= internal_out_valid & ok_to_forward;
out_payload <= internal_out_payload;
end
end
end
end
else begin
always @* begin
out_valid = internal_out_valid;
out_payload = internal_out_payload;
end
end
endgenerate
// --------------------------------------------------
// Fill Level
//
// The fill level is calculated from the next write
// and read pointers to avoid unnecessary latency.
//
// If the output pipeline is enabled, the fill level
// must account for it, or we'll always be off by one.
// This may, or may not be important depending on the
// application.
//
// For now, we'll always calculate the exact fill level
// at the cost of an extra adder when the output stage
// is enabled.
// --------------------------------------------------
generate if (USE_FILL_LEVEL) begin
wire [31:0] depth32;
assign depth32 = DEPTH;
always @(posedge clk or posedge reset) begin
if (reset)
fifo_fill_level <= 0;
else if (next_full & !drop_on_error)
fifo_fill_level <= depth32[ADDR_WIDTH:0];
else begin
fifo_fill_level[ADDR_WIDTH] <= 1'b0;
fifo_fill_level[ADDR_WIDTH-1 : 0] <= next_wr_ptr - next_rd_ptr;
end
end
always @* begin
fill_level = fifo_fill_level;
if (EMPTY_LATENCY == 3)
fill_level = fifo_fill_level + {{ADDR_WIDTH{1'b0}}, out_valid};
end
end
else begin
always @* begin
fill_level = 0;
end
end
endgenerate
generate if (USE_ALMOST_FULL_IF) begin
assign almost_full_data = (fill_level >= almost_full_threshold);
end
else
assign almost_full_data = 0;
endgenerate
generate if (USE_ALMOST_EMPTY_IF) begin
assign almost_empty_data = (fill_level <= almost_empty_threshold);
end
else
assign almost_empty_data = 0;
endgenerate
// --------------------------------------------------
// Avalon-MM Status & Control Connection Point
//
// Register map:
//
// | Addr | RW | 31 - 0 |
// | 0 | R | Fill level |
//
// The registering of this connection point means
// that there is a cycle of latency between
// reads/writes and the updating of the fill level.
// --------------------------------------------------
generate if (USE_STORE_FORWARD) begin
assign max_fifo_size = FIFO_DEPTH - 1;
always @(posedge clk or posedge reset) begin
if (reset) begin
almost_full_threshold <= max_fifo_size[23 : 0];
almost_empty_threshold <= 0;
cut_through_threshold <= 0;
drop_on_error_en <= 0;
csr_readdata <= 0;
pkt_mode <= 1'b1;
end
else begin
if (csr_write) begin
if(csr_address == 3'b010)
almost_full_threshold <= csr_writedata[23:0];
if(csr_address == 3'b011)
almost_empty_threshold <= csr_writedata[23:0];
if(csr_address == 3'b100) begin
cut_through_threshold <= csr_writedata[23:0];
pkt_mode <= (csr_writedata[23:0] == 0);
end
if(csr_address == 3'b101)
drop_on_error_en <= csr_writedata[0];
end
if (csr_read) begin
csr_readdata <= 32'b0;
if (csr_address == 0)
csr_readdata <= {{(31 - ADDR_WIDTH){1'b0}}, fill_level};
if (csr_address == 2)
csr_readdata <= {8'b0, almost_full_threshold};
if (csr_address == 3)
csr_readdata <= {8'b0, almost_empty_threshold};
if (csr_address == 4)
csr_readdata <= {8'b0, cut_through_threshold};
if (csr_address == 5)
csr_readdata <= {31'b0, drop_on_error_en};
end
end
end
end
else if (USE_ALMOST_FULL_IF || USE_ALMOST_EMPTY_IF) begin
assign max_fifo_size = FIFO_DEPTH - 1;
always @(posedge clk or posedge reset) begin
if (reset) begin
almost_full_threshold <= max_fifo_size[23 : 0];
almost_empty_threshold <= 0;
csr_readdata <= 0;
end
else begin
if (csr_write) begin
if(csr_address == 3'b010)
almost_full_threshold <= csr_writedata[23:0];
if(csr_address == 3'b011)
almost_empty_threshold <= csr_writedata[23:0];
end
if (csr_read) begin
csr_readdata <= 32'b0;
if (csr_address == 0)
csr_readdata <= {{(31 - ADDR_WIDTH){1'b0}}, fill_level};
if (csr_address == 2)
csr_readdata <= {8'b0, almost_full_threshold};
if (csr_address == 3)
csr_readdata <= {8'b0, almost_empty_threshold};
end
end
end
end
else begin
always @(posedge clk or posedge reset) begin
if (reset) begin
csr_readdata <= 0;
end
else if (csr_read) begin
csr_readdata <= 0;
if (csr_address == 0)
csr_readdata <= fill_level;
end
end
end
endgenerate
// --------------------------------------------------
// Store and forward logic
// --------------------------------------------------
// if the fifo gets full before the entire packet or the
// cut-threshold condition is met then start sending out
// data in order to avoid dead-lock situation
generate if (USE_STORE_FORWARD) begin
assign wait_for_threshold = (fifo_fill_level_lt_cut_through_threshold) & wait_for_pkt ;
assign wait_for_pkt = pkt_cnt_eq_zero | (pkt_cnt_eq_one & out_pkt_leave);
assign ok_to_forward = (pkt_mode ? (~wait_for_pkt | ~pkt_has_started) :
~wait_for_threshold) | fifo_too_small_r;
assign in_pkt_eop_arrive = in_valid & in_ready & in_endofpacket;
assign in_pkt_start = in_valid & in_ready & in_startofpacket;
assign in_pkt_error = in_valid & in_ready & |in_error;
assign out_pkt_sop_leave = out_valid & out_ready & out_startofpacket;
assign out_pkt_leave = out_valid & out_ready & out_endofpacket;
assign fifo_too_small = (pkt_mode ? wait_for_pkt : wait_for_threshold) & full & out_ready;
// count packets coming and going into the fifo
always @(posedge clk or posedge reset) begin
if (reset) begin
pkt_cnt <= 0;
pkt_cnt_r <= 0;
pkt_cnt_plusone <= 1;
pkt_cnt_minusone <= 0;
pkt_cnt_changed <= 0;
pkt_has_started <= 0;
sop_has_left_fifo <= 0;
fifo_too_small_r <= 0;
pkt_cnt_eq_zero <= 1'b1;
pkt_cnt_eq_one <= 1'b0;
fifo_fill_level_lt_cut_through_threshold <= 1'b1;
end
else begin
fifo_fill_level_lt_cut_through_threshold <= fifo_fill_level < cut_through_threshold;
fifo_too_small_r <= fifo_too_small;
pkt_cnt_plusone <= pkt_cnt + 1'b1;
pkt_cnt_minusone <= pkt_cnt - 1'b1;
pkt_cnt_r <= pkt_cnt;
pkt_cnt_changed <= 1'b0;
if( in_pkt_eop_arrive )
sop_has_left_fifo <= 1'b0;
else if (out_pkt_sop_leave & pkt_cnt_eq_zero )
sop_has_left_fifo <= 1'b1;
if (in_pkt_eop_arrive & ~out_pkt_leave & ~drop_on_error ) begin
pkt_cnt_changed <= 1'b1;
pkt_cnt <= pkt_cnt_changed ? pkt_cnt_r : pkt_cnt_plusone;
pkt_cnt_eq_zero <= 0;
if (pkt_cnt == 0)
pkt_cnt_eq_one <= 1'b1;
else
pkt_cnt_eq_one <= 1'b0;
end
else if((~in_pkt_eop_arrive | drop_on_error) & out_pkt_leave) begin
pkt_cnt_changed <= 1'b1;
pkt_cnt <= pkt_cnt_changed ? pkt_cnt_r : pkt_cnt_minusone;
if (pkt_cnt == 1)
pkt_cnt_eq_zero <= 1'b1;
else
pkt_cnt_eq_zero <= 1'b0;
if (pkt_cnt == 2)
pkt_cnt_eq_one <= 1'b1;
else
pkt_cnt_eq_one <= 1'b0;
end
if (in_pkt_start)
pkt_has_started <= 1'b1;
else if (in_pkt_eop_arrive)
pkt_has_started <= 1'b0;
end
end
// drop on error logic
always @(posedge clk or posedge reset) begin
if (reset) begin
sop_ptr <= 0;
error_in_pkt <= 0;
end
else begin
// save the location of the SOP
if ( in_pkt_start )
sop_ptr <= wr_ptr;
// remember if error in pkt
// log error only if packet has already started
if (in_pkt_eop_arrive)
error_in_pkt <= 1'b0;
else if ( in_pkt_error & (pkt_has_started | in_pkt_start))
error_in_pkt <= 1'b1;
end
end
assign drop_on_error = drop_on_error_en & (error_in_pkt | in_pkt_error) & in_pkt_eop_arrive &
~sop_has_left_fifo & ~(out_pkt_sop_leave & pkt_cnt_eq_zero);
end
else begin
assign ok_to_forward = 1'b1;
assign drop_on_error = 1'b0;
end
endgenerate
// --------------------------------------------------
// Calculates the log2ceil of the input value
// --------------------------------------------------
function integer log2ceil;
input integer val;
integer i;
begin
i = 1;
log2ceil = 0;
while (i < val) begin
log2ceil = log2ceil + 1;
i = i << 1;
end
end
endfunction
endmodule
|
// -----------------------------------------------------------
// Legal Notice: (C)2007 Altera Corporation. All rights reserved. Your
// use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any
// output files any of the foregoing (including device programming or
// simulation files), and any associated documentation or information are
// expressly subject to the terms and conditions of the Altera Program
// License Subscription Agreement or other applicable license agreement,
// including, without limitation, that your use is for the sole purpose
// of programming logic devices manufactured by Altera and sold by Altera
// or its authorized distributors. Please refer to the applicable
// agreement for further details.
//
// Description: Single clock Avalon-ST FIFO.
// -----------------------------------------------------------
`timescale 1 ns / 1 ns
module altera_avalon_sc_fifo
#(
// --------------------------------------------------
// Parameters
// --------------------------------------------------
parameter SYMBOLS_PER_BEAT = 1,
parameter BITS_PER_SYMBOL = 8,
parameter FIFO_DEPTH = 16,
parameter CHANNEL_WIDTH = 0,
parameter ERROR_WIDTH = 0,
parameter USE_PACKETS = 0,
parameter USE_FILL_LEVEL = 0,
parameter USE_STORE_FORWARD = 0,
parameter USE_ALMOST_FULL_IF = 0,
parameter USE_ALMOST_EMPTY_IF = 0,
// --------------------------------------------------
// Empty latency is defined as the number of cycles
// required for a write to deassert the empty flag.
// For example, a latency of 1 means that the empty
// flag is deasserted on the cycle after a write.
//
// Another way to think of it is the latency for a
// write to propagate to the output.
//
// An empty latency of 0 implies lookahead, which is
// only implemented for the register-based FIFO.
// --------------------------------------------------
parameter EMPTY_LATENCY = 3,
parameter USE_MEMORY_BLOCKS = 1,
// --------------------------------------------------
// Internal Parameters
// --------------------------------------------------
parameter DATA_WIDTH = SYMBOLS_PER_BEAT * BITS_PER_SYMBOL,
parameter EMPTY_WIDTH = log2ceil(SYMBOLS_PER_BEAT)
)
(
// --------------------------------------------------
// Ports
// --------------------------------------------------
input clk,
input reset,
input [DATA_WIDTH-1: 0] in_data,
input in_valid,
input in_startofpacket,
input in_endofpacket,
input [((EMPTY_WIDTH>0) ? (EMPTY_WIDTH-1):0) : 0] in_empty,
input [((ERROR_WIDTH>0) ? (ERROR_WIDTH-1):0) : 0] in_error,
input [((CHANNEL_WIDTH>0) ? (CHANNEL_WIDTH-1):0): 0] in_channel,
output in_ready,
output [DATA_WIDTH-1 : 0] out_data,
output reg out_valid,
output out_startofpacket,
output out_endofpacket,
output [((EMPTY_WIDTH>0) ? (EMPTY_WIDTH-1):0) : 0] out_empty,
output [((ERROR_WIDTH>0) ? (ERROR_WIDTH-1):0) : 0] out_error,
output [((CHANNEL_WIDTH>0) ? (CHANNEL_WIDTH-1):0): 0] out_channel,
input out_ready,
input [(USE_STORE_FORWARD ? 2 : 1) : 0] csr_address,
input csr_write,
input csr_read,
input [31 : 0] csr_writedata,
output reg [31 : 0] csr_readdata,
output wire almost_full_data,
output wire almost_empty_data
);
// --------------------------------------------------
// Local Parameters
// --------------------------------------------------
localparam ADDR_WIDTH = log2ceil(FIFO_DEPTH);
localparam DEPTH = FIFO_DEPTH;
localparam PKT_SIGNALS_WIDTH = 2 + EMPTY_WIDTH;
localparam PAYLOAD_WIDTH = (USE_PACKETS == 1) ?
2 + EMPTY_WIDTH + DATA_WIDTH + ERROR_WIDTH + CHANNEL_WIDTH:
DATA_WIDTH + ERROR_WIDTH + CHANNEL_WIDTH;
// --------------------------------------------------
// Internal Signals
// --------------------------------------------------
genvar i;
reg [PAYLOAD_WIDTH-1 : 0] mem [DEPTH-1 : 0];
reg [ADDR_WIDTH-1 : 0] wr_ptr;
reg [ADDR_WIDTH-1 : 0] rd_ptr;
reg [DEPTH-1 : 0] mem_used;
wire [ADDR_WIDTH-1 : 0] next_wr_ptr;
wire [ADDR_WIDTH-1 : 0] next_rd_ptr;
wire [ADDR_WIDTH-1 : 0] incremented_wr_ptr;
wire [ADDR_WIDTH-1 : 0] incremented_rd_ptr;
wire [ADDR_WIDTH-1 : 0] mem_rd_ptr;
wire read;
wire write;
reg empty;
reg next_empty;
reg full;
reg next_full;
wire [PKT_SIGNALS_WIDTH-1 : 0] in_packet_signals;
wire [PKT_SIGNALS_WIDTH-1 : 0] out_packet_signals;
wire [PAYLOAD_WIDTH-1 : 0] in_payload;
reg [PAYLOAD_WIDTH-1 : 0] internal_out_payload;
reg [PAYLOAD_WIDTH-1 : 0] out_payload;
reg internal_out_valid;
wire internal_out_ready;
reg [ADDR_WIDTH : 0] fifo_fill_level;
reg [ADDR_WIDTH : 0] fill_level;
reg [ADDR_WIDTH-1 : 0] sop_ptr = 0;
reg [23:0] almost_full_threshold;
reg [23:0] almost_empty_threshold;
reg [23:0] cut_through_threshold;
reg [15:0] pkt_cnt;
reg [15:0] pkt_cnt_r;
reg [15:0] pkt_cnt_plusone;
reg [15:0] pkt_cnt_minusone;
reg drop_on_error_en;
reg error_in_pkt;
reg pkt_has_started;
reg sop_has_left_fifo;
reg fifo_too_small_r;
reg pkt_cnt_eq_zero;
reg pkt_cnt_eq_one;
reg pkt_cnt_changed;
wire wait_for_threshold;
reg pkt_mode;
wire wait_for_pkt;
wire ok_to_forward;
wire in_pkt_eop_arrive;
wire out_pkt_leave;
wire in_pkt_start;
wire in_pkt_error;
wire drop_on_error;
wire fifo_too_small;
wire out_pkt_sop_leave;
wire [31:0] max_fifo_size;
reg fifo_fill_level_lt_cut_through_threshold;
// --------------------------------------------------
// Define Payload
//
// Icky part where we decide which signals form the
// payload to the FIFO with generate blocks.
// --------------------------------------------------
generate
if (EMPTY_WIDTH > 0) begin
assign in_packet_signals = {in_startofpacket, in_endofpacket, in_empty};
assign {out_startofpacket, out_endofpacket, out_empty} = out_packet_signals;
end
else begin
assign out_empty = in_error;
assign in_packet_signals = {in_startofpacket, in_endofpacket};
assign {out_startofpacket, out_endofpacket} = out_packet_signals;
end
endgenerate
generate
if (USE_PACKETS) begin
if (ERROR_WIDTH > 0) begin
if (CHANNEL_WIDTH > 0) begin
assign in_payload = {in_packet_signals, in_data, in_error, in_channel};
assign {out_packet_signals, out_data, out_error, out_channel} = out_payload;
end
else begin
assign out_channel = in_channel;
assign in_payload = {in_packet_signals, in_data, in_error};
assign {out_packet_signals, out_data, out_error} = out_payload;
end
end
else begin
assign out_error = in_error;
if (CHANNEL_WIDTH > 0) begin
assign in_payload = {in_packet_signals, in_data, in_channel};
assign {out_packet_signals, out_data, out_channel} = out_payload;
end
else begin
assign out_channel = in_channel;
assign in_payload = {in_packet_signals, in_data};
assign {out_packet_signals, out_data} = out_payload;
end
end
end
else begin
assign out_packet_signals = 0;
if (ERROR_WIDTH > 0) begin
if (CHANNEL_WIDTH > 0) begin
assign in_payload = {in_data, in_error, in_channel};
assign {out_data, out_error, out_channel} = out_payload;
end
else begin
assign out_channel = in_channel;
assign in_payload = {in_data, in_error};
assign {out_data, out_error} = out_payload;
end
end
else begin
assign out_error = in_error;
if (CHANNEL_WIDTH > 0) begin
assign in_payload = {in_data, in_channel};
assign {out_data, out_channel} = out_payload;
end
else begin
assign out_channel = in_channel;
assign in_payload = in_data;
assign out_data = out_payload;
end
end
end
endgenerate
// --------------------------------------------------
// Memory-based FIFO storage
//
// To allow a ready latency of 0, the read index is
// obtained from the next read pointer and memory
// outputs are unregistered.
//
// If the empty latency is 1, we infer bypass logic
// around the memory so writes propagate to the
// outputs on the next cycle.
//
// Do not change the way this is coded: Quartus needs
// a perfect match to the template, and any attempt to
// refactor the two always blocks into one will break
// memory inference.
// --------------------------------------------------
generate if (USE_MEMORY_BLOCKS == 1) begin
if (EMPTY_LATENCY == 1) begin
always @(posedge clk) begin
if (in_valid && in_ready)
mem[wr_ptr] = in_payload;
internal_out_payload = mem[mem_rd_ptr];
end
end else begin
always @(posedge clk) begin
if (in_valid && in_ready)
mem[wr_ptr] <= in_payload;
internal_out_payload <= mem[mem_rd_ptr];
end
end
assign mem_rd_ptr = next_rd_ptr;
end else begin
// --------------------------------------------------
// Register-based FIFO storage
//
// Uses a shift register as the storage element. Each
// shift register slot has a bit which indicates if
// the slot is occupied (credit to Sam H for the idea).
// The occupancy bits are contiguous and start from the
// lsb, so 0000, 0001, 0011, 0111, 1111 for a 4-deep
// FIFO.
//
// Each slot is enabled during a read or when it
// is unoccupied. New data is always written to every
// going-to-be-empty slot (we keep track of which ones
// are actually useful with the occupancy bits). On a
// read we shift occupied slots.
//
// The exception is the last slot, which always gets
// new data when it is unoccupied.
// --------------------------------------------------
for (i = 0; i < DEPTH-1; i = i + 1) begin : shift_reg
always @(posedge clk or posedge reset) begin
if (reset) begin
mem[i] <= 0;
end
else if (read || !mem_used[i]) begin
if (!mem_used[i+1])
mem[i] <= in_payload;
else
mem[i] <= mem[i+1];
end
end
end
always @(posedge clk, posedge reset) begin
if (reset) begin
mem[DEPTH-1] <= 0;
end
else begin
if (!mem_used[DEPTH-1])
mem[DEPTH-1] <= in_payload;
if (DEPTH == 1) begin
if (write)
mem[DEPTH-1] <= in_payload;
end
end
end
end
endgenerate
assign read = internal_out_ready && internal_out_valid && ok_to_forward;
assign write = in_ready && in_valid;
// --------------------------------------------------
// Pointer Management
// --------------------------------------------------
generate if (USE_MEMORY_BLOCKS == 1) begin
assign incremented_wr_ptr = wr_ptr + 1'b1;
assign incremented_rd_ptr = rd_ptr + 1'b1;
assign next_wr_ptr = drop_on_error ? sop_ptr : write ? incremented_wr_ptr : wr_ptr;
assign next_rd_ptr = (read) ? incremented_rd_ptr : rd_ptr;
always @(posedge clk or posedge reset) begin
if (reset) begin
wr_ptr <= 0;
rd_ptr <= 0;
end
else begin
wr_ptr <= next_wr_ptr;
rd_ptr <= next_rd_ptr;
end
end
end else begin
// --------------------------------------------------
// Shift Register Occupancy Bits
//
// Consider a 4-deep FIFO with 2 entries: 0011
// On a read and write, do not modify the bits.
// On a write, left-shift the bits to get 0111.
// On a read, right-shift the bits to get 0001.
//
// Also, on a write we set bit0 (the head), while
// clearing the tail on a read.
// --------------------------------------------------
always @(posedge clk or posedge reset) begin
if (reset) begin
mem_used[0] <= 0;
end
else begin
if (write ^ read) begin
if (read) begin
if (DEPTH > 1)
mem_used[0] <= mem_used[1];
else
mem_used[0] <= 0;
end
if (write)
mem_used[0] <= 1;
end
end
end
if (DEPTH > 1) begin
always @(posedge clk or posedge reset) begin
if (reset) begin
mem_used[DEPTH-1] <= 0;
end
else begin
if (write ^ read) begin
mem_used[DEPTH-1] <= 0;
if (write)
mem_used[DEPTH-1] <= mem_used[DEPTH-2];
end
end
end
end
for (i = 1; i < DEPTH-1; i = i + 1) begin : storage_logic
always @(posedge clk, posedge reset) begin
if (reset) begin
mem_used[i] <= 0;
end
else begin
if (write ^ read) begin
if (read)
mem_used[i] <= mem_used[i+1];
if (write)
mem_used[i] <= mem_used[i-1];
end
end
end
end
end
endgenerate
// --------------------------------------------------
// Memory FIFO Status Management
//
// Generates the full and empty signals from the
// pointers. The FIFO is full when the next write
// pointer will be equal to the read pointer after
// a write. Reading from a FIFO clears full.
//
// The FIFO is empty when the next read pointer will
// be equal to the write pointer after a read. Writing
// to a FIFO clears empty.
//
// A simultaneous read and write must not change any of
// the empty or full flags unless there is a drop on error event.
// --------------------------------------------------
generate if (USE_MEMORY_BLOCKS == 1) begin
always @* begin
next_full = full;
next_empty = empty;
if (read && !write) begin
next_full = 1'b0;
if (incremented_rd_ptr == wr_ptr)
next_empty = 1'b1;
end
if (write && !read) begin
if (!drop_on_error)
next_empty = 1'b0;
else if (sop_ptr == rd_ptr) // drop on error and only 1 pkt in fifo
next_empty = 1'b1;
if (incremented_wr_ptr == rd_ptr && !drop_on_error)
next_full = 1'b1;
end
if (write && read && drop_on_error) begin
if (sop_ptr == next_rd_ptr)
next_empty = 1'b1;
end
end
always @(posedge clk or posedge reset) begin
if (reset) begin
empty <= 1;
full <= 0;
end
else begin
empty <= next_empty;
full <= next_full;
end
end
end else begin
// --------------------------------------------------
// Register FIFO Status Management
//
// Full when the tail occupancy bit is 1. Empty when
// the head occupancy bit is 0.
// --------------------------------------------------
always @* begin
full = mem_used[DEPTH-1];
empty = !mem_used[0];
// ------------------------------------------
// For a single slot FIFO, reading clears the
// full status immediately.
// ------------------------------------------
if (DEPTH == 1)
full = mem_used[0] && !read;
internal_out_payload = mem[0];
// ------------------------------------------
// Writes clear empty immediately for lookahead modes.
// Note that we use in_valid instead of write to avoid
// combinational loops (in lookahead mode, qualifying
// with in_ready is meaningless).
//
// In a 1-deep FIFO, a possible combinational loop runs
// from write -> out_valid -> out_ready -> write
// ------------------------------------------
if (EMPTY_LATENCY == 0) begin
empty = !mem_used[0] && !in_valid;
if (!mem_used[0] && in_valid)
internal_out_payload = in_payload;
end
end
end
endgenerate
// --------------------------------------------------
// Avalon-ST Signals
//
// The in_ready signal is straightforward.
//
// To match memory latency when empty latency > 1,
// out_valid assertions must be delayed by one clock
// cycle.
//
// Note: out_valid deassertions must not be delayed or
// the FIFO will underflow.
// --------------------------------------------------
assign in_ready = !full;
assign internal_out_ready = out_ready || !out_valid;
generate if (EMPTY_LATENCY > 1) begin
always @(posedge clk or posedge reset) begin
if (reset)
internal_out_valid <= 0;
else begin
internal_out_valid <= !empty & ok_to_forward & ~drop_on_error;
if (read) begin
if (incremented_rd_ptr == wr_ptr)
internal_out_valid <= 1'b0;
end
end
end
end else begin
always @* begin
internal_out_valid = !empty & ok_to_forward;
end
end
endgenerate
// --------------------------------------------------
// Single Output Pipeline Stage
//
// This output pipeline stage is enabled if the FIFO's
// empty latency is set to 3 (default). It is disabled
// for all other allowed latencies.
//
// Reason: The memory outputs are unregistered, so we have to
// register the output or fmax will drop if combinatorial
// logic is present on the output datapath.
//
// Q: The Avalon-ST spec says that I have to register my outputs
// But isn't the memory counted as a register?
// A: The path from the address lookup to the memory output is
// slow. Registering the memory outputs is a good idea.
//
// The registers get packed into the memory by the fitter
// which means minimal resources are consumed (the result
// is a altsyncram with registered outputs, available on
// all modern Altera devices).
//
// This output stage acts as an extra slot in the FIFO,
// and complicates the fill level.
// --------------------------------------------------
generate if (EMPTY_LATENCY == 3) begin
always @(posedge clk or posedge reset) begin
if (reset) begin
out_valid <= 0;
out_payload <= 0;
end
else begin
if (internal_out_ready) begin
out_valid <= internal_out_valid & ok_to_forward;
out_payload <= internal_out_payload;
end
end
end
end
else begin
always @* begin
out_valid = internal_out_valid;
out_payload = internal_out_payload;
end
end
endgenerate
// --------------------------------------------------
// Fill Level
//
// The fill level is calculated from the next write
// and read pointers to avoid unnecessary latency.
//
// If the output pipeline is enabled, the fill level
// must account for it, or we'll always be off by one.
// This may, or may not be important depending on the
// application.
//
// For now, we'll always calculate the exact fill level
// at the cost of an extra adder when the output stage
// is enabled.
// --------------------------------------------------
generate if (USE_FILL_LEVEL) begin
wire [31:0] depth32;
assign depth32 = DEPTH;
always @(posedge clk or posedge reset) begin
if (reset)
fifo_fill_level <= 0;
else if (next_full & !drop_on_error)
fifo_fill_level <= depth32[ADDR_WIDTH:0];
else begin
fifo_fill_level[ADDR_WIDTH] <= 1'b0;
fifo_fill_level[ADDR_WIDTH-1 : 0] <= next_wr_ptr - next_rd_ptr;
end
end
always @* begin
fill_level = fifo_fill_level;
if (EMPTY_LATENCY == 3)
fill_level = fifo_fill_level + {{ADDR_WIDTH{1'b0}}, out_valid};
end
end
else begin
always @* begin
fill_level = 0;
end
end
endgenerate
generate if (USE_ALMOST_FULL_IF) begin
assign almost_full_data = (fill_level >= almost_full_threshold);
end
else
assign almost_full_data = 0;
endgenerate
generate if (USE_ALMOST_EMPTY_IF) begin
assign almost_empty_data = (fill_level <= almost_empty_threshold);
end
else
assign almost_empty_data = 0;
endgenerate
// --------------------------------------------------
// Avalon-MM Status & Control Connection Point
//
// Register map:
//
// | Addr | RW | 31 - 0 |
// | 0 | R | Fill level |
//
// The registering of this connection point means
// that there is a cycle of latency between
// reads/writes and the updating of the fill level.
// --------------------------------------------------
generate if (USE_STORE_FORWARD) begin
assign max_fifo_size = FIFO_DEPTH - 1;
always @(posedge clk or posedge reset) begin
if (reset) begin
almost_full_threshold <= max_fifo_size[23 : 0];
almost_empty_threshold <= 0;
cut_through_threshold <= 0;
drop_on_error_en <= 0;
csr_readdata <= 0;
pkt_mode <= 1'b1;
end
else begin
if (csr_write) begin
if(csr_address == 3'b010)
almost_full_threshold <= csr_writedata[23:0];
if(csr_address == 3'b011)
almost_empty_threshold <= csr_writedata[23:0];
if(csr_address == 3'b100) begin
cut_through_threshold <= csr_writedata[23:0];
pkt_mode <= (csr_writedata[23:0] == 0);
end
if(csr_address == 3'b101)
drop_on_error_en <= csr_writedata[0];
end
if (csr_read) begin
csr_readdata <= 32'b0;
if (csr_address == 0)
csr_readdata <= {{(31 - ADDR_WIDTH){1'b0}}, fill_level};
if (csr_address == 2)
csr_readdata <= {8'b0, almost_full_threshold};
if (csr_address == 3)
csr_readdata <= {8'b0, almost_empty_threshold};
if (csr_address == 4)
csr_readdata <= {8'b0, cut_through_threshold};
if (csr_address == 5)
csr_readdata <= {31'b0, drop_on_error_en};
end
end
end
end
else if (USE_ALMOST_FULL_IF || USE_ALMOST_EMPTY_IF) begin
assign max_fifo_size = FIFO_DEPTH - 1;
always @(posedge clk or posedge reset) begin
if (reset) begin
almost_full_threshold <= max_fifo_size[23 : 0];
almost_empty_threshold <= 0;
csr_readdata <= 0;
end
else begin
if (csr_write) begin
if(csr_address == 3'b010)
almost_full_threshold <= csr_writedata[23:0];
if(csr_address == 3'b011)
almost_empty_threshold <= csr_writedata[23:0];
end
if (csr_read) begin
csr_readdata <= 32'b0;
if (csr_address == 0)
csr_readdata <= {{(31 - ADDR_WIDTH){1'b0}}, fill_level};
if (csr_address == 2)
csr_readdata <= {8'b0, almost_full_threshold};
if (csr_address == 3)
csr_readdata <= {8'b0, almost_empty_threshold};
end
end
end
end
else begin
always @(posedge clk or posedge reset) begin
if (reset) begin
csr_readdata <= 0;
end
else if (csr_read) begin
csr_readdata <= 0;
if (csr_address == 0)
csr_readdata <= fill_level;
end
end
end
endgenerate
// --------------------------------------------------
// Store and forward logic
// --------------------------------------------------
// if the fifo gets full before the entire packet or the
// cut-threshold condition is met then start sending out
// data in order to avoid dead-lock situation
generate if (USE_STORE_FORWARD) begin
assign wait_for_threshold = (fifo_fill_level_lt_cut_through_threshold) & wait_for_pkt ;
assign wait_for_pkt = pkt_cnt_eq_zero | (pkt_cnt_eq_one & out_pkt_leave);
assign ok_to_forward = (pkt_mode ? (~wait_for_pkt | ~pkt_has_started) :
~wait_for_threshold) | fifo_too_small_r;
assign in_pkt_eop_arrive = in_valid & in_ready & in_endofpacket;
assign in_pkt_start = in_valid & in_ready & in_startofpacket;
assign in_pkt_error = in_valid & in_ready & |in_error;
assign out_pkt_sop_leave = out_valid & out_ready & out_startofpacket;
assign out_pkt_leave = out_valid & out_ready & out_endofpacket;
assign fifo_too_small = (pkt_mode ? wait_for_pkt : wait_for_threshold) & full & out_ready;
// count packets coming and going into the fifo
always @(posedge clk or posedge reset) begin
if (reset) begin
pkt_cnt <= 0;
pkt_cnt_r <= 0;
pkt_cnt_plusone <= 1;
pkt_cnt_minusone <= 0;
pkt_cnt_changed <= 0;
pkt_has_started <= 0;
sop_has_left_fifo <= 0;
fifo_too_small_r <= 0;
pkt_cnt_eq_zero <= 1'b1;
pkt_cnt_eq_one <= 1'b0;
fifo_fill_level_lt_cut_through_threshold <= 1'b1;
end
else begin
fifo_fill_level_lt_cut_through_threshold <= fifo_fill_level < cut_through_threshold;
fifo_too_small_r <= fifo_too_small;
pkt_cnt_plusone <= pkt_cnt + 1'b1;
pkt_cnt_minusone <= pkt_cnt - 1'b1;
pkt_cnt_r <= pkt_cnt;
pkt_cnt_changed <= 1'b0;
if( in_pkt_eop_arrive )
sop_has_left_fifo <= 1'b0;
else if (out_pkt_sop_leave & pkt_cnt_eq_zero )
sop_has_left_fifo <= 1'b1;
if (in_pkt_eop_arrive & ~out_pkt_leave & ~drop_on_error ) begin
pkt_cnt_changed <= 1'b1;
pkt_cnt <= pkt_cnt_changed ? pkt_cnt_r : pkt_cnt_plusone;
pkt_cnt_eq_zero <= 0;
if (pkt_cnt == 0)
pkt_cnt_eq_one <= 1'b1;
else
pkt_cnt_eq_one <= 1'b0;
end
else if((~in_pkt_eop_arrive | drop_on_error) & out_pkt_leave) begin
pkt_cnt_changed <= 1'b1;
pkt_cnt <= pkt_cnt_changed ? pkt_cnt_r : pkt_cnt_minusone;
if (pkt_cnt == 1)
pkt_cnt_eq_zero <= 1'b1;
else
pkt_cnt_eq_zero <= 1'b0;
if (pkt_cnt == 2)
pkt_cnt_eq_one <= 1'b1;
else
pkt_cnt_eq_one <= 1'b0;
end
if (in_pkt_start)
pkt_has_started <= 1'b1;
else if (in_pkt_eop_arrive)
pkt_has_started <= 1'b0;
end
end
// drop on error logic
always @(posedge clk or posedge reset) begin
if (reset) begin
sop_ptr <= 0;
error_in_pkt <= 0;
end
else begin
// save the location of the SOP
if ( in_pkt_start )
sop_ptr <= wr_ptr;
// remember if error in pkt
// log error only if packet has already started
if (in_pkt_eop_arrive)
error_in_pkt <= 1'b0;
else if ( in_pkt_error & (pkt_has_started | in_pkt_start))
error_in_pkt <= 1'b1;
end
end
assign drop_on_error = drop_on_error_en & (error_in_pkt | in_pkt_error) & in_pkt_eop_arrive &
~sop_has_left_fifo & ~(out_pkt_sop_leave & pkt_cnt_eq_zero);
end
else begin
assign ok_to_forward = 1'b1;
assign drop_on_error = 1'b0;
end
endgenerate
// --------------------------------------------------
// Calculates the log2ceil of the input value
// --------------------------------------------------
function integer log2ceil;
input integer val;
integer i;
begin
i = 1;
log2ceil = 0;
while (i < val) begin
log2ceil = log2ceil + 1;
i = i << 1;
end
end
endfunction
endmodule
|
/////////////////////////////////////////////////////////////////////
//// ////
//// EXCEPT ////
//// Floating Point Exception/Special Numbers Unit ////
//// ////
//// Author: Rudolf Usselmann ////
//// [email protected] ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Rudolf Usselmann ////
//// [email protected] ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
`timescale 1ns / 100ps
module except( clk, opa, opb, inf, ind, qnan, snan, opa_nan, opb_nan,
opa_00, opb_00, opa_inf, opb_inf, opa_dn, opb_dn);
input clk;
input [31:0] opa, opb;
output inf, ind, qnan, snan, opa_nan, opb_nan;
output opa_00, opb_00;
output opa_inf, opb_inf;
output opa_dn;
output opb_dn;
////////////////////////////////////////////////////////////////////////
//
// Local Wires and registers
//
wire [7:0] expa, expb; // alias to opX exponent
wire [22:0] fracta, fractb; // alias to opX fraction
reg expa_ff, infa_f_r, qnan_r_a, snan_r_a;
reg expb_ff, infb_f_r, qnan_r_b, snan_r_b;
reg inf, ind, qnan, snan; // Output registers
reg opa_nan, opb_nan;
reg expa_00, expb_00, fracta_00, fractb_00;
reg opa_00, opb_00;
reg opa_inf, opb_inf;
reg opa_dn, opb_dn;
////////////////////////////////////////////////////////////////////////
//
// Aliases
//
assign expa = opa[30:23];
assign expb = opb[30:23];
assign fracta = opa[22:0];
assign fractb = opb[22:0];
////////////////////////////////////////////////////////////////////////
//
// Determine if any of the input operators is a INF or NAN or any other special number
//
always @(posedge clk)
expa_ff <= #1 &expa;
always @(posedge clk)
expb_ff <= #1 &expb;
always @(posedge clk)
infa_f_r <= #1 !(|fracta);
always @(posedge clk)
infb_f_r <= #1 !(|fractb);
always @(posedge clk)
qnan_r_a <= #1 fracta[22];
always @(posedge clk)
snan_r_a <= #1 !fracta[22] & |fracta[21:0];
always @(posedge clk)
qnan_r_b <= #1 fractb[22];
always @(posedge clk)
snan_r_b <= #1 !fractb[22] & |fractb[21:0];
always @(posedge clk)
ind <= #1 (expa_ff & infa_f_r) & (expb_ff & infb_f_r);
always @(posedge clk)
inf <= #1 (expa_ff & infa_f_r) | (expb_ff & infb_f_r);
always @(posedge clk)
qnan <= #1 (expa_ff & qnan_r_a) | (expb_ff & qnan_r_b);
always @(posedge clk)
snan <= #1 (expa_ff & snan_r_a) | (expb_ff & snan_r_b);
always @(posedge clk)
opa_nan <= #1 &expa & (|fracta[22:0]);
always @(posedge clk)
opb_nan <= #1 &expb & (|fractb[22:0]);
always @(posedge clk)
opa_inf <= #1 (expa_ff & infa_f_r);
always @(posedge clk)
opb_inf <= #1 (expb_ff & infb_f_r);
always @(posedge clk)
expa_00 <= #1 !(|expa);
always @(posedge clk)
expb_00 <= #1 !(|expb);
always @(posedge clk)
fracta_00 <= #1 !(|fracta);
always @(posedge clk)
fractb_00 <= #1 !(|fractb);
always @(posedge clk)
opa_00 <= #1 expa_00 & fracta_00;
always @(posedge clk)
opb_00 <= #1 expb_00 & fractb_00;
always @(posedge clk)
opa_dn <= #1 expa_00;
always @(posedge clk)
opb_dn <= #1 expb_00;
endmodule
|
/////////////////////////////////////////////////////////////////////
//// ////
//// FPU ////
//// Floating Point Unit (Single precision) ////
//// ////
//// Author: Rudolf Usselmann ////
//// [email protected] ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Rudolf Usselmann ////
//// [email protected] ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
`timescale 1ns / 100ps
/*
FPU Operations (fpu_op):
========================
0 = add
1 = sub
2 = mul
3 = div
4 =
5 =
6 =
7 =
Rounding Modes (rmode):
=======================
0 = round_nearest_even
1 = round_to_zero
2 = round_up
3 = round_down
*/
module fpu( clk, rmode, fpu_op, opa, opb, out, inf, snan, qnan, ine, overflow, underflow, zero, div_by_zero);
input clk;
input [1:0] rmode;
input [2:0] fpu_op;
input [31:0] opa, opb;
output [31:0] out;
output inf, snan, qnan;
output ine;
output overflow, underflow;
output zero;
output div_by_zero;
parameter INF = 31'h7f800000,
QNAN = 31'h7fc00001,
SNAN = 31'h7f800001;
////////////////////////////////////////////////////////////////////////
//
// Local Wires
//
reg zero;
reg [31:0] opa_r, opb_r; // Input operand registers
reg [31:0] out; // Output register
reg div_by_zero; // Divide by zero output register
wire signa, signb; // alias to opX sign
wire sign_fasu; // sign output
wire [26:0] fracta, fractb; // Fraction Outputs from EQU block
wire [7:0] exp_fasu; // Exponent output from EQU block
reg [7:0] exp_r; // Exponent output (registerd)
wire [26:0] fract_out_d; // fraction output
wire co; // carry output
reg [27:0] fract_out_q; // fraction output (registerd)
wire [30:0] out_d; // Intermediate final result output
wire overflow_d, underflow_d;// Overflow/Underflow Indicators
reg overflow, underflow; // Output registers for Overflow & Underflow
reg inf, snan, qnan; // Output Registers for INF, SNAN and QNAN
reg ine; // Output Registers for INE
reg [1:0] rmode_r1, rmode_r2, // Pipeline registers for rounding mode
rmode_r3;
reg [2:0] fpu_op_r1, fpu_op_r2, // Pipeline registers for fp opration
fpu_op_r3;
wire mul_inf, div_inf;
wire mul_00, div_00;
////////////////////////////////////////////////////////////////////////
//
// Input Registers
//
always @(posedge clk)
opa_r <= #1 opa;
always @(posedge clk)
opb_r <= #1 opb;
always @(posedge clk)
rmode_r1 <= #1 rmode;
always @(posedge clk)
rmode_r2 <= #1 rmode_r1;
always @(posedge clk)
rmode_r3 <= #1 rmode_r2;
always @(posedge clk)
fpu_op_r1 <= #1 fpu_op;
always @(posedge clk)
fpu_op_r2 <= #1 fpu_op_r1;
always @(posedge clk)
fpu_op_r3 <= #1 fpu_op_r2;
////////////////////////////////////////////////////////////////////////
//
// Exceptions block
//
wire inf_d, ind_d, qnan_d, snan_d, opa_nan, opb_nan;
wire opa_00, opb_00;
wire opa_inf, opb_inf;
wire opa_dn, opb_dn;
except u0( .clk(clk),
.opa(opa_r), .opb(opb_r),
.inf(inf_d), .ind(ind_d),
.qnan(qnan_d), .snan(snan_d),
.opa_nan(opa_nan), .opb_nan(opb_nan),
.opa_00(opa_00), .opb_00(opb_00),
.opa_inf(opa_inf), .opb_inf(opb_inf),
.opa_dn(opa_dn), .opb_dn(opb_dn)
);
////////////////////////////////////////////////////////////////////////
//
// Pre-Normalize block
// - Adjusts the numbers to equal exponents and sorts them
// - determine result sign
// - determine actual operation to perform (add or sub)
//
wire nan_sign_d, result_zero_sign_d;
reg sign_fasu_r;
wire [7:0] exp_mul;
wire sign_mul;
reg sign_mul_r;
wire [23:0] fracta_mul, fractb_mul;
wire inf_mul;
reg inf_mul_r;
wire [1:0] exp_ovf;
reg [1:0] exp_ovf_r;
wire sign_exe;
reg sign_exe_r;
wire [2:0] underflow_fmul_d;
pre_norm u1(.clk(clk), // System Clock
.rmode(rmode_r2), // Roundin Mode
.add(!fpu_op_r1[0]), // Add/Sub Input
.opa(opa_r), .opb(opb_r), // Registered OP Inputs
.opa_nan(opa_nan), // OpA is a NAN indicator
.opb_nan(opb_nan), // OpB is a NAN indicator
.fracta_out(fracta), // Equalized and sorted fraction
.fractb_out(fractb), // outputs (Registered)
.exp_dn_out(exp_fasu), // Selected exponent output (registered);
.sign(sign_fasu), // Encoded output Sign (registered)
.nan_sign(nan_sign_d), // Output Sign for NANs (registered)
.result_zero_sign(result_zero_sign_d), // Output Sign for zero result (registered)
.fasu_op(fasu_op) // Actual fasu operation output (registered)
);
always @(posedge clk)
sign_fasu_r <= #1 sign_fasu;
pre_norm_fmul u2(
.clk(clk),
.fpu_op(fpu_op_r1),
.opa(opa_r), .opb(opb_r),
.fracta(fracta_mul),
.fractb(fractb_mul),
.exp_out(exp_mul), // FMUL exponent output (registered)
.sign(sign_mul), // FMUL sign output (registered)
.sign_exe(sign_exe), // FMUL exception sign output (registered)
.inf(inf_mul), // FMUL inf output (registered)
.exp_ovf(exp_ovf), // FMUL exponnent overflow output (registered)
.underflow(underflow_fmul_d)
);
always @(posedge clk)
sign_mul_r <= #1 sign_mul;
always @(posedge clk)
sign_exe_r <= #1 sign_exe;
always @(posedge clk)
inf_mul_r <= #1 inf_mul;
always @(posedge clk)
exp_ovf_r <= #1 exp_ovf;
////////////////////////////////////////////////////////////////////////
//
// Add/Sub
//
add_sub27 u3(
.add(fasu_op), // Add/Sub
.opa(fracta), // Fraction A input
.opb(fractb), // Fraction B Input
.sum(fract_out_d), // SUM output
.co(co_d) ); // Carry Output
always @(posedge clk)
fract_out_q <= #1 {co_d, fract_out_d};
////////////////////////////////////////////////////////////////////////
//
// Mul
//
wire [47:0] prod;
mul_r2 u5(.clk(clk), .opa(fracta_mul), .opb(fractb_mul), .prod(prod));
////////////////////////////////////////////////////////////////////////
//
// Divide
//
wire [49:0] quo;
wire [49:0] fdiv_opa;
wire [49:0] remainder;
wire remainder_00;
reg [4:0] div_opa_ldz_d, div_opa_ldz_r1, div_opa_ldz_r2;
always @(fracta_mul)
casex(fracta_mul[22:0])
23'b1??????????????????????: div_opa_ldz_d = 1;
23'b01?????????????????????: div_opa_ldz_d = 2;
23'b001????????????????????: div_opa_ldz_d = 3;
23'b0001???????????????????: div_opa_ldz_d = 4;
23'b00001??????????????????: div_opa_ldz_d = 5;
23'b000001?????????????????: div_opa_ldz_d = 6;
23'b0000001????????????????: div_opa_ldz_d = 7;
23'b00000001???????????????: div_opa_ldz_d = 8;
23'b000000001??????????????: div_opa_ldz_d = 9;
23'b0000000001?????????????: div_opa_ldz_d = 10;
23'b00000000001????????????: div_opa_ldz_d = 11;
23'b000000000001???????????: div_opa_ldz_d = 12;
23'b0000000000001??????????: div_opa_ldz_d = 13;
23'b00000000000001?????????: div_opa_ldz_d = 14;
23'b000000000000001????????: div_opa_ldz_d = 15;
23'b0000000000000001???????: div_opa_ldz_d = 16;
23'b00000000000000001??????: div_opa_ldz_d = 17;
23'b000000000000000001?????: div_opa_ldz_d = 18;
23'b0000000000000000001????: div_opa_ldz_d = 19;
23'b00000000000000000001???: div_opa_ldz_d = 20;
23'b000000000000000000001??: div_opa_ldz_d = 21;
23'b0000000000000000000001?: div_opa_ldz_d = 22;
23'b0000000000000000000000?: div_opa_ldz_d = 23;
endcase
assign fdiv_opa = !(|opa_r[30:23]) ? {(fracta_mul<<div_opa_ldz_d), 26'h0} : {fracta_mul, 26'h0};
div_r2 u6(.clk(clk), .opa(fdiv_opa), .opb(fractb_mul), .quo(quo), .rem(remainder));
assign remainder_00 = !(|remainder);
always @(posedge clk)
div_opa_ldz_r1 <= #1 div_opa_ldz_d;
always @(posedge clk)
div_opa_ldz_r2 <= #1 div_opa_ldz_r1;
////////////////////////////////////////////////////////////////////////
//
// Normalize Result
//
wire ine_d;
reg [47:0] fract_denorm;
wire [47:0] fract_div;
wire sign_d;
reg sign;
reg [30:0] opa_r1;
reg [47:0] fract_i2f;
reg opas_r1, opas_r2;
wire f2i_out_sign;
always @(posedge clk) // Exponent must be once cycle delayed
case(fpu_op_r2)
0,1: exp_r <= #1 exp_fasu;
2,3: exp_r <= #1 exp_mul;
4: exp_r <= #1 0;
5: exp_r <= #1 opa_r1[30:23];
endcase
assign fract_div = (opb_dn ? quo[49:2] : {quo[26:0], 21'h0});
always @(posedge clk)
opa_r1 <= #1 opa_r[30:0];
always @(posedge clk)
fract_i2f <= #1 (fpu_op_r2==5) ?
(sign_d ? 1-{24'h00, (|opa_r1[30:23]), opa_r1[22:0]}-1 : {24'h0, (|opa_r1[30:23]), opa_r1[22:0]}) :
(sign_d ? 1 - {opa_r1, 17'h01} : {opa_r1, 17'h0});
always @(fpu_op_r3 or fract_out_q or prod or fract_div or fract_i2f)
case(fpu_op_r3)
0,1: fract_denorm = {fract_out_q, 20'h0};
2: fract_denorm = prod;
3: fract_denorm = fract_div;
4,5: fract_denorm = fract_i2f;
endcase
always @(posedge clk)
opas_r1 <= #1 opa_r[31];
always @(posedge clk)
opas_r2 <= #1 opas_r1;
assign sign_d = fpu_op_r2[1] ? sign_mul : sign_fasu;
always @(posedge clk)
sign <= #1 (rmode_r2==2'h3) ? !sign_d : sign_d;
post_norm u4(.clk(clk), // System Clock
.fpu_op(fpu_op_r3), // Floating Point Operation
.opas(opas_r2), // OPA Sign
.sign(sign), // Sign of the result
.rmode(rmode_r3), // Rounding mode
.fract_in(fract_denorm), // Fraction Input
.exp_ovf(exp_ovf_r), // Exponent Overflow
.exp_in(exp_r), // Exponent Input
.opa_dn(opa_dn), // Operand A Denormalized
.opb_dn(opb_dn), // Operand A Denormalized
.rem_00(remainder_00), // Diveide Remainder is zero
.div_opa_ldz(div_opa_ldz_r2), // Divide opa leading zeros count
.output_zero(mul_00 | div_00), // Force output to Zero
.out(out_d), // Normalized output (un-registered)
.ine(ine_d), // Result Inexact output (un-registered)
.overflow(overflow_d), // Overflow output (un-registered)
.underflow(underflow_d), // Underflow output (un-registered)
.f2i_out_sign(f2i_out_sign) // F2I Output Sign
);
////////////////////////////////////////////////////////////////////////
//
// FPU Outputs
//
reg fasu_op_r1, fasu_op_r2;
wire [30:0] out_fixed;
wire output_zero_fasu;
wire output_zero_fdiv;
wire output_zero_fmul;
reg inf_mul2;
wire overflow_fasu;
wire overflow_fmul;
wire overflow_fdiv;
wire inf_fmul;
wire sign_mul_final;
wire out_d_00;
wire sign_div_final;
wire ine_mul, ine_mula, ine_div, ine_fasu;
wire underflow_fasu, underflow_fmul, underflow_fdiv;
wire underflow_fmul1;
reg [2:0] underflow_fmul_r;
reg opa_nan_r;
always @(posedge clk)
fasu_op_r1 <= #1 fasu_op;
always @(posedge clk)
fasu_op_r2 <= #1 fasu_op_r1;
always @(posedge clk)
inf_mul2 <= #1 exp_mul == 8'hff;
// Force pre-set values for non numerical output
assign mul_inf = (fpu_op_r3==3'b010) & (inf_mul_r | inf_mul2) & (rmode_r3==2'h0);
assign div_inf = (fpu_op_r3==3'b011) & (opb_00 | opa_inf);
assign mul_00 = (fpu_op_r3==3'b010) & (opa_00 | opb_00);
assign div_00 = (fpu_op_r3==3'b011) & (opa_00 | opb_inf);
assign out_fixed = ( (qnan_d | snan_d) |
(ind_d & !fasu_op_r2) |
((fpu_op_r3==3'b011) & opb_00 & opa_00) |
(((opa_inf & opb_00) | (opb_inf & opa_00 )) & fpu_op_r3==3'b010)
) ? QNAN : INF;
always @(posedge clk)
out[30:0] <= #1 (mul_inf | div_inf | (inf_d & (fpu_op_r3!=3'b011) & (fpu_op_r3!=3'b101)) | snan_d | qnan_d) & fpu_op_r3!=3'b100 ? out_fixed :
out_d;
assign out_d_00 = !(|out_d);
assign sign_mul_final = (sign_exe_r & ((opa_00 & opb_inf) | (opb_00 & opa_inf))) ? !sign_mul_r : sign_mul_r;
assign sign_div_final = (sign_exe_r & (opa_inf & opb_inf)) ? !sign_mul_r : sign_mul_r | (opa_00 & opb_00);
always @(posedge clk)
out[31] <= #1 ((fpu_op_r3==3'b101) & out_d_00) ? (f2i_out_sign & !(qnan_d | snan_d) ) :
((fpu_op_r3==3'b010) & !(snan_d | qnan_d)) ? sign_mul_final :
((fpu_op_r3==3'b011) & !(snan_d | qnan_d)) ? sign_div_final :
(snan_d | qnan_d | ind_d) ? nan_sign_d :
output_zero_fasu ? result_zero_sign_d :
sign_fasu_r;
// Exception Outputs
assign ine_mula = ((inf_mul_r | inf_mul2 | opa_inf | opb_inf) & (rmode_r3==2'h1) &
!((opa_inf & opb_00) | (opb_inf & opa_00 )) & fpu_op_r3[1]);
assign ine_mul = (ine_mula | ine_d | inf_fmul | out_d_00 | overflow_d | underflow_d) &
!opa_00 & !opb_00 & !(snan_d | qnan_d | inf_d);
assign ine_div = (ine_d | overflow_d | underflow_d) & !(opb_00 | snan_d | qnan_d | inf_d);
assign ine_fasu = (ine_d | overflow_d | underflow_d) & !(snan_d | qnan_d | inf_d);
always @(posedge clk)
ine <= #1 fpu_op_r3[2] ? ine_d :
!fpu_op_r3[1] ? ine_fasu :
fpu_op_r3[0] ? ine_div : ine_mul;
assign overflow_fasu = overflow_d & !(snan_d | qnan_d | inf_d);
assign overflow_fmul = !inf_d & (inf_mul_r | inf_mul2 | overflow_d) & !(snan_d | qnan_d);
assign overflow_fdiv = (overflow_d & !(opb_00 | inf_d | snan_d | qnan_d));
always @(posedge clk)
overflow <= #1 fpu_op_r3[2] ? 0 :
!fpu_op_r3[1] ? overflow_fasu :
fpu_op_r3[0] ? overflow_fdiv : overflow_fmul;
always @(posedge clk)
underflow_fmul_r <= #1 underflow_fmul_d;
assign underflow_fmul1 = underflow_fmul_r[0] |
(underflow_fmul_r[1] & underflow_d ) |
((opa_dn | opb_dn) & out_d_00 & (prod!=0) & sign) |
(underflow_fmul_r[2] & ((out_d[30:23]==0) | (out_d[22:0]==0)));
assign underflow_fasu = underflow_d & !(inf_d | snan_d | qnan_d);
assign underflow_fmul = underflow_fmul1 & !(snan_d | qnan_d | inf_mul_r);
assign underflow_fdiv = underflow_fasu & !opb_00;
always @(posedge clk)
underflow <= #1 fpu_op_r3[2] ? 0 :
!fpu_op_r3[1] ? underflow_fasu :
fpu_op_r3[0] ? underflow_fdiv : underflow_fmul;
always @(posedge clk)
snan <= #1 snan_d;
// synopsys translate_off
wire mul_uf_del;
wire uf2_del, ufb2_del, ufc2_del, underflow_d_del;
wire co_del;
wire [30:0] out_d_del;
wire ov_fasu_del, ov_fmul_del;
wire [2:0] fop;
wire [4:0] ldza_del;
wire [49:0] quo_del;
delay1 #0 ud000(clk, underflow_fmul1, mul_uf_del);
delay1 #0 ud001(clk, underflow_fmul_r[0], uf2_del);
delay1 #0 ud002(clk, underflow_fmul_r[1], ufb2_del);
delay1 #0 ud003(clk, underflow_d, underflow_d_del);
delay1 #0 ud004(clk, test.u0.u4.exp_out1_co, co_del);
delay1 #0 ud005(clk, underflow_fmul_r[2], ufc2_del);
delay1 #30 ud006(clk, out_d, out_d_del);
delay1 #0 ud007(clk, overflow_fasu, ov_fasu_del);
delay1 #0 ud008(clk, overflow_fmul, ov_fmul_del);
delay1 #2 ud009(clk, fpu_op_r3, fop);
delay3 #4 ud010(clk, div_opa_ldz_d, ldza_del);
delay1 #49 ud012(clk, quo, quo_del);
always @(test.error_event)
begin
#0.2
$display("muf: %b uf0: %b uf1: %b uf2: %b, tx0: %b, co: %b, out_d: %h (%h %h), ov_fasu: %b, ov_fmul: %b, fop: %h",
mul_uf_del, uf2_del, ufb2_del, ufc2_del, underflow_d_del, co_del, out_d_del, out_d_del[30:23], out_d_del[22:0],
ov_fasu_del, ov_fmul_del, fop );
$display("ldza: %h, quo: %b",
ldza_del, quo_del);
end
// synopsys translate_on
// Status Outputs
always @(posedge clk)
qnan <= #1 fpu_op_r3[2] ? 0 : (
snan_d | qnan_d | (ind_d & !fasu_op_r2) |
(opa_00 & opb_00 & fpu_op_r3==3'b011) |
(((opa_inf & opb_00) | (opb_inf & opa_00 )) & fpu_op_r3==3'b010)
);
assign inf_fmul = (((inf_mul_r | inf_mul2) & (rmode_r3==2'h0)) | opa_inf | opb_inf) &
!((opa_inf & opb_00) | (opb_inf & opa_00 )) &
fpu_op_r3==3'b010;
always @(posedge clk)
inf <= #1 fpu_op_r3[2] ? 0 :
(!(qnan_d | snan_d) & (
((&out_d[30:23]) & !(|out_d[22:0]) & !(opb_00 & fpu_op_r3==3'b011)) |
(inf_d & !(ind_d & !fasu_op_r2) & !fpu_op_r3[1]) |
inf_fmul |
(!opa_00 & opb_00 & fpu_op_r3==3'b011) |
(fpu_op_r3==3'b011 & opa_inf & !opb_inf)
)
);
assign output_zero_fasu = out_d_00 & !(inf_d | snan_d | qnan_d);
assign output_zero_fdiv = (div_00 | (out_d_00 & !opb_00)) & !(opa_inf & opb_inf) &
!(opa_00 & opb_00) & !(qnan_d | snan_d);
assign output_zero_fmul = (out_d_00 | opa_00 | opb_00) &
!(inf_mul_r | inf_mul2 | opa_inf | opb_inf | snan_d | qnan_d) &
!(opa_inf & opb_00) & !(opb_inf & opa_00);
always @(posedge clk)
zero <= #1 fpu_op_r3==3'b101 ? out_d_00 & !(snan_d | qnan_d):
fpu_op_r3==3'b011 ? output_zero_fdiv :
fpu_op_r3==3'b010 ? output_zero_fmul :
output_zero_fasu ;
always @(posedge clk)
opa_nan_r <= #1 !opa_nan & fpu_op_r2==3'b011;
always @(posedge clk)
div_by_zero <= #1 opa_nan_r & !opa_00 & !opa_inf & opb_00;
endmodule
|
/////////////////////////////////////////////////////////////////////
//// ////
//// Post Norm ////
//// Floating Point Post Normalisation Unit ////
//// ////
//// Author: Rudolf Usselmann ////
//// [email protected] ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Rudolf Usselmann ////
//// [email protected] ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
`timescale 1ns / 100ps
module post_norm( clk, fpu_op, opas, sign, rmode, fract_in, exp_in, exp_ovf,
opa_dn, opb_dn, rem_00, div_opa_ldz, output_zero, out,
ine, overflow, underflow, f2i_out_sign);
input clk;
input [2:0] fpu_op;
input opas;
input sign;
input [1:0] rmode;
input [47:0] fract_in;
input [1:0] exp_ovf;
input [7:0] exp_in;
input opa_dn, opb_dn;
input rem_00;
input [4:0] div_opa_ldz;
input output_zero;
output [30:0] out;
output ine;
output overflow, underflow;
output f2i_out_sign;
////////////////////////////////////////////////////////////////////////
//
// Local Wires and registers
//
wire [22:0] fract_out;
wire [7:0] exp_out;
wire [30:0] out;
wire exp_out1_co, overflow, underflow;
wire [22:0] fract_out_final;
reg [22:0] fract_out_rnd;
wire [8:0] exp_next_mi;
wire dn;
wire exp_rnd_adj;
wire [7:0] exp_out_final;
reg [7:0] exp_out_rnd;
wire op_dn = opa_dn | opb_dn;
wire op_mul = fpu_op[2:0]==3'b010;
wire op_div = fpu_op[2:0]==3'b011;
wire op_i2f = fpu_op[2:0]==3'b100;
wire op_f2i = fpu_op[2:0]==3'b101;
reg [5:0] fi_ldz;
wire g, r, s;
wire round, round2, round2a, round2_fasu, round2_fmul;
wire [7:0] exp_out_rnd0, exp_out_rnd1, exp_out_rnd2, exp_out_rnd2a;
wire [22:0] fract_out_rnd0, fract_out_rnd1, fract_out_rnd2, fract_out_rnd2a;
wire exp_rnd_adj0, exp_rnd_adj2a;
wire r_sign;
wire ovf0, ovf1;
wire [23:0] fract_out_pl1;
wire [7:0] exp_out_pl1, exp_out_mi1;
wire exp_out_00, exp_out_fe, exp_out_ff, exp_in_00, exp_in_ff;
wire exp_out_final_ff, fract_out_7fffff;
wire [24:0] fract_trunc;
wire [7:0] exp_out1;
wire grs_sel;
wire fract_out_00, fract_in_00;
wire shft_co;
wire [8:0] exp_in_pl1, exp_in_mi1;
wire [47:0] fract_in_shftr;
wire [47:0] fract_in_shftl;
wire [7:0] exp_div;
wire [7:0] shft2;
wire [7:0] exp_out1_mi1;
wire div_dn;
wire div_nr;
wire grs_sel_div;
wire div_inf;
wire [6:0] fi_ldz_2a;
wire [7:0] fi_ldz_2;
wire [7:0] div_shft1, div_shft2, div_shft3, div_shft4;
wire div_shft1_co;
wire [8:0] div_exp1;
wire [7:0] div_exp2, div_exp3;
wire left_right, lr_mul, lr_div;
wire [7:0] shift_right, shftr_mul, shftr_div;
wire [7:0] shift_left, shftl_mul, shftl_div;
wire [7:0] fasu_shift;
wire [7:0] exp_fix_div;
wire [7:0] exp_fix_diva, exp_fix_divb;
wire [5:0] fi_ldz_mi1;
wire [5:0] fi_ldz_mi22;
wire exp_zero;
wire [6:0] ldz_all;
wire [7:0] ldz_dif;
wire [8:0] div_scht1a;
wire [7:0] f2i_shft;
wire [55:0] exp_f2i_1;
wire f2i_zero, f2i_max;
wire [7:0] f2i_emin;
wire [7:0] conv_shft;
wire [7:0] exp_i2f, exp_f2i, conv_exp;
wire round2_f2i;
////////////////////////////////////////////////////////////////////////
//
// Normalize and Round Logic
//
// ---------------------------------------------------------------------
// Count Leading zeros in fraction
always @(fract_in)
casex(fract_in) // synopsys full_case parallel_case
48'b1???????????????????????????????????????????????: fi_ldz = 1;
48'b01??????????????????????????????????????????????: fi_ldz = 2;
48'b001?????????????????????????????????????????????: fi_ldz = 3;
48'b0001????????????????????????????????????????????: fi_ldz = 4;
48'b00001???????????????????????????????????????????: fi_ldz = 5;
48'b000001??????????????????????????????????????????: fi_ldz = 6;
48'b0000001?????????????????????????????????????????: fi_ldz = 7;
48'b00000001????????????????????????????????????????: fi_ldz = 8;
48'b000000001???????????????????????????????????????: fi_ldz = 9;
48'b0000000001??????????????????????????????????????: fi_ldz = 10;
48'b00000000001?????????????????????????????????????: fi_ldz = 11;
48'b000000000001????????????????????????????????????: fi_ldz = 12;
48'b0000000000001???????????????????????????????????: fi_ldz = 13;
48'b00000000000001??????????????????????????????????: fi_ldz = 14;
48'b000000000000001?????????????????????????????????: fi_ldz = 15;
48'b0000000000000001????????????????????????????????: fi_ldz = 16;
48'b00000000000000001???????????????????????????????: fi_ldz = 17;
48'b000000000000000001??????????????????????????????: fi_ldz = 18;
48'b0000000000000000001?????????????????????????????: fi_ldz = 19;
48'b00000000000000000001????????????????????????????: fi_ldz = 20;
48'b000000000000000000001???????????????????????????: fi_ldz = 21;
48'b0000000000000000000001??????????????????????????: fi_ldz = 22;
48'b00000000000000000000001?????????????????????????: fi_ldz = 23;
48'b000000000000000000000001????????????????????????: fi_ldz = 24;
48'b0000000000000000000000001???????????????????????: fi_ldz = 25;
48'b00000000000000000000000001??????????????????????: fi_ldz = 26;
48'b000000000000000000000000001?????????????????????: fi_ldz = 27;
48'b0000000000000000000000000001????????????????????: fi_ldz = 28;
48'b00000000000000000000000000001???????????????????: fi_ldz = 29;
48'b000000000000000000000000000001??????????????????: fi_ldz = 30;
48'b0000000000000000000000000000001?????????????????: fi_ldz = 31;
48'b00000000000000000000000000000001????????????????: fi_ldz = 32;
48'b000000000000000000000000000000001???????????????: fi_ldz = 33;
48'b0000000000000000000000000000000001??????????????: fi_ldz = 34;
48'b00000000000000000000000000000000001?????????????: fi_ldz = 35;
48'b000000000000000000000000000000000001????????????: fi_ldz = 36;
48'b0000000000000000000000000000000000001???????????: fi_ldz = 37;
48'b00000000000000000000000000000000000001??????????: fi_ldz = 38;
48'b000000000000000000000000000000000000001?????????: fi_ldz = 39;
48'b0000000000000000000000000000000000000001????????: fi_ldz = 40;
48'b00000000000000000000000000000000000000001???????: fi_ldz = 41;
48'b000000000000000000000000000000000000000001??????: fi_ldz = 42;
48'b0000000000000000000000000000000000000000001?????: fi_ldz = 43;
48'b00000000000000000000000000000000000000000001????: fi_ldz = 44;
48'b000000000000000000000000000000000000000000001???: fi_ldz = 45;
48'b0000000000000000000000000000000000000000000001??: fi_ldz = 46;
48'b00000000000000000000000000000000000000000000001?: fi_ldz = 47;
48'b00000000000000000000000000000000000000000000000?: fi_ldz = 48;
endcase
// ---------------------------------------------------------------------
// Normalize
wire exp_in_80;
wire rmode_00, rmode_01, rmode_10, rmode_11;
// Misc common signals
assign exp_in_ff = &exp_in;
assign exp_in_00 = !(|exp_in);
assign exp_in_80 = exp_in[7] & !(|exp_in[6:0]);
assign exp_out_ff = &exp_out;
assign exp_out_00 = !(|exp_out);
assign exp_out_fe = &exp_out[7:1] & !exp_out[0];
assign exp_out_final_ff = &exp_out_final;
assign fract_out_7fffff = &fract_out;
assign fract_out_00 = !(|fract_out);
assign fract_in_00 = !(|fract_in);
assign rmode_00 = (rmode==2'b00);
assign rmode_01 = (rmode==2'b01);
assign rmode_10 = (rmode==2'b10);
assign rmode_11 = (rmode==2'b11);
// Fasu Output will be denormalized ...
assign dn = !op_mul & !op_div & (exp_in_00 | (exp_next_mi[8] & !fract_in[47]) );
// ---------------------------------------------------------------------
// Fraction Normalization
parameter f2i_emax = 8'h9d;
// Incremented fraction for rounding
assign fract_out_pl1 = fract_out + 1;
// Special Signals for f2i
assign f2i_emin = rmode_00 ? 8'h7e : 8'h7f;
assign f2i_zero = (!opas & (exp_in<f2i_emin)) | (opas & (exp_in>f2i_emax)) | (opas & (exp_in<f2i_emin) & (fract_in_00 | !rmode_11));
assign f2i_max = (!opas & (exp_in>f2i_emax)) | (opas & (exp_in<f2i_emin) & !fract_in_00 & rmode_11);
// Claculate various shifting options
assign {shft_co,shftr_mul} = (!exp_ovf[1] & exp_in_00) ? {1'b0, exp_out} : exp_in_mi1 ;
assign {div_shft1_co, div_shft1} = exp_in_00 ? {1'b0, div_opa_ldz} : div_scht1a;
assign div_scht1a = exp_in-div_opa_ldz; // 9 bits - includes carry out
assign div_shft2 = exp_in+2;
assign div_shft3 = div_opa_ldz+exp_in;
assign div_shft4 = div_opa_ldz-exp_in;
assign div_dn = op_dn & div_shft1_co;
assign div_nr = op_dn & exp_ovf[1] & !(|fract_in[46:23]) & (div_shft3>8'h16);
assign f2i_shft = exp_in-8'h7d;
// Select shifting direction
assign left_right = op_div ? lr_div : op_mul ? lr_mul : 1;
assign lr_div = (op_dn & !exp_ovf[1] & exp_ovf[0]) ? 1 :
(op_dn & exp_ovf[1]) ? 0 :
(op_dn & div_shft1_co) ? 0 :
(op_dn & exp_out_00) ? 1 :
(!op_dn & exp_out_00 & !exp_ovf[1]) ? 1 :
exp_ovf[1] ? 0 :
1;
assign lr_mul = (shft_co | (!exp_ovf[1] & exp_in_00) |
(!exp_ovf[1] & !exp_in_00 & (exp_out1_co | exp_out_00) )) ? 1 :
( exp_ovf[1] | exp_in_00 ) ? 0 :
1;
// Select Left and Right shift value
assign fasu_shift = (dn | exp_out_00) ? (exp_in_00 ? 8'h2 : exp_in_pl1[7:0]) : {2'h0, fi_ldz};
assign shift_right = op_div ? shftr_div : shftr_mul;
assign conv_shft = op_f2i ? f2i_shft : {2'h0, fi_ldz};
assign shift_left = op_div ? shftl_div : op_mul ? shftl_mul : (op_f2i | op_i2f) ? conv_shft : fasu_shift;
assign shftl_mul = (shft_co |
(!exp_ovf[1] & exp_in_00) |
(!exp_ovf[1] & !exp_in_00 & (exp_out1_co | exp_out_00))) ? exp_in_pl1[7:0] : {2'h0, fi_ldz};
assign shftl_div = ( op_dn & exp_out_00 & !(!exp_ovf[1] & exp_ovf[0])) ? div_shft1[7:0] :
(!op_dn & exp_out_00 & !exp_ovf[1]) ? exp_in[7:0] :
{2'h0, fi_ldz};
assign shftr_div = (op_dn & exp_ovf[1]) ? div_shft3 :
(op_dn & div_shft1_co) ? div_shft4 :
div_shft2;
// Do the actual shifting
assign fract_in_shftr = (|shift_right[7:6]) ? 0 : fract_in>>shift_right[5:0];
assign fract_in_shftl = (|shift_left[7:6] | (f2i_zero & op_f2i)) ? 0 : fract_in<<shift_left[5:0];
// Chose final fraction output
assign {fract_out,fract_trunc} = left_right ? fract_in_shftl : fract_in_shftr;
// ---------------------------------------------------------------------
// Exponent Normalization
assign fi_ldz_mi1 = fi_ldz - 1;
assign fi_ldz_mi22 = fi_ldz - 22;
assign exp_out_pl1 = exp_out + 1;
assign exp_out_mi1 = exp_out - 1;
assign exp_in_pl1 = exp_in + 1; // 9 bits - includes carry out
assign exp_in_mi1 = exp_in - 1; // 9 bits - includes carry out
assign exp_out1_mi1 = exp_out1 - 1;
assign exp_next_mi = exp_in_pl1 - fi_ldz_mi1; // 9 bits - includes carry out
assign exp_fix_diva = exp_in - fi_ldz_mi22;
assign exp_fix_divb = exp_in - fi_ldz_mi1;
assign exp_zero = (exp_ovf[1] & !exp_ovf[0] & op_mul & (!exp_rnd_adj2a | !rmode[1])) | (op_mul & exp_out1_co);
assign {exp_out1_co, exp_out1} = fract_in[47] ? exp_in_pl1 : exp_next_mi;
assign f2i_out_sign = !opas ? ((exp_in<f2i_emin) ? 0 : (exp_in>f2i_emax) ? 0 : opas) :
((exp_in<f2i_emin) ? 0 : (exp_in>f2i_emax) ? 1 : opas);
assign exp_i2f = fract_in_00 ? (opas ? 8'h9e : 0) : (8'h9e-fi_ldz);
assign exp_f2i_1 = {{8{fract_in[47]}}, fract_in }<<f2i_shft;
assign exp_f2i = f2i_zero ? 0 : f2i_max ? 8'hff : exp_f2i_1[55:48];
assign conv_exp = op_f2i ? exp_f2i : exp_i2f;
assign exp_out = op_div ? exp_div : (op_f2i | op_i2f) ? conv_exp : exp_zero ? 8'h0 : dn ? {6'h0, fract_in[47:46]} : exp_out1;
assign ldz_all = div_opa_ldz + fi_ldz;
assign ldz_dif = fi_ldz_2 - div_opa_ldz;
assign fi_ldz_2a = 6'd23 - fi_ldz;
assign fi_ldz_2 = {fi_ldz_2a[6], fi_ldz_2a[6:0]};
assign div_exp1 = exp_in_mi1 + fi_ldz_2; // 9 bits - includes carry out
assign div_exp2 = exp_in_pl1 - ldz_all;
assign div_exp3 = exp_in + ldz_dif;
assign exp_div =(opa_dn & opb_dn) ? div_exp3 :
opb_dn ? div_exp1[7:0] :
(opa_dn & !( (exp_in<div_opa_ldz) | (div_exp2>9'hfe) )) ? div_exp2 :
(opa_dn | (exp_in_00 & !exp_ovf[1]) ) ? 0 :
exp_out1_mi1;
assign div_inf = opb_dn & !opa_dn & (div_exp1[7:0] < 8'h7f);
// ---------------------------------------------------------------------
// Round
// Extract rounding (GRS) bits
assign grs_sel_div = op_div & (exp_ovf[1] | div_dn | exp_out1_co | exp_out_00);
assign g = grs_sel_div ? fract_out[0] : fract_out[0];
assign r = grs_sel_div ? (fract_trunc[24] & !div_nr) : fract_trunc[24];
assign s = grs_sel_div ? |fract_trunc[24:0] : (|fract_trunc[23:0] | (fract_trunc[24] & op_div));
// Round to nearest even
assign round = (g & r) | (r & s) ;
assign {exp_rnd_adj0, fract_out_rnd0} = round ? fract_out_pl1 : {1'b0, fract_out};
assign exp_out_rnd0 = exp_rnd_adj0 ? exp_out_pl1 : exp_out;
assign ovf0 = exp_out_final_ff & !rmode_01 & !op_f2i;
// round to zero
assign fract_out_rnd1 = (exp_out_ff & !op_div & !dn & !op_f2i) ? 23'h7fffff : fract_out;
assign exp_fix_div = (fi_ldz>22) ? exp_fix_diva : exp_fix_divb;
assign exp_out_rnd1 = (g & r & s & exp_in_ff) ? (op_div ? exp_fix_div : exp_next_mi[7:0]) :
(exp_out_ff & !op_f2i) ? exp_in : exp_out;
assign ovf1 = exp_out_ff & !dn;
// round to +inf (UP) and -inf (DOWN)
assign r_sign = sign;
assign round2a = !exp_out_fe | !fract_out_7fffff | (exp_out_fe & fract_out_7fffff);
assign round2_fasu = ((r | s) & !r_sign) & (!exp_out[7] | (exp_out[7] & round2a));
assign round2_fmul = !r_sign &
(
(exp_ovf[1] & !fract_in_00 &
( ((!exp_out1_co | op_dn) & (r | s | (!rem_00 & op_div) )) | fract_out_00 | (!op_dn & !op_div))
) |
(
(r | s | (!rem_00 & op_div)) & (
(!exp_ovf[1] & (exp_in_80 | !exp_ovf[0])) | op_div |
( exp_ovf[1] & !exp_ovf[0] & exp_out1_co)
)
)
);
assign round2_f2i = rmode_10 & (( |fract_in[23:0] & !opas & (exp_in<8'h80 )) | (|fract_trunc));
assign round2 = (op_mul | op_div) ? round2_fmul : op_f2i ? round2_f2i : round2_fasu;
assign {exp_rnd_adj2a, fract_out_rnd2a} = round2 ? fract_out_pl1 : {1'b0, fract_out};
assign exp_out_rnd2a = exp_rnd_adj2a ? ((exp_ovf[1] & op_mul) ? exp_out_mi1 : exp_out_pl1) : exp_out;
assign fract_out_rnd2 = (r_sign & exp_out_ff & !op_div & !dn & !op_f2i) ? 23'h7fffff : fract_out_rnd2a;
assign exp_out_rnd2 = (r_sign & exp_out_ff & !op_f2i) ? 8'hfe : exp_out_rnd2a;
// Choose rounding mode
always @(rmode or exp_out_rnd0 or exp_out_rnd1 or exp_out_rnd2)
case(rmode) // synopsys full_case parallel_case
0: exp_out_rnd = exp_out_rnd0;
1: exp_out_rnd = exp_out_rnd1;
2,3: exp_out_rnd = exp_out_rnd2;
endcase
always @(rmode or fract_out_rnd0 or fract_out_rnd1 or fract_out_rnd2)
case(rmode) // synopsys full_case parallel_case
0: fract_out_rnd = fract_out_rnd0;
1: fract_out_rnd = fract_out_rnd1;
2,3: fract_out_rnd = fract_out_rnd2;
endcase
// ---------------------------------------------------------------------
// Final Output Mux
// Fix Output for denormalized and special numbers
wire max_num, inf_out;
assign max_num = ( !rmode_00 & (op_mul | op_div ) & (
( exp_ovf[1] & exp_ovf[0]) |
(!exp_ovf[1] & !exp_ovf[0] & exp_in_ff & (fi_ldz_2<24) & (exp_out!=8'hfe) )
)
) |
( op_div & (
( rmode_01 & ( div_inf |
(exp_out_ff & !exp_ovf[1] ) |
(exp_ovf[1] & exp_ovf[0] )
)
) |
( rmode[1] & !exp_ovf[1] & (
( exp_ovf[0] & exp_in_ff & r_sign & fract_in[47]
) |
( r_sign & (
(fract_in[47] & div_inf) |
(exp_in[7] & !exp_out_rnd[7] & !exp_in_80 & exp_out!=8'h7f ) |
(exp_in[7] & exp_out_rnd[7] & r_sign & exp_out_ff & op_dn &
div_exp1>9'h0fe )
)
) |
( exp_in_00 & r_sign & (
div_inf |
(r_sign & exp_out_ff & fi_ldz_2<24)
)
)
)
)
)
);
assign inf_out = (rmode[1] & (op_mul | op_div) & !r_sign & ( (exp_in_ff & !op_div) |
(exp_ovf[1] & exp_ovf[0] & (exp_in_00 | exp_in[7]) )
)
) | (div_inf & op_div & (
rmode_00 |
(rmode[1] & !exp_in_ff & !exp_ovf[1] & !exp_ovf[0] & !r_sign ) |
(rmode[1] & !exp_ovf[1] & exp_ovf[0] & exp_in_00 & !r_sign)
)
) | (op_div & rmode[1] & exp_in_ff & op_dn & !r_sign & (fi_ldz_2 < 24) & (exp_out_rnd!=8'hfe) );
assign fract_out_final = (inf_out | ovf0 | output_zero ) ? 23'h0 :
(max_num | (f2i_max & op_f2i) ) ? 23'h7fffff :
fract_out_rnd;
assign exp_out_final = ((op_div & exp_ovf[1] & !exp_ovf[0]) | output_zero ) ? 8'h00 :
((op_div & exp_ovf[1] & exp_ovf[0] & rmode_00) | inf_out | (f2i_max & op_f2i) ) ? 8'hff :
max_num ? 8'hfe :
exp_out_rnd;
// ---------------------------------------------------------------------
// Pack Result
assign out = {exp_out_final, fract_out_final};
// ---------------------------------------------------------------------
// Exceptions
wire underflow_fmul;
wire overflow_fdiv;
wire undeflow_div;
wire z = shft_co | ( exp_ovf[1] | exp_in_00) |
(!exp_ovf[1] & !exp_in_00 & (exp_out1_co | exp_out_00));
assign underflow_fmul = ( (|fract_trunc) & z & !exp_in_ff ) |
(fract_out_00 & !fract_in_00 & exp_ovf[1]);
assign undeflow_div = !(exp_ovf[1] & exp_ovf[0] & rmode_00) & !inf_out & !max_num & exp_out_final!=8'hff & (
((|fract_trunc) & !opb_dn & (
( op_dn & !exp_ovf[1] & exp_ovf[0]) |
( op_dn & exp_ovf[1]) |
( op_dn & div_shft1_co) |
exp_out_00 |
exp_ovf[1]
)
) |
( exp_ovf[1] & !exp_ovf[0] & (
( op_dn & exp_in>8'h16 & fi_ldz<23) |
( op_dn & exp_in<23 & fi_ldz<23 & !rem_00) |
( !op_dn & (exp_in[7]==exp_div[7]) & !rem_00) |
( !op_dn & exp_in_00 & (exp_div[7:1]==7'h7f) ) |
( !op_dn & exp_in<8'h7f & exp_in>8'h20 )
)
) |
(!exp_ovf[1] & !exp_ovf[0] & (
( op_dn & fi_ldz<23 & exp_out_00) |
( exp_in_00 & !rem_00) |
( !op_dn & ldz_all<23 & exp_in==1 & exp_out_00 & !rem_00)
)
)
);
assign underflow = op_div ? undeflow_div : op_mul ? underflow_fmul : (!fract_in[47] & exp_out1_co) & !dn;
assign overflow_fdiv = inf_out |
(!rmode_00 & max_num) |
(exp_in[7] & op_dn & exp_out_ff) |
(exp_ovf[0] & (exp_ovf[1] | exp_out_ff) );
assign overflow = op_div ? overflow_fdiv : (ovf0 | ovf1);
wire f2i_ine;
assign f2i_ine = (f2i_zero & !fract_in_00 & !opas) |
(|fract_trunc) |
(f2i_zero & (exp_in<8'h80) & opas & !fract_in_00) |
(f2i_max & rmode_11 & (exp_in<8'h80));
assign ine = op_f2i ? f2i_ine :
op_i2f ? (|fract_trunc) :
((r & !dn) | (s & !dn) | max_num | (op_div & !rem_00));
// ---------------------------------------------------------------------
// Debugging Stuff
// synopsys translate_off
wire [26:0] fracta_del, fractb_del;
wire [2:0] grs_del;
wire dn_del;
wire [7:0] exp_in_del;
wire [7:0] exp_out_del;
wire [22:0] fract_out_del;
wire [47:0] fract_in_del;
wire overflow_del;
wire [1:0] exp_ovf_del;
wire [22:0] fract_out_x_del, fract_out_rnd2a_del;
wire [24:0] trunc_xx_del;
wire exp_rnd_adj2a_del;
wire [22:0] fract_dn_del;
wire [4:0] div_opa_ldz_del;
wire [23:0] fracta_div_del;
wire [23:0] fractb_div_del;
wire div_inf_del;
wire [7:0] fi_ldz_2_del;
wire inf_out_del, max_out_del;
wire [5:0] fi_ldz_del;
wire rx_del;
wire ez_del;
wire lr;
wire [7:0] shr, shl, exp_div_del;
delay2 #26 ud000(clk, test.u0.fracta, fracta_del);
delay2 #26 ud001(clk, test.u0.fractb, fractb_del);
delay1 #2 ud002(clk, {g,r,s}, grs_del);
delay1 #0 ud004(clk, dn, dn_del);
delay1 #7 ud005(clk, exp_in, exp_in_del);
delay1 #7 ud007(clk, exp_out_rnd, exp_out_del);
delay1 #47 ud009(clk, fract_in, fract_in_del);
delay1 #0 ud010(clk, overflow, overflow_del);
delay1 #1 ud011(clk, exp_ovf, exp_ovf_del);
delay1 #22 ud014(clk, fract_out, fract_out_x_del);
delay1 #24 ud015(clk, fract_trunc, trunc_xx_del);
delay1 #0 ud017(clk, exp_rnd_adj2a, exp_rnd_adj2a_del);
delay1 #4 ud019(clk, div_opa_ldz, div_opa_ldz_del);
delay3 #23 ud020(clk, test.u0.fdiv_opa[49:26], fracta_div_del);
delay3 #23 ud021(clk, test.u0.fractb_mul, fractb_div_del);
delay1 #0 ud023(clk, div_inf, div_inf_del);
delay1 #7 ud024(clk, fi_ldz_2, fi_ldz_2_del);
delay1 #0 ud025(clk, inf_out, inf_out_del);
delay1 #0 ud026(clk, max_num, max_num_del);
delay1 #5 ud027(clk, fi_ldz, fi_ldz_del);
delay1 #0 ud028(clk, rem_00, rx_del);
delay1 #0 ud029(clk, left_right, lr);
delay1 #7 ud030(clk, shift_right, shr);
delay1 #7 ud031(clk, shift_left, shl);
delay1 #22 ud032(clk, fract_out_rnd2a, fract_out_rnd2a_del);
delay1 #7 ud033(clk, exp_div, exp_div_del);
always @(test.error_event)
begin
$display("\n----------------------------------------------");
$display("ERROR: GRS: %b exp_ovf: %b dn: %h exp_in: %h exp_out: %h, exp_rnd_adj2a: %b",
grs_del, exp_ovf_del, dn_del, exp_in_del, exp_out_del, exp_rnd_adj2a_del);
$display(" div_opa: %b, div_opb: %b, rem_00: %b, exp_div: %h",
fracta_div_del, fractb_div_del, rx_del, exp_div_del);
$display(" lr: %b, shl: %h, shr: %h",
lr, shl, shr);
$display(" overflow: %b, fract_in=%b fa:%h fb:%h",
overflow_del, fract_in_del, fracta_del, fractb_del);
$display(" div_opa_ldz: %h, div_inf: %b, inf_out: %b, max_num: %b, fi_ldz: %h, fi_ldz_2: %h",
div_opa_ldz_del, div_inf_del, inf_out_del, max_num_del, fi_ldz_del, fi_ldz_2_del);
$display(" fract_out_x: %b, fract_out_rnd2a_del: %h, fract_trunc: %b\n",
fract_out_x_del, fract_out_rnd2a_del, trunc_xx_del);
end
// synopsys translate_on
endmodule
// synopsys translate_off
module delay1(clk, in, out);
parameter N = 1;
input [N:0] in;
output [N:0] out;
input clk;
reg [N:0] out;
always @(posedge clk)
out <= #1 in;
endmodule
module delay2(clk, in, out);
parameter N = 1;
input [N:0] in;
output [N:0] out;
input clk;
reg [N:0] out, r1;
always @(posedge clk)
r1 <= #1 in;
always @(posedge clk)
out <= #1 r1;
endmodule
module delay3(clk, in, out);
parameter N = 1;
input [N:0] in;
output [N:0] out;
input clk;
reg [N:0] out, r1, r2;
always @(posedge clk)
r1 <= #1 in;
always @(posedge clk)
r2 <= #1 r1;
always @(posedge clk)
out <= #1 r2;
endmodule
// synopsys translate_on |
/////////////////////////////////////////////////////////////////////
//// ////
//// Pre Normalize ////
//// Pre Normalization Unit for Add/Sub Operations ////
//// ////
//// Author: Rudolf Usselmann ////
//// [email protected] ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Rudolf Usselmann ////
//// [email protected] ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
`timescale 1ns / 100ps
module pre_norm(clk, rmode, add, opa, opb, opa_nan, opb_nan, fracta_out,
fractb_out, exp_dn_out, sign, nan_sign, result_zero_sign,
fasu_op);
input clk;
input [1:0] rmode;
input add;
input [31:0] opa, opb;
input opa_nan, opb_nan;
output [26:0] fracta_out, fractb_out;
output [7:0] exp_dn_out;
output sign;
output nan_sign, result_zero_sign;
output fasu_op; // Operation Output
////////////////////////////////////////////////////////////////////////
//
// Local Wires and registers
//
wire signa, signb; // alias to opX sign
wire [7:0] expa, expb; // alias to opX exponent
wire [22:0] fracta, fractb; // alias to opX fraction
wire expa_lt_expb; // expa is larger than expb indicator
wire fractb_lt_fracta; // fractb is larger than fracta indicator
reg [7:0] exp_dn_out; // de normalized exponent output
wire [7:0] exp_small, exp_large;
wire [7:0] exp_diff; // Numeric difference of the two exponents
wire [22:0] adj_op; // Fraction adjustment: input
wire [26:0] adj_op_tmp;
wire [26:0] adj_op_out; // Fraction adjustment: output
wire [26:0] fracta_n, fractb_n; // Fraction selection after normalizing
wire [26:0] fracta_s, fractb_s; // Fraction Sorting out
reg [26:0] fracta_out, fractb_out; // Fraction Output
reg sign, sign_d; // Sign Output
reg add_d; // operation (add/sub)
reg fasu_op; // operation (add/sub) register
wire expa_dn, expb_dn;
reg sticky;
reg result_zero_sign;
reg add_r, signa_r, signb_r;
wire [4:0] exp_diff_sft;
wire exp_lt_27;
wire op_dn;
wire [26:0] adj_op_out_sft;
reg fracta_lt_fractb, fracta_eq_fractb;
wire nan_sign1;
reg nan_sign;
////////////////////////////////////////////////////////////////////////
//
// Aliases
//
assign signa = opa[31];
assign signb = opb[31];
assign expa = opa[30:23];
assign expb = opb[30:23];
assign fracta = opa[22:0];
assign fractb = opb[22:0];
////////////////////////////////////////////////////////////////////////
//
// Pre-Normalize exponents (and fractions)
//
assign expa_lt_expb = expa > expb; // expa is larger than expb
// ---------------------------------------------------------------------
// Normalize
assign expa_dn = !(|expa); // opa denormalized
assign expb_dn = !(|expb); // opb denormalized
// ---------------------------------------------------------------------
// Calculate the difference between the smaller and larger exponent
wire [7:0] exp_diff1, exp_diff1a, exp_diff2;
assign exp_small = expa_lt_expb ? expb : expa;
assign exp_large = expa_lt_expb ? expa : expb;
assign exp_diff1 = exp_large - exp_small;
assign exp_diff1a = exp_diff1-1;
assign exp_diff2 = (expa_dn | expb_dn) ? exp_diff1a : exp_diff1;
assign exp_diff = (expa_dn & expb_dn) ? 8'h0 : exp_diff2;
always @(posedge clk) // If numbers are equal we should return zero
exp_dn_out <= #1 (!add_d & expa==expb & fracta==fractb) ? 8'h0 : exp_large;
// ---------------------------------------------------------------------
// Adjust the smaller fraction
assign op_dn = expa_lt_expb ? expb_dn : expa_dn;
assign adj_op = expa_lt_expb ? fractb : fracta;
assign adj_op_tmp = { ~op_dn, adj_op, 3'b0 }; // recover hidden bit (op_dn)
// adj_op_out is 27 bits wide, so can only be shifted 27 bits to the right
assign exp_lt_27 = exp_diff > 8'd27;
assign exp_diff_sft = exp_lt_27 ? 5'd27 : exp_diff[4:0];
assign adj_op_out_sft = adj_op_tmp >> exp_diff_sft;
assign adj_op_out = {adj_op_out_sft[26:1], adj_op_out_sft[0] | sticky };
// ---------------------------------------------------------------------
// Get truncated portion (sticky bit)
always @(exp_diff_sft or adj_op_tmp)
case(exp_diff_sft) // synopsys full_case parallel_case
00: sticky = 1'h0;
01: sticky = adj_op_tmp[0];
02: sticky = |adj_op_tmp[01:0];
03: sticky = |adj_op_tmp[02:0];
04: sticky = |adj_op_tmp[03:0];
05: sticky = |adj_op_tmp[04:0];
06: sticky = |adj_op_tmp[05:0];
07: sticky = |adj_op_tmp[06:0];
08: sticky = |adj_op_tmp[07:0];
09: sticky = |adj_op_tmp[08:0];
10: sticky = |adj_op_tmp[09:0];
11: sticky = |adj_op_tmp[10:0];
12: sticky = |adj_op_tmp[11:0];
13: sticky = |adj_op_tmp[12:0];
14: sticky = |adj_op_tmp[13:0];
15: sticky = |adj_op_tmp[14:0];
16: sticky = |adj_op_tmp[15:0];
17: sticky = |adj_op_tmp[16:0];
18: sticky = |adj_op_tmp[17:0];
19: sticky = |adj_op_tmp[18:0];
20: sticky = |adj_op_tmp[19:0];
21: sticky = |adj_op_tmp[20:0];
22: sticky = |adj_op_tmp[21:0];
23: sticky = |adj_op_tmp[22:0];
24: sticky = |adj_op_tmp[23:0];
25: sticky = |adj_op_tmp[24:0];
26: sticky = |adj_op_tmp[25:0];
27: sticky = |adj_op_tmp[26:0];
endcase
// ---------------------------------------------------------------------
// Select operands for add/sub (recover hidden bit)
assign fracta_n = expa_lt_expb ? {~expa_dn, fracta, 3'b0} : adj_op_out;
assign fractb_n = expa_lt_expb ? adj_op_out : {~expb_dn, fractb, 3'b0};
// ---------------------------------------------------------------------
// Sort operands (for sub only)
assign fractb_lt_fracta = fractb_n > fracta_n; // fractb is larger than fracta
assign fracta_s = fractb_lt_fracta ? fractb_n : fracta_n;
assign fractb_s = fractb_lt_fracta ? fracta_n : fractb_n;
always @(posedge clk)
fracta_out <= #1 fracta_s;
always @(posedge clk)
fractb_out <= #1 fractb_s;
// ---------------------------------------------------------------------
// Determine sign for the output
// sign: 0=Positive Number; 1=Negative Number
always @(signa or signb or add or fractb_lt_fracta)
case({signa, signb, add}) // synopsys full_case parallel_case
// Add
3'b0_0_1: sign_d = 0;
3'b0_1_1: sign_d = fractb_lt_fracta;
3'b1_0_1: sign_d = !fractb_lt_fracta;
3'b1_1_1: sign_d = 1;
// Sub
3'b0_0_0: sign_d = fractb_lt_fracta;
3'b0_1_0: sign_d = 0;
3'b1_0_0: sign_d = 1;
3'b1_1_0: sign_d = !fractb_lt_fracta;
endcase
always @(posedge clk)
sign <= #1 sign_d;
// Fix sign for ZERO result
always @(posedge clk)
signa_r <= #1 signa;
always @(posedge clk)
signb_r <= #1 signb;
always @(posedge clk)
add_r <= #1 add;
always @(posedge clk)
result_zero_sign <= #1 ( add_r & signa_r & signb_r) |
(!add_r & signa_r & !signb_r) |
( add_r & (signa_r | signb_r) & (rmode==3)) |
(!add_r & (signa_r == signb_r) & (rmode==3));
// Fix sign for NAN result
always @(posedge clk)
fracta_lt_fractb <= #1 fracta < fractb;
always @(posedge clk)
fracta_eq_fractb <= #1 fracta == fractb;
assign nan_sign1 = fracta_eq_fractb ? (signa_r & signb_r) : fracta_lt_fractb ? signb_r : signa_r;
always @(posedge clk)
nan_sign <= #1 (opa_nan & opb_nan) ? nan_sign1 : opb_nan ? signb_r : signa_r;
////////////////////////////////////////////////////////////////////////
//
// Decode Add/Sub operation
//
// add: 1=Add; 0=Subtract
always @(signa or signb or add)
case({signa, signb, add}) // synopsys full_case parallel_case
// Add
3'b0_0_1: add_d = 1;
3'b0_1_1: add_d = 0;
3'b1_0_1: add_d = 0;
3'b1_1_1: add_d = 1;
// Sub
3'b0_0_0: add_d = 0;
3'b0_1_0: add_d = 1;
3'b1_0_0: add_d = 1;
3'b1_1_0: add_d = 0;
endcase
always @(posedge clk)
fasu_op <= #1 add_d;
endmodule
|
/////////////////////////////////////////////////////////////////////
//// ////
//// Pre Normalize ////
//// Floating Point Pre Normalization Unit for FMUL ////
//// ////
//// Author: Rudolf Usselmann ////
//// [email protected] ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Rudolf Usselmann ////
//// [email protected] ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
`timescale 1ns / 100ps
module pre_norm_fmul(clk, fpu_op, opa, opb, fracta, fractb, exp_out, sign,
sign_exe, inf, exp_ovf, underflow);
input clk;
input [2:0] fpu_op;
input [31:0] opa, opb;
output [23:0] fracta, fractb;
output [7:0] exp_out;
output sign, sign_exe;
output inf;
output [1:0] exp_ovf;
output [2:0] underflow;
////////////////////////////////////////////////////////////////////////
//
// Local Wires and registers
//
reg [7:0] exp_out;
wire signa, signb;
reg sign, sign_d;
reg sign_exe;
reg inf;
wire [1:0] exp_ovf_d;
reg [1:0] exp_ovf;
wire [7:0] expa, expb;
wire [7:0] exp_tmp1, exp_tmp2;
wire co1, co2;
wire expa_dn, expb_dn;
wire [7:0] exp_out_a;
wire opa_00, opb_00, fracta_00, fractb_00;
wire [7:0] exp_tmp3, exp_tmp4, exp_tmp5;
wire [2:0] underflow_d;
reg [2:0] underflow;
wire op_div = (fpu_op == 3'b011);
wire [7:0] exp_out_mul, exp_out_div;
////////////////////////////////////////////////////////////////////////
//
// Aliases
//
assign signa = opa[31];
assign signb = opb[31];
assign expa = opa[30:23];
assign expb = opb[30:23];
////////////////////////////////////////////////////////////////////////
//
// Calculate Exponenet
//
assign expa_dn = !(|expa);
assign expb_dn = !(|expb);
assign opa_00 = !(|opa[30:0]);
assign opb_00 = !(|opb[30:0]);
assign fracta_00 = !(|opa[22:0]);
assign fractb_00 = !(|opb[22:0]);
assign fracta = {!expa_dn,opa[22:0]}; // Recover hidden bit
assign fractb = {!expb_dn,opb[22:0]}; // Recover hidden bit
assign {co1,exp_tmp1} = op_div ? (expa - expb) : (expa + expb);
assign {co2,exp_tmp2} = op_div ? ({co1,exp_tmp1} + 8'h7f) : ({co1,exp_tmp1} - 8'h7f);
assign exp_tmp3 = exp_tmp2 + 1;
assign exp_tmp4 = 8'h7f - exp_tmp1;
assign exp_tmp5 = op_div ? (exp_tmp4+1) : (exp_tmp4-1);
always@(posedge clk)
exp_out <= #1 op_div ? exp_out_div : exp_out_mul;
assign exp_out_div = (expa_dn | expb_dn) ? (co2 ? exp_tmp5 : exp_tmp3 ) : co2 ? exp_tmp4 : exp_tmp2;
assign exp_out_mul = exp_ovf_d[1] ? exp_out_a : (expa_dn | expb_dn) ? exp_tmp3 : exp_tmp2;
assign exp_out_a = (expa_dn | expb_dn) ? exp_tmp5 : exp_tmp4;
assign exp_ovf_d[0] = op_div ? (expa[7] & !expb[7]) : (co2 & expa[7] & expb[7]);
assign exp_ovf_d[1] = op_div ? co2 : ((!expa[7] & !expb[7] & exp_tmp2[7]) | co2);
always @(posedge clk)
exp_ovf <= #1 exp_ovf_d;
assign underflow_d[0] = (exp_tmp1 < 8'h7f) & !co1 & !(opa_00 | opb_00 | expa_dn | expb_dn);
assign underflow_d[1] = ((expa[7] | expb[7]) & !opa_00 & !opb_00) |
(expa_dn & !fracta_00) | (expb_dn & !fractb_00);
assign underflow_d[2] = !opa_00 & !opb_00 & (exp_tmp1 == 8'h7f);
always @(posedge clk)
underflow <= #1 underflow_d;
always @(posedge clk)
inf <= #1 op_div ? (expb_dn & !expa[7]) : ({co1,exp_tmp1} > 9'h17e) ;
////////////////////////////////////////////////////////////////////////
//
// Determine sign for the output
//
// sign: 0=Posetive Number; 1=Negative Number
always @(signa or signb)
case({signa, signb}) // synopsys full_case parallel_case
2'b0_0: sign_d = 0;
2'b0_1: sign_d = 1;
2'b1_0: sign_d = 1;
2'b1_1: sign_d = 0;
endcase
always @(posedge clk)
sign <= #1 sign_d;
always @(posedge clk)
sign_exe <= #1 signa & signb;
endmodule |
/////////////////////////////////////////////////////////////////////
//// ////
//// Primitives ////
//// FPU Primitives ////
//// ////
//// Author: Rudolf Usselmann ////
//// [email protected] ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Rudolf Usselmann ////
//// [email protected] ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
`timescale 1ns / 100ps
////////////////////////////////////////////////////////////////////////
//
// Add/Sub
//
module add_sub27(add, opa, opb, sum, co);
input add;
input [26:0] opa, opb;
output [26:0] sum;
output co;
assign {co, sum} = add ? (opa + opb) : (opa - opb);
endmodule
////////////////////////////////////////////////////////////////////////
//
// Multiply
//
module mul_r2(clk, opa, opb, prod);
input clk;
input [23:0] opa, opb;
output [47:0] prod;
reg [47:0] prod1, prod;
always @(posedge clk)
prod1 <= #1 opa * opb;
always @(posedge clk)
prod <= #1 prod1;
endmodule
////////////////////////////////////////////////////////////////////////
//
// Divide
//
module div_r2(clk, opa, opb, quo, rem);
input clk;
input [49:0] opa;
input [23:0] opb;
output [49:0] quo, rem;
reg [49:0] quo, rem, quo1, remainder;
always @(posedge clk)
quo1 <= #1 opa / opb;
always @(posedge clk)
quo <= #1 quo1;
always @(posedge clk)
remainder <= #1 opa % opb;
always @(posedge clk)
rem <= #1 remainder;
endmodule
|
// ==============================================================
// File generated by AutoESL - High-Level Synthesis System (C, C++, SystemC)
// Version: 2011.1
// Copyright (C) 2011 Xilinx Inc. All rights reserved.
//
// ==============================================================
/*-----------------------------------------------------------------------
-- AESL_FPSim_pkg.v:
-- Floating point simulation model for verilog.
--
-----------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Single precision units.
-- FAdd, FSub, FAddSub, FMul, FDiv, FSqrt
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Double precision units.
-- DAdd, DSub, DAddSub, DMul, DDiv, DSqrt
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Single precision units.
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Single precision Add.
-------------------------------------------------------------------------------
*/
module ACMP_fadd_comb(din0, din1, dout);
parameter ID = 0;
parameter NUM_STAGE = 13;
parameter din0_WIDTH = 32;
parameter din1_WIDTH = 32;
parameter dout_WIDTH = 32;
input[din0_WIDTH-1:0] din0;
input[din1_WIDTH-1:0] din1;
output[dout_WIDTH-1:0] dout;
AESL_WP_FAdd #(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH)
ACMP_FAdd_U (
.clk(1'b1),
.reset(1'b1),
.ce(1'b1),
.din0(din0),
.din1(din1),
.dout(dout));
endmodule
module ACMP_fadd(clk, reset, ce, din0, din1, dout);
parameter ID = 0;
parameter NUM_STAGE = 13;
parameter din0_WIDTH = 32;
parameter din1_WIDTH = 32;
parameter dout_WIDTH = 32;
input clk, reset, ce;
input[din0_WIDTH-1:0] din0;
input[din1_WIDTH-1:0] din1;
output[dout_WIDTH-1:0] dout;
AESL_WP_FAdd #(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH)
ACMP_FAdd_U (
.clk(clk),
.reset(reset),
.ce(ce),
.din0(din0),
.din1(din1),
.dout(dout));
endmodule
/*
-------------------------------------------------------------------------------
-- Single precision Sub.
-------------------------------------------------------------------------------
*/
module ACMP_fsub_comb (din0, din1, dout);
parameter ID = 0;
parameter NUM_STAGE = 13;
parameter din0_WIDTH = 32;
parameter din1_WIDTH = 32;
parameter dout_WIDTH = 32;
input[din0_WIDTH-1:0] din0;
input[din1_WIDTH-1:0] din1;
output[dout_WIDTH-1:0] dout;
AESL_WP_FSub #(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH)
ACMP_FSub_U(
.clk(1'b1),
.reset(1'b1),
.ce(1'b1),
.din0(din0),
.din1(din1),
.dout(dout));
endmodule
module ACMP_fsub(clk, reset, ce, din0, din1, dout);
parameter ID = 0;
parameter NUM_STAGE = 13;
parameter din0_WIDTH = 32;
parameter din1_WIDTH = 32;
parameter dout_WIDTH = 32;
input clk, reset, ce;
input[din0_WIDTH-1:0] din0;
input[din1_WIDTH-1:0] din1;
output[dout_WIDTH-1:0] dout;
AESL_WP_FSub #(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH)
ACMP_FSub_U(
.clk(clk),
.reset(reset),
.ce(ce),
.din0(din0),
.din1(din1),
.dout(dout));
endmodule
/*
-------------------------------------------------------------------------------
-- Single precision AddSub.
-------------------------------------------------------------------------------
*/
module ACMP_faddfsub_comb(opcode, din0, din1, dout);
parameter ID = 0;
parameter NUM_STAGE = 13;
parameter din0_WIDTH = 32;
parameter din1_WIDTH = 32;
parameter dout_WIDTH = 32;
input[1:0] opcode;
input[din0_WIDTH-1:0] din0;
input[din1_WIDTH-1:0] din1;
output[dout_WIDTH-1:0] dout;
AESL_WP_FAddFSub
#(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH)
ACMP_FAddFSub_U(
.clk(1'b1),
.reset(1'b1),
.ce(1'b1),
.opcode(opcode),
.din0(din0),
.din1(din1),
.dout(dout));
endmodule
module ACMP_faddfsub(clk, reset, ce, opcode, din0, din1, dout);
parameter ID = 0;
parameter NUM_STAGE = 13;
parameter din0_WIDTH = 32;
parameter din1_WIDTH = 32;
parameter dout_WIDTH = 32;
input clk, reset, ce;
input[1:0] opcode;
input[din0_WIDTH-1:0] din0;
input[din1_WIDTH-1:0] din1;
output[dout_WIDTH-1:0] dout;
AESL_WP_FAddFSub
#(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH)
ACMP_FAddFSub_U(
.clk(clk),
.reset(reset),
.ce(ce),
.opcode(opcode),
.din0(din0),
.din1(din1),
.dout(dout));
endmodule
module ACMP_fmul_comb(din0, din1, dout);
parameter ID = 0;
parameter NUM_STAGE = 13;
parameter din0_WIDTH = 32;
parameter din1_WIDTH = 32;
parameter dout_WIDTH = 32;
input[din0_WIDTH-1:0] din0;
input[din1_WIDTH-1:0] din1;
output[dout_WIDTH-1:0] dout;
AESL_WP_FMul
#(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH)
ACMP_FMul_U(
.clk(1'b1),
.reset(1'b1),
.ce(1'b1),
.din0(din0),
.din1(din1),
.dout(dout));
endmodule
module ACMP_fmul(clk, reset, ce, din0, din1, dout);
parameter ID = 0;
parameter NUM_STAGE = 13;
parameter din0_WIDTH = 32;
parameter din1_WIDTH = 32;
parameter dout_WIDTH = 32;
input clk, reset, ce;
input[din0_WIDTH-1:0] din0;
input[din1_WIDTH-1:0] din1;
output[dout_WIDTH-1:0] dout;
AESL_WP_FMul
#(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH)
ACMP_FMul_U(
.clk(clk),
.reset(reset),
.ce(ce),
.din0(din0),
.din1(din1),
.dout(dout));
endmodule
module ACMP_fdiv_comb(din0, din1, dout);
parameter ID = 0;
parameter NUM_STAGE = 13;
parameter din0_WIDTH = 32;
parameter din1_WIDTH = 32;
parameter dout_WIDTH = 32;
input[din0_WIDTH-1:0] din0;
input[din1_WIDTH-1:0] din1;
output[dout_WIDTH-1:0] dout;
AESL_WP_FDiv
#(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH)
ACMP_FDiv_U(
.clk(1'b1),
.reset(1'b1),
.ce(1'b1),
.din0(din0),
.din1(din1),
.dout(dout));
endmodule
module ACMP_fdiv(clk, reset, ce, din0, din1, dout);
parameter ID = 0;
parameter NUM_STAGE = 13;
parameter din0_WIDTH = 32;
parameter din1_WIDTH = 32;
parameter dout_WIDTH = 32;
input clk, reset, ce;
input[din0_WIDTH-1:0] din0;
input[din1_WIDTH-1:0] din1;
output[dout_WIDTH-1:0] dout;
AESL_WP_FDiv
#(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH)
ACMP_FDiv_U(
.clk(clk),
.reset(reset),
.ce(ce),
.din0(din0),
.din1(din1),
.dout(dout));
endmodule
module ACMP_fsqrt_comb (din0, din1, dout);
parameter ID = 0;
parameter NUM_STAGE = 13;
parameter din0_WIDTH = 32;
parameter din1_WIDTH = 32;
parameter dout_WIDTH = 32;
input[din0_WIDTH-1:0] din0;
input[din1_WIDTH-1:0] din1;
output[dout_WIDTH-1:0] dout;
AESL_WP_FSqrt
#(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH)
ACMP_FSqrt_U(
.clk(1'b1),
.reset(1'b1),
.ce(1'b1),
.din0(din0),
.din1(din1),
.dout(dout));
endmodule
module ACMP_fsqrt(clk, reset, ce, din0, din1, dout);
parameter ID = 0;
parameter NUM_STAGE = 13;
parameter din0_WIDTH = 32;
parameter din1_WIDTH = 32;
parameter dout_WIDTH = 32;
input clk, reset, ce;
input[din0_WIDTH-1:0] din0;
input[din1_WIDTH-1:0] din1;
output[dout_WIDTH-1:0] dout;
AESL_WP_FSqrt
#(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH)
ACMP_FSqrt_U(
.clk(clk),
.reset(reset),
.ce(ce),
.din0(din0),
.din1(din1),
.dout(dout));
endmodule
/*
-------------------------------------------------------------------------------
-- Double precision
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Double precision ADD
-------------------------------------------------------------------------------
*/
module ACMP_dadd_comb(din0, din1, dout);
parameter ID = 0;
parameter NUM_STAGE = 13;
parameter din0_WIDTH = 64;
parameter din1_WIDTH = 64;
parameter dout_WIDTH = 64;
input[din0_WIDTH-1:0] din0;
input[din1_WIDTH-1:0] din1;
output[dout_WIDTH-1:0] dout;
AESL_WP_DAdd
#(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH)
ACMP_DAdd_U(
.clk(1'b1),
.reset(1'b1),
.ce(1'b1),
.din0(din0),
.din1(din1),
.dout(dout));
endmodule
module ACMP_dadd(clk, reset, ce, din0, din1, dout);
parameter ID = 0;
parameter NUM_STAGE = 13;
parameter din0_WIDTH = 64;
parameter din1_WIDTH = 64;
parameter dout_WIDTH = 64;
input clk, reset, ce;
input[din0_WIDTH-1:0] din0;
input[din1_WIDTH-1:0] din1;
output[dout_WIDTH-1:0] dout;
AESL_WP_DAdd
#(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH)
ACMP_DAdd_U(
.clk(clk),
.reset(reset),
.ce(ce),
.din0(din0),
.din1(din1),
.dout(dout));
endmodule
/*
-------------------------------------------------------------------------------
-- Double precision Sub
-------------------------------------------------------------------------------
*/
module ACMP_dsub_comb(din0, din1, dout);
parameter ID = 0;
parameter NUM_STAGE = 13;
parameter din0_WIDTH = 64;
parameter din1_WIDTH = 64;
parameter dout_WIDTH = 64;
input[din0_WIDTH-1:0] din0;
input[din1_WIDTH-1:0] din1;
output[dout_WIDTH-1:0] dout;
AESL_WP_DSub
#(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH)
ACMP_DSub_U(
.clk(1'b1),
.reset(1'b1),
.ce(1'b1),
.din0(din0),
.din1(din1),
.dout(dout));
endmodule
module ACMP_dsub(clk, reset, ce, din0, din1, dout);
parameter ID = 0;
parameter NUM_STAGE = 13;
parameter din0_WIDTH = 64;
parameter din1_WIDTH = 64;
parameter dout_WIDTH = 64;
input clk, reset, ce;
input[din0_WIDTH-1:0] din0;
input[din1_WIDTH-1:0] din1;
output[dout_WIDTH-1:0] dout;
AESL_WP_DSub
#(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH)
ACMP_DSub_U(
.clk(clk),
.reset(reset),
.ce(ce),
.din0(din0),
.din1(din1),
.dout(dout));
endmodule
/*
-------------------------------------------------------------------------------
-- Double precision AddSub
-------------------------------------------------------------------------------
*/
module ACMP_dadddsub_comb(opcode, din0, din1, dout);
parameter ID = 0;
parameter NUM_STAGE = 13;
parameter din0_WIDTH = 64;
parameter din1_WIDTH = 64;
parameter dout_WIDTH = 64;
input[1:0] opcode;
input[din0_WIDTH-1:0] din0;
input[din1_WIDTH-1:0] din1;
output[dout_WIDTH-1:0] dout;
AESL_WP_DAddDSub
#(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH)
ACMP_DAddDSub_U(
.clk(1'b1),
.reset(1'b1),
.ce(1'b1),
.opcode(opcode),
.din0(din0),
.din1(din1),
.dout(dout));
endmodule
module ACMP_dadddsub(clk, reset, ce, opcode, din0, din1, dout);
parameter ID = 0;
parameter NUM_STAGE = 13;
parameter din0_WIDTH = 64;
parameter din1_WIDTH = 64;
parameter dout_WIDTH = 64;
input clk, reset, ce;
input[1:0] opcode;
input[din0_WIDTH-1:0] din0;
input[din1_WIDTH-1:0] din1;
output[dout_WIDTH-1:0] dout;
AESL_WP_DAddDSub
#(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH)
ACMP_DAddDSub_U(
.clk(clk),
.reset(reset),
.ce(ce),
.opcode(opcode),
.din0(din0),
.din1(din1),
.dout(dout));
endmodule
module ACMP_dmul_comb(din0, din1, dout);
parameter ID = 0;
parameter NUM_STAGE = 13;
parameter din0_WIDTH = 64;
parameter din1_WIDTH = 64;
parameter dout_WIDTH = 64;
input[din0_WIDTH-1:0] din0;
input[din1_WIDTH-1:0] din1;
output[dout_WIDTH-1:0] dout;
AESL_WP_DMul
#(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH)
ACMP_DMul_U(
.clk(1'b1),
.reset(1'b1),
.ce(1'b1),
.din0(din0),
.din1(din1),
.dout(dout));
endmodule
module ACMP_dmul(clk, reset, ce, din0, din1, dout);
parameter ID = 0;
parameter NUM_STAGE = 13;
parameter din0_WIDTH = 64;
parameter din1_WIDTH = 64;
parameter dout_WIDTH = 64;
input clk, reset, ce;
input[din0_WIDTH-1:0] din0;
input[din1_WIDTH-1:0] din1;
output[dout_WIDTH-1:0] dout;
AESL_WP_DMul
#(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH)
ACMP_DMul_U(
.clk(clk),
.reset(reset),
.ce(ce),
.din0(din0),
.din1(din1),
.dout(dout));
endmodule
module ACMP_ddiv_comb(din0, din1, dout);
parameter ID = 0;
parameter NUM_STAGE = 13;
parameter din0_WIDTH = 64;
parameter din1_WIDTH = 64;
parameter dout_WIDTH = 64;
input[din0_WIDTH-1:0] din0;
input[din1_WIDTH-1:0] din1;
output[dout_WIDTH-1:0] dout;
AESL_WP_DDiv
#(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH)
ACMP_DDiv_U(
.clk(1'b1),
.reset(1'b1),
.ce(1'b1),
.din0(din0),
.din1(din1),
.dout(dout));
endmodule
module ACMP_ddiv(clk, reset, ce, din0, din1, dout);
parameter ID = 0;
parameter NUM_STAGE = 13;
parameter din0_WIDTH = 64;
parameter din1_WIDTH = 64;
parameter dout_WIDTH = 64;
input clk, reset, ce;
input[din0_WIDTH-1:0] din0;
input[din1_WIDTH-1:0] din1;
output[dout_WIDTH-1:0] dout;
AESL_WP_DDiv
#(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH)
ACMP_DDiv_U(
.clk(clk),
.reset(reset),
.ce(ce),
.din0(din0),
.din1(din1),
.dout(dout));
endmodule
module ACMP_dsqrt_comb(din0, din1, dout);
parameter ID = 0;
parameter NUM_STAGE = 13;
parameter din0_WIDTH = 64;
parameter din1_WIDTH = 64;
parameter dout_WIDTH = 64;
input[din0_WIDTH-1:0] din0;
input[din1_WIDTH-1:0] din1;
output[dout_WIDTH-1:0] dout;
AESL_WP_DSqrt
#(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH)
ACMP_DSqrt_U(
.clk(1'b1),
.reset(1'b1),
.ce(1'b1),
.din0(din0),
.din1(din1),
.dout(dout));
endmodule
module ACMP_dsqrt(clk, reset, ce, din0, din1, dout);
parameter ID = 0;
parameter NUM_STAGE = 13;
parameter din0_WIDTH = 64;
parameter din1_WIDTH = 64;
parameter dout_WIDTH = 64;
input clk, reset, ce;
input[din0_WIDTH-1:0] din0;
input[din1_WIDTH-1:0] din1;
output[dout_WIDTH-1:0] dout;
AESL_WP_DSqrt
#(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH)
ACMP_DSqrt_U(
.clk(clk),
.reset(reset),
.ce(ce),
.din0(din0),
.din1(din1),
.dout(dout));
endmodule
/*
-------------------------------------------------------------------------------
-- Single precision Cmp (Comparator)
-------------------------------------------------------------------------------
-- Predicate values:
-- FCMP_FALSE = 0, ///< 0 0 0 0 Always false (always folded)
-- FCMP_OEQ = 1, ///< 0 0 0 1 True if ordered and equal
-- FCMP_OGT = 2, ///< 0 0 1 0 True if ordered and greater than
-- FCMP_OGE = 3, ///< 0 0 1 1 True if ordered and greater than or equal
-- FCMP_OLT = 4, ///< 0 1 0 0 True if ordered and less than
-- FCMP_OLE = 5, ///< 0 1 0 1 True if ordered and less than or equal
-- FCMP_ONE = 6, ///< 0 1 1 0 True if ordered and operands are unequal
-- FCMP_ORD = 7, ///< 0 1 1 1 True if ordered (no nans)
-- FCMP_UNO = 8, ///< 1 0 0 0 True if unordered: isnan(X) | isnan(Y)
-- FCMP_UEQ = 9, ///< 1 0 0 1 True if unordered or equal
-- FCMP_UGT =10, ///< 1 0 1 0 True if unordered or greater than
-- FCMP_UGE =11, ///< 1 0 1 1 True if unordered, greater than, or equal
-- FCMP_ULT =12, ///< 1 1 0 0 True if unordered or less than
-- FCMP_ULE =13, ///< 1 1 0 1 True if unordered, less than, or equal
-- FCMP_UNE =14, ///< 1 1 1 0 True if unordered or not equal
-- FCMP_TRUE =15, ///< 1 1 1 1 Always true (always folded)
*/
module ACMP_fcmp_comb(opcode, din0, din1, dout);
parameter ID = 0;
parameter NUM_STAGE = 12;
parameter din0_WIDTH = 32;
parameter din1_WIDTH = 32;
parameter dout_WIDTH = 1;
input[4:0] opcode;
input[din0_WIDTH-1:0] din0;
input[din1_WIDTH-1:0] din1;
output[0:0] dout;
AESL_WP_FCmp
#(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH)
ACMP_FCmp_U(
.clk(1'b1),
.reset(1'b1),
.ce(1'b1),
.opcode(opcode),
.din0(din0),
.din1(din1),
.dout(dout));
endmodule
module ACMP_fcmp(clk, reset, ce, opcode, din0, din1, dout);
parameter ID = 0;
parameter NUM_STAGE = 12;
parameter din0_WIDTH = 32;
parameter din1_WIDTH = 32;
parameter dout_WIDTH = 1;
input clk;
input reset, ce;
input[4:0] opcode;
input[din0_WIDTH-1:0] din0;
input[din1_WIDTH-1:0] din1;
output[0:0] dout;
AESL_WP_FCmp
#(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH)
ACMP_FCmp_U(
.clk(clk),
.reset(reset),
.ce(ce),
.opcode(opcode),
.din0(din0),
.din1(din1),
.dout(dout));
endmodule
/*
-------------------------------------------------------------------------------
-- Double precision Cmp (Comparator)
-------------------------------------------------------------------------------
-- Predicate values:
-- FCMP_FALSE = 0, ///< 0 0 0 0 Always false (always folded)
-- FCMP_OEQ = 1, ///< 0 0 0 1 True if ordered and equal
-- FCMP_OGT = 2, ///< 0 0 1 0 True if ordered and greater than
-- FCMP_OGE = 3, ///< 0 0 1 1 True if ordered and greater than or equal
-- FCMP_OLT = 4, ///< 0 1 0 0 True if ordered and less than
-- FCMP_OLE = 5, ///< 0 1 0 1 True if ordered and less than or equal
-- FCMP_ONE = 6, ///< 0 1 1 0 True if ordered and operands are unequal
-- FCMP_ORD = 7, ///< 0 1 1 1 True if ordered (no nans)
-- FCMP_UNO = 8, ///< 1 0 0 0 True if unordered: isnan(X) | isnan(Y)
-- FCMP_UEQ = 9, ///< 1 0 0 1 True if unordered or equal
-- FCMP_UGT =10, ///< 1 0 1 0 True if unordered or greater than
-- FCMP_UGE =11, ///< 1 0 1 1 True if unordered, greater than, or equal
-- FCMP_ULT =12, ///< 1 1 0 0 True if unordered or less than
-- FCMP_ULE =13, ///< 1 1 0 1 True if unordered, less than, or equal
-- FCMP_UNE =14, ///< 1 1 1 0 True if unordered or not equal
-- FCMP_TRUE =15, ///< 1 1 1 1 Always true (always folded)
*/
module ACMP_dcmp_comb(opcode, din0, din1, dout);
parameter ID = 0;
parameter NUM_STAGE = 12;
parameter din0_WIDTH = 64;
parameter din1_WIDTH = 64;
parameter dout_WIDTH = 1;
input[4:0] opcode;
input[din0_WIDTH-1:0] din0;
input[din1_WIDTH-1:0] din1;
output[0:0] dout;
AESL_WP_DCmp
#(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH)
ACMP_DCmp_U(
.clk(1'b1),
.reset(1'b1),
.ce(1'b1),
.opcode(opcode),
.din0(din0),
.din1(din1),
.dout(dout));
endmodule
module ACMP_dcmp(clk, reset, ce, opcode, din0, din1, dout);
parameter ID = 0;
parameter NUM_STAGE = 12;
parameter din0_WIDTH = 64;
parameter din1_WIDTH = 64;
parameter dout_WIDTH = 1;
input clk;
input reset, ce;
input[4:0] opcode;
input[din0_WIDTH-1:0] din0;
input[din1_WIDTH-1:0] din1;
output[0:0] dout;
AESL_WP_DCmp
#(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH)
ACMP_DCmp_U(
.clk(clk),
.reset(reset),
.ce(ce),
.opcode(opcode),
.din0(din0),
.din1(din1),
.dout(dout));
endmodule
/*
-------------------------------------------------------------------------------
-- Single precision to int32
-------------------------------------------------------------------------------
*/
module ACMP_fptosi_comb(din0, dout);
parameter ID = 0;
parameter NUM_STAGE = 12;
parameter din0_WIDTH = 32;
parameter dout_WIDTH = 32;
input[din0_WIDTH-1:0] din0;
output[dout_WIDTH-1:0] dout;
AESL_WP_SPToSI
#(NUM_STAGE, din0_WIDTH, dout_WIDTH)
ACMP_SPToSI_U(
.clk(1'b1),
.reset(1'b1),
.ce(1'b1),
.din0(din0),
.dout(dout));
endmodule
module ACMP_fptosi(clk, reset, ce, din0, dout);
parameter ID = 0;
parameter NUM_STAGE = 12;
parameter din0_WIDTH = 32;
parameter dout_WIDTH = 32;
input clk;
input reset, ce;
input[din0_WIDTH-1:0] din0;
output[dout_WIDTH-1:0] dout;
AESL_WP_SPToSI
#(NUM_STAGE, din0_WIDTH, dout_WIDTH)
ACMP_SPToSI_U(
.clk(clk),
.reset(reset),
.ce(ce),
.din0(din0),
.dout(dout));
endmodule
/*
-------------------------------------------------------------------------------
-- Double precision to int32
-------------------------------------------------------------------------------
*/
module ACMP_dptosi_comb(din0, dout);
parameter ID = 0;
parameter NUM_STAGE = 12;
parameter din0_WIDTH = 64;
parameter dout_WIDTH = 32;
input[din0_WIDTH-1:0] din0;
output[dout_WIDTH-1:0] dout;
AESL_WP_DPToSI
#(NUM_STAGE, din0_WIDTH, dout_WIDTH)
ACMP_DPToSI_U(
.clk(1'b1),
.reset(1'b1),
.ce(1'b1),
.din0(din0),
.dout(dout));
endmodule
module ACMP_dptosi(clk, reset, ce, din0, dout);
parameter ID = 0;
parameter NUM_STAGE = 12;
parameter din0_WIDTH = 64;
parameter dout_WIDTH = 32;
input clk;
input reset, ce;
input[din0_WIDTH-1:0] din0;
output[dout_WIDTH-1:0] dout;
AESL_WP_DPToSI
#(NUM_STAGE, din0_WIDTH, dout_WIDTH)
ACMP_DPToSI_U(
.clk(clk),
.reset(reset),
.ce(ce),
.din0(din0),
.dout(dout));
endmodule
/*
-------------------------------------------------------------------------------
-- Int32 to single precision
-------------------------------------------------------------------------------
*/
module ACMP_sitofp_comb(din0, dout);
parameter ID = 0;
parameter NUM_STAGE = 12;
parameter din0_WIDTH = 32;
parameter dout_WIDTH = 64;
input[din0_WIDTH-1:0] din0;
output[dout_WIDTH-1:0] dout;
AESL_WP_SIToSP
#(NUM_STAGE, din0_WIDTH, dout_WIDTH)
ACMP_SIToDP_U(
.clk(1'b1),
.reset(1'b1),
.ce(1'b1),
.din0(din0),
.dout(dout));
endmodule
module ACMP_sitofp(clk, reset, ce, din0, dout);
parameter ID = 0;
parameter NUM_STAGE = 12;
parameter din0_WIDTH = 32;
parameter dout_WIDTH = 64;
input clk;
input reset, ce;
input[din0_WIDTH-1:0] din0;
output[dout_WIDTH-1:0] dout;
AESL_WP_SIToSP
#(NUM_STAGE, din0_WIDTH, dout_WIDTH)
ACMP_SIToDP_U(
.clk(clk),
.reset(reset),
.ce(ce),
.din0(din0),
.dout(dout));
endmodule
/*
-------------------------------------------------------------------------------
-- Int32 to double precision
-------------------------------------------------------------------------------
*/
module ACMP_sitodp_comb(din0, dout);
parameter ID = 0;
parameter NUM_STAGE = 12;
parameter din0_WIDTH = 32;
parameter dout_WIDTH = 64;
input[din0_WIDTH-1:0] din0;
output[dout_WIDTH-1:0] dout;
AESL_WP_SIToDP
#(NUM_STAGE, din0_WIDTH, dout_WIDTH)
ACMP_SIToDP_U(
.clk(1'b1),
.reset(1'b1),
.ce(1'b1),
.din0(din0),
.dout(dout));
endmodule
module ACMP_sitodp(clk, reset, ce, din0, dout);
parameter ID = 0;
parameter NUM_STAGE = 12;
parameter din0_WIDTH = 32;
parameter dout_WIDTH = 64;
input clk;
input reset, ce;
input[din0_WIDTH-1:0] din0;
output[dout_WIDTH-1:0] dout;
AESL_WP_SIToDP
#(NUM_STAGE, din0_WIDTH, dout_WIDTH)
ACMP_SIToDP_U(
.clk(clk),
.reset(reset),
.ce(ce),
.din0(din0),
.dout(dout));
endmodule
/*
-------------------------------------------------------------------------------
-- Single precision to uint32
-------------------------------------------------------------------------------
*/
module ACMP_fptoui_comb(din0, dout);
parameter ID = 0;
parameter NUM_STAGE = 12;
parameter din0_WIDTH = 32;
parameter dout_WIDTH = 32;
input[din0_WIDTH-1:0] din0;
output[dout_WIDTH-1:0] dout;
AESL_WP_SPToUI
#(NUM_STAGE, din0_WIDTH, dout_WIDTH)
ACMP_SPToUI_U(
.clk(1'b1),
.reset(1'b1),
.ce(1'b1),
.din0(din0),
.dout(dout));
endmodule
module ACMP_fptoui(clk, reset, ce, din0, dout);
parameter ID = 0;
parameter NUM_STAGE = 12;
parameter din0_WIDTH = 32;
parameter dout_WIDTH = 32;
input clk;
input reset, ce;
input[din0_WIDTH-1:0] din0;
output[dout_WIDTH-1:0] dout;
AESL_WP_SPToUI
#(NUM_STAGE, din0_WIDTH, dout_WIDTH)
ACMP_SPToUI_U(
.clk(clk),
.reset(reset),
.ce(ce),
.din0(din0),
.dout(dout));
endmodule
/*
-------------------------------------------------------------------------------
-- Double precision to uint32
-------------------------------------------------------------------------------
*/
module ACMP_dptoui_comb(din0, dout);
parameter ID = 0;
parameter NUM_STAGE = 12;
parameter din0_WIDTH = 64;
parameter dout_WIDTH = 32;
input[din0_WIDTH-1:0] din0;
output[dout_WIDTH-1:0] dout;
AESL_WP_DPToUI
#(NUM_STAGE, din0_WIDTH, dout_WIDTH)
ACMP_DPToUI_U(
.clk(1'b1),
.reset(1'b1),
.ce(1'b1),
.din0(din0),
.dout(dout));
endmodule
module ACMP_dptoui(clk, reset, ce, din0, dout);
parameter ID = 0;
parameter NUM_STAGE = 12;
parameter din0_WIDTH = 64;
parameter dout_WIDTH = 32;
input clk;
input reset, ce;
input[din0_WIDTH-1:0] din0;
output[dout_WIDTH-1:0] dout;
AESL_WP_DPToUI
#(NUM_STAGE, din0_WIDTH, dout_WIDTH)
ACMP_DPToUI_U(
.clk(clk),
.reset(reset),
.ce(ce),
.din0(din0),
.dout(dout));
endmodule
/*
-------------------------------------------------------------------------------
-- uInt32 to single precision
-------------------------------------------------------------------------------
*/
module ACMP_uitofp_comb(din0, dout);
parameter ID = 0;
parameter NUM_STAGE = 12;
parameter din0_WIDTH = 32;
parameter dout_WIDTH = 64;
input[din0_WIDTH-1:0] din0;
output[dout_WIDTH-1:0] dout;
AESL_WP_UIToSP
#(NUM_STAGE, din0_WIDTH, dout_WIDTH)
ACMP_UIToSP_U(
.clk(1'b1),
.reset(1'b1),
.ce(1'b1),
.din0(din0),
.dout(dout));
endmodule
module ACMP_uitofp(clk, reset, ce, din0, dout);
parameter ID = 0;
parameter NUM_STAGE = 12;
parameter din0_WIDTH = 32;
parameter dout_WIDTH = 64;
input clk;
input reset, ce;
input[din0_WIDTH-1:0] din0;
output[dout_WIDTH-1:0] dout;
AESL_WP_UIToSP
#(NUM_STAGE, din0_WIDTH, dout_WIDTH)
ACMP_UIToSP_U(
.clk(clk),
.reset(reset),
.ce(ce),
.din0(din0),
.dout(dout));
endmodule
/*
-------------------------------------------------------------------------------
-- uInt32 to double precision
-------------------------------------------------------------------------------
*/
module ACMP_uitodp_comb(din0, dout);
parameter ID = 0;
parameter NUM_STAGE = 12;
parameter din0_WIDTH = 32;
parameter dout_WIDTH = 64;
input[din0_WIDTH-1:0] din0;
output[dout_WIDTH-1:0] dout;
AESL_WP_UIToDP
#(NUM_STAGE, din0_WIDTH, dout_WIDTH)
ACMP_UIToDP_U(
.clk(1'b1),
.reset(1'b1),
.ce(1'b1),
.din0(din0),
.dout(dout));
endmodule
module ACMP_uitodp(clk, reset, ce, din0, dout);
parameter ID = 0;
parameter NUM_STAGE = 12;
parameter din0_WIDTH = 32;
parameter dout_WIDTH = 64;
input clk;
input reset, ce;
input[din0_WIDTH-1:0] din0;
output[dout_WIDTH-1:0] dout;
AESL_WP_UIToDP
#(NUM_STAGE, din0_WIDTH, dout_WIDTH)
ACMP_UIToDP_U(
.clk(clk),
.reset(reset),
.ce(ce),
.din0(din0),
.dout(dout));
endmodule
/*
-------------------------------------------------------------------------------
-- single to double precision
-------------------------------------------------------------------------------
*/
module ACMP_fpext_comb(din0, dout);
parameter ID = 0;
parameter NUM_STAGE = 12;
parameter din0_WIDTH = 32;
parameter dout_WIDTH = 64;
input[din0_WIDTH-1:0] din0;
output[dout_WIDTH-1:0] dout;
AESL_WP_SPToDP
#(NUM_STAGE, din0_WIDTH, dout_WIDTH)
ACMP_fpext_U(
.clk(1'b1),
.reset(1'b1),
.ce(1'b1),
.din0(din0),
.dout(dout));
endmodule
module ACMP_fpext(clk, reset, ce, din0, dout);
parameter ID = 0;
parameter NUM_STAGE = 12;
parameter din0_WIDTH = 32;
parameter dout_WIDTH = 64;
input clk;
input reset, ce;
input[din0_WIDTH-1:0] din0;
output[dout_WIDTH-1:0] dout;
AESL_WP_SPToDP
#(NUM_STAGE, din0_WIDTH, dout_WIDTH)
ACMP_fpext_U(
.clk(clk),
.reset(reset),
.ce(ce),
.din0(din0),
.dout(dout));
endmodule
/*
-------------------------------------------------------------------------------
-- double to single precision
-------------------------------------------------------------------------------
*/
module ACMP_fptrunc_comb(din0, dout);
parameter ID = 0;
parameter NUM_STAGE = 12;
parameter din0_WIDTH = 32;
parameter dout_WIDTH = 64;
input[din0_WIDTH-1:0] din0;
output[dout_WIDTH-1:0] dout;
AESL_WP_DPToSP
#(NUM_STAGE, din0_WIDTH, dout_WIDTH)
ACMP_fptrunc_U(
.clk(1'b1),
.reset(1'b1),
.ce(1'b1),
.din0(din0),
.dout(dout));
endmodule
module ACMP_fptrunc(clk, reset, ce, din0, dout);
parameter ID = 0;
parameter NUM_STAGE = 12;
parameter din0_WIDTH = 32;
parameter dout_WIDTH = 64;
input clk;
input reset, ce;
input[din0_WIDTH-1:0] din0;
output[dout_WIDTH-1:0] dout;
AESL_WP_DPToSP
#(NUM_STAGE, din0_WIDTH, dout_WIDTH)
ACMP_fptrunc_U(
.clk(clk),
.reset(reset),
.ce(ce),
.din0(din0),
.dout(dout));
endmodule
|
// ==============================================================
// RTL generated by AutoESL - High-Level Synthesis System (C, C++, SystemC)
// Version: 2011.1
// Copyright (C) 2011 Xilinx Inc. All rights reserved.
//
// ===========================================================
`timescale 1 ns / 1 ps
module fetch (
ap_clk,
ap_rst,
ap_start,
ap_done,
ap_idle,
tag,
counter,
a_address0,
a_ce0,
a_we0,
a_d0,
a_address1,
a_ce1,
a_we1,
a_d1,
V_bus_req_din,
V_bus_req_full_n,
V_bus_req_write,
V_bus_rsp_dout,
V_bus_rsp_empty_n,
V_bus_rsp_read,
V_bus_address,
V_bus_datain,
V_bus_dataout,
V_bus_size
);
input ap_clk;
input ap_rst;
input ap_start;
output ap_done;
output ap_idle;
input [1:0] tag;
input [6:0] counter;
output [11:0] a_address0;
output a_ce0;
output a_we0;
output [31:0] a_d0;
output [11:0] a_address1;
output a_ce1;
output a_we1;
output [31:0] a_d1;
output V_bus_req_din;
input V_bus_req_full_n;
output V_bus_req_write;
input V_bus_rsp_dout;
input V_bus_rsp_empty_n;
output V_bus_rsp_read;
output [31:0] V_bus_address;
input [127:0] V_bus_datain;
output [127:0] V_bus_dataout;
output [31:0] V_bus_size;
reg ap_done;
reg ap_idle;
reg[11:0] a_address0;
reg a_ce0;
reg a_we0;
reg[31:0] a_d0;
reg[11:0] a_address1;
reg a_ce1;
reg a_we1;
reg[31:0] a_d1;
reg V_bus_req_write;
reg V_bus_rsp_read;
reg[31:0] V_bus_address;
reg [2:0] ap_CS_fsm;
reg [10:0] indvar_flatten_reg_180;
reg [6:0] i_reg_191;
reg [4:0] indvar1_reg_202;
reg [6:0] j_reg_213;
reg [10:0] indvar_flatten1_reg_224;
reg [6:0] i_1_reg_235;
reg [4:0] indvar_reg_246;
reg [6:0] j_1_reg_257;
wire [19:0] tmp3_cast_fu_303_p1;
reg [19:0] tmp3_cast_reg_835;
wire [0:0] icmp_fu_281_p2;
wire [0:0] tmp_2_fu_287_p2;
wire [19:0] tmp2_fu_321_p2;
reg [19:0] tmp2_reg_840;
wire [0:0] exitcond2_fu_327_p2;
reg [0:0] exitcond2_reg_845;
reg ap_reg_ppiten_pp0_it0;
reg ap_sig_bdd_86;
reg ap_reg_ppiten_pp0_it1;
reg ap_reg_ppiten_pp0_it2;
reg [0:0] ap_reg_ppstg_exitcond2_reg_845_pp0_it1;
reg [10:0] indvar_flatten_next_reg_849;
reg [6:0] j_mid2_reg_854;
reg [6:0] ap_reg_ppstg_j_mid2_reg_854_pp0_it1;
wire [6:0] i_mid2_fu_367_p3;
reg [6:0] i_mid2_reg_863;
reg [6:0] ap_reg_ppstg_i_mid2_reg_863_pp0_it1;
wire [19:0] tmp13_fu_409_p2;
reg [19:0] tmp13_reg_869;
reg [4:0] indvar_next1_reg_874;
reg ap_sig_bdd_119;
reg [31:0] tmp_17_reg_884;
reg [31:0] p_4_reg_889;
reg [31:0] p_5_reg_894;
reg [31:0] p_6_reg_899;
wire [6:0] tmp_25_fu_470_p2;
wire [13:0] a_addr2_cast_fu_491_p1;
reg [13:0] a_addr2_cast_reg_909;
wire [0:0] exitcond_fu_576_p2;
reg [0:0] exitcond_reg_915;
reg ap_reg_ppiten_pp1_it0;
reg ap_sig_bdd_151;
reg ap_reg_ppiten_pp1_it1;
reg ap_reg_ppiten_pp1_it2;
reg [0:0] ap_reg_ppstg_exitcond_reg_915_pp1_it1;
reg [10:0] indvar_flatten_next1_reg_919;
reg [6:0] j_1_mid2_reg_924;
reg [6:0] ap_reg_ppstg_j_1_mid2_reg_924_pp1_it1;
wire [6:0] i_1_mid2_fu_616_p3;
reg [6:0] i_1_mid2_reg_933;
reg [6:0] ap_reg_ppstg_i_1_mid2_reg_933_pp1_it1;
reg [17:0] tmp_26_reg_939;
reg [4:0] indvar_next_reg_944;
reg ap_sig_bdd_183;
reg [31:0] tmp_9_reg_954;
reg [31:0] p_1_reg_959;
reg [31:0] p_2_reg_964;
reg [31:0] p_3_reg_969;
wire [6:0] tmp_13_fu_723_p2;
wire [13:0] a_addr9_cast_fu_744_p1;
reg [13:0] a_addr9_cast_reg_979;
reg [10:0] indvar_flatten_phi_fu_184_p4;
reg [6:0] i_phi_fu_195_p4;
reg [4:0] indvar1_phi_fu_206_p4;
reg [6:0] j_phi_fu_217_p4;
reg [10:0] indvar_flatten1_phi_fu_228_p4;
reg [6:0] i_1_phi_fu_239_p4;
reg [4:0] indvar_phi_fu_250_p4;
reg [6:0] j_1_phi_fu_261_p4;
wire [63:0] tmp_18_fu_501_p1;
wire [63:0] tmp_20_fu_525_p1;
wire [63:0] tmp_22_fu_548_p1;
wire [63:0] tmp_24_fu_571_p1;
wire [63:0] tmp_3_fu_754_p1;
wire [63:0] tmp_4_fu_778_p1;
wire [63:0] tmp_10_fu_801_p1;
wire [63:0] tmp_12_fu_824_p1;
wire [63:0] tmp_16_fu_425_p1;
wire [63:0] tmp_7_fu_679_p1;
wire [31:0] tmp18_fu_475_p1;
wire [31:0] tmp12_fu_535_p1;
wire [31:0] tmp15_fu_728_p1;
wire [31:0] tmp14_fu_788_p1;
wire [31:0] tmp16_fu_511_p1;
wire [31:0] tmp8_fu_558_p1;
wire [31:0] tmp17_fu_764_p1;
wire [31:0] tmp10_fu_811_p1;
wire [0:0] tmp_1_fu_269_p3;
wire [1:0] tmp_8_fu_277_p1;
wire [18:0] counter_cast_fu_293_p1;
wire [18:0] tmp3_fu_297_p2;
wire [18:0] counter_cast2_fu_307_p1;
wire [18:0] tmp1_fu_311_p2;
wire [19:0] tmp1_cast_fu_317_p1;
wire [0:0] exitcond3_fu_339_p2;
wire [6:0] tmp_17_dup_fu_361_p2;
wire [12:0] i_cast_fu_375_p1;
wire [4:0] indvar1_mid2_fu_345_p3;
wire [6:0] indvar1_cast_fu_385_p1;
wire [6:0] tmp7_fu_389_p2;
wire [12:0] tmp6_fu_379_p2;
wire [12:0] tmp7_cast_fu_395_p1;
wire [12:0] tmp11_fu_399_p2;
wire [19:0] tmp11_cast_fu_405_p1;
wire [19:0] tmp_15_fu_420_p2;
wire [12:0] tmp_4_trn_cast_fu_479_p1;
wire [12:0] a_addr2_fu_485_p2;
wire [13:0] tmp_22_trn_cast_fu_482_p1;
wire [13:0] a_addr3_fu_495_p2;
wire [6:0] tmp_19_fu_506_p2;
wire [13:0] tmp_24_trn_cast_fu_515_p1;
wire [13:0] a_addr5_fu_519_p2;
wire [6:0] tmp_21_fu_530_p2;
wire [13:0] tmp_26_trn_cast_fu_539_p1;
wire [13:0] a_addr6_fu_543_p2;
wire [6:0] tmp_23_fu_553_p2;
wire [13:0] tmp_28_trn_cast_fu_562_p1;
wire [13:0] a_addr8_fu_566_p2;
wire [0:0] exitcond1_fu_588_p2;
wire [6:0] tmp_5_dup_fu_610_p2;
wire [12:0] i_1_cast_fu_624_p1;
wire [4:0] indvar_mid2_fu_594_p3;
wire [6:0] indvar_cast_fu_634_p1;
wire [6:0] tmp_fu_638_p2;
wire [12:0] tmp4_fu_628_p2;
wire [12:0] tmp_cast_fu_644_p1;
wire [12:0] tmp5_fu_648_p2;
wire [19:0] tmp5_cast_cast_fu_654_p1;
wire [19:0] tmp9_fu_658_p2;
wire [12:0] tmp_3_trn8_cast_fu_732_p1;
wire [12:0] a_addr9_fu_738_p2;
wire [13:0] tmp_trn_cast_fu_735_p1;
wire [13:0] a_addr_fu_748_p2;
wire [6:0] tmp_s_fu_759_p2;
wire [13:0] tmp_11_trn_cast_fu_768_p1;
wire [13:0] a_addr7_fu_772_p2;
wire [6:0] tmp_5_fu_783_p2;
wire [13:0] tmp_13_trn_cast_fu_792_p1;
wire [13:0] a_addr4_fu_796_p2;
wire [6:0] tmp_11_fu_806_p2;
wire [13:0] tmp_15_trn_cast_fu_815_p1;
wire [13:0] a_addr1_fu_819_p2;
reg [2:0] ap_NS_fsm;
parameter ap_const_logic_1 = 1'b1;
parameter ap_const_logic_0 = 1'b0;
parameter ap_ST_st0_fsm_0 = 3'b000;
parameter ap_ST_st1_fsm_1 = 3'b001;
parameter ap_ST_pp0_stg0_fsm_2 = 3'b010;
parameter ap_ST_pp0_stg1_fsm_3 = 3'b011;
parameter ap_ST_pp1_stg0_fsm_4 = 3'b100;
parameter ap_ST_pp1_stg1_fsm_5 = 3'b101;
parameter ap_ST_st12_fsm_6 = 3'b110;
parameter ap_const_lv1_0 = 1'b0;
parameter ap_const_lv11_0 = 11'b00000000000;
parameter ap_const_lv7_0 = 7'b0000000;
parameter ap_const_lv5_0 = 5'b00000;
parameter ap_const_lv32_0 = 32'b00000000000000000000000000000000;
parameter ap_const_lv32_6 = 32'b00000000000000000000000000000110;
parameter ap_const_lv2_1 = 2'b01;
parameter ap_const_lv2_0 = 2'b00;
parameter ap_const_lv19_C = 19'b0000000000000001100;
parameter ap_const_lv20_3F000 = 20'b00111111000000000000;
parameter ap_const_lv11_400 = 11'b10000000000;
parameter ap_const_lv11_1 = 11'b00000000001;
parameter ap_const_lv5_10 = 5'b10000;
parameter ap_const_lv7_1 = 7'b0000001;
parameter ap_const_lv13_6 = 13'b0000000000110;
parameter ap_const_lv7_2 = 7'b0000010;
parameter ap_const_lv5_1 = 5'b00001;
parameter ap_const_lv20_2 = 20'b00000000000000000010;
parameter ap_const_lv32_20 = 32'b00000000000000000000000000100000;
parameter ap_const_lv32_3F = 32'b00000000000000000000000000111111;
parameter ap_const_lv32_40 = 32'b00000000000000000000000001000000;
parameter ap_const_lv32_5F = 32'b00000000000000000000000001011111;
parameter ap_const_lv32_60 = 32'b00000000000000000000000001100000;
parameter ap_const_lv32_7F = 32'b00000000000000000000000001111111;
parameter ap_const_lv7_4 = 7'b0000100;
parameter ap_const_lv7_3 = 7'b0000011;
parameter ap_const_lv32_2 = 32'b00000000000000000000000000000010;
parameter ap_const_lv32_13 = 32'b00000000000000000000000000010011;
parameter ap_const_lv128_lc_1 = 128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_true = 1'b1;
/// ap_CS_fsm assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_CS_fsm
if (ap_rst == 1'b1) begin
ap_CS_fsm <= ap_ST_st0_fsm_0;
end else begin
ap_CS_fsm <= ap_NS_fsm;
end
end
/// ap_reg_ppiten_pp0_it0 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it0
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it0 <= ap_const_logic_0;
end else begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & ~(ap_sig_bdd_86 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) & ~(ap_const_lv1_0 == exitcond2_fu_327_p2))) begin
ap_reg_ppiten_pp0_it0 <= ap_const_logic_0;
end else if (((ap_ST_st1_fsm_1 == ap_CS_fsm) & (icmp_fu_281_p2 == ap_const_lv1_0) & ~(ap_const_lv1_0 == tmp_2_fu_287_p2))) begin
ap_reg_ppiten_pp0_it0 <= ap_const_logic_1;
end
end
end
/// ap_reg_ppiten_pp0_it1 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it1
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it1 <= ap_const_logic_0;
end else begin
if (((ap_const_lv1_0 == exitcond2_reg_845) & (ap_ST_pp0_stg1_fsm_3 == ap_CS_fsm) & ~((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ap_sig_bdd_119))) begin
ap_reg_ppiten_pp0_it1 <= ap_const_logic_1;
end else if ((((ap_ST_st1_fsm_1 == ap_CS_fsm) & (icmp_fu_281_p2 == ap_const_lv1_0) & ~(ap_const_lv1_0 == tmp_2_fu_287_p2)) | ((ap_ST_pp0_stg1_fsm_3 == ap_CS_fsm) & ~((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ap_sig_bdd_119) & ~(ap_const_lv1_0 == exitcond2_reg_845)))) begin
ap_reg_ppiten_pp0_it1 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp0_it2 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it2
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it2 <= ap_const_logic_0;
end else begin
if (((ap_ST_pp0_stg1_fsm_3 == ap_CS_fsm) & ~((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ap_sig_bdd_119))) begin
ap_reg_ppiten_pp0_it2 <= ap_reg_ppiten_pp0_it1;
end else if (((ap_ST_st1_fsm_1 == ap_CS_fsm) & (icmp_fu_281_p2 == ap_const_lv1_0) & ~(ap_const_lv1_0 == tmp_2_fu_287_p2))) begin
ap_reg_ppiten_pp0_it2 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp1_it0 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp1_it0
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp1_it0 <= ap_const_logic_0;
end else begin
if (((ap_ST_pp1_stg0_fsm_4 == ap_CS_fsm) & ~(ap_sig_bdd_151 & (ap_const_logic_1 == ap_reg_ppiten_pp1_it1)) & ~(ap_const_lv1_0 == exitcond_fu_576_p2))) begin
ap_reg_ppiten_pp1_it0 <= ap_const_logic_0;
end else if (((ap_ST_st1_fsm_1 == ap_CS_fsm) & ~(icmp_fu_281_p2 == ap_const_lv1_0))) begin
ap_reg_ppiten_pp1_it0 <= ap_const_logic_1;
end
end
end
/// ap_reg_ppiten_pp1_it1 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp1_it1
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp1_it1 <= ap_const_logic_0;
end else begin
if (((ap_const_lv1_0 == exitcond_reg_915) & (ap_ST_pp1_stg1_fsm_5 == ap_CS_fsm) & ~((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & ap_sig_bdd_183))) begin
ap_reg_ppiten_pp1_it1 <= ap_const_logic_1;
end else if ((((ap_ST_st1_fsm_1 == ap_CS_fsm) & ~(icmp_fu_281_p2 == ap_const_lv1_0)) | ((ap_ST_pp1_stg1_fsm_5 == ap_CS_fsm) & ~((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & ap_sig_bdd_183) & ~(ap_const_lv1_0 == exitcond_reg_915)))) begin
ap_reg_ppiten_pp1_it1 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp1_it2 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp1_it2
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp1_it2 <= ap_const_logic_0;
end else begin
if (((ap_ST_pp1_stg1_fsm_5 == ap_CS_fsm) & ~((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & ap_sig_bdd_183))) begin
ap_reg_ppiten_pp1_it2 <= ap_reg_ppiten_pp1_it1;
end else if (((ap_ST_st1_fsm_1 == ap_CS_fsm) & ~(icmp_fu_281_p2 == ap_const_lv1_0))) begin
ap_reg_ppiten_pp1_it2 <= ap_const_logic_0;
end
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (ap_ST_pp0_stg1_fsm_3 == ap_CS_fsm) & ~((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ap_sig_bdd_119) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_845_pp0_it1))) begin
a_addr2_cast_reg_909[6] <= a_addr2_cast_fu_491_p1[6];
a_addr2_cast_reg_909[7] <= a_addr2_cast_fu_491_p1[7];
a_addr2_cast_reg_909[8] <= a_addr2_cast_fu_491_p1[8];
a_addr2_cast_reg_909[9] <= a_addr2_cast_fu_491_p1[9];
a_addr2_cast_reg_909[10] <= a_addr2_cast_fu_491_p1[10];
a_addr2_cast_reg_909[11] <= a_addr2_cast_fu_491_p1[11];
a_addr2_cast_reg_909[12] <= a_addr2_cast_fu_491_p1[12];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_ST_pp1_stg1_fsm_5 == ap_CS_fsm) & ~((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & ap_sig_bdd_183) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_915_pp1_it1))) begin
a_addr9_cast_reg_979[6] <= a_addr9_cast_fu_744_p1[6];
a_addr9_cast_reg_979[7] <= a_addr9_cast_fu_744_p1[7];
a_addr9_cast_reg_979[8] <= a_addr9_cast_fu_744_p1[8];
a_addr9_cast_reg_979[9] <= a_addr9_cast_fu_744_p1[9];
a_addr9_cast_reg_979[10] <= a_addr9_cast_fu_744_p1[10];
a_addr9_cast_reg_979[11] <= a_addr9_cast_fu_744_p1[11];
a_addr9_cast_reg_979[12] <= a_addr9_cast_fu_744_p1[12];
end
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & ~(ap_sig_bdd_86 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)))) begin
ap_reg_ppstg_exitcond2_reg_845_pp0_it1 <= exitcond2_reg_845;
end
if (((ap_ST_pp1_stg0_fsm_4 == ap_CS_fsm) & ~(ap_sig_bdd_151 & (ap_const_logic_1 == ap_reg_ppiten_pp1_it1)))) begin
ap_reg_ppstg_exitcond_reg_915_pp1_it1 <= exitcond_reg_915;
end
if (((ap_ST_pp1_stg0_fsm_4 == ap_CS_fsm) & ~(ap_sig_bdd_151 & (ap_const_logic_1 == ap_reg_ppiten_pp1_it1)))) begin
ap_reg_ppstg_i_1_mid2_reg_933_pp1_it1 <= i_1_mid2_reg_933;
end
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & ~(ap_sig_bdd_86 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)))) begin
ap_reg_ppstg_i_mid2_reg_863_pp0_it1 <= i_mid2_reg_863;
end
if (((ap_ST_pp1_stg0_fsm_4 == ap_CS_fsm) & ~(ap_sig_bdd_151 & (ap_const_logic_1 == ap_reg_ppiten_pp1_it1)))) begin
ap_reg_ppstg_j_1_mid2_reg_924_pp1_it1 <= j_1_mid2_reg_924;
end
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & ~(ap_sig_bdd_86 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)))) begin
ap_reg_ppstg_j_mid2_reg_854_pp0_it1 <= j_mid2_reg_854;
end
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ~(ap_sig_bdd_86 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)))) begin
exitcond2_reg_845 <= (indvar_flatten_phi_fu_184_p4 == ap_const_lv11_400? 1'b1: 1'b0);
end
if (((ap_ST_pp1_stg0_fsm_4 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & ~(ap_sig_bdd_151 & (ap_const_logic_1 == ap_reg_ppiten_pp1_it1)))) begin
exitcond_reg_915 <= (indvar_flatten1_phi_fu_228_p4 == ap_const_lv11_400? 1'b1: 1'b0);
end
if (((ap_ST_pp1_stg0_fsm_4 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & ~(ap_sig_bdd_151 & (ap_const_logic_1 == ap_reg_ppiten_pp1_it1)) & (ap_const_lv1_0 == exitcond_fu_576_p2))) begin
if (exitcond1_fu_588_p2) begin
i_1_mid2_reg_933 <= tmp_5_dup_fu_610_p2;
end else begin
i_1_mid2_reg_933 <= i_1_phi_fu_239_p4;
end
end
if (((ap_ST_pp1_stg0_fsm_4 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond_reg_915) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & ~(ap_sig_bdd_151 & (ap_const_logic_1 == ap_reg_ppiten_pp1_it1)))) begin
i_1_reg_235 <= i_1_mid2_reg_933;
end else if (((ap_ST_st1_fsm_1 == ap_CS_fsm) & ~(icmp_fu_281_p2 == ap_const_lv1_0))) begin
i_1_reg_235 <= ap_const_lv7_0;
end
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ~(ap_sig_bdd_86 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) & (ap_const_lv1_0 == exitcond2_fu_327_p2))) begin
if (exitcond3_fu_339_p2) begin
i_mid2_reg_863 <= tmp_17_dup_fu_361_p2;
end else begin
i_mid2_reg_863 <= i_phi_fu_195_p4;
end
end
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond2_reg_845) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & ~(ap_sig_bdd_86 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)))) begin
i_reg_191 <= i_mid2_reg_863;
end else if (((ap_ST_st1_fsm_1 == ap_CS_fsm) & (icmp_fu_281_p2 == ap_const_lv1_0) & ~(ap_const_lv1_0 == tmp_2_fu_287_p2))) begin
i_reg_191 <= ap_const_lv7_0;
end
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond2_reg_845) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & ~(ap_sig_bdd_86 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)))) begin
indvar1_reg_202 <= indvar_next1_reg_874;
end else if (((ap_ST_st1_fsm_1 == ap_CS_fsm) & (icmp_fu_281_p2 == ap_const_lv1_0) & ~(ap_const_lv1_0 == tmp_2_fu_287_p2))) begin
indvar1_reg_202 <= ap_const_lv5_0;
end
if (((ap_ST_pp1_stg0_fsm_4 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond_reg_915) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & ~(ap_sig_bdd_151 & (ap_const_logic_1 == ap_reg_ppiten_pp1_it1)))) begin
indvar_flatten1_reg_224 <= indvar_flatten_next1_reg_919;
end else if (((ap_ST_st1_fsm_1 == ap_CS_fsm) & ~(icmp_fu_281_p2 == ap_const_lv1_0))) begin
indvar_flatten1_reg_224 <= ap_const_lv11_0;
end
if (((ap_ST_pp1_stg0_fsm_4 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & ~(ap_sig_bdd_151 & (ap_const_logic_1 == ap_reg_ppiten_pp1_it1)))) begin
indvar_flatten_next1_reg_919 <= (indvar_flatten1_phi_fu_228_p4 + ap_const_lv11_1);
end
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ~(ap_sig_bdd_86 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)))) begin
indvar_flatten_next_reg_849 <= (indvar_flatten_phi_fu_184_p4 + ap_const_lv11_1);
end
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond2_reg_845) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & ~(ap_sig_bdd_86 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)))) begin
indvar_flatten_reg_180 <= indvar_flatten_next_reg_849;
end else if (((ap_ST_st1_fsm_1 == ap_CS_fsm) & (icmp_fu_281_p2 == ap_const_lv1_0) & ~(ap_const_lv1_0 == tmp_2_fu_287_p2))) begin
indvar_flatten_reg_180 <= ap_const_lv11_0;
end
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ~(ap_sig_bdd_86 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) & (ap_const_lv1_0 == exitcond2_fu_327_p2))) begin
indvar_next1_reg_874 <= (indvar1_mid2_fu_345_p3 + ap_const_lv5_1);
end
if (((ap_ST_pp1_stg0_fsm_4 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & ~(ap_sig_bdd_151 & (ap_const_logic_1 == ap_reg_ppiten_pp1_it1)) & (ap_const_lv1_0 == exitcond_fu_576_p2))) begin
indvar_next_reg_944 <= (indvar_mid2_fu_594_p3 + ap_const_lv5_1);
end
if (((ap_ST_pp1_stg0_fsm_4 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond_reg_915) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & ~(ap_sig_bdd_151 & (ap_const_logic_1 == ap_reg_ppiten_pp1_it1)))) begin
indvar_reg_246 <= indvar_next_reg_944;
end else if (((ap_ST_st1_fsm_1 == ap_CS_fsm) & ~(icmp_fu_281_p2 == ap_const_lv1_0))) begin
indvar_reg_246 <= ap_const_lv5_0;
end
if (((ap_ST_pp1_stg0_fsm_4 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & ~(ap_sig_bdd_151 & (ap_const_logic_1 == ap_reg_ppiten_pp1_it1)) & (ap_const_lv1_0 == exitcond_fu_576_p2))) begin
if (exitcond1_fu_588_p2) begin
j_1_mid2_reg_924 <= ap_const_lv7_0;
end else begin
j_1_mid2_reg_924 <= j_1_phi_fu_261_p4;
end
end
if (((ap_ST_pp1_stg0_fsm_4 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond_reg_915) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & ~(ap_sig_bdd_151 & (ap_const_logic_1 == ap_reg_ppiten_pp1_it1)))) begin
j_1_reg_257 <= (j_1_mid2_reg_924 + ap_const_lv7_4);
end else if (((ap_ST_st1_fsm_1 == ap_CS_fsm) & ~(icmp_fu_281_p2 == ap_const_lv1_0))) begin
j_1_reg_257 <= ap_const_lv7_0;
end
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ~(ap_sig_bdd_86 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) & (ap_const_lv1_0 == exitcond2_fu_327_p2))) begin
if (exitcond3_fu_339_p2) begin
j_mid2_reg_854 <= ap_const_lv7_0;
end else begin
j_mid2_reg_854 <= j_phi_fu_217_p4;
end
end
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond2_reg_845) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & ~(ap_sig_bdd_86 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)))) begin
j_reg_213 <= (j_mid2_reg_854 + ap_const_lv7_4);
end else if (((ap_ST_st1_fsm_1 == ap_CS_fsm) & (icmp_fu_281_p2 == ap_const_lv1_0) & ~(ap_const_lv1_0 == tmp_2_fu_287_p2))) begin
j_reg_213 <= ap_const_lv7_0;
end
if (((ap_ST_pp1_stg0_fsm_4 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond_reg_915) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & ~(ap_sig_bdd_151 & (ap_const_logic_1 == ap_reg_ppiten_pp1_it1)))) begin
p_1_reg_959 <= {{V_bus_datain[ap_const_lv32_3F : ap_const_lv32_20]}};
end
if (((ap_ST_pp1_stg0_fsm_4 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond_reg_915) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & ~(ap_sig_bdd_151 & (ap_const_logic_1 == ap_reg_ppiten_pp1_it1)))) begin
p_2_reg_964 <= {{V_bus_datain[ap_const_lv32_5F : ap_const_lv32_40]}};
end
if (((ap_ST_pp1_stg0_fsm_4 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond_reg_915) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & ~(ap_sig_bdd_151 & (ap_const_logic_1 == ap_reg_ppiten_pp1_it1)))) begin
p_3_reg_969 <= {{V_bus_datain[ap_const_lv32_7F : ap_const_lv32_60]}};
end
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond2_reg_845) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & ~(ap_sig_bdd_86 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)))) begin
p_4_reg_889 <= {{V_bus_datain[ap_const_lv32_3F : ap_const_lv32_20]}};
end
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond2_reg_845) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & ~(ap_sig_bdd_86 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)))) begin
p_5_reg_894 <= {{V_bus_datain[ap_const_lv32_5F : ap_const_lv32_40]}};
end
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond2_reg_845) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & ~(ap_sig_bdd_86 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)))) begin
p_6_reg_899 <= {{V_bus_datain[ap_const_lv32_7F : ap_const_lv32_60]}};
end
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ~(ap_sig_bdd_86 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) & (ap_const_lv1_0 == exitcond2_fu_327_p2))) begin
tmp13_reg_869[2] <= tmp13_fu_409_p2[2];
tmp13_reg_869[3] <= tmp13_fu_409_p2[3];
tmp13_reg_869[4] <= tmp13_fu_409_p2[4];
tmp13_reg_869[5] <= tmp13_fu_409_p2[5];
tmp13_reg_869[6] <= tmp13_fu_409_p2[6];
tmp13_reg_869[7] <= tmp13_fu_409_p2[7];
tmp13_reg_869[8] <= tmp13_fu_409_p2[8];
tmp13_reg_869[9] <= tmp13_fu_409_p2[9];
tmp13_reg_869[10] <= tmp13_fu_409_p2[10];
tmp13_reg_869[11] <= tmp13_fu_409_p2[11];
tmp13_reg_869[12] <= tmp13_fu_409_p2[12];
tmp13_reg_869[13] <= tmp13_fu_409_p2[13];
tmp13_reg_869[14] <= tmp13_fu_409_p2[14];
tmp13_reg_869[15] <= tmp13_fu_409_p2[15];
tmp13_reg_869[16] <= tmp13_fu_409_p2[16];
tmp13_reg_869[17] <= tmp13_fu_409_p2[17];
tmp13_reg_869[18] <= tmp13_fu_409_p2[18];
tmp13_reg_869[19] <= tmp13_fu_409_p2[19];
end
if (((ap_ST_st1_fsm_1 == ap_CS_fsm) & ~(icmp_fu_281_p2 == ap_const_lv1_0))) begin
tmp2_reg_840[12] <= tmp2_fu_321_p2[12];
tmp2_reg_840[13] <= tmp2_fu_321_p2[13];
tmp2_reg_840[14] <= tmp2_fu_321_p2[14];
tmp2_reg_840[15] <= tmp2_fu_321_p2[15];
tmp2_reg_840[16] <= tmp2_fu_321_p2[16];
tmp2_reg_840[17] <= tmp2_fu_321_p2[17];
tmp2_reg_840[18] <= tmp2_fu_321_p2[18];
tmp2_reg_840[19] <= tmp2_fu_321_p2[19];
end
if (((ap_ST_st1_fsm_1 == ap_CS_fsm) & (icmp_fu_281_p2 == ap_const_lv1_0) & ~(ap_const_lv1_0 == tmp_2_fu_287_p2))) begin
tmp3_cast_reg_835[12] <= tmp3_cast_fu_303_p1[12];
tmp3_cast_reg_835[13] <= tmp3_cast_fu_303_p1[13];
tmp3_cast_reg_835[14] <= tmp3_cast_fu_303_p1[14];
tmp3_cast_reg_835[15] <= tmp3_cast_fu_303_p1[15];
tmp3_cast_reg_835[16] <= tmp3_cast_fu_303_p1[16];
tmp3_cast_reg_835[17] <= tmp3_cast_fu_303_p1[17];
tmp3_cast_reg_835[18] <= tmp3_cast_fu_303_p1[18];
end
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond2_reg_845) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & ~(ap_sig_bdd_86 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)))) begin
tmp_17_reg_884 <= V_bus_datain[31:0];
end
if (((ap_ST_pp1_stg0_fsm_4 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & ~(ap_sig_bdd_151 & (ap_const_logic_1 == ap_reg_ppiten_pp1_it1)) & (ap_const_lv1_0 == exitcond_fu_576_p2))) begin
tmp_26_reg_939 <= {{tmp9_fu_658_p2[ap_const_lv32_13 : ap_const_lv32_2]}};
end
if (((ap_ST_pp1_stg0_fsm_4 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond_reg_915) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & ~(ap_sig_bdd_151 & (ap_const_logic_1 == ap_reg_ppiten_pp1_it1)))) begin
tmp_9_reg_954 <= V_bus_datain[31:0];
end
end
/// V_bus_address assign process. ///
always @ (ap_CS_fsm or exitcond2_reg_845 or ap_reg_ppiten_pp0_it0 or ap_sig_bdd_119 or exitcond_reg_915 or ap_reg_ppiten_pp1_it0 or ap_sig_bdd_183 or tmp_16_fu_425_p1 or tmp_7_fu_679_p1)
begin
if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond_reg_915) & (ap_ST_pp1_stg1_fsm_5 == ap_CS_fsm) & ~((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & ap_sig_bdd_183))) begin
V_bus_address = tmp_7_fu_679_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (ap_const_lv1_0 == exitcond2_reg_845) & (ap_ST_pp0_stg1_fsm_3 == ap_CS_fsm) & ~((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ap_sig_bdd_119))) begin
V_bus_address = tmp_16_fu_425_p1;
end else begin
V_bus_address = tmp_7_fu_679_p1;
end
end
/// V_bus_req_write assign process. ///
always @ (ap_CS_fsm or exitcond2_reg_845 or ap_reg_ppiten_pp0_it0 or ap_sig_bdd_119 or exitcond_reg_915 or ap_reg_ppiten_pp1_it0 or ap_sig_bdd_183)
begin
if ((((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (ap_const_lv1_0 == exitcond2_reg_845) & (ap_ST_pp0_stg1_fsm_3 == ap_CS_fsm) & ~((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ap_sig_bdd_119)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond_reg_915) & (ap_ST_pp1_stg1_fsm_5 == ap_CS_fsm) & ~((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & ap_sig_bdd_183)))) begin
V_bus_req_write = ap_const_logic_1;
end else begin
V_bus_req_write = ap_const_logic_0;
end
end
/// V_bus_rsp_read assign process. ///
always @ (ap_CS_fsm or exitcond2_reg_845 or ap_sig_bdd_86 or ap_reg_ppiten_pp0_it1 or exitcond_reg_915 or ap_sig_bdd_151 or ap_reg_ppiten_pp1_it1)
begin
if ((((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond2_reg_845) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & ~(ap_sig_bdd_86 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1))) | ((ap_ST_pp1_stg0_fsm_4 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond_reg_915) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & ~(ap_sig_bdd_151 & (ap_const_logic_1 == ap_reg_ppiten_pp1_it1))))) begin
V_bus_rsp_read = ap_const_logic_1;
end else begin
V_bus_rsp_read = ap_const_logic_0;
end
end
/// a_address0 assign process. ///
always @ (ap_CS_fsm or ap_reg_ppiten_pp0_it0 or ap_sig_bdd_86 or ap_reg_ppiten_pp0_it1 or ap_reg_ppiten_pp0_it2 or ap_reg_ppstg_exitcond2_reg_845_pp0_it1 or ap_sig_bdd_119 or ap_reg_ppiten_pp1_it0 or ap_sig_bdd_151 or ap_reg_ppiten_pp1_it1 or ap_reg_ppiten_pp1_it2 or ap_reg_ppstg_exitcond_reg_915_pp1_it1 or ap_sig_bdd_183 or tmp_18_fu_501_p1 or tmp_22_fu_548_p1 or tmp_3_fu_754_p1 or tmp_10_fu_801_p1)
begin
if (((ap_ST_pp1_stg0_fsm_4 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it2) & ~(ap_sig_bdd_151 & (ap_const_logic_1 == ap_reg_ppiten_pp1_it1)) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_915_pp1_it1))) begin
a_address0 = tmp_10_fu_801_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_ST_pp1_stg1_fsm_5 == ap_CS_fsm) & ~((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & ap_sig_bdd_183) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_915_pp1_it1))) begin
a_address0 = tmp_3_fu_754_p1;
end else if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it2) & ~(ap_sig_bdd_86 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_845_pp0_it1))) begin
a_address0 = tmp_22_fu_548_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (ap_ST_pp0_stg1_fsm_3 == ap_CS_fsm) & ~((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ap_sig_bdd_119) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_845_pp0_it1))) begin
a_address0 = tmp_18_fu_501_p1;
end else begin
a_address0 = tmp_10_fu_801_p1;
end
end
/// a_address1 assign process. ///
always @ (ap_CS_fsm or ap_reg_ppiten_pp0_it0 or ap_sig_bdd_86 or ap_reg_ppiten_pp0_it1 or ap_reg_ppiten_pp0_it2 or ap_reg_ppstg_exitcond2_reg_845_pp0_it1 or ap_sig_bdd_119 or ap_reg_ppiten_pp1_it0 or ap_sig_bdd_151 or ap_reg_ppiten_pp1_it1 or ap_reg_ppiten_pp1_it2 or ap_reg_ppstg_exitcond_reg_915_pp1_it1 or ap_sig_bdd_183 or tmp_20_fu_525_p1 or tmp_24_fu_571_p1 or tmp_4_fu_778_p1 or tmp_12_fu_824_p1)
begin
if (((ap_ST_pp1_stg0_fsm_4 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it2) & ~(ap_sig_bdd_151 & (ap_const_logic_1 == ap_reg_ppiten_pp1_it1)) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_915_pp1_it1))) begin
a_address1 = tmp_12_fu_824_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_ST_pp1_stg1_fsm_5 == ap_CS_fsm) & ~((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & ap_sig_bdd_183) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_915_pp1_it1))) begin
a_address1 = tmp_4_fu_778_p1;
end else if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it2) & ~(ap_sig_bdd_86 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_845_pp0_it1))) begin
a_address1 = tmp_24_fu_571_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (ap_ST_pp0_stg1_fsm_3 == ap_CS_fsm) & ~((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ap_sig_bdd_119) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_845_pp0_it1))) begin
a_address1 = tmp_20_fu_525_p1;
end else begin
a_address1 = tmp_12_fu_824_p1;
end
end
/// a_ce0 assign process. ///
always @ (ap_CS_fsm or ap_reg_ppiten_pp0_it0 or ap_sig_bdd_86 or ap_reg_ppiten_pp0_it1 or ap_reg_ppiten_pp0_it2 or ap_reg_ppstg_exitcond2_reg_845_pp0_it1 or ap_sig_bdd_119 or ap_reg_ppiten_pp1_it0 or ap_sig_bdd_151 or ap_reg_ppiten_pp1_it1 or ap_reg_ppiten_pp1_it2 or ap_reg_ppstg_exitcond_reg_915_pp1_it1 or ap_sig_bdd_183)
begin
if ((((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (ap_ST_pp0_stg1_fsm_3 == ap_CS_fsm) & ~((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ap_sig_bdd_119) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_845_pp0_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_ST_pp1_stg1_fsm_5 == ap_CS_fsm) & ~((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & ap_sig_bdd_183) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_915_pp1_it1)) | ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it2) & ~(ap_sig_bdd_86 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_845_pp0_it1)) | ((ap_ST_pp1_stg0_fsm_4 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it2) & ~(ap_sig_bdd_151 & (ap_const_logic_1 == ap_reg_ppiten_pp1_it1)) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_915_pp1_it1)))) begin
a_ce0 = ap_const_logic_1;
end else begin
a_ce0 = ap_const_logic_0;
end
end
/// a_ce1 assign process. ///
always @ (ap_CS_fsm or ap_reg_ppiten_pp0_it0 or ap_sig_bdd_86 or ap_reg_ppiten_pp0_it1 or ap_reg_ppiten_pp0_it2 or ap_reg_ppstg_exitcond2_reg_845_pp0_it1 or ap_sig_bdd_119 or ap_reg_ppiten_pp1_it0 or ap_sig_bdd_151 or ap_reg_ppiten_pp1_it1 or ap_reg_ppiten_pp1_it2 or ap_reg_ppstg_exitcond_reg_915_pp1_it1 or ap_sig_bdd_183)
begin
if ((((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (ap_ST_pp0_stg1_fsm_3 == ap_CS_fsm) & ~((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ap_sig_bdd_119) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_845_pp0_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_ST_pp1_stg1_fsm_5 == ap_CS_fsm) & ~((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & ap_sig_bdd_183) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_915_pp1_it1)) | ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it2) & ~(ap_sig_bdd_86 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_845_pp0_it1)) | ((ap_ST_pp1_stg0_fsm_4 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it2) & ~(ap_sig_bdd_151 & (ap_const_logic_1 == ap_reg_ppiten_pp1_it1)) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_915_pp1_it1)))) begin
a_ce1 = ap_const_logic_1;
end else begin
a_ce1 = ap_const_logic_0;
end
end
/// a_d0 assign process. ///
always @ (ap_CS_fsm or ap_reg_ppiten_pp0_it0 or ap_sig_bdd_86 or ap_reg_ppiten_pp0_it1 or ap_reg_ppiten_pp0_it2 or ap_reg_ppstg_exitcond2_reg_845_pp0_it1 or ap_sig_bdd_119 or ap_reg_ppiten_pp1_it0 or ap_sig_bdd_151 or ap_reg_ppiten_pp1_it1 or ap_reg_ppiten_pp1_it2 or ap_reg_ppstg_exitcond_reg_915_pp1_it1 or ap_sig_bdd_183 or tmp18_fu_475_p1 or tmp12_fu_535_p1 or tmp15_fu_728_p1 or tmp14_fu_788_p1)
begin
if (((ap_ST_pp1_stg0_fsm_4 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it2) & ~(ap_sig_bdd_151 & (ap_const_logic_1 == ap_reg_ppiten_pp1_it1)) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_915_pp1_it1))) begin
a_d0 = tmp14_fu_788_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_ST_pp1_stg1_fsm_5 == ap_CS_fsm) & ~((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & ap_sig_bdd_183) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_915_pp1_it1))) begin
a_d0 = tmp15_fu_728_p1;
end else if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it2) & ~(ap_sig_bdd_86 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_845_pp0_it1))) begin
a_d0 = tmp12_fu_535_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (ap_ST_pp0_stg1_fsm_3 == ap_CS_fsm) & ~((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ap_sig_bdd_119) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_845_pp0_it1))) begin
a_d0 = tmp18_fu_475_p1;
end else begin
a_d0 = tmp14_fu_788_p1;
end
end
/// a_d1 assign process. ///
always @ (ap_CS_fsm or ap_reg_ppiten_pp0_it0 or ap_sig_bdd_86 or ap_reg_ppiten_pp0_it1 or ap_reg_ppiten_pp0_it2 or ap_reg_ppstg_exitcond2_reg_845_pp0_it1 or ap_sig_bdd_119 or ap_reg_ppiten_pp1_it0 or ap_sig_bdd_151 or ap_reg_ppiten_pp1_it1 or ap_reg_ppiten_pp1_it2 or ap_reg_ppstg_exitcond_reg_915_pp1_it1 or ap_sig_bdd_183 or tmp16_fu_511_p1 or tmp8_fu_558_p1 or tmp17_fu_764_p1 or tmp10_fu_811_p1)
begin
if (((ap_ST_pp1_stg0_fsm_4 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it2) & ~(ap_sig_bdd_151 & (ap_const_logic_1 == ap_reg_ppiten_pp1_it1)) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_915_pp1_it1))) begin
a_d1 = tmp10_fu_811_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_ST_pp1_stg1_fsm_5 == ap_CS_fsm) & ~((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & ap_sig_bdd_183) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_915_pp1_it1))) begin
a_d1 = tmp17_fu_764_p1;
end else if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it2) & ~(ap_sig_bdd_86 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_845_pp0_it1))) begin
a_d1 = tmp8_fu_558_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (ap_ST_pp0_stg1_fsm_3 == ap_CS_fsm) & ~((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ap_sig_bdd_119) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_845_pp0_it1))) begin
a_d1 = tmp16_fu_511_p1;
end else begin
a_d1 = tmp10_fu_811_p1;
end
end
/// a_we0 assign process. ///
always @ (ap_CS_fsm or ap_reg_ppiten_pp0_it0 or ap_sig_bdd_86 or ap_reg_ppiten_pp0_it1 or ap_reg_ppiten_pp0_it2 or ap_reg_ppstg_exitcond2_reg_845_pp0_it1 or ap_sig_bdd_119 or ap_reg_ppiten_pp1_it0 or ap_sig_bdd_151 or ap_reg_ppiten_pp1_it1 or ap_reg_ppiten_pp1_it2 or ap_reg_ppstg_exitcond_reg_915_pp1_it1 or ap_sig_bdd_183)
begin
if ((((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (ap_ST_pp0_stg1_fsm_3 == ap_CS_fsm) & ~((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ap_sig_bdd_119) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_845_pp0_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_ST_pp1_stg1_fsm_5 == ap_CS_fsm) & ~((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & ap_sig_bdd_183) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_915_pp1_it1)) | ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it2) & ~(ap_sig_bdd_86 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_845_pp0_it1)) | ((ap_ST_pp1_stg0_fsm_4 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it2) & ~(ap_sig_bdd_151 & (ap_const_logic_1 == ap_reg_ppiten_pp1_it1)) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_915_pp1_it1)))) begin
a_we0 = ap_const_logic_1;
end else begin
a_we0 = ap_const_logic_0;
end
end
/// a_we1 assign process. ///
always @ (ap_CS_fsm or ap_reg_ppiten_pp0_it0 or ap_sig_bdd_86 or ap_reg_ppiten_pp0_it1 or ap_reg_ppiten_pp0_it2 or ap_reg_ppstg_exitcond2_reg_845_pp0_it1 or ap_sig_bdd_119 or ap_reg_ppiten_pp1_it0 or ap_sig_bdd_151 or ap_reg_ppiten_pp1_it1 or ap_reg_ppiten_pp1_it2 or ap_reg_ppstg_exitcond_reg_915_pp1_it1 or ap_sig_bdd_183)
begin
if ((((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (ap_ST_pp0_stg1_fsm_3 == ap_CS_fsm) & ~((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ap_sig_bdd_119) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_845_pp0_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_ST_pp1_stg1_fsm_5 == ap_CS_fsm) & ~((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & ap_sig_bdd_183) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_915_pp1_it1)) | ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it2) & ~(ap_sig_bdd_86 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_845_pp0_it1)) | ((ap_ST_pp1_stg0_fsm_4 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it2) & ~(ap_sig_bdd_151 & (ap_const_logic_1 == ap_reg_ppiten_pp1_it1)) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_915_pp1_it1)))) begin
a_we1 = ap_const_logic_1;
end else begin
a_we1 = ap_const_logic_0;
end
end
/// ap_NS_fsm assign process. ///
always @ (ap_start or ap_CS_fsm or icmp_fu_281_p2 or tmp_2_fu_287_p2 or exitcond2_fu_327_p2 or ap_reg_ppiten_pp0_it0 or ap_sig_bdd_86 or ap_reg_ppiten_pp0_it1 or ap_reg_ppiten_pp0_it2 or ap_sig_bdd_119 or exitcond_fu_576_p2 or ap_reg_ppiten_pp1_it0 or ap_sig_bdd_151 or ap_reg_ppiten_pp1_it1 or ap_reg_ppiten_pp1_it2 or ap_sig_bdd_183)
begin
if (((ap_ST_pp1_stg0_fsm_4 == ap_CS_fsm) & ~(ap_sig_bdd_151 & (ap_const_logic_1 == ap_reg_ppiten_pp1_it1)) & ~((ap_ST_pp1_stg0_fsm_4 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it2) & ~(ap_sig_bdd_151 & (ap_const_logic_1 == ap_reg_ppiten_pp1_it1)) & ~(ap_const_logic_1 == ap_reg_ppiten_pp1_it1)) & ~((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & ~(ap_sig_bdd_151 & (ap_const_logic_1 == ap_reg_ppiten_pp1_it1)) & ~(ap_const_lv1_0 == exitcond_fu_576_p2) & ~(ap_const_logic_1 == ap_reg_ppiten_pp1_it1)))) begin
ap_NS_fsm = ap_ST_pp1_stg1_fsm_5;
end else if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & ~(ap_sig_bdd_86 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) & ~((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it2) & ~(ap_sig_bdd_86 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) & ~(ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) & ~((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ~(ap_sig_bdd_86 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) & ~(ap_const_lv1_0 == exitcond2_fu_327_p2) & ~(ap_const_logic_1 == ap_reg_ppiten_pp0_it1)))) begin
ap_NS_fsm = ap_ST_pp0_stg1_fsm_3;
end else if ((~(ap_const_logic_1 == ap_start) & (ap_ST_st12_fsm_6 == ap_CS_fsm))) begin
ap_NS_fsm = ap_ST_st0_fsm_0;
end else if ((((ap_ST_st1_fsm_1 == ap_CS_fsm) & ~(icmp_fu_281_p2 == ap_const_lv1_0)) | ((ap_ST_pp1_stg1_fsm_5 == ap_CS_fsm) & ~((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & ap_sig_bdd_183)))) begin
ap_NS_fsm = ap_ST_pp1_stg0_fsm_4;
end else if ((((ap_ST_st1_fsm_1 == ap_CS_fsm) & (icmp_fu_281_p2 == ap_const_lv1_0) & ~(ap_const_lv1_0 == tmp_2_fu_287_p2)) | ((ap_ST_pp0_stg1_fsm_3 == ap_CS_fsm) & ~((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ap_sig_bdd_119)))) begin
ap_NS_fsm = ap_ST_pp0_stg0_fsm_2;
end else if ((((ap_ST_st1_fsm_1 == ap_CS_fsm) & (icmp_fu_281_p2 == ap_const_lv1_0) & (ap_const_lv1_0 == tmp_2_fu_287_p2)) | ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it2) & ~(ap_sig_bdd_86 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) & ~(ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ~(ap_sig_bdd_86 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) & ~(ap_const_lv1_0 == exitcond2_fu_327_p2) & ~(ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | ((ap_ST_pp1_stg0_fsm_4 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it2) & ~(ap_sig_bdd_151 & (ap_const_logic_1 == ap_reg_ppiten_pp1_it1)) & ~(ap_const_logic_1 == ap_reg_ppiten_pp1_it1)) | ((ap_ST_pp1_stg0_fsm_4 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & ~(ap_sig_bdd_151 & (ap_const_logic_1 == ap_reg_ppiten_pp1_it1)) & ~(ap_const_lv1_0 == exitcond_fu_576_p2) & ~(ap_const_logic_1 == ap_reg_ppiten_pp1_it1)))) begin
ap_NS_fsm = ap_ST_st12_fsm_6;
end else if ((((ap_ST_st0_fsm_0 == ap_CS_fsm) & (ap_const_logic_1 == ap_start)) | ((ap_const_logic_1 == ap_start) & (ap_ST_st12_fsm_6 == ap_CS_fsm)))) begin
ap_NS_fsm = ap_ST_st1_fsm_1;
end else begin
ap_NS_fsm = ap_CS_fsm;
end
end
/// ap_done assign process. ///
always @ (ap_CS_fsm)
begin
if (((ap_ST_st0_fsm_0 == ap_CS_fsm) | (ap_ST_st12_fsm_6 == ap_CS_fsm))) begin
ap_done = ap_const_logic_1;
end else begin
ap_done = ap_const_logic_0;
end
end
/// ap_idle assign process. ///
always @ (ap_CS_fsm)
begin
if ((ap_ST_st0_fsm_0 == ap_CS_fsm)) begin
ap_idle = ap_const_logic_1;
end else begin
ap_idle = ap_const_logic_0;
end
end
/// i_1_phi_fu_239_p4 assign process. ///
always @ (ap_CS_fsm or i_1_reg_235 or exitcond_reg_915 or ap_reg_ppiten_pp1_it1 or i_1_mid2_reg_933)
begin
if (((ap_ST_pp1_stg0_fsm_4 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond_reg_915) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it1))) begin
i_1_phi_fu_239_p4 = i_1_mid2_reg_933;
end else begin
i_1_phi_fu_239_p4 = i_1_reg_235;
end
end
/// i_phi_fu_195_p4 assign process. ///
always @ (ap_CS_fsm or i_reg_191 or exitcond2_reg_845 or ap_reg_ppiten_pp0_it1 or i_mid2_reg_863)
begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond2_reg_845) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1))) begin
i_phi_fu_195_p4 = i_mid2_reg_863;
end else begin
i_phi_fu_195_p4 = i_reg_191;
end
end
/// indvar1_phi_fu_206_p4 assign process. ///
always @ (ap_CS_fsm or indvar1_reg_202 or exitcond2_reg_845 or ap_reg_ppiten_pp0_it1 or indvar_next1_reg_874)
begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond2_reg_845) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1))) begin
indvar1_phi_fu_206_p4 = indvar_next1_reg_874;
end else begin
indvar1_phi_fu_206_p4 = indvar1_reg_202;
end
end
/// indvar_flatten1_phi_fu_228_p4 assign process. ///
always @ (ap_CS_fsm or indvar_flatten1_reg_224 or exitcond_reg_915 or ap_reg_ppiten_pp1_it1 or indvar_flatten_next1_reg_919)
begin
if (((ap_ST_pp1_stg0_fsm_4 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond_reg_915) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it1))) begin
indvar_flatten1_phi_fu_228_p4 = indvar_flatten_next1_reg_919;
end else begin
indvar_flatten1_phi_fu_228_p4 = indvar_flatten1_reg_224;
end
end
/// indvar_flatten_phi_fu_184_p4 assign process. ///
always @ (ap_CS_fsm or indvar_flatten_reg_180 or exitcond2_reg_845 or ap_reg_ppiten_pp0_it1 or indvar_flatten_next_reg_849)
begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond2_reg_845) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1))) begin
indvar_flatten_phi_fu_184_p4 = indvar_flatten_next_reg_849;
end else begin
indvar_flatten_phi_fu_184_p4 = indvar_flatten_reg_180;
end
end
/// indvar_phi_fu_250_p4 assign process. ///
always @ (ap_CS_fsm or indvar_reg_246 or exitcond_reg_915 or ap_reg_ppiten_pp1_it1 or indvar_next_reg_944)
begin
if (((ap_ST_pp1_stg0_fsm_4 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond_reg_915) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it1))) begin
indvar_phi_fu_250_p4 = indvar_next_reg_944;
end else begin
indvar_phi_fu_250_p4 = indvar_reg_246;
end
end
/// j_1_phi_fu_261_p4 assign process. ///
always @ (ap_CS_fsm or j_1_reg_257 or exitcond_reg_915 or ap_reg_ppiten_pp1_it1 or tmp_13_fu_723_p2)
begin
if (((ap_ST_pp1_stg0_fsm_4 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond_reg_915) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it1))) begin
j_1_phi_fu_261_p4 = tmp_13_fu_723_p2;
end else begin
j_1_phi_fu_261_p4 = j_1_reg_257;
end
end
/// j_phi_fu_217_p4 assign process. ///
always @ (ap_CS_fsm or j_reg_213 or exitcond2_reg_845 or ap_reg_ppiten_pp0_it1 or tmp_25_fu_470_p2)
begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond2_reg_845) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1))) begin
j_phi_fu_217_p4 = tmp_25_fu_470_p2;
end else begin
j_phi_fu_217_p4 = j_reg_213;
end
end
assign V_bus_dataout = ap_const_lv128_lc_1;
assign V_bus_req_din = ap_const_logic_0;
assign V_bus_size = ap_const_lv32_0;
assign a_addr1_fu_819_p2 = (a_addr9_cast_reg_979 + tmp_15_trn_cast_fu_815_p1);
assign a_addr2_cast_fu_491_p1 = {{1{1'b0}}, {a_addr2_fu_485_p2}};
assign a_addr2_fu_485_p2 = tmp_4_trn_cast_fu_479_p1 << ap_const_lv13_6;
assign a_addr3_fu_495_p2 = (a_addr2_cast_fu_491_p1 + tmp_22_trn_cast_fu_482_p1);
assign a_addr4_fu_796_p2 = (a_addr9_cast_reg_979 + tmp_13_trn_cast_fu_792_p1);
assign a_addr5_fu_519_p2 = (a_addr2_cast_fu_491_p1 + tmp_24_trn_cast_fu_515_p1);
assign a_addr6_fu_543_p2 = (a_addr2_cast_reg_909 + tmp_26_trn_cast_fu_539_p1);
assign a_addr7_fu_772_p2 = (a_addr9_cast_fu_744_p1 + tmp_11_trn_cast_fu_768_p1);
assign a_addr8_fu_566_p2 = (a_addr2_cast_reg_909 + tmp_28_trn_cast_fu_562_p1);
assign a_addr9_cast_fu_744_p1 = {{1{1'b0}}, {a_addr9_fu_738_p2}};
assign a_addr9_fu_738_p2 = tmp_3_trn8_cast_fu_732_p1 << ap_const_lv13_6;
assign a_addr_fu_748_p2 = (a_addr9_cast_fu_744_p1 + tmp_trn_cast_fu_735_p1);
/// ap_sig_bdd_119 assign process. ///
always @ (V_bus_req_full_n or exitcond2_reg_845)
begin
ap_sig_bdd_119 = ((ap_const_lv1_0 == exitcond2_reg_845) & (V_bus_req_full_n == ap_const_logic_0));
end
/// ap_sig_bdd_151 assign process. ///
always @ (V_bus_rsp_empty_n or exitcond_reg_915)
begin
ap_sig_bdd_151 = ((V_bus_rsp_empty_n == ap_const_logic_0) & (ap_const_lv1_0 == exitcond_reg_915));
end
/// ap_sig_bdd_183 assign process. ///
always @ (V_bus_req_full_n or exitcond_reg_915)
begin
ap_sig_bdd_183 = ((V_bus_req_full_n == ap_const_logic_0) & (ap_const_lv1_0 == exitcond_reg_915));
end
/// ap_sig_bdd_86 assign process. ///
always @ (V_bus_rsp_empty_n or exitcond2_reg_845)
begin
ap_sig_bdd_86 = ((V_bus_rsp_empty_n == ap_const_logic_0) & (ap_const_lv1_0 == exitcond2_reg_845));
end
assign counter_cast2_fu_307_p1 = {{12{1'b0}}, {counter}};
assign counter_cast_fu_293_p1 = {{12{1'b0}}, {counter}};
assign exitcond1_fu_588_p2 = (indvar_phi_fu_250_p4 == ap_const_lv5_10? 1'b1: 1'b0);
assign exitcond2_fu_327_p2 = (indvar_flatten_phi_fu_184_p4 == ap_const_lv11_400? 1'b1: 1'b0);
assign exitcond3_fu_339_p2 = (indvar1_phi_fu_206_p4 == ap_const_lv5_10? 1'b1: 1'b0);
assign exitcond_fu_576_p2 = (indvar_flatten1_phi_fu_228_p4 == ap_const_lv11_400? 1'b1: 1'b0);
assign i_1_cast_fu_624_p1 = {{6{1'b0}}, {i_1_mid2_fu_616_p3}};
assign i_1_mid2_fu_616_p3 = ((exitcond1_fu_588_p2)? tmp_5_dup_fu_610_p2: i_1_phi_fu_239_p4);
assign i_cast_fu_375_p1 = {{6{1'b0}}, {i_mid2_fu_367_p3}};
assign i_mid2_fu_367_p3 = ((exitcond3_fu_339_p2)? tmp_17_dup_fu_361_p2: i_phi_fu_195_p4);
assign icmp_fu_281_p2 = (tmp_8_fu_277_p1 == ap_const_lv2_1? 1'b1: 1'b0);
assign indvar1_cast_fu_385_p1 = {{2{1'b0}}, {indvar1_mid2_fu_345_p3}};
assign indvar1_mid2_fu_345_p3 = ((exitcond3_fu_339_p2)? ap_const_lv5_0: indvar1_phi_fu_206_p4);
assign indvar_cast_fu_634_p1 = {{2{1'b0}}, {indvar_mid2_fu_594_p3}};
assign indvar_mid2_fu_594_p3 = ((exitcond1_fu_588_p2)? ap_const_lv5_0: indvar_phi_fu_250_p4);
assign tmp10_fu_811_p1 = p_3_reg_969;
assign tmp11_cast_fu_405_p1 = {{7{1'b0}}, {tmp11_fu_399_p2}};
assign tmp11_fu_399_p2 = (tmp6_fu_379_p2 + tmp7_cast_fu_395_p1);
assign tmp12_fu_535_p1 = p_5_reg_894;
assign tmp13_fu_409_p2 = (tmp11_cast_fu_405_p1 + tmp3_cast_reg_835);
assign tmp14_fu_788_p1 = p_2_reg_964;
assign tmp15_fu_728_p1 = tmp_9_reg_954;
assign tmp16_fu_511_p1 = p_4_reg_889;
assign tmp17_fu_764_p1 = p_1_reg_959;
assign tmp18_fu_475_p1 = tmp_17_reg_884;
assign tmp1_cast_fu_317_p1 = {{1{1'b0}}, {tmp1_fu_311_p2}};
assign tmp1_fu_311_p2 = counter_cast2_fu_307_p1 << ap_const_lv19_C;
assign tmp2_fu_321_p2 = (ap_const_lv20_3F000 - tmp1_cast_fu_317_p1);
assign tmp3_cast_fu_303_p1 = {{1{1'b0}}, {tmp3_fu_297_p2}};
assign tmp3_fu_297_p2 = counter_cast_fu_293_p1 << ap_const_lv19_C;
assign tmp4_fu_628_p2 = i_1_cast_fu_624_p1 << ap_const_lv13_6;
assign tmp5_cast_cast_fu_654_p1 = {{7{1'b0}}, {tmp5_fu_648_p2}};
assign tmp5_fu_648_p2 = (tmp4_fu_628_p2 + tmp_cast_fu_644_p1);
assign tmp6_fu_379_p2 = i_cast_fu_375_p1 << ap_const_lv13_6;
assign tmp7_cast_fu_395_p1 = {{6{1'b0}}, {tmp7_fu_389_p2}};
assign tmp7_fu_389_p2 = indvar1_cast_fu_385_p1 << ap_const_lv7_2;
assign tmp8_fu_558_p1 = p_6_reg_899;
assign tmp9_fu_658_p2 = (tmp5_cast_cast_fu_654_p1 + tmp2_reg_840);
assign tmp_10_fu_801_p1 = {{50{1'b0}}, {a_addr4_fu_796_p2}};
assign tmp_11_fu_806_p2 = (ap_reg_ppstg_j_1_mid2_reg_924_pp1_it1 | ap_const_lv7_3);
assign tmp_11_trn_cast_fu_768_p1 = {{7{1'b0}}, {tmp_s_fu_759_p2}};
assign tmp_12_fu_824_p1 = {{50{1'b0}}, {a_addr1_fu_819_p2}};
assign tmp_13_fu_723_p2 = (j_1_mid2_reg_924 + ap_const_lv7_4);
assign tmp_13_trn_cast_fu_792_p1 = {{7{1'b0}}, {tmp_5_fu_783_p2}};
assign tmp_15_fu_420_p2 = tmp13_reg_869 >> ap_const_lv20_2;
assign tmp_15_trn_cast_fu_815_p1 = {{7{1'b0}}, {tmp_11_fu_806_p2}};
assign tmp_16_fu_425_p1 = {{44{1'b0}}, {tmp_15_fu_420_p2}};
assign tmp_17_dup_fu_361_p2 = (i_phi_fu_195_p4 + ap_const_lv7_1);
assign tmp_18_fu_501_p1 = {{50{1'b0}}, {a_addr3_fu_495_p2}};
assign tmp_19_fu_506_p2 = (ap_reg_ppstg_j_mid2_reg_854_pp0_it1 | ap_const_lv7_1);
assign tmp_1_fu_269_p3 = counter[ap_const_lv32_6];
assign tmp_20_fu_525_p1 = {{50{1'b0}}, {a_addr5_fu_519_p2}};
assign tmp_21_fu_530_p2 = (ap_reg_ppstg_j_mid2_reg_854_pp0_it1 | ap_const_lv7_2);
assign tmp_22_fu_548_p1 = {{50{1'b0}}, {a_addr6_fu_543_p2}};
assign tmp_22_trn_cast_fu_482_p1 = {{7{1'b0}}, {ap_reg_ppstg_j_mid2_reg_854_pp0_it1}};
assign tmp_23_fu_553_p2 = (ap_reg_ppstg_j_mid2_reg_854_pp0_it1 | ap_const_lv7_3);
assign tmp_24_fu_571_p1 = {{50{1'b0}}, {a_addr8_fu_566_p2}};
assign tmp_24_trn_cast_fu_515_p1 = {{7{1'b0}}, {tmp_19_fu_506_p2}};
assign tmp_25_fu_470_p2 = (j_mid2_reg_854 + ap_const_lv7_4);
assign tmp_26_trn_cast_fu_539_p1 = {{7{1'b0}}, {tmp_21_fu_530_p2}};
assign tmp_28_trn_cast_fu_562_p1 = {{7{1'b0}}, {tmp_23_fu_553_p2}};
assign tmp_2_fu_287_p2 = (tag == ap_const_lv2_0? 1'b1: 1'b0);
assign tmp_3_fu_754_p1 = {{50{1'b0}}, {a_addr_fu_748_p2}};
assign tmp_3_trn8_cast_fu_732_p1 = {{6{1'b0}}, {ap_reg_ppstg_i_1_mid2_reg_933_pp1_it1}};
assign tmp_4_fu_778_p1 = {{50{1'b0}}, {a_addr7_fu_772_p2}};
assign tmp_4_trn_cast_fu_479_p1 = {{6{1'b0}}, {ap_reg_ppstg_i_mid2_reg_863_pp0_it1}};
assign tmp_5_dup_fu_610_p2 = (i_1_phi_fu_239_p4 + ap_const_lv7_1);
assign tmp_5_fu_783_p2 = (ap_reg_ppstg_j_1_mid2_reg_924_pp1_it1 | ap_const_lv7_2);
assign tmp_7_fu_679_p1 = {{46{tmp_26_reg_939[17]}}, {tmp_26_reg_939}};
assign tmp_8_fu_277_p1 = {{1{1'b0}}, {tmp_1_fu_269_p3}};
assign tmp_cast_fu_644_p1 = {{6{1'b0}}, {tmp_fu_638_p2}};
assign tmp_fu_638_p2 = indvar_cast_fu_634_p1 << ap_const_lv7_2;
assign tmp_s_fu_759_p2 = (ap_reg_ppstg_j_1_mid2_reg_924_pp1_it1 | ap_const_lv7_1);
assign tmp_trn_cast_fu_735_p1 = {{7{1'b0}}, {ap_reg_ppstg_j_1_mid2_reg_924_pp1_it1}};
always @ (ap_clk)
begin
tmp3_cast_reg_835[0] <= 1'b0;
tmp3_cast_reg_835[1] <= 1'b0;
tmp3_cast_reg_835[2] <= 1'b0;
tmp3_cast_reg_835[3] <= 1'b0;
tmp3_cast_reg_835[4] <= 1'b0;
tmp3_cast_reg_835[5] <= 1'b0;
tmp3_cast_reg_835[6] <= 1'b0;
tmp3_cast_reg_835[7] <= 1'b0;
tmp3_cast_reg_835[8] <= 1'b0;
tmp3_cast_reg_835[9] <= 1'b0;
tmp3_cast_reg_835[10] <= 1'b0;
tmp3_cast_reg_835[11] <= 1'b0;
tmp3_cast_reg_835[19] <= 1'b0;
end
always @ (ap_clk)
begin
tmp2_reg_840[0] <= 1'b0;
tmp2_reg_840[1] <= 1'b0;
tmp2_reg_840[2] <= 1'b0;
tmp2_reg_840[3] <= 1'b0;
tmp2_reg_840[4] <= 1'b0;
tmp2_reg_840[5] <= 1'b0;
tmp2_reg_840[6] <= 1'b0;
tmp2_reg_840[7] <= 1'b0;
tmp2_reg_840[8] <= 1'b0;
tmp2_reg_840[9] <= 1'b0;
tmp2_reg_840[10] <= 1'b0;
tmp2_reg_840[11] <= 1'b0;
end
always @ (ap_clk)
begin
tmp13_reg_869[0] <= 1'b0;
tmp13_reg_869[1] <= 1'b0;
end
always @ (ap_clk)
begin
a_addr2_cast_reg_909[0] <= 1'b0;
a_addr2_cast_reg_909[1] <= 1'b0;
a_addr2_cast_reg_909[2] <= 1'b0;
a_addr2_cast_reg_909[3] <= 1'b0;
a_addr2_cast_reg_909[4] <= 1'b0;
a_addr2_cast_reg_909[5] <= 1'b0;
a_addr2_cast_reg_909[13] <= 1'b0;
end
always @ (ap_clk)
begin
a_addr9_cast_reg_979[0] <= 1'b0;
a_addr9_cast_reg_979[1] <= 1'b0;
a_addr9_cast_reg_979[2] <= 1'b0;
a_addr9_cast_reg_979[3] <= 1'b0;
a_addr9_cast_reg_979[4] <= 1'b0;
a_addr9_cast_reg_979[5] <= 1'b0;
a_addr9_cast_reg_979[13] <= 1'b0;
end
endmodule //fetch
|
// ==============================================================
// RTL generated by AutoESL - High-Level Synthesis System (C, C++, SystemC)
// Version: 2011.1
// Copyright (C) 2011 Xilinx Inc. All rights reserved.
//
// ===========================================================
`timescale 1 ns / 1 ps
module Gaussianblur (
ap_clk,
ap_rst,
ap_start,
ap_done,
ap_idle,
V1_bus_req_din,
V1_bus_req_full_n,
V1_bus_req_write,
V1_bus_rsp_dout,
V1_bus_rsp_empty_n,
V1_bus_rsp_read,
V1_bus_address,
V1_bus_datain,
V1_bus_dataout,
V1_bus_size,
V2_bus_req_din,
V2_bus_req_full_n,
V2_bus_req_write,
V2_bus_rsp_dout,
V2_bus_rsp_empty_n,
V2_bus_rsp_read,
V2_bus_address,
V2_bus_datain,
V2_bus_dataout,
V2_bus_size,
std
);
input ap_clk;
input ap_rst;
input ap_start;
output ap_done;
output ap_idle;
output V1_bus_req_din;
input V1_bus_req_full_n;
output V1_bus_req_write;
input V1_bus_rsp_dout;
input V1_bus_rsp_empty_n;
output V1_bus_rsp_read;
output [31:0] V1_bus_address;
input [127:0] V1_bus_datain;
output [127:0] V1_bus_dataout;
output [31:0] V1_bus_size;
output V2_bus_req_din;
input V2_bus_req_full_n;
output V2_bus_req_write;
input V2_bus_rsp_dout;
input V2_bus_rsp_empty_n;
output V2_bus_rsp_read;
output [31:0] V2_bus_address;
input [127:0] V2_bus_datain;
output [127:0] V2_bus_dataout;
output [31:0] V2_bus_size;
input [31:0] std;
reg ap_done;
reg ap_idle;
reg [6:0] ap_CS_fsm;
wire [31:0] grp_fu_226_p2;
reg [31:0] reg_250;
wire [31:0] grp_fu_235_p2;
reg [31:0] reg_258;
wire [31:0] grp_fu_220_p2;
reg [31:0] reg_266;
wire [31:0] grp_fu_245_p2;
reg [31:0] tmp_5_reg_320;
reg [31:0] nu_reg_325;
wire [31:0] grp_fu_241_p2;
reg [31:0] tmp_8_reg_333;
reg [1:0] tmp_s_reg_341;
reg [1:0] tmp_10_reg_349;
reg [6:0] tmp_11_reg_357;
reg [11:0] a0_address0;
reg a0_ce0;
reg a0_we0;
reg [31:0] a0_d0;
wire [31:0] a0_q0;
reg [11:0] a0_address1;
reg a0_ce1;
reg a0_we1;
reg [31:0] a0_d1;
wire [31:0] a0_q1;
reg [11:0] a1_address0;
reg a1_ce0;
reg a1_we0;
reg [31:0] a1_d0;
wire [31:0] a1_q0;
reg [11:0] a1_address1;
reg a1_ce1;
reg a1_we1;
reg [31:0] a1_d1;
wire [31:0] a1_q1;
reg [11:0] b0_address0;
reg b0_ce0;
reg b0_we0;
wire [31:0] b0_d0;
wire [31:0] b0_q0;
reg [11:0] b0_address1;
reg b0_ce1;
reg b0_we1;
wire [31:0] b0_d1;
wire [31:0] b0_q1;
reg [11:0] b1_address0;
reg b1_ce0;
reg b1_we0;
wire [31:0] b1_d0;
wire [31:0] b1_q0;
reg [11:0] b1_address1;
reg b1_ce1;
reg b1_we1;
wire [31:0] b1_d1;
wire [31:0] b1_q1;
reg [11:0] c0_address0;
reg c0_ce0;
reg c0_we0;
wire [31:0] c0_d0;
wire [31:0] c0_q0;
reg [11:0] c0_address1;
reg c0_ce1;
reg c0_we1;
wire [31:0] c0_d1;
wire [31:0] c0_q1;
reg [11:0] c1_address0;
reg c1_ce0;
reg c1_we0;
wire [31:0] c1_d0;
wire [31:0] c1_q0;
reg [11:0] c1_address1;
reg c1_ce1;
reg c1_we1;
wire [31:0] c1_d1;
wire [31:0] c1_q1;
reg [11:0] d0_address0;
reg d0_ce0;
reg d0_we0;
wire [31:0] d0_d0;
wire [31:0] d0_q0;
reg [11:0] d0_address1;
reg d0_ce1;
reg d0_we1;
wire [31:0] d0_d1;
wire [31:0] d0_q1;
reg [11:0] d1_address0;
reg d1_ce0;
reg d1_we0;
wire [31:0] d1_d0;
wire [31:0] d1_q0;
reg [11:0] d1_address1;
reg d1_ce1;
reg d1_we1;
wire [31:0] d1_d1;
wire [31:0] d1_q1;
reg grp_step0_fu_168_ap_start;
wire grp_step0_fu_168_ap_done;
wire grp_step0_fu_168_ap_idle;
wire [1:0] grp_step0_fu_168_tag;
wire [6:0] grp_step0_fu_168_counter;
wire [11:0] grp_step0_fu_168_a_address0;
wire grp_step0_fu_168_a_ce0;
wire grp_step0_fu_168_a_we0;
wire [31:0] grp_step0_fu_168_a_d0;
reg [31:0] grp_step0_fu_168_a_q0;
wire [11:0] grp_step0_fu_168_a_address1;
wire grp_step0_fu_168_a_ce1;
wire grp_step0_fu_168_a_we1;
wire [31:0] grp_step0_fu_168_a_d1;
reg [31:0] grp_step0_fu_168_a_q1;
wire [11:0] grp_step0_fu_168_b_address0;
wire grp_step0_fu_168_b_ce0;
wire grp_step0_fu_168_b_we0;
wire [31:0] grp_step0_fu_168_b_d0;
reg [31:0] grp_step0_fu_168_b_q0;
wire [11:0] grp_step0_fu_168_b_address1;
wire grp_step0_fu_168_b_ce1;
wire grp_step0_fu_168_b_we1;
wire [31:0] grp_step0_fu_168_b_d1;
reg [31:0] grp_step0_fu_168_b_q1;
wire [31:0] grp_step0_fu_168_BoundryScale;
wire [31:0] grp_step0_fu_168_nu;
reg grp_step1_fu_180_ap_start;
wire grp_step1_fu_180_ap_done;
wire grp_step1_fu_180_ap_idle;
wire [0:0] grp_step1_fu_180_step;
wire [1:0] grp_step1_fu_180_tag;
wire [6:0] grp_step1_fu_180_counter;
wire [11:0] grp_step1_fu_180_c_address0;
wire grp_step1_fu_180_c_ce0;
reg [31:0] grp_step1_fu_180_c_q0;
wire [11:0] grp_step1_fu_180_c_address1;
wire grp_step1_fu_180_c_ce1;
reg [31:0] grp_step1_fu_180_c_q1;
wire [11:0] grp_step1_fu_180_b_address0;
wire grp_step1_fu_180_b_ce0;
reg [31:0] grp_step1_fu_180_b_q0;
wire [11:0] grp_step1_fu_180_b_address1;
wire grp_step1_fu_180_b_ce1;
reg [31:0] grp_step1_fu_180_b_q1;
wire [11:0] grp_step1_fu_180_d_address0;
wire grp_step1_fu_180_d_ce0;
wire grp_step1_fu_180_d_we0;
wire [31:0] grp_step1_fu_180_d_d0;
wire [11:0] grp_step1_fu_180_d_address1;
wire grp_step1_fu_180_d_ce1;
wire grp_step1_fu_180_d_we1;
wire [31:0] grp_step1_fu_180_d_d1;
wire [11:0] grp_step1_fu_180_c1_address0;
wire grp_step1_fu_180_c1_ce0;
wire grp_step1_fu_180_c1_we0;
wire [31:0] grp_step1_fu_180_c1_d0;
wire [11:0] grp_step1_fu_180_c1_address1;
wire grp_step1_fu_180_c1_ce1;
wire grp_step1_fu_180_c1_we1;
wire [31:0] grp_step1_fu_180_c1_d1;
wire [31:0] grp_step1_fu_180_BoundryScale;
wire [31:0] grp_step1_fu_180_nu;
wire [31:0] grp_step1_fu_180_PostScale;
reg grp_write_r_fu_198_ap_start;
wire grp_write_r_fu_198_ap_done;
wire grp_write_r_fu_198_ap_idle;
wire [1:0] grp_write_r_fu_198_tag;
wire [6:0] grp_write_r_fu_198_counter;
wire [11:0] grp_write_r_fu_198_d_address0;
wire grp_write_r_fu_198_d_ce0;
reg [31:0] grp_write_r_fu_198_d_q0;
wire [11:0] grp_write_r_fu_198_d_address1;
wire grp_write_r_fu_198_d_ce1;
reg [31:0] grp_write_r_fu_198_d_q1;
wire grp_write_r_fu_198_V_bus_req_din;
wire grp_write_r_fu_198_V_bus_req_full_n;
wire grp_write_r_fu_198_V_bus_req_write;
wire grp_write_r_fu_198_V_bus_rsp_dout;
wire grp_write_r_fu_198_V_bus_rsp_empty_n;
wire grp_write_r_fu_198_V_bus_rsp_read;
wire [31:0] grp_write_r_fu_198_V_bus_address;
wire [127:0] grp_write_r_fu_198_V_bus_datain;
wire [127:0] grp_write_r_fu_198_V_bus_dataout;
wire [31:0] grp_write_r_fu_198_V_bus_size;
reg grp_fetch_fu_209_ap_start;
wire grp_fetch_fu_209_ap_done;
wire grp_fetch_fu_209_ap_idle;
wire [1:0] grp_fetch_fu_209_tag;
wire [6:0] grp_fetch_fu_209_counter;
wire [11:0] grp_fetch_fu_209_a_address0;
wire grp_fetch_fu_209_a_ce0;
wire grp_fetch_fu_209_a_we0;
wire [31:0] grp_fetch_fu_209_a_d0;
wire [11:0] grp_fetch_fu_209_a_address1;
wire grp_fetch_fu_209_a_ce1;
wire grp_fetch_fu_209_a_we1;
wire [31:0] grp_fetch_fu_209_a_d1;
wire grp_fetch_fu_209_V_bus_req_din;
wire grp_fetch_fu_209_V_bus_req_full_n;
wire grp_fetch_fu_209_V_bus_req_write;
wire grp_fetch_fu_209_V_bus_rsp_dout;
wire grp_fetch_fu_209_V_bus_rsp_empty_n;
wire grp_fetch_fu_209_V_bus_rsp_read;
wire [31:0] grp_fetch_fu_209_V_bus_address;
wire [127:0] grp_fetch_fu_209_V_bus_datain;
wire [127:0] grp_fetch_fu_209_V_bus_dataout;
wire [31:0] grp_fetch_fu_209_V_bus_size;
reg [1:0] i_reg_104;
reg [31:0] PostScale_reg_115;
wire [0:0] indvar_phi_fu_132_p4;
reg [0:0] indvar_reg_127;
wire [0:0] exitcond1_fu_274_p2;
wire [0:0] exitcond_fu_286_p2;
reg [1:0] tag_reg_141;
wire [0:0] exitcond2_fu_298_p2;
reg [6:0] counter_reg_153;
wire [0:0] tmp_12_fu_310_p1;
reg [31:0] grp_fu_220_p0;
reg [31:0] grp_fu_220_p1;
reg [31:0] grp_fu_226_p0;
reg [31:0] grp_fu_226_p1;
reg [31:0] grp_fu_235_p0;
reg [31:0] grp_fu_235_p1;
wire [31:0] grp_fu_241_p0;
wire [31:0] grp_fu_241_p1;
wire [31:0] grp_fu_245_p1;
reg [1:0] grp_fu_220_opcode;
wire grp_fu_220_ce;
reg grp_fu_226_ce;
wire grp_fu_235_ce;
wire grp_fu_241_ce;
wire [31:0] grp_fu_245_p0;
wire grp_fu_245_ce;
reg [6:0] ap_NS_fsm;
parameter ap_const_logic_1 = 1'b1;
parameter ap_const_logic_0 = 1'b0;
parameter ap_ST_st0_fsm_0 = 7'b0000000;
parameter ap_ST_st1_fsm_1 = 7'b0000001;
parameter ap_ST_st2_fsm_2 = 7'b0000010;
parameter ap_ST_st3_fsm_3 = 7'b0000011;
parameter ap_ST_st4_fsm_4 = 7'b0000100;
parameter ap_ST_st5_fsm_5 = 7'b0000101;
parameter ap_ST_st6_fsm_6 = 7'b0000110;
parameter ap_ST_st7_fsm_7 = 7'b0000111;
parameter ap_ST_st8_fsm_8 = 7'b0001000;
parameter ap_ST_st9_fsm_9 = 7'b0001001;
parameter ap_ST_st10_fsm_10 = 7'b0001010;
parameter ap_ST_st11_fsm_11 = 7'b0001011;
parameter ap_ST_st12_fsm_12 = 7'b0001100;
parameter ap_ST_st13_fsm_13 = 7'b0001101;
parameter ap_ST_st14_fsm_14 = 7'b0001110;
parameter ap_ST_st15_fsm_15 = 7'b0001111;
parameter ap_ST_st16_fsm_16 = 7'b0010000;
parameter ap_ST_st17_fsm_17 = 7'b0010001;
parameter ap_ST_st18_fsm_18 = 7'b0010010;
parameter ap_ST_st19_fsm_19 = 7'b0010011;
parameter ap_ST_st20_fsm_20 = 7'b0010100;
parameter ap_ST_st21_fsm_21 = 7'b0010101;
parameter ap_ST_st22_fsm_22 = 7'b0010110;
parameter ap_ST_st23_fsm_23 = 7'b0010111;
parameter ap_ST_st24_fsm_24 = 7'b0011000;
parameter ap_ST_st25_fsm_25 = 7'b0011001;
parameter ap_ST_st26_fsm_26 = 7'b0011010;
parameter ap_ST_st27_fsm_27 = 7'b0011011;
parameter ap_ST_st28_fsm_28 = 7'b0011100;
parameter ap_ST_st29_fsm_29 = 7'b0011101;
parameter ap_ST_st30_fsm_30 = 7'b0011110;
parameter ap_ST_st31_fsm_31 = 7'b0011111;
parameter ap_ST_st32_fsm_32 = 7'b0100000;
parameter ap_ST_st33_fsm_33 = 7'b0100001;
parameter ap_ST_st34_fsm_34 = 7'b0100010;
parameter ap_ST_st35_fsm_35 = 7'b0100011;
parameter ap_ST_st36_fsm_36 = 7'b0100100;
parameter ap_ST_st37_fsm_37 = 7'b0100101;
parameter ap_ST_st38_fsm_38 = 7'b0100110;
parameter ap_ST_st39_fsm_39 = 7'b0100111;
parameter ap_ST_st40_fsm_40 = 7'b0101000;
parameter ap_ST_st41_fsm_41 = 7'b0101001;
parameter ap_ST_st42_fsm_42 = 7'b0101010;
parameter ap_ST_st43_fsm_43 = 7'b0101011;
parameter ap_ST_st44_fsm_44 = 7'b0101100;
parameter ap_ST_st45_fsm_45 = 7'b0101101;
parameter ap_ST_st46_fsm_46 = 7'b0101110;
parameter ap_ST_st47_fsm_47 = 7'b0101111;
parameter ap_ST_st48_fsm_48 = 7'b0110000;
parameter ap_ST_st49_fsm_49 = 7'b0110001;
parameter ap_ST_st50_fsm_50 = 7'b0110010;
parameter ap_ST_st51_fsm_51 = 7'b0110011;
parameter ap_ST_st52_fsm_52 = 7'b0110100;
parameter ap_ST_st53_fsm_53 = 7'b0110101;
parameter ap_ST_st54_fsm_54 = 7'b0110110;
parameter ap_ST_st55_fsm_55 = 7'b0110111;
parameter ap_ST_st56_fsm_56 = 7'b0111000;
parameter ap_ST_st57_fsm_57 = 7'b0111001;
parameter ap_ST_st58_fsm_58 = 7'b0111010;
parameter ap_ST_st59_fsm_59 = 7'b0111011;
parameter ap_ST_st60_fsm_60 = 7'b0111100;
parameter ap_ST_st61_fsm_61 = 7'b0111101;
parameter ap_ST_st62_fsm_62 = 7'b0111110;
parameter ap_ST_st63_fsm_63 = 7'b0111111;
parameter ap_ST_st64_fsm_64 = 7'b1000000;
parameter ap_ST_st65_fsm_65 = 7'b1000001;
parameter ap_ST_st66_fsm_66 = 7'b1000010;
parameter ap_ST_st67_fsm_67 = 7'b1000011;
parameter ap_ST_st68_fsm_68 = 7'b1000100;
parameter ap_ST_st69_fsm_69 = 7'b1000101;
parameter ap_ST_st70_fsm_70 = 7'b1000110;
parameter ap_ST_st71_fsm_71 = 7'b1000111;
parameter ap_ST_st72_fsm_72 = 7'b1001000;
parameter ap_const_lv2_0 = 2'b00;
parameter ap_const_lv32_3F800000 = 32'b00111111100000000000000000000000;
parameter ap_const_lv1_0 = 1'b0;
parameter ap_const_lv1_1 = 1'b1;
parameter ap_const_lv7_0 = 7'b0000000;
parameter ap_const_lv32_40800000 = 32'b01000000100000000000000000000000;
parameter ap_const_lv32_40000000 = 32'b01000000000000000000000000000000;
parameter ap_const_lv2_3 = 2'b11;
parameter ap_const_lv2_1 = 2'b01;
parameter ap_const_lv2_2 = 2'b10;
parameter ap_const_lv7_43 = 7'b1000011;
parameter ap_const_lv7_1 = 7'b0000001;
parameter ap_const_lv32_1 = 32'b00000000000000000000000000000001;
parameter ap_true = 1'b1;
Gaussianblur_a0 #(
.DataWidth( 32 ),
.AddressRange( 4096 ),
.AddressWidth( 12 ))
a0_U(
.clk( ap_clk ),
.address0( a0_address0 ),
.ce0( a0_ce0 ),
.we0( a0_we0 ),
.d0( a0_d0 ),
.q0( a0_q0 ),
.address1( a0_address1 ),
.ce1( a0_ce1 ),
.we1( a0_we1 ),
.d1( a0_d1 ),
.q1( a0_q1 )
);
Gaussianblur_a1 #(
.DataWidth( 32 ),
.AddressRange( 4096 ),
.AddressWidth( 12 ))
a1_U(
.clk( ap_clk ),
.address0( a1_address0 ),
.ce0( a1_ce0 ),
.we0( a1_we0 ),
.d0( a1_d0 ),
.q0( a1_q0 ),
.address1( a1_address1 ),
.ce1( a1_ce1 ),
.we1( a1_we1 ),
.d1( a1_d1 ),
.q1( a1_q1 )
);
Gaussianblur_b0 #(
.DataWidth( 32 ),
.AddressRange( 4096 ),
.AddressWidth( 12 ))
b0_U(
.clk( ap_clk ),
.address0( b0_address0 ),
.ce0( b0_ce0 ),
.we0( b0_we0 ),
.d0( b0_d0 ),
.q0( b0_q0 ),
.address1( b0_address1 ),
.ce1( b0_ce1 ),
.we1( b0_we1 ),
.d1( b0_d1 ),
.q1( b0_q1 )
);
Gaussianblur_b1 #(
.DataWidth( 32 ),
.AddressRange( 4096 ),
.AddressWidth( 12 ))
b1_U(
.clk( ap_clk ),
.address0( b1_address0 ),
.ce0( b1_ce0 ),
.we0( b1_we0 ),
.d0( b1_d0 ),
.q0( b1_q0 ),
.address1( b1_address1 ),
.ce1( b1_ce1 ),
.we1( b1_we1 ),
.d1( b1_d1 ),
.q1( b1_q1 )
);
Gaussianblur_c0 #(
.DataWidth( 32 ),
.AddressRange( 4096 ),
.AddressWidth( 12 ))
c0_U(
.clk( ap_clk ),
.address0( c0_address0 ),
.ce0( c0_ce0 ),
.we0( c0_we0 ),
.d0( c0_d0 ),
.q0( c0_q0 ),
.address1( c0_address1 ),
.ce1( c0_ce1 ),
.we1( c0_we1 ),
.d1( c0_d1 ),
.q1( c0_q1 )
);
Gaussianblur_c1 #(
.DataWidth( 32 ),
.AddressRange( 4096 ),
.AddressWidth( 12 ))
c1_U(
.clk( ap_clk ),
.address0( c1_address0 ),
.ce0( c1_ce0 ),
.we0( c1_we0 ),
.d0( c1_d0 ),
.q0( c1_q0 ),
.address1( c1_address1 ),
.ce1( c1_ce1 ),
.we1( c1_we1 ),
.d1( c1_d1 ),
.q1( c1_q1 )
);
Gaussianblur_d0 #(
.DataWidth( 32 ),
.AddressRange( 4096 ),
.AddressWidth( 12 ))
d0_U(
.clk( ap_clk ),
.address0( d0_address0 ),
.ce0( d0_ce0 ),
.we0( d0_we0 ),
.d0( d0_d0 ),
.q0( d0_q0 ),
.address1( d0_address1 ),
.ce1( d0_ce1 ),
.we1( d0_we1 ),
.d1( d0_d1 ),
.q1( d0_q1 )
);
Gaussianblur_d1 #(
.DataWidth( 32 ),
.AddressRange( 4096 ),
.AddressWidth( 12 ))
d1_U(
.clk( ap_clk ),
.address0( d1_address0 ),
.ce0( d1_ce0 ),
.we0( d1_we0 ),
.d0( d1_d0 ),
.q0( d1_q0 ),
.address1( d1_address1 ),
.ce1( d1_ce1 ),
.we1( d1_we1 ),
.d1( d1_d1 ),
.q1( d1_q1 )
);
step0 grp_step0_fu_168(
.ap_clk( ap_clk ),
.ap_rst( ap_rst ),
.ap_start( grp_step0_fu_168_ap_start ),
.ap_done( grp_step0_fu_168_ap_done ),
.ap_idle( grp_step0_fu_168_ap_idle ),
.tag( grp_step0_fu_168_tag ),
.counter( grp_step0_fu_168_counter ),
.a_address0( grp_step0_fu_168_a_address0 ),
.a_ce0( grp_step0_fu_168_a_ce0 ),
.a_we0( grp_step0_fu_168_a_we0 ),
.a_d0( grp_step0_fu_168_a_d0 ),
.a_q0( grp_step0_fu_168_a_q0 ),
.a_address1( grp_step0_fu_168_a_address1 ),
.a_ce1( grp_step0_fu_168_a_ce1 ),
.a_we1( grp_step0_fu_168_a_we1 ),
.a_d1( grp_step0_fu_168_a_d1 ),
.a_q1( grp_step0_fu_168_a_q1 ),
.b_address0( grp_step0_fu_168_b_address0 ),
.b_ce0( grp_step0_fu_168_b_ce0 ),
.b_we0( grp_step0_fu_168_b_we0 ),
.b_d0( grp_step0_fu_168_b_d0 ),
.b_q0( grp_step0_fu_168_b_q0 ),
.b_address1( grp_step0_fu_168_b_address1 ),
.b_ce1( grp_step0_fu_168_b_ce1 ),
.b_we1( grp_step0_fu_168_b_we1 ),
.b_d1( grp_step0_fu_168_b_d1 ),
.b_q1( grp_step0_fu_168_b_q1 ),
.BoundryScale( grp_step0_fu_168_BoundryScale ),
.nu( grp_step0_fu_168_nu )
);
step1 grp_step1_fu_180(
.ap_clk( ap_clk ),
.ap_rst( ap_rst ),
.ap_start( grp_step1_fu_180_ap_start ),
.ap_done( grp_step1_fu_180_ap_done ),
.ap_idle( grp_step1_fu_180_ap_idle ),
.step( grp_step1_fu_180_step ),
.tag( grp_step1_fu_180_tag ),
.counter( grp_step1_fu_180_counter ),
.c_address0( grp_step1_fu_180_c_address0 ),
.c_ce0( grp_step1_fu_180_c_ce0 ),
.c_q0( grp_step1_fu_180_c_q0 ),
.c_address1( grp_step1_fu_180_c_address1 ),
.c_ce1( grp_step1_fu_180_c_ce1 ),
.c_q1( grp_step1_fu_180_c_q1 ),
.b_address0( grp_step1_fu_180_b_address0 ),
.b_ce0( grp_step1_fu_180_b_ce0 ),
.b_q0( grp_step1_fu_180_b_q0 ),
.b_address1( grp_step1_fu_180_b_address1 ),
.b_ce1( grp_step1_fu_180_b_ce1 ),
.b_q1( grp_step1_fu_180_b_q1 ),
.d_address0( grp_step1_fu_180_d_address0 ),
.d_ce0( grp_step1_fu_180_d_ce0 ),
.d_we0( grp_step1_fu_180_d_we0 ),
.d_d0( grp_step1_fu_180_d_d0 ),
.d_address1( grp_step1_fu_180_d_address1 ),
.d_ce1( grp_step1_fu_180_d_ce1 ),
.d_we1( grp_step1_fu_180_d_we1 ),
.d_d1( grp_step1_fu_180_d_d1 ),
.c1_address0( grp_step1_fu_180_c1_address0 ),
.c1_ce0( grp_step1_fu_180_c1_ce0 ),
.c1_we0( grp_step1_fu_180_c1_we0 ),
.c1_d0( grp_step1_fu_180_c1_d0 ),
.c1_address1( grp_step1_fu_180_c1_address1 ),
.c1_ce1( grp_step1_fu_180_c1_ce1 ),
.c1_we1( grp_step1_fu_180_c1_we1 ),
.c1_d1( grp_step1_fu_180_c1_d1 ),
.BoundryScale( grp_step1_fu_180_BoundryScale ),
.nu( grp_step1_fu_180_nu ),
.PostScale( grp_step1_fu_180_PostScale )
);
write_r grp_write_r_fu_198(
.ap_clk( ap_clk ),
.ap_rst( ap_rst ),
.ap_start( grp_write_r_fu_198_ap_start ),
.ap_done( grp_write_r_fu_198_ap_done ),
.ap_idle( grp_write_r_fu_198_ap_idle ),
.tag( grp_write_r_fu_198_tag ),
.counter( grp_write_r_fu_198_counter ),
.d_address0( grp_write_r_fu_198_d_address0 ),
.d_ce0( grp_write_r_fu_198_d_ce0 ),
.d_q0( grp_write_r_fu_198_d_q0 ),
.d_address1( grp_write_r_fu_198_d_address1 ),
.d_ce1( grp_write_r_fu_198_d_ce1 ),
.d_q1( grp_write_r_fu_198_d_q1 ),
.V_bus_req_din( grp_write_r_fu_198_V_bus_req_din ),
.V_bus_req_full_n( grp_write_r_fu_198_V_bus_req_full_n ),
.V_bus_req_write( grp_write_r_fu_198_V_bus_req_write ),
.V_bus_rsp_dout( grp_write_r_fu_198_V_bus_rsp_dout ),
.V_bus_rsp_empty_n( grp_write_r_fu_198_V_bus_rsp_empty_n ),
.V_bus_rsp_read( grp_write_r_fu_198_V_bus_rsp_read ),
.V_bus_address( grp_write_r_fu_198_V_bus_address ),
.V_bus_datain( grp_write_r_fu_198_V_bus_datain ),
.V_bus_dataout( grp_write_r_fu_198_V_bus_dataout ),
.V_bus_size( grp_write_r_fu_198_V_bus_size )
);
fetch grp_fetch_fu_209(
.ap_clk( ap_clk ),
.ap_rst( ap_rst ),
.ap_start( grp_fetch_fu_209_ap_start ),
.ap_done( grp_fetch_fu_209_ap_done ),
.ap_idle( grp_fetch_fu_209_ap_idle ),
.tag( grp_fetch_fu_209_tag ),
.counter( grp_fetch_fu_209_counter ),
.a_address0( grp_fetch_fu_209_a_address0 ),
.a_ce0( grp_fetch_fu_209_a_ce0 ),
.a_we0( grp_fetch_fu_209_a_we0 ),
.a_d0( grp_fetch_fu_209_a_d0 ),
.a_address1( grp_fetch_fu_209_a_address1 ),
.a_ce1( grp_fetch_fu_209_a_ce1 ),
.a_we1( grp_fetch_fu_209_a_we1 ),
.a_d1( grp_fetch_fu_209_a_d1 ),
.V_bus_req_din( grp_fetch_fu_209_V_bus_req_din ),
.V_bus_req_full_n( grp_fetch_fu_209_V_bus_req_full_n ),
.V_bus_req_write( grp_fetch_fu_209_V_bus_req_write ),
.V_bus_rsp_dout( grp_fetch_fu_209_V_bus_rsp_dout ),
.V_bus_rsp_empty_n( grp_fetch_fu_209_V_bus_rsp_empty_n ),
.V_bus_rsp_read( grp_fetch_fu_209_V_bus_rsp_read ),
.V_bus_address( grp_fetch_fu_209_V_bus_address ),
.V_bus_datain( grp_fetch_fu_209_V_bus_datain ),
.V_bus_dataout( grp_fetch_fu_209_V_bus_dataout ),
.V_bus_size( grp_fetch_fu_209_V_bus_size )
);
Gaussianblur_grp_fu_220_ACMP_faddfsub_30 #(
.ID( 30 ),
.NUM_STAGE( 5 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
Gaussianblur_grp_fu_220_ACMP_faddfsub_30_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_220_p0 ),
.din1( grp_fu_220_p1 ),
.opcode( grp_fu_220_opcode ),
.ce( grp_fu_220_ce ),
.dout( grp_fu_220_p2 )
);
Gaussianblur_grp_fu_226_ACMP_fmul_31 #(
.ID( 31 ),
.NUM_STAGE( 4 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
Gaussianblur_grp_fu_226_ACMP_fmul_31_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_226_p0 ),
.din1( grp_fu_226_p1 ),
.ce( grp_fu_226_ce ),
.dout( grp_fu_226_p2 )
);
Gaussianblur_grp_fu_235_ACMP_fdiv_32 #(
.ID( 32 ),
.NUM_STAGE( 10 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
Gaussianblur_grp_fu_235_ACMP_fdiv_32_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_235_p0 ),
.din1( grp_fu_235_p1 ),
.ce( grp_fu_235_ce ),
.dout( grp_fu_235_p2 )
);
Gaussianblur_grp_fu_241_ACMP_fdiv_33 #(
.ID( 33 ),
.NUM_STAGE( 10 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
Gaussianblur_grp_fu_241_ACMP_fdiv_33_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_241_p0 ),
.din1( grp_fu_241_p1 ),
.ce( grp_fu_241_ce ),
.dout( grp_fu_241_p2 )
);
Gaussianblur_grp_fu_245_ACMP_fsqrt_34 #(
.ID( 34 ),
.NUM_STAGE( 10 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
Gaussianblur_grp_fu_245_ACMP_fsqrt_34_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_245_p0 ),
.din1( grp_fu_245_p1 ),
.ce( grp_fu_245_ce ),
.dout( grp_fu_245_p2 )
);
/// ap_CS_fsm assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_CS_fsm
if (ap_rst == 1'b1) begin
ap_CS_fsm <= ap_ST_st0_fsm_0;
end else begin
ap_CS_fsm <= ap_NS_fsm;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_ST_st67_fsm_67 == ap_CS_fsm)) begin
PostScale_reg_115 <= grp_fu_226_p2;
end else if ((ap_ST_st63_fsm_63 == ap_CS_fsm)) begin
PostScale_reg_115 <= ap_const_lv32_3F800000;
end
if (((ap_ST_st69_fsm_69 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond_fu_286_p2))) begin
counter_reg_153 <= ap_const_lv7_0;
end else if ((((ap_ST_st72_fsm_72 == ap_CS_fsm) & ~((ap_const_logic_0 == grp_fetch_fu_209_ap_done) | (ap_const_logic_0 == grp_step0_fu_168_ap_done) | (ap_const_logic_0 == grp_step1_fu_180_ap_done) | (ap_const_logic_0 == grp_write_r_fu_198_ap_done))) | (~((ap_const_logic_0 == grp_fetch_fu_209_ap_done) | (ap_const_logic_0 == grp_step0_fu_168_ap_done) | (ap_const_logic_0 == grp_step1_fu_180_ap_done) | (ap_const_logic_0 == grp_write_r_fu_198_ap_done)) & (ap_ST_st71_fsm_71 == ap_CS_fsm)))) begin
counter_reg_153 <= tmp_11_reg_357;
end
if ((ap_ST_st67_fsm_67 == ap_CS_fsm)) begin
i_reg_104 <= tmp_s_reg_341;
end else if ((ap_ST_st63_fsm_63 == ap_CS_fsm)) begin
i_reg_104 <= ap_const_lv2_0;
end
if (((ap_ST_st69_fsm_69 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond_fu_286_p2))) begin
indvar_reg_127 <= ap_const_lv1_1;
end else if (((ap_ST_st64_fsm_64 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond1_fu_274_p2))) begin
indvar_reg_127 <= ap_const_lv1_0;
end
if ((ap_ST_st48_fsm_48 == ap_CS_fsm)) begin
nu_reg_325 <= grp_fu_235_p2;
end
if (((ap_ST_st4_fsm_4 == ap_CS_fsm) | (ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st67_fsm_67 == ap_CS_fsm))) begin
reg_250 <= grp_fu_226_p2;
end
if (((ap_ST_st14_fsm_14 == ap_CS_fsm) | (ap_ST_st63_fsm_63 == ap_CS_fsm))) begin
reg_258 <= grp_fu_235_p2;
end
if (((ap_ST_st23_fsm_23 == ap_CS_fsm) | (ap_ST_st33_fsm_33 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st53_fsm_53 == ap_CS_fsm))) begin
reg_266 <= grp_fu_220_p2;
end
if (((ap_ST_st68_fsm_68 == ap_CS_fsm) & (ap_const_lv1_0 == indvar_phi_fu_132_p4))) begin
tag_reg_141 <= ap_const_lv2_0;
end else if (((ap_ST_st70_fsm_70 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond2_fu_298_p2))) begin
tag_reg_141 <= tmp_10_reg_349;
end
if ((ap_ST_st69_fsm_69 == ap_CS_fsm)) begin
tmp_10_reg_349 <= (tag_reg_141 + ap_const_lv2_1);
end
if ((ap_ST_st70_fsm_70 == ap_CS_fsm)) begin
tmp_11_reg_357 <= (counter_reg_153 + ap_const_lv7_1);
end
if ((ap_ST_st33_fsm_33 == ap_CS_fsm)) begin
tmp_5_reg_320 <= grp_fu_245_p2;
end
if ((ap_ST_st63_fsm_63 == ap_CS_fsm)) begin
tmp_8_reg_333 <= grp_fu_241_p2;
end
if ((ap_ST_st64_fsm_64 == ap_CS_fsm)) begin
tmp_s_reg_341 <= (i_reg_104 + ap_const_lv2_1);
end
end
/// a0_address0 assign process. ///
always @ (ap_CS_fsm or grp_step0_fu_168_a_address0 or grp_fetch_fu_209_a_address0)
begin
if ((ap_ST_st71_fsm_71 == ap_CS_fsm)) begin
a0_address0 = grp_fetch_fu_209_a_address0;
end else if ((ap_ST_st72_fsm_72 == ap_CS_fsm)) begin
a0_address0 = grp_step0_fu_168_a_address0;
end else begin
a0_address0 = grp_fetch_fu_209_a_address0;
end
end
/// a0_address1 assign process. ///
always @ (ap_CS_fsm or grp_step0_fu_168_a_address1 or grp_fetch_fu_209_a_address1)
begin
if ((ap_ST_st71_fsm_71 == ap_CS_fsm)) begin
a0_address1 = grp_fetch_fu_209_a_address1;
end else if ((ap_ST_st72_fsm_72 == ap_CS_fsm)) begin
a0_address1 = grp_step0_fu_168_a_address1;
end else begin
a0_address1 = grp_fetch_fu_209_a_address1;
end
end
/// a0_ce0 assign process. ///
always @ (ap_CS_fsm or grp_step0_fu_168_a_ce0 or grp_fetch_fu_209_a_ce0)
begin
if ((ap_ST_st71_fsm_71 == ap_CS_fsm)) begin
a0_ce0 = grp_fetch_fu_209_a_ce0;
end else if ((ap_ST_st72_fsm_72 == ap_CS_fsm)) begin
a0_ce0 = grp_step0_fu_168_a_ce0;
end else begin
a0_ce0 = ap_const_logic_0;
end
end
/// a0_ce1 assign process. ///
always @ (ap_CS_fsm or grp_step0_fu_168_a_ce1 or grp_fetch_fu_209_a_ce1)
begin
if ((ap_ST_st71_fsm_71 == ap_CS_fsm)) begin
a0_ce1 = grp_fetch_fu_209_a_ce1;
end else if ((ap_ST_st72_fsm_72 == ap_CS_fsm)) begin
a0_ce1 = grp_step0_fu_168_a_ce1;
end else begin
a0_ce1 = ap_const_logic_0;
end
end
/// a0_d0 assign process. ///
always @ (ap_CS_fsm or grp_step0_fu_168_a_d0 or grp_fetch_fu_209_a_d0)
begin
if ((ap_ST_st71_fsm_71 == ap_CS_fsm)) begin
a0_d0 = grp_fetch_fu_209_a_d0;
end else if ((ap_ST_st72_fsm_72 == ap_CS_fsm)) begin
a0_d0 = grp_step0_fu_168_a_d0;
end else begin
a0_d0 = grp_fetch_fu_209_a_d0;
end
end
/// a0_d1 assign process. ///
always @ (ap_CS_fsm or grp_step0_fu_168_a_d1 or grp_fetch_fu_209_a_d1)
begin
if ((ap_ST_st71_fsm_71 == ap_CS_fsm)) begin
a0_d1 = grp_fetch_fu_209_a_d1;
end else if ((ap_ST_st72_fsm_72 == ap_CS_fsm)) begin
a0_d1 = grp_step0_fu_168_a_d1;
end else begin
a0_d1 = grp_fetch_fu_209_a_d1;
end
end
/// a0_we0 assign process. ///
always @ (ap_CS_fsm or grp_step0_fu_168_a_we0 or grp_fetch_fu_209_a_we0)
begin
if ((ap_ST_st71_fsm_71 == ap_CS_fsm)) begin
a0_we0 = grp_fetch_fu_209_a_we0;
end else if ((ap_ST_st72_fsm_72 == ap_CS_fsm)) begin
a0_we0 = grp_step0_fu_168_a_we0;
end else begin
a0_we0 = ap_const_logic_0;
end
end
/// a0_we1 assign process. ///
always @ (ap_CS_fsm or grp_step0_fu_168_a_we1 or grp_fetch_fu_209_a_we1)
begin
if ((ap_ST_st71_fsm_71 == ap_CS_fsm)) begin
a0_we1 = grp_fetch_fu_209_a_we1;
end else if ((ap_ST_st72_fsm_72 == ap_CS_fsm)) begin
a0_we1 = grp_step0_fu_168_a_we1;
end else begin
a0_we1 = ap_const_logic_0;
end
end
/// a1_address0 assign process. ///
always @ (ap_CS_fsm or grp_step0_fu_168_a_address0 or grp_fetch_fu_209_a_address0)
begin
if ((ap_ST_st72_fsm_72 == ap_CS_fsm)) begin
a1_address0 = grp_fetch_fu_209_a_address0;
end else if ((ap_ST_st71_fsm_71 == ap_CS_fsm)) begin
a1_address0 = grp_step0_fu_168_a_address0;
end else begin
a1_address0 = grp_fetch_fu_209_a_address0;
end
end
/// a1_address1 assign process. ///
always @ (ap_CS_fsm or grp_step0_fu_168_a_address1 or grp_fetch_fu_209_a_address1)
begin
if ((ap_ST_st72_fsm_72 == ap_CS_fsm)) begin
a1_address1 = grp_fetch_fu_209_a_address1;
end else if ((ap_ST_st71_fsm_71 == ap_CS_fsm)) begin
a1_address1 = grp_step0_fu_168_a_address1;
end else begin
a1_address1 = grp_fetch_fu_209_a_address1;
end
end
/// a1_ce0 assign process. ///
always @ (ap_CS_fsm or grp_step0_fu_168_a_ce0 or grp_fetch_fu_209_a_ce0)
begin
if ((ap_ST_st72_fsm_72 == ap_CS_fsm)) begin
a1_ce0 = grp_fetch_fu_209_a_ce0;
end else if ((ap_ST_st71_fsm_71 == ap_CS_fsm)) begin
a1_ce0 = grp_step0_fu_168_a_ce0;
end else begin
a1_ce0 = ap_const_logic_0;
end
end
/// a1_ce1 assign process. ///
always @ (ap_CS_fsm or grp_step0_fu_168_a_ce1 or grp_fetch_fu_209_a_ce1)
begin
if ((ap_ST_st72_fsm_72 == ap_CS_fsm)) begin
a1_ce1 = grp_fetch_fu_209_a_ce1;
end else if ((ap_ST_st71_fsm_71 == ap_CS_fsm)) begin
a1_ce1 = grp_step0_fu_168_a_ce1;
end else begin
a1_ce1 = ap_const_logic_0;
end
end
/// a1_d0 assign process. ///
always @ (ap_CS_fsm or grp_step0_fu_168_a_d0 or grp_fetch_fu_209_a_d0)
begin
if ((ap_ST_st72_fsm_72 == ap_CS_fsm)) begin
a1_d0 = grp_fetch_fu_209_a_d0;
end else if ((ap_ST_st71_fsm_71 == ap_CS_fsm)) begin
a1_d0 = grp_step0_fu_168_a_d0;
end else begin
a1_d0 = grp_fetch_fu_209_a_d0;
end
end
/// a1_d1 assign process. ///
always @ (ap_CS_fsm or grp_step0_fu_168_a_d1 or grp_fetch_fu_209_a_d1)
begin
if ((ap_ST_st72_fsm_72 == ap_CS_fsm)) begin
a1_d1 = grp_fetch_fu_209_a_d1;
end else if ((ap_ST_st71_fsm_71 == ap_CS_fsm)) begin
a1_d1 = grp_step0_fu_168_a_d1;
end else begin
a1_d1 = grp_fetch_fu_209_a_d1;
end
end
/// a1_we0 assign process. ///
always @ (ap_CS_fsm or grp_step0_fu_168_a_we0 or grp_fetch_fu_209_a_we0)
begin
if ((ap_ST_st72_fsm_72 == ap_CS_fsm)) begin
a1_we0 = grp_fetch_fu_209_a_we0;
end else if ((ap_ST_st71_fsm_71 == ap_CS_fsm)) begin
a1_we0 = grp_step0_fu_168_a_we0;
end else begin
a1_we0 = ap_const_logic_0;
end
end
/// a1_we1 assign process. ///
always @ (ap_CS_fsm or grp_step0_fu_168_a_we1 or grp_fetch_fu_209_a_we1)
begin
if ((ap_ST_st72_fsm_72 == ap_CS_fsm)) begin
a1_we1 = grp_fetch_fu_209_a_we1;
end else if ((ap_ST_st71_fsm_71 == ap_CS_fsm)) begin
a1_we1 = grp_step0_fu_168_a_we1;
end else begin
a1_we1 = ap_const_logic_0;
end
end
/// ap_NS_fsm assign process. ///
always @ (ap_start or ap_CS_fsm or grp_step0_fu_168_ap_done or grp_step1_fu_180_ap_done or grp_write_r_fu_198_ap_done or grp_fetch_fu_209_ap_done or indvar_phi_fu_132_p4 or exitcond1_fu_274_p2 or exitcond_fu_286_p2 or exitcond2_fu_298_p2 or tmp_12_fu_310_p1)
begin
if (((ap_ST_st70_fsm_70 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond2_fu_298_p2) & ~(ap_const_lv1_0 == tmp_12_fu_310_p1))) begin
ap_NS_fsm = ap_ST_st72_fsm_72;
end else if (((ap_ST_st70_fsm_70 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond2_fu_298_p2) & (ap_const_lv1_0 == tmp_12_fu_310_p1))) begin
ap_NS_fsm = ap_ST_st71_fsm_71;
end else if ((((ap_ST_st72_fsm_72 == ap_CS_fsm) & ~((ap_const_logic_0 == grp_fetch_fu_209_ap_done) | (ap_const_logic_0 == grp_step0_fu_168_ap_done) | (ap_const_logic_0 == grp_step1_fu_180_ap_done) | (ap_const_logic_0 == grp_write_r_fu_198_ap_done))) | (~((ap_const_logic_0 == grp_fetch_fu_209_ap_done) | (ap_const_logic_0 == grp_step0_fu_168_ap_done) | (ap_const_logic_0 == grp_step1_fu_180_ap_done) | (ap_const_logic_0 == grp_write_r_fu_198_ap_done)) & (ap_ST_st71_fsm_71 == ap_CS_fsm)) | ((ap_ST_st69_fsm_69 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond_fu_286_p2)))) begin
ap_NS_fsm = ap_ST_st70_fsm_70;
end else if (((ap_ST_st68_fsm_68 == ap_CS_fsm) & ~(ap_const_logic_1 == ap_start) & ~(ap_const_lv1_0 == indvar_phi_fu_132_p4))) begin
ap_NS_fsm = ap_ST_st0_fsm_0;
end else if ((((ap_ST_st70_fsm_70 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond2_fu_298_p2)) | ((ap_ST_st68_fsm_68 == ap_CS_fsm) & (ap_const_lv1_0 == indvar_phi_fu_132_p4)))) begin
ap_NS_fsm = ap_ST_st69_fsm_69;
end else if ((ap_ST_st66_fsm_66 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st67_fsm_67;
end else if ((ap_ST_st65_fsm_65 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st66_fsm_66;
end else if ((((ap_ST_st64_fsm_64 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond1_fu_274_p2)) | ((ap_ST_st69_fsm_69 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond_fu_286_p2)))) begin
ap_NS_fsm = ap_ST_st68_fsm_68;
end else if (((ap_ST_st64_fsm_64 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond1_fu_274_p2))) begin
ap_NS_fsm = ap_ST_st65_fsm_65;
end else if (((ap_ST_st67_fsm_67 == ap_CS_fsm) | (ap_ST_st63_fsm_63 == ap_CS_fsm))) begin
ap_NS_fsm = ap_ST_st64_fsm_64;
end else if ((ap_ST_st62_fsm_62 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st63_fsm_63;
end else if ((ap_ST_st61_fsm_61 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st62_fsm_62;
end else if ((ap_ST_st60_fsm_60 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st61_fsm_61;
end else if ((ap_ST_st59_fsm_59 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st60_fsm_60;
end else if ((ap_ST_st58_fsm_58 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st59_fsm_59;
end else if ((ap_ST_st57_fsm_57 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st58_fsm_58;
end else if ((ap_ST_st56_fsm_56 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st57_fsm_57;
end else if ((ap_ST_st55_fsm_55 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st56_fsm_56;
end else if ((ap_ST_st54_fsm_54 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st55_fsm_55;
end else if ((ap_ST_st53_fsm_53 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st54_fsm_54;
end else if ((ap_ST_st52_fsm_52 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st53_fsm_53;
end else if ((ap_ST_st51_fsm_51 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st52_fsm_52;
end else if ((ap_ST_st50_fsm_50 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st51_fsm_51;
end else if ((ap_ST_st49_fsm_49 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st50_fsm_50;
end else if ((ap_ST_st48_fsm_48 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st49_fsm_49;
end else if ((ap_ST_st47_fsm_47 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st48_fsm_48;
end else if ((ap_ST_st46_fsm_46 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st47_fsm_47;
end else if ((ap_ST_st45_fsm_45 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st46_fsm_46;
end else if ((ap_ST_st44_fsm_44 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st45_fsm_45;
end else if ((ap_ST_st43_fsm_43 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st44_fsm_44;
end else if ((ap_ST_st42_fsm_42 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st43_fsm_43;
end else if ((ap_ST_st41_fsm_41 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st42_fsm_42;
end else if ((ap_ST_st40_fsm_40 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st41_fsm_41;
end else if ((ap_ST_st39_fsm_39 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st40_fsm_40;
end else if ((ap_ST_st38_fsm_38 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st39_fsm_39;
end else if ((ap_ST_st37_fsm_37 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st38_fsm_38;
end else if ((ap_ST_st36_fsm_36 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st37_fsm_37;
end else if ((ap_ST_st35_fsm_35 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st36_fsm_36;
end else if ((ap_ST_st34_fsm_34 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st35_fsm_35;
end else if ((ap_ST_st33_fsm_33 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st34_fsm_34;
end else if ((ap_ST_st32_fsm_32 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st33_fsm_33;
end else if ((ap_ST_st31_fsm_31 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st32_fsm_32;
end else if ((ap_ST_st30_fsm_30 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st31_fsm_31;
end else if ((ap_ST_st29_fsm_29 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st30_fsm_30;
end else if ((ap_ST_st28_fsm_28 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st29_fsm_29;
end else if ((ap_ST_st27_fsm_27 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st28_fsm_28;
end else if ((ap_ST_st26_fsm_26 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st27_fsm_27;
end else if ((ap_ST_st25_fsm_25 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st26_fsm_26;
end else if ((ap_ST_st24_fsm_24 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st25_fsm_25;
end else if ((ap_ST_st23_fsm_23 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st24_fsm_24;
end else if ((ap_ST_st22_fsm_22 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st23_fsm_23;
end else if ((ap_ST_st21_fsm_21 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st22_fsm_22;
end else if ((ap_ST_st20_fsm_20 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st21_fsm_21;
end else if ((ap_ST_st19_fsm_19 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st20_fsm_20;
end else if ((ap_ST_st18_fsm_18 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st19_fsm_19;
end else if ((ap_ST_st17_fsm_17 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st18_fsm_18;
end else if ((ap_ST_st16_fsm_16 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st17_fsm_17;
end else if ((ap_ST_st15_fsm_15 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st16_fsm_16;
end else if ((ap_ST_st14_fsm_14 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st15_fsm_15;
end else if ((ap_ST_st13_fsm_13 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st14_fsm_14;
end else if ((ap_ST_st12_fsm_12 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st13_fsm_13;
end else if ((ap_ST_st11_fsm_11 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st12_fsm_12;
end else if ((ap_ST_st10_fsm_10 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st11_fsm_11;
end else if ((ap_ST_st9_fsm_9 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st10_fsm_10;
end else if ((ap_ST_st8_fsm_8 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st9_fsm_9;
end else if ((ap_ST_st7_fsm_7 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st8_fsm_8;
end else if ((ap_ST_st6_fsm_6 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st7_fsm_7;
end else if ((ap_ST_st5_fsm_5 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st6_fsm_6;
end else if ((ap_ST_st4_fsm_4 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st5_fsm_5;
end else if ((ap_ST_st3_fsm_3 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st4_fsm_4;
end else if ((ap_ST_st2_fsm_2 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st3_fsm_3;
end else if ((ap_ST_st1_fsm_1 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st2_fsm_2;
end else if ((((ap_ST_st0_fsm_0 == ap_CS_fsm) & (ap_const_logic_1 == ap_start)) | ((ap_ST_st68_fsm_68 == ap_CS_fsm) & (ap_const_logic_1 == ap_start) & ~(ap_const_lv1_0 == indvar_phi_fu_132_p4)))) begin
ap_NS_fsm = ap_ST_st1_fsm_1;
end else begin
ap_NS_fsm = ap_CS_fsm;
end
end
/// ap_done assign process. ///
always @ (ap_CS_fsm or indvar_phi_fu_132_p4)
begin
if (((ap_ST_st68_fsm_68 == ap_CS_fsm) & ~(ap_const_lv1_0 == indvar_phi_fu_132_p4))) begin
ap_done = ap_const_logic_1;
end else begin
ap_done = ap_const_logic_0;
end
end
/// ap_idle assign process. ///
always @ (ap_CS_fsm)
begin
if ((ap_ST_st0_fsm_0 == ap_CS_fsm)) begin
ap_idle = ap_const_logic_1;
end else begin
ap_idle = ap_const_logic_0;
end
end
/// b0_address0 assign process. ///
always @ (ap_CS_fsm or grp_step0_fu_168_b_address0 or grp_step1_fu_180_b_address0)
begin
if ((ap_ST_st71_fsm_71 == ap_CS_fsm)) begin
b0_address0 = grp_step1_fu_180_b_address0;
end else if ((ap_ST_st72_fsm_72 == ap_CS_fsm)) begin
b0_address0 = grp_step0_fu_168_b_address0;
end else begin
b0_address0 = grp_step1_fu_180_b_address0;
end
end
/// b0_address1 assign process. ///
always @ (ap_CS_fsm or grp_step0_fu_168_b_address1 or grp_step1_fu_180_b_address1)
begin
if ((ap_ST_st71_fsm_71 == ap_CS_fsm)) begin
b0_address1 = grp_step1_fu_180_b_address1;
end else if ((ap_ST_st72_fsm_72 == ap_CS_fsm)) begin
b0_address1 = grp_step0_fu_168_b_address1;
end else begin
b0_address1 = grp_step1_fu_180_b_address1;
end
end
/// b0_ce0 assign process. ///
always @ (ap_CS_fsm or grp_step0_fu_168_b_ce0 or grp_step1_fu_180_b_ce0)
begin
if ((ap_ST_st71_fsm_71 == ap_CS_fsm)) begin
b0_ce0 = grp_step1_fu_180_b_ce0;
end else if ((ap_ST_st72_fsm_72 == ap_CS_fsm)) begin
b0_ce0 = grp_step0_fu_168_b_ce0;
end else begin
b0_ce0 = ap_const_logic_0;
end
end
/// b0_ce1 assign process. ///
always @ (ap_CS_fsm or grp_step0_fu_168_b_ce1 or grp_step1_fu_180_b_ce1)
begin
if ((ap_ST_st71_fsm_71 == ap_CS_fsm)) begin
b0_ce1 = grp_step1_fu_180_b_ce1;
end else if ((ap_ST_st72_fsm_72 == ap_CS_fsm)) begin
b0_ce1 = grp_step0_fu_168_b_ce1;
end else begin
b0_ce1 = ap_const_logic_0;
end
end
/// b0_we0 assign process. ///
always @ (ap_CS_fsm or grp_step0_fu_168_b_we0)
begin
if ((ap_ST_st72_fsm_72 == ap_CS_fsm)) begin
b0_we0 = grp_step0_fu_168_b_we0;
end else begin
b0_we0 = ap_const_logic_0;
end
end
/// b0_we1 assign process. ///
always @ (ap_CS_fsm or grp_step0_fu_168_b_we1)
begin
if ((ap_ST_st72_fsm_72 == ap_CS_fsm)) begin
b0_we1 = grp_step0_fu_168_b_we1;
end else begin
b0_we1 = ap_const_logic_0;
end
end
/// b1_address0 assign process. ///
always @ (ap_CS_fsm or grp_step0_fu_168_b_address0 or grp_step1_fu_180_b_address0)
begin
if ((ap_ST_st72_fsm_72 == ap_CS_fsm)) begin
b1_address0 = grp_step1_fu_180_b_address0;
end else if ((ap_ST_st71_fsm_71 == ap_CS_fsm)) begin
b1_address0 = grp_step0_fu_168_b_address0;
end else begin
b1_address0 = grp_step1_fu_180_b_address0;
end
end
/// b1_address1 assign process. ///
always @ (ap_CS_fsm or grp_step0_fu_168_b_address1 or grp_step1_fu_180_b_address1)
begin
if ((ap_ST_st72_fsm_72 == ap_CS_fsm)) begin
b1_address1 = grp_step1_fu_180_b_address1;
end else if ((ap_ST_st71_fsm_71 == ap_CS_fsm)) begin
b1_address1 = grp_step0_fu_168_b_address1;
end else begin
b1_address1 = grp_step1_fu_180_b_address1;
end
end
/// b1_ce0 assign process. ///
always @ (ap_CS_fsm or grp_step0_fu_168_b_ce0 or grp_step1_fu_180_b_ce0)
begin
if ((ap_ST_st72_fsm_72 == ap_CS_fsm)) begin
b1_ce0 = grp_step1_fu_180_b_ce0;
end else if ((ap_ST_st71_fsm_71 == ap_CS_fsm)) begin
b1_ce0 = grp_step0_fu_168_b_ce0;
end else begin
b1_ce0 = ap_const_logic_0;
end
end
/// b1_ce1 assign process. ///
always @ (ap_CS_fsm or grp_step0_fu_168_b_ce1 or grp_step1_fu_180_b_ce1)
begin
if ((ap_ST_st72_fsm_72 == ap_CS_fsm)) begin
b1_ce1 = grp_step1_fu_180_b_ce1;
end else if ((ap_ST_st71_fsm_71 == ap_CS_fsm)) begin
b1_ce1 = grp_step0_fu_168_b_ce1;
end else begin
b1_ce1 = ap_const_logic_0;
end
end
/// b1_we0 assign process. ///
always @ (ap_CS_fsm or grp_step0_fu_168_b_we0)
begin
if ((ap_ST_st71_fsm_71 == ap_CS_fsm)) begin
b1_we0 = grp_step0_fu_168_b_we0;
end else begin
b1_we0 = ap_const_logic_0;
end
end
/// b1_we1 assign process. ///
always @ (ap_CS_fsm or grp_step0_fu_168_b_we1)
begin
if ((ap_ST_st71_fsm_71 == ap_CS_fsm)) begin
b1_we1 = grp_step0_fu_168_b_we1;
end else begin
b1_we1 = ap_const_logic_0;
end
end
/// c0_address0 assign process. ///
always @ (ap_CS_fsm or grp_step1_fu_180_c_address0 or grp_step1_fu_180_c1_address0)
begin
if ((ap_ST_st72_fsm_72 == ap_CS_fsm)) begin
c0_address0 = grp_step1_fu_180_c1_address0;
end else if ((ap_ST_st71_fsm_71 == ap_CS_fsm)) begin
c0_address0 = grp_step1_fu_180_c_address0;
end else begin
c0_address0 = grp_step1_fu_180_c1_address0;
end
end
/// c0_address1 assign process. ///
always @ (ap_CS_fsm or grp_step1_fu_180_c_address1 or grp_step1_fu_180_c1_address1)
begin
if ((ap_ST_st72_fsm_72 == ap_CS_fsm)) begin
c0_address1 = grp_step1_fu_180_c1_address1;
end else if ((ap_ST_st71_fsm_71 == ap_CS_fsm)) begin
c0_address1 = grp_step1_fu_180_c_address1;
end else begin
c0_address1 = grp_step1_fu_180_c1_address1;
end
end
/// c0_ce0 assign process. ///
always @ (ap_CS_fsm or grp_step1_fu_180_c_ce0 or grp_step1_fu_180_c1_ce0)
begin
if ((ap_ST_st72_fsm_72 == ap_CS_fsm)) begin
c0_ce0 = grp_step1_fu_180_c1_ce0;
end else if ((ap_ST_st71_fsm_71 == ap_CS_fsm)) begin
c0_ce0 = grp_step1_fu_180_c_ce0;
end else begin
c0_ce0 = ap_const_logic_0;
end
end
/// c0_ce1 assign process. ///
always @ (ap_CS_fsm or grp_step1_fu_180_c_ce1 or grp_step1_fu_180_c1_ce1)
begin
if ((ap_ST_st72_fsm_72 == ap_CS_fsm)) begin
c0_ce1 = grp_step1_fu_180_c1_ce1;
end else if ((ap_ST_st71_fsm_71 == ap_CS_fsm)) begin
c0_ce1 = grp_step1_fu_180_c_ce1;
end else begin
c0_ce1 = ap_const_logic_0;
end
end
/// c0_we0 assign process. ///
always @ (ap_CS_fsm or grp_step1_fu_180_c1_we0)
begin
if ((ap_ST_st72_fsm_72 == ap_CS_fsm)) begin
c0_we0 = grp_step1_fu_180_c1_we0;
end else begin
c0_we0 = ap_const_logic_0;
end
end
/// c0_we1 assign process. ///
always @ (ap_CS_fsm or grp_step1_fu_180_c1_we1)
begin
if ((ap_ST_st72_fsm_72 == ap_CS_fsm)) begin
c0_we1 = grp_step1_fu_180_c1_we1;
end else begin
c0_we1 = ap_const_logic_0;
end
end
/// c1_address0 assign process. ///
always @ (ap_CS_fsm or grp_step1_fu_180_c_address0 or grp_step1_fu_180_c1_address0)
begin
if ((ap_ST_st71_fsm_71 == ap_CS_fsm)) begin
c1_address0 = grp_step1_fu_180_c1_address0;
end else if ((ap_ST_st72_fsm_72 == ap_CS_fsm)) begin
c1_address0 = grp_step1_fu_180_c_address0;
end else begin
c1_address0 = grp_step1_fu_180_c1_address0;
end
end
/// c1_address1 assign process. ///
always @ (ap_CS_fsm or grp_step1_fu_180_c_address1 or grp_step1_fu_180_c1_address1)
begin
if ((ap_ST_st71_fsm_71 == ap_CS_fsm)) begin
c1_address1 = grp_step1_fu_180_c1_address1;
end else if ((ap_ST_st72_fsm_72 == ap_CS_fsm)) begin
c1_address1 = grp_step1_fu_180_c_address1;
end else begin
c1_address1 = grp_step1_fu_180_c1_address1;
end
end
/// c1_ce0 assign process. ///
always @ (ap_CS_fsm or grp_step1_fu_180_c_ce0 or grp_step1_fu_180_c1_ce0)
begin
if ((ap_ST_st71_fsm_71 == ap_CS_fsm)) begin
c1_ce0 = grp_step1_fu_180_c1_ce0;
end else if ((ap_ST_st72_fsm_72 == ap_CS_fsm)) begin
c1_ce0 = grp_step1_fu_180_c_ce0;
end else begin
c1_ce0 = ap_const_logic_0;
end
end
/// c1_ce1 assign process. ///
always @ (ap_CS_fsm or grp_step1_fu_180_c_ce1 or grp_step1_fu_180_c1_ce1)
begin
if ((ap_ST_st71_fsm_71 == ap_CS_fsm)) begin
c1_ce1 = grp_step1_fu_180_c1_ce1;
end else if ((ap_ST_st72_fsm_72 == ap_CS_fsm)) begin
c1_ce1 = grp_step1_fu_180_c_ce1;
end else begin
c1_ce1 = ap_const_logic_0;
end
end
/// c1_we0 assign process. ///
always @ (ap_CS_fsm or grp_step1_fu_180_c1_we0)
begin
if ((ap_ST_st71_fsm_71 == ap_CS_fsm)) begin
c1_we0 = grp_step1_fu_180_c1_we0;
end else begin
c1_we0 = ap_const_logic_0;
end
end
/// c1_we1 assign process. ///
always @ (ap_CS_fsm or grp_step1_fu_180_c1_we1)
begin
if ((ap_ST_st71_fsm_71 == ap_CS_fsm)) begin
c1_we1 = grp_step1_fu_180_c1_we1;
end else begin
c1_we1 = ap_const_logic_0;
end
end
/// d0_address0 assign process. ///
always @ (ap_CS_fsm or grp_step1_fu_180_d_address0 or grp_write_r_fu_198_d_address0)
begin
if ((ap_ST_st72_fsm_72 == ap_CS_fsm)) begin
d0_address0 = grp_write_r_fu_198_d_address0;
end else if ((ap_ST_st71_fsm_71 == ap_CS_fsm)) begin
d0_address0 = grp_step1_fu_180_d_address0;
end else begin
d0_address0 = grp_write_r_fu_198_d_address0;
end
end
/// d0_address1 assign process. ///
always @ (ap_CS_fsm or grp_step1_fu_180_d_address1 or grp_write_r_fu_198_d_address1)
begin
if ((ap_ST_st72_fsm_72 == ap_CS_fsm)) begin
d0_address1 = grp_write_r_fu_198_d_address1;
end else if ((ap_ST_st71_fsm_71 == ap_CS_fsm)) begin
d0_address1 = grp_step1_fu_180_d_address1;
end else begin
d0_address1 = grp_write_r_fu_198_d_address1;
end
end
/// d0_ce0 assign process. ///
always @ (ap_CS_fsm or grp_step1_fu_180_d_ce0 or grp_write_r_fu_198_d_ce0)
begin
if ((ap_ST_st72_fsm_72 == ap_CS_fsm)) begin
d0_ce0 = grp_write_r_fu_198_d_ce0;
end else if ((ap_ST_st71_fsm_71 == ap_CS_fsm)) begin
d0_ce0 = grp_step1_fu_180_d_ce0;
end else begin
d0_ce0 = ap_const_logic_0;
end
end
/// d0_ce1 assign process. ///
always @ (ap_CS_fsm or grp_step1_fu_180_d_ce1 or grp_write_r_fu_198_d_ce1)
begin
if ((ap_ST_st72_fsm_72 == ap_CS_fsm)) begin
d0_ce1 = grp_write_r_fu_198_d_ce1;
end else if ((ap_ST_st71_fsm_71 == ap_CS_fsm)) begin
d0_ce1 = grp_step1_fu_180_d_ce1;
end else begin
d0_ce1 = ap_const_logic_0;
end
end
/// d0_we0 assign process. ///
always @ (ap_CS_fsm or grp_step1_fu_180_d_we0)
begin
if ((ap_ST_st71_fsm_71 == ap_CS_fsm)) begin
d0_we0 = grp_step1_fu_180_d_we0;
end else begin
d0_we0 = ap_const_logic_0;
end
end
/// d0_we1 assign process. ///
always @ (ap_CS_fsm or grp_step1_fu_180_d_we1)
begin
if ((ap_ST_st71_fsm_71 == ap_CS_fsm)) begin
d0_we1 = grp_step1_fu_180_d_we1;
end else begin
d0_we1 = ap_const_logic_0;
end
end
/// d1_address0 assign process. ///
always @ (ap_CS_fsm or grp_step1_fu_180_d_address0 or grp_write_r_fu_198_d_address0)
begin
if ((ap_ST_st71_fsm_71 == ap_CS_fsm)) begin
d1_address0 = grp_write_r_fu_198_d_address0;
end else if ((ap_ST_st72_fsm_72 == ap_CS_fsm)) begin
d1_address0 = grp_step1_fu_180_d_address0;
end else begin
d1_address0 = grp_write_r_fu_198_d_address0;
end
end
/// d1_address1 assign process. ///
always @ (ap_CS_fsm or grp_step1_fu_180_d_address1 or grp_write_r_fu_198_d_address1)
begin
if ((ap_ST_st71_fsm_71 == ap_CS_fsm)) begin
d1_address1 = grp_write_r_fu_198_d_address1;
end else if ((ap_ST_st72_fsm_72 == ap_CS_fsm)) begin
d1_address1 = grp_step1_fu_180_d_address1;
end else begin
d1_address1 = grp_write_r_fu_198_d_address1;
end
end
/// d1_ce0 assign process. ///
always @ (ap_CS_fsm or grp_step1_fu_180_d_ce0 or grp_write_r_fu_198_d_ce0)
begin
if ((ap_ST_st71_fsm_71 == ap_CS_fsm)) begin
d1_ce0 = grp_write_r_fu_198_d_ce0;
end else if ((ap_ST_st72_fsm_72 == ap_CS_fsm)) begin
d1_ce0 = grp_step1_fu_180_d_ce0;
end else begin
d1_ce0 = ap_const_logic_0;
end
end
/// d1_ce1 assign process. ///
always @ (ap_CS_fsm or grp_step1_fu_180_d_ce1 or grp_write_r_fu_198_d_ce1)
begin
if ((ap_ST_st71_fsm_71 == ap_CS_fsm)) begin
d1_ce1 = grp_write_r_fu_198_d_ce1;
end else if ((ap_ST_st72_fsm_72 == ap_CS_fsm)) begin
d1_ce1 = grp_step1_fu_180_d_ce1;
end else begin
d1_ce1 = ap_const_logic_0;
end
end
/// d1_we0 assign process. ///
always @ (ap_CS_fsm or grp_step1_fu_180_d_we0)
begin
if ((ap_ST_st72_fsm_72 == ap_CS_fsm)) begin
d1_we0 = grp_step1_fu_180_d_we0;
end else begin
d1_we0 = ap_const_logic_0;
end
end
/// d1_we1 assign process. ///
always @ (ap_CS_fsm or grp_step1_fu_180_d_we1)
begin
if ((ap_ST_st72_fsm_72 == ap_CS_fsm)) begin
d1_we1 = grp_step1_fu_180_d_we1;
end else begin
d1_we1 = ap_const_logic_0;
end
end
/// grp_fetch_fu_209_ap_start assign process. ///
always @ (ap_CS_fsm or exitcond2_fu_298_p2 or tmp_12_fu_310_p1)
begin
if ((((ap_ST_st70_fsm_70 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond2_fu_298_p2) & (ap_const_lv1_0 == tmp_12_fu_310_p1)) | ((ap_ST_st70_fsm_70 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond2_fu_298_p2) & ~(ap_const_lv1_0 == tmp_12_fu_310_p1)))) begin
grp_fetch_fu_209_ap_start = ap_const_logic_1;
end else begin
grp_fetch_fu_209_ap_start = ap_const_logic_0;
end
end
/// grp_fu_220_opcode assign process. ///
always @ (ap_CS_fsm)
begin
if (((ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st49_fsm_49 == ap_CS_fsm))) begin
grp_fu_220_opcode = ap_const_lv2_1;
end else if (((ap_ST_st19_fsm_19 == ap_CS_fsm) | (ap_ST_st29_fsm_29 == ap_CS_fsm))) begin
grp_fu_220_opcode = ap_const_lv2_0;
end else begin
grp_fu_220_opcode = ap_const_lv2_1;
end
end
/// grp_fu_220_p0 assign process. ///
always @ (ap_CS_fsm or reg_250 or reg_266)
begin
if ((ap_ST_st49_fsm_49 == ap_CS_fsm)) begin
grp_fu_220_p0 = ap_const_lv32_3F800000;
end else if ((ap_ST_st34_fsm_34 == ap_CS_fsm)) begin
grp_fu_220_p0 = reg_266;
end else if (((ap_ST_st19_fsm_19 == ap_CS_fsm) | (ap_ST_st29_fsm_29 == ap_CS_fsm))) begin
grp_fu_220_p0 = reg_250;
end else begin
grp_fu_220_p0 = ap_const_lv32_3F800000;
end
end
/// grp_fu_220_p1 assign process. ///
always @ (ap_CS_fsm or tmp_5_reg_320 or nu_reg_325)
begin
if ((ap_ST_st49_fsm_49 == ap_CS_fsm)) begin
grp_fu_220_p1 = nu_reg_325;
end else if ((ap_ST_st34_fsm_34 == ap_CS_fsm)) begin
grp_fu_220_p1 = tmp_5_reg_320;
end else if (((ap_ST_st19_fsm_19 == ap_CS_fsm) | (ap_ST_st29_fsm_29 == ap_CS_fsm))) begin
grp_fu_220_p1 = ap_const_lv32_3F800000;
end else begin
grp_fu_220_p1 = ap_const_lv32_3F800000;
end
end
/// grp_fu_226_ce assign process. ///
always @ (ap_CS_fsm or exitcond1_fu_274_p2)
begin
if (((ap_ST_st4_fsm_4 == ap_CS_fsm) | (ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st67_fsm_67 == ap_CS_fsm) | (ap_ST_st1_fsm_1 == ap_CS_fsm) | (ap_ST_st15_fsm_15 == ap_CS_fsm) | (ap_ST_st25_fsm_25 == ap_CS_fsm) | ((ap_ST_st64_fsm_64 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond1_fu_274_p2)) | (ap_ST_st2_fsm_2 == ap_CS_fsm) | (ap_ST_st3_fsm_3 == ap_CS_fsm) | (ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st17_fsm_17 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st27_fsm_27 == ap_CS_fsm) | (ap_ST_st65_fsm_65 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm))) begin
grp_fu_226_ce = ap_const_logic_1;
end else begin
grp_fu_226_ce = ap_const_logic_0;
end
end
/// grp_fu_226_p0 assign process. ///
always @ (ap_CS_fsm or std or reg_258 or tmp_8_reg_333 or exitcond1_fu_274_p2)
begin
if (((ap_ST_st64_fsm_64 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond1_fu_274_p2))) begin
grp_fu_226_p0 = tmp_8_reg_333;
end else if (((ap_ST_st15_fsm_15 == ap_CS_fsm) | (ap_ST_st25_fsm_25 == ap_CS_fsm))) begin
grp_fu_226_p0 = reg_258;
end else if ((ap_ST_st1_fsm_1 == ap_CS_fsm)) begin
grp_fu_226_p0 = std;
end else begin
grp_fu_226_p0 = tmp_8_reg_333;
end
end
/// grp_fu_226_p1 assign process. ///
always @ (ap_CS_fsm or std or PostScale_reg_115 or exitcond1_fu_274_p2)
begin
if (((ap_ST_st64_fsm_64 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond1_fu_274_p2))) begin
grp_fu_226_p1 = PostScale_reg_115;
end else if ((ap_ST_st25_fsm_25 == ap_CS_fsm)) begin
grp_fu_226_p1 = ap_const_lv32_40000000;
end else if ((ap_ST_st15_fsm_15 == ap_CS_fsm)) begin
grp_fu_226_p1 = ap_const_lv32_40800000;
end else if ((ap_ST_st1_fsm_1 == ap_CS_fsm)) begin
grp_fu_226_p1 = std;
end else begin
grp_fu_226_p1 = ap_const_lv32_40000000;
end
end
/// grp_fu_235_p0 assign process. ///
always @ (ap_CS_fsm or reg_250 or reg_266)
begin
if ((ap_ST_st54_fsm_54 == ap_CS_fsm)) begin
grp_fu_235_p0 = ap_const_lv32_3F800000;
end else if ((ap_ST_st39_fsm_39 == ap_CS_fsm)) begin
grp_fu_235_p0 = reg_266;
end else if ((ap_ST_st5_fsm_5 == ap_CS_fsm)) begin
grp_fu_235_p0 = reg_250;
end else begin
grp_fu_235_p0 = ap_const_lv32_3F800000;
end
end
/// grp_fu_235_p1 assign process. ///
always @ (ap_CS_fsm or reg_250 or reg_266)
begin
if ((ap_ST_st54_fsm_54 == ap_CS_fsm)) begin
grp_fu_235_p1 = reg_266;
end else if ((ap_ST_st39_fsm_39 == ap_CS_fsm)) begin
grp_fu_235_p1 = reg_250;
end else if ((ap_ST_st5_fsm_5 == ap_CS_fsm)) begin
grp_fu_235_p1 = ap_const_lv32_40000000;
end else begin
grp_fu_235_p1 = ap_const_lv32_40000000;
end
end
/// grp_step0_fu_168_a_q0 assign process. ///
always @ (ap_CS_fsm or a0_q0 or a1_q0)
begin
if ((ap_ST_st72_fsm_72 == ap_CS_fsm)) begin
grp_step0_fu_168_a_q0 = a0_q0;
end else if ((ap_ST_st71_fsm_71 == ap_CS_fsm)) begin
grp_step0_fu_168_a_q0 = a1_q0;
end else begin
grp_step0_fu_168_a_q0 = a1_q0;
end
end
/// grp_step0_fu_168_a_q1 assign process. ///
always @ (ap_CS_fsm or a0_q1 or a1_q1)
begin
if ((ap_ST_st72_fsm_72 == ap_CS_fsm)) begin
grp_step0_fu_168_a_q1 = a0_q1;
end else if ((ap_ST_st71_fsm_71 == ap_CS_fsm)) begin
grp_step0_fu_168_a_q1 = a1_q1;
end else begin
grp_step0_fu_168_a_q1 = a1_q1;
end
end
/// grp_step0_fu_168_ap_start assign process. ///
always @ (ap_CS_fsm or exitcond2_fu_298_p2 or tmp_12_fu_310_p1)
begin
if ((((ap_ST_st70_fsm_70 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond2_fu_298_p2) & (ap_const_lv1_0 == tmp_12_fu_310_p1)) | ((ap_ST_st70_fsm_70 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond2_fu_298_p2) & ~(ap_const_lv1_0 == tmp_12_fu_310_p1)))) begin
grp_step0_fu_168_ap_start = ap_const_logic_1;
end else begin
grp_step0_fu_168_ap_start = ap_const_logic_0;
end
end
/// grp_step0_fu_168_b_q0 assign process. ///
always @ (ap_CS_fsm or b0_q0 or b1_q0)
begin
if ((ap_ST_st72_fsm_72 == ap_CS_fsm)) begin
grp_step0_fu_168_b_q0 = b0_q0;
end else if ((ap_ST_st71_fsm_71 == ap_CS_fsm)) begin
grp_step0_fu_168_b_q0 = b1_q0;
end else begin
grp_step0_fu_168_b_q0 = b1_q0;
end
end
/// grp_step0_fu_168_b_q1 assign process. ///
always @ (ap_CS_fsm or b0_q1 or b1_q1)
begin
if ((ap_ST_st72_fsm_72 == ap_CS_fsm)) begin
grp_step0_fu_168_b_q1 = b0_q1;
end else if ((ap_ST_st71_fsm_71 == ap_CS_fsm)) begin
grp_step0_fu_168_b_q1 = b1_q1;
end else begin
grp_step0_fu_168_b_q1 = b1_q1;
end
end
/// grp_step1_fu_180_ap_start assign process. ///
always @ (ap_CS_fsm or exitcond2_fu_298_p2 or tmp_12_fu_310_p1)
begin
if ((((ap_ST_st70_fsm_70 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond2_fu_298_p2) & (ap_const_lv1_0 == tmp_12_fu_310_p1)) | ((ap_ST_st70_fsm_70 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond2_fu_298_p2) & ~(ap_const_lv1_0 == tmp_12_fu_310_p1)))) begin
grp_step1_fu_180_ap_start = ap_const_logic_1;
end else begin
grp_step1_fu_180_ap_start = ap_const_logic_0;
end
end
/// grp_step1_fu_180_b_q0 assign process. ///
always @ (ap_CS_fsm or b0_q0 or b1_q0)
begin
if ((ap_ST_st72_fsm_72 == ap_CS_fsm)) begin
grp_step1_fu_180_b_q0 = b1_q0;
end else if ((ap_ST_st71_fsm_71 == ap_CS_fsm)) begin
grp_step1_fu_180_b_q0 = b0_q0;
end else begin
grp_step1_fu_180_b_q0 = b1_q0;
end
end
/// grp_step1_fu_180_b_q1 assign process. ///
always @ (ap_CS_fsm or b0_q1 or b1_q1)
begin
if ((ap_ST_st72_fsm_72 == ap_CS_fsm)) begin
grp_step1_fu_180_b_q1 = b1_q1;
end else if ((ap_ST_st71_fsm_71 == ap_CS_fsm)) begin
grp_step1_fu_180_b_q1 = b0_q1;
end else begin
grp_step1_fu_180_b_q1 = b1_q1;
end
end
/// grp_step1_fu_180_c_q0 assign process. ///
always @ (ap_CS_fsm or c0_q0 or c1_q0)
begin
if ((ap_ST_st72_fsm_72 == ap_CS_fsm)) begin
grp_step1_fu_180_c_q0 = c1_q0;
end else if ((ap_ST_st71_fsm_71 == ap_CS_fsm)) begin
grp_step1_fu_180_c_q0 = c0_q0;
end else begin
grp_step1_fu_180_c_q0 = c1_q0;
end
end
/// grp_step1_fu_180_c_q1 assign process. ///
always @ (ap_CS_fsm or c0_q1 or c1_q1)
begin
if ((ap_ST_st72_fsm_72 == ap_CS_fsm)) begin
grp_step1_fu_180_c_q1 = c1_q1;
end else if ((ap_ST_st71_fsm_71 == ap_CS_fsm)) begin
grp_step1_fu_180_c_q1 = c0_q1;
end else begin
grp_step1_fu_180_c_q1 = c1_q1;
end
end
/// grp_write_r_fu_198_ap_start assign process. ///
always @ (ap_CS_fsm or exitcond2_fu_298_p2 or tmp_12_fu_310_p1)
begin
if ((((ap_ST_st70_fsm_70 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond2_fu_298_p2) & (ap_const_lv1_0 == tmp_12_fu_310_p1)) | ((ap_ST_st70_fsm_70 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond2_fu_298_p2) & ~(ap_const_lv1_0 == tmp_12_fu_310_p1)))) begin
grp_write_r_fu_198_ap_start = ap_const_logic_1;
end else begin
grp_write_r_fu_198_ap_start = ap_const_logic_0;
end
end
/// grp_write_r_fu_198_d_q0 assign process. ///
always @ (ap_CS_fsm or d0_q0 or d1_q0)
begin
if ((ap_ST_st72_fsm_72 == ap_CS_fsm)) begin
grp_write_r_fu_198_d_q0 = d0_q0;
end else if ((ap_ST_st71_fsm_71 == ap_CS_fsm)) begin
grp_write_r_fu_198_d_q0 = d1_q0;
end else begin
grp_write_r_fu_198_d_q0 = d1_q0;
end
end
/// grp_write_r_fu_198_d_q1 assign process. ///
always @ (ap_CS_fsm or d0_q1 or d1_q1)
begin
if ((ap_ST_st72_fsm_72 == ap_CS_fsm)) begin
grp_write_r_fu_198_d_q1 = d0_q1;
end else if ((ap_ST_st71_fsm_71 == ap_CS_fsm)) begin
grp_write_r_fu_198_d_q1 = d1_q1;
end else begin
grp_write_r_fu_198_d_q1 = d1_q1;
end
end
assign V1_bus_address = grp_fetch_fu_209_V_bus_address;
assign V1_bus_dataout = grp_fetch_fu_209_V_bus_dataout;
assign V1_bus_req_din = grp_fetch_fu_209_V_bus_req_din;
assign V1_bus_req_write = grp_fetch_fu_209_V_bus_req_write;
assign V1_bus_rsp_read = grp_fetch_fu_209_V_bus_rsp_read;
assign V1_bus_size = grp_fetch_fu_209_V_bus_size;
assign V2_bus_address = grp_write_r_fu_198_V_bus_address;
assign V2_bus_dataout = grp_write_r_fu_198_V_bus_dataout;
assign V2_bus_req_din = grp_write_r_fu_198_V_bus_req_din;
assign V2_bus_req_write = grp_write_r_fu_198_V_bus_req_write;
assign V2_bus_rsp_read = grp_write_r_fu_198_V_bus_rsp_read;
assign V2_bus_size = grp_write_r_fu_198_V_bus_size;
assign b0_d0 = grp_step0_fu_168_b_d0;
assign b0_d1 = grp_step0_fu_168_b_d1;
assign b1_d0 = grp_step0_fu_168_b_d0;
assign b1_d1 = grp_step0_fu_168_b_d1;
assign c0_d0 = grp_step1_fu_180_c1_d0;
assign c0_d1 = grp_step1_fu_180_c1_d1;
assign c1_d0 = grp_step1_fu_180_c1_d0;
assign c1_d1 = grp_step1_fu_180_c1_d1;
assign d0_d0 = grp_step1_fu_180_d_d0;
assign d0_d1 = grp_step1_fu_180_d_d1;
assign d1_d0 = grp_step1_fu_180_d_d0;
assign d1_d1 = grp_step1_fu_180_d_d1;
assign exitcond1_fu_274_p2 = (i_reg_104 == ap_const_lv2_3? 1'b1: 1'b0);
assign exitcond2_fu_298_p2 = (counter_reg_153 == ap_const_lv7_43? 1'b1: 1'b0);
assign exitcond_fu_286_p2 = (tag_reg_141 == ap_const_lv2_2? 1'b1: 1'b0);
assign grp_fetch_fu_209_V_bus_datain = V1_bus_datain;
assign grp_fetch_fu_209_V_bus_req_full_n = V1_bus_req_full_n;
assign grp_fetch_fu_209_V_bus_rsp_dout = V1_bus_rsp_dout;
assign grp_fetch_fu_209_V_bus_rsp_empty_n = V1_bus_rsp_empty_n;
assign grp_fetch_fu_209_counter = counter_reg_153;
assign grp_fetch_fu_209_tag = tag_reg_141;
assign grp_fu_220_ce = ap_const_logic_1;
assign grp_fu_235_ce = ap_const_logic_1;
assign grp_fu_241_ce = ap_const_logic_1;
assign grp_fu_241_p0 = nu_reg_325;
assign grp_fu_241_p1 = reg_258;
assign grp_fu_245_ce = ap_const_logic_1;
assign grp_fu_245_p0 = ap_const_lv32_1;
assign grp_fu_245_p1 = reg_266;
assign grp_step0_fu_168_BoundryScale = reg_258;
assign grp_step0_fu_168_counter = counter_reg_153;
assign grp_step0_fu_168_nu = nu_reg_325;
assign grp_step0_fu_168_tag = tag_reg_141;
assign grp_step1_fu_180_BoundryScale = reg_258;
assign grp_step1_fu_180_PostScale = PostScale_reg_115;
assign grp_step1_fu_180_counter = counter_reg_153;
assign grp_step1_fu_180_nu = nu_reg_325;
assign grp_step1_fu_180_step = indvar_reg_127;
assign grp_step1_fu_180_tag = tag_reg_141;
assign grp_write_r_fu_198_V_bus_datain = V2_bus_datain;
assign grp_write_r_fu_198_V_bus_req_full_n = V2_bus_req_full_n;
assign grp_write_r_fu_198_V_bus_rsp_dout = V2_bus_rsp_dout;
assign grp_write_r_fu_198_V_bus_rsp_empty_n = V2_bus_rsp_empty_n;
assign grp_write_r_fu_198_counter = counter_reg_153;
assign grp_write_r_fu_198_tag = tag_reg_141;
assign indvar_phi_fu_132_p4 = indvar_reg_127;
assign tmp_12_fu_310_p1 = counter_reg_153[0:0];
endmodule //Gaussianblur
|
// ==============================================================
// File generated by AutoESL - High-Level Synthesis System (C, C++, SystemC)
// Version: 2011.1
// Copyright (C) 2011 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module Gaussianblur_a0_core (q, ra, ce, clk
, d, wa, we);
parameter READ_PORT_COUNT=32'd2;
parameter WRITE_PORT_COUNT=32'd2;
parameter DATA_WIDTH=32'd32;
parameter ADDRESS_WIDTH=32'd12;
parameter WORD_COUNT=32'd4096;
output [READ_PORT_COUNT*DATA_WIDTH-1:0] q;
input [READ_PORT_COUNT*ADDRESS_WIDTH-1:0] ra;
input [READ_PORT_COUNT-1:0] ce;
input [WRITE_PORT_COUNT*DATA_WIDTH-1:0] d;
input [WRITE_PORT_COUNT*ADDRESS_WIDTH-1:0] wa;
input [WRITE_PORT_COUNT-1:0] we;
input clk;
integer i,j,k;
reg [DATA_WIDTH-1:0] mem [0:WORD_COUNT-1];
reg [ADDRESS_WIDTH-1:0] rat;
reg [ADDRESS_WIDTH-1:0] rai [READ_PORT_COUNT-1:0];
reg [ADDRESS_WIDTH-1:0] rai_reg [READ_PORT_COUNT-1:0];
reg [READ_PORT_COUNT*DATA_WIDTH-1:0] qi;
reg [DATA_WIDTH-1:0] qt;
reg [DATA_WIDTH-1:0] di [WRITE_PORT_COUNT-1:0];
reg [DATA_WIDTH-1:0] dt;
reg [ADDRESS_WIDTH-1:0] wat;
reg [ADDRESS_WIDTH-1:0] wai [WRITE_PORT_COUNT-1:0];
// Split input data
always @ (d) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<DATA_WIDTH;j=j+1) begin
dt[j]=d[i*DATA_WIDTH+j];
end
di[i]=dt;
end
end
// Split write addresses
always @ (wa) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
wat[j]=wa[i*ADDRESS_WIDTH+j];
end
wai[i]=wat;
end
end
// Write memory
always @ (posedge clk) begin
for (j=0;j<WRITE_PORT_COUNT;j=j+1) begin
if (we[j]) begin
mem[wai[j]] <= di[j];
end
end
end
// Split read addresses
always @ (ra) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
rat[j]=ra[i*ADDRESS_WIDTH+j];
end
rai[i]=rat;
end
end
// guide read addresses using CE
always @ (posedge clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if ( ce[i] ) begin
rai_reg[i] <= rai[i];
end
end
end
// Memory read
genvar x;
generate
for (x = 0; x < READ_PORT_COUNT; x = x + 1) begin : gen_q
assign q[x*DATA_WIDTH+DATA_WIDTH-1:x*DATA_WIDTH] = (rai_reg[x]<WORD_COUNT)?
mem[rai_reg[x]] : {DATA_WIDTH{1'b0}};
end
endgenerate
endmodule
module Gaussianblur_a0 (
address0,
ce0,
q0,
we0,
d0,
address1,
ce1,
q1,
we1,
d1,
clk);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd4096;
parameter AddressWidth = 32'd12;
input[AddressWidth-1:0] address0;
input ce0;
output[DataWidth-1:0] q0;
input we0;
input[DataWidth-1:0] d0;
input[AddressWidth-1:0] address1;
input ce1;
output[DataWidth-1:0] q1;
input we1;
input[DataWidth-1:0] d1;
input clk;
reg[DataWidth-1:0] q0;
reg[DataWidth-1:0] q1;
wire[2 * DataWidth - 1:0] mem_q;
wire[DataWidth - 1:0] mem_q0;
wire[DataWidth - 1:0] mem_q1;
wire[2 - 1:0] mem_we;
wire[2 * DataWidth - 1:0] mem_d;
wire[2 * AddressWidth - 1:0] mem_wa;
wire[2 * AddressWidth - 1:0] mem_ra;
wire[2 - 1:0] mem_ce;
Gaussianblur_a0_core #(
.READ_PORT_COUNT( 2 ),
.WRITE_PORT_COUNT( 2 ),
.DATA_WIDTH( DataWidth ),
.ADDRESS_WIDTH( AddressWidth ),
.WORD_COUNT( AddressRange ))
core_inst (
.q( mem_q ),
.ra( mem_ra ),
.ce( mem_ce ),
.d( mem_d ),
.wa( mem_wa ),
.we( mem_we ),
.clk( clk ));
assign mem_q0 = mem_q[2 * DataWidth - 1 : 1 * DataWidth];
always @ (mem_q0) begin
q0 = mem_q0;
end
assign mem_q1 = mem_q[1 * DataWidth - 1 : 0 * DataWidth];
always @ (mem_q1) begin
q1 = mem_q1;
end
assign mem_ra = {address0, address1};
assign mem_ce = {ce0, ce1};
assign mem_we[1] = we0;
assign mem_we[0] = we1;
assign mem_d = {d0, d1};
assign mem_wa = {address0, address1};
endmodule
|
// ==============================================================
// File generated by AutoESL - High-Level Synthesis System (C, C++, SystemC)
// Version: 2011.1
// Copyright (C) 2011 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module Gaussianblur_a1_core (q, ra, ce, clk
, d, wa, we);
parameter READ_PORT_COUNT=32'd2;
parameter WRITE_PORT_COUNT=32'd2;
parameter DATA_WIDTH=32'd32;
parameter ADDRESS_WIDTH=32'd12;
parameter WORD_COUNT=32'd4096;
output [READ_PORT_COUNT*DATA_WIDTH-1:0] q;
input [READ_PORT_COUNT*ADDRESS_WIDTH-1:0] ra;
input [READ_PORT_COUNT-1:0] ce;
input [WRITE_PORT_COUNT*DATA_WIDTH-1:0] d;
input [WRITE_PORT_COUNT*ADDRESS_WIDTH-1:0] wa;
input [WRITE_PORT_COUNT-1:0] we;
input clk;
integer i,j,k;
reg [DATA_WIDTH-1:0] mem [0:WORD_COUNT-1];
reg [ADDRESS_WIDTH-1:0] rat;
reg [ADDRESS_WIDTH-1:0] rai [READ_PORT_COUNT-1:0];
reg [ADDRESS_WIDTH-1:0] rai_reg [READ_PORT_COUNT-1:0];
reg [READ_PORT_COUNT*DATA_WIDTH-1:0] qi;
reg [DATA_WIDTH-1:0] qt;
reg [DATA_WIDTH-1:0] di [WRITE_PORT_COUNT-1:0];
reg [DATA_WIDTH-1:0] dt;
reg [ADDRESS_WIDTH-1:0] wat;
reg [ADDRESS_WIDTH-1:0] wai [WRITE_PORT_COUNT-1:0];
// Split input data
always @ (d) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<DATA_WIDTH;j=j+1) begin
dt[j]=d[i*DATA_WIDTH+j];
end
di[i]=dt;
end
end
// Split write addresses
always @ (wa) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
wat[j]=wa[i*ADDRESS_WIDTH+j];
end
wai[i]=wat;
end
end
// Write memory
always @ (posedge clk) begin
for (j=0;j<WRITE_PORT_COUNT;j=j+1) begin
if (we[j]) begin
mem[wai[j]] <= di[j];
end
end
end
// Split read addresses
always @ (ra) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
rat[j]=ra[i*ADDRESS_WIDTH+j];
end
rai[i]=rat;
end
end
// guide read addresses using CE
always @ (posedge clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if ( ce[i] ) begin
rai_reg[i] <= rai[i];
end
end
end
// Memory read
genvar x;
generate
for (x = 0; x < READ_PORT_COUNT; x = x + 1) begin : gen_q
assign q[x*DATA_WIDTH+DATA_WIDTH-1:x*DATA_WIDTH] = (rai_reg[x]<WORD_COUNT)?
mem[rai_reg[x]] : {DATA_WIDTH{1'b0}};
end
endgenerate
endmodule
module Gaussianblur_a1 (
address0,
ce0,
q0,
we0,
d0,
address1,
ce1,
q1,
we1,
d1,
clk);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd4096;
parameter AddressWidth = 32'd12;
input[AddressWidth-1:0] address0;
input ce0;
output[DataWidth-1:0] q0;
input we0;
input[DataWidth-1:0] d0;
input[AddressWidth-1:0] address1;
input ce1;
output[DataWidth-1:0] q1;
input we1;
input[DataWidth-1:0] d1;
input clk;
reg[DataWidth-1:0] q0;
reg[DataWidth-1:0] q1;
wire[2 * DataWidth - 1:0] mem_q;
wire[DataWidth - 1:0] mem_q0;
wire[DataWidth - 1:0] mem_q1;
wire[2 - 1:0] mem_we;
wire[2 * DataWidth - 1:0] mem_d;
wire[2 * AddressWidth - 1:0] mem_wa;
wire[2 * AddressWidth - 1:0] mem_ra;
wire[2 - 1:0] mem_ce;
Gaussianblur_a1_core #(
.READ_PORT_COUNT( 2 ),
.WRITE_PORT_COUNT( 2 ),
.DATA_WIDTH( DataWidth ),
.ADDRESS_WIDTH( AddressWidth ),
.WORD_COUNT( AddressRange ))
core_inst (
.q( mem_q ),
.ra( mem_ra ),
.ce( mem_ce ),
.d( mem_d ),
.wa( mem_wa ),
.we( mem_we ),
.clk( clk ));
assign mem_q0 = mem_q[2 * DataWidth - 1 : 1 * DataWidth];
always @ (mem_q0) begin
q0 = mem_q0;
end
assign mem_q1 = mem_q[1 * DataWidth - 1 : 0 * DataWidth];
always @ (mem_q1) begin
q1 = mem_q1;
end
assign mem_ra = {address0, address1};
assign mem_ce = {ce0, ce1};
assign mem_we[1] = we0;
assign mem_we[0] = we1;
assign mem_d = {d0, d1};
assign mem_wa = {address0, address1};
endmodule
|
// ==============================================================
// File generated by AutoESL - High-Level Synthesis System (C, C++, SystemC)
// Version: 2011.1
// Copyright (C) 2011 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module Gaussianblur_b0_core (q, ra, ce, clk
, d, wa, we);
parameter READ_PORT_COUNT=32'd2;
parameter WRITE_PORT_COUNT=32'd2;
parameter DATA_WIDTH=32'd32;
parameter ADDRESS_WIDTH=32'd12;
parameter WORD_COUNT=32'd4096;
output [READ_PORT_COUNT*DATA_WIDTH-1:0] q;
input [READ_PORT_COUNT*ADDRESS_WIDTH-1:0] ra;
input [READ_PORT_COUNT-1:0] ce;
input [WRITE_PORT_COUNT*DATA_WIDTH-1:0] d;
input [WRITE_PORT_COUNT*ADDRESS_WIDTH-1:0] wa;
input [WRITE_PORT_COUNT-1:0] we;
input clk;
integer i,j,k;
reg [DATA_WIDTH-1:0] mem [0:WORD_COUNT-1];
reg [ADDRESS_WIDTH-1:0] rat;
reg [ADDRESS_WIDTH-1:0] rai [READ_PORT_COUNT-1:0];
reg [ADDRESS_WIDTH-1:0] rai_reg [READ_PORT_COUNT-1:0];
reg [READ_PORT_COUNT*DATA_WIDTH-1:0] qi;
reg [DATA_WIDTH-1:0] qt;
reg [DATA_WIDTH-1:0] di [WRITE_PORT_COUNT-1:0];
reg [DATA_WIDTH-1:0] dt;
reg [ADDRESS_WIDTH-1:0] wat;
reg [ADDRESS_WIDTH-1:0] wai [WRITE_PORT_COUNT-1:0];
// Split input data
always @ (d) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<DATA_WIDTH;j=j+1) begin
dt[j]=d[i*DATA_WIDTH+j];
end
di[i]=dt;
end
end
// Split write addresses
always @ (wa) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
wat[j]=wa[i*ADDRESS_WIDTH+j];
end
wai[i]=wat;
end
end
// Write memory
always @ (posedge clk) begin
for (j=0;j<WRITE_PORT_COUNT;j=j+1) begin
if (we[j]) begin
mem[wai[j]] <= di[j];
end
end
end
// Split read addresses
always @ (ra) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
rat[j]=ra[i*ADDRESS_WIDTH+j];
end
rai[i]=rat;
end
end
// guide read addresses using CE
always @ (posedge clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if ( ce[i] ) begin
rai_reg[i] <= rai[i];
end
end
end
// Memory read
genvar x;
generate
for (x = 0; x < READ_PORT_COUNT; x = x + 1) begin : gen_q
assign q[x*DATA_WIDTH+DATA_WIDTH-1:x*DATA_WIDTH] = (rai_reg[x]<WORD_COUNT)?
mem[rai_reg[x]] : {DATA_WIDTH{1'b0}};
end
endgenerate
endmodule
module Gaussianblur_b0 (
address0,
ce0,
q0,
we0,
d0,
address1,
ce1,
q1,
we1,
d1,
clk);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd4096;
parameter AddressWidth = 32'd12;
input[AddressWidth-1:0] address0;
input ce0;
output[DataWidth-1:0] q0;
input we0;
input[DataWidth-1:0] d0;
input[AddressWidth-1:0] address1;
input ce1;
output[DataWidth-1:0] q1;
input we1;
input[DataWidth-1:0] d1;
input clk;
reg[DataWidth-1:0] q0;
reg[DataWidth-1:0] q1;
wire[2 * DataWidth - 1:0] mem_q;
wire[DataWidth - 1:0] mem_q0;
wire[DataWidth - 1:0] mem_q1;
wire[2 - 1:0] mem_we;
wire[2 * DataWidth - 1:0] mem_d;
wire[2 * AddressWidth - 1:0] mem_wa;
wire[2 * AddressWidth - 1:0] mem_ra;
wire[2 - 1:0] mem_ce;
Gaussianblur_b0_core #(
.READ_PORT_COUNT( 2 ),
.WRITE_PORT_COUNT( 2 ),
.DATA_WIDTH( DataWidth ),
.ADDRESS_WIDTH( AddressWidth ),
.WORD_COUNT( AddressRange ))
core_inst (
.q( mem_q ),
.ra( mem_ra ),
.ce( mem_ce ),
.d( mem_d ),
.wa( mem_wa ),
.we( mem_we ),
.clk( clk ));
assign mem_q0 = mem_q[2 * DataWidth - 1 : 1 * DataWidth];
always @ (mem_q0) begin
q0 = mem_q0;
end
assign mem_q1 = mem_q[1 * DataWidth - 1 : 0 * DataWidth];
always @ (mem_q1) begin
q1 = mem_q1;
end
assign mem_ra = {address0, address1};
assign mem_ce = {ce0, ce1};
assign mem_we[1] = we0;
assign mem_we[0] = we1;
assign mem_d = {d0, d1};
assign mem_wa = {address0, address1};
endmodule
|
// ==============================================================
// File generated by AutoESL - High-Level Synthesis System (C, C++, SystemC)
// Version: 2011.1
// Copyright (C) 2011 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module Gaussianblur_b1_core (q, ra, ce, clk
, d, wa, we);
parameter READ_PORT_COUNT=32'd2;
parameter WRITE_PORT_COUNT=32'd2;
parameter DATA_WIDTH=32'd32;
parameter ADDRESS_WIDTH=32'd12;
parameter WORD_COUNT=32'd4096;
output [READ_PORT_COUNT*DATA_WIDTH-1:0] q;
input [READ_PORT_COUNT*ADDRESS_WIDTH-1:0] ra;
input [READ_PORT_COUNT-1:0] ce;
input [WRITE_PORT_COUNT*DATA_WIDTH-1:0] d;
input [WRITE_PORT_COUNT*ADDRESS_WIDTH-1:0] wa;
input [WRITE_PORT_COUNT-1:0] we;
input clk;
integer i,j,k;
reg [DATA_WIDTH-1:0] mem [0:WORD_COUNT-1];
reg [ADDRESS_WIDTH-1:0] rat;
reg [ADDRESS_WIDTH-1:0] rai [READ_PORT_COUNT-1:0];
reg [ADDRESS_WIDTH-1:0] rai_reg [READ_PORT_COUNT-1:0];
reg [READ_PORT_COUNT*DATA_WIDTH-1:0] qi;
reg [DATA_WIDTH-1:0] qt;
reg [DATA_WIDTH-1:0] di [WRITE_PORT_COUNT-1:0];
reg [DATA_WIDTH-1:0] dt;
reg [ADDRESS_WIDTH-1:0] wat;
reg [ADDRESS_WIDTH-1:0] wai [WRITE_PORT_COUNT-1:0];
// Split input data
always @ (d) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<DATA_WIDTH;j=j+1) begin
dt[j]=d[i*DATA_WIDTH+j];
end
di[i]=dt;
end
end
// Split write addresses
always @ (wa) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
wat[j]=wa[i*ADDRESS_WIDTH+j];
end
wai[i]=wat;
end
end
// Write memory
always @ (posedge clk) begin
for (j=0;j<WRITE_PORT_COUNT;j=j+1) begin
if (we[j]) begin
mem[wai[j]] <= di[j];
end
end
end
// Split read addresses
always @ (ra) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
rat[j]=ra[i*ADDRESS_WIDTH+j];
end
rai[i]=rat;
end
end
// guide read addresses using CE
always @ (posedge clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if ( ce[i] ) begin
rai_reg[i] <= rai[i];
end
end
end
// Memory read
genvar x;
generate
for (x = 0; x < READ_PORT_COUNT; x = x + 1) begin : gen_q
assign q[x*DATA_WIDTH+DATA_WIDTH-1:x*DATA_WIDTH] = (rai_reg[x]<WORD_COUNT)?
mem[rai_reg[x]] : {DATA_WIDTH{1'b0}};
end
endgenerate
endmodule
module Gaussianblur_b1 (
address0,
ce0,
q0,
we0,
d0,
address1,
ce1,
q1,
we1,
d1,
clk);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd4096;
parameter AddressWidth = 32'd12;
input[AddressWidth-1:0] address0;
input ce0;
output[DataWidth-1:0] q0;
input we0;
input[DataWidth-1:0] d0;
input[AddressWidth-1:0] address1;
input ce1;
output[DataWidth-1:0] q1;
input we1;
input[DataWidth-1:0] d1;
input clk;
reg[DataWidth-1:0] q0;
reg[DataWidth-1:0] q1;
wire[2 * DataWidth - 1:0] mem_q;
wire[DataWidth - 1:0] mem_q0;
wire[DataWidth - 1:0] mem_q1;
wire[2 - 1:0] mem_we;
wire[2 * DataWidth - 1:0] mem_d;
wire[2 * AddressWidth - 1:0] mem_wa;
wire[2 * AddressWidth - 1:0] mem_ra;
wire[2 - 1:0] mem_ce;
Gaussianblur_b1_core #(
.READ_PORT_COUNT( 2 ),
.WRITE_PORT_COUNT( 2 ),
.DATA_WIDTH( DataWidth ),
.ADDRESS_WIDTH( AddressWidth ),
.WORD_COUNT( AddressRange ))
core_inst (
.q( mem_q ),
.ra( mem_ra ),
.ce( mem_ce ),
.d( mem_d ),
.wa( mem_wa ),
.we( mem_we ),
.clk( clk ));
assign mem_q0 = mem_q[2 * DataWidth - 1 : 1 * DataWidth];
always @ (mem_q0) begin
q0 = mem_q0;
end
assign mem_q1 = mem_q[1 * DataWidth - 1 : 0 * DataWidth];
always @ (mem_q1) begin
q1 = mem_q1;
end
assign mem_ra = {address0, address1};
assign mem_ce = {ce0, ce1};
assign mem_we[1] = we0;
assign mem_we[0] = we1;
assign mem_d = {d0, d1};
assign mem_wa = {address0, address1};
endmodule
|
// ==============================================================
// File generated by AutoESL - High-Level Synthesis System (C, C++, SystemC)
// Version: 2011.1
// Copyright (C) 2011 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module Gaussianblur_c0_core (q, ra, ce, clk
, d, wa, we);
parameter READ_PORT_COUNT=32'd2;
parameter WRITE_PORT_COUNT=32'd2;
parameter DATA_WIDTH=32'd32;
parameter ADDRESS_WIDTH=32'd12;
parameter WORD_COUNT=32'd4096;
output [READ_PORT_COUNT*DATA_WIDTH-1:0] q;
input [READ_PORT_COUNT*ADDRESS_WIDTH-1:0] ra;
input [READ_PORT_COUNT-1:0] ce;
input [WRITE_PORT_COUNT*DATA_WIDTH-1:0] d;
input [WRITE_PORT_COUNT*ADDRESS_WIDTH-1:0] wa;
input [WRITE_PORT_COUNT-1:0] we;
input clk;
integer i,j,k;
reg [DATA_WIDTH-1:0] mem [0:WORD_COUNT-1];
reg [ADDRESS_WIDTH-1:0] rat;
reg [ADDRESS_WIDTH-1:0] rai [READ_PORT_COUNT-1:0];
reg [ADDRESS_WIDTH-1:0] rai_reg [READ_PORT_COUNT-1:0];
reg [READ_PORT_COUNT*DATA_WIDTH-1:0] qi;
reg [DATA_WIDTH-1:0] qt;
reg [DATA_WIDTH-1:0] di [WRITE_PORT_COUNT-1:0];
reg [DATA_WIDTH-1:0] dt;
reg [ADDRESS_WIDTH-1:0] wat;
reg [ADDRESS_WIDTH-1:0] wai [WRITE_PORT_COUNT-1:0];
// Split input data
always @ (d) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<DATA_WIDTH;j=j+1) begin
dt[j]=d[i*DATA_WIDTH+j];
end
di[i]=dt;
end
end
// Split write addresses
always @ (wa) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
wat[j]=wa[i*ADDRESS_WIDTH+j];
end
wai[i]=wat;
end
end
// Write memory
always @ (posedge clk) begin
for (j=0;j<WRITE_PORT_COUNT;j=j+1) begin
if (we[j]) begin
mem[wai[j]] <= di[j];
end
end
end
// Split read addresses
always @ (ra) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
rat[j]=ra[i*ADDRESS_WIDTH+j];
end
rai[i]=rat;
end
end
// guide read addresses using CE
always @ (posedge clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if ( ce[i] ) begin
rai_reg[i] <= rai[i];
end
end
end
// Memory read
genvar x;
generate
for (x = 0; x < READ_PORT_COUNT; x = x + 1) begin : gen_q
assign q[x*DATA_WIDTH+DATA_WIDTH-1:x*DATA_WIDTH] = (rai_reg[x]<WORD_COUNT)?
mem[rai_reg[x]] : {DATA_WIDTH{1'b0}};
end
endgenerate
endmodule
module Gaussianblur_c0 (
address0,
ce0,
q0,
we0,
d0,
address1,
ce1,
q1,
we1,
d1,
clk);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd4096;
parameter AddressWidth = 32'd12;
input[AddressWidth-1:0] address0;
input ce0;
output[DataWidth-1:0] q0;
input we0;
input[DataWidth-1:0] d0;
input[AddressWidth-1:0] address1;
input ce1;
output[DataWidth-1:0] q1;
input we1;
input[DataWidth-1:0] d1;
input clk;
reg[DataWidth-1:0] q0;
reg[DataWidth-1:0] q1;
wire[2 * DataWidth - 1:0] mem_q;
wire[DataWidth - 1:0] mem_q0;
wire[DataWidth - 1:0] mem_q1;
wire[2 - 1:0] mem_we;
wire[2 * DataWidth - 1:0] mem_d;
wire[2 * AddressWidth - 1:0] mem_wa;
wire[2 * AddressWidth - 1:0] mem_ra;
wire[2 - 1:0] mem_ce;
Gaussianblur_c0_core #(
.READ_PORT_COUNT( 2 ),
.WRITE_PORT_COUNT( 2 ),
.DATA_WIDTH( DataWidth ),
.ADDRESS_WIDTH( AddressWidth ),
.WORD_COUNT( AddressRange ))
core_inst (
.q( mem_q ),
.ra( mem_ra ),
.ce( mem_ce ),
.d( mem_d ),
.wa( mem_wa ),
.we( mem_we ),
.clk( clk ));
assign mem_q0 = mem_q[2 * DataWidth - 1 : 1 * DataWidth];
always @ (mem_q0) begin
q0 = mem_q0;
end
assign mem_q1 = mem_q[1 * DataWidth - 1 : 0 * DataWidth];
always @ (mem_q1) begin
q1 = mem_q1;
end
assign mem_ra = {address0, address1};
assign mem_ce = {ce0, ce1};
assign mem_we[1] = we0;
assign mem_we[0] = we1;
assign mem_d = {d0, d1};
assign mem_wa = {address0, address1};
endmodule
|
// ==============================================================
// File generated by AutoESL - High-Level Synthesis System (C, C++, SystemC)
// Version: 2011.1
// Copyright (C) 2011 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module Gaussianblur_c1_core (q, ra, ce, clk
, d, wa, we);
parameter READ_PORT_COUNT=32'd2;
parameter WRITE_PORT_COUNT=32'd2;
parameter DATA_WIDTH=32'd32;
parameter ADDRESS_WIDTH=32'd12;
parameter WORD_COUNT=32'd4096;
output [READ_PORT_COUNT*DATA_WIDTH-1:0] q;
input [READ_PORT_COUNT*ADDRESS_WIDTH-1:0] ra;
input [READ_PORT_COUNT-1:0] ce;
input [WRITE_PORT_COUNT*DATA_WIDTH-1:0] d;
input [WRITE_PORT_COUNT*ADDRESS_WIDTH-1:0] wa;
input [WRITE_PORT_COUNT-1:0] we;
input clk;
integer i,j,k;
reg [DATA_WIDTH-1:0] mem [0:WORD_COUNT-1];
reg [ADDRESS_WIDTH-1:0] rat;
reg [ADDRESS_WIDTH-1:0] rai [READ_PORT_COUNT-1:0];
reg [ADDRESS_WIDTH-1:0] rai_reg [READ_PORT_COUNT-1:0];
reg [READ_PORT_COUNT*DATA_WIDTH-1:0] qi;
reg [DATA_WIDTH-1:0] qt;
reg [DATA_WIDTH-1:0] di [WRITE_PORT_COUNT-1:0];
reg [DATA_WIDTH-1:0] dt;
reg [ADDRESS_WIDTH-1:0] wat;
reg [ADDRESS_WIDTH-1:0] wai [WRITE_PORT_COUNT-1:0];
// Split input data
always @ (d) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<DATA_WIDTH;j=j+1) begin
dt[j]=d[i*DATA_WIDTH+j];
end
di[i]=dt;
end
end
// Split write addresses
always @ (wa) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
wat[j]=wa[i*ADDRESS_WIDTH+j];
end
wai[i]=wat;
end
end
// Write memory
always @ (posedge clk) begin
for (j=0;j<WRITE_PORT_COUNT;j=j+1) begin
if (we[j]) begin
mem[wai[j]] <= di[j];
end
end
end
// Split read addresses
always @ (ra) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
rat[j]=ra[i*ADDRESS_WIDTH+j];
end
rai[i]=rat;
end
end
// guide read addresses using CE
always @ (posedge clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if ( ce[i] ) begin
rai_reg[i] <= rai[i];
end
end
end
// Memory read
genvar x;
generate
for (x = 0; x < READ_PORT_COUNT; x = x + 1) begin : gen_q
assign q[x*DATA_WIDTH+DATA_WIDTH-1:x*DATA_WIDTH] = (rai_reg[x]<WORD_COUNT)?
mem[rai_reg[x]] : {DATA_WIDTH{1'b0}};
end
endgenerate
endmodule
module Gaussianblur_c1 (
address0,
ce0,
q0,
we0,
d0,
address1,
ce1,
q1,
we1,
d1,
clk);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd4096;
parameter AddressWidth = 32'd12;
input[AddressWidth-1:0] address0;
input ce0;
output[DataWidth-1:0] q0;
input we0;
input[DataWidth-1:0] d0;
input[AddressWidth-1:0] address1;
input ce1;
output[DataWidth-1:0] q1;
input we1;
input[DataWidth-1:0] d1;
input clk;
reg[DataWidth-1:0] q0;
reg[DataWidth-1:0] q1;
wire[2 * DataWidth - 1:0] mem_q;
wire[DataWidth - 1:0] mem_q0;
wire[DataWidth - 1:0] mem_q1;
wire[2 - 1:0] mem_we;
wire[2 * DataWidth - 1:0] mem_d;
wire[2 * AddressWidth - 1:0] mem_wa;
wire[2 * AddressWidth - 1:0] mem_ra;
wire[2 - 1:0] mem_ce;
Gaussianblur_c1_core #(
.READ_PORT_COUNT( 2 ),
.WRITE_PORT_COUNT( 2 ),
.DATA_WIDTH( DataWidth ),
.ADDRESS_WIDTH( AddressWidth ),
.WORD_COUNT( AddressRange ))
core_inst (
.q( mem_q ),
.ra( mem_ra ),
.ce( mem_ce ),
.d( mem_d ),
.wa( mem_wa ),
.we( mem_we ),
.clk( clk ));
assign mem_q0 = mem_q[2 * DataWidth - 1 : 1 * DataWidth];
always @ (mem_q0) begin
q0 = mem_q0;
end
assign mem_q1 = mem_q[1 * DataWidth - 1 : 0 * DataWidth];
always @ (mem_q1) begin
q1 = mem_q1;
end
assign mem_ra = {address0, address1};
assign mem_ce = {ce0, ce1};
assign mem_we[1] = we0;
assign mem_we[0] = we1;
assign mem_d = {d0, d1};
assign mem_wa = {address0, address1};
endmodule
|
// ==============================================================
// File generated by AutoESL - High-Level Synthesis System (C, C++, SystemC)
// Version: 2011.1
// Copyright (C) 2011 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module Gaussianblur_d0_core (q, ra, ce, clk
, d, wa, we);
parameter READ_PORT_COUNT=32'd2;
parameter WRITE_PORT_COUNT=32'd2;
parameter DATA_WIDTH=32'd32;
parameter ADDRESS_WIDTH=32'd12;
parameter WORD_COUNT=32'd4096;
output [READ_PORT_COUNT*DATA_WIDTH-1:0] q;
input [READ_PORT_COUNT*ADDRESS_WIDTH-1:0] ra;
input [READ_PORT_COUNT-1:0] ce;
input [WRITE_PORT_COUNT*DATA_WIDTH-1:0] d;
input [WRITE_PORT_COUNT*ADDRESS_WIDTH-1:0] wa;
input [WRITE_PORT_COUNT-1:0] we;
input clk;
integer i,j,k;
reg [DATA_WIDTH-1:0] mem [0:WORD_COUNT-1];
reg [ADDRESS_WIDTH-1:0] rat;
reg [ADDRESS_WIDTH-1:0] rai [READ_PORT_COUNT-1:0];
reg [ADDRESS_WIDTH-1:0] rai_reg [READ_PORT_COUNT-1:0];
reg [READ_PORT_COUNT*DATA_WIDTH-1:0] qi;
reg [DATA_WIDTH-1:0] qt;
reg [DATA_WIDTH-1:0] di [WRITE_PORT_COUNT-1:0];
reg [DATA_WIDTH-1:0] dt;
reg [ADDRESS_WIDTH-1:0] wat;
reg [ADDRESS_WIDTH-1:0] wai [WRITE_PORT_COUNT-1:0];
// Split input data
always @ (d) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<DATA_WIDTH;j=j+1) begin
dt[j]=d[i*DATA_WIDTH+j];
end
di[i]=dt;
end
end
// Split write addresses
always @ (wa) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
wat[j]=wa[i*ADDRESS_WIDTH+j];
end
wai[i]=wat;
end
end
// Write memory
always @ (posedge clk) begin
for (j=0;j<WRITE_PORT_COUNT;j=j+1) begin
if (we[j]) begin
mem[wai[j]] <= di[j];
end
end
end
// Split read addresses
always @ (ra) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
rat[j]=ra[i*ADDRESS_WIDTH+j];
end
rai[i]=rat;
end
end
// guide read addresses using CE
always @ (posedge clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if ( ce[i] ) begin
rai_reg[i] <= rai[i];
end
end
end
// Memory read
genvar x;
generate
for (x = 0; x < READ_PORT_COUNT; x = x + 1) begin : gen_q
assign q[x*DATA_WIDTH+DATA_WIDTH-1:x*DATA_WIDTH] = (rai_reg[x]<WORD_COUNT)?
mem[rai_reg[x]] : {DATA_WIDTH{1'b0}};
end
endgenerate
endmodule
module Gaussianblur_d0 (
address0,
ce0,
q0,
we0,
d0,
address1,
ce1,
q1,
we1,
d1,
clk);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd4096;
parameter AddressWidth = 32'd12;
input[AddressWidth-1:0] address0;
input ce0;
output[DataWidth-1:0] q0;
input we0;
input[DataWidth-1:0] d0;
input[AddressWidth-1:0] address1;
input ce1;
output[DataWidth-1:0] q1;
input we1;
input[DataWidth-1:0] d1;
input clk;
reg[DataWidth-1:0] q0;
reg[DataWidth-1:0] q1;
wire[2 * DataWidth - 1:0] mem_q;
wire[DataWidth - 1:0] mem_q0;
wire[DataWidth - 1:0] mem_q1;
wire[2 - 1:0] mem_we;
wire[2 * DataWidth - 1:0] mem_d;
wire[2 * AddressWidth - 1:0] mem_wa;
wire[2 * AddressWidth - 1:0] mem_ra;
wire[2 - 1:0] mem_ce;
Gaussianblur_d0_core #(
.READ_PORT_COUNT( 2 ),
.WRITE_PORT_COUNT( 2 ),
.DATA_WIDTH( DataWidth ),
.ADDRESS_WIDTH( AddressWidth ),
.WORD_COUNT( AddressRange ))
core_inst (
.q( mem_q ),
.ra( mem_ra ),
.ce( mem_ce ),
.d( mem_d ),
.wa( mem_wa ),
.we( mem_we ),
.clk( clk ));
assign mem_q0 = mem_q[2 * DataWidth - 1 : 1 * DataWidth];
always @ (mem_q0) begin
q0 = mem_q0;
end
assign mem_q1 = mem_q[1 * DataWidth - 1 : 0 * DataWidth];
always @ (mem_q1) begin
q1 = mem_q1;
end
assign mem_ra = {address0, address1};
assign mem_ce = {ce0, ce1};
assign mem_we[1] = we0;
assign mem_we[0] = we1;
assign mem_d = {d0, d1};
assign mem_wa = {address0, address1};
endmodule
|
// ==============================================================
// File generated by AutoESL - High-Level Synthesis System (C, C++, SystemC)
// Version: 2011.1
// Copyright (C) 2011 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module Gaussianblur_d1_core (q, ra, ce, clk
, d, wa, we);
parameter READ_PORT_COUNT=32'd2;
parameter WRITE_PORT_COUNT=32'd2;
parameter DATA_WIDTH=32'd32;
parameter ADDRESS_WIDTH=32'd12;
parameter WORD_COUNT=32'd4096;
output [READ_PORT_COUNT*DATA_WIDTH-1:0] q;
input [READ_PORT_COUNT*ADDRESS_WIDTH-1:0] ra;
input [READ_PORT_COUNT-1:0] ce;
input [WRITE_PORT_COUNT*DATA_WIDTH-1:0] d;
input [WRITE_PORT_COUNT*ADDRESS_WIDTH-1:0] wa;
input [WRITE_PORT_COUNT-1:0] we;
input clk;
integer i,j,k;
reg [DATA_WIDTH-1:0] mem [0:WORD_COUNT-1];
reg [ADDRESS_WIDTH-1:0] rat;
reg [ADDRESS_WIDTH-1:0] rai [READ_PORT_COUNT-1:0];
reg [ADDRESS_WIDTH-1:0] rai_reg [READ_PORT_COUNT-1:0];
reg [READ_PORT_COUNT*DATA_WIDTH-1:0] qi;
reg [DATA_WIDTH-1:0] qt;
reg [DATA_WIDTH-1:0] di [WRITE_PORT_COUNT-1:0];
reg [DATA_WIDTH-1:0] dt;
reg [ADDRESS_WIDTH-1:0] wat;
reg [ADDRESS_WIDTH-1:0] wai [WRITE_PORT_COUNT-1:0];
// Split input data
always @ (d) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<DATA_WIDTH;j=j+1) begin
dt[j]=d[i*DATA_WIDTH+j];
end
di[i]=dt;
end
end
// Split write addresses
always @ (wa) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
wat[j]=wa[i*ADDRESS_WIDTH+j];
end
wai[i]=wat;
end
end
// Write memory
always @ (posedge clk) begin
for (j=0;j<WRITE_PORT_COUNT;j=j+1) begin
if (we[j]) begin
mem[wai[j]] <= di[j];
end
end
end
// Split read addresses
always @ (ra) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
rat[j]=ra[i*ADDRESS_WIDTH+j];
end
rai[i]=rat;
end
end
// guide read addresses using CE
always @ (posedge clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if ( ce[i] ) begin
rai_reg[i] <= rai[i];
end
end
end
// Memory read
genvar x;
generate
for (x = 0; x < READ_PORT_COUNT; x = x + 1) begin : gen_q
assign q[x*DATA_WIDTH+DATA_WIDTH-1:x*DATA_WIDTH] = (rai_reg[x]<WORD_COUNT)?
mem[rai_reg[x]] : {DATA_WIDTH{1'b0}};
end
endgenerate
endmodule
module Gaussianblur_d1 (
address0,
ce0,
q0,
we0,
d0,
address1,
ce1,
q1,
we1,
d1,
clk);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd4096;
parameter AddressWidth = 32'd12;
input[AddressWidth-1:0] address0;
input ce0;
output[DataWidth-1:0] q0;
input we0;
input[DataWidth-1:0] d0;
input[AddressWidth-1:0] address1;
input ce1;
output[DataWidth-1:0] q1;
input we1;
input[DataWidth-1:0] d1;
input clk;
reg[DataWidth-1:0] q0;
reg[DataWidth-1:0] q1;
wire[2 * DataWidth - 1:0] mem_q;
wire[DataWidth - 1:0] mem_q0;
wire[DataWidth - 1:0] mem_q1;
wire[2 - 1:0] mem_we;
wire[2 * DataWidth - 1:0] mem_d;
wire[2 * AddressWidth - 1:0] mem_wa;
wire[2 * AddressWidth - 1:0] mem_ra;
wire[2 - 1:0] mem_ce;
Gaussianblur_d1_core #(
.READ_PORT_COUNT( 2 ),
.WRITE_PORT_COUNT( 2 ),
.DATA_WIDTH( DataWidth ),
.ADDRESS_WIDTH( AddressWidth ),
.WORD_COUNT( AddressRange ))
core_inst (
.q( mem_q ),
.ra( mem_ra ),
.ce( mem_ce ),
.d( mem_d ),
.wa( mem_wa ),
.we( mem_we ),
.clk( clk ));
assign mem_q0 = mem_q[2 * DataWidth - 1 : 1 * DataWidth];
always @ (mem_q0) begin
q0 = mem_q0;
end
assign mem_q1 = mem_q[1 * DataWidth - 1 : 0 * DataWidth];
always @ (mem_q1) begin
q1 = mem_q1;
end
assign mem_ra = {address0, address1};
assign mem_ce = {ce0, ce1};
assign mem_we[1] = we0;
assign mem_we[0] = we1;
assign mem_d = {d0, d1};
assign mem_wa = {address0, address1};
endmodule
|
// ==============================================================
// File generated by AutoESL - High-Level Synthesis System (C, C++, SystemC)
// Version: 2011.1
// Copyright (C) 2011 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module Gaussianblur_grp_fu_220_ACMP_faddfsub_30(
clk,
reset,
ce,
din0,
din1,
opcode,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
input[2 - 1:0] opcode;
output[dout_WIDTH - 1:0] dout;
ACMP_faddfsub #(
.ID( ID ),
.NUM_STAGE( 5 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_faddfsub_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ),
.opcode( opcode ));
endmodule
|
// ==============================================================
// File generated by AutoESL - High-Level Synthesis System (C, C++, SystemC)
// Version: 2011.1
// Copyright (C) 2011 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module Gaussianblur_grp_fu_226_ACMP_fmul_31(
clk,
reset,
ce,
din0,
din1,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
output[dout_WIDTH - 1:0] dout;
ACMP_fmul #(
.ID( ID ),
.NUM_STAGE( 4 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_fmul_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ));
endmodule
|
// ==============================================================
// File generated by AutoESL - High-Level Synthesis System (C, C++, SystemC)
// Version: 2011.1
// Copyright (C) 2011 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module Gaussianblur_grp_fu_235_ACMP_fdiv_32(
clk,
reset,
ce,
din0,
din1,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
output[dout_WIDTH - 1:0] dout;
ACMP_fdiv #(
.ID( ID ),
.NUM_STAGE( 10 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_fdiv_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ));
endmodule
|
// ==============================================================
// File generated by AutoESL - High-Level Synthesis System (C, C++, SystemC)
// Version: 2011.1
// Copyright (C) 2011 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module Gaussianblur_grp_fu_241_ACMP_fdiv_33(
clk,
reset,
ce,
din0,
din1,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
output[dout_WIDTH - 1:0] dout;
ACMP_fdiv #(
.ID( ID ),
.NUM_STAGE( 10 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_fdiv_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ));
endmodule
|
// ==============================================================
// File generated by AutoESL - High-Level Synthesis System (C, C++, SystemC)
// Version: 2011.1
// Copyright (C) 2011 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module Gaussianblur_grp_fu_245_ACMP_fsqrt_34(
clk,
reset,
ce,
din0,
din1,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
output[dout_WIDTH - 1:0] dout;
ACMP_fsqrt #(
.ID( ID ),
.NUM_STAGE( 10 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_fsqrt_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ));
endmodule
|
// ==============================================================
// RTL generated by AutoESL - High-Level Synthesis System (C, C++, SystemC)
// Version: 2011.1
// Copyright (C) 2011 Xilinx Inc. All rights reserved.
//
// ===========================================================
`timescale 1 ns / 1 ps
module step0 (
ap_clk,
ap_rst,
ap_start,
ap_done,
ap_idle,
tag,
counter,
a_address0,
a_ce0,
a_we0,
a_d0,
a_q0,
a_address1,
a_ce1,
a_we1,
a_d1,
a_q1,
b_address0,
b_ce0,
b_we0,
b_d0,
b_q0,
b_address1,
b_ce1,
b_we1,
b_d1,
b_q1,
BoundryScale,
nu
);
input ap_clk;
input ap_rst;
input ap_start;
output ap_done;
output ap_idle;
input [1:0] tag;
input [6:0] counter;
output [11:0] a_address0;
output a_ce0;
output a_we0;
output [31:0] a_d0;
input [31:0] a_q0;
output [11:0] a_address1;
output a_ce1;
output a_we1;
output [31:0] a_d1;
input [31:0] a_q1;
output [11:0] b_address0;
output b_ce0;
output b_we0;
output [31:0] b_d0;
input [31:0] b_q0;
output [11:0] b_address1;
output b_ce1;
output b_we1;
output [31:0] b_d1;
input [31:0] b_q1;
input [31:0] BoundryScale;
input [31:0] nu;
reg ap_done;
reg ap_idle;
reg[11:0] a_address0;
reg a_ce0;
reg a_we0;
reg[31:0] a_d0;
reg[11:0] a_address1;
reg a_ce1;
reg a_we1;
reg[31:0] a_d1;
reg[11:0] b_address0;
reg b_ce0;
reg b_we0;
reg[31:0] b_d0;
reg[11:0] b_address1;
reg b_ce1;
reg b_we1;
reg[31:0] b_d1;
reg [6:0] ap_CS_fsm;
reg [6:0] i_reg_1886;
reg [8:0] indvar_flatten_reg_1897;
reg [6:0] j_reg_1908;
reg [3:0] indvar3_reg_1919;
reg [6:0] i_1_reg_1930;
reg [6:0] i_2_reg_1941;
reg [8:0] indvar_flatten1_reg_1952;
reg [6:0] j_1_reg_1963;
reg [3:0] indvar6_reg_1974;
reg [6:0] i_3_reg_1985;
reg [6:0] j_2_reg_1996;
reg [8:0] indvar_flatten2_reg_2007;
reg [6:0] i_4_reg_2018;
reg [3:0] indvar9_reg_2029;
reg [6:0] j_3_reg_2040;
reg [6:0] j_4_reg_2051;
reg [8:0] indvar_flatten3_reg_2062;
reg [6:0] i_5_reg_2073;
reg [3:0] indvar4_reg_2084;
reg [6:0] j_5_reg_2095;
reg [6:0] indvar_flatten4_reg_2106;
reg [6:0] i_6_reg_2120;
reg [3:0] indvar_reg_2134;
reg [6:0] j_6_reg_2148;
reg [31:0] reg_2171;
reg ap_reg_ppiten_pp0_it1;
reg ap_reg_ppiten_pp0_it0;
reg ap_reg_ppiten_pp0_it2;
reg ap_reg_ppiten_pp0_it3;
reg ap_reg_ppiten_pp0_it4;
reg ap_reg_ppiten_pp0_it5;
reg ap_reg_ppiten_pp0_it6;
reg [0:0] exitcond1_reg_5171;
reg ap_reg_ppiten_pp1_it0;
reg ap_reg_ppiten_pp1_it1;
reg ap_reg_ppiten_pp1_it2;
reg [0:0] exitcond3_reg_5195;
reg ap_reg_ppiten_pp3_it0;
reg ap_reg_ppiten_pp3_it1;
reg ap_reg_ppiten_pp3_it2;
reg [0:0] exitcond6_reg_5446;
reg ap_reg_ppiten_pp4_it1;
reg ap_reg_ppiten_pp4_it0;
reg ap_reg_ppiten_pp4_it2;
reg ap_reg_ppiten_pp4_it3;
reg ap_reg_ppiten_pp4_it4;
reg ap_reg_ppiten_pp4_it5;
reg ap_reg_ppiten_pp4_it6;
reg [0:0] exitcond7_reg_5678;
reg ap_reg_ppiten_pp5_it0;
reg ap_reg_ppiten_pp5_it1;
reg ap_reg_ppiten_pp5_it2;
reg [0:0] exitcond9_reg_5697;
reg ap_reg_ppiten_pp7_it0;
reg ap_reg_ppiten_pp7_it1;
reg ap_reg_ppiten_pp7_it2;
reg [0:0] exitcond12_reg_5924;
wire [31:0] grp_fu_2167_p2;
reg [31:0] reg_2177;
reg [0:0] ap_reg_ppstg_exitcond1_reg_5171_pp0_it4;
reg ap_reg_ppiten_pp2_it5;
reg ap_reg_ppiten_pp2_it0;
reg ap_reg_ppiten_pp2_it1;
reg ap_reg_ppiten_pp2_it2;
reg ap_reg_ppiten_pp2_it3;
reg ap_reg_ppiten_pp2_it4;
reg ap_reg_ppiten_pp2_it6;
reg [0:0] exitcond4_reg_5427;
reg [0:0] ap_reg_ppstg_exitcond4_reg_5427_pp2_it4;
reg [0:0] ap_reg_ppstg_exitcond7_reg_5678_pp4_it4;
reg ap_reg_ppiten_pp6_it5;
reg ap_reg_ppiten_pp6_it0;
reg ap_reg_ppiten_pp6_it1;
reg ap_reg_ppiten_pp6_it2;
reg ap_reg_ppiten_pp6_it3;
reg ap_reg_ppiten_pp6_it4;
reg ap_reg_ppiten_pp6_it6;
reg [0:0] exitcond10_reg_5905;
reg [0:0] ap_reg_ppstg_exitcond10_reg_5905_pp6_it4;
reg [31:0] reg_2184;
reg [31:0] reg_2190;
reg [31:0] reg_2197;
reg [31:0] reg_2204;
reg [31:0] reg_2211;
reg [31:0] reg_2218;
reg [31:0] reg_2225;
reg [31:0] reg_2232;
reg [31:0] reg_2239;
reg [31:0] reg_2246;
reg [31:0] reg_2253;
reg [31:0] reg_2260;
reg [0:0] ap_reg_ppstg_exitcond6_reg_5446_pp3_it1;
reg [0:0] ap_reg_ppstg_exitcond12_reg_5924_pp7_it1;
reg [31:0] reg_2267;
reg [31:0] reg_2274;
reg [31:0] reg_2279;
reg ap_reg_ppiten_pp1_it3;
reg ap_reg_ppiten_pp3_it3;
reg ap_reg_ppiten_pp5_it3;
reg ap_reg_ppiten_pp7_it3;
reg [31:0] reg_2284;
reg [0:0] ap_reg_ppstg_exitcond3_reg_5195_pp1_it1;
reg [0:0] ap_reg_ppstg_exitcond9_reg_5697_pp5_it1;
reg [31:0] reg_2289;
wire [31:0] grp_fu_2163_p2;
reg [31:0] reg_2294;
reg [31:0] reg_2300;
reg [31:0] reg_2305;
reg [31:0] reg_2311;
reg [31:0] reg_2318;
reg [31:0] reg_2323;
reg [31:0] reg_2330;
reg [31:0] reg_2335;
reg [31:0] reg_2341;
reg [0:0] ap_reg_ppstg_exitcond3_reg_5195_pp1_it2;
reg [0:0] ap_reg_ppstg_exitcond6_reg_5446_pp3_it2;
reg [0:0] ap_reg_ppstg_exitcond9_reg_5697_pp5_it2;
reg [0:0] ap_reg_ppstg_exitcond12_reg_5924_pp7_it2;
reg [31:0] reg_2347;
wire [0:0] or_cond_fu_2365_p2;
wire [0:0] tmp_2_fu_2371_p2;
wire [0:0] exitcond1_fu_2377_p2;
reg [0:0] ap_reg_ppstg_exitcond1_reg_5171_pp0_it1;
reg [0:0] ap_reg_ppstg_exitcond1_reg_5171_pp0_it2;
reg [0:0] ap_reg_ppstg_exitcond1_reg_5171_pp0_it3;
reg [0:0] ap_reg_ppstg_exitcond1_reg_5171_pp0_it5;
reg [6:0] tmp_5_reg_5175;
wire [63:0] tmp_6_fu_2399_p1;
reg [63:0] tmp_6_reg_5180;
reg [63:0] ap_reg_ppstg_tmp_6_reg_5180_pp0_it1;
reg [63:0] ap_reg_ppstg_tmp_6_reg_5180_pp0_it2;
reg [63:0] ap_reg_ppstg_tmp_6_reg_5180_pp0_it3;
reg [63:0] ap_reg_ppstg_tmp_6_reg_5180_pp0_it4;
reg [63:0] ap_reg_ppstg_tmp_6_reg_5180_pp0_it5;
wire [0:0] exitcond3_fu_2404_p2;
reg [8:0] indvar_flatten_next_reg_5199;
wire [6:0] i_1_mid2_fu_2422_p3;
reg [6:0] i_1_mid2_reg_5204;
wire [6:0] j_mid2_fu_2436_p3;
reg [6:0] j_mid2_reg_5216;
reg [5:0] j_cast_reg_5221;
wire [13:0] tmp_6_trn_cast_fu_2452_p1;
reg [13:0] tmp_6_trn_cast_reg_5226;
wire [63:0] tmp_9_fu_2472_p1;
reg [63:0] tmp_9_reg_5237;
reg [63:0] ap_reg_ppstg_tmp_9_reg_5237_pp1_it1;
reg [6:0] a_addr100_reg_5247;
reg [3:0] indvar_next3_reg_5252;
wire [12:0] tmp_8_trn_cast_fu_2500_p1;
reg [12:0] tmp_8_trn_cast_reg_5257;
wire [63:0] tmp_15_fu_2560_p1;
reg [63:0] tmp_15_reg_5272;
reg [63:0] ap_reg_ppstg_tmp_15_reg_5272_pp1_it1;
wire [63:0] tmp_20_fu_2626_p1;
reg [63:0] tmp_20_reg_5287;
reg [63:0] ap_reg_ppstg_tmp_20_reg_5287_pp1_it1;
wire [6:0] b_addr4_fu_2645_p2;
reg [6:0] b_addr4_reg_5297;
reg [6:0] tmp_8_trn_cast4_reg_5302;
reg [6:0] tmp_8_trn_cast5_reg_5307;
reg [6:0] tmp_8_trn_cast6_reg_5312;
reg [6:0] tmp_8_trn_cast7_reg_5317;
reg [6:0] tmp_8_trn_cast8_reg_5322;
wire [63:0] tmp_28_fu_2740_p1;
reg [63:0] tmp_28_reg_5332;
reg [63:0] ap_reg_ppstg_tmp_28_reg_5332_pp1_it1;
wire [63:0] tmp_36_fu_2794_p1;
reg [63:0] tmp_36_reg_5347;
reg [63:0] ap_reg_ppstg_tmp_36_reg_5347_pp1_it1;
wire [6:0] b_addr8_fu_2803_p2;
reg [6:0] b_addr8_reg_5357;
wire [63:0] tmp_44_fu_2847_p1;
reg [63:0] tmp_44_reg_5367;
reg [63:0] ap_reg_ppstg_tmp_44_reg_5367_pp1_it1;
reg [63:0] ap_reg_ppstg_tmp_44_reg_5367_pp1_it2;
reg [13:0] a_addr23_reg_5382;
reg [13:0] a_addr25_reg_5392;
reg [6:0] tmp_43_reg_5402;
wire [63:0] tmp_47_fu_2980_p1;
reg [63:0] tmp_47_reg_5407;
reg [63:0] ap_reg_ppstg_tmp_47_reg_5407_pp1_it2;
wire [63:0] tmp_51_fu_2984_p1;
reg [63:0] tmp_51_reg_5417;
reg [63:0] ap_reg_ppstg_tmp_51_reg_5417_pp1_it2;
wire [0:0] exitcond4_fu_2988_p2;
reg [0:0] ap_reg_ppstg_exitcond4_reg_5427_pp2_it1;
reg [0:0] ap_reg_ppstg_exitcond4_reg_5427_pp2_it2;
reg [0:0] ap_reg_ppstg_exitcond4_reg_5427_pp2_it3;
reg [0:0] ap_reg_ppstg_exitcond4_reg_5427_pp2_it5;
reg [6:0] tmp_10_reg_5431;
wire [63:0] tmp_59_fu_3020_p1;
reg [63:0] tmp_59_reg_5436;
reg [63:0] ap_reg_ppstg_tmp_59_reg_5436_pp2_it1;
reg [63:0] ap_reg_ppstg_tmp_59_reg_5436_pp2_it2;
reg [63:0] ap_reg_ppstg_tmp_59_reg_5436_pp2_it3;
reg [63:0] ap_reg_ppstg_tmp_59_reg_5436_pp2_it4;
reg [63:0] ap_reg_ppstg_tmp_59_reg_5436_pp2_it5;
wire [0:0] exitcond6_fu_3025_p2;
reg [8:0] indvar_flatten_next1_reg_5450;
wire [6:0] i_3_mid2_fu_3043_p3;
reg [6:0] i_3_mid2_reg_5455;
wire [6:0] j_1_mid2_fu_3057_p3;
reg [6:0] j_1_mid2_reg_5467;
reg [5:0] j_1_cast_reg_5472;
reg [13:0] tmp_44_trn_cast_reg_5477;
wire [63:0] tmp_67_fu_3093_p1;
reg [63:0] tmp_67_reg_5488;
reg [63:0] ap_reg_ppstg_tmp_67_reg_5488_pp3_it1;
reg [6:0] b_addr53_reg_5498;
reg [3:0] indvar_next6_reg_5503;
wire [12:0] tmp_46_trn_cast_fu_3121_p1;
reg [12:0] tmp_46_trn_cast_reg_5508;
wire [63:0] tmp_75_fu_3181_p1;
reg [63:0] tmp_75_reg_5523;
reg [63:0] ap_reg_ppstg_tmp_75_reg_5523_pp3_it1;
wire [63:0] tmp_83_fu_3247_p1;
reg [63:0] tmp_83_reg_5538;
reg [63:0] ap_reg_ppstg_tmp_83_reg_5538_pp3_it1;
wire [6:0] a_addr112_fu_3266_p2;
reg [6:0] a_addr112_reg_5548;
reg [6:0] tmp_46_trn_cast4_reg_5553;
reg [6:0] tmp_46_trn_cast5_reg_5558;
reg [6:0] tmp_46_trn_cast6_reg_5563;
reg [6:0] tmp_46_trn_cast7_reg_5568;
reg [6:0] tmp_46_trn_cast8_reg_5573;
wire [63:0] tmp_86_fu_3361_p1;
reg [63:0] tmp_86_reg_5583;
reg [63:0] ap_reg_ppstg_tmp_86_reg_5583_pp3_it1;
wire [63:0] tmp_90_fu_3415_p1;
reg [63:0] tmp_90_reg_5598;
reg [63:0] ap_reg_ppstg_tmp_90_reg_5598_pp3_it1;
wire [6:0] a_addr116_fu_3424_p2;
reg [6:0] a_addr116_reg_5608;
wire [63:0] tmp_98_fu_3468_p1;
reg [63:0] tmp_98_reg_5618;
reg [63:0] ap_reg_ppstg_tmp_98_reg_5618_pp3_it1;
reg [63:0] ap_reg_ppstg_tmp_98_reg_5618_pp3_it2;
reg [13:0] b_addr23_reg_5633;
reg [13:0] b_addr25_reg_5643;
reg [6:0] tmp_82_reg_5653;
wire [63:0] tmp_106_fu_3601_p1;
reg [63:0] tmp_106_reg_5658;
reg [63:0] ap_reg_ppstg_tmp_106_reg_5658_pp3_it2;
wire [63:0] tmp_114_fu_3605_p1;
reg [63:0] tmp_114_reg_5668;
reg [63:0] ap_reg_ppstg_tmp_114_reg_5668_pp3_it2;
wire [0:0] exitcond7_fu_3609_p2;
reg [0:0] ap_reg_ppstg_exitcond7_reg_5678_pp4_it1;
reg [0:0] ap_reg_ppstg_exitcond7_reg_5678_pp4_it2;
reg [0:0] ap_reg_ppstg_exitcond7_reg_5678_pp4_it3;
reg [0:0] ap_reg_ppstg_exitcond7_reg_5678_pp4_it5;
reg [6:0] tmp_49_reg_5682;
wire [63:0] tmp_122_fu_3621_p1;
reg [63:0] tmp_122_reg_5687;
reg [63:0] ap_reg_ppstg_tmp_122_reg_5687_pp4_it1;
reg [63:0] ap_reg_ppstg_tmp_122_reg_5687_pp4_it2;
reg [63:0] ap_reg_ppstg_tmp_122_reg_5687_pp4_it3;
reg [63:0] ap_reg_ppstg_tmp_122_reg_5687_pp4_it4;
reg [63:0] ap_reg_ppstg_tmp_122_reg_5687_pp4_it5;
wire [0:0] exitcond9_fu_3626_p2;
reg [8:0] indvar_flatten_next2_reg_5701;
wire [6:0] j_3_mid2_fu_3644_p3;
reg [6:0] j_3_mid2_reg_5706;
wire [6:0] i_4_mid2_fu_3658_p3;
reg [6:0] i_4_mid2_reg_5719;
reg [5:0] i_4_cast_reg_5724;
wire [13:0] a_addr37_cast_fu_3684_p1;
reg [13:0] a_addr37_cast_reg_5729;
reg [13:0] ap_reg_ppstg_a_addr37_cast_reg_5729_pp5_it1;
wire [63:0] tmp_125_fu_3694_p1;
reg [63:0] tmp_125_reg_5740;
reg [63:0] ap_reg_ppstg_tmp_125_reg_5740_pp5_it1;
reg [3:0] indvar_next9_reg_5750;
wire [12:0] b_addr26_cast_fu_3731_p1;
reg [12:0] b_addr26_cast_reg_5755;
wire [63:0] tmp_130_fu_3764_p1;
reg [63:0] tmp_130_reg_5770;
reg [63:0] ap_reg_ppstg_tmp_130_reg_5770_pp5_it1;
wire [6:0] tmp_97_fu_3780_p2;
reg [6:0] tmp_97_reg_5785;
wire [63:0] tmp_138_fu_3794_p1;
reg [63:0] tmp_138_reg_5790;
reg [63:0] ap_reg_ppstg_tmp_138_reg_5790_pp5_it1;
wire [63:0] tmp_146_fu_3830_p1;
reg [63:0] tmp_146_reg_5805;
reg [63:0] ap_reg_ppstg_tmp_146_reg_5805_pp5_it1;
wire [6:0] tmp_105_fu_3845_p2;
reg [6:0] tmp_105_reg_5820;
wire [63:0] tmp_154_fu_3859_p1;
reg [63:0] tmp_154_reg_5825;
reg [63:0] ap_reg_ppstg_tmp_154_reg_5825_pp5_it1;
wire [63:0] tmp_160_fu_3895_p1;
reg [63:0] tmp_160_reg_5840;
reg [63:0] ap_reg_ppstg_tmp_160_reg_5840_pp5_it1;
reg [63:0] ap_reg_ppstg_tmp_160_reg_5840_pp5_it2;
wire [6:0] tmp_113_fu_3910_p2;
reg [6:0] tmp_113_reg_5855;
wire [6:0] tmp_117_fu_3929_p2;
reg [6:0] tmp_117_reg_5865;
reg [6:0] tmp_121_reg_5875;
wire [63:0] tmp_164_fu_3961_p1;
reg [63:0] tmp_164_reg_5880;
reg [63:0] ap_reg_ppstg_tmp_164_reg_5880_pp5_it2;
wire [13:0] a_addr50_fu_3969_p2;
reg [13:0] a_addr50_reg_5890;
wire [63:0] tmp_168_fu_3974_p1;
reg [63:0] tmp_168_reg_5895;
reg [63:0] ap_reg_ppstg_tmp_168_reg_5895_pp5_it2;
wire [0:0] exitcond10_fu_3978_p2;
reg [0:0] ap_reg_ppstg_exitcond10_reg_5905_pp6_it1;
reg [0:0] ap_reg_ppstg_exitcond10_reg_5905_pp6_it2;
reg [0:0] ap_reg_ppstg_exitcond10_reg_5905_pp6_it3;
reg [0:0] ap_reg_ppstg_exitcond10_reg_5905_pp6_it5;
reg [6:0] tmp_88_reg_5909;
wire [63:0] tmp_172_fu_4000_p1;
reg [63:0] tmp_172_reg_5914;
reg [63:0] ap_reg_ppstg_tmp_172_reg_5914_pp6_it1;
reg [63:0] ap_reg_ppstg_tmp_172_reg_5914_pp6_it2;
reg [63:0] ap_reg_ppstg_tmp_172_reg_5914_pp6_it3;
reg [63:0] ap_reg_ppstg_tmp_172_reg_5914_pp6_it4;
reg [63:0] ap_reg_ppstg_tmp_172_reg_5914_pp6_it5;
wire [0:0] exitcond12_fu_4005_p2;
reg [8:0] indvar_flatten_next3_reg_5928;
wire [6:0] j_5_mid2_fu_4023_p3;
reg [6:0] j_5_mid2_reg_5933;
wire [6:0] i_5_mid2_fu_4037_p3;
reg [6:0] i_5_mid2_reg_5946;
reg [5:0] i_5_cast_reg_5951;
wire [13:0] b_addr36_cast_fu_4063_p1;
reg [13:0] b_addr36_cast_reg_5956;
reg [13:0] ap_reg_ppstg_b_addr36_cast_reg_5956_pp7_it1;
wire [63:0] tmp_174_fu_4073_p1;
reg [63:0] tmp_174_reg_5967;
reg [63:0] ap_reg_ppstg_tmp_174_reg_5967_pp7_it1;
reg [3:0] indvar_next5_reg_5977;
wire [12:0] a_addr51_cast_fu_4110_p1;
reg [12:0] a_addr51_cast_reg_5982;
wire [63:0] tmp_178_fu_4143_p1;
reg [63:0] tmp_178_reg_5997;
reg [63:0] ap_reg_ppstg_tmp_178_reg_5997_pp7_it1;
wire [6:0] tmp_133_fu_4159_p2;
reg [6:0] tmp_133_reg_6012;
wire [63:0] tmp_182_fu_4173_p1;
reg [63:0] tmp_182_reg_6017;
reg [63:0] ap_reg_ppstg_tmp_182_reg_6017_pp7_it1;
wire [63:0] tmp_186_fu_4209_p1;
reg [63:0] tmp_186_reg_6032;
reg [63:0] ap_reg_ppstg_tmp_186_reg_6032_pp7_it1;
wire [6:0] tmp_141_fu_4224_p2;
reg [6:0] tmp_141_reg_6047;
wire [63:0] tmp_190_fu_4238_p1;
reg [63:0] tmp_190_reg_6052;
reg [63:0] ap_reg_ppstg_tmp_190_reg_6052_pp7_it1;
wire [63:0] tmp_192_fu_4274_p1;
reg [63:0] tmp_192_reg_6067;
reg [63:0] ap_reg_ppstg_tmp_192_reg_6067_pp7_it1;
reg [63:0] ap_reg_ppstg_tmp_192_reg_6067_pp7_it2;
wire [6:0] tmp_149_fu_4289_p2;
reg [6:0] tmp_149_reg_6082;
wire [6:0] tmp_153_fu_4308_p2;
reg [6:0] tmp_153_reg_6092;
reg [6:0] tmp_157_reg_6102;
wire [63:0] tmp_194_fu_4340_p1;
reg [63:0] tmp_194_reg_6107;
reg [63:0] ap_reg_ppstg_tmp_194_reg_6107_pp7_it2;
wire [13:0] b_addr44_fu_4348_p2;
reg [13:0] b_addr44_reg_6117;
wire [63:0] tmp_197_fu_4353_p1;
reg [63:0] tmp_197_reg_6122;
reg [63:0] ap_reg_ppstg_tmp_197_reg_6122_pp7_it2;
wire [0:0] exitcond_fu_4357_p2;
reg [0:0] exitcond_reg_6132;
reg ap_reg_ppiten_pp8_it0;
reg ap_reg_ppiten_pp8_it1;
reg [6:0] indvar_flatten_next4_reg_6136;
wire [6:0] j_6_mid2_fu_4375_p3;
reg [6:0] j_6_mid2_reg_6141;
wire [6:0] i_6_mid2_fu_4389_p3;
reg [6:0] i_6_mid2_reg_6153;
wire [13:0] a_addr63_cast_fu_4411_p1;
reg [13:0] a_addr63_cast_reg_6165;
wire [63:0] tmp_199_fu_4421_p1;
reg [63:0] tmp_199_reg_6176;
reg [3:0] indvar_next_reg_6186;
wire [13:0] tmp_176_trn_cast_fu_4445_p1;
reg [13:0] tmp_176_trn_cast_reg_6191;
wire [63:0] tmp_200_fu_4454_p1;
reg [63:0] tmp_200_reg_6202;
wire [13:0] tmp_178_trn_cast_fu_4464_p1;
reg [13:0] tmp_178_trn_cast_reg_6212;
wire [63:0] tmp_201_fu_4473_p1;
reg [63:0] tmp_201_reg_6223;
wire [13:0] tmp_180_trn_cast_fu_4483_p1;
reg [13:0] tmp_180_trn_cast_reg_6233;
wire [63:0] tmp_202_fu_4492_p1;
reg [63:0] tmp_202_reg_6244;
wire [13:0] tmp_182_trn_cast_fu_4502_p1;
reg [13:0] tmp_182_trn_cast_reg_6254;
wire [63:0] tmp_203_fu_4511_p1;
reg [63:0] tmp_203_reg_6265;
wire [13:0] tmp_184_trn_cast_fu_4521_p1;
reg [13:0] tmp_184_trn_cast_reg_6275;
wire [63:0] tmp_204_fu_4530_p1;
reg [63:0] tmp_204_reg_6286;
wire [13:0] tmp_186_trn_cast_fu_4540_p1;
reg [13:0] tmp_186_trn_cast_reg_6296;
wire [63:0] tmp_205_fu_4549_p1;
reg [63:0] tmp_205_reg_6307;
wire [13:0] tmp_188_trn_cast_fu_4564_p1;
reg [13:0] tmp_188_trn_cast_reg_6317;
wire [63:0] tmp_206_fu_4573_p1;
reg [63:0] tmp_206_reg_6328;
wire [13:0] a_addr77_cast_fu_4588_p1;
reg [13:0] a_addr77_cast_reg_6338;
wire [63:0] tmp_207_fu_4597_p1;
reg [63:0] tmp_207_reg_6348;
reg [6:0] tmp_189_reg_6358;
wire [63:0] tmp_208_fu_4611_p1;
reg [63:0] tmp_208_reg_6363;
wire [63:0] tmp_209_fu_4620_p1;
reg [63:0] tmp_209_reg_6373;
wire [63:0] tmp_210_fu_4629_p1;
reg [63:0] tmp_210_reg_6383;
wire [63:0] tmp_211_fu_4638_p1;
reg [63:0] tmp_211_reg_6393;
wire [63:0] tmp_212_fu_4647_p1;
reg [63:0] tmp_212_reg_6403;
wire [63:0] tmp_213_fu_4656_p1;
reg [63:0] tmp_213_reg_6413;
wire [13:0] a_addr87_cast_fu_4676_p1;
reg [13:0] a_addr87_cast_reg_6423;
wire [63:0] tmp_214_fu_4685_p1;
reg [63:0] tmp_214_reg_6432;
wire [63:0] tmp_215_fu_4695_p1;
reg [63:0] tmp_215_reg_6442;
wire [63:0] tmp_216_fu_4704_p1;
reg [63:0] tmp_216_reg_6452;
wire [63:0] tmp_217_fu_4713_p1;
reg [63:0] tmp_217_reg_6462;
wire [63:0] tmp_218_fu_4722_p1;
reg [63:0] tmp_218_reg_6472;
wire [63:0] tmp_219_fu_4731_p1;
reg [63:0] tmp_219_reg_6482;
wire [63:0] tmp_220_fu_4745_p1;
reg [63:0] tmp_220_reg_6492;
wire [13:0] a_addr98_cast_fu_4760_p1;
reg [13:0] a_addr98_cast_reg_6502;
wire [63:0] tmp_221_fu_4769_p1;
reg [63:0] tmp_221_reg_6512;
wire [63:0] tmp_222_fu_4778_p1;
reg [63:0] tmp_222_reg_6522;
wire [63:0] tmp_223_fu_4787_p1;
reg [63:0] tmp_223_reg_6532;
wire [63:0] tmp_224_fu_4796_p1;
reg [63:0] tmp_224_reg_6542;
wire [63:0] tmp_225_fu_4805_p1;
reg [63:0] tmp_225_reg_6552;
wire [63:0] tmp_226_fu_4814_p1;
reg [63:0] tmp_226_reg_6562;
wire [63:0] tmp_227_fu_4823_p1;
reg [63:0] tmp_227_reg_6572;
wire [13:0] a_addr99_cast_fu_4843_p1;
reg [13:0] a_addr99_cast_reg_6582;
wire [63:0] tmp_228_fu_4852_p1;
reg [63:0] tmp_228_reg_6591;
wire [63:0] tmp_229_fu_4862_p1;
reg [63:0] tmp_229_reg_6601;
wire [63:0] tmp_230_fu_4871_p1;
reg [63:0] tmp_230_reg_6611;
wire [63:0] tmp_231_fu_4880_p1;
reg [63:0] tmp_231_reg_6621;
wire [63:0] tmp_232_fu_4889_p1;
reg [63:0] tmp_232_reg_6631;
wire [63:0] tmp_233_fu_4898_p1;
reg [63:0] tmp_233_reg_6641;
wire [63:0] tmp_234_fu_4912_p1;
reg [63:0] tmp_234_reg_6651;
wire [13:0] a_addr72_cast_fu_4927_p1;
reg [13:0] a_addr72_cast_reg_6661;
wire [63:0] tmp_235_fu_4936_p1;
reg [63:0] tmp_235_reg_6671;
wire [63:0] tmp_236_fu_4945_p1;
reg [63:0] tmp_236_reg_6681;
wire [63:0] tmp_237_fu_4954_p1;
reg [63:0] tmp_237_reg_6691;
wire [63:0] tmp_238_fu_4963_p1;
reg [63:0] tmp_238_reg_6701;
wire [63:0] tmp_239_fu_4972_p1;
reg [63:0] tmp_239_reg_6711;
wire [63:0] tmp_240_fu_4981_p1;
reg [63:0] tmp_240_reg_6721;
wire [63:0] tmp_241_fu_4990_p1;
reg [63:0] tmp_241_reg_6731;
wire [13:0] a_addr45_cast_fu_5010_p1;
reg [13:0] a_addr45_cast_reg_6741;
wire [63:0] tmp_242_fu_5019_p1;
reg [63:0] tmp_242_reg_6750;
wire [63:0] tmp_243_fu_5029_p1;
reg [63:0] tmp_243_reg_6760;
wire [63:0] tmp_244_fu_5038_p1;
reg [63:0] tmp_244_reg_6770;
wire [63:0] tmp_245_fu_5047_p1;
reg [63:0] tmp_245_reg_6780;
wire [63:0] tmp_246_fu_5061_p1;
reg [63:0] tmp_246_reg_6790;
wire [63:0] tmp_247_fu_5070_p1;
reg [63:0] tmp_247_reg_6800;
wire [13:0] a_addr22_fu_5075_p2;
reg [13:0] a_addr22_reg_6810;
wire [13:0] a_addr19_fu_5093_p2;
reg [13:0] a_addr19_reg_6815;
reg [13:0] a_addr16_reg_6820;
wire [13:0] a_addr13_fu_5103_p2;
reg [13:0] a_addr13_reg_6825;
reg [13:0] a_addr10_reg_6830;
wire [13:0] a_addr7_fu_5113_p2;
reg [13:0] a_addr7_reg_6835;
reg [13:0] a_addr4_reg_6840;
wire [13:0] a_addr1_fu_5123_p2;
reg [13:0] a_addr1_reg_6845;
wire [63:0] tmp_248_fu_5128_p1;
reg [63:0] tmp_248_reg_6850;
wire [63:0] tmp_249_fu_5132_p1;
reg [63:0] tmp_249_reg_6860;
wire [63:0] tmp_250_fu_5136_p1;
reg [63:0] tmp_250_reg_6870;
wire [63:0] tmp_251_fu_5140_p1;
reg [63:0] tmp_251_reg_6880;
wire [63:0] tmp_252_fu_5144_p1;
reg [63:0] tmp_252_reg_6890;
wire [63:0] tmp_253_fu_5148_p1;
reg [63:0] tmp_253_reg_6900;
wire [63:0] tmp_254_fu_5152_p1;
reg [63:0] tmp_254_reg_6910;
wire [63:0] tmp_255_fu_5156_p1;
reg [63:0] tmp_255_reg_6920;
reg [6:0] i_phi_fu_1890_p4;
reg [8:0] indvar_flatten_phi_fu_1901_p4;
reg [6:0] j_phi_fu_1912_p4;
reg [3:0] indvar3_phi_fu_1923_p4;
reg [6:0] i_1_phi_fu_1934_p4;
reg [6:0] i_2_phi_fu_1945_p4;
reg [8:0] indvar_flatten1_phi_fu_1956_p4;
reg [6:0] j_1_phi_fu_1967_p4;
reg [3:0] indvar6_phi_fu_1978_p4;
reg [6:0] i_3_phi_fu_1989_p4;
reg [6:0] j_2_phi_fu_2000_p4;
reg [8:0] indvar_flatten2_phi_fu_2011_p4;
reg [6:0] i_4_phi_fu_2022_p4;
reg [3:0] indvar9_phi_fu_2033_p4;
reg [6:0] j_3_phi_fu_2044_p4;
reg [6:0] j_4_phi_fu_2055_p4;
reg [8:0] indvar_flatten3_phi_fu_2066_p4;
reg [6:0] i_5_phi_fu_2077_p4;
reg [3:0] indvar4_phi_fu_2088_p4;
reg [6:0] j_5_phi_fu_2099_p4;
reg [6:0] indvar_flatten4_phi_fu_2110_p6;
reg [6:0] i_6_phi_fu_2124_p6;
reg [3:0] indvar_phi_fu_2138_p6;
reg [6:0] j_6_phi_fu_2152_p6;
wire [63:0] tmp_11_fu_2531_p1;
wire [63:0] tmp_16_fu_2597_p1;
wire [63:0] tmp_24_fu_2711_p1;
wire [63:0] tmp_32_fu_2765_p1;
wire [63:0] tmp_40_fu_2818_p1;
wire [63:0] tmp_46_fu_2872_p1;
wire [63:0] tmp_50_fu_2921_p1;
wire [63:0] tmp_55_fu_2970_p1;
wire [63:0] tmp_71_fu_3152_p1;
wire [63:0] tmp_79_fu_3218_p1;
wire [63:0] tmp_85_fu_3332_p1;
wire [63:0] tmp_89_fu_3386_p1;
wire [63:0] tmp_94_fu_3439_p1;
wire [63:0] tmp_102_fu_3493_p1;
wire [63:0] tmp_110_fu_3542_p1;
wire [63:0] tmp_118_fu_3591_p1;
wire [63:0] tmp_126_fu_3741_p1;
wire [63:0] tmp_134_fu_3775_p1;
wire [63:0] tmp_142_fu_3807_p1;
wire [63:0] tmp_150_fu_3840_p1;
wire [63:0] tmp_158_fu_3872_p1;
wire [63:0] tmp_162_fu_3905_p1;
wire [63:0] tmp_166_fu_3924_p1;
wire [63:0] tmp_170_fu_3943_p1;
wire [63:0] tmp_176_fu_4120_p1;
wire [63:0] tmp_180_fu_4154_p1;
wire [63:0] tmp_184_fu_4186_p1;
wire [63:0] tmp_188_fu_4219_p1;
wire [63:0] tmp_191_fu_4251_p1;
wire [63:0] tmp_193_fu_4284_p1;
wire [63:0] tmp_196_fu_4303_p1;
wire [63:0] tmp_198_fu_4322_p1;
reg [31:0] grp_fu_2163_p0;
reg [31:0] grp_fu_2163_p1;
reg [31:0] grp_fu_2167_p0;
reg [31:0] grp_fu_2167_p1;
wire [0:0] tmp_fu_2353_p2;
wire [0:0] tmp_1_fu_2359_p2;
wire [12:0] tmp_3_trn_cast_fu_2389_p1;
wire [12:0] a_addr_fu_2393_p2;
wire [0:0] exitcond5_fu_2416_p2;
wire [6:0] tmp_11_dup_fu_2430_p2;
wire [12:0] tmp_12_trn_cast_fu_2448_p1;
wire [12:0] a_addr2_fu_2456_p2;
wire [13:0] a_addr2_cast_fu_2462_p1;
wire [13:0] a_addr3_fu_2466_p2;
wire [3:0] indvar3_op_fu_2481_p2;
wire [5:0] tmp_7_fu_2495_p2;
wire [6:0] tmp_8_trn_cast1_fu_2504_p4;
wire [6:0] b_addr_fu_2514_p2;
wire [12:0] b_addr1_fu_2519_p5;
wire [6:0] tmp_14_fu_2536_p2;
wire [12:0] tmp_16_trn_cast_fu_2541_p1;
wire [12:0] a_addr5_fu_2545_p2;
wire [13:0] a_addr5_cast_fu_2551_p1;
wire [13:0] a_addr6_fu_2555_p2;
wire [6:0] a_addr101_fu_2565_p1;
wire [6:0] tmp_8_trn_cast2_fu_2569_p4;
wire [6:0] b_addr2_fu_2579_p2;
wire [12:0] b_addr3_fu_2585_p5;
wire [6:0] tmp_19_fu_2602_p2;
wire [12:0] tmp_20_trn_cast_fu_2607_p1;
wire [12:0] a_addr8_fu_2611_p2;
wire [13:0] a_addr8_cast_fu_2617_p1;
wire [13:0] a_addr9_fu_2621_p2;
wire [6:0] a_addr102_fu_2631_p1;
wire [6:0] tmp_8_trn_cast3_fu_2635_p4;
wire [12:0] b_addr5_fu_2701_p5;
wire [6:0] tmp_23_fu_2716_p2;
wire [12:0] tmp_24_trn_cast_fu_2721_p1;
wire [12:0] a_addr11_fu_2725_p2;
wire [13:0] a_addr11_cast_fu_2731_p1;
wire [13:0] a_addr12_fu_2735_p2;
wire [6:0] a_addr103_fu_2745_p1;
wire [6:0] b_addr6_fu_2749_p2;
wire [12:0] b_addr7_fu_2754_p5;
wire [6:0] tmp_27_fu_2770_p2;
wire [12:0] tmp_28_trn_cast_fu_2775_p1;
wire [12:0] a_addr14_fu_2779_p2;
wire [13:0] a_addr14_cast_fu_2785_p1;
wire [13:0] a_addr15_fu_2789_p2;
wire [6:0] a_addr104_fu_2799_p1;
wire [12:0] b_addr9_fu_2808_p5;
wire [6:0] tmp_31_fu_2823_p2;
wire [12:0] tmp_32_trn_cast_fu_2828_p1;
wire [12:0] a_addr17_fu_2832_p2;
wire [13:0] a_addr17_cast_fu_2838_p1;
wire [13:0] a_addr20_fu_2842_p2;
wire [6:0] a_addr105_fu_2852_p1;
wire [6:0] b_addr45_fu_2856_p2;
wire [12:0] b_addr46_fu_2861_p5;
wire [6:0] tmp_35_fu_2877_p2;
wire [12:0] tmp_36_trn_cast_fu_2882_p1;
wire [12:0] a_addr21_fu_2886_p2;
wire [13:0] a_addr21_cast_fu_2892_p1;
wire [6:0] a_addr106_fu_2901_p1;
wire [6:0] b_addr47_fu_2905_p2;
wire [12:0] b_addr48_fu_2910_p5;
wire [6:0] tmp_39_fu_2926_p2;
wire [12:0] tmp_40_trn_cast_fu_2931_p1;
wire [12:0] a_addr24_fu_2935_p2;
wire [13:0] a_addr24_cast_fu_2941_p1;
wire [6:0] a_addr107_fu_2950_p1;
wire [6:0] b_addr49_fu_2954_p2;
wire [12:0] b_addr50_fu_2959_p5;
wire [12:0] tmp_9_trn_cast_fu_3000_p1;
wire [6:0] b_addr51_fu_3004_p1;
wire [12:0] b_addr52_fu_3008_p5;
wire [0:0] exitcond8_fu_3037_p2;
wire [6:0] tmp_50_dup_fu_3051_p2;
wire [12:0] tmp_51_trn_cast_fu_3069_p1;
wire [12:0] b_addr10_fu_3077_p2;
wire [13:0] b_addr10_cast_fu_3083_p1;
wire [13:0] b_addr11_fu_3087_p1;
wire [13:0] b_addr11_fu_3087_p2;
wire [3:0] indvar6_op_fu_3102_p2;
wire [5:0] tmp_45_fu_3116_p2;
wire [6:0] tmp_46_trn_cast1_fu_3125_p4;
wire [6:0] a_addr108_fu_3135_p2;
wire [12:0] a_addr109_fu_3140_p5;
wire [6:0] tmp_54_fu_3157_p2;
wire [12:0] tmp_55_trn_cast_fu_3162_p1;
wire [12:0] b_addr12_fu_3166_p2;
wire [13:0] b_addr12_cast_fu_3172_p1;
wire [13:0] b_addr13_fu_3176_p2;
wire [6:0] b_addr54_fu_3186_p1;
wire [6:0] tmp_46_trn_cast2_fu_3190_p4;
wire [6:0] a_addr110_fu_3200_p2;
wire [12:0] a_addr111_fu_3206_p5;
wire [6:0] tmp_58_fu_3223_p2;
wire [12:0] tmp_59_trn_cast_fu_3228_p1;
wire [12:0] b_addr14_fu_3232_p2;
wire [13:0] b_addr14_cast_fu_3238_p1;
wire [13:0] b_addr15_fu_3242_p2;
wire [6:0] b_addr55_fu_3252_p1;
wire [6:0] tmp_46_trn_cast3_fu_3256_p4;
wire [12:0] a_addr113_fu_3322_p5;
wire [6:0] tmp_62_fu_3337_p2;
wire [12:0] tmp_63_trn_cast_fu_3342_p1;
wire [12:0] b_addr16_fu_3346_p2;
wire [13:0] b_addr16_cast_fu_3352_p1;
wire [13:0] b_addr17_fu_3356_p2;
wire [6:0] b_addr56_fu_3366_p1;
wire [6:0] a_addr114_fu_3370_p2;
wire [12:0] a_addr115_fu_3375_p5;
wire [6:0] tmp_66_fu_3391_p2;
wire [12:0] tmp_67_trn_cast_fu_3396_p1;
wire [12:0] b_addr18_fu_3400_p2;
wire [13:0] b_addr18_cast_fu_3406_p1;
wire [13:0] b_addr19_fu_3410_p2;
wire [6:0] b_addr57_fu_3420_p1;
wire [12:0] a_addr117_fu_3429_p5;
wire [6:0] tmp_70_fu_3444_p2;
wire [12:0] tmp_71_trn_cast_fu_3449_p1;
wire [12:0] b_addr20_fu_3453_p2;
wire [13:0] b_addr20_cast_fu_3459_p1;
wire [13:0] b_addr21_fu_3463_p2;
wire [6:0] b_addr58_fu_3473_p1;
wire [6:0] a_addr118_fu_3477_p2;
wire [12:0] a_addr119_fu_3482_p5;
wire [6:0] tmp_74_fu_3498_p2;
wire [12:0] tmp_75_trn_cast_fu_3503_p1;
wire [12:0] b_addr22_fu_3507_p2;
wire [13:0] b_addr22_cast_fu_3513_p1;
wire [6:0] b_addr59_fu_3522_p1;
wire [6:0] a_addr120_fu_3526_p2;
wire [12:0] a_addr121_fu_3531_p5;
wire [6:0] tmp_78_fu_3547_p2;
wire [12:0] tmp_79_trn_cast_fu_3552_p1;
wire [12:0] b_addr24_fu_3556_p2;
wire [13:0] b_addr24_cast_fu_3562_p1;
wire [6:0] b_addr60_fu_3571_p1;
wire [6:0] a_addr122_fu_3575_p2;
wire [12:0] a_addr123_fu_3580_p5;
wire [0:0] exitcond11_fu_3638_p2;
wire [6:0] tmp_89_dup_fu_3652_p2;
wire [12:0] tmp_83_trn_cast_fu_3670_p1;
wire [12:0] a_addr37_fu_3678_p2;
wire [13:0] tmp_90_trn_cast_fu_3674_p1;
wire [13:0] a_addr39_fu_3688_p2;
wire [3:0] indvar9_op_fu_3699_p2;
wire [5:0] tmp_84_fu_3713_p2;
wire [11:0] tmp_85_trn_cast_fu_3721_p1;
wire [11:0] b_addr26_fu_3725_p2;
wire [12:0] tmp_90_trn_cast1_fu_3718_p1;
wire [12:0] b_addr27_fu_3735_p2;
wire [6:0] tmp_93_fu_3746_p2;
wire [13:0] tmp_94_trn_cast_fu_3755_p1;
wire [13:0] a_addr40_fu_3759_p2;
wire [12:0] tmp_94_trn_cast1_fu_3751_p1;
wire [12:0] b_addr28_fu_3769_p2;
wire [13:0] tmp_98_trn_cast_fu_3785_p1;
wire [13:0] a_addr41_fu_3789_p2;
wire [12:0] tmp_98_trn_cast1_fu_3799_p1;
wire [12:0] b_addr29_fu_3802_p2;
wire [6:0] tmp_101_fu_3812_p2;
wire [13:0] tmp_102_trn_cast_fu_3821_p1;
wire [13:0] a_addr43_fu_3825_p2;
wire [12:0] tmp_102_trn_cast1_fu_3817_p1;
wire [12:0] b_addr30_fu_3835_p2;
wire [13:0] tmp_106_trn_cast_fu_3850_p1;
wire [13:0] a_addr44_fu_3854_p2;
wire [12:0] tmp_106_trn_cast1_fu_3864_p1;
wire [12:0] b_addr31_fu_3867_p2;
wire [6:0] tmp_109_fu_3877_p2;
wire [13:0] tmp_110_trn_cast_fu_3886_p1;
wire [13:0] a_addr47_fu_3890_p2;
wire [12:0] tmp_110_trn_cast1_fu_3882_p1;
wire [12:0] b_addr32_fu_3900_p2;
wire [12:0] tmp_114_trn_cast1_fu_3915_p1;
wire [12:0] b_addr33_fu_3919_p2;
wire [12:0] tmp_118_trn_cast1_fu_3934_p1;
wire [12:0] b_addr34_fu_3938_p2;
wire [13:0] tmp_114_trn_cast_fu_3953_p1;
wire [13:0] a_addr48_fu_3956_p2;
wire [13:0] tmp_118_trn_cast_fu_3966_p1;
wire [12:0] tmp_86_trn_cast_fu_3990_p1;
wire [12:0] b_addr35_fu_3994_p2;
wire [0:0] exitcond13_fu_4017_p2;
wire [6:0] tmp_125_dup_fu_4031_p2;
wire [12:0] tmp_122_trn_cast_fu_4049_p1;
wire [12:0] b_addr36_fu_4057_p2;
wire [13:0] b_addr37_fu_4067_p0;
wire [13:0] tmp_126_trn_cast_fu_4053_p1;
wire [13:0] b_addr37_fu_4067_p2;
wire [3:0] indvar4_op_fu_4078_p2;
wire [5:0] tmp_123_fu_4092_p2;
wire [11:0] tmp_124_trn_cast_fu_4100_p1;
wire [11:0] a_addr51_fu_4104_p2;
wire [12:0] tmp_126_trn_cast1_fu_4097_p1;
wire [12:0] a_addr52_fu_4114_p2;
wire [6:0] tmp_129_fu_4125_p2;
wire [13:0] tmp_130_trn_cast_fu_4134_p1;
wire [13:0] b_addr38_fu_4138_p2;
wire [12:0] tmp_130_trn_cast1_fu_4130_p1;
wire [12:0] a_addr54_fu_4148_p2;
wire [13:0] tmp_134_trn_cast_fu_4164_p1;
wire [13:0] b_addr39_fu_4168_p2;
wire [12:0] tmp_134_trn_cast1_fu_4178_p1;
wire [12:0] a_addr55_fu_4181_p2;
wire [6:0] tmp_137_fu_4191_p2;
wire [13:0] tmp_138_trn_cast_fu_4200_p1;
wire [13:0] b_addr40_fu_4204_p2;
wire [12:0] tmp_138_trn_cast1_fu_4196_p1;
wire [12:0] a_addr56_fu_4214_p2;
wire [13:0] tmp_142_trn_cast_fu_4229_p1;
wire [13:0] b_addr41_fu_4233_p2;
wire [12:0] tmp_142_trn_cast1_fu_4243_p1;
wire [12:0] a_addr58_fu_4246_p2;
wire [6:0] tmp_145_fu_4256_p2;
wire [13:0] tmp_146_trn_cast_fu_4265_p1;
wire [13:0] b_addr42_fu_4269_p2;
wire [12:0] tmp_146_trn_cast1_fu_4261_p1;
wire [12:0] a_addr59_fu_4279_p2;
wire [12:0] tmp_150_trn_cast1_fu_4294_p1;
wire [12:0] a_addr60_fu_4298_p2;
wire [12:0] tmp_154_trn_cast1_fu_4313_p1;
wire [12:0] a_addr62_fu_4317_p2;
wire [13:0] tmp_150_trn_cast_fu_4332_p1;
wire [13:0] b_addr43_fu_4335_p2;
wire [13:0] tmp_154_trn_cast_fu_4345_p1;
wire [0:0] exitcond2_fu_4369_p2;
wire [6:0] tmp_173_dup_fu_4383_p2;
wire [12:0] tmp_158_trn_cast_fu_4397_p1;
wire [12:0] a_addr27_fu_4405_p2;
wire [13:0] tmp_174_trn_cast_fu_4401_p1;
wire [13:0] a_addr28_fu_4415_p2;
wire [3:0] indvar_op_fu_4426_p2;
wire [6:0] tmp_175_fu_4440_p2;
wire [13:0] a_addr29_fu_4449_p2;
wire [6:0] tmp_177_fu_4459_p2;
wire [13:0] a_addr31_fu_4468_p2;
wire [6:0] tmp_179_fu_4478_p2;
wire [13:0] a_addr32_fu_4487_p2;
wire [6:0] tmp_181_fu_4497_p2;
wire [13:0] a_addr33_fu_4506_p2;
wire [6:0] tmp_183_fu_4516_p2;
wire [13:0] a_addr35_fu_4525_p2;
wire [6:0] tmp_185_fu_4535_p2;
wire [13:0] a_addr36_fu_4544_p2;
wire [6:0] tmp_187_fu_4559_p2;
wire [13:0] a_addr63_fu_4568_p2;
wire [6:0] tmp_159_fu_4554_p2;
wire [12:0] tmp_160_trn_cast_fu_4578_p1;
wire [12:0] a_addr64_fu_4582_p2;
wire [13:0] a_addr66_fu_4592_p2;
wire [13:0] a_addr67_fu_4607_p2;
wire [13:0] a_addr68_fu_4616_p2;
wire [13:0] a_addr70_fu_4625_p2;
wire [13:0] a_addr71_fu_4634_p2;
wire [13:0] a_addr74_fu_4643_p2;
wire [13:0] a_addr75_fu_4652_p2;
wire [6:0] tmp_161_fu_4661_p2;
wire [12:0] tmp_162_trn_cast_fu_4666_p1;
wire [12:0] a_addr77_fu_4670_p2;
wire [13:0] a_addr78_fu_4680_p2;
wire [13:0] a_addr79_fu_4690_p2;
wire [13:0] a_addr81_fu_4700_p2;
wire [13:0] a_addr82_fu_4709_p2;
wire [13:0] a_addr83_fu_4718_p2;
wire [13:0] a_addr85_fu_4727_p2;
wire [13:0] a_addr86_fu_4741_p2;
wire [6:0] tmp_163_fu_4736_p2;
wire [12:0] tmp_164_trn_cast_fu_4750_p1;
wire [12:0] a_addr87_fu_4754_p2;
wire [13:0] a_addr89_fu_4764_p2;
wire [13:0] a_addr90_fu_4774_p2;
wire [13:0] a_addr91_fu_4783_p2;
wire [13:0] a_addr93_fu_4792_p2;
wire [13:0] a_addr94_fu_4801_p2;
wire [13:0] a_addr95_fu_4810_p2;
wire [13:0] a_addr97_fu_4819_p2;
wire [6:0] tmp_165_fu_4828_p2;
wire [12:0] tmp_166_trn_cast_fu_4833_p1;
wire [12:0] a_addr98_fu_4837_p2;
wire [13:0] a_addr99_fu_4847_p2;
wire [13:0] a_addr96_fu_4857_p2;
wire [13:0] a_addr92_fu_4867_p2;
wire [13:0] a_addr88_fu_4876_p2;
wire [13:0] a_addr84_fu_4885_p2;
wire [13:0] a_addr80_fu_4894_p2;
wire [13:0] a_addr76_fu_4908_p2;
wire [6:0] tmp_167_fu_4903_p2;
wire [12:0] tmp_168_trn_cast_fu_4917_p1;
wire [12:0] a_addr72_fu_4921_p2;
wire [13:0] a_addr73_fu_4931_p2;
wire [13:0] a_addr69_fu_4941_p2;
wire [13:0] a_addr65_fu_4950_p2;
wire [13:0] a_addr61_fu_4959_p2;
wire [13:0] a_addr57_fu_4968_p2;
wire [13:0] a_addr53_fu_4977_p2;
wire [13:0] a_addr49_fu_4986_p2;
wire [6:0] tmp_169_fu_4995_p2;
wire [12:0] tmp_170_trn_cast_fu_5000_p1;
wire [12:0] a_addr45_fu_5004_p2;
wire [13:0] a_addr46_fu_5014_p2;
wire [13:0] a_addr42_fu_5024_p2;
wire [13:0] a_addr38_fu_5034_p2;
wire [13:0] a_addr34_fu_5043_p2;
wire [13:0] a_addr30_fu_5057_p2;
wire [13:0] a_addr26_fu_5066_p2;
wire [6:0] tmp_171_fu_5052_p2;
wire [12:0] tmp_172_trn_cast_fu_5079_p1;
wire [12:0] a_addr18_fu_5083_p2;
wire [13:0] a_addr18_cast_fu_5089_p1;
wire grp_fu_2163_ce;
wire grp_fu_2167_ce;
reg [6:0] ap_NS_fsm;
parameter ap_const_logic_1 = 1'b1;
parameter ap_const_logic_0 = 1'b0;
parameter ap_ST_st0_fsm_0 = 7'b0000000;
parameter ap_ST_st1_fsm_1 = 7'b0000001;
parameter ap_ST_pp0_stg0_fsm_2 = 7'b0000010;
parameter ap_ST_st9_fsm_3 = 7'b0000011;
parameter ap_ST_pp1_stg0_fsm_4 = 7'b0000100;
parameter ap_ST_pp1_stg1_fsm_5 = 7'b0000101;
parameter ap_ST_pp1_stg2_fsm_6 = 7'b0000110;
parameter ap_ST_pp1_stg3_fsm_7 = 7'b0000111;
parameter ap_ST_pp1_stg4_fsm_8 = 7'b0001000;
parameter ap_ST_pp1_stg5_fsm_9 = 7'b0001001;
parameter ap_ST_pp1_stg6_fsm_10 = 7'b0001010;
parameter ap_ST_pp1_stg7_fsm_11 = 7'b0001011;
parameter ap_ST_pp2_stg0_fsm_12 = 7'b0001100;
parameter ap_ST_pp3_stg0_fsm_13 = 7'b0001101;
parameter ap_ST_pp3_stg1_fsm_14 = 7'b0001110;
parameter ap_ST_pp3_stg2_fsm_15 = 7'b0001111;
parameter ap_ST_pp3_stg3_fsm_16 = 7'b0010000;
parameter ap_ST_pp3_stg4_fsm_17 = 7'b0010001;
parameter ap_ST_pp3_stg5_fsm_18 = 7'b0010010;
parameter ap_ST_pp3_stg6_fsm_19 = 7'b0010011;
parameter ap_ST_pp3_stg7_fsm_20 = 7'b0010100;
parameter ap_ST_pp4_stg0_fsm_21 = 7'b0010101;
parameter ap_ST_pp5_stg0_fsm_22 = 7'b0010110;
parameter ap_ST_pp5_stg1_fsm_23 = 7'b0010111;
parameter ap_ST_pp5_stg2_fsm_24 = 7'b0011000;
parameter ap_ST_pp5_stg3_fsm_25 = 7'b0011001;
parameter ap_ST_pp5_stg4_fsm_26 = 7'b0011010;
parameter ap_ST_pp5_stg5_fsm_27 = 7'b0011011;
parameter ap_ST_pp5_stg6_fsm_28 = 7'b0011100;
parameter ap_ST_pp5_stg7_fsm_29 = 7'b0011101;
parameter ap_ST_pp6_stg0_fsm_30 = 7'b0011110;
parameter ap_ST_pp7_stg0_fsm_31 = 7'b0011111;
parameter ap_ST_pp7_stg1_fsm_32 = 7'b0100000;
parameter ap_ST_pp7_stg2_fsm_33 = 7'b0100001;
parameter ap_ST_pp7_stg3_fsm_34 = 7'b0100010;
parameter ap_ST_pp7_stg4_fsm_35 = 7'b0100011;
parameter ap_ST_pp7_stg5_fsm_36 = 7'b0100100;
parameter ap_ST_pp7_stg6_fsm_37 = 7'b0100101;
parameter ap_ST_pp7_stg7_fsm_38 = 7'b0100110;
parameter ap_ST_st131_fsm_39 = 7'b0100111;
parameter ap_ST_pp8_stg0_fsm_40 = 7'b0101000;
parameter ap_ST_pp8_stg1_fsm_41 = 7'b0101001;
parameter ap_ST_pp8_stg2_fsm_42 = 7'b0101010;
parameter ap_ST_pp8_stg3_fsm_43 = 7'b0101011;
parameter ap_ST_pp8_stg4_fsm_44 = 7'b0101100;
parameter ap_ST_pp8_stg5_fsm_45 = 7'b0101101;
parameter ap_ST_pp8_stg6_fsm_46 = 7'b0101110;
parameter ap_ST_pp8_stg7_fsm_47 = 7'b0101111;
parameter ap_ST_pp8_stg8_fsm_48 = 7'b0110000;
parameter ap_ST_pp8_stg9_fsm_49 = 7'b0110001;
parameter ap_ST_pp8_stg10_fsm_50 = 7'b0110010;
parameter ap_ST_pp8_stg11_fsm_51 = 7'b0110011;
parameter ap_ST_pp8_stg12_fsm_52 = 7'b0110100;
parameter ap_ST_pp8_stg13_fsm_53 = 7'b0110101;
parameter ap_ST_pp8_stg14_fsm_54 = 7'b0110110;
parameter ap_ST_pp8_stg15_fsm_55 = 7'b0110111;
parameter ap_ST_pp8_stg16_fsm_56 = 7'b0111000;
parameter ap_ST_pp8_stg17_fsm_57 = 7'b0111001;
parameter ap_ST_pp8_stg18_fsm_58 = 7'b0111010;
parameter ap_ST_pp8_stg19_fsm_59 = 7'b0111011;
parameter ap_ST_pp8_stg20_fsm_60 = 7'b0111100;
parameter ap_ST_pp8_stg21_fsm_61 = 7'b0111101;
parameter ap_ST_pp8_stg22_fsm_62 = 7'b0111110;
parameter ap_ST_pp8_stg23_fsm_63 = 7'b0111111;
parameter ap_ST_pp8_stg24_fsm_64 = 7'b1000000;
parameter ap_ST_pp8_stg25_fsm_65 = 7'b1000001;
parameter ap_ST_pp8_stg26_fsm_66 = 7'b1000010;
parameter ap_ST_pp8_stg27_fsm_67 = 7'b1000011;
parameter ap_ST_pp8_stg28_fsm_68 = 7'b1000100;
parameter ap_ST_st162_fsm_69 = 7'b1000101;
parameter ap_const_lv1_0 = 1'b0;
parameter ap_const_lv7_0 = 7'b0000000;
parameter ap_const_lv9_0 = 9'b000000000;
parameter ap_const_lv7_1 = 7'b0000001;
parameter ap_const_lv4_0 = 4'b0000;
parameter ap_const_lv7_3E = 7'b0111110;
parameter ap_const_lv7_41 = 7'b1000001;
parameter ap_const_lv2_0 = 2'b00;
parameter ap_const_lv7_40 = 7'b1000000;
parameter ap_const_lv13_6 = 13'b0000000000110;
parameter ap_const_lv9_1F8 = 9'b111111000;
parameter ap_const_lv9_1 = 9'b000000001;
parameter ap_const_lv4_8 = 4'b1000;
parameter ap_const_lv4_1 = 4'b0001;
parameter ap_const_lv6_3F = 6'b111111;
parameter ap_const_lv32_6 = 32'b00000000000000000000000000000110;
parameter ap_const_lv32_C = 32'b00000000000000000000000000001100;
parameter ap_const_lv7_2 = 7'b0000010;
parameter ap_const_lv7_3 = 7'b0000011;
parameter ap_const_lv7_4 = 7'b0000100;
parameter ap_const_lv7_5 = 7'b0000101;
parameter ap_const_lv7_6 = 7'b0000110;
parameter ap_const_lv7_7 = 7'b0000111;
parameter ap_const_lv7_8 = 7'b0001000;
parameter ap_const_lv13_3F = 13'b0000000111111;
parameter ap_const_lv7_7F = 7'b1111111;
parameter ap_const_lv6_1 = 6'b000001;
parameter ap_const_lv12_6 = 12'b000000000110;
parameter ap_const_lv13_FC0 = 13'b0111111000000;
parameter ap_true = 1'b1;
step0_grp_fu_2163_ACMP_fadd_5 #(
.ID( 5 ),
.NUM_STAGE( 5 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
step0_grp_fu_2163_ACMP_fadd_5_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_2163_p0 ),
.din1( grp_fu_2163_p1 ),
.ce( grp_fu_2163_ce ),
.dout( grp_fu_2163_p2 )
);
step0_grp_fu_2167_ACMP_fmul_6 #(
.ID( 6 ),
.NUM_STAGE( 4 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
step0_grp_fu_2167_ACMP_fmul_6_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_2167_p0 ),
.din1( grp_fu_2167_p1 ),
.ce( grp_fu_2167_ce ),
.dout( grp_fu_2167_p2 )
);
/// ap_CS_fsm assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_CS_fsm
if (ap_rst == 1'b1) begin
ap_CS_fsm <= ap_ST_st0_fsm_0;
end else begin
ap_CS_fsm <= ap_NS_fsm;
end
end
/// ap_reg_ppiten_pp0_it0 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it0
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it0 <= ap_const_logic_0;
end else begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond1_fu_2377_p2))) begin
ap_reg_ppiten_pp0_it0 <= ap_const_logic_0;
end else if (((ap_ST_st1_fsm_1 == ap_CS_fsm) & ~(ap_const_lv1_0 == or_cond_fu_2365_p2) & ~(ap_const_lv1_0 == tmp_2_fu_2371_p2))) begin
ap_reg_ppiten_pp0_it0 <= ap_const_logic_1;
end
end
end
/// ap_reg_ppiten_pp0_it1 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it1
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it1 <= ap_const_logic_0;
end else begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond1_fu_2377_p2))) begin
ap_reg_ppiten_pp0_it1 <= ap_const_logic_1;
end else if ((((ap_ST_st1_fsm_1 == ap_CS_fsm) & ~(ap_const_lv1_0 == or_cond_fu_2365_p2) & ~(ap_const_lv1_0 == tmp_2_fu_2371_p2)) | ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond1_fu_2377_p2)))) begin
ap_reg_ppiten_pp0_it1 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp0_it2 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it2
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it2 <= ap_const_logic_0;
end else begin
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it2 <= ap_reg_ppiten_pp0_it1;
end else if (((ap_ST_st1_fsm_1 == ap_CS_fsm) & ~(ap_const_lv1_0 == or_cond_fu_2365_p2) & ~(ap_const_lv1_0 == tmp_2_fu_2371_p2))) begin
ap_reg_ppiten_pp0_it2 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp0_it3 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it3
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it3 <= ap_const_logic_0;
end else begin
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it3 <= ap_reg_ppiten_pp0_it2;
end else if (((ap_ST_st1_fsm_1 == ap_CS_fsm) & ~(ap_const_lv1_0 == or_cond_fu_2365_p2) & ~(ap_const_lv1_0 == tmp_2_fu_2371_p2))) begin
ap_reg_ppiten_pp0_it3 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp0_it4 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it4
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it4 <= ap_const_logic_0;
end else begin
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it4 <= ap_reg_ppiten_pp0_it3;
end else if (((ap_ST_st1_fsm_1 == ap_CS_fsm) & ~(ap_const_lv1_0 == or_cond_fu_2365_p2) & ~(ap_const_lv1_0 == tmp_2_fu_2371_p2))) begin
ap_reg_ppiten_pp0_it4 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp0_it5 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it5
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it5 <= ap_const_logic_0;
end else begin
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it5 <= ap_reg_ppiten_pp0_it4;
end else if (((ap_ST_st1_fsm_1 == ap_CS_fsm) & ~(ap_const_lv1_0 == or_cond_fu_2365_p2) & ~(ap_const_lv1_0 == tmp_2_fu_2371_p2))) begin
ap_reg_ppiten_pp0_it5 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp0_it6 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it6
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it6 <= ap_const_logic_0;
end else begin
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it6 <= ap_reg_ppiten_pp0_it5;
end else if (((ap_ST_st1_fsm_1 == ap_CS_fsm) & ~(ap_const_lv1_0 == or_cond_fu_2365_p2) & ~(ap_const_lv1_0 == tmp_2_fu_2371_p2))) begin
ap_reg_ppiten_pp0_it6 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp1_it0 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp1_it0
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp1_it0 <= ap_const_logic_0;
end else begin
if (((ap_ST_pp1_stg0_fsm_4 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond3_fu_2404_p2))) begin
ap_reg_ppiten_pp1_it0 <= ap_const_logic_0;
end else if ((ap_ST_st9_fsm_3 == ap_CS_fsm)) begin
ap_reg_ppiten_pp1_it0 <= ap_const_logic_1;
end
end
end
/// ap_reg_ppiten_pp1_it1 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp1_it1
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp1_it1 <= ap_const_logic_0;
end else begin
if (((ap_const_lv1_0 == exitcond3_reg_5195) & (ap_ST_pp1_stg7_fsm_11 == ap_CS_fsm))) begin
ap_reg_ppiten_pp1_it1 <= ap_const_logic_1;
end else if (((ap_ST_st9_fsm_3 == ap_CS_fsm) | ((ap_ST_pp1_stg7_fsm_11 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond3_reg_5195)))) begin
ap_reg_ppiten_pp1_it1 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp1_it2 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp1_it2
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp1_it2 <= ap_const_logic_0;
end else begin
if ((ap_ST_pp1_stg7_fsm_11 == ap_CS_fsm)) begin
ap_reg_ppiten_pp1_it2 <= ap_reg_ppiten_pp1_it1;
end else if ((ap_ST_st9_fsm_3 == ap_CS_fsm)) begin
ap_reg_ppiten_pp1_it2 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp1_it3 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp1_it3
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp1_it3 <= ap_const_logic_0;
end else begin
if ((ap_ST_pp1_stg7_fsm_11 == ap_CS_fsm)) begin
ap_reg_ppiten_pp1_it3 <= ap_reg_ppiten_pp1_it2;
end else if ((ap_ST_st9_fsm_3 == ap_CS_fsm)) begin
ap_reg_ppiten_pp1_it3 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp2_it0 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp2_it0
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp2_it0 <= ap_const_logic_0;
end else begin
if (((ap_ST_pp2_stg0_fsm_12 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond4_fu_2988_p2))) begin
ap_reg_ppiten_pp2_it0 <= ap_const_logic_0;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_ST_pp1_stg0_fsm_4 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond3_fu_2404_p2))) begin
ap_reg_ppiten_pp2_it0 <= ap_const_logic_1;
end
end
end
/// ap_reg_ppiten_pp2_it1 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp2_it1
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp2_it1 <= ap_const_logic_0;
end else begin
if (((ap_ST_pp2_stg0_fsm_12 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond4_fu_2988_p2))) begin
ap_reg_ppiten_pp2_it1 <= ap_const_logic_1;
end else if ((((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_ST_pp1_stg0_fsm_4 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond3_fu_2404_p2)) | ((ap_ST_pp2_stg0_fsm_12 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond4_fu_2988_p2)))) begin
ap_reg_ppiten_pp2_it1 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp2_it2 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp2_it2
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp2_it2 <= ap_const_logic_0;
end else begin
if ((ap_ST_pp2_stg0_fsm_12 == ap_CS_fsm)) begin
ap_reg_ppiten_pp2_it2 <= ap_reg_ppiten_pp2_it1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_ST_pp1_stg0_fsm_4 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond3_fu_2404_p2))) begin
ap_reg_ppiten_pp2_it2 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp2_it3 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp2_it3
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp2_it3 <= ap_const_logic_0;
end else begin
if ((ap_ST_pp2_stg0_fsm_12 == ap_CS_fsm)) begin
ap_reg_ppiten_pp2_it3 <= ap_reg_ppiten_pp2_it2;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_ST_pp1_stg0_fsm_4 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond3_fu_2404_p2))) begin
ap_reg_ppiten_pp2_it3 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp2_it4 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp2_it4
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp2_it4 <= ap_const_logic_0;
end else begin
if ((ap_ST_pp2_stg0_fsm_12 == ap_CS_fsm)) begin
ap_reg_ppiten_pp2_it4 <= ap_reg_ppiten_pp2_it3;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_ST_pp1_stg0_fsm_4 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond3_fu_2404_p2))) begin
ap_reg_ppiten_pp2_it4 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp2_it5 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp2_it5
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp2_it5 <= ap_const_logic_0;
end else begin
if ((ap_ST_pp2_stg0_fsm_12 == ap_CS_fsm)) begin
ap_reg_ppiten_pp2_it5 <= ap_reg_ppiten_pp2_it4;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_ST_pp1_stg0_fsm_4 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond3_fu_2404_p2))) begin
ap_reg_ppiten_pp2_it5 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp2_it6 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp2_it6
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp2_it6 <= ap_const_logic_0;
end else begin
if ((ap_ST_pp2_stg0_fsm_12 == ap_CS_fsm)) begin
ap_reg_ppiten_pp2_it6 <= ap_reg_ppiten_pp2_it5;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_ST_pp1_stg0_fsm_4 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond3_fu_2404_p2))) begin
ap_reg_ppiten_pp2_it6 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp3_it0 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp3_it0
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp3_it0 <= ap_const_logic_0;
end else begin
if (((ap_ST_pp3_stg0_fsm_13 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond6_fu_3025_p2))) begin
ap_reg_ppiten_pp3_it0 <= ap_const_logic_0;
end else if (((ap_ST_pp2_stg0_fsm_12 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp2_it0) & ~(ap_const_lv1_0 == exitcond4_fu_2988_p2))) begin
ap_reg_ppiten_pp3_it0 <= ap_const_logic_1;
end
end
end
/// ap_reg_ppiten_pp3_it1 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp3_it1
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp3_it1 <= ap_const_logic_0;
end else begin
if (((ap_const_lv1_0 == exitcond6_reg_5446) & (ap_ST_pp3_stg7_fsm_20 == ap_CS_fsm))) begin
ap_reg_ppiten_pp3_it1 <= ap_const_logic_1;
end else if ((((ap_ST_pp2_stg0_fsm_12 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp2_it0) & ~(ap_const_lv1_0 == exitcond4_fu_2988_p2)) | ((ap_ST_pp3_stg7_fsm_20 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond6_reg_5446)))) begin
ap_reg_ppiten_pp3_it1 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp3_it2 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp3_it2
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp3_it2 <= ap_const_logic_0;
end else begin
if ((ap_ST_pp3_stg7_fsm_20 == ap_CS_fsm)) begin
ap_reg_ppiten_pp3_it2 <= ap_reg_ppiten_pp3_it1;
end else if (((ap_ST_pp2_stg0_fsm_12 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp2_it0) & ~(ap_const_lv1_0 == exitcond4_fu_2988_p2))) begin
ap_reg_ppiten_pp3_it2 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp3_it3 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp3_it3
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp3_it3 <= ap_const_logic_0;
end else begin
if ((ap_ST_pp3_stg7_fsm_20 == ap_CS_fsm)) begin
ap_reg_ppiten_pp3_it3 <= ap_reg_ppiten_pp3_it2;
end else if (((ap_ST_pp2_stg0_fsm_12 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp2_it0) & ~(ap_const_lv1_0 == exitcond4_fu_2988_p2))) begin
ap_reg_ppiten_pp3_it3 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp4_it0 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp4_it0
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp4_it0 <= ap_const_logic_0;
end else begin
if (((ap_ST_pp4_stg0_fsm_21 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond7_fu_3609_p2))) begin
ap_reg_ppiten_pp4_it0 <= ap_const_logic_0;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp3_it0) & (ap_ST_pp3_stg0_fsm_13 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond6_fu_3025_p2))) begin
ap_reg_ppiten_pp4_it0 <= ap_const_logic_1;
end
end
end
/// ap_reg_ppiten_pp4_it1 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp4_it1
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp4_it1 <= ap_const_logic_0;
end else begin
if (((ap_ST_pp4_stg0_fsm_21 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond7_fu_3609_p2))) begin
ap_reg_ppiten_pp4_it1 <= ap_const_logic_1;
end else if ((((ap_const_logic_1 == ap_reg_ppiten_pp3_it0) & (ap_ST_pp3_stg0_fsm_13 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond6_fu_3025_p2)) | ((ap_ST_pp4_stg0_fsm_21 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond7_fu_3609_p2)))) begin
ap_reg_ppiten_pp4_it1 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp4_it2 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp4_it2
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp4_it2 <= ap_const_logic_0;
end else begin
if ((ap_ST_pp4_stg0_fsm_21 == ap_CS_fsm)) begin
ap_reg_ppiten_pp4_it2 <= ap_reg_ppiten_pp4_it1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp3_it0) & (ap_ST_pp3_stg0_fsm_13 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond6_fu_3025_p2))) begin
ap_reg_ppiten_pp4_it2 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp4_it3 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp4_it3
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp4_it3 <= ap_const_logic_0;
end else begin
if ((ap_ST_pp4_stg0_fsm_21 == ap_CS_fsm)) begin
ap_reg_ppiten_pp4_it3 <= ap_reg_ppiten_pp4_it2;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp3_it0) & (ap_ST_pp3_stg0_fsm_13 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond6_fu_3025_p2))) begin
ap_reg_ppiten_pp4_it3 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp4_it4 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp4_it4
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp4_it4 <= ap_const_logic_0;
end else begin
if ((ap_ST_pp4_stg0_fsm_21 == ap_CS_fsm)) begin
ap_reg_ppiten_pp4_it4 <= ap_reg_ppiten_pp4_it3;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp3_it0) & (ap_ST_pp3_stg0_fsm_13 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond6_fu_3025_p2))) begin
ap_reg_ppiten_pp4_it4 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp4_it5 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp4_it5
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp4_it5 <= ap_const_logic_0;
end else begin
if ((ap_ST_pp4_stg0_fsm_21 == ap_CS_fsm)) begin
ap_reg_ppiten_pp4_it5 <= ap_reg_ppiten_pp4_it4;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp3_it0) & (ap_ST_pp3_stg0_fsm_13 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond6_fu_3025_p2))) begin
ap_reg_ppiten_pp4_it5 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp4_it6 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp4_it6
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp4_it6 <= ap_const_logic_0;
end else begin
if ((ap_ST_pp4_stg0_fsm_21 == ap_CS_fsm)) begin
ap_reg_ppiten_pp4_it6 <= ap_reg_ppiten_pp4_it5;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp3_it0) & (ap_ST_pp3_stg0_fsm_13 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond6_fu_3025_p2))) begin
ap_reg_ppiten_pp4_it6 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp5_it0 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp5_it0
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp5_it0 <= ap_const_logic_0;
end else begin
if (((ap_ST_pp5_stg0_fsm_22 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond9_fu_3626_p2))) begin
ap_reg_ppiten_pp5_it0 <= ap_const_logic_0;
end else if (((ap_ST_pp4_stg0_fsm_21 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp4_it0) & ~(ap_const_lv1_0 == exitcond7_fu_3609_p2))) begin
ap_reg_ppiten_pp5_it0 <= ap_const_logic_1;
end
end
end
/// ap_reg_ppiten_pp5_it1 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp5_it1
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp5_it1 <= ap_const_logic_0;
end else begin
if (((ap_const_lv1_0 == exitcond9_reg_5697) & (ap_ST_pp5_stg7_fsm_29 == ap_CS_fsm))) begin
ap_reg_ppiten_pp5_it1 <= ap_const_logic_1;
end else if ((((ap_ST_pp4_stg0_fsm_21 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp4_it0) & ~(ap_const_lv1_0 == exitcond7_fu_3609_p2)) | ((ap_ST_pp5_stg7_fsm_29 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond9_reg_5697)))) begin
ap_reg_ppiten_pp5_it1 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp5_it2 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp5_it2
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp5_it2 <= ap_const_logic_0;
end else begin
if ((ap_ST_pp5_stg7_fsm_29 == ap_CS_fsm)) begin
ap_reg_ppiten_pp5_it2 <= ap_reg_ppiten_pp5_it1;
end else if (((ap_ST_pp4_stg0_fsm_21 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp4_it0) & ~(ap_const_lv1_0 == exitcond7_fu_3609_p2))) begin
ap_reg_ppiten_pp5_it2 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp5_it3 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp5_it3
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp5_it3 <= ap_const_logic_0;
end else begin
if ((ap_ST_pp5_stg7_fsm_29 == ap_CS_fsm)) begin
ap_reg_ppiten_pp5_it3 <= ap_reg_ppiten_pp5_it2;
end else if (((ap_ST_pp4_stg0_fsm_21 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp4_it0) & ~(ap_const_lv1_0 == exitcond7_fu_3609_p2))) begin
ap_reg_ppiten_pp5_it3 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp6_it0 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp6_it0
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp6_it0 <= ap_const_logic_0;
end else begin
if (((ap_ST_pp6_stg0_fsm_30 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond10_fu_3978_p2))) begin
ap_reg_ppiten_pp6_it0 <= ap_const_logic_0;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp5_it0) & (ap_ST_pp5_stg0_fsm_22 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond9_fu_3626_p2))) begin
ap_reg_ppiten_pp6_it0 <= ap_const_logic_1;
end
end
end
/// ap_reg_ppiten_pp6_it1 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp6_it1
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp6_it1 <= ap_const_logic_0;
end else begin
if (((ap_ST_pp6_stg0_fsm_30 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond10_fu_3978_p2))) begin
ap_reg_ppiten_pp6_it1 <= ap_const_logic_1;
end else if ((((ap_const_logic_1 == ap_reg_ppiten_pp5_it0) & (ap_ST_pp5_stg0_fsm_22 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond9_fu_3626_p2)) | ((ap_ST_pp6_stg0_fsm_30 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond10_fu_3978_p2)))) begin
ap_reg_ppiten_pp6_it1 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp6_it2 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp6_it2
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp6_it2 <= ap_const_logic_0;
end else begin
if ((ap_ST_pp6_stg0_fsm_30 == ap_CS_fsm)) begin
ap_reg_ppiten_pp6_it2 <= ap_reg_ppiten_pp6_it1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp5_it0) & (ap_ST_pp5_stg0_fsm_22 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond9_fu_3626_p2))) begin
ap_reg_ppiten_pp6_it2 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp6_it3 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp6_it3
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp6_it3 <= ap_const_logic_0;
end else begin
if ((ap_ST_pp6_stg0_fsm_30 == ap_CS_fsm)) begin
ap_reg_ppiten_pp6_it3 <= ap_reg_ppiten_pp6_it2;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp5_it0) & (ap_ST_pp5_stg0_fsm_22 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond9_fu_3626_p2))) begin
ap_reg_ppiten_pp6_it3 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp6_it4 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp6_it4
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp6_it4 <= ap_const_logic_0;
end else begin
if ((ap_ST_pp6_stg0_fsm_30 == ap_CS_fsm)) begin
ap_reg_ppiten_pp6_it4 <= ap_reg_ppiten_pp6_it3;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp5_it0) & (ap_ST_pp5_stg0_fsm_22 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond9_fu_3626_p2))) begin
ap_reg_ppiten_pp6_it4 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp6_it5 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp6_it5
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp6_it5 <= ap_const_logic_0;
end else begin
if ((ap_ST_pp6_stg0_fsm_30 == ap_CS_fsm)) begin
ap_reg_ppiten_pp6_it5 <= ap_reg_ppiten_pp6_it4;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp5_it0) & (ap_ST_pp5_stg0_fsm_22 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond9_fu_3626_p2))) begin
ap_reg_ppiten_pp6_it5 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp6_it6 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp6_it6
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp6_it6 <= ap_const_logic_0;
end else begin
if ((ap_ST_pp6_stg0_fsm_30 == ap_CS_fsm)) begin
ap_reg_ppiten_pp6_it6 <= ap_reg_ppiten_pp6_it5;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp5_it0) & (ap_ST_pp5_stg0_fsm_22 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond9_fu_3626_p2))) begin
ap_reg_ppiten_pp6_it6 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp7_it0 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp7_it0
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp7_it0 <= ap_const_logic_0;
end else begin
if (((ap_ST_pp7_stg0_fsm_31 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond12_fu_4005_p2))) begin
ap_reg_ppiten_pp7_it0 <= ap_const_logic_0;
end else if (((ap_ST_pp6_stg0_fsm_30 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp6_it0) & ~(ap_const_lv1_0 == exitcond10_fu_3978_p2))) begin
ap_reg_ppiten_pp7_it0 <= ap_const_logic_1;
end
end
end
/// ap_reg_ppiten_pp7_it1 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp7_it1
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp7_it1 <= ap_const_logic_0;
end else begin
if (((ap_const_lv1_0 == exitcond12_reg_5924) & (ap_ST_pp7_stg7_fsm_38 == ap_CS_fsm))) begin
ap_reg_ppiten_pp7_it1 <= ap_const_logic_1;
end else if ((((ap_ST_pp6_stg0_fsm_30 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp6_it0) & ~(ap_const_lv1_0 == exitcond10_fu_3978_p2)) | ((ap_ST_pp7_stg7_fsm_38 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond12_reg_5924)))) begin
ap_reg_ppiten_pp7_it1 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp7_it2 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp7_it2
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp7_it2 <= ap_const_logic_0;
end else begin
if ((ap_ST_pp7_stg7_fsm_38 == ap_CS_fsm)) begin
ap_reg_ppiten_pp7_it2 <= ap_reg_ppiten_pp7_it1;
end else if (((ap_ST_pp6_stg0_fsm_30 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp6_it0) & ~(ap_const_lv1_0 == exitcond10_fu_3978_p2))) begin
ap_reg_ppiten_pp7_it2 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp7_it3 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp7_it3
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp7_it3 <= ap_const_logic_0;
end else begin
if ((ap_ST_pp7_stg7_fsm_38 == ap_CS_fsm)) begin
ap_reg_ppiten_pp7_it3 <= ap_reg_ppiten_pp7_it2;
end else if (((ap_ST_pp6_stg0_fsm_30 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp6_it0) & ~(ap_const_lv1_0 == exitcond10_fu_3978_p2))) begin
ap_reg_ppiten_pp7_it3 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp8_it0 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp8_it0
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp8_it0 <= ap_const_logic_0;
end else begin
if (((ap_ST_pp8_stg0_fsm_40 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond_fu_4357_p2))) begin
ap_reg_ppiten_pp8_it0 <= ap_const_logic_0;
end else if ((((ap_ST_st1_fsm_1 == ap_CS_fsm) & ~(ap_const_lv1_0 == or_cond_fu_2365_p2) & (ap_const_lv1_0 == tmp_2_fu_2371_p2)) | (ap_ST_st131_fsm_39 == ap_CS_fsm))) begin
ap_reg_ppiten_pp8_it0 <= ap_const_logic_1;
end
end
end
/// ap_reg_ppiten_pp8_it1 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp8_it1
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp8_it1 <= ap_const_logic_0;
end else begin
if (((ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg28_fsm_68 == ap_CS_fsm))) begin
ap_reg_ppiten_pp8_it1 <= ap_const_logic_1;
end else if ((((ap_ST_st1_fsm_1 == ap_CS_fsm) & ~(ap_const_lv1_0 == or_cond_fu_2365_p2) & (ap_const_lv1_0 == tmp_2_fu_2371_p2)) | (ap_ST_st131_fsm_39 == ap_CS_fsm) | ((ap_ST_pp8_stg28_fsm_68 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond_reg_6132)))) begin
ap_reg_ppiten_pp8_it1 <= ap_const_logic_0;
end
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_ST_pp1_stg0_fsm_4 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond3_fu_2404_p2))) begin
a_addr100_reg_5247 <= tmp_12_trn_cast_fu_2448_p1[6:0];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg24_fsm_64 == ap_CS_fsm))) begin
a_addr10_reg_6830 <= (a_addr18_cast_fu_5089_p1 + tmp_182_trn_cast_reg_6254);
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp3_it0) & (ap_const_lv1_0 == exitcond6_reg_5446) & (ap_ST_pp3_stg1_fsm_14 == ap_CS_fsm))) begin
a_addr112_reg_5548[0] <= a_addr112_fu_3266_p2[0];
a_addr112_reg_5548[2] <= a_addr112_fu_3266_p2[2];
a_addr112_reg_5548[3] <= a_addr112_fu_3266_p2[3];
a_addr112_reg_5548[4] <= a_addr112_fu_3266_p2[4];
a_addr112_reg_5548[5] <= a_addr112_fu_3266_p2[5];
a_addr112_reg_5548[6] <= a_addr112_fu_3266_p2[6];
end
if (((ap_ST_pp3_stg2_fsm_15 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp3_it0) & (ap_const_lv1_0 == exitcond6_reg_5446))) begin
a_addr116_reg_5608[0] <= a_addr116_fu_3424_p2[0];
a_addr116_reg_5608[1] <= a_addr116_fu_3424_p2[1];
a_addr116_reg_5608[3] <= a_addr116_fu_3424_p2[3];
a_addr116_reg_5608[4] <= a_addr116_fu_3424_p2[4];
a_addr116_reg_5608[5] <= a_addr116_fu_3424_p2[5];
a_addr116_reg_5608[6] <= a_addr116_fu_3424_p2[6];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg24_fsm_64 == ap_CS_fsm))) begin
a_addr13_reg_6825[2] <= a_addr13_fu_5103_p2[2];
a_addr13_reg_6825[3] <= a_addr13_fu_5103_p2[3];
a_addr13_reg_6825[4] <= a_addr13_fu_5103_p2[4];
a_addr13_reg_6825[5] <= a_addr13_fu_5103_p2[5];
a_addr13_reg_6825[6] <= a_addr13_fu_5103_p2[6];
a_addr13_reg_6825[7] <= a_addr13_fu_5103_p2[7];
a_addr13_reg_6825[8] <= a_addr13_fu_5103_p2[8];
a_addr13_reg_6825[9] <= a_addr13_fu_5103_p2[9];
a_addr13_reg_6825[10] <= a_addr13_fu_5103_p2[10];
a_addr13_reg_6825[11] <= a_addr13_fu_5103_p2[11];
a_addr13_reg_6825[12] <= a_addr13_fu_5103_p2[12];
a_addr13_reg_6825[13] <= a_addr13_fu_5103_p2[13];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg24_fsm_64 == ap_CS_fsm))) begin
a_addr16_reg_6820 <= (a_addr18_cast_fu_5089_p1 + tmp_178_trn_cast_reg_6212);
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg24_fsm_64 == ap_CS_fsm))) begin
a_addr19_reg_6815[1] <= a_addr19_fu_5093_p2[1];
a_addr19_reg_6815[2] <= a_addr19_fu_5093_p2[2];
a_addr19_reg_6815[3] <= a_addr19_fu_5093_p2[3];
a_addr19_reg_6815[4] <= a_addr19_fu_5093_p2[4];
a_addr19_reg_6815[5] <= a_addr19_fu_5093_p2[5];
a_addr19_reg_6815[6] <= a_addr19_fu_5093_p2[6];
a_addr19_reg_6815[7] <= a_addr19_fu_5093_p2[7];
a_addr19_reg_6815[8] <= a_addr19_fu_5093_p2[8];
a_addr19_reg_6815[9] <= a_addr19_fu_5093_p2[9];
a_addr19_reg_6815[10] <= a_addr19_fu_5093_p2[10];
a_addr19_reg_6815[11] <= a_addr19_fu_5093_p2[11];
a_addr19_reg_6815[12] <= a_addr19_fu_5093_p2[12];
a_addr19_reg_6815[13] <= a_addr19_fu_5093_p2[13];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg24_fsm_64 == ap_CS_fsm))) begin
a_addr1_reg_6845[3] <= a_addr1_fu_5123_p2[3];
a_addr1_reg_6845[4] <= a_addr1_fu_5123_p2[4];
a_addr1_reg_6845[5] <= a_addr1_fu_5123_p2[5];
a_addr1_reg_6845[6] <= a_addr1_fu_5123_p2[6];
a_addr1_reg_6845[7] <= a_addr1_fu_5123_p2[7];
a_addr1_reg_6845[8] <= a_addr1_fu_5123_p2[8];
a_addr1_reg_6845[9] <= a_addr1_fu_5123_p2[9];
a_addr1_reg_6845[10] <= a_addr1_fu_5123_p2[10];
a_addr1_reg_6845[11] <= a_addr1_fu_5123_p2[11];
a_addr1_reg_6845[12] <= a_addr1_fu_5123_p2[12];
a_addr1_reg_6845[13] <= a_addr1_fu_5123_p2[13];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg24_fsm_64 == ap_CS_fsm))) begin
a_addr22_reg_6810[3] <= a_addr22_fu_5075_p2[3];
a_addr22_reg_6810[4] <= a_addr22_fu_5075_p2[4];
a_addr22_reg_6810[5] <= a_addr22_fu_5075_p2[5];
a_addr22_reg_6810[6] <= a_addr22_fu_5075_p2[6];
a_addr22_reg_6810[7] <= a_addr22_fu_5075_p2[7];
a_addr22_reg_6810[8] <= a_addr22_fu_5075_p2[8];
a_addr22_reg_6810[9] <= a_addr22_fu_5075_p2[9];
a_addr22_reg_6810[10] <= a_addr22_fu_5075_p2[10];
a_addr22_reg_6810[11] <= a_addr22_fu_5075_p2[11];
a_addr22_reg_6810[12] <= a_addr22_fu_5075_p2[12];
a_addr22_reg_6810[13] <= a_addr22_fu_5075_p2[13];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond3_reg_5195) & (ap_ST_pp1_stg4_fsm_8 == ap_CS_fsm))) begin
a_addr23_reg_5382 <= (a_addr21_cast_fu_2892_p1 + tmp_6_trn_cast_reg_5226);
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond3_reg_5195) & (ap_ST_pp1_stg4_fsm_8 == ap_CS_fsm))) begin
a_addr25_reg_5392 <= (a_addr24_cast_fu_2941_p1 + tmp_6_trn_cast_reg_5226);
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp5_it0) & (ap_ST_pp5_stg0_fsm_22 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond9_fu_3626_p2))) begin
a_addr37_cast_reg_5729[6] <= a_addr37_cast_fu_3684_p1[6];
a_addr37_cast_reg_5729[7] <= a_addr37_cast_fu_3684_p1[7];
a_addr37_cast_reg_5729[8] <= a_addr37_cast_fu_3684_p1[8];
a_addr37_cast_reg_5729[9] <= a_addr37_cast_fu_3684_p1[9];
a_addr37_cast_reg_5729[10] <= a_addr37_cast_fu_3684_p1[10];
a_addr37_cast_reg_5729[11] <= a_addr37_cast_fu_3684_p1[11];
a_addr37_cast_reg_5729[12] <= a_addr37_cast_fu_3684_p1[12];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg22_fsm_62 == ap_CS_fsm))) begin
a_addr45_cast_reg_6741[6] <= a_addr45_cast_fu_5010_p1[6];
a_addr45_cast_reg_6741[9] <= a_addr45_cast_fu_5010_p1[9];
a_addr45_cast_reg_6741[10] <= a_addr45_cast_fu_5010_p1[10];
a_addr45_cast_reg_6741[11] <= a_addr45_cast_fu_5010_p1[11];
a_addr45_cast_reg_6741[12] <= a_addr45_cast_fu_5010_p1[12];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg24_fsm_64 == ap_CS_fsm))) begin
a_addr4_reg_6840 <= (a_addr18_cast_fu_5089_p1 + tmp_186_trn_cast_reg_6296);
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp5_it1) & (ap_ST_pp5_stg3_fsm_25 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond9_reg_5697_pp5_it1))) begin
a_addr50_reg_5890[3] <= a_addr50_fu_3969_p2[3];
a_addr50_reg_5890[4] <= a_addr50_fu_3969_p2[4];
a_addr50_reg_5890[5] <= a_addr50_fu_3969_p2[5];
a_addr50_reg_5890[6] <= a_addr50_fu_3969_p2[6];
a_addr50_reg_5890[7] <= a_addr50_fu_3969_p2[7];
a_addr50_reg_5890[8] <= a_addr50_fu_3969_p2[8];
a_addr50_reg_5890[9] <= a_addr50_fu_3969_p2[9];
a_addr50_reg_5890[10] <= a_addr50_fu_3969_p2[10];
a_addr50_reg_5890[11] <= a_addr50_fu_3969_p2[11];
a_addr50_reg_5890[12] <= a_addr50_fu_3969_p2[12];
a_addr50_reg_5890[13] <= a_addr50_fu_3969_p2[13];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp7_it0) & (ap_const_lv1_0 == exitcond12_reg_5924) & (ap_ST_pp7_stg1_fsm_32 == ap_CS_fsm))) begin
a_addr51_cast_reg_5982[6] <= a_addr51_cast_fu_4110_p1[6];
a_addr51_cast_reg_5982[7] <= a_addr51_cast_fu_4110_p1[7];
a_addr51_cast_reg_5982[8] <= a_addr51_cast_fu_4110_p1[8];
a_addr51_cast_reg_5982[9] <= a_addr51_cast_fu_4110_p1[9];
a_addr51_cast_reg_5982[10] <= a_addr51_cast_fu_4110_p1[10];
a_addr51_cast_reg_5982[11] <= a_addr51_cast_fu_4110_p1[11];
end
if (((ap_ST_pp8_stg0_fsm_40 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_fu_4357_p2))) begin
a_addr63_cast_reg_6165[6] <= a_addr63_cast_fu_4411_p1[6];
a_addr63_cast_reg_6165[7] <= a_addr63_cast_fu_4411_p1[7];
a_addr63_cast_reg_6165[8] <= a_addr63_cast_fu_4411_p1[8];
a_addr63_cast_reg_6165[9] <= a_addr63_cast_fu_4411_p1[9];
a_addr63_cast_reg_6165[10] <= a_addr63_cast_fu_4411_p1[10];
a_addr63_cast_reg_6165[11] <= a_addr63_cast_fu_4411_p1[11];
a_addr63_cast_reg_6165[12] <= a_addr63_cast_fu_4411_p1[12];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg18_fsm_58 == ap_CS_fsm))) begin
a_addr72_cast_reg_6661[7] <= a_addr72_cast_fu_4927_p1[7];
a_addr72_cast_reg_6661[9] <= a_addr72_cast_fu_4927_p1[9];
a_addr72_cast_reg_6661[10] <= a_addr72_cast_fu_4927_p1[10];
a_addr72_cast_reg_6661[11] <= a_addr72_cast_fu_4927_p1[11];
a_addr72_cast_reg_6661[12] <= a_addr72_cast_fu_4927_p1[12];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg4_fsm_44 == ap_CS_fsm))) begin
a_addr77_cast_reg_6338[7] <= a_addr77_cast_fu_4588_p1[7];
a_addr77_cast_reg_6338[8] <= a_addr77_cast_fu_4588_p1[8];
a_addr77_cast_reg_6338[9] <= a_addr77_cast_fu_4588_p1[9];
a_addr77_cast_reg_6338[10] <= a_addr77_cast_fu_4588_p1[10];
a_addr77_cast_reg_6338[11] <= a_addr77_cast_fu_4588_p1[11];
a_addr77_cast_reg_6338[12] <= a_addr77_cast_fu_4588_p1[12];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg24_fsm_64 == ap_CS_fsm))) begin
a_addr7_reg_6835[1] <= a_addr7_fu_5113_p2[1];
a_addr7_reg_6835[2] <= a_addr7_fu_5113_p2[2];
a_addr7_reg_6835[3] <= a_addr7_fu_5113_p2[3];
a_addr7_reg_6835[4] <= a_addr7_fu_5113_p2[4];
a_addr7_reg_6835[5] <= a_addr7_fu_5113_p2[5];
a_addr7_reg_6835[6] <= a_addr7_fu_5113_p2[6];
a_addr7_reg_6835[7] <= a_addr7_fu_5113_p2[7];
a_addr7_reg_6835[8] <= a_addr7_fu_5113_p2[8];
a_addr7_reg_6835[9] <= a_addr7_fu_5113_p2[9];
a_addr7_reg_6835[10] <= a_addr7_fu_5113_p2[10];
a_addr7_reg_6835[11] <= a_addr7_fu_5113_p2[11];
a_addr7_reg_6835[12] <= a_addr7_fu_5113_p2[12];
a_addr7_reg_6835[13] <= a_addr7_fu_5113_p2[13];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg8_fsm_48 == ap_CS_fsm))) begin
a_addr87_cast_reg_6423[6] <= a_addr87_cast_fu_4676_p1[6];
a_addr87_cast_reg_6423[8] <= a_addr87_cast_fu_4676_p1[8];
a_addr87_cast_reg_6423[9] <= a_addr87_cast_fu_4676_p1[9];
a_addr87_cast_reg_6423[10] <= a_addr87_cast_fu_4676_p1[10];
a_addr87_cast_reg_6423[11] <= a_addr87_cast_fu_4676_p1[11];
a_addr87_cast_reg_6423[12] <= a_addr87_cast_fu_4676_p1[12];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg11_fsm_51 == ap_CS_fsm))) begin
a_addr98_cast_reg_6502[8] <= a_addr98_cast_fu_4760_p1[8];
a_addr98_cast_reg_6502[9] <= a_addr98_cast_fu_4760_p1[9];
a_addr98_cast_reg_6502[10] <= a_addr98_cast_fu_4760_p1[10];
a_addr98_cast_reg_6502[11] <= a_addr98_cast_fu_4760_p1[11];
a_addr98_cast_reg_6502[12] <= a_addr98_cast_fu_4760_p1[12];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg15_fsm_55 == ap_CS_fsm))) begin
a_addr99_cast_reg_6582[6] <= a_addr99_cast_fu_4843_p1[6];
a_addr99_cast_reg_6582[7] <= a_addr99_cast_fu_4843_p1[7];
a_addr99_cast_reg_6582[9] <= a_addr99_cast_fu_4843_p1[9];
a_addr99_cast_reg_6582[10] <= a_addr99_cast_fu_4843_p1[10];
a_addr99_cast_reg_6582[11] <= a_addr99_cast_fu_4843_p1[11];
a_addr99_cast_reg_6582[12] <= a_addr99_cast_fu_4843_p1[12];
end
if ((ap_ST_pp5_stg0_fsm_22 == ap_CS_fsm)) begin
ap_reg_ppstg_a_addr37_cast_reg_5729_pp5_it1[6] <= a_addr37_cast_reg_5729[6];
ap_reg_ppstg_a_addr37_cast_reg_5729_pp5_it1[7] <= a_addr37_cast_reg_5729[7];
ap_reg_ppstg_a_addr37_cast_reg_5729_pp5_it1[8] <= a_addr37_cast_reg_5729[8];
ap_reg_ppstg_a_addr37_cast_reg_5729_pp5_it1[9] <= a_addr37_cast_reg_5729[9];
ap_reg_ppstg_a_addr37_cast_reg_5729_pp5_it1[10] <= a_addr37_cast_reg_5729[10];
ap_reg_ppstg_a_addr37_cast_reg_5729_pp5_it1[11] <= a_addr37_cast_reg_5729[11];
ap_reg_ppstg_a_addr37_cast_reg_5729_pp5_it1[12] <= a_addr37_cast_reg_5729[12];
end
if ((ap_ST_pp7_stg0_fsm_31 == ap_CS_fsm)) begin
ap_reg_ppstg_b_addr36_cast_reg_5956_pp7_it1[6] <= b_addr36_cast_reg_5956[6];
ap_reg_ppstg_b_addr36_cast_reg_5956_pp7_it1[7] <= b_addr36_cast_reg_5956[7];
ap_reg_ppstg_b_addr36_cast_reg_5956_pp7_it1[8] <= b_addr36_cast_reg_5956[8];
ap_reg_ppstg_b_addr36_cast_reg_5956_pp7_it1[9] <= b_addr36_cast_reg_5956[9];
ap_reg_ppstg_b_addr36_cast_reg_5956_pp7_it1[10] <= b_addr36_cast_reg_5956[10];
ap_reg_ppstg_b_addr36_cast_reg_5956_pp7_it1[11] <= b_addr36_cast_reg_5956[11];
ap_reg_ppstg_b_addr36_cast_reg_5956_pp7_it1[12] <= b_addr36_cast_reg_5956[12];
ap_reg_ppstg_b_addr36_cast_reg_5956_pp7_it1[13] <= b_addr36_cast_reg_5956[13];
end
if ((ap_ST_pp6_stg0_fsm_30 == ap_CS_fsm)) begin
ap_reg_ppstg_exitcond10_reg_5905_pp6_it1 <= exitcond10_reg_5905;
end
if ((ap_ST_pp6_stg0_fsm_30 == ap_CS_fsm)) begin
ap_reg_ppstg_exitcond10_reg_5905_pp6_it2 <= ap_reg_ppstg_exitcond10_reg_5905_pp6_it1;
end
if ((ap_ST_pp6_stg0_fsm_30 == ap_CS_fsm)) begin
ap_reg_ppstg_exitcond10_reg_5905_pp6_it3 <= ap_reg_ppstg_exitcond10_reg_5905_pp6_it2;
end
if ((ap_ST_pp6_stg0_fsm_30 == ap_CS_fsm)) begin
ap_reg_ppstg_exitcond10_reg_5905_pp6_it4 <= ap_reg_ppstg_exitcond10_reg_5905_pp6_it3;
end
if ((ap_ST_pp6_stg0_fsm_30 == ap_CS_fsm)) begin
ap_reg_ppstg_exitcond10_reg_5905_pp6_it5 <= ap_reg_ppstg_exitcond10_reg_5905_pp6_it4;
end
if ((ap_ST_pp7_stg0_fsm_31 == ap_CS_fsm)) begin
ap_reg_ppstg_exitcond12_reg_5924_pp7_it1 <= exitcond12_reg_5924;
end
if ((ap_ST_pp7_stg0_fsm_31 == ap_CS_fsm)) begin
ap_reg_ppstg_exitcond12_reg_5924_pp7_it2 <= ap_reg_ppstg_exitcond12_reg_5924_pp7_it1;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_exitcond1_reg_5171_pp0_it1 <= exitcond1_reg_5171;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_exitcond1_reg_5171_pp0_it2 <= ap_reg_ppstg_exitcond1_reg_5171_pp0_it1;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_exitcond1_reg_5171_pp0_it3 <= ap_reg_ppstg_exitcond1_reg_5171_pp0_it2;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_exitcond1_reg_5171_pp0_it4 <= ap_reg_ppstg_exitcond1_reg_5171_pp0_it3;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_exitcond1_reg_5171_pp0_it5 <= ap_reg_ppstg_exitcond1_reg_5171_pp0_it4;
end
if ((ap_ST_pp1_stg0_fsm_4 == ap_CS_fsm)) begin
ap_reg_ppstg_exitcond3_reg_5195_pp1_it1 <= exitcond3_reg_5195;
end
if ((ap_ST_pp1_stg0_fsm_4 == ap_CS_fsm)) begin
ap_reg_ppstg_exitcond3_reg_5195_pp1_it2 <= ap_reg_ppstg_exitcond3_reg_5195_pp1_it1;
end
if ((ap_ST_pp2_stg0_fsm_12 == ap_CS_fsm)) begin
ap_reg_ppstg_exitcond4_reg_5427_pp2_it1 <= exitcond4_reg_5427;
end
if ((ap_ST_pp2_stg0_fsm_12 == ap_CS_fsm)) begin
ap_reg_ppstg_exitcond4_reg_5427_pp2_it2 <= ap_reg_ppstg_exitcond4_reg_5427_pp2_it1;
end
if ((ap_ST_pp2_stg0_fsm_12 == ap_CS_fsm)) begin
ap_reg_ppstg_exitcond4_reg_5427_pp2_it3 <= ap_reg_ppstg_exitcond4_reg_5427_pp2_it2;
end
if ((ap_ST_pp2_stg0_fsm_12 == ap_CS_fsm)) begin
ap_reg_ppstg_exitcond4_reg_5427_pp2_it4 <= ap_reg_ppstg_exitcond4_reg_5427_pp2_it3;
end
if ((ap_ST_pp2_stg0_fsm_12 == ap_CS_fsm)) begin
ap_reg_ppstg_exitcond4_reg_5427_pp2_it5 <= ap_reg_ppstg_exitcond4_reg_5427_pp2_it4;
end
if ((ap_ST_pp3_stg0_fsm_13 == ap_CS_fsm)) begin
ap_reg_ppstg_exitcond6_reg_5446_pp3_it1 <= exitcond6_reg_5446;
end
if ((ap_ST_pp3_stg0_fsm_13 == ap_CS_fsm)) begin
ap_reg_ppstg_exitcond6_reg_5446_pp3_it2 <= ap_reg_ppstg_exitcond6_reg_5446_pp3_it1;
end
if ((ap_ST_pp4_stg0_fsm_21 == ap_CS_fsm)) begin
ap_reg_ppstg_exitcond7_reg_5678_pp4_it1 <= exitcond7_reg_5678;
end
if ((ap_ST_pp4_stg0_fsm_21 == ap_CS_fsm)) begin
ap_reg_ppstg_exitcond7_reg_5678_pp4_it2 <= ap_reg_ppstg_exitcond7_reg_5678_pp4_it1;
end
if ((ap_ST_pp4_stg0_fsm_21 == ap_CS_fsm)) begin
ap_reg_ppstg_exitcond7_reg_5678_pp4_it3 <= ap_reg_ppstg_exitcond7_reg_5678_pp4_it2;
end
if ((ap_ST_pp4_stg0_fsm_21 == ap_CS_fsm)) begin
ap_reg_ppstg_exitcond7_reg_5678_pp4_it4 <= ap_reg_ppstg_exitcond7_reg_5678_pp4_it3;
end
if ((ap_ST_pp4_stg0_fsm_21 == ap_CS_fsm)) begin
ap_reg_ppstg_exitcond7_reg_5678_pp4_it5 <= ap_reg_ppstg_exitcond7_reg_5678_pp4_it4;
end
if ((ap_ST_pp5_stg0_fsm_22 == ap_CS_fsm)) begin
ap_reg_ppstg_exitcond9_reg_5697_pp5_it1 <= exitcond9_reg_5697;
end
if ((ap_ST_pp5_stg0_fsm_22 == ap_CS_fsm)) begin
ap_reg_ppstg_exitcond9_reg_5697_pp5_it2 <= ap_reg_ppstg_exitcond9_reg_5697_pp5_it1;
end
if ((ap_ST_pp3_stg3_fsm_16 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_106_reg_5658_pp3_it2 <= tmp_106_reg_5658;
end
if ((ap_ST_pp3_stg4_fsm_17 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_114_reg_5668_pp3_it2 <= tmp_114_reg_5668;
end
if ((ap_ST_pp4_stg0_fsm_21 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_122_reg_5687_pp4_it1[0] <= tmp_122_reg_5687[0];
ap_reg_ppstg_tmp_122_reg_5687_pp4_it1[1] <= tmp_122_reg_5687[1];
ap_reg_ppstg_tmp_122_reg_5687_pp4_it1[2] <= tmp_122_reg_5687[2];
ap_reg_ppstg_tmp_122_reg_5687_pp4_it1[3] <= tmp_122_reg_5687[3];
ap_reg_ppstg_tmp_122_reg_5687_pp4_it1[4] <= tmp_122_reg_5687[4];
ap_reg_ppstg_tmp_122_reg_5687_pp4_it1[5] <= tmp_122_reg_5687[5];
ap_reg_ppstg_tmp_122_reg_5687_pp4_it1[6] <= tmp_122_reg_5687[6];
end
if ((ap_ST_pp4_stg0_fsm_21 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_122_reg_5687_pp4_it2[0] <= ap_reg_ppstg_tmp_122_reg_5687_pp4_it1[0];
ap_reg_ppstg_tmp_122_reg_5687_pp4_it2[1] <= ap_reg_ppstg_tmp_122_reg_5687_pp4_it1[1];
ap_reg_ppstg_tmp_122_reg_5687_pp4_it2[2] <= ap_reg_ppstg_tmp_122_reg_5687_pp4_it1[2];
ap_reg_ppstg_tmp_122_reg_5687_pp4_it2[3] <= ap_reg_ppstg_tmp_122_reg_5687_pp4_it1[3];
ap_reg_ppstg_tmp_122_reg_5687_pp4_it2[4] <= ap_reg_ppstg_tmp_122_reg_5687_pp4_it1[4];
ap_reg_ppstg_tmp_122_reg_5687_pp4_it2[5] <= ap_reg_ppstg_tmp_122_reg_5687_pp4_it1[5];
ap_reg_ppstg_tmp_122_reg_5687_pp4_it2[6] <= ap_reg_ppstg_tmp_122_reg_5687_pp4_it1[6];
end
if ((ap_ST_pp4_stg0_fsm_21 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_122_reg_5687_pp4_it3[0] <= ap_reg_ppstg_tmp_122_reg_5687_pp4_it2[0];
ap_reg_ppstg_tmp_122_reg_5687_pp4_it3[1] <= ap_reg_ppstg_tmp_122_reg_5687_pp4_it2[1];
ap_reg_ppstg_tmp_122_reg_5687_pp4_it3[2] <= ap_reg_ppstg_tmp_122_reg_5687_pp4_it2[2];
ap_reg_ppstg_tmp_122_reg_5687_pp4_it3[3] <= ap_reg_ppstg_tmp_122_reg_5687_pp4_it2[3];
ap_reg_ppstg_tmp_122_reg_5687_pp4_it3[4] <= ap_reg_ppstg_tmp_122_reg_5687_pp4_it2[4];
ap_reg_ppstg_tmp_122_reg_5687_pp4_it3[5] <= ap_reg_ppstg_tmp_122_reg_5687_pp4_it2[5];
ap_reg_ppstg_tmp_122_reg_5687_pp4_it3[6] <= ap_reg_ppstg_tmp_122_reg_5687_pp4_it2[6];
end
if ((ap_ST_pp4_stg0_fsm_21 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_122_reg_5687_pp4_it4[0] <= ap_reg_ppstg_tmp_122_reg_5687_pp4_it3[0];
ap_reg_ppstg_tmp_122_reg_5687_pp4_it4[1] <= ap_reg_ppstg_tmp_122_reg_5687_pp4_it3[1];
ap_reg_ppstg_tmp_122_reg_5687_pp4_it4[2] <= ap_reg_ppstg_tmp_122_reg_5687_pp4_it3[2];
ap_reg_ppstg_tmp_122_reg_5687_pp4_it4[3] <= ap_reg_ppstg_tmp_122_reg_5687_pp4_it3[3];
ap_reg_ppstg_tmp_122_reg_5687_pp4_it4[4] <= ap_reg_ppstg_tmp_122_reg_5687_pp4_it3[4];
ap_reg_ppstg_tmp_122_reg_5687_pp4_it4[5] <= ap_reg_ppstg_tmp_122_reg_5687_pp4_it3[5];
ap_reg_ppstg_tmp_122_reg_5687_pp4_it4[6] <= ap_reg_ppstg_tmp_122_reg_5687_pp4_it3[6];
end
if ((ap_ST_pp4_stg0_fsm_21 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_122_reg_5687_pp4_it5[0] <= ap_reg_ppstg_tmp_122_reg_5687_pp4_it4[0];
ap_reg_ppstg_tmp_122_reg_5687_pp4_it5[1] <= ap_reg_ppstg_tmp_122_reg_5687_pp4_it4[1];
ap_reg_ppstg_tmp_122_reg_5687_pp4_it5[2] <= ap_reg_ppstg_tmp_122_reg_5687_pp4_it4[2];
ap_reg_ppstg_tmp_122_reg_5687_pp4_it5[3] <= ap_reg_ppstg_tmp_122_reg_5687_pp4_it4[3];
ap_reg_ppstg_tmp_122_reg_5687_pp4_it5[4] <= ap_reg_ppstg_tmp_122_reg_5687_pp4_it4[4];
ap_reg_ppstg_tmp_122_reg_5687_pp4_it5[5] <= ap_reg_ppstg_tmp_122_reg_5687_pp4_it4[5];
ap_reg_ppstg_tmp_122_reg_5687_pp4_it5[6] <= ap_reg_ppstg_tmp_122_reg_5687_pp4_it4[6];
end
if ((ap_ST_pp5_stg0_fsm_22 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_125_reg_5740_pp5_it1[0] <= tmp_125_reg_5740[0];
ap_reg_ppstg_tmp_125_reg_5740_pp5_it1[1] <= tmp_125_reg_5740[1];
ap_reg_ppstg_tmp_125_reg_5740_pp5_it1[2] <= tmp_125_reg_5740[2];
ap_reg_ppstg_tmp_125_reg_5740_pp5_it1[3] <= tmp_125_reg_5740[3];
ap_reg_ppstg_tmp_125_reg_5740_pp5_it1[4] <= tmp_125_reg_5740[4];
ap_reg_ppstg_tmp_125_reg_5740_pp5_it1[5] <= tmp_125_reg_5740[5];
ap_reg_ppstg_tmp_125_reg_5740_pp5_it1[6] <= tmp_125_reg_5740[6];
ap_reg_ppstg_tmp_125_reg_5740_pp5_it1[7] <= tmp_125_reg_5740[7];
ap_reg_ppstg_tmp_125_reg_5740_pp5_it1[8] <= tmp_125_reg_5740[8];
ap_reg_ppstg_tmp_125_reg_5740_pp5_it1[9] <= tmp_125_reg_5740[9];
ap_reg_ppstg_tmp_125_reg_5740_pp5_it1[10] <= tmp_125_reg_5740[10];
ap_reg_ppstg_tmp_125_reg_5740_pp5_it1[11] <= tmp_125_reg_5740[11];
ap_reg_ppstg_tmp_125_reg_5740_pp5_it1[12] <= tmp_125_reg_5740[12];
ap_reg_ppstg_tmp_125_reg_5740_pp5_it1[13] <= tmp_125_reg_5740[13];
end
if ((ap_ST_pp5_stg1_fsm_23 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_130_reg_5770_pp5_it1[1] <= tmp_130_reg_5770[1];
ap_reg_ppstg_tmp_130_reg_5770_pp5_it1[2] <= tmp_130_reg_5770[2];
ap_reg_ppstg_tmp_130_reg_5770_pp5_it1[3] <= tmp_130_reg_5770[3];
ap_reg_ppstg_tmp_130_reg_5770_pp5_it1[4] <= tmp_130_reg_5770[4];
ap_reg_ppstg_tmp_130_reg_5770_pp5_it1[5] <= tmp_130_reg_5770[5];
ap_reg_ppstg_tmp_130_reg_5770_pp5_it1[6] <= tmp_130_reg_5770[6];
ap_reg_ppstg_tmp_130_reg_5770_pp5_it1[7] <= tmp_130_reg_5770[7];
ap_reg_ppstg_tmp_130_reg_5770_pp5_it1[8] <= tmp_130_reg_5770[8];
ap_reg_ppstg_tmp_130_reg_5770_pp5_it1[9] <= tmp_130_reg_5770[9];
ap_reg_ppstg_tmp_130_reg_5770_pp5_it1[10] <= tmp_130_reg_5770[10];
ap_reg_ppstg_tmp_130_reg_5770_pp5_it1[11] <= tmp_130_reg_5770[11];
ap_reg_ppstg_tmp_130_reg_5770_pp5_it1[12] <= tmp_130_reg_5770[12];
ap_reg_ppstg_tmp_130_reg_5770_pp5_it1[13] <= tmp_130_reg_5770[13];
end
if ((ap_ST_pp5_stg1_fsm_23 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_138_reg_5790_pp5_it1[0] <= tmp_138_reg_5790[0];
ap_reg_ppstg_tmp_138_reg_5790_pp5_it1[1] <= tmp_138_reg_5790[1];
ap_reg_ppstg_tmp_138_reg_5790_pp5_it1[2] <= tmp_138_reg_5790[2];
ap_reg_ppstg_tmp_138_reg_5790_pp5_it1[3] <= tmp_138_reg_5790[3];
ap_reg_ppstg_tmp_138_reg_5790_pp5_it1[4] <= tmp_138_reg_5790[4];
ap_reg_ppstg_tmp_138_reg_5790_pp5_it1[5] <= tmp_138_reg_5790[5];
ap_reg_ppstg_tmp_138_reg_5790_pp5_it1[6] <= tmp_138_reg_5790[6];
ap_reg_ppstg_tmp_138_reg_5790_pp5_it1[7] <= tmp_138_reg_5790[7];
ap_reg_ppstg_tmp_138_reg_5790_pp5_it1[8] <= tmp_138_reg_5790[8];
ap_reg_ppstg_tmp_138_reg_5790_pp5_it1[9] <= tmp_138_reg_5790[9];
ap_reg_ppstg_tmp_138_reg_5790_pp5_it1[10] <= tmp_138_reg_5790[10];
ap_reg_ppstg_tmp_138_reg_5790_pp5_it1[11] <= tmp_138_reg_5790[11];
ap_reg_ppstg_tmp_138_reg_5790_pp5_it1[12] <= tmp_138_reg_5790[12];
ap_reg_ppstg_tmp_138_reg_5790_pp5_it1[13] <= tmp_138_reg_5790[13];
end
if ((ap_ST_pp5_stg2_fsm_24 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_146_reg_5805_pp5_it1[2] <= tmp_146_reg_5805[2];
ap_reg_ppstg_tmp_146_reg_5805_pp5_it1[3] <= tmp_146_reg_5805[3];
ap_reg_ppstg_tmp_146_reg_5805_pp5_it1[4] <= tmp_146_reg_5805[4];
ap_reg_ppstg_tmp_146_reg_5805_pp5_it1[5] <= tmp_146_reg_5805[5];
ap_reg_ppstg_tmp_146_reg_5805_pp5_it1[6] <= tmp_146_reg_5805[6];
ap_reg_ppstg_tmp_146_reg_5805_pp5_it1[7] <= tmp_146_reg_5805[7];
ap_reg_ppstg_tmp_146_reg_5805_pp5_it1[8] <= tmp_146_reg_5805[8];
ap_reg_ppstg_tmp_146_reg_5805_pp5_it1[9] <= tmp_146_reg_5805[9];
ap_reg_ppstg_tmp_146_reg_5805_pp5_it1[10] <= tmp_146_reg_5805[10];
ap_reg_ppstg_tmp_146_reg_5805_pp5_it1[11] <= tmp_146_reg_5805[11];
ap_reg_ppstg_tmp_146_reg_5805_pp5_it1[12] <= tmp_146_reg_5805[12];
ap_reg_ppstg_tmp_146_reg_5805_pp5_it1[13] <= tmp_146_reg_5805[13];
end
if ((ap_ST_pp5_stg2_fsm_24 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_154_reg_5825_pp5_it1[0] <= tmp_154_reg_5825[0];
ap_reg_ppstg_tmp_154_reg_5825_pp5_it1[1] <= tmp_154_reg_5825[1];
ap_reg_ppstg_tmp_154_reg_5825_pp5_it1[2] <= tmp_154_reg_5825[2];
ap_reg_ppstg_tmp_154_reg_5825_pp5_it1[3] <= tmp_154_reg_5825[3];
ap_reg_ppstg_tmp_154_reg_5825_pp5_it1[4] <= tmp_154_reg_5825[4];
ap_reg_ppstg_tmp_154_reg_5825_pp5_it1[5] <= tmp_154_reg_5825[5];
ap_reg_ppstg_tmp_154_reg_5825_pp5_it1[6] <= tmp_154_reg_5825[6];
ap_reg_ppstg_tmp_154_reg_5825_pp5_it1[7] <= tmp_154_reg_5825[7];
ap_reg_ppstg_tmp_154_reg_5825_pp5_it1[8] <= tmp_154_reg_5825[8];
ap_reg_ppstg_tmp_154_reg_5825_pp5_it1[9] <= tmp_154_reg_5825[9];
ap_reg_ppstg_tmp_154_reg_5825_pp5_it1[10] <= tmp_154_reg_5825[10];
ap_reg_ppstg_tmp_154_reg_5825_pp5_it1[11] <= tmp_154_reg_5825[11];
ap_reg_ppstg_tmp_154_reg_5825_pp5_it1[12] <= tmp_154_reg_5825[12];
ap_reg_ppstg_tmp_154_reg_5825_pp5_it1[13] <= tmp_154_reg_5825[13];
end
if ((ap_ST_pp1_stg1_fsm_5 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_15_reg_5272_pp1_it1[0] <= tmp_15_reg_5272[0];
ap_reg_ppstg_tmp_15_reg_5272_pp1_it1[1] <= tmp_15_reg_5272[1];
ap_reg_ppstg_tmp_15_reg_5272_pp1_it1[2] <= tmp_15_reg_5272[2];
ap_reg_ppstg_tmp_15_reg_5272_pp1_it1[3] <= tmp_15_reg_5272[3];
ap_reg_ppstg_tmp_15_reg_5272_pp1_it1[4] <= tmp_15_reg_5272[4];
ap_reg_ppstg_tmp_15_reg_5272_pp1_it1[5] <= tmp_15_reg_5272[5];
ap_reg_ppstg_tmp_15_reg_5272_pp1_it1[6] <= tmp_15_reg_5272[6];
ap_reg_ppstg_tmp_15_reg_5272_pp1_it1[7] <= tmp_15_reg_5272[7];
ap_reg_ppstg_tmp_15_reg_5272_pp1_it1[8] <= tmp_15_reg_5272[8];
ap_reg_ppstg_tmp_15_reg_5272_pp1_it1[9] <= tmp_15_reg_5272[9];
ap_reg_ppstg_tmp_15_reg_5272_pp1_it1[10] <= tmp_15_reg_5272[10];
ap_reg_ppstg_tmp_15_reg_5272_pp1_it1[11] <= tmp_15_reg_5272[11];
ap_reg_ppstg_tmp_15_reg_5272_pp1_it1[12] <= tmp_15_reg_5272[12];
ap_reg_ppstg_tmp_15_reg_5272_pp1_it1[13] <= tmp_15_reg_5272[13];
end
if ((ap_ST_pp5_stg3_fsm_25 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_160_reg_5840_pp5_it1[1] <= tmp_160_reg_5840[1];
ap_reg_ppstg_tmp_160_reg_5840_pp5_it1[2] <= tmp_160_reg_5840[2];
ap_reg_ppstg_tmp_160_reg_5840_pp5_it1[3] <= tmp_160_reg_5840[3];
ap_reg_ppstg_tmp_160_reg_5840_pp5_it1[4] <= tmp_160_reg_5840[4];
ap_reg_ppstg_tmp_160_reg_5840_pp5_it1[5] <= tmp_160_reg_5840[5];
ap_reg_ppstg_tmp_160_reg_5840_pp5_it1[6] <= tmp_160_reg_5840[6];
ap_reg_ppstg_tmp_160_reg_5840_pp5_it1[7] <= tmp_160_reg_5840[7];
ap_reg_ppstg_tmp_160_reg_5840_pp5_it1[8] <= tmp_160_reg_5840[8];
ap_reg_ppstg_tmp_160_reg_5840_pp5_it1[9] <= tmp_160_reg_5840[9];
ap_reg_ppstg_tmp_160_reg_5840_pp5_it1[10] <= tmp_160_reg_5840[10];
ap_reg_ppstg_tmp_160_reg_5840_pp5_it1[11] <= tmp_160_reg_5840[11];
ap_reg_ppstg_tmp_160_reg_5840_pp5_it1[12] <= tmp_160_reg_5840[12];
ap_reg_ppstg_tmp_160_reg_5840_pp5_it1[13] <= tmp_160_reg_5840[13];
end
if ((ap_ST_pp5_stg3_fsm_25 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_160_reg_5840_pp5_it2[1] <= ap_reg_ppstg_tmp_160_reg_5840_pp5_it1[1];
ap_reg_ppstg_tmp_160_reg_5840_pp5_it2[2] <= ap_reg_ppstg_tmp_160_reg_5840_pp5_it1[2];
ap_reg_ppstg_tmp_160_reg_5840_pp5_it2[3] <= ap_reg_ppstg_tmp_160_reg_5840_pp5_it1[3];
ap_reg_ppstg_tmp_160_reg_5840_pp5_it2[4] <= ap_reg_ppstg_tmp_160_reg_5840_pp5_it1[4];
ap_reg_ppstg_tmp_160_reg_5840_pp5_it2[5] <= ap_reg_ppstg_tmp_160_reg_5840_pp5_it1[5];
ap_reg_ppstg_tmp_160_reg_5840_pp5_it2[6] <= ap_reg_ppstg_tmp_160_reg_5840_pp5_it1[6];
ap_reg_ppstg_tmp_160_reg_5840_pp5_it2[7] <= ap_reg_ppstg_tmp_160_reg_5840_pp5_it1[7];
ap_reg_ppstg_tmp_160_reg_5840_pp5_it2[8] <= ap_reg_ppstg_tmp_160_reg_5840_pp5_it1[8];
ap_reg_ppstg_tmp_160_reg_5840_pp5_it2[9] <= ap_reg_ppstg_tmp_160_reg_5840_pp5_it1[9];
ap_reg_ppstg_tmp_160_reg_5840_pp5_it2[10] <= ap_reg_ppstg_tmp_160_reg_5840_pp5_it1[10];
ap_reg_ppstg_tmp_160_reg_5840_pp5_it2[11] <= ap_reg_ppstg_tmp_160_reg_5840_pp5_it1[11];
ap_reg_ppstg_tmp_160_reg_5840_pp5_it2[12] <= ap_reg_ppstg_tmp_160_reg_5840_pp5_it1[12];
ap_reg_ppstg_tmp_160_reg_5840_pp5_it2[13] <= ap_reg_ppstg_tmp_160_reg_5840_pp5_it1[13];
end
if ((ap_ST_pp5_stg3_fsm_25 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_164_reg_5880_pp5_it2[0] <= tmp_164_reg_5880[0];
ap_reg_ppstg_tmp_164_reg_5880_pp5_it2[1] <= tmp_164_reg_5880[1];
ap_reg_ppstg_tmp_164_reg_5880_pp5_it2[2] <= tmp_164_reg_5880[2];
ap_reg_ppstg_tmp_164_reg_5880_pp5_it2[3] <= tmp_164_reg_5880[3];
ap_reg_ppstg_tmp_164_reg_5880_pp5_it2[4] <= tmp_164_reg_5880[4];
ap_reg_ppstg_tmp_164_reg_5880_pp5_it2[5] <= tmp_164_reg_5880[5];
ap_reg_ppstg_tmp_164_reg_5880_pp5_it2[6] <= tmp_164_reg_5880[6];
ap_reg_ppstg_tmp_164_reg_5880_pp5_it2[7] <= tmp_164_reg_5880[7];
ap_reg_ppstg_tmp_164_reg_5880_pp5_it2[8] <= tmp_164_reg_5880[8];
ap_reg_ppstg_tmp_164_reg_5880_pp5_it2[9] <= tmp_164_reg_5880[9];
ap_reg_ppstg_tmp_164_reg_5880_pp5_it2[10] <= tmp_164_reg_5880[10];
ap_reg_ppstg_tmp_164_reg_5880_pp5_it2[11] <= tmp_164_reg_5880[11];
ap_reg_ppstg_tmp_164_reg_5880_pp5_it2[12] <= tmp_164_reg_5880[12];
ap_reg_ppstg_tmp_164_reg_5880_pp5_it2[13] <= tmp_164_reg_5880[13];
end
if ((ap_ST_pp5_stg4_fsm_26 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_168_reg_5895_pp5_it2[3] <= tmp_168_reg_5895[3];
ap_reg_ppstg_tmp_168_reg_5895_pp5_it2[4] <= tmp_168_reg_5895[4];
ap_reg_ppstg_tmp_168_reg_5895_pp5_it2[5] <= tmp_168_reg_5895[5];
ap_reg_ppstg_tmp_168_reg_5895_pp5_it2[6] <= tmp_168_reg_5895[6];
ap_reg_ppstg_tmp_168_reg_5895_pp5_it2[7] <= tmp_168_reg_5895[7];
ap_reg_ppstg_tmp_168_reg_5895_pp5_it2[8] <= tmp_168_reg_5895[8];
ap_reg_ppstg_tmp_168_reg_5895_pp5_it2[9] <= tmp_168_reg_5895[9];
ap_reg_ppstg_tmp_168_reg_5895_pp5_it2[10] <= tmp_168_reg_5895[10];
ap_reg_ppstg_tmp_168_reg_5895_pp5_it2[11] <= tmp_168_reg_5895[11];
ap_reg_ppstg_tmp_168_reg_5895_pp5_it2[12] <= tmp_168_reg_5895[12];
ap_reg_ppstg_tmp_168_reg_5895_pp5_it2[13] <= tmp_168_reg_5895[13];
end
if ((ap_ST_pp6_stg0_fsm_30 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_172_reg_5914_pp6_it1[0] <= tmp_172_reg_5914[0];
ap_reg_ppstg_tmp_172_reg_5914_pp6_it1[1] <= tmp_172_reg_5914[1];
ap_reg_ppstg_tmp_172_reg_5914_pp6_it1[2] <= tmp_172_reg_5914[2];
ap_reg_ppstg_tmp_172_reg_5914_pp6_it1[3] <= tmp_172_reg_5914[3];
ap_reg_ppstg_tmp_172_reg_5914_pp6_it1[4] <= tmp_172_reg_5914[4];
ap_reg_ppstg_tmp_172_reg_5914_pp6_it1[5] <= tmp_172_reg_5914[5];
ap_reg_ppstg_tmp_172_reg_5914_pp6_it1[6] <= tmp_172_reg_5914[6];
ap_reg_ppstg_tmp_172_reg_5914_pp6_it1[7] <= tmp_172_reg_5914[7];
ap_reg_ppstg_tmp_172_reg_5914_pp6_it1[8] <= tmp_172_reg_5914[8];
ap_reg_ppstg_tmp_172_reg_5914_pp6_it1[9] <= tmp_172_reg_5914[9];
ap_reg_ppstg_tmp_172_reg_5914_pp6_it1[10] <= tmp_172_reg_5914[10];
ap_reg_ppstg_tmp_172_reg_5914_pp6_it1[11] <= tmp_172_reg_5914[11];
ap_reg_ppstg_tmp_172_reg_5914_pp6_it1[12] <= tmp_172_reg_5914[12];
end
if ((ap_ST_pp6_stg0_fsm_30 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_172_reg_5914_pp6_it2[0] <= ap_reg_ppstg_tmp_172_reg_5914_pp6_it1[0];
ap_reg_ppstg_tmp_172_reg_5914_pp6_it2[1] <= ap_reg_ppstg_tmp_172_reg_5914_pp6_it1[1];
ap_reg_ppstg_tmp_172_reg_5914_pp6_it2[2] <= ap_reg_ppstg_tmp_172_reg_5914_pp6_it1[2];
ap_reg_ppstg_tmp_172_reg_5914_pp6_it2[3] <= ap_reg_ppstg_tmp_172_reg_5914_pp6_it1[3];
ap_reg_ppstg_tmp_172_reg_5914_pp6_it2[4] <= ap_reg_ppstg_tmp_172_reg_5914_pp6_it1[4];
ap_reg_ppstg_tmp_172_reg_5914_pp6_it2[5] <= ap_reg_ppstg_tmp_172_reg_5914_pp6_it1[5];
ap_reg_ppstg_tmp_172_reg_5914_pp6_it2[6] <= ap_reg_ppstg_tmp_172_reg_5914_pp6_it1[6];
ap_reg_ppstg_tmp_172_reg_5914_pp6_it2[7] <= ap_reg_ppstg_tmp_172_reg_5914_pp6_it1[7];
ap_reg_ppstg_tmp_172_reg_5914_pp6_it2[8] <= ap_reg_ppstg_tmp_172_reg_5914_pp6_it1[8];
ap_reg_ppstg_tmp_172_reg_5914_pp6_it2[9] <= ap_reg_ppstg_tmp_172_reg_5914_pp6_it1[9];
ap_reg_ppstg_tmp_172_reg_5914_pp6_it2[10] <= ap_reg_ppstg_tmp_172_reg_5914_pp6_it1[10];
ap_reg_ppstg_tmp_172_reg_5914_pp6_it2[11] <= ap_reg_ppstg_tmp_172_reg_5914_pp6_it1[11];
ap_reg_ppstg_tmp_172_reg_5914_pp6_it2[12] <= ap_reg_ppstg_tmp_172_reg_5914_pp6_it1[12];
end
if ((ap_ST_pp6_stg0_fsm_30 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_172_reg_5914_pp6_it3[0] <= ap_reg_ppstg_tmp_172_reg_5914_pp6_it2[0];
ap_reg_ppstg_tmp_172_reg_5914_pp6_it3[1] <= ap_reg_ppstg_tmp_172_reg_5914_pp6_it2[1];
ap_reg_ppstg_tmp_172_reg_5914_pp6_it3[2] <= ap_reg_ppstg_tmp_172_reg_5914_pp6_it2[2];
ap_reg_ppstg_tmp_172_reg_5914_pp6_it3[3] <= ap_reg_ppstg_tmp_172_reg_5914_pp6_it2[3];
ap_reg_ppstg_tmp_172_reg_5914_pp6_it3[4] <= ap_reg_ppstg_tmp_172_reg_5914_pp6_it2[4];
ap_reg_ppstg_tmp_172_reg_5914_pp6_it3[5] <= ap_reg_ppstg_tmp_172_reg_5914_pp6_it2[5];
ap_reg_ppstg_tmp_172_reg_5914_pp6_it3[6] <= ap_reg_ppstg_tmp_172_reg_5914_pp6_it2[6];
ap_reg_ppstg_tmp_172_reg_5914_pp6_it3[7] <= ap_reg_ppstg_tmp_172_reg_5914_pp6_it2[7];
ap_reg_ppstg_tmp_172_reg_5914_pp6_it3[8] <= ap_reg_ppstg_tmp_172_reg_5914_pp6_it2[8];
ap_reg_ppstg_tmp_172_reg_5914_pp6_it3[9] <= ap_reg_ppstg_tmp_172_reg_5914_pp6_it2[9];
ap_reg_ppstg_tmp_172_reg_5914_pp6_it3[10] <= ap_reg_ppstg_tmp_172_reg_5914_pp6_it2[10];
ap_reg_ppstg_tmp_172_reg_5914_pp6_it3[11] <= ap_reg_ppstg_tmp_172_reg_5914_pp6_it2[11];
ap_reg_ppstg_tmp_172_reg_5914_pp6_it3[12] <= ap_reg_ppstg_tmp_172_reg_5914_pp6_it2[12];
end
if ((ap_ST_pp6_stg0_fsm_30 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_172_reg_5914_pp6_it4[0] <= ap_reg_ppstg_tmp_172_reg_5914_pp6_it3[0];
ap_reg_ppstg_tmp_172_reg_5914_pp6_it4[1] <= ap_reg_ppstg_tmp_172_reg_5914_pp6_it3[1];
ap_reg_ppstg_tmp_172_reg_5914_pp6_it4[2] <= ap_reg_ppstg_tmp_172_reg_5914_pp6_it3[2];
ap_reg_ppstg_tmp_172_reg_5914_pp6_it4[3] <= ap_reg_ppstg_tmp_172_reg_5914_pp6_it3[3];
ap_reg_ppstg_tmp_172_reg_5914_pp6_it4[4] <= ap_reg_ppstg_tmp_172_reg_5914_pp6_it3[4];
ap_reg_ppstg_tmp_172_reg_5914_pp6_it4[5] <= ap_reg_ppstg_tmp_172_reg_5914_pp6_it3[5];
ap_reg_ppstg_tmp_172_reg_5914_pp6_it4[6] <= ap_reg_ppstg_tmp_172_reg_5914_pp6_it3[6];
ap_reg_ppstg_tmp_172_reg_5914_pp6_it4[7] <= ap_reg_ppstg_tmp_172_reg_5914_pp6_it3[7];
ap_reg_ppstg_tmp_172_reg_5914_pp6_it4[8] <= ap_reg_ppstg_tmp_172_reg_5914_pp6_it3[8];
ap_reg_ppstg_tmp_172_reg_5914_pp6_it4[9] <= ap_reg_ppstg_tmp_172_reg_5914_pp6_it3[9];
ap_reg_ppstg_tmp_172_reg_5914_pp6_it4[10] <= ap_reg_ppstg_tmp_172_reg_5914_pp6_it3[10];
ap_reg_ppstg_tmp_172_reg_5914_pp6_it4[11] <= ap_reg_ppstg_tmp_172_reg_5914_pp6_it3[11];
ap_reg_ppstg_tmp_172_reg_5914_pp6_it4[12] <= ap_reg_ppstg_tmp_172_reg_5914_pp6_it3[12];
end
if ((ap_ST_pp6_stg0_fsm_30 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_172_reg_5914_pp6_it5[0] <= ap_reg_ppstg_tmp_172_reg_5914_pp6_it4[0];
ap_reg_ppstg_tmp_172_reg_5914_pp6_it5[1] <= ap_reg_ppstg_tmp_172_reg_5914_pp6_it4[1];
ap_reg_ppstg_tmp_172_reg_5914_pp6_it5[2] <= ap_reg_ppstg_tmp_172_reg_5914_pp6_it4[2];
ap_reg_ppstg_tmp_172_reg_5914_pp6_it5[3] <= ap_reg_ppstg_tmp_172_reg_5914_pp6_it4[3];
ap_reg_ppstg_tmp_172_reg_5914_pp6_it5[4] <= ap_reg_ppstg_tmp_172_reg_5914_pp6_it4[4];
ap_reg_ppstg_tmp_172_reg_5914_pp6_it5[5] <= ap_reg_ppstg_tmp_172_reg_5914_pp6_it4[5];
ap_reg_ppstg_tmp_172_reg_5914_pp6_it5[6] <= ap_reg_ppstg_tmp_172_reg_5914_pp6_it4[6];
ap_reg_ppstg_tmp_172_reg_5914_pp6_it5[7] <= ap_reg_ppstg_tmp_172_reg_5914_pp6_it4[7];
ap_reg_ppstg_tmp_172_reg_5914_pp6_it5[8] <= ap_reg_ppstg_tmp_172_reg_5914_pp6_it4[8];
ap_reg_ppstg_tmp_172_reg_5914_pp6_it5[9] <= ap_reg_ppstg_tmp_172_reg_5914_pp6_it4[9];
ap_reg_ppstg_tmp_172_reg_5914_pp6_it5[10] <= ap_reg_ppstg_tmp_172_reg_5914_pp6_it4[10];
ap_reg_ppstg_tmp_172_reg_5914_pp6_it5[11] <= ap_reg_ppstg_tmp_172_reg_5914_pp6_it4[11];
ap_reg_ppstg_tmp_172_reg_5914_pp6_it5[12] <= ap_reg_ppstg_tmp_172_reg_5914_pp6_it4[12];
end
if ((ap_ST_pp7_stg0_fsm_31 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_174_reg_5967_pp7_it1 <= tmp_174_reg_5967;
end
if ((ap_ST_pp7_stg1_fsm_32 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_178_reg_5997_pp7_it1[1] <= tmp_178_reg_5997[1];
ap_reg_ppstg_tmp_178_reg_5997_pp7_it1[2] <= tmp_178_reg_5997[2];
ap_reg_ppstg_tmp_178_reg_5997_pp7_it1[3] <= tmp_178_reg_5997[3];
ap_reg_ppstg_tmp_178_reg_5997_pp7_it1[4] <= tmp_178_reg_5997[4];
ap_reg_ppstg_tmp_178_reg_5997_pp7_it1[5] <= tmp_178_reg_5997[5];
ap_reg_ppstg_tmp_178_reg_5997_pp7_it1[6] <= tmp_178_reg_5997[6];
ap_reg_ppstg_tmp_178_reg_5997_pp7_it1[7] <= tmp_178_reg_5997[7];
ap_reg_ppstg_tmp_178_reg_5997_pp7_it1[8] <= tmp_178_reg_5997[8];
ap_reg_ppstg_tmp_178_reg_5997_pp7_it1[9] <= tmp_178_reg_5997[9];
ap_reg_ppstg_tmp_178_reg_5997_pp7_it1[10] <= tmp_178_reg_5997[10];
ap_reg_ppstg_tmp_178_reg_5997_pp7_it1[11] <= tmp_178_reg_5997[11];
ap_reg_ppstg_tmp_178_reg_5997_pp7_it1[12] <= tmp_178_reg_5997[12];
ap_reg_ppstg_tmp_178_reg_5997_pp7_it1[13] <= tmp_178_reg_5997[13];
ap_reg_ppstg_tmp_178_reg_5997_pp7_it1[14] <= tmp_178_reg_5997[14];
ap_reg_ppstg_tmp_178_reg_5997_pp7_it1[15] <= tmp_178_reg_5997[15];
ap_reg_ppstg_tmp_178_reg_5997_pp7_it1[16] <= tmp_178_reg_5997[16];
ap_reg_ppstg_tmp_178_reg_5997_pp7_it1[17] <= tmp_178_reg_5997[17];
ap_reg_ppstg_tmp_178_reg_5997_pp7_it1[18] <= tmp_178_reg_5997[18];
ap_reg_ppstg_tmp_178_reg_5997_pp7_it1[19] <= tmp_178_reg_5997[19];
ap_reg_ppstg_tmp_178_reg_5997_pp7_it1[20] <= tmp_178_reg_5997[20];
ap_reg_ppstg_tmp_178_reg_5997_pp7_it1[21] <= tmp_178_reg_5997[21];
ap_reg_ppstg_tmp_178_reg_5997_pp7_it1[22] <= tmp_178_reg_5997[22];
ap_reg_ppstg_tmp_178_reg_5997_pp7_it1[23] <= tmp_178_reg_5997[23];
ap_reg_ppstg_tmp_178_reg_5997_pp7_it1[24] <= tmp_178_reg_5997[24];
ap_reg_ppstg_tmp_178_reg_5997_pp7_it1[25] <= tmp_178_reg_5997[25];
ap_reg_ppstg_tmp_178_reg_5997_pp7_it1[26] <= tmp_178_reg_5997[26];
ap_reg_ppstg_tmp_178_reg_5997_pp7_it1[27] <= tmp_178_reg_5997[27];
ap_reg_ppstg_tmp_178_reg_5997_pp7_it1[28] <= tmp_178_reg_5997[28];
ap_reg_ppstg_tmp_178_reg_5997_pp7_it1[29] <= tmp_178_reg_5997[29];
ap_reg_ppstg_tmp_178_reg_5997_pp7_it1[30] <= tmp_178_reg_5997[30];
ap_reg_ppstg_tmp_178_reg_5997_pp7_it1[31] <= tmp_178_reg_5997[31];
ap_reg_ppstg_tmp_178_reg_5997_pp7_it1[32] <= tmp_178_reg_5997[32];
ap_reg_ppstg_tmp_178_reg_5997_pp7_it1[33] <= tmp_178_reg_5997[33];
ap_reg_ppstg_tmp_178_reg_5997_pp7_it1[34] <= tmp_178_reg_5997[34];
ap_reg_ppstg_tmp_178_reg_5997_pp7_it1[35] <= tmp_178_reg_5997[35];
ap_reg_ppstg_tmp_178_reg_5997_pp7_it1[36] <= tmp_178_reg_5997[36];
ap_reg_ppstg_tmp_178_reg_5997_pp7_it1[37] <= tmp_178_reg_5997[37];
ap_reg_ppstg_tmp_178_reg_5997_pp7_it1[38] <= tmp_178_reg_5997[38];
ap_reg_ppstg_tmp_178_reg_5997_pp7_it1[39] <= tmp_178_reg_5997[39];
ap_reg_ppstg_tmp_178_reg_5997_pp7_it1[40] <= tmp_178_reg_5997[40];
ap_reg_ppstg_tmp_178_reg_5997_pp7_it1[41] <= tmp_178_reg_5997[41];
ap_reg_ppstg_tmp_178_reg_5997_pp7_it1[42] <= tmp_178_reg_5997[42];
ap_reg_ppstg_tmp_178_reg_5997_pp7_it1[43] <= tmp_178_reg_5997[43];
ap_reg_ppstg_tmp_178_reg_5997_pp7_it1[44] <= tmp_178_reg_5997[44];
ap_reg_ppstg_tmp_178_reg_5997_pp7_it1[45] <= tmp_178_reg_5997[45];
ap_reg_ppstg_tmp_178_reg_5997_pp7_it1[46] <= tmp_178_reg_5997[46];
ap_reg_ppstg_tmp_178_reg_5997_pp7_it1[47] <= tmp_178_reg_5997[47];
ap_reg_ppstg_tmp_178_reg_5997_pp7_it1[48] <= tmp_178_reg_5997[48];
ap_reg_ppstg_tmp_178_reg_5997_pp7_it1[49] <= tmp_178_reg_5997[49];
ap_reg_ppstg_tmp_178_reg_5997_pp7_it1[50] <= tmp_178_reg_5997[50];
ap_reg_ppstg_tmp_178_reg_5997_pp7_it1[51] <= tmp_178_reg_5997[51];
ap_reg_ppstg_tmp_178_reg_5997_pp7_it1[52] <= tmp_178_reg_5997[52];
ap_reg_ppstg_tmp_178_reg_5997_pp7_it1[53] <= tmp_178_reg_5997[53];
ap_reg_ppstg_tmp_178_reg_5997_pp7_it1[54] <= tmp_178_reg_5997[54];
ap_reg_ppstg_tmp_178_reg_5997_pp7_it1[55] <= tmp_178_reg_5997[55];
ap_reg_ppstg_tmp_178_reg_5997_pp7_it1[56] <= tmp_178_reg_5997[56];
ap_reg_ppstg_tmp_178_reg_5997_pp7_it1[57] <= tmp_178_reg_5997[57];
ap_reg_ppstg_tmp_178_reg_5997_pp7_it1[58] <= tmp_178_reg_5997[58];
ap_reg_ppstg_tmp_178_reg_5997_pp7_it1[59] <= tmp_178_reg_5997[59];
ap_reg_ppstg_tmp_178_reg_5997_pp7_it1[60] <= tmp_178_reg_5997[60];
ap_reg_ppstg_tmp_178_reg_5997_pp7_it1[61] <= tmp_178_reg_5997[61];
ap_reg_ppstg_tmp_178_reg_5997_pp7_it1[62] <= tmp_178_reg_5997[62];
ap_reg_ppstg_tmp_178_reg_5997_pp7_it1[63] <= tmp_178_reg_5997[63];
end
if ((ap_ST_pp7_stg1_fsm_32 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_182_reg_6017_pp7_it1 <= tmp_182_reg_6017;
end
if ((ap_ST_pp7_stg2_fsm_33 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_186_reg_6032_pp7_it1[2] <= tmp_186_reg_6032[2];
ap_reg_ppstg_tmp_186_reg_6032_pp7_it1[3] <= tmp_186_reg_6032[3];
ap_reg_ppstg_tmp_186_reg_6032_pp7_it1[4] <= tmp_186_reg_6032[4];
ap_reg_ppstg_tmp_186_reg_6032_pp7_it1[5] <= tmp_186_reg_6032[5];
ap_reg_ppstg_tmp_186_reg_6032_pp7_it1[6] <= tmp_186_reg_6032[6];
ap_reg_ppstg_tmp_186_reg_6032_pp7_it1[7] <= tmp_186_reg_6032[7];
ap_reg_ppstg_tmp_186_reg_6032_pp7_it1[8] <= tmp_186_reg_6032[8];
ap_reg_ppstg_tmp_186_reg_6032_pp7_it1[9] <= tmp_186_reg_6032[9];
ap_reg_ppstg_tmp_186_reg_6032_pp7_it1[10] <= tmp_186_reg_6032[10];
ap_reg_ppstg_tmp_186_reg_6032_pp7_it1[11] <= tmp_186_reg_6032[11];
ap_reg_ppstg_tmp_186_reg_6032_pp7_it1[12] <= tmp_186_reg_6032[12];
ap_reg_ppstg_tmp_186_reg_6032_pp7_it1[13] <= tmp_186_reg_6032[13];
ap_reg_ppstg_tmp_186_reg_6032_pp7_it1[14] <= tmp_186_reg_6032[14];
ap_reg_ppstg_tmp_186_reg_6032_pp7_it1[15] <= tmp_186_reg_6032[15];
ap_reg_ppstg_tmp_186_reg_6032_pp7_it1[16] <= tmp_186_reg_6032[16];
ap_reg_ppstg_tmp_186_reg_6032_pp7_it1[17] <= tmp_186_reg_6032[17];
ap_reg_ppstg_tmp_186_reg_6032_pp7_it1[18] <= tmp_186_reg_6032[18];
ap_reg_ppstg_tmp_186_reg_6032_pp7_it1[19] <= tmp_186_reg_6032[19];
ap_reg_ppstg_tmp_186_reg_6032_pp7_it1[20] <= tmp_186_reg_6032[20];
ap_reg_ppstg_tmp_186_reg_6032_pp7_it1[21] <= tmp_186_reg_6032[21];
ap_reg_ppstg_tmp_186_reg_6032_pp7_it1[22] <= tmp_186_reg_6032[22];
ap_reg_ppstg_tmp_186_reg_6032_pp7_it1[23] <= tmp_186_reg_6032[23];
ap_reg_ppstg_tmp_186_reg_6032_pp7_it1[24] <= tmp_186_reg_6032[24];
ap_reg_ppstg_tmp_186_reg_6032_pp7_it1[25] <= tmp_186_reg_6032[25];
ap_reg_ppstg_tmp_186_reg_6032_pp7_it1[26] <= tmp_186_reg_6032[26];
ap_reg_ppstg_tmp_186_reg_6032_pp7_it1[27] <= tmp_186_reg_6032[27];
ap_reg_ppstg_tmp_186_reg_6032_pp7_it1[28] <= tmp_186_reg_6032[28];
ap_reg_ppstg_tmp_186_reg_6032_pp7_it1[29] <= tmp_186_reg_6032[29];
ap_reg_ppstg_tmp_186_reg_6032_pp7_it1[30] <= tmp_186_reg_6032[30];
ap_reg_ppstg_tmp_186_reg_6032_pp7_it1[31] <= tmp_186_reg_6032[31];
ap_reg_ppstg_tmp_186_reg_6032_pp7_it1[32] <= tmp_186_reg_6032[32];
ap_reg_ppstg_tmp_186_reg_6032_pp7_it1[33] <= tmp_186_reg_6032[33];
ap_reg_ppstg_tmp_186_reg_6032_pp7_it1[34] <= tmp_186_reg_6032[34];
ap_reg_ppstg_tmp_186_reg_6032_pp7_it1[35] <= tmp_186_reg_6032[35];
ap_reg_ppstg_tmp_186_reg_6032_pp7_it1[36] <= tmp_186_reg_6032[36];
ap_reg_ppstg_tmp_186_reg_6032_pp7_it1[37] <= tmp_186_reg_6032[37];
ap_reg_ppstg_tmp_186_reg_6032_pp7_it1[38] <= tmp_186_reg_6032[38];
ap_reg_ppstg_tmp_186_reg_6032_pp7_it1[39] <= tmp_186_reg_6032[39];
ap_reg_ppstg_tmp_186_reg_6032_pp7_it1[40] <= tmp_186_reg_6032[40];
ap_reg_ppstg_tmp_186_reg_6032_pp7_it1[41] <= tmp_186_reg_6032[41];
ap_reg_ppstg_tmp_186_reg_6032_pp7_it1[42] <= tmp_186_reg_6032[42];
ap_reg_ppstg_tmp_186_reg_6032_pp7_it1[43] <= tmp_186_reg_6032[43];
ap_reg_ppstg_tmp_186_reg_6032_pp7_it1[44] <= tmp_186_reg_6032[44];
ap_reg_ppstg_tmp_186_reg_6032_pp7_it1[45] <= tmp_186_reg_6032[45];
ap_reg_ppstg_tmp_186_reg_6032_pp7_it1[46] <= tmp_186_reg_6032[46];
ap_reg_ppstg_tmp_186_reg_6032_pp7_it1[47] <= tmp_186_reg_6032[47];
ap_reg_ppstg_tmp_186_reg_6032_pp7_it1[48] <= tmp_186_reg_6032[48];
ap_reg_ppstg_tmp_186_reg_6032_pp7_it1[49] <= tmp_186_reg_6032[49];
ap_reg_ppstg_tmp_186_reg_6032_pp7_it1[50] <= tmp_186_reg_6032[50];
ap_reg_ppstg_tmp_186_reg_6032_pp7_it1[51] <= tmp_186_reg_6032[51];
ap_reg_ppstg_tmp_186_reg_6032_pp7_it1[52] <= tmp_186_reg_6032[52];
ap_reg_ppstg_tmp_186_reg_6032_pp7_it1[53] <= tmp_186_reg_6032[53];
ap_reg_ppstg_tmp_186_reg_6032_pp7_it1[54] <= tmp_186_reg_6032[54];
ap_reg_ppstg_tmp_186_reg_6032_pp7_it1[55] <= tmp_186_reg_6032[55];
ap_reg_ppstg_tmp_186_reg_6032_pp7_it1[56] <= tmp_186_reg_6032[56];
ap_reg_ppstg_tmp_186_reg_6032_pp7_it1[57] <= tmp_186_reg_6032[57];
ap_reg_ppstg_tmp_186_reg_6032_pp7_it1[58] <= tmp_186_reg_6032[58];
ap_reg_ppstg_tmp_186_reg_6032_pp7_it1[59] <= tmp_186_reg_6032[59];
ap_reg_ppstg_tmp_186_reg_6032_pp7_it1[60] <= tmp_186_reg_6032[60];
ap_reg_ppstg_tmp_186_reg_6032_pp7_it1[61] <= tmp_186_reg_6032[61];
ap_reg_ppstg_tmp_186_reg_6032_pp7_it1[62] <= tmp_186_reg_6032[62];
ap_reg_ppstg_tmp_186_reg_6032_pp7_it1[63] <= tmp_186_reg_6032[63];
end
if ((ap_ST_pp7_stg2_fsm_33 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_190_reg_6052_pp7_it1 <= tmp_190_reg_6052;
end
if ((ap_ST_pp7_stg3_fsm_34 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[1] <= tmp_192_reg_6067[1];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[2] <= tmp_192_reg_6067[2];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[3] <= tmp_192_reg_6067[3];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[4] <= tmp_192_reg_6067[4];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[5] <= tmp_192_reg_6067[5];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[6] <= tmp_192_reg_6067[6];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[7] <= tmp_192_reg_6067[7];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[8] <= tmp_192_reg_6067[8];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[9] <= tmp_192_reg_6067[9];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[10] <= tmp_192_reg_6067[10];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[11] <= tmp_192_reg_6067[11];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[12] <= tmp_192_reg_6067[12];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[13] <= tmp_192_reg_6067[13];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[14] <= tmp_192_reg_6067[14];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[15] <= tmp_192_reg_6067[15];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[16] <= tmp_192_reg_6067[16];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[17] <= tmp_192_reg_6067[17];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[18] <= tmp_192_reg_6067[18];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[19] <= tmp_192_reg_6067[19];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[20] <= tmp_192_reg_6067[20];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[21] <= tmp_192_reg_6067[21];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[22] <= tmp_192_reg_6067[22];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[23] <= tmp_192_reg_6067[23];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[24] <= tmp_192_reg_6067[24];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[25] <= tmp_192_reg_6067[25];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[26] <= tmp_192_reg_6067[26];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[27] <= tmp_192_reg_6067[27];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[28] <= tmp_192_reg_6067[28];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[29] <= tmp_192_reg_6067[29];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[30] <= tmp_192_reg_6067[30];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[31] <= tmp_192_reg_6067[31];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[32] <= tmp_192_reg_6067[32];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[33] <= tmp_192_reg_6067[33];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[34] <= tmp_192_reg_6067[34];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[35] <= tmp_192_reg_6067[35];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[36] <= tmp_192_reg_6067[36];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[37] <= tmp_192_reg_6067[37];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[38] <= tmp_192_reg_6067[38];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[39] <= tmp_192_reg_6067[39];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[40] <= tmp_192_reg_6067[40];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[41] <= tmp_192_reg_6067[41];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[42] <= tmp_192_reg_6067[42];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[43] <= tmp_192_reg_6067[43];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[44] <= tmp_192_reg_6067[44];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[45] <= tmp_192_reg_6067[45];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[46] <= tmp_192_reg_6067[46];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[47] <= tmp_192_reg_6067[47];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[48] <= tmp_192_reg_6067[48];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[49] <= tmp_192_reg_6067[49];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[50] <= tmp_192_reg_6067[50];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[51] <= tmp_192_reg_6067[51];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[52] <= tmp_192_reg_6067[52];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[53] <= tmp_192_reg_6067[53];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[54] <= tmp_192_reg_6067[54];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[55] <= tmp_192_reg_6067[55];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[56] <= tmp_192_reg_6067[56];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[57] <= tmp_192_reg_6067[57];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[58] <= tmp_192_reg_6067[58];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[59] <= tmp_192_reg_6067[59];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[60] <= tmp_192_reg_6067[60];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[61] <= tmp_192_reg_6067[61];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[62] <= tmp_192_reg_6067[62];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[63] <= tmp_192_reg_6067[63];
end
if ((ap_ST_pp7_stg3_fsm_34 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_192_reg_6067_pp7_it2[1] <= ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[1];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it2[2] <= ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[2];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it2[3] <= ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[3];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it2[4] <= ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[4];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it2[5] <= ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[5];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it2[6] <= ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[6];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it2[7] <= ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[7];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it2[8] <= ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[8];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it2[9] <= ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[9];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it2[10] <= ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[10];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it2[11] <= ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[11];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it2[12] <= ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[12];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it2[13] <= ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[13];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it2[14] <= ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[14];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it2[15] <= ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[15];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it2[16] <= ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[16];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it2[17] <= ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[17];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it2[18] <= ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[18];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it2[19] <= ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[19];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it2[20] <= ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[20];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it2[21] <= ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[21];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it2[22] <= ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[22];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it2[23] <= ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[23];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it2[24] <= ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[24];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it2[25] <= ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[25];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it2[26] <= ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[26];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it2[27] <= ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[27];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it2[28] <= ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[28];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it2[29] <= ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[29];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it2[30] <= ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[30];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it2[31] <= ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[31];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it2[32] <= ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[32];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it2[33] <= ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[33];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it2[34] <= ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[34];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it2[35] <= ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[35];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it2[36] <= ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[36];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it2[37] <= ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[37];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it2[38] <= ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[38];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it2[39] <= ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[39];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it2[40] <= ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[40];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it2[41] <= ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[41];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it2[42] <= ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[42];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it2[43] <= ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[43];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it2[44] <= ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[44];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it2[45] <= ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[45];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it2[46] <= ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[46];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it2[47] <= ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[47];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it2[48] <= ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[48];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it2[49] <= ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[49];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it2[50] <= ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[50];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it2[51] <= ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[51];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it2[52] <= ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[52];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it2[53] <= ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[53];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it2[54] <= ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[54];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it2[55] <= ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[55];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it2[56] <= ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[56];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it2[57] <= ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[57];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it2[58] <= ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[58];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it2[59] <= ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[59];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it2[60] <= ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[60];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it2[61] <= ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[61];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it2[62] <= ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[62];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it2[63] <= ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[63];
end
if ((ap_ST_pp7_stg3_fsm_34 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_194_reg_6107_pp7_it2 <= tmp_194_reg_6107;
end
if ((ap_ST_pp7_stg4_fsm_35 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_197_reg_6122_pp7_it2[3] <= tmp_197_reg_6122[3];
ap_reg_ppstg_tmp_197_reg_6122_pp7_it2[4] <= tmp_197_reg_6122[4];
ap_reg_ppstg_tmp_197_reg_6122_pp7_it2[5] <= tmp_197_reg_6122[5];
ap_reg_ppstg_tmp_197_reg_6122_pp7_it2[6] <= tmp_197_reg_6122[6];
ap_reg_ppstg_tmp_197_reg_6122_pp7_it2[7] <= tmp_197_reg_6122[7];
ap_reg_ppstg_tmp_197_reg_6122_pp7_it2[8] <= tmp_197_reg_6122[8];
ap_reg_ppstg_tmp_197_reg_6122_pp7_it2[9] <= tmp_197_reg_6122[9];
ap_reg_ppstg_tmp_197_reg_6122_pp7_it2[10] <= tmp_197_reg_6122[10];
ap_reg_ppstg_tmp_197_reg_6122_pp7_it2[11] <= tmp_197_reg_6122[11];
ap_reg_ppstg_tmp_197_reg_6122_pp7_it2[12] <= tmp_197_reg_6122[12];
ap_reg_ppstg_tmp_197_reg_6122_pp7_it2[13] <= tmp_197_reg_6122[13];
ap_reg_ppstg_tmp_197_reg_6122_pp7_it2[14] <= tmp_197_reg_6122[14];
ap_reg_ppstg_tmp_197_reg_6122_pp7_it2[15] <= tmp_197_reg_6122[15];
ap_reg_ppstg_tmp_197_reg_6122_pp7_it2[16] <= tmp_197_reg_6122[16];
ap_reg_ppstg_tmp_197_reg_6122_pp7_it2[17] <= tmp_197_reg_6122[17];
ap_reg_ppstg_tmp_197_reg_6122_pp7_it2[18] <= tmp_197_reg_6122[18];
ap_reg_ppstg_tmp_197_reg_6122_pp7_it2[19] <= tmp_197_reg_6122[19];
ap_reg_ppstg_tmp_197_reg_6122_pp7_it2[20] <= tmp_197_reg_6122[20];
ap_reg_ppstg_tmp_197_reg_6122_pp7_it2[21] <= tmp_197_reg_6122[21];
ap_reg_ppstg_tmp_197_reg_6122_pp7_it2[22] <= tmp_197_reg_6122[22];
ap_reg_ppstg_tmp_197_reg_6122_pp7_it2[23] <= tmp_197_reg_6122[23];
ap_reg_ppstg_tmp_197_reg_6122_pp7_it2[24] <= tmp_197_reg_6122[24];
ap_reg_ppstg_tmp_197_reg_6122_pp7_it2[25] <= tmp_197_reg_6122[25];
ap_reg_ppstg_tmp_197_reg_6122_pp7_it2[26] <= tmp_197_reg_6122[26];
ap_reg_ppstg_tmp_197_reg_6122_pp7_it2[27] <= tmp_197_reg_6122[27];
ap_reg_ppstg_tmp_197_reg_6122_pp7_it2[28] <= tmp_197_reg_6122[28];
ap_reg_ppstg_tmp_197_reg_6122_pp7_it2[29] <= tmp_197_reg_6122[29];
ap_reg_ppstg_tmp_197_reg_6122_pp7_it2[30] <= tmp_197_reg_6122[30];
ap_reg_ppstg_tmp_197_reg_6122_pp7_it2[31] <= tmp_197_reg_6122[31];
ap_reg_ppstg_tmp_197_reg_6122_pp7_it2[32] <= tmp_197_reg_6122[32];
ap_reg_ppstg_tmp_197_reg_6122_pp7_it2[33] <= tmp_197_reg_6122[33];
ap_reg_ppstg_tmp_197_reg_6122_pp7_it2[34] <= tmp_197_reg_6122[34];
ap_reg_ppstg_tmp_197_reg_6122_pp7_it2[35] <= tmp_197_reg_6122[35];
ap_reg_ppstg_tmp_197_reg_6122_pp7_it2[36] <= tmp_197_reg_6122[36];
ap_reg_ppstg_tmp_197_reg_6122_pp7_it2[37] <= tmp_197_reg_6122[37];
ap_reg_ppstg_tmp_197_reg_6122_pp7_it2[38] <= tmp_197_reg_6122[38];
ap_reg_ppstg_tmp_197_reg_6122_pp7_it2[39] <= tmp_197_reg_6122[39];
ap_reg_ppstg_tmp_197_reg_6122_pp7_it2[40] <= tmp_197_reg_6122[40];
ap_reg_ppstg_tmp_197_reg_6122_pp7_it2[41] <= tmp_197_reg_6122[41];
ap_reg_ppstg_tmp_197_reg_6122_pp7_it2[42] <= tmp_197_reg_6122[42];
ap_reg_ppstg_tmp_197_reg_6122_pp7_it2[43] <= tmp_197_reg_6122[43];
ap_reg_ppstg_tmp_197_reg_6122_pp7_it2[44] <= tmp_197_reg_6122[44];
ap_reg_ppstg_tmp_197_reg_6122_pp7_it2[45] <= tmp_197_reg_6122[45];
ap_reg_ppstg_tmp_197_reg_6122_pp7_it2[46] <= tmp_197_reg_6122[46];
ap_reg_ppstg_tmp_197_reg_6122_pp7_it2[47] <= tmp_197_reg_6122[47];
ap_reg_ppstg_tmp_197_reg_6122_pp7_it2[48] <= tmp_197_reg_6122[48];
ap_reg_ppstg_tmp_197_reg_6122_pp7_it2[49] <= tmp_197_reg_6122[49];
ap_reg_ppstg_tmp_197_reg_6122_pp7_it2[50] <= tmp_197_reg_6122[50];
ap_reg_ppstg_tmp_197_reg_6122_pp7_it2[51] <= tmp_197_reg_6122[51];
ap_reg_ppstg_tmp_197_reg_6122_pp7_it2[52] <= tmp_197_reg_6122[52];
ap_reg_ppstg_tmp_197_reg_6122_pp7_it2[53] <= tmp_197_reg_6122[53];
ap_reg_ppstg_tmp_197_reg_6122_pp7_it2[54] <= tmp_197_reg_6122[54];
ap_reg_ppstg_tmp_197_reg_6122_pp7_it2[55] <= tmp_197_reg_6122[55];
ap_reg_ppstg_tmp_197_reg_6122_pp7_it2[56] <= tmp_197_reg_6122[56];
ap_reg_ppstg_tmp_197_reg_6122_pp7_it2[57] <= tmp_197_reg_6122[57];
ap_reg_ppstg_tmp_197_reg_6122_pp7_it2[58] <= tmp_197_reg_6122[58];
ap_reg_ppstg_tmp_197_reg_6122_pp7_it2[59] <= tmp_197_reg_6122[59];
ap_reg_ppstg_tmp_197_reg_6122_pp7_it2[60] <= tmp_197_reg_6122[60];
ap_reg_ppstg_tmp_197_reg_6122_pp7_it2[61] <= tmp_197_reg_6122[61];
ap_reg_ppstg_tmp_197_reg_6122_pp7_it2[62] <= tmp_197_reg_6122[62];
ap_reg_ppstg_tmp_197_reg_6122_pp7_it2[63] <= tmp_197_reg_6122[63];
end
if ((ap_ST_pp1_stg1_fsm_5 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_20_reg_5287_pp1_it1[0] <= tmp_20_reg_5287[0];
ap_reg_ppstg_tmp_20_reg_5287_pp1_it1[1] <= tmp_20_reg_5287[1];
ap_reg_ppstg_tmp_20_reg_5287_pp1_it1[2] <= tmp_20_reg_5287[2];
ap_reg_ppstg_tmp_20_reg_5287_pp1_it1[3] <= tmp_20_reg_5287[3];
ap_reg_ppstg_tmp_20_reg_5287_pp1_it1[4] <= tmp_20_reg_5287[4];
ap_reg_ppstg_tmp_20_reg_5287_pp1_it1[5] <= tmp_20_reg_5287[5];
ap_reg_ppstg_tmp_20_reg_5287_pp1_it1[6] <= tmp_20_reg_5287[6];
ap_reg_ppstg_tmp_20_reg_5287_pp1_it1[7] <= tmp_20_reg_5287[7];
ap_reg_ppstg_tmp_20_reg_5287_pp1_it1[8] <= tmp_20_reg_5287[8];
ap_reg_ppstg_tmp_20_reg_5287_pp1_it1[9] <= tmp_20_reg_5287[9];
ap_reg_ppstg_tmp_20_reg_5287_pp1_it1[10] <= tmp_20_reg_5287[10];
ap_reg_ppstg_tmp_20_reg_5287_pp1_it1[11] <= tmp_20_reg_5287[11];
ap_reg_ppstg_tmp_20_reg_5287_pp1_it1[12] <= tmp_20_reg_5287[12];
ap_reg_ppstg_tmp_20_reg_5287_pp1_it1[13] <= tmp_20_reg_5287[13];
end
if ((ap_ST_pp1_stg2_fsm_6 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_28_reg_5332_pp1_it1[0] <= tmp_28_reg_5332[0];
ap_reg_ppstg_tmp_28_reg_5332_pp1_it1[1] <= tmp_28_reg_5332[1];
ap_reg_ppstg_tmp_28_reg_5332_pp1_it1[2] <= tmp_28_reg_5332[2];
ap_reg_ppstg_tmp_28_reg_5332_pp1_it1[3] <= tmp_28_reg_5332[3];
ap_reg_ppstg_tmp_28_reg_5332_pp1_it1[4] <= tmp_28_reg_5332[4];
ap_reg_ppstg_tmp_28_reg_5332_pp1_it1[5] <= tmp_28_reg_5332[5];
ap_reg_ppstg_tmp_28_reg_5332_pp1_it1[6] <= tmp_28_reg_5332[6];
ap_reg_ppstg_tmp_28_reg_5332_pp1_it1[7] <= tmp_28_reg_5332[7];
ap_reg_ppstg_tmp_28_reg_5332_pp1_it1[8] <= tmp_28_reg_5332[8];
ap_reg_ppstg_tmp_28_reg_5332_pp1_it1[9] <= tmp_28_reg_5332[9];
ap_reg_ppstg_tmp_28_reg_5332_pp1_it1[10] <= tmp_28_reg_5332[10];
ap_reg_ppstg_tmp_28_reg_5332_pp1_it1[11] <= tmp_28_reg_5332[11];
ap_reg_ppstg_tmp_28_reg_5332_pp1_it1[12] <= tmp_28_reg_5332[12];
ap_reg_ppstg_tmp_28_reg_5332_pp1_it1[13] <= tmp_28_reg_5332[13];
end
if ((ap_ST_pp1_stg2_fsm_6 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_36_reg_5347_pp1_it1[0] <= tmp_36_reg_5347[0];
ap_reg_ppstg_tmp_36_reg_5347_pp1_it1[1] <= tmp_36_reg_5347[1];
ap_reg_ppstg_tmp_36_reg_5347_pp1_it1[2] <= tmp_36_reg_5347[2];
ap_reg_ppstg_tmp_36_reg_5347_pp1_it1[3] <= tmp_36_reg_5347[3];
ap_reg_ppstg_tmp_36_reg_5347_pp1_it1[4] <= tmp_36_reg_5347[4];
ap_reg_ppstg_tmp_36_reg_5347_pp1_it1[5] <= tmp_36_reg_5347[5];
ap_reg_ppstg_tmp_36_reg_5347_pp1_it1[6] <= tmp_36_reg_5347[6];
ap_reg_ppstg_tmp_36_reg_5347_pp1_it1[7] <= tmp_36_reg_5347[7];
ap_reg_ppstg_tmp_36_reg_5347_pp1_it1[8] <= tmp_36_reg_5347[8];
ap_reg_ppstg_tmp_36_reg_5347_pp1_it1[9] <= tmp_36_reg_5347[9];
ap_reg_ppstg_tmp_36_reg_5347_pp1_it1[10] <= tmp_36_reg_5347[10];
ap_reg_ppstg_tmp_36_reg_5347_pp1_it1[11] <= tmp_36_reg_5347[11];
ap_reg_ppstg_tmp_36_reg_5347_pp1_it1[12] <= tmp_36_reg_5347[12];
ap_reg_ppstg_tmp_36_reg_5347_pp1_it1[13] <= tmp_36_reg_5347[13];
end
if ((ap_ST_pp1_stg3_fsm_7 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_44_reg_5367_pp1_it1[0] <= tmp_44_reg_5367[0];
ap_reg_ppstg_tmp_44_reg_5367_pp1_it1[1] <= tmp_44_reg_5367[1];
ap_reg_ppstg_tmp_44_reg_5367_pp1_it1[2] <= tmp_44_reg_5367[2];
ap_reg_ppstg_tmp_44_reg_5367_pp1_it1[3] <= tmp_44_reg_5367[3];
ap_reg_ppstg_tmp_44_reg_5367_pp1_it1[4] <= tmp_44_reg_5367[4];
ap_reg_ppstg_tmp_44_reg_5367_pp1_it1[5] <= tmp_44_reg_5367[5];
ap_reg_ppstg_tmp_44_reg_5367_pp1_it1[6] <= tmp_44_reg_5367[6];
ap_reg_ppstg_tmp_44_reg_5367_pp1_it1[7] <= tmp_44_reg_5367[7];
ap_reg_ppstg_tmp_44_reg_5367_pp1_it1[8] <= tmp_44_reg_5367[8];
ap_reg_ppstg_tmp_44_reg_5367_pp1_it1[9] <= tmp_44_reg_5367[9];
ap_reg_ppstg_tmp_44_reg_5367_pp1_it1[10] <= tmp_44_reg_5367[10];
ap_reg_ppstg_tmp_44_reg_5367_pp1_it1[11] <= tmp_44_reg_5367[11];
ap_reg_ppstg_tmp_44_reg_5367_pp1_it1[12] <= tmp_44_reg_5367[12];
ap_reg_ppstg_tmp_44_reg_5367_pp1_it1[13] <= tmp_44_reg_5367[13];
end
if ((ap_ST_pp1_stg3_fsm_7 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_44_reg_5367_pp1_it2[0] <= ap_reg_ppstg_tmp_44_reg_5367_pp1_it1[0];
ap_reg_ppstg_tmp_44_reg_5367_pp1_it2[1] <= ap_reg_ppstg_tmp_44_reg_5367_pp1_it1[1];
ap_reg_ppstg_tmp_44_reg_5367_pp1_it2[2] <= ap_reg_ppstg_tmp_44_reg_5367_pp1_it1[2];
ap_reg_ppstg_tmp_44_reg_5367_pp1_it2[3] <= ap_reg_ppstg_tmp_44_reg_5367_pp1_it1[3];
ap_reg_ppstg_tmp_44_reg_5367_pp1_it2[4] <= ap_reg_ppstg_tmp_44_reg_5367_pp1_it1[4];
ap_reg_ppstg_tmp_44_reg_5367_pp1_it2[5] <= ap_reg_ppstg_tmp_44_reg_5367_pp1_it1[5];
ap_reg_ppstg_tmp_44_reg_5367_pp1_it2[6] <= ap_reg_ppstg_tmp_44_reg_5367_pp1_it1[6];
ap_reg_ppstg_tmp_44_reg_5367_pp1_it2[7] <= ap_reg_ppstg_tmp_44_reg_5367_pp1_it1[7];
ap_reg_ppstg_tmp_44_reg_5367_pp1_it2[8] <= ap_reg_ppstg_tmp_44_reg_5367_pp1_it1[8];
ap_reg_ppstg_tmp_44_reg_5367_pp1_it2[9] <= ap_reg_ppstg_tmp_44_reg_5367_pp1_it1[9];
ap_reg_ppstg_tmp_44_reg_5367_pp1_it2[10] <= ap_reg_ppstg_tmp_44_reg_5367_pp1_it1[10];
ap_reg_ppstg_tmp_44_reg_5367_pp1_it2[11] <= ap_reg_ppstg_tmp_44_reg_5367_pp1_it1[11];
ap_reg_ppstg_tmp_44_reg_5367_pp1_it2[12] <= ap_reg_ppstg_tmp_44_reg_5367_pp1_it1[12];
ap_reg_ppstg_tmp_44_reg_5367_pp1_it2[13] <= ap_reg_ppstg_tmp_44_reg_5367_pp1_it1[13];
end
if ((ap_ST_pp1_stg3_fsm_7 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_47_reg_5407_pp1_it2[0] <= tmp_47_reg_5407[0];
ap_reg_ppstg_tmp_47_reg_5407_pp1_it2[1] <= tmp_47_reg_5407[1];
ap_reg_ppstg_tmp_47_reg_5407_pp1_it2[2] <= tmp_47_reg_5407[2];
ap_reg_ppstg_tmp_47_reg_5407_pp1_it2[3] <= tmp_47_reg_5407[3];
ap_reg_ppstg_tmp_47_reg_5407_pp1_it2[4] <= tmp_47_reg_5407[4];
ap_reg_ppstg_tmp_47_reg_5407_pp1_it2[5] <= tmp_47_reg_5407[5];
ap_reg_ppstg_tmp_47_reg_5407_pp1_it2[6] <= tmp_47_reg_5407[6];
ap_reg_ppstg_tmp_47_reg_5407_pp1_it2[7] <= tmp_47_reg_5407[7];
ap_reg_ppstg_tmp_47_reg_5407_pp1_it2[8] <= tmp_47_reg_5407[8];
ap_reg_ppstg_tmp_47_reg_5407_pp1_it2[9] <= tmp_47_reg_5407[9];
ap_reg_ppstg_tmp_47_reg_5407_pp1_it2[10] <= tmp_47_reg_5407[10];
ap_reg_ppstg_tmp_47_reg_5407_pp1_it2[11] <= tmp_47_reg_5407[11];
ap_reg_ppstg_tmp_47_reg_5407_pp1_it2[12] <= tmp_47_reg_5407[12];
ap_reg_ppstg_tmp_47_reg_5407_pp1_it2[13] <= tmp_47_reg_5407[13];
end
if ((ap_ST_pp1_stg4_fsm_8 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_51_reg_5417_pp1_it2[0] <= tmp_51_reg_5417[0];
ap_reg_ppstg_tmp_51_reg_5417_pp1_it2[1] <= tmp_51_reg_5417[1];
ap_reg_ppstg_tmp_51_reg_5417_pp1_it2[2] <= tmp_51_reg_5417[2];
ap_reg_ppstg_tmp_51_reg_5417_pp1_it2[3] <= tmp_51_reg_5417[3];
ap_reg_ppstg_tmp_51_reg_5417_pp1_it2[4] <= tmp_51_reg_5417[4];
ap_reg_ppstg_tmp_51_reg_5417_pp1_it2[5] <= tmp_51_reg_5417[5];
ap_reg_ppstg_tmp_51_reg_5417_pp1_it2[6] <= tmp_51_reg_5417[6];
ap_reg_ppstg_tmp_51_reg_5417_pp1_it2[7] <= tmp_51_reg_5417[7];
ap_reg_ppstg_tmp_51_reg_5417_pp1_it2[8] <= tmp_51_reg_5417[8];
ap_reg_ppstg_tmp_51_reg_5417_pp1_it2[9] <= tmp_51_reg_5417[9];
ap_reg_ppstg_tmp_51_reg_5417_pp1_it2[10] <= tmp_51_reg_5417[10];
ap_reg_ppstg_tmp_51_reg_5417_pp1_it2[11] <= tmp_51_reg_5417[11];
ap_reg_ppstg_tmp_51_reg_5417_pp1_it2[12] <= tmp_51_reg_5417[12];
ap_reg_ppstg_tmp_51_reg_5417_pp1_it2[13] <= tmp_51_reg_5417[13];
end
if ((ap_ST_pp2_stg0_fsm_12 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_59_reg_5436_pp2_it1[0] <= tmp_59_reg_5436[0];
ap_reg_ppstg_tmp_59_reg_5436_pp2_it1[1] <= tmp_59_reg_5436[1];
ap_reg_ppstg_tmp_59_reg_5436_pp2_it1[2] <= tmp_59_reg_5436[2];
ap_reg_ppstg_tmp_59_reg_5436_pp2_it1[3] <= tmp_59_reg_5436[3];
ap_reg_ppstg_tmp_59_reg_5436_pp2_it1[4] <= tmp_59_reg_5436[4];
ap_reg_ppstg_tmp_59_reg_5436_pp2_it1[5] <= tmp_59_reg_5436[5];
ap_reg_ppstg_tmp_59_reg_5436_pp2_it1[6] <= tmp_59_reg_5436[6];
ap_reg_ppstg_tmp_59_reg_5436_pp2_it1[7] <= tmp_59_reg_5436[7];
ap_reg_ppstg_tmp_59_reg_5436_pp2_it1[8] <= tmp_59_reg_5436[8];
ap_reg_ppstg_tmp_59_reg_5436_pp2_it1[9] <= tmp_59_reg_5436[9];
ap_reg_ppstg_tmp_59_reg_5436_pp2_it1[10] <= tmp_59_reg_5436[10];
ap_reg_ppstg_tmp_59_reg_5436_pp2_it1[11] <= tmp_59_reg_5436[11];
ap_reg_ppstg_tmp_59_reg_5436_pp2_it1[12] <= tmp_59_reg_5436[12];
end
if ((ap_ST_pp2_stg0_fsm_12 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_59_reg_5436_pp2_it2[0] <= ap_reg_ppstg_tmp_59_reg_5436_pp2_it1[0];
ap_reg_ppstg_tmp_59_reg_5436_pp2_it2[1] <= ap_reg_ppstg_tmp_59_reg_5436_pp2_it1[1];
ap_reg_ppstg_tmp_59_reg_5436_pp2_it2[2] <= ap_reg_ppstg_tmp_59_reg_5436_pp2_it1[2];
ap_reg_ppstg_tmp_59_reg_5436_pp2_it2[3] <= ap_reg_ppstg_tmp_59_reg_5436_pp2_it1[3];
ap_reg_ppstg_tmp_59_reg_5436_pp2_it2[4] <= ap_reg_ppstg_tmp_59_reg_5436_pp2_it1[4];
ap_reg_ppstg_tmp_59_reg_5436_pp2_it2[5] <= ap_reg_ppstg_tmp_59_reg_5436_pp2_it1[5];
ap_reg_ppstg_tmp_59_reg_5436_pp2_it2[6] <= ap_reg_ppstg_tmp_59_reg_5436_pp2_it1[6];
ap_reg_ppstg_tmp_59_reg_5436_pp2_it2[7] <= ap_reg_ppstg_tmp_59_reg_5436_pp2_it1[7];
ap_reg_ppstg_tmp_59_reg_5436_pp2_it2[8] <= ap_reg_ppstg_tmp_59_reg_5436_pp2_it1[8];
ap_reg_ppstg_tmp_59_reg_5436_pp2_it2[9] <= ap_reg_ppstg_tmp_59_reg_5436_pp2_it1[9];
ap_reg_ppstg_tmp_59_reg_5436_pp2_it2[10] <= ap_reg_ppstg_tmp_59_reg_5436_pp2_it1[10];
ap_reg_ppstg_tmp_59_reg_5436_pp2_it2[11] <= ap_reg_ppstg_tmp_59_reg_5436_pp2_it1[11];
ap_reg_ppstg_tmp_59_reg_5436_pp2_it2[12] <= ap_reg_ppstg_tmp_59_reg_5436_pp2_it1[12];
end
if ((ap_ST_pp2_stg0_fsm_12 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_59_reg_5436_pp2_it3[0] <= ap_reg_ppstg_tmp_59_reg_5436_pp2_it2[0];
ap_reg_ppstg_tmp_59_reg_5436_pp2_it3[1] <= ap_reg_ppstg_tmp_59_reg_5436_pp2_it2[1];
ap_reg_ppstg_tmp_59_reg_5436_pp2_it3[2] <= ap_reg_ppstg_tmp_59_reg_5436_pp2_it2[2];
ap_reg_ppstg_tmp_59_reg_5436_pp2_it3[3] <= ap_reg_ppstg_tmp_59_reg_5436_pp2_it2[3];
ap_reg_ppstg_tmp_59_reg_5436_pp2_it3[4] <= ap_reg_ppstg_tmp_59_reg_5436_pp2_it2[4];
ap_reg_ppstg_tmp_59_reg_5436_pp2_it3[5] <= ap_reg_ppstg_tmp_59_reg_5436_pp2_it2[5];
ap_reg_ppstg_tmp_59_reg_5436_pp2_it3[6] <= ap_reg_ppstg_tmp_59_reg_5436_pp2_it2[6];
ap_reg_ppstg_tmp_59_reg_5436_pp2_it3[7] <= ap_reg_ppstg_tmp_59_reg_5436_pp2_it2[7];
ap_reg_ppstg_tmp_59_reg_5436_pp2_it3[8] <= ap_reg_ppstg_tmp_59_reg_5436_pp2_it2[8];
ap_reg_ppstg_tmp_59_reg_5436_pp2_it3[9] <= ap_reg_ppstg_tmp_59_reg_5436_pp2_it2[9];
ap_reg_ppstg_tmp_59_reg_5436_pp2_it3[10] <= ap_reg_ppstg_tmp_59_reg_5436_pp2_it2[10];
ap_reg_ppstg_tmp_59_reg_5436_pp2_it3[11] <= ap_reg_ppstg_tmp_59_reg_5436_pp2_it2[11];
ap_reg_ppstg_tmp_59_reg_5436_pp2_it3[12] <= ap_reg_ppstg_tmp_59_reg_5436_pp2_it2[12];
end
if ((ap_ST_pp2_stg0_fsm_12 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_59_reg_5436_pp2_it4[0] <= ap_reg_ppstg_tmp_59_reg_5436_pp2_it3[0];
ap_reg_ppstg_tmp_59_reg_5436_pp2_it4[1] <= ap_reg_ppstg_tmp_59_reg_5436_pp2_it3[1];
ap_reg_ppstg_tmp_59_reg_5436_pp2_it4[2] <= ap_reg_ppstg_tmp_59_reg_5436_pp2_it3[2];
ap_reg_ppstg_tmp_59_reg_5436_pp2_it4[3] <= ap_reg_ppstg_tmp_59_reg_5436_pp2_it3[3];
ap_reg_ppstg_tmp_59_reg_5436_pp2_it4[4] <= ap_reg_ppstg_tmp_59_reg_5436_pp2_it3[4];
ap_reg_ppstg_tmp_59_reg_5436_pp2_it4[5] <= ap_reg_ppstg_tmp_59_reg_5436_pp2_it3[5];
ap_reg_ppstg_tmp_59_reg_5436_pp2_it4[6] <= ap_reg_ppstg_tmp_59_reg_5436_pp2_it3[6];
ap_reg_ppstg_tmp_59_reg_5436_pp2_it4[7] <= ap_reg_ppstg_tmp_59_reg_5436_pp2_it3[7];
ap_reg_ppstg_tmp_59_reg_5436_pp2_it4[8] <= ap_reg_ppstg_tmp_59_reg_5436_pp2_it3[8];
ap_reg_ppstg_tmp_59_reg_5436_pp2_it4[9] <= ap_reg_ppstg_tmp_59_reg_5436_pp2_it3[9];
ap_reg_ppstg_tmp_59_reg_5436_pp2_it4[10] <= ap_reg_ppstg_tmp_59_reg_5436_pp2_it3[10];
ap_reg_ppstg_tmp_59_reg_5436_pp2_it4[11] <= ap_reg_ppstg_tmp_59_reg_5436_pp2_it3[11];
ap_reg_ppstg_tmp_59_reg_5436_pp2_it4[12] <= ap_reg_ppstg_tmp_59_reg_5436_pp2_it3[12];
end
if ((ap_ST_pp2_stg0_fsm_12 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_59_reg_5436_pp2_it5[0] <= ap_reg_ppstg_tmp_59_reg_5436_pp2_it4[0];
ap_reg_ppstg_tmp_59_reg_5436_pp2_it5[1] <= ap_reg_ppstg_tmp_59_reg_5436_pp2_it4[1];
ap_reg_ppstg_tmp_59_reg_5436_pp2_it5[2] <= ap_reg_ppstg_tmp_59_reg_5436_pp2_it4[2];
ap_reg_ppstg_tmp_59_reg_5436_pp2_it5[3] <= ap_reg_ppstg_tmp_59_reg_5436_pp2_it4[3];
ap_reg_ppstg_tmp_59_reg_5436_pp2_it5[4] <= ap_reg_ppstg_tmp_59_reg_5436_pp2_it4[4];
ap_reg_ppstg_tmp_59_reg_5436_pp2_it5[5] <= ap_reg_ppstg_tmp_59_reg_5436_pp2_it4[5];
ap_reg_ppstg_tmp_59_reg_5436_pp2_it5[6] <= ap_reg_ppstg_tmp_59_reg_5436_pp2_it4[6];
ap_reg_ppstg_tmp_59_reg_5436_pp2_it5[7] <= ap_reg_ppstg_tmp_59_reg_5436_pp2_it4[7];
ap_reg_ppstg_tmp_59_reg_5436_pp2_it5[8] <= ap_reg_ppstg_tmp_59_reg_5436_pp2_it4[8];
ap_reg_ppstg_tmp_59_reg_5436_pp2_it5[9] <= ap_reg_ppstg_tmp_59_reg_5436_pp2_it4[9];
ap_reg_ppstg_tmp_59_reg_5436_pp2_it5[10] <= ap_reg_ppstg_tmp_59_reg_5436_pp2_it4[10];
ap_reg_ppstg_tmp_59_reg_5436_pp2_it5[11] <= ap_reg_ppstg_tmp_59_reg_5436_pp2_it4[11];
ap_reg_ppstg_tmp_59_reg_5436_pp2_it5[12] <= ap_reg_ppstg_tmp_59_reg_5436_pp2_it4[12];
end
if ((ap_ST_pp3_stg0_fsm_13 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_67_reg_5488_pp3_it1 <= tmp_67_reg_5488;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_6_reg_5180_pp0_it1[6] <= tmp_6_reg_5180[6];
ap_reg_ppstg_tmp_6_reg_5180_pp0_it1[7] <= tmp_6_reg_5180[7];
ap_reg_ppstg_tmp_6_reg_5180_pp0_it1[8] <= tmp_6_reg_5180[8];
ap_reg_ppstg_tmp_6_reg_5180_pp0_it1[9] <= tmp_6_reg_5180[9];
ap_reg_ppstg_tmp_6_reg_5180_pp0_it1[10] <= tmp_6_reg_5180[10];
ap_reg_ppstg_tmp_6_reg_5180_pp0_it1[11] <= tmp_6_reg_5180[11];
ap_reg_ppstg_tmp_6_reg_5180_pp0_it1[12] <= tmp_6_reg_5180[12];
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_6_reg_5180_pp0_it2[6] <= ap_reg_ppstg_tmp_6_reg_5180_pp0_it1[6];
ap_reg_ppstg_tmp_6_reg_5180_pp0_it2[7] <= ap_reg_ppstg_tmp_6_reg_5180_pp0_it1[7];
ap_reg_ppstg_tmp_6_reg_5180_pp0_it2[8] <= ap_reg_ppstg_tmp_6_reg_5180_pp0_it1[8];
ap_reg_ppstg_tmp_6_reg_5180_pp0_it2[9] <= ap_reg_ppstg_tmp_6_reg_5180_pp0_it1[9];
ap_reg_ppstg_tmp_6_reg_5180_pp0_it2[10] <= ap_reg_ppstg_tmp_6_reg_5180_pp0_it1[10];
ap_reg_ppstg_tmp_6_reg_5180_pp0_it2[11] <= ap_reg_ppstg_tmp_6_reg_5180_pp0_it1[11];
ap_reg_ppstg_tmp_6_reg_5180_pp0_it2[12] <= ap_reg_ppstg_tmp_6_reg_5180_pp0_it1[12];
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_6_reg_5180_pp0_it3[6] <= ap_reg_ppstg_tmp_6_reg_5180_pp0_it2[6];
ap_reg_ppstg_tmp_6_reg_5180_pp0_it3[7] <= ap_reg_ppstg_tmp_6_reg_5180_pp0_it2[7];
ap_reg_ppstg_tmp_6_reg_5180_pp0_it3[8] <= ap_reg_ppstg_tmp_6_reg_5180_pp0_it2[8];
ap_reg_ppstg_tmp_6_reg_5180_pp0_it3[9] <= ap_reg_ppstg_tmp_6_reg_5180_pp0_it2[9];
ap_reg_ppstg_tmp_6_reg_5180_pp0_it3[10] <= ap_reg_ppstg_tmp_6_reg_5180_pp0_it2[10];
ap_reg_ppstg_tmp_6_reg_5180_pp0_it3[11] <= ap_reg_ppstg_tmp_6_reg_5180_pp0_it2[11];
ap_reg_ppstg_tmp_6_reg_5180_pp0_it3[12] <= ap_reg_ppstg_tmp_6_reg_5180_pp0_it2[12];
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_6_reg_5180_pp0_it4[6] <= ap_reg_ppstg_tmp_6_reg_5180_pp0_it3[6];
ap_reg_ppstg_tmp_6_reg_5180_pp0_it4[7] <= ap_reg_ppstg_tmp_6_reg_5180_pp0_it3[7];
ap_reg_ppstg_tmp_6_reg_5180_pp0_it4[8] <= ap_reg_ppstg_tmp_6_reg_5180_pp0_it3[8];
ap_reg_ppstg_tmp_6_reg_5180_pp0_it4[9] <= ap_reg_ppstg_tmp_6_reg_5180_pp0_it3[9];
ap_reg_ppstg_tmp_6_reg_5180_pp0_it4[10] <= ap_reg_ppstg_tmp_6_reg_5180_pp0_it3[10];
ap_reg_ppstg_tmp_6_reg_5180_pp0_it4[11] <= ap_reg_ppstg_tmp_6_reg_5180_pp0_it3[11];
ap_reg_ppstg_tmp_6_reg_5180_pp0_it4[12] <= ap_reg_ppstg_tmp_6_reg_5180_pp0_it3[12];
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_6_reg_5180_pp0_it5[6] <= ap_reg_ppstg_tmp_6_reg_5180_pp0_it4[6];
ap_reg_ppstg_tmp_6_reg_5180_pp0_it5[7] <= ap_reg_ppstg_tmp_6_reg_5180_pp0_it4[7];
ap_reg_ppstg_tmp_6_reg_5180_pp0_it5[8] <= ap_reg_ppstg_tmp_6_reg_5180_pp0_it4[8];
ap_reg_ppstg_tmp_6_reg_5180_pp0_it5[9] <= ap_reg_ppstg_tmp_6_reg_5180_pp0_it4[9];
ap_reg_ppstg_tmp_6_reg_5180_pp0_it5[10] <= ap_reg_ppstg_tmp_6_reg_5180_pp0_it4[10];
ap_reg_ppstg_tmp_6_reg_5180_pp0_it5[11] <= ap_reg_ppstg_tmp_6_reg_5180_pp0_it4[11];
ap_reg_ppstg_tmp_6_reg_5180_pp0_it5[12] <= ap_reg_ppstg_tmp_6_reg_5180_pp0_it4[12];
end
if ((ap_ST_pp3_stg1_fsm_14 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_75_reg_5523_pp3_it1 <= tmp_75_reg_5523;
end
if ((ap_ST_pp3_stg1_fsm_14 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_83_reg_5538_pp3_it1 <= tmp_83_reg_5538;
end
if ((ap_ST_pp3_stg2_fsm_15 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_86_reg_5583_pp3_it1 <= tmp_86_reg_5583;
end
if ((ap_ST_pp3_stg2_fsm_15 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_90_reg_5598_pp3_it1 <= tmp_90_reg_5598;
end
if ((ap_ST_pp3_stg3_fsm_16 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_98_reg_5618_pp3_it1 <= tmp_98_reg_5618;
end
if ((ap_ST_pp3_stg3_fsm_16 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_98_reg_5618_pp3_it2 <= ap_reg_ppstg_tmp_98_reg_5618_pp3_it1;
end
if ((ap_ST_pp1_stg0_fsm_4 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_9_reg_5237_pp1_it1[0] <= tmp_9_reg_5237[0];
ap_reg_ppstg_tmp_9_reg_5237_pp1_it1[1] <= tmp_9_reg_5237[1];
ap_reg_ppstg_tmp_9_reg_5237_pp1_it1[2] <= tmp_9_reg_5237[2];
ap_reg_ppstg_tmp_9_reg_5237_pp1_it1[3] <= tmp_9_reg_5237[3];
ap_reg_ppstg_tmp_9_reg_5237_pp1_it1[4] <= tmp_9_reg_5237[4];
ap_reg_ppstg_tmp_9_reg_5237_pp1_it1[5] <= tmp_9_reg_5237[5];
ap_reg_ppstg_tmp_9_reg_5237_pp1_it1[6] <= tmp_9_reg_5237[6];
ap_reg_ppstg_tmp_9_reg_5237_pp1_it1[7] <= tmp_9_reg_5237[7];
ap_reg_ppstg_tmp_9_reg_5237_pp1_it1[8] <= tmp_9_reg_5237[8];
ap_reg_ppstg_tmp_9_reg_5237_pp1_it1[9] <= tmp_9_reg_5237[9];
ap_reg_ppstg_tmp_9_reg_5237_pp1_it1[10] <= tmp_9_reg_5237[10];
ap_reg_ppstg_tmp_9_reg_5237_pp1_it1[11] <= tmp_9_reg_5237[11];
ap_reg_ppstg_tmp_9_reg_5237_pp1_it1[12] <= tmp_9_reg_5237[12];
ap_reg_ppstg_tmp_9_reg_5237_pp1_it1[13] <= tmp_9_reg_5237[13];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp3_it0) & (ap_const_lv1_0 == exitcond6_reg_5446) & (ap_ST_pp3_stg4_fsm_17 == ap_CS_fsm))) begin
b_addr23_reg_5633 <= (b_addr22_cast_fu_3513_p1 + tmp_44_trn_cast_reg_5477);
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp3_it0) & (ap_const_lv1_0 == exitcond6_reg_5446) & (ap_ST_pp3_stg4_fsm_17 == ap_CS_fsm))) begin
b_addr25_reg_5643 <= (b_addr24_cast_fu_3562_p1 + tmp_44_trn_cast_reg_5477);
end
if (((ap_ST_pp5_stg1_fsm_23 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp5_it0) & (ap_const_lv1_0 == exitcond9_reg_5697))) begin
b_addr26_cast_reg_5755[6] <= b_addr26_cast_fu_3731_p1[6];
b_addr26_cast_reg_5755[7] <= b_addr26_cast_fu_3731_p1[7];
b_addr26_cast_reg_5755[8] <= b_addr26_cast_fu_3731_p1[8];
b_addr26_cast_reg_5755[9] <= b_addr26_cast_fu_3731_p1[9];
b_addr26_cast_reg_5755[10] <= b_addr26_cast_fu_3731_p1[10];
b_addr26_cast_reg_5755[11] <= b_addr26_cast_fu_3731_p1[11];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp7_it0) & (ap_ST_pp7_stg0_fsm_31 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond12_fu_4005_p2))) begin
b_addr36_cast_reg_5956[6] <= b_addr36_cast_fu_4063_p1[6];
b_addr36_cast_reg_5956[7] <= b_addr36_cast_fu_4063_p1[7];
b_addr36_cast_reg_5956[8] <= b_addr36_cast_fu_4063_p1[8];
b_addr36_cast_reg_5956[9] <= b_addr36_cast_fu_4063_p1[9];
b_addr36_cast_reg_5956[10] <= b_addr36_cast_fu_4063_p1[10];
b_addr36_cast_reg_5956[11] <= b_addr36_cast_fu_4063_p1[11];
b_addr36_cast_reg_5956[12] <= b_addr36_cast_fu_4063_p1[12];
b_addr36_cast_reg_5956[13] <= b_addr36_cast_fu_4063_p1[13];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp7_it1) & (ap_ST_pp7_stg3_fsm_34 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond12_reg_5924_pp7_it1))) begin
b_addr44_reg_6117[3] <= b_addr44_fu_4348_p2[3];
b_addr44_reg_6117[4] <= b_addr44_fu_4348_p2[4];
b_addr44_reg_6117[5] <= b_addr44_fu_4348_p2[5];
b_addr44_reg_6117[6] <= b_addr44_fu_4348_p2[6];
b_addr44_reg_6117[7] <= b_addr44_fu_4348_p2[7];
b_addr44_reg_6117[8] <= b_addr44_fu_4348_p2[8];
b_addr44_reg_6117[9] <= b_addr44_fu_4348_p2[9];
b_addr44_reg_6117[10] <= b_addr44_fu_4348_p2[10];
b_addr44_reg_6117[11] <= b_addr44_fu_4348_p2[11];
b_addr44_reg_6117[12] <= b_addr44_fu_4348_p2[12];
b_addr44_reg_6117[13] <= b_addr44_fu_4348_p2[13];
end
if (((ap_ST_pp1_stg1_fsm_5 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond3_reg_5195))) begin
b_addr4_reg_5297[0] <= b_addr4_fu_2645_p2[0];
b_addr4_reg_5297[2] <= b_addr4_fu_2645_p2[2];
b_addr4_reg_5297[3] <= b_addr4_fu_2645_p2[3];
b_addr4_reg_5297[4] <= b_addr4_fu_2645_p2[4];
b_addr4_reg_5297[5] <= b_addr4_fu_2645_p2[5];
b_addr4_reg_5297[6] <= b_addr4_fu_2645_p2[6];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp3_it0) & (ap_ST_pp3_stg0_fsm_13 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond6_fu_3025_p2))) begin
b_addr53_reg_5498 <= tmp_51_trn_cast_fu_3069_p1[6:0];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond3_reg_5195) & (ap_ST_pp1_stg2_fsm_6 == ap_CS_fsm))) begin
b_addr8_reg_5357[0] <= b_addr8_fu_2803_p2[0];
b_addr8_reg_5357[1] <= b_addr8_fu_2803_p2[1];
b_addr8_reg_5357[3] <= b_addr8_fu_2803_p2[3];
b_addr8_reg_5357[4] <= b_addr8_fu_2803_p2[4];
b_addr8_reg_5357[5] <= b_addr8_fu_2803_p2[5];
b_addr8_reg_5357[6] <= b_addr8_fu_2803_p2[6];
end
if (((ap_ST_pp6_stg0_fsm_30 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp6_it0))) begin
exitcond10_reg_5905 <= (j_4_phi_fu_2055_p4 == ap_const_lv7_40? 1'b1: 1'b0);
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp7_it0) & (ap_ST_pp7_stg0_fsm_31 == ap_CS_fsm))) begin
exitcond12_reg_5924 <= (indvar_flatten3_phi_fu_2066_p4 == ap_const_lv9_1F8? 1'b1: 1'b0);
end
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0))) begin
exitcond1_reg_5171 <= (i_phi_fu_1890_p4 == ap_const_lv7_40? 1'b1: 1'b0);
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_ST_pp1_stg0_fsm_4 == ap_CS_fsm))) begin
exitcond3_reg_5195 <= (indvar_flatten_phi_fu_1901_p4 == ap_const_lv9_1F8? 1'b1: 1'b0);
end
if (((ap_ST_pp2_stg0_fsm_12 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp2_it0))) begin
exitcond4_reg_5427 <= (i_2_phi_fu_1945_p4 == ap_const_lv7_40? 1'b1: 1'b0);
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp3_it0) & (ap_ST_pp3_stg0_fsm_13 == ap_CS_fsm))) begin
exitcond6_reg_5446 <= (indvar_flatten1_phi_fu_1956_p4 == ap_const_lv9_1F8? 1'b1: 1'b0);
end
if (((ap_ST_pp4_stg0_fsm_21 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp4_it0))) begin
exitcond7_reg_5678 <= (j_2_phi_fu_2000_p4 == ap_const_lv7_40? 1'b1: 1'b0);
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp5_it0) & (ap_ST_pp5_stg0_fsm_22 == ap_CS_fsm))) begin
exitcond9_reg_5697 <= (indvar_flatten2_phi_fu_2011_p4 == ap_const_lv9_1F8? 1'b1: 1'b0);
end
if (((ap_ST_pp8_stg0_fsm_40 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp8_it0))) begin
exitcond_reg_6132 <= (indvar_flatten4_phi_fu_2110_p6 == ap_const_lv7_40? 1'b1: 1'b0);
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_ST_pp1_stg0_fsm_4 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond3_fu_2404_p2))) begin
if (exitcond5_fu_2416_p2) begin
i_1_mid2_reg_5204 <= ap_const_lv7_0;
end else begin
i_1_mid2_reg_5204 <= i_1_phi_fu_1934_p4;
end
end
if ((ap_ST_st9_fsm_3 == ap_CS_fsm)) begin
i_1_reg_1930 <= ap_const_lv7_0;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_const_lv1_0 == exitcond3_reg_5195) & (ap_ST_pp1_stg0_fsm_4 == ap_CS_fsm))) begin
i_1_reg_1930 <= tmp_43_reg_5402;
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_ST_pp1_stg0_fsm_4 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond3_fu_2404_p2))) begin
i_2_reg_1941 <= ap_const_lv7_0;
end else if (((ap_ST_pp2_stg0_fsm_12 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp2_it1) & (ap_const_lv1_0 == exitcond4_reg_5427))) begin
i_2_reg_1941 <= tmp_10_reg_5431;
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp3_it0) & (ap_ST_pp3_stg0_fsm_13 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond6_fu_3025_p2))) begin
if (exitcond8_fu_3037_p2) begin
i_3_mid2_reg_5455 <= ap_const_lv7_0;
end else begin
i_3_mid2_reg_5455 <= i_3_phi_fu_1989_p4;
end
end
if (((ap_ST_pp2_stg0_fsm_12 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp2_it0) & ~(ap_const_lv1_0 == exitcond4_fu_2988_p2))) begin
i_3_reg_1985 <= ap_const_lv7_0;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp3_it1) & (ap_const_lv1_0 == exitcond6_reg_5446) & (ap_ST_pp3_stg0_fsm_13 == ap_CS_fsm))) begin
i_3_reg_1985 <= tmp_82_reg_5653;
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp5_it0) & (ap_ST_pp5_stg0_fsm_22 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond9_fu_3626_p2))) begin
i_4_cast_reg_5724 <= i_4_mid2_fu_3658_p3[5:0];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp5_it0) & (ap_ST_pp5_stg0_fsm_22 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond9_fu_3626_p2))) begin
if (exitcond11_fu_3638_p2) begin
i_4_mid2_reg_5719 <= tmp_89_dup_fu_3652_p2;
end else begin
i_4_mid2_reg_5719 <= i_4_phi_fu_2022_p4;
end
end
if (((ap_ST_pp4_stg0_fsm_21 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp4_it0) & ~(ap_const_lv1_0 == exitcond7_fu_3609_p2))) begin
i_4_reg_2018 <= ap_const_lv7_1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp5_it1) & (ap_const_lv1_0 == exitcond9_reg_5697) & (ap_ST_pp5_stg0_fsm_22 == ap_CS_fsm))) begin
i_4_reg_2018 <= i_4_mid2_reg_5719;
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp7_it0) & (ap_ST_pp7_stg0_fsm_31 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond12_fu_4005_p2))) begin
i_5_cast_reg_5951 <= i_5_mid2_fu_4037_p3[5:0];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp7_it0) & (ap_ST_pp7_stg0_fsm_31 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond12_fu_4005_p2))) begin
if (exitcond13_fu_4017_p2) begin
i_5_mid2_reg_5946 <= tmp_125_dup_fu_4031_p2;
end else begin
i_5_mid2_reg_5946 <= i_5_phi_fu_2077_p4;
end
end
if (((ap_ST_pp6_stg0_fsm_30 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp6_it0) & ~(ap_const_lv1_0 == exitcond10_fu_3978_p2))) begin
i_5_reg_2073 <= ap_const_lv7_3E;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp7_it1) & (ap_const_lv1_0 == exitcond12_reg_5924) & (ap_ST_pp7_stg0_fsm_31 == ap_CS_fsm))) begin
i_5_reg_2073 <= i_5_mid2_reg_5946;
end
if (((ap_ST_pp8_stg0_fsm_40 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_fu_4357_p2))) begin
if (exitcond2_fu_4369_p2) begin
i_6_mid2_reg_6153 <= tmp_173_dup_fu_4383_p2;
end else begin
i_6_mid2_reg_6153 <= i_6_phi_fu_2124_p6;
end
end
if ((((ap_ST_st1_fsm_1 == ap_CS_fsm) & ~(ap_const_lv1_0 == or_cond_fu_2365_p2) & (ap_const_lv1_0 == tmp_2_fu_2371_p2)) | (ap_ST_st131_fsm_39 == ap_CS_fsm))) begin
i_6_reg_2120 <= ap_const_lv7_0;
end else if (((ap_ST_pp8_stg0_fsm_40 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp8_it1) & (ap_const_lv1_0 == exitcond_reg_6132))) begin
i_6_reg_2120 <= i_6_mid2_reg_6153;
end
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (exitcond1_reg_5171 == ap_const_lv1_0))) begin
i_reg_1886 <= tmp_5_reg_5175;
end else if (((ap_ST_st1_fsm_1 == ap_CS_fsm) & ~(ap_const_lv1_0 == or_cond_fu_2365_p2) & ~(ap_const_lv1_0 == tmp_2_fu_2371_p2))) begin
i_reg_1886 <= ap_const_lv7_0;
end
if ((ap_ST_st9_fsm_3 == ap_CS_fsm)) begin
indvar3_reg_1919 <= ap_const_lv4_0;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_const_lv1_0 == exitcond3_reg_5195) & (ap_ST_pp1_stg0_fsm_4 == ap_CS_fsm))) begin
indvar3_reg_1919 <= indvar_next3_reg_5252;
end
if (((ap_ST_pp6_stg0_fsm_30 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp6_it0) & ~(ap_const_lv1_0 == exitcond10_fu_3978_p2))) begin
indvar4_reg_2084 <= ap_const_lv4_0;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp7_it1) & (ap_const_lv1_0 == exitcond12_reg_5924) & (ap_ST_pp7_stg0_fsm_31 == ap_CS_fsm))) begin
indvar4_reg_2084 <= indvar_next5_reg_5977;
end
if (((ap_ST_pp2_stg0_fsm_12 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp2_it0) & ~(ap_const_lv1_0 == exitcond4_fu_2988_p2))) begin
indvar6_reg_1974 <= ap_const_lv4_0;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp3_it1) & (ap_const_lv1_0 == exitcond6_reg_5446) & (ap_ST_pp3_stg0_fsm_13 == ap_CS_fsm))) begin
indvar6_reg_1974 <= indvar_next6_reg_5503;
end
if (((ap_ST_pp4_stg0_fsm_21 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp4_it0) & ~(ap_const_lv1_0 == exitcond7_fu_3609_p2))) begin
indvar9_reg_2029 <= ap_const_lv4_0;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp5_it1) & (ap_const_lv1_0 == exitcond9_reg_5697) & (ap_ST_pp5_stg0_fsm_22 == ap_CS_fsm))) begin
indvar9_reg_2029 <= indvar_next9_reg_5750;
end
if (((ap_ST_pp2_stg0_fsm_12 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp2_it0) & ~(ap_const_lv1_0 == exitcond4_fu_2988_p2))) begin
indvar_flatten1_reg_1952 <= ap_const_lv9_0;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp3_it1) & (ap_const_lv1_0 == exitcond6_reg_5446) & (ap_ST_pp3_stg0_fsm_13 == ap_CS_fsm))) begin
indvar_flatten1_reg_1952 <= indvar_flatten_next1_reg_5450;
end
if (((ap_ST_pp4_stg0_fsm_21 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp4_it0) & ~(ap_const_lv1_0 == exitcond7_fu_3609_p2))) begin
indvar_flatten2_reg_2007 <= ap_const_lv9_0;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp5_it1) & (ap_const_lv1_0 == exitcond9_reg_5697) & (ap_ST_pp5_stg0_fsm_22 == ap_CS_fsm))) begin
indvar_flatten2_reg_2007 <= indvar_flatten_next2_reg_5701;
end
if (((ap_ST_pp6_stg0_fsm_30 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp6_it0) & ~(ap_const_lv1_0 == exitcond10_fu_3978_p2))) begin
indvar_flatten3_reg_2062 <= ap_const_lv9_0;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp7_it1) & (ap_const_lv1_0 == exitcond12_reg_5924) & (ap_ST_pp7_stg0_fsm_31 == ap_CS_fsm))) begin
indvar_flatten3_reg_2062 <= indvar_flatten_next3_reg_5928;
end
if ((((ap_ST_st1_fsm_1 == ap_CS_fsm) & ~(ap_const_lv1_0 == or_cond_fu_2365_p2) & (ap_const_lv1_0 == tmp_2_fu_2371_p2)) | (ap_ST_st131_fsm_39 == ap_CS_fsm))) begin
indvar_flatten4_reg_2106 <= ap_const_lv7_0;
end else if (((ap_ST_pp8_stg0_fsm_40 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp8_it1) & (ap_const_lv1_0 == exitcond_reg_6132))) begin
indvar_flatten4_reg_2106 <= indvar_flatten_next4_reg_6136;
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp3_it0) & (ap_ST_pp3_stg0_fsm_13 == ap_CS_fsm))) begin
indvar_flatten_next1_reg_5450 <= (indvar_flatten1_phi_fu_1956_p4 + ap_const_lv9_1);
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp5_it0) & (ap_ST_pp5_stg0_fsm_22 == ap_CS_fsm))) begin
indvar_flatten_next2_reg_5701 <= (indvar_flatten2_phi_fu_2011_p4 + ap_const_lv9_1);
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp7_it0) & (ap_ST_pp7_stg0_fsm_31 == ap_CS_fsm))) begin
indvar_flatten_next3_reg_5928 <= (indvar_flatten3_phi_fu_2066_p4 + ap_const_lv9_1);
end
if (((ap_ST_pp8_stg0_fsm_40 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp8_it0))) begin
indvar_flatten_next4_reg_6136 <= (indvar_flatten4_phi_fu_2110_p6 + ap_const_lv7_1);
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_ST_pp1_stg0_fsm_4 == ap_CS_fsm))) begin
indvar_flatten_next_reg_5199 <= (indvar_flatten_phi_fu_1901_p4 + ap_const_lv9_1);
end
if ((ap_ST_st9_fsm_3 == ap_CS_fsm)) begin
indvar_flatten_reg_1897 <= ap_const_lv9_0;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_const_lv1_0 == exitcond3_reg_5195) & (ap_ST_pp1_stg0_fsm_4 == ap_CS_fsm))) begin
indvar_flatten_reg_1897 <= indvar_flatten_next_reg_5199;
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_ST_pp1_stg0_fsm_4 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond3_fu_2404_p2))) begin
if (exitcond5_fu_2416_p2) begin
indvar_next3_reg_5252 <= ap_const_lv4_1;
end else begin
indvar_next3_reg_5252 <= indvar3_op_fu_2481_p2;
end
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp7_it0) & (ap_ST_pp7_stg0_fsm_31 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond12_fu_4005_p2))) begin
if (exitcond13_fu_4017_p2) begin
indvar_next5_reg_5977 <= ap_const_lv4_1;
end else begin
indvar_next5_reg_5977 <= indvar4_op_fu_4078_p2;
end
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp3_it0) & (ap_ST_pp3_stg0_fsm_13 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond6_fu_3025_p2))) begin
if (exitcond8_fu_3037_p2) begin
indvar_next6_reg_5503 <= ap_const_lv4_1;
end else begin
indvar_next6_reg_5503 <= indvar6_op_fu_3102_p2;
end
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp5_it0) & (ap_ST_pp5_stg0_fsm_22 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond9_fu_3626_p2))) begin
if (exitcond11_fu_3638_p2) begin
indvar_next9_reg_5750 <= ap_const_lv4_1;
end else begin
indvar_next9_reg_5750 <= indvar9_op_fu_3699_p2;
end
end
if (((ap_ST_pp8_stg0_fsm_40 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_fu_4357_p2))) begin
if (exitcond2_fu_4369_p2) begin
indvar_next_reg_6186 <= ap_const_lv4_1;
end else begin
indvar_next_reg_6186 <= indvar_op_fu_4426_p2;
end
end
if ((((ap_ST_st1_fsm_1 == ap_CS_fsm) & ~(ap_const_lv1_0 == or_cond_fu_2365_p2) & (ap_const_lv1_0 == tmp_2_fu_2371_p2)) | (ap_ST_st131_fsm_39 == ap_CS_fsm))) begin
indvar_reg_2134 <= ap_const_lv4_0;
end else if (((ap_ST_pp8_stg0_fsm_40 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp8_it1) & (ap_const_lv1_0 == exitcond_reg_6132))) begin
indvar_reg_2134 <= indvar_next_reg_6186;
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp3_it0) & (ap_ST_pp3_stg0_fsm_13 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond6_fu_3025_p2))) begin
j_1_cast_reg_5472 <= j_1_mid2_fu_3057_p3[5:0];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp3_it0) & (ap_ST_pp3_stg0_fsm_13 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond6_fu_3025_p2))) begin
if (exitcond8_fu_3037_p2) begin
j_1_mid2_reg_5467 <= tmp_50_dup_fu_3051_p2;
end else begin
j_1_mid2_reg_5467 <= j_1_phi_fu_1967_p4;
end
end
if (((ap_ST_pp2_stg0_fsm_12 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp2_it0) & ~(ap_const_lv1_0 == exitcond4_fu_2988_p2))) begin
j_1_reg_1963 <= ap_const_lv7_3E;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp3_it1) & (ap_const_lv1_0 == exitcond6_reg_5446) & (ap_ST_pp3_stg0_fsm_13 == ap_CS_fsm))) begin
j_1_reg_1963 <= j_1_mid2_reg_5467;
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp3_it0) & (ap_ST_pp3_stg0_fsm_13 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond6_fu_3025_p2))) begin
j_2_reg_1996 <= ap_const_lv7_0;
end else if (((ap_ST_pp4_stg0_fsm_21 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp4_it1) & (ap_const_lv1_0 == exitcond7_reg_5678))) begin
j_2_reg_1996 <= tmp_49_reg_5682;
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp5_it0) & (ap_ST_pp5_stg0_fsm_22 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond9_fu_3626_p2))) begin
if (exitcond11_fu_3638_p2) begin
j_3_mid2_reg_5706 <= ap_const_lv7_0;
end else begin
j_3_mid2_reg_5706 <= j_3_phi_fu_2044_p4;
end
end
if (((ap_ST_pp4_stg0_fsm_21 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp4_it0) & ~(ap_const_lv1_0 == exitcond7_fu_3609_p2))) begin
j_3_reg_2040 <= ap_const_lv7_0;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp5_it1) & (ap_const_lv1_0 == exitcond9_reg_5697) & (ap_ST_pp5_stg0_fsm_22 == ap_CS_fsm))) begin
j_3_reg_2040 <= tmp_121_reg_5875;
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp5_it0) & (ap_ST_pp5_stg0_fsm_22 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond9_fu_3626_p2))) begin
j_4_reg_2051 <= ap_const_lv7_0;
end else if (((ap_ST_pp6_stg0_fsm_30 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp6_it1) & (ap_const_lv1_0 == exitcond10_reg_5905))) begin
j_4_reg_2051 <= tmp_88_reg_5909;
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp7_it0) & (ap_ST_pp7_stg0_fsm_31 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond12_fu_4005_p2))) begin
if (exitcond13_fu_4017_p2) begin
j_5_mid2_reg_5933 <= ap_const_lv7_0;
end else begin
j_5_mid2_reg_5933 <= j_5_phi_fu_2099_p4;
end
end
if (((ap_ST_pp6_stg0_fsm_30 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp6_it0) & ~(ap_const_lv1_0 == exitcond10_fu_3978_p2))) begin
j_5_reg_2095 <= ap_const_lv7_0;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp7_it1) & (ap_const_lv1_0 == exitcond12_reg_5924) & (ap_ST_pp7_stg0_fsm_31 == ap_CS_fsm))) begin
j_5_reg_2095 <= tmp_157_reg_6102;
end
if (((ap_ST_pp8_stg0_fsm_40 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_fu_4357_p2))) begin
if (exitcond2_fu_4369_p2) begin
j_6_mid2_reg_6141 <= ap_const_lv7_0;
end else begin
j_6_mid2_reg_6141 <= j_6_phi_fu_2152_p6;
end
end
if ((((ap_ST_st1_fsm_1 == ap_CS_fsm) & ~(ap_const_lv1_0 == or_cond_fu_2365_p2) & (ap_const_lv1_0 == tmp_2_fu_2371_p2)) | (ap_ST_st131_fsm_39 == ap_CS_fsm))) begin
j_6_reg_2148 <= ap_const_lv7_0;
end else if (((ap_ST_pp8_stg0_fsm_40 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp8_it1) & (ap_const_lv1_0 == exitcond_reg_6132))) begin
j_6_reg_2148 <= tmp_189_reg_6358;
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_ST_pp1_stg0_fsm_4 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond3_fu_2404_p2))) begin
j_cast_reg_5221 <= j_mid2_fu_2436_p3[5:0];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_ST_pp1_stg0_fsm_4 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond3_fu_2404_p2))) begin
if (exitcond5_fu_2416_p2) begin
j_mid2_reg_5216 <= tmp_11_dup_fu_2430_p2;
end else begin
j_mid2_reg_5216 <= j_phi_fu_1912_p4;
end
end
if ((ap_ST_st9_fsm_3 == ap_CS_fsm)) begin
j_reg_1908 <= ap_const_lv7_1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_const_lv1_0 == exitcond3_reg_5195) & (ap_ST_pp1_stg0_fsm_4 == ap_CS_fsm))) begin
j_reg_1908 <= j_mid2_reg_5216;
end
if ((((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (exitcond1_reg_5171 == ap_const_lv1_0)) | ((ap_ST_pp1_stg1_fsm_5 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond3_reg_5195)) | ((ap_ST_pp3_stg2_fsm_15 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp3_it0) & (ap_const_lv1_0 == exitcond6_reg_5446)) | ((ap_ST_pp4_stg0_fsm_21 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp4_it1) & (ap_const_lv1_0 == exitcond7_reg_5678)) | ((ap_ST_pp5_stg1_fsm_23 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp5_it0) & (ap_const_lv1_0 == exitcond9_reg_5697)) | ((ap_ST_pp7_stg2_fsm_33 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp7_it0) & (ap_const_lv1_0 == exitcond12_reg_5924)))) begin
reg_2171 <= a_q0;
end
if ((((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it5) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond1_reg_5171_pp0_it4)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond3_reg_5195) & (ap_ST_pp1_stg6_fsm_10 == ap_CS_fsm)) | ((ap_ST_pp2_stg0_fsm_12 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp2_it5) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond4_reg_5427_pp2_it4)) | ((ap_const_logic_1 == ap_reg_ppiten_pp3_it0) & (ap_const_lv1_0 == exitcond6_reg_5446) & (ap_ST_pp3_stg6_fsm_19 == ap_CS_fsm)) | ((ap_ST_pp4_stg0_fsm_21 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp4_it5) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond7_reg_5678_pp4_it4)) | ((ap_const_logic_1 == ap_reg_ppiten_pp5_it0) & (ap_const_lv1_0 == exitcond9_reg_5697) & (ap_ST_pp5_stg6_fsm_28 == ap_CS_fsm)) | ((ap_ST_pp6_stg0_fsm_30 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp6_it5) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond10_reg_5905_pp6_it4)) | ((ap_const_logic_1 == ap_reg_ppiten_pp7_it0) & (ap_const_lv1_0 == exitcond12_reg_5924) & (ap_ST_pp7_stg6_fsm_37 == ap_CS_fsm)))) begin
reg_2177 <= grp_fu_2167_p2;
end
if ((((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond3_reg_5195) & (ap_ST_pp1_stg2_fsm_6 == ap_CS_fsm)) | ((ap_ST_pp2_stg0_fsm_12 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp2_it1) & (ap_const_lv1_0 == exitcond4_reg_5427)) | ((ap_const_logic_1 == ap_reg_ppiten_pp3_it0) & (ap_const_lv1_0 == exitcond6_reg_5446) & (ap_ST_pp3_stg1_fsm_14 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp5_it0) & (ap_const_lv1_0 == exitcond9_reg_5697) & (ap_ST_pp5_stg2_fsm_24 == ap_CS_fsm)) | ((ap_ST_pp6_stg0_fsm_30 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp6_it1) & (ap_const_lv1_0 == exitcond10_reg_5905)) | ((ap_const_logic_1 == ap_reg_ppiten_pp7_it0) & (ap_const_lv1_0 == exitcond12_reg_5924) & (ap_ST_pp7_stg1_fsm_32 == ap_CS_fsm)))) begin
reg_2184 <= b_q0;
end
if ((((ap_ST_pp3_stg2_fsm_15 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp3_it0) & (ap_const_lv1_0 == exitcond6_reg_5446)) | ((ap_ST_pp7_stg2_fsm_33 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp7_it0) & (ap_const_lv1_0 == exitcond12_reg_5924)))) begin
reg_2190 <= a_q1;
end else if ((((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond3_reg_5195) & (ap_ST_pp1_stg2_fsm_6 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp5_it0) & (ap_const_lv1_0 == exitcond9_reg_5697) & (ap_ST_pp5_stg2_fsm_24 == ap_CS_fsm)))) begin
reg_2190 <= a_q0;
end
if ((((ap_ST_pp3_stg2_fsm_15 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp3_it0) & (ap_const_lv1_0 == exitcond6_reg_5446)) | ((ap_ST_pp7_stg2_fsm_33 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp7_it0) & (ap_const_lv1_0 == exitcond12_reg_5924)))) begin
reg_2197 <= b_q0;
end else if ((((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond3_reg_5195) & (ap_ST_pp1_stg2_fsm_6 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp5_it0) & (ap_const_lv1_0 == exitcond9_reg_5697) & (ap_ST_pp5_stg2_fsm_24 == ap_CS_fsm)))) begin
reg_2197 <= b_q1;
end
if ((((ap_const_logic_1 == ap_reg_ppiten_pp3_it0) & (ap_const_lv1_0 == exitcond6_reg_5446) & (ap_ST_pp3_stg3_fsm_16 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp7_it0) & (ap_const_lv1_0 == exitcond12_reg_5924) & (ap_ST_pp7_stg3_fsm_34 == ap_CS_fsm)))) begin
reg_2204 <= a_q0;
end else if ((((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond3_reg_5195) & (ap_ST_pp1_stg2_fsm_6 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp5_it0) & (ap_const_lv1_0 == exitcond9_reg_5697) & (ap_ST_pp5_stg2_fsm_24 == ap_CS_fsm)))) begin
reg_2204 <= a_q1;
end
if ((((ap_ST_pp3_stg2_fsm_15 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp3_it0) & (ap_const_lv1_0 == exitcond6_reg_5446)) | ((ap_ST_pp7_stg2_fsm_33 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp7_it0) & (ap_const_lv1_0 == exitcond12_reg_5924)))) begin
reg_2211 <= b_q1;
end else if ((((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond3_reg_5195) & (ap_ST_pp1_stg3_fsm_7 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp5_it0) & (ap_const_lv1_0 == exitcond9_reg_5697) & (ap_ST_pp5_stg3_fsm_25 == ap_CS_fsm)))) begin
reg_2211 <= b_q0;
end
if ((((ap_const_logic_1 == ap_reg_ppiten_pp3_it0) & (ap_const_lv1_0 == exitcond6_reg_5446) & (ap_ST_pp3_stg3_fsm_16 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp7_it0) & (ap_const_lv1_0 == exitcond12_reg_5924) & (ap_ST_pp7_stg3_fsm_34 == ap_CS_fsm)))) begin
reg_2218 <= a_q1;
end else if ((((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond3_reg_5195) & (ap_ST_pp1_stg3_fsm_7 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp5_it0) & (ap_const_lv1_0 == exitcond9_reg_5697) & (ap_ST_pp5_stg3_fsm_25 == ap_CS_fsm)))) begin
reg_2218 <= a_q0;
end
if ((((ap_const_logic_1 == ap_reg_ppiten_pp3_it0) & (ap_const_lv1_0 == exitcond6_reg_5446) & (ap_ST_pp3_stg3_fsm_16 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp7_it0) & (ap_const_lv1_0 == exitcond12_reg_5924) & (ap_ST_pp7_stg3_fsm_34 == ap_CS_fsm)))) begin
reg_2225 <= b_q0;
end else if ((((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond3_reg_5195) & (ap_ST_pp1_stg3_fsm_7 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp5_it0) & (ap_const_lv1_0 == exitcond9_reg_5697) & (ap_ST_pp5_stg3_fsm_25 == ap_CS_fsm)))) begin
reg_2225 <= b_q1;
end
if ((((ap_const_logic_1 == ap_reg_ppiten_pp3_it0) & (ap_const_lv1_0 == exitcond6_reg_5446) & (ap_ST_pp3_stg4_fsm_17 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp7_it0) & (ap_const_lv1_0 == exitcond12_reg_5924) & (ap_ST_pp7_stg4_fsm_35 == ap_CS_fsm)))) begin
reg_2232 <= a_q0;
end else if ((((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond3_reg_5195) & (ap_ST_pp1_stg3_fsm_7 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp5_it0) & (ap_const_lv1_0 == exitcond9_reg_5697) & (ap_ST_pp5_stg3_fsm_25 == ap_CS_fsm)))) begin
reg_2232 <= a_q1;
end
if ((((ap_const_logic_1 == ap_reg_ppiten_pp3_it0) & (ap_const_lv1_0 == exitcond6_reg_5446) & (ap_ST_pp3_stg3_fsm_16 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp7_it0) & (ap_const_lv1_0 == exitcond12_reg_5924) & (ap_ST_pp7_stg3_fsm_34 == ap_CS_fsm)))) begin
reg_2239 <= b_q1;
end else if ((((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond3_reg_5195) & (ap_ST_pp1_stg4_fsm_8 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp5_it0) & (ap_const_lv1_0 == exitcond9_reg_5697) & (ap_ST_pp5_stg4_fsm_26 == ap_CS_fsm)))) begin
reg_2239 <= b_q0;
end
if ((((ap_const_logic_1 == ap_reg_ppiten_pp3_it0) & (ap_const_lv1_0 == exitcond6_reg_5446) & (ap_ST_pp3_stg4_fsm_17 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp7_it0) & (ap_const_lv1_0 == exitcond12_reg_5924) & (ap_ST_pp7_stg4_fsm_35 == ap_CS_fsm)))) begin
reg_2246 <= a_q1;
end else if ((((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond3_reg_5195) & (ap_ST_pp1_stg4_fsm_8 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp5_it0) & (ap_const_lv1_0 == exitcond9_reg_5697) & (ap_ST_pp5_stg4_fsm_26 == ap_CS_fsm)))) begin
reg_2246 <= a_q0;
end
if ((((ap_const_logic_1 == ap_reg_ppiten_pp3_it0) & (ap_const_lv1_0 == exitcond6_reg_5446) & (ap_ST_pp3_stg4_fsm_17 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp7_it0) & (ap_const_lv1_0 == exitcond12_reg_5924) & (ap_ST_pp7_stg4_fsm_35 == ap_CS_fsm)))) begin
reg_2253 <= b_q0;
end else if ((((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond3_reg_5195) & (ap_ST_pp1_stg4_fsm_8 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp5_it0) & (ap_const_lv1_0 == exitcond9_reg_5697) & (ap_ST_pp5_stg4_fsm_26 == ap_CS_fsm)))) begin
reg_2253 <= b_q1;
end
if ((((ap_const_logic_1 == ap_reg_ppiten_pp3_it1) & (ap_ST_pp3_stg4_fsm_17 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond6_reg_5446_pp3_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp7_it1) & (ap_ST_pp7_stg4_fsm_35 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond12_reg_5924_pp7_it1)))) begin
reg_2260 <= b_q1;
end else if ((((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond3_reg_5195) & (ap_ST_pp1_stg5_fsm_9 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp5_it0) & (ap_const_lv1_0 == exitcond9_reg_5697) & (ap_ST_pp5_stg5_fsm_27 == ap_CS_fsm)))) begin
reg_2260 <= b_q0;
end
if ((((ap_const_logic_1 == ap_reg_ppiten_pp3_it1) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond6_reg_5446_pp3_it1) & (ap_ST_pp3_stg5_fsm_18 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp7_it1) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond12_reg_5924_pp7_it1) & (ap_ST_pp7_stg5_fsm_36 == ap_CS_fsm)))) begin
reg_2267 <= b_q0;
end else if ((((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond3_reg_5195) & (ap_ST_pp1_stg5_fsm_9 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp5_it0) & (ap_const_lv1_0 == exitcond9_reg_5697) & (ap_ST_pp5_stg5_fsm_27 == ap_CS_fsm)))) begin
reg_2267 <= b_q1;
end
if ((((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond3_reg_5195) & (ap_ST_pp1_stg7_fsm_11 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp3_it0) & (ap_const_lv1_0 == exitcond6_reg_5446) & (ap_ST_pp3_stg7_fsm_20 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp5_it0) & (ap_const_lv1_0 == exitcond9_reg_5697) & (ap_ST_pp5_stg7_fsm_29 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp7_it0) & (ap_const_lv1_0 == exitcond12_reg_5924) & (ap_ST_pp7_stg7_fsm_38 == ap_CS_fsm)))) begin
reg_2274 <= grp_fu_2167_p2;
end
if ((((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_const_lv1_0 == exitcond3_reg_5195) & (ap_ST_pp1_stg0_fsm_4 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp3_it1) & (ap_const_lv1_0 == exitcond6_reg_5446) & (ap_ST_pp3_stg0_fsm_13 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp5_it1) & (ap_const_lv1_0 == exitcond9_reg_5697) & (ap_ST_pp5_stg0_fsm_22 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp7_it1) & (ap_const_lv1_0 == exitcond12_reg_5924) & (ap_ST_pp7_stg0_fsm_31 == ap_CS_fsm)))) begin
reg_2279 <= grp_fu_2167_p2;
end
if ((((ap_ST_pp1_stg1_fsm_5 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond3_reg_5195_pp1_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp3_it1) & (ap_ST_pp3_stg1_fsm_14 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond6_reg_5446_pp3_it1)) | ((ap_ST_pp5_stg1_fsm_23 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp5_it1) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond9_reg_5697_pp5_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp7_it1) & (ap_ST_pp7_stg1_fsm_32 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond12_reg_5924_pp7_it1)))) begin
reg_2284 <= grp_fu_2167_p2;
end
if ((((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_ST_pp1_stg2_fsm_6 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond3_reg_5195_pp1_it1)) | ((ap_ST_pp3_stg2_fsm_15 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp3_it1) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond6_reg_5446_pp3_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp5_it1) & (ap_ST_pp5_stg2_fsm_24 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond9_reg_5697_pp5_it1)) | ((ap_ST_pp7_stg2_fsm_33 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp7_it1) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond12_reg_5924_pp7_it1)))) begin
reg_2289 <= grp_fu_2167_p2;
end
if ((((ap_const_logic_1 == ap_reg_ppiten_pp3_it1) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond6_reg_5446_pp3_it1) & (ap_ST_pp3_stg5_fsm_18 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp7_it1) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond12_reg_5924_pp7_it1) & (ap_ST_pp7_stg5_fsm_36 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_ST_pp1_stg3_fsm_7 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond3_reg_5195_pp1_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_ST_pp1_stg5_fsm_9 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond3_reg_5195_pp1_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_ST_pp1_stg6_fsm_10 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond3_reg_5195_pp1_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_ST_pp1_stg7_fsm_11 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond3_reg_5195_pp1_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp3_it1) & (ap_ST_pp3_stg3_fsm_16 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond6_reg_5446_pp3_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp3_it1) & (ap_ST_pp3_stg6_fsm_19 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond6_reg_5446_pp3_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp3_it1) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond6_reg_5446_pp3_it1) & (ap_ST_pp3_stg7_fsm_20 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp5_it1) & (ap_ST_pp5_stg3_fsm_25 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond9_reg_5697_pp5_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp5_it1) & (ap_ST_pp5_stg5_fsm_27 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond9_reg_5697_pp5_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp5_it1) & (ap_ST_pp5_stg6_fsm_28 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond9_reg_5697_pp5_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp5_it1) & (ap_ST_pp5_stg7_fsm_29 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond9_reg_5697_pp5_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp7_it1) & (ap_ST_pp7_stg3_fsm_34 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond12_reg_5924_pp7_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp7_it1) & (ap_ST_pp7_stg6_fsm_37 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond12_reg_5924_pp7_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp7_it1) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond12_reg_5924_pp7_it1) & (ap_ST_pp7_stg7_fsm_38 == ap_CS_fsm)))) begin
reg_2294 <= grp_fu_2163_p2;
end
if ((((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_ST_pp1_stg3_fsm_7 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond3_reg_5195_pp1_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp3_it1) & (ap_ST_pp3_stg3_fsm_16 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond6_reg_5446_pp3_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp5_it1) & (ap_ST_pp5_stg3_fsm_25 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond9_reg_5697_pp5_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp7_it1) & (ap_ST_pp7_stg3_fsm_34 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond12_reg_5924_pp7_it1)))) begin
reg_2300 <= grp_fu_2167_p2;
end
if ((((ap_const_logic_1 == ap_reg_ppiten_pp3_it1) & (ap_ST_pp3_stg4_fsm_17 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond6_reg_5446_pp3_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp7_it1) & (ap_ST_pp7_stg4_fsm_35 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond12_reg_5924_pp7_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_ST_pp1_stg4_fsm_8 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond3_reg_5195_pp1_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp5_it1) & (ap_ST_pp5_stg4_fsm_26 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond9_reg_5697_pp5_it1)))) begin
reg_2305 <= grp_fu_2163_p2;
end
if ((((ap_const_logic_1 == ap_reg_ppiten_pp3_it0) & (ap_const_lv1_0 == exitcond6_reg_5446) & (ap_ST_pp3_stg5_fsm_18 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp7_it0) & (ap_const_lv1_0 == exitcond12_reg_5924) & (ap_ST_pp7_stg5_fsm_36 == ap_CS_fsm)))) begin
reg_2311 <= a_q0;
end else if ((((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_ST_pp1_stg4_fsm_8 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond3_reg_5195_pp1_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp5_it1) & (ap_ST_pp5_stg4_fsm_26 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond9_reg_5697_pp5_it1)))) begin
reg_2311 <= a_q1;
end
if ((((ap_const_logic_1 == ap_reg_ppiten_pp3_it1) & (ap_ST_pp3_stg4_fsm_17 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond6_reg_5446_pp3_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp7_it1) & (ap_ST_pp7_stg4_fsm_35 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond12_reg_5924_pp7_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_ST_pp1_stg4_fsm_8 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond3_reg_5195_pp1_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp5_it1) & (ap_ST_pp5_stg4_fsm_26 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond9_reg_5697_pp5_it1)))) begin
reg_2318 <= grp_fu_2167_p2;
end
if ((((ap_const_logic_1 == ap_reg_ppiten_pp3_it0) & (ap_const_lv1_0 == exitcond6_reg_5446) & (ap_ST_pp3_stg5_fsm_18 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp7_it0) & (ap_const_lv1_0 == exitcond12_reg_5924) & (ap_ST_pp7_stg5_fsm_36 == ap_CS_fsm)))) begin
reg_2323 <= a_q1;
end else if ((((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_ST_pp1_stg5_fsm_9 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond3_reg_5195_pp1_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp5_it1) & (ap_ST_pp5_stg5_fsm_27 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond9_reg_5697_pp5_it1)))) begin
reg_2323 <= a_q0;
end
if ((((ap_const_logic_1 == ap_reg_ppiten_pp3_it1) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond6_reg_5446_pp3_it1) & (ap_ST_pp3_stg5_fsm_18 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp7_it1) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond12_reg_5924_pp7_it1) & (ap_ST_pp7_stg5_fsm_36 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_ST_pp1_stg5_fsm_9 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond3_reg_5195_pp1_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp5_it1) & (ap_ST_pp5_stg5_fsm_27 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond9_reg_5697_pp5_it1)))) begin
reg_2330 <= grp_fu_2167_p2;
end
if ((((ap_const_logic_1 == ap_reg_ppiten_pp1_it2) & (ap_ST_pp1_stg0_fsm_4 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond3_reg_5195_pp1_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp3_it2) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond6_reg_5446_pp3_it1) & (ap_ST_pp3_stg0_fsm_13 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp5_it2) & (ap_ST_pp5_stg0_fsm_22 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond9_reg_5697_pp5_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp7_it2) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond12_reg_5924_pp7_it1) & (ap_ST_pp7_stg0_fsm_31 == ap_CS_fsm)))) begin
reg_2335 <= grp_fu_2163_p2;
end
if ((((ap_ST_pp1_stg1_fsm_5 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it2) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond3_reg_5195_pp1_it2)) | ((ap_const_logic_1 == ap_reg_ppiten_pp3_it2) & (ap_ST_pp3_stg1_fsm_14 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond6_reg_5446_pp3_it2)) | ((ap_ST_pp5_stg1_fsm_23 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp5_it2) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond9_reg_5697_pp5_it2)) | ((ap_const_logic_1 == ap_reg_ppiten_pp7_it2) & (ap_ST_pp7_stg1_fsm_32 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond12_reg_5924_pp7_it2)))) begin
reg_2341 <= grp_fu_2163_p2;
end
if ((((ap_const_logic_1 == ap_reg_ppiten_pp1_it2) & (ap_ST_pp1_stg2_fsm_6 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond3_reg_5195_pp1_it2)) | ((ap_ST_pp3_stg2_fsm_15 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp3_it2) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond6_reg_5446_pp3_it2)) | ((ap_const_logic_1 == ap_reg_ppiten_pp5_it2) & (ap_ST_pp5_stg2_fsm_24 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond9_reg_5697_pp5_it2)) | ((ap_ST_pp7_stg2_fsm_33 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp7_it2) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond12_reg_5924_pp7_it2)))) begin
reg_2347 <= grp_fu_2163_p2;
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp5_it0) & (ap_const_lv1_0 == exitcond9_reg_5697) & (ap_ST_pp5_stg2_fsm_24 == ap_CS_fsm))) begin
tmp_105_reg_5820[0] <= tmp_105_fu_3845_p2[0];
tmp_105_reg_5820[1] <= tmp_105_fu_3845_p2[1];
tmp_105_reg_5820[3] <= tmp_105_fu_3845_p2[3];
tmp_105_reg_5820[4] <= tmp_105_fu_3845_p2[4];
tmp_105_reg_5820[5] <= tmp_105_fu_3845_p2[5];
tmp_105_reg_5820[6] <= tmp_105_fu_3845_p2[6];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp3_it1) & (ap_ST_pp3_stg3_fsm_16 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond6_reg_5446_pp3_it1))) begin
tmp_106_reg_5658 <= {{50{b_addr23_reg_5633[13]}}, {b_addr23_reg_5633}};
end
if (((ap_ST_pp2_stg0_fsm_12 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp2_it0))) begin
tmp_10_reg_5431 <= (i_2_phi_fu_1945_p4 + ap_const_lv7_1);
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp5_it0) & (ap_const_lv1_0 == exitcond9_reg_5697) & (ap_ST_pp5_stg4_fsm_26 == ap_CS_fsm))) begin
tmp_113_reg_5855[0] <= tmp_113_fu_3910_p2[0];
tmp_113_reg_5855[3] <= tmp_113_fu_3910_p2[3];
tmp_113_reg_5855[4] <= tmp_113_fu_3910_p2[4];
tmp_113_reg_5855[5] <= tmp_113_fu_3910_p2[5];
tmp_113_reg_5855[6] <= tmp_113_fu_3910_p2[6];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp3_it1) & (ap_ST_pp3_stg4_fsm_17 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond6_reg_5446_pp3_it1))) begin
tmp_114_reg_5668 <= {{50{b_addr25_reg_5643[13]}}, {b_addr25_reg_5643}};
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp5_it0) & (ap_const_lv1_0 == exitcond9_reg_5697) & (ap_ST_pp5_stg4_fsm_26 == ap_CS_fsm))) begin
tmp_117_reg_5865[3] <= tmp_117_fu_3929_p2[3];
tmp_117_reg_5865[4] <= tmp_117_fu_3929_p2[4];
tmp_117_reg_5865[5] <= tmp_117_fu_3929_p2[5];
tmp_117_reg_5865[6] <= tmp_117_fu_3929_p2[6];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp5_it0) & (ap_const_lv1_0 == exitcond9_reg_5697) & (ap_ST_pp5_stg4_fsm_26 == ap_CS_fsm))) begin
tmp_121_reg_5875 <= (j_3_mid2_reg_5706 + ap_const_lv7_8);
end
if (((ap_ST_pp4_stg0_fsm_21 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp4_it0) & (ap_const_lv1_0 == exitcond7_fu_3609_p2))) begin
tmp_122_reg_5687[0] <= tmp_122_fu_3621_p1[0];
tmp_122_reg_5687[1] <= tmp_122_fu_3621_p1[1];
tmp_122_reg_5687[2] <= tmp_122_fu_3621_p1[2];
tmp_122_reg_5687[3] <= tmp_122_fu_3621_p1[3];
tmp_122_reg_5687[4] <= tmp_122_fu_3621_p1[4];
tmp_122_reg_5687[5] <= tmp_122_fu_3621_p1[5];
tmp_122_reg_5687[6] <= tmp_122_fu_3621_p1[6];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp5_it0) & (ap_ST_pp5_stg0_fsm_22 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond9_fu_3626_p2))) begin
tmp_125_reg_5740[0] <= tmp_125_fu_3694_p1[0];
tmp_125_reg_5740[1] <= tmp_125_fu_3694_p1[1];
tmp_125_reg_5740[2] <= tmp_125_fu_3694_p1[2];
tmp_125_reg_5740[3] <= tmp_125_fu_3694_p1[3];
tmp_125_reg_5740[4] <= tmp_125_fu_3694_p1[4];
tmp_125_reg_5740[5] <= tmp_125_fu_3694_p1[5];
tmp_125_reg_5740[6] <= tmp_125_fu_3694_p1[6];
tmp_125_reg_5740[7] <= tmp_125_fu_3694_p1[7];
tmp_125_reg_5740[8] <= tmp_125_fu_3694_p1[8];
tmp_125_reg_5740[9] <= tmp_125_fu_3694_p1[9];
tmp_125_reg_5740[10] <= tmp_125_fu_3694_p1[10];
tmp_125_reg_5740[11] <= tmp_125_fu_3694_p1[11];
tmp_125_reg_5740[12] <= tmp_125_fu_3694_p1[12];
tmp_125_reg_5740[13] <= tmp_125_fu_3694_p1[13];
end
if (((ap_ST_pp5_stg1_fsm_23 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp5_it0) & (ap_const_lv1_0 == exitcond9_reg_5697))) begin
tmp_130_reg_5770[1] <= tmp_130_fu_3764_p1[1];
tmp_130_reg_5770[2] <= tmp_130_fu_3764_p1[2];
tmp_130_reg_5770[3] <= tmp_130_fu_3764_p1[3];
tmp_130_reg_5770[4] <= tmp_130_fu_3764_p1[4];
tmp_130_reg_5770[5] <= tmp_130_fu_3764_p1[5];
tmp_130_reg_5770[6] <= tmp_130_fu_3764_p1[6];
tmp_130_reg_5770[7] <= tmp_130_fu_3764_p1[7];
tmp_130_reg_5770[8] <= tmp_130_fu_3764_p1[8];
tmp_130_reg_5770[9] <= tmp_130_fu_3764_p1[9];
tmp_130_reg_5770[10] <= tmp_130_fu_3764_p1[10];
tmp_130_reg_5770[11] <= tmp_130_fu_3764_p1[11];
tmp_130_reg_5770[12] <= tmp_130_fu_3764_p1[12];
tmp_130_reg_5770[13] <= tmp_130_fu_3764_p1[13];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp7_it0) & (ap_const_lv1_0 == exitcond12_reg_5924) & (ap_ST_pp7_stg1_fsm_32 == ap_CS_fsm))) begin
tmp_133_reg_6012[0] <= tmp_133_fu_4159_p2[0];
tmp_133_reg_6012[2] <= tmp_133_fu_4159_p2[2];
tmp_133_reg_6012[3] <= tmp_133_fu_4159_p2[3];
tmp_133_reg_6012[4] <= tmp_133_fu_4159_p2[4];
tmp_133_reg_6012[5] <= tmp_133_fu_4159_p2[5];
tmp_133_reg_6012[6] <= tmp_133_fu_4159_p2[6];
end
if (((ap_ST_pp5_stg1_fsm_23 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp5_it0) & (ap_const_lv1_0 == exitcond9_reg_5697))) begin
tmp_138_reg_5790[0] <= tmp_138_fu_3794_p1[0];
tmp_138_reg_5790[1] <= tmp_138_fu_3794_p1[1];
tmp_138_reg_5790[2] <= tmp_138_fu_3794_p1[2];
tmp_138_reg_5790[3] <= tmp_138_fu_3794_p1[3];
tmp_138_reg_5790[4] <= tmp_138_fu_3794_p1[4];
tmp_138_reg_5790[5] <= tmp_138_fu_3794_p1[5];
tmp_138_reg_5790[6] <= tmp_138_fu_3794_p1[6];
tmp_138_reg_5790[7] <= tmp_138_fu_3794_p1[7];
tmp_138_reg_5790[8] <= tmp_138_fu_3794_p1[8];
tmp_138_reg_5790[9] <= tmp_138_fu_3794_p1[9];
tmp_138_reg_5790[10] <= tmp_138_fu_3794_p1[10];
tmp_138_reg_5790[11] <= tmp_138_fu_3794_p1[11];
tmp_138_reg_5790[12] <= tmp_138_fu_3794_p1[12];
tmp_138_reg_5790[13] <= tmp_138_fu_3794_p1[13];
end
if (((ap_ST_pp7_stg2_fsm_33 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp7_it0) & (ap_const_lv1_0 == exitcond12_reg_5924))) begin
tmp_141_reg_6047[0] <= tmp_141_fu_4224_p2[0];
tmp_141_reg_6047[1] <= tmp_141_fu_4224_p2[1];
tmp_141_reg_6047[3] <= tmp_141_fu_4224_p2[3];
tmp_141_reg_6047[4] <= tmp_141_fu_4224_p2[4];
tmp_141_reg_6047[5] <= tmp_141_fu_4224_p2[5];
tmp_141_reg_6047[6] <= tmp_141_fu_4224_p2[6];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp5_it0) & (ap_const_lv1_0 == exitcond9_reg_5697) & (ap_ST_pp5_stg2_fsm_24 == ap_CS_fsm))) begin
tmp_146_reg_5805[2] <= tmp_146_fu_3830_p1[2];
tmp_146_reg_5805[3] <= tmp_146_fu_3830_p1[3];
tmp_146_reg_5805[4] <= tmp_146_fu_3830_p1[4];
tmp_146_reg_5805[5] <= tmp_146_fu_3830_p1[5];
tmp_146_reg_5805[6] <= tmp_146_fu_3830_p1[6];
tmp_146_reg_5805[7] <= tmp_146_fu_3830_p1[7];
tmp_146_reg_5805[8] <= tmp_146_fu_3830_p1[8];
tmp_146_reg_5805[9] <= tmp_146_fu_3830_p1[9];
tmp_146_reg_5805[10] <= tmp_146_fu_3830_p1[10];
tmp_146_reg_5805[11] <= tmp_146_fu_3830_p1[11];
tmp_146_reg_5805[12] <= tmp_146_fu_3830_p1[12];
tmp_146_reg_5805[13] <= tmp_146_fu_3830_p1[13];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp7_it0) & (ap_const_lv1_0 == exitcond12_reg_5924) & (ap_ST_pp7_stg4_fsm_35 == ap_CS_fsm))) begin
tmp_149_reg_6082[0] <= tmp_149_fu_4289_p2[0];
tmp_149_reg_6082[3] <= tmp_149_fu_4289_p2[3];
tmp_149_reg_6082[4] <= tmp_149_fu_4289_p2[4];
tmp_149_reg_6082[5] <= tmp_149_fu_4289_p2[5];
tmp_149_reg_6082[6] <= tmp_149_fu_4289_p2[6];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp7_it0) & (ap_const_lv1_0 == exitcond12_reg_5924) & (ap_ST_pp7_stg4_fsm_35 == ap_CS_fsm))) begin
tmp_153_reg_6092[3] <= tmp_153_fu_4308_p2[3];
tmp_153_reg_6092[4] <= tmp_153_fu_4308_p2[4];
tmp_153_reg_6092[5] <= tmp_153_fu_4308_p2[5];
tmp_153_reg_6092[6] <= tmp_153_fu_4308_p2[6];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp5_it0) & (ap_const_lv1_0 == exitcond9_reg_5697) & (ap_ST_pp5_stg2_fsm_24 == ap_CS_fsm))) begin
tmp_154_reg_5825[0] <= tmp_154_fu_3859_p1[0];
tmp_154_reg_5825[1] <= tmp_154_fu_3859_p1[1];
tmp_154_reg_5825[2] <= tmp_154_fu_3859_p1[2];
tmp_154_reg_5825[3] <= tmp_154_fu_3859_p1[3];
tmp_154_reg_5825[4] <= tmp_154_fu_3859_p1[4];
tmp_154_reg_5825[5] <= tmp_154_fu_3859_p1[5];
tmp_154_reg_5825[6] <= tmp_154_fu_3859_p1[6];
tmp_154_reg_5825[7] <= tmp_154_fu_3859_p1[7];
tmp_154_reg_5825[8] <= tmp_154_fu_3859_p1[8];
tmp_154_reg_5825[9] <= tmp_154_fu_3859_p1[9];
tmp_154_reg_5825[10] <= tmp_154_fu_3859_p1[10];
tmp_154_reg_5825[11] <= tmp_154_fu_3859_p1[11];
tmp_154_reg_5825[12] <= tmp_154_fu_3859_p1[12];
tmp_154_reg_5825[13] <= tmp_154_fu_3859_p1[13];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp7_it0) & (ap_const_lv1_0 == exitcond12_reg_5924) & (ap_ST_pp7_stg4_fsm_35 == ap_CS_fsm))) begin
tmp_157_reg_6102 <= (j_5_mid2_reg_5933 + ap_const_lv7_8);
end
if (((ap_ST_pp1_stg1_fsm_5 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond3_reg_5195))) begin
tmp_15_reg_5272[0] <= tmp_15_fu_2560_p1[0];
tmp_15_reg_5272[1] <= tmp_15_fu_2560_p1[1];
tmp_15_reg_5272[2] <= tmp_15_fu_2560_p1[2];
tmp_15_reg_5272[3] <= tmp_15_fu_2560_p1[3];
tmp_15_reg_5272[4] <= tmp_15_fu_2560_p1[4];
tmp_15_reg_5272[5] <= tmp_15_fu_2560_p1[5];
tmp_15_reg_5272[6] <= tmp_15_fu_2560_p1[6];
tmp_15_reg_5272[7] <= tmp_15_fu_2560_p1[7];
tmp_15_reg_5272[8] <= tmp_15_fu_2560_p1[8];
tmp_15_reg_5272[9] <= tmp_15_fu_2560_p1[9];
tmp_15_reg_5272[10] <= tmp_15_fu_2560_p1[10];
tmp_15_reg_5272[11] <= tmp_15_fu_2560_p1[11];
tmp_15_reg_5272[12] <= tmp_15_fu_2560_p1[12];
tmp_15_reg_5272[13] <= tmp_15_fu_2560_p1[13];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp5_it0) & (ap_const_lv1_0 == exitcond9_reg_5697) & (ap_ST_pp5_stg3_fsm_25 == ap_CS_fsm))) begin
tmp_160_reg_5840[1] <= tmp_160_fu_3895_p1[1];
tmp_160_reg_5840[2] <= tmp_160_fu_3895_p1[2];
tmp_160_reg_5840[3] <= tmp_160_fu_3895_p1[3];
tmp_160_reg_5840[4] <= tmp_160_fu_3895_p1[4];
tmp_160_reg_5840[5] <= tmp_160_fu_3895_p1[5];
tmp_160_reg_5840[6] <= tmp_160_fu_3895_p1[6];
tmp_160_reg_5840[7] <= tmp_160_fu_3895_p1[7];
tmp_160_reg_5840[8] <= tmp_160_fu_3895_p1[8];
tmp_160_reg_5840[9] <= tmp_160_fu_3895_p1[9];
tmp_160_reg_5840[10] <= tmp_160_fu_3895_p1[10];
tmp_160_reg_5840[11] <= tmp_160_fu_3895_p1[11];
tmp_160_reg_5840[12] <= tmp_160_fu_3895_p1[12];
tmp_160_reg_5840[13] <= tmp_160_fu_3895_p1[13];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp5_it1) & (ap_ST_pp5_stg3_fsm_25 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond9_reg_5697_pp5_it1))) begin
tmp_164_reg_5880[0] <= tmp_164_fu_3961_p1[0];
tmp_164_reg_5880[1] <= tmp_164_fu_3961_p1[1];
tmp_164_reg_5880[2] <= tmp_164_fu_3961_p1[2];
tmp_164_reg_5880[3] <= tmp_164_fu_3961_p1[3];
tmp_164_reg_5880[4] <= tmp_164_fu_3961_p1[4];
tmp_164_reg_5880[5] <= tmp_164_fu_3961_p1[5];
tmp_164_reg_5880[6] <= tmp_164_fu_3961_p1[6];
tmp_164_reg_5880[7] <= tmp_164_fu_3961_p1[7];
tmp_164_reg_5880[8] <= tmp_164_fu_3961_p1[8];
tmp_164_reg_5880[9] <= tmp_164_fu_3961_p1[9];
tmp_164_reg_5880[10] <= tmp_164_fu_3961_p1[10];
tmp_164_reg_5880[11] <= tmp_164_fu_3961_p1[11];
tmp_164_reg_5880[12] <= tmp_164_fu_3961_p1[12];
tmp_164_reg_5880[13] <= tmp_164_fu_3961_p1[13];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp5_it1) & (ap_ST_pp5_stg4_fsm_26 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond9_reg_5697_pp5_it1))) begin
tmp_168_reg_5895[3] <= tmp_168_fu_3974_p1[3];
tmp_168_reg_5895[4] <= tmp_168_fu_3974_p1[4];
tmp_168_reg_5895[5] <= tmp_168_fu_3974_p1[5];
tmp_168_reg_5895[6] <= tmp_168_fu_3974_p1[6];
tmp_168_reg_5895[7] <= tmp_168_fu_3974_p1[7];
tmp_168_reg_5895[8] <= tmp_168_fu_3974_p1[8];
tmp_168_reg_5895[9] <= tmp_168_fu_3974_p1[9];
tmp_168_reg_5895[10] <= tmp_168_fu_3974_p1[10];
tmp_168_reg_5895[11] <= tmp_168_fu_3974_p1[11];
tmp_168_reg_5895[12] <= tmp_168_fu_3974_p1[12];
tmp_168_reg_5895[13] <= tmp_168_fu_3974_p1[13];
end
if (((ap_ST_pp6_stg0_fsm_30 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp6_it0) & (ap_const_lv1_0 == exitcond10_fu_3978_p2))) begin
tmp_172_reg_5914[0] <= tmp_172_fu_4000_p1[0];
tmp_172_reg_5914[1] <= tmp_172_fu_4000_p1[1];
tmp_172_reg_5914[2] <= tmp_172_fu_4000_p1[2];
tmp_172_reg_5914[3] <= tmp_172_fu_4000_p1[3];
tmp_172_reg_5914[4] <= tmp_172_fu_4000_p1[4];
tmp_172_reg_5914[5] <= tmp_172_fu_4000_p1[5];
tmp_172_reg_5914[6] <= tmp_172_fu_4000_p1[6];
tmp_172_reg_5914[7] <= tmp_172_fu_4000_p1[7];
tmp_172_reg_5914[8] <= tmp_172_fu_4000_p1[8];
tmp_172_reg_5914[9] <= tmp_172_fu_4000_p1[9];
tmp_172_reg_5914[10] <= tmp_172_fu_4000_p1[10];
tmp_172_reg_5914[11] <= tmp_172_fu_4000_p1[11];
tmp_172_reg_5914[12] <= tmp_172_fu_4000_p1[12];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp7_it0) & (ap_ST_pp7_stg0_fsm_31 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond12_fu_4005_p2))) begin
tmp_174_reg_5967 <= {{50{b_addr37_fu_4067_p2[13]}}, {b_addr37_fu_4067_p2}};
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_ST_pp8_stg1_fsm_41 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond_reg_6132))) begin
tmp_176_trn_cast_reg_6191[1] <= tmp_176_trn_cast_fu_4445_p1[1];
tmp_176_trn_cast_reg_6191[2] <= tmp_176_trn_cast_fu_4445_p1[2];
tmp_176_trn_cast_reg_6191[3] <= tmp_176_trn_cast_fu_4445_p1[3];
tmp_176_trn_cast_reg_6191[4] <= tmp_176_trn_cast_fu_4445_p1[4];
tmp_176_trn_cast_reg_6191[5] <= tmp_176_trn_cast_fu_4445_p1[5];
tmp_176_trn_cast_reg_6191[6] <= tmp_176_trn_cast_fu_4445_p1[6];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp7_it0) & (ap_const_lv1_0 == exitcond12_reg_5924) & (ap_ST_pp7_stg1_fsm_32 == ap_CS_fsm))) begin
tmp_178_reg_5997[1] <= tmp_178_fu_4143_p1[1];
tmp_178_reg_5997[2] <= tmp_178_fu_4143_p1[2];
tmp_178_reg_5997[3] <= tmp_178_fu_4143_p1[3];
tmp_178_reg_5997[4] <= tmp_178_fu_4143_p1[4];
tmp_178_reg_5997[5] <= tmp_178_fu_4143_p1[5];
tmp_178_reg_5997[6] <= tmp_178_fu_4143_p1[6];
tmp_178_reg_5997[7] <= tmp_178_fu_4143_p1[7];
tmp_178_reg_5997[8] <= tmp_178_fu_4143_p1[8];
tmp_178_reg_5997[9] <= tmp_178_fu_4143_p1[9];
tmp_178_reg_5997[10] <= tmp_178_fu_4143_p1[10];
tmp_178_reg_5997[11] <= tmp_178_fu_4143_p1[11];
tmp_178_reg_5997[12] <= tmp_178_fu_4143_p1[12];
tmp_178_reg_5997[13] <= tmp_178_fu_4143_p1[13];
tmp_178_reg_5997[14] <= tmp_178_fu_4143_p1[14];
tmp_178_reg_5997[15] <= tmp_178_fu_4143_p1[15];
tmp_178_reg_5997[16] <= tmp_178_fu_4143_p1[16];
tmp_178_reg_5997[17] <= tmp_178_fu_4143_p1[17];
tmp_178_reg_5997[18] <= tmp_178_fu_4143_p1[18];
tmp_178_reg_5997[19] <= tmp_178_fu_4143_p1[19];
tmp_178_reg_5997[20] <= tmp_178_fu_4143_p1[20];
tmp_178_reg_5997[21] <= tmp_178_fu_4143_p1[21];
tmp_178_reg_5997[22] <= tmp_178_fu_4143_p1[22];
tmp_178_reg_5997[23] <= tmp_178_fu_4143_p1[23];
tmp_178_reg_5997[24] <= tmp_178_fu_4143_p1[24];
tmp_178_reg_5997[25] <= tmp_178_fu_4143_p1[25];
tmp_178_reg_5997[26] <= tmp_178_fu_4143_p1[26];
tmp_178_reg_5997[27] <= tmp_178_fu_4143_p1[27];
tmp_178_reg_5997[28] <= tmp_178_fu_4143_p1[28];
tmp_178_reg_5997[29] <= tmp_178_fu_4143_p1[29];
tmp_178_reg_5997[30] <= tmp_178_fu_4143_p1[30];
tmp_178_reg_5997[31] <= tmp_178_fu_4143_p1[31];
tmp_178_reg_5997[32] <= tmp_178_fu_4143_p1[32];
tmp_178_reg_5997[33] <= tmp_178_fu_4143_p1[33];
tmp_178_reg_5997[34] <= tmp_178_fu_4143_p1[34];
tmp_178_reg_5997[35] <= tmp_178_fu_4143_p1[35];
tmp_178_reg_5997[36] <= tmp_178_fu_4143_p1[36];
tmp_178_reg_5997[37] <= tmp_178_fu_4143_p1[37];
tmp_178_reg_5997[38] <= tmp_178_fu_4143_p1[38];
tmp_178_reg_5997[39] <= tmp_178_fu_4143_p1[39];
tmp_178_reg_5997[40] <= tmp_178_fu_4143_p1[40];
tmp_178_reg_5997[41] <= tmp_178_fu_4143_p1[41];
tmp_178_reg_5997[42] <= tmp_178_fu_4143_p1[42];
tmp_178_reg_5997[43] <= tmp_178_fu_4143_p1[43];
tmp_178_reg_5997[44] <= tmp_178_fu_4143_p1[44];
tmp_178_reg_5997[45] <= tmp_178_fu_4143_p1[45];
tmp_178_reg_5997[46] <= tmp_178_fu_4143_p1[46];
tmp_178_reg_5997[47] <= tmp_178_fu_4143_p1[47];
tmp_178_reg_5997[48] <= tmp_178_fu_4143_p1[48];
tmp_178_reg_5997[49] <= tmp_178_fu_4143_p1[49];
tmp_178_reg_5997[50] <= tmp_178_fu_4143_p1[50];
tmp_178_reg_5997[51] <= tmp_178_fu_4143_p1[51];
tmp_178_reg_5997[52] <= tmp_178_fu_4143_p1[52];
tmp_178_reg_5997[53] <= tmp_178_fu_4143_p1[53];
tmp_178_reg_5997[54] <= tmp_178_fu_4143_p1[54];
tmp_178_reg_5997[55] <= tmp_178_fu_4143_p1[55];
tmp_178_reg_5997[56] <= tmp_178_fu_4143_p1[56];
tmp_178_reg_5997[57] <= tmp_178_fu_4143_p1[57];
tmp_178_reg_5997[58] <= tmp_178_fu_4143_p1[58];
tmp_178_reg_5997[59] <= tmp_178_fu_4143_p1[59];
tmp_178_reg_5997[60] <= tmp_178_fu_4143_p1[60];
tmp_178_reg_5997[61] <= tmp_178_fu_4143_p1[61];
tmp_178_reg_5997[62] <= tmp_178_fu_4143_p1[62];
tmp_178_reg_5997[63] <= tmp_178_fu_4143_p1[63];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_ST_pp8_stg1_fsm_41 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond_reg_6132))) begin
tmp_178_trn_cast_reg_6212[0] <= tmp_178_trn_cast_fu_4464_p1[0];
tmp_178_trn_cast_reg_6212[2] <= tmp_178_trn_cast_fu_4464_p1[2];
tmp_178_trn_cast_reg_6212[3] <= tmp_178_trn_cast_fu_4464_p1[3];
tmp_178_trn_cast_reg_6212[4] <= tmp_178_trn_cast_fu_4464_p1[4];
tmp_178_trn_cast_reg_6212[5] <= tmp_178_trn_cast_fu_4464_p1[5];
tmp_178_trn_cast_reg_6212[6] <= tmp_178_trn_cast_fu_4464_p1[6];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg2_fsm_42 == ap_CS_fsm))) begin
tmp_180_trn_cast_reg_6233[2] <= tmp_180_trn_cast_fu_4483_p1[2];
tmp_180_trn_cast_reg_6233[3] <= tmp_180_trn_cast_fu_4483_p1[3];
tmp_180_trn_cast_reg_6233[4] <= tmp_180_trn_cast_fu_4483_p1[4];
tmp_180_trn_cast_reg_6233[5] <= tmp_180_trn_cast_fu_4483_p1[5];
tmp_180_trn_cast_reg_6233[6] <= tmp_180_trn_cast_fu_4483_p1[6];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp7_it0) & (ap_const_lv1_0 == exitcond12_reg_5924) & (ap_ST_pp7_stg1_fsm_32 == ap_CS_fsm))) begin
tmp_182_reg_6017 <= {{50{b_addr39_fu_4168_p2[13]}}, {b_addr39_fu_4168_p2}};
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg2_fsm_42 == ap_CS_fsm))) begin
tmp_182_trn_cast_reg_6254[0] <= tmp_182_trn_cast_fu_4502_p1[0];
tmp_182_trn_cast_reg_6254[1] <= tmp_182_trn_cast_fu_4502_p1[1];
tmp_182_trn_cast_reg_6254[3] <= tmp_182_trn_cast_fu_4502_p1[3];
tmp_182_trn_cast_reg_6254[4] <= tmp_182_trn_cast_fu_4502_p1[4];
tmp_182_trn_cast_reg_6254[5] <= tmp_182_trn_cast_fu_4502_p1[5];
tmp_182_trn_cast_reg_6254[6] <= tmp_182_trn_cast_fu_4502_p1[6];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg3_fsm_43 == ap_CS_fsm))) begin
tmp_184_trn_cast_reg_6275[1] <= tmp_184_trn_cast_fu_4521_p1[1];
tmp_184_trn_cast_reg_6275[3] <= tmp_184_trn_cast_fu_4521_p1[3];
tmp_184_trn_cast_reg_6275[4] <= tmp_184_trn_cast_fu_4521_p1[4];
tmp_184_trn_cast_reg_6275[5] <= tmp_184_trn_cast_fu_4521_p1[5];
tmp_184_trn_cast_reg_6275[6] <= tmp_184_trn_cast_fu_4521_p1[6];
end
if (((ap_ST_pp7_stg2_fsm_33 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp7_it0) & (ap_const_lv1_0 == exitcond12_reg_5924))) begin
tmp_186_reg_6032[2] <= tmp_186_fu_4209_p1[2];
tmp_186_reg_6032[3] <= tmp_186_fu_4209_p1[3];
tmp_186_reg_6032[4] <= tmp_186_fu_4209_p1[4];
tmp_186_reg_6032[5] <= tmp_186_fu_4209_p1[5];
tmp_186_reg_6032[6] <= tmp_186_fu_4209_p1[6];
tmp_186_reg_6032[7] <= tmp_186_fu_4209_p1[7];
tmp_186_reg_6032[8] <= tmp_186_fu_4209_p1[8];
tmp_186_reg_6032[9] <= tmp_186_fu_4209_p1[9];
tmp_186_reg_6032[10] <= tmp_186_fu_4209_p1[10];
tmp_186_reg_6032[11] <= tmp_186_fu_4209_p1[11];
tmp_186_reg_6032[12] <= tmp_186_fu_4209_p1[12];
tmp_186_reg_6032[13] <= tmp_186_fu_4209_p1[13];
tmp_186_reg_6032[14] <= tmp_186_fu_4209_p1[14];
tmp_186_reg_6032[15] <= tmp_186_fu_4209_p1[15];
tmp_186_reg_6032[16] <= tmp_186_fu_4209_p1[16];
tmp_186_reg_6032[17] <= tmp_186_fu_4209_p1[17];
tmp_186_reg_6032[18] <= tmp_186_fu_4209_p1[18];
tmp_186_reg_6032[19] <= tmp_186_fu_4209_p1[19];
tmp_186_reg_6032[20] <= tmp_186_fu_4209_p1[20];
tmp_186_reg_6032[21] <= tmp_186_fu_4209_p1[21];
tmp_186_reg_6032[22] <= tmp_186_fu_4209_p1[22];
tmp_186_reg_6032[23] <= tmp_186_fu_4209_p1[23];
tmp_186_reg_6032[24] <= tmp_186_fu_4209_p1[24];
tmp_186_reg_6032[25] <= tmp_186_fu_4209_p1[25];
tmp_186_reg_6032[26] <= tmp_186_fu_4209_p1[26];
tmp_186_reg_6032[27] <= tmp_186_fu_4209_p1[27];
tmp_186_reg_6032[28] <= tmp_186_fu_4209_p1[28];
tmp_186_reg_6032[29] <= tmp_186_fu_4209_p1[29];
tmp_186_reg_6032[30] <= tmp_186_fu_4209_p1[30];
tmp_186_reg_6032[31] <= tmp_186_fu_4209_p1[31];
tmp_186_reg_6032[32] <= tmp_186_fu_4209_p1[32];
tmp_186_reg_6032[33] <= tmp_186_fu_4209_p1[33];
tmp_186_reg_6032[34] <= tmp_186_fu_4209_p1[34];
tmp_186_reg_6032[35] <= tmp_186_fu_4209_p1[35];
tmp_186_reg_6032[36] <= tmp_186_fu_4209_p1[36];
tmp_186_reg_6032[37] <= tmp_186_fu_4209_p1[37];
tmp_186_reg_6032[38] <= tmp_186_fu_4209_p1[38];
tmp_186_reg_6032[39] <= tmp_186_fu_4209_p1[39];
tmp_186_reg_6032[40] <= tmp_186_fu_4209_p1[40];
tmp_186_reg_6032[41] <= tmp_186_fu_4209_p1[41];
tmp_186_reg_6032[42] <= tmp_186_fu_4209_p1[42];
tmp_186_reg_6032[43] <= tmp_186_fu_4209_p1[43];
tmp_186_reg_6032[44] <= tmp_186_fu_4209_p1[44];
tmp_186_reg_6032[45] <= tmp_186_fu_4209_p1[45];
tmp_186_reg_6032[46] <= tmp_186_fu_4209_p1[46];
tmp_186_reg_6032[47] <= tmp_186_fu_4209_p1[47];
tmp_186_reg_6032[48] <= tmp_186_fu_4209_p1[48];
tmp_186_reg_6032[49] <= tmp_186_fu_4209_p1[49];
tmp_186_reg_6032[50] <= tmp_186_fu_4209_p1[50];
tmp_186_reg_6032[51] <= tmp_186_fu_4209_p1[51];
tmp_186_reg_6032[52] <= tmp_186_fu_4209_p1[52];
tmp_186_reg_6032[53] <= tmp_186_fu_4209_p1[53];
tmp_186_reg_6032[54] <= tmp_186_fu_4209_p1[54];
tmp_186_reg_6032[55] <= tmp_186_fu_4209_p1[55];
tmp_186_reg_6032[56] <= tmp_186_fu_4209_p1[56];
tmp_186_reg_6032[57] <= tmp_186_fu_4209_p1[57];
tmp_186_reg_6032[58] <= tmp_186_fu_4209_p1[58];
tmp_186_reg_6032[59] <= tmp_186_fu_4209_p1[59];
tmp_186_reg_6032[60] <= tmp_186_fu_4209_p1[60];
tmp_186_reg_6032[61] <= tmp_186_fu_4209_p1[61];
tmp_186_reg_6032[62] <= tmp_186_fu_4209_p1[62];
tmp_186_reg_6032[63] <= tmp_186_fu_4209_p1[63];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg3_fsm_43 == ap_CS_fsm))) begin
tmp_186_trn_cast_reg_6296[0] <= tmp_186_trn_cast_fu_4540_p1[0];
tmp_186_trn_cast_reg_6296[3] <= tmp_186_trn_cast_fu_4540_p1[3];
tmp_186_trn_cast_reg_6296[4] <= tmp_186_trn_cast_fu_4540_p1[4];
tmp_186_trn_cast_reg_6296[5] <= tmp_186_trn_cast_fu_4540_p1[5];
tmp_186_trn_cast_reg_6296[6] <= tmp_186_trn_cast_fu_4540_p1[6];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg4_fsm_44 == ap_CS_fsm))) begin
tmp_188_trn_cast_reg_6317[3] <= tmp_188_trn_cast_fu_4564_p1[3];
tmp_188_trn_cast_reg_6317[4] <= tmp_188_trn_cast_fu_4564_p1[4];
tmp_188_trn_cast_reg_6317[5] <= tmp_188_trn_cast_fu_4564_p1[5];
tmp_188_trn_cast_reg_6317[6] <= tmp_188_trn_cast_fu_4564_p1[6];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg4_fsm_44 == ap_CS_fsm))) begin
tmp_189_reg_6358 <= (j_6_mid2_reg_6141 + ap_const_lv7_8);
end
if (((ap_ST_pp7_stg2_fsm_33 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp7_it0) & (ap_const_lv1_0 == exitcond12_reg_5924))) begin
tmp_190_reg_6052 <= {{50{b_addr41_fu_4233_p2[13]}}, {b_addr41_fu_4233_p2}};
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp7_it0) & (ap_const_lv1_0 == exitcond12_reg_5924) & (ap_ST_pp7_stg3_fsm_34 == ap_CS_fsm))) begin
tmp_192_reg_6067[1] <= tmp_192_fu_4274_p1[1];
tmp_192_reg_6067[2] <= tmp_192_fu_4274_p1[2];
tmp_192_reg_6067[3] <= tmp_192_fu_4274_p1[3];
tmp_192_reg_6067[4] <= tmp_192_fu_4274_p1[4];
tmp_192_reg_6067[5] <= tmp_192_fu_4274_p1[5];
tmp_192_reg_6067[6] <= tmp_192_fu_4274_p1[6];
tmp_192_reg_6067[7] <= tmp_192_fu_4274_p1[7];
tmp_192_reg_6067[8] <= tmp_192_fu_4274_p1[8];
tmp_192_reg_6067[9] <= tmp_192_fu_4274_p1[9];
tmp_192_reg_6067[10] <= tmp_192_fu_4274_p1[10];
tmp_192_reg_6067[11] <= tmp_192_fu_4274_p1[11];
tmp_192_reg_6067[12] <= tmp_192_fu_4274_p1[12];
tmp_192_reg_6067[13] <= tmp_192_fu_4274_p1[13];
tmp_192_reg_6067[14] <= tmp_192_fu_4274_p1[14];
tmp_192_reg_6067[15] <= tmp_192_fu_4274_p1[15];
tmp_192_reg_6067[16] <= tmp_192_fu_4274_p1[16];
tmp_192_reg_6067[17] <= tmp_192_fu_4274_p1[17];
tmp_192_reg_6067[18] <= tmp_192_fu_4274_p1[18];
tmp_192_reg_6067[19] <= tmp_192_fu_4274_p1[19];
tmp_192_reg_6067[20] <= tmp_192_fu_4274_p1[20];
tmp_192_reg_6067[21] <= tmp_192_fu_4274_p1[21];
tmp_192_reg_6067[22] <= tmp_192_fu_4274_p1[22];
tmp_192_reg_6067[23] <= tmp_192_fu_4274_p1[23];
tmp_192_reg_6067[24] <= tmp_192_fu_4274_p1[24];
tmp_192_reg_6067[25] <= tmp_192_fu_4274_p1[25];
tmp_192_reg_6067[26] <= tmp_192_fu_4274_p1[26];
tmp_192_reg_6067[27] <= tmp_192_fu_4274_p1[27];
tmp_192_reg_6067[28] <= tmp_192_fu_4274_p1[28];
tmp_192_reg_6067[29] <= tmp_192_fu_4274_p1[29];
tmp_192_reg_6067[30] <= tmp_192_fu_4274_p1[30];
tmp_192_reg_6067[31] <= tmp_192_fu_4274_p1[31];
tmp_192_reg_6067[32] <= tmp_192_fu_4274_p1[32];
tmp_192_reg_6067[33] <= tmp_192_fu_4274_p1[33];
tmp_192_reg_6067[34] <= tmp_192_fu_4274_p1[34];
tmp_192_reg_6067[35] <= tmp_192_fu_4274_p1[35];
tmp_192_reg_6067[36] <= tmp_192_fu_4274_p1[36];
tmp_192_reg_6067[37] <= tmp_192_fu_4274_p1[37];
tmp_192_reg_6067[38] <= tmp_192_fu_4274_p1[38];
tmp_192_reg_6067[39] <= tmp_192_fu_4274_p1[39];
tmp_192_reg_6067[40] <= tmp_192_fu_4274_p1[40];
tmp_192_reg_6067[41] <= tmp_192_fu_4274_p1[41];
tmp_192_reg_6067[42] <= tmp_192_fu_4274_p1[42];
tmp_192_reg_6067[43] <= tmp_192_fu_4274_p1[43];
tmp_192_reg_6067[44] <= tmp_192_fu_4274_p1[44];
tmp_192_reg_6067[45] <= tmp_192_fu_4274_p1[45];
tmp_192_reg_6067[46] <= tmp_192_fu_4274_p1[46];
tmp_192_reg_6067[47] <= tmp_192_fu_4274_p1[47];
tmp_192_reg_6067[48] <= tmp_192_fu_4274_p1[48];
tmp_192_reg_6067[49] <= tmp_192_fu_4274_p1[49];
tmp_192_reg_6067[50] <= tmp_192_fu_4274_p1[50];
tmp_192_reg_6067[51] <= tmp_192_fu_4274_p1[51];
tmp_192_reg_6067[52] <= tmp_192_fu_4274_p1[52];
tmp_192_reg_6067[53] <= tmp_192_fu_4274_p1[53];
tmp_192_reg_6067[54] <= tmp_192_fu_4274_p1[54];
tmp_192_reg_6067[55] <= tmp_192_fu_4274_p1[55];
tmp_192_reg_6067[56] <= tmp_192_fu_4274_p1[56];
tmp_192_reg_6067[57] <= tmp_192_fu_4274_p1[57];
tmp_192_reg_6067[58] <= tmp_192_fu_4274_p1[58];
tmp_192_reg_6067[59] <= tmp_192_fu_4274_p1[59];
tmp_192_reg_6067[60] <= tmp_192_fu_4274_p1[60];
tmp_192_reg_6067[61] <= tmp_192_fu_4274_p1[61];
tmp_192_reg_6067[62] <= tmp_192_fu_4274_p1[62];
tmp_192_reg_6067[63] <= tmp_192_fu_4274_p1[63];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp7_it1) & (ap_ST_pp7_stg3_fsm_34 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond12_reg_5924_pp7_it1))) begin
tmp_194_reg_6107 <= {{50{b_addr43_fu_4335_p2[13]}}, {b_addr43_fu_4335_p2}};
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp7_it1) & (ap_ST_pp7_stg4_fsm_35 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond12_reg_5924_pp7_it1))) begin
tmp_197_reg_6122[3] <= tmp_197_fu_4353_p1[3];
tmp_197_reg_6122[4] <= tmp_197_fu_4353_p1[4];
tmp_197_reg_6122[5] <= tmp_197_fu_4353_p1[5];
tmp_197_reg_6122[6] <= tmp_197_fu_4353_p1[6];
tmp_197_reg_6122[7] <= tmp_197_fu_4353_p1[7];
tmp_197_reg_6122[8] <= tmp_197_fu_4353_p1[8];
tmp_197_reg_6122[9] <= tmp_197_fu_4353_p1[9];
tmp_197_reg_6122[10] <= tmp_197_fu_4353_p1[10];
tmp_197_reg_6122[11] <= tmp_197_fu_4353_p1[11];
tmp_197_reg_6122[12] <= tmp_197_fu_4353_p1[12];
tmp_197_reg_6122[13] <= tmp_197_fu_4353_p1[13];
tmp_197_reg_6122[14] <= tmp_197_fu_4353_p1[14];
tmp_197_reg_6122[15] <= tmp_197_fu_4353_p1[15];
tmp_197_reg_6122[16] <= tmp_197_fu_4353_p1[16];
tmp_197_reg_6122[17] <= tmp_197_fu_4353_p1[17];
tmp_197_reg_6122[18] <= tmp_197_fu_4353_p1[18];
tmp_197_reg_6122[19] <= tmp_197_fu_4353_p1[19];
tmp_197_reg_6122[20] <= tmp_197_fu_4353_p1[20];
tmp_197_reg_6122[21] <= tmp_197_fu_4353_p1[21];
tmp_197_reg_6122[22] <= tmp_197_fu_4353_p1[22];
tmp_197_reg_6122[23] <= tmp_197_fu_4353_p1[23];
tmp_197_reg_6122[24] <= tmp_197_fu_4353_p1[24];
tmp_197_reg_6122[25] <= tmp_197_fu_4353_p1[25];
tmp_197_reg_6122[26] <= tmp_197_fu_4353_p1[26];
tmp_197_reg_6122[27] <= tmp_197_fu_4353_p1[27];
tmp_197_reg_6122[28] <= tmp_197_fu_4353_p1[28];
tmp_197_reg_6122[29] <= tmp_197_fu_4353_p1[29];
tmp_197_reg_6122[30] <= tmp_197_fu_4353_p1[30];
tmp_197_reg_6122[31] <= tmp_197_fu_4353_p1[31];
tmp_197_reg_6122[32] <= tmp_197_fu_4353_p1[32];
tmp_197_reg_6122[33] <= tmp_197_fu_4353_p1[33];
tmp_197_reg_6122[34] <= tmp_197_fu_4353_p1[34];
tmp_197_reg_6122[35] <= tmp_197_fu_4353_p1[35];
tmp_197_reg_6122[36] <= tmp_197_fu_4353_p1[36];
tmp_197_reg_6122[37] <= tmp_197_fu_4353_p1[37];
tmp_197_reg_6122[38] <= tmp_197_fu_4353_p1[38];
tmp_197_reg_6122[39] <= tmp_197_fu_4353_p1[39];
tmp_197_reg_6122[40] <= tmp_197_fu_4353_p1[40];
tmp_197_reg_6122[41] <= tmp_197_fu_4353_p1[41];
tmp_197_reg_6122[42] <= tmp_197_fu_4353_p1[42];
tmp_197_reg_6122[43] <= tmp_197_fu_4353_p1[43];
tmp_197_reg_6122[44] <= tmp_197_fu_4353_p1[44];
tmp_197_reg_6122[45] <= tmp_197_fu_4353_p1[45];
tmp_197_reg_6122[46] <= tmp_197_fu_4353_p1[46];
tmp_197_reg_6122[47] <= tmp_197_fu_4353_p1[47];
tmp_197_reg_6122[48] <= tmp_197_fu_4353_p1[48];
tmp_197_reg_6122[49] <= tmp_197_fu_4353_p1[49];
tmp_197_reg_6122[50] <= tmp_197_fu_4353_p1[50];
tmp_197_reg_6122[51] <= tmp_197_fu_4353_p1[51];
tmp_197_reg_6122[52] <= tmp_197_fu_4353_p1[52];
tmp_197_reg_6122[53] <= tmp_197_fu_4353_p1[53];
tmp_197_reg_6122[54] <= tmp_197_fu_4353_p1[54];
tmp_197_reg_6122[55] <= tmp_197_fu_4353_p1[55];
tmp_197_reg_6122[56] <= tmp_197_fu_4353_p1[56];
tmp_197_reg_6122[57] <= tmp_197_fu_4353_p1[57];
tmp_197_reg_6122[58] <= tmp_197_fu_4353_p1[58];
tmp_197_reg_6122[59] <= tmp_197_fu_4353_p1[59];
tmp_197_reg_6122[60] <= tmp_197_fu_4353_p1[60];
tmp_197_reg_6122[61] <= tmp_197_fu_4353_p1[61];
tmp_197_reg_6122[62] <= tmp_197_fu_4353_p1[62];
tmp_197_reg_6122[63] <= tmp_197_fu_4353_p1[63];
end
if (((ap_ST_pp8_stg0_fsm_40 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_fu_4357_p2))) begin
tmp_199_reg_6176[0] <= tmp_199_fu_4421_p1[0];
tmp_199_reg_6176[1] <= tmp_199_fu_4421_p1[1];
tmp_199_reg_6176[2] <= tmp_199_fu_4421_p1[2];
tmp_199_reg_6176[3] <= tmp_199_fu_4421_p1[3];
tmp_199_reg_6176[4] <= tmp_199_fu_4421_p1[4];
tmp_199_reg_6176[5] <= tmp_199_fu_4421_p1[5];
tmp_199_reg_6176[6] <= tmp_199_fu_4421_p1[6];
tmp_199_reg_6176[7] <= tmp_199_fu_4421_p1[7];
tmp_199_reg_6176[8] <= tmp_199_fu_4421_p1[8];
tmp_199_reg_6176[9] <= tmp_199_fu_4421_p1[9];
tmp_199_reg_6176[10] <= tmp_199_fu_4421_p1[10];
tmp_199_reg_6176[11] <= tmp_199_fu_4421_p1[11];
tmp_199_reg_6176[12] <= tmp_199_fu_4421_p1[12];
tmp_199_reg_6176[13] <= tmp_199_fu_4421_p1[13];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_ST_pp8_stg1_fsm_41 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond_reg_6132))) begin
tmp_200_reg_6202[1] <= tmp_200_fu_4454_p1[1];
tmp_200_reg_6202[2] <= tmp_200_fu_4454_p1[2];
tmp_200_reg_6202[3] <= tmp_200_fu_4454_p1[3];
tmp_200_reg_6202[4] <= tmp_200_fu_4454_p1[4];
tmp_200_reg_6202[5] <= tmp_200_fu_4454_p1[5];
tmp_200_reg_6202[6] <= tmp_200_fu_4454_p1[6];
tmp_200_reg_6202[7] <= tmp_200_fu_4454_p1[7];
tmp_200_reg_6202[8] <= tmp_200_fu_4454_p1[8];
tmp_200_reg_6202[9] <= tmp_200_fu_4454_p1[9];
tmp_200_reg_6202[10] <= tmp_200_fu_4454_p1[10];
tmp_200_reg_6202[11] <= tmp_200_fu_4454_p1[11];
tmp_200_reg_6202[12] <= tmp_200_fu_4454_p1[12];
tmp_200_reg_6202[13] <= tmp_200_fu_4454_p1[13];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_ST_pp8_stg1_fsm_41 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond_reg_6132))) begin
tmp_201_reg_6223[0] <= tmp_201_fu_4473_p1[0];
tmp_201_reg_6223[1] <= tmp_201_fu_4473_p1[1];
tmp_201_reg_6223[2] <= tmp_201_fu_4473_p1[2];
tmp_201_reg_6223[3] <= tmp_201_fu_4473_p1[3];
tmp_201_reg_6223[4] <= tmp_201_fu_4473_p1[4];
tmp_201_reg_6223[5] <= tmp_201_fu_4473_p1[5];
tmp_201_reg_6223[6] <= tmp_201_fu_4473_p1[6];
tmp_201_reg_6223[7] <= tmp_201_fu_4473_p1[7];
tmp_201_reg_6223[8] <= tmp_201_fu_4473_p1[8];
tmp_201_reg_6223[9] <= tmp_201_fu_4473_p1[9];
tmp_201_reg_6223[10] <= tmp_201_fu_4473_p1[10];
tmp_201_reg_6223[11] <= tmp_201_fu_4473_p1[11];
tmp_201_reg_6223[12] <= tmp_201_fu_4473_p1[12];
tmp_201_reg_6223[13] <= tmp_201_fu_4473_p1[13];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg2_fsm_42 == ap_CS_fsm))) begin
tmp_202_reg_6244[2] <= tmp_202_fu_4492_p1[2];
tmp_202_reg_6244[3] <= tmp_202_fu_4492_p1[3];
tmp_202_reg_6244[4] <= tmp_202_fu_4492_p1[4];
tmp_202_reg_6244[5] <= tmp_202_fu_4492_p1[5];
tmp_202_reg_6244[6] <= tmp_202_fu_4492_p1[6];
tmp_202_reg_6244[7] <= tmp_202_fu_4492_p1[7];
tmp_202_reg_6244[8] <= tmp_202_fu_4492_p1[8];
tmp_202_reg_6244[9] <= tmp_202_fu_4492_p1[9];
tmp_202_reg_6244[10] <= tmp_202_fu_4492_p1[10];
tmp_202_reg_6244[11] <= tmp_202_fu_4492_p1[11];
tmp_202_reg_6244[12] <= tmp_202_fu_4492_p1[12];
tmp_202_reg_6244[13] <= tmp_202_fu_4492_p1[13];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg2_fsm_42 == ap_CS_fsm))) begin
tmp_203_reg_6265[0] <= tmp_203_fu_4511_p1[0];
tmp_203_reg_6265[1] <= tmp_203_fu_4511_p1[1];
tmp_203_reg_6265[2] <= tmp_203_fu_4511_p1[2];
tmp_203_reg_6265[3] <= tmp_203_fu_4511_p1[3];
tmp_203_reg_6265[4] <= tmp_203_fu_4511_p1[4];
tmp_203_reg_6265[5] <= tmp_203_fu_4511_p1[5];
tmp_203_reg_6265[6] <= tmp_203_fu_4511_p1[6];
tmp_203_reg_6265[7] <= tmp_203_fu_4511_p1[7];
tmp_203_reg_6265[8] <= tmp_203_fu_4511_p1[8];
tmp_203_reg_6265[9] <= tmp_203_fu_4511_p1[9];
tmp_203_reg_6265[10] <= tmp_203_fu_4511_p1[10];
tmp_203_reg_6265[11] <= tmp_203_fu_4511_p1[11];
tmp_203_reg_6265[12] <= tmp_203_fu_4511_p1[12];
tmp_203_reg_6265[13] <= tmp_203_fu_4511_p1[13];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg3_fsm_43 == ap_CS_fsm))) begin
tmp_204_reg_6286[1] <= tmp_204_fu_4530_p1[1];
tmp_204_reg_6286[2] <= tmp_204_fu_4530_p1[2];
tmp_204_reg_6286[3] <= tmp_204_fu_4530_p1[3];
tmp_204_reg_6286[4] <= tmp_204_fu_4530_p1[4];
tmp_204_reg_6286[5] <= tmp_204_fu_4530_p1[5];
tmp_204_reg_6286[6] <= tmp_204_fu_4530_p1[6];
tmp_204_reg_6286[7] <= tmp_204_fu_4530_p1[7];
tmp_204_reg_6286[8] <= tmp_204_fu_4530_p1[8];
tmp_204_reg_6286[9] <= tmp_204_fu_4530_p1[9];
tmp_204_reg_6286[10] <= tmp_204_fu_4530_p1[10];
tmp_204_reg_6286[11] <= tmp_204_fu_4530_p1[11];
tmp_204_reg_6286[12] <= tmp_204_fu_4530_p1[12];
tmp_204_reg_6286[13] <= tmp_204_fu_4530_p1[13];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg3_fsm_43 == ap_CS_fsm))) begin
tmp_205_reg_6307[0] <= tmp_205_fu_4549_p1[0];
tmp_205_reg_6307[1] <= tmp_205_fu_4549_p1[1];
tmp_205_reg_6307[2] <= tmp_205_fu_4549_p1[2];
tmp_205_reg_6307[3] <= tmp_205_fu_4549_p1[3];
tmp_205_reg_6307[4] <= tmp_205_fu_4549_p1[4];
tmp_205_reg_6307[5] <= tmp_205_fu_4549_p1[5];
tmp_205_reg_6307[6] <= tmp_205_fu_4549_p1[6];
tmp_205_reg_6307[7] <= tmp_205_fu_4549_p1[7];
tmp_205_reg_6307[8] <= tmp_205_fu_4549_p1[8];
tmp_205_reg_6307[9] <= tmp_205_fu_4549_p1[9];
tmp_205_reg_6307[10] <= tmp_205_fu_4549_p1[10];
tmp_205_reg_6307[11] <= tmp_205_fu_4549_p1[11];
tmp_205_reg_6307[12] <= tmp_205_fu_4549_p1[12];
tmp_205_reg_6307[13] <= tmp_205_fu_4549_p1[13];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg4_fsm_44 == ap_CS_fsm))) begin
tmp_206_reg_6328[3] <= tmp_206_fu_4573_p1[3];
tmp_206_reg_6328[4] <= tmp_206_fu_4573_p1[4];
tmp_206_reg_6328[5] <= tmp_206_fu_4573_p1[5];
tmp_206_reg_6328[6] <= tmp_206_fu_4573_p1[6];
tmp_206_reg_6328[7] <= tmp_206_fu_4573_p1[7];
tmp_206_reg_6328[8] <= tmp_206_fu_4573_p1[8];
tmp_206_reg_6328[9] <= tmp_206_fu_4573_p1[9];
tmp_206_reg_6328[10] <= tmp_206_fu_4573_p1[10];
tmp_206_reg_6328[11] <= tmp_206_fu_4573_p1[11];
tmp_206_reg_6328[12] <= tmp_206_fu_4573_p1[12];
tmp_206_reg_6328[13] <= tmp_206_fu_4573_p1[13];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg4_fsm_44 == ap_CS_fsm))) begin
tmp_207_reg_6348[1] <= tmp_207_fu_4597_p1[1];
tmp_207_reg_6348[2] <= tmp_207_fu_4597_p1[2];
tmp_207_reg_6348[3] <= tmp_207_fu_4597_p1[3];
tmp_207_reg_6348[4] <= tmp_207_fu_4597_p1[4];
tmp_207_reg_6348[5] <= tmp_207_fu_4597_p1[5];
tmp_207_reg_6348[6] <= tmp_207_fu_4597_p1[6];
tmp_207_reg_6348[7] <= tmp_207_fu_4597_p1[7];
tmp_207_reg_6348[8] <= tmp_207_fu_4597_p1[8];
tmp_207_reg_6348[9] <= tmp_207_fu_4597_p1[9];
tmp_207_reg_6348[10] <= tmp_207_fu_4597_p1[10];
tmp_207_reg_6348[11] <= tmp_207_fu_4597_p1[11];
tmp_207_reg_6348[12] <= tmp_207_fu_4597_p1[12];
tmp_207_reg_6348[13] <= tmp_207_fu_4597_p1[13];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg5_fsm_45 == ap_CS_fsm))) begin
tmp_208_reg_6363[0] <= tmp_208_fu_4611_p1[0];
tmp_208_reg_6363[1] <= tmp_208_fu_4611_p1[1];
tmp_208_reg_6363[2] <= tmp_208_fu_4611_p1[2];
tmp_208_reg_6363[3] <= tmp_208_fu_4611_p1[3];
tmp_208_reg_6363[4] <= tmp_208_fu_4611_p1[4];
tmp_208_reg_6363[5] <= tmp_208_fu_4611_p1[5];
tmp_208_reg_6363[6] <= tmp_208_fu_4611_p1[6];
tmp_208_reg_6363[7] <= tmp_208_fu_4611_p1[7];
tmp_208_reg_6363[8] <= tmp_208_fu_4611_p1[8];
tmp_208_reg_6363[9] <= tmp_208_fu_4611_p1[9];
tmp_208_reg_6363[10] <= tmp_208_fu_4611_p1[10];
tmp_208_reg_6363[11] <= tmp_208_fu_4611_p1[11];
tmp_208_reg_6363[12] <= tmp_208_fu_4611_p1[12];
tmp_208_reg_6363[13] <= tmp_208_fu_4611_p1[13];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg5_fsm_45 == ap_CS_fsm))) begin
tmp_209_reg_6373[2] <= tmp_209_fu_4620_p1[2];
tmp_209_reg_6373[3] <= tmp_209_fu_4620_p1[3];
tmp_209_reg_6373[4] <= tmp_209_fu_4620_p1[4];
tmp_209_reg_6373[5] <= tmp_209_fu_4620_p1[5];
tmp_209_reg_6373[6] <= tmp_209_fu_4620_p1[6];
tmp_209_reg_6373[7] <= tmp_209_fu_4620_p1[7];
tmp_209_reg_6373[8] <= tmp_209_fu_4620_p1[8];
tmp_209_reg_6373[9] <= tmp_209_fu_4620_p1[9];
tmp_209_reg_6373[10] <= tmp_209_fu_4620_p1[10];
tmp_209_reg_6373[11] <= tmp_209_fu_4620_p1[11];
tmp_209_reg_6373[12] <= tmp_209_fu_4620_p1[12];
tmp_209_reg_6373[13] <= tmp_209_fu_4620_p1[13];
end
if (((ap_ST_pp1_stg1_fsm_5 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond3_reg_5195))) begin
tmp_20_reg_5287[0] <= tmp_20_fu_2626_p1[0];
tmp_20_reg_5287[1] <= tmp_20_fu_2626_p1[1];
tmp_20_reg_5287[2] <= tmp_20_fu_2626_p1[2];
tmp_20_reg_5287[3] <= tmp_20_fu_2626_p1[3];
tmp_20_reg_5287[4] <= tmp_20_fu_2626_p1[4];
tmp_20_reg_5287[5] <= tmp_20_fu_2626_p1[5];
tmp_20_reg_5287[6] <= tmp_20_fu_2626_p1[6];
tmp_20_reg_5287[7] <= tmp_20_fu_2626_p1[7];
tmp_20_reg_5287[8] <= tmp_20_fu_2626_p1[8];
tmp_20_reg_5287[9] <= tmp_20_fu_2626_p1[9];
tmp_20_reg_5287[10] <= tmp_20_fu_2626_p1[10];
tmp_20_reg_5287[11] <= tmp_20_fu_2626_p1[11];
tmp_20_reg_5287[12] <= tmp_20_fu_2626_p1[12];
tmp_20_reg_5287[13] <= tmp_20_fu_2626_p1[13];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg6_fsm_46 == ap_CS_fsm))) begin
tmp_210_reg_6383[0] <= tmp_210_fu_4629_p1[0];
tmp_210_reg_6383[1] <= tmp_210_fu_4629_p1[1];
tmp_210_reg_6383[2] <= tmp_210_fu_4629_p1[2];
tmp_210_reg_6383[3] <= tmp_210_fu_4629_p1[3];
tmp_210_reg_6383[4] <= tmp_210_fu_4629_p1[4];
tmp_210_reg_6383[5] <= tmp_210_fu_4629_p1[5];
tmp_210_reg_6383[6] <= tmp_210_fu_4629_p1[6];
tmp_210_reg_6383[7] <= tmp_210_fu_4629_p1[7];
tmp_210_reg_6383[8] <= tmp_210_fu_4629_p1[8];
tmp_210_reg_6383[9] <= tmp_210_fu_4629_p1[9];
tmp_210_reg_6383[10] <= tmp_210_fu_4629_p1[10];
tmp_210_reg_6383[11] <= tmp_210_fu_4629_p1[11];
tmp_210_reg_6383[12] <= tmp_210_fu_4629_p1[12];
tmp_210_reg_6383[13] <= tmp_210_fu_4629_p1[13];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg6_fsm_46 == ap_CS_fsm))) begin
tmp_211_reg_6393[1] <= tmp_211_fu_4638_p1[1];
tmp_211_reg_6393[2] <= tmp_211_fu_4638_p1[2];
tmp_211_reg_6393[3] <= tmp_211_fu_4638_p1[3];
tmp_211_reg_6393[4] <= tmp_211_fu_4638_p1[4];
tmp_211_reg_6393[5] <= tmp_211_fu_4638_p1[5];
tmp_211_reg_6393[6] <= tmp_211_fu_4638_p1[6];
tmp_211_reg_6393[7] <= tmp_211_fu_4638_p1[7];
tmp_211_reg_6393[8] <= tmp_211_fu_4638_p1[8];
tmp_211_reg_6393[9] <= tmp_211_fu_4638_p1[9];
tmp_211_reg_6393[10] <= tmp_211_fu_4638_p1[10];
tmp_211_reg_6393[11] <= tmp_211_fu_4638_p1[11];
tmp_211_reg_6393[12] <= tmp_211_fu_4638_p1[12];
tmp_211_reg_6393[13] <= tmp_211_fu_4638_p1[13];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg7_fsm_47 == ap_CS_fsm))) begin
tmp_212_reg_6403[0] <= tmp_212_fu_4647_p1[0];
tmp_212_reg_6403[1] <= tmp_212_fu_4647_p1[1];
tmp_212_reg_6403[2] <= tmp_212_fu_4647_p1[2];
tmp_212_reg_6403[3] <= tmp_212_fu_4647_p1[3];
tmp_212_reg_6403[4] <= tmp_212_fu_4647_p1[4];
tmp_212_reg_6403[5] <= tmp_212_fu_4647_p1[5];
tmp_212_reg_6403[6] <= tmp_212_fu_4647_p1[6];
tmp_212_reg_6403[7] <= tmp_212_fu_4647_p1[7];
tmp_212_reg_6403[8] <= tmp_212_fu_4647_p1[8];
tmp_212_reg_6403[9] <= tmp_212_fu_4647_p1[9];
tmp_212_reg_6403[10] <= tmp_212_fu_4647_p1[10];
tmp_212_reg_6403[11] <= tmp_212_fu_4647_p1[11];
tmp_212_reg_6403[12] <= tmp_212_fu_4647_p1[12];
tmp_212_reg_6403[13] <= tmp_212_fu_4647_p1[13];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg7_fsm_47 == ap_CS_fsm))) begin
tmp_213_reg_6413[3] <= tmp_213_fu_4656_p1[3];
tmp_213_reg_6413[4] <= tmp_213_fu_4656_p1[4];
tmp_213_reg_6413[5] <= tmp_213_fu_4656_p1[5];
tmp_213_reg_6413[6] <= tmp_213_fu_4656_p1[6];
tmp_213_reg_6413[7] <= tmp_213_fu_4656_p1[7];
tmp_213_reg_6413[8] <= tmp_213_fu_4656_p1[8];
tmp_213_reg_6413[9] <= tmp_213_fu_4656_p1[9];
tmp_213_reg_6413[10] <= tmp_213_fu_4656_p1[10];
tmp_213_reg_6413[11] <= tmp_213_fu_4656_p1[11];
tmp_213_reg_6413[12] <= tmp_213_fu_4656_p1[12];
tmp_213_reg_6413[13] <= tmp_213_fu_4656_p1[13];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg8_fsm_48 == ap_CS_fsm))) begin
tmp_214_reg_6432[1] <= tmp_214_fu_4685_p1[1];
tmp_214_reg_6432[2] <= tmp_214_fu_4685_p1[2];
tmp_214_reg_6432[3] <= tmp_214_fu_4685_p1[3];
tmp_214_reg_6432[4] <= tmp_214_fu_4685_p1[4];
tmp_214_reg_6432[5] <= tmp_214_fu_4685_p1[5];
tmp_214_reg_6432[6] <= tmp_214_fu_4685_p1[6];
tmp_214_reg_6432[7] <= tmp_214_fu_4685_p1[7];
tmp_214_reg_6432[8] <= tmp_214_fu_4685_p1[8];
tmp_214_reg_6432[9] <= tmp_214_fu_4685_p1[9];
tmp_214_reg_6432[10] <= tmp_214_fu_4685_p1[10];
tmp_214_reg_6432[11] <= tmp_214_fu_4685_p1[11];
tmp_214_reg_6432[12] <= tmp_214_fu_4685_p1[12];
tmp_214_reg_6432[13] <= tmp_214_fu_4685_p1[13];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg8_fsm_48 == ap_CS_fsm))) begin
tmp_215_reg_6442[0] <= tmp_215_fu_4695_p1[0];
tmp_215_reg_6442[1] <= tmp_215_fu_4695_p1[1];
tmp_215_reg_6442[2] <= tmp_215_fu_4695_p1[2];
tmp_215_reg_6442[3] <= tmp_215_fu_4695_p1[3];
tmp_215_reg_6442[4] <= tmp_215_fu_4695_p1[4];
tmp_215_reg_6442[5] <= tmp_215_fu_4695_p1[5];
tmp_215_reg_6442[6] <= tmp_215_fu_4695_p1[6];
tmp_215_reg_6442[7] <= tmp_215_fu_4695_p1[7];
tmp_215_reg_6442[8] <= tmp_215_fu_4695_p1[8];
tmp_215_reg_6442[9] <= tmp_215_fu_4695_p1[9];
tmp_215_reg_6442[10] <= tmp_215_fu_4695_p1[10];
tmp_215_reg_6442[11] <= tmp_215_fu_4695_p1[11];
tmp_215_reg_6442[12] <= tmp_215_fu_4695_p1[12];
tmp_215_reg_6442[13] <= tmp_215_fu_4695_p1[13];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg9_fsm_49 == ap_CS_fsm))) begin
tmp_216_reg_6452[2] <= tmp_216_fu_4704_p1[2];
tmp_216_reg_6452[3] <= tmp_216_fu_4704_p1[3];
tmp_216_reg_6452[4] <= tmp_216_fu_4704_p1[4];
tmp_216_reg_6452[5] <= tmp_216_fu_4704_p1[5];
tmp_216_reg_6452[6] <= tmp_216_fu_4704_p1[6];
tmp_216_reg_6452[7] <= tmp_216_fu_4704_p1[7];
tmp_216_reg_6452[8] <= tmp_216_fu_4704_p1[8];
tmp_216_reg_6452[9] <= tmp_216_fu_4704_p1[9];
tmp_216_reg_6452[10] <= tmp_216_fu_4704_p1[10];
tmp_216_reg_6452[11] <= tmp_216_fu_4704_p1[11];
tmp_216_reg_6452[12] <= tmp_216_fu_4704_p1[12];
tmp_216_reg_6452[13] <= tmp_216_fu_4704_p1[13];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg9_fsm_49 == ap_CS_fsm))) begin
tmp_217_reg_6462[0] <= tmp_217_fu_4713_p1[0];
tmp_217_reg_6462[1] <= tmp_217_fu_4713_p1[1];
tmp_217_reg_6462[2] <= tmp_217_fu_4713_p1[2];
tmp_217_reg_6462[3] <= tmp_217_fu_4713_p1[3];
tmp_217_reg_6462[4] <= tmp_217_fu_4713_p1[4];
tmp_217_reg_6462[5] <= tmp_217_fu_4713_p1[5];
tmp_217_reg_6462[6] <= tmp_217_fu_4713_p1[6];
tmp_217_reg_6462[7] <= tmp_217_fu_4713_p1[7];
tmp_217_reg_6462[8] <= tmp_217_fu_4713_p1[8];
tmp_217_reg_6462[9] <= tmp_217_fu_4713_p1[9];
tmp_217_reg_6462[10] <= tmp_217_fu_4713_p1[10];
tmp_217_reg_6462[11] <= tmp_217_fu_4713_p1[11];
tmp_217_reg_6462[12] <= tmp_217_fu_4713_p1[12];
tmp_217_reg_6462[13] <= tmp_217_fu_4713_p1[13];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg10_fsm_50 == ap_CS_fsm))) begin
tmp_218_reg_6472[1] <= tmp_218_fu_4722_p1[1];
tmp_218_reg_6472[2] <= tmp_218_fu_4722_p1[2];
tmp_218_reg_6472[3] <= tmp_218_fu_4722_p1[3];
tmp_218_reg_6472[4] <= tmp_218_fu_4722_p1[4];
tmp_218_reg_6472[5] <= tmp_218_fu_4722_p1[5];
tmp_218_reg_6472[6] <= tmp_218_fu_4722_p1[6];
tmp_218_reg_6472[7] <= tmp_218_fu_4722_p1[7];
tmp_218_reg_6472[8] <= tmp_218_fu_4722_p1[8];
tmp_218_reg_6472[9] <= tmp_218_fu_4722_p1[9];
tmp_218_reg_6472[10] <= tmp_218_fu_4722_p1[10];
tmp_218_reg_6472[11] <= tmp_218_fu_4722_p1[11];
tmp_218_reg_6472[12] <= tmp_218_fu_4722_p1[12];
tmp_218_reg_6472[13] <= tmp_218_fu_4722_p1[13];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg10_fsm_50 == ap_CS_fsm))) begin
tmp_219_reg_6482[0] <= tmp_219_fu_4731_p1[0];
tmp_219_reg_6482[1] <= tmp_219_fu_4731_p1[1];
tmp_219_reg_6482[2] <= tmp_219_fu_4731_p1[2];
tmp_219_reg_6482[3] <= tmp_219_fu_4731_p1[3];
tmp_219_reg_6482[4] <= tmp_219_fu_4731_p1[4];
tmp_219_reg_6482[5] <= tmp_219_fu_4731_p1[5];
tmp_219_reg_6482[6] <= tmp_219_fu_4731_p1[6];
tmp_219_reg_6482[7] <= tmp_219_fu_4731_p1[7];
tmp_219_reg_6482[8] <= tmp_219_fu_4731_p1[8];
tmp_219_reg_6482[9] <= tmp_219_fu_4731_p1[9];
tmp_219_reg_6482[10] <= tmp_219_fu_4731_p1[10];
tmp_219_reg_6482[11] <= tmp_219_fu_4731_p1[11];
tmp_219_reg_6482[12] <= tmp_219_fu_4731_p1[12];
tmp_219_reg_6482[13] <= tmp_219_fu_4731_p1[13];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg11_fsm_51 == ap_CS_fsm))) begin
tmp_220_reg_6492[3] <= tmp_220_fu_4745_p1[3];
tmp_220_reg_6492[4] <= tmp_220_fu_4745_p1[4];
tmp_220_reg_6492[5] <= tmp_220_fu_4745_p1[5];
tmp_220_reg_6492[6] <= tmp_220_fu_4745_p1[6];
tmp_220_reg_6492[7] <= tmp_220_fu_4745_p1[7];
tmp_220_reg_6492[8] <= tmp_220_fu_4745_p1[8];
tmp_220_reg_6492[9] <= tmp_220_fu_4745_p1[9];
tmp_220_reg_6492[10] <= tmp_220_fu_4745_p1[10];
tmp_220_reg_6492[11] <= tmp_220_fu_4745_p1[11];
tmp_220_reg_6492[12] <= tmp_220_fu_4745_p1[12];
tmp_220_reg_6492[13] <= tmp_220_fu_4745_p1[13];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg11_fsm_51 == ap_CS_fsm))) begin
tmp_221_reg_6512[1] <= tmp_221_fu_4769_p1[1];
tmp_221_reg_6512[2] <= tmp_221_fu_4769_p1[2];
tmp_221_reg_6512[3] <= tmp_221_fu_4769_p1[3];
tmp_221_reg_6512[4] <= tmp_221_fu_4769_p1[4];
tmp_221_reg_6512[5] <= tmp_221_fu_4769_p1[5];
tmp_221_reg_6512[6] <= tmp_221_fu_4769_p1[6];
tmp_221_reg_6512[7] <= tmp_221_fu_4769_p1[7];
tmp_221_reg_6512[8] <= tmp_221_fu_4769_p1[8];
tmp_221_reg_6512[9] <= tmp_221_fu_4769_p1[9];
tmp_221_reg_6512[10] <= tmp_221_fu_4769_p1[10];
tmp_221_reg_6512[11] <= tmp_221_fu_4769_p1[11];
tmp_221_reg_6512[12] <= tmp_221_fu_4769_p1[12];
tmp_221_reg_6512[13] <= tmp_221_fu_4769_p1[13];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg12_fsm_52 == ap_CS_fsm))) begin
tmp_222_reg_6522[0] <= tmp_222_fu_4778_p1[0];
tmp_222_reg_6522[1] <= tmp_222_fu_4778_p1[1];
tmp_222_reg_6522[2] <= tmp_222_fu_4778_p1[2];
tmp_222_reg_6522[3] <= tmp_222_fu_4778_p1[3];
tmp_222_reg_6522[4] <= tmp_222_fu_4778_p1[4];
tmp_222_reg_6522[5] <= tmp_222_fu_4778_p1[5];
tmp_222_reg_6522[6] <= tmp_222_fu_4778_p1[6];
tmp_222_reg_6522[7] <= tmp_222_fu_4778_p1[7];
tmp_222_reg_6522[8] <= tmp_222_fu_4778_p1[8];
tmp_222_reg_6522[9] <= tmp_222_fu_4778_p1[9];
tmp_222_reg_6522[10] <= tmp_222_fu_4778_p1[10];
tmp_222_reg_6522[11] <= tmp_222_fu_4778_p1[11];
tmp_222_reg_6522[12] <= tmp_222_fu_4778_p1[12];
tmp_222_reg_6522[13] <= tmp_222_fu_4778_p1[13];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg12_fsm_52 == ap_CS_fsm))) begin
tmp_223_reg_6532[2] <= tmp_223_fu_4787_p1[2];
tmp_223_reg_6532[3] <= tmp_223_fu_4787_p1[3];
tmp_223_reg_6532[4] <= tmp_223_fu_4787_p1[4];
tmp_223_reg_6532[5] <= tmp_223_fu_4787_p1[5];
tmp_223_reg_6532[6] <= tmp_223_fu_4787_p1[6];
tmp_223_reg_6532[7] <= tmp_223_fu_4787_p1[7];
tmp_223_reg_6532[8] <= tmp_223_fu_4787_p1[8];
tmp_223_reg_6532[9] <= tmp_223_fu_4787_p1[9];
tmp_223_reg_6532[10] <= tmp_223_fu_4787_p1[10];
tmp_223_reg_6532[11] <= tmp_223_fu_4787_p1[11];
tmp_223_reg_6532[12] <= tmp_223_fu_4787_p1[12];
tmp_223_reg_6532[13] <= tmp_223_fu_4787_p1[13];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg13_fsm_53 == ap_CS_fsm))) begin
tmp_224_reg_6542[0] <= tmp_224_fu_4796_p1[0];
tmp_224_reg_6542[1] <= tmp_224_fu_4796_p1[1];
tmp_224_reg_6542[2] <= tmp_224_fu_4796_p1[2];
tmp_224_reg_6542[3] <= tmp_224_fu_4796_p1[3];
tmp_224_reg_6542[4] <= tmp_224_fu_4796_p1[4];
tmp_224_reg_6542[5] <= tmp_224_fu_4796_p1[5];
tmp_224_reg_6542[6] <= tmp_224_fu_4796_p1[6];
tmp_224_reg_6542[7] <= tmp_224_fu_4796_p1[7];
tmp_224_reg_6542[8] <= tmp_224_fu_4796_p1[8];
tmp_224_reg_6542[9] <= tmp_224_fu_4796_p1[9];
tmp_224_reg_6542[10] <= tmp_224_fu_4796_p1[10];
tmp_224_reg_6542[11] <= tmp_224_fu_4796_p1[11];
tmp_224_reg_6542[12] <= tmp_224_fu_4796_p1[12];
tmp_224_reg_6542[13] <= tmp_224_fu_4796_p1[13];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg13_fsm_53 == ap_CS_fsm))) begin
tmp_225_reg_6552[1] <= tmp_225_fu_4805_p1[1];
tmp_225_reg_6552[2] <= tmp_225_fu_4805_p1[2];
tmp_225_reg_6552[3] <= tmp_225_fu_4805_p1[3];
tmp_225_reg_6552[4] <= tmp_225_fu_4805_p1[4];
tmp_225_reg_6552[5] <= tmp_225_fu_4805_p1[5];
tmp_225_reg_6552[6] <= tmp_225_fu_4805_p1[6];
tmp_225_reg_6552[7] <= tmp_225_fu_4805_p1[7];
tmp_225_reg_6552[8] <= tmp_225_fu_4805_p1[8];
tmp_225_reg_6552[9] <= tmp_225_fu_4805_p1[9];
tmp_225_reg_6552[10] <= tmp_225_fu_4805_p1[10];
tmp_225_reg_6552[11] <= tmp_225_fu_4805_p1[11];
tmp_225_reg_6552[12] <= tmp_225_fu_4805_p1[12];
tmp_225_reg_6552[13] <= tmp_225_fu_4805_p1[13];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg14_fsm_54 == ap_CS_fsm))) begin
tmp_226_reg_6562[0] <= tmp_226_fu_4814_p1[0];
tmp_226_reg_6562[1] <= tmp_226_fu_4814_p1[1];
tmp_226_reg_6562[2] <= tmp_226_fu_4814_p1[2];
tmp_226_reg_6562[3] <= tmp_226_fu_4814_p1[3];
tmp_226_reg_6562[4] <= tmp_226_fu_4814_p1[4];
tmp_226_reg_6562[5] <= tmp_226_fu_4814_p1[5];
tmp_226_reg_6562[6] <= tmp_226_fu_4814_p1[6];
tmp_226_reg_6562[7] <= tmp_226_fu_4814_p1[7];
tmp_226_reg_6562[8] <= tmp_226_fu_4814_p1[8];
tmp_226_reg_6562[9] <= tmp_226_fu_4814_p1[9];
tmp_226_reg_6562[10] <= tmp_226_fu_4814_p1[10];
tmp_226_reg_6562[11] <= tmp_226_fu_4814_p1[11];
tmp_226_reg_6562[12] <= tmp_226_fu_4814_p1[12];
tmp_226_reg_6562[13] <= tmp_226_fu_4814_p1[13];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg14_fsm_54 == ap_CS_fsm))) begin
tmp_227_reg_6572[3] <= tmp_227_fu_4823_p1[3];
tmp_227_reg_6572[4] <= tmp_227_fu_4823_p1[4];
tmp_227_reg_6572[5] <= tmp_227_fu_4823_p1[5];
tmp_227_reg_6572[6] <= tmp_227_fu_4823_p1[6];
tmp_227_reg_6572[7] <= tmp_227_fu_4823_p1[7];
tmp_227_reg_6572[8] <= tmp_227_fu_4823_p1[8];
tmp_227_reg_6572[9] <= tmp_227_fu_4823_p1[9];
tmp_227_reg_6572[10] <= tmp_227_fu_4823_p1[10];
tmp_227_reg_6572[11] <= tmp_227_fu_4823_p1[11];
tmp_227_reg_6572[12] <= tmp_227_fu_4823_p1[12];
tmp_227_reg_6572[13] <= tmp_227_fu_4823_p1[13];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg15_fsm_55 == ap_CS_fsm))) begin
tmp_228_reg_6591[1] <= tmp_228_fu_4852_p1[1];
tmp_228_reg_6591[2] <= tmp_228_fu_4852_p1[2];
tmp_228_reg_6591[3] <= tmp_228_fu_4852_p1[3];
tmp_228_reg_6591[4] <= tmp_228_fu_4852_p1[4];
tmp_228_reg_6591[5] <= tmp_228_fu_4852_p1[5];
tmp_228_reg_6591[6] <= tmp_228_fu_4852_p1[6];
tmp_228_reg_6591[7] <= tmp_228_fu_4852_p1[7];
tmp_228_reg_6591[8] <= tmp_228_fu_4852_p1[8];
tmp_228_reg_6591[9] <= tmp_228_fu_4852_p1[9];
tmp_228_reg_6591[10] <= tmp_228_fu_4852_p1[10];
tmp_228_reg_6591[11] <= tmp_228_fu_4852_p1[11];
tmp_228_reg_6591[12] <= tmp_228_fu_4852_p1[12];
tmp_228_reg_6591[13] <= tmp_228_fu_4852_p1[13];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg15_fsm_55 == ap_CS_fsm))) begin
tmp_229_reg_6601[0] <= tmp_229_fu_4862_p1[0];
tmp_229_reg_6601[1] <= tmp_229_fu_4862_p1[1];
tmp_229_reg_6601[2] <= tmp_229_fu_4862_p1[2];
tmp_229_reg_6601[3] <= tmp_229_fu_4862_p1[3];
tmp_229_reg_6601[4] <= tmp_229_fu_4862_p1[4];
tmp_229_reg_6601[5] <= tmp_229_fu_4862_p1[5];
tmp_229_reg_6601[6] <= tmp_229_fu_4862_p1[6];
tmp_229_reg_6601[7] <= tmp_229_fu_4862_p1[7];
tmp_229_reg_6601[8] <= tmp_229_fu_4862_p1[8];
tmp_229_reg_6601[9] <= tmp_229_fu_4862_p1[9];
tmp_229_reg_6601[10] <= tmp_229_fu_4862_p1[10];
tmp_229_reg_6601[11] <= tmp_229_fu_4862_p1[11];
tmp_229_reg_6601[12] <= tmp_229_fu_4862_p1[12];
tmp_229_reg_6601[13] <= tmp_229_fu_4862_p1[13];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg16_fsm_56 == ap_CS_fsm))) begin
tmp_230_reg_6611[2] <= tmp_230_fu_4871_p1[2];
tmp_230_reg_6611[3] <= tmp_230_fu_4871_p1[3];
tmp_230_reg_6611[4] <= tmp_230_fu_4871_p1[4];
tmp_230_reg_6611[5] <= tmp_230_fu_4871_p1[5];
tmp_230_reg_6611[6] <= tmp_230_fu_4871_p1[6];
tmp_230_reg_6611[7] <= tmp_230_fu_4871_p1[7];
tmp_230_reg_6611[8] <= tmp_230_fu_4871_p1[8];
tmp_230_reg_6611[9] <= tmp_230_fu_4871_p1[9];
tmp_230_reg_6611[10] <= tmp_230_fu_4871_p1[10];
tmp_230_reg_6611[11] <= tmp_230_fu_4871_p1[11];
tmp_230_reg_6611[12] <= tmp_230_fu_4871_p1[12];
tmp_230_reg_6611[13] <= tmp_230_fu_4871_p1[13];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg16_fsm_56 == ap_CS_fsm))) begin
tmp_231_reg_6621[0] <= tmp_231_fu_4880_p1[0];
tmp_231_reg_6621[1] <= tmp_231_fu_4880_p1[1];
tmp_231_reg_6621[2] <= tmp_231_fu_4880_p1[2];
tmp_231_reg_6621[3] <= tmp_231_fu_4880_p1[3];
tmp_231_reg_6621[4] <= tmp_231_fu_4880_p1[4];
tmp_231_reg_6621[5] <= tmp_231_fu_4880_p1[5];
tmp_231_reg_6621[6] <= tmp_231_fu_4880_p1[6];
tmp_231_reg_6621[7] <= tmp_231_fu_4880_p1[7];
tmp_231_reg_6621[8] <= tmp_231_fu_4880_p1[8];
tmp_231_reg_6621[9] <= tmp_231_fu_4880_p1[9];
tmp_231_reg_6621[10] <= tmp_231_fu_4880_p1[10];
tmp_231_reg_6621[11] <= tmp_231_fu_4880_p1[11];
tmp_231_reg_6621[12] <= tmp_231_fu_4880_p1[12];
tmp_231_reg_6621[13] <= tmp_231_fu_4880_p1[13];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg17_fsm_57 == ap_CS_fsm))) begin
tmp_232_reg_6631[1] <= tmp_232_fu_4889_p1[1];
tmp_232_reg_6631[2] <= tmp_232_fu_4889_p1[2];
tmp_232_reg_6631[3] <= tmp_232_fu_4889_p1[3];
tmp_232_reg_6631[4] <= tmp_232_fu_4889_p1[4];
tmp_232_reg_6631[5] <= tmp_232_fu_4889_p1[5];
tmp_232_reg_6631[6] <= tmp_232_fu_4889_p1[6];
tmp_232_reg_6631[7] <= tmp_232_fu_4889_p1[7];
tmp_232_reg_6631[8] <= tmp_232_fu_4889_p1[8];
tmp_232_reg_6631[9] <= tmp_232_fu_4889_p1[9];
tmp_232_reg_6631[10] <= tmp_232_fu_4889_p1[10];
tmp_232_reg_6631[11] <= tmp_232_fu_4889_p1[11];
tmp_232_reg_6631[12] <= tmp_232_fu_4889_p1[12];
tmp_232_reg_6631[13] <= tmp_232_fu_4889_p1[13];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg17_fsm_57 == ap_CS_fsm))) begin
tmp_233_reg_6641[0] <= tmp_233_fu_4898_p1[0];
tmp_233_reg_6641[1] <= tmp_233_fu_4898_p1[1];
tmp_233_reg_6641[2] <= tmp_233_fu_4898_p1[2];
tmp_233_reg_6641[3] <= tmp_233_fu_4898_p1[3];
tmp_233_reg_6641[4] <= tmp_233_fu_4898_p1[4];
tmp_233_reg_6641[5] <= tmp_233_fu_4898_p1[5];
tmp_233_reg_6641[6] <= tmp_233_fu_4898_p1[6];
tmp_233_reg_6641[7] <= tmp_233_fu_4898_p1[7];
tmp_233_reg_6641[8] <= tmp_233_fu_4898_p1[8];
tmp_233_reg_6641[9] <= tmp_233_fu_4898_p1[9];
tmp_233_reg_6641[10] <= tmp_233_fu_4898_p1[10];
tmp_233_reg_6641[11] <= tmp_233_fu_4898_p1[11];
tmp_233_reg_6641[12] <= tmp_233_fu_4898_p1[12];
tmp_233_reg_6641[13] <= tmp_233_fu_4898_p1[13];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg18_fsm_58 == ap_CS_fsm))) begin
tmp_234_reg_6651[3] <= tmp_234_fu_4912_p1[3];
tmp_234_reg_6651[4] <= tmp_234_fu_4912_p1[4];
tmp_234_reg_6651[5] <= tmp_234_fu_4912_p1[5];
tmp_234_reg_6651[6] <= tmp_234_fu_4912_p1[6];
tmp_234_reg_6651[7] <= tmp_234_fu_4912_p1[7];
tmp_234_reg_6651[8] <= tmp_234_fu_4912_p1[8];
tmp_234_reg_6651[9] <= tmp_234_fu_4912_p1[9];
tmp_234_reg_6651[10] <= tmp_234_fu_4912_p1[10];
tmp_234_reg_6651[11] <= tmp_234_fu_4912_p1[11];
tmp_234_reg_6651[12] <= tmp_234_fu_4912_p1[12];
tmp_234_reg_6651[13] <= tmp_234_fu_4912_p1[13];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg18_fsm_58 == ap_CS_fsm))) begin
tmp_235_reg_6671[1] <= tmp_235_fu_4936_p1[1];
tmp_235_reg_6671[2] <= tmp_235_fu_4936_p1[2];
tmp_235_reg_6671[3] <= tmp_235_fu_4936_p1[3];
tmp_235_reg_6671[4] <= tmp_235_fu_4936_p1[4];
tmp_235_reg_6671[5] <= tmp_235_fu_4936_p1[5];
tmp_235_reg_6671[6] <= tmp_235_fu_4936_p1[6];
tmp_235_reg_6671[7] <= tmp_235_fu_4936_p1[7];
tmp_235_reg_6671[8] <= tmp_235_fu_4936_p1[8];
tmp_235_reg_6671[9] <= tmp_235_fu_4936_p1[9];
tmp_235_reg_6671[10] <= tmp_235_fu_4936_p1[10];
tmp_235_reg_6671[11] <= tmp_235_fu_4936_p1[11];
tmp_235_reg_6671[12] <= tmp_235_fu_4936_p1[12];
tmp_235_reg_6671[13] <= tmp_235_fu_4936_p1[13];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg19_fsm_59 == ap_CS_fsm))) begin
tmp_236_reg_6681[0] <= tmp_236_fu_4945_p1[0];
tmp_236_reg_6681[1] <= tmp_236_fu_4945_p1[1];
tmp_236_reg_6681[2] <= tmp_236_fu_4945_p1[2];
tmp_236_reg_6681[3] <= tmp_236_fu_4945_p1[3];
tmp_236_reg_6681[4] <= tmp_236_fu_4945_p1[4];
tmp_236_reg_6681[5] <= tmp_236_fu_4945_p1[5];
tmp_236_reg_6681[6] <= tmp_236_fu_4945_p1[6];
tmp_236_reg_6681[7] <= tmp_236_fu_4945_p1[7];
tmp_236_reg_6681[8] <= tmp_236_fu_4945_p1[8];
tmp_236_reg_6681[9] <= tmp_236_fu_4945_p1[9];
tmp_236_reg_6681[10] <= tmp_236_fu_4945_p1[10];
tmp_236_reg_6681[11] <= tmp_236_fu_4945_p1[11];
tmp_236_reg_6681[12] <= tmp_236_fu_4945_p1[12];
tmp_236_reg_6681[13] <= tmp_236_fu_4945_p1[13];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg19_fsm_59 == ap_CS_fsm))) begin
tmp_237_reg_6691[2] <= tmp_237_fu_4954_p1[2];
tmp_237_reg_6691[3] <= tmp_237_fu_4954_p1[3];
tmp_237_reg_6691[4] <= tmp_237_fu_4954_p1[4];
tmp_237_reg_6691[5] <= tmp_237_fu_4954_p1[5];
tmp_237_reg_6691[6] <= tmp_237_fu_4954_p1[6];
tmp_237_reg_6691[7] <= tmp_237_fu_4954_p1[7];
tmp_237_reg_6691[8] <= tmp_237_fu_4954_p1[8];
tmp_237_reg_6691[9] <= tmp_237_fu_4954_p1[9];
tmp_237_reg_6691[10] <= tmp_237_fu_4954_p1[10];
tmp_237_reg_6691[11] <= tmp_237_fu_4954_p1[11];
tmp_237_reg_6691[12] <= tmp_237_fu_4954_p1[12];
tmp_237_reg_6691[13] <= tmp_237_fu_4954_p1[13];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg20_fsm_60 == ap_CS_fsm))) begin
tmp_238_reg_6701[0] <= tmp_238_fu_4963_p1[0];
tmp_238_reg_6701[1] <= tmp_238_fu_4963_p1[1];
tmp_238_reg_6701[2] <= tmp_238_fu_4963_p1[2];
tmp_238_reg_6701[3] <= tmp_238_fu_4963_p1[3];
tmp_238_reg_6701[4] <= tmp_238_fu_4963_p1[4];
tmp_238_reg_6701[5] <= tmp_238_fu_4963_p1[5];
tmp_238_reg_6701[6] <= tmp_238_fu_4963_p1[6];
tmp_238_reg_6701[7] <= tmp_238_fu_4963_p1[7];
tmp_238_reg_6701[8] <= tmp_238_fu_4963_p1[8];
tmp_238_reg_6701[9] <= tmp_238_fu_4963_p1[9];
tmp_238_reg_6701[10] <= tmp_238_fu_4963_p1[10];
tmp_238_reg_6701[11] <= tmp_238_fu_4963_p1[11];
tmp_238_reg_6701[12] <= tmp_238_fu_4963_p1[12];
tmp_238_reg_6701[13] <= tmp_238_fu_4963_p1[13];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg20_fsm_60 == ap_CS_fsm))) begin
tmp_239_reg_6711[1] <= tmp_239_fu_4972_p1[1];
tmp_239_reg_6711[2] <= tmp_239_fu_4972_p1[2];
tmp_239_reg_6711[3] <= tmp_239_fu_4972_p1[3];
tmp_239_reg_6711[4] <= tmp_239_fu_4972_p1[4];
tmp_239_reg_6711[5] <= tmp_239_fu_4972_p1[5];
tmp_239_reg_6711[6] <= tmp_239_fu_4972_p1[6];
tmp_239_reg_6711[7] <= tmp_239_fu_4972_p1[7];
tmp_239_reg_6711[8] <= tmp_239_fu_4972_p1[8];
tmp_239_reg_6711[9] <= tmp_239_fu_4972_p1[9];
tmp_239_reg_6711[10] <= tmp_239_fu_4972_p1[10];
tmp_239_reg_6711[11] <= tmp_239_fu_4972_p1[11];
tmp_239_reg_6711[12] <= tmp_239_fu_4972_p1[12];
tmp_239_reg_6711[13] <= tmp_239_fu_4972_p1[13];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg21_fsm_61 == ap_CS_fsm))) begin
tmp_240_reg_6721[0] <= tmp_240_fu_4981_p1[0];
tmp_240_reg_6721[1] <= tmp_240_fu_4981_p1[1];
tmp_240_reg_6721[2] <= tmp_240_fu_4981_p1[2];
tmp_240_reg_6721[3] <= tmp_240_fu_4981_p1[3];
tmp_240_reg_6721[4] <= tmp_240_fu_4981_p1[4];
tmp_240_reg_6721[5] <= tmp_240_fu_4981_p1[5];
tmp_240_reg_6721[6] <= tmp_240_fu_4981_p1[6];
tmp_240_reg_6721[7] <= tmp_240_fu_4981_p1[7];
tmp_240_reg_6721[8] <= tmp_240_fu_4981_p1[8];
tmp_240_reg_6721[9] <= tmp_240_fu_4981_p1[9];
tmp_240_reg_6721[10] <= tmp_240_fu_4981_p1[10];
tmp_240_reg_6721[11] <= tmp_240_fu_4981_p1[11];
tmp_240_reg_6721[12] <= tmp_240_fu_4981_p1[12];
tmp_240_reg_6721[13] <= tmp_240_fu_4981_p1[13];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg21_fsm_61 == ap_CS_fsm))) begin
tmp_241_reg_6731[3] <= tmp_241_fu_4990_p1[3];
tmp_241_reg_6731[4] <= tmp_241_fu_4990_p1[4];
tmp_241_reg_6731[5] <= tmp_241_fu_4990_p1[5];
tmp_241_reg_6731[6] <= tmp_241_fu_4990_p1[6];
tmp_241_reg_6731[7] <= tmp_241_fu_4990_p1[7];
tmp_241_reg_6731[8] <= tmp_241_fu_4990_p1[8];
tmp_241_reg_6731[9] <= tmp_241_fu_4990_p1[9];
tmp_241_reg_6731[10] <= tmp_241_fu_4990_p1[10];
tmp_241_reg_6731[11] <= tmp_241_fu_4990_p1[11];
tmp_241_reg_6731[12] <= tmp_241_fu_4990_p1[12];
tmp_241_reg_6731[13] <= tmp_241_fu_4990_p1[13];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg22_fsm_62 == ap_CS_fsm))) begin
tmp_242_reg_6750[1] <= tmp_242_fu_5019_p1[1];
tmp_242_reg_6750[2] <= tmp_242_fu_5019_p1[2];
tmp_242_reg_6750[3] <= tmp_242_fu_5019_p1[3];
tmp_242_reg_6750[4] <= tmp_242_fu_5019_p1[4];
tmp_242_reg_6750[5] <= tmp_242_fu_5019_p1[5];
tmp_242_reg_6750[6] <= tmp_242_fu_5019_p1[6];
tmp_242_reg_6750[7] <= tmp_242_fu_5019_p1[7];
tmp_242_reg_6750[8] <= tmp_242_fu_5019_p1[8];
tmp_242_reg_6750[9] <= tmp_242_fu_5019_p1[9];
tmp_242_reg_6750[10] <= tmp_242_fu_5019_p1[10];
tmp_242_reg_6750[11] <= tmp_242_fu_5019_p1[11];
tmp_242_reg_6750[12] <= tmp_242_fu_5019_p1[12];
tmp_242_reg_6750[13] <= tmp_242_fu_5019_p1[13];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg22_fsm_62 == ap_CS_fsm))) begin
tmp_243_reg_6760[0] <= tmp_243_fu_5029_p1[0];
tmp_243_reg_6760[1] <= tmp_243_fu_5029_p1[1];
tmp_243_reg_6760[2] <= tmp_243_fu_5029_p1[2];
tmp_243_reg_6760[3] <= tmp_243_fu_5029_p1[3];
tmp_243_reg_6760[4] <= tmp_243_fu_5029_p1[4];
tmp_243_reg_6760[5] <= tmp_243_fu_5029_p1[5];
tmp_243_reg_6760[6] <= tmp_243_fu_5029_p1[6];
tmp_243_reg_6760[7] <= tmp_243_fu_5029_p1[7];
tmp_243_reg_6760[8] <= tmp_243_fu_5029_p1[8];
tmp_243_reg_6760[9] <= tmp_243_fu_5029_p1[9];
tmp_243_reg_6760[10] <= tmp_243_fu_5029_p1[10];
tmp_243_reg_6760[11] <= tmp_243_fu_5029_p1[11];
tmp_243_reg_6760[12] <= tmp_243_fu_5029_p1[12];
tmp_243_reg_6760[13] <= tmp_243_fu_5029_p1[13];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg23_fsm_63 == ap_CS_fsm))) begin
tmp_244_reg_6770[2] <= tmp_244_fu_5038_p1[2];
tmp_244_reg_6770[3] <= tmp_244_fu_5038_p1[3];
tmp_244_reg_6770[4] <= tmp_244_fu_5038_p1[4];
tmp_244_reg_6770[5] <= tmp_244_fu_5038_p1[5];
tmp_244_reg_6770[6] <= tmp_244_fu_5038_p1[6];
tmp_244_reg_6770[7] <= tmp_244_fu_5038_p1[7];
tmp_244_reg_6770[8] <= tmp_244_fu_5038_p1[8];
tmp_244_reg_6770[9] <= tmp_244_fu_5038_p1[9];
tmp_244_reg_6770[10] <= tmp_244_fu_5038_p1[10];
tmp_244_reg_6770[11] <= tmp_244_fu_5038_p1[11];
tmp_244_reg_6770[12] <= tmp_244_fu_5038_p1[12];
tmp_244_reg_6770[13] <= tmp_244_fu_5038_p1[13];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg23_fsm_63 == ap_CS_fsm))) begin
tmp_245_reg_6780[0] <= tmp_245_fu_5047_p1[0];
tmp_245_reg_6780[1] <= tmp_245_fu_5047_p1[1];
tmp_245_reg_6780[2] <= tmp_245_fu_5047_p1[2];
tmp_245_reg_6780[3] <= tmp_245_fu_5047_p1[3];
tmp_245_reg_6780[4] <= tmp_245_fu_5047_p1[4];
tmp_245_reg_6780[5] <= tmp_245_fu_5047_p1[5];
tmp_245_reg_6780[6] <= tmp_245_fu_5047_p1[6];
tmp_245_reg_6780[7] <= tmp_245_fu_5047_p1[7];
tmp_245_reg_6780[8] <= tmp_245_fu_5047_p1[8];
tmp_245_reg_6780[9] <= tmp_245_fu_5047_p1[9];
tmp_245_reg_6780[10] <= tmp_245_fu_5047_p1[10];
tmp_245_reg_6780[11] <= tmp_245_fu_5047_p1[11];
tmp_245_reg_6780[12] <= tmp_245_fu_5047_p1[12];
tmp_245_reg_6780[13] <= tmp_245_fu_5047_p1[13];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg24_fsm_64 == ap_CS_fsm))) begin
tmp_246_reg_6790[1] <= tmp_246_fu_5061_p1[1];
tmp_246_reg_6790[2] <= tmp_246_fu_5061_p1[2];
tmp_246_reg_6790[3] <= tmp_246_fu_5061_p1[3];
tmp_246_reg_6790[4] <= tmp_246_fu_5061_p1[4];
tmp_246_reg_6790[5] <= tmp_246_fu_5061_p1[5];
tmp_246_reg_6790[6] <= tmp_246_fu_5061_p1[6];
tmp_246_reg_6790[7] <= tmp_246_fu_5061_p1[7];
tmp_246_reg_6790[8] <= tmp_246_fu_5061_p1[8];
tmp_246_reg_6790[9] <= tmp_246_fu_5061_p1[9];
tmp_246_reg_6790[10] <= tmp_246_fu_5061_p1[10];
tmp_246_reg_6790[11] <= tmp_246_fu_5061_p1[11];
tmp_246_reg_6790[12] <= tmp_246_fu_5061_p1[12];
tmp_246_reg_6790[13] <= tmp_246_fu_5061_p1[13];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg24_fsm_64 == ap_CS_fsm))) begin
tmp_247_reg_6800[0] <= tmp_247_fu_5070_p1[0];
tmp_247_reg_6800[1] <= tmp_247_fu_5070_p1[1];
tmp_247_reg_6800[2] <= tmp_247_fu_5070_p1[2];
tmp_247_reg_6800[3] <= tmp_247_fu_5070_p1[3];
tmp_247_reg_6800[4] <= tmp_247_fu_5070_p1[4];
tmp_247_reg_6800[5] <= tmp_247_fu_5070_p1[5];
tmp_247_reg_6800[6] <= tmp_247_fu_5070_p1[6];
tmp_247_reg_6800[7] <= tmp_247_fu_5070_p1[7];
tmp_247_reg_6800[8] <= tmp_247_fu_5070_p1[8];
tmp_247_reg_6800[9] <= tmp_247_fu_5070_p1[9];
tmp_247_reg_6800[10] <= tmp_247_fu_5070_p1[10];
tmp_247_reg_6800[11] <= tmp_247_fu_5070_p1[11];
tmp_247_reg_6800[12] <= tmp_247_fu_5070_p1[12];
tmp_247_reg_6800[13] <= tmp_247_fu_5070_p1[13];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg25_fsm_65 == ap_CS_fsm))) begin
tmp_248_reg_6850[3] <= tmp_248_fu_5128_p1[3];
tmp_248_reg_6850[4] <= tmp_248_fu_5128_p1[4];
tmp_248_reg_6850[5] <= tmp_248_fu_5128_p1[5];
tmp_248_reg_6850[6] <= tmp_248_fu_5128_p1[6];
tmp_248_reg_6850[7] <= tmp_248_fu_5128_p1[7];
tmp_248_reg_6850[8] <= tmp_248_fu_5128_p1[8];
tmp_248_reg_6850[9] <= tmp_248_fu_5128_p1[9];
tmp_248_reg_6850[10] <= tmp_248_fu_5128_p1[10];
tmp_248_reg_6850[11] <= tmp_248_fu_5128_p1[11];
tmp_248_reg_6850[12] <= tmp_248_fu_5128_p1[12];
tmp_248_reg_6850[13] <= tmp_248_fu_5128_p1[13];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg25_fsm_65 == ap_CS_fsm))) begin
tmp_249_reg_6860[1] <= tmp_249_fu_5132_p1[1];
tmp_249_reg_6860[2] <= tmp_249_fu_5132_p1[2];
tmp_249_reg_6860[3] <= tmp_249_fu_5132_p1[3];
tmp_249_reg_6860[4] <= tmp_249_fu_5132_p1[4];
tmp_249_reg_6860[5] <= tmp_249_fu_5132_p1[5];
tmp_249_reg_6860[6] <= tmp_249_fu_5132_p1[6];
tmp_249_reg_6860[7] <= tmp_249_fu_5132_p1[7];
tmp_249_reg_6860[8] <= tmp_249_fu_5132_p1[8];
tmp_249_reg_6860[9] <= tmp_249_fu_5132_p1[9];
tmp_249_reg_6860[10] <= tmp_249_fu_5132_p1[10];
tmp_249_reg_6860[11] <= tmp_249_fu_5132_p1[11];
tmp_249_reg_6860[12] <= tmp_249_fu_5132_p1[12];
tmp_249_reg_6860[13] <= tmp_249_fu_5132_p1[13];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg26_fsm_66 == ap_CS_fsm))) begin
tmp_250_reg_6870[0] <= tmp_250_fu_5136_p1[0];
tmp_250_reg_6870[1] <= tmp_250_fu_5136_p1[1];
tmp_250_reg_6870[2] <= tmp_250_fu_5136_p1[2];
tmp_250_reg_6870[3] <= tmp_250_fu_5136_p1[3];
tmp_250_reg_6870[4] <= tmp_250_fu_5136_p1[4];
tmp_250_reg_6870[5] <= tmp_250_fu_5136_p1[5];
tmp_250_reg_6870[6] <= tmp_250_fu_5136_p1[6];
tmp_250_reg_6870[7] <= tmp_250_fu_5136_p1[7];
tmp_250_reg_6870[8] <= tmp_250_fu_5136_p1[8];
tmp_250_reg_6870[9] <= tmp_250_fu_5136_p1[9];
tmp_250_reg_6870[10] <= tmp_250_fu_5136_p1[10];
tmp_250_reg_6870[11] <= tmp_250_fu_5136_p1[11];
tmp_250_reg_6870[12] <= tmp_250_fu_5136_p1[12];
tmp_250_reg_6870[13] <= tmp_250_fu_5136_p1[13];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg26_fsm_66 == ap_CS_fsm))) begin
tmp_251_reg_6880[2] <= tmp_251_fu_5140_p1[2];
tmp_251_reg_6880[3] <= tmp_251_fu_5140_p1[3];
tmp_251_reg_6880[4] <= tmp_251_fu_5140_p1[4];
tmp_251_reg_6880[5] <= tmp_251_fu_5140_p1[5];
tmp_251_reg_6880[6] <= tmp_251_fu_5140_p1[6];
tmp_251_reg_6880[7] <= tmp_251_fu_5140_p1[7];
tmp_251_reg_6880[8] <= tmp_251_fu_5140_p1[8];
tmp_251_reg_6880[9] <= tmp_251_fu_5140_p1[9];
tmp_251_reg_6880[10] <= tmp_251_fu_5140_p1[10];
tmp_251_reg_6880[11] <= tmp_251_fu_5140_p1[11];
tmp_251_reg_6880[12] <= tmp_251_fu_5140_p1[12];
tmp_251_reg_6880[13] <= tmp_251_fu_5140_p1[13];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg27_fsm_67 == ap_CS_fsm))) begin
tmp_252_reg_6890[0] <= tmp_252_fu_5144_p1[0];
tmp_252_reg_6890[1] <= tmp_252_fu_5144_p1[1];
tmp_252_reg_6890[2] <= tmp_252_fu_5144_p1[2];
tmp_252_reg_6890[3] <= tmp_252_fu_5144_p1[3];
tmp_252_reg_6890[4] <= tmp_252_fu_5144_p1[4];
tmp_252_reg_6890[5] <= tmp_252_fu_5144_p1[5];
tmp_252_reg_6890[6] <= tmp_252_fu_5144_p1[6];
tmp_252_reg_6890[7] <= tmp_252_fu_5144_p1[7];
tmp_252_reg_6890[8] <= tmp_252_fu_5144_p1[8];
tmp_252_reg_6890[9] <= tmp_252_fu_5144_p1[9];
tmp_252_reg_6890[10] <= tmp_252_fu_5144_p1[10];
tmp_252_reg_6890[11] <= tmp_252_fu_5144_p1[11];
tmp_252_reg_6890[12] <= tmp_252_fu_5144_p1[12];
tmp_252_reg_6890[13] <= tmp_252_fu_5144_p1[13];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg27_fsm_67 == ap_CS_fsm))) begin
tmp_253_reg_6900[1] <= tmp_253_fu_5148_p1[1];
tmp_253_reg_6900[2] <= tmp_253_fu_5148_p1[2];
tmp_253_reg_6900[3] <= tmp_253_fu_5148_p1[3];
tmp_253_reg_6900[4] <= tmp_253_fu_5148_p1[4];
tmp_253_reg_6900[5] <= tmp_253_fu_5148_p1[5];
tmp_253_reg_6900[6] <= tmp_253_fu_5148_p1[6];
tmp_253_reg_6900[7] <= tmp_253_fu_5148_p1[7];
tmp_253_reg_6900[8] <= tmp_253_fu_5148_p1[8];
tmp_253_reg_6900[9] <= tmp_253_fu_5148_p1[9];
tmp_253_reg_6900[10] <= tmp_253_fu_5148_p1[10];
tmp_253_reg_6900[11] <= tmp_253_fu_5148_p1[11];
tmp_253_reg_6900[12] <= tmp_253_fu_5148_p1[12];
tmp_253_reg_6900[13] <= tmp_253_fu_5148_p1[13];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg28_fsm_68 == ap_CS_fsm))) begin
tmp_254_reg_6910[0] <= tmp_254_fu_5152_p1[0];
tmp_254_reg_6910[1] <= tmp_254_fu_5152_p1[1];
tmp_254_reg_6910[2] <= tmp_254_fu_5152_p1[2];
tmp_254_reg_6910[3] <= tmp_254_fu_5152_p1[3];
tmp_254_reg_6910[4] <= tmp_254_fu_5152_p1[4];
tmp_254_reg_6910[5] <= tmp_254_fu_5152_p1[5];
tmp_254_reg_6910[6] <= tmp_254_fu_5152_p1[6];
tmp_254_reg_6910[7] <= tmp_254_fu_5152_p1[7];
tmp_254_reg_6910[8] <= tmp_254_fu_5152_p1[8];
tmp_254_reg_6910[9] <= tmp_254_fu_5152_p1[9];
tmp_254_reg_6910[10] <= tmp_254_fu_5152_p1[10];
tmp_254_reg_6910[11] <= tmp_254_fu_5152_p1[11];
tmp_254_reg_6910[12] <= tmp_254_fu_5152_p1[12];
tmp_254_reg_6910[13] <= tmp_254_fu_5152_p1[13];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg28_fsm_68 == ap_CS_fsm))) begin
tmp_255_reg_6920[3] <= tmp_255_fu_5156_p1[3];
tmp_255_reg_6920[4] <= tmp_255_fu_5156_p1[4];
tmp_255_reg_6920[5] <= tmp_255_fu_5156_p1[5];
tmp_255_reg_6920[6] <= tmp_255_fu_5156_p1[6];
tmp_255_reg_6920[7] <= tmp_255_fu_5156_p1[7];
tmp_255_reg_6920[8] <= tmp_255_fu_5156_p1[8];
tmp_255_reg_6920[9] <= tmp_255_fu_5156_p1[9];
tmp_255_reg_6920[10] <= tmp_255_fu_5156_p1[10];
tmp_255_reg_6920[11] <= tmp_255_fu_5156_p1[11];
tmp_255_reg_6920[12] <= tmp_255_fu_5156_p1[12];
tmp_255_reg_6920[13] <= tmp_255_fu_5156_p1[13];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond3_reg_5195) & (ap_ST_pp1_stg2_fsm_6 == ap_CS_fsm))) begin
tmp_28_reg_5332[0] <= tmp_28_fu_2740_p1[0];
tmp_28_reg_5332[1] <= tmp_28_fu_2740_p1[1];
tmp_28_reg_5332[2] <= tmp_28_fu_2740_p1[2];
tmp_28_reg_5332[3] <= tmp_28_fu_2740_p1[3];
tmp_28_reg_5332[4] <= tmp_28_fu_2740_p1[4];
tmp_28_reg_5332[5] <= tmp_28_fu_2740_p1[5];
tmp_28_reg_5332[6] <= tmp_28_fu_2740_p1[6];
tmp_28_reg_5332[7] <= tmp_28_fu_2740_p1[7];
tmp_28_reg_5332[8] <= tmp_28_fu_2740_p1[8];
tmp_28_reg_5332[9] <= tmp_28_fu_2740_p1[9];
tmp_28_reg_5332[10] <= tmp_28_fu_2740_p1[10];
tmp_28_reg_5332[11] <= tmp_28_fu_2740_p1[11];
tmp_28_reg_5332[12] <= tmp_28_fu_2740_p1[12];
tmp_28_reg_5332[13] <= tmp_28_fu_2740_p1[13];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond3_reg_5195) & (ap_ST_pp1_stg2_fsm_6 == ap_CS_fsm))) begin
tmp_36_reg_5347[0] <= tmp_36_fu_2794_p1[0];
tmp_36_reg_5347[1] <= tmp_36_fu_2794_p1[1];
tmp_36_reg_5347[2] <= tmp_36_fu_2794_p1[2];
tmp_36_reg_5347[3] <= tmp_36_fu_2794_p1[3];
tmp_36_reg_5347[4] <= tmp_36_fu_2794_p1[4];
tmp_36_reg_5347[5] <= tmp_36_fu_2794_p1[5];
tmp_36_reg_5347[6] <= tmp_36_fu_2794_p1[6];
tmp_36_reg_5347[7] <= tmp_36_fu_2794_p1[7];
tmp_36_reg_5347[8] <= tmp_36_fu_2794_p1[8];
tmp_36_reg_5347[9] <= tmp_36_fu_2794_p1[9];
tmp_36_reg_5347[10] <= tmp_36_fu_2794_p1[10];
tmp_36_reg_5347[11] <= tmp_36_fu_2794_p1[11];
tmp_36_reg_5347[12] <= tmp_36_fu_2794_p1[12];
tmp_36_reg_5347[13] <= tmp_36_fu_2794_p1[13];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond3_reg_5195) & (ap_ST_pp1_stg4_fsm_8 == ap_CS_fsm))) begin
tmp_43_reg_5402 <= (i_1_mid2_reg_5204 + ap_const_lv7_8);
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond3_reg_5195) & (ap_ST_pp1_stg3_fsm_7 == ap_CS_fsm))) begin
tmp_44_reg_5367[0] <= tmp_44_fu_2847_p1[0];
tmp_44_reg_5367[1] <= tmp_44_fu_2847_p1[1];
tmp_44_reg_5367[2] <= tmp_44_fu_2847_p1[2];
tmp_44_reg_5367[3] <= tmp_44_fu_2847_p1[3];
tmp_44_reg_5367[4] <= tmp_44_fu_2847_p1[4];
tmp_44_reg_5367[5] <= tmp_44_fu_2847_p1[5];
tmp_44_reg_5367[6] <= tmp_44_fu_2847_p1[6];
tmp_44_reg_5367[7] <= tmp_44_fu_2847_p1[7];
tmp_44_reg_5367[8] <= tmp_44_fu_2847_p1[8];
tmp_44_reg_5367[9] <= tmp_44_fu_2847_p1[9];
tmp_44_reg_5367[10] <= tmp_44_fu_2847_p1[10];
tmp_44_reg_5367[11] <= tmp_44_fu_2847_p1[11];
tmp_44_reg_5367[12] <= tmp_44_fu_2847_p1[12];
tmp_44_reg_5367[13] <= tmp_44_fu_2847_p1[13];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp3_it0) & (ap_ST_pp3_stg0_fsm_13 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond6_fu_3025_p2))) begin
tmp_44_trn_cast_reg_5477 <= {{7{j_1_mid2_fu_3057_p3[6]}}, {j_1_mid2_fu_3057_p3}};
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp3_it0) & (ap_const_lv1_0 == exitcond6_reg_5446) & (ap_ST_pp3_stg1_fsm_14 == ap_CS_fsm))) begin
tmp_46_trn_cast4_reg_5553 <= {{tmp_46_trn_cast_fu_3121_p1[ap_const_lv32_C : ap_const_lv32_6]}};
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp3_it0) & (ap_const_lv1_0 == exitcond6_reg_5446) & (ap_ST_pp3_stg1_fsm_14 == ap_CS_fsm))) begin
tmp_46_trn_cast5_reg_5558 <= {{tmp_46_trn_cast_fu_3121_p1[ap_const_lv32_C : ap_const_lv32_6]}};
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp3_it0) & (ap_const_lv1_0 == exitcond6_reg_5446) & (ap_ST_pp3_stg1_fsm_14 == ap_CS_fsm))) begin
tmp_46_trn_cast6_reg_5563 <= {{tmp_46_trn_cast_fu_3121_p1[ap_const_lv32_C : ap_const_lv32_6]}};
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp3_it0) & (ap_const_lv1_0 == exitcond6_reg_5446) & (ap_ST_pp3_stg1_fsm_14 == ap_CS_fsm))) begin
tmp_46_trn_cast7_reg_5568 <= {{tmp_46_trn_cast_fu_3121_p1[ap_const_lv32_C : ap_const_lv32_6]}};
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp3_it0) & (ap_const_lv1_0 == exitcond6_reg_5446) & (ap_ST_pp3_stg1_fsm_14 == ap_CS_fsm))) begin
tmp_46_trn_cast8_reg_5573 <= {{tmp_46_trn_cast_fu_3121_p1[ap_const_lv32_C : ap_const_lv32_6]}};
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp3_it0) & (ap_const_lv1_0 == exitcond6_reg_5446) & (ap_ST_pp3_stg1_fsm_14 == ap_CS_fsm))) begin
tmp_46_trn_cast_reg_5508[0] <= tmp_46_trn_cast_fu_3121_p1[0];
tmp_46_trn_cast_reg_5508[1] <= tmp_46_trn_cast_fu_3121_p1[1];
tmp_46_trn_cast_reg_5508[2] <= tmp_46_trn_cast_fu_3121_p1[2];
tmp_46_trn_cast_reg_5508[3] <= tmp_46_trn_cast_fu_3121_p1[3];
tmp_46_trn_cast_reg_5508[4] <= tmp_46_trn_cast_fu_3121_p1[4];
tmp_46_trn_cast_reg_5508[5] <= tmp_46_trn_cast_fu_3121_p1[5];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_ST_pp1_stg3_fsm_7 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond3_reg_5195_pp1_it1))) begin
tmp_47_reg_5407[0] <= tmp_47_fu_2980_p1[0];
tmp_47_reg_5407[1] <= tmp_47_fu_2980_p1[1];
tmp_47_reg_5407[2] <= tmp_47_fu_2980_p1[2];
tmp_47_reg_5407[3] <= tmp_47_fu_2980_p1[3];
tmp_47_reg_5407[4] <= tmp_47_fu_2980_p1[4];
tmp_47_reg_5407[5] <= tmp_47_fu_2980_p1[5];
tmp_47_reg_5407[6] <= tmp_47_fu_2980_p1[6];
tmp_47_reg_5407[7] <= tmp_47_fu_2980_p1[7];
tmp_47_reg_5407[8] <= tmp_47_fu_2980_p1[8];
tmp_47_reg_5407[9] <= tmp_47_fu_2980_p1[9];
tmp_47_reg_5407[10] <= tmp_47_fu_2980_p1[10];
tmp_47_reg_5407[11] <= tmp_47_fu_2980_p1[11];
tmp_47_reg_5407[12] <= tmp_47_fu_2980_p1[12];
tmp_47_reg_5407[13] <= tmp_47_fu_2980_p1[13];
end
if (((ap_ST_pp4_stg0_fsm_21 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp4_it0))) begin
tmp_49_reg_5682 <= (j_2_phi_fu_2000_p4 + ap_const_lv7_1);
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_ST_pp1_stg4_fsm_8 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond3_reg_5195_pp1_it1))) begin
tmp_51_reg_5417[0] <= tmp_51_fu_2984_p1[0];
tmp_51_reg_5417[1] <= tmp_51_fu_2984_p1[1];
tmp_51_reg_5417[2] <= tmp_51_fu_2984_p1[2];
tmp_51_reg_5417[3] <= tmp_51_fu_2984_p1[3];
tmp_51_reg_5417[4] <= tmp_51_fu_2984_p1[4];
tmp_51_reg_5417[5] <= tmp_51_fu_2984_p1[5];
tmp_51_reg_5417[6] <= tmp_51_fu_2984_p1[6];
tmp_51_reg_5417[7] <= tmp_51_fu_2984_p1[7];
tmp_51_reg_5417[8] <= tmp_51_fu_2984_p1[8];
tmp_51_reg_5417[9] <= tmp_51_fu_2984_p1[9];
tmp_51_reg_5417[10] <= tmp_51_fu_2984_p1[10];
tmp_51_reg_5417[11] <= tmp_51_fu_2984_p1[11];
tmp_51_reg_5417[12] <= tmp_51_fu_2984_p1[12];
tmp_51_reg_5417[13] <= tmp_51_fu_2984_p1[13];
end
if (((ap_ST_pp2_stg0_fsm_12 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp2_it0) & (ap_const_lv1_0 == exitcond4_fu_2988_p2))) begin
tmp_59_reg_5436[0] <= tmp_59_fu_3020_p1[0];
tmp_59_reg_5436[1] <= tmp_59_fu_3020_p1[1];
tmp_59_reg_5436[2] <= tmp_59_fu_3020_p1[2];
tmp_59_reg_5436[3] <= tmp_59_fu_3020_p1[3];
tmp_59_reg_5436[4] <= tmp_59_fu_3020_p1[4];
tmp_59_reg_5436[5] <= tmp_59_fu_3020_p1[5];
tmp_59_reg_5436[6] <= tmp_59_fu_3020_p1[6];
tmp_59_reg_5436[7] <= tmp_59_fu_3020_p1[7];
tmp_59_reg_5436[8] <= tmp_59_fu_3020_p1[8];
tmp_59_reg_5436[9] <= tmp_59_fu_3020_p1[9];
tmp_59_reg_5436[10] <= tmp_59_fu_3020_p1[10];
tmp_59_reg_5436[11] <= tmp_59_fu_3020_p1[11];
tmp_59_reg_5436[12] <= tmp_59_fu_3020_p1[12];
end
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0))) begin
tmp_5_reg_5175 <= (i_phi_fu_1890_p4 + ap_const_lv7_1);
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp3_it0) & (ap_ST_pp3_stg0_fsm_13 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond6_fu_3025_p2))) begin
tmp_67_reg_5488 <= {{50{b_addr11_fu_3087_p2[13]}}, {b_addr11_fu_3087_p2}};
end
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (ap_const_lv1_0 == exitcond1_fu_2377_p2))) begin
tmp_6_reg_5180[6] <= tmp_6_fu_2399_p1[6];
tmp_6_reg_5180[7] <= tmp_6_fu_2399_p1[7];
tmp_6_reg_5180[8] <= tmp_6_fu_2399_p1[8];
tmp_6_reg_5180[9] <= tmp_6_fu_2399_p1[9];
tmp_6_reg_5180[10] <= tmp_6_fu_2399_p1[10];
tmp_6_reg_5180[11] <= tmp_6_fu_2399_p1[11];
tmp_6_reg_5180[12] <= tmp_6_fu_2399_p1[12];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_ST_pp1_stg0_fsm_4 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond3_fu_2404_p2))) begin
tmp_6_trn_cast_reg_5226[0] <= tmp_6_trn_cast_fu_2452_p1[0];
tmp_6_trn_cast_reg_5226[1] <= tmp_6_trn_cast_fu_2452_p1[1];
tmp_6_trn_cast_reg_5226[2] <= tmp_6_trn_cast_fu_2452_p1[2];
tmp_6_trn_cast_reg_5226[3] <= tmp_6_trn_cast_fu_2452_p1[3];
tmp_6_trn_cast_reg_5226[4] <= tmp_6_trn_cast_fu_2452_p1[4];
tmp_6_trn_cast_reg_5226[5] <= tmp_6_trn_cast_fu_2452_p1[5];
tmp_6_trn_cast_reg_5226[6] <= tmp_6_trn_cast_fu_2452_p1[6];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp3_it0) & (ap_const_lv1_0 == exitcond6_reg_5446) & (ap_ST_pp3_stg1_fsm_14 == ap_CS_fsm))) begin
tmp_75_reg_5523 <= {{50{b_addr13_fu_3176_p2[13]}}, {b_addr13_fu_3176_p2}};
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp3_it0) & (ap_const_lv1_0 == exitcond6_reg_5446) & (ap_ST_pp3_stg4_fsm_17 == ap_CS_fsm))) begin
tmp_82_reg_5653 <= (i_3_mid2_reg_5455 + ap_const_lv7_8);
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp3_it0) & (ap_const_lv1_0 == exitcond6_reg_5446) & (ap_ST_pp3_stg1_fsm_14 == ap_CS_fsm))) begin
tmp_83_reg_5538 <= {{50{b_addr15_fu_3242_p2[13]}}, {b_addr15_fu_3242_p2}};
end
if (((ap_ST_pp3_stg2_fsm_15 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp3_it0) & (ap_const_lv1_0 == exitcond6_reg_5446))) begin
tmp_86_reg_5583 <= {{50{b_addr17_fu_3356_p2[13]}}, {b_addr17_fu_3356_p2}};
end
if (((ap_ST_pp6_stg0_fsm_30 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp6_it0))) begin
tmp_88_reg_5909 <= (j_4_phi_fu_2055_p4 + ap_const_lv7_1);
end
if (((ap_ST_pp1_stg1_fsm_5 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond3_reg_5195))) begin
tmp_8_trn_cast4_reg_5302 <= {{tmp_8_trn_cast_fu_2500_p1[ap_const_lv32_C : ap_const_lv32_6]}};
end
if (((ap_ST_pp1_stg1_fsm_5 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond3_reg_5195))) begin
tmp_8_trn_cast5_reg_5307 <= {{tmp_8_trn_cast_fu_2500_p1[ap_const_lv32_C : ap_const_lv32_6]}};
end
if (((ap_ST_pp1_stg1_fsm_5 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond3_reg_5195))) begin
tmp_8_trn_cast6_reg_5312 <= {{tmp_8_trn_cast_fu_2500_p1[ap_const_lv32_C : ap_const_lv32_6]}};
end
if (((ap_ST_pp1_stg1_fsm_5 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond3_reg_5195))) begin
tmp_8_trn_cast7_reg_5317 <= {{tmp_8_trn_cast_fu_2500_p1[ap_const_lv32_C : ap_const_lv32_6]}};
end
if (((ap_ST_pp1_stg1_fsm_5 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond3_reg_5195))) begin
tmp_8_trn_cast8_reg_5322 <= {{tmp_8_trn_cast_fu_2500_p1[ap_const_lv32_C : ap_const_lv32_6]}};
end
if (((ap_ST_pp1_stg1_fsm_5 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond3_reg_5195))) begin
tmp_8_trn_cast_reg_5257[0] <= tmp_8_trn_cast_fu_2500_p1[0];
tmp_8_trn_cast_reg_5257[1] <= tmp_8_trn_cast_fu_2500_p1[1];
tmp_8_trn_cast_reg_5257[2] <= tmp_8_trn_cast_fu_2500_p1[2];
tmp_8_trn_cast_reg_5257[3] <= tmp_8_trn_cast_fu_2500_p1[3];
tmp_8_trn_cast_reg_5257[4] <= tmp_8_trn_cast_fu_2500_p1[4];
tmp_8_trn_cast_reg_5257[5] <= tmp_8_trn_cast_fu_2500_p1[5];
end
if (((ap_ST_pp3_stg2_fsm_15 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp3_it0) & (ap_const_lv1_0 == exitcond6_reg_5446))) begin
tmp_90_reg_5598 <= {{50{b_addr19_fu_3410_p2[13]}}, {b_addr19_fu_3410_p2}};
end
if (((ap_ST_pp5_stg1_fsm_23 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp5_it0) & (ap_const_lv1_0 == exitcond9_reg_5697))) begin
tmp_97_reg_5785[0] <= tmp_97_fu_3780_p2[0];
tmp_97_reg_5785[2] <= tmp_97_fu_3780_p2[2];
tmp_97_reg_5785[3] <= tmp_97_fu_3780_p2[3];
tmp_97_reg_5785[4] <= tmp_97_fu_3780_p2[4];
tmp_97_reg_5785[5] <= tmp_97_fu_3780_p2[5];
tmp_97_reg_5785[6] <= tmp_97_fu_3780_p2[6];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp3_it0) & (ap_const_lv1_0 == exitcond6_reg_5446) & (ap_ST_pp3_stg3_fsm_16 == ap_CS_fsm))) begin
tmp_98_reg_5618 <= {{50{b_addr21_fu_3463_p2[13]}}, {b_addr21_fu_3463_p2}};
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_ST_pp1_stg0_fsm_4 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond3_fu_2404_p2))) begin
tmp_9_reg_5237[0] <= tmp_9_fu_2472_p1[0];
tmp_9_reg_5237[1] <= tmp_9_fu_2472_p1[1];
tmp_9_reg_5237[2] <= tmp_9_fu_2472_p1[2];
tmp_9_reg_5237[3] <= tmp_9_fu_2472_p1[3];
tmp_9_reg_5237[4] <= tmp_9_fu_2472_p1[4];
tmp_9_reg_5237[5] <= tmp_9_fu_2472_p1[5];
tmp_9_reg_5237[6] <= tmp_9_fu_2472_p1[6];
tmp_9_reg_5237[7] <= tmp_9_fu_2472_p1[7];
tmp_9_reg_5237[8] <= tmp_9_fu_2472_p1[8];
tmp_9_reg_5237[9] <= tmp_9_fu_2472_p1[9];
tmp_9_reg_5237[10] <= tmp_9_fu_2472_p1[10];
tmp_9_reg_5237[11] <= tmp_9_fu_2472_p1[11];
tmp_9_reg_5237[12] <= tmp_9_fu_2472_p1[12];
tmp_9_reg_5237[13] <= tmp_9_fu_2472_p1[13];
end
end
/// a_address0 assign process. ///
always @ (ap_CS_fsm or ap_reg_ppiten_pp0_it0 or ap_reg_ppiten_pp1_it0 or ap_reg_ppiten_pp1_it1 or exitcond3_reg_5195 or ap_reg_ppiten_pp3_it0 or ap_reg_ppiten_pp3_it1 or ap_reg_ppiten_pp3_it2 or exitcond6_reg_5446 or ap_reg_ppiten_pp4_it0 or ap_reg_ppiten_pp5_it0 or ap_reg_ppiten_pp5_it1 or exitcond9_reg_5697 or ap_reg_ppiten_pp7_it0 or ap_reg_ppiten_pp7_it1 or ap_reg_ppiten_pp7_it2 or exitcond12_reg_5924 or ap_reg_ppiten_pp2_it6 or ap_reg_ppiten_pp6_it6 or ap_reg_ppstg_exitcond6_reg_5446_pp3_it1 or ap_reg_ppstg_exitcond12_reg_5924_pp7_it1 or ap_reg_ppstg_exitcond3_reg_5195_pp1_it1 or ap_reg_ppstg_exitcond9_reg_5697_pp5_it1 or exitcond1_fu_2377_p2 or tmp_6_fu_2399_p1 or exitcond3_fu_2404_p2 or tmp_9_fu_2472_p1 or tmp_15_fu_2560_p1 or tmp_28_fu_2740_p1 or tmp_44_fu_2847_p1 or tmp_51_fu_2984_p1 or ap_reg_ppstg_exitcond4_reg_5427_pp2_it5 or ap_reg_ppstg_tmp_59_reg_5436_pp2_it5 or ap_reg_ppstg_tmp_67_reg_5488_pp3_it1 or ap_reg_ppstg_tmp_83_reg_5538_pp3_it1 or ap_reg_ppstg_tmp_86_reg_5583_pp3_it1 or ap_reg_ppstg_tmp_90_reg_5598_pp3_it1 or exitcond7_fu_3609_p2 or tmp_122_fu_3621_p1 or exitcond9_fu_3626_p2 or tmp_125_fu_3694_p1 or tmp_130_fu_3764_p1 or tmp_146_fu_3830_p1 or tmp_160_fu_3895_p1 or tmp_168_fu_3974_p1 or ap_reg_ppstg_exitcond10_reg_5905_pp6_it5 or ap_reg_ppstg_tmp_172_reg_5914_pp6_it5 or ap_reg_ppstg_tmp_174_reg_5967_pp7_it1 or ap_reg_ppstg_tmp_182_reg_6017_pp7_it1 or ap_reg_ppstg_tmp_186_reg_6032_pp7_it1 or ap_reg_ppstg_tmp_190_reg_6052_pp7_it1 or exitcond_fu_4357_p2 or exitcond_reg_6132 or ap_reg_ppiten_pp8_it0 or tmp_199_fu_4421_p1 or tmp_200_fu_4454_p1 or tmp_202_fu_4492_p1 or tmp_204_fu_4530_p1 or tmp_206_fu_4573_p1 or tmp_208_fu_4611_p1 or tmp_210_fu_4629_p1 or tmp_212_fu_4647_p1 or tmp_214_fu_4685_p1 or tmp_216_fu_4704_p1 or tmp_218_fu_4722_p1 or tmp_220_fu_4745_p1 or tmp_222_fu_4778_p1 or tmp_224_fu_4796_p1 or tmp_226_fu_4814_p1 or tmp_228_fu_4852_p1 or tmp_230_fu_4871_p1 or tmp_232_fu_4889_p1 or tmp_234_fu_4912_p1 or tmp_236_fu_4945_p1 or tmp_238_fu_4963_p1 or tmp_240_fu_4981_p1 or tmp_242_fu_5019_p1 or tmp_244_fu_5038_p1 or tmp_246_fu_5061_p1 or tmp_248_fu_5128_p1 or tmp_250_fu_5136_p1 or tmp_252_fu_5144_p1 or tmp_254_fu_5152_p1 or tmp_71_fu_3152_p1 or tmp_85_fu_3332_p1 or tmp_94_fu_3439_p1 or tmp_110_fu_3542_p1 or tmp_176_fu_4120_p1 or tmp_184_fu_4186_p1 or tmp_191_fu_4251_p1 or tmp_196_fu_4303_p1)
begin
if (((ap_const_logic_1 == ap_reg_ppiten_pp7_it2) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond12_reg_5924_pp7_it1) & (ap_ST_pp7_stg0_fsm_31 == ap_CS_fsm))) begin
a_address0 = ap_reg_ppstg_tmp_190_reg_6052_pp7_it1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp7_it1) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond12_reg_5924_pp7_it1) & (ap_ST_pp7_stg7_fsm_38 == ap_CS_fsm))) begin
a_address0 = ap_reg_ppstg_tmp_186_reg_6032_pp7_it1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp7_it1) & (ap_ST_pp7_stg6_fsm_37 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond12_reg_5924_pp7_it1))) begin
a_address0 = ap_reg_ppstg_tmp_182_reg_6017_pp7_it1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp7_it1) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond12_reg_5924_pp7_it1) & (ap_ST_pp7_stg5_fsm_36 == ap_CS_fsm))) begin
a_address0 = ap_reg_ppstg_tmp_174_reg_5967_pp7_it1;
end else if (((ap_ST_pp6_stg0_fsm_30 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp6_it6) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond10_reg_5905_pp6_it5))) begin
a_address0 = ap_reg_ppstg_tmp_172_reg_5914_pp6_it5;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp3_it2) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond6_reg_5446_pp3_it1) & (ap_ST_pp3_stg0_fsm_13 == ap_CS_fsm))) begin
a_address0 = ap_reg_ppstg_tmp_90_reg_5598_pp3_it1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp3_it1) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond6_reg_5446_pp3_it1) & (ap_ST_pp3_stg7_fsm_20 == ap_CS_fsm))) begin
a_address0 = ap_reg_ppstg_tmp_86_reg_5583_pp3_it1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp3_it1) & (ap_ST_pp3_stg6_fsm_19 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond6_reg_5446_pp3_it1))) begin
a_address0 = ap_reg_ppstg_tmp_83_reg_5538_pp3_it1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp3_it1) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond6_reg_5446_pp3_it1) & (ap_ST_pp3_stg5_fsm_18 == ap_CS_fsm))) begin
a_address0 = ap_reg_ppstg_tmp_67_reg_5488_pp3_it1;
end else if (((ap_ST_pp2_stg0_fsm_12 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp2_it6) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond4_reg_5427_pp2_it5))) begin
a_address0 = ap_reg_ppstg_tmp_59_reg_5436_pp2_it5;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg28_fsm_68 == ap_CS_fsm))) begin
a_address0 = tmp_254_fu_5152_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg27_fsm_67 == ap_CS_fsm))) begin
a_address0 = tmp_252_fu_5144_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg26_fsm_66 == ap_CS_fsm))) begin
a_address0 = tmp_250_fu_5136_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg25_fsm_65 == ap_CS_fsm))) begin
a_address0 = tmp_248_fu_5128_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg24_fsm_64 == ap_CS_fsm))) begin
a_address0 = tmp_246_fu_5061_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg23_fsm_63 == ap_CS_fsm))) begin
a_address0 = tmp_244_fu_5038_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg22_fsm_62 == ap_CS_fsm))) begin
a_address0 = tmp_242_fu_5019_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg21_fsm_61 == ap_CS_fsm))) begin
a_address0 = tmp_240_fu_4981_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg20_fsm_60 == ap_CS_fsm))) begin
a_address0 = tmp_238_fu_4963_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg19_fsm_59 == ap_CS_fsm))) begin
a_address0 = tmp_236_fu_4945_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg18_fsm_58 == ap_CS_fsm))) begin
a_address0 = tmp_234_fu_4912_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg17_fsm_57 == ap_CS_fsm))) begin
a_address0 = tmp_232_fu_4889_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg16_fsm_56 == ap_CS_fsm))) begin
a_address0 = tmp_230_fu_4871_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg15_fsm_55 == ap_CS_fsm))) begin
a_address0 = tmp_228_fu_4852_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg14_fsm_54 == ap_CS_fsm))) begin
a_address0 = tmp_226_fu_4814_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg13_fsm_53 == ap_CS_fsm))) begin
a_address0 = tmp_224_fu_4796_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg12_fsm_52 == ap_CS_fsm))) begin
a_address0 = tmp_222_fu_4778_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg11_fsm_51 == ap_CS_fsm))) begin
a_address0 = tmp_220_fu_4745_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg10_fsm_50 == ap_CS_fsm))) begin
a_address0 = tmp_218_fu_4722_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg9_fsm_49 == ap_CS_fsm))) begin
a_address0 = tmp_216_fu_4704_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg8_fsm_48 == ap_CS_fsm))) begin
a_address0 = tmp_214_fu_4685_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg7_fsm_47 == ap_CS_fsm))) begin
a_address0 = tmp_212_fu_4647_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg6_fsm_46 == ap_CS_fsm))) begin
a_address0 = tmp_210_fu_4629_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg5_fsm_45 == ap_CS_fsm))) begin
a_address0 = tmp_208_fu_4611_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg4_fsm_44 == ap_CS_fsm))) begin
a_address0 = tmp_206_fu_4573_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg3_fsm_43 == ap_CS_fsm))) begin
a_address0 = tmp_204_fu_4530_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg2_fsm_42 == ap_CS_fsm))) begin
a_address0 = tmp_202_fu_4492_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_ST_pp8_stg1_fsm_41 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond_reg_6132))) begin
a_address0 = tmp_200_fu_4454_p1;
end else if (((ap_ST_pp8_stg0_fsm_40 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_fu_4357_p2))) begin
a_address0 = tmp_199_fu_4421_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp7_it0) & (ap_const_lv1_0 == exitcond12_reg_5924) & (ap_ST_pp7_stg4_fsm_35 == ap_CS_fsm))) begin
a_address0 = tmp_196_fu_4303_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp7_it0) & (ap_const_lv1_0 == exitcond12_reg_5924) & (ap_ST_pp7_stg3_fsm_34 == ap_CS_fsm))) begin
a_address0 = tmp_191_fu_4251_p1;
end else if (((ap_ST_pp7_stg2_fsm_33 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp7_it0) & (ap_const_lv1_0 == exitcond12_reg_5924))) begin
a_address0 = tmp_184_fu_4186_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp7_it0) & (ap_const_lv1_0 == exitcond12_reg_5924) & (ap_ST_pp7_stg1_fsm_32 == ap_CS_fsm))) begin
a_address0 = tmp_176_fu_4120_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp5_it1) & (ap_ST_pp5_stg4_fsm_26 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond9_reg_5697_pp5_it1))) begin
a_address0 = tmp_168_fu_3974_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp5_it0) & (ap_const_lv1_0 == exitcond9_reg_5697) & (ap_ST_pp5_stg3_fsm_25 == ap_CS_fsm))) begin
a_address0 = tmp_160_fu_3895_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp5_it0) & (ap_const_lv1_0 == exitcond9_reg_5697) & (ap_ST_pp5_stg2_fsm_24 == ap_CS_fsm))) begin
a_address0 = tmp_146_fu_3830_p1;
end else if (((ap_ST_pp5_stg1_fsm_23 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp5_it0) & (ap_const_lv1_0 == exitcond9_reg_5697))) begin
a_address0 = tmp_130_fu_3764_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp5_it0) & (ap_ST_pp5_stg0_fsm_22 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond9_fu_3626_p2))) begin
a_address0 = tmp_125_fu_3694_p1;
end else if (((ap_ST_pp4_stg0_fsm_21 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp4_it0) & (ap_const_lv1_0 == exitcond7_fu_3609_p2))) begin
a_address0 = tmp_122_fu_3621_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp3_it0) & (ap_const_lv1_0 == exitcond6_reg_5446) & (ap_ST_pp3_stg4_fsm_17 == ap_CS_fsm))) begin
a_address0 = tmp_110_fu_3542_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp3_it0) & (ap_const_lv1_0 == exitcond6_reg_5446) & (ap_ST_pp3_stg3_fsm_16 == ap_CS_fsm))) begin
a_address0 = tmp_94_fu_3439_p1;
end else if (((ap_ST_pp3_stg2_fsm_15 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp3_it0) & (ap_const_lv1_0 == exitcond6_reg_5446))) begin
a_address0 = tmp_85_fu_3332_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp3_it0) & (ap_const_lv1_0 == exitcond6_reg_5446) & (ap_ST_pp3_stg1_fsm_14 == ap_CS_fsm))) begin
a_address0 = tmp_71_fu_3152_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_ST_pp1_stg4_fsm_8 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond3_reg_5195_pp1_it1))) begin
a_address0 = tmp_51_fu_2984_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond3_reg_5195) & (ap_ST_pp1_stg3_fsm_7 == ap_CS_fsm))) begin
a_address0 = tmp_44_fu_2847_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond3_reg_5195) & (ap_ST_pp1_stg2_fsm_6 == ap_CS_fsm))) begin
a_address0 = tmp_28_fu_2740_p1;
end else if (((ap_ST_pp1_stg1_fsm_5 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond3_reg_5195))) begin
a_address0 = tmp_15_fu_2560_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_ST_pp1_stg0_fsm_4 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond3_fu_2404_p2))) begin
a_address0 = tmp_9_fu_2472_p1;
end else if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (ap_const_lv1_0 == exitcond1_fu_2377_p2))) begin
a_address0 = tmp_6_fu_2399_p1;
end else begin
a_address0 = ap_reg_ppstg_tmp_190_reg_6052_pp7_it1;
end
end
/// a_address1 assign process. ///
always @ (ap_CS_fsm or ap_reg_ppiten_pp1_it0 or ap_reg_ppiten_pp1_it1 or exitcond3_reg_5195 or ap_reg_ppiten_pp3_it0 or ap_reg_ppiten_pp3_it1 or ap_reg_ppiten_pp3_it2 or exitcond6_reg_5446 or ap_reg_ppiten_pp5_it0 or ap_reg_ppiten_pp5_it1 or exitcond9_reg_5697 or ap_reg_ppiten_pp7_it0 or ap_reg_ppiten_pp7_it1 or ap_reg_ppiten_pp7_it2 or exitcond12_reg_5924 or ap_reg_ppstg_exitcond6_reg_5446_pp3_it1 or ap_reg_ppstg_exitcond12_reg_5924_pp7_it1 or ap_reg_ppiten_pp3_it3 or ap_reg_ppiten_pp7_it3 or ap_reg_ppstg_exitcond3_reg_5195_pp1_it1 or ap_reg_ppstg_exitcond9_reg_5697_pp5_it1 or ap_reg_ppstg_exitcond6_reg_5446_pp3_it2 or ap_reg_ppstg_exitcond12_reg_5924_pp7_it2 or tmp_20_fu_2626_p1 or tmp_36_fu_2794_p1 or tmp_47_fu_2980_p1 or ap_reg_ppstg_tmp_75_reg_5523_pp3_it1 or ap_reg_ppstg_tmp_98_reg_5618_pp3_it2 or ap_reg_ppstg_tmp_106_reg_5658_pp3_it2 or ap_reg_ppstg_tmp_114_reg_5668_pp3_it2 or tmp_138_fu_3794_p1 or tmp_154_fu_3859_p1 or tmp_164_fu_3961_p1 or ap_reg_ppstg_tmp_178_reg_5997_pp7_it1 or ap_reg_ppstg_tmp_192_reg_6067_pp7_it2 or ap_reg_ppstg_tmp_194_reg_6107_pp7_it2 or ap_reg_ppstg_tmp_197_reg_6122_pp7_it2 or exitcond_reg_6132 or ap_reg_ppiten_pp8_it0 or tmp_201_fu_4473_p1 or tmp_203_fu_4511_p1 or tmp_205_fu_4549_p1 or tmp_207_fu_4597_p1 or tmp_209_fu_4620_p1 or tmp_211_fu_4638_p1 or tmp_213_fu_4656_p1 or tmp_215_fu_4695_p1 or tmp_217_fu_4713_p1 or tmp_219_fu_4731_p1 or tmp_221_fu_4769_p1 or tmp_223_fu_4787_p1 or tmp_225_fu_4805_p1 or tmp_227_fu_4823_p1 or tmp_229_fu_4862_p1 or tmp_231_fu_4880_p1 or tmp_233_fu_4898_p1 or tmp_235_fu_4936_p1 or tmp_237_fu_4954_p1 or tmp_239_fu_4972_p1 or tmp_241_fu_4990_p1 or tmp_243_fu_5029_p1 or tmp_245_fu_5047_p1 or tmp_247_fu_5070_p1 or tmp_249_fu_5132_p1 or tmp_251_fu_5140_p1 or tmp_253_fu_5148_p1 or tmp_255_fu_5156_p1 or tmp_79_fu_3218_p1 or tmp_89_fu_3386_p1 or tmp_102_fu_3493_p1 or tmp_118_fu_3591_p1 or tmp_180_fu_4154_p1 or tmp_188_fu_4219_p1 or tmp_193_fu_4284_p1 or tmp_198_fu_4322_p1)
begin
if (((ap_ST_pp7_stg0_fsm_31 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp7_it3) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond12_reg_5924_pp7_it2))) begin
a_address1 = ap_reg_ppstg_tmp_197_reg_6122_pp7_it2;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp7_it2) & (ap_ST_pp7_stg7_fsm_38 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond12_reg_5924_pp7_it2))) begin
a_address1 = ap_reg_ppstg_tmp_194_reg_6107_pp7_it2;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp7_it2) & (ap_ST_pp7_stg6_fsm_37 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond12_reg_5924_pp7_it2))) begin
a_address1 = ap_reg_ppstg_tmp_192_reg_6067_pp7_it2;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp7_it1) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond12_reg_5924_pp7_it1) & (ap_ST_pp7_stg5_fsm_36 == ap_CS_fsm))) begin
a_address1 = ap_reg_ppstg_tmp_178_reg_5997_pp7_it1;
end else if (((ap_ST_pp3_stg0_fsm_13 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp3_it3) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond6_reg_5446_pp3_it2))) begin
a_address1 = ap_reg_ppstg_tmp_114_reg_5668_pp3_it2;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp3_it2) & (ap_ST_pp3_stg7_fsm_20 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond6_reg_5446_pp3_it2))) begin
a_address1 = ap_reg_ppstg_tmp_106_reg_5658_pp3_it2;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp3_it2) & (ap_ST_pp3_stg6_fsm_19 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond6_reg_5446_pp3_it2))) begin
a_address1 = ap_reg_ppstg_tmp_98_reg_5618_pp3_it2;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp3_it1) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond6_reg_5446_pp3_it1) & (ap_ST_pp3_stg5_fsm_18 == ap_CS_fsm))) begin
a_address1 = ap_reg_ppstg_tmp_75_reg_5523_pp3_it1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg28_fsm_68 == ap_CS_fsm))) begin
a_address1 = tmp_255_fu_5156_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg27_fsm_67 == ap_CS_fsm))) begin
a_address1 = tmp_253_fu_5148_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg26_fsm_66 == ap_CS_fsm))) begin
a_address1 = tmp_251_fu_5140_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg25_fsm_65 == ap_CS_fsm))) begin
a_address1 = tmp_249_fu_5132_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg24_fsm_64 == ap_CS_fsm))) begin
a_address1 = tmp_247_fu_5070_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg23_fsm_63 == ap_CS_fsm))) begin
a_address1 = tmp_245_fu_5047_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg22_fsm_62 == ap_CS_fsm))) begin
a_address1 = tmp_243_fu_5029_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg21_fsm_61 == ap_CS_fsm))) begin
a_address1 = tmp_241_fu_4990_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg20_fsm_60 == ap_CS_fsm))) begin
a_address1 = tmp_239_fu_4972_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg19_fsm_59 == ap_CS_fsm))) begin
a_address1 = tmp_237_fu_4954_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg18_fsm_58 == ap_CS_fsm))) begin
a_address1 = tmp_235_fu_4936_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg17_fsm_57 == ap_CS_fsm))) begin
a_address1 = tmp_233_fu_4898_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg16_fsm_56 == ap_CS_fsm))) begin
a_address1 = tmp_231_fu_4880_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg15_fsm_55 == ap_CS_fsm))) begin
a_address1 = tmp_229_fu_4862_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg14_fsm_54 == ap_CS_fsm))) begin
a_address1 = tmp_227_fu_4823_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg13_fsm_53 == ap_CS_fsm))) begin
a_address1 = tmp_225_fu_4805_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg12_fsm_52 == ap_CS_fsm))) begin
a_address1 = tmp_223_fu_4787_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg11_fsm_51 == ap_CS_fsm))) begin
a_address1 = tmp_221_fu_4769_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg10_fsm_50 == ap_CS_fsm))) begin
a_address1 = tmp_219_fu_4731_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg9_fsm_49 == ap_CS_fsm))) begin
a_address1 = tmp_217_fu_4713_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg8_fsm_48 == ap_CS_fsm))) begin
a_address1 = tmp_215_fu_4695_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg7_fsm_47 == ap_CS_fsm))) begin
a_address1 = tmp_213_fu_4656_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg6_fsm_46 == ap_CS_fsm))) begin
a_address1 = tmp_211_fu_4638_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg5_fsm_45 == ap_CS_fsm))) begin
a_address1 = tmp_209_fu_4620_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg4_fsm_44 == ap_CS_fsm))) begin
a_address1 = tmp_207_fu_4597_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg3_fsm_43 == ap_CS_fsm))) begin
a_address1 = tmp_205_fu_4549_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg2_fsm_42 == ap_CS_fsm))) begin
a_address1 = tmp_203_fu_4511_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_ST_pp8_stg1_fsm_41 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond_reg_6132))) begin
a_address1 = tmp_201_fu_4473_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp7_it0) & (ap_const_lv1_0 == exitcond12_reg_5924) & (ap_ST_pp7_stg4_fsm_35 == ap_CS_fsm))) begin
a_address1 = tmp_198_fu_4322_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp7_it0) & (ap_const_lv1_0 == exitcond12_reg_5924) & (ap_ST_pp7_stg3_fsm_34 == ap_CS_fsm))) begin
a_address1 = tmp_193_fu_4284_p1;
end else if (((ap_ST_pp7_stg2_fsm_33 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp7_it0) & (ap_const_lv1_0 == exitcond12_reg_5924))) begin
a_address1 = tmp_188_fu_4219_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp7_it0) & (ap_const_lv1_0 == exitcond12_reg_5924) & (ap_ST_pp7_stg1_fsm_32 == ap_CS_fsm))) begin
a_address1 = tmp_180_fu_4154_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp5_it1) & (ap_ST_pp5_stg3_fsm_25 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond9_reg_5697_pp5_it1))) begin
a_address1 = tmp_164_fu_3961_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp5_it0) & (ap_const_lv1_0 == exitcond9_reg_5697) & (ap_ST_pp5_stg2_fsm_24 == ap_CS_fsm))) begin
a_address1 = tmp_154_fu_3859_p1;
end else if (((ap_ST_pp5_stg1_fsm_23 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp5_it0) & (ap_const_lv1_0 == exitcond9_reg_5697))) begin
a_address1 = tmp_138_fu_3794_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp3_it0) & (ap_const_lv1_0 == exitcond6_reg_5446) & (ap_ST_pp3_stg4_fsm_17 == ap_CS_fsm))) begin
a_address1 = tmp_118_fu_3591_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp3_it0) & (ap_const_lv1_0 == exitcond6_reg_5446) & (ap_ST_pp3_stg3_fsm_16 == ap_CS_fsm))) begin
a_address1 = tmp_102_fu_3493_p1;
end else if (((ap_ST_pp3_stg2_fsm_15 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp3_it0) & (ap_const_lv1_0 == exitcond6_reg_5446))) begin
a_address1 = tmp_89_fu_3386_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp3_it0) & (ap_const_lv1_0 == exitcond6_reg_5446) & (ap_ST_pp3_stg1_fsm_14 == ap_CS_fsm))) begin
a_address1 = tmp_79_fu_3218_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_ST_pp1_stg3_fsm_7 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond3_reg_5195_pp1_it1))) begin
a_address1 = tmp_47_fu_2980_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond3_reg_5195) & (ap_ST_pp1_stg2_fsm_6 == ap_CS_fsm))) begin
a_address1 = tmp_36_fu_2794_p1;
end else if (((ap_ST_pp1_stg1_fsm_5 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond3_reg_5195))) begin
a_address1 = tmp_20_fu_2626_p1;
end else begin
a_address1 = ap_reg_ppstg_tmp_197_reg_6122_pp7_it2;
end
end
/// a_ce0 assign process. ///
always @ (ap_CS_fsm or ap_reg_ppiten_pp0_it0 or ap_reg_ppiten_pp1_it0 or ap_reg_ppiten_pp1_it1 or exitcond3_reg_5195 or ap_reg_ppiten_pp3_it0 or ap_reg_ppiten_pp3_it1 or ap_reg_ppiten_pp3_it2 or exitcond6_reg_5446 or ap_reg_ppiten_pp4_it0 or ap_reg_ppiten_pp5_it0 or ap_reg_ppiten_pp5_it1 or exitcond9_reg_5697 or ap_reg_ppiten_pp7_it0 or ap_reg_ppiten_pp7_it1 or ap_reg_ppiten_pp7_it2 or exitcond12_reg_5924 or ap_reg_ppiten_pp2_it6 or ap_reg_ppiten_pp6_it6 or ap_reg_ppstg_exitcond6_reg_5446_pp3_it1 or ap_reg_ppstg_exitcond12_reg_5924_pp7_it1 or ap_reg_ppstg_exitcond3_reg_5195_pp1_it1 or ap_reg_ppstg_exitcond9_reg_5697_pp5_it1 or exitcond1_fu_2377_p2 or exitcond3_fu_2404_p2 or ap_reg_ppstg_exitcond4_reg_5427_pp2_it5 or exitcond7_fu_3609_p2 or exitcond9_fu_3626_p2 or ap_reg_ppstg_exitcond10_reg_5905_pp6_it5 or exitcond_fu_4357_p2 or exitcond_reg_6132 or ap_reg_ppiten_pp8_it0)
begin
if ((((ap_ST_pp1_stg1_fsm_5 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond3_reg_5195)) | ((ap_ST_pp3_stg2_fsm_15 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp3_it0) & (ap_const_lv1_0 == exitcond6_reg_5446)) | ((ap_ST_pp5_stg1_fsm_23 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp5_it0) & (ap_const_lv1_0 == exitcond9_reg_5697)) | ((ap_ST_pp7_stg2_fsm_33 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp7_it0) & (ap_const_lv1_0 == exitcond12_reg_5924)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond3_reg_5195) & (ap_ST_pp1_stg2_fsm_6 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp3_it0) & (ap_const_lv1_0 == exitcond6_reg_5446) & (ap_ST_pp3_stg1_fsm_14 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp5_it0) & (ap_const_lv1_0 == exitcond9_reg_5697) & (ap_ST_pp5_stg2_fsm_24 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp7_it0) & (ap_const_lv1_0 == exitcond12_reg_5924) & (ap_ST_pp7_stg1_fsm_32 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp3_it0) & (ap_const_lv1_0 == exitcond6_reg_5446) & (ap_ST_pp3_stg3_fsm_16 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp7_it0) & (ap_const_lv1_0 == exitcond12_reg_5924) & (ap_ST_pp7_stg3_fsm_34 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond3_reg_5195) & (ap_ST_pp1_stg3_fsm_7 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp5_it0) & (ap_const_lv1_0 == exitcond9_reg_5697) & (ap_ST_pp5_stg3_fsm_25 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp3_it0) & (ap_const_lv1_0 == exitcond6_reg_5446) & (ap_ST_pp3_stg4_fsm_17 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp7_it0) & (ap_const_lv1_0 == exitcond12_reg_5924) & (ap_ST_pp7_stg4_fsm_35 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp3_it1) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond6_reg_5446_pp3_it1) & (ap_ST_pp3_stg5_fsm_18 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp7_it1) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond12_reg_5924_pp7_it1) & (ap_ST_pp7_stg5_fsm_36 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp3_it1) & (ap_ST_pp3_stg6_fsm_19 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond6_reg_5446_pp3_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp3_it1) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond6_reg_5446_pp3_it1) & (ap_ST_pp3_stg7_fsm_20 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp7_it1) & (ap_ST_pp7_stg6_fsm_37 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond12_reg_5924_pp7_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp7_it1) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond12_reg_5924_pp7_it1) & (ap_ST_pp7_stg7_fsm_38 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_ST_pp1_stg4_fsm_8 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond3_reg_5195_pp1_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp5_it1) & (ap_ST_pp5_stg4_fsm_26 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond9_reg_5697_pp5_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp3_it2) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond6_reg_5446_pp3_it1) & (ap_ST_pp3_stg0_fsm_13 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp7_it2) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond12_reg_5924_pp7_it1) & (ap_ST_pp7_stg0_fsm_31 == ap_CS_fsm)) | ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (ap_const_lv1_0 == exitcond1_fu_2377_p2)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_ST_pp1_stg0_fsm_4 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond3_fu_2404_p2)) | ((ap_ST_pp4_stg0_fsm_21 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp4_it0) & (ap_const_lv1_0 == exitcond7_fu_3609_p2)) | ((ap_const_logic_1 == ap_reg_ppiten_pp5_it0) & (ap_ST_pp5_stg0_fsm_22 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond9_fu_3626_p2)) | ((ap_ST_pp8_stg0_fsm_40 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_fu_4357_p2)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_ST_pp8_stg1_fsm_41 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond_reg_6132)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg2_fsm_42 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg3_fsm_43 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg4_fsm_44 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg5_fsm_45 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg6_fsm_46 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg7_fsm_47 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg8_fsm_48 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg9_fsm_49 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg10_fsm_50 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg11_fsm_51 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg12_fsm_52 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg13_fsm_53 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg14_fsm_54 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg15_fsm_55 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg16_fsm_56 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg17_fsm_57 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg18_fsm_58 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg19_fsm_59 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg20_fsm_60 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg21_fsm_61 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg22_fsm_62 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg23_fsm_63 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg24_fsm_64 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg25_fsm_65 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg26_fsm_66 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg27_fsm_67 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg28_fsm_68 == ap_CS_fsm)) | ((ap_ST_pp2_stg0_fsm_12 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp2_it6) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond4_reg_5427_pp2_it5)) | ((ap_ST_pp6_stg0_fsm_30 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp6_it6) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond10_reg_5905_pp6_it5)))) begin
a_ce0 = ap_const_logic_1;
end else begin
a_ce0 = ap_const_logic_0;
end
end
/// a_ce1 assign process. ///
always @ (ap_CS_fsm or ap_reg_ppiten_pp1_it0 or ap_reg_ppiten_pp1_it1 or exitcond3_reg_5195 or ap_reg_ppiten_pp3_it0 or ap_reg_ppiten_pp3_it1 or ap_reg_ppiten_pp3_it2 or exitcond6_reg_5446 or ap_reg_ppiten_pp5_it0 or ap_reg_ppiten_pp5_it1 or exitcond9_reg_5697 or ap_reg_ppiten_pp7_it0 or ap_reg_ppiten_pp7_it1 or ap_reg_ppiten_pp7_it2 or exitcond12_reg_5924 or ap_reg_ppstg_exitcond6_reg_5446_pp3_it1 or ap_reg_ppstg_exitcond12_reg_5924_pp7_it1 or ap_reg_ppiten_pp3_it3 or ap_reg_ppiten_pp7_it3 or ap_reg_ppstg_exitcond3_reg_5195_pp1_it1 or ap_reg_ppstg_exitcond9_reg_5697_pp5_it1 or ap_reg_ppstg_exitcond6_reg_5446_pp3_it2 or ap_reg_ppstg_exitcond12_reg_5924_pp7_it2 or exitcond_reg_6132 or ap_reg_ppiten_pp8_it0)
begin
if ((((ap_ST_pp1_stg1_fsm_5 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond3_reg_5195)) | ((ap_ST_pp3_stg2_fsm_15 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp3_it0) & (ap_const_lv1_0 == exitcond6_reg_5446)) | ((ap_ST_pp5_stg1_fsm_23 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp5_it0) & (ap_const_lv1_0 == exitcond9_reg_5697)) | ((ap_ST_pp7_stg2_fsm_33 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp7_it0) & (ap_const_lv1_0 == exitcond12_reg_5924)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond3_reg_5195) & (ap_ST_pp1_stg2_fsm_6 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp3_it0) & (ap_const_lv1_0 == exitcond6_reg_5446) & (ap_ST_pp3_stg1_fsm_14 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp5_it0) & (ap_const_lv1_0 == exitcond9_reg_5697) & (ap_ST_pp5_stg2_fsm_24 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp7_it0) & (ap_const_lv1_0 == exitcond12_reg_5924) & (ap_ST_pp7_stg1_fsm_32 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp3_it0) & (ap_const_lv1_0 == exitcond6_reg_5446) & (ap_ST_pp3_stg3_fsm_16 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp7_it0) & (ap_const_lv1_0 == exitcond12_reg_5924) & (ap_ST_pp7_stg3_fsm_34 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp3_it0) & (ap_const_lv1_0 == exitcond6_reg_5446) & (ap_ST_pp3_stg4_fsm_17 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp7_it0) & (ap_const_lv1_0 == exitcond12_reg_5924) & (ap_ST_pp7_stg4_fsm_35 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp3_it1) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond6_reg_5446_pp3_it1) & (ap_ST_pp3_stg5_fsm_18 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp7_it1) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond12_reg_5924_pp7_it1) & (ap_ST_pp7_stg5_fsm_36 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_ST_pp1_stg3_fsm_7 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond3_reg_5195_pp1_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp5_it1) & (ap_ST_pp5_stg3_fsm_25 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond9_reg_5697_pp5_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_ST_pp8_stg1_fsm_41 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond_reg_6132)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg2_fsm_42 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg3_fsm_43 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg4_fsm_44 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg5_fsm_45 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg6_fsm_46 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg7_fsm_47 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg8_fsm_48 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg9_fsm_49 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg10_fsm_50 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg11_fsm_51 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg12_fsm_52 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg13_fsm_53 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg14_fsm_54 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg15_fsm_55 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg16_fsm_56 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg17_fsm_57 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg18_fsm_58 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg19_fsm_59 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg20_fsm_60 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg21_fsm_61 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg22_fsm_62 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg23_fsm_63 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg24_fsm_64 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg25_fsm_65 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg26_fsm_66 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg27_fsm_67 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg28_fsm_68 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp3_it2) & (ap_ST_pp3_stg6_fsm_19 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond6_reg_5446_pp3_it2)) | ((ap_const_logic_1 == ap_reg_ppiten_pp3_it2) & (ap_ST_pp3_stg7_fsm_20 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond6_reg_5446_pp3_it2)) | ((ap_ST_pp3_stg0_fsm_13 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp3_it3) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond6_reg_5446_pp3_it2)) | ((ap_const_logic_1 == ap_reg_ppiten_pp7_it2) & (ap_ST_pp7_stg6_fsm_37 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond12_reg_5924_pp7_it2)) | ((ap_const_logic_1 == ap_reg_ppiten_pp7_it2) & (ap_ST_pp7_stg7_fsm_38 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond12_reg_5924_pp7_it2)) | ((ap_ST_pp7_stg0_fsm_31 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp7_it3) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond12_reg_5924_pp7_it2)))) begin
a_ce1 = ap_const_logic_1;
end else begin
a_ce1 = ap_const_logic_0;
end
end
/// a_d0 assign process. ///
always @ (ap_CS_fsm or ap_reg_ppiten_pp3_it1 or ap_reg_ppiten_pp3_it2 or ap_reg_ppiten_pp7_it1 or ap_reg_ppiten_pp7_it2 or reg_2177 or ap_reg_ppiten_pp2_it6 or ap_reg_ppiten_pp6_it6 or ap_reg_ppstg_exitcond6_reg_5446_pp3_it1 or ap_reg_ppstg_exitcond12_reg_5924_pp7_it1 or reg_2294 or ap_reg_ppstg_exitcond4_reg_5427_pp2_it5 or ap_reg_ppstg_exitcond10_reg_5905_pp6_it5)
begin
if ((((ap_const_logic_1 == ap_reg_ppiten_pp3_it1) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond6_reg_5446_pp3_it1) & (ap_ST_pp3_stg5_fsm_18 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp7_it1) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond12_reg_5924_pp7_it1) & (ap_ST_pp7_stg5_fsm_36 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp3_it1) & (ap_ST_pp3_stg6_fsm_19 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond6_reg_5446_pp3_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp3_it1) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond6_reg_5446_pp3_it1) & (ap_ST_pp3_stg7_fsm_20 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp7_it1) & (ap_ST_pp7_stg6_fsm_37 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond12_reg_5924_pp7_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp7_it1) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond12_reg_5924_pp7_it1) & (ap_ST_pp7_stg7_fsm_38 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp3_it2) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond6_reg_5446_pp3_it1) & (ap_ST_pp3_stg0_fsm_13 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp7_it2) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond12_reg_5924_pp7_it1) & (ap_ST_pp7_stg0_fsm_31 == ap_CS_fsm)))) begin
a_d0 = reg_2294;
end else if ((((ap_ST_pp2_stg0_fsm_12 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp2_it6) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond4_reg_5427_pp2_it5)) | ((ap_ST_pp6_stg0_fsm_30 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp6_it6) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond10_reg_5905_pp6_it5)))) begin
a_d0 = reg_2177;
end else begin
a_d0 = reg_2294;
end
end
/// a_d1 assign process. ///
always @ (ap_CS_fsm or ap_reg_ppiten_pp3_it1 or ap_reg_ppiten_pp3_it2 or ap_reg_ppiten_pp7_it1 or ap_reg_ppiten_pp7_it2 or ap_reg_ppstg_exitcond6_reg_5446_pp3_it1 or ap_reg_ppstg_exitcond12_reg_5924_pp7_it1 or ap_reg_ppiten_pp3_it3 or ap_reg_ppiten_pp7_it3 or reg_2305 or reg_2335 or reg_2341 or ap_reg_ppstg_exitcond6_reg_5446_pp3_it2 or ap_reg_ppstg_exitcond12_reg_5924_pp7_it2 or reg_2347)
begin
if ((((ap_ST_pp3_stg0_fsm_13 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp3_it3) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond6_reg_5446_pp3_it2)) | ((ap_ST_pp7_stg0_fsm_31 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp7_it3) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond12_reg_5924_pp7_it2)))) begin
a_d1 = reg_2347;
end else if ((((ap_const_logic_1 == ap_reg_ppiten_pp3_it2) & (ap_ST_pp3_stg7_fsm_20 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond6_reg_5446_pp3_it2)) | ((ap_const_logic_1 == ap_reg_ppiten_pp7_it2) & (ap_ST_pp7_stg7_fsm_38 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond12_reg_5924_pp7_it2)))) begin
a_d1 = reg_2341;
end else if ((((ap_const_logic_1 == ap_reg_ppiten_pp3_it2) & (ap_ST_pp3_stg6_fsm_19 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond6_reg_5446_pp3_it2)) | ((ap_const_logic_1 == ap_reg_ppiten_pp7_it2) & (ap_ST_pp7_stg6_fsm_37 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond12_reg_5924_pp7_it2)))) begin
a_d1 = reg_2335;
end else if ((((ap_const_logic_1 == ap_reg_ppiten_pp3_it1) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond6_reg_5446_pp3_it1) & (ap_ST_pp3_stg5_fsm_18 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp7_it1) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond12_reg_5924_pp7_it1) & (ap_ST_pp7_stg5_fsm_36 == ap_CS_fsm)))) begin
a_d1 = reg_2305;
end else begin
a_d1 = reg_2347;
end
end
/// a_we0 assign process. ///
always @ (ap_CS_fsm or ap_reg_ppiten_pp3_it1 or ap_reg_ppiten_pp3_it2 or ap_reg_ppiten_pp7_it1 or ap_reg_ppiten_pp7_it2 or ap_reg_ppiten_pp2_it6 or ap_reg_ppiten_pp6_it6 or ap_reg_ppstg_exitcond6_reg_5446_pp3_it1 or ap_reg_ppstg_exitcond12_reg_5924_pp7_it1 or ap_reg_ppstg_exitcond4_reg_5427_pp2_it5 or ap_reg_ppstg_exitcond10_reg_5905_pp6_it5)
begin
if ((((ap_const_logic_1 == ap_reg_ppiten_pp3_it1) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond6_reg_5446_pp3_it1) & (ap_ST_pp3_stg5_fsm_18 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp7_it1) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond12_reg_5924_pp7_it1) & (ap_ST_pp7_stg5_fsm_36 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp3_it1) & (ap_ST_pp3_stg6_fsm_19 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond6_reg_5446_pp3_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp3_it1) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond6_reg_5446_pp3_it1) & (ap_ST_pp3_stg7_fsm_20 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp7_it1) & (ap_ST_pp7_stg6_fsm_37 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond12_reg_5924_pp7_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp7_it1) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond12_reg_5924_pp7_it1) & (ap_ST_pp7_stg7_fsm_38 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp3_it2) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond6_reg_5446_pp3_it1) & (ap_ST_pp3_stg0_fsm_13 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp7_it2) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond12_reg_5924_pp7_it1) & (ap_ST_pp7_stg0_fsm_31 == ap_CS_fsm)) | ((ap_ST_pp2_stg0_fsm_12 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp2_it6) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond4_reg_5427_pp2_it5)) | ((ap_ST_pp6_stg0_fsm_30 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp6_it6) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond10_reg_5905_pp6_it5)))) begin
a_we0 = ap_const_logic_1;
end else begin
a_we0 = ap_const_logic_0;
end
end
/// a_we1 assign process. ///
always @ (ap_CS_fsm or ap_reg_ppiten_pp3_it1 or ap_reg_ppiten_pp3_it2 or ap_reg_ppiten_pp7_it1 or ap_reg_ppiten_pp7_it2 or ap_reg_ppstg_exitcond6_reg_5446_pp3_it1 or ap_reg_ppstg_exitcond12_reg_5924_pp7_it1 or ap_reg_ppiten_pp3_it3 or ap_reg_ppiten_pp7_it3 or ap_reg_ppstg_exitcond6_reg_5446_pp3_it2 or ap_reg_ppstg_exitcond12_reg_5924_pp7_it2)
begin
if ((((ap_const_logic_1 == ap_reg_ppiten_pp3_it1) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond6_reg_5446_pp3_it1) & (ap_ST_pp3_stg5_fsm_18 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp7_it1) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond12_reg_5924_pp7_it1) & (ap_ST_pp7_stg5_fsm_36 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp3_it2) & (ap_ST_pp3_stg6_fsm_19 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond6_reg_5446_pp3_it2)) | ((ap_const_logic_1 == ap_reg_ppiten_pp3_it2) & (ap_ST_pp3_stg7_fsm_20 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond6_reg_5446_pp3_it2)) | ((ap_ST_pp3_stg0_fsm_13 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp3_it3) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond6_reg_5446_pp3_it2)) | ((ap_const_logic_1 == ap_reg_ppiten_pp7_it2) & (ap_ST_pp7_stg6_fsm_37 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond12_reg_5924_pp7_it2)) | ((ap_const_logic_1 == ap_reg_ppiten_pp7_it2) & (ap_ST_pp7_stg7_fsm_38 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond12_reg_5924_pp7_it2)) | ((ap_ST_pp7_stg0_fsm_31 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp7_it3) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond12_reg_5924_pp7_it2)))) begin
a_we1 = ap_const_logic_1;
end else begin
a_we1 = ap_const_logic_0;
end
end
/// ap_NS_fsm assign process. ///
always @ (ap_start or ap_CS_fsm or ap_reg_ppiten_pp0_it1 or ap_reg_ppiten_pp0_it0 or ap_reg_ppiten_pp0_it5 or ap_reg_ppiten_pp0_it6 or ap_reg_ppiten_pp1_it0 or ap_reg_ppiten_pp1_it1 or ap_reg_ppiten_pp1_it2 or ap_reg_ppiten_pp3_it0 or ap_reg_ppiten_pp3_it1 or ap_reg_ppiten_pp3_it2 or ap_reg_ppiten_pp4_it1 or ap_reg_ppiten_pp4_it0 or ap_reg_ppiten_pp4_it5 or ap_reg_ppiten_pp4_it6 or ap_reg_ppiten_pp5_it0 or ap_reg_ppiten_pp5_it1 or ap_reg_ppiten_pp5_it2 or ap_reg_ppiten_pp7_it0 or ap_reg_ppiten_pp7_it1 or ap_reg_ppiten_pp7_it2 or ap_reg_ppiten_pp2_it5 or ap_reg_ppiten_pp2_it0 or ap_reg_ppiten_pp2_it1 or ap_reg_ppiten_pp2_it6 or ap_reg_ppiten_pp6_it5 or ap_reg_ppiten_pp6_it0 or ap_reg_ppiten_pp6_it1 or ap_reg_ppiten_pp6_it6 or ap_reg_ppiten_pp1_it3 or ap_reg_ppiten_pp3_it3 or ap_reg_ppiten_pp5_it3 or ap_reg_ppiten_pp7_it3 or or_cond_fu_2365_p2 or tmp_2_fu_2371_p2 or exitcond1_fu_2377_p2 or exitcond3_fu_2404_p2 or exitcond4_fu_2988_p2 or exitcond6_fu_3025_p2 or exitcond7_fu_3609_p2 or exitcond9_fu_3626_p2 or exitcond10_fu_3978_p2 or exitcond12_fu_4005_p2 or exitcond_fu_4357_p2 or ap_reg_ppiten_pp8_it0)
begin
if ((ap_ST_pp8_stg27_fsm_67 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_pp8_stg28_fsm_68;
end else if ((ap_ST_pp8_stg26_fsm_66 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_pp8_stg27_fsm_67;
end else if ((ap_ST_pp8_stg25_fsm_65 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_pp8_stg26_fsm_66;
end else if ((ap_ST_pp8_stg24_fsm_64 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_pp8_stg25_fsm_65;
end else if ((ap_ST_pp8_stg23_fsm_63 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_pp8_stg24_fsm_64;
end else if ((ap_ST_pp8_stg22_fsm_62 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_pp8_stg23_fsm_63;
end else if ((ap_ST_pp8_stg21_fsm_61 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_pp8_stg22_fsm_62;
end else if ((ap_ST_pp8_stg20_fsm_60 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_pp8_stg21_fsm_61;
end else if ((ap_ST_pp8_stg19_fsm_59 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_pp8_stg20_fsm_60;
end else if ((ap_ST_pp8_stg18_fsm_58 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_pp8_stg19_fsm_59;
end else if ((ap_ST_pp8_stg17_fsm_57 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_pp8_stg18_fsm_58;
end else if ((ap_ST_pp8_stg16_fsm_56 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_pp8_stg17_fsm_57;
end else if ((ap_ST_pp8_stg15_fsm_55 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_pp8_stg16_fsm_56;
end else if ((ap_ST_pp8_stg14_fsm_54 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_pp8_stg15_fsm_55;
end else if ((ap_ST_pp8_stg13_fsm_53 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_pp8_stg14_fsm_54;
end else if ((ap_ST_pp8_stg12_fsm_52 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_pp8_stg13_fsm_53;
end else if ((ap_ST_pp8_stg11_fsm_51 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_pp8_stg12_fsm_52;
end else if ((ap_ST_pp8_stg10_fsm_50 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_pp8_stg11_fsm_51;
end else if ((ap_ST_pp8_stg9_fsm_49 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_pp8_stg10_fsm_50;
end else if ((ap_ST_pp8_stg8_fsm_48 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_pp8_stg9_fsm_49;
end else if ((ap_ST_pp8_stg7_fsm_47 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_pp8_stg8_fsm_48;
end else if ((ap_ST_pp8_stg6_fsm_46 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_pp8_stg7_fsm_47;
end else if ((ap_ST_pp8_stg5_fsm_45 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_pp8_stg6_fsm_46;
end else if ((ap_ST_pp8_stg4_fsm_44 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_pp8_stg5_fsm_45;
end else if ((ap_ST_pp8_stg3_fsm_43 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_pp8_stg4_fsm_44;
end else if ((ap_ST_pp8_stg2_fsm_42 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_pp8_stg3_fsm_43;
end else if ((ap_ST_pp8_stg1_fsm_41 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_pp8_stg2_fsm_42;
end else if (((ap_ST_pp8_stg0_fsm_40 == ap_CS_fsm) & ~((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & ~(ap_const_lv1_0 == exitcond_fu_4357_p2)))) begin
ap_NS_fsm = ap_ST_pp8_stg1_fsm_41;
end else if ((ap_ST_pp7_stg6_fsm_37 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_pp7_stg7_fsm_38;
end else if ((ap_ST_pp7_stg5_fsm_36 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_pp7_stg6_fsm_37;
end else if ((ap_ST_pp7_stg4_fsm_35 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_pp7_stg5_fsm_36;
end else if ((ap_ST_pp7_stg3_fsm_34 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_pp7_stg4_fsm_35;
end else if ((ap_ST_pp7_stg2_fsm_33 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_pp7_stg3_fsm_34;
end else if ((ap_ST_pp7_stg1_fsm_32 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_pp7_stg2_fsm_33;
end else if (((ap_ST_pp7_stg0_fsm_31 == ap_CS_fsm) & ~((ap_ST_pp7_stg0_fsm_31 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp7_it3) & ~(ap_const_logic_1 == ap_reg_ppiten_pp7_it2)) & ~((ap_const_logic_1 == ap_reg_ppiten_pp7_it0) & ~(ap_const_lv1_0 == exitcond12_fu_4005_p2) & ~(ap_const_logic_1 == ap_reg_ppiten_pp7_it1)))) begin
ap_NS_fsm = ap_ST_pp7_stg1_fsm_32;
end else if ((((ap_ST_pp7_stg0_fsm_31 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp7_it3) & ~(ap_const_logic_1 == ap_reg_ppiten_pp7_it2)) | ((ap_const_logic_1 == ap_reg_ppiten_pp7_it0) & (ap_ST_pp7_stg0_fsm_31 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond12_fu_4005_p2) & ~(ap_const_logic_1 == ap_reg_ppiten_pp7_it1)))) begin
ap_NS_fsm = ap_ST_st131_fsm_39;
end else if (((ap_ST_pp7_stg7_fsm_38 == ap_CS_fsm) | ((ap_ST_pp6_stg0_fsm_30 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp6_it6) & ~(ap_const_logic_1 == ap_reg_ppiten_pp6_it5)) | ((ap_ST_pp6_stg0_fsm_30 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp6_it0) & ~(ap_const_lv1_0 == exitcond10_fu_3978_p2) & ~(ap_const_logic_1 == ap_reg_ppiten_pp6_it1)))) begin
ap_NS_fsm = ap_ST_pp7_stg0_fsm_31;
end else if ((ap_ST_pp5_stg6_fsm_28 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_pp5_stg7_fsm_29;
end else if ((ap_ST_pp5_stg5_fsm_27 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_pp5_stg6_fsm_28;
end else if ((ap_ST_pp5_stg4_fsm_26 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_pp5_stg5_fsm_27;
end else if ((ap_ST_pp5_stg3_fsm_25 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_pp5_stg4_fsm_26;
end else if ((ap_ST_pp5_stg2_fsm_24 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_pp5_stg3_fsm_25;
end else if ((ap_ST_pp5_stg1_fsm_23 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_pp5_stg2_fsm_24;
end else if (((ap_ST_pp5_stg0_fsm_22 == ap_CS_fsm) & ~((ap_ST_pp5_stg0_fsm_22 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp5_it3) & ~(ap_const_logic_1 == ap_reg_ppiten_pp5_it2)) & ~((ap_const_logic_1 == ap_reg_ppiten_pp5_it0) & ~(ap_const_lv1_0 == exitcond9_fu_3626_p2) & ~(ap_const_logic_1 == ap_reg_ppiten_pp5_it1)))) begin
ap_NS_fsm = ap_ST_pp5_stg1_fsm_23;
end else if ((((ap_ST_pp5_stg0_fsm_22 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp5_it3) & ~(ap_const_logic_1 == ap_reg_ppiten_pp5_it2)) | ((ap_const_logic_1 == ap_reg_ppiten_pp5_it0) & (ap_ST_pp5_stg0_fsm_22 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond9_fu_3626_p2) & ~(ap_const_logic_1 == ap_reg_ppiten_pp5_it1)))) begin
ap_NS_fsm = ap_ST_pp6_stg0_fsm_30;
end else if (((ap_ST_pp5_stg7_fsm_29 == ap_CS_fsm) | ((ap_ST_pp4_stg0_fsm_21 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp4_it6) & ~(ap_const_logic_1 == ap_reg_ppiten_pp4_it5)) | ((ap_ST_pp4_stg0_fsm_21 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp4_it0) & ~(ap_const_lv1_0 == exitcond7_fu_3609_p2) & ~(ap_const_logic_1 == ap_reg_ppiten_pp4_it1)))) begin
ap_NS_fsm = ap_ST_pp5_stg0_fsm_22;
end else if ((ap_ST_pp3_stg6_fsm_19 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_pp3_stg7_fsm_20;
end else if ((ap_ST_pp3_stg5_fsm_18 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_pp3_stg6_fsm_19;
end else if ((ap_ST_pp3_stg4_fsm_17 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_pp3_stg5_fsm_18;
end else if ((ap_ST_pp3_stg3_fsm_16 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_pp3_stg4_fsm_17;
end else if ((ap_ST_pp3_stg2_fsm_15 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_pp3_stg3_fsm_16;
end else if ((ap_ST_pp3_stg1_fsm_14 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_pp3_stg2_fsm_15;
end else if (((ap_ST_pp3_stg0_fsm_13 == ap_CS_fsm) & ~((ap_ST_pp3_stg0_fsm_13 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp3_it3) & ~(ap_const_logic_1 == ap_reg_ppiten_pp3_it2)) & ~((ap_const_logic_1 == ap_reg_ppiten_pp3_it0) & ~(ap_const_lv1_0 == exitcond6_fu_3025_p2) & ~(ap_const_logic_1 == ap_reg_ppiten_pp3_it1)))) begin
ap_NS_fsm = ap_ST_pp3_stg1_fsm_14;
end else if ((((ap_ST_pp3_stg0_fsm_13 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp3_it3) & ~(ap_const_logic_1 == ap_reg_ppiten_pp3_it2)) | ((ap_const_logic_1 == ap_reg_ppiten_pp3_it0) & (ap_ST_pp3_stg0_fsm_13 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond6_fu_3025_p2) & ~(ap_const_logic_1 == ap_reg_ppiten_pp3_it1)))) begin
ap_NS_fsm = ap_ST_pp4_stg0_fsm_21;
end else if (((ap_ST_pp3_stg7_fsm_20 == ap_CS_fsm) | ((ap_ST_pp2_stg0_fsm_12 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp2_it6) & ~(ap_const_logic_1 == ap_reg_ppiten_pp2_it5)) | ((ap_ST_pp2_stg0_fsm_12 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp2_it0) & ~(ap_const_lv1_0 == exitcond4_fu_2988_p2) & ~(ap_const_logic_1 == ap_reg_ppiten_pp2_it1)))) begin
ap_NS_fsm = ap_ST_pp3_stg0_fsm_13;
end else if ((ap_ST_pp1_stg6_fsm_10 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_pp1_stg7_fsm_11;
end else if ((ap_ST_pp1_stg5_fsm_9 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_pp1_stg6_fsm_10;
end else if ((ap_ST_pp1_stg4_fsm_8 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_pp1_stg5_fsm_9;
end else if ((ap_ST_pp1_stg3_fsm_7 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_pp1_stg4_fsm_8;
end else if ((ap_ST_pp1_stg2_fsm_6 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_pp1_stg3_fsm_7;
end else if ((ap_ST_pp1_stg1_fsm_5 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_pp1_stg2_fsm_6;
end else if (((ap_ST_pp1_stg0_fsm_4 == ap_CS_fsm) & ~((ap_ST_pp1_stg0_fsm_4 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it3) & ~(ap_const_logic_1 == ap_reg_ppiten_pp1_it2)) & ~((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & ~(ap_const_lv1_0 == exitcond3_fu_2404_p2) & ~(ap_const_logic_1 == ap_reg_ppiten_pp1_it1)))) begin
ap_NS_fsm = ap_ST_pp1_stg1_fsm_5;
end else if ((((ap_ST_pp1_stg0_fsm_4 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it3) & ~(ap_const_logic_1 == ap_reg_ppiten_pp1_it2)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_ST_pp1_stg0_fsm_4 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond3_fu_2404_p2) & ~(ap_const_logic_1 == ap_reg_ppiten_pp1_it1)))) begin
ap_NS_fsm = ap_ST_pp2_stg0_fsm_12;
end else if ((((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6) & ~(ap_const_logic_1 == ap_reg_ppiten_pp0_it5)) | ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ~(ap_const_lv1_0 == exitcond1_fu_2377_p2) & ~(ap_const_logic_1 == ap_reg_ppiten_pp0_it1)))) begin
ap_NS_fsm = ap_ST_st9_fsm_3;
end else if ((~(ap_const_logic_1 == ap_start) & (ap_ST_st162_fsm_69 == ap_CS_fsm))) begin
ap_NS_fsm = ap_ST_st0_fsm_0;
end else if (((ap_ST_pp1_stg7_fsm_11 == ap_CS_fsm) | (ap_ST_st9_fsm_3 == ap_CS_fsm))) begin
ap_NS_fsm = ap_ST_pp1_stg0_fsm_4;
end else if (((ap_ST_st1_fsm_1 == ap_CS_fsm) & ~(ap_const_lv1_0 == or_cond_fu_2365_p2) & ~(ap_const_lv1_0 == tmp_2_fu_2371_p2))) begin
ap_NS_fsm = ap_ST_pp0_stg0_fsm_2;
end else if (((ap_ST_pp8_stg28_fsm_68 == ap_CS_fsm) | ((ap_ST_st1_fsm_1 == ap_CS_fsm) & ~(ap_const_lv1_0 == or_cond_fu_2365_p2) & (ap_const_lv1_0 == tmp_2_fu_2371_p2)) | (ap_ST_st131_fsm_39 == ap_CS_fsm))) begin
ap_NS_fsm = ap_ST_pp8_stg0_fsm_40;
end else if ((((ap_ST_st1_fsm_1 == ap_CS_fsm) & (ap_const_lv1_0 == or_cond_fu_2365_p2)) | ((ap_ST_pp8_stg0_fsm_40 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & ~(ap_const_lv1_0 == exitcond_fu_4357_p2)))) begin
ap_NS_fsm = ap_ST_st162_fsm_69;
end else if ((((ap_ST_st0_fsm_0 == ap_CS_fsm) & (ap_const_logic_1 == ap_start)) | ((ap_const_logic_1 == ap_start) & (ap_ST_st162_fsm_69 == ap_CS_fsm)))) begin
ap_NS_fsm = ap_ST_st1_fsm_1;
end else begin
ap_NS_fsm = ap_CS_fsm;
end
end
/// ap_done assign process. ///
always @ (ap_CS_fsm)
begin
if (((ap_ST_st0_fsm_0 == ap_CS_fsm) | (ap_ST_st162_fsm_69 == ap_CS_fsm))) begin
ap_done = ap_const_logic_1;
end else begin
ap_done = ap_const_logic_0;
end
end
/// ap_idle assign process. ///
always @ (ap_CS_fsm)
begin
if ((ap_ST_st0_fsm_0 == ap_CS_fsm)) begin
ap_idle = ap_const_logic_1;
end else begin
ap_idle = ap_const_logic_0;
end
end
/// b_address0 assign process. ///
always @ (ap_CS_fsm or ap_reg_ppiten_pp0_it6 or ap_reg_ppiten_pp1_it0 or ap_reg_ppiten_pp1_it1 or ap_reg_ppiten_pp1_it2 or exitcond3_reg_5195 or ap_reg_ppiten_pp3_it0 or ap_reg_ppiten_pp3_it1 or exitcond6_reg_5446 or ap_reg_ppiten_pp4_it6 or ap_reg_ppiten_pp5_it0 or ap_reg_ppiten_pp5_it1 or ap_reg_ppiten_pp5_it2 or exitcond9_reg_5697 or ap_reg_ppiten_pp7_it0 or ap_reg_ppiten_pp7_it1 or exitcond12_reg_5924 or ap_reg_ppiten_pp2_it0 or ap_reg_ppiten_pp6_it0 or ap_reg_ppstg_exitcond6_reg_5446_pp3_it1 or ap_reg_ppstg_exitcond12_reg_5924_pp7_it1 or ap_reg_ppstg_exitcond3_reg_5195_pp1_it1 or ap_reg_ppstg_exitcond9_reg_5697_pp5_it1 or ap_reg_ppstg_exitcond1_reg_5171_pp0_it5 or ap_reg_ppstg_tmp_6_reg_5180_pp0_it5 or ap_reg_ppstg_tmp_9_reg_5237_pp1_it1 or ap_reg_ppstg_tmp_20_reg_5287_pp1_it1 or ap_reg_ppstg_tmp_28_reg_5332_pp1_it1 or ap_reg_ppstg_tmp_36_reg_5347_pp1_it1 or exitcond4_fu_2988_p2 or tmp_59_fu_3020_p1 or exitcond6_fu_3025_p2 or tmp_67_fu_3093_p1 or tmp_75_fu_3181_p1 or tmp_86_fu_3361_p1 or tmp_98_fu_3468_p1 or tmp_114_fu_3605_p1 or ap_reg_ppstg_exitcond7_reg_5678_pp4_it5 or ap_reg_ppstg_tmp_122_reg_5687_pp4_it5 or ap_reg_ppstg_tmp_125_reg_5740_pp5_it1 or ap_reg_ppstg_tmp_138_reg_5790_pp5_it1 or ap_reg_ppstg_tmp_146_reg_5805_pp5_it1 or ap_reg_ppstg_tmp_154_reg_5825_pp5_it1 or exitcond10_fu_3978_p2 or tmp_172_fu_4000_p1 or exitcond12_fu_4005_p2 or tmp_174_fu_4073_p1 or tmp_178_fu_4143_p1 or tmp_186_fu_4209_p1 or tmp_192_fu_4274_p1 or tmp_197_fu_4353_p1 or exitcond_reg_6132 or ap_reg_ppiten_pp8_it0 or ap_reg_ppiten_pp8_it1 or tmp_199_reg_6176 or tmp_200_reg_6202 or tmp_202_reg_6244 or tmp_204_reg_6286 or tmp_206_reg_6328 or tmp_208_reg_6363 or tmp_210_reg_6383 or tmp_212_reg_6403 or tmp_214_reg_6432 or tmp_216_reg_6452 or tmp_218_reg_6472 or tmp_220_reg_6492 or tmp_222_reg_6522 or tmp_224_reg_6542 or tmp_226_reg_6562 or tmp_228_reg_6591 or tmp_230_reg_6611 or tmp_232_reg_6631 or tmp_234_reg_6651 or tmp_236_reg_6681 or tmp_238_reg_6701 or tmp_240_reg_6721 or tmp_242_reg_6750 or tmp_244_reg_6770 or tmp_246_reg_6790 or tmp_248_reg_6850 or tmp_250_reg_6870 or tmp_252_reg_6890 or tmp_254_reg_6910 or tmp_11_fu_2531_p1 or tmp_24_fu_2711_p1 or tmp_40_fu_2818_p1 or tmp_50_fu_2921_p1 or tmp_126_fu_3741_p1 or tmp_142_fu_3807_p1 or tmp_158_fu_3872_p1 or tmp_166_fu_3924_p1)
begin
if (((ap_ST_pp8_stg0_fsm_40 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp8_it1) & (ap_const_lv1_0 == exitcond_reg_6132))) begin
b_address0 = tmp_254_reg_6910;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg28_fsm_68 == ap_CS_fsm))) begin
b_address0 = tmp_252_reg_6890;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg27_fsm_67 == ap_CS_fsm))) begin
b_address0 = tmp_250_reg_6870;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg26_fsm_66 == ap_CS_fsm))) begin
b_address0 = tmp_248_reg_6850;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg25_fsm_65 == ap_CS_fsm))) begin
b_address0 = tmp_246_reg_6790;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg24_fsm_64 == ap_CS_fsm))) begin
b_address0 = tmp_244_reg_6770;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg23_fsm_63 == ap_CS_fsm))) begin
b_address0 = tmp_242_reg_6750;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg22_fsm_62 == ap_CS_fsm))) begin
b_address0 = tmp_240_reg_6721;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg21_fsm_61 == ap_CS_fsm))) begin
b_address0 = tmp_238_reg_6701;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg20_fsm_60 == ap_CS_fsm))) begin
b_address0 = tmp_236_reg_6681;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg19_fsm_59 == ap_CS_fsm))) begin
b_address0 = tmp_234_reg_6651;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg18_fsm_58 == ap_CS_fsm))) begin
b_address0 = tmp_232_reg_6631;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg17_fsm_57 == ap_CS_fsm))) begin
b_address0 = tmp_230_reg_6611;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg16_fsm_56 == ap_CS_fsm))) begin
b_address0 = tmp_228_reg_6591;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg15_fsm_55 == ap_CS_fsm))) begin
b_address0 = tmp_226_reg_6562;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg14_fsm_54 == ap_CS_fsm))) begin
b_address0 = tmp_224_reg_6542;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg13_fsm_53 == ap_CS_fsm))) begin
b_address0 = tmp_222_reg_6522;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg12_fsm_52 == ap_CS_fsm))) begin
b_address0 = tmp_220_reg_6492;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg11_fsm_51 == ap_CS_fsm))) begin
b_address0 = tmp_218_reg_6472;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg10_fsm_50 == ap_CS_fsm))) begin
b_address0 = tmp_216_reg_6452;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg9_fsm_49 == ap_CS_fsm))) begin
b_address0 = tmp_214_reg_6432;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg8_fsm_48 == ap_CS_fsm))) begin
b_address0 = tmp_212_reg_6403;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg7_fsm_47 == ap_CS_fsm))) begin
b_address0 = tmp_210_reg_6383;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg6_fsm_46 == ap_CS_fsm))) begin
b_address0 = tmp_208_reg_6363;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg5_fsm_45 == ap_CS_fsm))) begin
b_address0 = tmp_206_reg_6328;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg4_fsm_44 == ap_CS_fsm))) begin
b_address0 = tmp_204_reg_6286;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg3_fsm_43 == ap_CS_fsm))) begin
b_address0 = tmp_202_reg_6244;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg2_fsm_42 == ap_CS_fsm))) begin
b_address0 = tmp_200_reg_6202;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_ST_pp8_stg1_fsm_41 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond_reg_6132))) begin
b_address0 = tmp_199_reg_6176;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp5_it2) & (ap_ST_pp5_stg0_fsm_22 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond9_reg_5697_pp5_it1))) begin
b_address0 = ap_reg_ppstg_tmp_154_reg_5825_pp5_it1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp5_it1) & (ap_ST_pp5_stg7_fsm_29 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond9_reg_5697_pp5_it1))) begin
b_address0 = ap_reg_ppstg_tmp_146_reg_5805_pp5_it1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp5_it1) & (ap_ST_pp5_stg6_fsm_28 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond9_reg_5697_pp5_it1))) begin
b_address0 = ap_reg_ppstg_tmp_138_reg_5790_pp5_it1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp5_it1) & (ap_ST_pp5_stg5_fsm_27 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond9_reg_5697_pp5_it1))) begin
b_address0 = ap_reg_ppstg_tmp_125_reg_5740_pp5_it1;
end else if (((ap_ST_pp4_stg0_fsm_21 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp4_it6) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond7_reg_5678_pp4_it5))) begin
b_address0 = ap_reg_ppstg_tmp_122_reg_5687_pp4_it5;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it2) & (ap_ST_pp1_stg0_fsm_4 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond3_reg_5195_pp1_it1))) begin
b_address0 = ap_reg_ppstg_tmp_36_reg_5347_pp1_it1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_ST_pp1_stg7_fsm_11 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond3_reg_5195_pp1_it1))) begin
b_address0 = ap_reg_ppstg_tmp_28_reg_5332_pp1_it1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_ST_pp1_stg6_fsm_10 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond3_reg_5195_pp1_it1))) begin
b_address0 = ap_reg_ppstg_tmp_20_reg_5287_pp1_it1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_ST_pp1_stg5_fsm_9 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond3_reg_5195_pp1_it1))) begin
b_address0 = ap_reg_ppstg_tmp_9_reg_5237_pp1_it1;
end else if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond1_reg_5171_pp0_it5))) begin
b_address0 = ap_reg_ppstg_tmp_6_reg_5180_pp0_it5;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp7_it1) & (ap_ST_pp7_stg4_fsm_35 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond12_reg_5924_pp7_it1))) begin
b_address0 = tmp_197_fu_4353_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp7_it0) & (ap_const_lv1_0 == exitcond12_reg_5924) & (ap_ST_pp7_stg3_fsm_34 == ap_CS_fsm))) begin
b_address0 = tmp_192_fu_4274_p1;
end else if (((ap_ST_pp7_stg2_fsm_33 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp7_it0) & (ap_const_lv1_0 == exitcond12_reg_5924))) begin
b_address0 = tmp_186_fu_4209_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp7_it0) & (ap_const_lv1_0 == exitcond12_reg_5924) & (ap_ST_pp7_stg1_fsm_32 == ap_CS_fsm))) begin
b_address0 = tmp_178_fu_4143_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp7_it0) & (ap_ST_pp7_stg0_fsm_31 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond12_fu_4005_p2))) begin
b_address0 = tmp_174_fu_4073_p1;
end else if (((ap_ST_pp6_stg0_fsm_30 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp6_it0) & (ap_const_lv1_0 == exitcond10_fu_3978_p2))) begin
b_address0 = tmp_172_fu_4000_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp5_it0) & (ap_const_lv1_0 == exitcond9_reg_5697) & (ap_ST_pp5_stg4_fsm_26 == ap_CS_fsm))) begin
b_address0 = tmp_166_fu_3924_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp5_it0) & (ap_const_lv1_0 == exitcond9_reg_5697) & (ap_ST_pp5_stg3_fsm_25 == ap_CS_fsm))) begin
b_address0 = tmp_158_fu_3872_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp5_it0) & (ap_const_lv1_0 == exitcond9_reg_5697) & (ap_ST_pp5_stg2_fsm_24 == ap_CS_fsm))) begin
b_address0 = tmp_142_fu_3807_p1;
end else if (((ap_ST_pp5_stg1_fsm_23 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp5_it0) & (ap_const_lv1_0 == exitcond9_reg_5697))) begin
b_address0 = tmp_126_fu_3741_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp3_it1) & (ap_ST_pp3_stg4_fsm_17 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond6_reg_5446_pp3_it1))) begin
b_address0 = tmp_114_fu_3605_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp3_it0) & (ap_const_lv1_0 == exitcond6_reg_5446) & (ap_ST_pp3_stg3_fsm_16 == ap_CS_fsm))) begin
b_address0 = tmp_98_fu_3468_p1;
end else if (((ap_ST_pp3_stg2_fsm_15 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp3_it0) & (ap_const_lv1_0 == exitcond6_reg_5446))) begin
b_address0 = tmp_86_fu_3361_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp3_it0) & (ap_const_lv1_0 == exitcond6_reg_5446) & (ap_ST_pp3_stg1_fsm_14 == ap_CS_fsm))) begin
b_address0 = tmp_75_fu_3181_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp3_it0) & (ap_ST_pp3_stg0_fsm_13 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond6_fu_3025_p2))) begin
b_address0 = tmp_67_fu_3093_p1;
end else if (((ap_ST_pp2_stg0_fsm_12 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp2_it0) & (ap_const_lv1_0 == exitcond4_fu_2988_p2))) begin
b_address0 = tmp_59_fu_3020_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond3_reg_5195) & (ap_ST_pp1_stg4_fsm_8 == ap_CS_fsm))) begin
b_address0 = tmp_50_fu_2921_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond3_reg_5195) & (ap_ST_pp1_stg3_fsm_7 == ap_CS_fsm))) begin
b_address0 = tmp_40_fu_2818_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond3_reg_5195) & (ap_ST_pp1_stg2_fsm_6 == ap_CS_fsm))) begin
b_address0 = tmp_24_fu_2711_p1;
end else if (((ap_ST_pp1_stg1_fsm_5 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond3_reg_5195))) begin
b_address0 = tmp_11_fu_2531_p1;
end else begin
b_address0 = tmp_254_reg_6910;
end
end
/// b_address1 assign process. ///
always @ (ap_CS_fsm or ap_reg_ppiten_pp1_it0 or ap_reg_ppiten_pp1_it1 or ap_reg_ppiten_pp1_it2 or exitcond3_reg_5195 or ap_reg_ppiten_pp3_it0 or ap_reg_ppiten_pp3_it1 or exitcond6_reg_5446 or ap_reg_ppiten_pp5_it0 or ap_reg_ppiten_pp5_it1 or ap_reg_ppiten_pp5_it2 or exitcond9_reg_5697 or ap_reg_ppiten_pp7_it0 or ap_reg_ppiten_pp7_it1 or exitcond12_reg_5924 or ap_reg_ppstg_exitcond6_reg_5446_pp3_it1 or ap_reg_ppstg_exitcond12_reg_5924_pp7_it1 or ap_reg_ppiten_pp1_it3 or ap_reg_ppiten_pp5_it3 or ap_reg_ppstg_exitcond3_reg_5195_pp1_it1 or ap_reg_ppstg_exitcond9_reg_5697_pp5_it1 or ap_reg_ppstg_exitcond3_reg_5195_pp1_it2 or ap_reg_ppstg_exitcond9_reg_5697_pp5_it2 or ap_reg_ppstg_tmp_15_reg_5272_pp1_it1 or ap_reg_ppstg_tmp_44_reg_5367_pp1_it2 or ap_reg_ppstg_tmp_47_reg_5407_pp1_it2 or ap_reg_ppstg_tmp_51_reg_5417_pp1_it2 or tmp_83_fu_3247_p1 or tmp_90_fu_3415_p1 or tmp_106_fu_3601_p1 or ap_reg_ppstg_tmp_130_reg_5770_pp5_it1 or ap_reg_ppstg_tmp_160_reg_5840_pp5_it2 or ap_reg_ppstg_tmp_164_reg_5880_pp5_it2 or ap_reg_ppstg_tmp_168_reg_5895_pp5_it2 or tmp_182_fu_4173_p1 or tmp_190_fu_4238_p1 or tmp_194_fu_4340_p1 or exitcond_reg_6132 or ap_reg_ppiten_pp8_it0 or ap_reg_ppiten_pp8_it1 or tmp_201_reg_6223 or tmp_203_reg_6265 or tmp_205_reg_6307 or tmp_207_reg_6348 or tmp_209_reg_6373 or tmp_211_reg_6393 or tmp_213_reg_6413 or tmp_215_reg_6442 or tmp_217_reg_6462 or tmp_219_reg_6482 or tmp_221_reg_6512 or tmp_223_reg_6532 or tmp_225_reg_6552 or tmp_227_reg_6572 or tmp_229_reg_6601 or tmp_231_reg_6621 or tmp_233_reg_6641 or tmp_235_reg_6671 or tmp_237_reg_6691 or tmp_239_reg_6711 or tmp_241_reg_6731 or tmp_243_reg_6760 or tmp_245_reg_6780 or tmp_247_reg_6800 or tmp_249_reg_6860 or tmp_251_reg_6880 or tmp_253_reg_6900 or tmp_255_reg_6920 or tmp_16_fu_2597_p1 or tmp_32_fu_2765_p1 or tmp_46_fu_2872_p1 or tmp_55_fu_2970_p1 or tmp_134_fu_3775_p1 or tmp_150_fu_3840_p1 or tmp_162_fu_3905_p1 or tmp_170_fu_3943_p1)
begin
if (((ap_ST_pp8_stg0_fsm_40 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp8_it1) & (ap_const_lv1_0 == exitcond_reg_6132))) begin
b_address1 = tmp_255_reg_6920;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg28_fsm_68 == ap_CS_fsm))) begin
b_address1 = tmp_253_reg_6900;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg27_fsm_67 == ap_CS_fsm))) begin
b_address1 = tmp_251_reg_6880;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg26_fsm_66 == ap_CS_fsm))) begin
b_address1 = tmp_249_reg_6860;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg25_fsm_65 == ap_CS_fsm))) begin
b_address1 = tmp_247_reg_6800;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg24_fsm_64 == ap_CS_fsm))) begin
b_address1 = tmp_245_reg_6780;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg23_fsm_63 == ap_CS_fsm))) begin
b_address1 = tmp_243_reg_6760;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg22_fsm_62 == ap_CS_fsm))) begin
b_address1 = tmp_241_reg_6731;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg21_fsm_61 == ap_CS_fsm))) begin
b_address1 = tmp_239_reg_6711;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg20_fsm_60 == ap_CS_fsm))) begin
b_address1 = tmp_237_reg_6691;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg19_fsm_59 == ap_CS_fsm))) begin
b_address1 = tmp_235_reg_6671;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg18_fsm_58 == ap_CS_fsm))) begin
b_address1 = tmp_233_reg_6641;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg17_fsm_57 == ap_CS_fsm))) begin
b_address1 = tmp_231_reg_6621;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg16_fsm_56 == ap_CS_fsm))) begin
b_address1 = tmp_229_reg_6601;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg15_fsm_55 == ap_CS_fsm))) begin
b_address1 = tmp_227_reg_6572;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg14_fsm_54 == ap_CS_fsm))) begin
b_address1 = tmp_225_reg_6552;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg13_fsm_53 == ap_CS_fsm))) begin
b_address1 = tmp_223_reg_6532;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg12_fsm_52 == ap_CS_fsm))) begin
b_address1 = tmp_221_reg_6512;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg11_fsm_51 == ap_CS_fsm))) begin
b_address1 = tmp_219_reg_6482;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg10_fsm_50 == ap_CS_fsm))) begin
b_address1 = tmp_217_reg_6462;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg9_fsm_49 == ap_CS_fsm))) begin
b_address1 = tmp_215_reg_6442;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg8_fsm_48 == ap_CS_fsm))) begin
b_address1 = tmp_213_reg_6413;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg7_fsm_47 == ap_CS_fsm))) begin
b_address1 = tmp_211_reg_6393;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg6_fsm_46 == ap_CS_fsm))) begin
b_address1 = tmp_209_reg_6373;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg5_fsm_45 == ap_CS_fsm))) begin
b_address1 = tmp_207_reg_6348;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg4_fsm_44 == ap_CS_fsm))) begin
b_address1 = tmp_205_reg_6307;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg3_fsm_43 == ap_CS_fsm))) begin
b_address1 = tmp_203_reg_6265;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg2_fsm_42 == ap_CS_fsm))) begin
b_address1 = tmp_201_reg_6223;
end else if (((ap_ST_pp5_stg0_fsm_22 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp5_it3) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond9_reg_5697_pp5_it2))) begin
b_address1 = ap_reg_ppstg_tmp_168_reg_5895_pp5_it2;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp5_it2) & (ap_ST_pp5_stg7_fsm_29 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond9_reg_5697_pp5_it2))) begin
b_address1 = ap_reg_ppstg_tmp_164_reg_5880_pp5_it2;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp5_it2) & (ap_ST_pp5_stg6_fsm_28 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond9_reg_5697_pp5_it2))) begin
b_address1 = ap_reg_ppstg_tmp_160_reg_5840_pp5_it2;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp5_it1) & (ap_ST_pp5_stg5_fsm_27 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond9_reg_5697_pp5_it1))) begin
b_address1 = ap_reg_ppstg_tmp_130_reg_5770_pp5_it1;
end else if (((ap_ST_pp1_stg0_fsm_4 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it3) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond3_reg_5195_pp1_it2))) begin
b_address1 = ap_reg_ppstg_tmp_51_reg_5417_pp1_it2;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it2) & (ap_ST_pp1_stg7_fsm_11 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond3_reg_5195_pp1_it2))) begin
b_address1 = ap_reg_ppstg_tmp_47_reg_5407_pp1_it2;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it2) & (ap_ST_pp1_stg6_fsm_10 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond3_reg_5195_pp1_it2))) begin
b_address1 = ap_reg_ppstg_tmp_44_reg_5367_pp1_it2;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_ST_pp1_stg5_fsm_9 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond3_reg_5195_pp1_it1))) begin
b_address1 = ap_reg_ppstg_tmp_15_reg_5272_pp1_it1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp7_it1) & (ap_ST_pp7_stg3_fsm_34 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond12_reg_5924_pp7_it1))) begin
b_address1 = tmp_194_fu_4340_p1;
end else if (((ap_ST_pp7_stg2_fsm_33 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp7_it0) & (ap_const_lv1_0 == exitcond12_reg_5924))) begin
b_address1 = tmp_190_fu_4238_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp7_it0) & (ap_const_lv1_0 == exitcond12_reg_5924) & (ap_ST_pp7_stg1_fsm_32 == ap_CS_fsm))) begin
b_address1 = tmp_182_fu_4173_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp5_it0) & (ap_const_lv1_0 == exitcond9_reg_5697) & (ap_ST_pp5_stg4_fsm_26 == ap_CS_fsm))) begin
b_address1 = tmp_170_fu_3943_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp5_it0) & (ap_const_lv1_0 == exitcond9_reg_5697) & (ap_ST_pp5_stg3_fsm_25 == ap_CS_fsm))) begin
b_address1 = tmp_162_fu_3905_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp5_it0) & (ap_const_lv1_0 == exitcond9_reg_5697) & (ap_ST_pp5_stg2_fsm_24 == ap_CS_fsm))) begin
b_address1 = tmp_150_fu_3840_p1;
end else if (((ap_ST_pp5_stg1_fsm_23 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp5_it0) & (ap_const_lv1_0 == exitcond9_reg_5697))) begin
b_address1 = tmp_134_fu_3775_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp3_it1) & (ap_ST_pp3_stg3_fsm_16 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond6_reg_5446_pp3_it1))) begin
b_address1 = tmp_106_fu_3601_p1;
end else if (((ap_ST_pp3_stg2_fsm_15 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp3_it0) & (ap_const_lv1_0 == exitcond6_reg_5446))) begin
b_address1 = tmp_90_fu_3415_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp3_it0) & (ap_const_lv1_0 == exitcond6_reg_5446) & (ap_ST_pp3_stg1_fsm_14 == ap_CS_fsm))) begin
b_address1 = tmp_83_fu_3247_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond3_reg_5195) & (ap_ST_pp1_stg4_fsm_8 == ap_CS_fsm))) begin
b_address1 = tmp_55_fu_2970_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond3_reg_5195) & (ap_ST_pp1_stg3_fsm_7 == ap_CS_fsm))) begin
b_address1 = tmp_46_fu_2872_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond3_reg_5195) & (ap_ST_pp1_stg2_fsm_6 == ap_CS_fsm))) begin
b_address1 = tmp_32_fu_2765_p1;
end else if (((ap_ST_pp1_stg1_fsm_5 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond3_reg_5195))) begin
b_address1 = tmp_16_fu_2597_p1;
end else begin
b_address1 = tmp_255_reg_6920;
end
end
/// b_ce0 assign process. ///
always @ (ap_CS_fsm or ap_reg_ppiten_pp0_it6 or ap_reg_ppiten_pp1_it0 or ap_reg_ppiten_pp1_it1 or ap_reg_ppiten_pp1_it2 or exitcond3_reg_5195 or ap_reg_ppiten_pp3_it0 or ap_reg_ppiten_pp3_it1 or exitcond6_reg_5446 or ap_reg_ppiten_pp4_it6 or ap_reg_ppiten_pp5_it0 or ap_reg_ppiten_pp5_it1 or ap_reg_ppiten_pp5_it2 or exitcond9_reg_5697 or ap_reg_ppiten_pp7_it0 or ap_reg_ppiten_pp7_it1 or exitcond12_reg_5924 or ap_reg_ppiten_pp2_it0 or ap_reg_ppiten_pp6_it0 or ap_reg_ppstg_exitcond6_reg_5446_pp3_it1 or ap_reg_ppstg_exitcond12_reg_5924_pp7_it1 or ap_reg_ppstg_exitcond3_reg_5195_pp1_it1 or ap_reg_ppstg_exitcond9_reg_5697_pp5_it1 or ap_reg_ppstg_exitcond1_reg_5171_pp0_it5 or exitcond4_fu_2988_p2 or exitcond6_fu_3025_p2 or ap_reg_ppstg_exitcond7_reg_5678_pp4_it5 or exitcond10_fu_3978_p2 or exitcond12_fu_4005_p2 or exitcond_reg_6132 or ap_reg_ppiten_pp8_it0 or ap_reg_ppiten_pp8_it1)
begin
if ((((ap_ST_pp1_stg1_fsm_5 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond3_reg_5195)) | ((ap_ST_pp3_stg2_fsm_15 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp3_it0) & (ap_const_lv1_0 == exitcond6_reg_5446)) | ((ap_ST_pp5_stg1_fsm_23 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp5_it0) & (ap_const_lv1_0 == exitcond9_reg_5697)) | ((ap_ST_pp7_stg2_fsm_33 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp7_it0) & (ap_const_lv1_0 == exitcond12_reg_5924)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond3_reg_5195) & (ap_ST_pp1_stg2_fsm_6 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp3_it0) & (ap_const_lv1_0 == exitcond6_reg_5446) & (ap_ST_pp3_stg1_fsm_14 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp5_it0) & (ap_const_lv1_0 == exitcond9_reg_5697) & (ap_ST_pp5_stg2_fsm_24 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp7_it0) & (ap_const_lv1_0 == exitcond12_reg_5924) & (ap_ST_pp7_stg1_fsm_32 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp3_it0) & (ap_const_lv1_0 == exitcond6_reg_5446) & (ap_ST_pp3_stg3_fsm_16 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp7_it0) & (ap_const_lv1_0 == exitcond12_reg_5924) & (ap_ST_pp7_stg3_fsm_34 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond3_reg_5195) & (ap_ST_pp1_stg3_fsm_7 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp5_it0) & (ap_const_lv1_0 == exitcond9_reg_5697) & (ap_ST_pp5_stg3_fsm_25 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond3_reg_5195) & (ap_ST_pp1_stg4_fsm_8 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp5_it0) & (ap_const_lv1_0 == exitcond9_reg_5697) & (ap_ST_pp5_stg4_fsm_26 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp3_it1) & (ap_ST_pp3_stg4_fsm_17 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond6_reg_5446_pp3_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp7_it1) & (ap_ST_pp7_stg4_fsm_35 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond12_reg_5924_pp7_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_ST_pp1_stg5_fsm_9 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond3_reg_5195_pp1_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_ST_pp1_stg6_fsm_10 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond3_reg_5195_pp1_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_ST_pp1_stg7_fsm_11 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond3_reg_5195_pp1_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp5_it1) & (ap_ST_pp5_stg5_fsm_27 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond9_reg_5697_pp5_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp5_it1) & (ap_ST_pp5_stg6_fsm_28 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond9_reg_5697_pp5_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp5_it1) & (ap_ST_pp5_stg7_fsm_29 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond9_reg_5697_pp5_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it2) & (ap_ST_pp1_stg0_fsm_4 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond3_reg_5195_pp1_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp5_it2) & (ap_ST_pp5_stg0_fsm_22 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond9_reg_5697_pp5_it1)) | ((ap_ST_pp2_stg0_fsm_12 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp2_it0) & (ap_const_lv1_0 == exitcond4_fu_2988_p2)) | ((ap_const_logic_1 == ap_reg_ppiten_pp3_it0) & (ap_ST_pp3_stg0_fsm_13 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond6_fu_3025_p2)) | ((ap_ST_pp6_stg0_fsm_30 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp6_it0) & (ap_const_lv1_0 == exitcond10_fu_3978_p2)) | ((ap_const_logic_1 == ap_reg_ppiten_pp7_it0) & (ap_ST_pp7_stg0_fsm_31 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond12_fu_4005_p2)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_ST_pp8_stg1_fsm_41 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond_reg_6132)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg2_fsm_42 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg3_fsm_43 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg4_fsm_44 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg5_fsm_45 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg6_fsm_46 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg7_fsm_47 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg8_fsm_48 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg9_fsm_49 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg10_fsm_50 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg11_fsm_51 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg12_fsm_52 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg13_fsm_53 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg14_fsm_54 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg15_fsm_55 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg16_fsm_56 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg17_fsm_57 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg18_fsm_58 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg19_fsm_59 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg20_fsm_60 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg21_fsm_61 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg22_fsm_62 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg23_fsm_63 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg24_fsm_64 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg25_fsm_65 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg26_fsm_66 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg27_fsm_67 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg28_fsm_68 == ap_CS_fsm)) | ((ap_ST_pp8_stg0_fsm_40 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp8_it1) & (ap_const_lv1_0 == exitcond_reg_6132)) | ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond1_reg_5171_pp0_it5)) | ((ap_ST_pp4_stg0_fsm_21 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp4_it6) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond7_reg_5678_pp4_it5)))) begin
b_ce0 = ap_const_logic_1;
end else begin
b_ce0 = ap_const_logic_0;
end
end
/// b_ce1 assign process. ///
always @ (ap_CS_fsm or ap_reg_ppiten_pp1_it0 or ap_reg_ppiten_pp1_it1 or ap_reg_ppiten_pp1_it2 or exitcond3_reg_5195 or ap_reg_ppiten_pp3_it0 or ap_reg_ppiten_pp3_it1 or exitcond6_reg_5446 or ap_reg_ppiten_pp5_it0 or ap_reg_ppiten_pp5_it1 or ap_reg_ppiten_pp5_it2 or exitcond9_reg_5697 or ap_reg_ppiten_pp7_it0 or ap_reg_ppiten_pp7_it1 or exitcond12_reg_5924 or ap_reg_ppstg_exitcond6_reg_5446_pp3_it1 or ap_reg_ppstg_exitcond12_reg_5924_pp7_it1 or ap_reg_ppiten_pp1_it3 or ap_reg_ppiten_pp5_it3 or ap_reg_ppstg_exitcond3_reg_5195_pp1_it1 or ap_reg_ppstg_exitcond9_reg_5697_pp5_it1 or ap_reg_ppstg_exitcond3_reg_5195_pp1_it2 or ap_reg_ppstg_exitcond9_reg_5697_pp5_it2 or exitcond_reg_6132 or ap_reg_ppiten_pp8_it0 or ap_reg_ppiten_pp8_it1)
begin
if ((((ap_ST_pp1_stg1_fsm_5 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond3_reg_5195)) | ((ap_ST_pp3_stg2_fsm_15 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp3_it0) & (ap_const_lv1_0 == exitcond6_reg_5446)) | ((ap_ST_pp5_stg1_fsm_23 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp5_it0) & (ap_const_lv1_0 == exitcond9_reg_5697)) | ((ap_ST_pp7_stg2_fsm_33 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp7_it0) & (ap_const_lv1_0 == exitcond12_reg_5924)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond3_reg_5195) & (ap_ST_pp1_stg2_fsm_6 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp3_it0) & (ap_const_lv1_0 == exitcond6_reg_5446) & (ap_ST_pp3_stg1_fsm_14 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp5_it0) & (ap_const_lv1_0 == exitcond9_reg_5697) & (ap_ST_pp5_stg2_fsm_24 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp7_it0) & (ap_const_lv1_0 == exitcond12_reg_5924) & (ap_ST_pp7_stg1_fsm_32 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond3_reg_5195) & (ap_ST_pp1_stg3_fsm_7 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp5_it0) & (ap_const_lv1_0 == exitcond9_reg_5697) & (ap_ST_pp5_stg3_fsm_25 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond3_reg_5195) & (ap_ST_pp1_stg4_fsm_8 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp5_it0) & (ap_const_lv1_0 == exitcond9_reg_5697) & (ap_ST_pp5_stg4_fsm_26 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_ST_pp1_stg5_fsm_9 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond3_reg_5195_pp1_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp3_it1) & (ap_ST_pp3_stg3_fsm_16 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond6_reg_5446_pp3_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp5_it1) & (ap_ST_pp5_stg5_fsm_27 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond9_reg_5697_pp5_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp7_it1) & (ap_ST_pp7_stg3_fsm_34 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond12_reg_5924_pp7_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg2_fsm_42 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg3_fsm_43 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg4_fsm_44 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg5_fsm_45 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg6_fsm_46 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg7_fsm_47 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg8_fsm_48 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg9_fsm_49 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg10_fsm_50 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg11_fsm_51 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg12_fsm_52 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg13_fsm_53 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg14_fsm_54 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg15_fsm_55 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg16_fsm_56 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg17_fsm_57 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg18_fsm_58 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg19_fsm_59 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg20_fsm_60 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg21_fsm_61 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg22_fsm_62 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg23_fsm_63 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg24_fsm_64 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg25_fsm_65 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg26_fsm_66 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg27_fsm_67 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg28_fsm_68 == ap_CS_fsm)) | ((ap_ST_pp8_stg0_fsm_40 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp8_it1) & (ap_const_lv1_0 == exitcond_reg_6132)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it2) & (ap_ST_pp1_stg6_fsm_10 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond3_reg_5195_pp1_it2)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it2) & (ap_ST_pp1_stg7_fsm_11 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond3_reg_5195_pp1_it2)) | ((ap_ST_pp1_stg0_fsm_4 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it3) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond3_reg_5195_pp1_it2)) | ((ap_const_logic_1 == ap_reg_ppiten_pp5_it2) & (ap_ST_pp5_stg6_fsm_28 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond9_reg_5697_pp5_it2)) | ((ap_const_logic_1 == ap_reg_ppiten_pp5_it2) & (ap_ST_pp5_stg7_fsm_29 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond9_reg_5697_pp5_it2)) | ((ap_ST_pp5_stg0_fsm_22 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp5_it3) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond9_reg_5697_pp5_it2)))) begin
b_ce1 = ap_const_logic_1;
end else begin
b_ce1 = ap_const_logic_0;
end
end
/// b_d0 assign process. ///
always @ (ap_CS_fsm or a_q0 or ap_reg_ppiten_pp0_it6 or ap_reg_ppiten_pp1_it1 or ap_reg_ppiten_pp1_it2 or ap_reg_ppiten_pp4_it6 or ap_reg_ppiten_pp5_it1 or ap_reg_ppiten_pp5_it2 or reg_2177 or ap_reg_ppstg_exitcond3_reg_5195_pp1_it1 or ap_reg_ppstg_exitcond9_reg_5697_pp5_it1 or reg_2294 or ap_reg_ppstg_exitcond1_reg_5171_pp0_it5 or ap_reg_ppstg_exitcond7_reg_5678_pp4_it5 or exitcond_reg_6132 or ap_reg_ppiten_pp8_it0 or ap_reg_ppiten_pp8_it1)
begin
if ((((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_ST_pp8_stg1_fsm_41 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond_reg_6132)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg2_fsm_42 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg3_fsm_43 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg4_fsm_44 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg5_fsm_45 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg6_fsm_46 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg7_fsm_47 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg8_fsm_48 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg9_fsm_49 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg10_fsm_50 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg11_fsm_51 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg12_fsm_52 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg13_fsm_53 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg14_fsm_54 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg15_fsm_55 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg16_fsm_56 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg17_fsm_57 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg18_fsm_58 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg19_fsm_59 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg20_fsm_60 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg21_fsm_61 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg22_fsm_62 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg23_fsm_63 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg24_fsm_64 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg25_fsm_65 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg26_fsm_66 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg27_fsm_67 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg28_fsm_68 == ap_CS_fsm)) | ((ap_ST_pp8_stg0_fsm_40 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp8_it1) & (ap_const_lv1_0 == exitcond_reg_6132)))) begin
b_d0 = a_q0;
end else if ((((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_ST_pp1_stg5_fsm_9 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond3_reg_5195_pp1_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_ST_pp1_stg6_fsm_10 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond3_reg_5195_pp1_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_ST_pp1_stg7_fsm_11 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond3_reg_5195_pp1_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp5_it1) & (ap_ST_pp5_stg5_fsm_27 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond9_reg_5697_pp5_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp5_it1) & (ap_ST_pp5_stg6_fsm_28 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond9_reg_5697_pp5_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp5_it1) & (ap_ST_pp5_stg7_fsm_29 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond9_reg_5697_pp5_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it2) & (ap_ST_pp1_stg0_fsm_4 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond3_reg_5195_pp1_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp5_it2) & (ap_ST_pp5_stg0_fsm_22 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond9_reg_5697_pp5_it1)))) begin
b_d0 = reg_2294;
end else if ((((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond1_reg_5171_pp0_it5)) | ((ap_ST_pp4_stg0_fsm_21 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp4_it6) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond7_reg_5678_pp4_it5)))) begin
b_d0 = reg_2177;
end else begin
b_d0 = reg_2294;
end
end
/// b_d1 assign process. ///
always @ (ap_CS_fsm or a_q1 or ap_reg_ppiten_pp1_it1 or ap_reg_ppiten_pp1_it2 or ap_reg_ppiten_pp5_it1 or ap_reg_ppiten_pp5_it2 or ap_reg_ppiten_pp1_it3 or ap_reg_ppiten_pp5_it3 or ap_reg_ppstg_exitcond3_reg_5195_pp1_it1 or ap_reg_ppstg_exitcond9_reg_5697_pp5_it1 or reg_2305 or reg_2335 or reg_2341 or ap_reg_ppstg_exitcond3_reg_5195_pp1_it2 or ap_reg_ppstg_exitcond9_reg_5697_pp5_it2 or reg_2347 or exitcond_reg_6132 or ap_reg_ppiten_pp8_it0 or ap_reg_ppiten_pp8_it1)
begin
if ((((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg2_fsm_42 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg3_fsm_43 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg4_fsm_44 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg5_fsm_45 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg6_fsm_46 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg7_fsm_47 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg8_fsm_48 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg9_fsm_49 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg10_fsm_50 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg11_fsm_51 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg12_fsm_52 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg13_fsm_53 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg14_fsm_54 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg15_fsm_55 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg16_fsm_56 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg17_fsm_57 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg18_fsm_58 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg19_fsm_59 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg20_fsm_60 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg21_fsm_61 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg22_fsm_62 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg23_fsm_63 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg24_fsm_64 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg25_fsm_65 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg26_fsm_66 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg27_fsm_67 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg28_fsm_68 == ap_CS_fsm)) | ((ap_ST_pp8_stg0_fsm_40 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp8_it1) & (ap_const_lv1_0 == exitcond_reg_6132)))) begin
b_d1 = a_q1;
end else if ((((ap_ST_pp1_stg0_fsm_4 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it3) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond3_reg_5195_pp1_it2)) | ((ap_ST_pp5_stg0_fsm_22 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp5_it3) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond9_reg_5697_pp5_it2)))) begin
b_d1 = reg_2347;
end else if ((((ap_const_logic_1 == ap_reg_ppiten_pp1_it2) & (ap_ST_pp1_stg7_fsm_11 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond3_reg_5195_pp1_it2)) | ((ap_const_logic_1 == ap_reg_ppiten_pp5_it2) & (ap_ST_pp5_stg7_fsm_29 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond9_reg_5697_pp5_it2)))) begin
b_d1 = reg_2341;
end else if ((((ap_const_logic_1 == ap_reg_ppiten_pp1_it2) & (ap_ST_pp1_stg6_fsm_10 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond3_reg_5195_pp1_it2)) | ((ap_const_logic_1 == ap_reg_ppiten_pp5_it2) & (ap_ST_pp5_stg6_fsm_28 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond9_reg_5697_pp5_it2)))) begin
b_d1 = reg_2335;
end else if ((((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_ST_pp1_stg5_fsm_9 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond3_reg_5195_pp1_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp5_it1) & (ap_ST_pp5_stg5_fsm_27 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond9_reg_5697_pp5_it1)))) begin
b_d1 = reg_2305;
end else begin
b_d1 = reg_2347;
end
end
/// b_we0 assign process. ///
always @ (ap_CS_fsm or ap_reg_ppiten_pp0_it6 or ap_reg_ppiten_pp1_it1 or ap_reg_ppiten_pp1_it2 or ap_reg_ppiten_pp4_it6 or ap_reg_ppiten_pp5_it1 or ap_reg_ppiten_pp5_it2 or ap_reg_ppstg_exitcond3_reg_5195_pp1_it1 or ap_reg_ppstg_exitcond9_reg_5697_pp5_it1 or ap_reg_ppstg_exitcond1_reg_5171_pp0_it5 or ap_reg_ppstg_exitcond7_reg_5678_pp4_it5 or exitcond_reg_6132 or ap_reg_ppiten_pp8_it0 or ap_reg_ppiten_pp8_it1)
begin
if ((((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_ST_pp1_stg5_fsm_9 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond3_reg_5195_pp1_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_ST_pp1_stg6_fsm_10 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond3_reg_5195_pp1_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_ST_pp1_stg7_fsm_11 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond3_reg_5195_pp1_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp5_it1) & (ap_ST_pp5_stg5_fsm_27 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond9_reg_5697_pp5_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp5_it1) & (ap_ST_pp5_stg6_fsm_28 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond9_reg_5697_pp5_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp5_it1) & (ap_ST_pp5_stg7_fsm_29 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond9_reg_5697_pp5_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it2) & (ap_ST_pp1_stg0_fsm_4 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond3_reg_5195_pp1_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp5_it2) & (ap_ST_pp5_stg0_fsm_22 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond9_reg_5697_pp5_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_ST_pp8_stg1_fsm_41 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond_reg_6132)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg2_fsm_42 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg3_fsm_43 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg4_fsm_44 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg5_fsm_45 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg6_fsm_46 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg7_fsm_47 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg8_fsm_48 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg9_fsm_49 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg10_fsm_50 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg11_fsm_51 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg12_fsm_52 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg13_fsm_53 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg14_fsm_54 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg15_fsm_55 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg16_fsm_56 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg17_fsm_57 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg18_fsm_58 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg19_fsm_59 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg20_fsm_60 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg21_fsm_61 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg22_fsm_62 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg23_fsm_63 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg24_fsm_64 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg25_fsm_65 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg26_fsm_66 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg27_fsm_67 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg28_fsm_68 == ap_CS_fsm)) | ((ap_ST_pp8_stg0_fsm_40 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp8_it1) & (ap_const_lv1_0 == exitcond_reg_6132)) | ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond1_reg_5171_pp0_it5)) | ((ap_ST_pp4_stg0_fsm_21 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp4_it6) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond7_reg_5678_pp4_it5)))) begin
b_we0 = ap_const_logic_1;
end else begin
b_we0 = ap_const_logic_0;
end
end
/// b_we1 assign process. ///
always @ (ap_CS_fsm or ap_reg_ppiten_pp1_it1 or ap_reg_ppiten_pp1_it2 or ap_reg_ppiten_pp5_it1 or ap_reg_ppiten_pp5_it2 or ap_reg_ppiten_pp1_it3 or ap_reg_ppiten_pp5_it3 or ap_reg_ppstg_exitcond3_reg_5195_pp1_it1 or ap_reg_ppstg_exitcond9_reg_5697_pp5_it1 or ap_reg_ppstg_exitcond3_reg_5195_pp1_it2 or ap_reg_ppstg_exitcond9_reg_5697_pp5_it2 or exitcond_reg_6132 or ap_reg_ppiten_pp8_it0 or ap_reg_ppiten_pp8_it1)
begin
if ((((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_ST_pp1_stg5_fsm_9 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond3_reg_5195_pp1_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp5_it1) & (ap_ST_pp5_stg5_fsm_27 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond9_reg_5697_pp5_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg2_fsm_42 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg3_fsm_43 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg4_fsm_44 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg5_fsm_45 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg6_fsm_46 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg7_fsm_47 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg8_fsm_48 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg9_fsm_49 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg10_fsm_50 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg11_fsm_51 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg12_fsm_52 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg13_fsm_53 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg14_fsm_54 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg15_fsm_55 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg16_fsm_56 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg17_fsm_57 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg18_fsm_58 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg19_fsm_59 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg20_fsm_60 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg21_fsm_61 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg22_fsm_62 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg23_fsm_63 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg24_fsm_64 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg25_fsm_65 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg26_fsm_66 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg27_fsm_67 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg28_fsm_68 == ap_CS_fsm)) | ((ap_ST_pp8_stg0_fsm_40 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp8_it1) & (ap_const_lv1_0 == exitcond_reg_6132)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it2) & (ap_ST_pp1_stg6_fsm_10 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond3_reg_5195_pp1_it2)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it2) & (ap_ST_pp1_stg7_fsm_11 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond3_reg_5195_pp1_it2)) | ((ap_ST_pp1_stg0_fsm_4 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it3) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond3_reg_5195_pp1_it2)) | ((ap_const_logic_1 == ap_reg_ppiten_pp5_it2) & (ap_ST_pp5_stg6_fsm_28 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond9_reg_5697_pp5_it2)) | ((ap_const_logic_1 == ap_reg_ppiten_pp5_it2) & (ap_ST_pp5_stg7_fsm_29 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond9_reg_5697_pp5_it2)) | ((ap_ST_pp5_stg0_fsm_22 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp5_it3) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond9_reg_5697_pp5_it2)))) begin
b_we1 = ap_const_logic_1;
end else begin
b_we1 = ap_const_logic_0;
end
end
/// grp_fu_2163_p0 assign process. ///
always @ (ap_CS_fsm or reg_2171 or ap_reg_ppiten_pp1_it0 or ap_reg_ppiten_pp1_it1 or exitcond3_reg_5195 or ap_reg_ppiten_pp3_it0 or ap_reg_ppiten_pp3_it1 or exitcond6_reg_5446 or ap_reg_ppiten_pp5_it0 or ap_reg_ppiten_pp5_it1 or exitcond9_reg_5697 or ap_reg_ppiten_pp7_it0 or ap_reg_ppiten_pp7_it1 or exitcond12_reg_5924 or reg_2184 or reg_2190 or reg_2197 or reg_2204 or reg_2211 or reg_2218 or reg_2225 or reg_2232 or reg_2239 or reg_2246 or reg_2253 or reg_2260 or ap_reg_ppstg_exitcond6_reg_5446_pp3_it1 or ap_reg_ppstg_exitcond12_reg_5924_pp7_it1 or reg_2267 or ap_reg_ppstg_exitcond3_reg_5195_pp1_it1 or ap_reg_ppstg_exitcond9_reg_5697_pp5_it1 or reg_2311 or reg_2323)
begin
if ((((ap_const_logic_1 == ap_reg_ppiten_pp3_it1) & (ap_ST_pp3_stg6_fsm_19 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond6_reg_5446_pp3_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp7_it1) & (ap_ST_pp7_stg6_fsm_37 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond12_reg_5924_pp7_it1)))) begin
grp_fu_2163_p0 = reg_2267;
end else if ((((ap_const_logic_1 == ap_reg_ppiten_pp3_it1) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond6_reg_5446_pp3_it1) & (ap_ST_pp3_stg5_fsm_18 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp7_it1) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond12_reg_5924_pp7_it1) & (ap_ST_pp7_stg5_fsm_36 == ap_CS_fsm)))) begin
grp_fu_2163_p0 = reg_2260;
end else if ((((ap_const_logic_1 == ap_reg_ppiten_pp3_it1) & (ap_ST_pp3_stg4_fsm_17 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond6_reg_5446_pp3_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp7_it1) & (ap_ST_pp7_stg4_fsm_35 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond12_reg_5924_pp7_it1)))) begin
grp_fu_2163_p0 = reg_2253;
end else if ((((ap_const_logic_1 == ap_reg_ppiten_pp3_it1) & (ap_ST_pp3_stg3_fsm_16 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond6_reg_5446_pp3_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp7_it1) & (ap_ST_pp7_stg3_fsm_34 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond12_reg_5924_pp7_it1)))) begin
grp_fu_2163_p0 = reg_2239;
end else if ((((ap_ST_pp3_stg2_fsm_15 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp3_it1) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond6_reg_5446_pp3_it1)) | ((ap_ST_pp7_stg2_fsm_33 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp7_it1) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond12_reg_5924_pp7_it1)))) begin
grp_fu_2163_p0 = reg_2225;
end else if ((((ap_const_logic_1 == ap_reg_ppiten_pp3_it1) & (ap_ST_pp3_stg1_fsm_14 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond6_reg_5446_pp3_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp7_it1) & (ap_ST_pp7_stg1_fsm_32 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond12_reg_5924_pp7_it1)))) begin
grp_fu_2163_p0 = reg_2211;
end else if ((((ap_const_logic_1 == ap_reg_ppiten_pp3_it1) & (ap_const_lv1_0 == exitcond6_reg_5446) & (ap_ST_pp3_stg0_fsm_13 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp7_it1) & (ap_const_lv1_0 == exitcond12_reg_5924) & (ap_ST_pp7_stg0_fsm_31 == ap_CS_fsm)))) begin
grp_fu_2163_p0 = reg_2197;
end else if ((((ap_const_logic_1 == ap_reg_ppiten_pp3_it0) & (ap_const_lv1_0 == exitcond6_reg_5446) & (ap_ST_pp3_stg7_fsm_20 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp7_it0) & (ap_const_lv1_0 == exitcond12_reg_5924) & (ap_ST_pp7_stg7_fsm_38 == ap_CS_fsm)))) begin
grp_fu_2163_p0 = reg_2184;
end else if ((((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_ST_pp1_stg6_fsm_10 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond3_reg_5195_pp1_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp5_it1) & (ap_ST_pp5_stg6_fsm_28 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond9_reg_5697_pp5_it1)))) begin
grp_fu_2163_p0 = reg_2323;
end else if ((((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_ST_pp1_stg5_fsm_9 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond3_reg_5195_pp1_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp5_it1) & (ap_ST_pp5_stg5_fsm_27 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond9_reg_5697_pp5_it1)))) begin
grp_fu_2163_p0 = reg_2311;
end else if ((((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_ST_pp1_stg4_fsm_8 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond3_reg_5195_pp1_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp5_it1) & (ap_ST_pp5_stg4_fsm_26 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond9_reg_5697_pp5_it1)))) begin
grp_fu_2163_p0 = reg_2246;
end else if ((((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_ST_pp1_stg3_fsm_7 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond3_reg_5195_pp1_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp5_it1) & (ap_ST_pp5_stg3_fsm_25 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond9_reg_5697_pp5_it1)))) begin
grp_fu_2163_p0 = reg_2232;
end else if ((((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_ST_pp1_stg2_fsm_6 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond3_reg_5195_pp1_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp5_it1) & (ap_ST_pp5_stg2_fsm_24 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond9_reg_5697_pp5_it1)))) begin
grp_fu_2163_p0 = reg_2218;
end else if ((((ap_ST_pp1_stg1_fsm_5 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond3_reg_5195_pp1_it1)) | ((ap_ST_pp5_stg1_fsm_23 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp5_it1) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond9_reg_5697_pp5_it1)))) begin
grp_fu_2163_p0 = reg_2204;
end else if ((((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_const_lv1_0 == exitcond3_reg_5195) & (ap_ST_pp1_stg0_fsm_4 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp5_it1) & (ap_const_lv1_0 == exitcond9_reg_5697) & (ap_ST_pp5_stg0_fsm_22 == ap_CS_fsm)))) begin
grp_fu_2163_p0 = reg_2190;
end else if ((((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond3_reg_5195) & (ap_ST_pp1_stg7_fsm_11 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp5_it0) & (ap_const_lv1_0 == exitcond9_reg_5697) & (ap_ST_pp5_stg7_fsm_29 == ap_CS_fsm)))) begin
grp_fu_2163_p0 = reg_2171;
end else begin
grp_fu_2163_p0 = reg_2323;
end
end
/// grp_fu_2163_p1 assign process. ///
always @ (ap_CS_fsm or ap_reg_ppiten_pp1_it0 or ap_reg_ppiten_pp1_it1 or exitcond3_reg_5195 or ap_reg_ppiten_pp3_it0 or ap_reg_ppiten_pp3_it1 or exitcond6_reg_5446 or ap_reg_ppiten_pp5_it0 or ap_reg_ppiten_pp5_it1 or exitcond9_reg_5697 or ap_reg_ppiten_pp7_it0 or ap_reg_ppiten_pp7_it1 or exitcond12_reg_5924 or reg_2177 or ap_reg_ppstg_exitcond6_reg_5446_pp3_it1 or ap_reg_ppstg_exitcond12_reg_5924_pp7_it1 or reg_2274 or reg_2279 or reg_2284 or ap_reg_ppstg_exitcond3_reg_5195_pp1_it1 or ap_reg_ppstg_exitcond9_reg_5697_pp5_it1 or reg_2289 or reg_2300 or reg_2318 or reg_2330)
begin
if ((((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_ST_pp1_stg6_fsm_10 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond3_reg_5195_pp1_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp3_it1) & (ap_ST_pp3_stg6_fsm_19 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond6_reg_5446_pp3_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp5_it1) & (ap_ST_pp5_stg6_fsm_28 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond9_reg_5697_pp5_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp7_it1) & (ap_ST_pp7_stg6_fsm_37 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond12_reg_5924_pp7_it1)))) begin
grp_fu_2163_p1 = reg_2330;
end else if ((((ap_const_logic_1 == ap_reg_ppiten_pp3_it1) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond6_reg_5446_pp3_it1) & (ap_ST_pp3_stg5_fsm_18 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp7_it1) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond12_reg_5924_pp7_it1) & (ap_ST_pp7_stg5_fsm_36 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_ST_pp1_stg5_fsm_9 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond3_reg_5195_pp1_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp5_it1) & (ap_ST_pp5_stg5_fsm_27 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond9_reg_5697_pp5_it1)))) begin
grp_fu_2163_p1 = reg_2318;
end else if ((((ap_const_logic_1 == ap_reg_ppiten_pp3_it1) & (ap_ST_pp3_stg4_fsm_17 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond6_reg_5446_pp3_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp7_it1) & (ap_ST_pp7_stg4_fsm_35 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond12_reg_5924_pp7_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_ST_pp1_stg4_fsm_8 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond3_reg_5195_pp1_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp5_it1) & (ap_ST_pp5_stg4_fsm_26 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond9_reg_5697_pp5_it1)))) begin
grp_fu_2163_p1 = reg_2300;
end else if ((((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_ST_pp1_stg3_fsm_7 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond3_reg_5195_pp1_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp3_it1) & (ap_ST_pp3_stg3_fsm_16 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond6_reg_5446_pp3_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp5_it1) & (ap_ST_pp5_stg3_fsm_25 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond9_reg_5697_pp5_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp7_it1) & (ap_ST_pp7_stg3_fsm_34 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond12_reg_5924_pp7_it1)))) begin
grp_fu_2163_p1 = reg_2289;
end else if ((((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_ST_pp1_stg2_fsm_6 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond3_reg_5195_pp1_it1)) | ((ap_ST_pp3_stg2_fsm_15 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp3_it1) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond6_reg_5446_pp3_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp5_it1) & (ap_ST_pp5_stg2_fsm_24 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond9_reg_5697_pp5_it1)) | ((ap_ST_pp7_stg2_fsm_33 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp7_it1) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond12_reg_5924_pp7_it1)))) begin
grp_fu_2163_p1 = reg_2284;
end else if ((((ap_ST_pp1_stg1_fsm_5 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond3_reg_5195_pp1_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp3_it1) & (ap_ST_pp3_stg1_fsm_14 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond6_reg_5446_pp3_it1)) | ((ap_ST_pp5_stg1_fsm_23 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp5_it1) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond9_reg_5697_pp5_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp7_it1) & (ap_ST_pp7_stg1_fsm_32 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond12_reg_5924_pp7_it1)))) begin
grp_fu_2163_p1 = reg_2279;
end else if ((((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_const_lv1_0 == exitcond3_reg_5195) & (ap_ST_pp1_stg0_fsm_4 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp3_it1) & (ap_const_lv1_0 == exitcond6_reg_5446) & (ap_ST_pp3_stg0_fsm_13 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp5_it1) & (ap_const_lv1_0 == exitcond9_reg_5697) & (ap_ST_pp5_stg0_fsm_22 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp7_it1) & (ap_const_lv1_0 == exitcond12_reg_5924) & (ap_ST_pp7_stg0_fsm_31 == ap_CS_fsm)))) begin
grp_fu_2163_p1 = reg_2274;
end else if ((((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond3_reg_5195) & (ap_ST_pp1_stg7_fsm_11 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp3_it0) & (ap_const_lv1_0 == exitcond6_reg_5446) & (ap_ST_pp3_stg7_fsm_20 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp5_it0) & (ap_const_lv1_0 == exitcond9_reg_5697) & (ap_ST_pp5_stg7_fsm_29 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp7_it0) & (ap_const_lv1_0 == exitcond12_reg_5924) & (ap_ST_pp7_stg7_fsm_38 == ap_CS_fsm)))) begin
grp_fu_2163_p1 = reg_2177;
end else begin
grp_fu_2163_p1 = reg_2330;
end
end
/// grp_fu_2167_p0 assign process. ///
always @ (ap_CS_fsm or reg_2171 or ap_reg_ppiten_pp0_it2 or ap_reg_ppiten_pp1_it0 or ap_reg_ppiten_pp1_it1 or exitcond3_reg_5195 or ap_reg_ppiten_pp3_it0 or ap_reg_ppiten_pp3_it1 or exitcond6_reg_5446 or ap_reg_ppiten_pp4_it2 or ap_reg_ppiten_pp5_it0 or ap_reg_ppiten_pp5_it1 or exitcond9_reg_5697 or ap_reg_ppiten_pp7_it0 or ap_reg_ppiten_pp7_it1 or exitcond12_reg_5924 or ap_reg_ppiten_pp2_it2 or ap_reg_ppiten_pp6_it2 or reg_2184 or reg_2190 or reg_2197 or reg_2204 or reg_2211 or reg_2218 or reg_2225 or reg_2232 or reg_2239 or reg_2246 or reg_2253 or reg_2260 or ap_reg_ppstg_exitcond6_reg_5446_pp3_it1 or ap_reg_ppstg_exitcond12_reg_5924_pp7_it1 or reg_2267 or ap_reg_ppstg_exitcond3_reg_5195_pp1_it1 or ap_reg_ppstg_exitcond9_reg_5697_pp5_it1 or reg_2311 or reg_2323 or ap_reg_ppstg_exitcond1_reg_5171_pp0_it1 or ap_reg_ppstg_exitcond4_reg_5427_pp2_it1 or ap_reg_ppstg_exitcond7_reg_5678_pp4_it1 or ap_reg_ppstg_exitcond10_reg_5905_pp6_it1)
begin
if ((((ap_ST_pp3_stg2_fsm_15 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp3_it1) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond6_reg_5446_pp3_it1)) | ((ap_ST_pp7_stg2_fsm_33 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp7_it1) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond12_reg_5924_pp7_it1)))) begin
grp_fu_2167_p0 = reg_2323;
end else if ((((ap_const_logic_1 == ap_reg_ppiten_pp3_it1) & (ap_ST_pp3_stg1_fsm_14 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond6_reg_5446_pp3_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp7_it1) & (ap_ST_pp7_stg1_fsm_32 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond12_reg_5924_pp7_it1)))) begin
grp_fu_2167_p0 = reg_2311;
end else if ((((ap_const_logic_1 == ap_reg_ppiten_pp3_it1) & (ap_const_lv1_0 == exitcond6_reg_5446) & (ap_ST_pp3_stg0_fsm_13 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp7_it1) & (ap_const_lv1_0 == exitcond12_reg_5924) & (ap_ST_pp7_stg0_fsm_31 == ap_CS_fsm)))) begin
grp_fu_2167_p0 = reg_2246;
end else if ((((ap_const_logic_1 == ap_reg_ppiten_pp3_it0) & (ap_const_lv1_0 == exitcond6_reg_5446) & (ap_ST_pp3_stg7_fsm_20 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp7_it0) & (ap_const_lv1_0 == exitcond12_reg_5924) & (ap_ST_pp7_stg7_fsm_38 == ap_CS_fsm)))) begin
grp_fu_2167_p0 = reg_2232;
end else if ((((ap_const_logic_1 == ap_reg_ppiten_pp3_it0) & (ap_const_lv1_0 == exitcond6_reg_5446) & (ap_ST_pp3_stg6_fsm_19 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp7_it0) & (ap_const_lv1_0 == exitcond12_reg_5924) & (ap_ST_pp7_stg6_fsm_37 == ap_CS_fsm)))) begin
grp_fu_2167_p0 = reg_2218;
end else if ((((ap_const_logic_1 == ap_reg_ppiten_pp3_it0) & (ap_const_lv1_0 == exitcond6_reg_5446) & (ap_ST_pp3_stg5_fsm_18 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp7_it0) & (ap_const_lv1_0 == exitcond12_reg_5924) & (ap_ST_pp7_stg5_fsm_36 == ap_CS_fsm)))) begin
grp_fu_2167_p0 = reg_2204;
end else if ((((ap_const_logic_1 == ap_reg_ppiten_pp3_it0) & (ap_const_lv1_0 == exitcond6_reg_5446) & (ap_ST_pp3_stg4_fsm_17 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp7_it0) & (ap_const_lv1_0 == exitcond12_reg_5924) & (ap_ST_pp7_stg4_fsm_35 == ap_CS_fsm)))) begin
grp_fu_2167_p0 = reg_2190;
end else if ((((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_ST_pp1_stg2_fsm_6 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond3_reg_5195_pp1_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp5_it1) & (ap_ST_pp5_stg2_fsm_24 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond9_reg_5697_pp5_it1)))) begin
grp_fu_2167_p0 = reg_2267;
end else if ((((ap_ST_pp1_stg1_fsm_5 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond3_reg_5195_pp1_it1)) | ((ap_ST_pp5_stg1_fsm_23 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp5_it1) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond9_reg_5697_pp5_it1)))) begin
grp_fu_2167_p0 = reg_2260;
end else if ((((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_const_lv1_0 == exitcond3_reg_5195) & (ap_ST_pp1_stg0_fsm_4 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp5_it1) & (ap_const_lv1_0 == exitcond9_reg_5697) & (ap_ST_pp5_stg0_fsm_22 == ap_CS_fsm)))) begin
grp_fu_2167_p0 = reg_2253;
end else if ((((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond3_reg_5195) & (ap_ST_pp1_stg7_fsm_11 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp5_it0) & (ap_const_lv1_0 == exitcond9_reg_5697) & (ap_ST_pp5_stg7_fsm_29 == ap_CS_fsm)))) begin
grp_fu_2167_p0 = reg_2239;
end else if ((((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond3_reg_5195) & (ap_ST_pp1_stg6_fsm_10 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp5_it0) & (ap_const_lv1_0 == exitcond9_reg_5697) & (ap_ST_pp5_stg6_fsm_28 == ap_CS_fsm)))) begin
grp_fu_2167_p0 = reg_2225;
end else if ((((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond3_reg_5195) & (ap_ST_pp1_stg5_fsm_9 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp5_it0) & (ap_const_lv1_0 == exitcond9_reg_5697) & (ap_ST_pp5_stg5_fsm_27 == ap_CS_fsm)))) begin
grp_fu_2167_p0 = reg_2211;
end else if ((((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond3_reg_5195) & (ap_ST_pp1_stg4_fsm_8 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp5_it0) & (ap_const_lv1_0 == exitcond9_reg_5697) & (ap_ST_pp5_stg4_fsm_26 == ap_CS_fsm)))) begin
grp_fu_2167_p0 = reg_2197;
end else if ((((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond3_reg_5195) & (ap_ST_pp1_stg3_fsm_7 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp5_it0) & (ap_const_lv1_0 == exitcond9_reg_5697) & (ap_ST_pp5_stg3_fsm_25 == ap_CS_fsm)) | ((ap_ST_pp2_stg0_fsm_12 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp2_it2) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond4_reg_5427_pp2_it1)) | ((ap_ST_pp6_stg0_fsm_30 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp6_it2) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond10_reg_5905_pp6_it1)))) begin
grp_fu_2167_p0 = reg_2184;
end else if ((((ap_const_logic_1 == ap_reg_ppiten_pp3_it0) & (ap_const_lv1_0 == exitcond6_reg_5446) & (ap_ST_pp3_stg3_fsm_16 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp7_it0) & (ap_const_lv1_0 == exitcond12_reg_5924) & (ap_ST_pp7_stg3_fsm_34 == ap_CS_fsm)) | ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it2) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond1_reg_5171_pp0_it1)) | ((ap_ST_pp4_stg0_fsm_21 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp4_it2) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond7_reg_5678_pp4_it1)))) begin
grp_fu_2167_p0 = reg_2171;
end else begin
grp_fu_2167_p0 = reg_2323;
end
end
/// grp_fu_2167_p1 assign process. ///
always @ (ap_CS_fsm or BoundryScale or nu or ap_reg_ppiten_pp0_it2 or ap_reg_ppiten_pp1_it0 or ap_reg_ppiten_pp1_it1 or exitcond3_reg_5195 or ap_reg_ppiten_pp3_it0 or ap_reg_ppiten_pp3_it1 or exitcond6_reg_5446 or ap_reg_ppiten_pp4_it2 or ap_reg_ppiten_pp5_it0 or ap_reg_ppiten_pp5_it1 or exitcond9_reg_5697 or ap_reg_ppiten_pp7_it0 or ap_reg_ppiten_pp7_it1 or exitcond12_reg_5924 or ap_reg_ppiten_pp2_it2 or ap_reg_ppiten_pp6_it2 or ap_reg_ppstg_exitcond6_reg_5446_pp3_it1 or ap_reg_ppstg_exitcond12_reg_5924_pp7_it1 or ap_reg_ppstg_exitcond3_reg_5195_pp1_it1 or ap_reg_ppstg_exitcond9_reg_5697_pp5_it1 or ap_reg_ppstg_exitcond1_reg_5171_pp0_it1 or ap_reg_ppstg_exitcond4_reg_5427_pp2_it1 or ap_reg_ppstg_exitcond7_reg_5678_pp4_it1 or ap_reg_ppstg_exitcond10_reg_5905_pp6_it1)
begin
if ((((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond3_reg_5195) & (ap_ST_pp1_stg6_fsm_10 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp3_it0) & (ap_const_lv1_0 == exitcond6_reg_5446) & (ap_ST_pp3_stg6_fsm_19 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp5_it0) & (ap_const_lv1_0 == exitcond9_reg_5697) & (ap_ST_pp5_stg6_fsm_28 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp7_it0) & (ap_const_lv1_0 == exitcond12_reg_5924) & (ap_ST_pp7_stg6_fsm_37 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp3_it0) & (ap_const_lv1_0 == exitcond6_reg_5446) & (ap_ST_pp3_stg3_fsm_16 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp7_it0) & (ap_const_lv1_0 == exitcond12_reg_5924) & (ap_ST_pp7_stg3_fsm_34 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond3_reg_5195) & (ap_ST_pp1_stg3_fsm_7 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp5_it0) & (ap_const_lv1_0 == exitcond9_reg_5697) & (ap_ST_pp5_stg3_fsm_25 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp3_it0) & (ap_const_lv1_0 == exitcond6_reg_5446) & (ap_ST_pp3_stg4_fsm_17 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp7_it0) & (ap_const_lv1_0 == exitcond12_reg_5924) & (ap_ST_pp7_stg4_fsm_35 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond3_reg_5195) & (ap_ST_pp1_stg4_fsm_8 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp5_it0) & (ap_const_lv1_0 == exitcond9_reg_5697) & (ap_ST_pp5_stg4_fsm_26 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond3_reg_5195) & (ap_ST_pp1_stg5_fsm_9 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp5_it0) & (ap_const_lv1_0 == exitcond9_reg_5697) & (ap_ST_pp5_stg5_fsm_27 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond3_reg_5195) & (ap_ST_pp1_stg7_fsm_11 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp3_it0) & (ap_const_lv1_0 == exitcond6_reg_5446) & (ap_ST_pp3_stg7_fsm_20 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp5_it0) & (ap_const_lv1_0 == exitcond9_reg_5697) & (ap_ST_pp5_stg7_fsm_29 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp7_it0) & (ap_const_lv1_0 == exitcond12_reg_5924) & (ap_ST_pp7_stg7_fsm_38 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_const_lv1_0 == exitcond3_reg_5195) & (ap_ST_pp1_stg0_fsm_4 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp3_it1) & (ap_const_lv1_0 == exitcond6_reg_5446) & (ap_ST_pp3_stg0_fsm_13 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp5_it1) & (ap_const_lv1_0 == exitcond9_reg_5697) & (ap_ST_pp5_stg0_fsm_22 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp7_it1) & (ap_const_lv1_0 == exitcond12_reg_5924) & (ap_ST_pp7_stg0_fsm_31 == ap_CS_fsm)) | ((ap_ST_pp1_stg1_fsm_5 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond3_reg_5195_pp1_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp3_it1) & (ap_ST_pp3_stg1_fsm_14 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond6_reg_5446_pp3_it1)) | ((ap_ST_pp5_stg1_fsm_23 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp5_it1) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond9_reg_5697_pp5_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp7_it1) & (ap_ST_pp7_stg1_fsm_32 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond12_reg_5924_pp7_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_ST_pp1_stg2_fsm_6 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond3_reg_5195_pp1_it1)) | ((ap_ST_pp3_stg2_fsm_15 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp3_it1) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond6_reg_5446_pp3_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp5_it1) & (ap_ST_pp5_stg2_fsm_24 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond9_reg_5697_pp5_it1)) | ((ap_ST_pp7_stg2_fsm_33 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp7_it1) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond12_reg_5924_pp7_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp3_it0) & (ap_const_lv1_0 == exitcond6_reg_5446) & (ap_ST_pp3_stg5_fsm_18 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp7_it0) & (ap_const_lv1_0 == exitcond12_reg_5924) & (ap_ST_pp7_stg5_fsm_36 == ap_CS_fsm)))) begin
grp_fu_2167_p1 = nu;
end else if ((((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it2) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond1_reg_5171_pp0_it1)) | ((ap_ST_pp2_stg0_fsm_12 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp2_it2) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond4_reg_5427_pp2_it1)) | ((ap_ST_pp4_stg0_fsm_21 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp4_it2) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond7_reg_5678_pp4_it1)) | ((ap_ST_pp6_stg0_fsm_30 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp6_it2) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond10_reg_5905_pp6_it1)))) begin
grp_fu_2167_p1 = BoundryScale;
end else begin
grp_fu_2167_p1 = nu;
end
end
/// i_1_phi_fu_1934_p4 assign process. ///
always @ (ap_CS_fsm or i_1_reg_1930 or ap_reg_ppiten_pp1_it1 or exitcond3_reg_5195 or tmp_43_reg_5402)
begin
if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_const_lv1_0 == exitcond3_reg_5195) & (ap_ST_pp1_stg0_fsm_4 == ap_CS_fsm))) begin
i_1_phi_fu_1934_p4 = tmp_43_reg_5402;
end else begin
i_1_phi_fu_1934_p4 = i_1_reg_1930;
end
end
/// i_2_phi_fu_1945_p4 assign process. ///
always @ (ap_CS_fsm or i_2_reg_1941 or ap_reg_ppiten_pp2_it1 or exitcond4_reg_5427 or tmp_10_reg_5431)
begin
if (((ap_ST_pp2_stg0_fsm_12 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp2_it1) & (ap_const_lv1_0 == exitcond4_reg_5427))) begin
i_2_phi_fu_1945_p4 = tmp_10_reg_5431;
end else begin
i_2_phi_fu_1945_p4 = i_2_reg_1941;
end
end
/// i_3_phi_fu_1989_p4 assign process. ///
always @ (ap_CS_fsm or i_3_reg_1985 or ap_reg_ppiten_pp3_it1 or exitcond6_reg_5446 or tmp_82_reg_5653)
begin
if (((ap_const_logic_1 == ap_reg_ppiten_pp3_it1) & (ap_const_lv1_0 == exitcond6_reg_5446) & (ap_ST_pp3_stg0_fsm_13 == ap_CS_fsm))) begin
i_3_phi_fu_1989_p4 = tmp_82_reg_5653;
end else begin
i_3_phi_fu_1989_p4 = i_3_reg_1985;
end
end
/// i_4_phi_fu_2022_p4 assign process. ///
always @ (ap_CS_fsm or i_4_reg_2018 or ap_reg_ppiten_pp5_it1 or exitcond9_reg_5697 or i_4_mid2_reg_5719)
begin
if (((ap_const_logic_1 == ap_reg_ppiten_pp5_it1) & (ap_const_lv1_0 == exitcond9_reg_5697) & (ap_ST_pp5_stg0_fsm_22 == ap_CS_fsm))) begin
i_4_phi_fu_2022_p4 = i_4_mid2_reg_5719;
end else begin
i_4_phi_fu_2022_p4 = i_4_reg_2018;
end
end
/// i_5_phi_fu_2077_p4 assign process. ///
always @ (ap_CS_fsm or i_5_reg_2073 or ap_reg_ppiten_pp7_it1 or exitcond12_reg_5924 or i_5_mid2_reg_5946)
begin
if (((ap_const_logic_1 == ap_reg_ppiten_pp7_it1) & (ap_const_lv1_0 == exitcond12_reg_5924) & (ap_ST_pp7_stg0_fsm_31 == ap_CS_fsm))) begin
i_5_phi_fu_2077_p4 = i_5_mid2_reg_5946;
end else begin
i_5_phi_fu_2077_p4 = i_5_reg_2073;
end
end
/// i_6_phi_fu_2124_p6 assign process. ///
always @ (ap_CS_fsm or i_6_reg_2120 or exitcond_reg_6132 or ap_reg_ppiten_pp8_it1 or i_6_mid2_reg_6153)
begin
if (((ap_ST_pp8_stg0_fsm_40 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp8_it1) & (ap_const_lv1_0 == exitcond_reg_6132))) begin
i_6_phi_fu_2124_p6 = i_6_mid2_reg_6153;
end else begin
i_6_phi_fu_2124_p6 = i_6_reg_2120;
end
end
/// i_phi_fu_1890_p4 assign process. ///
always @ (ap_CS_fsm or i_reg_1886 or ap_reg_ppiten_pp0_it1 or exitcond1_reg_5171 or tmp_5_reg_5175)
begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (exitcond1_reg_5171 == ap_const_lv1_0))) begin
i_phi_fu_1890_p4 = tmp_5_reg_5175;
end else begin
i_phi_fu_1890_p4 = i_reg_1886;
end
end
/// indvar3_phi_fu_1923_p4 assign process. ///
always @ (ap_CS_fsm or indvar3_reg_1919 or ap_reg_ppiten_pp1_it1 or exitcond3_reg_5195 or indvar_next3_reg_5252)
begin
if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_const_lv1_0 == exitcond3_reg_5195) & (ap_ST_pp1_stg0_fsm_4 == ap_CS_fsm))) begin
indvar3_phi_fu_1923_p4 = indvar_next3_reg_5252;
end else begin
indvar3_phi_fu_1923_p4 = indvar3_reg_1919;
end
end
/// indvar4_phi_fu_2088_p4 assign process. ///
always @ (ap_CS_fsm or indvar4_reg_2084 or ap_reg_ppiten_pp7_it1 or exitcond12_reg_5924 or indvar_next5_reg_5977)
begin
if (((ap_const_logic_1 == ap_reg_ppiten_pp7_it1) & (ap_const_lv1_0 == exitcond12_reg_5924) & (ap_ST_pp7_stg0_fsm_31 == ap_CS_fsm))) begin
indvar4_phi_fu_2088_p4 = indvar_next5_reg_5977;
end else begin
indvar4_phi_fu_2088_p4 = indvar4_reg_2084;
end
end
/// indvar6_phi_fu_1978_p4 assign process. ///
always @ (ap_CS_fsm or indvar6_reg_1974 or ap_reg_ppiten_pp3_it1 or exitcond6_reg_5446 or indvar_next6_reg_5503)
begin
if (((ap_const_logic_1 == ap_reg_ppiten_pp3_it1) & (ap_const_lv1_0 == exitcond6_reg_5446) & (ap_ST_pp3_stg0_fsm_13 == ap_CS_fsm))) begin
indvar6_phi_fu_1978_p4 = indvar_next6_reg_5503;
end else begin
indvar6_phi_fu_1978_p4 = indvar6_reg_1974;
end
end
/// indvar9_phi_fu_2033_p4 assign process. ///
always @ (ap_CS_fsm or indvar9_reg_2029 or ap_reg_ppiten_pp5_it1 or exitcond9_reg_5697 or indvar_next9_reg_5750)
begin
if (((ap_const_logic_1 == ap_reg_ppiten_pp5_it1) & (ap_const_lv1_0 == exitcond9_reg_5697) & (ap_ST_pp5_stg0_fsm_22 == ap_CS_fsm))) begin
indvar9_phi_fu_2033_p4 = indvar_next9_reg_5750;
end else begin
indvar9_phi_fu_2033_p4 = indvar9_reg_2029;
end
end
/// indvar_flatten1_phi_fu_1956_p4 assign process. ///
always @ (ap_CS_fsm or indvar_flatten1_reg_1952 or ap_reg_ppiten_pp3_it1 or exitcond6_reg_5446 or indvar_flatten_next1_reg_5450)
begin
if (((ap_const_logic_1 == ap_reg_ppiten_pp3_it1) & (ap_const_lv1_0 == exitcond6_reg_5446) & (ap_ST_pp3_stg0_fsm_13 == ap_CS_fsm))) begin
indvar_flatten1_phi_fu_1956_p4 = indvar_flatten_next1_reg_5450;
end else begin
indvar_flatten1_phi_fu_1956_p4 = indvar_flatten1_reg_1952;
end
end
/// indvar_flatten2_phi_fu_2011_p4 assign process. ///
always @ (ap_CS_fsm or indvar_flatten2_reg_2007 or ap_reg_ppiten_pp5_it1 or exitcond9_reg_5697 or indvar_flatten_next2_reg_5701)
begin
if (((ap_const_logic_1 == ap_reg_ppiten_pp5_it1) & (ap_const_lv1_0 == exitcond9_reg_5697) & (ap_ST_pp5_stg0_fsm_22 == ap_CS_fsm))) begin
indvar_flatten2_phi_fu_2011_p4 = indvar_flatten_next2_reg_5701;
end else begin
indvar_flatten2_phi_fu_2011_p4 = indvar_flatten2_reg_2007;
end
end
/// indvar_flatten3_phi_fu_2066_p4 assign process. ///
always @ (ap_CS_fsm or indvar_flatten3_reg_2062 or ap_reg_ppiten_pp7_it1 or exitcond12_reg_5924 or indvar_flatten_next3_reg_5928)
begin
if (((ap_const_logic_1 == ap_reg_ppiten_pp7_it1) & (ap_const_lv1_0 == exitcond12_reg_5924) & (ap_ST_pp7_stg0_fsm_31 == ap_CS_fsm))) begin
indvar_flatten3_phi_fu_2066_p4 = indvar_flatten_next3_reg_5928;
end else begin
indvar_flatten3_phi_fu_2066_p4 = indvar_flatten3_reg_2062;
end
end
/// indvar_flatten4_phi_fu_2110_p6 assign process. ///
always @ (ap_CS_fsm or indvar_flatten4_reg_2106 or exitcond_reg_6132 or ap_reg_ppiten_pp8_it1 or indvar_flatten_next4_reg_6136)
begin
if (((ap_ST_pp8_stg0_fsm_40 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp8_it1) & (ap_const_lv1_0 == exitcond_reg_6132))) begin
indvar_flatten4_phi_fu_2110_p6 = indvar_flatten_next4_reg_6136;
end else begin
indvar_flatten4_phi_fu_2110_p6 = indvar_flatten4_reg_2106;
end
end
/// indvar_flatten_phi_fu_1901_p4 assign process. ///
always @ (ap_CS_fsm or indvar_flatten_reg_1897 or ap_reg_ppiten_pp1_it1 or exitcond3_reg_5195 or indvar_flatten_next_reg_5199)
begin
if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_const_lv1_0 == exitcond3_reg_5195) & (ap_ST_pp1_stg0_fsm_4 == ap_CS_fsm))) begin
indvar_flatten_phi_fu_1901_p4 = indvar_flatten_next_reg_5199;
end else begin
indvar_flatten_phi_fu_1901_p4 = indvar_flatten_reg_1897;
end
end
/// indvar_phi_fu_2138_p6 assign process. ///
always @ (ap_CS_fsm or indvar_reg_2134 or exitcond_reg_6132 or ap_reg_ppiten_pp8_it1 or indvar_next_reg_6186)
begin
if (((ap_ST_pp8_stg0_fsm_40 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp8_it1) & (ap_const_lv1_0 == exitcond_reg_6132))) begin
indvar_phi_fu_2138_p6 = indvar_next_reg_6186;
end else begin
indvar_phi_fu_2138_p6 = indvar_reg_2134;
end
end
/// j_1_phi_fu_1967_p4 assign process. ///
always @ (ap_CS_fsm or j_1_reg_1963 or ap_reg_ppiten_pp3_it1 or exitcond6_reg_5446 or j_1_mid2_reg_5467)
begin
if (((ap_const_logic_1 == ap_reg_ppiten_pp3_it1) & (ap_const_lv1_0 == exitcond6_reg_5446) & (ap_ST_pp3_stg0_fsm_13 == ap_CS_fsm))) begin
j_1_phi_fu_1967_p4 = j_1_mid2_reg_5467;
end else begin
j_1_phi_fu_1967_p4 = j_1_reg_1963;
end
end
/// j_2_phi_fu_2000_p4 assign process. ///
always @ (ap_CS_fsm or j_2_reg_1996 or ap_reg_ppiten_pp4_it1 or exitcond7_reg_5678 or tmp_49_reg_5682)
begin
if (((ap_ST_pp4_stg0_fsm_21 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp4_it1) & (ap_const_lv1_0 == exitcond7_reg_5678))) begin
j_2_phi_fu_2000_p4 = tmp_49_reg_5682;
end else begin
j_2_phi_fu_2000_p4 = j_2_reg_1996;
end
end
/// j_3_phi_fu_2044_p4 assign process. ///
always @ (ap_CS_fsm or j_3_reg_2040 or ap_reg_ppiten_pp5_it1 or exitcond9_reg_5697 or tmp_121_reg_5875)
begin
if (((ap_const_logic_1 == ap_reg_ppiten_pp5_it1) & (ap_const_lv1_0 == exitcond9_reg_5697) & (ap_ST_pp5_stg0_fsm_22 == ap_CS_fsm))) begin
j_3_phi_fu_2044_p4 = tmp_121_reg_5875;
end else begin
j_3_phi_fu_2044_p4 = j_3_reg_2040;
end
end
/// j_4_phi_fu_2055_p4 assign process. ///
always @ (ap_CS_fsm or j_4_reg_2051 or ap_reg_ppiten_pp6_it1 or exitcond10_reg_5905 or tmp_88_reg_5909)
begin
if (((ap_ST_pp6_stg0_fsm_30 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp6_it1) & (ap_const_lv1_0 == exitcond10_reg_5905))) begin
j_4_phi_fu_2055_p4 = tmp_88_reg_5909;
end else begin
j_4_phi_fu_2055_p4 = j_4_reg_2051;
end
end
/// j_5_phi_fu_2099_p4 assign process. ///
always @ (ap_CS_fsm or j_5_reg_2095 or ap_reg_ppiten_pp7_it1 or exitcond12_reg_5924 or tmp_157_reg_6102)
begin
if (((ap_const_logic_1 == ap_reg_ppiten_pp7_it1) & (ap_const_lv1_0 == exitcond12_reg_5924) & (ap_ST_pp7_stg0_fsm_31 == ap_CS_fsm))) begin
j_5_phi_fu_2099_p4 = tmp_157_reg_6102;
end else begin
j_5_phi_fu_2099_p4 = j_5_reg_2095;
end
end
/// j_6_phi_fu_2152_p6 assign process. ///
always @ (ap_CS_fsm or j_6_reg_2148 or exitcond_reg_6132 or ap_reg_ppiten_pp8_it1 or tmp_189_reg_6358)
begin
if (((ap_ST_pp8_stg0_fsm_40 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp8_it1) & (ap_const_lv1_0 == exitcond_reg_6132))) begin
j_6_phi_fu_2152_p6 = tmp_189_reg_6358;
end else begin
j_6_phi_fu_2152_p6 = j_6_reg_2148;
end
end
/// j_phi_fu_1912_p4 assign process. ///
always @ (ap_CS_fsm or j_reg_1908 or ap_reg_ppiten_pp1_it1 or exitcond3_reg_5195 or j_mid2_reg_5216)
begin
if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_const_lv1_0 == exitcond3_reg_5195) & (ap_ST_pp1_stg0_fsm_4 == ap_CS_fsm))) begin
j_phi_fu_1912_p4 = j_mid2_reg_5216;
end else begin
j_phi_fu_1912_p4 = j_reg_1908;
end
end
assign a_addr101_fu_2565_p1 = tmp_16_trn_cast_fu_2541_p1[6:0];
assign a_addr102_fu_2631_p1 = tmp_20_trn_cast_fu_2607_p1[6:0];
assign a_addr103_fu_2745_p1 = tmp_24_trn_cast_fu_2721_p1[6:0];
assign a_addr104_fu_2799_p1 = tmp_28_trn_cast_fu_2775_p1[6:0];
assign a_addr105_fu_2852_p1 = tmp_32_trn_cast_fu_2828_p1[6:0];
assign a_addr106_fu_2901_p1 = tmp_36_trn_cast_fu_2882_p1[6:0];
assign a_addr107_fu_2950_p1 = tmp_40_trn_cast_fu_2931_p1[6:0];
assign a_addr108_fu_3135_p2 = (b_addr53_reg_5498 | tmp_46_trn_cast1_fu_3125_p4);
assign a_addr109_fu_3140_p5 = {{a_addr108_fu_3135_p2}, {tmp_46_trn_cast_fu_3121_p1[32'd5 : 32'd0]}};
assign a_addr110_fu_3200_p2 = (b_addr54_fu_3186_p1 | tmp_46_trn_cast2_fu_3190_p4);
assign a_addr111_fu_3206_p5 = {{a_addr110_fu_3200_p2}, {tmp_46_trn_cast_fu_3121_p1[32'd5 : 32'd0]}};
assign a_addr112_fu_3266_p2 = (b_addr55_fu_3252_p1 | tmp_46_trn_cast3_fu_3256_p4);
assign a_addr113_fu_3322_p5 = {{a_addr112_reg_5548}, {tmp_46_trn_cast_reg_5508[32'd5 : 32'd0]}};
assign a_addr114_fu_3370_p2 = (b_addr56_fu_3366_p1 | tmp_46_trn_cast4_reg_5553);
assign a_addr115_fu_3375_p5 = {{a_addr114_fu_3370_p2}, {tmp_46_trn_cast_reg_5508[32'd5 : 32'd0]}};
assign a_addr116_fu_3424_p2 = (b_addr57_fu_3420_p1 | tmp_46_trn_cast5_reg_5558);
assign a_addr117_fu_3429_p5 = {{a_addr116_reg_5608}, {tmp_46_trn_cast_reg_5508[32'd5 : 32'd0]}};
assign a_addr118_fu_3477_p2 = (b_addr58_fu_3473_p1 | tmp_46_trn_cast6_reg_5563);
assign a_addr119_fu_3482_p5 = {{a_addr118_fu_3477_p2}, {tmp_46_trn_cast_reg_5508[32'd5 : 32'd0]}};
assign a_addr11_cast_fu_2731_p1 = {{1{1'b0}}, {a_addr11_fu_2725_p2}};
assign a_addr11_fu_2725_p2 = tmp_24_trn_cast_fu_2721_p1 << ap_const_lv13_6;
assign a_addr120_fu_3526_p2 = (b_addr59_fu_3522_p1 | tmp_46_trn_cast7_reg_5568);
assign a_addr121_fu_3531_p5 = {{a_addr120_fu_3526_p2}, {tmp_46_trn_cast_reg_5508[32'd5 : 32'd0]}};
assign a_addr122_fu_3575_p2 = (b_addr60_fu_3571_p1 | tmp_46_trn_cast8_reg_5573);
assign a_addr123_fu_3580_p5 = {{a_addr122_fu_3575_p2}, {tmp_46_trn_cast_reg_5508[32'd5 : 32'd0]}};
assign a_addr12_fu_2735_p2 = (a_addr11_cast_fu_2731_p1 + tmp_6_trn_cast_reg_5226);
assign a_addr13_fu_5103_p2 = (a_addr18_cast_fu_5089_p1 + tmp_180_trn_cast_reg_6233);
assign a_addr14_cast_fu_2785_p1 = {{1{1'b0}}, {a_addr14_fu_2779_p2}};
assign a_addr14_fu_2779_p2 = tmp_28_trn_cast_fu_2775_p1 << ap_const_lv13_6;
assign a_addr15_fu_2789_p2 = (a_addr14_cast_fu_2785_p1 + tmp_6_trn_cast_reg_5226);
assign a_addr17_cast_fu_2838_p1 = {{1{1'b0}}, {a_addr17_fu_2832_p2}};
assign a_addr17_fu_2832_p2 = tmp_32_trn_cast_fu_2828_p1 << ap_const_lv13_6;
assign a_addr18_cast_fu_5089_p1 = {{1{1'b0}}, {a_addr18_fu_5083_p2}};
assign a_addr18_fu_5083_p2 = tmp_172_trn_cast_fu_5079_p1 << ap_const_lv13_6;
assign a_addr19_fu_5093_p2 = (a_addr18_cast_fu_5089_p1 + tmp_176_trn_cast_reg_6191);
assign a_addr1_fu_5123_p2 = (a_addr18_cast_fu_5089_p1 + tmp_188_trn_cast_reg_6317);
assign a_addr20_fu_2842_p2 = (a_addr17_cast_fu_2838_p1 + tmp_6_trn_cast_reg_5226);
assign a_addr21_cast_fu_2892_p1 = {{1{1'b0}}, {a_addr21_fu_2886_p2}};
assign a_addr21_fu_2886_p2 = tmp_36_trn_cast_fu_2882_p1 << ap_const_lv13_6;
assign a_addr22_fu_5075_p2 = (a_addr45_cast_reg_6741 + tmp_188_trn_cast_reg_6317);
assign a_addr24_cast_fu_2941_p1 = {{1{1'b0}}, {a_addr24_fu_2935_p2}};
assign a_addr24_fu_2935_p2 = tmp_40_trn_cast_fu_2931_p1 << ap_const_lv13_6;
assign a_addr26_fu_5066_p2 = (a_addr45_cast_reg_6741 + tmp_186_trn_cast_reg_6296);
assign a_addr27_fu_4405_p2 = tmp_158_trn_cast_fu_4397_p1 << ap_const_lv13_6;
assign a_addr28_fu_4415_p2 = (a_addr63_cast_fu_4411_p1 + tmp_174_trn_cast_fu_4401_p1);
assign a_addr29_fu_4449_p2 = (a_addr63_cast_reg_6165 + tmp_176_trn_cast_fu_4445_p1);
assign a_addr2_cast_fu_2462_p1 = {{1{1'b0}}, {a_addr2_fu_2456_p2}};
assign a_addr2_fu_2456_p2 = tmp_12_trn_cast_fu_2448_p1 << ap_const_lv13_6;
assign a_addr30_fu_5057_p2 = (a_addr45_cast_reg_6741 + tmp_184_trn_cast_reg_6275);
assign a_addr31_fu_4468_p2 = (a_addr63_cast_reg_6165 + tmp_178_trn_cast_fu_4464_p1);
assign a_addr32_fu_4487_p2 = (a_addr63_cast_reg_6165 + tmp_180_trn_cast_fu_4483_p1);
assign a_addr33_fu_4506_p2 = (a_addr63_cast_reg_6165 + tmp_182_trn_cast_fu_4502_p1);
assign a_addr34_fu_5043_p2 = (a_addr45_cast_reg_6741 + tmp_182_trn_cast_reg_6254);
assign a_addr35_fu_4525_p2 = (a_addr63_cast_reg_6165 + tmp_184_trn_cast_fu_4521_p1);
assign a_addr36_fu_4544_p2 = (a_addr63_cast_reg_6165 + tmp_186_trn_cast_fu_4540_p1);
assign a_addr37_cast_fu_3684_p1 = {{1{1'b0}}, {a_addr37_fu_3678_p2}};
assign a_addr37_fu_3678_p2 = tmp_83_trn_cast_fu_3670_p1 << ap_const_lv13_6;
assign a_addr38_fu_5034_p2 = (a_addr45_cast_reg_6741 + tmp_180_trn_cast_reg_6233);
assign a_addr39_fu_3688_p2 = (a_addr37_cast_fu_3684_p1 + tmp_90_trn_cast_fu_3674_p1);
assign a_addr3_fu_2466_p2 = (a_addr2_cast_fu_2462_p1 + tmp_6_trn_cast_fu_2452_p1);
assign a_addr40_fu_3759_p2 = (a_addr37_cast_reg_5729 + tmp_94_trn_cast_fu_3755_p1);
assign a_addr41_fu_3789_p2 = (a_addr37_cast_reg_5729 + tmp_98_trn_cast_fu_3785_p1);
assign a_addr42_fu_5024_p2 = (a_addr45_cast_fu_5010_p1 + tmp_178_trn_cast_reg_6212);
assign a_addr43_fu_3825_p2 = (a_addr37_cast_reg_5729 + tmp_102_trn_cast_fu_3821_p1);
assign a_addr44_fu_3854_p2 = (a_addr37_cast_reg_5729 + tmp_106_trn_cast_fu_3850_p1);
assign a_addr45_cast_fu_5010_p1 = {{1{1'b0}}, {a_addr45_fu_5004_p2}};
assign a_addr45_fu_5004_p2 = tmp_170_trn_cast_fu_5000_p1 << ap_const_lv13_6;
assign a_addr46_fu_5014_p2 = (a_addr45_cast_fu_5010_p1 + tmp_176_trn_cast_reg_6191);
assign a_addr47_fu_3890_p2 = (a_addr37_cast_reg_5729 + tmp_110_trn_cast_fu_3886_p1);
assign a_addr48_fu_3956_p2 = (ap_reg_ppstg_a_addr37_cast_reg_5729_pp5_it1 + tmp_114_trn_cast_fu_3953_p1);
assign a_addr49_fu_4986_p2 = (a_addr72_cast_reg_6661 + tmp_188_trn_cast_reg_6317);
assign a_addr50_fu_3969_p2 = (ap_reg_ppstg_a_addr37_cast_reg_5729_pp5_it1 + tmp_118_trn_cast_fu_3966_p1);
assign a_addr51_cast_fu_4110_p1 = {{1{1'b0}}, {a_addr51_fu_4104_p2}};
assign a_addr51_fu_4104_p2 = tmp_124_trn_cast_fu_4100_p1 << ap_const_lv12_6;
assign a_addr52_fu_4114_p2 = (a_addr51_cast_fu_4110_p1 + tmp_126_trn_cast1_fu_4097_p1);
assign a_addr53_fu_4977_p2 = (a_addr72_cast_reg_6661 + tmp_186_trn_cast_reg_6296);
assign a_addr54_fu_4148_p2 = (a_addr51_cast_fu_4110_p1 + tmp_130_trn_cast1_fu_4130_p1);
assign a_addr55_fu_4181_p2 = (a_addr51_cast_reg_5982 + tmp_134_trn_cast1_fu_4178_p1);
assign a_addr56_fu_4214_p2 = (a_addr51_cast_reg_5982 + tmp_138_trn_cast1_fu_4196_p1);
assign a_addr57_fu_4968_p2 = (a_addr72_cast_reg_6661 + tmp_184_trn_cast_reg_6275);
assign a_addr58_fu_4246_p2 = (a_addr51_cast_reg_5982 + tmp_142_trn_cast1_fu_4243_p1);
assign a_addr59_fu_4279_p2 = (a_addr51_cast_reg_5982 + tmp_146_trn_cast1_fu_4261_p1);
assign a_addr5_cast_fu_2551_p1 = {{1{1'b0}}, {a_addr5_fu_2545_p2}};
assign a_addr5_fu_2545_p2 = tmp_16_trn_cast_fu_2541_p1 << ap_const_lv13_6;
assign a_addr60_fu_4298_p2 = (a_addr51_cast_reg_5982 + tmp_150_trn_cast1_fu_4294_p1);
assign a_addr61_fu_4959_p2 = (a_addr72_cast_reg_6661 + tmp_182_trn_cast_reg_6254);
assign a_addr62_fu_4317_p2 = (a_addr51_cast_reg_5982 + tmp_154_trn_cast1_fu_4313_p1);
assign a_addr63_cast_fu_4411_p1 = {{1{1'b0}}, {a_addr27_fu_4405_p2}};
assign a_addr63_fu_4568_p2 = (a_addr63_cast_reg_6165 + tmp_188_trn_cast_fu_4564_p1);
assign a_addr64_fu_4582_p2 = tmp_160_trn_cast_fu_4578_p1 << ap_const_lv13_6;
assign a_addr65_fu_4950_p2 = (a_addr72_cast_reg_6661 + tmp_180_trn_cast_reg_6233);
assign a_addr66_fu_4592_p2 = (a_addr77_cast_fu_4588_p1 + tmp_176_trn_cast_reg_6191);
assign a_addr67_fu_4607_p2 = (a_addr77_cast_reg_6338 + tmp_178_trn_cast_reg_6212);
assign a_addr68_fu_4616_p2 = (a_addr77_cast_reg_6338 + tmp_180_trn_cast_reg_6233);
assign a_addr69_fu_4941_p2 = (a_addr72_cast_reg_6661 + tmp_178_trn_cast_reg_6212);
assign a_addr6_fu_2555_p2 = (a_addr5_cast_fu_2551_p1 + tmp_6_trn_cast_reg_5226);
assign a_addr70_fu_4625_p2 = (a_addr77_cast_reg_6338 + tmp_182_trn_cast_reg_6254);
assign a_addr71_fu_4634_p2 = (a_addr77_cast_reg_6338 + tmp_184_trn_cast_reg_6275);
assign a_addr72_cast_fu_4927_p1 = {{1{1'b0}}, {a_addr72_fu_4921_p2}};
assign a_addr72_fu_4921_p2 = tmp_168_trn_cast_fu_4917_p1 << ap_const_lv13_6;
assign a_addr73_fu_4931_p2 = (a_addr72_cast_fu_4927_p1 + tmp_176_trn_cast_reg_6191);
assign a_addr74_fu_4643_p2 = (a_addr77_cast_reg_6338 + tmp_186_trn_cast_reg_6296);
assign a_addr75_fu_4652_p2 = (a_addr77_cast_reg_6338 + tmp_188_trn_cast_reg_6317);
assign a_addr76_fu_4908_p2 = (a_addr99_cast_reg_6582 + tmp_188_trn_cast_reg_6317);
assign a_addr77_cast_fu_4588_p1 = {{1{1'b0}}, {a_addr64_fu_4582_p2}};
assign a_addr77_fu_4670_p2 = tmp_162_trn_cast_fu_4666_p1 << ap_const_lv13_6;
assign a_addr78_fu_4680_p2 = (a_addr87_cast_fu_4676_p1 + tmp_176_trn_cast_reg_6191);
assign a_addr79_fu_4690_p2 = (a_addr87_cast_fu_4676_p1 + tmp_178_trn_cast_reg_6212);
assign a_addr7_fu_5113_p2 = (a_addr18_cast_fu_5089_p1 + tmp_184_trn_cast_reg_6275);
assign a_addr80_fu_4894_p2 = (a_addr99_cast_reg_6582 + tmp_186_trn_cast_reg_6296);
assign a_addr81_fu_4700_p2 = (a_addr87_cast_reg_6423 + tmp_180_trn_cast_reg_6233);
assign a_addr82_fu_4709_p2 = (a_addr87_cast_reg_6423 + tmp_182_trn_cast_reg_6254);
assign a_addr83_fu_4718_p2 = (a_addr87_cast_reg_6423 + tmp_184_trn_cast_reg_6275);
assign a_addr84_fu_4885_p2 = (a_addr99_cast_reg_6582 + tmp_184_trn_cast_reg_6275);
assign a_addr85_fu_4727_p2 = (a_addr87_cast_reg_6423 + tmp_186_trn_cast_reg_6296);
assign a_addr86_fu_4741_p2 = (a_addr87_cast_reg_6423 + tmp_188_trn_cast_reg_6317);
assign a_addr87_cast_fu_4676_p1 = {{1{1'b0}}, {a_addr77_fu_4670_p2}};
assign a_addr87_fu_4754_p2 = tmp_164_trn_cast_fu_4750_p1 << ap_const_lv13_6;
assign a_addr88_fu_4876_p2 = (a_addr99_cast_reg_6582 + tmp_182_trn_cast_reg_6254);
assign a_addr89_fu_4764_p2 = (a_addr98_cast_fu_4760_p1 + tmp_176_trn_cast_reg_6191);
assign a_addr8_cast_fu_2617_p1 = {{1{1'b0}}, {a_addr8_fu_2611_p2}};
assign a_addr8_fu_2611_p2 = tmp_20_trn_cast_fu_2607_p1 << ap_const_lv13_6;
assign a_addr90_fu_4774_p2 = (a_addr98_cast_reg_6502 + tmp_178_trn_cast_reg_6212);
assign a_addr91_fu_4783_p2 = (a_addr98_cast_reg_6502 + tmp_180_trn_cast_reg_6233);
assign a_addr92_fu_4867_p2 = (a_addr99_cast_reg_6582 + tmp_180_trn_cast_reg_6233);
assign a_addr93_fu_4792_p2 = (a_addr98_cast_reg_6502 + tmp_182_trn_cast_reg_6254);
assign a_addr94_fu_4801_p2 = (a_addr98_cast_reg_6502 + tmp_184_trn_cast_reg_6275);
assign a_addr95_fu_4810_p2 = (a_addr98_cast_reg_6502 + tmp_186_trn_cast_reg_6296);
assign a_addr96_fu_4857_p2 = (a_addr99_cast_fu_4843_p1 + tmp_178_trn_cast_reg_6212);
assign a_addr97_fu_4819_p2 = (a_addr98_cast_reg_6502 + tmp_188_trn_cast_reg_6317);
assign a_addr98_cast_fu_4760_p1 = {{1{1'b0}}, {a_addr87_fu_4754_p2}};
assign a_addr98_fu_4837_p2 = tmp_166_trn_cast_fu_4833_p1 << ap_const_lv13_6;
assign a_addr99_cast_fu_4843_p1 = {{1{1'b0}}, {a_addr98_fu_4837_p2}};
assign a_addr99_fu_4847_p2 = (a_addr99_cast_fu_4843_p1 + tmp_176_trn_cast_reg_6191);
assign a_addr9_fu_2621_p2 = (a_addr8_cast_fu_2617_p1 + tmp_6_trn_cast_reg_5226);
assign a_addr_fu_2393_p2 = tmp_3_trn_cast_fu_2389_p1 << ap_const_lv13_6;
assign b_addr10_cast_fu_3083_p1 = {{1{1'b0}}, {b_addr10_fu_3077_p2}};
assign b_addr10_fu_3077_p2 = tmp_51_trn_cast_fu_3069_p1 << ap_const_lv13_6;
assign b_addr11_fu_3087_p1 = {{7{j_1_mid2_fu_3057_p3[6]}}, {j_1_mid2_fu_3057_p3}};
assign b_addr11_fu_3087_p2 = (b_addr10_cast_fu_3083_p1 + b_addr11_fu_3087_p1);
assign b_addr12_cast_fu_3172_p1 = {{1{1'b0}}, {b_addr12_fu_3166_p2}};
assign b_addr12_fu_3166_p2 = tmp_55_trn_cast_fu_3162_p1 << ap_const_lv13_6;
assign b_addr13_fu_3176_p2 = (b_addr12_cast_fu_3172_p1 + tmp_44_trn_cast_reg_5477);
assign b_addr14_cast_fu_3238_p1 = {{1{1'b0}}, {b_addr14_fu_3232_p2}};
assign b_addr14_fu_3232_p2 = tmp_59_trn_cast_fu_3228_p1 << ap_const_lv13_6;
assign b_addr15_fu_3242_p2 = (b_addr14_cast_fu_3238_p1 + tmp_44_trn_cast_reg_5477);
assign b_addr16_cast_fu_3352_p1 = {{1{1'b0}}, {b_addr16_fu_3346_p2}};
assign b_addr16_fu_3346_p2 = tmp_63_trn_cast_fu_3342_p1 << ap_const_lv13_6;
assign b_addr17_fu_3356_p2 = (b_addr16_cast_fu_3352_p1 + tmp_44_trn_cast_reg_5477);
assign b_addr18_cast_fu_3406_p1 = {{1{1'b0}}, {b_addr18_fu_3400_p2}};
assign b_addr18_fu_3400_p2 = tmp_67_trn_cast_fu_3396_p1 << ap_const_lv13_6;
assign b_addr19_fu_3410_p2 = (b_addr18_cast_fu_3406_p1 + tmp_44_trn_cast_reg_5477);
assign b_addr1_fu_2519_p5 = {{b_addr_fu_2514_p2}, {tmp_8_trn_cast_fu_2500_p1[32'd5 : 32'd0]}};
assign b_addr20_cast_fu_3459_p1 = {{1{1'b0}}, {b_addr20_fu_3453_p2}};
assign b_addr20_fu_3453_p2 = tmp_71_trn_cast_fu_3449_p1 << ap_const_lv13_6;
assign b_addr21_fu_3463_p2 = (b_addr20_cast_fu_3459_p1 + tmp_44_trn_cast_reg_5477);
assign b_addr22_cast_fu_3513_p1 = {{1{1'b0}}, {b_addr22_fu_3507_p2}};
assign b_addr22_fu_3507_p2 = tmp_75_trn_cast_fu_3503_p1 << ap_const_lv13_6;
assign b_addr24_cast_fu_3562_p1 = {{1{1'b0}}, {b_addr24_fu_3556_p2}};
assign b_addr24_fu_3556_p2 = tmp_79_trn_cast_fu_3552_p1 << ap_const_lv13_6;
assign b_addr26_cast_fu_3731_p1 = {{1{1'b0}}, {b_addr26_fu_3725_p2}};
assign b_addr26_fu_3725_p2 = tmp_85_trn_cast_fu_3721_p1 << ap_const_lv12_6;
assign b_addr27_fu_3735_p2 = (b_addr26_cast_fu_3731_p1 + tmp_90_trn_cast1_fu_3718_p1);
assign b_addr28_fu_3769_p2 = (b_addr26_cast_fu_3731_p1 + tmp_94_trn_cast1_fu_3751_p1);
assign b_addr29_fu_3802_p2 = (b_addr26_cast_reg_5755 + tmp_98_trn_cast1_fu_3799_p1);
assign b_addr2_fu_2579_p2 = (a_addr101_fu_2565_p1 | tmp_8_trn_cast2_fu_2569_p4);
assign b_addr30_fu_3835_p2 = (b_addr26_cast_reg_5755 + tmp_102_trn_cast1_fu_3817_p1);
assign b_addr31_fu_3867_p2 = (b_addr26_cast_reg_5755 + tmp_106_trn_cast1_fu_3864_p1);
assign b_addr32_fu_3900_p2 = (b_addr26_cast_reg_5755 + tmp_110_trn_cast1_fu_3882_p1);
assign b_addr33_fu_3919_p2 = (b_addr26_cast_reg_5755 + tmp_114_trn_cast1_fu_3915_p1);
assign b_addr34_fu_3938_p2 = (b_addr26_cast_reg_5755 + tmp_118_trn_cast1_fu_3934_p1);
assign b_addr35_fu_3994_p2 = (tmp_86_trn_cast_fu_3990_p1 + ap_const_lv13_FC0);
assign b_addr36_cast_fu_4063_p1 = {{1{b_addr36_fu_4057_p2[12]}}, {b_addr36_fu_4057_p2}};
assign b_addr36_fu_4057_p2 = tmp_122_trn_cast_fu_4049_p1 << ap_const_lv13_6;
assign b_addr37_fu_4067_p0 = {{1{b_addr36_fu_4057_p2[12]}}, {b_addr36_fu_4057_p2}};
assign b_addr37_fu_4067_p2 = (b_addr37_fu_4067_p0 + tmp_126_trn_cast_fu_4053_p1);
assign b_addr38_fu_4138_p2 = (b_addr36_cast_reg_5956 + tmp_130_trn_cast_fu_4134_p1);
assign b_addr39_fu_4168_p2 = (b_addr36_cast_reg_5956 + tmp_134_trn_cast_fu_4164_p1);
assign b_addr3_fu_2585_p5 = {{b_addr2_fu_2579_p2}, {tmp_8_trn_cast_fu_2500_p1[32'd5 : 32'd0]}};
assign b_addr40_fu_4204_p2 = (b_addr36_cast_reg_5956 + tmp_138_trn_cast_fu_4200_p1);
assign b_addr41_fu_4233_p2 = (b_addr36_cast_reg_5956 + tmp_142_trn_cast_fu_4229_p1);
assign b_addr42_fu_4269_p2 = (b_addr36_cast_reg_5956 + tmp_146_trn_cast_fu_4265_p1);
assign b_addr43_fu_4335_p2 = (ap_reg_ppstg_b_addr36_cast_reg_5956_pp7_it1 + tmp_150_trn_cast_fu_4332_p1);
assign b_addr44_fu_4348_p2 = (ap_reg_ppstg_b_addr36_cast_reg_5956_pp7_it1 + tmp_154_trn_cast_fu_4345_p1);
assign b_addr45_fu_2856_p2 = (a_addr105_fu_2852_p1 | tmp_8_trn_cast6_reg_5312);
assign b_addr46_fu_2861_p5 = {{b_addr45_fu_2856_p2}, {tmp_8_trn_cast_reg_5257[32'd5 : 32'd0]}};
assign b_addr47_fu_2905_p2 = (a_addr106_fu_2901_p1 | tmp_8_trn_cast7_reg_5317);
assign b_addr48_fu_2910_p5 = {{b_addr47_fu_2905_p2}, {tmp_8_trn_cast_reg_5257[32'd5 : 32'd0]}};
assign b_addr49_fu_2954_p2 = (a_addr107_fu_2950_p1 | tmp_8_trn_cast8_reg_5322);
assign b_addr4_fu_2645_p2 = (a_addr102_fu_2631_p1 | tmp_8_trn_cast3_fu_2635_p4);
assign b_addr50_fu_2959_p5 = {{b_addr49_fu_2954_p2}, {tmp_8_trn_cast_reg_5257[32'd5 : 32'd0]}};
assign b_addr51_fu_3004_p1 = tmp_9_trn_cast_fu_3000_p1[6:0];
assign b_addr52_fu_3008_p5 = {{b_addr51_fu_3004_p1}, {ap_const_lv13_3F[32'd5 : 32'd0]}};
assign b_addr54_fu_3186_p1 = tmp_55_trn_cast_fu_3162_p1[6:0];
assign b_addr55_fu_3252_p1 = tmp_59_trn_cast_fu_3228_p1[6:0];
assign b_addr56_fu_3366_p1 = tmp_63_trn_cast_fu_3342_p1[6:0];
assign b_addr57_fu_3420_p1 = tmp_67_trn_cast_fu_3396_p1[6:0];
assign b_addr58_fu_3473_p1 = tmp_71_trn_cast_fu_3449_p1[6:0];
assign b_addr59_fu_3522_p1 = tmp_75_trn_cast_fu_3503_p1[6:0];
assign b_addr5_fu_2701_p5 = {{b_addr4_reg_5297}, {tmp_8_trn_cast_reg_5257[32'd5 : 32'd0]}};
assign b_addr60_fu_3571_p1 = tmp_79_trn_cast_fu_3552_p1[6:0];
assign b_addr6_fu_2749_p2 = (a_addr103_fu_2745_p1 | tmp_8_trn_cast4_reg_5302);
assign b_addr7_fu_2754_p5 = {{b_addr6_fu_2749_p2}, {tmp_8_trn_cast_reg_5257[32'd5 : 32'd0]}};
assign b_addr8_fu_2803_p2 = (a_addr104_fu_2799_p1 | tmp_8_trn_cast5_reg_5307);
assign b_addr9_fu_2808_p5 = {{b_addr8_reg_5357}, {tmp_8_trn_cast_reg_5257[32'd5 : 32'd0]}};
assign b_addr_fu_2514_p2 = (a_addr100_reg_5247 | tmp_8_trn_cast1_fu_2504_p4);
assign exitcond10_fu_3978_p2 = (j_4_phi_fu_2055_p4 == ap_const_lv7_40? 1'b1: 1'b0);
assign exitcond11_fu_3638_p2 = (indvar9_phi_fu_2033_p4 == ap_const_lv4_8? 1'b1: 1'b0);
assign exitcond12_fu_4005_p2 = (indvar_flatten3_phi_fu_2066_p4 == ap_const_lv9_1F8? 1'b1: 1'b0);
assign exitcond13_fu_4017_p2 = (indvar4_phi_fu_2088_p4 == ap_const_lv4_8? 1'b1: 1'b0);
assign exitcond1_fu_2377_p2 = (i_phi_fu_1890_p4 == ap_const_lv7_40? 1'b1: 1'b0);
assign exitcond2_fu_4369_p2 = (indvar_phi_fu_2138_p6 == ap_const_lv4_8? 1'b1: 1'b0);
assign exitcond3_fu_2404_p2 = (indvar_flatten_phi_fu_1901_p4 == ap_const_lv9_1F8? 1'b1: 1'b0);
assign exitcond4_fu_2988_p2 = (i_2_phi_fu_1945_p4 == ap_const_lv7_40? 1'b1: 1'b0);
assign exitcond5_fu_2416_p2 = (indvar3_phi_fu_1923_p4 == ap_const_lv4_8? 1'b1: 1'b0);
assign exitcond6_fu_3025_p2 = (indvar_flatten1_phi_fu_1956_p4 == ap_const_lv9_1F8? 1'b1: 1'b0);
assign exitcond7_fu_3609_p2 = (j_2_phi_fu_2000_p4 == ap_const_lv7_40? 1'b1: 1'b0);
assign exitcond8_fu_3037_p2 = (indvar6_phi_fu_1978_p4 == ap_const_lv4_8? 1'b1: 1'b0);
assign exitcond9_fu_3626_p2 = (indvar_flatten2_phi_fu_2011_p4 == ap_const_lv9_1F8? 1'b1: 1'b0);
assign exitcond_fu_4357_p2 = (indvar_flatten4_phi_fu_2110_p6 == ap_const_lv7_40? 1'b1: 1'b0);
assign grp_fu_2163_ce = ap_const_logic_1;
assign grp_fu_2167_ce = ap_const_logic_1;
assign i_1_mid2_fu_2422_p3 = ((exitcond5_fu_2416_p2)? ap_const_lv7_0: i_1_phi_fu_1934_p4);
assign i_3_mid2_fu_3043_p3 = ((exitcond8_fu_3037_p2)? ap_const_lv7_0: i_3_phi_fu_1989_p4);
assign i_4_mid2_fu_3658_p3 = ((exitcond11_fu_3638_p2)? tmp_89_dup_fu_3652_p2: i_4_phi_fu_2022_p4);
assign i_5_mid2_fu_4037_p3 = ((exitcond13_fu_4017_p2)? tmp_125_dup_fu_4031_p2: i_5_phi_fu_2077_p4);
assign i_6_mid2_fu_4389_p3 = ((exitcond2_fu_4369_p2)? tmp_173_dup_fu_4383_p2: i_6_phi_fu_2124_p6);
assign indvar3_op_fu_2481_p2 = (indvar3_phi_fu_1923_p4 + ap_const_lv4_1);
assign indvar4_op_fu_4078_p2 = (indvar4_phi_fu_2088_p4 + ap_const_lv4_1);
assign indvar6_op_fu_3102_p2 = (indvar6_phi_fu_1978_p4 + ap_const_lv4_1);
assign indvar9_op_fu_3699_p2 = (indvar9_phi_fu_2033_p4 + ap_const_lv4_1);
assign indvar_op_fu_4426_p2 = (indvar_phi_fu_2138_p6 + ap_const_lv4_1);
assign j_1_mid2_fu_3057_p3 = ((exitcond8_fu_3037_p2)? tmp_50_dup_fu_3051_p2: j_1_phi_fu_1967_p4);
assign j_3_mid2_fu_3644_p3 = ((exitcond11_fu_3638_p2)? ap_const_lv7_0: j_3_phi_fu_2044_p4);
assign j_5_mid2_fu_4023_p3 = ((exitcond13_fu_4017_p2)? ap_const_lv7_0: j_5_phi_fu_2099_p4);
assign j_6_mid2_fu_4375_p3 = ((exitcond2_fu_4369_p2)? ap_const_lv7_0: j_6_phi_fu_2152_p6);
assign j_mid2_fu_2436_p3 = ((exitcond5_fu_2416_p2)? tmp_11_dup_fu_2430_p2: j_phi_fu_1912_p4);
assign or_cond_fu_2365_p2 = (tmp_fu_2353_p2 & tmp_1_fu_2359_p2);
assign tmp_101_fu_3812_p2 = (j_3_mid2_reg_5706 | ap_const_lv7_3);
assign tmp_102_fu_3493_p1 = {{51{1'b0}}, {a_addr119_fu_3482_p5}};
assign tmp_102_trn_cast1_fu_3817_p1 = {{6{1'b0}}, {tmp_101_fu_3812_p2}};
assign tmp_102_trn_cast_fu_3821_p1 = {{7{1'b0}}, {tmp_101_fu_3812_p2}};
assign tmp_105_fu_3845_p2 = (j_3_mid2_reg_5706 | ap_const_lv7_4);
assign tmp_106_fu_3601_p1 = {{50{b_addr23_reg_5633[13]}}, {b_addr23_reg_5633}};
assign tmp_106_trn_cast1_fu_3864_p1 = {{6{1'b0}}, {tmp_105_reg_5820}};
assign tmp_106_trn_cast_fu_3850_p1 = {{7{1'b0}}, {tmp_105_fu_3845_p2}};
assign tmp_109_fu_3877_p2 = (j_3_mid2_reg_5706 | ap_const_lv7_5);
assign tmp_110_fu_3542_p1 = {{51{1'b0}}, {a_addr121_fu_3531_p5}};
assign tmp_110_trn_cast1_fu_3882_p1 = {{6{1'b0}}, {tmp_109_fu_3877_p2}};
assign tmp_110_trn_cast_fu_3886_p1 = {{7{1'b0}}, {tmp_109_fu_3877_p2}};
assign tmp_113_fu_3910_p2 = (j_3_mid2_reg_5706 | ap_const_lv7_6);
assign tmp_114_fu_3605_p1 = {{50{b_addr25_reg_5643[13]}}, {b_addr25_reg_5643}};
assign tmp_114_trn_cast1_fu_3915_p1 = {{6{1'b0}}, {tmp_113_fu_3910_p2}};
assign tmp_114_trn_cast_fu_3953_p1 = {{7{1'b0}}, {tmp_113_reg_5855}};
assign tmp_117_fu_3929_p2 = (j_3_mid2_reg_5706 | ap_const_lv7_7);
assign tmp_118_fu_3591_p1 = {{51{1'b0}}, {a_addr123_fu_3580_p5}};
assign tmp_118_trn_cast1_fu_3934_p1 = {{6{1'b0}}, {tmp_117_fu_3929_p2}};
assign tmp_118_trn_cast_fu_3966_p1 = {{7{1'b0}}, {tmp_117_reg_5865}};
assign tmp_11_dup_fu_2430_p2 = (j_phi_fu_1912_p4 + ap_const_lv7_1);
assign tmp_11_fu_2531_p1 = {{51{1'b0}}, {b_addr1_fu_2519_p5}};
assign tmp_122_fu_3621_p1 = {{57{1'b0}}, {j_2_phi_fu_2000_p4}};
assign tmp_122_trn_cast_fu_4049_p1 = {{6{1'b0}}, {i_5_mid2_fu_4037_p3}};
assign tmp_123_fu_4092_p2 = (i_5_cast_reg_5951 + ap_const_lv6_1);
assign tmp_124_trn_cast_fu_4100_p1 = {{6{1'b0}}, {tmp_123_fu_4092_p2}};
assign tmp_125_dup_fu_4031_p2 = (i_5_phi_fu_2077_p4 + ap_const_lv7_7F);
assign tmp_125_fu_3694_p1 = {{50{1'b0}}, {a_addr39_fu_3688_p2}};
assign tmp_126_fu_3741_p1 = {{51{1'b0}}, {b_addr27_fu_3735_p2}};
assign tmp_126_trn_cast1_fu_4097_p1 = {{6{1'b0}}, {j_5_mid2_reg_5933}};
assign tmp_126_trn_cast_fu_4053_p1 = {{7{1'b0}}, {j_5_mid2_fu_4023_p3}};
assign tmp_129_fu_4125_p2 = (j_5_mid2_reg_5933 | ap_const_lv7_1);
assign tmp_12_trn_cast_fu_2448_p1 = {{6{1'b0}}, {i_1_mid2_fu_2422_p3}};
assign tmp_130_fu_3764_p1 = {{50{1'b0}}, {a_addr40_fu_3759_p2}};
assign tmp_130_trn_cast1_fu_4130_p1 = {{6{1'b0}}, {tmp_129_fu_4125_p2}};
assign tmp_130_trn_cast_fu_4134_p1 = {{7{1'b0}}, {tmp_129_fu_4125_p2}};
assign tmp_133_fu_4159_p2 = (j_5_mid2_reg_5933 | ap_const_lv7_2);
assign tmp_134_fu_3775_p1 = {{51{1'b0}}, {b_addr28_fu_3769_p2}};
assign tmp_134_trn_cast1_fu_4178_p1 = {{6{1'b0}}, {tmp_133_reg_6012}};
assign tmp_134_trn_cast_fu_4164_p1 = {{7{1'b0}}, {tmp_133_fu_4159_p2}};
assign tmp_137_fu_4191_p2 = (j_5_mid2_reg_5933 | ap_const_lv7_3);
assign tmp_138_fu_3794_p1 = {{50{1'b0}}, {a_addr41_fu_3789_p2}};
assign tmp_138_trn_cast1_fu_4196_p1 = {{6{1'b0}}, {tmp_137_fu_4191_p2}};
assign tmp_138_trn_cast_fu_4200_p1 = {{7{1'b0}}, {tmp_137_fu_4191_p2}};
assign tmp_141_fu_4224_p2 = (j_5_mid2_reg_5933 | ap_const_lv7_4);
assign tmp_142_fu_3807_p1 = {{51{1'b0}}, {b_addr29_fu_3802_p2}};
assign tmp_142_trn_cast1_fu_4243_p1 = {{6{1'b0}}, {tmp_141_reg_6047}};
assign tmp_142_trn_cast_fu_4229_p1 = {{7{1'b0}}, {tmp_141_fu_4224_p2}};
assign tmp_145_fu_4256_p2 = (j_5_mid2_reg_5933 | ap_const_lv7_5);
assign tmp_146_fu_3830_p1 = {{50{1'b0}}, {a_addr43_fu_3825_p2}};
assign tmp_146_trn_cast1_fu_4261_p1 = {{6{1'b0}}, {tmp_145_fu_4256_p2}};
assign tmp_146_trn_cast_fu_4265_p1 = {{7{1'b0}}, {tmp_145_fu_4256_p2}};
assign tmp_149_fu_4289_p2 = (j_5_mid2_reg_5933 | ap_const_lv7_6);
assign tmp_14_fu_2536_p2 = (i_1_mid2_reg_5204 | ap_const_lv7_1);
assign tmp_150_fu_3840_p1 = {{51{1'b0}}, {b_addr30_fu_3835_p2}};
assign tmp_150_trn_cast1_fu_4294_p1 = {{6{1'b0}}, {tmp_149_fu_4289_p2}};
assign tmp_150_trn_cast_fu_4332_p1 = {{7{1'b0}}, {tmp_149_reg_6082}};
assign tmp_153_fu_4308_p2 = (j_5_mid2_reg_5933 | ap_const_lv7_7);
assign tmp_154_fu_3859_p1 = {{50{1'b0}}, {a_addr44_fu_3854_p2}};
assign tmp_154_trn_cast1_fu_4313_p1 = {{6{1'b0}}, {tmp_153_fu_4308_p2}};
assign tmp_154_trn_cast_fu_4345_p1 = {{7{1'b0}}, {tmp_153_reg_6092}};
assign tmp_158_fu_3872_p1 = {{51{1'b0}}, {b_addr31_fu_3867_p2}};
assign tmp_158_trn_cast_fu_4397_p1 = {{6{1'b0}}, {i_6_mid2_fu_4389_p3}};
assign tmp_159_fu_4554_p2 = (i_6_mid2_reg_6153 | ap_const_lv7_1);
assign tmp_15_fu_2560_p1 = {{50{1'b0}}, {a_addr6_fu_2555_p2}};
assign tmp_160_fu_3895_p1 = {{50{1'b0}}, {a_addr47_fu_3890_p2}};
assign tmp_160_trn_cast_fu_4578_p1 = {{6{1'b0}}, {tmp_159_fu_4554_p2}};
assign tmp_161_fu_4661_p2 = (i_6_mid2_reg_6153 | ap_const_lv7_2);
assign tmp_162_fu_3905_p1 = {{51{1'b0}}, {b_addr32_fu_3900_p2}};
assign tmp_162_trn_cast_fu_4666_p1 = {{6{1'b0}}, {tmp_161_fu_4661_p2}};
assign tmp_163_fu_4736_p2 = (i_6_mid2_reg_6153 | ap_const_lv7_3);
assign tmp_164_fu_3961_p1 = {{50{1'b0}}, {a_addr48_fu_3956_p2}};
assign tmp_164_trn_cast_fu_4750_p1 = {{6{1'b0}}, {tmp_163_fu_4736_p2}};
assign tmp_165_fu_4828_p2 = (i_6_mid2_reg_6153 | ap_const_lv7_4);
assign tmp_166_fu_3924_p1 = {{51{1'b0}}, {b_addr33_fu_3919_p2}};
assign tmp_166_trn_cast_fu_4833_p1 = {{6{1'b0}}, {tmp_165_fu_4828_p2}};
assign tmp_167_fu_4903_p2 = (i_6_mid2_reg_6153 | ap_const_lv7_5);
assign tmp_168_fu_3974_p1 = {{50{1'b0}}, {a_addr50_reg_5890}};
assign tmp_168_trn_cast_fu_4917_p1 = {{6{1'b0}}, {tmp_167_fu_4903_p2}};
assign tmp_169_fu_4995_p2 = (i_6_mid2_reg_6153 | ap_const_lv7_6);
assign tmp_16_fu_2597_p1 = {{51{1'b0}}, {b_addr3_fu_2585_p5}};
assign tmp_16_trn_cast_fu_2541_p1 = {{6{1'b0}}, {tmp_14_fu_2536_p2}};
assign tmp_170_fu_3943_p1 = {{51{1'b0}}, {b_addr34_fu_3938_p2}};
assign tmp_170_trn_cast_fu_5000_p1 = {{6{1'b0}}, {tmp_169_fu_4995_p2}};
assign tmp_171_fu_5052_p2 = (i_6_mid2_reg_6153 | ap_const_lv7_7);
assign tmp_172_fu_4000_p1 = {{51{1'b0}}, {b_addr35_fu_3994_p2}};
assign tmp_172_trn_cast_fu_5079_p1 = {{6{1'b0}}, {tmp_171_fu_5052_p2}};
assign tmp_173_dup_fu_4383_p2 = (i_6_phi_fu_2124_p6 + ap_const_lv7_8);
assign tmp_174_fu_4073_p1 = {{50{b_addr37_fu_4067_p2[13]}}, {b_addr37_fu_4067_p2}};
assign tmp_174_trn_cast_fu_4401_p1 = {{7{1'b0}}, {j_6_mid2_fu_4375_p3}};
assign tmp_175_fu_4440_p2 = (j_6_mid2_reg_6141 | ap_const_lv7_1);
assign tmp_176_fu_4120_p1 = {{51{1'b0}}, {a_addr52_fu_4114_p2}};
assign tmp_176_trn_cast_fu_4445_p1 = {{7{1'b0}}, {tmp_175_fu_4440_p2}};
assign tmp_177_fu_4459_p2 = (j_6_mid2_reg_6141 | ap_const_lv7_2);
assign tmp_178_fu_4143_p1 = {{50{b_addr38_fu_4138_p2[13]}}, {b_addr38_fu_4138_p2}};
assign tmp_178_trn_cast_fu_4464_p1 = {{7{1'b0}}, {tmp_177_fu_4459_p2}};
assign tmp_179_fu_4478_p2 = (j_6_mid2_reg_6141 | ap_const_lv7_3);
assign tmp_180_fu_4154_p1 = {{51{1'b0}}, {a_addr54_fu_4148_p2}};
assign tmp_180_trn_cast_fu_4483_p1 = {{7{1'b0}}, {tmp_179_fu_4478_p2}};
assign tmp_181_fu_4497_p2 = (j_6_mid2_reg_6141 | ap_const_lv7_4);
assign tmp_182_fu_4173_p1 = {{50{b_addr39_fu_4168_p2[13]}}, {b_addr39_fu_4168_p2}};
assign tmp_182_trn_cast_fu_4502_p1 = {{7{1'b0}}, {tmp_181_fu_4497_p2}};
assign tmp_183_fu_4516_p2 = (j_6_mid2_reg_6141 | ap_const_lv7_5);
assign tmp_184_fu_4186_p1 = {{51{1'b0}}, {a_addr55_fu_4181_p2}};
assign tmp_184_trn_cast_fu_4521_p1 = {{7{1'b0}}, {tmp_183_fu_4516_p2}};
assign tmp_185_fu_4535_p2 = (j_6_mid2_reg_6141 | ap_const_lv7_6);
assign tmp_186_fu_4209_p1 = {{50{b_addr40_fu_4204_p2[13]}}, {b_addr40_fu_4204_p2}};
assign tmp_186_trn_cast_fu_4540_p1 = {{7{1'b0}}, {tmp_185_fu_4535_p2}};
assign tmp_187_fu_4559_p2 = (j_6_mid2_reg_6141 | ap_const_lv7_7);
assign tmp_188_fu_4219_p1 = {{51{1'b0}}, {a_addr56_fu_4214_p2}};
assign tmp_188_trn_cast_fu_4564_p1 = {{7{1'b0}}, {tmp_187_fu_4559_p2}};
assign tmp_190_fu_4238_p1 = {{50{b_addr41_fu_4233_p2[13]}}, {b_addr41_fu_4233_p2}};
assign tmp_191_fu_4251_p1 = {{51{1'b0}}, {a_addr58_fu_4246_p2}};
assign tmp_192_fu_4274_p1 = {{50{b_addr42_fu_4269_p2[13]}}, {b_addr42_fu_4269_p2}};
assign tmp_193_fu_4284_p1 = {{51{1'b0}}, {a_addr59_fu_4279_p2}};
assign tmp_194_fu_4340_p1 = {{50{b_addr43_fu_4335_p2[13]}}, {b_addr43_fu_4335_p2}};
assign tmp_196_fu_4303_p1 = {{51{1'b0}}, {a_addr60_fu_4298_p2}};
assign tmp_197_fu_4353_p1 = {{50{b_addr44_reg_6117[13]}}, {b_addr44_reg_6117}};
assign tmp_198_fu_4322_p1 = {{51{1'b0}}, {a_addr62_fu_4317_p2}};
assign tmp_199_fu_4421_p1 = {{50{1'b0}}, {a_addr28_fu_4415_p2}};
assign tmp_19_fu_2602_p2 = (i_1_mid2_reg_5204 | ap_const_lv7_2);
assign tmp_1_fu_2359_p2 = (counter != ap_const_lv7_0? 1'b1: 1'b0);
assign tmp_200_fu_4454_p1 = {{50{1'b0}}, {a_addr29_fu_4449_p2}};
assign tmp_201_fu_4473_p1 = {{50{1'b0}}, {a_addr31_fu_4468_p2}};
assign tmp_202_fu_4492_p1 = {{50{1'b0}}, {a_addr32_fu_4487_p2}};
assign tmp_203_fu_4511_p1 = {{50{1'b0}}, {a_addr33_fu_4506_p2}};
assign tmp_204_fu_4530_p1 = {{50{1'b0}}, {a_addr35_fu_4525_p2}};
assign tmp_205_fu_4549_p1 = {{50{1'b0}}, {a_addr36_fu_4544_p2}};
assign tmp_206_fu_4573_p1 = {{50{1'b0}}, {a_addr63_fu_4568_p2}};
assign tmp_207_fu_4597_p1 = {{50{1'b0}}, {a_addr66_fu_4592_p2}};
assign tmp_208_fu_4611_p1 = {{50{1'b0}}, {a_addr67_fu_4607_p2}};
assign tmp_209_fu_4620_p1 = {{50{1'b0}}, {a_addr68_fu_4616_p2}};
assign tmp_20_fu_2626_p1 = {{50{1'b0}}, {a_addr9_fu_2621_p2}};
assign tmp_20_trn_cast_fu_2607_p1 = {{6{1'b0}}, {tmp_19_fu_2602_p2}};
assign tmp_210_fu_4629_p1 = {{50{1'b0}}, {a_addr70_fu_4625_p2}};
assign tmp_211_fu_4638_p1 = {{50{1'b0}}, {a_addr71_fu_4634_p2}};
assign tmp_212_fu_4647_p1 = {{50{1'b0}}, {a_addr74_fu_4643_p2}};
assign tmp_213_fu_4656_p1 = {{50{1'b0}}, {a_addr75_fu_4652_p2}};
assign tmp_214_fu_4685_p1 = {{50{1'b0}}, {a_addr78_fu_4680_p2}};
assign tmp_215_fu_4695_p1 = {{50{1'b0}}, {a_addr79_fu_4690_p2}};
assign tmp_216_fu_4704_p1 = {{50{1'b0}}, {a_addr81_fu_4700_p2}};
assign tmp_217_fu_4713_p1 = {{50{1'b0}}, {a_addr82_fu_4709_p2}};
assign tmp_218_fu_4722_p1 = {{50{1'b0}}, {a_addr83_fu_4718_p2}};
assign tmp_219_fu_4731_p1 = {{50{1'b0}}, {a_addr85_fu_4727_p2}};
assign tmp_220_fu_4745_p1 = {{50{1'b0}}, {a_addr86_fu_4741_p2}};
assign tmp_221_fu_4769_p1 = {{50{1'b0}}, {a_addr89_fu_4764_p2}};
assign tmp_222_fu_4778_p1 = {{50{1'b0}}, {a_addr90_fu_4774_p2}};
assign tmp_223_fu_4787_p1 = {{50{1'b0}}, {a_addr91_fu_4783_p2}};
assign tmp_224_fu_4796_p1 = {{50{1'b0}}, {a_addr93_fu_4792_p2}};
assign tmp_225_fu_4805_p1 = {{50{1'b0}}, {a_addr94_fu_4801_p2}};
assign tmp_226_fu_4814_p1 = {{50{1'b0}}, {a_addr95_fu_4810_p2}};
assign tmp_227_fu_4823_p1 = {{50{1'b0}}, {a_addr97_fu_4819_p2}};
assign tmp_228_fu_4852_p1 = {{50{1'b0}}, {a_addr99_fu_4847_p2}};
assign tmp_229_fu_4862_p1 = {{50{1'b0}}, {a_addr96_fu_4857_p2}};
assign tmp_230_fu_4871_p1 = {{50{1'b0}}, {a_addr92_fu_4867_p2}};
assign tmp_231_fu_4880_p1 = {{50{1'b0}}, {a_addr88_fu_4876_p2}};
assign tmp_232_fu_4889_p1 = {{50{1'b0}}, {a_addr84_fu_4885_p2}};
assign tmp_233_fu_4898_p1 = {{50{1'b0}}, {a_addr80_fu_4894_p2}};
assign tmp_234_fu_4912_p1 = {{50{1'b0}}, {a_addr76_fu_4908_p2}};
assign tmp_235_fu_4936_p1 = {{50{1'b0}}, {a_addr73_fu_4931_p2}};
assign tmp_236_fu_4945_p1 = {{50{1'b0}}, {a_addr69_fu_4941_p2}};
assign tmp_237_fu_4954_p1 = {{50{1'b0}}, {a_addr65_fu_4950_p2}};
assign tmp_238_fu_4963_p1 = {{50{1'b0}}, {a_addr61_fu_4959_p2}};
assign tmp_239_fu_4972_p1 = {{50{1'b0}}, {a_addr57_fu_4968_p2}};
assign tmp_23_fu_2716_p2 = (i_1_mid2_reg_5204 | ap_const_lv7_3);
assign tmp_240_fu_4981_p1 = {{50{1'b0}}, {a_addr53_fu_4977_p2}};
assign tmp_241_fu_4990_p1 = {{50{1'b0}}, {a_addr49_fu_4986_p2}};
assign tmp_242_fu_5019_p1 = {{50{1'b0}}, {a_addr46_fu_5014_p2}};
assign tmp_243_fu_5029_p1 = {{50{1'b0}}, {a_addr42_fu_5024_p2}};
assign tmp_244_fu_5038_p1 = {{50{1'b0}}, {a_addr38_fu_5034_p2}};
assign tmp_245_fu_5047_p1 = {{50{1'b0}}, {a_addr34_fu_5043_p2}};
assign tmp_246_fu_5061_p1 = {{50{1'b0}}, {a_addr30_fu_5057_p2}};
assign tmp_247_fu_5070_p1 = {{50{1'b0}}, {a_addr26_fu_5066_p2}};
assign tmp_248_fu_5128_p1 = {{50{1'b0}}, {a_addr22_reg_6810}};
assign tmp_249_fu_5132_p1 = {{50{1'b0}}, {a_addr19_reg_6815}};
assign tmp_24_fu_2711_p1 = {{51{1'b0}}, {b_addr5_fu_2701_p5}};
assign tmp_24_trn_cast_fu_2721_p1 = {{6{1'b0}}, {tmp_23_fu_2716_p2}};
assign tmp_250_fu_5136_p1 = {{50{1'b0}}, {a_addr16_reg_6820}};
assign tmp_251_fu_5140_p1 = {{50{1'b0}}, {a_addr13_reg_6825}};
assign tmp_252_fu_5144_p1 = {{50{1'b0}}, {a_addr10_reg_6830}};
assign tmp_253_fu_5148_p1 = {{50{1'b0}}, {a_addr7_reg_6835}};
assign tmp_254_fu_5152_p1 = {{50{1'b0}}, {a_addr4_reg_6840}};
assign tmp_255_fu_5156_p1 = {{50{1'b0}}, {a_addr1_reg_6845}};
assign tmp_27_fu_2770_p2 = (i_1_mid2_reg_5204 | ap_const_lv7_4);
assign tmp_28_fu_2740_p1 = {{50{1'b0}}, {a_addr12_fu_2735_p2}};
assign tmp_28_trn_cast_fu_2775_p1 = {{6{1'b0}}, {tmp_27_fu_2770_p2}};
assign tmp_2_fu_2371_p2 = (tag == ap_const_lv2_0? 1'b1: 1'b0);
assign tmp_31_fu_2823_p2 = (i_1_mid2_reg_5204 | ap_const_lv7_5);
assign tmp_32_fu_2765_p1 = {{51{1'b0}}, {b_addr7_fu_2754_p5}};
assign tmp_32_trn_cast_fu_2828_p1 = {{6{1'b0}}, {tmp_31_fu_2823_p2}};
assign tmp_35_fu_2877_p2 = (i_1_mid2_reg_5204 | ap_const_lv7_6);
assign tmp_36_fu_2794_p1 = {{50{1'b0}}, {a_addr15_fu_2789_p2}};
assign tmp_36_trn_cast_fu_2882_p1 = {{6{1'b0}}, {tmp_35_fu_2877_p2}};
assign tmp_39_fu_2926_p2 = (i_1_mid2_reg_5204 | ap_const_lv7_7);
assign tmp_3_trn_cast_fu_2389_p1 = {{6{1'b0}}, {i_phi_fu_1890_p4}};
assign tmp_40_fu_2818_p1 = {{51{1'b0}}, {b_addr9_fu_2808_p5}};
assign tmp_40_trn_cast_fu_2931_p1 = {{6{1'b0}}, {tmp_39_fu_2926_p2}};
assign tmp_44_fu_2847_p1 = {{50{1'b0}}, {a_addr20_fu_2842_p2}};
assign tmp_45_fu_3116_p2 = (j_1_cast_reg_5472 + ap_const_lv6_1);
assign tmp_46_fu_2872_p1 = {{51{1'b0}}, {b_addr46_fu_2861_p5}};
assign tmp_46_trn_cast1_fu_3125_p4 = {{tmp_46_trn_cast_fu_3121_p1[ap_const_lv32_C : ap_const_lv32_6]}};
assign tmp_46_trn_cast2_fu_3190_p4 = {{tmp_46_trn_cast_fu_3121_p1[ap_const_lv32_C : ap_const_lv32_6]}};
assign tmp_46_trn_cast3_fu_3256_p4 = {{tmp_46_trn_cast_fu_3121_p1[ap_const_lv32_C : ap_const_lv32_6]}};
assign tmp_46_trn_cast_fu_3121_p1 = {{7{1'b0}}, {tmp_45_fu_3116_p2}};
assign tmp_47_fu_2980_p1 = {{50{1'b0}}, {a_addr23_reg_5382}};
assign tmp_50_dup_fu_3051_p2 = (j_1_phi_fu_1967_p4 + ap_const_lv7_7F);
assign tmp_50_fu_2921_p1 = {{51{1'b0}}, {b_addr48_fu_2910_p5}};
assign tmp_51_fu_2984_p1 = {{50{1'b0}}, {a_addr25_reg_5392}};
assign tmp_51_trn_cast_fu_3069_p1 = {{6{1'b0}}, {i_3_mid2_fu_3043_p3}};
assign tmp_54_fu_3157_p2 = (i_3_mid2_reg_5455 | ap_const_lv7_1);
assign tmp_55_fu_2970_p1 = {{51{1'b0}}, {b_addr50_fu_2959_p5}};
assign tmp_55_trn_cast_fu_3162_p1 = {{6{1'b0}}, {tmp_54_fu_3157_p2}};
assign tmp_58_fu_3223_p2 = (i_3_mid2_reg_5455 | ap_const_lv7_2);
assign tmp_59_fu_3020_p1 = {{51{1'b0}}, {b_addr52_fu_3008_p5}};
assign tmp_59_trn_cast_fu_3228_p1 = {{6{1'b0}}, {tmp_58_fu_3223_p2}};
assign tmp_62_fu_3337_p2 = (i_3_mid2_reg_5455 | ap_const_lv7_3);
assign tmp_63_trn_cast_fu_3342_p1 = {{6{1'b0}}, {tmp_62_fu_3337_p2}};
assign tmp_66_fu_3391_p2 = (i_3_mid2_reg_5455 | ap_const_lv7_4);
assign tmp_67_fu_3093_p1 = {{50{b_addr11_fu_3087_p2[13]}}, {b_addr11_fu_3087_p2}};
assign tmp_67_trn_cast_fu_3396_p1 = {{6{1'b0}}, {tmp_66_fu_3391_p2}};
assign tmp_6_fu_2399_p1 = {{51{1'b0}}, {a_addr_fu_2393_p2}};
assign tmp_6_trn_cast_fu_2452_p1 = {{7{1'b0}}, {j_mid2_fu_2436_p3}};
assign tmp_70_fu_3444_p2 = (i_3_mid2_reg_5455 | ap_const_lv7_5);
assign tmp_71_fu_3152_p1 = {{51{1'b0}}, {a_addr109_fu_3140_p5}};
assign tmp_71_trn_cast_fu_3449_p1 = {{6{1'b0}}, {tmp_70_fu_3444_p2}};
assign tmp_74_fu_3498_p2 = (i_3_mid2_reg_5455 | ap_const_lv7_6);
assign tmp_75_fu_3181_p1 = {{50{b_addr13_fu_3176_p2[13]}}, {b_addr13_fu_3176_p2}};
assign tmp_75_trn_cast_fu_3503_p1 = {{6{1'b0}}, {tmp_74_fu_3498_p2}};
assign tmp_78_fu_3547_p2 = (i_3_mid2_reg_5455 | ap_const_lv7_7);
assign tmp_79_fu_3218_p1 = {{51{1'b0}}, {a_addr111_fu_3206_p5}};
assign tmp_79_trn_cast_fu_3552_p1 = {{6{1'b0}}, {tmp_78_fu_3547_p2}};
assign tmp_7_fu_2495_p2 = (j_cast_reg_5221 + ap_const_lv6_3F);
assign tmp_83_fu_3247_p1 = {{50{b_addr15_fu_3242_p2[13]}}, {b_addr15_fu_3242_p2}};
assign tmp_83_trn_cast_fu_3670_p1 = {{6{1'b0}}, {i_4_mid2_fu_3658_p3}};
assign tmp_84_fu_3713_p2 = (i_4_cast_reg_5724 + ap_const_lv6_3F);
assign tmp_85_fu_3332_p1 = {{51{1'b0}}, {a_addr113_fu_3322_p5}};
assign tmp_85_trn_cast_fu_3721_p1 = {{6{1'b0}}, {tmp_84_fu_3713_p2}};
assign tmp_86_fu_3361_p1 = {{50{b_addr17_fu_3356_p2[13]}}, {b_addr17_fu_3356_p2}};
assign tmp_86_trn_cast_fu_3990_p1 = {{6{1'b0}}, {j_4_phi_fu_2055_p4}};
assign tmp_89_dup_fu_3652_p2 = (i_4_phi_fu_2022_p4 + ap_const_lv7_1);
assign tmp_89_fu_3386_p1 = {{51{1'b0}}, {a_addr115_fu_3375_p5}};
assign tmp_8_trn_cast1_fu_2504_p4 = {{tmp_8_trn_cast_fu_2500_p1[ap_const_lv32_C : ap_const_lv32_6]}};
assign tmp_8_trn_cast2_fu_2569_p4 = {{tmp_8_trn_cast_fu_2500_p1[ap_const_lv32_C : ap_const_lv32_6]}};
assign tmp_8_trn_cast3_fu_2635_p4 = {{tmp_8_trn_cast_fu_2500_p1[ap_const_lv32_C : ap_const_lv32_6]}};
assign tmp_8_trn_cast_fu_2500_p1 = {{7{1'b0}}, {tmp_7_fu_2495_p2}};
assign tmp_90_fu_3415_p1 = {{50{b_addr19_fu_3410_p2[13]}}, {b_addr19_fu_3410_p2}};
assign tmp_90_trn_cast1_fu_3718_p1 = {{6{1'b0}}, {j_3_mid2_reg_5706}};
assign tmp_90_trn_cast_fu_3674_p1 = {{7{1'b0}}, {j_3_mid2_fu_3644_p3}};
assign tmp_93_fu_3746_p2 = (j_3_mid2_reg_5706 | ap_const_lv7_1);
assign tmp_94_fu_3439_p1 = {{51{1'b0}}, {a_addr117_fu_3429_p5}};
assign tmp_94_trn_cast1_fu_3751_p1 = {{6{1'b0}}, {tmp_93_fu_3746_p2}};
assign tmp_94_trn_cast_fu_3755_p1 = {{7{1'b0}}, {tmp_93_fu_3746_p2}};
assign tmp_97_fu_3780_p2 = (j_3_mid2_reg_5706 | ap_const_lv7_2);
assign tmp_98_fu_3468_p1 = {{50{b_addr21_fu_3463_p2[13]}}, {b_addr21_fu_3463_p2}};
assign tmp_98_trn_cast1_fu_3799_p1 = {{6{1'b0}}, {tmp_97_reg_5785}};
assign tmp_98_trn_cast_fu_3785_p1 = {{7{1'b0}}, {tmp_97_fu_3780_p2}};
assign tmp_9_fu_2472_p1 = {{50{1'b0}}, {a_addr3_fu_2466_p2}};
assign tmp_9_trn_cast_fu_3000_p1 = {{6{1'b0}}, {i_2_phi_fu_1945_p4}};
assign tmp_fu_2353_p2 = (counter < ap_const_lv7_41? 1'b1: 1'b0);
always @ (ap_clk)
begin
tmp_6_reg_5180[0] <= 1'b0;
tmp_6_reg_5180[1] <= 1'b0;
tmp_6_reg_5180[2] <= 1'b0;
tmp_6_reg_5180[3] <= 1'b0;
tmp_6_reg_5180[4] <= 1'b0;
tmp_6_reg_5180[5] <= 1'b0;
tmp_6_reg_5180[13] <= 1'b0;
tmp_6_reg_5180[14] <= 1'b0;
tmp_6_reg_5180[15] <= 1'b0;
tmp_6_reg_5180[16] <= 1'b0;
tmp_6_reg_5180[17] <= 1'b0;
tmp_6_reg_5180[18] <= 1'b0;
tmp_6_reg_5180[19] <= 1'b0;
tmp_6_reg_5180[20] <= 1'b0;
tmp_6_reg_5180[21] <= 1'b0;
tmp_6_reg_5180[22] <= 1'b0;
tmp_6_reg_5180[23] <= 1'b0;
tmp_6_reg_5180[24] <= 1'b0;
tmp_6_reg_5180[25] <= 1'b0;
tmp_6_reg_5180[26] <= 1'b0;
tmp_6_reg_5180[27] <= 1'b0;
tmp_6_reg_5180[28] <= 1'b0;
tmp_6_reg_5180[29] <= 1'b0;
tmp_6_reg_5180[30] <= 1'b0;
tmp_6_reg_5180[31] <= 1'b0;
tmp_6_reg_5180[32] <= 1'b0;
tmp_6_reg_5180[33] <= 1'b0;
tmp_6_reg_5180[34] <= 1'b0;
tmp_6_reg_5180[35] <= 1'b0;
tmp_6_reg_5180[36] <= 1'b0;
tmp_6_reg_5180[37] <= 1'b0;
tmp_6_reg_5180[38] <= 1'b0;
tmp_6_reg_5180[39] <= 1'b0;
tmp_6_reg_5180[40] <= 1'b0;
tmp_6_reg_5180[41] <= 1'b0;
tmp_6_reg_5180[42] <= 1'b0;
tmp_6_reg_5180[43] <= 1'b0;
tmp_6_reg_5180[44] <= 1'b0;
tmp_6_reg_5180[45] <= 1'b0;
tmp_6_reg_5180[46] <= 1'b0;
tmp_6_reg_5180[47] <= 1'b0;
tmp_6_reg_5180[48] <= 1'b0;
tmp_6_reg_5180[49] <= 1'b0;
tmp_6_reg_5180[50] <= 1'b0;
tmp_6_reg_5180[51] <= 1'b0;
tmp_6_reg_5180[52] <= 1'b0;
tmp_6_reg_5180[53] <= 1'b0;
tmp_6_reg_5180[54] <= 1'b0;
tmp_6_reg_5180[55] <= 1'b0;
tmp_6_reg_5180[56] <= 1'b0;
tmp_6_reg_5180[57] <= 1'b0;
tmp_6_reg_5180[58] <= 1'b0;
tmp_6_reg_5180[59] <= 1'b0;
tmp_6_reg_5180[60] <= 1'b0;
tmp_6_reg_5180[61] <= 1'b0;
tmp_6_reg_5180[62] <= 1'b0;
tmp_6_reg_5180[63] <= 1'b0;
end
always @ (ap_clk)
begin
ap_reg_ppstg_tmp_6_reg_5180_pp0_it1[0] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it1[1] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it1[2] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it1[3] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it1[4] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it1[5] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it1[13] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it1[14] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it1[15] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it1[16] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it1[17] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it1[18] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it1[19] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it1[20] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it1[21] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it1[22] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it1[23] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it1[24] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it1[25] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it1[26] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it1[27] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it1[28] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it1[29] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it1[30] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it1[31] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it1[32] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it1[33] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it1[34] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it1[35] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it1[36] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it1[37] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it1[38] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it1[39] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it1[40] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it1[41] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it1[42] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it1[43] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it1[44] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it1[45] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it1[46] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it1[47] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it1[48] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it1[49] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it1[50] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it1[51] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it1[52] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it1[53] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it1[54] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it1[55] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it1[56] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it1[57] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it1[58] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it1[59] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it1[60] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it1[61] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it1[62] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it1[63] <= 1'b0;
end
always @ (ap_clk)
begin
ap_reg_ppstg_tmp_6_reg_5180_pp0_it2[0] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it2[1] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it2[2] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it2[3] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it2[4] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it2[5] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it2[13] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it2[14] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it2[15] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it2[16] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it2[17] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it2[18] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it2[19] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it2[20] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it2[21] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it2[22] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it2[23] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it2[24] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it2[25] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it2[26] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it2[27] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it2[28] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it2[29] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it2[30] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it2[31] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it2[32] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it2[33] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it2[34] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it2[35] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it2[36] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it2[37] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it2[38] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it2[39] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it2[40] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it2[41] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it2[42] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it2[43] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it2[44] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it2[45] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it2[46] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it2[47] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it2[48] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it2[49] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it2[50] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it2[51] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it2[52] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it2[53] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it2[54] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it2[55] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it2[56] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it2[57] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it2[58] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it2[59] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it2[60] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it2[61] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it2[62] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it2[63] <= 1'b0;
end
always @ (ap_clk)
begin
ap_reg_ppstg_tmp_6_reg_5180_pp0_it3[0] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it3[1] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it3[2] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it3[3] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it3[4] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it3[5] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it3[13] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it3[14] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it3[15] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it3[16] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it3[17] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it3[18] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it3[19] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it3[20] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it3[21] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it3[22] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it3[23] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it3[24] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it3[25] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it3[26] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it3[27] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it3[28] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it3[29] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it3[30] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it3[31] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it3[32] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it3[33] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it3[34] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it3[35] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it3[36] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it3[37] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it3[38] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it3[39] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it3[40] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it3[41] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it3[42] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it3[43] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it3[44] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it3[45] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it3[46] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it3[47] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it3[48] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it3[49] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it3[50] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it3[51] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it3[52] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it3[53] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it3[54] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it3[55] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it3[56] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it3[57] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it3[58] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it3[59] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it3[60] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it3[61] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it3[62] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it3[63] <= 1'b0;
end
always @ (ap_clk)
begin
ap_reg_ppstg_tmp_6_reg_5180_pp0_it4[0] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it4[1] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it4[2] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it4[3] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it4[4] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it4[5] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it4[13] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it4[14] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it4[15] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it4[16] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it4[17] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it4[18] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it4[19] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it4[20] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it4[21] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it4[22] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it4[23] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it4[24] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it4[25] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it4[26] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it4[27] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it4[28] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it4[29] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it4[30] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it4[31] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it4[32] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it4[33] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it4[34] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it4[35] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it4[36] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it4[37] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it4[38] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it4[39] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it4[40] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it4[41] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it4[42] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it4[43] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it4[44] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it4[45] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it4[46] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it4[47] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it4[48] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it4[49] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it4[50] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it4[51] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it4[52] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it4[53] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it4[54] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it4[55] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it4[56] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it4[57] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it4[58] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it4[59] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it4[60] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it4[61] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it4[62] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it4[63] <= 1'b0;
end
always @ (ap_clk)
begin
ap_reg_ppstg_tmp_6_reg_5180_pp0_it5[0] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it5[1] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it5[2] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it5[3] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it5[4] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it5[5] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it5[13] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it5[14] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it5[15] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it5[16] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it5[17] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it5[18] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it5[19] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it5[20] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it5[21] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it5[22] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it5[23] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it5[24] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it5[25] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it5[26] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it5[27] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it5[28] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it5[29] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it5[30] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it5[31] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it5[32] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it5[33] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it5[34] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it5[35] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it5[36] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it5[37] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it5[38] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it5[39] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it5[40] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it5[41] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it5[42] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it5[43] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it5[44] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it5[45] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it5[46] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it5[47] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it5[48] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it5[49] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it5[50] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it5[51] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it5[52] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it5[53] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it5[54] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it5[55] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it5[56] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it5[57] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it5[58] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it5[59] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it5[60] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it5[61] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it5[62] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it5[63] <= 1'b0;
end
always @ (ap_clk)
begin
tmp_6_trn_cast_reg_5226[7] <= 1'b0;
tmp_6_trn_cast_reg_5226[8] <= 1'b0;
tmp_6_trn_cast_reg_5226[9] <= 1'b0;
tmp_6_trn_cast_reg_5226[10] <= 1'b0;
tmp_6_trn_cast_reg_5226[11] <= 1'b0;
tmp_6_trn_cast_reg_5226[12] <= 1'b0;
tmp_6_trn_cast_reg_5226[13] <= 1'b0;
end
always @ (ap_clk)
begin
tmp_9_reg_5237[14] <= 1'b0;
tmp_9_reg_5237[15] <= 1'b0;
tmp_9_reg_5237[16] <= 1'b0;
tmp_9_reg_5237[17] <= 1'b0;
tmp_9_reg_5237[18] <= 1'b0;
tmp_9_reg_5237[19] <= 1'b0;
tmp_9_reg_5237[20] <= 1'b0;
tmp_9_reg_5237[21] <= 1'b0;
tmp_9_reg_5237[22] <= 1'b0;
tmp_9_reg_5237[23] <= 1'b0;
tmp_9_reg_5237[24] <= 1'b0;
tmp_9_reg_5237[25] <= 1'b0;
tmp_9_reg_5237[26] <= 1'b0;
tmp_9_reg_5237[27] <= 1'b0;
tmp_9_reg_5237[28] <= 1'b0;
tmp_9_reg_5237[29] <= 1'b0;
tmp_9_reg_5237[30] <= 1'b0;
tmp_9_reg_5237[31] <= 1'b0;
tmp_9_reg_5237[32] <= 1'b0;
tmp_9_reg_5237[33] <= 1'b0;
tmp_9_reg_5237[34] <= 1'b0;
tmp_9_reg_5237[35] <= 1'b0;
tmp_9_reg_5237[36] <= 1'b0;
tmp_9_reg_5237[37] <= 1'b0;
tmp_9_reg_5237[38] <= 1'b0;
tmp_9_reg_5237[39] <= 1'b0;
tmp_9_reg_5237[40] <= 1'b0;
tmp_9_reg_5237[41] <= 1'b0;
tmp_9_reg_5237[42] <= 1'b0;
tmp_9_reg_5237[43] <= 1'b0;
tmp_9_reg_5237[44] <= 1'b0;
tmp_9_reg_5237[45] <= 1'b0;
tmp_9_reg_5237[46] <= 1'b0;
tmp_9_reg_5237[47] <= 1'b0;
tmp_9_reg_5237[48] <= 1'b0;
tmp_9_reg_5237[49] <= 1'b0;
tmp_9_reg_5237[50] <= 1'b0;
tmp_9_reg_5237[51] <= 1'b0;
tmp_9_reg_5237[52] <= 1'b0;
tmp_9_reg_5237[53] <= 1'b0;
tmp_9_reg_5237[54] <= 1'b0;
tmp_9_reg_5237[55] <= 1'b0;
tmp_9_reg_5237[56] <= 1'b0;
tmp_9_reg_5237[57] <= 1'b0;
tmp_9_reg_5237[58] <= 1'b0;
tmp_9_reg_5237[59] <= 1'b0;
tmp_9_reg_5237[60] <= 1'b0;
tmp_9_reg_5237[61] <= 1'b0;
tmp_9_reg_5237[62] <= 1'b0;
tmp_9_reg_5237[63] <= 1'b0;
end
always @ (ap_clk)
begin
ap_reg_ppstg_tmp_9_reg_5237_pp1_it1[14] <= 1'b0;
ap_reg_ppstg_tmp_9_reg_5237_pp1_it1[15] <= 1'b0;
ap_reg_ppstg_tmp_9_reg_5237_pp1_it1[16] <= 1'b0;
ap_reg_ppstg_tmp_9_reg_5237_pp1_it1[17] <= 1'b0;
ap_reg_ppstg_tmp_9_reg_5237_pp1_it1[18] <= 1'b0;
ap_reg_ppstg_tmp_9_reg_5237_pp1_it1[19] <= 1'b0;
ap_reg_ppstg_tmp_9_reg_5237_pp1_it1[20] <= 1'b0;
ap_reg_ppstg_tmp_9_reg_5237_pp1_it1[21] <= 1'b0;
ap_reg_ppstg_tmp_9_reg_5237_pp1_it1[22] <= 1'b0;
ap_reg_ppstg_tmp_9_reg_5237_pp1_it1[23] <= 1'b0;
ap_reg_ppstg_tmp_9_reg_5237_pp1_it1[24] <= 1'b0;
ap_reg_ppstg_tmp_9_reg_5237_pp1_it1[25] <= 1'b0;
ap_reg_ppstg_tmp_9_reg_5237_pp1_it1[26] <= 1'b0;
ap_reg_ppstg_tmp_9_reg_5237_pp1_it1[27] <= 1'b0;
ap_reg_ppstg_tmp_9_reg_5237_pp1_it1[28] <= 1'b0;
ap_reg_ppstg_tmp_9_reg_5237_pp1_it1[29] <= 1'b0;
ap_reg_ppstg_tmp_9_reg_5237_pp1_it1[30] <= 1'b0;
ap_reg_ppstg_tmp_9_reg_5237_pp1_it1[31] <= 1'b0;
ap_reg_ppstg_tmp_9_reg_5237_pp1_it1[32] <= 1'b0;
ap_reg_ppstg_tmp_9_reg_5237_pp1_it1[33] <= 1'b0;
ap_reg_ppstg_tmp_9_reg_5237_pp1_it1[34] <= 1'b0;
ap_reg_ppstg_tmp_9_reg_5237_pp1_it1[35] <= 1'b0;
ap_reg_ppstg_tmp_9_reg_5237_pp1_it1[36] <= 1'b0;
ap_reg_ppstg_tmp_9_reg_5237_pp1_it1[37] <= 1'b0;
ap_reg_ppstg_tmp_9_reg_5237_pp1_it1[38] <= 1'b0;
ap_reg_ppstg_tmp_9_reg_5237_pp1_it1[39] <= 1'b0;
ap_reg_ppstg_tmp_9_reg_5237_pp1_it1[40] <= 1'b0;
ap_reg_ppstg_tmp_9_reg_5237_pp1_it1[41] <= 1'b0;
ap_reg_ppstg_tmp_9_reg_5237_pp1_it1[42] <= 1'b0;
ap_reg_ppstg_tmp_9_reg_5237_pp1_it1[43] <= 1'b0;
ap_reg_ppstg_tmp_9_reg_5237_pp1_it1[44] <= 1'b0;
ap_reg_ppstg_tmp_9_reg_5237_pp1_it1[45] <= 1'b0;
ap_reg_ppstg_tmp_9_reg_5237_pp1_it1[46] <= 1'b0;
ap_reg_ppstg_tmp_9_reg_5237_pp1_it1[47] <= 1'b0;
ap_reg_ppstg_tmp_9_reg_5237_pp1_it1[48] <= 1'b0;
ap_reg_ppstg_tmp_9_reg_5237_pp1_it1[49] <= 1'b0;
ap_reg_ppstg_tmp_9_reg_5237_pp1_it1[50] <= 1'b0;
ap_reg_ppstg_tmp_9_reg_5237_pp1_it1[51] <= 1'b0;
ap_reg_ppstg_tmp_9_reg_5237_pp1_it1[52] <= 1'b0;
ap_reg_ppstg_tmp_9_reg_5237_pp1_it1[53] <= 1'b0;
ap_reg_ppstg_tmp_9_reg_5237_pp1_it1[54] <= 1'b0;
ap_reg_ppstg_tmp_9_reg_5237_pp1_it1[55] <= 1'b0;
ap_reg_ppstg_tmp_9_reg_5237_pp1_it1[56] <= 1'b0;
ap_reg_ppstg_tmp_9_reg_5237_pp1_it1[57] <= 1'b0;
ap_reg_ppstg_tmp_9_reg_5237_pp1_it1[58] <= 1'b0;
ap_reg_ppstg_tmp_9_reg_5237_pp1_it1[59] <= 1'b0;
ap_reg_ppstg_tmp_9_reg_5237_pp1_it1[60] <= 1'b0;
ap_reg_ppstg_tmp_9_reg_5237_pp1_it1[61] <= 1'b0;
ap_reg_ppstg_tmp_9_reg_5237_pp1_it1[62] <= 1'b0;
ap_reg_ppstg_tmp_9_reg_5237_pp1_it1[63] <= 1'b0;
end
always @ (ap_clk)
begin
tmp_8_trn_cast_reg_5257[6] <= 1'b0;
tmp_8_trn_cast_reg_5257[7] <= 1'b0;
tmp_8_trn_cast_reg_5257[8] <= 1'b0;
tmp_8_trn_cast_reg_5257[9] <= 1'b0;
tmp_8_trn_cast_reg_5257[10] <= 1'b0;
tmp_8_trn_cast_reg_5257[11] <= 1'b0;
tmp_8_trn_cast_reg_5257[12] <= 1'b0;
end
always @ (ap_clk)
begin
tmp_15_reg_5272[14] <= 1'b0;
tmp_15_reg_5272[15] <= 1'b0;
tmp_15_reg_5272[16] <= 1'b0;
tmp_15_reg_5272[17] <= 1'b0;
tmp_15_reg_5272[18] <= 1'b0;
tmp_15_reg_5272[19] <= 1'b0;
tmp_15_reg_5272[20] <= 1'b0;
tmp_15_reg_5272[21] <= 1'b0;
tmp_15_reg_5272[22] <= 1'b0;
tmp_15_reg_5272[23] <= 1'b0;
tmp_15_reg_5272[24] <= 1'b0;
tmp_15_reg_5272[25] <= 1'b0;
tmp_15_reg_5272[26] <= 1'b0;
tmp_15_reg_5272[27] <= 1'b0;
tmp_15_reg_5272[28] <= 1'b0;
tmp_15_reg_5272[29] <= 1'b0;
tmp_15_reg_5272[30] <= 1'b0;
tmp_15_reg_5272[31] <= 1'b0;
tmp_15_reg_5272[32] <= 1'b0;
tmp_15_reg_5272[33] <= 1'b0;
tmp_15_reg_5272[34] <= 1'b0;
tmp_15_reg_5272[35] <= 1'b0;
tmp_15_reg_5272[36] <= 1'b0;
tmp_15_reg_5272[37] <= 1'b0;
tmp_15_reg_5272[38] <= 1'b0;
tmp_15_reg_5272[39] <= 1'b0;
tmp_15_reg_5272[40] <= 1'b0;
tmp_15_reg_5272[41] <= 1'b0;
tmp_15_reg_5272[42] <= 1'b0;
tmp_15_reg_5272[43] <= 1'b0;
tmp_15_reg_5272[44] <= 1'b0;
tmp_15_reg_5272[45] <= 1'b0;
tmp_15_reg_5272[46] <= 1'b0;
tmp_15_reg_5272[47] <= 1'b0;
tmp_15_reg_5272[48] <= 1'b0;
tmp_15_reg_5272[49] <= 1'b0;
tmp_15_reg_5272[50] <= 1'b0;
tmp_15_reg_5272[51] <= 1'b0;
tmp_15_reg_5272[52] <= 1'b0;
tmp_15_reg_5272[53] <= 1'b0;
tmp_15_reg_5272[54] <= 1'b0;
tmp_15_reg_5272[55] <= 1'b0;
tmp_15_reg_5272[56] <= 1'b0;
tmp_15_reg_5272[57] <= 1'b0;
tmp_15_reg_5272[58] <= 1'b0;
tmp_15_reg_5272[59] <= 1'b0;
tmp_15_reg_5272[60] <= 1'b0;
tmp_15_reg_5272[61] <= 1'b0;
tmp_15_reg_5272[62] <= 1'b0;
tmp_15_reg_5272[63] <= 1'b0;
end
always @ (ap_clk)
begin
ap_reg_ppstg_tmp_15_reg_5272_pp1_it1[14] <= 1'b0;
ap_reg_ppstg_tmp_15_reg_5272_pp1_it1[15] <= 1'b0;
ap_reg_ppstg_tmp_15_reg_5272_pp1_it1[16] <= 1'b0;
ap_reg_ppstg_tmp_15_reg_5272_pp1_it1[17] <= 1'b0;
ap_reg_ppstg_tmp_15_reg_5272_pp1_it1[18] <= 1'b0;
ap_reg_ppstg_tmp_15_reg_5272_pp1_it1[19] <= 1'b0;
ap_reg_ppstg_tmp_15_reg_5272_pp1_it1[20] <= 1'b0;
ap_reg_ppstg_tmp_15_reg_5272_pp1_it1[21] <= 1'b0;
ap_reg_ppstg_tmp_15_reg_5272_pp1_it1[22] <= 1'b0;
ap_reg_ppstg_tmp_15_reg_5272_pp1_it1[23] <= 1'b0;
ap_reg_ppstg_tmp_15_reg_5272_pp1_it1[24] <= 1'b0;
ap_reg_ppstg_tmp_15_reg_5272_pp1_it1[25] <= 1'b0;
ap_reg_ppstg_tmp_15_reg_5272_pp1_it1[26] <= 1'b0;
ap_reg_ppstg_tmp_15_reg_5272_pp1_it1[27] <= 1'b0;
ap_reg_ppstg_tmp_15_reg_5272_pp1_it1[28] <= 1'b0;
ap_reg_ppstg_tmp_15_reg_5272_pp1_it1[29] <= 1'b0;
ap_reg_ppstg_tmp_15_reg_5272_pp1_it1[30] <= 1'b0;
ap_reg_ppstg_tmp_15_reg_5272_pp1_it1[31] <= 1'b0;
ap_reg_ppstg_tmp_15_reg_5272_pp1_it1[32] <= 1'b0;
ap_reg_ppstg_tmp_15_reg_5272_pp1_it1[33] <= 1'b0;
ap_reg_ppstg_tmp_15_reg_5272_pp1_it1[34] <= 1'b0;
ap_reg_ppstg_tmp_15_reg_5272_pp1_it1[35] <= 1'b0;
ap_reg_ppstg_tmp_15_reg_5272_pp1_it1[36] <= 1'b0;
ap_reg_ppstg_tmp_15_reg_5272_pp1_it1[37] <= 1'b0;
ap_reg_ppstg_tmp_15_reg_5272_pp1_it1[38] <= 1'b0;
ap_reg_ppstg_tmp_15_reg_5272_pp1_it1[39] <= 1'b0;
ap_reg_ppstg_tmp_15_reg_5272_pp1_it1[40] <= 1'b0;
ap_reg_ppstg_tmp_15_reg_5272_pp1_it1[41] <= 1'b0;
ap_reg_ppstg_tmp_15_reg_5272_pp1_it1[42] <= 1'b0;
ap_reg_ppstg_tmp_15_reg_5272_pp1_it1[43] <= 1'b0;
ap_reg_ppstg_tmp_15_reg_5272_pp1_it1[44] <= 1'b0;
ap_reg_ppstg_tmp_15_reg_5272_pp1_it1[45] <= 1'b0;
ap_reg_ppstg_tmp_15_reg_5272_pp1_it1[46] <= 1'b0;
ap_reg_ppstg_tmp_15_reg_5272_pp1_it1[47] <= 1'b0;
ap_reg_ppstg_tmp_15_reg_5272_pp1_it1[48] <= 1'b0;
ap_reg_ppstg_tmp_15_reg_5272_pp1_it1[49] <= 1'b0;
ap_reg_ppstg_tmp_15_reg_5272_pp1_it1[50] <= 1'b0;
ap_reg_ppstg_tmp_15_reg_5272_pp1_it1[51] <= 1'b0;
ap_reg_ppstg_tmp_15_reg_5272_pp1_it1[52] <= 1'b0;
ap_reg_ppstg_tmp_15_reg_5272_pp1_it1[53] <= 1'b0;
ap_reg_ppstg_tmp_15_reg_5272_pp1_it1[54] <= 1'b0;
ap_reg_ppstg_tmp_15_reg_5272_pp1_it1[55] <= 1'b0;
ap_reg_ppstg_tmp_15_reg_5272_pp1_it1[56] <= 1'b0;
ap_reg_ppstg_tmp_15_reg_5272_pp1_it1[57] <= 1'b0;
ap_reg_ppstg_tmp_15_reg_5272_pp1_it1[58] <= 1'b0;
ap_reg_ppstg_tmp_15_reg_5272_pp1_it1[59] <= 1'b0;
ap_reg_ppstg_tmp_15_reg_5272_pp1_it1[60] <= 1'b0;
ap_reg_ppstg_tmp_15_reg_5272_pp1_it1[61] <= 1'b0;
ap_reg_ppstg_tmp_15_reg_5272_pp1_it1[62] <= 1'b0;
ap_reg_ppstg_tmp_15_reg_5272_pp1_it1[63] <= 1'b0;
end
always @ (ap_clk)
begin
tmp_20_reg_5287[14] <= 1'b0;
tmp_20_reg_5287[15] <= 1'b0;
tmp_20_reg_5287[16] <= 1'b0;
tmp_20_reg_5287[17] <= 1'b0;
tmp_20_reg_5287[18] <= 1'b0;
tmp_20_reg_5287[19] <= 1'b0;
tmp_20_reg_5287[20] <= 1'b0;
tmp_20_reg_5287[21] <= 1'b0;
tmp_20_reg_5287[22] <= 1'b0;
tmp_20_reg_5287[23] <= 1'b0;
tmp_20_reg_5287[24] <= 1'b0;
tmp_20_reg_5287[25] <= 1'b0;
tmp_20_reg_5287[26] <= 1'b0;
tmp_20_reg_5287[27] <= 1'b0;
tmp_20_reg_5287[28] <= 1'b0;
tmp_20_reg_5287[29] <= 1'b0;
tmp_20_reg_5287[30] <= 1'b0;
tmp_20_reg_5287[31] <= 1'b0;
tmp_20_reg_5287[32] <= 1'b0;
tmp_20_reg_5287[33] <= 1'b0;
tmp_20_reg_5287[34] <= 1'b0;
tmp_20_reg_5287[35] <= 1'b0;
tmp_20_reg_5287[36] <= 1'b0;
tmp_20_reg_5287[37] <= 1'b0;
tmp_20_reg_5287[38] <= 1'b0;
tmp_20_reg_5287[39] <= 1'b0;
tmp_20_reg_5287[40] <= 1'b0;
tmp_20_reg_5287[41] <= 1'b0;
tmp_20_reg_5287[42] <= 1'b0;
tmp_20_reg_5287[43] <= 1'b0;
tmp_20_reg_5287[44] <= 1'b0;
tmp_20_reg_5287[45] <= 1'b0;
tmp_20_reg_5287[46] <= 1'b0;
tmp_20_reg_5287[47] <= 1'b0;
tmp_20_reg_5287[48] <= 1'b0;
tmp_20_reg_5287[49] <= 1'b0;
tmp_20_reg_5287[50] <= 1'b0;
tmp_20_reg_5287[51] <= 1'b0;
tmp_20_reg_5287[52] <= 1'b0;
tmp_20_reg_5287[53] <= 1'b0;
tmp_20_reg_5287[54] <= 1'b0;
tmp_20_reg_5287[55] <= 1'b0;
tmp_20_reg_5287[56] <= 1'b0;
tmp_20_reg_5287[57] <= 1'b0;
tmp_20_reg_5287[58] <= 1'b0;
tmp_20_reg_5287[59] <= 1'b0;
tmp_20_reg_5287[60] <= 1'b0;
tmp_20_reg_5287[61] <= 1'b0;
tmp_20_reg_5287[62] <= 1'b0;
tmp_20_reg_5287[63] <= 1'b0;
end
always @ (ap_clk)
begin
ap_reg_ppstg_tmp_20_reg_5287_pp1_it1[14] <= 1'b0;
ap_reg_ppstg_tmp_20_reg_5287_pp1_it1[15] <= 1'b0;
ap_reg_ppstg_tmp_20_reg_5287_pp1_it1[16] <= 1'b0;
ap_reg_ppstg_tmp_20_reg_5287_pp1_it1[17] <= 1'b0;
ap_reg_ppstg_tmp_20_reg_5287_pp1_it1[18] <= 1'b0;
ap_reg_ppstg_tmp_20_reg_5287_pp1_it1[19] <= 1'b0;
ap_reg_ppstg_tmp_20_reg_5287_pp1_it1[20] <= 1'b0;
ap_reg_ppstg_tmp_20_reg_5287_pp1_it1[21] <= 1'b0;
ap_reg_ppstg_tmp_20_reg_5287_pp1_it1[22] <= 1'b0;
ap_reg_ppstg_tmp_20_reg_5287_pp1_it1[23] <= 1'b0;
ap_reg_ppstg_tmp_20_reg_5287_pp1_it1[24] <= 1'b0;
ap_reg_ppstg_tmp_20_reg_5287_pp1_it1[25] <= 1'b0;
ap_reg_ppstg_tmp_20_reg_5287_pp1_it1[26] <= 1'b0;
ap_reg_ppstg_tmp_20_reg_5287_pp1_it1[27] <= 1'b0;
ap_reg_ppstg_tmp_20_reg_5287_pp1_it1[28] <= 1'b0;
ap_reg_ppstg_tmp_20_reg_5287_pp1_it1[29] <= 1'b0;
ap_reg_ppstg_tmp_20_reg_5287_pp1_it1[30] <= 1'b0;
ap_reg_ppstg_tmp_20_reg_5287_pp1_it1[31] <= 1'b0;
ap_reg_ppstg_tmp_20_reg_5287_pp1_it1[32] <= 1'b0;
ap_reg_ppstg_tmp_20_reg_5287_pp1_it1[33] <= 1'b0;
ap_reg_ppstg_tmp_20_reg_5287_pp1_it1[34] <= 1'b0;
ap_reg_ppstg_tmp_20_reg_5287_pp1_it1[35] <= 1'b0;
ap_reg_ppstg_tmp_20_reg_5287_pp1_it1[36] <= 1'b0;
ap_reg_ppstg_tmp_20_reg_5287_pp1_it1[37] <= 1'b0;
ap_reg_ppstg_tmp_20_reg_5287_pp1_it1[38] <= 1'b0;
ap_reg_ppstg_tmp_20_reg_5287_pp1_it1[39] <= 1'b0;
ap_reg_ppstg_tmp_20_reg_5287_pp1_it1[40] <= 1'b0;
ap_reg_ppstg_tmp_20_reg_5287_pp1_it1[41] <= 1'b0;
ap_reg_ppstg_tmp_20_reg_5287_pp1_it1[42] <= 1'b0;
ap_reg_ppstg_tmp_20_reg_5287_pp1_it1[43] <= 1'b0;
ap_reg_ppstg_tmp_20_reg_5287_pp1_it1[44] <= 1'b0;
ap_reg_ppstg_tmp_20_reg_5287_pp1_it1[45] <= 1'b0;
ap_reg_ppstg_tmp_20_reg_5287_pp1_it1[46] <= 1'b0;
ap_reg_ppstg_tmp_20_reg_5287_pp1_it1[47] <= 1'b0;
ap_reg_ppstg_tmp_20_reg_5287_pp1_it1[48] <= 1'b0;
ap_reg_ppstg_tmp_20_reg_5287_pp1_it1[49] <= 1'b0;
ap_reg_ppstg_tmp_20_reg_5287_pp1_it1[50] <= 1'b0;
ap_reg_ppstg_tmp_20_reg_5287_pp1_it1[51] <= 1'b0;
ap_reg_ppstg_tmp_20_reg_5287_pp1_it1[52] <= 1'b0;
ap_reg_ppstg_tmp_20_reg_5287_pp1_it1[53] <= 1'b0;
ap_reg_ppstg_tmp_20_reg_5287_pp1_it1[54] <= 1'b0;
ap_reg_ppstg_tmp_20_reg_5287_pp1_it1[55] <= 1'b0;
ap_reg_ppstg_tmp_20_reg_5287_pp1_it1[56] <= 1'b0;
ap_reg_ppstg_tmp_20_reg_5287_pp1_it1[57] <= 1'b0;
ap_reg_ppstg_tmp_20_reg_5287_pp1_it1[58] <= 1'b0;
ap_reg_ppstg_tmp_20_reg_5287_pp1_it1[59] <= 1'b0;
ap_reg_ppstg_tmp_20_reg_5287_pp1_it1[60] <= 1'b0;
ap_reg_ppstg_tmp_20_reg_5287_pp1_it1[61] <= 1'b0;
ap_reg_ppstg_tmp_20_reg_5287_pp1_it1[62] <= 1'b0;
ap_reg_ppstg_tmp_20_reg_5287_pp1_it1[63] <= 1'b0;
end
always @ (ap_clk)
begin
b_addr4_reg_5297[1] <= 1'b1;
end
always @ (ap_clk)
begin
tmp_28_reg_5332[14] <= 1'b0;
tmp_28_reg_5332[15] <= 1'b0;
tmp_28_reg_5332[16] <= 1'b0;
tmp_28_reg_5332[17] <= 1'b0;
tmp_28_reg_5332[18] <= 1'b0;
tmp_28_reg_5332[19] <= 1'b0;
tmp_28_reg_5332[20] <= 1'b0;
tmp_28_reg_5332[21] <= 1'b0;
tmp_28_reg_5332[22] <= 1'b0;
tmp_28_reg_5332[23] <= 1'b0;
tmp_28_reg_5332[24] <= 1'b0;
tmp_28_reg_5332[25] <= 1'b0;
tmp_28_reg_5332[26] <= 1'b0;
tmp_28_reg_5332[27] <= 1'b0;
tmp_28_reg_5332[28] <= 1'b0;
tmp_28_reg_5332[29] <= 1'b0;
tmp_28_reg_5332[30] <= 1'b0;
tmp_28_reg_5332[31] <= 1'b0;
tmp_28_reg_5332[32] <= 1'b0;
tmp_28_reg_5332[33] <= 1'b0;
tmp_28_reg_5332[34] <= 1'b0;
tmp_28_reg_5332[35] <= 1'b0;
tmp_28_reg_5332[36] <= 1'b0;
tmp_28_reg_5332[37] <= 1'b0;
tmp_28_reg_5332[38] <= 1'b0;
tmp_28_reg_5332[39] <= 1'b0;
tmp_28_reg_5332[40] <= 1'b0;
tmp_28_reg_5332[41] <= 1'b0;
tmp_28_reg_5332[42] <= 1'b0;
tmp_28_reg_5332[43] <= 1'b0;
tmp_28_reg_5332[44] <= 1'b0;
tmp_28_reg_5332[45] <= 1'b0;
tmp_28_reg_5332[46] <= 1'b0;
tmp_28_reg_5332[47] <= 1'b0;
tmp_28_reg_5332[48] <= 1'b0;
tmp_28_reg_5332[49] <= 1'b0;
tmp_28_reg_5332[50] <= 1'b0;
tmp_28_reg_5332[51] <= 1'b0;
tmp_28_reg_5332[52] <= 1'b0;
tmp_28_reg_5332[53] <= 1'b0;
tmp_28_reg_5332[54] <= 1'b0;
tmp_28_reg_5332[55] <= 1'b0;
tmp_28_reg_5332[56] <= 1'b0;
tmp_28_reg_5332[57] <= 1'b0;
tmp_28_reg_5332[58] <= 1'b0;
tmp_28_reg_5332[59] <= 1'b0;
tmp_28_reg_5332[60] <= 1'b0;
tmp_28_reg_5332[61] <= 1'b0;
tmp_28_reg_5332[62] <= 1'b0;
tmp_28_reg_5332[63] <= 1'b0;
end
always @ (ap_clk)
begin
ap_reg_ppstg_tmp_28_reg_5332_pp1_it1[14] <= 1'b0;
ap_reg_ppstg_tmp_28_reg_5332_pp1_it1[15] <= 1'b0;
ap_reg_ppstg_tmp_28_reg_5332_pp1_it1[16] <= 1'b0;
ap_reg_ppstg_tmp_28_reg_5332_pp1_it1[17] <= 1'b0;
ap_reg_ppstg_tmp_28_reg_5332_pp1_it1[18] <= 1'b0;
ap_reg_ppstg_tmp_28_reg_5332_pp1_it1[19] <= 1'b0;
ap_reg_ppstg_tmp_28_reg_5332_pp1_it1[20] <= 1'b0;
ap_reg_ppstg_tmp_28_reg_5332_pp1_it1[21] <= 1'b0;
ap_reg_ppstg_tmp_28_reg_5332_pp1_it1[22] <= 1'b0;
ap_reg_ppstg_tmp_28_reg_5332_pp1_it1[23] <= 1'b0;
ap_reg_ppstg_tmp_28_reg_5332_pp1_it1[24] <= 1'b0;
ap_reg_ppstg_tmp_28_reg_5332_pp1_it1[25] <= 1'b0;
ap_reg_ppstg_tmp_28_reg_5332_pp1_it1[26] <= 1'b0;
ap_reg_ppstg_tmp_28_reg_5332_pp1_it1[27] <= 1'b0;
ap_reg_ppstg_tmp_28_reg_5332_pp1_it1[28] <= 1'b0;
ap_reg_ppstg_tmp_28_reg_5332_pp1_it1[29] <= 1'b0;
ap_reg_ppstg_tmp_28_reg_5332_pp1_it1[30] <= 1'b0;
ap_reg_ppstg_tmp_28_reg_5332_pp1_it1[31] <= 1'b0;
ap_reg_ppstg_tmp_28_reg_5332_pp1_it1[32] <= 1'b0;
ap_reg_ppstg_tmp_28_reg_5332_pp1_it1[33] <= 1'b0;
ap_reg_ppstg_tmp_28_reg_5332_pp1_it1[34] <= 1'b0;
ap_reg_ppstg_tmp_28_reg_5332_pp1_it1[35] <= 1'b0;
ap_reg_ppstg_tmp_28_reg_5332_pp1_it1[36] <= 1'b0;
ap_reg_ppstg_tmp_28_reg_5332_pp1_it1[37] <= 1'b0;
ap_reg_ppstg_tmp_28_reg_5332_pp1_it1[38] <= 1'b0;
ap_reg_ppstg_tmp_28_reg_5332_pp1_it1[39] <= 1'b0;
ap_reg_ppstg_tmp_28_reg_5332_pp1_it1[40] <= 1'b0;
ap_reg_ppstg_tmp_28_reg_5332_pp1_it1[41] <= 1'b0;
ap_reg_ppstg_tmp_28_reg_5332_pp1_it1[42] <= 1'b0;
ap_reg_ppstg_tmp_28_reg_5332_pp1_it1[43] <= 1'b0;
ap_reg_ppstg_tmp_28_reg_5332_pp1_it1[44] <= 1'b0;
ap_reg_ppstg_tmp_28_reg_5332_pp1_it1[45] <= 1'b0;
ap_reg_ppstg_tmp_28_reg_5332_pp1_it1[46] <= 1'b0;
ap_reg_ppstg_tmp_28_reg_5332_pp1_it1[47] <= 1'b0;
ap_reg_ppstg_tmp_28_reg_5332_pp1_it1[48] <= 1'b0;
ap_reg_ppstg_tmp_28_reg_5332_pp1_it1[49] <= 1'b0;
ap_reg_ppstg_tmp_28_reg_5332_pp1_it1[50] <= 1'b0;
ap_reg_ppstg_tmp_28_reg_5332_pp1_it1[51] <= 1'b0;
ap_reg_ppstg_tmp_28_reg_5332_pp1_it1[52] <= 1'b0;
ap_reg_ppstg_tmp_28_reg_5332_pp1_it1[53] <= 1'b0;
ap_reg_ppstg_tmp_28_reg_5332_pp1_it1[54] <= 1'b0;
ap_reg_ppstg_tmp_28_reg_5332_pp1_it1[55] <= 1'b0;
ap_reg_ppstg_tmp_28_reg_5332_pp1_it1[56] <= 1'b0;
ap_reg_ppstg_tmp_28_reg_5332_pp1_it1[57] <= 1'b0;
ap_reg_ppstg_tmp_28_reg_5332_pp1_it1[58] <= 1'b0;
ap_reg_ppstg_tmp_28_reg_5332_pp1_it1[59] <= 1'b0;
ap_reg_ppstg_tmp_28_reg_5332_pp1_it1[60] <= 1'b0;
ap_reg_ppstg_tmp_28_reg_5332_pp1_it1[61] <= 1'b0;
ap_reg_ppstg_tmp_28_reg_5332_pp1_it1[62] <= 1'b0;
ap_reg_ppstg_tmp_28_reg_5332_pp1_it1[63] <= 1'b0;
end
always @ (ap_clk)
begin
tmp_36_reg_5347[14] <= 1'b0;
tmp_36_reg_5347[15] <= 1'b0;
tmp_36_reg_5347[16] <= 1'b0;
tmp_36_reg_5347[17] <= 1'b0;
tmp_36_reg_5347[18] <= 1'b0;
tmp_36_reg_5347[19] <= 1'b0;
tmp_36_reg_5347[20] <= 1'b0;
tmp_36_reg_5347[21] <= 1'b0;
tmp_36_reg_5347[22] <= 1'b0;
tmp_36_reg_5347[23] <= 1'b0;
tmp_36_reg_5347[24] <= 1'b0;
tmp_36_reg_5347[25] <= 1'b0;
tmp_36_reg_5347[26] <= 1'b0;
tmp_36_reg_5347[27] <= 1'b0;
tmp_36_reg_5347[28] <= 1'b0;
tmp_36_reg_5347[29] <= 1'b0;
tmp_36_reg_5347[30] <= 1'b0;
tmp_36_reg_5347[31] <= 1'b0;
tmp_36_reg_5347[32] <= 1'b0;
tmp_36_reg_5347[33] <= 1'b0;
tmp_36_reg_5347[34] <= 1'b0;
tmp_36_reg_5347[35] <= 1'b0;
tmp_36_reg_5347[36] <= 1'b0;
tmp_36_reg_5347[37] <= 1'b0;
tmp_36_reg_5347[38] <= 1'b0;
tmp_36_reg_5347[39] <= 1'b0;
tmp_36_reg_5347[40] <= 1'b0;
tmp_36_reg_5347[41] <= 1'b0;
tmp_36_reg_5347[42] <= 1'b0;
tmp_36_reg_5347[43] <= 1'b0;
tmp_36_reg_5347[44] <= 1'b0;
tmp_36_reg_5347[45] <= 1'b0;
tmp_36_reg_5347[46] <= 1'b0;
tmp_36_reg_5347[47] <= 1'b0;
tmp_36_reg_5347[48] <= 1'b0;
tmp_36_reg_5347[49] <= 1'b0;
tmp_36_reg_5347[50] <= 1'b0;
tmp_36_reg_5347[51] <= 1'b0;
tmp_36_reg_5347[52] <= 1'b0;
tmp_36_reg_5347[53] <= 1'b0;
tmp_36_reg_5347[54] <= 1'b0;
tmp_36_reg_5347[55] <= 1'b0;
tmp_36_reg_5347[56] <= 1'b0;
tmp_36_reg_5347[57] <= 1'b0;
tmp_36_reg_5347[58] <= 1'b0;
tmp_36_reg_5347[59] <= 1'b0;
tmp_36_reg_5347[60] <= 1'b0;
tmp_36_reg_5347[61] <= 1'b0;
tmp_36_reg_5347[62] <= 1'b0;
tmp_36_reg_5347[63] <= 1'b0;
end
always @ (ap_clk)
begin
ap_reg_ppstg_tmp_36_reg_5347_pp1_it1[14] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_5347_pp1_it1[15] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_5347_pp1_it1[16] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_5347_pp1_it1[17] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_5347_pp1_it1[18] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_5347_pp1_it1[19] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_5347_pp1_it1[20] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_5347_pp1_it1[21] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_5347_pp1_it1[22] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_5347_pp1_it1[23] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_5347_pp1_it1[24] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_5347_pp1_it1[25] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_5347_pp1_it1[26] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_5347_pp1_it1[27] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_5347_pp1_it1[28] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_5347_pp1_it1[29] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_5347_pp1_it1[30] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_5347_pp1_it1[31] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_5347_pp1_it1[32] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_5347_pp1_it1[33] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_5347_pp1_it1[34] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_5347_pp1_it1[35] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_5347_pp1_it1[36] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_5347_pp1_it1[37] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_5347_pp1_it1[38] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_5347_pp1_it1[39] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_5347_pp1_it1[40] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_5347_pp1_it1[41] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_5347_pp1_it1[42] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_5347_pp1_it1[43] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_5347_pp1_it1[44] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_5347_pp1_it1[45] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_5347_pp1_it1[46] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_5347_pp1_it1[47] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_5347_pp1_it1[48] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_5347_pp1_it1[49] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_5347_pp1_it1[50] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_5347_pp1_it1[51] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_5347_pp1_it1[52] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_5347_pp1_it1[53] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_5347_pp1_it1[54] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_5347_pp1_it1[55] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_5347_pp1_it1[56] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_5347_pp1_it1[57] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_5347_pp1_it1[58] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_5347_pp1_it1[59] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_5347_pp1_it1[60] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_5347_pp1_it1[61] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_5347_pp1_it1[62] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_5347_pp1_it1[63] <= 1'b0;
end
always @ (ap_clk)
begin
b_addr8_reg_5357[2] <= 1'b1;
end
always @ (ap_clk)
begin
tmp_44_reg_5367[14] <= 1'b0;
tmp_44_reg_5367[15] <= 1'b0;
tmp_44_reg_5367[16] <= 1'b0;
tmp_44_reg_5367[17] <= 1'b0;
tmp_44_reg_5367[18] <= 1'b0;
tmp_44_reg_5367[19] <= 1'b0;
tmp_44_reg_5367[20] <= 1'b0;
tmp_44_reg_5367[21] <= 1'b0;
tmp_44_reg_5367[22] <= 1'b0;
tmp_44_reg_5367[23] <= 1'b0;
tmp_44_reg_5367[24] <= 1'b0;
tmp_44_reg_5367[25] <= 1'b0;
tmp_44_reg_5367[26] <= 1'b0;
tmp_44_reg_5367[27] <= 1'b0;
tmp_44_reg_5367[28] <= 1'b0;
tmp_44_reg_5367[29] <= 1'b0;
tmp_44_reg_5367[30] <= 1'b0;
tmp_44_reg_5367[31] <= 1'b0;
tmp_44_reg_5367[32] <= 1'b0;
tmp_44_reg_5367[33] <= 1'b0;
tmp_44_reg_5367[34] <= 1'b0;
tmp_44_reg_5367[35] <= 1'b0;
tmp_44_reg_5367[36] <= 1'b0;
tmp_44_reg_5367[37] <= 1'b0;
tmp_44_reg_5367[38] <= 1'b0;
tmp_44_reg_5367[39] <= 1'b0;
tmp_44_reg_5367[40] <= 1'b0;
tmp_44_reg_5367[41] <= 1'b0;
tmp_44_reg_5367[42] <= 1'b0;
tmp_44_reg_5367[43] <= 1'b0;
tmp_44_reg_5367[44] <= 1'b0;
tmp_44_reg_5367[45] <= 1'b0;
tmp_44_reg_5367[46] <= 1'b0;
tmp_44_reg_5367[47] <= 1'b0;
tmp_44_reg_5367[48] <= 1'b0;
tmp_44_reg_5367[49] <= 1'b0;
tmp_44_reg_5367[50] <= 1'b0;
tmp_44_reg_5367[51] <= 1'b0;
tmp_44_reg_5367[52] <= 1'b0;
tmp_44_reg_5367[53] <= 1'b0;
tmp_44_reg_5367[54] <= 1'b0;
tmp_44_reg_5367[55] <= 1'b0;
tmp_44_reg_5367[56] <= 1'b0;
tmp_44_reg_5367[57] <= 1'b0;
tmp_44_reg_5367[58] <= 1'b0;
tmp_44_reg_5367[59] <= 1'b0;
tmp_44_reg_5367[60] <= 1'b0;
tmp_44_reg_5367[61] <= 1'b0;
tmp_44_reg_5367[62] <= 1'b0;
tmp_44_reg_5367[63] <= 1'b0;
end
always @ (ap_clk)
begin
ap_reg_ppstg_tmp_44_reg_5367_pp1_it1[14] <= 1'b0;
ap_reg_ppstg_tmp_44_reg_5367_pp1_it1[15] <= 1'b0;
ap_reg_ppstg_tmp_44_reg_5367_pp1_it1[16] <= 1'b0;
ap_reg_ppstg_tmp_44_reg_5367_pp1_it1[17] <= 1'b0;
ap_reg_ppstg_tmp_44_reg_5367_pp1_it1[18] <= 1'b0;
ap_reg_ppstg_tmp_44_reg_5367_pp1_it1[19] <= 1'b0;
ap_reg_ppstg_tmp_44_reg_5367_pp1_it1[20] <= 1'b0;
ap_reg_ppstg_tmp_44_reg_5367_pp1_it1[21] <= 1'b0;
ap_reg_ppstg_tmp_44_reg_5367_pp1_it1[22] <= 1'b0;
ap_reg_ppstg_tmp_44_reg_5367_pp1_it1[23] <= 1'b0;
ap_reg_ppstg_tmp_44_reg_5367_pp1_it1[24] <= 1'b0;
ap_reg_ppstg_tmp_44_reg_5367_pp1_it1[25] <= 1'b0;
ap_reg_ppstg_tmp_44_reg_5367_pp1_it1[26] <= 1'b0;
ap_reg_ppstg_tmp_44_reg_5367_pp1_it1[27] <= 1'b0;
ap_reg_ppstg_tmp_44_reg_5367_pp1_it1[28] <= 1'b0;
ap_reg_ppstg_tmp_44_reg_5367_pp1_it1[29] <= 1'b0;
ap_reg_ppstg_tmp_44_reg_5367_pp1_it1[30] <= 1'b0;
ap_reg_ppstg_tmp_44_reg_5367_pp1_it1[31] <= 1'b0;
ap_reg_ppstg_tmp_44_reg_5367_pp1_it1[32] <= 1'b0;
ap_reg_ppstg_tmp_44_reg_5367_pp1_it1[33] <= 1'b0;
ap_reg_ppstg_tmp_44_reg_5367_pp1_it1[34] <= 1'b0;
ap_reg_ppstg_tmp_44_reg_5367_pp1_it1[35] <= 1'b0;
ap_reg_ppstg_tmp_44_reg_5367_pp1_it1[36] <= 1'b0;
ap_reg_ppstg_tmp_44_reg_5367_pp1_it1[37] <= 1'b0;
ap_reg_ppstg_tmp_44_reg_5367_pp1_it1[38] <= 1'b0;
ap_reg_ppstg_tmp_44_reg_5367_pp1_it1[39] <= 1'b0;
ap_reg_ppstg_tmp_44_reg_5367_pp1_it1[40] <= 1'b0;
ap_reg_ppstg_tmp_44_reg_5367_pp1_it1[41] <= 1'b0;
ap_reg_ppstg_tmp_44_reg_5367_pp1_it1[42] <= 1'b0;
ap_reg_ppstg_tmp_44_reg_5367_pp1_it1[43] <= 1'b0;
ap_reg_ppstg_tmp_44_reg_5367_pp1_it1[44] <= 1'b0;
ap_reg_ppstg_tmp_44_reg_5367_pp1_it1[45] <= 1'b0;
ap_reg_ppstg_tmp_44_reg_5367_pp1_it1[46] <= 1'b0;
ap_reg_ppstg_tmp_44_reg_5367_pp1_it1[47] <= 1'b0;
ap_reg_ppstg_tmp_44_reg_5367_pp1_it1[48] <= 1'b0;
ap_reg_ppstg_tmp_44_reg_5367_pp1_it1[49] <= 1'b0;
ap_reg_ppstg_tmp_44_reg_5367_pp1_it1[50] <= 1'b0;
ap_reg_ppstg_tmp_44_reg_5367_pp1_it1[51] <= 1'b0;
ap_reg_ppstg_tmp_44_reg_5367_pp1_it1[52] <= 1'b0;
ap_reg_ppstg_tmp_44_reg_5367_pp1_it1[53] <= 1'b0;
ap_reg_ppstg_tmp_44_reg_5367_pp1_it1[54] <= 1'b0;
ap_reg_ppstg_tmp_44_reg_5367_pp1_it1[55] <= 1'b0;
ap_reg_ppstg_tmp_44_reg_5367_pp1_it1[56] <= 1'b0;
ap_reg_ppstg_tmp_44_reg_5367_pp1_it1[57] <= 1'b0;
ap_reg_ppstg_tmp_44_reg_5367_pp1_it1[58] <= 1'b0;
ap_reg_ppstg_tmp_44_reg_5367_pp1_it1[59] <= 1'b0;
ap_reg_ppstg_tmp_44_reg_5367_pp1_it1[60] <= 1'b0;
ap_reg_ppstg_tmp_44_reg_5367_pp1_it1[61] <= 1'b0;
ap_reg_ppstg_tmp_44_reg_5367_pp1_it1[62] <= 1'b0;
ap_reg_ppstg_tmp_44_reg_5367_pp1_it1[63] <= 1'b0;
end
always @ (ap_clk)
begin
ap_reg_ppstg_tmp_44_reg_5367_pp1_it2[14] <= 1'b0;
ap_reg_ppstg_tmp_44_reg_5367_pp1_it2[15] <= 1'b0;
ap_reg_ppstg_tmp_44_reg_5367_pp1_it2[16] <= 1'b0;
ap_reg_ppstg_tmp_44_reg_5367_pp1_it2[17] <= 1'b0;
ap_reg_ppstg_tmp_44_reg_5367_pp1_it2[18] <= 1'b0;
ap_reg_ppstg_tmp_44_reg_5367_pp1_it2[19] <= 1'b0;
ap_reg_ppstg_tmp_44_reg_5367_pp1_it2[20] <= 1'b0;
ap_reg_ppstg_tmp_44_reg_5367_pp1_it2[21] <= 1'b0;
ap_reg_ppstg_tmp_44_reg_5367_pp1_it2[22] <= 1'b0;
ap_reg_ppstg_tmp_44_reg_5367_pp1_it2[23] <= 1'b0;
ap_reg_ppstg_tmp_44_reg_5367_pp1_it2[24] <= 1'b0;
ap_reg_ppstg_tmp_44_reg_5367_pp1_it2[25] <= 1'b0;
ap_reg_ppstg_tmp_44_reg_5367_pp1_it2[26] <= 1'b0;
ap_reg_ppstg_tmp_44_reg_5367_pp1_it2[27] <= 1'b0;
ap_reg_ppstg_tmp_44_reg_5367_pp1_it2[28] <= 1'b0;
ap_reg_ppstg_tmp_44_reg_5367_pp1_it2[29] <= 1'b0;
ap_reg_ppstg_tmp_44_reg_5367_pp1_it2[30] <= 1'b0;
ap_reg_ppstg_tmp_44_reg_5367_pp1_it2[31] <= 1'b0;
ap_reg_ppstg_tmp_44_reg_5367_pp1_it2[32] <= 1'b0;
ap_reg_ppstg_tmp_44_reg_5367_pp1_it2[33] <= 1'b0;
ap_reg_ppstg_tmp_44_reg_5367_pp1_it2[34] <= 1'b0;
ap_reg_ppstg_tmp_44_reg_5367_pp1_it2[35] <= 1'b0;
ap_reg_ppstg_tmp_44_reg_5367_pp1_it2[36] <= 1'b0;
ap_reg_ppstg_tmp_44_reg_5367_pp1_it2[37] <= 1'b0;
ap_reg_ppstg_tmp_44_reg_5367_pp1_it2[38] <= 1'b0;
ap_reg_ppstg_tmp_44_reg_5367_pp1_it2[39] <= 1'b0;
ap_reg_ppstg_tmp_44_reg_5367_pp1_it2[40] <= 1'b0;
ap_reg_ppstg_tmp_44_reg_5367_pp1_it2[41] <= 1'b0;
ap_reg_ppstg_tmp_44_reg_5367_pp1_it2[42] <= 1'b0;
ap_reg_ppstg_tmp_44_reg_5367_pp1_it2[43] <= 1'b0;
ap_reg_ppstg_tmp_44_reg_5367_pp1_it2[44] <= 1'b0;
ap_reg_ppstg_tmp_44_reg_5367_pp1_it2[45] <= 1'b0;
ap_reg_ppstg_tmp_44_reg_5367_pp1_it2[46] <= 1'b0;
ap_reg_ppstg_tmp_44_reg_5367_pp1_it2[47] <= 1'b0;
ap_reg_ppstg_tmp_44_reg_5367_pp1_it2[48] <= 1'b0;
ap_reg_ppstg_tmp_44_reg_5367_pp1_it2[49] <= 1'b0;
ap_reg_ppstg_tmp_44_reg_5367_pp1_it2[50] <= 1'b0;
ap_reg_ppstg_tmp_44_reg_5367_pp1_it2[51] <= 1'b0;
ap_reg_ppstg_tmp_44_reg_5367_pp1_it2[52] <= 1'b0;
ap_reg_ppstg_tmp_44_reg_5367_pp1_it2[53] <= 1'b0;
ap_reg_ppstg_tmp_44_reg_5367_pp1_it2[54] <= 1'b0;
ap_reg_ppstg_tmp_44_reg_5367_pp1_it2[55] <= 1'b0;
ap_reg_ppstg_tmp_44_reg_5367_pp1_it2[56] <= 1'b0;
ap_reg_ppstg_tmp_44_reg_5367_pp1_it2[57] <= 1'b0;
ap_reg_ppstg_tmp_44_reg_5367_pp1_it2[58] <= 1'b0;
ap_reg_ppstg_tmp_44_reg_5367_pp1_it2[59] <= 1'b0;
ap_reg_ppstg_tmp_44_reg_5367_pp1_it2[60] <= 1'b0;
ap_reg_ppstg_tmp_44_reg_5367_pp1_it2[61] <= 1'b0;
ap_reg_ppstg_tmp_44_reg_5367_pp1_it2[62] <= 1'b0;
ap_reg_ppstg_tmp_44_reg_5367_pp1_it2[63] <= 1'b0;
end
always @ (ap_clk)
begin
tmp_47_reg_5407[14] <= 1'b0;
tmp_47_reg_5407[15] <= 1'b0;
tmp_47_reg_5407[16] <= 1'b0;
tmp_47_reg_5407[17] <= 1'b0;
tmp_47_reg_5407[18] <= 1'b0;
tmp_47_reg_5407[19] <= 1'b0;
tmp_47_reg_5407[20] <= 1'b0;
tmp_47_reg_5407[21] <= 1'b0;
tmp_47_reg_5407[22] <= 1'b0;
tmp_47_reg_5407[23] <= 1'b0;
tmp_47_reg_5407[24] <= 1'b0;
tmp_47_reg_5407[25] <= 1'b0;
tmp_47_reg_5407[26] <= 1'b0;
tmp_47_reg_5407[27] <= 1'b0;
tmp_47_reg_5407[28] <= 1'b0;
tmp_47_reg_5407[29] <= 1'b0;
tmp_47_reg_5407[30] <= 1'b0;
tmp_47_reg_5407[31] <= 1'b0;
tmp_47_reg_5407[32] <= 1'b0;
tmp_47_reg_5407[33] <= 1'b0;
tmp_47_reg_5407[34] <= 1'b0;
tmp_47_reg_5407[35] <= 1'b0;
tmp_47_reg_5407[36] <= 1'b0;
tmp_47_reg_5407[37] <= 1'b0;
tmp_47_reg_5407[38] <= 1'b0;
tmp_47_reg_5407[39] <= 1'b0;
tmp_47_reg_5407[40] <= 1'b0;
tmp_47_reg_5407[41] <= 1'b0;
tmp_47_reg_5407[42] <= 1'b0;
tmp_47_reg_5407[43] <= 1'b0;
tmp_47_reg_5407[44] <= 1'b0;
tmp_47_reg_5407[45] <= 1'b0;
tmp_47_reg_5407[46] <= 1'b0;
tmp_47_reg_5407[47] <= 1'b0;
tmp_47_reg_5407[48] <= 1'b0;
tmp_47_reg_5407[49] <= 1'b0;
tmp_47_reg_5407[50] <= 1'b0;
tmp_47_reg_5407[51] <= 1'b0;
tmp_47_reg_5407[52] <= 1'b0;
tmp_47_reg_5407[53] <= 1'b0;
tmp_47_reg_5407[54] <= 1'b0;
tmp_47_reg_5407[55] <= 1'b0;
tmp_47_reg_5407[56] <= 1'b0;
tmp_47_reg_5407[57] <= 1'b0;
tmp_47_reg_5407[58] <= 1'b0;
tmp_47_reg_5407[59] <= 1'b0;
tmp_47_reg_5407[60] <= 1'b0;
tmp_47_reg_5407[61] <= 1'b0;
tmp_47_reg_5407[62] <= 1'b0;
tmp_47_reg_5407[63] <= 1'b0;
end
always @ (ap_clk)
begin
ap_reg_ppstg_tmp_47_reg_5407_pp1_it2[14] <= 1'b0;
ap_reg_ppstg_tmp_47_reg_5407_pp1_it2[15] <= 1'b0;
ap_reg_ppstg_tmp_47_reg_5407_pp1_it2[16] <= 1'b0;
ap_reg_ppstg_tmp_47_reg_5407_pp1_it2[17] <= 1'b0;
ap_reg_ppstg_tmp_47_reg_5407_pp1_it2[18] <= 1'b0;
ap_reg_ppstg_tmp_47_reg_5407_pp1_it2[19] <= 1'b0;
ap_reg_ppstg_tmp_47_reg_5407_pp1_it2[20] <= 1'b0;
ap_reg_ppstg_tmp_47_reg_5407_pp1_it2[21] <= 1'b0;
ap_reg_ppstg_tmp_47_reg_5407_pp1_it2[22] <= 1'b0;
ap_reg_ppstg_tmp_47_reg_5407_pp1_it2[23] <= 1'b0;
ap_reg_ppstg_tmp_47_reg_5407_pp1_it2[24] <= 1'b0;
ap_reg_ppstg_tmp_47_reg_5407_pp1_it2[25] <= 1'b0;
ap_reg_ppstg_tmp_47_reg_5407_pp1_it2[26] <= 1'b0;
ap_reg_ppstg_tmp_47_reg_5407_pp1_it2[27] <= 1'b0;
ap_reg_ppstg_tmp_47_reg_5407_pp1_it2[28] <= 1'b0;
ap_reg_ppstg_tmp_47_reg_5407_pp1_it2[29] <= 1'b0;
ap_reg_ppstg_tmp_47_reg_5407_pp1_it2[30] <= 1'b0;
ap_reg_ppstg_tmp_47_reg_5407_pp1_it2[31] <= 1'b0;
ap_reg_ppstg_tmp_47_reg_5407_pp1_it2[32] <= 1'b0;
ap_reg_ppstg_tmp_47_reg_5407_pp1_it2[33] <= 1'b0;
ap_reg_ppstg_tmp_47_reg_5407_pp1_it2[34] <= 1'b0;
ap_reg_ppstg_tmp_47_reg_5407_pp1_it2[35] <= 1'b0;
ap_reg_ppstg_tmp_47_reg_5407_pp1_it2[36] <= 1'b0;
ap_reg_ppstg_tmp_47_reg_5407_pp1_it2[37] <= 1'b0;
ap_reg_ppstg_tmp_47_reg_5407_pp1_it2[38] <= 1'b0;
ap_reg_ppstg_tmp_47_reg_5407_pp1_it2[39] <= 1'b0;
ap_reg_ppstg_tmp_47_reg_5407_pp1_it2[40] <= 1'b0;
ap_reg_ppstg_tmp_47_reg_5407_pp1_it2[41] <= 1'b0;
ap_reg_ppstg_tmp_47_reg_5407_pp1_it2[42] <= 1'b0;
ap_reg_ppstg_tmp_47_reg_5407_pp1_it2[43] <= 1'b0;
ap_reg_ppstg_tmp_47_reg_5407_pp1_it2[44] <= 1'b0;
ap_reg_ppstg_tmp_47_reg_5407_pp1_it2[45] <= 1'b0;
ap_reg_ppstg_tmp_47_reg_5407_pp1_it2[46] <= 1'b0;
ap_reg_ppstg_tmp_47_reg_5407_pp1_it2[47] <= 1'b0;
ap_reg_ppstg_tmp_47_reg_5407_pp1_it2[48] <= 1'b0;
ap_reg_ppstg_tmp_47_reg_5407_pp1_it2[49] <= 1'b0;
ap_reg_ppstg_tmp_47_reg_5407_pp1_it2[50] <= 1'b0;
ap_reg_ppstg_tmp_47_reg_5407_pp1_it2[51] <= 1'b0;
ap_reg_ppstg_tmp_47_reg_5407_pp1_it2[52] <= 1'b0;
ap_reg_ppstg_tmp_47_reg_5407_pp1_it2[53] <= 1'b0;
ap_reg_ppstg_tmp_47_reg_5407_pp1_it2[54] <= 1'b0;
ap_reg_ppstg_tmp_47_reg_5407_pp1_it2[55] <= 1'b0;
ap_reg_ppstg_tmp_47_reg_5407_pp1_it2[56] <= 1'b0;
ap_reg_ppstg_tmp_47_reg_5407_pp1_it2[57] <= 1'b0;
ap_reg_ppstg_tmp_47_reg_5407_pp1_it2[58] <= 1'b0;
ap_reg_ppstg_tmp_47_reg_5407_pp1_it2[59] <= 1'b0;
ap_reg_ppstg_tmp_47_reg_5407_pp1_it2[60] <= 1'b0;
ap_reg_ppstg_tmp_47_reg_5407_pp1_it2[61] <= 1'b0;
ap_reg_ppstg_tmp_47_reg_5407_pp1_it2[62] <= 1'b0;
ap_reg_ppstg_tmp_47_reg_5407_pp1_it2[63] <= 1'b0;
end
always @ (ap_clk)
begin
tmp_51_reg_5417[14] <= 1'b0;
tmp_51_reg_5417[15] <= 1'b0;
tmp_51_reg_5417[16] <= 1'b0;
tmp_51_reg_5417[17] <= 1'b0;
tmp_51_reg_5417[18] <= 1'b0;
tmp_51_reg_5417[19] <= 1'b0;
tmp_51_reg_5417[20] <= 1'b0;
tmp_51_reg_5417[21] <= 1'b0;
tmp_51_reg_5417[22] <= 1'b0;
tmp_51_reg_5417[23] <= 1'b0;
tmp_51_reg_5417[24] <= 1'b0;
tmp_51_reg_5417[25] <= 1'b0;
tmp_51_reg_5417[26] <= 1'b0;
tmp_51_reg_5417[27] <= 1'b0;
tmp_51_reg_5417[28] <= 1'b0;
tmp_51_reg_5417[29] <= 1'b0;
tmp_51_reg_5417[30] <= 1'b0;
tmp_51_reg_5417[31] <= 1'b0;
tmp_51_reg_5417[32] <= 1'b0;
tmp_51_reg_5417[33] <= 1'b0;
tmp_51_reg_5417[34] <= 1'b0;
tmp_51_reg_5417[35] <= 1'b0;
tmp_51_reg_5417[36] <= 1'b0;
tmp_51_reg_5417[37] <= 1'b0;
tmp_51_reg_5417[38] <= 1'b0;
tmp_51_reg_5417[39] <= 1'b0;
tmp_51_reg_5417[40] <= 1'b0;
tmp_51_reg_5417[41] <= 1'b0;
tmp_51_reg_5417[42] <= 1'b0;
tmp_51_reg_5417[43] <= 1'b0;
tmp_51_reg_5417[44] <= 1'b0;
tmp_51_reg_5417[45] <= 1'b0;
tmp_51_reg_5417[46] <= 1'b0;
tmp_51_reg_5417[47] <= 1'b0;
tmp_51_reg_5417[48] <= 1'b0;
tmp_51_reg_5417[49] <= 1'b0;
tmp_51_reg_5417[50] <= 1'b0;
tmp_51_reg_5417[51] <= 1'b0;
tmp_51_reg_5417[52] <= 1'b0;
tmp_51_reg_5417[53] <= 1'b0;
tmp_51_reg_5417[54] <= 1'b0;
tmp_51_reg_5417[55] <= 1'b0;
tmp_51_reg_5417[56] <= 1'b0;
tmp_51_reg_5417[57] <= 1'b0;
tmp_51_reg_5417[58] <= 1'b0;
tmp_51_reg_5417[59] <= 1'b0;
tmp_51_reg_5417[60] <= 1'b0;
tmp_51_reg_5417[61] <= 1'b0;
tmp_51_reg_5417[62] <= 1'b0;
tmp_51_reg_5417[63] <= 1'b0;
end
always @ (ap_clk)
begin
ap_reg_ppstg_tmp_51_reg_5417_pp1_it2[14] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_5417_pp1_it2[15] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_5417_pp1_it2[16] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_5417_pp1_it2[17] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_5417_pp1_it2[18] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_5417_pp1_it2[19] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_5417_pp1_it2[20] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_5417_pp1_it2[21] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_5417_pp1_it2[22] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_5417_pp1_it2[23] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_5417_pp1_it2[24] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_5417_pp1_it2[25] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_5417_pp1_it2[26] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_5417_pp1_it2[27] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_5417_pp1_it2[28] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_5417_pp1_it2[29] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_5417_pp1_it2[30] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_5417_pp1_it2[31] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_5417_pp1_it2[32] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_5417_pp1_it2[33] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_5417_pp1_it2[34] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_5417_pp1_it2[35] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_5417_pp1_it2[36] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_5417_pp1_it2[37] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_5417_pp1_it2[38] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_5417_pp1_it2[39] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_5417_pp1_it2[40] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_5417_pp1_it2[41] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_5417_pp1_it2[42] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_5417_pp1_it2[43] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_5417_pp1_it2[44] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_5417_pp1_it2[45] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_5417_pp1_it2[46] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_5417_pp1_it2[47] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_5417_pp1_it2[48] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_5417_pp1_it2[49] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_5417_pp1_it2[50] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_5417_pp1_it2[51] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_5417_pp1_it2[52] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_5417_pp1_it2[53] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_5417_pp1_it2[54] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_5417_pp1_it2[55] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_5417_pp1_it2[56] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_5417_pp1_it2[57] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_5417_pp1_it2[58] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_5417_pp1_it2[59] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_5417_pp1_it2[60] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_5417_pp1_it2[61] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_5417_pp1_it2[62] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_5417_pp1_it2[63] <= 1'b0;
end
always @ (ap_clk)
begin
tmp_59_reg_5436[13] <= 1'b0;
tmp_59_reg_5436[14] <= 1'b0;
tmp_59_reg_5436[15] <= 1'b0;
tmp_59_reg_5436[16] <= 1'b0;
tmp_59_reg_5436[17] <= 1'b0;
tmp_59_reg_5436[18] <= 1'b0;
tmp_59_reg_5436[19] <= 1'b0;
tmp_59_reg_5436[20] <= 1'b0;
tmp_59_reg_5436[21] <= 1'b0;
tmp_59_reg_5436[22] <= 1'b0;
tmp_59_reg_5436[23] <= 1'b0;
tmp_59_reg_5436[24] <= 1'b0;
tmp_59_reg_5436[25] <= 1'b0;
tmp_59_reg_5436[26] <= 1'b0;
tmp_59_reg_5436[27] <= 1'b0;
tmp_59_reg_5436[28] <= 1'b0;
tmp_59_reg_5436[29] <= 1'b0;
tmp_59_reg_5436[30] <= 1'b0;
tmp_59_reg_5436[31] <= 1'b0;
tmp_59_reg_5436[32] <= 1'b0;
tmp_59_reg_5436[33] <= 1'b0;
tmp_59_reg_5436[34] <= 1'b0;
tmp_59_reg_5436[35] <= 1'b0;
tmp_59_reg_5436[36] <= 1'b0;
tmp_59_reg_5436[37] <= 1'b0;
tmp_59_reg_5436[38] <= 1'b0;
tmp_59_reg_5436[39] <= 1'b0;
tmp_59_reg_5436[40] <= 1'b0;
tmp_59_reg_5436[41] <= 1'b0;
tmp_59_reg_5436[42] <= 1'b0;
tmp_59_reg_5436[43] <= 1'b0;
tmp_59_reg_5436[44] <= 1'b0;
tmp_59_reg_5436[45] <= 1'b0;
tmp_59_reg_5436[46] <= 1'b0;
tmp_59_reg_5436[47] <= 1'b0;
tmp_59_reg_5436[48] <= 1'b0;
tmp_59_reg_5436[49] <= 1'b0;
tmp_59_reg_5436[50] <= 1'b0;
tmp_59_reg_5436[51] <= 1'b0;
tmp_59_reg_5436[52] <= 1'b0;
tmp_59_reg_5436[53] <= 1'b0;
tmp_59_reg_5436[54] <= 1'b0;
tmp_59_reg_5436[55] <= 1'b0;
tmp_59_reg_5436[56] <= 1'b0;
tmp_59_reg_5436[57] <= 1'b0;
tmp_59_reg_5436[58] <= 1'b0;
tmp_59_reg_5436[59] <= 1'b0;
tmp_59_reg_5436[60] <= 1'b0;
tmp_59_reg_5436[61] <= 1'b0;
tmp_59_reg_5436[62] <= 1'b0;
tmp_59_reg_5436[63] <= 1'b0;
end
always @ (ap_clk)
begin
ap_reg_ppstg_tmp_59_reg_5436_pp2_it1[13] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it1[14] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it1[15] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it1[16] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it1[17] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it1[18] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it1[19] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it1[20] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it1[21] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it1[22] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it1[23] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it1[24] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it1[25] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it1[26] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it1[27] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it1[28] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it1[29] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it1[30] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it1[31] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it1[32] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it1[33] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it1[34] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it1[35] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it1[36] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it1[37] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it1[38] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it1[39] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it1[40] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it1[41] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it1[42] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it1[43] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it1[44] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it1[45] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it1[46] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it1[47] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it1[48] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it1[49] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it1[50] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it1[51] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it1[52] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it1[53] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it1[54] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it1[55] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it1[56] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it1[57] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it1[58] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it1[59] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it1[60] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it1[61] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it1[62] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it1[63] <= 1'b0;
end
always @ (ap_clk)
begin
ap_reg_ppstg_tmp_59_reg_5436_pp2_it2[13] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it2[14] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it2[15] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it2[16] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it2[17] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it2[18] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it2[19] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it2[20] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it2[21] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it2[22] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it2[23] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it2[24] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it2[25] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it2[26] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it2[27] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it2[28] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it2[29] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it2[30] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it2[31] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it2[32] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it2[33] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it2[34] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it2[35] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it2[36] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it2[37] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it2[38] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it2[39] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it2[40] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it2[41] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it2[42] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it2[43] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it2[44] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it2[45] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it2[46] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it2[47] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it2[48] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it2[49] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it2[50] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it2[51] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it2[52] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it2[53] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it2[54] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it2[55] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it2[56] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it2[57] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it2[58] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it2[59] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it2[60] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it2[61] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it2[62] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it2[63] <= 1'b0;
end
always @ (ap_clk)
begin
ap_reg_ppstg_tmp_59_reg_5436_pp2_it3[13] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it3[14] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it3[15] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it3[16] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it3[17] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it3[18] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it3[19] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it3[20] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it3[21] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it3[22] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it3[23] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it3[24] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it3[25] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it3[26] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it3[27] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it3[28] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it3[29] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it3[30] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it3[31] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it3[32] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it3[33] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it3[34] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it3[35] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it3[36] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it3[37] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it3[38] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it3[39] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it3[40] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it3[41] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it3[42] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it3[43] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it3[44] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it3[45] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it3[46] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it3[47] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it3[48] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it3[49] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it3[50] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it3[51] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it3[52] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it3[53] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it3[54] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it3[55] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it3[56] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it3[57] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it3[58] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it3[59] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it3[60] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it3[61] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it3[62] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it3[63] <= 1'b0;
end
always @ (ap_clk)
begin
ap_reg_ppstg_tmp_59_reg_5436_pp2_it4[13] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it4[14] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it4[15] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it4[16] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it4[17] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it4[18] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it4[19] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it4[20] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it4[21] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it4[22] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it4[23] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it4[24] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it4[25] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it4[26] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it4[27] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it4[28] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it4[29] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it4[30] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it4[31] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it4[32] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it4[33] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it4[34] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it4[35] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it4[36] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it4[37] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it4[38] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it4[39] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it4[40] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it4[41] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it4[42] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it4[43] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it4[44] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it4[45] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it4[46] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it4[47] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it4[48] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it4[49] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it4[50] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it4[51] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it4[52] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it4[53] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it4[54] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it4[55] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it4[56] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it4[57] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it4[58] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it4[59] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it4[60] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it4[61] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it4[62] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it4[63] <= 1'b0;
end
always @ (ap_clk)
begin
ap_reg_ppstg_tmp_59_reg_5436_pp2_it5[13] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it5[14] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it5[15] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it5[16] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it5[17] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it5[18] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it5[19] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it5[20] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it5[21] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it5[22] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it5[23] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it5[24] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it5[25] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it5[26] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it5[27] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it5[28] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it5[29] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it5[30] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it5[31] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it5[32] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it5[33] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it5[34] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it5[35] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it5[36] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it5[37] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it5[38] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it5[39] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it5[40] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it5[41] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it5[42] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it5[43] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it5[44] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it5[45] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it5[46] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it5[47] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it5[48] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it5[49] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it5[50] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it5[51] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it5[52] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it5[53] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it5[54] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it5[55] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it5[56] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it5[57] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it5[58] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it5[59] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it5[60] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it5[61] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it5[62] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it5[63] <= 1'b0;
end
always @ (ap_clk)
begin
tmp_46_trn_cast_reg_5508[6] <= 1'b0;
tmp_46_trn_cast_reg_5508[7] <= 1'b0;
tmp_46_trn_cast_reg_5508[8] <= 1'b0;
tmp_46_trn_cast_reg_5508[9] <= 1'b0;
tmp_46_trn_cast_reg_5508[10] <= 1'b0;
tmp_46_trn_cast_reg_5508[11] <= 1'b0;
tmp_46_trn_cast_reg_5508[12] <= 1'b0;
end
always @ (ap_clk)
begin
a_addr112_reg_5548[1] <= 1'b1;
end
always @ (ap_clk)
begin
a_addr116_reg_5608[2] <= 1'b1;
end
always @ (ap_clk)
begin
tmp_122_reg_5687[7] <= 1'b0;
tmp_122_reg_5687[8] <= 1'b0;
tmp_122_reg_5687[9] <= 1'b0;
tmp_122_reg_5687[10] <= 1'b0;
tmp_122_reg_5687[11] <= 1'b0;
tmp_122_reg_5687[12] <= 1'b0;
tmp_122_reg_5687[13] <= 1'b0;
tmp_122_reg_5687[14] <= 1'b0;
tmp_122_reg_5687[15] <= 1'b0;
tmp_122_reg_5687[16] <= 1'b0;
tmp_122_reg_5687[17] <= 1'b0;
tmp_122_reg_5687[18] <= 1'b0;
tmp_122_reg_5687[19] <= 1'b0;
tmp_122_reg_5687[20] <= 1'b0;
tmp_122_reg_5687[21] <= 1'b0;
tmp_122_reg_5687[22] <= 1'b0;
tmp_122_reg_5687[23] <= 1'b0;
tmp_122_reg_5687[24] <= 1'b0;
tmp_122_reg_5687[25] <= 1'b0;
tmp_122_reg_5687[26] <= 1'b0;
tmp_122_reg_5687[27] <= 1'b0;
tmp_122_reg_5687[28] <= 1'b0;
tmp_122_reg_5687[29] <= 1'b0;
tmp_122_reg_5687[30] <= 1'b0;
tmp_122_reg_5687[31] <= 1'b0;
tmp_122_reg_5687[32] <= 1'b0;
tmp_122_reg_5687[33] <= 1'b0;
tmp_122_reg_5687[34] <= 1'b0;
tmp_122_reg_5687[35] <= 1'b0;
tmp_122_reg_5687[36] <= 1'b0;
tmp_122_reg_5687[37] <= 1'b0;
tmp_122_reg_5687[38] <= 1'b0;
tmp_122_reg_5687[39] <= 1'b0;
tmp_122_reg_5687[40] <= 1'b0;
tmp_122_reg_5687[41] <= 1'b0;
tmp_122_reg_5687[42] <= 1'b0;
tmp_122_reg_5687[43] <= 1'b0;
tmp_122_reg_5687[44] <= 1'b0;
tmp_122_reg_5687[45] <= 1'b0;
tmp_122_reg_5687[46] <= 1'b0;
tmp_122_reg_5687[47] <= 1'b0;
tmp_122_reg_5687[48] <= 1'b0;
tmp_122_reg_5687[49] <= 1'b0;
tmp_122_reg_5687[50] <= 1'b0;
tmp_122_reg_5687[51] <= 1'b0;
tmp_122_reg_5687[52] <= 1'b0;
tmp_122_reg_5687[53] <= 1'b0;
tmp_122_reg_5687[54] <= 1'b0;
tmp_122_reg_5687[55] <= 1'b0;
tmp_122_reg_5687[56] <= 1'b0;
tmp_122_reg_5687[57] <= 1'b0;
tmp_122_reg_5687[58] <= 1'b0;
tmp_122_reg_5687[59] <= 1'b0;
tmp_122_reg_5687[60] <= 1'b0;
tmp_122_reg_5687[61] <= 1'b0;
tmp_122_reg_5687[62] <= 1'b0;
tmp_122_reg_5687[63] <= 1'b0;
end
always @ (ap_clk)
begin
ap_reg_ppstg_tmp_122_reg_5687_pp4_it1[7] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it1[8] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it1[9] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it1[10] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it1[11] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it1[12] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it1[13] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it1[14] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it1[15] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it1[16] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it1[17] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it1[18] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it1[19] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it1[20] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it1[21] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it1[22] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it1[23] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it1[24] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it1[25] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it1[26] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it1[27] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it1[28] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it1[29] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it1[30] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it1[31] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it1[32] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it1[33] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it1[34] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it1[35] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it1[36] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it1[37] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it1[38] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it1[39] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it1[40] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it1[41] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it1[42] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it1[43] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it1[44] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it1[45] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it1[46] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it1[47] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it1[48] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it1[49] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it1[50] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it1[51] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it1[52] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it1[53] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it1[54] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it1[55] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it1[56] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it1[57] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it1[58] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it1[59] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it1[60] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it1[61] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it1[62] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it1[63] <= 1'b0;
end
always @ (ap_clk)
begin
ap_reg_ppstg_tmp_122_reg_5687_pp4_it2[7] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it2[8] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it2[9] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it2[10] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it2[11] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it2[12] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it2[13] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it2[14] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it2[15] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it2[16] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it2[17] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it2[18] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it2[19] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it2[20] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it2[21] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it2[22] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it2[23] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it2[24] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it2[25] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it2[26] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it2[27] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it2[28] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it2[29] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it2[30] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it2[31] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it2[32] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it2[33] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it2[34] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it2[35] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it2[36] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it2[37] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it2[38] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it2[39] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it2[40] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it2[41] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it2[42] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it2[43] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it2[44] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it2[45] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it2[46] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it2[47] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it2[48] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it2[49] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it2[50] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it2[51] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it2[52] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it2[53] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it2[54] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it2[55] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it2[56] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it2[57] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it2[58] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it2[59] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it2[60] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it2[61] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it2[62] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it2[63] <= 1'b0;
end
always @ (ap_clk)
begin
ap_reg_ppstg_tmp_122_reg_5687_pp4_it3[7] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it3[8] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it3[9] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it3[10] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it3[11] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it3[12] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it3[13] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it3[14] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it3[15] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it3[16] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it3[17] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it3[18] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it3[19] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it3[20] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it3[21] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it3[22] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it3[23] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it3[24] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it3[25] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it3[26] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it3[27] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it3[28] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it3[29] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it3[30] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it3[31] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it3[32] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it3[33] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it3[34] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it3[35] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it3[36] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it3[37] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it3[38] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it3[39] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it3[40] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it3[41] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it3[42] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it3[43] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it3[44] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it3[45] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it3[46] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it3[47] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it3[48] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it3[49] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it3[50] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it3[51] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it3[52] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it3[53] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it3[54] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it3[55] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it3[56] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it3[57] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it3[58] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it3[59] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it3[60] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it3[61] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it3[62] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it3[63] <= 1'b0;
end
always @ (ap_clk)
begin
ap_reg_ppstg_tmp_122_reg_5687_pp4_it4[7] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it4[8] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it4[9] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it4[10] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it4[11] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it4[12] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it4[13] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it4[14] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it4[15] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it4[16] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it4[17] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it4[18] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it4[19] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it4[20] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it4[21] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it4[22] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it4[23] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it4[24] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it4[25] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it4[26] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it4[27] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it4[28] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it4[29] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it4[30] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it4[31] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it4[32] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it4[33] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it4[34] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it4[35] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it4[36] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it4[37] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it4[38] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it4[39] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it4[40] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it4[41] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it4[42] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it4[43] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it4[44] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it4[45] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it4[46] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it4[47] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it4[48] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it4[49] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it4[50] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it4[51] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it4[52] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it4[53] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it4[54] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it4[55] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it4[56] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it4[57] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it4[58] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it4[59] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it4[60] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it4[61] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it4[62] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it4[63] <= 1'b0;
end
always @ (ap_clk)
begin
ap_reg_ppstg_tmp_122_reg_5687_pp4_it5[7] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it5[8] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it5[9] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it5[10] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it5[11] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it5[12] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it5[13] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it5[14] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it5[15] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it5[16] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it5[17] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it5[18] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it5[19] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it5[20] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it5[21] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it5[22] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it5[23] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it5[24] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it5[25] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it5[26] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it5[27] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it5[28] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it5[29] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it5[30] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it5[31] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it5[32] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it5[33] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it5[34] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it5[35] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it5[36] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it5[37] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it5[38] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it5[39] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it5[40] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it5[41] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it5[42] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it5[43] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it5[44] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it5[45] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it5[46] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it5[47] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it5[48] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it5[49] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it5[50] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it5[51] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it5[52] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it5[53] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it5[54] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it5[55] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it5[56] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it5[57] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it5[58] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it5[59] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it5[60] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it5[61] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it5[62] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it5[63] <= 1'b0;
end
always @ (ap_clk)
begin
a_addr37_cast_reg_5729[0] <= 1'b0;
a_addr37_cast_reg_5729[1] <= 1'b0;
a_addr37_cast_reg_5729[2] <= 1'b0;
a_addr37_cast_reg_5729[3] <= 1'b0;
a_addr37_cast_reg_5729[4] <= 1'b0;
a_addr37_cast_reg_5729[5] <= 1'b0;
a_addr37_cast_reg_5729[13] <= 1'b0;
end
always @ (ap_clk)
begin
ap_reg_ppstg_a_addr37_cast_reg_5729_pp5_it1[0] <= 1'b0;
ap_reg_ppstg_a_addr37_cast_reg_5729_pp5_it1[1] <= 1'b0;
ap_reg_ppstg_a_addr37_cast_reg_5729_pp5_it1[2] <= 1'b0;
ap_reg_ppstg_a_addr37_cast_reg_5729_pp5_it1[3] <= 1'b0;
ap_reg_ppstg_a_addr37_cast_reg_5729_pp5_it1[4] <= 1'b0;
ap_reg_ppstg_a_addr37_cast_reg_5729_pp5_it1[5] <= 1'b0;
ap_reg_ppstg_a_addr37_cast_reg_5729_pp5_it1[13] <= 1'b0;
end
always @ (ap_clk)
begin
tmp_125_reg_5740[14] <= 1'b0;
tmp_125_reg_5740[15] <= 1'b0;
tmp_125_reg_5740[16] <= 1'b0;
tmp_125_reg_5740[17] <= 1'b0;
tmp_125_reg_5740[18] <= 1'b0;
tmp_125_reg_5740[19] <= 1'b0;
tmp_125_reg_5740[20] <= 1'b0;
tmp_125_reg_5740[21] <= 1'b0;
tmp_125_reg_5740[22] <= 1'b0;
tmp_125_reg_5740[23] <= 1'b0;
tmp_125_reg_5740[24] <= 1'b0;
tmp_125_reg_5740[25] <= 1'b0;
tmp_125_reg_5740[26] <= 1'b0;
tmp_125_reg_5740[27] <= 1'b0;
tmp_125_reg_5740[28] <= 1'b0;
tmp_125_reg_5740[29] <= 1'b0;
tmp_125_reg_5740[30] <= 1'b0;
tmp_125_reg_5740[31] <= 1'b0;
tmp_125_reg_5740[32] <= 1'b0;
tmp_125_reg_5740[33] <= 1'b0;
tmp_125_reg_5740[34] <= 1'b0;
tmp_125_reg_5740[35] <= 1'b0;
tmp_125_reg_5740[36] <= 1'b0;
tmp_125_reg_5740[37] <= 1'b0;
tmp_125_reg_5740[38] <= 1'b0;
tmp_125_reg_5740[39] <= 1'b0;
tmp_125_reg_5740[40] <= 1'b0;
tmp_125_reg_5740[41] <= 1'b0;
tmp_125_reg_5740[42] <= 1'b0;
tmp_125_reg_5740[43] <= 1'b0;
tmp_125_reg_5740[44] <= 1'b0;
tmp_125_reg_5740[45] <= 1'b0;
tmp_125_reg_5740[46] <= 1'b0;
tmp_125_reg_5740[47] <= 1'b0;
tmp_125_reg_5740[48] <= 1'b0;
tmp_125_reg_5740[49] <= 1'b0;
tmp_125_reg_5740[50] <= 1'b0;
tmp_125_reg_5740[51] <= 1'b0;
tmp_125_reg_5740[52] <= 1'b0;
tmp_125_reg_5740[53] <= 1'b0;
tmp_125_reg_5740[54] <= 1'b0;
tmp_125_reg_5740[55] <= 1'b0;
tmp_125_reg_5740[56] <= 1'b0;
tmp_125_reg_5740[57] <= 1'b0;
tmp_125_reg_5740[58] <= 1'b0;
tmp_125_reg_5740[59] <= 1'b0;
tmp_125_reg_5740[60] <= 1'b0;
tmp_125_reg_5740[61] <= 1'b0;
tmp_125_reg_5740[62] <= 1'b0;
tmp_125_reg_5740[63] <= 1'b0;
end
always @ (ap_clk)
begin
ap_reg_ppstg_tmp_125_reg_5740_pp5_it1[14] <= 1'b0;
ap_reg_ppstg_tmp_125_reg_5740_pp5_it1[15] <= 1'b0;
ap_reg_ppstg_tmp_125_reg_5740_pp5_it1[16] <= 1'b0;
ap_reg_ppstg_tmp_125_reg_5740_pp5_it1[17] <= 1'b0;
ap_reg_ppstg_tmp_125_reg_5740_pp5_it1[18] <= 1'b0;
ap_reg_ppstg_tmp_125_reg_5740_pp5_it1[19] <= 1'b0;
ap_reg_ppstg_tmp_125_reg_5740_pp5_it1[20] <= 1'b0;
ap_reg_ppstg_tmp_125_reg_5740_pp5_it1[21] <= 1'b0;
ap_reg_ppstg_tmp_125_reg_5740_pp5_it1[22] <= 1'b0;
ap_reg_ppstg_tmp_125_reg_5740_pp5_it1[23] <= 1'b0;
ap_reg_ppstg_tmp_125_reg_5740_pp5_it1[24] <= 1'b0;
ap_reg_ppstg_tmp_125_reg_5740_pp5_it1[25] <= 1'b0;
ap_reg_ppstg_tmp_125_reg_5740_pp5_it1[26] <= 1'b0;
ap_reg_ppstg_tmp_125_reg_5740_pp5_it1[27] <= 1'b0;
ap_reg_ppstg_tmp_125_reg_5740_pp5_it1[28] <= 1'b0;
ap_reg_ppstg_tmp_125_reg_5740_pp5_it1[29] <= 1'b0;
ap_reg_ppstg_tmp_125_reg_5740_pp5_it1[30] <= 1'b0;
ap_reg_ppstg_tmp_125_reg_5740_pp5_it1[31] <= 1'b0;
ap_reg_ppstg_tmp_125_reg_5740_pp5_it1[32] <= 1'b0;
ap_reg_ppstg_tmp_125_reg_5740_pp5_it1[33] <= 1'b0;
ap_reg_ppstg_tmp_125_reg_5740_pp5_it1[34] <= 1'b0;
ap_reg_ppstg_tmp_125_reg_5740_pp5_it1[35] <= 1'b0;
ap_reg_ppstg_tmp_125_reg_5740_pp5_it1[36] <= 1'b0;
ap_reg_ppstg_tmp_125_reg_5740_pp5_it1[37] <= 1'b0;
ap_reg_ppstg_tmp_125_reg_5740_pp5_it1[38] <= 1'b0;
ap_reg_ppstg_tmp_125_reg_5740_pp5_it1[39] <= 1'b0;
ap_reg_ppstg_tmp_125_reg_5740_pp5_it1[40] <= 1'b0;
ap_reg_ppstg_tmp_125_reg_5740_pp5_it1[41] <= 1'b0;
ap_reg_ppstg_tmp_125_reg_5740_pp5_it1[42] <= 1'b0;
ap_reg_ppstg_tmp_125_reg_5740_pp5_it1[43] <= 1'b0;
ap_reg_ppstg_tmp_125_reg_5740_pp5_it1[44] <= 1'b0;
ap_reg_ppstg_tmp_125_reg_5740_pp5_it1[45] <= 1'b0;
ap_reg_ppstg_tmp_125_reg_5740_pp5_it1[46] <= 1'b0;
ap_reg_ppstg_tmp_125_reg_5740_pp5_it1[47] <= 1'b0;
ap_reg_ppstg_tmp_125_reg_5740_pp5_it1[48] <= 1'b0;
ap_reg_ppstg_tmp_125_reg_5740_pp5_it1[49] <= 1'b0;
ap_reg_ppstg_tmp_125_reg_5740_pp5_it1[50] <= 1'b0;
ap_reg_ppstg_tmp_125_reg_5740_pp5_it1[51] <= 1'b0;
ap_reg_ppstg_tmp_125_reg_5740_pp5_it1[52] <= 1'b0;
ap_reg_ppstg_tmp_125_reg_5740_pp5_it1[53] <= 1'b0;
ap_reg_ppstg_tmp_125_reg_5740_pp5_it1[54] <= 1'b0;
ap_reg_ppstg_tmp_125_reg_5740_pp5_it1[55] <= 1'b0;
ap_reg_ppstg_tmp_125_reg_5740_pp5_it1[56] <= 1'b0;
ap_reg_ppstg_tmp_125_reg_5740_pp5_it1[57] <= 1'b0;
ap_reg_ppstg_tmp_125_reg_5740_pp5_it1[58] <= 1'b0;
ap_reg_ppstg_tmp_125_reg_5740_pp5_it1[59] <= 1'b0;
ap_reg_ppstg_tmp_125_reg_5740_pp5_it1[60] <= 1'b0;
ap_reg_ppstg_tmp_125_reg_5740_pp5_it1[61] <= 1'b0;
ap_reg_ppstg_tmp_125_reg_5740_pp5_it1[62] <= 1'b0;
ap_reg_ppstg_tmp_125_reg_5740_pp5_it1[63] <= 1'b0;
end
always @ (ap_clk)
begin
b_addr26_cast_reg_5755[0] <= 1'b0;
b_addr26_cast_reg_5755[1] <= 1'b0;
b_addr26_cast_reg_5755[2] <= 1'b0;
b_addr26_cast_reg_5755[3] <= 1'b0;
b_addr26_cast_reg_5755[4] <= 1'b0;
b_addr26_cast_reg_5755[5] <= 1'b0;
b_addr26_cast_reg_5755[12] <= 1'b0;
end
always @ (ap_clk)
begin
tmp_130_reg_5770[0] <= 1'b1;
tmp_130_reg_5770[14] <= 1'b0;
tmp_130_reg_5770[15] <= 1'b0;
tmp_130_reg_5770[16] <= 1'b0;
tmp_130_reg_5770[17] <= 1'b0;
tmp_130_reg_5770[18] <= 1'b0;
tmp_130_reg_5770[19] <= 1'b0;
tmp_130_reg_5770[20] <= 1'b0;
tmp_130_reg_5770[21] <= 1'b0;
tmp_130_reg_5770[22] <= 1'b0;
tmp_130_reg_5770[23] <= 1'b0;
tmp_130_reg_5770[24] <= 1'b0;
tmp_130_reg_5770[25] <= 1'b0;
tmp_130_reg_5770[26] <= 1'b0;
tmp_130_reg_5770[27] <= 1'b0;
tmp_130_reg_5770[28] <= 1'b0;
tmp_130_reg_5770[29] <= 1'b0;
tmp_130_reg_5770[30] <= 1'b0;
tmp_130_reg_5770[31] <= 1'b0;
tmp_130_reg_5770[32] <= 1'b0;
tmp_130_reg_5770[33] <= 1'b0;
tmp_130_reg_5770[34] <= 1'b0;
tmp_130_reg_5770[35] <= 1'b0;
tmp_130_reg_5770[36] <= 1'b0;
tmp_130_reg_5770[37] <= 1'b0;
tmp_130_reg_5770[38] <= 1'b0;
tmp_130_reg_5770[39] <= 1'b0;
tmp_130_reg_5770[40] <= 1'b0;
tmp_130_reg_5770[41] <= 1'b0;
tmp_130_reg_5770[42] <= 1'b0;
tmp_130_reg_5770[43] <= 1'b0;
tmp_130_reg_5770[44] <= 1'b0;
tmp_130_reg_5770[45] <= 1'b0;
tmp_130_reg_5770[46] <= 1'b0;
tmp_130_reg_5770[47] <= 1'b0;
tmp_130_reg_5770[48] <= 1'b0;
tmp_130_reg_5770[49] <= 1'b0;
tmp_130_reg_5770[50] <= 1'b0;
tmp_130_reg_5770[51] <= 1'b0;
tmp_130_reg_5770[52] <= 1'b0;
tmp_130_reg_5770[53] <= 1'b0;
tmp_130_reg_5770[54] <= 1'b0;
tmp_130_reg_5770[55] <= 1'b0;
tmp_130_reg_5770[56] <= 1'b0;
tmp_130_reg_5770[57] <= 1'b0;
tmp_130_reg_5770[58] <= 1'b0;
tmp_130_reg_5770[59] <= 1'b0;
tmp_130_reg_5770[60] <= 1'b0;
tmp_130_reg_5770[61] <= 1'b0;
tmp_130_reg_5770[62] <= 1'b0;
tmp_130_reg_5770[63] <= 1'b0;
end
always @ (ap_clk)
begin
ap_reg_ppstg_tmp_130_reg_5770_pp5_it1[0] <= 1'b1;
ap_reg_ppstg_tmp_130_reg_5770_pp5_it1[14] <= 1'b0;
ap_reg_ppstg_tmp_130_reg_5770_pp5_it1[15] <= 1'b0;
ap_reg_ppstg_tmp_130_reg_5770_pp5_it1[16] <= 1'b0;
ap_reg_ppstg_tmp_130_reg_5770_pp5_it1[17] <= 1'b0;
ap_reg_ppstg_tmp_130_reg_5770_pp5_it1[18] <= 1'b0;
ap_reg_ppstg_tmp_130_reg_5770_pp5_it1[19] <= 1'b0;
ap_reg_ppstg_tmp_130_reg_5770_pp5_it1[20] <= 1'b0;
ap_reg_ppstg_tmp_130_reg_5770_pp5_it1[21] <= 1'b0;
ap_reg_ppstg_tmp_130_reg_5770_pp5_it1[22] <= 1'b0;
ap_reg_ppstg_tmp_130_reg_5770_pp5_it1[23] <= 1'b0;
ap_reg_ppstg_tmp_130_reg_5770_pp5_it1[24] <= 1'b0;
ap_reg_ppstg_tmp_130_reg_5770_pp5_it1[25] <= 1'b0;
ap_reg_ppstg_tmp_130_reg_5770_pp5_it1[26] <= 1'b0;
ap_reg_ppstg_tmp_130_reg_5770_pp5_it1[27] <= 1'b0;
ap_reg_ppstg_tmp_130_reg_5770_pp5_it1[28] <= 1'b0;
ap_reg_ppstg_tmp_130_reg_5770_pp5_it1[29] <= 1'b0;
ap_reg_ppstg_tmp_130_reg_5770_pp5_it1[30] <= 1'b0;
ap_reg_ppstg_tmp_130_reg_5770_pp5_it1[31] <= 1'b0;
ap_reg_ppstg_tmp_130_reg_5770_pp5_it1[32] <= 1'b0;
ap_reg_ppstg_tmp_130_reg_5770_pp5_it1[33] <= 1'b0;
ap_reg_ppstg_tmp_130_reg_5770_pp5_it1[34] <= 1'b0;
ap_reg_ppstg_tmp_130_reg_5770_pp5_it1[35] <= 1'b0;
ap_reg_ppstg_tmp_130_reg_5770_pp5_it1[36] <= 1'b0;
ap_reg_ppstg_tmp_130_reg_5770_pp5_it1[37] <= 1'b0;
ap_reg_ppstg_tmp_130_reg_5770_pp5_it1[38] <= 1'b0;
ap_reg_ppstg_tmp_130_reg_5770_pp5_it1[39] <= 1'b0;
ap_reg_ppstg_tmp_130_reg_5770_pp5_it1[40] <= 1'b0;
ap_reg_ppstg_tmp_130_reg_5770_pp5_it1[41] <= 1'b0;
ap_reg_ppstg_tmp_130_reg_5770_pp5_it1[42] <= 1'b0;
ap_reg_ppstg_tmp_130_reg_5770_pp5_it1[43] <= 1'b0;
ap_reg_ppstg_tmp_130_reg_5770_pp5_it1[44] <= 1'b0;
ap_reg_ppstg_tmp_130_reg_5770_pp5_it1[45] <= 1'b0;
ap_reg_ppstg_tmp_130_reg_5770_pp5_it1[46] <= 1'b0;
ap_reg_ppstg_tmp_130_reg_5770_pp5_it1[47] <= 1'b0;
ap_reg_ppstg_tmp_130_reg_5770_pp5_it1[48] <= 1'b0;
ap_reg_ppstg_tmp_130_reg_5770_pp5_it1[49] <= 1'b0;
ap_reg_ppstg_tmp_130_reg_5770_pp5_it1[50] <= 1'b0;
ap_reg_ppstg_tmp_130_reg_5770_pp5_it1[51] <= 1'b0;
ap_reg_ppstg_tmp_130_reg_5770_pp5_it1[52] <= 1'b0;
ap_reg_ppstg_tmp_130_reg_5770_pp5_it1[53] <= 1'b0;
ap_reg_ppstg_tmp_130_reg_5770_pp5_it1[54] <= 1'b0;
ap_reg_ppstg_tmp_130_reg_5770_pp5_it1[55] <= 1'b0;
ap_reg_ppstg_tmp_130_reg_5770_pp5_it1[56] <= 1'b0;
ap_reg_ppstg_tmp_130_reg_5770_pp5_it1[57] <= 1'b0;
ap_reg_ppstg_tmp_130_reg_5770_pp5_it1[58] <= 1'b0;
ap_reg_ppstg_tmp_130_reg_5770_pp5_it1[59] <= 1'b0;
ap_reg_ppstg_tmp_130_reg_5770_pp5_it1[60] <= 1'b0;
ap_reg_ppstg_tmp_130_reg_5770_pp5_it1[61] <= 1'b0;
ap_reg_ppstg_tmp_130_reg_5770_pp5_it1[62] <= 1'b0;
ap_reg_ppstg_tmp_130_reg_5770_pp5_it1[63] <= 1'b0;
end
always @ (ap_clk)
begin
tmp_97_reg_5785[1] <= 1'b1;
end
always @ (ap_clk)
begin
tmp_138_reg_5790[14] <= 1'b0;
tmp_138_reg_5790[15] <= 1'b0;
tmp_138_reg_5790[16] <= 1'b0;
tmp_138_reg_5790[17] <= 1'b0;
tmp_138_reg_5790[18] <= 1'b0;
tmp_138_reg_5790[19] <= 1'b0;
tmp_138_reg_5790[20] <= 1'b0;
tmp_138_reg_5790[21] <= 1'b0;
tmp_138_reg_5790[22] <= 1'b0;
tmp_138_reg_5790[23] <= 1'b0;
tmp_138_reg_5790[24] <= 1'b0;
tmp_138_reg_5790[25] <= 1'b0;
tmp_138_reg_5790[26] <= 1'b0;
tmp_138_reg_5790[27] <= 1'b0;
tmp_138_reg_5790[28] <= 1'b0;
tmp_138_reg_5790[29] <= 1'b0;
tmp_138_reg_5790[30] <= 1'b0;
tmp_138_reg_5790[31] <= 1'b0;
tmp_138_reg_5790[32] <= 1'b0;
tmp_138_reg_5790[33] <= 1'b0;
tmp_138_reg_5790[34] <= 1'b0;
tmp_138_reg_5790[35] <= 1'b0;
tmp_138_reg_5790[36] <= 1'b0;
tmp_138_reg_5790[37] <= 1'b0;
tmp_138_reg_5790[38] <= 1'b0;
tmp_138_reg_5790[39] <= 1'b0;
tmp_138_reg_5790[40] <= 1'b0;
tmp_138_reg_5790[41] <= 1'b0;
tmp_138_reg_5790[42] <= 1'b0;
tmp_138_reg_5790[43] <= 1'b0;
tmp_138_reg_5790[44] <= 1'b0;
tmp_138_reg_5790[45] <= 1'b0;
tmp_138_reg_5790[46] <= 1'b0;
tmp_138_reg_5790[47] <= 1'b0;
tmp_138_reg_5790[48] <= 1'b0;
tmp_138_reg_5790[49] <= 1'b0;
tmp_138_reg_5790[50] <= 1'b0;
tmp_138_reg_5790[51] <= 1'b0;
tmp_138_reg_5790[52] <= 1'b0;
tmp_138_reg_5790[53] <= 1'b0;
tmp_138_reg_5790[54] <= 1'b0;
tmp_138_reg_5790[55] <= 1'b0;
tmp_138_reg_5790[56] <= 1'b0;
tmp_138_reg_5790[57] <= 1'b0;
tmp_138_reg_5790[58] <= 1'b0;
tmp_138_reg_5790[59] <= 1'b0;
tmp_138_reg_5790[60] <= 1'b0;
tmp_138_reg_5790[61] <= 1'b0;
tmp_138_reg_5790[62] <= 1'b0;
tmp_138_reg_5790[63] <= 1'b0;
end
always @ (ap_clk)
begin
ap_reg_ppstg_tmp_138_reg_5790_pp5_it1[14] <= 1'b0;
ap_reg_ppstg_tmp_138_reg_5790_pp5_it1[15] <= 1'b0;
ap_reg_ppstg_tmp_138_reg_5790_pp5_it1[16] <= 1'b0;
ap_reg_ppstg_tmp_138_reg_5790_pp5_it1[17] <= 1'b0;
ap_reg_ppstg_tmp_138_reg_5790_pp5_it1[18] <= 1'b0;
ap_reg_ppstg_tmp_138_reg_5790_pp5_it1[19] <= 1'b0;
ap_reg_ppstg_tmp_138_reg_5790_pp5_it1[20] <= 1'b0;
ap_reg_ppstg_tmp_138_reg_5790_pp5_it1[21] <= 1'b0;
ap_reg_ppstg_tmp_138_reg_5790_pp5_it1[22] <= 1'b0;
ap_reg_ppstg_tmp_138_reg_5790_pp5_it1[23] <= 1'b0;
ap_reg_ppstg_tmp_138_reg_5790_pp5_it1[24] <= 1'b0;
ap_reg_ppstg_tmp_138_reg_5790_pp5_it1[25] <= 1'b0;
ap_reg_ppstg_tmp_138_reg_5790_pp5_it1[26] <= 1'b0;
ap_reg_ppstg_tmp_138_reg_5790_pp5_it1[27] <= 1'b0;
ap_reg_ppstg_tmp_138_reg_5790_pp5_it1[28] <= 1'b0;
ap_reg_ppstg_tmp_138_reg_5790_pp5_it1[29] <= 1'b0;
ap_reg_ppstg_tmp_138_reg_5790_pp5_it1[30] <= 1'b0;
ap_reg_ppstg_tmp_138_reg_5790_pp5_it1[31] <= 1'b0;
ap_reg_ppstg_tmp_138_reg_5790_pp5_it1[32] <= 1'b0;
ap_reg_ppstg_tmp_138_reg_5790_pp5_it1[33] <= 1'b0;
ap_reg_ppstg_tmp_138_reg_5790_pp5_it1[34] <= 1'b0;
ap_reg_ppstg_tmp_138_reg_5790_pp5_it1[35] <= 1'b0;
ap_reg_ppstg_tmp_138_reg_5790_pp5_it1[36] <= 1'b0;
ap_reg_ppstg_tmp_138_reg_5790_pp5_it1[37] <= 1'b0;
ap_reg_ppstg_tmp_138_reg_5790_pp5_it1[38] <= 1'b0;
ap_reg_ppstg_tmp_138_reg_5790_pp5_it1[39] <= 1'b0;
ap_reg_ppstg_tmp_138_reg_5790_pp5_it1[40] <= 1'b0;
ap_reg_ppstg_tmp_138_reg_5790_pp5_it1[41] <= 1'b0;
ap_reg_ppstg_tmp_138_reg_5790_pp5_it1[42] <= 1'b0;
ap_reg_ppstg_tmp_138_reg_5790_pp5_it1[43] <= 1'b0;
ap_reg_ppstg_tmp_138_reg_5790_pp5_it1[44] <= 1'b0;
ap_reg_ppstg_tmp_138_reg_5790_pp5_it1[45] <= 1'b0;
ap_reg_ppstg_tmp_138_reg_5790_pp5_it1[46] <= 1'b0;
ap_reg_ppstg_tmp_138_reg_5790_pp5_it1[47] <= 1'b0;
ap_reg_ppstg_tmp_138_reg_5790_pp5_it1[48] <= 1'b0;
ap_reg_ppstg_tmp_138_reg_5790_pp5_it1[49] <= 1'b0;
ap_reg_ppstg_tmp_138_reg_5790_pp5_it1[50] <= 1'b0;
ap_reg_ppstg_tmp_138_reg_5790_pp5_it1[51] <= 1'b0;
ap_reg_ppstg_tmp_138_reg_5790_pp5_it1[52] <= 1'b0;
ap_reg_ppstg_tmp_138_reg_5790_pp5_it1[53] <= 1'b0;
ap_reg_ppstg_tmp_138_reg_5790_pp5_it1[54] <= 1'b0;
ap_reg_ppstg_tmp_138_reg_5790_pp5_it1[55] <= 1'b0;
ap_reg_ppstg_tmp_138_reg_5790_pp5_it1[56] <= 1'b0;
ap_reg_ppstg_tmp_138_reg_5790_pp5_it1[57] <= 1'b0;
ap_reg_ppstg_tmp_138_reg_5790_pp5_it1[58] <= 1'b0;
ap_reg_ppstg_tmp_138_reg_5790_pp5_it1[59] <= 1'b0;
ap_reg_ppstg_tmp_138_reg_5790_pp5_it1[60] <= 1'b0;
ap_reg_ppstg_tmp_138_reg_5790_pp5_it1[61] <= 1'b0;
ap_reg_ppstg_tmp_138_reg_5790_pp5_it1[62] <= 1'b0;
ap_reg_ppstg_tmp_138_reg_5790_pp5_it1[63] <= 1'b0;
end
always @ (ap_clk)
begin
tmp_146_reg_5805[0] <= 1'b1;
tmp_146_reg_5805[1] <= 1'b1;
tmp_146_reg_5805[14] <= 1'b0;
tmp_146_reg_5805[15] <= 1'b0;
tmp_146_reg_5805[16] <= 1'b0;
tmp_146_reg_5805[17] <= 1'b0;
tmp_146_reg_5805[18] <= 1'b0;
tmp_146_reg_5805[19] <= 1'b0;
tmp_146_reg_5805[20] <= 1'b0;
tmp_146_reg_5805[21] <= 1'b0;
tmp_146_reg_5805[22] <= 1'b0;
tmp_146_reg_5805[23] <= 1'b0;
tmp_146_reg_5805[24] <= 1'b0;
tmp_146_reg_5805[25] <= 1'b0;
tmp_146_reg_5805[26] <= 1'b0;
tmp_146_reg_5805[27] <= 1'b0;
tmp_146_reg_5805[28] <= 1'b0;
tmp_146_reg_5805[29] <= 1'b0;
tmp_146_reg_5805[30] <= 1'b0;
tmp_146_reg_5805[31] <= 1'b0;
tmp_146_reg_5805[32] <= 1'b0;
tmp_146_reg_5805[33] <= 1'b0;
tmp_146_reg_5805[34] <= 1'b0;
tmp_146_reg_5805[35] <= 1'b0;
tmp_146_reg_5805[36] <= 1'b0;
tmp_146_reg_5805[37] <= 1'b0;
tmp_146_reg_5805[38] <= 1'b0;
tmp_146_reg_5805[39] <= 1'b0;
tmp_146_reg_5805[40] <= 1'b0;
tmp_146_reg_5805[41] <= 1'b0;
tmp_146_reg_5805[42] <= 1'b0;
tmp_146_reg_5805[43] <= 1'b0;
tmp_146_reg_5805[44] <= 1'b0;
tmp_146_reg_5805[45] <= 1'b0;
tmp_146_reg_5805[46] <= 1'b0;
tmp_146_reg_5805[47] <= 1'b0;
tmp_146_reg_5805[48] <= 1'b0;
tmp_146_reg_5805[49] <= 1'b0;
tmp_146_reg_5805[50] <= 1'b0;
tmp_146_reg_5805[51] <= 1'b0;
tmp_146_reg_5805[52] <= 1'b0;
tmp_146_reg_5805[53] <= 1'b0;
tmp_146_reg_5805[54] <= 1'b0;
tmp_146_reg_5805[55] <= 1'b0;
tmp_146_reg_5805[56] <= 1'b0;
tmp_146_reg_5805[57] <= 1'b0;
tmp_146_reg_5805[58] <= 1'b0;
tmp_146_reg_5805[59] <= 1'b0;
tmp_146_reg_5805[60] <= 1'b0;
tmp_146_reg_5805[61] <= 1'b0;
tmp_146_reg_5805[62] <= 1'b0;
tmp_146_reg_5805[63] <= 1'b0;
end
always @ (ap_clk)
begin
ap_reg_ppstg_tmp_146_reg_5805_pp5_it1[0] <= 1'b1;
ap_reg_ppstg_tmp_146_reg_5805_pp5_it1[1] <= 1'b1;
ap_reg_ppstg_tmp_146_reg_5805_pp5_it1[14] <= 1'b0;
ap_reg_ppstg_tmp_146_reg_5805_pp5_it1[15] <= 1'b0;
ap_reg_ppstg_tmp_146_reg_5805_pp5_it1[16] <= 1'b0;
ap_reg_ppstg_tmp_146_reg_5805_pp5_it1[17] <= 1'b0;
ap_reg_ppstg_tmp_146_reg_5805_pp5_it1[18] <= 1'b0;
ap_reg_ppstg_tmp_146_reg_5805_pp5_it1[19] <= 1'b0;
ap_reg_ppstg_tmp_146_reg_5805_pp5_it1[20] <= 1'b0;
ap_reg_ppstg_tmp_146_reg_5805_pp5_it1[21] <= 1'b0;
ap_reg_ppstg_tmp_146_reg_5805_pp5_it1[22] <= 1'b0;
ap_reg_ppstg_tmp_146_reg_5805_pp5_it1[23] <= 1'b0;
ap_reg_ppstg_tmp_146_reg_5805_pp5_it1[24] <= 1'b0;
ap_reg_ppstg_tmp_146_reg_5805_pp5_it1[25] <= 1'b0;
ap_reg_ppstg_tmp_146_reg_5805_pp5_it1[26] <= 1'b0;
ap_reg_ppstg_tmp_146_reg_5805_pp5_it1[27] <= 1'b0;
ap_reg_ppstg_tmp_146_reg_5805_pp5_it1[28] <= 1'b0;
ap_reg_ppstg_tmp_146_reg_5805_pp5_it1[29] <= 1'b0;
ap_reg_ppstg_tmp_146_reg_5805_pp5_it1[30] <= 1'b0;
ap_reg_ppstg_tmp_146_reg_5805_pp5_it1[31] <= 1'b0;
ap_reg_ppstg_tmp_146_reg_5805_pp5_it1[32] <= 1'b0;
ap_reg_ppstg_tmp_146_reg_5805_pp5_it1[33] <= 1'b0;
ap_reg_ppstg_tmp_146_reg_5805_pp5_it1[34] <= 1'b0;
ap_reg_ppstg_tmp_146_reg_5805_pp5_it1[35] <= 1'b0;
ap_reg_ppstg_tmp_146_reg_5805_pp5_it1[36] <= 1'b0;
ap_reg_ppstg_tmp_146_reg_5805_pp5_it1[37] <= 1'b0;
ap_reg_ppstg_tmp_146_reg_5805_pp5_it1[38] <= 1'b0;
ap_reg_ppstg_tmp_146_reg_5805_pp5_it1[39] <= 1'b0;
ap_reg_ppstg_tmp_146_reg_5805_pp5_it1[40] <= 1'b0;
ap_reg_ppstg_tmp_146_reg_5805_pp5_it1[41] <= 1'b0;
ap_reg_ppstg_tmp_146_reg_5805_pp5_it1[42] <= 1'b0;
ap_reg_ppstg_tmp_146_reg_5805_pp5_it1[43] <= 1'b0;
ap_reg_ppstg_tmp_146_reg_5805_pp5_it1[44] <= 1'b0;
ap_reg_ppstg_tmp_146_reg_5805_pp5_it1[45] <= 1'b0;
ap_reg_ppstg_tmp_146_reg_5805_pp5_it1[46] <= 1'b0;
ap_reg_ppstg_tmp_146_reg_5805_pp5_it1[47] <= 1'b0;
ap_reg_ppstg_tmp_146_reg_5805_pp5_it1[48] <= 1'b0;
ap_reg_ppstg_tmp_146_reg_5805_pp5_it1[49] <= 1'b0;
ap_reg_ppstg_tmp_146_reg_5805_pp5_it1[50] <= 1'b0;
ap_reg_ppstg_tmp_146_reg_5805_pp5_it1[51] <= 1'b0;
ap_reg_ppstg_tmp_146_reg_5805_pp5_it1[52] <= 1'b0;
ap_reg_ppstg_tmp_146_reg_5805_pp5_it1[53] <= 1'b0;
ap_reg_ppstg_tmp_146_reg_5805_pp5_it1[54] <= 1'b0;
ap_reg_ppstg_tmp_146_reg_5805_pp5_it1[55] <= 1'b0;
ap_reg_ppstg_tmp_146_reg_5805_pp5_it1[56] <= 1'b0;
ap_reg_ppstg_tmp_146_reg_5805_pp5_it1[57] <= 1'b0;
ap_reg_ppstg_tmp_146_reg_5805_pp5_it1[58] <= 1'b0;
ap_reg_ppstg_tmp_146_reg_5805_pp5_it1[59] <= 1'b0;
ap_reg_ppstg_tmp_146_reg_5805_pp5_it1[60] <= 1'b0;
ap_reg_ppstg_tmp_146_reg_5805_pp5_it1[61] <= 1'b0;
ap_reg_ppstg_tmp_146_reg_5805_pp5_it1[62] <= 1'b0;
ap_reg_ppstg_tmp_146_reg_5805_pp5_it1[63] <= 1'b0;
end
always @ (ap_clk)
begin
tmp_105_reg_5820[2] <= 1'b1;
end
always @ (ap_clk)
begin
tmp_154_reg_5825[14] <= 1'b0;
tmp_154_reg_5825[15] <= 1'b0;
tmp_154_reg_5825[16] <= 1'b0;
tmp_154_reg_5825[17] <= 1'b0;
tmp_154_reg_5825[18] <= 1'b0;
tmp_154_reg_5825[19] <= 1'b0;
tmp_154_reg_5825[20] <= 1'b0;
tmp_154_reg_5825[21] <= 1'b0;
tmp_154_reg_5825[22] <= 1'b0;
tmp_154_reg_5825[23] <= 1'b0;
tmp_154_reg_5825[24] <= 1'b0;
tmp_154_reg_5825[25] <= 1'b0;
tmp_154_reg_5825[26] <= 1'b0;
tmp_154_reg_5825[27] <= 1'b0;
tmp_154_reg_5825[28] <= 1'b0;
tmp_154_reg_5825[29] <= 1'b0;
tmp_154_reg_5825[30] <= 1'b0;
tmp_154_reg_5825[31] <= 1'b0;
tmp_154_reg_5825[32] <= 1'b0;
tmp_154_reg_5825[33] <= 1'b0;
tmp_154_reg_5825[34] <= 1'b0;
tmp_154_reg_5825[35] <= 1'b0;
tmp_154_reg_5825[36] <= 1'b0;
tmp_154_reg_5825[37] <= 1'b0;
tmp_154_reg_5825[38] <= 1'b0;
tmp_154_reg_5825[39] <= 1'b0;
tmp_154_reg_5825[40] <= 1'b0;
tmp_154_reg_5825[41] <= 1'b0;
tmp_154_reg_5825[42] <= 1'b0;
tmp_154_reg_5825[43] <= 1'b0;
tmp_154_reg_5825[44] <= 1'b0;
tmp_154_reg_5825[45] <= 1'b0;
tmp_154_reg_5825[46] <= 1'b0;
tmp_154_reg_5825[47] <= 1'b0;
tmp_154_reg_5825[48] <= 1'b0;
tmp_154_reg_5825[49] <= 1'b0;
tmp_154_reg_5825[50] <= 1'b0;
tmp_154_reg_5825[51] <= 1'b0;
tmp_154_reg_5825[52] <= 1'b0;
tmp_154_reg_5825[53] <= 1'b0;
tmp_154_reg_5825[54] <= 1'b0;
tmp_154_reg_5825[55] <= 1'b0;
tmp_154_reg_5825[56] <= 1'b0;
tmp_154_reg_5825[57] <= 1'b0;
tmp_154_reg_5825[58] <= 1'b0;
tmp_154_reg_5825[59] <= 1'b0;
tmp_154_reg_5825[60] <= 1'b0;
tmp_154_reg_5825[61] <= 1'b0;
tmp_154_reg_5825[62] <= 1'b0;
tmp_154_reg_5825[63] <= 1'b0;
end
always @ (ap_clk)
begin
ap_reg_ppstg_tmp_154_reg_5825_pp5_it1[14] <= 1'b0;
ap_reg_ppstg_tmp_154_reg_5825_pp5_it1[15] <= 1'b0;
ap_reg_ppstg_tmp_154_reg_5825_pp5_it1[16] <= 1'b0;
ap_reg_ppstg_tmp_154_reg_5825_pp5_it1[17] <= 1'b0;
ap_reg_ppstg_tmp_154_reg_5825_pp5_it1[18] <= 1'b0;
ap_reg_ppstg_tmp_154_reg_5825_pp5_it1[19] <= 1'b0;
ap_reg_ppstg_tmp_154_reg_5825_pp5_it1[20] <= 1'b0;
ap_reg_ppstg_tmp_154_reg_5825_pp5_it1[21] <= 1'b0;
ap_reg_ppstg_tmp_154_reg_5825_pp5_it1[22] <= 1'b0;
ap_reg_ppstg_tmp_154_reg_5825_pp5_it1[23] <= 1'b0;
ap_reg_ppstg_tmp_154_reg_5825_pp5_it1[24] <= 1'b0;
ap_reg_ppstg_tmp_154_reg_5825_pp5_it1[25] <= 1'b0;
ap_reg_ppstg_tmp_154_reg_5825_pp5_it1[26] <= 1'b0;
ap_reg_ppstg_tmp_154_reg_5825_pp5_it1[27] <= 1'b0;
ap_reg_ppstg_tmp_154_reg_5825_pp5_it1[28] <= 1'b0;
ap_reg_ppstg_tmp_154_reg_5825_pp5_it1[29] <= 1'b0;
ap_reg_ppstg_tmp_154_reg_5825_pp5_it1[30] <= 1'b0;
ap_reg_ppstg_tmp_154_reg_5825_pp5_it1[31] <= 1'b0;
ap_reg_ppstg_tmp_154_reg_5825_pp5_it1[32] <= 1'b0;
ap_reg_ppstg_tmp_154_reg_5825_pp5_it1[33] <= 1'b0;
ap_reg_ppstg_tmp_154_reg_5825_pp5_it1[34] <= 1'b0;
ap_reg_ppstg_tmp_154_reg_5825_pp5_it1[35] <= 1'b0;
ap_reg_ppstg_tmp_154_reg_5825_pp5_it1[36] <= 1'b0;
ap_reg_ppstg_tmp_154_reg_5825_pp5_it1[37] <= 1'b0;
ap_reg_ppstg_tmp_154_reg_5825_pp5_it1[38] <= 1'b0;
ap_reg_ppstg_tmp_154_reg_5825_pp5_it1[39] <= 1'b0;
ap_reg_ppstg_tmp_154_reg_5825_pp5_it1[40] <= 1'b0;
ap_reg_ppstg_tmp_154_reg_5825_pp5_it1[41] <= 1'b0;
ap_reg_ppstg_tmp_154_reg_5825_pp5_it1[42] <= 1'b0;
ap_reg_ppstg_tmp_154_reg_5825_pp5_it1[43] <= 1'b0;
ap_reg_ppstg_tmp_154_reg_5825_pp5_it1[44] <= 1'b0;
ap_reg_ppstg_tmp_154_reg_5825_pp5_it1[45] <= 1'b0;
ap_reg_ppstg_tmp_154_reg_5825_pp5_it1[46] <= 1'b0;
ap_reg_ppstg_tmp_154_reg_5825_pp5_it1[47] <= 1'b0;
ap_reg_ppstg_tmp_154_reg_5825_pp5_it1[48] <= 1'b0;
ap_reg_ppstg_tmp_154_reg_5825_pp5_it1[49] <= 1'b0;
ap_reg_ppstg_tmp_154_reg_5825_pp5_it1[50] <= 1'b0;
ap_reg_ppstg_tmp_154_reg_5825_pp5_it1[51] <= 1'b0;
ap_reg_ppstg_tmp_154_reg_5825_pp5_it1[52] <= 1'b0;
ap_reg_ppstg_tmp_154_reg_5825_pp5_it1[53] <= 1'b0;
ap_reg_ppstg_tmp_154_reg_5825_pp5_it1[54] <= 1'b0;
ap_reg_ppstg_tmp_154_reg_5825_pp5_it1[55] <= 1'b0;
ap_reg_ppstg_tmp_154_reg_5825_pp5_it1[56] <= 1'b0;
ap_reg_ppstg_tmp_154_reg_5825_pp5_it1[57] <= 1'b0;
ap_reg_ppstg_tmp_154_reg_5825_pp5_it1[58] <= 1'b0;
ap_reg_ppstg_tmp_154_reg_5825_pp5_it1[59] <= 1'b0;
ap_reg_ppstg_tmp_154_reg_5825_pp5_it1[60] <= 1'b0;
ap_reg_ppstg_tmp_154_reg_5825_pp5_it1[61] <= 1'b0;
ap_reg_ppstg_tmp_154_reg_5825_pp5_it1[62] <= 1'b0;
ap_reg_ppstg_tmp_154_reg_5825_pp5_it1[63] <= 1'b0;
end
always @ (ap_clk)
begin
tmp_160_reg_5840[0] <= 1'b1;
tmp_160_reg_5840[14] <= 1'b0;
tmp_160_reg_5840[15] <= 1'b0;
tmp_160_reg_5840[16] <= 1'b0;
tmp_160_reg_5840[17] <= 1'b0;
tmp_160_reg_5840[18] <= 1'b0;
tmp_160_reg_5840[19] <= 1'b0;
tmp_160_reg_5840[20] <= 1'b0;
tmp_160_reg_5840[21] <= 1'b0;
tmp_160_reg_5840[22] <= 1'b0;
tmp_160_reg_5840[23] <= 1'b0;
tmp_160_reg_5840[24] <= 1'b0;
tmp_160_reg_5840[25] <= 1'b0;
tmp_160_reg_5840[26] <= 1'b0;
tmp_160_reg_5840[27] <= 1'b0;
tmp_160_reg_5840[28] <= 1'b0;
tmp_160_reg_5840[29] <= 1'b0;
tmp_160_reg_5840[30] <= 1'b0;
tmp_160_reg_5840[31] <= 1'b0;
tmp_160_reg_5840[32] <= 1'b0;
tmp_160_reg_5840[33] <= 1'b0;
tmp_160_reg_5840[34] <= 1'b0;
tmp_160_reg_5840[35] <= 1'b0;
tmp_160_reg_5840[36] <= 1'b0;
tmp_160_reg_5840[37] <= 1'b0;
tmp_160_reg_5840[38] <= 1'b0;
tmp_160_reg_5840[39] <= 1'b0;
tmp_160_reg_5840[40] <= 1'b0;
tmp_160_reg_5840[41] <= 1'b0;
tmp_160_reg_5840[42] <= 1'b0;
tmp_160_reg_5840[43] <= 1'b0;
tmp_160_reg_5840[44] <= 1'b0;
tmp_160_reg_5840[45] <= 1'b0;
tmp_160_reg_5840[46] <= 1'b0;
tmp_160_reg_5840[47] <= 1'b0;
tmp_160_reg_5840[48] <= 1'b0;
tmp_160_reg_5840[49] <= 1'b0;
tmp_160_reg_5840[50] <= 1'b0;
tmp_160_reg_5840[51] <= 1'b0;
tmp_160_reg_5840[52] <= 1'b0;
tmp_160_reg_5840[53] <= 1'b0;
tmp_160_reg_5840[54] <= 1'b0;
tmp_160_reg_5840[55] <= 1'b0;
tmp_160_reg_5840[56] <= 1'b0;
tmp_160_reg_5840[57] <= 1'b0;
tmp_160_reg_5840[58] <= 1'b0;
tmp_160_reg_5840[59] <= 1'b0;
tmp_160_reg_5840[60] <= 1'b0;
tmp_160_reg_5840[61] <= 1'b0;
tmp_160_reg_5840[62] <= 1'b0;
tmp_160_reg_5840[63] <= 1'b0;
end
always @ (ap_clk)
begin
ap_reg_ppstg_tmp_160_reg_5840_pp5_it1[0] <= 1'b1;
ap_reg_ppstg_tmp_160_reg_5840_pp5_it1[14] <= 1'b0;
ap_reg_ppstg_tmp_160_reg_5840_pp5_it1[15] <= 1'b0;
ap_reg_ppstg_tmp_160_reg_5840_pp5_it1[16] <= 1'b0;
ap_reg_ppstg_tmp_160_reg_5840_pp5_it1[17] <= 1'b0;
ap_reg_ppstg_tmp_160_reg_5840_pp5_it1[18] <= 1'b0;
ap_reg_ppstg_tmp_160_reg_5840_pp5_it1[19] <= 1'b0;
ap_reg_ppstg_tmp_160_reg_5840_pp5_it1[20] <= 1'b0;
ap_reg_ppstg_tmp_160_reg_5840_pp5_it1[21] <= 1'b0;
ap_reg_ppstg_tmp_160_reg_5840_pp5_it1[22] <= 1'b0;
ap_reg_ppstg_tmp_160_reg_5840_pp5_it1[23] <= 1'b0;
ap_reg_ppstg_tmp_160_reg_5840_pp5_it1[24] <= 1'b0;
ap_reg_ppstg_tmp_160_reg_5840_pp5_it1[25] <= 1'b0;
ap_reg_ppstg_tmp_160_reg_5840_pp5_it1[26] <= 1'b0;
ap_reg_ppstg_tmp_160_reg_5840_pp5_it1[27] <= 1'b0;
ap_reg_ppstg_tmp_160_reg_5840_pp5_it1[28] <= 1'b0;
ap_reg_ppstg_tmp_160_reg_5840_pp5_it1[29] <= 1'b0;
ap_reg_ppstg_tmp_160_reg_5840_pp5_it1[30] <= 1'b0;
ap_reg_ppstg_tmp_160_reg_5840_pp5_it1[31] <= 1'b0;
ap_reg_ppstg_tmp_160_reg_5840_pp5_it1[32] <= 1'b0;
ap_reg_ppstg_tmp_160_reg_5840_pp5_it1[33] <= 1'b0;
ap_reg_ppstg_tmp_160_reg_5840_pp5_it1[34] <= 1'b0;
ap_reg_ppstg_tmp_160_reg_5840_pp5_it1[35] <= 1'b0;
ap_reg_ppstg_tmp_160_reg_5840_pp5_it1[36] <= 1'b0;
ap_reg_ppstg_tmp_160_reg_5840_pp5_it1[37] <= 1'b0;
ap_reg_ppstg_tmp_160_reg_5840_pp5_it1[38] <= 1'b0;
ap_reg_ppstg_tmp_160_reg_5840_pp5_it1[39] <= 1'b0;
ap_reg_ppstg_tmp_160_reg_5840_pp5_it1[40] <= 1'b0;
ap_reg_ppstg_tmp_160_reg_5840_pp5_it1[41] <= 1'b0;
ap_reg_ppstg_tmp_160_reg_5840_pp5_it1[42] <= 1'b0;
ap_reg_ppstg_tmp_160_reg_5840_pp5_it1[43] <= 1'b0;
ap_reg_ppstg_tmp_160_reg_5840_pp5_it1[44] <= 1'b0;
ap_reg_ppstg_tmp_160_reg_5840_pp5_it1[45] <= 1'b0;
ap_reg_ppstg_tmp_160_reg_5840_pp5_it1[46] <= 1'b0;
ap_reg_ppstg_tmp_160_reg_5840_pp5_it1[47] <= 1'b0;
ap_reg_ppstg_tmp_160_reg_5840_pp5_it1[48] <= 1'b0;
ap_reg_ppstg_tmp_160_reg_5840_pp5_it1[49] <= 1'b0;
ap_reg_ppstg_tmp_160_reg_5840_pp5_it1[50] <= 1'b0;
ap_reg_ppstg_tmp_160_reg_5840_pp5_it1[51] <= 1'b0;
ap_reg_ppstg_tmp_160_reg_5840_pp5_it1[52] <= 1'b0;
ap_reg_ppstg_tmp_160_reg_5840_pp5_it1[53] <= 1'b0;
ap_reg_ppstg_tmp_160_reg_5840_pp5_it1[54] <= 1'b0;
ap_reg_ppstg_tmp_160_reg_5840_pp5_it1[55] <= 1'b0;
ap_reg_ppstg_tmp_160_reg_5840_pp5_it1[56] <= 1'b0;
ap_reg_ppstg_tmp_160_reg_5840_pp5_it1[57] <= 1'b0;
ap_reg_ppstg_tmp_160_reg_5840_pp5_it1[58] <= 1'b0;
ap_reg_ppstg_tmp_160_reg_5840_pp5_it1[59] <= 1'b0;
ap_reg_ppstg_tmp_160_reg_5840_pp5_it1[60] <= 1'b0;
ap_reg_ppstg_tmp_160_reg_5840_pp5_it1[61] <= 1'b0;
ap_reg_ppstg_tmp_160_reg_5840_pp5_it1[62] <= 1'b0;
ap_reg_ppstg_tmp_160_reg_5840_pp5_it1[63] <= 1'b0;
end
always @ (ap_clk)
begin
ap_reg_ppstg_tmp_160_reg_5840_pp5_it2[0] <= 1'b1;
ap_reg_ppstg_tmp_160_reg_5840_pp5_it2[14] <= 1'b0;
ap_reg_ppstg_tmp_160_reg_5840_pp5_it2[15] <= 1'b0;
ap_reg_ppstg_tmp_160_reg_5840_pp5_it2[16] <= 1'b0;
ap_reg_ppstg_tmp_160_reg_5840_pp5_it2[17] <= 1'b0;
ap_reg_ppstg_tmp_160_reg_5840_pp5_it2[18] <= 1'b0;
ap_reg_ppstg_tmp_160_reg_5840_pp5_it2[19] <= 1'b0;
ap_reg_ppstg_tmp_160_reg_5840_pp5_it2[20] <= 1'b0;
ap_reg_ppstg_tmp_160_reg_5840_pp5_it2[21] <= 1'b0;
ap_reg_ppstg_tmp_160_reg_5840_pp5_it2[22] <= 1'b0;
ap_reg_ppstg_tmp_160_reg_5840_pp5_it2[23] <= 1'b0;
ap_reg_ppstg_tmp_160_reg_5840_pp5_it2[24] <= 1'b0;
ap_reg_ppstg_tmp_160_reg_5840_pp5_it2[25] <= 1'b0;
ap_reg_ppstg_tmp_160_reg_5840_pp5_it2[26] <= 1'b0;
ap_reg_ppstg_tmp_160_reg_5840_pp5_it2[27] <= 1'b0;
ap_reg_ppstg_tmp_160_reg_5840_pp5_it2[28] <= 1'b0;
ap_reg_ppstg_tmp_160_reg_5840_pp5_it2[29] <= 1'b0;
ap_reg_ppstg_tmp_160_reg_5840_pp5_it2[30] <= 1'b0;
ap_reg_ppstg_tmp_160_reg_5840_pp5_it2[31] <= 1'b0;
ap_reg_ppstg_tmp_160_reg_5840_pp5_it2[32] <= 1'b0;
ap_reg_ppstg_tmp_160_reg_5840_pp5_it2[33] <= 1'b0;
ap_reg_ppstg_tmp_160_reg_5840_pp5_it2[34] <= 1'b0;
ap_reg_ppstg_tmp_160_reg_5840_pp5_it2[35] <= 1'b0;
ap_reg_ppstg_tmp_160_reg_5840_pp5_it2[36] <= 1'b0;
ap_reg_ppstg_tmp_160_reg_5840_pp5_it2[37] <= 1'b0;
ap_reg_ppstg_tmp_160_reg_5840_pp5_it2[38] <= 1'b0;
ap_reg_ppstg_tmp_160_reg_5840_pp5_it2[39] <= 1'b0;
ap_reg_ppstg_tmp_160_reg_5840_pp5_it2[40] <= 1'b0;
ap_reg_ppstg_tmp_160_reg_5840_pp5_it2[41] <= 1'b0;
ap_reg_ppstg_tmp_160_reg_5840_pp5_it2[42] <= 1'b0;
ap_reg_ppstg_tmp_160_reg_5840_pp5_it2[43] <= 1'b0;
ap_reg_ppstg_tmp_160_reg_5840_pp5_it2[44] <= 1'b0;
ap_reg_ppstg_tmp_160_reg_5840_pp5_it2[45] <= 1'b0;
ap_reg_ppstg_tmp_160_reg_5840_pp5_it2[46] <= 1'b0;
ap_reg_ppstg_tmp_160_reg_5840_pp5_it2[47] <= 1'b0;
ap_reg_ppstg_tmp_160_reg_5840_pp5_it2[48] <= 1'b0;
ap_reg_ppstg_tmp_160_reg_5840_pp5_it2[49] <= 1'b0;
ap_reg_ppstg_tmp_160_reg_5840_pp5_it2[50] <= 1'b0;
ap_reg_ppstg_tmp_160_reg_5840_pp5_it2[51] <= 1'b0;
ap_reg_ppstg_tmp_160_reg_5840_pp5_it2[52] <= 1'b0;
ap_reg_ppstg_tmp_160_reg_5840_pp5_it2[53] <= 1'b0;
ap_reg_ppstg_tmp_160_reg_5840_pp5_it2[54] <= 1'b0;
ap_reg_ppstg_tmp_160_reg_5840_pp5_it2[55] <= 1'b0;
ap_reg_ppstg_tmp_160_reg_5840_pp5_it2[56] <= 1'b0;
ap_reg_ppstg_tmp_160_reg_5840_pp5_it2[57] <= 1'b0;
ap_reg_ppstg_tmp_160_reg_5840_pp5_it2[58] <= 1'b0;
ap_reg_ppstg_tmp_160_reg_5840_pp5_it2[59] <= 1'b0;
ap_reg_ppstg_tmp_160_reg_5840_pp5_it2[60] <= 1'b0;
ap_reg_ppstg_tmp_160_reg_5840_pp5_it2[61] <= 1'b0;
ap_reg_ppstg_tmp_160_reg_5840_pp5_it2[62] <= 1'b0;
ap_reg_ppstg_tmp_160_reg_5840_pp5_it2[63] <= 1'b0;
end
always @ (ap_clk)
begin
tmp_113_reg_5855[1] <= 1'b1;
tmp_113_reg_5855[2] <= 1'b1;
end
always @ (ap_clk)
begin
tmp_117_reg_5865[0] <= 1'b1;
tmp_117_reg_5865[1] <= 1'b1;
tmp_117_reg_5865[2] <= 1'b1;
end
always @ (ap_clk)
begin
tmp_164_reg_5880[14] <= 1'b0;
tmp_164_reg_5880[15] <= 1'b0;
tmp_164_reg_5880[16] <= 1'b0;
tmp_164_reg_5880[17] <= 1'b0;
tmp_164_reg_5880[18] <= 1'b0;
tmp_164_reg_5880[19] <= 1'b0;
tmp_164_reg_5880[20] <= 1'b0;
tmp_164_reg_5880[21] <= 1'b0;
tmp_164_reg_5880[22] <= 1'b0;
tmp_164_reg_5880[23] <= 1'b0;
tmp_164_reg_5880[24] <= 1'b0;
tmp_164_reg_5880[25] <= 1'b0;
tmp_164_reg_5880[26] <= 1'b0;
tmp_164_reg_5880[27] <= 1'b0;
tmp_164_reg_5880[28] <= 1'b0;
tmp_164_reg_5880[29] <= 1'b0;
tmp_164_reg_5880[30] <= 1'b0;
tmp_164_reg_5880[31] <= 1'b0;
tmp_164_reg_5880[32] <= 1'b0;
tmp_164_reg_5880[33] <= 1'b0;
tmp_164_reg_5880[34] <= 1'b0;
tmp_164_reg_5880[35] <= 1'b0;
tmp_164_reg_5880[36] <= 1'b0;
tmp_164_reg_5880[37] <= 1'b0;
tmp_164_reg_5880[38] <= 1'b0;
tmp_164_reg_5880[39] <= 1'b0;
tmp_164_reg_5880[40] <= 1'b0;
tmp_164_reg_5880[41] <= 1'b0;
tmp_164_reg_5880[42] <= 1'b0;
tmp_164_reg_5880[43] <= 1'b0;
tmp_164_reg_5880[44] <= 1'b0;
tmp_164_reg_5880[45] <= 1'b0;
tmp_164_reg_5880[46] <= 1'b0;
tmp_164_reg_5880[47] <= 1'b0;
tmp_164_reg_5880[48] <= 1'b0;
tmp_164_reg_5880[49] <= 1'b0;
tmp_164_reg_5880[50] <= 1'b0;
tmp_164_reg_5880[51] <= 1'b0;
tmp_164_reg_5880[52] <= 1'b0;
tmp_164_reg_5880[53] <= 1'b0;
tmp_164_reg_5880[54] <= 1'b0;
tmp_164_reg_5880[55] <= 1'b0;
tmp_164_reg_5880[56] <= 1'b0;
tmp_164_reg_5880[57] <= 1'b0;
tmp_164_reg_5880[58] <= 1'b0;
tmp_164_reg_5880[59] <= 1'b0;
tmp_164_reg_5880[60] <= 1'b0;
tmp_164_reg_5880[61] <= 1'b0;
tmp_164_reg_5880[62] <= 1'b0;
tmp_164_reg_5880[63] <= 1'b0;
end
always @ (ap_clk)
begin
ap_reg_ppstg_tmp_164_reg_5880_pp5_it2[14] <= 1'b0;
ap_reg_ppstg_tmp_164_reg_5880_pp5_it2[15] <= 1'b0;
ap_reg_ppstg_tmp_164_reg_5880_pp5_it2[16] <= 1'b0;
ap_reg_ppstg_tmp_164_reg_5880_pp5_it2[17] <= 1'b0;
ap_reg_ppstg_tmp_164_reg_5880_pp5_it2[18] <= 1'b0;
ap_reg_ppstg_tmp_164_reg_5880_pp5_it2[19] <= 1'b0;
ap_reg_ppstg_tmp_164_reg_5880_pp5_it2[20] <= 1'b0;
ap_reg_ppstg_tmp_164_reg_5880_pp5_it2[21] <= 1'b0;
ap_reg_ppstg_tmp_164_reg_5880_pp5_it2[22] <= 1'b0;
ap_reg_ppstg_tmp_164_reg_5880_pp5_it2[23] <= 1'b0;
ap_reg_ppstg_tmp_164_reg_5880_pp5_it2[24] <= 1'b0;
ap_reg_ppstg_tmp_164_reg_5880_pp5_it2[25] <= 1'b0;
ap_reg_ppstg_tmp_164_reg_5880_pp5_it2[26] <= 1'b0;
ap_reg_ppstg_tmp_164_reg_5880_pp5_it2[27] <= 1'b0;
ap_reg_ppstg_tmp_164_reg_5880_pp5_it2[28] <= 1'b0;
ap_reg_ppstg_tmp_164_reg_5880_pp5_it2[29] <= 1'b0;
ap_reg_ppstg_tmp_164_reg_5880_pp5_it2[30] <= 1'b0;
ap_reg_ppstg_tmp_164_reg_5880_pp5_it2[31] <= 1'b0;
ap_reg_ppstg_tmp_164_reg_5880_pp5_it2[32] <= 1'b0;
ap_reg_ppstg_tmp_164_reg_5880_pp5_it2[33] <= 1'b0;
ap_reg_ppstg_tmp_164_reg_5880_pp5_it2[34] <= 1'b0;
ap_reg_ppstg_tmp_164_reg_5880_pp5_it2[35] <= 1'b0;
ap_reg_ppstg_tmp_164_reg_5880_pp5_it2[36] <= 1'b0;
ap_reg_ppstg_tmp_164_reg_5880_pp5_it2[37] <= 1'b0;
ap_reg_ppstg_tmp_164_reg_5880_pp5_it2[38] <= 1'b0;
ap_reg_ppstg_tmp_164_reg_5880_pp5_it2[39] <= 1'b0;
ap_reg_ppstg_tmp_164_reg_5880_pp5_it2[40] <= 1'b0;
ap_reg_ppstg_tmp_164_reg_5880_pp5_it2[41] <= 1'b0;
ap_reg_ppstg_tmp_164_reg_5880_pp5_it2[42] <= 1'b0;
ap_reg_ppstg_tmp_164_reg_5880_pp5_it2[43] <= 1'b0;
ap_reg_ppstg_tmp_164_reg_5880_pp5_it2[44] <= 1'b0;
ap_reg_ppstg_tmp_164_reg_5880_pp5_it2[45] <= 1'b0;
ap_reg_ppstg_tmp_164_reg_5880_pp5_it2[46] <= 1'b0;
ap_reg_ppstg_tmp_164_reg_5880_pp5_it2[47] <= 1'b0;
ap_reg_ppstg_tmp_164_reg_5880_pp5_it2[48] <= 1'b0;
ap_reg_ppstg_tmp_164_reg_5880_pp5_it2[49] <= 1'b0;
ap_reg_ppstg_tmp_164_reg_5880_pp5_it2[50] <= 1'b0;
ap_reg_ppstg_tmp_164_reg_5880_pp5_it2[51] <= 1'b0;
ap_reg_ppstg_tmp_164_reg_5880_pp5_it2[52] <= 1'b0;
ap_reg_ppstg_tmp_164_reg_5880_pp5_it2[53] <= 1'b0;
ap_reg_ppstg_tmp_164_reg_5880_pp5_it2[54] <= 1'b0;
ap_reg_ppstg_tmp_164_reg_5880_pp5_it2[55] <= 1'b0;
ap_reg_ppstg_tmp_164_reg_5880_pp5_it2[56] <= 1'b0;
ap_reg_ppstg_tmp_164_reg_5880_pp5_it2[57] <= 1'b0;
ap_reg_ppstg_tmp_164_reg_5880_pp5_it2[58] <= 1'b0;
ap_reg_ppstg_tmp_164_reg_5880_pp5_it2[59] <= 1'b0;
ap_reg_ppstg_tmp_164_reg_5880_pp5_it2[60] <= 1'b0;
ap_reg_ppstg_tmp_164_reg_5880_pp5_it2[61] <= 1'b0;
ap_reg_ppstg_tmp_164_reg_5880_pp5_it2[62] <= 1'b0;
ap_reg_ppstg_tmp_164_reg_5880_pp5_it2[63] <= 1'b0;
end
always @ (ap_clk)
begin
a_addr50_reg_5890[0] <= 1'b1;
a_addr50_reg_5890[1] <= 1'b1;
a_addr50_reg_5890[2] <= 1'b1;
end
always @ (ap_clk)
begin
tmp_168_reg_5895[0] <= 1'b1;
tmp_168_reg_5895[1] <= 1'b1;
tmp_168_reg_5895[2] <= 1'b1;
tmp_168_reg_5895[14] <= 1'b0;
tmp_168_reg_5895[15] <= 1'b0;
tmp_168_reg_5895[16] <= 1'b0;
tmp_168_reg_5895[17] <= 1'b0;
tmp_168_reg_5895[18] <= 1'b0;
tmp_168_reg_5895[19] <= 1'b0;
tmp_168_reg_5895[20] <= 1'b0;
tmp_168_reg_5895[21] <= 1'b0;
tmp_168_reg_5895[22] <= 1'b0;
tmp_168_reg_5895[23] <= 1'b0;
tmp_168_reg_5895[24] <= 1'b0;
tmp_168_reg_5895[25] <= 1'b0;
tmp_168_reg_5895[26] <= 1'b0;
tmp_168_reg_5895[27] <= 1'b0;
tmp_168_reg_5895[28] <= 1'b0;
tmp_168_reg_5895[29] <= 1'b0;
tmp_168_reg_5895[30] <= 1'b0;
tmp_168_reg_5895[31] <= 1'b0;
tmp_168_reg_5895[32] <= 1'b0;
tmp_168_reg_5895[33] <= 1'b0;
tmp_168_reg_5895[34] <= 1'b0;
tmp_168_reg_5895[35] <= 1'b0;
tmp_168_reg_5895[36] <= 1'b0;
tmp_168_reg_5895[37] <= 1'b0;
tmp_168_reg_5895[38] <= 1'b0;
tmp_168_reg_5895[39] <= 1'b0;
tmp_168_reg_5895[40] <= 1'b0;
tmp_168_reg_5895[41] <= 1'b0;
tmp_168_reg_5895[42] <= 1'b0;
tmp_168_reg_5895[43] <= 1'b0;
tmp_168_reg_5895[44] <= 1'b0;
tmp_168_reg_5895[45] <= 1'b0;
tmp_168_reg_5895[46] <= 1'b0;
tmp_168_reg_5895[47] <= 1'b0;
tmp_168_reg_5895[48] <= 1'b0;
tmp_168_reg_5895[49] <= 1'b0;
tmp_168_reg_5895[50] <= 1'b0;
tmp_168_reg_5895[51] <= 1'b0;
tmp_168_reg_5895[52] <= 1'b0;
tmp_168_reg_5895[53] <= 1'b0;
tmp_168_reg_5895[54] <= 1'b0;
tmp_168_reg_5895[55] <= 1'b0;
tmp_168_reg_5895[56] <= 1'b0;
tmp_168_reg_5895[57] <= 1'b0;
tmp_168_reg_5895[58] <= 1'b0;
tmp_168_reg_5895[59] <= 1'b0;
tmp_168_reg_5895[60] <= 1'b0;
tmp_168_reg_5895[61] <= 1'b0;
tmp_168_reg_5895[62] <= 1'b0;
tmp_168_reg_5895[63] <= 1'b0;
end
always @ (ap_clk)
begin
ap_reg_ppstg_tmp_168_reg_5895_pp5_it2[0] <= 1'b1;
ap_reg_ppstg_tmp_168_reg_5895_pp5_it2[1] <= 1'b1;
ap_reg_ppstg_tmp_168_reg_5895_pp5_it2[2] <= 1'b1;
ap_reg_ppstg_tmp_168_reg_5895_pp5_it2[14] <= 1'b0;
ap_reg_ppstg_tmp_168_reg_5895_pp5_it2[15] <= 1'b0;
ap_reg_ppstg_tmp_168_reg_5895_pp5_it2[16] <= 1'b0;
ap_reg_ppstg_tmp_168_reg_5895_pp5_it2[17] <= 1'b0;
ap_reg_ppstg_tmp_168_reg_5895_pp5_it2[18] <= 1'b0;
ap_reg_ppstg_tmp_168_reg_5895_pp5_it2[19] <= 1'b0;
ap_reg_ppstg_tmp_168_reg_5895_pp5_it2[20] <= 1'b0;
ap_reg_ppstg_tmp_168_reg_5895_pp5_it2[21] <= 1'b0;
ap_reg_ppstg_tmp_168_reg_5895_pp5_it2[22] <= 1'b0;
ap_reg_ppstg_tmp_168_reg_5895_pp5_it2[23] <= 1'b0;
ap_reg_ppstg_tmp_168_reg_5895_pp5_it2[24] <= 1'b0;
ap_reg_ppstg_tmp_168_reg_5895_pp5_it2[25] <= 1'b0;
ap_reg_ppstg_tmp_168_reg_5895_pp5_it2[26] <= 1'b0;
ap_reg_ppstg_tmp_168_reg_5895_pp5_it2[27] <= 1'b0;
ap_reg_ppstg_tmp_168_reg_5895_pp5_it2[28] <= 1'b0;
ap_reg_ppstg_tmp_168_reg_5895_pp5_it2[29] <= 1'b0;
ap_reg_ppstg_tmp_168_reg_5895_pp5_it2[30] <= 1'b0;
ap_reg_ppstg_tmp_168_reg_5895_pp5_it2[31] <= 1'b0;
ap_reg_ppstg_tmp_168_reg_5895_pp5_it2[32] <= 1'b0;
ap_reg_ppstg_tmp_168_reg_5895_pp5_it2[33] <= 1'b0;
ap_reg_ppstg_tmp_168_reg_5895_pp5_it2[34] <= 1'b0;
ap_reg_ppstg_tmp_168_reg_5895_pp5_it2[35] <= 1'b0;
ap_reg_ppstg_tmp_168_reg_5895_pp5_it2[36] <= 1'b0;
ap_reg_ppstg_tmp_168_reg_5895_pp5_it2[37] <= 1'b0;
ap_reg_ppstg_tmp_168_reg_5895_pp5_it2[38] <= 1'b0;
ap_reg_ppstg_tmp_168_reg_5895_pp5_it2[39] <= 1'b0;
ap_reg_ppstg_tmp_168_reg_5895_pp5_it2[40] <= 1'b0;
ap_reg_ppstg_tmp_168_reg_5895_pp5_it2[41] <= 1'b0;
ap_reg_ppstg_tmp_168_reg_5895_pp5_it2[42] <= 1'b0;
ap_reg_ppstg_tmp_168_reg_5895_pp5_it2[43] <= 1'b0;
ap_reg_ppstg_tmp_168_reg_5895_pp5_it2[44] <= 1'b0;
ap_reg_ppstg_tmp_168_reg_5895_pp5_it2[45] <= 1'b0;
ap_reg_ppstg_tmp_168_reg_5895_pp5_it2[46] <= 1'b0;
ap_reg_ppstg_tmp_168_reg_5895_pp5_it2[47] <= 1'b0;
ap_reg_ppstg_tmp_168_reg_5895_pp5_it2[48] <= 1'b0;
ap_reg_ppstg_tmp_168_reg_5895_pp5_it2[49] <= 1'b0;
ap_reg_ppstg_tmp_168_reg_5895_pp5_it2[50] <= 1'b0;
ap_reg_ppstg_tmp_168_reg_5895_pp5_it2[51] <= 1'b0;
ap_reg_ppstg_tmp_168_reg_5895_pp5_it2[52] <= 1'b0;
ap_reg_ppstg_tmp_168_reg_5895_pp5_it2[53] <= 1'b0;
ap_reg_ppstg_tmp_168_reg_5895_pp5_it2[54] <= 1'b0;
ap_reg_ppstg_tmp_168_reg_5895_pp5_it2[55] <= 1'b0;
ap_reg_ppstg_tmp_168_reg_5895_pp5_it2[56] <= 1'b0;
ap_reg_ppstg_tmp_168_reg_5895_pp5_it2[57] <= 1'b0;
ap_reg_ppstg_tmp_168_reg_5895_pp5_it2[58] <= 1'b0;
ap_reg_ppstg_tmp_168_reg_5895_pp5_it2[59] <= 1'b0;
ap_reg_ppstg_tmp_168_reg_5895_pp5_it2[60] <= 1'b0;
ap_reg_ppstg_tmp_168_reg_5895_pp5_it2[61] <= 1'b0;
ap_reg_ppstg_tmp_168_reg_5895_pp5_it2[62] <= 1'b0;
ap_reg_ppstg_tmp_168_reg_5895_pp5_it2[63] <= 1'b0;
end
always @ (ap_clk)
begin
tmp_172_reg_5914[13] <= 1'b0;
tmp_172_reg_5914[14] <= 1'b0;
tmp_172_reg_5914[15] <= 1'b0;
tmp_172_reg_5914[16] <= 1'b0;
tmp_172_reg_5914[17] <= 1'b0;
tmp_172_reg_5914[18] <= 1'b0;
tmp_172_reg_5914[19] <= 1'b0;
tmp_172_reg_5914[20] <= 1'b0;
tmp_172_reg_5914[21] <= 1'b0;
tmp_172_reg_5914[22] <= 1'b0;
tmp_172_reg_5914[23] <= 1'b0;
tmp_172_reg_5914[24] <= 1'b0;
tmp_172_reg_5914[25] <= 1'b0;
tmp_172_reg_5914[26] <= 1'b0;
tmp_172_reg_5914[27] <= 1'b0;
tmp_172_reg_5914[28] <= 1'b0;
tmp_172_reg_5914[29] <= 1'b0;
tmp_172_reg_5914[30] <= 1'b0;
tmp_172_reg_5914[31] <= 1'b0;
tmp_172_reg_5914[32] <= 1'b0;
tmp_172_reg_5914[33] <= 1'b0;
tmp_172_reg_5914[34] <= 1'b0;
tmp_172_reg_5914[35] <= 1'b0;
tmp_172_reg_5914[36] <= 1'b0;
tmp_172_reg_5914[37] <= 1'b0;
tmp_172_reg_5914[38] <= 1'b0;
tmp_172_reg_5914[39] <= 1'b0;
tmp_172_reg_5914[40] <= 1'b0;
tmp_172_reg_5914[41] <= 1'b0;
tmp_172_reg_5914[42] <= 1'b0;
tmp_172_reg_5914[43] <= 1'b0;
tmp_172_reg_5914[44] <= 1'b0;
tmp_172_reg_5914[45] <= 1'b0;
tmp_172_reg_5914[46] <= 1'b0;
tmp_172_reg_5914[47] <= 1'b0;
tmp_172_reg_5914[48] <= 1'b0;
tmp_172_reg_5914[49] <= 1'b0;
tmp_172_reg_5914[50] <= 1'b0;
tmp_172_reg_5914[51] <= 1'b0;
tmp_172_reg_5914[52] <= 1'b0;
tmp_172_reg_5914[53] <= 1'b0;
tmp_172_reg_5914[54] <= 1'b0;
tmp_172_reg_5914[55] <= 1'b0;
tmp_172_reg_5914[56] <= 1'b0;
tmp_172_reg_5914[57] <= 1'b0;
tmp_172_reg_5914[58] <= 1'b0;
tmp_172_reg_5914[59] <= 1'b0;
tmp_172_reg_5914[60] <= 1'b0;
tmp_172_reg_5914[61] <= 1'b0;
tmp_172_reg_5914[62] <= 1'b0;
tmp_172_reg_5914[63] <= 1'b0;
end
always @ (ap_clk)
begin
ap_reg_ppstg_tmp_172_reg_5914_pp6_it1[13] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it1[14] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it1[15] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it1[16] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it1[17] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it1[18] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it1[19] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it1[20] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it1[21] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it1[22] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it1[23] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it1[24] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it1[25] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it1[26] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it1[27] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it1[28] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it1[29] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it1[30] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it1[31] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it1[32] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it1[33] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it1[34] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it1[35] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it1[36] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it1[37] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it1[38] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it1[39] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it1[40] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it1[41] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it1[42] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it1[43] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it1[44] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it1[45] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it1[46] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it1[47] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it1[48] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it1[49] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it1[50] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it1[51] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it1[52] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it1[53] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it1[54] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it1[55] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it1[56] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it1[57] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it1[58] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it1[59] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it1[60] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it1[61] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it1[62] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it1[63] <= 1'b0;
end
always @ (ap_clk)
begin
ap_reg_ppstg_tmp_172_reg_5914_pp6_it2[13] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it2[14] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it2[15] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it2[16] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it2[17] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it2[18] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it2[19] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it2[20] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it2[21] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it2[22] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it2[23] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it2[24] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it2[25] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it2[26] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it2[27] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it2[28] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it2[29] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it2[30] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it2[31] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it2[32] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it2[33] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it2[34] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it2[35] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it2[36] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it2[37] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it2[38] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it2[39] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it2[40] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it2[41] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it2[42] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it2[43] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it2[44] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it2[45] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it2[46] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it2[47] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it2[48] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it2[49] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it2[50] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it2[51] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it2[52] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it2[53] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it2[54] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it2[55] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it2[56] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it2[57] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it2[58] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it2[59] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it2[60] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it2[61] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it2[62] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it2[63] <= 1'b0;
end
always @ (ap_clk)
begin
ap_reg_ppstg_tmp_172_reg_5914_pp6_it3[13] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it3[14] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it3[15] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it3[16] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it3[17] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it3[18] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it3[19] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it3[20] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it3[21] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it3[22] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it3[23] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it3[24] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it3[25] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it3[26] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it3[27] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it3[28] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it3[29] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it3[30] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it3[31] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it3[32] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it3[33] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it3[34] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it3[35] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it3[36] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it3[37] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it3[38] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it3[39] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it3[40] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it3[41] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it3[42] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it3[43] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it3[44] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it3[45] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it3[46] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it3[47] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it3[48] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it3[49] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it3[50] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it3[51] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it3[52] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it3[53] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it3[54] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it3[55] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it3[56] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it3[57] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it3[58] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it3[59] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it3[60] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it3[61] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it3[62] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it3[63] <= 1'b0;
end
always @ (ap_clk)
begin
ap_reg_ppstg_tmp_172_reg_5914_pp6_it4[13] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it4[14] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it4[15] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it4[16] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it4[17] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it4[18] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it4[19] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it4[20] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it4[21] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it4[22] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it4[23] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it4[24] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it4[25] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it4[26] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it4[27] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it4[28] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it4[29] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it4[30] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it4[31] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it4[32] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it4[33] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it4[34] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it4[35] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it4[36] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it4[37] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it4[38] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it4[39] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it4[40] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it4[41] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it4[42] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it4[43] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it4[44] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it4[45] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it4[46] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it4[47] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it4[48] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it4[49] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it4[50] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it4[51] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it4[52] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it4[53] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it4[54] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it4[55] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it4[56] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it4[57] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it4[58] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it4[59] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it4[60] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it4[61] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it4[62] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it4[63] <= 1'b0;
end
always @ (ap_clk)
begin
ap_reg_ppstg_tmp_172_reg_5914_pp6_it5[13] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it5[14] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it5[15] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it5[16] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it5[17] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it5[18] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it5[19] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it5[20] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it5[21] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it5[22] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it5[23] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it5[24] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it5[25] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it5[26] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it5[27] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it5[28] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it5[29] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it5[30] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it5[31] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it5[32] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it5[33] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it5[34] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it5[35] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it5[36] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it5[37] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it5[38] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it5[39] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it5[40] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it5[41] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it5[42] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it5[43] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it5[44] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it5[45] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it5[46] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it5[47] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it5[48] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it5[49] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it5[50] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it5[51] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it5[52] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it5[53] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it5[54] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it5[55] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it5[56] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it5[57] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it5[58] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it5[59] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it5[60] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it5[61] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it5[62] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it5[63] <= 1'b0;
end
always @ (ap_clk)
begin
b_addr36_cast_reg_5956[0] <= 1'b0;
b_addr36_cast_reg_5956[1] <= 1'b0;
b_addr36_cast_reg_5956[2] <= 1'b0;
b_addr36_cast_reg_5956[3] <= 1'b0;
b_addr36_cast_reg_5956[4] <= 1'b0;
b_addr36_cast_reg_5956[5] <= 1'b0;
end
always @ (ap_clk)
begin
ap_reg_ppstg_b_addr36_cast_reg_5956_pp7_it1[0] <= 1'b0;
ap_reg_ppstg_b_addr36_cast_reg_5956_pp7_it1[1] <= 1'b0;
ap_reg_ppstg_b_addr36_cast_reg_5956_pp7_it1[2] <= 1'b0;
ap_reg_ppstg_b_addr36_cast_reg_5956_pp7_it1[3] <= 1'b0;
ap_reg_ppstg_b_addr36_cast_reg_5956_pp7_it1[4] <= 1'b0;
ap_reg_ppstg_b_addr36_cast_reg_5956_pp7_it1[5] <= 1'b0;
end
always @ (ap_clk)
begin
a_addr51_cast_reg_5982[0] <= 1'b0;
a_addr51_cast_reg_5982[1] <= 1'b0;
a_addr51_cast_reg_5982[2] <= 1'b0;
a_addr51_cast_reg_5982[3] <= 1'b0;
a_addr51_cast_reg_5982[4] <= 1'b0;
a_addr51_cast_reg_5982[5] <= 1'b0;
a_addr51_cast_reg_5982[12] <= 1'b0;
end
always @ (ap_clk)
begin
tmp_178_reg_5997[0] <= 1'b1;
end
always @ (ap_clk)
begin
ap_reg_ppstg_tmp_178_reg_5997_pp7_it1[0] <= 1'b1;
end
always @ (ap_clk)
begin
tmp_133_reg_6012[1] <= 1'b1;
end
always @ (ap_clk)
begin
tmp_186_reg_6032[0] <= 1'b1;
tmp_186_reg_6032[1] <= 1'b1;
end
always @ (ap_clk)
begin
ap_reg_ppstg_tmp_186_reg_6032_pp7_it1[0] <= 1'b1;
ap_reg_ppstg_tmp_186_reg_6032_pp7_it1[1] <= 1'b1;
end
always @ (ap_clk)
begin
tmp_141_reg_6047[2] <= 1'b1;
end
always @ (ap_clk)
begin
tmp_192_reg_6067[0] <= 1'b1;
end
always @ (ap_clk)
begin
ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[0] <= 1'b1;
end
always @ (ap_clk)
begin
ap_reg_ppstg_tmp_192_reg_6067_pp7_it2[0] <= 1'b1;
end
always @ (ap_clk)
begin
tmp_149_reg_6082[1] <= 1'b1;
tmp_149_reg_6082[2] <= 1'b1;
end
always @ (ap_clk)
begin
tmp_153_reg_6092[0] <= 1'b1;
tmp_153_reg_6092[1] <= 1'b1;
tmp_153_reg_6092[2] <= 1'b1;
end
always @ (ap_clk)
begin
b_addr44_reg_6117[0] <= 1'b1;
b_addr44_reg_6117[1] <= 1'b1;
b_addr44_reg_6117[2] <= 1'b1;
end
always @ (ap_clk)
begin
tmp_197_reg_6122[0] <= 1'b1;
tmp_197_reg_6122[1] <= 1'b1;
tmp_197_reg_6122[2] <= 1'b1;
end
always @ (ap_clk)
begin
ap_reg_ppstg_tmp_197_reg_6122_pp7_it2[0] <= 1'b1;
ap_reg_ppstg_tmp_197_reg_6122_pp7_it2[1] <= 1'b1;
ap_reg_ppstg_tmp_197_reg_6122_pp7_it2[2] <= 1'b1;
end
always @ (ap_clk)
begin
a_addr63_cast_reg_6165[0] <= 1'b0;
a_addr63_cast_reg_6165[1] <= 1'b0;
a_addr63_cast_reg_6165[2] <= 1'b0;
a_addr63_cast_reg_6165[3] <= 1'b0;
a_addr63_cast_reg_6165[4] <= 1'b0;
a_addr63_cast_reg_6165[5] <= 1'b0;
a_addr63_cast_reg_6165[13] <= 1'b0;
end
always @ (ap_clk)
begin
tmp_199_reg_6176[14] <= 1'b0;
tmp_199_reg_6176[15] <= 1'b0;
tmp_199_reg_6176[16] <= 1'b0;
tmp_199_reg_6176[17] <= 1'b0;
tmp_199_reg_6176[18] <= 1'b0;
tmp_199_reg_6176[19] <= 1'b0;
tmp_199_reg_6176[20] <= 1'b0;
tmp_199_reg_6176[21] <= 1'b0;
tmp_199_reg_6176[22] <= 1'b0;
tmp_199_reg_6176[23] <= 1'b0;
tmp_199_reg_6176[24] <= 1'b0;
tmp_199_reg_6176[25] <= 1'b0;
tmp_199_reg_6176[26] <= 1'b0;
tmp_199_reg_6176[27] <= 1'b0;
tmp_199_reg_6176[28] <= 1'b0;
tmp_199_reg_6176[29] <= 1'b0;
tmp_199_reg_6176[30] <= 1'b0;
tmp_199_reg_6176[31] <= 1'b0;
tmp_199_reg_6176[32] <= 1'b0;
tmp_199_reg_6176[33] <= 1'b0;
tmp_199_reg_6176[34] <= 1'b0;
tmp_199_reg_6176[35] <= 1'b0;
tmp_199_reg_6176[36] <= 1'b0;
tmp_199_reg_6176[37] <= 1'b0;
tmp_199_reg_6176[38] <= 1'b0;
tmp_199_reg_6176[39] <= 1'b0;
tmp_199_reg_6176[40] <= 1'b0;
tmp_199_reg_6176[41] <= 1'b0;
tmp_199_reg_6176[42] <= 1'b0;
tmp_199_reg_6176[43] <= 1'b0;
tmp_199_reg_6176[44] <= 1'b0;
tmp_199_reg_6176[45] <= 1'b0;
tmp_199_reg_6176[46] <= 1'b0;
tmp_199_reg_6176[47] <= 1'b0;
tmp_199_reg_6176[48] <= 1'b0;
tmp_199_reg_6176[49] <= 1'b0;
tmp_199_reg_6176[50] <= 1'b0;
tmp_199_reg_6176[51] <= 1'b0;
tmp_199_reg_6176[52] <= 1'b0;
tmp_199_reg_6176[53] <= 1'b0;
tmp_199_reg_6176[54] <= 1'b0;
tmp_199_reg_6176[55] <= 1'b0;
tmp_199_reg_6176[56] <= 1'b0;
tmp_199_reg_6176[57] <= 1'b0;
tmp_199_reg_6176[58] <= 1'b0;
tmp_199_reg_6176[59] <= 1'b0;
tmp_199_reg_6176[60] <= 1'b0;
tmp_199_reg_6176[61] <= 1'b0;
tmp_199_reg_6176[62] <= 1'b0;
tmp_199_reg_6176[63] <= 1'b0;
end
always @ (ap_clk)
begin
tmp_176_trn_cast_reg_6191[0] <= 1'b1;
tmp_176_trn_cast_reg_6191[7] <= 1'b0;
tmp_176_trn_cast_reg_6191[8] <= 1'b0;
tmp_176_trn_cast_reg_6191[9] <= 1'b0;
tmp_176_trn_cast_reg_6191[10] <= 1'b0;
tmp_176_trn_cast_reg_6191[11] <= 1'b0;
tmp_176_trn_cast_reg_6191[12] <= 1'b0;
tmp_176_trn_cast_reg_6191[13] <= 1'b0;
end
always @ (ap_clk)
begin
tmp_200_reg_6202[0] <= 1'b1;
tmp_200_reg_6202[14] <= 1'b0;
tmp_200_reg_6202[15] <= 1'b0;
tmp_200_reg_6202[16] <= 1'b0;
tmp_200_reg_6202[17] <= 1'b0;
tmp_200_reg_6202[18] <= 1'b0;
tmp_200_reg_6202[19] <= 1'b0;
tmp_200_reg_6202[20] <= 1'b0;
tmp_200_reg_6202[21] <= 1'b0;
tmp_200_reg_6202[22] <= 1'b0;
tmp_200_reg_6202[23] <= 1'b0;
tmp_200_reg_6202[24] <= 1'b0;
tmp_200_reg_6202[25] <= 1'b0;
tmp_200_reg_6202[26] <= 1'b0;
tmp_200_reg_6202[27] <= 1'b0;
tmp_200_reg_6202[28] <= 1'b0;
tmp_200_reg_6202[29] <= 1'b0;
tmp_200_reg_6202[30] <= 1'b0;
tmp_200_reg_6202[31] <= 1'b0;
tmp_200_reg_6202[32] <= 1'b0;
tmp_200_reg_6202[33] <= 1'b0;
tmp_200_reg_6202[34] <= 1'b0;
tmp_200_reg_6202[35] <= 1'b0;
tmp_200_reg_6202[36] <= 1'b0;
tmp_200_reg_6202[37] <= 1'b0;
tmp_200_reg_6202[38] <= 1'b0;
tmp_200_reg_6202[39] <= 1'b0;
tmp_200_reg_6202[40] <= 1'b0;
tmp_200_reg_6202[41] <= 1'b0;
tmp_200_reg_6202[42] <= 1'b0;
tmp_200_reg_6202[43] <= 1'b0;
tmp_200_reg_6202[44] <= 1'b0;
tmp_200_reg_6202[45] <= 1'b0;
tmp_200_reg_6202[46] <= 1'b0;
tmp_200_reg_6202[47] <= 1'b0;
tmp_200_reg_6202[48] <= 1'b0;
tmp_200_reg_6202[49] <= 1'b0;
tmp_200_reg_6202[50] <= 1'b0;
tmp_200_reg_6202[51] <= 1'b0;
tmp_200_reg_6202[52] <= 1'b0;
tmp_200_reg_6202[53] <= 1'b0;
tmp_200_reg_6202[54] <= 1'b0;
tmp_200_reg_6202[55] <= 1'b0;
tmp_200_reg_6202[56] <= 1'b0;
tmp_200_reg_6202[57] <= 1'b0;
tmp_200_reg_6202[58] <= 1'b0;
tmp_200_reg_6202[59] <= 1'b0;
tmp_200_reg_6202[60] <= 1'b0;
tmp_200_reg_6202[61] <= 1'b0;
tmp_200_reg_6202[62] <= 1'b0;
tmp_200_reg_6202[63] <= 1'b0;
end
always @ (ap_clk)
begin
tmp_178_trn_cast_reg_6212[1] <= 1'b1;
tmp_178_trn_cast_reg_6212[7] <= 1'b0;
tmp_178_trn_cast_reg_6212[8] <= 1'b0;
tmp_178_trn_cast_reg_6212[9] <= 1'b0;
tmp_178_trn_cast_reg_6212[10] <= 1'b0;
tmp_178_trn_cast_reg_6212[11] <= 1'b0;
tmp_178_trn_cast_reg_6212[12] <= 1'b0;
tmp_178_trn_cast_reg_6212[13] <= 1'b0;
end
always @ (ap_clk)
begin
tmp_201_reg_6223[14] <= 1'b0;
tmp_201_reg_6223[15] <= 1'b0;
tmp_201_reg_6223[16] <= 1'b0;
tmp_201_reg_6223[17] <= 1'b0;
tmp_201_reg_6223[18] <= 1'b0;
tmp_201_reg_6223[19] <= 1'b0;
tmp_201_reg_6223[20] <= 1'b0;
tmp_201_reg_6223[21] <= 1'b0;
tmp_201_reg_6223[22] <= 1'b0;
tmp_201_reg_6223[23] <= 1'b0;
tmp_201_reg_6223[24] <= 1'b0;
tmp_201_reg_6223[25] <= 1'b0;
tmp_201_reg_6223[26] <= 1'b0;
tmp_201_reg_6223[27] <= 1'b0;
tmp_201_reg_6223[28] <= 1'b0;
tmp_201_reg_6223[29] <= 1'b0;
tmp_201_reg_6223[30] <= 1'b0;
tmp_201_reg_6223[31] <= 1'b0;
tmp_201_reg_6223[32] <= 1'b0;
tmp_201_reg_6223[33] <= 1'b0;
tmp_201_reg_6223[34] <= 1'b0;
tmp_201_reg_6223[35] <= 1'b0;
tmp_201_reg_6223[36] <= 1'b0;
tmp_201_reg_6223[37] <= 1'b0;
tmp_201_reg_6223[38] <= 1'b0;
tmp_201_reg_6223[39] <= 1'b0;
tmp_201_reg_6223[40] <= 1'b0;
tmp_201_reg_6223[41] <= 1'b0;
tmp_201_reg_6223[42] <= 1'b0;
tmp_201_reg_6223[43] <= 1'b0;
tmp_201_reg_6223[44] <= 1'b0;
tmp_201_reg_6223[45] <= 1'b0;
tmp_201_reg_6223[46] <= 1'b0;
tmp_201_reg_6223[47] <= 1'b0;
tmp_201_reg_6223[48] <= 1'b0;
tmp_201_reg_6223[49] <= 1'b0;
tmp_201_reg_6223[50] <= 1'b0;
tmp_201_reg_6223[51] <= 1'b0;
tmp_201_reg_6223[52] <= 1'b0;
tmp_201_reg_6223[53] <= 1'b0;
tmp_201_reg_6223[54] <= 1'b0;
tmp_201_reg_6223[55] <= 1'b0;
tmp_201_reg_6223[56] <= 1'b0;
tmp_201_reg_6223[57] <= 1'b0;
tmp_201_reg_6223[58] <= 1'b0;
tmp_201_reg_6223[59] <= 1'b0;
tmp_201_reg_6223[60] <= 1'b0;
tmp_201_reg_6223[61] <= 1'b0;
tmp_201_reg_6223[62] <= 1'b0;
tmp_201_reg_6223[63] <= 1'b0;
end
always @ (ap_clk)
begin
tmp_180_trn_cast_reg_6233[0] <= 1'b1;
tmp_180_trn_cast_reg_6233[1] <= 1'b1;
tmp_180_trn_cast_reg_6233[7] <= 1'b0;
tmp_180_trn_cast_reg_6233[8] <= 1'b0;
tmp_180_trn_cast_reg_6233[9] <= 1'b0;
tmp_180_trn_cast_reg_6233[10] <= 1'b0;
tmp_180_trn_cast_reg_6233[11] <= 1'b0;
tmp_180_trn_cast_reg_6233[12] <= 1'b0;
tmp_180_trn_cast_reg_6233[13] <= 1'b0;
end
always @ (ap_clk)
begin
tmp_202_reg_6244[0] <= 1'b1;
tmp_202_reg_6244[1] <= 1'b1;
tmp_202_reg_6244[14] <= 1'b0;
tmp_202_reg_6244[15] <= 1'b0;
tmp_202_reg_6244[16] <= 1'b0;
tmp_202_reg_6244[17] <= 1'b0;
tmp_202_reg_6244[18] <= 1'b0;
tmp_202_reg_6244[19] <= 1'b0;
tmp_202_reg_6244[20] <= 1'b0;
tmp_202_reg_6244[21] <= 1'b0;
tmp_202_reg_6244[22] <= 1'b0;
tmp_202_reg_6244[23] <= 1'b0;
tmp_202_reg_6244[24] <= 1'b0;
tmp_202_reg_6244[25] <= 1'b0;
tmp_202_reg_6244[26] <= 1'b0;
tmp_202_reg_6244[27] <= 1'b0;
tmp_202_reg_6244[28] <= 1'b0;
tmp_202_reg_6244[29] <= 1'b0;
tmp_202_reg_6244[30] <= 1'b0;
tmp_202_reg_6244[31] <= 1'b0;
tmp_202_reg_6244[32] <= 1'b0;
tmp_202_reg_6244[33] <= 1'b0;
tmp_202_reg_6244[34] <= 1'b0;
tmp_202_reg_6244[35] <= 1'b0;
tmp_202_reg_6244[36] <= 1'b0;
tmp_202_reg_6244[37] <= 1'b0;
tmp_202_reg_6244[38] <= 1'b0;
tmp_202_reg_6244[39] <= 1'b0;
tmp_202_reg_6244[40] <= 1'b0;
tmp_202_reg_6244[41] <= 1'b0;
tmp_202_reg_6244[42] <= 1'b0;
tmp_202_reg_6244[43] <= 1'b0;
tmp_202_reg_6244[44] <= 1'b0;
tmp_202_reg_6244[45] <= 1'b0;
tmp_202_reg_6244[46] <= 1'b0;
tmp_202_reg_6244[47] <= 1'b0;
tmp_202_reg_6244[48] <= 1'b0;
tmp_202_reg_6244[49] <= 1'b0;
tmp_202_reg_6244[50] <= 1'b0;
tmp_202_reg_6244[51] <= 1'b0;
tmp_202_reg_6244[52] <= 1'b0;
tmp_202_reg_6244[53] <= 1'b0;
tmp_202_reg_6244[54] <= 1'b0;
tmp_202_reg_6244[55] <= 1'b0;
tmp_202_reg_6244[56] <= 1'b0;
tmp_202_reg_6244[57] <= 1'b0;
tmp_202_reg_6244[58] <= 1'b0;
tmp_202_reg_6244[59] <= 1'b0;
tmp_202_reg_6244[60] <= 1'b0;
tmp_202_reg_6244[61] <= 1'b0;
tmp_202_reg_6244[62] <= 1'b0;
tmp_202_reg_6244[63] <= 1'b0;
end
always @ (ap_clk)
begin
tmp_182_trn_cast_reg_6254[2] <= 1'b1;
tmp_182_trn_cast_reg_6254[7] <= 1'b0;
tmp_182_trn_cast_reg_6254[8] <= 1'b0;
tmp_182_trn_cast_reg_6254[9] <= 1'b0;
tmp_182_trn_cast_reg_6254[10] <= 1'b0;
tmp_182_trn_cast_reg_6254[11] <= 1'b0;
tmp_182_trn_cast_reg_6254[12] <= 1'b0;
tmp_182_trn_cast_reg_6254[13] <= 1'b0;
end
always @ (ap_clk)
begin
tmp_203_reg_6265[14] <= 1'b0;
tmp_203_reg_6265[15] <= 1'b0;
tmp_203_reg_6265[16] <= 1'b0;
tmp_203_reg_6265[17] <= 1'b0;
tmp_203_reg_6265[18] <= 1'b0;
tmp_203_reg_6265[19] <= 1'b0;
tmp_203_reg_6265[20] <= 1'b0;
tmp_203_reg_6265[21] <= 1'b0;
tmp_203_reg_6265[22] <= 1'b0;
tmp_203_reg_6265[23] <= 1'b0;
tmp_203_reg_6265[24] <= 1'b0;
tmp_203_reg_6265[25] <= 1'b0;
tmp_203_reg_6265[26] <= 1'b0;
tmp_203_reg_6265[27] <= 1'b0;
tmp_203_reg_6265[28] <= 1'b0;
tmp_203_reg_6265[29] <= 1'b0;
tmp_203_reg_6265[30] <= 1'b0;
tmp_203_reg_6265[31] <= 1'b0;
tmp_203_reg_6265[32] <= 1'b0;
tmp_203_reg_6265[33] <= 1'b0;
tmp_203_reg_6265[34] <= 1'b0;
tmp_203_reg_6265[35] <= 1'b0;
tmp_203_reg_6265[36] <= 1'b0;
tmp_203_reg_6265[37] <= 1'b0;
tmp_203_reg_6265[38] <= 1'b0;
tmp_203_reg_6265[39] <= 1'b0;
tmp_203_reg_6265[40] <= 1'b0;
tmp_203_reg_6265[41] <= 1'b0;
tmp_203_reg_6265[42] <= 1'b0;
tmp_203_reg_6265[43] <= 1'b0;
tmp_203_reg_6265[44] <= 1'b0;
tmp_203_reg_6265[45] <= 1'b0;
tmp_203_reg_6265[46] <= 1'b0;
tmp_203_reg_6265[47] <= 1'b0;
tmp_203_reg_6265[48] <= 1'b0;
tmp_203_reg_6265[49] <= 1'b0;
tmp_203_reg_6265[50] <= 1'b0;
tmp_203_reg_6265[51] <= 1'b0;
tmp_203_reg_6265[52] <= 1'b0;
tmp_203_reg_6265[53] <= 1'b0;
tmp_203_reg_6265[54] <= 1'b0;
tmp_203_reg_6265[55] <= 1'b0;
tmp_203_reg_6265[56] <= 1'b0;
tmp_203_reg_6265[57] <= 1'b0;
tmp_203_reg_6265[58] <= 1'b0;
tmp_203_reg_6265[59] <= 1'b0;
tmp_203_reg_6265[60] <= 1'b0;
tmp_203_reg_6265[61] <= 1'b0;
tmp_203_reg_6265[62] <= 1'b0;
tmp_203_reg_6265[63] <= 1'b0;
end
always @ (ap_clk)
begin
tmp_184_trn_cast_reg_6275[0] <= 1'b1;
tmp_184_trn_cast_reg_6275[2] <= 1'b1;
tmp_184_trn_cast_reg_6275[7] <= 1'b0;
tmp_184_trn_cast_reg_6275[8] <= 1'b0;
tmp_184_trn_cast_reg_6275[9] <= 1'b0;
tmp_184_trn_cast_reg_6275[10] <= 1'b0;
tmp_184_trn_cast_reg_6275[11] <= 1'b0;
tmp_184_trn_cast_reg_6275[12] <= 1'b0;
tmp_184_trn_cast_reg_6275[13] <= 1'b0;
end
always @ (ap_clk)
begin
tmp_204_reg_6286[0] <= 1'b1;
tmp_204_reg_6286[14] <= 1'b0;
tmp_204_reg_6286[15] <= 1'b0;
tmp_204_reg_6286[16] <= 1'b0;
tmp_204_reg_6286[17] <= 1'b0;
tmp_204_reg_6286[18] <= 1'b0;
tmp_204_reg_6286[19] <= 1'b0;
tmp_204_reg_6286[20] <= 1'b0;
tmp_204_reg_6286[21] <= 1'b0;
tmp_204_reg_6286[22] <= 1'b0;
tmp_204_reg_6286[23] <= 1'b0;
tmp_204_reg_6286[24] <= 1'b0;
tmp_204_reg_6286[25] <= 1'b0;
tmp_204_reg_6286[26] <= 1'b0;
tmp_204_reg_6286[27] <= 1'b0;
tmp_204_reg_6286[28] <= 1'b0;
tmp_204_reg_6286[29] <= 1'b0;
tmp_204_reg_6286[30] <= 1'b0;
tmp_204_reg_6286[31] <= 1'b0;
tmp_204_reg_6286[32] <= 1'b0;
tmp_204_reg_6286[33] <= 1'b0;
tmp_204_reg_6286[34] <= 1'b0;
tmp_204_reg_6286[35] <= 1'b0;
tmp_204_reg_6286[36] <= 1'b0;
tmp_204_reg_6286[37] <= 1'b0;
tmp_204_reg_6286[38] <= 1'b0;
tmp_204_reg_6286[39] <= 1'b0;
tmp_204_reg_6286[40] <= 1'b0;
tmp_204_reg_6286[41] <= 1'b0;
tmp_204_reg_6286[42] <= 1'b0;
tmp_204_reg_6286[43] <= 1'b0;
tmp_204_reg_6286[44] <= 1'b0;
tmp_204_reg_6286[45] <= 1'b0;
tmp_204_reg_6286[46] <= 1'b0;
tmp_204_reg_6286[47] <= 1'b0;
tmp_204_reg_6286[48] <= 1'b0;
tmp_204_reg_6286[49] <= 1'b0;
tmp_204_reg_6286[50] <= 1'b0;
tmp_204_reg_6286[51] <= 1'b0;
tmp_204_reg_6286[52] <= 1'b0;
tmp_204_reg_6286[53] <= 1'b0;
tmp_204_reg_6286[54] <= 1'b0;
tmp_204_reg_6286[55] <= 1'b0;
tmp_204_reg_6286[56] <= 1'b0;
tmp_204_reg_6286[57] <= 1'b0;
tmp_204_reg_6286[58] <= 1'b0;
tmp_204_reg_6286[59] <= 1'b0;
tmp_204_reg_6286[60] <= 1'b0;
tmp_204_reg_6286[61] <= 1'b0;
tmp_204_reg_6286[62] <= 1'b0;
tmp_204_reg_6286[63] <= 1'b0;
end
always @ (ap_clk)
begin
tmp_186_trn_cast_reg_6296[1] <= 1'b1;
tmp_186_trn_cast_reg_6296[2] <= 1'b1;
tmp_186_trn_cast_reg_6296[7] <= 1'b0;
tmp_186_trn_cast_reg_6296[8] <= 1'b0;
tmp_186_trn_cast_reg_6296[9] <= 1'b0;
tmp_186_trn_cast_reg_6296[10] <= 1'b0;
tmp_186_trn_cast_reg_6296[11] <= 1'b0;
tmp_186_trn_cast_reg_6296[12] <= 1'b0;
tmp_186_trn_cast_reg_6296[13] <= 1'b0;
end
always @ (ap_clk)
begin
tmp_205_reg_6307[14] <= 1'b0;
tmp_205_reg_6307[15] <= 1'b0;
tmp_205_reg_6307[16] <= 1'b0;
tmp_205_reg_6307[17] <= 1'b0;
tmp_205_reg_6307[18] <= 1'b0;
tmp_205_reg_6307[19] <= 1'b0;
tmp_205_reg_6307[20] <= 1'b0;
tmp_205_reg_6307[21] <= 1'b0;
tmp_205_reg_6307[22] <= 1'b0;
tmp_205_reg_6307[23] <= 1'b0;
tmp_205_reg_6307[24] <= 1'b0;
tmp_205_reg_6307[25] <= 1'b0;
tmp_205_reg_6307[26] <= 1'b0;
tmp_205_reg_6307[27] <= 1'b0;
tmp_205_reg_6307[28] <= 1'b0;
tmp_205_reg_6307[29] <= 1'b0;
tmp_205_reg_6307[30] <= 1'b0;
tmp_205_reg_6307[31] <= 1'b0;
tmp_205_reg_6307[32] <= 1'b0;
tmp_205_reg_6307[33] <= 1'b0;
tmp_205_reg_6307[34] <= 1'b0;
tmp_205_reg_6307[35] <= 1'b0;
tmp_205_reg_6307[36] <= 1'b0;
tmp_205_reg_6307[37] <= 1'b0;
tmp_205_reg_6307[38] <= 1'b0;
tmp_205_reg_6307[39] <= 1'b0;
tmp_205_reg_6307[40] <= 1'b0;
tmp_205_reg_6307[41] <= 1'b0;
tmp_205_reg_6307[42] <= 1'b0;
tmp_205_reg_6307[43] <= 1'b0;
tmp_205_reg_6307[44] <= 1'b0;
tmp_205_reg_6307[45] <= 1'b0;
tmp_205_reg_6307[46] <= 1'b0;
tmp_205_reg_6307[47] <= 1'b0;
tmp_205_reg_6307[48] <= 1'b0;
tmp_205_reg_6307[49] <= 1'b0;
tmp_205_reg_6307[50] <= 1'b0;
tmp_205_reg_6307[51] <= 1'b0;
tmp_205_reg_6307[52] <= 1'b0;
tmp_205_reg_6307[53] <= 1'b0;
tmp_205_reg_6307[54] <= 1'b0;
tmp_205_reg_6307[55] <= 1'b0;
tmp_205_reg_6307[56] <= 1'b0;
tmp_205_reg_6307[57] <= 1'b0;
tmp_205_reg_6307[58] <= 1'b0;
tmp_205_reg_6307[59] <= 1'b0;
tmp_205_reg_6307[60] <= 1'b0;
tmp_205_reg_6307[61] <= 1'b0;
tmp_205_reg_6307[62] <= 1'b0;
tmp_205_reg_6307[63] <= 1'b0;
end
always @ (ap_clk)
begin
tmp_188_trn_cast_reg_6317[0] <= 1'b1;
tmp_188_trn_cast_reg_6317[1] <= 1'b1;
tmp_188_trn_cast_reg_6317[2] <= 1'b1;
tmp_188_trn_cast_reg_6317[7] <= 1'b0;
tmp_188_trn_cast_reg_6317[8] <= 1'b0;
tmp_188_trn_cast_reg_6317[9] <= 1'b0;
tmp_188_trn_cast_reg_6317[10] <= 1'b0;
tmp_188_trn_cast_reg_6317[11] <= 1'b0;
tmp_188_trn_cast_reg_6317[12] <= 1'b0;
tmp_188_trn_cast_reg_6317[13] <= 1'b0;
end
always @ (ap_clk)
begin
tmp_206_reg_6328[0] <= 1'b1;
tmp_206_reg_6328[1] <= 1'b1;
tmp_206_reg_6328[2] <= 1'b1;
tmp_206_reg_6328[14] <= 1'b0;
tmp_206_reg_6328[15] <= 1'b0;
tmp_206_reg_6328[16] <= 1'b0;
tmp_206_reg_6328[17] <= 1'b0;
tmp_206_reg_6328[18] <= 1'b0;
tmp_206_reg_6328[19] <= 1'b0;
tmp_206_reg_6328[20] <= 1'b0;
tmp_206_reg_6328[21] <= 1'b0;
tmp_206_reg_6328[22] <= 1'b0;
tmp_206_reg_6328[23] <= 1'b0;
tmp_206_reg_6328[24] <= 1'b0;
tmp_206_reg_6328[25] <= 1'b0;
tmp_206_reg_6328[26] <= 1'b0;
tmp_206_reg_6328[27] <= 1'b0;
tmp_206_reg_6328[28] <= 1'b0;
tmp_206_reg_6328[29] <= 1'b0;
tmp_206_reg_6328[30] <= 1'b0;
tmp_206_reg_6328[31] <= 1'b0;
tmp_206_reg_6328[32] <= 1'b0;
tmp_206_reg_6328[33] <= 1'b0;
tmp_206_reg_6328[34] <= 1'b0;
tmp_206_reg_6328[35] <= 1'b0;
tmp_206_reg_6328[36] <= 1'b0;
tmp_206_reg_6328[37] <= 1'b0;
tmp_206_reg_6328[38] <= 1'b0;
tmp_206_reg_6328[39] <= 1'b0;
tmp_206_reg_6328[40] <= 1'b0;
tmp_206_reg_6328[41] <= 1'b0;
tmp_206_reg_6328[42] <= 1'b0;
tmp_206_reg_6328[43] <= 1'b0;
tmp_206_reg_6328[44] <= 1'b0;
tmp_206_reg_6328[45] <= 1'b0;
tmp_206_reg_6328[46] <= 1'b0;
tmp_206_reg_6328[47] <= 1'b0;
tmp_206_reg_6328[48] <= 1'b0;
tmp_206_reg_6328[49] <= 1'b0;
tmp_206_reg_6328[50] <= 1'b0;
tmp_206_reg_6328[51] <= 1'b0;
tmp_206_reg_6328[52] <= 1'b0;
tmp_206_reg_6328[53] <= 1'b0;
tmp_206_reg_6328[54] <= 1'b0;
tmp_206_reg_6328[55] <= 1'b0;
tmp_206_reg_6328[56] <= 1'b0;
tmp_206_reg_6328[57] <= 1'b0;
tmp_206_reg_6328[58] <= 1'b0;
tmp_206_reg_6328[59] <= 1'b0;
tmp_206_reg_6328[60] <= 1'b0;
tmp_206_reg_6328[61] <= 1'b0;
tmp_206_reg_6328[62] <= 1'b0;
tmp_206_reg_6328[63] <= 1'b0;
end
always @ (ap_clk)
begin
a_addr77_cast_reg_6338[0] <= 1'b0;
a_addr77_cast_reg_6338[1] <= 1'b0;
a_addr77_cast_reg_6338[2] <= 1'b0;
a_addr77_cast_reg_6338[3] <= 1'b0;
a_addr77_cast_reg_6338[4] <= 1'b0;
a_addr77_cast_reg_6338[5] <= 1'b0;
a_addr77_cast_reg_6338[6] <= 1'b1;
a_addr77_cast_reg_6338[13] <= 1'b0;
end
always @ (ap_clk)
begin
tmp_207_reg_6348[0] <= 1'b1;
tmp_207_reg_6348[14] <= 1'b0;
tmp_207_reg_6348[15] <= 1'b0;
tmp_207_reg_6348[16] <= 1'b0;
tmp_207_reg_6348[17] <= 1'b0;
tmp_207_reg_6348[18] <= 1'b0;
tmp_207_reg_6348[19] <= 1'b0;
tmp_207_reg_6348[20] <= 1'b0;
tmp_207_reg_6348[21] <= 1'b0;
tmp_207_reg_6348[22] <= 1'b0;
tmp_207_reg_6348[23] <= 1'b0;
tmp_207_reg_6348[24] <= 1'b0;
tmp_207_reg_6348[25] <= 1'b0;
tmp_207_reg_6348[26] <= 1'b0;
tmp_207_reg_6348[27] <= 1'b0;
tmp_207_reg_6348[28] <= 1'b0;
tmp_207_reg_6348[29] <= 1'b0;
tmp_207_reg_6348[30] <= 1'b0;
tmp_207_reg_6348[31] <= 1'b0;
tmp_207_reg_6348[32] <= 1'b0;
tmp_207_reg_6348[33] <= 1'b0;
tmp_207_reg_6348[34] <= 1'b0;
tmp_207_reg_6348[35] <= 1'b0;
tmp_207_reg_6348[36] <= 1'b0;
tmp_207_reg_6348[37] <= 1'b0;
tmp_207_reg_6348[38] <= 1'b0;
tmp_207_reg_6348[39] <= 1'b0;
tmp_207_reg_6348[40] <= 1'b0;
tmp_207_reg_6348[41] <= 1'b0;
tmp_207_reg_6348[42] <= 1'b0;
tmp_207_reg_6348[43] <= 1'b0;
tmp_207_reg_6348[44] <= 1'b0;
tmp_207_reg_6348[45] <= 1'b0;
tmp_207_reg_6348[46] <= 1'b0;
tmp_207_reg_6348[47] <= 1'b0;
tmp_207_reg_6348[48] <= 1'b0;
tmp_207_reg_6348[49] <= 1'b0;
tmp_207_reg_6348[50] <= 1'b0;
tmp_207_reg_6348[51] <= 1'b0;
tmp_207_reg_6348[52] <= 1'b0;
tmp_207_reg_6348[53] <= 1'b0;
tmp_207_reg_6348[54] <= 1'b0;
tmp_207_reg_6348[55] <= 1'b0;
tmp_207_reg_6348[56] <= 1'b0;
tmp_207_reg_6348[57] <= 1'b0;
tmp_207_reg_6348[58] <= 1'b0;
tmp_207_reg_6348[59] <= 1'b0;
tmp_207_reg_6348[60] <= 1'b0;
tmp_207_reg_6348[61] <= 1'b0;
tmp_207_reg_6348[62] <= 1'b0;
tmp_207_reg_6348[63] <= 1'b0;
end
always @ (ap_clk)
begin
tmp_208_reg_6363[14] <= 1'b0;
tmp_208_reg_6363[15] <= 1'b0;
tmp_208_reg_6363[16] <= 1'b0;
tmp_208_reg_6363[17] <= 1'b0;
tmp_208_reg_6363[18] <= 1'b0;
tmp_208_reg_6363[19] <= 1'b0;
tmp_208_reg_6363[20] <= 1'b0;
tmp_208_reg_6363[21] <= 1'b0;
tmp_208_reg_6363[22] <= 1'b0;
tmp_208_reg_6363[23] <= 1'b0;
tmp_208_reg_6363[24] <= 1'b0;
tmp_208_reg_6363[25] <= 1'b0;
tmp_208_reg_6363[26] <= 1'b0;
tmp_208_reg_6363[27] <= 1'b0;
tmp_208_reg_6363[28] <= 1'b0;
tmp_208_reg_6363[29] <= 1'b0;
tmp_208_reg_6363[30] <= 1'b0;
tmp_208_reg_6363[31] <= 1'b0;
tmp_208_reg_6363[32] <= 1'b0;
tmp_208_reg_6363[33] <= 1'b0;
tmp_208_reg_6363[34] <= 1'b0;
tmp_208_reg_6363[35] <= 1'b0;
tmp_208_reg_6363[36] <= 1'b0;
tmp_208_reg_6363[37] <= 1'b0;
tmp_208_reg_6363[38] <= 1'b0;
tmp_208_reg_6363[39] <= 1'b0;
tmp_208_reg_6363[40] <= 1'b0;
tmp_208_reg_6363[41] <= 1'b0;
tmp_208_reg_6363[42] <= 1'b0;
tmp_208_reg_6363[43] <= 1'b0;
tmp_208_reg_6363[44] <= 1'b0;
tmp_208_reg_6363[45] <= 1'b0;
tmp_208_reg_6363[46] <= 1'b0;
tmp_208_reg_6363[47] <= 1'b0;
tmp_208_reg_6363[48] <= 1'b0;
tmp_208_reg_6363[49] <= 1'b0;
tmp_208_reg_6363[50] <= 1'b0;
tmp_208_reg_6363[51] <= 1'b0;
tmp_208_reg_6363[52] <= 1'b0;
tmp_208_reg_6363[53] <= 1'b0;
tmp_208_reg_6363[54] <= 1'b0;
tmp_208_reg_6363[55] <= 1'b0;
tmp_208_reg_6363[56] <= 1'b0;
tmp_208_reg_6363[57] <= 1'b0;
tmp_208_reg_6363[58] <= 1'b0;
tmp_208_reg_6363[59] <= 1'b0;
tmp_208_reg_6363[60] <= 1'b0;
tmp_208_reg_6363[61] <= 1'b0;
tmp_208_reg_6363[62] <= 1'b0;
tmp_208_reg_6363[63] <= 1'b0;
end
always @ (ap_clk)
begin
tmp_209_reg_6373[0] <= 1'b1;
tmp_209_reg_6373[1] <= 1'b1;
tmp_209_reg_6373[14] <= 1'b0;
tmp_209_reg_6373[15] <= 1'b0;
tmp_209_reg_6373[16] <= 1'b0;
tmp_209_reg_6373[17] <= 1'b0;
tmp_209_reg_6373[18] <= 1'b0;
tmp_209_reg_6373[19] <= 1'b0;
tmp_209_reg_6373[20] <= 1'b0;
tmp_209_reg_6373[21] <= 1'b0;
tmp_209_reg_6373[22] <= 1'b0;
tmp_209_reg_6373[23] <= 1'b0;
tmp_209_reg_6373[24] <= 1'b0;
tmp_209_reg_6373[25] <= 1'b0;
tmp_209_reg_6373[26] <= 1'b0;
tmp_209_reg_6373[27] <= 1'b0;
tmp_209_reg_6373[28] <= 1'b0;
tmp_209_reg_6373[29] <= 1'b0;
tmp_209_reg_6373[30] <= 1'b0;
tmp_209_reg_6373[31] <= 1'b0;
tmp_209_reg_6373[32] <= 1'b0;
tmp_209_reg_6373[33] <= 1'b0;
tmp_209_reg_6373[34] <= 1'b0;
tmp_209_reg_6373[35] <= 1'b0;
tmp_209_reg_6373[36] <= 1'b0;
tmp_209_reg_6373[37] <= 1'b0;
tmp_209_reg_6373[38] <= 1'b0;
tmp_209_reg_6373[39] <= 1'b0;
tmp_209_reg_6373[40] <= 1'b0;
tmp_209_reg_6373[41] <= 1'b0;
tmp_209_reg_6373[42] <= 1'b0;
tmp_209_reg_6373[43] <= 1'b0;
tmp_209_reg_6373[44] <= 1'b0;
tmp_209_reg_6373[45] <= 1'b0;
tmp_209_reg_6373[46] <= 1'b0;
tmp_209_reg_6373[47] <= 1'b0;
tmp_209_reg_6373[48] <= 1'b0;
tmp_209_reg_6373[49] <= 1'b0;
tmp_209_reg_6373[50] <= 1'b0;
tmp_209_reg_6373[51] <= 1'b0;
tmp_209_reg_6373[52] <= 1'b0;
tmp_209_reg_6373[53] <= 1'b0;
tmp_209_reg_6373[54] <= 1'b0;
tmp_209_reg_6373[55] <= 1'b0;
tmp_209_reg_6373[56] <= 1'b0;
tmp_209_reg_6373[57] <= 1'b0;
tmp_209_reg_6373[58] <= 1'b0;
tmp_209_reg_6373[59] <= 1'b0;
tmp_209_reg_6373[60] <= 1'b0;
tmp_209_reg_6373[61] <= 1'b0;
tmp_209_reg_6373[62] <= 1'b0;
tmp_209_reg_6373[63] <= 1'b0;
end
always @ (ap_clk)
begin
tmp_210_reg_6383[14] <= 1'b0;
tmp_210_reg_6383[15] <= 1'b0;
tmp_210_reg_6383[16] <= 1'b0;
tmp_210_reg_6383[17] <= 1'b0;
tmp_210_reg_6383[18] <= 1'b0;
tmp_210_reg_6383[19] <= 1'b0;
tmp_210_reg_6383[20] <= 1'b0;
tmp_210_reg_6383[21] <= 1'b0;
tmp_210_reg_6383[22] <= 1'b0;
tmp_210_reg_6383[23] <= 1'b0;
tmp_210_reg_6383[24] <= 1'b0;
tmp_210_reg_6383[25] <= 1'b0;
tmp_210_reg_6383[26] <= 1'b0;
tmp_210_reg_6383[27] <= 1'b0;
tmp_210_reg_6383[28] <= 1'b0;
tmp_210_reg_6383[29] <= 1'b0;
tmp_210_reg_6383[30] <= 1'b0;
tmp_210_reg_6383[31] <= 1'b0;
tmp_210_reg_6383[32] <= 1'b0;
tmp_210_reg_6383[33] <= 1'b0;
tmp_210_reg_6383[34] <= 1'b0;
tmp_210_reg_6383[35] <= 1'b0;
tmp_210_reg_6383[36] <= 1'b0;
tmp_210_reg_6383[37] <= 1'b0;
tmp_210_reg_6383[38] <= 1'b0;
tmp_210_reg_6383[39] <= 1'b0;
tmp_210_reg_6383[40] <= 1'b0;
tmp_210_reg_6383[41] <= 1'b0;
tmp_210_reg_6383[42] <= 1'b0;
tmp_210_reg_6383[43] <= 1'b0;
tmp_210_reg_6383[44] <= 1'b0;
tmp_210_reg_6383[45] <= 1'b0;
tmp_210_reg_6383[46] <= 1'b0;
tmp_210_reg_6383[47] <= 1'b0;
tmp_210_reg_6383[48] <= 1'b0;
tmp_210_reg_6383[49] <= 1'b0;
tmp_210_reg_6383[50] <= 1'b0;
tmp_210_reg_6383[51] <= 1'b0;
tmp_210_reg_6383[52] <= 1'b0;
tmp_210_reg_6383[53] <= 1'b0;
tmp_210_reg_6383[54] <= 1'b0;
tmp_210_reg_6383[55] <= 1'b0;
tmp_210_reg_6383[56] <= 1'b0;
tmp_210_reg_6383[57] <= 1'b0;
tmp_210_reg_6383[58] <= 1'b0;
tmp_210_reg_6383[59] <= 1'b0;
tmp_210_reg_6383[60] <= 1'b0;
tmp_210_reg_6383[61] <= 1'b0;
tmp_210_reg_6383[62] <= 1'b0;
tmp_210_reg_6383[63] <= 1'b0;
end
always @ (ap_clk)
begin
tmp_211_reg_6393[0] <= 1'b1;
tmp_211_reg_6393[14] <= 1'b0;
tmp_211_reg_6393[15] <= 1'b0;
tmp_211_reg_6393[16] <= 1'b0;
tmp_211_reg_6393[17] <= 1'b0;
tmp_211_reg_6393[18] <= 1'b0;
tmp_211_reg_6393[19] <= 1'b0;
tmp_211_reg_6393[20] <= 1'b0;
tmp_211_reg_6393[21] <= 1'b0;
tmp_211_reg_6393[22] <= 1'b0;
tmp_211_reg_6393[23] <= 1'b0;
tmp_211_reg_6393[24] <= 1'b0;
tmp_211_reg_6393[25] <= 1'b0;
tmp_211_reg_6393[26] <= 1'b0;
tmp_211_reg_6393[27] <= 1'b0;
tmp_211_reg_6393[28] <= 1'b0;
tmp_211_reg_6393[29] <= 1'b0;
tmp_211_reg_6393[30] <= 1'b0;
tmp_211_reg_6393[31] <= 1'b0;
tmp_211_reg_6393[32] <= 1'b0;
tmp_211_reg_6393[33] <= 1'b0;
tmp_211_reg_6393[34] <= 1'b0;
tmp_211_reg_6393[35] <= 1'b0;
tmp_211_reg_6393[36] <= 1'b0;
tmp_211_reg_6393[37] <= 1'b0;
tmp_211_reg_6393[38] <= 1'b0;
tmp_211_reg_6393[39] <= 1'b0;
tmp_211_reg_6393[40] <= 1'b0;
tmp_211_reg_6393[41] <= 1'b0;
tmp_211_reg_6393[42] <= 1'b0;
tmp_211_reg_6393[43] <= 1'b0;
tmp_211_reg_6393[44] <= 1'b0;
tmp_211_reg_6393[45] <= 1'b0;
tmp_211_reg_6393[46] <= 1'b0;
tmp_211_reg_6393[47] <= 1'b0;
tmp_211_reg_6393[48] <= 1'b0;
tmp_211_reg_6393[49] <= 1'b0;
tmp_211_reg_6393[50] <= 1'b0;
tmp_211_reg_6393[51] <= 1'b0;
tmp_211_reg_6393[52] <= 1'b0;
tmp_211_reg_6393[53] <= 1'b0;
tmp_211_reg_6393[54] <= 1'b0;
tmp_211_reg_6393[55] <= 1'b0;
tmp_211_reg_6393[56] <= 1'b0;
tmp_211_reg_6393[57] <= 1'b0;
tmp_211_reg_6393[58] <= 1'b0;
tmp_211_reg_6393[59] <= 1'b0;
tmp_211_reg_6393[60] <= 1'b0;
tmp_211_reg_6393[61] <= 1'b0;
tmp_211_reg_6393[62] <= 1'b0;
tmp_211_reg_6393[63] <= 1'b0;
end
always @ (ap_clk)
begin
tmp_212_reg_6403[14] <= 1'b0;
tmp_212_reg_6403[15] <= 1'b0;
tmp_212_reg_6403[16] <= 1'b0;
tmp_212_reg_6403[17] <= 1'b0;
tmp_212_reg_6403[18] <= 1'b0;
tmp_212_reg_6403[19] <= 1'b0;
tmp_212_reg_6403[20] <= 1'b0;
tmp_212_reg_6403[21] <= 1'b0;
tmp_212_reg_6403[22] <= 1'b0;
tmp_212_reg_6403[23] <= 1'b0;
tmp_212_reg_6403[24] <= 1'b0;
tmp_212_reg_6403[25] <= 1'b0;
tmp_212_reg_6403[26] <= 1'b0;
tmp_212_reg_6403[27] <= 1'b0;
tmp_212_reg_6403[28] <= 1'b0;
tmp_212_reg_6403[29] <= 1'b0;
tmp_212_reg_6403[30] <= 1'b0;
tmp_212_reg_6403[31] <= 1'b0;
tmp_212_reg_6403[32] <= 1'b0;
tmp_212_reg_6403[33] <= 1'b0;
tmp_212_reg_6403[34] <= 1'b0;
tmp_212_reg_6403[35] <= 1'b0;
tmp_212_reg_6403[36] <= 1'b0;
tmp_212_reg_6403[37] <= 1'b0;
tmp_212_reg_6403[38] <= 1'b0;
tmp_212_reg_6403[39] <= 1'b0;
tmp_212_reg_6403[40] <= 1'b0;
tmp_212_reg_6403[41] <= 1'b0;
tmp_212_reg_6403[42] <= 1'b0;
tmp_212_reg_6403[43] <= 1'b0;
tmp_212_reg_6403[44] <= 1'b0;
tmp_212_reg_6403[45] <= 1'b0;
tmp_212_reg_6403[46] <= 1'b0;
tmp_212_reg_6403[47] <= 1'b0;
tmp_212_reg_6403[48] <= 1'b0;
tmp_212_reg_6403[49] <= 1'b0;
tmp_212_reg_6403[50] <= 1'b0;
tmp_212_reg_6403[51] <= 1'b0;
tmp_212_reg_6403[52] <= 1'b0;
tmp_212_reg_6403[53] <= 1'b0;
tmp_212_reg_6403[54] <= 1'b0;
tmp_212_reg_6403[55] <= 1'b0;
tmp_212_reg_6403[56] <= 1'b0;
tmp_212_reg_6403[57] <= 1'b0;
tmp_212_reg_6403[58] <= 1'b0;
tmp_212_reg_6403[59] <= 1'b0;
tmp_212_reg_6403[60] <= 1'b0;
tmp_212_reg_6403[61] <= 1'b0;
tmp_212_reg_6403[62] <= 1'b0;
tmp_212_reg_6403[63] <= 1'b0;
end
always @ (ap_clk)
begin
tmp_213_reg_6413[0] <= 1'b1;
tmp_213_reg_6413[1] <= 1'b1;
tmp_213_reg_6413[2] <= 1'b1;
tmp_213_reg_6413[14] <= 1'b0;
tmp_213_reg_6413[15] <= 1'b0;
tmp_213_reg_6413[16] <= 1'b0;
tmp_213_reg_6413[17] <= 1'b0;
tmp_213_reg_6413[18] <= 1'b0;
tmp_213_reg_6413[19] <= 1'b0;
tmp_213_reg_6413[20] <= 1'b0;
tmp_213_reg_6413[21] <= 1'b0;
tmp_213_reg_6413[22] <= 1'b0;
tmp_213_reg_6413[23] <= 1'b0;
tmp_213_reg_6413[24] <= 1'b0;
tmp_213_reg_6413[25] <= 1'b0;
tmp_213_reg_6413[26] <= 1'b0;
tmp_213_reg_6413[27] <= 1'b0;
tmp_213_reg_6413[28] <= 1'b0;
tmp_213_reg_6413[29] <= 1'b0;
tmp_213_reg_6413[30] <= 1'b0;
tmp_213_reg_6413[31] <= 1'b0;
tmp_213_reg_6413[32] <= 1'b0;
tmp_213_reg_6413[33] <= 1'b0;
tmp_213_reg_6413[34] <= 1'b0;
tmp_213_reg_6413[35] <= 1'b0;
tmp_213_reg_6413[36] <= 1'b0;
tmp_213_reg_6413[37] <= 1'b0;
tmp_213_reg_6413[38] <= 1'b0;
tmp_213_reg_6413[39] <= 1'b0;
tmp_213_reg_6413[40] <= 1'b0;
tmp_213_reg_6413[41] <= 1'b0;
tmp_213_reg_6413[42] <= 1'b0;
tmp_213_reg_6413[43] <= 1'b0;
tmp_213_reg_6413[44] <= 1'b0;
tmp_213_reg_6413[45] <= 1'b0;
tmp_213_reg_6413[46] <= 1'b0;
tmp_213_reg_6413[47] <= 1'b0;
tmp_213_reg_6413[48] <= 1'b0;
tmp_213_reg_6413[49] <= 1'b0;
tmp_213_reg_6413[50] <= 1'b0;
tmp_213_reg_6413[51] <= 1'b0;
tmp_213_reg_6413[52] <= 1'b0;
tmp_213_reg_6413[53] <= 1'b0;
tmp_213_reg_6413[54] <= 1'b0;
tmp_213_reg_6413[55] <= 1'b0;
tmp_213_reg_6413[56] <= 1'b0;
tmp_213_reg_6413[57] <= 1'b0;
tmp_213_reg_6413[58] <= 1'b0;
tmp_213_reg_6413[59] <= 1'b0;
tmp_213_reg_6413[60] <= 1'b0;
tmp_213_reg_6413[61] <= 1'b0;
tmp_213_reg_6413[62] <= 1'b0;
tmp_213_reg_6413[63] <= 1'b0;
end
always @ (ap_clk)
begin
a_addr87_cast_reg_6423[0] <= 1'b0;
a_addr87_cast_reg_6423[1] <= 1'b0;
a_addr87_cast_reg_6423[2] <= 1'b0;
a_addr87_cast_reg_6423[3] <= 1'b0;
a_addr87_cast_reg_6423[4] <= 1'b0;
a_addr87_cast_reg_6423[5] <= 1'b0;
a_addr87_cast_reg_6423[7] <= 1'b1;
a_addr87_cast_reg_6423[13] <= 1'b0;
end
always @ (ap_clk)
begin
tmp_214_reg_6432[0] <= 1'b1;
tmp_214_reg_6432[14] <= 1'b0;
tmp_214_reg_6432[15] <= 1'b0;
tmp_214_reg_6432[16] <= 1'b0;
tmp_214_reg_6432[17] <= 1'b0;
tmp_214_reg_6432[18] <= 1'b0;
tmp_214_reg_6432[19] <= 1'b0;
tmp_214_reg_6432[20] <= 1'b0;
tmp_214_reg_6432[21] <= 1'b0;
tmp_214_reg_6432[22] <= 1'b0;
tmp_214_reg_6432[23] <= 1'b0;
tmp_214_reg_6432[24] <= 1'b0;
tmp_214_reg_6432[25] <= 1'b0;
tmp_214_reg_6432[26] <= 1'b0;
tmp_214_reg_6432[27] <= 1'b0;
tmp_214_reg_6432[28] <= 1'b0;
tmp_214_reg_6432[29] <= 1'b0;
tmp_214_reg_6432[30] <= 1'b0;
tmp_214_reg_6432[31] <= 1'b0;
tmp_214_reg_6432[32] <= 1'b0;
tmp_214_reg_6432[33] <= 1'b0;
tmp_214_reg_6432[34] <= 1'b0;
tmp_214_reg_6432[35] <= 1'b0;
tmp_214_reg_6432[36] <= 1'b0;
tmp_214_reg_6432[37] <= 1'b0;
tmp_214_reg_6432[38] <= 1'b0;
tmp_214_reg_6432[39] <= 1'b0;
tmp_214_reg_6432[40] <= 1'b0;
tmp_214_reg_6432[41] <= 1'b0;
tmp_214_reg_6432[42] <= 1'b0;
tmp_214_reg_6432[43] <= 1'b0;
tmp_214_reg_6432[44] <= 1'b0;
tmp_214_reg_6432[45] <= 1'b0;
tmp_214_reg_6432[46] <= 1'b0;
tmp_214_reg_6432[47] <= 1'b0;
tmp_214_reg_6432[48] <= 1'b0;
tmp_214_reg_6432[49] <= 1'b0;
tmp_214_reg_6432[50] <= 1'b0;
tmp_214_reg_6432[51] <= 1'b0;
tmp_214_reg_6432[52] <= 1'b0;
tmp_214_reg_6432[53] <= 1'b0;
tmp_214_reg_6432[54] <= 1'b0;
tmp_214_reg_6432[55] <= 1'b0;
tmp_214_reg_6432[56] <= 1'b0;
tmp_214_reg_6432[57] <= 1'b0;
tmp_214_reg_6432[58] <= 1'b0;
tmp_214_reg_6432[59] <= 1'b0;
tmp_214_reg_6432[60] <= 1'b0;
tmp_214_reg_6432[61] <= 1'b0;
tmp_214_reg_6432[62] <= 1'b0;
tmp_214_reg_6432[63] <= 1'b0;
end
always @ (ap_clk)
begin
tmp_215_reg_6442[14] <= 1'b0;
tmp_215_reg_6442[15] <= 1'b0;
tmp_215_reg_6442[16] <= 1'b0;
tmp_215_reg_6442[17] <= 1'b0;
tmp_215_reg_6442[18] <= 1'b0;
tmp_215_reg_6442[19] <= 1'b0;
tmp_215_reg_6442[20] <= 1'b0;
tmp_215_reg_6442[21] <= 1'b0;
tmp_215_reg_6442[22] <= 1'b0;
tmp_215_reg_6442[23] <= 1'b0;
tmp_215_reg_6442[24] <= 1'b0;
tmp_215_reg_6442[25] <= 1'b0;
tmp_215_reg_6442[26] <= 1'b0;
tmp_215_reg_6442[27] <= 1'b0;
tmp_215_reg_6442[28] <= 1'b0;
tmp_215_reg_6442[29] <= 1'b0;
tmp_215_reg_6442[30] <= 1'b0;
tmp_215_reg_6442[31] <= 1'b0;
tmp_215_reg_6442[32] <= 1'b0;
tmp_215_reg_6442[33] <= 1'b0;
tmp_215_reg_6442[34] <= 1'b0;
tmp_215_reg_6442[35] <= 1'b0;
tmp_215_reg_6442[36] <= 1'b0;
tmp_215_reg_6442[37] <= 1'b0;
tmp_215_reg_6442[38] <= 1'b0;
tmp_215_reg_6442[39] <= 1'b0;
tmp_215_reg_6442[40] <= 1'b0;
tmp_215_reg_6442[41] <= 1'b0;
tmp_215_reg_6442[42] <= 1'b0;
tmp_215_reg_6442[43] <= 1'b0;
tmp_215_reg_6442[44] <= 1'b0;
tmp_215_reg_6442[45] <= 1'b0;
tmp_215_reg_6442[46] <= 1'b0;
tmp_215_reg_6442[47] <= 1'b0;
tmp_215_reg_6442[48] <= 1'b0;
tmp_215_reg_6442[49] <= 1'b0;
tmp_215_reg_6442[50] <= 1'b0;
tmp_215_reg_6442[51] <= 1'b0;
tmp_215_reg_6442[52] <= 1'b0;
tmp_215_reg_6442[53] <= 1'b0;
tmp_215_reg_6442[54] <= 1'b0;
tmp_215_reg_6442[55] <= 1'b0;
tmp_215_reg_6442[56] <= 1'b0;
tmp_215_reg_6442[57] <= 1'b0;
tmp_215_reg_6442[58] <= 1'b0;
tmp_215_reg_6442[59] <= 1'b0;
tmp_215_reg_6442[60] <= 1'b0;
tmp_215_reg_6442[61] <= 1'b0;
tmp_215_reg_6442[62] <= 1'b0;
tmp_215_reg_6442[63] <= 1'b0;
end
always @ (ap_clk)
begin
tmp_216_reg_6452[0] <= 1'b1;
tmp_216_reg_6452[1] <= 1'b1;
tmp_216_reg_6452[14] <= 1'b0;
tmp_216_reg_6452[15] <= 1'b0;
tmp_216_reg_6452[16] <= 1'b0;
tmp_216_reg_6452[17] <= 1'b0;
tmp_216_reg_6452[18] <= 1'b0;
tmp_216_reg_6452[19] <= 1'b0;
tmp_216_reg_6452[20] <= 1'b0;
tmp_216_reg_6452[21] <= 1'b0;
tmp_216_reg_6452[22] <= 1'b0;
tmp_216_reg_6452[23] <= 1'b0;
tmp_216_reg_6452[24] <= 1'b0;
tmp_216_reg_6452[25] <= 1'b0;
tmp_216_reg_6452[26] <= 1'b0;
tmp_216_reg_6452[27] <= 1'b0;
tmp_216_reg_6452[28] <= 1'b0;
tmp_216_reg_6452[29] <= 1'b0;
tmp_216_reg_6452[30] <= 1'b0;
tmp_216_reg_6452[31] <= 1'b0;
tmp_216_reg_6452[32] <= 1'b0;
tmp_216_reg_6452[33] <= 1'b0;
tmp_216_reg_6452[34] <= 1'b0;
tmp_216_reg_6452[35] <= 1'b0;
tmp_216_reg_6452[36] <= 1'b0;
tmp_216_reg_6452[37] <= 1'b0;
tmp_216_reg_6452[38] <= 1'b0;
tmp_216_reg_6452[39] <= 1'b0;
tmp_216_reg_6452[40] <= 1'b0;
tmp_216_reg_6452[41] <= 1'b0;
tmp_216_reg_6452[42] <= 1'b0;
tmp_216_reg_6452[43] <= 1'b0;
tmp_216_reg_6452[44] <= 1'b0;
tmp_216_reg_6452[45] <= 1'b0;
tmp_216_reg_6452[46] <= 1'b0;
tmp_216_reg_6452[47] <= 1'b0;
tmp_216_reg_6452[48] <= 1'b0;
tmp_216_reg_6452[49] <= 1'b0;
tmp_216_reg_6452[50] <= 1'b0;
tmp_216_reg_6452[51] <= 1'b0;
tmp_216_reg_6452[52] <= 1'b0;
tmp_216_reg_6452[53] <= 1'b0;
tmp_216_reg_6452[54] <= 1'b0;
tmp_216_reg_6452[55] <= 1'b0;
tmp_216_reg_6452[56] <= 1'b0;
tmp_216_reg_6452[57] <= 1'b0;
tmp_216_reg_6452[58] <= 1'b0;
tmp_216_reg_6452[59] <= 1'b0;
tmp_216_reg_6452[60] <= 1'b0;
tmp_216_reg_6452[61] <= 1'b0;
tmp_216_reg_6452[62] <= 1'b0;
tmp_216_reg_6452[63] <= 1'b0;
end
always @ (ap_clk)
begin
tmp_217_reg_6462[14] <= 1'b0;
tmp_217_reg_6462[15] <= 1'b0;
tmp_217_reg_6462[16] <= 1'b0;
tmp_217_reg_6462[17] <= 1'b0;
tmp_217_reg_6462[18] <= 1'b0;
tmp_217_reg_6462[19] <= 1'b0;
tmp_217_reg_6462[20] <= 1'b0;
tmp_217_reg_6462[21] <= 1'b0;
tmp_217_reg_6462[22] <= 1'b0;
tmp_217_reg_6462[23] <= 1'b0;
tmp_217_reg_6462[24] <= 1'b0;
tmp_217_reg_6462[25] <= 1'b0;
tmp_217_reg_6462[26] <= 1'b0;
tmp_217_reg_6462[27] <= 1'b0;
tmp_217_reg_6462[28] <= 1'b0;
tmp_217_reg_6462[29] <= 1'b0;
tmp_217_reg_6462[30] <= 1'b0;
tmp_217_reg_6462[31] <= 1'b0;
tmp_217_reg_6462[32] <= 1'b0;
tmp_217_reg_6462[33] <= 1'b0;
tmp_217_reg_6462[34] <= 1'b0;
tmp_217_reg_6462[35] <= 1'b0;
tmp_217_reg_6462[36] <= 1'b0;
tmp_217_reg_6462[37] <= 1'b0;
tmp_217_reg_6462[38] <= 1'b0;
tmp_217_reg_6462[39] <= 1'b0;
tmp_217_reg_6462[40] <= 1'b0;
tmp_217_reg_6462[41] <= 1'b0;
tmp_217_reg_6462[42] <= 1'b0;
tmp_217_reg_6462[43] <= 1'b0;
tmp_217_reg_6462[44] <= 1'b0;
tmp_217_reg_6462[45] <= 1'b0;
tmp_217_reg_6462[46] <= 1'b0;
tmp_217_reg_6462[47] <= 1'b0;
tmp_217_reg_6462[48] <= 1'b0;
tmp_217_reg_6462[49] <= 1'b0;
tmp_217_reg_6462[50] <= 1'b0;
tmp_217_reg_6462[51] <= 1'b0;
tmp_217_reg_6462[52] <= 1'b0;
tmp_217_reg_6462[53] <= 1'b0;
tmp_217_reg_6462[54] <= 1'b0;
tmp_217_reg_6462[55] <= 1'b0;
tmp_217_reg_6462[56] <= 1'b0;
tmp_217_reg_6462[57] <= 1'b0;
tmp_217_reg_6462[58] <= 1'b0;
tmp_217_reg_6462[59] <= 1'b0;
tmp_217_reg_6462[60] <= 1'b0;
tmp_217_reg_6462[61] <= 1'b0;
tmp_217_reg_6462[62] <= 1'b0;
tmp_217_reg_6462[63] <= 1'b0;
end
always @ (ap_clk)
begin
tmp_218_reg_6472[0] <= 1'b1;
tmp_218_reg_6472[14] <= 1'b0;
tmp_218_reg_6472[15] <= 1'b0;
tmp_218_reg_6472[16] <= 1'b0;
tmp_218_reg_6472[17] <= 1'b0;
tmp_218_reg_6472[18] <= 1'b0;
tmp_218_reg_6472[19] <= 1'b0;
tmp_218_reg_6472[20] <= 1'b0;
tmp_218_reg_6472[21] <= 1'b0;
tmp_218_reg_6472[22] <= 1'b0;
tmp_218_reg_6472[23] <= 1'b0;
tmp_218_reg_6472[24] <= 1'b0;
tmp_218_reg_6472[25] <= 1'b0;
tmp_218_reg_6472[26] <= 1'b0;
tmp_218_reg_6472[27] <= 1'b0;
tmp_218_reg_6472[28] <= 1'b0;
tmp_218_reg_6472[29] <= 1'b0;
tmp_218_reg_6472[30] <= 1'b0;
tmp_218_reg_6472[31] <= 1'b0;
tmp_218_reg_6472[32] <= 1'b0;
tmp_218_reg_6472[33] <= 1'b0;
tmp_218_reg_6472[34] <= 1'b0;
tmp_218_reg_6472[35] <= 1'b0;
tmp_218_reg_6472[36] <= 1'b0;
tmp_218_reg_6472[37] <= 1'b0;
tmp_218_reg_6472[38] <= 1'b0;
tmp_218_reg_6472[39] <= 1'b0;
tmp_218_reg_6472[40] <= 1'b0;
tmp_218_reg_6472[41] <= 1'b0;
tmp_218_reg_6472[42] <= 1'b0;
tmp_218_reg_6472[43] <= 1'b0;
tmp_218_reg_6472[44] <= 1'b0;
tmp_218_reg_6472[45] <= 1'b0;
tmp_218_reg_6472[46] <= 1'b0;
tmp_218_reg_6472[47] <= 1'b0;
tmp_218_reg_6472[48] <= 1'b0;
tmp_218_reg_6472[49] <= 1'b0;
tmp_218_reg_6472[50] <= 1'b0;
tmp_218_reg_6472[51] <= 1'b0;
tmp_218_reg_6472[52] <= 1'b0;
tmp_218_reg_6472[53] <= 1'b0;
tmp_218_reg_6472[54] <= 1'b0;
tmp_218_reg_6472[55] <= 1'b0;
tmp_218_reg_6472[56] <= 1'b0;
tmp_218_reg_6472[57] <= 1'b0;
tmp_218_reg_6472[58] <= 1'b0;
tmp_218_reg_6472[59] <= 1'b0;
tmp_218_reg_6472[60] <= 1'b0;
tmp_218_reg_6472[61] <= 1'b0;
tmp_218_reg_6472[62] <= 1'b0;
tmp_218_reg_6472[63] <= 1'b0;
end
always @ (ap_clk)
begin
tmp_219_reg_6482[14] <= 1'b0;
tmp_219_reg_6482[15] <= 1'b0;
tmp_219_reg_6482[16] <= 1'b0;
tmp_219_reg_6482[17] <= 1'b0;
tmp_219_reg_6482[18] <= 1'b0;
tmp_219_reg_6482[19] <= 1'b0;
tmp_219_reg_6482[20] <= 1'b0;
tmp_219_reg_6482[21] <= 1'b0;
tmp_219_reg_6482[22] <= 1'b0;
tmp_219_reg_6482[23] <= 1'b0;
tmp_219_reg_6482[24] <= 1'b0;
tmp_219_reg_6482[25] <= 1'b0;
tmp_219_reg_6482[26] <= 1'b0;
tmp_219_reg_6482[27] <= 1'b0;
tmp_219_reg_6482[28] <= 1'b0;
tmp_219_reg_6482[29] <= 1'b0;
tmp_219_reg_6482[30] <= 1'b0;
tmp_219_reg_6482[31] <= 1'b0;
tmp_219_reg_6482[32] <= 1'b0;
tmp_219_reg_6482[33] <= 1'b0;
tmp_219_reg_6482[34] <= 1'b0;
tmp_219_reg_6482[35] <= 1'b0;
tmp_219_reg_6482[36] <= 1'b0;
tmp_219_reg_6482[37] <= 1'b0;
tmp_219_reg_6482[38] <= 1'b0;
tmp_219_reg_6482[39] <= 1'b0;
tmp_219_reg_6482[40] <= 1'b0;
tmp_219_reg_6482[41] <= 1'b0;
tmp_219_reg_6482[42] <= 1'b0;
tmp_219_reg_6482[43] <= 1'b0;
tmp_219_reg_6482[44] <= 1'b0;
tmp_219_reg_6482[45] <= 1'b0;
tmp_219_reg_6482[46] <= 1'b0;
tmp_219_reg_6482[47] <= 1'b0;
tmp_219_reg_6482[48] <= 1'b0;
tmp_219_reg_6482[49] <= 1'b0;
tmp_219_reg_6482[50] <= 1'b0;
tmp_219_reg_6482[51] <= 1'b0;
tmp_219_reg_6482[52] <= 1'b0;
tmp_219_reg_6482[53] <= 1'b0;
tmp_219_reg_6482[54] <= 1'b0;
tmp_219_reg_6482[55] <= 1'b0;
tmp_219_reg_6482[56] <= 1'b0;
tmp_219_reg_6482[57] <= 1'b0;
tmp_219_reg_6482[58] <= 1'b0;
tmp_219_reg_6482[59] <= 1'b0;
tmp_219_reg_6482[60] <= 1'b0;
tmp_219_reg_6482[61] <= 1'b0;
tmp_219_reg_6482[62] <= 1'b0;
tmp_219_reg_6482[63] <= 1'b0;
end
always @ (ap_clk)
begin
tmp_220_reg_6492[0] <= 1'b1;
tmp_220_reg_6492[1] <= 1'b1;
tmp_220_reg_6492[2] <= 1'b1;
tmp_220_reg_6492[14] <= 1'b0;
tmp_220_reg_6492[15] <= 1'b0;
tmp_220_reg_6492[16] <= 1'b0;
tmp_220_reg_6492[17] <= 1'b0;
tmp_220_reg_6492[18] <= 1'b0;
tmp_220_reg_6492[19] <= 1'b0;
tmp_220_reg_6492[20] <= 1'b0;
tmp_220_reg_6492[21] <= 1'b0;
tmp_220_reg_6492[22] <= 1'b0;
tmp_220_reg_6492[23] <= 1'b0;
tmp_220_reg_6492[24] <= 1'b0;
tmp_220_reg_6492[25] <= 1'b0;
tmp_220_reg_6492[26] <= 1'b0;
tmp_220_reg_6492[27] <= 1'b0;
tmp_220_reg_6492[28] <= 1'b0;
tmp_220_reg_6492[29] <= 1'b0;
tmp_220_reg_6492[30] <= 1'b0;
tmp_220_reg_6492[31] <= 1'b0;
tmp_220_reg_6492[32] <= 1'b0;
tmp_220_reg_6492[33] <= 1'b0;
tmp_220_reg_6492[34] <= 1'b0;
tmp_220_reg_6492[35] <= 1'b0;
tmp_220_reg_6492[36] <= 1'b0;
tmp_220_reg_6492[37] <= 1'b0;
tmp_220_reg_6492[38] <= 1'b0;
tmp_220_reg_6492[39] <= 1'b0;
tmp_220_reg_6492[40] <= 1'b0;
tmp_220_reg_6492[41] <= 1'b0;
tmp_220_reg_6492[42] <= 1'b0;
tmp_220_reg_6492[43] <= 1'b0;
tmp_220_reg_6492[44] <= 1'b0;
tmp_220_reg_6492[45] <= 1'b0;
tmp_220_reg_6492[46] <= 1'b0;
tmp_220_reg_6492[47] <= 1'b0;
tmp_220_reg_6492[48] <= 1'b0;
tmp_220_reg_6492[49] <= 1'b0;
tmp_220_reg_6492[50] <= 1'b0;
tmp_220_reg_6492[51] <= 1'b0;
tmp_220_reg_6492[52] <= 1'b0;
tmp_220_reg_6492[53] <= 1'b0;
tmp_220_reg_6492[54] <= 1'b0;
tmp_220_reg_6492[55] <= 1'b0;
tmp_220_reg_6492[56] <= 1'b0;
tmp_220_reg_6492[57] <= 1'b0;
tmp_220_reg_6492[58] <= 1'b0;
tmp_220_reg_6492[59] <= 1'b0;
tmp_220_reg_6492[60] <= 1'b0;
tmp_220_reg_6492[61] <= 1'b0;
tmp_220_reg_6492[62] <= 1'b0;
tmp_220_reg_6492[63] <= 1'b0;
end
always @ (ap_clk)
begin
a_addr98_cast_reg_6502[0] <= 1'b0;
a_addr98_cast_reg_6502[1] <= 1'b0;
a_addr98_cast_reg_6502[2] <= 1'b0;
a_addr98_cast_reg_6502[3] <= 1'b0;
a_addr98_cast_reg_6502[4] <= 1'b0;
a_addr98_cast_reg_6502[5] <= 1'b0;
a_addr98_cast_reg_6502[6] <= 1'b1;
a_addr98_cast_reg_6502[7] <= 1'b1;
a_addr98_cast_reg_6502[13] <= 1'b0;
end
always @ (ap_clk)
begin
tmp_221_reg_6512[0] <= 1'b1;
tmp_221_reg_6512[14] <= 1'b0;
tmp_221_reg_6512[15] <= 1'b0;
tmp_221_reg_6512[16] <= 1'b0;
tmp_221_reg_6512[17] <= 1'b0;
tmp_221_reg_6512[18] <= 1'b0;
tmp_221_reg_6512[19] <= 1'b0;
tmp_221_reg_6512[20] <= 1'b0;
tmp_221_reg_6512[21] <= 1'b0;
tmp_221_reg_6512[22] <= 1'b0;
tmp_221_reg_6512[23] <= 1'b0;
tmp_221_reg_6512[24] <= 1'b0;
tmp_221_reg_6512[25] <= 1'b0;
tmp_221_reg_6512[26] <= 1'b0;
tmp_221_reg_6512[27] <= 1'b0;
tmp_221_reg_6512[28] <= 1'b0;
tmp_221_reg_6512[29] <= 1'b0;
tmp_221_reg_6512[30] <= 1'b0;
tmp_221_reg_6512[31] <= 1'b0;
tmp_221_reg_6512[32] <= 1'b0;
tmp_221_reg_6512[33] <= 1'b0;
tmp_221_reg_6512[34] <= 1'b0;
tmp_221_reg_6512[35] <= 1'b0;
tmp_221_reg_6512[36] <= 1'b0;
tmp_221_reg_6512[37] <= 1'b0;
tmp_221_reg_6512[38] <= 1'b0;
tmp_221_reg_6512[39] <= 1'b0;
tmp_221_reg_6512[40] <= 1'b0;
tmp_221_reg_6512[41] <= 1'b0;
tmp_221_reg_6512[42] <= 1'b0;
tmp_221_reg_6512[43] <= 1'b0;
tmp_221_reg_6512[44] <= 1'b0;
tmp_221_reg_6512[45] <= 1'b0;
tmp_221_reg_6512[46] <= 1'b0;
tmp_221_reg_6512[47] <= 1'b0;
tmp_221_reg_6512[48] <= 1'b0;
tmp_221_reg_6512[49] <= 1'b0;
tmp_221_reg_6512[50] <= 1'b0;
tmp_221_reg_6512[51] <= 1'b0;
tmp_221_reg_6512[52] <= 1'b0;
tmp_221_reg_6512[53] <= 1'b0;
tmp_221_reg_6512[54] <= 1'b0;
tmp_221_reg_6512[55] <= 1'b0;
tmp_221_reg_6512[56] <= 1'b0;
tmp_221_reg_6512[57] <= 1'b0;
tmp_221_reg_6512[58] <= 1'b0;
tmp_221_reg_6512[59] <= 1'b0;
tmp_221_reg_6512[60] <= 1'b0;
tmp_221_reg_6512[61] <= 1'b0;
tmp_221_reg_6512[62] <= 1'b0;
tmp_221_reg_6512[63] <= 1'b0;
end
always @ (ap_clk)
begin
tmp_222_reg_6522[14] <= 1'b0;
tmp_222_reg_6522[15] <= 1'b0;
tmp_222_reg_6522[16] <= 1'b0;
tmp_222_reg_6522[17] <= 1'b0;
tmp_222_reg_6522[18] <= 1'b0;
tmp_222_reg_6522[19] <= 1'b0;
tmp_222_reg_6522[20] <= 1'b0;
tmp_222_reg_6522[21] <= 1'b0;
tmp_222_reg_6522[22] <= 1'b0;
tmp_222_reg_6522[23] <= 1'b0;
tmp_222_reg_6522[24] <= 1'b0;
tmp_222_reg_6522[25] <= 1'b0;
tmp_222_reg_6522[26] <= 1'b0;
tmp_222_reg_6522[27] <= 1'b0;
tmp_222_reg_6522[28] <= 1'b0;
tmp_222_reg_6522[29] <= 1'b0;
tmp_222_reg_6522[30] <= 1'b0;
tmp_222_reg_6522[31] <= 1'b0;
tmp_222_reg_6522[32] <= 1'b0;
tmp_222_reg_6522[33] <= 1'b0;
tmp_222_reg_6522[34] <= 1'b0;
tmp_222_reg_6522[35] <= 1'b0;
tmp_222_reg_6522[36] <= 1'b0;
tmp_222_reg_6522[37] <= 1'b0;
tmp_222_reg_6522[38] <= 1'b0;
tmp_222_reg_6522[39] <= 1'b0;
tmp_222_reg_6522[40] <= 1'b0;
tmp_222_reg_6522[41] <= 1'b0;
tmp_222_reg_6522[42] <= 1'b0;
tmp_222_reg_6522[43] <= 1'b0;
tmp_222_reg_6522[44] <= 1'b0;
tmp_222_reg_6522[45] <= 1'b0;
tmp_222_reg_6522[46] <= 1'b0;
tmp_222_reg_6522[47] <= 1'b0;
tmp_222_reg_6522[48] <= 1'b0;
tmp_222_reg_6522[49] <= 1'b0;
tmp_222_reg_6522[50] <= 1'b0;
tmp_222_reg_6522[51] <= 1'b0;
tmp_222_reg_6522[52] <= 1'b0;
tmp_222_reg_6522[53] <= 1'b0;
tmp_222_reg_6522[54] <= 1'b0;
tmp_222_reg_6522[55] <= 1'b0;
tmp_222_reg_6522[56] <= 1'b0;
tmp_222_reg_6522[57] <= 1'b0;
tmp_222_reg_6522[58] <= 1'b0;
tmp_222_reg_6522[59] <= 1'b0;
tmp_222_reg_6522[60] <= 1'b0;
tmp_222_reg_6522[61] <= 1'b0;
tmp_222_reg_6522[62] <= 1'b0;
tmp_222_reg_6522[63] <= 1'b0;
end
always @ (ap_clk)
begin
tmp_223_reg_6532[0] <= 1'b1;
tmp_223_reg_6532[1] <= 1'b1;
tmp_223_reg_6532[14] <= 1'b0;
tmp_223_reg_6532[15] <= 1'b0;
tmp_223_reg_6532[16] <= 1'b0;
tmp_223_reg_6532[17] <= 1'b0;
tmp_223_reg_6532[18] <= 1'b0;
tmp_223_reg_6532[19] <= 1'b0;
tmp_223_reg_6532[20] <= 1'b0;
tmp_223_reg_6532[21] <= 1'b0;
tmp_223_reg_6532[22] <= 1'b0;
tmp_223_reg_6532[23] <= 1'b0;
tmp_223_reg_6532[24] <= 1'b0;
tmp_223_reg_6532[25] <= 1'b0;
tmp_223_reg_6532[26] <= 1'b0;
tmp_223_reg_6532[27] <= 1'b0;
tmp_223_reg_6532[28] <= 1'b0;
tmp_223_reg_6532[29] <= 1'b0;
tmp_223_reg_6532[30] <= 1'b0;
tmp_223_reg_6532[31] <= 1'b0;
tmp_223_reg_6532[32] <= 1'b0;
tmp_223_reg_6532[33] <= 1'b0;
tmp_223_reg_6532[34] <= 1'b0;
tmp_223_reg_6532[35] <= 1'b0;
tmp_223_reg_6532[36] <= 1'b0;
tmp_223_reg_6532[37] <= 1'b0;
tmp_223_reg_6532[38] <= 1'b0;
tmp_223_reg_6532[39] <= 1'b0;
tmp_223_reg_6532[40] <= 1'b0;
tmp_223_reg_6532[41] <= 1'b0;
tmp_223_reg_6532[42] <= 1'b0;
tmp_223_reg_6532[43] <= 1'b0;
tmp_223_reg_6532[44] <= 1'b0;
tmp_223_reg_6532[45] <= 1'b0;
tmp_223_reg_6532[46] <= 1'b0;
tmp_223_reg_6532[47] <= 1'b0;
tmp_223_reg_6532[48] <= 1'b0;
tmp_223_reg_6532[49] <= 1'b0;
tmp_223_reg_6532[50] <= 1'b0;
tmp_223_reg_6532[51] <= 1'b0;
tmp_223_reg_6532[52] <= 1'b0;
tmp_223_reg_6532[53] <= 1'b0;
tmp_223_reg_6532[54] <= 1'b0;
tmp_223_reg_6532[55] <= 1'b0;
tmp_223_reg_6532[56] <= 1'b0;
tmp_223_reg_6532[57] <= 1'b0;
tmp_223_reg_6532[58] <= 1'b0;
tmp_223_reg_6532[59] <= 1'b0;
tmp_223_reg_6532[60] <= 1'b0;
tmp_223_reg_6532[61] <= 1'b0;
tmp_223_reg_6532[62] <= 1'b0;
tmp_223_reg_6532[63] <= 1'b0;
end
always @ (ap_clk)
begin
tmp_224_reg_6542[14] <= 1'b0;
tmp_224_reg_6542[15] <= 1'b0;
tmp_224_reg_6542[16] <= 1'b0;
tmp_224_reg_6542[17] <= 1'b0;
tmp_224_reg_6542[18] <= 1'b0;
tmp_224_reg_6542[19] <= 1'b0;
tmp_224_reg_6542[20] <= 1'b0;
tmp_224_reg_6542[21] <= 1'b0;
tmp_224_reg_6542[22] <= 1'b0;
tmp_224_reg_6542[23] <= 1'b0;
tmp_224_reg_6542[24] <= 1'b0;
tmp_224_reg_6542[25] <= 1'b0;
tmp_224_reg_6542[26] <= 1'b0;
tmp_224_reg_6542[27] <= 1'b0;
tmp_224_reg_6542[28] <= 1'b0;
tmp_224_reg_6542[29] <= 1'b0;
tmp_224_reg_6542[30] <= 1'b0;
tmp_224_reg_6542[31] <= 1'b0;
tmp_224_reg_6542[32] <= 1'b0;
tmp_224_reg_6542[33] <= 1'b0;
tmp_224_reg_6542[34] <= 1'b0;
tmp_224_reg_6542[35] <= 1'b0;
tmp_224_reg_6542[36] <= 1'b0;
tmp_224_reg_6542[37] <= 1'b0;
tmp_224_reg_6542[38] <= 1'b0;
tmp_224_reg_6542[39] <= 1'b0;
tmp_224_reg_6542[40] <= 1'b0;
tmp_224_reg_6542[41] <= 1'b0;
tmp_224_reg_6542[42] <= 1'b0;
tmp_224_reg_6542[43] <= 1'b0;
tmp_224_reg_6542[44] <= 1'b0;
tmp_224_reg_6542[45] <= 1'b0;
tmp_224_reg_6542[46] <= 1'b0;
tmp_224_reg_6542[47] <= 1'b0;
tmp_224_reg_6542[48] <= 1'b0;
tmp_224_reg_6542[49] <= 1'b0;
tmp_224_reg_6542[50] <= 1'b0;
tmp_224_reg_6542[51] <= 1'b0;
tmp_224_reg_6542[52] <= 1'b0;
tmp_224_reg_6542[53] <= 1'b0;
tmp_224_reg_6542[54] <= 1'b0;
tmp_224_reg_6542[55] <= 1'b0;
tmp_224_reg_6542[56] <= 1'b0;
tmp_224_reg_6542[57] <= 1'b0;
tmp_224_reg_6542[58] <= 1'b0;
tmp_224_reg_6542[59] <= 1'b0;
tmp_224_reg_6542[60] <= 1'b0;
tmp_224_reg_6542[61] <= 1'b0;
tmp_224_reg_6542[62] <= 1'b0;
tmp_224_reg_6542[63] <= 1'b0;
end
always @ (ap_clk)
begin
tmp_225_reg_6552[0] <= 1'b1;
tmp_225_reg_6552[14] <= 1'b0;
tmp_225_reg_6552[15] <= 1'b0;
tmp_225_reg_6552[16] <= 1'b0;
tmp_225_reg_6552[17] <= 1'b0;
tmp_225_reg_6552[18] <= 1'b0;
tmp_225_reg_6552[19] <= 1'b0;
tmp_225_reg_6552[20] <= 1'b0;
tmp_225_reg_6552[21] <= 1'b0;
tmp_225_reg_6552[22] <= 1'b0;
tmp_225_reg_6552[23] <= 1'b0;
tmp_225_reg_6552[24] <= 1'b0;
tmp_225_reg_6552[25] <= 1'b0;
tmp_225_reg_6552[26] <= 1'b0;
tmp_225_reg_6552[27] <= 1'b0;
tmp_225_reg_6552[28] <= 1'b0;
tmp_225_reg_6552[29] <= 1'b0;
tmp_225_reg_6552[30] <= 1'b0;
tmp_225_reg_6552[31] <= 1'b0;
tmp_225_reg_6552[32] <= 1'b0;
tmp_225_reg_6552[33] <= 1'b0;
tmp_225_reg_6552[34] <= 1'b0;
tmp_225_reg_6552[35] <= 1'b0;
tmp_225_reg_6552[36] <= 1'b0;
tmp_225_reg_6552[37] <= 1'b0;
tmp_225_reg_6552[38] <= 1'b0;
tmp_225_reg_6552[39] <= 1'b0;
tmp_225_reg_6552[40] <= 1'b0;
tmp_225_reg_6552[41] <= 1'b0;
tmp_225_reg_6552[42] <= 1'b0;
tmp_225_reg_6552[43] <= 1'b0;
tmp_225_reg_6552[44] <= 1'b0;
tmp_225_reg_6552[45] <= 1'b0;
tmp_225_reg_6552[46] <= 1'b0;
tmp_225_reg_6552[47] <= 1'b0;
tmp_225_reg_6552[48] <= 1'b0;
tmp_225_reg_6552[49] <= 1'b0;
tmp_225_reg_6552[50] <= 1'b0;
tmp_225_reg_6552[51] <= 1'b0;
tmp_225_reg_6552[52] <= 1'b0;
tmp_225_reg_6552[53] <= 1'b0;
tmp_225_reg_6552[54] <= 1'b0;
tmp_225_reg_6552[55] <= 1'b0;
tmp_225_reg_6552[56] <= 1'b0;
tmp_225_reg_6552[57] <= 1'b0;
tmp_225_reg_6552[58] <= 1'b0;
tmp_225_reg_6552[59] <= 1'b0;
tmp_225_reg_6552[60] <= 1'b0;
tmp_225_reg_6552[61] <= 1'b0;
tmp_225_reg_6552[62] <= 1'b0;
tmp_225_reg_6552[63] <= 1'b0;
end
always @ (ap_clk)
begin
tmp_226_reg_6562[14] <= 1'b0;
tmp_226_reg_6562[15] <= 1'b0;
tmp_226_reg_6562[16] <= 1'b0;
tmp_226_reg_6562[17] <= 1'b0;
tmp_226_reg_6562[18] <= 1'b0;
tmp_226_reg_6562[19] <= 1'b0;
tmp_226_reg_6562[20] <= 1'b0;
tmp_226_reg_6562[21] <= 1'b0;
tmp_226_reg_6562[22] <= 1'b0;
tmp_226_reg_6562[23] <= 1'b0;
tmp_226_reg_6562[24] <= 1'b0;
tmp_226_reg_6562[25] <= 1'b0;
tmp_226_reg_6562[26] <= 1'b0;
tmp_226_reg_6562[27] <= 1'b0;
tmp_226_reg_6562[28] <= 1'b0;
tmp_226_reg_6562[29] <= 1'b0;
tmp_226_reg_6562[30] <= 1'b0;
tmp_226_reg_6562[31] <= 1'b0;
tmp_226_reg_6562[32] <= 1'b0;
tmp_226_reg_6562[33] <= 1'b0;
tmp_226_reg_6562[34] <= 1'b0;
tmp_226_reg_6562[35] <= 1'b0;
tmp_226_reg_6562[36] <= 1'b0;
tmp_226_reg_6562[37] <= 1'b0;
tmp_226_reg_6562[38] <= 1'b0;
tmp_226_reg_6562[39] <= 1'b0;
tmp_226_reg_6562[40] <= 1'b0;
tmp_226_reg_6562[41] <= 1'b0;
tmp_226_reg_6562[42] <= 1'b0;
tmp_226_reg_6562[43] <= 1'b0;
tmp_226_reg_6562[44] <= 1'b0;
tmp_226_reg_6562[45] <= 1'b0;
tmp_226_reg_6562[46] <= 1'b0;
tmp_226_reg_6562[47] <= 1'b0;
tmp_226_reg_6562[48] <= 1'b0;
tmp_226_reg_6562[49] <= 1'b0;
tmp_226_reg_6562[50] <= 1'b0;
tmp_226_reg_6562[51] <= 1'b0;
tmp_226_reg_6562[52] <= 1'b0;
tmp_226_reg_6562[53] <= 1'b0;
tmp_226_reg_6562[54] <= 1'b0;
tmp_226_reg_6562[55] <= 1'b0;
tmp_226_reg_6562[56] <= 1'b0;
tmp_226_reg_6562[57] <= 1'b0;
tmp_226_reg_6562[58] <= 1'b0;
tmp_226_reg_6562[59] <= 1'b0;
tmp_226_reg_6562[60] <= 1'b0;
tmp_226_reg_6562[61] <= 1'b0;
tmp_226_reg_6562[62] <= 1'b0;
tmp_226_reg_6562[63] <= 1'b0;
end
always @ (ap_clk)
begin
tmp_227_reg_6572[0] <= 1'b1;
tmp_227_reg_6572[1] <= 1'b1;
tmp_227_reg_6572[2] <= 1'b1;
tmp_227_reg_6572[14] <= 1'b0;
tmp_227_reg_6572[15] <= 1'b0;
tmp_227_reg_6572[16] <= 1'b0;
tmp_227_reg_6572[17] <= 1'b0;
tmp_227_reg_6572[18] <= 1'b0;
tmp_227_reg_6572[19] <= 1'b0;
tmp_227_reg_6572[20] <= 1'b0;
tmp_227_reg_6572[21] <= 1'b0;
tmp_227_reg_6572[22] <= 1'b0;
tmp_227_reg_6572[23] <= 1'b0;
tmp_227_reg_6572[24] <= 1'b0;
tmp_227_reg_6572[25] <= 1'b0;
tmp_227_reg_6572[26] <= 1'b0;
tmp_227_reg_6572[27] <= 1'b0;
tmp_227_reg_6572[28] <= 1'b0;
tmp_227_reg_6572[29] <= 1'b0;
tmp_227_reg_6572[30] <= 1'b0;
tmp_227_reg_6572[31] <= 1'b0;
tmp_227_reg_6572[32] <= 1'b0;
tmp_227_reg_6572[33] <= 1'b0;
tmp_227_reg_6572[34] <= 1'b0;
tmp_227_reg_6572[35] <= 1'b0;
tmp_227_reg_6572[36] <= 1'b0;
tmp_227_reg_6572[37] <= 1'b0;
tmp_227_reg_6572[38] <= 1'b0;
tmp_227_reg_6572[39] <= 1'b0;
tmp_227_reg_6572[40] <= 1'b0;
tmp_227_reg_6572[41] <= 1'b0;
tmp_227_reg_6572[42] <= 1'b0;
tmp_227_reg_6572[43] <= 1'b0;
tmp_227_reg_6572[44] <= 1'b0;
tmp_227_reg_6572[45] <= 1'b0;
tmp_227_reg_6572[46] <= 1'b0;
tmp_227_reg_6572[47] <= 1'b0;
tmp_227_reg_6572[48] <= 1'b0;
tmp_227_reg_6572[49] <= 1'b0;
tmp_227_reg_6572[50] <= 1'b0;
tmp_227_reg_6572[51] <= 1'b0;
tmp_227_reg_6572[52] <= 1'b0;
tmp_227_reg_6572[53] <= 1'b0;
tmp_227_reg_6572[54] <= 1'b0;
tmp_227_reg_6572[55] <= 1'b0;
tmp_227_reg_6572[56] <= 1'b0;
tmp_227_reg_6572[57] <= 1'b0;
tmp_227_reg_6572[58] <= 1'b0;
tmp_227_reg_6572[59] <= 1'b0;
tmp_227_reg_6572[60] <= 1'b0;
tmp_227_reg_6572[61] <= 1'b0;
tmp_227_reg_6572[62] <= 1'b0;
tmp_227_reg_6572[63] <= 1'b0;
end
always @ (ap_clk)
begin
a_addr99_cast_reg_6582[0] <= 1'b0;
a_addr99_cast_reg_6582[1] <= 1'b0;
a_addr99_cast_reg_6582[2] <= 1'b0;
a_addr99_cast_reg_6582[3] <= 1'b0;
a_addr99_cast_reg_6582[4] <= 1'b0;
a_addr99_cast_reg_6582[5] <= 1'b0;
a_addr99_cast_reg_6582[8] <= 1'b1;
a_addr99_cast_reg_6582[13] <= 1'b0;
end
always @ (ap_clk)
begin
tmp_228_reg_6591[0] <= 1'b1;
tmp_228_reg_6591[14] <= 1'b0;
tmp_228_reg_6591[15] <= 1'b0;
tmp_228_reg_6591[16] <= 1'b0;
tmp_228_reg_6591[17] <= 1'b0;
tmp_228_reg_6591[18] <= 1'b0;
tmp_228_reg_6591[19] <= 1'b0;
tmp_228_reg_6591[20] <= 1'b0;
tmp_228_reg_6591[21] <= 1'b0;
tmp_228_reg_6591[22] <= 1'b0;
tmp_228_reg_6591[23] <= 1'b0;
tmp_228_reg_6591[24] <= 1'b0;
tmp_228_reg_6591[25] <= 1'b0;
tmp_228_reg_6591[26] <= 1'b0;
tmp_228_reg_6591[27] <= 1'b0;
tmp_228_reg_6591[28] <= 1'b0;
tmp_228_reg_6591[29] <= 1'b0;
tmp_228_reg_6591[30] <= 1'b0;
tmp_228_reg_6591[31] <= 1'b0;
tmp_228_reg_6591[32] <= 1'b0;
tmp_228_reg_6591[33] <= 1'b0;
tmp_228_reg_6591[34] <= 1'b0;
tmp_228_reg_6591[35] <= 1'b0;
tmp_228_reg_6591[36] <= 1'b0;
tmp_228_reg_6591[37] <= 1'b0;
tmp_228_reg_6591[38] <= 1'b0;
tmp_228_reg_6591[39] <= 1'b0;
tmp_228_reg_6591[40] <= 1'b0;
tmp_228_reg_6591[41] <= 1'b0;
tmp_228_reg_6591[42] <= 1'b0;
tmp_228_reg_6591[43] <= 1'b0;
tmp_228_reg_6591[44] <= 1'b0;
tmp_228_reg_6591[45] <= 1'b0;
tmp_228_reg_6591[46] <= 1'b0;
tmp_228_reg_6591[47] <= 1'b0;
tmp_228_reg_6591[48] <= 1'b0;
tmp_228_reg_6591[49] <= 1'b0;
tmp_228_reg_6591[50] <= 1'b0;
tmp_228_reg_6591[51] <= 1'b0;
tmp_228_reg_6591[52] <= 1'b0;
tmp_228_reg_6591[53] <= 1'b0;
tmp_228_reg_6591[54] <= 1'b0;
tmp_228_reg_6591[55] <= 1'b0;
tmp_228_reg_6591[56] <= 1'b0;
tmp_228_reg_6591[57] <= 1'b0;
tmp_228_reg_6591[58] <= 1'b0;
tmp_228_reg_6591[59] <= 1'b0;
tmp_228_reg_6591[60] <= 1'b0;
tmp_228_reg_6591[61] <= 1'b0;
tmp_228_reg_6591[62] <= 1'b0;
tmp_228_reg_6591[63] <= 1'b0;
end
always @ (ap_clk)
begin
tmp_229_reg_6601[14] <= 1'b0;
tmp_229_reg_6601[15] <= 1'b0;
tmp_229_reg_6601[16] <= 1'b0;
tmp_229_reg_6601[17] <= 1'b0;
tmp_229_reg_6601[18] <= 1'b0;
tmp_229_reg_6601[19] <= 1'b0;
tmp_229_reg_6601[20] <= 1'b0;
tmp_229_reg_6601[21] <= 1'b0;
tmp_229_reg_6601[22] <= 1'b0;
tmp_229_reg_6601[23] <= 1'b0;
tmp_229_reg_6601[24] <= 1'b0;
tmp_229_reg_6601[25] <= 1'b0;
tmp_229_reg_6601[26] <= 1'b0;
tmp_229_reg_6601[27] <= 1'b0;
tmp_229_reg_6601[28] <= 1'b0;
tmp_229_reg_6601[29] <= 1'b0;
tmp_229_reg_6601[30] <= 1'b0;
tmp_229_reg_6601[31] <= 1'b0;
tmp_229_reg_6601[32] <= 1'b0;
tmp_229_reg_6601[33] <= 1'b0;
tmp_229_reg_6601[34] <= 1'b0;
tmp_229_reg_6601[35] <= 1'b0;
tmp_229_reg_6601[36] <= 1'b0;
tmp_229_reg_6601[37] <= 1'b0;
tmp_229_reg_6601[38] <= 1'b0;
tmp_229_reg_6601[39] <= 1'b0;
tmp_229_reg_6601[40] <= 1'b0;
tmp_229_reg_6601[41] <= 1'b0;
tmp_229_reg_6601[42] <= 1'b0;
tmp_229_reg_6601[43] <= 1'b0;
tmp_229_reg_6601[44] <= 1'b0;
tmp_229_reg_6601[45] <= 1'b0;
tmp_229_reg_6601[46] <= 1'b0;
tmp_229_reg_6601[47] <= 1'b0;
tmp_229_reg_6601[48] <= 1'b0;
tmp_229_reg_6601[49] <= 1'b0;
tmp_229_reg_6601[50] <= 1'b0;
tmp_229_reg_6601[51] <= 1'b0;
tmp_229_reg_6601[52] <= 1'b0;
tmp_229_reg_6601[53] <= 1'b0;
tmp_229_reg_6601[54] <= 1'b0;
tmp_229_reg_6601[55] <= 1'b0;
tmp_229_reg_6601[56] <= 1'b0;
tmp_229_reg_6601[57] <= 1'b0;
tmp_229_reg_6601[58] <= 1'b0;
tmp_229_reg_6601[59] <= 1'b0;
tmp_229_reg_6601[60] <= 1'b0;
tmp_229_reg_6601[61] <= 1'b0;
tmp_229_reg_6601[62] <= 1'b0;
tmp_229_reg_6601[63] <= 1'b0;
end
always @ (ap_clk)
begin
tmp_230_reg_6611[0] <= 1'b1;
tmp_230_reg_6611[1] <= 1'b1;
tmp_230_reg_6611[14] <= 1'b0;
tmp_230_reg_6611[15] <= 1'b0;
tmp_230_reg_6611[16] <= 1'b0;
tmp_230_reg_6611[17] <= 1'b0;
tmp_230_reg_6611[18] <= 1'b0;
tmp_230_reg_6611[19] <= 1'b0;
tmp_230_reg_6611[20] <= 1'b0;
tmp_230_reg_6611[21] <= 1'b0;
tmp_230_reg_6611[22] <= 1'b0;
tmp_230_reg_6611[23] <= 1'b0;
tmp_230_reg_6611[24] <= 1'b0;
tmp_230_reg_6611[25] <= 1'b0;
tmp_230_reg_6611[26] <= 1'b0;
tmp_230_reg_6611[27] <= 1'b0;
tmp_230_reg_6611[28] <= 1'b0;
tmp_230_reg_6611[29] <= 1'b0;
tmp_230_reg_6611[30] <= 1'b0;
tmp_230_reg_6611[31] <= 1'b0;
tmp_230_reg_6611[32] <= 1'b0;
tmp_230_reg_6611[33] <= 1'b0;
tmp_230_reg_6611[34] <= 1'b0;
tmp_230_reg_6611[35] <= 1'b0;
tmp_230_reg_6611[36] <= 1'b0;
tmp_230_reg_6611[37] <= 1'b0;
tmp_230_reg_6611[38] <= 1'b0;
tmp_230_reg_6611[39] <= 1'b0;
tmp_230_reg_6611[40] <= 1'b0;
tmp_230_reg_6611[41] <= 1'b0;
tmp_230_reg_6611[42] <= 1'b0;
tmp_230_reg_6611[43] <= 1'b0;
tmp_230_reg_6611[44] <= 1'b0;
tmp_230_reg_6611[45] <= 1'b0;
tmp_230_reg_6611[46] <= 1'b0;
tmp_230_reg_6611[47] <= 1'b0;
tmp_230_reg_6611[48] <= 1'b0;
tmp_230_reg_6611[49] <= 1'b0;
tmp_230_reg_6611[50] <= 1'b0;
tmp_230_reg_6611[51] <= 1'b0;
tmp_230_reg_6611[52] <= 1'b0;
tmp_230_reg_6611[53] <= 1'b0;
tmp_230_reg_6611[54] <= 1'b0;
tmp_230_reg_6611[55] <= 1'b0;
tmp_230_reg_6611[56] <= 1'b0;
tmp_230_reg_6611[57] <= 1'b0;
tmp_230_reg_6611[58] <= 1'b0;
tmp_230_reg_6611[59] <= 1'b0;
tmp_230_reg_6611[60] <= 1'b0;
tmp_230_reg_6611[61] <= 1'b0;
tmp_230_reg_6611[62] <= 1'b0;
tmp_230_reg_6611[63] <= 1'b0;
end
always @ (ap_clk)
begin
tmp_231_reg_6621[14] <= 1'b0;
tmp_231_reg_6621[15] <= 1'b0;
tmp_231_reg_6621[16] <= 1'b0;
tmp_231_reg_6621[17] <= 1'b0;
tmp_231_reg_6621[18] <= 1'b0;
tmp_231_reg_6621[19] <= 1'b0;
tmp_231_reg_6621[20] <= 1'b0;
tmp_231_reg_6621[21] <= 1'b0;
tmp_231_reg_6621[22] <= 1'b0;
tmp_231_reg_6621[23] <= 1'b0;
tmp_231_reg_6621[24] <= 1'b0;
tmp_231_reg_6621[25] <= 1'b0;
tmp_231_reg_6621[26] <= 1'b0;
tmp_231_reg_6621[27] <= 1'b0;
tmp_231_reg_6621[28] <= 1'b0;
tmp_231_reg_6621[29] <= 1'b0;
tmp_231_reg_6621[30] <= 1'b0;
tmp_231_reg_6621[31] <= 1'b0;
tmp_231_reg_6621[32] <= 1'b0;
tmp_231_reg_6621[33] <= 1'b0;
tmp_231_reg_6621[34] <= 1'b0;
tmp_231_reg_6621[35] <= 1'b0;
tmp_231_reg_6621[36] <= 1'b0;
tmp_231_reg_6621[37] <= 1'b0;
tmp_231_reg_6621[38] <= 1'b0;
tmp_231_reg_6621[39] <= 1'b0;
tmp_231_reg_6621[40] <= 1'b0;
tmp_231_reg_6621[41] <= 1'b0;
tmp_231_reg_6621[42] <= 1'b0;
tmp_231_reg_6621[43] <= 1'b0;
tmp_231_reg_6621[44] <= 1'b0;
tmp_231_reg_6621[45] <= 1'b0;
tmp_231_reg_6621[46] <= 1'b0;
tmp_231_reg_6621[47] <= 1'b0;
tmp_231_reg_6621[48] <= 1'b0;
tmp_231_reg_6621[49] <= 1'b0;
tmp_231_reg_6621[50] <= 1'b0;
tmp_231_reg_6621[51] <= 1'b0;
tmp_231_reg_6621[52] <= 1'b0;
tmp_231_reg_6621[53] <= 1'b0;
tmp_231_reg_6621[54] <= 1'b0;
tmp_231_reg_6621[55] <= 1'b0;
tmp_231_reg_6621[56] <= 1'b0;
tmp_231_reg_6621[57] <= 1'b0;
tmp_231_reg_6621[58] <= 1'b0;
tmp_231_reg_6621[59] <= 1'b0;
tmp_231_reg_6621[60] <= 1'b0;
tmp_231_reg_6621[61] <= 1'b0;
tmp_231_reg_6621[62] <= 1'b0;
tmp_231_reg_6621[63] <= 1'b0;
end
always @ (ap_clk)
begin
tmp_232_reg_6631[0] <= 1'b1;
tmp_232_reg_6631[14] <= 1'b0;
tmp_232_reg_6631[15] <= 1'b0;
tmp_232_reg_6631[16] <= 1'b0;
tmp_232_reg_6631[17] <= 1'b0;
tmp_232_reg_6631[18] <= 1'b0;
tmp_232_reg_6631[19] <= 1'b0;
tmp_232_reg_6631[20] <= 1'b0;
tmp_232_reg_6631[21] <= 1'b0;
tmp_232_reg_6631[22] <= 1'b0;
tmp_232_reg_6631[23] <= 1'b0;
tmp_232_reg_6631[24] <= 1'b0;
tmp_232_reg_6631[25] <= 1'b0;
tmp_232_reg_6631[26] <= 1'b0;
tmp_232_reg_6631[27] <= 1'b0;
tmp_232_reg_6631[28] <= 1'b0;
tmp_232_reg_6631[29] <= 1'b0;
tmp_232_reg_6631[30] <= 1'b0;
tmp_232_reg_6631[31] <= 1'b0;
tmp_232_reg_6631[32] <= 1'b0;
tmp_232_reg_6631[33] <= 1'b0;
tmp_232_reg_6631[34] <= 1'b0;
tmp_232_reg_6631[35] <= 1'b0;
tmp_232_reg_6631[36] <= 1'b0;
tmp_232_reg_6631[37] <= 1'b0;
tmp_232_reg_6631[38] <= 1'b0;
tmp_232_reg_6631[39] <= 1'b0;
tmp_232_reg_6631[40] <= 1'b0;
tmp_232_reg_6631[41] <= 1'b0;
tmp_232_reg_6631[42] <= 1'b0;
tmp_232_reg_6631[43] <= 1'b0;
tmp_232_reg_6631[44] <= 1'b0;
tmp_232_reg_6631[45] <= 1'b0;
tmp_232_reg_6631[46] <= 1'b0;
tmp_232_reg_6631[47] <= 1'b0;
tmp_232_reg_6631[48] <= 1'b0;
tmp_232_reg_6631[49] <= 1'b0;
tmp_232_reg_6631[50] <= 1'b0;
tmp_232_reg_6631[51] <= 1'b0;
tmp_232_reg_6631[52] <= 1'b0;
tmp_232_reg_6631[53] <= 1'b0;
tmp_232_reg_6631[54] <= 1'b0;
tmp_232_reg_6631[55] <= 1'b0;
tmp_232_reg_6631[56] <= 1'b0;
tmp_232_reg_6631[57] <= 1'b0;
tmp_232_reg_6631[58] <= 1'b0;
tmp_232_reg_6631[59] <= 1'b0;
tmp_232_reg_6631[60] <= 1'b0;
tmp_232_reg_6631[61] <= 1'b0;
tmp_232_reg_6631[62] <= 1'b0;
tmp_232_reg_6631[63] <= 1'b0;
end
always @ (ap_clk)
begin
tmp_233_reg_6641[14] <= 1'b0;
tmp_233_reg_6641[15] <= 1'b0;
tmp_233_reg_6641[16] <= 1'b0;
tmp_233_reg_6641[17] <= 1'b0;
tmp_233_reg_6641[18] <= 1'b0;
tmp_233_reg_6641[19] <= 1'b0;
tmp_233_reg_6641[20] <= 1'b0;
tmp_233_reg_6641[21] <= 1'b0;
tmp_233_reg_6641[22] <= 1'b0;
tmp_233_reg_6641[23] <= 1'b0;
tmp_233_reg_6641[24] <= 1'b0;
tmp_233_reg_6641[25] <= 1'b0;
tmp_233_reg_6641[26] <= 1'b0;
tmp_233_reg_6641[27] <= 1'b0;
tmp_233_reg_6641[28] <= 1'b0;
tmp_233_reg_6641[29] <= 1'b0;
tmp_233_reg_6641[30] <= 1'b0;
tmp_233_reg_6641[31] <= 1'b0;
tmp_233_reg_6641[32] <= 1'b0;
tmp_233_reg_6641[33] <= 1'b0;
tmp_233_reg_6641[34] <= 1'b0;
tmp_233_reg_6641[35] <= 1'b0;
tmp_233_reg_6641[36] <= 1'b0;
tmp_233_reg_6641[37] <= 1'b0;
tmp_233_reg_6641[38] <= 1'b0;
tmp_233_reg_6641[39] <= 1'b0;
tmp_233_reg_6641[40] <= 1'b0;
tmp_233_reg_6641[41] <= 1'b0;
tmp_233_reg_6641[42] <= 1'b0;
tmp_233_reg_6641[43] <= 1'b0;
tmp_233_reg_6641[44] <= 1'b0;
tmp_233_reg_6641[45] <= 1'b0;
tmp_233_reg_6641[46] <= 1'b0;
tmp_233_reg_6641[47] <= 1'b0;
tmp_233_reg_6641[48] <= 1'b0;
tmp_233_reg_6641[49] <= 1'b0;
tmp_233_reg_6641[50] <= 1'b0;
tmp_233_reg_6641[51] <= 1'b0;
tmp_233_reg_6641[52] <= 1'b0;
tmp_233_reg_6641[53] <= 1'b0;
tmp_233_reg_6641[54] <= 1'b0;
tmp_233_reg_6641[55] <= 1'b0;
tmp_233_reg_6641[56] <= 1'b0;
tmp_233_reg_6641[57] <= 1'b0;
tmp_233_reg_6641[58] <= 1'b0;
tmp_233_reg_6641[59] <= 1'b0;
tmp_233_reg_6641[60] <= 1'b0;
tmp_233_reg_6641[61] <= 1'b0;
tmp_233_reg_6641[62] <= 1'b0;
tmp_233_reg_6641[63] <= 1'b0;
end
always @ (ap_clk)
begin
tmp_234_reg_6651[0] <= 1'b1;
tmp_234_reg_6651[1] <= 1'b1;
tmp_234_reg_6651[2] <= 1'b1;
tmp_234_reg_6651[14] <= 1'b0;
tmp_234_reg_6651[15] <= 1'b0;
tmp_234_reg_6651[16] <= 1'b0;
tmp_234_reg_6651[17] <= 1'b0;
tmp_234_reg_6651[18] <= 1'b0;
tmp_234_reg_6651[19] <= 1'b0;
tmp_234_reg_6651[20] <= 1'b0;
tmp_234_reg_6651[21] <= 1'b0;
tmp_234_reg_6651[22] <= 1'b0;
tmp_234_reg_6651[23] <= 1'b0;
tmp_234_reg_6651[24] <= 1'b0;
tmp_234_reg_6651[25] <= 1'b0;
tmp_234_reg_6651[26] <= 1'b0;
tmp_234_reg_6651[27] <= 1'b0;
tmp_234_reg_6651[28] <= 1'b0;
tmp_234_reg_6651[29] <= 1'b0;
tmp_234_reg_6651[30] <= 1'b0;
tmp_234_reg_6651[31] <= 1'b0;
tmp_234_reg_6651[32] <= 1'b0;
tmp_234_reg_6651[33] <= 1'b0;
tmp_234_reg_6651[34] <= 1'b0;
tmp_234_reg_6651[35] <= 1'b0;
tmp_234_reg_6651[36] <= 1'b0;
tmp_234_reg_6651[37] <= 1'b0;
tmp_234_reg_6651[38] <= 1'b0;
tmp_234_reg_6651[39] <= 1'b0;
tmp_234_reg_6651[40] <= 1'b0;
tmp_234_reg_6651[41] <= 1'b0;
tmp_234_reg_6651[42] <= 1'b0;
tmp_234_reg_6651[43] <= 1'b0;
tmp_234_reg_6651[44] <= 1'b0;
tmp_234_reg_6651[45] <= 1'b0;
tmp_234_reg_6651[46] <= 1'b0;
tmp_234_reg_6651[47] <= 1'b0;
tmp_234_reg_6651[48] <= 1'b0;
tmp_234_reg_6651[49] <= 1'b0;
tmp_234_reg_6651[50] <= 1'b0;
tmp_234_reg_6651[51] <= 1'b0;
tmp_234_reg_6651[52] <= 1'b0;
tmp_234_reg_6651[53] <= 1'b0;
tmp_234_reg_6651[54] <= 1'b0;
tmp_234_reg_6651[55] <= 1'b0;
tmp_234_reg_6651[56] <= 1'b0;
tmp_234_reg_6651[57] <= 1'b0;
tmp_234_reg_6651[58] <= 1'b0;
tmp_234_reg_6651[59] <= 1'b0;
tmp_234_reg_6651[60] <= 1'b0;
tmp_234_reg_6651[61] <= 1'b0;
tmp_234_reg_6651[62] <= 1'b0;
tmp_234_reg_6651[63] <= 1'b0;
end
always @ (ap_clk)
begin
a_addr72_cast_reg_6661[0] <= 1'b0;
a_addr72_cast_reg_6661[1] <= 1'b0;
a_addr72_cast_reg_6661[2] <= 1'b0;
a_addr72_cast_reg_6661[3] <= 1'b0;
a_addr72_cast_reg_6661[4] <= 1'b0;
a_addr72_cast_reg_6661[5] <= 1'b0;
a_addr72_cast_reg_6661[6] <= 1'b1;
a_addr72_cast_reg_6661[8] <= 1'b1;
a_addr72_cast_reg_6661[13] <= 1'b0;
end
always @ (ap_clk)
begin
tmp_235_reg_6671[0] <= 1'b1;
tmp_235_reg_6671[14] <= 1'b0;
tmp_235_reg_6671[15] <= 1'b0;
tmp_235_reg_6671[16] <= 1'b0;
tmp_235_reg_6671[17] <= 1'b0;
tmp_235_reg_6671[18] <= 1'b0;
tmp_235_reg_6671[19] <= 1'b0;
tmp_235_reg_6671[20] <= 1'b0;
tmp_235_reg_6671[21] <= 1'b0;
tmp_235_reg_6671[22] <= 1'b0;
tmp_235_reg_6671[23] <= 1'b0;
tmp_235_reg_6671[24] <= 1'b0;
tmp_235_reg_6671[25] <= 1'b0;
tmp_235_reg_6671[26] <= 1'b0;
tmp_235_reg_6671[27] <= 1'b0;
tmp_235_reg_6671[28] <= 1'b0;
tmp_235_reg_6671[29] <= 1'b0;
tmp_235_reg_6671[30] <= 1'b0;
tmp_235_reg_6671[31] <= 1'b0;
tmp_235_reg_6671[32] <= 1'b0;
tmp_235_reg_6671[33] <= 1'b0;
tmp_235_reg_6671[34] <= 1'b0;
tmp_235_reg_6671[35] <= 1'b0;
tmp_235_reg_6671[36] <= 1'b0;
tmp_235_reg_6671[37] <= 1'b0;
tmp_235_reg_6671[38] <= 1'b0;
tmp_235_reg_6671[39] <= 1'b0;
tmp_235_reg_6671[40] <= 1'b0;
tmp_235_reg_6671[41] <= 1'b0;
tmp_235_reg_6671[42] <= 1'b0;
tmp_235_reg_6671[43] <= 1'b0;
tmp_235_reg_6671[44] <= 1'b0;
tmp_235_reg_6671[45] <= 1'b0;
tmp_235_reg_6671[46] <= 1'b0;
tmp_235_reg_6671[47] <= 1'b0;
tmp_235_reg_6671[48] <= 1'b0;
tmp_235_reg_6671[49] <= 1'b0;
tmp_235_reg_6671[50] <= 1'b0;
tmp_235_reg_6671[51] <= 1'b0;
tmp_235_reg_6671[52] <= 1'b0;
tmp_235_reg_6671[53] <= 1'b0;
tmp_235_reg_6671[54] <= 1'b0;
tmp_235_reg_6671[55] <= 1'b0;
tmp_235_reg_6671[56] <= 1'b0;
tmp_235_reg_6671[57] <= 1'b0;
tmp_235_reg_6671[58] <= 1'b0;
tmp_235_reg_6671[59] <= 1'b0;
tmp_235_reg_6671[60] <= 1'b0;
tmp_235_reg_6671[61] <= 1'b0;
tmp_235_reg_6671[62] <= 1'b0;
tmp_235_reg_6671[63] <= 1'b0;
end
always @ (ap_clk)
begin
tmp_236_reg_6681[14] <= 1'b0;
tmp_236_reg_6681[15] <= 1'b0;
tmp_236_reg_6681[16] <= 1'b0;
tmp_236_reg_6681[17] <= 1'b0;
tmp_236_reg_6681[18] <= 1'b0;
tmp_236_reg_6681[19] <= 1'b0;
tmp_236_reg_6681[20] <= 1'b0;
tmp_236_reg_6681[21] <= 1'b0;
tmp_236_reg_6681[22] <= 1'b0;
tmp_236_reg_6681[23] <= 1'b0;
tmp_236_reg_6681[24] <= 1'b0;
tmp_236_reg_6681[25] <= 1'b0;
tmp_236_reg_6681[26] <= 1'b0;
tmp_236_reg_6681[27] <= 1'b0;
tmp_236_reg_6681[28] <= 1'b0;
tmp_236_reg_6681[29] <= 1'b0;
tmp_236_reg_6681[30] <= 1'b0;
tmp_236_reg_6681[31] <= 1'b0;
tmp_236_reg_6681[32] <= 1'b0;
tmp_236_reg_6681[33] <= 1'b0;
tmp_236_reg_6681[34] <= 1'b0;
tmp_236_reg_6681[35] <= 1'b0;
tmp_236_reg_6681[36] <= 1'b0;
tmp_236_reg_6681[37] <= 1'b0;
tmp_236_reg_6681[38] <= 1'b0;
tmp_236_reg_6681[39] <= 1'b0;
tmp_236_reg_6681[40] <= 1'b0;
tmp_236_reg_6681[41] <= 1'b0;
tmp_236_reg_6681[42] <= 1'b0;
tmp_236_reg_6681[43] <= 1'b0;
tmp_236_reg_6681[44] <= 1'b0;
tmp_236_reg_6681[45] <= 1'b0;
tmp_236_reg_6681[46] <= 1'b0;
tmp_236_reg_6681[47] <= 1'b0;
tmp_236_reg_6681[48] <= 1'b0;
tmp_236_reg_6681[49] <= 1'b0;
tmp_236_reg_6681[50] <= 1'b0;
tmp_236_reg_6681[51] <= 1'b0;
tmp_236_reg_6681[52] <= 1'b0;
tmp_236_reg_6681[53] <= 1'b0;
tmp_236_reg_6681[54] <= 1'b0;
tmp_236_reg_6681[55] <= 1'b0;
tmp_236_reg_6681[56] <= 1'b0;
tmp_236_reg_6681[57] <= 1'b0;
tmp_236_reg_6681[58] <= 1'b0;
tmp_236_reg_6681[59] <= 1'b0;
tmp_236_reg_6681[60] <= 1'b0;
tmp_236_reg_6681[61] <= 1'b0;
tmp_236_reg_6681[62] <= 1'b0;
tmp_236_reg_6681[63] <= 1'b0;
end
always @ (ap_clk)
begin
tmp_237_reg_6691[0] <= 1'b1;
tmp_237_reg_6691[1] <= 1'b1;
tmp_237_reg_6691[14] <= 1'b0;
tmp_237_reg_6691[15] <= 1'b0;
tmp_237_reg_6691[16] <= 1'b0;
tmp_237_reg_6691[17] <= 1'b0;
tmp_237_reg_6691[18] <= 1'b0;
tmp_237_reg_6691[19] <= 1'b0;
tmp_237_reg_6691[20] <= 1'b0;
tmp_237_reg_6691[21] <= 1'b0;
tmp_237_reg_6691[22] <= 1'b0;
tmp_237_reg_6691[23] <= 1'b0;
tmp_237_reg_6691[24] <= 1'b0;
tmp_237_reg_6691[25] <= 1'b0;
tmp_237_reg_6691[26] <= 1'b0;
tmp_237_reg_6691[27] <= 1'b0;
tmp_237_reg_6691[28] <= 1'b0;
tmp_237_reg_6691[29] <= 1'b0;
tmp_237_reg_6691[30] <= 1'b0;
tmp_237_reg_6691[31] <= 1'b0;
tmp_237_reg_6691[32] <= 1'b0;
tmp_237_reg_6691[33] <= 1'b0;
tmp_237_reg_6691[34] <= 1'b0;
tmp_237_reg_6691[35] <= 1'b0;
tmp_237_reg_6691[36] <= 1'b0;
tmp_237_reg_6691[37] <= 1'b0;
tmp_237_reg_6691[38] <= 1'b0;
tmp_237_reg_6691[39] <= 1'b0;
tmp_237_reg_6691[40] <= 1'b0;
tmp_237_reg_6691[41] <= 1'b0;
tmp_237_reg_6691[42] <= 1'b0;
tmp_237_reg_6691[43] <= 1'b0;
tmp_237_reg_6691[44] <= 1'b0;
tmp_237_reg_6691[45] <= 1'b0;
tmp_237_reg_6691[46] <= 1'b0;
tmp_237_reg_6691[47] <= 1'b0;
tmp_237_reg_6691[48] <= 1'b0;
tmp_237_reg_6691[49] <= 1'b0;
tmp_237_reg_6691[50] <= 1'b0;
tmp_237_reg_6691[51] <= 1'b0;
tmp_237_reg_6691[52] <= 1'b0;
tmp_237_reg_6691[53] <= 1'b0;
tmp_237_reg_6691[54] <= 1'b0;
tmp_237_reg_6691[55] <= 1'b0;
tmp_237_reg_6691[56] <= 1'b0;
tmp_237_reg_6691[57] <= 1'b0;
tmp_237_reg_6691[58] <= 1'b0;
tmp_237_reg_6691[59] <= 1'b0;
tmp_237_reg_6691[60] <= 1'b0;
tmp_237_reg_6691[61] <= 1'b0;
tmp_237_reg_6691[62] <= 1'b0;
tmp_237_reg_6691[63] <= 1'b0;
end
always @ (ap_clk)
begin
tmp_238_reg_6701[14] <= 1'b0;
tmp_238_reg_6701[15] <= 1'b0;
tmp_238_reg_6701[16] <= 1'b0;
tmp_238_reg_6701[17] <= 1'b0;
tmp_238_reg_6701[18] <= 1'b0;
tmp_238_reg_6701[19] <= 1'b0;
tmp_238_reg_6701[20] <= 1'b0;
tmp_238_reg_6701[21] <= 1'b0;
tmp_238_reg_6701[22] <= 1'b0;
tmp_238_reg_6701[23] <= 1'b0;
tmp_238_reg_6701[24] <= 1'b0;
tmp_238_reg_6701[25] <= 1'b0;
tmp_238_reg_6701[26] <= 1'b0;
tmp_238_reg_6701[27] <= 1'b0;
tmp_238_reg_6701[28] <= 1'b0;
tmp_238_reg_6701[29] <= 1'b0;
tmp_238_reg_6701[30] <= 1'b0;
tmp_238_reg_6701[31] <= 1'b0;
tmp_238_reg_6701[32] <= 1'b0;
tmp_238_reg_6701[33] <= 1'b0;
tmp_238_reg_6701[34] <= 1'b0;
tmp_238_reg_6701[35] <= 1'b0;
tmp_238_reg_6701[36] <= 1'b0;
tmp_238_reg_6701[37] <= 1'b0;
tmp_238_reg_6701[38] <= 1'b0;
tmp_238_reg_6701[39] <= 1'b0;
tmp_238_reg_6701[40] <= 1'b0;
tmp_238_reg_6701[41] <= 1'b0;
tmp_238_reg_6701[42] <= 1'b0;
tmp_238_reg_6701[43] <= 1'b0;
tmp_238_reg_6701[44] <= 1'b0;
tmp_238_reg_6701[45] <= 1'b0;
tmp_238_reg_6701[46] <= 1'b0;
tmp_238_reg_6701[47] <= 1'b0;
tmp_238_reg_6701[48] <= 1'b0;
tmp_238_reg_6701[49] <= 1'b0;
tmp_238_reg_6701[50] <= 1'b0;
tmp_238_reg_6701[51] <= 1'b0;
tmp_238_reg_6701[52] <= 1'b0;
tmp_238_reg_6701[53] <= 1'b0;
tmp_238_reg_6701[54] <= 1'b0;
tmp_238_reg_6701[55] <= 1'b0;
tmp_238_reg_6701[56] <= 1'b0;
tmp_238_reg_6701[57] <= 1'b0;
tmp_238_reg_6701[58] <= 1'b0;
tmp_238_reg_6701[59] <= 1'b0;
tmp_238_reg_6701[60] <= 1'b0;
tmp_238_reg_6701[61] <= 1'b0;
tmp_238_reg_6701[62] <= 1'b0;
tmp_238_reg_6701[63] <= 1'b0;
end
always @ (ap_clk)
begin
tmp_239_reg_6711[0] <= 1'b1;
tmp_239_reg_6711[14] <= 1'b0;
tmp_239_reg_6711[15] <= 1'b0;
tmp_239_reg_6711[16] <= 1'b0;
tmp_239_reg_6711[17] <= 1'b0;
tmp_239_reg_6711[18] <= 1'b0;
tmp_239_reg_6711[19] <= 1'b0;
tmp_239_reg_6711[20] <= 1'b0;
tmp_239_reg_6711[21] <= 1'b0;
tmp_239_reg_6711[22] <= 1'b0;
tmp_239_reg_6711[23] <= 1'b0;
tmp_239_reg_6711[24] <= 1'b0;
tmp_239_reg_6711[25] <= 1'b0;
tmp_239_reg_6711[26] <= 1'b0;
tmp_239_reg_6711[27] <= 1'b0;
tmp_239_reg_6711[28] <= 1'b0;
tmp_239_reg_6711[29] <= 1'b0;
tmp_239_reg_6711[30] <= 1'b0;
tmp_239_reg_6711[31] <= 1'b0;
tmp_239_reg_6711[32] <= 1'b0;
tmp_239_reg_6711[33] <= 1'b0;
tmp_239_reg_6711[34] <= 1'b0;
tmp_239_reg_6711[35] <= 1'b0;
tmp_239_reg_6711[36] <= 1'b0;
tmp_239_reg_6711[37] <= 1'b0;
tmp_239_reg_6711[38] <= 1'b0;
tmp_239_reg_6711[39] <= 1'b0;
tmp_239_reg_6711[40] <= 1'b0;
tmp_239_reg_6711[41] <= 1'b0;
tmp_239_reg_6711[42] <= 1'b0;
tmp_239_reg_6711[43] <= 1'b0;
tmp_239_reg_6711[44] <= 1'b0;
tmp_239_reg_6711[45] <= 1'b0;
tmp_239_reg_6711[46] <= 1'b0;
tmp_239_reg_6711[47] <= 1'b0;
tmp_239_reg_6711[48] <= 1'b0;
tmp_239_reg_6711[49] <= 1'b0;
tmp_239_reg_6711[50] <= 1'b0;
tmp_239_reg_6711[51] <= 1'b0;
tmp_239_reg_6711[52] <= 1'b0;
tmp_239_reg_6711[53] <= 1'b0;
tmp_239_reg_6711[54] <= 1'b0;
tmp_239_reg_6711[55] <= 1'b0;
tmp_239_reg_6711[56] <= 1'b0;
tmp_239_reg_6711[57] <= 1'b0;
tmp_239_reg_6711[58] <= 1'b0;
tmp_239_reg_6711[59] <= 1'b0;
tmp_239_reg_6711[60] <= 1'b0;
tmp_239_reg_6711[61] <= 1'b0;
tmp_239_reg_6711[62] <= 1'b0;
tmp_239_reg_6711[63] <= 1'b0;
end
always @ (ap_clk)
begin
tmp_240_reg_6721[14] <= 1'b0;
tmp_240_reg_6721[15] <= 1'b0;
tmp_240_reg_6721[16] <= 1'b0;
tmp_240_reg_6721[17] <= 1'b0;
tmp_240_reg_6721[18] <= 1'b0;
tmp_240_reg_6721[19] <= 1'b0;
tmp_240_reg_6721[20] <= 1'b0;
tmp_240_reg_6721[21] <= 1'b0;
tmp_240_reg_6721[22] <= 1'b0;
tmp_240_reg_6721[23] <= 1'b0;
tmp_240_reg_6721[24] <= 1'b0;
tmp_240_reg_6721[25] <= 1'b0;
tmp_240_reg_6721[26] <= 1'b0;
tmp_240_reg_6721[27] <= 1'b0;
tmp_240_reg_6721[28] <= 1'b0;
tmp_240_reg_6721[29] <= 1'b0;
tmp_240_reg_6721[30] <= 1'b0;
tmp_240_reg_6721[31] <= 1'b0;
tmp_240_reg_6721[32] <= 1'b0;
tmp_240_reg_6721[33] <= 1'b0;
tmp_240_reg_6721[34] <= 1'b0;
tmp_240_reg_6721[35] <= 1'b0;
tmp_240_reg_6721[36] <= 1'b0;
tmp_240_reg_6721[37] <= 1'b0;
tmp_240_reg_6721[38] <= 1'b0;
tmp_240_reg_6721[39] <= 1'b0;
tmp_240_reg_6721[40] <= 1'b0;
tmp_240_reg_6721[41] <= 1'b0;
tmp_240_reg_6721[42] <= 1'b0;
tmp_240_reg_6721[43] <= 1'b0;
tmp_240_reg_6721[44] <= 1'b0;
tmp_240_reg_6721[45] <= 1'b0;
tmp_240_reg_6721[46] <= 1'b0;
tmp_240_reg_6721[47] <= 1'b0;
tmp_240_reg_6721[48] <= 1'b0;
tmp_240_reg_6721[49] <= 1'b0;
tmp_240_reg_6721[50] <= 1'b0;
tmp_240_reg_6721[51] <= 1'b0;
tmp_240_reg_6721[52] <= 1'b0;
tmp_240_reg_6721[53] <= 1'b0;
tmp_240_reg_6721[54] <= 1'b0;
tmp_240_reg_6721[55] <= 1'b0;
tmp_240_reg_6721[56] <= 1'b0;
tmp_240_reg_6721[57] <= 1'b0;
tmp_240_reg_6721[58] <= 1'b0;
tmp_240_reg_6721[59] <= 1'b0;
tmp_240_reg_6721[60] <= 1'b0;
tmp_240_reg_6721[61] <= 1'b0;
tmp_240_reg_6721[62] <= 1'b0;
tmp_240_reg_6721[63] <= 1'b0;
end
always @ (ap_clk)
begin
tmp_241_reg_6731[0] <= 1'b1;
tmp_241_reg_6731[1] <= 1'b1;
tmp_241_reg_6731[2] <= 1'b1;
tmp_241_reg_6731[14] <= 1'b0;
tmp_241_reg_6731[15] <= 1'b0;
tmp_241_reg_6731[16] <= 1'b0;
tmp_241_reg_6731[17] <= 1'b0;
tmp_241_reg_6731[18] <= 1'b0;
tmp_241_reg_6731[19] <= 1'b0;
tmp_241_reg_6731[20] <= 1'b0;
tmp_241_reg_6731[21] <= 1'b0;
tmp_241_reg_6731[22] <= 1'b0;
tmp_241_reg_6731[23] <= 1'b0;
tmp_241_reg_6731[24] <= 1'b0;
tmp_241_reg_6731[25] <= 1'b0;
tmp_241_reg_6731[26] <= 1'b0;
tmp_241_reg_6731[27] <= 1'b0;
tmp_241_reg_6731[28] <= 1'b0;
tmp_241_reg_6731[29] <= 1'b0;
tmp_241_reg_6731[30] <= 1'b0;
tmp_241_reg_6731[31] <= 1'b0;
tmp_241_reg_6731[32] <= 1'b0;
tmp_241_reg_6731[33] <= 1'b0;
tmp_241_reg_6731[34] <= 1'b0;
tmp_241_reg_6731[35] <= 1'b0;
tmp_241_reg_6731[36] <= 1'b0;
tmp_241_reg_6731[37] <= 1'b0;
tmp_241_reg_6731[38] <= 1'b0;
tmp_241_reg_6731[39] <= 1'b0;
tmp_241_reg_6731[40] <= 1'b0;
tmp_241_reg_6731[41] <= 1'b0;
tmp_241_reg_6731[42] <= 1'b0;
tmp_241_reg_6731[43] <= 1'b0;
tmp_241_reg_6731[44] <= 1'b0;
tmp_241_reg_6731[45] <= 1'b0;
tmp_241_reg_6731[46] <= 1'b0;
tmp_241_reg_6731[47] <= 1'b0;
tmp_241_reg_6731[48] <= 1'b0;
tmp_241_reg_6731[49] <= 1'b0;
tmp_241_reg_6731[50] <= 1'b0;
tmp_241_reg_6731[51] <= 1'b0;
tmp_241_reg_6731[52] <= 1'b0;
tmp_241_reg_6731[53] <= 1'b0;
tmp_241_reg_6731[54] <= 1'b0;
tmp_241_reg_6731[55] <= 1'b0;
tmp_241_reg_6731[56] <= 1'b0;
tmp_241_reg_6731[57] <= 1'b0;
tmp_241_reg_6731[58] <= 1'b0;
tmp_241_reg_6731[59] <= 1'b0;
tmp_241_reg_6731[60] <= 1'b0;
tmp_241_reg_6731[61] <= 1'b0;
tmp_241_reg_6731[62] <= 1'b0;
tmp_241_reg_6731[63] <= 1'b0;
end
always @ (ap_clk)
begin
a_addr45_cast_reg_6741[0] <= 1'b0;
a_addr45_cast_reg_6741[1] <= 1'b0;
a_addr45_cast_reg_6741[2] <= 1'b0;
a_addr45_cast_reg_6741[3] <= 1'b0;
a_addr45_cast_reg_6741[4] <= 1'b0;
a_addr45_cast_reg_6741[5] <= 1'b0;
a_addr45_cast_reg_6741[7] <= 1'b1;
a_addr45_cast_reg_6741[8] <= 1'b1;
a_addr45_cast_reg_6741[13] <= 1'b0;
end
always @ (ap_clk)
begin
tmp_242_reg_6750[0] <= 1'b1;
tmp_242_reg_6750[14] <= 1'b0;
tmp_242_reg_6750[15] <= 1'b0;
tmp_242_reg_6750[16] <= 1'b0;
tmp_242_reg_6750[17] <= 1'b0;
tmp_242_reg_6750[18] <= 1'b0;
tmp_242_reg_6750[19] <= 1'b0;
tmp_242_reg_6750[20] <= 1'b0;
tmp_242_reg_6750[21] <= 1'b0;
tmp_242_reg_6750[22] <= 1'b0;
tmp_242_reg_6750[23] <= 1'b0;
tmp_242_reg_6750[24] <= 1'b0;
tmp_242_reg_6750[25] <= 1'b0;
tmp_242_reg_6750[26] <= 1'b0;
tmp_242_reg_6750[27] <= 1'b0;
tmp_242_reg_6750[28] <= 1'b0;
tmp_242_reg_6750[29] <= 1'b0;
tmp_242_reg_6750[30] <= 1'b0;
tmp_242_reg_6750[31] <= 1'b0;
tmp_242_reg_6750[32] <= 1'b0;
tmp_242_reg_6750[33] <= 1'b0;
tmp_242_reg_6750[34] <= 1'b0;
tmp_242_reg_6750[35] <= 1'b0;
tmp_242_reg_6750[36] <= 1'b0;
tmp_242_reg_6750[37] <= 1'b0;
tmp_242_reg_6750[38] <= 1'b0;
tmp_242_reg_6750[39] <= 1'b0;
tmp_242_reg_6750[40] <= 1'b0;
tmp_242_reg_6750[41] <= 1'b0;
tmp_242_reg_6750[42] <= 1'b0;
tmp_242_reg_6750[43] <= 1'b0;
tmp_242_reg_6750[44] <= 1'b0;
tmp_242_reg_6750[45] <= 1'b0;
tmp_242_reg_6750[46] <= 1'b0;
tmp_242_reg_6750[47] <= 1'b0;
tmp_242_reg_6750[48] <= 1'b0;
tmp_242_reg_6750[49] <= 1'b0;
tmp_242_reg_6750[50] <= 1'b0;
tmp_242_reg_6750[51] <= 1'b0;
tmp_242_reg_6750[52] <= 1'b0;
tmp_242_reg_6750[53] <= 1'b0;
tmp_242_reg_6750[54] <= 1'b0;
tmp_242_reg_6750[55] <= 1'b0;
tmp_242_reg_6750[56] <= 1'b0;
tmp_242_reg_6750[57] <= 1'b0;
tmp_242_reg_6750[58] <= 1'b0;
tmp_242_reg_6750[59] <= 1'b0;
tmp_242_reg_6750[60] <= 1'b0;
tmp_242_reg_6750[61] <= 1'b0;
tmp_242_reg_6750[62] <= 1'b0;
tmp_242_reg_6750[63] <= 1'b0;
end
always @ (ap_clk)
begin
tmp_243_reg_6760[14] <= 1'b0;
tmp_243_reg_6760[15] <= 1'b0;
tmp_243_reg_6760[16] <= 1'b0;
tmp_243_reg_6760[17] <= 1'b0;
tmp_243_reg_6760[18] <= 1'b0;
tmp_243_reg_6760[19] <= 1'b0;
tmp_243_reg_6760[20] <= 1'b0;
tmp_243_reg_6760[21] <= 1'b0;
tmp_243_reg_6760[22] <= 1'b0;
tmp_243_reg_6760[23] <= 1'b0;
tmp_243_reg_6760[24] <= 1'b0;
tmp_243_reg_6760[25] <= 1'b0;
tmp_243_reg_6760[26] <= 1'b0;
tmp_243_reg_6760[27] <= 1'b0;
tmp_243_reg_6760[28] <= 1'b0;
tmp_243_reg_6760[29] <= 1'b0;
tmp_243_reg_6760[30] <= 1'b0;
tmp_243_reg_6760[31] <= 1'b0;
tmp_243_reg_6760[32] <= 1'b0;
tmp_243_reg_6760[33] <= 1'b0;
tmp_243_reg_6760[34] <= 1'b0;
tmp_243_reg_6760[35] <= 1'b0;
tmp_243_reg_6760[36] <= 1'b0;
tmp_243_reg_6760[37] <= 1'b0;
tmp_243_reg_6760[38] <= 1'b0;
tmp_243_reg_6760[39] <= 1'b0;
tmp_243_reg_6760[40] <= 1'b0;
tmp_243_reg_6760[41] <= 1'b0;
tmp_243_reg_6760[42] <= 1'b0;
tmp_243_reg_6760[43] <= 1'b0;
tmp_243_reg_6760[44] <= 1'b0;
tmp_243_reg_6760[45] <= 1'b0;
tmp_243_reg_6760[46] <= 1'b0;
tmp_243_reg_6760[47] <= 1'b0;
tmp_243_reg_6760[48] <= 1'b0;
tmp_243_reg_6760[49] <= 1'b0;
tmp_243_reg_6760[50] <= 1'b0;
tmp_243_reg_6760[51] <= 1'b0;
tmp_243_reg_6760[52] <= 1'b0;
tmp_243_reg_6760[53] <= 1'b0;
tmp_243_reg_6760[54] <= 1'b0;
tmp_243_reg_6760[55] <= 1'b0;
tmp_243_reg_6760[56] <= 1'b0;
tmp_243_reg_6760[57] <= 1'b0;
tmp_243_reg_6760[58] <= 1'b0;
tmp_243_reg_6760[59] <= 1'b0;
tmp_243_reg_6760[60] <= 1'b0;
tmp_243_reg_6760[61] <= 1'b0;
tmp_243_reg_6760[62] <= 1'b0;
tmp_243_reg_6760[63] <= 1'b0;
end
always @ (ap_clk)
begin
tmp_244_reg_6770[0] <= 1'b1;
tmp_244_reg_6770[1] <= 1'b1;
tmp_244_reg_6770[14] <= 1'b0;
tmp_244_reg_6770[15] <= 1'b0;
tmp_244_reg_6770[16] <= 1'b0;
tmp_244_reg_6770[17] <= 1'b0;
tmp_244_reg_6770[18] <= 1'b0;
tmp_244_reg_6770[19] <= 1'b0;
tmp_244_reg_6770[20] <= 1'b0;
tmp_244_reg_6770[21] <= 1'b0;
tmp_244_reg_6770[22] <= 1'b0;
tmp_244_reg_6770[23] <= 1'b0;
tmp_244_reg_6770[24] <= 1'b0;
tmp_244_reg_6770[25] <= 1'b0;
tmp_244_reg_6770[26] <= 1'b0;
tmp_244_reg_6770[27] <= 1'b0;
tmp_244_reg_6770[28] <= 1'b0;
tmp_244_reg_6770[29] <= 1'b0;
tmp_244_reg_6770[30] <= 1'b0;
tmp_244_reg_6770[31] <= 1'b0;
tmp_244_reg_6770[32] <= 1'b0;
tmp_244_reg_6770[33] <= 1'b0;
tmp_244_reg_6770[34] <= 1'b0;
tmp_244_reg_6770[35] <= 1'b0;
tmp_244_reg_6770[36] <= 1'b0;
tmp_244_reg_6770[37] <= 1'b0;
tmp_244_reg_6770[38] <= 1'b0;
tmp_244_reg_6770[39] <= 1'b0;
tmp_244_reg_6770[40] <= 1'b0;
tmp_244_reg_6770[41] <= 1'b0;
tmp_244_reg_6770[42] <= 1'b0;
tmp_244_reg_6770[43] <= 1'b0;
tmp_244_reg_6770[44] <= 1'b0;
tmp_244_reg_6770[45] <= 1'b0;
tmp_244_reg_6770[46] <= 1'b0;
tmp_244_reg_6770[47] <= 1'b0;
tmp_244_reg_6770[48] <= 1'b0;
tmp_244_reg_6770[49] <= 1'b0;
tmp_244_reg_6770[50] <= 1'b0;
tmp_244_reg_6770[51] <= 1'b0;
tmp_244_reg_6770[52] <= 1'b0;
tmp_244_reg_6770[53] <= 1'b0;
tmp_244_reg_6770[54] <= 1'b0;
tmp_244_reg_6770[55] <= 1'b0;
tmp_244_reg_6770[56] <= 1'b0;
tmp_244_reg_6770[57] <= 1'b0;
tmp_244_reg_6770[58] <= 1'b0;
tmp_244_reg_6770[59] <= 1'b0;
tmp_244_reg_6770[60] <= 1'b0;
tmp_244_reg_6770[61] <= 1'b0;
tmp_244_reg_6770[62] <= 1'b0;
tmp_244_reg_6770[63] <= 1'b0;
end
always @ (ap_clk)
begin
tmp_245_reg_6780[14] <= 1'b0;
tmp_245_reg_6780[15] <= 1'b0;
tmp_245_reg_6780[16] <= 1'b0;
tmp_245_reg_6780[17] <= 1'b0;
tmp_245_reg_6780[18] <= 1'b0;
tmp_245_reg_6780[19] <= 1'b0;
tmp_245_reg_6780[20] <= 1'b0;
tmp_245_reg_6780[21] <= 1'b0;
tmp_245_reg_6780[22] <= 1'b0;
tmp_245_reg_6780[23] <= 1'b0;
tmp_245_reg_6780[24] <= 1'b0;
tmp_245_reg_6780[25] <= 1'b0;
tmp_245_reg_6780[26] <= 1'b0;
tmp_245_reg_6780[27] <= 1'b0;
tmp_245_reg_6780[28] <= 1'b0;
tmp_245_reg_6780[29] <= 1'b0;
tmp_245_reg_6780[30] <= 1'b0;
tmp_245_reg_6780[31] <= 1'b0;
tmp_245_reg_6780[32] <= 1'b0;
tmp_245_reg_6780[33] <= 1'b0;
tmp_245_reg_6780[34] <= 1'b0;
tmp_245_reg_6780[35] <= 1'b0;
tmp_245_reg_6780[36] <= 1'b0;
tmp_245_reg_6780[37] <= 1'b0;
tmp_245_reg_6780[38] <= 1'b0;
tmp_245_reg_6780[39] <= 1'b0;
tmp_245_reg_6780[40] <= 1'b0;
tmp_245_reg_6780[41] <= 1'b0;
tmp_245_reg_6780[42] <= 1'b0;
tmp_245_reg_6780[43] <= 1'b0;
tmp_245_reg_6780[44] <= 1'b0;
tmp_245_reg_6780[45] <= 1'b0;
tmp_245_reg_6780[46] <= 1'b0;
tmp_245_reg_6780[47] <= 1'b0;
tmp_245_reg_6780[48] <= 1'b0;
tmp_245_reg_6780[49] <= 1'b0;
tmp_245_reg_6780[50] <= 1'b0;
tmp_245_reg_6780[51] <= 1'b0;
tmp_245_reg_6780[52] <= 1'b0;
tmp_245_reg_6780[53] <= 1'b0;
tmp_245_reg_6780[54] <= 1'b0;
tmp_245_reg_6780[55] <= 1'b0;
tmp_245_reg_6780[56] <= 1'b0;
tmp_245_reg_6780[57] <= 1'b0;
tmp_245_reg_6780[58] <= 1'b0;
tmp_245_reg_6780[59] <= 1'b0;
tmp_245_reg_6780[60] <= 1'b0;
tmp_245_reg_6780[61] <= 1'b0;
tmp_245_reg_6780[62] <= 1'b0;
tmp_245_reg_6780[63] <= 1'b0;
end
always @ (ap_clk)
begin
tmp_246_reg_6790[0] <= 1'b1;
tmp_246_reg_6790[14] <= 1'b0;
tmp_246_reg_6790[15] <= 1'b0;
tmp_246_reg_6790[16] <= 1'b0;
tmp_246_reg_6790[17] <= 1'b0;
tmp_246_reg_6790[18] <= 1'b0;
tmp_246_reg_6790[19] <= 1'b0;
tmp_246_reg_6790[20] <= 1'b0;
tmp_246_reg_6790[21] <= 1'b0;
tmp_246_reg_6790[22] <= 1'b0;
tmp_246_reg_6790[23] <= 1'b0;
tmp_246_reg_6790[24] <= 1'b0;
tmp_246_reg_6790[25] <= 1'b0;
tmp_246_reg_6790[26] <= 1'b0;
tmp_246_reg_6790[27] <= 1'b0;
tmp_246_reg_6790[28] <= 1'b0;
tmp_246_reg_6790[29] <= 1'b0;
tmp_246_reg_6790[30] <= 1'b0;
tmp_246_reg_6790[31] <= 1'b0;
tmp_246_reg_6790[32] <= 1'b0;
tmp_246_reg_6790[33] <= 1'b0;
tmp_246_reg_6790[34] <= 1'b0;
tmp_246_reg_6790[35] <= 1'b0;
tmp_246_reg_6790[36] <= 1'b0;
tmp_246_reg_6790[37] <= 1'b0;
tmp_246_reg_6790[38] <= 1'b0;
tmp_246_reg_6790[39] <= 1'b0;
tmp_246_reg_6790[40] <= 1'b0;
tmp_246_reg_6790[41] <= 1'b0;
tmp_246_reg_6790[42] <= 1'b0;
tmp_246_reg_6790[43] <= 1'b0;
tmp_246_reg_6790[44] <= 1'b0;
tmp_246_reg_6790[45] <= 1'b0;
tmp_246_reg_6790[46] <= 1'b0;
tmp_246_reg_6790[47] <= 1'b0;
tmp_246_reg_6790[48] <= 1'b0;
tmp_246_reg_6790[49] <= 1'b0;
tmp_246_reg_6790[50] <= 1'b0;
tmp_246_reg_6790[51] <= 1'b0;
tmp_246_reg_6790[52] <= 1'b0;
tmp_246_reg_6790[53] <= 1'b0;
tmp_246_reg_6790[54] <= 1'b0;
tmp_246_reg_6790[55] <= 1'b0;
tmp_246_reg_6790[56] <= 1'b0;
tmp_246_reg_6790[57] <= 1'b0;
tmp_246_reg_6790[58] <= 1'b0;
tmp_246_reg_6790[59] <= 1'b0;
tmp_246_reg_6790[60] <= 1'b0;
tmp_246_reg_6790[61] <= 1'b0;
tmp_246_reg_6790[62] <= 1'b0;
tmp_246_reg_6790[63] <= 1'b0;
end
always @ (ap_clk)
begin
tmp_247_reg_6800[14] <= 1'b0;
tmp_247_reg_6800[15] <= 1'b0;
tmp_247_reg_6800[16] <= 1'b0;
tmp_247_reg_6800[17] <= 1'b0;
tmp_247_reg_6800[18] <= 1'b0;
tmp_247_reg_6800[19] <= 1'b0;
tmp_247_reg_6800[20] <= 1'b0;
tmp_247_reg_6800[21] <= 1'b0;
tmp_247_reg_6800[22] <= 1'b0;
tmp_247_reg_6800[23] <= 1'b0;
tmp_247_reg_6800[24] <= 1'b0;
tmp_247_reg_6800[25] <= 1'b0;
tmp_247_reg_6800[26] <= 1'b0;
tmp_247_reg_6800[27] <= 1'b0;
tmp_247_reg_6800[28] <= 1'b0;
tmp_247_reg_6800[29] <= 1'b0;
tmp_247_reg_6800[30] <= 1'b0;
tmp_247_reg_6800[31] <= 1'b0;
tmp_247_reg_6800[32] <= 1'b0;
tmp_247_reg_6800[33] <= 1'b0;
tmp_247_reg_6800[34] <= 1'b0;
tmp_247_reg_6800[35] <= 1'b0;
tmp_247_reg_6800[36] <= 1'b0;
tmp_247_reg_6800[37] <= 1'b0;
tmp_247_reg_6800[38] <= 1'b0;
tmp_247_reg_6800[39] <= 1'b0;
tmp_247_reg_6800[40] <= 1'b0;
tmp_247_reg_6800[41] <= 1'b0;
tmp_247_reg_6800[42] <= 1'b0;
tmp_247_reg_6800[43] <= 1'b0;
tmp_247_reg_6800[44] <= 1'b0;
tmp_247_reg_6800[45] <= 1'b0;
tmp_247_reg_6800[46] <= 1'b0;
tmp_247_reg_6800[47] <= 1'b0;
tmp_247_reg_6800[48] <= 1'b0;
tmp_247_reg_6800[49] <= 1'b0;
tmp_247_reg_6800[50] <= 1'b0;
tmp_247_reg_6800[51] <= 1'b0;
tmp_247_reg_6800[52] <= 1'b0;
tmp_247_reg_6800[53] <= 1'b0;
tmp_247_reg_6800[54] <= 1'b0;
tmp_247_reg_6800[55] <= 1'b0;
tmp_247_reg_6800[56] <= 1'b0;
tmp_247_reg_6800[57] <= 1'b0;
tmp_247_reg_6800[58] <= 1'b0;
tmp_247_reg_6800[59] <= 1'b0;
tmp_247_reg_6800[60] <= 1'b0;
tmp_247_reg_6800[61] <= 1'b0;
tmp_247_reg_6800[62] <= 1'b0;
tmp_247_reg_6800[63] <= 1'b0;
end
always @ (ap_clk)
begin
a_addr22_reg_6810[0] <= 1'b1;
a_addr22_reg_6810[1] <= 1'b1;
a_addr22_reg_6810[2] <= 1'b1;
end
always @ (ap_clk)
begin
a_addr19_reg_6815[0] <= 1'b1;
end
always @ (ap_clk)
begin
a_addr13_reg_6825[0] <= 1'b1;
a_addr13_reg_6825[1] <= 1'b1;
end
always @ (ap_clk)
begin
a_addr7_reg_6835[0] <= 1'b1;
end
always @ (ap_clk)
begin
a_addr1_reg_6845[0] <= 1'b1;
a_addr1_reg_6845[1] <= 1'b1;
a_addr1_reg_6845[2] <= 1'b1;
end
always @ (ap_clk)
begin
tmp_248_reg_6850[0] <= 1'b1;
tmp_248_reg_6850[1] <= 1'b1;
tmp_248_reg_6850[2] <= 1'b1;
tmp_248_reg_6850[14] <= 1'b0;
tmp_248_reg_6850[15] <= 1'b0;
tmp_248_reg_6850[16] <= 1'b0;
tmp_248_reg_6850[17] <= 1'b0;
tmp_248_reg_6850[18] <= 1'b0;
tmp_248_reg_6850[19] <= 1'b0;
tmp_248_reg_6850[20] <= 1'b0;
tmp_248_reg_6850[21] <= 1'b0;
tmp_248_reg_6850[22] <= 1'b0;
tmp_248_reg_6850[23] <= 1'b0;
tmp_248_reg_6850[24] <= 1'b0;
tmp_248_reg_6850[25] <= 1'b0;
tmp_248_reg_6850[26] <= 1'b0;
tmp_248_reg_6850[27] <= 1'b0;
tmp_248_reg_6850[28] <= 1'b0;
tmp_248_reg_6850[29] <= 1'b0;
tmp_248_reg_6850[30] <= 1'b0;
tmp_248_reg_6850[31] <= 1'b0;
tmp_248_reg_6850[32] <= 1'b0;
tmp_248_reg_6850[33] <= 1'b0;
tmp_248_reg_6850[34] <= 1'b0;
tmp_248_reg_6850[35] <= 1'b0;
tmp_248_reg_6850[36] <= 1'b0;
tmp_248_reg_6850[37] <= 1'b0;
tmp_248_reg_6850[38] <= 1'b0;
tmp_248_reg_6850[39] <= 1'b0;
tmp_248_reg_6850[40] <= 1'b0;
tmp_248_reg_6850[41] <= 1'b0;
tmp_248_reg_6850[42] <= 1'b0;
tmp_248_reg_6850[43] <= 1'b0;
tmp_248_reg_6850[44] <= 1'b0;
tmp_248_reg_6850[45] <= 1'b0;
tmp_248_reg_6850[46] <= 1'b0;
tmp_248_reg_6850[47] <= 1'b0;
tmp_248_reg_6850[48] <= 1'b0;
tmp_248_reg_6850[49] <= 1'b0;
tmp_248_reg_6850[50] <= 1'b0;
tmp_248_reg_6850[51] <= 1'b0;
tmp_248_reg_6850[52] <= 1'b0;
tmp_248_reg_6850[53] <= 1'b0;
tmp_248_reg_6850[54] <= 1'b0;
tmp_248_reg_6850[55] <= 1'b0;
tmp_248_reg_6850[56] <= 1'b0;
tmp_248_reg_6850[57] <= 1'b0;
tmp_248_reg_6850[58] <= 1'b0;
tmp_248_reg_6850[59] <= 1'b0;
tmp_248_reg_6850[60] <= 1'b0;
tmp_248_reg_6850[61] <= 1'b0;
tmp_248_reg_6850[62] <= 1'b0;
tmp_248_reg_6850[63] <= 1'b0;
end
always @ (ap_clk)
begin
tmp_249_reg_6860[0] <= 1'b1;
tmp_249_reg_6860[14] <= 1'b0;
tmp_249_reg_6860[15] <= 1'b0;
tmp_249_reg_6860[16] <= 1'b0;
tmp_249_reg_6860[17] <= 1'b0;
tmp_249_reg_6860[18] <= 1'b0;
tmp_249_reg_6860[19] <= 1'b0;
tmp_249_reg_6860[20] <= 1'b0;
tmp_249_reg_6860[21] <= 1'b0;
tmp_249_reg_6860[22] <= 1'b0;
tmp_249_reg_6860[23] <= 1'b0;
tmp_249_reg_6860[24] <= 1'b0;
tmp_249_reg_6860[25] <= 1'b0;
tmp_249_reg_6860[26] <= 1'b0;
tmp_249_reg_6860[27] <= 1'b0;
tmp_249_reg_6860[28] <= 1'b0;
tmp_249_reg_6860[29] <= 1'b0;
tmp_249_reg_6860[30] <= 1'b0;
tmp_249_reg_6860[31] <= 1'b0;
tmp_249_reg_6860[32] <= 1'b0;
tmp_249_reg_6860[33] <= 1'b0;
tmp_249_reg_6860[34] <= 1'b0;
tmp_249_reg_6860[35] <= 1'b0;
tmp_249_reg_6860[36] <= 1'b0;
tmp_249_reg_6860[37] <= 1'b0;
tmp_249_reg_6860[38] <= 1'b0;
tmp_249_reg_6860[39] <= 1'b0;
tmp_249_reg_6860[40] <= 1'b0;
tmp_249_reg_6860[41] <= 1'b0;
tmp_249_reg_6860[42] <= 1'b0;
tmp_249_reg_6860[43] <= 1'b0;
tmp_249_reg_6860[44] <= 1'b0;
tmp_249_reg_6860[45] <= 1'b0;
tmp_249_reg_6860[46] <= 1'b0;
tmp_249_reg_6860[47] <= 1'b0;
tmp_249_reg_6860[48] <= 1'b0;
tmp_249_reg_6860[49] <= 1'b0;
tmp_249_reg_6860[50] <= 1'b0;
tmp_249_reg_6860[51] <= 1'b0;
tmp_249_reg_6860[52] <= 1'b0;
tmp_249_reg_6860[53] <= 1'b0;
tmp_249_reg_6860[54] <= 1'b0;
tmp_249_reg_6860[55] <= 1'b0;
tmp_249_reg_6860[56] <= 1'b0;
tmp_249_reg_6860[57] <= 1'b0;
tmp_249_reg_6860[58] <= 1'b0;
tmp_249_reg_6860[59] <= 1'b0;
tmp_249_reg_6860[60] <= 1'b0;
tmp_249_reg_6860[61] <= 1'b0;
tmp_249_reg_6860[62] <= 1'b0;
tmp_249_reg_6860[63] <= 1'b0;
end
always @ (ap_clk)
begin
tmp_250_reg_6870[14] <= 1'b0;
tmp_250_reg_6870[15] <= 1'b0;
tmp_250_reg_6870[16] <= 1'b0;
tmp_250_reg_6870[17] <= 1'b0;
tmp_250_reg_6870[18] <= 1'b0;
tmp_250_reg_6870[19] <= 1'b0;
tmp_250_reg_6870[20] <= 1'b0;
tmp_250_reg_6870[21] <= 1'b0;
tmp_250_reg_6870[22] <= 1'b0;
tmp_250_reg_6870[23] <= 1'b0;
tmp_250_reg_6870[24] <= 1'b0;
tmp_250_reg_6870[25] <= 1'b0;
tmp_250_reg_6870[26] <= 1'b0;
tmp_250_reg_6870[27] <= 1'b0;
tmp_250_reg_6870[28] <= 1'b0;
tmp_250_reg_6870[29] <= 1'b0;
tmp_250_reg_6870[30] <= 1'b0;
tmp_250_reg_6870[31] <= 1'b0;
tmp_250_reg_6870[32] <= 1'b0;
tmp_250_reg_6870[33] <= 1'b0;
tmp_250_reg_6870[34] <= 1'b0;
tmp_250_reg_6870[35] <= 1'b0;
tmp_250_reg_6870[36] <= 1'b0;
tmp_250_reg_6870[37] <= 1'b0;
tmp_250_reg_6870[38] <= 1'b0;
tmp_250_reg_6870[39] <= 1'b0;
tmp_250_reg_6870[40] <= 1'b0;
tmp_250_reg_6870[41] <= 1'b0;
tmp_250_reg_6870[42] <= 1'b0;
tmp_250_reg_6870[43] <= 1'b0;
tmp_250_reg_6870[44] <= 1'b0;
tmp_250_reg_6870[45] <= 1'b0;
tmp_250_reg_6870[46] <= 1'b0;
tmp_250_reg_6870[47] <= 1'b0;
tmp_250_reg_6870[48] <= 1'b0;
tmp_250_reg_6870[49] <= 1'b0;
tmp_250_reg_6870[50] <= 1'b0;
tmp_250_reg_6870[51] <= 1'b0;
tmp_250_reg_6870[52] <= 1'b0;
tmp_250_reg_6870[53] <= 1'b0;
tmp_250_reg_6870[54] <= 1'b0;
tmp_250_reg_6870[55] <= 1'b0;
tmp_250_reg_6870[56] <= 1'b0;
tmp_250_reg_6870[57] <= 1'b0;
tmp_250_reg_6870[58] <= 1'b0;
tmp_250_reg_6870[59] <= 1'b0;
tmp_250_reg_6870[60] <= 1'b0;
tmp_250_reg_6870[61] <= 1'b0;
tmp_250_reg_6870[62] <= 1'b0;
tmp_250_reg_6870[63] <= 1'b0;
end
always @ (ap_clk)
begin
tmp_251_reg_6880[0] <= 1'b1;
tmp_251_reg_6880[1] <= 1'b1;
tmp_251_reg_6880[14] <= 1'b0;
tmp_251_reg_6880[15] <= 1'b0;
tmp_251_reg_6880[16] <= 1'b0;
tmp_251_reg_6880[17] <= 1'b0;
tmp_251_reg_6880[18] <= 1'b0;
tmp_251_reg_6880[19] <= 1'b0;
tmp_251_reg_6880[20] <= 1'b0;
tmp_251_reg_6880[21] <= 1'b0;
tmp_251_reg_6880[22] <= 1'b0;
tmp_251_reg_6880[23] <= 1'b0;
tmp_251_reg_6880[24] <= 1'b0;
tmp_251_reg_6880[25] <= 1'b0;
tmp_251_reg_6880[26] <= 1'b0;
tmp_251_reg_6880[27] <= 1'b0;
tmp_251_reg_6880[28] <= 1'b0;
tmp_251_reg_6880[29] <= 1'b0;
tmp_251_reg_6880[30] <= 1'b0;
tmp_251_reg_6880[31] <= 1'b0;
tmp_251_reg_6880[32] <= 1'b0;
tmp_251_reg_6880[33] <= 1'b0;
tmp_251_reg_6880[34] <= 1'b0;
tmp_251_reg_6880[35] <= 1'b0;
tmp_251_reg_6880[36] <= 1'b0;
tmp_251_reg_6880[37] <= 1'b0;
tmp_251_reg_6880[38] <= 1'b0;
tmp_251_reg_6880[39] <= 1'b0;
tmp_251_reg_6880[40] <= 1'b0;
tmp_251_reg_6880[41] <= 1'b0;
tmp_251_reg_6880[42] <= 1'b0;
tmp_251_reg_6880[43] <= 1'b0;
tmp_251_reg_6880[44] <= 1'b0;
tmp_251_reg_6880[45] <= 1'b0;
tmp_251_reg_6880[46] <= 1'b0;
tmp_251_reg_6880[47] <= 1'b0;
tmp_251_reg_6880[48] <= 1'b0;
tmp_251_reg_6880[49] <= 1'b0;
tmp_251_reg_6880[50] <= 1'b0;
tmp_251_reg_6880[51] <= 1'b0;
tmp_251_reg_6880[52] <= 1'b0;
tmp_251_reg_6880[53] <= 1'b0;
tmp_251_reg_6880[54] <= 1'b0;
tmp_251_reg_6880[55] <= 1'b0;
tmp_251_reg_6880[56] <= 1'b0;
tmp_251_reg_6880[57] <= 1'b0;
tmp_251_reg_6880[58] <= 1'b0;
tmp_251_reg_6880[59] <= 1'b0;
tmp_251_reg_6880[60] <= 1'b0;
tmp_251_reg_6880[61] <= 1'b0;
tmp_251_reg_6880[62] <= 1'b0;
tmp_251_reg_6880[63] <= 1'b0;
end
always @ (ap_clk)
begin
tmp_252_reg_6890[14] <= 1'b0;
tmp_252_reg_6890[15] <= 1'b0;
tmp_252_reg_6890[16] <= 1'b0;
tmp_252_reg_6890[17] <= 1'b0;
tmp_252_reg_6890[18] <= 1'b0;
tmp_252_reg_6890[19] <= 1'b0;
tmp_252_reg_6890[20] <= 1'b0;
tmp_252_reg_6890[21] <= 1'b0;
tmp_252_reg_6890[22] <= 1'b0;
tmp_252_reg_6890[23] <= 1'b0;
tmp_252_reg_6890[24] <= 1'b0;
tmp_252_reg_6890[25] <= 1'b0;
tmp_252_reg_6890[26] <= 1'b0;
tmp_252_reg_6890[27] <= 1'b0;
tmp_252_reg_6890[28] <= 1'b0;
tmp_252_reg_6890[29] <= 1'b0;
tmp_252_reg_6890[30] <= 1'b0;
tmp_252_reg_6890[31] <= 1'b0;
tmp_252_reg_6890[32] <= 1'b0;
tmp_252_reg_6890[33] <= 1'b0;
tmp_252_reg_6890[34] <= 1'b0;
tmp_252_reg_6890[35] <= 1'b0;
tmp_252_reg_6890[36] <= 1'b0;
tmp_252_reg_6890[37] <= 1'b0;
tmp_252_reg_6890[38] <= 1'b0;
tmp_252_reg_6890[39] <= 1'b0;
tmp_252_reg_6890[40] <= 1'b0;
tmp_252_reg_6890[41] <= 1'b0;
tmp_252_reg_6890[42] <= 1'b0;
tmp_252_reg_6890[43] <= 1'b0;
tmp_252_reg_6890[44] <= 1'b0;
tmp_252_reg_6890[45] <= 1'b0;
tmp_252_reg_6890[46] <= 1'b0;
tmp_252_reg_6890[47] <= 1'b0;
tmp_252_reg_6890[48] <= 1'b0;
tmp_252_reg_6890[49] <= 1'b0;
tmp_252_reg_6890[50] <= 1'b0;
tmp_252_reg_6890[51] <= 1'b0;
tmp_252_reg_6890[52] <= 1'b0;
tmp_252_reg_6890[53] <= 1'b0;
tmp_252_reg_6890[54] <= 1'b0;
tmp_252_reg_6890[55] <= 1'b0;
tmp_252_reg_6890[56] <= 1'b0;
tmp_252_reg_6890[57] <= 1'b0;
tmp_252_reg_6890[58] <= 1'b0;
tmp_252_reg_6890[59] <= 1'b0;
tmp_252_reg_6890[60] <= 1'b0;
tmp_252_reg_6890[61] <= 1'b0;
tmp_252_reg_6890[62] <= 1'b0;
tmp_252_reg_6890[63] <= 1'b0;
end
always @ (ap_clk)
begin
tmp_253_reg_6900[0] <= 1'b1;
tmp_253_reg_6900[14] <= 1'b0;
tmp_253_reg_6900[15] <= 1'b0;
tmp_253_reg_6900[16] <= 1'b0;
tmp_253_reg_6900[17] <= 1'b0;
tmp_253_reg_6900[18] <= 1'b0;
tmp_253_reg_6900[19] <= 1'b0;
tmp_253_reg_6900[20] <= 1'b0;
tmp_253_reg_6900[21] <= 1'b0;
tmp_253_reg_6900[22] <= 1'b0;
tmp_253_reg_6900[23] <= 1'b0;
tmp_253_reg_6900[24] <= 1'b0;
tmp_253_reg_6900[25] <= 1'b0;
tmp_253_reg_6900[26] <= 1'b0;
tmp_253_reg_6900[27] <= 1'b0;
tmp_253_reg_6900[28] <= 1'b0;
tmp_253_reg_6900[29] <= 1'b0;
tmp_253_reg_6900[30] <= 1'b0;
tmp_253_reg_6900[31] <= 1'b0;
tmp_253_reg_6900[32] <= 1'b0;
tmp_253_reg_6900[33] <= 1'b0;
tmp_253_reg_6900[34] <= 1'b0;
tmp_253_reg_6900[35] <= 1'b0;
tmp_253_reg_6900[36] <= 1'b0;
tmp_253_reg_6900[37] <= 1'b0;
tmp_253_reg_6900[38] <= 1'b0;
tmp_253_reg_6900[39] <= 1'b0;
tmp_253_reg_6900[40] <= 1'b0;
tmp_253_reg_6900[41] <= 1'b0;
tmp_253_reg_6900[42] <= 1'b0;
tmp_253_reg_6900[43] <= 1'b0;
tmp_253_reg_6900[44] <= 1'b0;
tmp_253_reg_6900[45] <= 1'b0;
tmp_253_reg_6900[46] <= 1'b0;
tmp_253_reg_6900[47] <= 1'b0;
tmp_253_reg_6900[48] <= 1'b0;
tmp_253_reg_6900[49] <= 1'b0;
tmp_253_reg_6900[50] <= 1'b0;
tmp_253_reg_6900[51] <= 1'b0;
tmp_253_reg_6900[52] <= 1'b0;
tmp_253_reg_6900[53] <= 1'b0;
tmp_253_reg_6900[54] <= 1'b0;
tmp_253_reg_6900[55] <= 1'b0;
tmp_253_reg_6900[56] <= 1'b0;
tmp_253_reg_6900[57] <= 1'b0;
tmp_253_reg_6900[58] <= 1'b0;
tmp_253_reg_6900[59] <= 1'b0;
tmp_253_reg_6900[60] <= 1'b0;
tmp_253_reg_6900[61] <= 1'b0;
tmp_253_reg_6900[62] <= 1'b0;
tmp_253_reg_6900[63] <= 1'b0;
end
always @ (ap_clk)
begin
tmp_254_reg_6910[14] <= 1'b0;
tmp_254_reg_6910[15] <= 1'b0;
tmp_254_reg_6910[16] <= 1'b0;
tmp_254_reg_6910[17] <= 1'b0;
tmp_254_reg_6910[18] <= 1'b0;
tmp_254_reg_6910[19] <= 1'b0;
tmp_254_reg_6910[20] <= 1'b0;
tmp_254_reg_6910[21] <= 1'b0;
tmp_254_reg_6910[22] <= 1'b0;
tmp_254_reg_6910[23] <= 1'b0;
tmp_254_reg_6910[24] <= 1'b0;
tmp_254_reg_6910[25] <= 1'b0;
tmp_254_reg_6910[26] <= 1'b0;
tmp_254_reg_6910[27] <= 1'b0;
tmp_254_reg_6910[28] <= 1'b0;
tmp_254_reg_6910[29] <= 1'b0;
tmp_254_reg_6910[30] <= 1'b0;
tmp_254_reg_6910[31] <= 1'b0;
tmp_254_reg_6910[32] <= 1'b0;
tmp_254_reg_6910[33] <= 1'b0;
tmp_254_reg_6910[34] <= 1'b0;
tmp_254_reg_6910[35] <= 1'b0;
tmp_254_reg_6910[36] <= 1'b0;
tmp_254_reg_6910[37] <= 1'b0;
tmp_254_reg_6910[38] <= 1'b0;
tmp_254_reg_6910[39] <= 1'b0;
tmp_254_reg_6910[40] <= 1'b0;
tmp_254_reg_6910[41] <= 1'b0;
tmp_254_reg_6910[42] <= 1'b0;
tmp_254_reg_6910[43] <= 1'b0;
tmp_254_reg_6910[44] <= 1'b0;
tmp_254_reg_6910[45] <= 1'b0;
tmp_254_reg_6910[46] <= 1'b0;
tmp_254_reg_6910[47] <= 1'b0;
tmp_254_reg_6910[48] <= 1'b0;
tmp_254_reg_6910[49] <= 1'b0;
tmp_254_reg_6910[50] <= 1'b0;
tmp_254_reg_6910[51] <= 1'b0;
tmp_254_reg_6910[52] <= 1'b0;
tmp_254_reg_6910[53] <= 1'b0;
tmp_254_reg_6910[54] <= 1'b0;
tmp_254_reg_6910[55] <= 1'b0;
tmp_254_reg_6910[56] <= 1'b0;
tmp_254_reg_6910[57] <= 1'b0;
tmp_254_reg_6910[58] <= 1'b0;
tmp_254_reg_6910[59] <= 1'b0;
tmp_254_reg_6910[60] <= 1'b0;
tmp_254_reg_6910[61] <= 1'b0;
tmp_254_reg_6910[62] <= 1'b0;
tmp_254_reg_6910[63] <= 1'b0;
end
always @ (ap_clk)
begin
tmp_255_reg_6920[0] <= 1'b1;
tmp_255_reg_6920[1] <= 1'b1;
tmp_255_reg_6920[2] <= 1'b1;
tmp_255_reg_6920[14] <= 1'b0;
tmp_255_reg_6920[15] <= 1'b0;
tmp_255_reg_6920[16] <= 1'b0;
tmp_255_reg_6920[17] <= 1'b0;
tmp_255_reg_6920[18] <= 1'b0;
tmp_255_reg_6920[19] <= 1'b0;
tmp_255_reg_6920[20] <= 1'b0;
tmp_255_reg_6920[21] <= 1'b0;
tmp_255_reg_6920[22] <= 1'b0;
tmp_255_reg_6920[23] <= 1'b0;
tmp_255_reg_6920[24] <= 1'b0;
tmp_255_reg_6920[25] <= 1'b0;
tmp_255_reg_6920[26] <= 1'b0;
tmp_255_reg_6920[27] <= 1'b0;
tmp_255_reg_6920[28] <= 1'b0;
tmp_255_reg_6920[29] <= 1'b0;
tmp_255_reg_6920[30] <= 1'b0;
tmp_255_reg_6920[31] <= 1'b0;
tmp_255_reg_6920[32] <= 1'b0;
tmp_255_reg_6920[33] <= 1'b0;
tmp_255_reg_6920[34] <= 1'b0;
tmp_255_reg_6920[35] <= 1'b0;
tmp_255_reg_6920[36] <= 1'b0;
tmp_255_reg_6920[37] <= 1'b0;
tmp_255_reg_6920[38] <= 1'b0;
tmp_255_reg_6920[39] <= 1'b0;
tmp_255_reg_6920[40] <= 1'b0;
tmp_255_reg_6920[41] <= 1'b0;
tmp_255_reg_6920[42] <= 1'b0;
tmp_255_reg_6920[43] <= 1'b0;
tmp_255_reg_6920[44] <= 1'b0;
tmp_255_reg_6920[45] <= 1'b0;
tmp_255_reg_6920[46] <= 1'b0;
tmp_255_reg_6920[47] <= 1'b0;
tmp_255_reg_6920[48] <= 1'b0;
tmp_255_reg_6920[49] <= 1'b0;
tmp_255_reg_6920[50] <= 1'b0;
tmp_255_reg_6920[51] <= 1'b0;
tmp_255_reg_6920[52] <= 1'b0;
tmp_255_reg_6920[53] <= 1'b0;
tmp_255_reg_6920[54] <= 1'b0;
tmp_255_reg_6920[55] <= 1'b0;
tmp_255_reg_6920[56] <= 1'b0;
tmp_255_reg_6920[57] <= 1'b0;
tmp_255_reg_6920[58] <= 1'b0;
tmp_255_reg_6920[59] <= 1'b0;
tmp_255_reg_6920[60] <= 1'b0;
tmp_255_reg_6920[61] <= 1'b0;
tmp_255_reg_6920[62] <= 1'b0;
tmp_255_reg_6920[63] <= 1'b0;
end
endmodule //step0
|
// ==============================================================
// File generated by AutoESL - High-Level Synthesis System (C, C++, SystemC)
// Version: 2011.1
// Copyright (C) 2011 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module step0_grp_fu_2163_ACMP_fadd_5(
clk,
reset,
ce,
din0,
din1,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
output[dout_WIDTH - 1:0] dout;
ACMP_fadd #(
.ID( ID ),
.NUM_STAGE( 5 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_fadd_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ));
endmodule
|
// ==============================================================
// File generated by AutoESL - High-Level Synthesis System (C, C++, SystemC)
// Version: 2011.1
// Copyright (C) 2011 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module step0_grp_fu_2167_ACMP_fmul_6(
clk,
reset,
ce,
din0,
din1,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
output[dout_WIDTH - 1:0] dout;
ACMP_fmul #(
.ID( ID ),
.NUM_STAGE( 4 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_fmul_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ));
endmodule
|
// ==============================================================
// RTL generated by AutoESL - High-Level Synthesis System (C, C++, SystemC)
// Version: 2011.1
// Copyright (C) 2011 Xilinx Inc. All rights reserved.
//
// ===========================================================
`timescale 1 ns / 1 ps
module step1 (
ap_clk,
ap_rst,
ap_start,
ap_done,
ap_idle,
step,
tag,
counter,
c_address0,
c_ce0,
c_q0,
c_address1,
c_ce1,
c_q1,
b_address0,
b_ce0,
b_q0,
b_address1,
b_ce1,
b_q1,
d_address0,
d_ce0,
d_we0,
d_d0,
d_address1,
d_ce1,
d_we1,
d_d1,
c1_address0,
c1_ce0,
c1_we0,
c1_d0,
c1_address1,
c1_ce1,
c1_we1,
c1_d1,
BoundryScale,
nu,
PostScale
);
input ap_clk;
input ap_rst;
input ap_start;
output ap_done;
output ap_idle;
input [0:0] step;
input [1:0] tag;
input [6:0] counter;
output [11:0] c_address0;
output c_ce0;
input [31:0] c_q0;
output [11:0] c_address1;
output c_ce1;
input [31:0] c_q1;
output [11:0] b_address0;
output b_ce0;
input [31:0] b_q0;
output [11:0] b_address1;
output b_ce1;
input [31:0] b_q1;
output [11:0] d_address0;
output d_ce0;
output d_we0;
output [31:0] d_d0;
output [11:0] d_address1;
output d_ce1;
output d_we1;
output [31:0] d_d1;
output [11:0] c1_address0;
output c1_ce0;
output c1_we0;
output [31:0] c1_d0;
output [11:0] c1_address1;
output c1_ce1;
output c1_we1;
output [31:0] c1_d1;
input [31:0] BoundryScale;
input [31:0] nu;
input [31:0] PostScale;
reg ap_done;
reg ap_idle;
reg[11:0] c_address0;
reg c_ce0;
reg[11:0] c_address1;
reg c_ce1;
reg[11:0] b_address0;
reg b_ce0;
reg[11:0] b_address1;
reg b_ce1;
reg[11:0] d_address0;
reg d_ce0;
reg d_we0;
reg[31:0] d_d0;
reg[11:0] d_address1;
reg d_ce1;
reg d_we1;
reg[31:0] d_d1;
reg[11:0] c1_address0;
reg c1_ce0;
reg c1_we0;
reg[31:0] c1_d0;
reg[11:0] c1_address1;
reg c1_ce1;
reg c1_we1;
reg[31:0] c1_d1;
reg [4:0] ap_CS_fsm;
reg [9:0] indvar_flatten_reg_722;
reg [6:0] i_reg_733;
reg [3:0] indvar3_reg_744;
reg [6:0] j_reg_755;
reg [9:0] indvar_flatten9_reg_766;
reg [6:0] i1_reg_777;
reg [3:0] indvar_reg_788;
reg [6:0] j1_reg_799;
reg [31:0] reg_823;
reg ap_reg_ppiten_pp0_it0;
reg ap_reg_ppiten_pp0_it1;
reg [0:0] exitcond_reg_1446;
reg ap_reg_ppiten_pp1_it0;
reg ap_reg_ppiten_pp1_it1;
reg ap_reg_ppiten_pp1_it2;
reg ap_reg_ppiten_pp1_it3;
reg [0:0] exitcond2_reg_1603;
reg [31:0] reg_829;
reg [31:0] reg_835;
reg [31:0] reg_841;
reg [31:0] reg_847;
reg [31:0] reg_853;
reg [31:0] reg_859;
wire [31:0] grp_fu_815_p2;
reg [31:0] reg_865;
reg [0:0] ap_reg_ppstg_exitcond_reg_1446_pp0_it1;
reg [0:0] or_cond_reg_1433;
reg [0:0] ap_reg_ppstg_exitcond2_reg_1603_pp1_it2;
reg [31:0] reg_874;
wire [31:0] grp_fu_819_p2;
reg [31:0] reg_882;
reg [31:0] reg_890;
reg [31:0] reg_898;
reg [31:0] reg_906;
reg [31:0] reg_914;
reg [31:0] reg_922;
reg [31:0] reg_928;
wire [0:0] tmp_2_fu_951_p2;
wire [0:0] exitcond_fu_957_p2;
reg [9:0] indvar_flatten_next_reg_1450;
wire [6:0] j_mid2_fu_975_p3;
reg [6:0] j_mid2_reg_1455;
wire [6:0] i_mid2_fu_989_p3;
reg [6:0] i_mid2_reg_1467;
wire [13:0] b_addr_cast_fu_1011_p1;
reg [13:0] b_addr_cast_reg_1472;
wire [63:0] tmp_6_fu_1021_p1;
reg [63:0] tmp_6_reg_1483;
reg [63:0] ap_reg_ppstg_tmp_6_reg_1483_pp0_it1;
reg [3:0] indvar_next4_reg_1495;
wire [63:0] tmp_7_fu_1054_p1;
reg [63:0] tmp_7_reg_1500;
reg [63:0] ap_reg_ppstg_tmp_7_reg_1500_pp0_it1;
wire [63:0] tmp_9_fu_1073_p1;
reg [63:0] tmp_9_reg_1512;
reg [63:0] ap_reg_ppstg_tmp_9_reg_1512_pp0_it1;
wire [63:0] tmp_11_fu_1092_p1;
reg [63:0] tmp_11_reg_1524;
reg [63:0] ap_reg_ppstg_tmp_11_reg_1524_pp0_it1;
wire [63:0] tmp_13_fu_1111_p1;
reg [63:0] tmp_13_reg_1536;
reg [63:0] ap_reg_ppstg_tmp_13_reg_1536_pp0_it1;
wire [63:0] tmp_15_fu_1130_p1;
reg [63:0] tmp_15_reg_1548;
reg [63:0] ap_reg_ppstg_tmp_15_reg_1548_pp0_it1;
wire [63:0] tmp_17_fu_1149_p1;
reg [63:0] tmp_17_reg_1560;
reg [63:0] ap_reg_ppstg_tmp_17_reg_1560_pp0_it1;
wire [13:0] b_addr8_fu_1163_p2;
reg [13:0] b_addr8_reg_1572;
reg [6:0] tmp_28_reg_1577;
wire [63:0] tmp_19_fu_1173_p1;
reg [63:0] tmp_19_reg_1582;
reg [63:0] ap_reg_ppstg_tmp_19_reg_1582_pp0_it1;
wire [0:0] or_cond1_fu_1187_p2;
wire [0:0] exitcond2_fu_1193_p2;
reg [0:0] ap_reg_ppstg_exitcond2_reg_1603_pp1_it1;
reg [0:0] ap_reg_ppstg_exitcond2_reg_1603_pp1_it3;
reg [9:0] indvar_flatten_next1_reg_1607;
wire [6:0] j1_mid2_fu_1211_p3;
reg [6:0] j1_mid2_reg_1612;
wire [6:0] i1_mid2_fu_1225_p3;
reg [6:0] i1_mid2_reg_1624;
wire [13:0] b_addr9_cast_fu_1247_p1;
reg [13:0] b_addr9_cast_reg_1629;
wire [63:0] tmp_30_fu_1257_p1;
reg [63:0] tmp_30_reg_1640;
reg [63:0] ap_reg_ppstg_tmp_30_reg_1640_pp1_it1;
reg [63:0] ap_reg_ppstg_tmp_30_reg_1640_pp1_it2;
reg [3:0] indvar_next_reg_1657;
wire [63:0] tmp_33_fu_1291_p1;
reg [63:0] tmp_33_reg_1662;
reg [63:0] ap_reg_ppstg_tmp_33_reg_1662_pp1_it1;
reg [63:0] ap_reg_ppstg_tmp_33_reg_1662_pp1_it2;
wire [63:0] tmp_36_fu_1311_p1;
reg [63:0] tmp_36_reg_1679;
reg [63:0] ap_reg_ppstg_tmp_36_reg_1679_pp1_it1;
reg [63:0] ap_reg_ppstg_tmp_36_reg_1679_pp1_it2;
reg [31:0] c_load_1_reg_1696;
reg [31:0] c_load_2_reg_1701;
wire [63:0] tmp_39_fu_1331_p1;
reg [63:0] tmp_39_reg_1706;
reg [63:0] ap_reg_ppstg_tmp_39_reg_1706_pp1_it1;
reg [63:0] ap_reg_ppstg_tmp_39_reg_1706_pp1_it2;
wire [63:0] tmp_42_fu_1351_p1;
reg [63:0] tmp_42_reg_1723;
reg [63:0] ap_reg_ppstg_tmp_42_reg_1723_pp1_it1;
reg [63:0] ap_reg_ppstg_tmp_42_reg_1723_pp1_it2;
reg [31:0] c_load_3_reg_1740;
reg [31:0] c_load_4_reg_1745;
wire [63:0] tmp_45_fu_1371_p1;
reg [63:0] tmp_45_reg_1750;
reg [63:0] ap_reg_ppstg_tmp_45_reg_1750_pp1_it1;
reg [63:0] ap_reg_ppstg_tmp_45_reg_1750_pp1_it2;
wire [63:0] tmp_48_fu_1391_p1;
reg [63:0] tmp_48_reg_1767;
reg [63:0] ap_reg_ppstg_tmp_48_reg_1767_pp1_it1;
reg [63:0] ap_reg_ppstg_tmp_48_reg_1767_pp1_it2;
wire [13:0] b_addr17_fu_1406_p2;
reg [13:0] b_addr17_reg_1784;
reg [6:0] tmp_61_reg_1789;
reg [31:0] c_load_5_reg_1794;
reg [31:0] c_load_6_reg_1799;
wire [63:0] tmp_51_fu_1416_p1;
reg [63:0] tmp_51_reg_1804;
reg [63:0] ap_reg_ppstg_tmp_51_reg_1804_pp1_it1;
reg [63:0] ap_reg_ppstg_tmp_51_reg_1804_pp1_it2;
reg [31:0] b_load_15_reg_1821;
reg [31:0] tmp_52_reg_1826;
wire [31:0] grp_fu_811_p2;
reg [31:0] t_reg_1831;
reg [31:0] t8_reg_1838;
reg [31:0] t9_reg_1845;
reg [31:0] t10_reg_1852;
reg [31:0] t11_reg_1859;
reg [31:0] t12_reg_1866;
reg [31:0] t13_reg_1873;
reg [31:0] t14_reg_1880;
reg [31:0] tmp_57_reg_1887;
reg [31:0] tmp_58_reg_1892;
reg [31:0] tmp_60_reg_1897;
reg [9:0] indvar_flatten_phi_fu_726_p4;
reg [6:0] i_phi_fu_737_p4;
reg [3:0] indvar3_phi_fu_748_p4;
reg [6:0] j_phi_fu_759_p4;
reg [9:0] indvar_flatten9_phi_fu_770_p4;
reg [6:0] i1_phi_fu_781_p4;
reg [3:0] indvar_phi_fu_792_p4;
reg [6:0] j1_phi_fu_803_p4;
reg [31:0] grp_fu_811_p0;
reg [31:0] grp_fu_811_p1;
reg [31:0] grp_fu_815_p0;
reg [31:0] grp_fu_815_p1;
reg [31:0] grp_fu_819_p0;
reg [31:0] grp_fu_819_p1;
wire [0:0] tmp_fu_933_p2;
wire [0:0] tmp_1_fu_939_p2;
wire [0:0] exitcond1_fu_969_p2;
wire [6:0] tmp_6_dup_fu_983_p2;
wire [12:0] tmp_3_trn_cast_fu_997_p1;
wire [12:0] b_addr_fu_1005_p2;
wire [13:0] tmp_7_trn_cast_fu_1001_p1;
wire [13:0] b_addr1_fu_1015_p2;
wire [3:0] indvar3_op_fu_1026_p2;
wire [6:0] tmp_8_fu_1040_p2;
wire [13:0] tmp_9_trn_cast_fu_1045_p1;
wire [13:0] b_addr2_fu_1049_p2;
wire [6:0] tmp_s_fu_1059_p2;
wire [13:0] tmp_10_trn_cast_fu_1064_p1;
wire [13:0] b_addr3_fu_1068_p2;
wire [6:0] tmp_10_fu_1078_p2;
wire [13:0] tmp_12_trn_cast_fu_1083_p1;
wire [13:0] b_addr4_fu_1087_p2;
wire [6:0] tmp_12_fu_1097_p2;
wire [13:0] tmp_14_trn_cast_fu_1102_p1;
wire [13:0] b_addr5_fu_1106_p2;
wire [6:0] tmp_14_fu_1116_p2;
wire [13:0] tmp_16_trn_cast_fu_1121_p1;
wire [13:0] b_addr6_fu_1125_p2;
wire [6:0] tmp_16_fu_1135_p2;
wire [13:0] tmp_18_trn_cast_fu_1140_p1;
wire [13:0] b_addr7_fu_1144_p2;
wire [6:0] tmp_18_fu_1154_p2;
wire [13:0] tmp_20_trn_cast_fu_1159_p1;
wire [0:0] tmp_4_fu_1177_p2;
wire [0:0] tmp_5_fu_1182_p2;
wire [0:0] exitcond3_fu_1205_p2;
wire [6:0] tmp_31_dup_fu_1219_p2;
wire [12:0] tmp_29_trn_cast_fu_1233_p1;
wire [12:0] b_addr9_fu_1241_p2;
wire [13:0] tmp_32_trn_cast_fu_1237_p1;
wire [13:0] b_addr10_fu_1251_p2;
wire [3:0] indvar_op_fu_1263_p2;
wire [6:0] tmp_32_fu_1277_p2;
wire [13:0] tmp_35_trn_cast_fu_1282_p1;
wire [13:0] b_addr11_fu_1286_p2;
wire [6:0] tmp_35_fu_1297_p2;
wire [13:0] tmp_38_trn_cast_fu_1302_p1;
wire [13:0] b_addr12_fu_1306_p2;
wire [6:0] tmp_38_fu_1317_p2;
wire [13:0] tmp_41_trn_cast_fu_1322_p1;
wire [13:0] b_addr13_fu_1326_p2;
wire [6:0] tmp_41_fu_1337_p2;
wire [13:0] tmp_44_trn_cast_fu_1342_p1;
wire [13:0] b_addr14_fu_1346_p2;
wire [6:0] tmp_44_fu_1357_p2;
wire [13:0] tmp_47_trn_cast_fu_1362_p1;
wire [13:0] b_addr15_fu_1366_p2;
wire [6:0] tmp_47_fu_1377_p2;
wire [13:0] tmp_50_trn_cast_fu_1382_p1;
wire [13:0] b_addr16_fu_1386_p2;
wire [6:0] tmp_50_fu_1397_p2;
wire [13:0] tmp_53_trn_cast_fu_1402_p1;
wire grp_fu_811_ce;
wire grp_fu_815_ce;
wire grp_fu_819_ce;
reg [4:0] ap_NS_fsm;
parameter ap_const_logic_1 = 1'b1;
parameter ap_const_logic_0 = 1'b0;
parameter ap_ST_st0_fsm_0 = 5'b00000;
parameter ap_ST_st1_fsm_1 = 5'b00001;
parameter ap_ST_pp0_stg0_fsm_2 = 5'b00010;
parameter ap_ST_pp0_stg1_fsm_3 = 5'b00011;
parameter ap_ST_pp0_stg2_fsm_4 = 5'b00100;
parameter ap_ST_pp0_stg3_fsm_5 = 5'b00101;
parameter ap_ST_pp0_stg4_fsm_6 = 5'b00110;
parameter ap_ST_pp0_stg5_fsm_7 = 5'b00111;
parameter ap_ST_pp0_stg6_fsm_8 = 5'b01000;
parameter ap_ST_pp0_stg7_fsm_9 = 5'b01001;
parameter ap_ST_st17_fsm_10 = 5'b01010;
parameter ap_ST_pp1_stg0_fsm_11 = 5'b01011;
parameter ap_ST_pp1_stg1_fsm_12 = 5'b01100;
parameter ap_ST_pp1_stg2_fsm_13 = 5'b01101;
parameter ap_ST_pp1_stg3_fsm_14 = 5'b01110;
parameter ap_ST_pp1_stg4_fsm_15 = 5'b01111;
parameter ap_ST_pp1_stg5_fsm_16 = 5'b10000;
parameter ap_ST_pp1_stg6_fsm_17 = 5'b10001;
parameter ap_ST_pp1_stg7_fsm_18 = 5'b10010;
parameter ap_ST_st44_fsm_19 = 5'b10011;
parameter ap_const_lv1_0 = 1'b0;
parameter ap_const_lv10_0 = 10'b0000000000;
parameter ap_const_lv7_0 = 7'b0000000;
parameter ap_const_lv4_0 = 4'b0000;
parameter ap_const_lv2_1 = 2'b01;
parameter ap_const_lv1_1 = 1'b1;
parameter ap_const_lv7_2 = 7'b0000010;
parameter ap_const_lv10_200 = 10'b1000000000;
parameter ap_const_lv10_1 = 10'b0000000001;
parameter ap_const_lv4_8 = 4'b1000;
parameter ap_const_lv7_1 = 7'b0000001;
parameter ap_const_lv13_6 = 13'b0000000000110;
parameter ap_const_lv4_1 = 4'b0001;
parameter ap_const_lv7_3 = 7'b0000011;
parameter ap_const_lv7_4 = 7'b0000100;
parameter ap_const_lv7_5 = 7'b0000101;
parameter ap_const_lv7_6 = 7'b0000110;
parameter ap_const_lv7_7 = 7'b0000111;
parameter ap_const_lv7_8 = 7'b0001000;
parameter ap_const_lv7_42 = 7'b1000010;
parameter ap_true = 1'b1;
step1_grp_fu_811_ACMP_fadd_13 #(
.ID( 13 ),
.NUM_STAGE( 5 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
step1_grp_fu_811_ACMP_fadd_13_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_811_p0 ),
.din1( grp_fu_811_p1 ),
.ce( grp_fu_811_ce ),
.dout( grp_fu_811_p2 )
);
step1_grp_fu_815_ACMP_fmul_14 #(
.ID( 14 ),
.NUM_STAGE( 4 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
step1_grp_fu_815_ACMP_fmul_14_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_815_p0 ),
.din1( grp_fu_815_p1 ),
.ce( grp_fu_815_ce ),
.dout( grp_fu_815_p2 )
);
step1_grp_fu_819_ACMP_fmul_15 #(
.ID( 15 ),
.NUM_STAGE( 4 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
step1_grp_fu_819_ACMP_fmul_15_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_819_p0 ),
.din1( grp_fu_819_p1 ),
.ce( grp_fu_819_ce ),
.dout( grp_fu_819_p2 )
);
/// ap_CS_fsm assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_CS_fsm
if (ap_rst == 1'b1) begin
ap_CS_fsm <= ap_ST_st0_fsm_0;
end else begin
ap_CS_fsm <= ap_NS_fsm;
end
end
/// ap_reg_ppiten_pp0_it0 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it0
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it0 <= ap_const_logic_0;
end else begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond_fu_957_p2))) begin
ap_reg_ppiten_pp0_it0 <= ap_const_logic_0;
end else if (((ap_ST_st1_fsm_1 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_2_fu_951_p2))) begin
ap_reg_ppiten_pp0_it0 <= ap_const_logic_1;
end
end
end
/// ap_reg_ppiten_pp0_it1 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it1
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it1 <= ap_const_logic_0;
end else begin
if (((exitcond_reg_1446 == ap_const_lv1_0) & (ap_ST_pp0_stg7_fsm_9 == ap_CS_fsm))) begin
ap_reg_ppiten_pp0_it1 <= ap_const_logic_1;
end else if ((((ap_ST_st1_fsm_1 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_2_fu_951_p2)) | ((ap_ST_pp0_stg7_fsm_9 == ap_CS_fsm) & ~(exitcond_reg_1446 == ap_const_lv1_0)))) begin
ap_reg_ppiten_pp0_it1 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp1_it0 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp1_it0
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp1_it0 <= ap_const_logic_0;
end else begin
if (((ap_ST_pp1_stg0_fsm_11 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond2_fu_1193_p2))) begin
ap_reg_ppiten_pp1_it0 <= ap_const_logic_0;
end else if (((ap_ST_st17_fsm_10 == ap_CS_fsm) & ~(ap_const_lv1_0 == or_cond1_fu_1187_p2))) begin
ap_reg_ppiten_pp1_it0 <= ap_const_logic_1;
end
end
end
/// ap_reg_ppiten_pp1_it1 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp1_it1
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp1_it1 <= ap_const_logic_0;
end else begin
if (((ap_const_lv1_0 == exitcond2_reg_1603) & (ap_ST_pp1_stg7_fsm_18 == ap_CS_fsm))) begin
ap_reg_ppiten_pp1_it1 <= ap_const_logic_1;
end else if ((((ap_ST_st17_fsm_10 == ap_CS_fsm) & ~(ap_const_lv1_0 == or_cond1_fu_1187_p2)) | ((ap_ST_pp1_stg7_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond2_reg_1603)))) begin
ap_reg_ppiten_pp1_it1 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp1_it2 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp1_it2
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp1_it2 <= ap_const_logic_0;
end else begin
if ((ap_ST_pp1_stg7_fsm_18 == ap_CS_fsm)) begin
ap_reg_ppiten_pp1_it2 <= ap_reg_ppiten_pp1_it1;
end else if (((ap_ST_st17_fsm_10 == ap_CS_fsm) & ~(ap_const_lv1_0 == or_cond1_fu_1187_p2))) begin
ap_reg_ppiten_pp1_it2 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp1_it3 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp1_it3
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp1_it3 <= ap_const_logic_0;
end else begin
if ((ap_ST_pp1_stg7_fsm_18 == ap_CS_fsm)) begin
ap_reg_ppiten_pp1_it3 <= ap_reg_ppiten_pp1_it2;
end else if (((ap_ST_st17_fsm_10 == ap_CS_fsm) & ~(ap_const_lv1_0 == or_cond1_fu_1187_p2))) begin
ap_reg_ppiten_pp1_it3 <= ap_const_logic_0;
end
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_ST_pp1_stg0_fsm_11 == ap_CS_fsm)) begin
ap_reg_ppstg_exitcond2_reg_1603_pp1_it1 <= exitcond2_reg_1603;
end
if ((ap_ST_pp1_stg0_fsm_11 == ap_CS_fsm)) begin
ap_reg_ppstg_exitcond2_reg_1603_pp1_it2 <= ap_reg_ppstg_exitcond2_reg_1603_pp1_it1;
end
if ((ap_ST_pp1_stg0_fsm_11 == ap_CS_fsm)) begin
ap_reg_ppstg_exitcond2_reg_1603_pp1_it3 <= ap_reg_ppstg_exitcond2_reg_1603_pp1_it2;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_exitcond_reg_1446_pp0_it1 <= exitcond_reg_1446;
end
if ((ap_ST_pp0_stg2_fsm_4 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_11_reg_1524_pp0_it1[2] <= tmp_11_reg_1524[2];
ap_reg_ppstg_tmp_11_reg_1524_pp0_it1[3] <= tmp_11_reg_1524[3];
ap_reg_ppstg_tmp_11_reg_1524_pp0_it1[4] <= tmp_11_reg_1524[4];
ap_reg_ppstg_tmp_11_reg_1524_pp0_it1[5] <= tmp_11_reg_1524[5];
ap_reg_ppstg_tmp_11_reg_1524_pp0_it1[6] <= tmp_11_reg_1524[6];
ap_reg_ppstg_tmp_11_reg_1524_pp0_it1[7] <= tmp_11_reg_1524[7];
ap_reg_ppstg_tmp_11_reg_1524_pp0_it1[8] <= tmp_11_reg_1524[8];
ap_reg_ppstg_tmp_11_reg_1524_pp0_it1[9] <= tmp_11_reg_1524[9];
ap_reg_ppstg_tmp_11_reg_1524_pp0_it1[10] <= tmp_11_reg_1524[10];
ap_reg_ppstg_tmp_11_reg_1524_pp0_it1[11] <= tmp_11_reg_1524[11];
ap_reg_ppstg_tmp_11_reg_1524_pp0_it1[12] <= tmp_11_reg_1524[12];
ap_reg_ppstg_tmp_11_reg_1524_pp0_it1[13] <= tmp_11_reg_1524[13];
end
if ((ap_ST_pp0_stg2_fsm_4 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_13_reg_1536_pp0_it1[0] <= tmp_13_reg_1536[0];
ap_reg_ppstg_tmp_13_reg_1536_pp0_it1[1] <= tmp_13_reg_1536[1];
ap_reg_ppstg_tmp_13_reg_1536_pp0_it1[2] <= tmp_13_reg_1536[2];
ap_reg_ppstg_tmp_13_reg_1536_pp0_it1[3] <= tmp_13_reg_1536[3];
ap_reg_ppstg_tmp_13_reg_1536_pp0_it1[4] <= tmp_13_reg_1536[4];
ap_reg_ppstg_tmp_13_reg_1536_pp0_it1[5] <= tmp_13_reg_1536[5];
ap_reg_ppstg_tmp_13_reg_1536_pp0_it1[6] <= tmp_13_reg_1536[6];
ap_reg_ppstg_tmp_13_reg_1536_pp0_it1[7] <= tmp_13_reg_1536[7];
ap_reg_ppstg_tmp_13_reg_1536_pp0_it1[8] <= tmp_13_reg_1536[8];
ap_reg_ppstg_tmp_13_reg_1536_pp0_it1[9] <= tmp_13_reg_1536[9];
ap_reg_ppstg_tmp_13_reg_1536_pp0_it1[10] <= tmp_13_reg_1536[10];
ap_reg_ppstg_tmp_13_reg_1536_pp0_it1[11] <= tmp_13_reg_1536[11];
ap_reg_ppstg_tmp_13_reg_1536_pp0_it1[12] <= tmp_13_reg_1536[12];
ap_reg_ppstg_tmp_13_reg_1536_pp0_it1[13] <= tmp_13_reg_1536[13];
end
if ((ap_ST_pp0_stg3_fsm_5 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_15_reg_1548_pp0_it1[1] <= tmp_15_reg_1548[1];
ap_reg_ppstg_tmp_15_reg_1548_pp0_it1[2] <= tmp_15_reg_1548[2];
ap_reg_ppstg_tmp_15_reg_1548_pp0_it1[3] <= tmp_15_reg_1548[3];
ap_reg_ppstg_tmp_15_reg_1548_pp0_it1[4] <= tmp_15_reg_1548[4];
ap_reg_ppstg_tmp_15_reg_1548_pp0_it1[5] <= tmp_15_reg_1548[5];
ap_reg_ppstg_tmp_15_reg_1548_pp0_it1[6] <= tmp_15_reg_1548[6];
ap_reg_ppstg_tmp_15_reg_1548_pp0_it1[7] <= tmp_15_reg_1548[7];
ap_reg_ppstg_tmp_15_reg_1548_pp0_it1[8] <= tmp_15_reg_1548[8];
ap_reg_ppstg_tmp_15_reg_1548_pp0_it1[9] <= tmp_15_reg_1548[9];
ap_reg_ppstg_tmp_15_reg_1548_pp0_it1[10] <= tmp_15_reg_1548[10];
ap_reg_ppstg_tmp_15_reg_1548_pp0_it1[11] <= tmp_15_reg_1548[11];
ap_reg_ppstg_tmp_15_reg_1548_pp0_it1[12] <= tmp_15_reg_1548[12];
ap_reg_ppstg_tmp_15_reg_1548_pp0_it1[13] <= tmp_15_reg_1548[13];
end
if ((ap_ST_pp0_stg3_fsm_5 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_17_reg_1560_pp0_it1[0] <= tmp_17_reg_1560[0];
ap_reg_ppstg_tmp_17_reg_1560_pp0_it1[1] <= tmp_17_reg_1560[1];
ap_reg_ppstg_tmp_17_reg_1560_pp0_it1[2] <= tmp_17_reg_1560[2];
ap_reg_ppstg_tmp_17_reg_1560_pp0_it1[3] <= tmp_17_reg_1560[3];
ap_reg_ppstg_tmp_17_reg_1560_pp0_it1[4] <= tmp_17_reg_1560[4];
ap_reg_ppstg_tmp_17_reg_1560_pp0_it1[5] <= tmp_17_reg_1560[5];
ap_reg_ppstg_tmp_17_reg_1560_pp0_it1[6] <= tmp_17_reg_1560[6];
ap_reg_ppstg_tmp_17_reg_1560_pp0_it1[7] <= tmp_17_reg_1560[7];
ap_reg_ppstg_tmp_17_reg_1560_pp0_it1[8] <= tmp_17_reg_1560[8];
ap_reg_ppstg_tmp_17_reg_1560_pp0_it1[9] <= tmp_17_reg_1560[9];
ap_reg_ppstg_tmp_17_reg_1560_pp0_it1[10] <= tmp_17_reg_1560[10];
ap_reg_ppstg_tmp_17_reg_1560_pp0_it1[11] <= tmp_17_reg_1560[11];
ap_reg_ppstg_tmp_17_reg_1560_pp0_it1[12] <= tmp_17_reg_1560[12];
ap_reg_ppstg_tmp_17_reg_1560_pp0_it1[13] <= tmp_17_reg_1560[13];
end
if ((ap_ST_pp0_stg4_fsm_6 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_19_reg_1582_pp0_it1[3] <= tmp_19_reg_1582[3];
ap_reg_ppstg_tmp_19_reg_1582_pp0_it1[4] <= tmp_19_reg_1582[4];
ap_reg_ppstg_tmp_19_reg_1582_pp0_it1[5] <= tmp_19_reg_1582[5];
ap_reg_ppstg_tmp_19_reg_1582_pp0_it1[6] <= tmp_19_reg_1582[6];
ap_reg_ppstg_tmp_19_reg_1582_pp0_it1[7] <= tmp_19_reg_1582[7];
ap_reg_ppstg_tmp_19_reg_1582_pp0_it1[8] <= tmp_19_reg_1582[8];
ap_reg_ppstg_tmp_19_reg_1582_pp0_it1[9] <= tmp_19_reg_1582[9];
ap_reg_ppstg_tmp_19_reg_1582_pp0_it1[10] <= tmp_19_reg_1582[10];
ap_reg_ppstg_tmp_19_reg_1582_pp0_it1[11] <= tmp_19_reg_1582[11];
ap_reg_ppstg_tmp_19_reg_1582_pp0_it1[12] <= tmp_19_reg_1582[12];
ap_reg_ppstg_tmp_19_reg_1582_pp0_it1[13] <= tmp_19_reg_1582[13];
end
if ((ap_ST_pp1_stg0_fsm_11 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_30_reg_1640_pp1_it1[0] <= tmp_30_reg_1640[0];
ap_reg_ppstg_tmp_30_reg_1640_pp1_it1[1] <= tmp_30_reg_1640[1];
ap_reg_ppstg_tmp_30_reg_1640_pp1_it1[2] <= tmp_30_reg_1640[2];
ap_reg_ppstg_tmp_30_reg_1640_pp1_it1[3] <= tmp_30_reg_1640[3];
ap_reg_ppstg_tmp_30_reg_1640_pp1_it1[4] <= tmp_30_reg_1640[4];
ap_reg_ppstg_tmp_30_reg_1640_pp1_it1[5] <= tmp_30_reg_1640[5];
ap_reg_ppstg_tmp_30_reg_1640_pp1_it1[6] <= tmp_30_reg_1640[6];
ap_reg_ppstg_tmp_30_reg_1640_pp1_it1[7] <= tmp_30_reg_1640[7];
ap_reg_ppstg_tmp_30_reg_1640_pp1_it1[8] <= tmp_30_reg_1640[8];
ap_reg_ppstg_tmp_30_reg_1640_pp1_it1[9] <= tmp_30_reg_1640[9];
ap_reg_ppstg_tmp_30_reg_1640_pp1_it1[10] <= tmp_30_reg_1640[10];
ap_reg_ppstg_tmp_30_reg_1640_pp1_it1[11] <= tmp_30_reg_1640[11];
ap_reg_ppstg_tmp_30_reg_1640_pp1_it1[12] <= tmp_30_reg_1640[12];
ap_reg_ppstg_tmp_30_reg_1640_pp1_it1[13] <= tmp_30_reg_1640[13];
end
if ((ap_ST_pp1_stg0_fsm_11 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_30_reg_1640_pp1_it2[0] <= ap_reg_ppstg_tmp_30_reg_1640_pp1_it1[0];
ap_reg_ppstg_tmp_30_reg_1640_pp1_it2[1] <= ap_reg_ppstg_tmp_30_reg_1640_pp1_it1[1];
ap_reg_ppstg_tmp_30_reg_1640_pp1_it2[2] <= ap_reg_ppstg_tmp_30_reg_1640_pp1_it1[2];
ap_reg_ppstg_tmp_30_reg_1640_pp1_it2[3] <= ap_reg_ppstg_tmp_30_reg_1640_pp1_it1[3];
ap_reg_ppstg_tmp_30_reg_1640_pp1_it2[4] <= ap_reg_ppstg_tmp_30_reg_1640_pp1_it1[4];
ap_reg_ppstg_tmp_30_reg_1640_pp1_it2[5] <= ap_reg_ppstg_tmp_30_reg_1640_pp1_it1[5];
ap_reg_ppstg_tmp_30_reg_1640_pp1_it2[6] <= ap_reg_ppstg_tmp_30_reg_1640_pp1_it1[6];
ap_reg_ppstg_tmp_30_reg_1640_pp1_it2[7] <= ap_reg_ppstg_tmp_30_reg_1640_pp1_it1[7];
ap_reg_ppstg_tmp_30_reg_1640_pp1_it2[8] <= ap_reg_ppstg_tmp_30_reg_1640_pp1_it1[8];
ap_reg_ppstg_tmp_30_reg_1640_pp1_it2[9] <= ap_reg_ppstg_tmp_30_reg_1640_pp1_it1[9];
ap_reg_ppstg_tmp_30_reg_1640_pp1_it2[10] <= ap_reg_ppstg_tmp_30_reg_1640_pp1_it1[10];
ap_reg_ppstg_tmp_30_reg_1640_pp1_it2[11] <= ap_reg_ppstg_tmp_30_reg_1640_pp1_it1[11];
ap_reg_ppstg_tmp_30_reg_1640_pp1_it2[12] <= ap_reg_ppstg_tmp_30_reg_1640_pp1_it1[12];
ap_reg_ppstg_tmp_30_reg_1640_pp1_it2[13] <= ap_reg_ppstg_tmp_30_reg_1640_pp1_it1[13];
end
if ((ap_ST_pp1_stg1_fsm_12 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_33_reg_1662_pp1_it1[1] <= tmp_33_reg_1662[1];
ap_reg_ppstg_tmp_33_reg_1662_pp1_it1[2] <= tmp_33_reg_1662[2];
ap_reg_ppstg_tmp_33_reg_1662_pp1_it1[3] <= tmp_33_reg_1662[3];
ap_reg_ppstg_tmp_33_reg_1662_pp1_it1[4] <= tmp_33_reg_1662[4];
ap_reg_ppstg_tmp_33_reg_1662_pp1_it1[5] <= tmp_33_reg_1662[5];
ap_reg_ppstg_tmp_33_reg_1662_pp1_it1[6] <= tmp_33_reg_1662[6];
ap_reg_ppstg_tmp_33_reg_1662_pp1_it1[7] <= tmp_33_reg_1662[7];
ap_reg_ppstg_tmp_33_reg_1662_pp1_it1[8] <= tmp_33_reg_1662[8];
ap_reg_ppstg_tmp_33_reg_1662_pp1_it1[9] <= tmp_33_reg_1662[9];
ap_reg_ppstg_tmp_33_reg_1662_pp1_it1[10] <= tmp_33_reg_1662[10];
ap_reg_ppstg_tmp_33_reg_1662_pp1_it1[11] <= tmp_33_reg_1662[11];
ap_reg_ppstg_tmp_33_reg_1662_pp1_it1[12] <= tmp_33_reg_1662[12];
ap_reg_ppstg_tmp_33_reg_1662_pp1_it1[13] <= tmp_33_reg_1662[13];
end
if ((ap_ST_pp1_stg1_fsm_12 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_33_reg_1662_pp1_it2[1] <= ap_reg_ppstg_tmp_33_reg_1662_pp1_it1[1];
ap_reg_ppstg_tmp_33_reg_1662_pp1_it2[2] <= ap_reg_ppstg_tmp_33_reg_1662_pp1_it1[2];
ap_reg_ppstg_tmp_33_reg_1662_pp1_it2[3] <= ap_reg_ppstg_tmp_33_reg_1662_pp1_it1[3];
ap_reg_ppstg_tmp_33_reg_1662_pp1_it2[4] <= ap_reg_ppstg_tmp_33_reg_1662_pp1_it1[4];
ap_reg_ppstg_tmp_33_reg_1662_pp1_it2[5] <= ap_reg_ppstg_tmp_33_reg_1662_pp1_it1[5];
ap_reg_ppstg_tmp_33_reg_1662_pp1_it2[6] <= ap_reg_ppstg_tmp_33_reg_1662_pp1_it1[6];
ap_reg_ppstg_tmp_33_reg_1662_pp1_it2[7] <= ap_reg_ppstg_tmp_33_reg_1662_pp1_it1[7];
ap_reg_ppstg_tmp_33_reg_1662_pp1_it2[8] <= ap_reg_ppstg_tmp_33_reg_1662_pp1_it1[8];
ap_reg_ppstg_tmp_33_reg_1662_pp1_it2[9] <= ap_reg_ppstg_tmp_33_reg_1662_pp1_it1[9];
ap_reg_ppstg_tmp_33_reg_1662_pp1_it2[10] <= ap_reg_ppstg_tmp_33_reg_1662_pp1_it1[10];
ap_reg_ppstg_tmp_33_reg_1662_pp1_it2[11] <= ap_reg_ppstg_tmp_33_reg_1662_pp1_it1[11];
ap_reg_ppstg_tmp_33_reg_1662_pp1_it2[12] <= ap_reg_ppstg_tmp_33_reg_1662_pp1_it1[12];
ap_reg_ppstg_tmp_33_reg_1662_pp1_it2[13] <= ap_reg_ppstg_tmp_33_reg_1662_pp1_it1[13];
end
if ((ap_ST_pp1_stg1_fsm_12 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_36_reg_1679_pp1_it1[0] <= tmp_36_reg_1679[0];
ap_reg_ppstg_tmp_36_reg_1679_pp1_it1[1] <= tmp_36_reg_1679[1];
ap_reg_ppstg_tmp_36_reg_1679_pp1_it1[2] <= tmp_36_reg_1679[2];
ap_reg_ppstg_tmp_36_reg_1679_pp1_it1[3] <= tmp_36_reg_1679[3];
ap_reg_ppstg_tmp_36_reg_1679_pp1_it1[4] <= tmp_36_reg_1679[4];
ap_reg_ppstg_tmp_36_reg_1679_pp1_it1[5] <= tmp_36_reg_1679[5];
ap_reg_ppstg_tmp_36_reg_1679_pp1_it1[6] <= tmp_36_reg_1679[6];
ap_reg_ppstg_tmp_36_reg_1679_pp1_it1[7] <= tmp_36_reg_1679[7];
ap_reg_ppstg_tmp_36_reg_1679_pp1_it1[8] <= tmp_36_reg_1679[8];
ap_reg_ppstg_tmp_36_reg_1679_pp1_it1[9] <= tmp_36_reg_1679[9];
ap_reg_ppstg_tmp_36_reg_1679_pp1_it1[10] <= tmp_36_reg_1679[10];
ap_reg_ppstg_tmp_36_reg_1679_pp1_it1[11] <= tmp_36_reg_1679[11];
ap_reg_ppstg_tmp_36_reg_1679_pp1_it1[12] <= tmp_36_reg_1679[12];
ap_reg_ppstg_tmp_36_reg_1679_pp1_it1[13] <= tmp_36_reg_1679[13];
end
if ((ap_ST_pp1_stg1_fsm_12 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_36_reg_1679_pp1_it2[0] <= ap_reg_ppstg_tmp_36_reg_1679_pp1_it1[0];
ap_reg_ppstg_tmp_36_reg_1679_pp1_it2[1] <= ap_reg_ppstg_tmp_36_reg_1679_pp1_it1[1];
ap_reg_ppstg_tmp_36_reg_1679_pp1_it2[2] <= ap_reg_ppstg_tmp_36_reg_1679_pp1_it1[2];
ap_reg_ppstg_tmp_36_reg_1679_pp1_it2[3] <= ap_reg_ppstg_tmp_36_reg_1679_pp1_it1[3];
ap_reg_ppstg_tmp_36_reg_1679_pp1_it2[4] <= ap_reg_ppstg_tmp_36_reg_1679_pp1_it1[4];
ap_reg_ppstg_tmp_36_reg_1679_pp1_it2[5] <= ap_reg_ppstg_tmp_36_reg_1679_pp1_it1[5];
ap_reg_ppstg_tmp_36_reg_1679_pp1_it2[6] <= ap_reg_ppstg_tmp_36_reg_1679_pp1_it1[6];
ap_reg_ppstg_tmp_36_reg_1679_pp1_it2[7] <= ap_reg_ppstg_tmp_36_reg_1679_pp1_it1[7];
ap_reg_ppstg_tmp_36_reg_1679_pp1_it2[8] <= ap_reg_ppstg_tmp_36_reg_1679_pp1_it1[8];
ap_reg_ppstg_tmp_36_reg_1679_pp1_it2[9] <= ap_reg_ppstg_tmp_36_reg_1679_pp1_it1[9];
ap_reg_ppstg_tmp_36_reg_1679_pp1_it2[10] <= ap_reg_ppstg_tmp_36_reg_1679_pp1_it1[10];
ap_reg_ppstg_tmp_36_reg_1679_pp1_it2[11] <= ap_reg_ppstg_tmp_36_reg_1679_pp1_it1[11];
ap_reg_ppstg_tmp_36_reg_1679_pp1_it2[12] <= ap_reg_ppstg_tmp_36_reg_1679_pp1_it1[12];
ap_reg_ppstg_tmp_36_reg_1679_pp1_it2[13] <= ap_reg_ppstg_tmp_36_reg_1679_pp1_it1[13];
end
if ((ap_ST_pp1_stg2_fsm_13 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_39_reg_1706_pp1_it1[2] <= tmp_39_reg_1706[2];
ap_reg_ppstg_tmp_39_reg_1706_pp1_it1[3] <= tmp_39_reg_1706[3];
ap_reg_ppstg_tmp_39_reg_1706_pp1_it1[4] <= tmp_39_reg_1706[4];
ap_reg_ppstg_tmp_39_reg_1706_pp1_it1[5] <= tmp_39_reg_1706[5];
ap_reg_ppstg_tmp_39_reg_1706_pp1_it1[6] <= tmp_39_reg_1706[6];
ap_reg_ppstg_tmp_39_reg_1706_pp1_it1[7] <= tmp_39_reg_1706[7];
ap_reg_ppstg_tmp_39_reg_1706_pp1_it1[8] <= tmp_39_reg_1706[8];
ap_reg_ppstg_tmp_39_reg_1706_pp1_it1[9] <= tmp_39_reg_1706[9];
ap_reg_ppstg_tmp_39_reg_1706_pp1_it1[10] <= tmp_39_reg_1706[10];
ap_reg_ppstg_tmp_39_reg_1706_pp1_it1[11] <= tmp_39_reg_1706[11];
ap_reg_ppstg_tmp_39_reg_1706_pp1_it1[12] <= tmp_39_reg_1706[12];
ap_reg_ppstg_tmp_39_reg_1706_pp1_it1[13] <= tmp_39_reg_1706[13];
end
if ((ap_ST_pp1_stg2_fsm_13 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_39_reg_1706_pp1_it2[2] <= ap_reg_ppstg_tmp_39_reg_1706_pp1_it1[2];
ap_reg_ppstg_tmp_39_reg_1706_pp1_it2[3] <= ap_reg_ppstg_tmp_39_reg_1706_pp1_it1[3];
ap_reg_ppstg_tmp_39_reg_1706_pp1_it2[4] <= ap_reg_ppstg_tmp_39_reg_1706_pp1_it1[4];
ap_reg_ppstg_tmp_39_reg_1706_pp1_it2[5] <= ap_reg_ppstg_tmp_39_reg_1706_pp1_it1[5];
ap_reg_ppstg_tmp_39_reg_1706_pp1_it2[6] <= ap_reg_ppstg_tmp_39_reg_1706_pp1_it1[6];
ap_reg_ppstg_tmp_39_reg_1706_pp1_it2[7] <= ap_reg_ppstg_tmp_39_reg_1706_pp1_it1[7];
ap_reg_ppstg_tmp_39_reg_1706_pp1_it2[8] <= ap_reg_ppstg_tmp_39_reg_1706_pp1_it1[8];
ap_reg_ppstg_tmp_39_reg_1706_pp1_it2[9] <= ap_reg_ppstg_tmp_39_reg_1706_pp1_it1[9];
ap_reg_ppstg_tmp_39_reg_1706_pp1_it2[10] <= ap_reg_ppstg_tmp_39_reg_1706_pp1_it1[10];
ap_reg_ppstg_tmp_39_reg_1706_pp1_it2[11] <= ap_reg_ppstg_tmp_39_reg_1706_pp1_it1[11];
ap_reg_ppstg_tmp_39_reg_1706_pp1_it2[12] <= ap_reg_ppstg_tmp_39_reg_1706_pp1_it1[12];
ap_reg_ppstg_tmp_39_reg_1706_pp1_it2[13] <= ap_reg_ppstg_tmp_39_reg_1706_pp1_it1[13];
end
if ((ap_ST_pp1_stg2_fsm_13 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_42_reg_1723_pp1_it1[0] <= tmp_42_reg_1723[0];
ap_reg_ppstg_tmp_42_reg_1723_pp1_it1[1] <= tmp_42_reg_1723[1];
ap_reg_ppstg_tmp_42_reg_1723_pp1_it1[2] <= tmp_42_reg_1723[2];
ap_reg_ppstg_tmp_42_reg_1723_pp1_it1[3] <= tmp_42_reg_1723[3];
ap_reg_ppstg_tmp_42_reg_1723_pp1_it1[4] <= tmp_42_reg_1723[4];
ap_reg_ppstg_tmp_42_reg_1723_pp1_it1[5] <= tmp_42_reg_1723[5];
ap_reg_ppstg_tmp_42_reg_1723_pp1_it1[6] <= tmp_42_reg_1723[6];
ap_reg_ppstg_tmp_42_reg_1723_pp1_it1[7] <= tmp_42_reg_1723[7];
ap_reg_ppstg_tmp_42_reg_1723_pp1_it1[8] <= tmp_42_reg_1723[8];
ap_reg_ppstg_tmp_42_reg_1723_pp1_it1[9] <= tmp_42_reg_1723[9];
ap_reg_ppstg_tmp_42_reg_1723_pp1_it1[10] <= tmp_42_reg_1723[10];
ap_reg_ppstg_tmp_42_reg_1723_pp1_it1[11] <= tmp_42_reg_1723[11];
ap_reg_ppstg_tmp_42_reg_1723_pp1_it1[12] <= tmp_42_reg_1723[12];
ap_reg_ppstg_tmp_42_reg_1723_pp1_it1[13] <= tmp_42_reg_1723[13];
end
if ((ap_ST_pp1_stg2_fsm_13 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_42_reg_1723_pp1_it2[0] <= ap_reg_ppstg_tmp_42_reg_1723_pp1_it1[0];
ap_reg_ppstg_tmp_42_reg_1723_pp1_it2[1] <= ap_reg_ppstg_tmp_42_reg_1723_pp1_it1[1];
ap_reg_ppstg_tmp_42_reg_1723_pp1_it2[2] <= ap_reg_ppstg_tmp_42_reg_1723_pp1_it1[2];
ap_reg_ppstg_tmp_42_reg_1723_pp1_it2[3] <= ap_reg_ppstg_tmp_42_reg_1723_pp1_it1[3];
ap_reg_ppstg_tmp_42_reg_1723_pp1_it2[4] <= ap_reg_ppstg_tmp_42_reg_1723_pp1_it1[4];
ap_reg_ppstg_tmp_42_reg_1723_pp1_it2[5] <= ap_reg_ppstg_tmp_42_reg_1723_pp1_it1[5];
ap_reg_ppstg_tmp_42_reg_1723_pp1_it2[6] <= ap_reg_ppstg_tmp_42_reg_1723_pp1_it1[6];
ap_reg_ppstg_tmp_42_reg_1723_pp1_it2[7] <= ap_reg_ppstg_tmp_42_reg_1723_pp1_it1[7];
ap_reg_ppstg_tmp_42_reg_1723_pp1_it2[8] <= ap_reg_ppstg_tmp_42_reg_1723_pp1_it1[8];
ap_reg_ppstg_tmp_42_reg_1723_pp1_it2[9] <= ap_reg_ppstg_tmp_42_reg_1723_pp1_it1[9];
ap_reg_ppstg_tmp_42_reg_1723_pp1_it2[10] <= ap_reg_ppstg_tmp_42_reg_1723_pp1_it1[10];
ap_reg_ppstg_tmp_42_reg_1723_pp1_it2[11] <= ap_reg_ppstg_tmp_42_reg_1723_pp1_it1[11];
ap_reg_ppstg_tmp_42_reg_1723_pp1_it2[12] <= ap_reg_ppstg_tmp_42_reg_1723_pp1_it1[12];
ap_reg_ppstg_tmp_42_reg_1723_pp1_it2[13] <= ap_reg_ppstg_tmp_42_reg_1723_pp1_it1[13];
end
if ((ap_ST_pp1_stg3_fsm_14 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_45_reg_1750_pp1_it1[1] <= tmp_45_reg_1750[1];
ap_reg_ppstg_tmp_45_reg_1750_pp1_it1[2] <= tmp_45_reg_1750[2];
ap_reg_ppstg_tmp_45_reg_1750_pp1_it1[3] <= tmp_45_reg_1750[3];
ap_reg_ppstg_tmp_45_reg_1750_pp1_it1[4] <= tmp_45_reg_1750[4];
ap_reg_ppstg_tmp_45_reg_1750_pp1_it1[5] <= tmp_45_reg_1750[5];
ap_reg_ppstg_tmp_45_reg_1750_pp1_it1[6] <= tmp_45_reg_1750[6];
ap_reg_ppstg_tmp_45_reg_1750_pp1_it1[7] <= tmp_45_reg_1750[7];
ap_reg_ppstg_tmp_45_reg_1750_pp1_it1[8] <= tmp_45_reg_1750[8];
ap_reg_ppstg_tmp_45_reg_1750_pp1_it1[9] <= tmp_45_reg_1750[9];
ap_reg_ppstg_tmp_45_reg_1750_pp1_it1[10] <= tmp_45_reg_1750[10];
ap_reg_ppstg_tmp_45_reg_1750_pp1_it1[11] <= tmp_45_reg_1750[11];
ap_reg_ppstg_tmp_45_reg_1750_pp1_it1[12] <= tmp_45_reg_1750[12];
ap_reg_ppstg_tmp_45_reg_1750_pp1_it1[13] <= tmp_45_reg_1750[13];
end
if ((ap_ST_pp1_stg3_fsm_14 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_45_reg_1750_pp1_it2[1] <= ap_reg_ppstg_tmp_45_reg_1750_pp1_it1[1];
ap_reg_ppstg_tmp_45_reg_1750_pp1_it2[2] <= ap_reg_ppstg_tmp_45_reg_1750_pp1_it1[2];
ap_reg_ppstg_tmp_45_reg_1750_pp1_it2[3] <= ap_reg_ppstg_tmp_45_reg_1750_pp1_it1[3];
ap_reg_ppstg_tmp_45_reg_1750_pp1_it2[4] <= ap_reg_ppstg_tmp_45_reg_1750_pp1_it1[4];
ap_reg_ppstg_tmp_45_reg_1750_pp1_it2[5] <= ap_reg_ppstg_tmp_45_reg_1750_pp1_it1[5];
ap_reg_ppstg_tmp_45_reg_1750_pp1_it2[6] <= ap_reg_ppstg_tmp_45_reg_1750_pp1_it1[6];
ap_reg_ppstg_tmp_45_reg_1750_pp1_it2[7] <= ap_reg_ppstg_tmp_45_reg_1750_pp1_it1[7];
ap_reg_ppstg_tmp_45_reg_1750_pp1_it2[8] <= ap_reg_ppstg_tmp_45_reg_1750_pp1_it1[8];
ap_reg_ppstg_tmp_45_reg_1750_pp1_it2[9] <= ap_reg_ppstg_tmp_45_reg_1750_pp1_it1[9];
ap_reg_ppstg_tmp_45_reg_1750_pp1_it2[10] <= ap_reg_ppstg_tmp_45_reg_1750_pp1_it1[10];
ap_reg_ppstg_tmp_45_reg_1750_pp1_it2[11] <= ap_reg_ppstg_tmp_45_reg_1750_pp1_it1[11];
ap_reg_ppstg_tmp_45_reg_1750_pp1_it2[12] <= ap_reg_ppstg_tmp_45_reg_1750_pp1_it1[12];
ap_reg_ppstg_tmp_45_reg_1750_pp1_it2[13] <= ap_reg_ppstg_tmp_45_reg_1750_pp1_it1[13];
end
if ((ap_ST_pp1_stg3_fsm_14 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_48_reg_1767_pp1_it1[0] <= tmp_48_reg_1767[0];
ap_reg_ppstg_tmp_48_reg_1767_pp1_it1[1] <= tmp_48_reg_1767[1];
ap_reg_ppstg_tmp_48_reg_1767_pp1_it1[2] <= tmp_48_reg_1767[2];
ap_reg_ppstg_tmp_48_reg_1767_pp1_it1[3] <= tmp_48_reg_1767[3];
ap_reg_ppstg_tmp_48_reg_1767_pp1_it1[4] <= tmp_48_reg_1767[4];
ap_reg_ppstg_tmp_48_reg_1767_pp1_it1[5] <= tmp_48_reg_1767[5];
ap_reg_ppstg_tmp_48_reg_1767_pp1_it1[6] <= tmp_48_reg_1767[6];
ap_reg_ppstg_tmp_48_reg_1767_pp1_it1[7] <= tmp_48_reg_1767[7];
ap_reg_ppstg_tmp_48_reg_1767_pp1_it1[8] <= tmp_48_reg_1767[8];
ap_reg_ppstg_tmp_48_reg_1767_pp1_it1[9] <= tmp_48_reg_1767[9];
ap_reg_ppstg_tmp_48_reg_1767_pp1_it1[10] <= tmp_48_reg_1767[10];
ap_reg_ppstg_tmp_48_reg_1767_pp1_it1[11] <= tmp_48_reg_1767[11];
ap_reg_ppstg_tmp_48_reg_1767_pp1_it1[12] <= tmp_48_reg_1767[12];
ap_reg_ppstg_tmp_48_reg_1767_pp1_it1[13] <= tmp_48_reg_1767[13];
end
if ((ap_ST_pp1_stg3_fsm_14 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_48_reg_1767_pp1_it2[0] <= ap_reg_ppstg_tmp_48_reg_1767_pp1_it1[0];
ap_reg_ppstg_tmp_48_reg_1767_pp1_it2[1] <= ap_reg_ppstg_tmp_48_reg_1767_pp1_it1[1];
ap_reg_ppstg_tmp_48_reg_1767_pp1_it2[2] <= ap_reg_ppstg_tmp_48_reg_1767_pp1_it1[2];
ap_reg_ppstg_tmp_48_reg_1767_pp1_it2[3] <= ap_reg_ppstg_tmp_48_reg_1767_pp1_it1[3];
ap_reg_ppstg_tmp_48_reg_1767_pp1_it2[4] <= ap_reg_ppstg_tmp_48_reg_1767_pp1_it1[4];
ap_reg_ppstg_tmp_48_reg_1767_pp1_it2[5] <= ap_reg_ppstg_tmp_48_reg_1767_pp1_it1[5];
ap_reg_ppstg_tmp_48_reg_1767_pp1_it2[6] <= ap_reg_ppstg_tmp_48_reg_1767_pp1_it1[6];
ap_reg_ppstg_tmp_48_reg_1767_pp1_it2[7] <= ap_reg_ppstg_tmp_48_reg_1767_pp1_it1[7];
ap_reg_ppstg_tmp_48_reg_1767_pp1_it2[8] <= ap_reg_ppstg_tmp_48_reg_1767_pp1_it1[8];
ap_reg_ppstg_tmp_48_reg_1767_pp1_it2[9] <= ap_reg_ppstg_tmp_48_reg_1767_pp1_it1[9];
ap_reg_ppstg_tmp_48_reg_1767_pp1_it2[10] <= ap_reg_ppstg_tmp_48_reg_1767_pp1_it1[10];
ap_reg_ppstg_tmp_48_reg_1767_pp1_it2[11] <= ap_reg_ppstg_tmp_48_reg_1767_pp1_it1[11];
ap_reg_ppstg_tmp_48_reg_1767_pp1_it2[12] <= ap_reg_ppstg_tmp_48_reg_1767_pp1_it1[12];
ap_reg_ppstg_tmp_48_reg_1767_pp1_it2[13] <= ap_reg_ppstg_tmp_48_reg_1767_pp1_it1[13];
end
if ((ap_ST_pp1_stg4_fsm_15 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_51_reg_1804_pp1_it1[3] <= tmp_51_reg_1804[3];
ap_reg_ppstg_tmp_51_reg_1804_pp1_it1[4] <= tmp_51_reg_1804[4];
ap_reg_ppstg_tmp_51_reg_1804_pp1_it1[5] <= tmp_51_reg_1804[5];
ap_reg_ppstg_tmp_51_reg_1804_pp1_it1[6] <= tmp_51_reg_1804[6];
ap_reg_ppstg_tmp_51_reg_1804_pp1_it1[7] <= tmp_51_reg_1804[7];
ap_reg_ppstg_tmp_51_reg_1804_pp1_it1[8] <= tmp_51_reg_1804[8];
ap_reg_ppstg_tmp_51_reg_1804_pp1_it1[9] <= tmp_51_reg_1804[9];
ap_reg_ppstg_tmp_51_reg_1804_pp1_it1[10] <= tmp_51_reg_1804[10];
ap_reg_ppstg_tmp_51_reg_1804_pp1_it1[11] <= tmp_51_reg_1804[11];
ap_reg_ppstg_tmp_51_reg_1804_pp1_it1[12] <= tmp_51_reg_1804[12];
ap_reg_ppstg_tmp_51_reg_1804_pp1_it1[13] <= tmp_51_reg_1804[13];
end
if ((ap_ST_pp1_stg4_fsm_15 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_51_reg_1804_pp1_it2[3] <= ap_reg_ppstg_tmp_51_reg_1804_pp1_it1[3];
ap_reg_ppstg_tmp_51_reg_1804_pp1_it2[4] <= ap_reg_ppstg_tmp_51_reg_1804_pp1_it1[4];
ap_reg_ppstg_tmp_51_reg_1804_pp1_it2[5] <= ap_reg_ppstg_tmp_51_reg_1804_pp1_it1[5];
ap_reg_ppstg_tmp_51_reg_1804_pp1_it2[6] <= ap_reg_ppstg_tmp_51_reg_1804_pp1_it1[6];
ap_reg_ppstg_tmp_51_reg_1804_pp1_it2[7] <= ap_reg_ppstg_tmp_51_reg_1804_pp1_it1[7];
ap_reg_ppstg_tmp_51_reg_1804_pp1_it2[8] <= ap_reg_ppstg_tmp_51_reg_1804_pp1_it1[8];
ap_reg_ppstg_tmp_51_reg_1804_pp1_it2[9] <= ap_reg_ppstg_tmp_51_reg_1804_pp1_it1[9];
ap_reg_ppstg_tmp_51_reg_1804_pp1_it2[10] <= ap_reg_ppstg_tmp_51_reg_1804_pp1_it1[10];
ap_reg_ppstg_tmp_51_reg_1804_pp1_it2[11] <= ap_reg_ppstg_tmp_51_reg_1804_pp1_it1[11];
ap_reg_ppstg_tmp_51_reg_1804_pp1_it2[12] <= ap_reg_ppstg_tmp_51_reg_1804_pp1_it1[12];
ap_reg_ppstg_tmp_51_reg_1804_pp1_it2[13] <= ap_reg_ppstg_tmp_51_reg_1804_pp1_it1[13];
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_6_reg_1483_pp0_it1[0] <= tmp_6_reg_1483[0];
ap_reg_ppstg_tmp_6_reg_1483_pp0_it1[1] <= tmp_6_reg_1483[1];
ap_reg_ppstg_tmp_6_reg_1483_pp0_it1[2] <= tmp_6_reg_1483[2];
ap_reg_ppstg_tmp_6_reg_1483_pp0_it1[3] <= tmp_6_reg_1483[3];
ap_reg_ppstg_tmp_6_reg_1483_pp0_it1[4] <= tmp_6_reg_1483[4];
ap_reg_ppstg_tmp_6_reg_1483_pp0_it1[5] <= tmp_6_reg_1483[5];
ap_reg_ppstg_tmp_6_reg_1483_pp0_it1[6] <= tmp_6_reg_1483[6];
ap_reg_ppstg_tmp_6_reg_1483_pp0_it1[7] <= tmp_6_reg_1483[7];
ap_reg_ppstg_tmp_6_reg_1483_pp0_it1[8] <= tmp_6_reg_1483[8];
ap_reg_ppstg_tmp_6_reg_1483_pp0_it1[9] <= tmp_6_reg_1483[9];
ap_reg_ppstg_tmp_6_reg_1483_pp0_it1[10] <= tmp_6_reg_1483[10];
ap_reg_ppstg_tmp_6_reg_1483_pp0_it1[11] <= tmp_6_reg_1483[11];
ap_reg_ppstg_tmp_6_reg_1483_pp0_it1[12] <= tmp_6_reg_1483[12];
ap_reg_ppstg_tmp_6_reg_1483_pp0_it1[13] <= tmp_6_reg_1483[13];
end
if ((ap_ST_pp0_stg1_fsm_3 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_7_reg_1500_pp0_it1[1] <= tmp_7_reg_1500[1];
ap_reg_ppstg_tmp_7_reg_1500_pp0_it1[2] <= tmp_7_reg_1500[2];
ap_reg_ppstg_tmp_7_reg_1500_pp0_it1[3] <= tmp_7_reg_1500[3];
ap_reg_ppstg_tmp_7_reg_1500_pp0_it1[4] <= tmp_7_reg_1500[4];
ap_reg_ppstg_tmp_7_reg_1500_pp0_it1[5] <= tmp_7_reg_1500[5];
ap_reg_ppstg_tmp_7_reg_1500_pp0_it1[6] <= tmp_7_reg_1500[6];
ap_reg_ppstg_tmp_7_reg_1500_pp0_it1[7] <= tmp_7_reg_1500[7];
ap_reg_ppstg_tmp_7_reg_1500_pp0_it1[8] <= tmp_7_reg_1500[8];
ap_reg_ppstg_tmp_7_reg_1500_pp0_it1[9] <= tmp_7_reg_1500[9];
ap_reg_ppstg_tmp_7_reg_1500_pp0_it1[10] <= tmp_7_reg_1500[10];
ap_reg_ppstg_tmp_7_reg_1500_pp0_it1[11] <= tmp_7_reg_1500[11];
ap_reg_ppstg_tmp_7_reg_1500_pp0_it1[12] <= tmp_7_reg_1500[12];
ap_reg_ppstg_tmp_7_reg_1500_pp0_it1[13] <= tmp_7_reg_1500[13];
end
if ((ap_ST_pp0_stg1_fsm_3 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_9_reg_1512_pp0_it1[0] <= tmp_9_reg_1512[0];
ap_reg_ppstg_tmp_9_reg_1512_pp0_it1[1] <= tmp_9_reg_1512[1];
ap_reg_ppstg_tmp_9_reg_1512_pp0_it1[2] <= tmp_9_reg_1512[2];
ap_reg_ppstg_tmp_9_reg_1512_pp0_it1[3] <= tmp_9_reg_1512[3];
ap_reg_ppstg_tmp_9_reg_1512_pp0_it1[4] <= tmp_9_reg_1512[4];
ap_reg_ppstg_tmp_9_reg_1512_pp0_it1[5] <= tmp_9_reg_1512[5];
ap_reg_ppstg_tmp_9_reg_1512_pp0_it1[6] <= tmp_9_reg_1512[6];
ap_reg_ppstg_tmp_9_reg_1512_pp0_it1[7] <= tmp_9_reg_1512[7];
ap_reg_ppstg_tmp_9_reg_1512_pp0_it1[8] <= tmp_9_reg_1512[8];
ap_reg_ppstg_tmp_9_reg_1512_pp0_it1[9] <= tmp_9_reg_1512[9];
ap_reg_ppstg_tmp_9_reg_1512_pp0_it1[10] <= tmp_9_reg_1512[10];
ap_reg_ppstg_tmp_9_reg_1512_pp0_it1[11] <= tmp_9_reg_1512[11];
ap_reg_ppstg_tmp_9_reg_1512_pp0_it1[12] <= tmp_9_reg_1512[12];
ap_reg_ppstg_tmp_9_reg_1512_pp0_it1[13] <= tmp_9_reg_1512[13];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond2_reg_1603) & (ap_ST_pp1_stg3_fsm_14 == ap_CS_fsm))) begin
b_addr17_reg_1784[3] <= b_addr17_fu_1406_p2[3];
b_addr17_reg_1784[4] <= b_addr17_fu_1406_p2[4];
b_addr17_reg_1784[5] <= b_addr17_fu_1406_p2[5];
b_addr17_reg_1784[6] <= b_addr17_fu_1406_p2[6];
b_addr17_reg_1784[7] <= b_addr17_fu_1406_p2[7];
b_addr17_reg_1784[8] <= b_addr17_fu_1406_p2[8];
b_addr17_reg_1784[9] <= b_addr17_fu_1406_p2[9];
b_addr17_reg_1784[10] <= b_addr17_fu_1406_p2[10];
b_addr17_reg_1784[11] <= b_addr17_fu_1406_p2[11];
b_addr17_reg_1784[12] <= b_addr17_fu_1406_p2[12];
b_addr17_reg_1784[13] <= b_addr17_fu_1406_p2[13];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_reg_1446 == ap_const_lv1_0) & (ap_ST_pp0_stg3_fsm_5 == ap_CS_fsm))) begin
b_addr8_reg_1572[3] <= b_addr8_fu_1163_p2[3];
b_addr8_reg_1572[4] <= b_addr8_fu_1163_p2[4];
b_addr8_reg_1572[5] <= b_addr8_fu_1163_p2[5];
b_addr8_reg_1572[6] <= b_addr8_fu_1163_p2[6];
b_addr8_reg_1572[7] <= b_addr8_fu_1163_p2[7];
b_addr8_reg_1572[8] <= b_addr8_fu_1163_p2[8];
b_addr8_reg_1572[9] <= b_addr8_fu_1163_p2[9];
b_addr8_reg_1572[10] <= b_addr8_fu_1163_p2[10];
b_addr8_reg_1572[11] <= b_addr8_fu_1163_p2[11];
b_addr8_reg_1572[12] <= b_addr8_fu_1163_p2[12];
b_addr8_reg_1572[13] <= b_addr8_fu_1163_p2[13];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_ST_pp1_stg0_fsm_11 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond2_fu_1193_p2))) begin
b_addr9_cast_reg_1629[6] <= b_addr9_cast_fu_1247_p1[6];
b_addr9_cast_reg_1629[7] <= b_addr9_cast_fu_1247_p1[7];
b_addr9_cast_reg_1629[8] <= b_addr9_cast_fu_1247_p1[8];
b_addr9_cast_reg_1629[9] <= b_addr9_cast_fu_1247_p1[9];
b_addr9_cast_reg_1629[10] <= b_addr9_cast_fu_1247_p1[10];
b_addr9_cast_reg_1629[11] <= b_addr9_cast_fu_1247_p1[11];
b_addr9_cast_reg_1629[12] <= b_addr9_cast_fu_1247_p1[12];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond_fu_957_p2))) begin
b_addr_cast_reg_1472[6] <= b_addr_cast_fu_1011_p1[6];
b_addr_cast_reg_1472[7] <= b_addr_cast_fu_1011_p1[7];
b_addr_cast_reg_1472[8] <= b_addr_cast_fu_1011_p1[8];
b_addr_cast_reg_1472[9] <= b_addr_cast_fu_1011_p1[9];
b_addr_cast_reg_1472[10] <= b_addr_cast_fu_1011_p1[10];
b_addr_cast_reg_1472[11] <= b_addr_cast_fu_1011_p1[11];
b_addr_cast_reg_1472[12] <= b_addr_cast_fu_1011_p1[12];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond2_reg_1603) & (ap_ST_pp1_stg5_fsm_16 == ap_CS_fsm))) begin
b_load_15_reg_1821 <= b_q0;
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond2_reg_1603) & (ap_ST_pp1_stg2_fsm_13 == ap_CS_fsm))) begin
c_load_1_reg_1696 <= c_q0;
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond2_reg_1603) & (ap_ST_pp1_stg2_fsm_13 == ap_CS_fsm))) begin
c_load_2_reg_1701 <= c_q1;
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond2_reg_1603) & (ap_ST_pp1_stg3_fsm_14 == ap_CS_fsm))) begin
c_load_3_reg_1740 <= c_q0;
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond2_reg_1603) & (ap_ST_pp1_stg3_fsm_14 == ap_CS_fsm))) begin
c_load_4_reg_1745 <= c_q1;
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond2_reg_1603) & (ap_ST_pp1_stg4_fsm_15 == ap_CS_fsm))) begin
c_load_5_reg_1794 <= c_q0;
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond2_reg_1603) & (ap_ST_pp1_stg4_fsm_15 == ap_CS_fsm))) begin
c_load_6_reg_1799 <= c_q1;
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_ST_pp1_stg0_fsm_11 == ap_CS_fsm))) begin
exitcond2_reg_1603 <= (indvar_flatten9_phi_fu_770_p4 == ap_const_lv10_200? 1'b1: 1'b0);
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm))) begin
exitcond_reg_1446 <= (indvar_flatten_phi_fu_726_p4 == ap_const_lv10_200? 1'b1: 1'b0);
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_ST_pp1_stg0_fsm_11 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond2_fu_1193_p2))) begin
if (exitcond3_fu_1205_p2) begin
i1_mid2_reg_1624 <= tmp_31_dup_fu_1219_p2;
end else begin
i1_mid2_reg_1624 <= i1_phi_fu_781_p4;
end
end
if (((ap_ST_st17_fsm_10 == ap_CS_fsm) & ~(ap_const_lv1_0 == or_cond1_fu_1187_p2))) begin
i1_reg_777 <= ap_const_lv7_0;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_const_lv1_0 == exitcond2_reg_1603) & (ap_ST_pp1_stg0_fsm_11 == ap_CS_fsm))) begin
i1_reg_777 <= i1_mid2_reg_1624;
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond_fu_957_p2))) begin
if (exitcond1_fu_969_p2) begin
i_mid2_reg_1467 <= tmp_6_dup_fu_983_p2;
end else begin
i_mid2_reg_1467 <= i_phi_fu_737_p4;
end
end
if (((ap_ST_st1_fsm_1 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_2_fu_951_p2))) begin
i_reg_733 <= ap_const_lv7_0;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (exitcond_reg_1446 == ap_const_lv1_0) & (ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm))) begin
i_reg_733 <= i_mid2_reg_1467;
end
if (((ap_ST_st1_fsm_1 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_2_fu_951_p2))) begin
indvar3_reg_744 <= ap_const_lv4_0;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (exitcond_reg_1446 == ap_const_lv1_0) & (ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm))) begin
indvar3_reg_744 <= indvar_next4_reg_1495;
end
if (((ap_ST_st17_fsm_10 == ap_CS_fsm) & ~(ap_const_lv1_0 == or_cond1_fu_1187_p2))) begin
indvar_flatten9_reg_766 <= ap_const_lv10_0;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_const_lv1_0 == exitcond2_reg_1603) & (ap_ST_pp1_stg0_fsm_11 == ap_CS_fsm))) begin
indvar_flatten9_reg_766 <= indvar_flatten_next1_reg_1607;
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_ST_pp1_stg0_fsm_11 == ap_CS_fsm))) begin
indvar_flatten_next1_reg_1607 <= (indvar_flatten9_phi_fu_770_p4 + ap_const_lv10_1);
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm))) begin
indvar_flatten_next_reg_1450 <= (indvar_flatten_phi_fu_726_p4 + ap_const_lv10_1);
end
if (((ap_ST_st1_fsm_1 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_2_fu_951_p2))) begin
indvar_flatten_reg_722 <= ap_const_lv10_0;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (exitcond_reg_1446 == ap_const_lv1_0) & (ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm))) begin
indvar_flatten_reg_722 <= indvar_flatten_next_reg_1450;
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond_fu_957_p2))) begin
if (exitcond1_fu_969_p2) begin
indvar_next4_reg_1495 <= ap_const_lv4_1;
end else begin
indvar_next4_reg_1495 <= indvar3_op_fu_1026_p2;
end
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_ST_pp1_stg0_fsm_11 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond2_fu_1193_p2))) begin
if (exitcond3_fu_1205_p2) begin
indvar_next_reg_1657 <= ap_const_lv4_1;
end else begin
indvar_next_reg_1657 <= indvar_op_fu_1263_p2;
end
end
if (((ap_ST_st17_fsm_10 == ap_CS_fsm) & ~(ap_const_lv1_0 == or_cond1_fu_1187_p2))) begin
indvar_reg_788 <= ap_const_lv4_0;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_const_lv1_0 == exitcond2_reg_1603) & (ap_ST_pp1_stg0_fsm_11 == ap_CS_fsm))) begin
indvar_reg_788 <= indvar_next_reg_1657;
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_ST_pp1_stg0_fsm_11 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond2_fu_1193_p2))) begin
if (exitcond3_fu_1205_p2) begin
j1_mid2_reg_1612 <= ap_const_lv7_0;
end else begin
j1_mid2_reg_1612 <= j1_phi_fu_803_p4;
end
end
if (((ap_ST_st17_fsm_10 == ap_CS_fsm) & ~(ap_const_lv1_0 == or_cond1_fu_1187_p2))) begin
j1_reg_799 <= ap_const_lv7_0;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_const_lv1_0 == exitcond2_reg_1603) & (ap_ST_pp1_stg0_fsm_11 == ap_CS_fsm))) begin
j1_reg_799 <= tmp_61_reg_1789;
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond_fu_957_p2))) begin
if (exitcond1_fu_969_p2) begin
j_mid2_reg_1455 <= ap_const_lv7_0;
end else begin
j_mid2_reg_1455 <= j_phi_fu_759_p4;
end
end
if (((ap_ST_st1_fsm_1 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_2_fu_951_p2))) begin
j_reg_755 <= ap_const_lv7_0;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (exitcond_reg_1446 == ap_const_lv1_0) & (ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm))) begin
j_reg_755 <= tmp_28_reg_1577;
end
if ((ap_ST_st1_fsm_1 == ap_CS_fsm)) begin
or_cond_reg_1433 <= (tmp_fu_933_p2 & tmp_1_fu_939_p2);
end
if ((((ap_ST_pp0_stg1_fsm_3 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_reg_1446 == ap_const_lv1_0)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_reg_1446 == ap_const_lv1_0) & (ap_ST_pp0_stg5_fsm_7 == ap_CS_fsm)) | ((ap_ST_pp1_stg1_fsm_12 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond2_reg_1603)))) begin
reg_823 <= b_q0;
end
if ((((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_reg_1446 == ap_const_lv1_0) & (ap_ST_pp0_stg2_fsm_4 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond2_reg_1603) & (ap_ST_pp1_stg2_fsm_13 == ap_CS_fsm)))) begin
reg_829 <= b_q0;
end
if ((((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_reg_1446 == ap_const_lv1_0) & (ap_ST_pp0_stg2_fsm_4 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond2_reg_1603) & (ap_ST_pp1_stg2_fsm_13 == ap_CS_fsm)))) begin
reg_835 <= b_q1;
end
if ((((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_reg_1446 == ap_const_lv1_0) & (ap_ST_pp0_stg3_fsm_5 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond2_reg_1603) & (ap_ST_pp1_stg3_fsm_14 == ap_CS_fsm)))) begin
reg_841 <= b_q0;
end
if ((((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_reg_1446 == ap_const_lv1_0) & (ap_ST_pp0_stg3_fsm_5 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond2_reg_1603) & (ap_ST_pp1_stg3_fsm_14 == ap_CS_fsm)))) begin
reg_847 <= b_q1;
end
if ((((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_reg_1446 == ap_const_lv1_0) & (ap_ST_pp0_stg4_fsm_6 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond2_reg_1603) & (ap_ST_pp1_stg4_fsm_15 == ap_CS_fsm)))) begin
reg_853 <= b_q0;
end
if ((((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_reg_1446 == ap_const_lv1_0) & (ap_ST_pp0_stg4_fsm_6 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond2_reg_1603) & (ap_ST_pp1_stg4_fsm_15 == ap_CS_fsm)))) begin
reg_859 <= b_q1;
end
if ((((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_reg_1446 == ap_const_lv1_0) & (ap_ST_pp0_stg5_fsm_7 == ap_CS_fsm)) | ((ap_ST_pp0_stg1_fsm_3 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_1446_pp0_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond2_reg_1603) & (ap_ST_pp1_stg5_fsm_16 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it2) & (ap_ST_pp1_stg2_fsm_13 == ap_CS_fsm) & ~(ap_const_lv1_0 == or_cond_reg_1433) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it2)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it2) & (ap_ST_pp1_stg3_fsm_14 == ap_CS_fsm) & ~(ap_const_lv1_0 == or_cond_reg_1433) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it2)))) begin
reg_865 <= grp_fu_815_p2;
end
if ((((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_reg_1446 == ap_const_lv1_0) & (ap_ST_pp0_stg6_fsm_8 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (ap_ST_pp0_stg2_fsm_4 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_1446_pp0_it1) & ~(ap_const_lv1_0 == or_cond_reg_1433)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (ap_ST_pp0_stg3_fsm_5 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_1446_pp0_it1) & ~(ap_const_lv1_0 == or_cond_reg_1433)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (ap_ST_pp0_stg4_fsm_6 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_1446_pp0_it1) & ~(ap_const_lv1_0 == or_cond_reg_1433)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond2_reg_1603) & (ap_ST_pp1_stg6_fsm_17 == ap_CS_fsm)))) begin
reg_874 <= grp_fu_815_p2;
end
if ((((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_reg_1446 == ap_const_lv1_0) & (ap_ST_pp0_stg6_fsm_8 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (ap_ST_pp0_stg2_fsm_4 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_1446_pp0_it1) & ~(ap_const_lv1_0 == or_cond_reg_1433)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (ap_ST_pp0_stg3_fsm_5 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_1446_pp0_it1) & ~(ap_const_lv1_0 == or_cond_reg_1433)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (ap_ST_pp0_stg4_fsm_6 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_1446_pp0_it1) & ~(ap_const_lv1_0 == or_cond_reg_1433)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond2_reg_1603) & (ap_ST_pp1_stg6_fsm_17 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (ap_ST_pp0_stg5_fsm_7 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_1446_pp0_it1) & ~(ap_const_lv1_0 == or_cond_reg_1433)))) begin
reg_882 <= grp_fu_819_p2;
end
if ((((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_reg_1446 == ap_const_lv1_0) & (ap_ST_pp0_stg7_fsm_9 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond2_reg_1603) & (ap_ST_pp1_stg7_fsm_18 == ap_CS_fsm)))) begin
reg_890 <= grp_fu_815_p2;
end
if ((((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_reg_1446 == ap_const_lv1_0) & (ap_ST_pp0_stg7_fsm_9 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond2_reg_1603) & (ap_ST_pp1_stg7_fsm_18 == ap_CS_fsm)))) begin
reg_898 <= grp_fu_819_p2;
end
if ((((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (exitcond_reg_1446 == ap_const_lv1_0) & (ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_const_lv1_0 == exitcond2_reg_1603) & (ap_ST_pp1_stg0_fsm_11 == ap_CS_fsm)))) begin
reg_906 <= grp_fu_815_p2;
end
if ((((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (exitcond_reg_1446 == ap_const_lv1_0) & (ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_const_lv1_0 == exitcond2_reg_1603) & (ap_ST_pp1_stg0_fsm_11 == ap_CS_fsm)))) begin
reg_914 <= grp_fu_819_p2;
end
if ((((ap_const_logic_1 == ap_reg_ppiten_pp1_it2) & (ap_ST_pp1_stg2_fsm_13 == ap_CS_fsm) & ~(ap_const_lv1_0 == or_cond_reg_1433) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it2)) | ((ap_ST_pp0_stg1_fsm_3 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_1446_pp0_it1) & ~(ap_const_lv1_0 == or_cond_reg_1433)) | ((ap_ST_pp1_stg1_fsm_12 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it2) & ~(ap_const_lv1_0 == or_cond_reg_1433) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it2)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it2) & (ap_ST_pp1_stg4_fsm_15 == ap_CS_fsm) & ~(ap_const_lv1_0 == or_cond_reg_1433) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it2)))) begin
reg_922 <= grp_fu_819_p2;
end
if ((((ap_ST_pp1_stg1_fsm_12 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond2_reg_1603)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond2_reg_1603) & (ap_ST_pp1_stg5_fsm_16 == ap_CS_fsm)))) begin
reg_928 <= c_q0;
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_ST_pp1_stg5_fsm_16 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it1))) begin
t10_reg_1852 <= grp_fu_811_p2;
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_ST_pp1_stg6_fsm_17 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it1))) begin
t11_reg_1859 <= grp_fu_811_p2;
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_ST_pp1_stg7_fsm_18 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it1))) begin
t12_reg_1866 <= grp_fu_811_p2;
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it2) & (ap_ST_pp1_stg0_fsm_11 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it1))) begin
t13_reg_1873 <= grp_fu_811_p2;
end
if (((ap_ST_pp1_stg1_fsm_12 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it2) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it2))) begin
t14_reg_1880 <= grp_fu_811_p2;
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_ST_pp1_stg3_fsm_14 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it1))) begin
t8_reg_1838 <= grp_fu_811_p2;
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_ST_pp1_stg4_fsm_15 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it1))) begin
t9_reg_1845 <= grp_fu_811_p2;
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_ST_pp1_stg2_fsm_13 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it1))) begin
t_reg_1831 <= grp_fu_811_p2;
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_reg_1446 == ap_const_lv1_0) & (ap_ST_pp0_stg2_fsm_4 == ap_CS_fsm))) begin
tmp_11_reg_1524[2] <= tmp_11_fu_1092_p1[2];
tmp_11_reg_1524[3] <= tmp_11_fu_1092_p1[3];
tmp_11_reg_1524[4] <= tmp_11_fu_1092_p1[4];
tmp_11_reg_1524[5] <= tmp_11_fu_1092_p1[5];
tmp_11_reg_1524[6] <= tmp_11_fu_1092_p1[6];
tmp_11_reg_1524[7] <= tmp_11_fu_1092_p1[7];
tmp_11_reg_1524[8] <= tmp_11_fu_1092_p1[8];
tmp_11_reg_1524[9] <= tmp_11_fu_1092_p1[9];
tmp_11_reg_1524[10] <= tmp_11_fu_1092_p1[10];
tmp_11_reg_1524[11] <= tmp_11_fu_1092_p1[11];
tmp_11_reg_1524[12] <= tmp_11_fu_1092_p1[12];
tmp_11_reg_1524[13] <= tmp_11_fu_1092_p1[13];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_reg_1446 == ap_const_lv1_0) & (ap_ST_pp0_stg2_fsm_4 == ap_CS_fsm))) begin
tmp_13_reg_1536[0] <= tmp_13_fu_1111_p1[0];
tmp_13_reg_1536[1] <= tmp_13_fu_1111_p1[1];
tmp_13_reg_1536[2] <= tmp_13_fu_1111_p1[2];
tmp_13_reg_1536[3] <= tmp_13_fu_1111_p1[3];
tmp_13_reg_1536[4] <= tmp_13_fu_1111_p1[4];
tmp_13_reg_1536[5] <= tmp_13_fu_1111_p1[5];
tmp_13_reg_1536[6] <= tmp_13_fu_1111_p1[6];
tmp_13_reg_1536[7] <= tmp_13_fu_1111_p1[7];
tmp_13_reg_1536[8] <= tmp_13_fu_1111_p1[8];
tmp_13_reg_1536[9] <= tmp_13_fu_1111_p1[9];
tmp_13_reg_1536[10] <= tmp_13_fu_1111_p1[10];
tmp_13_reg_1536[11] <= tmp_13_fu_1111_p1[11];
tmp_13_reg_1536[12] <= tmp_13_fu_1111_p1[12];
tmp_13_reg_1536[13] <= tmp_13_fu_1111_p1[13];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_reg_1446 == ap_const_lv1_0) & (ap_ST_pp0_stg3_fsm_5 == ap_CS_fsm))) begin
tmp_15_reg_1548[1] <= tmp_15_fu_1130_p1[1];
tmp_15_reg_1548[2] <= tmp_15_fu_1130_p1[2];
tmp_15_reg_1548[3] <= tmp_15_fu_1130_p1[3];
tmp_15_reg_1548[4] <= tmp_15_fu_1130_p1[4];
tmp_15_reg_1548[5] <= tmp_15_fu_1130_p1[5];
tmp_15_reg_1548[6] <= tmp_15_fu_1130_p1[6];
tmp_15_reg_1548[7] <= tmp_15_fu_1130_p1[7];
tmp_15_reg_1548[8] <= tmp_15_fu_1130_p1[8];
tmp_15_reg_1548[9] <= tmp_15_fu_1130_p1[9];
tmp_15_reg_1548[10] <= tmp_15_fu_1130_p1[10];
tmp_15_reg_1548[11] <= tmp_15_fu_1130_p1[11];
tmp_15_reg_1548[12] <= tmp_15_fu_1130_p1[12];
tmp_15_reg_1548[13] <= tmp_15_fu_1130_p1[13];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_reg_1446 == ap_const_lv1_0) & (ap_ST_pp0_stg3_fsm_5 == ap_CS_fsm))) begin
tmp_17_reg_1560[0] <= tmp_17_fu_1149_p1[0];
tmp_17_reg_1560[1] <= tmp_17_fu_1149_p1[1];
tmp_17_reg_1560[2] <= tmp_17_fu_1149_p1[2];
tmp_17_reg_1560[3] <= tmp_17_fu_1149_p1[3];
tmp_17_reg_1560[4] <= tmp_17_fu_1149_p1[4];
tmp_17_reg_1560[5] <= tmp_17_fu_1149_p1[5];
tmp_17_reg_1560[6] <= tmp_17_fu_1149_p1[6];
tmp_17_reg_1560[7] <= tmp_17_fu_1149_p1[7];
tmp_17_reg_1560[8] <= tmp_17_fu_1149_p1[8];
tmp_17_reg_1560[9] <= tmp_17_fu_1149_p1[9];
tmp_17_reg_1560[10] <= tmp_17_fu_1149_p1[10];
tmp_17_reg_1560[11] <= tmp_17_fu_1149_p1[11];
tmp_17_reg_1560[12] <= tmp_17_fu_1149_p1[12];
tmp_17_reg_1560[13] <= tmp_17_fu_1149_p1[13];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_reg_1446 == ap_const_lv1_0) & (ap_ST_pp0_stg4_fsm_6 == ap_CS_fsm))) begin
tmp_19_reg_1582[3] <= tmp_19_fu_1173_p1[3];
tmp_19_reg_1582[4] <= tmp_19_fu_1173_p1[4];
tmp_19_reg_1582[5] <= tmp_19_fu_1173_p1[5];
tmp_19_reg_1582[6] <= tmp_19_fu_1173_p1[6];
tmp_19_reg_1582[7] <= tmp_19_fu_1173_p1[7];
tmp_19_reg_1582[8] <= tmp_19_fu_1173_p1[8];
tmp_19_reg_1582[9] <= tmp_19_fu_1173_p1[9];
tmp_19_reg_1582[10] <= tmp_19_fu_1173_p1[10];
tmp_19_reg_1582[11] <= tmp_19_fu_1173_p1[11];
tmp_19_reg_1582[12] <= tmp_19_fu_1173_p1[12];
tmp_19_reg_1582[13] <= tmp_19_fu_1173_p1[13];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_reg_1446 == ap_const_lv1_0) & (ap_ST_pp0_stg3_fsm_5 == ap_CS_fsm))) begin
tmp_28_reg_1577 <= (j_mid2_reg_1455 + ap_const_lv7_8);
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_ST_pp1_stg0_fsm_11 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond2_fu_1193_p2))) begin
tmp_30_reg_1640[0] <= tmp_30_fu_1257_p1[0];
tmp_30_reg_1640[1] <= tmp_30_fu_1257_p1[1];
tmp_30_reg_1640[2] <= tmp_30_fu_1257_p1[2];
tmp_30_reg_1640[3] <= tmp_30_fu_1257_p1[3];
tmp_30_reg_1640[4] <= tmp_30_fu_1257_p1[4];
tmp_30_reg_1640[5] <= tmp_30_fu_1257_p1[5];
tmp_30_reg_1640[6] <= tmp_30_fu_1257_p1[6];
tmp_30_reg_1640[7] <= tmp_30_fu_1257_p1[7];
tmp_30_reg_1640[8] <= tmp_30_fu_1257_p1[8];
tmp_30_reg_1640[9] <= tmp_30_fu_1257_p1[9];
tmp_30_reg_1640[10] <= tmp_30_fu_1257_p1[10];
tmp_30_reg_1640[11] <= tmp_30_fu_1257_p1[11];
tmp_30_reg_1640[12] <= tmp_30_fu_1257_p1[12];
tmp_30_reg_1640[13] <= tmp_30_fu_1257_p1[13];
end
if (((ap_ST_pp1_stg1_fsm_12 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond2_reg_1603))) begin
tmp_33_reg_1662[1] <= tmp_33_fu_1291_p1[1];
tmp_33_reg_1662[2] <= tmp_33_fu_1291_p1[2];
tmp_33_reg_1662[3] <= tmp_33_fu_1291_p1[3];
tmp_33_reg_1662[4] <= tmp_33_fu_1291_p1[4];
tmp_33_reg_1662[5] <= tmp_33_fu_1291_p1[5];
tmp_33_reg_1662[6] <= tmp_33_fu_1291_p1[6];
tmp_33_reg_1662[7] <= tmp_33_fu_1291_p1[7];
tmp_33_reg_1662[8] <= tmp_33_fu_1291_p1[8];
tmp_33_reg_1662[9] <= tmp_33_fu_1291_p1[9];
tmp_33_reg_1662[10] <= tmp_33_fu_1291_p1[10];
tmp_33_reg_1662[11] <= tmp_33_fu_1291_p1[11];
tmp_33_reg_1662[12] <= tmp_33_fu_1291_p1[12];
tmp_33_reg_1662[13] <= tmp_33_fu_1291_p1[13];
end
if (((ap_ST_pp1_stg1_fsm_12 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond2_reg_1603))) begin
tmp_36_reg_1679[0] <= tmp_36_fu_1311_p1[0];
tmp_36_reg_1679[1] <= tmp_36_fu_1311_p1[1];
tmp_36_reg_1679[2] <= tmp_36_fu_1311_p1[2];
tmp_36_reg_1679[3] <= tmp_36_fu_1311_p1[3];
tmp_36_reg_1679[4] <= tmp_36_fu_1311_p1[4];
tmp_36_reg_1679[5] <= tmp_36_fu_1311_p1[5];
tmp_36_reg_1679[6] <= tmp_36_fu_1311_p1[6];
tmp_36_reg_1679[7] <= tmp_36_fu_1311_p1[7];
tmp_36_reg_1679[8] <= tmp_36_fu_1311_p1[8];
tmp_36_reg_1679[9] <= tmp_36_fu_1311_p1[9];
tmp_36_reg_1679[10] <= tmp_36_fu_1311_p1[10];
tmp_36_reg_1679[11] <= tmp_36_fu_1311_p1[11];
tmp_36_reg_1679[12] <= tmp_36_fu_1311_p1[12];
tmp_36_reg_1679[13] <= tmp_36_fu_1311_p1[13];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond2_reg_1603) & (ap_ST_pp1_stg2_fsm_13 == ap_CS_fsm))) begin
tmp_39_reg_1706[2] <= tmp_39_fu_1331_p1[2];
tmp_39_reg_1706[3] <= tmp_39_fu_1331_p1[3];
tmp_39_reg_1706[4] <= tmp_39_fu_1331_p1[4];
tmp_39_reg_1706[5] <= tmp_39_fu_1331_p1[5];
tmp_39_reg_1706[6] <= tmp_39_fu_1331_p1[6];
tmp_39_reg_1706[7] <= tmp_39_fu_1331_p1[7];
tmp_39_reg_1706[8] <= tmp_39_fu_1331_p1[8];
tmp_39_reg_1706[9] <= tmp_39_fu_1331_p1[9];
tmp_39_reg_1706[10] <= tmp_39_fu_1331_p1[10];
tmp_39_reg_1706[11] <= tmp_39_fu_1331_p1[11];
tmp_39_reg_1706[12] <= tmp_39_fu_1331_p1[12];
tmp_39_reg_1706[13] <= tmp_39_fu_1331_p1[13];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond2_reg_1603) & (ap_ST_pp1_stg2_fsm_13 == ap_CS_fsm))) begin
tmp_42_reg_1723[0] <= tmp_42_fu_1351_p1[0];
tmp_42_reg_1723[1] <= tmp_42_fu_1351_p1[1];
tmp_42_reg_1723[2] <= tmp_42_fu_1351_p1[2];
tmp_42_reg_1723[3] <= tmp_42_fu_1351_p1[3];
tmp_42_reg_1723[4] <= tmp_42_fu_1351_p1[4];
tmp_42_reg_1723[5] <= tmp_42_fu_1351_p1[5];
tmp_42_reg_1723[6] <= tmp_42_fu_1351_p1[6];
tmp_42_reg_1723[7] <= tmp_42_fu_1351_p1[7];
tmp_42_reg_1723[8] <= tmp_42_fu_1351_p1[8];
tmp_42_reg_1723[9] <= tmp_42_fu_1351_p1[9];
tmp_42_reg_1723[10] <= tmp_42_fu_1351_p1[10];
tmp_42_reg_1723[11] <= tmp_42_fu_1351_p1[11];
tmp_42_reg_1723[12] <= tmp_42_fu_1351_p1[12];
tmp_42_reg_1723[13] <= tmp_42_fu_1351_p1[13];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond2_reg_1603) & (ap_ST_pp1_stg3_fsm_14 == ap_CS_fsm))) begin
tmp_45_reg_1750[1] <= tmp_45_fu_1371_p1[1];
tmp_45_reg_1750[2] <= tmp_45_fu_1371_p1[2];
tmp_45_reg_1750[3] <= tmp_45_fu_1371_p1[3];
tmp_45_reg_1750[4] <= tmp_45_fu_1371_p1[4];
tmp_45_reg_1750[5] <= tmp_45_fu_1371_p1[5];
tmp_45_reg_1750[6] <= tmp_45_fu_1371_p1[6];
tmp_45_reg_1750[7] <= tmp_45_fu_1371_p1[7];
tmp_45_reg_1750[8] <= tmp_45_fu_1371_p1[8];
tmp_45_reg_1750[9] <= tmp_45_fu_1371_p1[9];
tmp_45_reg_1750[10] <= tmp_45_fu_1371_p1[10];
tmp_45_reg_1750[11] <= tmp_45_fu_1371_p1[11];
tmp_45_reg_1750[12] <= tmp_45_fu_1371_p1[12];
tmp_45_reg_1750[13] <= tmp_45_fu_1371_p1[13];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond2_reg_1603) & (ap_ST_pp1_stg3_fsm_14 == ap_CS_fsm))) begin
tmp_48_reg_1767[0] <= tmp_48_fu_1391_p1[0];
tmp_48_reg_1767[1] <= tmp_48_fu_1391_p1[1];
tmp_48_reg_1767[2] <= tmp_48_fu_1391_p1[2];
tmp_48_reg_1767[3] <= tmp_48_fu_1391_p1[3];
tmp_48_reg_1767[4] <= tmp_48_fu_1391_p1[4];
tmp_48_reg_1767[5] <= tmp_48_fu_1391_p1[5];
tmp_48_reg_1767[6] <= tmp_48_fu_1391_p1[6];
tmp_48_reg_1767[7] <= tmp_48_fu_1391_p1[7];
tmp_48_reg_1767[8] <= tmp_48_fu_1391_p1[8];
tmp_48_reg_1767[9] <= tmp_48_fu_1391_p1[9];
tmp_48_reg_1767[10] <= tmp_48_fu_1391_p1[10];
tmp_48_reg_1767[11] <= tmp_48_fu_1391_p1[11];
tmp_48_reg_1767[12] <= tmp_48_fu_1391_p1[12];
tmp_48_reg_1767[13] <= tmp_48_fu_1391_p1[13];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond2_reg_1603) & (ap_ST_pp1_stg4_fsm_15 == ap_CS_fsm))) begin
tmp_51_reg_1804[3] <= tmp_51_fu_1416_p1[3];
tmp_51_reg_1804[4] <= tmp_51_fu_1416_p1[4];
tmp_51_reg_1804[5] <= tmp_51_fu_1416_p1[5];
tmp_51_reg_1804[6] <= tmp_51_fu_1416_p1[6];
tmp_51_reg_1804[7] <= tmp_51_fu_1416_p1[7];
tmp_51_reg_1804[8] <= tmp_51_fu_1416_p1[8];
tmp_51_reg_1804[9] <= tmp_51_fu_1416_p1[9];
tmp_51_reg_1804[10] <= tmp_51_fu_1416_p1[10];
tmp_51_reg_1804[11] <= tmp_51_fu_1416_p1[11];
tmp_51_reg_1804[12] <= tmp_51_fu_1416_p1[12];
tmp_51_reg_1804[13] <= tmp_51_fu_1416_p1[13];
end
if (((ap_ST_pp1_stg1_fsm_12 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it1))) begin
tmp_52_reg_1826 <= grp_fu_815_p2;
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it2) & (ap_ST_pp1_stg3_fsm_14 == ap_CS_fsm) & ~(ap_const_lv1_0 == or_cond_reg_1433) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it2))) begin
tmp_57_reg_1887 <= grp_fu_819_p2;
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it2) & (ap_ST_pp1_stg4_fsm_15 == ap_CS_fsm) & ~(ap_const_lv1_0 == or_cond_reg_1433) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it2))) begin
tmp_58_reg_1892 <= grp_fu_815_p2;
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it2) & (ap_ST_pp1_stg5_fsm_16 == ap_CS_fsm) & ~(ap_const_lv1_0 == or_cond_reg_1433) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it2))) begin
tmp_60_reg_1897 <= grp_fu_819_p2;
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond2_reg_1603) & (ap_ST_pp1_stg3_fsm_14 == ap_CS_fsm))) begin
tmp_61_reg_1789 <= (j1_mid2_reg_1612 + ap_const_lv7_8);
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond_fu_957_p2))) begin
tmp_6_reg_1483[0] <= tmp_6_fu_1021_p1[0];
tmp_6_reg_1483[1] <= tmp_6_fu_1021_p1[1];
tmp_6_reg_1483[2] <= tmp_6_fu_1021_p1[2];
tmp_6_reg_1483[3] <= tmp_6_fu_1021_p1[3];
tmp_6_reg_1483[4] <= tmp_6_fu_1021_p1[4];
tmp_6_reg_1483[5] <= tmp_6_fu_1021_p1[5];
tmp_6_reg_1483[6] <= tmp_6_fu_1021_p1[6];
tmp_6_reg_1483[7] <= tmp_6_fu_1021_p1[7];
tmp_6_reg_1483[8] <= tmp_6_fu_1021_p1[8];
tmp_6_reg_1483[9] <= tmp_6_fu_1021_p1[9];
tmp_6_reg_1483[10] <= tmp_6_fu_1021_p1[10];
tmp_6_reg_1483[11] <= tmp_6_fu_1021_p1[11];
tmp_6_reg_1483[12] <= tmp_6_fu_1021_p1[12];
tmp_6_reg_1483[13] <= tmp_6_fu_1021_p1[13];
end
if (((ap_ST_pp0_stg1_fsm_3 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_reg_1446 == ap_const_lv1_0))) begin
tmp_7_reg_1500[1] <= tmp_7_fu_1054_p1[1];
tmp_7_reg_1500[2] <= tmp_7_fu_1054_p1[2];
tmp_7_reg_1500[3] <= tmp_7_fu_1054_p1[3];
tmp_7_reg_1500[4] <= tmp_7_fu_1054_p1[4];
tmp_7_reg_1500[5] <= tmp_7_fu_1054_p1[5];
tmp_7_reg_1500[6] <= tmp_7_fu_1054_p1[6];
tmp_7_reg_1500[7] <= tmp_7_fu_1054_p1[7];
tmp_7_reg_1500[8] <= tmp_7_fu_1054_p1[8];
tmp_7_reg_1500[9] <= tmp_7_fu_1054_p1[9];
tmp_7_reg_1500[10] <= tmp_7_fu_1054_p1[10];
tmp_7_reg_1500[11] <= tmp_7_fu_1054_p1[11];
tmp_7_reg_1500[12] <= tmp_7_fu_1054_p1[12];
tmp_7_reg_1500[13] <= tmp_7_fu_1054_p1[13];
end
if (((ap_ST_pp0_stg1_fsm_3 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_reg_1446 == ap_const_lv1_0))) begin
tmp_9_reg_1512[0] <= tmp_9_fu_1073_p1[0];
tmp_9_reg_1512[1] <= tmp_9_fu_1073_p1[1];
tmp_9_reg_1512[2] <= tmp_9_fu_1073_p1[2];
tmp_9_reg_1512[3] <= tmp_9_fu_1073_p1[3];
tmp_9_reg_1512[4] <= tmp_9_fu_1073_p1[4];
tmp_9_reg_1512[5] <= tmp_9_fu_1073_p1[5];
tmp_9_reg_1512[6] <= tmp_9_fu_1073_p1[6];
tmp_9_reg_1512[7] <= tmp_9_fu_1073_p1[7];
tmp_9_reg_1512[8] <= tmp_9_fu_1073_p1[8];
tmp_9_reg_1512[9] <= tmp_9_fu_1073_p1[9];
tmp_9_reg_1512[10] <= tmp_9_fu_1073_p1[10];
tmp_9_reg_1512[11] <= tmp_9_fu_1073_p1[11];
tmp_9_reg_1512[12] <= tmp_9_fu_1073_p1[12];
tmp_9_reg_1512[13] <= tmp_9_fu_1073_p1[13];
end
end
/// ap_NS_fsm assign process. ///
always @ (ap_start or ap_CS_fsm or ap_reg_ppiten_pp0_it0 or ap_reg_ppiten_pp0_it1 or ap_reg_ppiten_pp1_it0 or ap_reg_ppiten_pp1_it1 or ap_reg_ppiten_pp1_it2 or ap_reg_ppiten_pp1_it3 or tmp_2_fu_951_p2 or exitcond_fu_957_p2 or or_cond1_fu_1187_p2 or exitcond2_fu_1193_p2)
begin
if ((ap_ST_pp1_stg6_fsm_17 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_pp1_stg7_fsm_18;
end else if ((ap_ST_pp1_stg5_fsm_16 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_pp1_stg6_fsm_17;
end else if ((ap_ST_pp1_stg4_fsm_15 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_pp1_stg5_fsm_16;
end else if ((ap_ST_pp1_stg3_fsm_14 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_pp1_stg4_fsm_15;
end else if ((ap_ST_pp1_stg2_fsm_13 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_pp1_stg3_fsm_14;
end else if (((ap_ST_pp1_stg1_fsm_12 == ap_CS_fsm) & ~((ap_ST_pp1_stg1_fsm_12 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it3) & ~(ap_const_logic_1 == ap_reg_ppiten_pp1_it2)))) begin
ap_NS_fsm = ap_ST_pp1_stg2_fsm_13;
end else if (((ap_ST_pp1_stg0_fsm_11 == ap_CS_fsm) & ~((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & ~(ap_const_lv1_0 == exitcond2_fu_1193_p2) & ~(ap_const_logic_1 == ap_reg_ppiten_pp1_it1)))) begin
ap_NS_fsm = ap_ST_pp1_stg1_fsm_12;
end else if (((ap_ST_pp0_stg6_fsm_8 == ap_CS_fsm) & ~((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (ap_ST_pp0_stg6_fsm_8 == ap_CS_fsm) & ~(ap_const_logic_1 == ap_reg_ppiten_pp0_it0)))) begin
ap_NS_fsm = ap_ST_pp0_stg7_fsm_9;
end else if ((ap_ST_pp0_stg5_fsm_7 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_pp0_stg6_fsm_8;
end else if ((ap_ST_pp0_stg4_fsm_6 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_pp0_stg5_fsm_7;
end else if ((ap_ST_pp0_stg3_fsm_5 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_pp0_stg4_fsm_6;
end else if ((ap_ST_pp0_stg2_fsm_4 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_pp0_stg3_fsm_5;
end else if ((ap_ST_pp0_stg1_fsm_3 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_pp0_stg2_fsm_4;
end else if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & ~((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ~(ap_const_lv1_0 == exitcond_fu_957_p2) & ~(ap_const_logic_1 == ap_reg_ppiten_pp0_it1)))) begin
ap_NS_fsm = ap_ST_pp0_stg1_fsm_3;
end else if ((~(ap_const_logic_1 == ap_start) & (ap_ST_st44_fsm_19 == ap_CS_fsm))) begin
ap_NS_fsm = ap_ST_st0_fsm_0;
end else if (((ap_ST_pp1_stg7_fsm_18 == ap_CS_fsm) | ((ap_ST_st17_fsm_10 == ap_CS_fsm) & ~(ap_const_lv1_0 == or_cond1_fu_1187_p2)))) begin
ap_NS_fsm = ap_ST_pp1_stg0_fsm_11;
end else if ((((ap_ST_st17_fsm_10 == ap_CS_fsm) & (ap_const_lv1_0 == or_cond1_fu_1187_p2)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_ST_pp1_stg0_fsm_11 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond2_fu_1193_p2) & ~(ap_const_logic_1 == ap_reg_ppiten_pp1_it1)) | ((ap_ST_pp1_stg1_fsm_12 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it3) & ~(ap_const_logic_1 == ap_reg_ppiten_pp1_it2)))) begin
ap_NS_fsm = ap_ST_st44_fsm_19;
end else if (((ap_ST_pp0_stg7_fsm_9 == ap_CS_fsm) | ((ap_ST_st1_fsm_1 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_2_fu_951_p2)))) begin
ap_NS_fsm = ap_ST_pp0_stg0_fsm_2;
end else if ((((ap_ST_st1_fsm_1 == ap_CS_fsm) & (ap_const_lv1_0 == tmp_2_fu_951_p2)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond_fu_957_p2) & ~(ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (ap_ST_pp0_stg6_fsm_8 == ap_CS_fsm) & ~(ap_const_logic_1 == ap_reg_ppiten_pp0_it0)))) begin
ap_NS_fsm = ap_ST_st17_fsm_10;
end else if ((((ap_ST_st0_fsm_0 == ap_CS_fsm) & (ap_const_logic_1 == ap_start)) | ((ap_const_logic_1 == ap_start) & (ap_ST_st44_fsm_19 == ap_CS_fsm)))) begin
ap_NS_fsm = ap_ST_st1_fsm_1;
end else begin
ap_NS_fsm = ap_CS_fsm;
end
end
/// ap_done assign process. ///
always @ (ap_CS_fsm)
begin
if (((ap_ST_st0_fsm_0 == ap_CS_fsm) | (ap_ST_st44_fsm_19 == ap_CS_fsm))) begin
ap_done = ap_const_logic_1;
end else begin
ap_done = ap_const_logic_0;
end
end
/// ap_idle assign process. ///
always @ (ap_CS_fsm)
begin
if ((ap_ST_st0_fsm_0 == ap_CS_fsm)) begin
ap_idle = ap_const_logic_1;
end else begin
ap_idle = ap_const_logic_0;
end
end
/// b_address0 assign process. ///
always @ (ap_CS_fsm or ap_reg_ppiten_pp0_it0 or exitcond_reg_1446 or ap_reg_ppiten_pp1_it0 or exitcond2_reg_1603 or exitcond_fu_957_p2 or tmp_6_fu_1021_p1 or tmp_7_fu_1054_p1 or tmp_11_fu_1092_p1 or tmp_15_fu_1130_p1 or tmp_19_fu_1173_p1 or exitcond2_fu_1193_p2 or tmp_30_fu_1257_p1 or tmp_33_fu_1291_p1 or tmp_39_fu_1331_p1 or tmp_45_fu_1371_p1 or tmp_51_fu_1416_p1)
begin
if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond2_reg_1603) & (ap_ST_pp1_stg4_fsm_15 == ap_CS_fsm))) begin
b_address0 = tmp_51_fu_1416_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond2_reg_1603) & (ap_ST_pp1_stg3_fsm_14 == ap_CS_fsm))) begin
b_address0 = tmp_45_fu_1371_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond2_reg_1603) & (ap_ST_pp1_stg2_fsm_13 == ap_CS_fsm))) begin
b_address0 = tmp_39_fu_1331_p1;
end else if (((ap_ST_pp1_stg1_fsm_12 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond2_reg_1603))) begin
b_address0 = tmp_33_fu_1291_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_ST_pp1_stg0_fsm_11 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond2_fu_1193_p2))) begin
b_address0 = tmp_30_fu_1257_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_reg_1446 == ap_const_lv1_0) & (ap_ST_pp0_stg4_fsm_6 == ap_CS_fsm))) begin
b_address0 = tmp_19_fu_1173_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_reg_1446 == ap_const_lv1_0) & (ap_ST_pp0_stg3_fsm_5 == ap_CS_fsm))) begin
b_address0 = tmp_15_fu_1130_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_reg_1446 == ap_const_lv1_0) & (ap_ST_pp0_stg2_fsm_4 == ap_CS_fsm))) begin
b_address0 = tmp_11_fu_1092_p1;
end else if (((ap_ST_pp0_stg1_fsm_3 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_reg_1446 == ap_const_lv1_0))) begin
b_address0 = tmp_7_fu_1054_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond_fu_957_p2))) begin
b_address0 = tmp_6_fu_1021_p1;
end else begin
b_address0 = tmp_51_fu_1416_p1;
end
end
/// b_address1 assign process. ///
always @ (ap_CS_fsm or ap_reg_ppiten_pp0_it0 or exitcond_reg_1446 or ap_reg_ppiten_pp1_it0 or exitcond2_reg_1603 or tmp_9_fu_1073_p1 or tmp_13_fu_1111_p1 or tmp_17_fu_1149_p1 or tmp_36_fu_1311_p1 or tmp_42_fu_1351_p1 or tmp_48_fu_1391_p1)
begin
if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond2_reg_1603) & (ap_ST_pp1_stg3_fsm_14 == ap_CS_fsm))) begin
b_address1 = tmp_48_fu_1391_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond2_reg_1603) & (ap_ST_pp1_stg2_fsm_13 == ap_CS_fsm))) begin
b_address1 = tmp_42_fu_1351_p1;
end else if (((ap_ST_pp1_stg1_fsm_12 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond2_reg_1603))) begin
b_address1 = tmp_36_fu_1311_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_reg_1446 == ap_const_lv1_0) & (ap_ST_pp0_stg3_fsm_5 == ap_CS_fsm))) begin
b_address1 = tmp_17_fu_1149_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_reg_1446 == ap_const_lv1_0) & (ap_ST_pp0_stg2_fsm_4 == ap_CS_fsm))) begin
b_address1 = tmp_13_fu_1111_p1;
end else if (((ap_ST_pp0_stg1_fsm_3 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_reg_1446 == ap_const_lv1_0))) begin
b_address1 = tmp_9_fu_1073_p1;
end else begin
b_address1 = tmp_48_fu_1391_p1;
end
end
/// b_ce0 assign process. ///
always @ (ap_CS_fsm or ap_reg_ppiten_pp0_it0 or exitcond_reg_1446 or ap_reg_ppiten_pp1_it0 or exitcond2_reg_1603 or exitcond_fu_957_p2 or exitcond2_fu_1193_p2)
begin
if ((((ap_ST_pp0_stg1_fsm_3 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_reg_1446 == ap_const_lv1_0)) | ((ap_ST_pp1_stg1_fsm_12 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond2_reg_1603)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_reg_1446 == ap_const_lv1_0) & (ap_ST_pp0_stg2_fsm_4 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond2_reg_1603) & (ap_ST_pp1_stg2_fsm_13 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_reg_1446 == ap_const_lv1_0) & (ap_ST_pp0_stg3_fsm_5 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond2_reg_1603) & (ap_ST_pp1_stg3_fsm_14 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_reg_1446 == ap_const_lv1_0) & (ap_ST_pp0_stg4_fsm_6 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond2_reg_1603) & (ap_ST_pp1_stg4_fsm_15 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond_fu_957_p2)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_ST_pp1_stg0_fsm_11 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond2_fu_1193_p2)))) begin
b_ce0 = ap_const_logic_1;
end else begin
b_ce0 = ap_const_logic_0;
end
end
/// b_ce1 assign process. ///
always @ (ap_CS_fsm or ap_reg_ppiten_pp0_it0 or exitcond_reg_1446 or ap_reg_ppiten_pp1_it0 or exitcond2_reg_1603)
begin
if ((((ap_ST_pp0_stg1_fsm_3 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_reg_1446 == ap_const_lv1_0)) | ((ap_ST_pp1_stg1_fsm_12 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond2_reg_1603)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_reg_1446 == ap_const_lv1_0) & (ap_ST_pp0_stg2_fsm_4 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond2_reg_1603) & (ap_ST_pp1_stg2_fsm_13 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_reg_1446 == ap_const_lv1_0) & (ap_ST_pp0_stg3_fsm_5 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond2_reg_1603) & (ap_ST_pp1_stg3_fsm_14 == ap_CS_fsm)))) begin
b_ce1 = ap_const_logic_1;
end else begin
b_ce1 = ap_const_logic_0;
end
end
/// c1_address0 assign process. ///
always @ (ap_CS_fsm or ap_reg_ppiten_pp0_it0 or ap_reg_ppiten_pp0_it1 or exitcond_reg_1446 or ap_reg_ppiten_pp1_it1 or ap_reg_ppiten_pp1_it2 or ap_reg_ppstg_exitcond_reg_1446_pp0_it1 or ap_reg_ppstg_exitcond2_reg_1603_pp1_it2 or tmp_6_reg_1483 or tmp_7_reg_1500 or tmp_11_reg_1524 or tmp_15_reg_1548 or tmp_19_reg_1582 or ap_reg_ppstg_exitcond2_reg_1603_pp1_it1 or ap_reg_ppstg_tmp_30_reg_1640_pp1_it1 or ap_reg_ppstg_tmp_33_reg_1662_pp1_it1 or ap_reg_ppstg_tmp_36_reg_1679_pp1_it1 or ap_reg_ppstg_tmp_39_reg_1706_pp1_it1 or ap_reg_ppstg_tmp_42_reg_1723_pp1_it1 or ap_reg_ppstg_tmp_45_reg_1750_pp1_it1 or ap_reg_ppstg_tmp_48_reg_1767_pp1_it1 or ap_reg_ppstg_tmp_51_reg_1804_pp1_it1)
begin
if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it2) & (ap_ST_pp1_stg2_fsm_13 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it2))) begin
c1_address0 = ap_reg_ppstg_tmp_51_reg_1804_pp1_it1;
end else if (((ap_ST_pp1_stg1_fsm_12 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it2) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it2))) begin
c1_address0 = ap_reg_ppstg_tmp_48_reg_1767_pp1_it1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it2) & (ap_ST_pp1_stg0_fsm_11 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it1))) begin
c1_address0 = ap_reg_ppstg_tmp_45_reg_1750_pp1_it1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_ST_pp1_stg7_fsm_18 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it1))) begin
c1_address0 = ap_reg_ppstg_tmp_42_reg_1723_pp1_it1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_ST_pp1_stg6_fsm_17 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it1))) begin
c1_address0 = ap_reg_ppstg_tmp_39_reg_1706_pp1_it1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_ST_pp1_stg5_fsm_16 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it1))) begin
c1_address0 = ap_reg_ppstg_tmp_36_reg_1679_pp1_it1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_ST_pp1_stg4_fsm_15 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it1))) begin
c1_address0 = ap_reg_ppstg_tmp_33_reg_1662_pp1_it1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_ST_pp1_stg3_fsm_14 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it1))) begin
c1_address0 = ap_reg_ppstg_tmp_30_reg_1640_pp1_it1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (ap_ST_pp0_stg2_fsm_4 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_1446_pp0_it1))) begin
c1_address0 = tmp_19_reg_1582;
end else if (((ap_ST_pp0_stg1_fsm_3 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_1446_pp0_it1))) begin
c1_address0 = tmp_15_reg_1548;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (exitcond_reg_1446 == ap_const_lv1_0) & (ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm))) begin
c1_address0 = tmp_11_reg_1524;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_reg_1446 == ap_const_lv1_0) & (ap_ST_pp0_stg7_fsm_9 == ap_CS_fsm))) begin
c1_address0 = tmp_7_reg_1500;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_reg_1446 == ap_const_lv1_0) & (ap_ST_pp0_stg6_fsm_8 == ap_CS_fsm))) begin
c1_address0 = tmp_6_reg_1483;
end else begin
c1_address0 = ap_reg_ppstg_tmp_51_reg_1804_pp1_it1;
end
end
/// c1_address1 assign process. ///
always @ (ap_CS_fsm or ap_reg_ppiten_pp0_it0 or ap_reg_ppiten_pp0_it1 or exitcond_reg_1446 or ap_reg_ppstg_exitcond_reg_1446_pp0_it1 or tmp_9_reg_1512 or tmp_13_reg_1536 or tmp_17_reg_1560)
begin
if (((ap_ST_pp0_stg1_fsm_3 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_1446_pp0_it1))) begin
c1_address1 = tmp_17_reg_1560;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (exitcond_reg_1446 == ap_const_lv1_0) & (ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm))) begin
c1_address1 = tmp_13_reg_1536;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_reg_1446 == ap_const_lv1_0) & (ap_ST_pp0_stg7_fsm_9 == ap_CS_fsm))) begin
c1_address1 = tmp_9_reg_1512;
end else begin
c1_address1 = tmp_17_reg_1560;
end
end
/// c1_ce0 assign process. ///
always @ (ap_CS_fsm or ap_reg_ppiten_pp0_it0 or ap_reg_ppiten_pp0_it1 or exitcond_reg_1446 or ap_reg_ppiten_pp1_it1 or ap_reg_ppiten_pp1_it2 or ap_reg_ppstg_exitcond_reg_1446_pp0_it1 or ap_reg_ppstg_exitcond2_reg_1603_pp1_it2 or ap_reg_ppstg_exitcond2_reg_1603_pp1_it1)
begin
if ((((ap_ST_pp0_stg1_fsm_3 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_1446_pp0_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_reg_1446 == ap_const_lv1_0) & (ap_ST_pp0_stg6_fsm_8 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_reg_1446 == ap_const_lv1_0) & (ap_ST_pp0_stg7_fsm_9 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (exitcond_reg_1446 == ap_const_lv1_0) & (ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_ST_pp1_stg3_fsm_14 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_ST_pp1_stg4_fsm_15 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_ST_pp1_stg5_fsm_16 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_ST_pp1_stg6_fsm_17 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_ST_pp1_stg7_fsm_18 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it2) & (ap_ST_pp1_stg0_fsm_11 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it1)) | ((ap_ST_pp1_stg1_fsm_12 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it2) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it2)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (ap_ST_pp0_stg2_fsm_4 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_1446_pp0_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it2) & (ap_ST_pp1_stg2_fsm_13 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it2)))) begin
c1_ce0 = ap_const_logic_1;
end else begin
c1_ce0 = ap_const_logic_0;
end
end
/// c1_ce1 assign process. ///
always @ (ap_CS_fsm or ap_reg_ppiten_pp0_it0 or ap_reg_ppiten_pp0_it1 or exitcond_reg_1446 or ap_reg_ppstg_exitcond_reg_1446_pp0_it1)
begin
if ((((ap_ST_pp0_stg1_fsm_3 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_1446_pp0_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_reg_1446 == ap_const_lv1_0) & (ap_ST_pp0_stg7_fsm_9 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (exitcond_reg_1446 == ap_const_lv1_0) & (ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)))) begin
c1_ce1 = ap_const_logic_1;
end else begin
c1_ce1 = ap_const_logic_0;
end
end
/// c1_d0 assign process. ///
always @ (ap_CS_fsm or ap_reg_ppiten_pp0_it0 or ap_reg_ppiten_pp0_it1 or exitcond_reg_1446 or ap_reg_ppiten_pp1_it1 or ap_reg_ppiten_pp1_it2 or reg_865 or ap_reg_ppstg_exitcond_reg_1446_pp0_it1 or ap_reg_ppstg_exitcond2_reg_1603_pp1_it2 or reg_874 or reg_890 or reg_906 or ap_reg_ppstg_exitcond2_reg_1603_pp1_it1 or t_reg_1831 or t8_reg_1838 or t9_reg_1845 or t10_reg_1852 or t11_reg_1859 or t12_reg_1866 or t13_reg_1873 or t14_reg_1880)
begin
if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it2) & (ap_ST_pp1_stg2_fsm_13 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it2))) begin
c1_d0 = t14_reg_1880;
end else if (((ap_ST_pp1_stg1_fsm_12 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it2) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it2))) begin
c1_d0 = t13_reg_1873;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it2) & (ap_ST_pp1_stg0_fsm_11 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it1))) begin
c1_d0 = t12_reg_1866;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_ST_pp1_stg7_fsm_18 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it1))) begin
c1_d0 = t11_reg_1859;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_ST_pp1_stg6_fsm_17 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it1))) begin
c1_d0 = t10_reg_1852;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_ST_pp1_stg5_fsm_16 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it1))) begin
c1_d0 = t9_reg_1845;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_ST_pp1_stg4_fsm_15 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it1))) begin
c1_d0 = t8_reg_1838;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_ST_pp1_stg3_fsm_14 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it1))) begin
c1_d0 = t_reg_1831;
end else if (((ap_ST_pp0_stg1_fsm_3 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_1446_pp0_it1))) begin
c1_d0 = reg_906;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (exitcond_reg_1446 == ap_const_lv1_0) & (ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm))) begin
c1_d0 = reg_890;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_reg_1446 == ap_const_lv1_0) & (ap_ST_pp0_stg7_fsm_9 == ap_CS_fsm))) begin
c1_d0 = reg_874;
end else if ((((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_reg_1446 == ap_const_lv1_0) & (ap_ST_pp0_stg6_fsm_8 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (ap_ST_pp0_stg2_fsm_4 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_1446_pp0_it1)))) begin
c1_d0 = reg_865;
end else begin
c1_d0 = t14_reg_1880;
end
end
/// c1_d1 assign process. ///
always @ (ap_CS_fsm or ap_reg_ppiten_pp0_it0 or ap_reg_ppiten_pp0_it1 or exitcond_reg_1446 or ap_reg_ppstg_exitcond_reg_1446_pp0_it1 or reg_882 or reg_898 or reg_914)
begin
if (((ap_ST_pp0_stg1_fsm_3 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_1446_pp0_it1))) begin
c1_d1 = reg_914;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (exitcond_reg_1446 == ap_const_lv1_0) & (ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm))) begin
c1_d1 = reg_898;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_reg_1446 == ap_const_lv1_0) & (ap_ST_pp0_stg7_fsm_9 == ap_CS_fsm))) begin
c1_d1 = reg_882;
end else begin
c1_d1 = reg_914;
end
end
/// c1_we0 assign process. ///
always @ (ap_CS_fsm or ap_reg_ppiten_pp0_it0 or ap_reg_ppiten_pp0_it1 or exitcond_reg_1446 or ap_reg_ppiten_pp1_it1 or ap_reg_ppiten_pp1_it2 or ap_reg_ppstg_exitcond_reg_1446_pp0_it1 or ap_reg_ppstg_exitcond2_reg_1603_pp1_it2 or ap_reg_ppstg_exitcond2_reg_1603_pp1_it1)
begin
if ((((ap_ST_pp0_stg1_fsm_3 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_1446_pp0_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_reg_1446 == ap_const_lv1_0) & (ap_ST_pp0_stg6_fsm_8 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_reg_1446 == ap_const_lv1_0) & (ap_ST_pp0_stg7_fsm_9 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (exitcond_reg_1446 == ap_const_lv1_0) & (ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_ST_pp1_stg3_fsm_14 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_ST_pp1_stg4_fsm_15 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_ST_pp1_stg5_fsm_16 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_ST_pp1_stg6_fsm_17 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_ST_pp1_stg7_fsm_18 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it2) & (ap_ST_pp1_stg0_fsm_11 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it1)) | ((ap_ST_pp1_stg1_fsm_12 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it2) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it2)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (ap_ST_pp0_stg2_fsm_4 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_1446_pp0_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it2) & (ap_ST_pp1_stg2_fsm_13 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it2)))) begin
c1_we0 = ap_const_logic_1;
end else begin
c1_we0 = ap_const_logic_0;
end
end
/// c1_we1 assign process. ///
always @ (ap_CS_fsm or ap_reg_ppiten_pp0_it0 or ap_reg_ppiten_pp0_it1 or exitcond_reg_1446 or ap_reg_ppstg_exitcond_reg_1446_pp0_it1)
begin
if ((((ap_ST_pp0_stg1_fsm_3 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_1446_pp0_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_reg_1446 == ap_const_lv1_0) & (ap_ST_pp0_stg7_fsm_9 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (exitcond_reg_1446 == ap_const_lv1_0) & (ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)))) begin
c1_we1 = ap_const_logic_1;
end else begin
c1_we1 = ap_const_logic_0;
end
end
/// c_address0 assign process. ///
always @ (ap_CS_fsm or ap_reg_ppiten_pp1_it0 or exitcond2_reg_1603 or exitcond2_fu_1193_p2 or tmp_30_fu_1257_p1 or tmp_33_fu_1291_p1 or tmp_39_fu_1331_p1 or tmp_45_fu_1371_p1 or tmp_51_fu_1416_p1)
begin
if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond2_reg_1603) & (ap_ST_pp1_stg4_fsm_15 == ap_CS_fsm))) begin
c_address0 = tmp_51_fu_1416_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond2_reg_1603) & (ap_ST_pp1_stg3_fsm_14 == ap_CS_fsm))) begin
c_address0 = tmp_45_fu_1371_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond2_reg_1603) & (ap_ST_pp1_stg2_fsm_13 == ap_CS_fsm))) begin
c_address0 = tmp_39_fu_1331_p1;
end else if (((ap_ST_pp1_stg1_fsm_12 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond2_reg_1603))) begin
c_address0 = tmp_33_fu_1291_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_ST_pp1_stg0_fsm_11 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond2_fu_1193_p2))) begin
c_address0 = tmp_30_fu_1257_p1;
end else begin
c_address0 = tmp_51_fu_1416_p1;
end
end
/// c_address1 assign process. ///
always @ (ap_CS_fsm or ap_reg_ppiten_pp1_it0 or exitcond2_reg_1603 or tmp_36_fu_1311_p1 or tmp_42_fu_1351_p1 or tmp_48_fu_1391_p1)
begin
if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond2_reg_1603) & (ap_ST_pp1_stg3_fsm_14 == ap_CS_fsm))) begin
c_address1 = tmp_48_fu_1391_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond2_reg_1603) & (ap_ST_pp1_stg2_fsm_13 == ap_CS_fsm))) begin
c_address1 = tmp_42_fu_1351_p1;
end else if (((ap_ST_pp1_stg1_fsm_12 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond2_reg_1603))) begin
c_address1 = tmp_36_fu_1311_p1;
end else begin
c_address1 = tmp_48_fu_1391_p1;
end
end
/// c_ce0 assign process. ///
always @ (ap_CS_fsm or ap_reg_ppiten_pp1_it0 or exitcond2_reg_1603 or exitcond2_fu_1193_p2)
begin
if ((((ap_ST_pp1_stg1_fsm_12 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond2_reg_1603)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond2_reg_1603) & (ap_ST_pp1_stg2_fsm_13 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond2_reg_1603) & (ap_ST_pp1_stg3_fsm_14 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond2_reg_1603) & (ap_ST_pp1_stg4_fsm_15 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_ST_pp1_stg0_fsm_11 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond2_fu_1193_p2)))) begin
c_ce0 = ap_const_logic_1;
end else begin
c_ce0 = ap_const_logic_0;
end
end
/// c_ce1 assign process. ///
always @ (ap_CS_fsm or ap_reg_ppiten_pp1_it0 or exitcond2_reg_1603)
begin
if ((((ap_ST_pp1_stg1_fsm_12 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond2_reg_1603)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond2_reg_1603) & (ap_ST_pp1_stg2_fsm_13 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond2_reg_1603) & (ap_ST_pp1_stg3_fsm_14 == ap_CS_fsm)))) begin
c_ce1 = ap_const_logic_1;
end else begin
c_ce1 = ap_const_logic_0;
end
end
/// d_address0 assign process. ///
always @ (ap_CS_fsm or ap_reg_ppiten_pp0_it0 or ap_reg_ppiten_pp0_it1 or exitcond_reg_1446 or ap_reg_ppiten_pp1_it1 or ap_reg_ppiten_pp1_it2 or ap_reg_ppstg_exitcond_reg_1446_pp0_it1 or or_cond_reg_1433 or ap_reg_ppstg_exitcond2_reg_1603_pp1_it2 or tmp_6_reg_1483 or ap_reg_ppstg_tmp_6_reg_1483_pp0_it1 or tmp_7_reg_1500 or ap_reg_ppstg_tmp_7_reg_1500_pp0_it1 or tmp_11_reg_1524 or ap_reg_ppstg_tmp_11_reg_1524_pp0_it1 or tmp_15_reg_1548 or ap_reg_ppstg_tmp_15_reg_1548_pp0_it1 or tmp_19_reg_1582 or ap_reg_ppstg_exitcond2_reg_1603_pp1_it1 or ap_reg_ppstg_tmp_30_reg_1640_pp1_it1 or ap_reg_ppstg_tmp_30_reg_1640_pp1_it2 or ap_reg_ppstg_tmp_33_reg_1662_pp1_it1 or ap_reg_ppstg_tmp_36_reg_1679_pp1_it1 or ap_reg_ppstg_tmp_39_reg_1706_pp1_it1 or ap_reg_ppstg_tmp_42_reg_1723_pp1_it1 or ap_reg_ppstg_tmp_45_reg_1750_pp1_it1 or ap_reg_ppstg_tmp_48_reg_1767_pp1_it1 or ap_reg_ppstg_tmp_51_reg_1804_pp1_it1)
begin
if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it2) & (ap_ST_pp1_stg2_fsm_13 == ap_CS_fsm) & ~(ap_const_lv1_0 == or_cond_reg_1433) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it2))) begin
d_address0 = ap_reg_ppstg_tmp_30_reg_1640_pp1_it2;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it2) & (ap_ST_pp1_stg2_fsm_13 == ap_CS_fsm) & (ap_const_lv1_0 == or_cond_reg_1433) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it2))) begin
d_address0 = ap_reg_ppstg_tmp_51_reg_1804_pp1_it1;
end else if (((ap_ST_pp1_stg1_fsm_12 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it2) & (ap_const_lv1_0 == or_cond_reg_1433) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it2))) begin
d_address0 = ap_reg_ppstg_tmp_48_reg_1767_pp1_it1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it2) & (ap_const_lv1_0 == or_cond_reg_1433) & (ap_ST_pp1_stg0_fsm_11 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it1))) begin
d_address0 = ap_reg_ppstg_tmp_45_reg_1750_pp1_it1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_const_lv1_0 == or_cond_reg_1433) & (ap_ST_pp1_stg7_fsm_18 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it1))) begin
d_address0 = ap_reg_ppstg_tmp_42_reg_1723_pp1_it1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_const_lv1_0 == or_cond_reg_1433) & (ap_ST_pp1_stg6_fsm_17 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it1))) begin
d_address0 = ap_reg_ppstg_tmp_39_reg_1706_pp1_it1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_ST_pp1_stg5_fsm_16 == ap_CS_fsm) & (ap_const_lv1_0 == or_cond_reg_1433) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it1))) begin
d_address0 = ap_reg_ppstg_tmp_36_reg_1679_pp1_it1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_ST_pp1_stg4_fsm_15 == ap_CS_fsm) & (ap_const_lv1_0 == or_cond_reg_1433) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it1))) begin
d_address0 = ap_reg_ppstg_tmp_33_reg_1662_pp1_it1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_ST_pp1_stg3_fsm_14 == ap_CS_fsm) & (ap_const_lv1_0 == or_cond_reg_1433) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it1))) begin
d_address0 = ap_reg_ppstg_tmp_30_reg_1640_pp1_it1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (ap_ST_pp0_stg5_fsm_7 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_1446_pp0_it1) & ~(ap_const_lv1_0 == or_cond_reg_1433))) begin
d_address0 = ap_reg_ppstg_tmp_15_reg_1548_pp0_it1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (ap_ST_pp0_stg4_fsm_6 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_1446_pp0_it1) & ~(ap_const_lv1_0 == or_cond_reg_1433))) begin
d_address0 = ap_reg_ppstg_tmp_11_reg_1524_pp0_it1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (ap_ST_pp0_stg3_fsm_5 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_1446_pp0_it1) & ~(ap_const_lv1_0 == or_cond_reg_1433))) begin
d_address0 = ap_reg_ppstg_tmp_7_reg_1500_pp0_it1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (ap_ST_pp0_stg2_fsm_4 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_1446_pp0_it1) & ~(ap_const_lv1_0 == or_cond_reg_1433))) begin
d_address0 = ap_reg_ppstg_tmp_6_reg_1483_pp0_it1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (ap_ST_pp0_stg2_fsm_4 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_1446_pp0_it1) & (ap_const_lv1_0 == or_cond_reg_1433))) begin
d_address0 = tmp_19_reg_1582;
end else if (((ap_ST_pp0_stg1_fsm_3 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_1446_pp0_it1) & (ap_const_lv1_0 == or_cond_reg_1433))) begin
d_address0 = tmp_15_reg_1548;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (exitcond_reg_1446 == ap_const_lv1_0) & (ap_const_lv1_0 == or_cond_reg_1433) & (ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm))) begin
d_address0 = tmp_11_reg_1524;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_reg_1446 == ap_const_lv1_0) & (ap_const_lv1_0 == or_cond_reg_1433) & (ap_ST_pp0_stg7_fsm_9 == ap_CS_fsm))) begin
d_address0 = tmp_7_reg_1500;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_reg_1446 == ap_const_lv1_0) & (ap_const_lv1_0 == or_cond_reg_1433) & (ap_ST_pp0_stg6_fsm_8 == ap_CS_fsm))) begin
d_address0 = tmp_6_reg_1483;
end else begin
d_address0 = ap_reg_ppstg_tmp_30_reg_1640_pp1_it2;
end
end
/// d_address1 assign process. ///
always @ (ap_CS_fsm or ap_reg_ppiten_pp0_it0 or ap_reg_ppiten_pp0_it1 or exitcond_reg_1446 or ap_reg_ppiten_pp1_it2 or ap_reg_ppiten_pp1_it3 or ap_reg_ppstg_exitcond_reg_1446_pp0_it1 or or_cond_reg_1433 or ap_reg_ppstg_exitcond2_reg_1603_pp1_it2 or tmp_9_reg_1512 or ap_reg_ppstg_tmp_9_reg_1512_pp0_it1 or tmp_13_reg_1536 or ap_reg_ppstg_tmp_13_reg_1536_pp0_it1 or tmp_17_reg_1560 or ap_reg_ppstg_tmp_17_reg_1560_pp0_it1 or ap_reg_ppstg_tmp_19_reg_1582_pp0_it1 or ap_reg_ppstg_exitcond2_reg_1603_pp1_it3 or ap_reg_ppstg_tmp_33_reg_1662_pp1_it2 or ap_reg_ppstg_tmp_36_reg_1679_pp1_it2 or ap_reg_ppstg_tmp_39_reg_1706_pp1_it2 or ap_reg_ppstg_tmp_42_reg_1723_pp1_it2 or ap_reg_ppstg_tmp_45_reg_1750_pp1_it2 or ap_reg_ppstg_tmp_48_reg_1767_pp1_it2 or ap_reg_ppstg_tmp_51_reg_1804_pp1_it2)
begin
if (((ap_ST_pp1_stg1_fsm_12 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it3) & ~(ap_const_lv1_0 == or_cond_reg_1433) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it3))) begin
d_address1 = ap_reg_ppstg_tmp_51_reg_1804_pp1_it2;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it3) & ~(ap_const_lv1_0 == or_cond_reg_1433) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it2) & (ap_ST_pp1_stg0_fsm_11 == ap_CS_fsm))) begin
d_address1 = ap_reg_ppstg_tmp_48_reg_1767_pp1_it2;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it2) & ~(ap_const_lv1_0 == or_cond_reg_1433) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it2) & (ap_ST_pp1_stg7_fsm_18 == ap_CS_fsm))) begin
d_address1 = ap_reg_ppstg_tmp_45_reg_1750_pp1_it2;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it2) & ~(ap_const_lv1_0 == or_cond_reg_1433) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it2) & (ap_ST_pp1_stg6_fsm_17 == ap_CS_fsm))) begin
d_address1 = ap_reg_ppstg_tmp_42_reg_1723_pp1_it2;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it2) & (ap_ST_pp1_stg5_fsm_16 == ap_CS_fsm) & ~(ap_const_lv1_0 == or_cond_reg_1433) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it2))) begin
d_address1 = ap_reg_ppstg_tmp_39_reg_1706_pp1_it2;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it2) & (ap_ST_pp1_stg4_fsm_15 == ap_CS_fsm) & ~(ap_const_lv1_0 == or_cond_reg_1433) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it2))) begin
d_address1 = ap_reg_ppstg_tmp_36_reg_1679_pp1_it2;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it2) & (ap_ST_pp1_stg3_fsm_14 == ap_CS_fsm) & ~(ap_const_lv1_0 == or_cond_reg_1433) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it2))) begin
d_address1 = ap_reg_ppstg_tmp_33_reg_1662_pp1_it2;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_1446_pp0_it1) & ~(ap_const_lv1_0 == or_cond_reg_1433) & (ap_ST_pp0_stg6_fsm_8 == ap_CS_fsm))) begin
d_address1 = ap_reg_ppstg_tmp_19_reg_1582_pp0_it1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (ap_ST_pp0_stg5_fsm_7 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_1446_pp0_it1) & ~(ap_const_lv1_0 == or_cond_reg_1433))) begin
d_address1 = ap_reg_ppstg_tmp_17_reg_1560_pp0_it1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (ap_ST_pp0_stg4_fsm_6 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_1446_pp0_it1) & ~(ap_const_lv1_0 == or_cond_reg_1433))) begin
d_address1 = ap_reg_ppstg_tmp_13_reg_1536_pp0_it1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (ap_ST_pp0_stg3_fsm_5 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_1446_pp0_it1) & ~(ap_const_lv1_0 == or_cond_reg_1433))) begin
d_address1 = ap_reg_ppstg_tmp_9_reg_1512_pp0_it1;
end else if (((ap_ST_pp0_stg1_fsm_3 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_1446_pp0_it1) & (ap_const_lv1_0 == or_cond_reg_1433))) begin
d_address1 = tmp_17_reg_1560;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (exitcond_reg_1446 == ap_const_lv1_0) & (ap_const_lv1_0 == or_cond_reg_1433) & (ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm))) begin
d_address1 = tmp_13_reg_1536;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_reg_1446 == ap_const_lv1_0) & (ap_const_lv1_0 == or_cond_reg_1433) & (ap_ST_pp0_stg7_fsm_9 == ap_CS_fsm))) begin
d_address1 = tmp_9_reg_1512;
end else begin
d_address1 = ap_reg_ppstg_tmp_51_reg_1804_pp1_it2;
end
end
/// d_ce0 assign process. ///
always @ (ap_CS_fsm or ap_reg_ppiten_pp0_it0 or ap_reg_ppiten_pp0_it1 or exitcond_reg_1446 or ap_reg_ppiten_pp1_it1 or ap_reg_ppiten_pp1_it2 or ap_reg_ppstg_exitcond_reg_1446_pp0_it1 or or_cond_reg_1433 or ap_reg_ppstg_exitcond2_reg_1603_pp1_it2 or ap_reg_ppstg_exitcond2_reg_1603_pp1_it1)
begin
if ((((ap_const_logic_1 == ap_reg_ppiten_pp1_it2) & (ap_ST_pp1_stg2_fsm_13 == ap_CS_fsm) & ~(ap_const_lv1_0 == or_cond_reg_1433) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it2)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (ap_ST_pp0_stg2_fsm_4 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_1446_pp0_it1) & ~(ap_const_lv1_0 == or_cond_reg_1433)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (ap_ST_pp0_stg3_fsm_5 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_1446_pp0_it1) & ~(ap_const_lv1_0 == or_cond_reg_1433)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (ap_ST_pp0_stg4_fsm_6 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_1446_pp0_it1) & ~(ap_const_lv1_0 == or_cond_reg_1433)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (ap_ST_pp0_stg5_fsm_7 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_1446_pp0_it1) & ~(ap_const_lv1_0 == or_cond_reg_1433)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_reg_1446 == ap_const_lv1_0) & (ap_const_lv1_0 == or_cond_reg_1433) & (ap_ST_pp0_stg6_fsm_8 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_reg_1446 == ap_const_lv1_0) & (ap_const_lv1_0 == or_cond_reg_1433) & (ap_ST_pp0_stg7_fsm_9 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (exitcond_reg_1446 == ap_const_lv1_0) & (ap_const_lv1_0 == or_cond_reg_1433) & (ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) | ((ap_ST_pp0_stg1_fsm_3 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_1446_pp0_it1) & (ap_const_lv1_0 == or_cond_reg_1433)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (ap_ST_pp0_stg2_fsm_4 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_1446_pp0_it1) & (ap_const_lv1_0 == or_cond_reg_1433)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_ST_pp1_stg3_fsm_14 == ap_CS_fsm) & (ap_const_lv1_0 == or_cond_reg_1433) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_ST_pp1_stg4_fsm_15 == ap_CS_fsm) & (ap_const_lv1_0 == or_cond_reg_1433) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_ST_pp1_stg5_fsm_16 == ap_CS_fsm) & (ap_const_lv1_0 == or_cond_reg_1433) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_const_lv1_0 == or_cond_reg_1433) & (ap_ST_pp1_stg6_fsm_17 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_const_lv1_0 == or_cond_reg_1433) & (ap_ST_pp1_stg7_fsm_18 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it2) & (ap_const_lv1_0 == or_cond_reg_1433) & (ap_ST_pp1_stg0_fsm_11 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it1)) | ((ap_ST_pp1_stg1_fsm_12 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it2) & (ap_const_lv1_0 == or_cond_reg_1433) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it2)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it2) & (ap_ST_pp1_stg2_fsm_13 == ap_CS_fsm) & (ap_const_lv1_0 == or_cond_reg_1433) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it2)))) begin
d_ce0 = ap_const_logic_1;
end else begin
d_ce0 = ap_const_logic_0;
end
end
/// d_ce1 assign process. ///
always @ (ap_CS_fsm or ap_reg_ppiten_pp0_it0 or ap_reg_ppiten_pp0_it1 or exitcond_reg_1446 or ap_reg_ppiten_pp1_it2 or ap_reg_ppiten_pp1_it3 or ap_reg_ppstg_exitcond_reg_1446_pp0_it1 or or_cond_reg_1433 or ap_reg_ppstg_exitcond2_reg_1603_pp1_it2 or ap_reg_ppstg_exitcond2_reg_1603_pp1_it3)
begin
if ((((ap_const_logic_1 == ap_reg_ppiten_pp1_it2) & (ap_ST_pp1_stg3_fsm_14 == ap_CS_fsm) & ~(ap_const_lv1_0 == or_cond_reg_1433) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it2)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (ap_ST_pp0_stg3_fsm_5 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_1446_pp0_it1) & ~(ap_const_lv1_0 == or_cond_reg_1433)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (ap_ST_pp0_stg4_fsm_6 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_1446_pp0_it1) & ~(ap_const_lv1_0 == or_cond_reg_1433)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (ap_ST_pp0_stg5_fsm_7 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_1446_pp0_it1) & ~(ap_const_lv1_0 == or_cond_reg_1433)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it2) & (ap_ST_pp1_stg4_fsm_15 == ap_CS_fsm) & ~(ap_const_lv1_0 == or_cond_reg_1433) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it2)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it2) & (ap_ST_pp1_stg5_fsm_16 == ap_CS_fsm) & ~(ap_const_lv1_0 == or_cond_reg_1433) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it2)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_reg_1446 == ap_const_lv1_0) & (ap_const_lv1_0 == or_cond_reg_1433) & (ap_ST_pp0_stg7_fsm_9 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (exitcond_reg_1446 == ap_const_lv1_0) & (ap_const_lv1_0 == or_cond_reg_1433) & (ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) | ((ap_ST_pp0_stg1_fsm_3 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_1446_pp0_it1) & (ap_const_lv1_0 == or_cond_reg_1433)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_1446_pp0_it1) & ~(ap_const_lv1_0 == or_cond_reg_1433) & (ap_ST_pp0_stg6_fsm_8 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it2) & ~(ap_const_lv1_0 == or_cond_reg_1433) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it2) & (ap_ST_pp1_stg6_fsm_17 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it2) & ~(ap_const_lv1_0 == or_cond_reg_1433) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it2) & (ap_ST_pp1_stg7_fsm_18 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it3) & ~(ap_const_lv1_0 == or_cond_reg_1433) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it2) & (ap_ST_pp1_stg0_fsm_11 == ap_CS_fsm)) | ((ap_ST_pp1_stg1_fsm_12 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it3) & ~(ap_const_lv1_0 == or_cond_reg_1433) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it3)))) begin
d_ce1 = ap_const_logic_1;
end else begin
d_ce1 = ap_const_logic_0;
end
end
/// d_d0 assign process. ///
always @ (ap_CS_fsm or ap_reg_ppiten_pp0_it0 or ap_reg_ppiten_pp0_it1 or exitcond_reg_1446 or ap_reg_ppiten_pp1_it1 or ap_reg_ppiten_pp1_it2 or reg_865 or ap_reg_ppstg_exitcond_reg_1446_pp0_it1 or or_cond_reg_1433 or ap_reg_ppstg_exitcond2_reg_1603_pp1_it2 or reg_874 or reg_890 or reg_906 or reg_922 or ap_reg_ppstg_exitcond2_reg_1603_pp1_it1 or t_reg_1831 or t8_reg_1838 or t9_reg_1845 or t10_reg_1852 or t11_reg_1859 or t12_reg_1866 or t13_reg_1873 or t14_reg_1880)
begin
if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it2) & (ap_ST_pp1_stg2_fsm_13 == ap_CS_fsm) & (ap_const_lv1_0 == or_cond_reg_1433) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it2))) begin
d_d0 = t14_reg_1880;
end else if (((ap_ST_pp1_stg1_fsm_12 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it2) & (ap_const_lv1_0 == or_cond_reg_1433) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it2))) begin
d_d0 = t13_reg_1873;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it2) & (ap_const_lv1_0 == or_cond_reg_1433) & (ap_ST_pp1_stg0_fsm_11 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it1))) begin
d_d0 = t12_reg_1866;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_const_lv1_0 == or_cond_reg_1433) & (ap_ST_pp1_stg7_fsm_18 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it1))) begin
d_d0 = t11_reg_1859;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_const_lv1_0 == or_cond_reg_1433) & (ap_ST_pp1_stg6_fsm_17 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it1))) begin
d_d0 = t10_reg_1852;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_ST_pp1_stg5_fsm_16 == ap_CS_fsm) & (ap_const_lv1_0 == or_cond_reg_1433) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it1))) begin
d_d0 = t9_reg_1845;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_ST_pp1_stg4_fsm_15 == ap_CS_fsm) & (ap_const_lv1_0 == or_cond_reg_1433) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it1))) begin
d_d0 = t8_reg_1838;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_ST_pp1_stg3_fsm_14 == ap_CS_fsm) & (ap_const_lv1_0 == or_cond_reg_1433) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it1))) begin
d_d0 = t_reg_1831;
end else if ((((ap_const_logic_1 == ap_reg_ppiten_pp1_it2) & (ap_ST_pp1_stg2_fsm_13 == ap_CS_fsm) & ~(ap_const_lv1_0 == or_cond_reg_1433) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it2)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (ap_ST_pp0_stg2_fsm_4 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_1446_pp0_it1) & ~(ap_const_lv1_0 == or_cond_reg_1433)))) begin
d_d0 = reg_922;
end else if (((ap_ST_pp0_stg1_fsm_3 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_1446_pp0_it1) & (ap_const_lv1_0 == or_cond_reg_1433))) begin
d_d0 = reg_906;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (exitcond_reg_1446 == ap_const_lv1_0) & (ap_const_lv1_0 == or_cond_reg_1433) & (ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm))) begin
d_d0 = reg_890;
end else if ((((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (ap_ST_pp0_stg3_fsm_5 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_1446_pp0_it1) & ~(ap_const_lv1_0 == or_cond_reg_1433)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (ap_ST_pp0_stg4_fsm_6 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_1446_pp0_it1) & ~(ap_const_lv1_0 == or_cond_reg_1433)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (ap_ST_pp0_stg5_fsm_7 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_1446_pp0_it1) & ~(ap_const_lv1_0 == or_cond_reg_1433)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_reg_1446 == ap_const_lv1_0) & (ap_const_lv1_0 == or_cond_reg_1433) & (ap_ST_pp0_stg7_fsm_9 == ap_CS_fsm)))) begin
d_d0 = reg_874;
end else if ((((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_reg_1446 == ap_const_lv1_0) & (ap_const_lv1_0 == or_cond_reg_1433) & (ap_ST_pp0_stg6_fsm_8 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (ap_ST_pp0_stg2_fsm_4 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_1446_pp0_it1) & (ap_const_lv1_0 == or_cond_reg_1433)))) begin
d_d0 = reg_865;
end else begin
d_d0 = t14_reg_1880;
end
end
/// d_d1 assign process. ///
always @ (ap_CS_fsm or ap_reg_ppiten_pp0_it0 or ap_reg_ppiten_pp0_it1 or exitcond_reg_1446 or ap_reg_ppiten_pp1_it2 or ap_reg_ppiten_pp1_it3 or reg_865 or ap_reg_ppstg_exitcond_reg_1446_pp0_it1 or or_cond_reg_1433 or ap_reg_ppstg_exitcond2_reg_1603_pp1_it2 or reg_882 or reg_898 or reg_914 or reg_922 or ap_reg_ppstg_exitcond2_reg_1603_pp1_it3 or tmp_57_reg_1887 or tmp_58_reg_1892 or tmp_60_reg_1897)
begin
if (((ap_ST_pp1_stg1_fsm_12 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it3) & ~(ap_const_lv1_0 == or_cond_reg_1433) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it3))) begin
d_d1 = tmp_60_reg_1897;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it2) & ~(ap_const_lv1_0 == or_cond_reg_1433) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it2) & (ap_ST_pp1_stg7_fsm_18 == ap_CS_fsm))) begin
d_d1 = tmp_58_reg_1892;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it2) & ~(ap_const_lv1_0 == or_cond_reg_1433) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it2) & (ap_ST_pp1_stg6_fsm_17 == ap_CS_fsm))) begin
d_d1 = tmp_57_reg_1887;
end else if ((((ap_const_logic_1 == ap_reg_ppiten_pp1_it2) & (ap_ST_pp1_stg4_fsm_15 == ap_CS_fsm) & ~(ap_const_lv1_0 == or_cond_reg_1433) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it2)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it3) & ~(ap_const_lv1_0 == or_cond_reg_1433) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it2) & (ap_ST_pp1_stg0_fsm_11 == ap_CS_fsm)))) begin
d_d1 = reg_922;
end else if ((((ap_const_logic_1 == ap_reg_ppiten_pp1_it2) & (ap_ST_pp1_stg3_fsm_14 == ap_CS_fsm) & ~(ap_const_lv1_0 == or_cond_reg_1433) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it2)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it2) & (ap_ST_pp1_stg5_fsm_16 == ap_CS_fsm) & ~(ap_const_lv1_0 == or_cond_reg_1433) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it2)))) begin
d_d1 = reg_865;
end else if (((ap_ST_pp0_stg1_fsm_3 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_1446_pp0_it1) & (ap_const_lv1_0 == or_cond_reg_1433))) begin
d_d1 = reg_914;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (exitcond_reg_1446 == ap_const_lv1_0) & (ap_const_lv1_0 == or_cond_reg_1433) & (ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm))) begin
d_d1 = reg_898;
end else if ((((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (ap_ST_pp0_stg3_fsm_5 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_1446_pp0_it1) & ~(ap_const_lv1_0 == or_cond_reg_1433)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (ap_ST_pp0_stg4_fsm_6 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_1446_pp0_it1) & ~(ap_const_lv1_0 == or_cond_reg_1433)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (ap_ST_pp0_stg5_fsm_7 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_1446_pp0_it1) & ~(ap_const_lv1_0 == or_cond_reg_1433)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_reg_1446 == ap_const_lv1_0) & (ap_const_lv1_0 == or_cond_reg_1433) & (ap_ST_pp0_stg7_fsm_9 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_1446_pp0_it1) & ~(ap_const_lv1_0 == or_cond_reg_1433) & (ap_ST_pp0_stg6_fsm_8 == ap_CS_fsm)))) begin
d_d1 = reg_882;
end else begin
d_d1 = tmp_60_reg_1897;
end
end
/// d_we0 assign process. ///
always @ (ap_CS_fsm or ap_reg_ppiten_pp0_it0 or ap_reg_ppiten_pp0_it1 or exitcond_reg_1446 or ap_reg_ppiten_pp1_it1 or ap_reg_ppiten_pp1_it2 or ap_reg_ppstg_exitcond_reg_1446_pp0_it1 or or_cond_reg_1433 or ap_reg_ppstg_exitcond2_reg_1603_pp1_it2 or ap_reg_ppstg_exitcond2_reg_1603_pp1_it1)
begin
if ((((ap_const_logic_1 == ap_reg_ppiten_pp1_it2) & (ap_ST_pp1_stg2_fsm_13 == ap_CS_fsm) & ~(ap_const_lv1_0 == or_cond_reg_1433) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it2)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (ap_ST_pp0_stg2_fsm_4 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_1446_pp0_it1) & ~(ap_const_lv1_0 == or_cond_reg_1433)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (ap_ST_pp0_stg3_fsm_5 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_1446_pp0_it1) & ~(ap_const_lv1_0 == or_cond_reg_1433)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (ap_ST_pp0_stg4_fsm_6 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_1446_pp0_it1) & ~(ap_const_lv1_0 == or_cond_reg_1433)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (ap_ST_pp0_stg5_fsm_7 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_1446_pp0_it1) & ~(ap_const_lv1_0 == or_cond_reg_1433)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_reg_1446 == ap_const_lv1_0) & (ap_const_lv1_0 == or_cond_reg_1433) & (ap_ST_pp0_stg6_fsm_8 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_reg_1446 == ap_const_lv1_0) & (ap_const_lv1_0 == or_cond_reg_1433) & (ap_ST_pp0_stg7_fsm_9 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (exitcond_reg_1446 == ap_const_lv1_0) & (ap_const_lv1_0 == or_cond_reg_1433) & (ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) | ((ap_ST_pp0_stg1_fsm_3 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_1446_pp0_it1) & (ap_const_lv1_0 == or_cond_reg_1433)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (ap_ST_pp0_stg2_fsm_4 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_1446_pp0_it1) & (ap_const_lv1_0 == or_cond_reg_1433)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_ST_pp1_stg3_fsm_14 == ap_CS_fsm) & (ap_const_lv1_0 == or_cond_reg_1433) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_ST_pp1_stg4_fsm_15 == ap_CS_fsm) & (ap_const_lv1_0 == or_cond_reg_1433) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_ST_pp1_stg5_fsm_16 == ap_CS_fsm) & (ap_const_lv1_0 == or_cond_reg_1433) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_const_lv1_0 == or_cond_reg_1433) & (ap_ST_pp1_stg6_fsm_17 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_const_lv1_0 == or_cond_reg_1433) & (ap_ST_pp1_stg7_fsm_18 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it2) & (ap_const_lv1_0 == or_cond_reg_1433) & (ap_ST_pp1_stg0_fsm_11 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it1)) | ((ap_ST_pp1_stg1_fsm_12 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it2) & (ap_const_lv1_0 == or_cond_reg_1433) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it2)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it2) & (ap_ST_pp1_stg2_fsm_13 == ap_CS_fsm) & (ap_const_lv1_0 == or_cond_reg_1433) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it2)))) begin
d_we0 = ap_const_logic_1;
end else begin
d_we0 = ap_const_logic_0;
end
end
/// d_we1 assign process. ///
always @ (ap_CS_fsm or ap_reg_ppiten_pp0_it0 or ap_reg_ppiten_pp0_it1 or exitcond_reg_1446 or ap_reg_ppiten_pp1_it2 or ap_reg_ppiten_pp1_it3 or ap_reg_ppstg_exitcond_reg_1446_pp0_it1 or or_cond_reg_1433 or ap_reg_ppstg_exitcond2_reg_1603_pp1_it2 or ap_reg_ppstg_exitcond2_reg_1603_pp1_it3)
begin
if ((((ap_const_logic_1 == ap_reg_ppiten_pp1_it2) & (ap_ST_pp1_stg3_fsm_14 == ap_CS_fsm) & ~(ap_const_lv1_0 == or_cond_reg_1433) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it2)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (ap_ST_pp0_stg3_fsm_5 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_1446_pp0_it1) & ~(ap_const_lv1_0 == or_cond_reg_1433)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (ap_ST_pp0_stg4_fsm_6 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_1446_pp0_it1) & ~(ap_const_lv1_0 == or_cond_reg_1433)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (ap_ST_pp0_stg5_fsm_7 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_1446_pp0_it1) & ~(ap_const_lv1_0 == or_cond_reg_1433)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it2) & (ap_ST_pp1_stg4_fsm_15 == ap_CS_fsm) & ~(ap_const_lv1_0 == or_cond_reg_1433) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it2)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it2) & (ap_ST_pp1_stg5_fsm_16 == ap_CS_fsm) & ~(ap_const_lv1_0 == or_cond_reg_1433) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it2)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_reg_1446 == ap_const_lv1_0) & (ap_const_lv1_0 == or_cond_reg_1433) & (ap_ST_pp0_stg7_fsm_9 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (exitcond_reg_1446 == ap_const_lv1_0) & (ap_const_lv1_0 == or_cond_reg_1433) & (ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) | ((ap_ST_pp0_stg1_fsm_3 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_1446_pp0_it1) & (ap_const_lv1_0 == or_cond_reg_1433)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_1446_pp0_it1) & ~(ap_const_lv1_0 == or_cond_reg_1433) & (ap_ST_pp0_stg6_fsm_8 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it2) & ~(ap_const_lv1_0 == or_cond_reg_1433) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it2) & (ap_ST_pp1_stg6_fsm_17 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it2) & ~(ap_const_lv1_0 == or_cond_reg_1433) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it2) & (ap_ST_pp1_stg7_fsm_18 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it3) & ~(ap_const_lv1_0 == or_cond_reg_1433) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it2) & (ap_ST_pp1_stg0_fsm_11 == ap_CS_fsm)) | ((ap_ST_pp1_stg1_fsm_12 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it3) & ~(ap_const_lv1_0 == or_cond_reg_1433) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it3)))) begin
d_we1 = ap_const_logic_1;
end else begin
d_we1 = ap_const_logic_0;
end
end
/// grp_fu_811_p0 assign process. ///
always @ (ap_CS_fsm or reg_823 or ap_reg_ppiten_pp1_it0 or ap_reg_ppiten_pp1_it1 or exitcond2_reg_1603 or reg_829 or reg_835 or reg_841 or reg_847 or reg_853 or reg_859 or ap_reg_ppstg_exitcond2_reg_1603_pp1_it1 or b_load_15_reg_1821)
begin
if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_ST_pp1_stg5_fsm_16 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it1))) begin
grp_fu_811_p0 = b_load_15_reg_1821;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_ST_pp1_stg4_fsm_15 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it1))) begin
grp_fu_811_p0 = reg_859;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_ST_pp1_stg3_fsm_14 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it1))) begin
grp_fu_811_p0 = reg_853;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_ST_pp1_stg2_fsm_13 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it1))) begin
grp_fu_811_p0 = reg_847;
end else if (((ap_ST_pp1_stg1_fsm_12 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it1))) begin
grp_fu_811_p0 = reg_841;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_const_lv1_0 == exitcond2_reg_1603) & (ap_ST_pp1_stg0_fsm_11 == ap_CS_fsm))) begin
grp_fu_811_p0 = reg_835;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond2_reg_1603) & (ap_ST_pp1_stg7_fsm_18 == ap_CS_fsm))) begin
grp_fu_811_p0 = reg_829;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond2_reg_1603) & (ap_ST_pp1_stg6_fsm_17 == ap_CS_fsm))) begin
grp_fu_811_p0 = reg_823;
end else begin
grp_fu_811_p0 = b_load_15_reg_1821;
end
end
/// grp_fu_811_p1 assign process. ///
always @ (ap_CS_fsm or ap_reg_ppiten_pp1_it0 or ap_reg_ppiten_pp1_it1 or exitcond2_reg_1603 or reg_865 or reg_874 or reg_882 or reg_890 or reg_898 or reg_906 or reg_914 or ap_reg_ppstg_exitcond2_reg_1603_pp1_it1 or tmp_52_reg_1826)
begin
if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_ST_pp1_stg5_fsm_16 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it1))) begin
grp_fu_811_p1 = tmp_52_reg_1826;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_ST_pp1_stg4_fsm_15 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it1))) begin
grp_fu_811_p1 = reg_914;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_ST_pp1_stg3_fsm_14 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it1))) begin
grp_fu_811_p1 = reg_906;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_ST_pp1_stg2_fsm_13 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it1))) begin
grp_fu_811_p1 = reg_898;
end else if (((ap_ST_pp1_stg1_fsm_12 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it1))) begin
grp_fu_811_p1 = reg_890;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_const_lv1_0 == exitcond2_reg_1603) & (ap_ST_pp1_stg0_fsm_11 == ap_CS_fsm))) begin
grp_fu_811_p1 = reg_882;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond2_reg_1603) & (ap_ST_pp1_stg7_fsm_18 == ap_CS_fsm))) begin
grp_fu_811_p1 = reg_874;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond2_reg_1603) & (ap_ST_pp1_stg6_fsm_17 == ap_CS_fsm))) begin
grp_fu_811_p1 = reg_865;
end else begin
grp_fu_811_p1 = tmp_52_reg_1826;
end
end
/// grp_fu_815_p0 assign process. ///
always @ (ap_CS_fsm or reg_823 or ap_reg_ppiten_pp0_it0 or ap_reg_ppiten_pp0_it1 or exitcond_reg_1446 or ap_reg_ppiten_pp1_it0 or ap_reg_ppiten_pp1_it1 or ap_reg_ppiten_pp1_it2 or exitcond2_reg_1603 or reg_829 or reg_841 or reg_853 or ap_reg_ppstg_exitcond_reg_1446_pp0_it1 or or_cond_reg_1433 or ap_reg_ppstg_exitcond2_reg_1603_pp1_it2 or reg_874 or reg_890 or reg_906 or reg_928 or ap_reg_ppstg_exitcond2_reg_1603_pp1_it1 or c_load_1_reg_1696 or c_load_3_reg_1740 or c_load_5_reg_1794 or t8_reg_1838 or t10_reg_1852 or t12_reg_1866)
begin
if (((ap_ST_pp1_stg1_fsm_12 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it2) & ~(ap_const_lv1_0 == or_cond_reg_1433) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it2))) begin
grp_fu_815_p0 = t12_reg_1866;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it2) & ~(ap_const_lv1_0 == or_cond_reg_1433) & (ap_ST_pp1_stg0_fsm_11 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it1))) begin
grp_fu_815_p0 = t10_reg_1852;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & ~(ap_const_lv1_0 == or_cond_reg_1433) & (ap_ST_pp1_stg7_fsm_18 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it1))) begin
grp_fu_815_p0 = t8_reg_1838;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond2_reg_1603) & (ap_ST_pp1_stg5_fsm_16 == ap_CS_fsm))) begin
grp_fu_815_p0 = c_load_5_reg_1794;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond2_reg_1603) & (ap_ST_pp1_stg4_fsm_15 == ap_CS_fsm))) begin
grp_fu_815_p0 = c_load_3_reg_1740;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond2_reg_1603) & (ap_ST_pp1_stg3_fsm_14 == ap_CS_fsm))) begin
grp_fu_815_p0 = c_load_1_reg_1696;
end else if ((((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond2_reg_1603) & (ap_ST_pp1_stg2_fsm_13 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond2_reg_1603) & (ap_ST_pp1_stg6_fsm_17 == ap_CS_fsm)))) begin
grp_fu_815_p0 = reg_928;
end else if (((ap_ST_pp0_stg1_fsm_3 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_1446_pp0_it1) & ~(ap_const_lv1_0 == or_cond_reg_1433))) begin
grp_fu_815_p0 = reg_906;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (exitcond_reg_1446 == ap_const_lv1_0) & ~(ap_const_lv1_0 == or_cond_reg_1433) & (ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm))) begin
grp_fu_815_p0 = reg_890;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_reg_1446 == ap_const_lv1_0) & ~(ap_const_lv1_0 == or_cond_reg_1433) & (ap_ST_pp0_stg7_fsm_9 == ap_CS_fsm))) begin
grp_fu_815_p0 = reg_874;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_reg_1446 == ap_const_lv1_0) & (ap_ST_pp0_stg5_fsm_7 == ap_CS_fsm))) begin
grp_fu_815_p0 = reg_853;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_reg_1446 == ap_const_lv1_0) & (ap_ST_pp0_stg4_fsm_6 == ap_CS_fsm))) begin
grp_fu_815_p0 = reg_841;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_reg_1446 == ap_const_lv1_0) & (ap_ST_pp0_stg3_fsm_5 == ap_CS_fsm))) begin
grp_fu_815_p0 = reg_829;
end else if ((((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_reg_1446 == ap_const_lv1_0) & (ap_ST_pp0_stg2_fsm_4 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_reg_1446 == ap_const_lv1_0) & (ap_ST_pp0_stg6_fsm_8 == ap_CS_fsm)))) begin
grp_fu_815_p0 = reg_823;
end else begin
grp_fu_815_p0 = t12_reg_1866;
end
end
/// grp_fu_815_p1 assign process. ///
always @ (ap_CS_fsm or BoundryScale or nu or PostScale or ap_reg_ppiten_pp0_it0 or ap_reg_ppiten_pp0_it1 or exitcond_reg_1446 or ap_reg_ppiten_pp1_it0 or ap_reg_ppiten_pp1_it1 or ap_reg_ppiten_pp1_it2 or exitcond2_reg_1603 or ap_reg_ppstg_exitcond_reg_1446_pp0_it1 or or_cond_reg_1433 or ap_reg_ppstg_exitcond2_reg_1603_pp1_it2 or ap_reg_ppstg_exitcond2_reg_1603_pp1_it1)
begin
if ((((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond2_reg_1603) & (ap_ST_pp1_stg2_fsm_13 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond2_reg_1603) & (ap_ST_pp1_stg3_fsm_14 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond2_reg_1603) & (ap_ST_pp1_stg4_fsm_15 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond2_reg_1603) & (ap_ST_pp1_stg5_fsm_16 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond2_reg_1603) & (ap_ST_pp1_stg6_fsm_17 == ap_CS_fsm)))) begin
grp_fu_815_p1 = nu;
end else if ((((ap_ST_pp0_stg1_fsm_3 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_1446_pp0_it1) & ~(ap_const_lv1_0 == or_cond_reg_1433)) | ((ap_ST_pp1_stg1_fsm_12 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it2) & ~(ap_const_lv1_0 == or_cond_reg_1433) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it2)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_reg_1446 == ap_const_lv1_0) & ~(ap_const_lv1_0 == or_cond_reg_1433) & (ap_ST_pp0_stg7_fsm_9 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (exitcond_reg_1446 == ap_const_lv1_0) & ~(ap_const_lv1_0 == or_cond_reg_1433) & (ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & ~(ap_const_lv1_0 == or_cond_reg_1433) & (ap_ST_pp1_stg7_fsm_18 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it2) & ~(ap_const_lv1_0 == or_cond_reg_1433) & (ap_ST_pp1_stg0_fsm_11 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it1)))) begin
grp_fu_815_p1 = PostScale;
end else if ((((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_reg_1446 == ap_const_lv1_0) & (ap_ST_pp0_stg5_fsm_7 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_reg_1446 == ap_const_lv1_0) & (ap_ST_pp0_stg2_fsm_4 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_reg_1446 == ap_const_lv1_0) & (ap_ST_pp0_stg3_fsm_5 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_reg_1446 == ap_const_lv1_0) & (ap_ST_pp0_stg4_fsm_6 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_reg_1446 == ap_const_lv1_0) & (ap_ST_pp0_stg6_fsm_8 == ap_CS_fsm)))) begin
grp_fu_815_p1 = BoundryScale;
end else begin
grp_fu_815_p1 = nu;
end
end
/// grp_fu_819_p0 assign process. ///
always @ (ap_CS_fsm or ap_reg_ppiten_pp0_it0 or ap_reg_ppiten_pp0_it1 or exitcond_reg_1446 or ap_reg_ppiten_pp1_it0 or ap_reg_ppiten_pp1_it1 or ap_reg_ppiten_pp1_it2 or exitcond2_reg_1603 or reg_835 or reg_847 or reg_859 or reg_865 or ap_reg_ppstg_exitcond_reg_1446_pp0_it1 or or_cond_reg_1433 or ap_reg_ppstg_exitcond2_reg_1603_pp1_it2 or reg_882 or reg_898 or reg_914 or ap_reg_ppstg_exitcond2_reg_1603_pp1_it1 or c_load_2_reg_1701 or c_load_4_reg_1745 or c_load_6_reg_1799 or t_reg_1831 or t9_reg_1845 or t11_reg_1859 or t13_reg_1873 or t14_reg_1880)
begin
if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it2) & (ap_ST_pp1_stg2_fsm_13 == ap_CS_fsm) & ~(ap_const_lv1_0 == or_cond_reg_1433) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it2))) begin
grp_fu_819_p0 = t14_reg_1880;
end else if (((ap_ST_pp1_stg1_fsm_12 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it2) & ~(ap_const_lv1_0 == or_cond_reg_1433) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it2))) begin
grp_fu_819_p0 = t13_reg_1873;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it2) & ~(ap_const_lv1_0 == or_cond_reg_1433) & (ap_ST_pp1_stg0_fsm_11 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it1))) begin
grp_fu_819_p0 = t11_reg_1859;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & ~(ap_const_lv1_0 == or_cond_reg_1433) & (ap_ST_pp1_stg7_fsm_18 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it1))) begin
grp_fu_819_p0 = t9_reg_1845;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & ~(ap_const_lv1_0 == or_cond_reg_1433) & (ap_ST_pp1_stg6_fsm_17 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it1))) begin
grp_fu_819_p0 = t_reg_1831;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond2_reg_1603) & (ap_ST_pp1_stg5_fsm_16 == ap_CS_fsm))) begin
grp_fu_819_p0 = c_load_6_reg_1799;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond2_reg_1603) & (ap_ST_pp1_stg4_fsm_15 == ap_CS_fsm))) begin
grp_fu_819_p0 = c_load_4_reg_1745;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond2_reg_1603) & (ap_ST_pp1_stg3_fsm_14 == ap_CS_fsm))) begin
grp_fu_819_p0 = c_load_2_reg_1701;
end else if (((ap_ST_pp0_stg1_fsm_3 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_1446_pp0_it1) & ~(ap_const_lv1_0 == or_cond_reg_1433))) begin
grp_fu_819_p0 = reg_914;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (exitcond_reg_1446 == ap_const_lv1_0) & ~(ap_const_lv1_0 == or_cond_reg_1433) & (ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm))) begin
grp_fu_819_p0 = reg_898;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_reg_1446 == ap_const_lv1_0) & ~(ap_const_lv1_0 == or_cond_reg_1433) & (ap_ST_pp0_stg7_fsm_9 == ap_CS_fsm))) begin
grp_fu_819_p0 = reg_882;
end else if ((((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (ap_ST_pp0_stg2_fsm_4 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_1446_pp0_it1) & ~(ap_const_lv1_0 == or_cond_reg_1433)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_reg_1446 == ap_const_lv1_0) & ~(ap_const_lv1_0 == or_cond_reg_1433) & (ap_ST_pp0_stg6_fsm_8 == ap_CS_fsm)))) begin
grp_fu_819_p0 = reg_865;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_reg_1446 == ap_const_lv1_0) & (ap_ST_pp0_stg5_fsm_7 == ap_CS_fsm))) begin
grp_fu_819_p0 = reg_859;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_reg_1446 == ap_const_lv1_0) & (ap_ST_pp0_stg4_fsm_6 == ap_CS_fsm))) begin
grp_fu_819_p0 = reg_847;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_reg_1446 == ap_const_lv1_0) & (ap_ST_pp0_stg3_fsm_5 == ap_CS_fsm))) begin
grp_fu_819_p0 = reg_835;
end else begin
grp_fu_819_p0 = t14_reg_1880;
end
end
/// grp_fu_819_p1 assign process. ///
always @ (ap_CS_fsm or BoundryScale or nu or PostScale or ap_reg_ppiten_pp0_it0 or ap_reg_ppiten_pp0_it1 or exitcond_reg_1446 or ap_reg_ppiten_pp1_it0 or ap_reg_ppiten_pp1_it1 or ap_reg_ppiten_pp1_it2 or exitcond2_reg_1603 or ap_reg_ppstg_exitcond_reg_1446_pp0_it1 or or_cond_reg_1433 or ap_reg_ppstg_exitcond2_reg_1603_pp1_it2 or ap_reg_ppstg_exitcond2_reg_1603_pp1_it1)
begin
if ((((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond2_reg_1603) & (ap_ST_pp1_stg3_fsm_14 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond2_reg_1603) & (ap_ST_pp1_stg4_fsm_15 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond2_reg_1603) & (ap_ST_pp1_stg5_fsm_16 == ap_CS_fsm)))) begin
grp_fu_819_p1 = nu;
end else if ((((ap_const_logic_1 == ap_reg_ppiten_pp1_it2) & (ap_ST_pp1_stg2_fsm_13 == ap_CS_fsm) & ~(ap_const_lv1_0 == or_cond_reg_1433) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it2)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (ap_ST_pp0_stg2_fsm_4 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_1446_pp0_it1) & ~(ap_const_lv1_0 == or_cond_reg_1433)) | ((ap_ST_pp0_stg1_fsm_3 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_1446_pp0_it1) & ~(ap_const_lv1_0 == or_cond_reg_1433)) | ((ap_ST_pp1_stg1_fsm_12 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it2) & ~(ap_const_lv1_0 == or_cond_reg_1433) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it2)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_reg_1446 == ap_const_lv1_0) & ~(ap_const_lv1_0 == or_cond_reg_1433) & (ap_ST_pp0_stg7_fsm_9 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (exitcond_reg_1446 == ap_const_lv1_0) & ~(ap_const_lv1_0 == or_cond_reg_1433) & (ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & ~(ap_const_lv1_0 == or_cond_reg_1433) & (ap_ST_pp1_stg7_fsm_18 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it2) & ~(ap_const_lv1_0 == or_cond_reg_1433) & (ap_ST_pp1_stg0_fsm_11 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_reg_1446 == ap_const_lv1_0) & ~(ap_const_lv1_0 == or_cond_reg_1433) & (ap_ST_pp0_stg6_fsm_8 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & ~(ap_const_lv1_0 == or_cond_reg_1433) & (ap_ST_pp1_stg6_fsm_17 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it1)))) begin
grp_fu_819_p1 = PostScale;
end else if ((((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_reg_1446 == ap_const_lv1_0) & (ap_ST_pp0_stg5_fsm_7 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_reg_1446 == ap_const_lv1_0) & (ap_ST_pp0_stg3_fsm_5 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_reg_1446 == ap_const_lv1_0) & (ap_ST_pp0_stg4_fsm_6 == ap_CS_fsm)))) begin
grp_fu_819_p1 = BoundryScale;
end else begin
grp_fu_819_p1 = nu;
end
end
/// i1_phi_fu_781_p4 assign process. ///
always @ (ap_CS_fsm or i1_reg_777 or ap_reg_ppiten_pp1_it1 or exitcond2_reg_1603 or i1_mid2_reg_1624)
begin
if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_const_lv1_0 == exitcond2_reg_1603) & (ap_ST_pp1_stg0_fsm_11 == ap_CS_fsm))) begin
i1_phi_fu_781_p4 = i1_mid2_reg_1624;
end else begin
i1_phi_fu_781_p4 = i1_reg_777;
end
end
/// i_phi_fu_737_p4 assign process. ///
always @ (ap_CS_fsm or i_reg_733 or ap_reg_ppiten_pp0_it1 or exitcond_reg_1446 or i_mid2_reg_1467)
begin
if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (exitcond_reg_1446 == ap_const_lv1_0) & (ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm))) begin
i_phi_fu_737_p4 = i_mid2_reg_1467;
end else begin
i_phi_fu_737_p4 = i_reg_733;
end
end
/// indvar3_phi_fu_748_p4 assign process. ///
always @ (ap_CS_fsm or indvar3_reg_744 or ap_reg_ppiten_pp0_it1 or exitcond_reg_1446 or indvar_next4_reg_1495)
begin
if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (exitcond_reg_1446 == ap_const_lv1_0) & (ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm))) begin
indvar3_phi_fu_748_p4 = indvar_next4_reg_1495;
end else begin
indvar3_phi_fu_748_p4 = indvar3_reg_744;
end
end
/// indvar_flatten9_phi_fu_770_p4 assign process. ///
always @ (ap_CS_fsm or indvar_flatten9_reg_766 or ap_reg_ppiten_pp1_it1 or exitcond2_reg_1603 or indvar_flatten_next1_reg_1607)
begin
if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_const_lv1_0 == exitcond2_reg_1603) & (ap_ST_pp1_stg0_fsm_11 == ap_CS_fsm))) begin
indvar_flatten9_phi_fu_770_p4 = indvar_flatten_next1_reg_1607;
end else begin
indvar_flatten9_phi_fu_770_p4 = indvar_flatten9_reg_766;
end
end
/// indvar_flatten_phi_fu_726_p4 assign process. ///
always @ (ap_CS_fsm or indvar_flatten_reg_722 or ap_reg_ppiten_pp0_it1 or exitcond_reg_1446 or indvar_flatten_next_reg_1450)
begin
if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (exitcond_reg_1446 == ap_const_lv1_0) & (ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm))) begin
indvar_flatten_phi_fu_726_p4 = indvar_flatten_next_reg_1450;
end else begin
indvar_flatten_phi_fu_726_p4 = indvar_flatten_reg_722;
end
end
/// indvar_phi_fu_792_p4 assign process. ///
always @ (ap_CS_fsm or indvar_reg_788 or ap_reg_ppiten_pp1_it1 or exitcond2_reg_1603 or indvar_next_reg_1657)
begin
if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_const_lv1_0 == exitcond2_reg_1603) & (ap_ST_pp1_stg0_fsm_11 == ap_CS_fsm))) begin
indvar_phi_fu_792_p4 = indvar_next_reg_1657;
end else begin
indvar_phi_fu_792_p4 = indvar_reg_788;
end
end
/// j1_phi_fu_803_p4 assign process. ///
always @ (ap_CS_fsm or j1_reg_799 or ap_reg_ppiten_pp1_it1 or exitcond2_reg_1603 or tmp_61_reg_1789)
begin
if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_const_lv1_0 == exitcond2_reg_1603) & (ap_ST_pp1_stg0_fsm_11 == ap_CS_fsm))) begin
j1_phi_fu_803_p4 = tmp_61_reg_1789;
end else begin
j1_phi_fu_803_p4 = j1_reg_799;
end
end
/// j_phi_fu_759_p4 assign process. ///
always @ (ap_CS_fsm or j_reg_755 or ap_reg_ppiten_pp0_it1 or exitcond_reg_1446 or tmp_28_reg_1577)
begin
if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (exitcond_reg_1446 == ap_const_lv1_0) & (ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm))) begin
j_phi_fu_759_p4 = tmp_28_reg_1577;
end else begin
j_phi_fu_759_p4 = j_reg_755;
end
end
assign b_addr10_fu_1251_p2 = (b_addr9_cast_fu_1247_p1 + tmp_32_trn_cast_fu_1237_p1);
assign b_addr11_fu_1286_p2 = (b_addr9_cast_reg_1629 + tmp_35_trn_cast_fu_1282_p1);
assign b_addr12_fu_1306_p2 = (b_addr9_cast_reg_1629 + tmp_38_trn_cast_fu_1302_p1);
assign b_addr13_fu_1326_p2 = (b_addr9_cast_reg_1629 + tmp_41_trn_cast_fu_1322_p1);
assign b_addr14_fu_1346_p2 = (b_addr9_cast_reg_1629 + tmp_44_trn_cast_fu_1342_p1);
assign b_addr15_fu_1366_p2 = (b_addr9_cast_reg_1629 + tmp_47_trn_cast_fu_1362_p1);
assign b_addr16_fu_1386_p2 = (b_addr9_cast_reg_1629 + tmp_50_trn_cast_fu_1382_p1);
assign b_addr17_fu_1406_p2 = (b_addr9_cast_reg_1629 + tmp_53_trn_cast_fu_1402_p1);
assign b_addr1_fu_1015_p2 = (b_addr_cast_fu_1011_p1 + tmp_7_trn_cast_fu_1001_p1);
assign b_addr2_fu_1049_p2 = (b_addr_cast_reg_1472 + tmp_9_trn_cast_fu_1045_p1);
assign b_addr3_fu_1068_p2 = (b_addr_cast_reg_1472 + tmp_10_trn_cast_fu_1064_p1);
assign b_addr4_fu_1087_p2 = (b_addr_cast_reg_1472 + tmp_12_trn_cast_fu_1083_p1);
assign b_addr5_fu_1106_p2 = (b_addr_cast_reg_1472 + tmp_14_trn_cast_fu_1102_p1);
assign b_addr6_fu_1125_p2 = (b_addr_cast_reg_1472 + tmp_16_trn_cast_fu_1121_p1);
assign b_addr7_fu_1144_p2 = (b_addr_cast_reg_1472 + tmp_18_trn_cast_fu_1140_p1);
assign b_addr8_fu_1163_p2 = (b_addr_cast_reg_1472 + tmp_20_trn_cast_fu_1159_p1);
assign b_addr9_cast_fu_1247_p1 = {{1{1'b0}}, {b_addr9_fu_1241_p2}};
assign b_addr9_fu_1241_p2 = tmp_29_trn_cast_fu_1233_p1 << ap_const_lv13_6;
assign b_addr_cast_fu_1011_p1 = {{1{1'b0}}, {b_addr_fu_1005_p2}};
assign b_addr_fu_1005_p2 = tmp_3_trn_cast_fu_997_p1 << ap_const_lv13_6;
assign exitcond1_fu_969_p2 = (indvar3_phi_fu_748_p4 == ap_const_lv4_8? 1'b1: 1'b0);
assign exitcond2_fu_1193_p2 = (indvar_flatten9_phi_fu_770_p4 == ap_const_lv10_200? 1'b1: 1'b0);
assign exitcond3_fu_1205_p2 = (indvar_phi_fu_792_p4 == ap_const_lv4_8? 1'b1: 1'b0);
assign exitcond_fu_957_p2 = (indvar_flatten_phi_fu_726_p4 == ap_const_lv10_200? 1'b1: 1'b0);
assign grp_fu_811_ce = ap_const_logic_1;
assign grp_fu_815_ce = ap_const_logic_1;
assign grp_fu_819_ce = ap_const_logic_1;
assign i1_mid2_fu_1225_p3 = ((exitcond3_fu_1205_p2)? tmp_31_dup_fu_1219_p2: i1_phi_fu_781_p4);
assign i_mid2_fu_989_p3 = ((exitcond1_fu_969_p2)? tmp_6_dup_fu_983_p2: i_phi_fu_737_p4);
assign indvar3_op_fu_1026_p2 = (indvar3_phi_fu_748_p4 + ap_const_lv4_1);
assign indvar_op_fu_1263_p2 = (indvar_phi_fu_792_p4 + ap_const_lv4_1);
assign j1_mid2_fu_1211_p3 = ((exitcond3_fu_1205_p2)? ap_const_lv7_0: j1_phi_fu_803_p4);
assign j_mid2_fu_975_p3 = ((exitcond1_fu_969_p2)? ap_const_lv7_0: j_phi_fu_759_p4);
assign or_cond1_fu_1187_p2 = (tmp_4_fu_1177_p2 & tmp_5_fu_1182_p2);
assign tmp_10_fu_1078_p2 = (j_mid2_reg_1455 | ap_const_lv7_3);
assign tmp_10_trn_cast_fu_1064_p1 = {{7{1'b0}}, {tmp_s_fu_1059_p2}};
assign tmp_11_fu_1092_p1 = {{50{1'b0}}, {b_addr4_fu_1087_p2}};
assign tmp_12_fu_1097_p2 = (j_mid2_reg_1455 | ap_const_lv7_4);
assign tmp_12_trn_cast_fu_1083_p1 = {{7{1'b0}}, {tmp_10_fu_1078_p2}};
assign tmp_13_fu_1111_p1 = {{50{1'b0}}, {b_addr5_fu_1106_p2}};
assign tmp_14_fu_1116_p2 = (j_mid2_reg_1455 | ap_const_lv7_5);
assign tmp_14_trn_cast_fu_1102_p1 = {{7{1'b0}}, {tmp_12_fu_1097_p2}};
assign tmp_15_fu_1130_p1 = {{50{1'b0}}, {b_addr6_fu_1125_p2}};
assign tmp_16_fu_1135_p2 = (j_mid2_reg_1455 | ap_const_lv7_6);
assign tmp_16_trn_cast_fu_1121_p1 = {{7{1'b0}}, {tmp_14_fu_1116_p2}};
assign tmp_17_fu_1149_p1 = {{50{1'b0}}, {b_addr7_fu_1144_p2}};
assign tmp_18_fu_1154_p2 = (j_mid2_reg_1455 | ap_const_lv7_7);
assign tmp_18_trn_cast_fu_1140_p1 = {{7{1'b0}}, {tmp_16_fu_1135_p2}};
assign tmp_19_fu_1173_p1 = {{50{1'b0}}, {b_addr8_reg_1572}};
assign tmp_1_fu_939_p2 = (step ^ ap_const_lv1_1);
assign tmp_20_trn_cast_fu_1159_p1 = {{7{1'b0}}, {tmp_18_fu_1154_p2}};
assign tmp_29_trn_cast_fu_1233_p1 = {{6{1'b0}}, {i1_mid2_fu_1225_p3}};
assign tmp_2_fu_951_p2 = (counter == ap_const_lv7_2? 1'b1: 1'b0);
assign tmp_30_fu_1257_p1 = {{50{1'b0}}, {b_addr10_fu_1251_p2}};
assign tmp_31_dup_fu_1219_p2 = (i1_phi_fu_781_p4 + ap_const_lv7_1);
assign tmp_32_fu_1277_p2 = (j1_mid2_reg_1612 | ap_const_lv7_1);
assign tmp_32_trn_cast_fu_1237_p1 = {{7{1'b0}}, {j1_mid2_fu_1211_p3}};
assign tmp_33_fu_1291_p1 = {{50{1'b0}}, {b_addr11_fu_1286_p2}};
assign tmp_35_fu_1297_p2 = (j1_mid2_reg_1612 | ap_const_lv7_2);
assign tmp_35_trn_cast_fu_1282_p1 = {{7{1'b0}}, {tmp_32_fu_1277_p2}};
assign tmp_36_fu_1311_p1 = {{50{1'b0}}, {b_addr12_fu_1306_p2}};
assign tmp_38_fu_1317_p2 = (j1_mid2_reg_1612 | ap_const_lv7_3);
assign tmp_38_trn_cast_fu_1302_p1 = {{7{1'b0}}, {tmp_35_fu_1297_p2}};
assign tmp_39_fu_1331_p1 = {{50{1'b0}}, {b_addr13_fu_1326_p2}};
assign tmp_3_trn_cast_fu_997_p1 = {{6{1'b0}}, {i_mid2_fu_989_p3}};
assign tmp_41_fu_1337_p2 = (j1_mid2_reg_1612 | ap_const_lv7_4);
assign tmp_41_trn_cast_fu_1322_p1 = {{7{1'b0}}, {tmp_38_fu_1317_p2}};
assign tmp_42_fu_1351_p1 = {{50{1'b0}}, {b_addr14_fu_1346_p2}};
assign tmp_44_fu_1357_p2 = (j1_mid2_reg_1612 | ap_const_lv7_5);
assign tmp_44_trn_cast_fu_1342_p1 = {{7{1'b0}}, {tmp_41_fu_1337_p2}};
assign tmp_45_fu_1371_p1 = {{50{1'b0}}, {b_addr15_fu_1366_p2}};
assign tmp_47_fu_1377_p2 = (j1_mid2_reg_1612 | ap_const_lv7_6);
assign tmp_47_trn_cast_fu_1362_p1 = {{7{1'b0}}, {tmp_44_fu_1357_p2}};
assign tmp_48_fu_1391_p1 = {{50{1'b0}}, {b_addr16_fu_1386_p2}};
assign tmp_4_fu_1177_p2 = (counter < ap_const_lv7_42? 1'b1: 1'b0);
assign tmp_50_fu_1397_p2 = (j1_mid2_reg_1612 | ap_const_lv7_7);
assign tmp_50_trn_cast_fu_1382_p1 = {{7{1'b0}}, {tmp_47_fu_1377_p2}};
assign tmp_51_fu_1416_p1 = {{50{1'b0}}, {b_addr17_reg_1784}};
assign tmp_53_trn_cast_fu_1402_p1 = {{7{1'b0}}, {tmp_50_fu_1397_p2}};
assign tmp_5_fu_1182_p2 = (counter > ap_const_lv7_2? 1'b1: 1'b0);
assign tmp_6_dup_fu_983_p2 = (i_phi_fu_737_p4 + ap_const_lv7_1);
assign tmp_6_fu_1021_p1 = {{50{1'b0}}, {b_addr1_fu_1015_p2}};
assign tmp_7_fu_1054_p1 = {{50{1'b0}}, {b_addr2_fu_1049_p2}};
assign tmp_7_trn_cast_fu_1001_p1 = {{7{1'b0}}, {j_mid2_fu_975_p3}};
assign tmp_8_fu_1040_p2 = (j_mid2_reg_1455 | ap_const_lv7_1);
assign tmp_9_fu_1073_p1 = {{50{1'b0}}, {b_addr3_fu_1068_p2}};
assign tmp_9_trn_cast_fu_1045_p1 = {{7{1'b0}}, {tmp_8_fu_1040_p2}};
assign tmp_fu_933_p2 = (tag == ap_const_lv2_1? 1'b1: 1'b0);
assign tmp_s_fu_1059_p2 = (j_mid2_reg_1455 | ap_const_lv7_2);
always @ (ap_clk)
begin
b_addr_cast_reg_1472[0] <= 1'b0;
b_addr_cast_reg_1472[1] <= 1'b0;
b_addr_cast_reg_1472[2] <= 1'b0;
b_addr_cast_reg_1472[3] <= 1'b0;
b_addr_cast_reg_1472[4] <= 1'b0;
b_addr_cast_reg_1472[5] <= 1'b0;
b_addr_cast_reg_1472[13] <= 1'b0;
end
always @ (ap_clk)
begin
tmp_6_reg_1483[14] <= 1'b0;
tmp_6_reg_1483[15] <= 1'b0;
tmp_6_reg_1483[16] <= 1'b0;
tmp_6_reg_1483[17] <= 1'b0;
tmp_6_reg_1483[18] <= 1'b0;
tmp_6_reg_1483[19] <= 1'b0;
tmp_6_reg_1483[20] <= 1'b0;
tmp_6_reg_1483[21] <= 1'b0;
tmp_6_reg_1483[22] <= 1'b0;
tmp_6_reg_1483[23] <= 1'b0;
tmp_6_reg_1483[24] <= 1'b0;
tmp_6_reg_1483[25] <= 1'b0;
tmp_6_reg_1483[26] <= 1'b0;
tmp_6_reg_1483[27] <= 1'b0;
tmp_6_reg_1483[28] <= 1'b0;
tmp_6_reg_1483[29] <= 1'b0;
tmp_6_reg_1483[30] <= 1'b0;
tmp_6_reg_1483[31] <= 1'b0;
tmp_6_reg_1483[32] <= 1'b0;
tmp_6_reg_1483[33] <= 1'b0;
tmp_6_reg_1483[34] <= 1'b0;
tmp_6_reg_1483[35] <= 1'b0;
tmp_6_reg_1483[36] <= 1'b0;
tmp_6_reg_1483[37] <= 1'b0;
tmp_6_reg_1483[38] <= 1'b0;
tmp_6_reg_1483[39] <= 1'b0;
tmp_6_reg_1483[40] <= 1'b0;
tmp_6_reg_1483[41] <= 1'b0;
tmp_6_reg_1483[42] <= 1'b0;
tmp_6_reg_1483[43] <= 1'b0;
tmp_6_reg_1483[44] <= 1'b0;
tmp_6_reg_1483[45] <= 1'b0;
tmp_6_reg_1483[46] <= 1'b0;
tmp_6_reg_1483[47] <= 1'b0;
tmp_6_reg_1483[48] <= 1'b0;
tmp_6_reg_1483[49] <= 1'b0;
tmp_6_reg_1483[50] <= 1'b0;
tmp_6_reg_1483[51] <= 1'b0;
tmp_6_reg_1483[52] <= 1'b0;
tmp_6_reg_1483[53] <= 1'b0;
tmp_6_reg_1483[54] <= 1'b0;
tmp_6_reg_1483[55] <= 1'b0;
tmp_6_reg_1483[56] <= 1'b0;
tmp_6_reg_1483[57] <= 1'b0;
tmp_6_reg_1483[58] <= 1'b0;
tmp_6_reg_1483[59] <= 1'b0;
tmp_6_reg_1483[60] <= 1'b0;
tmp_6_reg_1483[61] <= 1'b0;
tmp_6_reg_1483[62] <= 1'b0;
tmp_6_reg_1483[63] <= 1'b0;
end
always @ (ap_clk)
begin
ap_reg_ppstg_tmp_6_reg_1483_pp0_it1[14] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_1483_pp0_it1[15] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_1483_pp0_it1[16] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_1483_pp0_it1[17] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_1483_pp0_it1[18] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_1483_pp0_it1[19] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_1483_pp0_it1[20] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_1483_pp0_it1[21] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_1483_pp0_it1[22] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_1483_pp0_it1[23] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_1483_pp0_it1[24] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_1483_pp0_it1[25] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_1483_pp0_it1[26] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_1483_pp0_it1[27] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_1483_pp0_it1[28] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_1483_pp0_it1[29] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_1483_pp0_it1[30] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_1483_pp0_it1[31] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_1483_pp0_it1[32] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_1483_pp0_it1[33] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_1483_pp0_it1[34] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_1483_pp0_it1[35] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_1483_pp0_it1[36] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_1483_pp0_it1[37] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_1483_pp0_it1[38] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_1483_pp0_it1[39] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_1483_pp0_it1[40] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_1483_pp0_it1[41] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_1483_pp0_it1[42] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_1483_pp0_it1[43] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_1483_pp0_it1[44] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_1483_pp0_it1[45] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_1483_pp0_it1[46] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_1483_pp0_it1[47] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_1483_pp0_it1[48] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_1483_pp0_it1[49] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_1483_pp0_it1[50] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_1483_pp0_it1[51] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_1483_pp0_it1[52] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_1483_pp0_it1[53] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_1483_pp0_it1[54] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_1483_pp0_it1[55] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_1483_pp0_it1[56] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_1483_pp0_it1[57] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_1483_pp0_it1[58] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_1483_pp0_it1[59] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_1483_pp0_it1[60] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_1483_pp0_it1[61] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_1483_pp0_it1[62] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_1483_pp0_it1[63] <= 1'b0;
end
always @ (ap_clk)
begin
tmp_7_reg_1500[0] <= 1'b1;
tmp_7_reg_1500[14] <= 1'b0;
tmp_7_reg_1500[15] <= 1'b0;
tmp_7_reg_1500[16] <= 1'b0;
tmp_7_reg_1500[17] <= 1'b0;
tmp_7_reg_1500[18] <= 1'b0;
tmp_7_reg_1500[19] <= 1'b0;
tmp_7_reg_1500[20] <= 1'b0;
tmp_7_reg_1500[21] <= 1'b0;
tmp_7_reg_1500[22] <= 1'b0;
tmp_7_reg_1500[23] <= 1'b0;
tmp_7_reg_1500[24] <= 1'b0;
tmp_7_reg_1500[25] <= 1'b0;
tmp_7_reg_1500[26] <= 1'b0;
tmp_7_reg_1500[27] <= 1'b0;
tmp_7_reg_1500[28] <= 1'b0;
tmp_7_reg_1500[29] <= 1'b0;
tmp_7_reg_1500[30] <= 1'b0;
tmp_7_reg_1500[31] <= 1'b0;
tmp_7_reg_1500[32] <= 1'b0;
tmp_7_reg_1500[33] <= 1'b0;
tmp_7_reg_1500[34] <= 1'b0;
tmp_7_reg_1500[35] <= 1'b0;
tmp_7_reg_1500[36] <= 1'b0;
tmp_7_reg_1500[37] <= 1'b0;
tmp_7_reg_1500[38] <= 1'b0;
tmp_7_reg_1500[39] <= 1'b0;
tmp_7_reg_1500[40] <= 1'b0;
tmp_7_reg_1500[41] <= 1'b0;
tmp_7_reg_1500[42] <= 1'b0;
tmp_7_reg_1500[43] <= 1'b0;
tmp_7_reg_1500[44] <= 1'b0;
tmp_7_reg_1500[45] <= 1'b0;
tmp_7_reg_1500[46] <= 1'b0;
tmp_7_reg_1500[47] <= 1'b0;
tmp_7_reg_1500[48] <= 1'b0;
tmp_7_reg_1500[49] <= 1'b0;
tmp_7_reg_1500[50] <= 1'b0;
tmp_7_reg_1500[51] <= 1'b0;
tmp_7_reg_1500[52] <= 1'b0;
tmp_7_reg_1500[53] <= 1'b0;
tmp_7_reg_1500[54] <= 1'b0;
tmp_7_reg_1500[55] <= 1'b0;
tmp_7_reg_1500[56] <= 1'b0;
tmp_7_reg_1500[57] <= 1'b0;
tmp_7_reg_1500[58] <= 1'b0;
tmp_7_reg_1500[59] <= 1'b0;
tmp_7_reg_1500[60] <= 1'b0;
tmp_7_reg_1500[61] <= 1'b0;
tmp_7_reg_1500[62] <= 1'b0;
tmp_7_reg_1500[63] <= 1'b0;
end
always @ (ap_clk)
begin
ap_reg_ppstg_tmp_7_reg_1500_pp0_it1[0] <= 1'b1;
ap_reg_ppstg_tmp_7_reg_1500_pp0_it1[14] <= 1'b0;
ap_reg_ppstg_tmp_7_reg_1500_pp0_it1[15] <= 1'b0;
ap_reg_ppstg_tmp_7_reg_1500_pp0_it1[16] <= 1'b0;
ap_reg_ppstg_tmp_7_reg_1500_pp0_it1[17] <= 1'b0;
ap_reg_ppstg_tmp_7_reg_1500_pp0_it1[18] <= 1'b0;
ap_reg_ppstg_tmp_7_reg_1500_pp0_it1[19] <= 1'b0;
ap_reg_ppstg_tmp_7_reg_1500_pp0_it1[20] <= 1'b0;
ap_reg_ppstg_tmp_7_reg_1500_pp0_it1[21] <= 1'b0;
ap_reg_ppstg_tmp_7_reg_1500_pp0_it1[22] <= 1'b0;
ap_reg_ppstg_tmp_7_reg_1500_pp0_it1[23] <= 1'b0;
ap_reg_ppstg_tmp_7_reg_1500_pp0_it1[24] <= 1'b0;
ap_reg_ppstg_tmp_7_reg_1500_pp0_it1[25] <= 1'b0;
ap_reg_ppstg_tmp_7_reg_1500_pp0_it1[26] <= 1'b0;
ap_reg_ppstg_tmp_7_reg_1500_pp0_it1[27] <= 1'b0;
ap_reg_ppstg_tmp_7_reg_1500_pp0_it1[28] <= 1'b0;
ap_reg_ppstg_tmp_7_reg_1500_pp0_it1[29] <= 1'b0;
ap_reg_ppstg_tmp_7_reg_1500_pp0_it1[30] <= 1'b0;
ap_reg_ppstg_tmp_7_reg_1500_pp0_it1[31] <= 1'b0;
ap_reg_ppstg_tmp_7_reg_1500_pp0_it1[32] <= 1'b0;
ap_reg_ppstg_tmp_7_reg_1500_pp0_it1[33] <= 1'b0;
ap_reg_ppstg_tmp_7_reg_1500_pp0_it1[34] <= 1'b0;
ap_reg_ppstg_tmp_7_reg_1500_pp0_it1[35] <= 1'b0;
ap_reg_ppstg_tmp_7_reg_1500_pp0_it1[36] <= 1'b0;
ap_reg_ppstg_tmp_7_reg_1500_pp0_it1[37] <= 1'b0;
ap_reg_ppstg_tmp_7_reg_1500_pp0_it1[38] <= 1'b0;
ap_reg_ppstg_tmp_7_reg_1500_pp0_it1[39] <= 1'b0;
ap_reg_ppstg_tmp_7_reg_1500_pp0_it1[40] <= 1'b0;
ap_reg_ppstg_tmp_7_reg_1500_pp0_it1[41] <= 1'b0;
ap_reg_ppstg_tmp_7_reg_1500_pp0_it1[42] <= 1'b0;
ap_reg_ppstg_tmp_7_reg_1500_pp0_it1[43] <= 1'b0;
ap_reg_ppstg_tmp_7_reg_1500_pp0_it1[44] <= 1'b0;
ap_reg_ppstg_tmp_7_reg_1500_pp0_it1[45] <= 1'b0;
ap_reg_ppstg_tmp_7_reg_1500_pp0_it1[46] <= 1'b0;
ap_reg_ppstg_tmp_7_reg_1500_pp0_it1[47] <= 1'b0;
ap_reg_ppstg_tmp_7_reg_1500_pp0_it1[48] <= 1'b0;
ap_reg_ppstg_tmp_7_reg_1500_pp0_it1[49] <= 1'b0;
ap_reg_ppstg_tmp_7_reg_1500_pp0_it1[50] <= 1'b0;
ap_reg_ppstg_tmp_7_reg_1500_pp0_it1[51] <= 1'b0;
ap_reg_ppstg_tmp_7_reg_1500_pp0_it1[52] <= 1'b0;
ap_reg_ppstg_tmp_7_reg_1500_pp0_it1[53] <= 1'b0;
ap_reg_ppstg_tmp_7_reg_1500_pp0_it1[54] <= 1'b0;
ap_reg_ppstg_tmp_7_reg_1500_pp0_it1[55] <= 1'b0;
ap_reg_ppstg_tmp_7_reg_1500_pp0_it1[56] <= 1'b0;
ap_reg_ppstg_tmp_7_reg_1500_pp0_it1[57] <= 1'b0;
ap_reg_ppstg_tmp_7_reg_1500_pp0_it1[58] <= 1'b0;
ap_reg_ppstg_tmp_7_reg_1500_pp0_it1[59] <= 1'b0;
ap_reg_ppstg_tmp_7_reg_1500_pp0_it1[60] <= 1'b0;
ap_reg_ppstg_tmp_7_reg_1500_pp0_it1[61] <= 1'b0;
ap_reg_ppstg_tmp_7_reg_1500_pp0_it1[62] <= 1'b0;
ap_reg_ppstg_tmp_7_reg_1500_pp0_it1[63] <= 1'b0;
end
always @ (ap_clk)
begin
tmp_9_reg_1512[14] <= 1'b0;
tmp_9_reg_1512[15] <= 1'b0;
tmp_9_reg_1512[16] <= 1'b0;
tmp_9_reg_1512[17] <= 1'b0;
tmp_9_reg_1512[18] <= 1'b0;
tmp_9_reg_1512[19] <= 1'b0;
tmp_9_reg_1512[20] <= 1'b0;
tmp_9_reg_1512[21] <= 1'b0;
tmp_9_reg_1512[22] <= 1'b0;
tmp_9_reg_1512[23] <= 1'b0;
tmp_9_reg_1512[24] <= 1'b0;
tmp_9_reg_1512[25] <= 1'b0;
tmp_9_reg_1512[26] <= 1'b0;
tmp_9_reg_1512[27] <= 1'b0;
tmp_9_reg_1512[28] <= 1'b0;
tmp_9_reg_1512[29] <= 1'b0;
tmp_9_reg_1512[30] <= 1'b0;
tmp_9_reg_1512[31] <= 1'b0;
tmp_9_reg_1512[32] <= 1'b0;
tmp_9_reg_1512[33] <= 1'b0;
tmp_9_reg_1512[34] <= 1'b0;
tmp_9_reg_1512[35] <= 1'b0;
tmp_9_reg_1512[36] <= 1'b0;
tmp_9_reg_1512[37] <= 1'b0;
tmp_9_reg_1512[38] <= 1'b0;
tmp_9_reg_1512[39] <= 1'b0;
tmp_9_reg_1512[40] <= 1'b0;
tmp_9_reg_1512[41] <= 1'b0;
tmp_9_reg_1512[42] <= 1'b0;
tmp_9_reg_1512[43] <= 1'b0;
tmp_9_reg_1512[44] <= 1'b0;
tmp_9_reg_1512[45] <= 1'b0;
tmp_9_reg_1512[46] <= 1'b0;
tmp_9_reg_1512[47] <= 1'b0;
tmp_9_reg_1512[48] <= 1'b0;
tmp_9_reg_1512[49] <= 1'b0;
tmp_9_reg_1512[50] <= 1'b0;
tmp_9_reg_1512[51] <= 1'b0;
tmp_9_reg_1512[52] <= 1'b0;
tmp_9_reg_1512[53] <= 1'b0;
tmp_9_reg_1512[54] <= 1'b0;
tmp_9_reg_1512[55] <= 1'b0;
tmp_9_reg_1512[56] <= 1'b0;
tmp_9_reg_1512[57] <= 1'b0;
tmp_9_reg_1512[58] <= 1'b0;
tmp_9_reg_1512[59] <= 1'b0;
tmp_9_reg_1512[60] <= 1'b0;
tmp_9_reg_1512[61] <= 1'b0;
tmp_9_reg_1512[62] <= 1'b0;
tmp_9_reg_1512[63] <= 1'b0;
end
always @ (ap_clk)
begin
ap_reg_ppstg_tmp_9_reg_1512_pp0_it1[14] <= 1'b0;
ap_reg_ppstg_tmp_9_reg_1512_pp0_it1[15] <= 1'b0;
ap_reg_ppstg_tmp_9_reg_1512_pp0_it1[16] <= 1'b0;
ap_reg_ppstg_tmp_9_reg_1512_pp0_it1[17] <= 1'b0;
ap_reg_ppstg_tmp_9_reg_1512_pp0_it1[18] <= 1'b0;
ap_reg_ppstg_tmp_9_reg_1512_pp0_it1[19] <= 1'b0;
ap_reg_ppstg_tmp_9_reg_1512_pp0_it1[20] <= 1'b0;
ap_reg_ppstg_tmp_9_reg_1512_pp0_it1[21] <= 1'b0;
ap_reg_ppstg_tmp_9_reg_1512_pp0_it1[22] <= 1'b0;
ap_reg_ppstg_tmp_9_reg_1512_pp0_it1[23] <= 1'b0;
ap_reg_ppstg_tmp_9_reg_1512_pp0_it1[24] <= 1'b0;
ap_reg_ppstg_tmp_9_reg_1512_pp0_it1[25] <= 1'b0;
ap_reg_ppstg_tmp_9_reg_1512_pp0_it1[26] <= 1'b0;
ap_reg_ppstg_tmp_9_reg_1512_pp0_it1[27] <= 1'b0;
ap_reg_ppstg_tmp_9_reg_1512_pp0_it1[28] <= 1'b0;
ap_reg_ppstg_tmp_9_reg_1512_pp0_it1[29] <= 1'b0;
ap_reg_ppstg_tmp_9_reg_1512_pp0_it1[30] <= 1'b0;
ap_reg_ppstg_tmp_9_reg_1512_pp0_it1[31] <= 1'b0;
ap_reg_ppstg_tmp_9_reg_1512_pp0_it1[32] <= 1'b0;
ap_reg_ppstg_tmp_9_reg_1512_pp0_it1[33] <= 1'b0;
ap_reg_ppstg_tmp_9_reg_1512_pp0_it1[34] <= 1'b0;
ap_reg_ppstg_tmp_9_reg_1512_pp0_it1[35] <= 1'b0;
ap_reg_ppstg_tmp_9_reg_1512_pp0_it1[36] <= 1'b0;
ap_reg_ppstg_tmp_9_reg_1512_pp0_it1[37] <= 1'b0;
ap_reg_ppstg_tmp_9_reg_1512_pp0_it1[38] <= 1'b0;
ap_reg_ppstg_tmp_9_reg_1512_pp0_it1[39] <= 1'b0;
ap_reg_ppstg_tmp_9_reg_1512_pp0_it1[40] <= 1'b0;
ap_reg_ppstg_tmp_9_reg_1512_pp0_it1[41] <= 1'b0;
ap_reg_ppstg_tmp_9_reg_1512_pp0_it1[42] <= 1'b0;
ap_reg_ppstg_tmp_9_reg_1512_pp0_it1[43] <= 1'b0;
ap_reg_ppstg_tmp_9_reg_1512_pp0_it1[44] <= 1'b0;
ap_reg_ppstg_tmp_9_reg_1512_pp0_it1[45] <= 1'b0;
ap_reg_ppstg_tmp_9_reg_1512_pp0_it1[46] <= 1'b0;
ap_reg_ppstg_tmp_9_reg_1512_pp0_it1[47] <= 1'b0;
ap_reg_ppstg_tmp_9_reg_1512_pp0_it1[48] <= 1'b0;
ap_reg_ppstg_tmp_9_reg_1512_pp0_it1[49] <= 1'b0;
ap_reg_ppstg_tmp_9_reg_1512_pp0_it1[50] <= 1'b0;
ap_reg_ppstg_tmp_9_reg_1512_pp0_it1[51] <= 1'b0;
ap_reg_ppstg_tmp_9_reg_1512_pp0_it1[52] <= 1'b0;
ap_reg_ppstg_tmp_9_reg_1512_pp0_it1[53] <= 1'b0;
ap_reg_ppstg_tmp_9_reg_1512_pp0_it1[54] <= 1'b0;
ap_reg_ppstg_tmp_9_reg_1512_pp0_it1[55] <= 1'b0;
ap_reg_ppstg_tmp_9_reg_1512_pp0_it1[56] <= 1'b0;
ap_reg_ppstg_tmp_9_reg_1512_pp0_it1[57] <= 1'b0;
ap_reg_ppstg_tmp_9_reg_1512_pp0_it1[58] <= 1'b0;
ap_reg_ppstg_tmp_9_reg_1512_pp0_it1[59] <= 1'b0;
ap_reg_ppstg_tmp_9_reg_1512_pp0_it1[60] <= 1'b0;
ap_reg_ppstg_tmp_9_reg_1512_pp0_it1[61] <= 1'b0;
ap_reg_ppstg_tmp_9_reg_1512_pp0_it1[62] <= 1'b0;
ap_reg_ppstg_tmp_9_reg_1512_pp0_it1[63] <= 1'b0;
end
always @ (ap_clk)
begin
tmp_11_reg_1524[0] <= 1'b1;
tmp_11_reg_1524[1] <= 1'b1;
tmp_11_reg_1524[14] <= 1'b0;
tmp_11_reg_1524[15] <= 1'b0;
tmp_11_reg_1524[16] <= 1'b0;
tmp_11_reg_1524[17] <= 1'b0;
tmp_11_reg_1524[18] <= 1'b0;
tmp_11_reg_1524[19] <= 1'b0;
tmp_11_reg_1524[20] <= 1'b0;
tmp_11_reg_1524[21] <= 1'b0;
tmp_11_reg_1524[22] <= 1'b0;
tmp_11_reg_1524[23] <= 1'b0;
tmp_11_reg_1524[24] <= 1'b0;
tmp_11_reg_1524[25] <= 1'b0;
tmp_11_reg_1524[26] <= 1'b0;
tmp_11_reg_1524[27] <= 1'b0;
tmp_11_reg_1524[28] <= 1'b0;
tmp_11_reg_1524[29] <= 1'b0;
tmp_11_reg_1524[30] <= 1'b0;
tmp_11_reg_1524[31] <= 1'b0;
tmp_11_reg_1524[32] <= 1'b0;
tmp_11_reg_1524[33] <= 1'b0;
tmp_11_reg_1524[34] <= 1'b0;
tmp_11_reg_1524[35] <= 1'b0;
tmp_11_reg_1524[36] <= 1'b0;
tmp_11_reg_1524[37] <= 1'b0;
tmp_11_reg_1524[38] <= 1'b0;
tmp_11_reg_1524[39] <= 1'b0;
tmp_11_reg_1524[40] <= 1'b0;
tmp_11_reg_1524[41] <= 1'b0;
tmp_11_reg_1524[42] <= 1'b0;
tmp_11_reg_1524[43] <= 1'b0;
tmp_11_reg_1524[44] <= 1'b0;
tmp_11_reg_1524[45] <= 1'b0;
tmp_11_reg_1524[46] <= 1'b0;
tmp_11_reg_1524[47] <= 1'b0;
tmp_11_reg_1524[48] <= 1'b0;
tmp_11_reg_1524[49] <= 1'b0;
tmp_11_reg_1524[50] <= 1'b0;
tmp_11_reg_1524[51] <= 1'b0;
tmp_11_reg_1524[52] <= 1'b0;
tmp_11_reg_1524[53] <= 1'b0;
tmp_11_reg_1524[54] <= 1'b0;
tmp_11_reg_1524[55] <= 1'b0;
tmp_11_reg_1524[56] <= 1'b0;
tmp_11_reg_1524[57] <= 1'b0;
tmp_11_reg_1524[58] <= 1'b0;
tmp_11_reg_1524[59] <= 1'b0;
tmp_11_reg_1524[60] <= 1'b0;
tmp_11_reg_1524[61] <= 1'b0;
tmp_11_reg_1524[62] <= 1'b0;
tmp_11_reg_1524[63] <= 1'b0;
end
always @ (ap_clk)
begin
ap_reg_ppstg_tmp_11_reg_1524_pp0_it1[0] <= 1'b1;
ap_reg_ppstg_tmp_11_reg_1524_pp0_it1[1] <= 1'b1;
ap_reg_ppstg_tmp_11_reg_1524_pp0_it1[14] <= 1'b0;
ap_reg_ppstg_tmp_11_reg_1524_pp0_it1[15] <= 1'b0;
ap_reg_ppstg_tmp_11_reg_1524_pp0_it1[16] <= 1'b0;
ap_reg_ppstg_tmp_11_reg_1524_pp0_it1[17] <= 1'b0;
ap_reg_ppstg_tmp_11_reg_1524_pp0_it1[18] <= 1'b0;
ap_reg_ppstg_tmp_11_reg_1524_pp0_it1[19] <= 1'b0;
ap_reg_ppstg_tmp_11_reg_1524_pp0_it1[20] <= 1'b0;
ap_reg_ppstg_tmp_11_reg_1524_pp0_it1[21] <= 1'b0;
ap_reg_ppstg_tmp_11_reg_1524_pp0_it1[22] <= 1'b0;
ap_reg_ppstg_tmp_11_reg_1524_pp0_it1[23] <= 1'b0;
ap_reg_ppstg_tmp_11_reg_1524_pp0_it1[24] <= 1'b0;
ap_reg_ppstg_tmp_11_reg_1524_pp0_it1[25] <= 1'b0;
ap_reg_ppstg_tmp_11_reg_1524_pp0_it1[26] <= 1'b0;
ap_reg_ppstg_tmp_11_reg_1524_pp0_it1[27] <= 1'b0;
ap_reg_ppstg_tmp_11_reg_1524_pp0_it1[28] <= 1'b0;
ap_reg_ppstg_tmp_11_reg_1524_pp0_it1[29] <= 1'b0;
ap_reg_ppstg_tmp_11_reg_1524_pp0_it1[30] <= 1'b0;
ap_reg_ppstg_tmp_11_reg_1524_pp0_it1[31] <= 1'b0;
ap_reg_ppstg_tmp_11_reg_1524_pp0_it1[32] <= 1'b0;
ap_reg_ppstg_tmp_11_reg_1524_pp0_it1[33] <= 1'b0;
ap_reg_ppstg_tmp_11_reg_1524_pp0_it1[34] <= 1'b0;
ap_reg_ppstg_tmp_11_reg_1524_pp0_it1[35] <= 1'b0;
ap_reg_ppstg_tmp_11_reg_1524_pp0_it1[36] <= 1'b0;
ap_reg_ppstg_tmp_11_reg_1524_pp0_it1[37] <= 1'b0;
ap_reg_ppstg_tmp_11_reg_1524_pp0_it1[38] <= 1'b0;
ap_reg_ppstg_tmp_11_reg_1524_pp0_it1[39] <= 1'b0;
ap_reg_ppstg_tmp_11_reg_1524_pp0_it1[40] <= 1'b0;
ap_reg_ppstg_tmp_11_reg_1524_pp0_it1[41] <= 1'b0;
ap_reg_ppstg_tmp_11_reg_1524_pp0_it1[42] <= 1'b0;
ap_reg_ppstg_tmp_11_reg_1524_pp0_it1[43] <= 1'b0;
ap_reg_ppstg_tmp_11_reg_1524_pp0_it1[44] <= 1'b0;
ap_reg_ppstg_tmp_11_reg_1524_pp0_it1[45] <= 1'b0;
ap_reg_ppstg_tmp_11_reg_1524_pp0_it1[46] <= 1'b0;
ap_reg_ppstg_tmp_11_reg_1524_pp0_it1[47] <= 1'b0;
ap_reg_ppstg_tmp_11_reg_1524_pp0_it1[48] <= 1'b0;
ap_reg_ppstg_tmp_11_reg_1524_pp0_it1[49] <= 1'b0;
ap_reg_ppstg_tmp_11_reg_1524_pp0_it1[50] <= 1'b0;
ap_reg_ppstg_tmp_11_reg_1524_pp0_it1[51] <= 1'b0;
ap_reg_ppstg_tmp_11_reg_1524_pp0_it1[52] <= 1'b0;
ap_reg_ppstg_tmp_11_reg_1524_pp0_it1[53] <= 1'b0;
ap_reg_ppstg_tmp_11_reg_1524_pp0_it1[54] <= 1'b0;
ap_reg_ppstg_tmp_11_reg_1524_pp0_it1[55] <= 1'b0;
ap_reg_ppstg_tmp_11_reg_1524_pp0_it1[56] <= 1'b0;
ap_reg_ppstg_tmp_11_reg_1524_pp0_it1[57] <= 1'b0;
ap_reg_ppstg_tmp_11_reg_1524_pp0_it1[58] <= 1'b0;
ap_reg_ppstg_tmp_11_reg_1524_pp0_it1[59] <= 1'b0;
ap_reg_ppstg_tmp_11_reg_1524_pp0_it1[60] <= 1'b0;
ap_reg_ppstg_tmp_11_reg_1524_pp0_it1[61] <= 1'b0;
ap_reg_ppstg_tmp_11_reg_1524_pp0_it1[62] <= 1'b0;
ap_reg_ppstg_tmp_11_reg_1524_pp0_it1[63] <= 1'b0;
end
always @ (ap_clk)
begin
tmp_13_reg_1536[14] <= 1'b0;
tmp_13_reg_1536[15] <= 1'b0;
tmp_13_reg_1536[16] <= 1'b0;
tmp_13_reg_1536[17] <= 1'b0;
tmp_13_reg_1536[18] <= 1'b0;
tmp_13_reg_1536[19] <= 1'b0;
tmp_13_reg_1536[20] <= 1'b0;
tmp_13_reg_1536[21] <= 1'b0;
tmp_13_reg_1536[22] <= 1'b0;
tmp_13_reg_1536[23] <= 1'b0;
tmp_13_reg_1536[24] <= 1'b0;
tmp_13_reg_1536[25] <= 1'b0;
tmp_13_reg_1536[26] <= 1'b0;
tmp_13_reg_1536[27] <= 1'b0;
tmp_13_reg_1536[28] <= 1'b0;
tmp_13_reg_1536[29] <= 1'b0;
tmp_13_reg_1536[30] <= 1'b0;
tmp_13_reg_1536[31] <= 1'b0;
tmp_13_reg_1536[32] <= 1'b0;
tmp_13_reg_1536[33] <= 1'b0;
tmp_13_reg_1536[34] <= 1'b0;
tmp_13_reg_1536[35] <= 1'b0;
tmp_13_reg_1536[36] <= 1'b0;
tmp_13_reg_1536[37] <= 1'b0;
tmp_13_reg_1536[38] <= 1'b0;
tmp_13_reg_1536[39] <= 1'b0;
tmp_13_reg_1536[40] <= 1'b0;
tmp_13_reg_1536[41] <= 1'b0;
tmp_13_reg_1536[42] <= 1'b0;
tmp_13_reg_1536[43] <= 1'b0;
tmp_13_reg_1536[44] <= 1'b0;
tmp_13_reg_1536[45] <= 1'b0;
tmp_13_reg_1536[46] <= 1'b0;
tmp_13_reg_1536[47] <= 1'b0;
tmp_13_reg_1536[48] <= 1'b0;
tmp_13_reg_1536[49] <= 1'b0;
tmp_13_reg_1536[50] <= 1'b0;
tmp_13_reg_1536[51] <= 1'b0;
tmp_13_reg_1536[52] <= 1'b0;
tmp_13_reg_1536[53] <= 1'b0;
tmp_13_reg_1536[54] <= 1'b0;
tmp_13_reg_1536[55] <= 1'b0;
tmp_13_reg_1536[56] <= 1'b0;
tmp_13_reg_1536[57] <= 1'b0;
tmp_13_reg_1536[58] <= 1'b0;
tmp_13_reg_1536[59] <= 1'b0;
tmp_13_reg_1536[60] <= 1'b0;
tmp_13_reg_1536[61] <= 1'b0;
tmp_13_reg_1536[62] <= 1'b0;
tmp_13_reg_1536[63] <= 1'b0;
end
always @ (ap_clk)
begin
ap_reg_ppstg_tmp_13_reg_1536_pp0_it1[14] <= 1'b0;
ap_reg_ppstg_tmp_13_reg_1536_pp0_it1[15] <= 1'b0;
ap_reg_ppstg_tmp_13_reg_1536_pp0_it1[16] <= 1'b0;
ap_reg_ppstg_tmp_13_reg_1536_pp0_it1[17] <= 1'b0;
ap_reg_ppstg_tmp_13_reg_1536_pp0_it1[18] <= 1'b0;
ap_reg_ppstg_tmp_13_reg_1536_pp0_it1[19] <= 1'b0;
ap_reg_ppstg_tmp_13_reg_1536_pp0_it1[20] <= 1'b0;
ap_reg_ppstg_tmp_13_reg_1536_pp0_it1[21] <= 1'b0;
ap_reg_ppstg_tmp_13_reg_1536_pp0_it1[22] <= 1'b0;
ap_reg_ppstg_tmp_13_reg_1536_pp0_it1[23] <= 1'b0;
ap_reg_ppstg_tmp_13_reg_1536_pp0_it1[24] <= 1'b0;
ap_reg_ppstg_tmp_13_reg_1536_pp0_it1[25] <= 1'b0;
ap_reg_ppstg_tmp_13_reg_1536_pp0_it1[26] <= 1'b0;
ap_reg_ppstg_tmp_13_reg_1536_pp0_it1[27] <= 1'b0;
ap_reg_ppstg_tmp_13_reg_1536_pp0_it1[28] <= 1'b0;
ap_reg_ppstg_tmp_13_reg_1536_pp0_it1[29] <= 1'b0;
ap_reg_ppstg_tmp_13_reg_1536_pp0_it1[30] <= 1'b0;
ap_reg_ppstg_tmp_13_reg_1536_pp0_it1[31] <= 1'b0;
ap_reg_ppstg_tmp_13_reg_1536_pp0_it1[32] <= 1'b0;
ap_reg_ppstg_tmp_13_reg_1536_pp0_it1[33] <= 1'b0;
ap_reg_ppstg_tmp_13_reg_1536_pp0_it1[34] <= 1'b0;
ap_reg_ppstg_tmp_13_reg_1536_pp0_it1[35] <= 1'b0;
ap_reg_ppstg_tmp_13_reg_1536_pp0_it1[36] <= 1'b0;
ap_reg_ppstg_tmp_13_reg_1536_pp0_it1[37] <= 1'b0;
ap_reg_ppstg_tmp_13_reg_1536_pp0_it1[38] <= 1'b0;
ap_reg_ppstg_tmp_13_reg_1536_pp0_it1[39] <= 1'b0;
ap_reg_ppstg_tmp_13_reg_1536_pp0_it1[40] <= 1'b0;
ap_reg_ppstg_tmp_13_reg_1536_pp0_it1[41] <= 1'b0;
ap_reg_ppstg_tmp_13_reg_1536_pp0_it1[42] <= 1'b0;
ap_reg_ppstg_tmp_13_reg_1536_pp0_it1[43] <= 1'b0;
ap_reg_ppstg_tmp_13_reg_1536_pp0_it1[44] <= 1'b0;
ap_reg_ppstg_tmp_13_reg_1536_pp0_it1[45] <= 1'b0;
ap_reg_ppstg_tmp_13_reg_1536_pp0_it1[46] <= 1'b0;
ap_reg_ppstg_tmp_13_reg_1536_pp0_it1[47] <= 1'b0;
ap_reg_ppstg_tmp_13_reg_1536_pp0_it1[48] <= 1'b0;
ap_reg_ppstg_tmp_13_reg_1536_pp0_it1[49] <= 1'b0;
ap_reg_ppstg_tmp_13_reg_1536_pp0_it1[50] <= 1'b0;
ap_reg_ppstg_tmp_13_reg_1536_pp0_it1[51] <= 1'b0;
ap_reg_ppstg_tmp_13_reg_1536_pp0_it1[52] <= 1'b0;
ap_reg_ppstg_tmp_13_reg_1536_pp0_it1[53] <= 1'b0;
ap_reg_ppstg_tmp_13_reg_1536_pp0_it1[54] <= 1'b0;
ap_reg_ppstg_tmp_13_reg_1536_pp0_it1[55] <= 1'b0;
ap_reg_ppstg_tmp_13_reg_1536_pp0_it1[56] <= 1'b0;
ap_reg_ppstg_tmp_13_reg_1536_pp0_it1[57] <= 1'b0;
ap_reg_ppstg_tmp_13_reg_1536_pp0_it1[58] <= 1'b0;
ap_reg_ppstg_tmp_13_reg_1536_pp0_it1[59] <= 1'b0;
ap_reg_ppstg_tmp_13_reg_1536_pp0_it1[60] <= 1'b0;
ap_reg_ppstg_tmp_13_reg_1536_pp0_it1[61] <= 1'b0;
ap_reg_ppstg_tmp_13_reg_1536_pp0_it1[62] <= 1'b0;
ap_reg_ppstg_tmp_13_reg_1536_pp0_it1[63] <= 1'b0;
end
always @ (ap_clk)
begin
tmp_15_reg_1548[0] <= 1'b1;
tmp_15_reg_1548[14] <= 1'b0;
tmp_15_reg_1548[15] <= 1'b0;
tmp_15_reg_1548[16] <= 1'b0;
tmp_15_reg_1548[17] <= 1'b0;
tmp_15_reg_1548[18] <= 1'b0;
tmp_15_reg_1548[19] <= 1'b0;
tmp_15_reg_1548[20] <= 1'b0;
tmp_15_reg_1548[21] <= 1'b0;
tmp_15_reg_1548[22] <= 1'b0;
tmp_15_reg_1548[23] <= 1'b0;
tmp_15_reg_1548[24] <= 1'b0;
tmp_15_reg_1548[25] <= 1'b0;
tmp_15_reg_1548[26] <= 1'b0;
tmp_15_reg_1548[27] <= 1'b0;
tmp_15_reg_1548[28] <= 1'b0;
tmp_15_reg_1548[29] <= 1'b0;
tmp_15_reg_1548[30] <= 1'b0;
tmp_15_reg_1548[31] <= 1'b0;
tmp_15_reg_1548[32] <= 1'b0;
tmp_15_reg_1548[33] <= 1'b0;
tmp_15_reg_1548[34] <= 1'b0;
tmp_15_reg_1548[35] <= 1'b0;
tmp_15_reg_1548[36] <= 1'b0;
tmp_15_reg_1548[37] <= 1'b0;
tmp_15_reg_1548[38] <= 1'b0;
tmp_15_reg_1548[39] <= 1'b0;
tmp_15_reg_1548[40] <= 1'b0;
tmp_15_reg_1548[41] <= 1'b0;
tmp_15_reg_1548[42] <= 1'b0;
tmp_15_reg_1548[43] <= 1'b0;
tmp_15_reg_1548[44] <= 1'b0;
tmp_15_reg_1548[45] <= 1'b0;
tmp_15_reg_1548[46] <= 1'b0;
tmp_15_reg_1548[47] <= 1'b0;
tmp_15_reg_1548[48] <= 1'b0;
tmp_15_reg_1548[49] <= 1'b0;
tmp_15_reg_1548[50] <= 1'b0;
tmp_15_reg_1548[51] <= 1'b0;
tmp_15_reg_1548[52] <= 1'b0;
tmp_15_reg_1548[53] <= 1'b0;
tmp_15_reg_1548[54] <= 1'b0;
tmp_15_reg_1548[55] <= 1'b0;
tmp_15_reg_1548[56] <= 1'b0;
tmp_15_reg_1548[57] <= 1'b0;
tmp_15_reg_1548[58] <= 1'b0;
tmp_15_reg_1548[59] <= 1'b0;
tmp_15_reg_1548[60] <= 1'b0;
tmp_15_reg_1548[61] <= 1'b0;
tmp_15_reg_1548[62] <= 1'b0;
tmp_15_reg_1548[63] <= 1'b0;
end
always @ (ap_clk)
begin
ap_reg_ppstg_tmp_15_reg_1548_pp0_it1[0] <= 1'b1;
ap_reg_ppstg_tmp_15_reg_1548_pp0_it1[14] <= 1'b0;
ap_reg_ppstg_tmp_15_reg_1548_pp0_it1[15] <= 1'b0;
ap_reg_ppstg_tmp_15_reg_1548_pp0_it1[16] <= 1'b0;
ap_reg_ppstg_tmp_15_reg_1548_pp0_it1[17] <= 1'b0;
ap_reg_ppstg_tmp_15_reg_1548_pp0_it1[18] <= 1'b0;
ap_reg_ppstg_tmp_15_reg_1548_pp0_it1[19] <= 1'b0;
ap_reg_ppstg_tmp_15_reg_1548_pp0_it1[20] <= 1'b0;
ap_reg_ppstg_tmp_15_reg_1548_pp0_it1[21] <= 1'b0;
ap_reg_ppstg_tmp_15_reg_1548_pp0_it1[22] <= 1'b0;
ap_reg_ppstg_tmp_15_reg_1548_pp0_it1[23] <= 1'b0;
ap_reg_ppstg_tmp_15_reg_1548_pp0_it1[24] <= 1'b0;
ap_reg_ppstg_tmp_15_reg_1548_pp0_it1[25] <= 1'b0;
ap_reg_ppstg_tmp_15_reg_1548_pp0_it1[26] <= 1'b0;
ap_reg_ppstg_tmp_15_reg_1548_pp0_it1[27] <= 1'b0;
ap_reg_ppstg_tmp_15_reg_1548_pp0_it1[28] <= 1'b0;
ap_reg_ppstg_tmp_15_reg_1548_pp0_it1[29] <= 1'b0;
ap_reg_ppstg_tmp_15_reg_1548_pp0_it1[30] <= 1'b0;
ap_reg_ppstg_tmp_15_reg_1548_pp0_it1[31] <= 1'b0;
ap_reg_ppstg_tmp_15_reg_1548_pp0_it1[32] <= 1'b0;
ap_reg_ppstg_tmp_15_reg_1548_pp0_it1[33] <= 1'b0;
ap_reg_ppstg_tmp_15_reg_1548_pp0_it1[34] <= 1'b0;
ap_reg_ppstg_tmp_15_reg_1548_pp0_it1[35] <= 1'b0;
ap_reg_ppstg_tmp_15_reg_1548_pp0_it1[36] <= 1'b0;
ap_reg_ppstg_tmp_15_reg_1548_pp0_it1[37] <= 1'b0;
ap_reg_ppstg_tmp_15_reg_1548_pp0_it1[38] <= 1'b0;
ap_reg_ppstg_tmp_15_reg_1548_pp0_it1[39] <= 1'b0;
ap_reg_ppstg_tmp_15_reg_1548_pp0_it1[40] <= 1'b0;
ap_reg_ppstg_tmp_15_reg_1548_pp0_it1[41] <= 1'b0;
ap_reg_ppstg_tmp_15_reg_1548_pp0_it1[42] <= 1'b0;
ap_reg_ppstg_tmp_15_reg_1548_pp0_it1[43] <= 1'b0;
ap_reg_ppstg_tmp_15_reg_1548_pp0_it1[44] <= 1'b0;
ap_reg_ppstg_tmp_15_reg_1548_pp0_it1[45] <= 1'b0;
ap_reg_ppstg_tmp_15_reg_1548_pp0_it1[46] <= 1'b0;
ap_reg_ppstg_tmp_15_reg_1548_pp0_it1[47] <= 1'b0;
ap_reg_ppstg_tmp_15_reg_1548_pp0_it1[48] <= 1'b0;
ap_reg_ppstg_tmp_15_reg_1548_pp0_it1[49] <= 1'b0;
ap_reg_ppstg_tmp_15_reg_1548_pp0_it1[50] <= 1'b0;
ap_reg_ppstg_tmp_15_reg_1548_pp0_it1[51] <= 1'b0;
ap_reg_ppstg_tmp_15_reg_1548_pp0_it1[52] <= 1'b0;
ap_reg_ppstg_tmp_15_reg_1548_pp0_it1[53] <= 1'b0;
ap_reg_ppstg_tmp_15_reg_1548_pp0_it1[54] <= 1'b0;
ap_reg_ppstg_tmp_15_reg_1548_pp0_it1[55] <= 1'b0;
ap_reg_ppstg_tmp_15_reg_1548_pp0_it1[56] <= 1'b0;
ap_reg_ppstg_tmp_15_reg_1548_pp0_it1[57] <= 1'b0;
ap_reg_ppstg_tmp_15_reg_1548_pp0_it1[58] <= 1'b0;
ap_reg_ppstg_tmp_15_reg_1548_pp0_it1[59] <= 1'b0;
ap_reg_ppstg_tmp_15_reg_1548_pp0_it1[60] <= 1'b0;
ap_reg_ppstg_tmp_15_reg_1548_pp0_it1[61] <= 1'b0;
ap_reg_ppstg_tmp_15_reg_1548_pp0_it1[62] <= 1'b0;
ap_reg_ppstg_tmp_15_reg_1548_pp0_it1[63] <= 1'b0;
end
always @ (ap_clk)
begin
tmp_17_reg_1560[14] <= 1'b0;
tmp_17_reg_1560[15] <= 1'b0;
tmp_17_reg_1560[16] <= 1'b0;
tmp_17_reg_1560[17] <= 1'b0;
tmp_17_reg_1560[18] <= 1'b0;
tmp_17_reg_1560[19] <= 1'b0;
tmp_17_reg_1560[20] <= 1'b0;
tmp_17_reg_1560[21] <= 1'b0;
tmp_17_reg_1560[22] <= 1'b0;
tmp_17_reg_1560[23] <= 1'b0;
tmp_17_reg_1560[24] <= 1'b0;
tmp_17_reg_1560[25] <= 1'b0;
tmp_17_reg_1560[26] <= 1'b0;
tmp_17_reg_1560[27] <= 1'b0;
tmp_17_reg_1560[28] <= 1'b0;
tmp_17_reg_1560[29] <= 1'b0;
tmp_17_reg_1560[30] <= 1'b0;
tmp_17_reg_1560[31] <= 1'b0;
tmp_17_reg_1560[32] <= 1'b0;
tmp_17_reg_1560[33] <= 1'b0;
tmp_17_reg_1560[34] <= 1'b0;
tmp_17_reg_1560[35] <= 1'b0;
tmp_17_reg_1560[36] <= 1'b0;
tmp_17_reg_1560[37] <= 1'b0;
tmp_17_reg_1560[38] <= 1'b0;
tmp_17_reg_1560[39] <= 1'b0;
tmp_17_reg_1560[40] <= 1'b0;
tmp_17_reg_1560[41] <= 1'b0;
tmp_17_reg_1560[42] <= 1'b0;
tmp_17_reg_1560[43] <= 1'b0;
tmp_17_reg_1560[44] <= 1'b0;
tmp_17_reg_1560[45] <= 1'b0;
tmp_17_reg_1560[46] <= 1'b0;
tmp_17_reg_1560[47] <= 1'b0;
tmp_17_reg_1560[48] <= 1'b0;
tmp_17_reg_1560[49] <= 1'b0;
tmp_17_reg_1560[50] <= 1'b0;
tmp_17_reg_1560[51] <= 1'b0;
tmp_17_reg_1560[52] <= 1'b0;
tmp_17_reg_1560[53] <= 1'b0;
tmp_17_reg_1560[54] <= 1'b0;
tmp_17_reg_1560[55] <= 1'b0;
tmp_17_reg_1560[56] <= 1'b0;
tmp_17_reg_1560[57] <= 1'b0;
tmp_17_reg_1560[58] <= 1'b0;
tmp_17_reg_1560[59] <= 1'b0;
tmp_17_reg_1560[60] <= 1'b0;
tmp_17_reg_1560[61] <= 1'b0;
tmp_17_reg_1560[62] <= 1'b0;
tmp_17_reg_1560[63] <= 1'b0;
end
always @ (ap_clk)
begin
ap_reg_ppstg_tmp_17_reg_1560_pp0_it1[14] <= 1'b0;
ap_reg_ppstg_tmp_17_reg_1560_pp0_it1[15] <= 1'b0;
ap_reg_ppstg_tmp_17_reg_1560_pp0_it1[16] <= 1'b0;
ap_reg_ppstg_tmp_17_reg_1560_pp0_it1[17] <= 1'b0;
ap_reg_ppstg_tmp_17_reg_1560_pp0_it1[18] <= 1'b0;
ap_reg_ppstg_tmp_17_reg_1560_pp0_it1[19] <= 1'b0;
ap_reg_ppstg_tmp_17_reg_1560_pp0_it1[20] <= 1'b0;
ap_reg_ppstg_tmp_17_reg_1560_pp0_it1[21] <= 1'b0;
ap_reg_ppstg_tmp_17_reg_1560_pp0_it1[22] <= 1'b0;
ap_reg_ppstg_tmp_17_reg_1560_pp0_it1[23] <= 1'b0;
ap_reg_ppstg_tmp_17_reg_1560_pp0_it1[24] <= 1'b0;
ap_reg_ppstg_tmp_17_reg_1560_pp0_it1[25] <= 1'b0;
ap_reg_ppstg_tmp_17_reg_1560_pp0_it1[26] <= 1'b0;
ap_reg_ppstg_tmp_17_reg_1560_pp0_it1[27] <= 1'b0;
ap_reg_ppstg_tmp_17_reg_1560_pp0_it1[28] <= 1'b0;
ap_reg_ppstg_tmp_17_reg_1560_pp0_it1[29] <= 1'b0;
ap_reg_ppstg_tmp_17_reg_1560_pp0_it1[30] <= 1'b0;
ap_reg_ppstg_tmp_17_reg_1560_pp0_it1[31] <= 1'b0;
ap_reg_ppstg_tmp_17_reg_1560_pp0_it1[32] <= 1'b0;
ap_reg_ppstg_tmp_17_reg_1560_pp0_it1[33] <= 1'b0;
ap_reg_ppstg_tmp_17_reg_1560_pp0_it1[34] <= 1'b0;
ap_reg_ppstg_tmp_17_reg_1560_pp0_it1[35] <= 1'b0;
ap_reg_ppstg_tmp_17_reg_1560_pp0_it1[36] <= 1'b0;
ap_reg_ppstg_tmp_17_reg_1560_pp0_it1[37] <= 1'b0;
ap_reg_ppstg_tmp_17_reg_1560_pp0_it1[38] <= 1'b0;
ap_reg_ppstg_tmp_17_reg_1560_pp0_it1[39] <= 1'b0;
ap_reg_ppstg_tmp_17_reg_1560_pp0_it1[40] <= 1'b0;
ap_reg_ppstg_tmp_17_reg_1560_pp0_it1[41] <= 1'b0;
ap_reg_ppstg_tmp_17_reg_1560_pp0_it1[42] <= 1'b0;
ap_reg_ppstg_tmp_17_reg_1560_pp0_it1[43] <= 1'b0;
ap_reg_ppstg_tmp_17_reg_1560_pp0_it1[44] <= 1'b0;
ap_reg_ppstg_tmp_17_reg_1560_pp0_it1[45] <= 1'b0;
ap_reg_ppstg_tmp_17_reg_1560_pp0_it1[46] <= 1'b0;
ap_reg_ppstg_tmp_17_reg_1560_pp0_it1[47] <= 1'b0;
ap_reg_ppstg_tmp_17_reg_1560_pp0_it1[48] <= 1'b0;
ap_reg_ppstg_tmp_17_reg_1560_pp0_it1[49] <= 1'b0;
ap_reg_ppstg_tmp_17_reg_1560_pp0_it1[50] <= 1'b0;
ap_reg_ppstg_tmp_17_reg_1560_pp0_it1[51] <= 1'b0;
ap_reg_ppstg_tmp_17_reg_1560_pp0_it1[52] <= 1'b0;
ap_reg_ppstg_tmp_17_reg_1560_pp0_it1[53] <= 1'b0;
ap_reg_ppstg_tmp_17_reg_1560_pp0_it1[54] <= 1'b0;
ap_reg_ppstg_tmp_17_reg_1560_pp0_it1[55] <= 1'b0;
ap_reg_ppstg_tmp_17_reg_1560_pp0_it1[56] <= 1'b0;
ap_reg_ppstg_tmp_17_reg_1560_pp0_it1[57] <= 1'b0;
ap_reg_ppstg_tmp_17_reg_1560_pp0_it1[58] <= 1'b0;
ap_reg_ppstg_tmp_17_reg_1560_pp0_it1[59] <= 1'b0;
ap_reg_ppstg_tmp_17_reg_1560_pp0_it1[60] <= 1'b0;
ap_reg_ppstg_tmp_17_reg_1560_pp0_it1[61] <= 1'b0;
ap_reg_ppstg_tmp_17_reg_1560_pp0_it1[62] <= 1'b0;
ap_reg_ppstg_tmp_17_reg_1560_pp0_it1[63] <= 1'b0;
end
always @ (ap_clk)
begin
b_addr8_reg_1572[0] <= 1'b1;
b_addr8_reg_1572[1] <= 1'b1;
b_addr8_reg_1572[2] <= 1'b1;
end
always @ (ap_clk)
begin
tmp_19_reg_1582[0] <= 1'b1;
tmp_19_reg_1582[1] <= 1'b1;
tmp_19_reg_1582[2] <= 1'b1;
tmp_19_reg_1582[14] <= 1'b0;
tmp_19_reg_1582[15] <= 1'b0;
tmp_19_reg_1582[16] <= 1'b0;
tmp_19_reg_1582[17] <= 1'b0;
tmp_19_reg_1582[18] <= 1'b0;
tmp_19_reg_1582[19] <= 1'b0;
tmp_19_reg_1582[20] <= 1'b0;
tmp_19_reg_1582[21] <= 1'b0;
tmp_19_reg_1582[22] <= 1'b0;
tmp_19_reg_1582[23] <= 1'b0;
tmp_19_reg_1582[24] <= 1'b0;
tmp_19_reg_1582[25] <= 1'b0;
tmp_19_reg_1582[26] <= 1'b0;
tmp_19_reg_1582[27] <= 1'b0;
tmp_19_reg_1582[28] <= 1'b0;
tmp_19_reg_1582[29] <= 1'b0;
tmp_19_reg_1582[30] <= 1'b0;
tmp_19_reg_1582[31] <= 1'b0;
tmp_19_reg_1582[32] <= 1'b0;
tmp_19_reg_1582[33] <= 1'b0;
tmp_19_reg_1582[34] <= 1'b0;
tmp_19_reg_1582[35] <= 1'b0;
tmp_19_reg_1582[36] <= 1'b0;
tmp_19_reg_1582[37] <= 1'b0;
tmp_19_reg_1582[38] <= 1'b0;
tmp_19_reg_1582[39] <= 1'b0;
tmp_19_reg_1582[40] <= 1'b0;
tmp_19_reg_1582[41] <= 1'b0;
tmp_19_reg_1582[42] <= 1'b0;
tmp_19_reg_1582[43] <= 1'b0;
tmp_19_reg_1582[44] <= 1'b0;
tmp_19_reg_1582[45] <= 1'b0;
tmp_19_reg_1582[46] <= 1'b0;
tmp_19_reg_1582[47] <= 1'b0;
tmp_19_reg_1582[48] <= 1'b0;
tmp_19_reg_1582[49] <= 1'b0;
tmp_19_reg_1582[50] <= 1'b0;
tmp_19_reg_1582[51] <= 1'b0;
tmp_19_reg_1582[52] <= 1'b0;
tmp_19_reg_1582[53] <= 1'b0;
tmp_19_reg_1582[54] <= 1'b0;
tmp_19_reg_1582[55] <= 1'b0;
tmp_19_reg_1582[56] <= 1'b0;
tmp_19_reg_1582[57] <= 1'b0;
tmp_19_reg_1582[58] <= 1'b0;
tmp_19_reg_1582[59] <= 1'b0;
tmp_19_reg_1582[60] <= 1'b0;
tmp_19_reg_1582[61] <= 1'b0;
tmp_19_reg_1582[62] <= 1'b0;
tmp_19_reg_1582[63] <= 1'b0;
end
always @ (ap_clk)
begin
ap_reg_ppstg_tmp_19_reg_1582_pp0_it1[0] <= 1'b1;
ap_reg_ppstg_tmp_19_reg_1582_pp0_it1[1] <= 1'b1;
ap_reg_ppstg_tmp_19_reg_1582_pp0_it1[2] <= 1'b1;
ap_reg_ppstg_tmp_19_reg_1582_pp0_it1[14] <= 1'b0;
ap_reg_ppstg_tmp_19_reg_1582_pp0_it1[15] <= 1'b0;
ap_reg_ppstg_tmp_19_reg_1582_pp0_it1[16] <= 1'b0;
ap_reg_ppstg_tmp_19_reg_1582_pp0_it1[17] <= 1'b0;
ap_reg_ppstg_tmp_19_reg_1582_pp0_it1[18] <= 1'b0;
ap_reg_ppstg_tmp_19_reg_1582_pp0_it1[19] <= 1'b0;
ap_reg_ppstg_tmp_19_reg_1582_pp0_it1[20] <= 1'b0;
ap_reg_ppstg_tmp_19_reg_1582_pp0_it1[21] <= 1'b0;
ap_reg_ppstg_tmp_19_reg_1582_pp0_it1[22] <= 1'b0;
ap_reg_ppstg_tmp_19_reg_1582_pp0_it1[23] <= 1'b0;
ap_reg_ppstg_tmp_19_reg_1582_pp0_it1[24] <= 1'b0;
ap_reg_ppstg_tmp_19_reg_1582_pp0_it1[25] <= 1'b0;
ap_reg_ppstg_tmp_19_reg_1582_pp0_it1[26] <= 1'b0;
ap_reg_ppstg_tmp_19_reg_1582_pp0_it1[27] <= 1'b0;
ap_reg_ppstg_tmp_19_reg_1582_pp0_it1[28] <= 1'b0;
ap_reg_ppstg_tmp_19_reg_1582_pp0_it1[29] <= 1'b0;
ap_reg_ppstg_tmp_19_reg_1582_pp0_it1[30] <= 1'b0;
ap_reg_ppstg_tmp_19_reg_1582_pp0_it1[31] <= 1'b0;
ap_reg_ppstg_tmp_19_reg_1582_pp0_it1[32] <= 1'b0;
ap_reg_ppstg_tmp_19_reg_1582_pp0_it1[33] <= 1'b0;
ap_reg_ppstg_tmp_19_reg_1582_pp0_it1[34] <= 1'b0;
ap_reg_ppstg_tmp_19_reg_1582_pp0_it1[35] <= 1'b0;
ap_reg_ppstg_tmp_19_reg_1582_pp0_it1[36] <= 1'b0;
ap_reg_ppstg_tmp_19_reg_1582_pp0_it1[37] <= 1'b0;
ap_reg_ppstg_tmp_19_reg_1582_pp0_it1[38] <= 1'b0;
ap_reg_ppstg_tmp_19_reg_1582_pp0_it1[39] <= 1'b0;
ap_reg_ppstg_tmp_19_reg_1582_pp0_it1[40] <= 1'b0;
ap_reg_ppstg_tmp_19_reg_1582_pp0_it1[41] <= 1'b0;
ap_reg_ppstg_tmp_19_reg_1582_pp0_it1[42] <= 1'b0;
ap_reg_ppstg_tmp_19_reg_1582_pp0_it1[43] <= 1'b0;
ap_reg_ppstg_tmp_19_reg_1582_pp0_it1[44] <= 1'b0;
ap_reg_ppstg_tmp_19_reg_1582_pp0_it1[45] <= 1'b0;
ap_reg_ppstg_tmp_19_reg_1582_pp0_it1[46] <= 1'b0;
ap_reg_ppstg_tmp_19_reg_1582_pp0_it1[47] <= 1'b0;
ap_reg_ppstg_tmp_19_reg_1582_pp0_it1[48] <= 1'b0;
ap_reg_ppstg_tmp_19_reg_1582_pp0_it1[49] <= 1'b0;
ap_reg_ppstg_tmp_19_reg_1582_pp0_it1[50] <= 1'b0;
ap_reg_ppstg_tmp_19_reg_1582_pp0_it1[51] <= 1'b0;
ap_reg_ppstg_tmp_19_reg_1582_pp0_it1[52] <= 1'b0;
ap_reg_ppstg_tmp_19_reg_1582_pp0_it1[53] <= 1'b0;
ap_reg_ppstg_tmp_19_reg_1582_pp0_it1[54] <= 1'b0;
ap_reg_ppstg_tmp_19_reg_1582_pp0_it1[55] <= 1'b0;
ap_reg_ppstg_tmp_19_reg_1582_pp0_it1[56] <= 1'b0;
ap_reg_ppstg_tmp_19_reg_1582_pp0_it1[57] <= 1'b0;
ap_reg_ppstg_tmp_19_reg_1582_pp0_it1[58] <= 1'b0;
ap_reg_ppstg_tmp_19_reg_1582_pp0_it1[59] <= 1'b0;
ap_reg_ppstg_tmp_19_reg_1582_pp0_it1[60] <= 1'b0;
ap_reg_ppstg_tmp_19_reg_1582_pp0_it1[61] <= 1'b0;
ap_reg_ppstg_tmp_19_reg_1582_pp0_it1[62] <= 1'b0;
ap_reg_ppstg_tmp_19_reg_1582_pp0_it1[63] <= 1'b0;
end
always @ (ap_clk)
begin
b_addr9_cast_reg_1629[0] <= 1'b0;
b_addr9_cast_reg_1629[1] <= 1'b0;
b_addr9_cast_reg_1629[2] <= 1'b0;
b_addr9_cast_reg_1629[3] <= 1'b0;
b_addr9_cast_reg_1629[4] <= 1'b0;
b_addr9_cast_reg_1629[5] <= 1'b0;
b_addr9_cast_reg_1629[13] <= 1'b0;
end
always @ (ap_clk)
begin
tmp_30_reg_1640[14] <= 1'b0;
tmp_30_reg_1640[15] <= 1'b0;
tmp_30_reg_1640[16] <= 1'b0;
tmp_30_reg_1640[17] <= 1'b0;
tmp_30_reg_1640[18] <= 1'b0;
tmp_30_reg_1640[19] <= 1'b0;
tmp_30_reg_1640[20] <= 1'b0;
tmp_30_reg_1640[21] <= 1'b0;
tmp_30_reg_1640[22] <= 1'b0;
tmp_30_reg_1640[23] <= 1'b0;
tmp_30_reg_1640[24] <= 1'b0;
tmp_30_reg_1640[25] <= 1'b0;
tmp_30_reg_1640[26] <= 1'b0;
tmp_30_reg_1640[27] <= 1'b0;
tmp_30_reg_1640[28] <= 1'b0;
tmp_30_reg_1640[29] <= 1'b0;
tmp_30_reg_1640[30] <= 1'b0;
tmp_30_reg_1640[31] <= 1'b0;
tmp_30_reg_1640[32] <= 1'b0;
tmp_30_reg_1640[33] <= 1'b0;
tmp_30_reg_1640[34] <= 1'b0;
tmp_30_reg_1640[35] <= 1'b0;
tmp_30_reg_1640[36] <= 1'b0;
tmp_30_reg_1640[37] <= 1'b0;
tmp_30_reg_1640[38] <= 1'b0;
tmp_30_reg_1640[39] <= 1'b0;
tmp_30_reg_1640[40] <= 1'b0;
tmp_30_reg_1640[41] <= 1'b0;
tmp_30_reg_1640[42] <= 1'b0;
tmp_30_reg_1640[43] <= 1'b0;
tmp_30_reg_1640[44] <= 1'b0;
tmp_30_reg_1640[45] <= 1'b0;
tmp_30_reg_1640[46] <= 1'b0;
tmp_30_reg_1640[47] <= 1'b0;
tmp_30_reg_1640[48] <= 1'b0;
tmp_30_reg_1640[49] <= 1'b0;
tmp_30_reg_1640[50] <= 1'b0;
tmp_30_reg_1640[51] <= 1'b0;
tmp_30_reg_1640[52] <= 1'b0;
tmp_30_reg_1640[53] <= 1'b0;
tmp_30_reg_1640[54] <= 1'b0;
tmp_30_reg_1640[55] <= 1'b0;
tmp_30_reg_1640[56] <= 1'b0;
tmp_30_reg_1640[57] <= 1'b0;
tmp_30_reg_1640[58] <= 1'b0;
tmp_30_reg_1640[59] <= 1'b0;
tmp_30_reg_1640[60] <= 1'b0;
tmp_30_reg_1640[61] <= 1'b0;
tmp_30_reg_1640[62] <= 1'b0;
tmp_30_reg_1640[63] <= 1'b0;
end
always @ (ap_clk)
begin
ap_reg_ppstg_tmp_30_reg_1640_pp1_it1[14] <= 1'b0;
ap_reg_ppstg_tmp_30_reg_1640_pp1_it1[15] <= 1'b0;
ap_reg_ppstg_tmp_30_reg_1640_pp1_it1[16] <= 1'b0;
ap_reg_ppstg_tmp_30_reg_1640_pp1_it1[17] <= 1'b0;
ap_reg_ppstg_tmp_30_reg_1640_pp1_it1[18] <= 1'b0;
ap_reg_ppstg_tmp_30_reg_1640_pp1_it1[19] <= 1'b0;
ap_reg_ppstg_tmp_30_reg_1640_pp1_it1[20] <= 1'b0;
ap_reg_ppstg_tmp_30_reg_1640_pp1_it1[21] <= 1'b0;
ap_reg_ppstg_tmp_30_reg_1640_pp1_it1[22] <= 1'b0;
ap_reg_ppstg_tmp_30_reg_1640_pp1_it1[23] <= 1'b0;
ap_reg_ppstg_tmp_30_reg_1640_pp1_it1[24] <= 1'b0;
ap_reg_ppstg_tmp_30_reg_1640_pp1_it1[25] <= 1'b0;
ap_reg_ppstg_tmp_30_reg_1640_pp1_it1[26] <= 1'b0;
ap_reg_ppstg_tmp_30_reg_1640_pp1_it1[27] <= 1'b0;
ap_reg_ppstg_tmp_30_reg_1640_pp1_it1[28] <= 1'b0;
ap_reg_ppstg_tmp_30_reg_1640_pp1_it1[29] <= 1'b0;
ap_reg_ppstg_tmp_30_reg_1640_pp1_it1[30] <= 1'b0;
ap_reg_ppstg_tmp_30_reg_1640_pp1_it1[31] <= 1'b0;
ap_reg_ppstg_tmp_30_reg_1640_pp1_it1[32] <= 1'b0;
ap_reg_ppstg_tmp_30_reg_1640_pp1_it1[33] <= 1'b0;
ap_reg_ppstg_tmp_30_reg_1640_pp1_it1[34] <= 1'b0;
ap_reg_ppstg_tmp_30_reg_1640_pp1_it1[35] <= 1'b0;
ap_reg_ppstg_tmp_30_reg_1640_pp1_it1[36] <= 1'b0;
ap_reg_ppstg_tmp_30_reg_1640_pp1_it1[37] <= 1'b0;
ap_reg_ppstg_tmp_30_reg_1640_pp1_it1[38] <= 1'b0;
ap_reg_ppstg_tmp_30_reg_1640_pp1_it1[39] <= 1'b0;
ap_reg_ppstg_tmp_30_reg_1640_pp1_it1[40] <= 1'b0;
ap_reg_ppstg_tmp_30_reg_1640_pp1_it1[41] <= 1'b0;
ap_reg_ppstg_tmp_30_reg_1640_pp1_it1[42] <= 1'b0;
ap_reg_ppstg_tmp_30_reg_1640_pp1_it1[43] <= 1'b0;
ap_reg_ppstg_tmp_30_reg_1640_pp1_it1[44] <= 1'b0;
ap_reg_ppstg_tmp_30_reg_1640_pp1_it1[45] <= 1'b0;
ap_reg_ppstg_tmp_30_reg_1640_pp1_it1[46] <= 1'b0;
ap_reg_ppstg_tmp_30_reg_1640_pp1_it1[47] <= 1'b0;
ap_reg_ppstg_tmp_30_reg_1640_pp1_it1[48] <= 1'b0;
ap_reg_ppstg_tmp_30_reg_1640_pp1_it1[49] <= 1'b0;
ap_reg_ppstg_tmp_30_reg_1640_pp1_it1[50] <= 1'b0;
ap_reg_ppstg_tmp_30_reg_1640_pp1_it1[51] <= 1'b0;
ap_reg_ppstg_tmp_30_reg_1640_pp1_it1[52] <= 1'b0;
ap_reg_ppstg_tmp_30_reg_1640_pp1_it1[53] <= 1'b0;
ap_reg_ppstg_tmp_30_reg_1640_pp1_it1[54] <= 1'b0;
ap_reg_ppstg_tmp_30_reg_1640_pp1_it1[55] <= 1'b0;
ap_reg_ppstg_tmp_30_reg_1640_pp1_it1[56] <= 1'b0;
ap_reg_ppstg_tmp_30_reg_1640_pp1_it1[57] <= 1'b0;
ap_reg_ppstg_tmp_30_reg_1640_pp1_it1[58] <= 1'b0;
ap_reg_ppstg_tmp_30_reg_1640_pp1_it1[59] <= 1'b0;
ap_reg_ppstg_tmp_30_reg_1640_pp1_it1[60] <= 1'b0;
ap_reg_ppstg_tmp_30_reg_1640_pp1_it1[61] <= 1'b0;
ap_reg_ppstg_tmp_30_reg_1640_pp1_it1[62] <= 1'b0;
ap_reg_ppstg_tmp_30_reg_1640_pp1_it1[63] <= 1'b0;
end
always @ (ap_clk)
begin
ap_reg_ppstg_tmp_30_reg_1640_pp1_it2[14] <= 1'b0;
ap_reg_ppstg_tmp_30_reg_1640_pp1_it2[15] <= 1'b0;
ap_reg_ppstg_tmp_30_reg_1640_pp1_it2[16] <= 1'b0;
ap_reg_ppstg_tmp_30_reg_1640_pp1_it2[17] <= 1'b0;
ap_reg_ppstg_tmp_30_reg_1640_pp1_it2[18] <= 1'b0;
ap_reg_ppstg_tmp_30_reg_1640_pp1_it2[19] <= 1'b0;
ap_reg_ppstg_tmp_30_reg_1640_pp1_it2[20] <= 1'b0;
ap_reg_ppstg_tmp_30_reg_1640_pp1_it2[21] <= 1'b0;
ap_reg_ppstg_tmp_30_reg_1640_pp1_it2[22] <= 1'b0;
ap_reg_ppstg_tmp_30_reg_1640_pp1_it2[23] <= 1'b0;
ap_reg_ppstg_tmp_30_reg_1640_pp1_it2[24] <= 1'b0;
ap_reg_ppstg_tmp_30_reg_1640_pp1_it2[25] <= 1'b0;
ap_reg_ppstg_tmp_30_reg_1640_pp1_it2[26] <= 1'b0;
ap_reg_ppstg_tmp_30_reg_1640_pp1_it2[27] <= 1'b0;
ap_reg_ppstg_tmp_30_reg_1640_pp1_it2[28] <= 1'b0;
ap_reg_ppstg_tmp_30_reg_1640_pp1_it2[29] <= 1'b0;
ap_reg_ppstg_tmp_30_reg_1640_pp1_it2[30] <= 1'b0;
ap_reg_ppstg_tmp_30_reg_1640_pp1_it2[31] <= 1'b0;
ap_reg_ppstg_tmp_30_reg_1640_pp1_it2[32] <= 1'b0;
ap_reg_ppstg_tmp_30_reg_1640_pp1_it2[33] <= 1'b0;
ap_reg_ppstg_tmp_30_reg_1640_pp1_it2[34] <= 1'b0;
ap_reg_ppstg_tmp_30_reg_1640_pp1_it2[35] <= 1'b0;
ap_reg_ppstg_tmp_30_reg_1640_pp1_it2[36] <= 1'b0;
ap_reg_ppstg_tmp_30_reg_1640_pp1_it2[37] <= 1'b0;
ap_reg_ppstg_tmp_30_reg_1640_pp1_it2[38] <= 1'b0;
ap_reg_ppstg_tmp_30_reg_1640_pp1_it2[39] <= 1'b0;
ap_reg_ppstg_tmp_30_reg_1640_pp1_it2[40] <= 1'b0;
ap_reg_ppstg_tmp_30_reg_1640_pp1_it2[41] <= 1'b0;
ap_reg_ppstg_tmp_30_reg_1640_pp1_it2[42] <= 1'b0;
ap_reg_ppstg_tmp_30_reg_1640_pp1_it2[43] <= 1'b0;
ap_reg_ppstg_tmp_30_reg_1640_pp1_it2[44] <= 1'b0;
ap_reg_ppstg_tmp_30_reg_1640_pp1_it2[45] <= 1'b0;
ap_reg_ppstg_tmp_30_reg_1640_pp1_it2[46] <= 1'b0;
ap_reg_ppstg_tmp_30_reg_1640_pp1_it2[47] <= 1'b0;
ap_reg_ppstg_tmp_30_reg_1640_pp1_it2[48] <= 1'b0;
ap_reg_ppstg_tmp_30_reg_1640_pp1_it2[49] <= 1'b0;
ap_reg_ppstg_tmp_30_reg_1640_pp1_it2[50] <= 1'b0;
ap_reg_ppstg_tmp_30_reg_1640_pp1_it2[51] <= 1'b0;
ap_reg_ppstg_tmp_30_reg_1640_pp1_it2[52] <= 1'b0;
ap_reg_ppstg_tmp_30_reg_1640_pp1_it2[53] <= 1'b0;
ap_reg_ppstg_tmp_30_reg_1640_pp1_it2[54] <= 1'b0;
ap_reg_ppstg_tmp_30_reg_1640_pp1_it2[55] <= 1'b0;
ap_reg_ppstg_tmp_30_reg_1640_pp1_it2[56] <= 1'b0;
ap_reg_ppstg_tmp_30_reg_1640_pp1_it2[57] <= 1'b0;
ap_reg_ppstg_tmp_30_reg_1640_pp1_it2[58] <= 1'b0;
ap_reg_ppstg_tmp_30_reg_1640_pp1_it2[59] <= 1'b0;
ap_reg_ppstg_tmp_30_reg_1640_pp1_it2[60] <= 1'b0;
ap_reg_ppstg_tmp_30_reg_1640_pp1_it2[61] <= 1'b0;
ap_reg_ppstg_tmp_30_reg_1640_pp1_it2[62] <= 1'b0;
ap_reg_ppstg_tmp_30_reg_1640_pp1_it2[63] <= 1'b0;
end
always @ (ap_clk)
begin
tmp_33_reg_1662[0] <= 1'b1;
tmp_33_reg_1662[14] <= 1'b0;
tmp_33_reg_1662[15] <= 1'b0;
tmp_33_reg_1662[16] <= 1'b0;
tmp_33_reg_1662[17] <= 1'b0;
tmp_33_reg_1662[18] <= 1'b0;
tmp_33_reg_1662[19] <= 1'b0;
tmp_33_reg_1662[20] <= 1'b0;
tmp_33_reg_1662[21] <= 1'b0;
tmp_33_reg_1662[22] <= 1'b0;
tmp_33_reg_1662[23] <= 1'b0;
tmp_33_reg_1662[24] <= 1'b0;
tmp_33_reg_1662[25] <= 1'b0;
tmp_33_reg_1662[26] <= 1'b0;
tmp_33_reg_1662[27] <= 1'b0;
tmp_33_reg_1662[28] <= 1'b0;
tmp_33_reg_1662[29] <= 1'b0;
tmp_33_reg_1662[30] <= 1'b0;
tmp_33_reg_1662[31] <= 1'b0;
tmp_33_reg_1662[32] <= 1'b0;
tmp_33_reg_1662[33] <= 1'b0;
tmp_33_reg_1662[34] <= 1'b0;
tmp_33_reg_1662[35] <= 1'b0;
tmp_33_reg_1662[36] <= 1'b0;
tmp_33_reg_1662[37] <= 1'b0;
tmp_33_reg_1662[38] <= 1'b0;
tmp_33_reg_1662[39] <= 1'b0;
tmp_33_reg_1662[40] <= 1'b0;
tmp_33_reg_1662[41] <= 1'b0;
tmp_33_reg_1662[42] <= 1'b0;
tmp_33_reg_1662[43] <= 1'b0;
tmp_33_reg_1662[44] <= 1'b0;
tmp_33_reg_1662[45] <= 1'b0;
tmp_33_reg_1662[46] <= 1'b0;
tmp_33_reg_1662[47] <= 1'b0;
tmp_33_reg_1662[48] <= 1'b0;
tmp_33_reg_1662[49] <= 1'b0;
tmp_33_reg_1662[50] <= 1'b0;
tmp_33_reg_1662[51] <= 1'b0;
tmp_33_reg_1662[52] <= 1'b0;
tmp_33_reg_1662[53] <= 1'b0;
tmp_33_reg_1662[54] <= 1'b0;
tmp_33_reg_1662[55] <= 1'b0;
tmp_33_reg_1662[56] <= 1'b0;
tmp_33_reg_1662[57] <= 1'b0;
tmp_33_reg_1662[58] <= 1'b0;
tmp_33_reg_1662[59] <= 1'b0;
tmp_33_reg_1662[60] <= 1'b0;
tmp_33_reg_1662[61] <= 1'b0;
tmp_33_reg_1662[62] <= 1'b0;
tmp_33_reg_1662[63] <= 1'b0;
end
always @ (ap_clk)
begin
ap_reg_ppstg_tmp_33_reg_1662_pp1_it1[0] <= 1'b1;
ap_reg_ppstg_tmp_33_reg_1662_pp1_it1[14] <= 1'b0;
ap_reg_ppstg_tmp_33_reg_1662_pp1_it1[15] <= 1'b0;
ap_reg_ppstg_tmp_33_reg_1662_pp1_it1[16] <= 1'b0;
ap_reg_ppstg_tmp_33_reg_1662_pp1_it1[17] <= 1'b0;
ap_reg_ppstg_tmp_33_reg_1662_pp1_it1[18] <= 1'b0;
ap_reg_ppstg_tmp_33_reg_1662_pp1_it1[19] <= 1'b0;
ap_reg_ppstg_tmp_33_reg_1662_pp1_it1[20] <= 1'b0;
ap_reg_ppstg_tmp_33_reg_1662_pp1_it1[21] <= 1'b0;
ap_reg_ppstg_tmp_33_reg_1662_pp1_it1[22] <= 1'b0;
ap_reg_ppstg_tmp_33_reg_1662_pp1_it1[23] <= 1'b0;
ap_reg_ppstg_tmp_33_reg_1662_pp1_it1[24] <= 1'b0;
ap_reg_ppstg_tmp_33_reg_1662_pp1_it1[25] <= 1'b0;
ap_reg_ppstg_tmp_33_reg_1662_pp1_it1[26] <= 1'b0;
ap_reg_ppstg_tmp_33_reg_1662_pp1_it1[27] <= 1'b0;
ap_reg_ppstg_tmp_33_reg_1662_pp1_it1[28] <= 1'b0;
ap_reg_ppstg_tmp_33_reg_1662_pp1_it1[29] <= 1'b0;
ap_reg_ppstg_tmp_33_reg_1662_pp1_it1[30] <= 1'b0;
ap_reg_ppstg_tmp_33_reg_1662_pp1_it1[31] <= 1'b0;
ap_reg_ppstg_tmp_33_reg_1662_pp1_it1[32] <= 1'b0;
ap_reg_ppstg_tmp_33_reg_1662_pp1_it1[33] <= 1'b0;
ap_reg_ppstg_tmp_33_reg_1662_pp1_it1[34] <= 1'b0;
ap_reg_ppstg_tmp_33_reg_1662_pp1_it1[35] <= 1'b0;
ap_reg_ppstg_tmp_33_reg_1662_pp1_it1[36] <= 1'b0;
ap_reg_ppstg_tmp_33_reg_1662_pp1_it1[37] <= 1'b0;
ap_reg_ppstg_tmp_33_reg_1662_pp1_it1[38] <= 1'b0;
ap_reg_ppstg_tmp_33_reg_1662_pp1_it1[39] <= 1'b0;
ap_reg_ppstg_tmp_33_reg_1662_pp1_it1[40] <= 1'b0;
ap_reg_ppstg_tmp_33_reg_1662_pp1_it1[41] <= 1'b0;
ap_reg_ppstg_tmp_33_reg_1662_pp1_it1[42] <= 1'b0;
ap_reg_ppstg_tmp_33_reg_1662_pp1_it1[43] <= 1'b0;
ap_reg_ppstg_tmp_33_reg_1662_pp1_it1[44] <= 1'b0;
ap_reg_ppstg_tmp_33_reg_1662_pp1_it1[45] <= 1'b0;
ap_reg_ppstg_tmp_33_reg_1662_pp1_it1[46] <= 1'b0;
ap_reg_ppstg_tmp_33_reg_1662_pp1_it1[47] <= 1'b0;
ap_reg_ppstg_tmp_33_reg_1662_pp1_it1[48] <= 1'b0;
ap_reg_ppstg_tmp_33_reg_1662_pp1_it1[49] <= 1'b0;
ap_reg_ppstg_tmp_33_reg_1662_pp1_it1[50] <= 1'b0;
ap_reg_ppstg_tmp_33_reg_1662_pp1_it1[51] <= 1'b0;
ap_reg_ppstg_tmp_33_reg_1662_pp1_it1[52] <= 1'b0;
ap_reg_ppstg_tmp_33_reg_1662_pp1_it1[53] <= 1'b0;
ap_reg_ppstg_tmp_33_reg_1662_pp1_it1[54] <= 1'b0;
ap_reg_ppstg_tmp_33_reg_1662_pp1_it1[55] <= 1'b0;
ap_reg_ppstg_tmp_33_reg_1662_pp1_it1[56] <= 1'b0;
ap_reg_ppstg_tmp_33_reg_1662_pp1_it1[57] <= 1'b0;
ap_reg_ppstg_tmp_33_reg_1662_pp1_it1[58] <= 1'b0;
ap_reg_ppstg_tmp_33_reg_1662_pp1_it1[59] <= 1'b0;
ap_reg_ppstg_tmp_33_reg_1662_pp1_it1[60] <= 1'b0;
ap_reg_ppstg_tmp_33_reg_1662_pp1_it1[61] <= 1'b0;
ap_reg_ppstg_tmp_33_reg_1662_pp1_it1[62] <= 1'b0;
ap_reg_ppstg_tmp_33_reg_1662_pp1_it1[63] <= 1'b0;
end
always @ (ap_clk)
begin
ap_reg_ppstg_tmp_33_reg_1662_pp1_it2[0] <= 1'b1;
ap_reg_ppstg_tmp_33_reg_1662_pp1_it2[14] <= 1'b0;
ap_reg_ppstg_tmp_33_reg_1662_pp1_it2[15] <= 1'b0;
ap_reg_ppstg_tmp_33_reg_1662_pp1_it2[16] <= 1'b0;
ap_reg_ppstg_tmp_33_reg_1662_pp1_it2[17] <= 1'b0;
ap_reg_ppstg_tmp_33_reg_1662_pp1_it2[18] <= 1'b0;
ap_reg_ppstg_tmp_33_reg_1662_pp1_it2[19] <= 1'b0;
ap_reg_ppstg_tmp_33_reg_1662_pp1_it2[20] <= 1'b0;
ap_reg_ppstg_tmp_33_reg_1662_pp1_it2[21] <= 1'b0;
ap_reg_ppstg_tmp_33_reg_1662_pp1_it2[22] <= 1'b0;
ap_reg_ppstg_tmp_33_reg_1662_pp1_it2[23] <= 1'b0;
ap_reg_ppstg_tmp_33_reg_1662_pp1_it2[24] <= 1'b0;
ap_reg_ppstg_tmp_33_reg_1662_pp1_it2[25] <= 1'b0;
ap_reg_ppstg_tmp_33_reg_1662_pp1_it2[26] <= 1'b0;
ap_reg_ppstg_tmp_33_reg_1662_pp1_it2[27] <= 1'b0;
ap_reg_ppstg_tmp_33_reg_1662_pp1_it2[28] <= 1'b0;
ap_reg_ppstg_tmp_33_reg_1662_pp1_it2[29] <= 1'b0;
ap_reg_ppstg_tmp_33_reg_1662_pp1_it2[30] <= 1'b0;
ap_reg_ppstg_tmp_33_reg_1662_pp1_it2[31] <= 1'b0;
ap_reg_ppstg_tmp_33_reg_1662_pp1_it2[32] <= 1'b0;
ap_reg_ppstg_tmp_33_reg_1662_pp1_it2[33] <= 1'b0;
ap_reg_ppstg_tmp_33_reg_1662_pp1_it2[34] <= 1'b0;
ap_reg_ppstg_tmp_33_reg_1662_pp1_it2[35] <= 1'b0;
ap_reg_ppstg_tmp_33_reg_1662_pp1_it2[36] <= 1'b0;
ap_reg_ppstg_tmp_33_reg_1662_pp1_it2[37] <= 1'b0;
ap_reg_ppstg_tmp_33_reg_1662_pp1_it2[38] <= 1'b0;
ap_reg_ppstg_tmp_33_reg_1662_pp1_it2[39] <= 1'b0;
ap_reg_ppstg_tmp_33_reg_1662_pp1_it2[40] <= 1'b0;
ap_reg_ppstg_tmp_33_reg_1662_pp1_it2[41] <= 1'b0;
ap_reg_ppstg_tmp_33_reg_1662_pp1_it2[42] <= 1'b0;
ap_reg_ppstg_tmp_33_reg_1662_pp1_it2[43] <= 1'b0;
ap_reg_ppstg_tmp_33_reg_1662_pp1_it2[44] <= 1'b0;
ap_reg_ppstg_tmp_33_reg_1662_pp1_it2[45] <= 1'b0;
ap_reg_ppstg_tmp_33_reg_1662_pp1_it2[46] <= 1'b0;
ap_reg_ppstg_tmp_33_reg_1662_pp1_it2[47] <= 1'b0;
ap_reg_ppstg_tmp_33_reg_1662_pp1_it2[48] <= 1'b0;
ap_reg_ppstg_tmp_33_reg_1662_pp1_it2[49] <= 1'b0;
ap_reg_ppstg_tmp_33_reg_1662_pp1_it2[50] <= 1'b0;
ap_reg_ppstg_tmp_33_reg_1662_pp1_it2[51] <= 1'b0;
ap_reg_ppstg_tmp_33_reg_1662_pp1_it2[52] <= 1'b0;
ap_reg_ppstg_tmp_33_reg_1662_pp1_it2[53] <= 1'b0;
ap_reg_ppstg_tmp_33_reg_1662_pp1_it2[54] <= 1'b0;
ap_reg_ppstg_tmp_33_reg_1662_pp1_it2[55] <= 1'b0;
ap_reg_ppstg_tmp_33_reg_1662_pp1_it2[56] <= 1'b0;
ap_reg_ppstg_tmp_33_reg_1662_pp1_it2[57] <= 1'b0;
ap_reg_ppstg_tmp_33_reg_1662_pp1_it2[58] <= 1'b0;
ap_reg_ppstg_tmp_33_reg_1662_pp1_it2[59] <= 1'b0;
ap_reg_ppstg_tmp_33_reg_1662_pp1_it2[60] <= 1'b0;
ap_reg_ppstg_tmp_33_reg_1662_pp1_it2[61] <= 1'b0;
ap_reg_ppstg_tmp_33_reg_1662_pp1_it2[62] <= 1'b0;
ap_reg_ppstg_tmp_33_reg_1662_pp1_it2[63] <= 1'b0;
end
always @ (ap_clk)
begin
tmp_36_reg_1679[14] <= 1'b0;
tmp_36_reg_1679[15] <= 1'b0;
tmp_36_reg_1679[16] <= 1'b0;
tmp_36_reg_1679[17] <= 1'b0;
tmp_36_reg_1679[18] <= 1'b0;
tmp_36_reg_1679[19] <= 1'b0;
tmp_36_reg_1679[20] <= 1'b0;
tmp_36_reg_1679[21] <= 1'b0;
tmp_36_reg_1679[22] <= 1'b0;
tmp_36_reg_1679[23] <= 1'b0;
tmp_36_reg_1679[24] <= 1'b0;
tmp_36_reg_1679[25] <= 1'b0;
tmp_36_reg_1679[26] <= 1'b0;
tmp_36_reg_1679[27] <= 1'b0;
tmp_36_reg_1679[28] <= 1'b0;
tmp_36_reg_1679[29] <= 1'b0;
tmp_36_reg_1679[30] <= 1'b0;
tmp_36_reg_1679[31] <= 1'b0;
tmp_36_reg_1679[32] <= 1'b0;
tmp_36_reg_1679[33] <= 1'b0;
tmp_36_reg_1679[34] <= 1'b0;
tmp_36_reg_1679[35] <= 1'b0;
tmp_36_reg_1679[36] <= 1'b0;
tmp_36_reg_1679[37] <= 1'b0;
tmp_36_reg_1679[38] <= 1'b0;
tmp_36_reg_1679[39] <= 1'b0;
tmp_36_reg_1679[40] <= 1'b0;
tmp_36_reg_1679[41] <= 1'b0;
tmp_36_reg_1679[42] <= 1'b0;
tmp_36_reg_1679[43] <= 1'b0;
tmp_36_reg_1679[44] <= 1'b0;
tmp_36_reg_1679[45] <= 1'b0;
tmp_36_reg_1679[46] <= 1'b0;
tmp_36_reg_1679[47] <= 1'b0;
tmp_36_reg_1679[48] <= 1'b0;
tmp_36_reg_1679[49] <= 1'b0;
tmp_36_reg_1679[50] <= 1'b0;
tmp_36_reg_1679[51] <= 1'b0;
tmp_36_reg_1679[52] <= 1'b0;
tmp_36_reg_1679[53] <= 1'b0;
tmp_36_reg_1679[54] <= 1'b0;
tmp_36_reg_1679[55] <= 1'b0;
tmp_36_reg_1679[56] <= 1'b0;
tmp_36_reg_1679[57] <= 1'b0;
tmp_36_reg_1679[58] <= 1'b0;
tmp_36_reg_1679[59] <= 1'b0;
tmp_36_reg_1679[60] <= 1'b0;
tmp_36_reg_1679[61] <= 1'b0;
tmp_36_reg_1679[62] <= 1'b0;
tmp_36_reg_1679[63] <= 1'b0;
end
always @ (ap_clk)
begin
ap_reg_ppstg_tmp_36_reg_1679_pp1_it1[14] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_1679_pp1_it1[15] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_1679_pp1_it1[16] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_1679_pp1_it1[17] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_1679_pp1_it1[18] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_1679_pp1_it1[19] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_1679_pp1_it1[20] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_1679_pp1_it1[21] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_1679_pp1_it1[22] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_1679_pp1_it1[23] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_1679_pp1_it1[24] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_1679_pp1_it1[25] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_1679_pp1_it1[26] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_1679_pp1_it1[27] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_1679_pp1_it1[28] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_1679_pp1_it1[29] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_1679_pp1_it1[30] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_1679_pp1_it1[31] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_1679_pp1_it1[32] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_1679_pp1_it1[33] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_1679_pp1_it1[34] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_1679_pp1_it1[35] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_1679_pp1_it1[36] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_1679_pp1_it1[37] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_1679_pp1_it1[38] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_1679_pp1_it1[39] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_1679_pp1_it1[40] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_1679_pp1_it1[41] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_1679_pp1_it1[42] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_1679_pp1_it1[43] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_1679_pp1_it1[44] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_1679_pp1_it1[45] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_1679_pp1_it1[46] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_1679_pp1_it1[47] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_1679_pp1_it1[48] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_1679_pp1_it1[49] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_1679_pp1_it1[50] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_1679_pp1_it1[51] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_1679_pp1_it1[52] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_1679_pp1_it1[53] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_1679_pp1_it1[54] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_1679_pp1_it1[55] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_1679_pp1_it1[56] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_1679_pp1_it1[57] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_1679_pp1_it1[58] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_1679_pp1_it1[59] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_1679_pp1_it1[60] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_1679_pp1_it1[61] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_1679_pp1_it1[62] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_1679_pp1_it1[63] <= 1'b0;
end
always @ (ap_clk)
begin
ap_reg_ppstg_tmp_36_reg_1679_pp1_it2[14] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_1679_pp1_it2[15] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_1679_pp1_it2[16] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_1679_pp1_it2[17] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_1679_pp1_it2[18] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_1679_pp1_it2[19] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_1679_pp1_it2[20] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_1679_pp1_it2[21] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_1679_pp1_it2[22] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_1679_pp1_it2[23] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_1679_pp1_it2[24] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_1679_pp1_it2[25] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_1679_pp1_it2[26] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_1679_pp1_it2[27] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_1679_pp1_it2[28] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_1679_pp1_it2[29] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_1679_pp1_it2[30] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_1679_pp1_it2[31] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_1679_pp1_it2[32] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_1679_pp1_it2[33] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_1679_pp1_it2[34] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_1679_pp1_it2[35] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_1679_pp1_it2[36] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_1679_pp1_it2[37] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_1679_pp1_it2[38] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_1679_pp1_it2[39] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_1679_pp1_it2[40] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_1679_pp1_it2[41] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_1679_pp1_it2[42] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_1679_pp1_it2[43] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_1679_pp1_it2[44] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_1679_pp1_it2[45] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_1679_pp1_it2[46] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_1679_pp1_it2[47] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_1679_pp1_it2[48] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_1679_pp1_it2[49] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_1679_pp1_it2[50] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_1679_pp1_it2[51] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_1679_pp1_it2[52] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_1679_pp1_it2[53] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_1679_pp1_it2[54] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_1679_pp1_it2[55] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_1679_pp1_it2[56] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_1679_pp1_it2[57] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_1679_pp1_it2[58] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_1679_pp1_it2[59] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_1679_pp1_it2[60] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_1679_pp1_it2[61] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_1679_pp1_it2[62] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_1679_pp1_it2[63] <= 1'b0;
end
always @ (ap_clk)
begin
tmp_39_reg_1706[0] <= 1'b1;
tmp_39_reg_1706[1] <= 1'b1;
tmp_39_reg_1706[14] <= 1'b0;
tmp_39_reg_1706[15] <= 1'b0;
tmp_39_reg_1706[16] <= 1'b0;
tmp_39_reg_1706[17] <= 1'b0;
tmp_39_reg_1706[18] <= 1'b0;
tmp_39_reg_1706[19] <= 1'b0;
tmp_39_reg_1706[20] <= 1'b0;
tmp_39_reg_1706[21] <= 1'b0;
tmp_39_reg_1706[22] <= 1'b0;
tmp_39_reg_1706[23] <= 1'b0;
tmp_39_reg_1706[24] <= 1'b0;
tmp_39_reg_1706[25] <= 1'b0;
tmp_39_reg_1706[26] <= 1'b0;
tmp_39_reg_1706[27] <= 1'b0;
tmp_39_reg_1706[28] <= 1'b0;
tmp_39_reg_1706[29] <= 1'b0;
tmp_39_reg_1706[30] <= 1'b0;
tmp_39_reg_1706[31] <= 1'b0;
tmp_39_reg_1706[32] <= 1'b0;
tmp_39_reg_1706[33] <= 1'b0;
tmp_39_reg_1706[34] <= 1'b0;
tmp_39_reg_1706[35] <= 1'b0;
tmp_39_reg_1706[36] <= 1'b0;
tmp_39_reg_1706[37] <= 1'b0;
tmp_39_reg_1706[38] <= 1'b0;
tmp_39_reg_1706[39] <= 1'b0;
tmp_39_reg_1706[40] <= 1'b0;
tmp_39_reg_1706[41] <= 1'b0;
tmp_39_reg_1706[42] <= 1'b0;
tmp_39_reg_1706[43] <= 1'b0;
tmp_39_reg_1706[44] <= 1'b0;
tmp_39_reg_1706[45] <= 1'b0;
tmp_39_reg_1706[46] <= 1'b0;
tmp_39_reg_1706[47] <= 1'b0;
tmp_39_reg_1706[48] <= 1'b0;
tmp_39_reg_1706[49] <= 1'b0;
tmp_39_reg_1706[50] <= 1'b0;
tmp_39_reg_1706[51] <= 1'b0;
tmp_39_reg_1706[52] <= 1'b0;
tmp_39_reg_1706[53] <= 1'b0;
tmp_39_reg_1706[54] <= 1'b0;
tmp_39_reg_1706[55] <= 1'b0;
tmp_39_reg_1706[56] <= 1'b0;
tmp_39_reg_1706[57] <= 1'b0;
tmp_39_reg_1706[58] <= 1'b0;
tmp_39_reg_1706[59] <= 1'b0;
tmp_39_reg_1706[60] <= 1'b0;
tmp_39_reg_1706[61] <= 1'b0;
tmp_39_reg_1706[62] <= 1'b0;
tmp_39_reg_1706[63] <= 1'b0;
end
always @ (ap_clk)
begin
ap_reg_ppstg_tmp_39_reg_1706_pp1_it1[0] <= 1'b1;
ap_reg_ppstg_tmp_39_reg_1706_pp1_it1[1] <= 1'b1;
ap_reg_ppstg_tmp_39_reg_1706_pp1_it1[14] <= 1'b0;
ap_reg_ppstg_tmp_39_reg_1706_pp1_it1[15] <= 1'b0;
ap_reg_ppstg_tmp_39_reg_1706_pp1_it1[16] <= 1'b0;
ap_reg_ppstg_tmp_39_reg_1706_pp1_it1[17] <= 1'b0;
ap_reg_ppstg_tmp_39_reg_1706_pp1_it1[18] <= 1'b0;
ap_reg_ppstg_tmp_39_reg_1706_pp1_it1[19] <= 1'b0;
ap_reg_ppstg_tmp_39_reg_1706_pp1_it1[20] <= 1'b0;
ap_reg_ppstg_tmp_39_reg_1706_pp1_it1[21] <= 1'b0;
ap_reg_ppstg_tmp_39_reg_1706_pp1_it1[22] <= 1'b0;
ap_reg_ppstg_tmp_39_reg_1706_pp1_it1[23] <= 1'b0;
ap_reg_ppstg_tmp_39_reg_1706_pp1_it1[24] <= 1'b0;
ap_reg_ppstg_tmp_39_reg_1706_pp1_it1[25] <= 1'b0;
ap_reg_ppstg_tmp_39_reg_1706_pp1_it1[26] <= 1'b0;
ap_reg_ppstg_tmp_39_reg_1706_pp1_it1[27] <= 1'b0;
ap_reg_ppstg_tmp_39_reg_1706_pp1_it1[28] <= 1'b0;
ap_reg_ppstg_tmp_39_reg_1706_pp1_it1[29] <= 1'b0;
ap_reg_ppstg_tmp_39_reg_1706_pp1_it1[30] <= 1'b0;
ap_reg_ppstg_tmp_39_reg_1706_pp1_it1[31] <= 1'b0;
ap_reg_ppstg_tmp_39_reg_1706_pp1_it1[32] <= 1'b0;
ap_reg_ppstg_tmp_39_reg_1706_pp1_it1[33] <= 1'b0;
ap_reg_ppstg_tmp_39_reg_1706_pp1_it1[34] <= 1'b0;
ap_reg_ppstg_tmp_39_reg_1706_pp1_it1[35] <= 1'b0;
ap_reg_ppstg_tmp_39_reg_1706_pp1_it1[36] <= 1'b0;
ap_reg_ppstg_tmp_39_reg_1706_pp1_it1[37] <= 1'b0;
ap_reg_ppstg_tmp_39_reg_1706_pp1_it1[38] <= 1'b0;
ap_reg_ppstg_tmp_39_reg_1706_pp1_it1[39] <= 1'b0;
ap_reg_ppstg_tmp_39_reg_1706_pp1_it1[40] <= 1'b0;
ap_reg_ppstg_tmp_39_reg_1706_pp1_it1[41] <= 1'b0;
ap_reg_ppstg_tmp_39_reg_1706_pp1_it1[42] <= 1'b0;
ap_reg_ppstg_tmp_39_reg_1706_pp1_it1[43] <= 1'b0;
ap_reg_ppstg_tmp_39_reg_1706_pp1_it1[44] <= 1'b0;
ap_reg_ppstg_tmp_39_reg_1706_pp1_it1[45] <= 1'b0;
ap_reg_ppstg_tmp_39_reg_1706_pp1_it1[46] <= 1'b0;
ap_reg_ppstg_tmp_39_reg_1706_pp1_it1[47] <= 1'b0;
ap_reg_ppstg_tmp_39_reg_1706_pp1_it1[48] <= 1'b0;
ap_reg_ppstg_tmp_39_reg_1706_pp1_it1[49] <= 1'b0;
ap_reg_ppstg_tmp_39_reg_1706_pp1_it1[50] <= 1'b0;
ap_reg_ppstg_tmp_39_reg_1706_pp1_it1[51] <= 1'b0;
ap_reg_ppstg_tmp_39_reg_1706_pp1_it1[52] <= 1'b0;
ap_reg_ppstg_tmp_39_reg_1706_pp1_it1[53] <= 1'b0;
ap_reg_ppstg_tmp_39_reg_1706_pp1_it1[54] <= 1'b0;
ap_reg_ppstg_tmp_39_reg_1706_pp1_it1[55] <= 1'b0;
ap_reg_ppstg_tmp_39_reg_1706_pp1_it1[56] <= 1'b0;
ap_reg_ppstg_tmp_39_reg_1706_pp1_it1[57] <= 1'b0;
ap_reg_ppstg_tmp_39_reg_1706_pp1_it1[58] <= 1'b0;
ap_reg_ppstg_tmp_39_reg_1706_pp1_it1[59] <= 1'b0;
ap_reg_ppstg_tmp_39_reg_1706_pp1_it1[60] <= 1'b0;
ap_reg_ppstg_tmp_39_reg_1706_pp1_it1[61] <= 1'b0;
ap_reg_ppstg_tmp_39_reg_1706_pp1_it1[62] <= 1'b0;
ap_reg_ppstg_tmp_39_reg_1706_pp1_it1[63] <= 1'b0;
end
always @ (ap_clk)
begin
ap_reg_ppstg_tmp_39_reg_1706_pp1_it2[0] <= 1'b1;
ap_reg_ppstg_tmp_39_reg_1706_pp1_it2[1] <= 1'b1;
ap_reg_ppstg_tmp_39_reg_1706_pp1_it2[14] <= 1'b0;
ap_reg_ppstg_tmp_39_reg_1706_pp1_it2[15] <= 1'b0;
ap_reg_ppstg_tmp_39_reg_1706_pp1_it2[16] <= 1'b0;
ap_reg_ppstg_tmp_39_reg_1706_pp1_it2[17] <= 1'b0;
ap_reg_ppstg_tmp_39_reg_1706_pp1_it2[18] <= 1'b0;
ap_reg_ppstg_tmp_39_reg_1706_pp1_it2[19] <= 1'b0;
ap_reg_ppstg_tmp_39_reg_1706_pp1_it2[20] <= 1'b0;
ap_reg_ppstg_tmp_39_reg_1706_pp1_it2[21] <= 1'b0;
ap_reg_ppstg_tmp_39_reg_1706_pp1_it2[22] <= 1'b0;
ap_reg_ppstg_tmp_39_reg_1706_pp1_it2[23] <= 1'b0;
ap_reg_ppstg_tmp_39_reg_1706_pp1_it2[24] <= 1'b0;
ap_reg_ppstg_tmp_39_reg_1706_pp1_it2[25] <= 1'b0;
ap_reg_ppstg_tmp_39_reg_1706_pp1_it2[26] <= 1'b0;
ap_reg_ppstg_tmp_39_reg_1706_pp1_it2[27] <= 1'b0;
ap_reg_ppstg_tmp_39_reg_1706_pp1_it2[28] <= 1'b0;
ap_reg_ppstg_tmp_39_reg_1706_pp1_it2[29] <= 1'b0;
ap_reg_ppstg_tmp_39_reg_1706_pp1_it2[30] <= 1'b0;
ap_reg_ppstg_tmp_39_reg_1706_pp1_it2[31] <= 1'b0;
ap_reg_ppstg_tmp_39_reg_1706_pp1_it2[32] <= 1'b0;
ap_reg_ppstg_tmp_39_reg_1706_pp1_it2[33] <= 1'b0;
ap_reg_ppstg_tmp_39_reg_1706_pp1_it2[34] <= 1'b0;
ap_reg_ppstg_tmp_39_reg_1706_pp1_it2[35] <= 1'b0;
ap_reg_ppstg_tmp_39_reg_1706_pp1_it2[36] <= 1'b0;
ap_reg_ppstg_tmp_39_reg_1706_pp1_it2[37] <= 1'b0;
ap_reg_ppstg_tmp_39_reg_1706_pp1_it2[38] <= 1'b0;
ap_reg_ppstg_tmp_39_reg_1706_pp1_it2[39] <= 1'b0;
ap_reg_ppstg_tmp_39_reg_1706_pp1_it2[40] <= 1'b0;
ap_reg_ppstg_tmp_39_reg_1706_pp1_it2[41] <= 1'b0;
ap_reg_ppstg_tmp_39_reg_1706_pp1_it2[42] <= 1'b0;
ap_reg_ppstg_tmp_39_reg_1706_pp1_it2[43] <= 1'b0;
ap_reg_ppstg_tmp_39_reg_1706_pp1_it2[44] <= 1'b0;
ap_reg_ppstg_tmp_39_reg_1706_pp1_it2[45] <= 1'b0;
ap_reg_ppstg_tmp_39_reg_1706_pp1_it2[46] <= 1'b0;
ap_reg_ppstg_tmp_39_reg_1706_pp1_it2[47] <= 1'b0;
ap_reg_ppstg_tmp_39_reg_1706_pp1_it2[48] <= 1'b0;
ap_reg_ppstg_tmp_39_reg_1706_pp1_it2[49] <= 1'b0;
ap_reg_ppstg_tmp_39_reg_1706_pp1_it2[50] <= 1'b0;
ap_reg_ppstg_tmp_39_reg_1706_pp1_it2[51] <= 1'b0;
ap_reg_ppstg_tmp_39_reg_1706_pp1_it2[52] <= 1'b0;
ap_reg_ppstg_tmp_39_reg_1706_pp1_it2[53] <= 1'b0;
ap_reg_ppstg_tmp_39_reg_1706_pp1_it2[54] <= 1'b0;
ap_reg_ppstg_tmp_39_reg_1706_pp1_it2[55] <= 1'b0;
ap_reg_ppstg_tmp_39_reg_1706_pp1_it2[56] <= 1'b0;
ap_reg_ppstg_tmp_39_reg_1706_pp1_it2[57] <= 1'b0;
ap_reg_ppstg_tmp_39_reg_1706_pp1_it2[58] <= 1'b0;
ap_reg_ppstg_tmp_39_reg_1706_pp1_it2[59] <= 1'b0;
ap_reg_ppstg_tmp_39_reg_1706_pp1_it2[60] <= 1'b0;
ap_reg_ppstg_tmp_39_reg_1706_pp1_it2[61] <= 1'b0;
ap_reg_ppstg_tmp_39_reg_1706_pp1_it2[62] <= 1'b0;
ap_reg_ppstg_tmp_39_reg_1706_pp1_it2[63] <= 1'b0;
end
always @ (ap_clk)
begin
tmp_42_reg_1723[14] <= 1'b0;
tmp_42_reg_1723[15] <= 1'b0;
tmp_42_reg_1723[16] <= 1'b0;
tmp_42_reg_1723[17] <= 1'b0;
tmp_42_reg_1723[18] <= 1'b0;
tmp_42_reg_1723[19] <= 1'b0;
tmp_42_reg_1723[20] <= 1'b0;
tmp_42_reg_1723[21] <= 1'b0;
tmp_42_reg_1723[22] <= 1'b0;
tmp_42_reg_1723[23] <= 1'b0;
tmp_42_reg_1723[24] <= 1'b0;
tmp_42_reg_1723[25] <= 1'b0;
tmp_42_reg_1723[26] <= 1'b0;
tmp_42_reg_1723[27] <= 1'b0;
tmp_42_reg_1723[28] <= 1'b0;
tmp_42_reg_1723[29] <= 1'b0;
tmp_42_reg_1723[30] <= 1'b0;
tmp_42_reg_1723[31] <= 1'b0;
tmp_42_reg_1723[32] <= 1'b0;
tmp_42_reg_1723[33] <= 1'b0;
tmp_42_reg_1723[34] <= 1'b0;
tmp_42_reg_1723[35] <= 1'b0;
tmp_42_reg_1723[36] <= 1'b0;
tmp_42_reg_1723[37] <= 1'b0;
tmp_42_reg_1723[38] <= 1'b0;
tmp_42_reg_1723[39] <= 1'b0;
tmp_42_reg_1723[40] <= 1'b0;
tmp_42_reg_1723[41] <= 1'b0;
tmp_42_reg_1723[42] <= 1'b0;
tmp_42_reg_1723[43] <= 1'b0;
tmp_42_reg_1723[44] <= 1'b0;
tmp_42_reg_1723[45] <= 1'b0;
tmp_42_reg_1723[46] <= 1'b0;
tmp_42_reg_1723[47] <= 1'b0;
tmp_42_reg_1723[48] <= 1'b0;
tmp_42_reg_1723[49] <= 1'b0;
tmp_42_reg_1723[50] <= 1'b0;
tmp_42_reg_1723[51] <= 1'b0;
tmp_42_reg_1723[52] <= 1'b0;
tmp_42_reg_1723[53] <= 1'b0;
tmp_42_reg_1723[54] <= 1'b0;
tmp_42_reg_1723[55] <= 1'b0;
tmp_42_reg_1723[56] <= 1'b0;
tmp_42_reg_1723[57] <= 1'b0;
tmp_42_reg_1723[58] <= 1'b0;
tmp_42_reg_1723[59] <= 1'b0;
tmp_42_reg_1723[60] <= 1'b0;
tmp_42_reg_1723[61] <= 1'b0;
tmp_42_reg_1723[62] <= 1'b0;
tmp_42_reg_1723[63] <= 1'b0;
end
always @ (ap_clk)
begin
ap_reg_ppstg_tmp_42_reg_1723_pp1_it1[14] <= 1'b0;
ap_reg_ppstg_tmp_42_reg_1723_pp1_it1[15] <= 1'b0;
ap_reg_ppstg_tmp_42_reg_1723_pp1_it1[16] <= 1'b0;
ap_reg_ppstg_tmp_42_reg_1723_pp1_it1[17] <= 1'b0;
ap_reg_ppstg_tmp_42_reg_1723_pp1_it1[18] <= 1'b0;
ap_reg_ppstg_tmp_42_reg_1723_pp1_it1[19] <= 1'b0;
ap_reg_ppstg_tmp_42_reg_1723_pp1_it1[20] <= 1'b0;
ap_reg_ppstg_tmp_42_reg_1723_pp1_it1[21] <= 1'b0;
ap_reg_ppstg_tmp_42_reg_1723_pp1_it1[22] <= 1'b0;
ap_reg_ppstg_tmp_42_reg_1723_pp1_it1[23] <= 1'b0;
ap_reg_ppstg_tmp_42_reg_1723_pp1_it1[24] <= 1'b0;
ap_reg_ppstg_tmp_42_reg_1723_pp1_it1[25] <= 1'b0;
ap_reg_ppstg_tmp_42_reg_1723_pp1_it1[26] <= 1'b0;
ap_reg_ppstg_tmp_42_reg_1723_pp1_it1[27] <= 1'b0;
ap_reg_ppstg_tmp_42_reg_1723_pp1_it1[28] <= 1'b0;
ap_reg_ppstg_tmp_42_reg_1723_pp1_it1[29] <= 1'b0;
ap_reg_ppstg_tmp_42_reg_1723_pp1_it1[30] <= 1'b0;
ap_reg_ppstg_tmp_42_reg_1723_pp1_it1[31] <= 1'b0;
ap_reg_ppstg_tmp_42_reg_1723_pp1_it1[32] <= 1'b0;
ap_reg_ppstg_tmp_42_reg_1723_pp1_it1[33] <= 1'b0;
ap_reg_ppstg_tmp_42_reg_1723_pp1_it1[34] <= 1'b0;
ap_reg_ppstg_tmp_42_reg_1723_pp1_it1[35] <= 1'b0;
ap_reg_ppstg_tmp_42_reg_1723_pp1_it1[36] <= 1'b0;
ap_reg_ppstg_tmp_42_reg_1723_pp1_it1[37] <= 1'b0;
ap_reg_ppstg_tmp_42_reg_1723_pp1_it1[38] <= 1'b0;
ap_reg_ppstg_tmp_42_reg_1723_pp1_it1[39] <= 1'b0;
ap_reg_ppstg_tmp_42_reg_1723_pp1_it1[40] <= 1'b0;
ap_reg_ppstg_tmp_42_reg_1723_pp1_it1[41] <= 1'b0;
ap_reg_ppstg_tmp_42_reg_1723_pp1_it1[42] <= 1'b0;
ap_reg_ppstg_tmp_42_reg_1723_pp1_it1[43] <= 1'b0;
ap_reg_ppstg_tmp_42_reg_1723_pp1_it1[44] <= 1'b0;
ap_reg_ppstg_tmp_42_reg_1723_pp1_it1[45] <= 1'b0;
ap_reg_ppstg_tmp_42_reg_1723_pp1_it1[46] <= 1'b0;
ap_reg_ppstg_tmp_42_reg_1723_pp1_it1[47] <= 1'b0;
ap_reg_ppstg_tmp_42_reg_1723_pp1_it1[48] <= 1'b0;
ap_reg_ppstg_tmp_42_reg_1723_pp1_it1[49] <= 1'b0;
ap_reg_ppstg_tmp_42_reg_1723_pp1_it1[50] <= 1'b0;
ap_reg_ppstg_tmp_42_reg_1723_pp1_it1[51] <= 1'b0;
ap_reg_ppstg_tmp_42_reg_1723_pp1_it1[52] <= 1'b0;
ap_reg_ppstg_tmp_42_reg_1723_pp1_it1[53] <= 1'b0;
ap_reg_ppstg_tmp_42_reg_1723_pp1_it1[54] <= 1'b0;
ap_reg_ppstg_tmp_42_reg_1723_pp1_it1[55] <= 1'b0;
ap_reg_ppstg_tmp_42_reg_1723_pp1_it1[56] <= 1'b0;
ap_reg_ppstg_tmp_42_reg_1723_pp1_it1[57] <= 1'b0;
ap_reg_ppstg_tmp_42_reg_1723_pp1_it1[58] <= 1'b0;
ap_reg_ppstg_tmp_42_reg_1723_pp1_it1[59] <= 1'b0;
ap_reg_ppstg_tmp_42_reg_1723_pp1_it1[60] <= 1'b0;
ap_reg_ppstg_tmp_42_reg_1723_pp1_it1[61] <= 1'b0;
ap_reg_ppstg_tmp_42_reg_1723_pp1_it1[62] <= 1'b0;
ap_reg_ppstg_tmp_42_reg_1723_pp1_it1[63] <= 1'b0;
end
always @ (ap_clk)
begin
ap_reg_ppstg_tmp_42_reg_1723_pp1_it2[14] <= 1'b0;
ap_reg_ppstg_tmp_42_reg_1723_pp1_it2[15] <= 1'b0;
ap_reg_ppstg_tmp_42_reg_1723_pp1_it2[16] <= 1'b0;
ap_reg_ppstg_tmp_42_reg_1723_pp1_it2[17] <= 1'b0;
ap_reg_ppstg_tmp_42_reg_1723_pp1_it2[18] <= 1'b0;
ap_reg_ppstg_tmp_42_reg_1723_pp1_it2[19] <= 1'b0;
ap_reg_ppstg_tmp_42_reg_1723_pp1_it2[20] <= 1'b0;
ap_reg_ppstg_tmp_42_reg_1723_pp1_it2[21] <= 1'b0;
ap_reg_ppstg_tmp_42_reg_1723_pp1_it2[22] <= 1'b0;
ap_reg_ppstg_tmp_42_reg_1723_pp1_it2[23] <= 1'b0;
ap_reg_ppstg_tmp_42_reg_1723_pp1_it2[24] <= 1'b0;
ap_reg_ppstg_tmp_42_reg_1723_pp1_it2[25] <= 1'b0;
ap_reg_ppstg_tmp_42_reg_1723_pp1_it2[26] <= 1'b0;
ap_reg_ppstg_tmp_42_reg_1723_pp1_it2[27] <= 1'b0;
ap_reg_ppstg_tmp_42_reg_1723_pp1_it2[28] <= 1'b0;
ap_reg_ppstg_tmp_42_reg_1723_pp1_it2[29] <= 1'b0;
ap_reg_ppstg_tmp_42_reg_1723_pp1_it2[30] <= 1'b0;
ap_reg_ppstg_tmp_42_reg_1723_pp1_it2[31] <= 1'b0;
ap_reg_ppstg_tmp_42_reg_1723_pp1_it2[32] <= 1'b0;
ap_reg_ppstg_tmp_42_reg_1723_pp1_it2[33] <= 1'b0;
ap_reg_ppstg_tmp_42_reg_1723_pp1_it2[34] <= 1'b0;
ap_reg_ppstg_tmp_42_reg_1723_pp1_it2[35] <= 1'b0;
ap_reg_ppstg_tmp_42_reg_1723_pp1_it2[36] <= 1'b0;
ap_reg_ppstg_tmp_42_reg_1723_pp1_it2[37] <= 1'b0;
ap_reg_ppstg_tmp_42_reg_1723_pp1_it2[38] <= 1'b0;
ap_reg_ppstg_tmp_42_reg_1723_pp1_it2[39] <= 1'b0;
ap_reg_ppstg_tmp_42_reg_1723_pp1_it2[40] <= 1'b0;
ap_reg_ppstg_tmp_42_reg_1723_pp1_it2[41] <= 1'b0;
ap_reg_ppstg_tmp_42_reg_1723_pp1_it2[42] <= 1'b0;
ap_reg_ppstg_tmp_42_reg_1723_pp1_it2[43] <= 1'b0;
ap_reg_ppstg_tmp_42_reg_1723_pp1_it2[44] <= 1'b0;
ap_reg_ppstg_tmp_42_reg_1723_pp1_it2[45] <= 1'b0;
ap_reg_ppstg_tmp_42_reg_1723_pp1_it2[46] <= 1'b0;
ap_reg_ppstg_tmp_42_reg_1723_pp1_it2[47] <= 1'b0;
ap_reg_ppstg_tmp_42_reg_1723_pp1_it2[48] <= 1'b0;
ap_reg_ppstg_tmp_42_reg_1723_pp1_it2[49] <= 1'b0;
ap_reg_ppstg_tmp_42_reg_1723_pp1_it2[50] <= 1'b0;
ap_reg_ppstg_tmp_42_reg_1723_pp1_it2[51] <= 1'b0;
ap_reg_ppstg_tmp_42_reg_1723_pp1_it2[52] <= 1'b0;
ap_reg_ppstg_tmp_42_reg_1723_pp1_it2[53] <= 1'b0;
ap_reg_ppstg_tmp_42_reg_1723_pp1_it2[54] <= 1'b0;
ap_reg_ppstg_tmp_42_reg_1723_pp1_it2[55] <= 1'b0;
ap_reg_ppstg_tmp_42_reg_1723_pp1_it2[56] <= 1'b0;
ap_reg_ppstg_tmp_42_reg_1723_pp1_it2[57] <= 1'b0;
ap_reg_ppstg_tmp_42_reg_1723_pp1_it2[58] <= 1'b0;
ap_reg_ppstg_tmp_42_reg_1723_pp1_it2[59] <= 1'b0;
ap_reg_ppstg_tmp_42_reg_1723_pp1_it2[60] <= 1'b0;
ap_reg_ppstg_tmp_42_reg_1723_pp1_it2[61] <= 1'b0;
ap_reg_ppstg_tmp_42_reg_1723_pp1_it2[62] <= 1'b0;
ap_reg_ppstg_tmp_42_reg_1723_pp1_it2[63] <= 1'b0;
end
always @ (ap_clk)
begin
tmp_45_reg_1750[0] <= 1'b1;
tmp_45_reg_1750[14] <= 1'b0;
tmp_45_reg_1750[15] <= 1'b0;
tmp_45_reg_1750[16] <= 1'b0;
tmp_45_reg_1750[17] <= 1'b0;
tmp_45_reg_1750[18] <= 1'b0;
tmp_45_reg_1750[19] <= 1'b0;
tmp_45_reg_1750[20] <= 1'b0;
tmp_45_reg_1750[21] <= 1'b0;
tmp_45_reg_1750[22] <= 1'b0;
tmp_45_reg_1750[23] <= 1'b0;
tmp_45_reg_1750[24] <= 1'b0;
tmp_45_reg_1750[25] <= 1'b0;
tmp_45_reg_1750[26] <= 1'b0;
tmp_45_reg_1750[27] <= 1'b0;
tmp_45_reg_1750[28] <= 1'b0;
tmp_45_reg_1750[29] <= 1'b0;
tmp_45_reg_1750[30] <= 1'b0;
tmp_45_reg_1750[31] <= 1'b0;
tmp_45_reg_1750[32] <= 1'b0;
tmp_45_reg_1750[33] <= 1'b0;
tmp_45_reg_1750[34] <= 1'b0;
tmp_45_reg_1750[35] <= 1'b0;
tmp_45_reg_1750[36] <= 1'b0;
tmp_45_reg_1750[37] <= 1'b0;
tmp_45_reg_1750[38] <= 1'b0;
tmp_45_reg_1750[39] <= 1'b0;
tmp_45_reg_1750[40] <= 1'b0;
tmp_45_reg_1750[41] <= 1'b0;
tmp_45_reg_1750[42] <= 1'b0;
tmp_45_reg_1750[43] <= 1'b0;
tmp_45_reg_1750[44] <= 1'b0;
tmp_45_reg_1750[45] <= 1'b0;
tmp_45_reg_1750[46] <= 1'b0;
tmp_45_reg_1750[47] <= 1'b0;
tmp_45_reg_1750[48] <= 1'b0;
tmp_45_reg_1750[49] <= 1'b0;
tmp_45_reg_1750[50] <= 1'b0;
tmp_45_reg_1750[51] <= 1'b0;
tmp_45_reg_1750[52] <= 1'b0;
tmp_45_reg_1750[53] <= 1'b0;
tmp_45_reg_1750[54] <= 1'b0;
tmp_45_reg_1750[55] <= 1'b0;
tmp_45_reg_1750[56] <= 1'b0;
tmp_45_reg_1750[57] <= 1'b0;
tmp_45_reg_1750[58] <= 1'b0;
tmp_45_reg_1750[59] <= 1'b0;
tmp_45_reg_1750[60] <= 1'b0;
tmp_45_reg_1750[61] <= 1'b0;
tmp_45_reg_1750[62] <= 1'b0;
tmp_45_reg_1750[63] <= 1'b0;
end
always @ (ap_clk)
begin
ap_reg_ppstg_tmp_45_reg_1750_pp1_it1[0] <= 1'b1;
ap_reg_ppstg_tmp_45_reg_1750_pp1_it1[14] <= 1'b0;
ap_reg_ppstg_tmp_45_reg_1750_pp1_it1[15] <= 1'b0;
ap_reg_ppstg_tmp_45_reg_1750_pp1_it1[16] <= 1'b0;
ap_reg_ppstg_tmp_45_reg_1750_pp1_it1[17] <= 1'b0;
ap_reg_ppstg_tmp_45_reg_1750_pp1_it1[18] <= 1'b0;
ap_reg_ppstg_tmp_45_reg_1750_pp1_it1[19] <= 1'b0;
ap_reg_ppstg_tmp_45_reg_1750_pp1_it1[20] <= 1'b0;
ap_reg_ppstg_tmp_45_reg_1750_pp1_it1[21] <= 1'b0;
ap_reg_ppstg_tmp_45_reg_1750_pp1_it1[22] <= 1'b0;
ap_reg_ppstg_tmp_45_reg_1750_pp1_it1[23] <= 1'b0;
ap_reg_ppstg_tmp_45_reg_1750_pp1_it1[24] <= 1'b0;
ap_reg_ppstg_tmp_45_reg_1750_pp1_it1[25] <= 1'b0;
ap_reg_ppstg_tmp_45_reg_1750_pp1_it1[26] <= 1'b0;
ap_reg_ppstg_tmp_45_reg_1750_pp1_it1[27] <= 1'b0;
ap_reg_ppstg_tmp_45_reg_1750_pp1_it1[28] <= 1'b0;
ap_reg_ppstg_tmp_45_reg_1750_pp1_it1[29] <= 1'b0;
ap_reg_ppstg_tmp_45_reg_1750_pp1_it1[30] <= 1'b0;
ap_reg_ppstg_tmp_45_reg_1750_pp1_it1[31] <= 1'b0;
ap_reg_ppstg_tmp_45_reg_1750_pp1_it1[32] <= 1'b0;
ap_reg_ppstg_tmp_45_reg_1750_pp1_it1[33] <= 1'b0;
ap_reg_ppstg_tmp_45_reg_1750_pp1_it1[34] <= 1'b0;
ap_reg_ppstg_tmp_45_reg_1750_pp1_it1[35] <= 1'b0;
ap_reg_ppstg_tmp_45_reg_1750_pp1_it1[36] <= 1'b0;
ap_reg_ppstg_tmp_45_reg_1750_pp1_it1[37] <= 1'b0;
ap_reg_ppstg_tmp_45_reg_1750_pp1_it1[38] <= 1'b0;
ap_reg_ppstg_tmp_45_reg_1750_pp1_it1[39] <= 1'b0;
ap_reg_ppstg_tmp_45_reg_1750_pp1_it1[40] <= 1'b0;
ap_reg_ppstg_tmp_45_reg_1750_pp1_it1[41] <= 1'b0;
ap_reg_ppstg_tmp_45_reg_1750_pp1_it1[42] <= 1'b0;
ap_reg_ppstg_tmp_45_reg_1750_pp1_it1[43] <= 1'b0;
ap_reg_ppstg_tmp_45_reg_1750_pp1_it1[44] <= 1'b0;
ap_reg_ppstg_tmp_45_reg_1750_pp1_it1[45] <= 1'b0;
ap_reg_ppstg_tmp_45_reg_1750_pp1_it1[46] <= 1'b0;
ap_reg_ppstg_tmp_45_reg_1750_pp1_it1[47] <= 1'b0;
ap_reg_ppstg_tmp_45_reg_1750_pp1_it1[48] <= 1'b0;
ap_reg_ppstg_tmp_45_reg_1750_pp1_it1[49] <= 1'b0;
ap_reg_ppstg_tmp_45_reg_1750_pp1_it1[50] <= 1'b0;
ap_reg_ppstg_tmp_45_reg_1750_pp1_it1[51] <= 1'b0;
ap_reg_ppstg_tmp_45_reg_1750_pp1_it1[52] <= 1'b0;
ap_reg_ppstg_tmp_45_reg_1750_pp1_it1[53] <= 1'b0;
ap_reg_ppstg_tmp_45_reg_1750_pp1_it1[54] <= 1'b0;
ap_reg_ppstg_tmp_45_reg_1750_pp1_it1[55] <= 1'b0;
ap_reg_ppstg_tmp_45_reg_1750_pp1_it1[56] <= 1'b0;
ap_reg_ppstg_tmp_45_reg_1750_pp1_it1[57] <= 1'b0;
ap_reg_ppstg_tmp_45_reg_1750_pp1_it1[58] <= 1'b0;
ap_reg_ppstg_tmp_45_reg_1750_pp1_it1[59] <= 1'b0;
ap_reg_ppstg_tmp_45_reg_1750_pp1_it1[60] <= 1'b0;
ap_reg_ppstg_tmp_45_reg_1750_pp1_it1[61] <= 1'b0;
ap_reg_ppstg_tmp_45_reg_1750_pp1_it1[62] <= 1'b0;
ap_reg_ppstg_tmp_45_reg_1750_pp1_it1[63] <= 1'b0;
end
always @ (ap_clk)
begin
ap_reg_ppstg_tmp_45_reg_1750_pp1_it2[0] <= 1'b1;
ap_reg_ppstg_tmp_45_reg_1750_pp1_it2[14] <= 1'b0;
ap_reg_ppstg_tmp_45_reg_1750_pp1_it2[15] <= 1'b0;
ap_reg_ppstg_tmp_45_reg_1750_pp1_it2[16] <= 1'b0;
ap_reg_ppstg_tmp_45_reg_1750_pp1_it2[17] <= 1'b0;
ap_reg_ppstg_tmp_45_reg_1750_pp1_it2[18] <= 1'b0;
ap_reg_ppstg_tmp_45_reg_1750_pp1_it2[19] <= 1'b0;
ap_reg_ppstg_tmp_45_reg_1750_pp1_it2[20] <= 1'b0;
ap_reg_ppstg_tmp_45_reg_1750_pp1_it2[21] <= 1'b0;
ap_reg_ppstg_tmp_45_reg_1750_pp1_it2[22] <= 1'b0;
ap_reg_ppstg_tmp_45_reg_1750_pp1_it2[23] <= 1'b0;
ap_reg_ppstg_tmp_45_reg_1750_pp1_it2[24] <= 1'b0;
ap_reg_ppstg_tmp_45_reg_1750_pp1_it2[25] <= 1'b0;
ap_reg_ppstg_tmp_45_reg_1750_pp1_it2[26] <= 1'b0;
ap_reg_ppstg_tmp_45_reg_1750_pp1_it2[27] <= 1'b0;
ap_reg_ppstg_tmp_45_reg_1750_pp1_it2[28] <= 1'b0;
ap_reg_ppstg_tmp_45_reg_1750_pp1_it2[29] <= 1'b0;
ap_reg_ppstg_tmp_45_reg_1750_pp1_it2[30] <= 1'b0;
ap_reg_ppstg_tmp_45_reg_1750_pp1_it2[31] <= 1'b0;
ap_reg_ppstg_tmp_45_reg_1750_pp1_it2[32] <= 1'b0;
ap_reg_ppstg_tmp_45_reg_1750_pp1_it2[33] <= 1'b0;
ap_reg_ppstg_tmp_45_reg_1750_pp1_it2[34] <= 1'b0;
ap_reg_ppstg_tmp_45_reg_1750_pp1_it2[35] <= 1'b0;
ap_reg_ppstg_tmp_45_reg_1750_pp1_it2[36] <= 1'b0;
ap_reg_ppstg_tmp_45_reg_1750_pp1_it2[37] <= 1'b0;
ap_reg_ppstg_tmp_45_reg_1750_pp1_it2[38] <= 1'b0;
ap_reg_ppstg_tmp_45_reg_1750_pp1_it2[39] <= 1'b0;
ap_reg_ppstg_tmp_45_reg_1750_pp1_it2[40] <= 1'b0;
ap_reg_ppstg_tmp_45_reg_1750_pp1_it2[41] <= 1'b0;
ap_reg_ppstg_tmp_45_reg_1750_pp1_it2[42] <= 1'b0;
ap_reg_ppstg_tmp_45_reg_1750_pp1_it2[43] <= 1'b0;
ap_reg_ppstg_tmp_45_reg_1750_pp1_it2[44] <= 1'b0;
ap_reg_ppstg_tmp_45_reg_1750_pp1_it2[45] <= 1'b0;
ap_reg_ppstg_tmp_45_reg_1750_pp1_it2[46] <= 1'b0;
ap_reg_ppstg_tmp_45_reg_1750_pp1_it2[47] <= 1'b0;
ap_reg_ppstg_tmp_45_reg_1750_pp1_it2[48] <= 1'b0;
ap_reg_ppstg_tmp_45_reg_1750_pp1_it2[49] <= 1'b0;
ap_reg_ppstg_tmp_45_reg_1750_pp1_it2[50] <= 1'b0;
ap_reg_ppstg_tmp_45_reg_1750_pp1_it2[51] <= 1'b0;
ap_reg_ppstg_tmp_45_reg_1750_pp1_it2[52] <= 1'b0;
ap_reg_ppstg_tmp_45_reg_1750_pp1_it2[53] <= 1'b0;
ap_reg_ppstg_tmp_45_reg_1750_pp1_it2[54] <= 1'b0;
ap_reg_ppstg_tmp_45_reg_1750_pp1_it2[55] <= 1'b0;
ap_reg_ppstg_tmp_45_reg_1750_pp1_it2[56] <= 1'b0;
ap_reg_ppstg_tmp_45_reg_1750_pp1_it2[57] <= 1'b0;
ap_reg_ppstg_tmp_45_reg_1750_pp1_it2[58] <= 1'b0;
ap_reg_ppstg_tmp_45_reg_1750_pp1_it2[59] <= 1'b0;
ap_reg_ppstg_tmp_45_reg_1750_pp1_it2[60] <= 1'b0;
ap_reg_ppstg_tmp_45_reg_1750_pp1_it2[61] <= 1'b0;
ap_reg_ppstg_tmp_45_reg_1750_pp1_it2[62] <= 1'b0;
ap_reg_ppstg_tmp_45_reg_1750_pp1_it2[63] <= 1'b0;
end
always @ (ap_clk)
begin
tmp_48_reg_1767[14] <= 1'b0;
tmp_48_reg_1767[15] <= 1'b0;
tmp_48_reg_1767[16] <= 1'b0;
tmp_48_reg_1767[17] <= 1'b0;
tmp_48_reg_1767[18] <= 1'b0;
tmp_48_reg_1767[19] <= 1'b0;
tmp_48_reg_1767[20] <= 1'b0;
tmp_48_reg_1767[21] <= 1'b0;
tmp_48_reg_1767[22] <= 1'b0;
tmp_48_reg_1767[23] <= 1'b0;
tmp_48_reg_1767[24] <= 1'b0;
tmp_48_reg_1767[25] <= 1'b0;
tmp_48_reg_1767[26] <= 1'b0;
tmp_48_reg_1767[27] <= 1'b0;
tmp_48_reg_1767[28] <= 1'b0;
tmp_48_reg_1767[29] <= 1'b0;
tmp_48_reg_1767[30] <= 1'b0;
tmp_48_reg_1767[31] <= 1'b0;
tmp_48_reg_1767[32] <= 1'b0;
tmp_48_reg_1767[33] <= 1'b0;
tmp_48_reg_1767[34] <= 1'b0;
tmp_48_reg_1767[35] <= 1'b0;
tmp_48_reg_1767[36] <= 1'b0;
tmp_48_reg_1767[37] <= 1'b0;
tmp_48_reg_1767[38] <= 1'b0;
tmp_48_reg_1767[39] <= 1'b0;
tmp_48_reg_1767[40] <= 1'b0;
tmp_48_reg_1767[41] <= 1'b0;
tmp_48_reg_1767[42] <= 1'b0;
tmp_48_reg_1767[43] <= 1'b0;
tmp_48_reg_1767[44] <= 1'b0;
tmp_48_reg_1767[45] <= 1'b0;
tmp_48_reg_1767[46] <= 1'b0;
tmp_48_reg_1767[47] <= 1'b0;
tmp_48_reg_1767[48] <= 1'b0;
tmp_48_reg_1767[49] <= 1'b0;
tmp_48_reg_1767[50] <= 1'b0;
tmp_48_reg_1767[51] <= 1'b0;
tmp_48_reg_1767[52] <= 1'b0;
tmp_48_reg_1767[53] <= 1'b0;
tmp_48_reg_1767[54] <= 1'b0;
tmp_48_reg_1767[55] <= 1'b0;
tmp_48_reg_1767[56] <= 1'b0;
tmp_48_reg_1767[57] <= 1'b0;
tmp_48_reg_1767[58] <= 1'b0;
tmp_48_reg_1767[59] <= 1'b0;
tmp_48_reg_1767[60] <= 1'b0;
tmp_48_reg_1767[61] <= 1'b0;
tmp_48_reg_1767[62] <= 1'b0;
tmp_48_reg_1767[63] <= 1'b0;
end
always @ (ap_clk)
begin
ap_reg_ppstg_tmp_48_reg_1767_pp1_it1[14] <= 1'b0;
ap_reg_ppstg_tmp_48_reg_1767_pp1_it1[15] <= 1'b0;
ap_reg_ppstg_tmp_48_reg_1767_pp1_it1[16] <= 1'b0;
ap_reg_ppstg_tmp_48_reg_1767_pp1_it1[17] <= 1'b0;
ap_reg_ppstg_tmp_48_reg_1767_pp1_it1[18] <= 1'b0;
ap_reg_ppstg_tmp_48_reg_1767_pp1_it1[19] <= 1'b0;
ap_reg_ppstg_tmp_48_reg_1767_pp1_it1[20] <= 1'b0;
ap_reg_ppstg_tmp_48_reg_1767_pp1_it1[21] <= 1'b0;
ap_reg_ppstg_tmp_48_reg_1767_pp1_it1[22] <= 1'b0;
ap_reg_ppstg_tmp_48_reg_1767_pp1_it1[23] <= 1'b0;
ap_reg_ppstg_tmp_48_reg_1767_pp1_it1[24] <= 1'b0;
ap_reg_ppstg_tmp_48_reg_1767_pp1_it1[25] <= 1'b0;
ap_reg_ppstg_tmp_48_reg_1767_pp1_it1[26] <= 1'b0;
ap_reg_ppstg_tmp_48_reg_1767_pp1_it1[27] <= 1'b0;
ap_reg_ppstg_tmp_48_reg_1767_pp1_it1[28] <= 1'b0;
ap_reg_ppstg_tmp_48_reg_1767_pp1_it1[29] <= 1'b0;
ap_reg_ppstg_tmp_48_reg_1767_pp1_it1[30] <= 1'b0;
ap_reg_ppstg_tmp_48_reg_1767_pp1_it1[31] <= 1'b0;
ap_reg_ppstg_tmp_48_reg_1767_pp1_it1[32] <= 1'b0;
ap_reg_ppstg_tmp_48_reg_1767_pp1_it1[33] <= 1'b0;
ap_reg_ppstg_tmp_48_reg_1767_pp1_it1[34] <= 1'b0;
ap_reg_ppstg_tmp_48_reg_1767_pp1_it1[35] <= 1'b0;
ap_reg_ppstg_tmp_48_reg_1767_pp1_it1[36] <= 1'b0;
ap_reg_ppstg_tmp_48_reg_1767_pp1_it1[37] <= 1'b0;
ap_reg_ppstg_tmp_48_reg_1767_pp1_it1[38] <= 1'b0;
ap_reg_ppstg_tmp_48_reg_1767_pp1_it1[39] <= 1'b0;
ap_reg_ppstg_tmp_48_reg_1767_pp1_it1[40] <= 1'b0;
ap_reg_ppstg_tmp_48_reg_1767_pp1_it1[41] <= 1'b0;
ap_reg_ppstg_tmp_48_reg_1767_pp1_it1[42] <= 1'b0;
ap_reg_ppstg_tmp_48_reg_1767_pp1_it1[43] <= 1'b0;
ap_reg_ppstg_tmp_48_reg_1767_pp1_it1[44] <= 1'b0;
ap_reg_ppstg_tmp_48_reg_1767_pp1_it1[45] <= 1'b0;
ap_reg_ppstg_tmp_48_reg_1767_pp1_it1[46] <= 1'b0;
ap_reg_ppstg_tmp_48_reg_1767_pp1_it1[47] <= 1'b0;
ap_reg_ppstg_tmp_48_reg_1767_pp1_it1[48] <= 1'b0;
ap_reg_ppstg_tmp_48_reg_1767_pp1_it1[49] <= 1'b0;
ap_reg_ppstg_tmp_48_reg_1767_pp1_it1[50] <= 1'b0;
ap_reg_ppstg_tmp_48_reg_1767_pp1_it1[51] <= 1'b0;
ap_reg_ppstg_tmp_48_reg_1767_pp1_it1[52] <= 1'b0;
ap_reg_ppstg_tmp_48_reg_1767_pp1_it1[53] <= 1'b0;
ap_reg_ppstg_tmp_48_reg_1767_pp1_it1[54] <= 1'b0;
ap_reg_ppstg_tmp_48_reg_1767_pp1_it1[55] <= 1'b0;
ap_reg_ppstg_tmp_48_reg_1767_pp1_it1[56] <= 1'b0;
ap_reg_ppstg_tmp_48_reg_1767_pp1_it1[57] <= 1'b0;
ap_reg_ppstg_tmp_48_reg_1767_pp1_it1[58] <= 1'b0;
ap_reg_ppstg_tmp_48_reg_1767_pp1_it1[59] <= 1'b0;
ap_reg_ppstg_tmp_48_reg_1767_pp1_it1[60] <= 1'b0;
ap_reg_ppstg_tmp_48_reg_1767_pp1_it1[61] <= 1'b0;
ap_reg_ppstg_tmp_48_reg_1767_pp1_it1[62] <= 1'b0;
ap_reg_ppstg_tmp_48_reg_1767_pp1_it1[63] <= 1'b0;
end
always @ (ap_clk)
begin
ap_reg_ppstg_tmp_48_reg_1767_pp1_it2[14] <= 1'b0;
ap_reg_ppstg_tmp_48_reg_1767_pp1_it2[15] <= 1'b0;
ap_reg_ppstg_tmp_48_reg_1767_pp1_it2[16] <= 1'b0;
ap_reg_ppstg_tmp_48_reg_1767_pp1_it2[17] <= 1'b0;
ap_reg_ppstg_tmp_48_reg_1767_pp1_it2[18] <= 1'b0;
ap_reg_ppstg_tmp_48_reg_1767_pp1_it2[19] <= 1'b0;
ap_reg_ppstg_tmp_48_reg_1767_pp1_it2[20] <= 1'b0;
ap_reg_ppstg_tmp_48_reg_1767_pp1_it2[21] <= 1'b0;
ap_reg_ppstg_tmp_48_reg_1767_pp1_it2[22] <= 1'b0;
ap_reg_ppstg_tmp_48_reg_1767_pp1_it2[23] <= 1'b0;
ap_reg_ppstg_tmp_48_reg_1767_pp1_it2[24] <= 1'b0;
ap_reg_ppstg_tmp_48_reg_1767_pp1_it2[25] <= 1'b0;
ap_reg_ppstg_tmp_48_reg_1767_pp1_it2[26] <= 1'b0;
ap_reg_ppstg_tmp_48_reg_1767_pp1_it2[27] <= 1'b0;
ap_reg_ppstg_tmp_48_reg_1767_pp1_it2[28] <= 1'b0;
ap_reg_ppstg_tmp_48_reg_1767_pp1_it2[29] <= 1'b0;
ap_reg_ppstg_tmp_48_reg_1767_pp1_it2[30] <= 1'b0;
ap_reg_ppstg_tmp_48_reg_1767_pp1_it2[31] <= 1'b0;
ap_reg_ppstg_tmp_48_reg_1767_pp1_it2[32] <= 1'b0;
ap_reg_ppstg_tmp_48_reg_1767_pp1_it2[33] <= 1'b0;
ap_reg_ppstg_tmp_48_reg_1767_pp1_it2[34] <= 1'b0;
ap_reg_ppstg_tmp_48_reg_1767_pp1_it2[35] <= 1'b0;
ap_reg_ppstg_tmp_48_reg_1767_pp1_it2[36] <= 1'b0;
ap_reg_ppstg_tmp_48_reg_1767_pp1_it2[37] <= 1'b0;
ap_reg_ppstg_tmp_48_reg_1767_pp1_it2[38] <= 1'b0;
ap_reg_ppstg_tmp_48_reg_1767_pp1_it2[39] <= 1'b0;
ap_reg_ppstg_tmp_48_reg_1767_pp1_it2[40] <= 1'b0;
ap_reg_ppstg_tmp_48_reg_1767_pp1_it2[41] <= 1'b0;
ap_reg_ppstg_tmp_48_reg_1767_pp1_it2[42] <= 1'b0;
ap_reg_ppstg_tmp_48_reg_1767_pp1_it2[43] <= 1'b0;
ap_reg_ppstg_tmp_48_reg_1767_pp1_it2[44] <= 1'b0;
ap_reg_ppstg_tmp_48_reg_1767_pp1_it2[45] <= 1'b0;
ap_reg_ppstg_tmp_48_reg_1767_pp1_it2[46] <= 1'b0;
ap_reg_ppstg_tmp_48_reg_1767_pp1_it2[47] <= 1'b0;
ap_reg_ppstg_tmp_48_reg_1767_pp1_it2[48] <= 1'b0;
ap_reg_ppstg_tmp_48_reg_1767_pp1_it2[49] <= 1'b0;
ap_reg_ppstg_tmp_48_reg_1767_pp1_it2[50] <= 1'b0;
ap_reg_ppstg_tmp_48_reg_1767_pp1_it2[51] <= 1'b0;
ap_reg_ppstg_tmp_48_reg_1767_pp1_it2[52] <= 1'b0;
ap_reg_ppstg_tmp_48_reg_1767_pp1_it2[53] <= 1'b0;
ap_reg_ppstg_tmp_48_reg_1767_pp1_it2[54] <= 1'b0;
ap_reg_ppstg_tmp_48_reg_1767_pp1_it2[55] <= 1'b0;
ap_reg_ppstg_tmp_48_reg_1767_pp1_it2[56] <= 1'b0;
ap_reg_ppstg_tmp_48_reg_1767_pp1_it2[57] <= 1'b0;
ap_reg_ppstg_tmp_48_reg_1767_pp1_it2[58] <= 1'b0;
ap_reg_ppstg_tmp_48_reg_1767_pp1_it2[59] <= 1'b0;
ap_reg_ppstg_tmp_48_reg_1767_pp1_it2[60] <= 1'b0;
ap_reg_ppstg_tmp_48_reg_1767_pp1_it2[61] <= 1'b0;
ap_reg_ppstg_tmp_48_reg_1767_pp1_it2[62] <= 1'b0;
ap_reg_ppstg_tmp_48_reg_1767_pp1_it2[63] <= 1'b0;
end
always @ (ap_clk)
begin
b_addr17_reg_1784[0] <= 1'b1;
b_addr17_reg_1784[1] <= 1'b1;
b_addr17_reg_1784[2] <= 1'b1;
end
always @ (ap_clk)
begin
tmp_51_reg_1804[0] <= 1'b1;
tmp_51_reg_1804[1] <= 1'b1;
tmp_51_reg_1804[2] <= 1'b1;
tmp_51_reg_1804[14] <= 1'b0;
tmp_51_reg_1804[15] <= 1'b0;
tmp_51_reg_1804[16] <= 1'b0;
tmp_51_reg_1804[17] <= 1'b0;
tmp_51_reg_1804[18] <= 1'b0;
tmp_51_reg_1804[19] <= 1'b0;
tmp_51_reg_1804[20] <= 1'b0;
tmp_51_reg_1804[21] <= 1'b0;
tmp_51_reg_1804[22] <= 1'b0;
tmp_51_reg_1804[23] <= 1'b0;
tmp_51_reg_1804[24] <= 1'b0;
tmp_51_reg_1804[25] <= 1'b0;
tmp_51_reg_1804[26] <= 1'b0;
tmp_51_reg_1804[27] <= 1'b0;
tmp_51_reg_1804[28] <= 1'b0;
tmp_51_reg_1804[29] <= 1'b0;
tmp_51_reg_1804[30] <= 1'b0;
tmp_51_reg_1804[31] <= 1'b0;
tmp_51_reg_1804[32] <= 1'b0;
tmp_51_reg_1804[33] <= 1'b0;
tmp_51_reg_1804[34] <= 1'b0;
tmp_51_reg_1804[35] <= 1'b0;
tmp_51_reg_1804[36] <= 1'b0;
tmp_51_reg_1804[37] <= 1'b0;
tmp_51_reg_1804[38] <= 1'b0;
tmp_51_reg_1804[39] <= 1'b0;
tmp_51_reg_1804[40] <= 1'b0;
tmp_51_reg_1804[41] <= 1'b0;
tmp_51_reg_1804[42] <= 1'b0;
tmp_51_reg_1804[43] <= 1'b0;
tmp_51_reg_1804[44] <= 1'b0;
tmp_51_reg_1804[45] <= 1'b0;
tmp_51_reg_1804[46] <= 1'b0;
tmp_51_reg_1804[47] <= 1'b0;
tmp_51_reg_1804[48] <= 1'b0;
tmp_51_reg_1804[49] <= 1'b0;
tmp_51_reg_1804[50] <= 1'b0;
tmp_51_reg_1804[51] <= 1'b0;
tmp_51_reg_1804[52] <= 1'b0;
tmp_51_reg_1804[53] <= 1'b0;
tmp_51_reg_1804[54] <= 1'b0;
tmp_51_reg_1804[55] <= 1'b0;
tmp_51_reg_1804[56] <= 1'b0;
tmp_51_reg_1804[57] <= 1'b0;
tmp_51_reg_1804[58] <= 1'b0;
tmp_51_reg_1804[59] <= 1'b0;
tmp_51_reg_1804[60] <= 1'b0;
tmp_51_reg_1804[61] <= 1'b0;
tmp_51_reg_1804[62] <= 1'b0;
tmp_51_reg_1804[63] <= 1'b0;
end
always @ (ap_clk)
begin
ap_reg_ppstg_tmp_51_reg_1804_pp1_it1[0] <= 1'b1;
ap_reg_ppstg_tmp_51_reg_1804_pp1_it1[1] <= 1'b1;
ap_reg_ppstg_tmp_51_reg_1804_pp1_it1[2] <= 1'b1;
ap_reg_ppstg_tmp_51_reg_1804_pp1_it1[14] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_1804_pp1_it1[15] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_1804_pp1_it1[16] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_1804_pp1_it1[17] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_1804_pp1_it1[18] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_1804_pp1_it1[19] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_1804_pp1_it1[20] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_1804_pp1_it1[21] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_1804_pp1_it1[22] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_1804_pp1_it1[23] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_1804_pp1_it1[24] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_1804_pp1_it1[25] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_1804_pp1_it1[26] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_1804_pp1_it1[27] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_1804_pp1_it1[28] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_1804_pp1_it1[29] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_1804_pp1_it1[30] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_1804_pp1_it1[31] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_1804_pp1_it1[32] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_1804_pp1_it1[33] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_1804_pp1_it1[34] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_1804_pp1_it1[35] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_1804_pp1_it1[36] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_1804_pp1_it1[37] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_1804_pp1_it1[38] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_1804_pp1_it1[39] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_1804_pp1_it1[40] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_1804_pp1_it1[41] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_1804_pp1_it1[42] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_1804_pp1_it1[43] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_1804_pp1_it1[44] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_1804_pp1_it1[45] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_1804_pp1_it1[46] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_1804_pp1_it1[47] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_1804_pp1_it1[48] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_1804_pp1_it1[49] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_1804_pp1_it1[50] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_1804_pp1_it1[51] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_1804_pp1_it1[52] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_1804_pp1_it1[53] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_1804_pp1_it1[54] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_1804_pp1_it1[55] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_1804_pp1_it1[56] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_1804_pp1_it1[57] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_1804_pp1_it1[58] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_1804_pp1_it1[59] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_1804_pp1_it1[60] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_1804_pp1_it1[61] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_1804_pp1_it1[62] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_1804_pp1_it1[63] <= 1'b0;
end
always @ (ap_clk)
begin
ap_reg_ppstg_tmp_51_reg_1804_pp1_it2[0] <= 1'b1;
ap_reg_ppstg_tmp_51_reg_1804_pp1_it2[1] <= 1'b1;
ap_reg_ppstg_tmp_51_reg_1804_pp1_it2[2] <= 1'b1;
ap_reg_ppstg_tmp_51_reg_1804_pp1_it2[14] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_1804_pp1_it2[15] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_1804_pp1_it2[16] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_1804_pp1_it2[17] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_1804_pp1_it2[18] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_1804_pp1_it2[19] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_1804_pp1_it2[20] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_1804_pp1_it2[21] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_1804_pp1_it2[22] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_1804_pp1_it2[23] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_1804_pp1_it2[24] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_1804_pp1_it2[25] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_1804_pp1_it2[26] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_1804_pp1_it2[27] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_1804_pp1_it2[28] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_1804_pp1_it2[29] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_1804_pp1_it2[30] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_1804_pp1_it2[31] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_1804_pp1_it2[32] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_1804_pp1_it2[33] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_1804_pp1_it2[34] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_1804_pp1_it2[35] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_1804_pp1_it2[36] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_1804_pp1_it2[37] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_1804_pp1_it2[38] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_1804_pp1_it2[39] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_1804_pp1_it2[40] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_1804_pp1_it2[41] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_1804_pp1_it2[42] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_1804_pp1_it2[43] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_1804_pp1_it2[44] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_1804_pp1_it2[45] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_1804_pp1_it2[46] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_1804_pp1_it2[47] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_1804_pp1_it2[48] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_1804_pp1_it2[49] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_1804_pp1_it2[50] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_1804_pp1_it2[51] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_1804_pp1_it2[52] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_1804_pp1_it2[53] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_1804_pp1_it2[54] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_1804_pp1_it2[55] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_1804_pp1_it2[56] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_1804_pp1_it2[57] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_1804_pp1_it2[58] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_1804_pp1_it2[59] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_1804_pp1_it2[60] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_1804_pp1_it2[61] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_1804_pp1_it2[62] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_1804_pp1_it2[63] <= 1'b0;
end
endmodule //step1
|
// ==============================================================
// File generated by AutoESL - High-Level Synthesis System (C, C++, SystemC)
// Version: 2011.1
// Copyright (C) 2011 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module step1_grp_fu_811_ACMP_fadd_13(
clk,
reset,
ce,
din0,
din1,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
output[dout_WIDTH - 1:0] dout;
ACMP_fadd #(
.ID( ID ),
.NUM_STAGE( 5 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_fadd_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ));
endmodule
|
// ==============================================================
// File generated by AutoESL - High-Level Synthesis System (C, C++, SystemC)
// Version: 2011.1
// Copyright (C) 2011 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module step1_grp_fu_815_ACMP_fmul_14(
clk,
reset,
ce,
din0,
din1,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
output[dout_WIDTH - 1:0] dout;
ACMP_fmul #(
.ID( ID ),
.NUM_STAGE( 4 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_fmul_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ));
endmodule
|
// ==============================================================
// File generated by AutoESL - High-Level Synthesis System (C, C++, SystemC)
// Version: 2011.1
// Copyright (C) 2011 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module step1_grp_fu_819_ACMP_fmul_15(
clk,
reset,
ce,
din0,
din1,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
output[dout_WIDTH - 1:0] dout;
ACMP_fmul #(
.ID( ID ),
.NUM_STAGE( 4 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_fmul_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ));
endmodule
|
// ==============================================================
// RTL generated by AutoESL - High-Level Synthesis System (C, C++, SystemC)
// Version: 2011.1
// Copyright (C) 2011 Xilinx Inc. All rights reserved.
//
// ===========================================================
`timescale 1 ns / 1 ps
module write_r (
ap_clk,
ap_rst,
ap_start,
ap_done,
ap_idle,
tag,
counter,
d_address0,
d_ce0,
d_q0,
d_address1,
d_ce1,
d_q1,
V_bus_req_din,
V_bus_req_full_n,
V_bus_req_write,
V_bus_rsp_dout,
V_bus_rsp_empty_n,
V_bus_rsp_read,
V_bus_address,
V_bus_datain,
V_bus_dataout,
V_bus_size
);
input ap_clk;
input ap_rst;
input ap_start;
output ap_done;
output ap_idle;
input [1:0] tag;
input [6:0] counter;
output [11:0] d_address0;
output d_ce0;
input [31:0] d_q0;
output [11:0] d_address1;
output d_ce1;
input [31:0] d_q1;
output V_bus_req_din;
input V_bus_req_full_n;
output V_bus_req_write;
input V_bus_rsp_dout;
input V_bus_rsp_empty_n;
output V_bus_rsp_read;
output [31:0] V_bus_address;
input [127:0] V_bus_datain;
output [127:0] V_bus_dataout;
output [31:0] V_bus_size;
reg ap_done;
reg ap_idle;
reg[11:0] d_address0;
reg d_ce0;
reg[11:0] d_address1;
reg d_ce1;
reg V_bus_req_din;
reg V_bus_req_write;
reg[31:0] V_bus_address;
reg[127:0] V_bus_dataout;
reg [2:0] ap_CS_fsm;
reg [10:0] indvar_flatten1_reg_135;
reg [6:0] i_1_reg_146;
reg [4:0] indvar_reg_157;
reg [6:0] j_1_reg_168;
reg [10:0] indvar_flatten_reg_179;
reg [6:0] i_reg_190;
reg [4:0] indvar1_reg_201;
reg [6:0] j_reg_212;
reg [31:0] reg_224;
reg ap_reg_ppiten_pp0_it2;
reg ap_reg_ppiten_pp0_it0;
reg ap_reg_ppiten_pp0_it1;
reg [0:0] exitcond2_reg_672;
reg [0:0] ap_reg_ppstg_exitcond2_reg_672_pp0_it2;
reg ap_sig_bdd_73;
reg ap_reg_ppiten_pp0_it3;
reg ap_reg_ppiten_pp0_it4;
reg [0:0] ap_reg_ppstg_exitcond2_reg_672_pp0_it1;
reg ap_reg_ppiten_pp1_it2;
reg ap_reg_ppiten_pp1_it0;
reg ap_reg_ppiten_pp1_it1;
reg [0:0] exitcond_reg_736;
reg [0:0] ap_reg_ppstg_exitcond_reg_736_pp1_it2;
reg ap_sig_bdd_96;
reg ap_reg_ppiten_pp1_it3;
reg ap_reg_ppiten_pp1_it4;
reg [0:0] ap_reg_ppstg_exitcond_reg_736_pp1_it1;
reg [31:0] reg_228;
wire [19:0] tmp1_cast_fu_266_p1;
reg [19:0] tmp1_cast_reg_662;
wire [0:0] or_cond_fu_244_p2;
wire [19:0] tmp3_fu_270_p2;
reg [19:0] tmp3_reg_667;
wire [0:0] tmp_3_fu_250_p2;
wire [0:0] exitcond2_fu_276_p2;
reg [10:0] indvar_flatten_next1_reg_676;
reg [4:0] indvar_mid2_reg_681;
reg [4:0] ap_reg_ppstg_indvar_mid2_reg_681_pp0_it1;
reg [6:0] j_1_mid2_reg_687;
reg [6:0] i_1_mid2_reg_694;
reg [6:0] ap_reg_ppstg_i_1_mid2_reg_694_pp0_it1;
wire [6:0] tmp_18_fu_371_p2;
wire [4:0] indvar_next_fu_376_p2;
reg [17:0] tmp_16_reg_721;
wire [127:0] tmp_15_fu_444_p1;
wire [0:0] exitcond_fu_459_p2;
reg [10:0] indvar_flatten_next_reg_740;
reg [4:0] indvar1_mid2_reg_745;
reg [4:0] ap_reg_ppstg_indvar1_mid2_reg_745_pp1_it1;
reg [6:0] j_mid2_reg_751;
reg [6:0] i_mid2_reg_758;
reg [6:0] ap_reg_ppstg_i_mid2_reg_758_pp1_it1;
wire [6:0] tmp_10_fu_554_p2;
wire [4:0] indvar_next1_fu_559_p2;
reg [19:0] tmp_7_reg_785;
wire [127:0] tmp_s_fu_641_p1;
reg [10:0] indvar_flatten1_phi_fu_139_p4;
reg [6:0] i_1_phi_fu_150_p4;
reg [4:0] indvar_phi_fu_161_p4;
reg [6:0] j_1_phi_fu_172_p4;
reg [10:0] indvar_flatten_phi_fu_183_p4;
reg [6:0] i_phi_fu_194_p4;
reg [4:0] indvar1_phi_fu_205_p4;
reg [6:0] j_phi_fu_216_p4;
wire [63:0] tmp_12_fu_346_p1;
wire [63:0] tmp_14_fu_366_p1;
wire [63:0] tmp_5_fu_529_p1;
wire [63:0] tmp_6_fu_549_p1;
wire [63:0] tmp_17_fu_449_p1;
wire [63:0] tmp_9_fu_646_p1;
wire [0:0] tmp_1_fu_232_p2;
wire [0:0] tmp_2_fu_238_p2;
wire [18:0] counter_cast_fu_256_p1;
wire [18:0] tmp1_fu_260_p2;
wire [0:0] exitcond3_fu_288_p2;
wire [6:0] tmp_13_dup_fu_310_p2;
wire [12:0] tmp_5_trn2_cast_fu_324_p1;
wire [12:0] d_addr3_fu_330_p2;
wire [13:0] d_addr3_cast_fu_336_p1;
wire [13:0] tmp_14_trn_cast_fu_327_p1;
wire [13:0] d_addr4_fu_340_p2;
wire [6:0] tmp_13_fu_351_p2;
wire [13:0] tmp_16_trn_cast_fu_356_p1;
wire [13:0] d_addr1_fu_360_p2;
wire [12:0] i_1_cast_fu_381_p1;
wire [6:0] indvar_cast_fu_390_p1;
wire [6:0] tmp_fu_393_p2;
wire [12:0] tmp6_fu_384_p2;
wire [12:0] tmp_cast_fu_399_p1;
wire [12:0] tmp7_fu_403_p2;
wire [19:0] tmp7_cast_cast_fu_409_p1;
wire [19:0] tmp10_fu_413_p2;
wire [31:0] tmp13_fu_432_p1;
wire [31:0] tmp14_fu_428_p1;
wire [63:0] p_0_fu_436_p3;
wire [0:0] exitcond1_fu_471_p2;
wire [6:0] tmp_6_dup_fu_493_p2;
wire [12:0] tmp_4_trn7_cast_fu_507_p1;
wire [12:0] d_addr8_fu_513_p2;
wire [13:0] d_addr8_cast_fu_519_p1;
wire [13:0] tmp_7_trn_cast_fu_510_p1;
wire [13:0] d_addr9_fu_523_p2;
wire [6:0] tmp_8_fu_534_p2;
wire [13:0] tmp_9_trn_cast_fu_539_p1;
wire [13:0] d_addr6_fu_543_p2;
wire [12:0] i_cast_fu_564_p1;
wire [12:0] tmp4_fu_567_p2;
wire [19:0] tmp4_cast_fu_573_p1;
wire [19:0] tmp2_fu_577_p2;
wire [6:0] indvar1_cast_fu_586_p1;
wire [6:0] tmp8_fu_589_p2;
wire [14:0] tmp8_cast_fu_595_p1;
wire [14:0] tmp5_fu_599_p2;
wire [21:0] tmp9_fu_609_p0;
wire [21:0] tmp2_cast_fu_582_p1;
wire [21:0] tmp9_fu_609_p2;
wire [31:0] tmp11_fu_629_p1;
wire [31:0] tmp12_fu_625_p1;
wire [63:0] p_s_fu_633_p3;
reg [2:0] ap_NS_fsm;
parameter ap_const_logic_1 = 1'b1;
parameter ap_const_logic_0 = 1'b0;
parameter ap_ST_st0_fsm_0 = 3'b000;
parameter ap_ST_st1_fsm_1 = 3'b001;
parameter ap_ST_pp0_stg0_fsm_2 = 3'b010;
parameter ap_ST_pp1_stg0_fsm_3 = 3'b011;
parameter ap_ST_st12_fsm_4 = 3'b100;
parameter ap_const_lv1_0 = 1'b0;
parameter ap_const_lv11_0 = 11'b00000000000;
parameter ap_const_lv7_0 = 7'b0000000;
parameter ap_const_lv5_0 = 5'b00000;
parameter ap_const_lv32_0 = 32'b00000000000000000000000000000000;
parameter ap_const_lv7_43 = 7'b1000011;
parameter ap_const_lv7_2 = 7'b0000010;
parameter ap_const_lv2_0 = 2'b00;
parameter ap_const_lv19_C = 19'b0000000000000001100;
parameter ap_const_lv20_42000 = 20'b01000010000000000000;
parameter ap_const_lv11_400 = 11'b10000000000;
parameter ap_const_lv11_1 = 11'b00000000001;
parameter ap_const_lv5_10 = 5'b10000;
parameter ap_const_lv7_1 = 7'b0000001;
parameter ap_const_lv13_6 = 13'b0000000000110;
parameter ap_const_lv7_4 = 7'b0000100;
parameter ap_const_lv5_1 = 5'b00001;
parameter ap_const_lv32_2 = 32'b00000000000000000000000000000010;
parameter ap_const_lv32_13 = 32'b00000000000000000000000000010011;
parameter ap_const_lv15_5000 = 15'b101000000000000;
parameter ap_const_lv32_15 = 32'b00000000000000000000000000010101;
parameter ap_true = 1'b1;
/// ap_CS_fsm assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_CS_fsm
if (ap_rst == 1'b1) begin
ap_CS_fsm <= ap_ST_st0_fsm_0;
end else begin
ap_CS_fsm <= ap_NS_fsm;
end
end
/// ap_reg_ppiten_pp0_it0 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it0
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it0 <= ap_const_logic_0;
end else begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & ~(ap_sig_bdd_73 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it3)) & ~(ap_const_lv1_0 == exitcond2_fu_276_p2))) begin
ap_reg_ppiten_pp0_it0 <= ap_const_logic_0;
end else if (((ap_ST_st1_fsm_1 == ap_CS_fsm) & ~(ap_const_lv1_0 == or_cond_fu_244_p2) & (ap_const_lv1_0 == tmp_3_fu_250_p2))) begin
ap_reg_ppiten_pp0_it0 <= ap_const_logic_1;
end
end
end
/// ap_reg_ppiten_pp0_it1 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it1
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it1 <= ap_const_logic_0;
end else begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & ~(ap_sig_bdd_73 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it3)) & (ap_const_lv1_0 == exitcond2_fu_276_p2))) begin
ap_reg_ppiten_pp0_it1 <= ap_const_logic_1;
end else if ((((ap_ST_st1_fsm_1 == ap_CS_fsm) & ~(ap_const_lv1_0 == or_cond_fu_244_p2) & (ap_const_lv1_0 == tmp_3_fu_250_p2)) | ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & ~(ap_sig_bdd_73 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it3)) & ~(ap_const_lv1_0 == exitcond2_fu_276_p2)))) begin
ap_reg_ppiten_pp0_it1 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp0_it2 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it2
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it2 <= ap_const_logic_0;
end else begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & ~(ap_sig_bdd_73 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it3)))) begin
ap_reg_ppiten_pp0_it2 <= ap_reg_ppiten_pp0_it1;
end else if (((ap_ST_st1_fsm_1 == ap_CS_fsm) & ~(ap_const_lv1_0 == or_cond_fu_244_p2) & (ap_const_lv1_0 == tmp_3_fu_250_p2))) begin
ap_reg_ppiten_pp0_it2 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp0_it3 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it3
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it3 <= ap_const_logic_0;
end else begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & ~(ap_sig_bdd_73 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it3)))) begin
ap_reg_ppiten_pp0_it3 <= ap_reg_ppiten_pp0_it2;
end else if (((ap_ST_st1_fsm_1 == ap_CS_fsm) & ~(ap_const_lv1_0 == or_cond_fu_244_p2) & (ap_const_lv1_0 == tmp_3_fu_250_p2))) begin
ap_reg_ppiten_pp0_it3 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp0_it4 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it4
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it4 <= ap_const_logic_0;
end else begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & ~(ap_sig_bdd_73 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it3)))) begin
ap_reg_ppiten_pp0_it4 <= ap_reg_ppiten_pp0_it3;
end else if (((ap_ST_st1_fsm_1 == ap_CS_fsm) & ~(ap_const_lv1_0 == or_cond_fu_244_p2) & (ap_const_lv1_0 == tmp_3_fu_250_p2))) begin
ap_reg_ppiten_pp0_it4 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp1_it0 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp1_it0
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp1_it0 <= ap_const_logic_0;
end else begin
if (((ap_ST_pp1_stg0_fsm_3 == ap_CS_fsm) & ~(ap_sig_bdd_96 & (ap_const_logic_1 == ap_reg_ppiten_pp1_it3)) & ~(ap_const_lv1_0 == exitcond_fu_459_p2))) begin
ap_reg_ppiten_pp1_it0 <= ap_const_logic_0;
end else if (((ap_ST_st1_fsm_1 == ap_CS_fsm) & ~(ap_const_lv1_0 == or_cond_fu_244_p2) & ~(ap_const_lv1_0 == tmp_3_fu_250_p2))) begin
ap_reg_ppiten_pp1_it0 <= ap_const_logic_1;
end
end
end
/// ap_reg_ppiten_pp1_it1 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp1_it1
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp1_it1 <= ap_const_logic_0;
end else begin
if (((ap_ST_pp1_stg0_fsm_3 == ap_CS_fsm) & ~(ap_sig_bdd_96 & (ap_const_logic_1 == ap_reg_ppiten_pp1_it3)) & (ap_const_lv1_0 == exitcond_fu_459_p2))) begin
ap_reg_ppiten_pp1_it1 <= ap_const_logic_1;
end else if ((((ap_ST_st1_fsm_1 == ap_CS_fsm) & ~(ap_const_lv1_0 == or_cond_fu_244_p2) & ~(ap_const_lv1_0 == tmp_3_fu_250_p2)) | ((ap_ST_pp1_stg0_fsm_3 == ap_CS_fsm) & ~(ap_sig_bdd_96 & (ap_const_logic_1 == ap_reg_ppiten_pp1_it3)) & ~(ap_const_lv1_0 == exitcond_fu_459_p2)))) begin
ap_reg_ppiten_pp1_it1 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp1_it2 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp1_it2
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp1_it2 <= ap_const_logic_0;
end else begin
if (((ap_ST_pp1_stg0_fsm_3 == ap_CS_fsm) & ~(ap_sig_bdd_96 & (ap_const_logic_1 == ap_reg_ppiten_pp1_it3)))) begin
ap_reg_ppiten_pp1_it2 <= ap_reg_ppiten_pp1_it1;
end else if (((ap_ST_st1_fsm_1 == ap_CS_fsm) & ~(ap_const_lv1_0 == or_cond_fu_244_p2) & ~(ap_const_lv1_0 == tmp_3_fu_250_p2))) begin
ap_reg_ppiten_pp1_it2 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp1_it3 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp1_it3
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp1_it3 <= ap_const_logic_0;
end else begin
if (((ap_ST_pp1_stg0_fsm_3 == ap_CS_fsm) & ~(ap_sig_bdd_96 & (ap_const_logic_1 == ap_reg_ppiten_pp1_it3)))) begin
ap_reg_ppiten_pp1_it3 <= ap_reg_ppiten_pp1_it2;
end else if (((ap_ST_st1_fsm_1 == ap_CS_fsm) & ~(ap_const_lv1_0 == or_cond_fu_244_p2) & ~(ap_const_lv1_0 == tmp_3_fu_250_p2))) begin
ap_reg_ppiten_pp1_it3 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp1_it4 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp1_it4
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp1_it4 <= ap_const_logic_0;
end else begin
if (((ap_ST_pp1_stg0_fsm_3 == ap_CS_fsm) & ~(ap_sig_bdd_96 & (ap_const_logic_1 == ap_reg_ppiten_pp1_it3)))) begin
ap_reg_ppiten_pp1_it4 <= ap_reg_ppiten_pp1_it3;
end else if (((ap_ST_st1_fsm_1 == ap_CS_fsm) & ~(ap_const_lv1_0 == or_cond_fu_244_p2) & ~(ap_const_lv1_0 == tmp_3_fu_250_p2))) begin
ap_reg_ppiten_pp1_it4 <= ap_const_logic_0;
end
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & ~(ap_sig_bdd_73 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it3)))) begin
ap_reg_ppstg_exitcond2_reg_672_pp0_it1 <= exitcond2_reg_672;
end
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & ~(ap_sig_bdd_73 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it3)))) begin
ap_reg_ppstg_exitcond2_reg_672_pp0_it2 <= ap_reg_ppstg_exitcond2_reg_672_pp0_it1;
end
if (((ap_ST_pp1_stg0_fsm_3 == ap_CS_fsm) & ~(ap_sig_bdd_96 & (ap_const_logic_1 == ap_reg_ppiten_pp1_it3)))) begin
ap_reg_ppstg_exitcond_reg_736_pp1_it1 <= exitcond_reg_736;
end
if (((ap_ST_pp1_stg0_fsm_3 == ap_CS_fsm) & ~(ap_sig_bdd_96 & (ap_const_logic_1 == ap_reg_ppiten_pp1_it3)))) begin
ap_reg_ppstg_exitcond_reg_736_pp1_it2 <= ap_reg_ppstg_exitcond_reg_736_pp1_it1;
end
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & ~(ap_sig_bdd_73 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it3)))) begin
ap_reg_ppstg_i_1_mid2_reg_694_pp0_it1 <= i_1_mid2_reg_694;
end
if (((ap_ST_pp1_stg0_fsm_3 == ap_CS_fsm) & ~(ap_sig_bdd_96 & (ap_const_logic_1 == ap_reg_ppiten_pp1_it3)))) begin
ap_reg_ppstg_i_mid2_reg_758_pp1_it1 <= i_mid2_reg_758;
end
if (((ap_ST_pp1_stg0_fsm_3 == ap_CS_fsm) & ~(ap_sig_bdd_96 & (ap_const_logic_1 == ap_reg_ppiten_pp1_it3)))) begin
ap_reg_ppstg_indvar1_mid2_reg_745_pp1_it1 <= indvar1_mid2_reg_745;
end
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & ~(ap_sig_bdd_73 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it3)))) begin
ap_reg_ppstg_indvar_mid2_reg_681_pp0_it1 <= indvar_mid2_reg_681;
end
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ~(ap_sig_bdd_73 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it3)))) begin
exitcond2_reg_672 <= (indvar_flatten1_phi_fu_139_p4 == ap_const_lv11_400? 1'b1: 1'b0);
end
if (((ap_ST_pp1_stg0_fsm_3 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & ~(ap_sig_bdd_96 & (ap_const_logic_1 == ap_reg_ppiten_pp1_it3)))) begin
exitcond_reg_736 <= (indvar_flatten_phi_fu_183_p4 == ap_const_lv11_400? 1'b1: 1'b0);
end
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ~(ap_sig_bdd_73 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it3)) & (ap_const_lv1_0 == exitcond2_fu_276_p2))) begin
if (exitcond3_fu_288_p2) begin
i_1_mid2_reg_694 <= tmp_13_dup_fu_310_p2;
end else begin
i_1_mid2_reg_694 <= i_1_phi_fu_150_p4;
end
end
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & ~(ap_sig_bdd_73 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it3)) & (exitcond2_reg_672 == ap_const_lv1_0))) begin
i_1_reg_146 <= i_1_mid2_reg_694;
end else if (((ap_ST_st1_fsm_1 == ap_CS_fsm) & ~(ap_const_lv1_0 == or_cond_fu_244_p2) & (ap_const_lv1_0 == tmp_3_fu_250_p2))) begin
i_1_reg_146 <= ap_const_lv7_0;
end
if (((ap_ST_pp1_stg0_fsm_3 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & ~(ap_sig_bdd_96 & (ap_const_logic_1 == ap_reg_ppiten_pp1_it3)) & (ap_const_lv1_0 == exitcond_fu_459_p2))) begin
if (exitcond1_fu_471_p2) begin
i_mid2_reg_758 <= tmp_6_dup_fu_493_p2;
end else begin
i_mid2_reg_758 <= i_phi_fu_194_p4;
end
end
if (((ap_ST_st1_fsm_1 == ap_CS_fsm) & ~(ap_const_lv1_0 == or_cond_fu_244_p2) & ~(ap_const_lv1_0 == tmp_3_fu_250_p2))) begin
i_reg_190 <= ap_const_lv7_0;
end else if (((ap_ST_pp1_stg0_fsm_3 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & ~(ap_sig_bdd_96 & (ap_const_logic_1 == ap_reg_ppiten_pp1_it3)) & (ap_const_lv1_0 == exitcond_reg_736))) begin
i_reg_190 <= i_mid2_reg_758;
end
if (((ap_ST_pp1_stg0_fsm_3 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & ~(ap_sig_bdd_96 & (ap_const_logic_1 == ap_reg_ppiten_pp1_it3)) & (ap_const_lv1_0 == exitcond_fu_459_p2))) begin
if (exitcond1_fu_471_p2) begin
indvar1_mid2_reg_745 <= ap_const_lv5_0;
end else begin
indvar1_mid2_reg_745 <= indvar1_phi_fu_205_p4;
end
end
if (((ap_ST_st1_fsm_1 == ap_CS_fsm) & ~(ap_const_lv1_0 == or_cond_fu_244_p2) & ~(ap_const_lv1_0 == tmp_3_fu_250_p2))) begin
indvar1_reg_201 <= ap_const_lv5_0;
end else if (((ap_ST_pp1_stg0_fsm_3 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & ~(ap_sig_bdd_96 & (ap_const_logic_1 == ap_reg_ppiten_pp1_it3)) & (ap_const_lv1_0 == exitcond_reg_736))) begin
indvar1_reg_201 <= (indvar1_mid2_reg_745 + ap_const_lv5_1);
end
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & ~(ap_sig_bdd_73 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it3)) & (exitcond2_reg_672 == ap_const_lv1_0))) begin
indvar_flatten1_reg_135 <= indvar_flatten_next1_reg_676;
end else if (((ap_ST_st1_fsm_1 == ap_CS_fsm) & ~(ap_const_lv1_0 == or_cond_fu_244_p2) & (ap_const_lv1_0 == tmp_3_fu_250_p2))) begin
indvar_flatten1_reg_135 <= ap_const_lv11_0;
end
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ~(ap_sig_bdd_73 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it3)))) begin
indvar_flatten_next1_reg_676 <= (indvar_flatten1_phi_fu_139_p4 + ap_const_lv11_1);
end
if (((ap_ST_pp1_stg0_fsm_3 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & ~(ap_sig_bdd_96 & (ap_const_logic_1 == ap_reg_ppiten_pp1_it3)))) begin
indvar_flatten_next_reg_740 <= (indvar_flatten_phi_fu_183_p4 + ap_const_lv11_1);
end
if (((ap_ST_st1_fsm_1 == ap_CS_fsm) & ~(ap_const_lv1_0 == or_cond_fu_244_p2) & ~(ap_const_lv1_0 == tmp_3_fu_250_p2))) begin
indvar_flatten_reg_179 <= ap_const_lv11_0;
end else if (((ap_ST_pp1_stg0_fsm_3 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & ~(ap_sig_bdd_96 & (ap_const_logic_1 == ap_reg_ppiten_pp1_it3)) & (ap_const_lv1_0 == exitcond_reg_736))) begin
indvar_flatten_reg_179 <= indvar_flatten_next_reg_740;
end
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ~(ap_sig_bdd_73 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it3)) & (ap_const_lv1_0 == exitcond2_fu_276_p2))) begin
if (exitcond3_fu_288_p2) begin
indvar_mid2_reg_681 <= ap_const_lv5_0;
end else begin
indvar_mid2_reg_681 <= indvar_phi_fu_161_p4;
end
end
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & ~(ap_sig_bdd_73 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it3)) & (exitcond2_reg_672 == ap_const_lv1_0))) begin
indvar_reg_157 <= (indvar_mid2_reg_681 + ap_const_lv5_1);
end else if (((ap_ST_st1_fsm_1 == ap_CS_fsm) & ~(ap_const_lv1_0 == or_cond_fu_244_p2) & (ap_const_lv1_0 == tmp_3_fu_250_p2))) begin
indvar_reg_157 <= ap_const_lv5_0;
end
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ~(ap_sig_bdd_73 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it3)) & (ap_const_lv1_0 == exitcond2_fu_276_p2))) begin
if (exitcond3_fu_288_p2) begin
j_1_mid2_reg_687 <= ap_const_lv7_0;
end else begin
j_1_mid2_reg_687 <= j_1_phi_fu_172_p4;
end
end
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & ~(ap_sig_bdd_73 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it3)) & (exitcond2_reg_672 == ap_const_lv1_0))) begin
j_1_reg_168 <= (j_1_mid2_reg_687 + ap_const_lv7_4);
end else if (((ap_ST_st1_fsm_1 == ap_CS_fsm) & ~(ap_const_lv1_0 == or_cond_fu_244_p2) & (ap_const_lv1_0 == tmp_3_fu_250_p2))) begin
j_1_reg_168 <= ap_const_lv7_0;
end
if (((ap_ST_pp1_stg0_fsm_3 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & ~(ap_sig_bdd_96 & (ap_const_logic_1 == ap_reg_ppiten_pp1_it3)) & (ap_const_lv1_0 == exitcond_fu_459_p2))) begin
if (exitcond1_fu_471_p2) begin
j_mid2_reg_751 <= ap_const_lv7_0;
end else begin
j_mid2_reg_751 <= j_phi_fu_216_p4;
end
end
if (((ap_ST_st1_fsm_1 == ap_CS_fsm) & ~(ap_const_lv1_0 == or_cond_fu_244_p2) & ~(ap_const_lv1_0 == tmp_3_fu_250_p2))) begin
j_reg_212 <= ap_const_lv7_0;
end else if (((ap_ST_pp1_stg0_fsm_3 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & ~(ap_sig_bdd_96 & (ap_const_logic_1 == ap_reg_ppiten_pp1_it3)) & (ap_const_lv1_0 == exitcond_reg_736))) begin
j_reg_212 <= (j_mid2_reg_751 + ap_const_lv7_4);
end
if ((((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it2) & ~(ap_sig_bdd_73 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it3)) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_672_pp0_it1)) | ((ap_ST_pp1_stg0_fsm_3 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it2) & ~(ap_sig_bdd_96 & (ap_const_logic_1 == ap_reg_ppiten_pp1_it3)) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_736_pp1_it1)))) begin
reg_224 <= d_q0;
end
if ((((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it2) & ~(ap_sig_bdd_73 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it3)) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_672_pp0_it1)) | ((ap_ST_pp1_stg0_fsm_3 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it2) & ~(ap_sig_bdd_96 & (ap_const_logic_1 == ap_reg_ppiten_pp1_it3)) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_736_pp1_it1)))) begin
reg_228 <= d_q1;
end
if (((ap_ST_st1_fsm_1 == ap_CS_fsm) & ~(ap_const_lv1_0 == or_cond_fu_244_p2))) begin
tmp1_cast_reg_662[12] <= tmp1_cast_fu_266_p1[12];
tmp1_cast_reg_662[13] <= tmp1_cast_fu_266_p1[13];
tmp1_cast_reg_662[14] <= tmp1_cast_fu_266_p1[14];
tmp1_cast_reg_662[15] <= tmp1_cast_fu_266_p1[15];
tmp1_cast_reg_662[16] <= tmp1_cast_fu_266_p1[16];
tmp1_cast_reg_662[17] <= tmp1_cast_fu_266_p1[17];
tmp1_cast_reg_662[18] <= tmp1_cast_fu_266_p1[18];
end
if (((ap_ST_st1_fsm_1 == ap_CS_fsm) & ~(ap_const_lv1_0 == or_cond_fu_244_p2) & (ap_const_lv1_0 == tmp_3_fu_250_p2))) begin
tmp3_reg_667[12] <= tmp3_fu_270_p2[12];
tmp3_reg_667[13] <= tmp3_fu_270_p2[13];
tmp3_reg_667[14] <= tmp3_fu_270_p2[14];
tmp3_reg_667[15] <= tmp3_fu_270_p2[15];
tmp3_reg_667[16] <= tmp3_fu_270_p2[16];
tmp3_reg_667[17] <= tmp3_fu_270_p2[17];
tmp3_reg_667[18] <= tmp3_fu_270_p2[18];
tmp3_reg_667[19] <= tmp3_fu_270_p2[19];
end
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it2) & ~(ap_sig_bdd_73 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it3)) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_672_pp0_it1))) begin
tmp_16_reg_721 <= {{tmp10_fu_413_p2[ap_const_lv32_13 : ap_const_lv32_2]}};
end
if (((ap_ST_pp1_stg0_fsm_3 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it2) & ~(ap_sig_bdd_96 & (ap_const_logic_1 == ap_reg_ppiten_pp1_it3)) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_736_pp1_it1))) begin
tmp_7_reg_785 <= {{tmp9_fu_609_p2[ap_const_lv32_15 : ap_const_lv32_2]}};
end
end
/// V_bus_address assign process. ///
always @ (ap_CS_fsm or ap_reg_ppstg_exitcond2_reg_672_pp0_it2 or ap_sig_bdd_73 or ap_reg_ppiten_pp0_it3 or ap_reg_ppstg_exitcond_reg_736_pp1_it2 or ap_sig_bdd_96 or ap_reg_ppiten_pp1_it3 or tmp_17_fu_449_p1 or tmp_9_fu_646_p1)
begin
if (((ap_ST_pp1_stg0_fsm_3 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_736_pp1_it2) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it3) & ~(ap_sig_bdd_96 & (ap_const_logic_1 == ap_reg_ppiten_pp1_it3)))) begin
V_bus_address = tmp_9_fu_646_p1;
end else if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_reg_ppstg_exitcond2_reg_672_pp0_it2 == ap_const_lv1_0) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it3) & ~(ap_sig_bdd_73 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it3)))) begin
V_bus_address = tmp_17_fu_449_p1;
end else begin
V_bus_address = tmp_9_fu_646_p1;
end
end
/// V_bus_dataout assign process. ///
always @ (ap_CS_fsm or ap_reg_ppstg_exitcond2_reg_672_pp0_it2 or ap_sig_bdd_73 or ap_reg_ppiten_pp0_it3 or ap_reg_ppstg_exitcond_reg_736_pp1_it2 or ap_sig_bdd_96 or ap_reg_ppiten_pp1_it3 or tmp_15_fu_444_p1 or tmp_s_fu_641_p1)
begin
if (((ap_ST_pp1_stg0_fsm_3 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_736_pp1_it2) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it3) & ~(ap_sig_bdd_96 & (ap_const_logic_1 == ap_reg_ppiten_pp1_it3)))) begin
V_bus_dataout = tmp_s_fu_641_p1;
end else if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_reg_ppstg_exitcond2_reg_672_pp0_it2 == ap_const_lv1_0) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it3) & ~(ap_sig_bdd_73 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it3)))) begin
V_bus_dataout = tmp_15_fu_444_p1;
end else begin
V_bus_dataout = tmp_s_fu_641_p1;
end
end
/// V_bus_req_din assign process. ///
always @ (ap_CS_fsm or ap_reg_ppstg_exitcond2_reg_672_pp0_it2 or ap_sig_bdd_73 or ap_reg_ppiten_pp0_it3 or ap_reg_ppstg_exitcond_reg_736_pp1_it2 or ap_sig_bdd_96 or ap_reg_ppiten_pp1_it3)
begin
if ((((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_reg_ppstg_exitcond2_reg_672_pp0_it2 == ap_const_lv1_0) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it3) & ~(ap_sig_bdd_73 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it3))) | ((ap_ST_pp1_stg0_fsm_3 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_736_pp1_it2) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it3) & ~(ap_sig_bdd_96 & (ap_const_logic_1 == ap_reg_ppiten_pp1_it3))))) begin
V_bus_req_din = ap_const_logic_1;
end else begin
V_bus_req_din = ap_const_logic_0;
end
end
/// V_bus_req_write assign process. ///
always @ (ap_CS_fsm or ap_reg_ppstg_exitcond2_reg_672_pp0_it2 or ap_sig_bdd_73 or ap_reg_ppiten_pp0_it3 or ap_reg_ppstg_exitcond_reg_736_pp1_it2 or ap_sig_bdd_96 or ap_reg_ppiten_pp1_it3)
begin
if ((((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_reg_ppstg_exitcond2_reg_672_pp0_it2 == ap_const_lv1_0) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it3) & ~(ap_sig_bdd_73 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it3))) | ((ap_ST_pp1_stg0_fsm_3 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_736_pp1_it2) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it3) & ~(ap_sig_bdd_96 & (ap_const_logic_1 == ap_reg_ppiten_pp1_it3))))) begin
V_bus_req_write = ap_const_logic_1;
end else begin
V_bus_req_write = ap_const_logic_0;
end
end
/// ap_NS_fsm assign process. ///
always @ (ap_start or ap_CS_fsm or ap_reg_ppiten_pp0_it0 or ap_reg_ppiten_pp0_it1 or ap_sig_bdd_73 or ap_reg_ppiten_pp0_it3 or ap_reg_ppiten_pp0_it4 or ap_reg_ppiten_pp1_it0 or ap_reg_ppiten_pp1_it1 or ap_sig_bdd_96 or ap_reg_ppiten_pp1_it3 or ap_reg_ppiten_pp1_it4 or or_cond_fu_244_p2 or tmp_3_fu_250_p2 or exitcond2_fu_276_p2 or exitcond_fu_459_p2)
begin
if ((~(ap_const_logic_1 == ap_start) & (ap_ST_st12_fsm_4 == ap_CS_fsm))) begin
ap_NS_fsm = ap_ST_st0_fsm_0;
end else if (((ap_ST_st1_fsm_1 == ap_CS_fsm) & ~(ap_const_lv1_0 == or_cond_fu_244_p2) & (ap_const_lv1_0 == tmp_3_fu_250_p2))) begin
ap_NS_fsm = ap_ST_pp0_stg0_fsm_2;
end else if (((ap_ST_st1_fsm_1 == ap_CS_fsm) & ~(ap_const_lv1_0 == or_cond_fu_244_p2) & ~(ap_const_lv1_0 == tmp_3_fu_250_p2))) begin
ap_NS_fsm = ap_ST_pp1_stg0_fsm_3;
end else if ((((ap_ST_st1_fsm_1 == ap_CS_fsm) & (ap_const_lv1_0 == or_cond_fu_244_p2)) | ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it4) & ~(ap_sig_bdd_73 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it3)) & ~(ap_const_logic_1 == ap_reg_ppiten_pp0_it3)) | ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ~(ap_sig_bdd_73 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it3)) & ~(ap_const_lv1_0 == exitcond2_fu_276_p2) & ~(ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | ((ap_ST_pp1_stg0_fsm_3 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it4) & ~(ap_sig_bdd_96 & (ap_const_logic_1 == ap_reg_ppiten_pp1_it3)) & ~(ap_const_logic_1 == ap_reg_ppiten_pp1_it3)) | ((ap_ST_pp1_stg0_fsm_3 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & ~(ap_sig_bdd_96 & (ap_const_logic_1 == ap_reg_ppiten_pp1_it3)) & ~(ap_const_lv1_0 == exitcond_fu_459_p2) & ~(ap_const_logic_1 == ap_reg_ppiten_pp1_it1)))) begin
ap_NS_fsm = ap_ST_st12_fsm_4;
end else if ((((ap_ST_st0_fsm_0 == ap_CS_fsm) & (ap_const_logic_1 == ap_start)) | ((ap_const_logic_1 == ap_start) & (ap_ST_st12_fsm_4 == ap_CS_fsm)))) begin
ap_NS_fsm = ap_ST_st1_fsm_1;
end else begin
ap_NS_fsm = ap_CS_fsm;
end
end
/// ap_done assign process. ///
always @ (ap_CS_fsm)
begin
if (((ap_ST_st0_fsm_0 == ap_CS_fsm) | (ap_ST_st12_fsm_4 == ap_CS_fsm))) begin
ap_done = ap_const_logic_1;
end else begin
ap_done = ap_const_logic_0;
end
end
/// ap_idle assign process. ///
always @ (ap_CS_fsm)
begin
if ((ap_ST_st0_fsm_0 == ap_CS_fsm)) begin
ap_idle = ap_const_logic_1;
end else begin
ap_idle = ap_const_logic_0;
end
end
/// d_address0 assign process. ///
always @ (ap_CS_fsm or ap_reg_ppiten_pp0_it1 or exitcond2_reg_672 or ap_sig_bdd_73 or ap_reg_ppiten_pp0_it3 or ap_reg_ppiten_pp1_it1 or exitcond_reg_736 or ap_sig_bdd_96 or ap_reg_ppiten_pp1_it3 or tmp_12_fu_346_p1 or tmp_5_fu_529_p1)
begin
if (((ap_ST_pp1_stg0_fsm_3 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & ~(ap_sig_bdd_96 & (ap_const_logic_1 == ap_reg_ppiten_pp1_it3)) & (ap_const_lv1_0 == exitcond_reg_736))) begin
d_address0 = tmp_5_fu_529_p1;
end else if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & ~(ap_sig_bdd_73 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it3)) & (exitcond2_reg_672 == ap_const_lv1_0))) begin
d_address0 = tmp_12_fu_346_p1;
end else begin
d_address0 = tmp_5_fu_529_p1;
end
end
/// d_address1 assign process. ///
always @ (ap_CS_fsm or ap_reg_ppiten_pp0_it1 or exitcond2_reg_672 or ap_sig_bdd_73 or ap_reg_ppiten_pp0_it3 or ap_reg_ppiten_pp1_it1 or exitcond_reg_736 or ap_sig_bdd_96 or ap_reg_ppiten_pp1_it3 or tmp_14_fu_366_p1 or tmp_6_fu_549_p1)
begin
if (((ap_ST_pp1_stg0_fsm_3 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & ~(ap_sig_bdd_96 & (ap_const_logic_1 == ap_reg_ppiten_pp1_it3)) & (ap_const_lv1_0 == exitcond_reg_736))) begin
d_address1 = tmp_6_fu_549_p1;
end else if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & ~(ap_sig_bdd_73 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it3)) & (exitcond2_reg_672 == ap_const_lv1_0))) begin
d_address1 = tmp_14_fu_366_p1;
end else begin
d_address1 = tmp_6_fu_549_p1;
end
end
/// d_ce0 assign process. ///
always @ (ap_CS_fsm or ap_reg_ppiten_pp0_it1 or exitcond2_reg_672 or ap_sig_bdd_73 or ap_reg_ppiten_pp0_it3 or ap_reg_ppiten_pp1_it1 or exitcond_reg_736 or ap_sig_bdd_96 or ap_reg_ppiten_pp1_it3)
begin
if ((((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & ~(ap_sig_bdd_73 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it3)) & (exitcond2_reg_672 == ap_const_lv1_0)) | ((ap_ST_pp1_stg0_fsm_3 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & ~(ap_sig_bdd_96 & (ap_const_logic_1 == ap_reg_ppiten_pp1_it3)) & (ap_const_lv1_0 == exitcond_reg_736)))) begin
d_ce0 = ap_const_logic_1;
end else begin
d_ce0 = ap_const_logic_0;
end
end
/// d_ce1 assign process. ///
always @ (ap_CS_fsm or ap_reg_ppiten_pp0_it1 or exitcond2_reg_672 or ap_sig_bdd_73 or ap_reg_ppiten_pp0_it3 or ap_reg_ppiten_pp1_it1 or exitcond_reg_736 or ap_sig_bdd_96 or ap_reg_ppiten_pp1_it3)
begin
if ((((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & ~(ap_sig_bdd_73 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it3)) & (exitcond2_reg_672 == ap_const_lv1_0)) | ((ap_ST_pp1_stg0_fsm_3 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & ~(ap_sig_bdd_96 & (ap_const_logic_1 == ap_reg_ppiten_pp1_it3)) & (ap_const_lv1_0 == exitcond_reg_736)))) begin
d_ce1 = ap_const_logic_1;
end else begin
d_ce1 = ap_const_logic_0;
end
end
/// i_1_phi_fu_150_p4 assign process. ///
always @ (ap_CS_fsm or i_1_reg_146 or ap_reg_ppiten_pp0_it1 or exitcond2_reg_672 or i_1_mid2_reg_694)
begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (exitcond2_reg_672 == ap_const_lv1_0))) begin
i_1_phi_fu_150_p4 = i_1_mid2_reg_694;
end else begin
i_1_phi_fu_150_p4 = i_1_reg_146;
end
end
/// i_phi_fu_194_p4 assign process. ///
always @ (ap_CS_fsm or i_reg_190 or ap_reg_ppiten_pp1_it1 or exitcond_reg_736 or i_mid2_reg_758)
begin
if (((ap_ST_pp1_stg0_fsm_3 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_const_lv1_0 == exitcond_reg_736))) begin
i_phi_fu_194_p4 = i_mid2_reg_758;
end else begin
i_phi_fu_194_p4 = i_reg_190;
end
end
/// indvar1_phi_fu_205_p4 assign process. ///
always @ (ap_CS_fsm or indvar1_reg_201 or ap_reg_ppiten_pp1_it1 or exitcond_reg_736 or indvar_next1_fu_559_p2)
begin
if (((ap_ST_pp1_stg0_fsm_3 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_const_lv1_0 == exitcond_reg_736))) begin
indvar1_phi_fu_205_p4 = indvar_next1_fu_559_p2;
end else begin
indvar1_phi_fu_205_p4 = indvar1_reg_201;
end
end
/// indvar_flatten1_phi_fu_139_p4 assign process. ///
always @ (ap_CS_fsm or indvar_flatten1_reg_135 or ap_reg_ppiten_pp0_it1 or exitcond2_reg_672 or indvar_flatten_next1_reg_676)
begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (exitcond2_reg_672 == ap_const_lv1_0))) begin
indvar_flatten1_phi_fu_139_p4 = indvar_flatten_next1_reg_676;
end else begin
indvar_flatten1_phi_fu_139_p4 = indvar_flatten1_reg_135;
end
end
/// indvar_flatten_phi_fu_183_p4 assign process. ///
always @ (ap_CS_fsm or indvar_flatten_reg_179 or ap_reg_ppiten_pp1_it1 or exitcond_reg_736 or indvar_flatten_next_reg_740)
begin
if (((ap_ST_pp1_stg0_fsm_3 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_const_lv1_0 == exitcond_reg_736))) begin
indvar_flatten_phi_fu_183_p4 = indvar_flatten_next_reg_740;
end else begin
indvar_flatten_phi_fu_183_p4 = indvar_flatten_reg_179;
end
end
/// indvar_phi_fu_161_p4 assign process. ///
always @ (ap_CS_fsm or indvar_reg_157 or ap_reg_ppiten_pp0_it1 or exitcond2_reg_672 or indvar_next_fu_376_p2)
begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (exitcond2_reg_672 == ap_const_lv1_0))) begin
indvar_phi_fu_161_p4 = indvar_next_fu_376_p2;
end else begin
indvar_phi_fu_161_p4 = indvar_reg_157;
end
end
/// j_1_phi_fu_172_p4 assign process. ///
always @ (ap_CS_fsm or j_1_reg_168 or ap_reg_ppiten_pp0_it1 or exitcond2_reg_672 or tmp_18_fu_371_p2)
begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (exitcond2_reg_672 == ap_const_lv1_0))) begin
j_1_phi_fu_172_p4 = tmp_18_fu_371_p2;
end else begin
j_1_phi_fu_172_p4 = j_1_reg_168;
end
end
/// j_phi_fu_216_p4 assign process. ///
always @ (ap_CS_fsm or j_reg_212 or ap_reg_ppiten_pp1_it1 or exitcond_reg_736 or tmp_10_fu_554_p2)
begin
if (((ap_ST_pp1_stg0_fsm_3 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_const_lv1_0 == exitcond_reg_736))) begin
j_phi_fu_216_p4 = tmp_10_fu_554_p2;
end else begin
j_phi_fu_216_p4 = j_reg_212;
end
end
assign V_bus_rsp_read = ap_const_logic_0;
assign V_bus_size = ap_const_lv32_0;
/// ap_sig_bdd_73 assign process. ///
always @ (V_bus_req_full_n or ap_reg_ppstg_exitcond2_reg_672_pp0_it2)
begin
ap_sig_bdd_73 = ((V_bus_req_full_n == ap_const_logic_0) & (ap_reg_ppstg_exitcond2_reg_672_pp0_it2 == ap_const_lv1_0));
end
/// ap_sig_bdd_96 assign process. ///
always @ (V_bus_req_full_n or ap_reg_ppstg_exitcond_reg_736_pp1_it2)
begin
ap_sig_bdd_96 = ((V_bus_req_full_n == ap_const_logic_0) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_736_pp1_it2));
end
assign counter_cast_fu_256_p1 = {{12{1'b0}}, {counter}};
assign d_addr1_fu_360_p2 = (d_addr3_cast_fu_336_p1 + tmp_16_trn_cast_fu_356_p1);
assign d_addr3_cast_fu_336_p1 = {{1{1'b0}}, {d_addr3_fu_330_p2}};
assign d_addr3_fu_330_p2 = tmp_5_trn2_cast_fu_324_p1 << ap_const_lv13_6;
assign d_addr4_fu_340_p2 = (d_addr3_cast_fu_336_p1 + tmp_14_trn_cast_fu_327_p1);
assign d_addr6_fu_543_p2 = (d_addr8_cast_fu_519_p1 + tmp_9_trn_cast_fu_539_p1);
assign d_addr8_cast_fu_519_p1 = {{1{1'b0}}, {d_addr8_fu_513_p2}};
assign d_addr8_fu_513_p2 = tmp_4_trn7_cast_fu_507_p1 << ap_const_lv13_6;
assign d_addr9_fu_523_p2 = (d_addr8_cast_fu_519_p1 + tmp_7_trn_cast_fu_510_p1);
assign exitcond1_fu_471_p2 = (indvar1_phi_fu_205_p4 == ap_const_lv5_10? 1'b1: 1'b0);
assign exitcond2_fu_276_p2 = (indvar_flatten1_phi_fu_139_p4 == ap_const_lv11_400? 1'b1: 1'b0);
assign exitcond3_fu_288_p2 = (indvar_phi_fu_161_p4 == ap_const_lv5_10? 1'b1: 1'b0);
assign exitcond_fu_459_p2 = (indvar_flatten_phi_fu_183_p4 == ap_const_lv11_400? 1'b1: 1'b0);
assign i_1_cast_fu_381_p1 = {{6{1'b0}}, {ap_reg_ppstg_i_1_mid2_reg_694_pp0_it1}};
assign i_cast_fu_564_p1 = {{6{1'b0}}, {ap_reg_ppstg_i_mid2_reg_758_pp1_it1}};
assign indvar1_cast_fu_586_p1 = {{2{1'b0}}, {ap_reg_ppstg_indvar1_mid2_reg_745_pp1_it1}};
assign indvar_cast_fu_390_p1 = {{2{1'b0}}, {ap_reg_ppstg_indvar_mid2_reg_681_pp0_it1}};
assign indvar_next1_fu_559_p2 = (indvar1_mid2_reg_745 + ap_const_lv5_1);
assign indvar_next_fu_376_p2 = (indvar_mid2_reg_681 + ap_const_lv5_1);
assign or_cond_fu_244_p2 = (tmp_1_fu_232_p2 & tmp_2_fu_238_p2);
assign p_0_fu_436_p3 = {{tmp13_fu_432_p1}, {tmp14_fu_428_p1}};
assign p_s_fu_633_p3 = {{tmp11_fu_629_p1}, {tmp12_fu_625_p1}};
assign tmp10_fu_413_p2 = (tmp7_cast_cast_fu_409_p1 + tmp3_reg_667);
assign tmp11_fu_629_p1 = reg_228;
assign tmp12_fu_625_p1 = reg_224;
assign tmp13_fu_432_p1 = reg_228;
assign tmp14_fu_428_p1 = reg_224;
assign tmp1_cast_fu_266_p1 = {{1{1'b0}}, {tmp1_fu_260_p2}};
assign tmp1_fu_260_p2 = counter_cast_fu_256_p1 << ap_const_lv19_C;
assign tmp2_cast_fu_582_p1 = {{2{1'b0}}, {tmp2_fu_577_p2}};
assign tmp2_fu_577_p2 = (tmp1_cast_reg_662 + tmp4_cast_fu_573_p1);
assign tmp3_fu_270_p2 = (ap_const_lv20_42000 - tmp1_cast_fu_266_p1);
assign tmp4_cast_fu_573_p1 = {{7{1'b0}}, {tmp4_fu_567_p2}};
assign tmp4_fu_567_p2 = i_cast_fu_564_p1 << ap_const_lv13_6;
assign tmp5_fu_599_p2 = (tmp8_cast_fu_595_p1 | ap_const_lv15_5000);
assign tmp6_fu_384_p2 = i_1_cast_fu_381_p1 << ap_const_lv13_6;
assign tmp7_cast_cast_fu_409_p1 = {{7{1'b0}}, {tmp7_fu_403_p2}};
assign tmp7_fu_403_p2 = (tmp6_fu_384_p2 + tmp_cast_fu_399_p1);
assign tmp8_cast_fu_595_p1 = {{8{1'b0}}, {tmp8_fu_589_p2}};
assign tmp8_fu_589_p2 = indvar1_cast_fu_586_p1 << ap_const_lv7_2;
assign tmp9_fu_609_p0 = {{7{tmp5_fu_599_p2[14]}}, {tmp5_fu_599_p2}};
assign tmp9_fu_609_p2 = (tmp9_fu_609_p0 + tmp2_cast_fu_582_p1);
assign tmp_10_fu_554_p2 = (j_mid2_reg_751 + ap_const_lv7_4);
assign tmp_12_fu_346_p1 = {{50{1'b0}}, {d_addr4_fu_340_p2}};
assign tmp_13_dup_fu_310_p2 = (i_1_phi_fu_150_p4 + ap_const_lv7_1);
assign tmp_13_fu_351_p2 = (j_1_mid2_reg_687 | ap_const_lv7_2);
assign tmp_14_fu_366_p1 = {{50{1'b0}}, {d_addr1_fu_360_p2}};
assign tmp_14_trn_cast_fu_327_p1 = {{7{1'b0}}, {j_1_mid2_reg_687}};
assign tmp_15_fu_444_p1 = {{64{1'b0}}, {p_0_fu_436_p3}};
assign tmp_16_trn_cast_fu_356_p1 = {{7{1'b0}}, {tmp_13_fu_351_p2}};
assign tmp_17_fu_449_p1 = {{46{tmp_16_reg_721[17]}}, {tmp_16_reg_721}};
assign tmp_18_fu_371_p2 = (j_1_mid2_reg_687 + ap_const_lv7_4);
assign tmp_1_fu_232_p2 = (counter < ap_const_lv7_43? 1'b1: 1'b0);
assign tmp_2_fu_238_p2 = (counter > ap_const_lv7_2? 1'b1: 1'b0);
assign tmp_3_fu_250_p2 = (tag == ap_const_lv2_0? 1'b1: 1'b0);
assign tmp_4_trn7_cast_fu_507_p1 = {{6{1'b0}}, {i_mid2_reg_758}};
assign tmp_5_fu_529_p1 = {{50{1'b0}}, {d_addr9_fu_523_p2}};
assign tmp_5_trn2_cast_fu_324_p1 = {{6{1'b0}}, {i_1_mid2_reg_694}};
assign tmp_6_dup_fu_493_p2 = (i_phi_fu_194_p4 + ap_const_lv7_1);
assign tmp_6_fu_549_p1 = {{50{1'b0}}, {d_addr6_fu_543_p2}};
assign tmp_7_trn_cast_fu_510_p1 = {{7{1'b0}}, {j_mid2_reg_751}};
assign tmp_8_fu_534_p2 = (j_mid2_reg_751 | ap_const_lv7_2);
assign tmp_9_fu_646_p1 = {{44{tmp_7_reg_785[19]}}, {tmp_7_reg_785}};
assign tmp_9_trn_cast_fu_539_p1 = {{7{1'b0}}, {tmp_8_fu_534_p2}};
assign tmp_cast_fu_399_p1 = {{6{1'b0}}, {tmp_fu_393_p2}};
assign tmp_fu_393_p2 = indvar_cast_fu_390_p1 << ap_const_lv7_2;
assign tmp_s_fu_641_p1 = {{64{1'b0}}, {p_s_fu_633_p3}};
always @ (ap_clk)
begin
tmp1_cast_reg_662[0] <= 1'b0;
tmp1_cast_reg_662[1] <= 1'b0;
tmp1_cast_reg_662[2] <= 1'b0;
tmp1_cast_reg_662[3] <= 1'b0;
tmp1_cast_reg_662[4] <= 1'b0;
tmp1_cast_reg_662[5] <= 1'b0;
tmp1_cast_reg_662[6] <= 1'b0;
tmp1_cast_reg_662[7] <= 1'b0;
tmp1_cast_reg_662[8] <= 1'b0;
tmp1_cast_reg_662[9] <= 1'b0;
tmp1_cast_reg_662[10] <= 1'b0;
tmp1_cast_reg_662[11] <= 1'b0;
tmp1_cast_reg_662[19] <= 1'b0;
end
always @ (ap_clk)
begin
tmp3_reg_667[0] <= 1'b0;
tmp3_reg_667[1] <= 1'b0;
tmp3_reg_667[2] <= 1'b0;
tmp3_reg_667[3] <= 1'b0;
tmp3_reg_667[4] <= 1'b0;
tmp3_reg_667[5] <= 1'b0;
tmp3_reg_667[6] <= 1'b0;
tmp3_reg_667[7] <= 1'b0;
tmp3_reg_667[8] <= 1'b0;
tmp3_reg_667[9] <= 1'b0;
tmp3_reg_667[10] <= 1'b0;
tmp3_reg_667[11] <= 1'b0;
end
endmodule //write_r
|
// ==============================================================
// File generated by AutoESL - High-Level Synthesis System (C, C++, SystemC)
// Version: 2011.1
// Copyright (C) 2011 Xilinx Inc. All rights reserved.
//
// ==============================================================
/*-----------------------------------------------------------------------
-- AESL_FPSim_pkg.v:
-- Floating point simulation model for verilog.
--
-----------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Single precision units.
-- FAdd, FSub, FAddSub, FMul, FDiv, FSqrt
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Double precision units.
-- DAdd, DSub, DAddSub, DMul, DDiv, DSqrt
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Single precision units.
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Single precision Add.
-------------------------------------------------------------------------------
*/
module ACMP_fadd_comb(din0, din1, dout);
parameter ID = 0;
parameter NUM_STAGE = 13;
parameter din0_WIDTH = 32;
parameter din1_WIDTH = 32;
parameter dout_WIDTH = 32;
input[din0_WIDTH-1:0] din0;
input[din1_WIDTH-1:0] din1;
output[dout_WIDTH-1:0] dout;
AESL_WP_FAdd #(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH)
ACMP_FAdd_U (
.clk(1'b1),
.reset(1'b1),
.ce(1'b1),
.din0(din0),
.din1(din1),
.dout(dout));
endmodule
module ACMP_fadd(clk, reset, ce, din0, din1, dout);
parameter ID = 0;
parameter NUM_STAGE = 13;
parameter din0_WIDTH = 32;
parameter din1_WIDTH = 32;
parameter dout_WIDTH = 32;
input clk, reset, ce;
input[din0_WIDTH-1:0] din0;
input[din1_WIDTH-1:0] din1;
output[dout_WIDTH-1:0] dout;
AESL_WP_FAdd #(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH)
ACMP_FAdd_U (
.clk(clk),
.reset(reset),
.ce(ce),
.din0(din0),
.din1(din1),
.dout(dout));
endmodule
/*
-------------------------------------------------------------------------------
-- Single precision Sub.
-------------------------------------------------------------------------------
*/
module ACMP_fsub_comb (din0, din1, dout);
parameter ID = 0;
parameter NUM_STAGE = 13;
parameter din0_WIDTH = 32;
parameter din1_WIDTH = 32;
parameter dout_WIDTH = 32;
input[din0_WIDTH-1:0] din0;
input[din1_WIDTH-1:0] din1;
output[dout_WIDTH-1:0] dout;
AESL_WP_FSub #(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH)
ACMP_FSub_U(
.clk(1'b1),
.reset(1'b1),
.ce(1'b1),
.din0(din0),
.din1(din1),
.dout(dout));
endmodule
module ACMP_fsub(clk, reset, ce, din0, din1, dout);
parameter ID = 0;
parameter NUM_STAGE = 13;
parameter din0_WIDTH = 32;
parameter din1_WIDTH = 32;
parameter dout_WIDTH = 32;
input clk, reset, ce;
input[din0_WIDTH-1:0] din0;
input[din1_WIDTH-1:0] din1;
output[dout_WIDTH-1:0] dout;
AESL_WP_FSub #(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH)
ACMP_FSub_U(
.clk(clk),
.reset(reset),
.ce(ce),
.din0(din0),
.din1(din1),
.dout(dout));
endmodule
/*
-------------------------------------------------------------------------------
-- Single precision AddSub.
-------------------------------------------------------------------------------
*/
module ACMP_faddfsub_comb(opcode, din0, din1, dout);
parameter ID = 0;
parameter NUM_STAGE = 13;
parameter din0_WIDTH = 32;
parameter din1_WIDTH = 32;
parameter dout_WIDTH = 32;
input[1:0] opcode;
input[din0_WIDTH-1:0] din0;
input[din1_WIDTH-1:0] din1;
output[dout_WIDTH-1:0] dout;
AESL_WP_FAddFSub
#(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH)
ACMP_FAddFSub_U(
.clk(1'b1),
.reset(1'b1),
.ce(1'b1),
.opcode(opcode),
.din0(din0),
.din1(din1),
.dout(dout));
endmodule
module ACMP_faddfsub(clk, reset, ce, opcode, din0, din1, dout);
parameter ID = 0;
parameter NUM_STAGE = 13;
parameter din0_WIDTH = 32;
parameter din1_WIDTH = 32;
parameter dout_WIDTH = 32;
input clk, reset, ce;
input[1:0] opcode;
input[din0_WIDTH-1:0] din0;
input[din1_WIDTH-1:0] din1;
output[dout_WIDTH-1:0] dout;
AESL_WP_FAddFSub
#(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH)
ACMP_FAddFSub_U(
.clk(clk),
.reset(reset),
.ce(ce),
.opcode(opcode),
.din0(din0),
.din1(din1),
.dout(dout));
endmodule
module ACMP_fmul_comb(din0, din1, dout);
parameter ID = 0;
parameter NUM_STAGE = 13;
parameter din0_WIDTH = 32;
parameter din1_WIDTH = 32;
parameter dout_WIDTH = 32;
input[din0_WIDTH-1:0] din0;
input[din1_WIDTH-1:0] din1;
output[dout_WIDTH-1:0] dout;
AESL_WP_FMul
#(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH)
ACMP_FMul_U(
.clk(1'b1),
.reset(1'b1),
.ce(1'b1),
.din0(din0),
.din1(din1),
.dout(dout));
endmodule
module ACMP_fmul(clk, reset, ce, din0, din1, dout);
parameter ID = 0;
parameter NUM_STAGE = 13;
parameter din0_WIDTH = 32;
parameter din1_WIDTH = 32;
parameter dout_WIDTH = 32;
input clk, reset, ce;
input[din0_WIDTH-1:0] din0;
input[din1_WIDTH-1:0] din1;
output[dout_WIDTH-1:0] dout;
AESL_WP_FMul
#(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH)
ACMP_FMul_U(
.clk(clk),
.reset(reset),
.ce(ce),
.din0(din0),
.din1(din1),
.dout(dout));
endmodule
module ACMP_fdiv_comb(din0, din1, dout);
parameter ID = 0;
parameter NUM_STAGE = 13;
parameter din0_WIDTH = 32;
parameter din1_WIDTH = 32;
parameter dout_WIDTH = 32;
input[din0_WIDTH-1:0] din0;
input[din1_WIDTH-1:0] din1;
output[dout_WIDTH-1:0] dout;
AESL_WP_FDiv
#(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH)
ACMP_FDiv_U(
.clk(1'b1),
.reset(1'b1),
.ce(1'b1),
.din0(din0),
.din1(din1),
.dout(dout));
endmodule
module ACMP_fdiv(clk, reset, ce, din0, din1, dout);
parameter ID = 0;
parameter NUM_STAGE = 13;
parameter din0_WIDTH = 32;
parameter din1_WIDTH = 32;
parameter dout_WIDTH = 32;
input clk, reset, ce;
input[din0_WIDTH-1:0] din0;
input[din1_WIDTH-1:0] din1;
output[dout_WIDTH-1:0] dout;
AESL_WP_FDiv
#(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH)
ACMP_FDiv_U(
.clk(clk),
.reset(reset),
.ce(ce),
.din0(din0),
.din1(din1),
.dout(dout));
endmodule
module ACMP_fsqrt_comb (din0, din1, dout);
parameter ID = 0;
parameter NUM_STAGE = 13;
parameter din0_WIDTH = 32;
parameter din1_WIDTH = 32;
parameter dout_WIDTH = 32;
input[din0_WIDTH-1:0] din0;
input[din1_WIDTH-1:0] din1;
output[dout_WIDTH-1:0] dout;
AESL_WP_FSqrt
#(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH)
ACMP_FSqrt_U(
.clk(1'b1),
.reset(1'b1),
.ce(1'b1),
.din0(din0),
.din1(din1),
.dout(dout));
endmodule
module ACMP_fsqrt(clk, reset, ce, din0, din1, dout);
parameter ID = 0;
parameter NUM_STAGE = 13;
parameter din0_WIDTH = 32;
parameter din1_WIDTH = 32;
parameter dout_WIDTH = 32;
input clk, reset, ce;
input[din0_WIDTH-1:0] din0;
input[din1_WIDTH-1:0] din1;
output[dout_WIDTH-1:0] dout;
AESL_WP_FSqrt
#(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH)
ACMP_FSqrt_U(
.clk(clk),
.reset(reset),
.ce(ce),
.din0(din0),
.din1(din1),
.dout(dout));
endmodule
/*
-------------------------------------------------------------------------------
-- Double precision
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Double precision ADD
-------------------------------------------------------------------------------
*/
module ACMP_dadd_comb(din0, din1, dout);
parameter ID = 0;
parameter NUM_STAGE = 13;
parameter din0_WIDTH = 64;
parameter din1_WIDTH = 64;
parameter dout_WIDTH = 64;
input[din0_WIDTH-1:0] din0;
input[din1_WIDTH-1:0] din1;
output[dout_WIDTH-1:0] dout;
AESL_WP_DAdd
#(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH)
ACMP_DAdd_U(
.clk(1'b1),
.reset(1'b1),
.ce(1'b1),
.din0(din0),
.din1(din1),
.dout(dout));
endmodule
module ACMP_dadd(clk, reset, ce, din0, din1, dout);
parameter ID = 0;
parameter NUM_STAGE = 13;
parameter din0_WIDTH = 64;
parameter din1_WIDTH = 64;
parameter dout_WIDTH = 64;
input clk, reset, ce;
input[din0_WIDTH-1:0] din0;
input[din1_WIDTH-1:0] din1;
output[dout_WIDTH-1:0] dout;
AESL_WP_DAdd
#(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH)
ACMP_DAdd_U(
.clk(clk),
.reset(reset),
.ce(ce),
.din0(din0),
.din1(din1),
.dout(dout));
endmodule
/*
-------------------------------------------------------------------------------
-- Double precision Sub
-------------------------------------------------------------------------------
*/
module ACMP_dsub_comb(din0, din1, dout);
parameter ID = 0;
parameter NUM_STAGE = 13;
parameter din0_WIDTH = 64;
parameter din1_WIDTH = 64;
parameter dout_WIDTH = 64;
input[din0_WIDTH-1:0] din0;
input[din1_WIDTH-1:0] din1;
output[dout_WIDTH-1:0] dout;
AESL_WP_DSub
#(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH)
ACMP_DSub_U(
.clk(1'b1),
.reset(1'b1),
.ce(1'b1),
.din0(din0),
.din1(din1),
.dout(dout));
endmodule
module ACMP_dsub(clk, reset, ce, din0, din1, dout);
parameter ID = 0;
parameter NUM_STAGE = 13;
parameter din0_WIDTH = 64;
parameter din1_WIDTH = 64;
parameter dout_WIDTH = 64;
input clk, reset, ce;
input[din0_WIDTH-1:0] din0;
input[din1_WIDTH-1:0] din1;
output[dout_WIDTH-1:0] dout;
AESL_WP_DSub
#(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH)
ACMP_DSub_U(
.clk(clk),
.reset(reset),
.ce(ce),
.din0(din0),
.din1(din1),
.dout(dout));
endmodule
/*
-------------------------------------------------------------------------------
-- Double precision AddSub
-------------------------------------------------------------------------------
*/
module ACMP_dadddsub_comb(opcode, din0, din1, dout);
parameter ID = 0;
parameter NUM_STAGE = 13;
parameter din0_WIDTH = 64;
parameter din1_WIDTH = 64;
parameter dout_WIDTH = 64;
input[1:0] opcode;
input[din0_WIDTH-1:0] din0;
input[din1_WIDTH-1:0] din1;
output[dout_WIDTH-1:0] dout;
AESL_WP_DAddDSub
#(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH)
ACMP_DAddDSub_U(
.clk(1'b1),
.reset(1'b1),
.ce(1'b1),
.opcode(opcode),
.din0(din0),
.din1(din1),
.dout(dout));
endmodule
module ACMP_dadddsub(clk, reset, ce, opcode, din0, din1, dout);
parameter ID = 0;
parameter NUM_STAGE = 13;
parameter din0_WIDTH = 64;
parameter din1_WIDTH = 64;
parameter dout_WIDTH = 64;
input clk, reset, ce;
input[1:0] opcode;
input[din0_WIDTH-1:0] din0;
input[din1_WIDTH-1:0] din1;
output[dout_WIDTH-1:0] dout;
AESL_WP_DAddDSub
#(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH)
ACMP_DAddDSub_U(
.clk(clk),
.reset(reset),
.ce(ce),
.opcode(opcode),
.din0(din0),
.din1(din1),
.dout(dout));
endmodule
module ACMP_dmul_comb(din0, din1, dout);
parameter ID = 0;
parameter NUM_STAGE = 13;
parameter din0_WIDTH = 64;
parameter din1_WIDTH = 64;
parameter dout_WIDTH = 64;
input[din0_WIDTH-1:0] din0;
input[din1_WIDTH-1:0] din1;
output[dout_WIDTH-1:0] dout;
AESL_WP_DMul
#(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH)
ACMP_DMul_U(
.clk(1'b1),
.reset(1'b1),
.ce(1'b1),
.din0(din0),
.din1(din1),
.dout(dout));
endmodule
module ACMP_dmul(clk, reset, ce, din0, din1, dout);
parameter ID = 0;
parameter NUM_STAGE = 13;
parameter din0_WIDTH = 64;
parameter din1_WIDTH = 64;
parameter dout_WIDTH = 64;
input clk, reset, ce;
input[din0_WIDTH-1:0] din0;
input[din1_WIDTH-1:0] din1;
output[dout_WIDTH-1:0] dout;
AESL_WP_DMul
#(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH)
ACMP_DMul_U(
.clk(clk),
.reset(reset),
.ce(ce),
.din0(din0),
.din1(din1),
.dout(dout));
endmodule
module ACMP_ddiv_comb(din0, din1, dout);
parameter ID = 0;
parameter NUM_STAGE = 13;
parameter din0_WIDTH = 64;
parameter din1_WIDTH = 64;
parameter dout_WIDTH = 64;
input[din0_WIDTH-1:0] din0;
input[din1_WIDTH-1:0] din1;
output[dout_WIDTH-1:0] dout;
AESL_WP_DDiv
#(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH)
ACMP_DDiv_U(
.clk(1'b1),
.reset(1'b1),
.ce(1'b1),
.din0(din0),
.din1(din1),
.dout(dout));
endmodule
module ACMP_ddiv(clk, reset, ce, din0, din1, dout);
parameter ID = 0;
parameter NUM_STAGE = 13;
parameter din0_WIDTH = 64;
parameter din1_WIDTH = 64;
parameter dout_WIDTH = 64;
input clk, reset, ce;
input[din0_WIDTH-1:0] din0;
input[din1_WIDTH-1:0] din1;
output[dout_WIDTH-1:0] dout;
AESL_WP_DDiv
#(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH)
ACMP_DDiv_U(
.clk(clk),
.reset(reset),
.ce(ce),
.din0(din0),
.din1(din1),
.dout(dout));
endmodule
module ACMP_dsqrt_comb(din0, din1, dout);
parameter ID = 0;
parameter NUM_STAGE = 13;
parameter din0_WIDTH = 64;
parameter din1_WIDTH = 64;
parameter dout_WIDTH = 64;
input[din0_WIDTH-1:0] din0;
input[din1_WIDTH-1:0] din1;
output[dout_WIDTH-1:0] dout;
AESL_WP_DSqrt
#(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH)
ACMP_DSqrt_U(
.clk(1'b1),
.reset(1'b1),
.ce(1'b1),
.din0(din0),
.din1(din1),
.dout(dout));
endmodule
module ACMP_dsqrt(clk, reset, ce, din0, din1, dout);
parameter ID = 0;
parameter NUM_STAGE = 13;
parameter din0_WIDTH = 64;
parameter din1_WIDTH = 64;
parameter dout_WIDTH = 64;
input clk, reset, ce;
input[din0_WIDTH-1:0] din0;
input[din1_WIDTH-1:0] din1;
output[dout_WIDTH-1:0] dout;
AESL_WP_DSqrt
#(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH)
ACMP_DSqrt_U(
.clk(clk),
.reset(reset),
.ce(ce),
.din0(din0),
.din1(din1),
.dout(dout));
endmodule
/*
-------------------------------------------------------------------------------
-- Single precision Cmp (Comparator)
-------------------------------------------------------------------------------
-- Predicate values:
-- FCMP_FALSE = 0, ///< 0 0 0 0 Always false (always folded)
-- FCMP_OEQ = 1, ///< 0 0 0 1 True if ordered and equal
-- FCMP_OGT = 2, ///< 0 0 1 0 True if ordered and greater than
-- FCMP_OGE = 3, ///< 0 0 1 1 True if ordered and greater than or equal
-- FCMP_OLT = 4, ///< 0 1 0 0 True if ordered and less than
-- FCMP_OLE = 5, ///< 0 1 0 1 True if ordered and less than or equal
-- FCMP_ONE = 6, ///< 0 1 1 0 True if ordered and operands are unequal
-- FCMP_ORD = 7, ///< 0 1 1 1 True if ordered (no nans)
-- FCMP_UNO = 8, ///< 1 0 0 0 True if unordered: isnan(X) | isnan(Y)
-- FCMP_UEQ = 9, ///< 1 0 0 1 True if unordered or equal
-- FCMP_UGT =10, ///< 1 0 1 0 True if unordered or greater than
-- FCMP_UGE =11, ///< 1 0 1 1 True if unordered, greater than, or equal
-- FCMP_ULT =12, ///< 1 1 0 0 True if unordered or less than
-- FCMP_ULE =13, ///< 1 1 0 1 True if unordered, less than, or equal
-- FCMP_UNE =14, ///< 1 1 1 0 True if unordered or not equal
-- FCMP_TRUE =15, ///< 1 1 1 1 Always true (always folded)
*/
module ACMP_fcmp_comb(opcode, din0, din1, dout);
parameter ID = 0;
parameter NUM_STAGE = 12;
parameter din0_WIDTH = 32;
parameter din1_WIDTH = 32;
parameter dout_WIDTH = 1;
input[4:0] opcode;
input[din0_WIDTH-1:0] din0;
input[din1_WIDTH-1:0] din1;
output[0:0] dout;
AESL_WP_FCmp
#(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH)
ACMP_FCmp_U(
.clk(1'b1),
.reset(1'b1),
.ce(1'b1),
.opcode(opcode),
.din0(din0),
.din1(din1),
.dout(dout));
endmodule
module ACMP_fcmp(clk, reset, ce, opcode, din0, din1, dout);
parameter ID = 0;
parameter NUM_STAGE = 12;
parameter din0_WIDTH = 32;
parameter din1_WIDTH = 32;
parameter dout_WIDTH = 1;
input clk;
input reset, ce;
input[4:0] opcode;
input[din0_WIDTH-1:0] din0;
input[din1_WIDTH-1:0] din1;
output[0:0] dout;
AESL_WP_FCmp
#(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH)
ACMP_FCmp_U(
.clk(clk),
.reset(reset),
.ce(ce),
.opcode(opcode),
.din0(din0),
.din1(din1),
.dout(dout));
endmodule
/*
-------------------------------------------------------------------------------
-- Double precision Cmp (Comparator)
-------------------------------------------------------------------------------
-- Predicate values:
-- FCMP_FALSE = 0, ///< 0 0 0 0 Always false (always folded)
-- FCMP_OEQ = 1, ///< 0 0 0 1 True if ordered and equal
-- FCMP_OGT = 2, ///< 0 0 1 0 True if ordered and greater than
-- FCMP_OGE = 3, ///< 0 0 1 1 True if ordered and greater than or equal
-- FCMP_OLT = 4, ///< 0 1 0 0 True if ordered and less than
-- FCMP_OLE = 5, ///< 0 1 0 1 True if ordered and less than or equal
-- FCMP_ONE = 6, ///< 0 1 1 0 True if ordered and operands are unequal
-- FCMP_ORD = 7, ///< 0 1 1 1 True if ordered (no nans)
-- FCMP_UNO = 8, ///< 1 0 0 0 True if unordered: isnan(X) | isnan(Y)
-- FCMP_UEQ = 9, ///< 1 0 0 1 True if unordered or equal
-- FCMP_UGT =10, ///< 1 0 1 0 True if unordered or greater than
-- FCMP_UGE =11, ///< 1 0 1 1 True if unordered, greater than, or equal
-- FCMP_ULT =12, ///< 1 1 0 0 True if unordered or less than
-- FCMP_ULE =13, ///< 1 1 0 1 True if unordered, less than, or equal
-- FCMP_UNE =14, ///< 1 1 1 0 True if unordered or not equal
-- FCMP_TRUE =15, ///< 1 1 1 1 Always true (always folded)
*/
module ACMP_dcmp_comb(opcode, din0, din1, dout);
parameter ID = 0;
parameter NUM_STAGE = 12;
parameter din0_WIDTH = 64;
parameter din1_WIDTH = 64;
parameter dout_WIDTH = 1;
input[4:0] opcode;
input[din0_WIDTH-1:0] din0;
input[din1_WIDTH-1:0] din1;
output[0:0] dout;
AESL_WP_DCmp
#(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH)
ACMP_DCmp_U(
.clk(1'b1),
.reset(1'b1),
.ce(1'b1),
.opcode(opcode),
.din0(din0),
.din1(din1),
.dout(dout));
endmodule
module ACMP_dcmp(clk, reset, ce, opcode, din0, din1, dout);
parameter ID = 0;
parameter NUM_STAGE = 12;
parameter din0_WIDTH = 64;
parameter din1_WIDTH = 64;
parameter dout_WIDTH = 1;
input clk;
input reset, ce;
input[4:0] opcode;
input[din0_WIDTH-1:0] din0;
input[din1_WIDTH-1:0] din1;
output[0:0] dout;
AESL_WP_DCmp
#(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH)
ACMP_DCmp_U(
.clk(clk),
.reset(reset),
.ce(ce),
.opcode(opcode),
.din0(din0),
.din1(din1),
.dout(dout));
endmodule
/*
-------------------------------------------------------------------------------
-- Single precision to int32
-------------------------------------------------------------------------------
*/
module ACMP_fptosi_comb(din0, dout);
parameter ID = 0;
parameter NUM_STAGE = 12;
parameter din0_WIDTH = 32;
parameter dout_WIDTH = 32;
input[din0_WIDTH-1:0] din0;
output[dout_WIDTH-1:0] dout;
AESL_WP_SPToSI
#(NUM_STAGE, din0_WIDTH, dout_WIDTH)
ACMP_SPToSI_U(
.clk(1'b1),
.reset(1'b1),
.ce(1'b1),
.din0(din0),
.dout(dout));
endmodule
module ACMP_fptosi(clk, reset, ce, din0, dout);
parameter ID = 0;
parameter NUM_STAGE = 12;
parameter din0_WIDTH = 32;
parameter dout_WIDTH = 32;
input clk;
input reset, ce;
input[din0_WIDTH-1:0] din0;
output[dout_WIDTH-1:0] dout;
AESL_WP_SPToSI
#(NUM_STAGE, din0_WIDTH, dout_WIDTH)
ACMP_SPToSI_U(
.clk(clk),
.reset(reset),
.ce(ce),
.din0(din0),
.dout(dout));
endmodule
/*
-------------------------------------------------------------------------------
-- Double precision to int32
-------------------------------------------------------------------------------
*/
module ACMP_dptosi_comb(din0, dout);
parameter ID = 0;
parameter NUM_STAGE = 12;
parameter din0_WIDTH = 64;
parameter dout_WIDTH = 32;
input[din0_WIDTH-1:0] din0;
output[dout_WIDTH-1:0] dout;
AESL_WP_DPToSI
#(NUM_STAGE, din0_WIDTH, dout_WIDTH)
ACMP_DPToSI_U(
.clk(1'b1),
.reset(1'b1),
.ce(1'b1),
.din0(din0),
.dout(dout));
endmodule
module ACMP_dptosi(clk, reset, ce, din0, dout);
parameter ID = 0;
parameter NUM_STAGE = 12;
parameter din0_WIDTH = 64;
parameter dout_WIDTH = 32;
input clk;
input reset, ce;
input[din0_WIDTH-1:0] din0;
output[dout_WIDTH-1:0] dout;
AESL_WP_DPToSI
#(NUM_STAGE, din0_WIDTH, dout_WIDTH)
ACMP_DPToSI_U(
.clk(clk),
.reset(reset),
.ce(ce),
.din0(din0),
.dout(dout));
endmodule
/*
-------------------------------------------------------------------------------
-- Int32 to single precision
-------------------------------------------------------------------------------
*/
module ACMP_sitofp_comb(din0, dout);
parameter ID = 0;
parameter NUM_STAGE = 12;
parameter din0_WIDTH = 32;
parameter dout_WIDTH = 64;
input[din0_WIDTH-1:0] din0;
output[dout_WIDTH-1:0] dout;
AESL_WP_SIToSP
#(NUM_STAGE, din0_WIDTH, dout_WIDTH)
ACMP_SIToDP_U(
.clk(1'b1),
.reset(1'b1),
.ce(1'b1),
.din0(din0),
.dout(dout));
endmodule
module ACMP_sitofp(clk, reset, ce, din0, dout);
parameter ID = 0;
parameter NUM_STAGE = 12;
parameter din0_WIDTH = 32;
parameter dout_WIDTH = 64;
input clk;
input reset, ce;
input[din0_WIDTH-1:0] din0;
output[dout_WIDTH-1:0] dout;
AESL_WP_SIToSP
#(NUM_STAGE, din0_WIDTH, dout_WIDTH)
ACMP_SIToDP_U(
.clk(clk),
.reset(reset),
.ce(ce),
.din0(din0),
.dout(dout));
endmodule
/*
-------------------------------------------------------------------------------
-- Int32 to double precision
-------------------------------------------------------------------------------
*/
module ACMP_sitodp_comb(din0, dout);
parameter ID = 0;
parameter NUM_STAGE = 12;
parameter din0_WIDTH = 32;
parameter dout_WIDTH = 64;
input[din0_WIDTH-1:0] din0;
output[dout_WIDTH-1:0] dout;
AESL_WP_SIToDP
#(NUM_STAGE, din0_WIDTH, dout_WIDTH)
ACMP_SIToDP_U(
.clk(1'b1),
.reset(1'b1),
.ce(1'b1),
.din0(din0),
.dout(dout));
endmodule
module ACMP_sitodp(clk, reset, ce, din0, dout);
parameter ID = 0;
parameter NUM_STAGE = 12;
parameter din0_WIDTH = 32;
parameter dout_WIDTH = 64;
input clk;
input reset, ce;
input[din0_WIDTH-1:0] din0;
output[dout_WIDTH-1:0] dout;
AESL_WP_SIToDP
#(NUM_STAGE, din0_WIDTH, dout_WIDTH)
ACMP_SIToDP_U(
.clk(clk),
.reset(reset),
.ce(ce),
.din0(din0),
.dout(dout));
endmodule
/*
-------------------------------------------------------------------------------
-- Single precision to uint32
-------------------------------------------------------------------------------
*/
module ACMP_fptoui_comb(din0, dout);
parameter ID = 0;
parameter NUM_STAGE = 12;
parameter din0_WIDTH = 32;
parameter dout_WIDTH = 32;
input[din0_WIDTH-1:0] din0;
output[dout_WIDTH-1:0] dout;
AESL_WP_SPToUI
#(NUM_STAGE, din0_WIDTH, dout_WIDTH)
ACMP_SPToUI_U(
.clk(1'b1),
.reset(1'b1),
.ce(1'b1),
.din0(din0),
.dout(dout));
endmodule
module ACMP_fptoui(clk, reset, ce, din0, dout);
parameter ID = 0;
parameter NUM_STAGE = 12;
parameter din0_WIDTH = 32;
parameter dout_WIDTH = 32;
input clk;
input reset, ce;
input[din0_WIDTH-1:0] din0;
output[dout_WIDTH-1:0] dout;
AESL_WP_SPToUI
#(NUM_STAGE, din0_WIDTH, dout_WIDTH)
ACMP_SPToUI_U(
.clk(clk),
.reset(reset),
.ce(ce),
.din0(din0),
.dout(dout));
endmodule
/*
-------------------------------------------------------------------------------
-- Double precision to uint32
-------------------------------------------------------------------------------
*/
module ACMP_dptoui_comb(din0, dout);
parameter ID = 0;
parameter NUM_STAGE = 12;
parameter din0_WIDTH = 64;
parameter dout_WIDTH = 32;
input[din0_WIDTH-1:0] din0;
output[dout_WIDTH-1:0] dout;
AESL_WP_DPToUI
#(NUM_STAGE, din0_WIDTH, dout_WIDTH)
ACMP_DPToUI_U(
.clk(1'b1),
.reset(1'b1),
.ce(1'b1),
.din0(din0),
.dout(dout));
endmodule
module ACMP_dptoui(clk, reset, ce, din0, dout);
parameter ID = 0;
parameter NUM_STAGE = 12;
parameter din0_WIDTH = 64;
parameter dout_WIDTH = 32;
input clk;
input reset, ce;
input[din0_WIDTH-1:0] din0;
output[dout_WIDTH-1:0] dout;
AESL_WP_DPToUI
#(NUM_STAGE, din0_WIDTH, dout_WIDTH)
ACMP_DPToUI_U(
.clk(clk),
.reset(reset),
.ce(ce),
.din0(din0),
.dout(dout));
endmodule
/*
-------------------------------------------------------------------------------
-- uInt32 to single precision
-------------------------------------------------------------------------------
*/
module ACMP_uitofp_comb(din0, dout);
parameter ID = 0;
parameter NUM_STAGE = 12;
parameter din0_WIDTH = 32;
parameter dout_WIDTH = 64;
input[din0_WIDTH-1:0] din0;
output[dout_WIDTH-1:0] dout;
AESL_WP_UIToSP
#(NUM_STAGE, din0_WIDTH, dout_WIDTH)
ACMP_UIToSP_U(
.clk(1'b1),
.reset(1'b1),
.ce(1'b1),
.din0(din0),
.dout(dout));
endmodule
module ACMP_uitofp(clk, reset, ce, din0, dout);
parameter ID = 0;
parameter NUM_STAGE = 12;
parameter din0_WIDTH = 32;
parameter dout_WIDTH = 64;
input clk;
input reset, ce;
input[din0_WIDTH-1:0] din0;
output[dout_WIDTH-1:0] dout;
AESL_WP_UIToSP
#(NUM_STAGE, din0_WIDTH, dout_WIDTH)
ACMP_UIToSP_U(
.clk(clk),
.reset(reset),
.ce(ce),
.din0(din0),
.dout(dout));
endmodule
/*
-------------------------------------------------------------------------------
-- uInt32 to double precision
-------------------------------------------------------------------------------
*/
module ACMP_uitodp_comb(din0, dout);
parameter ID = 0;
parameter NUM_STAGE = 12;
parameter din0_WIDTH = 32;
parameter dout_WIDTH = 64;
input[din0_WIDTH-1:0] din0;
output[dout_WIDTH-1:0] dout;
AESL_WP_UIToDP
#(NUM_STAGE, din0_WIDTH, dout_WIDTH)
ACMP_UIToDP_U(
.clk(1'b1),
.reset(1'b1),
.ce(1'b1),
.din0(din0),
.dout(dout));
endmodule
module ACMP_uitodp(clk, reset, ce, din0, dout);
parameter ID = 0;
parameter NUM_STAGE = 12;
parameter din0_WIDTH = 32;
parameter dout_WIDTH = 64;
input clk;
input reset, ce;
input[din0_WIDTH-1:0] din0;
output[dout_WIDTH-1:0] dout;
AESL_WP_UIToDP
#(NUM_STAGE, din0_WIDTH, dout_WIDTH)
ACMP_UIToDP_U(
.clk(clk),
.reset(reset),
.ce(ce),
.din0(din0),
.dout(dout));
endmodule
/*
-------------------------------------------------------------------------------
-- single to double precision
-------------------------------------------------------------------------------
*/
module ACMP_fpext_comb(din0, dout);
parameter ID = 0;
parameter NUM_STAGE = 12;
parameter din0_WIDTH = 32;
parameter dout_WIDTH = 64;
input[din0_WIDTH-1:0] din0;
output[dout_WIDTH-1:0] dout;
AESL_WP_SPToDP
#(NUM_STAGE, din0_WIDTH, dout_WIDTH)
ACMP_fpext_U(
.clk(1'b1),
.reset(1'b1),
.ce(1'b1),
.din0(din0),
.dout(dout));
endmodule
module ACMP_fpext(clk, reset, ce, din0, dout);
parameter ID = 0;
parameter NUM_STAGE = 12;
parameter din0_WIDTH = 32;
parameter dout_WIDTH = 64;
input clk;
input reset, ce;
input[din0_WIDTH-1:0] din0;
output[dout_WIDTH-1:0] dout;
AESL_WP_SPToDP
#(NUM_STAGE, din0_WIDTH, dout_WIDTH)
ACMP_fpext_U(
.clk(clk),
.reset(reset),
.ce(ce),
.din0(din0),
.dout(dout));
endmodule
/*
-------------------------------------------------------------------------------
-- double to single precision
-------------------------------------------------------------------------------
*/
module ACMP_fptrunc_comb(din0, dout);
parameter ID = 0;
parameter NUM_STAGE = 12;
parameter din0_WIDTH = 32;
parameter dout_WIDTH = 64;
input[din0_WIDTH-1:0] din0;
output[dout_WIDTH-1:0] dout;
AESL_WP_DPToSP
#(NUM_STAGE, din0_WIDTH, dout_WIDTH)
ACMP_fptrunc_U(
.clk(1'b1),
.reset(1'b1),
.ce(1'b1),
.din0(din0),
.dout(dout));
endmodule
module ACMP_fptrunc(clk, reset, ce, din0, dout);
parameter ID = 0;
parameter NUM_STAGE = 12;
parameter din0_WIDTH = 32;
parameter dout_WIDTH = 64;
input clk;
input reset, ce;
input[din0_WIDTH-1:0] din0;
output[dout_WIDTH-1:0] dout;
AESL_WP_DPToSP
#(NUM_STAGE, din0_WIDTH, dout_WIDTH)
ACMP_fptrunc_U(
.clk(clk),
.reset(reset),
.ce(ce),
.din0(din0),
.dout(dout));
endmodule
|
// ==============================================================
// RTL generated by AutoESL - High-Level Synthesis System (C, C++, SystemC)
// Version: 2011.1
// Copyright (C) 2011 Xilinx Inc. All rights reserved.
//
// ===========================================================
`timescale 1 ns / 1 ps
module fetch (
ap_clk,
ap_rst,
ap_start,
ap_done,
ap_idle,
tag,
counter,
a_address0,
a_ce0,
a_we0,
a_d0,
a_address1,
a_ce1,
a_we1,
a_d1,
V_bus_req_din,
V_bus_req_full_n,
V_bus_req_write,
V_bus_rsp_dout,
V_bus_rsp_empty_n,
V_bus_rsp_read,
V_bus_address,
V_bus_datain,
V_bus_dataout,
V_bus_size
);
input ap_clk;
input ap_rst;
input ap_start;
output ap_done;
output ap_idle;
input [1:0] tag;
input [6:0] counter;
output [11:0] a_address0;
output a_ce0;
output a_we0;
output [31:0] a_d0;
output [11:0] a_address1;
output a_ce1;
output a_we1;
output [31:0] a_d1;
output V_bus_req_din;
input V_bus_req_full_n;
output V_bus_req_write;
input V_bus_rsp_dout;
input V_bus_rsp_empty_n;
output V_bus_rsp_read;
output [31:0] V_bus_address;
input [127:0] V_bus_datain;
output [127:0] V_bus_dataout;
output [31:0] V_bus_size;
reg ap_done;
reg ap_idle;
reg[11:0] a_address0;
reg a_ce0;
reg a_we0;
reg[31:0] a_d0;
reg[11:0] a_address1;
reg a_ce1;
reg a_we1;
reg[31:0] a_d1;
reg V_bus_req_write;
reg V_bus_rsp_read;
reg[31:0] V_bus_address;
reg [2:0] ap_CS_fsm;
reg [10:0] indvar_flatten_reg_180;
reg [6:0] i_reg_191;
reg [4:0] indvar1_reg_202;
reg [6:0] j_reg_213;
reg [10:0] indvar_flatten1_reg_224;
reg [6:0] i_1_reg_235;
reg [4:0] indvar_reg_246;
reg [6:0] j_1_reg_257;
wire [19:0] tmp3_cast_fu_303_p1;
reg [19:0] tmp3_cast_reg_835;
wire [0:0] icmp_fu_281_p2;
wire [0:0] tmp_2_fu_287_p2;
wire [19:0] tmp2_fu_321_p2;
reg [19:0] tmp2_reg_840;
wire [0:0] exitcond2_fu_327_p2;
reg [0:0] exitcond2_reg_845;
reg ap_reg_ppiten_pp0_it0;
reg ap_sig_bdd_86;
reg ap_reg_ppiten_pp0_it1;
reg ap_reg_ppiten_pp0_it2;
reg [0:0] ap_reg_ppstg_exitcond2_reg_845_pp0_it1;
reg [10:0] indvar_flatten_next_reg_849;
reg [6:0] j_mid2_reg_854;
reg [6:0] ap_reg_ppstg_j_mid2_reg_854_pp0_it1;
wire [6:0] i_mid2_fu_367_p3;
reg [6:0] i_mid2_reg_863;
reg [6:0] ap_reg_ppstg_i_mid2_reg_863_pp0_it1;
wire [19:0] tmp13_fu_409_p2;
reg [19:0] tmp13_reg_869;
reg [4:0] indvar_next1_reg_874;
reg ap_sig_bdd_119;
reg [31:0] tmp_17_reg_884;
reg [31:0] p_4_reg_889;
reg [31:0] p_5_reg_894;
reg [31:0] p_6_reg_899;
wire [6:0] tmp_25_fu_470_p2;
wire [13:0] a_addr2_cast_fu_491_p1;
reg [13:0] a_addr2_cast_reg_909;
wire [0:0] exitcond_fu_576_p2;
reg [0:0] exitcond_reg_915;
reg ap_reg_ppiten_pp1_it0;
reg ap_sig_bdd_151;
reg ap_reg_ppiten_pp1_it1;
reg ap_reg_ppiten_pp1_it2;
reg [0:0] ap_reg_ppstg_exitcond_reg_915_pp1_it1;
reg [10:0] indvar_flatten_next1_reg_919;
reg [6:0] j_1_mid2_reg_924;
reg [6:0] ap_reg_ppstg_j_1_mid2_reg_924_pp1_it1;
wire [6:0] i_1_mid2_fu_616_p3;
reg [6:0] i_1_mid2_reg_933;
reg [6:0] ap_reg_ppstg_i_1_mid2_reg_933_pp1_it1;
reg [17:0] tmp_26_reg_939;
reg [4:0] indvar_next_reg_944;
reg ap_sig_bdd_183;
reg [31:0] tmp_9_reg_954;
reg [31:0] p_1_reg_959;
reg [31:0] p_2_reg_964;
reg [31:0] p_3_reg_969;
wire [6:0] tmp_13_fu_723_p2;
wire [13:0] a_addr9_cast_fu_744_p1;
reg [13:0] a_addr9_cast_reg_979;
reg [10:0] indvar_flatten_phi_fu_184_p4;
reg [6:0] i_phi_fu_195_p4;
reg [4:0] indvar1_phi_fu_206_p4;
reg [6:0] j_phi_fu_217_p4;
reg [10:0] indvar_flatten1_phi_fu_228_p4;
reg [6:0] i_1_phi_fu_239_p4;
reg [4:0] indvar_phi_fu_250_p4;
reg [6:0] j_1_phi_fu_261_p4;
wire [63:0] tmp_18_fu_501_p1;
wire [63:0] tmp_20_fu_525_p1;
wire [63:0] tmp_22_fu_548_p1;
wire [63:0] tmp_24_fu_571_p1;
wire [63:0] tmp_3_fu_754_p1;
wire [63:0] tmp_4_fu_778_p1;
wire [63:0] tmp_10_fu_801_p1;
wire [63:0] tmp_12_fu_824_p1;
wire [63:0] tmp_16_fu_425_p1;
wire [63:0] tmp_7_fu_679_p1;
wire [31:0] tmp18_fu_475_p1;
wire [31:0] tmp12_fu_535_p1;
wire [31:0] tmp15_fu_728_p1;
wire [31:0] tmp14_fu_788_p1;
wire [31:0] tmp16_fu_511_p1;
wire [31:0] tmp8_fu_558_p1;
wire [31:0] tmp17_fu_764_p1;
wire [31:0] tmp10_fu_811_p1;
wire [0:0] tmp_1_fu_269_p3;
wire [1:0] tmp_8_fu_277_p1;
wire [18:0] counter_cast_fu_293_p1;
wire [18:0] tmp3_fu_297_p2;
wire [18:0] counter_cast2_fu_307_p1;
wire [18:0] tmp1_fu_311_p2;
wire [19:0] tmp1_cast_fu_317_p1;
wire [0:0] exitcond3_fu_339_p2;
wire [6:0] tmp_17_dup_fu_361_p2;
wire [12:0] i_cast_fu_375_p1;
wire [4:0] indvar1_mid2_fu_345_p3;
wire [6:0] indvar1_cast_fu_385_p1;
wire [6:0] tmp7_fu_389_p2;
wire [12:0] tmp6_fu_379_p2;
wire [12:0] tmp7_cast_fu_395_p1;
wire [12:0] tmp11_fu_399_p2;
wire [19:0] tmp11_cast_fu_405_p1;
wire [19:0] tmp_15_fu_420_p2;
wire [12:0] tmp_4_trn_cast_fu_479_p1;
wire [12:0] a_addr2_fu_485_p2;
wire [13:0] tmp_22_trn_cast_fu_482_p1;
wire [13:0] a_addr3_fu_495_p2;
wire [6:0] tmp_19_fu_506_p2;
wire [13:0] tmp_24_trn_cast_fu_515_p1;
wire [13:0] a_addr5_fu_519_p2;
wire [6:0] tmp_21_fu_530_p2;
wire [13:0] tmp_26_trn_cast_fu_539_p1;
wire [13:0] a_addr6_fu_543_p2;
wire [6:0] tmp_23_fu_553_p2;
wire [13:0] tmp_28_trn_cast_fu_562_p1;
wire [13:0] a_addr8_fu_566_p2;
wire [0:0] exitcond1_fu_588_p2;
wire [6:0] tmp_5_dup_fu_610_p2;
wire [12:0] i_1_cast_fu_624_p1;
wire [4:0] indvar_mid2_fu_594_p3;
wire [6:0] indvar_cast_fu_634_p1;
wire [6:0] tmp_fu_638_p2;
wire [12:0] tmp4_fu_628_p2;
wire [12:0] tmp_cast_fu_644_p1;
wire [12:0] tmp5_fu_648_p2;
wire [19:0] tmp5_cast_cast_fu_654_p1;
wire [19:0] tmp9_fu_658_p2;
wire [12:0] tmp_3_trn8_cast_fu_732_p1;
wire [12:0] a_addr9_fu_738_p2;
wire [13:0] tmp_trn_cast_fu_735_p1;
wire [13:0] a_addr_fu_748_p2;
wire [6:0] tmp_s_fu_759_p2;
wire [13:0] tmp_11_trn_cast_fu_768_p1;
wire [13:0] a_addr7_fu_772_p2;
wire [6:0] tmp_5_fu_783_p2;
wire [13:0] tmp_13_trn_cast_fu_792_p1;
wire [13:0] a_addr4_fu_796_p2;
wire [6:0] tmp_11_fu_806_p2;
wire [13:0] tmp_15_trn_cast_fu_815_p1;
wire [13:0] a_addr1_fu_819_p2;
reg [2:0] ap_NS_fsm;
parameter ap_const_logic_1 = 1'b1;
parameter ap_const_logic_0 = 1'b0;
parameter ap_ST_st0_fsm_0 = 3'b000;
parameter ap_ST_st1_fsm_1 = 3'b001;
parameter ap_ST_pp0_stg0_fsm_2 = 3'b010;
parameter ap_ST_pp0_stg1_fsm_3 = 3'b011;
parameter ap_ST_pp1_stg0_fsm_4 = 3'b100;
parameter ap_ST_pp1_stg1_fsm_5 = 3'b101;
parameter ap_ST_st12_fsm_6 = 3'b110;
parameter ap_const_lv1_0 = 1'b0;
parameter ap_const_lv11_0 = 11'b00000000000;
parameter ap_const_lv7_0 = 7'b0000000;
parameter ap_const_lv5_0 = 5'b00000;
parameter ap_const_lv32_0 = 32'b00000000000000000000000000000000;
parameter ap_const_lv32_6 = 32'b00000000000000000000000000000110;
parameter ap_const_lv2_1 = 2'b01;
parameter ap_const_lv2_0 = 2'b00;
parameter ap_const_lv19_C = 19'b0000000000000001100;
parameter ap_const_lv20_3F000 = 20'b00111111000000000000;
parameter ap_const_lv11_400 = 11'b10000000000;
parameter ap_const_lv11_1 = 11'b00000000001;
parameter ap_const_lv5_10 = 5'b10000;
parameter ap_const_lv7_1 = 7'b0000001;
parameter ap_const_lv13_6 = 13'b0000000000110;
parameter ap_const_lv7_2 = 7'b0000010;
parameter ap_const_lv5_1 = 5'b00001;
parameter ap_const_lv20_2 = 20'b00000000000000000010;
parameter ap_const_lv32_20 = 32'b00000000000000000000000000100000;
parameter ap_const_lv32_3F = 32'b00000000000000000000000000111111;
parameter ap_const_lv32_40 = 32'b00000000000000000000000001000000;
parameter ap_const_lv32_5F = 32'b00000000000000000000000001011111;
parameter ap_const_lv32_60 = 32'b00000000000000000000000001100000;
parameter ap_const_lv32_7F = 32'b00000000000000000000000001111111;
parameter ap_const_lv7_4 = 7'b0000100;
parameter ap_const_lv7_3 = 7'b0000011;
parameter ap_const_lv32_2 = 32'b00000000000000000000000000000010;
parameter ap_const_lv32_13 = 32'b00000000000000000000000000010011;
parameter ap_const_lv128_lc_1 = 128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_true = 1'b1;
/// ap_CS_fsm assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_CS_fsm
if (ap_rst == 1'b1) begin
ap_CS_fsm <= ap_ST_st0_fsm_0;
end else begin
ap_CS_fsm <= ap_NS_fsm;
end
end
/// ap_reg_ppiten_pp0_it0 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it0
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it0 <= ap_const_logic_0;
end else begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & ~(ap_sig_bdd_86 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) & ~(ap_const_lv1_0 == exitcond2_fu_327_p2))) begin
ap_reg_ppiten_pp0_it0 <= ap_const_logic_0;
end else if (((ap_ST_st1_fsm_1 == ap_CS_fsm) & (icmp_fu_281_p2 == ap_const_lv1_0) & ~(ap_const_lv1_0 == tmp_2_fu_287_p2))) begin
ap_reg_ppiten_pp0_it0 <= ap_const_logic_1;
end
end
end
/// ap_reg_ppiten_pp0_it1 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it1
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it1 <= ap_const_logic_0;
end else begin
if (((ap_const_lv1_0 == exitcond2_reg_845) & (ap_ST_pp0_stg1_fsm_3 == ap_CS_fsm) & ~((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ap_sig_bdd_119))) begin
ap_reg_ppiten_pp0_it1 <= ap_const_logic_1;
end else if ((((ap_ST_st1_fsm_1 == ap_CS_fsm) & (icmp_fu_281_p2 == ap_const_lv1_0) & ~(ap_const_lv1_0 == tmp_2_fu_287_p2)) | ((ap_ST_pp0_stg1_fsm_3 == ap_CS_fsm) & ~((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ap_sig_bdd_119) & ~(ap_const_lv1_0 == exitcond2_reg_845)))) begin
ap_reg_ppiten_pp0_it1 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp0_it2 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it2
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it2 <= ap_const_logic_0;
end else begin
if (((ap_ST_pp0_stg1_fsm_3 == ap_CS_fsm) & ~((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ap_sig_bdd_119))) begin
ap_reg_ppiten_pp0_it2 <= ap_reg_ppiten_pp0_it1;
end else if (((ap_ST_st1_fsm_1 == ap_CS_fsm) & (icmp_fu_281_p2 == ap_const_lv1_0) & ~(ap_const_lv1_0 == tmp_2_fu_287_p2))) begin
ap_reg_ppiten_pp0_it2 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp1_it0 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp1_it0
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp1_it0 <= ap_const_logic_0;
end else begin
if (((ap_ST_pp1_stg0_fsm_4 == ap_CS_fsm) & ~(ap_sig_bdd_151 & (ap_const_logic_1 == ap_reg_ppiten_pp1_it1)) & ~(ap_const_lv1_0 == exitcond_fu_576_p2))) begin
ap_reg_ppiten_pp1_it0 <= ap_const_logic_0;
end else if (((ap_ST_st1_fsm_1 == ap_CS_fsm) & ~(icmp_fu_281_p2 == ap_const_lv1_0))) begin
ap_reg_ppiten_pp1_it0 <= ap_const_logic_1;
end
end
end
/// ap_reg_ppiten_pp1_it1 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp1_it1
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp1_it1 <= ap_const_logic_0;
end else begin
if (((ap_const_lv1_0 == exitcond_reg_915) & (ap_ST_pp1_stg1_fsm_5 == ap_CS_fsm) & ~((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & ap_sig_bdd_183))) begin
ap_reg_ppiten_pp1_it1 <= ap_const_logic_1;
end else if ((((ap_ST_st1_fsm_1 == ap_CS_fsm) & ~(icmp_fu_281_p2 == ap_const_lv1_0)) | ((ap_ST_pp1_stg1_fsm_5 == ap_CS_fsm) & ~((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & ap_sig_bdd_183) & ~(ap_const_lv1_0 == exitcond_reg_915)))) begin
ap_reg_ppiten_pp1_it1 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp1_it2 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp1_it2
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp1_it2 <= ap_const_logic_0;
end else begin
if (((ap_ST_pp1_stg1_fsm_5 == ap_CS_fsm) & ~((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & ap_sig_bdd_183))) begin
ap_reg_ppiten_pp1_it2 <= ap_reg_ppiten_pp1_it1;
end else if (((ap_ST_st1_fsm_1 == ap_CS_fsm) & ~(icmp_fu_281_p2 == ap_const_lv1_0))) begin
ap_reg_ppiten_pp1_it2 <= ap_const_logic_0;
end
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (ap_ST_pp0_stg1_fsm_3 == ap_CS_fsm) & ~((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ap_sig_bdd_119) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_845_pp0_it1))) begin
a_addr2_cast_reg_909[6] <= a_addr2_cast_fu_491_p1[6];
a_addr2_cast_reg_909[7] <= a_addr2_cast_fu_491_p1[7];
a_addr2_cast_reg_909[8] <= a_addr2_cast_fu_491_p1[8];
a_addr2_cast_reg_909[9] <= a_addr2_cast_fu_491_p1[9];
a_addr2_cast_reg_909[10] <= a_addr2_cast_fu_491_p1[10];
a_addr2_cast_reg_909[11] <= a_addr2_cast_fu_491_p1[11];
a_addr2_cast_reg_909[12] <= a_addr2_cast_fu_491_p1[12];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_ST_pp1_stg1_fsm_5 == ap_CS_fsm) & ~((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & ap_sig_bdd_183) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_915_pp1_it1))) begin
a_addr9_cast_reg_979[6] <= a_addr9_cast_fu_744_p1[6];
a_addr9_cast_reg_979[7] <= a_addr9_cast_fu_744_p1[7];
a_addr9_cast_reg_979[8] <= a_addr9_cast_fu_744_p1[8];
a_addr9_cast_reg_979[9] <= a_addr9_cast_fu_744_p1[9];
a_addr9_cast_reg_979[10] <= a_addr9_cast_fu_744_p1[10];
a_addr9_cast_reg_979[11] <= a_addr9_cast_fu_744_p1[11];
a_addr9_cast_reg_979[12] <= a_addr9_cast_fu_744_p1[12];
end
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & ~(ap_sig_bdd_86 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)))) begin
ap_reg_ppstg_exitcond2_reg_845_pp0_it1 <= exitcond2_reg_845;
end
if (((ap_ST_pp1_stg0_fsm_4 == ap_CS_fsm) & ~(ap_sig_bdd_151 & (ap_const_logic_1 == ap_reg_ppiten_pp1_it1)))) begin
ap_reg_ppstg_exitcond_reg_915_pp1_it1 <= exitcond_reg_915;
end
if (((ap_ST_pp1_stg0_fsm_4 == ap_CS_fsm) & ~(ap_sig_bdd_151 & (ap_const_logic_1 == ap_reg_ppiten_pp1_it1)))) begin
ap_reg_ppstg_i_1_mid2_reg_933_pp1_it1 <= i_1_mid2_reg_933;
end
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & ~(ap_sig_bdd_86 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)))) begin
ap_reg_ppstg_i_mid2_reg_863_pp0_it1 <= i_mid2_reg_863;
end
if (((ap_ST_pp1_stg0_fsm_4 == ap_CS_fsm) & ~(ap_sig_bdd_151 & (ap_const_logic_1 == ap_reg_ppiten_pp1_it1)))) begin
ap_reg_ppstg_j_1_mid2_reg_924_pp1_it1 <= j_1_mid2_reg_924;
end
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & ~(ap_sig_bdd_86 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)))) begin
ap_reg_ppstg_j_mid2_reg_854_pp0_it1 <= j_mid2_reg_854;
end
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ~(ap_sig_bdd_86 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)))) begin
exitcond2_reg_845 <= (indvar_flatten_phi_fu_184_p4 == ap_const_lv11_400? 1'b1: 1'b0);
end
if (((ap_ST_pp1_stg0_fsm_4 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & ~(ap_sig_bdd_151 & (ap_const_logic_1 == ap_reg_ppiten_pp1_it1)))) begin
exitcond_reg_915 <= (indvar_flatten1_phi_fu_228_p4 == ap_const_lv11_400? 1'b1: 1'b0);
end
if (((ap_ST_pp1_stg0_fsm_4 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & ~(ap_sig_bdd_151 & (ap_const_logic_1 == ap_reg_ppiten_pp1_it1)) & (ap_const_lv1_0 == exitcond_fu_576_p2))) begin
if (exitcond1_fu_588_p2) begin
i_1_mid2_reg_933 <= tmp_5_dup_fu_610_p2;
end else begin
i_1_mid2_reg_933 <= i_1_phi_fu_239_p4;
end
end
if (((ap_ST_pp1_stg0_fsm_4 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond_reg_915) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & ~(ap_sig_bdd_151 & (ap_const_logic_1 == ap_reg_ppiten_pp1_it1)))) begin
i_1_reg_235 <= i_1_mid2_reg_933;
end else if (((ap_ST_st1_fsm_1 == ap_CS_fsm) & ~(icmp_fu_281_p2 == ap_const_lv1_0))) begin
i_1_reg_235 <= ap_const_lv7_0;
end
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ~(ap_sig_bdd_86 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) & (ap_const_lv1_0 == exitcond2_fu_327_p2))) begin
if (exitcond3_fu_339_p2) begin
i_mid2_reg_863 <= tmp_17_dup_fu_361_p2;
end else begin
i_mid2_reg_863 <= i_phi_fu_195_p4;
end
end
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond2_reg_845) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & ~(ap_sig_bdd_86 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)))) begin
i_reg_191 <= i_mid2_reg_863;
end else if (((ap_ST_st1_fsm_1 == ap_CS_fsm) & (icmp_fu_281_p2 == ap_const_lv1_0) & ~(ap_const_lv1_0 == tmp_2_fu_287_p2))) begin
i_reg_191 <= ap_const_lv7_0;
end
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond2_reg_845) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & ~(ap_sig_bdd_86 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)))) begin
indvar1_reg_202 <= indvar_next1_reg_874;
end else if (((ap_ST_st1_fsm_1 == ap_CS_fsm) & (icmp_fu_281_p2 == ap_const_lv1_0) & ~(ap_const_lv1_0 == tmp_2_fu_287_p2))) begin
indvar1_reg_202 <= ap_const_lv5_0;
end
if (((ap_ST_pp1_stg0_fsm_4 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond_reg_915) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & ~(ap_sig_bdd_151 & (ap_const_logic_1 == ap_reg_ppiten_pp1_it1)))) begin
indvar_flatten1_reg_224 <= indvar_flatten_next1_reg_919;
end else if (((ap_ST_st1_fsm_1 == ap_CS_fsm) & ~(icmp_fu_281_p2 == ap_const_lv1_0))) begin
indvar_flatten1_reg_224 <= ap_const_lv11_0;
end
if (((ap_ST_pp1_stg0_fsm_4 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & ~(ap_sig_bdd_151 & (ap_const_logic_1 == ap_reg_ppiten_pp1_it1)))) begin
indvar_flatten_next1_reg_919 <= (indvar_flatten1_phi_fu_228_p4 + ap_const_lv11_1);
end
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ~(ap_sig_bdd_86 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)))) begin
indvar_flatten_next_reg_849 <= (indvar_flatten_phi_fu_184_p4 + ap_const_lv11_1);
end
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond2_reg_845) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & ~(ap_sig_bdd_86 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)))) begin
indvar_flatten_reg_180 <= indvar_flatten_next_reg_849;
end else if (((ap_ST_st1_fsm_1 == ap_CS_fsm) & (icmp_fu_281_p2 == ap_const_lv1_0) & ~(ap_const_lv1_0 == tmp_2_fu_287_p2))) begin
indvar_flatten_reg_180 <= ap_const_lv11_0;
end
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ~(ap_sig_bdd_86 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) & (ap_const_lv1_0 == exitcond2_fu_327_p2))) begin
indvar_next1_reg_874 <= (indvar1_mid2_fu_345_p3 + ap_const_lv5_1);
end
if (((ap_ST_pp1_stg0_fsm_4 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & ~(ap_sig_bdd_151 & (ap_const_logic_1 == ap_reg_ppiten_pp1_it1)) & (ap_const_lv1_0 == exitcond_fu_576_p2))) begin
indvar_next_reg_944 <= (indvar_mid2_fu_594_p3 + ap_const_lv5_1);
end
if (((ap_ST_pp1_stg0_fsm_4 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond_reg_915) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & ~(ap_sig_bdd_151 & (ap_const_logic_1 == ap_reg_ppiten_pp1_it1)))) begin
indvar_reg_246 <= indvar_next_reg_944;
end else if (((ap_ST_st1_fsm_1 == ap_CS_fsm) & ~(icmp_fu_281_p2 == ap_const_lv1_0))) begin
indvar_reg_246 <= ap_const_lv5_0;
end
if (((ap_ST_pp1_stg0_fsm_4 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & ~(ap_sig_bdd_151 & (ap_const_logic_1 == ap_reg_ppiten_pp1_it1)) & (ap_const_lv1_0 == exitcond_fu_576_p2))) begin
if (exitcond1_fu_588_p2) begin
j_1_mid2_reg_924 <= ap_const_lv7_0;
end else begin
j_1_mid2_reg_924 <= j_1_phi_fu_261_p4;
end
end
if (((ap_ST_pp1_stg0_fsm_4 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond_reg_915) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & ~(ap_sig_bdd_151 & (ap_const_logic_1 == ap_reg_ppiten_pp1_it1)))) begin
j_1_reg_257 <= (j_1_mid2_reg_924 + ap_const_lv7_4);
end else if (((ap_ST_st1_fsm_1 == ap_CS_fsm) & ~(icmp_fu_281_p2 == ap_const_lv1_0))) begin
j_1_reg_257 <= ap_const_lv7_0;
end
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ~(ap_sig_bdd_86 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) & (ap_const_lv1_0 == exitcond2_fu_327_p2))) begin
if (exitcond3_fu_339_p2) begin
j_mid2_reg_854 <= ap_const_lv7_0;
end else begin
j_mid2_reg_854 <= j_phi_fu_217_p4;
end
end
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond2_reg_845) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & ~(ap_sig_bdd_86 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)))) begin
j_reg_213 <= (j_mid2_reg_854 + ap_const_lv7_4);
end else if (((ap_ST_st1_fsm_1 == ap_CS_fsm) & (icmp_fu_281_p2 == ap_const_lv1_0) & ~(ap_const_lv1_0 == tmp_2_fu_287_p2))) begin
j_reg_213 <= ap_const_lv7_0;
end
if (((ap_ST_pp1_stg0_fsm_4 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond_reg_915) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & ~(ap_sig_bdd_151 & (ap_const_logic_1 == ap_reg_ppiten_pp1_it1)))) begin
p_1_reg_959 <= {{V_bus_datain[ap_const_lv32_3F : ap_const_lv32_20]}};
end
if (((ap_ST_pp1_stg0_fsm_4 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond_reg_915) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & ~(ap_sig_bdd_151 & (ap_const_logic_1 == ap_reg_ppiten_pp1_it1)))) begin
p_2_reg_964 <= {{V_bus_datain[ap_const_lv32_5F : ap_const_lv32_40]}};
end
if (((ap_ST_pp1_stg0_fsm_4 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond_reg_915) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & ~(ap_sig_bdd_151 & (ap_const_logic_1 == ap_reg_ppiten_pp1_it1)))) begin
p_3_reg_969 <= {{V_bus_datain[ap_const_lv32_7F : ap_const_lv32_60]}};
end
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond2_reg_845) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & ~(ap_sig_bdd_86 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)))) begin
p_4_reg_889 <= {{V_bus_datain[ap_const_lv32_3F : ap_const_lv32_20]}};
end
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond2_reg_845) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & ~(ap_sig_bdd_86 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)))) begin
p_5_reg_894 <= {{V_bus_datain[ap_const_lv32_5F : ap_const_lv32_40]}};
end
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond2_reg_845) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & ~(ap_sig_bdd_86 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)))) begin
p_6_reg_899 <= {{V_bus_datain[ap_const_lv32_7F : ap_const_lv32_60]}};
end
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ~(ap_sig_bdd_86 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) & (ap_const_lv1_0 == exitcond2_fu_327_p2))) begin
tmp13_reg_869[2] <= tmp13_fu_409_p2[2];
tmp13_reg_869[3] <= tmp13_fu_409_p2[3];
tmp13_reg_869[4] <= tmp13_fu_409_p2[4];
tmp13_reg_869[5] <= tmp13_fu_409_p2[5];
tmp13_reg_869[6] <= tmp13_fu_409_p2[6];
tmp13_reg_869[7] <= tmp13_fu_409_p2[7];
tmp13_reg_869[8] <= tmp13_fu_409_p2[8];
tmp13_reg_869[9] <= tmp13_fu_409_p2[9];
tmp13_reg_869[10] <= tmp13_fu_409_p2[10];
tmp13_reg_869[11] <= tmp13_fu_409_p2[11];
tmp13_reg_869[12] <= tmp13_fu_409_p2[12];
tmp13_reg_869[13] <= tmp13_fu_409_p2[13];
tmp13_reg_869[14] <= tmp13_fu_409_p2[14];
tmp13_reg_869[15] <= tmp13_fu_409_p2[15];
tmp13_reg_869[16] <= tmp13_fu_409_p2[16];
tmp13_reg_869[17] <= tmp13_fu_409_p2[17];
tmp13_reg_869[18] <= tmp13_fu_409_p2[18];
tmp13_reg_869[19] <= tmp13_fu_409_p2[19];
end
if (((ap_ST_st1_fsm_1 == ap_CS_fsm) & ~(icmp_fu_281_p2 == ap_const_lv1_0))) begin
tmp2_reg_840[12] <= tmp2_fu_321_p2[12];
tmp2_reg_840[13] <= tmp2_fu_321_p2[13];
tmp2_reg_840[14] <= tmp2_fu_321_p2[14];
tmp2_reg_840[15] <= tmp2_fu_321_p2[15];
tmp2_reg_840[16] <= tmp2_fu_321_p2[16];
tmp2_reg_840[17] <= tmp2_fu_321_p2[17];
tmp2_reg_840[18] <= tmp2_fu_321_p2[18];
tmp2_reg_840[19] <= tmp2_fu_321_p2[19];
end
if (((ap_ST_st1_fsm_1 == ap_CS_fsm) & (icmp_fu_281_p2 == ap_const_lv1_0) & ~(ap_const_lv1_0 == tmp_2_fu_287_p2))) begin
tmp3_cast_reg_835[12] <= tmp3_cast_fu_303_p1[12];
tmp3_cast_reg_835[13] <= tmp3_cast_fu_303_p1[13];
tmp3_cast_reg_835[14] <= tmp3_cast_fu_303_p1[14];
tmp3_cast_reg_835[15] <= tmp3_cast_fu_303_p1[15];
tmp3_cast_reg_835[16] <= tmp3_cast_fu_303_p1[16];
tmp3_cast_reg_835[17] <= tmp3_cast_fu_303_p1[17];
tmp3_cast_reg_835[18] <= tmp3_cast_fu_303_p1[18];
end
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond2_reg_845) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & ~(ap_sig_bdd_86 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)))) begin
tmp_17_reg_884 <= V_bus_datain[31:0];
end
if (((ap_ST_pp1_stg0_fsm_4 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & ~(ap_sig_bdd_151 & (ap_const_logic_1 == ap_reg_ppiten_pp1_it1)) & (ap_const_lv1_0 == exitcond_fu_576_p2))) begin
tmp_26_reg_939 <= {{tmp9_fu_658_p2[ap_const_lv32_13 : ap_const_lv32_2]}};
end
if (((ap_ST_pp1_stg0_fsm_4 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond_reg_915) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & ~(ap_sig_bdd_151 & (ap_const_logic_1 == ap_reg_ppiten_pp1_it1)))) begin
tmp_9_reg_954 <= V_bus_datain[31:0];
end
end
/// V_bus_address assign process. ///
always @ (ap_CS_fsm or exitcond2_reg_845 or ap_reg_ppiten_pp0_it0 or ap_sig_bdd_119 or exitcond_reg_915 or ap_reg_ppiten_pp1_it0 or ap_sig_bdd_183 or tmp_16_fu_425_p1 or tmp_7_fu_679_p1)
begin
if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond_reg_915) & (ap_ST_pp1_stg1_fsm_5 == ap_CS_fsm) & ~((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & ap_sig_bdd_183))) begin
V_bus_address = tmp_7_fu_679_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (ap_const_lv1_0 == exitcond2_reg_845) & (ap_ST_pp0_stg1_fsm_3 == ap_CS_fsm) & ~((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ap_sig_bdd_119))) begin
V_bus_address = tmp_16_fu_425_p1;
end else begin
V_bus_address = tmp_7_fu_679_p1;
end
end
/// V_bus_req_write assign process. ///
always @ (ap_CS_fsm or exitcond2_reg_845 or ap_reg_ppiten_pp0_it0 or ap_sig_bdd_119 or exitcond_reg_915 or ap_reg_ppiten_pp1_it0 or ap_sig_bdd_183)
begin
if ((((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (ap_const_lv1_0 == exitcond2_reg_845) & (ap_ST_pp0_stg1_fsm_3 == ap_CS_fsm) & ~((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ap_sig_bdd_119)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond_reg_915) & (ap_ST_pp1_stg1_fsm_5 == ap_CS_fsm) & ~((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & ap_sig_bdd_183)))) begin
V_bus_req_write = ap_const_logic_1;
end else begin
V_bus_req_write = ap_const_logic_0;
end
end
/// V_bus_rsp_read assign process. ///
always @ (ap_CS_fsm or exitcond2_reg_845 or ap_sig_bdd_86 or ap_reg_ppiten_pp0_it1 or exitcond_reg_915 or ap_sig_bdd_151 or ap_reg_ppiten_pp1_it1)
begin
if ((((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond2_reg_845) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & ~(ap_sig_bdd_86 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1))) | ((ap_ST_pp1_stg0_fsm_4 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond_reg_915) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & ~(ap_sig_bdd_151 & (ap_const_logic_1 == ap_reg_ppiten_pp1_it1))))) begin
V_bus_rsp_read = ap_const_logic_1;
end else begin
V_bus_rsp_read = ap_const_logic_0;
end
end
/// a_address0 assign process. ///
always @ (ap_CS_fsm or ap_reg_ppiten_pp0_it0 or ap_sig_bdd_86 or ap_reg_ppiten_pp0_it1 or ap_reg_ppiten_pp0_it2 or ap_reg_ppstg_exitcond2_reg_845_pp0_it1 or ap_sig_bdd_119 or ap_reg_ppiten_pp1_it0 or ap_sig_bdd_151 or ap_reg_ppiten_pp1_it1 or ap_reg_ppiten_pp1_it2 or ap_reg_ppstg_exitcond_reg_915_pp1_it1 or ap_sig_bdd_183 or tmp_18_fu_501_p1 or tmp_22_fu_548_p1 or tmp_3_fu_754_p1 or tmp_10_fu_801_p1)
begin
if (((ap_ST_pp1_stg0_fsm_4 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it2) & ~(ap_sig_bdd_151 & (ap_const_logic_1 == ap_reg_ppiten_pp1_it1)) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_915_pp1_it1))) begin
a_address0 = tmp_10_fu_801_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_ST_pp1_stg1_fsm_5 == ap_CS_fsm) & ~((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & ap_sig_bdd_183) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_915_pp1_it1))) begin
a_address0 = tmp_3_fu_754_p1;
end else if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it2) & ~(ap_sig_bdd_86 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_845_pp0_it1))) begin
a_address0 = tmp_22_fu_548_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (ap_ST_pp0_stg1_fsm_3 == ap_CS_fsm) & ~((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ap_sig_bdd_119) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_845_pp0_it1))) begin
a_address0 = tmp_18_fu_501_p1;
end else begin
a_address0 = tmp_10_fu_801_p1;
end
end
/// a_address1 assign process. ///
always @ (ap_CS_fsm or ap_reg_ppiten_pp0_it0 or ap_sig_bdd_86 or ap_reg_ppiten_pp0_it1 or ap_reg_ppiten_pp0_it2 or ap_reg_ppstg_exitcond2_reg_845_pp0_it1 or ap_sig_bdd_119 or ap_reg_ppiten_pp1_it0 or ap_sig_bdd_151 or ap_reg_ppiten_pp1_it1 or ap_reg_ppiten_pp1_it2 or ap_reg_ppstg_exitcond_reg_915_pp1_it1 or ap_sig_bdd_183 or tmp_20_fu_525_p1 or tmp_24_fu_571_p1 or tmp_4_fu_778_p1 or tmp_12_fu_824_p1)
begin
if (((ap_ST_pp1_stg0_fsm_4 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it2) & ~(ap_sig_bdd_151 & (ap_const_logic_1 == ap_reg_ppiten_pp1_it1)) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_915_pp1_it1))) begin
a_address1 = tmp_12_fu_824_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_ST_pp1_stg1_fsm_5 == ap_CS_fsm) & ~((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & ap_sig_bdd_183) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_915_pp1_it1))) begin
a_address1 = tmp_4_fu_778_p1;
end else if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it2) & ~(ap_sig_bdd_86 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_845_pp0_it1))) begin
a_address1 = tmp_24_fu_571_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (ap_ST_pp0_stg1_fsm_3 == ap_CS_fsm) & ~((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ap_sig_bdd_119) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_845_pp0_it1))) begin
a_address1 = tmp_20_fu_525_p1;
end else begin
a_address1 = tmp_12_fu_824_p1;
end
end
/// a_ce0 assign process. ///
always @ (ap_CS_fsm or ap_reg_ppiten_pp0_it0 or ap_sig_bdd_86 or ap_reg_ppiten_pp0_it1 or ap_reg_ppiten_pp0_it2 or ap_reg_ppstg_exitcond2_reg_845_pp0_it1 or ap_sig_bdd_119 or ap_reg_ppiten_pp1_it0 or ap_sig_bdd_151 or ap_reg_ppiten_pp1_it1 or ap_reg_ppiten_pp1_it2 or ap_reg_ppstg_exitcond_reg_915_pp1_it1 or ap_sig_bdd_183)
begin
if ((((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (ap_ST_pp0_stg1_fsm_3 == ap_CS_fsm) & ~((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ap_sig_bdd_119) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_845_pp0_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_ST_pp1_stg1_fsm_5 == ap_CS_fsm) & ~((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & ap_sig_bdd_183) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_915_pp1_it1)) | ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it2) & ~(ap_sig_bdd_86 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_845_pp0_it1)) | ((ap_ST_pp1_stg0_fsm_4 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it2) & ~(ap_sig_bdd_151 & (ap_const_logic_1 == ap_reg_ppiten_pp1_it1)) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_915_pp1_it1)))) begin
a_ce0 = ap_const_logic_1;
end else begin
a_ce0 = ap_const_logic_0;
end
end
/// a_ce1 assign process. ///
always @ (ap_CS_fsm or ap_reg_ppiten_pp0_it0 or ap_sig_bdd_86 or ap_reg_ppiten_pp0_it1 or ap_reg_ppiten_pp0_it2 or ap_reg_ppstg_exitcond2_reg_845_pp0_it1 or ap_sig_bdd_119 or ap_reg_ppiten_pp1_it0 or ap_sig_bdd_151 or ap_reg_ppiten_pp1_it1 or ap_reg_ppiten_pp1_it2 or ap_reg_ppstg_exitcond_reg_915_pp1_it1 or ap_sig_bdd_183)
begin
if ((((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (ap_ST_pp0_stg1_fsm_3 == ap_CS_fsm) & ~((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ap_sig_bdd_119) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_845_pp0_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_ST_pp1_stg1_fsm_5 == ap_CS_fsm) & ~((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & ap_sig_bdd_183) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_915_pp1_it1)) | ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it2) & ~(ap_sig_bdd_86 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_845_pp0_it1)) | ((ap_ST_pp1_stg0_fsm_4 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it2) & ~(ap_sig_bdd_151 & (ap_const_logic_1 == ap_reg_ppiten_pp1_it1)) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_915_pp1_it1)))) begin
a_ce1 = ap_const_logic_1;
end else begin
a_ce1 = ap_const_logic_0;
end
end
/// a_d0 assign process. ///
always @ (ap_CS_fsm or ap_reg_ppiten_pp0_it0 or ap_sig_bdd_86 or ap_reg_ppiten_pp0_it1 or ap_reg_ppiten_pp0_it2 or ap_reg_ppstg_exitcond2_reg_845_pp0_it1 or ap_sig_bdd_119 or ap_reg_ppiten_pp1_it0 or ap_sig_bdd_151 or ap_reg_ppiten_pp1_it1 or ap_reg_ppiten_pp1_it2 or ap_reg_ppstg_exitcond_reg_915_pp1_it1 or ap_sig_bdd_183 or tmp18_fu_475_p1 or tmp12_fu_535_p1 or tmp15_fu_728_p1 or tmp14_fu_788_p1)
begin
if (((ap_ST_pp1_stg0_fsm_4 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it2) & ~(ap_sig_bdd_151 & (ap_const_logic_1 == ap_reg_ppiten_pp1_it1)) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_915_pp1_it1))) begin
a_d0 = tmp14_fu_788_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_ST_pp1_stg1_fsm_5 == ap_CS_fsm) & ~((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & ap_sig_bdd_183) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_915_pp1_it1))) begin
a_d0 = tmp15_fu_728_p1;
end else if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it2) & ~(ap_sig_bdd_86 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_845_pp0_it1))) begin
a_d0 = tmp12_fu_535_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (ap_ST_pp0_stg1_fsm_3 == ap_CS_fsm) & ~((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ap_sig_bdd_119) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_845_pp0_it1))) begin
a_d0 = tmp18_fu_475_p1;
end else begin
a_d0 = tmp14_fu_788_p1;
end
end
/// a_d1 assign process. ///
always @ (ap_CS_fsm or ap_reg_ppiten_pp0_it0 or ap_sig_bdd_86 or ap_reg_ppiten_pp0_it1 or ap_reg_ppiten_pp0_it2 or ap_reg_ppstg_exitcond2_reg_845_pp0_it1 or ap_sig_bdd_119 or ap_reg_ppiten_pp1_it0 or ap_sig_bdd_151 or ap_reg_ppiten_pp1_it1 or ap_reg_ppiten_pp1_it2 or ap_reg_ppstg_exitcond_reg_915_pp1_it1 or ap_sig_bdd_183 or tmp16_fu_511_p1 or tmp8_fu_558_p1 or tmp17_fu_764_p1 or tmp10_fu_811_p1)
begin
if (((ap_ST_pp1_stg0_fsm_4 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it2) & ~(ap_sig_bdd_151 & (ap_const_logic_1 == ap_reg_ppiten_pp1_it1)) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_915_pp1_it1))) begin
a_d1 = tmp10_fu_811_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_ST_pp1_stg1_fsm_5 == ap_CS_fsm) & ~((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & ap_sig_bdd_183) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_915_pp1_it1))) begin
a_d1 = tmp17_fu_764_p1;
end else if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it2) & ~(ap_sig_bdd_86 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_845_pp0_it1))) begin
a_d1 = tmp8_fu_558_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (ap_ST_pp0_stg1_fsm_3 == ap_CS_fsm) & ~((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ap_sig_bdd_119) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_845_pp0_it1))) begin
a_d1 = tmp16_fu_511_p1;
end else begin
a_d1 = tmp10_fu_811_p1;
end
end
/// a_we0 assign process. ///
always @ (ap_CS_fsm or ap_reg_ppiten_pp0_it0 or ap_sig_bdd_86 or ap_reg_ppiten_pp0_it1 or ap_reg_ppiten_pp0_it2 or ap_reg_ppstg_exitcond2_reg_845_pp0_it1 or ap_sig_bdd_119 or ap_reg_ppiten_pp1_it0 or ap_sig_bdd_151 or ap_reg_ppiten_pp1_it1 or ap_reg_ppiten_pp1_it2 or ap_reg_ppstg_exitcond_reg_915_pp1_it1 or ap_sig_bdd_183)
begin
if ((((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (ap_ST_pp0_stg1_fsm_3 == ap_CS_fsm) & ~((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ap_sig_bdd_119) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_845_pp0_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_ST_pp1_stg1_fsm_5 == ap_CS_fsm) & ~((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & ap_sig_bdd_183) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_915_pp1_it1)) | ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it2) & ~(ap_sig_bdd_86 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_845_pp0_it1)) | ((ap_ST_pp1_stg0_fsm_4 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it2) & ~(ap_sig_bdd_151 & (ap_const_logic_1 == ap_reg_ppiten_pp1_it1)) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_915_pp1_it1)))) begin
a_we0 = ap_const_logic_1;
end else begin
a_we0 = ap_const_logic_0;
end
end
/// a_we1 assign process. ///
always @ (ap_CS_fsm or ap_reg_ppiten_pp0_it0 or ap_sig_bdd_86 or ap_reg_ppiten_pp0_it1 or ap_reg_ppiten_pp0_it2 or ap_reg_ppstg_exitcond2_reg_845_pp0_it1 or ap_sig_bdd_119 or ap_reg_ppiten_pp1_it0 or ap_sig_bdd_151 or ap_reg_ppiten_pp1_it1 or ap_reg_ppiten_pp1_it2 or ap_reg_ppstg_exitcond_reg_915_pp1_it1 or ap_sig_bdd_183)
begin
if ((((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (ap_ST_pp0_stg1_fsm_3 == ap_CS_fsm) & ~((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ap_sig_bdd_119) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_845_pp0_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_ST_pp1_stg1_fsm_5 == ap_CS_fsm) & ~((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & ap_sig_bdd_183) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_915_pp1_it1)) | ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it2) & ~(ap_sig_bdd_86 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_845_pp0_it1)) | ((ap_ST_pp1_stg0_fsm_4 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it2) & ~(ap_sig_bdd_151 & (ap_const_logic_1 == ap_reg_ppiten_pp1_it1)) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_915_pp1_it1)))) begin
a_we1 = ap_const_logic_1;
end else begin
a_we1 = ap_const_logic_0;
end
end
/// ap_NS_fsm assign process. ///
always @ (ap_start or ap_CS_fsm or icmp_fu_281_p2 or tmp_2_fu_287_p2 or exitcond2_fu_327_p2 or ap_reg_ppiten_pp0_it0 or ap_sig_bdd_86 or ap_reg_ppiten_pp0_it1 or ap_reg_ppiten_pp0_it2 or ap_sig_bdd_119 or exitcond_fu_576_p2 or ap_reg_ppiten_pp1_it0 or ap_sig_bdd_151 or ap_reg_ppiten_pp1_it1 or ap_reg_ppiten_pp1_it2 or ap_sig_bdd_183)
begin
if (((ap_ST_pp1_stg0_fsm_4 == ap_CS_fsm) & ~(ap_sig_bdd_151 & (ap_const_logic_1 == ap_reg_ppiten_pp1_it1)) & ~((ap_ST_pp1_stg0_fsm_4 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it2) & ~(ap_sig_bdd_151 & (ap_const_logic_1 == ap_reg_ppiten_pp1_it1)) & ~(ap_const_logic_1 == ap_reg_ppiten_pp1_it1)) & ~((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & ~(ap_sig_bdd_151 & (ap_const_logic_1 == ap_reg_ppiten_pp1_it1)) & ~(ap_const_lv1_0 == exitcond_fu_576_p2) & ~(ap_const_logic_1 == ap_reg_ppiten_pp1_it1)))) begin
ap_NS_fsm = ap_ST_pp1_stg1_fsm_5;
end else if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & ~(ap_sig_bdd_86 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) & ~((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it2) & ~(ap_sig_bdd_86 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) & ~(ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) & ~((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ~(ap_sig_bdd_86 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) & ~(ap_const_lv1_0 == exitcond2_fu_327_p2) & ~(ap_const_logic_1 == ap_reg_ppiten_pp0_it1)))) begin
ap_NS_fsm = ap_ST_pp0_stg1_fsm_3;
end else if ((~(ap_const_logic_1 == ap_start) & (ap_ST_st12_fsm_6 == ap_CS_fsm))) begin
ap_NS_fsm = ap_ST_st0_fsm_0;
end else if ((((ap_ST_st1_fsm_1 == ap_CS_fsm) & ~(icmp_fu_281_p2 == ap_const_lv1_0)) | ((ap_ST_pp1_stg1_fsm_5 == ap_CS_fsm) & ~((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & ap_sig_bdd_183)))) begin
ap_NS_fsm = ap_ST_pp1_stg0_fsm_4;
end else if ((((ap_ST_st1_fsm_1 == ap_CS_fsm) & (icmp_fu_281_p2 == ap_const_lv1_0) & ~(ap_const_lv1_0 == tmp_2_fu_287_p2)) | ((ap_ST_pp0_stg1_fsm_3 == ap_CS_fsm) & ~((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ap_sig_bdd_119)))) begin
ap_NS_fsm = ap_ST_pp0_stg0_fsm_2;
end else if ((((ap_ST_st1_fsm_1 == ap_CS_fsm) & (icmp_fu_281_p2 == ap_const_lv1_0) & (ap_const_lv1_0 == tmp_2_fu_287_p2)) | ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it2) & ~(ap_sig_bdd_86 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) & ~(ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ~(ap_sig_bdd_86 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) & ~(ap_const_lv1_0 == exitcond2_fu_327_p2) & ~(ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | ((ap_ST_pp1_stg0_fsm_4 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it2) & ~(ap_sig_bdd_151 & (ap_const_logic_1 == ap_reg_ppiten_pp1_it1)) & ~(ap_const_logic_1 == ap_reg_ppiten_pp1_it1)) | ((ap_ST_pp1_stg0_fsm_4 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & ~(ap_sig_bdd_151 & (ap_const_logic_1 == ap_reg_ppiten_pp1_it1)) & ~(ap_const_lv1_0 == exitcond_fu_576_p2) & ~(ap_const_logic_1 == ap_reg_ppiten_pp1_it1)))) begin
ap_NS_fsm = ap_ST_st12_fsm_6;
end else if ((((ap_ST_st0_fsm_0 == ap_CS_fsm) & (ap_const_logic_1 == ap_start)) | ((ap_const_logic_1 == ap_start) & (ap_ST_st12_fsm_6 == ap_CS_fsm)))) begin
ap_NS_fsm = ap_ST_st1_fsm_1;
end else begin
ap_NS_fsm = ap_CS_fsm;
end
end
/// ap_done assign process. ///
always @ (ap_CS_fsm)
begin
if (((ap_ST_st0_fsm_0 == ap_CS_fsm) | (ap_ST_st12_fsm_6 == ap_CS_fsm))) begin
ap_done = ap_const_logic_1;
end else begin
ap_done = ap_const_logic_0;
end
end
/// ap_idle assign process. ///
always @ (ap_CS_fsm)
begin
if ((ap_ST_st0_fsm_0 == ap_CS_fsm)) begin
ap_idle = ap_const_logic_1;
end else begin
ap_idle = ap_const_logic_0;
end
end
/// i_1_phi_fu_239_p4 assign process. ///
always @ (ap_CS_fsm or i_1_reg_235 or exitcond_reg_915 or ap_reg_ppiten_pp1_it1 or i_1_mid2_reg_933)
begin
if (((ap_ST_pp1_stg0_fsm_4 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond_reg_915) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it1))) begin
i_1_phi_fu_239_p4 = i_1_mid2_reg_933;
end else begin
i_1_phi_fu_239_p4 = i_1_reg_235;
end
end
/// i_phi_fu_195_p4 assign process. ///
always @ (ap_CS_fsm or i_reg_191 or exitcond2_reg_845 or ap_reg_ppiten_pp0_it1 or i_mid2_reg_863)
begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond2_reg_845) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1))) begin
i_phi_fu_195_p4 = i_mid2_reg_863;
end else begin
i_phi_fu_195_p4 = i_reg_191;
end
end
/// indvar1_phi_fu_206_p4 assign process. ///
always @ (ap_CS_fsm or indvar1_reg_202 or exitcond2_reg_845 or ap_reg_ppiten_pp0_it1 or indvar_next1_reg_874)
begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond2_reg_845) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1))) begin
indvar1_phi_fu_206_p4 = indvar_next1_reg_874;
end else begin
indvar1_phi_fu_206_p4 = indvar1_reg_202;
end
end
/// indvar_flatten1_phi_fu_228_p4 assign process. ///
always @ (ap_CS_fsm or indvar_flatten1_reg_224 or exitcond_reg_915 or ap_reg_ppiten_pp1_it1 or indvar_flatten_next1_reg_919)
begin
if (((ap_ST_pp1_stg0_fsm_4 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond_reg_915) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it1))) begin
indvar_flatten1_phi_fu_228_p4 = indvar_flatten_next1_reg_919;
end else begin
indvar_flatten1_phi_fu_228_p4 = indvar_flatten1_reg_224;
end
end
/// indvar_flatten_phi_fu_184_p4 assign process. ///
always @ (ap_CS_fsm or indvar_flatten_reg_180 or exitcond2_reg_845 or ap_reg_ppiten_pp0_it1 or indvar_flatten_next_reg_849)
begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond2_reg_845) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1))) begin
indvar_flatten_phi_fu_184_p4 = indvar_flatten_next_reg_849;
end else begin
indvar_flatten_phi_fu_184_p4 = indvar_flatten_reg_180;
end
end
/// indvar_phi_fu_250_p4 assign process. ///
always @ (ap_CS_fsm or indvar_reg_246 or exitcond_reg_915 or ap_reg_ppiten_pp1_it1 or indvar_next_reg_944)
begin
if (((ap_ST_pp1_stg0_fsm_4 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond_reg_915) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it1))) begin
indvar_phi_fu_250_p4 = indvar_next_reg_944;
end else begin
indvar_phi_fu_250_p4 = indvar_reg_246;
end
end
/// j_1_phi_fu_261_p4 assign process. ///
always @ (ap_CS_fsm or j_1_reg_257 or exitcond_reg_915 or ap_reg_ppiten_pp1_it1 or tmp_13_fu_723_p2)
begin
if (((ap_ST_pp1_stg0_fsm_4 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond_reg_915) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it1))) begin
j_1_phi_fu_261_p4 = tmp_13_fu_723_p2;
end else begin
j_1_phi_fu_261_p4 = j_1_reg_257;
end
end
/// j_phi_fu_217_p4 assign process. ///
always @ (ap_CS_fsm or j_reg_213 or exitcond2_reg_845 or ap_reg_ppiten_pp0_it1 or tmp_25_fu_470_p2)
begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond2_reg_845) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1))) begin
j_phi_fu_217_p4 = tmp_25_fu_470_p2;
end else begin
j_phi_fu_217_p4 = j_reg_213;
end
end
assign V_bus_dataout = ap_const_lv128_lc_1;
assign V_bus_req_din = ap_const_logic_0;
assign V_bus_size = ap_const_lv32_0;
assign a_addr1_fu_819_p2 = (a_addr9_cast_reg_979 + tmp_15_trn_cast_fu_815_p1);
assign a_addr2_cast_fu_491_p1 = {{1{1'b0}}, {a_addr2_fu_485_p2}};
assign a_addr2_fu_485_p2 = tmp_4_trn_cast_fu_479_p1 << ap_const_lv13_6;
assign a_addr3_fu_495_p2 = (a_addr2_cast_fu_491_p1 + tmp_22_trn_cast_fu_482_p1);
assign a_addr4_fu_796_p2 = (a_addr9_cast_reg_979 + tmp_13_trn_cast_fu_792_p1);
assign a_addr5_fu_519_p2 = (a_addr2_cast_fu_491_p1 + tmp_24_trn_cast_fu_515_p1);
assign a_addr6_fu_543_p2 = (a_addr2_cast_reg_909 + tmp_26_trn_cast_fu_539_p1);
assign a_addr7_fu_772_p2 = (a_addr9_cast_fu_744_p1 + tmp_11_trn_cast_fu_768_p1);
assign a_addr8_fu_566_p2 = (a_addr2_cast_reg_909 + tmp_28_trn_cast_fu_562_p1);
assign a_addr9_cast_fu_744_p1 = {{1{1'b0}}, {a_addr9_fu_738_p2}};
assign a_addr9_fu_738_p2 = tmp_3_trn8_cast_fu_732_p1 << ap_const_lv13_6;
assign a_addr_fu_748_p2 = (a_addr9_cast_fu_744_p1 + tmp_trn_cast_fu_735_p1);
/// ap_sig_bdd_119 assign process. ///
always @ (V_bus_req_full_n or exitcond2_reg_845)
begin
ap_sig_bdd_119 = ((ap_const_lv1_0 == exitcond2_reg_845) & (V_bus_req_full_n == ap_const_logic_0));
end
/// ap_sig_bdd_151 assign process. ///
always @ (V_bus_rsp_empty_n or exitcond_reg_915)
begin
ap_sig_bdd_151 = ((V_bus_rsp_empty_n == ap_const_logic_0) & (ap_const_lv1_0 == exitcond_reg_915));
end
/// ap_sig_bdd_183 assign process. ///
always @ (V_bus_req_full_n or exitcond_reg_915)
begin
ap_sig_bdd_183 = ((V_bus_req_full_n == ap_const_logic_0) & (ap_const_lv1_0 == exitcond_reg_915));
end
/// ap_sig_bdd_86 assign process. ///
always @ (V_bus_rsp_empty_n or exitcond2_reg_845)
begin
ap_sig_bdd_86 = ((V_bus_rsp_empty_n == ap_const_logic_0) & (ap_const_lv1_0 == exitcond2_reg_845));
end
assign counter_cast2_fu_307_p1 = {{12{1'b0}}, {counter}};
assign counter_cast_fu_293_p1 = {{12{1'b0}}, {counter}};
assign exitcond1_fu_588_p2 = (indvar_phi_fu_250_p4 == ap_const_lv5_10? 1'b1: 1'b0);
assign exitcond2_fu_327_p2 = (indvar_flatten_phi_fu_184_p4 == ap_const_lv11_400? 1'b1: 1'b0);
assign exitcond3_fu_339_p2 = (indvar1_phi_fu_206_p4 == ap_const_lv5_10? 1'b1: 1'b0);
assign exitcond_fu_576_p2 = (indvar_flatten1_phi_fu_228_p4 == ap_const_lv11_400? 1'b1: 1'b0);
assign i_1_cast_fu_624_p1 = {{6{1'b0}}, {i_1_mid2_fu_616_p3}};
assign i_1_mid2_fu_616_p3 = ((exitcond1_fu_588_p2)? tmp_5_dup_fu_610_p2: i_1_phi_fu_239_p4);
assign i_cast_fu_375_p1 = {{6{1'b0}}, {i_mid2_fu_367_p3}};
assign i_mid2_fu_367_p3 = ((exitcond3_fu_339_p2)? tmp_17_dup_fu_361_p2: i_phi_fu_195_p4);
assign icmp_fu_281_p2 = (tmp_8_fu_277_p1 == ap_const_lv2_1? 1'b1: 1'b0);
assign indvar1_cast_fu_385_p1 = {{2{1'b0}}, {indvar1_mid2_fu_345_p3}};
assign indvar1_mid2_fu_345_p3 = ((exitcond3_fu_339_p2)? ap_const_lv5_0: indvar1_phi_fu_206_p4);
assign indvar_cast_fu_634_p1 = {{2{1'b0}}, {indvar_mid2_fu_594_p3}};
assign indvar_mid2_fu_594_p3 = ((exitcond1_fu_588_p2)? ap_const_lv5_0: indvar_phi_fu_250_p4);
assign tmp10_fu_811_p1 = p_3_reg_969;
assign tmp11_cast_fu_405_p1 = {{7{1'b0}}, {tmp11_fu_399_p2}};
assign tmp11_fu_399_p2 = (tmp6_fu_379_p2 + tmp7_cast_fu_395_p1);
assign tmp12_fu_535_p1 = p_5_reg_894;
assign tmp13_fu_409_p2 = (tmp11_cast_fu_405_p1 + tmp3_cast_reg_835);
assign tmp14_fu_788_p1 = p_2_reg_964;
assign tmp15_fu_728_p1 = tmp_9_reg_954;
assign tmp16_fu_511_p1 = p_4_reg_889;
assign tmp17_fu_764_p1 = p_1_reg_959;
assign tmp18_fu_475_p1 = tmp_17_reg_884;
assign tmp1_cast_fu_317_p1 = {{1{1'b0}}, {tmp1_fu_311_p2}};
assign tmp1_fu_311_p2 = counter_cast2_fu_307_p1 << ap_const_lv19_C;
assign tmp2_fu_321_p2 = (ap_const_lv20_3F000 - tmp1_cast_fu_317_p1);
assign tmp3_cast_fu_303_p1 = {{1{1'b0}}, {tmp3_fu_297_p2}};
assign tmp3_fu_297_p2 = counter_cast_fu_293_p1 << ap_const_lv19_C;
assign tmp4_fu_628_p2 = i_1_cast_fu_624_p1 << ap_const_lv13_6;
assign tmp5_cast_cast_fu_654_p1 = {{7{1'b0}}, {tmp5_fu_648_p2}};
assign tmp5_fu_648_p2 = (tmp4_fu_628_p2 + tmp_cast_fu_644_p1);
assign tmp6_fu_379_p2 = i_cast_fu_375_p1 << ap_const_lv13_6;
assign tmp7_cast_fu_395_p1 = {{6{1'b0}}, {tmp7_fu_389_p2}};
assign tmp7_fu_389_p2 = indvar1_cast_fu_385_p1 << ap_const_lv7_2;
assign tmp8_fu_558_p1 = p_6_reg_899;
assign tmp9_fu_658_p2 = (tmp5_cast_cast_fu_654_p1 + tmp2_reg_840);
assign tmp_10_fu_801_p1 = {{50{1'b0}}, {a_addr4_fu_796_p2}};
assign tmp_11_fu_806_p2 = (ap_reg_ppstg_j_1_mid2_reg_924_pp1_it1 | ap_const_lv7_3);
assign tmp_11_trn_cast_fu_768_p1 = {{7{1'b0}}, {tmp_s_fu_759_p2}};
assign tmp_12_fu_824_p1 = {{50{1'b0}}, {a_addr1_fu_819_p2}};
assign tmp_13_fu_723_p2 = (j_1_mid2_reg_924 + ap_const_lv7_4);
assign tmp_13_trn_cast_fu_792_p1 = {{7{1'b0}}, {tmp_5_fu_783_p2}};
assign tmp_15_fu_420_p2 = tmp13_reg_869 >> ap_const_lv20_2;
assign tmp_15_trn_cast_fu_815_p1 = {{7{1'b0}}, {tmp_11_fu_806_p2}};
assign tmp_16_fu_425_p1 = {{44{1'b0}}, {tmp_15_fu_420_p2}};
assign tmp_17_dup_fu_361_p2 = (i_phi_fu_195_p4 + ap_const_lv7_1);
assign tmp_18_fu_501_p1 = {{50{1'b0}}, {a_addr3_fu_495_p2}};
assign tmp_19_fu_506_p2 = (ap_reg_ppstg_j_mid2_reg_854_pp0_it1 | ap_const_lv7_1);
assign tmp_1_fu_269_p3 = counter[ap_const_lv32_6];
assign tmp_20_fu_525_p1 = {{50{1'b0}}, {a_addr5_fu_519_p2}};
assign tmp_21_fu_530_p2 = (ap_reg_ppstg_j_mid2_reg_854_pp0_it1 | ap_const_lv7_2);
assign tmp_22_fu_548_p1 = {{50{1'b0}}, {a_addr6_fu_543_p2}};
assign tmp_22_trn_cast_fu_482_p1 = {{7{1'b0}}, {ap_reg_ppstg_j_mid2_reg_854_pp0_it1}};
assign tmp_23_fu_553_p2 = (ap_reg_ppstg_j_mid2_reg_854_pp0_it1 | ap_const_lv7_3);
assign tmp_24_fu_571_p1 = {{50{1'b0}}, {a_addr8_fu_566_p2}};
assign tmp_24_trn_cast_fu_515_p1 = {{7{1'b0}}, {tmp_19_fu_506_p2}};
assign tmp_25_fu_470_p2 = (j_mid2_reg_854 + ap_const_lv7_4);
assign tmp_26_trn_cast_fu_539_p1 = {{7{1'b0}}, {tmp_21_fu_530_p2}};
assign tmp_28_trn_cast_fu_562_p1 = {{7{1'b0}}, {tmp_23_fu_553_p2}};
assign tmp_2_fu_287_p2 = (tag == ap_const_lv2_0? 1'b1: 1'b0);
assign tmp_3_fu_754_p1 = {{50{1'b0}}, {a_addr_fu_748_p2}};
assign tmp_3_trn8_cast_fu_732_p1 = {{6{1'b0}}, {ap_reg_ppstg_i_1_mid2_reg_933_pp1_it1}};
assign tmp_4_fu_778_p1 = {{50{1'b0}}, {a_addr7_fu_772_p2}};
assign tmp_4_trn_cast_fu_479_p1 = {{6{1'b0}}, {ap_reg_ppstg_i_mid2_reg_863_pp0_it1}};
assign tmp_5_dup_fu_610_p2 = (i_1_phi_fu_239_p4 + ap_const_lv7_1);
assign tmp_5_fu_783_p2 = (ap_reg_ppstg_j_1_mid2_reg_924_pp1_it1 | ap_const_lv7_2);
assign tmp_7_fu_679_p1 = {{46{tmp_26_reg_939[17]}}, {tmp_26_reg_939}};
assign tmp_8_fu_277_p1 = {{1{1'b0}}, {tmp_1_fu_269_p3}};
assign tmp_cast_fu_644_p1 = {{6{1'b0}}, {tmp_fu_638_p2}};
assign tmp_fu_638_p2 = indvar_cast_fu_634_p1 << ap_const_lv7_2;
assign tmp_s_fu_759_p2 = (ap_reg_ppstg_j_1_mid2_reg_924_pp1_it1 | ap_const_lv7_1);
assign tmp_trn_cast_fu_735_p1 = {{7{1'b0}}, {ap_reg_ppstg_j_1_mid2_reg_924_pp1_it1}};
always @ (ap_clk)
begin
tmp3_cast_reg_835[0] <= 1'b0;
tmp3_cast_reg_835[1] <= 1'b0;
tmp3_cast_reg_835[2] <= 1'b0;
tmp3_cast_reg_835[3] <= 1'b0;
tmp3_cast_reg_835[4] <= 1'b0;
tmp3_cast_reg_835[5] <= 1'b0;
tmp3_cast_reg_835[6] <= 1'b0;
tmp3_cast_reg_835[7] <= 1'b0;
tmp3_cast_reg_835[8] <= 1'b0;
tmp3_cast_reg_835[9] <= 1'b0;
tmp3_cast_reg_835[10] <= 1'b0;
tmp3_cast_reg_835[11] <= 1'b0;
tmp3_cast_reg_835[19] <= 1'b0;
end
always @ (ap_clk)
begin
tmp2_reg_840[0] <= 1'b0;
tmp2_reg_840[1] <= 1'b0;
tmp2_reg_840[2] <= 1'b0;
tmp2_reg_840[3] <= 1'b0;
tmp2_reg_840[4] <= 1'b0;
tmp2_reg_840[5] <= 1'b0;
tmp2_reg_840[6] <= 1'b0;
tmp2_reg_840[7] <= 1'b0;
tmp2_reg_840[8] <= 1'b0;
tmp2_reg_840[9] <= 1'b0;
tmp2_reg_840[10] <= 1'b0;
tmp2_reg_840[11] <= 1'b0;
end
always @ (ap_clk)
begin
tmp13_reg_869[0] <= 1'b0;
tmp13_reg_869[1] <= 1'b0;
end
always @ (ap_clk)
begin
a_addr2_cast_reg_909[0] <= 1'b0;
a_addr2_cast_reg_909[1] <= 1'b0;
a_addr2_cast_reg_909[2] <= 1'b0;
a_addr2_cast_reg_909[3] <= 1'b0;
a_addr2_cast_reg_909[4] <= 1'b0;
a_addr2_cast_reg_909[5] <= 1'b0;
a_addr2_cast_reg_909[13] <= 1'b0;
end
always @ (ap_clk)
begin
a_addr9_cast_reg_979[0] <= 1'b0;
a_addr9_cast_reg_979[1] <= 1'b0;
a_addr9_cast_reg_979[2] <= 1'b0;
a_addr9_cast_reg_979[3] <= 1'b0;
a_addr9_cast_reg_979[4] <= 1'b0;
a_addr9_cast_reg_979[5] <= 1'b0;
a_addr9_cast_reg_979[13] <= 1'b0;
end
endmodule //fetch
|
// ==============================================================
// RTL generated by AutoESL - High-Level Synthesis System (C, C++, SystemC)
// Version: 2011.1
// Copyright (C) 2011 Xilinx Inc. All rights reserved.
//
// ===========================================================
`timescale 1 ns / 1 ps
module Gaussianblur (
ap_clk,
ap_rst,
ap_start,
ap_done,
ap_idle,
V1_bus_req_din,
V1_bus_req_full_n,
V1_bus_req_write,
V1_bus_rsp_dout,
V1_bus_rsp_empty_n,
V1_bus_rsp_read,
V1_bus_address,
V1_bus_datain,
V1_bus_dataout,
V1_bus_size,
V2_bus_req_din,
V2_bus_req_full_n,
V2_bus_req_write,
V2_bus_rsp_dout,
V2_bus_rsp_empty_n,
V2_bus_rsp_read,
V2_bus_address,
V2_bus_datain,
V2_bus_dataout,
V2_bus_size,
std
);
input ap_clk;
input ap_rst;
input ap_start;
output ap_done;
output ap_idle;
output V1_bus_req_din;
input V1_bus_req_full_n;
output V1_bus_req_write;
input V1_bus_rsp_dout;
input V1_bus_rsp_empty_n;
output V1_bus_rsp_read;
output [31:0] V1_bus_address;
input [127:0] V1_bus_datain;
output [127:0] V1_bus_dataout;
output [31:0] V1_bus_size;
output V2_bus_req_din;
input V2_bus_req_full_n;
output V2_bus_req_write;
input V2_bus_rsp_dout;
input V2_bus_rsp_empty_n;
output V2_bus_rsp_read;
output [31:0] V2_bus_address;
input [127:0] V2_bus_datain;
output [127:0] V2_bus_dataout;
output [31:0] V2_bus_size;
input [31:0] std;
reg ap_done;
reg ap_idle;
reg [6:0] ap_CS_fsm;
wire [31:0] grp_fu_226_p2;
reg [31:0] reg_250;
wire [31:0] grp_fu_235_p2;
reg [31:0] reg_258;
wire [31:0] grp_fu_220_p2;
reg [31:0] reg_266;
wire [31:0] grp_fu_245_p2;
reg [31:0] tmp_5_reg_320;
reg [31:0] nu_reg_325;
wire [31:0] grp_fu_241_p2;
reg [31:0] tmp_8_reg_333;
reg [1:0] tmp_s_reg_341;
reg [1:0] tmp_10_reg_349;
reg [6:0] tmp_11_reg_357;
reg [11:0] a0_address0;
reg a0_ce0;
reg a0_we0;
reg [31:0] a0_d0;
wire [31:0] a0_q0;
reg [11:0] a0_address1;
reg a0_ce1;
reg a0_we1;
reg [31:0] a0_d1;
wire [31:0] a0_q1;
reg [11:0] a1_address0;
reg a1_ce0;
reg a1_we0;
reg [31:0] a1_d0;
wire [31:0] a1_q0;
reg [11:0] a1_address1;
reg a1_ce1;
reg a1_we1;
reg [31:0] a1_d1;
wire [31:0] a1_q1;
reg [11:0] b0_address0;
reg b0_ce0;
reg b0_we0;
wire [31:0] b0_d0;
wire [31:0] b0_q0;
reg [11:0] b0_address1;
reg b0_ce1;
reg b0_we1;
wire [31:0] b0_d1;
wire [31:0] b0_q1;
reg [11:0] b1_address0;
reg b1_ce0;
reg b1_we0;
wire [31:0] b1_d0;
wire [31:0] b1_q0;
reg [11:0] b1_address1;
reg b1_ce1;
reg b1_we1;
wire [31:0] b1_d1;
wire [31:0] b1_q1;
reg [11:0] c0_address0;
reg c0_ce0;
reg c0_we0;
wire [31:0] c0_d0;
wire [31:0] c0_q0;
reg [11:0] c0_address1;
reg c0_ce1;
reg c0_we1;
wire [31:0] c0_d1;
wire [31:0] c0_q1;
reg [11:0] c1_address0;
reg c1_ce0;
reg c1_we0;
wire [31:0] c1_d0;
wire [31:0] c1_q0;
reg [11:0] c1_address1;
reg c1_ce1;
reg c1_we1;
wire [31:0] c1_d1;
wire [31:0] c1_q1;
reg [11:0] d0_address0;
reg d0_ce0;
reg d0_we0;
wire [31:0] d0_d0;
wire [31:0] d0_q0;
reg [11:0] d0_address1;
reg d0_ce1;
reg d0_we1;
wire [31:0] d0_d1;
wire [31:0] d0_q1;
reg [11:0] d1_address0;
reg d1_ce0;
reg d1_we0;
wire [31:0] d1_d0;
wire [31:0] d1_q0;
reg [11:0] d1_address1;
reg d1_ce1;
reg d1_we1;
wire [31:0] d1_d1;
wire [31:0] d1_q1;
reg grp_step0_fu_168_ap_start;
wire grp_step0_fu_168_ap_done;
wire grp_step0_fu_168_ap_idle;
wire [1:0] grp_step0_fu_168_tag;
wire [6:0] grp_step0_fu_168_counter;
wire [11:0] grp_step0_fu_168_a_address0;
wire grp_step0_fu_168_a_ce0;
wire grp_step0_fu_168_a_we0;
wire [31:0] grp_step0_fu_168_a_d0;
reg [31:0] grp_step0_fu_168_a_q0;
wire [11:0] grp_step0_fu_168_a_address1;
wire grp_step0_fu_168_a_ce1;
wire grp_step0_fu_168_a_we1;
wire [31:0] grp_step0_fu_168_a_d1;
reg [31:0] grp_step0_fu_168_a_q1;
wire [11:0] grp_step0_fu_168_b_address0;
wire grp_step0_fu_168_b_ce0;
wire grp_step0_fu_168_b_we0;
wire [31:0] grp_step0_fu_168_b_d0;
reg [31:0] grp_step0_fu_168_b_q0;
wire [11:0] grp_step0_fu_168_b_address1;
wire grp_step0_fu_168_b_ce1;
wire grp_step0_fu_168_b_we1;
wire [31:0] grp_step0_fu_168_b_d1;
reg [31:0] grp_step0_fu_168_b_q1;
wire [31:0] grp_step0_fu_168_BoundryScale;
wire [31:0] grp_step0_fu_168_nu;
reg grp_step1_fu_180_ap_start;
wire grp_step1_fu_180_ap_done;
wire grp_step1_fu_180_ap_idle;
wire [0:0] grp_step1_fu_180_step;
wire [1:0] grp_step1_fu_180_tag;
wire [6:0] grp_step1_fu_180_counter;
wire [11:0] grp_step1_fu_180_c_address0;
wire grp_step1_fu_180_c_ce0;
reg [31:0] grp_step1_fu_180_c_q0;
wire [11:0] grp_step1_fu_180_c_address1;
wire grp_step1_fu_180_c_ce1;
reg [31:0] grp_step1_fu_180_c_q1;
wire [11:0] grp_step1_fu_180_b_address0;
wire grp_step1_fu_180_b_ce0;
reg [31:0] grp_step1_fu_180_b_q0;
wire [11:0] grp_step1_fu_180_b_address1;
wire grp_step1_fu_180_b_ce1;
reg [31:0] grp_step1_fu_180_b_q1;
wire [11:0] grp_step1_fu_180_d_address0;
wire grp_step1_fu_180_d_ce0;
wire grp_step1_fu_180_d_we0;
wire [31:0] grp_step1_fu_180_d_d0;
wire [11:0] grp_step1_fu_180_d_address1;
wire grp_step1_fu_180_d_ce1;
wire grp_step1_fu_180_d_we1;
wire [31:0] grp_step1_fu_180_d_d1;
wire [11:0] grp_step1_fu_180_c1_address0;
wire grp_step1_fu_180_c1_ce0;
wire grp_step1_fu_180_c1_we0;
wire [31:0] grp_step1_fu_180_c1_d0;
wire [11:0] grp_step1_fu_180_c1_address1;
wire grp_step1_fu_180_c1_ce1;
wire grp_step1_fu_180_c1_we1;
wire [31:0] grp_step1_fu_180_c1_d1;
wire [31:0] grp_step1_fu_180_BoundryScale;
wire [31:0] grp_step1_fu_180_nu;
wire [31:0] grp_step1_fu_180_PostScale;
reg grp_write_r_fu_198_ap_start;
wire grp_write_r_fu_198_ap_done;
wire grp_write_r_fu_198_ap_idle;
wire [1:0] grp_write_r_fu_198_tag;
wire [6:0] grp_write_r_fu_198_counter;
wire [11:0] grp_write_r_fu_198_d_address0;
wire grp_write_r_fu_198_d_ce0;
reg [31:0] grp_write_r_fu_198_d_q0;
wire [11:0] grp_write_r_fu_198_d_address1;
wire grp_write_r_fu_198_d_ce1;
reg [31:0] grp_write_r_fu_198_d_q1;
wire grp_write_r_fu_198_V_bus_req_din;
wire grp_write_r_fu_198_V_bus_req_full_n;
wire grp_write_r_fu_198_V_bus_req_write;
wire grp_write_r_fu_198_V_bus_rsp_dout;
wire grp_write_r_fu_198_V_bus_rsp_empty_n;
wire grp_write_r_fu_198_V_bus_rsp_read;
wire [31:0] grp_write_r_fu_198_V_bus_address;
wire [127:0] grp_write_r_fu_198_V_bus_datain;
wire [127:0] grp_write_r_fu_198_V_bus_dataout;
wire [31:0] grp_write_r_fu_198_V_bus_size;
reg grp_fetch_fu_209_ap_start;
wire grp_fetch_fu_209_ap_done;
wire grp_fetch_fu_209_ap_idle;
wire [1:0] grp_fetch_fu_209_tag;
wire [6:0] grp_fetch_fu_209_counter;
wire [11:0] grp_fetch_fu_209_a_address0;
wire grp_fetch_fu_209_a_ce0;
wire grp_fetch_fu_209_a_we0;
wire [31:0] grp_fetch_fu_209_a_d0;
wire [11:0] grp_fetch_fu_209_a_address1;
wire grp_fetch_fu_209_a_ce1;
wire grp_fetch_fu_209_a_we1;
wire [31:0] grp_fetch_fu_209_a_d1;
wire grp_fetch_fu_209_V_bus_req_din;
wire grp_fetch_fu_209_V_bus_req_full_n;
wire grp_fetch_fu_209_V_bus_req_write;
wire grp_fetch_fu_209_V_bus_rsp_dout;
wire grp_fetch_fu_209_V_bus_rsp_empty_n;
wire grp_fetch_fu_209_V_bus_rsp_read;
wire [31:0] grp_fetch_fu_209_V_bus_address;
wire [127:0] grp_fetch_fu_209_V_bus_datain;
wire [127:0] grp_fetch_fu_209_V_bus_dataout;
wire [31:0] grp_fetch_fu_209_V_bus_size;
reg [1:0] i_reg_104;
reg [31:0] PostScale_reg_115;
wire [0:0] indvar_phi_fu_132_p4;
reg [0:0] indvar_reg_127;
wire [0:0] exitcond1_fu_274_p2;
wire [0:0] exitcond_fu_286_p2;
reg [1:0] tag_reg_141;
wire [0:0] exitcond2_fu_298_p2;
reg [6:0] counter_reg_153;
wire [0:0] tmp_12_fu_310_p1;
reg [31:0] grp_fu_220_p0;
reg [31:0] grp_fu_220_p1;
reg [31:0] grp_fu_226_p0;
reg [31:0] grp_fu_226_p1;
reg [31:0] grp_fu_235_p0;
reg [31:0] grp_fu_235_p1;
wire [31:0] grp_fu_241_p0;
wire [31:0] grp_fu_241_p1;
wire [31:0] grp_fu_245_p1;
reg [1:0] grp_fu_220_opcode;
wire grp_fu_220_ce;
reg grp_fu_226_ce;
wire grp_fu_235_ce;
wire grp_fu_241_ce;
wire [31:0] grp_fu_245_p0;
wire grp_fu_245_ce;
reg [6:0] ap_NS_fsm;
parameter ap_const_logic_1 = 1'b1;
parameter ap_const_logic_0 = 1'b0;
parameter ap_ST_st0_fsm_0 = 7'b0000000;
parameter ap_ST_st1_fsm_1 = 7'b0000001;
parameter ap_ST_st2_fsm_2 = 7'b0000010;
parameter ap_ST_st3_fsm_3 = 7'b0000011;
parameter ap_ST_st4_fsm_4 = 7'b0000100;
parameter ap_ST_st5_fsm_5 = 7'b0000101;
parameter ap_ST_st6_fsm_6 = 7'b0000110;
parameter ap_ST_st7_fsm_7 = 7'b0000111;
parameter ap_ST_st8_fsm_8 = 7'b0001000;
parameter ap_ST_st9_fsm_9 = 7'b0001001;
parameter ap_ST_st10_fsm_10 = 7'b0001010;
parameter ap_ST_st11_fsm_11 = 7'b0001011;
parameter ap_ST_st12_fsm_12 = 7'b0001100;
parameter ap_ST_st13_fsm_13 = 7'b0001101;
parameter ap_ST_st14_fsm_14 = 7'b0001110;
parameter ap_ST_st15_fsm_15 = 7'b0001111;
parameter ap_ST_st16_fsm_16 = 7'b0010000;
parameter ap_ST_st17_fsm_17 = 7'b0010001;
parameter ap_ST_st18_fsm_18 = 7'b0010010;
parameter ap_ST_st19_fsm_19 = 7'b0010011;
parameter ap_ST_st20_fsm_20 = 7'b0010100;
parameter ap_ST_st21_fsm_21 = 7'b0010101;
parameter ap_ST_st22_fsm_22 = 7'b0010110;
parameter ap_ST_st23_fsm_23 = 7'b0010111;
parameter ap_ST_st24_fsm_24 = 7'b0011000;
parameter ap_ST_st25_fsm_25 = 7'b0011001;
parameter ap_ST_st26_fsm_26 = 7'b0011010;
parameter ap_ST_st27_fsm_27 = 7'b0011011;
parameter ap_ST_st28_fsm_28 = 7'b0011100;
parameter ap_ST_st29_fsm_29 = 7'b0011101;
parameter ap_ST_st30_fsm_30 = 7'b0011110;
parameter ap_ST_st31_fsm_31 = 7'b0011111;
parameter ap_ST_st32_fsm_32 = 7'b0100000;
parameter ap_ST_st33_fsm_33 = 7'b0100001;
parameter ap_ST_st34_fsm_34 = 7'b0100010;
parameter ap_ST_st35_fsm_35 = 7'b0100011;
parameter ap_ST_st36_fsm_36 = 7'b0100100;
parameter ap_ST_st37_fsm_37 = 7'b0100101;
parameter ap_ST_st38_fsm_38 = 7'b0100110;
parameter ap_ST_st39_fsm_39 = 7'b0100111;
parameter ap_ST_st40_fsm_40 = 7'b0101000;
parameter ap_ST_st41_fsm_41 = 7'b0101001;
parameter ap_ST_st42_fsm_42 = 7'b0101010;
parameter ap_ST_st43_fsm_43 = 7'b0101011;
parameter ap_ST_st44_fsm_44 = 7'b0101100;
parameter ap_ST_st45_fsm_45 = 7'b0101101;
parameter ap_ST_st46_fsm_46 = 7'b0101110;
parameter ap_ST_st47_fsm_47 = 7'b0101111;
parameter ap_ST_st48_fsm_48 = 7'b0110000;
parameter ap_ST_st49_fsm_49 = 7'b0110001;
parameter ap_ST_st50_fsm_50 = 7'b0110010;
parameter ap_ST_st51_fsm_51 = 7'b0110011;
parameter ap_ST_st52_fsm_52 = 7'b0110100;
parameter ap_ST_st53_fsm_53 = 7'b0110101;
parameter ap_ST_st54_fsm_54 = 7'b0110110;
parameter ap_ST_st55_fsm_55 = 7'b0110111;
parameter ap_ST_st56_fsm_56 = 7'b0111000;
parameter ap_ST_st57_fsm_57 = 7'b0111001;
parameter ap_ST_st58_fsm_58 = 7'b0111010;
parameter ap_ST_st59_fsm_59 = 7'b0111011;
parameter ap_ST_st60_fsm_60 = 7'b0111100;
parameter ap_ST_st61_fsm_61 = 7'b0111101;
parameter ap_ST_st62_fsm_62 = 7'b0111110;
parameter ap_ST_st63_fsm_63 = 7'b0111111;
parameter ap_ST_st64_fsm_64 = 7'b1000000;
parameter ap_ST_st65_fsm_65 = 7'b1000001;
parameter ap_ST_st66_fsm_66 = 7'b1000010;
parameter ap_ST_st67_fsm_67 = 7'b1000011;
parameter ap_ST_st68_fsm_68 = 7'b1000100;
parameter ap_ST_st69_fsm_69 = 7'b1000101;
parameter ap_ST_st70_fsm_70 = 7'b1000110;
parameter ap_ST_st71_fsm_71 = 7'b1000111;
parameter ap_ST_st72_fsm_72 = 7'b1001000;
parameter ap_const_lv2_0 = 2'b00;
parameter ap_const_lv32_3F800000 = 32'b00111111100000000000000000000000;
parameter ap_const_lv1_0 = 1'b0;
parameter ap_const_lv1_1 = 1'b1;
parameter ap_const_lv7_0 = 7'b0000000;
parameter ap_const_lv32_40800000 = 32'b01000000100000000000000000000000;
parameter ap_const_lv32_40000000 = 32'b01000000000000000000000000000000;
parameter ap_const_lv2_3 = 2'b11;
parameter ap_const_lv2_1 = 2'b01;
parameter ap_const_lv2_2 = 2'b10;
parameter ap_const_lv7_43 = 7'b1000011;
parameter ap_const_lv7_1 = 7'b0000001;
parameter ap_const_lv32_1 = 32'b00000000000000000000000000000001;
parameter ap_true = 1'b1;
Gaussianblur_a0 #(
.DataWidth( 32 ),
.AddressRange( 4096 ),
.AddressWidth( 12 ))
a0_U(
.clk( ap_clk ),
.address0( a0_address0 ),
.ce0( a0_ce0 ),
.we0( a0_we0 ),
.d0( a0_d0 ),
.q0( a0_q0 ),
.address1( a0_address1 ),
.ce1( a0_ce1 ),
.we1( a0_we1 ),
.d1( a0_d1 ),
.q1( a0_q1 )
);
Gaussianblur_a1 #(
.DataWidth( 32 ),
.AddressRange( 4096 ),
.AddressWidth( 12 ))
a1_U(
.clk( ap_clk ),
.address0( a1_address0 ),
.ce0( a1_ce0 ),
.we0( a1_we0 ),
.d0( a1_d0 ),
.q0( a1_q0 ),
.address1( a1_address1 ),
.ce1( a1_ce1 ),
.we1( a1_we1 ),
.d1( a1_d1 ),
.q1( a1_q1 )
);
Gaussianblur_b0 #(
.DataWidth( 32 ),
.AddressRange( 4096 ),
.AddressWidth( 12 ))
b0_U(
.clk( ap_clk ),
.address0( b0_address0 ),
.ce0( b0_ce0 ),
.we0( b0_we0 ),
.d0( b0_d0 ),
.q0( b0_q0 ),
.address1( b0_address1 ),
.ce1( b0_ce1 ),
.we1( b0_we1 ),
.d1( b0_d1 ),
.q1( b0_q1 )
);
Gaussianblur_b1 #(
.DataWidth( 32 ),
.AddressRange( 4096 ),
.AddressWidth( 12 ))
b1_U(
.clk( ap_clk ),
.address0( b1_address0 ),
.ce0( b1_ce0 ),
.we0( b1_we0 ),
.d0( b1_d0 ),
.q0( b1_q0 ),
.address1( b1_address1 ),
.ce1( b1_ce1 ),
.we1( b1_we1 ),
.d1( b1_d1 ),
.q1( b1_q1 )
);
Gaussianblur_c0 #(
.DataWidth( 32 ),
.AddressRange( 4096 ),
.AddressWidth( 12 ))
c0_U(
.clk( ap_clk ),
.address0( c0_address0 ),
.ce0( c0_ce0 ),
.we0( c0_we0 ),
.d0( c0_d0 ),
.q0( c0_q0 ),
.address1( c0_address1 ),
.ce1( c0_ce1 ),
.we1( c0_we1 ),
.d1( c0_d1 ),
.q1( c0_q1 )
);
Gaussianblur_c1 #(
.DataWidth( 32 ),
.AddressRange( 4096 ),
.AddressWidth( 12 ))
c1_U(
.clk( ap_clk ),
.address0( c1_address0 ),
.ce0( c1_ce0 ),
.we0( c1_we0 ),
.d0( c1_d0 ),
.q0( c1_q0 ),
.address1( c1_address1 ),
.ce1( c1_ce1 ),
.we1( c1_we1 ),
.d1( c1_d1 ),
.q1( c1_q1 )
);
Gaussianblur_d0 #(
.DataWidth( 32 ),
.AddressRange( 4096 ),
.AddressWidth( 12 ))
d0_U(
.clk( ap_clk ),
.address0( d0_address0 ),
.ce0( d0_ce0 ),
.we0( d0_we0 ),
.d0( d0_d0 ),
.q0( d0_q0 ),
.address1( d0_address1 ),
.ce1( d0_ce1 ),
.we1( d0_we1 ),
.d1( d0_d1 ),
.q1( d0_q1 )
);
Gaussianblur_d1 #(
.DataWidth( 32 ),
.AddressRange( 4096 ),
.AddressWidth( 12 ))
d1_U(
.clk( ap_clk ),
.address0( d1_address0 ),
.ce0( d1_ce0 ),
.we0( d1_we0 ),
.d0( d1_d0 ),
.q0( d1_q0 ),
.address1( d1_address1 ),
.ce1( d1_ce1 ),
.we1( d1_we1 ),
.d1( d1_d1 ),
.q1( d1_q1 )
);
step0 grp_step0_fu_168(
.ap_clk( ap_clk ),
.ap_rst( ap_rst ),
.ap_start( grp_step0_fu_168_ap_start ),
.ap_done( grp_step0_fu_168_ap_done ),
.ap_idle( grp_step0_fu_168_ap_idle ),
.tag( grp_step0_fu_168_tag ),
.counter( grp_step0_fu_168_counter ),
.a_address0( grp_step0_fu_168_a_address0 ),
.a_ce0( grp_step0_fu_168_a_ce0 ),
.a_we0( grp_step0_fu_168_a_we0 ),
.a_d0( grp_step0_fu_168_a_d0 ),
.a_q0( grp_step0_fu_168_a_q0 ),
.a_address1( grp_step0_fu_168_a_address1 ),
.a_ce1( grp_step0_fu_168_a_ce1 ),
.a_we1( grp_step0_fu_168_a_we1 ),
.a_d1( grp_step0_fu_168_a_d1 ),
.a_q1( grp_step0_fu_168_a_q1 ),
.b_address0( grp_step0_fu_168_b_address0 ),
.b_ce0( grp_step0_fu_168_b_ce0 ),
.b_we0( grp_step0_fu_168_b_we0 ),
.b_d0( grp_step0_fu_168_b_d0 ),
.b_q0( grp_step0_fu_168_b_q0 ),
.b_address1( grp_step0_fu_168_b_address1 ),
.b_ce1( grp_step0_fu_168_b_ce1 ),
.b_we1( grp_step0_fu_168_b_we1 ),
.b_d1( grp_step0_fu_168_b_d1 ),
.b_q1( grp_step0_fu_168_b_q1 ),
.BoundryScale( grp_step0_fu_168_BoundryScale ),
.nu( grp_step0_fu_168_nu )
);
step1 grp_step1_fu_180(
.ap_clk( ap_clk ),
.ap_rst( ap_rst ),
.ap_start( grp_step1_fu_180_ap_start ),
.ap_done( grp_step1_fu_180_ap_done ),
.ap_idle( grp_step1_fu_180_ap_idle ),
.step( grp_step1_fu_180_step ),
.tag( grp_step1_fu_180_tag ),
.counter( grp_step1_fu_180_counter ),
.c_address0( grp_step1_fu_180_c_address0 ),
.c_ce0( grp_step1_fu_180_c_ce0 ),
.c_q0( grp_step1_fu_180_c_q0 ),
.c_address1( grp_step1_fu_180_c_address1 ),
.c_ce1( grp_step1_fu_180_c_ce1 ),
.c_q1( grp_step1_fu_180_c_q1 ),
.b_address0( grp_step1_fu_180_b_address0 ),
.b_ce0( grp_step1_fu_180_b_ce0 ),
.b_q0( grp_step1_fu_180_b_q0 ),
.b_address1( grp_step1_fu_180_b_address1 ),
.b_ce1( grp_step1_fu_180_b_ce1 ),
.b_q1( grp_step1_fu_180_b_q1 ),
.d_address0( grp_step1_fu_180_d_address0 ),
.d_ce0( grp_step1_fu_180_d_ce0 ),
.d_we0( grp_step1_fu_180_d_we0 ),
.d_d0( grp_step1_fu_180_d_d0 ),
.d_address1( grp_step1_fu_180_d_address1 ),
.d_ce1( grp_step1_fu_180_d_ce1 ),
.d_we1( grp_step1_fu_180_d_we1 ),
.d_d1( grp_step1_fu_180_d_d1 ),
.c1_address0( grp_step1_fu_180_c1_address0 ),
.c1_ce0( grp_step1_fu_180_c1_ce0 ),
.c1_we0( grp_step1_fu_180_c1_we0 ),
.c1_d0( grp_step1_fu_180_c1_d0 ),
.c1_address1( grp_step1_fu_180_c1_address1 ),
.c1_ce1( grp_step1_fu_180_c1_ce1 ),
.c1_we1( grp_step1_fu_180_c1_we1 ),
.c1_d1( grp_step1_fu_180_c1_d1 ),
.BoundryScale( grp_step1_fu_180_BoundryScale ),
.nu( grp_step1_fu_180_nu ),
.PostScale( grp_step1_fu_180_PostScale )
);
write_r grp_write_r_fu_198(
.ap_clk( ap_clk ),
.ap_rst( ap_rst ),
.ap_start( grp_write_r_fu_198_ap_start ),
.ap_done( grp_write_r_fu_198_ap_done ),
.ap_idle( grp_write_r_fu_198_ap_idle ),
.tag( grp_write_r_fu_198_tag ),
.counter( grp_write_r_fu_198_counter ),
.d_address0( grp_write_r_fu_198_d_address0 ),
.d_ce0( grp_write_r_fu_198_d_ce0 ),
.d_q0( grp_write_r_fu_198_d_q0 ),
.d_address1( grp_write_r_fu_198_d_address1 ),
.d_ce1( grp_write_r_fu_198_d_ce1 ),
.d_q1( grp_write_r_fu_198_d_q1 ),
.V_bus_req_din( grp_write_r_fu_198_V_bus_req_din ),
.V_bus_req_full_n( grp_write_r_fu_198_V_bus_req_full_n ),
.V_bus_req_write( grp_write_r_fu_198_V_bus_req_write ),
.V_bus_rsp_dout( grp_write_r_fu_198_V_bus_rsp_dout ),
.V_bus_rsp_empty_n( grp_write_r_fu_198_V_bus_rsp_empty_n ),
.V_bus_rsp_read( grp_write_r_fu_198_V_bus_rsp_read ),
.V_bus_address( grp_write_r_fu_198_V_bus_address ),
.V_bus_datain( grp_write_r_fu_198_V_bus_datain ),
.V_bus_dataout( grp_write_r_fu_198_V_bus_dataout ),
.V_bus_size( grp_write_r_fu_198_V_bus_size )
);
fetch grp_fetch_fu_209(
.ap_clk( ap_clk ),
.ap_rst( ap_rst ),
.ap_start( grp_fetch_fu_209_ap_start ),
.ap_done( grp_fetch_fu_209_ap_done ),
.ap_idle( grp_fetch_fu_209_ap_idle ),
.tag( grp_fetch_fu_209_tag ),
.counter( grp_fetch_fu_209_counter ),
.a_address0( grp_fetch_fu_209_a_address0 ),
.a_ce0( grp_fetch_fu_209_a_ce0 ),
.a_we0( grp_fetch_fu_209_a_we0 ),
.a_d0( grp_fetch_fu_209_a_d0 ),
.a_address1( grp_fetch_fu_209_a_address1 ),
.a_ce1( grp_fetch_fu_209_a_ce1 ),
.a_we1( grp_fetch_fu_209_a_we1 ),
.a_d1( grp_fetch_fu_209_a_d1 ),
.V_bus_req_din( grp_fetch_fu_209_V_bus_req_din ),
.V_bus_req_full_n( grp_fetch_fu_209_V_bus_req_full_n ),
.V_bus_req_write( grp_fetch_fu_209_V_bus_req_write ),
.V_bus_rsp_dout( grp_fetch_fu_209_V_bus_rsp_dout ),
.V_bus_rsp_empty_n( grp_fetch_fu_209_V_bus_rsp_empty_n ),
.V_bus_rsp_read( grp_fetch_fu_209_V_bus_rsp_read ),
.V_bus_address( grp_fetch_fu_209_V_bus_address ),
.V_bus_datain( grp_fetch_fu_209_V_bus_datain ),
.V_bus_dataout( grp_fetch_fu_209_V_bus_dataout ),
.V_bus_size( grp_fetch_fu_209_V_bus_size )
);
Gaussianblur_grp_fu_220_ACMP_faddfsub_30 #(
.ID( 30 ),
.NUM_STAGE( 5 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
Gaussianblur_grp_fu_220_ACMP_faddfsub_30_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_220_p0 ),
.din1( grp_fu_220_p1 ),
.opcode( grp_fu_220_opcode ),
.ce( grp_fu_220_ce ),
.dout( grp_fu_220_p2 )
);
Gaussianblur_grp_fu_226_ACMP_fmul_31 #(
.ID( 31 ),
.NUM_STAGE( 4 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
Gaussianblur_grp_fu_226_ACMP_fmul_31_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_226_p0 ),
.din1( grp_fu_226_p1 ),
.ce( grp_fu_226_ce ),
.dout( grp_fu_226_p2 )
);
Gaussianblur_grp_fu_235_ACMP_fdiv_32 #(
.ID( 32 ),
.NUM_STAGE( 10 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
Gaussianblur_grp_fu_235_ACMP_fdiv_32_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_235_p0 ),
.din1( grp_fu_235_p1 ),
.ce( grp_fu_235_ce ),
.dout( grp_fu_235_p2 )
);
Gaussianblur_grp_fu_241_ACMP_fdiv_33 #(
.ID( 33 ),
.NUM_STAGE( 10 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
Gaussianblur_grp_fu_241_ACMP_fdiv_33_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_241_p0 ),
.din1( grp_fu_241_p1 ),
.ce( grp_fu_241_ce ),
.dout( grp_fu_241_p2 )
);
Gaussianblur_grp_fu_245_ACMP_fsqrt_34 #(
.ID( 34 ),
.NUM_STAGE( 10 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
Gaussianblur_grp_fu_245_ACMP_fsqrt_34_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_245_p0 ),
.din1( grp_fu_245_p1 ),
.ce( grp_fu_245_ce ),
.dout( grp_fu_245_p2 )
);
/// ap_CS_fsm assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_CS_fsm
if (ap_rst == 1'b1) begin
ap_CS_fsm <= ap_ST_st0_fsm_0;
end else begin
ap_CS_fsm <= ap_NS_fsm;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_ST_st67_fsm_67 == ap_CS_fsm)) begin
PostScale_reg_115 <= grp_fu_226_p2;
end else if ((ap_ST_st63_fsm_63 == ap_CS_fsm)) begin
PostScale_reg_115 <= ap_const_lv32_3F800000;
end
if (((ap_ST_st69_fsm_69 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond_fu_286_p2))) begin
counter_reg_153 <= ap_const_lv7_0;
end else if ((((ap_ST_st72_fsm_72 == ap_CS_fsm) & ~((ap_const_logic_0 == grp_fetch_fu_209_ap_done) | (ap_const_logic_0 == grp_step0_fu_168_ap_done) | (ap_const_logic_0 == grp_step1_fu_180_ap_done) | (ap_const_logic_0 == grp_write_r_fu_198_ap_done))) | (~((ap_const_logic_0 == grp_fetch_fu_209_ap_done) | (ap_const_logic_0 == grp_step0_fu_168_ap_done) | (ap_const_logic_0 == grp_step1_fu_180_ap_done) | (ap_const_logic_0 == grp_write_r_fu_198_ap_done)) & (ap_ST_st71_fsm_71 == ap_CS_fsm)))) begin
counter_reg_153 <= tmp_11_reg_357;
end
if ((ap_ST_st67_fsm_67 == ap_CS_fsm)) begin
i_reg_104 <= tmp_s_reg_341;
end else if ((ap_ST_st63_fsm_63 == ap_CS_fsm)) begin
i_reg_104 <= ap_const_lv2_0;
end
if (((ap_ST_st69_fsm_69 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond_fu_286_p2))) begin
indvar_reg_127 <= ap_const_lv1_1;
end else if (((ap_ST_st64_fsm_64 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond1_fu_274_p2))) begin
indvar_reg_127 <= ap_const_lv1_0;
end
if ((ap_ST_st48_fsm_48 == ap_CS_fsm)) begin
nu_reg_325 <= grp_fu_235_p2;
end
if (((ap_ST_st4_fsm_4 == ap_CS_fsm) | (ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st67_fsm_67 == ap_CS_fsm))) begin
reg_250 <= grp_fu_226_p2;
end
if (((ap_ST_st14_fsm_14 == ap_CS_fsm) | (ap_ST_st63_fsm_63 == ap_CS_fsm))) begin
reg_258 <= grp_fu_235_p2;
end
if (((ap_ST_st23_fsm_23 == ap_CS_fsm) | (ap_ST_st33_fsm_33 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st53_fsm_53 == ap_CS_fsm))) begin
reg_266 <= grp_fu_220_p2;
end
if (((ap_ST_st68_fsm_68 == ap_CS_fsm) & (ap_const_lv1_0 == indvar_phi_fu_132_p4))) begin
tag_reg_141 <= ap_const_lv2_0;
end else if (((ap_ST_st70_fsm_70 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond2_fu_298_p2))) begin
tag_reg_141 <= tmp_10_reg_349;
end
if ((ap_ST_st69_fsm_69 == ap_CS_fsm)) begin
tmp_10_reg_349 <= (tag_reg_141 + ap_const_lv2_1);
end
if ((ap_ST_st70_fsm_70 == ap_CS_fsm)) begin
tmp_11_reg_357 <= (counter_reg_153 + ap_const_lv7_1);
end
if ((ap_ST_st33_fsm_33 == ap_CS_fsm)) begin
tmp_5_reg_320 <= grp_fu_245_p2;
end
if ((ap_ST_st63_fsm_63 == ap_CS_fsm)) begin
tmp_8_reg_333 <= grp_fu_241_p2;
end
if ((ap_ST_st64_fsm_64 == ap_CS_fsm)) begin
tmp_s_reg_341 <= (i_reg_104 + ap_const_lv2_1);
end
end
/// a0_address0 assign process. ///
always @ (ap_CS_fsm or grp_step0_fu_168_a_address0 or grp_fetch_fu_209_a_address0)
begin
if ((ap_ST_st71_fsm_71 == ap_CS_fsm)) begin
a0_address0 = grp_fetch_fu_209_a_address0;
end else if ((ap_ST_st72_fsm_72 == ap_CS_fsm)) begin
a0_address0 = grp_step0_fu_168_a_address0;
end else begin
a0_address0 = grp_fetch_fu_209_a_address0;
end
end
/// a0_address1 assign process. ///
always @ (ap_CS_fsm or grp_step0_fu_168_a_address1 or grp_fetch_fu_209_a_address1)
begin
if ((ap_ST_st71_fsm_71 == ap_CS_fsm)) begin
a0_address1 = grp_fetch_fu_209_a_address1;
end else if ((ap_ST_st72_fsm_72 == ap_CS_fsm)) begin
a0_address1 = grp_step0_fu_168_a_address1;
end else begin
a0_address1 = grp_fetch_fu_209_a_address1;
end
end
/// a0_ce0 assign process. ///
always @ (ap_CS_fsm or grp_step0_fu_168_a_ce0 or grp_fetch_fu_209_a_ce0)
begin
if ((ap_ST_st71_fsm_71 == ap_CS_fsm)) begin
a0_ce0 = grp_fetch_fu_209_a_ce0;
end else if ((ap_ST_st72_fsm_72 == ap_CS_fsm)) begin
a0_ce0 = grp_step0_fu_168_a_ce0;
end else begin
a0_ce0 = ap_const_logic_0;
end
end
/// a0_ce1 assign process. ///
always @ (ap_CS_fsm or grp_step0_fu_168_a_ce1 or grp_fetch_fu_209_a_ce1)
begin
if ((ap_ST_st71_fsm_71 == ap_CS_fsm)) begin
a0_ce1 = grp_fetch_fu_209_a_ce1;
end else if ((ap_ST_st72_fsm_72 == ap_CS_fsm)) begin
a0_ce1 = grp_step0_fu_168_a_ce1;
end else begin
a0_ce1 = ap_const_logic_0;
end
end
/// a0_d0 assign process. ///
always @ (ap_CS_fsm or grp_step0_fu_168_a_d0 or grp_fetch_fu_209_a_d0)
begin
if ((ap_ST_st71_fsm_71 == ap_CS_fsm)) begin
a0_d0 = grp_fetch_fu_209_a_d0;
end else if ((ap_ST_st72_fsm_72 == ap_CS_fsm)) begin
a0_d0 = grp_step0_fu_168_a_d0;
end else begin
a0_d0 = grp_fetch_fu_209_a_d0;
end
end
/// a0_d1 assign process. ///
always @ (ap_CS_fsm or grp_step0_fu_168_a_d1 or grp_fetch_fu_209_a_d1)
begin
if ((ap_ST_st71_fsm_71 == ap_CS_fsm)) begin
a0_d1 = grp_fetch_fu_209_a_d1;
end else if ((ap_ST_st72_fsm_72 == ap_CS_fsm)) begin
a0_d1 = grp_step0_fu_168_a_d1;
end else begin
a0_d1 = grp_fetch_fu_209_a_d1;
end
end
/// a0_we0 assign process. ///
always @ (ap_CS_fsm or grp_step0_fu_168_a_we0 or grp_fetch_fu_209_a_we0)
begin
if ((ap_ST_st71_fsm_71 == ap_CS_fsm)) begin
a0_we0 = grp_fetch_fu_209_a_we0;
end else if ((ap_ST_st72_fsm_72 == ap_CS_fsm)) begin
a0_we0 = grp_step0_fu_168_a_we0;
end else begin
a0_we0 = ap_const_logic_0;
end
end
/// a0_we1 assign process. ///
always @ (ap_CS_fsm or grp_step0_fu_168_a_we1 or grp_fetch_fu_209_a_we1)
begin
if ((ap_ST_st71_fsm_71 == ap_CS_fsm)) begin
a0_we1 = grp_fetch_fu_209_a_we1;
end else if ((ap_ST_st72_fsm_72 == ap_CS_fsm)) begin
a0_we1 = grp_step0_fu_168_a_we1;
end else begin
a0_we1 = ap_const_logic_0;
end
end
/// a1_address0 assign process. ///
always @ (ap_CS_fsm or grp_step0_fu_168_a_address0 or grp_fetch_fu_209_a_address0)
begin
if ((ap_ST_st72_fsm_72 == ap_CS_fsm)) begin
a1_address0 = grp_fetch_fu_209_a_address0;
end else if ((ap_ST_st71_fsm_71 == ap_CS_fsm)) begin
a1_address0 = grp_step0_fu_168_a_address0;
end else begin
a1_address0 = grp_fetch_fu_209_a_address0;
end
end
/// a1_address1 assign process. ///
always @ (ap_CS_fsm or grp_step0_fu_168_a_address1 or grp_fetch_fu_209_a_address1)
begin
if ((ap_ST_st72_fsm_72 == ap_CS_fsm)) begin
a1_address1 = grp_fetch_fu_209_a_address1;
end else if ((ap_ST_st71_fsm_71 == ap_CS_fsm)) begin
a1_address1 = grp_step0_fu_168_a_address1;
end else begin
a1_address1 = grp_fetch_fu_209_a_address1;
end
end
/// a1_ce0 assign process. ///
always @ (ap_CS_fsm or grp_step0_fu_168_a_ce0 or grp_fetch_fu_209_a_ce0)
begin
if ((ap_ST_st72_fsm_72 == ap_CS_fsm)) begin
a1_ce0 = grp_fetch_fu_209_a_ce0;
end else if ((ap_ST_st71_fsm_71 == ap_CS_fsm)) begin
a1_ce0 = grp_step0_fu_168_a_ce0;
end else begin
a1_ce0 = ap_const_logic_0;
end
end
/// a1_ce1 assign process. ///
always @ (ap_CS_fsm or grp_step0_fu_168_a_ce1 or grp_fetch_fu_209_a_ce1)
begin
if ((ap_ST_st72_fsm_72 == ap_CS_fsm)) begin
a1_ce1 = grp_fetch_fu_209_a_ce1;
end else if ((ap_ST_st71_fsm_71 == ap_CS_fsm)) begin
a1_ce1 = grp_step0_fu_168_a_ce1;
end else begin
a1_ce1 = ap_const_logic_0;
end
end
/// a1_d0 assign process. ///
always @ (ap_CS_fsm or grp_step0_fu_168_a_d0 or grp_fetch_fu_209_a_d0)
begin
if ((ap_ST_st72_fsm_72 == ap_CS_fsm)) begin
a1_d0 = grp_fetch_fu_209_a_d0;
end else if ((ap_ST_st71_fsm_71 == ap_CS_fsm)) begin
a1_d0 = grp_step0_fu_168_a_d0;
end else begin
a1_d0 = grp_fetch_fu_209_a_d0;
end
end
/// a1_d1 assign process. ///
always @ (ap_CS_fsm or grp_step0_fu_168_a_d1 or grp_fetch_fu_209_a_d1)
begin
if ((ap_ST_st72_fsm_72 == ap_CS_fsm)) begin
a1_d1 = grp_fetch_fu_209_a_d1;
end else if ((ap_ST_st71_fsm_71 == ap_CS_fsm)) begin
a1_d1 = grp_step0_fu_168_a_d1;
end else begin
a1_d1 = grp_fetch_fu_209_a_d1;
end
end
/// a1_we0 assign process. ///
always @ (ap_CS_fsm or grp_step0_fu_168_a_we0 or grp_fetch_fu_209_a_we0)
begin
if ((ap_ST_st72_fsm_72 == ap_CS_fsm)) begin
a1_we0 = grp_fetch_fu_209_a_we0;
end else if ((ap_ST_st71_fsm_71 == ap_CS_fsm)) begin
a1_we0 = grp_step0_fu_168_a_we0;
end else begin
a1_we0 = ap_const_logic_0;
end
end
/// a1_we1 assign process. ///
always @ (ap_CS_fsm or grp_step0_fu_168_a_we1 or grp_fetch_fu_209_a_we1)
begin
if ((ap_ST_st72_fsm_72 == ap_CS_fsm)) begin
a1_we1 = grp_fetch_fu_209_a_we1;
end else if ((ap_ST_st71_fsm_71 == ap_CS_fsm)) begin
a1_we1 = grp_step0_fu_168_a_we1;
end else begin
a1_we1 = ap_const_logic_0;
end
end
/// ap_NS_fsm assign process. ///
always @ (ap_start or ap_CS_fsm or grp_step0_fu_168_ap_done or grp_step1_fu_180_ap_done or grp_write_r_fu_198_ap_done or grp_fetch_fu_209_ap_done or indvar_phi_fu_132_p4 or exitcond1_fu_274_p2 or exitcond_fu_286_p2 or exitcond2_fu_298_p2 or tmp_12_fu_310_p1)
begin
if (((ap_ST_st70_fsm_70 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond2_fu_298_p2) & ~(ap_const_lv1_0 == tmp_12_fu_310_p1))) begin
ap_NS_fsm = ap_ST_st72_fsm_72;
end else if (((ap_ST_st70_fsm_70 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond2_fu_298_p2) & (ap_const_lv1_0 == tmp_12_fu_310_p1))) begin
ap_NS_fsm = ap_ST_st71_fsm_71;
end else if ((((ap_ST_st72_fsm_72 == ap_CS_fsm) & ~((ap_const_logic_0 == grp_fetch_fu_209_ap_done) | (ap_const_logic_0 == grp_step0_fu_168_ap_done) | (ap_const_logic_0 == grp_step1_fu_180_ap_done) | (ap_const_logic_0 == grp_write_r_fu_198_ap_done))) | (~((ap_const_logic_0 == grp_fetch_fu_209_ap_done) | (ap_const_logic_0 == grp_step0_fu_168_ap_done) | (ap_const_logic_0 == grp_step1_fu_180_ap_done) | (ap_const_logic_0 == grp_write_r_fu_198_ap_done)) & (ap_ST_st71_fsm_71 == ap_CS_fsm)) | ((ap_ST_st69_fsm_69 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond_fu_286_p2)))) begin
ap_NS_fsm = ap_ST_st70_fsm_70;
end else if (((ap_ST_st68_fsm_68 == ap_CS_fsm) & ~(ap_const_logic_1 == ap_start) & ~(ap_const_lv1_0 == indvar_phi_fu_132_p4))) begin
ap_NS_fsm = ap_ST_st0_fsm_0;
end else if ((((ap_ST_st70_fsm_70 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond2_fu_298_p2)) | ((ap_ST_st68_fsm_68 == ap_CS_fsm) & (ap_const_lv1_0 == indvar_phi_fu_132_p4)))) begin
ap_NS_fsm = ap_ST_st69_fsm_69;
end else if ((ap_ST_st66_fsm_66 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st67_fsm_67;
end else if ((ap_ST_st65_fsm_65 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st66_fsm_66;
end else if ((((ap_ST_st64_fsm_64 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond1_fu_274_p2)) | ((ap_ST_st69_fsm_69 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond_fu_286_p2)))) begin
ap_NS_fsm = ap_ST_st68_fsm_68;
end else if (((ap_ST_st64_fsm_64 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond1_fu_274_p2))) begin
ap_NS_fsm = ap_ST_st65_fsm_65;
end else if (((ap_ST_st67_fsm_67 == ap_CS_fsm) | (ap_ST_st63_fsm_63 == ap_CS_fsm))) begin
ap_NS_fsm = ap_ST_st64_fsm_64;
end else if ((ap_ST_st62_fsm_62 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st63_fsm_63;
end else if ((ap_ST_st61_fsm_61 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st62_fsm_62;
end else if ((ap_ST_st60_fsm_60 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st61_fsm_61;
end else if ((ap_ST_st59_fsm_59 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st60_fsm_60;
end else if ((ap_ST_st58_fsm_58 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st59_fsm_59;
end else if ((ap_ST_st57_fsm_57 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st58_fsm_58;
end else if ((ap_ST_st56_fsm_56 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st57_fsm_57;
end else if ((ap_ST_st55_fsm_55 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st56_fsm_56;
end else if ((ap_ST_st54_fsm_54 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st55_fsm_55;
end else if ((ap_ST_st53_fsm_53 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st54_fsm_54;
end else if ((ap_ST_st52_fsm_52 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st53_fsm_53;
end else if ((ap_ST_st51_fsm_51 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st52_fsm_52;
end else if ((ap_ST_st50_fsm_50 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st51_fsm_51;
end else if ((ap_ST_st49_fsm_49 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st50_fsm_50;
end else if ((ap_ST_st48_fsm_48 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st49_fsm_49;
end else if ((ap_ST_st47_fsm_47 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st48_fsm_48;
end else if ((ap_ST_st46_fsm_46 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st47_fsm_47;
end else if ((ap_ST_st45_fsm_45 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st46_fsm_46;
end else if ((ap_ST_st44_fsm_44 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st45_fsm_45;
end else if ((ap_ST_st43_fsm_43 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st44_fsm_44;
end else if ((ap_ST_st42_fsm_42 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st43_fsm_43;
end else if ((ap_ST_st41_fsm_41 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st42_fsm_42;
end else if ((ap_ST_st40_fsm_40 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st41_fsm_41;
end else if ((ap_ST_st39_fsm_39 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st40_fsm_40;
end else if ((ap_ST_st38_fsm_38 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st39_fsm_39;
end else if ((ap_ST_st37_fsm_37 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st38_fsm_38;
end else if ((ap_ST_st36_fsm_36 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st37_fsm_37;
end else if ((ap_ST_st35_fsm_35 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st36_fsm_36;
end else if ((ap_ST_st34_fsm_34 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st35_fsm_35;
end else if ((ap_ST_st33_fsm_33 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st34_fsm_34;
end else if ((ap_ST_st32_fsm_32 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st33_fsm_33;
end else if ((ap_ST_st31_fsm_31 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st32_fsm_32;
end else if ((ap_ST_st30_fsm_30 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st31_fsm_31;
end else if ((ap_ST_st29_fsm_29 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st30_fsm_30;
end else if ((ap_ST_st28_fsm_28 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st29_fsm_29;
end else if ((ap_ST_st27_fsm_27 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st28_fsm_28;
end else if ((ap_ST_st26_fsm_26 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st27_fsm_27;
end else if ((ap_ST_st25_fsm_25 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st26_fsm_26;
end else if ((ap_ST_st24_fsm_24 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st25_fsm_25;
end else if ((ap_ST_st23_fsm_23 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st24_fsm_24;
end else if ((ap_ST_st22_fsm_22 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st23_fsm_23;
end else if ((ap_ST_st21_fsm_21 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st22_fsm_22;
end else if ((ap_ST_st20_fsm_20 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st21_fsm_21;
end else if ((ap_ST_st19_fsm_19 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st20_fsm_20;
end else if ((ap_ST_st18_fsm_18 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st19_fsm_19;
end else if ((ap_ST_st17_fsm_17 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st18_fsm_18;
end else if ((ap_ST_st16_fsm_16 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st17_fsm_17;
end else if ((ap_ST_st15_fsm_15 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st16_fsm_16;
end else if ((ap_ST_st14_fsm_14 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st15_fsm_15;
end else if ((ap_ST_st13_fsm_13 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st14_fsm_14;
end else if ((ap_ST_st12_fsm_12 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st13_fsm_13;
end else if ((ap_ST_st11_fsm_11 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st12_fsm_12;
end else if ((ap_ST_st10_fsm_10 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st11_fsm_11;
end else if ((ap_ST_st9_fsm_9 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st10_fsm_10;
end else if ((ap_ST_st8_fsm_8 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st9_fsm_9;
end else if ((ap_ST_st7_fsm_7 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st8_fsm_8;
end else if ((ap_ST_st6_fsm_6 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st7_fsm_7;
end else if ((ap_ST_st5_fsm_5 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st6_fsm_6;
end else if ((ap_ST_st4_fsm_4 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st5_fsm_5;
end else if ((ap_ST_st3_fsm_3 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st4_fsm_4;
end else if ((ap_ST_st2_fsm_2 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st3_fsm_3;
end else if ((ap_ST_st1_fsm_1 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st2_fsm_2;
end else if ((((ap_ST_st0_fsm_0 == ap_CS_fsm) & (ap_const_logic_1 == ap_start)) | ((ap_ST_st68_fsm_68 == ap_CS_fsm) & (ap_const_logic_1 == ap_start) & ~(ap_const_lv1_0 == indvar_phi_fu_132_p4)))) begin
ap_NS_fsm = ap_ST_st1_fsm_1;
end else begin
ap_NS_fsm = ap_CS_fsm;
end
end
/// ap_done assign process. ///
always @ (ap_CS_fsm or indvar_phi_fu_132_p4)
begin
if (((ap_ST_st68_fsm_68 == ap_CS_fsm) & ~(ap_const_lv1_0 == indvar_phi_fu_132_p4))) begin
ap_done = ap_const_logic_1;
end else begin
ap_done = ap_const_logic_0;
end
end
/// ap_idle assign process. ///
always @ (ap_CS_fsm)
begin
if ((ap_ST_st0_fsm_0 == ap_CS_fsm)) begin
ap_idle = ap_const_logic_1;
end else begin
ap_idle = ap_const_logic_0;
end
end
/// b0_address0 assign process. ///
always @ (ap_CS_fsm or grp_step0_fu_168_b_address0 or grp_step1_fu_180_b_address0)
begin
if ((ap_ST_st71_fsm_71 == ap_CS_fsm)) begin
b0_address0 = grp_step1_fu_180_b_address0;
end else if ((ap_ST_st72_fsm_72 == ap_CS_fsm)) begin
b0_address0 = grp_step0_fu_168_b_address0;
end else begin
b0_address0 = grp_step1_fu_180_b_address0;
end
end
/// b0_address1 assign process. ///
always @ (ap_CS_fsm or grp_step0_fu_168_b_address1 or grp_step1_fu_180_b_address1)
begin
if ((ap_ST_st71_fsm_71 == ap_CS_fsm)) begin
b0_address1 = grp_step1_fu_180_b_address1;
end else if ((ap_ST_st72_fsm_72 == ap_CS_fsm)) begin
b0_address1 = grp_step0_fu_168_b_address1;
end else begin
b0_address1 = grp_step1_fu_180_b_address1;
end
end
/// b0_ce0 assign process. ///
always @ (ap_CS_fsm or grp_step0_fu_168_b_ce0 or grp_step1_fu_180_b_ce0)
begin
if ((ap_ST_st71_fsm_71 == ap_CS_fsm)) begin
b0_ce0 = grp_step1_fu_180_b_ce0;
end else if ((ap_ST_st72_fsm_72 == ap_CS_fsm)) begin
b0_ce0 = grp_step0_fu_168_b_ce0;
end else begin
b0_ce0 = ap_const_logic_0;
end
end
/// b0_ce1 assign process. ///
always @ (ap_CS_fsm or grp_step0_fu_168_b_ce1 or grp_step1_fu_180_b_ce1)
begin
if ((ap_ST_st71_fsm_71 == ap_CS_fsm)) begin
b0_ce1 = grp_step1_fu_180_b_ce1;
end else if ((ap_ST_st72_fsm_72 == ap_CS_fsm)) begin
b0_ce1 = grp_step0_fu_168_b_ce1;
end else begin
b0_ce1 = ap_const_logic_0;
end
end
/// b0_we0 assign process. ///
always @ (ap_CS_fsm or grp_step0_fu_168_b_we0)
begin
if ((ap_ST_st72_fsm_72 == ap_CS_fsm)) begin
b0_we0 = grp_step0_fu_168_b_we0;
end else begin
b0_we0 = ap_const_logic_0;
end
end
/// b0_we1 assign process. ///
always @ (ap_CS_fsm or grp_step0_fu_168_b_we1)
begin
if ((ap_ST_st72_fsm_72 == ap_CS_fsm)) begin
b0_we1 = grp_step0_fu_168_b_we1;
end else begin
b0_we1 = ap_const_logic_0;
end
end
/// b1_address0 assign process. ///
always @ (ap_CS_fsm or grp_step0_fu_168_b_address0 or grp_step1_fu_180_b_address0)
begin
if ((ap_ST_st72_fsm_72 == ap_CS_fsm)) begin
b1_address0 = grp_step1_fu_180_b_address0;
end else if ((ap_ST_st71_fsm_71 == ap_CS_fsm)) begin
b1_address0 = grp_step0_fu_168_b_address0;
end else begin
b1_address0 = grp_step1_fu_180_b_address0;
end
end
/// b1_address1 assign process. ///
always @ (ap_CS_fsm or grp_step0_fu_168_b_address1 or grp_step1_fu_180_b_address1)
begin
if ((ap_ST_st72_fsm_72 == ap_CS_fsm)) begin
b1_address1 = grp_step1_fu_180_b_address1;
end else if ((ap_ST_st71_fsm_71 == ap_CS_fsm)) begin
b1_address1 = grp_step0_fu_168_b_address1;
end else begin
b1_address1 = grp_step1_fu_180_b_address1;
end
end
/// b1_ce0 assign process. ///
always @ (ap_CS_fsm or grp_step0_fu_168_b_ce0 or grp_step1_fu_180_b_ce0)
begin
if ((ap_ST_st72_fsm_72 == ap_CS_fsm)) begin
b1_ce0 = grp_step1_fu_180_b_ce0;
end else if ((ap_ST_st71_fsm_71 == ap_CS_fsm)) begin
b1_ce0 = grp_step0_fu_168_b_ce0;
end else begin
b1_ce0 = ap_const_logic_0;
end
end
/// b1_ce1 assign process. ///
always @ (ap_CS_fsm or grp_step0_fu_168_b_ce1 or grp_step1_fu_180_b_ce1)
begin
if ((ap_ST_st72_fsm_72 == ap_CS_fsm)) begin
b1_ce1 = grp_step1_fu_180_b_ce1;
end else if ((ap_ST_st71_fsm_71 == ap_CS_fsm)) begin
b1_ce1 = grp_step0_fu_168_b_ce1;
end else begin
b1_ce1 = ap_const_logic_0;
end
end
/// b1_we0 assign process. ///
always @ (ap_CS_fsm or grp_step0_fu_168_b_we0)
begin
if ((ap_ST_st71_fsm_71 == ap_CS_fsm)) begin
b1_we0 = grp_step0_fu_168_b_we0;
end else begin
b1_we0 = ap_const_logic_0;
end
end
/// b1_we1 assign process. ///
always @ (ap_CS_fsm or grp_step0_fu_168_b_we1)
begin
if ((ap_ST_st71_fsm_71 == ap_CS_fsm)) begin
b1_we1 = grp_step0_fu_168_b_we1;
end else begin
b1_we1 = ap_const_logic_0;
end
end
/// c0_address0 assign process. ///
always @ (ap_CS_fsm or grp_step1_fu_180_c_address0 or grp_step1_fu_180_c1_address0)
begin
if ((ap_ST_st72_fsm_72 == ap_CS_fsm)) begin
c0_address0 = grp_step1_fu_180_c1_address0;
end else if ((ap_ST_st71_fsm_71 == ap_CS_fsm)) begin
c0_address0 = grp_step1_fu_180_c_address0;
end else begin
c0_address0 = grp_step1_fu_180_c1_address0;
end
end
/// c0_address1 assign process. ///
always @ (ap_CS_fsm or grp_step1_fu_180_c_address1 or grp_step1_fu_180_c1_address1)
begin
if ((ap_ST_st72_fsm_72 == ap_CS_fsm)) begin
c0_address1 = grp_step1_fu_180_c1_address1;
end else if ((ap_ST_st71_fsm_71 == ap_CS_fsm)) begin
c0_address1 = grp_step1_fu_180_c_address1;
end else begin
c0_address1 = grp_step1_fu_180_c1_address1;
end
end
/// c0_ce0 assign process. ///
always @ (ap_CS_fsm or grp_step1_fu_180_c_ce0 or grp_step1_fu_180_c1_ce0)
begin
if ((ap_ST_st72_fsm_72 == ap_CS_fsm)) begin
c0_ce0 = grp_step1_fu_180_c1_ce0;
end else if ((ap_ST_st71_fsm_71 == ap_CS_fsm)) begin
c0_ce0 = grp_step1_fu_180_c_ce0;
end else begin
c0_ce0 = ap_const_logic_0;
end
end
/// c0_ce1 assign process. ///
always @ (ap_CS_fsm or grp_step1_fu_180_c_ce1 or grp_step1_fu_180_c1_ce1)
begin
if ((ap_ST_st72_fsm_72 == ap_CS_fsm)) begin
c0_ce1 = grp_step1_fu_180_c1_ce1;
end else if ((ap_ST_st71_fsm_71 == ap_CS_fsm)) begin
c0_ce1 = grp_step1_fu_180_c_ce1;
end else begin
c0_ce1 = ap_const_logic_0;
end
end
/// c0_we0 assign process. ///
always @ (ap_CS_fsm or grp_step1_fu_180_c1_we0)
begin
if ((ap_ST_st72_fsm_72 == ap_CS_fsm)) begin
c0_we0 = grp_step1_fu_180_c1_we0;
end else begin
c0_we0 = ap_const_logic_0;
end
end
/// c0_we1 assign process. ///
always @ (ap_CS_fsm or grp_step1_fu_180_c1_we1)
begin
if ((ap_ST_st72_fsm_72 == ap_CS_fsm)) begin
c0_we1 = grp_step1_fu_180_c1_we1;
end else begin
c0_we1 = ap_const_logic_0;
end
end
/// c1_address0 assign process. ///
always @ (ap_CS_fsm or grp_step1_fu_180_c_address0 or grp_step1_fu_180_c1_address0)
begin
if ((ap_ST_st71_fsm_71 == ap_CS_fsm)) begin
c1_address0 = grp_step1_fu_180_c1_address0;
end else if ((ap_ST_st72_fsm_72 == ap_CS_fsm)) begin
c1_address0 = grp_step1_fu_180_c_address0;
end else begin
c1_address0 = grp_step1_fu_180_c1_address0;
end
end
/// c1_address1 assign process. ///
always @ (ap_CS_fsm or grp_step1_fu_180_c_address1 or grp_step1_fu_180_c1_address1)
begin
if ((ap_ST_st71_fsm_71 == ap_CS_fsm)) begin
c1_address1 = grp_step1_fu_180_c1_address1;
end else if ((ap_ST_st72_fsm_72 == ap_CS_fsm)) begin
c1_address1 = grp_step1_fu_180_c_address1;
end else begin
c1_address1 = grp_step1_fu_180_c1_address1;
end
end
/// c1_ce0 assign process. ///
always @ (ap_CS_fsm or grp_step1_fu_180_c_ce0 or grp_step1_fu_180_c1_ce0)
begin
if ((ap_ST_st71_fsm_71 == ap_CS_fsm)) begin
c1_ce0 = grp_step1_fu_180_c1_ce0;
end else if ((ap_ST_st72_fsm_72 == ap_CS_fsm)) begin
c1_ce0 = grp_step1_fu_180_c_ce0;
end else begin
c1_ce0 = ap_const_logic_0;
end
end
/// c1_ce1 assign process. ///
always @ (ap_CS_fsm or grp_step1_fu_180_c_ce1 or grp_step1_fu_180_c1_ce1)
begin
if ((ap_ST_st71_fsm_71 == ap_CS_fsm)) begin
c1_ce1 = grp_step1_fu_180_c1_ce1;
end else if ((ap_ST_st72_fsm_72 == ap_CS_fsm)) begin
c1_ce1 = grp_step1_fu_180_c_ce1;
end else begin
c1_ce1 = ap_const_logic_0;
end
end
/// c1_we0 assign process. ///
always @ (ap_CS_fsm or grp_step1_fu_180_c1_we0)
begin
if ((ap_ST_st71_fsm_71 == ap_CS_fsm)) begin
c1_we0 = grp_step1_fu_180_c1_we0;
end else begin
c1_we0 = ap_const_logic_0;
end
end
/// c1_we1 assign process. ///
always @ (ap_CS_fsm or grp_step1_fu_180_c1_we1)
begin
if ((ap_ST_st71_fsm_71 == ap_CS_fsm)) begin
c1_we1 = grp_step1_fu_180_c1_we1;
end else begin
c1_we1 = ap_const_logic_0;
end
end
/// d0_address0 assign process. ///
always @ (ap_CS_fsm or grp_step1_fu_180_d_address0 or grp_write_r_fu_198_d_address0)
begin
if ((ap_ST_st72_fsm_72 == ap_CS_fsm)) begin
d0_address0 = grp_write_r_fu_198_d_address0;
end else if ((ap_ST_st71_fsm_71 == ap_CS_fsm)) begin
d0_address0 = grp_step1_fu_180_d_address0;
end else begin
d0_address0 = grp_write_r_fu_198_d_address0;
end
end
/// d0_address1 assign process. ///
always @ (ap_CS_fsm or grp_step1_fu_180_d_address1 or grp_write_r_fu_198_d_address1)
begin
if ((ap_ST_st72_fsm_72 == ap_CS_fsm)) begin
d0_address1 = grp_write_r_fu_198_d_address1;
end else if ((ap_ST_st71_fsm_71 == ap_CS_fsm)) begin
d0_address1 = grp_step1_fu_180_d_address1;
end else begin
d0_address1 = grp_write_r_fu_198_d_address1;
end
end
/// d0_ce0 assign process. ///
always @ (ap_CS_fsm or grp_step1_fu_180_d_ce0 or grp_write_r_fu_198_d_ce0)
begin
if ((ap_ST_st72_fsm_72 == ap_CS_fsm)) begin
d0_ce0 = grp_write_r_fu_198_d_ce0;
end else if ((ap_ST_st71_fsm_71 == ap_CS_fsm)) begin
d0_ce0 = grp_step1_fu_180_d_ce0;
end else begin
d0_ce0 = ap_const_logic_0;
end
end
/// d0_ce1 assign process. ///
always @ (ap_CS_fsm or grp_step1_fu_180_d_ce1 or grp_write_r_fu_198_d_ce1)
begin
if ((ap_ST_st72_fsm_72 == ap_CS_fsm)) begin
d0_ce1 = grp_write_r_fu_198_d_ce1;
end else if ((ap_ST_st71_fsm_71 == ap_CS_fsm)) begin
d0_ce1 = grp_step1_fu_180_d_ce1;
end else begin
d0_ce1 = ap_const_logic_0;
end
end
/// d0_we0 assign process. ///
always @ (ap_CS_fsm or grp_step1_fu_180_d_we0)
begin
if ((ap_ST_st71_fsm_71 == ap_CS_fsm)) begin
d0_we0 = grp_step1_fu_180_d_we0;
end else begin
d0_we0 = ap_const_logic_0;
end
end
/// d0_we1 assign process. ///
always @ (ap_CS_fsm or grp_step1_fu_180_d_we1)
begin
if ((ap_ST_st71_fsm_71 == ap_CS_fsm)) begin
d0_we1 = grp_step1_fu_180_d_we1;
end else begin
d0_we1 = ap_const_logic_0;
end
end
/// d1_address0 assign process. ///
always @ (ap_CS_fsm or grp_step1_fu_180_d_address0 or grp_write_r_fu_198_d_address0)
begin
if ((ap_ST_st71_fsm_71 == ap_CS_fsm)) begin
d1_address0 = grp_write_r_fu_198_d_address0;
end else if ((ap_ST_st72_fsm_72 == ap_CS_fsm)) begin
d1_address0 = grp_step1_fu_180_d_address0;
end else begin
d1_address0 = grp_write_r_fu_198_d_address0;
end
end
/// d1_address1 assign process. ///
always @ (ap_CS_fsm or grp_step1_fu_180_d_address1 or grp_write_r_fu_198_d_address1)
begin
if ((ap_ST_st71_fsm_71 == ap_CS_fsm)) begin
d1_address1 = grp_write_r_fu_198_d_address1;
end else if ((ap_ST_st72_fsm_72 == ap_CS_fsm)) begin
d1_address1 = grp_step1_fu_180_d_address1;
end else begin
d1_address1 = grp_write_r_fu_198_d_address1;
end
end
/// d1_ce0 assign process. ///
always @ (ap_CS_fsm or grp_step1_fu_180_d_ce0 or grp_write_r_fu_198_d_ce0)
begin
if ((ap_ST_st71_fsm_71 == ap_CS_fsm)) begin
d1_ce0 = grp_write_r_fu_198_d_ce0;
end else if ((ap_ST_st72_fsm_72 == ap_CS_fsm)) begin
d1_ce0 = grp_step1_fu_180_d_ce0;
end else begin
d1_ce0 = ap_const_logic_0;
end
end
/// d1_ce1 assign process. ///
always @ (ap_CS_fsm or grp_step1_fu_180_d_ce1 or grp_write_r_fu_198_d_ce1)
begin
if ((ap_ST_st71_fsm_71 == ap_CS_fsm)) begin
d1_ce1 = grp_write_r_fu_198_d_ce1;
end else if ((ap_ST_st72_fsm_72 == ap_CS_fsm)) begin
d1_ce1 = grp_step1_fu_180_d_ce1;
end else begin
d1_ce1 = ap_const_logic_0;
end
end
/// d1_we0 assign process. ///
always @ (ap_CS_fsm or grp_step1_fu_180_d_we0)
begin
if ((ap_ST_st72_fsm_72 == ap_CS_fsm)) begin
d1_we0 = grp_step1_fu_180_d_we0;
end else begin
d1_we0 = ap_const_logic_0;
end
end
/// d1_we1 assign process. ///
always @ (ap_CS_fsm or grp_step1_fu_180_d_we1)
begin
if ((ap_ST_st72_fsm_72 == ap_CS_fsm)) begin
d1_we1 = grp_step1_fu_180_d_we1;
end else begin
d1_we1 = ap_const_logic_0;
end
end
/// grp_fetch_fu_209_ap_start assign process. ///
always @ (ap_CS_fsm or exitcond2_fu_298_p2 or tmp_12_fu_310_p1)
begin
if ((((ap_ST_st70_fsm_70 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond2_fu_298_p2) & (ap_const_lv1_0 == tmp_12_fu_310_p1)) | ((ap_ST_st70_fsm_70 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond2_fu_298_p2) & ~(ap_const_lv1_0 == tmp_12_fu_310_p1)))) begin
grp_fetch_fu_209_ap_start = ap_const_logic_1;
end else begin
grp_fetch_fu_209_ap_start = ap_const_logic_0;
end
end
/// grp_fu_220_opcode assign process. ///
always @ (ap_CS_fsm)
begin
if (((ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st49_fsm_49 == ap_CS_fsm))) begin
grp_fu_220_opcode = ap_const_lv2_1;
end else if (((ap_ST_st19_fsm_19 == ap_CS_fsm) | (ap_ST_st29_fsm_29 == ap_CS_fsm))) begin
grp_fu_220_opcode = ap_const_lv2_0;
end else begin
grp_fu_220_opcode = ap_const_lv2_1;
end
end
/// grp_fu_220_p0 assign process. ///
always @ (ap_CS_fsm or reg_250 or reg_266)
begin
if ((ap_ST_st49_fsm_49 == ap_CS_fsm)) begin
grp_fu_220_p0 = ap_const_lv32_3F800000;
end else if ((ap_ST_st34_fsm_34 == ap_CS_fsm)) begin
grp_fu_220_p0 = reg_266;
end else if (((ap_ST_st19_fsm_19 == ap_CS_fsm) | (ap_ST_st29_fsm_29 == ap_CS_fsm))) begin
grp_fu_220_p0 = reg_250;
end else begin
grp_fu_220_p0 = ap_const_lv32_3F800000;
end
end
/// grp_fu_220_p1 assign process. ///
always @ (ap_CS_fsm or tmp_5_reg_320 or nu_reg_325)
begin
if ((ap_ST_st49_fsm_49 == ap_CS_fsm)) begin
grp_fu_220_p1 = nu_reg_325;
end else if ((ap_ST_st34_fsm_34 == ap_CS_fsm)) begin
grp_fu_220_p1 = tmp_5_reg_320;
end else if (((ap_ST_st19_fsm_19 == ap_CS_fsm) | (ap_ST_st29_fsm_29 == ap_CS_fsm))) begin
grp_fu_220_p1 = ap_const_lv32_3F800000;
end else begin
grp_fu_220_p1 = ap_const_lv32_3F800000;
end
end
/// grp_fu_226_ce assign process. ///
always @ (ap_CS_fsm or exitcond1_fu_274_p2)
begin
if (((ap_ST_st4_fsm_4 == ap_CS_fsm) | (ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st67_fsm_67 == ap_CS_fsm) | (ap_ST_st1_fsm_1 == ap_CS_fsm) | (ap_ST_st15_fsm_15 == ap_CS_fsm) | (ap_ST_st25_fsm_25 == ap_CS_fsm) | ((ap_ST_st64_fsm_64 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond1_fu_274_p2)) | (ap_ST_st2_fsm_2 == ap_CS_fsm) | (ap_ST_st3_fsm_3 == ap_CS_fsm) | (ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st17_fsm_17 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st27_fsm_27 == ap_CS_fsm) | (ap_ST_st65_fsm_65 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm))) begin
grp_fu_226_ce = ap_const_logic_1;
end else begin
grp_fu_226_ce = ap_const_logic_0;
end
end
/// grp_fu_226_p0 assign process. ///
always @ (ap_CS_fsm or std or reg_258 or tmp_8_reg_333 or exitcond1_fu_274_p2)
begin
if (((ap_ST_st64_fsm_64 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond1_fu_274_p2))) begin
grp_fu_226_p0 = tmp_8_reg_333;
end else if (((ap_ST_st15_fsm_15 == ap_CS_fsm) | (ap_ST_st25_fsm_25 == ap_CS_fsm))) begin
grp_fu_226_p0 = reg_258;
end else if ((ap_ST_st1_fsm_1 == ap_CS_fsm)) begin
grp_fu_226_p0 = std;
end else begin
grp_fu_226_p0 = tmp_8_reg_333;
end
end
/// grp_fu_226_p1 assign process. ///
always @ (ap_CS_fsm or std or PostScale_reg_115 or exitcond1_fu_274_p2)
begin
if (((ap_ST_st64_fsm_64 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond1_fu_274_p2))) begin
grp_fu_226_p1 = PostScale_reg_115;
end else if ((ap_ST_st25_fsm_25 == ap_CS_fsm)) begin
grp_fu_226_p1 = ap_const_lv32_40000000;
end else if ((ap_ST_st15_fsm_15 == ap_CS_fsm)) begin
grp_fu_226_p1 = ap_const_lv32_40800000;
end else if ((ap_ST_st1_fsm_1 == ap_CS_fsm)) begin
grp_fu_226_p1 = std;
end else begin
grp_fu_226_p1 = ap_const_lv32_40000000;
end
end
/// grp_fu_235_p0 assign process. ///
always @ (ap_CS_fsm or reg_250 or reg_266)
begin
if ((ap_ST_st54_fsm_54 == ap_CS_fsm)) begin
grp_fu_235_p0 = ap_const_lv32_3F800000;
end else if ((ap_ST_st39_fsm_39 == ap_CS_fsm)) begin
grp_fu_235_p0 = reg_266;
end else if ((ap_ST_st5_fsm_5 == ap_CS_fsm)) begin
grp_fu_235_p0 = reg_250;
end else begin
grp_fu_235_p0 = ap_const_lv32_3F800000;
end
end
/// grp_fu_235_p1 assign process. ///
always @ (ap_CS_fsm or reg_250 or reg_266)
begin
if ((ap_ST_st54_fsm_54 == ap_CS_fsm)) begin
grp_fu_235_p1 = reg_266;
end else if ((ap_ST_st39_fsm_39 == ap_CS_fsm)) begin
grp_fu_235_p1 = reg_250;
end else if ((ap_ST_st5_fsm_5 == ap_CS_fsm)) begin
grp_fu_235_p1 = ap_const_lv32_40000000;
end else begin
grp_fu_235_p1 = ap_const_lv32_40000000;
end
end
/// grp_step0_fu_168_a_q0 assign process. ///
always @ (ap_CS_fsm or a0_q0 or a1_q0)
begin
if ((ap_ST_st72_fsm_72 == ap_CS_fsm)) begin
grp_step0_fu_168_a_q0 = a0_q0;
end else if ((ap_ST_st71_fsm_71 == ap_CS_fsm)) begin
grp_step0_fu_168_a_q0 = a1_q0;
end else begin
grp_step0_fu_168_a_q0 = a1_q0;
end
end
/// grp_step0_fu_168_a_q1 assign process. ///
always @ (ap_CS_fsm or a0_q1 or a1_q1)
begin
if ((ap_ST_st72_fsm_72 == ap_CS_fsm)) begin
grp_step0_fu_168_a_q1 = a0_q1;
end else if ((ap_ST_st71_fsm_71 == ap_CS_fsm)) begin
grp_step0_fu_168_a_q1 = a1_q1;
end else begin
grp_step0_fu_168_a_q1 = a1_q1;
end
end
/// grp_step0_fu_168_ap_start assign process. ///
always @ (ap_CS_fsm or exitcond2_fu_298_p2 or tmp_12_fu_310_p1)
begin
if ((((ap_ST_st70_fsm_70 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond2_fu_298_p2) & (ap_const_lv1_0 == tmp_12_fu_310_p1)) | ((ap_ST_st70_fsm_70 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond2_fu_298_p2) & ~(ap_const_lv1_0 == tmp_12_fu_310_p1)))) begin
grp_step0_fu_168_ap_start = ap_const_logic_1;
end else begin
grp_step0_fu_168_ap_start = ap_const_logic_0;
end
end
/// grp_step0_fu_168_b_q0 assign process. ///
always @ (ap_CS_fsm or b0_q0 or b1_q0)
begin
if ((ap_ST_st72_fsm_72 == ap_CS_fsm)) begin
grp_step0_fu_168_b_q0 = b0_q0;
end else if ((ap_ST_st71_fsm_71 == ap_CS_fsm)) begin
grp_step0_fu_168_b_q0 = b1_q0;
end else begin
grp_step0_fu_168_b_q0 = b1_q0;
end
end
/// grp_step0_fu_168_b_q1 assign process. ///
always @ (ap_CS_fsm or b0_q1 or b1_q1)
begin
if ((ap_ST_st72_fsm_72 == ap_CS_fsm)) begin
grp_step0_fu_168_b_q1 = b0_q1;
end else if ((ap_ST_st71_fsm_71 == ap_CS_fsm)) begin
grp_step0_fu_168_b_q1 = b1_q1;
end else begin
grp_step0_fu_168_b_q1 = b1_q1;
end
end
/// grp_step1_fu_180_ap_start assign process. ///
always @ (ap_CS_fsm or exitcond2_fu_298_p2 or tmp_12_fu_310_p1)
begin
if ((((ap_ST_st70_fsm_70 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond2_fu_298_p2) & (ap_const_lv1_0 == tmp_12_fu_310_p1)) | ((ap_ST_st70_fsm_70 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond2_fu_298_p2) & ~(ap_const_lv1_0 == tmp_12_fu_310_p1)))) begin
grp_step1_fu_180_ap_start = ap_const_logic_1;
end else begin
grp_step1_fu_180_ap_start = ap_const_logic_0;
end
end
/// grp_step1_fu_180_b_q0 assign process. ///
always @ (ap_CS_fsm or b0_q0 or b1_q0)
begin
if ((ap_ST_st72_fsm_72 == ap_CS_fsm)) begin
grp_step1_fu_180_b_q0 = b1_q0;
end else if ((ap_ST_st71_fsm_71 == ap_CS_fsm)) begin
grp_step1_fu_180_b_q0 = b0_q0;
end else begin
grp_step1_fu_180_b_q0 = b1_q0;
end
end
/// grp_step1_fu_180_b_q1 assign process. ///
always @ (ap_CS_fsm or b0_q1 or b1_q1)
begin
if ((ap_ST_st72_fsm_72 == ap_CS_fsm)) begin
grp_step1_fu_180_b_q1 = b1_q1;
end else if ((ap_ST_st71_fsm_71 == ap_CS_fsm)) begin
grp_step1_fu_180_b_q1 = b0_q1;
end else begin
grp_step1_fu_180_b_q1 = b1_q1;
end
end
/// grp_step1_fu_180_c_q0 assign process. ///
always @ (ap_CS_fsm or c0_q0 or c1_q0)
begin
if ((ap_ST_st72_fsm_72 == ap_CS_fsm)) begin
grp_step1_fu_180_c_q0 = c1_q0;
end else if ((ap_ST_st71_fsm_71 == ap_CS_fsm)) begin
grp_step1_fu_180_c_q0 = c0_q0;
end else begin
grp_step1_fu_180_c_q0 = c1_q0;
end
end
/// grp_step1_fu_180_c_q1 assign process. ///
always @ (ap_CS_fsm or c0_q1 or c1_q1)
begin
if ((ap_ST_st72_fsm_72 == ap_CS_fsm)) begin
grp_step1_fu_180_c_q1 = c1_q1;
end else if ((ap_ST_st71_fsm_71 == ap_CS_fsm)) begin
grp_step1_fu_180_c_q1 = c0_q1;
end else begin
grp_step1_fu_180_c_q1 = c1_q1;
end
end
/// grp_write_r_fu_198_ap_start assign process. ///
always @ (ap_CS_fsm or exitcond2_fu_298_p2 or tmp_12_fu_310_p1)
begin
if ((((ap_ST_st70_fsm_70 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond2_fu_298_p2) & (ap_const_lv1_0 == tmp_12_fu_310_p1)) | ((ap_ST_st70_fsm_70 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond2_fu_298_p2) & ~(ap_const_lv1_0 == tmp_12_fu_310_p1)))) begin
grp_write_r_fu_198_ap_start = ap_const_logic_1;
end else begin
grp_write_r_fu_198_ap_start = ap_const_logic_0;
end
end
/// grp_write_r_fu_198_d_q0 assign process. ///
always @ (ap_CS_fsm or d0_q0 or d1_q0)
begin
if ((ap_ST_st72_fsm_72 == ap_CS_fsm)) begin
grp_write_r_fu_198_d_q0 = d0_q0;
end else if ((ap_ST_st71_fsm_71 == ap_CS_fsm)) begin
grp_write_r_fu_198_d_q0 = d1_q0;
end else begin
grp_write_r_fu_198_d_q0 = d1_q0;
end
end
/// grp_write_r_fu_198_d_q1 assign process. ///
always @ (ap_CS_fsm or d0_q1 or d1_q1)
begin
if ((ap_ST_st72_fsm_72 == ap_CS_fsm)) begin
grp_write_r_fu_198_d_q1 = d0_q1;
end else if ((ap_ST_st71_fsm_71 == ap_CS_fsm)) begin
grp_write_r_fu_198_d_q1 = d1_q1;
end else begin
grp_write_r_fu_198_d_q1 = d1_q1;
end
end
assign V1_bus_address = grp_fetch_fu_209_V_bus_address;
assign V1_bus_dataout = grp_fetch_fu_209_V_bus_dataout;
assign V1_bus_req_din = grp_fetch_fu_209_V_bus_req_din;
assign V1_bus_req_write = grp_fetch_fu_209_V_bus_req_write;
assign V1_bus_rsp_read = grp_fetch_fu_209_V_bus_rsp_read;
assign V1_bus_size = grp_fetch_fu_209_V_bus_size;
assign V2_bus_address = grp_write_r_fu_198_V_bus_address;
assign V2_bus_dataout = grp_write_r_fu_198_V_bus_dataout;
assign V2_bus_req_din = grp_write_r_fu_198_V_bus_req_din;
assign V2_bus_req_write = grp_write_r_fu_198_V_bus_req_write;
assign V2_bus_rsp_read = grp_write_r_fu_198_V_bus_rsp_read;
assign V2_bus_size = grp_write_r_fu_198_V_bus_size;
assign b0_d0 = grp_step0_fu_168_b_d0;
assign b0_d1 = grp_step0_fu_168_b_d1;
assign b1_d0 = grp_step0_fu_168_b_d0;
assign b1_d1 = grp_step0_fu_168_b_d1;
assign c0_d0 = grp_step1_fu_180_c1_d0;
assign c0_d1 = grp_step1_fu_180_c1_d1;
assign c1_d0 = grp_step1_fu_180_c1_d0;
assign c1_d1 = grp_step1_fu_180_c1_d1;
assign d0_d0 = grp_step1_fu_180_d_d0;
assign d0_d1 = grp_step1_fu_180_d_d1;
assign d1_d0 = grp_step1_fu_180_d_d0;
assign d1_d1 = grp_step1_fu_180_d_d1;
assign exitcond1_fu_274_p2 = (i_reg_104 == ap_const_lv2_3? 1'b1: 1'b0);
assign exitcond2_fu_298_p2 = (counter_reg_153 == ap_const_lv7_43? 1'b1: 1'b0);
assign exitcond_fu_286_p2 = (tag_reg_141 == ap_const_lv2_2? 1'b1: 1'b0);
assign grp_fetch_fu_209_V_bus_datain = V1_bus_datain;
assign grp_fetch_fu_209_V_bus_req_full_n = V1_bus_req_full_n;
assign grp_fetch_fu_209_V_bus_rsp_dout = V1_bus_rsp_dout;
assign grp_fetch_fu_209_V_bus_rsp_empty_n = V1_bus_rsp_empty_n;
assign grp_fetch_fu_209_counter = counter_reg_153;
assign grp_fetch_fu_209_tag = tag_reg_141;
assign grp_fu_220_ce = ap_const_logic_1;
assign grp_fu_235_ce = ap_const_logic_1;
assign grp_fu_241_ce = ap_const_logic_1;
assign grp_fu_241_p0 = nu_reg_325;
assign grp_fu_241_p1 = reg_258;
assign grp_fu_245_ce = ap_const_logic_1;
assign grp_fu_245_p0 = ap_const_lv32_1;
assign grp_fu_245_p1 = reg_266;
assign grp_step0_fu_168_BoundryScale = reg_258;
assign grp_step0_fu_168_counter = counter_reg_153;
assign grp_step0_fu_168_nu = nu_reg_325;
assign grp_step0_fu_168_tag = tag_reg_141;
assign grp_step1_fu_180_BoundryScale = reg_258;
assign grp_step1_fu_180_PostScale = PostScale_reg_115;
assign grp_step1_fu_180_counter = counter_reg_153;
assign grp_step1_fu_180_nu = nu_reg_325;
assign grp_step1_fu_180_step = indvar_reg_127;
assign grp_step1_fu_180_tag = tag_reg_141;
assign grp_write_r_fu_198_V_bus_datain = V2_bus_datain;
assign grp_write_r_fu_198_V_bus_req_full_n = V2_bus_req_full_n;
assign grp_write_r_fu_198_V_bus_rsp_dout = V2_bus_rsp_dout;
assign grp_write_r_fu_198_V_bus_rsp_empty_n = V2_bus_rsp_empty_n;
assign grp_write_r_fu_198_counter = counter_reg_153;
assign grp_write_r_fu_198_tag = tag_reg_141;
assign indvar_phi_fu_132_p4 = indvar_reg_127;
assign tmp_12_fu_310_p1 = counter_reg_153[0:0];
endmodule //Gaussianblur
|
// ==============================================================
// File generated by AutoESL - High-Level Synthesis System (C, C++, SystemC)
// Version: 2011.1
// Copyright (C) 2011 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module Gaussianblur_a0_core (q, ra, ce, clk
, d, wa, we);
parameter READ_PORT_COUNT=32'd2;
parameter WRITE_PORT_COUNT=32'd2;
parameter DATA_WIDTH=32'd32;
parameter ADDRESS_WIDTH=32'd12;
parameter WORD_COUNT=32'd4096;
output [READ_PORT_COUNT*DATA_WIDTH-1:0] q;
input [READ_PORT_COUNT*ADDRESS_WIDTH-1:0] ra;
input [READ_PORT_COUNT-1:0] ce;
input [WRITE_PORT_COUNT*DATA_WIDTH-1:0] d;
input [WRITE_PORT_COUNT*ADDRESS_WIDTH-1:0] wa;
input [WRITE_PORT_COUNT-1:0] we;
input clk;
integer i,j,k;
reg [DATA_WIDTH-1:0] mem [0:WORD_COUNT-1];
reg [ADDRESS_WIDTH-1:0] rat;
reg [ADDRESS_WIDTH-1:0] rai [READ_PORT_COUNT-1:0];
reg [ADDRESS_WIDTH-1:0] rai_reg [READ_PORT_COUNT-1:0];
reg [READ_PORT_COUNT*DATA_WIDTH-1:0] qi;
reg [DATA_WIDTH-1:0] qt;
reg [DATA_WIDTH-1:0] di [WRITE_PORT_COUNT-1:0];
reg [DATA_WIDTH-1:0] dt;
reg [ADDRESS_WIDTH-1:0] wat;
reg [ADDRESS_WIDTH-1:0] wai [WRITE_PORT_COUNT-1:0];
// Split input data
always @ (d) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<DATA_WIDTH;j=j+1) begin
dt[j]=d[i*DATA_WIDTH+j];
end
di[i]=dt;
end
end
// Split write addresses
always @ (wa) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
wat[j]=wa[i*ADDRESS_WIDTH+j];
end
wai[i]=wat;
end
end
// Write memory
always @ (posedge clk) begin
for (j=0;j<WRITE_PORT_COUNT;j=j+1) begin
if (we[j]) begin
mem[wai[j]] <= di[j];
end
end
end
// Split read addresses
always @ (ra) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
rat[j]=ra[i*ADDRESS_WIDTH+j];
end
rai[i]=rat;
end
end
// guide read addresses using CE
always @ (posedge clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if ( ce[i] ) begin
rai_reg[i] <= rai[i];
end
end
end
// Memory read
genvar x;
generate
for (x = 0; x < READ_PORT_COUNT; x = x + 1) begin : gen_q
assign q[x*DATA_WIDTH+DATA_WIDTH-1:x*DATA_WIDTH] = (rai_reg[x]<WORD_COUNT)?
mem[rai_reg[x]] : {DATA_WIDTH{1'b0}};
end
endgenerate
endmodule
module Gaussianblur_a0 (
address0,
ce0,
q0,
we0,
d0,
address1,
ce1,
q1,
we1,
d1,
clk);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd4096;
parameter AddressWidth = 32'd12;
input[AddressWidth-1:0] address0;
input ce0;
output[DataWidth-1:0] q0;
input we0;
input[DataWidth-1:0] d0;
input[AddressWidth-1:0] address1;
input ce1;
output[DataWidth-1:0] q1;
input we1;
input[DataWidth-1:0] d1;
input clk;
reg[DataWidth-1:0] q0;
reg[DataWidth-1:0] q1;
wire[2 * DataWidth - 1:0] mem_q;
wire[DataWidth - 1:0] mem_q0;
wire[DataWidth - 1:0] mem_q1;
wire[2 - 1:0] mem_we;
wire[2 * DataWidth - 1:0] mem_d;
wire[2 * AddressWidth - 1:0] mem_wa;
wire[2 * AddressWidth - 1:0] mem_ra;
wire[2 - 1:0] mem_ce;
Gaussianblur_a0_core #(
.READ_PORT_COUNT( 2 ),
.WRITE_PORT_COUNT( 2 ),
.DATA_WIDTH( DataWidth ),
.ADDRESS_WIDTH( AddressWidth ),
.WORD_COUNT( AddressRange ))
core_inst (
.q( mem_q ),
.ra( mem_ra ),
.ce( mem_ce ),
.d( mem_d ),
.wa( mem_wa ),
.we( mem_we ),
.clk( clk ));
assign mem_q0 = mem_q[2 * DataWidth - 1 : 1 * DataWidth];
always @ (mem_q0) begin
q0 = mem_q0;
end
assign mem_q1 = mem_q[1 * DataWidth - 1 : 0 * DataWidth];
always @ (mem_q1) begin
q1 = mem_q1;
end
assign mem_ra = {address0, address1};
assign mem_ce = {ce0, ce1};
assign mem_we[1] = we0;
assign mem_we[0] = we1;
assign mem_d = {d0, d1};
assign mem_wa = {address0, address1};
endmodule
|
// ==============================================================
// File generated by AutoESL - High-Level Synthesis System (C, C++, SystemC)
// Version: 2011.1
// Copyright (C) 2011 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module Gaussianblur_a1_core (q, ra, ce, clk
, d, wa, we);
parameter READ_PORT_COUNT=32'd2;
parameter WRITE_PORT_COUNT=32'd2;
parameter DATA_WIDTH=32'd32;
parameter ADDRESS_WIDTH=32'd12;
parameter WORD_COUNT=32'd4096;
output [READ_PORT_COUNT*DATA_WIDTH-1:0] q;
input [READ_PORT_COUNT*ADDRESS_WIDTH-1:0] ra;
input [READ_PORT_COUNT-1:0] ce;
input [WRITE_PORT_COUNT*DATA_WIDTH-1:0] d;
input [WRITE_PORT_COUNT*ADDRESS_WIDTH-1:0] wa;
input [WRITE_PORT_COUNT-1:0] we;
input clk;
integer i,j,k;
reg [DATA_WIDTH-1:0] mem [0:WORD_COUNT-1];
reg [ADDRESS_WIDTH-1:0] rat;
reg [ADDRESS_WIDTH-1:0] rai [READ_PORT_COUNT-1:0];
reg [ADDRESS_WIDTH-1:0] rai_reg [READ_PORT_COUNT-1:0];
reg [READ_PORT_COUNT*DATA_WIDTH-1:0] qi;
reg [DATA_WIDTH-1:0] qt;
reg [DATA_WIDTH-1:0] di [WRITE_PORT_COUNT-1:0];
reg [DATA_WIDTH-1:0] dt;
reg [ADDRESS_WIDTH-1:0] wat;
reg [ADDRESS_WIDTH-1:0] wai [WRITE_PORT_COUNT-1:0];
// Split input data
always @ (d) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<DATA_WIDTH;j=j+1) begin
dt[j]=d[i*DATA_WIDTH+j];
end
di[i]=dt;
end
end
// Split write addresses
always @ (wa) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
wat[j]=wa[i*ADDRESS_WIDTH+j];
end
wai[i]=wat;
end
end
// Write memory
always @ (posedge clk) begin
for (j=0;j<WRITE_PORT_COUNT;j=j+1) begin
if (we[j]) begin
mem[wai[j]] <= di[j];
end
end
end
// Split read addresses
always @ (ra) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
rat[j]=ra[i*ADDRESS_WIDTH+j];
end
rai[i]=rat;
end
end
// guide read addresses using CE
always @ (posedge clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if ( ce[i] ) begin
rai_reg[i] <= rai[i];
end
end
end
// Memory read
genvar x;
generate
for (x = 0; x < READ_PORT_COUNT; x = x + 1) begin : gen_q
assign q[x*DATA_WIDTH+DATA_WIDTH-1:x*DATA_WIDTH] = (rai_reg[x]<WORD_COUNT)?
mem[rai_reg[x]] : {DATA_WIDTH{1'b0}};
end
endgenerate
endmodule
module Gaussianblur_a1 (
address0,
ce0,
q0,
we0,
d0,
address1,
ce1,
q1,
we1,
d1,
clk);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd4096;
parameter AddressWidth = 32'd12;
input[AddressWidth-1:0] address0;
input ce0;
output[DataWidth-1:0] q0;
input we0;
input[DataWidth-1:0] d0;
input[AddressWidth-1:0] address1;
input ce1;
output[DataWidth-1:0] q1;
input we1;
input[DataWidth-1:0] d1;
input clk;
reg[DataWidth-1:0] q0;
reg[DataWidth-1:0] q1;
wire[2 * DataWidth - 1:0] mem_q;
wire[DataWidth - 1:0] mem_q0;
wire[DataWidth - 1:0] mem_q1;
wire[2 - 1:0] mem_we;
wire[2 * DataWidth - 1:0] mem_d;
wire[2 * AddressWidth - 1:0] mem_wa;
wire[2 * AddressWidth - 1:0] mem_ra;
wire[2 - 1:0] mem_ce;
Gaussianblur_a1_core #(
.READ_PORT_COUNT( 2 ),
.WRITE_PORT_COUNT( 2 ),
.DATA_WIDTH( DataWidth ),
.ADDRESS_WIDTH( AddressWidth ),
.WORD_COUNT( AddressRange ))
core_inst (
.q( mem_q ),
.ra( mem_ra ),
.ce( mem_ce ),
.d( mem_d ),
.wa( mem_wa ),
.we( mem_we ),
.clk( clk ));
assign mem_q0 = mem_q[2 * DataWidth - 1 : 1 * DataWidth];
always @ (mem_q0) begin
q0 = mem_q0;
end
assign mem_q1 = mem_q[1 * DataWidth - 1 : 0 * DataWidth];
always @ (mem_q1) begin
q1 = mem_q1;
end
assign mem_ra = {address0, address1};
assign mem_ce = {ce0, ce1};
assign mem_we[1] = we0;
assign mem_we[0] = we1;
assign mem_d = {d0, d1};
assign mem_wa = {address0, address1};
endmodule
|
// ==============================================================
// File generated by AutoESL - High-Level Synthesis System (C, C++, SystemC)
// Version: 2011.1
// Copyright (C) 2011 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module Gaussianblur_b0_core (q, ra, ce, clk
, d, wa, we);
parameter READ_PORT_COUNT=32'd2;
parameter WRITE_PORT_COUNT=32'd2;
parameter DATA_WIDTH=32'd32;
parameter ADDRESS_WIDTH=32'd12;
parameter WORD_COUNT=32'd4096;
output [READ_PORT_COUNT*DATA_WIDTH-1:0] q;
input [READ_PORT_COUNT*ADDRESS_WIDTH-1:0] ra;
input [READ_PORT_COUNT-1:0] ce;
input [WRITE_PORT_COUNT*DATA_WIDTH-1:0] d;
input [WRITE_PORT_COUNT*ADDRESS_WIDTH-1:0] wa;
input [WRITE_PORT_COUNT-1:0] we;
input clk;
integer i,j,k;
reg [DATA_WIDTH-1:0] mem [0:WORD_COUNT-1];
reg [ADDRESS_WIDTH-1:0] rat;
reg [ADDRESS_WIDTH-1:0] rai [READ_PORT_COUNT-1:0];
reg [ADDRESS_WIDTH-1:0] rai_reg [READ_PORT_COUNT-1:0];
reg [READ_PORT_COUNT*DATA_WIDTH-1:0] qi;
reg [DATA_WIDTH-1:0] qt;
reg [DATA_WIDTH-1:0] di [WRITE_PORT_COUNT-1:0];
reg [DATA_WIDTH-1:0] dt;
reg [ADDRESS_WIDTH-1:0] wat;
reg [ADDRESS_WIDTH-1:0] wai [WRITE_PORT_COUNT-1:0];
// Split input data
always @ (d) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<DATA_WIDTH;j=j+1) begin
dt[j]=d[i*DATA_WIDTH+j];
end
di[i]=dt;
end
end
// Split write addresses
always @ (wa) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
wat[j]=wa[i*ADDRESS_WIDTH+j];
end
wai[i]=wat;
end
end
// Write memory
always @ (posedge clk) begin
for (j=0;j<WRITE_PORT_COUNT;j=j+1) begin
if (we[j]) begin
mem[wai[j]] <= di[j];
end
end
end
// Split read addresses
always @ (ra) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
rat[j]=ra[i*ADDRESS_WIDTH+j];
end
rai[i]=rat;
end
end
// guide read addresses using CE
always @ (posedge clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if ( ce[i] ) begin
rai_reg[i] <= rai[i];
end
end
end
// Memory read
genvar x;
generate
for (x = 0; x < READ_PORT_COUNT; x = x + 1) begin : gen_q
assign q[x*DATA_WIDTH+DATA_WIDTH-1:x*DATA_WIDTH] = (rai_reg[x]<WORD_COUNT)?
mem[rai_reg[x]] : {DATA_WIDTH{1'b0}};
end
endgenerate
endmodule
module Gaussianblur_b0 (
address0,
ce0,
q0,
we0,
d0,
address1,
ce1,
q1,
we1,
d1,
clk);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd4096;
parameter AddressWidth = 32'd12;
input[AddressWidth-1:0] address0;
input ce0;
output[DataWidth-1:0] q0;
input we0;
input[DataWidth-1:0] d0;
input[AddressWidth-1:0] address1;
input ce1;
output[DataWidth-1:0] q1;
input we1;
input[DataWidth-1:0] d1;
input clk;
reg[DataWidth-1:0] q0;
reg[DataWidth-1:0] q1;
wire[2 * DataWidth - 1:0] mem_q;
wire[DataWidth - 1:0] mem_q0;
wire[DataWidth - 1:0] mem_q1;
wire[2 - 1:0] mem_we;
wire[2 * DataWidth - 1:0] mem_d;
wire[2 * AddressWidth - 1:0] mem_wa;
wire[2 * AddressWidth - 1:0] mem_ra;
wire[2 - 1:0] mem_ce;
Gaussianblur_b0_core #(
.READ_PORT_COUNT( 2 ),
.WRITE_PORT_COUNT( 2 ),
.DATA_WIDTH( DataWidth ),
.ADDRESS_WIDTH( AddressWidth ),
.WORD_COUNT( AddressRange ))
core_inst (
.q( mem_q ),
.ra( mem_ra ),
.ce( mem_ce ),
.d( mem_d ),
.wa( mem_wa ),
.we( mem_we ),
.clk( clk ));
assign mem_q0 = mem_q[2 * DataWidth - 1 : 1 * DataWidth];
always @ (mem_q0) begin
q0 = mem_q0;
end
assign mem_q1 = mem_q[1 * DataWidth - 1 : 0 * DataWidth];
always @ (mem_q1) begin
q1 = mem_q1;
end
assign mem_ra = {address0, address1};
assign mem_ce = {ce0, ce1};
assign mem_we[1] = we0;
assign mem_we[0] = we1;
assign mem_d = {d0, d1};
assign mem_wa = {address0, address1};
endmodule
|
// ==============================================================
// File generated by AutoESL - High-Level Synthesis System (C, C++, SystemC)
// Version: 2011.1
// Copyright (C) 2011 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module Gaussianblur_b1_core (q, ra, ce, clk
, d, wa, we);
parameter READ_PORT_COUNT=32'd2;
parameter WRITE_PORT_COUNT=32'd2;
parameter DATA_WIDTH=32'd32;
parameter ADDRESS_WIDTH=32'd12;
parameter WORD_COUNT=32'd4096;
output [READ_PORT_COUNT*DATA_WIDTH-1:0] q;
input [READ_PORT_COUNT*ADDRESS_WIDTH-1:0] ra;
input [READ_PORT_COUNT-1:0] ce;
input [WRITE_PORT_COUNT*DATA_WIDTH-1:0] d;
input [WRITE_PORT_COUNT*ADDRESS_WIDTH-1:0] wa;
input [WRITE_PORT_COUNT-1:0] we;
input clk;
integer i,j,k;
reg [DATA_WIDTH-1:0] mem [0:WORD_COUNT-1];
reg [ADDRESS_WIDTH-1:0] rat;
reg [ADDRESS_WIDTH-1:0] rai [READ_PORT_COUNT-1:0];
reg [ADDRESS_WIDTH-1:0] rai_reg [READ_PORT_COUNT-1:0];
reg [READ_PORT_COUNT*DATA_WIDTH-1:0] qi;
reg [DATA_WIDTH-1:0] qt;
reg [DATA_WIDTH-1:0] di [WRITE_PORT_COUNT-1:0];
reg [DATA_WIDTH-1:0] dt;
reg [ADDRESS_WIDTH-1:0] wat;
reg [ADDRESS_WIDTH-1:0] wai [WRITE_PORT_COUNT-1:0];
// Split input data
always @ (d) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<DATA_WIDTH;j=j+1) begin
dt[j]=d[i*DATA_WIDTH+j];
end
di[i]=dt;
end
end
// Split write addresses
always @ (wa) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
wat[j]=wa[i*ADDRESS_WIDTH+j];
end
wai[i]=wat;
end
end
// Write memory
always @ (posedge clk) begin
for (j=0;j<WRITE_PORT_COUNT;j=j+1) begin
if (we[j]) begin
mem[wai[j]] <= di[j];
end
end
end
// Split read addresses
always @ (ra) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
rat[j]=ra[i*ADDRESS_WIDTH+j];
end
rai[i]=rat;
end
end
// guide read addresses using CE
always @ (posedge clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if ( ce[i] ) begin
rai_reg[i] <= rai[i];
end
end
end
// Memory read
genvar x;
generate
for (x = 0; x < READ_PORT_COUNT; x = x + 1) begin : gen_q
assign q[x*DATA_WIDTH+DATA_WIDTH-1:x*DATA_WIDTH] = (rai_reg[x]<WORD_COUNT)?
mem[rai_reg[x]] : {DATA_WIDTH{1'b0}};
end
endgenerate
endmodule
module Gaussianblur_b1 (
address0,
ce0,
q0,
we0,
d0,
address1,
ce1,
q1,
we1,
d1,
clk);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd4096;
parameter AddressWidth = 32'd12;
input[AddressWidth-1:0] address0;
input ce0;
output[DataWidth-1:0] q0;
input we0;
input[DataWidth-1:0] d0;
input[AddressWidth-1:0] address1;
input ce1;
output[DataWidth-1:0] q1;
input we1;
input[DataWidth-1:0] d1;
input clk;
reg[DataWidth-1:0] q0;
reg[DataWidth-1:0] q1;
wire[2 * DataWidth - 1:0] mem_q;
wire[DataWidth - 1:0] mem_q0;
wire[DataWidth - 1:0] mem_q1;
wire[2 - 1:0] mem_we;
wire[2 * DataWidth - 1:0] mem_d;
wire[2 * AddressWidth - 1:0] mem_wa;
wire[2 * AddressWidth - 1:0] mem_ra;
wire[2 - 1:0] mem_ce;
Gaussianblur_b1_core #(
.READ_PORT_COUNT( 2 ),
.WRITE_PORT_COUNT( 2 ),
.DATA_WIDTH( DataWidth ),
.ADDRESS_WIDTH( AddressWidth ),
.WORD_COUNT( AddressRange ))
core_inst (
.q( mem_q ),
.ra( mem_ra ),
.ce( mem_ce ),
.d( mem_d ),
.wa( mem_wa ),
.we( mem_we ),
.clk( clk ));
assign mem_q0 = mem_q[2 * DataWidth - 1 : 1 * DataWidth];
always @ (mem_q0) begin
q0 = mem_q0;
end
assign mem_q1 = mem_q[1 * DataWidth - 1 : 0 * DataWidth];
always @ (mem_q1) begin
q1 = mem_q1;
end
assign mem_ra = {address0, address1};
assign mem_ce = {ce0, ce1};
assign mem_we[1] = we0;
assign mem_we[0] = we1;
assign mem_d = {d0, d1};
assign mem_wa = {address0, address1};
endmodule
|
// ==============================================================
// File generated by AutoESL - High-Level Synthesis System (C, C++, SystemC)
// Version: 2011.1
// Copyright (C) 2011 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module Gaussianblur_c0_core (q, ra, ce, clk
, d, wa, we);
parameter READ_PORT_COUNT=32'd2;
parameter WRITE_PORT_COUNT=32'd2;
parameter DATA_WIDTH=32'd32;
parameter ADDRESS_WIDTH=32'd12;
parameter WORD_COUNT=32'd4096;
output [READ_PORT_COUNT*DATA_WIDTH-1:0] q;
input [READ_PORT_COUNT*ADDRESS_WIDTH-1:0] ra;
input [READ_PORT_COUNT-1:0] ce;
input [WRITE_PORT_COUNT*DATA_WIDTH-1:0] d;
input [WRITE_PORT_COUNT*ADDRESS_WIDTH-1:0] wa;
input [WRITE_PORT_COUNT-1:0] we;
input clk;
integer i,j,k;
reg [DATA_WIDTH-1:0] mem [0:WORD_COUNT-1];
reg [ADDRESS_WIDTH-1:0] rat;
reg [ADDRESS_WIDTH-1:0] rai [READ_PORT_COUNT-1:0];
reg [ADDRESS_WIDTH-1:0] rai_reg [READ_PORT_COUNT-1:0];
reg [READ_PORT_COUNT*DATA_WIDTH-1:0] qi;
reg [DATA_WIDTH-1:0] qt;
reg [DATA_WIDTH-1:0] di [WRITE_PORT_COUNT-1:0];
reg [DATA_WIDTH-1:0] dt;
reg [ADDRESS_WIDTH-1:0] wat;
reg [ADDRESS_WIDTH-1:0] wai [WRITE_PORT_COUNT-1:0];
// Split input data
always @ (d) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<DATA_WIDTH;j=j+1) begin
dt[j]=d[i*DATA_WIDTH+j];
end
di[i]=dt;
end
end
// Split write addresses
always @ (wa) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
wat[j]=wa[i*ADDRESS_WIDTH+j];
end
wai[i]=wat;
end
end
// Write memory
always @ (posedge clk) begin
for (j=0;j<WRITE_PORT_COUNT;j=j+1) begin
if (we[j]) begin
mem[wai[j]] <= di[j];
end
end
end
// Split read addresses
always @ (ra) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
rat[j]=ra[i*ADDRESS_WIDTH+j];
end
rai[i]=rat;
end
end
// guide read addresses using CE
always @ (posedge clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if ( ce[i] ) begin
rai_reg[i] <= rai[i];
end
end
end
// Memory read
genvar x;
generate
for (x = 0; x < READ_PORT_COUNT; x = x + 1) begin : gen_q
assign q[x*DATA_WIDTH+DATA_WIDTH-1:x*DATA_WIDTH] = (rai_reg[x]<WORD_COUNT)?
mem[rai_reg[x]] : {DATA_WIDTH{1'b0}};
end
endgenerate
endmodule
module Gaussianblur_c0 (
address0,
ce0,
q0,
we0,
d0,
address1,
ce1,
q1,
we1,
d1,
clk);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd4096;
parameter AddressWidth = 32'd12;
input[AddressWidth-1:0] address0;
input ce0;
output[DataWidth-1:0] q0;
input we0;
input[DataWidth-1:0] d0;
input[AddressWidth-1:0] address1;
input ce1;
output[DataWidth-1:0] q1;
input we1;
input[DataWidth-1:0] d1;
input clk;
reg[DataWidth-1:0] q0;
reg[DataWidth-1:0] q1;
wire[2 * DataWidth - 1:0] mem_q;
wire[DataWidth - 1:0] mem_q0;
wire[DataWidth - 1:0] mem_q1;
wire[2 - 1:0] mem_we;
wire[2 * DataWidth - 1:0] mem_d;
wire[2 * AddressWidth - 1:0] mem_wa;
wire[2 * AddressWidth - 1:0] mem_ra;
wire[2 - 1:0] mem_ce;
Gaussianblur_c0_core #(
.READ_PORT_COUNT( 2 ),
.WRITE_PORT_COUNT( 2 ),
.DATA_WIDTH( DataWidth ),
.ADDRESS_WIDTH( AddressWidth ),
.WORD_COUNT( AddressRange ))
core_inst (
.q( mem_q ),
.ra( mem_ra ),
.ce( mem_ce ),
.d( mem_d ),
.wa( mem_wa ),
.we( mem_we ),
.clk( clk ));
assign mem_q0 = mem_q[2 * DataWidth - 1 : 1 * DataWidth];
always @ (mem_q0) begin
q0 = mem_q0;
end
assign mem_q1 = mem_q[1 * DataWidth - 1 : 0 * DataWidth];
always @ (mem_q1) begin
q1 = mem_q1;
end
assign mem_ra = {address0, address1};
assign mem_ce = {ce0, ce1};
assign mem_we[1] = we0;
assign mem_we[0] = we1;
assign mem_d = {d0, d1};
assign mem_wa = {address0, address1};
endmodule
|
// ==============================================================
// File generated by AutoESL - High-Level Synthesis System (C, C++, SystemC)
// Version: 2011.1
// Copyright (C) 2011 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module Gaussianblur_c1_core (q, ra, ce, clk
, d, wa, we);
parameter READ_PORT_COUNT=32'd2;
parameter WRITE_PORT_COUNT=32'd2;
parameter DATA_WIDTH=32'd32;
parameter ADDRESS_WIDTH=32'd12;
parameter WORD_COUNT=32'd4096;
output [READ_PORT_COUNT*DATA_WIDTH-1:0] q;
input [READ_PORT_COUNT*ADDRESS_WIDTH-1:0] ra;
input [READ_PORT_COUNT-1:0] ce;
input [WRITE_PORT_COUNT*DATA_WIDTH-1:0] d;
input [WRITE_PORT_COUNT*ADDRESS_WIDTH-1:0] wa;
input [WRITE_PORT_COUNT-1:0] we;
input clk;
integer i,j,k;
reg [DATA_WIDTH-1:0] mem [0:WORD_COUNT-1];
reg [ADDRESS_WIDTH-1:0] rat;
reg [ADDRESS_WIDTH-1:0] rai [READ_PORT_COUNT-1:0];
reg [ADDRESS_WIDTH-1:0] rai_reg [READ_PORT_COUNT-1:0];
reg [READ_PORT_COUNT*DATA_WIDTH-1:0] qi;
reg [DATA_WIDTH-1:0] qt;
reg [DATA_WIDTH-1:0] di [WRITE_PORT_COUNT-1:0];
reg [DATA_WIDTH-1:0] dt;
reg [ADDRESS_WIDTH-1:0] wat;
reg [ADDRESS_WIDTH-1:0] wai [WRITE_PORT_COUNT-1:0];
// Split input data
always @ (d) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<DATA_WIDTH;j=j+1) begin
dt[j]=d[i*DATA_WIDTH+j];
end
di[i]=dt;
end
end
// Split write addresses
always @ (wa) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
wat[j]=wa[i*ADDRESS_WIDTH+j];
end
wai[i]=wat;
end
end
// Write memory
always @ (posedge clk) begin
for (j=0;j<WRITE_PORT_COUNT;j=j+1) begin
if (we[j]) begin
mem[wai[j]] <= di[j];
end
end
end
// Split read addresses
always @ (ra) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
rat[j]=ra[i*ADDRESS_WIDTH+j];
end
rai[i]=rat;
end
end
// guide read addresses using CE
always @ (posedge clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if ( ce[i] ) begin
rai_reg[i] <= rai[i];
end
end
end
// Memory read
genvar x;
generate
for (x = 0; x < READ_PORT_COUNT; x = x + 1) begin : gen_q
assign q[x*DATA_WIDTH+DATA_WIDTH-1:x*DATA_WIDTH] = (rai_reg[x]<WORD_COUNT)?
mem[rai_reg[x]] : {DATA_WIDTH{1'b0}};
end
endgenerate
endmodule
module Gaussianblur_c1 (
address0,
ce0,
q0,
we0,
d0,
address1,
ce1,
q1,
we1,
d1,
clk);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd4096;
parameter AddressWidth = 32'd12;
input[AddressWidth-1:0] address0;
input ce0;
output[DataWidth-1:0] q0;
input we0;
input[DataWidth-1:0] d0;
input[AddressWidth-1:0] address1;
input ce1;
output[DataWidth-1:0] q1;
input we1;
input[DataWidth-1:0] d1;
input clk;
reg[DataWidth-1:0] q0;
reg[DataWidth-1:0] q1;
wire[2 * DataWidth - 1:0] mem_q;
wire[DataWidth - 1:0] mem_q0;
wire[DataWidth - 1:0] mem_q1;
wire[2 - 1:0] mem_we;
wire[2 * DataWidth - 1:0] mem_d;
wire[2 * AddressWidth - 1:0] mem_wa;
wire[2 * AddressWidth - 1:0] mem_ra;
wire[2 - 1:0] mem_ce;
Gaussianblur_c1_core #(
.READ_PORT_COUNT( 2 ),
.WRITE_PORT_COUNT( 2 ),
.DATA_WIDTH( DataWidth ),
.ADDRESS_WIDTH( AddressWidth ),
.WORD_COUNT( AddressRange ))
core_inst (
.q( mem_q ),
.ra( mem_ra ),
.ce( mem_ce ),
.d( mem_d ),
.wa( mem_wa ),
.we( mem_we ),
.clk( clk ));
assign mem_q0 = mem_q[2 * DataWidth - 1 : 1 * DataWidth];
always @ (mem_q0) begin
q0 = mem_q0;
end
assign mem_q1 = mem_q[1 * DataWidth - 1 : 0 * DataWidth];
always @ (mem_q1) begin
q1 = mem_q1;
end
assign mem_ra = {address0, address1};
assign mem_ce = {ce0, ce1};
assign mem_we[1] = we0;
assign mem_we[0] = we1;
assign mem_d = {d0, d1};
assign mem_wa = {address0, address1};
endmodule
|
// ==============================================================
// File generated by AutoESL - High-Level Synthesis System (C, C++, SystemC)
// Version: 2011.1
// Copyright (C) 2011 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module Gaussianblur_d0_core (q, ra, ce, clk
, d, wa, we);
parameter READ_PORT_COUNT=32'd2;
parameter WRITE_PORT_COUNT=32'd2;
parameter DATA_WIDTH=32'd32;
parameter ADDRESS_WIDTH=32'd12;
parameter WORD_COUNT=32'd4096;
output [READ_PORT_COUNT*DATA_WIDTH-1:0] q;
input [READ_PORT_COUNT*ADDRESS_WIDTH-1:0] ra;
input [READ_PORT_COUNT-1:0] ce;
input [WRITE_PORT_COUNT*DATA_WIDTH-1:0] d;
input [WRITE_PORT_COUNT*ADDRESS_WIDTH-1:0] wa;
input [WRITE_PORT_COUNT-1:0] we;
input clk;
integer i,j,k;
reg [DATA_WIDTH-1:0] mem [0:WORD_COUNT-1];
reg [ADDRESS_WIDTH-1:0] rat;
reg [ADDRESS_WIDTH-1:0] rai [READ_PORT_COUNT-1:0];
reg [ADDRESS_WIDTH-1:0] rai_reg [READ_PORT_COUNT-1:0];
reg [READ_PORT_COUNT*DATA_WIDTH-1:0] qi;
reg [DATA_WIDTH-1:0] qt;
reg [DATA_WIDTH-1:0] di [WRITE_PORT_COUNT-1:0];
reg [DATA_WIDTH-1:0] dt;
reg [ADDRESS_WIDTH-1:0] wat;
reg [ADDRESS_WIDTH-1:0] wai [WRITE_PORT_COUNT-1:0];
// Split input data
always @ (d) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<DATA_WIDTH;j=j+1) begin
dt[j]=d[i*DATA_WIDTH+j];
end
di[i]=dt;
end
end
// Split write addresses
always @ (wa) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
wat[j]=wa[i*ADDRESS_WIDTH+j];
end
wai[i]=wat;
end
end
// Write memory
always @ (posedge clk) begin
for (j=0;j<WRITE_PORT_COUNT;j=j+1) begin
if (we[j]) begin
mem[wai[j]] <= di[j];
end
end
end
// Split read addresses
always @ (ra) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
rat[j]=ra[i*ADDRESS_WIDTH+j];
end
rai[i]=rat;
end
end
// guide read addresses using CE
always @ (posedge clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if ( ce[i] ) begin
rai_reg[i] <= rai[i];
end
end
end
// Memory read
genvar x;
generate
for (x = 0; x < READ_PORT_COUNT; x = x + 1) begin : gen_q
assign q[x*DATA_WIDTH+DATA_WIDTH-1:x*DATA_WIDTH] = (rai_reg[x]<WORD_COUNT)?
mem[rai_reg[x]] : {DATA_WIDTH{1'b0}};
end
endgenerate
endmodule
module Gaussianblur_d0 (
address0,
ce0,
q0,
we0,
d0,
address1,
ce1,
q1,
we1,
d1,
clk);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd4096;
parameter AddressWidth = 32'd12;
input[AddressWidth-1:0] address0;
input ce0;
output[DataWidth-1:0] q0;
input we0;
input[DataWidth-1:0] d0;
input[AddressWidth-1:0] address1;
input ce1;
output[DataWidth-1:0] q1;
input we1;
input[DataWidth-1:0] d1;
input clk;
reg[DataWidth-1:0] q0;
reg[DataWidth-1:0] q1;
wire[2 * DataWidth - 1:0] mem_q;
wire[DataWidth - 1:0] mem_q0;
wire[DataWidth - 1:0] mem_q1;
wire[2 - 1:0] mem_we;
wire[2 * DataWidth - 1:0] mem_d;
wire[2 * AddressWidth - 1:0] mem_wa;
wire[2 * AddressWidth - 1:0] mem_ra;
wire[2 - 1:0] mem_ce;
Gaussianblur_d0_core #(
.READ_PORT_COUNT( 2 ),
.WRITE_PORT_COUNT( 2 ),
.DATA_WIDTH( DataWidth ),
.ADDRESS_WIDTH( AddressWidth ),
.WORD_COUNT( AddressRange ))
core_inst (
.q( mem_q ),
.ra( mem_ra ),
.ce( mem_ce ),
.d( mem_d ),
.wa( mem_wa ),
.we( mem_we ),
.clk( clk ));
assign mem_q0 = mem_q[2 * DataWidth - 1 : 1 * DataWidth];
always @ (mem_q0) begin
q0 = mem_q0;
end
assign mem_q1 = mem_q[1 * DataWidth - 1 : 0 * DataWidth];
always @ (mem_q1) begin
q1 = mem_q1;
end
assign mem_ra = {address0, address1};
assign mem_ce = {ce0, ce1};
assign mem_we[1] = we0;
assign mem_we[0] = we1;
assign mem_d = {d0, d1};
assign mem_wa = {address0, address1};
endmodule
|
// ==============================================================
// File generated by AutoESL - High-Level Synthesis System (C, C++, SystemC)
// Version: 2011.1
// Copyright (C) 2011 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module Gaussianblur_d1_core (q, ra, ce, clk
, d, wa, we);
parameter READ_PORT_COUNT=32'd2;
parameter WRITE_PORT_COUNT=32'd2;
parameter DATA_WIDTH=32'd32;
parameter ADDRESS_WIDTH=32'd12;
parameter WORD_COUNT=32'd4096;
output [READ_PORT_COUNT*DATA_WIDTH-1:0] q;
input [READ_PORT_COUNT*ADDRESS_WIDTH-1:0] ra;
input [READ_PORT_COUNT-1:0] ce;
input [WRITE_PORT_COUNT*DATA_WIDTH-1:0] d;
input [WRITE_PORT_COUNT*ADDRESS_WIDTH-1:0] wa;
input [WRITE_PORT_COUNT-1:0] we;
input clk;
integer i,j,k;
reg [DATA_WIDTH-1:0] mem [0:WORD_COUNT-1];
reg [ADDRESS_WIDTH-1:0] rat;
reg [ADDRESS_WIDTH-1:0] rai [READ_PORT_COUNT-1:0];
reg [ADDRESS_WIDTH-1:0] rai_reg [READ_PORT_COUNT-1:0];
reg [READ_PORT_COUNT*DATA_WIDTH-1:0] qi;
reg [DATA_WIDTH-1:0] qt;
reg [DATA_WIDTH-1:0] di [WRITE_PORT_COUNT-1:0];
reg [DATA_WIDTH-1:0] dt;
reg [ADDRESS_WIDTH-1:0] wat;
reg [ADDRESS_WIDTH-1:0] wai [WRITE_PORT_COUNT-1:0];
// Split input data
always @ (d) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<DATA_WIDTH;j=j+1) begin
dt[j]=d[i*DATA_WIDTH+j];
end
di[i]=dt;
end
end
// Split write addresses
always @ (wa) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
wat[j]=wa[i*ADDRESS_WIDTH+j];
end
wai[i]=wat;
end
end
// Write memory
always @ (posedge clk) begin
for (j=0;j<WRITE_PORT_COUNT;j=j+1) begin
if (we[j]) begin
mem[wai[j]] <= di[j];
end
end
end
// Split read addresses
always @ (ra) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
rat[j]=ra[i*ADDRESS_WIDTH+j];
end
rai[i]=rat;
end
end
// guide read addresses using CE
always @ (posedge clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if ( ce[i] ) begin
rai_reg[i] <= rai[i];
end
end
end
// Memory read
genvar x;
generate
for (x = 0; x < READ_PORT_COUNT; x = x + 1) begin : gen_q
assign q[x*DATA_WIDTH+DATA_WIDTH-1:x*DATA_WIDTH] = (rai_reg[x]<WORD_COUNT)?
mem[rai_reg[x]] : {DATA_WIDTH{1'b0}};
end
endgenerate
endmodule
module Gaussianblur_d1 (
address0,
ce0,
q0,
we0,
d0,
address1,
ce1,
q1,
we1,
d1,
clk);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd4096;
parameter AddressWidth = 32'd12;
input[AddressWidth-1:0] address0;
input ce0;
output[DataWidth-1:0] q0;
input we0;
input[DataWidth-1:0] d0;
input[AddressWidth-1:0] address1;
input ce1;
output[DataWidth-1:0] q1;
input we1;
input[DataWidth-1:0] d1;
input clk;
reg[DataWidth-1:0] q0;
reg[DataWidth-1:0] q1;
wire[2 * DataWidth - 1:0] mem_q;
wire[DataWidth - 1:0] mem_q0;
wire[DataWidth - 1:0] mem_q1;
wire[2 - 1:0] mem_we;
wire[2 * DataWidth - 1:0] mem_d;
wire[2 * AddressWidth - 1:0] mem_wa;
wire[2 * AddressWidth - 1:0] mem_ra;
wire[2 - 1:0] mem_ce;
Gaussianblur_d1_core #(
.READ_PORT_COUNT( 2 ),
.WRITE_PORT_COUNT( 2 ),
.DATA_WIDTH( DataWidth ),
.ADDRESS_WIDTH( AddressWidth ),
.WORD_COUNT( AddressRange ))
core_inst (
.q( mem_q ),
.ra( mem_ra ),
.ce( mem_ce ),
.d( mem_d ),
.wa( mem_wa ),
.we( mem_we ),
.clk( clk ));
assign mem_q0 = mem_q[2 * DataWidth - 1 : 1 * DataWidth];
always @ (mem_q0) begin
q0 = mem_q0;
end
assign mem_q1 = mem_q[1 * DataWidth - 1 : 0 * DataWidth];
always @ (mem_q1) begin
q1 = mem_q1;
end
assign mem_ra = {address0, address1};
assign mem_ce = {ce0, ce1};
assign mem_we[1] = we0;
assign mem_we[0] = we1;
assign mem_d = {d0, d1};
assign mem_wa = {address0, address1};
endmodule
|
// ==============================================================
// File generated by AutoESL - High-Level Synthesis System (C, C++, SystemC)
// Version: 2011.1
// Copyright (C) 2011 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module Gaussianblur_grp_fu_220_ACMP_faddfsub_30(
clk,
reset,
ce,
din0,
din1,
opcode,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
input[2 - 1:0] opcode;
output[dout_WIDTH - 1:0] dout;
ACMP_faddfsub #(
.ID( ID ),
.NUM_STAGE( 5 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_faddfsub_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ),
.opcode( opcode ));
endmodule
|
// ==============================================================
// File generated by AutoESL - High-Level Synthesis System (C, C++, SystemC)
// Version: 2011.1
// Copyright (C) 2011 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module Gaussianblur_grp_fu_226_ACMP_fmul_31(
clk,
reset,
ce,
din0,
din1,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
output[dout_WIDTH - 1:0] dout;
ACMP_fmul #(
.ID( ID ),
.NUM_STAGE( 4 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_fmul_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ));
endmodule
|
// ==============================================================
// File generated by AutoESL - High-Level Synthesis System (C, C++, SystemC)
// Version: 2011.1
// Copyright (C) 2011 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module Gaussianblur_grp_fu_235_ACMP_fdiv_32(
clk,
reset,
ce,
din0,
din1,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
output[dout_WIDTH - 1:0] dout;
ACMP_fdiv #(
.ID( ID ),
.NUM_STAGE( 10 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_fdiv_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ));
endmodule
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// ==============================================================
// File generated by AutoESL - High-Level Synthesis System (C, C++, SystemC)
// Version: 2011.1
// Copyright (C) 2011 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module Gaussianblur_grp_fu_241_ACMP_fdiv_33(
clk,
reset,
ce,
din0,
din1,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
output[dout_WIDTH - 1:0] dout;
ACMP_fdiv #(
.ID( ID ),
.NUM_STAGE( 10 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_fdiv_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ));
endmodule
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// ==============================================================
// File generated by AutoESL - High-Level Synthesis System (C, C++, SystemC)
// Version: 2011.1
// Copyright (C) 2011 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module Gaussianblur_grp_fu_245_ACMP_fsqrt_34(
clk,
reset,
ce,
din0,
din1,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
output[dout_WIDTH - 1:0] dout;
ACMP_fsqrt #(
.ID( ID ),
.NUM_STAGE( 10 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_fsqrt_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ));
endmodule
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// ==============================================================
// RTL generated by AutoESL - High-Level Synthesis System (C, C++, SystemC)
// Version: 2011.1
// Copyright (C) 2011 Xilinx Inc. All rights reserved.
//
// ===========================================================
`timescale 1 ns / 1 ps
module step0 (
ap_clk,
ap_rst,
ap_start,
ap_done,
ap_idle,
tag,
counter,
a_address0,
a_ce0,
a_we0,
a_d0,
a_q0,
a_address1,
a_ce1,
a_we1,
a_d1,
a_q1,
b_address0,
b_ce0,
b_we0,
b_d0,
b_q0,
b_address1,
b_ce1,
b_we1,
b_d1,
b_q1,
BoundryScale,
nu
);
input ap_clk;
input ap_rst;
input ap_start;
output ap_done;
output ap_idle;
input [1:0] tag;
input [6:0] counter;
output [11:0] a_address0;
output a_ce0;
output a_we0;
output [31:0] a_d0;
input [31:0] a_q0;
output [11:0] a_address1;
output a_ce1;
output a_we1;
output [31:0] a_d1;
input [31:0] a_q1;
output [11:0] b_address0;
output b_ce0;
output b_we0;
output [31:0] b_d0;
input [31:0] b_q0;
output [11:0] b_address1;
output b_ce1;
output b_we1;
output [31:0] b_d1;
input [31:0] b_q1;
input [31:0] BoundryScale;
input [31:0] nu;
reg ap_done;
reg ap_idle;
reg[11:0] a_address0;
reg a_ce0;
reg a_we0;
reg[31:0] a_d0;
reg[11:0] a_address1;
reg a_ce1;
reg a_we1;
reg[31:0] a_d1;
reg[11:0] b_address0;
reg b_ce0;
reg b_we0;
reg[31:0] b_d0;
reg[11:0] b_address1;
reg b_ce1;
reg b_we1;
reg[31:0] b_d1;
reg [6:0] ap_CS_fsm;
reg [6:0] i_reg_1886;
reg [8:0] indvar_flatten_reg_1897;
reg [6:0] j_reg_1908;
reg [3:0] indvar3_reg_1919;
reg [6:0] i_1_reg_1930;
reg [6:0] i_2_reg_1941;
reg [8:0] indvar_flatten1_reg_1952;
reg [6:0] j_1_reg_1963;
reg [3:0] indvar6_reg_1974;
reg [6:0] i_3_reg_1985;
reg [6:0] j_2_reg_1996;
reg [8:0] indvar_flatten2_reg_2007;
reg [6:0] i_4_reg_2018;
reg [3:0] indvar9_reg_2029;
reg [6:0] j_3_reg_2040;
reg [6:0] j_4_reg_2051;
reg [8:0] indvar_flatten3_reg_2062;
reg [6:0] i_5_reg_2073;
reg [3:0] indvar4_reg_2084;
reg [6:0] j_5_reg_2095;
reg [6:0] indvar_flatten4_reg_2106;
reg [6:0] i_6_reg_2120;
reg [3:0] indvar_reg_2134;
reg [6:0] j_6_reg_2148;
reg [31:0] reg_2171;
reg ap_reg_ppiten_pp0_it1;
reg ap_reg_ppiten_pp0_it0;
reg ap_reg_ppiten_pp0_it2;
reg ap_reg_ppiten_pp0_it3;
reg ap_reg_ppiten_pp0_it4;
reg ap_reg_ppiten_pp0_it5;
reg ap_reg_ppiten_pp0_it6;
reg [0:0] exitcond1_reg_5171;
reg ap_reg_ppiten_pp1_it0;
reg ap_reg_ppiten_pp1_it1;
reg ap_reg_ppiten_pp1_it2;
reg [0:0] exitcond3_reg_5195;
reg ap_reg_ppiten_pp3_it0;
reg ap_reg_ppiten_pp3_it1;
reg ap_reg_ppiten_pp3_it2;
reg [0:0] exitcond6_reg_5446;
reg ap_reg_ppiten_pp4_it1;
reg ap_reg_ppiten_pp4_it0;
reg ap_reg_ppiten_pp4_it2;
reg ap_reg_ppiten_pp4_it3;
reg ap_reg_ppiten_pp4_it4;
reg ap_reg_ppiten_pp4_it5;
reg ap_reg_ppiten_pp4_it6;
reg [0:0] exitcond7_reg_5678;
reg ap_reg_ppiten_pp5_it0;
reg ap_reg_ppiten_pp5_it1;
reg ap_reg_ppiten_pp5_it2;
reg [0:0] exitcond9_reg_5697;
reg ap_reg_ppiten_pp7_it0;
reg ap_reg_ppiten_pp7_it1;
reg ap_reg_ppiten_pp7_it2;
reg [0:0] exitcond12_reg_5924;
wire [31:0] grp_fu_2167_p2;
reg [31:0] reg_2177;
reg [0:0] ap_reg_ppstg_exitcond1_reg_5171_pp0_it4;
reg ap_reg_ppiten_pp2_it5;
reg ap_reg_ppiten_pp2_it0;
reg ap_reg_ppiten_pp2_it1;
reg ap_reg_ppiten_pp2_it2;
reg ap_reg_ppiten_pp2_it3;
reg ap_reg_ppiten_pp2_it4;
reg ap_reg_ppiten_pp2_it6;
reg [0:0] exitcond4_reg_5427;
reg [0:0] ap_reg_ppstg_exitcond4_reg_5427_pp2_it4;
reg [0:0] ap_reg_ppstg_exitcond7_reg_5678_pp4_it4;
reg ap_reg_ppiten_pp6_it5;
reg ap_reg_ppiten_pp6_it0;
reg ap_reg_ppiten_pp6_it1;
reg ap_reg_ppiten_pp6_it2;
reg ap_reg_ppiten_pp6_it3;
reg ap_reg_ppiten_pp6_it4;
reg ap_reg_ppiten_pp6_it6;
reg [0:0] exitcond10_reg_5905;
reg [0:0] ap_reg_ppstg_exitcond10_reg_5905_pp6_it4;
reg [31:0] reg_2184;
reg [31:0] reg_2190;
reg [31:0] reg_2197;
reg [31:0] reg_2204;
reg [31:0] reg_2211;
reg [31:0] reg_2218;
reg [31:0] reg_2225;
reg [31:0] reg_2232;
reg [31:0] reg_2239;
reg [31:0] reg_2246;
reg [31:0] reg_2253;
reg [31:0] reg_2260;
reg [0:0] ap_reg_ppstg_exitcond6_reg_5446_pp3_it1;
reg [0:0] ap_reg_ppstg_exitcond12_reg_5924_pp7_it1;
reg [31:0] reg_2267;
reg [31:0] reg_2274;
reg [31:0] reg_2279;
reg ap_reg_ppiten_pp1_it3;
reg ap_reg_ppiten_pp3_it3;
reg ap_reg_ppiten_pp5_it3;
reg ap_reg_ppiten_pp7_it3;
reg [31:0] reg_2284;
reg [0:0] ap_reg_ppstg_exitcond3_reg_5195_pp1_it1;
reg [0:0] ap_reg_ppstg_exitcond9_reg_5697_pp5_it1;
reg [31:0] reg_2289;
wire [31:0] grp_fu_2163_p2;
reg [31:0] reg_2294;
reg [31:0] reg_2300;
reg [31:0] reg_2305;
reg [31:0] reg_2311;
reg [31:0] reg_2318;
reg [31:0] reg_2323;
reg [31:0] reg_2330;
reg [31:0] reg_2335;
reg [31:0] reg_2341;
reg [0:0] ap_reg_ppstg_exitcond3_reg_5195_pp1_it2;
reg [0:0] ap_reg_ppstg_exitcond6_reg_5446_pp3_it2;
reg [0:0] ap_reg_ppstg_exitcond9_reg_5697_pp5_it2;
reg [0:0] ap_reg_ppstg_exitcond12_reg_5924_pp7_it2;
reg [31:0] reg_2347;
wire [0:0] or_cond_fu_2365_p2;
wire [0:0] tmp_2_fu_2371_p2;
wire [0:0] exitcond1_fu_2377_p2;
reg [0:0] ap_reg_ppstg_exitcond1_reg_5171_pp0_it1;
reg [0:0] ap_reg_ppstg_exitcond1_reg_5171_pp0_it2;
reg [0:0] ap_reg_ppstg_exitcond1_reg_5171_pp0_it3;
reg [0:0] ap_reg_ppstg_exitcond1_reg_5171_pp0_it5;
reg [6:0] tmp_5_reg_5175;
wire [63:0] tmp_6_fu_2399_p1;
reg [63:0] tmp_6_reg_5180;
reg [63:0] ap_reg_ppstg_tmp_6_reg_5180_pp0_it1;
reg [63:0] ap_reg_ppstg_tmp_6_reg_5180_pp0_it2;
reg [63:0] ap_reg_ppstg_tmp_6_reg_5180_pp0_it3;
reg [63:0] ap_reg_ppstg_tmp_6_reg_5180_pp0_it4;
reg [63:0] ap_reg_ppstg_tmp_6_reg_5180_pp0_it5;
wire [0:0] exitcond3_fu_2404_p2;
reg [8:0] indvar_flatten_next_reg_5199;
wire [6:0] i_1_mid2_fu_2422_p3;
reg [6:0] i_1_mid2_reg_5204;
wire [6:0] j_mid2_fu_2436_p3;
reg [6:0] j_mid2_reg_5216;
reg [5:0] j_cast_reg_5221;
wire [13:0] tmp_6_trn_cast_fu_2452_p1;
reg [13:0] tmp_6_trn_cast_reg_5226;
wire [63:0] tmp_9_fu_2472_p1;
reg [63:0] tmp_9_reg_5237;
reg [63:0] ap_reg_ppstg_tmp_9_reg_5237_pp1_it1;
reg [6:0] a_addr100_reg_5247;
reg [3:0] indvar_next3_reg_5252;
wire [12:0] tmp_8_trn_cast_fu_2500_p1;
reg [12:0] tmp_8_trn_cast_reg_5257;
wire [63:0] tmp_15_fu_2560_p1;
reg [63:0] tmp_15_reg_5272;
reg [63:0] ap_reg_ppstg_tmp_15_reg_5272_pp1_it1;
wire [63:0] tmp_20_fu_2626_p1;
reg [63:0] tmp_20_reg_5287;
reg [63:0] ap_reg_ppstg_tmp_20_reg_5287_pp1_it1;
wire [6:0] b_addr4_fu_2645_p2;
reg [6:0] b_addr4_reg_5297;
reg [6:0] tmp_8_trn_cast4_reg_5302;
reg [6:0] tmp_8_trn_cast5_reg_5307;
reg [6:0] tmp_8_trn_cast6_reg_5312;
reg [6:0] tmp_8_trn_cast7_reg_5317;
reg [6:0] tmp_8_trn_cast8_reg_5322;
wire [63:0] tmp_28_fu_2740_p1;
reg [63:0] tmp_28_reg_5332;
reg [63:0] ap_reg_ppstg_tmp_28_reg_5332_pp1_it1;
wire [63:0] tmp_36_fu_2794_p1;
reg [63:0] tmp_36_reg_5347;
reg [63:0] ap_reg_ppstg_tmp_36_reg_5347_pp1_it1;
wire [6:0] b_addr8_fu_2803_p2;
reg [6:0] b_addr8_reg_5357;
wire [63:0] tmp_44_fu_2847_p1;
reg [63:0] tmp_44_reg_5367;
reg [63:0] ap_reg_ppstg_tmp_44_reg_5367_pp1_it1;
reg [63:0] ap_reg_ppstg_tmp_44_reg_5367_pp1_it2;
reg [13:0] a_addr23_reg_5382;
reg [13:0] a_addr25_reg_5392;
reg [6:0] tmp_43_reg_5402;
wire [63:0] tmp_47_fu_2980_p1;
reg [63:0] tmp_47_reg_5407;
reg [63:0] ap_reg_ppstg_tmp_47_reg_5407_pp1_it2;
wire [63:0] tmp_51_fu_2984_p1;
reg [63:0] tmp_51_reg_5417;
reg [63:0] ap_reg_ppstg_tmp_51_reg_5417_pp1_it2;
wire [0:0] exitcond4_fu_2988_p2;
reg [0:0] ap_reg_ppstg_exitcond4_reg_5427_pp2_it1;
reg [0:0] ap_reg_ppstg_exitcond4_reg_5427_pp2_it2;
reg [0:0] ap_reg_ppstg_exitcond4_reg_5427_pp2_it3;
reg [0:0] ap_reg_ppstg_exitcond4_reg_5427_pp2_it5;
reg [6:0] tmp_10_reg_5431;
wire [63:0] tmp_59_fu_3020_p1;
reg [63:0] tmp_59_reg_5436;
reg [63:0] ap_reg_ppstg_tmp_59_reg_5436_pp2_it1;
reg [63:0] ap_reg_ppstg_tmp_59_reg_5436_pp2_it2;
reg [63:0] ap_reg_ppstg_tmp_59_reg_5436_pp2_it3;
reg [63:0] ap_reg_ppstg_tmp_59_reg_5436_pp2_it4;
reg [63:0] ap_reg_ppstg_tmp_59_reg_5436_pp2_it5;
wire [0:0] exitcond6_fu_3025_p2;
reg [8:0] indvar_flatten_next1_reg_5450;
wire [6:0] i_3_mid2_fu_3043_p3;
reg [6:0] i_3_mid2_reg_5455;
wire [6:0] j_1_mid2_fu_3057_p3;
reg [6:0] j_1_mid2_reg_5467;
reg [5:0] j_1_cast_reg_5472;
reg [13:0] tmp_44_trn_cast_reg_5477;
wire [63:0] tmp_67_fu_3093_p1;
reg [63:0] tmp_67_reg_5488;
reg [63:0] ap_reg_ppstg_tmp_67_reg_5488_pp3_it1;
reg [6:0] b_addr53_reg_5498;
reg [3:0] indvar_next6_reg_5503;
wire [12:0] tmp_46_trn_cast_fu_3121_p1;
reg [12:0] tmp_46_trn_cast_reg_5508;
wire [63:0] tmp_75_fu_3181_p1;
reg [63:0] tmp_75_reg_5523;
reg [63:0] ap_reg_ppstg_tmp_75_reg_5523_pp3_it1;
wire [63:0] tmp_83_fu_3247_p1;
reg [63:0] tmp_83_reg_5538;
reg [63:0] ap_reg_ppstg_tmp_83_reg_5538_pp3_it1;
wire [6:0] a_addr112_fu_3266_p2;
reg [6:0] a_addr112_reg_5548;
reg [6:0] tmp_46_trn_cast4_reg_5553;
reg [6:0] tmp_46_trn_cast5_reg_5558;
reg [6:0] tmp_46_trn_cast6_reg_5563;
reg [6:0] tmp_46_trn_cast7_reg_5568;
reg [6:0] tmp_46_trn_cast8_reg_5573;
wire [63:0] tmp_86_fu_3361_p1;
reg [63:0] tmp_86_reg_5583;
reg [63:0] ap_reg_ppstg_tmp_86_reg_5583_pp3_it1;
wire [63:0] tmp_90_fu_3415_p1;
reg [63:0] tmp_90_reg_5598;
reg [63:0] ap_reg_ppstg_tmp_90_reg_5598_pp3_it1;
wire [6:0] a_addr116_fu_3424_p2;
reg [6:0] a_addr116_reg_5608;
wire [63:0] tmp_98_fu_3468_p1;
reg [63:0] tmp_98_reg_5618;
reg [63:0] ap_reg_ppstg_tmp_98_reg_5618_pp3_it1;
reg [63:0] ap_reg_ppstg_tmp_98_reg_5618_pp3_it2;
reg [13:0] b_addr23_reg_5633;
reg [13:0] b_addr25_reg_5643;
reg [6:0] tmp_82_reg_5653;
wire [63:0] tmp_106_fu_3601_p1;
reg [63:0] tmp_106_reg_5658;
reg [63:0] ap_reg_ppstg_tmp_106_reg_5658_pp3_it2;
wire [63:0] tmp_114_fu_3605_p1;
reg [63:0] tmp_114_reg_5668;
reg [63:0] ap_reg_ppstg_tmp_114_reg_5668_pp3_it2;
wire [0:0] exitcond7_fu_3609_p2;
reg [0:0] ap_reg_ppstg_exitcond7_reg_5678_pp4_it1;
reg [0:0] ap_reg_ppstg_exitcond7_reg_5678_pp4_it2;
reg [0:0] ap_reg_ppstg_exitcond7_reg_5678_pp4_it3;
reg [0:0] ap_reg_ppstg_exitcond7_reg_5678_pp4_it5;
reg [6:0] tmp_49_reg_5682;
wire [63:0] tmp_122_fu_3621_p1;
reg [63:0] tmp_122_reg_5687;
reg [63:0] ap_reg_ppstg_tmp_122_reg_5687_pp4_it1;
reg [63:0] ap_reg_ppstg_tmp_122_reg_5687_pp4_it2;
reg [63:0] ap_reg_ppstg_tmp_122_reg_5687_pp4_it3;
reg [63:0] ap_reg_ppstg_tmp_122_reg_5687_pp4_it4;
reg [63:0] ap_reg_ppstg_tmp_122_reg_5687_pp4_it5;
wire [0:0] exitcond9_fu_3626_p2;
reg [8:0] indvar_flatten_next2_reg_5701;
wire [6:0] j_3_mid2_fu_3644_p3;
reg [6:0] j_3_mid2_reg_5706;
wire [6:0] i_4_mid2_fu_3658_p3;
reg [6:0] i_4_mid2_reg_5719;
reg [5:0] i_4_cast_reg_5724;
wire [13:0] a_addr37_cast_fu_3684_p1;
reg [13:0] a_addr37_cast_reg_5729;
reg [13:0] ap_reg_ppstg_a_addr37_cast_reg_5729_pp5_it1;
wire [63:0] tmp_125_fu_3694_p1;
reg [63:0] tmp_125_reg_5740;
reg [63:0] ap_reg_ppstg_tmp_125_reg_5740_pp5_it1;
reg [3:0] indvar_next9_reg_5750;
wire [12:0] b_addr26_cast_fu_3731_p1;
reg [12:0] b_addr26_cast_reg_5755;
wire [63:0] tmp_130_fu_3764_p1;
reg [63:0] tmp_130_reg_5770;
reg [63:0] ap_reg_ppstg_tmp_130_reg_5770_pp5_it1;
wire [6:0] tmp_97_fu_3780_p2;
reg [6:0] tmp_97_reg_5785;
wire [63:0] tmp_138_fu_3794_p1;
reg [63:0] tmp_138_reg_5790;
reg [63:0] ap_reg_ppstg_tmp_138_reg_5790_pp5_it1;
wire [63:0] tmp_146_fu_3830_p1;
reg [63:0] tmp_146_reg_5805;
reg [63:0] ap_reg_ppstg_tmp_146_reg_5805_pp5_it1;
wire [6:0] tmp_105_fu_3845_p2;
reg [6:0] tmp_105_reg_5820;
wire [63:0] tmp_154_fu_3859_p1;
reg [63:0] tmp_154_reg_5825;
reg [63:0] ap_reg_ppstg_tmp_154_reg_5825_pp5_it1;
wire [63:0] tmp_160_fu_3895_p1;
reg [63:0] tmp_160_reg_5840;
reg [63:0] ap_reg_ppstg_tmp_160_reg_5840_pp5_it1;
reg [63:0] ap_reg_ppstg_tmp_160_reg_5840_pp5_it2;
wire [6:0] tmp_113_fu_3910_p2;
reg [6:0] tmp_113_reg_5855;
wire [6:0] tmp_117_fu_3929_p2;
reg [6:0] tmp_117_reg_5865;
reg [6:0] tmp_121_reg_5875;
wire [63:0] tmp_164_fu_3961_p1;
reg [63:0] tmp_164_reg_5880;
reg [63:0] ap_reg_ppstg_tmp_164_reg_5880_pp5_it2;
wire [13:0] a_addr50_fu_3969_p2;
reg [13:0] a_addr50_reg_5890;
wire [63:0] tmp_168_fu_3974_p1;
reg [63:0] tmp_168_reg_5895;
reg [63:0] ap_reg_ppstg_tmp_168_reg_5895_pp5_it2;
wire [0:0] exitcond10_fu_3978_p2;
reg [0:0] ap_reg_ppstg_exitcond10_reg_5905_pp6_it1;
reg [0:0] ap_reg_ppstg_exitcond10_reg_5905_pp6_it2;
reg [0:0] ap_reg_ppstg_exitcond10_reg_5905_pp6_it3;
reg [0:0] ap_reg_ppstg_exitcond10_reg_5905_pp6_it5;
reg [6:0] tmp_88_reg_5909;
wire [63:0] tmp_172_fu_4000_p1;
reg [63:0] tmp_172_reg_5914;
reg [63:0] ap_reg_ppstg_tmp_172_reg_5914_pp6_it1;
reg [63:0] ap_reg_ppstg_tmp_172_reg_5914_pp6_it2;
reg [63:0] ap_reg_ppstg_tmp_172_reg_5914_pp6_it3;
reg [63:0] ap_reg_ppstg_tmp_172_reg_5914_pp6_it4;
reg [63:0] ap_reg_ppstg_tmp_172_reg_5914_pp6_it5;
wire [0:0] exitcond12_fu_4005_p2;
reg [8:0] indvar_flatten_next3_reg_5928;
wire [6:0] j_5_mid2_fu_4023_p3;
reg [6:0] j_5_mid2_reg_5933;
wire [6:0] i_5_mid2_fu_4037_p3;
reg [6:0] i_5_mid2_reg_5946;
reg [5:0] i_5_cast_reg_5951;
wire [13:0] b_addr36_cast_fu_4063_p1;
reg [13:0] b_addr36_cast_reg_5956;
reg [13:0] ap_reg_ppstg_b_addr36_cast_reg_5956_pp7_it1;
wire [63:0] tmp_174_fu_4073_p1;
reg [63:0] tmp_174_reg_5967;
reg [63:0] ap_reg_ppstg_tmp_174_reg_5967_pp7_it1;
reg [3:0] indvar_next5_reg_5977;
wire [12:0] a_addr51_cast_fu_4110_p1;
reg [12:0] a_addr51_cast_reg_5982;
wire [63:0] tmp_178_fu_4143_p1;
reg [63:0] tmp_178_reg_5997;
reg [63:0] ap_reg_ppstg_tmp_178_reg_5997_pp7_it1;
wire [6:0] tmp_133_fu_4159_p2;
reg [6:0] tmp_133_reg_6012;
wire [63:0] tmp_182_fu_4173_p1;
reg [63:0] tmp_182_reg_6017;
reg [63:0] ap_reg_ppstg_tmp_182_reg_6017_pp7_it1;
wire [63:0] tmp_186_fu_4209_p1;
reg [63:0] tmp_186_reg_6032;
reg [63:0] ap_reg_ppstg_tmp_186_reg_6032_pp7_it1;
wire [6:0] tmp_141_fu_4224_p2;
reg [6:0] tmp_141_reg_6047;
wire [63:0] tmp_190_fu_4238_p1;
reg [63:0] tmp_190_reg_6052;
reg [63:0] ap_reg_ppstg_tmp_190_reg_6052_pp7_it1;
wire [63:0] tmp_192_fu_4274_p1;
reg [63:0] tmp_192_reg_6067;
reg [63:0] ap_reg_ppstg_tmp_192_reg_6067_pp7_it1;
reg [63:0] ap_reg_ppstg_tmp_192_reg_6067_pp7_it2;
wire [6:0] tmp_149_fu_4289_p2;
reg [6:0] tmp_149_reg_6082;
wire [6:0] tmp_153_fu_4308_p2;
reg [6:0] tmp_153_reg_6092;
reg [6:0] tmp_157_reg_6102;
wire [63:0] tmp_194_fu_4340_p1;
reg [63:0] tmp_194_reg_6107;
reg [63:0] ap_reg_ppstg_tmp_194_reg_6107_pp7_it2;
wire [13:0] b_addr44_fu_4348_p2;
reg [13:0] b_addr44_reg_6117;
wire [63:0] tmp_197_fu_4353_p1;
reg [63:0] tmp_197_reg_6122;
reg [63:0] ap_reg_ppstg_tmp_197_reg_6122_pp7_it2;
wire [0:0] exitcond_fu_4357_p2;
reg [0:0] exitcond_reg_6132;
reg ap_reg_ppiten_pp8_it0;
reg ap_reg_ppiten_pp8_it1;
reg [6:0] indvar_flatten_next4_reg_6136;
wire [6:0] j_6_mid2_fu_4375_p3;
reg [6:0] j_6_mid2_reg_6141;
wire [6:0] i_6_mid2_fu_4389_p3;
reg [6:0] i_6_mid2_reg_6153;
wire [13:0] a_addr63_cast_fu_4411_p1;
reg [13:0] a_addr63_cast_reg_6165;
wire [63:0] tmp_199_fu_4421_p1;
reg [63:0] tmp_199_reg_6176;
reg [3:0] indvar_next_reg_6186;
wire [13:0] tmp_176_trn_cast_fu_4445_p1;
reg [13:0] tmp_176_trn_cast_reg_6191;
wire [63:0] tmp_200_fu_4454_p1;
reg [63:0] tmp_200_reg_6202;
wire [13:0] tmp_178_trn_cast_fu_4464_p1;
reg [13:0] tmp_178_trn_cast_reg_6212;
wire [63:0] tmp_201_fu_4473_p1;
reg [63:0] tmp_201_reg_6223;
wire [13:0] tmp_180_trn_cast_fu_4483_p1;
reg [13:0] tmp_180_trn_cast_reg_6233;
wire [63:0] tmp_202_fu_4492_p1;
reg [63:0] tmp_202_reg_6244;
wire [13:0] tmp_182_trn_cast_fu_4502_p1;
reg [13:0] tmp_182_trn_cast_reg_6254;
wire [63:0] tmp_203_fu_4511_p1;
reg [63:0] tmp_203_reg_6265;
wire [13:0] tmp_184_trn_cast_fu_4521_p1;
reg [13:0] tmp_184_trn_cast_reg_6275;
wire [63:0] tmp_204_fu_4530_p1;
reg [63:0] tmp_204_reg_6286;
wire [13:0] tmp_186_trn_cast_fu_4540_p1;
reg [13:0] tmp_186_trn_cast_reg_6296;
wire [63:0] tmp_205_fu_4549_p1;
reg [63:0] tmp_205_reg_6307;
wire [13:0] tmp_188_trn_cast_fu_4564_p1;
reg [13:0] tmp_188_trn_cast_reg_6317;
wire [63:0] tmp_206_fu_4573_p1;
reg [63:0] tmp_206_reg_6328;
wire [13:0] a_addr77_cast_fu_4588_p1;
reg [13:0] a_addr77_cast_reg_6338;
wire [63:0] tmp_207_fu_4597_p1;
reg [63:0] tmp_207_reg_6348;
reg [6:0] tmp_189_reg_6358;
wire [63:0] tmp_208_fu_4611_p1;
reg [63:0] tmp_208_reg_6363;
wire [63:0] tmp_209_fu_4620_p1;
reg [63:0] tmp_209_reg_6373;
wire [63:0] tmp_210_fu_4629_p1;
reg [63:0] tmp_210_reg_6383;
wire [63:0] tmp_211_fu_4638_p1;
reg [63:0] tmp_211_reg_6393;
wire [63:0] tmp_212_fu_4647_p1;
reg [63:0] tmp_212_reg_6403;
wire [63:0] tmp_213_fu_4656_p1;
reg [63:0] tmp_213_reg_6413;
wire [13:0] a_addr87_cast_fu_4676_p1;
reg [13:0] a_addr87_cast_reg_6423;
wire [63:0] tmp_214_fu_4685_p1;
reg [63:0] tmp_214_reg_6432;
wire [63:0] tmp_215_fu_4695_p1;
reg [63:0] tmp_215_reg_6442;
wire [63:0] tmp_216_fu_4704_p1;
reg [63:0] tmp_216_reg_6452;
wire [63:0] tmp_217_fu_4713_p1;
reg [63:0] tmp_217_reg_6462;
wire [63:0] tmp_218_fu_4722_p1;
reg [63:0] tmp_218_reg_6472;
wire [63:0] tmp_219_fu_4731_p1;
reg [63:0] tmp_219_reg_6482;
wire [63:0] tmp_220_fu_4745_p1;
reg [63:0] tmp_220_reg_6492;
wire [13:0] a_addr98_cast_fu_4760_p1;
reg [13:0] a_addr98_cast_reg_6502;
wire [63:0] tmp_221_fu_4769_p1;
reg [63:0] tmp_221_reg_6512;
wire [63:0] tmp_222_fu_4778_p1;
reg [63:0] tmp_222_reg_6522;
wire [63:0] tmp_223_fu_4787_p1;
reg [63:0] tmp_223_reg_6532;
wire [63:0] tmp_224_fu_4796_p1;
reg [63:0] tmp_224_reg_6542;
wire [63:0] tmp_225_fu_4805_p1;
reg [63:0] tmp_225_reg_6552;
wire [63:0] tmp_226_fu_4814_p1;
reg [63:0] tmp_226_reg_6562;
wire [63:0] tmp_227_fu_4823_p1;
reg [63:0] tmp_227_reg_6572;
wire [13:0] a_addr99_cast_fu_4843_p1;
reg [13:0] a_addr99_cast_reg_6582;
wire [63:0] tmp_228_fu_4852_p1;
reg [63:0] tmp_228_reg_6591;
wire [63:0] tmp_229_fu_4862_p1;
reg [63:0] tmp_229_reg_6601;
wire [63:0] tmp_230_fu_4871_p1;
reg [63:0] tmp_230_reg_6611;
wire [63:0] tmp_231_fu_4880_p1;
reg [63:0] tmp_231_reg_6621;
wire [63:0] tmp_232_fu_4889_p1;
reg [63:0] tmp_232_reg_6631;
wire [63:0] tmp_233_fu_4898_p1;
reg [63:0] tmp_233_reg_6641;
wire [63:0] tmp_234_fu_4912_p1;
reg [63:0] tmp_234_reg_6651;
wire [13:0] a_addr72_cast_fu_4927_p1;
reg [13:0] a_addr72_cast_reg_6661;
wire [63:0] tmp_235_fu_4936_p1;
reg [63:0] tmp_235_reg_6671;
wire [63:0] tmp_236_fu_4945_p1;
reg [63:0] tmp_236_reg_6681;
wire [63:0] tmp_237_fu_4954_p1;
reg [63:0] tmp_237_reg_6691;
wire [63:0] tmp_238_fu_4963_p1;
reg [63:0] tmp_238_reg_6701;
wire [63:0] tmp_239_fu_4972_p1;
reg [63:0] tmp_239_reg_6711;
wire [63:0] tmp_240_fu_4981_p1;
reg [63:0] tmp_240_reg_6721;
wire [63:0] tmp_241_fu_4990_p1;
reg [63:0] tmp_241_reg_6731;
wire [13:0] a_addr45_cast_fu_5010_p1;
reg [13:0] a_addr45_cast_reg_6741;
wire [63:0] tmp_242_fu_5019_p1;
reg [63:0] tmp_242_reg_6750;
wire [63:0] tmp_243_fu_5029_p1;
reg [63:0] tmp_243_reg_6760;
wire [63:0] tmp_244_fu_5038_p1;
reg [63:0] tmp_244_reg_6770;
wire [63:0] tmp_245_fu_5047_p1;
reg [63:0] tmp_245_reg_6780;
wire [63:0] tmp_246_fu_5061_p1;
reg [63:0] tmp_246_reg_6790;
wire [63:0] tmp_247_fu_5070_p1;
reg [63:0] tmp_247_reg_6800;
wire [13:0] a_addr22_fu_5075_p2;
reg [13:0] a_addr22_reg_6810;
wire [13:0] a_addr19_fu_5093_p2;
reg [13:0] a_addr19_reg_6815;
reg [13:0] a_addr16_reg_6820;
wire [13:0] a_addr13_fu_5103_p2;
reg [13:0] a_addr13_reg_6825;
reg [13:0] a_addr10_reg_6830;
wire [13:0] a_addr7_fu_5113_p2;
reg [13:0] a_addr7_reg_6835;
reg [13:0] a_addr4_reg_6840;
wire [13:0] a_addr1_fu_5123_p2;
reg [13:0] a_addr1_reg_6845;
wire [63:0] tmp_248_fu_5128_p1;
reg [63:0] tmp_248_reg_6850;
wire [63:0] tmp_249_fu_5132_p1;
reg [63:0] tmp_249_reg_6860;
wire [63:0] tmp_250_fu_5136_p1;
reg [63:0] tmp_250_reg_6870;
wire [63:0] tmp_251_fu_5140_p1;
reg [63:0] tmp_251_reg_6880;
wire [63:0] tmp_252_fu_5144_p1;
reg [63:0] tmp_252_reg_6890;
wire [63:0] tmp_253_fu_5148_p1;
reg [63:0] tmp_253_reg_6900;
wire [63:0] tmp_254_fu_5152_p1;
reg [63:0] tmp_254_reg_6910;
wire [63:0] tmp_255_fu_5156_p1;
reg [63:0] tmp_255_reg_6920;
reg [6:0] i_phi_fu_1890_p4;
reg [8:0] indvar_flatten_phi_fu_1901_p4;
reg [6:0] j_phi_fu_1912_p4;
reg [3:0] indvar3_phi_fu_1923_p4;
reg [6:0] i_1_phi_fu_1934_p4;
reg [6:0] i_2_phi_fu_1945_p4;
reg [8:0] indvar_flatten1_phi_fu_1956_p4;
reg [6:0] j_1_phi_fu_1967_p4;
reg [3:0] indvar6_phi_fu_1978_p4;
reg [6:0] i_3_phi_fu_1989_p4;
reg [6:0] j_2_phi_fu_2000_p4;
reg [8:0] indvar_flatten2_phi_fu_2011_p4;
reg [6:0] i_4_phi_fu_2022_p4;
reg [3:0] indvar9_phi_fu_2033_p4;
reg [6:0] j_3_phi_fu_2044_p4;
reg [6:0] j_4_phi_fu_2055_p4;
reg [8:0] indvar_flatten3_phi_fu_2066_p4;
reg [6:0] i_5_phi_fu_2077_p4;
reg [3:0] indvar4_phi_fu_2088_p4;
reg [6:0] j_5_phi_fu_2099_p4;
reg [6:0] indvar_flatten4_phi_fu_2110_p6;
reg [6:0] i_6_phi_fu_2124_p6;
reg [3:0] indvar_phi_fu_2138_p6;
reg [6:0] j_6_phi_fu_2152_p6;
wire [63:0] tmp_11_fu_2531_p1;
wire [63:0] tmp_16_fu_2597_p1;
wire [63:0] tmp_24_fu_2711_p1;
wire [63:0] tmp_32_fu_2765_p1;
wire [63:0] tmp_40_fu_2818_p1;
wire [63:0] tmp_46_fu_2872_p1;
wire [63:0] tmp_50_fu_2921_p1;
wire [63:0] tmp_55_fu_2970_p1;
wire [63:0] tmp_71_fu_3152_p1;
wire [63:0] tmp_79_fu_3218_p1;
wire [63:0] tmp_85_fu_3332_p1;
wire [63:0] tmp_89_fu_3386_p1;
wire [63:0] tmp_94_fu_3439_p1;
wire [63:0] tmp_102_fu_3493_p1;
wire [63:0] tmp_110_fu_3542_p1;
wire [63:0] tmp_118_fu_3591_p1;
wire [63:0] tmp_126_fu_3741_p1;
wire [63:0] tmp_134_fu_3775_p1;
wire [63:0] tmp_142_fu_3807_p1;
wire [63:0] tmp_150_fu_3840_p1;
wire [63:0] tmp_158_fu_3872_p1;
wire [63:0] tmp_162_fu_3905_p1;
wire [63:0] tmp_166_fu_3924_p1;
wire [63:0] tmp_170_fu_3943_p1;
wire [63:0] tmp_176_fu_4120_p1;
wire [63:0] tmp_180_fu_4154_p1;
wire [63:0] tmp_184_fu_4186_p1;
wire [63:0] tmp_188_fu_4219_p1;
wire [63:0] tmp_191_fu_4251_p1;
wire [63:0] tmp_193_fu_4284_p1;
wire [63:0] tmp_196_fu_4303_p1;
wire [63:0] tmp_198_fu_4322_p1;
reg [31:0] grp_fu_2163_p0;
reg [31:0] grp_fu_2163_p1;
reg [31:0] grp_fu_2167_p0;
reg [31:0] grp_fu_2167_p1;
wire [0:0] tmp_fu_2353_p2;
wire [0:0] tmp_1_fu_2359_p2;
wire [12:0] tmp_3_trn_cast_fu_2389_p1;
wire [12:0] a_addr_fu_2393_p2;
wire [0:0] exitcond5_fu_2416_p2;
wire [6:0] tmp_11_dup_fu_2430_p2;
wire [12:0] tmp_12_trn_cast_fu_2448_p1;
wire [12:0] a_addr2_fu_2456_p2;
wire [13:0] a_addr2_cast_fu_2462_p1;
wire [13:0] a_addr3_fu_2466_p2;
wire [3:0] indvar3_op_fu_2481_p2;
wire [5:0] tmp_7_fu_2495_p2;
wire [6:0] tmp_8_trn_cast1_fu_2504_p4;
wire [6:0] b_addr_fu_2514_p2;
wire [12:0] b_addr1_fu_2519_p5;
wire [6:0] tmp_14_fu_2536_p2;
wire [12:0] tmp_16_trn_cast_fu_2541_p1;
wire [12:0] a_addr5_fu_2545_p2;
wire [13:0] a_addr5_cast_fu_2551_p1;
wire [13:0] a_addr6_fu_2555_p2;
wire [6:0] a_addr101_fu_2565_p1;
wire [6:0] tmp_8_trn_cast2_fu_2569_p4;
wire [6:0] b_addr2_fu_2579_p2;
wire [12:0] b_addr3_fu_2585_p5;
wire [6:0] tmp_19_fu_2602_p2;
wire [12:0] tmp_20_trn_cast_fu_2607_p1;
wire [12:0] a_addr8_fu_2611_p2;
wire [13:0] a_addr8_cast_fu_2617_p1;
wire [13:0] a_addr9_fu_2621_p2;
wire [6:0] a_addr102_fu_2631_p1;
wire [6:0] tmp_8_trn_cast3_fu_2635_p4;
wire [12:0] b_addr5_fu_2701_p5;
wire [6:0] tmp_23_fu_2716_p2;
wire [12:0] tmp_24_trn_cast_fu_2721_p1;
wire [12:0] a_addr11_fu_2725_p2;
wire [13:0] a_addr11_cast_fu_2731_p1;
wire [13:0] a_addr12_fu_2735_p2;
wire [6:0] a_addr103_fu_2745_p1;
wire [6:0] b_addr6_fu_2749_p2;
wire [12:0] b_addr7_fu_2754_p5;
wire [6:0] tmp_27_fu_2770_p2;
wire [12:0] tmp_28_trn_cast_fu_2775_p1;
wire [12:0] a_addr14_fu_2779_p2;
wire [13:0] a_addr14_cast_fu_2785_p1;
wire [13:0] a_addr15_fu_2789_p2;
wire [6:0] a_addr104_fu_2799_p1;
wire [12:0] b_addr9_fu_2808_p5;
wire [6:0] tmp_31_fu_2823_p2;
wire [12:0] tmp_32_trn_cast_fu_2828_p1;
wire [12:0] a_addr17_fu_2832_p2;
wire [13:0] a_addr17_cast_fu_2838_p1;
wire [13:0] a_addr20_fu_2842_p2;
wire [6:0] a_addr105_fu_2852_p1;
wire [6:0] b_addr45_fu_2856_p2;
wire [12:0] b_addr46_fu_2861_p5;
wire [6:0] tmp_35_fu_2877_p2;
wire [12:0] tmp_36_trn_cast_fu_2882_p1;
wire [12:0] a_addr21_fu_2886_p2;
wire [13:0] a_addr21_cast_fu_2892_p1;
wire [6:0] a_addr106_fu_2901_p1;
wire [6:0] b_addr47_fu_2905_p2;
wire [12:0] b_addr48_fu_2910_p5;
wire [6:0] tmp_39_fu_2926_p2;
wire [12:0] tmp_40_trn_cast_fu_2931_p1;
wire [12:0] a_addr24_fu_2935_p2;
wire [13:0] a_addr24_cast_fu_2941_p1;
wire [6:0] a_addr107_fu_2950_p1;
wire [6:0] b_addr49_fu_2954_p2;
wire [12:0] b_addr50_fu_2959_p5;
wire [12:0] tmp_9_trn_cast_fu_3000_p1;
wire [6:0] b_addr51_fu_3004_p1;
wire [12:0] b_addr52_fu_3008_p5;
wire [0:0] exitcond8_fu_3037_p2;
wire [6:0] tmp_50_dup_fu_3051_p2;
wire [12:0] tmp_51_trn_cast_fu_3069_p1;
wire [12:0] b_addr10_fu_3077_p2;
wire [13:0] b_addr10_cast_fu_3083_p1;
wire [13:0] b_addr11_fu_3087_p1;
wire [13:0] b_addr11_fu_3087_p2;
wire [3:0] indvar6_op_fu_3102_p2;
wire [5:0] tmp_45_fu_3116_p2;
wire [6:0] tmp_46_trn_cast1_fu_3125_p4;
wire [6:0] a_addr108_fu_3135_p2;
wire [12:0] a_addr109_fu_3140_p5;
wire [6:0] tmp_54_fu_3157_p2;
wire [12:0] tmp_55_trn_cast_fu_3162_p1;
wire [12:0] b_addr12_fu_3166_p2;
wire [13:0] b_addr12_cast_fu_3172_p1;
wire [13:0] b_addr13_fu_3176_p2;
wire [6:0] b_addr54_fu_3186_p1;
wire [6:0] tmp_46_trn_cast2_fu_3190_p4;
wire [6:0] a_addr110_fu_3200_p2;
wire [12:0] a_addr111_fu_3206_p5;
wire [6:0] tmp_58_fu_3223_p2;
wire [12:0] tmp_59_trn_cast_fu_3228_p1;
wire [12:0] b_addr14_fu_3232_p2;
wire [13:0] b_addr14_cast_fu_3238_p1;
wire [13:0] b_addr15_fu_3242_p2;
wire [6:0] b_addr55_fu_3252_p1;
wire [6:0] tmp_46_trn_cast3_fu_3256_p4;
wire [12:0] a_addr113_fu_3322_p5;
wire [6:0] tmp_62_fu_3337_p2;
wire [12:0] tmp_63_trn_cast_fu_3342_p1;
wire [12:0] b_addr16_fu_3346_p2;
wire [13:0] b_addr16_cast_fu_3352_p1;
wire [13:0] b_addr17_fu_3356_p2;
wire [6:0] b_addr56_fu_3366_p1;
wire [6:0] a_addr114_fu_3370_p2;
wire [12:0] a_addr115_fu_3375_p5;
wire [6:0] tmp_66_fu_3391_p2;
wire [12:0] tmp_67_trn_cast_fu_3396_p1;
wire [12:0] b_addr18_fu_3400_p2;
wire [13:0] b_addr18_cast_fu_3406_p1;
wire [13:0] b_addr19_fu_3410_p2;
wire [6:0] b_addr57_fu_3420_p1;
wire [12:0] a_addr117_fu_3429_p5;
wire [6:0] tmp_70_fu_3444_p2;
wire [12:0] tmp_71_trn_cast_fu_3449_p1;
wire [12:0] b_addr20_fu_3453_p2;
wire [13:0] b_addr20_cast_fu_3459_p1;
wire [13:0] b_addr21_fu_3463_p2;
wire [6:0] b_addr58_fu_3473_p1;
wire [6:0] a_addr118_fu_3477_p2;
wire [12:0] a_addr119_fu_3482_p5;
wire [6:0] tmp_74_fu_3498_p2;
wire [12:0] tmp_75_trn_cast_fu_3503_p1;
wire [12:0] b_addr22_fu_3507_p2;
wire [13:0] b_addr22_cast_fu_3513_p1;
wire [6:0] b_addr59_fu_3522_p1;
wire [6:0] a_addr120_fu_3526_p2;
wire [12:0] a_addr121_fu_3531_p5;
wire [6:0] tmp_78_fu_3547_p2;
wire [12:0] tmp_79_trn_cast_fu_3552_p1;
wire [12:0] b_addr24_fu_3556_p2;
wire [13:0] b_addr24_cast_fu_3562_p1;
wire [6:0] b_addr60_fu_3571_p1;
wire [6:0] a_addr122_fu_3575_p2;
wire [12:0] a_addr123_fu_3580_p5;
wire [0:0] exitcond11_fu_3638_p2;
wire [6:0] tmp_89_dup_fu_3652_p2;
wire [12:0] tmp_83_trn_cast_fu_3670_p1;
wire [12:0] a_addr37_fu_3678_p2;
wire [13:0] tmp_90_trn_cast_fu_3674_p1;
wire [13:0] a_addr39_fu_3688_p2;
wire [3:0] indvar9_op_fu_3699_p2;
wire [5:0] tmp_84_fu_3713_p2;
wire [11:0] tmp_85_trn_cast_fu_3721_p1;
wire [11:0] b_addr26_fu_3725_p2;
wire [12:0] tmp_90_trn_cast1_fu_3718_p1;
wire [12:0] b_addr27_fu_3735_p2;
wire [6:0] tmp_93_fu_3746_p2;
wire [13:0] tmp_94_trn_cast_fu_3755_p1;
wire [13:0] a_addr40_fu_3759_p2;
wire [12:0] tmp_94_trn_cast1_fu_3751_p1;
wire [12:0] b_addr28_fu_3769_p2;
wire [13:0] tmp_98_trn_cast_fu_3785_p1;
wire [13:0] a_addr41_fu_3789_p2;
wire [12:0] tmp_98_trn_cast1_fu_3799_p1;
wire [12:0] b_addr29_fu_3802_p2;
wire [6:0] tmp_101_fu_3812_p2;
wire [13:0] tmp_102_trn_cast_fu_3821_p1;
wire [13:0] a_addr43_fu_3825_p2;
wire [12:0] tmp_102_trn_cast1_fu_3817_p1;
wire [12:0] b_addr30_fu_3835_p2;
wire [13:0] tmp_106_trn_cast_fu_3850_p1;
wire [13:0] a_addr44_fu_3854_p2;
wire [12:0] tmp_106_trn_cast1_fu_3864_p1;
wire [12:0] b_addr31_fu_3867_p2;
wire [6:0] tmp_109_fu_3877_p2;
wire [13:0] tmp_110_trn_cast_fu_3886_p1;
wire [13:0] a_addr47_fu_3890_p2;
wire [12:0] tmp_110_trn_cast1_fu_3882_p1;
wire [12:0] b_addr32_fu_3900_p2;
wire [12:0] tmp_114_trn_cast1_fu_3915_p1;
wire [12:0] b_addr33_fu_3919_p2;
wire [12:0] tmp_118_trn_cast1_fu_3934_p1;
wire [12:0] b_addr34_fu_3938_p2;
wire [13:0] tmp_114_trn_cast_fu_3953_p1;
wire [13:0] a_addr48_fu_3956_p2;
wire [13:0] tmp_118_trn_cast_fu_3966_p1;
wire [12:0] tmp_86_trn_cast_fu_3990_p1;
wire [12:0] b_addr35_fu_3994_p2;
wire [0:0] exitcond13_fu_4017_p2;
wire [6:0] tmp_125_dup_fu_4031_p2;
wire [12:0] tmp_122_trn_cast_fu_4049_p1;
wire [12:0] b_addr36_fu_4057_p2;
wire [13:0] b_addr37_fu_4067_p0;
wire [13:0] tmp_126_trn_cast_fu_4053_p1;
wire [13:0] b_addr37_fu_4067_p2;
wire [3:0] indvar4_op_fu_4078_p2;
wire [5:0] tmp_123_fu_4092_p2;
wire [11:0] tmp_124_trn_cast_fu_4100_p1;
wire [11:0] a_addr51_fu_4104_p2;
wire [12:0] tmp_126_trn_cast1_fu_4097_p1;
wire [12:0] a_addr52_fu_4114_p2;
wire [6:0] tmp_129_fu_4125_p2;
wire [13:0] tmp_130_trn_cast_fu_4134_p1;
wire [13:0] b_addr38_fu_4138_p2;
wire [12:0] tmp_130_trn_cast1_fu_4130_p1;
wire [12:0] a_addr54_fu_4148_p2;
wire [13:0] tmp_134_trn_cast_fu_4164_p1;
wire [13:0] b_addr39_fu_4168_p2;
wire [12:0] tmp_134_trn_cast1_fu_4178_p1;
wire [12:0] a_addr55_fu_4181_p2;
wire [6:0] tmp_137_fu_4191_p2;
wire [13:0] tmp_138_trn_cast_fu_4200_p1;
wire [13:0] b_addr40_fu_4204_p2;
wire [12:0] tmp_138_trn_cast1_fu_4196_p1;
wire [12:0] a_addr56_fu_4214_p2;
wire [13:0] tmp_142_trn_cast_fu_4229_p1;
wire [13:0] b_addr41_fu_4233_p2;
wire [12:0] tmp_142_trn_cast1_fu_4243_p1;
wire [12:0] a_addr58_fu_4246_p2;
wire [6:0] tmp_145_fu_4256_p2;
wire [13:0] tmp_146_trn_cast_fu_4265_p1;
wire [13:0] b_addr42_fu_4269_p2;
wire [12:0] tmp_146_trn_cast1_fu_4261_p1;
wire [12:0] a_addr59_fu_4279_p2;
wire [12:0] tmp_150_trn_cast1_fu_4294_p1;
wire [12:0] a_addr60_fu_4298_p2;
wire [12:0] tmp_154_trn_cast1_fu_4313_p1;
wire [12:0] a_addr62_fu_4317_p2;
wire [13:0] tmp_150_trn_cast_fu_4332_p1;
wire [13:0] b_addr43_fu_4335_p2;
wire [13:0] tmp_154_trn_cast_fu_4345_p1;
wire [0:0] exitcond2_fu_4369_p2;
wire [6:0] tmp_173_dup_fu_4383_p2;
wire [12:0] tmp_158_trn_cast_fu_4397_p1;
wire [12:0] a_addr27_fu_4405_p2;
wire [13:0] tmp_174_trn_cast_fu_4401_p1;
wire [13:0] a_addr28_fu_4415_p2;
wire [3:0] indvar_op_fu_4426_p2;
wire [6:0] tmp_175_fu_4440_p2;
wire [13:0] a_addr29_fu_4449_p2;
wire [6:0] tmp_177_fu_4459_p2;
wire [13:0] a_addr31_fu_4468_p2;
wire [6:0] tmp_179_fu_4478_p2;
wire [13:0] a_addr32_fu_4487_p2;
wire [6:0] tmp_181_fu_4497_p2;
wire [13:0] a_addr33_fu_4506_p2;
wire [6:0] tmp_183_fu_4516_p2;
wire [13:0] a_addr35_fu_4525_p2;
wire [6:0] tmp_185_fu_4535_p2;
wire [13:0] a_addr36_fu_4544_p2;
wire [6:0] tmp_187_fu_4559_p2;
wire [13:0] a_addr63_fu_4568_p2;
wire [6:0] tmp_159_fu_4554_p2;
wire [12:0] tmp_160_trn_cast_fu_4578_p1;
wire [12:0] a_addr64_fu_4582_p2;
wire [13:0] a_addr66_fu_4592_p2;
wire [13:0] a_addr67_fu_4607_p2;
wire [13:0] a_addr68_fu_4616_p2;
wire [13:0] a_addr70_fu_4625_p2;
wire [13:0] a_addr71_fu_4634_p2;
wire [13:0] a_addr74_fu_4643_p2;
wire [13:0] a_addr75_fu_4652_p2;
wire [6:0] tmp_161_fu_4661_p2;
wire [12:0] tmp_162_trn_cast_fu_4666_p1;
wire [12:0] a_addr77_fu_4670_p2;
wire [13:0] a_addr78_fu_4680_p2;
wire [13:0] a_addr79_fu_4690_p2;
wire [13:0] a_addr81_fu_4700_p2;
wire [13:0] a_addr82_fu_4709_p2;
wire [13:0] a_addr83_fu_4718_p2;
wire [13:0] a_addr85_fu_4727_p2;
wire [13:0] a_addr86_fu_4741_p2;
wire [6:0] tmp_163_fu_4736_p2;
wire [12:0] tmp_164_trn_cast_fu_4750_p1;
wire [12:0] a_addr87_fu_4754_p2;
wire [13:0] a_addr89_fu_4764_p2;
wire [13:0] a_addr90_fu_4774_p2;
wire [13:0] a_addr91_fu_4783_p2;
wire [13:0] a_addr93_fu_4792_p2;
wire [13:0] a_addr94_fu_4801_p2;
wire [13:0] a_addr95_fu_4810_p2;
wire [13:0] a_addr97_fu_4819_p2;
wire [6:0] tmp_165_fu_4828_p2;
wire [12:0] tmp_166_trn_cast_fu_4833_p1;
wire [12:0] a_addr98_fu_4837_p2;
wire [13:0] a_addr99_fu_4847_p2;
wire [13:0] a_addr96_fu_4857_p2;
wire [13:0] a_addr92_fu_4867_p2;
wire [13:0] a_addr88_fu_4876_p2;
wire [13:0] a_addr84_fu_4885_p2;
wire [13:0] a_addr80_fu_4894_p2;
wire [13:0] a_addr76_fu_4908_p2;
wire [6:0] tmp_167_fu_4903_p2;
wire [12:0] tmp_168_trn_cast_fu_4917_p1;
wire [12:0] a_addr72_fu_4921_p2;
wire [13:0] a_addr73_fu_4931_p2;
wire [13:0] a_addr69_fu_4941_p2;
wire [13:0] a_addr65_fu_4950_p2;
wire [13:0] a_addr61_fu_4959_p2;
wire [13:0] a_addr57_fu_4968_p2;
wire [13:0] a_addr53_fu_4977_p2;
wire [13:0] a_addr49_fu_4986_p2;
wire [6:0] tmp_169_fu_4995_p2;
wire [12:0] tmp_170_trn_cast_fu_5000_p1;
wire [12:0] a_addr45_fu_5004_p2;
wire [13:0] a_addr46_fu_5014_p2;
wire [13:0] a_addr42_fu_5024_p2;
wire [13:0] a_addr38_fu_5034_p2;
wire [13:0] a_addr34_fu_5043_p2;
wire [13:0] a_addr30_fu_5057_p2;
wire [13:0] a_addr26_fu_5066_p2;
wire [6:0] tmp_171_fu_5052_p2;
wire [12:0] tmp_172_trn_cast_fu_5079_p1;
wire [12:0] a_addr18_fu_5083_p2;
wire [13:0] a_addr18_cast_fu_5089_p1;
wire grp_fu_2163_ce;
wire grp_fu_2167_ce;
reg [6:0] ap_NS_fsm;
parameter ap_const_logic_1 = 1'b1;
parameter ap_const_logic_0 = 1'b0;
parameter ap_ST_st0_fsm_0 = 7'b0000000;
parameter ap_ST_st1_fsm_1 = 7'b0000001;
parameter ap_ST_pp0_stg0_fsm_2 = 7'b0000010;
parameter ap_ST_st9_fsm_3 = 7'b0000011;
parameter ap_ST_pp1_stg0_fsm_4 = 7'b0000100;
parameter ap_ST_pp1_stg1_fsm_5 = 7'b0000101;
parameter ap_ST_pp1_stg2_fsm_6 = 7'b0000110;
parameter ap_ST_pp1_stg3_fsm_7 = 7'b0000111;
parameter ap_ST_pp1_stg4_fsm_8 = 7'b0001000;
parameter ap_ST_pp1_stg5_fsm_9 = 7'b0001001;
parameter ap_ST_pp1_stg6_fsm_10 = 7'b0001010;
parameter ap_ST_pp1_stg7_fsm_11 = 7'b0001011;
parameter ap_ST_pp2_stg0_fsm_12 = 7'b0001100;
parameter ap_ST_pp3_stg0_fsm_13 = 7'b0001101;
parameter ap_ST_pp3_stg1_fsm_14 = 7'b0001110;
parameter ap_ST_pp3_stg2_fsm_15 = 7'b0001111;
parameter ap_ST_pp3_stg3_fsm_16 = 7'b0010000;
parameter ap_ST_pp3_stg4_fsm_17 = 7'b0010001;
parameter ap_ST_pp3_stg5_fsm_18 = 7'b0010010;
parameter ap_ST_pp3_stg6_fsm_19 = 7'b0010011;
parameter ap_ST_pp3_stg7_fsm_20 = 7'b0010100;
parameter ap_ST_pp4_stg0_fsm_21 = 7'b0010101;
parameter ap_ST_pp5_stg0_fsm_22 = 7'b0010110;
parameter ap_ST_pp5_stg1_fsm_23 = 7'b0010111;
parameter ap_ST_pp5_stg2_fsm_24 = 7'b0011000;
parameter ap_ST_pp5_stg3_fsm_25 = 7'b0011001;
parameter ap_ST_pp5_stg4_fsm_26 = 7'b0011010;
parameter ap_ST_pp5_stg5_fsm_27 = 7'b0011011;
parameter ap_ST_pp5_stg6_fsm_28 = 7'b0011100;
parameter ap_ST_pp5_stg7_fsm_29 = 7'b0011101;
parameter ap_ST_pp6_stg0_fsm_30 = 7'b0011110;
parameter ap_ST_pp7_stg0_fsm_31 = 7'b0011111;
parameter ap_ST_pp7_stg1_fsm_32 = 7'b0100000;
parameter ap_ST_pp7_stg2_fsm_33 = 7'b0100001;
parameter ap_ST_pp7_stg3_fsm_34 = 7'b0100010;
parameter ap_ST_pp7_stg4_fsm_35 = 7'b0100011;
parameter ap_ST_pp7_stg5_fsm_36 = 7'b0100100;
parameter ap_ST_pp7_stg6_fsm_37 = 7'b0100101;
parameter ap_ST_pp7_stg7_fsm_38 = 7'b0100110;
parameter ap_ST_st131_fsm_39 = 7'b0100111;
parameter ap_ST_pp8_stg0_fsm_40 = 7'b0101000;
parameter ap_ST_pp8_stg1_fsm_41 = 7'b0101001;
parameter ap_ST_pp8_stg2_fsm_42 = 7'b0101010;
parameter ap_ST_pp8_stg3_fsm_43 = 7'b0101011;
parameter ap_ST_pp8_stg4_fsm_44 = 7'b0101100;
parameter ap_ST_pp8_stg5_fsm_45 = 7'b0101101;
parameter ap_ST_pp8_stg6_fsm_46 = 7'b0101110;
parameter ap_ST_pp8_stg7_fsm_47 = 7'b0101111;
parameter ap_ST_pp8_stg8_fsm_48 = 7'b0110000;
parameter ap_ST_pp8_stg9_fsm_49 = 7'b0110001;
parameter ap_ST_pp8_stg10_fsm_50 = 7'b0110010;
parameter ap_ST_pp8_stg11_fsm_51 = 7'b0110011;
parameter ap_ST_pp8_stg12_fsm_52 = 7'b0110100;
parameter ap_ST_pp8_stg13_fsm_53 = 7'b0110101;
parameter ap_ST_pp8_stg14_fsm_54 = 7'b0110110;
parameter ap_ST_pp8_stg15_fsm_55 = 7'b0110111;
parameter ap_ST_pp8_stg16_fsm_56 = 7'b0111000;
parameter ap_ST_pp8_stg17_fsm_57 = 7'b0111001;
parameter ap_ST_pp8_stg18_fsm_58 = 7'b0111010;
parameter ap_ST_pp8_stg19_fsm_59 = 7'b0111011;
parameter ap_ST_pp8_stg20_fsm_60 = 7'b0111100;
parameter ap_ST_pp8_stg21_fsm_61 = 7'b0111101;
parameter ap_ST_pp8_stg22_fsm_62 = 7'b0111110;
parameter ap_ST_pp8_stg23_fsm_63 = 7'b0111111;
parameter ap_ST_pp8_stg24_fsm_64 = 7'b1000000;
parameter ap_ST_pp8_stg25_fsm_65 = 7'b1000001;
parameter ap_ST_pp8_stg26_fsm_66 = 7'b1000010;
parameter ap_ST_pp8_stg27_fsm_67 = 7'b1000011;
parameter ap_ST_pp8_stg28_fsm_68 = 7'b1000100;
parameter ap_ST_st162_fsm_69 = 7'b1000101;
parameter ap_const_lv1_0 = 1'b0;
parameter ap_const_lv7_0 = 7'b0000000;
parameter ap_const_lv9_0 = 9'b000000000;
parameter ap_const_lv7_1 = 7'b0000001;
parameter ap_const_lv4_0 = 4'b0000;
parameter ap_const_lv7_3E = 7'b0111110;
parameter ap_const_lv7_41 = 7'b1000001;
parameter ap_const_lv2_0 = 2'b00;
parameter ap_const_lv7_40 = 7'b1000000;
parameter ap_const_lv13_6 = 13'b0000000000110;
parameter ap_const_lv9_1F8 = 9'b111111000;
parameter ap_const_lv9_1 = 9'b000000001;
parameter ap_const_lv4_8 = 4'b1000;
parameter ap_const_lv4_1 = 4'b0001;
parameter ap_const_lv6_3F = 6'b111111;
parameter ap_const_lv32_6 = 32'b00000000000000000000000000000110;
parameter ap_const_lv32_C = 32'b00000000000000000000000000001100;
parameter ap_const_lv7_2 = 7'b0000010;
parameter ap_const_lv7_3 = 7'b0000011;
parameter ap_const_lv7_4 = 7'b0000100;
parameter ap_const_lv7_5 = 7'b0000101;
parameter ap_const_lv7_6 = 7'b0000110;
parameter ap_const_lv7_7 = 7'b0000111;
parameter ap_const_lv7_8 = 7'b0001000;
parameter ap_const_lv13_3F = 13'b0000000111111;
parameter ap_const_lv7_7F = 7'b1111111;
parameter ap_const_lv6_1 = 6'b000001;
parameter ap_const_lv12_6 = 12'b000000000110;
parameter ap_const_lv13_FC0 = 13'b0111111000000;
parameter ap_true = 1'b1;
step0_grp_fu_2163_ACMP_fadd_5 #(
.ID( 5 ),
.NUM_STAGE( 5 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
step0_grp_fu_2163_ACMP_fadd_5_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_2163_p0 ),
.din1( grp_fu_2163_p1 ),
.ce( grp_fu_2163_ce ),
.dout( grp_fu_2163_p2 )
);
step0_grp_fu_2167_ACMP_fmul_6 #(
.ID( 6 ),
.NUM_STAGE( 4 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
step0_grp_fu_2167_ACMP_fmul_6_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_2167_p0 ),
.din1( grp_fu_2167_p1 ),
.ce( grp_fu_2167_ce ),
.dout( grp_fu_2167_p2 )
);
/// ap_CS_fsm assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_CS_fsm
if (ap_rst == 1'b1) begin
ap_CS_fsm <= ap_ST_st0_fsm_0;
end else begin
ap_CS_fsm <= ap_NS_fsm;
end
end
/// ap_reg_ppiten_pp0_it0 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it0
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it0 <= ap_const_logic_0;
end else begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond1_fu_2377_p2))) begin
ap_reg_ppiten_pp0_it0 <= ap_const_logic_0;
end else if (((ap_ST_st1_fsm_1 == ap_CS_fsm) & ~(ap_const_lv1_0 == or_cond_fu_2365_p2) & ~(ap_const_lv1_0 == tmp_2_fu_2371_p2))) begin
ap_reg_ppiten_pp0_it0 <= ap_const_logic_1;
end
end
end
/// ap_reg_ppiten_pp0_it1 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it1
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it1 <= ap_const_logic_0;
end else begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond1_fu_2377_p2))) begin
ap_reg_ppiten_pp0_it1 <= ap_const_logic_1;
end else if ((((ap_ST_st1_fsm_1 == ap_CS_fsm) & ~(ap_const_lv1_0 == or_cond_fu_2365_p2) & ~(ap_const_lv1_0 == tmp_2_fu_2371_p2)) | ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond1_fu_2377_p2)))) begin
ap_reg_ppiten_pp0_it1 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp0_it2 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it2
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it2 <= ap_const_logic_0;
end else begin
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it2 <= ap_reg_ppiten_pp0_it1;
end else if (((ap_ST_st1_fsm_1 == ap_CS_fsm) & ~(ap_const_lv1_0 == or_cond_fu_2365_p2) & ~(ap_const_lv1_0 == tmp_2_fu_2371_p2))) begin
ap_reg_ppiten_pp0_it2 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp0_it3 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it3
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it3 <= ap_const_logic_0;
end else begin
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it3 <= ap_reg_ppiten_pp0_it2;
end else if (((ap_ST_st1_fsm_1 == ap_CS_fsm) & ~(ap_const_lv1_0 == or_cond_fu_2365_p2) & ~(ap_const_lv1_0 == tmp_2_fu_2371_p2))) begin
ap_reg_ppiten_pp0_it3 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp0_it4 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it4
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it4 <= ap_const_logic_0;
end else begin
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it4 <= ap_reg_ppiten_pp0_it3;
end else if (((ap_ST_st1_fsm_1 == ap_CS_fsm) & ~(ap_const_lv1_0 == or_cond_fu_2365_p2) & ~(ap_const_lv1_0 == tmp_2_fu_2371_p2))) begin
ap_reg_ppiten_pp0_it4 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp0_it5 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it5
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it5 <= ap_const_logic_0;
end else begin
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it5 <= ap_reg_ppiten_pp0_it4;
end else if (((ap_ST_st1_fsm_1 == ap_CS_fsm) & ~(ap_const_lv1_0 == or_cond_fu_2365_p2) & ~(ap_const_lv1_0 == tmp_2_fu_2371_p2))) begin
ap_reg_ppiten_pp0_it5 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp0_it6 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it6
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it6 <= ap_const_logic_0;
end else begin
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it6 <= ap_reg_ppiten_pp0_it5;
end else if (((ap_ST_st1_fsm_1 == ap_CS_fsm) & ~(ap_const_lv1_0 == or_cond_fu_2365_p2) & ~(ap_const_lv1_0 == tmp_2_fu_2371_p2))) begin
ap_reg_ppiten_pp0_it6 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp1_it0 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp1_it0
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp1_it0 <= ap_const_logic_0;
end else begin
if (((ap_ST_pp1_stg0_fsm_4 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond3_fu_2404_p2))) begin
ap_reg_ppiten_pp1_it0 <= ap_const_logic_0;
end else if ((ap_ST_st9_fsm_3 == ap_CS_fsm)) begin
ap_reg_ppiten_pp1_it0 <= ap_const_logic_1;
end
end
end
/// ap_reg_ppiten_pp1_it1 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp1_it1
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp1_it1 <= ap_const_logic_0;
end else begin
if (((ap_const_lv1_0 == exitcond3_reg_5195) & (ap_ST_pp1_stg7_fsm_11 == ap_CS_fsm))) begin
ap_reg_ppiten_pp1_it1 <= ap_const_logic_1;
end else if (((ap_ST_st9_fsm_3 == ap_CS_fsm) | ((ap_ST_pp1_stg7_fsm_11 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond3_reg_5195)))) begin
ap_reg_ppiten_pp1_it1 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp1_it2 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp1_it2
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp1_it2 <= ap_const_logic_0;
end else begin
if ((ap_ST_pp1_stg7_fsm_11 == ap_CS_fsm)) begin
ap_reg_ppiten_pp1_it2 <= ap_reg_ppiten_pp1_it1;
end else if ((ap_ST_st9_fsm_3 == ap_CS_fsm)) begin
ap_reg_ppiten_pp1_it2 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp1_it3 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp1_it3
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp1_it3 <= ap_const_logic_0;
end else begin
if ((ap_ST_pp1_stg7_fsm_11 == ap_CS_fsm)) begin
ap_reg_ppiten_pp1_it3 <= ap_reg_ppiten_pp1_it2;
end else if ((ap_ST_st9_fsm_3 == ap_CS_fsm)) begin
ap_reg_ppiten_pp1_it3 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp2_it0 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp2_it0
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp2_it0 <= ap_const_logic_0;
end else begin
if (((ap_ST_pp2_stg0_fsm_12 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond4_fu_2988_p2))) begin
ap_reg_ppiten_pp2_it0 <= ap_const_logic_0;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_ST_pp1_stg0_fsm_4 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond3_fu_2404_p2))) begin
ap_reg_ppiten_pp2_it0 <= ap_const_logic_1;
end
end
end
/// ap_reg_ppiten_pp2_it1 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp2_it1
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp2_it1 <= ap_const_logic_0;
end else begin
if (((ap_ST_pp2_stg0_fsm_12 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond4_fu_2988_p2))) begin
ap_reg_ppiten_pp2_it1 <= ap_const_logic_1;
end else if ((((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_ST_pp1_stg0_fsm_4 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond3_fu_2404_p2)) | ((ap_ST_pp2_stg0_fsm_12 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond4_fu_2988_p2)))) begin
ap_reg_ppiten_pp2_it1 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp2_it2 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp2_it2
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp2_it2 <= ap_const_logic_0;
end else begin
if ((ap_ST_pp2_stg0_fsm_12 == ap_CS_fsm)) begin
ap_reg_ppiten_pp2_it2 <= ap_reg_ppiten_pp2_it1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_ST_pp1_stg0_fsm_4 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond3_fu_2404_p2))) begin
ap_reg_ppiten_pp2_it2 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp2_it3 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp2_it3
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp2_it3 <= ap_const_logic_0;
end else begin
if ((ap_ST_pp2_stg0_fsm_12 == ap_CS_fsm)) begin
ap_reg_ppiten_pp2_it3 <= ap_reg_ppiten_pp2_it2;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_ST_pp1_stg0_fsm_4 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond3_fu_2404_p2))) begin
ap_reg_ppiten_pp2_it3 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp2_it4 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp2_it4
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp2_it4 <= ap_const_logic_0;
end else begin
if ((ap_ST_pp2_stg0_fsm_12 == ap_CS_fsm)) begin
ap_reg_ppiten_pp2_it4 <= ap_reg_ppiten_pp2_it3;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_ST_pp1_stg0_fsm_4 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond3_fu_2404_p2))) begin
ap_reg_ppiten_pp2_it4 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp2_it5 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp2_it5
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp2_it5 <= ap_const_logic_0;
end else begin
if ((ap_ST_pp2_stg0_fsm_12 == ap_CS_fsm)) begin
ap_reg_ppiten_pp2_it5 <= ap_reg_ppiten_pp2_it4;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_ST_pp1_stg0_fsm_4 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond3_fu_2404_p2))) begin
ap_reg_ppiten_pp2_it5 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp2_it6 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp2_it6
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp2_it6 <= ap_const_logic_0;
end else begin
if ((ap_ST_pp2_stg0_fsm_12 == ap_CS_fsm)) begin
ap_reg_ppiten_pp2_it6 <= ap_reg_ppiten_pp2_it5;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_ST_pp1_stg0_fsm_4 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond3_fu_2404_p2))) begin
ap_reg_ppiten_pp2_it6 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp3_it0 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp3_it0
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp3_it0 <= ap_const_logic_0;
end else begin
if (((ap_ST_pp3_stg0_fsm_13 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond6_fu_3025_p2))) begin
ap_reg_ppiten_pp3_it0 <= ap_const_logic_0;
end else if (((ap_ST_pp2_stg0_fsm_12 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp2_it0) & ~(ap_const_lv1_0 == exitcond4_fu_2988_p2))) begin
ap_reg_ppiten_pp3_it0 <= ap_const_logic_1;
end
end
end
/// ap_reg_ppiten_pp3_it1 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp3_it1
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp3_it1 <= ap_const_logic_0;
end else begin
if (((ap_const_lv1_0 == exitcond6_reg_5446) & (ap_ST_pp3_stg7_fsm_20 == ap_CS_fsm))) begin
ap_reg_ppiten_pp3_it1 <= ap_const_logic_1;
end else if ((((ap_ST_pp2_stg0_fsm_12 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp2_it0) & ~(ap_const_lv1_0 == exitcond4_fu_2988_p2)) | ((ap_ST_pp3_stg7_fsm_20 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond6_reg_5446)))) begin
ap_reg_ppiten_pp3_it1 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp3_it2 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp3_it2
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp3_it2 <= ap_const_logic_0;
end else begin
if ((ap_ST_pp3_stg7_fsm_20 == ap_CS_fsm)) begin
ap_reg_ppiten_pp3_it2 <= ap_reg_ppiten_pp3_it1;
end else if (((ap_ST_pp2_stg0_fsm_12 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp2_it0) & ~(ap_const_lv1_0 == exitcond4_fu_2988_p2))) begin
ap_reg_ppiten_pp3_it2 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp3_it3 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp3_it3
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp3_it3 <= ap_const_logic_0;
end else begin
if ((ap_ST_pp3_stg7_fsm_20 == ap_CS_fsm)) begin
ap_reg_ppiten_pp3_it3 <= ap_reg_ppiten_pp3_it2;
end else if (((ap_ST_pp2_stg0_fsm_12 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp2_it0) & ~(ap_const_lv1_0 == exitcond4_fu_2988_p2))) begin
ap_reg_ppiten_pp3_it3 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp4_it0 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp4_it0
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp4_it0 <= ap_const_logic_0;
end else begin
if (((ap_ST_pp4_stg0_fsm_21 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond7_fu_3609_p2))) begin
ap_reg_ppiten_pp4_it0 <= ap_const_logic_0;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp3_it0) & (ap_ST_pp3_stg0_fsm_13 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond6_fu_3025_p2))) begin
ap_reg_ppiten_pp4_it0 <= ap_const_logic_1;
end
end
end
/// ap_reg_ppiten_pp4_it1 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp4_it1
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp4_it1 <= ap_const_logic_0;
end else begin
if (((ap_ST_pp4_stg0_fsm_21 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond7_fu_3609_p2))) begin
ap_reg_ppiten_pp4_it1 <= ap_const_logic_1;
end else if ((((ap_const_logic_1 == ap_reg_ppiten_pp3_it0) & (ap_ST_pp3_stg0_fsm_13 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond6_fu_3025_p2)) | ((ap_ST_pp4_stg0_fsm_21 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond7_fu_3609_p2)))) begin
ap_reg_ppiten_pp4_it1 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp4_it2 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp4_it2
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp4_it2 <= ap_const_logic_0;
end else begin
if ((ap_ST_pp4_stg0_fsm_21 == ap_CS_fsm)) begin
ap_reg_ppiten_pp4_it2 <= ap_reg_ppiten_pp4_it1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp3_it0) & (ap_ST_pp3_stg0_fsm_13 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond6_fu_3025_p2))) begin
ap_reg_ppiten_pp4_it2 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp4_it3 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp4_it3
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp4_it3 <= ap_const_logic_0;
end else begin
if ((ap_ST_pp4_stg0_fsm_21 == ap_CS_fsm)) begin
ap_reg_ppiten_pp4_it3 <= ap_reg_ppiten_pp4_it2;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp3_it0) & (ap_ST_pp3_stg0_fsm_13 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond6_fu_3025_p2))) begin
ap_reg_ppiten_pp4_it3 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp4_it4 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp4_it4
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp4_it4 <= ap_const_logic_0;
end else begin
if ((ap_ST_pp4_stg0_fsm_21 == ap_CS_fsm)) begin
ap_reg_ppiten_pp4_it4 <= ap_reg_ppiten_pp4_it3;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp3_it0) & (ap_ST_pp3_stg0_fsm_13 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond6_fu_3025_p2))) begin
ap_reg_ppiten_pp4_it4 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp4_it5 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp4_it5
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp4_it5 <= ap_const_logic_0;
end else begin
if ((ap_ST_pp4_stg0_fsm_21 == ap_CS_fsm)) begin
ap_reg_ppiten_pp4_it5 <= ap_reg_ppiten_pp4_it4;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp3_it0) & (ap_ST_pp3_stg0_fsm_13 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond6_fu_3025_p2))) begin
ap_reg_ppiten_pp4_it5 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp4_it6 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp4_it6
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp4_it6 <= ap_const_logic_0;
end else begin
if ((ap_ST_pp4_stg0_fsm_21 == ap_CS_fsm)) begin
ap_reg_ppiten_pp4_it6 <= ap_reg_ppiten_pp4_it5;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp3_it0) & (ap_ST_pp3_stg0_fsm_13 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond6_fu_3025_p2))) begin
ap_reg_ppiten_pp4_it6 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp5_it0 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp5_it0
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp5_it0 <= ap_const_logic_0;
end else begin
if (((ap_ST_pp5_stg0_fsm_22 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond9_fu_3626_p2))) begin
ap_reg_ppiten_pp5_it0 <= ap_const_logic_0;
end else if (((ap_ST_pp4_stg0_fsm_21 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp4_it0) & ~(ap_const_lv1_0 == exitcond7_fu_3609_p2))) begin
ap_reg_ppiten_pp5_it0 <= ap_const_logic_1;
end
end
end
/// ap_reg_ppiten_pp5_it1 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp5_it1
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp5_it1 <= ap_const_logic_0;
end else begin
if (((ap_const_lv1_0 == exitcond9_reg_5697) & (ap_ST_pp5_stg7_fsm_29 == ap_CS_fsm))) begin
ap_reg_ppiten_pp5_it1 <= ap_const_logic_1;
end else if ((((ap_ST_pp4_stg0_fsm_21 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp4_it0) & ~(ap_const_lv1_0 == exitcond7_fu_3609_p2)) | ((ap_ST_pp5_stg7_fsm_29 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond9_reg_5697)))) begin
ap_reg_ppiten_pp5_it1 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp5_it2 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp5_it2
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp5_it2 <= ap_const_logic_0;
end else begin
if ((ap_ST_pp5_stg7_fsm_29 == ap_CS_fsm)) begin
ap_reg_ppiten_pp5_it2 <= ap_reg_ppiten_pp5_it1;
end else if (((ap_ST_pp4_stg0_fsm_21 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp4_it0) & ~(ap_const_lv1_0 == exitcond7_fu_3609_p2))) begin
ap_reg_ppiten_pp5_it2 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp5_it3 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp5_it3
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp5_it3 <= ap_const_logic_0;
end else begin
if ((ap_ST_pp5_stg7_fsm_29 == ap_CS_fsm)) begin
ap_reg_ppiten_pp5_it3 <= ap_reg_ppiten_pp5_it2;
end else if (((ap_ST_pp4_stg0_fsm_21 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp4_it0) & ~(ap_const_lv1_0 == exitcond7_fu_3609_p2))) begin
ap_reg_ppiten_pp5_it3 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp6_it0 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp6_it0
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp6_it0 <= ap_const_logic_0;
end else begin
if (((ap_ST_pp6_stg0_fsm_30 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond10_fu_3978_p2))) begin
ap_reg_ppiten_pp6_it0 <= ap_const_logic_0;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp5_it0) & (ap_ST_pp5_stg0_fsm_22 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond9_fu_3626_p2))) begin
ap_reg_ppiten_pp6_it0 <= ap_const_logic_1;
end
end
end
/// ap_reg_ppiten_pp6_it1 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp6_it1
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp6_it1 <= ap_const_logic_0;
end else begin
if (((ap_ST_pp6_stg0_fsm_30 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond10_fu_3978_p2))) begin
ap_reg_ppiten_pp6_it1 <= ap_const_logic_1;
end else if ((((ap_const_logic_1 == ap_reg_ppiten_pp5_it0) & (ap_ST_pp5_stg0_fsm_22 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond9_fu_3626_p2)) | ((ap_ST_pp6_stg0_fsm_30 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond10_fu_3978_p2)))) begin
ap_reg_ppiten_pp6_it1 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp6_it2 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp6_it2
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp6_it2 <= ap_const_logic_0;
end else begin
if ((ap_ST_pp6_stg0_fsm_30 == ap_CS_fsm)) begin
ap_reg_ppiten_pp6_it2 <= ap_reg_ppiten_pp6_it1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp5_it0) & (ap_ST_pp5_stg0_fsm_22 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond9_fu_3626_p2))) begin
ap_reg_ppiten_pp6_it2 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp6_it3 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp6_it3
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp6_it3 <= ap_const_logic_0;
end else begin
if ((ap_ST_pp6_stg0_fsm_30 == ap_CS_fsm)) begin
ap_reg_ppiten_pp6_it3 <= ap_reg_ppiten_pp6_it2;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp5_it0) & (ap_ST_pp5_stg0_fsm_22 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond9_fu_3626_p2))) begin
ap_reg_ppiten_pp6_it3 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp6_it4 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp6_it4
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp6_it4 <= ap_const_logic_0;
end else begin
if ((ap_ST_pp6_stg0_fsm_30 == ap_CS_fsm)) begin
ap_reg_ppiten_pp6_it4 <= ap_reg_ppiten_pp6_it3;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp5_it0) & (ap_ST_pp5_stg0_fsm_22 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond9_fu_3626_p2))) begin
ap_reg_ppiten_pp6_it4 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp6_it5 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp6_it5
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp6_it5 <= ap_const_logic_0;
end else begin
if ((ap_ST_pp6_stg0_fsm_30 == ap_CS_fsm)) begin
ap_reg_ppiten_pp6_it5 <= ap_reg_ppiten_pp6_it4;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp5_it0) & (ap_ST_pp5_stg0_fsm_22 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond9_fu_3626_p2))) begin
ap_reg_ppiten_pp6_it5 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp6_it6 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp6_it6
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp6_it6 <= ap_const_logic_0;
end else begin
if ((ap_ST_pp6_stg0_fsm_30 == ap_CS_fsm)) begin
ap_reg_ppiten_pp6_it6 <= ap_reg_ppiten_pp6_it5;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp5_it0) & (ap_ST_pp5_stg0_fsm_22 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond9_fu_3626_p2))) begin
ap_reg_ppiten_pp6_it6 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp7_it0 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp7_it0
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp7_it0 <= ap_const_logic_0;
end else begin
if (((ap_ST_pp7_stg0_fsm_31 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond12_fu_4005_p2))) begin
ap_reg_ppiten_pp7_it0 <= ap_const_logic_0;
end else if (((ap_ST_pp6_stg0_fsm_30 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp6_it0) & ~(ap_const_lv1_0 == exitcond10_fu_3978_p2))) begin
ap_reg_ppiten_pp7_it0 <= ap_const_logic_1;
end
end
end
/// ap_reg_ppiten_pp7_it1 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp7_it1
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp7_it1 <= ap_const_logic_0;
end else begin
if (((ap_const_lv1_0 == exitcond12_reg_5924) & (ap_ST_pp7_stg7_fsm_38 == ap_CS_fsm))) begin
ap_reg_ppiten_pp7_it1 <= ap_const_logic_1;
end else if ((((ap_ST_pp6_stg0_fsm_30 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp6_it0) & ~(ap_const_lv1_0 == exitcond10_fu_3978_p2)) | ((ap_ST_pp7_stg7_fsm_38 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond12_reg_5924)))) begin
ap_reg_ppiten_pp7_it1 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp7_it2 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp7_it2
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp7_it2 <= ap_const_logic_0;
end else begin
if ((ap_ST_pp7_stg7_fsm_38 == ap_CS_fsm)) begin
ap_reg_ppiten_pp7_it2 <= ap_reg_ppiten_pp7_it1;
end else if (((ap_ST_pp6_stg0_fsm_30 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp6_it0) & ~(ap_const_lv1_0 == exitcond10_fu_3978_p2))) begin
ap_reg_ppiten_pp7_it2 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp7_it3 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp7_it3
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp7_it3 <= ap_const_logic_0;
end else begin
if ((ap_ST_pp7_stg7_fsm_38 == ap_CS_fsm)) begin
ap_reg_ppiten_pp7_it3 <= ap_reg_ppiten_pp7_it2;
end else if (((ap_ST_pp6_stg0_fsm_30 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp6_it0) & ~(ap_const_lv1_0 == exitcond10_fu_3978_p2))) begin
ap_reg_ppiten_pp7_it3 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp8_it0 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp8_it0
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp8_it0 <= ap_const_logic_0;
end else begin
if (((ap_ST_pp8_stg0_fsm_40 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond_fu_4357_p2))) begin
ap_reg_ppiten_pp8_it0 <= ap_const_logic_0;
end else if ((((ap_ST_st1_fsm_1 == ap_CS_fsm) & ~(ap_const_lv1_0 == or_cond_fu_2365_p2) & (ap_const_lv1_0 == tmp_2_fu_2371_p2)) | (ap_ST_st131_fsm_39 == ap_CS_fsm))) begin
ap_reg_ppiten_pp8_it0 <= ap_const_logic_1;
end
end
end
/// ap_reg_ppiten_pp8_it1 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp8_it1
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp8_it1 <= ap_const_logic_0;
end else begin
if (((ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg28_fsm_68 == ap_CS_fsm))) begin
ap_reg_ppiten_pp8_it1 <= ap_const_logic_1;
end else if ((((ap_ST_st1_fsm_1 == ap_CS_fsm) & ~(ap_const_lv1_0 == or_cond_fu_2365_p2) & (ap_const_lv1_0 == tmp_2_fu_2371_p2)) | (ap_ST_st131_fsm_39 == ap_CS_fsm) | ((ap_ST_pp8_stg28_fsm_68 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond_reg_6132)))) begin
ap_reg_ppiten_pp8_it1 <= ap_const_logic_0;
end
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_ST_pp1_stg0_fsm_4 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond3_fu_2404_p2))) begin
a_addr100_reg_5247 <= tmp_12_trn_cast_fu_2448_p1[6:0];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg24_fsm_64 == ap_CS_fsm))) begin
a_addr10_reg_6830 <= (a_addr18_cast_fu_5089_p1 + tmp_182_trn_cast_reg_6254);
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp3_it0) & (ap_const_lv1_0 == exitcond6_reg_5446) & (ap_ST_pp3_stg1_fsm_14 == ap_CS_fsm))) begin
a_addr112_reg_5548[0] <= a_addr112_fu_3266_p2[0];
a_addr112_reg_5548[2] <= a_addr112_fu_3266_p2[2];
a_addr112_reg_5548[3] <= a_addr112_fu_3266_p2[3];
a_addr112_reg_5548[4] <= a_addr112_fu_3266_p2[4];
a_addr112_reg_5548[5] <= a_addr112_fu_3266_p2[5];
a_addr112_reg_5548[6] <= a_addr112_fu_3266_p2[6];
end
if (((ap_ST_pp3_stg2_fsm_15 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp3_it0) & (ap_const_lv1_0 == exitcond6_reg_5446))) begin
a_addr116_reg_5608[0] <= a_addr116_fu_3424_p2[0];
a_addr116_reg_5608[1] <= a_addr116_fu_3424_p2[1];
a_addr116_reg_5608[3] <= a_addr116_fu_3424_p2[3];
a_addr116_reg_5608[4] <= a_addr116_fu_3424_p2[4];
a_addr116_reg_5608[5] <= a_addr116_fu_3424_p2[5];
a_addr116_reg_5608[6] <= a_addr116_fu_3424_p2[6];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg24_fsm_64 == ap_CS_fsm))) begin
a_addr13_reg_6825[2] <= a_addr13_fu_5103_p2[2];
a_addr13_reg_6825[3] <= a_addr13_fu_5103_p2[3];
a_addr13_reg_6825[4] <= a_addr13_fu_5103_p2[4];
a_addr13_reg_6825[5] <= a_addr13_fu_5103_p2[5];
a_addr13_reg_6825[6] <= a_addr13_fu_5103_p2[6];
a_addr13_reg_6825[7] <= a_addr13_fu_5103_p2[7];
a_addr13_reg_6825[8] <= a_addr13_fu_5103_p2[8];
a_addr13_reg_6825[9] <= a_addr13_fu_5103_p2[9];
a_addr13_reg_6825[10] <= a_addr13_fu_5103_p2[10];
a_addr13_reg_6825[11] <= a_addr13_fu_5103_p2[11];
a_addr13_reg_6825[12] <= a_addr13_fu_5103_p2[12];
a_addr13_reg_6825[13] <= a_addr13_fu_5103_p2[13];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg24_fsm_64 == ap_CS_fsm))) begin
a_addr16_reg_6820 <= (a_addr18_cast_fu_5089_p1 + tmp_178_trn_cast_reg_6212);
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg24_fsm_64 == ap_CS_fsm))) begin
a_addr19_reg_6815[1] <= a_addr19_fu_5093_p2[1];
a_addr19_reg_6815[2] <= a_addr19_fu_5093_p2[2];
a_addr19_reg_6815[3] <= a_addr19_fu_5093_p2[3];
a_addr19_reg_6815[4] <= a_addr19_fu_5093_p2[4];
a_addr19_reg_6815[5] <= a_addr19_fu_5093_p2[5];
a_addr19_reg_6815[6] <= a_addr19_fu_5093_p2[6];
a_addr19_reg_6815[7] <= a_addr19_fu_5093_p2[7];
a_addr19_reg_6815[8] <= a_addr19_fu_5093_p2[8];
a_addr19_reg_6815[9] <= a_addr19_fu_5093_p2[9];
a_addr19_reg_6815[10] <= a_addr19_fu_5093_p2[10];
a_addr19_reg_6815[11] <= a_addr19_fu_5093_p2[11];
a_addr19_reg_6815[12] <= a_addr19_fu_5093_p2[12];
a_addr19_reg_6815[13] <= a_addr19_fu_5093_p2[13];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg24_fsm_64 == ap_CS_fsm))) begin
a_addr1_reg_6845[3] <= a_addr1_fu_5123_p2[3];
a_addr1_reg_6845[4] <= a_addr1_fu_5123_p2[4];
a_addr1_reg_6845[5] <= a_addr1_fu_5123_p2[5];
a_addr1_reg_6845[6] <= a_addr1_fu_5123_p2[6];
a_addr1_reg_6845[7] <= a_addr1_fu_5123_p2[7];
a_addr1_reg_6845[8] <= a_addr1_fu_5123_p2[8];
a_addr1_reg_6845[9] <= a_addr1_fu_5123_p2[9];
a_addr1_reg_6845[10] <= a_addr1_fu_5123_p2[10];
a_addr1_reg_6845[11] <= a_addr1_fu_5123_p2[11];
a_addr1_reg_6845[12] <= a_addr1_fu_5123_p2[12];
a_addr1_reg_6845[13] <= a_addr1_fu_5123_p2[13];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg24_fsm_64 == ap_CS_fsm))) begin
a_addr22_reg_6810[3] <= a_addr22_fu_5075_p2[3];
a_addr22_reg_6810[4] <= a_addr22_fu_5075_p2[4];
a_addr22_reg_6810[5] <= a_addr22_fu_5075_p2[5];
a_addr22_reg_6810[6] <= a_addr22_fu_5075_p2[6];
a_addr22_reg_6810[7] <= a_addr22_fu_5075_p2[7];
a_addr22_reg_6810[8] <= a_addr22_fu_5075_p2[8];
a_addr22_reg_6810[9] <= a_addr22_fu_5075_p2[9];
a_addr22_reg_6810[10] <= a_addr22_fu_5075_p2[10];
a_addr22_reg_6810[11] <= a_addr22_fu_5075_p2[11];
a_addr22_reg_6810[12] <= a_addr22_fu_5075_p2[12];
a_addr22_reg_6810[13] <= a_addr22_fu_5075_p2[13];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond3_reg_5195) & (ap_ST_pp1_stg4_fsm_8 == ap_CS_fsm))) begin
a_addr23_reg_5382 <= (a_addr21_cast_fu_2892_p1 + tmp_6_trn_cast_reg_5226);
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond3_reg_5195) & (ap_ST_pp1_stg4_fsm_8 == ap_CS_fsm))) begin
a_addr25_reg_5392 <= (a_addr24_cast_fu_2941_p1 + tmp_6_trn_cast_reg_5226);
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp5_it0) & (ap_ST_pp5_stg0_fsm_22 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond9_fu_3626_p2))) begin
a_addr37_cast_reg_5729[6] <= a_addr37_cast_fu_3684_p1[6];
a_addr37_cast_reg_5729[7] <= a_addr37_cast_fu_3684_p1[7];
a_addr37_cast_reg_5729[8] <= a_addr37_cast_fu_3684_p1[8];
a_addr37_cast_reg_5729[9] <= a_addr37_cast_fu_3684_p1[9];
a_addr37_cast_reg_5729[10] <= a_addr37_cast_fu_3684_p1[10];
a_addr37_cast_reg_5729[11] <= a_addr37_cast_fu_3684_p1[11];
a_addr37_cast_reg_5729[12] <= a_addr37_cast_fu_3684_p1[12];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg22_fsm_62 == ap_CS_fsm))) begin
a_addr45_cast_reg_6741[6] <= a_addr45_cast_fu_5010_p1[6];
a_addr45_cast_reg_6741[9] <= a_addr45_cast_fu_5010_p1[9];
a_addr45_cast_reg_6741[10] <= a_addr45_cast_fu_5010_p1[10];
a_addr45_cast_reg_6741[11] <= a_addr45_cast_fu_5010_p1[11];
a_addr45_cast_reg_6741[12] <= a_addr45_cast_fu_5010_p1[12];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg24_fsm_64 == ap_CS_fsm))) begin
a_addr4_reg_6840 <= (a_addr18_cast_fu_5089_p1 + tmp_186_trn_cast_reg_6296);
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp5_it1) & (ap_ST_pp5_stg3_fsm_25 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond9_reg_5697_pp5_it1))) begin
a_addr50_reg_5890[3] <= a_addr50_fu_3969_p2[3];
a_addr50_reg_5890[4] <= a_addr50_fu_3969_p2[4];
a_addr50_reg_5890[5] <= a_addr50_fu_3969_p2[5];
a_addr50_reg_5890[6] <= a_addr50_fu_3969_p2[6];
a_addr50_reg_5890[7] <= a_addr50_fu_3969_p2[7];
a_addr50_reg_5890[8] <= a_addr50_fu_3969_p2[8];
a_addr50_reg_5890[9] <= a_addr50_fu_3969_p2[9];
a_addr50_reg_5890[10] <= a_addr50_fu_3969_p2[10];
a_addr50_reg_5890[11] <= a_addr50_fu_3969_p2[11];
a_addr50_reg_5890[12] <= a_addr50_fu_3969_p2[12];
a_addr50_reg_5890[13] <= a_addr50_fu_3969_p2[13];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp7_it0) & (ap_const_lv1_0 == exitcond12_reg_5924) & (ap_ST_pp7_stg1_fsm_32 == ap_CS_fsm))) begin
a_addr51_cast_reg_5982[6] <= a_addr51_cast_fu_4110_p1[6];
a_addr51_cast_reg_5982[7] <= a_addr51_cast_fu_4110_p1[7];
a_addr51_cast_reg_5982[8] <= a_addr51_cast_fu_4110_p1[8];
a_addr51_cast_reg_5982[9] <= a_addr51_cast_fu_4110_p1[9];
a_addr51_cast_reg_5982[10] <= a_addr51_cast_fu_4110_p1[10];
a_addr51_cast_reg_5982[11] <= a_addr51_cast_fu_4110_p1[11];
end
if (((ap_ST_pp8_stg0_fsm_40 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_fu_4357_p2))) begin
a_addr63_cast_reg_6165[6] <= a_addr63_cast_fu_4411_p1[6];
a_addr63_cast_reg_6165[7] <= a_addr63_cast_fu_4411_p1[7];
a_addr63_cast_reg_6165[8] <= a_addr63_cast_fu_4411_p1[8];
a_addr63_cast_reg_6165[9] <= a_addr63_cast_fu_4411_p1[9];
a_addr63_cast_reg_6165[10] <= a_addr63_cast_fu_4411_p1[10];
a_addr63_cast_reg_6165[11] <= a_addr63_cast_fu_4411_p1[11];
a_addr63_cast_reg_6165[12] <= a_addr63_cast_fu_4411_p1[12];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg18_fsm_58 == ap_CS_fsm))) begin
a_addr72_cast_reg_6661[7] <= a_addr72_cast_fu_4927_p1[7];
a_addr72_cast_reg_6661[9] <= a_addr72_cast_fu_4927_p1[9];
a_addr72_cast_reg_6661[10] <= a_addr72_cast_fu_4927_p1[10];
a_addr72_cast_reg_6661[11] <= a_addr72_cast_fu_4927_p1[11];
a_addr72_cast_reg_6661[12] <= a_addr72_cast_fu_4927_p1[12];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg4_fsm_44 == ap_CS_fsm))) begin
a_addr77_cast_reg_6338[7] <= a_addr77_cast_fu_4588_p1[7];
a_addr77_cast_reg_6338[8] <= a_addr77_cast_fu_4588_p1[8];
a_addr77_cast_reg_6338[9] <= a_addr77_cast_fu_4588_p1[9];
a_addr77_cast_reg_6338[10] <= a_addr77_cast_fu_4588_p1[10];
a_addr77_cast_reg_6338[11] <= a_addr77_cast_fu_4588_p1[11];
a_addr77_cast_reg_6338[12] <= a_addr77_cast_fu_4588_p1[12];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg24_fsm_64 == ap_CS_fsm))) begin
a_addr7_reg_6835[1] <= a_addr7_fu_5113_p2[1];
a_addr7_reg_6835[2] <= a_addr7_fu_5113_p2[2];
a_addr7_reg_6835[3] <= a_addr7_fu_5113_p2[3];
a_addr7_reg_6835[4] <= a_addr7_fu_5113_p2[4];
a_addr7_reg_6835[5] <= a_addr7_fu_5113_p2[5];
a_addr7_reg_6835[6] <= a_addr7_fu_5113_p2[6];
a_addr7_reg_6835[7] <= a_addr7_fu_5113_p2[7];
a_addr7_reg_6835[8] <= a_addr7_fu_5113_p2[8];
a_addr7_reg_6835[9] <= a_addr7_fu_5113_p2[9];
a_addr7_reg_6835[10] <= a_addr7_fu_5113_p2[10];
a_addr7_reg_6835[11] <= a_addr7_fu_5113_p2[11];
a_addr7_reg_6835[12] <= a_addr7_fu_5113_p2[12];
a_addr7_reg_6835[13] <= a_addr7_fu_5113_p2[13];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg8_fsm_48 == ap_CS_fsm))) begin
a_addr87_cast_reg_6423[6] <= a_addr87_cast_fu_4676_p1[6];
a_addr87_cast_reg_6423[8] <= a_addr87_cast_fu_4676_p1[8];
a_addr87_cast_reg_6423[9] <= a_addr87_cast_fu_4676_p1[9];
a_addr87_cast_reg_6423[10] <= a_addr87_cast_fu_4676_p1[10];
a_addr87_cast_reg_6423[11] <= a_addr87_cast_fu_4676_p1[11];
a_addr87_cast_reg_6423[12] <= a_addr87_cast_fu_4676_p1[12];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg11_fsm_51 == ap_CS_fsm))) begin
a_addr98_cast_reg_6502[8] <= a_addr98_cast_fu_4760_p1[8];
a_addr98_cast_reg_6502[9] <= a_addr98_cast_fu_4760_p1[9];
a_addr98_cast_reg_6502[10] <= a_addr98_cast_fu_4760_p1[10];
a_addr98_cast_reg_6502[11] <= a_addr98_cast_fu_4760_p1[11];
a_addr98_cast_reg_6502[12] <= a_addr98_cast_fu_4760_p1[12];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg15_fsm_55 == ap_CS_fsm))) begin
a_addr99_cast_reg_6582[6] <= a_addr99_cast_fu_4843_p1[6];
a_addr99_cast_reg_6582[7] <= a_addr99_cast_fu_4843_p1[7];
a_addr99_cast_reg_6582[9] <= a_addr99_cast_fu_4843_p1[9];
a_addr99_cast_reg_6582[10] <= a_addr99_cast_fu_4843_p1[10];
a_addr99_cast_reg_6582[11] <= a_addr99_cast_fu_4843_p1[11];
a_addr99_cast_reg_6582[12] <= a_addr99_cast_fu_4843_p1[12];
end
if ((ap_ST_pp5_stg0_fsm_22 == ap_CS_fsm)) begin
ap_reg_ppstg_a_addr37_cast_reg_5729_pp5_it1[6] <= a_addr37_cast_reg_5729[6];
ap_reg_ppstg_a_addr37_cast_reg_5729_pp5_it1[7] <= a_addr37_cast_reg_5729[7];
ap_reg_ppstg_a_addr37_cast_reg_5729_pp5_it1[8] <= a_addr37_cast_reg_5729[8];
ap_reg_ppstg_a_addr37_cast_reg_5729_pp5_it1[9] <= a_addr37_cast_reg_5729[9];
ap_reg_ppstg_a_addr37_cast_reg_5729_pp5_it1[10] <= a_addr37_cast_reg_5729[10];
ap_reg_ppstg_a_addr37_cast_reg_5729_pp5_it1[11] <= a_addr37_cast_reg_5729[11];
ap_reg_ppstg_a_addr37_cast_reg_5729_pp5_it1[12] <= a_addr37_cast_reg_5729[12];
end
if ((ap_ST_pp7_stg0_fsm_31 == ap_CS_fsm)) begin
ap_reg_ppstg_b_addr36_cast_reg_5956_pp7_it1[6] <= b_addr36_cast_reg_5956[6];
ap_reg_ppstg_b_addr36_cast_reg_5956_pp7_it1[7] <= b_addr36_cast_reg_5956[7];
ap_reg_ppstg_b_addr36_cast_reg_5956_pp7_it1[8] <= b_addr36_cast_reg_5956[8];
ap_reg_ppstg_b_addr36_cast_reg_5956_pp7_it1[9] <= b_addr36_cast_reg_5956[9];
ap_reg_ppstg_b_addr36_cast_reg_5956_pp7_it1[10] <= b_addr36_cast_reg_5956[10];
ap_reg_ppstg_b_addr36_cast_reg_5956_pp7_it1[11] <= b_addr36_cast_reg_5956[11];
ap_reg_ppstg_b_addr36_cast_reg_5956_pp7_it1[12] <= b_addr36_cast_reg_5956[12];
ap_reg_ppstg_b_addr36_cast_reg_5956_pp7_it1[13] <= b_addr36_cast_reg_5956[13];
end
if ((ap_ST_pp6_stg0_fsm_30 == ap_CS_fsm)) begin
ap_reg_ppstg_exitcond10_reg_5905_pp6_it1 <= exitcond10_reg_5905;
end
if ((ap_ST_pp6_stg0_fsm_30 == ap_CS_fsm)) begin
ap_reg_ppstg_exitcond10_reg_5905_pp6_it2 <= ap_reg_ppstg_exitcond10_reg_5905_pp6_it1;
end
if ((ap_ST_pp6_stg0_fsm_30 == ap_CS_fsm)) begin
ap_reg_ppstg_exitcond10_reg_5905_pp6_it3 <= ap_reg_ppstg_exitcond10_reg_5905_pp6_it2;
end
if ((ap_ST_pp6_stg0_fsm_30 == ap_CS_fsm)) begin
ap_reg_ppstg_exitcond10_reg_5905_pp6_it4 <= ap_reg_ppstg_exitcond10_reg_5905_pp6_it3;
end
if ((ap_ST_pp6_stg0_fsm_30 == ap_CS_fsm)) begin
ap_reg_ppstg_exitcond10_reg_5905_pp6_it5 <= ap_reg_ppstg_exitcond10_reg_5905_pp6_it4;
end
if ((ap_ST_pp7_stg0_fsm_31 == ap_CS_fsm)) begin
ap_reg_ppstg_exitcond12_reg_5924_pp7_it1 <= exitcond12_reg_5924;
end
if ((ap_ST_pp7_stg0_fsm_31 == ap_CS_fsm)) begin
ap_reg_ppstg_exitcond12_reg_5924_pp7_it2 <= ap_reg_ppstg_exitcond12_reg_5924_pp7_it1;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_exitcond1_reg_5171_pp0_it1 <= exitcond1_reg_5171;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_exitcond1_reg_5171_pp0_it2 <= ap_reg_ppstg_exitcond1_reg_5171_pp0_it1;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_exitcond1_reg_5171_pp0_it3 <= ap_reg_ppstg_exitcond1_reg_5171_pp0_it2;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_exitcond1_reg_5171_pp0_it4 <= ap_reg_ppstg_exitcond1_reg_5171_pp0_it3;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_exitcond1_reg_5171_pp0_it5 <= ap_reg_ppstg_exitcond1_reg_5171_pp0_it4;
end
if ((ap_ST_pp1_stg0_fsm_4 == ap_CS_fsm)) begin
ap_reg_ppstg_exitcond3_reg_5195_pp1_it1 <= exitcond3_reg_5195;
end
if ((ap_ST_pp1_stg0_fsm_4 == ap_CS_fsm)) begin
ap_reg_ppstg_exitcond3_reg_5195_pp1_it2 <= ap_reg_ppstg_exitcond3_reg_5195_pp1_it1;
end
if ((ap_ST_pp2_stg0_fsm_12 == ap_CS_fsm)) begin
ap_reg_ppstg_exitcond4_reg_5427_pp2_it1 <= exitcond4_reg_5427;
end
if ((ap_ST_pp2_stg0_fsm_12 == ap_CS_fsm)) begin
ap_reg_ppstg_exitcond4_reg_5427_pp2_it2 <= ap_reg_ppstg_exitcond4_reg_5427_pp2_it1;
end
if ((ap_ST_pp2_stg0_fsm_12 == ap_CS_fsm)) begin
ap_reg_ppstg_exitcond4_reg_5427_pp2_it3 <= ap_reg_ppstg_exitcond4_reg_5427_pp2_it2;
end
if ((ap_ST_pp2_stg0_fsm_12 == ap_CS_fsm)) begin
ap_reg_ppstg_exitcond4_reg_5427_pp2_it4 <= ap_reg_ppstg_exitcond4_reg_5427_pp2_it3;
end
if ((ap_ST_pp2_stg0_fsm_12 == ap_CS_fsm)) begin
ap_reg_ppstg_exitcond4_reg_5427_pp2_it5 <= ap_reg_ppstg_exitcond4_reg_5427_pp2_it4;
end
if ((ap_ST_pp3_stg0_fsm_13 == ap_CS_fsm)) begin
ap_reg_ppstg_exitcond6_reg_5446_pp3_it1 <= exitcond6_reg_5446;
end
if ((ap_ST_pp3_stg0_fsm_13 == ap_CS_fsm)) begin
ap_reg_ppstg_exitcond6_reg_5446_pp3_it2 <= ap_reg_ppstg_exitcond6_reg_5446_pp3_it1;
end
if ((ap_ST_pp4_stg0_fsm_21 == ap_CS_fsm)) begin
ap_reg_ppstg_exitcond7_reg_5678_pp4_it1 <= exitcond7_reg_5678;
end
if ((ap_ST_pp4_stg0_fsm_21 == ap_CS_fsm)) begin
ap_reg_ppstg_exitcond7_reg_5678_pp4_it2 <= ap_reg_ppstg_exitcond7_reg_5678_pp4_it1;
end
if ((ap_ST_pp4_stg0_fsm_21 == ap_CS_fsm)) begin
ap_reg_ppstg_exitcond7_reg_5678_pp4_it3 <= ap_reg_ppstg_exitcond7_reg_5678_pp4_it2;
end
if ((ap_ST_pp4_stg0_fsm_21 == ap_CS_fsm)) begin
ap_reg_ppstg_exitcond7_reg_5678_pp4_it4 <= ap_reg_ppstg_exitcond7_reg_5678_pp4_it3;
end
if ((ap_ST_pp4_stg0_fsm_21 == ap_CS_fsm)) begin
ap_reg_ppstg_exitcond7_reg_5678_pp4_it5 <= ap_reg_ppstg_exitcond7_reg_5678_pp4_it4;
end
if ((ap_ST_pp5_stg0_fsm_22 == ap_CS_fsm)) begin
ap_reg_ppstg_exitcond9_reg_5697_pp5_it1 <= exitcond9_reg_5697;
end
if ((ap_ST_pp5_stg0_fsm_22 == ap_CS_fsm)) begin
ap_reg_ppstg_exitcond9_reg_5697_pp5_it2 <= ap_reg_ppstg_exitcond9_reg_5697_pp5_it1;
end
if ((ap_ST_pp3_stg3_fsm_16 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_106_reg_5658_pp3_it2 <= tmp_106_reg_5658;
end
if ((ap_ST_pp3_stg4_fsm_17 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_114_reg_5668_pp3_it2 <= tmp_114_reg_5668;
end
if ((ap_ST_pp4_stg0_fsm_21 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_122_reg_5687_pp4_it1[0] <= tmp_122_reg_5687[0];
ap_reg_ppstg_tmp_122_reg_5687_pp4_it1[1] <= tmp_122_reg_5687[1];
ap_reg_ppstg_tmp_122_reg_5687_pp4_it1[2] <= tmp_122_reg_5687[2];
ap_reg_ppstg_tmp_122_reg_5687_pp4_it1[3] <= tmp_122_reg_5687[3];
ap_reg_ppstg_tmp_122_reg_5687_pp4_it1[4] <= tmp_122_reg_5687[4];
ap_reg_ppstg_tmp_122_reg_5687_pp4_it1[5] <= tmp_122_reg_5687[5];
ap_reg_ppstg_tmp_122_reg_5687_pp4_it1[6] <= tmp_122_reg_5687[6];
end
if ((ap_ST_pp4_stg0_fsm_21 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_122_reg_5687_pp4_it2[0] <= ap_reg_ppstg_tmp_122_reg_5687_pp4_it1[0];
ap_reg_ppstg_tmp_122_reg_5687_pp4_it2[1] <= ap_reg_ppstg_tmp_122_reg_5687_pp4_it1[1];
ap_reg_ppstg_tmp_122_reg_5687_pp4_it2[2] <= ap_reg_ppstg_tmp_122_reg_5687_pp4_it1[2];
ap_reg_ppstg_tmp_122_reg_5687_pp4_it2[3] <= ap_reg_ppstg_tmp_122_reg_5687_pp4_it1[3];
ap_reg_ppstg_tmp_122_reg_5687_pp4_it2[4] <= ap_reg_ppstg_tmp_122_reg_5687_pp4_it1[4];
ap_reg_ppstg_tmp_122_reg_5687_pp4_it2[5] <= ap_reg_ppstg_tmp_122_reg_5687_pp4_it1[5];
ap_reg_ppstg_tmp_122_reg_5687_pp4_it2[6] <= ap_reg_ppstg_tmp_122_reg_5687_pp4_it1[6];
end
if ((ap_ST_pp4_stg0_fsm_21 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_122_reg_5687_pp4_it3[0] <= ap_reg_ppstg_tmp_122_reg_5687_pp4_it2[0];
ap_reg_ppstg_tmp_122_reg_5687_pp4_it3[1] <= ap_reg_ppstg_tmp_122_reg_5687_pp4_it2[1];
ap_reg_ppstg_tmp_122_reg_5687_pp4_it3[2] <= ap_reg_ppstg_tmp_122_reg_5687_pp4_it2[2];
ap_reg_ppstg_tmp_122_reg_5687_pp4_it3[3] <= ap_reg_ppstg_tmp_122_reg_5687_pp4_it2[3];
ap_reg_ppstg_tmp_122_reg_5687_pp4_it3[4] <= ap_reg_ppstg_tmp_122_reg_5687_pp4_it2[4];
ap_reg_ppstg_tmp_122_reg_5687_pp4_it3[5] <= ap_reg_ppstg_tmp_122_reg_5687_pp4_it2[5];
ap_reg_ppstg_tmp_122_reg_5687_pp4_it3[6] <= ap_reg_ppstg_tmp_122_reg_5687_pp4_it2[6];
end
if ((ap_ST_pp4_stg0_fsm_21 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_122_reg_5687_pp4_it4[0] <= ap_reg_ppstg_tmp_122_reg_5687_pp4_it3[0];
ap_reg_ppstg_tmp_122_reg_5687_pp4_it4[1] <= ap_reg_ppstg_tmp_122_reg_5687_pp4_it3[1];
ap_reg_ppstg_tmp_122_reg_5687_pp4_it4[2] <= ap_reg_ppstg_tmp_122_reg_5687_pp4_it3[2];
ap_reg_ppstg_tmp_122_reg_5687_pp4_it4[3] <= ap_reg_ppstg_tmp_122_reg_5687_pp4_it3[3];
ap_reg_ppstg_tmp_122_reg_5687_pp4_it4[4] <= ap_reg_ppstg_tmp_122_reg_5687_pp4_it3[4];
ap_reg_ppstg_tmp_122_reg_5687_pp4_it4[5] <= ap_reg_ppstg_tmp_122_reg_5687_pp4_it3[5];
ap_reg_ppstg_tmp_122_reg_5687_pp4_it4[6] <= ap_reg_ppstg_tmp_122_reg_5687_pp4_it3[6];
end
if ((ap_ST_pp4_stg0_fsm_21 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_122_reg_5687_pp4_it5[0] <= ap_reg_ppstg_tmp_122_reg_5687_pp4_it4[0];
ap_reg_ppstg_tmp_122_reg_5687_pp4_it5[1] <= ap_reg_ppstg_tmp_122_reg_5687_pp4_it4[1];
ap_reg_ppstg_tmp_122_reg_5687_pp4_it5[2] <= ap_reg_ppstg_tmp_122_reg_5687_pp4_it4[2];
ap_reg_ppstg_tmp_122_reg_5687_pp4_it5[3] <= ap_reg_ppstg_tmp_122_reg_5687_pp4_it4[3];
ap_reg_ppstg_tmp_122_reg_5687_pp4_it5[4] <= ap_reg_ppstg_tmp_122_reg_5687_pp4_it4[4];
ap_reg_ppstg_tmp_122_reg_5687_pp4_it5[5] <= ap_reg_ppstg_tmp_122_reg_5687_pp4_it4[5];
ap_reg_ppstg_tmp_122_reg_5687_pp4_it5[6] <= ap_reg_ppstg_tmp_122_reg_5687_pp4_it4[6];
end
if ((ap_ST_pp5_stg0_fsm_22 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_125_reg_5740_pp5_it1[0] <= tmp_125_reg_5740[0];
ap_reg_ppstg_tmp_125_reg_5740_pp5_it1[1] <= tmp_125_reg_5740[1];
ap_reg_ppstg_tmp_125_reg_5740_pp5_it1[2] <= tmp_125_reg_5740[2];
ap_reg_ppstg_tmp_125_reg_5740_pp5_it1[3] <= tmp_125_reg_5740[3];
ap_reg_ppstg_tmp_125_reg_5740_pp5_it1[4] <= tmp_125_reg_5740[4];
ap_reg_ppstg_tmp_125_reg_5740_pp5_it1[5] <= tmp_125_reg_5740[5];
ap_reg_ppstg_tmp_125_reg_5740_pp5_it1[6] <= tmp_125_reg_5740[6];
ap_reg_ppstg_tmp_125_reg_5740_pp5_it1[7] <= tmp_125_reg_5740[7];
ap_reg_ppstg_tmp_125_reg_5740_pp5_it1[8] <= tmp_125_reg_5740[8];
ap_reg_ppstg_tmp_125_reg_5740_pp5_it1[9] <= tmp_125_reg_5740[9];
ap_reg_ppstg_tmp_125_reg_5740_pp5_it1[10] <= tmp_125_reg_5740[10];
ap_reg_ppstg_tmp_125_reg_5740_pp5_it1[11] <= tmp_125_reg_5740[11];
ap_reg_ppstg_tmp_125_reg_5740_pp5_it1[12] <= tmp_125_reg_5740[12];
ap_reg_ppstg_tmp_125_reg_5740_pp5_it1[13] <= tmp_125_reg_5740[13];
end
if ((ap_ST_pp5_stg1_fsm_23 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_130_reg_5770_pp5_it1[1] <= tmp_130_reg_5770[1];
ap_reg_ppstg_tmp_130_reg_5770_pp5_it1[2] <= tmp_130_reg_5770[2];
ap_reg_ppstg_tmp_130_reg_5770_pp5_it1[3] <= tmp_130_reg_5770[3];
ap_reg_ppstg_tmp_130_reg_5770_pp5_it1[4] <= tmp_130_reg_5770[4];
ap_reg_ppstg_tmp_130_reg_5770_pp5_it1[5] <= tmp_130_reg_5770[5];
ap_reg_ppstg_tmp_130_reg_5770_pp5_it1[6] <= tmp_130_reg_5770[6];
ap_reg_ppstg_tmp_130_reg_5770_pp5_it1[7] <= tmp_130_reg_5770[7];
ap_reg_ppstg_tmp_130_reg_5770_pp5_it1[8] <= tmp_130_reg_5770[8];
ap_reg_ppstg_tmp_130_reg_5770_pp5_it1[9] <= tmp_130_reg_5770[9];
ap_reg_ppstg_tmp_130_reg_5770_pp5_it1[10] <= tmp_130_reg_5770[10];
ap_reg_ppstg_tmp_130_reg_5770_pp5_it1[11] <= tmp_130_reg_5770[11];
ap_reg_ppstg_tmp_130_reg_5770_pp5_it1[12] <= tmp_130_reg_5770[12];
ap_reg_ppstg_tmp_130_reg_5770_pp5_it1[13] <= tmp_130_reg_5770[13];
end
if ((ap_ST_pp5_stg1_fsm_23 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_138_reg_5790_pp5_it1[0] <= tmp_138_reg_5790[0];
ap_reg_ppstg_tmp_138_reg_5790_pp5_it1[1] <= tmp_138_reg_5790[1];
ap_reg_ppstg_tmp_138_reg_5790_pp5_it1[2] <= tmp_138_reg_5790[2];
ap_reg_ppstg_tmp_138_reg_5790_pp5_it1[3] <= tmp_138_reg_5790[3];
ap_reg_ppstg_tmp_138_reg_5790_pp5_it1[4] <= tmp_138_reg_5790[4];
ap_reg_ppstg_tmp_138_reg_5790_pp5_it1[5] <= tmp_138_reg_5790[5];
ap_reg_ppstg_tmp_138_reg_5790_pp5_it1[6] <= tmp_138_reg_5790[6];
ap_reg_ppstg_tmp_138_reg_5790_pp5_it1[7] <= tmp_138_reg_5790[7];
ap_reg_ppstg_tmp_138_reg_5790_pp5_it1[8] <= tmp_138_reg_5790[8];
ap_reg_ppstg_tmp_138_reg_5790_pp5_it1[9] <= tmp_138_reg_5790[9];
ap_reg_ppstg_tmp_138_reg_5790_pp5_it1[10] <= tmp_138_reg_5790[10];
ap_reg_ppstg_tmp_138_reg_5790_pp5_it1[11] <= tmp_138_reg_5790[11];
ap_reg_ppstg_tmp_138_reg_5790_pp5_it1[12] <= tmp_138_reg_5790[12];
ap_reg_ppstg_tmp_138_reg_5790_pp5_it1[13] <= tmp_138_reg_5790[13];
end
if ((ap_ST_pp5_stg2_fsm_24 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_146_reg_5805_pp5_it1[2] <= tmp_146_reg_5805[2];
ap_reg_ppstg_tmp_146_reg_5805_pp5_it1[3] <= tmp_146_reg_5805[3];
ap_reg_ppstg_tmp_146_reg_5805_pp5_it1[4] <= tmp_146_reg_5805[4];
ap_reg_ppstg_tmp_146_reg_5805_pp5_it1[5] <= tmp_146_reg_5805[5];
ap_reg_ppstg_tmp_146_reg_5805_pp5_it1[6] <= tmp_146_reg_5805[6];
ap_reg_ppstg_tmp_146_reg_5805_pp5_it1[7] <= tmp_146_reg_5805[7];
ap_reg_ppstg_tmp_146_reg_5805_pp5_it1[8] <= tmp_146_reg_5805[8];
ap_reg_ppstg_tmp_146_reg_5805_pp5_it1[9] <= tmp_146_reg_5805[9];
ap_reg_ppstg_tmp_146_reg_5805_pp5_it1[10] <= tmp_146_reg_5805[10];
ap_reg_ppstg_tmp_146_reg_5805_pp5_it1[11] <= tmp_146_reg_5805[11];
ap_reg_ppstg_tmp_146_reg_5805_pp5_it1[12] <= tmp_146_reg_5805[12];
ap_reg_ppstg_tmp_146_reg_5805_pp5_it1[13] <= tmp_146_reg_5805[13];
end
if ((ap_ST_pp5_stg2_fsm_24 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_154_reg_5825_pp5_it1[0] <= tmp_154_reg_5825[0];
ap_reg_ppstg_tmp_154_reg_5825_pp5_it1[1] <= tmp_154_reg_5825[1];
ap_reg_ppstg_tmp_154_reg_5825_pp5_it1[2] <= tmp_154_reg_5825[2];
ap_reg_ppstg_tmp_154_reg_5825_pp5_it1[3] <= tmp_154_reg_5825[3];
ap_reg_ppstg_tmp_154_reg_5825_pp5_it1[4] <= tmp_154_reg_5825[4];
ap_reg_ppstg_tmp_154_reg_5825_pp5_it1[5] <= tmp_154_reg_5825[5];
ap_reg_ppstg_tmp_154_reg_5825_pp5_it1[6] <= tmp_154_reg_5825[6];
ap_reg_ppstg_tmp_154_reg_5825_pp5_it1[7] <= tmp_154_reg_5825[7];
ap_reg_ppstg_tmp_154_reg_5825_pp5_it1[8] <= tmp_154_reg_5825[8];
ap_reg_ppstg_tmp_154_reg_5825_pp5_it1[9] <= tmp_154_reg_5825[9];
ap_reg_ppstg_tmp_154_reg_5825_pp5_it1[10] <= tmp_154_reg_5825[10];
ap_reg_ppstg_tmp_154_reg_5825_pp5_it1[11] <= tmp_154_reg_5825[11];
ap_reg_ppstg_tmp_154_reg_5825_pp5_it1[12] <= tmp_154_reg_5825[12];
ap_reg_ppstg_tmp_154_reg_5825_pp5_it1[13] <= tmp_154_reg_5825[13];
end
if ((ap_ST_pp1_stg1_fsm_5 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_15_reg_5272_pp1_it1[0] <= tmp_15_reg_5272[0];
ap_reg_ppstg_tmp_15_reg_5272_pp1_it1[1] <= tmp_15_reg_5272[1];
ap_reg_ppstg_tmp_15_reg_5272_pp1_it1[2] <= tmp_15_reg_5272[2];
ap_reg_ppstg_tmp_15_reg_5272_pp1_it1[3] <= tmp_15_reg_5272[3];
ap_reg_ppstg_tmp_15_reg_5272_pp1_it1[4] <= tmp_15_reg_5272[4];
ap_reg_ppstg_tmp_15_reg_5272_pp1_it1[5] <= tmp_15_reg_5272[5];
ap_reg_ppstg_tmp_15_reg_5272_pp1_it1[6] <= tmp_15_reg_5272[6];
ap_reg_ppstg_tmp_15_reg_5272_pp1_it1[7] <= tmp_15_reg_5272[7];
ap_reg_ppstg_tmp_15_reg_5272_pp1_it1[8] <= tmp_15_reg_5272[8];
ap_reg_ppstg_tmp_15_reg_5272_pp1_it1[9] <= tmp_15_reg_5272[9];
ap_reg_ppstg_tmp_15_reg_5272_pp1_it1[10] <= tmp_15_reg_5272[10];
ap_reg_ppstg_tmp_15_reg_5272_pp1_it1[11] <= tmp_15_reg_5272[11];
ap_reg_ppstg_tmp_15_reg_5272_pp1_it1[12] <= tmp_15_reg_5272[12];
ap_reg_ppstg_tmp_15_reg_5272_pp1_it1[13] <= tmp_15_reg_5272[13];
end
if ((ap_ST_pp5_stg3_fsm_25 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_160_reg_5840_pp5_it1[1] <= tmp_160_reg_5840[1];
ap_reg_ppstg_tmp_160_reg_5840_pp5_it1[2] <= tmp_160_reg_5840[2];
ap_reg_ppstg_tmp_160_reg_5840_pp5_it1[3] <= tmp_160_reg_5840[3];
ap_reg_ppstg_tmp_160_reg_5840_pp5_it1[4] <= tmp_160_reg_5840[4];
ap_reg_ppstg_tmp_160_reg_5840_pp5_it1[5] <= tmp_160_reg_5840[5];
ap_reg_ppstg_tmp_160_reg_5840_pp5_it1[6] <= tmp_160_reg_5840[6];
ap_reg_ppstg_tmp_160_reg_5840_pp5_it1[7] <= tmp_160_reg_5840[7];
ap_reg_ppstg_tmp_160_reg_5840_pp5_it1[8] <= tmp_160_reg_5840[8];
ap_reg_ppstg_tmp_160_reg_5840_pp5_it1[9] <= tmp_160_reg_5840[9];
ap_reg_ppstg_tmp_160_reg_5840_pp5_it1[10] <= tmp_160_reg_5840[10];
ap_reg_ppstg_tmp_160_reg_5840_pp5_it1[11] <= tmp_160_reg_5840[11];
ap_reg_ppstg_tmp_160_reg_5840_pp5_it1[12] <= tmp_160_reg_5840[12];
ap_reg_ppstg_tmp_160_reg_5840_pp5_it1[13] <= tmp_160_reg_5840[13];
end
if ((ap_ST_pp5_stg3_fsm_25 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_160_reg_5840_pp5_it2[1] <= ap_reg_ppstg_tmp_160_reg_5840_pp5_it1[1];
ap_reg_ppstg_tmp_160_reg_5840_pp5_it2[2] <= ap_reg_ppstg_tmp_160_reg_5840_pp5_it1[2];
ap_reg_ppstg_tmp_160_reg_5840_pp5_it2[3] <= ap_reg_ppstg_tmp_160_reg_5840_pp5_it1[3];
ap_reg_ppstg_tmp_160_reg_5840_pp5_it2[4] <= ap_reg_ppstg_tmp_160_reg_5840_pp5_it1[4];
ap_reg_ppstg_tmp_160_reg_5840_pp5_it2[5] <= ap_reg_ppstg_tmp_160_reg_5840_pp5_it1[5];
ap_reg_ppstg_tmp_160_reg_5840_pp5_it2[6] <= ap_reg_ppstg_tmp_160_reg_5840_pp5_it1[6];
ap_reg_ppstg_tmp_160_reg_5840_pp5_it2[7] <= ap_reg_ppstg_tmp_160_reg_5840_pp5_it1[7];
ap_reg_ppstg_tmp_160_reg_5840_pp5_it2[8] <= ap_reg_ppstg_tmp_160_reg_5840_pp5_it1[8];
ap_reg_ppstg_tmp_160_reg_5840_pp5_it2[9] <= ap_reg_ppstg_tmp_160_reg_5840_pp5_it1[9];
ap_reg_ppstg_tmp_160_reg_5840_pp5_it2[10] <= ap_reg_ppstg_tmp_160_reg_5840_pp5_it1[10];
ap_reg_ppstg_tmp_160_reg_5840_pp5_it2[11] <= ap_reg_ppstg_tmp_160_reg_5840_pp5_it1[11];
ap_reg_ppstg_tmp_160_reg_5840_pp5_it2[12] <= ap_reg_ppstg_tmp_160_reg_5840_pp5_it1[12];
ap_reg_ppstg_tmp_160_reg_5840_pp5_it2[13] <= ap_reg_ppstg_tmp_160_reg_5840_pp5_it1[13];
end
if ((ap_ST_pp5_stg3_fsm_25 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_164_reg_5880_pp5_it2[0] <= tmp_164_reg_5880[0];
ap_reg_ppstg_tmp_164_reg_5880_pp5_it2[1] <= tmp_164_reg_5880[1];
ap_reg_ppstg_tmp_164_reg_5880_pp5_it2[2] <= tmp_164_reg_5880[2];
ap_reg_ppstg_tmp_164_reg_5880_pp5_it2[3] <= tmp_164_reg_5880[3];
ap_reg_ppstg_tmp_164_reg_5880_pp5_it2[4] <= tmp_164_reg_5880[4];
ap_reg_ppstg_tmp_164_reg_5880_pp5_it2[5] <= tmp_164_reg_5880[5];
ap_reg_ppstg_tmp_164_reg_5880_pp5_it2[6] <= tmp_164_reg_5880[6];
ap_reg_ppstg_tmp_164_reg_5880_pp5_it2[7] <= tmp_164_reg_5880[7];
ap_reg_ppstg_tmp_164_reg_5880_pp5_it2[8] <= tmp_164_reg_5880[8];
ap_reg_ppstg_tmp_164_reg_5880_pp5_it2[9] <= tmp_164_reg_5880[9];
ap_reg_ppstg_tmp_164_reg_5880_pp5_it2[10] <= tmp_164_reg_5880[10];
ap_reg_ppstg_tmp_164_reg_5880_pp5_it2[11] <= tmp_164_reg_5880[11];
ap_reg_ppstg_tmp_164_reg_5880_pp5_it2[12] <= tmp_164_reg_5880[12];
ap_reg_ppstg_tmp_164_reg_5880_pp5_it2[13] <= tmp_164_reg_5880[13];
end
if ((ap_ST_pp5_stg4_fsm_26 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_168_reg_5895_pp5_it2[3] <= tmp_168_reg_5895[3];
ap_reg_ppstg_tmp_168_reg_5895_pp5_it2[4] <= tmp_168_reg_5895[4];
ap_reg_ppstg_tmp_168_reg_5895_pp5_it2[5] <= tmp_168_reg_5895[5];
ap_reg_ppstg_tmp_168_reg_5895_pp5_it2[6] <= tmp_168_reg_5895[6];
ap_reg_ppstg_tmp_168_reg_5895_pp5_it2[7] <= tmp_168_reg_5895[7];
ap_reg_ppstg_tmp_168_reg_5895_pp5_it2[8] <= tmp_168_reg_5895[8];
ap_reg_ppstg_tmp_168_reg_5895_pp5_it2[9] <= tmp_168_reg_5895[9];
ap_reg_ppstg_tmp_168_reg_5895_pp5_it2[10] <= tmp_168_reg_5895[10];
ap_reg_ppstg_tmp_168_reg_5895_pp5_it2[11] <= tmp_168_reg_5895[11];
ap_reg_ppstg_tmp_168_reg_5895_pp5_it2[12] <= tmp_168_reg_5895[12];
ap_reg_ppstg_tmp_168_reg_5895_pp5_it2[13] <= tmp_168_reg_5895[13];
end
if ((ap_ST_pp6_stg0_fsm_30 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_172_reg_5914_pp6_it1[0] <= tmp_172_reg_5914[0];
ap_reg_ppstg_tmp_172_reg_5914_pp6_it1[1] <= tmp_172_reg_5914[1];
ap_reg_ppstg_tmp_172_reg_5914_pp6_it1[2] <= tmp_172_reg_5914[2];
ap_reg_ppstg_tmp_172_reg_5914_pp6_it1[3] <= tmp_172_reg_5914[3];
ap_reg_ppstg_tmp_172_reg_5914_pp6_it1[4] <= tmp_172_reg_5914[4];
ap_reg_ppstg_tmp_172_reg_5914_pp6_it1[5] <= tmp_172_reg_5914[5];
ap_reg_ppstg_tmp_172_reg_5914_pp6_it1[6] <= tmp_172_reg_5914[6];
ap_reg_ppstg_tmp_172_reg_5914_pp6_it1[7] <= tmp_172_reg_5914[7];
ap_reg_ppstg_tmp_172_reg_5914_pp6_it1[8] <= tmp_172_reg_5914[8];
ap_reg_ppstg_tmp_172_reg_5914_pp6_it1[9] <= tmp_172_reg_5914[9];
ap_reg_ppstg_tmp_172_reg_5914_pp6_it1[10] <= tmp_172_reg_5914[10];
ap_reg_ppstg_tmp_172_reg_5914_pp6_it1[11] <= tmp_172_reg_5914[11];
ap_reg_ppstg_tmp_172_reg_5914_pp6_it1[12] <= tmp_172_reg_5914[12];
end
if ((ap_ST_pp6_stg0_fsm_30 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_172_reg_5914_pp6_it2[0] <= ap_reg_ppstg_tmp_172_reg_5914_pp6_it1[0];
ap_reg_ppstg_tmp_172_reg_5914_pp6_it2[1] <= ap_reg_ppstg_tmp_172_reg_5914_pp6_it1[1];
ap_reg_ppstg_tmp_172_reg_5914_pp6_it2[2] <= ap_reg_ppstg_tmp_172_reg_5914_pp6_it1[2];
ap_reg_ppstg_tmp_172_reg_5914_pp6_it2[3] <= ap_reg_ppstg_tmp_172_reg_5914_pp6_it1[3];
ap_reg_ppstg_tmp_172_reg_5914_pp6_it2[4] <= ap_reg_ppstg_tmp_172_reg_5914_pp6_it1[4];
ap_reg_ppstg_tmp_172_reg_5914_pp6_it2[5] <= ap_reg_ppstg_tmp_172_reg_5914_pp6_it1[5];
ap_reg_ppstg_tmp_172_reg_5914_pp6_it2[6] <= ap_reg_ppstg_tmp_172_reg_5914_pp6_it1[6];
ap_reg_ppstg_tmp_172_reg_5914_pp6_it2[7] <= ap_reg_ppstg_tmp_172_reg_5914_pp6_it1[7];
ap_reg_ppstg_tmp_172_reg_5914_pp6_it2[8] <= ap_reg_ppstg_tmp_172_reg_5914_pp6_it1[8];
ap_reg_ppstg_tmp_172_reg_5914_pp6_it2[9] <= ap_reg_ppstg_tmp_172_reg_5914_pp6_it1[9];
ap_reg_ppstg_tmp_172_reg_5914_pp6_it2[10] <= ap_reg_ppstg_tmp_172_reg_5914_pp6_it1[10];
ap_reg_ppstg_tmp_172_reg_5914_pp6_it2[11] <= ap_reg_ppstg_tmp_172_reg_5914_pp6_it1[11];
ap_reg_ppstg_tmp_172_reg_5914_pp6_it2[12] <= ap_reg_ppstg_tmp_172_reg_5914_pp6_it1[12];
end
if ((ap_ST_pp6_stg0_fsm_30 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_172_reg_5914_pp6_it3[0] <= ap_reg_ppstg_tmp_172_reg_5914_pp6_it2[0];
ap_reg_ppstg_tmp_172_reg_5914_pp6_it3[1] <= ap_reg_ppstg_tmp_172_reg_5914_pp6_it2[1];
ap_reg_ppstg_tmp_172_reg_5914_pp6_it3[2] <= ap_reg_ppstg_tmp_172_reg_5914_pp6_it2[2];
ap_reg_ppstg_tmp_172_reg_5914_pp6_it3[3] <= ap_reg_ppstg_tmp_172_reg_5914_pp6_it2[3];
ap_reg_ppstg_tmp_172_reg_5914_pp6_it3[4] <= ap_reg_ppstg_tmp_172_reg_5914_pp6_it2[4];
ap_reg_ppstg_tmp_172_reg_5914_pp6_it3[5] <= ap_reg_ppstg_tmp_172_reg_5914_pp6_it2[5];
ap_reg_ppstg_tmp_172_reg_5914_pp6_it3[6] <= ap_reg_ppstg_tmp_172_reg_5914_pp6_it2[6];
ap_reg_ppstg_tmp_172_reg_5914_pp6_it3[7] <= ap_reg_ppstg_tmp_172_reg_5914_pp6_it2[7];
ap_reg_ppstg_tmp_172_reg_5914_pp6_it3[8] <= ap_reg_ppstg_tmp_172_reg_5914_pp6_it2[8];
ap_reg_ppstg_tmp_172_reg_5914_pp6_it3[9] <= ap_reg_ppstg_tmp_172_reg_5914_pp6_it2[9];
ap_reg_ppstg_tmp_172_reg_5914_pp6_it3[10] <= ap_reg_ppstg_tmp_172_reg_5914_pp6_it2[10];
ap_reg_ppstg_tmp_172_reg_5914_pp6_it3[11] <= ap_reg_ppstg_tmp_172_reg_5914_pp6_it2[11];
ap_reg_ppstg_tmp_172_reg_5914_pp6_it3[12] <= ap_reg_ppstg_tmp_172_reg_5914_pp6_it2[12];
end
if ((ap_ST_pp6_stg0_fsm_30 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_172_reg_5914_pp6_it4[0] <= ap_reg_ppstg_tmp_172_reg_5914_pp6_it3[0];
ap_reg_ppstg_tmp_172_reg_5914_pp6_it4[1] <= ap_reg_ppstg_tmp_172_reg_5914_pp6_it3[1];
ap_reg_ppstg_tmp_172_reg_5914_pp6_it4[2] <= ap_reg_ppstg_tmp_172_reg_5914_pp6_it3[2];
ap_reg_ppstg_tmp_172_reg_5914_pp6_it4[3] <= ap_reg_ppstg_tmp_172_reg_5914_pp6_it3[3];
ap_reg_ppstg_tmp_172_reg_5914_pp6_it4[4] <= ap_reg_ppstg_tmp_172_reg_5914_pp6_it3[4];
ap_reg_ppstg_tmp_172_reg_5914_pp6_it4[5] <= ap_reg_ppstg_tmp_172_reg_5914_pp6_it3[5];
ap_reg_ppstg_tmp_172_reg_5914_pp6_it4[6] <= ap_reg_ppstg_tmp_172_reg_5914_pp6_it3[6];
ap_reg_ppstg_tmp_172_reg_5914_pp6_it4[7] <= ap_reg_ppstg_tmp_172_reg_5914_pp6_it3[7];
ap_reg_ppstg_tmp_172_reg_5914_pp6_it4[8] <= ap_reg_ppstg_tmp_172_reg_5914_pp6_it3[8];
ap_reg_ppstg_tmp_172_reg_5914_pp6_it4[9] <= ap_reg_ppstg_tmp_172_reg_5914_pp6_it3[9];
ap_reg_ppstg_tmp_172_reg_5914_pp6_it4[10] <= ap_reg_ppstg_tmp_172_reg_5914_pp6_it3[10];
ap_reg_ppstg_tmp_172_reg_5914_pp6_it4[11] <= ap_reg_ppstg_tmp_172_reg_5914_pp6_it3[11];
ap_reg_ppstg_tmp_172_reg_5914_pp6_it4[12] <= ap_reg_ppstg_tmp_172_reg_5914_pp6_it3[12];
end
if ((ap_ST_pp6_stg0_fsm_30 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_172_reg_5914_pp6_it5[0] <= ap_reg_ppstg_tmp_172_reg_5914_pp6_it4[0];
ap_reg_ppstg_tmp_172_reg_5914_pp6_it5[1] <= ap_reg_ppstg_tmp_172_reg_5914_pp6_it4[1];
ap_reg_ppstg_tmp_172_reg_5914_pp6_it5[2] <= ap_reg_ppstg_tmp_172_reg_5914_pp6_it4[2];
ap_reg_ppstg_tmp_172_reg_5914_pp6_it5[3] <= ap_reg_ppstg_tmp_172_reg_5914_pp6_it4[3];
ap_reg_ppstg_tmp_172_reg_5914_pp6_it5[4] <= ap_reg_ppstg_tmp_172_reg_5914_pp6_it4[4];
ap_reg_ppstg_tmp_172_reg_5914_pp6_it5[5] <= ap_reg_ppstg_tmp_172_reg_5914_pp6_it4[5];
ap_reg_ppstg_tmp_172_reg_5914_pp6_it5[6] <= ap_reg_ppstg_tmp_172_reg_5914_pp6_it4[6];
ap_reg_ppstg_tmp_172_reg_5914_pp6_it5[7] <= ap_reg_ppstg_tmp_172_reg_5914_pp6_it4[7];
ap_reg_ppstg_tmp_172_reg_5914_pp6_it5[8] <= ap_reg_ppstg_tmp_172_reg_5914_pp6_it4[8];
ap_reg_ppstg_tmp_172_reg_5914_pp6_it5[9] <= ap_reg_ppstg_tmp_172_reg_5914_pp6_it4[9];
ap_reg_ppstg_tmp_172_reg_5914_pp6_it5[10] <= ap_reg_ppstg_tmp_172_reg_5914_pp6_it4[10];
ap_reg_ppstg_tmp_172_reg_5914_pp6_it5[11] <= ap_reg_ppstg_tmp_172_reg_5914_pp6_it4[11];
ap_reg_ppstg_tmp_172_reg_5914_pp6_it5[12] <= ap_reg_ppstg_tmp_172_reg_5914_pp6_it4[12];
end
if ((ap_ST_pp7_stg0_fsm_31 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_174_reg_5967_pp7_it1 <= tmp_174_reg_5967;
end
if ((ap_ST_pp7_stg1_fsm_32 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_178_reg_5997_pp7_it1[1] <= tmp_178_reg_5997[1];
ap_reg_ppstg_tmp_178_reg_5997_pp7_it1[2] <= tmp_178_reg_5997[2];
ap_reg_ppstg_tmp_178_reg_5997_pp7_it1[3] <= tmp_178_reg_5997[3];
ap_reg_ppstg_tmp_178_reg_5997_pp7_it1[4] <= tmp_178_reg_5997[4];
ap_reg_ppstg_tmp_178_reg_5997_pp7_it1[5] <= tmp_178_reg_5997[5];
ap_reg_ppstg_tmp_178_reg_5997_pp7_it1[6] <= tmp_178_reg_5997[6];
ap_reg_ppstg_tmp_178_reg_5997_pp7_it1[7] <= tmp_178_reg_5997[7];
ap_reg_ppstg_tmp_178_reg_5997_pp7_it1[8] <= tmp_178_reg_5997[8];
ap_reg_ppstg_tmp_178_reg_5997_pp7_it1[9] <= tmp_178_reg_5997[9];
ap_reg_ppstg_tmp_178_reg_5997_pp7_it1[10] <= tmp_178_reg_5997[10];
ap_reg_ppstg_tmp_178_reg_5997_pp7_it1[11] <= tmp_178_reg_5997[11];
ap_reg_ppstg_tmp_178_reg_5997_pp7_it1[12] <= tmp_178_reg_5997[12];
ap_reg_ppstg_tmp_178_reg_5997_pp7_it1[13] <= tmp_178_reg_5997[13];
ap_reg_ppstg_tmp_178_reg_5997_pp7_it1[14] <= tmp_178_reg_5997[14];
ap_reg_ppstg_tmp_178_reg_5997_pp7_it1[15] <= tmp_178_reg_5997[15];
ap_reg_ppstg_tmp_178_reg_5997_pp7_it1[16] <= tmp_178_reg_5997[16];
ap_reg_ppstg_tmp_178_reg_5997_pp7_it1[17] <= tmp_178_reg_5997[17];
ap_reg_ppstg_tmp_178_reg_5997_pp7_it1[18] <= tmp_178_reg_5997[18];
ap_reg_ppstg_tmp_178_reg_5997_pp7_it1[19] <= tmp_178_reg_5997[19];
ap_reg_ppstg_tmp_178_reg_5997_pp7_it1[20] <= tmp_178_reg_5997[20];
ap_reg_ppstg_tmp_178_reg_5997_pp7_it1[21] <= tmp_178_reg_5997[21];
ap_reg_ppstg_tmp_178_reg_5997_pp7_it1[22] <= tmp_178_reg_5997[22];
ap_reg_ppstg_tmp_178_reg_5997_pp7_it1[23] <= tmp_178_reg_5997[23];
ap_reg_ppstg_tmp_178_reg_5997_pp7_it1[24] <= tmp_178_reg_5997[24];
ap_reg_ppstg_tmp_178_reg_5997_pp7_it1[25] <= tmp_178_reg_5997[25];
ap_reg_ppstg_tmp_178_reg_5997_pp7_it1[26] <= tmp_178_reg_5997[26];
ap_reg_ppstg_tmp_178_reg_5997_pp7_it1[27] <= tmp_178_reg_5997[27];
ap_reg_ppstg_tmp_178_reg_5997_pp7_it1[28] <= tmp_178_reg_5997[28];
ap_reg_ppstg_tmp_178_reg_5997_pp7_it1[29] <= tmp_178_reg_5997[29];
ap_reg_ppstg_tmp_178_reg_5997_pp7_it1[30] <= tmp_178_reg_5997[30];
ap_reg_ppstg_tmp_178_reg_5997_pp7_it1[31] <= tmp_178_reg_5997[31];
ap_reg_ppstg_tmp_178_reg_5997_pp7_it1[32] <= tmp_178_reg_5997[32];
ap_reg_ppstg_tmp_178_reg_5997_pp7_it1[33] <= tmp_178_reg_5997[33];
ap_reg_ppstg_tmp_178_reg_5997_pp7_it1[34] <= tmp_178_reg_5997[34];
ap_reg_ppstg_tmp_178_reg_5997_pp7_it1[35] <= tmp_178_reg_5997[35];
ap_reg_ppstg_tmp_178_reg_5997_pp7_it1[36] <= tmp_178_reg_5997[36];
ap_reg_ppstg_tmp_178_reg_5997_pp7_it1[37] <= tmp_178_reg_5997[37];
ap_reg_ppstg_tmp_178_reg_5997_pp7_it1[38] <= tmp_178_reg_5997[38];
ap_reg_ppstg_tmp_178_reg_5997_pp7_it1[39] <= tmp_178_reg_5997[39];
ap_reg_ppstg_tmp_178_reg_5997_pp7_it1[40] <= tmp_178_reg_5997[40];
ap_reg_ppstg_tmp_178_reg_5997_pp7_it1[41] <= tmp_178_reg_5997[41];
ap_reg_ppstg_tmp_178_reg_5997_pp7_it1[42] <= tmp_178_reg_5997[42];
ap_reg_ppstg_tmp_178_reg_5997_pp7_it1[43] <= tmp_178_reg_5997[43];
ap_reg_ppstg_tmp_178_reg_5997_pp7_it1[44] <= tmp_178_reg_5997[44];
ap_reg_ppstg_tmp_178_reg_5997_pp7_it1[45] <= tmp_178_reg_5997[45];
ap_reg_ppstg_tmp_178_reg_5997_pp7_it1[46] <= tmp_178_reg_5997[46];
ap_reg_ppstg_tmp_178_reg_5997_pp7_it1[47] <= tmp_178_reg_5997[47];
ap_reg_ppstg_tmp_178_reg_5997_pp7_it1[48] <= tmp_178_reg_5997[48];
ap_reg_ppstg_tmp_178_reg_5997_pp7_it1[49] <= tmp_178_reg_5997[49];
ap_reg_ppstg_tmp_178_reg_5997_pp7_it1[50] <= tmp_178_reg_5997[50];
ap_reg_ppstg_tmp_178_reg_5997_pp7_it1[51] <= tmp_178_reg_5997[51];
ap_reg_ppstg_tmp_178_reg_5997_pp7_it1[52] <= tmp_178_reg_5997[52];
ap_reg_ppstg_tmp_178_reg_5997_pp7_it1[53] <= tmp_178_reg_5997[53];
ap_reg_ppstg_tmp_178_reg_5997_pp7_it1[54] <= tmp_178_reg_5997[54];
ap_reg_ppstg_tmp_178_reg_5997_pp7_it1[55] <= tmp_178_reg_5997[55];
ap_reg_ppstg_tmp_178_reg_5997_pp7_it1[56] <= tmp_178_reg_5997[56];
ap_reg_ppstg_tmp_178_reg_5997_pp7_it1[57] <= tmp_178_reg_5997[57];
ap_reg_ppstg_tmp_178_reg_5997_pp7_it1[58] <= tmp_178_reg_5997[58];
ap_reg_ppstg_tmp_178_reg_5997_pp7_it1[59] <= tmp_178_reg_5997[59];
ap_reg_ppstg_tmp_178_reg_5997_pp7_it1[60] <= tmp_178_reg_5997[60];
ap_reg_ppstg_tmp_178_reg_5997_pp7_it1[61] <= tmp_178_reg_5997[61];
ap_reg_ppstg_tmp_178_reg_5997_pp7_it1[62] <= tmp_178_reg_5997[62];
ap_reg_ppstg_tmp_178_reg_5997_pp7_it1[63] <= tmp_178_reg_5997[63];
end
if ((ap_ST_pp7_stg1_fsm_32 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_182_reg_6017_pp7_it1 <= tmp_182_reg_6017;
end
if ((ap_ST_pp7_stg2_fsm_33 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_186_reg_6032_pp7_it1[2] <= tmp_186_reg_6032[2];
ap_reg_ppstg_tmp_186_reg_6032_pp7_it1[3] <= tmp_186_reg_6032[3];
ap_reg_ppstg_tmp_186_reg_6032_pp7_it1[4] <= tmp_186_reg_6032[4];
ap_reg_ppstg_tmp_186_reg_6032_pp7_it1[5] <= tmp_186_reg_6032[5];
ap_reg_ppstg_tmp_186_reg_6032_pp7_it1[6] <= tmp_186_reg_6032[6];
ap_reg_ppstg_tmp_186_reg_6032_pp7_it1[7] <= tmp_186_reg_6032[7];
ap_reg_ppstg_tmp_186_reg_6032_pp7_it1[8] <= tmp_186_reg_6032[8];
ap_reg_ppstg_tmp_186_reg_6032_pp7_it1[9] <= tmp_186_reg_6032[9];
ap_reg_ppstg_tmp_186_reg_6032_pp7_it1[10] <= tmp_186_reg_6032[10];
ap_reg_ppstg_tmp_186_reg_6032_pp7_it1[11] <= tmp_186_reg_6032[11];
ap_reg_ppstg_tmp_186_reg_6032_pp7_it1[12] <= tmp_186_reg_6032[12];
ap_reg_ppstg_tmp_186_reg_6032_pp7_it1[13] <= tmp_186_reg_6032[13];
ap_reg_ppstg_tmp_186_reg_6032_pp7_it1[14] <= tmp_186_reg_6032[14];
ap_reg_ppstg_tmp_186_reg_6032_pp7_it1[15] <= tmp_186_reg_6032[15];
ap_reg_ppstg_tmp_186_reg_6032_pp7_it1[16] <= tmp_186_reg_6032[16];
ap_reg_ppstg_tmp_186_reg_6032_pp7_it1[17] <= tmp_186_reg_6032[17];
ap_reg_ppstg_tmp_186_reg_6032_pp7_it1[18] <= tmp_186_reg_6032[18];
ap_reg_ppstg_tmp_186_reg_6032_pp7_it1[19] <= tmp_186_reg_6032[19];
ap_reg_ppstg_tmp_186_reg_6032_pp7_it1[20] <= tmp_186_reg_6032[20];
ap_reg_ppstg_tmp_186_reg_6032_pp7_it1[21] <= tmp_186_reg_6032[21];
ap_reg_ppstg_tmp_186_reg_6032_pp7_it1[22] <= tmp_186_reg_6032[22];
ap_reg_ppstg_tmp_186_reg_6032_pp7_it1[23] <= tmp_186_reg_6032[23];
ap_reg_ppstg_tmp_186_reg_6032_pp7_it1[24] <= tmp_186_reg_6032[24];
ap_reg_ppstg_tmp_186_reg_6032_pp7_it1[25] <= tmp_186_reg_6032[25];
ap_reg_ppstg_tmp_186_reg_6032_pp7_it1[26] <= tmp_186_reg_6032[26];
ap_reg_ppstg_tmp_186_reg_6032_pp7_it1[27] <= tmp_186_reg_6032[27];
ap_reg_ppstg_tmp_186_reg_6032_pp7_it1[28] <= tmp_186_reg_6032[28];
ap_reg_ppstg_tmp_186_reg_6032_pp7_it1[29] <= tmp_186_reg_6032[29];
ap_reg_ppstg_tmp_186_reg_6032_pp7_it1[30] <= tmp_186_reg_6032[30];
ap_reg_ppstg_tmp_186_reg_6032_pp7_it1[31] <= tmp_186_reg_6032[31];
ap_reg_ppstg_tmp_186_reg_6032_pp7_it1[32] <= tmp_186_reg_6032[32];
ap_reg_ppstg_tmp_186_reg_6032_pp7_it1[33] <= tmp_186_reg_6032[33];
ap_reg_ppstg_tmp_186_reg_6032_pp7_it1[34] <= tmp_186_reg_6032[34];
ap_reg_ppstg_tmp_186_reg_6032_pp7_it1[35] <= tmp_186_reg_6032[35];
ap_reg_ppstg_tmp_186_reg_6032_pp7_it1[36] <= tmp_186_reg_6032[36];
ap_reg_ppstg_tmp_186_reg_6032_pp7_it1[37] <= tmp_186_reg_6032[37];
ap_reg_ppstg_tmp_186_reg_6032_pp7_it1[38] <= tmp_186_reg_6032[38];
ap_reg_ppstg_tmp_186_reg_6032_pp7_it1[39] <= tmp_186_reg_6032[39];
ap_reg_ppstg_tmp_186_reg_6032_pp7_it1[40] <= tmp_186_reg_6032[40];
ap_reg_ppstg_tmp_186_reg_6032_pp7_it1[41] <= tmp_186_reg_6032[41];
ap_reg_ppstg_tmp_186_reg_6032_pp7_it1[42] <= tmp_186_reg_6032[42];
ap_reg_ppstg_tmp_186_reg_6032_pp7_it1[43] <= tmp_186_reg_6032[43];
ap_reg_ppstg_tmp_186_reg_6032_pp7_it1[44] <= tmp_186_reg_6032[44];
ap_reg_ppstg_tmp_186_reg_6032_pp7_it1[45] <= tmp_186_reg_6032[45];
ap_reg_ppstg_tmp_186_reg_6032_pp7_it1[46] <= tmp_186_reg_6032[46];
ap_reg_ppstg_tmp_186_reg_6032_pp7_it1[47] <= tmp_186_reg_6032[47];
ap_reg_ppstg_tmp_186_reg_6032_pp7_it1[48] <= tmp_186_reg_6032[48];
ap_reg_ppstg_tmp_186_reg_6032_pp7_it1[49] <= tmp_186_reg_6032[49];
ap_reg_ppstg_tmp_186_reg_6032_pp7_it1[50] <= tmp_186_reg_6032[50];
ap_reg_ppstg_tmp_186_reg_6032_pp7_it1[51] <= tmp_186_reg_6032[51];
ap_reg_ppstg_tmp_186_reg_6032_pp7_it1[52] <= tmp_186_reg_6032[52];
ap_reg_ppstg_tmp_186_reg_6032_pp7_it1[53] <= tmp_186_reg_6032[53];
ap_reg_ppstg_tmp_186_reg_6032_pp7_it1[54] <= tmp_186_reg_6032[54];
ap_reg_ppstg_tmp_186_reg_6032_pp7_it1[55] <= tmp_186_reg_6032[55];
ap_reg_ppstg_tmp_186_reg_6032_pp7_it1[56] <= tmp_186_reg_6032[56];
ap_reg_ppstg_tmp_186_reg_6032_pp7_it1[57] <= tmp_186_reg_6032[57];
ap_reg_ppstg_tmp_186_reg_6032_pp7_it1[58] <= tmp_186_reg_6032[58];
ap_reg_ppstg_tmp_186_reg_6032_pp7_it1[59] <= tmp_186_reg_6032[59];
ap_reg_ppstg_tmp_186_reg_6032_pp7_it1[60] <= tmp_186_reg_6032[60];
ap_reg_ppstg_tmp_186_reg_6032_pp7_it1[61] <= tmp_186_reg_6032[61];
ap_reg_ppstg_tmp_186_reg_6032_pp7_it1[62] <= tmp_186_reg_6032[62];
ap_reg_ppstg_tmp_186_reg_6032_pp7_it1[63] <= tmp_186_reg_6032[63];
end
if ((ap_ST_pp7_stg2_fsm_33 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_190_reg_6052_pp7_it1 <= tmp_190_reg_6052;
end
if ((ap_ST_pp7_stg3_fsm_34 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[1] <= tmp_192_reg_6067[1];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[2] <= tmp_192_reg_6067[2];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[3] <= tmp_192_reg_6067[3];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[4] <= tmp_192_reg_6067[4];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[5] <= tmp_192_reg_6067[5];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[6] <= tmp_192_reg_6067[6];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[7] <= tmp_192_reg_6067[7];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[8] <= tmp_192_reg_6067[8];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[9] <= tmp_192_reg_6067[9];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[10] <= tmp_192_reg_6067[10];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[11] <= tmp_192_reg_6067[11];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[12] <= tmp_192_reg_6067[12];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[13] <= tmp_192_reg_6067[13];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[14] <= tmp_192_reg_6067[14];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[15] <= tmp_192_reg_6067[15];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[16] <= tmp_192_reg_6067[16];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[17] <= tmp_192_reg_6067[17];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[18] <= tmp_192_reg_6067[18];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[19] <= tmp_192_reg_6067[19];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[20] <= tmp_192_reg_6067[20];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[21] <= tmp_192_reg_6067[21];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[22] <= tmp_192_reg_6067[22];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[23] <= tmp_192_reg_6067[23];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[24] <= tmp_192_reg_6067[24];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[25] <= tmp_192_reg_6067[25];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[26] <= tmp_192_reg_6067[26];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[27] <= tmp_192_reg_6067[27];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[28] <= tmp_192_reg_6067[28];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[29] <= tmp_192_reg_6067[29];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[30] <= tmp_192_reg_6067[30];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[31] <= tmp_192_reg_6067[31];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[32] <= tmp_192_reg_6067[32];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[33] <= tmp_192_reg_6067[33];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[34] <= tmp_192_reg_6067[34];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[35] <= tmp_192_reg_6067[35];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[36] <= tmp_192_reg_6067[36];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[37] <= tmp_192_reg_6067[37];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[38] <= tmp_192_reg_6067[38];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[39] <= tmp_192_reg_6067[39];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[40] <= tmp_192_reg_6067[40];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[41] <= tmp_192_reg_6067[41];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[42] <= tmp_192_reg_6067[42];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[43] <= tmp_192_reg_6067[43];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[44] <= tmp_192_reg_6067[44];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[45] <= tmp_192_reg_6067[45];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[46] <= tmp_192_reg_6067[46];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[47] <= tmp_192_reg_6067[47];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[48] <= tmp_192_reg_6067[48];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[49] <= tmp_192_reg_6067[49];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[50] <= tmp_192_reg_6067[50];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[51] <= tmp_192_reg_6067[51];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[52] <= tmp_192_reg_6067[52];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[53] <= tmp_192_reg_6067[53];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[54] <= tmp_192_reg_6067[54];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[55] <= tmp_192_reg_6067[55];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[56] <= tmp_192_reg_6067[56];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[57] <= tmp_192_reg_6067[57];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[58] <= tmp_192_reg_6067[58];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[59] <= tmp_192_reg_6067[59];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[60] <= tmp_192_reg_6067[60];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[61] <= tmp_192_reg_6067[61];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[62] <= tmp_192_reg_6067[62];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[63] <= tmp_192_reg_6067[63];
end
if ((ap_ST_pp7_stg3_fsm_34 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_192_reg_6067_pp7_it2[1] <= ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[1];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it2[2] <= ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[2];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it2[3] <= ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[3];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it2[4] <= ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[4];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it2[5] <= ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[5];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it2[6] <= ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[6];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it2[7] <= ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[7];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it2[8] <= ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[8];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it2[9] <= ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[9];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it2[10] <= ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[10];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it2[11] <= ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[11];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it2[12] <= ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[12];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it2[13] <= ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[13];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it2[14] <= ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[14];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it2[15] <= ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[15];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it2[16] <= ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[16];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it2[17] <= ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[17];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it2[18] <= ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[18];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it2[19] <= ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[19];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it2[20] <= ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[20];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it2[21] <= ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[21];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it2[22] <= ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[22];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it2[23] <= ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[23];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it2[24] <= ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[24];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it2[25] <= ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[25];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it2[26] <= ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[26];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it2[27] <= ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[27];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it2[28] <= ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[28];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it2[29] <= ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[29];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it2[30] <= ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[30];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it2[31] <= ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[31];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it2[32] <= ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[32];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it2[33] <= ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[33];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it2[34] <= ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[34];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it2[35] <= ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[35];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it2[36] <= ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[36];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it2[37] <= ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[37];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it2[38] <= ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[38];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it2[39] <= ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[39];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it2[40] <= ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[40];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it2[41] <= ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[41];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it2[42] <= ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[42];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it2[43] <= ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[43];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it2[44] <= ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[44];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it2[45] <= ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[45];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it2[46] <= ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[46];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it2[47] <= ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[47];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it2[48] <= ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[48];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it2[49] <= ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[49];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it2[50] <= ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[50];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it2[51] <= ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[51];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it2[52] <= ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[52];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it2[53] <= ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[53];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it2[54] <= ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[54];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it2[55] <= ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[55];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it2[56] <= ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[56];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it2[57] <= ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[57];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it2[58] <= ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[58];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it2[59] <= ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[59];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it2[60] <= ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[60];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it2[61] <= ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[61];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it2[62] <= ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[62];
ap_reg_ppstg_tmp_192_reg_6067_pp7_it2[63] <= ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[63];
end
if ((ap_ST_pp7_stg3_fsm_34 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_194_reg_6107_pp7_it2 <= tmp_194_reg_6107;
end
if ((ap_ST_pp7_stg4_fsm_35 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_197_reg_6122_pp7_it2[3] <= tmp_197_reg_6122[3];
ap_reg_ppstg_tmp_197_reg_6122_pp7_it2[4] <= tmp_197_reg_6122[4];
ap_reg_ppstg_tmp_197_reg_6122_pp7_it2[5] <= tmp_197_reg_6122[5];
ap_reg_ppstg_tmp_197_reg_6122_pp7_it2[6] <= tmp_197_reg_6122[6];
ap_reg_ppstg_tmp_197_reg_6122_pp7_it2[7] <= tmp_197_reg_6122[7];
ap_reg_ppstg_tmp_197_reg_6122_pp7_it2[8] <= tmp_197_reg_6122[8];
ap_reg_ppstg_tmp_197_reg_6122_pp7_it2[9] <= tmp_197_reg_6122[9];
ap_reg_ppstg_tmp_197_reg_6122_pp7_it2[10] <= tmp_197_reg_6122[10];
ap_reg_ppstg_tmp_197_reg_6122_pp7_it2[11] <= tmp_197_reg_6122[11];
ap_reg_ppstg_tmp_197_reg_6122_pp7_it2[12] <= tmp_197_reg_6122[12];
ap_reg_ppstg_tmp_197_reg_6122_pp7_it2[13] <= tmp_197_reg_6122[13];
ap_reg_ppstg_tmp_197_reg_6122_pp7_it2[14] <= tmp_197_reg_6122[14];
ap_reg_ppstg_tmp_197_reg_6122_pp7_it2[15] <= tmp_197_reg_6122[15];
ap_reg_ppstg_tmp_197_reg_6122_pp7_it2[16] <= tmp_197_reg_6122[16];
ap_reg_ppstg_tmp_197_reg_6122_pp7_it2[17] <= tmp_197_reg_6122[17];
ap_reg_ppstg_tmp_197_reg_6122_pp7_it2[18] <= tmp_197_reg_6122[18];
ap_reg_ppstg_tmp_197_reg_6122_pp7_it2[19] <= tmp_197_reg_6122[19];
ap_reg_ppstg_tmp_197_reg_6122_pp7_it2[20] <= tmp_197_reg_6122[20];
ap_reg_ppstg_tmp_197_reg_6122_pp7_it2[21] <= tmp_197_reg_6122[21];
ap_reg_ppstg_tmp_197_reg_6122_pp7_it2[22] <= tmp_197_reg_6122[22];
ap_reg_ppstg_tmp_197_reg_6122_pp7_it2[23] <= tmp_197_reg_6122[23];
ap_reg_ppstg_tmp_197_reg_6122_pp7_it2[24] <= tmp_197_reg_6122[24];
ap_reg_ppstg_tmp_197_reg_6122_pp7_it2[25] <= tmp_197_reg_6122[25];
ap_reg_ppstg_tmp_197_reg_6122_pp7_it2[26] <= tmp_197_reg_6122[26];
ap_reg_ppstg_tmp_197_reg_6122_pp7_it2[27] <= tmp_197_reg_6122[27];
ap_reg_ppstg_tmp_197_reg_6122_pp7_it2[28] <= tmp_197_reg_6122[28];
ap_reg_ppstg_tmp_197_reg_6122_pp7_it2[29] <= tmp_197_reg_6122[29];
ap_reg_ppstg_tmp_197_reg_6122_pp7_it2[30] <= tmp_197_reg_6122[30];
ap_reg_ppstg_tmp_197_reg_6122_pp7_it2[31] <= tmp_197_reg_6122[31];
ap_reg_ppstg_tmp_197_reg_6122_pp7_it2[32] <= tmp_197_reg_6122[32];
ap_reg_ppstg_tmp_197_reg_6122_pp7_it2[33] <= tmp_197_reg_6122[33];
ap_reg_ppstg_tmp_197_reg_6122_pp7_it2[34] <= tmp_197_reg_6122[34];
ap_reg_ppstg_tmp_197_reg_6122_pp7_it2[35] <= tmp_197_reg_6122[35];
ap_reg_ppstg_tmp_197_reg_6122_pp7_it2[36] <= tmp_197_reg_6122[36];
ap_reg_ppstg_tmp_197_reg_6122_pp7_it2[37] <= tmp_197_reg_6122[37];
ap_reg_ppstg_tmp_197_reg_6122_pp7_it2[38] <= tmp_197_reg_6122[38];
ap_reg_ppstg_tmp_197_reg_6122_pp7_it2[39] <= tmp_197_reg_6122[39];
ap_reg_ppstg_tmp_197_reg_6122_pp7_it2[40] <= tmp_197_reg_6122[40];
ap_reg_ppstg_tmp_197_reg_6122_pp7_it2[41] <= tmp_197_reg_6122[41];
ap_reg_ppstg_tmp_197_reg_6122_pp7_it2[42] <= tmp_197_reg_6122[42];
ap_reg_ppstg_tmp_197_reg_6122_pp7_it2[43] <= tmp_197_reg_6122[43];
ap_reg_ppstg_tmp_197_reg_6122_pp7_it2[44] <= tmp_197_reg_6122[44];
ap_reg_ppstg_tmp_197_reg_6122_pp7_it2[45] <= tmp_197_reg_6122[45];
ap_reg_ppstg_tmp_197_reg_6122_pp7_it2[46] <= tmp_197_reg_6122[46];
ap_reg_ppstg_tmp_197_reg_6122_pp7_it2[47] <= tmp_197_reg_6122[47];
ap_reg_ppstg_tmp_197_reg_6122_pp7_it2[48] <= tmp_197_reg_6122[48];
ap_reg_ppstg_tmp_197_reg_6122_pp7_it2[49] <= tmp_197_reg_6122[49];
ap_reg_ppstg_tmp_197_reg_6122_pp7_it2[50] <= tmp_197_reg_6122[50];
ap_reg_ppstg_tmp_197_reg_6122_pp7_it2[51] <= tmp_197_reg_6122[51];
ap_reg_ppstg_tmp_197_reg_6122_pp7_it2[52] <= tmp_197_reg_6122[52];
ap_reg_ppstg_tmp_197_reg_6122_pp7_it2[53] <= tmp_197_reg_6122[53];
ap_reg_ppstg_tmp_197_reg_6122_pp7_it2[54] <= tmp_197_reg_6122[54];
ap_reg_ppstg_tmp_197_reg_6122_pp7_it2[55] <= tmp_197_reg_6122[55];
ap_reg_ppstg_tmp_197_reg_6122_pp7_it2[56] <= tmp_197_reg_6122[56];
ap_reg_ppstg_tmp_197_reg_6122_pp7_it2[57] <= tmp_197_reg_6122[57];
ap_reg_ppstg_tmp_197_reg_6122_pp7_it2[58] <= tmp_197_reg_6122[58];
ap_reg_ppstg_tmp_197_reg_6122_pp7_it2[59] <= tmp_197_reg_6122[59];
ap_reg_ppstg_tmp_197_reg_6122_pp7_it2[60] <= tmp_197_reg_6122[60];
ap_reg_ppstg_tmp_197_reg_6122_pp7_it2[61] <= tmp_197_reg_6122[61];
ap_reg_ppstg_tmp_197_reg_6122_pp7_it2[62] <= tmp_197_reg_6122[62];
ap_reg_ppstg_tmp_197_reg_6122_pp7_it2[63] <= tmp_197_reg_6122[63];
end
if ((ap_ST_pp1_stg1_fsm_5 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_20_reg_5287_pp1_it1[0] <= tmp_20_reg_5287[0];
ap_reg_ppstg_tmp_20_reg_5287_pp1_it1[1] <= tmp_20_reg_5287[1];
ap_reg_ppstg_tmp_20_reg_5287_pp1_it1[2] <= tmp_20_reg_5287[2];
ap_reg_ppstg_tmp_20_reg_5287_pp1_it1[3] <= tmp_20_reg_5287[3];
ap_reg_ppstg_tmp_20_reg_5287_pp1_it1[4] <= tmp_20_reg_5287[4];
ap_reg_ppstg_tmp_20_reg_5287_pp1_it1[5] <= tmp_20_reg_5287[5];
ap_reg_ppstg_tmp_20_reg_5287_pp1_it1[6] <= tmp_20_reg_5287[6];
ap_reg_ppstg_tmp_20_reg_5287_pp1_it1[7] <= tmp_20_reg_5287[7];
ap_reg_ppstg_tmp_20_reg_5287_pp1_it1[8] <= tmp_20_reg_5287[8];
ap_reg_ppstg_tmp_20_reg_5287_pp1_it1[9] <= tmp_20_reg_5287[9];
ap_reg_ppstg_tmp_20_reg_5287_pp1_it1[10] <= tmp_20_reg_5287[10];
ap_reg_ppstg_tmp_20_reg_5287_pp1_it1[11] <= tmp_20_reg_5287[11];
ap_reg_ppstg_tmp_20_reg_5287_pp1_it1[12] <= tmp_20_reg_5287[12];
ap_reg_ppstg_tmp_20_reg_5287_pp1_it1[13] <= tmp_20_reg_5287[13];
end
if ((ap_ST_pp1_stg2_fsm_6 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_28_reg_5332_pp1_it1[0] <= tmp_28_reg_5332[0];
ap_reg_ppstg_tmp_28_reg_5332_pp1_it1[1] <= tmp_28_reg_5332[1];
ap_reg_ppstg_tmp_28_reg_5332_pp1_it1[2] <= tmp_28_reg_5332[2];
ap_reg_ppstg_tmp_28_reg_5332_pp1_it1[3] <= tmp_28_reg_5332[3];
ap_reg_ppstg_tmp_28_reg_5332_pp1_it1[4] <= tmp_28_reg_5332[4];
ap_reg_ppstg_tmp_28_reg_5332_pp1_it1[5] <= tmp_28_reg_5332[5];
ap_reg_ppstg_tmp_28_reg_5332_pp1_it1[6] <= tmp_28_reg_5332[6];
ap_reg_ppstg_tmp_28_reg_5332_pp1_it1[7] <= tmp_28_reg_5332[7];
ap_reg_ppstg_tmp_28_reg_5332_pp1_it1[8] <= tmp_28_reg_5332[8];
ap_reg_ppstg_tmp_28_reg_5332_pp1_it1[9] <= tmp_28_reg_5332[9];
ap_reg_ppstg_tmp_28_reg_5332_pp1_it1[10] <= tmp_28_reg_5332[10];
ap_reg_ppstg_tmp_28_reg_5332_pp1_it1[11] <= tmp_28_reg_5332[11];
ap_reg_ppstg_tmp_28_reg_5332_pp1_it1[12] <= tmp_28_reg_5332[12];
ap_reg_ppstg_tmp_28_reg_5332_pp1_it1[13] <= tmp_28_reg_5332[13];
end
if ((ap_ST_pp1_stg2_fsm_6 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_36_reg_5347_pp1_it1[0] <= tmp_36_reg_5347[0];
ap_reg_ppstg_tmp_36_reg_5347_pp1_it1[1] <= tmp_36_reg_5347[1];
ap_reg_ppstg_tmp_36_reg_5347_pp1_it1[2] <= tmp_36_reg_5347[2];
ap_reg_ppstg_tmp_36_reg_5347_pp1_it1[3] <= tmp_36_reg_5347[3];
ap_reg_ppstg_tmp_36_reg_5347_pp1_it1[4] <= tmp_36_reg_5347[4];
ap_reg_ppstg_tmp_36_reg_5347_pp1_it1[5] <= tmp_36_reg_5347[5];
ap_reg_ppstg_tmp_36_reg_5347_pp1_it1[6] <= tmp_36_reg_5347[6];
ap_reg_ppstg_tmp_36_reg_5347_pp1_it1[7] <= tmp_36_reg_5347[7];
ap_reg_ppstg_tmp_36_reg_5347_pp1_it1[8] <= tmp_36_reg_5347[8];
ap_reg_ppstg_tmp_36_reg_5347_pp1_it1[9] <= tmp_36_reg_5347[9];
ap_reg_ppstg_tmp_36_reg_5347_pp1_it1[10] <= tmp_36_reg_5347[10];
ap_reg_ppstg_tmp_36_reg_5347_pp1_it1[11] <= tmp_36_reg_5347[11];
ap_reg_ppstg_tmp_36_reg_5347_pp1_it1[12] <= tmp_36_reg_5347[12];
ap_reg_ppstg_tmp_36_reg_5347_pp1_it1[13] <= tmp_36_reg_5347[13];
end
if ((ap_ST_pp1_stg3_fsm_7 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_44_reg_5367_pp1_it1[0] <= tmp_44_reg_5367[0];
ap_reg_ppstg_tmp_44_reg_5367_pp1_it1[1] <= tmp_44_reg_5367[1];
ap_reg_ppstg_tmp_44_reg_5367_pp1_it1[2] <= tmp_44_reg_5367[2];
ap_reg_ppstg_tmp_44_reg_5367_pp1_it1[3] <= tmp_44_reg_5367[3];
ap_reg_ppstg_tmp_44_reg_5367_pp1_it1[4] <= tmp_44_reg_5367[4];
ap_reg_ppstg_tmp_44_reg_5367_pp1_it1[5] <= tmp_44_reg_5367[5];
ap_reg_ppstg_tmp_44_reg_5367_pp1_it1[6] <= tmp_44_reg_5367[6];
ap_reg_ppstg_tmp_44_reg_5367_pp1_it1[7] <= tmp_44_reg_5367[7];
ap_reg_ppstg_tmp_44_reg_5367_pp1_it1[8] <= tmp_44_reg_5367[8];
ap_reg_ppstg_tmp_44_reg_5367_pp1_it1[9] <= tmp_44_reg_5367[9];
ap_reg_ppstg_tmp_44_reg_5367_pp1_it1[10] <= tmp_44_reg_5367[10];
ap_reg_ppstg_tmp_44_reg_5367_pp1_it1[11] <= tmp_44_reg_5367[11];
ap_reg_ppstg_tmp_44_reg_5367_pp1_it1[12] <= tmp_44_reg_5367[12];
ap_reg_ppstg_tmp_44_reg_5367_pp1_it1[13] <= tmp_44_reg_5367[13];
end
if ((ap_ST_pp1_stg3_fsm_7 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_44_reg_5367_pp1_it2[0] <= ap_reg_ppstg_tmp_44_reg_5367_pp1_it1[0];
ap_reg_ppstg_tmp_44_reg_5367_pp1_it2[1] <= ap_reg_ppstg_tmp_44_reg_5367_pp1_it1[1];
ap_reg_ppstg_tmp_44_reg_5367_pp1_it2[2] <= ap_reg_ppstg_tmp_44_reg_5367_pp1_it1[2];
ap_reg_ppstg_tmp_44_reg_5367_pp1_it2[3] <= ap_reg_ppstg_tmp_44_reg_5367_pp1_it1[3];
ap_reg_ppstg_tmp_44_reg_5367_pp1_it2[4] <= ap_reg_ppstg_tmp_44_reg_5367_pp1_it1[4];
ap_reg_ppstg_tmp_44_reg_5367_pp1_it2[5] <= ap_reg_ppstg_tmp_44_reg_5367_pp1_it1[5];
ap_reg_ppstg_tmp_44_reg_5367_pp1_it2[6] <= ap_reg_ppstg_tmp_44_reg_5367_pp1_it1[6];
ap_reg_ppstg_tmp_44_reg_5367_pp1_it2[7] <= ap_reg_ppstg_tmp_44_reg_5367_pp1_it1[7];
ap_reg_ppstg_tmp_44_reg_5367_pp1_it2[8] <= ap_reg_ppstg_tmp_44_reg_5367_pp1_it1[8];
ap_reg_ppstg_tmp_44_reg_5367_pp1_it2[9] <= ap_reg_ppstg_tmp_44_reg_5367_pp1_it1[9];
ap_reg_ppstg_tmp_44_reg_5367_pp1_it2[10] <= ap_reg_ppstg_tmp_44_reg_5367_pp1_it1[10];
ap_reg_ppstg_tmp_44_reg_5367_pp1_it2[11] <= ap_reg_ppstg_tmp_44_reg_5367_pp1_it1[11];
ap_reg_ppstg_tmp_44_reg_5367_pp1_it2[12] <= ap_reg_ppstg_tmp_44_reg_5367_pp1_it1[12];
ap_reg_ppstg_tmp_44_reg_5367_pp1_it2[13] <= ap_reg_ppstg_tmp_44_reg_5367_pp1_it1[13];
end
if ((ap_ST_pp1_stg3_fsm_7 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_47_reg_5407_pp1_it2[0] <= tmp_47_reg_5407[0];
ap_reg_ppstg_tmp_47_reg_5407_pp1_it2[1] <= tmp_47_reg_5407[1];
ap_reg_ppstg_tmp_47_reg_5407_pp1_it2[2] <= tmp_47_reg_5407[2];
ap_reg_ppstg_tmp_47_reg_5407_pp1_it2[3] <= tmp_47_reg_5407[3];
ap_reg_ppstg_tmp_47_reg_5407_pp1_it2[4] <= tmp_47_reg_5407[4];
ap_reg_ppstg_tmp_47_reg_5407_pp1_it2[5] <= tmp_47_reg_5407[5];
ap_reg_ppstg_tmp_47_reg_5407_pp1_it2[6] <= tmp_47_reg_5407[6];
ap_reg_ppstg_tmp_47_reg_5407_pp1_it2[7] <= tmp_47_reg_5407[7];
ap_reg_ppstg_tmp_47_reg_5407_pp1_it2[8] <= tmp_47_reg_5407[8];
ap_reg_ppstg_tmp_47_reg_5407_pp1_it2[9] <= tmp_47_reg_5407[9];
ap_reg_ppstg_tmp_47_reg_5407_pp1_it2[10] <= tmp_47_reg_5407[10];
ap_reg_ppstg_tmp_47_reg_5407_pp1_it2[11] <= tmp_47_reg_5407[11];
ap_reg_ppstg_tmp_47_reg_5407_pp1_it2[12] <= tmp_47_reg_5407[12];
ap_reg_ppstg_tmp_47_reg_5407_pp1_it2[13] <= tmp_47_reg_5407[13];
end
if ((ap_ST_pp1_stg4_fsm_8 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_51_reg_5417_pp1_it2[0] <= tmp_51_reg_5417[0];
ap_reg_ppstg_tmp_51_reg_5417_pp1_it2[1] <= tmp_51_reg_5417[1];
ap_reg_ppstg_tmp_51_reg_5417_pp1_it2[2] <= tmp_51_reg_5417[2];
ap_reg_ppstg_tmp_51_reg_5417_pp1_it2[3] <= tmp_51_reg_5417[3];
ap_reg_ppstg_tmp_51_reg_5417_pp1_it2[4] <= tmp_51_reg_5417[4];
ap_reg_ppstg_tmp_51_reg_5417_pp1_it2[5] <= tmp_51_reg_5417[5];
ap_reg_ppstg_tmp_51_reg_5417_pp1_it2[6] <= tmp_51_reg_5417[6];
ap_reg_ppstg_tmp_51_reg_5417_pp1_it2[7] <= tmp_51_reg_5417[7];
ap_reg_ppstg_tmp_51_reg_5417_pp1_it2[8] <= tmp_51_reg_5417[8];
ap_reg_ppstg_tmp_51_reg_5417_pp1_it2[9] <= tmp_51_reg_5417[9];
ap_reg_ppstg_tmp_51_reg_5417_pp1_it2[10] <= tmp_51_reg_5417[10];
ap_reg_ppstg_tmp_51_reg_5417_pp1_it2[11] <= tmp_51_reg_5417[11];
ap_reg_ppstg_tmp_51_reg_5417_pp1_it2[12] <= tmp_51_reg_5417[12];
ap_reg_ppstg_tmp_51_reg_5417_pp1_it2[13] <= tmp_51_reg_5417[13];
end
if ((ap_ST_pp2_stg0_fsm_12 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_59_reg_5436_pp2_it1[0] <= tmp_59_reg_5436[0];
ap_reg_ppstg_tmp_59_reg_5436_pp2_it1[1] <= tmp_59_reg_5436[1];
ap_reg_ppstg_tmp_59_reg_5436_pp2_it1[2] <= tmp_59_reg_5436[2];
ap_reg_ppstg_tmp_59_reg_5436_pp2_it1[3] <= tmp_59_reg_5436[3];
ap_reg_ppstg_tmp_59_reg_5436_pp2_it1[4] <= tmp_59_reg_5436[4];
ap_reg_ppstg_tmp_59_reg_5436_pp2_it1[5] <= tmp_59_reg_5436[5];
ap_reg_ppstg_tmp_59_reg_5436_pp2_it1[6] <= tmp_59_reg_5436[6];
ap_reg_ppstg_tmp_59_reg_5436_pp2_it1[7] <= tmp_59_reg_5436[7];
ap_reg_ppstg_tmp_59_reg_5436_pp2_it1[8] <= tmp_59_reg_5436[8];
ap_reg_ppstg_tmp_59_reg_5436_pp2_it1[9] <= tmp_59_reg_5436[9];
ap_reg_ppstg_tmp_59_reg_5436_pp2_it1[10] <= tmp_59_reg_5436[10];
ap_reg_ppstg_tmp_59_reg_5436_pp2_it1[11] <= tmp_59_reg_5436[11];
ap_reg_ppstg_tmp_59_reg_5436_pp2_it1[12] <= tmp_59_reg_5436[12];
end
if ((ap_ST_pp2_stg0_fsm_12 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_59_reg_5436_pp2_it2[0] <= ap_reg_ppstg_tmp_59_reg_5436_pp2_it1[0];
ap_reg_ppstg_tmp_59_reg_5436_pp2_it2[1] <= ap_reg_ppstg_tmp_59_reg_5436_pp2_it1[1];
ap_reg_ppstg_tmp_59_reg_5436_pp2_it2[2] <= ap_reg_ppstg_tmp_59_reg_5436_pp2_it1[2];
ap_reg_ppstg_tmp_59_reg_5436_pp2_it2[3] <= ap_reg_ppstg_tmp_59_reg_5436_pp2_it1[3];
ap_reg_ppstg_tmp_59_reg_5436_pp2_it2[4] <= ap_reg_ppstg_tmp_59_reg_5436_pp2_it1[4];
ap_reg_ppstg_tmp_59_reg_5436_pp2_it2[5] <= ap_reg_ppstg_tmp_59_reg_5436_pp2_it1[5];
ap_reg_ppstg_tmp_59_reg_5436_pp2_it2[6] <= ap_reg_ppstg_tmp_59_reg_5436_pp2_it1[6];
ap_reg_ppstg_tmp_59_reg_5436_pp2_it2[7] <= ap_reg_ppstg_tmp_59_reg_5436_pp2_it1[7];
ap_reg_ppstg_tmp_59_reg_5436_pp2_it2[8] <= ap_reg_ppstg_tmp_59_reg_5436_pp2_it1[8];
ap_reg_ppstg_tmp_59_reg_5436_pp2_it2[9] <= ap_reg_ppstg_tmp_59_reg_5436_pp2_it1[9];
ap_reg_ppstg_tmp_59_reg_5436_pp2_it2[10] <= ap_reg_ppstg_tmp_59_reg_5436_pp2_it1[10];
ap_reg_ppstg_tmp_59_reg_5436_pp2_it2[11] <= ap_reg_ppstg_tmp_59_reg_5436_pp2_it1[11];
ap_reg_ppstg_tmp_59_reg_5436_pp2_it2[12] <= ap_reg_ppstg_tmp_59_reg_5436_pp2_it1[12];
end
if ((ap_ST_pp2_stg0_fsm_12 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_59_reg_5436_pp2_it3[0] <= ap_reg_ppstg_tmp_59_reg_5436_pp2_it2[0];
ap_reg_ppstg_tmp_59_reg_5436_pp2_it3[1] <= ap_reg_ppstg_tmp_59_reg_5436_pp2_it2[1];
ap_reg_ppstg_tmp_59_reg_5436_pp2_it3[2] <= ap_reg_ppstg_tmp_59_reg_5436_pp2_it2[2];
ap_reg_ppstg_tmp_59_reg_5436_pp2_it3[3] <= ap_reg_ppstg_tmp_59_reg_5436_pp2_it2[3];
ap_reg_ppstg_tmp_59_reg_5436_pp2_it3[4] <= ap_reg_ppstg_tmp_59_reg_5436_pp2_it2[4];
ap_reg_ppstg_tmp_59_reg_5436_pp2_it3[5] <= ap_reg_ppstg_tmp_59_reg_5436_pp2_it2[5];
ap_reg_ppstg_tmp_59_reg_5436_pp2_it3[6] <= ap_reg_ppstg_tmp_59_reg_5436_pp2_it2[6];
ap_reg_ppstg_tmp_59_reg_5436_pp2_it3[7] <= ap_reg_ppstg_tmp_59_reg_5436_pp2_it2[7];
ap_reg_ppstg_tmp_59_reg_5436_pp2_it3[8] <= ap_reg_ppstg_tmp_59_reg_5436_pp2_it2[8];
ap_reg_ppstg_tmp_59_reg_5436_pp2_it3[9] <= ap_reg_ppstg_tmp_59_reg_5436_pp2_it2[9];
ap_reg_ppstg_tmp_59_reg_5436_pp2_it3[10] <= ap_reg_ppstg_tmp_59_reg_5436_pp2_it2[10];
ap_reg_ppstg_tmp_59_reg_5436_pp2_it3[11] <= ap_reg_ppstg_tmp_59_reg_5436_pp2_it2[11];
ap_reg_ppstg_tmp_59_reg_5436_pp2_it3[12] <= ap_reg_ppstg_tmp_59_reg_5436_pp2_it2[12];
end
if ((ap_ST_pp2_stg0_fsm_12 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_59_reg_5436_pp2_it4[0] <= ap_reg_ppstg_tmp_59_reg_5436_pp2_it3[0];
ap_reg_ppstg_tmp_59_reg_5436_pp2_it4[1] <= ap_reg_ppstg_tmp_59_reg_5436_pp2_it3[1];
ap_reg_ppstg_tmp_59_reg_5436_pp2_it4[2] <= ap_reg_ppstg_tmp_59_reg_5436_pp2_it3[2];
ap_reg_ppstg_tmp_59_reg_5436_pp2_it4[3] <= ap_reg_ppstg_tmp_59_reg_5436_pp2_it3[3];
ap_reg_ppstg_tmp_59_reg_5436_pp2_it4[4] <= ap_reg_ppstg_tmp_59_reg_5436_pp2_it3[4];
ap_reg_ppstg_tmp_59_reg_5436_pp2_it4[5] <= ap_reg_ppstg_tmp_59_reg_5436_pp2_it3[5];
ap_reg_ppstg_tmp_59_reg_5436_pp2_it4[6] <= ap_reg_ppstg_tmp_59_reg_5436_pp2_it3[6];
ap_reg_ppstg_tmp_59_reg_5436_pp2_it4[7] <= ap_reg_ppstg_tmp_59_reg_5436_pp2_it3[7];
ap_reg_ppstg_tmp_59_reg_5436_pp2_it4[8] <= ap_reg_ppstg_tmp_59_reg_5436_pp2_it3[8];
ap_reg_ppstg_tmp_59_reg_5436_pp2_it4[9] <= ap_reg_ppstg_tmp_59_reg_5436_pp2_it3[9];
ap_reg_ppstg_tmp_59_reg_5436_pp2_it4[10] <= ap_reg_ppstg_tmp_59_reg_5436_pp2_it3[10];
ap_reg_ppstg_tmp_59_reg_5436_pp2_it4[11] <= ap_reg_ppstg_tmp_59_reg_5436_pp2_it3[11];
ap_reg_ppstg_tmp_59_reg_5436_pp2_it4[12] <= ap_reg_ppstg_tmp_59_reg_5436_pp2_it3[12];
end
if ((ap_ST_pp2_stg0_fsm_12 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_59_reg_5436_pp2_it5[0] <= ap_reg_ppstg_tmp_59_reg_5436_pp2_it4[0];
ap_reg_ppstg_tmp_59_reg_5436_pp2_it5[1] <= ap_reg_ppstg_tmp_59_reg_5436_pp2_it4[1];
ap_reg_ppstg_tmp_59_reg_5436_pp2_it5[2] <= ap_reg_ppstg_tmp_59_reg_5436_pp2_it4[2];
ap_reg_ppstg_tmp_59_reg_5436_pp2_it5[3] <= ap_reg_ppstg_tmp_59_reg_5436_pp2_it4[3];
ap_reg_ppstg_tmp_59_reg_5436_pp2_it5[4] <= ap_reg_ppstg_tmp_59_reg_5436_pp2_it4[4];
ap_reg_ppstg_tmp_59_reg_5436_pp2_it5[5] <= ap_reg_ppstg_tmp_59_reg_5436_pp2_it4[5];
ap_reg_ppstg_tmp_59_reg_5436_pp2_it5[6] <= ap_reg_ppstg_tmp_59_reg_5436_pp2_it4[6];
ap_reg_ppstg_tmp_59_reg_5436_pp2_it5[7] <= ap_reg_ppstg_tmp_59_reg_5436_pp2_it4[7];
ap_reg_ppstg_tmp_59_reg_5436_pp2_it5[8] <= ap_reg_ppstg_tmp_59_reg_5436_pp2_it4[8];
ap_reg_ppstg_tmp_59_reg_5436_pp2_it5[9] <= ap_reg_ppstg_tmp_59_reg_5436_pp2_it4[9];
ap_reg_ppstg_tmp_59_reg_5436_pp2_it5[10] <= ap_reg_ppstg_tmp_59_reg_5436_pp2_it4[10];
ap_reg_ppstg_tmp_59_reg_5436_pp2_it5[11] <= ap_reg_ppstg_tmp_59_reg_5436_pp2_it4[11];
ap_reg_ppstg_tmp_59_reg_5436_pp2_it5[12] <= ap_reg_ppstg_tmp_59_reg_5436_pp2_it4[12];
end
if ((ap_ST_pp3_stg0_fsm_13 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_67_reg_5488_pp3_it1 <= tmp_67_reg_5488;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_6_reg_5180_pp0_it1[6] <= tmp_6_reg_5180[6];
ap_reg_ppstg_tmp_6_reg_5180_pp0_it1[7] <= tmp_6_reg_5180[7];
ap_reg_ppstg_tmp_6_reg_5180_pp0_it1[8] <= tmp_6_reg_5180[8];
ap_reg_ppstg_tmp_6_reg_5180_pp0_it1[9] <= tmp_6_reg_5180[9];
ap_reg_ppstg_tmp_6_reg_5180_pp0_it1[10] <= tmp_6_reg_5180[10];
ap_reg_ppstg_tmp_6_reg_5180_pp0_it1[11] <= tmp_6_reg_5180[11];
ap_reg_ppstg_tmp_6_reg_5180_pp0_it1[12] <= tmp_6_reg_5180[12];
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_6_reg_5180_pp0_it2[6] <= ap_reg_ppstg_tmp_6_reg_5180_pp0_it1[6];
ap_reg_ppstg_tmp_6_reg_5180_pp0_it2[7] <= ap_reg_ppstg_tmp_6_reg_5180_pp0_it1[7];
ap_reg_ppstg_tmp_6_reg_5180_pp0_it2[8] <= ap_reg_ppstg_tmp_6_reg_5180_pp0_it1[8];
ap_reg_ppstg_tmp_6_reg_5180_pp0_it2[9] <= ap_reg_ppstg_tmp_6_reg_5180_pp0_it1[9];
ap_reg_ppstg_tmp_6_reg_5180_pp0_it2[10] <= ap_reg_ppstg_tmp_6_reg_5180_pp0_it1[10];
ap_reg_ppstg_tmp_6_reg_5180_pp0_it2[11] <= ap_reg_ppstg_tmp_6_reg_5180_pp0_it1[11];
ap_reg_ppstg_tmp_6_reg_5180_pp0_it2[12] <= ap_reg_ppstg_tmp_6_reg_5180_pp0_it1[12];
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_6_reg_5180_pp0_it3[6] <= ap_reg_ppstg_tmp_6_reg_5180_pp0_it2[6];
ap_reg_ppstg_tmp_6_reg_5180_pp0_it3[7] <= ap_reg_ppstg_tmp_6_reg_5180_pp0_it2[7];
ap_reg_ppstg_tmp_6_reg_5180_pp0_it3[8] <= ap_reg_ppstg_tmp_6_reg_5180_pp0_it2[8];
ap_reg_ppstg_tmp_6_reg_5180_pp0_it3[9] <= ap_reg_ppstg_tmp_6_reg_5180_pp0_it2[9];
ap_reg_ppstg_tmp_6_reg_5180_pp0_it3[10] <= ap_reg_ppstg_tmp_6_reg_5180_pp0_it2[10];
ap_reg_ppstg_tmp_6_reg_5180_pp0_it3[11] <= ap_reg_ppstg_tmp_6_reg_5180_pp0_it2[11];
ap_reg_ppstg_tmp_6_reg_5180_pp0_it3[12] <= ap_reg_ppstg_tmp_6_reg_5180_pp0_it2[12];
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_6_reg_5180_pp0_it4[6] <= ap_reg_ppstg_tmp_6_reg_5180_pp0_it3[6];
ap_reg_ppstg_tmp_6_reg_5180_pp0_it4[7] <= ap_reg_ppstg_tmp_6_reg_5180_pp0_it3[7];
ap_reg_ppstg_tmp_6_reg_5180_pp0_it4[8] <= ap_reg_ppstg_tmp_6_reg_5180_pp0_it3[8];
ap_reg_ppstg_tmp_6_reg_5180_pp0_it4[9] <= ap_reg_ppstg_tmp_6_reg_5180_pp0_it3[9];
ap_reg_ppstg_tmp_6_reg_5180_pp0_it4[10] <= ap_reg_ppstg_tmp_6_reg_5180_pp0_it3[10];
ap_reg_ppstg_tmp_6_reg_5180_pp0_it4[11] <= ap_reg_ppstg_tmp_6_reg_5180_pp0_it3[11];
ap_reg_ppstg_tmp_6_reg_5180_pp0_it4[12] <= ap_reg_ppstg_tmp_6_reg_5180_pp0_it3[12];
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_6_reg_5180_pp0_it5[6] <= ap_reg_ppstg_tmp_6_reg_5180_pp0_it4[6];
ap_reg_ppstg_tmp_6_reg_5180_pp0_it5[7] <= ap_reg_ppstg_tmp_6_reg_5180_pp0_it4[7];
ap_reg_ppstg_tmp_6_reg_5180_pp0_it5[8] <= ap_reg_ppstg_tmp_6_reg_5180_pp0_it4[8];
ap_reg_ppstg_tmp_6_reg_5180_pp0_it5[9] <= ap_reg_ppstg_tmp_6_reg_5180_pp0_it4[9];
ap_reg_ppstg_tmp_6_reg_5180_pp0_it5[10] <= ap_reg_ppstg_tmp_6_reg_5180_pp0_it4[10];
ap_reg_ppstg_tmp_6_reg_5180_pp0_it5[11] <= ap_reg_ppstg_tmp_6_reg_5180_pp0_it4[11];
ap_reg_ppstg_tmp_6_reg_5180_pp0_it5[12] <= ap_reg_ppstg_tmp_6_reg_5180_pp0_it4[12];
end
if ((ap_ST_pp3_stg1_fsm_14 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_75_reg_5523_pp3_it1 <= tmp_75_reg_5523;
end
if ((ap_ST_pp3_stg1_fsm_14 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_83_reg_5538_pp3_it1 <= tmp_83_reg_5538;
end
if ((ap_ST_pp3_stg2_fsm_15 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_86_reg_5583_pp3_it1 <= tmp_86_reg_5583;
end
if ((ap_ST_pp3_stg2_fsm_15 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_90_reg_5598_pp3_it1 <= tmp_90_reg_5598;
end
if ((ap_ST_pp3_stg3_fsm_16 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_98_reg_5618_pp3_it1 <= tmp_98_reg_5618;
end
if ((ap_ST_pp3_stg3_fsm_16 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_98_reg_5618_pp3_it2 <= ap_reg_ppstg_tmp_98_reg_5618_pp3_it1;
end
if ((ap_ST_pp1_stg0_fsm_4 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_9_reg_5237_pp1_it1[0] <= tmp_9_reg_5237[0];
ap_reg_ppstg_tmp_9_reg_5237_pp1_it1[1] <= tmp_9_reg_5237[1];
ap_reg_ppstg_tmp_9_reg_5237_pp1_it1[2] <= tmp_9_reg_5237[2];
ap_reg_ppstg_tmp_9_reg_5237_pp1_it1[3] <= tmp_9_reg_5237[3];
ap_reg_ppstg_tmp_9_reg_5237_pp1_it1[4] <= tmp_9_reg_5237[4];
ap_reg_ppstg_tmp_9_reg_5237_pp1_it1[5] <= tmp_9_reg_5237[5];
ap_reg_ppstg_tmp_9_reg_5237_pp1_it1[6] <= tmp_9_reg_5237[6];
ap_reg_ppstg_tmp_9_reg_5237_pp1_it1[7] <= tmp_9_reg_5237[7];
ap_reg_ppstg_tmp_9_reg_5237_pp1_it1[8] <= tmp_9_reg_5237[8];
ap_reg_ppstg_tmp_9_reg_5237_pp1_it1[9] <= tmp_9_reg_5237[9];
ap_reg_ppstg_tmp_9_reg_5237_pp1_it1[10] <= tmp_9_reg_5237[10];
ap_reg_ppstg_tmp_9_reg_5237_pp1_it1[11] <= tmp_9_reg_5237[11];
ap_reg_ppstg_tmp_9_reg_5237_pp1_it1[12] <= tmp_9_reg_5237[12];
ap_reg_ppstg_tmp_9_reg_5237_pp1_it1[13] <= tmp_9_reg_5237[13];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp3_it0) & (ap_const_lv1_0 == exitcond6_reg_5446) & (ap_ST_pp3_stg4_fsm_17 == ap_CS_fsm))) begin
b_addr23_reg_5633 <= (b_addr22_cast_fu_3513_p1 + tmp_44_trn_cast_reg_5477);
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp3_it0) & (ap_const_lv1_0 == exitcond6_reg_5446) & (ap_ST_pp3_stg4_fsm_17 == ap_CS_fsm))) begin
b_addr25_reg_5643 <= (b_addr24_cast_fu_3562_p1 + tmp_44_trn_cast_reg_5477);
end
if (((ap_ST_pp5_stg1_fsm_23 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp5_it0) & (ap_const_lv1_0 == exitcond9_reg_5697))) begin
b_addr26_cast_reg_5755[6] <= b_addr26_cast_fu_3731_p1[6];
b_addr26_cast_reg_5755[7] <= b_addr26_cast_fu_3731_p1[7];
b_addr26_cast_reg_5755[8] <= b_addr26_cast_fu_3731_p1[8];
b_addr26_cast_reg_5755[9] <= b_addr26_cast_fu_3731_p1[9];
b_addr26_cast_reg_5755[10] <= b_addr26_cast_fu_3731_p1[10];
b_addr26_cast_reg_5755[11] <= b_addr26_cast_fu_3731_p1[11];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp7_it0) & (ap_ST_pp7_stg0_fsm_31 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond12_fu_4005_p2))) begin
b_addr36_cast_reg_5956[6] <= b_addr36_cast_fu_4063_p1[6];
b_addr36_cast_reg_5956[7] <= b_addr36_cast_fu_4063_p1[7];
b_addr36_cast_reg_5956[8] <= b_addr36_cast_fu_4063_p1[8];
b_addr36_cast_reg_5956[9] <= b_addr36_cast_fu_4063_p1[9];
b_addr36_cast_reg_5956[10] <= b_addr36_cast_fu_4063_p1[10];
b_addr36_cast_reg_5956[11] <= b_addr36_cast_fu_4063_p1[11];
b_addr36_cast_reg_5956[12] <= b_addr36_cast_fu_4063_p1[12];
b_addr36_cast_reg_5956[13] <= b_addr36_cast_fu_4063_p1[13];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp7_it1) & (ap_ST_pp7_stg3_fsm_34 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond12_reg_5924_pp7_it1))) begin
b_addr44_reg_6117[3] <= b_addr44_fu_4348_p2[3];
b_addr44_reg_6117[4] <= b_addr44_fu_4348_p2[4];
b_addr44_reg_6117[5] <= b_addr44_fu_4348_p2[5];
b_addr44_reg_6117[6] <= b_addr44_fu_4348_p2[6];
b_addr44_reg_6117[7] <= b_addr44_fu_4348_p2[7];
b_addr44_reg_6117[8] <= b_addr44_fu_4348_p2[8];
b_addr44_reg_6117[9] <= b_addr44_fu_4348_p2[9];
b_addr44_reg_6117[10] <= b_addr44_fu_4348_p2[10];
b_addr44_reg_6117[11] <= b_addr44_fu_4348_p2[11];
b_addr44_reg_6117[12] <= b_addr44_fu_4348_p2[12];
b_addr44_reg_6117[13] <= b_addr44_fu_4348_p2[13];
end
if (((ap_ST_pp1_stg1_fsm_5 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond3_reg_5195))) begin
b_addr4_reg_5297[0] <= b_addr4_fu_2645_p2[0];
b_addr4_reg_5297[2] <= b_addr4_fu_2645_p2[2];
b_addr4_reg_5297[3] <= b_addr4_fu_2645_p2[3];
b_addr4_reg_5297[4] <= b_addr4_fu_2645_p2[4];
b_addr4_reg_5297[5] <= b_addr4_fu_2645_p2[5];
b_addr4_reg_5297[6] <= b_addr4_fu_2645_p2[6];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp3_it0) & (ap_ST_pp3_stg0_fsm_13 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond6_fu_3025_p2))) begin
b_addr53_reg_5498 <= tmp_51_trn_cast_fu_3069_p1[6:0];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond3_reg_5195) & (ap_ST_pp1_stg2_fsm_6 == ap_CS_fsm))) begin
b_addr8_reg_5357[0] <= b_addr8_fu_2803_p2[0];
b_addr8_reg_5357[1] <= b_addr8_fu_2803_p2[1];
b_addr8_reg_5357[3] <= b_addr8_fu_2803_p2[3];
b_addr8_reg_5357[4] <= b_addr8_fu_2803_p2[4];
b_addr8_reg_5357[5] <= b_addr8_fu_2803_p2[5];
b_addr8_reg_5357[6] <= b_addr8_fu_2803_p2[6];
end
if (((ap_ST_pp6_stg0_fsm_30 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp6_it0))) begin
exitcond10_reg_5905 <= (j_4_phi_fu_2055_p4 == ap_const_lv7_40? 1'b1: 1'b0);
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp7_it0) & (ap_ST_pp7_stg0_fsm_31 == ap_CS_fsm))) begin
exitcond12_reg_5924 <= (indvar_flatten3_phi_fu_2066_p4 == ap_const_lv9_1F8? 1'b1: 1'b0);
end
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0))) begin
exitcond1_reg_5171 <= (i_phi_fu_1890_p4 == ap_const_lv7_40? 1'b1: 1'b0);
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_ST_pp1_stg0_fsm_4 == ap_CS_fsm))) begin
exitcond3_reg_5195 <= (indvar_flatten_phi_fu_1901_p4 == ap_const_lv9_1F8? 1'b1: 1'b0);
end
if (((ap_ST_pp2_stg0_fsm_12 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp2_it0))) begin
exitcond4_reg_5427 <= (i_2_phi_fu_1945_p4 == ap_const_lv7_40? 1'b1: 1'b0);
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp3_it0) & (ap_ST_pp3_stg0_fsm_13 == ap_CS_fsm))) begin
exitcond6_reg_5446 <= (indvar_flatten1_phi_fu_1956_p4 == ap_const_lv9_1F8? 1'b1: 1'b0);
end
if (((ap_ST_pp4_stg0_fsm_21 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp4_it0))) begin
exitcond7_reg_5678 <= (j_2_phi_fu_2000_p4 == ap_const_lv7_40? 1'b1: 1'b0);
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp5_it0) & (ap_ST_pp5_stg0_fsm_22 == ap_CS_fsm))) begin
exitcond9_reg_5697 <= (indvar_flatten2_phi_fu_2011_p4 == ap_const_lv9_1F8? 1'b1: 1'b0);
end
if (((ap_ST_pp8_stg0_fsm_40 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp8_it0))) begin
exitcond_reg_6132 <= (indvar_flatten4_phi_fu_2110_p6 == ap_const_lv7_40? 1'b1: 1'b0);
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_ST_pp1_stg0_fsm_4 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond3_fu_2404_p2))) begin
if (exitcond5_fu_2416_p2) begin
i_1_mid2_reg_5204 <= ap_const_lv7_0;
end else begin
i_1_mid2_reg_5204 <= i_1_phi_fu_1934_p4;
end
end
if ((ap_ST_st9_fsm_3 == ap_CS_fsm)) begin
i_1_reg_1930 <= ap_const_lv7_0;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_const_lv1_0 == exitcond3_reg_5195) & (ap_ST_pp1_stg0_fsm_4 == ap_CS_fsm))) begin
i_1_reg_1930 <= tmp_43_reg_5402;
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_ST_pp1_stg0_fsm_4 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond3_fu_2404_p2))) begin
i_2_reg_1941 <= ap_const_lv7_0;
end else if (((ap_ST_pp2_stg0_fsm_12 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp2_it1) & (ap_const_lv1_0 == exitcond4_reg_5427))) begin
i_2_reg_1941 <= tmp_10_reg_5431;
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp3_it0) & (ap_ST_pp3_stg0_fsm_13 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond6_fu_3025_p2))) begin
if (exitcond8_fu_3037_p2) begin
i_3_mid2_reg_5455 <= ap_const_lv7_0;
end else begin
i_3_mid2_reg_5455 <= i_3_phi_fu_1989_p4;
end
end
if (((ap_ST_pp2_stg0_fsm_12 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp2_it0) & ~(ap_const_lv1_0 == exitcond4_fu_2988_p2))) begin
i_3_reg_1985 <= ap_const_lv7_0;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp3_it1) & (ap_const_lv1_0 == exitcond6_reg_5446) & (ap_ST_pp3_stg0_fsm_13 == ap_CS_fsm))) begin
i_3_reg_1985 <= tmp_82_reg_5653;
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp5_it0) & (ap_ST_pp5_stg0_fsm_22 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond9_fu_3626_p2))) begin
i_4_cast_reg_5724 <= i_4_mid2_fu_3658_p3[5:0];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp5_it0) & (ap_ST_pp5_stg0_fsm_22 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond9_fu_3626_p2))) begin
if (exitcond11_fu_3638_p2) begin
i_4_mid2_reg_5719 <= tmp_89_dup_fu_3652_p2;
end else begin
i_4_mid2_reg_5719 <= i_4_phi_fu_2022_p4;
end
end
if (((ap_ST_pp4_stg0_fsm_21 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp4_it0) & ~(ap_const_lv1_0 == exitcond7_fu_3609_p2))) begin
i_4_reg_2018 <= ap_const_lv7_1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp5_it1) & (ap_const_lv1_0 == exitcond9_reg_5697) & (ap_ST_pp5_stg0_fsm_22 == ap_CS_fsm))) begin
i_4_reg_2018 <= i_4_mid2_reg_5719;
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp7_it0) & (ap_ST_pp7_stg0_fsm_31 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond12_fu_4005_p2))) begin
i_5_cast_reg_5951 <= i_5_mid2_fu_4037_p3[5:0];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp7_it0) & (ap_ST_pp7_stg0_fsm_31 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond12_fu_4005_p2))) begin
if (exitcond13_fu_4017_p2) begin
i_5_mid2_reg_5946 <= tmp_125_dup_fu_4031_p2;
end else begin
i_5_mid2_reg_5946 <= i_5_phi_fu_2077_p4;
end
end
if (((ap_ST_pp6_stg0_fsm_30 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp6_it0) & ~(ap_const_lv1_0 == exitcond10_fu_3978_p2))) begin
i_5_reg_2073 <= ap_const_lv7_3E;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp7_it1) & (ap_const_lv1_0 == exitcond12_reg_5924) & (ap_ST_pp7_stg0_fsm_31 == ap_CS_fsm))) begin
i_5_reg_2073 <= i_5_mid2_reg_5946;
end
if (((ap_ST_pp8_stg0_fsm_40 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_fu_4357_p2))) begin
if (exitcond2_fu_4369_p2) begin
i_6_mid2_reg_6153 <= tmp_173_dup_fu_4383_p2;
end else begin
i_6_mid2_reg_6153 <= i_6_phi_fu_2124_p6;
end
end
if ((((ap_ST_st1_fsm_1 == ap_CS_fsm) & ~(ap_const_lv1_0 == or_cond_fu_2365_p2) & (ap_const_lv1_0 == tmp_2_fu_2371_p2)) | (ap_ST_st131_fsm_39 == ap_CS_fsm))) begin
i_6_reg_2120 <= ap_const_lv7_0;
end else if (((ap_ST_pp8_stg0_fsm_40 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp8_it1) & (ap_const_lv1_0 == exitcond_reg_6132))) begin
i_6_reg_2120 <= i_6_mid2_reg_6153;
end
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (exitcond1_reg_5171 == ap_const_lv1_0))) begin
i_reg_1886 <= tmp_5_reg_5175;
end else if (((ap_ST_st1_fsm_1 == ap_CS_fsm) & ~(ap_const_lv1_0 == or_cond_fu_2365_p2) & ~(ap_const_lv1_0 == tmp_2_fu_2371_p2))) begin
i_reg_1886 <= ap_const_lv7_0;
end
if ((ap_ST_st9_fsm_3 == ap_CS_fsm)) begin
indvar3_reg_1919 <= ap_const_lv4_0;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_const_lv1_0 == exitcond3_reg_5195) & (ap_ST_pp1_stg0_fsm_4 == ap_CS_fsm))) begin
indvar3_reg_1919 <= indvar_next3_reg_5252;
end
if (((ap_ST_pp6_stg0_fsm_30 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp6_it0) & ~(ap_const_lv1_0 == exitcond10_fu_3978_p2))) begin
indvar4_reg_2084 <= ap_const_lv4_0;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp7_it1) & (ap_const_lv1_0 == exitcond12_reg_5924) & (ap_ST_pp7_stg0_fsm_31 == ap_CS_fsm))) begin
indvar4_reg_2084 <= indvar_next5_reg_5977;
end
if (((ap_ST_pp2_stg0_fsm_12 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp2_it0) & ~(ap_const_lv1_0 == exitcond4_fu_2988_p2))) begin
indvar6_reg_1974 <= ap_const_lv4_0;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp3_it1) & (ap_const_lv1_0 == exitcond6_reg_5446) & (ap_ST_pp3_stg0_fsm_13 == ap_CS_fsm))) begin
indvar6_reg_1974 <= indvar_next6_reg_5503;
end
if (((ap_ST_pp4_stg0_fsm_21 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp4_it0) & ~(ap_const_lv1_0 == exitcond7_fu_3609_p2))) begin
indvar9_reg_2029 <= ap_const_lv4_0;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp5_it1) & (ap_const_lv1_0 == exitcond9_reg_5697) & (ap_ST_pp5_stg0_fsm_22 == ap_CS_fsm))) begin
indvar9_reg_2029 <= indvar_next9_reg_5750;
end
if (((ap_ST_pp2_stg0_fsm_12 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp2_it0) & ~(ap_const_lv1_0 == exitcond4_fu_2988_p2))) begin
indvar_flatten1_reg_1952 <= ap_const_lv9_0;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp3_it1) & (ap_const_lv1_0 == exitcond6_reg_5446) & (ap_ST_pp3_stg0_fsm_13 == ap_CS_fsm))) begin
indvar_flatten1_reg_1952 <= indvar_flatten_next1_reg_5450;
end
if (((ap_ST_pp4_stg0_fsm_21 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp4_it0) & ~(ap_const_lv1_0 == exitcond7_fu_3609_p2))) begin
indvar_flatten2_reg_2007 <= ap_const_lv9_0;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp5_it1) & (ap_const_lv1_0 == exitcond9_reg_5697) & (ap_ST_pp5_stg0_fsm_22 == ap_CS_fsm))) begin
indvar_flatten2_reg_2007 <= indvar_flatten_next2_reg_5701;
end
if (((ap_ST_pp6_stg0_fsm_30 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp6_it0) & ~(ap_const_lv1_0 == exitcond10_fu_3978_p2))) begin
indvar_flatten3_reg_2062 <= ap_const_lv9_0;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp7_it1) & (ap_const_lv1_0 == exitcond12_reg_5924) & (ap_ST_pp7_stg0_fsm_31 == ap_CS_fsm))) begin
indvar_flatten3_reg_2062 <= indvar_flatten_next3_reg_5928;
end
if ((((ap_ST_st1_fsm_1 == ap_CS_fsm) & ~(ap_const_lv1_0 == or_cond_fu_2365_p2) & (ap_const_lv1_0 == tmp_2_fu_2371_p2)) | (ap_ST_st131_fsm_39 == ap_CS_fsm))) begin
indvar_flatten4_reg_2106 <= ap_const_lv7_0;
end else if (((ap_ST_pp8_stg0_fsm_40 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp8_it1) & (ap_const_lv1_0 == exitcond_reg_6132))) begin
indvar_flatten4_reg_2106 <= indvar_flatten_next4_reg_6136;
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp3_it0) & (ap_ST_pp3_stg0_fsm_13 == ap_CS_fsm))) begin
indvar_flatten_next1_reg_5450 <= (indvar_flatten1_phi_fu_1956_p4 + ap_const_lv9_1);
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp5_it0) & (ap_ST_pp5_stg0_fsm_22 == ap_CS_fsm))) begin
indvar_flatten_next2_reg_5701 <= (indvar_flatten2_phi_fu_2011_p4 + ap_const_lv9_1);
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp7_it0) & (ap_ST_pp7_stg0_fsm_31 == ap_CS_fsm))) begin
indvar_flatten_next3_reg_5928 <= (indvar_flatten3_phi_fu_2066_p4 + ap_const_lv9_1);
end
if (((ap_ST_pp8_stg0_fsm_40 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp8_it0))) begin
indvar_flatten_next4_reg_6136 <= (indvar_flatten4_phi_fu_2110_p6 + ap_const_lv7_1);
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_ST_pp1_stg0_fsm_4 == ap_CS_fsm))) begin
indvar_flatten_next_reg_5199 <= (indvar_flatten_phi_fu_1901_p4 + ap_const_lv9_1);
end
if ((ap_ST_st9_fsm_3 == ap_CS_fsm)) begin
indvar_flatten_reg_1897 <= ap_const_lv9_0;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_const_lv1_0 == exitcond3_reg_5195) & (ap_ST_pp1_stg0_fsm_4 == ap_CS_fsm))) begin
indvar_flatten_reg_1897 <= indvar_flatten_next_reg_5199;
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_ST_pp1_stg0_fsm_4 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond3_fu_2404_p2))) begin
if (exitcond5_fu_2416_p2) begin
indvar_next3_reg_5252 <= ap_const_lv4_1;
end else begin
indvar_next3_reg_5252 <= indvar3_op_fu_2481_p2;
end
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp7_it0) & (ap_ST_pp7_stg0_fsm_31 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond12_fu_4005_p2))) begin
if (exitcond13_fu_4017_p2) begin
indvar_next5_reg_5977 <= ap_const_lv4_1;
end else begin
indvar_next5_reg_5977 <= indvar4_op_fu_4078_p2;
end
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp3_it0) & (ap_ST_pp3_stg0_fsm_13 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond6_fu_3025_p2))) begin
if (exitcond8_fu_3037_p2) begin
indvar_next6_reg_5503 <= ap_const_lv4_1;
end else begin
indvar_next6_reg_5503 <= indvar6_op_fu_3102_p2;
end
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp5_it0) & (ap_ST_pp5_stg0_fsm_22 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond9_fu_3626_p2))) begin
if (exitcond11_fu_3638_p2) begin
indvar_next9_reg_5750 <= ap_const_lv4_1;
end else begin
indvar_next9_reg_5750 <= indvar9_op_fu_3699_p2;
end
end
if (((ap_ST_pp8_stg0_fsm_40 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_fu_4357_p2))) begin
if (exitcond2_fu_4369_p2) begin
indvar_next_reg_6186 <= ap_const_lv4_1;
end else begin
indvar_next_reg_6186 <= indvar_op_fu_4426_p2;
end
end
if ((((ap_ST_st1_fsm_1 == ap_CS_fsm) & ~(ap_const_lv1_0 == or_cond_fu_2365_p2) & (ap_const_lv1_0 == tmp_2_fu_2371_p2)) | (ap_ST_st131_fsm_39 == ap_CS_fsm))) begin
indvar_reg_2134 <= ap_const_lv4_0;
end else if (((ap_ST_pp8_stg0_fsm_40 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp8_it1) & (ap_const_lv1_0 == exitcond_reg_6132))) begin
indvar_reg_2134 <= indvar_next_reg_6186;
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp3_it0) & (ap_ST_pp3_stg0_fsm_13 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond6_fu_3025_p2))) begin
j_1_cast_reg_5472 <= j_1_mid2_fu_3057_p3[5:0];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp3_it0) & (ap_ST_pp3_stg0_fsm_13 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond6_fu_3025_p2))) begin
if (exitcond8_fu_3037_p2) begin
j_1_mid2_reg_5467 <= tmp_50_dup_fu_3051_p2;
end else begin
j_1_mid2_reg_5467 <= j_1_phi_fu_1967_p4;
end
end
if (((ap_ST_pp2_stg0_fsm_12 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp2_it0) & ~(ap_const_lv1_0 == exitcond4_fu_2988_p2))) begin
j_1_reg_1963 <= ap_const_lv7_3E;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp3_it1) & (ap_const_lv1_0 == exitcond6_reg_5446) & (ap_ST_pp3_stg0_fsm_13 == ap_CS_fsm))) begin
j_1_reg_1963 <= j_1_mid2_reg_5467;
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp3_it0) & (ap_ST_pp3_stg0_fsm_13 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond6_fu_3025_p2))) begin
j_2_reg_1996 <= ap_const_lv7_0;
end else if (((ap_ST_pp4_stg0_fsm_21 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp4_it1) & (ap_const_lv1_0 == exitcond7_reg_5678))) begin
j_2_reg_1996 <= tmp_49_reg_5682;
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp5_it0) & (ap_ST_pp5_stg0_fsm_22 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond9_fu_3626_p2))) begin
if (exitcond11_fu_3638_p2) begin
j_3_mid2_reg_5706 <= ap_const_lv7_0;
end else begin
j_3_mid2_reg_5706 <= j_3_phi_fu_2044_p4;
end
end
if (((ap_ST_pp4_stg0_fsm_21 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp4_it0) & ~(ap_const_lv1_0 == exitcond7_fu_3609_p2))) begin
j_3_reg_2040 <= ap_const_lv7_0;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp5_it1) & (ap_const_lv1_0 == exitcond9_reg_5697) & (ap_ST_pp5_stg0_fsm_22 == ap_CS_fsm))) begin
j_3_reg_2040 <= tmp_121_reg_5875;
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp5_it0) & (ap_ST_pp5_stg0_fsm_22 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond9_fu_3626_p2))) begin
j_4_reg_2051 <= ap_const_lv7_0;
end else if (((ap_ST_pp6_stg0_fsm_30 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp6_it1) & (ap_const_lv1_0 == exitcond10_reg_5905))) begin
j_4_reg_2051 <= tmp_88_reg_5909;
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp7_it0) & (ap_ST_pp7_stg0_fsm_31 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond12_fu_4005_p2))) begin
if (exitcond13_fu_4017_p2) begin
j_5_mid2_reg_5933 <= ap_const_lv7_0;
end else begin
j_5_mid2_reg_5933 <= j_5_phi_fu_2099_p4;
end
end
if (((ap_ST_pp6_stg0_fsm_30 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp6_it0) & ~(ap_const_lv1_0 == exitcond10_fu_3978_p2))) begin
j_5_reg_2095 <= ap_const_lv7_0;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp7_it1) & (ap_const_lv1_0 == exitcond12_reg_5924) & (ap_ST_pp7_stg0_fsm_31 == ap_CS_fsm))) begin
j_5_reg_2095 <= tmp_157_reg_6102;
end
if (((ap_ST_pp8_stg0_fsm_40 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_fu_4357_p2))) begin
if (exitcond2_fu_4369_p2) begin
j_6_mid2_reg_6141 <= ap_const_lv7_0;
end else begin
j_6_mid2_reg_6141 <= j_6_phi_fu_2152_p6;
end
end
if ((((ap_ST_st1_fsm_1 == ap_CS_fsm) & ~(ap_const_lv1_0 == or_cond_fu_2365_p2) & (ap_const_lv1_0 == tmp_2_fu_2371_p2)) | (ap_ST_st131_fsm_39 == ap_CS_fsm))) begin
j_6_reg_2148 <= ap_const_lv7_0;
end else if (((ap_ST_pp8_stg0_fsm_40 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp8_it1) & (ap_const_lv1_0 == exitcond_reg_6132))) begin
j_6_reg_2148 <= tmp_189_reg_6358;
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_ST_pp1_stg0_fsm_4 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond3_fu_2404_p2))) begin
j_cast_reg_5221 <= j_mid2_fu_2436_p3[5:0];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_ST_pp1_stg0_fsm_4 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond3_fu_2404_p2))) begin
if (exitcond5_fu_2416_p2) begin
j_mid2_reg_5216 <= tmp_11_dup_fu_2430_p2;
end else begin
j_mid2_reg_5216 <= j_phi_fu_1912_p4;
end
end
if ((ap_ST_st9_fsm_3 == ap_CS_fsm)) begin
j_reg_1908 <= ap_const_lv7_1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_const_lv1_0 == exitcond3_reg_5195) & (ap_ST_pp1_stg0_fsm_4 == ap_CS_fsm))) begin
j_reg_1908 <= j_mid2_reg_5216;
end
if ((((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (exitcond1_reg_5171 == ap_const_lv1_0)) | ((ap_ST_pp1_stg1_fsm_5 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond3_reg_5195)) | ((ap_ST_pp3_stg2_fsm_15 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp3_it0) & (ap_const_lv1_0 == exitcond6_reg_5446)) | ((ap_ST_pp4_stg0_fsm_21 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp4_it1) & (ap_const_lv1_0 == exitcond7_reg_5678)) | ((ap_ST_pp5_stg1_fsm_23 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp5_it0) & (ap_const_lv1_0 == exitcond9_reg_5697)) | ((ap_ST_pp7_stg2_fsm_33 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp7_it0) & (ap_const_lv1_0 == exitcond12_reg_5924)))) begin
reg_2171 <= a_q0;
end
if ((((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it5) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond1_reg_5171_pp0_it4)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond3_reg_5195) & (ap_ST_pp1_stg6_fsm_10 == ap_CS_fsm)) | ((ap_ST_pp2_stg0_fsm_12 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp2_it5) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond4_reg_5427_pp2_it4)) | ((ap_const_logic_1 == ap_reg_ppiten_pp3_it0) & (ap_const_lv1_0 == exitcond6_reg_5446) & (ap_ST_pp3_stg6_fsm_19 == ap_CS_fsm)) | ((ap_ST_pp4_stg0_fsm_21 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp4_it5) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond7_reg_5678_pp4_it4)) | ((ap_const_logic_1 == ap_reg_ppiten_pp5_it0) & (ap_const_lv1_0 == exitcond9_reg_5697) & (ap_ST_pp5_stg6_fsm_28 == ap_CS_fsm)) | ((ap_ST_pp6_stg0_fsm_30 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp6_it5) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond10_reg_5905_pp6_it4)) | ((ap_const_logic_1 == ap_reg_ppiten_pp7_it0) & (ap_const_lv1_0 == exitcond12_reg_5924) & (ap_ST_pp7_stg6_fsm_37 == ap_CS_fsm)))) begin
reg_2177 <= grp_fu_2167_p2;
end
if ((((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond3_reg_5195) & (ap_ST_pp1_stg2_fsm_6 == ap_CS_fsm)) | ((ap_ST_pp2_stg0_fsm_12 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp2_it1) & (ap_const_lv1_0 == exitcond4_reg_5427)) | ((ap_const_logic_1 == ap_reg_ppiten_pp3_it0) & (ap_const_lv1_0 == exitcond6_reg_5446) & (ap_ST_pp3_stg1_fsm_14 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp5_it0) & (ap_const_lv1_0 == exitcond9_reg_5697) & (ap_ST_pp5_stg2_fsm_24 == ap_CS_fsm)) | ((ap_ST_pp6_stg0_fsm_30 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp6_it1) & (ap_const_lv1_0 == exitcond10_reg_5905)) | ((ap_const_logic_1 == ap_reg_ppiten_pp7_it0) & (ap_const_lv1_0 == exitcond12_reg_5924) & (ap_ST_pp7_stg1_fsm_32 == ap_CS_fsm)))) begin
reg_2184 <= b_q0;
end
if ((((ap_ST_pp3_stg2_fsm_15 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp3_it0) & (ap_const_lv1_0 == exitcond6_reg_5446)) | ((ap_ST_pp7_stg2_fsm_33 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp7_it0) & (ap_const_lv1_0 == exitcond12_reg_5924)))) begin
reg_2190 <= a_q1;
end else if ((((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond3_reg_5195) & (ap_ST_pp1_stg2_fsm_6 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp5_it0) & (ap_const_lv1_0 == exitcond9_reg_5697) & (ap_ST_pp5_stg2_fsm_24 == ap_CS_fsm)))) begin
reg_2190 <= a_q0;
end
if ((((ap_ST_pp3_stg2_fsm_15 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp3_it0) & (ap_const_lv1_0 == exitcond6_reg_5446)) | ((ap_ST_pp7_stg2_fsm_33 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp7_it0) & (ap_const_lv1_0 == exitcond12_reg_5924)))) begin
reg_2197 <= b_q0;
end else if ((((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond3_reg_5195) & (ap_ST_pp1_stg2_fsm_6 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp5_it0) & (ap_const_lv1_0 == exitcond9_reg_5697) & (ap_ST_pp5_stg2_fsm_24 == ap_CS_fsm)))) begin
reg_2197 <= b_q1;
end
if ((((ap_const_logic_1 == ap_reg_ppiten_pp3_it0) & (ap_const_lv1_0 == exitcond6_reg_5446) & (ap_ST_pp3_stg3_fsm_16 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp7_it0) & (ap_const_lv1_0 == exitcond12_reg_5924) & (ap_ST_pp7_stg3_fsm_34 == ap_CS_fsm)))) begin
reg_2204 <= a_q0;
end else if ((((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond3_reg_5195) & (ap_ST_pp1_stg2_fsm_6 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp5_it0) & (ap_const_lv1_0 == exitcond9_reg_5697) & (ap_ST_pp5_stg2_fsm_24 == ap_CS_fsm)))) begin
reg_2204 <= a_q1;
end
if ((((ap_ST_pp3_stg2_fsm_15 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp3_it0) & (ap_const_lv1_0 == exitcond6_reg_5446)) | ((ap_ST_pp7_stg2_fsm_33 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp7_it0) & (ap_const_lv1_0 == exitcond12_reg_5924)))) begin
reg_2211 <= b_q1;
end else if ((((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond3_reg_5195) & (ap_ST_pp1_stg3_fsm_7 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp5_it0) & (ap_const_lv1_0 == exitcond9_reg_5697) & (ap_ST_pp5_stg3_fsm_25 == ap_CS_fsm)))) begin
reg_2211 <= b_q0;
end
if ((((ap_const_logic_1 == ap_reg_ppiten_pp3_it0) & (ap_const_lv1_0 == exitcond6_reg_5446) & (ap_ST_pp3_stg3_fsm_16 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp7_it0) & (ap_const_lv1_0 == exitcond12_reg_5924) & (ap_ST_pp7_stg3_fsm_34 == ap_CS_fsm)))) begin
reg_2218 <= a_q1;
end else if ((((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond3_reg_5195) & (ap_ST_pp1_stg3_fsm_7 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp5_it0) & (ap_const_lv1_0 == exitcond9_reg_5697) & (ap_ST_pp5_stg3_fsm_25 == ap_CS_fsm)))) begin
reg_2218 <= a_q0;
end
if ((((ap_const_logic_1 == ap_reg_ppiten_pp3_it0) & (ap_const_lv1_0 == exitcond6_reg_5446) & (ap_ST_pp3_stg3_fsm_16 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp7_it0) & (ap_const_lv1_0 == exitcond12_reg_5924) & (ap_ST_pp7_stg3_fsm_34 == ap_CS_fsm)))) begin
reg_2225 <= b_q0;
end else if ((((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond3_reg_5195) & (ap_ST_pp1_stg3_fsm_7 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp5_it0) & (ap_const_lv1_0 == exitcond9_reg_5697) & (ap_ST_pp5_stg3_fsm_25 == ap_CS_fsm)))) begin
reg_2225 <= b_q1;
end
if ((((ap_const_logic_1 == ap_reg_ppiten_pp3_it0) & (ap_const_lv1_0 == exitcond6_reg_5446) & (ap_ST_pp3_stg4_fsm_17 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp7_it0) & (ap_const_lv1_0 == exitcond12_reg_5924) & (ap_ST_pp7_stg4_fsm_35 == ap_CS_fsm)))) begin
reg_2232 <= a_q0;
end else if ((((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond3_reg_5195) & (ap_ST_pp1_stg3_fsm_7 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp5_it0) & (ap_const_lv1_0 == exitcond9_reg_5697) & (ap_ST_pp5_stg3_fsm_25 == ap_CS_fsm)))) begin
reg_2232 <= a_q1;
end
if ((((ap_const_logic_1 == ap_reg_ppiten_pp3_it0) & (ap_const_lv1_0 == exitcond6_reg_5446) & (ap_ST_pp3_stg3_fsm_16 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp7_it0) & (ap_const_lv1_0 == exitcond12_reg_5924) & (ap_ST_pp7_stg3_fsm_34 == ap_CS_fsm)))) begin
reg_2239 <= b_q1;
end else if ((((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond3_reg_5195) & (ap_ST_pp1_stg4_fsm_8 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp5_it0) & (ap_const_lv1_0 == exitcond9_reg_5697) & (ap_ST_pp5_stg4_fsm_26 == ap_CS_fsm)))) begin
reg_2239 <= b_q0;
end
if ((((ap_const_logic_1 == ap_reg_ppiten_pp3_it0) & (ap_const_lv1_0 == exitcond6_reg_5446) & (ap_ST_pp3_stg4_fsm_17 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp7_it0) & (ap_const_lv1_0 == exitcond12_reg_5924) & (ap_ST_pp7_stg4_fsm_35 == ap_CS_fsm)))) begin
reg_2246 <= a_q1;
end else if ((((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond3_reg_5195) & (ap_ST_pp1_stg4_fsm_8 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp5_it0) & (ap_const_lv1_0 == exitcond9_reg_5697) & (ap_ST_pp5_stg4_fsm_26 == ap_CS_fsm)))) begin
reg_2246 <= a_q0;
end
if ((((ap_const_logic_1 == ap_reg_ppiten_pp3_it0) & (ap_const_lv1_0 == exitcond6_reg_5446) & (ap_ST_pp3_stg4_fsm_17 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp7_it0) & (ap_const_lv1_0 == exitcond12_reg_5924) & (ap_ST_pp7_stg4_fsm_35 == ap_CS_fsm)))) begin
reg_2253 <= b_q0;
end else if ((((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond3_reg_5195) & (ap_ST_pp1_stg4_fsm_8 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp5_it0) & (ap_const_lv1_0 == exitcond9_reg_5697) & (ap_ST_pp5_stg4_fsm_26 == ap_CS_fsm)))) begin
reg_2253 <= b_q1;
end
if ((((ap_const_logic_1 == ap_reg_ppiten_pp3_it1) & (ap_ST_pp3_stg4_fsm_17 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond6_reg_5446_pp3_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp7_it1) & (ap_ST_pp7_stg4_fsm_35 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond12_reg_5924_pp7_it1)))) begin
reg_2260 <= b_q1;
end else if ((((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond3_reg_5195) & (ap_ST_pp1_stg5_fsm_9 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp5_it0) & (ap_const_lv1_0 == exitcond9_reg_5697) & (ap_ST_pp5_stg5_fsm_27 == ap_CS_fsm)))) begin
reg_2260 <= b_q0;
end
if ((((ap_const_logic_1 == ap_reg_ppiten_pp3_it1) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond6_reg_5446_pp3_it1) & (ap_ST_pp3_stg5_fsm_18 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp7_it1) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond12_reg_5924_pp7_it1) & (ap_ST_pp7_stg5_fsm_36 == ap_CS_fsm)))) begin
reg_2267 <= b_q0;
end else if ((((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond3_reg_5195) & (ap_ST_pp1_stg5_fsm_9 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp5_it0) & (ap_const_lv1_0 == exitcond9_reg_5697) & (ap_ST_pp5_stg5_fsm_27 == ap_CS_fsm)))) begin
reg_2267 <= b_q1;
end
if ((((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond3_reg_5195) & (ap_ST_pp1_stg7_fsm_11 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp3_it0) & (ap_const_lv1_0 == exitcond6_reg_5446) & (ap_ST_pp3_stg7_fsm_20 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp5_it0) & (ap_const_lv1_0 == exitcond9_reg_5697) & (ap_ST_pp5_stg7_fsm_29 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp7_it0) & (ap_const_lv1_0 == exitcond12_reg_5924) & (ap_ST_pp7_stg7_fsm_38 == ap_CS_fsm)))) begin
reg_2274 <= grp_fu_2167_p2;
end
if ((((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_const_lv1_0 == exitcond3_reg_5195) & (ap_ST_pp1_stg0_fsm_4 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp3_it1) & (ap_const_lv1_0 == exitcond6_reg_5446) & (ap_ST_pp3_stg0_fsm_13 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp5_it1) & (ap_const_lv1_0 == exitcond9_reg_5697) & (ap_ST_pp5_stg0_fsm_22 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp7_it1) & (ap_const_lv1_0 == exitcond12_reg_5924) & (ap_ST_pp7_stg0_fsm_31 == ap_CS_fsm)))) begin
reg_2279 <= grp_fu_2167_p2;
end
if ((((ap_ST_pp1_stg1_fsm_5 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond3_reg_5195_pp1_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp3_it1) & (ap_ST_pp3_stg1_fsm_14 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond6_reg_5446_pp3_it1)) | ((ap_ST_pp5_stg1_fsm_23 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp5_it1) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond9_reg_5697_pp5_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp7_it1) & (ap_ST_pp7_stg1_fsm_32 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond12_reg_5924_pp7_it1)))) begin
reg_2284 <= grp_fu_2167_p2;
end
if ((((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_ST_pp1_stg2_fsm_6 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond3_reg_5195_pp1_it1)) | ((ap_ST_pp3_stg2_fsm_15 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp3_it1) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond6_reg_5446_pp3_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp5_it1) & (ap_ST_pp5_stg2_fsm_24 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond9_reg_5697_pp5_it1)) | ((ap_ST_pp7_stg2_fsm_33 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp7_it1) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond12_reg_5924_pp7_it1)))) begin
reg_2289 <= grp_fu_2167_p2;
end
if ((((ap_const_logic_1 == ap_reg_ppiten_pp3_it1) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond6_reg_5446_pp3_it1) & (ap_ST_pp3_stg5_fsm_18 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp7_it1) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond12_reg_5924_pp7_it1) & (ap_ST_pp7_stg5_fsm_36 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_ST_pp1_stg3_fsm_7 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond3_reg_5195_pp1_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_ST_pp1_stg5_fsm_9 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond3_reg_5195_pp1_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_ST_pp1_stg6_fsm_10 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond3_reg_5195_pp1_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_ST_pp1_stg7_fsm_11 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond3_reg_5195_pp1_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp3_it1) & (ap_ST_pp3_stg3_fsm_16 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond6_reg_5446_pp3_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp3_it1) & (ap_ST_pp3_stg6_fsm_19 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond6_reg_5446_pp3_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp3_it1) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond6_reg_5446_pp3_it1) & (ap_ST_pp3_stg7_fsm_20 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp5_it1) & (ap_ST_pp5_stg3_fsm_25 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond9_reg_5697_pp5_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp5_it1) & (ap_ST_pp5_stg5_fsm_27 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond9_reg_5697_pp5_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp5_it1) & (ap_ST_pp5_stg6_fsm_28 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond9_reg_5697_pp5_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp5_it1) & (ap_ST_pp5_stg7_fsm_29 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond9_reg_5697_pp5_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp7_it1) & (ap_ST_pp7_stg3_fsm_34 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond12_reg_5924_pp7_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp7_it1) & (ap_ST_pp7_stg6_fsm_37 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond12_reg_5924_pp7_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp7_it1) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond12_reg_5924_pp7_it1) & (ap_ST_pp7_stg7_fsm_38 == ap_CS_fsm)))) begin
reg_2294 <= grp_fu_2163_p2;
end
if ((((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_ST_pp1_stg3_fsm_7 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond3_reg_5195_pp1_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp3_it1) & (ap_ST_pp3_stg3_fsm_16 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond6_reg_5446_pp3_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp5_it1) & (ap_ST_pp5_stg3_fsm_25 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond9_reg_5697_pp5_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp7_it1) & (ap_ST_pp7_stg3_fsm_34 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond12_reg_5924_pp7_it1)))) begin
reg_2300 <= grp_fu_2167_p2;
end
if ((((ap_const_logic_1 == ap_reg_ppiten_pp3_it1) & (ap_ST_pp3_stg4_fsm_17 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond6_reg_5446_pp3_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp7_it1) & (ap_ST_pp7_stg4_fsm_35 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond12_reg_5924_pp7_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_ST_pp1_stg4_fsm_8 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond3_reg_5195_pp1_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp5_it1) & (ap_ST_pp5_stg4_fsm_26 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond9_reg_5697_pp5_it1)))) begin
reg_2305 <= grp_fu_2163_p2;
end
if ((((ap_const_logic_1 == ap_reg_ppiten_pp3_it0) & (ap_const_lv1_0 == exitcond6_reg_5446) & (ap_ST_pp3_stg5_fsm_18 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp7_it0) & (ap_const_lv1_0 == exitcond12_reg_5924) & (ap_ST_pp7_stg5_fsm_36 == ap_CS_fsm)))) begin
reg_2311 <= a_q0;
end else if ((((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_ST_pp1_stg4_fsm_8 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond3_reg_5195_pp1_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp5_it1) & (ap_ST_pp5_stg4_fsm_26 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond9_reg_5697_pp5_it1)))) begin
reg_2311 <= a_q1;
end
if ((((ap_const_logic_1 == ap_reg_ppiten_pp3_it1) & (ap_ST_pp3_stg4_fsm_17 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond6_reg_5446_pp3_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp7_it1) & (ap_ST_pp7_stg4_fsm_35 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond12_reg_5924_pp7_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_ST_pp1_stg4_fsm_8 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond3_reg_5195_pp1_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp5_it1) & (ap_ST_pp5_stg4_fsm_26 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond9_reg_5697_pp5_it1)))) begin
reg_2318 <= grp_fu_2167_p2;
end
if ((((ap_const_logic_1 == ap_reg_ppiten_pp3_it0) & (ap_const_lv1_0 == exitcond6_reg_5446) & (ap_ST_pp3_stg5_fsm_18 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp7_it0) & (ap_const_lv1_0 == exitcond12_reg_5924) & (ap_ST_pp7_stg5_fsm_36 == ap_CS_fsm)))) begin
reg_2323 <= a_q1;
end else if ((((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_ST_pp1_stg5_fsm_9 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond3_reg_5195_pp1_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp5_it1) & (ap_ST_pp5_stg5_fsm_27 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond9_reg_5697_pp5_it1)))) begin
reg_2323 <= a_q0;
end
if ((((ap_const_logic_1 == ap_reg_ppiten_pp3_it1) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond6_reg_5446_pp3_it1) & (ap_ST_pp3_stg5_fsm_18 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp7_it1) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond12_reg_5924_pp7_it1) & (ap_ST_pp7_stg5_fsm_36 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_ST_pp1_stg5_fsm_9 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond3_reg_5195_pp1_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp5_it1) & (ap_ST_pp5_stg5_fsm_27 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond9_reg_5697_pp5_it1)))) begin
reg_2330 <= grp_fu_2167_p2;
end
if ((((ap_const_logic_1 == ap_reg_ppiten_pp1_it2) & (ap_ST_pp1_stg0_fsm_4 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond3_reg_5195_pp1_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp3_it2) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond6_reg_5446_pp3_it1) & (ap_ST_pp3_stg0_fsm_13 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp5_it2) & (ap_ST_pp5_stg0_fsm_22 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond9_reg_5697_pp5_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp7_it2) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond12_reg_5924_pp7_it1) & (ap_ST_pp7_stg0_fsm_31 == ap_CS_fsm)))) begin
reg_2335 <= grp_fu_2163_p2;
end
if ((((ap_ST_pp1_stg1_fsm_5 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it2) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond3_reg_5195_pp1_it2)) | ((ap_const_logic_1 == ap_reg_ppiten_pp3_it2) & (ap_ST_pp3_stg1_fsm_14 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond6_reg_5446_pp3_it2)) | ((ap_ST_pp5_stg1_fsm_23 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp5_it2) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond9_reg_5697_pp5_it2)) | ((ap_const_logic_1 == ap_reg_ppiten_pp7_it2) & (ap_ST_pp7_stg1_fsm_32 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond12_reg_5924_pp7_it2)))) begin
reg_2341 <= grp_fu_2163_p2;
end
if ((((ap_const_logic_1 == ap_reg_ppiten_pp1_it2) & (ap_ST_pp1_stg2_fsm_6 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond3_reg_5195_pp1_it2)) | ((ap_ST_pp3_stg2_fsm_15 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp3_it2) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond6_reg_5446_pp3_it2)) | ((ap_const_logic_1 == ap_reg_ppiten_pp5_it2) & (ap_ST_pp5_stg2_fsm_24 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond9_reg_5697_pp5_it2)) | ((ap_ST_pp7_stg2_fsm_33 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp7_it2) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond12_reg_5924_pp7_it2)))) begin
reg_2347 <= grp_fu_2163_p2;
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp5_it0) & (ap_const_lv1_0 == exitcond9_reg_5697) & (ap_ST_pp5_stg2_fsm_24 == ap_CS_fsm))) begin
tmp_105_reg_5820[0] <= tmp_105_fu_3845_p2[0];
tmp_105_reg_5820[1] <= tmp_105_fu_3845_p2[1];
tmp_105_reg_5820[3] <= tmp_105_fu_3845_p2[3];
tmp_105_reg_5820[4] <= tmp_105_fu_3845_p2[4];
tmp_105_reg_5820[5] <= tmp_105_fu_3845_p2[5];
tmp_105_reg_5820[6] <= tmp_105_fu_3845_p2[6];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp3_it1) & (ap_ST_pp3_stg3_fsm_16 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond6_reg_5446_pp3_it1))) begin
tmp_106_reg_5658 <= {{50{b_addr23_reg_5633[13]}}, {b_addr23_reg_5633}};
end
if (((ap_ST_pp2_stg0_fsm_12 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp2_it0))) begin
tmp_10_reg_5431 <= (i_2_phi_fu_1945_p4 + ap_const_lv7_1);
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp5_it0) & (ap_const_lv1_0 == exitcond9_reg_5697) & (ap_ST_pp5_stg4_fsm_26 == ap_CS_fsm))) begin
tmp_113_reg_5855[0] <= tmp_113_fu_3910_p2[0];
tmp_113_reg_5855[3] <= tmp_113_fu_3910_p2[3];
tmp_113_reg_5855[4] <= tmp_113_fu_3910_p2[4];
tmp_113_reg_5855[5] <= tmp_113_fu_3910_p2[5];
tmp_113_reg_5855[6] <= tmp_113_fu_3910_p2[6];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp3_it1) & (ap_ST_pp3_stg4_fsm_17 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond6_reg_5446_pp3_it1))) begin
tmp_114_reg_5668 <= {{50{b_addr25_reg_5643[13]}}, {b_addr25_reg_5643}};
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp5_it0) & (ap_const_lv1_0 == exitcond9_reg_5697) & (ap_ST_pp5_stg4_fsm_26 == ap_CS_fsm))) begin
tmp_117_reg_5865[3] <= tmp_117_fu_3929_p2[3];
tmp_117_reg_5865[4] <= tmp_117_fu_3929_p2[4];
tmp_117_reg_5865[5] <= tmp_117_fu_3929_p2[5];
tmp_117_reg_5865[6] <= tmp_117_fu_3929_p2[6];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp5_it0) & (ap_const_lv1_0 == exitcond9_reg_5697) & (ap_ST_pp5_stg4_fsm_26 == ap_CS_fsm))) begin
tmp_121_reg_5875 <= (j_3_mid2_reg_5706 + ap_const_lv7_8);
end
if (((ap_ST_pp4_stg0_fsm_21 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp4_it0) & (ap_const_lv1_0 == exitcond7_fu_3609_p2))) begin
tmp_122_reg_5687[0] <= tmp_122_fu_3621_p1[0];
tmp_122_reg_5687[1] <= tmp_122_fu_3621_p1[1];
tmp_122_reg_5687[2] <= tmp_122_fu_3621_p1[2];
tmp_122_reg_5687[3] <= tmp_122_fu_3621_p1[3];
tmp_122_reg_5687[4] <= tmp_122_fu_3621_p1[4];
tmp_122_reg_5687[5] <= tmp_122_fu_3621_p1[5];
tmp_122_reg_5687[6] <= tmp_122_fu_3621_p1[6];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp5_it0) & (ap_ST_pp5_stg0_fsm_22 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond9_fu_3626_p2))) begin
tmp_125_reg_5740[0] <= tmp_125_fu_3694_p1[0];
tmp_125_reg_5740[1] <= tmp_125_fu_3694_p1[1];
tmp_125_reg_5740[2] <= tmp_125_fu_3694_p1[2];
tmp_125_reg_5740[3] <= tmp_125_fu_3694_p1[3];
tmp_125_reg_5740[4] <= tmp_125_fu_3694_p1[4];
tmp_125_reg_5740[5] <= tmp_125_fu_3694_p1[5];
tmp_125_reg_5740[6] <= tmp_125_fu_3694_p1[6];
tmp_125_reg_5740[7] <= tmp_125_fu_3694_p1[7];
tmp_125_reg_5740[8] <= tmp_125_fu_3694_p1[8];
tmp_125_reg_5740[9] <= tmp_125_fu_3694_p1[9];
tmp_125_reg_5740[10] <= tmp_125_fu_3694_p1[10];
tmp_125_reg_5740[11] <= tmp_125_fu_3694_p1[11];
tmp_125_reg_5740[12] <= tmp_125_fu_3694_p1[12];
tmp_125_reg_5740[13] <= tmp_125_fu_3694_p1[13];
end
if (((ap_ST_pp5_stg1_fsm_23 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp5_it0) & (ap_const_lv1_0 == exitcond9_reg_5697))) begin
tmp_130_reg_5770[1] <= tmp_130_fu_3764_p1[1];
tmp_130_reg_5770[2] <= tmp_130_fu_3764_p1[2];
tmp_130_reg_5770[3] <= tmp_130_fu_3764_p1[3];
tmp_130_reg_5770[4] <= tmp_130_fu_3764_p1[4];
tmp_130_reg_5770[5] <= tmp_130_fu_3764_p1[5];
tmp_130_reg_5770[6] <= tmp_130_fu_3764_p1[6];
tmp_130_reg_5770[7] <= tmp_130_fu_3764_p1[7];
tmp_130_reg_5770[8] <= tmp_130_fu_3764_p1[8];
tmp_130_reg_5770[9] <= tmp_130_fu_3764_p1[9];
tmp_130_reg_5770[10] <= tmp_130_fu_3764_p1[10];
tmp_130_reg_5770[11] <= tmp_130_fu_3764_p1[11];
tmp_130_reg_5770[12] <= tmp_130_fu_3764_p1[12];
tmp_130_reg_5770[13] <= tmp_130_fu_3764_p1[13];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp7_it0) & (ap_const_lv1_0 == exitcond12_reg_5924) & (ap_ST_pp7_stg1_fsm_32 == ap_CS_fsm))) begin
tmp_133_reg_6012[0] <= tmp_133_fu_4159_p2[0];
tmp_133_reg_6012[2] <= tmp_133_fu_4159_p2[2];
tmp_133_reg_6012[3] <= tmp_133_fu_4159_p2[3];
tmp_133_reg_6012[4] <= tmp_133_fu_4159_p2[4];
tmp_133_reg_6012[5] <= tmp_133_fu_4159_p2[5];
tmp_133_reg_6012[6] <= tmp_133_fu_4159_p2[6];
end
if (((ap_ST_pp5_stg1_fsm_23 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp5_it0) & (ap_const_lv1_0 == exitcond9_reg_5697))) begin
tmp_138_reg_5790[0] <= tmp_138_fu_3794_p1[0];
tmp_138_reg_5790[1] <= tmp_138_fu_3794_p1[1];
tmp_138_reg_5790[2] <= tmp_138_fu_3794_p1[2];
tmp_138_reg_5790[3] <= tmp_138_fu_3794_p1[3];
tmp_138_reg_5790[4] <= tmp_138_fu_3794_p1[4];
tmp_138_reg_5790[5] <= tmp_138_fu_3794_p1[5];
tmp_138_reg_5790[6] <= tmp_138_fu_3794_p1[6];
tmp_138_reg_5790[7] <= tmp_138_fu_3794_p1[7];
tmp_138_reg_5790[8] <= tmp_138_fu_3794_p1[8];
tmp_138_reg_5790[9] <= tmp_138_fu_3794_p1[9];
tmp_138_reg_5790[10] <= tmp_138_fu_3794_p1[10];
tmp_138_reg_5790[11] <= tmp_138_fu_3794_p1[11];
tmp_138_reg_5790[12] <= tmp_138_fu_3794_p1[12];
tmp_138_reg_5790[13] <= tmp_138_fu_3794_p1[13];
end
if (((ap_ST_pp7_stg2_fsm_33 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp7_it0) & (ap_const_lv1_0 == exitcond12_reg_5924))) begin
tmp_141_reg_6047[0] <= tmp_141_fu_4224_p2[0];
tmp_141_reg_6047[1] <= tmp_141_fu_4224_p2[1];
tmp_141_reg_6047[3] <= tmp_141_fu_4224_p2[3];
tmp_141_reg_6047[4] <= tmp_141_fu_4224_p2[4];
tmp_141_reg_6047[5] <= tmp_141_fu_4224_p2[5];
tmp_141_reg_6047[6] <= tmp_141_fu_4224_p2[6];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp5_it0) & (ap_const_lv1_0 == exitcond9_reg_5697) & (ap_ST_pp5_stg2_fsm_24 == ap_CS_fsm))) begin
tmp_146_reg_5805[2] <= tmp_146_fu_3830_p1[2];
tmp_146_reg_5805[3] <= tmp_146_fu_3830_p1[3];
tmp_146_reg_5805[4] <= tmp_146_fu_3830_p1[4];
tmp_146_reg_5805[5] <= tmp_146_fu_3830_p1[5];
tmp_146_reg_5805[6] <= tmp_146_fu_3830_p1[6];
tmp_146_reg_5805[7] <= tmp_146_fu_3830_p1[7];
tmp_146_reg_5805[8] <= tmp_146_fu_3830_p1[8];
tmp_146_reg_5805[9] <= tmp_146_fu_3830_p1[9];
tmp_146_reg_5805[10] <= tmp_146_fu_3830_p1[10];
tmp_146_reg_5805[11] <= tmp_146_fu_3830_p1[11];
tmp_146_reg_5805[12] <= tmp_146_fu_3830_p1[12];
tmp_146_reg_5805[13] <= tmp_146_fu_3830_p1[13];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp7_it0) & (ap_const_lv1_0 == exitcond12_reg_5924) & (ap_ST_pp7_stg4_fsm_35 == ap_CS_fsm))) begin
tmp_149_reg_6082[0] <= tmp_149_fu_4289_p2[0];
tmp_149_reg_6082[3] <= tmp_149_fu_4289_p2[3];
tmp_149_reg_6082[4] <= tmp_149_fu_4289_p2[4];
tmp_149_reg_6082[5] <= tmp_149_fu_4289_p2[5];
tmp_149_reg_6082[6] <= tmp_149_fu_4289_p2[6];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp7_it0) & (ap_const_lv1_0 == exitcond12_reg_5924) & (ap_ST_pp7_stg4_fsm_35 == ap_CS_fsm))) begin
tmp_153_reg_6092[3] <= tmp_153_fu_4308_p2[3];
tmp_153_reg_6092[4] <= tmp_153_fu_4308_p2[4];
tmp_153_reg_6092[5] <= tmp_153_fu_4308_p2[5];
tmp_153_reg_6092[6] <= tmp_153_fu_4308_p2[6];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp5_it0) & (ap_const_lv1_0 == exitcond9_reg_5697) & (ap_ST_pp5_stg2_fsm_24 == ap_CS_fsm))) begin
tmp_154_reg_5825[0] <= tmp_154_fu_3859_p1[0];
tmp_154_reg_5825[1] <= tmp_154_fu_3859_p1[1];
tmp_154_reg_5825[2] <= tmp_154_fu_3859_p1[2];
tmp_154_reg_5825[3] <= tmp_154_fu_3859_p1[3];
tmp_154_reg_5825[4] <= tmp_154_fu_3859_p1[4];
tmp_154_reg_5825[5] <= tmp_154_fu_3859_p1[5];
tmp_154_reg_5825[6] <= tmp_154_fu_3859_p1[6];
tmp_154_reg_5825[7] <= tmp_154_fu_3859_p1[7];
tmp_154_reg_5825[8] <= tmp_154_fu_3859_p1[8];
tmp_154_reg_5825[9] <= tmp_154_fu_3859_p1[9];
tmp_154_reg_5825[10] <= tmp_154_fu_3859_p1[10];
tmp_154_reg_5825[11] <= tmp_154_fu_3859_p1[11];
tmp_154_reg_5825[12] <= tmp_154_fu_3859_p1[12];
tmp_154_reg_5825[13] <= tmp_154_fu_3859_p1[13];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp7_it0) & (ap_const_lv1_0 == exitcond12_reg_5924) & (ap_ST_pp7_stg4_fsm_35 == ap_CS_fsm))) begin
tmp_157_reg_6102 <= (j_5_mid2_reg_5933 + ap_const_lv7_8);
end
if (((ap_ST_pp1_stg1_fsm_5 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond3_reg_5195))) begin
tmp_15_reg_5272[0] <= tmp_15_fu_2560_p1[0];
tmp_15_reg_5272[1] <= tmp_15_fu_2560_p1[1];
tmp_15_reg_5272[2] <= tmp_15_fu_2560_p1[2];
tmp_15_reg_5272[3] <= tmp_15_fu_2560_p1[3];
tmp_15_reg_5272[4] <= tmp_15_fu_2560_p1[4];
tmp_15_reg_5272[5] <= tmp_15_fu_2560_p1[5];
tmp_15_reg_5272[6] <= tmp_15_fu_2560_p1[6];
tmp_15_reg_5272[7] <= tmp_15_fu_2560_p1[7];
tmp_15_reg_5272[8] <= tmp_15_fu_2560_p1[8];
tmp_15_reg_5272[9] <= tmp_15_fu_2560_p1[9];
tmp_15_reg_5272[10] <= tmp_15_fu_2560_p1[10];
tmp_15_reg_5272[11] <= tmp_15_fu_2560_p1[11];
tmp_15_reg_5272[12] <= tmp_15_fu_2560_p1[12];
tmp_15_reg_5272[13] <= tmp_15_fu_2560_p1[13];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp5_it0) & (ap_const_lv1_0 == exitcond9_reg_5697) & (ap_ST_pp5_stg3_fsm_25 == ap_CS_fsm))) begin
tmp_160_reg_5840[1] <= tmp_160_fu_3895_p1[1];
tmp_160_reg_5840[2] <= tmp_160_fu_3895_p1[2];
tmp_160_reg_5840[3] <= tmp_160_fu_3895_p1[3];
tmp_160_reg_5840[4] <= tmp_160_fu_3895_p1[4];
tmp_160_reg_5840[5] <= tmp_160_fu_3895_p1[5];
tmp_160_reg_5840[6] <= tmp_160_fu_3895_p1[6];
tmp_160_reg_5840[7] <= tmp_160_fu_3895_p1[7];
tmp_160_reg_5840[8] <= tmp_160_fu_3895_p1[8];
tmp_160_reg_5840[9] <= tmp_160_fu_3895_p1[9];
tmp_160_reg_5840[10] <= tmp_160_fu_3895_p1[10];
tmp_160_reg_5840[11] <= tmp_160_fu_3895_p1[11];
tmp_160_reg_5840[12] <= tmp_160_fu_3895_p1[12];
tmp_160_reg_5840[13] <= tmp_160_fu_3895_p1[13];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp5_it1) & (ap_ST_pp5_stg3_fsm_25 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond9_reg_5697_pp5_it1))) begin
tmp_164_reg_5880[0] <= tmp_164_fu_3961_p1[0];
tmp_164_reg_5880[1] <= tmp_164_fu_3961_p1[1];
tmp_164_reg_5880[2] <= tmp_164_fu_3961_p1[2];
tmp_164_reg_5880[3] <= tmp_164_fu_3961_p1[3];
tmp_164_reg_5880[4] <= tmp_164_fu_3961_p1[4];
tmp_164_reg_5880[5] <= tmp_164_fu_3961_p1[5];
tmp_164_reg_5880[6] <= tmp_164_fu_3961_p1[6];
tmp_164_reg_5880[7] <= tmp_164_fu_3961_p1[7];
tmp_164_reg_5880[8] <= tmp_164_fu_3961_p1[8];
tmp_164_reg_5880[9] <= tmp_164_fu_3961_p1[9];
tmp_164_reg_5880[10] <= tmp_164_fu_3961_p1[10];
tmp_164_reg_5880[11] <= tmp_164_fu_3961_p1[11];
tmp_164_reg_5880[12] <= tmp_164_fu_3961_p1[12];
tmp_164_reg_5880[13] <= tmp_164_fu_3961_p1[13];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp5_it1) & (ap_ST_pp5_stg4_fsm_26 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond9_reg_5697_pp5_it1))) begin
tmp_168_reg_5895[3] <= tmp_168_fu_3974_p1[3];
tmp_168_reg_5895[4] <= tmp_168_fu_3974_p1[4];
tmp_168_reg_5895[5] <= tmp_168_fu_3974_p1[5];
tmp_168_reg_5895[6] <= tmp_168_fu_3974_p1[6];
tmp_168_reg_5895[7] <= tmp_168_fu_3974_p1[7];
tmp_168_reg_5895[8] <= tmp_168_fu_3974_p1[8];
tmp_168_reg_5895[9] <= tmp_168_fu_3974_p1[9];
tmp_168_reg_5895[10] <= tmp_168_fu_3974_p1[10];
tmp_168_reg_5895[11] <= tmp_168_fu_3974_p1[11];
tmp_168_reg_5895[12] <= tmp_168_fu_3974_p1[12];
tmp_168_reg_5895[13] <= tmp_168_fu_3974_p1[13];
end
if (((ap_ST_pp6_stg0_fsm_30 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp6_it0) & (ap_const_lv1_0 == exitcond10_fu_3978_p2))) begin
tmp_172_reg_5914[0] <= tmp_172_fu_4000_p1[0];
tmp_172_reg_5914[1] <= tmp_172_fu_4000_p1[1];
tmp_172_reg_5914[2] <= tmp_172_fu_4000_p1[2];
tmp_172_reg_5914[3] <= tmp_172_fu_4000_p1[3];
tmp_172_reg_5914[4] <= tmp_172_fu_4000_p1[4];
tmp_172_reg_5914[5] <= tmp_172_fu_4000_p1[5];
tmp_172_reg_5914[6] <= tmp_172_fu_4000_p1[6];
tmp_172_reg_5914[7] <= tmp_172_fu_4000_p1[7];
tmp_172_reg_5914[8] <= tmp_172_fu_4000_p1[8];
tmp_172_reg_5914[9] <= tmp_172_fu_4000_p1[9];
tmp_172_reg_5914[10] <= tmp_172_fu_4000_p1[10];
tmp_172_reg_5914[11] <= tmp_172_fu_4000_p1[11];
tmp_172_reg_5914[12] <= tmp_172_fu_4000_p1[12];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp7_it0) & (ap_ST_pp7_stg0_fsm_31 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond12_fu_4005_p2))) begin
tmp_174_reg_5967 <= {{50{b_addr37_fu_4067_p2[13]}}, {b_addr37_fu_4067_p2}};
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_ST_pp8_stg1_fsm_41 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond_reg_6132))) begin
tmp_176_trn_cast_reg_6191[1] <= tmp_176_trn_cast_fu_4445_p1[1];
tmp_176_trn_cast_reg_6191[2] <= tmp_176_trn_cast_fu_4445_p1[2];
tmp_176_trn_cast_reg_6191[3] <= tmp_176_trn_cast_fu_4445_p1[3];
tmp_176_trn_cast_reg_6191[4] <= tmp_176_trn_cast_fu_4445_p1[4];
tmp_176_trn_cast_reg_6191[5] <= tmp_176_trn_cast_fu_4445_p1[5];
tmp_176_trn_cast_reg_6191[6] <= tmp_176_trn_cast_fu_4445_p1[6];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp7_it0) & (ap_const_lv1_0 == exitcond12_reg_5924) & (ap_ST_pp7_stg1_fsm_32 == ap_CS_fsm))) begin
tmp_178_reg_5997[1] <= tmp_178_fu_4143_p1[1];
tmp_178_reg_5997[2] <= tmp_178_fu_4143_p1[2];
tmp_178_reg_5997[3] <= tmp_178_fu_4143_p1[3];
tmp_178_reg_5997[4] <= tmp_178_fu_4143_p1[4];
tmp_178_reg_5997[5] <= tmp_178_fu_4143_p1[5];
tmp_178_reg_5997[6] <= tmp_178_fu_4143_p1[6];
tmp_178_reg_5997[7] <= tmp_178_fu_4143_p1[7];
tmp_178_reg_5997[8] <= tmp_178_fu_4143_p1[8];
tmp_178_reg_5997[9] <= tmp_178_fu_4143_p1[9];
tmp_178_reg_5997[10] <= tmp_178_fu_4143_p1[10];
tmp_178_reg_5997[11] <= tmp_178_fu_4143_p1[11];
tmp_178_reg_5997[12] <= tmp_178_fu_4143_p1[12];
tmp_178_reg_5997[13] <= tmp_178_fu_4143_p1[13];
tmp_178_reg_5997[14] <= tmp_178_fu_4143_p1[14];
tmp_178_reg_5997[15] <= tmp_178_fu_4143_p1[15];
tmp_178_reg_5997[16] <= tmp_178_fu_4143_p1[16];
tmp_178_reg_5997[17] <= tmp_178_fu_4143_p1[17];
tmp_178_reg_5997[18] <= tmp_178_fu_4143_p1[18];
tmp_178_reg_5997[19] <= tmp_178_fu_4143_p1[19];
tmp_178_reg_5997[20] <= tmp_178_fu_4143_p1[20];
tmp_178_reg_5997[21] <= tmp_178_fu_4143_p1[21];
tmp_178_reg_5997[22] <= tmp_178_fu_4143_p1[22];
tmp_178_reg_5997[23] <= tmp_178_fu_4143_p1[23];
tmp_178_reg_5997[24] <= tmp_178_fu_4143_p1[24];
tmp_178_reg_5997[25] <= tmp_178_fu_4143_p1[25];
tmp_178_reg_5997[26] <= tmp_178_fu_4143_p1[26];
tmp_178_reg_5997[27] <= tmp_178_fu_4143_p1[27];
tmp_178_reg_5997[28] <= tmp_178_fu_4143_p1[28];
tmp_178_reg_5997[29] <= tmp_178_fu_4143_p1[29];
tmp_178_reg_5997[30] <= tmp_178_fu_4143_p1[30];
tmp_178_reg_5997[31] <= tmp_178_fu_4143_p1[31];
tmp_178_reg_5997[32] <= tmp_178_fu_4143_p1[32];
tmp_178_reg_5997[33] <= tmp_178_fu_4143_p1[33];
tmp_178_reg_5997[34] <= tmp_178_fu_4143_p1[34];
tmp_178_reg_5997[35] <= tmp_178_fu_4143_p1[35];
tmp_178_reg_5997[36] <= tmp_178_fu_4143_p1[36];
tmp_178_reg_5997[37] <= tmp_178_fu_4143_p1[37];
tmp_178_reg_5997[38] <= tmp_178_fu_4143_p1[38];
tmp_178_reg_5997[39] <= tmp_178_fu_4143_p1[39];
tmp_178_reg_5997[40] <= tmp_178_fu_4143_p1[40];
tmp_178_reg_5997[41] <= tmp_178_fu_4143_p1[41];
tmp_178_reg_5997[42] <= tmp_178_fu_4143_p1[42];
tmp_178_reg_5997[43] <= tmp_178_fu_4143_p1[43];
tmp_178_reg_5997[44] <= tmp_178_fu_4143_p1[44];
tmp_178_reg_5997[45] <= tmp_178_fu_4143_p1[45];
tmp_178_reg_5997[46] <= tmp_178_fu_4143_p1[46];
tmp_178_reg_5997[47] <= tmp_178_fu_4143_p1[47];
tmp_178_reg_5997[48] <= tmp_178_fu_4143_p1[48];
tmp_178_reg_5997[49] <= tmp_178_fu_4143_p1[49];
tmp_178_reg_5997[50] <= tmp_178_fu_4143_p1[50];
tmp_178_reg_5997[51] <= tmp_178_fu_4143_p1[51];
tmp_178_reg_5997[52] <= tmp_178_fu_4143_p1[52];
tmp_178_reg_5997[53] <= tmp_178_fu_4143_p1[53];
tmp_178_reg_5997[54] <= tmp_178_fu_4143_p1[54];
tmp_178_reg_5997[55] <= tmp_178_fu_4143_p1[55];
tmp_178_reg_5997[56] <= tmp_178_fu_4143_p1[56];
tmp_178_reg_5997[57] <= tmp_178_fu_4143_p1[57];
tmp_178_reg_5997[58] <= tmp_178_fu_4143_p1[58];
tmp_178_reg_5997[59] <= tmp_178_fu_4143_p1[59];
tmp_178_reg_5997[60] <= tmp_178_fu_4143_p1[60];
tmp_178_reg_5997[61] <= tmp_178_fu_4143_p1[61];
tmp_178_reg_5997[62] <= tmp_178_fu_4143_p1[62];
tmp_178_reg_5997[63] <= tmp_178_fu_4143_p1[63];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_ST_pp8_stg1_fsm_41 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond_reg_6132))) begin
tmp_178_trn_cast_reg_6212[0] <= tmp_178_trn_cast_fu_4464_p1[0];
tmp_178_trn_cast_reg_6212[2] <= tmp_178_trn_cast_fu_4464_p1[2];
tmp_178_trn_cast_reg_6212[3] <= tmp_178_trn_cast_fu_4464_p1[3];
tmp_178_trn_cast_reg_6212[4] <= tmp_178_trn_cast_fu_4464_p1[4];
tmp_178_trn_cast_reg_6212[5] <= tmp_178_trn_cast_fu_4464_p1[5];
tmp_178_trn_cast_reg_6212[6] <= tmp_178_trn_cast_fu_4464_p1[6];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg2_fsm_42 == ap_CS_fsm))) begin
tmp_180_trn_cast_reg_6233[2] <= tmp_180_trn_cast_fu_4483_p1[2];
tmp_180_trn_cast_reg_6233[3] <= tmp_180_trn_cast_fu_4483_p1[3];
tmp_180_trn_cast_reg_6233[4] <= tmp_180_trn_cast_fu_4483_p1[4];
tmp_180_trn_cast_reg_6233[5] <= tmp_180_trn_cast_fu_4483_p1[5];
tmp_180_trn_cast_reg_6233[6] <= tmp_180_trn_cast_fu_4483_p1[6];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp7_it0) & (ap_const_lv1_0 == exitcond12_reg_5924) & (ap_ST_pp7_stg1_fsm_32 == ap_CS_fsm))) begin
tmp_182_reg_6017 <= {{50{b_addr39_fu_4168_p2[13]}}, {b_addr39_fu_4168_p2}};
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg2_fsm_42 == ap_CS_fsm))) begin
tmp_182_trn_cast_reg_6254[0] <= tmp_182_trn_cast_fu_4502_p1[0];
tmp_182_trn_cast_reg_6254[1] <= tmp_182_trn_cast_fu_4502_p1[1];
tmp_182_trn_cast_reg_6254[3] <= tmp_182_trn_cast_fu_4502_p1[3];
tmp_182_trn_cast_reg_6254[4] <= tmp_182_trn_cast_fu_4502_p1[4];
tmp_182_trn_cast_reg_6254[5] <= tmp_182_trn_cast_fu_4502_p1[5];
tmp_182_trn_cast_reg_6254[6] <= tmp_182_trn_cast_fu_4502_p1[6];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg3_fsm_43 == ap_CS_fsm))) begin
tmp_184_trn_cast_reg_6275[1] <= tmp_184_trn_cast_fu_4521_p1[1];
tmp_184_trn_cast_reg_6275[3] <= tmp_184_trn_cast_fu_4521_p1[3];
tmp_184_trn_cast_reg_6275[4] <= tmp_184_trn_cast_fu_4521_p1[4];
tmp_184_trn_cast_reg_6275[5] <= tmp_184_trn_cast_fu_4521_p1[5];
tmp_184_trn_cast_reg_6275[6] <= tmp_184_trn_cast_fu_4521_p1[6];
end
if (((ap_ST_pp7_stg2_fsm_33 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp7_it0) & (ap_const_lv1_0 == exitcond12_reg_5924))) begin
tmp_186_reg_6032[2] <= tmp_186_fu_4209_p1[2];
tmp_186_reg_6032[3] <= tmp_186_fu_4209_p1[3];
tmp_186_reg_6032[4] <= tmp_186_fu_4209_p1[4];
tmp_186_reg_6032[5] <= tmp_186_fu_4209_p1[5];
tmp_186_reg_6032[6] <= tmp_186_fu_4209_p1[6];
tmp_186_reg_6032[7] <= tmp_186_fu_4209_p1[7];
tmp_186_reg_6032[8] <= tmp_186_fu_4209_p1[8];
tmp_186_reg_6032[9] <= tmp_186_fu_4209_p1[9];
tmp_186_reg_6032[10] <= tmp_186_fu_4209_p1[10];
tmp_186_reg_6032[11] <= tmp_186_fu_4209_p1[11];
tmp_186_reg_6032[12] <= tmp_186_fu_4209_p1[12];
tmp_186_reg_6032[13] <= tmp_186_fu_4209_p1[13];
tmp_186_reg_6032[14] <= tmp_186_fu_4209_p1[14];
tmp_186_reg_6032[15] <= tmp_186_fu_4209_p1[15];
tmp_186_reg_6032[16] <= tmp_186_fu_4209_p1[16];
tmp_186_reg_6032[17] <= tmp_186_fu_4209_p1[17];
tmp_186_reg_6032[18] <= tmp_186_fu_4209_p1[18];
tmp_186_reg_6032[19] <= tmp_186_fu_4209_p1[19];
tmp_186_reg_6032[20] <= tmp_186_fu_4209_p1[20];
tmp_186_reg_6032[21] <= tmp_186_fu_4209_p1[21];
tmp_186_reg_6032[22] <= tmp_186_fu_4209_p1[22];
tmp_186_reg_6032[23] <= tmp_186_fu_4209_p1[23];
tmp_186_reg_6032[24] <= tmp_186_fu_4209_p1[24];
tmp_186_reg_6032[25] <= tmp_186_fu_4209_p1[25];
tmp_186_reg_6032[26] <= tmp_186_fu_4209_p1[26];
tmp_186_reg_6032[27] <= tmp_186_fu_4209_p1[27];
tmp_186_reg_6032[28] <= tmp_186_fu_4209_p1[28];
tmp_186_reg_6032[29] <= tmp_186_fu_4209_p1[29];
tmp_186_reg_6032[30] <= tmp_186_fu_4209_p1[30];
tmp_186_reg_6032[31] <= tmp_186_fu_4209_p1[31];
tmp_186_reg_6032[32] <= tmp_186_fu_4209_p1[32];
tmp_186_reg_6032[33] <= tmp_186_fu_4209_p1[33];
tmp_186_reg_6032[34] <= tmp_186_fu_4209_p1[34];
tmp_186_reg_6032[35] <= tmp_186_fu_4209_p1[35];
tmp_186_reg_6032[36] <= tmp_186_fu_4209_p1[36];
tmp_186_reg_6032[37] <= tmp_186_fu_4209_p1[37];
tmp_186_reg_6032[38] <= tmp_186_fu_4209_p1[38];
tmp_186_reg_6032[39] <= tmp_186_fu_4209_p1[39];
tmp_186_reg_6032[40] <= tmp_186_fu_4209_p1[40];
tmp_186_reg_6032[41] <= tmp_186_fu_4209_p1[41];
tmp_186_reg_6032[42] <= tmp_186_fu_4209_p1[42];
tmp_186_reg_6032[43] <= tmp_186_fu_4209_p1[43];
tmp_186_reg_6032[44] <= tmp_186_fu_4209_p1[44];
tmp_186_reg_6032[45] <= tmp_186_fu_4209_p1[45];
tmp_186_reg_6032[46] <= tmp_186_fu_4209_p1[46];
tmp_186_reg_6032[47] <= tmp_186_fu_4209_p1[47];
tmp_186_reg_6032[48] <= tmp_186_fu_4209_p1[48];
tmp_186_reg_6032[49] <= tmp_186_fu_4209_p1[49];
tmp_186_reg_6032[50] <= tmp_186_fu_4209_p1[50];
tmp_186_reg_6032[51] <= tmp_186_fu_4209_p1[51];
tmp_186_reg_6032[52] <= tmp_186_fu_4209_p1[52];
tmp_186_reg_6032[53] <= tmp_186_fu_4209_p1[53];
tmp_186_reg_6032[54] <= tmp_186_fu_4209_p1[54];
tmp_186_reg_6032[55] <= tmp_186_fu_4209_p1[55];
tmp_186_reg_6032[56] <= tmp_186_fu_4209_p1[56];
tmp_186_reg_6032[57] <= tmp_186_fu_4209_p1[57];
tmp_186_reg_6032[58] <= tmp_186_fu_4209_p1[58];
tmp_186_reg_6032[59] <= tmp_186_fu_4209_p1[59];
tmp_186_reg_6032[60] <= tmp_186_fu_4209_p1[60];
tmp_186_reg_6032[61] <= tmp_186_fu_4209_p1[61];
tmp_186_reg_6032[62] <= tmp_186_fu_4209_p1[62];
tmp_186_reg_6032[63] <= tmp_186_fu_4209_p1[63];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg3_fsm_43 == ap_CS_fsm))) begin
tmp_186_trn_cast_reg_6296[0] <= tmp_186_trn_cast_fu_4540_p1[0];
tmp_186_trn_cast_reg_6296[3] <= tmp_186_trn_cast_fu_4540_p1[3];
tmp_186_trn_cast_reg_6296[4] <= tmp_186_trn_cast_fu_4540_p1[4];
tmp_186_trn_cast_reg_6296[5] <= tmp_186_trn_cast_fu_4540_p1[5];
tmp_186_trn_cast_reg_6296[6] <= tmp_186_trn_cast_fu_4540_p1[6];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg4_fsm_44 == ap_CS_fsm))) begin
tmp_188_trn_cast_reg_6317[3] <= tmp_188_trn_cast_fu_4564_p1[3];
tmp_188_trn_cast_reg_6317[4] <= tmp_188_trn_cast_fu_4564_p1[4];
tmp_188_trn_cast_reg_6317[5] <= tmp_188_trn_cast_fu_4564_p1[5];
tmp_188_trn_cast_reg_6317[6] <= tmp_188_trn_cast_fu_4564_p1[6];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg4_fsm_44 == ap_CS_fsm))) begin
tmp_189_reg_6358 <= (j_6_mid2_reg_6141 + ap_const_lv7_8);
end
if (((ap_ST_pp7_stg2_fsm_33 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp7_it0) & (ap_const_lv1_0 == exitcond12_reg_5924))) begin
tmp_190_reg_6052 <= {{50{b_addr41_fu_4233_p2[13]}}, {b_addr41_fu_4233_p2}};
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp7_it0) & (ap_const_lv1_0 == exitcond12_reg_5924) & (ap_ST_pp7_stg3_fsm_34 == ap_CS_fsm))) begin
tmp_192_reg_6067[1] <= tmp_192_fu_4274_p1[1];
tmp_192_reg_6067[2] <= tmp_192_fu_4274_p1[2];
tmp_192_reg_6067[3] <= tmp_192_fu_4274_p1[3];
tmp_192_reg_6067[4] <= tmp_192_fu_4274_p1[4];
tmp_192_reg_6067[5] <= tmp_192_fu_4274_p1[5];
tmp_192_reg_6067[6] <= tmp_192_fu_4274_p1[6];
tmp_192_reg_6067[7] <= tmp_192_fu_4274_p1[7];
tmp_192_reg_6067[8] <= tmp_192_fu_4274_p1[8];
tmp_192_reg_6067[9] <= tmp_192_fu_4274_p1[9];
tmp_192_reg_6067[10] <= tmp_192_fu_4274_p1[10];
tmp_192_reg_6067[11] <= tmp_192_fu_4274_p1[11];
tmp_192_reg_6067[12] <= tmp_192_fu_4274_p1[12];
tmp_192_reg_6067[13] <= tmp_192_fu_4274_p1[13];
tmp_192_reg_6067[14] <= tmp_192_fu_4274_p1[14];
tmp_192_reg_6067[15] <= tmp_192_fu_4274_p1[15];
tmp_192_reg_6067[16] <= tmp_192_fu_4274_p1[16];
tmp_192_reg_6067[17] <= tmp_192_fu_4274_p1[17];
tmp_192_reg_6067[18] <= tmp_192_fu_4274_p1[18];
tmp_192_reg_6067[19] <= tmp_192_fu_4274_p1[19];
tmp_192_reg_6067[20] <= tmp_192_fu_4274_p1[20];
tmp_192_reg_6067[21] <= tmp_192_fu_4274_p1[21];
tmp_192_reg_6067[22] <= tmp_192_fu_4274_p1[22];
tmp_192_reg_6067[23] <= tmp_192_fu_4274_p1[23];
tmp_192_reg_6067[24] <= tmp_192_fu_4274_p1[24];
tmp_192_reg_6067[25] <= tmp_192_fu_4274_p1[25];
tmp_192_reg_6067[26] <= tmp_192_fu_4274_p1[26];
tmp_192_reg_6067[27] <= tmp_192_fu_4274_p1[27];
tmp_192_reg_6067[28] <= tmp_192_fu_4274_p1[28];
tmp_192_reg_6067[29] <= tmp_192_fu_4274_p1[29];
tmp_192_reg_6067[30] <= tmp_192_fu_4274_p1[30];
tmp_192_reg_6067[31] <= tmp_192_fu_4274_p1[31];
tmp_192_reg_6067[32] <= tmp_192_fu_4274_p1[32];
tmp_192_reg_6067[33] <= tmp_192_fu_4274_p1[33];
tmp_192_reg_6067[34] <= tmp_192_fu_4274_p1[34];
tmp_192_reg_6067[35] <= tmp_192_fu_4274_p1[35];
tmp_192_reg_6067[36] <= tmp_192_fu_4274_p1[36];
tmp_192_reg_6067[37] <= tmp_192_fu_4274_p1[37];
tmp_192_reg_6067[38] <= tmp_192_fu_4274_p1[38];
tmp_192_reg_6067[39] <= tmp_192_fu_4274_p1[39];
tmp_192_reg_6067[40] <= tmp_192_fu_4274_p1[40];
tmp_192_reg_6067[41] <= tmp_192_fu_4274_p1[41];
tmp_192_reg_6067[42] <= tmp_192_fu_4274_p1[42];
tmp_192_reg_6067[43] <= tmp_192_fu_4274_p1[43];
tmp_192_reg_6067[44] <= tmp_192_fu_4274_p1[44];
tmp_192_reg_6067[45] <= tmp_192_fu_4274_p1[45];
tmp_192_reg_6067[46] <= tmp_192_fu_4274_p1[46];
tmp_192_reg_6067[47] <= tmp_192_fu_4274_p1[47];
tmp_192_reg_6067[48] <= tmp_192_fu_4274_p1[48];
tmp_192_reg_6067[49] <= tmp_192_fu_4274_p1[49];
tmp_192_reg_6067[50] <= tmp_192_fu_4274_p1[50];
tmp_192_reg_6067[51] <= tmp_192_fu_4274_p1[51];
tmp_192_reg_6067[52] <= tmp_192_fu_4274_p1[52];
tmp_192_reg_6067[53] <= tmp_192_fu_4274_p1[53];
tmp_192_reg_6067[54] <= tmp_192_fu_4274_p1[54];
tmp_192_reg_6067[55] <= tmp_192_fu_4274_p1[55];
tmp_192_reg_6067[56] <= tmp_192_fu_4274_p1[56];
tmp_192_reg_6067[57] <= tmp_192_fu_4274_p1[57];
tmp_192_reg_6067[58] <= tmp_192_fu_4274_p1[58];
tmp_192_reg_6067[59] <= tmp_192_fu_4274_p1[59];
tmp_192_reg_6067[60] <= tmp_192_fu_4274_p1[60];
tmp_192_reg_6067[61] <= tmp_192_fu_4274_p1[61];
tmp_192_reg_6067[62] <= tmp_192_fu_4274_p1[62];
tmp_192_reg_6067[63] <= tmp_192_fu_4274_p1[63];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp7_it1) & (ap_ST_pp7_stg3_fsm_34 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond12_reg_5924_pp7_it1))) begin
tmp_194_reg_6107 <= {{50{b_addr43_fu_4335_p2[13]}}, {b_addr43_fu_4335_p2}};
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp7_it1) & (ap_ST_pp7_stg4_fsm_35 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond12_reg_5924_pp7_it1))) begin
tmp_197_reg_6122[3] <= tmp_197_fu_4353_p1[3];
tmp_197_reg_6122[4] <= tmp_197_fu_4353_p1[4];
tmp_197_reg_6122[5] <= tmp_197_fu_4353_p1[5];
tmp_197_reg_6122[6] <= tmp_197_fu_4353_p1[6];
tmp_197_reg_6122[7] <= tmp_197_fu_4353_p1[7];
tmp_197_reg_6122[8] <= tmp_197_fu_4353_p1[8];
tmp_197_reg_6122[9] <= tmp_197_fu_4353_p1[9];
tmp_197_reg_6122[10] <= tmp_197_fu_4353_p1[10];
tmp_197_reg_6122[11] <= tmp_197_fu_4353_p1[11];
tmp_197_reg_6122[12] <= tmp_197_fu_4353_p1[12];
tmp_197_reg_6122[13] <= tmp_197_fu_4353_p1[13];
tmp_197_reg_6122[14] <= tmp_197_fu_4353_p1[14];
tmp_197_reg_6122[15] <= tmp_197_fu_4353_p1[15];
tmp_197_reg_6122[16] <= tmp_197_fu_4353_p1[16];
tmp_197_reg_6122[17] <= tmp_197_fu_4353_p1[17];
tmp_197_reg_6122[18] <= tmp_197_fu_4353_p1[18];
tmp_197_reg_6122[19] <= tmp_197_fu_4353_p1[19];
tmp_197_reg_6122[20] <= tmp_197_fu_4353_p1[20];
tmp_197_reg_6122[21] <= tmp_197_fu_4353_p1[21];
tmp_197_reg_6122[22] <= tmp_197_fu_4353_p1[22];
tmp_197_reg_6122[23] <= tmp_197_fu_4353_p1[23];
tmp_197_reg_6122[24] <= tmp_197_fu_4353_p1[24];
tmp_197_reg_6122[25] <= tmp_197_fu_4353_p1[25];
tmp_197_reg_6122[26] <= tmp_197_fu_4353_p1[26];
tmp_197_reg_6122[27] <= tmp_197_fu_4353_p1[27];
tmp_197_reg_6122[28] <= tmp_197_fu_4353_p1[28];
tmp_197_reg_6122[29] <= tmp_197_fu_4353_p1[29];
tmp_197_reg_6122[30] <= tmp_197_fu_4353_p1[30];
tmp_197_reg_6122[31] <= tmp_197_fu_4353_p1[31];
tmp_197_reg_6122[32] <= tmp_197_fu_4353_p1[32];
tmp_197_reg_6122[33] <= tmp_197_fu_4353_p1[33];
tmp_197_reg_6122[34] <= tmp_197_fu_4353_p1[34];
tmp_197_reg_6122[35] <= tmp_197_fu_4353_p1[35];
tmp_197_reg_6122[36] <= tmp_197_fu_4353_p1[36];
tmp_197_reg_6122[37] <= tmp_197_fu_4353_p1[37];
tmp_197_reg_6122[38] <= tmp_197_fu_4353_p1[38];
tmp_197_reg_6122[39] <= tmp_197_fu_4353_p1[39];
tmp_197_reg_6122[40] <= tmp_197_fu_4353_p1[40];
tmp_197_reg_6122[41] <= tmp_197_fu_4353_p1[41];
tmp_197_reg_6122[42] <= tmp_197_fu_4353_p1[42];
tmp_197_reg_6122[43] <= tmp_197_fu_4353_p1[43];
tmp_197_reg_6122[44] <= tmp_197_fu_4353_p1[44];
tmp_197_reg_6122[45] <= tmp_197_fu_4353_p1[45];
tmp_197_reg_6122[46] <= tmp_197_fu_4353_p1[46];
tmp_197_reg_6122[47] <= tmp_197_fu_4353_p1[47];
tmp_197_reg_6122[48] <= tmp_197_fu_4353_p1[48];
tmp_197_reg_6122[49] <= tmp_197_fu_4353_p1[49];
tmp_197_reg_6122[50] <= tmp_197_fu_4353_p1[50];
tmp_197_reg_6122[51] <= tmp_197_fu_4353_p1[51];
tmp_197_reg_6122[52] <= tmp_197_fu_4353_p1[52];
tmp_197_reg_6122[53] <= tmp_197_fu_4353_p1[53];
tmp_197_reg_6122[54] <= tmp_197_fu_4353_p1[54];
tmp_197_reg_6122[55] <= tmp_197_fu_4353_p1[55];
tmp_197_reg_6122[56] <= tmp_197_fu_4353_p1[56];
tmp_197_reg_6122[57] <= tmp_197_fu_4353_p1[57];
tmp_197_reg_6122[58] <= tmp_197_fu_4353_p1[58];
tmp_197_reg_6122[59] <= tmp_197_fu_4353_p1[59];
tmp_197_reg_6122[60] <= tmp_197_fu_4353_p1[60];
tmp_197_reg_6122[61] <= tmp_197_fu_4353_p1[61];
tmp_197_reg_6122[62] <= tmp_197_fu_4353_p1[62];
tmp_197_reg_6122[63] <= tmp_197_fu_4353_p1[63];
end
if (((ap_ST_pp8_stg0_fsm_40 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_fu_4357_p2))) begin
tmp_199_reg_6176[0] <= tmp_199_fu_4421_p1[0];
tmp_199_reg_6176[1] <= tmp_199_fu_4421_p1[1];
tmp_199_reg_6176[2] <= tmp_199_fu_4421_p1[2];
tmp_199_reg_6176[3] <= tmp_199_fu_4421_p1[3];
tmp_199_reg_6176[4] <= tmp_199_fu_4421_p1[4];
tmp_199_reg_6176[5] <= tmp_199_fu_4421_p1[5];
tmp_199_reg_6176[6] <= tmp_199_fu_4421_p1[6];
tmp_199_reg_6176[7] <= tmp_199_fu_4421_p1[7];
tmp_199_reg_6176[8] <= tmp_199_fu_4421_p1[8];
tmp_199_reg_6176[9] <= tmp_199_fu_4421_p1[9];
tmp_199_reg_6176[10] <= tmp_199_fu_4421_p1[10];
tmp_199_reg_6176[11] <= tmp_199_fu_4421_p1[11];
tmp_199_reg_6176[12] <= tmp_199_fu_4421_p1[12];
tmp_199_reg_6176[13] <= tmp_199_fu_4421_p1[13];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_ST_pp8_stg1_fsm_41 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond_reg_6132))) begin
tmp_200_reg_6202[1] <= tmp_200_fu_4454_p1[1];
tmp_200_reg_6202[2] <= tmp_200_fu_4454_p1[2];
tmp_200_reg_6202[3] <= tmp_200_fu_4454_p1[3];
tmp_200_reg_6202[4] <= tmp_200_fu_4454_p1[4];
tmp_200_reg_6202[5] <= tmp_200_fu_4454_p1[5];
tmp_200_reg_6202[6] <= tmp_200_fu_4454_p1[6];
tmp_200_reg_6202[7] <= tmp_200_fu_4454_p1[7];
tmp_200_reg_6202[8] <= tmp_200_fu_4454_p1[8];
tmp_200_reg_6202[9] <= tmp_200_fu_4454_p1[9];
tmp_200_reg_6202[10] <= tmp_200_fu_4454_p1[10];
tmp_200_reg_6202[11] <= tmp_200_fu_4454_p1[11];
tmp_200_reg_6202[12] <= tmp_200_fu_4454_p1[12];
tmp_200_reg_6202[13] <= tmp_200_fu_4454_p1[13];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_ST_pp8_stg1_fsm_41 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond_reg_6132))) begin
tmp_201_reg_6223[0] <= tmp_201_fu_4473_p1[0];
tmp_201_reg_6223[1] <= tmp_201_fu_4473_p1[1];
tmp_201_reg_6223[2] <= tmp_201_fu_4473_p1[2];
tmp_201_reg_6223[3] <= tmp_201_fu_4473_p1[3];
tmp_201_reg_6223[4] <= tmp_201_fu_4473_p1[4];
tmp_201_reg_6223[5] <= tmp_201_fu_4473_p1[5];
tmp_201_reg_6223[6] <= tmp_201_fu_4473_p1[6];
tmp_201_reg_6223[7] <= tmp_201_fu_4473_p1[7];
tmp_201_reg_6223[8] <= tmp_201_fu_4473_p1[8];
tmp_201_reg_6223[9] <= tmp_201_fu_4473_p1[9];
tmp_201_reg_6223[10] <= tmp_201_fu_4473_p1[10];
tmp_201_reg_6223[11] <= tmp_201_fu_4473_p1[11];
tmp_201_reg_6223[12] <= tmp_201_fu_4473_p1[12];
tmp_201_reg_6223[13] <= tmp_201_fu_4473_p1[13];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg2_fsm_42 == ap_CS_fsm))) begin
tmp_202_reg_6244[2] <= tmp_202_fu_4492_p1[2];
tmp_202_reg_6244[3] <= tmp_202_fu_4492_p1[3];
tmp_202_reg_6244[4] <= tmp_202_fu_4492_p1[4];
tmp_202_reg_6244[5] <= tmp_202_fu_4492_p1[5];
tmp_202_reg_6244[6] <= tmp_202_fu_4492_p1[6];
tmp_202_reg_6244[7] <= tmp_202_fu_4492_p1[7];
tmp_202_reg_6244[8] <= tmp_202_fu_4492_p1[8];
tmp_202_reg_6244[9] <= tmp_202_fu_4492_p1[9];
tmp_202_reg_6244[10] <= tmp_202_fu_4492_p1[10];
tmp_202_reg_6244[11] <= tmp_202_fu_4492_p1[11];
tmp_202_reg_6244[12] <= tmp_202_fu_4492_p1[12];
tmp_202_reg_6244[13] <= tmp_202_fu_4492_p1[13];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg2_fsm_42 == ap_CS_fsm))) begin
tmp_203_reg_6265[0] <= tmp_203_fu_4511_p1[0];
tmp_203_reg_6265[1] <= tmp_203_fu_4511_p1[1];
tmp_203_reg_6265[2] <= tmp_203_fu_4511_p1[2];
tmp_203_reg_6265[3] <= tmp_203_fu_4511_p1[3];
tmp_203_reg_6265[4] <= tmp_203_fu_4511_p1[4];
tmp_203_reg_6265[5] <= tmp_203_fu_4511_p1[5];
tmp_203_reg_6265[6] <= tmp_203_fu_4511_p1[6];
tmp_203_reg_6265[7] <= tmp_203_fu_4511_p1[7];
tmp_203_reg_6265[8] <= tmp_203_fu_4511_p1[8];
tmp_203_reg_6265[9] <= tmp_203_fu_4511_p1[9];
tmp_203_reg_6265[10] <= tmp_203_fu_4511_p1[10];
tmp_203_reg_6265[11] <= tmp_203_fu_4511_p1[11];
tmp_203_reg_6265[12] <= tmp_203_fu_4511_p1[12];
tmp_203_reg_6265[13] <= tmp_203_fu_4511_p1[13];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg3_fsm_43 == ap_CS_fsm))) begin
tmp_204_reg_6286[1] <= tmp_204_fu_4530_p1[1];
tmp_204_reg_6286[2] <= tmp_204_fu_4530_p1[2];
tmp_204_reg_6286[3] <= tmp_204_fu_4530_p1[3];
tmp_204_reg_6286[4] <= tmp_204_fu_4530_p1[4];
tmp_204_reg_6286[5] <= tmp_204_fu_4530_p1[5];
tmp_204_reg_6286[6] <= tmp_204_fu_4530_p1[6];
tmp_204_reg_6286[7] <= tmp_204_fu_4530_p1[7];
tmp_204_reg_6286[8] <= tmp_204_fu_4530_p1[8];
tmp_204_reg_6286[9] <= tmp_204_fu_4530_p1[9];
tmp_204_reg_6286[10] <= tmp_204_fu_4530_p1[10];
tmp_204_reg_6286[11] <= tmp_204_fu_4530_p1[11];
tmp_204_reg_6286[12] <= tmp_204_fu_4530_p1[12];
tmp_204_reg_6286[13] <= tmp_204_fu_4530_p1[13];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg3_fsm_43 == ap_CS_fsm))) begin
tmp_205_reg_6307[0] <= tmp_205_fu_4549_p1[0];
tmp_205_reg_6307[1] <= tmp_205_fu_4549_p1[1];
tmp_205_reg_6307[2] <= tmp_205_fu_4549_p1[2];
tmp_205_reg_6307[3] <= tmp_205_fu_4549_p1[3];
tmp_205_reg_6307[4] <= tmp_205_fu_4549_p1[4];
tmp_205_reg_6307[5] <= tmp_205_fu_4549_p1[5];
tmp_205_reg_6307[6] <= tmp_205_fu_4549_p1[6];
tmp_205_reg_6307[7] <= tmp_205_fu_4549_p1[7];
tmp_205_reg_6307[8] <= tmp_205_fu_4549_p1[8];
tmp_205_reg_6307[9] <= tmp_205_fu_4549_p1[9];
tmp_205_reg_6307[10] <= tmp_205_fu_4549_p1[10];
tmp_205_reg_6307[11] <= tmp_205_fu_4549_p1[11];
tmp_205_reg_6307[12] <= tmp_205_fu_4549_p1[12];
tmp_205_reg_6307[13] <= tmp_205_fu_4549_p1[13];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg4_fsm_44 == ap_CS_fsm))) begin
tmp_206_reg_6328[3] <= tmp_206_fu_4573_p1[3];
tmp_206_reg_6328[4] <= tmp_206_fu_4573_p1[4];
tmp_206_reg_6328[5] <= tmp_206_fu_4573_p1[5];
tmp_206_reg_6328[6] <= tmp_206_fu_4573_p1[6];
tmp_206_reg_6328[7] <= tmp_206_fu_4573_p1[7];
tmp_206_reg_6328[8] <= tmp_206_fu_4573_p1[8];
tmp_206_reg_6328[9] <= tmp_206_fu_4573_p1[9];
tmp_206_reg_6328[10] <= tmp_206_fu_4573_p1[10];
tmp_206_reg_6328[11] <= tmp_206_fu_4573_p1[11];
tmp_206_reg_6328[12] <= tmp_206_fu_4573_p1[12];
tmp_206_reg_6328[13] <= tmp_206_fu_4573_p1[13];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg4_fsm_44 == ap_CS_fsm))) begin
tmp_207_reg_6348[1] <= tmp_207_fu_4597_p1[1];
tmp_207_reg_6348[2] <= tmp_207_fu_4597_p1[2];
tmp_207_reg_6348[3] <= tmp_207_fu_4597_p1[3];
tmp_207_reg_6348[4] <= tmp_207_fu_4597_p1[4];
tmp_207_reg_6348[5] <= tmp_207_fu_4597_p1[5];
tmp_207_reg_6348[6] <= tmp_207_fu_4597_p1[6];
tmp_207_reg_6348[7] <= tmp_207_fu_4597_p1[7];
tmp_207_reg_6348[8] <= tmp_207_fu_4597_p1[8];
tmp_207_reg_6348[9] <= tmp_207_fu_4597_p1[9];
tmp_207_reg_6348[10] <= tmp_207_fu_4597_p1[10];
tmp_207_reg_6348[11] <= tmp_207_fu_4597_p1[11];
tmp_207_reg_6348[12] <= tmp_207_fu_4597_p1[12];
tmp_207_reg_6348[13] <= tmp_207_fu_4597_p1[13];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg5_fsm_45 == ap_CS_fsm))) begin
tmp_208_reg_6363[0] <= tmp_208_fu_4611_p1[0];
tmp_208_reg_6363[1] <= tmp_208_fu_4611_p1[1];
tmp_208_reg_6363[2] <= tmp_208_fu_4611_p1[2];
tmp_208_reg_6363[3] <= tmp_208_fu_4611_p1[3];
tmp_208_reg_6363[4] <= tmp_208_fu_4611_p1[4];
tmp_208_reg_6363[5] <= tmp_208_fu_4611_p1[5];
tmp_208_reg_6363[6] <= tmp_208_fu_4611_p1[6];
tmp_208_reg_6363[7] <= tmp_208_fu_4611_p1[7];
tmp_208_reg_6363[8] <= tmp_208_fu_4611_p1[8];
tmp_208_reg_6363[9] <= tmp_208_fu_4611_p1[9];
tmp_208_reg_6363[10] <= tmp_208_fu_4611_p1[10];
tmp_208_reg_6363[11] <= tmp_208_fu_4611_p1[11];
tmp_208_reg_6363[12] <= tmp_208_fu_4611_p1[12];
tmp_208_reg_6363[13] <= tmp_208_fu_4611_p1[13];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg5_fsm_45 == ap_CS_fsm))) begin
tmp_209_reg_6373[2] <= tmp_209_fu_4620_p1[2];
tmp_209_reg_6373[3] <= tmp_209_fu_4620_p1[3];
tmp_209_reg_6373[4] <= tmp_209_fu_4620_p1[4];
tmp_209_reg_6373[5] <= tmp_209_fu_4620_p1[5];
tmp_209_reg_6373[6] <= tmp_209_fu_4620_p1[6];
tmp_209_reg_6373[7] <= tmp_209_fu_4620_p1[7];
tmp_209_reg_6373[8] <= tmp_209_fu_4620_p1[8];
tmp_209_reg_6373[9] <= tmp_209_fu_4620_p1[9];
tmp_209_reg_6373[10] <= tmp_209_fu_4620_p1[10];
tmp_209_reg_6373[11] <= tmp_209_fu_4620_p1[11];
tmp_209_reg_6373[12] <= tmp_209_fu_4620_p1[12];
tmp_209_reg_6373[13] <= tmp_209_fu_4620_p1[13];
end
if (((ap_ST_pp1_stg1_fsm_5 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond3_reg_5195))) begin
tmp_20_reg_5287[0] <= tmp_20_fu_2626_p1[0];
tmp_20_reg_5287[1] <= tmp_20_fu_2626_p1[1];
tmp_20_reg_5287[2] <= tmp_20_fu_2626_p1[2];
tmp_20_reg_5287[3] <= tmp_20_fu_2626_p1[3];
tmp_20_reg_5287[4] <= tmp_20_fu_2626_p1[4];
tmp_20_reg_5287[5] <= tmp_20_fu_2626_p1[5];
tmp_20_reg_5287[6] <= tmp_20_fu_2626_p1[6];
tmp_20_reg_5287[7] <= tmp_20_fu_2626_p1[7];
tmp_20_reg_5287[8] <= tmp_20_fu_2626_p1[8];
tmp_20_reg_5287[9] <= tmp_20_fu_2626_p1[9];
tmp_20_reg_5287[10] <= tmp_20_fu_2626_p1[10];
tmp_20_reg_5287[11] <= tmp_20_fu_2626_p1[11];
tmp_20_reg_5287[12] <= tmp_20_fu_2626_p1[12];
tmp_20_reg_5287[13] <= tmp_20_fu_2626_p1[13];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg6_fsm_46 == ap_CS_fsm))) begin
tmp_210_reg_6383[0] <= tmp_210_fu_4629_p1[0];
tmp_210_reg_6383[1] <= tmp_210_fu_4629_p1[1];
tmp_210_reg_6383[2] <= tmp_210_fu_4629_p1[2];
tmp_210_reg_6383[3] <= tmp_210_fu_4629_p1[3];
tmp_210_reg_6383[4] <= tmp_210_fu_4629_p1[4];
tmp_210_reg_6383[5] <= tmp_210_fu_4629_p1[5];
tmp_210_reg_6383[6] <= tmp_210_fu_4629_p1[6];
tmp_210_reg_6383[7] <= tmp_210_fu_4629_p1[7];
tmp_210_reg_6383[8] <= tmp_210_fu_4629_p1[8];
tmp_210_reg_6383[9] <= tmp_210_fu_4629_p1[9];
tmp_210_reg_6383[10] <= tmp_210_fu_4629_p1[10];
tmp_210_reg_6383[11] <= tmp_210_fu_4629_p1[11];
tmp_210_reg_6383[12] <= tmp_210_fu_4629_p1[12];
tmp_210_reg_6383[13] <= tmp_210_fu_4629_p1[13];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg6_fsm_46 == ap_CS_fsm))) begin
tmp_211_reg_6393[1] <= tmp_211_fu_4638_p1[1];
tmp_211_reg_6393[2] <= tmp_211_fu_4638_p1[2];
tmp_211_reg_6393[3] <= tmp_211_fu_4638_p1[3];
tmp_211_reg_6393[4] <= tmp_211_fu_4638_p1[4];
tmp_211_reg_6393[5] <= tmp_211_fu_4638_p1[5];
tmp_211_reg_6393[6] <= tmp_211_fu_4638_p1[6];
tmp_211_reg_6393[7] <= tmp_211_fu_4638_p1[7];
tmp_211_reg_6393[8] <= tmp_211_fu_4638_p1[8];
tmp_211_reg_6393[9] <= tmp_211_fu_4638_p1[9];
tmp_211_reg_6393[10] <= tmp_211_fu_4638_p1[10];
tmp_211_reg_6393[11] <= tmp_211_fu_4638_p1[11];
tmp_211_reg_6393[12] <= tmp_211_fu_4638_p1[12];
tmp_211_reg_6393[13] <= tmp_211_fu_4638_p1[13];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg7_fsm_47 == ap_CS_fsm))) begin
tmp_212_reg_6403[0] <= tmp_212_fu_4647_p1[0];
tmp_212_reg_6403[1] <= tmp_212_fu_4647_p1[1];
tmp_212_reg_6403[2] <= tmp_212_fu_4647_p1[2];
tmp_212_reg_6403[3] <= tmp_212_fu_4647_p1[3];
tmp_212_reg_6403[4] <= tmp_212_fu_4647_p1[4];
tmp_212_reg_6403[5] <= tmp_212_fu_4647_p1[5];
tmp_212_reg_6403[6] <= tmp_212_fu_4647_p1[6];
tmp_212_reg_6403[7] <= tmp_212_fu_4647_p1[7];
tmp_212_reg_6403[8] <= tmp_212_fu_4647_p1[8];
tmp_212_reg_6403[9] <= tmp_212_fu_4647_p1[9];
tmp_212_reg_6403[10] <= tmp_212_fu_4647_p1[10];
tmp_212_reg_6403[11] <= tmp_212_fu_4647_p1[11];
tmp_212_reg_6403[12] <= tmp_212_fu_4647_p1[12];
tmp_212_reg_6403[13] <= tmp_212_fu_4647_p1[13];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg7_fsm_47 == ap_CS_fsm))) begin
tmp_213_reg_6413[3] <= tmp_213_fu_4656_p1[3];
tmp_213_reg_6413[4] <= tmp_213_fu_4656_p1[4];
tmp_213_reg_6413[5] <= tmp_213_fu_4656_p1[5];
tmp_213_reg_6413[6] <= tmp_213_fu_4656_p1[6];
tmp_213_reg_6413[7] <= tmp_213_fu_4656_p1[7];
tmp_213_reg_6413[8] <= tmp_213_fu_4656_p1[8];
tmp_213_reg_6413[9] <= tmp_213_fu_4656_p1[9];
tmp_213_reg_6413[10] <= tmp_213_fu_4656_p1[10];
tmp_213_reg_6413[11] <= tmp_213_fu_4656_p1[11];
tmp_213_reg_6413[12] <= tmp_213_fu_4656_p1[12];
tmp_213_reg_6413[13] <= tmp_213_fu_4656_p1[13];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg8_fsm_48 == ap_CS_fsm))) begin
tmp_214_reg_6432[1] <= tmp_214_fu_4685_p1[1];
tmp_214_reg_6432[2] <= tmp_214_fu_4685_p1[2];
tmp_214_reg_6432[3] <= tmp_214_fu_4685_p1[3];
tmp_214_reg_6432[4] <= tmp_214_fu_4685_p1[4];
tmp_214_reg_6432[5] <= tmp_214_fu_4685_p1[5];
tmp_214_reg_6432[6] <= tmp_214_fu_4685_p1[6];
tmp_214_reg_6432[7] <= tmp_214_fu_4685_p1[7];
tmp_214_reg_6432[8] <= tmp_214_fu_4685_p1[8];
tmp_214_reg_6432[9] <= tmp_214_fu_4685_p1[9];
tmp_214_reg_6432[10] <= tmp_214_fu_4685_p1[10];
tmp_214_reg_6432[11] <= tmp_214_fu_4685_p1[11];
tmp_214_reg_6432[12] <= tmp_214_fu_4685_p1[12];
tmp_214_reg_6432[13] <= tmp_214_fu_4685_p1[13];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg8_fsm_48 == ap_CS_fsm))) begin
tmp_215_reg_6442[0] <= tmp_215_fu_4695_p1[0];
tmp_215_reg_6442[1] <= tmp_215_fu_4695_p1[1];
tmp_215_reg_6442[2] <= tmp_215_fu_4695_p1[2];
tmp_215_reg_6442[3] <= tmp_215_fu_4695_p1[3];
tmp_215_reg_6442[4] <= tmp_215_fu_4695_p1[4];
tmp_215_reg_6442[5] <= tmp_215_fu_4695_p1[5];
tmp_215_reg_6442[6] <= tmp_215_fu_4695_p1[6];
tmp_215_reg_6442[7] <= tmp_215_fu_4695_p1[7];
tmp_215_reg_6442[8] <= tmp_215_fu_4695_p1[8];
tmp_215_reg_6442[9] <= tmp_215_fu_4695_p1[9];
tmp_215_reg_6442[10] <= tmp_215_fu_4695_p1[10];
tmp_215_reg_6442[11] <= tmp_215_fu_4695_p1[11];
tmp_215_reg_6442[12] <= tmp_215_fu_4695_p1[12];
tmp_215_reg_6442[13] <= tmp_215_fu_4695_p1[13];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg9_fsm_49 == ap_CS_fsm))) begin
tmp_216_reg_6452[2] <= tmp_216_fu_4704_p1[2];
tmp_216_reg_6452[3] <= tmp_216_fu_4704_p1[3];
tmp_216_reg_6452[4] <= tmp_216_fu_4704_p1[4];
tmp_216_reg_6452[5] <= tmp_216_fu_4704_p1[5];
tmp_216_reg_6452[6] <= tmp_216_fu_4704_p1[6];
tmp_216_reg_6452[7] <= tmp_216_fu_4704_p1[7];
tmp_216_reg_6452[8] <= tmp_216_fu_4704_p1[8];
tmp_216_reg_6452[9] <= tmp_216_fu_4704_p1[9];
tmp_216_reg_6452[10] <= tmp_216_fu_4704_p1[10];
tmp_216_reg_6452[11] <= tmp_216_fu_4704_p1[11];
tmp_216_reg_6452[12] <= tmp_216_fu_4704_p1[12];
tmp_216_reg_6452[13] <= tmp_216_fu_4704_p1[13];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg9_fsm_49 == ap_CS_fsm))) begin
tmp_217_reg_6462[0] <= tmp_217_fu_4713_p1[0];
tmp_217_reg_6462[1] <= tmp_217_fu_4713_p1[1];
tmp_217_reg_6462[2] <= tmp_217_fu_4713_p1[2];
tmp_217_reg_6462[3] <= tmp_217_fu_4713_p1[3];
tmp_217_reg_6462[4] <= tmp_217_fu_4713_p1[4];
tmp_217_reg_6462[5] <= tmp_217_fu_4713_p1[5];
tmp_217_reg_6462[6] <= tmp_217_fu_4713_p1[6];
tmp_217_reg_6462[7] <= tmp_217_fu_4713_p1[7];
tmp_217_reg_6462[8] <= tmp_217_fu_4713_p1[8];
tmp_217_reg_6462[9] <= tmp_217_fu_4713_p1[9];
tmp_217_reg_6462[10] <= tmp_217_fu_4713_p1[10];
tmp_217_reg_6462[11] <= tmp_217_fu_4713_p1[11];
tmp_217_reg_6462[12] <= tmp_217_fu_4713_p1[12];
tmp_217_reg_6462[13] <= tmp_217_fu_4713_p1[13];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg10_fsm_50 == ap_CS_fsm))) begin
tmp_218_reg_6472[1] <= tmp_218_fu_4722_p1[1];
tmp_218_reg_6472[2] <= tmp_218_fu_4722_p1[2];
tmp_218_reg_6472[3] <= tmp_218_fu_4722_p1[3];
tmp_218_reg_6472[4] <= tmp_218_fu_4722_p1[4];
tmp_218_reg_6472[5] <= tmp_218_fu_4722_p1[5];
tmp_218_reg_6472[6] <= tmp_218_fu_4722_p1[6];
tmp_218_reg_6472[7] <= tmp_218_fu_4722_p1[7];
tmp_218_reg_6472[8] <= tmp_218_fu_4722_p1[8];
tmp_218_reg_6472[9] <= tmp_218_fu_4722_p1[9];
tmp_218_reg_6472[10] <= tmp_218_fu_4722_p1[10];
tmp_218_reg_6472[11] <= tmp_218_fu_4722_p1[11];
tmp_218_reg_6472[12] <= tmp_218_fu_4722_p1[12];
tmp_218_reg_6472[13] <= tmp_218_fu_4722_p1[13];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg10_fsm_50 == ap_CS_fsm))) begin
tmp_219_reg_6482[0] <= tmp_219_fu_4731_p1[0];
tmp_219_reg_6482[1] <= tmp_219_fu_4731_p1[1];
tmp_219_reg_6482[2] <= tmp_219_fu_4731_p1[2];
tmp_219_reg_6482[3] <= tmp_219_fu_4731_p1[3];
tmp_219_reg_6482[4] <= tmp_219_fu_4731_p1[4];
tmp_219_reg_6482[5] <= tmp_219_fu_4731_p1[5];
tmp_219_reg_6482[6] <= tmp_219_fu_4731_p1[6];
tmp_219_reg_6482[7] <= tmp_219_fu_4731_p1[7];
tmp_219_reg_6482[8] <= tmp_219_fu_4731_p1[8];
tmp_219_reg_6482[9] <= tmp_219_fu_4731_p1[9];
tmp_219_reg_6482[10] <= tmp_219_fu_4731_p1[10];
tmp_219_reg_6482[11] <= tmp_219_fu_4731_p1[11];
tmp_219_reg_6482[12] <= tmp_219_fu_4731_p1[12];
tmp_219_reg_6482[13] <= tmp_219_fu_4731_p1[13];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg11_fsm_51 == ap_CS_fsm))) begin
tmp_220_reg_6492[3] <= tmp_220_fu_4745_p1[3];
tmp_220_reg_6492[4] <= tmp_220_fu_4745_p1[4];
tmp_220_reg_6492[5] <= tmp_220_fu_4745_p1[5];
tmp_220_reg_6492[6] <= tmp_220_fu_4745_p1[6];
tmp_220_reg_6492[7] <= tmp_220_fu_4745_p1[7];
tmp_220_reg_6492[8] <= tmp_220_fu_4745_p1[8];
tmp_220_reg_6492[9] <= tmp_220_fu_4745_p1[9];
tmp_220_reg_6492[10] <= tmp_220_fu_4745_p1[10];
tmp_220_reg_6492[11] <= tmp_220_fu_4745_p1[11];
tmp_220_reg_6492[12] <= tmp_220_fu_4745_p1[12];
tmp_220_reg_6492[13] <= tmp_220_fu_4745_p1[13];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg11_fsm_51 == ap_CS_fsm))) begin
tmp_221_reg_6512[1] <= tmp_221_fu_4769_p1[1];
tmp_221_reg_6512[2] <= tmp_221_fu_4769_p1[2];
tmp_221_reg_6512[3] <= tmp_221_fu_4769_p1[3];
tmp_221_reg_6512[4] <= tmp_221_fu_4769_p1[4];
tmp_221_reg_6512[5] <= tmp_221_fu_4769_p1[5];
tmp_221_reg_6512[6] <= tmp_221_fu_4769_p1[6];
tmp_221_reg_6512[7] <= tmp_221_fu_4769_p1[7];
tmp_221_reg_6512[8] <= tmp_221_fu_4769_p1[8];
tmp_221_reg_6512[9] <= tmp_221_fu_4769_p1[9];
tmp_221_reg_6512[10] <= tmp_221_fu_4769_p1[10];
tmp_221_reg_6512[11] <= tmp_221_fu_4769_p1[11];
tmp_221_reg_6512[12] <= tmp_221_fu_4769_p1[12];
tmp_221_reg_6512[13] <= tmp_221_fu_4769_p1[13];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg12_fsm_52 == ap_CS_fsm))) begin
tmp_222_reg_6522[0] <= tmp_222_fu_4778_p1[0];
tmp_222_reg_6522[1] <= tmp_222_fu_4778_p1[1];
tmp_222_reg_6522[2] <= tmp_222_fu_4778_p1[2];
tmp_222_reg_6522[3] <= tmp_222_fu_4778_p1[3];
tmp_222_reg_6522[4] <= tmp_222_fu_4778_p1[4];
tmp_222_reg_6522[5] <= tmp_222_fu_4778_p1[5];
tmp_222_reg_6522[6] <= tmp_222_fu_4778_p1[6];
tmp_222_reg_6522[7] <= tmp_222_fu_4778_p1[7];
tmp_222_reg_6522[8] <= tmp_222_fu_4778_p1[8];
tmp_222_reg_6522[9] <= tmp_222_fu_4778_p1[9];
tmp_222_reg_6522[10] <= tmp_222_fu_4778_p1[10];
tmp_222_reg_6522[11] <= tmp_222_fu_4778_p1[11];
tmp_222_reg_6522[12] <= tmp_222_fu_4778_p1[12];
tmp_222_reg_6522[13] <= tmp_222_fu_4778_p1[13];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg12_fsm_52 == ap_CS_fsm))) begin
tmp_223_reg_6532[2] <= tmp_223_fu_4787_p1[2];
tmp_223_reg_6532[3] <= tmp_223_fu_4787_p1[3];
tmp_223_reg_6532[4] <= tmp_223_fu_4787_p1[4];
tmp_223_reg_6532[5] <= tmp_223_fu_4787_p1[5];
tmp_223_reg_6532[6] <= tmp_223_fu_4787_p1[6];
tmp_223_reg_6532[7] <= tmp_223_fu_4787_p1[7];
tmp_223_reg_6532[8] <= tmp_223_fu_4787_p1[8];
tmp_223_reg_6532[9] <= tmp_223_fu_4787_p1[9];
tmp_223_reg_6532[10] <= tmp_223_fu_4787_p1[10];
tmp_223_reg_6532[11] <= tmp_223_fu_4787_p1[11];
tmp_223_reg_6532[12] <= tmp_223_fu_4787_p1[12];
tmp_223_reg_6532[13] <= tmp_223_fu_4787_p1[13];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg13_fsm_53 == ap_CS_fsm))) begin
tmp_224_reg_6542[0] <= tmp_224_fu_4796_p1[0];
tmp_224_reg_6542[1] <= tmp_224_fu_4796_p1[1];
tmp_224_reg_6542[2] <= tmp_224_fu_4796_p1[2];
tmp_224_reg_6542[3] <= tmp_224_fu_4796_p1[3];
tmp_224_reg_6542[4] <= tmp_224_fu_4796_p1[4];
tmp_224_reg_6542[5] <= tmp_224_fu_4796_p1[5];
tmp_224_reg_6542[6] <= tmp_224_fu_4796_p1[6];
tmp_224_reg_6542[7] <= tmp_224_fu_4796_p1[7];
tmp_224_reg_6542[8] <= tmp_224_fu_4796_p1[8];
tmp_224_reg_6542[9] <= tmp_224_fu_4796_p1[9];
tmp_224_reg_6542[10] <= tmp_224_fu_4796_p1[10];
tmp_224_reg_6542[11] <= tmp_224_fu_4796_p1[11];
tmp_224_reg_6542[12] <= tmp_224_fu_4796_p1[12];
tmp_224_reg_6542[13] <= tmp_224_fu_4796_p1[13];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg13_fsm_53 == ap_CS_fsm))) begin
tmp_225_reg_6552[1] <= tmp_225_fu_4805_p1[1];
tmp_225_reg_6552[2] <= tmp_225_fu_4805_p1[2];
tmp_225_reg_6552[3] <= tmp_225_fu_4805_p1[3];
tmp_225_reg_6552[4] <= tmp_225_fu_4805_p1[4];
tmp_225_reg_6552[5] <= tmp_225_fu_4805_p1[5];
tmp_225_reg_6552[6] <= tmp_225_fu_4805_p1[6];
tmp_225_reg_6552[7] <= tmp_225_fu_4805_p1[7];
tmp_225_reg_6552[8] <= tmp_225_fu_4805_p1[8];
tmp_225_reg_6552[9] <= tmp_225_fu_4805_p1[9];
tmp_225_reg_6552[10] <= tmp_225_fu_4805_p1[10];
tmp_225_reg_6552[11] <= tmp_225_fu_4805_p1[11];
tmp_225_reg_6552[12] <= tmp_225_fu_4805_p1[12];
tmp_225_reg_6552[13] <= tmp_225_fu_4805_p1[13];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg14_fsm_54 == ap_CS_fsm))) begin
tmp_226_reg_6562[0] <= tmp_226_fu_4814_p1[0];
tmp_226_reg_6562[1] <= tmp_226_fu_4814_p1[1];
tmp_226_reg_6562[2] <= tmp_226_fu_4814_p1[2];
tmp_226_reg_6562[3] <= tmp_226_fu_4814_p1[3];
tmp_226_reg_6562[4] <= tmp_226_fu_4814_p1[4];
tmp_226_reg_6562[5] <= tmp_226_fu_4814_p1[5];
tmp_226_reg_6562[6] <= tmp_226_fu_4814_p1[6];
tmp_226_reg_6562[7] <= tmp_226_fu_4814_p1[7];
tmp_226_reg_6562[8] <= tmp_226_fu_4814_p1[8];
tmp_226_reg_6562[9] <= tmp_226_fu_4814_p1[9];
tmp_226_reg_6562[10] <= tmp_226_fu_4814_p1[10];
tmp_226_reg_6562[11] <= tmp_226_fu_4814_p1[11];
tmp_226_reg_6562[12] <= tmp_226_fu_4814_p1[12];
tmp_226_reg_6562[13] <= tmp_226_fu_4814_p1[13];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg14_fsm_54 == ap_CS_fsm))) begin
tmp_227_reg_6572[3] <= tmp_227_fu_4823_p1[3];
tmp_227_reg_6572[4] <= tmp_227_fu_4823_p1[4];
tmp_227_reg_6572[5] <= tmp_227_fu_4823_p1[5];
tmp_227_reg_6572[6] <= tmp_227_fu_4823_p1[6];
tmp_227_reg_6572[7] <= tmp_227_fu_4823_p1[7];
tmp_227_reg_6572[8] <= tmp_227_fu_4823_p1[8];
tmp_227_reg_6572[9] <= tmp_227_fu_4823_p1[9];
tmp_227_reg_6572[10] <= tmp_227_fu_4823_p1[10];
tmp_227_reg_6572[11] <= tmp_227_fu_4823_p1[11];
tmp_227_reg_6572[12] <= tmp_227_fu_4823_p1[12];
tmp_227_reg_6572[13] <= tmp_227_fu_4823_p1[13];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg15_fsm_55 == ap_CS_fsm))) begin
tmp_228_reg_6591[1] <= tmp_228_fu_4852_p1[1];
tmp_228_reg_6591[2] <= tmp_228_fu_4852_p1[2];
tmp_228_reg_6591[3] <= tmp_228_fu_4852_p1[3];
tmp_228_reg_6591[4] <= tmp_228_fu_4852_p1[4];
tmp_228_reg_6591[5] <= tmp_228_fu_4852_p1[5];
tmp_228_reg_6591[6] <= tmp_228_fu_4852_p1[6];
tmp_228_reg_6591[7] <= tmp_228_fu_4852_p1[7];
tmp_228_reg_6591[8] <= tmp_228_fu_4852_p1[8];
tmp_228_reg_6591[9] <= tmp_228_fu_4852_p1[9];
tmp_228_reg_6591[10] <= tmp_228_fu_4852_p1[10];
tmp_228_reg_6591[11] <= tmp_228_fu_4852_p1[11];
tmp_228_reg_6591[12] <= tmp_228_fu_4852_p1[12];
tmp_228_reg_6591[13] <= tmp_228_fu_4852_p1[13];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg15_fsm_55 == ap_CS_fsm))) begin
tmp_229_reg_6601[0] <= tmp_229_fu_4862_p1[0];
tmp_229_reg_6601[1] <= tmp_229_fu_4862_p1[1];
tmp_229_reg_6601[2] <= tmp_229_fu_4862_p1[2];
tmp_229_reg_6601[3] <= tmp_229_fu_4862_p1[3];
tmp_229_reg_6601[4] <= tmp_229_fu_4862_p1[4];
tmp_229_reg_6601[5] <= tmp_229_fu_4862_p1[5];
tmp_229_reg_6601[6] <= tmp_229_fu_4862_p1[6];
tmp_229_reg_6601[7] <= tmp_229_fu_4862_p1[7];
tmp_229_reg_6601[8] <= tmp_229_fu_4862_p1[8];
tmp_229_reg_6601[9] <= tmp_229_fu_4862_p1[9];
tmp_229_reg_6601[10] <= tmp_229_fu_4862_p1[10];
tmp_229_reg_6601[11] <= tmp_229_fu_4862_p1[11];
tmp_229_reg_6601[12] <= tmp_229_fu_4862_p1[12];
tmp_229_reg_6601[13] <= tmp_229_fu_4862_p1[13];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg16_fsm_56 == ap_CS_fsm))) begin
tmp_230_reg_6611[2] <= tmp_230_fu_4871_p1[2];
tmp_230_reg_6611[3] <= tmp_230_fu_4871_p1[3];
tmp_230_reg_6611[4] <= tmp_230_fu_4871_p1[4];
tmp_230_reg_6611[5] <= tmp_230_fu_4871_p1[5];
tmp_230_reg_6611[6] <= tmp_230_fu_4871_p1[6];
tmp_230_reg_6611[7] <= tmp_230_fu_4871_p1[7];
tmp_230_reg_6611[8] <= tmp_230_fu_4871_p1[8];
tmp_230_reg_6611[9] <= tmp_230_fu_4871_p1[9];
tmp_230_reg_6611[10] <= tmp_230_fu_4871_p1[10];
tmp_230_reg_6611[11] <= tmp_230_fu_4871_p1[11];
tmp_230_reg_6611[12] <= tmp_230_fu_4871_p1[12];
tmp_230_reg_6611[13] <= tmp_230_fu_4871_p1[13];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg16_fsm_56 == ap_CS_fsm))) begin
tmp_231_reg_6621[0] <= tmp_231_fu_4880_p1[0];
tmp_231_reg_6621[1] <= tmp_231_fu_4880_p1[1];
tmp_231_reg_6621[2] <= tmp_231_fu_4880_p1[2];
tmp_231_reg_6621[3] <= tmp_231_fu_4880_p1[3];
tmp_231_reg_6621[4] <= tmp_231_fu_4880_p1[4];
tmp_231_reg_6621[5] <= tmp_231_fu_4880_p1[5];
tmp_231_reg_6621[6] <= tmp_231_fu_4880_p1[6];
tmp_231_reg_6621[7] <= tmp_231_fu_4880_p1[7];
tmp_231_reg_6621[8] <= tmp_231_fu_4880_p1[8];
tmp_231_reg_6621[9] <= tmp_231_fu_4880_p1[9];
tmp_231_reg_6621[10] <= tmp_231_fu_4880_p1[10];
tmp_231_reg_6621[11] <= tmp_231_fu_4880_p1[11];
tmp_231_reg_6621[12] <= tmp_231_fu_4880_p1[12];
tmp_231_reg_6621[13] <= tmp_231_fu_4880_p1[13];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg17_fsm_57 == ap_CS_fsm))) begin
tmp_232_reg_6631[1] <= tmp_232_fu_4889_p1[1];
tmp_232_reg_6631[2] <= tmp_232_fu_4889_p1[2];
tmp_232_reg_6631[3] <= tmp_232_fu_4889_p1[3];
tmp_232_reg_6631[4] <= tmp_232_fu_4889_p1[4];
tmp_232_reg_6631[5] <= tmp_232_fu_4889_p1[5];
tmp_232_reg_6631[6] <= tmp_232_fu_4889_p1[6];
tmp_232_reg_6631[7] <= tmp_232_fu_4889_p1[7];
tmp_232_reg_6631[8] <= tmp_232_fu_4889_p1[8];
tmp_232_reg_6631[9] <= tmp_232_fu_4889_p1[9];
tmp_232_reg_6631[10] <= tmp_232_fu_4889_p1[10];
tmp_232_reg_6631[11] <= tmp_232_fu_4889_p1[11];
tmp_232_reg_6631[12] <= tmp_232_fu_4889_p1[12];
tmp_232_reg_6631[13] <= tmp_232_fu_4889_p1[13];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg17_fsm_57 == ap_CS_fsm))) begin
tmp_233_reg_6641[0] <= tmp_233_fu_4898_p1[0];
tmp_233_reg_6641[1] <= tmp_233_fu_4898_p1[1];
tmp_233_reg_6641[2] <= tmp_233_fu_4898_p1[2];
tmp_233_reg_6641[3] <= tmp_233_fu_4898_p1[3];
tmp_233_reg_6641[4] <= tmp_233_fu_4898_p1[4];
tmp_233_reg_6641[5] <= tmp_233_fu_4898_p1[5];
tmp_233_reg_6641[6] <= tmp_233_fu_4898_p1[6];
tmp_233_reg_6641[7] <= tmp_233_fu_4898_p1[7];
tmp_233_reg_6641[8] <= tmp_233_fu_4898_p1[8];
tmp_233_reg_6641[9] <= tmp_233_fu_4898_p1[9];
tmp_233_reg_6641[10] <= tmp_233_fu_4898_p1[10];
tmp_233_reg_6641[11] <= tmp_233_fu_4898_p1[11];
tmp_233_reg_6641[12] <= tmp_233_fu_4898_p1[12];
tmp_233_reg_6641[13] <= tmp_233_fu_4898_p1[13];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg18_fsm_58 == ap_CS_fsm))) begin
tmp_234_reg_6651[3] <= tmp_234_fu_4912_p1[3];
tmp_234_reg_6651[4] <= tmp_234_fu_4912_p1[4];
tmp_234_reg_6651[5] <= tmp_234_fu_4912_p1[5];
tmp_234_reg_6651[6] <= tmp_234_fu_4912_p1[6];
tmp_234_reg_6651[7] <= tmp_234_fu_4912_p1[7];
tmp_234_reg_6651[8] <= tmp_234_fu_4912_p1[8];
tmp_234_reg_6651[9] <= tmp_234_fu_4912_p1[9];
tmp_234_reg_6651[10] <= tmp_234_fu_4912_p1[10];
tmp_234_reg_6651[11] <= tmp_234_fu_4912_p1[11];
tmp_234_reg_6651[12] <= tmp_234_fu_4912_p1[12];
tmp_234_reg_6651[13] <= tmp_234_fu_4912_p1[13];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg18_fsm_58 == ap_CS_fsm))) begin
tmp_235_reg_6671[1] <= tmp_235_fu_4936_p1[1];
tmp_235_reg_6671[2] <= tmp_235_fu_4936_p1[2];
tmp_235_reg_6671[3] <= tmp_235_fu_4936_p1[3];
tmp_235_reg_6671[4] <= tmp_235_fu_4936_p1[4];
tmp_235_reg_6671[5] <= tmp_235_fu_4936_p1[5];
tmp_235_reg_6671[6] <= tmp_235_fu_4936_p1[6];
tmp_235_reg_6671[7] <= tmp_235_fu_4936_p1[7];
tmp_235_reg_6671[8] <= tmp_235_fu_4936_p1[8];
tmp_235_reg_6671[9] <= tmp_235_fu_4936_p1[9];
tmp_235_reg_6671[10] <= tmp_235_fu_4936_p1[10];
tmp_235_reg_6671[11] <= tmp_235_fu_4936_p1[11];
tmp_235_reg_6671[12] <= tmp_235_fu_4936_p1[12];
tmp_235_reg_6671[13] <= tmp_235_fu_4936_p1[13];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg19_fsm_59 == ap_CS_fsm))) begin
tmp_236_reg_6681[0] <= tmp_236_fu_4945_p1[0];
tmp_236_reg_6681[1] <= tmp_236_fu_4945_p1[1];
tmp_236_reg_6681[2] <= tmp_236_fu_4945_p1[2];
tmp_236_reg_6681[3] <= tmp_236_fu_4945_p1[3];
tmp_236_reg_6681[4] <= tmp_236_fu_4945_p1[4];
tmp_236_reg_6681[5] <= tmp_236_fu_4945_p1[5];
tmp_236_reg_6681[6] <= tmp_236_fu_4945_p1[6];
tmp_236_reg_6681[7] <= tmp_236_fu_4945_p1[7];
tmp_236_reg_6681[8] <= tmp_236_fu_4945_p1[8];
tmp_236_reg_6681[9] <= tmp_236_fu_4945_p1[9];
tmp_236_reg_6681[10] <= tmp_236_fu_4945_p1[10];
tmp_236_reg_6681[11] <= tmp_236_fu_4945_p1[11];
tmp_236_reg_6681[12] <= tmp_236_fu_4945_p1[12];
tmp_236_reg_6681[13] <= tmp_236_fu_4945_p1[13];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg19_fsm_59 == ap_CS_fsm))) begin
tmp_237_reg_6691[2] <= tmp_237_fu_4954_p1[2];
tmp_237_reg_6691[3] <= tmp_237_fu_4954_p1[3];
tmp_237_reg_6691[4] <= tmp_237_fu_4954_p1[4];
tmp_237_reg_6691[5] <= tmp_237_fu_4954_p1[5];
tmp_237_reg_6691[6] <= tmp_237_fu_4954_p1[6];
tmp_237_reg_6691[7] <= tmp_237_fu_4954_p1[7];
tmp_237_reg_6691[8] <= tmp_237_fu_4954_p1[8];
tmp_237_reg_6691[9] <= tmp_237_fu_4954_p1[9];
tmp_237_reg_6691[10] <= tmp_237_fu_4954_p1[10];
tmp_237_reg_6691[11] <= tmp_237_fu_4954_p1[11];
tmp_237_reg_6691[12] <= tmp_237_fu_4954_p1[12];
tmp_237_reg_6691[13] <= tmp_237_fu_4954_p1[13];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg20_fsm_60 == ap_CS_fsm))) begin
tmp_238_reg_6701[0] <= tmp_238_fu_4963_p1[0];
tmp_238_reg_6701[1] <= tmp_238_fu_4963_p1[1];
tmp_238_reg_6701[2] <= tmp_238_fu_4963_p1[2];
tmp_238_reg_6701[3] <= tmp_238_fu_4963_p1[3];
tmp_238_reg_6701[4] <= tmp_238_fu_4963_p1[4];
tmp_238_reg_6701[5] <= tmp_238_fu_4963_p1[5];
tmp_238_reg_6701[6] <= tmp_238_fu_4963_p1[6];
tmp_238_reg_6701[7] <= tmp_238_fu_4963_p1[7];
tmp_238_reg_6701[8] <= tmp_238_fu_4963_p1[8];
tmp_238_reg_6701[9] <= tmp_238_fu_4963_p1[9];
tmp_238_reg_6701[10] <= tmp_238_fu_4963_p1[10];
tmp_238_reg_6701[11] <= tmp_238_fu_4963_p1[11];
tmp_238_reg_6701[12] <= tmp_238_fu_4963_p1[12];
tmp_238_reg_6701[13] <= tmp_238_fu_4963_p1[13];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg20_fsm_60 == ap_CS_fsm))) begin
tmp_239_reg_6711[1] <= tmp_239_fu_4972_p1[1];
tmp_239_reg_6711[2] <= tmp_239_fu_4972_p1[2];
tmp_239_reg_6711[3] <= tmp_239_fu_4972_p1[3];
tmp_239_reg_6711[4] <= tmp_239_fu_4972_p1[4];
tmp_239_reg_6711[5] <= tmp_239_fu_4972_p1[5];
tmp_239_reg_6711[6] <= tmp_239_fu_4972_p1[6];
tmp_239_reg_6711[7] <= tmp_239_fu_4972_p1[7];
tmp_239_reg_6711[8] <= tmp_239_fu_4972_p1[8];
tmp_239_reg_6711[9] <= tmp_239_fu_4972_p1[9];
tmp_239_reg_6711[10] <= tmp_239_fu_4972_p1[10];
tmp_239_reg_6711[11] <= tmp_239_fu_4972_p1[11];
tmp_239_reg_6711[12] <= tmp_239_fu_4972_p1[12];
tmp_239_reg_6711[13] <= tmp_239_fu_4972_p1[13];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg21_fsm_61 == ap_CS_fsm))) begin
tmp_240_reg_6721[0] <= tmp_240_fu_4981_p1[0];
tmp_240_reg_6721[1] <= tmp_240_fu_4981_p1[1];
tmp_240_reg_6721[2] <= tmp_240_fu_4981_p1[2];
tmp_240_reg_6721[3] <= tmp_240_fu_4981_p1[3];
tmp_240_reg_6721[4] <= tmp_240_fu_4981_p1[4];
tmp_240_reg_6721[5] <= tmp_240_fu_4981_p1[5];
tmp_240_reg_6721[6] <= tmp_240_fu_4981_p1[6];
tmp_240_reg_6721[7] <= tmp_240_fu_4981_p1[7];
tmp_240_reg_6721[8] <= tmp_240_fu_4981_p1[8];
tmp_240_reg_6721[9] <= tmp_240_fu_4981_p1[9];
tmp_240_reg_6721[10] <= tmp_240_fu_4981_p1[10];
tmp_240_reg_6721[11] <= tmp_240_fu_4981_p1[11];
tmp_240_reg_6721[12] <= tmp_240_fu_4981_p1[12];
tmp_240_reg_6721[13] <= tmp_240_fu_4981_p1[13];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg21_fsm_61 == ap_CS_fsm))) begin
tmp_241_reg_6731[3] <= tmp_241_fu_4990_p1[3];
tmp_241_reg_6731[4] <= tmp_241_fu_4990_p1[4];
tmp_241_reg_6731[5] <= tmp_241_fu_4990_p1[5];
tmp_241_reg_6731[6] <= tmp_241_fu_4990_p1[6];
tmp_241_reg_6731[7] <= tmp_241_fu_4990_p1[7];
tmp_241_reg_6731[8] <= tmp_241_fu_4990_p1[8];
tmp_241_reg_6731[9] <= tmp_241_fu_4990_p1[9];
tmp_241_reg_6731[10] <= tmp_241_fu_4990_p1[10];
tmp_241_reg_6731[11] <= tmp_241_fu_4990_p1[11];
tmp_241_reg_6731[12] <= tmp_241_fu_4990_p1[12];
tmp_241_reg_6731[13] <= tmp_241_fu_4990_p1[13];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg22_fsm_62 == ap_CS_fsm))) begin
tmp_242_reg_6750[1] <= tmp_242_fu_5019_p1[1];
tmp_242_reg_6750[2] <= tmp_242_fu_5019_p1[2];
tmp_242_reg_6750[3] <= tmp_242_fu_5019_p1[3];
tmp_242_reg_6750[4] <= tmp_242_fu_5019_p1[4];
tmp_242_reg_6750[5] <= tmp_242_fu_5019_p1[5];
tmp_242_reg_6750[6] <= tmp_242_fu_5019_p1[6];
tmp_242_reg_6750[7] <= tmp_242_fu_5019_p1[7];
tmp_242_reg_6750[8] <= tmp_242_fu_5019_p1[8];
tmp_242_reg_6750[9] <= tmp_242_fu_5019_p1[9];
tmp_242_reg_6750[10] <= tmp_242_fu_5019_p1[10];
tmp_242_reg_6750[11] <= tmp_242_fu_5019_p1[11];
tmp_242_reg_6750[12] <= tmp_242_fu_5019_p1[12];
tmp_242_reg_6750[13] <= tmp_242_fu_5019_p1[13];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg22_fsm_62 == ap_CS_fsm))) begin
tmp_243_reg_6760[0] <= tmp_243_fu_5029_p1[0];
tmp_243_reg_6760[1] <= tmp_243_fu_5029_p1[1];
tmp_243_reg_6760[2] <= tmp_243_fu_5029_p1[2];
tmp_243_reg_6760[3] <= tmp_243_fu_5029_p1[3];
tmp_243_reg_6760[4] <= tmp_243_fu_5029_p1[4];
tmp_243_reg_6760[5] <= tmp_243_fu_5029_p1[5];
tmp_243_reg_6760[6] <= tmp_243_fu_5029_p1[6];
tmp_243_reg_6760[7] <= tmp_243_fu_5029_p1[7];
tmp_243_reg_6760[8] <= tmp_243_fu_5029_p1[8];
tmp_243_reg_6760[9] <= tmp_243_fu_5029_p1[9];
tmp_243_reg_6760[10] <= tmp_243_fu_5029_p1[10];
tmp_243_reg_6760[11] <= tmp_243_fu_5029_p1[11];
tmp_243_reg_6760[12] <= tmp_243_fu_5029_p1[12];
tmp_243_reg_6760[13] <= tmp_243_fu_5029_p1[13];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg23_fsm_63 == ap_CS_fsm))) begin
tmp_244_reg_6770[2] <= tmp_244_fu_5038_p1[2];
tmp_244_reg_6770[3] <= tmp_244_fu_5038_p1[3];
tmp_244_reg_6770[4] <= tmp_244_fu_5038_p1[4];
tmp_244_reg_6770[5] <= tmp_244_fu_5038_p1[5];
tmp_244_reg_6770[6] <= tmp_244_fu_5038_p1[6];
tmp_244_reg_6770[7] <= tmp_244_fu_5038_p1[7];
tmp_244_reg_6770[8] <= tmp_244_fu_5038_p1[8];
tmp_244_reg_6770[9] <= tmp_244_fu_5038_p1[9];
tmp_244_reg_6770[10] <= tmp_244_fu_5038_p1[10];
tmp_244_reg_6770[11] <= tmp_244_fu_5038_p1[11];
tmp_244_reg_6770[12] <= tmp_244_fu_5038_p1[12];
tmp_244_reg_6770[13] <= tmp_244_fu_5038_p1[13];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg23_fsm_63 == ap_CS_fsm))) begin
tmp_245_reg_6780[0] <= tmp_245_fu_5047_p1[0];
tmp_245_reg_6780[1] <= tmp_245_fu_5047_p1[1];
tmp_245_reg_6780[2] <= tmp_245_fu_5047_p1[2];
tmp_245_reg_6780[3] <= tmp_245_fu_5047_p1[3];
tmp_245_reg_6780[4] <= tmp_245_fu_5047_p1[4];
tmp_245_reg_6780[5] <= tmp_245_fu_5047_p1[5];
tmp_245_reg_6780[6] <= tmp_245_fu_5047_p1[6];
tmp_245_reg_6780[7] <= tmp_245_fu_5047_p1[7];
tmp_245_reg_6780[8] <= tmp_245_fu_5047_p1[8];
tmp_245_reg_6780[9] <= tmp_245_fu_5047_p1[9];
tmp_245_reg_6780[10] <= tmp_245_fu_5047_p1[10];
tmp_245_reg_6780[11] <= tmp_245_fu_5047_p1[11];
tmp_245_reg_6780[12] <= tmp_245_fu_5047_p1[12];
tmp_245_reg_6780[13] <= tmp_245_fu_5047_p1[13];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg24_fsm_64 == ap_CS_fsm))) begin
tmp_246_reg_6790[1] <= tmp_246_fu_5061_p1[1];
tmp_246_reg_6790[2] <= tmp_246_fu_5061_p1[2];
tmp_246_reg_6790[3] <= tmp_246_fu_5061_p1[3];
tmp_246_reg_6790[4] <= tmp_246_fu_5061_p1[4];
tmp_246_reg_6790[5] <= tmp_246_fu_5061_p1[5];
tmp_246_reg_6790[6] <= tmp_246_fu_5061_p1[6];
tmp_246_reg_6790[7] <= tmp_246_fu_5061_p1[7];
tmp_246_reg_6790[8] <= tmp_246_fu_5061_p1[8];
tmp_246_reg_6790[9] <= tmp_246_fu_5061_p1[9];
tmp_246_reg_6790[10] <= tmp_246_fu_5061_p1[10];
tmp_246_reg_6790[11] <= tmp_246_fu_5061_p1[11];
tmp_246_reg_6790[12] <= tmp_246_fu_5061_p1[12];
tmp_246_reg_6790[13] <= tmp_246_fu_5061_p1[13];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg24_fsm_64 == ap_CS_fsm))) begin
tmp_247_reg_6800[0] <= tmp_247_fu_5070_p1[0];
tmp_247_reg_6800[1] <= tmp_247_fu_5070_p1[1];
tmp_247_reg_6800[2] <= tmp_247_fu_5070_p1[2];
tmp_247_reg_6800[3] <= tmp_247_fu_5070_p1[3];
tmp_247_reg_6800[4] <= tmp_247_fu_5070_p1[4];
tmp_247_reg_6800[5] <= tmp_247_fu_5070_p1[5];
tmp_247_reg_6800[6] <= tmp_247_fu_5070_p1[6];
tmp_247_reg_6800[7] <= tmp_247_fu_5070_p1[7];
tmp_247_reg_6800[8] <= tmp_247_fu_5070_p1[8];
tmp_247_reg_6800[9] <= tmp_247_fu_5070_p1[9];
tmp_247_reg_6800[10] <= tmp_247_fu_5070_p1[10];
tmp_247_reg_6800[11] <= tmp_247_fu_5070_p1[11];
tmp_247_reg_6800[12] <= tmp_247_fu_5070_p1[12];
tmp_247_reg_6800[13] <= tmp_247_fu_5070_p1[13];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg25_fsm_65 == ap_CS_fsm))) begin
tmp_248_reg_6850[3] <= tmp_248_fu_5128_p1[3];
tmp_248_reg_6850[4] <= tmp_248_fu_5128_p1[4];
tmp_248_reg_6850[5] <= tmp_248_fu_5128_p1[5];
tmp_248_reg_6850[6] <= tmp_248_fu_5128_p1[6];
tmp_248_reg_6850[7] <= tmp_248_fu_5128_p1[7];
tmp_248_reg_6850[8] <= tmp_248_fu_5128_p1[8];
tmp_248_reg_6850[9] <= tmp_248_fu_5128_p1[9];
tmp_248_reg_6850[10] <= tmp_248_fu_5128_p1[10];
tmp_248_reg_6850[11] <= tmp_248_fu_5128_p1[11];
tmp_248_reg_6850[12] <= tmp_248_fu_5128_p1[12];
tmp_248_reg_6850[13] <= tmp_248_fu_5128_p1[13];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg25_fsm_65 == ap_CS_fsm))) begin
tmp_249_reg_6860[1] <= tmp_249_fu_5132_p1[1];
tmp_249_reg_6860[2] <= tmp_249_fu_5132_p1[2];
tmp_249_reg_6860[3] <= tmp_249_fu_5132_p1[3];
tmp_249_reg_6860[4] <= tmp_249_fu_5132_p1[4];
tmp_249_reg_6860[5] <= tmp_249_fu_5132_p1[5];
tmp_249_reg_6860[6] <= tmp_249_fu_5132_p1[6];
tmp_249_reg_6860[7] <= tmp_249_fu_5132_p1[7];
tmp_249_reg_6860[8] <= tmp_249_fu_5132_p1[8];
tmp_249_reg_6860[9] <= tmp_249_fu_5132_p1[9];
tmp_249_reg_6860[10] <= tmp_249_fu_5132_p1[10];
tmp_249_reg_6860[11] <= tmp_249_fu_5132_p1[11];
tmp_249_reg_6860[12] <= tmp_249_fu_5132_p1[12];
tmp_249_reg_6860[13] <= tmp_249_fu_5132_p1[13];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg26_fsm_66 == ap_CS_fsm))) begin
tmp_250_reg_6870[0] <= tmp_250_fu_5136_p1[0];
tmp_250_reg_6870[1] <= tmp_250_fu_5136_p1[1];
tmp_250_reg_6870[2] <= tmp_250_fu_5136_p1[2];
tmp_250_reg_6870[3] <= tmp_250_fu_5136_p1[3];
tmp_250_reg_6870[4] <= tmp_250_fu_5136_p1[4];
tmp_250_reg_6870[5] <= tmp_250_fu_5136_p1[5];
tmp_250_reg_6870[6] <= tmp_250_fu_5136_p1[6];
tmp_250_reg_6870[7] <= tmp_250_fu_5136_p1[7];
tmp_250_reg_6870[8] <= tmp_250_fu_5136_p1[8];
tmp_250_reg_6870[9] <= tmp_250_fu_5136_p1[9];
tmp_250_reg_6870[10] <= tmp_250_fu_5136_p1[10];
tmp_250_reg_6870[11] <= tmp_250_fu_5136_p1[11];
tmp_250_reg_6870[12] <= tmp_250_fu_5136_p1[12];
tmp_250_reg_6870[13] <= tmp_250_fu_5136_p1[13];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg26_fsm_66 == ap_CS_fsm))) begin
tmp_251_reg_6880[2] <= tmp_251_fu_5140_p1[2];
tmp_251_reg_6880[3] <= tmp_251_fu_5140_p1[3];
tmp_251_reg_6880[4] <= tmp_251_fu_5140_p1[4];
tmp_251_reg_6880[5] <= tmp_251_fu_5140_p1[5];
tmp_251_reg_6880[6] <= tmp_251_fu_5140_p1[6];
tmp_251_reg_6880[7] <= tmp_251_fu_5140_p1[7];
tmp_251_reg_6880[8] <= tmp_251_fu_5140_p1[8];
tmp_251_reg_6880[9] <= tmp_251_fu_5140_p1[9];
tmp_251_reg_6880[10] <= tmp_251_fu_5140_p1[10];
tmp_251_reg_6880[11] <= tmp_251_fu_5140_p1[11];
tmp_251_reg_6880[12] <= tmp_251_fu_5140_p1[12];
tmp_251_reg_6880[13] <= tmp_251_fu_5140_p1[13];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg27_fsm_67 == ap_CS_fsm))) begin
tmp_252_reg_6890[0] <= tmp_252_fu_5144_p1[0];
tmp_252_reg_6890[1] <= tmp_252_fu_5144_p1[1];
tmp_252_reg_6890[2] <= tmp_252_fu_5144_p1[2];
tmp_252_reg_6890[3] <= tmp_252_fu_5144_p1[3];
tmp_252_reg_6890[4] <= tmp_252_fu_5144_p1[4];
tmp_252_reg_6890[5] <= tmp_252_fu_5144_p1[5];
tmp_252_reg_6890[6] <= tmp_252_fu_5144_p1[6];
tmp_252_reg_6890[7] <= tmp_252_fu_5144_p1[7];
tmp_252_reg_6890[8] <= tmp_252_fu_5144_p1[8];
tmp_252_reg_6890[9] <= tmp_252_fu_5144_p1[9];
tmp_252_reg_6890[10] <= tmp_252_fu_5144_p1[10];
tmp_252_reg_6890[11] <= tmp_252_fu_5144_p1[11];
tmp_252_reg_6890[12] <= tmp_252_fu_5144_p1[12];
tmp_252_reg_6890[13] <= tmp_252_fu_5144_p1[13];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg27_fsm_67 == ap_CS_fsm))) begin
tmp_253_reg_6900[1] <= tmp_253_fu_5148_p1[1];
tmp_253_reg_6900[2] <= tmp_253_fu_5148_p1[2];
tmp_253_reg_6900[3] <= tmp_253_fu_5148_p1[3];
tmp_253_reg_6900[4] <= tmp_253_fu_5148_p1[4];
tmp_253_reg_6900[5] <= tmp_253_fu_5148_p1[5];
tmp_253_reg_6900[6] <= tmp_253_fu_5148_p1[6];
tmp_253_reg_6900[7] <= tmp_253_fu_5148_p1[7];
tmp_253_reg_6900[8] <= tmp_253_fu_5148_p1[8];
tmp_253_reg_6900[9] <= tmp_253_fu_5148_p1[9];
tmp_253_reg_6900[10] <= tmp_253_fu_5148_p1[10];
tmp_253_reg_6900[11] <= tmp_253_fu_5148_p1[11];
tmp_253_reg_6900[12] <= tmp_253_fu_5148_p1[12];
tmp_253_reg_6900[13] <= tmp_253_fu_5148_p1[13];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg28_fsm_68 == ap_CS_fsm))) begin
tmp_254_reg_6910[0] <= tmp_254_fu_5152_p1[0];
tmp_254_reg_6910[1] <= tmp_254_fu_5152_p1[1];
tmp_254_reg_6910[2] <= tmp_254_fu_5152_p1[2];
tmp_254_reg_6910[3] <= tmp_254_fu_5152_p1[3];
tmp_254_reg_6910[4] <= tmp_254_fu_5152_p1[4];
tmp_254_reg_6910[5] <= tmp_254_fu_5152_p1[5];
tmp_254_reg_6910[6] <= tmp_254_fu_5152_p1[6];
tmp_254_reg_6910[7] <= tmp_254_fu_5152_p1[7];
tmp_254_reg_6910[8] <= tmp_254_fu_5152_p1[8];
tmp_254_reg_6910[9] <= tmp_254_fu_5152_p1[9];
tmp_254_reg_6910[10] <= tmp_254_fu_5152_p1[10];
tmp_254_reg_6910[11] <= tmp_254_fu_5152_p1[11];
tmp_254_reg_6910[12] <= tmp_254_fu_5152_p1[12];
tmp_254_reg_6910[13] <= tmp_254_fu_5152_p1[13];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg28_fsm_68 == ap_CS_fsm))) begin
tmp_255_reg_6920[3] <= tmp_255_fu_5156_p1[3];
tmp_255_reg_6920[4] <= tmp_255_fu_5156_p1[4];
tmp_255_reg_6920[5] <= tmp_255_fu_5156_p1[5];
tmp_255_reg_6920[6] <= tmp_255_fu_5156_p1[6];
tmp_255_reg_6920[7] <= tmp_255_fu_5156_p1[7];
tmp_255_reg_6920[8] <= tmp_255_fu_5156_p1[8];
tmp_255_reg_6920[9] <= tmp_255_fu_5156_p1[9];
tmp_255_reg_6920[10] <= tmp_255_fu_5156_p1[10];
tmp_255_reg_6920[11] <= tmp_255_fu_5156_p1[11];
tmp_255_reg_6920[12] <= tmp_255_fu_5156_p1[12];
tmp_255_reg_6920[13] <= tmp_255_fu_5156_p1[13];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond3_reg_5195) & (ap_ST_pp1_stg2_fsm_6 == ap_CS_fsm))) begin
tmp_28_reg_5332[0] <= tmp_28_fu_2740_p1[0];
tmp_28_reg_5332[1] <= tmp_28_fu_2740_p1[1];
tmp_28_reg_5332[2] <= tmp_28_fu_2740_p1[2];
tmp_28_reg_5332[3] <= tmp_28_fu_2740_p1[3];
tmp_28_reg_5332[4] <= tmp_28_fu_2740_p1[4];
tmp_28_reg_5332[5] <= tmp_28_fu_2740_p1[5];
tmp_28_reg_5332[6] <= tmp_28_fu_2740_p1[6];
tmp_28_reg_5332[7] <= tmp_28_fu_2740_p1[7];
tmp_28_reg_5332[8] <= tmp_28_fu_2740_p1[8];
tmp_28_reg_5332[9] <= tmp_28_fu_2740_p1[9];
tmp_28_reg_5332[10] <= tmp_28_fu_2740_p1[10];
tmp_28_reg_5332[11] <= tmp_28_fu_2740_p1[11];
tmp_28_reg_5332[12] <= tmp_28_fu_2740_p1[12];
tmp_28_reg_5332[13] <= tmp_28_fu_2740_p1[13];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond3_reg_5195) & (ap_ST_pp1_stg2_fsm_6 == ap_CS_fsm))) begin
tmp_36_reg_5347[0] <= tmp_36_fu_2794_p1[0];
tmp_36_reg_5347[1] <= tmp_36_fu_2794_p1[1];
tmp_36_reg_5347[2] <= tmp_36_fu_2794_p1[2];
tmp_36_reg_5347[3] <= tmp_36_fu_2794_p1[3];
tmp_36_reg_5347[4] <= tmp_36_fu_2794_p1[4];
tmp_36_reg_5347[5] <= tmp_36_fu_2794_p1[5];
tmp_36_reg_5347[6] <= tmp_36_fu_2794_p1[6];
tmp_36_reg_5347[7] <= tmp_36_fu_2794_p1[7];
tmp_36_reg_5347[8] <= tmp_36_fu_2794_p1[8];
tmp_36_reg_5347[9] <= tmp_36_fu_2794_p1[9];
tmp_36_reg_5347[10] <= tmp_36_fu_2794_p1[10];
tmp_36_reg_5347[11] <= tmp_36_fu_2794_p1[11];
tmp_36_reg_5347[12] <= tmp_36_fu_2794_p1[12];
tmp_36_reg_5347[13] <= tmp_36_fu_2794_p1[13];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond3_reg_5195) & (ap_ST_pp1_stg4_fsm_8 == ap_CS_fsm))) begin
tmp_43_reg_5402 <= (i_1_mid2_reg_5204 + ap_const_lv7_8);
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond3_reg_5195) & (ap_ST_pp1_stg3_fsm_7 == ap_CS_fsm))) begin
tmp_44_reg_5367[0] <= tmp_44_fu_2847_p1[0];
tmp_44_reg_5367[1] <= tmp_44_fu_2847_p1[1];
tmp_44_reg_5367[2] <= tmp_44_fu_2847_p1[2];
tmp_44_reg_5367[3] <= tmp_44_fu_2847_p1[3];
tmp_44_reg_5367[4] <= tmp_44_fu_2847_p1[4];
tmp_44_reg_5367[5] <= tmp_44_fu_2847_p1[5];
tmp_44_reg_5367[6] <= tmp_44_fu_2847_p1[6];
tmp_44_reg_5367[7] <= tmp_44_fu_2847_p1[7];
tmp_44_reg_5367[8] <= tmp_44_fu_2847_p1[8];
tmp_44_reg_5367[9] <= tmp_44_fu_2847_p1[9];
tmp_44_reg_5367[10] <= tmp_44_fu_2847_p1[10];
tmp_44_reg_5367[11] <= tmp_44_fu_2847_p1[11];
tmp_44_reg_5367[12] <= tmp_44_fu_2847_p1[12];
tmp_44_reg_5367[13] <= tmp_44_fu_2847_p1[13];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp3_it0) & (ap_ST_pp3_stg0_fsm_13 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond6_fu_3025_p2))) begin
tmp_44_trn_cast_reg_5477 <= {{7{j_1_mid2_fu_3057_p3[6]}}, {j_1_mid2_fu_3057_p3}};
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp3_it0) & (ap_const_lv1_0 == exitcond6_reg_5446) & (ap_ST_pp3_stg1_fsm_14 == ap_CS_fsm))) begin
tmp_46_trn_cast4_reg_5553 <= {{tmp_46_trn_cast_fu_3121_p1[ap_const_lv32_C : ap_const_lv32_6]}};
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp3_it0) & (ap_const_lv1_0 == exitcond6_reg_5446) & (ap_ST_pp3_stg1_fsm_14 == ap_CS_fsm))) begin
tmp_46_trn_cast5_reg_5558 <= {{tmp_46_trn_cast_fu_3121_p1[ap_const_lv32_C : ap_const_lv32_6]}};
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp3_it0) & (ap_const_lv1_0 == exitcond6_reg_5446) & (ap_ST_pp3_stg1_fsm_14 == ap_CS_fsm))) begin
tmp_46_trn_cast6_reg_5563 <= {{tmp_46_trn_cast_fu_3121_p1[ap_const_lv32_C : ap_const_lv32_6]}};
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp3_it0) & (ap_const_lv1_0 == exitcond6_reg_5446) & (ap_ST_pp3_stg1_fsm_14 == ap_CS_fsm))) begin
tmp_46_trn_cast7_reg_5568 <= {{tmp_46_trn_cast_fu_3121_p1[ap_const_lv32_C : ap_const_lv32_6]}};
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp3_it0) & (ap_const_lv1_0 == exitcond6_reg_5446) & (ap_ST_pp3_stg1_fsm_14 == ap_CS_fsm))) begin
tmp_46_trn_cast8_reg_5573 <= {{tmp_46_trn_cast_fu_3121_p1[ap_const_lv32_C : ap_const_lv32_6]}};
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp3_it0) & (ap_const_lv1_0 == exitcond6_reg_5446) & (ap_ST_pp3_stg1_fsm_14 == ap_CS_fsm))) begin
tmp_46_trn_cast_reg_5508[0] <= tmp_46_trn_cast_fu_3121_p1[0];
tmp_46_trn_cast_reg_5508[1] <= tmp_46_trn_cast_fu_3121_p1[1];
tmp_46_trn_cast_reg_5508[2] <= tmp_46_trn_cast_fu_3121_p1[2];
tmp_46_trn_cast_reg_5508[3] <= tmp_46_trn_cast_fu_3121_p1[3];
tmp_46_trn_cast_reg_5508[4] <= tmp_46_trn_cast_fu_3121_p1[4];
tmp_46_trn_cast_reg_5508[5] <= tmp_46_trn_cast_fu_3121_p1[5];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_ST_pp1_stg3_fsm_7 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond3_reg_5195_pp1_it1))) begin
tmp_47_reg_5407[0] <= tmp_47_fu_2980_p1[0];
tmp_47_reg_5407[1] <= tmp_47_fu_2980_p1[1];
tmp_47_reg_5407[2] <= tmp_47_fu_2980_p1[2];
tmp_47_reg_5407[3] <= tmp_47_fu_2980_p1[3];
tmp_47_reg_5407[4] <= tmp_47_fu_2980_p1[4];
tmp_47_reg_5407[5] <= tmp_47_fu_2980_p1[5];
tmp_47_reg_5407[6] <= tmp_47_fu_2980_p1[6];
tmp_47_reg_5407[7] <= tmp_47_fu_2980_p1[7];
tmp_47_reg_5407[8] <= tmp_47_fu_2980_p1[8];
tmp_47_reg_5407[9] <= tmp_47_fu_2980_p1[9];
tmp_47_reg_5407[10] <= tmp_47_fu_2980_p1[10];
tmp_47_reg_5407[11] <= tmp_47_fu_2980_p1[11];
tmp_47_reg_5407[12] <= tmp_47_fu_2980_p1[12];
tmp_47_reg_5407[13] <= tmp_47_fu_2980_p1[13];
end
if (((ap_ST_pp4_stg0_fsm_21 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp4_it0))) begin
tmp_49_reg_5682 <= (j_2_phi_fu_2000_p4 + ap_const_lv7_1);
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_ST_pp1_stg4_fsm_8 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond3_reg_5195_pp1_it1))) begin
tmp_51_reg_5417[0] <= tmp_51_fu_2984_p1[0];
tmp_51_reg_5417[1] <= tmp_51_fu_2984_p1[1];
tmp_51_reg_5417[2] <= tmp_51_fu_2984_p1[2];
tmp_51_reg_5417[3] <= tmp_51_fu_2984_p1[3];
tmp_51_reg_5417[4] <= tmp_51_fu_2984_p1[4];
tmp_51_reg_5417[5] <= tmp_51_fu_2984_p1[5];
tmp_51_reg_5417[6] <= tmp_51_fu_2984_p1[6];
tmp_51_reg_5417[7] <= tmp_51_fu_2984_p1[7];
tmp_51_reg_5417[8] <= tmp_51_fu_2984_p1[8];
tmp_51_reg_5417[9] <= tmp_51_fu_2984_p1[9];
tmp_51_reg_5417[10] <= tmp_51_fu_2984_p1[10];
tmp_51_reg_5417[11] <= tmp_51_fu_2984_p1[11];
tmp_51_reg_5417[12] <= tmp_51_fu_2984_p1[12];
tmp_51_reg_5417[13] <= tmp_51_fu_2984_p1[13];
end
if (((ap_ST_pp2_stg0_fsm_12 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp2_it0) & (ap_const_lv1_0 == exitcond4_fu_2988_p2))) begin
tmp_59_reg_5436[0] <= tmp_59_fu_3020_p1[0];
tmp_59_reg_5436[1] <= tmp_59_fu_3020_p1[1];
tmp_59_reg_5436[2] <= tmp_59_fu_3020_p1[2];
tmp_59_reg_5436[3] <= tmp_59_fu_3020_p1[3];
tmp_59_reg_5436[4] <= tmp_59_fu_3020_p1[4];
tmp_59_reg_5436[5] <= tmp_59_fu_3020_p1[5];
tmp_59_reg_5436[6] <= tmp_59_fu_3020_p1[6];
tmp_59_reg_5436[7] <= tmp_59_fu_3020_p1[7];
tmp_59_reg_5436[8] <= tmp_59_fu_3020_p1[8];
tmp_59_reg_5436[9] <= tmp_59_fu_3020_p1[9];
tmp_59_reg_5436[10] <= tmp_59_fu_3020_p1[10];
tmp_59_reg_5436[11] <= tmp_59_fu_3020_p1[11];
tmp_59_reg_5436[12] <= tmp_59_fu_3020_p1[12];
end
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0))) begin
tmp_5_reg_5175 <= (i_phi_fu_1890_p4 + ap_const_lv7_1);
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp3_it0) & (ap_ST_pp3_stg0_fsm_13 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond6_fu_3025_p2))) begin
tmp_67_reg_5488 <= {{50{b_addr11_fu_3087_p2[13]}}, {b_addr11_fu_3087_p2}};
end
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (ap_const_lv1_0 == exitcond1_fu_2377_p2))) begin
tmp_6_reg_5180[6] <= tmp_6_fu_2399_p1[6];
tmp_6_reg_5180[7] <= tmp_6_fu_2399_p1[7];
tmp_6_reg_5180[8] <= tmp_6_fu_2399_p1[8];
tmp_6_reg_5180[9] <= tmp_6_fu_2399_p1[9];
tmp_6_reg_5180[10] <= tmp_6_fu_2399_p1[10];
tmp_6_reg_5180[11] <= tmp_6_fu_2399_p1[11];
tmp_6_reg_5180[12] <= tmp_6_fu_2399_p1[12];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_ST_pp1_stg0_fsm_4 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond3_fu_2404_p2))) begin
tmp_6_trn_cast_reg_5226[0] <= tmp_6_trn_cast_fu_2452_p1[0];
tmp_6_trn_cast_reg_5226[1] <= tmp_6_trn_cast_fu_2452_p1[1];
tmp_6_trn_cast_reg_5226[2] <= tmp_6_trn_cast_fu_2452_p1[2];
tmp_6_trn_cast_reg_5226[3] <= tmp_6_trn_cast_fu_2452_p1[3];
tmp_6_trn_cast_reg_5226[4] <= tmp_6_trn_cast_fu_2452_p1[4];
tmp_6_trn_cast_reg_5226[5] <= tmp_6_trn_cast_fu_2452_p1[5];
tmp_6_trn_cast_reg_5226[6] <= tmp_6_trn_cast_fu_2452_p1[6];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp3_it0) & (ap_const_lv1_0 == exitcond6_reg_5446) & (ap_ST_pp3_stg1_fsm_14 == ap_CS_fsm))) begin
tmp_75_reg_5523 <= {{50{b_addr13_fu_3176_p2[13]}}, {b_addr13_fu_3176_p2}};
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp3_it0) & (ap_const_lv1_0 == exitcond6_reg_5446) & (ap_ST_pp3_stg4_fsm_17 == ap_CS_fsm))) begin
tmp_82_reg_5653 <= (i_3_mid2_reg_5455 + ap_const_lv7_8);
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp3_it0) & (ap_const_lv1_0 == exitcond6_reg_5446) & (ap_ST_pp3_stg1_fsm_14 == ap_CS_fsm))) begin
tmp_83_reg_5538 <= {{50{b_addr15_fu_3242_p2[13]}}, {b_addr15_fu_3242_p2}};
end
if (((ap_ST_pp3_stg2_fsm_15 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp3_it0) & (ap_const_lv1_0 == exitcond6_reg_5446))) begin
tmp_86_reg_5583 <= {{50{b_addr17_fu_3356_p2[13]}}, {b_addr17_fu_3356_p2}};
end
if (((ap_ST_pp6_stg0_fsm_30 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp6_it0))) begin
tmp_88_reg_5909 <= (j_4_phi_fu_2055_p4 + ap_const_lv7_1);
end
if (((ap_ST_pp1_stg1_fsm_5 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond3_reg_5195))) begin
tmp_8_trn_cast4_reg_5302 <= {{tmp_8_trn_cast_fu_2500_p1[ap_const_lv32_C : ap_const_lv32_6]}};
end
if (((ap_ST_pp1_stg1_fsm_5 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond3_reg_5195))) begin
tmp_8_trn_cast5_reg_5307 <= {{tmp_8_trn_cast_fu_2500_p1[ap_const_lv32_C : ap_const_lv32_6]}};
end
if (((ap_ST_pp1_stg1_fsm_5 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond3_reg_5195))) begin
tmp_8_trn_cast6_reg_5312 <= {{tmp_8_trn_cast_fu_2500_p1[ap_const_lv32_C : ap_const_lv32_6]}};
end
if (((ap_ST_pp1_stg1_fsm_5 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond3_reg_5195))) begin
tmp_8_trn_cast7_reg_5317 <= {{tmp_8_trn_cast_fu_2500_p1[ap_const_lv32_C : ap_const_lv32_6]}};
end
if (((ap_ST_pp1_stg1_fsm_5 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond3_reg_5195))) begin
tmp_8_trn_cast8_reg_5322 <= {{tmp_8_trn_cast_fu_2500_p1[ap_const_lv32_C : ap_const_lv32_6]}};
end
if (((ap_ST_pp1_stg1_fsm_5 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond3_reg_5195))) begin
tmp_8_trn_cast_reg_5257[0] <= tmp_8_trn_cast_fu_2500_p1[0];
tmp_8_trn_cast_reg_5257[1] <= tmp_8_trn_cast_fu_2500_p1[1];
tmp_8_trn_cast_reg_5257[2] <= tmp_8_trn_cast_fu_2500_p1[2];
tmp_8_trn_cast_reg_5257[3] <= tmp_8_trn_cast_fu_2500_p1[3];
tmp_8_trn_cast_reg_5257[4] <= tmp_8_trn_cast_fu_2500_p1[4];
tmp_8_trn_cast_reg_5257[5] <= tmp_8_trn_cast_fu_2500_p1[5];
end
if (((ap_ST_pp3_stg2_fsm_15 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp3_it0) & (ap_const_lv1_0 == exitcond6_reg_5446))) begin
tmp_90_reg_5598 <= {{50{b_addr19_fu_3410_p2[13]}}, {b_addr19_fu_3410_p2}};
end
if (((ap_ST_pp5_stg1_fsm_23 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp5_it0) & (ap_const_lv1_0 == exitcond9_reg_5697))) begin
tmp_97_reg_5785[0] <= tmp_97_fu_3780_p2[0];
tmp_97_reg_5785[2] <= tmp_97_fu_3780_p2[2];
tmp_97_reg_5785[3] <= tmp_97_fu_3780_p2[3];
tmp_97_reg_5785[4] <= tmp_97_fu_3780_p2[4];
tmp_97_reg_5785[5] <= tmp_97_fu_3780_p2[5];
tmp_97_reg_5785[6] <= tmp_97_fu_3780_p2[6];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp3_it0) & (ap_const_lv1_0 == exitcond6_reg_5446) & (ap_ST_pp3_stg3_fsm_16 == ap_CS_fsm))) begin
tmp_98_reg_5618 <= {{50{b_addr21_fu_3463_p2[13]}}, {b_addr21_fu_3463_p2}};
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_ST_pp1_stg0_fsm_4 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond3_fu_2404_p2))) begin
tmp_9_reg_5237[0] <= tmp_9_fu_2472_p1[0];
tmp_9_reg_5237[1] <= tmp_9_fu_2472_p1[1];
tmp_9_reg_5237[2] <= tmp_9_fu_2472_p1[2];
tmp_9_reg_5237[3] <= tmp_9_fu_2472_p1[3];
tmp_9_reg_5237[4] <= tmp_9_fu_2472_p1[4];
tmp_9_reg_5237[5] <= tmp_9_fu_2472_p1[5];
tmp_9_reg_5237[6] <= tmp_9_fu_2472_p1[6];
tmp_9_reg_5237[7] <= tmp_9_fu_2472_p1[7];
tmp_9_reg_5237[8] <= tmp_9_fu_2472_p1[8];
tmp_9_reg_5237[9] <= tmp_9_fu_2472_p1[9];
tmp_9_reg_5237[10] <= tmp_9_fu_2472_p1[10];
tmp_9_reg_5237[11] <= tmp_9_fu_2472_p1[11];
tmp_9_reg_5237[12] <= tmp_9_fu_2472_p1[12];
tmp_9_reg_5237[13] <= tmp_9_fu_2472_p1[13];
end
end
/// a_address0 assign process. ///
always @ (ap_CS_fsm or ap_reg_ppiten_pp0_it0 or ap_reg_ppiten_pp1_it0 or ap_reg_ppiten_pp1_it1 or exitcond3_reg_5195 or ap_reg_ppiten_pp3_it0 or ap_reg_ppiten_pp3_it1 or ap_reg_ppiten_pp3_it2 or exitcond6_reg_5446 or ap_reg_ppiten_pp4_it0 or ap_reg_ppiten_pp5_it0 or ap_reg_ppiten_pp5_it1 or exitcond9_reg_5697 or ap_reg_ppiten_pp7_it0 or ap_reg_ppiten_pp7_it1 or ap_reg_ppiten_pp7_it2 or exitcond12_reg_5924 or ap_reg_ppiten_pp2_it6 or ap_reg_ppiten_pp6_it6 or ap_reg_ppstg_exitcond6_reg_5446_pp3_it1 or ap_reg_ppstg_exitcond12_reg_5924_pp7_it1 or ap_reg_ppstg_exitcond3_reg_5195_pp1_it1 or ap_reg_ppstg_exitcond9_reg_5697_pp5_it1 or exitcond1_fu_2377_p2 or tmp_6_fu_2399_p1 or exitcond3_fu_2404_p2 or tmp_9_fu_2472_p1 or tmp_15_fu_2560_p1 or tmp_28_fu_2740_p1 or tmp_44_fu_2847_p1 or tmp_51_fu_2984_p1 or ap_reg_ppstg_exitcond4_reg_5427_pp2_it5 or ap_reg_ppstg_tmp_59_reg_5436_pp2_it5 or ap_reg_ppstg_tmp_67_reg_5488_pp3_it1 or ap_reg_ppstg_tmp_83_reg_5538_pp3_it1 or ap_reg_ppstg_tmp_86_reg_5583_pp3_it1 or ap_reg_ppstg_tmp_90_reg_5598_pp3_it1 or exitcond7_fu_3609_p2 or tmp_122_fu_3621_p1 or exitcond9_fu_3626_p2 or tmp_125_fu_3694_p1 or tmp_130_fu_3764_p1 or tmp_146_fu_3830_p1 or tmp_160_fu_3895_p1 or tmp_168_fu_3974_p1 or ap_reg_ppstg_exitcond10_reg_5905_pp6_it5 or ap_reg_ppstg_tmp_172_reg_5914_pp6_it5 or ap_reg_ppstg_tmp_174_reg_5967_pp7_it1 or ap_reg_ppstg_tmp_182_reg_6017_pp7_it1 or ap_reg_ppstg_tmp_186_reg_6032_pp7_it1 or ap_reg_ppstg_tmp_190_reg_6052_pp7_it1 or exitcond_fu_4357_p2 or exitcond_reg_6132 or ap_reg_ppiten_pp8_it0 or tmp_199_fu_4421_p1 or tmp_200_fu_4454_p1 or tmp_202_fu_4492_p1 or tmp_204_fu_4530_p1 or tmp_206_fu_4573_p1 or tmp_208_fu_4611_p1 or tmp_210_fu_4629_p1 or tmp_212_fu_4647_p1 or tmp_214_fu_4685_p1 or tmp_216_fu_4704_p1 or tmp_218_fu_4722_p1 or tmp_220_fu_4745_p1 or tmp_222_fu_4778_p1 or tmp_224_fu_4796_p1 or tmp_226_fu_4814_p1 or tmp_228_fu_4852_p1 or tmp_230_fu_4871_p1 or tmp_232_fu_4889_p1 or tmp_234_fu_4912_p1 or tmp_236_fu_4945_p1 or tmp_238_fu_4963_p1 or tmp_240_fu_4981_p1 or tmp_242_fu_5019_p1 or tmp_244_fu_5038_p1 or tmp_246_fu_5061_p1 or tmp_248_fu_5128_p1 or tmp_250_fu_5136_p1 or tmp_252_fu_5144_p1 or tmp_254_fu_5152_p1 or tmp_71_fu_3152_p1 or tmp_85_fu_3332_p1 or tmp_94_fu_3439_p1 or tmp_110_fu_3542_p1 or tmp_176_fu_4120_p1 or tmp_184_fu_4186_p1 or tmp_191_fu_4251_p1 or tmp_196_fu_4303_p1)
begin
if (((ap_const_logic_1 == ap_reg_ppiten_pp7_it2) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond12_reg_5924_pp7_it1) & (ap_ST_pp7_stg0_fsm_31 == ap_CS_fsm))) begin
a_address0 = ap_reg_ppstg_tmp_190_reg_6052_pp7_it1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp7_it1) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond12_reg_5924_pp7_it1) & (ap_ST_pp7_stg7_fsm_38 == ap_CS_fsm))) begin
a_address0 = ap_reg_ppstg_tmp_186_reg_6032_pp7_it1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp7_it1) & (ap_ST_pp7_stg6_fsm_37 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond12_reg_5924_pp7_it1))) begin
a_address0 = ap_reg_ppstg_tmp_182_reg_6017_pp7_it1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp7_it1) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond12_reg_5924_pp7_it1) & (ap_ST_pp7_stg5_fsm_36 == ap_CS_fsm))) begin
a_address0 = ap_reg_ppstg_tmp_174_reg_5967_pp7_it1;
end else if (((ap_ST_pp6_stg0_fsm_30 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp6_it6) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond10_reg_5905_pp6_it5))) begin
a_address0 = ap_reg_ppstg_tmp_172_reg_5914_pp6_it5;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp3_it2) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond6_reg_5446_pp3_it1) & (ap_ST_pp3_stg0_fsm_13 == ap_CS_fsm))) begin
a_address0 = ap_reg_ppstg_tmp_90_reg_5598_pp3_it1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp3_it1) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond6_reg_5446_pp3_it1) & (ap_ST_pp3_stg7_fsm_20 == ap_CS_fsm))) begin
a_address0 = ap_reg_ppstg_tmp_86_reg_5583_pp3_it1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp3_it1) & (ap_ST_pp3_stg6_fsm_19 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond6_reg_5446_pp3_it1))) begin
a_address0 = ap_reg_ppstg_tmp_83_reg_5538_pp3_it1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp3_it1) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond6_reg_5446_pp3_it1) & (ap_ST_pp3_stg5_fsm_18 == ap_CS_fsm))) begin
a_address0 = ap_reg_ppstg_tmp_67_reg_5488_pp3_it1;
end else if (((ap_ST_pp2_stg0_fsm_12 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp2_it6) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond4_reg_5427_pp2_it5))) begin
a_address0 = ap_reg_ppstg_tmp_59_reg_5436_pp2_it5;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg28_fsm_68 == ap_CS_fsm))) begin
a_address0 = tmp_254_fu_5152_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg27_fsm_67 == ap_CS_fsm))) begin
a_address0 = tmp_252_fu_5144_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg26_fsm_66 == ap_CS_fsm))) begin
a_address0 = tmp_250_fu_5136_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg25_fsm_65 == ap_CS_fsm))) begin
a_address0 = tmp_248_fu_5128_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg24_fsm_64 == ap_CS_fsm))) begin
a_address0 = tmp_246_fu_5061_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg23_fsm_63 == ap_CS_fsm))) begin
a_address0 = tmp_244_fu_5038_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg22_fsm_62 == ap_CS_fsm))) begin
a_address0 = tmp_242_fu_5019_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg21_fsm_61 == ap_CS_fsm))) begin
a_address0 = tmp_240_fu_4981_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg20_fsm_60 == ap_CS_fsm))) begin
a_address0 = tmp_238_fu_4963_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg19_fsm_59 == ap_CS_fsm))) begin
a_address0 = tmp_236_fu_4945_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg18_fsm_58 == ap_CS_fsm))) begin
a_address0 = tmp_234_fu_4912_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg17_fsm_57 == ap_CS_fsm))) begin
a_address0 = tmp_232_fu_4889_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg16_fsm_56 == ap_CS_fsm))) begin
a_address0 = tmp_230_fu_4871_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg15_fsm_55 == ap_CS_fsm))) begin
a_address0 = tmp_228_fu_4852_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg14_fsm_54 == ap_CS_fsm))) begin
a_address0 = tmp_226_fu_4814_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg13_fsm_53 == ap_CS_fsm))) begin
a_address0 = tmp_224_fu_4796_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg12_fsm_52 == ap_CS_fsm))) begin
a_address0 = tmp_222_fu_4778_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg11_fsm_51 == ap_CS_fsm))) begin
a_address0 = tmp_220_fu_4745_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg10_fsm_50 == ap_CS_fsm))) begin
a_address0 = tmp_218_fu_4722_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg9_fsm_49 == ap_CS_fsm))) begin
a_address0 = tmp_216_fu_4704_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg8_fsm_48 == ap_CS_fsm))) begin
a_address0 = tmp_214_fu_4685_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg7_fsm_47 == ap_CS_fsm))) begin
a_address0 = tmp_212_fu_4647_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg6_fsm_46 == ap_CS_fsm))) begin
a_address0 = tmp_210_fu_4629_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg5_fsm_45 == ap_CS_fsm))) begin
a_address0 = tmp_208_fu_4611_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg4_fsm_44 == ap_CS_fsm))) begin
a_address0 = tmp_206_fu_4573_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg3_fsm_43 == ap_CS_fsm))) begin
a_address0 = tmp_204_fu_4530_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg2_fsm_42 == ap_CS_fsm))) begin
a_address0 = tmp_202_fu_4492_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_ST_pp8_stg1_fsm_41 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond_reg_6132))) begin
a_address0 = tmp_200_fu_4454_p1;
end else if (((ap_ST_pp8_stg0_fsm_40 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_fu_4357_p2))) begin
a_address0 = tmp_199_fu_4421_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp7_it0) & (ap_const_lv1_0 == exitcond12_reg_5924) & (ap_ST_pp7_stg4_fsm_35 == ap_CS_fsm))) begin
a_address0 = tmp_196_fu_4303_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp7_it0) & (ap_const_lv1_0 == exitcond12_reg_5924) & (ap_ST_pp7_stg3_fsm_34 == ap_CS_fsm))) begin
a_address0 = tmp_191_fu_4251_p1;
end else if (((ap_ST_pp7_stg2_fsm_33 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp7_it0) & (ap_const_lv1_0 == exitcond12_reg_5924))) begin
a_address0 = tmp_184_fu_4186_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp7_it0) & (ap_const_lv1_0 == exitcond12_reg_5924) & (ap_ST_pp7_stg1_fsm_32 == ap_CS_fsm))) begin
a_address0 = tmp_176_fu_4120_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp5_it1) & (ap_ST_pp5_stg4_fsm_26 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond9_reg_5697_pp5_it1))) begin
a_address0 = tmp_168_fu_3974_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp5_it0) & (ap_const_lv1_0 == exitcond9_reg_5697) & (ap_ST_pp5_stg3_fsm_25 == ap_CS_fsm))) begin
a_address0 = tmp_160_fu_3895_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp5_it0) & (ap_const_lv1_0 == exitcond9_reg_5697) & (ap_ST_pp5_stg2_fsm_24 == ap_CS_fsm))) begin
a_address0 = tmp_146_fu_3830_p1;
end else if (((ap_ST_pp5_stg1_fsm_23 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp5_it0) & (ap_const_lv1_0 == exitcond9_reg_5697))) begin
a_address0 = tmp_130_fu_3764_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp5_it0) & (ap_ST_pp5_stg0_fsm_22 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond9_fu_3626_p2))) begin
a_address0 = tmp_125_fu_3694_p1;
end else if (((ap_ST_pp4_stg0_fsm_21 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp4_it0) & (ap_const_lv1_0 == exitcond7_fu_3609_p2))) begin
a_address0 = tmp_122_fu_3621_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp3_it0) & (ap_const_lv1_0 == exitcond6_reg_5446) & (ap_ST_pp3_stg4_fsm_17 == ap_CS_fsm))) begin
a_address0 = tmp_110_fu_3542_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp3_it0) & (ap_const_lv1_0 == exitcond6_reg_5446) & (ap_ST_pp3_stg3_fsm_16 == ap_CS_fsm))) begin
a_address0 = tmp_94_fu_3439_p1;
end else if (((ap_ST_pp3_stg2_fsm_15 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp3_it0) & (ap_const_lv1_0 == exitcond6_reg_5446))) begin
a_address0 = tmp_85_fu_3332_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp3_it0) & (ap_const_lv1_0 == exitcond6_reg_5446) & (ap_ST_pp3_stg1_fsm_14 == ap_CS_fsm))) begin
a_address0 = tmp_71_fu_3152_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_ST_pp1_stg4_fsm_8 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond3_reg_5195_pp1_it1))) begin
a_address0 = tmp_51_fu_2984_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond3_reg_5195) & (ap_ST_pp1_stg3_fsm_7 == ap_CS_fsm))) begin
a_address0 = tmp_44_fu_2847_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond3_reg_5195) & (ap_ST_pp1_stg2_fsm_6 == ap_CS_fsm))) begin
a_address0 = tmp_28_fu_2740_p1;
end else if (((ap_ST_pp1_stg1_fsm_5 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond3_reg_5195))) begin
a_address0 = tmp_15_fu_2560_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_ST_pp1_stg0_fsm_4 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond3_fu_2404_p2))) begin
a_address0 = tmp_9_fu_2472_p1;
end else if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (ap_const_lv1_0 == exitcond1_fu_2377_p2))) begin
a_address0 = tmp_6_fu_2399_p1;
end else begin
a_address0 = ap_reg_ppstg_tmp_190_reg_6052_pp7_it1;
end
end
/// a_address1 assign process. ///
always @ (ap_CS_fsm or ap_reg_ppiten_pp1_it0 or ap_reg_ppiten_pp1_it1 or exitcond3_reg_5195 or ap_reg_ppiten_pp3_it0 or ap_reg_ppiten_pp3_it1 or ap_reg_ppiten_pp3_it2 or exitcond6_reg_5446 or ap_reg_ppiten_pp5_it0 or ap_reg_ppiten_pp5_it1 or exitcond9_reg_5697 or ap_reg_ppiten_pp7_it0 or ap_reg_ppiten_pp7_it1 or ap_reg_ppiten_pp7_it2 or exitcond12_reg_5924 or ap_reg_ppstg_exitcond6_reg_5446_pp3_it1 or ap_reg_ppstg_exitcond12_reg_5924_pp7_it1 or ap_reg_ppiten_pp3_it3 or ap_reg_ppiten_pp7_it3 or ap_reg_ppstg_exitcond3_reg_5195_pp1_it1 or ap_reg_ppstg_exitcond9_reg_5697_pp5_it1 or ap_reg_ppstg_exitcond6_reg_5446_pp3_it2 or ap_reg_ppstg_exitcond12_reg_5924_pp7_it2 or tmp_20_fu_2626_p1 or tmp_36_fu_2794_p1 or tmp_47_fu_2980_p1 or ap_reg_ppstg_tmp_75_reg_5523_pp3_it1 or ap_reg_ppstg_tmp_98_reg_5618_pp3_it2 or ap_reg_ppstg_tmp_106_reg_5658_pp3_it2 or ap_reg_ppstg_tmp_114_reg_5668_pp3_it2 or tmp_138_fu_3794_p1 or tmp_154_fu_3859_p1 or tmp_164_fu_3961_p1 or ap_reg_ppstg_tmp_178_reg_5997_pp7_it1 or ap_reg_ppstg_tmp_192_reg_6067_pp7_it2 or ap_reg_ppstg_tmp_194_reg_6107_pp7_it2 or ap_reg_ppstg_tmp_197_reg_6122_pp7_it2 or exitcond_reg_6132 or ap_reg_ppiten_pp8_it0 or tmp_201_fu_4473_p1 or tmp_203_fu_4511_p1 or tmp_205_fu_4549_p1 or tmp_207_fu_4597_p1 or tmp_209_fu_4620_p1 or tmp_211_fu_4638_p1 or tmp_213_fu_4656_p1 or tmp_215_fu_4695_p1 or tmp_217_fu_4713_p1 or tmp_219_fu_4731_p1 or tmp_221_fu_4769_p1 or tmp_223_fu_4787_p1 or tmp_225_fu_4805_p1 or tmp_227_fu_4823_p1 or tmp_229_fu_4862_p1 or tmp_231_fu_4880_p1 or tmp_233_fu_4898_p1 or tmp_235_fu_4936_p1 or tmp_237_fu_4954_p1 or tmp_239_fu_4972_p1 or tmp_241_fu_4990_p1 or tmp_243_fu_5029_p1 or tmp_245_fu_5047_p1 or tmp_247_fu_5070_p1 or tmp_249_fu_5132_p1 or tmp_251_fu_5140_p1 or tmp_253_fu_5148_p1 or tmp_255_fu_5156_p1 or tmp_79_fu_3218_p1 or tmp_89_fu_3386_p1 or tmp_102_fu_3493_p1 or tmp_118_fu_3591_p1 or tmp_180_fu_4154_p1 or tmp_188_fu_4219_p1 or tmp_193_fu_4284_p1 or tmp_198_fu_4322_p1)
begin
if (((ap_ST_pp7_stg0_fsm_31 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp7_it3) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond12_reg_5924_pp7_it2))) begin
a_address1 = ap_reg_ppstg_tmp_197_reg_6122_pp7_it2;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp7_it2) & (ap_ST_pp7_stg7_fsm_38 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond12_reg_5924_pp7_it2))) begin
a_address1 = ap_reg_ppstg_tmp_194_reg_6107_pp7_it2;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp7_it2) & (ap_ST_pp7_stg6_fsm_37 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond12_reg_5924_pp7_it2))) begin
a_address1 = ap_reg_ppstg_tmp_192_reg_6067_pp7_it2;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp7_it1) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond12_reg_5924_pp7_it1) & (ap_ST_pp7_stg5_fsm_36 == ap_CS_fsm))) begin
a_address1 = ap_reg_ppstg_tmp_178_reg_5997_pp7_it1;
end else if (((ap_ST_pp3_stg0_fsm_13 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp3_it3) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond6_reg_5446_pp3_it2))) begin
a_address1 = ap_reg_ppstg_tmp_114_reg_5668_pp3_it2;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp3_it2) & (ap_ST_pp3_stg7_fsm_20 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond6_reg_5446_pp3_it2))) begin
a_address1 = ap_reg_ppstg_tmp_106_reg_5658_pp3_it2;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp3_it2) & (ap_ST_pp3_stg6_fsm_19 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond6_reg_5446_pp3_it2))) begin
a_address1 = ap_reg_ppstg_tmp_98_reg_5618_pp3_it2;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp3_it1) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond6_reg_5446_pp3_it1) & (ap_ST_pp3_stg5_fsm_18 == ap_CS_fsm))) begin
a_address1 = ap_reg_ppstg_tmp_75_reg_5523_pp3_it1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg28_fsm_68 == ap_CS_fsm))) begin
a_address1 = tmp_255_fu_5156_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg27_fsm_67 == ap_CS_fsm))) begin
a_address1 = tmp_253_fu_5148_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg26_fsm_66 == ap_CS_fsm))) begin
a_address1 = tmp_251_fu_5140_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg25_fsm_65 == ap_CS_fsm))) begin
a_address1 = tmp_249_fu_5132_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg24_fsm_64 == ap_CS_fsm))) begin
a_address1 = tmp_247_fu_5070_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg23_fsm_63 == ap_CS_fsm))) begin
a_address1 = tmp_245_fu_5047_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg22_fsm_62 == ap_CS_fsm))) begin
a_address1 = tmp_243_fu_5029_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg21_fsm_61 == ap_CS_fsm))) begin
a_address1 = tmp_241_fu_4990_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg20_fsm_60 == ap_CS_fsm))) begin
a_address1 = tmp_239_fu_4972_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg19_fsm_59 == ap_CS_fsm))) begin
a_address1 = tmp_237_fu_4954_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg18_fsm_58 == ap_CS_fsm))) begin
a_address1 = tmp_235_fu_4936_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg17_fsm_57 == ap_CS_fsm))) begin
a_address1 = tmp_233_fu_4898_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg16_fsm_56 == ap_CS_fsm))) begin
a_address1 = tmp_231_fu_4880_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg15_fsm_55 == ap_CS_fsm))) begin
a_address1 = tmp_229_fu_4862_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg14_fsm_54 == ap_CS_fsm))) begin
a_address1 = tmp_227_fu_4823_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg13_fsm_53 == ap_CS_fsm))) begin
a_address1 = tmp_225_fu_4805_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg12_fsm_52 == ap_CS_fsm))) begin
a_address1 = tmp_223_fu_4787_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg11_fsm_51 == ap_CS_fsm))) begin
a_address1 = tmp_221_fu_4769_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg10_fsm_50 == ap_CS_fsm))) begin
a_address1 = tmp_219_fu_4731_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg9_fsm_49 == ap_CS_fsm))) begin
a_address1 = tmp_217_fu_4713_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg8_fsm_48 == ap_CS_fsm))) begin
a_address1 = tmp_215_fu_4695_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg7_fsm_47 == ap_CS_fsm))) begin
a_address1 = tmp_213_fu_4656_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg6_fsm_46 == ap_CS_fsm))) begin
a_address1 = tmp_211_fu_4638_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg5_fsm_45 == ap_CS_fsm))) begin
a_address1 = tmp_209_fu_4620_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg4_fsm_44 == ap_CS_fsm))) begin
a_address1 = tmp_207_fu_4597_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg3_fsm_43 == ap_CS_fsm))) begin
a_address1 = tmp_205_fu_4549_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg2_fsm_42 == ap_CS_fsm))) begin
a_address1 = tmp_203_fu_4511_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_ST_pp8_stg1_fsm_41 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond_reg_6132))) begin
a_address1 = tmp_201_fu_4473_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp7_it0) & (ap_const_lv1_0 == exitcond12_reg_5924) & (ap_ST_pp7_stg4_fsm_35 == ap_CS_fsm))) begin
a_address1 = tmp_198_fu_4322_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp7_it0) & (ap_const_lv1_0 == exitcond12_reg_5924) & (ap_ST_pp7_stg3_fsm_34 == ap_CS_fsm))) begin
a_address1 = tmp_193_fu_4284_p1;
end else if (((ap_ST_pp7_stg2_fsm_33 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp7_it0) & (ap_const_lv1_0 == exitcond12_reg_5924))) begin
a_address1 = tmp_188_fu_4219_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp7_it0) & (ap_const_lv1_0 == exitcond12_reg_5924) & (ap_ST_pp7_stg1_fsm_32 == ap_CS_fsm))) begin
a_address1 = tmp_180_fu_4154_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp5_it1) & (ap_ST_pp5_stg3_fsm_25 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond9_reg_5697_pp5_it1))) begin
a_address1 = tmp_164_fu_3961_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp5_it0) & (ap_const_lv1_0 == exitcond9_reg_5697) & (ap_ST_pp5_stg2_fsm_24 == ap_CS_fsm))) begin
a_address1 = tmp_154_fu_3859_p1;
end else if (((ap_ST_pp5_stg1_fsm_23 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp5_it0) & (ap_const_lv1_0 == exitcond9_reg_5697))) begin
a_address1 = tmp_138_fu_3794_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp3_it0) & (ap_const_lv1_0 == exitcond6_reg_5446) & (ap_ST_pp3_stg4_fsm_17 == ap_CS_fsm))) begin
a_address1 = tmp_118_fu_3591_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp3_it0) & (ap_const_lv1_0 == exitcond6_reg_5446) & (ap_ST_pp3_stg3_fsm_16 == ap_CS_fsm))) begin
a_address1 = tmp_102_fu_3493_p1;
end else if (((ap_ST_pp3_stg2_fsm_15 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp3_it0) & (ap_const_lv1_0 == exitcond6_reg_5446))) begin
a_address1 = tmp_89_fu_3386_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp3_it0) & (ap_const_lv1_0 == exitcond6_reg_5446) & (ap_ST_pp3_stg1_fsm_14 == ap_CS_fsm))) begin
a_address1 = tmp_79_fu_3218_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_ST_pp1_stg3_fsm_7 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond3_reg_5195_pp1_it1))) begin
a_address1 = tmp_47_fu_2980_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond3_reg_5195) & (ap_ST_pp1_stg2_fsm_6 == ap_CS_fsm))) begin
a_address1 = tmp_36_fu_2794_p1;
end else if (((ap_ST_pp1_stg1_fsm_5 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond3_reg_5195))) begin
a_address1 = tmp_20_fu_2626_p1;
end else begin
a_address1 = ap_reg_ppstg_tmp_197_reg_6122_pp7_it2;
end
end
/// a_ce0 assign process. ///
always @ (ap_CS_fsm or ap_reg_ppiten_pp0_it0 or ap_reg_ppiten_pp1_it0 or ap_reg_ppiten_pp1_it1 or exitcond3_reg_5195 or ap_reg_ppiten_pp3_it0 or ap_reg_ppiten_pp3_it1 or ap_reg_ppiten_pp3_it2 or exitcond6_reg_5446 or ap_reg_ppiten_pp4_it0 or ap_reg_ppiten_pp5_it0 or ap_reg_ppiten_pp5_it1 or exitcond9_reg_5697 or ap_reg_ppiten_pp7_it0 or ap_reg_ppiten_pp7_it1 or ap_reg_ppiten_pp7_it2 or exitcond12_reg_5924 or ap_reg_ppiten_pp2_it6 or ap_reg_ppiten_pp6_it6 or ap_reg_ppstg_exitcond6_reg_5446_pp3_it1 or ap_reg_ppstg_exitcond12_reg_5924_pp7_it1 or ap_reg_ppstg_exitcond3_reg_5195_pp1_it1 or ap_reg_ppstg_exitcond9_reg_5697_pp5_it1 or exitcond1_fu_2377_p2 or exitcond3_fu_2404_p2 or ap_reg_ppstg_exitcond4_reg_5427_pp2_it5 or exitcond7_fu_3609_p2 or exitcond9_fu_3626_p2 or ap_reg_ppstg_exitcond10_reg_5905_pp6_it5 or exitcond_fu_4357_p2 or exitcond_reg_6132 or ap_reg_ppiten_pp8_it0)
begin
if ((((ap_ST_pp1_stg1_fsm_5 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond3_reg_5195)) | ((ap_ST_pp3_stg2_fsm_15 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp3_it0) & (ap_const_lv1_0 == exitcond6_reg_5446)) | ((ap_ST_pp5_stg1_fsm_23 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp5_it0) & (ap_const_lv1_0 == exitcond9_reg_5697)) | ((ap_ST_pp7_stg2_fsm_33 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp7_it0) & (ap_const_lv1_0 == exitcond12_reg_5924)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond3_reg_5195) & (ap_ST_pp1_stg2_fsm_6 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp3_it0) & (ap_const_lv1_0 == exitcond6_reg_5446) & (ap_ST_pp3_stg1_fsm_14 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp5_it0) & (ap_const_lv1_0 == exitcond9_reg_5697) & (ap_ST_pp5_stg2_fsm_24 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp7_it0) & (ap_const_lv1_0 == exitcond12_reg_5924) & (ap_ST_pp7_stg1_fsm_32 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp3_it0) & (ap_const_lv1_0 == exitcond6_reg_5446) & (ap_ST_pp3_stg3_fsm_16 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp7_it0) & (ap_const_lv1_0 == exitcond12_reg_5924) & (ap_ST_pp7_stg3_fsm_34 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond3_reg_5195) & (ap_ST_pp1_stg3_fsm_7 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp5_it0) & (ap_const_lv1_0 == exitcond9_reg_5697) & (ap_ST_pp5_stg3_fsm_25 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp3_it0) & (ap_const_lv1_0 == exitcond6_reg_5446) & (ap_ST_pp3_stg4_fsm_17 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp7_it0) & (ap_const_lv1_0 == exitcond12_reg_5924) & (ap_ST_pp7_stg4_fsm_35 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp3_it1) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond6_reg_5446_pp3_it1) & (ap_ST_pp3_stg5_fsm_18 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp7_it1) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond12_reg_5924_pp7_it1) & (ap_ST_pp7_stg5_fsm_36 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp3_it1) & (ap_ST_pp3_stg6_fsm_19 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond6_reg_5446_pp3_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp3_it1) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond6_reg_5446_pp3_it1) & (ap_ST_pp3_stg7_fsm_20 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp7_it1) & (ap_ST_pp7_stg6_fsm_37 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond12_reg_5924_pp7_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp7_it1) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond12_reg_5924_pp7_it1) & (ap_ST_pp7_stg7_fsm_38 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_ST_pp1_stg4_fsm_8 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond3_reg_5195_pp1_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp5_it1) & (ap_ST_pp5_stg4_fsm_26 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond9_reg_5697_pp5_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp3_it2) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond6_reg_5446_pp3_it1) & (ap_ST_pp3_stg0_fsm_13 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp7_it2) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond12_reg_5924_pp7_it1) & (ap_ST_pp7_stg0_fsm_31 == ap_CS_fsm)) | ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (ap_const_lv1_0 == exitcond1_fu_2377_p2)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_ST_pp1_stg0_fsm_4 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond3_fu_2404_p2)) | ((ap_ST_pp4_stg0_fsm_21 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp4_it0) & (ap_const_lv1_0 == exitcond7_fu_3609_p2)) | ((ap_const_logic_1 == ap_reg_ppiten_pp5_it0) & (ap_ST_pp5_stg0_fsm_22 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond9_fu_3626_p2)) | ((ap_ST_pp8_stg0_fsm_40 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_fu_4357_p2)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_ST_pp8_stg1_fsm_41 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond_reg_6132)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg2_fsm_42 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg3_fsm_43 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg4_fsm_44 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg5_fsm_45 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg6_fsm_46 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg7_fsm_47 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg8_fsm_48 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg9_fsm_49 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg10_fsm_50 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg11_fsm_51 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg12_fsm_52 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg13_fsm_53 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg14_fsm_54 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg15_fsm_55 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg16_fsm_56 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg17_fsm_57 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg18_fsm_58 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg19_fsm_59 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg20_fsm_60 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg21_fsm_61 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg22_fsm_62 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg23_fsm_63 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg24_fsm_64 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg25_fsm_65 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg26_fsm_66 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg27_fsm_67 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg28_fsm_68 == ap_CS_fsm)) | ((ap_ST_pp2_stg0_fsm_12 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp2_it6) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond4_reg_5427_pp2_it5)) | ((ap_ST_pp6_stg0_fsm_30 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp6_it6) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond10_reg_5905_pp6_it5)))) begin
a_ce0 = ap_const_logic_1;
end else begin
a_ce0 = ap_const_logic_0;
end
end
/// a_ce1 assign process. ///
always @ (ap_CS_fsm or ap_reg_ppiten_pp1_it0 or ap_reg_ppiten_pp1_it1 or exitcond3_reg_5195 or ap_reg_ppiten_pp3_it0 or ap_reg_ppiten_pp3_it1 or ap_reg_ppiten_pp3_it2 or exitcond6_reg_5446 or ap_reg_ppiten_pp5_it0 or ap_reg_ppiten_pp5_it1 or exitcond9_reg_5697 or ap_reg_ppiten_pp7_it0 or ap_reg_ppiten_pp7_it1 or ap_reg_ppiten_pp7_it2 or exitcond12_reg_5924 or ap_reg_ppstg_exitcond6_reg_5446_pp3_it1 or ap_reg_ppstg_exitcond12_reg_5924_pp7_it1 or ap_reg_ppiten_pp3_it3 or ap_reg_ppiten_pp7_it3 or ap_reg_ppstg_exitcond3_reg_5195_pp1_it1 or ap_reg_ppstg_exitcond9_reg_5697_pp5_it1 or ap_reg_ppstg_exitcond6_reg_5446_pp3_it2 or ap_reg_ppstg_exitcond12_reg_5924_pp7_it2 or exitcond_reg_6132 or ap_reg_ppiten_pp8_it0)
begin
if ((((ap_ST_pp1_stg1_fsm_5 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond3_reg_5195)) | ((ap_ST_pp3_stg2_fsm_15 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp3_it0) & (ap_const_lv1_0 == exitcond6_reg_5446)) | ((ap_ST_pp5_stg1_fsm_23 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp5_it0) & (ap_const_lv1_0 == exitcond9_reg_5697)) | ((ap_ST_pp7_stg2_fsm_33 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp7_it0) & (ap_const_lv1_0 == exitcond12_reg_5924)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond3_reg_5195) & (ap_ST_pp1_stg2_fsm_6 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp3_it0) & (ap_const_lv1_0 == exitcond6_reg_5446) & (ap_ST_pp3_stg1_fsm_14 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp5_it0) & (ap_const_lv1_0 == exitcond9_reg_5697) & (ap_ST_pp5_stg2_fsm_24 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp7_it0) & (ap_const_lv1_0 == exitcond12_reg_5924) & (ap_ST_pp7_stg1_fsm_32 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp3_it0) & (ap_const_lv1_0 == exitcond6_reg_5446) & (ap_ST_pp3_stg3_fsm_16 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp7_it0) & (ap_const_lv1_0 == exitcond12_reg_5924) & (ap_ST_pp7_stg3_fsm_34 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp3_it0) & (ap_const_lv1_0 == exitcond6_reg_5446) & (ap_ST_pp3_stg4_fsm_17 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp7_it0) & (ap_const_lv1_0 == exitcond12_reg_5924) & (ap_ST_pp7_stg4_fsm_35 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp3_it1) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond6_reg_5446_pp3_it1) & (ap_ST_pp3_stg5_fsm_18 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp7_it1) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond12_reg_5924_pp7_it1) & (ap_ST_pp7_stg5_fsm_36 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_ST_pp1_stg3_fsm_7 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond3_reg_5195_pp1_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp5_it1) & (ap_ST_pp5_stg3_fsm_25 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond9_reg_5697_pp5_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_ST_pp8_stg1_fsm_41 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond_reg_6132)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg2_fsm_42 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg3_fsm_43 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg4_fsm_44 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg5_fsm_45 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg6_fsm_46 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg7_fsm_47 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg8_fsm_48 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg9_fsm_49 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg10_fsm_50 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg11_fsm_51 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg12_fsm_52 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg13_fsm_53 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg14_fsm_54 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg15_fsm_55 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg16_fsm_56 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg17_fsm_57 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg18_fsm_58 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg19_fsm_59 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg20_fsm_60 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg21_fsm_61 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg22_fsm_62 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg23_fsm_63 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg24_fsm_64 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg25_fsm_65 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg26_fsm_66 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg27_fsm_67 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg28_fsm_68 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp3_it2) & (ap_ST_pp3_stg6_fsm_19 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond6_reg_5446_pp3_it2)) | ((ap_const_logic_1 == ap_reg_ppiten_pp3_it2) & (ap_ST_pp3_stg7_fsm_20 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond6_reg_5446_pp3_it2)) | ((ap_ST_pp3_stg0_fsm_13 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp3_it3) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond6_reg_5446_pp3_it2)) | ((ap_const_logic_1 == ap_reg_ppiten_pp7_it2) & (ap_ST_pp7_stg6_fsm_37 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond12_reg_5924_pp7_it2)) | ((ap_const_logic_1 == ap_reg_ppiten_pp7_it2) & (ap_ST_pp7_stg7_fsm_38 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond12_reg_5924_pp7_it2)) | ((ap_ST_pp7_stg0_fsm_31 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp7_it3) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond12_reg_5924_pp7_it2)))) begin
a_ce1 = ap_const_logic_1;
end else begin
a_ce1 = ap_const_logic_0;
end
end
/// a_d0 assign process. ///
always @ (ap_CS_fsm or ap_reg_ppiten_pp3_it1 or ap_reg_ppiten_pp3_it2 or ap_reg_ppiten_pp7_it1 or ap_reg_ppiten_pp7_it2 or reg_2177 or ap_reg_ppiten_pp2_it6 or ap_reg_ppiten_pp6_it6 or ap_reg_ppstg_exitcond6_reg_5446_pp3_it1 or ap_reg_ppstg_exitcond12_reg_5924_pp7_it1 or reg_2294 or ap_reg_ppstg_exitcond4_reg_5427_pp2_it5 or ap_reg_ppstg_exitcond10_reg_5905_pp6_it5)
begin
if ((((ap_const_logic_1 == ap_reg_ppiten_pp3_it1) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond6_reg_5446_pp3_it1) & (ap_ST_pp3_stg5_fsm_18 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp7_it1) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond12_reg_5924_pp7_it1) & (ap_ST_pp7_stg5_fsm_36 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp3_it1) & (ap_ST_pp3_stg6_fsm_19 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond6_reg_5446_pp3_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp3_it1) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond6_reg_5446_pp3_it1) & (ap_ST_pp3_stg7_fsm_20 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp7_it1) & (ap_ST_pp7_stg6_fsm_37 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond12_reg_5924_pp7_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp7_it1) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond12_reg_5924_pp7_it1) & (ap_ST_pp7_stg7_fsm_38 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp3_it2) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond6_reg_5446_pp3_it1) & (ap_ST_pp3_stg0_fsm_13 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp7_it2) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond12_reg_5924_pp7_it1) & (ap_ST_pp7_stg0_fsm_31 == ap_CS_fsm)))) begin
a_d0 = reg_2294;
end else if ((((ap_ST_pp2_stg0_fsm_12 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp2_it6) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond4_reg_5427_pp2_it5)) | ((ap_ST_pp6_stg0_fsm_30 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp6_it6) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond10_reg_5905_pp6_it5)))) begin
a_d0 = reg_2177;
end else begin
a_d0 = reg_2294;
end
end
/// a_d1 assign process. ///
always @ (ap_CS_fsm or ap_reg_ppiten_pp3_it1 or ap_reg_ppiten_pp3_it2 or ap_reg_ppiten_pp7_it1 or ap_reg_ppiten_pp7_it2 or ap_reg_ppstg_exitcond6_reg_5446_pp3_it1 or ap_reg_ppstg_exitcond12_reg_5924_pp7_it1 or ap_reg_ppiten_pp3_it3 or ap_reg_ppiten_pp7_it3 or reg_2305 or reg_2335 or reg_2341 or ap_reg_ppstg_exitcond6_reg_5446_pp3_it2 or ap_reg_ppstg_exitcond12_reg_5924_pp7_it2 or reg_2347)
begin
if ((((ap_ST_pp3_stg0_fsm_13 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp3_it3) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond6_reg_5446_pp3_it2)) | ((ap_ST_pp7_stg0_fsm_31 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp7_it3) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond12_reg_5924_pp7_it2)))) begin
a_d1 = reg_2347;
end else if ((((ap_const_logic_1 == ap_reg_ppiten_pp3_it2) & (ap_ST_pp3_stg7_fsm_20 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond6_reg_5446_pp3_it2)) | ((ap_const_logic_1 == ap_reg_ppiten_pp7_it2) & (ap_ST_pp7_stg7_fsm_38 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond12_reg_5924_pp7_it2)))) begin
a_d1 = reg_2341;
end else if ((((ap_const_logic_1 == ap_reg_ppiten_pp3_it2) & (ap_ST_pp3_stg6_fsm_19 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond6_reg_5446_pp3_it2)) | ((ap_const_logic_1 == ap_reg_ppiten_pp7_it2) & (ap_ST_pp7_stg6_fsm_37 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond12_reg_5924_pp7_it2)))) begin
a_d1 = reg_2335;
end else if ((((ap_const_logic_1 == ap_reg_ppiten_pp3_it1) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond6_reg_5446_pp3_it1) & (ap_ST_pp3_stg5_fsm_18 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp7_it1) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond12_reg_5924_pp7_it1) & (ap_ST_pp7_stg5_fsm_36 == ap_CS_fsm)))) begin
a_d1 = reg_2305;
end else begin
a_d1 = reg_2347;
end
end
/// a_we0 assign process. ///
always @ (ap_CS_fsm or ap_reg_ppiten_pp3_it1 or ap_reg_ppiten_pp3_it2 or ap_reg_ppiten_pp7_it1 or ap_reg_ppiten_pp7_it2 or ap_reg_ppiten_pp2_it6 or ap_reg_ppiten_pp6_it6 or ap_reg_ppstg_exitcond6_reg_5446_pp3_it1 or ap_reg_ppstg_exitcond12_reg_5924_pp7_it1 or ap_reg_ppstg_exitcond4_reg_5427_pp2_it5 or ap_reg_ppstg_exitcond10_reg_5905_pp6_it5)
begin
if ((((ap_const_logic_1 == ap_reg_ppiten_pp3_it1) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond6_reg_5446_pp3_it1) & (ap_ST_pp3_stg5_fsm_18 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp7_it1) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond12_reg_5924_pp7_it1) & (ap_ST_pp7_stg5_fsm_36 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp3_it1) & (ap_ST_pp3_stg6_fsm_19 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond6_reg_5446_pp3_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp3_it1) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond6_reg_5446_pp3_it1) & (ap_ST_pp3_stg7_fsm_20 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp7_it1) & (ap_ST_pp7_stg6_fsm_37 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond12_reg_5924_pp7_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp7_it1) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond12_reg_5924_pp7_it1) & (ap_ST_pp7_stg7_fsm_38 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp3_it2) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond6_reg_5446_pp3_it1) & (ap_ST_pp3_stg0_fsm_13 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp7_it2) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond12_reg_5924_pp7_it1) & (ap_ST_pp7_stg0_fsm_31 == ap_CS_fsm)) | ((ap_ST_pp2_stg0_fsm_12 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp2_it6) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond4_reg_5427_pp2_it5)) | ((ap_ST_pp6_stg0_fsm_30 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp6_it6) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond10_reg_5905_pp6_it5)))) begin
a_we0 = ap_const_logic_1;
end else begin
a_we0 = ap_const_logic_0;
end
end
/// a_we1 assign process. ///
always @ (ap_CS_fsm or ap_reg_ppiten_pp3_it1 or ap_reg_ppiten_pp3_it2 or ap_reg_ppiten_pp7_it1 or ap_reg_ppiten_pp7_it2 or ap_reg_ppstg_exitcond6_reg_5446_pp3_it1 or ap_reg_ppstg_exitcond12_reg_5924_pp7_it1 or ap_reg_ppiten_pp3_it3 or ap_reg_ppiten_pp7_it3 or ap_reg_ppstg_exitcond6_reg_5446_pp3_it2 or ap_reg_ppstg_exitcond12_reg_5924_pp7_it2)
begin
if ((((ap_const_logic_1 == ap_reg_ppiten_pp3_it1) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond6_reg_5446_pp3_it1) & (ap_ST_pp3_stg5_fsm_18 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp7_it1) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond12_reg_5924_pp7_it1) & (ap_ST_pp7_stg5_fsm_36 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp3_it2) & (ap_ST_pp3_stg6_fsm_19 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond6_reg_5446_pp3_it2)) | ((ap_const_logic_1 == ap_reg_ppiten_pp3_it2) & (ap_ST_pp3_stg7_fsm_20 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond6_reg_5446_pp3_it2)) | ((ap_ST_pp3_stg0_fsm_13 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp3_it3) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond6_reg_5446_pp3_it2)) | ((ap_const_logic_1 == ap_reg_ppiten_pp7_it2) & (ap_ST_pp7_stg6_fsm_37 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond12_reg_5924_pp7_it2)) | ((ap_const_logic_1 == ap_reg_ppiten_pp7_it2) & (ap_ST_pp7_stg7_fsm_38 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond12_reg_5924_pp7_it2)) | ((ap_ST_pp7_stg0_fsm_31 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp7_it3) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond12_reg_5924_pp7_it2)))) begin
a_we1 = ap_const_logic_1;
end else begin
a_we1 = ap_const_logic_0;
end
end
/// ap_NS_fsm assign process. ///
always @ (ap_start or ap_CS_fsm or ap_reg_ppiten_pp0_it1 or ap_reg_ppiten_pp0_it0 or ap_reg_ppiten_pp0_it5 or ap_reg_ppiten_pp0_it6 or ap_reg_ppiten_pp1_it0 or ap_reg_ppiten_pp1_it1 or ap_reg_ppiten_pp1_it2 or ap_reg_ppiten_pp3_it0 or ap_reg_ppiten_pp3_it1 or ap_reg_ppiten_pp3_it2 or ap_reg_ppiten_pp4_it1 or ap_reg_ppiten_pp4_it0 or ap_reg_ppiten_pp4_it5 or ap_reg_ppiten_pp4_it6 or ap_reg_ppiten_pp5_it0 or ap_reg_ppiten_pp5_it1 or ap_reg_ppiten_pp5_it2 or ap_reg_ppiten_pp7_it0 or ap_reg_ppiten_pp7_it1 or ap_reg_ppiten_pp7_it2 or ap_reg_ppiten_pp2_it5 or ap_reg_ppiten_pp2_it0 or ap_reg_ppiten_pp2_it1 or ap_reg_ppiten_pp2_it6 or ap_reg_ppiten_pp6_it5 or ap_reg_ppiten_pp6_it0 or ap_reg_ppiten_pp6_it1 or ap_reg_ppiten_pp6_it6 or ap_reg_ppiten_pp1_it3 or ap_reg_ppiten_pp3_it3 or ap_reg_ppiten_pp5_it3 or ap_reg_ppiten_pp7_it3 or or_cond_fu_2365_p2 or tmp_2_fu_2371_p2 or exitcond1_fu_2377_p2 or exitcond3_fu_2404_p2 or exitcond4_fu_2988_p2 or exitcond6_fu_3025_p2 or exitcond7_fu_3609_p2 or exitcond9_fu_3626_p2 or exitcond10_fu_3978_p2 or exitcond12_fu_4005_p2 or exitcond_fu_4357_p2 or ap_reg_ppiten_pp8_it0)
begin
if ((ap_ST_pp8_stg27_fsm_67 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_pp8_stg28_fsm_68;
end else if ((ap_ST_pp8_stg26_fsm_66 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_pp8_stg27_fsm_67;
end else if ((ap_ST_pp8_stg25_fsm_65 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_pp8_stg26_fsm_66;
end else if ((ap_ST_pp8_stg24_fsm_64 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_pp8_stg25_fsm_65;
end else if ((ap_ST_pp8_stg23_fsm_63 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_pp8_stg24_fsm_64;
end else if ((ap_ST_pp8_stg22_fsm_62 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_pp8_stg23_fsm_63;
end else if ((ap_ST_pp8_stg21_fsm_61 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_pp8_stg22_fsm_62;
end else if ((ap_ST_pp8_stg20_fsm_60 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_pp8_stg21_fsm_61;
end else if ((ap_ST_pp8_stg19_fsm_59 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_pp8_stg20_fsm_60;
end else if ((ap_ST_pp8_stg18_fsm_58 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_pp8_stg19_fsm_59;
end else if ((ap_ST_pp8_stg17_fsm_57 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_pp8_stg18_fsm_58;
end else if ((ap_ST_pp8_stg16_fsm_56 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_pp8_stg17_fsm_57;
end else if ((ap_ST_pp8_stg15_fsm_55 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_pp8_stg16_fsm_56;
end else if ((ap_ST_pp8_stg14_fsm_54 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_pp8_stg15_fsm_55;
end else if ((ap_ST_pp8_stg13_fsm_53 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_pp8_stg14_fsm_54;
end else if ((ap_ST_pp8_stg12_fsm_52 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_pp8_stg13_fsm_53;
end else if ((ap_ST_pp8_stg11_fsm_51 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_pp8_stg12_fsm_52;
end else if ((ap_ST_pp8_stg10_fsm_50 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_pp8_stg11_fsm_51;
end else if ((ap_ST_pp8_stg9_fsm_49 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_pp8_stg10_fsm_50;
end else if ((ap_ST_pp8_stg8_fsm_48 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_pp8_stg9_fsm_49;
end else if ((ap_ST_pp8_stg7_fsm_47 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_pp8_stg8_fsm_48;
end else if ((ap_ST_pp8_stg6_fsm_46 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_pp8_stg7_fsm_47;
end else if ((ap_ST_pp8_stg5_fsm_45 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_pp8_stg6_fsm_46;
end else if ((ap_ST_pp8_stg4_fsm_44 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_pp8_stg5_fsm_45;
end else if ((ap_ST_pp8_stg3_fsm_43 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_pp8_stg4_fsm_44;
end else if ((ap_ST_pp8_stg2_fsm_42 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_pp8_stg3_fsm_43;
end else if ((ap_ST_pp8_stg1_fsm_41 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_pp8_stg2_fsm_42;
end else if (((ap_ST_pp8_stg0_fsm_40 == ap_CS_fsm) & ~((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & ~(ap_const_lv1_0 == exitcond_fu_4357_p2)))) begin
ap_NS_fsm = ap_ST_pp8_stg1_fsm_41;
end else if ((ap_ST_pp7_stg6_fsm_37 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_pp7_stg7_fsm_38;
end else if ((ap_ST_pp7_stg5_fsm_36 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_pp7_stg6_fsm_37;
end else if ((ap_ST_pp7_stg4_fsm_35 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_pp7_stg5_fsm_36;
end else if ((ap_ST_pp7_stg3_fsm_34 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_pp7_stg4_fsm_35;
end else if ((ap_ST_pp7_stg2_fsm_33 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_pp7_stg3_fsm_34;
end else if ((ap_ST_pp7_stg1_fsm_32 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_pp7_stg2_fsm_33;
end else if (((ap_ST_pp7_stg0_fsm_31 == ap_CS_fsm) & ~((ap_ST_pp7_stg0_fsm_31 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp7_it3) & ~(ap_const_logic_1 == ap_reg_ppiten_pp7_it2)) & ~((ap_const_logic_1 == ap_reg_ppiten_pp7_it0) & ~(ap_const_lv1_0 == exitcond12_fu_4005_p2) & ~(ap_const_logic_1 == ap_reg_ppiten_pp7_it1)))) begin
ap_NS_fsm = ap_ST_pp7_stg1_fsm_32;
end else if ((((ap_ST_pp7_stg0_fsm_31 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp7_it3) & ~(ap_const_logic_1 == ap_reg_ppiten_pp7_it2)) | ((ap_const_logic_1 == ap_reg_ppiten_pp7_it0) & (ap_ST_pp7_stg0_fsm_31 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond12_fu_4005_p2) & ~(ap_const_logic_1 == ap_reg_ppiten_pp7_it1)))) begin
ap_NS_fsm = ap_ST_st131_fsm_39;
end else if (((ap_ST_pp7_stg7_fsm_38 == ap_CS_fsm) | ((ap_ST_pp6_stg0_fsm_30 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp6_it6) & ~(ap_const_logic_1 == ap_reg_ppiten_pp6_it5)) | ((ap_ST_pp6_stg0_fsm_30 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp6_it0) & ~(ap_const_lv1_0 == exitcond10_fu_3978_p2) & ~(ap_const_logic_1 == ap_reg_ppiten_pp6_it1)))) begin
ap_NS_fsm = ap_ST_pp7_stg0_fsm_31;
end else if ((ap_ST_pp5_stg6_fsm_28 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_pp5_stg7_fsm_29;
end else if ((ap_ST_pp5_stg5_fsm_27 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_pp5_stg6_fsm_28;
end else if ((ap_ST_pp5_stg4_fsm_26 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_pp5_stg5_fsm_27;
end else if ((ap_ST_pp5_stg3_fsm_25 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_pp5_stg4_fsm_26;
end else if ((ap_ST_pp5_stg2_fsm_24 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_pp5_stg3_fsm_25;
end else if ((ap_ST_pp5_stg1_fsm_23 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_pp5_stg2_fsm_24;
end else if (((ap_ST_pp5_stg0_fsm_22 == ap_CS_fsm) & ~((ap_ST_pp5_stg0_fsm_22 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp5_it3) & ~(ap_const_logic_1 == ap_reg_ppiten_pp5_it2)) & ~((ap_const_logic_1 == ap_reg_ppiten_pp5_it0) & ~(ap_const_lv1_0 == exitcond9_fu_3626_p2) & ~(ap_const_logic_1 == ap_reg_ppiten_pp5_it1)))) begin
ap_NS_fsm = ap_ST_pp5_stg1_fsm_23;
end else if ((((ap_ST_pp5_stg0_fsm_22 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp5_it3) & ~(ap_const_logic_1 == ap_reg_ppiten_pp5_it2)) | ((ap_const_logic_1 == ap_reg_ppiten_pp5_it0) & (ap_ST_pp5_stg0_fsm_22 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond9_fu_3626_p2) & ~(ap_const_logic_1 == ap_reg_ppiten_pp5_it1)))) begin
ap_NS_fsm = ap_ST_pp6_stg0_fsm_30;
end else if (((ap_ST_pp5_stg7_fsm_29 == ap_CS_fsm) | ((ap_ST_pp4_stg0_fsm_21 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp4_it6) & ~(ap_const_logic_1 == ap_reg_ppiten_pp4_it5)) | ((ap_ST_pp4_stg0_fsm_21 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp4_it0) & ~(ap_const_lv1_0 == exitcond7_fu_3609_p2) & ~(ap_const_logic_1 == ap_reg_ppiten_pp4_it1)))) begin
ap_NS_fsm = ap_ST_pp5_stg0_fsm_22;
end else if ((ap_ST_pp3_stg6_fsm_19 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_pp3_stg7_fsm_20;
end else if ((ap_ST_pp3_stg5_fsm_18 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_pp3_stg6_fsm_19;
end else if ((ap_ST_pp3_stg4_fsm_17 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_pp3_stg5_fsm_18;
end else if ((ap_ST_pp3_stg3_fsm_16 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_pp3_stg4_fsm_17;
end else if ((ap_ST_pp3_stg2_fsm_15 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_pp3_stg3_fsm_16;
end else if ((ap_ST_pp3_stg1_fsm_14 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_pp3_stg2_fsm_15;
end else if (((ap_ST_pp3_stg0_fsm_13 == ap_CS_fsm) & ~((ap_ST_pp3_stg0_fsm_13 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp3_it3) & ~(ap_const_logic_1 == ap_reg_ppiten_pp3_it2)) & ~((ap_const_logic_1 == ap_reg_ppiten_pp3_it0) & ~(ap_const_lv1_0 == exitcond6_fu_3025_p2) & ~(ap_const_logic_1 == ap_reg_ppiten_pp3_it1)))) begin
ap_NS_fsm = ap_ST_pp3_stg1_fsm_14;
end else if ((((ap_ST_pp3_stg0_fsm_13 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp3_it3) & ~(ap_const_logic_1 == ap_reg_ppiten_pp3_it2)) | ((ap_const_logic_1 == ap_reg_ppiten_pp3_it0) & (ap_ST_pp3_stg0_fsm_13 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond6_fu_3025_p2) & ~(ap_const_logic_1 == ap_reg_ppiten_pp3_it1)))) begin
ap_NS_fsm = ap_ST_pp4_stg0_fsm_21;
end else if (((ap_ST_pp3_stg7_fsm_20 == ap_CS_fsm) | ((ap_ST_pp2_stg0_fsm_12 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp2_it6) & ~(ap_const_logic_1 == ap_reg_ppiten_pp2_it5)) | ((ap_ST_pp2_stg0_fsm_12 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp2_it0) & ~(ap_const_lv1_0 == exitcond4_fu_2988_p2) & ~(ap_const_logic_1 == ap_reg_ppiten_pp2_it1)))) begin
ap_NS_fsm = ap_ST_pp3_stg0_fsm_13;
end else if ((ap_ST_pp1_stg6_fsm_10 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_pp1_stg7_fsm_11;
end else if ((ap_ST_pp1_stg5_fsm_9 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_pp1_stg6_fsm_10;
end else if ((ap_ST_pp1_stg4_fsm_8 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_pp1_stg5_fsm_9;
end else if ((ap_ST_pp1_stg3_fsm_7 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_pp1_stg4_fsm_8;
end else if ((ap_ST_pp1_stg2_fsm_6 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_pp1_stg3_fsm_7;
end else if ((ap_ST_pp1_stg1_fsm_5 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_pp1_stg2_fsm_6;
end else if (((ap_ST_pp1_stg0_fsm_4 == ap_CS_fsm) & ~((ap_ST_pp1_stg0_fsm_4 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it3) & ~(ap_const_logic_1 == ap_reg_ppiten_pp1_it2)) & ~((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & ~(ap_const_lv1_0 == exitcond3_fu_2404_p2) & ~(ap_const_logic_1 == ap_reg_ppiten_pp1_it1)))) begin
ap_NS_fsm = ap_ST_pp1_stg1_fsm_5;
end else if ((((ap_ST_pp1_stg0_fsm_4 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it3) & ~(ap_const_logic_1 == ap_reg_ppiten_pp1_it2)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_ST_pp1_stg0_fsm_4 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond3_fu_2404_p2) & ~(ap_const_logic_1 == ap_reg_ppiten_pp1_it1)))) begin
ap_NS_fsm = ap_ST_pp2_stg0_fsm_12;
end else if ((((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6) & ~(ap_const_logic_1 == ap_reg_ppiten_pp0_it5)) | ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ~(ap_const_lv1_0 == exitcond1_fu_2377_p2) & ~(ap_const_logic_1 == ap_reg_ppiten_pp0_it1)))) begin
ap_NS_fsm = ap_ST_st9_fsm_3;
end else if ((~(ap_const_logic_1 == ap_start) & (ap_ST_st162_fsm_69 == ap_CS_fsm))) begin
ap_NS_fsm = ap_ST_st0_fsm_0;
end else if (((ap_ST_pp1_stg7_fsm_11 == ap_CS_fsm) | (ap_ST_st9_fsm_3 == ap_CS_fsm))) begin
ap_NS_fsm = ap_ST_pp1_stg0_fsm_4;
end else if (((ap_ST_st1_fsm_1 == ap_CS_fsm) & ~(ap_const_lv1_0 == or_cond_fu_2365_p2) & ~(ap_const_lv1_0 == tmp_2_fu_2371_p2))) begin
ap_NS_fsm = ap_ST_pp0_stg0_fsm_2;
end else if (((ap_ST_pp8_stg28_fsm_68 == ap_CS_fsm) | ((ap_ST_st1_fsm_1 == ap_CS_fsm) & ~(ap_const_lv1_0 == or_cond_fu_2365_p2) & (ap_const_lv1_0 == tmp_2_fu_2371_p2)) | (ap_ST_st131_fsm_39 == ap_CS_fsm))) begin
ap_NS_fsm = ap_ST_pp8_stg0_fsm_40;
end else if ((((ap_ST_st1_fsm_1 == ap_CS_fsm) & (ap_const_lv1_0 == or_cond_fu_2365_p2)) | ((ap_ST_pp8_stg0_fsm_40 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & ~(ap_const_lv1_0 == exitcond_fu_4357_p2)))) begin
ap_NS_fsm = ap_ST_st162_fsm_69;
end else if ((((ap_ST_st0_fsm_0 == ap_CS_fsm) & (ap_const_logic_1 == ap_start)) | ((ap_const_logic_1 == ap_start) & (ap_ST_st162_fsm_69 == ap_CS_fsm)))) begin
ap_NS_fsm = ap_ST_st1_fsm_1;
end else begin
ap_NS_fsm = ap_CS_fsm;
end
end
/// ap_done assign process. ///
always @ (ap_CS_fsm)
begin
if (((ap_ST_st0_fsm_0 == ap_CS_fsm) | (ap_ST_st162_fsm_69 == ap_CS_fsm))) begin
ap_done = ap_const_logic_1;
end else begin
ap_done = ap_const_logic_0;
end
end
/// ap_idle assign process. ///
always @ (ap_CS_fsm)
begin
if ((ap_ST_st0_fsm_0 == ap_CS_fsm)) begin
ap_idle = ap_const_logic_1;
end else begin
ap_idle = ap_const_logic_0;
end
end
/// b_address0 assign process. ///
always @ (ap_CS_fsm or ap_reg_ppiten_pp0_it6 or ap_reg_ppiten_pp1_it0 or ap_reg_ppiten_pp1_it1 or ap_reg_ppiten_pp1_it2 or exitcond3_reg_5195 or ap_reg_ppiten_pp3_it0 or ap_reg_ppiten_pp3_it1 or exitcond6_reg_5446 or ap_reg_ppiten_pp4_it6 or ap_reg_ppiten_pp5_it0 or ap_reg_ppiten_pp5_it1 or ap_reg_ppiten_pp5_it2 or exitcond9_reg_5697 or ap_reg_ppiten_pp7_it0 or ap_reg_ppiten_pp7_it1 or exitcond12_reg_5924 or ap_reg_ppiten_pp2_it0 or ap_reg_ppiten_pp6_it0 or ap_reg_ppstg_exitcond6_reg_5446_pp3_it1 or ap_reg_ppstg_exitcond12_reg_5924_pp7_it1 or ap_reg_ppstg_exitcond3_reg_5195_pp1_it1 or ap_reg_ppstg_exitcond9_reg_5697_pp5_it1 or ap_reg_ppstg_exitcond1_reg_5171_pp0_it5 or ap_reg_ppstg_tmp_6_reg_5180_pp0_it5 or ap_reg_ppstg_tmp_9_reg_5237_pp1_it1 or ap_reg_ppstg_tmp_20_reg_5287_pp1_it1 or ap_reg_ppstg_tmp_28_reg_5332_pp1_it1 or ap_reg_ppstg_tmp_36_reg_5347_pp1_it1 or exitcond4_fu_2988_p2 or tmp_59_fu_3020_p1 or exitcond6_fu_3025_p2 or tmp_67_fu_3093_p1 or tmp_75_fu_3181_p1 or tmp_86_fu_3361_p1 or tmp_98_fu_3468_p1 or tmp_114_fu_3605_p1 or ap_reg_ppstg_exitcond7_reg_5678_pp4_it5 or ap_reg_ppstg_tmp_122_reg_5687_pp4_it5 or ap_reg_ppstg_tmp_125_reg_5740_pp5_it1 or ap_reg_ppstg_tmp_138_reg_5790_pp5_it1 or ap_reg_ppstg_tmp_146_reg_5805_pp5_it1 or ap_reg_ppstg_tmp_154_reg_5825_pp5_it1 or exitcond10_fu_3978_p2 or tmp_172_fu_4000_p1 or exitcond12_fu_4005_p2 or tmp_174_fu_4073_p1 or tmp_178_fu_4143_p1 or tmp_186_fu_4209_p1 or tmp_192_fu_4274_p1 or tmp_197_fu_4353_p1 or exitcond_reg_6132 or ap_reg_ppiten_pp8_it0 or ap_reg_ppiten_pp8_it1 or tmp_199_reg_6176 or tmp_200_reg_6202 or tmp_202_reg_6244 or tmp_204_reg_6286 or tmp_206_reg_6328 or tmp_208_reg_6363 or tmp_210_reg_6383 or tmp_212_reg_6403 or tmp_214_reg_6432 or tmp_216_reg_6452 or tmp_218_reg_6472 or tmp_220_reg_6492 or tmp_222_reg_6522 or tmp_224_reg_6542 or tmp_226_reg_6562 or tmp_228_reg_6591 or tmp_230_reg_6611 or tmp_232_reg_6631 or tmp_234_reg_6651 or tmp_236_reg_6681 or tmp_238_reg_6701 or tmp_240_reg_6721 or tmp_242_reg_6750 or tmp_244_reg_6770 or tmp_246_reg_6790 or tmp_248_reg_6850 or tmp_250_reg_6870 or tmp_252_reg_6890 or tmp_254_reg_6910 or tmp_11_fu_2531_p1 or tmp_24_fu_2711_p1 or tmp_40_fu_2818_p1 or tmp_50_fu_2921_p1 or tmp_126_fu_3741_p1 or tmp_142_fu_3807_p1 or tmp_158_fu_3872_p1 or tmp_166_fu_3924_p1)
begin
if (((ap_ST_pp8_stg0_fsm_40 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp8_it1) & (ap_const_lv1_0 == exitcond_reg_6132))) begin
b_address0 = tmp_254_reg_6910;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg28_fsm_68 == ap_CS_fsm))) begin
b_address0 = tmp_252_reg_6890;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg27_fsm_67 == ap_CS_fsm))) begin
b_address0 = tmp_250_reg_6870;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg26_fsm_66 == ap_CS_fsm))) begin
b_address0 = tmp_248_reg_6850;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg25_fsm_65 == ap_CS_fsm))) begin
b_address0 = tmp_246_reg_6790;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg24_fsm_64 == ap_CS_fsm))) begin
b_address0 = tmp_244_reg_6770;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg23_fsm_63 == ap_CS_fsm))) begin
b_address0 = tmp_242_reg_6750;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg22_fsm_62 == ap_CS_fsm))) begin
b_address0 = tmp_240_reg_6721;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg21_fsm_61 == ap_CS_fsm))) begin
b_address0 = tmp_238_reg_6701;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg20_fsm_60 == ap_CS_fsm))) begin
b_address0 = tmp_236_reg_6681;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg19_fsm_59 == ap_CS_fsm))) begin
b_address0 = tmp_234_reg_6651;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg18_fsm_58 == ap_CS_fsm))) begin
b_address0 = tmp_232_reg_6631;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg17_fsm_57 == ap_CS_fsm))) begin
b_address0 = tmp_230_reg_6611;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg16_fsm_56 == ap_CS_fsm))) begin
b_address0 = tmp_228_reg_6591;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg15_fsm_55 == ap_CS_fsm))) begin
b_address0 = tmp_226_reg_6562;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg14_fsm_54 == ap_CS_fsm))) begin
b_address0 = tmp_224_reg_6542;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg13_fsm_53 == ap_CS_fsm))) begin
b_address0 = tmp_222_reg_6522;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg12_fsm_52 == ap_CS_fsm))) begin
b_address0 = tmp_220_reg_6492;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg11_fsm_51 == ap_CS_fsm))) begin
b_address0 = tmp_218_reg_6472;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg10_fsm_50 == ap_CS_fsm))) begin
b_address0 = tmp_216_reg_6452;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg9_fsm_49 == ap_CS_fsm))) begin
b_address0 = tmp_214_reg_6432;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg8_fsm_48 == ap_CS_fsm))) begin
b_address0 = tmp_212_reg_6403;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg7_fsm_47 == ap_CS_fsm))) begin
b_address0 = tmp_210_reg_6383;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg6_fsm_46 == ap_CS_fsm))) begin
b_address0 = tmp_208_reg_6363;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg5_fsm_45 == ap_CS_fsm))) begin
b_address0 = tmp_206_reg_6328;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg4_fsm_44 == ap_CS_fsm))) begin
b_address0 = tmp_204_reg_6286;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg3_fsm_43 == ap_CS_fsm))) begin
b_address0 = tmp_202_reg_6244;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg2_fsm_42 == ap_CS_fsm))) begin
b_address0 = tmp_200_reg_6202;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_ST_pp8_stg1_fsm_41 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond_reg_6132))) begin
b_address0 = tmp_199_reg_6176;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp5_it2) & (ap_ST_pp5_stg0_fsm_22 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond9_reg_5697_pp5_it1))) begin
b_address0 = ap_reg_ppstg_tmp_154_reg_5825_pp5_it1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp5_it1) & (ap_ST_pp5_stg7_fsm_29 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond9_reg_5697_pp5_it1))) begin
b_address0 = ap_reg_ppstg_tmp_146_reg_5805_pp5_it1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp5_it1) & (ap_ST_pp5_stg6_fsm_28 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond9_reg_5697_pp5_it1))) begin
b_address0 = ap_reg_ppstg_tmp_138_reg_5790_pp5_it1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp5_it1) & (ap_ST_pp5_stg5_fsm_27 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond9_reg_5697_pp5_it1))) begin
b_address0 = ap_reg_ppstg_tmp_125_reg_5740_pp5_it1;
end else if (((ap_ST_pp4_stg0_fsm_21 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp4_it6) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond7_reg_5678_pp4_it5))) begin
b_address0 = ap_reg_ppstg_tmp_122_reg_5687_pp4_it5;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it2) & (ap_ST_pp1_stg0_fsm_4 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond3_reg_5195_pp1_it1))) begin
b_address0 = ap_reg_ppstg_tmp_36_reg_5347_pp1_it1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_ST_pp1_stg7_fsm_11 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond3_reg_5195_pp1_it1))) begin
b_address0 = ap_reg_ppstg_tmp_28_reg_5332_pp1_it1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_ST_pp1_stg6_fsm_10 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond3_reg_5195_pp1_it1))) begin
b_address0 = ap_reg_ppstg_tmp_20_reg_5287_pp1_it1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_ST_pp1_stg5_fsm_9 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond3_reg_5195_pp1_it1))) begin
b_address0 = ap_reg_ppstg_tmp_9_reg_5237_pp1_it1;
end else if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond1_reg_5171_pp0_it5))) begin
b_address0 = ap_reg_ppstg_tmp_6_reg_5180_pp0_it5;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp7_it1) & (ap_ST_pp7_stg4_fsm_35 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond12_reg_5924_pp7_it1))) begin
b_address0 = tmp_197_fu_4353_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp7_it0) & (ap_const_lv1_0 == exitcond12_reg_5924) & (ap_ST_pp7_stg3_fsm_34 == ap_CS_fsm))) begin
b_address0 = tmp_192_fu_4274_p1;
end else if (((ap_ST_pp7_stg2_fsm_33 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp7_it0) & (ap_const_lv1_0 == exitcond12_reg_5924))) begin
b_address0 = tmp_186_fu_4209_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp7_it0) & (ap_const_lv1_0 == exitcond12_reg_5924) & (ap_ST_pp7_stg1_fsm_32 == ap_CS_fsm))) begin
b_address0 = tmp_178_fu_4143_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp7_it0) & (ap_ST_pp7_stg0_fsm_31 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond12_fu_4005_p2))) begin
b_address0 = tmp_174_fu_4073_p1;
end else if (((ap_ST_pp6_stg0_fsm_30 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp6_it0) & (ap_const_lv1_0 == exitcond10_fu_3978_p2))) begin
b_address0 = tmp_172_fu_4000_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp5_it0) & (ap_const_lv1_0 == exitcond9_reg_5697) & (ap_ST_pp5_stg4_fsm_26 == ap_CS_fsm))) begin
b_address0 = tmp_166_fu_3924_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp5_it0) & (ap_const_lv1_0 == exitcond9_reg_5697) & (ap_ST_pp5_stg3_fsm_25 == ap_CS_fsm))) begin
b_address0 = tmp_158_fu_3872_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp5_it0) & (ap_const_lv1_0 == exitcond9_reg_5697) & (ap_ST_pp5_stg2_fsm_24 == ap_CS_fsm))) begin
b_address0 = tmp_142_fu_3807_p1;
end else if (((ap_ST_pp5_stg1_fsm_23 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp5_it0) & (ap_const_lv1_0 == exitcond9_reg_5697))) begin
b_address0 = tmp_126_fu_3741_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp3_it1) & (ap_ST_pp3_stg4_fsm_17 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond6_reg_5446_pp3_it1))) begin
b_address0 = tmp_114_fu_3605_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp3_it0) & (ap_const_lv1_0 == exitcond6_reg_5446) & (ap_ST_pp3_stg3_fsm_16 == ap_CS_fsm))) begin
b_address0 = tmp_98_fu_3468_p1;
end else if (((ap_ST_pp3_stg2_fsm_15 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp3_it0) & (ap_const_lv1_0 == exitcond6_reg_5446))) begin
b_address0 = tmp_86_fu_3361_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp3_it0) & (ap_const_lv1_0 == exitcond6_reg_5446) & (ap_ST_pp3_stg1_fsm_14 == ap_CS_fsm))) begin
b_address0 = tmp_75_fu_3181_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp3_it0) & (ap_ST_pp3_stg0_fsm_13 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond6_fu_3025_p2))) begin
b_address0 = tmp_67_fu_3093_p1;
end else if (((ap_ST_pp2_stg0_fsm_12 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp2_it0) & (ap_const_lv1_0 == exitcond4_fu_2988_p2))) begin
b_address0 = tmp_59_fu_3020_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond3_reg_5195) & (ap_ST_pp1_stg4_fsm_8 == ap_CS_fsm))) begin
b_address0 = tmp_50_fu_2921_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond3_reg_5195) & (ap_ST_pp1_stg3_fsm_7 == ap_CS_fsm))) begin
b_address0 = tmp_40_fu_2818_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond3_reg_5195) & (ap_ST_pp1_stg2_fsm_6 == ap_CS_fsm))) begin
b_address0 = tmp_24_fu_2711_p1;
end else if (((ap_ST_pp1_stg1_fsm_5 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond3_reg_5195))) begin
b_address0 = tmp_11_fu_2531_p1;
end else begin
b_address0 = tmp_254_reg_6910;
end
end
/// b_address1 assign process. ///
always @ (ap_CS_fsm or ap_reg_ppiten_pp1_it0 or ap_reg_ppiten_pp1_it1 or ap_reg_ppiten_pp1_it2 or exitcond3_reg_5195 or ap_reg_ppiten_pp3_it0 or ap_reg_ppiten_pp3_it1 or exitcond6_reg_5446 or ap_reg_ppiten_pp5_it0 or ap_reg_ppiten_pp5_it1 or ap_reg_ppiten_pp5_it2 or exitcond9_reg_5697 or ap_reg_ppiten_pp7_it0 or ap_reg_ppiten_pp7_it1 or exitcond12_reg_5924 or ap_reg_ppstg_exitcond6_reg_5446_pp3_it1 or ap_reg_ppstg_exitcond12_reg_5924_pp7_it1 or ap_reg_ppiten_pp1_it3 or ap_reg_ppiten_pp5_it3 or ap_reg_ppstg_exitcond3_reg_5195_pp1_it1 or ap_reg_ppstg_exitcond9_reg_5697_pp5_it1 or ap_reg_ppstg_exitcond3_reg_5195_pp1_it2 or ap_reg_ppstg_exitcond9_reg_5697_pp5_it2 or ap_reg_ppstg_tmp_15_reg_5272_pp1_it1 or ap_reg_ppstg_tmp_44_reg_5367_pp1_it2 or ap_reg_ppstg_tmp_47_reg_5407_pp1_it2 or ap_reg_ppstg_tmp_51_reg_5417_pp1_it2 or tmp_83_fu_3247_p1 or tmp_90_fu_3415_p1 or tmp_106_fu_3601_p1 or ap_reg_ppstg_tmp_130_reg_5770_pp5_it1 or ap_reg_ppstg_tmp_160_reg_5840_pp5_it2 or ap_reg_ppstg_tmp_164_reg_5880_pp5_it2 or ap_reg_ppstg_tmp_168_reg_5895_pp5_it2 or tmp_182_fu_4173_p1 or tmp_190_fu_4238_p1 or tmp_194_fu_4340_p1 or exitcond_reg_6132 or ap_reg_ppiten_pp8_it0 or ap_reg_ppiten_pp8_it1 or tmp_201_reg_6223 or tmp_203_reg_6265 or tmp_205_reg_6307 or tmp_207_reg_6348 or tmp_209_reg_6373 or tmp_211_reg_6393 or tmp_213_reg_6413 or tmp_215_reg_6442 or tmp_217_reg_6462 or tmp_219_reg_6482 or tmp_221_reg_6512 or tmp_223_reg_6532 or tmp_225_reg_6552 or tmp_227_reg_6572 or tmp_229_reg_6601 or tmp_231_reg_6621 or tmp_233_reg_6641 or tmp_235_reg_6671 or tmp_237_reg_6691 or tmp_239_reg_6711 or tmp_241_reg_6731 or tmp_243_reg_6760 or tmp_245_reg_6780 or tmp_247_reg_6800 or tmp_249_reg_6860 or tmp_251_reg_6880 or tmp_253_reg_6900 or tmp_255_reg_6920 or tmp_16_fu_2597_p1 or tmp_32_fu_2765_p1 or tmp_46_fu_2872_p1 or tmp_55_fu_2970_p1 or tmp_134_fu_3775_p1 or tmp_150_fu_3840_p1 or tmp_162_fu_3905_p1 or tmp_170_fu_3943_p1)
begin
if (((ap_ST_pp8_stg0_fsm_40 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp8_it1) & (ap_const_lv1_0 == exitcond_reg_6132))) begin
b_address1 = tmp_255_reg_6920;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg28_fsm_68 == ap_CS_fsm))) begin
b_address1 = tmp_253_reg_6900;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg27_fsm_67 == ap_CS_fsm))) begin
b_address1 = tmp_251_reg_6880;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg26_fsm_66 == ap_CS_fsm))) begin
b_address1 = tmp_249_reg_6860;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg25_fsm_65 == ap_CS_fsm))) begin
b_address1 = tmp_247_reg_6800;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg24_fsm_64 == ap_CS_fsm))) begin
b_address1 = tmp_245_reg_6780;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg23_fsm_63 == ap_CS_fsm))) begin
b_address1 = tmp_243_reg_6760;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg22_fsm_62 == ap_CS_fsm))) begin
b_address1 = tmp_241_reg_6731;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg21_fsm_61 == ap_CS_fsm))) begin
b_address1 = tmp_239_reg_6711;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg20_fsm_60 == ap_CS_fsm))) begin
b_address1 = tmp_237_reg_6691;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg19_fsm_59 == ap_CS_fsm))) begin
b_address1 = tmp_235_reg_6671;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg18_fsm_58 == ap_CS_fsm))) begin
b_address1 = tmp_233_reg_6641;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg17_fsm_57 == ap_CS_fsm))) begin
b_address1 = tmp_231_reg_6621;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg16_fsm_56 == ap_CS_fsm))) begin
b_address1 = tmp_229_reg_6601;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg15_fsm_55 == ap_CS_fsm))) begin
b_address1 = tmp_227_reg_6572;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg14_fsm_54 == ap_CS_fsm))) begin
b_address1 = tmp_225_reg_6552;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg13_fsm_53 == ap_CS_fsm))) begin
b_address1 = tmp_223_reg_6532;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg12_fsm_52 == ap_CS_fsm))) begin
b_address1 = tmp_221_reg_6512;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg11_fsm_51 == ap_CS_fsm))) begin
b_address1 = tmp_219_reg_6482;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg10_fsm_50 == ap_CS_fsm))) begin
b_address1 = tmp_217_reg_6462;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg9_fsm_49 == ap_CS_fsm))) begin
b_address1 = tmp_215_reg_6442;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg8_fsm_48 == ap_CS_fsm))) begin
b_address1 = tmp_213_reg_6413;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg7_fsm_47 == ap_CS_fsm))) begin
b_address1 = tmp_211_reg_6393;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg6_fsm_46 == ap_CS_fsm))) begin
b_address1 = tmp_209_reg_6373;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg5_fsm_45 == ap_CS_fsm))) begin
b_address1 = tmp_207_reg_6348;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg4_fsm_44 == ap_CS_fsm))) begin
b_address1 = tmp_205_reg_6307;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg3_fsm_43 == ap_CS_fsm))) begin
b_address1 = tmp_203_reg_6265;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg2_fsm_42 == ap_CS_fsm))) begin
b_address1 = tmp_201_reg_6223;
end else if (((ap_ST_pp5_stg0_fsm_22 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp5_it3) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond9_reg_5697_pp5_it2))) begin
b_address1 = ap_reg_ppstg_tmp_168_reg_5895_pp5_it2;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp5_it2) & (ap_ST_pp5_stg7_fsm_29 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond9_reg_5697_pp5_it2))) begin
b_address1 = ap_reg_ppstg_tmp_164_reg_5880_pp5_it2;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp5_it2) & (ap_ST_pp5_stg6_fsm_28 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond9_reg_5697_pp5_it2))) begin
b_address1 = ap_reg_ppstg_tmp_160_reg_5840_pp5_it2;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp5_it1) & (ap_ST_pp5_stg5_fsm_27 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond9_reg_5697_pp5_it1))) begin
b_address1 = ap_reg_ppstg_tmp_130_reg_5770_pp5_it1;
end else if (((ap_ST_pp1_stg0_fsm_4 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it3) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond3_reg_5195_pp1_it2))) begin
b_address1 = ap_reg_ppstg_tmp_51_reg_5417_pp1_it2;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it2) & (ap_ST_pp1_stg7_fsm_11 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond3_reg_5195_pp1_it2))) begin
b_address1 = ap_reg_ppstg_tmp_47_reg_5407_pp1_it2;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it2) & (ap_ST_pp1_stg6_fsm_10 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond3_reg_5195_pp1_it2))) begin
b_address1 = ap_reg_ppstg_tmp_44_reg_5367_pp1_it2;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_ST_pp1_stg5_fsm_9 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond3_reg_5195_pp1_it1))) begin
b_address1 = ap_reg_ppstg_tmp_15_reg_5272_pp1_it1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp7_it1) & (ap_ST_pp7_stg3_fsm_34 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond12_reg_5924_pp7_it1))) begin
b_address1 = tmp_194_fu_4340_p1;
end else if (((ap_ST_pp7_stg2_fsm_33 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp7_it0) & (ap_const_lv1_0 == exitcond12_reg_5924))) begin
b_address1 = tmp_190_fu_4238_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp7_it0) & (ap_const_lv1_0 == exitcond12_reg_5924) & (ap_ST_pp7_stg1_fsm_32 == ap_CS_fsm))) begin
b_address1 = tmp_182_fu_4173_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp5_it0) & (ap_const_lv1_0 == exitcond9_reg_5697) & (ap_ST_pp5_stg4_fsm_26 == ap_CS_fsm))) begin
b_address1 = tmp_170_fu_3943_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp5_it0) & (ap_const_lv1_0 == exitcond9_reg_5697) & (ap_ST_pp5_stg3_fsm_25 == ap_CS_fsm))) begin
b_address1 = tmp_162_fu_3905_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp5_it0) & (ap_const_lv1_0 == exitcond9_reg_5697) & (ap_ST_pp5_stg2_fsm_24 == ap_CS_fsm))) begin
b_address1 = tmp_150_fu_3840_p1;
end else if (((ap_ST_pp5_stg1_fsm_23 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp5_it0) & (ap_const_lv1_0 == exitcond9_reg_5697))) begin
b_address1 = tmp_134_fu_3775_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp3_it1) & (ap_ST_pp3_stg3_fsm_16 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond6_reg_5446_pp3_it1))) begin
b_address1 = tmp_106_fu_3601_p1;
end else if (((ap_ST_pp3_stg2_fsm_15 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp3_it0) & (ap_const_lv1_0 == exitcond6_reg_5446))) begin
b_address1 = tmp_90_fu_3415_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp3_it0) & (ap_const_lv1_0 == exitcond6_reg_5446) & (ap_ST_pp3_stg1_fsm_14 == ap_CS_fsm))) begin
b_address1 = tmp_83_fu_3247_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond3_reg_5195) & (ap_ST_pp1_stg4_fsm_8 == ap_CS_fsm))) begin
b_address1 = tmp_55_fu_2970_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond3_reg_5195) & (ap_ST_pp1_stg3_fsm_7 == ap_CS_fsm))) begin
b_address1 = tmp_46_fu_2872_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond3_reg_5195) & (ap_ST_pp1_stg2_fsm_6 == ap_CS_fsm))) begin
b_address1 = tmp_32_fu_2765_p1;
end else if (((ap_ST_pp1_stg1_fsm_5 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond3_reg_5195))) begin
b_address1 = tmp_16_fu_2597_p1;
end else begin
b_address1 = tmp_255_reg_6920;
end
end
/// b_ce0 assign process. ///
always @ (ap_CS_fsm or ap_reg_ppiten_pp0_it6 or ap_reg_ppiten_pp1_it0 or ap_reg_ppiten_pp1_it1 or ap_reg_ppiten_pp1_it2 or exitcond3_reg_5195 or ap_reg_ppiten_pp3_it0 or ap_reg_ppiten_pp3_it1 or exitcond6_reg_5446 or ap_reg_ppiten_pp4_it6 or ap_reg_ppiten_pp5_it0 or ap_reg_ppiten_pp5_it1 or ap_reg_ppiten_pp5_it2 or exitcond9_reg_5697 or ap_reg_ppiten_pp7_it0 or ap_reg_ppiten_pp7_it1 or exitcond12_reg_5924 or ap_reg_ppiten_pp2_it0 or ap_reg_ppiten_pp6_it0 or ap_reg_ppstg_exitcond6_reg_5446_pp3_it1 or ap_reg_ppstg_exitcond12_reg_5924_pp7_it1 or ap_reg_ppstg_exitcond3_reg_5195_pp1_it1 or ap_reg_ppstg_exitcond9_reg_5697_pp5_it1 or ap_reg_ppstg_exitcond1_reg_5171_pp0_it5 or exitcond4_fu_2988_p2 or exitcond6_fu_3025_p2 or ap_reg_ppstg_exitcond7_reg_5678_pp4_it5 or exitcond10_fu_3978_p2 or exitcond12_fu_4005_p2 or exitcond_reg_6132 or ap_reg_ppiten_pp8_it0 or ap_reg_ppiten_pp8_it1)
begin
if ((((ap_ST_pp1_stg1_fsm_5 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond3_reg_5195)) | ((ap_ST_pp3_stg2_fsm_15 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp3_it0) & (ap_const_lv1_0 == exitcond6_reg_5446)) | ((ap_ST_pp5_stg1_fsm_23 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp5_it0) & (ap_const_lv1_0 == exitcond9_reg_5697)) | ((ap_ST_pp7_stg2_fsm_33 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp7_it0) & (ap_const_lv1_0 == exitcond12_reg_5924)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond3_reg_5195) & (ap_ST_pp1_stg2_fsm_6 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp3_it0) & (ap_const_lv1_0 == exitcond6_reg_5446) & (ap_ST_pp3_stg1_fsm_14 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp5_it0) & (ap_const_lv1_0 == exitcond9_reg_5697) & (ap_ST_pp5_stg2_fsm_24 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp7_it0) & (ap_const_lv1_0 == exitcond12_reg_5924) & (ap_ST_pp7_stg1_fsm_32 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp3_it0) & (ap_const_lv1_0 == exitcond6_reg_5446) & (ap_ST_pp3_stg3_fsm_16 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp7_it0) & (ap_const_lv1_0 == exitcond12_reg_5924) & (ap_ST_pp7_stg3_fsm_34 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond3_reg_5195) & (ap_ST_pp1_stg3_fsm_7 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp5_it0) & (ap_const_lv1_0 == exitcond9_reg_5697) & (ap_ST_pp5_stg3_fsm_25 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond3_reg_5195) & (ap_ST_pp1_stg4_fsm_8 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp5_it0) & (ap_const_lv1_0 == exitcond9_reg_5697) & (ap_ST_pp5_stg4_fsm_26 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp3_it1) & (ap_ST_pp3_stg4_fsm_17 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond6_reg_5446_pp3_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp7_it1) & (ap_ST_pp7_stg4_fsm_35 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond12_reg_5924_pp7_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_ST_pp1_stg5_fsm_9 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond3_reg_5195_pp1_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_ST_pp1_stg6_fsm_10 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond3_reg_5195_pp1_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_ST_pp1_stg7_fsm_11 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond3_reg_5195_pp1_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp5_it1) & (ap_ST_pp5_stg5_fsm_27 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond9_reg_5697_pp5_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp5_it1) & (ap_ST_pp5_stg6_fsm_28 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond9_reg_5697_pp5_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp5_it1) & (ap_ST_pp5_stg7_fsm_29 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond9_reg_5697_pp5_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it2) & (ap_ST_pp1_stg0_fsm_4 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond3_reg_5195_pp1_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp5_it2) & (ap_ST_pp5_stg0_fsm_22 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond9_reg_5697_pp5_it1)) | ((ap_ST_pp2_stg0_fsm_12 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp2_it0) & (ap_const_lv1_0 == exitcond4_fu_2988_p2)) | ((ap_const_logic_1 == ap_reg_ppiten_pp3_it0) & (ap_ST_pp3_stg0_fsm_13 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond6_fu_3025_p2)) | ((ap_ST_pp6_stg0_fsm_30 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp6_it0) & (ap_const_lv1_0 == exitcond10_fu_3978_p2)) | ((ap_const_logic_1 == ap_reg_ppiten_pp7_it0) & (ap_ST_pp7_stg0_fsm_31 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond12_fu_4005_p2)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_ST_pp8_stg1_fsm_41 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond_reg_6132)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg2_fsm_42 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg3_fsm_43 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg4_fsm_44 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg5_fsm_45 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg6_fsm_46 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg7_fsm_47 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg8_fsm_48 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg9_fsm_49 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg10_fsm_50 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg11_fsm_51 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg12_fsm_52 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg13_fsm_53 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg14_fsm_54 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg15_fsm_55 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg16_fsm_56 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg17_fsm_57 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg18_fsm_58 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg19_fsm_59 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg20_fsm_60 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg21_fsm_61 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg22_fsm_62 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg23_fsm_63 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg24_fsm_64 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg25_fsm_65 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg26_fsm_66 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg27_fsm_67 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg28_fsm_68 == ap_CS_fsm)) | ((ap_ST_pp8_stg0_fsm_40 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp8_it1) & (ap_const_lv1_0 == exitcond_reg_6132)) | ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond1_reg_5171_pp0_it5)) | ((ap_ST_pp4_stg0_fsm_21 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp4_it6) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond7_reg_5678_pp4_it5)))) begin
b_ce0 = ap_const_logic_1;
end else begin
b_ce0 = ap_const_logic_0;
end
end
/// b_ce1 assign process. ///
always @ (ap_CS_fsm or ap_reg_ppiten_pp1_it0 or ap_reg_ppiten_pp1_it1 or ap_reg_ppiten_pp1_it2 or exitcond3_reg_5195 or ap_reg_ppiten_pp3_it0 or ap_reg_ppiten_pp3_it1 or exitcond6_reg_5446 or ap_reg_ppiten_pp5_it0 or ap_reg_ppiten_pp5_it1 or ap_reg_ppiten_pp5_it2 or exitcond9_reg_5697 or ap_reg_ppiten_pp7_it0 or ap_reg_ppiten_pp7_it1 or exitcond12_reg_5924 or ap_reg_ppstg_exitcond6_reg_5446_pp3_it1 or ap_reg_ppstg_exitcond12_reg_5924_pp7_it1 or ap_reg_ppiten_pp1_it3 or ap_reg_ppiten_pp5_it3 or ap_reg_ppstg_exitcond3_reg_5195_pp1_it1 or ap_reg_ppstg_exitcond9_reg_5697_pp5_it1 or ap_reg_ppstg_exitcond3_reg_5195_pp1_it2 or ap_reg_ppstg_exitcond9_reg_5697_pp5_it2 or exitcond_reg_6132 or ap_reg_ppiten_pp8_it0 or ap_reg_ppiten_pp8_it1)
begin
if ((((ap_ST_pp1_stg1_fsm_5 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond3_reg_5195)) | ((ap_ST_pp3_stg2_fsm_15 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp3_it0) & (ap_const_lv1_0 == exitcond6_reg_5446)) | ((ap_ST_pp5_stg1_fsm_23 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp5_it0) & (ap_const_lv1_0 == exitcond9_reg_5697)) | ((ap_ST_pp7_stg2_fsm_33 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp7_it0) & (ap_const_lv1_0 == exitcond12_reg_5924)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond3_reg_5195) & (ap_ST_pp1_stg2_fsm_6 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp3_it0) & (ap_const_lv1_0 == exitcond6_reg_5446) & (ap_ST_pp3_stg1_fsm_14 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp5_it0) & (ap_const_lv1_0 == exitcond9_reg_5697) & (ap_ST_pp5_stg2_fsm_24 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp7_it0) & (ap_const_lv1_0 == exitcond12_reg_5924) & (ap_ST_pp7_stg1_fsm_32 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond3_reg_5195) & (ap_ST_pp1_stg3_fsm_7 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp5_it0) & (ap_const_lv1_0 == exitcond9_reg_5697) & (ap_ST_pp5_stg3_fsm_25 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond3_reg_5195) & (ap_ST_pp1_stg4_fsm_8 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp5_it0) & (ap_const_lv1_0 == exitcond9_reg_5697) & (ap_ST_pp5_stg4_fsm_26 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_ST_pp1_stg5_fsm_9 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond3_reg_5195_pp1_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp3_it1) & (ap_ST_pp3_stg3_fsm_16 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond6_reg_5446_pp3_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp5_it1) & (ap_ST_pp5_stg5_fsm_27 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond9_reg_5697_pp5_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp7_it1) & (ap_ST_pp7_stg3_fsm_34 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond12_reg_5924_pp7_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg2_fsm_42 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg3_fsm_43 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg4_fsm_44 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg5_fsm_45 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg6_fsm_46 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg7_fsm_47 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg8_fsm_48 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg9_fsm_49 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg10_fsm_50 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg11_fsm_51 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg12_fsm_52 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg13_fsm_53 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg14_fsm_54 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg15_fsm_55 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg16_fsm_56 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg17_fsm_57 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg18_fsm_58 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg19_fsm_59 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg20_fsm_60 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg21_fsm_61 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg22_fsm_62 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg23_fsm_63 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg24_fsm_64 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg25_fsm_65 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg26_fsm_66 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg27_fsm_67 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg28_fsm_68 == ap_CS_fsm)) | ((ap_ST_pp8_stg0_fsm_40 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp8_it1) & (ap_const_lv1_0 == exitcond_reg_6132)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it2) & (ap_ST_pp1_stg6_fsm_10 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond3_reg_5195_pp1_it2)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it2) & (ap_ST_pp1_stg7_fsm_11 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond3_reg_5195_pp1_it2)) | ((ap_ST_pp1_stg0_fsm_4 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it3) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond3_reg_5195_pp1_it2)) | ((ap_const_logic_1 == ap_reg_ppiten_pp5_it2) & (ap_ST_pp5_stg6_fsm_28 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond9_reg_5697_pp5_it2)) | ((ap_const_logic_1 == ap_reg_ppiten_pp5_it2) & (ap_ST_pp5_stg7_fsm_29 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond9_reg_5697_pp5_it2)) | ((ap_ST_pp5_stg0_fsm_22 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp5_it3) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond9_reg_5697_pp5_it2)))) begin
b_ce1 = ap_const_logic_1;
end else begin
b_ce1 = ap_const_logic_0;
end
end
/// b_d0 assign process. ///
always @ (ap_CS_fsm or a_q0 or ap_reg_ppiten_pp0_it6 or ap_reg_ppiten_pp1_it1 or ap_reg_ppiten_pp1_it2 or ap_reg_ppiten_pp4_it6 or ap_reg_ppiten_pp5_it1 or ap_reg_ppiten_pp5_it2 or reg_2177 or ap_reg_ppstg_exitcond3_reg_5195_pp1_it1 or ap_reg_ppstg_exitcond9_reg_5697_pp5_it1 or reg_2294 or ap_reg_ppstg_exitcond1_reg_5171_pp0_it5 or ap_reg_ppstg_exitcond7_reg_5678_pp4_it5 or exitcond_reg_6132 or ap_reg_ppiten_pp8_it0 or ap_reg_ppiten_pp8_it1)
begin
if ((((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_ST_pp8_stg1_fsm_41 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond_reg_6132)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg2_fsm_42 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg3_fsm_43 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg4_fsm_44 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg5_fsm_45 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg6_fsm_46 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg7_fsm_47 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg8_fsm_48 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg9_fsm_49 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg10_fsm_50 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg11_fsm_51 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg12_fsm_52 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg13_fsm_53 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg14_fsm_54 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg15_fsm_55 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg16_fsm_56 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg17_fsm_57 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg18_fsm_58 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg19_fsm_59 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg20_fsm_60 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg21_fsm_61 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg22_fsm_62 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg23_fsm_63 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg24_fsm_64 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg25_fsm_65 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg26_fsm_66 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg27_fsm_67 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg28_fsm_68 == ap_CS_fsm)) | ((ap_ST_pp8_stg0_fsm_40 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp8_it1) & (ap_const_lv1_0 == exitcond_reg_6132)))) begin
b_d0 = a_q0;
end else if ((((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_ST_pp1_stg5_fsm_9 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond3_reg_5195_pp1_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_ST_pp1_stg6_fsm_10 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond3_reg_5195_pp1_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_ST_pp1_stg7_fsm_11 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond3_reg_5195_pp1_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp5_it1) & (ap_ST_pp5_stg5_fsm_27 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond9_reg_5697_pp5_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp5_it1) & (ap_ST_pp5_stg6_fsm_28 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond9_reg_5697_pp5_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp5_it1) & (ap_ST_pp5_stg7_fsm_29 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond9_reg_5697_pp5_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it2) & (ap_ST_pp1_stg0_fsm_4 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond3_reg_5195_pp1_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp5_it2) & (ap_ST_pp5_stg0_fsm_22 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond9_reg_5697_pp5_it1)))) begin
b_d0 = reg_2294;
end else if ((((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond1_reg_5171_pp0_it5)) | ((ap_ST_pp4_stg0_fsm_21 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp4_it6) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond7_reg_5678_pp4_it5)))) begin
b_d0 = reg_2177;
end else begin
b_d0 = reg_2294;
end
end
/// b_d1 assign process. ///
always @ (ap_CS_fsm or a_q1 or ap_reg_ppiten_pp1_it1 or ap_reg_ppiten_pp1_it2 or ap_reg_ppiten_pp5_it1 or ap_reg_ppiten_pp5_it2 or ap_reg_ppiten_pp1_it3 or ap_reg_ppiten_pp5_it3 or ap_reg_ppstg_exitcond3_reg_5195_pp1_it1 or ap_reg_ppstg_exitcond9_reg_5697_pp5_it1 or reg_2305 or reg_2335 or reg_2341 or ap_reg_ppstg_exitcond3_reg_5195_pp1_it2 or ap_reg_ppstg_exitcond9_reg_5697_pp5_it2 or reg_2347 or exitcond_reg_6132 or ap_reg_ppiten_pp8_it0 or ap_reg_ppiten_pp8_it1)
begin
if ((((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg2_fsm_42 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg3_fsm_43 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg4_fsm_44 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg5_fsm_45 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg6_fsm_46 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg7_fsm_47 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg8_fsm_48 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg9_fsm_49 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg10_fsm_50 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg11_fsm_51 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg12_fsm_52 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg13_fsm_53 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg14_fsm_54 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg15_fsm_55 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg16_fsm_56 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg17_fsm_57 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg18_fsm_58 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg19_fsm_59 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg20_fsm_60 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg21_fsm_61 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg22_fsm_62 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg23_fsm_63 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg24_fsm_64 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg25_fsm_65 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg26_fsm_66 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg27_fsm_67 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg28_fsm_68 == ap_CS_fsm)) | ((ap_ST_pp8_stg0_fsm_40 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp8_it1) & (ap_const_lv1_0 == exitcond_reg_6132)))) begin
b_d1 = a_q1;
end else if ((((ap_ST_pp1_stg0_fsm_4 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it3) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond3_reg_5195_pp1_it2)) | ((ap_ST_pp5_stg0_fsm_22 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp5_it3) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond9_reg_5697_pp5_it2)))) begin
b_d1 = reg_2347;
end else if ((((ap_const_logic_1 == ap_reg_ppiten_pp1_it2) & (ap_ST_pp1_stg7_fsm_11 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond3_reg_5195_pp1_it2)) | ((ap_const_logic_1 == ap_reg_ppiten_pp5_it2) & (ap_ST_pp5_stg7_fsm_29 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond9_reg_5697_pp5_it2)))) begin
b_d1 = reg_2341;
end else if ((((ap_const_logic_1 == ap_reg_ppiten_pp1_it2) & (ap_ST_pp1_stg6_fsm_10 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond3_reg_5195_pp1_it2)) | ((ap_const_logic_1 == ap_reg_ppiten_pp5_it2) & (ap_ST_pp5_stg6_fsm_28 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond9_reg_5697_pp5_it2)))) begin
b_d1 = reg_2335;
end else if ((((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_ST_pp1_stg5_fsm_9 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond3_reg_5195_pp1_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp5_it1) & (ap_ST_pp5_stg5_fsm_27 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond9_reg_5697_pp5_it1)))) begin
b_d1 = reg_2305;
end else begin
b_d1 = reg_2347;
end
end
/// b_we0 assign process. ///
always @ (ap_CS_fsm or ap_reg_ppiten_pp0_it6 or ap_reg_ppiten_pp1_it1 or ap_reg_ppiten_pp1_it2 or ap_reg_ppiten_pp4_it6 or ap_reg_ppiten_pp5_it1 or ap_reg_ppiten_pp5_it2 or ap_reg_ppstg_exitcond3_reg_5195_pp1_it1 or ap_reg_ppstg_exitcond9_reg_5697_pp5_it1 or ap_reg_ppstg_exitcond1_reg_5171_pp0_it5 or ap_reg_ppstg_exitcond7_reg_5678_pp4_it5 or exitcond_reg_6132 or ap_reg_ppiten_pp8_it0 or ap_reg_ppiten_pp8_it1)
begin
if ((((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_ST_pp1_stg5_fsm_9 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond3_reg_5195_pp1_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_ST_pp1_stg6_fsm_10 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond3_reg_5195_pp1_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_ST_pp1_stg7_fsm_11 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond3_reg_5195_pp1_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp5_it1) & (ap_ST_pp5_stg5_fsm_27 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond9_reg_5697_pp5_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp5_it1) & (ap_ST_pp5_stg6_fsm_28 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond9_reg_5697_pp5_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp5_it1) & (ap_ST_pp5_stg7_fsm_29 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond9_reg_5697_pp5_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it2) & (ap_ST_pp1_stg0_fsm_4 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond3_reg_5195_pp1_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp5_it2) & (ap_ST_pp5_stg0_fsm_22 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond9_reg_5697_pp5_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_ST_pp8_stg1_fsm_41 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond_reg_6132)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg2_fsm_42 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg3_fsm_43 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg4_fsm_44 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg5_fsm_45 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg6_fsm_46 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg7_fsm_47 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg8_fsm_48 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg9_fsm_49 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg10_fsm_50 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg11_fsm_51 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg12_fsm_52 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg13_fsm_53 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg14_fsm_54 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg15_fsm_55 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg16_fsm_56 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg17_fsm_57 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg18_fsm_58 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg19_fsm_59 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg20_fsm_60 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg21_fsm_61 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg22_fsm_62 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg23_fsm_63 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg24_fsm_64 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg25_fsm_65 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg26_fsm_66 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg27_fsm_67 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg28_fsm_68 == ap_CS_fsm)) | ((ap_ST_pp8_stg0_fsm_40 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp8_it1) & (ap_const_lv1_0 == exitcond_reg_6132)) | ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond1_reg_5171_pp0_it5)) | ((ap_ST_pp4_stg0_fsm_21 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp4_it6) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond7_reg_5678_pp4_it5)))) begin
b_we0 = ap_const_logic_1;
end else begin
b_we0 = ap_const_logic_0;
end
end
/// b_we1 assign process. ///
always @ (ap_CS_fsm or ap_reg_ppiten_pp1_it1 or ap_reg_ppiten_pp1_it2 or ap_reg_ppiten_pp5_it1 or ap_reg_ppiten_pp5_it2 or ap_reg_ppiten_pp1_it3 or ap_reg_ppiten_pp5_it3 or ap_reg_ppstg_exitcond3_reg_5195_pp1_it1 or ap_reg_ppstg_exitcond9_reg_5697_pp5_it1 or ap_reg_ppstg_exitcond3_reg_5195_pp1_it2 or ap_reg_ppstg_exitcond9_reg_5697_pp5_it2 or exitcond_reg_6132 or ap_reg_ppiten_pp8_it0 or ap_reg_ppiten_pp8_it1)
begin
if ((((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_ST_pp1_stg5_fsm_9 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond3_reg_5195_pp1_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp5_it1) & (ap_ST_pp5_stg5_fsm_27 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond9_reg_5697_pp5_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg2_fsm_42 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg3_fsm_43 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg4_fsm_44 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg5_fsm_45 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg6_fsm_46 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg7_fsm_47 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg8_fsm_48 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg9_fsm_49 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg10_fsm_50 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg11_fsm_51 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg12_fsm_52 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg13_fsm_53 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg14_fsm_54 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg15_fsm_55 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg16_fsm_56 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg17_fsm_57 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg18_fsm_58 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg19_fsm_59 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg20_fsm_60 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg21_fsm_61 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg22_fsm_62 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg23_fsm_63 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg24_fsm_64 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg25_fsm_65 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg26_fsm_66 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg27_fsm_67 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp8_it0) & (ap_const_lv1_0 == exitcond_reg_6132) & (ap_ST_pp8_stg28_fsm_68 == ap_CS_fsm)) | ((ap_ST_pp8_stg0_fsm_40 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp8_it1) & (ap_const_lv1_0 == exitcond_reg_6132)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it2) & (ap_ST_pp1_stg6_fsm_10 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond3_reg_5195_pp1_it2)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it2) & (ap_ST_pp1_stg7_fsm_11 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond3_reg_5195_pp1_it2)) | ((ap_ST_pp1_stg0_fsm_4 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it3) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond3_reg_5195_pp1_it2)) | ((ap_const_logic_1 == ap_reg_ppiten_pp5_it2) & (ap_ST_pp5_stg6_fsm_28 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond9_reg_5697_pp5_it2)) | ((ap_const_logic_1 == ap_reg_ppiten_pp5_it2) & (ap_ST_pp5_stg7_fsm_29 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond9_reg_5697_pp5_it2)) | ((ap_ST_pp5_stg0_fsm_22 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp5_it3) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond9_reg_5697_pp5_it2)))) begin
b_we1 = ap_const_logic_1;
end else begin
b_we1 = ap_const_logic_0;
end
end
/// grp_fu_2163_p0 assign process. ///
always @ (ap_CS_fsm or reg_2171 or ap_reg_ppiten_pp1_it0 or ap_reg_ppiten_pp1_it1 or exitcond3_reg_5195 or ap_reg_ppiten_pp3_it0 or ap_reg_ppiten_pp3_it1 or exitcond6_reg_5446 or ap_reg_ppiten_pp5_it0 or ap_reg_ppiten_pp5_it1 or exitcond9_reg_5697 or ap_reg_ppiten_pp7_it0 or ap_reg_ppiten_pp7_it1 or exitcond12_reg_5924 or reg_2184 or reg_2190 or reg_2197 or reg_2204 or reg_2211 or reg_2218 or reg_2225 or reg_2232 or reg_2239 or reg_2246 or reg_2253 or reg_2260 or ap_reg_ppstg_exitcond6_reg_5446_pp3_it1 or ap_reg_ppstg_exitcond12_reg_5924_pp7_it1 or reg_2267 or ap_reg_ppstg_exitcond3_reg_5195_pp1_it1 or ap_reg_ppstg_exitcond9_reg_5697_pp5_it1 or reg_2311 or reg_2323)
begin
if ((((ap_const_logic_1 == ap_reg_ppiten_pp3_it1) & (ap_ST_pp3_stg6_fsm_19 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond6_reg_5446_pp3_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp7_it1) & (ap_ST_pp7_stg6_fsm_37 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond12_reg_5924_pp7_it1)))) begin
grp_fu_2163_p0 = reg_2267;
end else if ((((ap_const_logic_1 == ap_reg_ppiten_pp3_it1) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond6_reg_5446_pp3_it1) & (ap_ST_pp3_stg5_fsm_18 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp7_it1) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond12_reg_5924_pp7_it1) & (ap_ST_pp7_stg5_fsm_36 == ap_CS_fsm)))) begin
grp_fu_2163_p0 = reg_2260;
end else if ((((ap_const_logic_1 == ap_reg_ppiten_pp3_it1) & (ap_ST_pp3_stg4_fsm_17 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond6_reg_5446_pp3_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp7_it1) & (ap_ST_pp7_stg4_fsm_35 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond12_reg_5924_pp7_it1)))) begin
grp_fu_2163_p0 = reg_2253;
end else if ((((ap_const_logic_1 == ap_reg_ppiten_pp3_it1) & (ap_ST_pp3_stg3_fsm_16 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond6_reg_5446_pp3_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp7_it1) & (ap_ST_pp7_stg3_fsm_34 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond12_reg_5924_pp7_it1)))) begin
grp_fu_2163_p0 = reg_2239;
end else if ((((ap_ST_pp3_stg2_fsm_15 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp3_it1) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond6_reg_5446_pp3_it1)) | ((ap_ST_pp7_stg2_fsm_33 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp7_it1) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond12_reg_5924_pp7_it1)))) begin
grp_fu_2163_p0 = reg_2225;
end else if ((((ap_const_logic_1 == ap_reg_ppiten_pp3_it1) & (ap_ST_pp3_stg1_fsm_14 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond6_reg_5446_pp3_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp7_it1) & (ap_ST_pp7_stg1_fsm_32 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond12_reg_5924_pp7_it1)))) begin
grp_fu_2163_p0 = reg_2211;
end else if ((((ap_const_logic_1 == ap_reg_ppiten_pp3_it1) & (ap_const_lv1_0 == exitcond6_reg_5446) & (ap_ST_pp3_stg0_fsm_13 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp7_it1) & (ap_const_lv1_0 == exitcond12_reg_5924) & (ap_ST_pp7_stg0_fsm_31 == ap_CS_fsm)))) begin
grp_fu_2163_p0 = reg_2197;
end else if ((((ap_const_logic_1 == ap_reg_ppiten_pp3_it0) & (ap_const_lv1_0 == exitcond6_reg_5446) & (ap_ST_pp3_stg7_fsm_20 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp7_it0) & (ap_const_lv1_0 == exitcond12_reg_5924) & (ap_ST_pp7_stg7_fsm_38 == ap_CS_fsm)))) begin
grp_fu_2163_p0 = reg_2184;
end else if ((((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_ST_pp1_stg6_fsm_10 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond3_reg_5195_pp1_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp5_it1) & (ap_ST_pp5_stg6_fsm_28 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond9_reg_5697_pp5_it1)))) begin
grp_fu_2163_p0 = reg_2323;
end else if ((((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_ST_pp1_stg5_fsm_9 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond3_reg_5195_pp1_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp5_it1) & (ap_ST_pp5_stg5_fsm_27 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond9_reg_5697_pp5_it1)))) begin
grp_fu_2163_p0 = reg_2311;
end else if ((((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_ST_pp1_stg4_fsm_8 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond3_reg_5195_pp1_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp5_it1) & (ap_ST_pp5_stg4_fsm_26 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond9_reg_5697_pp5_it1)))) begin
grp_fu_2163_p0 = reg_2246;
end else if ((((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_ST_pp1_stg3_fsm_7 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond3_reg_5195_pp1_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp5_it1) & (ap_ST_pp5_stg3_fsm_25 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond9_reg_5697_pp5_it1)))) begin
grp_fu_2163_p0 = reg_2232;
end else if ((((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_ST_pp1_stg2_fsm_6 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond3_reg_5195_pp1_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp5_it1) & (ap_ST_pp5_stg2_fsm_24 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond9_reg_5697_pp5_it1)))) begin
grp_fu_2163_p0 = reg_2218;
end else if ((((ap_ST_pp1_stg1_fsm_5 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond3_reg_5195_pp1_it1)) | ((ap_ST_pp5_stg1_fsm_23 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp5_it1) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond9_reg_5697_pp5_it1)))) begin
grp_fu_2163_p0 = reg_2204;
end else if ((((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_const_lv1_0 == exitcond3_reg_5195) & (ap_ST_pp1_stg0_fsm_4 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp5_it1) & (ap_const_lv1_0 == exitcond9_reg_5697) & (ap_ST_pp5_stg0_fsm_22 == ap_CS_fsm)))) begin
grp_fu_2163_p0 = reg_2190;
end else if ((((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond3_reg_5195) & (ap_ST_pp1_stg7_fsm_11 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp5_it0) & (ap_const_lv1_0 == exitcond9_reg_5697) & (ap_ST_pp5_stg7_fsm_29 == ap_CS_fsm)))) begin
grp_fu_2163_p0 = reg_2171;
end else begin
grp_fu_2163_p0 = reg_2323;
end
end
/// grp_fu_2163_p1 assign process. ///
always @ (ap_CS_fsm or ap_reg_ppiten_pp1_it0 or ap_reg_ppiten_pp1_it1 or exitcond3_reg_5195 or ap_reg_ppiten_pp3_it0 or ap_reg_ppiten_pp3_it1 or exitcond6_reg_5446 or ap_reg_ppiten_pp5_it0 or ap_reg_ppiten_pp5_it1 or exitcond9_reg_5697 or ap_reg_ppiten_pp7_it0 or ap_reg_ppiten_pp7_it1 or exitcond12_reg_5924 or reg_2177 or ap_reg_ppstg_exitcond6_reg_5446_pp3_it1 or ap_reg_ppstg_exitcond12_reg_5924_pp7_it1 or reg_2274 or reg_2279 or reg_2284 or ap_reg_ppstg_exitcond3_reg_5195_pp1_it1 or ap_reg_ppstg_exitcond9_reg_5697_pp5_it1 or reg_2289 or reg_2300 or reg_2318 or reg_2330)
begin
if ((((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_ST_pp1_stg6_fsm_10 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond3_reg_5195_pp1_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp3_it1) & (ap_ST_pp3_stg6_fsm_19 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond6_reg_5446_pp3_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp5_it1) & (ap_ST_pp5_stg6_fsm_28 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond9_reg_5697_pp5_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp7_it1) & (ap_ST_pp7_stg6_fsm_37 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond12_reg_5924_pp7_it1)))) begin
grp_fu_2163_p1 = reg_2330;
end else if ((((ap_const_logic_1 == ap_reg_ppiten_pp3_it1) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond6_reg_5446_pp3_it1) & (ap_ST_pp3_stg5_fsm_18 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp7_it1) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond12_reg_5924_pp7_it1) & (ap_ST_pp7_stg5_fsm_36 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_ST_pp1_stg5_fsm_9 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond3_reg_5195_pp1_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp5_it1) & (ap_ST_pp5_stg5_fsm_27 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond9_reg_5697_pp5_it1)))) begin
grp_fu_2163_p1 = reg_2318;
end else if ((((ap_const_logic_1 == ap_reg_ppiten_pp3_it1) & (ap_ST_pp3_stg4_fsm_17 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond6_reg_5446_pp3_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp7_it1) & (ap_ST_pp7_stg4_fsm_35 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond12_reg_5924_pp7_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_ST_pp1_stg4_fsm_8 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond3_reg_5195_pp1_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp5_it1) & (ap_ST_pp5_stg4_fsm_26 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond9_reg_5697_pp5_it1)))) begin
grp_fu_2163_p1 = reg_2300;
end else if ((((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_ST_pp1_stg3_fsm_7 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond3_reg_5195_pp1_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp3_it1) & (ap_ST_pp3_stg3_fsm_16 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond6_reg_5446_pp3_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp5_it1) & (ap_ST_pp5_stg3_fsm_25 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond9_reg_5697_pp5_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp7_it1) & (ap_ST_pp7_stg3_fsm_34 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond12_reg_5924_pp7_it1)))) begin
grp_fu_2163_p1 = reg_2289;
end else if ((((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_ST_pp1_stg2_fsm_6 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond3_reg_5195_pp1_it1)) | ((ap_ST_pp3_stg2_fsm_15 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp3_it1) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond6_reg_5446_pp3_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp5_it1) & (ap_ST_pp5_stg2_fsm_24 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond9_reg_5697_pp5_it1)) | ((ap_ST_pp7_stg2_fsm_33 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp7_it1) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond12_reg_5924_pp7_it1)))) begin
grp_fu_2163_p1 = reg_2284;
end else if ((((ap_ST_pp1_stg1_fsm_5 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond3_reg_5195_pp1_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp3_it1) & (ap_ST_pp3_stg1_fsm_14 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond6_reg_5446_pp3_it1)) | ((ap_ST_pp5_stg1_fsm_23 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp5_it1) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond9_reg_5697_pp5_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp7_it1) & (ap_ST_pp7_stg1_fsm_32 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond12_reg_5924_pp7_it1)))) begin
grp_fu_2163_p1 = reg_2279;
end else if ((((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_const_lv1_0 == exitcond3_reg_5195) & (ap_ST_pp1_stg0_fsm_4 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp3_it1) & (ap_const_lv1_0 == exitcond6_reg_5446) & (ap_ST_pp3_stg0_fsm_13 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp5_it1) & (ap_const_lv1_0 == exitcond9_reg_5697) & (ap_ST_pp5_stg0_fsm_22 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp7_it1) & (ap_const_lv1_0 == exitcond12_reg_5924) & (ap_ST_pp7_stg0_fsm_31 == ap_CS_fsm)))) begin
grp_fu_2163_p1 = reg_2274;
end else if ((((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond3_reg_5195) & (ap_ST_pp1_stg7_fsm_11 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp3_it0) & (ap_const_lv1_0 == exitcond6_reg_5446) & (ap_ST_pp3_stg7_fsm_20 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp5_it0) & (ap_const_lv1_0 == exitcond9_reg_5697) & (ap_ST_pp5_stg7_fsm_29 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp7_it0) & (ap_const_lv1_0 == exitcond12_reg_5924) & (ap_ST_pp7_stg7_fsm_38 == ap_CS_fsm)))) begin
grp_fu_2163_p1 = reg_2177;
end else begin
grp_fu_2163_p1 = reg_2330;
end
end
/// grp_fu_2167_p0 assign process. ///
always @ (ap_CS_fsm or reg_2171 or ap_reg_ppiten_pp0_it2 or ap_reg_ppiten_pp1_it0 or ap_reg_ppiten_pp1_it1 or exitcond3_reg_5195 or ap_reg_ppiten_pp3_it0 or ap_reg_ppiten_pp3_it1 or exitcond6_reg_5446 or ap_reg_ppiten_pp4_it2 or ap_reg_ppiten_pp5_it0 or ap_reg_ppiten_pp5_it1 or exitcond9_reg_5697 or ap_reg_ppiten_pp7_it0 or ap_reg_ppiten_pp7_it1 or exitcond12_reg_5924 or ap_reg_ppiten_pp2_it2 or ap_reg_ppiten_pp6_it2 or reg_2184 or reg_2190 or reg_2197 or reg_2204 or reg_2211 or reg_2218 or reg_2225 or reg_2232 or reg_2239 or reg_2246 or reg_2253 or reg_2260 or ap_reg_ppstg_exitcond6_reg_5446_pp3_it1 or ap_reg_ppstg_exitcond12_reg_5924_pp7_it1 or reg_2267 or ap_reg_ppstg_exitcond3_reg_5195_pp1_it1 or ap_reg_ppstg_exitcond9_reg_5697_pp5_it1 or reg_2311 or reg_2323 or ap_reg_ppstg_exitcond1_reg_5171_pp0_it1 or ap_reg_ppstg_exitcond4_reg_5427_pp2_it1 or ap_reg_ppstg_exitcond7_reg_5678_pp4_it1 or ap_reg_ppstg_exitcond10_reg_5905_pp6_it1)
begin
if ((((ap_ST_pp3_stg2_fsm_15 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp3_it1) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond6_reg_5446_pp3_it1)) | ((ap_ST_pp7_stg2_fsm_33 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp7_it1) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond12_reg_5924_pp7_it1)))) begin
grp_fu_2167_p0 = reg_2323;
end else if ((((ap_const_logic_1 == ap_reg_ppiten_pp3_it1) & (ap_ST_pp3_stg1_fsm_14 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond6_reg_5446_pp3_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp7_it1) & (ap_ST_pp7_stg1_fsm_32 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond12_reg_5924_pp7_it1)))) begin
grp_fu_2167_p0 = reg_2311;
end else if ((((ap_const_logic_1 == ap_reg_ppiten_pp3_it1) & (ap_const_lv1_0 == exitcond6_reg_5446) & (ap_ST_pp3_stg0_fsm_13 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp7_it1) & (ap_const_lv1_0 == exitcond12_reg_5924) & (ap_ST_pp7_stg0_fsm_31 == ap_CS_fsm)))) begin
grp_fu_2167_p0 = reg_2246;
end else if ((((ap_const_logic_1 == ap_reg_ppiten_pp3_it0) & (ap_const_lv1_0 == exitcond6_reg_5446) & (ap_ST_pp3_stg7_fsm_20 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp7_it0) & (ap_const_lv1_0 == exitcond12_reg_5924) & (ap_ST_pp7_stg7_fsm_38 == ap_CS_fsm)))) begin
grp_fu_2167_p0 = reg_2232;
end else if ((((ap_const_logic_1 == ap_reg_ppiten_pp3_it0) & (ap_const_lv1_0 == exitcond6_reg_5446) & (ap_ST_pp3_stg6_fsm_19 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp7_it0) & (ap_const_lv1_0 == exitcond12_reg_5924) & (ap_ST_pp7_stg6_fsm_37 == ap_CS_fsm)))) begin
grp_fu_2167_p0 = reg_2218;
end else if ((((ap_const_logic_1 == ap_reg_ppiten_pp3_it0) & (ap_const_lv1_0 == exitcond6_reg_5446) & (ap_ST_pp3_stg5_fsm_18 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp7_it0) & (ap_const_lv1_0 == exitcond12_reg_5924) & (ap_ST_pp7_stg5_fsm_36 == ap_CS_fsm)))) begin
grp_fu_2167_p0 = reg_2204;
end else if ((((ap_const_logic_1 == ap_reg_ppiten_pp3_it0) & (ap_const_lv1_0 == exitcond6_reg_5446) & (ap_ST_pp3_stg4_fsm_17 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp7_it0) & (ap_const_lv1_0 == exitcond12_reg_5924) & (ap_ST_pp7_stg4_fsm_35 == ap_CS_fsm)))) begin
grp_fu_2167_p0 = reg_2190;
end else if ((((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_ST_pp1_stg2_fsm_6 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond3_reg_5195_pp1_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp5_it1) & (ap_ST_pp5_stg2_fsm_24 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond9_reg_5697_pp5_it1)))) begin
grp_fu_2167_p0 = reg_2267;
end else if ((((ap_ST_pp1_stg1_fsm_5 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond3_reg_5195_pp1_it1)) | ((ap_ST_pp5_stg1_fsm_23 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp5_it1) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond9_reg_5697_pp5_it1)))) begin
grp_fu_2167_p0 = reg_2260;
end else if ((((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_const_lv1_0 == exitcond3_reg_5195) & (ap_ST_pp1_stg0_fsm_4 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp5_it1) & (ap_const_lv1_0 == exitcond9_reg_5697) & (ap_ST_pp5_stg0_fsm_22 == ap_CS_fsm)))) begin
grp_fu_2167_p0 = reg_2253;
end else if ((((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond3_reg_5195) & (ap_ST_pp1_stg7_fsm_11 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp5_it0) & (ap_const_lv1_0 == exitcond9_reg_5697) & (ap_ST_pp5_stg7_fsm_29 == ap_CS_fsm)))) begin
grp_fu_2167_p0 = reg_2239;
end else if ((((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond3_reg_5195) & (ap_ST_pp1_stg6_fsm_10 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp5_it0) & (ap_const_lv1_0 == exitcond9_reg_5697) & (ap_ST_pp5_stg6_fsm_28 == ap_CS_fsm)))) begin
grp_fu_2167_p0 = reg_2225;
end else if ((((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond3_reg_5195) & (ap_ST_pp1_stg5_fsm_9 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp5_it0) & (ap_const_lv1_0 == exitcond9_reg_5697) & (ap_ST_pp5_stg5_fsm_27 == ap_CS_fsm)))) begin
grp_fu_2167_p0 = reg_2211;
end else if ((((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond3_reg_5195) & (ap_ST_pp1_stg4_fsm_8 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp5_it0) & (ap_const_lv1_0 == exitcond9_reg_5697) & (ap_ST_pp5_stg4_fsm_26 == ap_CS_fsm)))) begin
grp_fu_2167_p0 = reg_2197;
end else if ((((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond3_reg_5195) & (ap_ST_pp1_stg3_fsm_7 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp5_it0) & (ap_const_lv1_0 == exitcond9_reg_5697) & (ap_ST_pp5_stg3_fsm_25 == ap_CS_fsm)) | ((ap_ST_pp2_stg0_fsm_12 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp2_it2) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond4_reg_5427_pp2_it1)) | ((ap_ST_pp6_stg0_fsm_30 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp6_it2) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond10_reg_5905_pp6_it1)))) begin
grp_fu_2167_p0 = reg_2184;
end else if ((((ap_const_logic_1 == ap_reg_ppiten_pp3_it0) & (ap_const_lv1_0 == exitcond6_reg_5446) & (ap_ST_pp3_stg3_fsm_16 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp7_it0) & (ap_const_lv1_0 == exitcond12_reg_5924) & (ap_ST_pp7_stg3_fsm_34 == ap_CS_fsm)) | ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it2) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond1_reg_5171_pp0_it1)) | ((ap_ST_pp4_stg0_fsm_21 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp4_it2) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond7_reg_5678_pp4_it1)))) begin
grp_fu_2167_p0 = reg_2171;
end else begin
grp_fu_2167_p0 = reg_2323;
end
end
/// grp_fu_2167_p1 assign process. ///
always @ (ap_CS_fsm or BoundryScale or nu or ap_reg_ppiten_pp0_it2 or ap_reg_ppiten_pp1_it0 or ap_reg_ppiten_pp1_it1 or exitcond3_reg_5195 or ap_reg_ppiten_pp3_it0 or ap_reg_ppiten_pp3_it1 or exitcond6_reg_5446 or ap_reg_ppiten_pp4_it2 or ap_reg_ppiten_pp5_it0 or ap_reg_ppiten_pp5_it1 or exitcond9_reg_5697 or ap_reg_ppiten_pp7_it0 or ap_reg_ppiten_pp7_it1 or exitcond12_reg_5924 or ap_reg_ppiten_pp2_it2 or ap_reg_ppiten_pp6_it2 or ap_reg_ppstg_exitcond6_reg_5446_pp3_it1 or ap_reg_ppstg_exitcond12_reg_5924_pp7_it1 or ap_reg_ppstg_exitcond3_reg_5195_pp1_it1 or ap_reg_ppstg_exitcond9_reg_5697_pp5_it1 or ap_reg_ppstg_exitcond1_reg_5171_pp0_it1 or ap_reg_ppstg_exitcond4_reg_5427_pp2_it1 or ap_reg_ppstg_exitcond7_reg_5678_pp4_it1 or ap_reg_ppstg_exitcond10_reg_5905_pp6_it1)
begin
if ((((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond3_reg_5195) & (ap_ST_pp1_stg6_fsm_10 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp3_it0) & (ap_const_lv1_0 == exitcond6_reg_5446) & (ap_ST_pp3_stg6_fsm_19 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp5_it0) & (ap_const_lv1_0 == exitcond9_reg_5697) & (ap_ST_pp5_stg6_fsm_28 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp7_it0) & (ap_const_lv1_0 == exitcond12_reg_5924) & (ap_ST_pp7_stg6_fsm_37 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp3_it0) & (ap_const_lv1_0 == exitcond6_reg_5446) & (ap_ST_pp3_stg3_fsm_16 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp7_it0) & (ap_const_lv1_0 == exitcond12_reg_5924) & (ap_ST_pp7_stg3_fsm_34 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond3_reg_5195) & (ap_ST_pp1_stg3_fsm_7 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp5_it0) & (ap_const_lv1_0 == exitcond9_reg_5697) & (ap_ST_pp5_stg3_fsm_25 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp3_it0) & (ap_const_lv1_0 == exitcond6_reg_5446) & (ap_ST_pp3_stg4_fsm_17 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp7_it0) & (ap_const_lv1_0 == exitcond12_reg_5924) & (ap_ST_pp7_stg4_fsm_35 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond3_reg_5195) & (ap_ST_pp1_stg4_fsm_8 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp5_it0) & (ap_const_lv1_0 == exitcond9_reg_5697) & (ap_ST_pp5_stg4_fsm_26 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond3_reg_5195) & (ap_ST_pp1_stg5_fsm_9 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp5_it0) & (ap_const_lv1_0 == exitcond9_reg_5697) & (ap_ST_pp5_stg5_fsm_27 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond3_reg_5195) & (ap_ST_pp1_stg7_fsm_11 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp3_it0) & (ap_const_lv1_0 == exitcond6_reg_5446) & (ap_ST_pp3_stg7_fsm_20 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp5_it0) & (ap_const_lv1_0 == exitcond9_reg_5697) & (ap_ST_pp5_stg7_fsm_29 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp7_it0) & (ap_const_lv1_0 == exitcond12_reg_5924) & (ap_ST_pp7_stg7_fsm_38 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_const_lv1_0 == exitcond3_reg_5195) & (ap_ST_pp1_stg0_fsm_4 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp3_it1) & (ap_const_lv1_0 == exitcond6_reg_5446) & (ap_ST_pp3_stg0_fsm_13 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp5_it1) & (ap_const_lv1_0 == exitcond9_reg_5697) & (ap_ST_pp5_stg0_fsm_22 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp7_it1) & (ap_const_lv1_0 == exitcond12_reg_5924) & (ap_ST_pp7_stg0_fsm_31 == ap_CS_fsm)) | ((ap_ST_pp1_stg1_fsm_5 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond3_reg_5195_pp1_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp3_it1) & (ap_ST_pp3_stg1_fsm_14 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond6_reg_5446_pp3_it1)) | ((ap_ST_pp5_stg1_fsm_23 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp5_it1) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond9_reg_5697_pp5_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp7_it1) & (ap_ST_pp7_stg1_fsm_32 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond12_reg_5924_pp7_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_ST_pp1_stg2_fsm_6 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond3_reg_5195_pp1_it1)) | ((ap_ST_pp3_stg2_fsm_15 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp3_it1) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond6_reg_5446_pp3_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp5_it1) & (ap_ST_pp5_stg2_fsm_24 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond9_reg_5697_pp5_it1)) | ((ap_ST_pp7_stg2_fsm_33 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp7_it1) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond12_reg_5924_pp7_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp3_it0) & (ap_const_lv1_0 == exitcond6_reg_5446) & (ap_ST_pp3_stg5_fsm_18 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp7_it0) & (ap_const_lv1_0 == exitcond12_reg_5924) & (ap_ST_pp7_stg5_fsm_36 == ap_CS_fsm)))) begin
grp_fu_2167_p1 = nu;
end else if ((((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it2) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond1_reg_5171_pp0_it1)) | ((ap_ST_pp2_stg0_fsm_12 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp2_it2) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond4_reg_5427_pp2_it1)) | ((ap_ST_pp4_stg0_fsm_21 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp4_it2) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond7_reg_5678_pp4_it1)) | ((ap_ST_pp6_stg0_fsm_30 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp6_it2) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond10_reg_5905_pp6_it1)))) begin
grp_fu_2167_p1 = BoundryScale;
end else begin
grp_fu_2167_p1 = nu;
end
end
/// i_1_phi_fu_1934_p4 assign process. ///
always @ (ap_CS_fsm or i_1_reg_1930 or ap_reg_ppiten_pp1_it1 or exitcond3_reg_5195 or tmp_43_reg_5402)
begin
if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_const_lv1_0 == exitcond3_reg_5195) & (ap_ST_pp1_stg0_fsm_4 == ap_CS_fsm))) begin
i_1_phi_fu_1934_p4 = tmp_43_reg_5402;
end else begin
i_1_phi_fu_1934_p4 = i_1_reg_1930;
end
end
/// i_2_phi_fu_1945_p4 assign process. ///
always @ (ap_CS_fsm or i_2_reg_1941 or ap_reg_ppiten_pp2_it1 or exitcond4_reg_5427 or tmp_10_reg_5431)
begin
if (((ap_ST_pp2_stg0_fsm_12 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp2_it1) & (ap_const_lv1_0 == exitcond4_reg_5427))) begin
i_2_phi_fu_1945_p4 = tmp_10_reg_5431;
end else begin
i_2_phi_fu_1945_p4 = i_2_reg_1941;
end
end
/// i_3_phi_fu_1989_p4 assign process. ///
always @ (ap_CS_fsm or i_3_reg_1985 or ap_reg_ppiten_pp3_it1 or exitcond6_reg_5446 or tmp_82_reg_5653)
begin
if (((ap_const_logic_1 == ap_reg_ppiten_pp3_it1) & (ap_const_lv1_0 == exitcond6_reg_5446) & (ap_ST_pp3_stg0_fsm_13 == ap_CS_fsm))) begin
i_3_phi_fu_1989_p4 = tmp_82_reg_5653;
end else begin
i_3_phi_fu_1989_p4 = i_3_reg_1985;
end
end
/// i_4_phi_fu_2022_p4 assign process. ///
always @ (ap_CS_fsm or i_4_reg_2018 or ap_reg_ppiten_pp5_it1 or exitcond9_reg_5697 or i_4_mid2_reg_5719)
begin
if (((ap_const_logic_1 == ap_reg_ppiten_pp5_it1) & (ap_const_lv1_0 == exitcond9_reg_5697) & (ap_ST_pp5_stg0_fsm_22 == ap_CS_fsm))) begin
i_4_phi_fu_2022_p4 = i_4_mid2_reg_5719;
end else begin
i_4_phi_fu_2022_p4 = i_4_reg_2018;
end
end
/// i_5_phi_fu_2077_p4 assign process. ///
always @ (ap_CS_fsm or i_5_reg_2073 or ap_reg_ppiten_pp7_it1 or exitcond12_reg_5924 or i_5_mid2_reg_5946)
begin
if (((ap_const_logic_1 == ap_reg_ppiten_pp7_it1) & (ap_const_lv1_0 == exitcond12_reg_5924) & (ap_ST_pp7_stg0_fsm_31 == ap_CS_fsm))) begin
i_5_phi_fu_2077_p4 = i_5_mid2_reg_5946;
end else begin
i_5_phi_fu_2077_p4 = i_5_reg_2073;
end
end
/// i_6_phi_fu_2124_p6 assign process. ///
always @ (ap_CS_fsm or i_6_reg_2120 or exitcond_reg_6132 or ap_reg_ppiten_pp8_it1 or i_6_mid2_reg_6153)
begin
if (((ap_ST_pp8_stg0_fsm_40 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp8_it1) & (ap_const_lv1_0 == exitcond_reg_6132))) begin
i_6_phi_fu_2124_p6 = i_6_mid2_reg_6153;
end else begin
i_6_phi_fu_2124_p6 = i_6_reg_2120;
end
end
/// i_phi_fu_1890_p4 assign process. ///
always @ (ap_CS_fsm or i_reg_1886 or ap_reg_ppiten_pp0_it1 or exitcond1_reg_5171 or tmp_5_reg_5175)
begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (exitcond1_reg_5171 == ap_const_lv1_0))) begin
i_phi_fu_1890_p4 = tmp_5_reg_5175;
end else begin
i_phi_fu_1890_p4 = i_reg_1886;
end
end
/// indvar3_phi_fu_1923_p4 assign process. ///
always @ (ap_CS_fsm or indvar3_reg_1919 or ap_reg_ppiten_pp1_it1 or exitcond3_reg_5195 or indvar_next3_reg_5252)
begin
if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_const_lv1_0 == exitcond3_reg_5195) & (ap_ST_pp1_stg0_fsm_4 == ap_CS_fsm))) begin
indvar3_phi_fu_1923_p4 = indvar_next3_reg_5252;
end else begin
indvar3_phi_fu_1923_p4 = indvar3_reg_1919;
end
end
/// indvar4_phi_fu_2088_p4 assign process. ///
always @ (ap_CS_fsm or indvar4_reg_2084 or ap_reg_ppiten_pp7_it1 or exitcond12_reg_5924 or indvar_next5_reg_5977)
begin
if (((ap_const_logic_1 == ap_reg_ppiten_pp7_it1) & (ap_const_lv1_0 == exitcond12_reg_5924) & (ap_ST_pp7_stg0_fsm_31 == ap_CS_fsm))) begin
indvar4_phi_fu_2088_p4 = indvar_next5_reg_5977;
end else begin
indvar4_phi_fu_2088_p4 = indvar4_reg_2084;
end
end
/// indvar6_phi_fu_1978_p4 assign process. ///
always @ (ap_CS_fsm or indvar6_reg_1974 or ap_reg_ppiten_pp3_it1 or exitcond6_reg_5446 or indvar_next6_reg_5503)
begin
if (((ap_const_logic_1 == ap_reg_ppiten_pp3_it1) & (ap_const_lv1_0 == exitcond6_reg_5446) & (ap_ST_pp3_stg0_fsm_13 == ap_CS_fsm))) begin
indvar6_phi_fu_1978_p4 = indvar_next6_reg_5503;
end else begin
indvar6_phi_fu_1978_p4 = indvar6_reg_1974;
end
end
/// indvar9_phi_fu_2033_p4 assign process. ///
always @ (ap_CS_fsm or indvar9_reg_2029 or ap_reg_ppiten_pp5_it1 or exitcond9_reg_5697 or indvar_next9_reg_5750)
begin
if (((ap_const_logic_1 == ap_reg_ppiten_pp5_it1) & (ap_const_lv1_0 == exitcond9_reg_5697) & (ap_ST_pp5_stg0_fsm_22 == ap_CS_fsm))) begin
indvar9_phi_fu_2033_p4 = indvar_next9_reg_5750;
end else begin
indvar9_phi_fu_2033_p4 = indvar9_reg_2029;
end
end
/// indvar_flatten1_phi_fu_1956_p4 assign process. ///
always @ (ap_CS_fsm or indvar_flatten1_reg_1952 or ap_reg_ppiten_pp3_it1 or exitcond6_reg_5446 or indvar_flatten_next1_reg_5450)
begin
if (((ap_const_logic_1 == ap_reg_ppiten_pp3_it1) & (ap_const_lv1_0 == exitcond6_reg_5446) & (ap_ST_pp3_stg0_fsm_13 == ap_CS_fsm))) begin
indvar_flatten1_phi_fu_1956_p4 = indvar_flatten_next1_reg_5450;
end else begin
indvar_flatten1_phi_fu_1956_p4 = indvar_flatten1_reg_1952;
end
end
/// indvar_flatten2_phi_fu_2011_p4 assign process. ///
always @ (ap_CS_fsm or indvar_flatten2_reg_2007 or ap_reg_ppiten_pp5_it1 or exitcond9_reg_5697 or indvar_flatten_next2_reg_5701)
begin
if (((ap_const_logic_1 == ap_reg_ppiten_pp5_it1) & (ap_const_lv1_0 == exitcond9_reg_5697) & (ap_ST_pp5_stg0_fsm_22 == ap_CS_fsm))) begin
indvar_flatten2_phi_fu_2011_p4 = indvar_flatten_next2_reg_5701;
end else begin
indvar_flatten2_phi_fu_2011_p4 = indvar_flatten2_reg_2007;
end
end
/// indvar_flatten3_phi_fu_2066_p4 assign process. ///
always @ (ap_CS_fsm or indvar_flatten3_reg_2062 or ap_reg_ppiten_pp7_it1 or exitcond12_reg_5924 or indvar_flatten_next3_reg_5928)
begin
if (((ap_const_logic_1 == ap_reg_ppiten_pp7_it1) & (ap_const_lv1_0 == exitcond12_reg_5924) & (ap_ST_pp7_stg0_fsm_31 == ap_CS_fsm))) begin
indvar_flatten3_phi_fu_2066_p4 = indvar_flatten_next3_reg_5928;
end else begin
indvar_flatten3_phi_fu_2066_p4 = indvar_flatten3_reg_2062;
end
end
/// indvar_flatten4_phi_fu_2110_p6 assign process. ///
always @ (ap_CS_fsm or indvar_flatten4_reg_2106 or exitcond_reg_6132 or ap_reg_ppiten_pp8_it1 or indvar_flatten_next4_reg_6136)
begin
if (((ap_ST_pp8_stg0_fsm_40 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp8_it1) & (ap_const_lv1_0 == exitcond_reg_6132))) begin
indvar_flatten4_phi_fu_2110_p6 = indvar_flatten_next4_reg_6136;
end else begin
indvar_flatten4_phi_fu_2110_p6 = indvar_flatten4_reg_2106;
end
end
/// indvar_flatten_phi_fu_1901_p4 assign process. ///
always @ (ap_CS_fsm or indvar_flatten_reg_1897 or ap_reg_ppiten_pp1_it1 or exitcond3_reg_5195 or indvar_flatten_next_reg_5199)
begin
if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_const_lv1_0 == exitcond3_reg_5195) & (ap_ST_pp1_stg0_fsm_4 == ap_CS_fsm))) begin
indvar_flatten_phi_fu_1901_p4 = indvar_flatten_next_reg_5199;
end else begin
indvar_flatten_phi_fu_1901_p4 = indvar_flatten_reg_1897;
end
end
/// indvar_phi_fu_2138_p6 assign process. ///
always @ (ap_CS_fsm or indvar_reg_2134 or exitcond_reg_6132 or ap_reg_ppiten_pp8_it1 or indvar_next_reg_6186)
begin
if (((ap_ST_pp8_stg0_fsm_40 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp8_it1) & (ap_const_lv1_0 == exitcond_reg_6132))) begin
indvar_phi_fu_2138_p6 = indvar_next_reg_6186;
end else begin
indvar_phi_fu_2138_p6 = indvar_reg_2134;
end
end
/// j_1_phi_fu_1967_p4 assign process. ///
always @ (ap_CS_fsm or j_1_reg_1963 or ap_reg_ppiten_pp3_it1 or exitcond6_reg_5446 or j_1_mid2_reg_5467)
begin
if (((ap_const_logic_1 == ap_reg_ppiten_pp3_it1) & (ap_const_lv1_0 == exitcond6_reg_5446) & (ap_ST_pp3_stg0_fsm_13 == ap_CS_fsm))) begin
j_1_phi_fu_1967_p4 = j_1_mid2_reg_5467;
end else begin
j_1_phi_fu_1967_p4 = j_1_reg_1963;
end
end
/// j_2_phi_fu_2000_p4 assign process. ///
always @ (ap_CS_fsm or j_2_reg_1996 or ap_reg_ppiten_pp4_it1 or exitcond7_reg_5678 or tmp_49_reg_5682)
begin
if (((ap_ST_pp4_stg0_fsm_21 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp4_it1) & (ap_const_lv1_0 == exitcond7_reg_5678))) begin
j_2_phi_fu_2000_p4 = tmp_49_reg_5682;
end else begin
j_2_phi_fu_2000_p4 = j_2_reg_1996;
end
end
/// j_3_phi_fu_2044_p4 assign process. ///
always @ (ap_CS_fsm or j_3_reg_2040 or ap_reg_ppiten_pp5_it1 or exitcond9_reg_5697 or tmp_121_reg_5875)
begin
if (((ap_const_logic_1 == ap_reg_ppiten_pp5_it1) & (ap_const_lv1_0 == exitcond9_reg_5697) & (ap_ST_pp5_stg0_fsm_22 == ap_CS_fsm))) begin
j_3_phi_fu_2044_p4 = tmp_121_reg_5875;
end else begin
j_3_phi_fu_2044_p4 = j_3_reg_2040;
end
end
/// j_4_phi_fu_2055_p4 assign process. ///
always @ (ap_CS_fsm or j_4_reg_2051 or ap_reg_ppiten_pp6_it1 or exitcond10_reg_5905 or tmp_88_reg_5909)
begin
if (((ap_ST_pp6_stg0_fsm_30 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp6_it1) & (ap_const_lv1_0 == exitcond10_reg_5905))) begin
j_4_phi_fu_2055_p4 = tmp_88_reg_5909;
end else begin
j_4_phi_fu_2055_p4 = j_4_reg_2051;
end
end
/// j_5_phi_fu_2099_p4 assign process. ///
always @ (ap_CS_fsm or j_5_reg_2095 or ap_reg_ppiten_pp7_it1 or exitcond12_reg_5924 or tmp_157_reg_6102)
begin
if (((ap_const_logic_1 == ap_reg_ppiten_pp7_it1) & (ap_const_lv1_0 == exitcond12_reg_5924) & (ap_ST_pp7_stg0_fsm_31 == ap_CS_fsm))) begin
j_5_phi_fu_2099_p4 = tmp_157_reg_6102;
end else begin
j_5_phi_fu_2099_p4 = j_5_reg_2095;
end
end
/// j_6_phi_fu_2152_p6 assign process. ///
always @ (ap_CS_fsm or j_6_reg_2148 or exitcond_reg_6132 or ap_reg_ppiten_pp8_it1 or tmp_189_reg_6358)
begin
if (((ap_ST_pp8_stg0_fsm_40 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp8_it1) & (ap_const_lv1_0 == exitcond_reg_6132))) begin
j_6_phi_fu_2152_p6 = tmp_189_reg_6358;
end else begin
j_6_phi_fu_2152_p6 = j_6_reg_2148;
end
end
/// j_phi_fu_1912_p4 assign process. ///
always @ (ap_CS_fsm or j_reg_1908 or ap_reg_ppiten_pp1_it1 or exitcond3_reg_5195 or j_mid2_reg_5216)
begin
if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_const_lv1_0 == exitcond3_reg_5195) & (ap_ST_pp1_stg0_fsm_4 == ap_CS_fsm))) begin
j_phi_fu_1912_p4 = j_mid2_reg_5216;
end else begin
j_phi_fu_1912_p4 = j_reg_1908;
end
end
assign a_addr101_fu_2565_p1 = tmp_16_trn_cast_fu_2541_p1[6:0];
assign a_addr102_fu_2631_p1 = tmp_20_trn_cast_fu_2607_p1[6:0];
assign a_addr103_fu_2745_p1 = tmp_24_trn_cast_fu_2721_p1[6:0];
assign a_addr104_fu_2799_p1 = tmp_28_trn_cast_fu_2775_p1[6:0];
assign a_addr105_fu_2852_p1 = tmp_32_trn_cast_fu_2828_p1[6:0];
assign a_addr106_fu_2901_p1 = tmp_36_trn_cast_fu_2882_p1[6:0];
assign a_addr107_fu_2950_p1 = tmp_40_trn_cast_fu_2931_p1[6:0];
assign a_addr108_fu_3135_p2 = (b_addr53_reg_5498 | tmp_46_trn_cast1_fu_3125_p4);
assign a_addr109_fu_3140_p5 = {{a_addr108_fu_3135_p2}, {tmp_46_trn_cast_fu_3121_p1[32'd5 : 32'd0]}};
assign a_addr110_fu_3200_p2 = (b_addr54_fu_3186_p1 | tmp_46_trn_cast2_fu_3190_p4);
assign a_addr111_fu_3206_p5 = {{a_addr110_fu_3200_p2}, {tmp_46_trn_cast_fu_3121_p1[32'd5 : 32'd0]}};
assign a_addr112_fu_3266_p2 = (b_addr55_fu_3252_p1 | tmp_46_trn_cast3_fu_3256_p4);
assign a_addr113_fu_3322_p5 = {{a_addr112_reg_5548}, {tmp_46_trn_cast_reg_5508[32'd5 : 32'd0]}};
assign a_addr114_fu_3370_p2 = (b_addr56_fu_3366_p1 | tmp_46_trn_cast4_reg_5553);
assign a_addr115_fu_3375_p5 = {{a_addr114_fu_3370_p2}, {tmp_46_trn_cast_reg_5508[32'd5 : 32'd0]}};
assign a_addr116_fu_3424_p2 = (b_addr57_fu_3420_p1 | tmp_46_trn_cast5_reg_5558);
assign a_addr117_fu_3429_p5 = {{a_addr116_reg_5608}, {tmp_46_trn_cast_reg_5508[32'd5 : 32'd0]}};
assign a_addr118_fu_3477_p2 = (b_addr58_fu_3473_p1 | tmp_46_trn_cast6_reg_5563);
assign a_addr119_fu_3482_p5 = {{a_addr118_fu_3477_p2}, {tmp_46_trn_cast_reg_5508[32'd5 : 32'd0]}};
assign a_addr11_cast_fu_2731_p1 = {{1{1'b0}}, {a_addr11_fu_2725_p2}};
assign a_addr11_fu_2725_p2 = tmp_24_trn_cast_fu_2721_p1 << ap_const_lv13_6;
assign a_addr120_fu_3526_p2 = (b_addr59_fu_3522_p1 | tmp_46_trn_cast7_reg_5568);
assign a_addr121_fu_3531_p5 = {{a_addr120_fu_3526_p2}, {tmp_46_trn_cast_reg_5508[32'd5 : 32'd0]}};
assign a_addr122_fu_3575_p2 = (b_addr60_fu_3571_p1 | tmp_46_trn_cast8_reg_5573);
assign a_addr123_fu_3580_p5 = {{a_addr122_fu_3575_p2}, {tmp_46_trn_cast_reg_5508[32'd5 : 32'd0]}};
assign a_addr12_fu_2735_p2 = (a_addr11_cast_fu_2731_p1 + tmp_6_trn_cast_reg_5226);
assign a_addr13_fu_5103_p2 = (a_addr18_cast_fu_5089_p1 + tmp_180_trn_cast_reg_6233);
assign a_addr14_cast_fu_2785_p1 = {{1{1'b0}}, {a_addr14_fu_2779_p2}};
assign a_addr14_fu_2779_p2 = tmp_28_trn_cast_fu_2775_p1 << ap_const_lv13_6;
assign a_addr15_fu_2789_p2 = (a_addr14_cast_fu_2785_p1 + tmp_6_trn_cast_reg_5226);
assign a_addr17_cast_fu_2838_p1 = {{1{1'b0}}, {a_addr17_fu_2832_p2}};
assign a_addr17_fu_2832_p2 = tmp_32_trn_cast_fu_2828_p1 << ap_const_lv13_6;
assign a_addr18_cast_fu_5089_p1 = {{1{1'b0}}, {a_addr18_fu_5083_p2}};
assign a_addr18_fu_5083_p2 = tmp_172_trn_cast_fu_5079_p1 << ap_const_lv13_6;
assign a_addr19_fu_5093_p2 = (a_addr18_cast_fu_5089_p1 + tmp_176_trn_cast_reg_6191);
assign a_addr1_fu_5123_p2 = (a_addr18_cast_fu_5089_p1 + tmp_188_trn_cast_reg_6317);
assign a_addr20_fu_2842_p2 = (a_addr17_cast_fu_2838_p1 + tmp_6_trn_cast_reg_5226);
assign a_addr21_cast_fu_2892_p1 = {{1{1'b0}}, {a_addr21_fu_2886_p2}};
assign a_addr21_fu_2886_p2 = tmp_36_trn_cast_fu_2882_p1 << ap_const_lv13_6;
assign a_addr22_fu_5075_p2 = (a_addr45_cast_reg_6741 + tmp_188_trn_cast_reg_6317);
assign a_addr24_cast_fu_2941_p1 = {{1{1'b0}}, {a_addr24_fu_2935_p2}};
assign a_addr24_fu_2935_p2 = tmp_40_trn_cast_fu_2931_p1 << ap_const_lv13_6;
assign a_addr26_fu_5066_p2 = (a_addr45_cast_reg_6741 + tmp_186_trn_cast_reg_6296);
assign a_addr27_fu_4405_p2 = tmp_158_trn_cast_fu_4397_p1 << ap_const_lv13_6;
assign a_addr28_fu_4415_p2 = (a_addr63_cast_fu_4411_p1 + tmp_174_trn_cast_fu_4401_p1);
assign a_addr29_fu_4449_p2 = (a_addr63_cast_reg_6165 + tmp_176_trn_cast_fu_4445_p1);
assign a_addr2_cast_fu_2462_p1 = {{1{1'b0}}, {a_addr2_fu_2456_p2}};
assign a_addr2_fu_2456_p2 = tmp_12_trn_cast_fu_2448_p1 << ap_const_lv13_6;
assign a_addr30_fu_5057_p2 = (a_addr45_cast_reg_6741 + tmp_184_trn_cast_reg_6275);
assign a_addr31_fu_4468_p2 = (a_addr63_cast_reg_6165 + tmp_178_trn_cast_fu_4464_p1);
assign a_addr32_fu_4487_p2 = (a_addr63_cast_reg_6165 + tmp_180_trn_cast_fu_4483_p1);
assign a_addr33_fu_4506_p2 = (a_addr63_cast_reg_6165 + tmp_182_trn_cast_fu_4502_p1);
assign a_addr34_fu_5043_p2 = (a_addr45_cast_reg_6741 + tmp_182_trn_cast_reg_6254);
assign a_addr35_fu_4525_p2 = (a_addr63_cast_reg_6165 + tmp_184_trn_cast_fu_4521_p1);
assign a_addr36_fu_4544_p2 = (a_addr63_cast_reg_6165 + tmp_186_trn_cast_fu_4540_p1);
assign a_addr37_cast_fu_3684_p1 = {{1{1'b0}}, {a_addr37_fu_3678_p2}};
assign a_addr37_fu_3678_p2 = tmp_83_trn_cast_fu_3670_p1 << ap_const_lv13_6;
assign a_addr38_fu_5034_p2 = (a_addr45_cast_reg_6741 + tmp_180_trn_cast_reg_6233);
assign a_addr39_fu_3688_p2 = (a_addr37_cast_fu_3684_p1 + tmp_90_trn_cast_fu_3674_p1);
assign a_addr3_fu_2466_p2 = (a_addr2_cast_fu_2462_p1 + tmp_6_trn_cast_fu_2452_p1);
assign a_addr40_fu_3759_p2 = (a_addr37_cast_reg_5729 + tmp_94_trn_cast_fu_3755_p1);
assign a_addr41_fu_3789_p2 = (a_addr37_cast_reg_5729 + tmp_98_trn_cast_fu_3785_p1);
assign a_addr42_fu_5024_p2 = (a_addr45_cast_fu_5010_p1 + tmp_178_trn_cast_reg_6212);
assign a_addr43_fu_3825_p2 = (a_addr37_cast_reg_5729 + tmp_102_trn_cast_fu_3821_p1);
assign a_addr44_fu_3854_p2 = (a_addr37_cast_reg_5729 + tmp_106_trn_cast_fu_3850_p1);
assign a_addr45_cast_fu_5010_p1 = {{1{1'b0}}, {a_addr45_fu_5004_p2}};
assign a_addr45_fu_5004_p2 = tmp_170_trn_cast_fu_5000_p1 << ap_const_lv13_6;
assign a_addr46_fu_5014_p2 = (a_addr45_cast_fu_5010_p1 + tmp_176_trn_cast_reg_6191);
assign a_addr47_fu_3890_p2 = (a_addr37_cast_reg_5729 + tmp_110_trn_cast_fu_3886_p1);
assign a_addr48_fu_3956_p2 = (ap_reg_ppstg_a_addr37_cast_reg_5729_pp5_it1 + tmp_114_trn_cast_fu_3953_p1);
assign a_addr49_fu_4986_p2 = (a_addr72_cast_reg_6661 + tmp_188_trn_cast_reg_6317);
assign a_addr50_fu_3969_p2 = (ap_reg_ppstg_a_addr37_cast_reg_5729_pp5_it1 + tmp_118_trn_cast_fu_3966_p1);
assign a_addr51_cast_fu_4110_p1 = {{1{1'b0}}, {a_addr51_fu_4104_p2}};
assign a_addr51_fu_4104_p2 = tmp_124_trn_cast_fu_4100_p1 << ap_const_lv12_6;
assign a_addr52_fu_4114_p2 = (a_addr51_cast_fu_4110_p1 + tmp_126_trn_cast1_fu_4097_p1);
assign a_addr53_fu_4977_p2 = (a_addr72_cast_reg_6661 + tmp_186_trn_cast_reg_6296);
assign a_addr54_fu_4148_p2 = (a_addr51_cast_fu_4110_p1 + tmp_130_trn_cast1_fu_4130_p1);
assign a_addr55_fu_4181_p2 = (a_addr51_cast_reg_5982 + tmp_134_trn_cast1_fu_4178_p1);
assign a_addr56_fu_4214_p2 = (a_addr51_cast_reg_5982 + tmp_138_trn_cast1_fu_4196_p1);
assign a_addr57_fu_4968_p2 = (a_addr72_cast_reg_6661 + tmp_184_trn_cast_reg_6275);
assign a_addr58_fu_4246_p2 = (a_addr51_cast_reg_5982 + tmp_142_trn_cast1_fu_4243_p1);
assign a_addr59_fu_4279_p2 = (a_addr51_cast_reg_5982 + tmp_146_trn_cast1_fu_4261_p1);
assign a_addr5_cast_fu_2551_p1 = {{1{1'b0}}, {a_addr5_fu_2545_p2}};
assign a_addr5_fu_2545_p2 = tmp_16_trn_cast_fu_2541_p1 << ap_const_lv13_6;
assign a_addr60_fu_4298_p2 = (a_addr51_cast_reg_5982 + tmp_150_trn_cast1_fu_4294_p1);
assign a_addr61_fu_4959_p2 = (a_addr72_cast_reg_6661 + tmp_182_trn_cast_reg_6254);
assign a_addr62_fu_4317_p2 = (a_addr51_cast_reg_5982 + tmp_154_trn_cast1_fu_4313_p1);
assign a_addr63_cast_fu_4411_p1 = {{1{1'b0}}, {a_addr27_fu_4405_p2}};
assign a_addr63_fu_4568_p2 = (a_addr63_cast_reg_6165 + tmp_188_trn_cast_fu_4564_p1);
assign a_addr64_fu_4582_p2 = tmp_160_trn_cast_fu_4578_p1 << ap_const_lv13_6;
assign a_addr65_fu_4950_p2 = (a_addr72_cast_reg_6661 + tmp_180_trn_cast_reg_6233);
assign a_addr66_fu_4592_p2 = (a_addr77_cast_fu_4588_p1 + tmp_176_trn_cast_reg_6191);
assign a_addr67_fu_4607_p2 = (a_addr77_cast_reg_6338 + tmp_178_trn_cast_reg_6212);
assign a_addr68_fu_4616_p2 = (a_addr77_cast_reg_6338 + tmp_180_trn_cast_reg_6233);
assign a_addr69_fu_4941_p2 = (a_addr72_cast_reg_6661 + tmp_178_trn_cast_reg_6212);
assign a_addr6_fu_2555_p2 = (a_addr5_cast_fu_2551_p1 + tmp_6_trn_cast_reg_5226);
assign a_addr70_fu_4625_p2 = (a_addr77_cast_reg_6338 + tmp_182_trn_cast_reg_6254);
assign a_addr71_fu_4634_p2 = (a_addr77_cast_reg_6338 + tmp_184_trn_cast_reg_6275);
assign a_addr72_cast_fu_4927_p1 = {{1{1'b0}}, {a_addr72_fu_4921_p2}};
assign a_addr72_fu_4921_p2 = tmp_168_trn_cast_fu_4917_p1 << ap_const_lv13_6;
assign a_addr73_fu_4931_p2 = (a_addr72_cast_fu_4927_p1 + tmp_176_trn_cast_reg_6191);
assign a_addr74_fu_4643_p2 = (a_addr77_cast_reg_6338 + tmp_186_trn_cast_reg_6296);
assign a_addr75_fu_4652_p2 = (a_addr77_cast_reg_6338 + tmp_188_trn_cast_reg_6317);
assign a_addr76_fu_4908_p2 = (a_addr99_cast_reg_6582 + tmp_188_trn_cast_reg_6317);
assign a_addr77_cast_fu_4588_p1 = {{1{1'b0}}, {a_addr64_fu_4582_p2}};
assign a_addr77_fu_4670_p2 = tmp_162_trn_cast_fu_4666_p1 << ap_const_lv13_6;
assign a_addr78_fu_4680_p2 = (a_addr87_cast_fu_4676_p1 + tmp_176_trn_cast_reg_6191);
assign a_addr79_fu_4690_p2 = (a_addr87_cast_fu_4676_p1 + tmp_178_trn_cast_reg_6212);
assign a_addr7_fu_5113_p2 = (a_addr18_cast_fu_5089_p1 + tmp_184_trn_cast_reg_6275);
assign a_addr80_fu_4894_p2 = (a_addr99_cast_reg_6582 + tmp_186_trn_cast_reg_6296);
assign a_addr81_fu_4700_p2 = (a_addr87_cast_reg_6423 + tmp_180_trn_cast_reg_6233);
assign a_addr82_fu_4709_p2 = (a_addr87_cast_reg_6423 + tmp_182_trn_cast_reg_6254);
assign a_addr83_fu_4718_p2 = (a_addr87_cast_reg_6423 + tmp_184_trn_cast_reg_6275);
assign a_addr84_fu_4885_p2 = (a_addr99_cast_reg_6582 + tmp_184_trn_cast_reg_6275);
assign a_addr85_fu_4727_p2 = (a_addr87_cast_reg_6423 + tmp_186_trn_cast_reg_6296);
assign a_addr86_fu_4741_p2 = (a_addr87_cast_reg_6423 + tmp_188_trn_cast_reg_6317);
assign a_addr87_cast_fu_4676_p1 = {{1{1'b0}}, {a_addr77_fu_4670_p2}};
assign a_addr87_fu_4754_p2 = tmp_164_trn_cast_fu_4750_p1 << ap_const_lv13_6;
assign a_addr88_fu_4876_p2 = (a_addr99_cast_reg_6582 + tmp_182_trn_cast_reg_6254);
assign a_addr89_fu_4764_p2 = (a_addr98_cast_fu_4760_p1 + tmp_176_trn_cast_reg_6191);
assign a_addr8_cast_fu_2617_p1 = {{1{1'b0}}, {a_addr8_fu_2611_p2}};
assign a_addr8_fu_2611_p2 = tmp_20_trn_cast_fu_2607_p1 << ap_const_lv13_6;
assign a_addr90_fu_4774_p2 = (a_addr98_cast_reg_6502 + tmp_178_trn_cast_reg_6212);
assign a_addr91_fu_4783_p2 = (a_addr98_cast_reg_6502 + tmp_180_trn_cast_reg_6233);
assign a_addr92_fu_4867_p2 = (a_addr99_cast_reg_6582 + tmp_180_trn_cast_reg_6233);
assign a_addr93_fu_4792_p2 = (a_addr98_cast_reg_6502 + tmp_182_trn_cast_reg_6254);
assign a_addr94_fu_4801_p2 = (a_addr98_cast_reg_6502 + tmp_184_trn_cast_reg_6275);
assign a_addr95_fu_4810_p2 = (a_addr98_cast_reg_6502 + tmp_186_trn_cast_reg_6296);
assign a_addr96_fu_4857_p2 = (a_addr99_cast_fu_4843_p1 + tmp_178_trn_cast_reg_6212);
assign a_addr97_fu_4819_p2 = (a_addr98_cast_reg_6502 + tmp_188_trn_cast_reg_6317);
assign a_addr98_cast_fu_4760_p1 = {{1{1'b0}}, {a_addr87_fu_4754_p2}};
assign a_addr98_fu_4837_p2 = tmp_166_trn_cast_fu_4833_p1 << ap_const_lv13_6;
assign a_addr99_cast_fu_4843_p1 = {{1{1'b0}}, {a_addr98_fu_4837_p2}};
assign a_addr99_fu_4847_p2 = (a_addr99_cast_fu_4843_p1 + tmp_176_trn_cast_reg_6191);
assign a_addr9_fu_2621_p2 = (a_addr8_cast_fu_2617_p1 + tmp_6_trn_cast_reg_5226);
assign a_addr_fu_2393_p2 = tmp_3_trn_cast_fu_2389_p1 << ap_const_lv13_6;
assign b_addr10_cast_fu_3083_p1 = {{1{1'b0}}, {b_addr10_fu_3077_p2}};
assign b_addr10_fu_3077_p2 = tmp_51_trn_cast_fu_3069_p1 << ap_const_lv13_6;
assign b_addr11_fu_3087_p1 = {{7{j_1_mid2_fu_3057_p3[6]}}, {j_1_mid2_fu_3057_p3}};
assign b_addr11_fu_3087_p2 = (b_addr10_cast_fu_3083_p1 + b_addr11_fu_3087_p1);
assign b_addr12_cast_fu_3172_p1 = {{1{1'b0}}, {b_addr12_fu_3166_p2}};
assign b_addr12_fu_3166_p2 = tmp_55_trn_cast_fu_3162_p1 << ap_const_lv13_6;
assign b_addr13_fu_3176_p2 = (b_addr12_cast_fu_3172_p1 + tmp_44_trn_cast_reg_5477);
assign b_addr14_cast_fu_3238_p1 = {{1{1'b0}}, {b_addr14_fu_3232_p2}};
assign b_addr14_fu_3232_p2 = tmp_59_trn_cast_fu_3228_p1 << ap_const_lv13_6;
assign b_addr15_fu_3242_p2 = (b_addr14_cast_fu_3238_p1 + tmp_44_trn_cast_reg_5477);
assign b_addr16_cast_fu_3352_p1 = {{1{1'b0}}, {b_addr16_fu_3346_p2}};
assign b_addr16_fu_3346_p2 = tmp_63_trn_cast_fu_3342_p1 << ap_const_lv13_6;
assign b_addr17_fu_3356_p2 = (b_addr16_cast_fu_3352_p1 + tmp_44_trn_cast_reg_5477);
assign b_addr18_cast_fu_3406_p1 = {{1{1'b0}}, {b_addr18_fu_3400_p2}};
assign b_addr18_fu_3400_p2 = tmp_67_trn_cast_fu_3396_p1 << ap_const_lv13_6;
assign b_addr19_fu_3410_p2 = (b_addr18_cast_fu_3406_p1 + tmp_44_trn_cast_reg_5477);
assign b_addr1_fu_2519_p5 = {{b_addr_fu_2514_p2}, {tmp_8_trn_cast_fu_2500_p1[32'd5 : 32'd0]}};
assign b_addr20_cast_fu_3459_p1 = {{1{1'b0}}, {b_addr20_fu_3453_p2}};
assign b_addr20_fu_3453_p2 = tmp_71_trn_cast_fu_3449_p1 << ap_const_lv13_6;
assign b_addr21_fu_3463_p2 = (b_addr20_cast_fu_3459_p1 + tmp_44_trn_cast_reg_5477);
assign b_addr22_cast_fu_3513_p1 = {{1{1'b0}}, {b_addr22_fu_3507_p2}};
assign b_addr22_fu_3507_p2 = tmp_75_trn_cast_fu_3503_p1 << ap_const_lv13_6;
assign b_addr24_cast_fu_3562_p1 = {{1{1'b0}}, {b_addr24_fu_3556_p2}};
assign b_addr24_fu_3556_p2 = tmp_79_trn_cast_fu_3552_p1 << ap_const_lv13_6;
assign b_addr26_cast_fu_3731_p1 = {{1{1'b0}}, {b_addr26_fu_3725_p2}};
assign b_addr26_fu_3725_p2 = tmp_85_trn_cast_fu_3721_p1 << ap_const_lv12_6;
assign b_addr27_fu_3735_p2 = (b_addr26_cast_fu_3731_p1 + tmp_90_trn_cast1_fu_3718_p1);
assign b_addr28_fu_3769_p2 = (b_addr26_cast_fu_3731_p1 + tmp_94_trn_cast1_fu_3751_p1);
assign b_addr29_fu_3802_p2 = (b_addr26_cast_reg_5755 + tmp_98_trn_cast1_fu_3799_p1);
assign b_addr2_fu_2579_p2 = (a_addr101_fu_2565_p1 | tmp_8_trn_cast2_fu_2569_p4);
assign b_addr30_fu_3835_p2 = (b_addr26_cast_reg_5755 + tmp_102_trn_cast1_fu_3817_p1);
assign b_addr31_fu_3867_p2 = (b_addr26_cast_reg_5755 + tmp_106_trn_cast1_fu_3864_p1);
assign b_addr32_fu_3900_p2 = (b_addr26_cast_reg_5755 + tmp_110_trn_cast1_fu_3882_p1);
assign b_addr33_fu_3919_p2 = (b_addr26_cast_reg_5755 + tmp_114_trn_cast1_fu_3915_p1);
assign b_addr34_fu_3938_p2 = (b_addr26_cast_reg_5755 + tmp_118_trn_cast1_fu_3934_p1);
assign b_addr35_fu_3994_p2 = (tmp_86_trn_cast_fu_3990_p1 + ap_const_lv13_FC0);
assign b_addr36_cast_fu_4063_p1 = {{1{b_addr36_fu_4057_p2[12]}}, {b_addr36_fu_4057_p2}};
assign b_addr36_fu_4057_p2 = tmp_122_trn_cast_fu_4049_p1 << ap_const_lv13_6;
assign b_addr37_fu_4067_p0 = {{1{b_addr36_fu_4057_p2[12]}}, {b_addr36_fu_4057_p2}};
assign b_addr37_fu_4067_p2 = (b_addr37_fu_4067_p0 + tmp_126_trn_cast_fu_4053_p1);
assign b_addr38_fu_4138_p2 = (b_addr36_cast_reg_5956 + tmp_130_trn_cast_fu_4134_p1);
assign b_addr39_fu_4168_p2 = (b_addr36_cast_reg_5956 + tmp_134_trn_cast_fu_4164_p1);
assign b_addr3_fu_2585_p5 = {{b_addr2_fu_2579_p2}, {tmp_8_trn_cast_fu_2500_p1[32'd5 : 32'd0]}};
assign b_addr40_fu_4204_p2 = (b_addr36_cast_reg_5956 + tmp_138_trn_cast_fu_4200_p1);
assign b_addr41_fu_4233_p2 = (b_addr36_cast_reg_5956 + tmp_142_trn_cast_fu_4229_p1);
assign b_addr42_fu_4269_p2 = (b_addr36_cast_reg_5956 + tmp_146_trn_cast_fu_4265_p1);
assign b_addr43_fu_4335_p2 = (ap_reg_ppstg_b_addr36_cast_reg_5956_pp7_it1 + tmp_150_trn_cast_fu_4332_p1);
assign b_addr44_fu_4348_p2 = (ap_reg_ppstg_b_addr36_cast_reg_5956_pp7_it1 + tmp_154_trn_cast_fu_4345_p1);
assign b_addr45_fu_2856_p2 = (a_addr105_fu_2852_p1 | tmp_8_trn_cast6_reg_5312);
assign b_addr46_fu_2861_p5 = {{b_addr45_fu_2856_p2}, {tmp_8_trn_cast_reg_5257[32'd5 : 32'd0]}};
assign b_addr47_fu_2905_p2 = (a_addr106_fu_2901_p1 | tmp_8_trn_cast7_reg_5317);
assign b_addr48_fu_2910_p5 = {{b_addr47_fu_2905_p2}, {tmp_8_trn_cast_reg_5257[32'd5 : 32'd0]}};
assign b_addr49_fu_2954_p2 = (a_addr107_fu_2950_p1 | tmp_8_trn_cast8_reg_5322);
assign b_addr4_fu_2645_p2 = (a_addr102_fu_2631_p1 | tmp_8_trn_cast3_fu_2635_p4);
assign b_addr50_fu_2959_p5 = {{b_addr49_fu_2954_p2}, {tmp_8_trn_cast_reg_5257[32'd5 : 32'd0]}};
assign b_addr51_fu_3004_p1 = tmp_9_trn_cast_fu_3000_p1[6:0];
assign b_addr52_fu_3008_p5 = {{b_addr51_fu_3004_p1}, {ap_const_lv13_3F[32'd5 : 32'd0]}};
assign b_addr54_fu_3186_p1 = tmp_55_trn_cast_fu_3162_p1[6:0];
assign b_addr55_fu_3252_p1 = tmp_59_trn_cast_fu_3228_p1[6:0];
assign b_addr56_fu_3366_p1 = tmp_63_trn_cast_fu_3342_p1[6:0];
assign b_addr57_fu_3420_p1 = tmp_67_trn_cast_fu_3396_p1[6:0];
assign b_addr58_fu_3473_p1 = tmp_71_trn_cast_fu_3449_p1[6:0];
assign b_addr59_fu_3522_p1 = tmp_75_trn_cast_fu_3503_p1[6:0];
assign b_addr5_fu_2701_p5 = {{b_addr4_reg_5297}, {tmp_8_trn_cast_reg_5257[32'd5 : 32'd0]}};
assign b_addr60_fu_3571_p1 = tmp_79_trn_cast_fu_3552_p1[6:0];
assign b_addr6_fu_2749_p2 = (a_addr103_fu_2745_p1 | tmp_8_trn_cast4_reg_5302);
assign b_addr7_fu_2754_p5 = {{b_addr6_fu_2749_p2}, {tmp_8_trn_cast_reg_5257[32'd5 : 32'd0]}};
assign b_addr8_fu_2803_p2 = (a_addr104_fu_2799_p1 | tmp_8_trn_cast5_reg_5307);
assign b_addr9_fu_2808_p5 = {{b_addr8_reg_5357}, {tmp_8_trn_cast_reg_5257[32'd5 : 32'd0]}};
assign b_addr_fu_2514_p2 = (a_addr100_reg_5247 | tmp_8_trn_cast1_fu_2504_p4);
assign exitcond10_fu_3978_p2 = (j_4_phi_fu_2055_p4 == ap_const_lv7_40? 1'b1: 1'b0);
assign exitcond11_fu_3638_p2 = (indvar9_phi_fu_2033_p4 == ap_const_lv4_8? 1'b1: 1'b0);
assign exitcond12_fu_4005_p2 = (indvar_flatten3_phi_fu_2066_p4 == ap_const_lv9_1F8? 1'b1: 1'b0);
assign exitcond13_fu_4017_p2 = (indvar4_phi_fu_2088_p4 == ap_const_lv4_8? 1'b1: 1'b0);
assign exitcond1_fu_2377_p2 = (i_phi_fu_1890_p4 == ap_const_lv7_40? 1'b1: 1'b0);
assign exitcond2_fu_4369_p2 = (indvar_phi_fu_2138_p6 == ap_const_lv4_8? 1'b1: 1'b0);
assign exitcond3_fu_2404_p2 = (indvar_flatten_phi_fu_1901_p4 == ap_const_lv9_1F8? 1'b1: 1'b0);
assign exitcond4_fu_2988_p2 = (i_2_phi_fu_1945_p4 == ap_const_lv7_40? 1'b1: 1'b0);
assign exitcond5_fu_2416_p2 = (indvar3_phi_fu_1923_p4 == ap_const_lv4_8? 1'b1: 1'b0);
assign exitcond6_fu_3025_p2 = (indvar_flatten1_phi_fu_1956_p4 == ap_const_lv9_1F8? 1'b1: 1'b0);
assign exitcond7_fu_3609_p2 = (j_2_phi_fu_2000_p4 == ap_const_lv7_40? 1'b1: 1'b0);
assign exitcond8_fu_3037_p2 = (indvar6_phi_fu_1978_p4 == ap_const_lv4_8? 1'b1: 1'b0);
assign exitcond9_fu_3626_p2 = (indvar_flatten2_phi_fu_2011_p4 == ap_const_lv9_1F8? 1'b1: 1'b0);
assign exitcond_fu_4357_p2 = (indvar_flatten4_phi_fu_2110_p6 == ap_const_lv7_40? 1'b1: 1'b0);
assign grp_fu_2163_ce = ap_const_logic_1;
assign grp_fu_2167_ce = ap_const_logic_1;
assign i_1_mid2_fu_2422_p3 = ((exitcond5_fu_2416_p2)? ap_const_lv7_0: i_1_phi_fu_1934_p4);
assign i_3_mid2_fu_3043_p3 = ((exitcond8_fu_3037_p2)? ap_const_lv7_0: i_3_phi_fu_1989_p4);
assign i_4_mid2_fu_3658_p3 = ((exitcond11_fu_3638_p2)? tmp_89_dup_fu_3652_p2: i_4_phi_fu_2022_p4);
assign i_5_mid2_fu_4037_p3 = ((exitcond13_fu_4017_p2)? tmp_125_dup_fu_4031_p2: i_5_phi_fu_2077_p4);
assign i_6_mid2_fu_4389_p3 = ((exitcond2_fu_4369_p2)? tmp_173_dup_fu_4383_p2: i_6_phi_fu_2124_p6);
assign indvar3_op_fu_2481_p2 = (indvar3_phi_fu_1923_p4 + ap_const_lv4_1);
assign indvar4_op_fu_4078_p2 = (indvar4_phi_fu_2088_p4 + ap_const_lv4_1);
assign indvar6_op_fu_3102_p2 = (indvar6_phi_fu_1978_p4 + ap_const_lv4_1);
assign indvar9_op_fu_3699_p2 = (indvar9_phi_fu_2033_p4 + ap_const_lv4_1);
assign indvar_op_fu_4426_p2 = (indvar_phi_fu_2138_p6 + ap_const_lv4_1);
assign j_1_mid2_fu_3057_p3 = ((exitcond8_fu_3037_p2)? tmp_50_dup_fu_3051_p2: j_1_phi_fu_1967_p4);
assign j_3_mid2_fu_3644_p3 = ((exitcond11_fu_3638_p2)? ap_const_lv7_0: j_3_phi_fu_2044_p4);
assign j_5_mid2_fu_4023_p3 = ((exitcond13_fu_4017_p2)? ap_const_lv7_0: j_5_phi_fu_2099_p4);
assign j_6_mid2_fu_4375_p3 = ((exitcond2_fu_4369_p2)? ap_const_lv7_0: j_6_phi_fu_2152_p6);
assign j_mid2_fu_2436_p3 = ((exitcond5_fu_2416_p2)? tmp_11_dup_fu_2430_p2: j_phi_fu_1912_p4);
assign or_cond_fu_2365_p2 = (tmp_fu_2353_p2 & tmp_1_fu_2359_p2);
assign tmp_101_fu_3812_p2 = (j_3_mid2_reg_5706 | ap_const_lv7_3);
assign tmp_102_fu_3493_p1 = {{51{1'b0}}, {a_addr119_fu_3482_p5}};
assign tmp_102_trn_cast1_fu_3817_p1 = {{6{1'b0}}, {tmp_101_fu_3812_p2}};
assign tmp_102_trn_cast_fu_3821_p1 = {{7{1'b0}}, {tmp_101_fu_3812_p2}};
assign tmp_105_fu_3845_p2 = (j_3_mid2_reg_5706 | ap_const_lv7_4);
assign tmp_106_fu_3601_p1 = {{50{b_addr23_reg_5633[13]}}, {b_addr23_reg_5633}};
assign tmp_106_trn_cast1_fu_3864_p1 = {{6{1'b0}}, {tmp_105_reg_5820}};
assign tmp_106_trn_cast_fu_3850_p1 = {{7{1'b0}}, {tmp_105_fu_3845_p2}};
assign tmp_109_fu_3877_p2 = (j_3_mid2_reg_5706 | ap_const_lv7_5);
assign tmp_110_fu_3542_p1 = {{51{1'b0}}, {a_addr121_fu_3531_p5}};
assign tmp_110_trn_cast1_fu_3882_p1 = {{6{1'b0}}, {tmp_109_fu_3877_p2}};
assign tmp_110_trn_cast_fu_3886_p1 = {{7{1'b0}}, {tmp_109_fu_3877_p2}};
assign tmp_113_fu_3910_p2 = (j_3_mid2_reg_5706 | ap_const_lv7_6);
assign tmp_114_fu_3605_p1 = {{50{b_addr25_reg_5643[13]}}, {b_addr25_reg_5643}};
assign tmp_114_trn_cast1_fu_3915_p1 = {{6{1'b0}}, {tmp_113_fu_3910_p2}};
assign tmp_114_trn_cast_fu_3953_p1 = {{7{1'b0}}, {tmp_113_reg_5855}};
assign tmp_117_fu_3929_p2 = (j_3_mid2_reg_5706 | ap_const_lv7_7);
assign tmp_118_fu_3591_p1 = {{51{1'b0}}, {a_addr123_fu_3580_p5}};
assign tmp_118_trn_cast1_fu_3934_p1 = {{6{1'b0}}, {tmp_117_fu_3929_p2}};
assign tmp_118_trn_cast_fu_3966_p1 = {{7{1'b0}}, {tmp_117_reg_5865}};
assign tmp_11_dup_fu_2430_p2 = (j_phi_fu_1912_p4 + ap_const_lv7_1);
assign tmp_11_fu_2531_p1 = {{51{1'b0}}, {b_addr1_fu_2519_p5}};
assign tmp_122_fu_3621_p1 = {{57{1'b0}}, {j_2_phi_fu_2000_p4}};
assign tmp_122_trn_cast_fu_4049_p1 = {{6{1'b0}}, {i_5_mid2_fu_4037_p3}};
assign tmp_123_fu_4092_p2 = (i_5_cast_reg_5951 + ap_const_lv6_1);
assign tmp_124_trn_cast_fu_4100_p1 = {{6{1'b0}}, {tmp_123_fu_4092_p2}};
assign tmp_125_dup_fu_4031_p2 = (i_5_phi_fu_2077_p4 + ap_const_lv7_7F);
assign tmp_125_fu_3694_p1 = {{50{1'b0}}, {a_addr39_fu_3688_p2}};
assign tmp_126_fu_3741_p1 = {{51{1'b0}}, {b_addr27_fu_3735_p2}};
assign tmp_126_trn_cast1_fu_4097_p1 = {{6{1'b0}}, {j_5_mid2_reg_5933}};
assign tmp_126_trn_cast_fu_4053_p1 = {{7{1'b0}}, {j_5_mid2_fu_4023_p3}};
assign tmp_129_fu_4125_p2 = (j_5_mid2_reg_5933 | ap_const_lv7_1);
assign tmp_12_trn_cast_fu_2448_p1 = {{6{1'b0}}, {i_1_mid2_fu_2422_p3}};
assign tmp_130_fu_3764_p1 = {{50{1'b0}}, {a_addr40_fu_3759_p2}};
assign tmp_130_trn_cast1_fu_4130_p1 = {{6{1'b0}}, {tmp_129_fu_4125_p2}};
assign tmp_130_trn_cast_fu_4134_p1 = {{7{1'b0}}, {tmp_129_fu_4125_p2}};
assign tmp_133_fu_4159_p2 = (j_5_mid2_reg_5933 | ap_const_lv7_2);
assign tmp_134_fu_3775_p1 = {{51{1'b0}}, {b_addr28_fu_3769_p2}};
assign tmp_134_trn_cast1_fu_4178_p1 = {{6{1'b0}}, {tmp_133_reg_6012}};
assign tmp_134_trn_cast_fu_4164_p1 = {{7{1'b0}}, {tmp_133_fu_4159_p2}};
assign tmp_137_fu_4191_p2 = (j_5_mid2_reg_5933 | ap_const_lv7_3);
assign tmp_138_fu_3794_p1 = {{50{1'b0}}, {a_addr41_fu_3789_p2}};
assign tmp_138_trn_cast1_fu_4196_p1 = {{6{1'b0}}, {tmp_137_fu_4191_p2}};
assign tmp_138_trn_cast_fu_4200_p1 = {{7{1'b0}}, {tmp_137_fu_4191_p2}};
assign tmp_141_fu_4224_p2 = (j_5_mid2_reg_5933 | ap_const_lv7_4);
assign tmp_142_fu_3807_p1 = {{51{1'b0}}, {b_addr29_fu_3802_p2}};
assign tmp_142_trn_cast1_fu_4243_p1 = {{6{1'b0}}, {tmp_141_reg_6047}};
assign tmp_142_trn_cast_fu_4229_p1 = {{7{1'b0}}, {tmp_141_fu_4224_p2}};
assign tmp_145_fu_4256_p2 = (j_5_mid2_reg_5933 | ap_const_lv7_5);
assign tmp_146_fu_3830_p1 = {{50{1'b0}}, {a_addr43_fu_3825_p2}};
assign tmp_146_trn_cast1_fu_4261_p1 = {{6{1'b0}}, {tmp_145_fu_4256_p2}};
assign tmp_146_trn_cast_fu_4265_p1 = {{7{1'b0}}, {tmp_145_fu_4256_p2}};
assign tmp_149_fu_4289_p2 = (j_5_mid2_reg_5933 | ap_const_lv7_6);
assign tmp_14_fu_2536_p2 = (i_1_mid2_reg_5204 | ap_const_lv7_1);
assign tmp_150_fu_3840_p1 = {{51{1'b0}}, {b_addr30_fu_3835_p2}};
assign tmp_150_trn_cast1_fu_4294_p1 = {{6{1'b0}}, {tmp_149_fu_4289_p2}};
assign tmp_150_trn_cast_fu_4332_p1 = {{7{1'b0}}, {tmp_149_reg_6082}};
assign tmp_153_fu_4308_p2 = (j_5_mid2_reg_5933 | ap_const_lv7_7);
assign tmp_154_fu_3859_p1 = {{50{1'b0}}, {a_addr44_fu_3854_p2}};
assign tmp_154_trn_cast1_fu_4313_p1 = {{6{1'b0}}, {tmp_153_fu_4308_p2}};
assign tmp_154_trn_cast_fu_4345_p1 = {{7{1'b0}}, {tmp_153_reg_6092}};
assign tmp_158_fu_3872_p1 = {{51{1'b0}}, {b_addr31_fu_3867_p2}};
assign tmp_158_trn_cast_fu_4397_p1 = {{6{1'b0}}, {i_6_mid2_fu_4389_p3}};
assign tmp_159_fu_4554_p2 = (i_6_mid2_reg_6153 | ap_const_lv7_1);
assign tmp_15_fu_2560_p1 = {{50{1'b0}}, {a_addr6_fu_2555_p2}};
assign tmp_160_fu_3895_p1 = {{50{1'b0}}, {a_addr47_fu_3890_p2}};
assign tmp_160_trn_cast_fu_4578_p1 = {{6{1'b0}}, {tmp_159_fu_4554_p2}};
assign tmp_161_fu_4661_p2 = (i_6_mid2_reg_6153 | ap_const_lv7_2);
assign tmp_162_fu_3905_p1 = {{51{1'b0}}, {b_addr32_fu_3900_p2}};
assign tmp_162_trn_cast_fu_4666_p1 = {{6{1'b0}}, {tmp_161_fu_4661_p2}};
assign tmp_163_fu_4736_p2 = (i_6_mid2_reg_6153 | ap_const_lv7_3);
assign tmp_164_fu_3961_p1 = {{50{1'b0}}, {a_addr48_fu_3956_p2}};
assign tmp_164_trn_cast_fu_4750_p1 = {{6{1'b0}}, {tmp_163_fu_4736_p2}};
assign tmp_165_fu_4828_p2 = (i_6_mid2_reg_6153 | ap_const_lv7_4);
assign tmp_166_fu_3924_p1 = {{51{1'b0}}, {b_addr33_fu_3919_p2}};
assign tmp_166_trn_cast_fu_4833_p1 = {{6{1'b0}}, {tmp_165_fu_4828_p2}};
assign tmp_167_fu_4903_p2 = (i_6_mid2_reg_6153 | ap_const_lv7_5);
assign tmp_168_fu_3974_p1 = {{50{1'b0}}, {a_addr50_reg_5890}};
assign tmp_168_trn_cast_fu_4917_p1 = {{6{1'b0}}, {tmp_167_fu_4903_p2}};
assign tmp_169_fu_4995_p2 = (i_6_mid2_reg_6153 | ap_const_lv7_6);
assign tmp_16_fu_2597_p1 = {{51{1'b0}}, {b_addr3_fu_2585_p5}};
assign tmp_16_trn_cast_fu_2541_p1 = {{6{1'b0}}, {tmp_14_fu_2536_p2}};
assign tmp_170_fu_3943_p1 = {{51{1'b0}}, {b_addr34_fu_3938_p2}};
assign tmp_170_trn_cast_fu_5000_p1 = {{6{1'b0}}, {tmp_169_fu_4995_p2}};
assign tmp_171_fu_5052_p2 = (i_6_mid2_reg_6153 | ap_const_lv7_7);
assign tmp_172_fu_4000_p1 = {{51{1'b0}}, {b_addr35_fu_3994_p2}};
assign tmp_172_trn_cast_fu_5079_p1 = {{6{1'b0}}, {tmp_171_fu_5052_p2}};
assign tmp_173_dup_fu_4383_p2 = (i_6_phi_fu_2124_p6 + ap_const_lv7_8);
assign tmp_174_fu_4073_p1 = {{50{b_addr37_fu_4067_p2[13]}}, {b_addr37_fu_4067_p2}};
assign tmp_174_trn_cast_fu_4401_p1 = {{7{1'b0}}, {j_6_mid2_fu_4375_p3}};
assign tmp_175_fu_4440_p2 = (j_6_mid2_reg_6141 | ap_const_lv7_1);
assign tmp_176_fu_4120_p1 = {{51{1'b0}}, {a_addr52_fu_4114_p2}};
assign tmp_176_trn_cast_fu_4445_p1 = {{7{1'b0}}, {tmp_175_fu_4440_p2}};
assign tmp_177_fu_4459_p2 = (j_6_mid2_reg_6141 | ap_const_lv7_2);
assign tmp_178_fu_4143_p1 = {{50{b_addr38_fu_4138_p2[13]}}, {b_addr38_fu_4138_p2}};
assign tmp_178_trn_cast_fu_4464_p1 = {{7{1'b0}}, {tmp_177_fu_4459_p2}};
assign tmp_179_fu_4478_p2 = (j_6_mid2_reg_6141 | ap_const_lv7_3);
assign tmp_180_fu_4154_p1 = {{51{1'b0}}, {a_addr54_fu_4148_p2}};
assign tmp_180_trn_cast_fu_4483_p1 = {{7{1'b0}}, {tmp_179_fu_4478_p2}};
assign tmp_181_fu_4497_p2 = (j_6_mid2_reg_6141 | ap_const_lv7_4);
assign tmp_182_fu_4173_p1 = {{50{b_addr39_fu_4168_p2[13]}}, {b_addr39_fu_4168_p2}};
assign tmp_182_trn_cast_fu_4502_p1 = {{7{1'b0}}, {tmp_181_fu_4497_p2}};
assign tmp_183_fu_4516_p2 = (j_6_mid2_reg_6141 | ap_const_lv7_5);
assign tmp_184_fu_4186_p1 = {{51{1'b0}}, {a_addr55_fu_4181_p2}};
assign tmp_184_trn_cast_fu_4521_p1 = {{7{1'b0}}, {tmp_183_fu_4516_p2}};
assign tmp_185_fu_4535_p2 = (j_6_mid2_reg_6141 | ap_const_lv7_6);
assign tmp_186_fu_4209_p1 = {{50{b_addr40_fu_4204_p2[13]}}, {b_addr40_fu_4204_p2}};
assign tmp_186_trn_cast_fu_4540_p1 = {{7{1'b0}}, {tmp_185_fu_4535_p2}};
assign tmp_187_fu_4559_p2 = (j_6_mid2_reg_6141 | ap_const_lv7_7);
assign tmp_188_fu_4219_p1 = {{51{1'b0}}, {a_addr56_fu_4214_p2}};
assign tmp_188_trn_cast_fu_4564_p1 = {{7{1'b0}}, {tmp_187_fu_4559_p2}};
assign tmp_190_fu_4238_p1 = {{50{b_addr41_fu_4233_p2[13]}}, {b_addr41_fu_4233_p2}};
assign tmp_191_fu_4251_p1 = {{51{1'b0}}, {a_addr58_fu_4246_p2}};
assign tmp_192_fu_4274_p1 = {{50{b_addr42_fu_4269_p2[13]}}, {b_addr42_fu_4269_p2}};
assign tmp_193_fu_4284_p1 = {{51{1'b0}}, {a_addr59_fu_4279_p2}};
assign tmp_194_fu_4340_p1 = {{50{b_addr43_fu_4335_p2[13]}}, {b_addr43_fu_4335_p2}};
assign tmp_196_fu_4303_p1 = {{51{1'b0}}, {a_addr60_fu_4298_p2}};
assign tmp_197_fu_4353_p1 = {{50{b_addr44_reg_6117[13]}}, {b_addr44_reg_6117}};
assign tmp_198_fu_4322_p1 = {{51{1'b0}}, {a_addr62_fu_4317_p2}};
assign tmp_199_fu_4421_p1 = {{50{1'b0}}, {a_addr28_fu_4415_p2}};
assign tmp_19_fu_2602_p2 = (i_1_mid2_reg_5204 | ap_const_lv7_2);
assign tmp_1_fu_2359_p2 = (counter != ap_const_lv7_0? 1'b1: 1'b0);
assign tmp_200_fu_4454_p1 = {{50{1'b0}}, {a_addr29_fu_4449_p2}};
assign tmp_201_fu_4473_p1 = {{50{1'b0}}, {a_addr31_fu_4468_p2}};
assign tmp_202_fu_4492_p1 = {{50{1'b0}}, {a_addr32_fu_4487_p2}};
assign tmp_203_fu_4511_p1 = {{50{1'b0}}, {a_addr33_fu_4506_p2}};
assign tmp_204_fu_4530_p1 = {{50{1'b0}}, {a_addr35_fu_4525_p2}};
assign tmp_205_fu_4549_p1 = {{50{1'b0}}, {a_addr36_fu_4544_p2}};
assign tmp_206_fu_4573_p1 = {{50{1'b0}}, {a_addr63_fu_4568_p2}};
assign tmp_207_fu_4597_p1 = {{50{1'b0}}, {a_addr66_fu_4592_p2}};
assign tmp_208_fu_4611_p1 = {{50{1'b0}}, {a_addr67_fu_4607_p2}};
assign tmp_209_fu_4620_p1 = {{50{1'b0}}, {a_addr68_fu_4616_p2}};
assign tmp_20_fu_2626_p1 = {{50{1'b0}}, {a_addr9_fu_2621_p2}};
assign tmp_20_trn_cast_fu_2607_p1 = {{6{1'b0}}, {tmp_19_fu_2602_p2}};
assign tmp_210_fu_4629_p1 = {{50{1'b0}}, {a_addr70_fu_4625_p2}};
assign tmp_211_fu_4638_p1 = {{50{1'b0}}, {a_addr71_fu_4634_p2}};
assign tmp_212_fu_4647_p1 = {{50{1'b0}}, {a_addr74_fu_4643_p2}};
assign tmp_213_fu_4656_p1 = {{50{1'b0}}, {a_addr75_fu_4652_p2}};
assign tmp_214_fu_4685_p1 = {{50{1'b0}}, {a_addr78_fu_4680_p2}};
assign tmp_215_fu_4695_p1 = {{50{1'b0}}, {a_addr79_fu_4690_p2}};
assign tmp_216_fu_4704_p1 = {{50{1'b0}}, {a_addr81_fu_4700_p2}};
assign tmp_217_fu_4713_p1 = {{50{1'b0}}, {a_addr82_fu_4709_p2}};
assign tmp_218_fu_4722_p1 = {{50{1'b0}}, {a_addr83_fu_4718_p2}};
assign tmp_219_fu_4731_p1 = {{50{1'b0}}, {a_addr85_fu_4727_p2}};
assign tmp_220_fu_4745_p1 = {{50{1'b0}}, {a_addr86_fu_4741_p2}};
assign tmp_221_fu_4769_p1 = {{50{1'b0}}, {a_addr89_fu_4764_p2}};
assign tmp_222_fu_4778_p1 = {{50{1'b0}}, {a_addr90_fu_4774_p2}};
assign tmp_223_fu_4787_p1 = {{50{1'b0}}, {a_addr91_fu_4783_p2}};
assign tmp_224_fu_4796_p1 = {{50{1'b0}}, {a_addr93_fu_4792_p2}};
assign tmp_225_fu_4805_p1 = {{50{1'b0}}, {a_addr94_fu_4801_p2}};
assign tmp_226_fu_4814_p1 = {{50{1'b0}}, {a_addr95_fu_4810_p2}};
assign tmp_227_fu_4823_p1 = {{50{1'b0}}, {a_addr97_fu_4819_p2}};
assign tmp_228_fu_4852_p1 = {{50{1'b0}}, {a_addr99_fu_4847_p2}};
assign tmp_229_fu_4862_p1 = {{50{1'b0}}, {a_addr96_fu_4857_p2}};
assign tmp_230_fu_4871_p1 = {{50{1'b0}}, {a_addr92_fu_4867_p2}};
assign tmp_231_fu_4880_p1 = {{50{1'b0}}, {a_addr88_fu_4876_p2}};
assign tmp_232_fu_4889_p1 = {{50{1'b0}}, {a_addr84_fu_4885_p2}};
assign tmp_233_fu_4898_p1 = {{50{1'b0}}, {a_addr80_fu_4894_p2}};
assign tmp_234_fu_4912_p1 = {{50{1'b0}}, {a_addr76_fu_4908_p2}};
assign tmp_235_fu_4936_p1 = {{50{1'b0}}, {a_addr73_fu_4931_p2}};
assign tmp_236_fu_4945_p1 = {{50{1'b0}}, {a_addr69_fu_4941_p2}};
assign tmp_237_fu_4954_p1 = {{50{1'b0}}, {a_addr65_fu_4950_p2}};
assign tmp_238_fu_4963_p1 = {{50{1'b0}}, {a_addr61_fu_4959_p2}};
assign tmp_239_fu_4972_p1 = {{50{1'b0}}, {a_addr57_fu_4968_p2}};
assign tmp_23_fu_2716_p2 = (i_1_mid2_reg_5204 | ap_const_lv7_3);
assign tmp_240_fu_4981_p1 = {{50{1'b0}}, {a_addr53_fu_4977_p2}};
assign tmp_241_fu_4990_p1 = {{50{1'b0}}, {a_addr49_fu_4986_p2}};
assign tmp_242_fu_5019_p1 = {{50{1'b0}}, {a_addr46_fu_5014_p2}};
assign tmp_243_fu_5029_p1 = {{50{1'b0}}, {a_addr42_fu_5024_p2}};
assign tmp_244_fu_5038_p1 = {{50{1'b0}}, {a_addr38_fu_5034_p2}};
assign tmp_245_fu_5047_p1 = {{50{1'b0}}, {a_addr34_fu_5043_p2}};
assign tmp_246_fu_5061_p1 = {{50{1'b0}}, {a_addr30_fu_5057_p2}};
assign tmp_247_fu_5070_p1 = {{50{1'b0}}, {a_addr26_fu_5066_p2}};
assign tmp_248_fu_5128_p1 = {{50{1'b0}}, {a_addr22_reg_6810}};
assign tmp_249_fu_5132_p1 = {{50{1'b0}}, {a_addr19_reg_6815}};
assign tmp_24_fu_2711_p1 = {{51{1'b0}}, {b_addr5_fu_2701_p5}};
assign tmp_24_trn_cast_fu_2721_p1 = {{6{1'b0}}, {tmp_23_fu_2716_p2}};
assign tmp_250_fu_5136_p1 = {{50{1'b0}}, {a_addr16_reg_6820}};
assign tmp_251_fu_5140_p1 = {{50{1'b0}}, {a_addr13_reg_6825}};
assign tmp_252_fu_5144_p1 = {{50{1'b0}}, {a_addr10_reg_6830}};
assign tmp_253_fu_5148_p1 = {{50{1'b0}}, {a_addr7_reg_6835}};
assign tmp_254_fu_5152_p1 = {{50{1'b0}}, {a_addr4_reg_6840}};
assign tmp_255_fu_5156_p1 = {{50{1'b0}}, {a_addr1_reg_6845}};
assign tmp_27_fu_2770_p2 = (i_1_mid2_reg_5204 | ap_const_lv7_4);
assign tmp_28_fu_2740_p1 = {{50{1'b0}}, {a_addr12_fu_2735_p2}};
assign tmp_28_trn_cast_fu_2775_p1 = {{6{1'b0}}, {tmp_27_fu_2770_p2}};
assign tmp_2_fu_2371_p2 = (tag == ap_const_lv2_0? 1'b1: 1'b0);
assign tmp_31_fu_2823_p2 = (i_1_mid2_reg_5204 | ap_const_lv7_5);
assign tmp_32_fu_2765_p1 = {{51{1'b0}}, {b_addr7_fu_2754_p5}};
assign tmp_32_trn_cast_fu_2828_p1 = {{6{1'b0}}, {tmp_31_fu_2823_p2}};
assign tmp_35_fu_2877_p2 = (i_1_mid2_reg_5204 | ap_const_lv7_6);
assign tmp_36_fu_2794_p1 = {{50{1'b0}}, {a_addr15_fu_2789_p2}};
assign tmp_36_trn_cast_fu_2882_p1 = {{6{1'b0}}, {tmp_35_fu_2877_p2}};
assign tmp_39_fu_2926_p2 = (i_1_mid2_reg_5204 | ap_const_lv7_7);
assign tmp_3_trn_cast_fu_2389_p1 = {{6{1'b0}}, {i_phi_fu_1890_p4}};
assign tmp_40_fu_2818_p1 = {{51{1'b0}}, {b_addr9_fu_2808_p5}};
assign tmp_40_trn_cast_fu_2931_p1 = {{6{1'b0}}, {tmp_39_fu_2926_p2}};
assign tmp_44_fu_2847_p1 = {{50{1'b0}}, {a_addr20_fu_2842_p2}};
assign tmp_45_fu_3116_p2 = (j_1_cast_reg_5472 + ap_const_lv6_1);
assign tmp_46_fu_2872_p1 = {{51{1'b0}}, {b_addr46_fu_2861_p5}};
assign tmp_46_trn_cast1_fu_3125_p4 = {{tmp_46_trn_cast_fu_3121_p1[ap_const_lv32_C : ap_const_lv32_6]}};
assign tmp_46_trn_cast2_fu_3190_p4 = {{tmp_46_trn_cast_fu_3121_p1[ap_const_lv32_C : ap_const_lv32_6]}};
assign tmp_46_trn_cast3_fu_3256_p4 = {{tmp_46_trn_cast_fu_3121_p1[ap_const_lv32_C : ap_const_lv32_6]}};
assign tmp_46_trn_cast_fu_3121_p1 = {{7{1'b0}}, {tmp_45_fu_3116_p2}};
assign tmp_47_fu_2980_p1 = {{50{1'b0}}, {a_addr23_reg_5382}};
assign tmp_50_dup_fu_3051_p2 = (j_1_phi_fu_1967_p4 + ap_const_lv7_7F);
assign tmp_50_fu_2921_p1 = {{51{1'b0}}, {b_addr48_fu_2910_p5}};
assign tmp_51_fu_2984_p1 = {{50{1'b0}}, {a_addr25_reg_5392}};
assign tmp_51_trn_cast_fu_3069_p1 = {{6{1'b0}}, {i_3_mid2_fu_3043_p3}};
assign tmp_54_fu_3157_p2 = (i_3_mid2_reg_5455 | ap_const_lv7_1);
assign tmp_55_fu_2970_p1 = {{51{1'b0}}, {b_addr50_fu_2959_p5}};
assign tmp_55_trn_cast_fu_3162_p1 = {{6{1'b0}}, {tmp_54_fu_3157_p2}};
assign tmp_58_fu_3223_p2 = (i_3_mid2_reg_5455 | ap_const_lv7_2);
assign tmp_59_fu_3020_p1 = {{51{1'b0}}, {b_addr52_fu_3008_p5}};
assign tmp_59_trn_cast_fu_3228_p1 = {{6{1'b0}}, {tmp_58_fu_3223_p2}};
assign tmp_62_fu_3337_p2 = (i_3_mid2_reg_5455 | ap_const_lv7_3);
assign tmp_63_trn_cast_fu_3342_p1 = {{6{1'b0}}, {tmp_62_fu_3337_p2}};
assign tmp_66_fu_3391_p2 = (i_3_mid2_reg_5455 | ap_const_lv7_4);
assign tmp_67_fu_3093_p1 = {{50{b_addr11_fu_3087_p2[13]}}, {b_addr11_fu_3087_p2}};
assign tmp_67_trn_cast_fu_3396_p1 = {{6{1'b0}}, {tmp_66_fu_3391_p2}};
assign tmp_6_fu_2399_p1 = {{51{1'b0}}, {a_addr_fu_2393_p2}};
assign tmp_6_trn_cast_fu_2452_p1 = {{7{1'b0}}, {j_mid2_fu_2436_p3}};
assign tmp_70_fu_3444_p2 = (i_3_mid2_reg_5455 | ap_const_lv7_5);
assign tmp_71_fu_3152_p1 = {{51{1'b0}}, {a_addr109_fu_3140_p5}};
assign tmp_71_trn_cast_fu_3449_p1 = {{6{1'b0}}, {tmp_70_fu_3444_p2}};
assign tmp_74_fu_3498_p2 = (i_3_mid2_reg_5455 | ap_const_lv7_6);
assign tmp_75_fu_3181_p1 = {{50{b_addr13_fu_3176_p2[13]}}, {b_addr13_fu_3176_p2}};
assign tmp_75_trn_cast_fu_3503_p1 = {{6{1'b0}}, {tmp_74_fu_3498_p2}};
assign tmp_78_fu_3547_p2 = (i_3_mid2_reg_5455 | ap_const_lv7_7);
assign tmp_79_fu_3218_p1 = {{51{1'b0}}, {a_addr111_fu_3206_p5}};
assign tmp_79_trn_cast_fu_3552_p1 = {{6{1'b0}}, {tmp_78_fu_3547_p2}};
assign tmp_7_fu_2495_p2 = (j_cast_reg_5221 + ap_const_lv6_3F);
assign tmp_83_fu_3247_p1 = {{50{b_addr15_fu_3242_p2[13]}}, {b_addr15_fu_3242_p2}};
assign tmp_83_trn_cast_fu_3670_p1 = {{6{1'b0}}, {i_4_mid2_fu_3658_p3}};
assign tmp_84_fu_3713_p2 = (i_4_cast_reg_5724 + ap_const_lv6_3F);
assign tmp_85_fu_3332_p1 = {{51{1'b0}}, {a_addr113_fu_3322_p5}};
assign tmp_85_trn_cast_fu_3721_p1 = {{6{1'b0}}, {tmp_84_fu_3713_p2}};
assign tmp_86_fu_3361_p1 = {{50{b_addr17_fu_3356_p2[13]}}, {b_addr17_fu_3356_p2}};
assign tmp_86_trn_cast_fu_3990_p1 = {{6{1'b0}}, {j_4_phi_fu_2055_p4}};
assign tmp_89_dup_fu_3652_p2 = (i_4_phi_fu_2022_p4 + ap_const_lv7_1);
assign tmp_89_fu_3386_p1 = {{51{1'b0}}, {a_addr115_fu_3375_p5}};
assign tmp_8_trn_cast1_fu_2504_p4 = {{tmp_8_trn_cast_fu_2500_p1[ap_const_lv32_C : ap_const_lv32_6]}};
assign tmp_8_trn_cast2_fu_2569_p4 = {{tmp_8_trn_cast_fu_2500_p1[ap_const_lv32_C : ap_const_lv32_6]}};
assign tmp_8_trn_cast3_fu_2635_p4 = {{tmp_8_trn_cast_fu_2500_p1[ap_const_lv32_C : ap_const_lv32_6]}};
assign tmp_8_trn_cast_fu_2500_p1 = {{7{1'b0}}, {tmp_7_fu_2495_p2}};
assign tmp_90_fu_3415_p1 = {{50{b_addr19_fu_3410_p2[13]}}, {b_addr19_fu_3410_p2}};
assign tmp_90_trn_cast1_fu_3718_p1 = {{6{1'b0}}, {j_3_mid2_reg_5706}};
assign tmp_90_trn_cast_fu_3674_p1 = {{7{1'b0}}, {j_3_mid2_fu_3644_p3}};
assign tmp_93_fu_3746_p2 = (j_3_mid2_reg_5706 | ap_const_lv7_1);
assign tmp_94_fu_3439_p1 = {{51{1'b0}}, {a_addr117_fu_3429_p5}};
assign tmp_94_trn_cast1_fu_3751_p1 = {{6{1'b0}}, {tmp_93_fu_3746_p2}};
assign tmp_94_trn_cast_fu_3755_p1 = {{7{1'b0}}, {tmp_93_fu_3746_p2}};
assign tmp_97_fu_3780_p2 = (j_3_mid2_reg_5706 | ap_const_lv7_2);
assign tmp_98_fu_3468_p1 = {{50{b_addr21_fu_3463_p2[13]}}, {b_addr21_fu_3463_p2}};
assign tmp_98_trn_cast1_fu_3799_p1 = {{6{1'b0}}, {tmp_97_reg_5785}};
assign tmp_98_trn_cast_fu_3785_p1 = {{7{1'b0}}, {tmp_97_fu_3780_p2}};
assign tmp_9_fu_2472_p1 = {{50{1'b0}}, {a_addr3_fu_2466_p2}};
assign tmp_9_trn_cast_fu_3000_p1 = {{6{1'b0}}, {i_2_phi_fu_1945_p4}};
assign tmp_fu_2353_p2 = (counter < ap_const_lv7_41? 1'b1: 1'b0);
always @ (ap_clk)
begin
tmp_6_reg_5180[0] <= 1'b0;
tmp_6_reg_5180[1] <= 1'b0;
tmp_6_reg_5180[2] <= 1'b0;
tmp_6_reg_5180[3] <= 1'b0;
tmp_6_reg_5180[4] <= 1'b0;
tmp_6_reg_5180[5] <= 1'b0;
tmp_6_reg_5180[13] <= 1'b0;
tmp_6_reg_5180[14] <= 1'b0;
tmp_6_reg_5180[15] <= 1'b0;
tmp_6_reg_5180[16] <= 1'b0;
tmp_6_reg_5180[17] <= 1'b0;
tmp_6_reg_5180[18] <= 1'b0;
tmp_6_reg_5180[19] <= 1'b0;
tmp_6_reg_5180[20] <= 1'b0;
tmp_6_reg_5180[21] <= 1'b0;
tmp_6_reg_5180[22] <= 1'b0;
tmp_6_reg_5180[23] <= 1'b0;
tmp_6_reg_5180[24] <= 1'b0;
tmp_6_reg_5180[25] <= 1'b0;
tmp_6_reg_5180[26] <= 1'b0;
tmp_6_reg_5180[27] <= 1'b0;
tmp_6_reg_5180[28] <= 1'b0;
tmp_6_reg_5180[29] <= 1'b0;
tmp_6_reg_5180[30] <= 1'b0;
tmp_6_reg_5180[31] <= 1'b0;
tmp_6_reg_5180[32] <= 1'b0;
tmp_6_reg_5180[33] <= 1'b0;
tmp_6_reg_5180[34] <= 1'b0;
tmp_6_reg_5180[35] <= 1'b0;
tmp_6_reg_5180[36] <= 1'b0;
tmp_6_reg_5180[37] <= 1'b0;
tmp_6_reg_5180[38] <= 1'b0;
tmp_6_reg_5180[39] <= 1'b0;
tmp_6_reg_5180[40] <= 1'b0;
tmp_6_reg_5180[41] <= 1'b0;
tmp_6_reg_5180[42] <= 1'b0;
tmp_6_reg_5180[43] <= 1'b0;
tmp_6_reg_5180[44] <= 1'b0;
tmp_6_reg_5180[45] <= 1'b0;
tmp_6_reg_5180[46] <= 1'b0;
tmp_6_reg_5180[47] <= 1'b0;
tmp_6_reg_5180[48] <= 1'b0;
tmp_6_reg_5180[49] <= 1'b0;
tmp_6_reg_5180[50] <= 1'b0;
tmp_6_reg_5180[51] <= 1'b0;
tmp_6_reg_5180[52] <= 1'b0;
tmp_6_reg_5180[53] <= 1'b0;
tmp_6_reg_5180[54] <= 1'b0;
tmp_6_reg_5180[55] <= 1'b0;
tmp_6_reg_5180[56] <= 1'b0;
tmp_6_reg_5180[57] <= 1'b0;
tmp_6_reg_5180[58] <= 1'b0;
tmp_6_reg_5180[59] <= 1'b0;
tmp_6_reg_5180[60] <= 1'b0;
tmp_6_reg_5180[61] <= 1'b0;
tmp_6_reg_5180[62] <= 1'b0;
tmp_6_reg_5180[63] <= 1'b0;
end
always @ (ap_clk)
begin
ap_reg_ppstg_tmp_6_reg_5180_pp0_it1[0] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it1[1] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it1[2] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it1[3] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it1[4] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it1[5] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it1[13] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it1[14] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it1[15] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it1[16] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it1[17] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it1[18] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it1[19] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it1[20] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it1[21] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it1[22] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it1[23] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it1[24] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it1[25] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it1[26] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it1[27] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it1[28] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it1[29] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it1[30] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it1[31] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it1[32] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it1[33] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it1[34] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it1[35] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it1[36] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it1[37] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it1[38] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it1[39] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it1[40] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it1[41] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it1[42] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it1[43] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it1[44] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it1[45] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it1[46] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it1[47] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it1[48] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it1[49] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it1[50] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it1[51] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it1[52] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it1[53] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it1[54] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it1[55] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it1[56] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it1[57] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it1[58] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it1[59] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it1[60] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it1[61] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it1[62] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it1[63] <= 1'b0;
end
always @ (ap_clk)
begin
ap_reg_ppstg_tmp_6_reg_5180_pp0_it2[0] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it2[1] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it2[2] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it2[3] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it2[4] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it2[5] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it2[13] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it2[14] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it2[15] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it2[16] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it2[17] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it2[18] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it2[19] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it2[20] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it2[21] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it2[22] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it2[23] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it2[24] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it2[25] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it2[26] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it2[27] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it2[28] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it2[29] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it2[30] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it2[31] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it2[32] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it2[33] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it2[34] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it2[35] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it2[36] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it2[37] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it2[38] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it2[39] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it2[40] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it2[41] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it2[42] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it2[43] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it2[44] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it2[45] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it2[46] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it2[47] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it2[48] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it2[49] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it2[50] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it2[51] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it2[52] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it2[53] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it2[54] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it2[55] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it2[56] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it2[57] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it2[58] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it2[59] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it2[60] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it2[61] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it2[62] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it2[63] <= 1'b0;
end
always @ (ap_clk)
begin
ap_reg_ppstg_tmp_6_reg_5180_pp0_it3[0] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it3[1] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it3[2] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it3[3] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it3[4] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it3[5] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it3[13] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it3[14] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it3[15] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it3[16] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it3[17] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it3[18] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it3[19] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it3[20] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it3[21] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it3[22] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it3[23] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it3[24] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it3[25] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it3[26] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it3[27] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it3[28] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it3[29] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it3[30] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it3[31] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it3[32] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it3[33] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it3[34] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it3[35] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it3[36] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it3[37] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it3[38] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it3[39] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it3[40] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it3[41] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it3[42] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it3[43] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it3[44] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it3[45] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it3[46] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it3[47] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it3[48] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it3[49] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it3[50] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it3[51] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it3[52] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it3[53] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it3[54] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it3[55] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it3[56] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it3[57] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it3[58] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it3[59] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it3[60] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it3[61] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it3[62] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it3[63] <= 1'b0;
end
always @ (ap_clk)
begin
ap_reg_ppstg_tmp_6_reg_5180_pp0_it4[0] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it4[1] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it4[2] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it4[3] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it4[4] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it4[5] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it4[13] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it4[14] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it4[15] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it4[16] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it4[17] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it4[18] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it4[19] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it4[20] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it4[21] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it4[22] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it4[23] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it4[24] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it4[25] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it4[26] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it4[27] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it4[28] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it4[29] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it4[30] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it4[31] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it4[32] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it4[33] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it4[34] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it4[35] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it4[36] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it4[37] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it4[38] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it4[39] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it4[40] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it4[41] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it4[42] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it4[43] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it4[44] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it4[45] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it4[46] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it4[47] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it4[48] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it4[49] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it4[50] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it4[51] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it4[52] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it4[53] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it4[54] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it4[55] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it4[56] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it4[57] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it4[58] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it4[59] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it4[60] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it4[61] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it4[62] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it4[63] <= 1'b0;
end
always @ (ap_clk)
begin
ap_reg_ppstg_tmp_6_reg_5180_pp0_it5[0] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it5[1] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it5[2] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it5[3] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it5[4] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it5[5] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it5[13] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it5[14] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it5[15] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it5[16] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it5[17] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it5[18] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it5[19] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it5[20] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it5[21] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it5[22] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it5[23] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it5[24] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it5[25] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it5[26] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it5[27] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it5[28] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it5[29] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it5[30] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it5[31] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it5[32] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it5[33] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it5[34] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it5[35] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it5[36] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it5[37] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it5[38] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it5[39] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it5[40] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it5[41] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it5[42] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it5[43] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it5[44] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it5[45] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it5[46] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it5[47] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it5[48] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it5[49] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it5[50] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it5[51] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it5[52] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it5[53] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it5[54] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it5[55] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it5[56] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it5[57] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it5[58] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it5[59] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it5[60] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it5[61] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it5[62] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_5180_pp0_it5[63] <= 1'b0;
end
always @ (ap_clk)
begin
tmp_6_trn_cast_reg_5226[7] <= 1'b0;
tmp_6_trn_cast_reg_5226[8] <= 1'b0;
tmp_6_trn_cast_reg_5226[9] <= 1'b0;
tmp_6_trn_cast_reg_5226[10] <= 1'b0;
tmp_6_trn_cast_reg_5226[11] <= 1'b0;
tmp_6_trn_cast_reg_5226[12] <= 1'b0;
tmp_6_trn_cast_reg_5226[13] <= 1'b0;
end
always @ (ap_clk)
begin
tmp_9_reg_5237[14] <= 1'b0;
tmp_9_reg_5237[15] <= 1'b0;
tmp_9_reg_5237[16] <= 1'b0;
tmp_9_reg_5237[17] <= 1'b0;
tmp_9_reg_5237[18] <= 1'b0;
tmp_9_reg_5237[19] <= 1'b0;
tmp_9_reg_5237[20] <= 1'b0;
tmp_9_reg_5237[21] <= 1'b0;
tmp_9_reg_5237[22] <= 1'b0;
tmp_9_reg_5237[23] <= 1'b0;
tmp_9_reg_5237[24] <= 1'b0;
tmp_9_reg_5237[25] <= 1'b0;
tmp_9_reg_5237[26] <= 1'b0;
tmp_9_reg_5237[27] <= 1'b0;
tmp_9_reg_5237[28] <= 1'b0;
tmp_9_reg_5237[29] <= 1'b0;
tmp_9_reg_5237[30] <= 1'b0;
tmp_9_reg_5237[31] <= 1'b0;
tmp_9_reg_5237[32] <= 1'b0;
tmp_9_reg_5237[33] <= 1'b0;
tmp_9_reg_5237[34] <= 1'b0;
tmp_9_reg_5237[35] <= 1'b0;
tmp_9_reg_5237[36] <= 1'b0;
tmp_9_reg_5237[37] <= 1'b0;
tmp_9_reg_5237[38] <= 1'b0;
tmp_9_reg_5237[39] <= 1'b0;
tmp_9_reg_5237[40] <= 1'b0;
tmp_9_reg_5237[41] <= 1'b0;
tmp_9_reg_5237[42] <= 1'b0;
tmp_9_reg_5237[43] <= 1'b0;
tmp_9_reg_5237[44] <= 1'b0;
tmp_9_reg_5237[45] <= 1'b0;
tmp_9_reg_5237[46] <= 1'b0;
tmp_9_reg_5237[47] <= 1'b0;
tmp_9_reg_5237[48] <= 1'b0;
tmp_9_reg_5237[49] <= 1'b0;
tmp_9_reg_5237[50] <= 1'b0;
tmp_9_reg_5237[51] <= 1'b0;
tmp_9_reg_5237[52] <= 1'b0;
tmp_9_reg_5237[53] <= 1'b0;
tmp_9_reg_5237[54] <= 1'b0;
tmp_9_reg_5237[55] <= 1'b0;
tmp_9_reg_5237[56] <= 1'b0;
tmp_9_reg_5237[57] <= 1'b0;
tmp_9_reg_5237[58] <= 1'b0;
tmp_9_reg_5237[59] <= 1'b0;
tmp_9_reg_5237[60] <= 1'b0;
tmp_9_reg_5237[61] <= 1'b0;
tmp_9_reg_5237[62] <= 1'b0;
tmp_9_reg_5237[63] <= 1'b0;
end
always @ (ap_clk)
begin
ap_reg_ppstg_tmp_9_reg_5237_pp1_it1[14] <= 1'b0;
ap_reg_ppstg_tmp_9_reg_5237_pp1_it1[15] <= 1'b0;
ap_reg_ppstg_tmp_9_reg_5237_pp1_it1[16] <= 1'b0;
ap_reg_ppstg_tmp_9_reg_5237_pp1_it1[17] <= 1'b0;
ap_reg_ppstg_tmp_9_reg_5237_pp1_it1[18] <= 1'b0;
ap_reg_ppstg_tmp_9_reg_5237_pp1_it1[19] <= 1'b0;
ap_reg_ppstg_tmp_9_reg_5237_pp1_it1[20] <= 1'b0;
ap_reg_ppstg_tmp_9_reg_5237_pp1_it1[21] <= 1'b0;
ap_reg_ppstg_tmp_9_reg_5237_pp1_it1[22] <= 1'b0;
ap_reg_ppstg_tmp_9_reg_5237_pp1_it1[23] <= 1'b0;
ap_reg_ppstg_tmp_9_reg_5237_pp1_it1[24] <= 1'b0;
ap_reg_ppstg_tmp_9_reg_5237_pp1_it1[25] <= 1'b0;
ap_reg_ppstg_tmp_9_reg_5237_pp1_it1[26] <= 1'b0;
ap_reg_ppstg_tmp_9_reg_5237_pp1_it1[27] <= 1'b0;
ap_reg_ppstg_tmp_9_reg_5237_pp1_it1[28] <= 1'b0;
ap_reg_ppstg_tmp_9_reg_5237_pp1_it1[29] <= 1'b0;
ap_reg_ppstg_tmp_9_reg_5237_pp1_it1[30] <= 1'b0;
ap_reg_ppstg_tmp_9_reg_5237_pp1_it1[31] <= 1'b0;
ap_reg_ppstg_tmp_9_reg_5237_pp1_it1[32] <= 1'b0;
ap_reg_ppstg_tmp_9_reg_5237_pp1_it1[33] <= 1'b0;
ap_reg_ppstg_tmp_9_reg_5237_pp1_it1[34] <= 1'b0;
ap_reg_ppstg_tmp_9_reg_5237_pp1_it1[35] <= 1'b0;
ap_reg_ppstg_tmp_9_reg_5237_pp1_it1[36] <= 1'b0;
ap_reg_ppstg_tmp_9_reg_5237_pp1_it1[37] <= 1'b0;
ap_reg_ppstg_tmp_9_reg_5237_pp1_it1[38] <= 1'b0;
ap_reg_ppstg_tmp_9_reg_5237_pp1_it1[39] <= 1'b0;
ap_reg_ppstg_tmp_9_reg_5237_pp1_it1[40] <= 1'b0;
ap_reg_ppstg_tmp_9_reg_5237_pp1_it1[41] <= 1'b0;
ap_reg_ppstg_tmp_9_reg_5237_pp1_it1[42] <= 1'b0;
ap_reg_ppstg_tmp_9_reg_5237_pp1_it1[43] <= 1'b0;
ap_reg_ppstg_tmp_9_reg_5237_pp1_it1[44] <= 1'b0;
ap_reg_ppstg_tmp_9_reg_5237_pp1_it1[45] <= 1'b0;
ap_reg_ppstg_tmp_9_reg_5237_pp1_it1[46] <= 1'b0;
ap_reg_ppstg_tmp_9_reg_5237_pp1_it1[47] <= 1'b0;
ap_reg_ppstg_tmp_9_reg_5237_pp1_it1[48] <= 1'b0;
ap_reg_ppstg_tmp_9_reg_5237_pp1_it1[49] <= 1'b0;
ap_reg_ppstg_tmp_9_reg_5237_pp1_it1[50] <= 1'b0;
ap_reg_ppstg_tmp_9_reg_5237_pp1_it1[51] <= 1'b0;
ap_reg_ppstg_tmp_9_reg_5237_pp1_it1[52] <= 1'b0;
ap_reg_ppstg_tmp_9_reg_5237_pp1_it1[53] <= 1'b0;
ap_reg_ppstg_tmp_9_reg_5237_pp1_it1[54] <= 1'b0;
ap_reg_ppstg_tmp_9_reg_5237_pp1_it1[55] <= 1'b0;
ap_reg_ppstg_tmp_9_reg_5237_pp1_it1[56] <= 1'b0;
ap_reg_ppstg_tmp_9_reg_5237_pp1_it1[57] <= 1'b0;
ap_reg_ppstg_tmp_9_reg_5237_pp1_it1[58] <= 1'b0;
ap_reg_ppstg_tmp_9_reg_5237_pp1_it1[59] <= 1'b0;
ap_reg_ppstg_tmp_9_reg_5237_pp1_it1[60] <= 1'b0;
ap_reg_ppstg_tmp_9_reg_5237_pp1_it1[61] <= 1'b0;
ap_reg_ppstg_tmp_9_reg_5237_pp1_it1[62] <= 1'b0;
ap_reg_ppstg_tmp_9_reg_5237_pp1_it1[63] <= 1'b0;
end
always @ (ap_clk)
begin
tmp_8_trn_cast_reg_5257[6] <= 1'b0;
tmp_8_trn_cast_reg_5257[7] <= 1'b0;
tmp_8_trn_cast_reg_5257[8] <= 1'b0;
tmp_8_trn_cast_reg_5257[9] <= 1'b0;
tmp_8_trn_cast_reg_5257[10] <= 1'b0;
tmp_8_trn_cast_reg_5257[11] <= 1'b0;
tmp_8_trn_cast_reg_5257[12] <= 1'b0;
end
always @ (ap_clk)
begin
tmp_15_reg_5272[14] <= 1'b0;
tmp_15_reg_5272[15] <= 1'b0;
tmp_15_reg_5272[16] <= 1'b0;
tmp_15_reg_5272[17] <= 1'b0;
tmp_15_reg_5272[18] <= 1'b0;
tmp_15_reg_5272[19] <= 1'b0;
tmp_15_reg_5272[20] <= 1'b0;
tmp_15_reg_5272[21] <= 1'b0;
tmp_15_reg_5272[22] <= 1'b0;
tmp_15_reg_5272[23] <= 1'b0;
tmp_15_reg_5272[24] <= 1'b0;
tmp_15_reg_5272[25] <= 1'b0;
tmp_15_reg_5272[26] <= 1'b0;
tmp_15_reg_5272[27] <= 1'b0;
tmp_15_reg_5272[28] <= 1'b0;
tmp_15_reg_5272[29] <= 1'b0;
tmp_15_reg_5272[30] <= 1'b0;
tmp_15_reg_5272[31] <= 1'b0;
tmp_15_reg_5272[32] <= 1'b0;
tmp_15_reg_5272[33] <= 1'b0;
tmp_15_reg_5272[34] <= 1'b0;
tmp_15_reg_5272[35] <= 1'b0;
tmp_15_reg_5272[36] <= 1'b0;
tmp_15_reg_5272[37] <= 1'b0;
tmp_15_reg_5272[38] <= 1'b0;
tmp_15_reg_5272[39] <= 1'b0;
tmp_15_reg_5272[40] <= 1'b0;
tmp_15_reg_5272[41] <= 1'b0;
tmp_15_reg_5272[42] <= 1'b0;
tmp_15_reg_5272[43] <= 1'b0;
tmp_15_reg_5272[44] <= 1'b0;
tmp_15_reg_5272[45] <= 1'b0;
tmp_15_reg_5272[46] <= 1'b0;
tmp_15_reg_5272[47] <= 1'b0;
tmp_15_reg_5272[48] <= 1'b0;
tmp_15_reg_5272[49] <= 1'b0;
tmp_15_reg_5272[50] <= 1'b0;
tmp_15_reg_5272[51] <= 1'b0;
tmp_15_reg_5272[52] <= 1'b0;
tmp_15_reg_5272[53] <= 1'b0;
tmp_15_reg_5272[54] <= 1'b0;
tmp_15_reg_5272[55] <= 1'b0;
tmp_15_reg_5272[56] <= 1'b0;
tmp_15_reg_5272[57] <= 1'b0;
tmp_15_reg_5272[58] <= 1'b0;
tmp_15_reg_5272[59] <= 1'b0;
tmp_15_reg_5272[60] <= 1'b0;
tmp_15_reg_5272[61] <= 1'b0;
tmp_15_reg_5272[62] <= 1'b0;
tmp_15_reg_5272[63] <= 1'b0;
end
always @ (ap_clk)
begin
ap_reg_ppstg_tmp_15_reg_5272_pp1_it1[14] <= 1'b0;
ap_reg_ppstg_tmp_15_reg_5272_pp1_it1[15] <= 1'b0;
ap_reg_ppstg_tmp_15_reg_5272_pp1_it1[16] <= 1'b0;
ap_reg_ppstg_tmp_15_reg_5272_pp1_it1[17] <= 1'b0;
ap_reg_ppstg_tmp_15_reg_5272_pp1_it1[18] <= 1'b0;
ap_reg_ppstg_tmp_15_reg_5272_pp1_it1[19] <= 1'b0;
ap_reg_ppstg_tmp_15_reg_5272_pp1_it1[20] <= 1'b0;
ap_reg_ppstg_tmp_15_reg_5272_pp1_it1[21] <= 1'b0;
ap_reg_ppstg_tmp_15_reg_5272_pp1_it1[22] <= 1'b0;
ap_reg_ppstg_tmp_15_reg_5272_pp1_it1[23] <= 1'b0;
ap_reg_ppstg_tmp_15_reg_5272_pp1_it1[24] <= 1'b0;
ap_reg_ppstg_tmp_15_reg_5272_pp1_it1[25] <= 1'b0;
ap_reg_ppstg_tmp_15_reg_5272_pp1_it1[26] <= 1'b0;
ap_reg_ppstg_tmp_15_reg_5272_pp1_it1[27] <= 1'b0;
ap_reg_ppstg_tmp_15_reg_5272_pp1_it1[28] <= 1'b0;
ap_reg_ppstg_tmp_15_reg_5272_pp1_it1[29] <= 1'b0;
ap_reg_ppstg_tmp_15_reg_5272_pp1_it1[30] <= 1'b0;
ap_reg_ppstg_tmp_15_reg_5272_pp1_it1[31] <= 1'b0;
ap_reg_ppstg_tmp_15_reg_5272_pp1_it1[32] <= 1'b0;
ap_reg_ppstg_tmp_15_reg_5272_pp1_it1[33] <= 1'b0;
ap_reg_ppstg_tmp_15_reg_5272_pp1_it1[34] <= 1'b0;
ap_reg_ppstg_tmp_15_reg_5272_pp1_it1[35] <= 1'b0;
ap_reg_ppstg_tmp_15_reg_5272_pp1_it1[36] <= 1'b0;
ap_reg_ppstg_tmp_15_reg_5272_pp1_it1[37] <= 1'b0;
ap_reg_ppstg_tmp_15_reg_5272_pp1_it1[38] <= 1'b0;
ap_reg_ppstg_tmp_15_reg_5272_pp1_it1[39] <= 1'b0;
ap_reg_ppstg_tmp_15_reg_5272_pp1_it1[40] <= 1'b0;
ap_reg_ppstg_tmp_15_reg_5272_pp1_it1[41] <= 1'b0;
ap_reg_ppstg_tmp_15_reg_5272_pp1_it1[42] <= 1'b0;
ap_reg_ppstg_tmp_15_reg_5272_pp1_it1[43] <= 1'b0;
ap_reg_ppstg_tmp_15_reg_5272_pp1_it1[44] <= 1'b0;
ap_reg_ppstg_tmp_15_reg_5272_pp1_it1[45] <= 1'b0;
ap_reg_ppstg_tmp_15_reg_5272_pp1_it1[46] <= 1'b0;
ap_reg_ppstg_tmp_15_reg_5272_pp1_it1[47] <= 1'b0;
ap_reg_ppstg_tmp_15_reg_5272_pp1_it1[48] <= 1'b0;
ap_reg_ppstg_tmp_15_reg_5272_pp1_it1[49] <= 1'b0;
ap_reg_ppstg_tmp_15_reg_5272_pp1_it1[50] <= 1'b0;
ap_reg_ppstg_tmp_15_reg_5272_pp1_it1[51] <= 1'b0;
ap_reg_ppstg_tmp_15_reg_5272_pp1_it1[52] <= 1'b0;
ap_reg_ppstg_tmp_15_reg_5272_pp1_it1[53] <= 1'b0;
ap_reg_ppstg_tmp_15_reg_5272_pp1_it1[54] <= 1'b0;
ap_reg_ppstg_tmp_15_reg_5272_pp1_it1[55] <= 1'b0;
ap_reg_ppstg_tmp_15_reg_5272_pp1_it1[56] <= 1'b0;
ap_reg_ppstg_tmp_15_reg_5272_pp1_it1[57] <= 1'b0;
ap_reg_ppstg_tmp_15_reg_5272_pp1_it1[58] <= 1'b0;
ap_reg_ppstg_tmp_15_reg_5272_pp1_it1[59] <= 1'b0;
ap_reg_ppstg_tmp_15_reg_5272_pp1_it1[60] <= 1'b0;
ap_reg_ppstg_tmp_15_reg_5272_pp1_it1[61] <= 1'b0;
ap_reg_ppstg_tmp_15_reg_5272_pp1_it1[62] <= 1'b0;
ap_reg_ppstg_tmp_15_reg_5272_pp1_it1[63] <= 1'b0;
end
always @ (ap_clk)
begin
tmp_20_reg_5287[14] <= 1'b0;
tmp_20_reg_5287[15] <= 1'b0;
tmp_20_reg_5287[16] <= 1'b0;
tmp_20_reg_5287[17] <= 1'b0;
tmp_20_reg_5287[18] <= 1'b0;
tmp_20_reg_5287[19] <= 1'b0;
tmp_20_reg_5287[20] <= 1'b0;
tmp_20_reg_5287[21] <= 1'b0;
tmp_20_reg_5287[22] <= 1'b0;
tmp_20_reg_5287[23] <= 1'b0;
tmp_20_reg_5287[24] <= 1'b0;
tmp_20_reg_5287[25] <= 1'b0;
tmp_20_reg_5287[26] <= 1'b0;
tmp_20_reg_5287[27] <= 1'b0;
tmp_20_reg_5287[28] <= 1'b0;
tmp_20_reg_5287[29] <= 1'b0;
tmp_20_reg_5287[30] <= 1'b0;
tmp_20_reg_5287[31] <= 1'b0;
tmp_20_reg_5287[32] <= 1'b0;
tmp_20_reg_5287[33] <= 1'b0;
tmp_20_reg_5287[34] <= 1'b0;
tmp_20_reg_5287[35] <= 1'b0;
tmp_20_reg_5287[36] <= 1'b0;
tmp_20_reg_5287[37] <= 1'b0;
tmp_20_reg_5287[38] <= 1'b0;
tmp_20_reg_5287[39] <= 1'b0;
tmp_20_reg_5287[40] <= 1'b0;
tmp_20_reg_5287[41] <= 1'b0;
tmp_20_reg_5287[42] <= 1'b0;
tmp_20_reg_5287[43] <= 1'b0;
tmp_20_reg_5287[44] <= 1'b0;
tmp_20_reg_5287[45] <= 1'b0;
tmp_20_reg_5287[46] <= 1'b0;
tmp_20_reg_5287[47] <= 1'b0;
tmp_20_reg_5287[48] <= 1'b0;
tmp_20_reg_5287[49] <= 1'b0;
tmp_20_reg_5287[50] <= 1'b0;
tmp_20_reg_5287[51] <= 1'b0;
tmp_20_reg_5287[52] <= 1'b0;
tmp_20_reg_5287[53] <= 1'b0;
tmp_20_reg_5287[54] <= 1'b0;
tmp_20_reg_5287[55] <= 1'b0;
tmp_20_reg_5287[56] <= 1'b0;
tmp_20_reg_5287[57] <= 1'b0;
tmp_20_reg_5287[58] <= 1'b0;
tmp_20_reg_5287[59] <= 1'b0;
tmp_20_reg_5287[60] <= 1'b0;
tmp_20_reg_5287[61] <= 1'b0;
tmp_20_reg_5287[62] <= 1'b0;
tmp_20_reg_5287[63] <= 1'b0;
end
always @ (ap_clk)
begin
ap_reg_ppstg_tmp_20_reg_5287_pp1_it1[14] <= 1'b0;
ap_reg_ppstg_tmp_20_reg_5287_pp1_it1[15] <= 1'b0;
ap_reg_ppstg_tmp_20_reg_5287_pp1_it1[16] <= 1'b0;
ap_reg_ppstg_tmp_20_reg_5287_pp1_it1[17] <= 1'b0;
ap_reg_ppstg_tmp_20_reg_5287_pp1_it1[18] <= 1'b0;
ap_reg_ppstg_tmp_20_reg_5287_pp1_it1[19] <= 1'b0;
ap_reg_ppstg_tmp_20_reg_5287_pp1_it1[20] <= 1'b0;
ap_reg_ppstg_tmp_20_reg_5287_pp1_it1[21] <= 1'b0;
ap_reg_ppstg_tmp_20_reg_5287_pp1_it1[22] <= 1'b0;
ap_reg_ppstg_tmp_20_reg_5287_pp1_it1[23] <= 1'b0;
ap_reg_ppstg_tmp_20_reg_5287_pp1_it1[24] <= 1'b0;
ap_reg_ppstg_tmp_20_reg_5287_pp1_it1[25] <= 1'b0;
ap_reg_ppstg_tmp_20_reg_5287_pp1_it1[26] <= 1'b0;
ap_reg_ppstg_tmp_20_reg_5287_pp1_it1[27] <= 1'b0;
ap_reg_ppstg_tmp_20_reg_5287_pp1_it1[28] <= 1'b0;
ap_reg_ppstg_tmp_20_reg_5287_pp1_it1[29] <= 1'b0;
ap_reg_ppstg_tmp_20_reg_5287_pp1_it1[30] <= 1'b0;
ap_reg_ppstg_tmp_20_reg_5287_pp1_it1[31] <= 1'b0;
ap_reg_ppstg_tmp_20_reg_5287_pp1_it1[32] <= 1'b0;
ap_reg_ppstg_tmp_20_reg_5287_pp1_it1[33] <= 1'b0;
ap_reg_ppstg_tmp_20_reg_5287_pp1_it1[34] <= 1'b0;
ap_reg_ppstg_tmp_20_reg_5287_pp1_it1[35] <= 1'b0;
ap_reg_ppstg_tmp_20_reg_5287_pp1_it1[36] <= 1'b0;
ap_reg_ppstg_tmp_20_reg_5287_pp1_it1[37] <= 1'b0;
ap_reg_ppstg_tmp_20_reg_5287_pp1_it1[38] <= 1'b0;
ap_reg_ppstg_tmp_20_reg_5287_pp1_it1[39] <= 1'b0;
ap_reg_ppstg_tmp_20_reg_5287_pp1_it1[40] <= 1'b0;
ap_reg_ppstg_tmp_20_reg_5287_pp1_it1[41] <= 1'b0;
ap_reg_ppstg_tmp_20_reg_5287_pp1_it1[42] <= 1'b0;
ap_reg_ppstg_tmp_20_reg_5287_pp1_it1[43] <= 1'b0;
ap_reg_ppstg_tmp_20_reg_5287_pp1_it1[44] <= 1'b0;
ap_reg_ppstg_tmp_20_reg_5287_pp1_it1[45] <= 1'b0;
ap_reg_ppstg_tmp_20_reg_5287_pp1_it1[46] <= 1'b0;
ap_reg_ppstg_tmp_20_reg_5287_pp1_it1[47] <= 1'b0;
ap_reg_ppstg_tmp_20_reg_5287_pp1_it1[48] <= 1'b0;
ap_reg_ppstg_tmp_20_reg_5287_pp1_it1[49] <= 1'b0;
ap_reg_ppstg_tmp_20_reg_5287_pp1_it1[50] <= 1'b0;
ap_reg_ppstg_tmp_20_reg_5287_pp1_it1[51] <= 1'b0;
ap_reg_ppstg_tmp_20_reg_5287_pp1_it1[52] <= 1'b0;
ap_reg_ppstg_tmp_20_reg_5287_pp1_it1[53] <= 1'b0;
ap_reg_ppstg_tmp_20_reg_5287_pp1_it1[54] <= 1'b0;
ap_reg_ppstg_tmp_20_reg_5287_pp1_it1[55] <= 1'b0;
ap_reg_ppstg_tmp_20_reg_5287_pp1_it1[56] <= 1'b0;
ap_reg_ppstg_tmp_20_reg_5287_pp1_it1[57] <= 1'b0;
ap_reg_ppstg_tmp_20_reg_5287_pp1_it1[58] <= 1'b0;
ap_reg_ppstg_tmp_20_reg_5287_pp1_it1[59] <= 1'b0;
ap_reg_ppstg_tmp_20_reg_5287_pp1_it1[60] <= 1'b0;
ap_reg_ppstg_tmp_20_reg_5287_pp1_it1[61] <= 1'b0;
ap_reg_ppstg_tmp_20_reg_5287_pp1_it1[62] <= 1'b0;
ap_reg_ppstg_tmp_20_reg_5287_pp1_it1[63] <= 1'b0;
end
always @ (ap_clk)
begin
b_addr4_reg_5297[1] <= 1'b1;
end
always @ (ap_clk)
begin
tmp_28_reg_5332[14] <= 1'b0;
tmp_28_reg_5332[15] <= 1'b0;
tmp_28_reg_5332[16] <= 1'b0;
tmp_28_reg_5332[17] <= 1'b0;
tmp_28_reg_5332[18] <= 1'b0;
tmp_28_reg_5332[19] <= 1'b0;
tmp_28_reg_5332[20] <= 1'b0;
tmp_28_reg_5332[21] <= 1'b0;
tmp_28_reg_5332[22] <= 1'b0;
tmp_28_reg_5332[23] <= 1'b0;
tmp_28_reg_5332[24] <= 1'b0;
tmp_28_reg_5332[25] <= 1'b0;
tmp_28_reg_5332[26] <= 1'b0;
tmp_28_reg_5332[27] <= 1'b0;
tmp_28_reg_5332[28] <= 1'b0;
tmp_28_reg_5332[29] <= 1'b0;
tmp_28_reg_5332[30] <= 1'b0;
tmp_28_reg_5332[31] <= 1'b0;
tmp_28_reg_5332[32] <= 1'b0;
tmp_28_reg_5332[33] <= 1'b0;
tmp_28_reg_5332[34] <= 1'b0;
tmp_28_reg_5332[35] <= 1'b0;
tmp_28_reg_5332[36] <= 1'b0;
tmp_28_reg_5332[37] <= 1'b0;
tmp_28_reg_5332[38] <= 1'b0;
tmp_28_reg_5332[39] <= 1'b0;
tmp_28_reg_5332[40] <= 1'b0;
tmp_28_reg_5332[41] <= 1'b0;
tmp_28_reg_5332[42] <= 1'b0;
tmp_28_reg_5332[43] <= 1'b0;
tmp_28_reg_5332[44] <= 1'b0;
tmp_28_reg_5332[45] <= 1'b0;
tmp_28_reg_5332[46] <= 1'b0;
tmp_28_reg_5332[47] <= 1'b0;
tmp_28_reg_5332[48] <= 1'b0;
tmp_28_reg_5332[49] <= 1'b0;
tmp_28_reg_5332[50] <= 1'b0;
tmp_28_reg_5332[51] <= 1'b0;
tmp_28_reg_5332[52] <= 1'b0;
tmp_28_reg_5332[53] <= 1'b0;
tmp_28_reg_5332[54] <= 1'b0;
tmp_28_reg_5332[55] <= 1'b0;
tmp_28_reg_5332[56] <= 1'b0;
tmp_28_reg_5332[57] <= 1'b0;
tmp_28_reg_5332[58] <= 1'b0;
tmp_28_reg_5332[59] <= 1'b0;
tmp_28_reg_5332[60] <= 1'b0;
tmp_28_reg_5332[61] <= 1'b0;
tmp_28_reg_5332[62] <= 1'b0;
tmp_28_reg_5332[63] <= 1'b0;
end
always @ (ap_clk)
begin
ap_reg_ppstg_tmp_28_reg_5332_pp1_it1[14] <= 1'b0;
ap_reg_ppstg_tmp_28_reg_5332_pp1_it1[15] <= 1'b0;
ap_reg_ppstg_tmp_28_reg_5332_pp1_it1[16] <= 1'b0;
ap_reg_ppstg_tmp_28_reg_5332_pp1_it1[17] <= 1'b0;
ap_reg_ppstg_tmp_28_reg_5332_pp1_it1[18] <= 1'b0;
ap_reg_ppstg_tmp_28_reg_5332_pp1_it1[19] <= 1'b0;
ap_reg_ppstg_tmp_28_reg_5332_pp1_it1[20] <= 1'b0;
ap_reg_ppstg_tmp_28_reg_5332_pp1_it1[21] <= 1'b0;
ap_reg_ppstg_tmp_28_reg_5332_pp1_it1[22] <= 1'b0;
ap_reg_ppstg_tmp_28_reg_5332_pp1_it1[23] <= 1'b0;
ap_reg_ppstg_tmp_28_reg_5332_pp1_it1[24] <= 1'b0;
ap_reg_ppstg_tmp_28_reg_5332_pp1_it1[25] <= 1'b0;
ap_reg_ppstg_tmp_28_reg_5332_pp1_it1[26] <= 1'b0;
ap_reg_ppstg_tmp_28_reg_5332_pp1_it1[27] <= 1'b0;
ap_reg_ppstg_tmp_28_reg_5332_pp1_it1[28] <= 1'b0;
ap_reg_ppstg_tmp_28_reg_5332_pp1_it1[29] <= 1'b0;
ap_reg_ppstg_tmp_28_reg_5332_pp1_it1[30] <= 1'b0;
ap_reg_ppstg_tmp_28_reg_5332_pp1_it1[31] <= 1'b0;
ap_reg_ppstg_tmp_28_reg_5332_pp1_it1[32] <= 1'b0;
ap_reg_ppstg_tmp_28_reg_5332_pp1_it1[33] <= 1'b0;
ap_reg_ppstg_tmp_28_reg_5332_pp1_it1[34] <= 1'b0;
ap_reg_ppstg_tmp_28_reg_5332_pp1_it1[35] <= 1'b0;
ap_reg_ppstg_tmp_28_reg_5332_pp1_it1[36] <= 1'b0;
ap_reg_ppstg_tmp_28_reg_5332_pp1_it1[37] <= 1'b0;
ap_reg_ppstg_tmp_28_reg_5332_pp1_it1[38] <= 1'b0;
ap_reg_ppstg_tmp_28_reg_5332_pp1_it1[39] <= 1'b0;
ap_reg_ppstg_tmp_28_reg_5332_pp1_it1[40] <= 1'b0;
ap_reg_ppstg_tmp_28_reg_5332_pp1_it1[41] <= 1'b0;
ap_reg_ppstg_tmp_28_reg_5332_pp1_it1[42] <= 1'b0;
ap_reg_ppstg_tmp_28_reg_5332_pp1_it1[43] <= 1'b0;
ap_reg_ppstg_tmp_28_reg_5332_pp1_it1[44] <= 1'b0;
ap_reg_ppstg_tmp_28_reg_5332_pp1_it1[45] <= 1'b0;
ap_reg_ppstg_tmp_28_reg_5332_pp1_it1[46] <= 1'b0;
ap_reg_ppstg_tmp_28_reg_5332_pp1_it1[47] <= 1'b0;
ap_reg_ppstg_tmp_28_reg_5332_pp1_it1[48] <= 1'b0;
ap_reg_ppstg_tmp_28_reg_5332_pp1_it1[49] <= 1'b0;
ap_reg_ppstg_tmp_28_reg_5332_pp1_it1[50] <= 1'b0;
ap_reg_ppstg_tmp_28_reg_5332_pp1_it1[51] <= 1'b0;
ap_reg_ppstg_tmp_28_reg_5332_pp1_it1[52] <= 1'b0;
ap_reg_ppstg_tmp_28_reg_5332_pp1_it1[53] <= 1'b0;
ap_reg_ppstg_tmp_28_reg_5332_pp1_it1[54] <= 1'b0;
ap_reg_ppstg_tmp_28_reg_5332_pp1_it1[55] <= 1'b0;
ap_reg_ppstg_tmp_28_reg_5332_pp1_it1[56] <= 1'b0;
ap_reg_ppstg_tmp_28_reg_5332_pp1_it1[57] <= 1'b0;
ap_reg_ppstg_tmp_28_reg_5332_pp1_it1[58] <= 1'b0;
ap_reg_ppstg_tmp_28_reg_5332_pp1_it1[59] <= 1'b0;
ap_reg_ppstg_tmp_28_reg_5332_pp1_it1[60] <= 1'b0;
ap_reg_ppstg_tmp_28_reg_5332_pp1_it1[61] <= 1'b0;
ap_reg_ppstg_tmp_28_reg_5332_pp1_it1[62] <= 1'b0;
ap_reg_ppstg_tmp_28_reg_5332_pp1_it1[63] <= 1'b0;
end
always @ (ap_clk)
begin
tmp_36_reg_5347[14] <= 1'b0;
tmp_36_reg_5347[15] <= 1'b0;
tmp_36_reg_5347[16] <= 1'b0;
tmp_36_reg_5347[17] <= 1'b0;
tmp_36_reg_5347[18] <= 1'b0;
tmp_36_reg_5347[19] <= 1'b0;
tmp_36_reg_5347[20] <= 1'b0;
tmp_36_reg_5347[21] <= 1'b0;
tmp_36_reg_5347[22] <= 1'b0;
tmp_36_reg_5347[23] <= 1'b0;
tmp_36_reg_5347[24] <= 1'b0;
tmp_36_reg_5347[25] <= 1'b0;
tmp_36_reg_5347[26] <= 1'b0;
tmp_36_reg_5347[27] <= 1'b0;
tmp_36_reg_5347[28] <= 1'b0;
tmp_36_reg_5347[29] <= 1'b0;
tmp_36_reg_5347[30] <= 1'b0;
tmp_36_reg_5347[31] <= 1'b0;
tmp_36_reg_5347[32] <= 1'b0;
tmp_36_reg_5347[33] <= 1'b0;
tmp_36_reg_5347[34] <= 1'b0;
tmp_36_reg_5347[35] <= 1'b0;
tmp_36_reg_5347[36] <= 1'b0;
tmp_36_reg_5347[37] <= 1'b0;
tmp_36_reg_5347[38] <= 1'b0;
tmp_36_reg_5347[39] <= 1'b0;
tmp_36_reg_5347[40] <= 1'b0;
tmp_36_reg_5347[41] <= 1'b0;
tmp_36_reg_5347[42] <= 1'b0;
tmp_36_reg_5347[43] <= 1'b0;
tmp_36_reg_5347[44] <= 1'b0;
tmp_36_reg_5347[45] <= 1'b0;
tmp_36_reg_5347[46] <= 1'b0;
tmp_36_reg_5347[47] <= 1'b0;
tmp_36_reg_5347[48] <= 1'b0;
tmp_36_reg_5347[49] <= 1'b0;
tmp_36_reg_5347[50] <= 1'b0;
tmp_36_reg_5347[51] <= 1'b0;
tmp_36_reg_5347[52] <= 1'b0;
tmp_36_reg_5347[53] <= 1'b0;
tmp_36_reg_5347[54] <= 1'b0;
tmp_36_reg_5347[55] <= 1'b0;
tmp_36_reg_5347[56] <= 1'b0;
tmp_36_reg_5347[57] <= 1'b0;
tmp_36_reg_5347[58] <= 1'b0;
tmp_36_reg_5347[59] <= 1'b0;
tmp_36_reg_5347[60] <= 1'b0;
tmp_36_reg_5347[61] <= 1'b0;
tmp_36_reg_5347[62] <= 1'b0;
tmp_36_reg_5347[63] <= 1'b0;
end
always @ (ap_clk)
begin
ap_reg_ppstg_tmp_36_reg_5347_pp1_it1[14] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_5347_pp1_it1[15] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_5347_pp1_it1[16] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_5347_pp1_it1[17] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_5347_pp1_it1[18] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_5347_pp1_it1[19] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_5347_pp1_it1[20] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_5347_pp1_it1[21] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_5347_pp1_it1[22] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_5347_pp1_it1[23] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_5347_pp1_it1[24] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_5347_pp1_it1[25] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_5347_pp1_it1[26] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_5347_pp1_it1[27] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_5347_pp1_it1[28] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_5347_pp1_it1[29] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_5347_pp1_it1[30] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_5347_pp1_it1[31] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_5347_pp1_it1[32] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_5347_pp1_it1[33] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_5347_pp1_it1[34] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_5347_pp1_it1[35] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_5347_pp1_it1[36] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_5347_pp1_it1[37] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_5347_pp1_it1[38] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_5347_pp1_it1[39] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_5347_pp1_it1[40] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_5347_pp1_it1[41] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_5347_pp1_it1[42] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_5347_pp1_it1[43] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_5347_pp1_it1[44] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_5347_pp1_it1[45] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_5347_pp1_it1[46] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_5347_pp1_it1[47] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_5347_pp1_it1[48] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_5347_pp1_it1[49] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_5347_pp1_it1[50] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_5347_pp1_it1[51] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_5347_pp1_it1[52] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_5347_pp1_it1[53] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_5347_pp1_it1[54] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_5347_pp1_it1[55] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_5347_pp1_it1[56] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_5347_pp1_it1[57] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_5347_pp1_it1[58] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_5347_pp1_it1[59] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_5347_pp1_it1[60] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_5347_pp1_it1[61] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_5347_pp1_it1[62] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_5347_pp1_it1[63] <= 1'b0;
end
always @ (ap_clk)
begin
b_addr8_reg_5357[2] <= 1'b1;
end
always @ (ap_clk)
begin
tmp_44_reg_5367[14] <= 1'b0;
tmp_44_reg_5367[15] <= 1'b0;
tmp_44_reg_5367[16] <= 1'b0;
tmp_44_reg_5367[17] <= 1'b0;
tmp_44_reg_5367[18] <= 1'b0;
tmp_44_reg_5367[19] <= 1'b0;
tmp_44_reg_5367[20] <= 1'b0;
tmp_44_reg_5367[21] <= 1'b0;
tmp_44_reg_5367[22] <= 1'b0;
tmp_44_reg_5367[23] <= 1'b0;
tmp_44_reg_5367[24] <= 1'b0;
tmp_44_reg_5367[25] <= 1'b0;
tmp_44_reg_5367[26] <= 1'b0;
tmp_44_reg_5367[27] <= 1'b0;
tmp_44_reg_5367[28] <= 1'b0;
tmp_44_reg_5367[29] <= 1'b0;
tmp_44_reg_5367[30] <= 1'b0;
tmp_44_reg_5367[31] <= 1'b0;
tmp_44_reg_5367[32] <= 1'b0;
tmp_44_reg_5367[33] <= 1'b0;
tmp_44_reg_5367[34] <= 1'b0;
tmp_44_reg_5367[35] <= 1'b0;
tmp_44_reg_5367[36] <= 1'b0;
tmp_44_reg_5367[37] <= 1'b0;
tmp_44_reg_5367[38] <= 1'b0;
tmp_44_reg_5367[39] <= 1'b0;
tmp_44_reg_5367[40] <= 1'b0;
tmp_44_reg_5367[41] <= 1'b0;
tmp_44_reg_5367[42] <= 1'b0;
tmp_44_reg_5367[43] <= 1'b0;
tmp_44_reg_5367[44] <= 1'b0;
tmp_44_reg_5367[45] <= 1'b0;
tmp_44_reg_5367[46] <= 1'b0;
tmp_44_reg_5367[47] <= 1'b0;
tmp_44_reg_5367[48] <= 1'b0;
tmp_44_reg_5367[49] <= 1'b0;
tmp_44_reg_5367[50] <= 1'b0;
tmp_44_reg_5367[51] <= 1'b0;
tmp_44_reg_5367[52] <= 1'b0;
tmp_44_reg_5367[53] <= 1'b0;
tmp_44_reg_5367[54] <= 1'b0;
tmp_44_reg_5367[55] <= 1'b0;
tmp_44_reg_5367[56] <= 1'b0;
tmp_44_reg_5367[57] <= 1'b0;
tmp_44_reg_5367[58] <= 1'b0;
tmp_44_reg_5367[59] <= 1'b0;
tmp_44_reg_5367[60] <= 1'b0;
tmp_44_reg_5367[61] <= 1'b0;
tmp_44_reg_5367[62] <= 1'b0;
tmp_44_reg_5367[63] <= 1'b0;
end
always @ (ap_clk)
begin
ap_reg_ppstg_tmp_44_reg_5367_pp1_it1[14] <= 1'b0;
ap_reg_ppstg_tmp_44_reg_5367_pp1_it1[15] <= 1'b0;
ap_reg_ppstg_tmp_44_reg_5367_pp1_it1[16] <= 1'b0;
ap_reg_ppstg_tmp_44_reg_5367_pp1_it1[17] <= 1'b0;
ap_reg_ppstg_tmp_44_reg_5367_pp1_it1[18] <= 1'b0;
ap_reg_ppstg_tmp_44_reg_5367_pp1_it1[19] <= 1'b0;
ap_reg_ppstg_tmp_44_reg_5367_pp1_it1[20] <= 1'b0;
ap_reg_ppstg_tmp_44_reg_5367_pp1_it1[21] <= 1'b0;
ap_reg_ppstg_tmp_44_reg_5367_pp1_it1[22] <= 1'b0;
ap_reg_ppstg_tmp_44_reg_5367_pp1_it1[23] <= 1'b0;
ap_reg_ppstg_tmp_44_reg_5367_pp1_it1[24] <= 1'b0;
ap_reg_ppstg_tmp_44_reg_5367_pp1_it1[25] <= 1'b0;
ap_reg_ppstg_tmp_44_reg_5367_pp1_it1[26] <= 1'b0;
ap_reg_ppstg_tmp_44_reg_5367_pp1_it1[27] <= 1'b0;
ap_reg_ppstg_tmp_44_reg_5367_pp1_it1[28] <= 1'b0;
ap_reg_ppstg_tmp_44_reg_5367_pp1_it1[29] <= 1'b0;
ap_reg_ppstg_tmp_44_reg_5367_pp1_it1[30] <= 1'b0;
ap_reg_ppstg_tmp_44_reg_5367_pp1_it1[31] <= 1'b0;
ap_reg_ppstg_tmp_44_reg_5367_pp1_it1[32] <= 1'b0;
ap_reg_ppstg_tmp_44_reg_5367_pp1_it1[33] <= 1'b0;
ap_reg_ppstg_tmp_44_reg_5367_pp1_it1[34] <= 1'b0;
ap_reg_ppstg_tmp_44_reg_5367_pp1_it1[35] <= 1'b0;
ap_reg_ppstg_tmp_44_reg_5367_pp1_it1[36] <= 1'b0;
ap_reg_ppstg_tmp_44_reg_5367_pp1_it1[37] <= 1'b0;
ap_reg_ppstg_tmp_44_reg_5367_pp1_it1[38] <= 1'b0;
ap_reg_ppstg_tmp_44_reg_5367_pp1_it1[39] <= 1'b0;
ap_reg_ppstg_tmp_44_reg_5367_pp1_it1[40] <= 1'b0;
ap_reg_ppstg_tmp_44_reg_5367_pp1_it1[41] <= 1'b0;
ap_reg_ppstg_tmp_44_reg_5367_pp1_it1[42] <= 1'b0;
ap_reg_ppstg_tmp_44_reg_5367_pp1_it1[43] <= 1'b0;
ap_reg_ppstg_tmp_44_reg_5367_pp1_it1[44] <= 1'b0;
ap_reg_ppstg_tmp_44_reg_5367_pp1_it1[45] <= 1'b0;
ap_reg_ppstg_tmp_44_reg_5367_pp1_it1[46] <= 1'b0;
ap_reg_ppstg_tmp_44_reg_5367_pp1_it1[47] <= 1'b0;
ap_reg_ppstg_tmp_44_reg_5367_pp1_it1[48] <= 1'b0;
ap_reg_ppstg_tmp_44_reg_5367_pp1_it1[49] <= 1'b0;
ap_reg_ppstg_tmp_44_reg_5367_pp1_it1[50] <= 1'b0;
ap_reg_ppstg_tmp_44_reg_5367_pp1_it1[51] <= 1'b0;
ap_reg_ppstg_tmp_44_reg_5367_pp1_it1[52] <= 1'b0;
ap_reg_ppstg_tmp_44_reg_5367_pp1_it1[53] <= 1'b0;
ap_reg_ppstg_tmp_44_reg_5367_pp1_it1[54] <= 1'b0;
ap_reg_ppstg_tmp_44_reg_5367_pp1_it1[55] <= 1'b0;
ap_reg_ppstg_tmp_44_reg_5367_pp1_it1[56] <= 1'b0;
ap_reg_ppstg_tmp_44_reg_5367_pp1_it1[57] <= 1'b0;
ap_reg_ppstg_tmp_44_reg_5367_pp1_it1[58] <= 1'b0;
ap_reg_ppstg_tmp_44_reg_5367_pp1_it1[59] <= 1'b0;
ap_reg_ppstg_tmp_44_reg_5367_pp1_it1[60] <= 1'b0;
ap_reg_ppstg_tmp_44_reg_5367_pp1_it1[61] <= 1'b0;
ap_reg_ppstg_tmp_44_reg_5367_pp1_it1[62] <= 1'b0;
ap_reg_ppstg_tmp_44_reg_5367_pp1_it1[63] <= 1'b0;
end
always @ (ap_clk)
begin
ap_reg_ppstg_tmp_44_reg_5367_pp1_it2[14] <= 1'b0;
ap_reg_ppstg_tmp_44_reg_5367_pp1_it2[15] <= 1'b0;
ap_reg_ppstg_tmp_44_reg_5367_pp1_it2[16] <= 1'b0;
ap_reg_ppstg_tmp_44_reg_5367_pp1_it2[17] <= 1'b0;
ap_reg_ppstg_tmp_44_reg_5367_pp1_it2[18] <= 1'b0;
ap_reg_ppstg_tmp_44_reg_5367_pp1_it2[19] <= 1'b0;
ap_reg_ppstg_tmp_44_reg_5367_pp1_it2[20] <= 1'b0;
ap_reg_ppstg_tmp_44_reg_5367_pp1_it2[21] <= 1'b0;
ap_reg_ppstg_tmp_44_reg_5367_pp1_it2[22] <= 1'b0;
ap_reg_ppstg_tmp_44_reg_5367_pp1_it2[23] <= 1'b0;
ap_reg_ppstg_tmp_44_reg_5367_pp1_it2[24] <= 1'b0;
ap_reg_ppstg_tmp_44_reg_5367_pp1_it2[25] <= 1'b0;
ap_reg_ppstg_tmp_44_reg_5367_pp1_it2[26] <= 1'b0;
ap_reg_ppstg_tmp_44_reg_5367_pp1_it2[27] <= 1'b0;
ap_reg_ppstg_tmp_44_reg_5367_pp1_it2[28] <= 1'b0;
ap_reg_ppstg_tmp_44_reg_5367_pp1_it2[29] <= 1'b0;
ap_reg_ppstg_tmp_44_reg_5367_pp1_it2[30] <= 1'b0;
ap_reg_ppstg_tmp_44_reg_5367_pp1_it2[31] <= 1'b0;
ap_reg_ppstg_tmp_44_reg_5367_pp1_it2[32] <= 1'b0;
ap_reg_ppstg_tmp_44_reg_5367_pp1_it2[33] <= 1'b0;
ap_reg_ppstg_tmp_44_reg_5367_pp1_it2[34] <= 1'b0;
ap_reg_ppstg_tmp_44_reg_5367_pp1_it2[35] <= 1'b0;
ap_reg_ppstg_tmp_44_reg_5367_pp1_it2[36] <= 1'b0;
ap_reg_ppstg_tmp_44_reg_5367_pp1_it2[37] <= 1'b0;
ap_reg_ppstg_tmp_44_reg_5367_pp1_it2[38] <= 1'b0;
ap_reg_ppstg_tmp_44_reg_5367_pp1_it2[39] <= 1'b0;
ap_reg_ppstg_tmp_44_reg_5367_pp1_it2[40] <= 1'b0;
ap_reg_ppstg_tmp_44_reg_5367_pp1_it2[41] <= 1'b0;
ap_reg_ppstg_tmp_44_reg_5367_pp1_it2[42] <= 1'b0;
ap_reg_ppstg_tmp_44_reg_5367_pp1_it2[43] <= 1'b0;
ap_reg_ppstg_tmp_44_reg_5367_pp1_it2[44] <= 1'b0;
ap_reg_ppstg_tmp_44_reg_5367_pp1_it2[45] <= 1'b0;
ap_reg_ppstg_tmp_44_reg_5367_pp1_it2[46] <= 1'b0;
ap_reg_ppstg_tmp_44_reg_5367_pp1_it2[47] <= 1'b0;
ap_reg_ppstg_tmp_44_reg_5367_pp1_it2[48] <= 1'b0;
ap_reg_ppstg_tmp_44_reg_5367_pp1_it2[49] <= 1'b0;
ap_reg_ppstg_tmp_44_reg_5367_pp1_it2[50] <= 1'b0;
ap_reg_ppstg_tmp_44_reg_5367_pp1_it2[51] <= 1'b0;
ap_reg_ppstg_tmp_44_reg_5367_pp1_it2[52] <= 1'b0;
ap_reg_ppstg_tmp_44_reg_5367_pp1_it2[53] <= 1'b0;
ap_reg_ppstg_tmp_44_reg_5367_pp1_it2[54] <= 1'b0;
ap_reg_ppstg_tmp_44_reg_5367_pp1_it2[55] <= 1'b0;
ap_reg_ppstg_tmp_44_reg_5367_pp1_it2[56] <= 1'b0;
ap_reg_ppstg_tmp_44_reg_5367_pp1_it2[57] <= 1'b0;
ap_reg_ppstg_tmp_44_reg_5367_pp1_it2[58] <= 1'b0;
ap_reg_ppstg_tmp_44_reg_5367_pp1_it2[59] <= 1'b0;
ap_reg_ppstg_tmp_44_reg_5367_pp1_it2[60] <= 1'b0;
ap_reg_ppstg_tmp_44_reg_5367_pp1_it2[61] <= 1'b0;
ap_reg_ppstg_tmp_44_reg_5367_pp1_it2[62] <= 1'b0;
ap_reg_ppstg_tmp_44_reg_5367_pp1_it2[63] <= 1'b0;
end
always @ (ap_clk)
begin
tmp_47_reg_5407[14] <= 1'b0;
tmp_47_reg_5407[15] <= 1'b0;
tmp_47_reg_5407[16] <= 1'b0;
tmp_47_reg_5407[17] <= 1'b0;
tmp_47_reg_5407[18] <= 1'b0;
tmp_47_reg_5407[19] <= 1'b0;
tmp_47_reg_5407[20] <= 1'b0;
tmp_47_reg_5407[21] <= 1'b0;
tmp_47_reg_5407[22] <= 1'b0;
tmp_47_reg_5407[23] <= 1'b0;
tmp_47_reg_5407[24] <= 1'b0;
tmp_47_reg_5407[25] <= 1'b0;
tmp_47_reg_5407[26] <= 1'b0;
tmp_47_reg_5407[27] <= 1'b0;
tmp_47_reg_5407[28] <= 1'b0;
tmp_47_reg_5407[29] <= 1'b0;
tmp_47_reg_5407[30] <= 1'b0;
tmp_47_reg_5407[31] <= 1'b0;
tmp_47_reg_5407[32] <= 1'b0;
tmp_47_reg_5407[33] <= 1'b0;
tmp_47_reg_5407[34] <= 1'b0;
tmp_47_reg_5407[35] <= 1'b0;
tmp_47_reg_5407[36] <= 1'b0;
tmp_47_reg_5407[37] <= 1'b0;
tmp_47_reg_5407[38] <= 1'b0;
tmp_47_reg_5407[39] <= 1'b0;
tmp_47_reg_5407[40] <= 1'b0;
tmp_47_reg_5407[41] <= 1'b0;
tmp_47_reg_5407[42] <= 1'b0;
tmp_47_reg_5407[43] <= 1'b0;
tmp_47_reg_5407[44] <= 1'b0;
tmp_47_reg_5407[45] <= 1'b0;
tmp_47_reg_5407[46] <= 1'b0;
tmp_47_reg_5407[47] <= 1'b0;
tmp_47_reg_5407[48] <= 1'b0;
tmp_47_reg_5407[49] <= 1'b0;
tmp_47_reg_5407[50] <= 1'b0;
tmp_47_reg_5407[51] <= 1'b0;
tmp_47_reg_5407[52] <= 1'b0;
tmp_47_reg_5407[53] <= 1'b0;
tmp_47_reg_5407[54] <= 1'b0;
tmp_47_reg_5407[55] <= 1'b0;
tmp_47_reg_5407[56] <= 1'b0;
tmp_47_reg_5407[57] <= 1'b0;
tmp_47_reg_5407[58] <= 1'b0;
tmp_47_reg_5407[59] <= 1'b0;
tmp_47_reg_5407[60] <= 1'b0;
tmp_47_reg_5407[61] <= 1'b0;
tmp_47_reg_5407[62] <= 1'b0;
tmp_47_reg_5407[63] <= 1'b0;
end
always @ (ap_clk)
begin
ap_reg_ppstg_tmp_47_reg_5407_pp1_it2[14] <= 1'b0;
ap_reg_ppstg_tmp_47_reg_5407_pp1_it2[15] <= 1'b0;
ap_reg_ppstg_tmp_47_reg_5407_pp1_it2[16] <= 1'b0;
ap_reg_ppstg_tmp_47_reg_5407_pp1_it2[17] <= 1'b0;
ap_reg_ppstg_tmp_47_reg_5407_pp1_it2[18] <= 1'b0;
ap_reg_ppstg_tmp_47_reg_5407_pp1_it2[19] <= 1'b0;
ap_reg_ppstg_tmp_47_reg_5407_pp1_it2[20] <= 1'b0;
ap_reg_ppstg_tmp_47_reg_5407_pp1_it2[21] <= 1'b0;
ap_reg_ppstg_tmp_47_reg_5407_pp1_it2[22] <= 1'b0;
ap_reg_ppstg_tmp_47_reg_5407_pp1_it2[23] <= 1'b0;
ap_reg_ppstg_tmp_47_reg_5407_pp1_it2[24] <= 1'b0;
ap_reg_ppstg_tmp_47_reg_5407_pp1_it2[25] <= 1'b0;
ap_reg_ppstg_tmp_47_reg_5407_pp1_it2[26] <= 1'b0;
ap_reg_ppstg_tmp_47_reg_5407_pp1_it2[27] <= 1'b0;
ap_reg_ppstg_tmp_47_reg_5407_pp1_it2[28] <= 1'b0;
ap_reg_ppstg_tmp_47_reg_5407_pp1_it2[29] <= 1'b0;
ap_reg_ppstg_tmp_47_reg_5407_pp1_it2[30] <= 1'b0;
ap_reg_ppstg_tmp_47_reg_5407_pp1_it2[31] <= 1'b0;
ap_reg_ppstg_tmp_47_reg_5407_pp1_it2[32] <= 1'b0;
ap_reg_ppstg_tmp_47_reg_5407_pp1_it2[33] <= 1'b0;
ap_reg_ppstg_tmp_47_reg_5407_pp1_it2[34] <= 1'b0;
ap_reg_ppstg_tmp_47_reg_5407_pp1_it2[35] <= 1'b0;
ap_reg_ppstg_tmp_47_reg_5407_pp1_it2[36] <= 1'b0;
ap_reg_ppstg_tmp_47_reg_5407_pp1_it2[37] <= 1'b0;
ap_reg_ppstg_tmp_47_reg_5407_pp1_it2[38] <= 1'b0;
ap_reg_ppstg_tmp_47_reg_5407_pp1_it2[39] <= 1'b0;
ap_reg_ppstg_tmp_47_reg_5407_pp1_it2[40] <= 1'b0;
ap_reg_ppstg_tmp_47_reg_5407_pp1_it2[41] <= 1'b0;
ap_reg_ppstg_tmp_47_reg_5407_pp1_it2[42] <= 1'b0;
ap_reg_ppstg_tmp_47_reg_5407_pp1_it2[43] <= 1'b0;
ap_reg_ppstg_tmp_47_reg_5407_pp1_it2[44] <= 1'b0;
ap_reg_ppstg_tmp_47_reg_5407_pp1_it2[45] <= 1'b0;
ap_reg_ppstg_tmp_47_reg_5407_pp1_it2[46] <= 1'b0;
ap_reg_ppstg_tmp_47_reg_5407_pp1_it2[47] <= 1'b0;
ap_reg_ppstg_tmp_47_reg_5407_pp1_it2[48] <= 1'b0;
ap_reg_ppstg_tmp_47_reg_5407_pp1_it2[49] <= 1'b0;
ap_reg_ppstg_tmp_47_reg_5407_pp1_it2[50] <= 1'b0;
ap_reg_ppstg_tmp_47_reg_5407_pp1_it2[51] <= 1'b0;
ap_reg_ppstg_tmp_47_reg_5407_pp1_it2[52] <= 1'b0;
ap_reg_ppstg_tmp_47_reg_5407_pp1_it2[53] <= 1'b0;
ap_reg_ppstg_tmp_47_reg_5407_pp1_it2[54] <= 1'b0;
ap_reg_ppstg_tmp_47_reg_5407_pp1_it2[55] <= 1'b0;
ap_reg_ppstg_tmp_47_reg_5407_pp1_it2[56] <= 1'b0;
ap_reg_ppstg_tmp_47_reg_5407_pp1_it2[57] <= 1'b0;
ap_reg_ppstg_tmp_47_reg_5407_pp1_it2[58] <= 1'b0;
ap_reg_ppstg_tmp_47_reg_5407_pp1_it2[59] <= 1'b0;
ap_reg_ppstg_tmp_47_reg_5407_pp1_it2[60] <= 1'b0;
ap_reg_ppstg_tmp_47_reg_5407_pp1_it2[61] <= 1'b0;
ap_reg_ppstg_tmp_47_reg_5407_pp1_it2[62] <= 1'b0;
ap_reg_ppstg_tmp_47_reg_5407_pp1_it2[63] <= 1'b0;
end
always @ (ap_clk)
begin
tmp_51_reg_5417[14] <= 1'b0;
tmp_51_reg_5417[15] <= 1'b0;
tmp_51_reg_5417[16] <= 1'b0;
tmp_51_reg_5417[17] <= 1'b0;
tmp_51_reg_5417[18] <= 1'b0;
tmp_51_reg_5417[19] <= 1'b0;
tmp_51_reg_5417[20] <= 1'b0;
tmp_51_reg_5417[21] <= 1'b0;
tmp_51_reg_5417[22] <= 1'b0;
tmp_51_reg_5417[23] <= 1'b0;
tmp_51_reg_5417[24] <= 1'b0;
tmp_51_reg_5417[25] <= 1'b0;
tmp_51_reg_5417[26] <= 1'b0;
tmp_51_reg_5417[27] <= 1'b0;
tmp_51_reg_5417[28] <= 1'b0;
tmp_51_reg_5417[29] <= 1'b0;
tmp_51_reg_5417[30] <= 1'b0;
tmp_51_reg_5417[31] <= 1'b0;
tmp_51_reg_5417[32] <= 1'b0;
tmp_51_reg_5417[33] <= 1'b0;
tmp_51_reg_5417[34] <= 1'b0;
tmp_51_reg_5417[35] <= 1'b0;
tmp_51_reg_5417[36] <= 1'b0;
tmp_51_reg_5417[37] <= 1'b0;
tmp_51_reg_5417[38] <= 1'b0;
tmp_51_reg_5417[39] <= 1'b0;
tmp_51_reg_5417[40] <= 1'b0;
tmp_51_reg_5417[41] <= 1'b0;
tmp_51_reg_5417[42] <= 1'b0;
tmp_51_reg_5417[43] <= 1'b0;
tmp_51_reg_5417[44] <= 1'b0;
tmp_51_reg_5417[45] <= 1'b0;
tmp_51_reg_5417[46] <= 1'b0;
tmp_51_reg_5417[47] <= 1'b0;
tmp_51_reg_5417[48] <= 1'b0;
tmp_51_reg_5417[49] <= 1'b0;
tmp_51_reg_5417[50] <= 1'b0;
tmp_51_reg_5417[51] <= 1'b0;
tmp_51_reg_5417[52] <= 1'b0;
tmp_51_reg_5417[53] <= 1'b0;
tmp_51_reg_5417[54] <= 1'b0;
tmp_51_reg_5417[55] <= 1'b0;
tmp_51_reg_5417[56] <= 1'b0;
tmp_51_reg_5417[57] <= 1'b0;
tmp_51_reg_5417[58] <= 1'b0;
tmp_51_reg_5417[59] <= 1'b0;
tmp_51_reg_5417[60] <= 1'b0;
tmp_51_reg_5417[61] <= 1'b0;
tmp_51_reg_5417[62] <= 1'b0;
tmp_51_reg_5417[63] <= 1'b0;
end
always @ (ap_clk)
begin
ap_reg_ppstg_tmp_51_reg_5417_pp1_it2[14] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_5417_pp1_it2[15] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_5417_pp1_it2[16] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_5417_pp1_it2[17] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_5417_pp1_it2[18] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_5417_pp1_it2[19] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_5417_pp1_it2[20] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_5417_pp1_it2[21] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_5417_pp1_it2[22] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_5417_pp1_it2[23] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_5417_pp1_it2[24] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_5417_pp1_it2[25] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_5417_pp1_it2[26] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_5417_pp1_it2[27] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_5417_pp1_it2[28] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_5417_pp1_it2[29] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_5417_pp1_it2[30] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_5417_pp1_it2[31] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_5417_pp1_it2[32] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_5417_pp1_it2[33] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_5417_pp1_it2[34] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_5417_pp1_it2[35] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_5417_pp1_it2[36] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_5417_pp1_it2[37] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_5417_pp1_it2[38] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_5417_pp1_it2[39] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_5417_pp1_it2[40] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_5417_pp1_it2[41] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_5417_pp1_it2[42] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_5417_pp1_it2[43] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_5417_pp1_it2[44] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_5417_pp1_it2[45] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_5417_pp1_it2[46] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_5417_pp1_it2[47] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_5417_pp1_it2[48] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_5417_pp1_it2[49] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_5417_pp1_it2[50] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_5417_pp1_it2[51] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_5417_pp1_it2[52] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_5417_pp1_it2[53] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_5417_pp1_it2[54] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_5417_pp1_it2[55] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_5417_pp1_it2[56] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_5417_pp1_it2[57] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_5417_pp1_it2[58] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_5417_pp1_it2[59] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_5417_pp1_it2[60] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_5417_pp1_it2[61] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_5417_pp1_it2[62] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_5417_pp1_it2[63] <= 1'b0;
end
always @ (ap_clk)
begin
tmp_59_reg_5436[13] <= 1'b0;
tmp_59_reg_5436[14] <= 1'b0;
tmp_59_reg_5436[15] <= 1'b0;
tmp_59_reg_5436[16] <= 1'b0;
tmp_59_reg_5436[17] <= 1'b0;
tmp_59_reg_5436[18] <= 1'b0;
tmp_59_reg_5436[19] <= 1'b0;
tmp_59_reg_5436[20] <= 1'b0;
tmp_59_reg_5436[21] <= 1'b0;
tmp_59_reg_5436[22] <= 1'b0;
tmp_59_reg_5436[23] <= 1'b0;
tmp_59_reg_5436[24] <= 1'b0;
tmp_59_reg_5436[25] <= 1'b0;
tmp_59_reg_5436[26] <= 1'b0;
tmp_59_reg_5436[27] <= 1'b0;
tmp_59_reg_5436[28] <= 1'b0;
tmp_59_reg_5436[29] <= 1'b0;
tmp_59_reg_5436[30] <= 1'b0;
tmp_59_reg_5436[31] <= 1'b0;
tmp_59_reg_5436[32] <= 1'b0;
tmp_59_reg_5436[33] <= 1'b0;
tmp_59_reg_5436[34] <= 1'b0;
tmp_59_reg_5436[35] <= 1'b0;
tmp_59_reg_5436[36] <= 1'b0;
tmp_59_reg_5436[37] <= 1'b0;
tmp_59_reg_5436[38] <= 1'b0;
tmp_59_reg_5436[39] <= 1'b0;
tmp_59_reg_5436[40] <= 1'b0;
tmp_59_reg_5436[41] <= 1'b0;
tmp_59_reg_5436[42] <= 1'b0;
tmp_59_reg_5436[43] <= 1'b0;
tmp_59_reg_5436[44] <= 1'b0;
tmp_59_reg_5436[45] <= 1'b0;
tmp_59_reg_5436[46] <= 1'b0;
tmp_59_reg_5436[47] <= 1'b0;
tmp_59_reg_5436[48] <= 1'b0;
tmp_59_reg_5436[49] <= 1'b0;
tmp_59_reg_5436[50] <= 1'b0;
tmp_59_reg_5436[51] <= 1'b0;
tmp_59_reg_5436[52] <= 1'b0;
tmp_59_reg_5436[53] <= 1'b0;
tmp_59_reg_5436[54] <= 1'b0;
tmp_59_reg_5436[55] <= 1'b0;
tmp_59_reg_5436[56] <= 1'b0;
tmp_59_reg_5436[57] <= 1'b0;
tmp_59_reg_5436[58] <= 1'b0;
tmp_59_reg_5436[59] <= 1'b0;
tmp_59_reg_5436[60] <= 1'b0;
tmp_59_reg_5436[61] <= 1'b0;
tmp_59_reg_5436[62] <= 1'b0;
tmp_59_reg_5436[63] <= 1'b0;
end
always @ (ap_clk)
begin
ap_reg_ppstg_tmp_59_reg_5436_pp2_it1[13] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it1[14] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it1[15] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it1[16] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it1[17] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it1[18] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it1[19] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it1[20] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it1[21] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it1[22] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it1[23] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it1[24] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it1[25] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it1[26] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it1[27] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it1[28] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it1[29] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it1[30] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it1[31] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it1[32] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it1[33] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it1[34] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it1[35] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it1[36] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it1[37] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it1[38] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it1[39] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it1[40] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it1[41] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it1[42] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it1[43] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it1[44] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it1[45] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it1[46] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it1[47] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it1[48] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it1[49] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it1[50] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it1[51] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it1[52] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it1[53] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it1[54] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it1[55] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it1[56] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it1[57] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it1[58] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it1[59] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it1[60] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it1[61] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it1[62] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it1[63] <= 1'b0;
end
always @ (ap_clk)
begin
ap_reg_ppstg_tmp_59_reg_5436_pp2_it2[13] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it2[14] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it2[15] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it2[16] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it2[17] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it2[18] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it2[19] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it2[20] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it2[21] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it2[22] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it2[23] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it2[24] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it2[25] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it2[26] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it2[27] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it2[28] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it2[29] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it2[30] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it2[31] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it2[32] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it2[33] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it2[34] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it2[35] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it2[36] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it2[37] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it2[38] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it2[39] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it2[40] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it2[41] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it2[42] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it2[43] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it2[44] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it2[45] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it2[46] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it2[47] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it2[48] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it2[49] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it2[50] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it2[51] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it2[52] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it2[53] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it2[54] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it2[55] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it2[56] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it2[57] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it2[58] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it2[59] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it2[60] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it2[61] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it2[62] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it2[63] <= 1'b0;
end
always @ (ap_clk)
begin
ap_reg_ppstg_tmp_59_reg_5436_pp2_it3[13] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it3[14] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it3[15] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it3[16] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it3[17] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it3[18] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it3[19] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it3[20] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it3[21] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it3[22] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it3[23] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it3[24] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it3[25] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it3[26] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it3[27] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it3[28] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it3[29] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it3[30] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it3[31] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it3[32] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it3[33] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it3[34] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it3[35] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it3[36] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it3[37] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it3[38] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it3[39] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it3[40] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it3[41] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it3[42] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it3[43] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it3[44] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it3[45] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it3[46] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it3[47] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it3[48] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it3[49] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it3[50] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it3[51] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it3[52] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it3[53] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it3[54] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it3[55] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it3[56] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it3[57] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it3[58] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it3[59] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it3[60] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it3[61] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it3[62] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it3[63] <= 1'b0;
end
always @ (ap_clk)
begin
ap_reg_ppstg_tmp_59_reg_5436_pp2_it4[13] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it4[14] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it4[15] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it4[16] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it4[17] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it4[18] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it4[19] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it4[20] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it4[21] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it4[22] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it4[23] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it4[24] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it4[25] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it4[26] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it4[27] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it4[28] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it4[29] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it4[30] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it4[31] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it4[32] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it4[33] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it4[34] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it4[35] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it4[36] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it4[37] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it4[38] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it4[39] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it4[40] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it4[41] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it4[42] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it4[43] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it4[44] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it4[45] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it4[46] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it4[47] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it4[48] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it4[49] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it4[50] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it4[51] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it4[52] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it4[53] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it4[54] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it4[55] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it4[56] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it4[57] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it4[58] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it4[59] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it4[60] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it4[61] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it4[62] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it4[63] <= 1'b0;
end
always @ (ap_clk)
begin
ap_reg_ppstg_tmp_59_reg_5436_pp2_it5[13] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it5[14] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it5[15] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it5[16] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it5[17] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it5[18] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it5[19] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it5[20] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it5[21] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it5[22] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it5[23] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it5[24] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it5[25] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it5[26] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it5[27] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it5[28] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it5[29] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it5[30] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it5[31] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it5[32] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it5[33] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it5[34] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it5[35] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it5[36] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it5[37] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it5[38] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it5[39] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it5[40] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it5[41] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it5[42] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it5[43] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it5[44] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it5[45] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it5[46] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it5[47] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it5[48] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it5[49] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it5[50] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it5[51] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it5[52] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it5[53] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it5[54] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it5[55] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it5[56] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it5[57] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it5[58] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it5[59] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it5[60] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it5[61] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it5[62] <= 1'b0;
ap_reg_ppstg_tmp_59_reg_5436_pp2_it5[63] <= 1'b0;
end
always @ (ap_clk)
begin
tmp_46_trn_cast_reg_5508[6] <= 1'b0;
tmp_46_trn_cast_reg_5508[7] <= 1'b0;
tmp_46_trn_cast_reg_5508[8] <= 1'b0;
tmp_46_trn_cast_reg_5508[9] <= 1'b0;
tmp_46_trn_cast_reg_5508[10] <= 1'b0;
tmp_46_trn_cast_reg_5508[11] <= 1'b0;
tmp_46_trn_cast_reg_5508[12] <= 1'b0;
end
always @ (ap_clk)
begin
a_addr112_reg_5548[1] <= 1'b1;
end
always @ (ap_clk)
begin
a_addr116_reg_5608[2] <= 1'b1;
end
always @ (ap_clk)
begin
tmp_122_reg_5687[7] <= 1'b0;
tmp_122_reg_5687[8] <= 1'b0;
tmp_122_reg_5687[9] <= 1'b0;
tmp_122_reg_5687[10] <= 1'b0;
tmp_122_reg_5687[11] <= 1'b0;
tmp_122_reg_5687[12] <= 1'b0;
tmp_122_reg_5687[13] <= 1'b0;
tmp_122_reg_5687[14] <= 1'b0;
tmp_122_reg_5687[15] <= 1'b0;
tmp_122_reg_5687[16] <= 1'b0;
tmp_122_reg_5687[17] <= 1'b0;
tmp_122_reg_5687[18] <= 1'b0;
tmp_122_reg_5687[19] <= 1'b0;
tmp_122_reg_5687[20] <= 1'b0;
tmp_122_reg_5687[21] <= 1'b0;
tmp_122_reg_5687[22] <= 1'b0;
tmp_122_reg_5687[23] <= 1'b0;
tmp_122_reg_5687[24] <= 1'b0;
tmp_122_reg_5687[25] <= 1'b0;
tmp_122_reg_5687[26] <= 1'b0;
tmp_122_reg_5687[27] <= 1'b0;
tmp_122_reg_5687[28] <= 1'b0;
tmp_122_reg_5687[29] <= 1'b0;
tmp_122_reg_5687[30] <= 1'b0;
tmp_122_reg_5687[31] <= 1'b0;
tmp_122_reg_5687[32] <= 1'b0;
tmp_122_reg_5687[33] <= 1'b0;
tmp_122_reg_5687[34] <= 1'b0;
tmp_122_reg_5687[35] <= 1'b0;
tmp_122_reg_5687[36] <= 1'b0;
tmp_122_reg_5687[37] <= 1'b0;
tmp_122_reg_5687[38] <= 1'b0;
tmp_122_reg_5687[39] <= 1'b0;
tmp_122_reg_5687[40] <= 1'b0;
tmp_122_reg_5687[41] <= 1'b0;
tmp_122_reg_5687[42] <= 1'b0;
tmp_122_reg_5687[43] <= 1'b0;
tmp_122_reg_5687[44] <= 1'b0;
tmp_122_reg_5687[45] <= 1'b0;
tmp_122_reg_5687[46] <= 1'b0;
tmp_122_reg_5687[47] <= 1'b0;
tmp_122_reg_5687[48] <= 1'b0;
tmp_122_reg_5687[49] <= 1'b0;
tmp_122_reg_5687[50] <= 1'b0;
tmp_122_reg_5687[51] <= 1'b0;
tmp_122_reg_5687[52] <= 1'b0;
tmp_122_reg_5687[53] <= 1'b0;
tmp_122_reg_5687[54] <= 1'b0;
tmp_122_reg_5687[55] <= 1'b0;
tmp_122_reg_5687[56] <= 1'b0;
tmp_122_reg_5687[57] <= 1'b0;
tmp_122_reg_5687[58] <= 1'b0;
tmp_122_reg_5687[59] <= 1'b0;
tmp_122_reg_5687[60] <= 1'b0;
tmp_122_reg_5687[61] <= 1'b0;
tmp_122_reg_5687[62] <= 1'b0;
tmp_122_reg_5687[63] <= 1'b0;
end
always @ (ap_clk)
begin
ap_reg_ppstg_tmp_122_reg_5687_pp4_it1[7] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it1[8] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it1[9] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it1[10] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it1[11] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it1[12] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it1[13] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it1[14] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it1[15] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it1[16] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it1[17] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it1[18] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it1[19] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it1[20] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it1[21] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it1[22] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it1[23] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it1[24] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it1[25] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it1[26] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it1[27] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it1[28] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it1[29] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it1[30] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it1[31] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it1[32] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it1[33] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it1[34] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it1[35] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it1[36] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it1[37] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it1[38] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it1[39] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it1[40] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it1[41] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it1[42] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it1[43] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it1[44] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it1[45] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it1[46] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it1[47] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it1[48] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it1[49] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it1[50] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it1[51] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it1[52] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it1[53] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it1[54] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it1[55] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it1[56] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it1[57] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it1[58] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it1[59] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it1[60] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it1[61] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it1[62] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it1[63] <= 1'b0;
end
always @ (ap_clk)
begin
ap_reg_ppstg_tmp_122_reg_5687_pp4_it2[7] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it2[8] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it2[9] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it2[10] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it2[11] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it2[12] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it2[13] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it2[14] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it2[15] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it2[16] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it2[17] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it2[18] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it2[19] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it2[20] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it2[21] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it2[22] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it2[23] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it2[24] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it2[25] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it2[26] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it2[27] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it2[28] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it2[29] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it2[30] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it2[31] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it2[32] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it2[33] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it2[34] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it2[35] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it2[36] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it2[37] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it2[38] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it2[39] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it2[40] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it2[41] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it2[42] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it2[43] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it2[44] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it2[45] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it2[46] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it2[47] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it2[48] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it2[49] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it2[50] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it2[51] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it2[52] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it2[53] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it2[54] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it2[55] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it2[56] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it2[57] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it2[58] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it2[59] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it2[60] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it2[61] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it2[62] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it2[63] <= 1'b0;
end
always @ (ap_clk)
begin
ap_reg_ppstg_tmp_122_reg_5687_pp4_it3[7] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it3[8] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it3[9] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it3[10] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it3[11] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it3[12] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it3[13] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it3[14] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it3[15] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it3[16] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it3[17] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it3[18] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it3[19] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it3[20] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it3[21] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it3[22] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it3[23] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it3[24] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it3[25] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it3[26] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it3[27] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it3[28] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it3[29] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it3[30] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it3[31] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it3[32] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it3[33] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it3[34] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it3[35] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it3[36] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it3[37] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it3[38] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it3[39] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it3[40] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it3[41] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it3[42] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it3[43] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it3[44] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it3[45] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it3[46] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it3[47] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it3[48] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it3[49] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it3[50] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it3[51] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it3[52] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it3[53] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it3[54] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it3[55] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it3[56] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it3[57] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it3[58] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it3[59] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it3[60] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it3[61] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it3[62] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it3[63] <= 1'b0;
end
always @ (ap_clk)
begin
ap_reg_ppstg_tmp_122_reg_5687_pp4_it4[7] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it4[8] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it4[9] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it4[10] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it4[11] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it4[12] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it4[13] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it4[14] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it4[15] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it4[16] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it4[17] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it4[18] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it4[19] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it4[20] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it4[21] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it4[22] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it4[23] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it4[24] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it4[25] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it4[26] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it4[27] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it4[28] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it4[29] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it4[30] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it4[31] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it4[32] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it4[33] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it4[34] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it4[35] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it4[36] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it4[37] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it4[38] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it4[39] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it4[40] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it4[41] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it4[42] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it4[43] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it4[44] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it4[45] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it4[46] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it4[47] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it4[48] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it4[49] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it4[50] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it4[51] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it4[52] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it4[53] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it4[54] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it4[55] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it4[56] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it4[57] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it4[58] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it4[59] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it4[60] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it4[61] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it4[62] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it4[63] <= 1'b0;
end
always @ (ap_clk)
begin
ap_reg_ppstg_tmp_122_reg_5687_pp4_it5[7] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it5[8] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it5[9] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it5[10] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it5[11] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it5[12] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it5[13] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it5[14] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it5[15] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it5[16] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it5[17] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it5[18] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it5[19] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it5[20] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it5[21] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it5[22] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it5[23] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it5[24] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it5[25] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it5[26] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it5[27] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it5[28] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it5[29] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it5[30] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it5[31] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it5[32] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it5[33] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it5[34] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it5[35] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it5[36] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it5[37] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it5[38] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it5[39] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it5[40] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it5[41] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it5[42] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it5[43] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it5[44] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it5[45] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it5[46] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it5[47] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it5[48] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it5[49] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it5[50] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it5[51] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it5[52] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it5[53] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it5[54] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it5[55] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it5[56] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it5[57] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it5[58] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it5[59] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it5[60] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it5[61] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it5[62] <= 1'b0;
ap_reg_ppstg_tmp_122_reg_5687_pp4_it5[63] <= 1'b0;
end
always @ (ap_clk)
begin
a_addr37_cast_reg_5729[0] <= 1'b0;
a_addr37_cast_reg_5729[1] <= 1'b0;
a_addr37_cast_reg_5729[2] <= 1'b0;
a_addr37_cast_reg_5729[3] <= 1'b0;
a_addr37_cast_reg_5729[4] <= 1'b0;
a_addr37_cast_reg_5729[5] <= 1'b0;
a_addr37_cast_reg_5729[13] <= 1'b0;
end
always @ (ap_clk)
begin
ap_reg_ppstg_a_addr37_cast_reg_5729_pp5_it1[0] <= 1'b0;
ap_reg_ppstg_a_addr37_cast_reg_5729_pp5_it1[1] <= 1'b0;
ap_reg_ppstg_a_addr37_cast_reg_5729_pp5_it1[2] <= 1'b0;
ap_reg_ppstg_a_addr37_cast_reg_5729_pp5_it1[3] <= 1'b0;
ap_reg_ppstg_a_addr37_cast_reg_5729_pp5_it1[4] <= 1'b0;
ap_reg_ppstg_a_addr37_cast_reg_5729_pp5_it1[5] <= 1'b0;
ap_reg_ppstg_a_addr37_cast_reg_5729_pp5_it1[13] <= 1'b0;
end
always @ (ap_clk)
begin
tmp_125_reg_5740[14] <= 1'b0;
tmp_125_reg_5740[15] <= 1'b0;
tmp_125_reg_5740[16] <= 1'b0;
tmp_125_reg_5740[17] <= 1'b0;
tmp_125_reg_5740[18] <= 1'b0;
tmp_125_reg_5740[19] <= 1'b0;
tmp_125_reg_5740[20] <= 1'b0;
tmp_125_reg_5740[21] <= 1'b0;
tmp_125_reg_5740[22] <= 1'b0;
tmp_125_reg_5740[23] <= 1'b0;
tmp_125_reg_5740[24] <= 1'b0;
tmp_125_reg_5740[25] <= 1'b0;
tmp_125_reg_5740[26] <= 1'b0;
tmp_125_reg_5740[27] <= 1'b0;
tmp_125_reg_5740[28] <= 1'b0;
tmp_125_reg_5740[29] <= 1'b0;
tmp_125_reg_5740[30] <= 1'b0;
tmp_125_reg_5740[31] <= 1'b0;
tmp_125_reg_5740[32] <= 1'b0;
tmp_125_reg_5740[33] <= 1'b0;
tmp_125_reg_5740[34] <= 1'b0;
tmp_125_reg_5740[35] <= 1'b0;
tmp_125_reg_5740[36] <= 1'b0;
tmp_125_reg_5740[37] <= 1'b0;
tmp_125_reg_5740[38] <= 1'b0;
tmp_125_reg_5740[39] <= 1'b0;
tmp_125_reg_5740[40] <= 1'b0;
tmp_125_reg_5740[41] <= 1'b0;
tmp_125_reg_5740[42] <= 1'b0;
tmp_125_reg_5740[43] <= 1'b0;
tmp_125_reg_5740[44] <= 1'b0;
tmp_125_reg_5740[45] <= 1'b0;
tmp_125_reg_5740[46] <= 1'b0;
tmp_125_reg_5740[47] <= 1'b0;
tmp_125_reg_5740[48] <= 1'b0;
tmp_125_reg_5740[49] <= 1'b0;
tmp_125_reg_5740[50] <= 1'b0;
tmp_125_reg_5740[51] <= 1'b0;
tmp_125_reg_5740[52] <= 1'b0;
tmp_125_reg_5740[53] <= 1'b0;
tmp_125_reg_5740[54] <= 1'b0;
tmp_125_reg_5740[55] <= 1'b0;
tmp_125_reg_5740[56] <= 1'b0;
tmp_125_reg_5740[57] <= 1'b0;
tmp_125_reg_5740[58] <= 1'b0;
tmp_125_reg_5740[59] <= 1'b0;
tmp_125_reg_5740[60] <= 1'b0;
tmp_125_reg_5740[61] <= 1'b0;
tmp_125_reg_5740[62] <= 1'b0;
tmp_125_reg_5740[63] <= 1'b0;
end
always @ (ap_clk)
begin
ap_reg_ppstg_tmp_125_reg_5740_pp5_it1[14] <= 1'b0;
ap_reg_ppstg_tmp_125_reg_5740_pp5_it1[15] <= 1'b0;
ap_reg_ppstg_tmp_125_reg_5740_pp5_it1[16] <= 1'b0;
ap_reg_ppstg_tmp_125_reg_5740_pp5_it1[17] <= 1'b0;
ap_reg_ppstg_tmp_125_reg_5740_pp5_it1[18] <= 1'b0;
ap_reg_ppstg_tmp_125_reg_5740_pp5_it1[19] <= 1'b0;
ap_reg_ppstg_tmp_125_reg_5740_pp5_it1[20] <= 1'b0;
ap_reg_ppstg_tmp_125_reg_5740_pp5_it1[21] <= 1'b0;
ap_reg_ppstg_tmp_125_reg_5740_pp5_it1[22] <= 1'b0;
ap_reg_ppstg_tmp_125_reg_5740_pp5_it1[23] <= 1'b0;
ap_reg_ppstg_tmp_125_reg_5740_pp5_it1[24] <= 1'b0;
ap_reg_ppstg_tmp_125_reg_5740_pp5_it1[25] <= 1'b0;
ap_reg_ppstg_tmp_125_reg_5740_pp5_it1[26] <= 1'b0;
ap_reg_ppstg_tmp_125_reg_5740_pp5_it1[27] <= 1'b0;
ap_reg_ppstg_tmp_125_reg_5740_pp5_it1[28] <= 1'b0;
ap_reg_ppstg_tmp_125_reg_5740_pp5_it1[29] <= 1'b0;
ap_reg_ppstg_tmp_125_reg_5740_pp5_it1[30] <= 1'b0;
ap_reg_ppstg_tmp_125_reg_5740_pp5_it1[31] <= 1'b0;
ap_reg_ppstg_tmp_125_reg_5740_pp5_it1[32] <= 1'b0;
ap_reg_ppstg_tmp_125_reg_5740_pp5_it1[33] <= 1'b0;
ap_reg_ppstg_tmp_125_reg_5740_pp5_it1[34] <= 1'b0;
ap_reg_ppstg_tmp_125_reg_5740_pp5_it1[35] <= 1'b0;
ap_reg_ppstg_tmp_125_reg_5740_pp5_it1[36] <= 1'b0;
ap_reg_ppstg_tmp_125_reg_5740_pp5_it1[37] <= 1'b0;
ap_reg_ppstg_tmp_125_reg_5740_pp5_it1[38] <= 1'b0;
ap_reg_ppstg_tmp_125_reg_5740_pp5_it1[39] <= 1'b0;
ap_reg_ppstg_tmp_125_reg_5740_pp5_it1[40] <= 1'b0;
ap_reg_ppstg_tmp_125_reg_5740_pp5_it1[41] <= 1'b0;
ap_reg_ppstg_tmp_125_reg_5740_pp5_it1[42] <= 1'b0;
ap_reg_ppstg_tmp_125_reg_5740_pp5_it1[43] <= 1'b0;
ap_reg_ppstg_tmp_125_reg_5740_pp5_it1[44] <= 1'b0;
ap_reg_ppstg_tmp_125_reg_5740_pp5_it1[45] <= 1'b0;
ap_reg_ppstg_tmp_125_reg_5740_pp5_it1[46] <= 1'b0;
ap_reg_ppstg_tmp_125_reg_5740_pp5_it1[47] <= 1'b0;
ap_reg_ppstg_tmp_125_reg_5740_pp5_it1[48] <= 1'b0;
ap_reg_ppstg_tmp_125_reg_5740_pp5_it1[49] <= 1'b0;
ap_reg_ppstg_tmp_125_reg_5740_pp5_it1[50] <= 1'b0;
ap_reg_ppstg_tmp_125_reg_5740_pp5_it1[51] <= 1'b0;
ap_reg_ppstg_tmp_125_reg_5740_pp5_it1[52] <= 1'b0;
ap_reg_ppstg_tmp_125_reg_5740_pp5_it1[53] <= 1'b0;
ap_reg_ppstg_tmp_125_reg_5740_pp5_it1[54] <= 1'b0;
ap_reg_ppstg_tmp_125_reg_5740_pp5_it1[55] <= 1'b0;
ap_reg_ppstg_tmp_125_reg_5740_pp5_it1[56] <= 1'b0;
ap_reg_ppstg_tmp_125_reg_5740_pp5_it1[57] <= 1'b0;
ap_reg_ppstg_tmp_125_reg_5740_pp5_it1[58] <= 1'b0;
ap_reg_ppstg_tmp_125_reg_5740_pp5_it1[59] <= 1'b0;
ap_reg_ppstg_tmp_125_reg_5740_pp5_it1[60] <= 1'b0;
ap_reg_ppstg_tmp_125_reg_5740_pp5_it1[61] <= 1'b0;
ap_reg_ppstg_tmp_125_reg_5740_pp5_it1[62] <= 1'b0;
ap_reg_ppstg_tmp_125_reg_5740_pp5_it1[63] <= 1'b0;
end
always @ (ap_clk)
begin
b_addr26_cast_reg_5755[0] <= 1'b0;
b_addr26_cast_reg_5755[1] <= 1'b0;
b_addr26_cast_reg_5755[2] <= 1'b0;
b_addr26_cast_reg_5755[3] <= 1'b0;
b_addr26_cast_reg_5755[4] <= 1'b0;
b_addr26_cast_reg_5755[5] <= 1'b0;
b_addr26_cast_reg_5755[12] <= 1'b0;
end
always @ (ap_clk)
begin
tmp_130_reg_5770[0] <= 1'b1;
tmp_130_reg_5770[14] <= 1'b0;
tmp_130_reg_5770[15] <= 1'b0;
tmp_130_reg_5770[16] <= 1'b0;
tmp_130_reg_5770[17] <= 1'b0;
tmp_130_reg_5770[18] <= 1'b0;
tmp_130_reg_5770[19] <= 1'b0;
tmp_130_reg_5770[20] <= 1'b0;
tmp_130_reg_5770[21] <= 1'b0;
tmp_130_reg_5770[22] <= 1'b0;
tmp_130_reg_5770[23] <= 1'b0;
tmp_130_reg_5770[24] <= 1'b0;
tmp_130_reg_5770[25] <= 1'b0;
tmp_130_reg_5770[26] <= 1'b0;
tmp_130_reg_5770[27] <= 1'b0;
tmp_130_reg_5770[28] <= 1'b0;
tmp_130_reg_5770[29] <= 1'b0;
tmp_130_reg_5770[30] <= 1'b0;
tmp_130_reg_5770[31] <= 1'b0;
tmp_130_reg_5770[32] <= 1'b0;
tmp_130_reg_5770[33] <= 1'b0;
tmp_130_reg_5770[34] <= 1'b0;
tmp_130_reg_5770[35] <= 1'b0;
tmp_130_reg_5770[36] <= 1'b0;
tmp_130_reg_5770[37] <= 1'b0;
tmp_130_reg_5770[38] <= 1'b0;
tmp_130_reg_5770[39] <= 1'b0;
tmp_130_reg_5770[40] <= 1'b0;
tmp_130_reg_5770[41] <= 1'b0;
tmp_130_reg_5770[42] <= 1'b0;
tmp_130_reg_5770[43] <= 1'b0;
tmp_130_reg_5770[44] <= 1'b0;
tmp_130_reg_5770[45] <= 1'b0;
tmp_130_reg_5770[46] <= 1'b0;
tmp_130_reg_5770[47] <= 1'b0;
tmp_130_reg_5770[48] <= 1'b0;
tmp_130_reg_5770[49] <= 1'b0;
tmp_130_reg_5770[50] <= 1'b0;
tmp_130_reg_5770[51] <= 1'b0;
tmp_130_reg_5770[52] <= 1'b0;
tmp_130_reg_5770[53] <= 1'b0;
tmp_130_reg_5770[54] <= 1'b0;
tmp_130_reg_5770[55] <= 1'b0;
tmp_130_reg_5770[56] <= 1'b0;
tmp_130_reg_5770[57] <= 1'b0;
tmp_130_reg_5770[58] <= 1'b0;
tmp_130_reg_5770[59] <= 1'b0;
tmp_130_reg_5770[60] <= 1'b0;
tmp_130_reg_5770[61] <= 1'b0;
tmp_130_reg_5770[62] <= 1'b0;
tmp_130_reg_5770[63] <= 1'b0;
end
always @ (ap_clk)
begin
ap_reg_ppstg_tmp_130_reg_5770_pp5_it1[0] <= 1'b1;
ap_reg_ppstg_tmp_130_reg_5770_pp5_it1[14] <= 1'b0;
ap_reg_ppstg_tmp_130_reg_5770_pp5_it1[15] <= 1'b0;
ap_reg_ppstg_tmp_130_reg_5770_pp5_it1[16] <= 1'b0;
ap_reg_ppstg_tmp_130_reg_5770_pp5_it1[17] <= 1'b0;
ap_reg_ppstg_tmp_130_reg_5770_pp5_it1[18] <= 1'b0;
ap_reg_ppstg_tmp_130_reg_5770_pp5_it1[19] <= 1'b0;
ap_reg_ppstg_tmp_130_reg_5770_pp5_it1[20] <= 1'b0;
ap_reg_ppstg_tmp_130_reg_5770_pp5_it1[21] <= 1'b0;
ap_reg_ppstg_tmp_130_reg_5770_pp5_it1[22] <= 1'b0;
ap_reg_ppstg_tmp_130_reg_5770_pp5_it1[23] <= 1'b0;
ap_reg_ppstg_tmp_130_reg_5770_pp5_it1[24] <= 1'b0;
ap_reg_ppstg_tmp_130_reg_5770_pp5_it1[25] <= 1'b0;
ap_reg_ppstg_tmp_130_reg_5770_pp5_it1[26] <= 1'b0;
ap_reg_ppstg_tmp_130_reg_5770_pp5_it1[27] <= 1'b0;
ap_reg_ppstg_tmp_130_reg_5770_pp5_it1[28] <= 1'b0;
ap_reg_ppstg_tmp_130_reg_5770_pp5_it1[29] <= 1'b0;
ap_reg_ppstg_tmp_130_reg_5770_pp5_it1[30] <= 1'b0;
ap_reg_ppstg_tmp_130_reg_5770_pp5_it1[31] <= 1'b0;
ap_reg_ppstg_tmp_130_reg_5770_pp5_it1[32] <= 1'b0;
ap_reg_ppstg_tmp_130_reg_5770_pp5_it1[33] <= 1'b0;
ap_reg_ppstg_tmp_130_reg_5770_pp5_it1[34] <= 1'b0;
ap_reg_ppstg_tmp_130_reg_5770_pp5_it1[35] <= 1'b0;
ap_reg_ppstg_tmp_130_reg_5770_pp5_it1[36] <= 1'b0;
ap_reg_ppstg_tmp_130_reg_5770_pp5_it1[37] <= 1'b0;
ap_reg_ppstg_tmp_130_reg_5770_pp5_it1[38] <= 1'b0;
ap_reg_ppstg_tmp_130_reg_5770_pp5_it1[39] <= 1'b0;
ap_reg_ppstg_tmp_130_reg_5770_pp5_it1[40] <= 1'b0;
ap_reg_ppstg_tmp_130_reg_5770_pp5_it1[41] <= 1'b0;
ap_reg_ppstg_tmp_130_reg_5770_pp5_it1[42] <= 1'b0;
ap_reg_ppstg_tmp_130_reg_5770_pp5_it1[43] <= 1'b0;
ap_reg_ppstg_tmp_130_reg_5770_pp5_it1[44] <= 1'b0;
ap_reg_ppstg_tmp_130_reg_5770_pp5_it1[45] <= 1'b0;
ap_reg_ppstg_tmp_130_reg_5770_pp5_it1[46] <= 1'b0;
ap_reg_ppstg_tmp_130_reg_5770_pp5_it1[47] <= 1'b0;
ap_reg_ppstg_tmp_130_reg_5770_pp5_it1[48] <= 1'b0;
ap_reg_ppstg_tmp_130_reg_5770_pp5_it1[49] <= 1'b0;
ap_reg_ppstg_tmp_130_reg_5770_pp5_it1[50] <= 1'b0;
ap_reg_ppstg_tmp_130_reg_5770_pp5_it1[51] <= 1'b0;
ap_reg_ppstg_tmp_130_reg_5770_pp5_it1[52] <= 1'b0;
ap_reg_ppstg_tmp_130_reg_5770_pp5_it1[53] <= 1'b0;
ap_reg_ppstg_tmp_130_reg_5770_pp5_it1[54] <= 1'b0;
ap_reg_ppstg_tmp_130_reg_5770_pp5_it1[55] <= 1'b0;
ap_reg_ppstg_tmp_130_reg_5770_pp5_it1[56] <= 1'b0;
ap_reg_ppstg_tmp_130_reg_5770_pp5_it1[57] <= 1'b0;
ap_reg_ppstg_tmp_130_reg_5770_pp5_it1[58] <= 1'b0;
ap_reg_ppstg_tmp_130_reg_5770_pp5_it1[59] <= 1'b0;
ap_reg_ppstg_tmp_130_reg_5770_pp5_it1[60] <= 1'b0;
ap_reg_ppstg_tmp_130_reg_5770_pp5_it1[61] <= 1'b0;
ap_reg_ppstg_tmp_130_reg_5770_pp5_it1[62] <= 1'b0;
ap_reg_ppstg_tmp_130_reg_5770_pp5_it1[63] <= 1'b0;
end
always @ (ap_clk)
begin
tmp_97_reg_5785[1] <= 1'b1;
end
always @ (ap_clk)
begin
tmp_138_reg_5790[14] <= 1'b0;
tmp_138_reg_5790[15] <= 1'b0;
tmp_138_reg_5790[16] <= 1'b0;
tmp_138_reg_5790[17] <= 1'b0;
tmp_138_reg_5790[18] <= 1'b0;
tmp_138_reg_5790[19] <= 1'b0;
tmp_138_reg_5790[20] <= 1'b0;
tmp_138_reg_5790[21] <= 1'b0;
tmp_138_reg_5790[22] <= 1'b0;
tmp_138_reg_5790[23] <= 1'b0;
tmp_138_reg_5790[24] <= 1'b0;
tmp_138_reg_5790[25] <= 1'b0;
tmp_138_reg_5790[26] <= 1'b0;
tmp_138_reg_5790[27] <= 1'b0;
tmp_138_reg_5790[28] <= 1'b0;
tmp_138_reg_5790[29] <= 1'b0;
tmp_138_reg_5790[30] <= 1'b0;
tmp_138_reg_5790[31] <= 1'b0;
tmp_138_reg_5790[32] <= 1'b0;
tmp_138_reg_5790[33] <= 1'b0;
tmp_138_reg_5790[34] <= 1'b0;
tmp_138_reg_5790[35] <= 1'b0;
tmp_138_reg_5790[36] <= 1'b0;
tmp_138_reg_5790[37] <= 1'b0;
tmp_138_reg_5790[38] <= 1'b0;
tmp_138_reg_5790[39] <= 1'b0;
tmp_138_reg_5790[40] <= 1'b0;
tmp_138_reg_5790[41] <= 1'b0;
tmp_138_reg_5790[42] <= 1'b0;
tmp_138_reg_5790[43] <= 1'b0;
tmp_138_reg_5790[44] <= 1'b0;
tmp_138_reg_5790[45] <= 1'b0;
tmp_138_reg_5790[46] <= 1'b0;
tmp_138_reg_5790[47] <= 1'b0;
tmp_138_reg_5790[48] <= 1'b0;
tmp_138_reg_5790[49] <= 1'b0;
tmp_138_reg_5790[50] <= 1'b0;
tmp_138_reg_5790[51] <= 1'b0;
tmp_138_reg_5790[52] <= 1'b0;
tmp_138_reg_5790[53] <= 1'b0;
tmp_138_reg_5790[54] <= 1'b0;
tmp_138_reg_5790[55] <= 1'b0;
tmp_138_reg_5790[56] <= 1'b0;
tmp_138_reg_5790[57] <= 1'b0;
tmp_138_reg_5790[58] <= 1'b0;
tmp_138_reg_5790[59] <= 1'b0;
tmp_138_reg_5790[60] <= 1'b0;
tmp_138_reg_5790[61] <= 1'b0;
tmp_138_reg_5790[62] <= 1'b0;
tmp_138_reg_5790[63] <= 1'b0;
end
always @ (ap_clk)
begin
ap_reg_ppstg_tmp_138_reg_5790_pp5_it1[14] <= 1'b0;
ap_reg_ppstg_tmp_138_reg_5790_pp5_it1[15] <= 1'b0;
ap_reg_ppstg_tmp_138_reg_5790_pp5_it1[16] <= 1'b0;
ap_reg_ppstg_tmp_138_reg_5790_pp5_it1[17] <= 1'b0;
ap_reg_ppstg_tmp_138_reg_5790_pp5_it1[18] <= 1'b0;
ap_reg_ppstg_tmp_138_reg_5790_pp5_it1[19] <= 1'b0;
ap_reg_ppstg_tmp_138_reg_5790_pp5_it1[20] <= 1'b0;
ap_reg_ppstg_tmp_138_reg_5790_pp5_it1[21] <= 1'b0;
ap_reg_ppstg_tmp_138_reg_5790_pp5_it1[22] <= 1'b0;
ap_reg_ppstg_tmp_138_reg_5790_pp5_it1[23] <= 1'b0;
ap_reg_ppstg_tmp_138_reg_5790_pp5_it1[24] <= 1'b0;
ap_reg_ppstg_tmp_138_reg_5790_pp5_it1[25] <= 1'b0;
ap_reg_ppstg_tmp_138_reg_5790_pp5_it1[26] <= 1'b0;
ap_reg_ppstg_tmp_138_reg_5790_pp5_it1[27] <= 1'b0;
ap_reg_ppstg_tmp_138_reg_5790_pp5_it1[28] <= 1'b0;
ap_reg_ppstg_tmp_138_reg_5790_pp5_it1[29] <= 1'b0;
ap_reg_ppstg_tmp_138_reg_5790_pp5_it1[30] <= 1'b0;
ap_reg_ppstg_tmp_138_reg_5790_pp5_it1[31] <= 1'b0;
ap_reg_ppstg_tmp_138_reg_5790_pp5_it1[32] <= 1'b0;
ap_reg_ppstg_tmp_138_reg_5790_pp5_it1[33] <= 1'b0;
ap_reg_ppstg_tmp_138_reg_5790_pp5_it1[34] <= 1'b0;
ap_reg_ppstg_tmp_138_reg_5790_pp5_it1[35] <= 1'b0;
ap_reg_ppstg_tmp_138_reg_5790_pp5_it1[36] <= 1'b0;
ap_reg_ppstg_tmp_138_reg_5790_pp5_it1[37] <= 1'b0;
ap_reg_ppstg_tmp_138_reg_5790_pp5_it1[38] <= 1'b0;
ap_reg_ppstg_tmp_138_reg_5790_pp5_it1[39] <= 1'b0;
ap_reg_ppstg_tmp_138_reg_5790_pp5_it1[40] <= 1'b0;
ap_reg_ppstg_tmp_138_reg_5790_pp5_it1[41] <= 1'b0;
ap_reg_ppstg_tmp_138_reg_5790_pp5_it1[42] <= 1'b0;
ap_reg_ppstg_tmp_138_reg_5790_pp5_it1[43] <= 1'b0;
ap_reg_ppstg_tmp_138_reg_5790_pp5_it1[44] <= 1'b0;
ap_reg_ppstg_tmp_138_reg_5790_pp5_it1[45] <= 1'b0;
ap_reg_ppstg_tmp_138_reg_5790_pp5_it1[46] <= 1'b0;
ap_reg_ppstg_tmp_138_reg_5790_pp5_it1[47] <= 1'b0;
ap_reg_ppstg_tmp_138_reg_5790_pp5_it1[48] <= 1'b0;
ap_reg_ppstg_tmp_138_reg_5790_pp5_it1[49] <= 1'b0;
ap_reg_ppstg_tmp_138_reg_5790_pp5_it1[50] <= 1'b0;
ap_reg_ppstg_tmp_138_reg_5790_pp5_it1[51] <= 1'b0;
ap_reg_ppstg_tmp_138_reg_5790_pp5_it1[52] <= 1'b0;
ap_reg_ppstg_tmp_138_reg_5790_pp5_it1[53] <= 1'b0;
ap_reg_ppstg_tmp_138_reg_5790_pp5_it1[54] <= 1'b0;
ap_reg_ppstg_tmp_138_reg_5790_pp5_it1[55] <= 1'b0;
ap_reg_ppstg_tmp_138_reg_5790_pp5_it1[56] <= 1'b0;
ap_reg_ppstg_tmp_138_reg_5790_pp5_it1[57] <= 1'b0;
ap_reg_ppstg_tmp_138_reg_5790_pp5_it1[58] <= 1'b0;
ap_reg_ppstg_tmp_138_reg_5790_pp5_it1[59] <= 1'b0;
ap_reg_ppstg_tmp_138_reg_5790_pp5_it1[60] <= 1'b0;
ap_reg_ppstg_tmp_138_reg_5790_pp5_it1[61] <= 1'b0;
ap_reg_ppstg_tmp_138_reg_5790_pp5_it1[62] <= 1'b0;
ap_reg_ppstg_tmp_138_reg_5790_pp5_it1[63] <= 1'b0;
end
always @ (ap_clk)
begin
tmp_146_reg_5805[0] <= 1'b1;
tmp_146_reg_5805[1] <= 1'b1;
tmp_146_reg_5805[14] <= 1'b0;
tmp_146_reg_5805[15] <= 1'b0;
tmp_146_reg_5805[16] <= 1'b0;
tmp_146_reg_5805[17] <= 1'b0;
tmp_146_reg_5805[18] <= 1'b0;
tmp_146_reg_5805[19] <= 1'b0;
tmp_146_reg_5805[20] <= 1'b0;
tmp_146_reg_5805[21] <= 1'b0;
tmp_146_reg_5805[22] <= 1'b0;
tmp_146_reg_5805[23] <= 1'b0;
tmp_146_reg_5805[24] <= 1'b0;
tmp_146_reg_5805[25] <= 1'b0;
tmp_146_reg_5805[26] <= 1'b0;
tmp_146_reg_5805[27] <= 1'b0;
tmp_146_reg_5805[28] <= 1'b0;
tmp_146_reg_5805[29] <= 1'b0;
tmp_146_reg_5805[30] <= 1'b0;
tmp_146_reg_5805[31] <= 1'b0;
tmp_146_reg_5805[32] <= 1'b0;
tmp_146_reg_5805[33] <= 1'b0;
tmp_146_reg_5805[34] <= 1'b0;
tmp_146_reg_5805[35] <= 1'b0;
tmp_146_reg_5805[36] <= 1'b0;
tmp_146_reg_5805[37] <= 1'b0;
tmp_146_reg_5805[38] <= 1'b0;
tmp_146_reg_5805[39] <= 1'b0;
tmp_146_reg_5805[40] <= 1'b0;
tmp_146_reg_5805[41] <= 1'b0;
tmp_146_reg_5805[42] <= 1'b0;
tmp_146_reg_5805[43] <= 1'b0;
tmp_146_reg_5805[44] <= 1'b0;
tmp_146_reg_5805[45] <= 1'b0;
tmp_146_reg_5805[46] <= 1'b0;
tmp_146_reg_5805[47] <= 1'b0;
tmp_146_reg_5805[48] <= 1'b0;
tmp_146_reg_5805[49] <= 1'b0;
tmp_146_reg_5805[50] <= 1'b0;
tmp_146_reg_5805[51] <= 1'b0;
tmp_146_reg_5805[52] <= 1'b0;
tmp_146_reg_5805[53] <= 1'b0;
tmp_146_reg_5805[54] <= 1'b0;
tmp_146_reg_5805[55] <= 1'b0;
tmp_146_reg_5805[56] <= 1'b0;
tmp_146_reg_5805[57] <= 1'b0;
tmp_146_reg_5805[58] <= 1'b0;
tmp_146_reg_5805[59] <= 1'b0;
tmp_146_reg_5805[60] <= 1'b0;
tmp_146_reg_5805[61] <= 1'b0;
tmp_146_reg_5805[62] <= 1'b0;
tmp_146_reg_5805[63] <= 1'b0;
end
always @ (ap_clk)
begin
ap_reg_ppstg_tmp_146_reg_5805_pp5_it1[0] <= 1'b1;
ap_reg_ppstg_tmp_146_reg_5805_pp5_it1[1] <= 1'b1;
ap_reg_ppstg_tmp_146_reg_5805_pp5_it1[14] <= 1'b0;
ap_reg_ppstg_tmp_146_reg_5805_pp5_it1[15] <= 1'b0;
ap_reg_ppstg_tmp_146_reg_5805_pp5_it1[16] <= 1'b0;
ap_reg_ppstg_tmp_146_reg_5805_pp5_it1[17] <= 1'b0;
ap_reg_ppstg_tmp_146_reg_5805_pp5_it1[18] <= 1'b0;
ap_reg_ppstg_tmp_146_reg_5805_pp5_it1[19] <= 1'b0;
ap_reg_ppstg_tmp_146_reg_5805_pp5_it1[20] <= 1'b0;
ap_reg_ppstg_tmp_146_reg_5805_pp5_it1[21] <= 1'b0;
ap_reg_ppstg_tmp_146_reg_5805_pp5_it1[22] <= 1'b0;
ap_reg_ppstg_tmp_146_reg_5805_pp5_it1[23] <= 1'b0;
ap_reg_ppstg_tmp_146_reg_5805_pp5_it1[24] <= 1'b0;
ap_reg_ppstg_tmp_146_reg_5805_pp5_it1[25] <= 1'b0;
ap_reg_ppstg_tmp_146_reg_5805_pp5_it1[26] <= 1'b0;
ap_reg_ppstg_tmp_146_reg_5805_pp5_it1[27] <= 1'b0;
ap_reg_ppstg_tmp_146_reg_5805_pp5_it1[28] <= 1'b0;
ap_reg_ppstg_tmp_146_reg_5805_pp5_it1[29] <= 1'b0;
ap_reg_ppstg_tmp_146_reg_5805_pp5_it1[30] <= 1'b0;
ap_reg_ppstg_tmp_146_reg_5805_pp5_it1[31] <= 1'b0;
ap_reg_ppstg_tmp_146_reg_5805_pp5_it1[32] <= 1'b0;
ap_reg_ppstg_tmp_146_reg_5805_pp5_it1[33] <= 1'b0;
ap_reg_ppstg_tmp_146_reg_5805_pp5_it1[34] <= 1'b0;
ap_reg_ppstg_tmp_146_reg_5805_pp5_it1[35] <= 1'b0;
ap_reg_ppstg_tmp_146_reg_5805_pp5_it1[36] <= 1'b0;
ap_reg_ppstg_tmp_146_reg_5805_pp5_it1[37] <= 1'b0;
ap_reg_ppstg_tmp_146_reg_5805_pp5_it1[38] <= 1'b0;
ap_reg_ppstg_tmp_146_reg_5805_pp5_it1[39] <= 1'b0;
ap_reg_ppstg_tmp_146_reg_5805_pp5_it1[40] <= 1'b0;
ap_reg_ppstg_tmp_146_reg_5805_pp5_it1[41] <= 1'b0;
ap_reg_ppstg_tmp_146_reg_5805_pp5_it1[42] <= 1'b0;
ap_reg_ppstg_tmp_146_reg_5805_pp5_it1[43] <= 1'b0;
ap_reg_ppstg_tmp_146_reg_5805_pp5_it1[44] <= 1'b0;
ap_reg_ppstg_tmp_146_reg_5805_pp5_it1[45] <= 1'b0;
ap_reg_ppstg_tmp_146_reg_5805_pp5_it1[46] <= 1'b0;
ap_reg_ppstg_tmp_146_reg_5805_pp5_it1[47] <= 1'b0;
ap_reg_ppstg_tmp_146_reg_5805_pp5_it1[48] <= 1'b0;
ap_reg_ppstg_tmp_146_reg_5805_pp5_it1[49] <= 1'b0;
ap_reg_ppstg_tmp_146_reg_5805_pp5_it1[50] <= 1'b0;
ap_reg_ppstg_tmp_146_reg_5805_pp5_it1[51] <= 1'b0;
ap_reg_ppstg_tmp_146_reg_5805_pp5_it1[52] <= 1'b0;
ap_reg_ppstg_tmp_146_reg_5805_pp5_it1[53] <= 1'b0;
ap_reg_ppstg_tmp_146_reg_5805_pp5_it1[54] <= 1'b0;
ap_reg_ppstg_tmp_146_reg_5805_pp5_it1[55] <= 1'b0;
ap_reg_ppstg_tmp_146_reg_5805_pp5_it1[56] <= 1'b0;
ap_reg_ppstg_tmp_146_reg_5805_pp5_it1[57] <= 1'b0;
ap_reg_ppstg_tmp_146_reg_5805_pp5_it1[58] <= 1'b0;
ap_reg_ppstg_tmp_146_reg_5805_pp5_it1[59] <= 1'b0;
ap_reg_ppstg_tmp_146_reg_5805_pp5_it1[60] <= 1'b0;
ap_reg_ppstg_tmp_146_reg_5805_pp5_it1[61] <= 1'b0;
ap_reg_ppstg_tmp_146_reg_5805_pp5_it1[62] <= 1'b0;
ap_reg_ppstg_tmp_146_reg_5805_pp5_it1[63] <= 1'b0;
end
always @ (ap_clk)
begin
tmp_105_reg_5820[2] <= 1'b1;
end
always @ (ap_clk)
begin
tmp_154_reg_5825[14] <= 1'b0;
tmp_154_reg_5825[15] <= 1'b0;
tmp_154_reg_5825[16] <= 1'b0;
tmp_154_reg_5825[17] <= 1'b0;
tmp_154_reg_5825[18] <= 1'b0;
tmp_154_reg_5825[19] <= 1'b0;
tmp_154_reg_5825[20] <= 1'b0;
tmp_154_reg_5825[21] <= 1'b0;
tmp_154_reg_5825[22] <= 1'b0;
tmp_154_reg_5825[23] <= 1'b0;
tmp_154_reg_5825[24] <= 1'b0;
tmp_154_reg_5825[25] <= 1'b0;
tmp_154_reg_5825[26] <= 1'b0;
tmp_154_reg_5825[27] <= 1'b0;
tmp_154_reg_5825[28] <= 1'b0;
tmp_154_reg_5825[29] <= 1'b0;
tmp_154_reg_5825[30] <= 1'b0;
tmp_154_reg_5825[31] <= 1'b0;
tmp_154_reg_5825[32] <= 1'b0;
tmp_154_reg_5825[33] <= 1'b0;
tmp_154_reg_5825[34] <= 1'b0;
tmp_154_reg_5825[35] <= 1'b0;
tmp_154_reg_5825[36] <= 1'b0;
tmp_154_reg_5825[37] <= 1'b0;
tmp_154_reg_5825[38] <= 1'b0;
tmp_154_reg_5825[39] <= 1'b0;
tmp_154_reg_5825[40] <= 1'b0;
tmp_154_reg_5825[41] <= 1'b0;
tmp_154_reg_5825[42] <= 1'b0;
tmp_154_reg_5825[43] <= 1'b0;
tmp_154_reg_5825[44] <= 1'b0;
tmp_154_reg_5825[45] <= 1'b0;
tmp_154_reg_5825[46] <= 1'b0;
tmp_154_reg_5825[47] <= 1'b0;
tmp_154_reg_5825[48] <= 1'b0;
tmp_154_reg_5825[49] <= 1'b0;
tmp_154_reg_5825[50] <= 1'b0;
tmp_154_reg_5825[51] <= 1'b0;
tmp_154_reg_5825[52] <= 1'b0;
tmp_154_reg_5825[53] <= 1'b0;
tmp_154_reg_5825[54] <= 1'b0;
tmp_154_reg_5825[55] <= 1'b0;
tmp_154_reg_5825[56] <= 1'b0;
tmp_154_reg_5825[57] <= 1'b0;
tmp_154_reg_5825[58] <= 1'b0;
tmp_154_reg_5825[59] <= 1'b0;
tmp_154_reg_5825[60] <= 1'b0;
tmp_154_reg_5825[61] <= 1'b0;
tmp_154_reg_5825[62] <= 1'b0;
tmp_154_reg_5825[63] <= 1'b0;
end
always @ (ap_clk)
begin
ap_reg_ppstg_tmp_154_reg_5825_pp5_it1[14] <= 1'b0;
ap_reg_ppstg_tmp_154_reg_5825_pp5_it1[15] <= 1'b0;
ap_reg_ppstg_tmp_154_reg_5825_pp5_it1[16] <= 1'b0;
ap_reg_ppstg_tmp_154_reg_5825_pp5_it1[17] <= 1'b0;
ap_reg_ppstg_tmp_154_reg_5825_pp5_it1[18] <= 1'b0;
ap_reg_ppstg_tmp_154_reg_5825_pp5_it1[19] <= 1'b0;
ap_reg_ppstg_tmp_154_reg_5825_pp5_it1[20] <= 1'b0;
ap_reg_ppstg_tmp_154_reg_5825_pp5_it1[21] <= 1'b0;
ap_reg_ppstg_tmp_154_reg_5825_pp5_it1[22] <= 1'b0;
ap_reg_ppstg_tmp_154_reg_5825_pp5_it1[23] <= 1'b0;
ap_reg_ppstg_tmp_154_reg_5825_pp5_it1[24] <= 1'b0;
ap_reg_ppstg_tmp_154_reg_5825_pp5_it1[25] <= 1'b0;
ap_reg_ppstg_tmp_154_reg_5825_pp5_it1[26] <= 1'b0;
ap_reg_ppstg_tmp_154_reg_5825_pp5_it1[27] <= 1'b0;
ap_reg_ppstg_tmp_154_reg_5825_pp5_it1[28] <= 1'b0;
ap_reg_ppstg_tmp_154_reg_5825_pp5_it1[29] <= 1'b0;
ap_reg_ppstg_tmp_154_reg_5825_pp5_it1[30] <= 1'b0;
ap_reg_ppstg_tmp_154_reg_5825_pp5_it1[31] <= 1'b0;
ap_reg_ppstg_tmp_154_reg_5825_pp5_it1[32] <= 1'b0;
ap_reg_ppstg_tmp_154_reg_5825_pp5_it1[33] <= 1'b0;
ap_reg_ppstg_tmp_154_reg_5825_pp5_it1[34] <= 1'b0;
ap_reg_ppstg_tmp_154_reg_5825_pp5_it1[35] <= 1'b0;
ap_reg_ppstg_tmp_154_reg_5825_pp5_it1[36] <= 1'b0;
ap_reg_ppstg_tmp_154_reg_5825_pp5_it1[37] <= 1'b0;
ap_reg_ppstg_tmp_154_reg_5825_pp5_it1[38] <= 1'b0;
ap_reg_ppstg_tmp_154_reg_5825_pp5_it1[39] <= 1'b0;
ap_reg_ppstg_tmp_154_reg_5825_pp5_it1[40] <= 1'b0;
ap_reg_ppstg_tmp_154_reg_5825_pp5_it1[41] <= 1'b0;
ap_reg_ppstg_tmp_154_reg_5825_pp5_it1[42] <= 1'b0;
ap_reg_ppstg_tmp_154_reg_5825_pp5_it1[43] <= 1'b0;
ap_reg_ppstg_tmp_154_reg_5825_pp5_it1[44] <= 1'b0;
ap_reg_ppstg_tmp_154_reg_5825_pp5_it1[45] <= 1'b0;
ap_reg_ppstg_tmp_154_reg_5825_pp5_it1[46] <= 1'b0;
ap_reg_ppstg_tmp_154_reg_5825_pp5_it1[47] <= 1'b0;
ap_reg_ppstg_tmp_154_reg_5825_pp5_it1[48] <= 1'b0;
ap_reg_ppstg_tmp_154_reg_5825_pp5_it1[49] <= 1'b0;
ap_reg_ppstg_tmp_154_reg_5825_pp5_it1[50] <= 1'b0;
ap_reg_ppstg_tmp_154_reg_5825_pp5_it1[51] <= 1'b0;
ap_reg_ppstg_tmp_154_reg_5825_pp5_it1[52] <= 1'b0;
ap_reg_ppstg_tmp_154_reg_5825_pp5_it1[53] <= 1'b0;
ap_reg_ppstg_tmp_154_reg_5825_pp5_it1[54] <= 1'b0;
ap_reg_ppstg_tmp_154_reg_5825_pp5_it1[55] <= 1'b0;
ap_reg_ppstg_tmp_154_reg_5825_pp5_it1[56] <= 1'b0;
ap_reg_ppstg_tmp_154_reg_5825_pp5_it1[57] <= 1'b0;
ap_reg_ppstg_tmp_154_reg_5825_pp5_it1[58] <= 1'b0;
ap_reg_ppstg_tmp_154_reg_5825_pp5_it1[59] <= 1'b0;
ap_reg_ppstg_tmp_154_reg_5825_pp5_it1[60] <= 1'b0;
ap_reg_ppstg_tmp_154_reg_5825_pp5_it1[61] <= 1'b0;
ap_reg_ppstg_tmp_154_reg_5825_pp5_it1[62] <= 1'b0;
ap_reg_ppstg_tmp_154_reg_5825_pp5_it1[63] <= 1'b0;
end
always @ (ap_clk)
begin
tmp_160_reg_5840[0] <= 1'b1;
tmp_160_reg_5840[14] <= 1'b0;
tmp_160_reg_5840[15] <= 1'b0;
tmp_160_reg_5840[16] <= 1'b0;
tmp_160_reg_5840[17] <= 1'b0;
tmp_160_reg_5840[18] <= 1'b0;
tmp_160_reg_5840[19] <= 1'b0;
tmp_160_reg_5840[20] <= 1'b0;
tmp_160_reg_5840[21] <= 1'b0;
tmp_160_reg_5840[22] <= 1'b0;
tmp_160_reg_5840[23] <= 1'b0;
tmp_160_reg_5840[24] <= 1'b0;
tmp_160_reg_5840[25] <= 1'b0;
tmp_160_reg_5840[26] <= 1'b0;
tmp_160_reg_5840[27] <= 1'b0;
tmp_160_reg_5840[28] <= 1'b0;
tmp_160_reg_5840[29] <= 1'b0;
tmp_160_reg_5840[30] <= 1'b0;
tmp_160_reg_5840[31] <= 1'b0;
tmp_160_reg_5840[32] <= 1'b0;
tmp_160_reg_5840[33] <= 1'b0;
tmp_160_reg_5840[34] <= 1'b0;
tmp_160_reg_5840[35] <= 1'b0;
tmp_160_reg_5840[36] <= 1'b0;
tmp_160_reg_5840[37] <= 1'b0;
tmp_160_reg_5840[38] <= 1'b0;
tmp_160_reg_5840[39] <= 1'b0;
tmp_160_reg_5840[40] <= 1'b0;
tmp_160_reg_5840[41] <= 1'b0;
tmp_160_reg_5840[42] <= 1'b0;
tmp_160_reg_5840[43] <= 1'b0;
tmp_160_reg_5840[44] <= 1'b0;
tmp_160_reg_5840[45] <= 1'b0;
tmp_160_reg_5840[46] <= 1'b0;
tmp_160_reg_5840[47] <= 1'b0;
tmp_160_reg_5840[48] <= 1'b0;
tmp_160_reg_5840[49] <= 1'b0;
tmp_160_reg_5840[50] <= 1'b0;
tmp_160_reg_5840[51] <= 1'b0;
tmp_160_reg_5840[52] <= 1'b0;
tmp_160_reg_5840[53] <= 1'b0;
tmp_160_reg_5840[54] <= 1'b0;
tmp_160_reg_5840[55] <= 1'b0;
tmp_160_reg_5840[56] <= 1'b0;
tmp_160_reg_5840[57] <= 1'b0;
tmp_160_reg_5840[58] <= 1'b0;
tmp_160_reg_5840[59] <= 1'b0;
tmp_160_reg_5840[60] <= 1'b0;
tmp_160_reg_5840[61] <= 1'b0;
tmp_160_reg_5840[62] <= 1'b0;
tmp_160_reg_5840[63] <= 1'b0;
end
always @ (ap_clk)
begin
ap_reg_ppstg_tmp_160_reg_5840_pp5_it1[0] <= 1'b1;
ap_reg_ppstg_tmp_160_reg_5840_pp5_it1[14] <= 1'b0;
ap_reg_ppstg_tmp_160_reg_5840_pp5_it1[15] <= 1'b0;
ap_reg_ppstg_tmp_160_reg_5840_pp5_it1[16] <= 1'b0;
ap_reg_ppstg_tmp_160_reg_5840_pp5_it1[17] <= 1'b0;
ap_reg_ppstg_tmp_160_reg_5840_pp5_it1[18] <= 1'b0;
ap_reg_ppstg_tmp_160_reg_5840_pp5_it1[19] <= 1'b0;
ap_reg_ppstg_tmp_160_reg_5840_pp5_it1[20] <= 1'b0;
ap_reg_ppstg_tmp_160_reg_5840_pp5_it1[21] <= 1'b0;
ap_reg_ppstg_tmp_160_reg_5840_pp5_it1[22] <= 1'b0;
ap_reg_ppstg_tmp_160_reg_5840_pp5_it1[23] <= 1'b0;
ap_reg_ppstg_tmp_160_reg_5840_pp5_it1[24] <= 1'b0;
ap_reg_ppstg_tmp_160_reg_5840_pp5_it1[25] <= 1'b0;
ap_reg_ppstg_tmp_160_reg_5840_pp5_it1[26] <= 1'b0;
ap_reg_ppstg_tmp_160_reg_5840_pp5_it1[27] <= 1'b0;
ap_reg_ppstg_tmp_160_reg_5840_pp5_it1[28] <= 1'b0;
ap_reg_ppstg_tmp_160_reg_5840_pp5_it1[29] <= 1'b0;
ap_reg_ppstg_tmp_160_reg_5840_pp5_it1[30] <= 1'b0;
ap_reg_ppstg_tmp_160_reg_5840_pp5_it1[31] <= 1'b0;
ap_reg_ppstg_tmp_160_reg_5840_pp5_it1[32] <= 1'b0;
ap_reg_ppstg_tmp_160_reg_5840_pp5_it1[33] <= 1'b0;
ap_reg_ppstg_tmp_160_reg_5840_pp5_it1[34] <= 1'b0;
ap_reg_ppstg_tmp_160_reg_5840_pp5_it1[35] <= 1'b0;
ap_reg_ppstg_tmp_160_reg_5840_pp5_it1[36] <= 1'b0;
ap_reg_ppstg_tmp_160_reg_5840_pp5_it1[37] <= 1'b0;
ap_reg_ppstg_tmp_160_reg_5840_pp5_it1[38] <= 1'b0;
ap_reg_ppstg_tmp_160_reg_5840_pp5_it1[39] <= 1'b0;
ap_reg_ppstg_tmp_160_reg_5840_pp5_it1[40] <= 1'b0;
ap_reg_ppstg_tmp_160_reg_5840_pp5_it1[41] <= 1'b0;
ap_reg_ppstg_tmp_160_reg_5840_pp5_it1[42] <= 1'b0;
ap_reg_ppstg_tmp_160_reg_5840_pp5_it1[43] <= 1'b0;
ap_reg_ppstg_tmp_160_reg_5840_pp5_it1[44] <= 1'b0;
ap_reg_ppstg_tmp_160_reg_5840_pp5_it1[45] <= 1'b0;
ap_reg_ppstg_tmp_160_reg_5840_pp5_it1[46] <= 1'b0;
ap_reg_ppstg_tmp_160_reg_5840_pp5_it1[47] <= 1'b0;
ap_reg_ppstg_tmp_160_reg_5840_pp5_it1[48] <= 1'b0;
ap_reg_ppstg_tmp_160_reg_5840_pp5_it1[49] <= 1'b0;
ap_reg_ppstg_tmp_160_reg_5840_pp5_it1[50] <= 1'b0;
ap_reg_ppstg_tmp_160_reg_5840_pp5_it1[51] <= 1'b0;
ap_reg_ppstg_tmp_160_reg_5840_pp5_it1[52] <= 1'b0;
ap_reg_ppstg_tmp_160_reg_5840_pp5_it1[53] <= 1'b0;
ap_reg_ppstg_tmp_160_reg_5840_pp5_it1[54] <= 1'b0;
ap_reg_ppstg_tmp_160_reg_5840_pp5_it1[55] <= 1'b0;
ap_reg_ppstg_tmp_160_reg_5840_pp5_it1[56] <= 1'b0;
ap_reg_ppstg_tmp_160_reg_5840_pp5_it1[57] <= 1'b0;
ap_reg_ppstg_tmp_160_reg_5840_pp5_it1[58] <= 1'b0;
ap_reg_ppstg_tmp_160_reg_5840_pp5_it1[59] <= 1'b0;
ap_reg_ppstg_tmp_160_reg_5840_pp5_it1[60] <= 1'b0;
ap_reg_ppstg_tmp_160_reg_5840_pp5_it1[61] <= 1'b0;
ap_reg_ppstg_tmp_160_reg_5840_pp5_it1[62] <= 1'b0;
ap_reg_ppstg_tmp_160_reg_5840_pp5_it1[63] <= 1'b0;
end
always @ (ap_clk)
begin
ap_reg_ppstg_tmp_160_reg_5840_pp5_it2[0] <= 1'b1;
ap_reg_ppstg_tmp_160_reg_5840_pp5_it2[14] <= 1'b0;
ap_reg_ppstg_tmp_160_reg_5840_pp5_it2[15] <= 1'b0;
ap_reg_ppstg_tmp_160_reg_5840_pp5_it2[16] <= 1'b0;
ap_reg_ppstg_tmp_160_reg_5840_pp5_it2[17] <= 1'b0;
ap_reg_ppstg_tmp_160_reg_5840_pp5_it2[18] <= 1'b0;
ap_reg_ppstg_tmp_160_reg_5840_pp5_it2[19] <= 1'b0;
ap_reg_ppstg_tmp_160_reg_5840_pp5_it2[20] <= 1'b0;
ap_reg_ppstg_tmp_160_reg_5840_pp5_it2[21] <= 1'b0;
ap_reg_ppstg_tmp_160_reg_5840_pp5_it2[22] <= 1'b0;
ap_reg_ppstg_tmp_160_reg_5840_pp5_it2[23] <= 1'b0;
ap_reg_ppstg_tmp_160_reg_5840_pp5_it2[24] <= 1'b0;
ap_reg_ppstg_tmp_160_reg_5840_pp5_it2[25] <= 1'b0;
ap_reg_ppstg_tmp_160_reg_5840_pp5_it2[26] <= 1'b0;
ap_reg_ppstg_tmp_160_reg_5840_pp5_it2[27] <= 1'b0;
ap_reg_ppstg_tmp_160_reg_5840_pp5_it2[28] <= 1'b0;
ap_reg_ppstg_tmp_160_reg_5840_pp5_it2[29] <= 1'b0;
ap_reg_ppstg_tmp_160_reg_5840_pp5_it2[30] <= 1'b0;
ap_reg_ppstg_tmp_160_reg_5840_pp5_it2[31] <= 1'b0;
ap_reg_ppstg_tmp_160_reg_5840_pp5_it2[32] <= 1'b0;
ap_reg_ppstg_tmp_160_reg_5840_pp5_it2[33] <= 1'b0;
ap_reg_ppstg_tmp_160_reg_5840_pp5_it2[34] <= 1'b0;
ap_reg_ppstg_tmp_160_reg_5840_pp5_it2[35] <= 1'b0;
ap_reg_ppstg_tmp_160_reg_5840_pp5_it2[36] <= 1'b0;
ap_reg_ppstg_tmp_160_reg_5840_pp5_it2[37] <= 1'b0;
ap_reg_ppstg_tmp_160_reg_5840_pp5_it2[38] <= 1'b0;
ap_reg_ppstg_tmp_160_reg_5840_pp5_it2[39] <= 1'b0;
ap_reg_ppstg_tmp_160_reg_5840_pp5_it2[40] <= 1'b0;
ap_reg_ppstg_tmp_160_reg_5840_pp5_it2[41] <= 1'b0;
ap_reg_ppstg_tmp_160_reg_5840_pp5_it2[42] <= 1'b0;
ap_reg_ppstg_tmp_160_reg_5840_pp5_it2[43] <= 1'b0;
ap_reg_ppstg_tmp_160_reg_5840_pp5_it2[44] <= 1'b0;
ap_reg_ppstg_tmp_160_reg_5840_pp5_it2[45] <= 1'b0;
ap_reg_ppstg_tmp_160_reg_5840_pp5_it2[46] <= 1'b0;
ap_reg_ppstg_tmp_160_reg_5840_pp5_it2[47] <= 1'b0;
ap_reg_ppstg_tmp_160_reg_5840_pp5_it2[48] <= 1'b0;
ap_reg_ppstg_tmp_160_reg_5840_pp5_it2[49] <= 1'b0;
ap_reg_ppstg_tmp_160_reg_5840_pp5_it2[50] <= 1'b0;
ap_reg_ppstg_tmp_160_reg_5840_pp5_it2[51] <= 1'b0;
ap_reg_ppstg_tmp_160_reg_5840_pp5_it2[52] <= 1'b0;
ap_reg_ppstg_tmp_160_reg_5840_pp5_it2[53] <= 1'b0;
ap_reg_ppstg_tmp_160_reg_5840_pp5_it2[54] <= 1'b0;
ap_reg_ppstg_tmp_160_reg_5840_pp5_it2[55] <= 1'b0;
ap_reg_ppstg_tmp_160_reg_5840_pp5_it2[56] <= 1'b0;
ap_reg_ppstg_tmp_160_reg_5840_pp5_it2[57] <= 1'b0;
ap_reg_ppstg_tmp_160_reg_5840_pp5_it2[58] <= 1'b0;
ap_reg_ppstg_tmp_160_reg_5840_pp5_it2[59] <= 1'b0;
ap_reg_ppstg_tmp_160_reg_5840_pp5_it2[60] <= 1'b0;
ap_reg_ppstg_tmp_160_reg_5840_pp5_it2[61] <= 1'b0;
ap_reg_ppstg_tmp_160_reg_5840_pp5_it2[62] <= 1'b0;
ap_reg_ppstg_tmp_160_reg_5840_pp5_it2[63] <= 1'b0;
end
always @ (ap_clk)
begin
tmp_113_reg_5855[1] <= 1'b1;
tmp_113_reg_5855[2] <= 1'b1;
end
always @ (ap_clk)
begin
tmp_117_reg_5865[0] <= 1'b1;
tmp_117_reg_5865[1] <= 1'b1;
tmp_117_reg_5865[2] <= 1'b1;
end
always @ (ap_clk)
begin
tmp_164_reg_5880[14] <= 1'b0;
tmp_164_reg_5880[15] <= 1'b0;
tmp_164_reg_5880[16] <= 1'b0;
tmp_164_reg_5880[17] <= 1'b0;
tmp_164_reg_5880[18] <= 1'b0;
tmp_164_reg_5880[19] <= 1'b0;
tmp_164_reg_5880[20] <= 1'b0;
tmp_164_reg_5880[21] <= 1'b0;
tmp_164_reg_5880[22] <= 1'b0;
tmp_164_reg_5880[23] <= 1'b0;
tmp_164_reg_5880[24] <= 1'b0;
tmp_164_reg_5880[25] <= 1'b0;
tmp_164_reg_5880[26] <= 1'b0;
tmp_164_reg_5880[27] <= 1'b0;
tmp_164_reg_5880[28] <= 1'b0;
tmp_164_reg_5880[29] <= 1'b0;
tmp_164_reg_5880[30] <= 1'b0;
tmp_164_reg_5880[31] <= 1'b0;
tmp_164_reg_5880[32] <= 1'b0;
tmp_164_reg_5880[33] <= 1'b0;
tmp_164_reg_5880[34] <= 1'b0;
tmp_164_reg_5880[35] <= 1'b0;
tmp_164_reg_5880[36] <= 1'b0;
tmp_164_reg_5880[37] <= 1'b0;
tmp_164_reg_5880[38] <= 1'b0;
tmp_164_reg_5880[39] <= 1'b0;
tmp_164_reg_5880[40] <= 1'b0;
tmp_164_reg_5880[41] <= 1'b0;
tmp_164_reg_5880[42] <= 1'b0;
tmp_164_reg_5880[43] <= 1'b0;
tmp_164_reg_5880[44] <= 1'b0;
tmp_164_reg_5880[45] <= 1'b0;
tmp_164_reg_5880[46] <= 1'b0;
tmp_164_reg_5880[47] <= 1'b0;
tmp_164_reg_5880[48] <= 1'b0;
tmp_164_reg_5880[49] <= 1'b0;
tmp_164_reg_5880[50] <= 1'b0;
tmp_164_reg_5880[51] <= 1'b0;
tmp_164_reg_5880[52] <= 1'b0;
tmp_164_reg_5880[53] <= 1'b0;
tmp_164_reg_5880[54] <= 1'b0;
tmp_164_reg_5880[55] <= 1'b0;
tmp_164_reg_5880[56] <= 1'b0;
tmp_164_reg_5880[57] <= 1'b0;
tmp_164_reg_5880[58] <= 1'b0;
tmp_164_reg_5880[59] <= 1'b0;
tmp_164_reg_5880[60] <= 1'b0;
tmp_164_reg_5880[61] <= 1'b0;
tmp_164_reg_5880[62] <= 1'b0;
tmp_164_reg_5880[63] <= 1'b0;
end
always @ (ap_clk)
begin
ap_reg_ppstg_tmp_164_reg_5880_pp5_it2[14] <= 1'b0;
ap_reg_ppstg_tmp_164_reg_5880_pp5_it2[15] <= 1'b0;
ap_reg_ppstg_tmp_164_reg_5880_pp5_it2[16] <= 1'b0;
ap_reg_ppstg_tmp_164_reg_5880_pp5_it2[17] <= 1'b0;
ap_reg_ppstg_tmp_164_reg_5880_pp5_it2[18] <= 1'b0;
ap_reg_ppstg_tmp_164_reg_5880_pp5_it2[19] <= 1'b0;
ap_reg_ppstg_tmp_164_reg_5880_pp5_it2[20] <= 1'b0;
ap_reg_ppstg_tmp_164_reg_5880_pp5_it2[21] <= 1'b0;
ap_reg_ppstg_tmp_164_reg_5880_pp5_it2[22] <= 1'b0;
ap_reg_ppstg_tmp_164_reg_5880_pp5_it2[23] <= 1'b0;
ap_reg_ppstg_tmp_164_reg_5880_pp5_it2[24] <= 1'b0;
ap_reg_ppstg_tmp_164_reg_5880_pp5_it2[25] <= 1'b0;
ap_reg_ppstg_tmp_164_reg_5880_pp5_it2[26] <= 1'b0;
ap_reg_ppstg_tmp_164_reg_5880_pp5_it2[27] <= 1'b0;
ap_reg_ppstg_tmp_164_reg_5880_pp5_it2[28] <= 1'b0;
ap_reg_ppstg_tmp_164_reg_5880_pp5_it2[29] <= 1'b0;
ap_reg_ppstg_tmp_164_reg_5880_pp5_it2[30] <= 1'b0;
ap_reg_ppstg_tmp_164_reg_5880_pp5_it2[31] <= 1'b0;
ap_reg_ppstg_tmp_164_reg_5880_pp5_it2[32] <= 1'b0;
ap_reg_ppstg_tmp_164_reg_5880_pp5_it2[33] <= 1'b0;
ap_reg_ppstg_tmp_164_reg_5880_pp5_it2[34] <= 1'b0;
ap_reg_ppstg_tmp_164_reg_5880_pp5_it2[35] <= 1'b0;
ap_reg_ppstg_tmp_164_reg_5880_pp5_it2[36] <= 1'b0;
ap_reg_ppstg_tmp_164_reg_5880_pp5_it2[37] <= 1'b0;
ap_reg_ppstg_tmp_164_reg_5880_pp5_it2[38] <= 1'b0;
ap_reg_ppstg_tmp_164_reg_5880_pp5_it2[39] <= 1'b0;
ap_reg_ppstg_tmp_164_reg_5880_pp5_it2[40] <= 1'b0;
ap_reg_ppstg_tmp_164_reg_5880_pp5_it2[41] <= 1'b0;
ap_reg_ppstg_tmp_164_reg_5880_pp5_it2[42] <= 1'b0;
ap_reg_ppstg_tmp_164_reg_5880_pp5_it2[43] <= 1'b0;
ap_reg_ppstg_tmp_164_reg_5880_pp5_it2[44] <= 1'b0;
ap_reg_ppstg_tmp_164_reg_5880_pp5_it2[45] <= 1'b0;
ap_reg_ppstg_tmp_164_reg_5880_pp5_it2[46] <= 1'b0;
ap_reg_ppstg_tmp_164_reg_5880_pp5_it2[47] <= 1'b0;
ap_reg_ppstg_tmp_164_reg_5880_pp5_it2[48] <= 1'b0;
ap_reg_ppstg_tmp_164_reg_5880_pp5_it2[49] <= 1'b0;
ap_reg_ppstg_tmp_164_reg_5880_pp5_it2[50] <= 1'b0;
ap_reg_ppstg_tmp_164_reg_5880_pp5_it2[51] <= 1'b0;
ap_reg_ppstg_tmp_164_reg_5880_pp5_it2[52] <= 1'b0;
ap_reg_ppstg_tmp_164_reg_5880_pp5_it2[53] <= 1'b0;
ap_reg_ppstg_tmp_164_reg_5880_pp5_it2[54] <= 1'b0;
ap_reg_ppstg_tmp_164_reg_5880_pp5_it2[55] <= 1'b0;
ap_reg_ppstg_tmp_164_reg_5880_pp5_it2[56] <= 1'b0;
ap_reg_ppstg_tmp_164_reg_5880_pp5_it2[57] <= 1'b0;
ap_reg_ppstg_tmp_164_reg_5880_pp5_it2[58] <= 1'b0;
ap_reg_ppstg_tmp_164_reg_5880_pp5_it2[59] <= 1'b0;
ap_reg_ppstg_tmp_164_reg_5880_pp5_it2[60] <= 1'b0;
ap_reg_ppstg_tmp_164_reg_5880_pp5_it2[61] <= 1'b0;
ap_reg_ppstg_tmp_164_reg_5880_pp5_it2[62] <= 1'b0;
ap_reg_ppstg_tmp_164_reg_5880_pp5_it2[63] <= 1'b0;
end
always @ (ap_clk)
begin
a_addr50_reg_5890[0] <= 1'b1;
a_addr50_reg_5890[1] <= 1'b1;
a_addr50_reg_5890[2] <= 1'b1;
end
always @ (ap_clk)
begin
tmp_168_reg_5895[0] <= 1'b1;
tmp_168_reg_5895[1] <= 1'b1;
tmp_168_reg_5895[2] <= 1'b1;
tmp_168_reg_5895[14] <= 1'b0;
tmp_168_reg_5895[15] <= 1'b0;
tmp_168_reg_5895[16] <= 1'b0;
tmp_168_reg_5895[17] <= 1'b0;
tmp_168_reg_5895[18] <= 1'b0;
tmp_168_reg_5895[19] <= 1'b0;
tmp_168_reg_5895[20] <= 1'b0;
tmp_168_reg_5895[21] <= 1'b0;
tmp_168_reg_5895[22] <= 1'b0;
tmp_168_reg_5895[23] <= 1'b0;
tmp_168_reg_5895[24] <= 1'b0;
tmp_168_reg_5895[25] <= 1'b0;
tmp_168_reg_5895[26] <= 1'b0;
tmp_168_reg_5895[27] <= 1'b0;
tmp_168_reg_5895[28] <= 1'b0;
tmp_168_reg_5895[29] <= 1'b0;
tmp_168_reg_5895[30] <= 1'b0;
tmp_168_reg_5895[31] <= 1'b0;
tmp_168_reg_5895[32] <= 1'b0;
tmp_168_reg_5895[33] <= 1'b0;
tmp_168_reg_5895[34] <= 1'b0;
tmp_168_reg_5895[35] <= 1'b0;
tmp_168_reg_5895[36] <= 1'b0;
tmp_168_reg_5895[37] <= 1'b0;
tmp_168_reg_5895[38] <= 1'b0;
tmp_168_reg_5895[39] <= 1'b0;
tmp_168_reg_5895[40] <= 1'b0;
tmp_168_reg_5895[41] <= 1'b0;
tmp_168_reg_5895[42] <= 1'b0;
tmp_168_reg_5895[43] <= 1'b0;
tmp_168_reg_5895[44] <= 1'b0;
tmp_168_reg_5895[45] <= 1'b0;
tmp_168_reg_5895[46] <= 1'b0;
tmp_168_reg_5895[47] <= 1'b0;
tmp_168_reg_5895[48] <= 1'b0;
tmp_168_reg_5895[49] <= 1'b0;
tmp_168_reg_5895[50] <= 1'b0;
tmp_168_reg_5895[51] <= 1'b0;
tmp_168_reg_5895[52] <= 1'b0;
tmp_168_reg_5895[53] <= 1'b0;
tmp_168_reg_5895[54] <= 1'b0;
tmp_168_reg_5895[55] <= 1'b0;
tmp_168_reg_5895[56] <= 1'b0;
tmp_168_reg_5895[57] <= 1'b0;
tmp_168_reg_5895[58] <= 1'b0;
tmp_168_reg_5895[59] <= 1'b0;
tmp_168_reg_5895[60] <= 1'b0;
tmp_168_reg_5895[61] <= 1'b0;
tmp_168_reg_5895[62] <= 1'b0;
tmp_168_reg_5895[63] <= 1'b0;
end
always @ (ap_clk)
begin
ap_reg_ppstg_tmp_168_reg_5895_pp5_it2[0] <= 1'b1;
ap_reg_ppstg_tmp_168_reg_5895_pp5_it2[1] <= 1'b1;
ap_reg_ppstg_tmp_168_reg_5895_pp5_it2[2] <= 1'b1;
ap_reg_ppstg_tmp_168_reg_5895_pp5_it2[14] <= 1'b0;
ap_reg_ppstg_tmp_168_reg_5895_pp5_it2[15] <= 1'b0;
ap_reg_ppstg_tmp_168_reg_5895_pp5_it2[16] <= 1'b0;
ap_reg_ppstg_tmp_168_reg_5895_pp5_it2[17] <= 1'b0;
ap_reg_ppstg_tmp_168_reg_5895_pp5_it2[18] <= 1'b0;
ap_reg_ppstg_tmp_168_reg_5895_pp5_it2[19] <= 1'b0;
ap_reg_ppstg_tmp_168_reg_5895_pp5_it2[20] <= 1'b0;
ap_reg_ppstg_tmp_168_reg_5895_pp5_it2[21] <= 1'b0;
ap_reg_ppstg_tmp_168_reg_5895_pp5_it2[22] <= 1'b0;
ap_reg_ppstg_tmp_168_reg_5895_pp5_it2[23] <= 1'b0;
ap_reg_ppstg_tmp_168_reg_5895_pp5_it2[24] <= 1'b0;
ap_reg_ppstg_tmp_168_reg_5895_pp5_it2[25] <= 1'b0;
ap_reg_ppstg_tmp_168_reg_5895_pp5_it2[26] <= 1'b0;
ap_reg_ppstg_tmp_168_reg_5895_pp5_it2[27] <= 1'b0;
ap_reg_ppstg_tmp_168_reg_5895_pp5_it2[28] <= 1'b0;
ap_reg_ppstg_tmp_168_reg_5895_pp5_it2[29] <= 1'b0;
ap_reg_ppstg_tmp_168_reg_5895_pp5_it2[30] <= 1'b0;
ap_reg_ppstg_tmp_168_reg_5895_pp5_it2[31] <= 1'b0;
ap_reg_ppstg_tmp_168_reg_5895_pp5_it2[32] <= 1'b0;
ap_reg_ppstg_tmp_168_reg_5895_pp5_it2[33] <= 1'b0;
ap_reg_ppstg_tmp_168_reg_5895_pp5_it2[34] <= 1'b0;
ap_reg_ppstg_tmp_168_reg_5895_pp5_it2[35] <= 1'b0;
ap_reg_ppstg_tmp_168_reg_5895_pp5_it2[36] <= 1'b0;
ap_reg_ppstg_tmp_168_reg_5895_pp5_it2[37] <= 1'b0;
ap_reg_ppstg_tmp_168_reg_5895_pp5_it2[38] <= 1'b0;
ap_reg_ppstg_tmp_168_reg_5895_pp5_it2[39] <= 1'b0;
ap_reg_ppstg_tmp_168_reg_5895_pp5_it2[40] <= 1'b0;
ap_reg_ppstg_tmp_168_reg_5895_pp5_it2[41] <= 1'b0;
ap_reg_ppstg_tmp_168_reg_5895_pp5_it2[42] <= 1'b0;
ap_reg_ppstg_tmp_168_reg_5895_pp5_it2[43] <= 1'b0;
ap_reg_ppstg_tmp_168_reg_5895_pp5_it2[44] <= 1'b0;
ap_reg_ppstg_tmp_168_reg_5895_pp5_it2[45] <= 1'b0;
ap_reg_ppstg_tmp_168_reg_5895_pp5_it2[46] <= 1'b0;
ap_reg_ppstg_tmp_168_reg_5895_pp5_it2[47] <= 1'b0;
ap_reg_ppstg_tmp_168_reg_5895_pp5_it2[48] <= 1'b0;
ap_reg_ppstg_tmp_168_reg_5895_pp5_it2[49] <= 1'b0;
ap_reg_ppstg_tmp_168_reg_5895_pp5_it2[50] <= 1'b0;
ap_reg_ppstg_tmp_168_reg_5895_pp5_it2[51] <= 1'b0;
ap_reg_ppstg_tmp_168_reg_5895_pp5_it2[52] <= 1'b0;
ap_reg_ppstg_tmp_168_reg_5895_pp5_it2[53] <= 1'b0;
ap_reg_ppstg_tmp_168_reg_5895_pp5_it2[54] <= 1'b0;
ap_reg_ppstg_tmp_168_reg_5895_pp5_it2[55] <= 1'b0;
ap_reg_ppstg_tmp_168_reg_5895_pp5_it2[56] <= 1'b0;
ap_reg_ppstg_tmp_168_reg_5895_pp5_it2[57] <= 1'b0;
ap_reg_ppstg_tmp_168_reg_5895_pp5_it2[58] <= 1'b0;
ap_reg_ppstg_tmp_168_reg_5895_pp5_it2[59] <= 1'b0;
ap_reg_ppstg_tmp_168_reg_5895_pp5_it2[60] <= 1'b0;
ap_reg_ppstg_tmp_168_reg_5895_pp5_it2[61] <= 1'b0;
ap_reg_ppstg_tmp_168_reg_5895_pp5_it2[62] <= 1'b0;
ap_reg_ppstg_tmp_168_reg_5895_pp5_it2[63] <= 1'b0;
end
always @ (ap_clk)
begin
tmp_172_reg_5914[13] <= 1'b0;
tmp_172_reg_5914[14] <= 1'b0;
tmp_172_reg_5914[15] <= 1'b0;
tmp_172_reg_5914[16] <= 1'b0;
tmp_172_reg_5914[17] <= 1'b0;
tmp_172_reg_5914[18] <= 1'b0;
tmp_172_reg_5914[19] <= 1'b0;
tmp_172_reg_5914[20] <= 1'b0;
tmp_172_reg_5914[21] <= 1'b0;
tmp_172_reg_5914[22] <= 1'b0;
tmp_172_reg_5914[23] <= 1'b0;
tmp_172_reg_5914[24] <= 1'b0;
tmp_172_reg_5914[25] <= 1'b0;
tmp_172_reg_5914[26] <= 1'b0;
tmp_172_reg_5914[27] <= 1'b0;
tmp_172_reg_5914[28] <= 1'b0;
tmp_172_reg_5914[29] <= 1'b0;
tmp_172_reg_5914[30] <= 1'b0;
tmp_172_reg_5914[31] <= 1'b0;
tmp_172_reg_5914[32] <= 1'b0;
tmp_172_reg_5914[33] <= 1'b0;
tmp_172_reg_5914[34] <= 1'b0;
tmp_172_reg_5914[35] <= 1'b0;
tmp_172_reg_5914[36] <= 1'b0;
tmp_172_reg_5914[37] <= 1'b0;
tmp_172_reg_5914[38] <= 1'b0;
tmp_172_reg_5914[39] <= 1'b0;
tmp_172_reg_5914[40] <= 1'b0;
tmp_172_reg_5914[41] <= 1'b0;
tmp_172_reg_5914[42] <= 1'b0;
tmp_172_reg_5914[43] <= 1'b0;
tmp_172_reg_5914[44] <= 1'b0;
tmp_172_reg_5914[45] <= 1'b0;
tmp_172_reg_5914[46] <= 1'b0;
tmp_172_reg_5914[47] <= 1'b0;
tmp_172_reg_5914[48] <= 1'b0;
tmp_172_reg_5914[49] <= 1'b0;
tmp_172_reg_5914[50] <= 1'b0;
tmp_172_reg_5914[51] <= 1'b0;
tmp_172_reg_5914[52] <= 1'b0;
tmp_172_reg_5914[53] <= 1'b0;
tmp_172_reg_5914[54] <= 1'b0;
tmp_172_reg_5914[55] <= 1'b0;
tmp_172_reg_5914[56] <= 1'b0;
tmp_172_reg_5914[57] <= 1'b0;
tmp_172_reg_5914[58] <= 1'b0;
tmp_172_reg_5914[59] <= 1'b0;
tmp_172_reg_5914[60] <= 1'b0;
tmp_172_reg_5914[61] <= 1'b0;
tmp_172_reg_5914[62] <= 1'b0;
tmp_172_reg_5914[63] <= 1'b0;
end
always @ (ap_clk)
begin
ap_reg_ppstg_tmp_172_reg_5914_pp6_it1[13] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it1[14] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it1[15] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it1[16] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it1[17] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it1[18] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it1[19] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it1[20] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it1[21] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it1[22] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it1[23] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it1[24] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it1[25] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it1[26] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it1[27] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it1[28] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it1[29] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it1[30] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it1[31] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it1[32] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it1[33] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it1[34] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it1[35] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it1[36] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it1[37] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it1[38] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it1[39] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it1[40] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it1[41] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it1[42] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it1[43] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it1[44] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it1[45] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it1[46] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it1[47] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it1[48] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it1[49] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it1[50] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it1[51] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it1[52] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it1[53] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it1[54] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it1[55] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it1[56] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it1[57] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it1[58] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it1[59] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it1[60] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it1[61] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it1[62] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it1[63] <= 1'b0;
end
always @ (ap_clk)
begin
ap_reg_ppstg_tmp_172_reg_5914_pp6_it2[13] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it2[14] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it2[15] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it2[16] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it2[17] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it2[18] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it2[19] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it2[20] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it2[21] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it2[22] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it2[23] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it2[24] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it2[25] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it2[26] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it2[27] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it2[28] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it2[29] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it2[30] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it2[31] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it2[32] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it2[33] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it2[34] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it2[35] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it2[36] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it2[37] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it2[38] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it2[39] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it2[40] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it2[41] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it2[42] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it2[43] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it2[44] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it2[45] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it2[46] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it2[47] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it2[48] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it2[49] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it2[50] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it2[51] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it2[52] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it2[53] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it2[54] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it2[55] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it2[56] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it2[57] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it2[58] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it2[59] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it2[60] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it2[61] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it2[62] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it2[63] <= 1'b0;
end
always @ (ap_clk)
begin
ap_reg_ppstg_tmp_172_reg_5914_pp6_it3[13] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it3[14] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it3[15] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it3[16] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it3[17] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it3[18] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it3[19] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it3[20] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it3[21] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it3[22] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it3[23] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it3[24] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it3[25] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it3[26] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it3[27] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it3[28] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it3[29] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it3[30] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it3[31] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it3[32] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it3[33] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it3[34] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it3[35] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it3[36] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it3[37] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it3[38] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it3[39] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it3[40] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it3[41] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it3[42] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it3[43] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it3[44] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it3[45] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it3[46] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it3[47] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it3[48] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it3[49] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it3[50] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it3[51] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it3[52] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it3[53] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it3[54] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it3[55] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it3[56] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it3[57] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it3[58] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it3[59] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it3[60] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it3[61] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it3[62] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it3[63] <= 1'b0;
end
always @ (ap_clk)
begin
ap_reg_ppstg_tmp_172_reg_5914_pp6_it4[13] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it4[14] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it4[15] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it4[16] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it4[17] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it4[18] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it4[19] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it4[20] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it4[21] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it4[22] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it4[23] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it4[24] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it4[25] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it4[26] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it4[27] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it4[28] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it4[29] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it4[30] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it4[31] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it4[32] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it4[33] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it4[34] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it4[35] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it4[36] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it4[37] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it4[38] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it4[39] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it4[40] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it4[41] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it4[42] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it4[43] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it4[44] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it4[45] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it4[46] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it4[47] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it4[48] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it4[49] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it4[50] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it4[51] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it4[52] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it4[53] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it4[54] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it4[55] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it4[56] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it4[57] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it4[58] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it4[59] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it4[60] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it4[61] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it4[62] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it4[63] <= 1'b0;
end
always @ (ap_clk)
begin
ap_reg_ppstg_tmp_172_reg_5914_pp6_it5[13] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it5[14] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it5[15] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it5[16] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it5[17] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it5[18] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it5[19] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it5[20] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it5[21] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it5[22] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it5[23] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it5[24] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it5[25] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it5[26] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it5[27] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it5[28] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it5[29] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it5[30] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it5[31] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it5[32] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it5[33] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it5[34] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it5[35] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it5[36] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it5[37] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it5[38] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it5[39] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it5[40] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it5[41] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it5[42] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it5[43] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it5[44] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it5[45] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it5[46] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it5[47] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it5[48] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it5[49] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it5[50] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it5[51] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it5[52] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it5[53] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it5[54] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it5[55] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it5[56] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it5[57] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it5[58] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it5[59] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it5[60] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it5[61] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it5[62] <= 1'b0;
ap_reg_ppstg_tmp_172_reg_5914_pp6_it5[63] <= 1'b0;
end
always @ (ap_clk)
begin
b_addr36_cast_reg_5956[0] <= 1'b0;
b_addr36_cast_reg_5956[1] <= 1'b0;
b_addr36_cast_reg_5956[2] <= 1'b0;
b_addr36_cast_reg_5956[3] <= 1'b0;
b_addr36_cast_reg_5956[4] <= 1'b0;
b_addr36_cast_reg_5956[5] <= 1'b0;
end
always @ (ap_clk)
begin
ap_reg_ppstg_b_addr36_cast_reg_5956_pp7_it1[0] <= 1'b0;
ap_reg_ppstg_b_addr36_cast_reg_5956_pp7_it1[1] <= 1'b0;
ap_reg_ppstg_b_addr36_cast_reg_5956_pp7_it1[2] <= 1'b0;
ap_reg_ppstg_b_addr36_cast_reg_5956_pp7_it1[3] <= 1'b0;
ap_reg_ppstg_b_addr36_cast_reg_5956_pp7_it1[4] <= 1'b0;
ap_reg_ppstg_b_addr36_cast_reg_5956_pp7_it1[5] <= 1'b0;
end
always @ (ap_clk)
begin
a_addr51_cast_reg_5982[0] <= 1'b0;
a_addr51_cast_reg_5982[1] <= 1'b0;
a_addr51_cast_reg_5982[2] <= 1'b0;
a_addr51_cast_reg_5982[3] <= 1'b0;
a_addr51_cast_reg_5982[4] <= 1'b0;
a_addr51_cast_reg_5982[5] <= 1'b0;
a_addr51_cast_reg_5982[12] <= 1'b0;
end
always @ (ap_clk)
begin
tmp_178_reg_5997[0] <= 1'b1;
end
always @ (ap_clk)
begin
ap_reg_ppstg_tmp_178_reg_5997_pp7_it1[0] <= 1'b1;
end
always @ (ap_clk)
begin
tmp_133_reg_6012[1] <= 1'b1;
end
always @ (ap_clk)
begin
tmp_186_reg_6032[0] <= 1'b1;
tmp_186_reg_6032[1] <= 1'b1;
end
always @ (ap_clk)
begin
ap_reg_ppstg_tmp_186_reg_6032_pp7_it1[0] <= 1'b1;
ap_reg_ppstg_tmp_186_reg_6032_pp7_it1[1] <= 1'b1;
end
always @ (ap_clk)
begin
tmp_141_reg_6047[2] <= 1'b1;
end
always @ (ap_clk)
begin
tmp_192_reg_6067[0] <= 1'b1;
end
always @ (ap_clk)
begin
ap_reg_ppstg_tmp_192_reg_6067_pp7_it1[0] <= 1'b1;
end
always @ (ap_clk)
begin
ap_reg_ppstg_tmp_192_reg_6067_pp7_it2[0] <= 1'b1;
end
always @ (ap_clk)
begin
tmp_149_reg_6082[1] <= 1'b1;
tmp_149_reg_6082[2] <= 1'b1;
end
always @ (ap_clk)
begin
tmp_153_reg_6092[0] <= 1'b1;
tmp_153_reg_6092[1] <= 1'b1;
tmp_153_reg_6092[2] <= 1'b1;
end
always @ (ap_clk)
begin
b_addr44_reg_6117[0] <= 1'b1;
b_addr44_reg_6117[1] <= 1'b1;
b_addr44_reg_6117[2] <= 1'b1;
end
always @ (ap_clk)
begin
tmp_197_reg_6122[0] <= 1'b1;
tmp_197_reg_6122[1] <= 1'b1;
tmp_197_reg_6122[2] <= 1'b1;
end
always @ (ap_clk)
begin
ap_reg_ppstg_tmp_197_reg_6122_pp7_it2[0] <= 1'b1;
ap_reg_ppstg_tmp_197_reg_6122_pp7_it2[1] <= 1'b1;
ap_reg_ppstg_tmp_197_reg_6122_pp7_it2[2] <= 1'b1;
end
always @ (ap_clk)
begin
a_addr63_cast_reg_6165[0] <= 1'b0;
a_addr63_cast_reg_6165[1] <= 1'b0;
a_addr63_cast_reg_6165[2] <= 1'b0;
a_addr63_cast_reg_6165[3] <= 1'b0;
a_addr63_cast_reg_6165[4] <= 1'b0;
a_addr63_cast_reg_6165[5] <= 1'b0;
a_addr63_cast_reg_6165[13] <= 1'b0;
end
always @ (ap_clk)
begin
tmp_199_reg_6176[14] <= 1'b0;
tmp_199_reg_6176[15] <= 1'b0;
tmp_199_reg_6176[16] <= 1'b0;
tmp_199_reg_6176[17] <= 1'b0;
tmp_199_reg_6176[18] <= 1'b0;
tmp_199_reg_6176[19] <= 1'b0;
tmp_199_reg_6176[20] <= 1'b0;
tmp_199_reg_6176[21] <= 1'b0;
tmp_199_reg_6176[22] <= 1'b0;
tmp_199_reg_6176[23] <= 1'b0;
tmp_199_reg_6176[24] <= 1'b0;
tmp_199_reg_6176[25] <= 1'b0;
tmp_199_reg_6176[26] <= 1'b0;
tmp_199_reg_6176[27] <= 1'b0;
tmp_199_reg_6176[28] <= 1'b0;
tmp_199_reg_6176[29] <= 1'b0;
tmp_199_reg_6176[30] <= 1'b0;
tmp_199_reg_6176[31] <= 1'b0;
tmp_199_reg_6176[32] <= 1'b0;
tmp_199_reg_6176[33] <= 1'b0;
tmp_199_reg_6176[34] <= 1'b0;
tmp_199_reg_6176[35] <= 1'b0;
tmp_199_reg_6176[36] <= 1'b0;
tmp_199_reg_6176[37] <= 1'b0;
tmp_199_reg_6176[38] <= 1'b0;
tmp_199_reg_6176[39] <= 1'b0;
tmp_199_reg_6176[40] <= 1'b0;
tmp_199_reg_6176[41] <= 1'b0;
tmp_199_reg_6176[42] <= 1'b0;
tmp_199_reg_6176[43] <= 1'b0;
tmp_199_reg_6176[44] <= 1'b0;
tmp_199_reg_6176[45] <= 1'b0;
tmp_199_reg_6176[46] <= 1'b0;
tmp_199_reg_6176[47] <= 1'b0;
tmp_199_reg_6176[48] <= 1'b0;
tmp_199_reg_6176[49] <= 1'b0;
tmp_199_reg_6176[50] <= 1'b0;
tmp_199_reg_6176[51] <= 1'b0;
tmp_199_reg_6176[52] <= 1'b0;
tmp_199_reg_6176[53] <= 1'b0;
tmp_199_reg_6176[54] <= 1'b0;
tmp_199_reg_6176[55] <= 1'b0;
tmp_199_reg_6176[56] <= 1'b0;
tmp_199_reg_6176[57] <= 1'b0;
tmp_199_reg_6176[58] <= 1'b0;
tmp_199_reg_6176[59] <= 1'b0;
tmp_199_reg_6176[60] <= 1'b0;
tmp_199_reg_6176[61] <= 1'b0;
tmp_199_reg_6176[62] <= 1'b0;
tmp_199_reg_6176[63] <= 1'b0;
end
always @ (ap_clk)
begin
tmp_176_trn_cast_reg_6191[0] <= 1'b1;
tmp_176_trn_cast_reg_6191[7] <= 1'b0;
tmp_176_trn_cast_reg_6191[8] <= 1'b0;
tmp_176_trn_cast_reg_6191[9] <= 1'b0;
tmp_176_trn_cast_reg_6191[10] <= 1'b0;
tmp_176_trn_cast_reg_6191[11] <= 1'b0;
tmp_176_trn_cast_reg_6191[12] <= 1'b0;
tmp_176_trn_cast_reg_6191[13] <= 1'b0;
end
always @ (ap_clk)
begin
tmp_200_reg_6202[0] <= 1'b1;
tmp_200_reg_6202[14] <= 1'b0;
tmp_200_reg_6202[15] <= 1'b0;
tmp_200_reg_6202[16] <= 1'b0;
tmp_200_reg_6202[17] <= 1'b0;
tmp_200_reg_6202[18] <= 1'b0;
tmp_200_reg_6202[19] <= 1'b0;
tmp_200_reg_6202[20] <= 1'b0;
tmp_200_reg_6202[21] <= 1'b0;
tmp_200_reg_6202[22] <= 1'b0;
tmp_200_reg_6202[23] <= 1'b0;
tmp_200_reg_6202[24] <= 1'b0;
tmp_200_reg_6202[25] <= 1'b0;
tmp_200_reg_6202[26] <= 1'b0;
tmp_200_reg_6202[27] <= 1'b0;
tmp_200_reg_6202[28] <= 1'b0;
tmp_200_reg_6202[29] <= 1'b0;
tmp_200_reg_6202[30] <= 1'b0;
tmp_200_reg_6202[31] <= 1'b0;
tmp_200_reg_6202[32] <= 1'b0;
tmp_200_reg_6202[33] <= 1'b0;
tmp_200_reg_6202[34] <= 1'b0;
tmp_200_reg_6202[35] <= 1'b0;
tmp_200_reg_6202[36] <= 1'b0;
tmp_200_reg_6202[37] <= 1'b0;
tmp_200_reg_6202[38] <= 1'b0;
tmp_200_reg_6202[39] <= 1'b0;
tmp_200_reg_6202[40] <= 1'b0;
tmp_200_reg_6202[41] <= 1'b0;
tmp_200_reg_6202[42] <= 1'b0;
tmp_200_reg_6202[43] <= 1'b0;
tmp_200_reg_6202[44] <= 1'b0;
tmp_200_reg_6202[45] <= 1'b0;
tmp_200_reg_6202[46] <= 1'b0;
tmp_200_reg_6202[47] <= 1'b0;
tmp_200_reg_6202[48] <= 1'b0;
tmp_200_reg_6202[49] <= 1'b0;
tmp_200_reg_6202[50] <= 1'b0;
tmp_200_reg_6202[51] <= 1'b0;
tmp_200_reg_6202[52] <= 1'b0;
tmp_200_reg_6202[53] <= 1'b0;
tmp_200_reg_6202[54] <= 1'b0;
tmp_200_reg_6202[55] <= 1'b0;
tmp_200_reg_6202[56] <= 1'b0;
tmp_200_reg_6202[57] <= 1'b0;
tmp_200_reg_6202[58] <= 1'b0;
tmp_200_reg_6202[59] <= 1'b0;
tmp_200_reg_6202[60] <= 1'b0;
tmp_200_reg_6202[61] <= 1'b0;
tmp_200_reg_6202[62] <= 1'b0;
tmp_200_reg_6202[63] <= 1'b0;
end
always @ (ap_clk)
begin
tmp_178_trn_cast_reg_6212[1] <= 1'b1;
tmp_178_trn_cast_reg_6212[7] <= 1'b0;
tmp_178_trn_cast_reg_6212[8] <= 1'b0;
tmp_178_trn_cast_reg_6212[9] <= 1'b0;
tmp_178_trn_cast_reg_6212[10] <= 1'b0;
tmp_178_trn_cast_reg_6212[11] <= 1'b0;
tmp_178_trn_cast_reg_6212[12] <= 1'b0;
tmp_178_trn_cast_reg_6212[13] <= 1'b0;
end
always @ (ap_clk)
begin
tmp_201_reg_6223[14] <= 1'b0;
tmp_201_reg_6223[15] <= 1'b0;
tmp_201_reg_6223[16] <= 1'b0;
tmp_201_reg_6223[17] <= 1'b0;
tmp_201_reg_6223[18] <= 1'b0;
tmp_201_reg_6223[19] <= 1'b0;
tmp_201_reg_6223[20] <= 1'b0;
tmp_201_reg_6223[21] <= 1'b0;
tmp_201_reg_6223[22] <= 1'b0;
tmp_201_reg_6223[23] <= 1'b0;
tmp_201_reg_6223[24] <= 1'b0;
tmp_201_reg_6223[25] <= 1'b0;
tmp_201_reg_6223[26] <= 1'b0;
tmp_201_reg_6223[27] <= 1'b0;
tmp_201_reg_6223[28] <= 1'b0;
tmp_201_reg_6223[29] <= 1'b0;
tmp_201_reg_6223[30] <= 1'b0;
tmp_201_reg_6223[31] <= 1'b0;
tmp_201_reg_6223[32] <= 1'b0;
tmp_201_reg_6223[33] <= 1'b0;
tmp_201_reg_6223[34] <= 1'b0;
tmp_201_reg_6223[35] <= 1'b0;
tmp_201_reg_6223[36] <= 1'b0;
tmp_201_reg_6223[37] <= 1'b0;
tmp_201_reg_6223[38] <= 1'b0;
tmp_201_reg_6223[39] <= 1'b0;
tmp_201_reg_6223[40] <= 1'b0;
tmp_201_reg_6223[41] <= 1'b0;
tmp_201_reg_6223[42] <= 1'b0;
tmp_201_reg_6223[43] <= 1'b0;
tmp_201_reg_6223[44] <= 1'b0;
tmp_201_reg_6223[45] <= 1'b0;
tmp_201_reg_6223[46] <= 1'b0;
tmp_201_reg_6223[47] <= 1'b0;
tmp_201_reg_6223[48] <= 1'b0;
tmp_201_reg_6223[49] <= 1'b0;
tmp_201_reg_6223[50] <= 1'b0;
tmp_201_reg_6223[51] <= 1'b0;
tmp_201_reg_6223[52] <= 1'b0;
tmp_201_reg_6223[53] <= 1'b0;
tmp_201_reg_6223[54] <= 1'b0;
tmp_201_reg_6223[55] <= 1'b0;
tmp_201_reg_6223[56] <= 1'b0;
tmp_201_reg_6223[57] <= 1'b0;
tmp_201_reg_6223[58] <= 1'b0;
tmp_201_reg_6223[59] <= 1'b0;
tmp_201_reg_6223[60] <= 1'b0;
tmp_201_reg_6223[61] <= 1'b0;
tmp_201_reg_6223[62] <= 1'b0;
tmp_201_reg_6223[63] <= 1'b0;
end
always @ (ap_clk)
begin
tmp_180_trn_cast_reg_6233[0] <= 1'b1;
tmp_180_trn_cast_reg_6233[1] <= 1'b1;
tmp_180_trn_cast_reg_6233[7] <= 1'b0;
tmp_180_trn_cast_reg_6233[8] <= 1'b0;
tmp_180_trn_cast_reg_6233[9] <= 1'b0;
tmp_180_trn_cast_reg_6233[10] <= 1'b0;
tmp_180_trn_cast_reg_6233[11] <= 1'b0;
tmp_180_trn_cast_reg_6233[12] <= 1'b0;
tmp_180_trn_cast_reg_6233[13] <= 1'b0;
end
always @ (ap_clk)
begin
tmp_202_reg_6244[0] <= 1'b1;
tmp_202_reg_6244[1] <= 1'b1;
tmp_202_reg_6244[14] <= 1'b0;
tmp_202_reg_6244[15] <= 1'b0;
tmp_202_reg_6244[16] <= 1'b0;
tmp_202_reg_6244[17] <= 1'b0;
tmp_202_reg_6244[18] <= 1'b0;
tmp_202_reg_6244[19] <= 1'b0;
tmp_202_reg_6244[20] <= 1'b0;
tmp_202_reg_6244[21] <= 1'b0;
tmp_202_reg_6244[22] <= 1'b0;
tmp_202_reg_6244[23] <= 1'b0;
tmp_202_reg_6244[24] <= 1'b0;
tmp_202_reg_6244[25] <= 1'b0;
tmp_202_reg_6244[26] <= 1'b0;
tmp_202_reg_6244[27] <= 1'b0;
tmp_202_reg_6244[28] <= 1'b0;
tmp_202_reg_6244[29] <= 1'b0;
tmp_202_reg_6244[30] <= 1'b0;
tmp_202_reg_6244[31] <= 1'b0;
tmp_202_reg_6244[32] <= 1'b0;
tmp_202_reg_6244[33] <= 1'b0;
tmp_202_reg_6244[34] <= 1'b0;
tmp_202_reg_6244[35] <= 1'b0;
tmp_202_reg_6244[36] <= 1'b0;
tmp_202_reg_6244[37] <= 1'b0;
tmp_202_reg_6244[38] <= 1'b0;
tmp_202_reg_6244[39] <= 1'b0;
tmp_202_reg_6244[40] <= 1'b0;
tmp_202_reg_6244[41] <= 1'b0;
tmp_202_reg_6244[42] <= 1'b0;
tmp_202_reg_6244[43] <= 1'b0;
tmp_202_reg_6244[44] <= 1'b0;
tmp_202_reg_6244[45] <= 1'b0;
tmp_202_reg_6244[46] <= 1'b0;
tmp_202_reg_6244[47] <= 1'b0;
tmp_202_reg_6244[48] <= 1'b0;
tmp_202_reg_6244[49] <= 1'b0;
tmp_202_reg_6244[50] <= 1'b0;
tmp_202_reg_6244[51] <= 1'b0;
tmp_202_reg_6244[52] <= 1'b0;
tmp_202_reg_6244[53] <= 1'b0;
tmp_202_reg_6244[54] <= 1'b0;
tmp_202_reg_6244[55] <= 1'b0;
tmp_202_reg_6244[56] <= 1'b0;
tmp_202_reg_6244[57] <= 1'b0;
tmp_202_reg_6244[58] <= 1'b0;
tmp_202_reg_6244[59] <= 1'b0;
tmp_202_reg_6244[60] <= 1'b0;
tmp_202_reg_6244[61] <= 1'b0;
tmp_202_reg_6244[62] <= 1'b0;
tmp_202_reg_6244[63] <= 1'b0;
end
always @ (ap_clk)
begin
tmp_182_trn_cast_reg_6254[2] <= 1'b1;
tmp_182_trn_cast_reg_6254[7] <= 1'b0;
tmp_182_trn_cast_reg_6254[8] <= 1'b0;
tmp_182_trn_cast_reg_6254[9] <= 1'b0;
tmp_182_trn_cast_reg_6254[10] <= 1'b0;
tmp_182_trn_cast_reg_6254[11] <= 1'b0;
tmp_182_trn_cast_reg_6254[12] <= 1'b0;
tmp_182_trn_cast_reg_6254[13] <= 1'b0;
end
always @ (ap_clk)
begin
tmp_203_reg_6265[14] <= 1'b0;
tmp_203_reg_6265[15] <= 1'b0;
tmp_203_reg_6265[16] <= 1'b0;
tmp_203_reg_6265[17] <= 1'b0;
tmp_203_reg_6265[18] <= 1'b0;
tmp_203_reg_6265[19] <= 1'b0;
tmp_203_reg_6265[20] <= 1'b0;
tmp_203_reg_6265[21] <= 1'b0;
tmp_203_reg_6265[22] <= 1'b0;
tmp_203_reg_6265[23] <= 1'b0;
tmp_203_reg_6265[24] <= 1'b0;
tmp_203_reg_6265[25] <= 1'b0;
tmp_203_reg_6265[26] <= 1'b0;
tmp_203_reg_6265[27] <= 1'b0;
tmp_203_reg_6265[28] <= 1'b0;
tmp_203_reg_6265[29] <= 1'b0;
tmp_203_reg_6265[30] <= 1'b0;
tmp_203_reg_6265[31] <= 1'b0;
tmp_203_reg_6265[32] <= 1'b0;
tmp_203_reg_6265[33] <= 1'b0;
tmp_203_reg_6265[34] <= 1'b0;
tmp_203_reg_6265[35] <= 1'b0;
tmp_203_reg_6265[36] <= 1'b0;
tmp_203_reg_6265[37] <= 1'b0;
tmp_203_reg_6265[38] <= 1'b0;
tmp_203_reg_6265[39] <= 1'b0;
tmp_203_reg_6265[40] <= 1'b0;
tmp_203_reg_6265[41] <= 1'b0;
tmp_203_reg_6265[42] <= 1'b0;
tmp_203_reg_6265[43] <= 1'b0;
tmp_203_reg_6265[44] <= 1'b0;
tmp_203_reg_6265[45] <= 1'b0;
tmp_203_reg_6265[46] <= 1'b0;
tmp_203_reg_6265[47] <= 1'b0;
tmp_203_reg_6265[48] <= 1'b0;
tmp_203_reg_6265[49] <= 1'b0;
tmp_203_reg_6265[50] <= 1'b0;
tmp_203_reg_6265[51] <= 1'b0;
tmp_203_reg_6265[52] <= 1'b0;
tmp_203_reg_6265[53] <= 1'b0;
tmp_203_reg_6265[54] <= 1'b0;
tmp_203_reg_6265[55] <= 1'b0;
tmp_203_reg_6265[56] <= 1'b0;
tmp_203_reg_6265[57] <= 1'b0;
tmp_203_reg_6265[58] <= 1'b0;
tmp_203_reg_6265[59] <= 1'b0;
tmp_203_reg_6265[60] <= 1'b0;
tmp_203_reg_6265[61] <= 1'b0;
tmp_203_reg_6265[62] <= 1'b0;
tmp_203_reg_6265[63] <= 1'b0;
end
always @ (ap_clk)
begin
tmp_184_trn_cast_reg_6275[0] <= 1'b1;
tmp_184_trn_cast_reg_6275[2] <= 1'b1;
tmp_184_trn_cast_reg_6275[7] <= 1'b0;
tmp_184_trn_cast_reg_6275[8] <= 1'b0;
tmp_184_trn_cast_reg_6275[9] <= 1'b0;
tmp_184_trn_cast_reg_6275[10] <= 1'b0;
tmp_184_trn_cast_reg_6275[11] <= 1'b0;
tmp_184_trn_cast_reg_6275[12] <= 1'b0;
tmp_184_trn_cast_reg_6275[13] <= 1'b0;
end
always @ (ap_clk)
begin
tmp_204_reg_6286[0] <= 1'b1;
tmp_204_reg_6286[14] <= 1'b0;
tmp_204_reg_6286[15] <= 1'b0;
tmp_204_reg_6286[16] <= 1'b0;
tmp_204_reg_6286[17] <= 1'b0;
tmp_204_reg_6286[18] <= 1'b0;
tmp_204_reg_6286[19] <= 1'b0;
tmp_204_reg_6286[20] <= 1'b0;
tmp_204_reg_6286[21] <= 1'b0;
tmp_204_reg_6286[22] <= 1'b0;
tmp_204_reg_6286[23] <= 1'b0;
tmp_204_reg_6286[24] <= 1'b0;
tmp_204_reg_6286[25] <= 1'b0;
tmp_204_reg_6286[26] <= 1'b0;
tmp_204_reg_6286[27] <= 1'b0;
tmp_204_reg_6286[28] <= 1'b0;
tmp_204_reg_6286[29] <= 1'b0;
tmp_204_reg_6286[30] <= 1'b0;
tmp_204_reg_6286[31] <= 1'b0;
tmp_204_reg_6286[32] <= 1'b0;
tmp_204_reg_6286[33] <= 1'b0;
tmp_204_reg_6286[34] <= 1'b0;
tmp_204_reg_6286[35] <= 1'b0;
tmp_204_reg_6286[36] <= 1'b0;
tmp_204_reg_6286[37] <= 1'b0;
tmp_204_reg_6286[38] <= 1'b0;
tmp_204_reg_6286[39] <= 1'b0;
tmp_204_reg_6286[40] <= 1'b0;
tmp_204_reg_6286[41] <= 1'b0;
tmp_204_reg_6286[42] <= 1'b0;
tmp_204_reg_6286[43] <= 1'b0;
tmp_204_reg_6286[44] <= 1'b0;
tmp_204_reg_6286[45] <= 1'b0;
tmp_204_reg_6286[46] <= 1'b0;
tmp_204_reg_6286[47] <= 1'b0;
tmp_204_reg_6286[48] <= 1'b0;
tmp_204_reg_6286[49] <= 1'b0;
tmp_204_reg_6286[50] <= 1'b0;
tmp_204_reg_6286[51] <= 1'b0;
tmp_204_reg_6286[52] <= 1'b0;
tmp_204_reg_6286[53] <= 1'b0;
tmp_204_reg_6286[54] <= 1'b0;
tmp_204_reg_6286[55] <= 1'b0;
tmp_204_reg_6286[56] <= 1'b0;
tmp_204_reg_6286[57] <= 1'b0;
tmp_204_reg_6286[58] <= 1'b0;
tmp_204_reg_6286[59] <= 1'b0;
tmp_204_reg_6286[60] <= 1'b0;
tmp_204_reg_6286[61] <= 1'b0;
tmp_204_reg_6286[62] <= 1'b0;
tmp_204_reg_6286[63] <= 1'b0;
end
always @ (ap_clk)
begin
tmp_186_trn_cast_reg_6296[1] <= 1'b1;
tmp_186_trn_cast_reg_6296[2] <= 1'b1;
tmp_186_trn_cast_reg_6296[7] <= 1'b0;
tmp_186_trn_cast_reg_6296[8] <= 1'b0;
tmp_186_trn_cast_reg_6296[9] <= 1'b0;
tmp_186_trn_cast_reg_6296[10] <= 1'b0;
tmp_186_trn_cast_reg_6296[11] <= 1'b0;
tmp_186_trn_cast_reg_6296[12] <= 1'b0;
tmp_186_trn_cast_reg_6296[13] <= 1'b0;
end
always @ (ap_clk)
begin
tmp_205_reg_6307[14] <= 1'b0;
tmp_205_reg_6307[15] <= 1'b0;
tmp_205_reg_6307[16] <= 1'b0;
tmp_205_reg_6307[17] <= 1'b0;
tmp_205_reg_6307[18] <= 1'b0;
tmp_205_reg_6307[19] <= 1'b0;
tmp_205_reg_6307[20] <= 1'b0;
tmp_205_reg_6307[21] <= 1'b0;
tmp_205_reg_6307[22] <= 1'b0;
tmp_205_reg_6307[23] <= 1'b0;
tmp_205_reg_6307[24] <= 1'b0;
tmp_205_reg_6307[25] <= 1'b0;
tmp_205_reg_6307[26] <= 1'b0;
tmp_205_reg_6307[27] <= 1'b0;
tmp_205_reg_6307[28] <= 1'b0;
tmp_205_reg_6307[29] <= 1'b0;
tmp_205_reg_6307[30] <= 1'b0;
tmp_205_reg_6307[31] <= 1'b0;
tmp_205_reg_6307[32] <= 1'b0;
tmp_205_reg_6307[33] <= 1'b0;
tmp_205_reg_6307[34] <= 1'b0;
tmp_205_reg_6307[35] <= 1'b0;
tmp_205_reg_6307[36] <= 1'b0;
tmp_205_reg_6307[37] <= 1'b0;
tmp_205_reg_6307[38] <= 1'b0;
tmp_205_reg_6307[39] <= 1'b0;
tmp_205_reg_6307[40] <= 1'b0;
tmp_205_reg_6307[41] <= 1'b0;
tmp_205_reg_6307[42] <= 1'b0;
tmp_205_reg_6307[43] <= 1'b0;
tmp_205_reg_6307[44] <= 1'b0;
tmp_205_reg_6307[45] <= 1'b0;
tmp_205_reg_6307[46] <= 1'b0;
tmp_205_reg_6307[47] <= 1'b0;
tmp_205_reg_6307[48] <= 1'b0;
tmp_205_reg_6307[49] <= 1'b0;
tmp_205_reg_6307[50] <= 1'b0;
tmp_205_reg_6307[51] <= 1'b0;
tmp_205_reg_6307[52] <= 1'b0;
tmp_205_reg_6307[53] <= 1'b0;
tmp_205_reg_6307[54] <= 1'b0;
tmp_205_reg_6307[55] <= 1'b0;
tmp_205_reg_6307[56] <= 1'b0;
tmp_205_reg_6307[57] <= 1'b0;
tmp_205_reg_6307[58] <= 1'b0;
tmp_205_reg_6307[59] <= 1'b0;
tmp_205_reg_6307[60] <= 1'b0;
tmp_205_reg_6307[61] <= 1'b0;
tmp_205_reg_6307[62] <= 1'b0;
tmp_205_reg_6307[63] <= 1'b0;
end
always @ (ap_clk)
begin
tmp_188_trn_cast_reg_6317[0] <= 1'b1;
tmp_188_trn_cast_reg_6317[1] <= 1'b1;
tmp_188_trn_cast_reg_6317[2] <= 1'b1;
tmp_188_trn_cast_reg_6317[7] <= 1'b0;
tmp_188_trn_cast_reg_6317[8] <= 1'b0;
tmp_188_trn_cast_reg_6317[9] <= 1'b0;
tmp_188_trn_cast_reg_6317[10] <= 1'b0;
tmp_188_trn_cast_reg_6317[11] <= 1'b0;
tmp_188_trn_cast_reg_6317[12] <= 1'b0;
tmp_188_trn_cast_reg_6317[13] <= 1'b0;
end
always @ (ap_clk)
begin
tmp_206_reg_6328[0] <= 1'b1;
tmp_206_reg_6328[1] <= 1'b1;
tmp_206_reg_6328[2] <= 1'b1;
tmp_206_reg_6328[14] <= 1'b0;
tmp_206_reg_6328[15] <= 1'b0;
tmp_206_reg_6328[16] <= 1'b0;
tmp_206_reg_6328[17] <= 1'b0;
tmp_206_reg_6328[18] <= 1'b0;
tmp_206_reg_6328[19] <= 1'b0;
tmp_206_reg_6328[20] <= 1'b0;
tmp_206_reg_6328[21] <= 1'b0;
tmp_206_reg_6328[22] <= 1'b0;
tmp_206_reg_6328[23] <= 1'b0;
tmp_206_reg_6328[24] <= 1'b0;
tmp_206_reg_6328[25] <= 1'b0;
tmp_206_reg_6328[26] <= 1'b0;
tmp_206_reg_6328[27] <= 1'b0;
tmp_206_reg_6328[28] <= 1'b0;
tmp_206_reg_6328[29] <= 1'b0;
tmp_206_reg_6328[30] <= 1'b0;
tmp_206_reg_6328[31] <= 1'b0;
tmp_206_reg_6328[32] <= 1'b0;
tmp_206_reg_6328[33] <= 1'b0;
tmp_206_reg_6328[34] <= 1'b0;
tmp_206_reg_6328[35] <= 1'b0;
tmp_206_reg_6328[36] <= 1'b0;
tmp_206_reg_6328[37] <= 1'b0;
tmp_206_reg_6328[38] <= 1'b0;
tmp_206_reg_6328[39] <= 1'b0;
tmp_206_reg_6328[40] <= 1'b0;
tmp_206_reg_6328[41] <= 1'b0;
tmp_206_reg_6328[42] <= 1'b0;
tmp_206_reg_6328[43] <= 1'b0;
tmp_206_reg_6328[44] <= 1'b0;
tmp_206_reg_6328[45] <= 1'b0;
tmp_206_reg_6328[46] <= 1'b0;
tmp_206_reg_6328[47] <= 1'b0;
tmp_206_reg_6328[48] <= 1'b0;
tmp_206_reg_6328[49] <= 1'b0;
tmp_206_reg_6328[50] <= 1'b0;
tmp_206_reg_6328[51] <= 1'b0;
tmp_206_reg_6328[52] <= 1'b0;
tmp_206_reg_6328[53] <= 1'b0;
tmp_206_reg_6328[54] <= 1'b0;
tmp_206_reg_6328[55] <= 1'b0;
tmp_206_reg_6328[56] <= 1'b0;
tmp_206_reg_6328[57] <= 1'b0;
tmp_206_reg_6328[58] <= 1'b0;
tmp_206_reg_6328[59] <= 1'b0;
tmp_206_reg_6328[60] <= 1'b0;
tmp_206_reg_6328[61] <= 1'b0;
tmp_206_reg_6328[62] <= 1'b0;
tmp_206_reg_6328[63] <= 1'b0;
end
always @ (ap_clk)
begin
a_addr77_cast_reg_6338[0] <= 1'b0;
a_addr77_cast_reg_6338[1] <= 1'b0;
a_addr77_cast_reg_6338[2] <= 1'b0;
a_addr77_cast_reg_6338[3] <= 1'b0;
a_addr77_cast_reg_6338[4] <= 1'b0;
a_addr77_cast_reg_6338[5] <= 1'b0;
a_addr77_cast_reg_6338[6] <= 1'b1;
a_addr77_cast_reg_6338[13] <= 1'b0;
end
always @ (ap_clk)
begin
tmp_207_reg_6348[0] <= 1'b1;
tmp_207_reg_6348[14] <= 1'b0;
tmp_207_reg_6348[15] <= 1'b0;
tmp_207_reg_6348[16] <= 1'b0;
tmp_207_reg_6348[17] <= 1'b0;
tmp_207_reg_6348[18] <= 1'b0;
tmp_207_reg_6348[19] <= 1'b0;
tmp_207_reg_6348[20] <= 1'b0;
tmp_207_reg_6348[21] <= 1'b0;
tmp_207_reg_6348[22] <= 1'b0;
tmp_207_reg_6348[23] <= 1'b0;
tmp_207_reg_6348[24] <= 1'b0;
tmp_207_reg_6348[25] <= 1'b0;
tmp_207_reg_6348[26] <= 1'b0;
tmp_207_reg_6348[27] <= 1'b0;
tmp_207_reg_6348[28] <= 1'b0;
tmp_207_reg_6348[29] <= 1'b0;
tmp_207_reg_6348[30] <= 1'b0;
tmp_207_reg_6348[31] <= 1'b0;
tmp_207_reg_6348[32] <= 1'b0;
tmp_207_reg_6348[33] <= 1'b0;
tmp_207_reg_6348[34] <= 1'b0;
tmp_207_reg_6348[35] <= 1'b0;
tmp_207_reg_6348[36] <= 1'b0;
tmp_207_reg_6348[37] <= 1'b0;
tmp_207_reg_6348[38] <= 1'b0;
tmp_207_reg_6348[39] <= 1'b0;
tmp_207_reg_6348[40] <= 1'b0;
tmp_207_reg_6348[41] <= 1'b0;
tmp_207_reg_6348[42] <= 1'b0;
tmp_207_reg_6348[43] <= 1'b0;
tmp_207_reg_6348[44] <= 1'b0;
tmp_207_reg_6348[45] <= 1'b0;
tmp_207_reg_6348[46] <= 1'b0;
tmp_207_reg_6348[47] <= 1'b0;
tmp_207_reg_6348[48] <= 1'b0;
tmp_207_reg_6348[49] <= 1'b0;
tmp_207_reg_6348[50] <= 1'b0;
tmp_207_reg_6348[51] <= 1'b0;
tmp_207_reg_6348[52] <= 1'b0;
tmp_207_reg_6348[53] <= 1'b0;
tmp_207_reg_6348[54] <= 1'b0;
tmp_207_reg_6348[55] <= 1'b0;
tmp_207_reg_6348[56] <= 1'b0;
tmp_207_reg_6348[57] <= 1'b0;
tmp_207_reg_6348[58] <= 1'b0;
tmp_207_reg_6348[59] <= 1'b0;
tmp_207_reg_6348[60] <= 1'b0;
tmp_207_reg_6348[61] <= 1'b0;
tmp_207_reg_6348[62] <= 1'b0;
tmp_207_reg_6348[63] <= 1'b0;
end
always @ (ap_clk)
begin
tmp_208_reg_6363[14] <= 1'b0;
tmp_208_reg_6363[15] <= 1'b0;
tmp_208_reg_6363[16] <= 1'b0;
tmp_208_reg_6363[17] <= 1'b0;
tmp_208_reg_6363[18] <= 1'b0;
tmp_208_reg_6363[19] <= 1'b0;
tmp_208_reg_6363[20] <= 1'b0;
tmp_208_reg_6363[21] <= 1'b0;
tmp_208_reg_6363[22] <= 1'b0;
tmp_208_reg_6363[23] <= 1'b0;
tmp_208_reg_6363[24] <= 1'b0;
tmp_208_reg_6363[25] <= 1'b0;
tmp_208_reg_6363[26] <= 1'b0;
tmp_208_reg_6363[27] <= 1'b0;
tmp_208_reg_6363[28] <= 1'b0;
tmp_208_reg_6363[29] <= 1'b0;
tmp_208_reg_6363[30] <= 1'b0;
tmp_208_reg_6363[31] <= 1'b0;
tmp_208_reg_6363[32] <= 1'b0;
tmp_208_reg_6363[33] <= 1'b0;
tmp_208_reg_6363[34] <= 1'b0;
tmp_208_reg_6363[35] <= 1'b0;
tmp_208_reg_6363[36] <= 1'b0;
tmp_208_reg_6363[37] <= 1'b0;
tmp_208_reg_6363[38] <= 1'b0;
tmp_208_reg_6363[39] <= 1'b0;
tmp_208_reg_6363[40] <= 1'b0;
tmp_208_reg_6363[41] <= 1'b0;
tmp_208_reg_6363[42] <= 1'b0;
tmp_208_reg_6363[43] <= 1'b0;
tmp_208_reg_6363[44] <= 1'b0;
tmp_208_reg_6363[45] <= 1'b0;
tmp_208_reg_6363[46] <= 1'b0;
tmp_208_reg_6363[47] <= 1'b0;
tmp_208_reg_6363[48] <= 1'b0;
tmp_208_reg_6363[49] <= 1'b0;
tmp_208_reg_6363[50] <= 1'b0;
tmp_208_reg_6363[51] <= 1'b0;
tmp_208_reg_6363[52] <= 1'b0;
tmp_208_reg_6363[53] <= 1'b0;
tmp_208_reg_6363[54] <= 1'b0;
tmp_208_reg_6363[55] <= 1'b0;
tmp_208_reg_6363[56] <= 1'b0;
tmp_208_reg_6363[57] <= 1'b0;
tmp_208_reg_6363[58] <= 1'b0;
tmp_208_reg_6363[59] <= 1'b0;
tmp_208_reg_6363[60] <= 1'b0;
tmp_208_reg_6363[61] <= 1'b0;
tmp_208_reg_6363[62] <= 1'b0;
tmp_208_reg_6363[63] <= 1'b0;
end
always @ (ap_clk)
begin
tmp_209_reg_6373[0] <= 1'b1;
tmp_209_reg_6373[1] <= 1'b1;
tmp_209_reg_6373[14] <= 1'b0;
tmp_209_reg_6373[15] <= 1'b0;
tmp_209_reg_6373[16] <= 1'b0;
tmp_209_reg_6373[17] <= 1'b0;
tmp_209_reg_6373[18] <= 1'b0;
tmp_209_reg_6373[19] <= 1'b0;
tmp_209_reg_6373[20] <= 1'b0;
tmp_209_reg_6373[21] <= 1'b0;
tmp_209_reg_6373[22] <= 1'b0;
tmp_209_reg_6373[23] <= 1'b0;
tmp_209_reg_6373[24] <= 1'b0;
tmp_209_reg_6373[25] <= 1'b0;
tmp_209_reg_6373[26] <= 1'b0;
tmp_209_reg_6373[27] <= 1'b0;
tmp_209_reg_6373[28] <= 1'b0;
tmp_209_reg_6373[29] <= 1'b0;
tmp_209_reg_6373[30] <= 1'b0;
tmp_209_reg_6373[31] <= 1'b0;
tmp_209_reg_6373[32] <= 1'b0;
tmp_209_reg_6373[33] <= 1'b0;
tmp_209_reg_6373[34] <= 1'b0;
tmp_209_reg_6373[35] <= 1'b0;
tmp_209_reg_6373[36] <= 1'b0;
tmp_209_reg_6373[37] <= 1'b0;
tmp_209_reg_6373[38] <= 1'b0;
tmp_209_reg_6373[39] <= 1'b0;
tmp_209_reg_6373[40] <= 1'b0;
tmp_209_reg_6373[41] <= 1'b0;
tmp_209_reg_6373[42] <= 1'b0;
tmp_209_reg_6373[43] <= 1'b0;
tmp_209_reg_6373[44] <= 1'b0;
tmp_209_reg_6373[45] <= 1'b0;
tmp_209_reg_6373[46] <= 1'b0;
tmp_209_reg_6373[47] <= 1'b0;
tmp_209_reg_6373[48] <= 1'b0;
tmp_209_reg_6373[49] <= 1'b0;
tmp_209_reg_6373[50] <= 1'b0;
tmp_209_reg_6373[51] <= 1'b0;
tmp_209_reg_6373[52] <= 1'b0;
tmp_209_reg_6373[53] <= 1'b0;
tmp_209_reg_6373[54] <= 1'b0;
tmp_209_reg_6373[55] <= 1'b0;
tmp_209_reg_6373[56] <= 1'b0;
tmp_209_reg_6373[57] <= 1'b0;
tmp_209_reg_6373[58] <= 1'b0;
tmp_209_reg_6373[59] <= 1'b0;
tmp_209_reg_6373[60] <= 1'b0;
tmp_209_reg_6373[61] <= 1'b0;
tmp_209_reg_6373[62] <= 1'b0;
tmp_209_reg_6373[63] <= 1'b0;
end
always @ (ap_clk)
begin
tmp_210_reg_6383[14] <= 1'b0;
tmp_210_reg_6383[15] <= 1'b0;
tmp_210_reg_6383[16] <= 1'b0;
tmp_210_reg_6383[17] <= 1'b0;
tmp_210_reg_6383[18] <= 1'b0;
tmp_210_reg_6383[19] <= 1'b0;
tmp_210_reg_6383[20] <= 1'b0;
tmp_210_reg_6383[21] <= 1'b0;
tmp_210_reg_6383[22] <= 1'b0;
tmp_210_reg_6383[23] <= 1'b0;
tmp_210_reg_6383[24] <= 1'b0;
tmp_210_reg_6383[25] <= 1'b0;
tmp_210_reg_6383[26] <= 1'b0;
tmp_210_reg_6383[27] <= 1'b0;
tmp_210_reg_6383[28] <= 1'b0;
tmp_210_reg_6383[29] <= 1'b0;
tmp_210_reg_6383[30] <= 1'b0;
tmp_210_reg_6383[31] <= 1'b0;
tmp_210_reg_6383[32] <= 1'b0;
tmp_210_reg_6383[33] <= 1'b0;
tmp_210_reg_6383[34] <= 1'b0;
tmp_210_reg_6383[35] <= 1'b0;
tmp_210_reg_6383[36] <= 1'b0;
tmp_210_reg_6383[37] <= 1'b0;
tmp_210_reg_6383[38] <= 1'b0;
tmp_210_reg_6383[39] <= 1'b0;
tmp_210_reg_6383[40] <= 1'b0;
tmp_210_reg_6383[41] <= 1'b0;
tmp_210_reg_6383[42] <= 1'b0;
tmp_210_reg_6383[43] <= 1'b0;
tmp_210_reg_6383[44] <= 1'b0;
tmp_210_reg_6383[45] <= 1'b0;
tmp_210_reg_6383[46] <= 1'b0;
tmp_210_reg_6383[47] <= 1'b0;
tmp_210_reg_6383[48] <= 1'b0;
tmp_210_reg_6383[49] <= 1'b0;
tmp_210_reg_6383[50] <= 1'b0;
tmp_210_reg_6383[51] <= 1'b0;
tmp_210_reg_6383[52] <= 1'b0;
tmp_210_reg_6383[53] <= 1'b0;
tmp_210_reg_6383[54] <= 1'b0;
tmp_210_reg_6383[55] <= 1'b0;
tmp_210_reg_6383[56] <= 1'b0;
tmp_210_reg_6383[57] <= 1'b0;
tmp_210_reg_6383[58] <= 1'b0;
tmp_210_reg_6383[59] <= 1'b0;
tmp_210_reg_6383[60] <= 1'b0;
tmp_210_reg_6383[61] <= 1'b0;
tmp_210_reg_6383[62] <= 1'b0;
tmp_210_reg_6383[63] <= 1'b0;
end
always @ (ap_clk)
begin
tmp_211_reg_6393[0] <= 1'b1;
tmp_211_reg_6393[14] <= 1'b0;
tmp_211_reg_6393[15] <= 1'b0;
tmp_211_reg_6393[16] <= 1'b0;
tmp_211_reg_6393[17] <= 1'b0;
tmp_211_reg_6393[18] <= 1'b0;
tmp_211_reg_6393[19] <= 1'b0;
tmp_211_reg_6393[20] <= 1'b0;
tmp_211_reg_6393[21] <= 1'b0;
tmp_211_reg_6393[22] <= 1'b0;
tmp_211_reg_6393[23] <= 1'b0;
tmp_211_reg_6393[24] <= 1'b0;
tmp_211_reg_6393[25] <= 1'b0;
tmp_211_reg_6393[26] <= 1'b0;
tmp_211_reg_6393[27] <= 1'b0;
tmp_211_reg_6393[28] <= 1'b0;
tmp_211_reg_6393[29] <= 1'b0;
tmp_211_reg_6393[30] <= 1'b0;
tmp_211_reg_6393[31] <= 1'b0;
tmp_211_reg_6393[32] <= 1'b0;
tmp_211_reg_6393[33] <= 1'b0;
tmp_211_reg_6393[34] <= 1'b0;
tmp_211_reg_6393[35] <= 1'b0;
tmp_211_reg_6393[36] <= 1'b0;
tmp_211_reg_6393[37] <= 1'b0;
tmp_211_reg_6393[38] <= 1'b0;
tmp_211_reg_6393[39] <= 1'b0;
tmp_211_reg_6393[40] <= 1'b0;
tmp_211_reg_6393[41] <= 1'b0;
tmp_211_reg_6393[42] <= 1'b0;
tmp_211_reg_6393[43] <= 1'b0;
tmp_211_reg_6393[44] <= 1'b0;
tmp_211_reg_6393[45] <= 1'b0;
tmp_211_reg_6393[46] <= 1'b0;
tmp_211_reg_6393[47] <= 1'b0;
tmp_211_reg_6393[48] <= 1'b0;
tmp_211_reg_6393[49] <= 1'b0;
tmp_211_reg_6393[50] <= 1'b0;
tmp_211_reg_6393[51] <= 1'b0;
tmp_211_reg_6393[52] <= 1'b0;
tmp_211_reg_6393[53] <= 1'b0;
tmp_211_reg_6393[54] <= 1'b0;
tmp_211_reg_6393[55] <= 1'b0;
tmp_211_reg_6393[56] <= 1'b0;
tmp_211_reg_6393[57] <= 1'b0;
tmp_211_reg_6393[58] <= 1'b0;
tmp_211_reg_6393[59] <= 1'b0;
tmp_211_reg_6393[60] <= 1'b0;
tmp_211_reg_6393[61] <= 1'b0;
tmp_211_reg_6393[62] <= 1'b0;
tmp_211_reg_6393[63] <= 1'b0;
end
always @ (ap_clk)
begin
tmp_212_reg_6403[14] <= 1'b0;
tmp_212_reg_6403[15] <= 1'b0;
tmp_212_reg_6403[16] <= 1'b0;
tmp_212_reg_6403[17] <= 1'b0;
tmp_212_reg_6403[18] <= 1'b0;
tmp_212_reg_6403[19] <= 1'b0;
tmp_212_reg_6403[20] <= 1'b0;
tmp_212_reg_6403[21] <= 1'b0;
tmp_212_reg_6403[22] <= 1'b0;
tmp_212_reg_6403[23] <= 1'b0;
tmp_212_reg_6403[24] <= 1'b0;
tmp_212_reg_6403[25] <= 1'b0;
tmp_212_reg_6403[26] <= 1'b0;
tmp_212_reg_6403[27] <= 1'b0;
tmp_212_reg_6403[28] <= 1'b0;
tmp_212_reg_6403[29] <= 1'b0;
tmp_212_reg_6403[30] <= 1'b0;
tmp_212_reg_6403[31] <= 1'b0;
tmp_212_reg_6403[32] <= 1'b0;
tmp_212_reg_6403[33] <= 1'b0;
tmp_212_reg_6403[34] <= 1'b0;
tmp_212_reg_6403[35] <= 1'b0;
tmp_212_reg_6403[36] <= 1'b0;
tmp_212_reg_6403[37] <= 1'b0;
tmp_212_reg_6403[38] <= 1'b0;
tmp_212_reg_6403[39] <= 1'b0;
tmp_212_reg_6403[40] <= 1'b0;
tmp_212_reg_6403[41] <= 1'b0;
tmp_212_reg_6403[42] <= 1'b0;
tmp_212_reg_6403[43] <= 1'b0;
tmp_212_reg_6403[44] <= 1'b0;
tmp_212_reg_6403[45] <= 1'b0;
tmp_212_reg_6403[46] <= 1'b0;
tmp_212_reg_6403[47] <= 1'b0;
tmp_212_reg_6403[48] <= 1'b0;
tmp_212_reg_6403[49] <= 1'b0;
tmp_212_reg_6403[50] <= 1'b0;
tmp_212_reg_6403[51] <= 1'b0;
tmp_212_reg_6403[52] <= 1'b0;
tmp_212_reg_6403[53] <= 1'b0;
tmp_212_reg_6403[54] <= 1'b0;
tmp_212_reg_6403[55] <= 1'b0;
tmp_212_reg_6403[56] <= 1'b0;
tmp_212_reg_6403[57] <= 1'b0;
tmp_212_reg_6403[58] <= 1'b0;
tmp_212_reg_6403[59] <= 1'b0;
tmp_212_reg_6403[60] <= 1'b0;
tmp_212_reg_6403[61] <= 1'b0;
tmp_212_reg_6403[62] <= 1'b0;
tmp_212_reg_6403[63] <= 1'b0;
end
always @ (ap_clk)
begin
tmp_213_reg_6413[0] <= 1'b1;
tmp_213_reg_6413[1] <= 1'b1;
tmp_213_reg_6413[2] <= 1'b1;
tmp_213_reg_6413[14] <= 1'b0;
tmp_213_reg_6413[15] <= 1'b0;
tmp_213_reg_6413[16] <= 1'b0;
tmp_213_reg_6413[17] <= 1'b0;
tmp_213_reg_6413[18] <= 1'b0;
tmp_213_reg_6413[19] <= 1'b0;
tmp_213_reg_6413[20] <= 1'b0;
tmp_213_reg_6413[21] <= 1'b0;
tmp_213_reg_6413[22] <= 1'b0;
tmp_213_reg_6413[23] <= 1'b0;
tmp_213_reg_6413[24] <= 1'b0;
tmp_213_reg_6413[25] <= 1'b0;
tmp_213_reg_6413[26] <= 1'b0;
tmp_213_reg_6413[27] <= 1'b0;
tmp_213_reg_6413[28] <= 1'b0;
tmp_213_reg_6413[29] <= 1'b0;
tmp_213_reg_6413[30] <= 1'b0;
tmp_213_reg_6413[31] <= 1'b0;
tmp_213_reg_6413[32] <= 1'b0;
tmp_213_reg_6413[33] <= 1'b0;
tmp_213_reg_6413[34] <= 1'b0;
tmp_213_reg_6413[35] <= 1'b0;
tmp_213_reg_6413[36] <= 1'b0;
tmp_213_reg_6413[37] <= 1'b0;
tmp_213_reg_6413[38] <= 1'b0;
tmp_213_reg_6413[39] <= 1'b0;
tmp_213_reg_6413[40] <= 1'b0;
tmp_213_reg_6413[41] <= 1'b0;
tmp_213_reg_6413[42] <= 1'b0;
tmp_213_reg_6413[43] <= 1'b0;
tmp_213_reg_6413[44] <= 1'b0;
tmp_213_reg_6413[45] <= 1'b0;
tmp_213_reg_6413[46] <= 1'b0;
tmp_213_reg_6413[47] <= 1'b0;
tmp_213_reg_6413[48] <= 1'b0;
tmp_213_reg_6413[49] <= 1'b0;
tmp_213_reg_6413[50] <= 1'b0;
tmp_213_reg_6413[51] <= 1'b0;
tmp_213_reg_6413[52] <= 1'b0;
tmp_213_reg_6413[53] <= 1'b0;
tmp_213_reg_6413[54] <= 1'b0;
tmp_213_reg_6413[55] <= 1'b0;
tmp_213_reg_6413[56] <= 1'b0;
tmp_213_reg_6413[57] <= 1'b0;
tmp_213_reg_6413[58] <= 1'b0;
tmp_213_reg_6413[59] <= 1'b0;
tmp_213_reg_6413[60] <= 1'b0;
tmp_213_reg_6413[61] <= 1'b0;
tmp_213_reg_6413[62] <= 1'b0;
tmp_213_reg_6413[63] <= 1'b0;
end
always @ (ap_clk)
begin
a_addr87_cast_reg_6423[0] <= 1'b0;
a_addr87_cast_reg_6423[1] <= 1'b0;
a_addr87_cast_reg_6423[2] <= 1'b0;
a_addr87_cast_reg_6423[3] <= 1'b0;
a_addr87_cast_reg_6423[4] <= 1'b0;
a_addr87_cast_reg_6423[5] <= 1'b0;
a_addr87_cast_reg_6423[7] <= 1'b1;
a_addr87_cast_reg_6423[13] <= 1'b0;
end
always @ (ap_clk)
begin
tmp_214_reg_6432[0] <= 1'b1;
tmp_214_reg_6432[14] <= 1'b0;
tmp_214_reg_6432[15] <= 1'b0;
tmp_214_reg_6432[16] <= 1'b0;
tmp_214_reg_6432[17] <= 1'b0;
tmp_214_reg_6432[18] <= 1'b0;
tmp_214_reg_6432[19] <= 1'b0;
tmp_214_reg_6432[20] <= 1'b0;
tmp_214_reg_6432[21] <= 1'b0;
tmp_214_reg_6432[22] <= 1'b0;
tmp_214_reg_6432[23] <= 1'b0;
tmp_214_reg_6432[24] <= 1'b0;
tmp_214_reg_6432[25] <= 1'b0;
tmp_214_reg_6432[26] <= 1'b0;
tmp_214_reg_6432[27] <= 1'b0;
tmp_214_reg_6432[28] <= 1'b0;
tmp_214_reg_6432[29] <= 1'b0;
tmp_214_reg_6432[30] <= 1'b0;
tmp_214_reg_6432[31] <= 1'b0;
tmp_214_reg_6432[32] <= 1'b0;
tmp_214_reg_6432[33] <= 1'b0;
tmp_214_reg_6432[34] <= 1'b0;
tmp_214_reg_6432[35] <= 1'b0;
tmp_214_reg_6432[36] <= 1'b0;
tmp_214_reg_6432[37] <= 1'b0;
tmp_214_reg_6432[38] <= 1'b0;
tmp_214_reg_6432[39] <= 1'b0;
tmp_214_reg_6432[40] <= 1'b0;
tmp_214_reg_6432[41] <= 1'b0;
tmp_214_reg_6432[42] <= 1'b0;
tmp_214_reg_6432[43] <= 1'b0;
tmp_214_reg_6432[44] <= 1'b0;
tmp_214_reg_6432[45] <= 1'b0;
tmp_214_reg_6432[46] <= 1'b0;
tmp_214_reg_6432[47] <= 1'b0;
tmp_214_reg_6432[48] <= 1'b0;
tmp_214_reg_6432[49] <= 1'b0;
tmp_214_reg_6432[50] <= 1'b0;
tmp_214_reg_6432[51] <= 1'b0;
tmp_214_reg_6432[52] <= 1'b0;
tmp_214_reg_6432[53] <= 1'b0;
tmp_214_reg_6432[54] <= 1'b0;
tmp_214_reg_6432[55] <= 1'b0;
tmp_214_reg_6432[56] <= 1'b0;
tmp_214_reg_6432[57] <= 1'b0;
tmp_214_reg_6432[58] <= 1'b0;
tmp_214_reg_6432[59] <= 1'b0;
tmp_214_reg_6432[60] <= 1'b0;
tmp_214_reg_6432[61] <= 1'b0;
tmp_214_reg_6432[62] <= 1'b0;
tmp_214_reg_6432[63] <= 1'b0;
end
always @ (ap_clk)
begin
tmp_215_reg_6442[14] <= 1'b0;
tmp_215_reg_6442[15] <= 1'b0;
tmp_215_reg_6442[16] <= 1'b0;
tmp_215_reg_6442[17] <= 1'b0;
tmp_215_reg_6442[18] <= 1'b0;
tmp_215_reg_6442[19] <= 1'b0;
tmp_215_reg_6442[20] <= 1'b0;
tmp_215_reg_6442[21] <= 1'b0;
tmp_215_reg_6442[22] <= 1'b0;
tmp_215_reg_6442[23] <= 1'b0;
tmp_215_reg_6442[24] <= 1'b0;
tmp_215_reg_6442[25] <= 1'b0;
tmp_215_reg_6442[26] <= 1'b0;
tmp_215_reg_6442[27] <= 1'b0;
tmp_215_reg_6442[28] <= 1'b0;
tmp_215_reg_6442[29] <= 1'b0;
tmp_215_reg_6442[30] <= 1'b0;
tmp_215_reg_6442[31] <= 1'b0;
tmp_215_reg_6442[32] <= 1'b0;
tmp_215_reg_6442[33] <= 1'b0;
tmp_215_reg_6442[34] <= 1'b0;
tmp_215_reg_6442[35] <= 1'b0;
tmp_215_reg_6442[36] <= 1'b0;
tmp_215_reg_6442[37] <= 1'b0;
tmp_215_reg_6442[38] <= 1'b0;
tmp_215_reg_6442[39] <= 1'b0;
tmp_215_reg_6442[40] <= 1'b0;
tmp_215_reg_6442[41] <= 1'b0;
tmp_215_reg_6442[42] <= 1'b0;
tmp_215_reg_6442[43] <= 1'b0;
tmp_215_reg_6442[44] <= 1'b0;
tmp_215_reg_6442[45] <= 1'b0;
tmp_215_reg_6442[46] <= 1'b0;
tmp_215_reg_6442[47] <= 1'b0;
tmp_215_reg_6442[48] <= 1'b0;
tmp_215_reg_6442[49] <= 1'b0;
tmp_215_reg_6442[50] <= 1'b0;
tmp_215_reg_6442[51] <= 1'b0;
tmp_215_reg_6442[52] <= 1'b0;
tmp_215_reg_6442[53] <= 1'b0;
tmp_215_reg_6442[54] <= 1'b0;
tmp_215_reg_6442[55] <= 1'b0;
tmp_215_reg_6442[56] <= 1'b0;
tmp_215_reg_6442[57] <= 1'b0;
tmp_215_reg_6442[58] <= 1'b0;
tmp_215_reg_6442[59] <= 1'b0;
tmp_215_reg_6442[60] <= 1'b0;
tmp_215_reg_6442[61] <= 1'b0;
tmp_215_reg_6442[62] <= 1'b0;
tmp_215_reg_6442[63] <= 1'b0;
end
always @ (ap_clk)
begin
tmp_216_reg_6452[0] <= 1'b1;
tmp_216_reg_6452[1] <= 1'b1;
tmp_216_reg_6452[14] <= 1'b0;
tmp_216_reg_6452[15] <= 1'b0;
tmp_216_reg_6452[16] <= 1'b0;
tmp_216_reg_6452[17] <= 1'b0;
tmp_216_reg_6452[18] <= 1'b0;
tmp_216_reg_6452[19] <= 1'b0;
tmp_216_reg_6452[20] <= 1'b0;
tmp_216_reg_6452[21] <= 1'b0;
tmp_216_reg_6452[22] <= 1'b0;
tmp_216_reg_6452[23] <= 1'b0;
tmp_216_reg_6452[24] <= 1'b0;
tmp_216_reg_6452[25] <= 1'b0;
tmp_216_reg_6452[26] <= 1'b0;
tmp_216_reg_6452[27] <= 1'b0;
tmp_216_reg_6452[28] <= 1'b0;
tmp_216_reg_6452[29] <= 1'b0;
tmp_216_reg_6452[30] <= 1'b0;
tmp_216_reg_6452[31] <= 1'b0;
tmp_216_reg_6452[32] <= 1'b0;
tmp_216_reg_6452[33] <= 1'b0;
tmp_216_reg_6452[34] <= 1'b0;
tmp_216_reg_6452[35] <= 1'b0;
tmp_216_reg_6452[36] <= 1'b0;
tmp_216_reg_6452[37] <= 1'b0;
tmp_216_reg_6452[38] <= 1'b0;
tmp_216_reg_6452[39] <= 1'b0;
tmp_216_reg_6452[40] <= 1'b0;
tmp_216_reg_6452[41] <= 1'b0;
tmp_216_reg_6452[42] <= 1'b0;
tmp_216_reg_6452[43] <= 1'b0;
tmp_216_reg_6452[44] <= 1'b0;
tmp_216_reg_6452[45] <= 1'b0;
tmp_216_reg_6452[46] <= 1'b0;
tmp_216_reg_6452[47] <= 1'b0;
tmp_216_reg_6452[48] <= 1'b0;
tmp_216_reg_6452[49] <= 1'b0;
tmp_216_reg_6452[50] <= 1'b0;
tmp_216_reg_6452[51] <= 1'b0;
tmp_216_reg_6452[52] <= 1'b0;
tmp_216_reg_6452[53] <= 1'b0;
tmp_216_reg_6452[54] <= 1'b0;
tmp_216_reg_6452[55] <= 1'b0;
tmp_216_reg_6452[56] <= 1'b0;
tmp_216_reg_6452[57] <= 1'b0;
tmp_216_reg_6452[58] <= 1'b0;
tmp_216_reg_6452[59] <= 1'b0;
tmp_216_reg_6452[60] <= 1'b0;
tmp_216_reg_6452[61] <= 1'b0;
tmp_216_reg_6452[62] <= 1'b0;
tmp_216_reg_6452[63] <= 1'b0;
end
always @ (ap_clk)
begin
tmp_217_reg_6462[14] <= 1'b0;
tmp_217_reg_6462[15] <= 1'b0;
tmp_217_reg_6462[16] <= 1'b0;
tmp_217_reg_6462[17] <= 1'b0;
tmp_217_reg_6462[18] <= 1'b0;
tmp_217_reg_6462[19] <= 1'b0;
tmp_217_reg_6462[20] <= 1'b0;
tmp_217_reg_6462[21] <= 1'b0;
tmp_217_reg_6462[22] <= 1'b0;
tmp_217_reg_6462[23] <= 1'b0;
tmp_217_reg_6462[24] <= 1'b0;
tmp_217_reg_6462[25] <= 1'b0;
tmp_217_reg_6462[26] <= 1'b0;
tmp_217_reg_6462[27] <= 1'b0;
tmp_217_reg_6462[28] <= 1'b0;
tmp_217_reg_6462[29] <= 1'b0;
tmp_217_reg_6462[30] <= 1'b0;
tmp_217_reg_6462[31] <= 1'b0;
tmp_217_reg_6462[32] <= 1'b0;
tmp_217_reg_6462[33] <= 1'b0;
tmp_217_reg_6462[34] <= 1'b0;
tmp_217_reg_6462[35] <= 1'b0;
tmp_217_reg_6462[36] <= 1'b0;
tmp_217_reg_6462[37] <= 1'b0;
tmp_217_reg_6462[38] <= 1'b0;
tmp_217_reg_6462[39] <= 1'b0;
tmp_217_reg_6462[40] <= 1'b0;
tmp_217_reg_6462[41] <= 1'b0;
tmp_217_reg_6462[42] <= 1'b0;
tmp_217_reg_6462[43] <= 1'b0;
tmp_217_reg_6462[44] <= 1'b0;
tmp_217_reg_6462[45] <= 1'b0;
tmp_217_reg_6462[46] <= 1'b0;
tmp_217_reg_6462[47] <= 1'b0;
tmp_217_reg_6462[48] <= 1'b0;
tmp_217_reg_6462[49] <= 1'b0;
tmp_217_reg_6462[50] <= 1'b0;
tmp_217_reg_6462[51] <= 1'b0;
tmp_217_reg_6462[52] <= 1'b0;
tmp_217_reg_6462[53] <= 1'b0;
tmp_217_reg_6462[54] <= 1'b0;
tmp_217_reg_6462[55] <= 1'b0;
tmp_217_reg_6462[56] <= 1'b0;
tmp_217_reg_6462[57] <= 1'b0;
tmp_217_reg_6462[58] <= 1'b0;
tmp_217_reg_6462[59] <= 1'b0;
tmp_217_reg_6462[60] <= 1'b0;
tmp_217_reg_6462[61] <= 1'b0;
tmp_217_reg_6462[62] <= 1'b0;
tmp_217_reg_6462[63] <= 1'b0;
end
always @ (ap_clk)
begin
tmp_218_reg_6472[0] <= 1'b1;
tmp_218_reg_6472[14] <= 1'b0;
tmp_218_reg_6472[15] <= 1'b0;
tmp_218_reg_6472[16] <= 1'b0;
tmp_218_reg_6472[17] <= 1'b0;
tmp_218_reg_6472[18] <= 1'b0;
tmp_218_reg_6472[19] <= 1'b0;
tmp_218_reg_6472[20] <= 1'b0;
tmp_218_reg_6472[21] <= 1'b0;
tmp_218_reg_6472[22] <= 1'b0;
tmp_218_reg_6472[23] <= 1'b0;
tmp_218_reg_6472[24] <= 1'b0;
tmp_218_reg_6472[25] <= 1'b0;
tmp_218_reg_6472[26] <= 1'b0;
tmp_218_reg_6472[27] <= 1'b0;
tmp_218_reg_6472[28] <= 1'b0;
tmp_218_reg_6472[29] <= 1'b0;
tmp_218_reg_6472[30] <= 1'b0;
tmp_218_reg_6472[31] <= 1'b0;
tmp_218_reg_6472[32] <= 1'b0;
tmp_218_reg_6472[33] <= 1'b0;
tmp_218_reg_6472[34] <= 1'b0;
tmp_218_reg_6472[35] <= 1'b0;
tmp_218_reg_6472[36] <= 1'b0;
tmp_218_reg_6472[37] <= 1'b0;
tmp_218_reg_6472[38] <= 1'b0;
tmp_218_reg_6472[39] <= 1'b0;
tmp_218_reg_6472[40] <= 1'b0;
tmp_218_reg_6472[41] <= 1'b0;
tmp_218_reg_6472[42] <= 1'b0;
tmp_218_reg_6472[43] <= 1'b0;
tmp_218_reg_6472[44] <= 1'b0;
tmp_218_reg_6472[45] <= 1'b0;
tmp_218_reg_6472[46] <= 1'b0;
tmp_218_reg_6472[47] <= 1'b0;
tmp_218_reg_6472[48] <= 1'b0;
tmp_218_reg_6472[49] <= 1'b0;
tmp_218_reg_6472[50] <= 1'b0;
tmp_218_reg_6472[51] <= 1'b0;
tmp_218_reg_6472[52] <= 1'b0;
tmp_218_reg_6472[53] <= 1'b0;
tmp_218_reg_6472[54] <= 1'b0;
tmp_218_reg_6472[55] <= 1'b0;
tmp_218_reg_6472[56] <= 1'b0;
tmp_218_reg_6472[57] <= 1'b0;
tmp_218_reg_6472[58] <= 1'b0;
tmp_218_reg_6472[59] <= 1'b0;
tmp_218_reg_6472[60] <= 1'b0;
tmp_218_reg_6472[61] <= 1'b0;
tmp_218_reg_6472[62] <= 1'b0;
tmp_218_reg_6472[63] <= 1'b0;
end
always @ (ap_clk)
begin
tmp_219_reg_6482[14] <= 1'b0;
tmp_219_reg_6482[15] <= 1'b0;
tmp_219_reg_6482[16] <= 1'b0;
tmp_219_reg_6482[17] <= 1'b0;
tmp_219_reg_6482[18] <= 1'b0;
tmp_219_reg_6482[19] <= 1'b0;
tmp_219_reg_6482[20] <= 1'b0;
tmp_219_reg_6482[21] <= 1'b0;
tmp_219_reg_6482[22] <= 1'b0;
tmp_219_reg_6482[23] <= 1'b0;
tmp_219_reg_6482[24] <= 1'b0;
tmp_219_reg_6482[25] <= 1'b0;
tmp_219_reg_6482[26] <= 1'b0;
tmp_219_reg_6482[27] <= 1'b0;
tmp_219_reg_6482[28] <= 1'b0;
tmp_219_reg_6482[29] <= 1'b0;
tmp_219_reg_6482[30] <= 1'b0;
tmp_219_reg_6482[31] <= 1'b0;
tmp_219_reg_6482[32] <= 1'b0;
tmp_219_reg_6482[33] <= 1'b0;
tmp_219_reg_6482[34] <= 1'b0;
tmp_219_reg_6482[35] <= 1'b0;
tmp_219_reg_6482[36] <= 1'b0;
tmp_219_reg_6482[37] <= 1'b0;
tmp_219_reg_6482[38] <= 1'b0;
tmp_219_reg_6482[39] <= 1'b0;
tmp_219_reg_6482[40] <= 1'b0;
tmp_219_reg_6482[41] <= 1'b0;
tmp_219_reg_6482[42] <= 1'b0;
tmp_219_reg_6482[43] <= 1'b0;
tmp_219_reg_6482[44] <= 1'b0;
tmp_219_reg_6482[45] <= 1'b0;
tmp_219_reg_6482[46] <= 1'b0;
tmp_219_reg_6482[47] <= 1'b0;
tmp_219_reg_6482[48] <= 1'b0;
tmp_219_reg_6482[49] <= 1'b0;
tmp_219_reg_6482[50] <= 1'b0;
tmp_219_reg_6482[51] <= 1'b0;
tmp_219_reg_6482[52] <= 1'b0;
tmp_219_reg_6482[53] <= 1'b0;
tmp_219_reg_6482[54] <= 1'b0;
tmp_219_reg_6482[55] <= 1'b0;
tmp_219_reg_6482[56] <= 1'b0;
tmp_219_reg_6482[57] <= 1'b0;
tmp_219_reg_6482[58] <= 1'b0;
tmp_219_reg_6482[59] <= 1'b0;
tmp_219_reg_6482[60] <= 1'b0;
tmp_219_reg_6482[61] <= 1'b0;
tmp_219_reg_6482[62] <= 1'b0;
tmp_219_reg_6482[63] <= 1'b0;
end
always @ (ap_clk)
begin
tmp_220_reg_6492[0] <= 1'b1;
tmp_220_reg_6492[1] <= 1'b1;
tmp_220_reg_6492[2] <= 1'b1;
tmp_220_reg_6492[14] <= 1'b0;
tmp_220_reg_6492[15] <= 1'b0;
tmp_220_reg_6492[16] <= 1'b0;
tmp_220_reg_6492[17] <= 1'b0;
tmp_220_reg_6492[18] <= 1'b0;
tmp_220_reg_6492[19] <= 1'b0;
tmp_220_reg_6492[20] <= 1'b0;
tmp_220_reg_6492[21] <= 1'b0;
tmp_220_reg_6492[22] <= 1'b0;
tmp_220_reg_6492[23] <= 1'b0;
tmp_220_reg_6492[24] <= 1'b0;
tmp_220_reg_6492[25] <= 1'b0;
tmp_220_reg_6492[26] <= 1'b0;
tmp_220_reg_6492[27] <= 1'b0;
tmp_220_reg_6492[28] <= 1'b0;
tmp_220_reg_6492[29] <= 1'b0;
tmp_220_reg_6492[30] <= 1'b0;
tmp_220_reg_6492[31] <= 1'b0;
tmp_220_reg_6492[32] <= 1'b0;
tmp_220_reg_6492[33] <= 1'b0;
tmp_220_reg_6492[34] <= 1'b0;
tmp_220_reg_6492[35] <= 1'b0;
tmp_220_reg_6492[36] <= 1'b0;
tmp_220_reg_6492[37] <= 1'b0;
tmp_220_reg_6492[38] <= 1'b0;
tmp_220_reg_6492[39] <= 1'b0;
tmp_220_reg_6492[40] <= 1'b0;
tmp_220_reg_6492[41] <= 1'b0;
tmp_220_reg_6492[42] <= 1'b0;
tmp_220_reg_6492[43] <= 1'b0;
tmp_220_reg_6492[44] <= 1'b0;
tmp_220_reg_6492[45] <= 1'b0;
tmp_220_reg_6492[46] <= 1'b0;
tmp_220_reg_6492[47] <= 1'b0;
tmp_220_reg_6492[48] <= 1'b0;
tmp_220_reg_6492[49] <= 1'b0;
tmp_220_reg_6492[50] <= 1'b0;
tmp_220_reg_6492[51] <= 1'b0;
tmp_220_reg_6492[52] <= 1'b0;
tmp_220_reg_6492[53] <= 1'b0;
tmp_220_reg_6492[54] <= 1'b0;
tmp_220_reg_6492[55] <= 1'b0;
tmp_220_reg_6492[56] <= 1'b0;
tmp_220_reg_6492[57] <= 1'b0;
tmp_220_reg_6492[58] <= 1'b0;
tmp_220_reg_6492[59] <= 1'b0;
tmp_220_reg_6492[60] <= 1'b0;
tmp_220_reg_6492[61] <= 1'b0;
tmp_220_reg_6492[62] <= 1'b0;
tmp_220_reg_6492[63] <= 1'b0;
end
always @ (ap_clk)
begin
a_addr98_cast_reg_6502[0] <= 1'b0;
a_addr98_cast_reg_6502[1] <= 1'b0;
a_addr98_cast_reg_6502[2] <= 1'b0;
a_addr98_cast_reg_6502[3] <= 1'b0;
a_addr98_cast_reg_6502[4] <= 1'b0;
a_addr98_cast_reg_6502[5] <= 1'b0;
a_addr98_cast_reg_6502[6] <= 1'b1;
a_addr98_cast_reg_6502[7] <= 1'b1;
a_addr98_cast_reg_6502[13] <= 1'b0;
end
always @ (ap_clk)
begin
tmp_221_reg_6512[0] <= 1'b1;
tmp_221_reg_6512[14] <= 1'b0;
tmp_221_reg_6512[15] <= 1'b0;
tmp_221_reg_6512[16] <= 1'b0;
tmp_221_reg_6512[17] <= 1'b0;
tmp_221_reg_6512[18] <= 1'b0;
tmp_221_reg_6512[19] <= 1'b0;
tmp_221_reg_6512[20] <= 1'b0;
tmp_221_reg_6512[21] <= 1'b0;
tmp_221_reg_6512[22] <= 1'b0;
tmp_221_reg_6512[23] <= 1'b0;
tmp_221_reg_6512[24] <= 1'b0;
tmp_221_reg_6512[25] <= 1'b0;
tmp_221_reg_6512[26] <= 1'b0;
tmp_221_reg_6512[27] <= 1'b0;
tmp_221_reg_6512[28] <= 1'b0;
tmp_221_reg_6512[29] <= 1'b0;
tmp_221_reg_6512[30] <= 1'b0;
tmp_221_reg_6512[31] <= 1'b0;
tmp_221_reg_6512[32] <= 1'b0;
tmp_221_reg_6512[33] <= 1'b0;
tmp_221_reg_6512[34] <= 1'b0;
tmp_221_reg_6512[35] <= 1'b0;
tmp_221_reg_6512[36] <= 1'b0;
tmp_221_reg_6512[37] <= 1'b0;
tmp_221_reg_6512[38] <= 1'b0;
tmp_221_reg_6512[39] <= 1'b0;
tmp_221_reg_6512[40] <= 1'b0;
tmp_221_reg_6512[41] <= 1'b0;
tmp_221_reg_6512[42] <= 1'b0;
tmp_221_reg_6512[43] <= 1'b0;
tmp_221_reg_6512[44] <= 1'b0;
tmp_221_reg_6512[45] <= 1'b0;
tmp_221_reg_6512[46] <= 1'b0;
tmp_221_reg_6512[47] <= 1'b0;
tmp_221_reg_6512[48] <= 1'b0;
tmp_221_reg_6512[49] <= 1'b0;
tmp_221_reg_6512[50] <= 1'b0;
tmp_221_reg_6512[51] <= 1'b0;
tmp_221_reg_6512[52] <= 1'b0;
tmp_221_reg_6512[53] <= 1'b0;
tmp_221_reg_6512[54] <= 1'b0;
tmp_221_reg_6512[55] <= 1'b0;
tmp_221_reg_6512[56] <= 1'b0;
tmp_221_reg_6512[57] <= 1'b0;
tmp_221_reg_6512[58] <= 1'b0;
tmp_221_reg_6512[59] <= 1'b0;
tmp_221_reg_6512[60] <= 1'b0;
tmp_221_reg_6512[61] <= 1'b0;
tmp_221_reg_6512[62] <= 1'b0;
tmp_221_reg_6512[63] <= 1'b0;
end
always @ (ap_clk)
begin
tmp_222_reg_6522[14] <= 1'b0;
tmp_222_reg_6522[15] <= 1'b0;
tmp_222_reg_6522[16] <= 1'b0;
tmp_222_reg_6522[17] <= 1'b0;
tmp_222_reg_6522[18] <= 1'b0;
tmp_222_reg_6522[19] <= 1'b0;
tmp_222_reg_6522[20] <= 1'b0;
tmp_222_reg_6522[21] <= 1'b0;
tmp_222_reg_6522[22] <= 1'b0;
tmp_222_reg_6522[23] <= 1'b0;
tmp_222_reg_6522[24] <= 1'b0;
tmp_222_reg_6522[25] <= 1'b0;
tmp_222_reg_6522[26] <= 1'b0;
tmp_222_reg_6522[27] <= 1'b0;
tmp_222_reg_6522[28] <= 1'b0;
tmp_222_reg_6522[29] <= 1'b0;
tmp_222_reg_6522[30] <= 1'b0;
tmp_222_reg_6522[31] <= 1'b0;
tmp_222_reg_6522[32] <= 1'b0;
tmp_222_reg_6522[33] <= 1'b0;
tmp_222_reg_6522[34] <= 1'b0;
tmp_222_reg_6522[35] <= 1'b0;
tmp_222_reg_6522[36] <= 1'b0;
tmp_222_reg_6522[37] <= 1'b0;
tmp_222_reg_6522[38] <= 1'b0;
tmp_222_reg_6522[39] <= 1'b0;
tmp_222_reg_6522[40] <= 1'b0;
tmp_222_reg_6522[41] <= 1'b0;
tmp_222_reg_6522[42] <= 1'b0;
tmp_222_reg_6522[43] <= 1'b0;
tmp_222_reg_6522[44] <= 1'b0;
tmp_222_reg_6522[45] <= 1'b0;
tmp_222_reg_6522[46] <= 1'b0;
tmp_222_reg_6522[47] <= 1'b0;
tmp_222_reg_6522[48] <= 1'b0;
tmp_222_reg_6522[49] <= 1'b0;
tmp_222_reg_6522[50] <= 1'b0;
tmp_222_reg_6522[51] <= 1'b0;
tmp_222_reg_6522[52] <= 1'b0;
tmp_222_reg_6522[53] <= 1'b0;
tmp_222_reg_6522[54] <= 1'b0;
tmp_222_reg_6522[55] <= 1'b0;
tmp_222_reg_6522[56] <= 1'b0;
tmp_222_reg_6522[57] <= 1'b0;
tmp_222_reg_6522[58] <= 1'b0;
tmp_222_reg_6522[59] <= 1'b0;
tmp_222_reg_6522[60] <= 1'b0;
tmp_222_reg_6522[61] <= 1'b0;
tmp_222_reg_6522[62] <= 1'b0;
tmp_222_reg_6522[63] <= 1'b0;
end
always @ (ap_clk)
begin
tmp_223_reg_6532[0] <= 1'b1;
tmp_223_reg_6532[1] <= 1'b1;
tmp_223_reg_6532[14] <= 1'b0;
tmp_223_reg_6532[15] <= 1'b0;
tmp_223_reg_6532[16] <= 1'b0;
tmp_223_reg_6532[17] <= 1'b0;
tmp_223_reg_6532[18] <= 1'b0;
tmp_223_reg_6532[19] <= 1'b0;
tmp_223_reg_6532[20] <= 1'b0;
tmp_223_reg_6532[21] <= 1'b0;
tmp_223_reg_6532[22] <= 1'b0;
tmp_223_reg_6532[23] <= 1'b0;
tmp_223_reg_6532[24] <= 1'b0;
tmp_223_reg_6532[25] <= 1'b0;
tmp_223_reg_6532[26] <= 1'b0;
tmp_223_reg_6532[27] <= 1'b0;
tmp_223_reg_6532[28] <= 1'b0;
tmp_223_reg_6532[29] <= 1'b0;
tmp_223_reg_6532[30] <= 1'b0;
tmp_223_reg_6532[31] <= 1'b0;
tmp_223_reg_6532[32] <= 1'b0;
tmp_223_reg_6532[33] <= 1'b0;
tmp_223_reg_6532[34] <= 1'b0;
tmp_223_reg_6532[35] <= 1'b0;
tmp_223_reg_6532[36] <= 1'b0;
tmp_223_reg_6532[37] <= 1'b0;
tmp_223_reg_6532[38] <= 1'b0;
tmp_223_reg_6532[39] <= 1'b0;
tmp_223_reg_6532[40] <= 1'b0;
tmp_223_reg_6532[41] <= 1'b0;
tmp_223_reg_6532[42] <= 1'b0;
tmp_223_reg_6532[43] <= 1'b0;
tmp_223_reg_6532[44] <= 1'b0;
tmp_223_reg_6532[45] <= 1'b0;
tmp_223_reg_6532[46] <= 1'b0;
tmp_223_reg_6532[47] <= 1'b0;
tmp_223_reg_6532[48] <= 1'b0;
tmp_223_reg_6532[49] <= 1'b0;
tmp_223_reg_6532[50] <= 1'b0;
tmp_223_reg_6532[51] <= 1'b0;
tmp_223_reg_6532[52] <= 1'b0;
tmp_223_reg_6532[53] <= 1'b0;
tmp_223_reg_6532[54] <= 1'b0;
tmp_223_reg_6532[55] <= 1'b0;
tmp_223_reg_6532[56] <= 1'b0;
tmp_223_reg_6532[57] <= 1'b0;
tmp_223_reg_6532[58] <= 1'b0;
tmp_223_reg_6532[59] <= 1'b0;
tmp_223_reg_6532[60] <= 1'b0;
tmp_223_reg_6532[61] <= 1'b0;
tmp_223_reg_6532[62] <= 1'b0;
tmp_223_reg_6532[63] <= 1'b0;
end
always @ (ap_clk)
begin
tmp_224_reg_6542[14] <= 1'b0;
tmp_224_reg_6542[15] <= 1'b0;
tmp_224_reg_6542[16] <= 1'b0;
tmp_224_reg_6542[17] <= 1'b0;
tmp_224_reg_6542[18] <= 1'b0;
tmp_224_reg_6542[19] <= 1'b0;
tmp_224_reg_6542[20] <= 1'b0;
tmp_224_reg_6542[21] <= 1'b0;
tmp_224_reg_6542[22] <= 1'b0;
tmp_224_reg_6542[23] <= 1'b0;
tmp_224_reg_6542[24] <= 1'b0;
tmp_224_reg_6542[25] <= 1'b0;
tmp_224_reg_6542[26] <= 1'b0;
tmp_224_reg_6542[27] <= 1'b0;
tmp_224_reg_6542[28] <= 1'b0;
tmp_224_reg_6542[29] <= 1'b0;
tmp_224_reg_6542[30] <= 1'b0;
tmp_224_reg_6542[31] <= 1'b0;
tmp_224_reg_6542[32] <= 1'b0;
tmp_224_reg_6542[33] <= 1'b0;
tmp_224_reg_6542[34] <= 1'b0;
tmp_224_reg_6542[35] <= 1'b0;
tmp_224_reg_6542[36] <= 1'b0;
tmp_224_reg_6542[37] <= 1'b0;
tmp_224_reg_6542[38] <= 1'b0;
tmp_224_reg_6542[39] <= 1'b0;
tmp_224_reg_6542[40] <= 1'b0;
tmp_224_reg_6542[41] <= 1'b0;
tmp_224_reg_6542[42] <= 1'b0;
tmp_224_reg_6542[43] <= 1'b0;
tmp_224_reg_6542[44] <= 1'b0;
tmp_224_reg_6542[45] <= 1'b0;
tmp_224_reg_6542[46] <= 1'b0;
tmp_224_reg_6542[47] <= 1'b0;
tmp_224_reg_6542[48] <= 1'b0;
tmp_224_reg_6542[49] <= 1'b0;
tmp_224_reg_6542[50] <= 1'b0;
tmp_224_reg_6542[51] <= 1'b0;
tmp_224_reg_6542[52] <= 1'b0;
tmp_224_reg_6542[53] <= 1'b0;
tmp_224_reg_6542[54] <= 1'b0;
tmp_224_reg_6542[55] <= 1'b0;
tmp_224_reg_6542[56] <= 1'b0;
tmp_224_reg_6542[57] <= 1'b0;
tmp_224_reg_6542[58] <= 1'b0;
tmp_224_reg_6542[59] <= 1'b0;
tmp_224_reg_6542[60] <= 1'b0;
tmp_224_reg_6542[61] <= 1'b0;
tmp_224_reg_6542[62] <= 1'b0;
tmp_224_reg_6542[63] <= 1'b0;
end
always @ (ap_clk)
begin
tmp_225_reg_6552[0] <= 1'b1;
tmp_225_reg_6552[14] <= 1'b0;
tmp_225_reg_6552[15] <= 1'b0;
tmp_225_reg_6552[16] <= 1'b0;
tmp_225_reg_6552[17] <= 1'b0;
tmp_225_reg_6552[18] <= 1'b0;
tmp_225_reg_6552[19] <= 1'b0;
tmp_225_reg_6552[20] <= 1'b0;
tmp_225_reg_6552[21] <= 1'b0;
tmp_225_reg_6552[22] <= 1'b0;
tmp_225_reg_6552[23] <= 1'b0;
tmp_225_reg_6552[24] <= 1'b0;
tmp_225_reg_6552[25] <= 1'b0;
tmp_225_reg_6552[26] <= 1'b0;
tmp_225_reg_6552[27] <= 1'b0;
tmp_225_reg_6552[28] <= 1'b0;
tmp_225_reg_6552[29] <= 1'b0;
tmp_225_reg_6552[30] <= 1'b0;
tmp_225_reg_6552[31] <= 1'b0;
tmp_225_reg_6552[32] <= 1'b0;
tmp_225_reg_6552[33] <= 1'b0;
tmp_225_reg_6552[34] <= 1'b0;
tmp_225_reg_6552[35] <= 1'b0;
tmp_225_reg_6552[36] <= 1'b0;
tmp_225_reg_6552[37] <= 1'b0;
tmp_225_reg_6552[38] <= 1'b0;
tmp_225_reg_6552[39] <= 1'b0;
tmp_225_reg_6552[40] <= 1'b0;
tmp_225_reg_6552[41] <= 1'b0;
tmp_225_reg_6552[42] <= 1'b0;
tmp_225_reg_6552[43] <= 1'b0;
tmp_225_reg_6552[44] <= 1'b0;
tmp_225_reg_6552[45] <= 1'b0;
tmp_225_reg_6552[46] <= 1'b0;
tmp_225_reg_6552[47] <= 1'b0;
tmp_225_reg_6552[48] <= 1'b0;
tmp_225_reg_6552[49] <= 1'b0;
tmp_225_reg_6552[50] <= 1'b0;
tmp_225_reg_6552[51] <= 1'b0;
tmp_225_reg_6552[52] <= 1'b0;
tmp_225_reg_6552[53] <= 1'b0;
tmp_225_reg_6552[54] <= 1'b0;
tmp_225_reg_6552[55] <= 1'b0;
tmp_225_reg_6552[56] <= 1'b0;
tmp_225_reg_6552[57] <= 1'b0;
tmp_225_reg_6552[58] <= 1'b0;
tmp_225_reg_6552[59] <= 1'b0;
tmp_225_reg_6552[60] <= 1'b0;
tmp_225_reg_6552[61] <= 1'b0;
tmp_225_reg_6552[62] <= 1'b0;
tmp_225_reg_6552[63] <= 1'b0;
end
always @ (ap_clk)
begin
tmp_226_reg_6562[14] <= 1'b0;
tmp_226_reg_6562[15] <= 1'b0;
tmp_226_reg_6562[16] <= 1'b0;
tmp_226_reg_6562[17] <= 1'b0;
tmp_226_reg_6562[18] <= 1'b0;
tmp_226_reg_6562[19] <= 1'b0;
tmp_226_reg_6562[20] <= 1'b0;
tmp_226_reg_6562[21] <= 1'b0;
tmp_226_reg_6562[22] <= 1'b0;
tmp_226_reg_6562[23] <= 1'b0;
tmp_226_reg_6562[24] <= 1'b0;
tmp_226_reg_6562[25] <= 1'b0;
tmp_226_reg_6562[26] <= 1'b0;
tmp_226_reg_6562[27] <= 1'b0;
tmp_226_reg_6562[28] <= 1'b0;
tmp_226_reg_6562[29] <= 1'b0;
tmp_226_reg_6562[30] <= 1'b0;
tmp_226_reg_6562[31] <= 1'b0;
tmp_226_reg_6562[32] <= 1'b0;
tmp_226_reg_6562[33] <= 1'b0;
tmp_226_reg_6562[34] <= 1'b0;
tmp_226_reg_6562[35] <= 1'b0;
tmp_226_reg_6562[36] <= 1'b0;
tmp_226_reg_6562[37] <= 1'b0;
tmp_226_reg_6562[38] <= 1'b0;
tmp_226_reg_6562[39] <= 1'b0;
tmp_226_reg_6562[40] <= 1'b0;
tmp_226_reg_6562[41] <= 1'b0;
tmp_226_reg_6562[42] <= 1'b0;
tmp_226_reg_6562[43] <= 1'b0;
tmp_226_reg_6562[44] <= 1'b0;
tmp_226_reg_6562[45] <= 1'b0;
tmp_226_reg_6562[46] <= 1'b0;
tmp_226_reg_6562[47] <= 1'b0;
tmp_226_reg_6562[48] <= 1'b0;
tmp_226_reg_6562[49] <= 1'b0;
tmp_226_reg_6562[50] <= 1'b0;
tmp_226_reg_6562[51] <= 1'b0;
tmp_226_reg_6562[52] <= 1'b0;
tmp_226_reg_6562[53] <= 1'b0;
tmp_226_reg_6562[54] <= 1'b0;
tmp_226_reg_6562[55] <= 1'b0;
tmp_226_reg_6562[56] <= 1'b0;
tmp_226_reg_6562[57] <= 1'b0;
tmp_226_reg_6562[58] <= 1'b0;
tmp_226_reg_6562[59] <= 1'b0;
tmp_226_reg_6562[60] <= 1'b0;
tmp_226_reg_6562[61] <= 1'b0;
tmp_226_reg_6562[62] <= 1'b0;
tmp_226_reg_6562[63] <= 1'b0;
end
always @ (ap_clk)
begin
tmp_227_reg_6572[0] <= 1'b1;
tmp_227_reg_6572[1] <= 1'b1;
tmp_227_reg_6572[2] <= 1'b1;
tmp_227_reg_6572[14] <= 1'b0;
tmp_227_reg_6572[15] <= 1'b0;
tmp_227_reg_6572[16] <= 1'b0;
tmp_227_reg_6572[17] <= 1'b0;
tmp_227_reg_6572[18] <= 1'b0;
tmp_227_reg_6572[19] <= 1'b0;
tmp_227_reg_6572[20] <= 1'b0;
tmp_227_reg_6572[21] <= 1'b0;
tmp_227_reg_6572[22] <= 1'b0;
tmp_227_reg_6572[23] <= 1'b0;
tmp_227_reg_6572[24] <= 1'b0;
tmp_227_reg_6572[25] <= 1'b0;
tmp_227_reg_6572[26] <= 1'b0;
tmp_227_reg_6572[27] <= 1'b0;
tmp_227_reg_6572[28] <= 1'b0;
tmp_227_reg_6572[29] <= 1'b0;
tmp_227_reg_6572[30] <= 1'b0;
tmp_227_reg_6572[31] <= 1'b0;
tmp_227_reg_6572[32] <= 1'b0;
tmp_227_reg_6572[33] <= 1'b0;
tmp_227_reg_6572[34] <= 1'b0;
tmp_227_reg_6572[35] <= 1'b0;
tmp_227_reg_6572[36] <= 1'b0;
tmp_227_reg_6572[37] <= 1'b0;
tmp_227_reg_6572[38] <= 1'b0;
tmp_227_reg_6572[39] <= 1'b0;
tmp_227_reg_6572[40] <= 1'b0;
tmp_227_reg_6572[41] <= 1'b0;
tmp_227_reg_6572[42] <= 1'b0;
tmp_227_reg_6572[43] <= 1'b0;
tmp_227_reg_6572[44] <= 1'b0;
tmp_227_reg_6572[45] <= 1'b0;
tmp_227_reg_6572[46] <= 1'b0;
tmp_227_reg_6572[47] <= 1'b0;
tmp_227_reg_6572[48] <= 1'b0;
tmp_227_reg_6572[49] <= 1'b0;
tmp_227_reg_6572[50] <= 1'b0;
tmp_227_reg_6572[51] <= 1'b0;
tmp_227_reg_6572[52] <= 1'b0;
tmp_227_reg_6572[53] <= 1'b0;
tmp_227_reg_6572[54] <= 1'b0;
tmp_227_reg_6572[55] <= 1'b0;
tmp_227_reg_6572[56] <= 1'b0;
tmp_227_reg_6572[57] <= 1'b0;
tmp_227_reg_6572[58] <= 1'b0;
tmp_227_reg_6572[59] <= 1'b0;
tmp_227_reg_6572[60] <= 1'b0;
tmp_227_reg_6572[61] <= 1'b0;
tmp_227_reg_6572[62] <= 1'b0;
tmp_227_reg_6572[63] <= 1'b0;
end
always @ (ap_clk)
begin
a_addr99_cast_reg_6582[0] <= 1'b0;
a_addr99_cast_reg_6582[1] <= 1'b0;
a_addr99_cast_reg_6582[2] <= 1'b0;
a_addr99_cast_reg_6582[3] <= 1'b0;
a_addr99_cast_reg_6582[4] <= 1'b0;
a_addr99_cast_reg_6582[5] <= 1'b0;
a_addr99_cast_reg_6582[8] <= 1'b1;
a_addr99_cast_reg_6582[13] <= 1'b0;
end
always @ (ap_clk)
begin
tmp_228_reg_6591[0] <= 1'b1;
tmp_228_reg_6591[14] <= 1'b0;
tmp_228_reg_6591[15] <= 1'b0;
tmp_228_reg_6591[16] <= 1'b0;
tmp_228_reg_6591[17] <= 1'b0;
tmp_228_reg_6591[18] <= 1'b0;
tmp_228_reg_6591[19] <= 1'b0;
tmp_228_reg_6591[20] <= 1'b0;
tmp_228_reg_6591[21] <= 1'b0;
tmp_228_reg_6591[22] <= 1'b0;
tmp_228_reg_6591[23] <= 1'b0;
tmp_228_reg_6591[24] <= 1'b0;
tmp_228_reg_6591[25] <= 1'b0;
tmp_228_reg_6591[26] <= 1'b0;
tmp_228_reg_6591[27] <= 1'b0;
tmp_228_reg_6591[28] <= 1'b0;
tmp_228_reg_6591[29] <= 1'b0;
tmp_228_reg_6591[30] <= 1'b0;
tmp_228_reg_6591[31] <= 1'b0;
tmp_228_reg_6591[32] <= 1'b0;
tmp_228_reg_6591[33] <= 1'b0;
tmp_228_reg_6591[34] <= 1'b0;
tmp_228_reg_6591[35] <= 1'b0;
tmp_228_reg_6591[36] <= 1'b0;
tmp_228_reg_6591[37] <= 1'b0;
tmp_228_reg_6591[38] <= 1'b0;
tmp_228_reg_6591[39] <= 1'b0;
tmp_228_reg_6591[40] <= 1'b0;
tmp_228_reg_6591[41] <= 1'b0;
tmp_228_reg_6591[42] <= 1'b0;
tmp_228_reg_6591[43] <= 1'b0;
tmp_228_reg_6591[44] <= 1'b0;
tmp_228_reg_6591[45] <= 1'b0;
tmp_228_reg_6591[46] <= 1'b0;
tmp_228_reg_6591[47] <= 1'b0;
tmp_228_reg_6591[48] <= 1'b0;
tmp_228_reg_6591[49] <= 1'b0;
tmp_228_reg_6591[50] <= 1'b0;
tmp_228_reg_6591[51] <= 1'b0;
tmp_228_reg_6591[52] <= 1'b0;
tmp_228_reg_6591[53] <= 1'b0;
tmp_228_reg_6591[54] <= 1'b0;
tmp_228_reg_6591[55] <= 1'b0;
tmp_228_reg_6591[56] <= 1'b0;
tmp_228_reg_6591[57] <= 1'b0;
tmp_228_reg_6591[58] <= 1'b0;
tmp_228_reg_6591[59] <= 1'b0;
tmp_228_reg_6591[60] <= 1'b0;
tmp_228_reg_6591[61] <= 1'b0;
tmp_228_reg_6591[62] <= 1'b0;
tmp_228_reg_6591[63] <= 1'b0;
end
always @ (ap_clk)
begin
tmp_229_reg_6601[14] <= 1'b0;
tmp_229_reg_6601[15] <= 1'b0;
tmp_229_reg_6601[16] <= 1'b0;
tmp_229_reg_6601[17] <= 1'b0;
tmp_229_reg_6601[18] <= 1'b0;
tmp_229_reg_6601[19] <= 1'b0;
tmp_229_reg_6601[20] <= 1'b0;
tmp_229_reg_6601[21] <= 1'b0;
tmp_229_reg_6601[22] <= 1'b0;
tmp_229_reg_6601[23] <= 1'b0;
tmp_229_reg_6601[24] <= 1'b0;
tmp_229_reg_6601[25] <= 1'b0;
tmp_229_reg_6601[26] <= 1'b0;
tmp_229_reg_6601[27] <= 1'b0;
tmp_229_reg_6601[28] <= 1'b0;
tmp_229_reg_6601[29] <= 1'b0;
tmp_229_reg_6601[30] <= 1'b0;
tmp_229_reg_6601[31] <= 1'b0;
tmp_229_reg_6601[32] <= 1'b0;
tmp_229_reg_6601[33] <= 1'b0;
tmp_229_reg_6601[34] <= 1'b0;
tmp_229_reg_6601[35] <= 1'b0;
tmp_229_reg_6601[36] <= 1'b0;
tmp_229_reg_6601[37] <= 1'b0;
tmp_229_reg_6601[38] <= 1'b0;
tmp_229_reg_6601[39] <= 1'b0;
tmp_229_reg_6601[40] <= 1'b0;
tmp_229_reg_6601[41] <= 1'b0;
tmp_229_reg_6601[42] <= 1'b0;
tmp_229_reg_6601[43] <= 1'b0;
tmp_229_reg_6601[44] <= 1'b0;
tmp_229_reg_6601[45] <= 1'b0;
tmp_229_reg_6601[46] <= 1'b0;
tmp_229_reg_6601[47] <= 1'b0;
tmp_229_reg_6601[48] <= 1'b0;
tmp_229_reg_6601[49] <= 1'b0;
tmp_229_reg_6601[50] <= 1'b0;
tmp_229_reg_6601[51] <= 1'b0;
tmp_229_reg_6601[52] <= 1'b0;
tmp_229_reg_6601[53] <= 1'b0;
tmp_229_reg_6601[54] <= 1'b0;
tmp_229_reg_6601[55] <= 1'b0;
tmp_229_reg_6601[56] <= 1'b0;
tmp_229_reg_6601[57] <= 1'b0;
tmp_229_reg_6601[58] <= 1'b0;
tmp_229_reg_6601[59] <= 1'b0;
tmp_229_reg_6601[60] <= 1'b0;
tmp_229_reg_6601[61] <= 1'b0;
tmp_229_reg_6601[62] <= 1'b0;
tmp_229_reg_6601[63] <= 1'b0;
end
always @ (ap_clk)
begin
tmp_230_reg_6611[0] <= 1'b1;
tmp_230_reg_6611[1] <= 1'b1;
tmp_230_reg_6611[14] <= 1'b0;
tmp_230_reg_6611[15] <= 1'b0;
tmp_230_reg_6611[16] <= 1'b0;
tmp_230_reg_6611[17] <= 1'b0;
tmp_230_reg_6611[18] <= 1'b0;
tmp_230_reg_6611[19] <= 1'b0;
tmp_230_reg_6611[20] <= 1'b0;
tmp_230_reg_6611[21] <= 1'b0;
tmp_230_reg_6611[22] <= 1'b0;
tmp_230_reg_6611[23] <= 1'b0;
tmp_230_reg_6611[24] <= 1'b0;
tmp_230_reg_6611[25] <= 1'b0;
tmp_230_reg_6611[26] <= 1'b0;
tmp_230_reg_6611[27] <= 1'b0;
tmp_230_reg_6611[28] <= 1'b0;
tmp_230_reg_6611[29] <= 1'b0;
tmp_230_reg_6611[30] <= 1'b0;
tmp_230_reg_6611[31] <= 1'b0;
tmp_230_reg_6611[32] <= 1'b0;
tmp_230_reg_6611[33] <= 1'b0;
tmp_230_reg_6611[34] <= 1'b0;
tmp_230_reg_6611[35] <= 1'b0;
tmp_230_reg_6611[36] <= 1'b0;
tmp_230_reg_6611[37] <= 1'b0;
tmp_230_reg_6611[38] <= 1'b0;
tmp_230_reg_6611[39] <= 1'b0;
tmp_230_reg_6611[40] <= 1'b0;
tmp_230_reg_6611[41] <= 1'b0;
tmp_230_reg_6611[42] <= 1'b0;
tmp_230_reg_6611[43] <= 1'b0;
tmp_230_reg_6611[44] <= 1'b0;
tmp_230_reg_6611[45] <= 1'b0;
tmp_230_reg_6611[46] <= 1'b0;
tmp_230_reg_6611[47] <= 1'b0;
tmp_230_reg_6611[48] <= 1'b0;
tmp_230_reg_6611[49] <= 1'b0;
tmp_230_reg_6611[50] <= 1'b0;
tmp_230_reg_6611[51] <= 1'b0;
tmp_230_reg_6611[52] <= 1'b0;
tmp_230_reg_6611[53] <= 1'b0;
tmp_230_reg_6611[54] <= 1'b0;
tmp_230_reg_6611[55] <= 1'b0;
tmp_230_reg_6611[56] <= 1'b0;
tmp_230_reg_6611[57] <= 1'b0;
tmp_230_reg_6611[58] <= 1'b0;
tmp_230_reg_6611[59] <= 1'b0;
tmp_230_reg_6611[60] <= 1'b0;
tmp_230_reg_6611[61] <= 1'b0;
tmp_230_reg_6611[62] <= 1'b0;
tmp_230_reg_6611[63] <= 1'b0;
end
always @ (ap_clk)
begin
tmp_231_reg_6621[14] <= 1'b0;
tmp_231_reg_6621[15] <= 1'b0;
tmp_231_reg_6621[16] <= 1'b0;
tmp_231_reg_6621[17] <= 1'b0;
tmp_231_reg_6621[18] <= 1'b0;
tmp_231_reg_6621[19] <= 1'b0;
tmp_231_reg_6621[20] <= 1'b0;
tmp_231_reg_6621[21] <= 1'b0;
tmp_231_reg_6621[22] <= 1'b0;
tmp_231_reg_6621[23] <= 1'b0;
tmp_231_reg_6621[24] <= 1'b0;
tmp_231_reg_6621[25] <= 1'b0;
tmp_231_reg_6621[26] <= 1'b0;
tmp_231_reg_6621[27] <= 1'b0;
tmp_231_reg_6621[28] <= 1'b0;
tmp_231_reg_6621[29] <= 1'b0;
tmp_231_reg_6621[30] <= 1'b0;
tmp_231_reg_6621[31] <= 1'b0;
tmp_231_reg_6621[32] <= 1'b0;
tmp_231_reg_6621[33] <= 1'b0;
tmp_231_reg_6621[34] <= 1'b0;
tmp_231_reg_6621[35] <= 1'b0;
tmp_231_reg_6621[36] <= 1'b0;
tmp_231_reg_6621[37] <= 1'b0;
tmp_231_reg_6621[38] <= 1'b0;
tmp_231_reg_6621[39] <= 1'b0;
tmp_231_reg_6621[40] <= 1'b0;
tmp_231_reg_6621[41] <= 1'b0;
tmp_231_reg_6621[42] <= 1'b0;
tmp_231_reg_6621[43] <= 1'b0;
tmp_231_reg_6621[44] <= 1'b0;
tmp_231_reg_6621[45] <= 1'b0;
tmp_231_reg_6621[46] <= 1'b0;
tmp_231_reg_6621[47] <= 1'b0;
tmp_231_reg_6621[48] <= 1'b0;
tmp_231_reg_6621[49] <= 1'b0;
tmp_231_reg_6621[50] <= 1'b0;
tmp_231_reg_6621[51] <= 1'b0;
tmp_231_reg_6621[52] <= 1'b0;
tmp_231_reg_6621[53] <= 1'b0;
tmp_231_reg_6621[54] <= 1'b0;
tmp_231_reg_6621[55] <= 1'b0;
tmp_231_reg_6621[56] <= 1'b0;
tmp_231_reg_6621[57] <= 1'b0;
tmp_231_reg_6621[58] <= 1'b0;
tmp_231_reg_6621[59] <= 1'b0;
tmp_231_reg_6621[60] <= 1'b0;
tmp_231_reg_6621[61] <= 1'b0;
tmp_231_reg_6621[62] <= 1'b0;
tmp_231_reg_6621[63] <= 1'b0;
end
always @ (ap_clk)
begin
tmp_232_reg_6631[0] <= 1'b1;
tmp_232_reg_6631[14] <= 1'b0;
tmp_232_reg_6631[15] <= 1'b0;
tmp_232_reg_6631[16] <= 1'b0;
tmp_232_reg_6631[17] <= 1'b0;
tmp_232_reg_6631[18] <= 1'b0;
tmp_232_reg_6631[19] <= 1'b0;
tmp_232_reg_6631[20] <= 1'b0;
tmp_232_reg_6631[21] <= 1'b0;
tmp_232_reg_6631[22] <= 1'b0;
tmp_232_reg_6631[23] <= 1'b0;
tmp_232_reg_6631[24] <= 1'b0;
tmp_232_reg_6631[25] <= 1'b0;
tmp_232_reg_6631[26] <= 1'b0;
tmp_232_reg_6631[27] <= 1'b0;
tmp_232_reg_6631[28] <= 1'b0;
tmp_232_reg_6631[29] <= 1'b0;
tmp_232_reg_6631[30] <= 1'b0;
tmp_232_reg_6631[31] <= 1'b0;
tmp_232_reg_6631[32] <= 1'b0;
tmp_232_reg_6631[33] <= 1'b0;
tmp_232_reg_6631[34] <= 1'b0;
tmp_232_reg_6631[35] <= 1'b0;
tmp_232_reg_6631[36] <= 1'b0;
tmp_232_reg_6631[37] <= 1'b0;
tmp_232_reg_6631[38] <= 1'b0;
tmp_232_reg_6631[39] <= 1'b0;
tmp_232_reg_6631[40] <= 1'b0;
tmp_232_reg_6631[41] <= 1'b0;
tmp_232_reg_6631[42] <= 1'b0;
tmp_232_reg_6631[43] <= 1'b0;
tmp_232_reg_6631[44] <= 1'b0;
tmp_232_reg_6631[45] <= 1'b0;
tmp_232_reg_6631[46] <= 1'b0;
tmp_232_reg_6631[47] <= 1'b0;
tmp_232_reg_6631[48] <= 1'b0;
tmp_232_reg_6631[49] <= 1'b0;
tmp_232_reg_6631[50] <= 1'b0;
tmp_232_reg_6631[51] <= 1'b0;
tmp_232_reg_6631[52] <= 1'b0;
tmp_232_reg_6631[53] <= 1'b0;
tmp_232_reg_6631[54] <= 1'b0;
tmp_232_reg_6631[55] <= 1'b0;
tmp_232_reg_6631[56] <= 1'b0;
tmp_232_reg_6631[57] <= 1'b0;
tmp_232_reg_6631[58] <= 1'b0;
tmp_232_reg_6631[59] <= 1'b0;
tmp_232_reg_6631[60] <= 1'b0;
tmp_232_reg_6631[61] <= 1'b0;
tmp_232_reg_6631[62] <= 1'b0;
tmp_232_reg_6631[63] <= 1'b0;
end
always @ (ap_clk)
begin
tmp_233_reg_6641[14] <= 1'b0;
tmp_233_reg_6641[15] <= 1'b0;
tmp_233_reg_6641[16] <= 1'b0;
tmp_233_reg_6641[17] <= 1'b0;
tmp_233_reg_6641[18] <= 1'b0;
tmp_233_reg_6641[19] <= 1'b0;
tmp_233_reg_6641[20] <= 1'b0;
tmp_233_reg_6641[21] <= 1'b0;
tmp_233_reg_6641[22] <= 1'b0;
tmp_233_reg_6641[23] <= 1'b0;
tmp_233_reg_6641[24] <= 1'b0;
tmp_233_reg_6641[25] <= 1'b0;
tmp_233_reg_6641[26] <= 1'b0;
tmp_233_reg_6641[27] <= 1'b0;
tmp_233_reg_6641[28] <= 1'b0;
tmp_233_reg_6641[29] <= 1'b0;
tmp_233_reg_6641[30] <= 1'b0;
tmp_233_reg_6641[31] <= 1'b0;
tmp_233_reg_6641[32] <= 1'b0;
tmp_233_reg_6641[33] <= 1'b0;
tmp_233_reg_6641[34] <= 1'b0;
tmp_233_reg_6641[35] <= 1'b0;
tmp_233_reg_6641[36] <= 1'b0;
tmp_233_reg_6641[37] <= 1'b0;
tmp_233_reg_6641[38] <= 1'b0;
tmp_233_reg_6641[39] <= 1'b0;
tmp_233_reg_6641[40] <= 1'b0;
tmp_233_reg_6641[41] <= 1'b0;
tmp_233_reg_6641[42] <= 1'b0;
tmp_233_reg_6641[43] <= 1'b0;
tmp_233_reg_6641[44] <= 1'b0;
tmp_233_reg_6641[45] <= 1'b0;
tmp_233_reg_6641[46] <= 1'b0;
tmp_233_reg_6641[47] <= 1'b0;
tmp_233_reg_6641[48] <= 1'b0;
tmp_233_reg_6641[49] <= 1'b0;
tmp_233_reg_6641[50] <= 1'b0;
tmp_233_reg_6641[51] <= 1'b0;
tmp_233_reg_6641[52] <= 1'b0;
tmp_233_reg_6641[53] <= 1'b0;
tmp_233_reg_6641[54] <= 1'b0;
tmp_233_reg_6641[55] <= 1'b0;
tmp_233_reg_6641[56] <= 1'b0;
tmp_233_reg_6641[57] <= 1'b0;
tmp_233_reg_6641[58] <= 1'b0;
tmp_233_reg_6641[59] <= 1'b0;
tmp_233_reg_6641[60] <= 1'b0;
tmp_233_reg_6641[61] <= 1'b0;
tmp_233_reg_6641[62] <= 1'b0;
tmp_233_reg_6641[63] <= 1'b0;
end
always @ (ap_clk)
begin
tmp_234_reg_6651[0] <= 1'b1;
tmp_234_reg_6651[1] <= 1'b1;
tmp_234_reg_6651[2] <= 1'b1;
tmp_234_reg_6651[14] <= 1'b0;
tmp_234_reg_6651[15] <= 1'b0;
tmp_234_reg_6651[16] <= 1'b0;
tmp_234_reg_6651[17] <= 1'b0;
tmp_234_reg_6651[18] <= 1'b0;
tmp_234_reg_6651[19] <= 1'b0;
tmp_234_reg_6651[20] <= 1'b0;
tmp_234_reg_6651[21] <= 1'b0;
tmp_234_reg_6651[22] <= 1'b0;
tmp_234_reg_6651[23] <= 1'b0;
tmp_234_reg_6651[24] <= 1'b0;
tmp_234_reg_6651[25] <= 1'b0;
tmp_234_reg_6651[26] <= 1'b0;
tmp_234_reg_6651[27] <= 1'b0;
tmp_234_reg_6651[28] <= 1'b0;
tmp_234_reg_6651[29] <= 1'b0;
tmp_234_reg_6651[30] <= 1'b0;
tmp_234_reg_6651[31] <= 1'b0;
tmp_234_reg_6651[32] <= 1'b0;
tmp_234_reg_6651[33] <= 1'b0;
tmp_234_reg_6651[34] <= 1'b0;
tmp_234_reg_6651[35] <= 1'b0;
tmp_234_reg_6651[36] <= 1'b0;
tmp_234_reg_6651[37] <= 1'b0;
tmp_234_reg_6651[38] <= 1'b0;
tmp_234_reg_6651[39] <= 1'b0;
tmp_234_reg_6651[40] <= 1'b0;
tmp_234_reg_6651[41] <= 1'b0;
tmp_234_reg_6651[42] <= 1'b0;
tmp_234_reg_6651[43] <= 1'b0;
tmp_234_reg_6651[44] <= 1'b0;
tmp_234_reg_6651[45] <= 1'b0;
tmp_234_reg_6651[46] <= 1'b0;
tmp_234_reg_6651[47] <= 1'b0;
tmp_234_reg_6651[48] <= 1'b0;
tmp_234_reg_6651[49] <= 1'b0;
tmp_234_reg_6651[50] <= 1'b0;
tmp_234_reg_6651[51] <= 1'b0;
tmp_234_reg_6651[52] <= 1'b0;
tmp_234_reg_6651[53] <= 1'b0;
tmp_234_reg_6651[54] <= 1'b0;
tmp_234_reg_6651[55] <= 1'b0;
tmp_234_reg_6651[56] <= 1'b0;
tmp_234_reg_6651[57] <= 1'b0;
tmp_234_reg_6651[58] <= 1'b0;
tmp_234_reg_6651[59] <= 1'b0;
tmp_234_reg_6651[60] <= 1'b0;
tmp_234_reg_6651[61] <= 1'b0;
tmp_234_reg_6651[62] <= 1'b0;
tmp_234_reg_6651[63] <= 1'b0;
end
always @ (ap_clk)
begin
a_addr72_cast_reg_6661[0] <= 1'b0;
a_addr72_cast_reg_6661[1] <= 1'b0;
a_addr72_cast_reg_6661[2] <= 1'b0;
a_addr72_cast_reg_6661[3] <= 1'b0;
a_addr72_cast_reg_6661[4] <= 1'b0;
a_addr72_cast_reg_6661[5] <= 1'b0;
a_addr72_cast_reg_6661[6] <= 1'b1;
a_addr72_cast_reg_6661[8] <= 1'b1;
a_addr72_cast_reg_6661[13] <= 1'b0;
end
always @ (ap_clk)
begin
tmp_235_reg_6671[0] <= 1'b1;
tmp_235_reg_6671[14] <= 1'b0;
tmp_235_reg_6671[15] <= 1'b0;
tmp_235_reg_6671[16] <= 1'b0;
tmp_235_reg_6671[17] <= 1'b0;
tmp_235_reg_6671[18] <= 1'b0;
tmp_235_reg_6671[19] <= 1'b0;
tmp_235_reg_6671[20] <= 1'b0;
tmp_235_reg_6671[21] <= 1'b0;
tmp_235_reg_6671[22] <= 1'b0;
tmp_235_reg_6671[23] <= 1'b0;
tmp_235_reg_6671[24] <= 1'b0;
tmp_235_reg_6671[25] <= 1'b0;
tmp_235_reg_6671[26] <= 1'b0;
tmp_235_reg_6671[27] <= 1'b0;
tmp_235_reg_6671[28] <= 1'b0;
tmp_235_reg_6671[29] <= 1'b0;
tmp_235_reg_6671[30] <= 1'b0;
tmp_235_reg_6671[31] <= 1'b0;
tmp_235_reg_6671[32] <= 1'b0;
tmp_235_reg_6671[33] <= 1'b0;
tmp_235_reg_6671[34] <= 1'b0;
tmp_235_reg_6671[35] <= 1'b0;
tmp_235_reg_6671[36] <= 1'b0;
tmp_235_reg_6671[37] <= 1'b0;
tmp_235_reg_6671[38] <= 1'b0;
tmp_235_reg_6671[39] <= 1'b0;
tmp_235_reg_6671[40] <= 1'b0;
tmp_235_reg_6671[41] <= 1'b0;
tmp_235_reg_6671[42] <= 1'b0;
tmp_235_reg_6671[43] <= 1'b0;
tmp_235_reg_6671[44] <= 1'b0;
tmp_235_reg_6671[45] <= 1'b0;
tmp_235_reg_6671[46] <= 1'b0;
tmp_235_reg_6671[47] <= 1'b0;
tmp_235_reg_6671[48] <= 1'b0;
tmp_235_reg_6671[49] <= 1'b0;
tmp_235_reg_6671[50] <= 1'b0;
tmp_235_reg_6671[51] <= 1'b0;
tmp_235_reg_6671[52] <= 1'b0;
tmp_235_reg_6671[53] <= 1'b0;
tmp_235_reg_6671[54] <= 1'b0;
tmp_235_reg_6671[55] <= 1'b0;
tmp_235_reg_6671[56] <= 1'b0;
tmp_235_reg_6671[57] <= 1'b0;
tmp_235_reg_6671[58] <= 1'b0;
tmp_235_reg_6671[59] <= 1'b0;
tmp_235_reg_6671[60] <= 1'b0;
tmp_235_reg_6671[61] <= 1'b0;
tmp_235_reg_6671[62] <= 1'b0;
tmp_235_reg_6671[63] <= 1'b0;
end
always @ (ap_clk)
begin
tmp_236_reg_6681[14] <= 1'b0;
tmp_236_reg_6681[15] <= 1'b0;
tmp_236_reg_6681[16] <= 1'b0;
tmp_236_reg_6681[17] <= 1'b0;
tmp_236_reg_6681[18] <= 1'b0;
tmp_236_reg_6681[19] <= 1'b0;
tmp_236_reg_6681[20] <= 1'b0;
tmp_236_reg_6681[21] <= 1'b0;
tmp_236_reg_6681[22] <= 1'b0;
tmp_236_reg_6681[23] <= 1'b0;
tmp_236_reg_6681[24] <= 1'b0;
tmp_236_reg_6681[25] <= 1'b0;
tmp_236_reg_6681[26] <= 1'b0;
tmp_236_reg_6681[27] <= 1'b0;
tmp_236_reg_6681[28] <= 1'b0;
tmp_236_reg_6681[29] <= 1'b0;
tmp_236_reg_6681[30] <= 1'b0;
tmp_236_reg_6681[31] <= 1'b0;
tmp_236_reg_6681[32] <= 1'b0;
tmp_236_reg_6681[33] <= 1'b0;
tmp_236_reg_6681[34] <= 1'b0;
tmp_236_reg_6681[35] <= 1'b0;
tmp_236_reg_6681[36] <= 1'b0;
tmp_236_reg_6681[37] <= 1'b0;
tmp_236_reg_6681[38] <= 1'b0;
tmp_236_reg_6681[39] <= 1'b0;
tmp_236_reg_6681[40] <= 1'b0;
tmp_236_reg_6681[41] <= 1'b0;
tmp_236_reg_6681[42] <= 1'b0;
tmp_236_reg_6681[43] <= 1'b0;
tmp_236_reg_6681[44] <= 1'b0;
tmp_236_reg_6681[45] <= 1'b0;
tmp_236_reg_6681[46] <= 1'b0;
tmp_236_reg_6681[47] <= 1'b0;
tmp_236_reg_6681[48] <= 1'b0;
tmp_236_reg_6681[49] <= 1'b0;
tmp_236_reg_6681[50] <= 1'b0;
tmp_236_reg_6681[51] <= 1'b0;
tmp_236_reg_6681[52] <= 1'b0;
tmp_236_reg_6681[53] <= 1'b0;
tmp_236_reg_6681[54] <= 1'b0;
tmp_236_reg_6681[55] <= 1'b0;
tmp_236_reg_6681[56] <= 1'b0;
tmp_236_reg_6681[57] <= 1'b0;
tmp_236_reg_6681[58] <= 1'b0;
tmp_236_reg_6681[59] <= 1'b0;
tmp_236_reg_6681[60] <= 1'b0;
tmp_236_reg_6681[61] <= 1'b0;
tmp_236_reg_6681[62] <= 1'b0;
tmp_236_reg_6681[63] <= 1'b0;
end
always @ (ap_clk)
begin
tmp_237_reg_6691[0] <= 1'b1;
tmp_237_reg_6691[1] <= 1'b1;
tmp_237_reg_6691[14] <= 1'b0;
tmp_237_reg_6691[15] <= 1'b0;
tmp_237_reg_6691[16] <= 1'b0;
tmp_237_reg_6691[17] <= 1'b0;
tmp_237_reg_6691[18] <= 1'b0;
tmp_237_reg_6691[19] <= 1'b0;
tmp_237_reg_6691[20] <= 1'b0;
tmp_237_reg_6691[21] <= 1'b0;
tmp_237_reg_6691[22] <= 1'b0;
tmp_237_reg_6691[23] <= 1'b0;
tmp_237_reg_6691[24] <= 1'b0;
tmp_237_reg_6691[25] <= 1'b0;
tmp_237_reg_6691[26] <= 1'b0;
tmp_237_reg_6691[27] <= 1'b0;
tmp_237_reg_6691[28] <= 1'b0;
tmp_237_reg_6691[29] <= 1'b0;
tmp_237_reg_6691[30] <= 1'b0;
tmp_237_reg_6691[31] <= 1'b0;
tmp_237_reg_6691[32] <= 1'b0;
tmp_237_reg_6691[33] <= 1'b0;
tmp_237_reg_6691[34] <= 1'b0;
tmp_237_reg_6691[35] <= 1'b0;
tmp_237_reg_6691[36] <= 1'b0;
tmp_237_reg_6691[37] <= 1'b0;
tmp_237_reg_6691[38] <= 1'b0;
tmp_237_reg_6691[39] <= 1'b0;
tmp_237_reg_6691[40] <= 1'b0;
tmp_237_reg_6691[41] <= 1'b0;
tmp_237_reg_6691[42] <= 1'b0;
tmp_237_reg_6691[43] <= 1'b0;
tmp_237_reg_6691[44] <= 1'b0;
tmp_237_reg_6691[45] <= 1'b0;
tmp_237_reg_6691[46] <= 1'b0;
tmp_237_reg_6691[47] <= 1'b0;
tmp_237_reg_6691[48] <= 1'b0;
tmp_237_reg_6691[49] <= 1'b0;
tmp_237_reg_6691[50] <= 1'b0;
tmp_237_reg_6691[51] <= 1'b0;
tmp_237_reg_6691[52] <= 1'b0;
tmp_237_reg_6691[53] <= 1'b0;
tmp_237_reg_6691[54] <= 1'b0;
tmp_237_reg_6691[55] <= 1'b0;
tmp_237_reg_6691[56] <= 1'b0;
tmp_237_reg_6691[57] <= 1'b0;
tmp_237_reg_6691[58] <= 1'b0;
tmp_237_reg_6691[59] <= 1'b0;
tmp_237_reg_6691[60] <= 1'b0;
tmp_237_reg_6691[61] <= 1'b0;
tmp_237_reg_6691[62] <= 1'b0;
tmp_237_reg_6691[63] <= 1'b0;
end
always @ (ap_clk)
begin
tmp_238_reg_6701[14] <= 1'b0;
tmp_238_reg_6701[15] <= 1'b0;
tmp_238_reg_6701[16] <= 1'b0;
tmp_238_reg_6701[17] <= 1'b0;
tmp_238_reg_6701[18] <= 1'b0;
tmp_238_reg_6701[19] <= 1'b0;
tmp_238_reg_6701[20] <= 1'b0;
tmp_238_reg_6701[21] <= 1'b0;
tmp_238_reg_6701[22] <= 1'b0;
tmp_238_reg_6701[23] <= 1'b0;
tmp_238_reg_6701[24] <= 1'b0;
tmp_238_reg_6701[25] <= 1'b0;
tmp_238_reg_6701[26] <= 1'b0;
tmp_238_reg_6701[27] <= 1'b0;
tmp_238_reg_6701[28] <= 1'b0;
tmp_238_reg_6701[29] <= 1'b0;
tmp_238_reg_6701[30] <= 1'b0;
tmp_238_reg_6701[31] <= 1'b0;
tmp_238_reg_6701[32] <= 1'b0;
tmp_238_reg_6701[33] <= 1'b0;
tmp_238_reg_6701[34] <= 1'b0;
tmp_238_reg_6701[35] <= 1'b0;
tmp_238_reg_6701[36] <= 1'b0;
tmp_238_reg_6701[37] <= 1'b0;
tmp_238_reg_6701[38] <= 1'b0;
tmp_238_reg_6701[39] <= 1'b0;
tmp_238_reg_6701[40] <= 1'b0;
tmp_238_reg_6701[41] <= 1'b0;
tmp_238_reg_6701[42] <= 1'b0;
tmp_238_reg_6701[43] <= 1'b0;
tmp_238_reg_6701[44] <= 1'b0;
tmp_238_reg_6701[45] <= 1'b0;
tmp_238_reg_6701[46] <= 1'b0;
tmp_238_reg_6701[47] <= 1'b0;
tmp_238_reg_6701[48] <= 1'b0;
tmp_238_reg_6701[49] <= 1'b0;
tmp_238_reg_6701[50] <= 1'b0;
tmp_238_reg_6701[51] <= 1'b0;
tmp_238_reg_6701[52] <= 1'b0;
tmp_238_reg_6701[53] <= 1'b0;
tmp_238_reg_6701[54] <= 1'b0;
tmp_238_reg_6701[55] <= 1'b0;
tmp_238_reg_6701[56] <= 1'b0;
tmp_238_reg_6701[57] <= 1'b0;
tmp_238_reg_6701[58] <= 1'b0;
tmp_238_reg_6701[59] <= 1'b0;
tmp_238_reg_6701[60] <= 1'b0;
tmp_238_reg_6701[61] <= 1'b0;
tmp_238_reg_6701[62] <= 1'b0;
tmp_238_reg_6701[63] <= 1'b0;
end
always @ (ap_clk)
begin
tmp_239_reg_6711[0] <= 1'b1;
tmp_239_reg_6711[14] <= 1'b0;
tmp_239_reg_6711[15] <= 1'b0;
tmp_239_reg_6711[16] <= 1'b0;
tmp_239_reg_6711[17] <= 1'b0;
tmp_239_reg_6711[18] <= 1'b0;
tmp_239_reg_6711[19] <= 1'b0;
tmp_239_reg_6711[20] <= 1'b0;
tmp_239_reg_6711[21] <= 1'b0;
tmp_239_reg_6711[22] <= 1'b0;
tmp_239_reg_6711[23] <= 1'b0;
tmp_239_reg_6711[24] <= 1'b0;
tmp_239_reg_6711[25] <= 1'b0;
tmp_239_reg_6711[26] <= 1'b0;
tmp_239_reg_6711[27] <= 1'b0;
tmp_239_reg_6711[28] <= 1'b0;
tmp_239_reg_6711[29] <= 1'b0;
tmp_239_reg_6711[30] <= 1'b0;
tmp_239_reg_6711[31] <= 1'b0;
tmp_239_reg_6711[32] <= 1'b0;
tmp_239_reg_6711[33] <= 1'b0;
tmp_239_reg_6711[34] <= 1'b0;
tmp_239_reg_6711[35] <= 1'b0;
tmp_239_reg_6711[36] <= 1'b0;
tmp_239_reg_6711[37] <= 1'b0;
tmp_239_reg_6711[38] <= 1'b0;
tmp_239_reg_6711[39] <= 1'b0;
tmp_239_reg_6711[40] <= 1'b0;
tmp_239_reg_6711[41] <= 1'b0;
tmp_239_reg_6711[42] <= 1'b0;
tmp_239_reg_6711[43] <= 1'b0;
tmp_239_reg_6711[44] <= 1'b0;
tmp_239_reg_6711[45] <= 1'b0;
tmp_239_reg_6711[46] <= 1'b0;
tmp_239_reg_6711[47] <= 1'b0;
tmp_239_reg_6711[48] <= 1'b0;
tmp_239_reg_6711[49] <= 1'b0;
tmp_239_reg_6711[50] <= 1'b0;
tmp_239_reg_6711[51] <= 1'b0;
tmp_239_reg_6711[52] <= 1'b0;
tmp_239_reg_6711[53] <= 1'b0;
tmp_239_reg_6711[54] <= 1'b0;
tmp_239_reg_6711[55] <= 1'b0;
tmp_239_reg_6711[56] <= 1'b0;
tmp_239_reg_6711[57] <= 1'b0;
tmp_239_reg_6711[58] <= 1'b0;
tmp_239_reg_6711[59] <= 1'b0;
tmp_239_reg_6711[60] <= 1'b0;
tmp_239_reg_6711[61] <= 1'b0;
tmp_239_reg_6711[62] <= 1'b0;
tmp_239_reg_6711[63] <= 1'b0;
end
always @ (ap_clk)
begin
tmp_240_reg_6721[14] <= 1'b0;
tmp_240_reg_6721[15] <= 1'b0;
tmp_240_reg_6721[16] <= 1'b0;
tmp_240_reg_6721[17] <= 1'b0;
tmp_240_reg_6721[18] <= 1'b0;
tmp_240_reg_6721[19] <= 1'b0;
tmp_240_reg_6721[20] <= 1'b0;
tmp_240_reg_6721[21] <= 1'b0;
tmp_240_reg_6721[22] <= 1'b0;
tmp_240_reg_6721[23] <= 1'b0;
tmp_240_reg_6721[24] <= 1'b0;
tmp_240_reg_6721[25] <= 1'b0;
tmp_240_reg_6721[26] <= 1'b0;
tmp_240_reg_6721[27] <= 1'b0;
tmp_240_reg_6721[28] <= 1'b0;
tmp_240_reg_6721[29] <= 1'b0;
tmp_240_reg_6721[30] <= 1'b0;
tmp_240_reg_6721[31] <= 1'b0;
tmp_240_reg_6721[32] <= 1'b0;
tmp_240_reg_6721[33] <= 1'b0;
tmp_240_reg_6721[34] <= 1'b0;
tmp_240_reg_6721[35] <= 1'b0;
tmp_240_reg_6721[36] <= 1'b0;
tmp_240_reg_6721[37] <= 1'b0;
tmp_240_reg_6721[38] <= 1'b0;
tmp_240_reg_6721[39] <= 1'b0;
tmp_240_reg_6721[40] <= 1'b0;
tmp_240_reg_6721[41] <= 1'b0;
tmp_240_reg_6721[42] <= 1'b0;
tmp_240_reg_6721[43] <= 1'b0;
tmp_240_reg_6721[44] <= 1'b0;
tmp_240_reg_6721[45] <= 1'b0;
tmp_240_reg_6721[46] <= 1'b0;
tmp_240_reg_6721[47] <= 1'b0;
tmp_240_reg_6721[48] <= 1'b0;
tmp_240_reg_6721[49] <= 1'b0;
tmp_240_reg_6721[50] <= 1'b0;
tmp_240_reg_6721[51] <= 1'b0;
tmp_240_reg_6721[52] <= 1'b0;
tmp_240_reg_6721[53] <= 1'b0;
tmp_240_reg_6721[54] <= 1'b0;
tmp_240_reg_6721[55] <= 1'b0;
tmp_240_reg_6721[56] <= 1'b0;
tmp_240_reg_6721[57] <= 1'b0;
tmp_240_reg_6721[58] <= 1'b0;
tmp_240_reg_6721[59] <= 1'b0;
tmp_240_reg_6721[60] <= 1'b0;
tmp_240_reg_6721[61] <= 1'b0;
tmp_240_reg_6721[62] <= 1'b0;
tmp_240_reg_6721[63] <= 1'b0;
end
always @ (ap_clk)
begin
tmp_241_reg_6731[0] <= 1'b1;
tmp_241_reg_6731[1] <= 1'b1;
tmp_241_reg_6731[2] <= 1'b1;
tmp_241_reg_6731[14] <= 1'b0;
tmp_241_reg_6731[15] <= 1'b0;
tmp_241_reg_6731[16] <= 1'b0;
tmp_241_reg_6731[17] <= 1'b0;
tmp_241_reg_6731[18] <= 1'b0;
tmp_241_reg_6731[19] <= 1'b0;
tmp_241_reg_6731[20] <= 1'b0;
tmp_241_reg_6731[21] <= 1'b0;
tmp_241_reg_6731[22] <= 1'b0;
tmp_241_reg_6731[23] <= 1'b0;
tmp_241_reg_6731[24] <= 1'b0;
tmp_241_reg_6731[25] <= 1'b0;
tmp_241_reg_6731[26] <= 1'b0;
tmp_241_reg_6731[27] <= 1'b0;
tmp_241_reg_6731[28] <= 1'b0;
tmp_241_reg_6731[29] <= 1'b0;
tmp_241_reg_6731[30] <= 1'b0;
tmp_241_reg_6731[31] <= 1'b0;
tmp_241_reg_6731[32] <= 1'b0;
tmp_241_reg_6731[33] <= 1'b0;
tmp_241_reg_6731[34] <= 1'b0;
tmp_241_reg_6731[35] <= 1'b0;
tmp_241_reg_6731[36] <= 1'b0;
tmp_241_reg_6731[37] <= 1'b0;
tmp_241_reg_6731[38] <= 1'b0;
tmp_241_reg_6731[39] <= 1'b0;
tmp_241_reg_6731[40] <= 1'b0;
tmp_241_reg_6731[41] <= 1'b0;
tmp_241_reg_6731[42] <= 1'b0;
tmp_241_reg_6731[43] <= 1'b0;
tmp_241_reg_6731[44] <= 1'b0;
tmp_241_reg_6731[45] <= 1'b0;
tmp_241_reg_6731[46] <= 1'b0;
tmp_241_reg_6731[47] <= 1'b0;
tmp_241_reg_6731[48] <= 1'b0;
tmp_241_reg_6731[49] <= 1'b0;
tmp_241_reg_6731[50] <= 1'b0;
tmp_241_reg_6731[51] <= 1'b0;
tmp_241_reg_6731[52] <= 1'b0;
tmp_241_reg_6731[53] <= 1'b0;
tmp_241_reg_6731[54] <= 1'b0;
tmp_241_reg_6731[55] <= 1'b0;
tmp_241_reg_6731[56] <= 1'b0;
tmp_241_reg_6731[57] <= 1'b0;
tmp_241_reg_6731[58] <= 1'b0;
tmp_241_reg_6731[59] <= 1'b0;
tmp_241_reg_6731[60] <= 1'b0;
tmp_241_reg_6731[61] <= 1'b0;
tmp_241_reg_6731[62] <= 1'b0;
tmp_241_reg_6731[63] <= 1'b0;
end
always @ (ap_clk)
begin
a_addr45_cast_reg_6741[0] <= 1'b0;
a_addr45_cast_reg_6741[1] <= 1'b0;
a_addr45_cast_reg_6741[2] <= 1'b0;
a_addr45_cast_reg_6741[3] <= 1'b0;
a_addr45_cast_reg_6741[4] <= 1'b0;
a_addr45_cast_reg_6741[5] <= 1'b0;
a_addr45_cast_reg_6741[7] <= 1'b1;
a_addr45_cast_reg_6741[8] <= 1'b1;
a_addr45_cast_reg_6741[13] <= 1'b0;
end
always @ (ap_clk)
begin
tmp_242_reg_6750[0] <= 1'b1;
tmp_242_reg_6750[14] <= 1'b0;
tmp_242_reg_6750[15] <= 1'b0;
tmp_242_reg_6750[16] <= 1'b0;
tmp_242_reg_6750[17] <= 1'b0;
tmp_242_reg_6750[18] <= 1'b0;
tmp_242_reg_6750[19] <= 1'b0;
tmp_242_reg_6750[20] <= 1'b0;
tmp_242_reg_6750[21] <= 1'b0;
tmp_242_reg_6750[22] <= 1'b0;
tmp_242_reg_6750[23] <= 1'b0;
tmp_242_reg_6750[24] <= 1'b0;
tmp_242_reg_6750[25] <= 1'b0;
tmp_242_reg_6750[26] <= 1'b0;
tmp_242_reg_6750[27] <= 1'b0;
tmp_242_reg_6750[28] <= 1'b0;
tmp_242_reg_6750[29] <= 1'b0;
tmp_242_reg_6750[30] <= 1'b0;
tmp_242_reg_6750[31] <= 1'b0;
tmp_242_reg_6750[32] <= 1'b0;
tmp_242_reg_6750[33] <= 1'b0;
tmp_242_reg_6750[34] <= 1'b0;
tmp_242_reg_6750[35] <= 1'b0;
tmp_242_reg_6750[36] <= 1'b0;
tmp_242_reg_6750[37] <= 1'b0;
tmp_242_reg_6750[38] <= 1'b0;
tmp_242_reg_6750[39] <= 1'b0;
tmp_242_reg_6750[40] <= 1'b0;
tmp_242_reg_6750[41] <= 1'b0;
tmp_242_reg_6750[42] <= 1'b0;
tmp_242_reg_6750[43] <= 1'b0;
tmp_242_reg_6750[44] <= 1'b0;
tmp_242_reg_6750[45] <= 1'b0;
tmp_242_reg_6750[46] <= 1'b0;
tmp_242_reg_6750[47] <= 1'b0;
tmp_242_reg_6750[48] <= 1'b0;
tmp_242_reg_6750[49] <= 1'b0;
tmp_242_reg_6750[50] <= 1'b0;
tmp_242_reg_6750[51] <= 1'b0;
tmp_242_reg_6750[52] <= 1'b0;
tmp_242_reg_6750[53] <= 1'b0;
tmp_242_reg_6750[54] <= 1'b0;
tmp_242_reg_6750[55] <= 1'b0;
tmp_242_reg_6750[56] <= 1'b0;
tmp_242_reg_6750[57] <= 1'b0;
tmp_242_reg_6750[58] <= 1'b0;
tmp_242_reg_6750[59] <= 1'b0;
tmp_242_reg_6750[60] <= 1'b0;
tmp_242_reg_6750[61] <= 1'b0;
tmp_242_reg_6750[62] <= 1'b0;
tmp_242_reg_6750[63] <= 1'b0;
end
always @ (ap_clk)
begin
tmp_243_reg_6760[14] <= 1'b0;
tmp_243_reg_6760[15] <= 1'b0;
tmp_243_reg_6760[16] <= 1'b0;
tmp_243_reg_6760[17] <= 1'b0;
tmp_243_reg_6760[18] <= 1'b0;
tmp_243_reg_6760[19] <= 1'b0;
tmp_243_reg_6760[20] <= 1'b0;
tmp_243_reg_6760[21] <= 1'b0;
tmp_243_reg_6760[22] <= 1'b0;
tmp_243_reg_6760[23] <= 1'b0;
tmp_243_reg_6760[24] <= 1'b0;
tmp_243_reg_6760[25] <= 1'b0;
tmp_243_reg_6760[26] <= 1'b0;
tmp_243_reg_6760[27] <= 1'b0;
tmp_243_reg_6760[28] <= 1'b0;
tmp_243_reg_6760[29] <= 1'b0;
tmp_243_reg_6760[30] <= 1'b0;
tmp_243_reg_6760[31] <= 1'b0;
tmp_243_reg_6760[32] <= 1'b0;
tmp_243_reg_6760[33] <= 1'b0;
tmp_243_reg_6760[34] <= 1'b0;
tmp_243_reg_6760[35] <= 1'b0;
tmp_243_reg_6760[36] <= 1'b0;
tmp_243_reg_6760[37] <= 1'b0;
tmp_243_reg_6760[38] <= 1'b0;
tmp_243_reg_6760[39] <= 1'b0;
tmp_243_reg_6760[40] <= 1'b0;
tmp_243_reg_6760[41] <= 1'b0;
tmp_243_reg_6760[42] <= 1'b0;
tmp_243_reg_6760[43] <= 1'b0;
tmp_243_reg_6760[44] <= 1'b0;
tmp_243_reg_6760[45] <= 1'b0;
tmp_243_reg_6760[46] <= 1'b0;
tmp_243_reg_6760[47] <= 1'b0;
tmp_243_reg_6760[48] <= 1'b0;
tmp_243_reg_6760[49] <= 1'b0;
tmp_243_reg_6760[50] <= 1'b0;
tmp_243_reg_6760[51] <= 1'b0;
tmp_243_reg_6760[52] <= 1'b0;
tmp_243_reg_6760[53] <= 1'b0;
tmp_243_reg_6760[54] <= 1'b0;
tmp_243_reg_6760[55] <= 1'b0;
tmp_243_reg_6760[56] <= 1'b0;
tmp_243_reg_6760[57] <= 1'b0;
tmp_243_reg_6760[58] <= 1'b0;
tmp_243_reg_6760[59] <= 1'b0;
tmp_243_reg_6760[60] <= 1'b0;
tmp_243_reg_6760[61] <= 1'b0;
tmp_243_reg_6760[62] <= 1'b0;
tmp_243_reg_6760[63] <= 1'b0;
end
always @ (ap_clk)
begin
tmp_244_reg_6770[0] <= 1'b1;
tmp_244_reg_6770[1] <= 1'b1;
tmp_244_reg_6770[14] <= 1'b0;
tmp_244_reg_6770[15] <= 1'b0;
tmp_244_reg_6770[16] <= 1'b0;
tmp_244_reg_6770[17] <= 1'b0;
tmp_244_reg_6770[18] <= 1'b0;
tmp_244_reg_6770[19] <= 1'b0;
tmp_244_reg_6770[20] <= 1'b0;
tmp_244_reg_6770[21] <= 1'b0;
tmp_244_reg_6770[22] <= 1'b0;
tmp_244_reg_6770[23] <= 1'b0;
tmp_244_reg_6770[24] <= 1'b0;
tmp_244_reg_6770[25] <= 1'b0;
tmp_244_reg_6770[26] <= 1'b0;
tmp_244_reg_6770[27] <= 1'b0;
tmp_244_reg_6770[28] <= 1'b0;
tmp_244_reg_6770[29] <= 1'b0;
tmp_244_reg_6770[30] <= 1'b0;
tmp_244_reg_6770[31] <= 1'b0;
tmp_244_reg_6770[32] <= 1'b0;
tmp_244_reg_6770[33] <= 1'b0;
tmp_244_reg_6770[34] <= 1'b0;
tmp_244_reg_6770[35] <= 1'b0;
tmp_244_reg_6770[36] <= 1'b0;
tmp_244_reg_6770[37] <= 1'b0;
tmp_244_reg_6770[38] <= 1'b0;
tmp_244_reg_6770[39] <= 1'b0;
tmp_244_reg_6770[40] <= 1'b0;
tmp_244_reg_6770[41] <= 1'b0;
tmp_244_reg_6770[42] <= 1'b0;
tmp_244_reg_6770[43] <= 1'b0;
tmp_244_reg_6770[44] <= 1'b0;
tmp_244_reg_6770[45] <= 1'b0;
tmp_244_reg_6770[46] <= 1'b0;
tmp_244_reg_6770[47] <= 1'b0;
tmp_244_reg_6770[48] <= 1'b0;
tmp_244_reg_6770[49] <= 1'b0;
tmp_244_reg_6770[50] <= 1'b0;
tmp_244_reg_6770[51] <= 1'b0;
tmp_244_reg_6770[52] <= 1'b0;
tmp_244_reg_6770[53] <= 1'b0;
tmp_244_reg_6770[54] <= 1'b0;
tmp_244_reg_6770[55] <= 1'b0;
tmp_244_reg_6770[56] <= 1'b0;
tmp_244_reg_6770[57] <= 1'b0;
tmp_244_reg_6770[58] <= 1'b0;
tmp_244_reg_6770[59] <= 1'b0;
tmp_244_reg_6770[60] <= 1'b0;
tmp_244_reg_6770[61] <= 1'b0;
tmp_244_reg_6770[62] <= 1'b0;
tmp_244_reg_6770[63] <= 1'b0;
end
always @ (ap_clk)
begin
tmp_245_reg_6780[14] <= 1'b0;
tmp_245_reg_6780[15] <= 1'b0;
tmp_245_reg_6780[16] <= 1'b0;
tmp_245_reg_6780[17] <= 1'b0;
tmp_245_reg_6780[18] <= 1'b0;
tmp_245_reg_6780[19] <= 1'b0;
tmp_245_reg_6780[20] <= 1'b0;
tmp_245_reg_6780[21] <= 1'b0;
tmp_245_reg_6780[22] <= 1'b0;
tmp_245_reg_6780[23] <= 1'b0;
tmp_245_reg_6780[24] <= 1'b0;
tmp_245_reg_6780[25] <= 1'b0;
tmp_245_reg_6780[26] <= 1'b0;
tmp_245_reg_6780[27] <= 1'b0;
tmp_245_reg_6780[28] <= 1'b0;
tmp_245_reg_6780[29] <= 1'b0;
tmp_245_reg_6780[30] <= 1'b0;
tmp_245_reg_6780[31] <= 1'b0;
tmp_245_reg_6780[32] <= 1'b0;
tmp_245_reg_6780[33] <= 1'b0;
tmp_245_reg_6780[34] <= 1'b0;
tmp_245_reg_6780[35] <= 1'b0;
tmp_245_reg_6780[36] <= 1'b0;
tmp_245_reg_6780[37] <= 1'b0;
tmp_245_reg_6780[38] <= 1'b0;
tmp_245_reg_6780[39] <= 1'b0;
tmp_245_reg_6780[40] <= 1'b0;
tmp_245_reg_6780[41] <= 1'b0;
tmp_245_reg_6780[42] <= 1'b0;
tmp_245_reg_6780[43] <= 1'b0;
tmp_245_reg_6780[44] <= 1'b0;
tmp_245_reg_6780[45] <= 1'b0;
tmp_245_reg_6780[46] <= 1'b0;
tmp_245_reg_6780[47] <= 1'b0;
tmp_245_reg_6780[48] <= 1'b0;
tmp_245_reg_6780[49] <= 1'b0;
tmp_245_reg_6780[50] <= 1'b0;
tmp_245_reg_6780[51] <= 1'b0;
tmp_245_reg_6780[52] <= 1'b0;
tmp_245_reg_6780[53] <= 1'b0;
tmp_245_reg_6780[54] <= 1'b0;
tmp_245_reg_6780[55] <= 1'b0;
tmp_245_reg_6780[56] <= 1'b0;
tmp_245_reg_6780[57] <= 1'b0;
tmp_245_reg_6780[58] <= 1'b0;
tmp_245_reg_6780[59] <= 1'b0;
tmp_245_reg_6780[60] <= 1'b0;
tmp_245_reg_6780[61] <= 1'b0;
tmp_245_reg_6780[62] <= 1'b0;
tmp_245_reg_6780[63] <= 1'b0;
end
always @ (ap_clk)
begin
tmp_246_reg_6790[0] <= 1'b1;
tmp_246_reg_6790[14] <= 1'b0;
tmp_246_reg_6790[15] <= 1'b0;
tmp_246_reg_6790[16] <= 1'b0;
tmp_246_reg_6790[17] <= 1'b0;
tmp_246_reg_6790[18] <= 1'b0;
tmp_246_reg_6790[19] <= 1'b0;
tmp_246_reg_6790[20] <= 1'b0;
tmp_246_reg_6790[21] <= 1'b0;
tmp_246_reg_6790[22] <= 1'b0;
tmp_246_reg_6790[23] <= 1'b0;
tmp_246_reg_6790[24] <= 1'b0;
tmp_246_reg_6790[25] <= 1'b0;
tmp_246_reg_6790[26] <= 1'b0;
tmp_246_reg_6790[27] <= 1'b0;
tmp_246_reg_6790[28] <= 1'b0;
tmp_246_reg_6790[29] <= 1'b0;
tmp_246_reg_6790[30] <= 1'b0;
tmp_246_reg_6790[31] <= 1'b0;
tmp_246_reg_6790[32] <= 1'b0;
tmp_246_reg_6790[33] <= 1'b0;
tmp_246_reg_6790[34] <= 1'b0;
tmp_246_reg_6790[35] <= 1'b0;
tmp_246_reg_6790[36] <= 1'b0;
tmp_246_reg_6790[37] <= 1'b0;
tmp_246_reg_6790[38] <= 1'b0;
tmp_246_reg_6790[39] <= 1'b0;
tmp_246_reg_6790[40] <= 1'b0;
tmp_246_reg_6790[41] <= 1'b0;
tmp_246_reg_6790[42] <= 1'b0;
tmp_246_reg_6790[43] <= 1'b0;
tmp_246_reg_6790[44] <= 1'b0;
tmp_246_reg_6790[45] <= 1'b0;
tmp_246_reg_6790[46] <= 1'b0;
tmp_246_reg_6790[47] <= 1'b0;
tmp_246_reg_6790[48] <= 1'b0;
tmp_246_reg_6790[49] <= 1'b0;
tmp_246_reg_6790[50] <= 1'b0;
tmp_246_reg_6790[51] <= 1'b0;
tmp_246_reg_6790[52] <= 1'b0;
tmp_246_reg_6790[53] <= 1'b0;
tmp_246_reg_6790[54] <= 1'b0;
tmp_246_reg_6790[55] <= 1'b0;
tmp_246_reg_6790[56] <= 1'b0;
tmp_246_reg_6790[57] <= 1'b0;
tmp_246_reg_6790[58] <= 1'b0;
tmp_246_reg_6790[59] <= 1'b0;
tmp_246_reg_6790[60] <= 1'b0;
tmp_246_reg_6790[61] <= 1'b0;
tmp_246_reg_6790[62] <= 1'b0;
tmp_246_reg_6790[63] <= 1'b0;
end
always @ (ap_clk)
begin
tmp_247_reg_6800[14] <= 1'b0;
tmp_247_reg_6800[15] <= 1'b0;
tmp_247_reg_6800[16] <= 1'b0;
tmp_247_reg_6800[17] <= 1'b0;
tmp_247_reg_6800[18] <= 1'b0;
tmp_247_reg_6800[19] <= 1'b0;
tmp_247_reg_6800[20] <= 1'b0;
tmp_247_reg_6800[21] <= 1'b0;
tmp_247_reg_6800[22] <= 1'b0;
tmp_247_reg_6800[23] <= 1'b0;
tmp_247_reg_6800[24] <= 1'b0;
tmp_247_reg_6800[25] <= 1'b0;
tmp_247_reg_6800[26] <= 1'b0;
tmp_247_reg_6800[27] <= 1'b0;
tmp_247_reg_6800[28] <= 1'b0;
tmp_247_reg_6800[29] <= 1'b0;
tmp_247_reg_6800[30] <= 1'b0;
tmp_247_reg_6800[31] <= 1'b0;
tmp_247_reg_6800[32] <= 1'b0;
tmp_247_reg_6800[33] <= 1'b0;
tmp_247_reg_6800[34] <= 1'b0;
tmp_247_reg_6800[35] <= 1'b0;
tmp_247_reg_6800[36] <= 1'b0;
tmp_247_reg_6800[37] <= 1'b0;
tmp_247_reg_6800[38] <= 1'b0;
tmp_247_reg_6800[39] <= 1'b0;
tmp_247_reg_6800[40] <= 1'b0;
tmp_247_reg_6800[41] <= 1'b0;
tmp_247_reg_6800[42] <= 1'b0;
tmp_247_reg_6800[43] <= 1'b0;
tmp_247_reg_6800[44] <= 1'b0;
tmp_247_reg_6800[45] <= 1'b0;
tmp_247_reg_6800[46] <= 1'b0;
tmp_247_reg_6800[47] <= 1'b0;
tmp_247_reg_6800[48] <= 1'b0;
tmp_247_reg_6800[49] <= 1'b0;
tmp_247_reg_6800[50] <= 1'b0;
tmp_247_reg_6800[51] <= 1'b0;
tmp_247_reg_6800[52] <= 1'b0;
tmp_247_reg_6800[53] <= 1'b0;
tmp_247_reg_6800[54] <= 1'b0;
tmp_247_reg_6800[55] <= 1'b0;
tmp_247_reg_6800[56] <= 1'b0;
tmp_247_reg_6800[57] <= 1'b0;
tmp_247_reg_6800[58] <= 1'b0;
tmp_247_reg_6800[59] <= 1'b0;
tmp_247_reg_6800[60] <= 1'b0;
tmp_247_reg_6800[61] <= 1'b0;
tmp_247_reg_6800[62] <= 1'b0;
tmp_247_reg_6800[63] <= 1'b0;
end
always @ (ap_clk)
begin
a_addr22_reg_6810[0] <= 1'b1;
a_addr22_reg_6810[1] <= 1'b1;
a_addr22_reg_6810[2] <= 1'b1;
end
always @ (ap_clk)
begin
a_addr19_reg_6815[0] <= 1'b1;
end
always @ (ap_clk)
begin
a_addr13_reg_6825[0] <= 1'b1;
a_addr13_reg_6825[1] <= 1'b1;
end
always @ (ap_clk)
begin
a_addr7_reg_6835[0] <= 1'b1;
end
always @ (ap_clk)
begin
a_addr1_reg_6845[0] <= 1'b1;
a_addr1_reg_6845[1] <= 1'b1;
a_addr1_reg_6845[2] <= 1'b1;
end
always @ (ap_clk)
begin
tmp_248_reg_6850[0] <= 1'b1;
tmp_248_reg_6850[1] <= 1'b1;
tmp_248_reg_6850[2] <= 1'b1;
tmp_248_reg_6850[14] <= 1'b0;
tmp_248_reg_6850[15] <= 1'b0;
tmp_248_reg_6850[16] <= 1'b0;
tmp_248_reg_6850[17] <= 1'b0;
tmp_248_reg_6850[18] <= 1'b0;
tmp_248_reg_6850[19] <= 1'b0;
tmp_248_reg_6850[20] <= 1'b0;
tmp_248_reg_6850[21] <= 1'b0;
tmp_248_reg_6850[22] <= 1'b0;
tmp_248_reg_6850[23] <= 1'b0;
tmp_248_reg_6850[24] <= 1'b0;
tmp_248_reg_6850[25] <= 1'b0;
tmp_248_reg_6850[26] <= 1'b0;
tmp_248_reg_6850[27] <= 1'b0;
tmp_248_reg_6850[28] <= 1'b0;
tmp_248_reg_6850[29] <= 1'b0;
tmp_248_reg_6850[30] <= 1'b0;
tmp_248_reg_6850[31] <= 1'b0;
tmp_248_reg_6850[32] <= 1'b0;
tmp_248_reg_6850[33] <= 1'b0;
tmp_248_reg_6850[34] <= 1'b0;
tmp_248_reg_6850[35] <= 1'b0;
tmp_248_reg_6850[36] <= 1'b0;
tmp_248_reg_6850[37] <= 1'b0;
tmp_248_reg_6850[38] <= 1'b0;
tmp_248_reg_6850[39] <= 1'b0;
tmp_248_reg_6850[40] <= 1'b0;
tmp_248_reg_6850[41] <= 1'b0;
tmp_248_reg_6850[42] <= 1'b0;
tmp_248_reg_6850[43] <= 1'b0;
tmp_248_reg_6850[44] <= 1'b0;
tmp_248_reg_6850[45] <= 1'b0;
tmp_248_reg_6850[46] <= 1'b0;
tmp_248_reg_6850[47] <= 1'b0;
tmp_248_reg_6850[48] <= 1'b0;
tmp_248_reg_6850[49] <= 1'b0;
tmp_248_reg_6850[50] <= 1'b0;
tmp_248_reg_6850[51] <= 1'b0;
tmp_248_reg_6850[52] <= 1'b0;
tmp_248_reg_6850[53] <= 1'b0;
tmp_248_reg_6850[54] <= 1'b0;
tmp_248_reg_6850[55] <= 1'b0;
tmp_248_reg_6850[56] <= 1'b0;
tmp_248_reg_6850[57] <= 1'b0;
tmp_248_reg_6850[58] <= 1'b0;
tmp_248_reg_6850[59] <= 1'b0;
tmp_248_reg_6850[60] <= 1'b0;
tmp_248_reg_6850[61] <= 1'b0;
tmp_248_reg_6850[62] <= 1'b0;
tmp_248_reg_6850[63] <= 1'b0;
end
always @ (ap_clk)
begin
tmp_249_reg_6860[0] <= 1'b1;
tmp_249_reg_6860[14] <= 1'b0;
tmp_249_reg_6860[15] <= 1'b0;
tmp_249_reg_6860[16] <= 1'b0;
tmp_249_reg_6860[17] <= 1'b0;
tmp_249_reg_6860[18] <= 1'b0;
tmp_249_reg_6860[19] <= 1'b0;
tmp_249_reg_6860[20] <= 1'b0;
tmp_249_reg_6860[21] <= 1'b0;
tmp_249_reg_6860[22] <= 1'b0;
tmp_249_reg_6860[23] <= 1'b0;
tmp_249_reg_6860[24] <= 1'b0;
tmp_249_reg_6860[25] <= 1'b0;
tmp_249_reg_6860[26] <= 1'b0;
tmp_249_reg_6860[27] <= 1'b0;
tmp_249_reg_6860[28] <= 1'b0;
tmp_249_reg_6860[29] <= 1'b0;
tmp_249_reg_6860[30] <= 1'b0;
tmp_249_reg_6860[31] <= 1'b0;
tmp_249_reg_6860[32] <= 1'b0;
tmp_249_reg_6860[33] <= 1'b0;
tmp_249_reg_6860[34] <= 1'b0;
tmp_249_reg_6860[35] <= 1'b0;
tmp_249_reg_6860[36] <= 1'b0;
tmp_249_reg_6860[37] <= 1'b0;
tmp_249_reg_6860[38] <= 1'b0;
tmp_249_reg_6860[39] <= 1'b0;
tmp_249_reg_6860[40] <= 1'b0;
tmp_249_reg_6860[41] <= 1'b0;
tmp_249_reg_6860[42] <= 1'b0;
tmp_249_reg_6860[43] <= 1'b0;
tmp_249_reg_6860[44] <= 1'b0;
tmp_249_reg_6860[45] <= 1'b0;
tmp_249_reg_6860[46] <= 1'b0;
tmp_249_reg_6860[47] <= 1'b0;
tmp_249_reg_6860[48] <= 1'b0;
tmp_249_reg_6860[49] <= 1'b0;
tmp_249_reg_6860[50] <= 1'b0;
tmp_249_reg_6860[51] <= 1'b0;
tmp_249_reg_6860[52] <= 1'b0;
tmp_249_reg_6860[53] <= 1'b0;
tmp_249_reg_6860[54] <= 1'b0;
tmp_249_reg_6860[55] <= 1'b0;
tmp_249_reg_6860[56] <= 1'b0;
tmp_249_reg_6860[57] <= 1'b0;
tmp_249_reg_6860[58] <= 1'b0;
tmp_249_reg_6860[59] <= 1'b0;
tmp_249_reg_6860[60] <= 1'b0;
tmp_249_reg_6860[61] <= 1'b0;
tmp_249_reg_6860[62] <= 1'b0;
tmp_249_reg_6860[63] <= 1'b0;
end
always @ (ap_clk)
begin
tmp_250_reg_6870[14] <= 1'b0;
tmp_250_reg_6870[15] <= 1'b0;
tmp_250_reg_6870[16] <= 1'b0;
tmp_250_reg_6870[17] <= 1'b0;
tmp_250_reg_6870[18] <= 1'b0;
tmp_250_reg_6870[19] <= 1'b0;
tmp_250_reg_6870[20] <= 1'b0;
tmp_250_reg_6870[21] <= 1'b0;
tmp_250_reg_6870[22] <= 1'b0;
tmp_250_reg_6870[23] <= 1'b0;
tmp_250_reg_6870[24] <= 1'b0;
tmp_250_reg_6870[25] <= 1'b0;
tmp_250_reg_6870[26] <= 1'b0;
tmp_250_reg_6870[27] <= 1'b0;
tmp_250_reg_6870[28] <= 1'b0;
tmp_250_reg_6870[29] <= 1'b0;
tmp_250_reg_6870[30] <= 1'b0;
tmp_250_reg_6870[31] <= 1'b0;
tmp_250_reg_6870[32] <= 1'b0;
tmp_250_reg_6870[33] <= 1'b0;
tmp_250_reg_6870[34] <= 1'b0;
tmp_250_reg_6870[35] <= 1'b0;
tmp_250_reg_6870[36] <= 1'b0;
tmp_250_reg_6870[37] <= 1'b0;
tmp_250_reg_6870[38] <= 1'b0;
tmp_250_reg_6870[39] <= 1'b0;
tmp_250_reg_6870[40] <= 1'b0;
tmp_250_reg_6870[41] <= 1'b0;
tmp_250_reg_6870[42] <= 1'b0;
tmp_250_reg_6870[43] <= 1'b0;
tmp_250_reg_6870[44] <= 1'b0;
tmp_250_reg_6870[45] <= 1'b0;
tmp_250_reg_6870[46] <= 1'b0;
tmp_250_reg_6870[47] <= 1'b0;
tmp_250_reg_6870[48] <= 1'b0;
tmp_250_reg_6870[49] <= 1'b0;
tmp_250_reg_6870[50] <= 1'b0;
tmp_250_reg_6870[51] <= 1'b0;
tmp_250_reg_6870[52] <= 1'b0;
tmp_250_reg_6870[53] <= 1'b0;
tmp_250_reg_6870[54] <= 1'b0;
tmp_250_reg_6870[55] <= 1'b0;
tmp_250_reg_6870[56] <= 1'b0;
tmp_250_reg_6870[57] <= 1'b0;
tmp_250_reg_6870[58] <= 1'b0;
tmp_250_reg_6870[59] <= 1'b0;
tmp_250_reg_6870[60] <= 1'b0;
tmp_250_reg_6870[61] <= 1'b0;
tmp_250_reg_6870[62] <= 1'b0;
tmp_250_reg_6870[63] <= 1'b0;
end
always @ (ap_clk)
begin
tmp_251_reg_6880[0] <= 1'b1;
tmp_251_reg_6880[1] <= 1'b1;
tmp_251_reg_6880[14] <= 1'b0;
tmp_251_reg_6880[15] <= 1'b0;
tmp_251_reg_6880[16] <= 1'b0;
tmp_251_reg_6880[17] <= 1'b0;
tmp_251_reg_6880[18] <= 1'b0;
tmp_251_reg_6880[19] <= 1'b0;
tmp_251_reg_6880[20] <= 1'b0;
tmp_251_reg_6880[21] <= 1'b0;
tmp_251_reg_6880[22] <= 1'b0;
tmp_251_reg_6880[23] <= 1'b0;
tmp_251_reg_6880[24] <= 1'b0;
tmp_251_reg_6880[25] <= 1'b0;
tmp_251_reg_6880[26] <= 1'b0;
tmp_251_reg_6880[27] <= 1'b0;
tmp_251_reg_6880[28] <= 1'b0;
tmp_251_reg_6880[29] <= 1'b0;
tmp_251_reg_6880[30] <= 1'b0;
tmp_251_reg_6880[31] <= 1'b0;
tmp_251_reg_6880[32] <= 1'b0;
tmp_251_reg_6880[33] <= 1'b0;
tmp_251_reg_6880[34] <= 1'b0;
tmp_251_reg_6880[35] <= 1'b0;
tmp_251_reg_6880[36] <= 1'b0;
tmp_251_reg_6880[37] <= 1'b0;
tmp_251_reg_6880[38] <= 1'b0;
tmp_251_reg_6880[39] <= 1'b0;
tmp_251_reg_6880[40] <= 1'b0;
tmp_251_reg_6880[41] <= 1'b0;
tmp_251_reg_6880[42] <= 1'b0;
tmp_251_reg_6880[43] <= 1'b0;
tmp_251_reg_6880[44] <= 1'b0;
tmp_251_reg_6880[45] <= 1'b0;
tmp_251_reg_6880[46] <= 1'b0;
tmp_251_reg_6880[47] <= 1'b0;
tmp_251_reg_6880[48] <= 1'b0;
tmp_251_reg_6880[49] <= 1'b0;
tmp_251_reg_6880[50] <= 1'b0;
tmp_251_reg_6880[51] <= 1'b0;
tmp_251_reg_6880[52] <= 1'b0;
tmp_251_reg_6880[53] <= 1'b0;
tmp_251_reg_6880[54] <= 1'b0;
tmp_251_reg_6880[55] <= 1'b0;
tmp_251_reg_6880[56] <= 1'b0;
tmp_251_reg_6880[57] <= 1'b0;
tmp_251_reg_6880[58] <= 1'b0;
tmp_251_reg_6880[59] <= 1'b0;
tmp_251_reg_6880[60] <= 1'b0;
tmp_251_reg_6880[61] <= 1'b0;
tmp_251_reg_6880[62] <= 1'b0;
tmp_251_reg_6880[63] <= 1'b0;
end
always @ (ap_clk)
begin
tmp_252_reg_6890[14] <= 1'b0;
tmp_252_reg_6890[15] <= 1'b0;
tmp_252_reg_6890[16] <= 1'b0;
tmp_252_reg_6890[17] <= 1'b0;
tmp_252_reg_6890[18] <= 1'b0;
tmp_252_reg_6890[19] <= 1'b0;
tmp_252_reg_6890[20] <= 1'b0;
tmp_252_reg_6890[21] <= 1'b0;
tmp_252_reg_6890[22] <= 1'b0;
tmp_252_reg_6890[23] <= 1'b0;
tmp_252_reg_6890[24] <= 1'b0;
tmp_252_reg_6890[25] <= 1'b0;
tmp_252_reg_6890[26] <= 1'b0;
tmp_252_reg_6890[27] <= 1'b0;
tmp_252_reg_6890[28] <= 1'b0;
tmp_252_reg_6890[29] <= 1'b0;
tmp_252_reg_6890[30] <= 1'b0;
tmp_252_reg_6890[31] <= 1'b0;
tmp_252_reg_6890[32] <= 1'b0;
tmp_252_reg_6890[33] <= 1'b0;
tmp_252_reg_6890[34] <= 1'b0;
tmp_252_reg_6890[35] <= 1'b0;
tmp_252_reg_6890[36] <= 1'b0;
tmp_252_reg_6890[37] <= 1'b0;
tmp_252_reg_6890[38] <= 1'b0;
tmp_252_reg_6890[39] <= 1'b0;
tmp_252_reg_6890[40] <= 1'b0;
tmp_252_reg_6890[41] <= 1'b0;
tmp_252_reg_6890[42] <= 1'b0;
tmp_252_reg_6890[43] <= 1'b0;
tmp_252_reg_6890[44] <= 1'b0;
tmp_252_reg_6890[45] <= 1'b0;
tmp_252_reg_6890[46] <= 1'b0;
tmp_252_reg_6890[47] <= 1'b0;
tmp_252_reg_6890[48] <= 1'b0;
tmp_252_reg_6890[49] <= 1'b0;
tmp_252_reg_6890[50] <= 1'b0;
tmp_252_reg_6890[51] <= 1'b0;
tmp_252_reg_6890[52] <= 1'b0;
tmp_252_reg_6890[53] <= 1'b0;
tmp_252_reg_6890[54] <= 1'b0;
tmp_252_reg_6890[55] <= 1'b0;
tmp_252_reg_6890[56] <= 1'b0;
tmp_252_reg_6890[57] <= 1'b0;
tmp_252_reg_6890[58] <= 1'b0;
tmp_252_reg_6890[59] <= 1'b0;
tmp_252_reg_6890[60] <= 1'b0;
tmp_252_reg_6890[61] <= 1'b0;
tmp_252_reg_6890[62] <= 1'b0;
tmp_252_reg_6890[63] <= 1'b0;
end
always @ (ap_clk)
begin
tmp_253_reg_6900[0] <= 1'b1;
tmp_253_reg_6900[14] <= 1'b0;
tmp_253_reg_6900[15] <= 1'b0;
tmp_253_reg_6900[16] <= 1'b0;
tmp_253_reg_6900[17] <= 1'b0;
tmp_253_reg_6900[18] <= 1'b0;
tmp_253_reg_6900[19] <= 1'b0;
tmp_253_reg_6900[20] <= 1'b0;
tmp_253_reg_6900[21] <= 1'b0;
tmp_253_reg_6900[22] <= 1'b0;
tmp_253_reg_6900[23] <= 1'b0;
tmp_253_reg_6900[24] <= 1'b0;
tmp_253_reg_6900[25] <= 1'b0;
tmp_253_reg_6900[26] <= 1'b0;
tmp_253_reg_6900[27] <= 1'b0;
tmp_253_reg_6900[28] <= 1'b0;
tmp_253_reg_6900[29] <= 1'b0;
tmp_253_reg_6900[30] <= 1'b0;
tmp_253_reg_6900[31] <= 1'b0;
tmp_253_reg_6900[32] <= 1'b0;
tmp_253_reg_6900[33] <= 1'b0;
tmp_253_reg_6900[34] <= 1'b0;
tmp_253_reg_6900[35] <= 1'b0;
tmp_253_reg_6900[36] <= 1'b0;
tmp_253_reg_6900[37] <= 1'b0;
tmp_253_reg_6900[38] <= 1'b0;
tmp_253_reg_6900[39] <= 1'b0;
tmp_253_reg_6900[40] <= 1'b0;
tmp_253_reg_6900[41] <= 1'b0;
tmp_253_reg_6900[42] <= 1'b0;
tmp_253_reg_6900[43] <= 1'b0;
tmp_253_reg_6900[44] <= 1'b0;
tmp_253_reg_6900[45] <= 1'b0;
tmp_253_reg_6900[46] <= 1'b0;
tmp_253_reg_6900[47] <= 1'b0;
tmp_253_reg_6900[48] <= 1'b0;
tmp_253_reg_6900[49] <= 1'b0;
tmp_253_reg_6900[50] <= 1'b0;
tmp_253_reg_6900[51] <= 1'b0;
tmp_253_reg_6900[52] <= 1'b0;
tmp_253_reg_6900[53] <= 1'b0;
tmp_253_reg_6900[54] <= 1'b0;
tmp_253_reg_6900[55] <= 1'b0;
tmp_253_reg_6900[56] <= 1'b0;
tmp_253_reg_6900[57] <= 1'b0;
tmp_253_reg_6900[58] <= 1'b0;
tmp_253_reg_6900[59] <= 1'b0;
tmp_253_reg_6900[60] <= 1'b0;
tmp_253_reg_6900[61] <= 1'b0;
tmp_253_reg_6900[62] <= 1'b0;
tmp_253_reg_6900[63] <= 1'b0;
end
always @ (ap_clk)
begin
tmp_254_reg_6910[14] <= 1'b0;
tmp_254_reg_6910[15] <= 1'b0;
tmp_254_reg_6910[16] <= 1'b0;
tmp_254_reg_6910[17] <= 1'b0;
tmp_254_reg_6910[18] <= 1'b0;
tmp_254_reg_6910[19] <= 1'b0;
tmp_254_reg_6910[20] <= 1'b0;
tmp_254_reg_6910[21] <= 1'b0;
tmp_254_reg_6910[22] <= 1'b0;
tmp_254_reg_6910[23] <= 1'b0;
tmp_254_reg_6910[24] <= 1'b0;
tmp_254_reg_6910[25] <= 1'b0;
tmp_254_reg_6910[26] <= 1'b0;
tmp_254_reg_6910[27] <= 1'b0;
tmp_254_reg_6910[28] <= 1'b0;
tmp_254_reg_6910[29] <= 1'b0;
tmp_254_reg_6910[30] <= 1'b0;
tmp_254_reg_6910[31] <= 1'b0;
tmp_254_reg_6910[32] <= 1'b0;
tmp_254_reg_6910[33] <= 1'b0;
tmp_254_reg_6910[34] <= 1'b0;
tmp_254_reg_6910[35] <= 1'b0;
tmp_254_reg_6910[36] <= 1'b0;
tmp_254_reg_6910[37] <= 1'b0;
tmp_254_reg_6910[38] <= 1'b0;
tmp_254_reg_6910[39] <= 1'b0;
tmp_254_reg_6910[40] <= 1'b0;
tmp_254_reg_6910[41] <= 1'b0;
tmp_254_reg_6910[42] <= 1'b0;
tmp_254_reg_6910[43] <= 1'b0;
tmp_254_reg_6910[44] <= 1'b0;
tmp_254_reg_6910[45] <= 1'b0;
tmp_254_reg_6910[46] <= 1'b0;
tmp_254_reg_6910[47] <= 1'b0;
tmp_254_reg_6910[48] <= 1'b0;
tmp_254_reg_6910[49] <= 1'b0;
tmp_254_reg_6910[50] <= 1'b0;
tmp_254_reg_6910[51] <= 1'b0;
tmp_254_reg_6910[52] <= 1'b0;
tmp_254_reg_6910[53] <= 1'b0;
tmp_254_reg_6910[54] <= 1'b0;
tmp_254_reg_6910[55] <= 1'b0;
tmp_254_reg_6910[56] <= 1'b0;
tmp_254_reg_6910[57] <= 1'b0;
tmp_254_reg_6910[58] <= 1'b0;
tmp_254_reg_6910[59] <= 1'b0;
tmp_254_reg_6910[60] <= 1'b0;
tmp_254_reg_6910[61] <= 1'b0;
tmp_254_reg_6910[62] <= 1'b0;
tmp_254_reg_6910[63] <= 1'b0;
end
always @ (ap_clk)
begin
tmp_255_reg_6920[0] <= 1'b1;
tmp_255_reg_6920[1] <= 1'b1;
tmp_255_reg_6920[2] <= 1'b1;
tmp_255_reg_6920[14] <= 1'b0;
tmp_255_reg_6920[15] <= 1'b0;
tmp_255_reg_6920[16] <= 1'b0;
tmp_255_reg_6920[17] <= 1'b0;
tmp_255_reg_6920[18] <= 1'b0;
tmp_255_reg_6920[19] <= 1'b0;
tmp_255_reg_6920[20] <= 1'b0;
tmp_255_reg_6920[21] <= 1'b0;
tmp_255_reg_6920[22] <= 1'b0;
tmp_255_reg_6920[23] <= 1'b0;
tmp_255_reg_6920[24] <= 1'b0;
tmp_255_reg_6920[25] <= 1'b0;
tmp_255_reg_6920[26] <= 1'b0;
tmp_255_reg_6920[27] <= 1'b0;
tmp_255_reg_6920[28] <= 1'b0;
tmp_255_reg_6920[29] <= 1'b0;
tmp_255_reg_6920[30] <= 1'b0;
tmp_255_reg_6920[31] <= 1'b0;
tmp_255_reg_6920[32] <= 1'b0;
tmp_255_reg_6920[33] <= 1'b0;
tmp_255_reg_6920[34] <= 1'b0;
tmp_255_reg_6920[35] <= 1'b0;
tmp_255_reg_6920[36] <= 1'b0;
tmp_255_reg_6920[37] <= 1'b0;
tmp_255_reg_6920[38] <= 1'b0;
tmp_255_reg_6920[39] <= 1'b0;
tmp_255_reg_6920[40] <= 1'b0;
tmp_255_reg_6920[41] <= 1'b0;
tmp_255_reg_6920[42] <= 1'b0;
tmp_255_reg_6920[43] <= 1'b0;
tmp_255_reg_6920[44] <= 1'b0;
tmp_255_reg_6920[45] <= 1'b0;
tmp_255_reg_6920[46] <= 1'b0;
tmp_255_reg_6920[47] <= 1'b0;
tmp_255_reg_6920[48] <= 1'b0;
tmp_255_reg_6920[49] <= 1'b0;
tmp_255_reg_6920[50] <= 1'b0;
tmp_255_reg_6920[51] <= 1'b0;
tmp_255_reg_6920[52] <= 1'b0;
tmp_255_reg_6920[53] <= 1'b0;
tmp_255_reg_6920[54] <= 1'b0;
tmp_255_reg_6920[55] <= 1'b0;
tmp_255_reg_6920[56] <= 1'b0;
tmp_255_reg_6920[57] <= 1'b0;
tmp_255_reg_6920[58] <= 1'b0;
tmp_255_reg_6920[59] <= 1'b0;
tmp_255_reg_6920[60] <= 1'b0;
tmp_255_reg_6920[61] <= 1'b0;
tmp_255_reg_6920[62] <= 1'b0;
tmp_255_reg_6920[63] <= 1'b0;
end
endmodule //step0
|
// ==============================================================
// File generated by AutoESL - High-Level Synthesis System (C, C++, SystemC)
// Version: 2011.1
// Copyright (C) 2011 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module step0_grp_fu_2163_ACMP_fadd_5(
clk,
reset,
ce,
din0,
din1,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
output[dout_WIDTH - 1:0] dout;
ACMP_fadd #(
.ID( ID ),
.NUM_STAGE( 5 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_fadd_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ));
endmodule
|
// ==============================================================
// File generated by AutoESL - High-Level Synthesis System (C, C++, SystemC)
// Version: 2011.1
// Copyright (C) 2011 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module step0_grp_fu_2167_ACMP_fmul_6(
clk,
reset,
ce,
din0,
din1,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
output[dout_WIDTH - 1:0] dout;
ACMP_fmul #(
.ID( ID ),
.NUM_STAGE( 4 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_fmul_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ));
endmodule
|
// ==============================================================
// RTL generated by AutoESL - High-Level Synthesis System (C, C++, SystemC)
// Version: 2011.1
// Copyright (C) 2011 Xilinx Inc. All rights reserved.
//
// ===========================================================
`timescale 1 ns / 1 ps
module step1 (
ap_clk,
ap_rst,
ap_start,
ap_done,
ap_idle,
step,
tag,
counter,
c_address0,
c_ce0,
c_q0,
c_address1,
c_ce1,
c_q1,
b_address0,
b_ce0,
b_q0,
b_address1,
b_ce1,
b_q1,
d_address0,
d_ce0,
d_we0,
d_d0,
d_address1,
d_ce1,
d_we1,
d_d1,
c1_address0,
c1_ce0,
c1_we0,
c1_d0,
c1_address1,
c1_ce1,
c1_we1,
c1_d1,
BoundryScale,
nu,
PostScale
);
input ap_clk;
input ap_rst;
input ap_start;
output ap_done;
output ap_idle;
input [0:0] step;
input [1:0] tag;
input [6:0] counter;
output [11:0] c_address0;
output c_ce0;
input [31:0] c_q0;
output [11:0] c_address1;
output c_ce1;
input [31:0] c_q1;
output [11:0] b_address0;
output b_ce0;
input [31:0] b_q0;
output [11:0] b_address1;
output b_ce1;
input [31:0] b_q1;
output [11:0] d_address0;
output d_ce0;
output d_we0;
output [31:0] d_d0;
output [11:0] d_address1;
output d_ce1;
output d_we1;
output [31:0] d_d1;
output [11:0] c1_address0;
output c1_ce0;
output c1_we0;
output [31:0] c1_d0;
output [11:0] c1_address1;
output c1_ce1;
output c1_we1;
output [31:0] c1_d1;
input [31:0] BoundryScale;
input [31:0] nu;
input [31:0] PostScale;
reg ap_done;
reg ap_idle;
reg[11:0] c_address0;
reg c_ce0;
reg[11:0] c_address1;
reg c_ce1;
reg[11:0] b_address0;
reg b_ce0;
reg[11:0] b_address1;
reg b_ce1;
reg[11:0] d_address0;
reg d_ce0;
reg d_we0;
reg[31:0] d_d0;
reg[11:0] d_address1;
reg d_ce1;
reg d_we1;
reg[31:0] d_d1;
reg[11:0] c1_address0;
reg c1_ce0;
reg c1_we0;
reg[31:0] c1_d0;
reg[11:0] c1_address1;
reg c1_ce1;
reg c1_we1;
reg[31:0] c1_d1;
reg [4:0] ap_CS_fsm;
reg [9:0] indvar_flatten_reg_722;
reg [6:0] i_reg_733;
reg [3:0] indvar3_reg_744;
reg [6:0] j_reg_755;
reg [9:0] indvar_flatten9_reg_766;
reg [6:0] i1_reg_777;
reg [3:0] indvar_reg_788;
reg [6:0] j1_reg_799;
reg [31:0] reg_823;
reg ap_reg_ppiten_pp0_it0;
reg ap_reg_ppiten_pp0_it1;
reg [0:0] exitcond_reg_1446;
reg ap_reg_ppiten_pp1_it0;
reg ap_reg_ppiten_pp1_it1;
reg ap_reg_ppiten_pp1_it2;
reg ap_reg_ppiten_pp1_it3;
reg [0:0] exitcond2_reg_1603;
reg [31:0] reg_829;
reg [31:0] reg_835;
reg [31:0] reg_841;
reg [31:0] reg_847;
reg [31:0] reg_853;
reg [31:0] reg_859;
wire [31:0] grp_fu_815_p2;
reg [31:0] reg_865;
reg [0:0] ap_reg_ppstg_exitcond_reg_1446_pp0_it1;
reg [0:0] or_cond_reg_1433;
reg [0:0] ap_reg_ppstg_exitcond2_reg_1603_pp1_it2;
reg [31:0] reg_874;
wire [31:0] grp_fu_819_p2;
reg [31:0] reg_882;
reg [31:0] reg_890;
reg [31:0] reg_898;
reg [31:0] reg_906;
reg [31:0] reg_914;
reg [31:0] reg_922;
reg [31:0] reg_928;
wire [0:0] tmp_2_fu_951_p2;
wire [0:0] exitcond_fu_957_p2;
reg [9:0] indvar_flatten_next_reg_1450;
wire [6:0] j_mid2_fu_975_p3;
reg [6:0] j_mid2_reg_1455;
wire [6:0] i_mid2_fu_989_p3;
reg [6:0] i_mid2_reg_1467;
wire [13:0] b_addr_cast_fu_1011_p1;
reg [13:0] b_addr_cast_reg_1472;
wire [63:0] tmp_6_fu_1021_p1;
reg [63:0] tmp_6_reg_1483;
reg [63:0] ap_reg_ppstg_tmp_6_reg_1483_pp0_it1;
reg [3:0] indvar_next4_reg_1495;
wire [63:0] tmp_7_fu_1054_p1;
reg [63:0] tmp_7_reg_1500;
reg [63:0] ap_reg_ppstg_tmp_7_reg_1500_pp0_it1;
wire [63:0] tmp_9_fu_1073_p1;
reg [63:0] tmp_9_reg_1512;
reg [63:0] ap_reg_ppstg_tmp_9_reg_1512_pp0_it1;
wire [63:0] tmp_11_fu_1092_p1;
reg [63:0] tmp_11_reg_1524;
reg [63:0] ap_reg_ppstg_tmp_11_reg_1524_pp0_it1;
wire [63:0] tmp_13_fu_1111_p1;
reg [63:0] tmp_13_reg_1536;
reg [63:0] ap_reg_ppstg_tmp_13_reg_1536_pp0_it1;
wire [63:0] tmp_15_fu_1130_p1;
reg [63:0] tmp_15_reg_1548;
reg [63:0] ap_reg_ppstg_tmp_15_reg_1548_pp0_it1;
wire [63:0] tmp_17_fu_1149_p1;
reg [63:0] tmp_17_reg_1560;
reg [63:0] ap_reg_ppstg_tmp_17_reg_1560_pp0_it1;
wire [13:0] b_addr8_fu_1163_p2;
reg [13:0] b_addr8_reg_1572;
reg [6:0] tmp_28_reg_1577;
wire [63:0] tmp_19_fu_1173_p1;
reg [63:0] tmp_19_reg_1582;
reg [63:0] ap_reg_ppstg_tmp_19_reg_1582_pp0_it1;
wire [0:0] or_cond1_fu_1187_p2;
wire [0:0] exitcond2_fu_1193_p2;
reg [0:0] ap_reg_ppstg_exitcond2_reg_1603_pp1_it1;
reg [0:0] ap_reg_ppstg_exitcond2_reg_1603_pp1_it3;
reg [9:0] indvar_flatten_next1_reg_1607;
wire [6:0] j1_mid2_fu_1211_p3;
reg [6:0] j1_mid2_reg_1612;
wire [6:0] i1_mid2_fu_1225_p3;
reg [6:0] i1_mid2_reg_1624;
wire [13:0] b_addr9_cast_fu_1247_p1;
reg [13:0] b_addr9_cast_reg_1629;
wire [63:0] tmp_30_fu_1257_p1;
reg [63:0] tmp_30_reg_1640;
reg [63:0] ap_reg_ppstg_tmp_30_reg_1640_pp1_it1;
reg [63:0] ap_reg_ppstg_tmp_30_reg_1640_pp1_it2;
reg [3:0] indvar_next_reg_1657;
wire [63:0] tmp_33_fu_1291_p1;
reg [63:0] tmp_33_reg_1662;
reg [63:0] ap_reg_ppstg_tmp_33_reg_1662_pp1_it1;
reg [63:0] ap_reg_ppstg_tmp_33_reg_1662_pp1_it2;
wire [63:0] tmp_36_fu_1311_p1;
reg [63:0] tmp_36_reg_1679;
reg [63:0] ap_reg_ppstg_tmp_36_reg_1679_pp1_it1;
reg [63:0] ap_reg_ppstg_tmp_36_reg_1679_pp1_it2;
reg [31:0] c_load_1_reg_1696;
reg [31:0] c_load_2_reg_1701;
wire [63:0] tmp_39_fu_1331_p1;
reg [63:0] tmp_39_reg_1706;
reg [63:0] ap_reg_ppstg_tmp_39_reg_1706_pp1_it1;
reg [63:0] ap_reg_ppstg_tmp_39_reg_1706_pp1_it2;
wire [63:0] tmp_42_fu_1351_p1;
reg [63:0] tmp_42_reg_1723;
reg [63:0] ap_reg_ppstg_tmp_42_reg_1723_pp1_it1;
reg [63:0] ap_reg_ppstg_tmp_42_reg_1723_pp1_it2;
reg [31:0] c_load_3_reg_1740;
reg [31:0] c_load_4_reg_1745;
wire [63:0] tmp_45_fu_1371_p1;
reg [63:0] tmp_45_reg_1750;
reg [63:0] ap_reg_ppstg_tmp_45_reg_1750_pp1_it1;
reg [63:0] ap_reg_ppstg_tmp_45_reg_1750_pp1_it2;
wire [63:0] tmp_48_fu_1391_p1;
reg [63:0] tmp_48_reg_1767;
reg [63:0] ap_reg_ppstg_tmp_48_reg_1767_pp1_it1;
reg [63:0] ap_reg_ppstg_tmp_48_reg_1767_pp1_it2;
wire [13:0] b_addr17_fu_1406_p2;
reg [13:0] b_addr17_reg_1784;
reg [6:0] tmp_61_reg_1789;
reg [31:0] c_load_5_reg_1794;
reg [31:0] c_load_6_reg_1799;
wire [63:0] tmp_51_fu_1416_p1;
reg [63:0] tmp_51_reg_1804;
reg [63:0] ap_reg_ppstg_tmp_51_reg_1804_pp1_it1;
reg [63:0] ap_reg_ppstg_tmp_51_reg_1804_pp1_it2;
reg [31:0] b_load_15_reg_1821;
reg [31:0] tmp_52_reg_1826;
wire [31:0] grp_fu_811_p2;
reg [31:0] t_reg_1831;
reg [31:0] t8_reg_1838;
reg [31:0] t9_reg_1845;
reg [31:0] t10_reg_1852;
reg [31:0] t11_reg_1859;
reg [31:0] t12_reg_1866;
reg [31:0] t13_reg_1873;
reg [31:0] t14_reg_1880;
reg [31:0] tmp_57_reg_1887;
reg [31:0] tmp_58_reg_1892;
reg [31:0] tmp_60_reg_1897;
reg [9:0] indvar_flatten_phi_fu_726_p4;
reg [6:0] i_phi_fu_737_p4;
reg [3:0] indvar3_phi_fu_748_p4;
reg [6:0] j_phi_fu_759_p4;
reg [9:0] indvar_flatten9_phi_fu_770_p4;
reg [6:0] i1_phi_fu_781_p4;
reg [3:0] indvar_phi_fu_792_p4;
reg [6:0] j1_phi_fu_803_p4;
reg [31:0] grp_fu_811_p0;
reg [31:0] grp_fu_811_p1;
reg [31:0] grp_fu_815_p0;
reg [31:0] grp_fu_815_p1;
reg [31:0] grp_fu_819_p0;
reg [31:0] grp_fu_819_p1;
wire [0:0] tmp_fu_933_p2;
wire [0:0] tmp_1_fu_939_p2;
wire [0:0] exitcond1_fu_969_p2;
wire [6:0] tmp_6_dup_fu_983_p2;
wire [12:0] tmp_3_trn_cast_fu_997_p1;
wire [12:0] b_addr_fu_1005_p2;
wire [13:0] tmp_7_trn_cast_fu_1001_p1;
wire [13:0] b_addr1_fu_1015_p2;
wire [3:0] indvar3_op_fu_1026_p2;
wire [6:0] tmp_8_fu_1040_p2;
wire [13:0] tmp_9_trn_cast_fu_1045_p1;
wire [13:0] b_addr2_fu_1049_p2;
wire [6:0] tmp_s_fu_1059_p2;
wire [13:0] tmp_10_trn_cast_fu_1064_p1;
wire [13:0] b_addr3_fu_1068_p2;
wire [6:0] tmp_10_fu_1078_p2;
wire [13:0] tmp_12_trn_cast_fu_1083_p1;
wire [13:0] b_addr4_fu_1087_p2;
wire [6:0] tmp_12_fu_1097_p2;
wire [13:0] tmp_14_trn_cast_fu_1102_p1;
wire [13:0] b_addr5_fu_1106_p2;
wire [6:0] tmp_14_fu_1116_p2;
wire [13:0] tmp_16_trn_cast_fu_1121_p1;
wire [13:0] b_addr6_fu_1125_p2;
wire [6:0] tmp_16_fu_1135_p2;
wire [13:0] tmp_18_trn_cast_fu_1140_p1;
wire [13:0] b_addr7_fu_1144_p2;
wire [6:0] tmp_18_fu_1154_p2;
wire [13:0] tmp_20_trn_cast_fu_1159_p1;
wire [0:0] tmp_4_fu_1177_p2;
wire [0:0] tmp_5_fu_1182_p2;
wire [0:0] exitcond3_fu_1205_p2;
wire [6:0] tmp_31_dup_fu_1219_p2;
wire [12:0] tmp_29_trn_cast_fu_1233_p1;
wire [12:0] b_addr9_fu_1241_p2;
wire [13:0] tmp_32_trn_cast_fu_1237_p1;
wire [13:0] b_addr10_fu_1251_p2;
wire [3:0] indvar_op_fu_1263_p2;
wire [6:0] tmp_32_fu_1277_p2;
wire [13:0] tmp_35_trn_cast_fu_1282_p1;
wire [13:0] b_addr11_fu_1286_p2;
wire [6:0] tmp_35_fu_1297_p2;
wire [13:0] tmp_38_trn_cast_fu_1302_p1;
wire [13:0] b_addr12_fu_1306_p2;
wire [6:0] tmp_38_fu_1317_p2;
wire [13:0] tmp_41_trn_cast_fu_1322_p1;
wire [13:0] b_addr13_fu_1326_p2;
wire [6:0] tmp_41_fu_1337_p2;
wire [13:0] tmp_44_trn_cast_fu_1342_p1;
wire [13:0] b_addr14_fu_1346_p2;
wire [6:0] tmp_44_fu_1357_p2;
wire [13:0] tmp_47_trn_cast_fu_1362_p1;
wire [13:0] b_addr15_fu_1366_p2;
wire [6:0] tmp_47_fu_1377_p2;
wire [13:0] tmp_50_trn_cast_fu_1382_p1;
wire [13:0] b_addr16_fu_1386_p2;
wire [6:0] tmp_50_fu_1397_p2;
wire [13:0] tmp_53_trn_cast_fu_1402_p1;
wire grp_fu_811_ce;
wire grp_fu_815_ce;
wire grp_fu_819_ce;
reg [4:0] ap_NS_fsm;
parameter ap_const_logic_1 = 1'b1;
parameter ap_const_logic_0 = 1'b0;
parameter ap_ST_st0_fsm_0 = 5'b00000;
parameter ap_ST_st1_fsm_1 = 5'b00001;
parameter ap_ST_pp0_stg0_fsm_2 = 5'b00010;
parameter ap_ST_pp0_stg1_fsm_3 = 5'b00011;
parameter ap_ST_pp0_stg2_fsm_4 = 5'b00100;
parameter ap_ST_pp0_stg3_fsm_5 = 5'b00101;
parameter ap_ST_pp0_stg4_fsm_6 = 5'b00110;
parameter ap_ST_pp0_stg5_fsm_7 = 5'b00111;
parameter ap_ST_pp0_stg6_fsm_8 = 5'b01000;
parameter ap_ST_pp0_stg7_fsm_9 = 5'b01001;
parameter ap_ST_st17_fsm_10 = 5'b01010;
parameter ap_ST_pp1_stg0_fsm_11 = 5'b01011;
parameter ap_ST_pp1_stg1_fsm_12 = 5'b01100;
parameter ap_ST_pp1_stg2_fsm_13 = 5'b01101;
parameter ap_ST_pp1_stg3_fsm_14 = 5'b01110;
parameter ap_ST_pp1_stg4_fsm_15 = 5'b01111;
parameter ap_ST_pp1_stg5_fsm_16 = 5'b10000;
parameter ap_ST_pp1_stg6_fsm_17 = 5'b10001;
parameter ap_ST_pp1_stg7_fsm_18 = 5'b10010;
parameter ap_ST_st44_fsm_19 = 5'b10011;
parameter ap_const_lv1_0 = 1'b0;
parameter ap_const_lv10_0 = 10'b0000000000;
parameter ap_const_lv7_0 = 7'b0000000;
parameter ap_const_lv4_0 = 4'b0000;
parameter ap_const_lv2_1 = 2'b01;
parameter ap_const_lv1_1 = 1'b1;
parameter ap_const_lv7_2 = 7'b0000010;
parameter ap_const_lv10_200 = 10'b1000000000;
parameter ap_const_lv10_1 = 10'b0000000001;
parameter ap_const_lv4_8 = 4'b1000;
parameter ap_const_lv7_1 = 7'b0000001;
parameter ap_const_lv13_6 = 13'b0000000000110;
parameter ap_const_lv4_1 = 4'b0001;
parameter ap_const_lv7_3 = 7'b0000011;
parameter ap_const_lv7_4 = 7'b0000100;
parameter ap_const_lv7_5 = 7'b0000101;
parameter ap_const_lv7_6 = 7'b0000110;
parameter ap_const_lv7_7 = 7'b0000111;
parameter ap_const_lv7_8 = 7'b0001000;
parameter ap_const_lv7_42 = 7'b1000010;
parameter ap_true = 1'b1;
step1_grp_fu_811_ACMP_fadd_13 #(
.ID( 13 ),
.NUM_STAGE( 5 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
step1_grp_fu_811_ACMP_fadd_13_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_811_p0 ),
.din1( grp_fu_811_p1 ),
.ce( grp_fu_811_ce ),
.dout( grp_fu_811_p2 )
);
step1_grp_fu_815_ACMP_fmul_14 #(
.ID( 14 ),
.NUM_STAGE( 4 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
step1_grp_fu_815_ACMP_fmul_14_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_815_p0 ),
.din1( grp_fu_815_p1 ),
.ce( grp_fu_815_ce ),
.dout( grp_fu_815_p2 )
);
step1_grp_fu_819_ACMP_fmul_15 #(
.ID( 15 ),
.NUM_STAGE( 4 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
step1_grp_fu_819_ACMP_fmul_15_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_819_p0 ),
.din1( grp_fu_819_p1 ),
.ce( grp_fu_819_ce ),
.dout( grp_fu_819_p2 )
);
/// ap_CS_fsm assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_CS_fsm
if (ap_rst == 1'b1) begin
ap_CS_fsm <= ap_ST_st0_fsm_0;
end else begin
ap_CS_fsm <= ap_NS_fsm;
end
end
/// ap_reg_ppiten_pp0_it0 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it0
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it0 <= ap_const_logic_0;
end else begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond_fu_957_p2))) begin
ap_reg_ppiten_pp0_it0 <= ap_const_logic_0;
end else if (((ap_ST_st1_fsm_1 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_2_fu_951_p2))) begin
ap_reg_ppiten_pp0_it0 <= ap_const_logic_1;
end
end
end
/// ap_reg_ppiten_pp0_it1 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it1
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it1 <= ap_const_logic_0;
end else begin
if (((exitcond_reg_1446 == ap_const_lv1_0) & (ap_ST_pp0_stg7_fsm_9 == ap_CS_fsm))) begin
ap_reg_ppiten_pp0_it1 <= ap_const_logic_1;
end else if ((((ap_ST_st1_fsm_1 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_2_fu_951_p2)) | ((ap_ST_pp0_stg7_fsm_9 == ap_CS_fsm) & ~(exitcond_reg_1446 == ap_const_lv1_0)))) begin
ap_reg_ppiten_pp0_it1 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp1_it0 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp1_it0
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp1_it0 <= ap_const_logic_0;
end else begin
if (((ap_ST_pp1_stg0_fsm_11 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond2_fu_1193_p2))) begin
ap_reg_ppiten_pp1_it0 <= ap_const_logic_0;
end else if (((ap_ST_st17_fsm_10 == ap_CS_fsm) & ~(ap_const_lv1_0 == or_cond1_fu_1187_p2))) begin
ap_reg_ppiten_pp1_it0 <= ap_const_logic_1;
end
end
end
/// ap_reg_ppiten_pp1_it1 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp1_it1
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp1_it1 <= ap_const_logic_0;
end else begin
if (((ap_const_lv1_0 == exitcond2_reg_1603) & (ap_ST_pp1_stg7_fsm_18 == ap_CS_fsm))) begin
ap_reg_ppiten_pp1_it1 <= ap_const_logic_1;
end else if ((((ap_ST_st17_fsm_10 == ap_CS_fsm) & ~(ap_const_lv1_0 == or_cond1_fu_1187_p2)) | ((ap_ST_pp1_stg7_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond2_reg_1603)))) begin
ap_reg_ppiten_pp1_it1 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp1_it2 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp1_it2
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp1_it2 <= ap_const_logic_0;
end else begin
if ((ap_ST_pp1_stg7_fsm_18 == ap_CS_fsm)) begin
ap_reg_ppiten_pp1_it2 <= ap_reg_ppiten_pp1_it1;
end else if (((ap_ST_st17_fsm_10 == ap_CS_fsm) & ~(ap_const_lv1_0 == or_cond1_fu_1187_p2))) begin
ap_reg_ppiten_pp1_it2 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp1_it3 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp1_it3
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp1_it3 <= ap_const_logic_0;
end else begin
if ((ap_ST_pp1_stg7_fsm_18 == ap_CS_fsm)) begin
ap_reg_ppiten_pp1_it3 <= ap_reg_ppiten_pp1_it2;
end else if (((ap_ST_st17_fsm_10 == ap_CS_fsm) & ~(ap_const_lv1_0 == or_cond1_fu_1187_p2))) begin
ap_reg_ppiten_pp1_it3 <= ap_const_logic_0;
end
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_ST_pp1_stg0_fsm_11 == ap_CS_fsm)) begin
ap_reg_ppstg_exitcond2_reg_1603_pp1_it1 <= exitcond2_reg_1603;
end
if ((ap_ST_pp1_stg0_fsm_11 == ap_CS_fsm)) begin
ap_reg_ppstg_exitcond2_reg_1603_pp1_it2 <= ap_reg_ppstg_exitcond2_reg_1603_pp1_it1;
end
if ((ap_ST_pp1_stg0_fsm_11 == ap_CS_fsm)) begin
ap_reg_ppstg_exitcond2_reg_1603_pp1_it3 <= ap_reg_ppstg_exitcond2_reg_1603_pp1_it2;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_exitcond_reg_1446_pp0_it1 <= exitcond_reg_1446;
end
if ((ap_ST_pp0_stg2_fsm_4 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_11_reg_1524_pp0_it1[2] <= tmp_11_reg_1524[2];
ap_reg_ppstg_tmp_11_reg_1524_pp0_it1[3] <= tmp_11_reg_1524[3];
ap_reg_ppstg_tmp_11_reg_1524_pp0_it1[4] <= tmp_11_reg_1524[4];
ap_reg_ppstg_tmp_11_reg_1524_pp0_it1[5] <= tmp_11_reg_1524[5];
ap_reg_ppstg_tmp_11_reg_1524_pp0_it1[6] <= tmp_11_reg_1524[6];
ap_reg_ppstg_tmp_11_reg_1524_pp0_it1[7] <= tmp_11_reg_1524[7];
ap_reg_ppstg_tmp_11_reg_1524_pp0_it1[8] <= tmp_11_reg_1524[8];
ap_reg_ppstg_tmp_11_reg_1524_pp0_it1[9] <= tmp_11_reg_1524[9];
ap_reg_ppstg_tmp_11_reg_1524_pp0_it1[10] <= tmp_11_reg_1524[10];
ap_reg_ppstg_tmp_11_reg_1524_pp0_it1[11] <= tmp_11_reg_1524[11];
ap_reg_ppstg_tmp_11_reg_1524_pp0_it1[12] <= tmp_11_reg_1524[12];
ap_reg_ppstg_tmp_11_reg_1524_pp0_it1[13] <= tmp_11_reg_1524[13];
end
if ((ap_ST_pp0_stg2_fsm_4 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_13_reg_1536_pp0_it1[0] <= tmp_13_reg_1536[0];
ap_reg_ppstg_tmp_13_reg_1536_pp0_it1[1] <= tmp_13_reg_1536[1];
ap_reg_ppstg_tmp_13_reg_1536_pp0_it1[2] <= tmp_13_reg_1536[2];
ap_reg_ppstg_tmp_13_reg_1536_pp0_it1[3] <= tmp_13_reg_1536[3];
ap_reg_ppstg_tmp_13_reg_1536_pp0_it1[4] <= tmp_13_reg_1536[4];
ap_reg_ppstg_tmp_13_reg_1536_pp0_it1[5] <= tmp_13_reg_1536[5];
ap_reg_ppstg_tmp_13_reg_1536_pp0_it1[6] <= tmp_13_reg_1536[6];
ap_reg_ppstg_tmp_13_reg_1536_pp0_it1[7] <= tmp_13_reg_1536[7];
ap_reg_ppstg_tmp_13_reg_1536_pp0_it1[8] <= tmp_13_reg_1536[8];
ap_reg_ppstg_tmp_13_reg_1536_pp0_it1[9] <= tmp_13_reg_1536[9];
ap_reg_ppstg_tmp_13_reg_1536_pp0_it1[10] <= tmp_13_reg_1536[10];
ap_reg_ppstg_tmp_13_reg_1536_pp0_it1[11] <= tmp_13_reg_1536[11];
ap_reg_ppstg_tmp_13_reg_1536_pp0_it1[12] <= tmp_13_reg_1536[12];
ap_reg_ppstg_tmp_13_reg_1536_pp0_it1[13] <= tmp_13_reg_1536[13];
end
if ((ap_ST_pp0_stg3_fsm_5 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_15_reg_1548_pp0_it1[1] <= tmp_15_reg_1548[1];
ap_reg_ppstg_tmp_15_reg_1548_pp0_it1[2] <= tmp_15_reg_1548[2];
ap_reg_ppstg_tmp_15_reg_1548_pp0_it1[3] <= tmp_15_reg_1548[3];
ap_reg_ppstg_tmp_15_reg_1548_pp0_it1[4] <= tmp_15_reg_1548[4];
ap_reg_ppstg_tmp_15_reg_1548_pp0_it1[5] <= tmp_15_reg_1548[5];
ap_reg_ppstg_tmp_15_reg_1548_pp0_it1[6] <= tmp_15_reg_1548[6];
ap_reg_ppstg_tmp_15_reg_1548_pp0_it1[7] <= tmp_15_reg_1548[7];
ap_reg_ppstg_tmp_15_reg_1548_pp0_it1[8] <= tmp_15_reg_1548[8];
ap_reg_ppstg_tmp_15_reg_1548_pp0_it1[9] <= tmp_15_reg_1548[9];
ap_reg_ppstg_tmp_15_reg_1548_pp0_it1[10] <= tmp_15_reg_1548[10];
ap_reg_ppstg_tmp_15_reg_1548_pp0_it1[11] <= tmp_15_reg_1548[11];
ap_reg_ppstg_tmp_15_reg_1548_pp0_it1[12] <= tmp_15_reg_1548[12];
ap_reg_ppstg_tmp_15_reg_1548_pp0_it1[13] <= tmp_15_reg_1548[13];
end
if ((ap_ST_pp0_stg3_fsm_5 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_17_reg_1560_pp0_it1[0] <= tmp_17_reg_1560[0];
ap_reg_ppstg_tmp_17_reg_1560_pp0_it1[1] <= tmp_17_reg_1560[1];
ap_reg_ppstg_tmp_17_reg_1560_pp0_it1[2] <= tmp_17_reg_1560[2];
ap_reg_ppstg_tmp_17_reg_1560_pp0_it1[3] <= tmp_17_reg_1560[3];
ap_reg_ppstg_tmp_17_reg_1560_pp0_it1[4] <= tmp_17_reg_1560[4];
ap_reg_ppstg_tmp_17_reg_1560_pp0_it1[5] <= tmp_17_reg_1560[5];
ap_reg_ppstg_tmp_17_reg_1560_pp0_it1[6] <= tmp_17_reg_1560[6];
ap_reg_ppstg_tmp_17_reg_1560_pp0_it1[7] <= tmp_17_reg_1560[7];
ap_reg_ppstg_tmp_17_reg_1560_pp0_it1[8] <= tmp_17_reg_1560[8];
ap_reg_ppstg_tmp_17_reg_1560_pp0_it1[9] <= tmp_17_reg_1560[9];
ap_reg_ppstg_tmp_17_reg_1560_pp0_it1[10] <= tmp_17_reg_1560[10];
ap_reg_ppstg_tmp_17_reg_1560_pp0_it1[11] <= tmp_17_reg_1560[11];
ap_reg_ppstg_tmp_17_reg_1560_pp0_it1[12] <= tmp_17_reg_1560[12];
ap_reg_ppstg_tmp_17_reg_1560_pp0_it1[13] <= tmp_17_reg_1560[13];
end
if ((ap_ST_pp0_stg4_fsm_6 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_19_reg_1582_pp0_it1[3] <= tmp_19_reg_1582[3];
ap_reg_ppstg_tmp_19_reg_1582_pp0_it1[4] <= tmp_19_reg_1582[4];
ap_reg_ppstg_tmp_19_reg_1582_pp0_it1[5] <= tmp_19_reg_1582[5];
ap_reg_ppstg_tmp_19_reg_1582_pp0_it1[6] <= tmp_19_reg_1582[6];
ap_reg_ppstg_tmp_19_reg_1582_pp0_it1[7] <= tmp_19_reg_1582[7];
ap_reg_ppstg_tmp_19_reg_1582_pp0_it1[8] <= tmp_19_reg_1582[8];
ap_reg_ppstg_tmp_19_reg_1582_pp0_it1[9] <= tmp_19_reg_1582[9];
ap_reg_ppstg_tmp_19_reg_1582_pp0_it1[10] <= tmp_19_reg_1582[10];
ap_reg_ppstg_tmp_19_reg_1582_pp0_it1[11] <= tmp_19_reg_1582[11];
ap_reg_ppstg_tmp_19_reg_1582_pp0_it1[12] <= tmp_19_reg_1582[12];
ap_reg_ppstg_tmp_19_reg_1582_pp0_it1[13] <= tmp_19_reg_1582[13];
end
if ((ap_ST_pp1_stg0_fsm_11 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_30_reg_1640_pp1_it1[0] <= tmp_30_reg_1640[0];
ap_reg_ppstg_tmp_30_reg_1640_pp1_it1[1] <= tmp_30_reg_1640[1];
ap_reg_ppstg_tmp_30_reg_1640_pp1_it1[2] <= tmp_30_reg_1640[2];
ap_reg_ppstg_tmp_30_reg_1640_pp1_it1[3] <= tmp_30_reg_1640[3];
ap_reg_ppstg_tmp_30_reg_1640_pp1_it1[4] <= tmp_30_reg_1640[4];
ap_reg_ppstg_tmp_30_reg_1640_pp1_it1[5] <= tmp_30_reg_1640[5];
ap_reg_ppstg_tmp_30_reg_1640_pp1_it1[6] <= tmp_30_reg_1640[6];
ap_reg_ppstg_tmp_30_reg_1640_pp1_it1[7] <= tmp_30_reg_1640[7];
ap_reg_ppstg_tmp_30_reg_1640_pp1_it1[8] <= tmp_30_reg_1640[8];
ap_reg_ppstg_tmp_30_reg_1640_pp1_it1[9] <= tmp_30_reg_1640[9];
ap_reg_ppstg_tmp_30_reg_1640_pp1_it1[10] <= tmp_30_reg_1640[10];
ap_reg_ppstg_tmp_30_reg_1640_pp1_it1[11] <= tmp_30_reg_1640[11];
ap_reg_ppstg_tmp_30_reg_1640_pp1_it1[12] <= tmp_30_reg_1640[12];
ap_reg_ppstg_tmp_30_reg_1640_pp1_it1[13] <= tmp_30_reg_1640[13];
end
if ((ap_ST_pp1_stg0_fsm_11 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_30_reg_1640_pp1_it2[0] <= ap_reg_ppstg_tmp_30_reg_1640_pp1_it1[0];
ap_reg_ppstg_tmp_30_reg_1640_pp1_it2[1] <= ap_reg_ppstg_tmp_30_reg_1640_pp1_it1[1];
ap_reg_ppstg_tmp_30_reg_1640_pp1_it2[2] <= ap_reg_ppstg_tmp_30_reg_1640_pp1_it1[2];
ap_reg_ppstg_tmp_30_reg_1640_pp1_it2[3] <= ap_reg_ppstg_tmp_30_reg_1640_pp1_it1[3];
ap_reg_ppstg_tmp_30_reg_1640_pp1_it2[4] <= ap_reg_ppstg_tmp_30_reg_1640_pp1_it1[4];
ap_reg_ppstg_tmp_30_reg_1640_pp1_it2[5] <= ap_reg_ppstg_tmp_30_reg_1640_pp1_it1[5];
ap_reg_ppstg_tmp_30_reg_1640_pp1_it2[6] <= ap_reg_ppstg_tmp_30_reg_1640_pp1_it1[6];
ap_reg_ppstg_tmp_30_reg_1640_pp1_it2[7] <= ap_reg_ppstg_tmp_30_reg_1640_pp1_it1[7];
ap_reg_ppstg_tmp_30_reg_1640_pp1_it2[8] <= ap_reg_ppstg_tmp_30_reg_1640_pp1_it1[8];
ap_reg_ppstg_tmp_30_reg_1640_pp1_it2[9] <= ap_reg_ppstg_tmp_30_reg_1640_pp1_it1[9];
ap_reg_ppstg_tmp_30_reg_1640_pp1_it2[10] <= ap_reg_ppstg_tmp_30_reg_1640_pp1_it1[10];
ap_reg_ppstg_tmp_30_reg_1640_pp1_it2[11] <= ap_reg_ppstg_tmp_30_reg_1640_pp1_it1[11];
ap_reg_ppstg_tmp_30_reg_1640_pp1_it2[12] <= ap_reg_ppstg_tmp_30_reg_1640_pp1_it1[12];
ap_reg_ppstg_tmp_30_reg_1640_pp1_it2[13] <= ap_reg_ppstg_tmp_30_reg_1640_pp1_it1[13];
end
if ((ap_ST_pp1_stg1_fsm_12 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_33_reg_1662_pp1_it1[1] <= tmp_33_reg_1662[1];
ap_reg_ppstg_tmp_33_reg_1662_pp1_it1[2] <= tmp_33_reg_1662[2];
ap_reg_ppstg_tmp_33_reg_1662_pp1_it1[3] <= tmp_33_reg_1662[3];
ap_reg_ppstg_tmp_33_reg_1662_pp1_it1[4] <= tmp_33_reg_1662[4];
ap_reg_ppstg_tmp_33_reg_1662_pp1_it1[5] <= tmp_33_reg_1662[5];
ap_reg_ppstg_tmp_33_reg_1662_pp1_it1[6] <= tmp_33_reg_1662[6];
ap_reg_ppstg_tmp_33_reg_1662_pp1_it1[7] <= tmp_33_reg_1662[7];
ap_reg_ppstg_tmp_33_reg_1662_pp1_it1[8] <= tmp_33_reg_1662[8];
ap_reg_ppstg_tmp_33_reg_1662_pp1_it1[9] <= tmp_33_reg_1662[9];
ap_reg_ppstg_tmp_33_reg_1662_pp1_it1[10] <= tmp_33_reg_1662[10];
ap_reg_ppstg_tmp_33_reg_1662_pp1_it1[11] <= tmp_33_reg_1662[11];
ap_reg_ppstg_tmp_33_reg_1662_pp1_it1[12] <= tmp_33_reg_1662[12];
ap_reg_ppstg_tmp_33_reg_1662_pp1_it1[13] <= tmp_33_reg_1662[13];
end
if ((ap_ST_pp1_stg1_fsm_12 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_33_reg_1662_pp1_it2[1] <= ap_reg_ppstg_tmp_33_reg_1662_pp1_it1[1];
ap_reg_ppstg_tmp_33_reg_1662_pp1_it2[2] <= ap_reg_ppstg_tmp_33_reg_1662_pp1_it1[2];
ap_reg_ppstg_tmp_33_reg_1662_pp1_it2[3] <= ap_reg_ppstg_tmp_33_reg_1662_pp1_it1[3];
ap_reg_ppstg_tmp_33_reg_1662_pp1_it2[4] <= ap_reg_ppstg_tmp_33_reg_1662_pp1_it1[4];
ap_reg_ppstg_tmp_33_reg_1662_pp1_it2[5] <= ap_reg_ppstg_tmp_33_reg_1662_pp1_it1[5];
ap_reg_ppstg_tmp_33_reg_1662_pp1_it2[6] <= ap_reg_ppstg_tmp_33_reg_1662_pp1_it1[6];
ap_reg_ppstg_tmp_33_reg_1662_pp1_it2[7] <= ap_reg_ppstg_tmp_33_reg_1662_pp1_it1[7];
ap_reg_ppstg_tmp_33_reg_1662_pp1_it2[8] <= ap_reg_ppstg_tmp_33_reg_1662_pp1_it1[8];
ap_reg_ppstg_tmp_33_reg_1662_pp1_it2[9] <= ap_reg_ppstg_tmp_33_reg_1662_pp1_it1[9];
ap_reg_ppstg_tmp_33_reg_1662_pp1_it2[10] <= ap_reg_ppstg_tmp_33_reg_1662_pp1_it1[10];
ap_reg_ppstg_tmp_33_reg_1662_pp1_it2[11] <= ap_reg_ppstg_tmp_33_reg_1662_pp1_it1[11];
ap_reg_ppstg_tmp_33_reg_1662_pp1_it2[12] <= ap_reg_ppstg_tmp_33_reg_1662_pp1_it1[12];
ap_reg_ppstg_tmp_33_reg_1662_pp1_it2[13] <= ap_reg_ppstg_tmp_33_reg_1662_pp1_it1[13];
end
if ((ap_ST_pp1_stg1_fsm_12 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_36_reg_1679_pp1_it1[0] <= tmp_36_reg_1679[0];
ap_reg_ppstg_tmp_36_reg_1679_pp1_it1[1] <= tmp_36_reg_1679[1];
ap_reg_ppstg_tmp_36_reg_1679_pp1_it1[2] <= tmp_36_reg_1679[2];
ap_reg_ppstg_tmp_36_reg_1679_pp1_it1[3] <= tmp_36_reg_1679[3];
ap_reg_ppstg_tmp_36_reg_1679_pp1_it1[4] <= tmp_36_reg_1679[4];
ap_reg_ppstg_tmp_36_reg_1679_pp1_it1[5] <= tmp_36_reg_1679[5];
ap_reg_ppstg_tmp_36_reg_1679_pp1_it1[6] <= tmp_36_reg_1679[6];
ap_reg_ppstg_tmp_36_reg_1679_pp1_it1[7] <= tmp_36_reg_1679[7];
ap_reg_ppstg_tmp_36_reg_1679_pp1_it1[8] <= tmp_36_reg_1679[8];
ap_reg_ppstg_tmp_36_reg_1679_pp1_it1[9] <= tmp_36_reg_1679[9];
ap_reg_ppstg_tmp_36_reg_1679_pp1_it1[10] <= tmp_36_reg_1679[10];
ap_reg_ppstg_tmp_36_reg_1679_pp1_it1[11] <= tmp_36_reg_1679[11];
ap_reg_ppstg_tmp_36_reg_1679_pp1_it1[12] <= tmp_36_reg_1679[12];
ap_reg_ppstg_tmp_36_reg_1679_pp1_it1[13] <= tmp_36_reg_1679[13];
end
if ((ap_ST_pp1_stg1_fsm_12 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_36_reg_1679_pp1_it2[0] <= ap_reg_ppstg_tmp_36_reg_1679_pp1_it1[0];
ap_reg_ppstg_tmp_36_reg_1679_pp1_it2[1] <= ap_reg_ppstg_tmp_36_reg_1679_pp1_it1[1];
ap_reg_ppstg_tmp_36_reg_1679_pp1_it2[2] <= ap_reg_ppstg_tmp_36_reg_1679_pp1_it1[2];
ap_reg_ppstg_tmp_36_reg_1679_pp1_it2[3] <= ap_reg_ppstg_tmp_36_reg_1679_pp1_it1[3];
ap_reg_ppstg_tmp_36_reg_1679_pp1_it2[4] <= ap_reg_ppstg_tmp_36_reg_1679_pp1_it1[4];
ap_reg_ppstg_tmp_36_reg_1679_pp1_it2[5] <= ap_reg_ppstg_tmp_36_reg_1679_pp1_it1[5];
ap_reg_ppstg_tmp_36_reg_1679_pp1_it2[6] <= ap_reg_ppstg_tmp_36_reg_1679_pp1_it1[6];
ap_reg_ppstg_tmp_36_reg_1679_pp1_it2[7] <= ap_reg_ppstg_tmp_36_reg_1679_pp1_it1[7];
ap_reg_ppstg_tmp_36_reg_1679_pp1_it2[8] <= ap_reg_ppstg_tmp_36_reg_1679_pp1_it1[8];
ap_reg_ppstg_tmp_36_reg_1679_pp1_it2[9] <= ap_reg_ppstg_tmp_36_reg_1679_pp1_it1[9];
ap_reg_ppstg_tmp_36_reg_1679_pp1_it2[10] <= ap_reg_ppstg_tmp_36_reg_1679_pp1_it1[10];
ap_reg_ppstg_tmp_36_reg_1679_pp1_it2[11] <= ap_reg_ppstg_tmp_36_reg_1679_pp1_it1[11];
ap_reg_ppstg_tmp_36_reg_1679_pp1_it2[12] <= ap_reg_ppstg_tmp_36_reg_1679_pp1_it1[12];
ap_reg_ppstg_tmp_36_reg_1679_pp1_it2[13] <= ap_reg_ppstg_tmp_36_reg_1679_pp1_it1[13];
end
if ((ap_ST_pp1_stg2_fsm_13 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_39_reg_1706_pp1_it1[2] <= tmp_39_reg_1706[2];
ap_reg_ppstg_tmp_39_reg_1706_pp1_it1[3] <= tmp_39_reg_1706[3];
ap_reg_ppstg_tmp_39_reg_1706_pp1_it1[4] <= tmp_39_reg_1706[4];
ap_reg_ppstg_tmp_39_reg_1706_pp1_it1[5] <= tmp_39_reg_1706[5];
ap_reg_ppstg_tmp_39_reg_1706_pp1_it1[6] <= tmp_39_reg_1706[6];
ap_reg_ppstg_tmp_39_reg_1706_pp1_it1[7] <= tmp_39_reg_1706[7];
ap_reg_ppstg_tmp_39_reg_1706_pp1_it1[8] <= tmp_39_reg_1706[8];
ap_reg_ppstg_tmp_39_reg_1706_pp1_it1[9] <= tmp_39_reg_1706[9];
ap_reg_ppstg_tmp_39_reg_1706_pp1_it1[10] <= tmp_39_reg_1706[10];
ap_reg_ppstg_tmp_39_reg_1706_pp1_it1[11] <= tmp_39_reg_1706[11];
ap_reg_ppstg_tmp_39_reg_1706_pp1_it1[12] <= tmp_39_reg_1706[12];
ap_reg_ppstg_tmp_39_reg_1706_pp1_it1[13] <= tmp_39_reg_1706[13];
end
if ((ap_ST_pp1_stg2_fsm_13 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_39_reg_1706_pp1_it2[2] <= ap_reg_ppstg_tmp_39_reg_1706_pp1_it1[2];
ap_reg_ppstg_tmp_39_reg_1706_pp1_it2[3] <= ap_reg_ppstg_tmp_39_reg_1706_pp1_it1[3];
ap_reg_ppstg_tmp_39_reg_1706_pp1_it2[4] <= ap_reg_ppstg_tmp_39_reg_1706_pp1_it1[4];
ap_reg_ppstg_tmp_39_reg_1706_pp1_it2[5] <= ap_reg_ppstg_tmp_39_reg_1706_pp1_it1[5];
ap_reg_ppstg_tmp_39_reg_1706_pp1_it2[6] <= ap_reg_ppstg_tmp_39_reg_1706_pp1_it1[6];
ap_reg_ppstg_tmp_39_reg_1706_pp1_it2[7] <= ap_reg_ppstg_tmp_39_reg_1706_pp1_it1[7];
ap_reg_ppstg_tmp_39_reg_1706_pp1_it2[8] <= ap_reg_ppstg_tmp_39_reg_1706_pp1_it1[8];
ap_reg_ppstg_tmp_39_reg_1706_pp1_it2[9] <= ap_reg_ppstg_tmp_39_reg_1706_pp1_it1[9];
ap_reg_ppstg_tmp_39_reg_1706_pp1_it2[10] <= ap_reg_ppstg_tmp_39_reg_1706_pp1_it1[10];
ap_reg_ppstg_tmp_39_reg_1706_pp1_it2[11] <= ap_reg_ppstg_tmp_39_reg_1706_pp1_it1[11];
ap_reg_ppstg_tmp_39_reg_1706_pp1_it2[12] <= ap_reg_ppstg_tmp_39_reg_1706_pp1_it1[12];
ap_reg_ppstg_tmp_39_reg_1706_pp1_it2[13] <= ap_reg_ppstg_tmp_39_reg_1706_pp1_it1[13];
end
if ((ap_ST_pp1_stg2_fsm_13 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_42_reg_1723_pp1_it1[0] <= tmp_42_reg_1723[0];
ap_reg_ppstg_tmp_42_reg_1723_pp1_it1[1] <= tmp_42_reg_1723[1];
ap_reg_ppstg_tmp_42_reg_1723_pp1_it1[2] <= tmp_42_reg_1723[2];
ap_reg_ppstg_tmp_42_reg_1723_pp1_it1[3] <= tmp_42_reg_1723[3];
ap_reg_ppstg_tmp_42_reg_1723_pp1_it1[4] <= tmp_42_reg_1723[4];
ap_reg_ppstg_tmp_42_reg_1723_pp1_it1[5] <= tmp_42_reg_1723[5];
ap_reg_ppstg_tmp_42_reg_1723_pp1_it1[6] <= tmp_42_reg_1723[6];
ap_reg_ppstg_tmp_42_reg_1723_pp1_it1[7] <= tmp_42_reg_1723[7];
ap_reg_ppstg_tmp_42_reg_1723_pp1_it1[8] <= tmp_42_reg_1723[8];
ap_reg_ppstg_tmp_42_reg_1723_pp1_it1[9] <= tmp_42_reg_1723[9];
ap_reg_ppstg_tmp_42_reg_1723_pp1_it1[10] <= tmp_42_reg_1723[10];
ap_reg_ppstg_tmp_42_reg_1723_pp1_it1[11] <= tmp_42_reg_1723[11];
ap_reg_ppstg_tmp_42_reg_1723_pp1_it1[12] <= tmp_42_reg_1723[12];
ap_reg_ppstg_tmp_42_reg_1723_pp1_it1[13] <= tmp_42_reg_1723[13];
end
if ((ap_ST_pp1_stg2_fsm_13 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_42_reg_1723_pp1_it2[0] <= ap_reg_ppstg_tmp_42_reg_1723_pp1_it1[0];
ap_reg_ppstg_tmp_42_reg_1723_pp1_it2[1] <= ap_reg_ppstg_tmp_42_reg_1723_pp1_it1[1];
ap_reg_ppstg_tmp_42_reg_1723_pp1_it2[2] <= ap_reg_ppstg_tmp_42_reg_1723_pp1_it1[2];
ap_reg_ppstg_tmp_42_reg_1723_pp1_it2[3] <= ap_reg_ppstg_tmp_42_reg_1723_pp1_it1[3];
ap_reg_ppstg_tmp_42_reg_1723_pp1_it2[4] <= ap_reg_ppstg_tmp_42_reg_1723_pp1_it1[4];
ap_reg_ppstg_tmp_42_reg_1723_pp1_it2[5] <= ap_reg_ppstg_tmp_42_reg_1723_pp1_it1[5];
ap_reg_ppstg_tmp_42_reg_1723_pp1_it2[6] <= ap_reg_ppstg_tmp_42_reg_1723_pp1_it1[6];
ap_reg_ppstg_tmp_42_reg_1723_pp1_it2[7] <= ap_reg_ppstg_tmp_42_reg_1723_pp1_it1[7];
ap_reg_ppstg_tmp_42_reg_1723_pp1_it2[8] <= ap_reg_ppstg_tmp_42_reg_1723_pp1_it1[8];
ap_reg_ppstg_tmp_42_reg_1723_pp1_it2[9] <= ap_reg_ppstg_tmp_42_reg_1723_pp1_it1[9];
ap_reg_ppstg_tmp_42_reg_1723_pp1_it2[10] <= ap_reg_ppstg_tmp_42_reg_1723_pp1_it1[10];
ap_reg_ppstg_tmp_42_reg_1723_pp1_it2[11] <= ap_reg_ppstg_tmp_42_reg_1723_pp1_it1[11];
ap_reg_ppstg_tmp_42_reg_1723_pp1_it2[12] <= ap_reg_ppstg_tmp_42_reg_1723_pp1_it1[12];
ap_reg_ppstg_tmp_42_reg_1723_pp1_it2[13] <= ap_reg_ppstg_tmp_42_reg_1723_pp1_it1[13];
end
if ((ap_ST_pp1_stg3_fsm_14 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_45_reg_1750_pp1_it1[1] <= tmp_45_reg_1750[1];
ap_reg_ppstg_tmp_45_reg_1750_pp1_it1[2] <= tmp_45_reg_1750[2];
ap_reg_ppstg_tmp_45_reg_1750_pp1_it1[3] <= tmp_45_reg_1750[3];
ap_reg_ppstg_tmp_45_reg_1750_pp1_it1[4] <= tmp_45_reg_1750[4];
ap_reg_ppstg_tmp_45_reg_1750_pp1_it1[5] <= tmp_45_reg_1750[5];
ap_reg_ppstg_tmp_45_reg_1750_pp1_it1[6] <= tmp_45_reg_1750[6];
ap_reg_ppstg_tmp_45_reg_1750_pp1_it1[7] <= tmp_45_reg_1750[7];
ap_reg_ppstg_tmp_45_reg_1750_pp1_it1[8] <= tmp_45_reg_1750[8];
ap_reg_ppstg_tmp_45_reg_1750_pp1_it1[9] <= tmp_45_reg_1750[9];
ap_reg_ppstg_tmp_45_reg_1750_pp1_it1[10] <= tmp_45_reg_1750[10];
ap_reg_ppstg_tmp_45_reg_1750_pp1_it1[11] <= tmp_45_reg_1750[11];
ap_reg_ppstg_tmp_45_reg_1750_pp1_it1[12] <= tmp_45_reg_1750[12];
ap_reg_ppstg_tmp_45_reg_1750_pp1_it1[13] <= tmp_45_reg_1750[13];
end
if ((ap_ST_pp1_stg3_fsm_14 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_45_reg_1750_pp1_it2[1] <= ap_reg_ppstg_tmp_45_reg_1750_pp1_it1[1];
ap_reg_ppstg_tmp_45_reg_1750_pp1_it2[2] <= ap_reg_ppstg_tmp_45_reg_1750_pp1_it1[2];
ap_reg_ppstg_tmp_45_reg_1750_pp1_it2[3] <= ap_reg_ppstg_tmp_45_reg_1750_pp1_it1[3];
ap_reg_ppstg_tmp_45_reg_1750_pp1_it2[4] <= ap_reg_ppstg_tmp_45_reg_1750_pp1_it1[4];
ap_reg_ppstg_tmp_45_reg_1750_pp1_it2[5] <= ap_reg_ppstg_tmp_45_reg_1750_pp1_it1[5];
ap_reg_ppstg_tmp_45_reg_1750_pp1_it2[6] <= ap_reg_ppstg_tmp_45_reg_1750_pp1_it1[6];
ap_reg_ppstg_tmp_45_reg_1750_pp1_it2[7] <= ap_reg_ppstg_tmp_45_reg_1750_pp1_it1[7];
ap_reg_ppstg_tmp_45_reg_1750_pp1_it2[8] <= ap_reg_ppstg_tmp_45_reg_1750_pp1_it1[8];
ap_reg_ppstg_tmp_45_reg_1750_pp1_it2[9] <= ap_reg_ppstg_tmp_45_reg_1750_pp1_it1[9];
ap_reg_ppstg_tmp_45_reg_1750_pp1_it2[10] <= ap_reg_ppstg_tmp_45_reg_1750_pp1_it1[10];
ap_reg_ppstg_tmp_45_reg_1750_pp1_it2[11] <= ap_reg_ppstg_tmp_45_reg_1750_pp1_it1[11];
ap_reg_ppstg_tmp_45_reg_1750_pp1_it2[12] <= ap_reg_ppstg_tmp_45_reg_1750_pp1_it1[12];
ap_reg_ppstg_tmp_45_reg_1750_pp1_it2[13] <= ap_reg_ppstg_tmp_45_reg_1750_pp1_it1[13];
end
if ((ap_ST_pp1_stg3_fsm_14 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_48_reg_1767_pp1_it1[0] <= tmp_48_reg_1767[0];
ap_reg_ppstg_tmp_48_reg_1767_pp1_it1[1] <= tmp_48_reg_1767[1];
ap_reg_ppstg_tmp_48_reg_1767_pp1_it1[2] <= tmp_48_reg_1767[2];
ap_reg_ppstg_tmp_48_reg_1767_pp1_it1[3] <= tmp_48_reg_1767[3];
ap_reg_ppstg_tmp_48_reg_1767_pp1_it1[4] <= tmp_48_reg_1767[4];
ap_reg_ppstg_tmp_48_reg_1767_pp1_it1[5] <= tmp_48_reg_1767[5];
ap_reg_ppstg_tmp_48_reg_1767_pp1_it1[6] <= tmp_48_reg_1767[6];
ap_reg_ppstg_tmp_48_reg_1767_pp1_it1[7] <= tmp_48_reg_1767[7];
ap_reg_ppstg_tmp_48_reg_1767_pp1_it1[8] <= tmp_48_reg_1767[8];
ap_reg_ppstg_tmp_48_reg_1767_pp1_it1[9] <= tmp_48_reg_1767[9];
ap_reg_ppstg_tmp_48_reg_1767_pp1_it1[10] <= tmp_48_reg_1767[10];
ap_reg_ppstg_tmp_48_reg_1767_pp1_it1[11] <= tmp_48_reg_1767[11];
ap_reg_ppstg_tmp_48_reg_1767_pp1_it1[12] <= tmp_48_reg_1767[12];
ap_reg_ppstg_tmp_48_reg_1767_pp1_it1[13] <= tmp_48_reg_1767[13];
end
if ((ap_ST_pp1_stg3_fsm_14 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_48_reg_1767_pp1_it2[0] <= ap_reg_ppstg_tmp_48_reg_1767_pp1_it1[0];
ap_reg_ppstg_tmp_48_reg_1767_pp1_it2[1] <= ap_reg_ppstg_tmp_48_reg_1767_pp1_it1[1];
ap_reg_ppstg_tmp_48_reg_1767_pp1_it2[2] <= ap_reg_ppstg_tmp_48_reg_1767_pp1_it1[2];
ap_reg_ppstg_tmp_48_reg_1767_pp1_it2[3] <= ap_reg_ppstg_tmp_48_reg_1767_pp1_it1[3];
ap_reg_ppstg_tmp_48_reg_1767_pp1_it2[4] <= ap_reg_ppstg_tmp_48_reg_1767_pp1_it1[4];
ap_reg_ppstg_tmp_48_reg_1767_pp1_it2[5] <= ap_reg_ppstg_tmp_48_reg_1767_pp1_it1[5];
ap_reg_ppstg_tmp_48_reg_1767_pp1_it2[6] <= ap_reg_ppstg_tmp_48_reg_1767_pp1_it1[6];
ap_reg_ppstg_tmp_48_reg_1767_pp1_it2[7] <= ap_reg_ppstg_tmp_48_reg_1767_pp1_it1[7];
ap_reg_ppstg_tmp_48_reg_1767_pp1_it2[8] <= ap_reg_ppstg_tmp_48_reg_1767_pp1_it1[8];
ap_reg_ppstg_tmp_48_reg_1767_pp1_it2[9] <= ap_reg_ppstg_tmp_48_reg_1767_pp1_it1[9];
ap_reg_ppstg_tmp_48_reg_1767_pp1_it2[10] <= ap_reg_ppstg_tmp_48_reg_1767_pp1_it1[10];
ap_reg_ppstg_tmp_48_reg_1767_pp1_it2[11] <= ap_reg_ppstg_tmp_48_reg_1767_pp1_it1[11];
ap_reg_ppstg_tmp_48_reg_1767_pp1_it2[12] <= ap_reg_ppstg_tmp_48_reg_1767_pp1_it1[12];
ap_reg_ppstg_tmp_48_reg_1767_pp1_it2[13] <= ap_reg_ppstg_tmp_48_reg_1767_pp1_it1[13];
end
if ((ap_ST_pp1_stg4_fsm_15 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_51_reg_1804_pp1_it1[3] <= tmp_51_reg_1804[3];
ap_reg_ppstg_tmp_51_reg_1804_pp1_it1[4] <= tmp_51_reg_1804[4];
ap_reg_ppstg_tmp_51_reg_1804_pp1_it1[5] <= tmp_51_reg_1804[5];
ap_reg_ppstg_tmp_51_reg_1804_pp1_it1[6] <= tmp_51_reg_1804[6];
ap_reg_ppstg_tmp_51_reg_1804_pp1_it1[7] <= tmp_51_reg_1804[7];
ap_reg_ppstg_tmp_51_reg_1804_pp1_it1[8] <= tmp_51_reg_1804[8];
ap_reg_ppstg_tmp_51_reg_1804_pp1_it1[9] <= tmp_51_reg_1804[9];
ap_reg_ppstg_tmp_51_reg_1804_pp1_it1[10] <= tmp_51_reg_1804[10];
ap_reg_ppstg_tmp_51_reg_1804_pp1_it1[11] <= tmp_51_reg_1804[11];
ap_reg_ppstg_tmp_51_reg_1804_pp1_it1[12] <= tmp_51_reg_1804[12];
ap_reg_ppstg_tmp_51_reg_1804_pp1_it1[13] <= tmp_51_reg_1804[13];
end
if ((ap_ST_pp1_stg4_fsm_15 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_51_reg_1804_pp1_it2[3] <= ap_reg_ppstg_tmp_51_reg_1804_pp1_it1[3];
ap_reg_ppstg_tmp_51_reg_1804_pp1_it2[4] <= ap_reg_ppstg_tmp_51_reg_1804_pp1_it1[4];
ap_reg_ppstg_tmp_51_reg_1804_pp1_it2[5] <= ap_reg_ppstg_tmp_51_reg_1804_pp1_it1[5];
ap_reg_ppstg_tmp_51_reg_1804_pp1_it2[6] <= ap_reg_ppstg_tmp_51_reg_1804_pp1_it1[6];
ap_reg_ppstg_tmp_51_reg_1804_pp1_it2[7] <= ap_reg_ppstg_tmp_51_reg_1804_pp1_it1[7];
ap_reg_ppstg_tmp_51_reg_1804_pp1_it2[8] <= ap_reg_ppstg_tmp_51_reg_1804_pp1_it1[8];
ap_reg_ppstg_tmp_51_reg_1804_pp1_it2[9] <= ap_reg_ppstg_tmp_51_reg_1804_pp1_it1[9];
ap_reg_ppstg_tmp_51_reg_1804_pp1_it2[10] <= ap_reg_ppstg_tmp_51_reg_1804_pp1_it1[10];
ap_reg_ppstg_tmp_51_reg_1804_pp1_it2[11] <= ap_reg_ppstg_tmp_51_reg_1804_pp1_it1[11];
ap_reg_ppstg_tmp_51_reg_1804_pp1_it2[12] <= ap_reg_ppstg_tmp_51_reg_1804_pp1_it1[12];
ap_reg_ppstg_tmp_51_reg_1804_pp1_it2[13] <= ap_reg_ppstg_tmp_51_reg_1804_pp1_it1[13];
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_6_reg_1483_pp0_it1[0] <= tmp_6_reg_1483[0];
ap_reg_ppstg_tmp_6_reg_1483_pp0_it1[1] <= tmp_6_reg_1483[1];
ap_reg_ppstg_tmp_6_reg_1483_pp0_it1[2] <= tmp_6_reg_1483[2];
ap_reg_ppstg_tmp_6_reg_1483_pp0_it1[3] <= tmp_6_reg_1483[3];
ap_reg_ppstg_tmp_6_reg_1483_pp0_it1[4] <= tmp_6_reg_1483[4];
ap_reg_ppstg_tmp_6_reg_1483_pp0_it1[5] <= tmp_6_reg_1483[5];
ap_reg_ppstg_tmp_6_reg_1483_pp0_it1[6] <= tmp_6_reg_1483[6];
ap_reg_ppstg_tmp_6_reg_1483_pp0_it1[7] <= tmp_6_reg_1483[7];
ap_reg_ppstg_tmp_6_reg_1483_pp0_it1[8] <= tmp_6_reg_1483[8];
ap_reg_ppstg_tmp_6_reg_1483_pp0_it1[9] <= tmp_6_reg_1483[9];
ap_reg_ppstg_tmp_6_reg_1483_pp0_it1[10] <= tmp_6_reg_1483[10];
ap_reg_ppstg_tmp_6_reg_1483_pp0_it1[11] <= tmp_6_reg_1483[11];
ap_reg_ppstg_tmp_6_reg_1483_pp0_it1[12] <= tmp_6_reg_1483[12];
ap_reg_ppstg_tmp_6_reg_1483_pp0_it1[13] <= tmp_6_reg_1483[13];
end
if ((ap_ST_pp0_stg1_fsm_3 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_7_reg_1500_pp0_it1[1] <= tmp_7_reg_1500[1];
ap_reg_ppstg_tmp_7_reg_1500_pp0_it1[2] <= tmp_7_reg_1500[2];
ap_reg_ppstg_tmp_7_reg_1500_pp0_it1[3] <= tmp_7_reg_1500[3];
ap_reg_ppstg_tmp_7_reg_1500_pp0_it1[4] <= tmp_7_reg_1500[4];
ap_reg_ppstg_tmp_7_reg_1500_pp0_it1[5] <= tmp_7_reg_1500[5];
ap_reg_ppstg_tmp_7_reg_1500_pp0_it1[6] <= tmp_7_reg_1500[6];
ap_reg_ppstg_tmp_7_reg_1500_pp0_it1[7] <= tmp_7_reg_1500[7];
ap_reg_ppstg_tmp_7_reg_1500_pp0_it1[8] <= tmp_7_reg_1500[8];
ap_reg_ppstg_tmp_7_reg_1500_pp0_it1[9] <= tmp_7_reg_1500[9];
ap_reg_ppstg_tmp_7_reg_1500_pp0_it1[10] <= tmp_7_reg_1500[10];
ap_reg_ppstg_tmp_7_reg_1500_pp0_it1[11] <= tmp_7_reg_1500[11];
ap_reg_ppstg_tmp_7_reg_1500_pp0_it1[12] <= tmp_7_reg_1500[12];
ap_reg_ppstg_tmp_7_reg_1500_pp0_it1[13] <= tmp_7_reg_1500[13];
end
if ((ap_ST_pp0_stg1_fsm_3 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_9_reg_1512_pp0_it1[0] <= tmp_9_reg_1512[0];
ap_reg_ppstg_tmp_9_reg_1512_pp0_it1[1] <= tmp_9_reg_1512[1];
ap_reg_ppstg_tmp_9_reg_1512_pp0_it1[2] <= tmp_9_reg_1512[2];
ap_reg_ppstg_tmp_9_reg_1512_pp0_it1[3] <= tmp_9_reg_1512[3];
ap_reg_ppstg_tmp_9_reg_1512_pp0_it1[4] <= tmp_9_reg_1512[4];
ap_reg_ppstg_tmp_9_reg_1512_pp0_it1[5] <= tmp_9_reg_1512[5];
ap_reg_ppstg_tmp_9_reg_1512_pp0_it1[6] <= tmp_9_reg_1512[6];
ap_reg_ppstg_tmp_9_reg_1512_pp0_it1[7] <= tmp_9_reg_1512[7];
ap_reg_ppstg_tmp_9_reg_1512_pp0_it1[8] <= tmp_9_reg_1512[8];
ap_reg_ppstg_tmp_9_reg_1512_pp0_it1[9] <= tmp_9_reg_1512[9];
ap_reg_ppstg_tmp_9_reg_1512_pp0_it1[10] <= tmp_9_reg_1512[10];
ap_reg_ppstg_tmp_9_reg_1512_pp0_it1[11] <= tmp_9_reg_1512[11];
ap_reg_ppstg_tmp_9_reg_1512_pp0_it1[12] <= tmp_9_reg_1512[12];
ap_reg_ppstg_tmp_9_reg_1512_pp0_it1[13] <= tmp_9_reg_1512[13];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond2_reg_1603) & (ap_ST_pp1_stg3_fsm_14 == ap_CS_fsm))) begin
b_addr17_reg_1784[3] <= b_addr17_fu_1406_p2[3];
b_addr17_reg_1784[4] <= b_addr17_fu_1406_p2[4];
b_addr17_reg_1784[5] <= b_addr17_fu_1406_p2[5];
b_addr17_reg_1784[6] <= b_addr17_fu_1406_p2[6];
b_addr17_reg_1784[7] <= b_addr17_fu_1406_p2[7];
b_addr17_reg_1784[8] <= b_addr17_fu_1406_p2[8];
b_addr17_reg_1784[9] <= b_addr17_fu_1406_p2[9];
b_addr17_reg_1784[10] <= b_addr17_fu_1406_p2[10];
b_addr17_reg_1784[11] <= b_addr17_fu_1406_p2[11];
b_addr17_reg_1784[12] <= b_addr17_fu_1406_p2[12];
b_addr17_reg_1784[13] <= b_addr17_fu_1406_p2[13];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_reg_1446 == ap_const_lv1_0) & (ap_ST_pp0_stg3_fsm_5 == ap_CS_fsm))) begin
b_addr8_reg_1572[3] <= b_addr8_fu_1163_p2[3];
b_addr8_reg_1572[4] <= b_addr8_fu_1163_p2[4];
b_addr8_reg_1572[5] <= b_addr8_fu_1163_p2[5];
b_addr8_reg_1572[6] <= b_addr8_fu_1163_p2[6];
b_addr8_reg_1572[7] <= b_addr8_fu_1163_p2[7];
b_addr8_reg_1572[8] <= b_addr8_fu_1163_p2[8];
b_addr8_reg_1572[9] <= b_addr8_fu_1163_p2[9];
b_addr8_reg_1572[10] <= b_addr8_fu_1163_p2[10];
b_addr8_reg_1572[11] <= b_addr8_fu_1163_p2[11];
b_addr8_reg_1572[12] <= b_addr8_fu_1163_p2[12];
b_addr8_reg_1572[13] <= b_addr8_fu_1163_p2[13];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_ST_pp1_stg0_fsm_11 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond2_fu_1193_p2))) begin
b_addr9_cast_reg_1629[6] <= b_addr9_cast_fu_1247_p1[6];
b_addr9_cast_reg_1629[7] <= b_addr9_cast_fu_1247_p1[7];
b_addr9_cast_reg_1629[8] <= b_addr9_cast_fu_1247_p1[8];
b_addr9_cast_reg_1629[9] <= b_addr9_cast_fu_1247_p1[9];
b_addr9_cast_reg_1629[10] <= b_addr9_cast_fu_1247_p1[10];
b_addr9_cast_reg_1629[11] <= b_addr9_cast_fu_1247_p1[11];
b_addr9_cast_reg_1629[12] <= b_addr9_cast_fu_1247_p1[12];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond_fu_957_p2))) begin
b_addr_cast_reg_1472[6] <= b_addr_cast_fu_1011_p1[6];
b_addr_cast_reg_1472[7] <= b_addr_cast_fu_1011_p1[7];
b_addr_cast_reg_1472[8] <= b_addr_cast_fu_1011_p1[8];
b_addr_cast_reg_1472[9] <= b_addr_cast_fu_1011_p1[9];
b_addr_cast_reg_1472[10] <= b_addr_cast_fu_1011_p1[10];
b_addr_cast_reg_1472[11] <= b_addr_cast_fu_1011_p1[11];
b_addr_cast_reg_1472[12] <= b_addr_cast_fu_1011_p1[12];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond2_reg_1603) & (ap_ST_pp1_stg5_fsm_16 == ap_CS_fsm))) begin
b_load_15_reg_1821 <= b_q0;
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond2_reg_1603) & (ap_ST_pp1_stg2_fsm_13 == ap_CS_fsm))) begin
c_load_1_reg_1696 <= c_q0;
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond2_reg_1603) & (ap_ST_pp1_stg2_fsm_13 == ap_CS_fsm))) begin
c_load_2_reg_1701 <= c_q1;
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond2_reg_1603) & (ap_ST_pp1_stg3_fsm_14 == ap_CS_fsm))) begin
c_load_3_reg_1740 <= c_q0;
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond2_reg_1603) & (ap_ST_pp1_stg3_fsm_14 == ap_CS_fsm))) begin
c_load_4_reg_1745 <= c_q1;
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond2_reg_1603) & (ap_ST_pp1_stg4_fsm_15 == ap_CS_fsm))) begin
c_load_5_reg_1794 <= c_q0;
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond2_reg_1603) & (ap_ST_pp1_stg4_fsm_15 == ap_CS_fsm))) begin
c_load_6_reg_1799 <= c_q1;
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_ST_pp1_stg0_fsm_11 == ap_CS_fsm))) begin
exitcond2_reg_1603 <= (indvar_flatten9_phi_fu_770_p4 == ap_const_lv10_200? 1'b1: 1'b0);
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm))) begin
exitcond_reg_1446 <= (indvar_flatten_phi_fu_726_p4 == ap_const_lv10_200? 1'b1: 1'b0);
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_ST_pp1_stg0_fsm_11 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond2_fu_1193_p2))) begin
if (exitcond3_fu_1205_p2) begin
i1_mid2_reg_1624 <= tmp_31_dup_fu_1219_p2;
end else begin
i1_mid2_reg_1624 <= i1_phi_fu_781_p4;
end
end
if (((ap_ST_st17_fsm_10 == ap_CS_fsm) & ~(ap_const_lv1_0 == or_cond1_fu_1187_p2))) begin
i1_reg_777 <= ap_const_lv7_0;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_const_lv1_0 == exitcond2_reg_1603) & (ap_ST_pp1_stg0_fsm_11 == ap_CS_fsm))) begin
i1_reg_777 <= i1_mid2_reg_1624;
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond_fu_957_p2))) begin
if (exitcond1_fu_969_p2) begin
i_mid2_reg_1467 <= tmp_6_dup_fu_983_p2;
end else begin
i_mid2_reg_1467 <= i_phi_fu_737_p4;
end
end
if (((ap_ST_st1_fsm_1 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_2_fu_951_p2))) begin
i_reg_733 <= ap_const_lv7_0;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (exitcond_reg_1446 == ap_const_lv1_0) & (ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm))) begin
i_reg_733 <= i_mid2_reg_1467;
end
if (((ap_ST_st1_fsm_1 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_2_fu_951_p2))) begin
indvar3_reg_744 <= ap_const_lv4_0;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (exitcond_reg_1446 == ap_const_lv1_0) & (ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm))) begin
indvar3_reg_744 <= indvar_next4_reg_1495;
end
if (((ap_ST_st17_fsm_10 == ap_CS_fsm) & ~(ap_const_lv1_0 == or_cond1_fu_1187_p2))) begin
indvar_flatten9_reg_766 <= ap_const_lv10_0;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_const_lv1_0 == exitcond2_reg_1603) & (ap_ST_pp1_stg0_fsm_11 == ap_CS_fsm))) begin
indvar_flatten9_reg_766 <= indvar_flatten_next1_reg_1607;
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_ST_pp1_stg0_fsm_11 == ap_CS_fsm))) begin
indvar_flatten_next1_reg_1607 <= (indvar_flatten9_phi_fu_770_p4 + ap_const_lv10_1);
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm))) begin
indvar_flatten_next_reg_1450 <= (indvar_flatten_phi_fu_726_p4 + ap_const_lv10_1);
end
if (((ap_ST_st1_fsm_1 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_2_fu_951_p2))) begin
indvar_flatten_reg_722 <= ap_const_lv10_0;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (exitcond_reg_1446 == ap_const_lv1_0) & (ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm))) begin
indvar_flatten_reg_722 <= indvar_flatten_next_reg_1450;
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond_fu_957_p2))) begin
if (exitcond1_fu_969_p2) begin
indvar_next4_reg_1495 <= ap_const_lv4_1;
end else begin
indvar_next4_reg_1495 <= indvar3_op_fu_1026_p2;
end
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_ST_pp1_stg0_fsm_11 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond2_fu_1193_p2))) begin
if (exitcond3_fu_1205_p2) begin
indvar_next_reg_1657 <= ap_const_lv4_1;
end else begin
indvar_next_reg_1657 <= indvar_op_fu_1263_p2;
end
end
if (((ap_ST_st17_fsm_10 == ap_CS_fsm) & ~(ap_const_lv1_0 == or_cond1_fu_1187_p2))) begin
indvar_reg_788 <= ap_const_lv4_0;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_const_lv1_0 == exitcond2_reg_1603) & (ap_ST_pp1_stg0_fsm_11 == ap_CS_fsm))) begin
indvar_reg_788 <= indvar_next_reg_1657;
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_ST_pp1_stg0_fsm_11 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond2_fu_1193_p2))) begin
if (exitcond3_fu_1205_p2) begin
j1_mid2_reg_1612 <= ap_const_lv7_0;
end else begin
j1_mid2_reg_1612 <= j1_phi_fu_803_p4;
end
end
if (((ap_ST_st17_fsm_10 == ap_CS_fsm) & ~(ap_const_lv1_0 == or_cond1_fu_1187_p2))) begin
j1_reg_799 <= ap_const_lv7_0;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_const_lv1_0 == exitcond2_reg_1603) & (ap_ST_pp1_stg0_fsm_11 == ap_CS_fsm))) begin
j1_reg_799 <= tmp_61_reg_1789;
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond_fu_957_p2))) begin
if (exitcond1_fu_969_p2) begin
j_mid2_reg_1455 <= ap_const_lv7_0;
end else begin
j_mid2_reg_1455 <= j_phi_fu_759_p4;
end
end
if (((ap_ST_st1_fsm_1 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_2_fu_951_p2))) begin
j_reg_755 <= ap_const_lv7_0;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (exitcond_reg_1446 == ap_const_lv1_0) & (ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm))) begin
j_reg_755 <= tmp_28_reg_1577;
end
if ((ap_ST_st1_fsm_1 == ap_CS_fsm)) begin
or_cond_reg_1433 <= (tmp_fu_933_p2 & tmp_1_fu_939_p2);
end
if ((((ap_ST_pp0_stg1_fsm_3 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_reg_1446 == ap_const_lv1_0)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_reg_1446 == ap_const_lv1_0) & (ap_ST_pp0_stg5_fsm_7 == ap_CS_fsm)) | ((ap_ST_pp1_stg1_fsm_12 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond2_reg_1603)))) begin
reg_823 <= b_q0;
end
if ((((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_reg_1446 == ap_const_lv1_0) & (ap_ST_pp0_stg2_fsm_4 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond2_reg_1603) & (ap_ST_pp1_stg2_fsm_13 == ap_CS_fsm)))) begin
reg_829 <= b_q0;
end
if ((((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_reg_1446 == ap_const_lv1_0) & (ap_ST_pp0_stg2_fsm_4 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond2_reg_1603) & (ap_ST_pp1_stg2_fsm_13 == ap_CS_fsm)))) begin
reg_835 <= b_q1;
end
if ((((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_reg_1446 == ap_const_lv1_0) & (ap_ST_pp0_stg3_fsm_5 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond2_reg_1603) & (ap_ST_pp1_stg3_fsm_14 == ap_CS_fsm)))) begin
reg_841 <= b_q0;
end
if ((((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_reg_1446 == ap_const_lv1_0) & (ap_ST_pp0_stg3_fsm_5 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond2_reg_1603) & (ap_ST_pp1_stg3_fsm_14 == ap_CS_fsm)))) begin
reg_847 <= b_q1;
end
if ((((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_reg_1446 == ap_const_lv1_0) & (ap_ST_pp0_stg4_fsm_6 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond2_reg_1603) & (ap_ST_pp1_stg4_fsm_15 == ap_CS_fsm)))) begin
reg_853 <= b_q0;
end
if ((((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_reg_1446 == ap_const_lv1_0) & (ap_ST_pp0_stg4_fsm_6 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond2_reg_1603) & (ap_ST_pp1_stg4_fsm_15 == ap_CS_fsm)))) begin
reg_859 <= b_q1;
end
if ((((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_reg_1446 == ap_const_lv1_0) & (ap_ST_pp0_stg5_fsm_7 == ap_CS_fsm)) | ((ap_ST_pp0_stg1_fsm_3 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_1446_pp0_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond2_reg_1603) & (ap_ST_pp1_stg5_fsm_16 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it2) & (ap_ST_pp1_stg2_fsm_13 == ap_CS_fsm) & ~(ap_const_lv1_0 == or_cond_reg_1433) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it2)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it2) & (ap_ST_pp1_stg3_fsm_14 == ap_CS_fsm) & ~(ap_const_lv1_0 == or_cond_reg_1433) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it2)))) begin
reg_865 <= grp_fu_815_p2;
end
if ((((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_reg_1446 == ap_const_lv1_0) & (ap_ST_pp0_stg6_fsm_8 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (ap_ST_pp0_stg2_fsm_4 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_1446_pp0_it1) & ~(ap_const_lv1_0 == or_cond_reg_1433)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (ap_ST_pp0_stg3_fsm_5 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_1446_pp0_it1) & ~(ap_const_lv1_0 == or_cond_reg_1433)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (ap_ST_pp0_stg4_fsm_6 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_1446_pp0_it1) & ~(ap_const_lv1_0 == or_cond_reg_1433)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond2_reg_1603) & (ap_ST_pp1_stg6_fsm_17 == ap_CS_fsm)))) begin
reg_874 <= grp_fu_815_p2;
end
if ((((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_reg_1446 == ap_const_lv1_0) & (ap_ST_pp0_stg6_fsm_8 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (ap_ST_pp0_stg2_fsm_4 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_1446_pp0_it1) & ~(ap_const_lv1_0 == or_cond_reg_1433)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (ap_ST_pp0_stg3_fsm_5 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_1446_pp0_it1) & ~(ap_const_lv1_0 == or_cond_reg_1433)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (ap_ST_pp0_stg4_fsm_6 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_1446_pp0_it1) & ~(ap_const_lv1_0 == or_cond_reg_1433)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond2_reg_1603) & (ap_ST_pp1_stg6_fsm_17 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (ap_ST_pp0_stg5_fsm_7 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_1446_pp0_it1) & ~(ap_const_lv1_0 == or_cond_reg_1433)))) begin
reg_882 <= grp_fu_819_p2;
end
if ((((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_reg_1446 == ap_const_lv1_0) & (ap_ST_pp0_stg7_fsm_9 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond2_reg_1603) & (ap_ST_pp1_stg7_fsm_18 == ap_CS_fsm)))) begin
reg_890 <= grp_fu_815_p2;
end
if ((((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_reg_1446 == ap_const_lv1_0) & (ap_ST_pp0_stg7_fsm_9 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond2_reg_1603) & (ap_ST_pp1_stg7_fsm_18 == ap_CS_fsm)))) begin
reg_898 <= grp_fu_819_p2;
end
if ((((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (exitcond_reg_1446 == ap_const_lv1_0) & (ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_const_lv1_0 == exitcond2_reg_1603) & (ap_ST_pp1_stg0_fsm_11 == ap_CS_fsm)))) begin
reg_906 <= grp_fu_815_p2;
end
if ((((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (exitcond_reg_1446 == ap_const_lv1_0) & (ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_const_lv1_0 == exitcond2_reg_1603) & (ap_ST_pp1_stg0_fsm_11 == ap_CS_fsm)))) begin
reg_914 <= grp_fu_819_p2;
end
if ((((ap_const_logic_1 == ap_reg_ppiten_pp1_it2) & (ap_ST_pp1_stg2_fsm_13 == ap_CS_fsm) & ~(ap_const_lv1_0 == or_cond_reg_1433) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it2)) | ((ap_ST_pp0_stg1_fsm_3 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_1446_pp0_it1) & ~(ap_const_lv1_0 == or_cond_reg_1433)) | ((ap_ST_pp1_stg1_fsm_12 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it2) & ~(ap_const_lv1_0 == or_cond_reg_1433) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it2)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it2) & (ap_ST_pp1_stg4_fsm_15 == ap_CS_fsm) & ~(ap_const_lv1_0 == or_cond_reg_1433) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it2)))) begin
reg_922 <= grp_fu_819_p2;
end
if ((((ap_ST_pp1_stg1_fsm_12 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond2_reg_1603)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond2_reg_1603) & (ap_ST_pp1_stg5_fsm_16 == ap_CS_fsm)))) begin
reg_928 <= c_q0;
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_ST_pp1_stg5_fsm_16 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it1))) begin
t10_reg_1852 <= grp_fu_811_p2;
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_ST_pp1_stg6_fsm_17 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it1))) begin
t11_reg_1859 <= grp_fu_811_p2;
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_ST_pp1_stg7_fsm_18 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it1))) begin
t12_reg_1866 <= grp_fu_811_p2;
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it2) & (ap_ST_pp1_stg0_fsm_11 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it1))) begin
t13_reg_1873 <= grp_fu_811_p2;
end
if (((ap_ST_pp1_stg1_fsm_12 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it2) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it2))) begin
t14_reg_1880 <= grp_fu_811_p2;
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_ST_pp1_stg3_fsm_14 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it1))) begin
t8_reg_1838 <= grp_fu_811_p2;
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_ST_pp1_stg4_fsm_15 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it1))) begin
t9_reg_1845 <= grp_fu_811_p2;
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_ST_pp1_stg2_fsm_13 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it1))) begin
t_reg_1831 <= grp_fu_811_p2;
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_reg_1446 == ap_const_lv1_0) & (ap_ST_pp0_stg2_fsm_4 == ap_CS_fsm))) begin
tmp_11_reg_1524[2] <= tmp_11_fu_1092_p1[2];
tmp_11_reg_1524[3] <= tmp_11_fu_1092_p1[3];
tmp_11_reg_1524[4] <= tmp_11_fu_1092_p1[4];
tmp_11_reg_1524[5] <= tmp_11_fu_1092_p1[5];
tmp_11_reg_1524[6] <= tmp_11_fu_1092_p1[6];
tmp_11_reg_1524[7] <= tmp_11_fu_1092_p1[7];
tmp_11_reg_1524[8] <= tmp_11_fu_1092_p1[8];
tmp_11_reg_1524[9] <= tmp_11_fu_1092_p1[9];
tmp_11_reg_1524[10] <= tmp_11_fu_1092_p1[10];
tmp_11_reg_1524[11] <= tmp_11_fu_1092_p1[11];
tmp_11_reg_1524[12] <= tmp_11_fu_1092_p1[12];
tmp_11_reg_1524[13] <= tmp_11_fu_1092_p1[13];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_reg_1446 == ap_const_lv1_0) & (ap_ST_pp0_stg2_fsm_4 == ap_CS_fsm))) begin
tmp_13_reg_1536[0] <= tmp_13_fu_1111_p1[0];
tmp_13_reg_1536[1] <= tmp_13_fu_1111_p1[1];
tmp_13_reg_1536[2] <= tmp_13_fu_1111_p1[2];
tmp_13_reg_1536[3] <= tmp_13_fu_1111_p1[3];
tmp_13_reg_1536[4] <= tmp_13_fu_1111_p1[4];
tmp_13_reg_1536[5] <= tmp_13_fu_1111_p1[5];
tmp_13_reg_1536[6] <= tmp_13_fu_1111_p1[6];
tmp_13_reg_1536[7] <= tmp_13_fu_1111_p1[7];
tmp_13_reg_1536[8] <= tmp_13_fu_1111_p1[8];
tmp_13_reg_1536[9] <= tmp_13_fu_1111_p1[9];
tmp_13_reg_1536[10] <= tmp_13_fu_1111_p1[10];
tmp_13_reg_1536[11] <= tmp_13_fu_1111_p1[11];
tmp_13_reg_1536[12] <= tmp_13_fu_1111_p1[12];
tmp_13_reg_1536[13] <= tmp_13_fu_1111_p1[13];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_reg_1446 == ap_const_lv1_0) & (ap_ST_pp0_stg3_fsm_5 == ap_CS_fsm))) begin
tmp_15_reg_1548[1] <= tmp_15_fu_1130_p1[1];
tmp_15_reg_1548[2] <= tmp_15_fu_1130_p1[2];
tmp_15_reg_1548[3] <= tmp_15_fu_1130_p1[3];
tmp_15_reg_1548[4] <= tmp_15_fu_1130_p1[4];
tmp_15_reg_1548[5] <= tmp_15_fu_1130_p1[5];
tmp_15_reg_1548[6] <= tmp_15_fu_1130_p1[6];
tmp_15_reg_1548[7] <= tmp_15_fu_1130_p1[7];
tmp_15_reg_1548[8] <= tmp_15_fu_1130_p1[8];
tmp_15_reg_1548[9] <= tmp_15_fu_1130_p1[9];
tmp_15_reg_1548[10] <= tmp_15_fu_1130_p1[10];
tmp_15_reg_1548[11] <= tmp_15_fu_1130_p1[11];
tmp_15_reg_1548[12] <= tmp_15_fu_1130_p1[12];
tmp_15_reg_1548[13] <= tmp_15_fu_1130_p1[13];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_reg_1446 == ap_const_lv1_0) & (ap_ST_pp0_stg3_fsm_5 == ap_CS_fsm))) begin
tmp_17_reg_1560[0] <= tmp_17_fu_1149_p1[0];
tmp_17_reg_1560[1] <= tmp_17_fu_1149_p1[1];
tmp_17_reg_1560[2] <= tmp_17_fu_1149_p1[2];
tmp_17_reg_1560[3] <= tmp_17_fu_1149_p1[3];
tmp_17_reg_1560[4] <= tmp_17_fu_1149_p1[4];
tmp_17_reg_1560[5] <= tmp_17_fu_1149_p1[5];
tmp_17_reg_1560[6] <= tmp_17_fu_1149_p1[6];
tmp_17_reg_1560[7] <= tmp_17_fu_1149_p1[7];
tmp_17_reg_1560[8] <= tmp_17_fu_1149_p1[8];
tmp_17_reg_1560[9] <= tmp_17_fu_1149_p1[9];
tmp_17_reg_1560[10] <= tmp_17_fu_1149_p1[10];
tmp_17_reg_1560[11] <= tmp_17_fu_1149_p1[11];
tmp_17_reg_1560[12] <= tmp_17_fu_1149_p1[12];
tmp_17_reg_1560[13] <= tmp_17_fu_1149_p1[13];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_reg_1446 == ap_const_lv1_0) & (ap_ST_pp0_stg4_fsm_6 == ap_CS_fsm))) begin
tmp_19_reg_1582[3] <= tmp_19_fu_1173_p1[3];
tmp_19_reg_1582[4] <= tmp_19_fu_1173_p1[4];
tmp_19_reg_1582[5] <= tmp_19_fu_1173_p1[5];
tmp_19_reg_1582[6] <= tmp_19_fu_1173_p1[6];
tmp_19_reg_1582[7] <= tmp_19_fu_1173_p1[7];
tmp_19_reg_1582[8] <= tmp_19_fu_1173_p1[8];
tmp_19_reg_1582[9] <= tmp_19_fu_1173_p1[9];
tmp_19_reg_1582[10] <= tmp_19_fu_1173_p1[10];
tmp_19_reg_1582[11] <= tmp_19_fu_1173_p1[11];
tmp_19_reg_1582[12] <= tmp_19_fu_1173_p1[12];
tmp_19_reg_1582[13] <= tmp_19_fu_1173_p1[13];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_reg_1446 == ap_const_lv1_0) & (ap_ST_pp0_stg3_fsm_5 == ap_CS_fsm))) begin
tmp_28_reg_1577 <= (j_mid2_reg_1455 + ap_const_lv7_8);
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_ST_pp1_stg0_fsm_11 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond2_fu_1193_p2))) begin
tmp_30_reg_1640[0] <= tmp_30_fu_1257_p1[0];
tmp_30_reg_1640[1] <= tmp_30_fu_1257_p1[1];
tmp_30_reg_1640[2] <= tmp_30_fu_1257_p1[2];
tmp_30_reg_1640[3] <= tmp_30_fu_1257_p1[3];
tmp_30_reg_1640[4] <= tmp_30_fu_1257_p1[4];
tmp_30_reg_1640[5] <= tmp_30_fu_1257_p1[5];
tmp_30_reg_1640[6] <= tmp_30_fu_1257_p1[6];
tmp_30_reg_1640[7] <= tmp_30_fu_1257_p1[7];
tmp_30_reg_1640[8] <= tmp_30_fu_1257_p1[8];
tmp_30_reg_1640[9] <= tmp_30_fu_1257_p1[9];
tmp_30_reg_1640[10] <= tmp_30_fu_1257_p1[10];
tmp_30_reg_1640[11] <= tmp_30_fu_1257_p1[11];
tmp_30_reg_1640[12] <= tmp_30_fu_1257_p1[12];
tmp_30_reg_1640[13] <= tmp_30_fu_1257_p1[13];
end
if (((ap_ST_pp1_stg1_fsm_12 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond2_reg_1603))) begin
tmp_33_reg_1662[1] <= tmp_33_fu_1291_p1[1];
tmp_33_reg_1662[2] <= tmp_33_fu_1291_p1[2];
tmp_33_reg_1662[3] <= tmp_33_fu_1291_p1[3];
tmp_33_reg_1662[4] <= tmp_33_fu_1291_p1[4];
tmp_33_reg_1662[5] <= tmp_33_fu_1291_p1[5];
tmp_33_reg_1662[6] <= tmp_33_fu_1291_p1[6];
tmp_33_reg_1662[7] <= tmp_33_fu_1291_p1[7];
tmp_33_reg_1662[8] <= tmp_33_fu_1291_p1[8];
tmp_33_reg_1662[9] <= tmp_33_fu_1291_p1[9];
tmp_33_reg_1662[10] <= tmp_33_fu_1291_p1[10];
tmp_33_reg_1662[11] <= tmp_33_fu_1291_p1[11];
tmp_33_reg_1662[12] <= tmp_33_fu_1291_p1[12];
tmp_33_reg_1662[13] <= tmp_33_fu_1291_p1[13];
end
if (((ap_ST_pp1_stg1_fsm_12 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond2_reg_1603))) begin
tmp_36_reg_1679[0] <= tmp_36_fu_1311_p1[0];
tmp_36_reg_1679[1] <= tmp_36_fu_1311_p1[1];
tmp_36_reg_1679[2] <= tmp_36_fu_1311_p1[2];
tmp_36_reg_1679[3] <= tmp_36_fu_1311_p1[3];
tmp_36_reg_1679[4] <= tmp_36_fu_1311_p1[4];
tmp_36_reg_1679[5] <= tmp_36_fu_1311_p1[5];
tmp_36_reg_1679[6] <= tmp_36_fu_1311_p1[6];
tmp_36_reg_1679[7] <= tmp_36_fu_1311_p1[7];
tmp_36_reg_1679[8] <= tmp_36_fu_1311_p1[8];
tmp_36_reg_1679[9] <= tmp_36_fu_1311_p1[9];
tmp_36_reg_1679[10] <= tmp_36_fu_1311_p1[10];
tmp_36_reg_1679[11] <= tmp_36_fu_1311_p1[11];
tmp_36_reg_1679[12] <= tmp_36_fu_1311_p1[12];
tmp_36_reg_1679[13] <= tmp_36_fu_1311_p1[13];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond2_reg_1603) & (ap_ST_pp1_stg2_fsm_13 == ap_CS_fsm))) begin
tmp_39_reg_1706[2] <= tmp_39_fu_1331_p1[2];
tmp_39_reg_1706[3] <= tmp_39_fu_1331_p1[3];
tmp_39_reg_1706[4] <= tmp_39_fu_1331_p1[4];
tmp_39_reg_1706[5] <= tmp_39_fu_1331_p1[5];
tmp_39_reg_1706[6] <= tmp_39_fu_1331_p1[6];
tmp_39_reg_1706[7] <= tmp_39_fu_1331_p1[7];
tmp_39_reg_1706[8] <= tmp_39_fu_1331_p1[8];
tmp_39_reg_1706[9] <= tmp_39_fu_1331_p1[9];
tmp_39_reg_1706[10] <= tmp_39_fu_1331_p1[10];
tmp_39_reg_1706[11] <= tmp_39_fu_1331_p1[11];
tmp_39_reg_1706[12] <= tmp_39_fu_1331_p1[12];
tmp_39_reg_1706[13] <= tmp_39_fu_1331_p1[13];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond2_reg_1603) & (ap_ST_pp1_stg2_fsm_13 == ap_CS_fsm))) begin
tmp_42_reg_1723[0] <= tmp_42_fu_1351_p1[0];
tmp_42_reg_1723[1] <= tmp_42_fu_1351_p1[1];
tmp_42_reg_1723[2] <= tmp_42_fu_1351_p1[2];
tmp_42_reg_1723[3] <= tmp_42_fu_1351_p1[3];
tmp_42_reg_1723[4] <= tmp_42_fu_1351_p1[4];
tmp_42_reg_1723[5] <= tmp_42_fu_1351_p1[5];
tmp_42_reg_1723[6] <= tmp_42_fu_1351_p1[6];
tmp_42_reg_1723[7] <= tmp_42_fu_1351_p1[7];
tmp_42_reg_1723[8] <= tmp_42_fu_1351_p1[8];
tmp_42_reg_1723[9] <= tmp_42_fu_1351_p1[9];
tmp_42_reg_1723[10] <= tmp_42_fu_1351_p1[10];
tmp_42_reg_1723[11] <= tmp_42_fu_1351_p1[11];
tmp_42_reg_1723[12] <= tmp_42_fu_1351_p1[12];
tmp_42_reg_1723[13] <= tmp_42_fu_1351_p1[13];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond2_reg_1603) & (ap_ST_pp1_stg3_fsm_14 == ap_CS_fsm))) begin
tmp_45_reg_1750[1] <= tmp_45_fu_1371_p1[1];
tmp_45_reg_1750[2] <= tmp_45_fu_1371_p1[2];
tmp_45_reg_1750[3] <= tmp_45_fu_1371_p1[3];
tmp_45_reg_1750[4] <= tmp_45_fu_1371_p1[4];
tmp_45_reg_1750[5] <= tmp_45_fu_1371_p1[5];
tmp_45_reg_1750[6] <= tmp_45_fu_1371_p1[6];
tmp_45_reg_1750[7] <= tmp_45_fu_1371_p1[7];
tmp_45_reg_1750[8] <= tmp_45_fu_1371_p1[8];
tmp_45_reg_1750[9] <= tmp_45_fu_1371_p1[9];
tmp_45_reg_1750[10] <= tmp_45_fu_1371_p1[10];
tmp_45_reg_1750[11] <= tmp_45_fu_1371_p1[11];
tmp_45_reg_1750[12] <= tmp_45_fu_1371_p1[12];
tmp_45_reg_1750[13] <= tmp_45_fu_1371_p1[13];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond2_reg_1603) & (ap_ST_pp1_stg3_fsm_14 == ap_CS_fsm))) begin
tmp_48_reg_1767[0] <= tmp_48_fu_1391_p1[0];
tmp_48_reg_1767[1] <= tmp_48_fu_1391_p1[1];
tmp_48_reg_1767[2] <= tmp_48_fu_1391_p1[2];
tmp_48_reg_1767[3] <= tmp_48_fu_1391_p1[3];
tmp_48_reg_1767[4] <= tmp_48_fu_1391_p1[4];
tmp_48_reg_1767[5] <= tmp_48_fu_1391_p1[5];
tmp_48_reg_1767[6] <= tmp_48_fu_1391_p1[6];
tmp_48_reg_1767[7] <= tmp_48_fu_1391_p1[7];
tmp_48_reg_1767[8] <= tmp_48_fu_1391_p1[8];
tmp_48_reg_1767[9] <= tmp_48_fu_1391_p1[9];
tmp_48_reg_1767[10] <= tmp_48_fu_1391_p1[10];
tmp_48_reg_1767[11] <= tmp_48_fu_1391_p1[11];
tmp_48_reg_1767[12] <= tmp_48_fu_1391_p1[12];
tmp_48_reg_1767[13] <= tmp_48_fu_1391_p1[13];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond2_reg_1603) & (ap_ST_pp1_stg4_fsm_15 == ap_CS_fsm))) begin
tmp_51_reg_1804[3] <= tmp_51_fu_1416_p1[3];
tmp_51_reg_1804[4] <= tmp_51_fu_1416_p1[4];
tmp_51_reg_1804[5] <= tmp_51_fu_1416_p1[5];
tmp_51_reg_1804[6] <= tmp_51_fu_1416_p1[6];
tmp_51_reg_1804[7] <= tmp_51_fu_1416_p1[7];
tmp_51_reg_1804[8] <= tmp_51_fu_1416_p1[8];
tmp_51_reg_1804[9] <= tmp_51_fu_1416_p1[9];
tmp_51_reg_1804[10] <= tmp_51_fu_1416_p1[10];
tmp_51_reg_1804[11] <= tmp_51_fu_1416_p1[11];
tmp_51_reg_1804[12] <= tmp_51_fu_1416_p1[12];
tmp_51_reg_1804[13] <= tmp_51_fu_1416_p1[13];
end
if (((ap_ST_pp1_stg1_fsm_12 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it1))) begin
tmp_52_reg_1826 <= grp_fu_815_p2;
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it2) & (ap_ST_pp1_stg3_fsm_14 == ap_CS_fsm) & ~(ap_const_lv1_0 == or_cond_reg_1433) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it2))) begin
tmp_57_reg_1887 <= grp_fu_819_p2;
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it2) & (ap_ST_pp1_stg4_fsm_15 == ap_CS_fsm) & ~(ap_const_lv1_0 == or_cond_reg_1433) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it2))) begin
tmp_58_reg_1892 <= grp_fu_815_p2;
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it2) & (ap_ST_pp1_stg5_fsm_16 == ap_CS_fsm) & ~(ap_const_lv1_0 == or_cond_reg_1433) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it2))) begin
tmp_60_reg_1897 <= grp_fu_819_p2;
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond2_reg_1603) & (ap_ST_pp1_stg3_fsm_14 == ap_CS_fsm))) begin
tmp_61_reg_1789 <= (j1_mid2_reg_1612 + ap_const_lv7_8);
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond_fu_957_p2))) begin
tmp_6_reg_1483[0] <= tmp_6_fu_1021_p1[0];
tmp_6_reg_1483[1] <= tmp_6_fu_1021_p1[1];
tmp_6_reg_1483[2] <= tmp_6_fu_1021_p1[2];
tmp_6_reg_1483[3] <= tmp_6_fu_1021_p1[3];
tmp_6_reg_1483[4] <= tmp_6_fu_1021_p1[4];
tmp_6_reg_1483[5] <= tmp_6_fu_1021_p1[5];
tmp_6_reg_1483[6] <= tmp_6_fu_1021_p1[6];
tmp_6_reg_1483[7] <= tmp_6_fu_1021_p1[7];
tmp_6_reg_1483[8] <= tmp_6_fu_1021_p1[8];
tmp_6_reg_1483[9] <= tmp_6_fu_1021_p1[9];
tmp_6_reg_1483[10] <= tmp_6_fu_1021_p1[10];
tmp_6_reg_1483[11] <= tmp_6_fu_1021_p1[11];
tmp_6_reg_1483[12] <= tmp_6_fu_1021_p1[12];
tmp_6_reg_1483[13] <= tmp_6_fu_1021_p1[13];
end
if (((ap_ST_pp0_stg1_fsm_3 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_reg_1446 == ap_const_lv1_0))) begin
tmp_7_reg_1500[1] <= tmp_7_fu_1054_p1[1];
tmp_7_reg_1500[2] <= tmp_7_fu_1054_p1[2];
tmp_7_reg_1500[3] <= tmp_7_fu_1054_p1[3];
tmp_7_reg_1500[4] <= tmp_7_fu_1054_p1[4];
tmp_7_reg_1500[5] <= tmp_7_fu_1054_p1[5];
tmp_7_reg_1500[6] <= tmp_7_fu_1054_p1[6];
tmp_7_reg_1500[7] <= tmp_7_fu_1054_p1[7];
tmp_7_reg_1500[8] <= tmp_7_fu_1054_p1[8];
tmp_7_reg_1500[9] <= tmp_7_fu_1054_p1[9];
tmp_7_reg_1500[10] <= tmp_7_fu_1054_p1[10];
tmp_7_reg_1500[11] <= tmp_7_fu_1054_p1[11];
tmp_7_reg_1500[12] <= tmp_7_fu_1054_p1[12];
tmp_7_reg_1500[13] <= tmp_7_fu_1054_p1[13];
end
if (((ap_ST_pp0_stg1_fsm_3 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_reg_1446 == ap_const_lv1_0))) begin
tmp_9_reg_1512[0] <= tmp_9_fu_1073_p1[0];
tmp_9_reg_1512[1] <= tmp_9_fu_1073_p1[1];
tmp_9_reg_1512[2] <= tmp_9_fu_1073_p1[2];
tmp_9_reg_1512[3] <= tmp_9_fu_1073_p1[3];
tmp_9_reg_1512[4] <= tmp_9_fu_1073_p1[4];
tmp_9_reg_1512[5] <= tmp_9_fu_1073_p1[5];
tmp_9_reg_1512[6] <= tmp_9_fu_1073_p1[6];
tmp_9_reg_1512[7] <= tmp_9_fu_1073_p1[7];
tmp_9_reg_1512[8] <= tmp_9_fu_1073_p1[8];
tmp_9_reg_1512[9] <= tmp_9_fu_1073_p1[9];
tmp_9_reg_1512[10] <= tmp_9_fu_1073_p1[10];
tmp_9_reg_1512[11] <= tmp_9_fu_1073_p1[11];
tmp_9_reg_1512[12] <= tmp_9_fu_1073_p1[12];
tmp_9_reg_1512[13] <= tmp_9_fu_1073_p1[13];
end
end
/// ap_NS_fsm assign process. ///
always @ (ap_start or ap_CS_fsm or ap_reg_ppiten_pp0_it0 or ap_reg_ppiten_pp0_it1 or ap_reg_ppiten_pp1_it0 or ap_reg_ppiten_pp1_it1 or ap_reg_ppiten_pp1_it2 or ap_reg_ppiten_pp1_it3 or tmp_2_fu_951_p2 or exitcond_fu_957_p2 or or_cond1_fu_1187_p2 or exitcond2_fu_1193_p2)
begin
if ((ap_ST_pp1_stg6_fsm_17 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_pp1_stg7_fsm_18;
end else if ((ap_ST_pp1_stg5_fsm_16 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_pp1_stg6_fsm_17;
end else if ((ap_ST_pp1_stg4_fsm_15 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_pp1_stg5_fsm_16;
end else if ((ap_ST_pp1_stg3_fsm_14 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_pp1_stg4_fsm_15;
end else if ((ap_ST_pp1_stg2_fsm_13 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_pp1_stg3_fsm_14;
end else if (((ap_ST_pp1_stg1_fsm_12 == ap_CS_fsm) & ~((ap_ST_pp1_stg1_fsm_12 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it3) & ~(ap_const_logic_1 == ap_reg_ppiten_pp1_it2)))) begin
ap_NS_fsm = ap_ST_pp1_stg2_fsm_13;
end else if (((ap_ST_pp1_stg0_fsm_11 == ap_CS_fsm) & ~((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & ~(ap_const_lv1_0 == exitcond2_fu_1193_p2) & ~(ap_const_logic_1 == ap_reg_ppiten_pp1_it1)))) begin
ap_NS_fsm = ap_ST_pp1_stg1_fsm_12;
end else if (((ap_ST_pp0_stg6_fsm_8 == ap_CS_fsm) & ~((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (ap_ST_pp0_stg6_fsm_8 == ap_CS_fsm) & ~(ap_const_logic_1 == ap_reg_ppiten_pp0_it0)))) begin
ap_NS_fsm = ap_ST_pp0_stg7_fsm_9;
end else if ((ap_ST_pp0_stg5_fsm_7 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_pp0_stg6_fsm_8;
end else if ((ap_ST_pp0_stg4_fsm_6 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_pp0_stg5_fsm_7;
end else if ((ap_ST_pp0_stg3_fsm_5 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_pp0_stg4_fsm_6;
end else if ((ap_ST_pp0_stg2_fsm_4 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_pp0_stg3_fsm_5;
end else if ((ap_ST_pp0_stg1_fsm_3 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_pp0_stg2_fsm_4;
end else if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & ~((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ~(ap_const_lv1_0 == exitcond_fu_957_p2) & ~(ap_const_logic_1 == ap_reg_ppiten_pp0_it1)))) begin
ap_NS_fsm = ap_ST_pp0_stg1_fsm_3;
end else if ((~(ap_const_logic_1 == ap_start) & (ap_ST_st44_fsm_19 == ap_CS_fsm))) begin
ap_NS_fsm = ap_ST_st0_fsm_0;
end else if (((ap_ST_pp1_stg7_fsm_18 == ap_CS_fsm) | ((ap_ST_st17_fsm_10 == ap_CS_fsm) & ~(ap_const_lv1_0 == or_cond1_fu_1187_p2)))) begin
ap_NS_fsm = ap_ST_pp1_stg0_fsm_11;
end else if ((((ap_ST_st17_fsm_10 == ap_CS_fsm) & (ap_const_lv1_0 == or_cond1_fu_1187_p2)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_ST_pp1_stg0_fsm_11 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond2_fu_1193_p2) & ~(ap_const_logic_1 == ap_reg_ppiten_pp1_it1)) | ((ap_ST_pp1_stg1_fsm_12 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it3) & ~(ap_const_logic_1 == ap_reg_ppiten_pp1_it2)))) begin
ap_NS_fsm = ap_ST_st44_fsm_19;
end else if (((ap_ST_pp0_stg7_fsm_9 == ap_CS_fsm) | ((ap_ST_st1_fsm_1 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_2_fu_951_p2)))) begin
ap_NS_fsm = ap_ST_pp0_stg0_fsm_2;
end else if ((((ap_ST_st1_fsm_1 == ap_CS_fsm) & (ap_const_lv1_0 == tmp_2_fu_951_p2)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond_fu_957_p2) & ~(ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (ap_ST_pp0_stg6_fsm_8 == ap_CS_fsm) & ~(ap_const_logic_1 == ap_reg_ppiten_pp0_it0)))) begin
ap_NS_fsm = ap_ST_st17_fsm_10;
end else if ((((ap_ST_st0_fsm_0 == ap_CS_fsm) & (ap_const_logic_1 == ap_start)) | ((ap_const_logic_1 == ap_start) & (ap_ST_st44_fsm_19 == ap_CS_fsm)))) begin
ap_NS_fsm = ap_ST_st1_fsm_1;
end else begin
ap_NS_fsm = ap_CS_fsm;
end
end
/// ap_done assign process. ///
always @ (ap_CS_fsm)
begin
if (((ap_ST_st0_fsm_0 == ap_CS_fsm) | (ap_ST_st44_fsm_19 == ap_CS_fsm))) begin
ap_done = ap_const_logic_1;
end else begin
ap_done = ap_const_logic_0;
end
end
/// ap_idle assign process. ///
always @ (ap_CS_fsm)
begin
if ((ap_ST_st0_fsm_0 == ap_CS_fsm)) begin
ap_idle = ap_const_logic_1;
end else begin
ap_idle = ap_const_logic_0;
end
end
/// b_address0 assign process. ///
always @ (ap_CS_fsm or ap_reg_ppiten_pp0_it0 or exitcond_reg_1446 or ap_reg_ppiten_pp1_it0 or exitcond2_reg_1603 or exitcond_fu_957_p2 or tmp_6_fu_1021_p1 or tmp_7_fu_1054_p1 or tmp_11_fu_1092_p1 or tmp_15_fu_1130_p1 or tmp_19_fu_1173_p1 or exitcond2_fu_1193_p2 or tmp_30_fu_1257_p1 or tmp_33_fu_1291_p1 or tmp_39_fu_1331_p1 or tmp_45_fu_1371_p1 or tmp_51_fu_1416_p1)
begin
if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond2_reg_1603) & (ap_ST_pp1_stg4_fsm_15 == ap_CS_fsm))) begin
b_address0 = tmp_51_fu_1416_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond2_reg_1603) & (ap_ST_pp1_stg3_fsm_14 == ap_CS_fsm))) begin
b_address0 = tmp_45_fu_1371_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond2_reg_1603) & (ap_ST_pp1_stg2_fsm_13 == ap_CS_fsm))) begin
b_address0 = tmp_39_fu_1331_p1;
end else if (((ap_ST_pp1_stg1_fsm_12 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond2_reg_1603))) begin
b_address0 = tmp_33_fu_1291_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_ST_pp1_stg0_fsm_11 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond2_fu_1193_p2))) begin
b_address0 = tmp_30_fu_1257_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_reg_1446 == ap_const_lv1_0) & (ap_ST_pp0_stg4_fsm_6 == ap_CS_fsm))) begin
b_address0 = tmp_19_fu_1173_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_reg_1446 == ap_const_lv1_0) & (ap_ST_pp0_stg3_fsm_5 == ap_CS_fsm))) begin
b_address0 = tmp_15_fu_1130_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_reg_1446 == ap_const_lv1_0) & (ap_ST_pp0_stg2_fsm_4 == ap_CS_fsm))) begin
b_address0 = tmp_11_fu_1092_p1;
end else if (((ap_ST_pp0_stg1_fsm_3 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_reg_1446 == ap_const_lv1_0))) begin
b_address0 = tmp_7_fu_1054_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond_fu_957_p2))) begin
b_address0 = tmp_6_fu_1021_p1;
end else begin
b_address0 = tmp_51_fu_1416_p1;
end
end
/// b_address1 assign process. ///
always @ (ap_CS_fsm or ap_reg_ppiten_pp0_it0 or exitcond_reg_1446 or ap_reg_ppiten_pp1_it0 or exitcond2_reg_1603 or tmp_9_fu_1073_p1 or tmp_13_fu_1111_p1 or tmp_17_fu_1149_p1 or tmp_36_fu_1311_p1 or tmp_42_fu_1351_p1 or tmp_48_fu_1391_p1)
begin
if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond2_reg_1603) & (ap_ST_pp1_stg3_fsm_14 == ap_CS_fsm))) begin
b_address1 = tmp_48_fu_1391_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond2_reg_1603) & (ap_ST_pp1_stg2_fsm_13 == ap_CS_fsm))) begin
b_address1 = tmp_42_fu_1351_p1;
end else if (((ap_ST_pp1_stg1_fsm_12 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond2_reg_1603))) begin
b_address1 = tmp_36_fu_1311_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_reg_1446 == ap_const_lv1_0) & (ap_ST_pp0_stg3_fsm_5 == ap_CS_fsm))) begin
b_address1 = tmp_17_fu_1149_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_reg_1446 == ap_const_lv1_0) & (ap_ST_pp0_stg2_fsm_4 == ap_CS_fsm))) begin
b_address1 = tmp_13_fu_1111_p1;
end else if (((ap_ST_pp0_stg1_fsm_3 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_reg_1446 == ap_const_lv1_0))) begin
b_address1 = tmp_9_fu_1073_p1;
end else begin
b_address1 = tmp_48_fu_1391_p1;
end
end
/// b_ce0 assign process. ///
always @ (ap_CS_fsm or ap_reg_ppiten_pp0_it0 or exitcond_reg_1446 or ap_reg_ppiten_pp1_it0 or exitcond2_reg_1603 or exitcond_fu_957_p2 or exitcond2_fu_1193_p2)
begin
if ((((ap_ST_pp0_stg1_fsm_3 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_reg_1446 == ap_const_lv1_0)) | ((ap_ST_pp1_stg1_fsm_12 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond2_reg_1603)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_reg_1446 == ap_const_lv1_0) & (ap_ST_pp0_stg2_fsm_4 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond2_reg_1603) & (ap_ST_pp1_stg2_fsm_13 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_reg_1446 == ap_const_lv1_0) & (ap_ST_pp0_stg3_fsm_5 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond2_reg_1603) & (ap_ST_pp1_stg3_fsm_14 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_reg_1446 == ap_const_lv1_0) & (ap_ST_pp0_stg4_fsm_6 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond2_reg_1603) & (ap_ST_pp1_stg4_fsm_15 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond_fu_957_p2)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_ST_pp1_stg0_fsm_11 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond2_fu_1193_p2)))) begin
b_ce0 = ap_const_logic_1;
end else begin
b_ce0 = ap_const_logic_0;
end
end
/// b_ce1 assign process. ///
always @ (ap_CS_fsm or ap_reg_ppiten_pp0_it0 or exitcond_reg_1446 or ap_reg_ppiten_pp1_it0 or exitcond2_reg_1603)
begin
if ((((ap_ST_pp0_stg1_fsm_3 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_reg_1446 == ap_const_lv1_0)) | ((ap_ST_pp1_stg1_fsm_12 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond2_reg_1603)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_reg_1446 == ap_const_lv1_0) & (ap_ST_pp0_stg2_fsm_4 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond2_reg_1603) & (ap_ST_pp1_stg2_fsm_13 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_reg_1446 == ap_const_lv1_0) & (ap_ST_pp0_stg3_fsm_5 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond2_reg_1603) & (ap_ST_pp1_stg3_fsm_14 == ap_CS_fsm)))) begin
b_ce1 = ap_const_logic_1;
end else begin
b_ce1 = ap_const_logic_0;
end
end
/// c1_address0 assign process. ///
always @ (ap_CS_fsm or ap_reg_ppiten_pp0_it0 or ap_reg_ppiten_pp0_it1 or exitcond_reg_1446 or ap_reg_ppiten_pp1_it1 or ap_reg_ppiten_pp1_it2 or ap_reg_ppstg_exitcond_reg_1446_pp0_it1 or ap_reg_ppstg_exitcond2_reg_1603_pp1_it2 or tmp_6_reg_1483 or tmp_7_reg_1500 or tmp_11_reg_1524 or tmp_15_reg_1548 or tmp_19_reg_1582 or ap_reg_ppstg_exitcond2_reg_1603_pp1_it1 or ap_reg_ppstg_tmp_30_reg_1640_pp1_it1 or ap_reg_ppstg_tmp_33_reg_1662_pp1_it1 or ap_reg_ppstg_tmp_36_reg_1679_pp1_it1 or ap_reg_ppstg_tmp_39_reg_1706_pp1_it1 or ap_reg_ppstg_tmp_42_reg_1723_pp1_it1 or ap_reg_ppstg_tmp_45_reg_1750_pp1_it1 or ap_reg_ppstg_tmp_48_reg_1767_pp1_it1 or ap_reg_ppstg_tmp_51_reg_1804_pp1_it1)
begin
if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it2) & (ap_ST_pp1_stg2_fsm_13 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it2))) begin
c1_address0 = ap_reg_ppstg_tmp_51_reg_1804_pp1_it1;
end else if (((ap_ST_pp1_stg1_fsm_12 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it2) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it2))) begin
c1_address0 = ap_reg_ppstg_tmp_48_reg_1767_pp1_it1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it2) & (ap_ST_pp1_stg0_fsm_11 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it1))) begin
c1_address0 = ap_reg_ppstg_tmp_45_reg_1750_pp1_it1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_ST_pp1_stg7_fsm_18 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it1))) begin
c1_address0 = ap_reg_ppstg_tmp_42_reg_1723_pp1_it1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_ST_pp1_stg6_fsm_17 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it1))) begin
c1_address0 = ap_reg_ppstg_tmp_39_reg_1706_pp1_it1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_ST_pp1_stg5_fsm_16 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it1))) begin
c1_address0 = ap_reg_ppstg_tmp_36_reg_1679_pp1_it1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_ST_pp1_stg4_fsm_15 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it1))) begin
c1_address0 = ap_reg_ppstg_tmp_33_reg_1662_pp1_it1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_ST_pp1_stg3_fsm_14 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it1))) begin
c1_address0 = ap_reg_ppstg_tmp_30_reg_1640_pp1_it1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (ap_ST_pp0_stg2_fsm_4 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_1446_pp0_it1))) begin
c1_address0 = tmp_19_reg_1582;
end else if (((ap_ST_pp0_stg1_fsm_3 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_1446_pp0_it1))) begin
c1_address0 = tmp_15_reg_1548;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (exitcond_reg_1446 == ap_const_lv1_0) & (ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm))) begin
c1_address0 = tmp_11_reg_1524;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_reg_1446 == ap_const_lv1_0) & (ap_ST_pp0_stg7_fsm_9 == ap_CS_fsm))) begin
c1_address0 = tmp_7_reg_1500;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_reg_1446 == ap_const_lv1_0) & (ap_ST_pp0_stg6_fsm_8 == ap_CS_fsm))) begin
c1_address0 = tmp_6_reg_1483;
end else begin
c1_address0 = ap_reg_ppstg_tmp_51_reg_1804_pp1_it1;
end
end
/// c1_address1 assign process. ///
always @ (ap_CS_fsm or ap_reg_ppiten_pp0_it0 or ap_reg_ppiten_pp0_it1 or exitcond_reg_1446 or ap_reg_ppstg_exitcond_reg_1446_pp0_it1 or tmp_9_reg_1512 or tmp_13_reg_1536 or tmp_17_reg_1560)
begin
if (((ap_ST_pp0_stg1_fsm_3 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_1446_pp0_it1))) begin
c1_address1 = tmp_17_reg_1560;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (exitcond_reg_1446 == ap_const_lv1_0) & (ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm))) begin
c1_address1 = tmp_13_reg_1536;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_reg_1446 == ap_const_lv1_0) & (ap_ST_pp0_stg7_fsm_9 == ap_CS_fsm))) begin
c1_address1 = tmp_9_reg_1512;
end else begin
c1_address1 = tmp_17_reg_1560;
end
end
/// c1_ce0 assign process. ///
always @ (ap_CS_fsm or ap_reg_ppiten_pp0_it0 or ap_reg_ppiten_pp0_it1 or exitcond_reg_1446 or ap_reg_ppiten_pp1_it1 or ap_reg_ppiten_pp1_it2 or ap_reg_ppstg_exitcond_reg_1446_pp0_it1 or ap_reg_ppstg_exitcond2_reg_1603_pp1_it2 or ap_reg_ppstg_exitcond2_reg_1603_pp1_it1)
begin
if ((((ap_ST_pp0_stg1_fsm_3 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_1446_pp0_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_reg_1446 == ap_const_lv1_0) & (ap_ST_pp0_stg6_fsm_8 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_reg_1446 == ap_const_lv1_0) & (ap_ST_pp0_stg7_fsm_9 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (exitcond_reg_1446 == ap_const_lv1_0) & (ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_ST_pp1_stg3_fsm_14 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_ST_pp1_stg4_fsm_15 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_ST_pp1_stg5_fsm_16 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_ST_pp1_stg6_fsm_17 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_ST_pp1_stg7_fsm_18 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it2) & (ap_ST_pp1_stg0_fsm_11 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it1)) | ((ap_ST_pp1_stg1_fsm_12 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it2) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it2)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (ap_ST_pp0_stg2_fsm_4 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_1446_pp0_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it2) & (ap_ST_pp1_stg2_fsm_13 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it2)))) begin
c1_ce0 = ap_const_logic_1;
end else begin
c1_ce0 = ap_const_logic_0;
end
end
/// c1_ce1 assign process. ///
always @ (ap_CS_fsm or ap_reg_ppiten_pp0_it0 or ap_reg_ppiten_pp0_it1 or exitcond_reg_1446 or ap_reg_ppstg_exitcond_reg_1446_pp0_it1)
begin
if ((((ap_ST_pp0_stg1_fsm_3 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_1446_pp0_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_reg_1446 == ap_const_lv1_0) & (ap_ST_pp0_stg7_fsm_9 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (exitcond_reg_1446 == ap_const_lv1_0) & (ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)))) begin
c1_ce1 = ap_const_logic_1;
end else begin
c1_ce1 = ap_const_logic_0;
end
end
/// c1_d0 assign process. ///
always @ (ap_CS_fsm or ap_reg_ppiten_pp0_it0 or ap_reg_ppiten_pp0_it1 or exitcond_reg_1446 or ap_reg_ppiten_pp1_it1 or ap_reg_ppiten_pp1_it2 or reg_865 or ap_reg_ppstg_exitcond_reg_1446_pp0_it1 or ap_reg_ppstg_exitcond2_reg_1603_pp1_it2 or reg_874 or reg_890 or reg_906 or ap_reg_ppstg_exitcond2_reg_1603_pp1_it1 or t_reg_1831 or t8_reg_1838 or t9_reg_1845 or t10_reg_1852 or t11_reg_1859 or t12_reg_1866 or t13_reg_1873 or t14_reg_1880)
begin
if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it2) & (ap_ST_pp1_stg2_fsm_13 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it2))) begin
c1_d0 = t14_reg_1880;
end else if (((ap_ST_pp1_stg1_fsm_12 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it2) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it2))) begin
c1_d0 = t13_reg_1873;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it2) & (ap_ST_pp1_stg0_fsm_11 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it1))) begin
c1_d0 = t12_reg_1866;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_ST_pp1_stg7_fsm_18 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it1))) begin
c1_d0 = t11_reg_1859;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_ST_pp1_stg6_fsm_17 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it1))) begin
c1_d0 = t10_reg_1852;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_ST_pp1_stg5_fsm_16 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it1))) begin
c1_d0 = t9_reg_1845;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_ST_pp1_stg4_fsm_15 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it1))) begin
c1_d0 = t8_reg_1838;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_ST_pp1_stg3_fsm_14 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it1))) begin
c1_d0 = t_reg_1831;
end else if (((ap_ST_pp0_stg1_fsm_3 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_1446_pp0_it1))) begin
c1_d0 = reg_906;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (exitcond_reg_1446 == ap_const_lv1_0) & (ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm))) begin
c1_d0 = reg_890;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_reg_1446 == ap_const_lv1_0) & (ap_ST_pp0_stg7_fsm_9 == ap_CS_fsm))) begin
c1_d0 = reg_874;
end else if ((((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_reg_1446 == ap_const_lv1_0) & (ap_ST_pp0_stg6_fsm_8 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (ap_ST_pp0_stg2_fsm_4 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_1446_pp0_it1)))) begin
c1_d0 = reg_865;
end else begin
c1_d0 = t14_reg_1880;
end
end
/// c1_d1 assign process. ///
always @ (ap_CS_fsm or ap_reg_ppiten_pp0_it0 or ap_reg_ppiten_pp0_it1 or exitcond_reg_1446 or ap_reg_ppstg_exitcond_reg_1446_pp0_it1 or reg_882 or reg_898 or reg_914)
begin
if (((ap_ST_pp0_stg1_fsm_3 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_1446_pp0_it1))) begin
c1_d1 = reg_914;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (exitcond_reg_1446 == ap_const_lv1_0) & (ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm))) begin
c1_d1 = reg_898;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_reg_1446 == ap_const_lv1_0) & (ap_ST_pp0_stg7_fsm_9 == ap_CS_fsm))) begin
c1_d1 = reg_882;
end else begin
c1_d1 = reg_914;
end
end
/// c1_we0 assign process. ///
always @ (ap_CS_fsm or ap_reg_ppiten_pp0_it0 or ap_reg_ppiten_pp0_it1 or exitcond_reg_1446 or ap_reg_ppiten_pp1_it1 or ap_reg_ppiten_pp1_it2 or ap_reg_ppstg_exitcond_reg_1446_pp0_it1 or ap_reg_ppstg_exitcond2_reg_1603_pp1_it2 or ap_reg_ppstg_exitcond2_reg_1603_pp1_it1)
begin
if ((((ap_ST_pp0_stg1_fsm_3 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_1446_pp0_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_reg_1446 == ap_const_lv1_0) & (ap_ST_pp0_stg6_fsm_8 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_reg_1446 == ap_const_lv1_0) & (ap_ST_pp0_stg7_fsm_9 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (exitcond_reg_1446 == ap_const_lv1_0) & (ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_ST_pp1_stg3_fsm_14 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_ST_pp1_stg4_fsm_15 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_ST_pp1_stg5_fsm_16 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_ST_pp1_stg6_fsm_17 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_ST_pp1_stg7_fsm_18 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it2) & (ap_ST_pp1_stg0_fsm_11 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it1)) | ((ap_ST_pp1_stg1_fsm_12 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it2) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it2)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (ap_ST_pp0_stg2_fsm_4 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_1446_pp0_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it2) & (ap_ST_pp1_stg2_fsm_13 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it2)))) begin
c1_we0 = ap_const_logic_1;
end else begin
c1_we0 = ap_const_logic_0;
end
end
/// c1_we1 assign process. ///
always @ (ap_CS_fsm or ap_reg_ppiten_pp0_it0 or ap_reg_ppiten_pp0_it1 or exitcond_reg_1446 or ap_reg_ppstg_exitcond_reg_1446_pp0_it1)
begin
if ((((ap_ST_pp0_stg1_fsm_3 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_1446_pp0_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_reg_1446 == ap_const_lv1_0) & (ap_ST_pp0_stg7_fsm_9 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (exitcond_reg_1446 == ap_const_lv1_0) & (ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)))) begin
c1_we1 = ap_const_logic_1;
end else begin
c1_we1 = ap_const_logic_0;
end
end
/// c_address0 assign process. ///
always @ (ap_CS_fsm or ap_reg_ppiten_pp1_it0 or exitcond2_reg_1603 or exitcond2_fu_1193_p2 or tmp_30_fu_1257_p1 or tmp_33_fu_1291_p1 or tmp_39_fu_1331_p1 or tmp_45_fu_1371_p1 or tmp_51_fu_1416_p1)
begin
if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond2_reg_1603) & (ap_ST_pp1_stg4_fsm_15 == ap_CS_fsm))) begin
c_address0 = tmp_51_fu_1416_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond2_reg_1603) & (ap_ST_pp1_stg3_fsm_14 == ap_CS_fsm))) begin
c_address0 = tmp_45_fu_1371_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond2_reg_1603) & (ap_ST_pp1_stg2_fsm_13 == ap_CS_fsm))) begin
c_address0 = tmp_39_fu_1331_p1;
end else if (((ap_ST_pp1_stg1_fsm_12 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond2_reg_1603))) begin
c_address0 = tmp_33_fu_1291_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_ST_pp1_stg0_fsm_11 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond2_fu_1193_p2))) begin
c_address0 = tmp_30_fu_1257_p1;
end else begin
c_address0 = tmp_51_fu_1416_p1;
end
end
/// c_address1 assign process. ///
always @ (ap_CS_fsm or ap_reg_ppiten_pp1_it0 or exitcond2_reg_1603 or tmp_36_fu_1311_p1 or tmp_42_fu_1351_p1 or tmp_48_fu_1391_p1)
begin
if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond2_reg_1603) & (ap_ST_pp1_stg3_fsm_14 == ap_CS_fsm))) begin
c_address1 = tmp_48_fu_1391_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond2_reg_1603) & (ap_ST_pp1_stg2_fsm_13 == ap_CS_fsm))) begin
c_address1 = tmp_42_fu_1351_p1;
end else if (((ap_ST_pp1_stg1_fsm_12 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond2_reg_1603))) begin
c_address1 = tmp_36_fu_1311_p1;
end else begin
c_address1 = tmp_48_fu_1391_p1;
end
end
/// c_ce0 assign process. ///
always @ (ap_CS_fsm or ap_reg_ppiten_pp1_it0 or exitcond2_reg_1603 or exitcond2_fu_1193_p2)
begin
if ((((ap_ST_pp1_stg1_fsm_12 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond2_reg_1603)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond2_reg_1603) & (ap_ST_pp1_stg2_fsm_13 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond2_reg_1603) & (ap_ST_pp1_stg3_fsm_14 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond2_reg_1603) & (ap_ST_pp1_stg4_fsm_15 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_ST_pp1_stg0_fsm_11 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond2_fu_1193_p2)))) begin
c_ce0 = ap_const_logic_1;
end else begin
c_ce0 = ap_const_logic_0;
end
end
/// c_ce1 assign process. ///
always @ (ap_CS_fsm or ap_reg_ppiten_pp1_it0 or exitcond2_reg_1603)
begin
if ((((ap_ST_pp1_stg1_fsm_12 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond2_reg_1603)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond2_reg_1603) & (ap_ST_pp1_stg2_fsm_13 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond2_reg_1603) & (ap_ST_pp1_stg3_fsm_14 == ap_CS_fsm)))) begin
c_ce1 = ap_const_logic_1;
end else begin
c_ce1 = ap_const_logic_0;
end
end
/// d_address0 assign process. ///
always @ (ap_CS_fsm or ap_reg_ppiten_pp0_it0 or ap_reg_ppiten_pp0_it1 or exitcond_reg_1446 or ap_reg_ppiten_pp1_it1 or ap_reg_ppiten_pp1_it2 or ap_reg_ppstg_exitcond_reg_1446_pp0_it1 or or_cond_reg_1433 or ap_reg_ppstg_exitcond2_reg_1603_pp1_it2 or tmp_6_reg_1483 or ap_reg_ppstg_tmp_6_reg_1483_pp0_it1 or tmp_7_reg_1500 or ap_reg_ppstg_tmp_7_reg_1500_pp0_it1 or tmp_11_reg_1524 or ap_reg_ppstg_tmp_11_reg_1524_pp0_it1 or tmp_15_reg_1548 or ap_reg_ppstg_tmp_15_reg_1548_pp0_it1 or tmp_19_reg_1582 or ap_reg_ppstg_exitcond2_reg_1603_pp1_it1 or ap_reg_ppstg_tmp_30_reg_1640_pp1_it1 or ap_reg_ppstg_tmp_30_reg_1640_pp1_it2 or ap_reg_ppstg_tmp_33_reg_1662_pp1_it1 or ap_reg_ppstg_tmp_36_reg_1679_pp1_it1 or ap_reg_ppstg_tmp_39_reg_1706_pp1_it1 or ap_reg_ppstg_tmp_42_reg_1723_pp1_it1 or ap_reg_ppstg_tmp_45_reg_1750_pp1_it1 or ap_reg_ppstg_tmp_48_reg_1767_pp1_it1 or ap_reg_ppstg_tmp_51_reg_1804_pp1_it1)
begin
if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it2) & (ap_ST_pp1_stg2_fsm_13 == ap_CS_fsm) & ~(ap_const_lv1_0 == or_cond_reg_1433) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it2))) begin
d_address0 = ap_reg_ppstg_tmp_30_reg_1640_pp1_it2;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it2) & (ap_ST_pp1_stg2_fsm_13 == ap_CS_fsm) & (ap_const_lv1_0 == or_cond_reg_1433) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it2))) begin
d_address0 = ap_reg_ppstg_tmp_51_reg_1804_pp1_it1;
end else if (((ap_ST_pp1_stg1_fsm_12 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it2) & (ap_const_lv1_0 == or_cond_reg_1433) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it2))) begin
d_address0 = ap_reg_ppstg_tmp_48_reg_1767_pp1_it1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it2) & (ap_const_lv1_0 == or_cond_reg_1433) & (ap_ST_pp1_stg0_fsm_11 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it1))) begin
d_address0 = ap_reg_ppstg_tmp_45_reg_1750_pp1_it1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_const_lv1_0 == or_cond_reg_1433) & (ap_ST_pp1_stg7_fsm_18 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it1))) begin
d_address0 = ap_reg_ppstg_tmp_42_reg_1723_pp1_it1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_const_lv1_0 == or_cond_reg_1433) & (ap_ST_pp1_stg6_fsm_17 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it1))) begin
d_address0 = ap_reg_ppstg_tmp_39_reg_1706_pp1_it1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_ST_pp1_stg5_fsm_16 == ap_CS_fsm) & (ap_const_lv1_0 == or_cond_reg_1433) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it1))) begin
d_address0 = ap_reg_ppstg_tmp_36_reg_1679_pp1_it1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_ST_pp1_stg4_fsm_15 == ap_CS_fsm) & (ap_const_lv1_0 == or_cond_reg_1433) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it1))) begin
d_address0 = ap_reg_ppstg_tmp_33_reg_1662_pp1_it1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_ST_pp1_stg3_fsm_14 == ap_CS_fsm) & (ap_const_lv1_0 == or_cond_reg_1433) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it1))) begin
d_address0 = ap_reg_ppstg_tmp_30_reg_1640_pp1_it1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (ap_ST_pp0_stg5_fsm_7 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_1446_pp0_it1) & ~(ap_const_lv1_0 == or_cond_reg_1433))) begin
d_address0 = ap_reg_ppstg_tmp_15_reg_1548_pp0_it1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (ap_ST_pp0_stg4_fsm_6 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_1446_pp0_it1) & ~(ap_const_lv1_0 == or_cond_reg_1433))) begin
d_address0 = ap_reg_ppstg_tmp_11_reg_1524_pp0_it1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (ap_ST_pp0_stg3_fsm_5 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_1446_pp0_it1) & ~(ap_const_lv1_0 == or_cond_reg_1433))) begin
d_address0 = ap_reg_ppstg_tmp_7_reg_1500_pp0_it1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (ap_ST_pp0_stg2_fsm_4 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_1446_pp0_it1) & ~(ap_const_lv1_0 == or_cond_reg_1433))) begin
d_address0 = ap_reg_ppstg_tmp_6_reg_1483_pp0_it1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (ap_ST_pp0_stg2_fsm_4 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_1446_pp0_it1) & (ap_const_lv1_0 == or_cond_reg_1433))) begin
d_address0 = tmp_19_reg_1582;
end else if (((ap_ST_pp0_stg1_fsm_3 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_1446_pp0_it1) & (ap_const_lv1_0 == or_cond_reg_1433))) begin
d_address0 = tmp_15_reg_1548;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (exitcond_reg_1446 == ap_const_lv1_0) & (ap_const_lv1_0 == or_cond_reg_1433) & (ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm))) begin
d_address0 = tmp_11_reg_1524;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_reg_1446 == ap_const_lv1_0) & (ap_const_lv1_0 == or_cond_reg_1433) & (ap_ST_pp0_stg7_fsm_9 == ap_CS_fsm))) begin
d_address0 = tmp_7_reg_1500;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_reg_1446 == ap_const_lv1_0) & (ap_const_lv1_0 == or_cond_reg_1433) & (ap_ST_pp0_stg6_fsm_8 == ap_CS_fsm))) begin
d_address0 = tmp_6_reg_1483;
end else begin
d_address0 = ap_reg_ppstg_tmp_30_reg_1640_pp1_it2;
end
end
/// d_address1 assign process. ///
always @ (ap_CS_fsm or ap_reg_ppiten_pp0_it0 or ap_reg_ppiten_pp0_it1 or exitcond_reg_1446 or ap_reg_ppiten_pp1_it2 or ap_reg_ppiten_pp1_it3 or ap_reg_ppstg_exitcond_reg_1446_pp0_it1 or or_cond_reg_1433 or ap_reg_ppstg_exitcond2_reg_1603_pp1_it2 or tmp_9_reg_1512 or ap_reg_ppstg_tmp_9_reg_1512_pp0_it1 or tmp_13_reg_1536 or ap_reg_ppstg_tmp_13_reg_1536_pp0_it1 or tmp_17_reg_1560 or ap_reg_ppstg_tmp_17_reg_1560_pp0_it1 or ap_reg_ppstg_tmp_19_reg_1582_pp0_it1 or ap_reg_ppstg_exitcond2_reg_1603_pp1_it3 or ap_reg_ppstg_tmp_33_reg_1662_pp1_it2 or ap_reg_ppstg_tmp_36_reg_1679_pp1_it2 or ap_reg_ppstg_tmp_39_reg_1706_pp1_it2 or ap_reg_ppstg_tmp_42_reg_1723_pp1_it2 or ap_reg_ppstg_tmp_45_reg_1750_pp1_it2 or ap_reg_ppstg_tmp_48_reg_1767_pp1_it2 or ap_reg_ppstg_tmp_51_reg_1804_pp1_it2)
begin
if (((ap_ST_pp1_stg1_fsm_12 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it3) & ~(ap_const_lv1_0 == or_cond_reg_1433) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it3))) begin
d_address1 = ap_reg_ppstg_tmp_51_reg_1804_pp1_it2;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it3) & ~(ap_const_lv1_0 == or_cond_reg_1433) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it2) & (ap_ST_pp1_stg0_fsm_11 == ap_CS_fsm))) begin
d_address1 = ap_reg_ppstg_tmp_48_reg_1767_pp1_it2;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it2) & ~(ap_const_lv1_0 == or_cond_reg_1433) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it2) & (ap_ST_pp1_stg7_fsm_18 == ap_CS_fsm))) begin
d_address1 = ap_reg_ppstg_tmp_45_reg_1750_pp1_it2;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it2) & ~(ap_const_lv1_0 == or_cond_reg_1433) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it2) & (ap_ST_pp1_stg6_fsm_17 == ap_CS_fsm))) begin
d_address1 = ap_reg_ppstg_tmp_42_reg_1723_pp1_it2;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it2) & (ap_ST_pp1_stg5_fsm_16 == ap_CS_fsm) & ~(ap_const_lv1_0 == or_cond_reg_1433) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it2))) begin
d_address1 = ap_reg_ppstg_tmp_39_reg_1706_pp1_it2;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it2) & (ap_ST_pp1_stg4_fsm_15 == ap_CS_fsm) & ~(ap_const_lv1_0 == or_cond_reg_1433) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it2))) begin
d_address1 = ap_reg_ppstg_tmp_36_reg_1679_pp1_it2;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it2) & (ap_ST_pp1_stg3_fsm_14 == ap_CS_fsm) & ~(ap_const_lv1_0 == or_cond_reg_1433) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it2))) begin
d_address1 = ap_reg_ppstg_tmp_33_reg_1662_pp1_it2;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_1446_pp0_it1) & ~(ap_const_lv1_0 == or_cond_reg_1433) & (ap_ST_pp0_stg6_fsm_8 == ap_CS_fsm))) begin
d_address1 = ap_reg_ppstg_tmp_19_reg_1582_pp0_it1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (ap_ST_pp0_stg5_fsm_7 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_1446_pp0_it1) & ~(ap_const_lv1_0 == or_cond_reg_1433))) begin
d_address1 = ap_reg_ppstg_tmp_17_reg_1560_pp0_it1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (ap_ST_pp0_stg4_fsm_6 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_1446_pp0_it1) & ~(ap_const_lv1_0 == or_cond_reg_1433))) begin
d_address1 = ap_reg_ppstg_tmp_13_reg_1536_pp0_it1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (ap_ST_pp0_stg3_fsm_5 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_1446_pp0_it1) & ~(ap_const_lv1_0 == or_cond_reg_1433))) begin
d_address1 = ap_reg_ppstg_tmp_9_reg_1512_pp0_it1;
end else if (((ap_ST_pp0_stg1_fsm_3 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_1446_pp0_it1) & (ap_const_lv1_0 == or_cond_reg_1433))) begin
d_address1 = tmp_17_reg_1560;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (exitcond_reg_1446 == ap_const_lv1_0) & (ap_const_lv1_0 == or_cond_reg_1433) & (ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm))) begin
d_address1 = tmp_13_reg_1536;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_reg_1446 == ap_const_lv1_0) & (ap_const_lv1_0 == or_cond_reg_1433) & (ap_ST_pp0_stg7_fsm_9 == ap_CS_fsm))) begin
d_address1 = tmp_9_reg_1512;
end else begin
d_address1 = ap_reg_ppstg_tmp_51_reg_1804_pp1_it2;
end
end
/// d_ce0 assign process. ///
always @ (ap_CS_fsm or ap_reg_ppiten_pp0_it0 or ap_reg_ppiten_pp0_it1 or exitcond_reg_1446 or ap_reg_ppiten_pp1_it1 or ap_reg_ppiten_pp1_it2 or ap_reg_ppstg_exitcond_reg_1446_pp0_it1 or or_cond_reg_1433 or ap_reg_ppstg_exitcond2_reg_1603_pp1_it2 or ap_reg_ppstg_exitcond2_reg_1603_pp1_it1)
begin
if ((((ap_const_logic_1 == ap_reg_ppiten_pp1_it2) & (ap_ST_pp1_stg2_fsm_13 == ap_CS_fsm) & ~(ap_const_lv1_0 == or_cond_reg_1433) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it2)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (ap_ST_pp0_stg2_fsm_4 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_1446_pp0_it1) & ~(ap_const_lv1_0 == or_cond_reg_1433)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (ap_ST_pp0_stg3_fsm_5 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_1446_pp0_it1) & ~(ap_const_lv1_0 == or_cond_reg_1433)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (ap_ST_pp0_stg4_fsm_6 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_1446_pp0_it1) & ~(ap_const_lv1_0 == or_cond_reg_1433)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (ap_ST_pp0_stg5_fsm_7 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_1446_pp0_it1) & ~(ap_const_lv1_0 == or_cond_reg_1433)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_reg_1446 == ap_const_lv1_0) & (ap_const_lv1_0 == or_cond_reg_1433) & (ap_ST_pp0_stg6_fsm_8 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_reg_1446 == ap_const_lv1_0) & (ap_const_lv1_0 == or_cond_reg_1433) & (ap_ST_pp0_stg7_fsm_9 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (exitcond_reg_1446 == ap_const_lv1_0) & (ap_const_lv1_0 == or_cond_reg_1433) & (ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) | ((ap_ST_pp0_stg1_fsm_3 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_1446_pp0_it1) & (ap_const_lv1_0 == or_cond_reg_1433)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (ap_ST_pp0_stg2_fsm_4 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_1446_pp0_it1) & (ap_const_lv1_0 == or_cond_reg_1433)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_ST_pp1_stg3_fsm_14 == ap_CS_fsm) & (ap_const_lv1_0 == or_cond_reg_1433) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_ST_pp1_stg4_fsm_15 == ap_CS_fsm) & (ap_const_lv1_0 == or_cond_reg_1433) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_ST_pp1_stg5_fsm_16 == ap_CS_fsm) & (ap_const_lv1_0 == or_cond_reg_1433) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_const_lv1_0 == or_cond_reg_1433) & (ap_ST_pp1_stg6_fsm_17 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_const_lv1_0 == or_cond_reg_1433) & (ap_ST_pp1_stg7_fsm_18 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it2) & (ap_const_lv1_0 == or_cond_reg_1433) & (ap_ST_pp1_stg0_fsm_11 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it1)) | ((ap_ST_pp1_stg1_fsm_12 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it2) & (ap_const_lv1_0 == or_cond_reg_1433) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it2)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it2) & (ap_ST_pp1_stg2_fsm_13 == ap_CS_fsm) & (ap_const_lv1_0 == or_cond_reg_1433) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it2)))) begin
d_ce0 = ap_const_logic_1;
end else begin
d_ce0 = ap_const_logic_0;
end
end
/// d_ce1 assign process. ///
always @ (ap_CS_fsm or ap_reg_ppiten_pp0_it0 or ap_reg_ppiten_pp0_it1 or exitcond_reg_1446 or ap_reg_ppiten_pp1_it2 or ap_reg_ppiten_pp1_it3 or ap_reg_ppstg_exitcond_reg_1446_pp0_it1 or or_cond_reg_1433 or ap_reg_ppstg_exitcond2_reg_1603_pp1_it2 or ap_reg_ppstg_exitcond2_reg_1603_pp1_it3)
begin
if ((((ap_const_logic_1 == ap_reg_ppiten_pp1_it2) & (ap_ST_pp1_stg3_fsm_14 == ap_CS_fsm) & ~(ap_const_lv1_0 == or_cond_reg_1433) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it2)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (ap_ST_pp0_stg3_fsm_5 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_1446_pp0_it1) & ~(ap_const_lv1_0 == or_cond_reg_1433)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (ap_ST_pp0_stg4_fsm_6 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_1446_pp0_it1) & ~(ap_const_lv1_0 == or_cond_reg_1433)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (ap_ST_pp0_stg5_fsm_7 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_1446_pp0_it1) & ~(ap_const_lv1_0 == or_cond_reg_1433)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it2) & (ap_ST_pp1_stg4_fsm_15 == ap_CS_fsm) & ~(ap_const_lv1_0 == or_cond_reg_1433) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it2)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it2) & (ap_ST_pp1_stg5_fsm_16 == ap_CS_fsm) & ~(ap_const_lv1_0 == or_cond_reg_1433) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it2)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_reg_1446 == ap_const_lv1_0) & (ap_const_lv1_0 == or_cond_reg_1433) & (ap_ST_pp0_stg7_fsm_9 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (exitcond_reg_1446 == ap_const_lv1_0) & (ap_const_lv1_0 == or_cond_reg_1433) & (ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) | ((ap_ST_pp0_stg1_fsm_3 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_1446_pp0_it1) & (ap_const_lv1_0 == or_cond_reg_1433)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_1446_pp0_it1) & ~(ap_const_lv1_0 == or_cond_reg_1433) & (ap_ST_pp0_stg6_fsm_8 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it2) & ~(ap_const_lv1_0 == or_cond_reg_1433) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it2) & (ap_ST_pp1_stg6_fsm_17 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it2) & ~(ap_const_lv1_0 == or_cond_reg_1433) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it2) & (ap_ST_pp1_stg7_fsm_18 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it3) & ~(ap_const_lv1_0 == or_cond_reg_1433) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it2) & (ap_ST_pp1_stg0_fsm_11 == ap_CS_fsm)) | ((ap_ST_pp1_stg1_fsm_12 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it3) & ~(ap_const_lv1_0 == or_cond_reg_1433) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it3)))) begin
d_ce1 = ap_const_logic_1;
end else begin
d_ce1 = ap_const_logic_0;
end
end
/// d_d0 assign process. ///
always @ (ap_CS_fsm or ap_reg_ppiten_pp0_it0 or ap_reg_ppiten_pp0_it1 or exitcond_reg_1446 or ap_reg_ppiten_pp1_it1 or ap_reg_ppiten_pp1_it2 or reg_865 or ap_reg_ppstg_exitcond_reg_1446_pp0_it1 or or_cond_reg_1433 or ap_reg_ppstg_exitcond2_reg_1603_pp1_it2 or reg_874 or reg_890 or reg_906 or reg_922 or ap_reg_ppstg_exitcond2_reg_1603_pp1_it1 or t_reg_1831 or t8_reg_1838 or t9_reg_1845 or t10_reg_1852 or t11_reg_1859 or t12_reg_1866 or t13_reg_1873 or t14_reg_1880)
begin
if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it2) & (ap_ST_pp1_stg2_fsm_13 == ap_CS_fsm) & (ap_const_lv1_0 == or_cond_reg_1433) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it2))) begin
d_d0 = t14_reg_1880;
end else if (((ap_ST_pp1_stg1_fsm_12 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it2) & (ap_const_lv1_0 == or_cond_reg_1433) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it2))) begin
d_d0 = t13_reg_1873;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it2) & (ap_const_lv1_0 == or_cond_reg_1433) & (ap_ST_pp1_stg0_fsm_11 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it1))) begin
d_d0 = t12_reg_1866;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_const_lv1_0 == or_cond_reg_1433) & (ap_ST_pp1_stg7_fsm_18 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it1))) begin
d_d0 = t11_reg_1859;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_const_lv1_0 == or_cond_reg_1433) & (ap_ST_pp1_stg6_fsm_17 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it1))) begin
d_d0 = t10_reg_1852;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_ST_pp1_stg5_fsm_16 == ap_CS_fsm) & (ap_const_lv1_0 == or_cond_reg_1433) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it1))) begin
d_d0 = t9_reg_1845;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_ST_pp1_stg4_fsm_15 == ap_CS_fsm) & (ap_const_lv1_0 == or_cond_reg_1433) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it1))) begin
d_d0 = t8_reg_1838;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_ST_pp1_stg3_fsm_14 == ap_CS_fsm) & (ap_const_lv1_0 == or_cond_reg_1433) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it1))) begin
d_d0 = t_reg_1831;
end else if ((((ap_const_logic_1 == ap_reg_ppiten_pp1_it2) & (ap_ST_pp1_stg2_fsm_13 == ap_CS_fsm) & ~(ap_const_lv1_0 == or_cond_reg_1433) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it2)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (ap_ST_pp0_stg2_fsm_4 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_1446_pp0_it1) & ~(ap_const_lv1_0 == or_cond_reg_1433)))) begin
d_d0 = reg_922;
end else if (((ap_ST_pp0_stg1_fsm_3 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_1446_pp0_it1) & (ap_const_lv1_0 == or_cond_reg_1433))) begin
d_d0 = reg_906;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (exitcond_reg_1446 == ap_const_lv1_0) & (ap_const_lv1_0 == or_cond_reg_1433) & (ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm))) begin
d_d0 = reg_890;
end else if ((((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (ap_ST_pp0_stg3_fsm_5 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_1446_pp0_it1) & ~(ap_const_lv1_0 == or_cond_reg_1433)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (ap_ST_pp0_stg4_fsm_6 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_1446_pp0_it1) & ~(ap_const_lv1_0 == or_cond_reg_1433)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (ap_ST_pp0_stg5_fsm_7 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_1446_pp0_it1) & ~(ap_const_lv1_0 == or_cond_reg_1433)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_reg_1446 == ap_const_lv1_0) & (ap_const_lv1_0 == or_cond_reg_1433) & (ap_ST_pp0_stg7_fsm_9 == ap_CS_fsm)))) begin
d_d0 = reg_874;
end else if ((((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_reg_1446 == ap_const_lv1_0) & (ap_const_lv1_0 == or_cond_reg_1433) & (ap_ST_pp0_stg6_fsm_8 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (ap_ST_pp0_stg2_fsm_4 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_1446_pp0_it1) & (ap_const_lv1_0 == or_cond_reg_1433)))) begin
d_d0 = reg_865;
end else begin
d_d0 = t14_reg_1880;
end
end
/// d_d1 assign process. ///
always @ (ap_CS_fsm or ap_reg_ppiten_pp0_it0 or ap_reg_ppiten_pp0_it1 or exitcond_reg_1446 or ap_reg_ppiten_pp1_it2 or ap_reg_ppiten_pp1_it3 or reg_865 or ap_reg_ppstg_exitcond_reg_1446_pp0_it1 or or_cond_reg_1433 or ap_reg_ppstg_exitcond2_reg_1603_pp1_it2 or reg_882 or reg_898 or reg_914 or reg_922 or ap_reg_ppstg_exitcond2_reg_1603_pp1_it3 or tmp_57_reg_1887 or tmp_58_reg_1892 or tmp_60_reg_1897)
begin
if (((ap_ST_pp1_stg1_fsm_12 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it3) & ~(ap_const_lv1_0 == or_cond_reg_1433) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it3))) begin
d_d1 = tmp_60_reg_1897;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it2) & ~(ap_const_lv1_0 == or_cond_reg_1433) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it2) & (ap_ST_pp1_stg7_fsm_18 == ap_CS_fsm))) begin
d_d1 = tmp_58_reg_1892;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it2) & ~(ap_const_lv1_0 == or_cond_reg_1433) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it2) & (ap_ST_pp1_stg6_fsm_17 == ap_CS_fsm))) begin
d_d1 = tmp_57_reg_1887;
end else if ((((ap_const_logic_1 == ap_reg_ppiten_pp1_it2) & (ap_ST_pp1_stg4_fsm_15 == ap_CS_fsm) & ~(ap_const_lv1_0 == or_cond_reg_1433) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it2)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it3) & ~(ap_const_lv1_0 == or_cond_reg_1433) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it2) & (ap_ST_pp1_stg0_fsm_11 == ap_CS_fsm)))) begin
d_d1 = reg_922;
end else if ((((ap_const_logic_1 == ap_reg_ppiten_pp1_it2) & (ap_ST_pp1_stg3_fsm_14 == ap_CS_fsm) & ~(ap_const_lv1_0 == or_cond_reg_1433) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it2)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it2) & (ap_ST_pp1_stg5_fsm_16 == ap_CS_fsm) & ~(ap_const_lv1_0 == or_cond_reg_1433) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it2)))) begin
d_d1 = reg_865;
end else if (((ap_ST_pp0_stg1_fsm_3 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_1446_pp0_it1) & (ap_const_lv1_0 == or_cond_reg_1433))) begin
d_d1 = reg_914;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (exitcond_reg_1446 == ap_const_lv1_0) & (ap_const_lv1_0 == or_cond_reg_1433) & (ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm))) begin
d_d1 = reg_898;
end else if ((((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (ap_ST_pp0_stg3_fsm_5 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_1446_pp0_it1) & ~(ap_const_lv1_0 == or_cond_reg_1433)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (ap_ST_pp0_stg4_fsm_6 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_1446_pp0_it1) & ~(ap_const_lv1_0 == or_cond_reg_1433)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (ap_ST_pp0_stg5_fsm_7 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_1446_pp0_it1) & ~(ap_const_lv1_0 == or_cond_reg_1433)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_reg_1446 == ap_const_lv1_0) & (ap_const_lv1_0 == or_cond_reg_1433) & (ap_ST_pp0_stg7_fsm_9 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_1446_pp0_it1) & ~(ap_const_lv1_0 == or_cond_reg_1433) & (ap_ST_pp0_stg6_fsm_8 == ap_CS_fsm)))) begin
d_d1 = reg_882;
end else begin
d_d1 = tmp_60_reg_1897;
end
end
/// d_we0 assign process. ///
always @ (ap_CS_fsm or ap_reg_ppiten_pp0_it0 or ap_reg_ppiten_pp0_it1 or exitcond_reg_1446 or ap_reg_ppiten_pp1_it1 or ap_reg_ppiten_pp1_it2 or ap_reg_ppstg_exitcond_reg_1446_pp0_it1 or or_cond_reg_1433 or ap_reg_ppstg_exitcond2_reg_1603_pp1_it2 or ap_reg_ppstg_exitcond2_reg_1603_pp1_it1)
begin
if ((((ap_const_logic_1 == ap_reg_ppiten_pp1_it2) & (ap_ST_pp1_stg2_fsm_13 == ap_CS_fsm) & ~(ap_const_lv1_0 == or_cond_reg_1433) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it2)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (ap_ST_pp0_stg2_fsm_4 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_1446_pp0_it1) & ~(ap_const_lv1_0 == or_cond_reg_1433)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (ap_ST_pp0_stg3_fsm_5 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_1446_pp0_it1) & ~(ap_const_lv1_0 == or_cond_reg_1433)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (ap_ST_pp0_stg4_fsm_6 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_1446_pp0_it1) & ~(ap_const_lv1_0 == or_cond_reg_1433)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (ap_ST_pp0_stg5_fsm_7 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_1446_pp0_it1) & ~(ap_const_lv1_0 == or_cond_reg_1433)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_reg_1446 == ap_const_lv1_0) & (ap_const_lv1_0 == or_cond_reg_1433) & (ap_ST_pp0_stg6_fsm_8 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_reg_1446 == ap_const_lv1_0) & (ap_const_lv1_0 == or_cond_reg_1433) & (ap_ST_pp0_stg7_fsm_9 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (exitcond_reg_1446 == ap_const_lv1_0) & (ap_const_lv1_0 == or_cond_reg_1433) & (ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) | ((ap_ST_pp0_stg1_fsm_3 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_1446_pp0_it1) & (ap_const_lv1_0 == or_cond_reg_1433)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (ap_ST_pp0_stg2_fsm_4 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_1446_pp0_it1) & (ap_const_lv1_0 == or_cond_reg_1433)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_ST_pp1_stg3_fsm_14 == ap_CS_fsm) & (ap_const_lv1_0 == or_cond_reg_1433) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_ST_pp1_stg4_fsm_15 == ap_CS_fsm) & (ap_const_lv1_0 == or_cond_reg_1433) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_ST_pp1_stg5_fsm_16 == ap_CS_fsm) & (ap_const_lv1_0 == or_cond_reg_1433) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_const_lv1_0 == or_cond_reg_1433) & (ap_ST_pp1_stg6_fsm_17 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_const_lv1_0 == or_cond_reg_1433) & (ap_ST_pp1_stg7_fsm_18 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it2) & (ap_const_lv1_0 == or_cond_reg_1433) & (ap_ST_pp1_stg0_fsm_11 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it1)) | ((ap_ST_pp1_stg1_fsm_12 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it2) & (ap_const_lv1_0 == or_cond_reg_1433) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it2)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it2) & (ap_ST_pp1_stg2_fsm_13 == ap_CS_fsm) & (ap_const_lv1_0 == or_cond_reg_1433) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it2)))) begin
d_we0 = ap_const_logic_1;
end else begin
d_we0 = ap_const_logic_0;
end
end
/// d_we1 assign process. ///
always @ (ap_CS_fsm or ap_reg_ppiten_pp0_it0 or ap_reg_ppiten_pp0_it1 or exitcond_reg_1446 or ap_reg_ppiten_pp1_it2 or ap_reg_ppiten_pp1_it3 or ap_reg_ppstg_exitcond_reg_1446_pp0_it1 or or_cond_reg_1433 or ap_reg_ppstg_exitcond2_reg_1603_pp1_it2 or ap_reg_ppstg_exitcond2_reg_1603_pp1_it3)
begin
if ((((ap_const_logic_1 == ap_reg_ppiten_pp1_it2) & (ap_ST_pp1_stg3_fsm_14 == ap_CS_fsm) & ~(ap_const_lv1_0 == or_cond_reg_1433) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it2)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (ap_ST_pp0_stg3_fsm_5 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_1446_pp0_it1) & ~(ap_const_lv1_0 == or_cond_reg_1433)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (ap_ST_pp0_stg4_fsm_6 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_1446_pp0_it1) & ~(ap_const_lv1_0 == or_cond_reg_1433)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (ap_ST_pp0_stg5_fsm_7 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_1446_pp0_it1) & ~(ap_const_lv1_0 == or_cond_reg_1433)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it2) & (ap_ST_pp1_stg4_fsm_15 == ap_CS_fsm) & ~(ap_const_lv1_0 == or_cond_reg_1433) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it2)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it2) & (ap_ST_pp1_stg5_fsm_16 == ap_CS_fsm) & ~(ap_const_lv1_0 == or_cond_reg_1433) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it2)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_reg_1446 == ap_const_lv1_0) & (ap_const_lv1_0 == or_cond_reg_1433) & (ap_ST_pp0_stg7_fsm_9 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (exitcond_reg_1446 == ap_const_lv1_0) & (ap_const_lv1_0 == or_cond_reg_1433) & (ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) | ((ap_ST_pp0_stg1_fsm_3 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_1446_pp0_it1) & (ap_const_lv1_0 == or_cond_reg_1433)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_1446_pp0_it1) & ~(ap_const_lv1_0 == or_cond_reg_1433) & (ap_ST_pp0_stg6_fsm_8 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it2) & ~(ap_const_lv1_0 == or_cond_reg_1433) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it2) & (ap_ST_pp1_stg6_fsm_17 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it2) & ~(ap_const_lv1_0 == or_cond_reg_1433) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it2) & (ap_ST_pp1_stg7_fsm_18 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it3) & ~(ap_const_lv1_0 == or_cond_reg_1433) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it2) & (ap_ST_pp1_stg0_fsm_11 == ap_CS_fsm)) | ((ap_ST_pp1_stg1_fsm_12 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it3) & ~(ap_const_lv1_0 == or_cond_reg_1433) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it3)))) begin
d_we1 = ap_const_logic_1;
end else begin
d_we1 = ap_const_logic_0;
end
end
/// grp_fu_811_p0 assign process. ///
always @ (ap_CS_fsm or reg_823 or ap_reg_ppiten_pp1_it0 or ap_reg_ppiten_pp1_it1 or exitcond2_reg_1603 or reg_829 or reg_835 or reg_841 or reg_847 or reg_853 or reg_859 or ap_reg_ppstg_exitcond2_reg_1603_pp1_it1 or b_load_15_reg_1821)
begin
if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_ST_pp1_stg5_fsm_16 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it1))) begin
grp_fu_811_p0 = b_load_15_reg_1821;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_ST_pp1_stg4_fsm_15 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it1))) begin
grp_fu_811_p0 = reg_859;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_ST_pp1_stg3_fsm_14 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it1))) begin
grp_fu_811_p0 = reg_853;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_ST_pp1_stg2_fsm_13 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it1))) begin
grp_fu_811_p0 = reg_847;
end else if (((ap_ST_pp1_stg1_fsm_12 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it1))) begin
grp_fu_811_p0 = reg_841;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_const_lv1_0 == exitcond2_reg_1603) & (ap_ST_pp1_stg0_fsm_11 == ap_CS_fsm))) begin
grp_fu_811_p0 = reg_835;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond2_reg_1603) & (ap_ST_pp1_stg7_fsm_18 == ap_CS_fsm))) begin
grp_fu_811_p0 = reg_829;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond2_reg_1603) & (ap_ST_pp1_stg6_fsm_17 == ap_CS_fsm))) begin
grp_fu_811_p0 = reg_823;
end else begin
grp_fu_811_p0 = b_load_15_reg_1821;
end
end
/// grp_fu_811_p1 assign process. ///
always @ (ap_CS_fsm or ap_reg_ppiten_pp1_it0 or ap_reg_ppiten_pp1_it1 or exitcond2_reg_1603 or reg_865 or reg_874 or reg_882 or reg_890 or reg_898 or reg_906 or reg_914 or ap_reg_ppstg_exitcond2_reg_1603_pp1_it1 or tmp_52_reg_1826)
begin
if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_ST_pp1_stg5_fsm_16 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it1))) begin
grp_fu_811_p1 = tmp_52_reg_1826;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_ST_pp1_stg4_fsm_15 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it1))) begin
grp_fu_811_p1 = reg_914;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_ST_pp1_stg3_fsm_14 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it1))) begin
grp_fu_811_p1 = reg_906;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_ST_pp1_stg2_fsm_13 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it1))) begin
grp_fu_811_p1 = reg_898;
end else if (((ap_ST_pp1_stg1_fsm_12 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it1))) begin
grp_fu_811_p1 = reg_890;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_const_lv1_0 == exitcond2_reg_1603) & (ap_ST_pp1_stg0_fsm_11 == ap_CS_fsm))) begin
grp_fu_811_p1 = reg_882;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond2_reg_1603) & (ap_ST_pp1_stg7_fsm_18 == ap_CS_fsm))) begin
grp_fu_811_p1 = reg_874;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond2_reg_1603) & (ap_ST_pp1_stg6_fsm_17 == ap_CS_fsm))) begin
grp_fu_811_p1 = reg_865;
end else begin
grp_fu_811_p1 = tmp_52_reg_1826;
end
end
/// grp_fu_815_p0 assign process. ///
always @ (ap_CS_fsm or reg_823 or ap_reg_ppiten_pp0_it0 or ap_reg_ppiten_pp0_it1 or exitcond_reg_1446 or ap_reg_ppiten_pp1_it0 or ap_reg_ppiten_pp1_it1 or ap_reg_ppiten_pp1_it2 or exitcond2_reg_1603 or reg_829 or reg_841 or reg_853 or ap_reg_ppstg_exitcond_reg_1446_pp0_it1 or or_cond_reg_1433 or ap_reg_ppstg_exitcond2_reg_1603_pp1_it2 or reg_874 or reg_890 or reg_906 or reg_928 or ap_reg_ppstg_exitcond2_reg_1603_pp1_it1 or c_load_1_reg_1696 or c_load_3_reg_1740 or c_load_5_reg_1794 or t8_reg_1838 or t10_reg_1852 or t12_reg_1866)
begin
if (((ap_ST_pp1_stg1_fsm_12 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it2) & ~(ap_const_lv1_0 == or_cond_reg_1433) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it2))) begin
grp_fu_815_p0 = t12_reg_1866;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it2) & ~(ap_const_lv1_0 == or_cond_reg_1433) & (ap_ST_pp1_stg0_fsm_11 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it1))) begin
grp_fu_815_p0 = t10_reg_1852;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & ~(ap_const_lv1_0 == or_cond_reg_1433) & (ap_ST_pp1_stg7_fsm_18 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it1))) begin
grp_fu_815_p0 = t8_reg_1838;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond2_reg_1603) & (ap_ST_pp1_stg5_fsm_16 == ap_CS_fsm))) begin
grp_fu_815_p0 = c_load_5_reg_1794;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond2_reg_1603) & (ap_ST_pp1_stg4_fsm_15 == ap_CS_fsm))) begin
grp_fu_815_p0 = c_load_3_reg_1740;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond2_reg_1603) & (ap_ST_pp1_stg3_fsm_14 == ap_CS_fsm))) begin
grp_fu_815_p0 = c_load_1_reg_1696;
end else if ((((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond2_reg_1603) & (ap_ST_pp1_stg2_fsm_13 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond2_reg_1603) & (ap_ST_pp1_stg6_fsm_17 == ap_CS_fsm)))) begin
grp_fu_815_p0 = reg_928;
end else if (((ap_ST_pp0_stg1_fsm_3 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_1446_pp0_it1) & ~(ap_const_lv1_0 == or_cond_reg_1433))) begin
grp_fu_815_p0 = reg_906;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (exitcond_reg_1446 == ap_const_lv1_0) & ~(ap_const_lv1_0 == or_cond_reg_1433) & (ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm))) begin
grp_fu_815_p0 = reg_890;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_reg_1446 == ap_const_lv1_0) & ~(ap_const_lv1_0 == or_cond_reg_1433) & (ap_ST_pp0_stg7_fsm_9 == ap_CS_fsm))) begin
grp_fu_815_p0 = reg_874;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_reg_1446 == ap_const_lv1_0) & (ap_ST_pp0_stg5_fsm_7 == ap_CS_fsm))) begin
grp_fu_815_p0 = reg_853;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_reg_1446 == ap_const_lv1_0) & (ap_ST_pp0_stg4_fsm_6 == ap_CS_fsm))) begin
grp_fu_815_p0 = reg_841;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_reg_1446 == ap_const_lv1_0) & (ap_ST_pp0_stg3_fsm_5 == ap_CS_fsm))) begin
grp_fu_815_p0 = reg_829;
end else if ((((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_reg_1446 == ap_const_lv1_0) & (ap_ST_pp0_stg2_fsm_4 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_reg_1446 == ap_const_lv1_0) & (ap_ST_pp0_stg6_fsm_8 == ap_CS_fsm)))) begin
grp_fu_815_p0 = reg_823;
end else begin
grp_fu_815_p0 = t12_reg_1866;
end
end
/// grp_fu_815_p1 assign process. ///
always @ (ap_CS_fsm or BoundryScale or nu or PostScale or ap_reg_ppiten_pp0_it0 or ap_reg_ppiten_pp0_it1 or exitcond_reg_1446 or ap_reg_ppiten_pp1_it0 or ap_reg_ppiten_pp1_it1 or ap_reg_ppiten_pp1_it2 or exitcond2_reg_1603 or ap_reg_ppstg_exitcond_reg_1446_pp0_it1 or or_cond_reg_1433 or ap_reg_ppstg_exitcond2_reg_1603_pp1_it2 or ap_reg_ppstg_exitcond2_reg_1603_pp1_it1)
begin
if ((((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond2_reg_1603) & (ap_ST_pp1_stg2_fsm_13 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond2_reg_1603) & (ap_ST_pp1_stg3_fsm_14 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond2_reg_1603) & (ap_ST_pp1_stg4_fsm_15 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond2_reg_1603) & (ap_ST_pp1_stg5_fsm_16 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond2_reg_1603) & (ap_ST_pp1_stg6_fsm_17 == ap_CS_fsm)))) begin
grp_fu_815_p1 = nu;
end else if ((((ap_ST_pp0_stg1_fsm_3 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_1446_pp0_it1) & ~(ap_const_lv1_0 == or_cond_reg_1433)) | ((ap_ST_pp1_stg1_fsm_12 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it2) & ~(ap_const_lv1_0 == or_cond_reg_1433) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it2)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_reg_1446 == ap_const_lv1_0) & ~(ap_const_lv1_0 == or_cond_reg_1433) & (ap_ST_pp0_stg7_fsm_9 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (exitcond_reg_1446 == ap_const_lv1_0) & ~(ap_const_lv1_0 == or_cond_reg_1433) & (ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & ~(ap_const_lv1_0 == or_cond_reg_1433) & (ap_ST_pp1_stg7_fsm_18 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it2) & ~(ap_const_lv1_0 == or_cond_reg_1433) & (ap_ST_pp1_stg0_fsm_11 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it1)))) begin
grp_fu_815_p1 = PostScale;
end else if ((((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_reg_1446 == ap_const_lv1_0) & (ap_ST_pp0_stg5_fsm_7 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_reg_1446 == ap_const_lv1_0) & (ap_ST_pp0_stg2_fsm_4 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_reg_1446 == ap_const_lv1_0) & (ap_ST_pp0_stg3_fsm_5 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_reg_1446 == ap_const_lv1_0) & (ap_ST_pp0_stg4_fsm_6 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_reg_1446 == ap_const_lv1_0) & (ap_ST_pp0_stg6_fsm_8 == ap_CS_fsm)))) begin
grp_fu_815_p1 = BoundryScale;
end else begin
grp_fu_815_p1 = nu;
end
end
/// grp_fu_819_p0 assign process. ///
always @ (ap_CS_fsm or ap_reg_ppiten_pp0_it0 or ap_reg_ppiten_pp0_it1 or exitcond_reg_1446 or ap_reg_ppiten_pp1_it0 or ap_reg_ppiten_pp1_it1 or ap_reg_ppiten_pp1_it2 or exitcond2_reg_1603 or reg_835 or reg_847 or reg_859 or reg_865 or ap_reg_ppstg_exitcond_reg_1446_pp0_it1 or or_cond_reg_1433 or ap_reg_ppstg_exitcond2_reg_1603_pp1_it2 or reg_882 or reg_898 or reg_914 or ap_reg_ppstg_exitcond2_reg_1603_pp1_it1 or c_load_2_reg_1701 or c_load_4_reg_1745 or c_load_6_reg_1799 or t_reg_1831 or t9_reg_1845 or t11_reg_1859 or t13_reg_1873 or t14_reg_1880)
begin
if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it2) & (ap_ST_pp1_stg2_fsm_13 == ap_CS_fsm) & ~(ap_const_lv1_0 == or_cond_reg_1433) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it2))) begin
grp_fu_819_p0 = t14_reg_1880;
end else if (((ap_ST_pp1_stg1_fsm_12 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it2) & ~(ap_const_lv1_0 == or_cond_reg_1433) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it2))) begin
grp_fu_819_p0 = t13_reg_1873;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it2) & ~(ap_const_lv1_0 == or_cond_reg_1433) & (ap_ST_pp1_stg0_fsm_11 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it1))) begin
grp_fu_819_p0 = t11_reg_1859;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & ~(ap_const_lv1_0 == or_cond_reg_1433) & (ap_ST_pp1_stg7_fsm_18 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it1))) begin
grp_fu_819_p0 = t9_reg_1845;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & ~(ap_const_lv1_0 == or_cond_reg_1433) & (ap_ST_pp1_stg6_fsm_17 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it1))) begin
grp_fu_819_p0 = t_reg_1831;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond2_reg_1603) & (ap_ST_pp1_stg5_fsm_16 == ap_CS_fsm))) begin
grp_fu_819_p0 = c_load_6_reg_1799;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond2_reg_1603) & (ap_ST_pp1_stg4_fsm_15 == ap_CS_fsm))) begin
grp_fu_819_p0 = c_load_4_reg_1745;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond2_reg_1603) & (ap_ST_pp1_stg3_fsm_14 == ap_CS_fsm))) begin
grp_fu_819_p0 = c_load_2_reg_1701;
end else if (((ap_ST_pp0_stg1_fsm_3 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_1446_pp0_it1) & ~(ap_const_lv1_0 == or_cond_reg_1433))) begin
grp_fu_819_p0 = reg_914;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (exitcond_reg_1446 == ap_const_lv1_0) & ~(ap_const_lv1_0 == or_cond_reg_1433) & (ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm))) begin
grp_fu_819_p0 = reg_898;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_reg_1446 == ap_const_lv1_0) & ~(ap_const_lv1_0 == or_cond_reg_1433) & (ap_ST_pp0_stg7_fsm_9 == ap_CS_fsm))) begin
grp_fu_819_p0 = reg_882;
end else if ((((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (ap_ST_pp0_stg2_fsm_4 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_1446_pp0_it1) & ~(ap_const_lv1_0 == or_cond_reg_1433)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_reg_1446 == ap_const_lv1_0) & ~(ap_const_lv1_0 == or_cond_reg_1433) & (ap_ST_pp0_stg6_fsm_8 == ap_CS_fsm)))) begin
grp_fu_819_p0 = reg_865;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_reg_1446 == ap_const_lv1_0) & (ap_ST_pp0_stg5_fsm_7 == ap_CS_fsm))) begin
grp_fu_819_p0 = reg_859;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_reg_1446 == ap_const_lv1_0) & (ap_ST_pp0_stg4_fsm_6 == ap_CS_fsm))) begin
grp_fu_819_p0 = reg_847;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_reg_1446 == ap_const_lv1_0) & (ap_ST_pp0_stg3_fsm_5 == ap_CS_fsm))) begin
grp_fu_819_p0 = reg_835;
end else begin
grp_fu_819_p0 = t14_reg_1880;
end
end
/// grp_fu_819_p1 assign process. ///
always @ (ap_CS_fsm or BoundryScale or nu or PostScale or ap_reg_ppiten_pp0_it0 or ap_reg_ppiten_pp0_it1 or exitcond_reg_1446 or ap_reg_ppiten_pp1_it0 or ap_reg_ppiten_pp1_it1 or ap_reg_ppiten_pp1_it2 or exitcond2_reg_1603 or ap_reg_ppstg_exitcond_reg_1446_pp0_it1 or or_cond_reg_1433 or ap_reg_ppstg_exitcond2_reg_1603_pp1_it2 or ap_reg_ppstg_exitcond2_reg_1603_pp1_it1)
begin
if ((((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond2_reg_1603) & (ap_ST_pp1_stg3_fsm_14 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond2_reg_1603) & (ap_ST_pp1_stg4_fsm_15 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == exitcond2_reg_1603) & (ap_ST_pp1_stg5_fsm_16 == ap_CS_fsm)))) begin
grp_fu_819_p1 = nu;
end else if ((((ap_const_logic_1 == ap_reg_ppiten_pp1_it2) & (ap_ST_pp1_stg2_fsm_13 == ap_CS_fsm) & ~(ap_const_lv1_0 == or_cond_reg_1433) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it2)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (ap_ST_pp0_stg2_fsm_4 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_1446_pp0_it1) & ~(ap_const_lv1_0 == or_cond_reg_1433)) | ((ap_ST_pp0_stg1_fsm_3 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_1446_pp0_it1) & ~(ap_const_lv1_0 == or_cond_reg_1433)) | ((ap_ST_pp1_stg1_fsm_12 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it2) & ~(ap_const_lv1_0 == or_cond_reg_1433) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it2)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_reg_1446 == ap_const_lv1_0) & ~(ap_const_lv1_0 == or_cond_reg_1433) & (ap_ST_pp0_stg7_fsm_9 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (exitcond_reg_1446 == ap_const_lv1_0) & ~(ap_const_lv1_0 == or_cond_reg_1433) & (ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & ~(ap_const_lv1_0 == or_cond_reg_1433) & (ap_ST_pp1_stg7_fsm_18 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it2) & ~(ap_const_lv1_0 == or_cond_reg_1433) & (ap_ST_pp1_stg0_fsm_11 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_reg_1446 == ap_const_lv1_0) & ~(ap_const_lv1_0 == or_cond_reg_1433) & (ap_ST_pp0_stg6_fsm_8 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & ~(ap_const_lv1_0 == or_cond_reg_1433) & (ap_ST_pp1_stg6_fsm_17 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_1603_pp1_it1)))) begin
grp_fu_819_p1 = PostScale;
end else if ((((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_reg_1446 == ap_const_lv1_0) & (ap_ST_pp0_stg5_fsm_7 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_reg_1446 == ap_const_lv1_0) & (ap_ST_pp0_stg3_fsm_5 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_reg_1446 == ap_const_lv1_0) & (ap_ST_pp0_stg4_fsm_6 == ap_CS_fsm)))) begin
grp_fu_819_p1 = BoundryScale;
end else begin
grp_fu_819_p1 = nu;
end
end
/// i1_phi_fu_781_p4 assign process. ///
always @ (ap_CS_fsm or i1_reg_777 or ap_reg_ppiten_pp1_it1 or exitcond2_reg_1603 or i1_mid2_reg_1624)
begin
if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_const_lv1_0 == exitcond2_reg_1603) & (ap_ST_pp1_stg0_fsm_11 == ap_CS_fsm))) begin
i1_phi_fu_781_p4 = i1_mid2_reg_1624;
end else begin
i1_phi_fu_781_p4 = i1_reg_777;
end
end
/// i_phi_fu_737_p4 assign process. ///
always @ (ap_CS_fsm or i_reg_733 or ap_reg_ppiten_pp0_it1 or exitcond_reg_1446 or i_mid2_reg_1467)
begin
if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (exitcond_reg_1446 == ap_const_lv1_0) & (ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm))) begin
i_phi_fu_737_p4 = i_mid2_reg_1467;
end else begin
i_phi_fu_737_p4 = i_reg_733;
end
end
/// indvar3_phi_fu_748_p4 assign process. ///
always @ (ap_CS_fsm or indvar3_reg_744 or ap_reg_ppiten_pp0_it1 or exitcond_reg_1446 or indvar_next4_reg_1495)
begin
if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (exitcond_reg_1446 == ap_const_lv1_0) & (ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm))) begin
indvar3_phi_fu_748_p4 = indvar_next4_reg_1495;
end else begin
indvar3_phi_fu_748_p4 = indvar3_reg_744;
end
end
/// indvar_flatten9_phi_fu_770_p4 assign process. ///
always @ (ap_CS_fsm or indvar_flatten9_reg_766 or ap_reg_ppiten_pp1_it1 or exitcond2_reg_1603 or indvar_flatten_next1_reg_1607)
begin
if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_const_lv1_0 == exitcond2_reg_1603) & (ap_ST_pp1_stg0_fsm_11 == ap_CS_fsm))) begin
indvar_flatten9_phi_fu_770_p4 = indvar_flatten_next1_reg_1607;
end else begin
indvar_flatten9_phi_fu_770_p4 = indvar_flatten9_reg_766;
end
end
/// indvar_flatten_phi_fu_726_p4 assign process. ///
always @ (ap_CS_fsm or indvar_flatten_reg_722 or ap_reg_ppiten_pp0_it1 or exitcond_reg_1446 or indvar_flatten_next_reg_1450)
begin
if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (exitcond_reg_1446 == ap_const_lv1_0) & (ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm))) begin
indvar_flatten_phi_fu_726_p4 = indvar_flatten_next_reg_1450;
end else begin
indvar_flatten_phi_fu_726_p4 = indvar_flatten_reg_722;
end
end
/// indvar_phi_fu_792_p4 assign process. ///
always @ (ap_CS_fsm or indvar_reg_788 or ap_reg_ppiten_pp1_it1 or exitcond2_reg_1603 or indvar_next_reg_1657)
begin
if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_const_lv1_0 == exitcond2_reg_1603) & (ap_ST_pp1_stg0_fsm_11 == ap_CS_fsm))) begin
indvar_phi_fu_792_p4 = indvar_next_reg_1657;
end else begin
indvar_phi_fu_792_p4 = indvar_reg_788;
end
end
/// j1_phi_fu_803_p4 assign process. ///
always @ (ap_CS_fsm or j1_reg_799 or ap_reg_ppiten_pp1_it1 or exitcond2_reg_1603 or tmp_61_reg_1789)
begin
if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_const_lv1_0 == exitcond2_reg_1603) & (ap_ST_pp1_stg0_fsm_11 == ap_CS_fsm))) begin
j1_phi_fu_803_p4 = tmp_61_reg_1789;
end else begin
j1_phi_fu_803_p4 = j1_reg_799;
end
end
/// j_phi_fu_759_p4 assign process. ///
always @ (ap_CS_fsm or j_reg_755 or ap_reg_ppiten_pp0_it1 or exitcond_reg_1446 or tmp_28_reg_1577)
begin
if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (exitcond_reg_1446 == ap_const_lv1_0) & (ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm))) begin
j_phi_fu_759_p4 = tmp_28_reg_1577;
end else begin
j_phi_fu_759_p4 = j_reg_755;
end
end
assign b_addr10_fu_1251_p2 = (b_addr9_cast_fu_1247_p1 + tmp_32_trn_cast_fu_1237_p1);
assign b_addr11_fu_1286_p2 = (b_addr9_cast_reg_1629 + tmp_35_trn_cast_fu_1282_p1);
assign b_addr12_fu_1306_p2 = (b_addr9_cast_reg_1629 + tmp_38_trn_cast_fu_1302_p1);
assign b_addr13_fu_1326_p2 = (b_addr9_cast_reg_1629 + tmp_41_trn_cast_fu_1322_p1);
assign b_addr14_fu_1346_p2 = (b_addr9_cast_reg_1629 + tmp_44_trn_cast_fu_1342_p1);
assign b_addr15_fu_1366_p2 = (b_addr9_cast_reg_1629 + tmp_47_trn_cast_fu_1362_p1);
assign b_addr16_fu_1386_p2 = (b_addr9_cast_reg_1629 + tmp_50_trn_cast_fu_1382_p1);
assign b_addr17_fu_1406_p2 = (b_addr9_cast_reg_1629 + tmp_53_trn_cast_fu_1402_p1);
assign b_addr1_fu_1015_p2 = (b_addr_cast_fu_1011_p1 + tmp_7_trn_cast_fu_1001_p1);
assign b_addr2_fu_1049_p2 = (b_addr_cast_reg_1472 + tmp_9_trn_cast_fu_1045_p1);
assign b_addr3_fu_1068_p2 = (b_addr_cast_reg_1472 + tmp_10_trn_cast_fu_1064_p1);
assign b_addr4_fu_1087_p2 = (b_addr_cast_reg_1472 + tmp_12_trn_cast_fu_1083_p1);
assign b_addr5_fu_1106_p2 = (b_addr_cast_reg_1472 + tmp_14_trn_cast_fu_1102_p1);
assign b_addr6_fu_1125_p2 = (b_addr_cast_reg_1472 + tmp_16_trn_cast_fu_1121_p1);
assign b_addr7_fu_1144_p2 = (b_addr_cast_reg_1472 + tmp_18_trn_cast_fu_1140_p1);
assign b_addr8_fu_1163_p2 = (b_addr_cast_reg_1472 + tmp_20_trn_cast_fu_1159_p1);
assign b_addr9_cast_fu_1247_p1 = {{1{1'b0}}, {b_addr9_fu_1241_p2}};
assign b_addr9_fu_1241_p2 = tmp_29_trn_cast_fu_1233_p1 << ap_const_lv13_6;
assign b_addr_cast_fu_1011_p1 = {{1{1'b0}}, {b_addr_fu_1005_p2}};
assign b_addr_fu_1005_p2 = tmp_3_trn_cast_fu_997_p1 << ap_const_lv13_6;
assign exitcond1_fu_969_p2 = (indvar3_phi_fu_748_p4 == ap_const_lv4_8? 1'b1: 1'b0);
assign exitcond2_fu_1193_p2 = (indvar_flatten9_phi_fu_770_p4 == ap_const_lv10_200? 1'b1: 1'b0);
assign exitcond3_fu_1205_p2 = (indvar_phi_fu_792_p4 == ap_const_lv4_8? 1'b1: 1'b0);
assign exitcond_fu_957_p2 = (indvar_flatten_phi_fu_726_p4 == ap_const_lv10_200? 1'b1: 1'b0);
assign grp_fu_811_ce = ap_const_logic_1;
assign grp_fu_815_ce = ap_const_logic_1;
assign grp_fu_819_ce = ap_const_logic_1;
assign i1_mid2_fu_1225_p3 = ((exitcond3_fu_1205_p2)? tmp_31_dup_fu_1219_p2: i1_phi_fu_781_p4);
assign i_mid2_fu_989_p3 = ((exitcond1_fu_969_p2)? tmp_6_dup_fu_983_p2: i_phi_fu_737_p4);
assign indvar3_op_fu_1026_p2 = (indvar3_phi_fu_748_p4 + ap_const_lv4_1);
assign indvar_op_fu_1263_p2 = (indvar_phi_fu_792_p4 + ap_const_lv4_1);
assign j1_mid2_fu_1211_p3 = ((exitcond3_fu_1205_p2)? ap_const_lv7_0: j1_phi_fu_803_p4);
assign j_mid2_fu_975_p3 = ((exitcond1_fu_969_p2)? ap_const_lv7_0: j_phi_fu_759_p4);
assign or_cond1_fu_1187_p2 = (tmp_4_fu_1177_p2 & tmp_5_fu_1182_p2);
assign tmp_10_fu_1078_p2 = (j_mid2_reg_1455 | ap_const_lv7_3);
assign tmp_10_trn_cast_fu_1064_p1 = {{7{1'b0}}, {tmp_s_fu_1059_p2}};
assign tmp_11_fu_1092_p1 = {{50{1'b0}}, {b_addr4_fu_1087_p2}};
assign tmp_12_fu_1097_p2 = (j_mid2_reg_1455 | ap_const_lv7_4);
assign tmp_12_trn_cast_fu_1083_p1 = {{7{1'b0}}, {tmp_10_fu_1078_p2}};
assign tmp_13_fu_1111_p1 = {{50{1'b0}}, {b_addr5_fu_1106_p2}};
assign tmp_14_fu_1116_p2 = (j_mid2_reg_1455 | ap_const_lv7_5);
assign tmp_14_trn_cast_fu_1102_p1 = {{7{1'b0}}, {tmp_12_fu_1097_p2}};
assign tmp_15_fu_1130_p1 = {{50{1'b0}}, {b_addr6_fu_1125_p2}};
assign tmp_16_fu_1135_p2 = (j_mid2_reg_1455 | ap_const_lv7_6);
assign tmp_16_trn_cast_fu_1121_p1 = {{7{1'b0}}, {tmp_14_fu_1116_p2}};
assign tmp_17_fu_1149_p1 = {{50{1'b0}}, {b_addr7_fu_1144_p2}};
assign tmp_18_fu_1154_p2 = (j_mid2_reg_1455 | ap_const_lv7_7);
assign tmp_18_trn_cast_fu_1140_p1 = {{7{1'b0}}, {tmp_16_fu_1135_p2}};
assign tmp_19_fu_1173_p1 = {{50{1'b0}}, {b_addr8_reg_1572}};
assign tmp_1_fu_939_p2 = (step ^ ap_const_lv1_1);
assign tmp_20_trn_cast_fu_1159_p1 = {{7{1'b0}}, {tmp_18_fu_1154_p2}};
assign tmp_29_trn_cast_fu_1233_p1 = {{6{1'b0}}, {i1_mid2_fu_1225_p3}};
assign tmp_2_fu_951_p2 = (counter == ap_const_lv7_2? 1'b1: 1'b0);
assign tmp_30_fu_1257_p1 = {{50{1'b0}}, {b_addr10_fu_1251_p2}};
assign tmp_31_dup_fu_1219_p2 = (i1_phi_fu_781_p4 + ap_const_lv7_1);
assign tmp_32_fu_1277_p2 = (j1_mid2_reg_1612 | ap_const_lv7_1);
assign tmp_32_trn_cast_fu_1237_p1 = {{7{1'b0}}, {j1_mid2_fu_1211_p3}};
assign tmp_33_fu_1291_p1 = {{50{1'b0}}, {b_addr11_fu_1286_p2}};
assign tmp_35_fu_1297_p2 = (j1_mid2_reg_1612 | ap_const_lv7_2);
assign tmp_35_trn_cast_fu_1282_p1 = {{7{1'b0}}, {tmp_32_fu_1277_p2}};
assign tmp_36_fu_1311_p1 = {{50{1'b0}}, {b_addr12_fu_1306_p2}};
assign tmp_38_fu_1317_p2 = (j1_mid2_reg_1612 | ap_const_lv7_3);
assign tmp_38_trn_cast_fu_1302_p1 = {{7{1'b0}}, {tmp_35_fu_1297_p2}};
assign tmp_39_fu_1331_p1 = {{50{1'b0}}, {b_addr13_fu_1326_p2}};
assign tmp_3_trn_cast_fu_997_p1 = {{6{1'b0}}, {i_mid2_fu_989_p3}};
assign tmp_41_fu_1337_p2 = (j1_mid2_reg_1612 | ap_const_lv7_4);
assign tmp_41_trn_cast_fu_1322_p1 = {{7{1'b0}}, {tmp_38_fu_1317_p2}};
assign tmp_42_fu_1351_p1 = {{50{1'b0}}, {b_addr14_fu_1346_p2}};
assign tmp_44_fu_1357_p2 = (j1_mid2_reg_1612 | ap_const_lv7_5);
assign tmp_44_trn_cast_fu_1342_p1 = {{7{1'b0}}, {tmp_41_fu_1337_p2}};
assign tmp_45_fu_1371_p1 = {{50{1'b0}}, {b_addr15_fu_1366_p2}};
assign tmp_47_fu_1377_p2 = (j1_mid2_reg_1612 | ap_const_lv7_6);
assign tmp_47_trn_cast_fu_1362_p1 = {{7{1'b0}}, {tmp_44_fu_1357_p2}};
assign tmp_48_fu_1391_p1 = {{50{1'b0}}, {b_addr16_fu_1386_p2}};
assign tmp_4_fu_1177_p2 = (counter < ap_const_lv7_42? 1'b1: 1'b0);
assign tmp_50_fu_1397_p2 = (j1_mid2_reg_1612 | ap_const_lv7_7);
assign tmp_50_trn_cast_fu_1382_p1 = {{7{1'b0}}, {tmp_47_fu_1377_p2}};
assign tmp_51_fu_1416_p1 = {{50{1'b0}}, {b_addr17_reg_1784}};
assign tmp_53_trn_cast_fu_1402_p1 = {{7{1'b0}}, {tmp_50_fu_1397_p2}};
assign tmp_5_fu_1182_p2 = (counter > ap_const_lv7_2? 1'b1: 1'b0);
assign tmp_6_dup_fu_983_p2 = (i_phi_fu_737_p4 + ap_const_lv7_1);
assign tmp_6_fu_1021_p1 = {{50{1'b0}}, {b_addr1_fu_1015_p2}};
assign tmp_7_fu_1054_p1 = {{50{1'b0}}, {b_addr2_fu_1049_p2}};
assign tmp_7_trn_cast_fu_1001_p1 = {{7{1'b0}}, {j_mid2_fu_975_p3}};
assign tmp_8_fu_1040_p2 = (j_mid2_reg_1455 | ap_const_lv7_1);
assign tmp_9_fu_1073_p1 = {{50{1'b0}}, {b_addr3_fu_1068_p2}};
assign tmp_9_trn_cast_fu_1045_p1 = {{7{1'b0}}, {tmp_8_fu_1040_p2}};
assign tmp_fu_933_p2 = (tag == ap_const_lv2_1? 1'b1: 1'b0);
assign tmp_s_fu_1059_p2 = (j_mid2_reg_1455 | ap_const_lv7_2);
always @ (ap_clk)
begin
b_addr_cast_reg_1472[0] <= 1'b0;
b_addr_cast_reg_1472[1] <= 1'b0;
b_addr_cast_reg_1472[2] <= 1'b0;
b_addr_cast_reg_1472[3] <= 1'b0;
b_addr_cast_reg_1472[4] <= 1'b0;
b_addr_cast_reg_1472[5] <= 1'b0;
b_addr_cast_reg_1472[13] <= 1'b0;
end
always @ (ap_clk)
begin
tmp_6_reg_1483[14] <= 1'b0;
tmp_6_reg_1483[15] <= 1'b0;
tmp_6_reg_1483[16] <= 1'b0;
tmp_6_reg_1483[17] <= 1'b0;
tmp_6_reg_1483[18] <= 1'b0;
tmp_6_reg_1483[19] <= 1'b0;
tmp_6_reg_1483[20] <= 1'b0;
tmp_6_reg_1483[21] <= 1'b0;
tmp_6_reg_1483[22] <= 1'b0;
tmp_6_reg_1483[23] <= 1'b0;
tmp_6_reg_1483[24] <= 1'b0;
tmp_6_reg_1483[25] <= 1'b0;
tmp_6_reg_1483[26] <= 1'b0;
tmp_6_reg_1483[27] <= 1'b0;
tmp_6_reg_1483[28] <= 1'b0;
tmp_6_reg_1483[29] <= 1'b0;
tmp_6_reg_1483[30] <= 1'b0;
tmp_6_reg_1483[31] <= 1'b0;
tmp_6_reg_1483[32] <= 1'b0;
tmp_6_reg_1483[33] <= 1'b0;
tmp_6_reg_1483[34] <= 1'b0;
tmp_6_reg_1483[35] <= 1'b0;
tmp_6_reg_1483[36] <= 1'b0;
tmp_6_reg_1483[37] <= 1'b0;
tmp_6_reg_1483[38] <= 1'b0;
tmp_6_reg_1483[39] <= 1'b0;
tmp_6_reg_1483[40] <= 1'b0;
tmp_6_reg_1483[41] <= 1'b0;
tmp_6_reg_1483[42] <= 1'b0;
tmp_6_reg_1483[43] <= 1'b0;
tmp_6_reg_1483[44] <= 1'b0;
tmp_6_reg_1483[45] <= 1'b0;
tmp_6_reg_1483[46] <= 1'b0;
tmp_6_reg_1483[47] <= 1'b0;
tmp_6_reg_1483[48] <= 1'b0;
tmp_6_reg_1483[49] <= 1'b0;
tmp_6_reg_1483[50] <= 1'b0;
tmp_6_reg_1483[51] <= 1'b0;
tmp_6_reg_1483[52] <= 1'b0;
tmp_6_reg_1483[53] <= 1'b0;
tmp_6_reg_1483[54] <= 1'b0;
tmp_6_reg_1483[55] <= 1'b0;
tmp_6_reg_1483[56] <= 1'b0;
tmp_6_reg_1483[57] <= 1'b0;
tmp_6_reg_1483[58] <= 1'b0;
tmp_6_reg_1483[59] <= 1'b0;
tmp_6_reg_1483[60] <= 1'b0;
tmp_6_reg_1483[61] <= 1'b0;
tmp_6_reg_1483[62] <= 1'b0;
tmp_6_reg_1483[63] <= 1'b0;
end
always @ (ap_clk)
begin
ap_reg_ppstg_tmp_6_reg_1483_pp0_it1[14] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_1483_pp0_it1[15] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_1483_pp0_it1[16] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_1483_pp0_it1[17] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_1483_pp0_it1[18] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_1483_pp0_it1[19] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_1483_pp0_it1[20] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_1483_pp0_it1[21] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_1483_pp0_it1[22] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_1483_pp0_it1[23] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_1483_pp0_it1[24] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_1483_pp0_it1[25] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_1483_pp0_it1[26] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_1483_pp0_it1[27] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_1483_pp0_it1[28] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_1483_pp0_it1[29] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_1483_pp0_it1[30] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_1483_pp0_it1[31] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_1483_pp0_it1[32] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_1483_pp0_it1[33] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_1483_pp0_it1[34] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_1483_pp0_it1[35] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_1483_pp0_it1[36] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_1483_pp0_it1[37] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_1483_pp0_it1[38] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_1483_pp0_it1[39] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_1483_pp0_it1[40] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_1483_pp0_it1[41] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_1483_pp0_it1[42] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_1483_pp0_it1[43] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_1483_pp0_it1[44] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_1483_pp0_it1[45] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_1483_pp0_it1[46] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_1483_pp0_it1[47] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_1483_pp0_it1[48] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_1483_pp0_it1[49] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_1483_pp0_it1[50] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_1483_pp0_it1[51] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_1483_pp0_it1[52] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_1483_pp0_it1[53] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_1483_pp0_it1[54] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_1483_pp0_it1[55] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_1483_pp0_it1[56] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_1483_pp0_it1[57] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_1483_pp0_it1[58] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_1483_pp0_it1[59] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_1483_pp0_it1[60] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_1483_pp0_it1[61] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_1483_pp0_it1[62] <= 1'b0;
ap_reg_ppstg_tmp_6_reg_1483_pp0_it1[63] <= 1'b0;
end
always @ (ap_clk)
begin
tmp_7_reg_1500[0] <= 1'b1;
tmp_7_reg_1500[14] <= 1'b0;
tmp_7_reg_1500[15] <= 1'b0;
tmp_7_reg_1500[16] <= 1'b0;
tmp_7_reg_1500[17] <= 1'b0;
tmp_7_reg_1500[18] <= 1'b0;
tmp_7_reg_1500[19] <= 1'b0;
tmp_7_reg_1500[20] <= 1'b0;
tmp_7_reg_1500[21] <= 1'b0;
tmp_7_reg_1500[22] <= 1'b0;
tmp_7_reg_1500[23] <= 1'b0;
tmp_7_reg_1500[24] <= 1'b0;
tmp_7_reg_1500[25] <= 1'b0;
tmp_7_reg_1500[26] <= 1'b0;
tmp_7_reg_1500[27] <= 1'b0;
tmp_7_reg_1500[28] <= 1'b0;
tmp_7_reg_1500[29] <= 1'b0;
tmp_7_reg_1500[30] <= 1'b0;
tmp_7_reg_1500[31] <= 1'b0;
tmp_7_reg_1500[32] <= 1'b0;
tmp_7_reg_1500[33] <= 1'b0;
tmp_7_reg_1500[34] <= 1'b0;
tmp_7_reg_1500[35] <= 1'b0;
tmp_7_reg_1500[36] <= 1'b0;
tmp_7_reg_1500[37] <= 1'b0;
tmp_7_reg_1500[38] <= 1'b0;
tmp_7_reg_1500[39] <= 1'b0;
tmp_7_reg_1500[40] <= 1'b0;
tmp_7_reg_1500[41] <= 1'b0;
tmp_7_reg_1500[42] <= 1'b0;
tmp_7_reg_1500[43] <= 1'b0;
tmp_7_reg_1500[44] <= 1'b0;
tmp_7_reg_1500[45] <= 1'b0;
tmp_7_reg_1500[46] <= 1'b0;
tmp_7_reg_1500[47] <= 1'b0;
tmp_7_reg_1500[48] <= 1'b0;
tmp_7_reg_1500[49] <= 1'b0;
tmp_7_reg_1500[50] <= 1'b0;
tmp_7_reg_1500[51] <= 1'b0;
tmp_7_reg_1500[52] <= 1'b0;
tmp_7_reg_1500[53] <= 1'b0;
tmp_7_reg_1500[54] <= 1'b0;
tmp_7_reg_1500[55] <= 1'b0;
tmp_7_reg_1500[56] <= 1'b0;
tmp_7_reg_1500[57] <= 1'b0;
tmp_7_reg_1500[58] <= 1'b0;
tmp_7_reg_1500[59] <= 1'b0;
tmp_7_reg_1500[60] <= 1'b0;
tmp_7_reg_1500[61] <= 1'b0;
tmp_7_reg_1500[62] <= 1'b0;
tmp_7_reg_1500[63] <= 1'b0;
end
always @ (ap_clk)
begin
ap_reg_ppstg_tmp_7_reg_1500_pp0_it1[0] <= 1'b1;
ap_reg_ppstg_tmp_7_reg_1500_pp0_it1[14] <= 1'b0;
ap_reg_ppstg_tmp_7_reg_1500_pp0_it1[15] <= 1'b0;
ap_reg_ppstg_tmp_7_reg_1500_pp0_it1[16] <= 1'b0;
ap_reg_ppstg_tmp_7_reg_1500_pp0_it1[17] <= 1'b0;
ap_reg_ppstg_tmp_7_reg_1500_pp0_it1[18] <= 1'b0;
ap_reg_ppstg_tmp_7_reg_1500_pp0_it1[19] <= 1'b0;
ap_reg_ppstg_tmp_7_reg_1500_pp0_it1[20] <= 1'b0;
ap_reg_ppstg_tmp_7_reg_1500_pp0_it1[21] <= 1'b0;
ap_reg_ppstg_tmp_7_reg_1500_pp0_it1[22] <= 1'b0;
ap_reg_ppstg_tmp_7_reg_1500_pp0_it1[23] <= 1'b0;
ap_reg_ppstg_tmp_7_reg_1500_pp0_it1[24] <= 1'b0;
ap_reg_ppstg_tmp_7_reg_1500_pp0_it1[25] <= 1'b0;
ap_reg_ppstg_tmp_7_reg_1500_pp0_it1[26] <= 1'b0;
ap_reg_ppstg_tmp_7_reg_1500_pp0_it1[27] <= 1'b0;
ap_reg_ppstg_tmp_7_reg_1500_pp0_it1[28] <= 1'b0;
ap_reg_ppstg_tmp_7_reg_1500_pp0_it1[29] <= 1'b0;
ap_reg_ppstg_tmp_7_reg_1500_pp0_it1[30] <= 1'b0;
ap_reg_ppstg_tmp_7_reg_1500_pp0_it1[31] <= 1'b0;
ap_reg_ppstg_tmp_7_reg_1500_pp0_it1[32] <= 1'b0;
ap_reg_ppstg_tmp_7_reg_1500_pp0_it1[33] <= 1'b0;
ap_reg_ppstg_tmp_7_reg_1500_pp0_it1[34] <= 1'b0;
ap_reg_ppstg_tmp_7_reg_1500_pp0_it1[35] <= 1'b0;
ap_reg_ppstg_tmp_7_reg_1500_pp0_it1[36] <= 1'b0;
ap_reg_ppstg_tmp_7_reg_1500_pp0_it1[37] <= 1'b0;
ap_reg_ppstg_tmp_7_reg_1500_pp0_it1[38] <= 1'b0;
ap_reg_ppstg_tmp_7_reg_1500_pp0_it1[39] <= 1'b0;
ap_reg_ppstg_tmp_7_reg_1500_pp0_it1[40] <= 1'b0;
ap_reg_ppstg_tmp_7_reg_1500_pp0_it1[41] <= 1'b0;
ap_reg_ppstg_tmp_7_reg_1500_pp0_it1[42] <= 1'b0;
ap_reg_ppstg_tmp_7_reg_1500_pp0_it1[43] <= 1'b0;
ap_reg_ppstg_tmp_7_reg_1500_pp0_it1[44] <= 1'b0;
ap_reg_ppstg_tmp_7_reg_1500_pp0_it1[45] <= 1'b0;
ap_reg_ppstg_tmp_7_reg_1500_pp0_it1[46] <= 1'b0;
ap_reg_ppstg_tmp_7_reg_1500_pp0_it1[47] <= 1'b0;
ap_reg_ppstg_tmp_7_reg_1500_pp0_it1[48] <= 1'b0;
ap_reg_ppstg_tmp_7_reg_1500_pp0_it1[49] <= 1'b0;
ap_reg_ppstg_tmp_7_reg_1500_pp0_it1[50] <= 1'b0;
ap_reg_ppstg_tmp_7_reg_1500_pp0_it1[51] <= 1'b0;
ap_reg_ppstg_tmp_7_reg_1500_pp0_it1[52] <= 1'b0;
ap_reg_ppstg_tmp_7_reg_1500_pp0_it1[53] <= 1'b0;
ap_reg_ppstg_tmp_7_reg_1500_pp0_it1[54] <= 1'b0;
ap_reg_ppstg_tmp_7_reg_1500_pp0_it1[55] <= 1'b0;
ap_reg_ppstg_tmp_7_reg_1500_pp0_it1[56] <= 1'b0;
ap_reg_ppstg_tmp_7_reg_1500_pp0_it1[57] <= 1'b0;
ap_reg_ppstg_tmp_7_reg_1500_pp0_it1[58] <= 1'b0;
ap_reg_ppstg_tmp_7_reg_1500_pp0_it1[59] <= 1'b0;
ap_reg_ppstg_tmp_7_reg_1500_pp0_it1[60] <= 1'b0;
ap_reg_ppstg_tmp_7_reg_1500_pp0_it1[61] <= 1'b0;
ap_reg_ppstg_tmp_7_reg_1500_pp0_it1[62] <= 1'b0;
ap_reg_ppstg_tmp_7_reg_1500_pp0_it1[63] <= 1'b0;
end
always @ (ap_clk)
begin
tmp_9_reg_1512[14] <= 1'b0;
tmp_9_reg_1512[15] <= 1'b0;
tmp_9_reg_1512[16] <= 1'b0;
tmp_9_reg_1512[17] <= 1'b0;
tmp_9_reg_1512[18] <= 1'b0;
tmp_9_reg_1512[19] <= 1'b0;
tmp_9_reg_1512[20] <= 1'b0;
tmp_9_reg_1512[21] <= 1'b0;
tmp_9_reg_1512[22] <= 1'b0;
tmp_9_reg_1512[23] <= 1'b0;
tmp_9_reg_1512[24] <= 1'b0;
tmp_9_reg_1512[25] <= 1'b0;
tmp_9_reg_1512[26] <= 1'b0;
tmp_9_reg_1512[27] <= 1'b0;
tmp_9_reg_1512[28] <= 1'b0;
tmp_9_reg_1512[29] <= 1'b0;
tmp_9_reg_1512[30] <= 1'b0;
tmp_9_reg_1512[31] <= 1'b0;
tmp_9_reg_1512[32] <= 1'b0;
tmp_9_reg_1512[33] <= 1'b0;
tmp_9_reg_1512[34] <= 1'b0;
tmp_9_reg_1512[35] <= 1'b0;
tmp_9_reg_1512[36] <= 1'b0;
tmp_9_reg_1512[37] <= 1'b0;
tmp_9_reg_1512[38] <= 1'b0;
tmp_9_reg_1512[39] <= 1'b0;
tmp_9_reg_1512[40] <= 1'b0;
tmp_9_reg_1512[41] <= 1'b0;
tmp_9_reg_1512[42] <= 1'b0;
tmp_9_reg_1512[43] <= 1'b0;
tmp_9_reg_1512[44] <= 1'b0;
tmp_9_reg_1512[45] <= 1'b0;
tmp_9_reg_1512[46] <= 1'b0;
tmp_9_reg_1512[47] <= 1'b0;
tmp_9_reg_1512[48] <= 1'b0;
tmp_9_reg_1512[49] <= 1'b0;
tmp_9_reg_1512[50] <= 1'b0;
tmp_9_reg_1512[51] <= 1'b0;
tmp_9_reg_1512[52] <= 1'b0;
tmp_9_reg_1512[53] <= 1'b0;
tmp_9_reg_1512[54] <= 1'b0;
tmp_9_reg_1512[55] <= 1'b0;
tmp_9_reg_1512[56] <= 1'b0;
tmp_9_reg_1512[57] <= 1'b0;
tmp_9_reg_1512[58] <= 1'b0;
tmp_9_reg_1512[59] <= 1'b0;
tmp_9_reg_1512[60] <= 1'b0;
tmp_9_reg_1512[61] <= 1'b0;
tmp_9_reg_1512[62] <= 1'b0;
tmp_9_reg_1512[63] <= 1'b0;
end
always @ (ap_clk)
begin
ap_reg_ppstg_tmp_9_reg_1512_pp0_it1[14] <= 1'b0;
ap_reg_ppstg_tmp_9_reg_1512_pp0_it1[15] <= 1'b0;
ap_reg_ppstg_tmp_9_reg_1512_pp0_it1[16] <= 1'b0;
ap_reg_ppstg_tmp_9_reg_1512_pp0_it1[17] <= 1'b0;
ap_reg_ppstg_tmp_9_reg_1512_pp0_it1[18] <= 1'b0;
ap_reg_ppstg_tmp_9_reg_1512_pp0_it1[19] <= 1'b0;
ap_reg_ppstg_tmp_9_reg_1512_pp0_it1[20] <= 1'b0;
ap_reg_ppstg_tmp_9_reg_1512_pp0_it1[21] <= 1'b0;
ap_reg_ppstg_tmp_9_reg_1512_pp0_it1[22] <= 1'b0;
ap_reg_ppstg_tmp_9_reg_1512_pp0_it1[23] <= 1'b0;
ap_reg_ppstg_tmp_9_reg_1512_pp0_it1[24] <= 1'b0;
ap_reg_ppstg_tmp_9_reg_1512_pp0_it1[25] <= 1'b0;
ap_reg_ppstg_tmp_9_reg_1512_pp0_it1[26] <= 1'b0;
ap_reg_ppstg_tmp_9_reg_1512_pp0_it1[27] <= 1'b0;
ap_reg_ppstg_tmp_9_reg_1512_pp0_it1[28] <= 1'b0;
ap_reg_ppstg_tmp_9_reg_1512_pp0_it1[29] <= 1'b0;
ap_reg_ppstg_tmp_9_reg_1512_pp0_it1[30] <= 1'b0;
ap_reg_ppstg_tmp_9_reg_1512_pp0_it1[31] <= 1'b0;
ap_reg_ppstg_tmp_9_reg_1512_pp0_it1[32] <= 1'b0;
ap_reg_ppstg_tmp_9_reg_1512_pp0_it1[33] <= 1'b0;
ap_reg_ppstg_tmp_9_reg_1512_pp0_it1[34] <= 1'b0;
ap_reg_ppstg_tmp_9_reg_1512_pp0_it1[35] <= 1'b0;
ap_reg_ppstg_tmp_9_reg_1512_pp0_it1[36] <= 1'b0;
ap_reg_ppstg_tmp_9_reg_1512_pp0_it1[37] <= 1'b0;
ap_reg_ppstg_tmp_9_reg_1512_pp0_it1[38] <= 1'b0;
ap_reg_ppstg_tmp_9_reg_1512_pp0_it1[39] <= 1'b0;
ap_reg_ppstg_tmp_9_reg_1512_pp0_it1[40] <= 1'b0;
ap_reg_ppstg_tmp_9_reg_1512_pp0_it1[41] <= 1'b0;
ap_reg_ppstg_tmp_9_reg_1512_pp0_it1[42] <= 1'b0;
ap_reg_ppstg_tmp_9_reg_1512_pp0_it1[43] <= 1'b0;
ap_reg_ppstg_tmp_9_reg_1512_pp0_it1[44] <= 1'b0;
ap_reg_ppstg_tmp_9_reg_1512_pp0_it1[45] <= 1'b0;
ap_reg_ppstg_tmp_9_reg_1512_pp0_it1[46] <= 1'b0;
ap_reg_ppstg_tmp_9_reg_1512_pp0_it1[47] <= 1'b0;
ap_reg_ppstg_tmp_9_reg_1512_pp0_it1[48] <= 1'b0;
ap_reg_ppstg_tmp_9_reg_1512_pp0_it1[49] <= 1'b0;
ap_reg_ppstg_tmp_9_reg_1512_pp0_it1[50] <= 1'b0;
ap_reg_ppstg_tmp_9_reg_1512_pp0_it1[51] <= 1'b0;
ap_reg_ppstg_tmp_9_reg_1512_pp0_it1[52] <= 1'b0;
ap_reg_ppstg_tmp_9_reg_1512_pp0_it1[53] <= 1'b0;
ap_reg_ppstg_tmp_9_reg_1512_pp0_it1[54] <= 1'b0;
ap_reg_ppstg_tmp_9_reg_1512_pp0_it1[55] <= 1'b0;
ap_reg_ppstg_tmp_9_reg_1512_pp0_it1[56] <= 1'b0;
ap_reg_ppstg_tmp_9_reg_1512_pp0_it1[57] <= 1'b0;
ap_reg_ppstg_tmp_9_reg_1512_pp0_it1[58] <= 1'b0;
ap_reg_ppstg_tmp_9_reg_1512_pp0_it1[59] <= 1'b0;
ap_reg_ppstg_tmp_9_reg_1512_pp0_it1[60] <= 1'b0;
ap_reg_ppstg_tmp_9_reg_1512_pp0_it1[61] <= 1'b0;
ap_reg_ppstg_tmp_9_reg_1512_pp0_it1[62] <= 1'b0;
ap_reg_ppstg_tmp_9_reg_1512_pp0_it1[63] <= 1'b0;
end
always @ (ap_clk)
begin
tmp_11_reg_1524[0] <= 1'b1;
tmp_11_reg_1524[1] <= 1'b1;
tmp_11_reg_1524[14] <= 1'b0;
tmp_11_reg_1524[15] <= 1'b0;
tmp_11_reg_1524[16] <= 1'b0;
tmp_11_reg_1524[17] <= 1'b0;
tmp_11_reg_1524[18] <= 1'b0;
tmp_11_reg_1524[19] <= 1'b0;
tmp_11_reg_1524[20] <= 1'b0;
tmp_11_reg_1524[21] <= 1'b0;
tmp_11_reg_1524[22] <= 1'b0;
tmp_11_reg_1524[23] <= 1'b0;
tmp_11_reg_1524[24] <= 1'b0;
tmp_11_reg_1524[25] <= 1'b0;
tmp_11_reg_1524[26] <= 1'b0;
tmp_11_reg_1524[27] <= 1'b0;
tmp_11_reg_1524[28] <= 1'b0;
tmp_11_reg_1524[29] <= 1'b0;
tmp_11_reg_1524[30] <= 1'b0;
tmp_11_reg_1524[31] <= 1'b0;
tmp_11_reg_1524[32] <= 1'b0;
tmp_11_reg_1524[33] <= 1'b0;
tmp_11_reg_1524[34] <= 1'b0;
tmp_11_reg_1524[35] <= 1'b0;
tmp_11_reg_1524[36] <= 1'b0;
tmp_11_reg_1524[37] <= 1'b0;
tmp_11_reg_1524[38] <= 1'b0;
tmp_11_reg_1524[39] <= 1'b0;
tmp_11_reg_1524[40] <= 1'b0;
tmp_11_reg_1524[41] <= 1'b0;
tmp_11_reg_1524[42] <= 1'b0;
tmp_11_reg_1524[43] <= 1'b0;
tmp_11_reg_1524[44] <= 1'b0;
tmp_11_reg_1524[45] <= 1'b0;
tmp_11_reg_1524[46] <= 1'b0;
tmp_11_reg_1524[47] <= 1'b0;
tmp_11_reg_1524[48] <= 1'b0;
tmp_11_reg_1524[49] <= 1'b0;
tmp_11_reg_1524[50] <= 1'b0;
tmp_11_reg_1524[51] <= 1'b0;
tmp_11_reg_1524[52] <= 1'b0;
tmp_11_reg_1524[53] <= 1'b0;
tmp_11_reg_1524[54] <= 1'b0;
tmp_11_reg_1524[55] <= 1'b0;
tmp_11_reg_1524[56] <= 1'b0;
tmp_11_reg_1524[57] <= 1'b0;
tmp_11_reg_1524[58] <= 1'b0;
tmp_11_reg_1524[59] <= 1'b0;
tmp_11_reg_1524[60] <= 1'b0;
tmp_11_reg_1524[61] <= 1'b0;
tmp_11_reg_1524[62] <= 1'b0;
tmp_11_reg_1524[63] <= 1'b0;
end
always @ (ap_clk)
begin
ap_reg_ppstg_tmp_11_reg_1524_pp0_it1[0] <= 1'b1;
ap_reg_ppstg_tmp_11_reg_1524_pp0_it1[1] <= 1'b1;
ap_reg_ppstg_tmp_11_reg_1524_pp0_it1[14] <= 1'b0;
ap_reg_ppstg_tmp_11_reg_1524_pp0_it1[15] <= 1'b0;
ap_reg_ppstg_tmp_11_reg_1524_pp0_it1[16] <= 1'b0;
ap_reg_ppstg_tmp_11_reg_1524_pp0_it1[17] <= 1'b0;
ap_reg_ppstg_tmp_11_reg_1524_pp0_it1[18] <= 1'b0;
ap_reg_ppstg_tmp_11_reg_1524_pp0_it1[19] <= 1'b0;
ap_reg_ppstg_tmp_11_reg_1524_pp0_it1[20] <= 1'b0;
ap_reg_ppstg_tmp_11_reg_1524_pp0_it1[21] <= 1'b0;
ap_reg_ppstg_tmp_11_reg_1524_pp0_it1[22] <= 1'b0;
ap_reg_ppstg_tmp_11_reg_1524_pp0_it1[23] <= 1'b0;
ap_reg_ppstg_tmp_11_reg_1524_pp0_it1[24] <= 1'b0;
ap_reg_ppstg_tmp_11_reg_1524_pp0_it1[25] <= 1'b0;
ap_reg_ppstg_tmp_11_reg_1524_pp0_it1[26] <= 1'b0;
ap_reg_ppstg_tmp_11_reg_1524_pp0_it1[27] <= 1'b0;
ap_reg_ppstg_tmp_11_reg_1524_pp0_it1[28] <= 1'b0;
ap_reg_ppstg_tmp_11_reg_1524_pp0_it1[29] <= 1'b0;
ap_reg_ppstg_tmp_11_reg_1524_pp0_it1[30] <= 1'b0;
ap_reg_ppstg_tmp_11_reg_1524_pp0_it1[31] <= 1'b0;
ap_reg_ppstg_tmp_11_reg_1524_pp0_it1[32] <= 1'b0;
ap_reg_ppstg_tmp_11_reg_1524_pp0_it1[33] <= 1'b0;
ap_reg_ppstg_tmp_11_reg_1524_pp0_it1[34] <= 1'b0;
ap_reg_ppstg_tmp_11_reg_1524_pp0_it1[35] <= 1'b0;
ap_reg_ppstg_tmp_11_reg_1524_pp0_it1[36] <= 1'b0;
ap_reg_ppstg_tmp_11_reg_1524_pp0_it1[37] <= 1'b0;
ap_reg_ppstg_tmp_11_reg_1524_pp0_it1[38] <= 1'b0;
ap_reg_ppstg_tmp_11_reg_1524_pp0_it1[39] <= 1'b0;
ap_reg_ppstg_tmp_11_reg_1524_pp0_it1[40] <= 1'b0;
ap_reg_ppstg_tmp_11_reg_1524_pp0_it1[41] <= 1'b0;
ap_reg_ppstg_tmp_11_reg_1524_pp0_it1[42] <= 1'b0;
ap_reg_ppstg_tmp_11_reg_1524_pp0_it1[43] <= 1'b0;
ap_reg_ppstg_tmp_11_reg_1524_pp0_it1[44] <= 1'b0;
ap_reg_ppstg_tmp_11_reg_1524_pp0_it1[45] <= 1'b0;
ap_reg_ppstg_tmp_11_reg_1524_pp0_it1[46] <= 1'b0;
ap_reg_ppstg_tmp_11_reg_1524_pp0_it1[47] <= 1'b0;
ap_reg_ppstg_tmp_11_reg_1524_pp0_it1[48] <= 1'b0;
ap_reg_ppstg_tmp_11_reg_1524_pp0_it1[49] <= 1'b0;
ap_reg_ppstg_tmp_11_reg_1524_pp0_it1[50] <= 1'b0;
ap_reg_ppstg_tmp_11_reg_1524_pp0_it1[51] <= 1'b0;
ap_reg_ppstg_tmp_11_reg_1524_pp0_it1[52] <= 1'b0;
ap_reg_ppstg_tmp_11_reg_1524_pp0_it1[53] <= 1'b0;
ap_reg_ppstg_tmp_11_reg_1524_pp0_it1[54] <= 1'b0;
ap_reg_ppstg_tmp_11_reg_1524_pp0_it1[55] <= 1'b0;
ap_reg_ppstg_tmp_11_reg_1524_pp0_it1[56] <= 1'b0;
ap_reg_ppstg_tmp_11_reg_1524_pp0_it1[57] <= 1'b0;
ap_reg_ppstg_tmp_11_reg_1524_pp0_it1[58] <= 1'b0;
ap_reg_ppstg_tmp_11_reg_1524_pp0_it1[59] <= 1'b0;
ap_reg_ppstg_tmp_11_reg_1524_pp0_it1[60] <= 1'b0;
ap_reg_ppstg_tmp_11_reg_1524_pp0_it1[61] <= 1'b0;
ap_reg_ppstg_tmp_11_reg_1524_pp0_it1[62] <= 1'b0;
ap_reg_ppstg_tmp_11_reg_1524_pp0_it1[63] <= 1'b0;
end
always @ (ap_clk)
begin
tmp_13_reg_1536[14] <= 1'b0;
tmp_13_reg_1536[15] <= 1'b0;
tmp_13_reg_1536[16] <= 1'b0;
tmp_13_reg_1536[17] <= 1'b0;
tmp_13_reg_1536[18] <= 1'b0;
tmp_13_reg_1536[19] <= 1'b0;
tmp_13_reg_1536[20] <= 1'b0;
tmp_13_reg_1536[21] <= 1'b0;
tmp_13_reg_1536[22] <= 1'b0;
tmp_13_reg_1536[23] <= 1'b0;
tmp_13_reg_1536[24] <= 1'b0;
tmp_13_reg_1536[25] <= 1'b0;
tmp_13_reg_1536[26] <= 1'b0;
tmp_13_reg_1536[27] <= 1'b0;
tmp_13_reg_1536[28] <= 1'b0;
tmp_13_reg_1536[29] <= 1'b0;
tmp_13_reg_1536[30] <= 1'b0;
tmp_13_reg_1536[31] <= 1'b0;
tmp_13_reg_1536[32] <= 1'b0;
tmp_13_reg_1536[33] <= 1'b0;
tmp_13_reg_1536[34] <= 1'b0;
tmp_13_reg_1536[35] <= 1'b0;
tmp_13_reg_1536[36] <= 1'b0;
tmp_13_reg_1536[37] <= 1'b0;
tmp_13_reg_1536[38] <= 1'b0;
tmp_13_reg_1536[39] <= 1'b0;
tmp_13_reg_1536[40] <= 1'b0;
tmp_13_reg_1536[41] <= 1'b0;
tmp_13_reg_1536[42] <= 1'b0;
tmp_13_reg_1536[43] <= 1'b0;
tmp_13_reg_1536[44] <= 1'b0;
tmp_13_reg_1536[45] <= 1'b0;
tmp_13_reg_1536[46] <= 1'b0;
tmp_13_reg_1536[47] <= 1'b0;
tmp_13_reg_1536[48] <= 1'b0;
tmp_13_reg_1536[49] <= 1'b0;
tmp_13_reg_1536[50] <= 1'b0;
tmp_13_reg_1536[51] <= 1'b0;
tmp_13_reg_1536[52] <= 1'b0;
tmp_13_reg_1536[53] <= 1'b0;
tmp_13_reg_1536[54] <= 1'b0;
tmp_13_reg_1536[55] <= 1'b0;
tmp_13_reg_1536[56] <= 1'b0;
tmp_13_reg_1536[57] <= 1'b0;
tmp_13_reg_1536[58] <= 1'b0;
tmp_13_reg_1536[59] <= 1'b0;
tmp_13_reg_1536[60] <= 1'b0;
tmp_13_reg_1536[61] <= 1'b0;
tmp_13_reg_1536[62] <= 1'b0;
tmp_13_reg_1536[63] <= 1'b0;
end
always @ (ap_clk)
begin
ap_reg_ppstg_tmp_13_reg_1536_pp0_it1[14] <= 1'b0;
ap_reg_ppstg_tmp_13_reg_1536_pp0_it1[15] <= 1'b0;
ap_reg_ppstg_tmp_13_reg_1536_pp0_it1[16] <= 1'b0;
ap_reg_ppstg_tmp_13_reg_1536_pp0_it1[17] <= 1'b0;
ap_reg_ppstg_tmp_13_reg_1536_pp0_it1[18] <= 1'b0;
ap_reg_ppstg_tmp_13_reg_1536_pp0_it1[19] <= 1'b0;
ap_reg_ppstg_tmp_13_reg_1536_pp0_it1[20] <= 1'b0;
ap_reg_ppstg_tmp_13_reg_1536_pp0_it1[21] <= 1'b0;
ap_reg_ppstg_tmp_13_reg_1536_pp0_it1[22] <= 1'b0;
ap_reg_ppstg_tmp_13_reg_1536_pp0_it1[23] <= 1'b0;
ap_reg_ppstg_tmp_13_reg_1536_pp0_it1[24] <= 1'b0;
ap_reg_ppstg_tmp_13_reg_1536_pp0_it1[25] <= 1'b0;
ap_reg_ppstg_tmp_13_reg_1536_pp0_it1[26] <= 1'b0;
ap_reg_ppstg_tmp_13_reg_1536_pp0_it1[27] <= 1'b0;
ap_reg_ppstg_tmp_13_reg_1536_pp0_it1[28] <= 1'b0;
ap_reg_ppstg_tmp_13_reg_1536_pp0_it1[29] <= 1'b0;
ap_reg_ppstg_tmp_13_reg_1536_pp0_it1[30] <= 1'b0;
ap_reg_ppstg_tmp_13_reg_1536_pp0_it1[31] <= 1'b0;
ap_reg_ppstg_tmp_13_reg_1536_pp0_it1[32] <= 1'b0;
ap_reg_ppstg_tmp_13_reg_1536_pp0_it1[33] <= 1'b0;
ap_reg_ppstg_tmp_13_reg_1536_pp0_it1[34] <= 1'b0;
ap_reg_ppstg_tmp_13_reg_1536_pp0_it1[35] <= 1'b0;
ap_reg_ppstg_tmp_13_reg_1536_pp0_it1[36] <= 1'b0;
ap_reg_ppstg_tmp_13_reg_1536_pp0_it1[37] <= 1'b0;
ap_reg_ppstg_tmp_13_reg_1536_pp0_it1[38] <= 1'b0;
ap_reg_ppstg_tmp_13_reg_1536_pp0_it1[39] <= 1'b0;
ap_reg_ppstg_tmp_13_reg_1536_pp0_it1[40] <= 1'b0;
ap_reg_ppstg_tmp_13_reg_1536_pp0_it1[41] <= 1'b0;
ap_reg_ppstg_tmp_13_reg_1536_pp0_it1[42] <= 1'b0;
ap_reg_ppstg_tmp_13_reg_1536_pp0_it1[43] <= 1'b0;
ap_reg_ppstg_tmp_13_reg_1536_pp0_it1[44] <= 1'b0;
ap_reg_ppstg_tmp_13_reg_1536_pp0_it1[45] <= 1'b0;
ap_reg_ppstg_tmp_13_reg_1536_pp0_it1[46] <= 1'b0;
ap_reg_ppstg_tmp_13_reg_1536_pp0_it1[47] <= 1'b0;
ap_reg_ppstg_tmp_13_reg_1536_pp0_it1[48] <= 1'b0;
ap_reg_ppstg_tmp_13_reg_1536_pp0_it1[49] <= 1'b0;
ap_reg_ppstg_tmp_13_reg_1536_pp0_it1[50] <= 1'b0;
ap_reg_ppstg_tmp_13_reg_1536_pp0_it1[51] <= 1'b0;
ap_reg_ppstg_tmp_13_reg_1536_pp0_it1[52] <= 1'b0;
ap_reg_ppstg_tmp_13_reg_1536_pp0_it1[53] <= 1'b0;
ap_reg_ppstg_tmp_13_reg_1536_pp0_it1[54] <= 1'b0;
ap_reg_ppstg_tmp_13_reg_1536_pp0_it1[55] <= 1'b0;
ap_reg_ppstg_tmp_13_reg_1536_pp0_it1[56] <= 1'b0;
ap_reg_ppstg_tmp_13_reg_1536_pp0_it1[57] <= 1'b0;
ap_reg_ppstg_tmp_13_reg_1536_pp0_it1[58] <= 1'b0;
ap_reg_ppstg_tmp_13_reg_1536_pp0_it1[59] <= 1'b0;
ap_reg_ppstg_tmp_13_reg_1536_pp0_it1[60] <= 1'b0;
ap_reg_ppstg_tmp_13_reg_1536_pp0_it1[61] <= 1'b0;
ap_reg_ppstg_tmp_13_reg_1536_pp0_it1[62] <= 1'b0;
ap_reg_ppstg_tmp_13_reg_1536_pp0_it1[63] <= 1'b0;
end
always @ (ap_clk)
begin
tmp_15_reg_1548[0] <= 1'b1;
tmp_15_reg_1548[14] <= 1'b0;
tmp_15_reg_1548[15] <= 1'b0;
tmp_15_reg_1548[16] <= 1'b0;
tmp_15_reg_1548[17] <= 1'b0;
tmp_15_reg_1548[18] <= 1'b0;
tmp_15_reg_1548[19] <= 1'b0;
tmp_15_reg_1548[20] <= 1'b0;
tmp_15_reg_1548[21] <= 1'b0;
tmp_15_reg_1548[22] <= 1'b0;
tmp_15_reg_1548[23] <= 1'b0;
tmp_15_reg_1548[24] <= 1'b0;
tmp_15_reg_1548[25] <= 1'b0;
tmp_15_reg_1548[26] <= 1'b0;
tmp_15_reg_1548[27] <= 1'b0;
tmp_15_reg_1548[28] <= 1'b0;
tmp_15_reg_1548[29] <= 1'b0;
tmp_15_reg_1548[30] <= 1'b0;
tmp_15_reg_1548[31] <= 1'b0;
tmp_15_reg_1548[32] <= 1'b0;
tmp_15_reg_1548[33] <= 1'b0;
tmp_15_reg_1548[34] <= 1'b0;
tmp_15_reg_1548[35] <= 1'b0;
tmp_15_reg_1548[36] <= 1'b0;
tmp_15_reg_1548[37] <= 1'b0;
tmp_15_reg_1548[38] <= 1'b0;
tmp_15_reg_1548[39] <= 1'b0;
tmp_15_reg_1548[40] <= 1'b0;
tmp_15_reg_1548[41] <= 1'b0;
tmp_15_reg_1548[42] <= 1'b0;
tmp_15_reg_1548[43] <= 1'b0;
tmp_15_reg_1548[44] <= 1'b0;
tmp_15_reg_1548[45] <= 1'b0;
tmp_15_reg_1548[46] <= 1'b0;
tmp_15_reg_1548[47] <= 1'b0;
tmp_15_reg_1548[48] <= 1'b0;
tmp_15_reg_1548[49] <= 1'b0;
tmp_15_reg_1548[50] <= 1'b0;
tmp_15_reg_1548[51] <= 1'b0;
tmp_15_reg_1548[52] <= 1'b0;
tmp_15_reg_1548[53] <= 1'b0;
tmp_15_reg_1548[54] <= 1'b0;
tmp_15_reg_1548[55] <= 1'b0;
tmp_15_reg_1548[56] <= 1'b0;
tmp_15_reg_1548[57] <= 1'b0;
tmp_15_reg_1548[58] <= 1'b0;
tmp_15_reg_1548[59] <= 1'b0;
tmp_15_reg_1548[60] <= 1'b0;
tmp_15_reg_1548[61] <= 1'b0;
tmp_15_reg_1548[62] <= 1'b0;
tmp_15_reg_1548[63] <= 1'b0;
end
always @ (ap_clk)
begin
ap_reg_ppstg_tmp_15_reg_1548_pp0_it1[0] <= 1'b1;
ap_reg_ppstg_tmp_15_reg_1548_pp0_it1[14] <= 1'b0;
ap_reg_ppstg_tmp_15_reg_1548_pp0_it1[15] <= 1'b0;
ap_reg_ppstg_tmp_15_reg_1548_pp0_it1[16] <= 1'b0;
ap_reg_ppstg_tmp_15_reg_1548_pp0_it1[17] <= 1'b0;
ap_reg_ppstg_tmp_15_reg_1548_pp0_it1[18] <= 1'b0;
ap_reg_ppstg_tmp_15_reg_1548_pp0_it1[19] <= 1'b0;
ap_reg_ppstg_tmp_15_reg_1548_pp0_it1[20] <= 1'b0;
ap_reg_ppstg_tmp_15_reg_1548_pp0_it1[21] <= 1'b0;
ap_reg_ppstg_tmp_15_reg_1548_pp0_it1[22] <= 1'b0;
ap_reg_ppstg_tmp_15_reg_1548_pp0_it1[23] <= 1'b0;
ap_reg_ppstg_tmp_15_reg_1548_pp0_it1[24] <= 1'b0;
ap_reg_ppstg_tmp_15_reg_1548_pp0_it1[25] <= 1'b0;
ap_reg_ppstg_tmp_15_reg_1548_pp0_it1[26] <= 1'b0;
ap_reg_ppstg_tmp_15_reg_1548_pp0_it1[27] <= 1'b0;
ap_reg_ppstg_tmp_15_reg_1548_pp0_it1[28] <= 1'b0;
ap_reg_ppstg_tmp_15_reg_1548_pp0_it1[29] <= 1'b0;
ap_reg_ppstg_tmp_15_reg_1548_pp0_it1[30] <= 1'b0;
ap_reg_ppstg_tmp_15_reg_1548_pp0_it1[31] <= 1'b0;
ap_reg_ppstg_tmp_15_reg_1548_pp0_it1[32] <= 1'b0;
ap_reg_ppstg_tmp_15_reg_1548_pp0_it1[33] <= 1'b0;
ap_reg_ppstg_tmp_15_reg_1548_pp0_it1[34] <= 1'b0;
ap_reg_ppstg_tmp_15_reg_1548_pp0_it1[35] <= 1'b0;
ap_reg_ppstg_tmp_15_reg_1548_pp0_it1[36] <= 1'b0;
ap_reg_ppstg_tmp_15_reg_1548_pp0_it1[37] <= 1'b0;
ap_reg_ppstg_tmp_15_reg_1548_pp0_it1[38] <= 1'b0;
ap_reg_ppstg_tmp_15_reg_1548_pp0_it1[39] <= 1'b0;
ap_reg_ppstg_tmp_15_reg_1548_pp0_it1[40] <= 1'b0;
ap_reg_ppstg_tmp_15_reg_1548_pp0_it1[41] <= 1'b0;
ap_reg_ppstg_tmp_15_reg_1548_pp0_it1[42] <= 1'b0;
ap_reg_ppstg_tmp_15_reg_1548_pp0_it1[43] <= 1'b0;
ap_reg_ppstg_tmp_15_reg_1548_pp0_it1[44] <= 1'b0;
ap_reg_ppstg_tmp_15_reg_1548_pp0_it1[45] <= 1'b0;
ap_reg_ppstg_tmp_15_reg_1548_pp0_it1[46] <= 1'b0;
ap_reg_ppstg_tmp_15_reg_1548_pp0_it1[47] <= 1'b0;
ap_reg_ppstg_tmp_15_reg_1548_pp0_it1[48] <= 1'b0;
ap_reg_ppstg_tmp_15_reg_1548_pp0_it1[49] <= 1'b0;
ap_reg_ppstg_tmp_15_reg_1548_pp0_it1[50] <= 1'b0;
ap_reg_ppstg_tmp_15_reg_1548_pp0_it1[51] <= 1'b0;
ap_reg_ppstg_tmp_15_reg_1548_pp0_it1[52] <= 1'b0;
ap_reg_ppstg_tmp_15_reg_1548_pp0_it1[53] <= 1'b0;
ap_reg_ppstg_tmp_15_reg_1548_pp0_it1[54] <= 1'b0;
ap_reg_ppstg_tmp_15_reg_1548_pp0_it1[55] <= 1'b0;
ap_reg_ppstg_tmp_15_reg_1548_pp0_it1[56] <= 1'b0;
ap_reg_ppstg_tmp_15_reg_1548_pp0_it1[57] <= 1'b0;
ap_reg_ppstg_tmp_15_reg_1548_pp0_it1[58] <= 1'b0;
ap_reg_ppstg_tmp_15_reg_1548_pp0_it1[59] <= 1'b0;
ap_reg_ppstg_tmp_15_reg_1548_pp0_it1[60] <= 1'b0;
ap_reg_ppstg_tmp_15_reg_1548_pp0_it1[61] <= 1'b0;
ap_reg_ppstg_tmp_15_reg_1548_pp0_it1[62] <= 1'b0;
ap_reg_ppstg_tmp_15_reg_1548_pp0_it1[63] <= 1'b0;
end
always @ (ap_clk)
begin
tmp_17_reg_1560[14] <= 1'b0;
tmp_17_reg_1560[15] <= 1'b0;
tmp_17_reg_1560[16] <= 1'b0;
tmp_17_reg_1560[17] <= 1'b0;
tmp_17_reg_1560[18] <= 1'b0;
tmp_17_reg_1560[19] <= 1'b0;
tmp_17_reg_1560[20] <= 1'b0;
tmp_17_reg_1560[21] <= 1'b0;
tmp_17_reg_1560[22] <= 1'b0;
tmp_17_reg_1560[23] <= 1'b0;
tmp_17_reg_1560[24] <= 1'b0;
tmp_17_reg_1560[25] <= 1'b0;
tmp_17_reg_1560[26] <= 1'b0;
tmp_17_reg_1560[27] <= 1'b0;
tmp_17_reg_1560[28] <= 1'b0;
tmp_17_reg_1560[29] <= 1'b0;
tmp_17_reg_1560[30] <= 1'b0;
tmp_17_reg_1560[31] <= 1'b0;
tmp_17_reg_1560[32] <= 1'b0;
tmp_17_reg_1560[33] <= 1'b0;
tmp_17_reg_1560[34] <= 1'b0;
tmp_17_reg_1560[35] <= 1'b0;
tmp_17_reg_1560[36] <= 1'b0;
tmp_17_reg_1560[37] <= 1'b0;
tmp_17_reg_1560[38] <= 1'b0;
tmp_17_reg_1560[39] <= 1'b0;
tmp_17_reg_1560[40] <= 1'b0;
tmp_17_reg_1560[41] <= 1'b0;
tmp_17_reg_1560[42] <= 1'b0;
tmp_17_reg_1560[43] <= 1'b0;
tmp_17_reg_1560[44] <= 1'b0;
tmp_17_reg_1560[45] <= 1'b0;
tmp_17_reg_1560[46] <= 1'b0;
tmp_17_reg_1560[47] <= 1'b0;
tmp_17_reg_1560[48] <= 1'b0;
tmp_17_reg_1560[49] <= 1'b0;
tmp_17_reg_1560[50] <= 1'b0;
tmp_17_reg_1560[51] <= 1'b0;
tmp_17_reg_1560[52] <= 1'b0;
tmp_17_reg_1560[53] <= 1'b0;
tmp_17_reg_1560[54] <= 1'b0;
tmp_17_reg_1560[55] <= 1'b0;
tmp_17_reg_1560[56] <= 1'b0;
tmp_17_reg_1560[57] <= 1'b0;
tmp_17_reg_1560[58] <= 1'b0;
tmp_17_reg_1560[59] <= 1'b0;
tmp_17_reg_1560[60] <= 1'b0;
tmp_17_reg_1560[61] <= 1'b0;
tmp_17_reg_1560[62] <= 1'b0;
tmp_17_reg_1560[63] <= 1'b0;
end
always @ (ap_clk)
begin
ap_reg_ppstg_tmp_17_reg_1560_pp0_it1[14] <= 1'b0;
ap_reg_ppstg_tmp_17_reg_1560_pp0_it1[15] <= 1'b0;
ap_reg_ppstg_tmp_17_reg_1560_pp0_it1[16] <= 1'b0;
ap_reg_ppstg_tmp_17_reg_1560_pp0_it1[17] <= 1'b0;
ap_reg_ppstg_tmp_17_reg_1560_pp0_it1[18] <= 1'b0;
ap_reg_ppstg_tmp_17_reg_1560_pp0_it1[19] <= 1'b0;
ap_reg_ppstg_tmp_17_reg_1560_pp0_it1[20] <= 1'b0;
ap_reg_ppstg_tmp_17_reg_1560_pp0_it1[21] <= 1'b0;
ap_reg_ppstg_tmp_17_reg_1560_pp0_it1[22] <= 1'b0;
ap_reg_ppstg_tmp_17_reg_1560_pp0_it1[23] <= 1'b0;
ap_reg_ppstg_tmp_17_reg_1560_pp0_it1[24] <= 1'b0;
ap_reg_ppstg_tmp_17_reg_1560_pp0_it1[25] <= 1'b0;
ap_reg_ppstg_tmp_17_reg_1560_pp0_it1[26] <= 1'b0;
ap_reg_ppstg_tmp_17_reg_1560_pp0_it1[27] <= 1'b0;
ap_reg_ppstg_tmp_17_reg_1560_pp0_it1[28] <= 1'b0;
ap_reg_ppstg_tmp_17_reg_1560_pp0_it1[29] <= 1'b0;
ap_reg_ppstg_tmp_17_reg_1560_pp0_it1[30] <= 1'b0;
ap_reg_ppstg_tmp_17_reg_1560_pp0_it1[31] <= 1'b0;
ap_reg_ppstg_tmp_17_reg_1560_pp0_it1[32] <= 1'b0;
ap_reg_ppstg_tmp_17_reg_1560_pp0_it1[33] <= 1'b0;
ap_reg_ppstg_tmp_17_reg_1560_pp0_it1[34] <= 1'b0;
ap_reg_ppstg_tmp_17_reg_1560_pp0_it1[35] <= 1'b0;
ap_reg_ppstg_tmp_17_reg_1560_pp0_it1[36] <= 1'b0;
ap_reg_ppstg_tmp_17_reg_1560_pp0_it1[37] <= 1'b0;
ap_reg_ppstg_tmp_17_reg_1560_pp0_it1[38] <= 1'b0;
ap_reg_ppstg_tmp_17_reg_1560_pp0_it1[39] <= 1'b0;
ap_reg_ppstg_tmp_17_reg_1560_pp0_it1[40] <= 1'b0;
ap_reg_ppstg_tmp_17_reg_1560_pp0_it1[41] <= 1'b0;
ap_reg_ppstg_tmp_17_reg_1560_pp0_it1[42] <= 1'b0;
ap_reg_ppstg_tmp_17_reg_1560_pp0_it1[43] <= 1'b0;
ap_reg_ppstg_tmp_17_reg_1560_pp0_it1[44] <= 1'b0;
ap_reg_ppstg_tmp_17_reg_1560_pp0_it1[45] <= 1'b0;
ap_reg_ppstg_tmp_17_reg_1560_pp0_it1[46] <= 1'b0;
ap_reg_ppstg_tmp_17_reg_1560_pp0_it1[47] <= 1'b0;
ap_reg_ppstg_tmp_17_reg_1560_pp0_it1[48] <= 1'b0;
ap_reg_ppstg_tmp_17_reg_1560_pp0_it1[49] <= 1'b0;
ap_reg_ppstg_tmp_17_reg_1560_pp0_it1[50] <= 1'b0;
ap_reg_ppstg_tmp_17_reg_1560_pp0_it1[51] <= 1'b0;
ap_reg_ppstg_tmp_17_reg_1560_pp0_it1[52] <= 1'b0;
ap_reg_ppstg_tmp_17_reg_1560_pp0_it1[53] <= 1'b0;
ap_reg_ppstg_tmp_17_reg_1560_pp0_it1[54] <= 1'b0;
ap_reg_ppstg_tmp_17_reg_1560_pp0_it1[55] <= 1'b0;
ap_reg_ppstg_tmp_17_reg_1560_pp0_it1[56] <= 1'b0;
ap_reg_ppstg_tmp_17_reg_1560_pp0_it1[57] <= 1'b0;
ap_reg_ppstg_tmp_17_reg_1560_pp0_it1[58] <= 1'b0;
ap_reg_ppstg_tmp_17_reg_1560_pp0_it1[59] <= 1'b0;
ap_reg_ppstg_tmp_17_reg_1560_pp0_it1[60] <= 1'b0;
ap_reg_ppstg_tmp_17_reg_1560_pp0_it1[61] <= 1'b0;
ap_reg_ppstg_tmp_17_reg_1560_pp0_it1[62] <= 1'b0;
ap_reg_ppstg_tmp_17_reg_1560_pp0_it1[63] <= 1'b0;
end
always @ (ap_clk)
begin
b_addr8_reg_1572[0] <= 1'b1;
b_addr8_reg_1572[1] <= 1'b1;
b_addr8_reg_1572[2] <= 1'b1;
end
always @ (ap_clk)
begin
tmp_19_reg_1582[0] <= 1'b1;
tmp_19_reg_1582[1] <= 1'b1;
tmp_19_reg_1582[2] <= 1'b1;
tmp_19_reg_1582[14] <= 1'b0;
tmp_19_reg_1582[15] <= 1'b0;
tmp_19_reg_1582[16] <= 1'b0;
tmp_19_reg_1582[17] <= 1'b0;
tmp_19_reg_1582[18] <= 1'b0;
tmp_19_reg_1582[19] <= 1'b0;
tmp_19_reg_1582[20] <= 1'b0;
tmp_19_reg_1582[21] <= 1'b0;
tmp_19_reg_1582[22] <= 1'b0;
tmp_19_reg_1582[23] <= 1'b0;
tmp_19_reg_1582[24] <= 1'b0;
tmp_19_reg_1582[25] <= 1'b0;
tmp_19_reg_1582[26] <= 1'b0;
tmp_19_reg_1582[27] <= 1'b0;
tmp_19_reg_1582[28] <= 1'b0;
tmp_19_reg_1582[29] <= 1'b0;
tmp_19_reg_1582[30] <= 1'b0;
tmp_19_reg_1582[31] <= 1'b0;
tmp_19_reg_1582[32] <= 1'b0;
tmp_19_reg_1582[33] <= 1'b0;
tmp_19_reg_1582[34] <= 1'b0;
tmp_19_reg_1582[35] <= 1'b0;
tmp_19_reg_1582[36] <= 1'b0;
tmp_19_reg_1582[37] <= 1'b0;
tmp_19_reg_1582[38] <= 1'b0;
tmp_19_reg_1582[39] <= 1'b0;
tmp_19_reg_1582[40] <= 1'b0;
tmp_19_reg_1582[41] <= 1'b0;
tmp_19_reg_1582[42] <= 1'b0;
tmp_19_reg_1582[43] <= 1'b0;
tmp_19_reg_1582[44] <= 1'b0;
tmp_19_reg_1582[45] <= 1'b0;
tmp_19_reg_1582[46] <= 1'b0;
tmp_19_reg_1582[47] <= 1'b0;
tmp_19_reg_1582[48] <= 1'b0;
tmp_19_reg_1582[49] <= 1'b0;
tmp_19_reg_1582[50] <= 1'b0;
tmp_19_reg_1582[51] <= 1'b0;
tmp_19_reg_1582[52] <= 1'b0;
tmp_19_reg_1582[53] <= 1'b0;
tmp_19_reg_1582[54] <= 1'b0;
tmp_19_reg_1582[55] <= 1'b0;
tmp_19_reg_1582[56] <= 1'b0;
tmp_19_reg_1582[57] <= 1'b0;
tmp_19_reg_1582[58] <= 1'b0;
tmp_19_reg_1582[59] <= 1'b0;
tmp_19_reg_1582[60] <= 1'b0;
tmp_19_reg_1582[61] <= 1'b0;
tmp_19_reg_1582[62] <= 1'b0;
tmp_19_reg_1582[63] <= 1'b0;
end
always @ (ap_clk)
begin
ap_reg_ppstg_tmp_19_reg_1582_pp0_it1[0] <= 1'b1;
ap_reg_ppstg_tmp_19_reg_1582_pp0_it1[1] <= 1'b1;
ap_reg_ppstg_tmp_19_reg_1582_pp0_it1[2] <= 1'b1;
ap_reg_ppstg_tmp_19_reg_1582_pp0_it1[14] <= 1'b0;
ap_reg_ppstg_tmp_19_reg_1582_pp0_it1[15] <= 1'b0;
ap_reg_ppstg_tmp_19_reg_1582_pp0_it1[16] <= 1'b0;
ap_reg_ppstg_tmp_19_reg_1582_pp0_it1[17] <= 1'b0;
ap_reg_ppstg_tmp_19_reg_1582_pp0_it1[18] <= 1'b0;
ap_reg_ppstg_tmp_19_reg_1582_pp0_it1[19] <= 1'b0;
ap_reg_ppstg_tmp_19_reg_1582_pp0_it1[20] <= 1'b0;
ap_reg_ppstg_tmp_19_reg_1582_pp0_it1[21] <= 1'b0;
ap_reg_ppstg_tmp_19_reg_1582_pp0_it1[22] <= 1'b0;
ap_reg_ppstg_tmp_19_reg_1582_pp0_it1[23] <= 1'b0;
ap_reg_ppstg_tmp_19_reg_1582_pp0_it1[24] <= 1'b0;
ap_reg_ppstg_tmp_19_reg_1582_pp0_it1[25] <= 1'b0;
ap_reg_ppstg_tmp_19_reg_1582_pp0_it1[26] <= 1'b0;
ap_reg_ppstg_tmp_19_reg_1582_pp0_it1[27] <= 1'b0;
ap_reg_ppstg_tmp_19_reg_1582_pp0_it1[28] <= 1'b0;
ap_reg_ppstg_tmp_19_reg_1582_pp0_it1[29] <= 1'b0;
ap_reg_ppstg_tmp_19_reg_1582_pp0_it1[30] <= 1'b0;
ap_reg_ppstg_tmp_19_reg_1582_pp0_it1[31] <= 1'b0;
ap_reg_ppstg_tmp_19_reg_1582_pp0_it1[32] <= 1'b0;
ap_reg_ppstg_tmp_19_reg_1582_pp0_it1[33] <= 1'b0;
ap_reg_ppstg_tmp_19_reg_1582_pp0_it1[34] <= 1'b0;
ap_reg_ppstg_tmp_19_reg_1582_pp0_it1[35] <= 1'b0;
ap_reg_ppstg_tmp_19_reg_1582_pp0_it1[36] <= 1'b0;
ap_reg_ppstg_tmp_19_reg_1582_pp0_it1[37] <= 1'b0;
ap_reg_ppstg_tmp_19_reg_1582_pp0_it1[38] <= 1'b0;
ap_reg_ppstg_tmp_19_reg_1582_pp0_it1[39] <= 1'b0;
ap_reg_ppstg_tmp_19_reg_1582_pp0_it1[40] <= 1'b0;
ap_reg_ppstg_tmp_19_reg_1582_pp0_it1[41] <= 1'b0;
ap_reg_ppstg_tmp_19_reg_1582_pp0_it1[42] <= 1'b0;
ap_reg_ppstg_tmp_19_reg_1582_pp0_it1[43] <= 1'b0;
ap_reg_ppstg_tmp_19_reg_1582_pp0_it1[44] <= 1'b0;
ap_reg_ppstg_tmp_19_reg_1582_pp0_it1[45] <= 1'b0;
ap_reg_ppstg_tmp_19_reg_1582_pp0_it1[46] <= 1'b0;
ap_reg_ppstg_tmp_19_reg_1582_pp0_it1[47] <= 1'b0;
ap_reg_ppstg_tmp_19_reg_1582_pp0_it1[48] <= 1'b0;
ap_reg_ppstg_tmp_19_reg_1582_pp0_it1[49] <= 1'b0;
ap_reg_ppstg_tmp_19_reg_1582_pp0_it1[50] <= 1'b0;
ap_reg_ppstg_tmp_19_reg_1582_pp0_it1[51] <= 1'b0;
ap_reg_ppstg_tmp_19_reg_1582_pp0_it1[52] <= 1'b0;
ap_reg_ppstg_tmp_19_reg_1582_pp0_it1[53] <= 1'b0;
ap_reg_ppstg_tmp_19_reg_1582_pp0_it1[54] <= 1'b0;
ap_reg_ppstg_tmp_19_reg_1582_pp0_it1[55] <= 1'b0;
ap_reg_ppstg_tmp_19_reg_1582_pp0_it1[56] <= 1'b0;
ap_reg_ppstg_tmp_19_reg_1582_pp0_it1[57] <= 1'b0;
ap_reg_ppstg_tmp_19_reg_1582_pp0_it1[58] <= 1'b0;
ap_reg_ppstg_tmp_19_reg_1582_pp0_it1[59] <= 1'b0;
ap_reg_ppstg_tmp_19_reg_1582_pp0_it1[60] <= 1'b0;
ap_reg_ppstg_tmp_19_reg_1582_pp0_it1[61] <= 1'b0;
ap_reg_ppstg_tmp_19_reg_1582_pp0_it1[62] <= 1'b0;
ap_reg_ppstg_tmp_19_reg_1582_pp0_it1[63] <= 1'b0;
end
always @ (ap_clk)
begin
b_addr9_cast_reg_1629[0] <= 1'b0;
b_addr9_cast_reg_1629[1] <= 1'b0;
b_addr9_cast_reg_1629[2] <= 1'b0;
b_addr9_cast_reg_1629[3] <= 1'b0;
b_addr9_cast_reg_1629[4] <= 1'b0;
b_addr9_cast_reg_1629[5] <= 1'b0;
b_addr9_cast_reg_1629[13] <= 1'b0;
end
always @ (ap_clk)
begin
tmp_30_reg_1640[14] <= 1'b0;
tmp_30_reg_1640[15] <= 1'b0;
tmp_30_reg_1640[16] <= 1'b0;
tmp_30_reg_1640[17] <= 1'b0;
tmp_30_reg_1640[18] <= 1'b0;
tmp_30_reg_1640[19] <= 1'b0;
tmp_30_reg_1640[20] <= 1'b0;
tmp_30_reg_1640[21] <= 1'b0;
tmp_30_reg_1640[22] <= 1'b0;
tmp_30_reg_1640[23] <= 1'b0;
tmp_30_reg_1640[24] <= 1'b0;
tmp_30_reg_1640[25] <= 1'b0;
tmp_30_reg_1640[26] <= 1'b0;
tmp_30_reg_1640[27] <= 1'b0;
tmp_30_reg_1640[28] <= 1'b0;
tmp_30_reg_1640[29] <= 1'b0;
tmp_30_reg_1640[30] <= 1'b0;
tmp_30_reg_1640[31] <= 1'b0;
tmp_30_reg_1640[32] <= 1'b0;
tmp_30_reg_1640[33] <= 1'b0;
tmp_30_reg_1640[34] <= 1'b0;
tmp_30_reg_1640[35] <= 1'b0;
tmp_30_reg_1640[36] <= 1'b0;
tmp_30_reg_1640[37] <= 1'b0;
tmp_30_reg_1640[38] <= 1'b0;
tmp_30_reg_1640[39] <= 1'b0;
tmp_30_reg_1640[40] <= 1'b0;
tmp_30_reg_1640[41] <= 1'b0;
tmp_30_reg_1640[42] <= 1'b0;
tmp_30_reg_1640[43] <= 1'b0;
tmp_30_reg_1640[44] <= 1'b0;
tmp_30_reg_1640[45] <= 1'b0;
tmp_30_reg_1640[46] <= 1'b0;
tmp_30_reg_1640[47] <= 1'b0;
tmp_30_reg_1640[48] <= 1'b0;
tmp_30_reg_1640[49] <= 1'b0;
tmp_30_reg_1640[50] <= 1'b0;
tmp_30_reg_1640[51] <= 1'b0;
tmp_30_reg_1640[52] <= 1'b0;
tmp_30_reg_1640[53] <= 1'b0;
tmp_30_reg_1640[54] <= 1'b0;
tmp_30_reg_1640[55] <= 1'b0;
tmp_30_reg_1640[56] <= 1'b0;
tmp_30_reg_1640[57] <= 1'b0;
tmp_30_reg_1640[58] <= 1'b0;
tmp_30_reg_1640[59] <= 1'b0;
tmp_30_reg_1640[60] <= 1'b0;
tmp_30_reg_1640[61] <= 1'b0;
tmp_30_reg_1640[62] <= 1'b0;
tmp_30_reg_1640[63] <= 1'b0;
end
always @ (ap_clk)
begin
ap_reg_ppstg_tmp_30_reg_1640_pp1_it1[14] <= 1'b0;
ap_reg_ppstg_tmp_30_reg_1640_pp1_it1[15] <= 1'b0;
ap_reg_ppstg_tmp_30_reg_1640_pp1_it1[16] <= 1'b0;
ap_reg_ppstg_tmp_30_reg_1640_pp1_it1[17] <= 1'b0;
ap_reg_ppstg_tmp_30_reg_1640_pp1_it1[18] <= 1'b0;
ap_reg_ppstg_tmp_30_reg_1640_pp1_it1[19] <= 1'b0;
ap_reg_ppstg_tmp_30_reg_1640_pp1_it1[20] <= 1'b0;
ap_reg_ppstg_tmp_30_reg_1640_pp1_it1[21] <= 1'b0;
ap_reg_ppstg_tmp_30_reg_1640_pp1_it1[22] <= 1'b0;
ap_reg_ppstg_tmp_30_reg_1640_pp1_it1[23] <= 1'b0;
ap_reg_ppstg_tmp_30_reg_1640_pp1_it1[24] <= 1'b0;
ap_reg_ppstg_tmp_30_reg_1640_pp1_it1[25] <= 1'b0;
ap_reg_ppstg_tmp_30_reg_1640_pp1_it1[26] <= 1'b0;
ap_reg_ppstg_tmp_30_reg_1640_pp1_it1[27] <= 1'b0;
ap_reg_ppstg_tmp_30_reg_1640_pp1_it1[28] <= 1'b0;
ap_reg_ppstg_tmp_30_reg_1640_pp1_it1[29] <= 1'b0;
ap_reg_ppstg_tmp_30_reg_1640_pp1_it1[30] <= 1'b0;
ap_reg_ppstg_tmp_30_reg_1640_pp1_it1[31] <= 1'b0;
ap_reg_ppstg_tmp_30_reg_1640_pp1_it1[32] <= 1'b0;
ap_reg_ppstg_tmp_30_reg_1640_pp1_it1[33] <= 1'b0;
ap_reg_ppstg_tmp_30_reg_1640_pp1_it1[34] <= 1'b0;
ap_reg_ppstg_tmp_30_reg_1640_pp1_it1[35] <= 1'b0;
ap_reg_ppstg_tmp_30_reg_1640_pp1_it1[36] <= 1'b0;
ap_reg_ppstg_tmp_30_reg_1640_pp1_it1[37] <= 1'b0;
ap_reg_ppstg_tmp_30_reg_1640_pp1_it1[38] <= 1'b0;
ap_reg_ppstg_tmp_30_reg_1640_pp1_it1[39] <= 1'b0;
ap_reg_ppstg_tmp_30_reg_1640_pp1_it1[40] <= 1'b0;
ap_reg_ppstg_tmp_30_reg_1640_pp1_it1[41] <= 1'b0;
ap_reg_ppstg_tmp_30_reg_1640_pp1_it1[42] <= 1'b0;
ap_reg_ppstg_tmp_30_reg_1640_pp1_it1[43] <= 1'b0;
ap_reg_ppstg_tmp_30_reg_1640_pp1_it1[44] <= 1'b0;
ap_reg_ppstg_tmp_30_reg_1640_pp1_it1[45] <= 1'b0;
ap_reg_ppstg_tmp_30_reg_1640_pp1_it1[46] <= 1'b0;
ap_reg_ppstg_tmp_30_reg_1640_pp1_it1[47] <= 1'b0;
ap_reg_ppstg_tmp_30_reg_1640_pp1_it1[48] <= 1'b0;
ap_reg_ppstg_tmp_30_reg_1640_pp1_it1[49] <= 1'b0;
ap_reg_ppstg_tmp_30_reg_1640_pp1_it1[50] <= 1'b0;
ap_reg_ppstg_tmp_30_reg_1640_pp1_it1[51] <= 1'b0;
ap_reg_ppstg_tmp_30_reg_1640_pp1_it1[52] <= 1'b0;
ap_reg_ppstg_tmp_30_reg_1640_pp1_it1[53] <= 1'b0;
ap_reg_ppstg_tmp_30_reg_1640_pp1_it1[54] <= 1'b0;
ap_reg_ppstg_tmp_30_reg_1640_pp1_it1[55] <= 1'b0;
ap_reg_ppstg_tmp_30_reg_1640_pp1_it1[56] <= 1'b0;
ap_reg_ppstg_tmp_30_reg_1640_pp1_it1[57] <= 1'b0;
ap_reg_ppstg_tmp_30_reg_1640_pp1_it1[58] <= 1'b0;
ap_reg_ppstg_tmp_30_reg_1640_pp1_it1[59] <= 1'b0;
ap_reg_ppstg_tmp_30_reg_1640_pp1_it1[60] <= 1'b0;
ap_reg_ppstg_tmp_30_reg_1640_pp1_it1[61] <= 1'b0;
ap_reg_ppstg_tmp_30_reg_1640_pp1_it1[62] <= 1'b0;
ap_reg_ppstg_tmp_30_reg_1640_pp1_it1[63] <= 1'b0;
end
always @ (ap_clk)
begin
ap_reg_ppstg_tmp_30_reg_1640_pp1_it2[14] <= 1'b0;
ap_reg_ppstg_tmp_30_reg_1640_pp1_it2[15] <= 1'b0;
ap_reg_ppstg_tmp_30_reg_1640_pp1_it2[16] <= 1'b0;
ap_reg_ppstg_tmp_30_reg_1640_pp1_it2[17] <= 1'b0;
ap_reg_ppstg_tmp_30_reg_1640_pp1_it2[18] <= 1'b0;
ap_reg_ppstg_tmp_30_reg_1640_pp1_it2[19] <= 1'b0;
ap_reg_ppstg_tmp_30_reg_1640_pp1_it2[20] <= 1'b0;
ap_reg_ppstg_tmp_30_reg_1640_pp1_it2[21] <= 1'b0;
ap_reg_ppstg_tmp_30_reg_1640_pp1_it2[22] <= 1'b0;
ap_reg_ppstg_tmp_30_reg_1640_pp1_it2[23] <= 1'b0;
ap_reg_ppstg_tmp_30_reg_1640_pp1_it2[24] <= 1'b0;
ap_reg_ppstg_tmp_30_reg_1640_pp1_it2[25] <= 1'b0;
ap_reg_ppstg_tmp_30_reg_1640_pp1_it2[26] <= 1'b0;
ap_reg_ppstg_tmp_30_reg_1640_pp1_it2[27] <= 1'b0;
ap_reg_ppstg_tmp_30_reg_1640_pp1_it2[28] <= 1'b0;
ap_reg_ppstg_tmp_30_reg_1640_pp1_it2[29] <= 1'b0;
ap_reg_ppstg_tmp_30_reg_1640_pp1_it2[30] <= 1'b0;
ap_reg_ppstg_tmp_30_reg_1640_pp1_it2[31] <= 1'b0;
ap_reg_ppstg_tmp_30_reg_1640_pp1_it2[32] <= 1'b0;
ap_reg_ppstg_tmp_30_reg_1640_pp1_it2[33] <= 1'b0;
ap_reg_ppstg_tmp_30_reg_1640_pp1_it2[34] <= 1'b0;
ap_reg_ppstg_tmp_30_reg_1640_pp1_it2[35] <= 1'b0;
ap_reg_ppstg_tmp_30_reg_1640_pp1_it2[36] <= 1'b0;
ap_reg_ppstg_tmp_30_reg_1640_pp1_it2[37] <= 1'b0;
ap_reg_ppstg_tmp_30_reg_1640_pp1_it2[38] <= 1'b0;
ap_reg_ppstg_tmp_30_reg_1640_pp1_it2[39] <= 1'b0;
ap_reg_ppstg_tmp_30_reg_1640_pp1_it2[40] <= 1'b0;
ap_reg_ppstg_tmp_30_reg_1640_pp1_it2[41] <= 1'b0;
ap_reg_ppstg_tmp_30_reg_1640_pp1_it2[42] <= 1'b0;
ap_reg_ppstg_tmp_30_reg_1640_pp1_it2[43] <= 1'b0;
ap_reg_ppstg_tmp_30_reg_1640_pp1_it2[44] <= 1'b0;
ap_reg_ppstg_tmp_30_reg_1640_pp1_it2[45] <= 1'b0;
ap_reg_ppstg_tmp_30_reg_1640_pp1_it2[46] <= 1'b0;
ap_reg_ppstg_tmp_30_reg_1640_pp1_it2[47] <= 1'b0;
ap_reg_ppstg_tmp_30_reg_1640_pp1_it2[48] <= 1'b0;
ap_reg_ppstg_tmp_30_reg_1640_pp1_it2[49] <= 1'b0;
ap_reg_ppstg_tmp_30_reg_1640_pp1_it2[50] <= 1'b0;
ap_reg_ppstg_tmp_30_reg_1640_pp1_it2[51] <= 1'b0;
ap_reg_ppstg_tmp_30_reg_1640_pp1_it2[52] <= 1'b0;
ap_reg_ppstg_tmp_30_reg_1640_pp1_it2[53] <= 1'b0;
ap_reg_ppstg_tmp_30_reg_1640_pp1_it2[54] <= 1'b0;
ap_reg_ppstg_tmp_30_reg_1640_pp1_it2[55] <= 1'b0;
ap_reg_ppstg_tmp_30_reg_1640_pp1_it2[56] <= 1'b0;
ap_reg_ppstg_tmp_30_reg_1640_pp1_it2[57] <= 1'b0;
ap_reg_ppstg_tmp_30_reg_1640_pp1_it2[58] <= 1'b0;
ap_reg_ppstg_tmp_30_reg_1640_pp1_it2[59] <= 1'b0;
ap_reg_ppstg_tmp_30_reg_1640_pp1_it2[60] <= 1'b0;
ap_reg_ppstg_tmp_30_reg_1640_pp1_it2[61] <= 1'b0;
ap_reg_ppstg_tmp_30_reg_1640_pp1_it2[62] <= 1'b0;
ap_reg_ppstg_tmp_30_reg_1640_pp1_it2[63] <= 1'b0;
end
always @ (ap_clk)
begin
tmp_33_reg_1662[0] <= 1'b1;
tmp_33_reg_1662[14] <= 1'b0;
tmp_33_reg_1662[15] <= 1'b0;
tmp_33_reg_1662[16] <= 1'b0;
tmp_33_reg_1662[17] <= 1'b0;
tmp_33_reg_1662[18] <= 1'b0;
tmp_33_reg_1662[19] <= 1'b0;
tmp_33_reg_1662[20] <= 1'b0;
tmp_33_reg_1662[21] <= 1'b0;
tmp_33_reg_1662[22] <= 1'b0;
tmp_33_reg_1662[23] <= 1'b0;
tmp_33_reg_1662[24] <= 1'b0;
tmp_33_reg_1662[25] <= 1'b0;
tmp_33_reg_1662[26] <= 1'b0;
tmp_33_reg_1662[27] <= 1'b0;
tmp_33_reg_1662[28] <= 1'b0;
tmp_33_reg_1662[29] <= 1'b0;
tmp_33_reg_1662[30] <= 1'b0;
tmp_33_reg_1662[31] <= 1'b0;
tmp_33_reg_1662[32] <= 1'b0;
tmp_33_reg_1662[33] <= 1'b0;
tmp_33_reg_1662[34] <= 1'b0;
tmp_33_reg_1662[35] <= 1'b0;
tmp_33_reg_1662[36] <= 1'b0;
tmp_33_reg_1662[37] <= 1'b0;
tmp_33_reg_1662[38] <= 1'b0;
tmp_33_reg_1662[39] <= 1'b0;
tmp_33_reg_1662[40] <= 1'b0;
tmp_33_reg_1662[41] <= 1'b0;
tmp_33_reg_1662[42] <= 1'b0;
tmp_33_reg_1662[43] <= 1'b0;
tmp_33_reg_1662[44] <= 1'b0;
tmp_33_reg_1662[45] <= 1'b0;
tmp_33_reg_1662[46] <= 1'b0;
tmp_33_reg_1662[47] <= 1'b0;
tmp_33_reg_1662[48] <= 1'b0;
tmp_33_reg_1662[49] <= 1'b0;
tmp_33_reg_1662[50] <= 1'b0;
tmp_33_reg_1662[51] <= 1'b0;
tmp_33_reg_1662[52] <= 1'b0;
tmp_33_reg_1662[53] <= 1'b0;
tmp_33_reg_1662[54] <= 1'b0;
tmp_33_reg_1662[55] <= 1'b0;
tmp_33_reg_1662[56] <= 1'b0;
tmp_33_reg_1662[57] <= 1'b0;
tmp_33_reg_1662[58] <= 1'b0;
tmp_33_reg_1662[59] <= 1'b0;
tmp_33_reg_1662[60] <= 1'b0;
tmp_33_reg_1662[61] <= 1'b0;
tmp_33_reg_1662[62] <= 1'b0;
tmp_33_reg_1662[63] <= 1'b0;
end
always @ (ap_clk)
begin
ap_reg_ppstg_tmp_33_reg_1662_pp1_it1[0] <= 1'b1;
ap_reg_ppstg_tmp_33_reg_1662_pp1_it1[14] <= 1'b0;
ap_reg_ppstg_tmp_33_reg_1662_pp1_it1[15] <= 1'b0;
ap_reg_ppstg_tmp_33_reg_1662_pp1_it1[16] <= 1'b0;
ap_reg_ppstg_tmp_33_reg_1662_pp1_it1[17] <= 1'b0;
ap_reg_ppstg_tmp_33_reg_1662_pp1_it1[18] <= 1'b0;
ap_reg_ppstg_tmp_33_reg_1662_pp1_it1[19] <= 1'b0;
ap_reg_ppstg_tmp_33_reg_1662_pp1_it1[20] <= 1'b0;
ap_reg_ppstg_tmp_33_reg_1662_pp1_it1[21] <= 1'b0;
ap_reg_ppstg_tmp_33_reg_1662_pp1_it1[22] <= 1'b0;
ap_reg_ppstg_tmp_33_reg_1662_pp1_it1[23] <= 1'b0;
ap_reg_ppstg_tmp_33_reg_1662_pp1_it1[24] <= 1'b0;
ap_reg_ppstg_tmp_33_reg_1662_pp1_it1[25] <= 1'b0;
ap_reg_ppstg_tmp_33_reg_1662_pp1_it1[26] <= 1'b0;
ap_reg_ppstg_tmp_33_reg_1662_pp1_it1[27] <= 1'b0;
ap_reg_ppstg_tmp_33_reg_1662_pp1_it1[28] <= 1'b0;
ap_reg_ppstg_tmp_33_reg_1662_pp1_it1[29] <= 1'b0;
ap_reg_ppstg_tmp_33_reg_1662_pp1_it1[30] <= 1'b0;
ap_reg_ppstg_tmp_33_reg_1662_pp1_it1[31] <= 1'b0;
ap_reg_ppstg_tmp_33_reg_1662_pp1_it1[32] <= 1'b0;
ap_reg_ppstg_tmp_33_reg_1662_pp1_it1[33] <= 1'b0;
ap_reg_ppstg_tmp_33_reg_1662_pp1_it1[34] <= 1'b0;
ap_reg_ppstg_tmp_33_reg_1662_pp1_it1[35] <= 1'b0;
ap_reg_ppstg_tmp_33_reg_1662_pp1_it1[36] <= 1'b0;
ap_reg_ppstg_tmp_33_reg_1662_pp1_it1[37] <= 1'b0;
ap_reg_ppstg_tmp_33_reg_1662_pp1_it1[38] <= 1'b0;
ap_reg_ppstg_tmp_33_reg_1662_pp1_it1[39] <= 1'b0;
ap_reg_ppstg_tmp_33_reg_1662_pp1_it1[40] <= 1'b0;
ap_reg_ppstg_tmp_33_reg_1662_pp1_it1[41] <= 1'b0;
ap_reg_ppstg_tmp_33_reg_1662_pp1_it1[42] <= 1'b0;
ap_reg_ppstg_tmp_33_reg_1662_pp1_it1[43] <= 1'b0;
ap_reg_ppstg_tmp_33_reg_1662_pp1_it1[44] <= 1'b0;
ap_reg_ppstg_tmp_33_reg_1662_pp1_it1[45] <= 1'b0;
ap_reg_ppstg_tmp_33_reg_1662_pp1_it1[46] <= 1'b0;
ap_reg_ppstg_tmp_33_reg_1662_pp1_it1[47] <= 1'b0;
ap_reg_ppstg_tmp_33_reg_1662_pp1_it1[48] <= 1'b0;
ap_reg_ppstg_tmp_33_reg_1662_pp1_it1[49] <= 1'b0;
ap_reg_ppstg_tmp_33_reg_1662_pp1_it1[50] <= 1'b0;
ap_reg_ppstg_tmp_33_reg_1662_pp1_it1[51] <= 1'b0;
ap_reg_ppstg_tmp_33_reg_1662_pp1_it1[52] <= 1'b0;
ap_reg_ppstg_tmp_33_reg_1662_pp1_it1[53] <= 1'b0;
ap_reg_ppstg_tmp_33_reg_1662_pp1_it1[54] <= 1'b0;
ap_reg_ppstg_tmp_33_reg_1662_pp1_it1[55] <= 1'b0;
ap_reg_ppstg_tmp_33_reg_1662_pp1_it1[56] <= 1'b0;
ap_reg_ppstg_tmp_33_reg_1662_pp1_it1[57] <= 1'b0;
ap_reg_ppstg_tmp_33_reg_1662_pp1_it1[58] <= 1'b0;
ap_reg_ppstg_tmp_33_reg_1662_pp1_it1[59] <= 1'b0;
ap_reg_ppstg_tmp_33_reg_1662_pp1_it1[60] <= 1'b0;
ap_reg_ppstg_tmp_33_reg_1662_pp1_it1[61] <= 1'b0;
ap_reg_ppstg_tmp_33_reg_1662_pp1_it1[62] <= 1'b0;
ap_reg_ppstg_tmp_33_reg_1662_pp1_it1[63] <= 1'b0;
end
always @ (ap_clk)
begin
ap_reg_ppstg_tmp_33_reg_1662_pp1_it2[0] <= 1'b1;
ap_reg_ppstg_tmp_33_reg_1662_pp1_it2[14] <= 1'b0;
ap_reg_ppstg_tmp_33_reg_1662_pp1_it2[15] <= 1'b0;
ap_reg_ppstg_tmp_33_reg_1662_pp1_it2[16] <= 1'b0;
ap_reg_ppstg_tmp_33_reg_1662_pp1_it2[17] <= 1'b0;
ap_reg_ppstg_tmp_33_reg_1662_pp1_it2[18] <= 1'b0;
ap_reg_ppstg_tmp_33_reg_1662_pp1_it2[19] <= 1'b0;
ap_reg_ppstg_tmp_33_reg_1662_pp1_it2[20] <= 1'b0;
ap_reg_ppstg_tmp_33_reg_1662_pp1_it2[21] <= 1'b0;
ap_reg_ppstg_tmp_33_reg_1662_pp1_it2[22] <= 1'b0;
ap_reg_ppstg_tmp_33_reg_1662_pp1_it2[23] <= 1'b0;
ap_reg_ppstg_tmp_33_reg_1662_pp1_it2[24] <= 1'b0;
ap_reg_ppstg_tmp_33_reg_1662_pp1_it2[25] <= 1'b0;
ap_reg_ppstg_tmp_33_reg_1662_pp1_it2[26] <= 1'b0;
ap_reg_ppstg_tmp_33_reg_1662_pp1_it2[27] <= 1'b0;
ap_reg_ppstg_tmp_33_reg_1662_pp1_it2[28] <= 1'b0;
ap_reg_ppstg_tmp_33_reg_1662_pp1_it2[29] <= 1'b0;
ap_reg_ppstg_tmp_33_reg_1662_pp1_it2[30] <= 1'b0;
ap_reg_ppstg_tmp_33_reg_1662_pp1_it2[31] <= 1'b0;
ap_reg_ppstg_tmp_33_reg_1662_pp1_it2[32] <= 1'b0;
ap_reg_ppstg_tmp_33_reg_1662_pp1_it2[33] <= 1'b0;
ap_reg_ppstg_tmp_33_reg_1662_pp1_it2[34] <= 1'b0;
ap_reg_ppstg_tmp_33_reg_1662_pp1_it2[35] <= 1'b0;
ap_reg_ppstg_tmp_33_reg_1662_pp1_it2[36] <= 1'b0;
ap_reg_ppstg_tmp_33_reg_1662_pp1_it2[37] <= 1'b0;
ap_reg_ppstg_tmp_33_reg_1662_pp1_it2[38] <= 1'b0;
ap_reg_ppstg_tmp_33_reg_1662_pp1_it2[39] <= 1'b0;
ap_reg_ppstg_tmp_33_reg_1662_pp1_it2[40] <= 1'b0;
ap_reg_ppstg_tmp_33_reg_1662_pp1_it2[41] <= 1'b0;
ap_reg_ppstg_tmp_33_reg_1662_pp1_it2[42] <= 1'b0;
ap_reg_ppstg_tmp_33_reg_1662_pp1_it2[43] <= 1'b0;
ap_reg_ppstg_tmp_33_reg_1662_pp1_it2[44] <= 1'b0;
ap_reg_ppstg_tmp_33_reg_1662_pp1_it2[45] <= 1'b0;
ap_reg_ppstg_tmp_33_reg_1662_pp1_it2[46] <= 1'b0;
ap_reg_ppstg_tmp_33_reg_1662_pp1_it2[47] <= 1'b0;
ap_reg_ppstg_tmp_33_reg_1662_pp1_it2[48] <= 1'b0;
ap_reg_ppstg_tmp_33_reg_1662_pp1_it2[49] <= 1'b0;
ap_reg_ppstg_tmp_33_reg_1662_pp1_it2[50] <= 1'b0;
ap_reg_ppstg_tmp_33_reg_1662_pp1_it2[51] <= 1'b0;
ap_reg_ppstg_tmp_33_reg_1662_pp1_it2[52] <= 1'b0;
ap_reg_ppstg_tmp_33_reg_1662_pp1_it2[53] <= 1'b0;
ap_reg_ppstg_tmp_33_reg_1662_pp1_it2[54] <= 1'b0;
ap_reg_ppstg_tmp_33_reg_1662_pp1_it2[55] <= 1'b0;
ap_reg_ppstg_tmp_33_reg_1662_pp1_it2[56] <= 1'b0;
ap_reg_ppstg_tmp_33_reg_1662_pp1_it2[57] <= 1'b0;
ap_reg_ppstg_tmp_33_reg_1662_pp1_it2[58] <= 1'b0;
ap_reg_ppstg_tmp_33_reg_1662_pp1_it2[59] <= 1'b0;
ap_reg_ppstg_tmp_33_reg_1662_pp1_it2[60] <= 1'b0;
ap_reg_ppstg_tmp_33_reg_1662_pp1_it2[61] <= 1'b0;
ap_reg_ppstg_tmp_33_reg_1662_pp1_it2[62] <= 1'b0;
ap_reg_ppstg_tmp_33_reg_1662_pp1_it2[63] <= 1'b0;
end
always @ (ap_clk)
begin
tmp_36_reg_1679[14] <= 1'b0;
tmp_36_reg_1679[15] <= 1'b0;
tmp_36_reg_1679[16] <= 1'b0;
tmp_36_reg_1679[17] <= 1'b0;
tmp_36_reg_1679[18] <= 1'b0;
tmp_36_reg_1679[19] <= 1'b0;
tmp_36_reg_1679[20] <= 1'b0;
tmp_36_reg_1679[21] <= 1'b0;
tmp_36_reg_1679[22] <= 1'b0;
tmp_36_reg_1679[23] <= 1'b0;
tmp_36_reg_1679[24] <= 1'b0;
tmp_36_reg_1679[25] <= 1'b0;
tmp_36_reg_1679[26] <= 1'b0;
tmp_36_reg_1679[27] <= 1'b0;
tmp_36_reg_1679[28] <= 1'b0;
tmp_36_reg_1679[29] <= 1'b0;
tmp_36_reg_1679[30] <= 1'b0;
tmp_36_reg_1679[31] <= 1'b0;
tmp_36_reg_1679[32] <= 1'b0;
tmp_36_reg_1679[33] <= 1'b0;
tmp_36_reg_1679[34] <= 1'b0;
tmp_36_reg_1679[35] <= 1'b0;
tmp_36_reg_1679[36] <= 1'b0;
tmp_36_reg_1679[37] <= 1'b0;
tmp_36_reg_1679[38] <= 1'b0;
tmp_36_reg_1679[39] <= 1'b0;
tmp_36_reg_1679[40] <= 1'b0;
tmp_36_reg_1679[41] <= 1'b0;
tmp_36_reg_1679[42] <= 1'b0;
tmp_36_reg_1679[43] <= 1'b0;
tmp_36_reg_1679[44] <= 1'b0;
tmp_36_reg_1679[45] <= 1'b0;
tmp_36_reg_1679[46] <= 1'b0;
tmp_36_reg_1679[47] <= 1'b0;
tmp_36_reg_1679[48] <= 1'b0;
tmp_36_reg_1679[49] <= 1'b0;
tmp_36_reg_1679[50] <= 1'b0;
tmp_36_reg_1679[51] <= 1'b0;
tmp_36_reg_1679[52] <= 1'b0;
tmp_36_reg_1679[53] <= 1'b0;
tmp_36_reg_1679[54] <= 1'b0;
tmp_36_reg_1679[55] <= 1'b0;
tmp_36_reg_1679[56] <= 1'b0;
tmp_36_reg_1679[57] <= 1'b0;
tmp_36_reg_1679[58] <= 1'b0;
tmp_36_reg_1679[59] <= 1'b0;
tmp_36_reg_1679[60] <= 1'b0;
tmp_36_reg_1679[61] <= 1'b0;
tmp_36_reg_1679[62] <= 1'b0;
tmp_36_reg_1679[63] <= 1'b0;
end
always @ (ap_clk)
begin
ap_reg_ppstg_tmp_36_reg_1679_pp1_it1[14] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_1679_pp1_it1[15] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_1679_pp1_it1[16] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_1679_pp1_it1[17] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_1679_pp1_it1[18] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_1679_pp1_it1[19] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_1679_pp1_it1[20] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_1679_pp1_it1[21] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_1679_pp1_it1[22] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_1679_pp1_it1[23] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_1679_pp1_it1[24] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_1679_pp1_it1[25] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_1679_pp1_it1[26] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_1679_pp1_it1[27] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_1679_pp1_it1[28] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_1679_pp1_it1[29] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_1679_pp1_it1[30] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_1679_pp1_it1[31] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_1679_pp1_it1[32] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_1679_pp1_it1[33] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_1679_pp1_it1[34] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_1679_pp1_it1[35] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_1679_pp1_it1[36] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_1679_pp1_it1[37] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_1679_pp1_it1[38] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_1679_pp1_it1[39] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_1679_pp1_it1[40] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_1679_pp1_it1[41] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_1679_pp1_it1[42] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_1679_pp1_it1[43] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_1679_pp1_it1[44] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_1679_pp1_it1[45] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_1679_pp1_it1[46] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_1679_pp1_it1[47] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_1679_pp1_it1[48] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_1679_pp1_it1[49] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_1679_pp1_it1[50] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_1679_pp1_it1[51] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_1679_pp1_it1[52] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_1679_pp1_it1[53] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_1679_pp1_it1[54] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_1679_pp1_it1[55] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_1679_pp1_it1[56] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_1679_pp1_it1[57] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_1679_pp1_it1[58] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_1679_pp1_it1[59] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_1679_pp1_it1[60] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_1679_pp1_it1[61] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_1679_pp1_it1[62] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_1679_pp1_it1[63] <= 1'b0;
end
always @ (ap_clk)
begin
ap_reg_ppstg_tmp_36_reg_1679_pp1_it2[14] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_1679_pp1_it2[15] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_1679_pp1_it2[16] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_1679_pp1_it2[17] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_1679_pp1_it2[18] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_1679_pp1_it2[19] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_1679_pp1_it2[20] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_1679_pp1_it2[21] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_1679_pp1_it2[22] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_1679_pp1_it2[23] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_1679_pp1_it2[24] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_1679_pp1_it2[25] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_1679_pp1_it2[26] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_1679_pp1_it2[27] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_1679_pp1_it2[28] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_1679_pp1_it2[29] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_1679_pp1_it2[30] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_1679_pp1_it2[31] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_1679_pp1_it2[32] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_1679_pp1_it2[33] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_1679_pp1_it2[34] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_1679_pp1_it2[35] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_1679_pp1_it2[36] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_1679_pp1_it2[37] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_1679_pp1_it2[38] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_1679_pp1_it2[39] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_1679_pp1_it2[40] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_1679_pp1_it2[41] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_1679_pp1_it2[42] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_1679_pp1_it2[43] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_1679_pp1_it2[44] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_1679_pp1_it2[45] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_1679_pp1_it2[46] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_1679_pp1_it2[47] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_1679_pp1_it2[48] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_1679_pp1_it2[49] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_1679_pp1_it2[50] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_1679_pp1_it2[51] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_1679_pp1_it2[52] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_1679_pp1_it2[53] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_1679_pp1_it2[54] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_1679_pp1_it2[55] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_1679_pp1_it2[56] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_1679_pp1_it2[57] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_1679_pp1_it2[58] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_1679_pp1_it2[59] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_1679_pp1_it2[60] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_1679_pp1_it2[61] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_1679_pp1_it2[62] <= 1'b0;
ap_reg_ppstg_tmp_36_reg_1679_pp1_it2[63] <= 1'b0;
end
always @ (ap_clk)
begin
tmp_39_reg_1706[0] <= 1'b1;
tmp_39_reg_1706[1] <= 1'b1;
tmp_39_reg_1706[14] <= 1'b0;
tmp_39_reg_1706[15] <= 1'b0;
tmp_39_reg_1706[16] <= 1'b0;
tmp_39_reg_1706[17] <= 1'b0;
tmp_39_reg_1706[18] <= 1'b0;
tmp_39_reg_1706[19] <= 1'b0;
tmp_39_reg_1706[20] <= 1'b0;
tmp_39_reg_1706[21] <= 1'b0;
tmp_39_reg_1706[22] <= 1'b0;
tmp_39_reg_1706[23] <= 1'b0;
tmp_39_reg_1706[24] <= 1'b0;
tmp_39_reg_1706[25] <= 1'b0;
tmp_39_reg_1706[26] <= 1'b0;
tmp_39_reg_1706[27] <= 1'b0;
tmp_39_reg_1706[28] <= 1'b0;
tmp_39_reg_1706[29] <= 1'b0;
tmp_39_reg_1706[30] <= 1'b0;
tmp_39_reg_1706[31] <= 1'b0;
tmp_39_reg_1706[32] <= 1'b0;
tmp_39_reg_1706[33] <= 1'b0;
tmp_39_reg_1706[34] <= 1'b0;
tmp_39_reg_1706[35] <= 1'b0;
tmp_39_reg_1706[36] <= 1'b0;
tmp_39_reg_1706[37] <= 1'b0;
tmp_39_reg_1706[38] <= 1'b0;
tmp_39_reg_1706[39] <= 1'b0;
tmp_39_reg_1706[40] <= 1'b0;
tmp_39_reg_1706[41] <= 1'b0;
tmp_39_reg_1706[42] <= 1'b0;
tmp_39_reg_1706[43] <= 1'b0;
tmp_39_reg_1706[44] <= 1'b0;
tmp_39_reg_1706[45] <= 1'b0;
tmp_39_reg_1706[46] <= 1'b0;
tmp_39_reg_1706[47] <= 1'b0;
tmp_39_reg_1706[48] <= 1'b0;
tmp_39_reg_1706[49] <= 1'b0;
tmp_39_reg_1706[50] <= 1'b0;
tmp_39_reg_1706[51] <= 1'b0;
tmp_39_reg_1706[52] <= 1'b0;
tmp_39_reg_1706[53] <= 1'b0;
tmp_39_reg_1706[54] <= 1'b0;
tmp_39_reg_1706[55] <= 1'b0;
tmp_39_reg_1706[56] <= 1'b0;
tmp_39_reg_1706[57] <= 1'b0;
tmp_39_reg_1706[58] <= 1'b0;
tmp_39_reg_1706[59] <= 1'b0;
tmp_39_reg_1706[60] <= 1'b0;
tmp_39_reg_1706[61] <= 1'b0;
tmp_39_reg_1706[62] <= 1'b0;
tmp_39_reg_1706[63] <= 1'b0;
end
always @ (ap_clk)
begin
ap_reg_ppstg_tmp_39_reg_1706_pp1_it1[0] <= 1'b1;
ap_reg_ppstg_tmp_39_reg_1706_pp1_it1[1] <= 1'b1;
ap_reg_ppstg_tmp_39_reg_1706_pp1_it1[14] <= 1'b0;
ap_reg_ppstg_tmp_39_reg_1706_pp1_it1[15] <= 1'b0;
ap_reg_ppstg_tmp_39_reg_1706_pp1_it1[16] <= 1'b0;
ap_reg_ppstg_tmp_39_reg_1706_pp1_it1[17] <= 1'b0;
ap_reg_ppstg_tmp_39_reg_1706_pp1_it1[18] <= 1'b0;
ap_reg_ppstg_tmp_39_reg_1706_pp1_it1[19] <= 1'b0;
ap_reg_ppstg_tmp_39_reg_1706_pp1_it1[20] <= 1'b0;
ap_reg_ppstg_tmp_39_reg_1706_pp1_it1[21] <= 1'b0;
ap_reg_ppstg_tmp_39_reg_1706_pp1_it1[22] <= 1'b0;
ap_reg_ppstg_tmp_39_reg_1706_pp1_it1[23] <= 1'b0;
ap_reg_ppstg_tmp_39_reg_1706_pp1_it1[24] <= 1'b0;
ap_reg_ppstg_tmp_39_reg_1706_pp1_it1[25] <= 1'b0;
ap_reg_ppstg_tmp_39_reg_1706_pp1_it1[26] <= 1'b0;
ap_reg_ppstg_tmp_39_reg_1706_pp1_it1[27] <= 1'b0;
ap_reg_ppstg_tmp_39_reg_1706_pp1_it1[28] <= 1'b0;
ap_reg_ppstg_tmp_39_reg_1706_pp1_it1[29] <= 1'b0;
ap_reg_ppstg_tmp_39_reg_1706_pp1_it1[30] <= 1'b0;
ap_reg_ppstg_tmp_39_reg_1706_pp1_it1[31] <= 1'b0;
ap_reg_ppstg_tmp_39_reg_1706_pp1_it1[32] <= 1'b0;
ap_reg_ppstg_tmp_39_reg_1706_pp1_it1[33] <= 1'b0;
ap_reg_ppstg_tmp_39_reg_1706_pp1_it1[34] <= 1'b0;
ap_reg_ppstg_tmp_39_reg_1706_pp1_it1[35] <= 1'b0;
ap_reg_ppstg_tmp_39_reg_1706_pp1_it1[36] <= 1'b0;
ap_reg_ppstg_tmp_39_reg_1706_pp1_it1[37] <= 1'b0;
ap_reg_ppstg_tmp_39_reg_1706_pp1_it1[38] <= 1'b0;
ap_reg_ppstg_tmp_39_reg_1706_pp1_it1[39] <= 1'b0;
ap_reg_ppstg_tmp_39_reg_1706_pp1_it1[40] <= 1'b0;
ap_reg_ppstg_tmp_39_reg_1706_pp1_it1[41] <= 1'b0;
ap_reg_ppstg_tmp_39_reg_1706_pp1_it1[42] <= 1'b0;
ap_reg_ppstg_tmp_39_reg_1706_pp1_it1[43] <= 1'b0;
ap_reg_ppstg_tmp_39_reg_1706_pp1_it1[44] <= 1'b0;
ap_reg_ppstg_tmp_39_reg_1706_pp1_it1[45] <= 1'b0;
ap_reg_ppstg_tmp_39_reg_1706_pp1_it1[46] <= 1'b0;
ap_reg_ppstg_tmp_39_reg_1706_pp1_it1[47] <= 1'b0;
ap_reg_ppstg_tmp_39_reg_1706_pp1_it1[48] <= 1'b0;
ap_reg_ppstg_tmp_39_reg_1706_pp1_it1[49] <= 1'b0;
ap_reg_ppstg_tmp_39_reg_1706_pp1_it1[50] <= 1'b0;
ap_reg_ppstg_tmp_39_reg_1706_pp1_it1[51] <= 1'b0;
ap_reg_ppstg_tmp_39_reg_1706_pp1_it1[52] <= 1'b0;
ap_reg_ppstg_tmp_39_reg_1706_pp1_it1[53] <= 1'b0;
ap_reg_ppstg_tmp_39_reg_1706_pp1_it1[54] <= 1'b0;
ap_reg_ppstg_tmp_39_reg_1706_pp1_it1[55] <= 1'b0;
ap_reg_ppstg_tmp_39_reg_1706_pp1_it1[56] <= 1'b0;
ap_reg_ppstg_tmp_39_reg_1706_pp1_it1[57] <= 1'b0;
ap_reg_ppstg_tmp_39_reg_1706_pp1_it1[58] <= 1'b0;
ap_reg_ppstg_tmp_39_reg_1706_pp1_it1[59] <= 1'b0;
ap_reg_ppstg_tmp_39_reg_1706_pp1_it1[60] <= 1'b0;
ap_reg_ppstg_tmp_39_reg_1706_pp1_it1[61] <= 1'b0;
ap_reg_ppstg_tmp_39_reg_1706_pp1_it1[62] <= 1'b0;
ap_reg_ppstg_tmp_39_reg_1706_pp1_it1[63] <= 1'b0;
end
always @ (ap_clk)
begin
ap_reg_ppstg_tmp_39_reg_1706_pp1_it2[0] <= 1'b1;
ap_reg_ppstg_tmp_39_reg_1706_pp1_it2[1] <= 1'b1;
ap_reg_ppstg_tmp_39_reg_1706_pp1_it2[14] <= 1'b0;
ap_reg_ppstg_tmp_39_reg_1706_pp1_it2[15] <= 1'b0;
ap_reg_ppstg_tmp_39_reg_1706_pp1_it2[16] <= 1'b0;
ap_reg_ppstg_tmp_39_reg_1706_pp1_it2[17] <= 1'b0;
ap_reg_ppstg_tmp_39_reg_1706_pp1_it2[18] <= 1'b0;
ap_reg_ppstg_tmp_39_reg_1706_pp1_it2[19] <= 1'b0;
ap_reg_ppstg_tmp_39_reg_1706_pp1_it2[20] <= 1'b0;
ap_reg_ppstg_tmp_39_reg_1706_pp1_it2[21] <= 1'b0;
ap_reg_ppstg_tmp_39_reg_1706_pp1_it2[22] <= 1'b0;
ap_reg_ppstg_tmp_39_reg_1706_pp1_it2[23] <= 1'b0;
ap_reg_ppstg_tmp_39_reg_1706_pp1_it2[24] <= 1'b0;
ap_reg_ppstg_tmp_39_reg_1706_pp1_it2[25] <= 1'b0;
ap_reg_ppstg_tmp_39_reg_1706_pp1_it2[26] <= 1'b0;
ap_reg_ppstg_tmp_39_reg_1706_pp1_it2[27] <= 1'b0;
ap_reg_ppstg_tmp_39_reg_1706_pp1_it2[28] <= 1'b0;
ap_reg_ppstg_tmp_39_reg_1706_pp1_it2[29] <= 1'b0;
ap_reg_ppstg_tmp_39_reg_1706_pp1_it2[30] <= 1'b0;
ap_reg_ppstg_tmp_39_reg_1706_pp1_it2[31] <= 1'b0;
ap_reg_ppstg_tmp_39_reg_1706_pp1_it2[32] <= 1'b0;
ap_reg_ppstg_tmp_39_reg_1706_pp1_it2[33] <= 1'b0;
ap_reg_ppstg_tmp_39_reg_1706_pp1_it2[34] <= 1'b0;
ap_reg_ppstg_tmp_39_reg_1706_pp1_it2[35] <= 1'b0;
ap_reg_ppstg_tmp_39_reg_1706_pp1_it2[36] <= 1'b0;
ap_reg_ppstg_tmp_39_reg_1706_pp1_it2[37] <= 1'b0;
ap_reg_ppstg_tmp_39_reg_1706_pp1_it2[38] <= 1'b0;
ap_reg_ppstg_tmp_39_reg_1706_pp1_it2[39] <= 1'b0;
ap_reg_ppstg_tmp_39_reg_1706_pp1_it2[40] <= 1'b0;
ap_reg_ppstg_tmp_39_reg_1706_pp1_it2[41] <= 1'b0;
ap_reg_ppstg_tmp_39_reg_1706_pp1_it2[42] <= 1'b0;
ap_reg_ppstg_tmp_39_reg_1706_pp1_it2[43] <= 1'b0;
ap_reg_ppstg_tmp_39_reg_1706_pp1_it2[44] <= 1'b0;
ap_reg_ppstg_tmp_39_reg_1706_pp1_it2[45] <= 1'b0;
ap_reg_ppstg_tmp_39_reg_1706_pp1_it2[46] <= 1'b0;
ap_reg_ppstg_tmp_39_reg_1706_pp1_it2[47] <= 1'b0;
ap_reg_ppstg_tmp_39_reg_1706_pp1_it2[48] <= 1'b0;
ap_reg_ppstg_tmp_39_reg_1706_pp1_it2[49] <= 1'b0;
ap_reg_ppstg_tmp_39_reg_1706_pp1_it2[50] <= 1'b0;
ap_reg_ppstg_tmp_39_reg_1706_pp1_it2[51] <= 1'b0;
ap_reg_ppstg_tmp_39_reg_1706_pp1_it2[52] <= 1'b0;
ap_reg_ppstg_tmp_39_reg_1706_pp1_it2[53] <= 1'b0;
ap_reg_ppstg_tmp_39_reg_1706_pp1_it2[54] <= 1'b0;
ap_reg_ppstg_tmp_39_reg_1706_pp1_it2[55] <= 1'b0;
ap_reg_ppstg_tmp_39_reg_1706_pp1_it2[56] <= 1'b0;
ap_reg_ppstg_tmp_39_reg_1706_pp1_it2[57] <= 1'b0;
ap_reg_ppstg_tmp_39_reg_1706_pp1_it2[58] <= 1'b0;
ap_reg_ppstg_tmp_39_reg_1706_pp1_it2[59] <= 1'b0;
ap_reg_ppstg_tmp_39_reg_1706_pp1_it2[60] <= 1'b0;
ap_reg_ppstg_tmp_39_reg_1706_pp1_it2[61] <= 1'b0;
ap_reg_ppstg_tmp_39_reg_1706_pp1_it2[62] <= 1'b0;
ap_reg_ppstg_tmp_39_reg_1706_pp1_it2[63] <= 1'b0;
end
always @ (ap_clk)
begin
tmp_42_reg_1723[14] <= 1'b0;
tmp_42_reg_1723[15] <= 1'b0;
tmp_42_reg_1723[16] <= 1'b0;
tmp_42_reg_1723[17] <= 1'b0;
tmp_42_reg_1723[18] <= 1'b0;
tmp_42_reg_1723[19] <= 1'b0;
tmp_42_reg_1723[20] <= 1'b0;
tmp_42_reg_1723[21] <= 1'b0;
tmp_42_reg_1723[22] <= 1'b0;
tmp_42_reg_1723[23] <= 1'b0;
tmp_42_reg_1723[24] <= 1'b0;
tmp_42_reg_1723[25] <= 1'b0;
tmp_42_reg_1723[26] <= 1'b0;
tmp_42_reg_1723[27] <= 1'b0;
tmp_42_reg_1723[28] <= 1'b0;
tmp_42_reg_1723[29] <= 1'b0;
tmp_42_reg_1723[30] <= 1'b0;
tmp_42_reg_1723[31] <= 1'b0;
tmp_42_reg_1723[32] <= 1'b0;
tmp_42_reg_1723[33] <= 1'b0;
tmp_42_reg_1723[34] <= 1'b0;
tmp_42_reg_1723[35] <= 1'b0;
tmp_42_reg_1723[36] <= 1'b0;
tmp_42_reg_1723[37] <= 1'b0;
tmp_42_reg_1723[38] <= 1'b0;
tmp_42_reg_1723[39] <= 1'b0;
tmp_42_reg_1723[40] <= 1'b0;
tmp_42_reg_1723[41] <= 1'b0;
tmp_42_reg_1723[42] <= 1'b0;
tmp_42_reg_1723[43] <= 1'b0;
tmp_42_reg_1723[44] <= 1'b0;
tmp_42_reg_1723[45] <= 1'b0;
tmp_42_reg_1723[46] <= 1'b0;
tmp_42_reg_1723[47] <= 1'b0;
tmp_42_reg_1723[48] <= 1'b0;
tmp_42_reg_1723[49] <= 1'b0;
tmp_42_reg_1723[50] <= 1'b0;
tmp_42_reg_1723[51] <= 1'b0;
tmp_42_reg_1723[52] <= 1'b0;
tmp_42_reg_1723[53] <= 1'b0;
tmp_42_reg_1723[54] <= 1'b0;
tmp_42_reg_1723[55] <= 1'b0;
tmp_42_reg_1723[56] <= 1'b0;
tmp_42_reg_1723[57] <= 1'b0;
tmp_42_reg_1723[58] <= 1'b0;
tmp_42_reg_1723[59] <= 1'b0;
tmp_42_reg_1723[60] <= 1'b0;
tmp_42_reg_1723[61] <= 1'b0;
tmp_42_reg_1723[62] <= 1'b0;
tmp_42_reg_1723[63] <= 1'b0;
end
always @ (ap_clk)
begin
ap_reg_ppstg_tmp_42_reg_1723_pp1_it1[14] <= 1'b0;
ap_reg_ppstg_tmp_42_reg_1723_pp1_it1[15] <= 1'b0;
ap_reg_ppstg_tmp_42_reg_1723_pp1_it1[16] <= 1'b0;
ap_reg_ppstg_tmp_42_reg_1723_pp1_it1[17] <= 1'b0;
ap_reg_ppstg_tmp_42_reg_1723_pp1_it1[18] <= 1'b0;
ap_reg_ppstg_tmp_42_reg_1723_pp1_it1[19] <= 1'b0;
ap_reg_ppstg_tmp_42_reg_1723_pp1_it1[20] <= 1'b0;
ap_reg_ppstg_tmp_42_reg_1723_pp1_it1[21] <= 1'b0;
ap_reg_ppstg_tmp_42_reg_1723_pp1_it1[22] <= 1'b0;
ap_reg_ppstg_tmp_42_reg_1723_pp1_it1[23] <= 1'b0;
ap_reg_ppstg_tmp_42_reg_1723_pp1_it1[24] <= 1'b0;
ap_reg_ppstg_tmp_42_reg_1723_pp1_it1[25] <= 1'b0;
ap_reg_ppstg_tmp_42_reg_1723_pp1_it1[26] <= 1'b0;
ap_reg_ppstg_tmp_42_reg_1723_pp1_it1[27] <= 1'b0;
ap_reg_ppstg_tmp_42_reg_1723_pp1_it1[28] <= 1'b0;
ap_reg_ppstg_tmp_42_reg_1723_pp1_it1[29] <= 1'b0;
ap_reg_ppstg_tmp_42_reg_1723_pp1_it1[30] <= 1'b0;
ap_reg_ppstg_tmp_42_reg_1723_pp1_it1[31] <= 1'b0;
ap_reg_ppstg_tmp_42_reg_1723_pp1_it1[32] <= 1'b0;
ap_reg_ppstg_tmp_42_reg_1723_pp1_it1[33] <= 1'b0;
ap_reg_ppstg_tmp_42_reg_1723_pp1_it1[34] <= 1'b0;
ap_reg_ppstg_tmp_42_reg_1723_pp1_it1[35] <= 1'b0;
ap_reg_ppstg_tmp_42_reg_1723_pp1_it1[36] <= 1'b0;
ap_reg_ppstg_tmp_42_reg_1723_pp1_it1[37] <= 1'b0;
ap_reg_ppstg_tmp_42_reg_1723_pp1_it1[38] <= 1'b0;
ap_reg_ppstg_tmp_42_reg_1723_pp1_it1[39] <= 1'b0;
ap_reg_ppstg_tmp_42_reg_1723_pp1_it1[40] <= 1'b0;
ap_reg_ppstg_tmp_42_reg_1723_pp1_it1[41] <= 1'b0;
ap_reg_ppstg_tmp_42_reg_1723_pp1_it1[42] <= 1'b0;
ap_reg_ppstg_tmp_42_reg_1723_pp1_it1[43] <= 1'b0;
ap_reg_ppstg_tmp_42_reg_1723_pp1_it1[44] <= 1'b0;
ap_reg_ppstg_tmp_42_reg_1723_pp1_it1[45] <= 1'b0;
ap_reg_ppstg_tmp_42_reg_1723_pp1_it1[46] <= 1'b0;
ap_reg_ppstg_tmp_42_reg_1723_pp1_it1[47] <= 1'b0;
ap_reg_ppstg_tmp_42_reg_1723_pp1_it1[48] <= 1'b0;
ap_reg_ppstg_tmp_42_reg_1723_pp1_it1[49] <= 1'b0;
ap_reg_ppstg_tmp_42_reg_1723_pp1_it1[50] <= 1'b0;
ap_reg_ppstg_tmp_42_reg_1723_pp1_it1[51] <= 1'b0;
ap_reg_ppstg_tmp_42_reg_1723_pp1_it1[52] <= 1'b0;
ap_reg_ppstg_tmp_42_reg_1723_pp1_it1[53] <= 1'b0;
ap_reg_ppstg_tmp_42_reg_1723_pp1_it1[54] <= 1'b0;
ap_reg_ppstg_tmp_42_reg_1723_pp1_it1[55] <= 1'b0;
ap_reg_ppstg_tmp_42_reg_1723_pp1_it1[56] <= 1'b0;
ap_reg_ppstg_tmp_42_reg_1723_pp1_it1[57] <= 1'b0;
ap_reg_ppstg_tmp_42_reg_1723_pp1_it1[58] <= 1'b0;
ap_reg_ppstg_tmp_42_reg_1723_pp1_it1[59] <= 1'b0;
ap_reg_ppstg_tmp_42_reg_1723_pp1_it1[60] <= 1'b0;
ap_reg_ppstg_tmp_42_reg_1723_pp1_it1[61] <= 1'b0;
ap_reg_ppstg_tmp_42_reg_1723_pp1_it1[62] <= 1'b0;
ap_reg_ppstg_tmp_42_reg_1723_pp1_it1[63] <= 1'b0;
end
always @ (ap_clk)
begin
ap_reg_ppstg_tmp_42_reg_1723_pp1_it2[14] <= 1'b0;
ap_reg_ppstg_tmp_42_reg_1723_pp1_it2[15] <= 1'b0;
ap_reg_ppstg_tmp_42_reg_1723_pp1_it2[16] <= 1'b0;
ap_reg_ppstg_tmp_42_reg_1723_pp1_it2[17] <= 1'b0;
ap_reg_ppstg_tmp_42_reg_1723_pp1_it2[18] <= 1'b0;
ap_reg_ppstg_tmp_42_reg_1723_pp1_it2[19] <= 1'b0;
ap_reg_ppstg_tmp_42_reg_1723_pp1_it2[20] <= 1'b0;
ap_reg_ppstg_tmp_42_reg_1723_pp1_it2[21] <= 1'b0;
ap_reg_ppstg_tmp_42_reg_1723_pp1_it2[22] <= 1'b0;
ap_reg_ppstg_tmp_42_reg_1723_pp1_it2[23] <= 1'b0;
ap_reg_ppstg_tmp_42_reg_1723_pp1_it2[24] <= 1'b0;
ap_reg_ppstg_tmp_42_reg_1723_pp1_it2[25] <= 1'b0;
ap_reg_ppstg_tmp_42_reg_1723_pp1_it2[26] <= 1'b0;
ap_reg_ppstg_tmp_42_reg_1723_pp1_it2[27] <= 1'b0;
ap_reg_ppstg_tmp_42_reg_1723_pp1_it2[28] <= 1'b0;
ap_reg_ppstg_tmp_42_reg_1723_pp1_it2[29] <= 1'b0;
ap_reg_ppstg_tmp_42_reg_1723_pp1_it2[30] <= 1'b0;
ap_reg_ppstg_tmp_42_reg_1723_pp1_it2[31] <= 1'b0;
ap_reg_ppstg_tmp_42_reg_1723_pp1_it2[32] <= 1'b0;
ap_reg_ppstg_tmp_42_reg_1723_pp1_it2[33] <= 1'b0;
ap_reg_ppstg_tmp_42_reg_1723_pp1_it2[34] <= 1'b0;
ap_reg_ppstg_tmp_42_reg_1723_pp1_it2[35] <= 1'b0;
ap_reg_ppstg_tmp_42_reg_1723_pp1_it2[36] <= 1'b0;
ap_reg_ppstg_tmp_42_reg_1723_pp1_it2[37] <= 1'b0;
ap_reg_ppstg_tmp_42_reg_1723_pp1_it2[38] <= 1'b0;
ap_reg_ppstg_tmp_42_reg_1723_pp1_it2[39] <= 1'b0;
ap_reg_ppstg_tmp_42_reg_1723_pp1_it2[40] <= 1'b0;
ap_reg_ppstg_tmp_42_reg_1723_pp1_it2[41] <= 1'b0;
ap_reg_ppstg_tmp_42_reg_1723_pp1_it2[42] <= 1'b0;
ap_reg_ppstg_tmp_42_reg_1723_pp1_it2[43] <= 1'b0;
ap_reg_ppstg_tmp_42_reg_1723_pp1_it2[44] <= 1'b0;
ap_reg_ppstg_tmp_42_reg_1723_pp1_it2[45] <= 1'b0;
ap_reg_ppstg_tmp_42_reg_1723_pp1_it2[46] <= 1'b0;
ap_reg_ppstg_tmp_42_reg_1723_pp1_it2[47] <= 1'b0;
ap_reg_ppstg_tmp_42_reg_1723_pp1_it2[48] <= 1'b0;
ap_reg_ppstg_tmp_42_reg_1723_pp1_it2[49] <= 1'b0;
ap_reg_ppstg_tmp_42_reg_1723_pp1_it2[50] <= 1'b0;
ap_reg_ppstg_tmp_42_reg_1723_pp1_it2[51] <= 1'b0;
ap_reg_ppstg_tmp_42_reg_1723_pp1_it2[52] <= 1'b0;
ap_reg_ppstg_tmp_42_reg_1723_pp1_it2[53] <= 1'b0;
ap_reg_ppstg_tmp_42_reg_1723_pp1_it2[54] <= 1'b0;
ap_reg_ppstg_tmp_42_reg_1723_pp1_it2[55] <= 1'b0;
ap_reg_ppstg_tmp_42_reg_1723_pp1_it2[56] <= 1'b0;
ap_reg_ppstg_tmp_42_reg_1723_pp1_it2[57] <= 1'b0;
ap_reg_ppstg_tmp_42_reg_1723_pp1_it2[58] <= 1'b0;
ap_reg_ppstg_tmp_42_reg_1723_pp1_it2[59] <= 1'b0;
ap_reg_ppstg_tmp_42_reg_1723_pp1_it2[60] <= 1'b0;
ap_reg_ppstg_tmp_42_reg_1723_pp1_it2[61] <= 1'b0;
ap_reg_ppstg_tmp_42_reg_1723_pp1_it2[62] <= 1'b0;
ap_reg_ppstg_tmp_42_reg_1723_pp1_it2[63] <= 1'b0;
end
always @ (ap_clk)
begin
tmp_45_reg_1750[0] <= 1'b1;
tmp_45_reg_1750[14] <= 1'b0;
tmp_45_reg_1750[15] <= 1'b0;
tmp_45_reg_1750[16] <= 1'b0;
tmp_45_reg_1750[17] <= 1'b0;
tmp_45_reg_1750[18] <= 1'b0;
tmp_45_reg_1750[19] <= 1'b0;
tmp_45_reg_1750[20] <= 1'b0;
tmp_45_reg_1750[21] <= 1'b0;
tmp_45_reg_1750[22] <= 1'b0;
tmp_45_reg_1750[23] <= 1'b0;
tmp_45_reg_1750[24] <= 1'b0;
tmp_45_reg_1750[25] <= 1'b0;
tmp_45_reg_1750[26] <= 1'b0;
tmp_45_reg_1750[27] <= 1'b0;
tmp_45_reg_1750[28] <= 1'b0;
tmp_45_reg_1750[29] <= 1'b0;
tmp_45_reg_1750[30] <= 1'b0;
tmp_45_reg_1750[31] <= 1'b0;
tmp_45_reg_1750[32] <= 1'b0;
tmp_45_reg_1750[33] <= 1'b0;
tmp_45_reg_1750[34] <= 1'b0;
tmp_45_reg_1750[35] <= 1'b0;
tmp_45_reg_1750[36] <= 1'b0;
tmp_45_reg_1750[37] <= 1'b0;
tmp_45_reg_1750[38] <= 1'b0;
tmp_45_reg_1750[39] <= 1'b0;
tmp_45_reg_1750[40] <= 1'b0;
tmp_45_reg_1750[41] <= 1'b0;
tmp_45_reg_1750[42] <= 1'b0;
tmp_45_reg_1750[43] <= 1'b0;
tmp_45_reg_1750[44] <= 1'b0;
tmp_45_reg_1750[45] <= 1'b0;
tmp_45_reg_1750[46] <= 1'b0;
tmp_45_reg_1750[47] <= 1'b0;
tmp_45_reg_1750[48] <= 1'b0;
tmp_45_reg_1750[49] <= 1'b0;
tmp_45_reg_1750[50] <= 1'b0;
tmp_45_reg_1750[51] <= 1'b0;
tmp_45_reg_1750[52] <= 1'b0;
tmp_45_reg_1750[53] <= 1'b0;
tmp_45_reg_1750[54] <= 1'b0;
tmp_45_reg_1750[55] <= 1'b0;
tmp_45_reg_1750[56] <= 1'b0;
tmp_45_reg_1750[57] <= 1'b0;
tmp_45_reg_1750[58] <= 1'b0;
tmp_45_reg_1750[59] <= 1'b0;
tmp_45_reg_1750[60] <= 1'b0;
tmp_45_reg_1750[61] <= 1'b0;
tmp_45_reg_1750[62] <= 1'b0;
tmp_45_reg_1750[63] <= 1'b0;
end
always @ (ap_clk)
begin
ap_reg_ppstg_tmp_45_reg_1750_pp1_it1[0] <= 1'b1;
ap_reg_ppstg_tmp_45_reg_1750_pp1_it1[14] <= 1'b0;
ap_reg_ppstg_tmp_45_reg_1750_pp1_it1[15] <= 1'b0;
ap_reg_ppstg_tmp_45_reg_1750_pp1_it1[16] <= 1'b0;
ap_reg_ppstg_tmp_45_reg_1750_pp1_it1[17] <= 1'b0;
ap_reg_ppstg_tmp_45_reg_1750_pp1_it1[18] <= 1'b0;
ap_reg_ppstg_tmp_45_reg_1750_pp1_it1[19] <= 1'b0;
ap_reg_ppstg_tmp_45_reg_1750_pp1_it1[20] <= 1'b0;
ap_reg_ppstg_tmp_45_reg_1750_pp1_it1[21] <= 1'b0;
ap_reg_ppstg_tmp_45_reg_1750_pp1_it1[22] <= 1'b0;
ap_reg_ppstg_tmp_45_reg_1750_pp1_it1[23] <= 1'b0;
ap_reg_ppstg_tmp_45_reg_1750_pp1_it1[24] <= 1'b0;
ap_reg_ppstg_tmp_45_reg_1750_pp1_it1[25] <= 1'b0;
ap_reg_ppstg_tmp_45_reg_1750_pp1_it1[26] <= 1'b0;
ap_reg_ppstg_tmp_45_reg_1750_pp1_it1[27] <= 1'b0;
ap_reg_ppstg_tmp_45_reg_1750_pp1_it1[28] <= 1'b0;
ap_reg_ppstg_tmp_45_reg_1750_pp1_it1[29] <= 1'b0;
ap_reg_ppstg_tmp_45_reg_1750_pp1_it1[30] <= 1'b0;
ap_reg_ppstg_tmp_45_reg_1750_pp1_it1[31] <= 1'b0;
ap_reg_ppstg_tmp_45_reg_1750_pp1_it1[32] <= 1'b0;
ap_reg_ppstg_tmp_45_reg_1750_pp1_it1[33] <= 1'b0;
ap_reg_ppstg_tmp_45_reg_1750_pp1_it1[34] <= 1'b0;
ap_reg_ppstg_tmp_45_reg_1750_pp1_it1[35] <= 1'b0;
ap_reg_ppstg_tmp_45_reg_1750_pp1_it1[36] <= 1'b0;
ap_reg_ppstg_tmp_45_reg_1750_pp1_it1[37] <= 1'b0;
ap_reg_ppstg_tmp_45_reg_1750_pp1_it1[38] <= 1'b0;
ap_reg_ppstg_tmp_45_reg_1750_pp1_it1[39] <= 1'b0;
ap_reg_ppstg_tmp_45_reg_1750_pp1_it1[40] <= 1'b0;
ap_reg_ppstg_tmp_45_reg_1750_pp1_it1[41] <= 1'b0;
ap_reg_ppstg_tmp_45_reg_1750_pp1_it1[42] <= 1'b0;
ap_reg_ppstg_tmp_45_reg_1750_pp1_it1[43] <= 1'b0;
ap_reg_ppstg_tmp_45_reg_1750_pp1_it1[44] <= 1'b0;
ap_reg_ppstg_tmp_45_reg_1750_pp1_it1[45] <= 1'b0;
ap_reg_ppstg_tmp_45_reg_1750_pp1_it1[46] <= 1'b0;
ap_reg_ppstg_tmp_45_reg_1750_pp1_it1[47] <= 1'b0;
ap_reg_ppstg_tmp_45_reg_1750_pp1_it1[48] <= 1'b0;
ap_reg_ppstg_tmp_45_reg_1750_pp1_it1[49] <= 1'b0;
ap_reg_ppstg_tmp_45_reg_1750_pp1_it1[50] <= 1'b0;
ap_reg_ppstg_tmp_45_reg_1750_pp1_it1[51] <= 1'b0;
ap_reg_ppstg_tmp_45_reg_1750_pp1_it1[52] <= 1'b0;
ap_reg_ppstg_tmp_45_reg_1750_pp1_it1[53] <= 1'b0;
ap_reg_ppstg_tmp_45_reg_1750_pp1_it1[54] <= 1'b0;
ap_reg_ppstg_tmp_45_reg_1750_pp1_it1[55] <= 1'b0;
ap_reg_ppstg_tmp_45_reg_1750_pp1_it1[56] <= 1'b0;
ap_reg_ppstg_tmp_45_reg_1750_pp1_it1[57] <= 1'b0;
ap_reg_ppstg_tmp_45_reg_1750_pp1_it1[58] <= 1'b0;
ap_reg_ppstg_tmp_45_reg_1750_pp1_it1[59] <= 1'b0;
ap_reg_ppstg_tmp_45_reg_1750_pp1_it1[60] <= 1'b0;
ap_reg_ppstg_tmp_45_reg_1750_pp1_it1[61] <= 1'b0;
ap_reg_ppstg_tmp_45_reg_1750_pp1_it1[62] <= 1'b0;
ap_reg_ppstg_tmp_45_reg_1750_pp1_it1[63] <= 1'b0;
end
always @ (ap_clk)
begin
ap_reg_ppstg_tmp_45_reg_1750_pp1_it2[0] <= 1'b1;
ap_reg_ppstg_tmp_45_reg_1750_pp1_it2[14] <= 1'b0;
ap_reg_ppstg_tmp_45_reg_1750_pp1_it2[15] <= 1'b0;
ap_reg_ppstg_tmp_45_reg_1750_pp1_it2[16] <= 1'b0;
ap_reg_ppstg_tmp_45_reg_1750_pp1_it2[17] <= 1'b0;
ap_reg_ppstg_tmp_45_reg_1750_pp1_it2[18] <= 1'b0;
ap_reg_ppstg_tmp_45_reg_1750_pp1_it2[19] <= 1'b0;
ap_reg_ppstg_tmp_45_reg_1750_pp1_it2[20] <= 1'b0;
ap_reg_ppstg_tmp_45_reg_1750_pp1_it2[21] <= 1'b0;
ap_reg_ppstg_tmp_45_reg_1750_pp1_it2[22] <= 1'b0;
ap_reg_ppstg_tmp_45_reg_1750_pp1_it2[23] <= 1'b0;
ap_reg_ppstg_tmp_45_reg_1750_pp1_it2[24] <= 1'b0;
ap_reg_ppstg_tmp_45_reg_1750_pp1_it2[25] <= 1'b0;
ap_reg_ppstg_tmp_45_reg_1750_pp1_it2[26] <= 1'b0;
ap_reg_ppstg_tmp_45_reg_1750_pp1_it2[27] <= 1'b0;
ap_reg_ppstg_tmp_45_reg_1750_pp1_it2[28] <= 1'b0;
ap_reg_ppstg_tmp_45_reg_1750_pp1_it2[29] <= 1'b0;
ap_reg_ppstg_tmp_45_reg_1750_pp1_it2[30] <= 1'b0;
ap_reg_ppstg_tmp_45_reg_1750_pp1_it2[31] <= 1'b0;
ap_reg_ppstg_tmp_45_reg_1750_pp1_it2[32] <= 1'b0;
ap_reg_ppstg_tmp_45_reg_1750_pp1_it2[33] <= 1'b0;
ap_reg_ppstg_tmp_45_reg_1750_pp1_it2[34] <= 1'b0;
ap_reg_ppstg_tmp_45_reg_1750_pp1_it2[35] <= 1'b0;
ap_reg_ppstg_tmp_45_reg_1750_pp1_it2[36] <= 1'b0;
ap_reg_ppstg_tmp_45_reg_1750_pp1_it2[37] <= 1'b0;
ap_reg_ppstg_tmp_45_reg_1750_pp1_it2[38] <= 1'b0;
ap_reg_ppstg_tmp_45_reg_1750_pp1_it2[39] <= 1'b0;
ap_reg_ppstg_tmp_45_reg_1750_pp1_it2[40] <= 1'b0;
ap_reg_ppstg_tmp_45_reg_1750_pp1_it2[41] <= 1'b0;
ap_reg_ppstg_tmp_45_reg_1750_pp1_it2[42] <= 1'b0;
ap_reg_ppstg_tmp_45_reg_1750_pp1_it2[43] <= 1'b0;
ap_reg_ppstg_tmp_45_reg_1750_pp1_it2[44] <= 1'b0;
ap_reg_ppstg_tmp_45_reg_1750_pp1_it2[45] <= 1'b0;
ap_reg_ppstg_tmp_45_reg_1750_pp1_it2[46] <= 1'b0;
ap_reg_ppstg_tmp_45_reg_1750_pp1_it2[47] <= 1'b0;
ap_reg_ppstg_tmp_45_reg_1750_pp1_it2[48] <= 1'b0;
ap_reg_ppstg_tmp_45_reg_1750_pp1_it2[49] <= 1'b0;
ap_reg_ppstg_tmp_45_reg_1750_pp1_it2[50] <= 1'b0;
ap_reg_ppstg_tmp_45_reg_1750_pp1_it2[51] <= 1'b0;
ap_reg_ppstg_tmp_45_reg_1750_pp1_it2[52] <= 1'b0;
ap_reg_ppstg_tmp_45_reg_1750_pp1_it2[53] <= 1'b0;
ap_reg_ppstg_tmp_45_reg_1750_pp1_it2[54] <= 1'b0;
ap_reg_ppstg_tmp_45_reg_1750_pp1_it2[55] <= 1'b0;
ap_reg_ppstg_tmp_45_reg_1750_pp1_it2[56] <= 1'b0;
ap_reg_ppstg_tmp_45_reg_1750_pp1_it2[57] <= 1'b0;
ap_reg_ppstg_tmp_45_reg_1750_pp1_it2[58] <= 1'b0;
ap_reg_ppstg_tmp_45_reg_1750_pp1_it2[59] <= 1'b0;
ap_reg_ppstg_tmp_45_reg_1750_pp1_it2[60] <= 1'b0;
ap_reg_ppstg_tmp_45_reg_1750_pp1_it2[61] <= 1'b0;
ap_reg_ppstg_tmp_45_reg_1750_pp1_it2[62] <= 1'b0;
ap_reg_ppstg_tmp_45_reg_1750_pp1_it2[63] <= 1'b0;
end
always @ (ap_clk)
begin
tmp_48_reg_1767[14] <= 1'b0;
tmp_48_reg_1767[15] <= 1'b0;
tmp_48_reg_1767[16] <= 1'b0;
tmp_48_reg_1767[17] <= 1'b0;
tmp_48_reg_1767[18] <= 1'b0;
tmp_48_reg_1767[19] <= 1'b0;
tmp_48_reg_1767[20] <= 1'b0;
tmp_48_reg_1767[21] <= 1'b0;
tmp_48_reg_1767[22] <= 1'b0;
tmp_48_reg_1767[23] <= 1'b0;
tmp_48_reg_1767[24] <= 1'b0;
tmp_48_reg_1767[25] <= 1'b0;
tmp_48_reg_1767[26] <= 1'b0;
tmp_48_reg_1767[27] <= 1'b0;
tmp_48_reg_1767[28] <= 1'b0;
tmp_48_reg_1767[29] <= 1'b0;
tmp_48_reg_1767[30] <= 1'b0;
tmp_48_reg_1767[31] <= 1'b0;
tmp_48_reg_1767[32] <= 1'b0;
tmp_48_reg_1767[33] <= 1'b0;
tmp_48_reg_1767[34] <= 1'b0;
tmp_48_reg_1767[35] <= 1'b0;
tmp_48_reg_1767[36] <= 1'b0;
tmp_48_reg_1767[37] <= 1'b0;
tmp_48_reg_1767[38] <= 1'b0;
tmp_48_reg_1767[39] <= 1'b0;
tmp_48_reg_1767[40] <= 1'b0;
tmp_48_reg_1767[41] <= 1'b0;
tmp_48_reg_1767[42] <= 1'b0;
tmp_48_reg_1767[43] <= 1'b0;
tmp_48_reg_1767[44] <= 1'b0;
tmp_48_reg_1767[45] <= 1'b0;
tmp_48_reg_1767[46] <= 1'b0;
tmp_48_reg_1767[47] <= 1'b0;
tmp_48_reg_1767[48] <= 1'b0;
tmp_48_reg_1767[49] <= 1'b0;
tmp_48_reg_1767[50] <= 1'b0;
tmp_48_reg_1767[51] <= 1'b0;
tmp_48_reg_1767[52] <= 1'b0;
tmp_48_reg_1767[53] <= 1'b0;
tmp_48_reg_1767[54] <= 1'b0;
tmp_48_reg_1767[55] <= 1'b0;
tmp_48_reg_1767[56] <= 1'b0;
tmp_48_reg_1767[57] <= 1'b0;
tmp_48_reg_1767[58] <= 1'b0;
tmp_48_reg_1767[59] <= 1'b0;
tmp_48_reg_1767[60] <= 1'b0;
tmp_48_reg_1767[61] <= 1'b0;
tmp_48_reg_1767[62] <= 1'b0;
tmp_48_reg_1767[63] <= 1'b0;
end
always @ (ap_clk)
begin
ap_reg_ppstg_tmp_48_reg_1767_pp1_it1[14] <= 1'b0;
ap_reg_ppstg_tmp_48_reg_1767_pp1_it1[15] <= 1'b0;
ap_reg_ppstg_tmp_48_reg_1767_pp1_it1[16] <= 1'b0;
ap_reg_ppstg_tmp_48_reg_1767_pp1_it1[17] <= 1'b0;
ap_reg_ppstg_tmp_48_reg_1767_pp1_it1[18] <= 1'b0;
ap_reg_ppstg_tmp_48_reg_1767_pp1_it1[19] <= 1'b0;
ap_reg_ppstg_tmp_48_reg_1767_pp1_it1[20] <= 1'b0;
ap_reg_ppstg_tmp_48_reg_1767_pp1_it1[21] <= 1'b0;
ap_reg_ppstg_tmp_48_reg_1767_pp1_it1[22] <= 1'b0;
ap_reg_ppstg_tmp_48_reg_1767_pp1_it1[23] <= 1'b0;
ap_reg_ppstg_tmp_48_reg_1767_pp1_it1[24] <= 1'b0;
ap_reg_ppstg_tmp_48_reg_1767_pp1_it1[25] <= 1'b0;
ap_reg_ppstg_tmp_48_reg_1767_pp1_it1[26] <= 1'b0;
ap_reg_ppstg_tmp_48_reg_1767_pp1_it1[27] <= 1'b0;
ap_reg_ppstg_tmp_48_reg_1767_pp1_it1[28] <= 1'b0;
ap_reg_ppstg_tmp_48_reg_1767_pp1_it1[29] <= 1'b0;
ap_reg_ppstg_tmp_48_reg_1767_pp1_it1[30] <= 1'b0;
ap_reg_ppstg_tmp_48_reg_1767_pp1_it1[31] <= 1'b0;
ap_reg_ppstg_tmp_48_reg_1767_pp1_it1[32] <= 1'b0;
ap_reg_ppstg_tmp_48_reg_1767_pp1_it1[33] <= 1'b0;
ap_reg_ppstg_tmp_48_reg_1767_pp1_it1[34] <= 1'b0;
ap_reg_ppstg_tmp_48_reg_1767_pp1_it1[35] <= 1'b0;
ap_reg_ppstg_tmp_48_reg_1767_pp1_it1[36] <= 1'b0;
ap_reg_ppstg_tmp_48_reg_1767_pp1_it1[37] <= 1'b0;
ap_reg_ppstg_tmp_48_reg_1767_pp1_it1[38] <= 1'b0;
ap_reg_ppstg_tmp_48_reg_1767_pp1_it1[39] <= 1'b0;
ap_reg_ppstg_tmp_48_reg_1767_pp1_it1[40] <= 1'b0;
ap_reg_ppstg_tmp_48_reg_1767_pp1_it1[41] <= 1'b0;
ap_reg_ppstg_tmp_48_reg_1767_pp1_it1[42] <= 1'b0;
ap_reg_ppstg_tmp_48_reg_1767_pp1_it1[43] <= 1'b0;
ap_reg_ppstg_tmp_48_reg_1767_pp1_it1[44] <= 1'b0;
ap_reg_ppstg_tmp_48_reg_1767_pp1_it1[45] <= 1'b0;
ap_reg_ppstg_tmp_48_reg_1767_pp1_it1[46] <= 1'b0;
ap_reg_ppstg_tmp_48_reg_1767_pp1_it1[47] <= 1'b0;
ap_reg_ppstg_tmp_48_reg_1767_pp1_it1[48] <= 1'b0;
ap_reg_ppstg_tmp_48_reg_1767_pp1_it1[49] <= 1'b0;
ap_reg_ppstg_tmp_48_reg_1767_pp1_it1[50] <= 1'b0;
ap_reg_ppstg_tmp_48_reg_1767_pp1_it1[51] <= 1'b0;
ap_reg_ppstg_tmp_48_reg_1767_pp1_it1[52] <= 1'b0;
ap_reg_ppstg_tmp_48_reg_1767_pp1_it1[53] <= 1'b0;
ap_reg_ppstg_tmp_48_reg_1767_pp1_it1[54] <= 1'b0;
ap_reg_ppstg_tmp_48_reg_1767_pp1_it1[55] <= 1'b0;
ap_reg_ppstg_tmp_48_reg_1767_pp1_it1[56] <= 1'b0;
ap_reg_ppstg_tmp_48_reg_1767_pp1_it1[57] <= 1'b0;
ap_reg_ppstg_tmp_48_reg_1767_pp1_it1[58] <= 1'b0;
ap_reg_ppstg_tmp_48_reg_1767_pp1_it1[59] <= 1'b0;
ap_reg_ppstg_tmp_48_reg_1767_pp1_it1[60] <= 1'b0;
ap_reg_ppstg_tmp_48_reg_1767_pp1_it1[61] <= 1'b0;
ap_reg_ppstg_tmp_48_reg_1767_pp1_it1[62] <= 1'b0;
ap_reg_ppstg_tmp_48_reg_1767_pp1_it1[63] <= 1'b0;
end
always @ (ap_clk)
begin
ap_reg_ppstg_tmp_48_reg_1767_pp1_it2[14] <= 1'b0;
ap_reg_ppstg_tmp_48_reg_1767_pp1_it2[15] <= 1'b0;
ap_reg_ppstg_tmp_48_reg_1767_pp1_it2[16] <= 1'b0;
ap_reg_ppstg_tmp_48_reg_1767_pp1_it2[17] <= 1'b0;
ap_reg_ppstg_tmp_48_reg_1767_pp1_it2[18] <= 1'b0;
ap_reg_ppstg_tmp_48_reg_1767_pp1_it2[19] <= 1'b0;
ap_reg_ppstg_tmp_48_reg_1767_pp1_it2[20] <= 1'b0;
ap_reg_ppstg_tmp_48_reg_1767_pp1_it2[21] <= 1'b0;
ap_reg_ppstg_tmp_48_reg_1767_pp1_it2[22] <= 1'b0;
ap_reg_ppstg_tmp_48_reg_1767_pp1_it2[23] <= 1'b0;
ap_reg_ppstg_tmp_48_reg_1767_pp1_it2[24] <= 1'b0;
ap_reg_ppstg_tmp_48_reg_1767_pp1_it2[25] <= 1'b0;
ap_reg_ppstg_tmp_48_reg_1767_pp1_it2[26] <= 1'b0;
ap_reg_ppstg_tmp_48_reg_1767_pp1_it2[27] <= 1'b0;
ap_reg_ppstg_tmp_48_reg_1767_pp1_it2[28] <= 1'b0;
ap_reg_ppstg_tmp_48_reg_1767_pp1_it2[29] <= 1'b0;
ap_reg_ppstg_tmp_48_reg_1767_pp1_it2[30] <= 1'b0;
ap_reg_ppstg_tmp_48_reg_1767_pp1_it2[31] <= 1'b0;
ap_reg_ppstg_tmp_48_reg_1767_pp1_it2[32] <= 1'b0;
ap_reg_ppstg_tmp_48_reg_1767_pp1_it2[33] <= 1'b0;
ap_reg_ppstg_tmp_48_reg_1767_pp1_it2[34] <= 1'b0;
ap_reg_ppstg_tmp_48_reg_1767_pp1_it2[35] <= 1'b0;
ap_reg_ppstg_tmp_48_reg_1767_pp1_it2[36] <= 1'b0;
ap_reg_ppstg_tmp_48_reg_1767_pp1_it2[37] <= 1'b0;
ap_reg_ppstg_tmp_48_reg_1767_pp1_it2[38] <= 1'b0;
ap_reg_ppstg_tmp_48_reg_1767_pp1_it2[39] <= 1'b0;
ap_reg_ppstg_tmp_48_reg_1767_pp1_it2[40] <= 1'b0;
ap_reg_ppstg_tmp_48_reg_1767_pp1_it2[41] <= 1'b0;
ap_reg_ppstg_tmp_48_reg_1767_pp1_it2[42] <= 1'b0;
ap_reg_ppstg_tmp_48_reg_1767_pp1_it2[43] <= 1'b0;
ap_reg_ppstg_tmp_48_reg_1767_pp1_it2[44] <= 1'b0;
ap_reg_ppstg_tmp_48_reg_1767_pp1_it2[45] <= 1'b0;
ap_reg_ppstg_tmp_48_reg_1767_pp1_it2[46] <= 1'b0;
ap_reg_ppstg_tmp_48_reg_1767_pp1_it2[47] <= 1'b0;
ap_reg_ppstg_tmp_48_reg_1767_pp1_it2[48] <= 1'b0;
ap_reg_ppstg_tmp_48_reg_1767_pp1_it2[49] <= 1'b0;
ap_reg_ppstg_tmp_48_reg_1767_pp1_it2[50] <= 1'b0;
ap_reg_ppstg_tmp_48_reg_1767_pp1_it2[51] <= 1'b0;
ap_reg_ppstg_tmp_48_reg_1767_pp1_it2[52] <= 1'b0;
ap_reg_ppstg_tmp_48_reg_1767_pp1_it2[53] <= 1'b0;
ap_reg_ppstg_tmp_48_reg_1767_pp1_it2[54] <= 1'b0;
ap_reg_ppstg_tmp_48_reg_1767_pp1_it2[55] <= 1'b0;
ap_reg_ppstg_tmp_48_reg_1767_pp1_it2[56] <= 1'b0;
ap_reg_ppstg_tmp_48_reg_1767_pp1_it2[57] <= 1'b0;
ap_reg_ppstg_tmp_48_reg_1767_pp1_it2[58] <= 1'b0;
ap_reg_ppstg_tmp_48_reg_1767_pp1_it2[59] <= 1'b0;
ap_reg_ppstg_tmp_48_reg_1767_pp1_it2[60] <= 1'b0;
ap_reg_ppstg_tmp_48_reg_1767_pp1_it2[61] <= 1'b0;
ap_reg_ppstg_tmp_48_reg_1767_pp1_it2[62] <= 1'b0;
ap_reg_ppstg_tmp_48_reg_1767_pp1_it2[63] <= 1'b0;
end
always @ (ap_clk)
begin
b_addr17_reg_1784[0] <= 1'b1;
b_addr17_reg_1784[1] <= 1'b1;
b_addr17_reg_1784[2] <= 1'b1;
end
always @ (ap_clk)
begin
tmp_51_reg_1804[0] <= 1'b1;
tmp_51_reg_1804[1] <= 1'b1;
tmp_51_reg_1804[2] <= 1'b1;
tmp_51_reg_1804[14] <= 1'b0;
tmp_51_reg_1804[15] <= 1'b0;
tmp_51_reg_1804[16] <= 1'b0;
tmp_51_reg_1804[17] <= 1'b0;
tmp_51_reg_1804[18] <= 1'b0;
tmp_51_reg_1804[19] <= 1'b0;
tmp_51_reg_1804[20] <= 1'b0;
tmp_51_reg_1804[21] <= 1'b0;
tmp_51_reg_1804[22] <= 1'b0;
tmp_51_reg_1804[23] <= 1'b0;
tmp_51_reg_1804[24] <= 1'b0;
tmp_51_reg_1804[25] <= 1'b0;
tmp_51_reg_1804[26] <= 1'b0;
tmp_51_reg_1804[27] <= 1'b0;
tmp_51_reg_1804[28] <= 1'b0;
tmp_51_reg_1804[29] <= 1'b0;
tmp_51_reg_1804[30] <= 1'b0;
tmp_51_reg_1804[31] <= 1'b0;
tmp_51_reg_1804[32] <= 1'b0;
tmp_51_reg_1804[33] <= 1'b0;
tmp_51_reg_1804[34] <= 1'b0;
tmp_51_reg_1804[35] <= 1'b0;
tmp_51_reg_1804[36] <= 1'b0;
tmp_51_reg_1804[37] <= 1'b0;
tmp_51_reg_1804[38] <= 1'b0;
tmp_51_reg_1804[39] <= 1'b0;
tmp_51_reg_1804[40] <= 1'b0;
tmp_51_reg_1804[41] <= 1'b0;
tmp_51_reg_1804[42] <= 1'b0;
tmp_51_reg_1804[43] <= 1'b0;
tmp_51_reg_1804[44] <= 1'b0;
tmp_51_reg_1804[45] <= 1'b0;
tmp_51_reg_1804[46] <= 1'b0;
tmp_51_reg_1804[47] <= 1'b0;
tmp_51_reg_1804[48] <= 1'b0;
tmp_51_reg_1804[49] <= 1'b0;
tmp_51_reg_1804[50] <= 1'b0;
tmp_51_reg_1804[51] <= 1'b0;
tmp_51_reg_1804[52] <= 1'b0;
tmp_51_reg_1804[53] <= 1'b0;
tmp_51_reg_1804[54] <= 1'b0;
tmp_51_reg_1804[55] <= 1'b0;
tmp_51_reg_1804[56] <= 1'b0;
tmp_51_reg_1804[57] <= 1'b0;
tmp_51_reg_1804[58] <= 1'b0;
tmp_51_reg_1804[59] <= 1'b0;
tmp_51_reg_1804[60] <= 1'b0;
tmp_51_reg_1804[61] <= 1'b0;
tmp_51_reg_1804[62] <= 1'b0;
tmp_51_reg_1804[63] <= 1'b0;
end
always @ (ap_clk)
begin
ap_reg_ppstg_tmp_51_reg_1804_pp1_it1[0] <= 1'b1;
ap_reg_ppstg_tmp_51_reg_1804_pp1_it1[1] <= 1'b1;
ap_reg_ppstg_tmp_51_reg_1804_pp1_it1[2] <= 1'b1;
ap_reg_ppstg_tmp_51_reg_1804_pp1_it1[14] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_1804_pp1_it1[15] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_1804_pp1_it1[16] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_1804_pp1_it1[17] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_1804_pp1_it1[18] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_1804_pp1_it1[19] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_1804_pp1_it1[20] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_1804_pp1_it1[21] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_1804_pp1_it1[22] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_1804_pp1_it1[23] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_1804_pp1_it1[24] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_1804_pp1_it1[25] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_1804_pp1_it1[26] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_1804_pp1_it1[27] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_1804_pp1_it1[28] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_1804_pp1_it1[29] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_1804_pp1_it1[30] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_1804_pp1_it1[31] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_1804_pp1_it1[32] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_1804_pp1_it1[33] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_1804_pp1_it1[34] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_1804_pp1_it1[35] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_1804_pp1_it1[36] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_1804_pp1_it1[37] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_1804_pp1_it1[38] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_1804_pp1_it1[39] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_1804_pp1_it1[40] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_1804_pp1_it1[41] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_1804_pp1_it1[42] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_1804_pp1_it1[43] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_1804_pp1_it1[44] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_1804_pp1_it1[45] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_1804_pp1_it1[46] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_1804_pp1_it1[47] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_1804_pp1_it1[48] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_1804_pp1_it1[49] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_1804_pp1_it1[50] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_1804_pp1_it1[51] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_1804_pp1_it1[52] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_1804_pp1_it1[53] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_1804_pp1_it1[54] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_1804_pp1_it1[55] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_1804_pp1_it1[56] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_1804_pp1_it1[57] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_1804_pp1_it1[58] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_1804_pp1_it1[59] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_1804_pp1_it1[60] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_1804_pp1_it1[61] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_1804_pp1_it1[62] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_1804_pp1_it1[63] <= 1'b0;
end
always @ (ap_clk)
begin
ap_reg_ppstg_tmp_51_reg_1804_pp1_it2[0] <= 1'b1;
ap_reg_ppstg_tmp_51_reg_1804_pp1_it2[1] <= 1'b1;
ap_reg_ppstg_tmp_51_reg_1804_pp1_it2[2] <= 1'b1;
ap_reg_ppstg_tmp_51_reg_1804_pp1_it2[14] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_1804_pp1_it2[15] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_1804_pp1_it2[16] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_1804_pp1_it2[17] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_1804_pp1_it2[18] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_1804_pp1_it2[19] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_1804_pp1_it2[20] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_1804_pp1_it2[21] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_1804_pp1_it2[22] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_1804_pp1_it2[23] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_1804_pp1_it2[24] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_1804_pp1_it2[25] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_1804_pp1_it2[26] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_1804_pp1_it2[27] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_1804_pp1_it2[28] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_1804_pp1_it2[29] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_1804_pp1_it2[30] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_1804_pp1_it2[31] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_1804_pp1_it2[32] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_1804_pp1_it2[33] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_1804_pp1_it2[34] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_1804_pp1_it2[35] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_1804_pp1_it2[36] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_1804_pp1_it2[37] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_1804_pp1_it2[38] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_1804_pp1_it2[39] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_1804_pp1_it2[40] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_1804_pp1_it2[41] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_1804_pp1_it2[42] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_1804_pp1_it2[43] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_1804_pp1_it2[44] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_1804_pp1_it2[45] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_1804_pp1_it2[46] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_1804_pp1_it2[47] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_1804_pp1_it2[48] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_1804_pp1_it2[49] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_1804_pp1_it2[50] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_1804_pp1_it2[51] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_1804_pp1_it2[52] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_1804_pp1_it2[53] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_1804_pp1_it2[54] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_1804_pp1_it2[55] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_1804_pp1_it2[56] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_1804_pp1_it2[57] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_1804_pp1_it2[58] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_1804_pp1_it2[59] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_1804_pp1_it2[60] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_1804_pp1_it2[61] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_1804_pp1_it2[62] <= 1'b0;
ap_reg_ppstg_tmp_51_reg_1804_pp1_it2[63] <= 1'b0;
end
endmodule //step1
|
// ==============================================================
// File generated by AutoESL - High-Level Synthesis System (C, C++, SystemC)
// Version: 2011.1
// Copyright (C) 2011 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module step1_grp_fu_811_ACMP_fadd_13(
clk,
reset,
ce,
din0,
din1,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
output[dout_WIDTH - 1:0] dout;
ACMP_fadd #(
.ID( ID ),
.NUM_STAGE( 5 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_fadd_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ));
endmodule
|
// ==============================================================
// File generated by AutoESL - High-Level Synthesis System (C, C++, SystemC)
// Version: 2011.1
// Copyright (C) 2011 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module step1_grp_fu_815_ACMP_fmul_14(
clk,
reset,
ce,
din0,
din1,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
output[dout_WIDTH - 1:0] dout;
ACMP_fmul #(
.ID( ID ),
.NUM_STAGE( 4 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_fmul_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ));
endmodule
|
// ==============================================================
// File generated by AutoESL - High-Level Synthesis System (C, C++, SystemC)
// Version: 2011.1
// Copyright (C) 2011 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module step1_grp_fu_819_ACMP_fmul_15(
clk,
reset,
ce,
din0,
din1,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
output[dout_WIDTH - 1:0] dout;
ACMP_fmul #(
.ID( ID ),
.NUM_STAGE( 4 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_fmul_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ));
endmodule
|
// ==============================================================
// RTL generated by AutoESL - High-Level Synthesis System (C, C++, SystemC)
// Version: 2011.1
// Copyright (C) 2011 Xilinx Inc. All rights reserved.
//
// ===========================================================
`timescale 1 ns / 1 ps
module write_r (
ap_clk,
ap_rst,
ap_start,
ap_done,
ap_idle,
tag,
counter,
d_address0,
d_ce0,
d_q0,
d_address1,
d_ce1,
d_q1,
V_bus_req_din,
V_bus_req_full_n,
V_bus_req_write,
V_bus_rsp_dout,
V_bus_rsp_empty_n,
V_bus_rsp_read,
V_bus_address,
V_bus_datain,
V_bus_dataout,
V_bus_size
);
input ap_clk;
input ap_rst;
input ap_start;
output ap_done;
output ap_idle;
input [1:0] tag;
input [6:0] counter;
output [11:0] d_address0;
output d_ce0;
input [31:0] d_q0;
output [11:0] d_address1;
output d_ce1;
input [31:0] d_q1;
output V_bus_req_din;
input V_bus_req_full_n;
output V_bus_req_write;
input V_bus_rsp_dout;
input V_bus_rsp_empty_n;
output V_bus_rsp_read;
output [31:0] V_bus_address;
input [127:0] V_bus_datain;
output [127:0] V_bus_dataout;
output [31:0] V_bus_size;
reg ap_done;
reg ap_idle;
reg[11:0] d_address0;
reg d_ce0;
reg[11:0] d_address1;
reg d_ce1;
reg V_bus_req_din;
reg V_bus_req_write;
reg[31:0] V_bus_address;
reg[127:0] V_bus_dataout;
reg [2:0] ap_CS_fsm;
reg [10:0] indvar_flatten1_reg_135;
reg [6:0] i_1_reg_146;
reg [4:0] indvar_reg_157;
reg [6:0] j_1_reg_168;
reg [10:0] indvar_flatten_reg_179;
reg [6:0] i_reg_190;
reg [4:0] indvar1_reg_201;
reg [6:0] j_reg_212;
reg [31:0] reg_224;
reg ap_reg_ppiten_pp0_it2;
reg ap_reg_ppiten_pp0_it0;
reg ap_reg_ppiten_pp0_it1;
reg [0:0] exitcond2_reg_672;
reg [0:0] ap_reg_ppstg_exitcond2_reg_672_pp0_it2;
reg ap_sig_bdd_73;
reg ap_reg_ppiten_pp0_it3;
reg ap_reg_ppiten_pp0_it4;
reg [0:0] ap_reg_ppstg_exitcond2_reg_672_pp0_it1;
reg ap_reg_ppiten_pp1_it2;
reg ap_reg_ppiten_pp1_it0;
reg ap_reg_ppiten_pp1_it1;
reg [0:0] exitcond_reg_736;
reg [0:0] ap_reg_ppstg_exitcond_reg_736_pp1_it2;
reg ap_sig_bdd_96;
reg ap_reg_ppiten_pp1_it3;
reg ap_reg_ppiten_pp1_it4;
reg [0:0] ap_reg_ppstg_exitcond_reg_736_pp1_it1;
reg [31:0] reg_228;
wire [19:0] tmp1_cast_fu_266_p1;
reg [19:0] tmp1_cast_reg_662;
wire [0:0] or_cond_fu_244_p2;
wire [19:0] tmp3_fu_270_p2;
reg [19:0] tmp3_reg_667;
wire [0:0] tmp_3_fu_250_p2;
wire [0:0] exitcond2_fu_276_p2;
reg [10:0] indvar_flatten_next1_reg_676;
reg [4:0] indvar_mid2_reg_681;
reg [4:0] ap_reg_ppstg_indvar_mid2_reg_681_pp0_it1;
reg [6:0] j_1_mid2_reg_687;
reg [6:0] i_1_mid2_reg_694;
reg [6:0] ap_reg_ppstg_i_1_mid2_reg_694_pp0_it1;
wire [6:0] tmp_18_fu_371_p2;
wire [4:0] indvar_next_fu_376_p2;
reg [17:0] tmp_16_reg_721;
wire [127:0] tmp_15_fu_444_p1;
wire [0:0] exitcond_fu_459_p2;
reg [10:0] indvar_flatten_next_reg_740;
reg [4:0] indvar1_mid2_reg_745;
reg [4:0] ap_reg_ppstg_indvar1_mid2_reg_745_pp1_it1;
reg [6:0] j_mid2_reg_751;
reg [6:0] i_mid2_reg_758;
reg [6:0] ap_reg_ppstg_i_mid2_reg_758_pp1_it1;
wire [6:0] tmp_10_fu_554_p2;
wire [4:0] indvar_next1_fu_559_p2;
reg [19:0] tmp_7_reg_785;
wire [127:0] tmp_s_fu_641_p1;
reg [10:0] indvar_flatten1_phi_fu_139_p4;
reg [6:0] i_1_phi_fu_150_p4;
reg [4:0] indvar_phi_fu_161_p4;
reg [6:0] j_1_phi_fu_172_p4;
reg [10:0] indvar_flatten_phi_fu_183_p4;
reg [6:0] i_phi_fu_194_p4;
reg [4:0] indvar1_phi_fu_205_p4;
reg [6:0] j_phi_fu_216_p4;
wire [63:0] tmp_12_fu_346_p1;
wire [63:0] tmp_14_fu_366_p1;
wire [63:0] tmp_5_fu_529_p1;
wire [63:0] tmp_6_fu_549_p1;
wire [63:0] tmp_17_fu_449_p1;
wire [63:0] tmp_9_fu_646_p1;
wire [0:0] tmp_1_fu_232_p2;
wire [0:0] tmp_2_fu_238_p2;
wire [18:0] counter_cast_fu_256_p1;
wire [18:0] tmp1_fu_260_p2;
wire [0:0] exitcond3_fu_288_p2;
wire [6:0] tmp_13_dup_fu_310_p2;
wire [12:0] tmp_5_trn2_cast_fu_324_p1;
wire [12:0] d_addr3_fu_330_p2;
wire [13:0] d_addr3_cast_fu_336_p1;
wire [13:0] tmp_14_trn_cast_fu_327_p1;
wire [13:0] d_addr4_fu_340_p2;
wire [6:0] tmp_13_fu_351_p2;
wire [13:0] tmp_16_trn_cast_fu_356_p1;
wire [13:0] d_addr1_fu_360_p2;
wire [12:0] i_1_cast_fu_381_p1;
wire [6:0] indvar_cast_fu_390_p1;
wire [6:0] tmp_fu_393_p2;
wire [12:0] tmp6_fu_384_p2;
wire [12:0] tmp_cast_fu_399_p1;
wire [12:0] tmp7_fu_403_p2;
wire [19:0] tmp7_cast_cast_fu_409_p1;
wire [19:0] tmp10_fu_413_p2;
wire [31:0] tmp13_fu_432_p1;
wire [31:0] tmp14_fu_428_p1;
wire [63:0] p_0_fu_436_p3;
wire [0:0] exitcond1_fu_471_p2;
wire [6:0] tmp_6_dup_fu_493_p2;
wire [12:0] tmp_4_trn7_cast_fu_507_p1;
wire [12:0] d_addr8_fu_513_p2;
wire [13:0] d_addr8_cast_fu_519_p1;
wire [13:0] tmp_7_trn_cast_fu_510_p1;
wire [13:0] d_addr9_fu_523_p2;
wire [6:0] tmp_8_fu_534_p2;
wire [13:0] tmp_9_trn_cast_fu_539_p1;
wire [13:0] d_addr6_fu_543_p2;
wire [12:0] i_cast_fu_564_p1;
wire [12:0] tmp4_fu_567_p2;
wire [19:0] tmp4_cast_fu_573_p1;
wire [19:0] tmp2_fu_577_p2;
wire [6:0] indvar1_cast_fu_586_p1;
wire [6:0] tmp8_fu_589_p2;
wire [14:0] tmp8_cast_fu_595_p1;
wire [14:0] tmp5_fu_599_p2;
wire [21:0] tmp9_fu_609_p0;
wire [21:0] tmp2_cast_fu_582_p1;
wire [21:0] tmp9_fu_609_p2;
wire [31:0] tmp11_fu_629_p1;
wire [31:0] tmp12_fu_625_p1;
wire [63:0] p_s_fu_633_p3;
reg [2:0] ap_NS_fsm;
parameter ap_const_logic_1 = 1'b1;
parameter ap_const_logic_0 = 1'b0;
parameter ap_ST_st0_fsm_0 = 3'b000;
parameter ap_ST_st1_fsm_1 = 3'b001;
parameter ap_ST_pp0_stg0_fsm_2 = 3'b010;
parameter ap_ST_pp1_stg0_fsm_3 = 3'b011;
parameter ap_ST_st12_fsm_4 = 3'b100;
parameter ap_const_lv1_0 = 1'b0;
parameter ap_const_lv11_0 = 11'b00000000000;
parameter ap_const_lv7_0 = 7'b0000000;
parameter ap_const_lv5_0 = 5'b00000;
parameter ap_const_lv32_0 = 32'b00000000000000000000000000000000;
parameter ap_const_lv7_43 = 7'b1000011;
parameter ap_const_lv7_2 = 7'b0000010;
parameter ap_const_lv2_0 = 2'b00;
parameter ap_const_lv19_C = 19'b0000000000000001100;
parameter ap_const_lv20_42000 = 20'b01000010000000000000;
parameter ap_const_lv11_400 = 11'b10000000000;
parameter ap_const_lv11_1 = 11'b00000000001;
parameter ap_const_lv5_10 = 5'b10000;
parameter ap_const_lv7_1 = 7'b0000001;
parameter ap_const_lv13_6 = 13'b0000000000110;
parameter ap_const_lv7_4 = 7'b0000100;
parameter ap_const_lv5_1 = 5'b00001;
parameter ap_const_lv32_2 = 32'b00000000000000000000000000000010;
parameter ap_const_lv32_13 = 32'b00000000000000000000000000010011;
parameter ap_const_lv15_5000 = 15'b101000000000000;
parameter ap_const_lv32_15 = 32'b00000000000000000000000000010101;
parameter ap_true = 1'b1;
/// ap_CS_fsm assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_CS_fsm
if (ap_rst == 1'b1) begin
ap_CS_fsm <= ap_ST_st0_fsm_0;
end else begin
ap_CS_fsm <= ap_NS_fsm;
end
end
/// ap_reg_ppiten_pp0_it0 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it0
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it0 <= ap_const_logic_0;
end else begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & ~(ap_sig_bdd_73 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it3)) & ~(ap_const_lv1_0 == exitcond2_fu_276_p2))) begin
ap_reg_ppiten_pp0_it0 <= ap_const_logic_0;
end else if (((ap_ST_st1_fsm_1 == ap_CS_fsm) & ~(ap_const_lv1_0 == or_cond_fu_244_p2) & (ap_const_lv1_0 == tmp_3_fu_250_p2))) begin
ap_reg_ppiten_pp0_it0 <= ap_const_logic_1;
end
end
end
/// ap_reg_ppiten_pp0_it1 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it1
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it1 <= ap_const_logic_0;
end else begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & ~(ap_sig_bdd_73 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it3)) & (ap_const_lv1_0 == exitcond2_fu_276_p2))) begin
ap_reg_ppiten_pp0_it1 <= ap_const_logic_1;
end else if ((((ap_ST_st1_fsm_1 == ap_CS_fsm) & ~(ap_const_lv1_0 == or_cond_fu_244_p2) & (ap_const_lv1_0 == tmp_3_fu_250_p2)) | ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & ~(ap_sig_bdd_73 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it3)) & ~(ap_const_lv1_0 == exitcond2_fu_276_p2)))) begin
ap_reg_ppiten_pp0_it1 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp0_it2 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it2
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it2 <= ap_const_logic_0;
end else begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & ~(ap_sig_bdd_73 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it3)))) begin
ap_reg_ppiten_pp0_it2 <= ap_reg_ppiten_pp0_it1;
end else if (((ap_ST_st1_fsm_1 == ap_CS_fsm) & ~(ap_const_lv1_0 == or_cond_fu_244_p2) & (ap_const_lv1_0 == tmp_3_fu_250_p2))) begin
ap_reg_ppiten_pp0_it2 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp0_it3 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it3
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it3 <= ap_const_logic_0;
end else begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & ~(ap_sig_bdd_73 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it3)))) begin
ap_reg_ppiten_pp0_it3 <= ap_reg_ppiten_pp0_it2;
end else if (((ap_ST_st1_fsm_1 == ap_CS_fsm) & ~(ap_const_lv1_0 == or_cond_fu_244_p2) & (ap_const_lv1_0 == tmp_3_fu_250_p2))) begin
ap_reg_ppiten_pp0_it3 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp0_it4 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it4
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it4 <= ap_const_logic_0;
end else begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & ~(ap_sig_bdd_73 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it3)))) begin
ap_reg_ppiten_pp0_it4 <= ap_reg_ppiten_pp0_it3;
end else if (((ap_ST_st1_fsm_1 == ap_CS_fsm) & ~(ap_const_lv1_0 == or_cond_fu_244_p2) & (ap_const_lv1_0 == tmp_3_fu_250_p2))) begin
ap_reg_ppiten_pp0_it4 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp1_it0 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp1_it0
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp1_it0 <= ap_const_logic_0;
end else begin
if (((ap_ST_pp1_stg0_fsm_3 == ap_CS_fsm) & ~(ap_sig_bdd_96 & (ap_const_logic_1 == ap_reg_ppiten_pp1_it3)) & ~(ap_const_lv1_0 == exitcond_fu_459_p2))) begin
ap_reg_ppiten_pp1_it0 <= ap_const_logic_0;
end else if (((ap_ST_st1_fsm_1 == ap_CS_fsm) & ~(ap_const_lv1_0 == or_cond_fu_244_p2) & ~(ap_const_lv1_0 == tmp_3_fu_250_p2))) begin
ap_reg_ppiten_pp1_it0 <= ap_const_logic_1;
end
end
end
/// ap_reg_ppiten_pp1_it1 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp1_it1
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp1_it1 <= ap_const_logic_0;
end else begin
if (((ap_ST_pp1_stg0_fsm_3 == ap_CS_fsm) & ~(ap_sig_bdd_96 & (ap_const_logic_1 == ap_reg_ppiten_pp1_it3)) & (ap_const_lv1_0 == exitcond_fu_459_p2))) begin
ap_reg_ppiten_pp1_it1 <= ap_const_logic_1;
end else if ((((ap_ST_st1_fsm_1 == ap_CS_fsm) & ~(ap_const_lv1_0 == or_cond_fu_244_p2) & ~(ap_const_lv1_0 == tmp_3_fu_250_p2)) | ((ap_ST_pp1_stg0_fsm_3 == ap_CS_fsm) & ~(ap_sig_bdd_96 & (ap_const_logic_1 == ap_reg_ppiten_pp1_it3)) & ~(ap_const_lv1_0 == exitcond_fu_459_p2)))) begin
ap_reg_ppiten_pp1_it1 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp1_it2 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp1_it2
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp1_it2 <= ap_const_logic_0;
end else begin
if (((ap_ST_pp1_stg0_fsm_3 == ap_CS_fsm) & ~(ap_sig_bdd_96 & (ap_const_logic_1 == ap_reg_ppiten_pp1_it3)))) begin
ap_reg_ppiten_pp1_it2 <= ap_reg_ppiten_pp1_it1;
end else if (((ap_ST_st1_fsm_1 == ap_CS_fsm) & ~(ap_const_lv1_0 == or_cond_fu_244_p2) & ~(ap_const_lv1_0 == tmp_3_fu_250_p2))) begin
ap_reg_ppiten_pp1_it2 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp1_it3 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp1_it3
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp1_it3 <= ap_const_logic_0;
end else begin
if (((ap_ST_pp1_stg0_fsm_3 == ap_CS_fsm) & ~(ap_sig_bdd_96 & (ap_const_logic_1 == ap_reg_ppiten_pp1_it3)))) begin
ap_reg_ppiten_pp1_it3 <= ap_reg_ppiten_pp1_it2;
end else if (((ap_ST_st1_fsm_1 == ap_CS_fsm) & ~(ap_const_lv1_0 == or_cond_fu_244_p2) & ~(ap_const_lv1_0 == tmp_3_fu_250_p2))) begin
ap_reg_ppiten_pp1_it3 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp1_it4 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp1_it4
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp1_it4 <= ap_const_logic_0;
end else begin
if (((ap_ST_pp1_stg0_fsm_3 == ap_CS_fsm) & ~(ap_sig_bdd_96 & (ap_const_logic_1 == ap_reg_ppiten_pp1_it3)))) begin
ap_reg_ppiten_pp1_it4 <= ap_reg_ppiten_pp1_it3;
end else if (((ap_ST_st1_fsm_1 == ap_CS_fsm) & ~(ap_const_lv1_0 == or_cond_fu_244_p2) & ~(ap_const_lv1_0 == tmp_3_fu_250_p2))) begin
ap_reg_ppiten_pp1_it4 <= ap_const_logic_0;
end
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & ~(ap_sig_bdd_73 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it3)))) begin
ap_reg_ppstg_exitcond2_reg_672_pp0_it1 <= exitcond2_reg_672;
end
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & ~(ap_sig_bdd_73 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it3)))) begin
ap_reg_ppstg_exitcond2_reg_672_pp0_it2 <= ap_reg_ppstg_exitcond2_reg_672_pp0_it1;
end
if (((ap_ST_pp1_stg0_fsm_3 == ap_CS_fsm) & ~(ap_sig_bdd_96 & (ap_const_logic_1 == ap_reg_ppiten_pp1_it3)))) begin
ap_reg_ppstg_exitcond_reg_736_pp1_it1 <= exitcond_reg_736;
end
if (((ap_ST_pp1_stg0_fsm_3 == ap_CS_fsm) & ~(ap_sig_bdd_96 & (ap_const_logic_1 == ap_reg_ppiten_pp1_it3)))) begin
ap_reg_ppstg_exitcond_reg_736_pp1_it2 <= ap_reg_ppstg_exitcond_reg_736_pp1_it1;
end
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & ~(ap_sig_bdd_73 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it3)))) begin
ap_reg_ppstg_i_1_mid2_reg_694_pp0_it1 <= i_1_mid2_reg_694;
end
if (((ap_ST_pp1_stg0_fsm_3 == ap_CS_fsm) & ~(ap_sig_bdd_96 & (ap_const_logic_1 == ap_reg_ppiten_pp1_it3)))) begin
ap_reg_ppstg_i_mid2_reg_758_pp1_it1 <= i_mid2_reg_758;
end
if (((ap_ST_pp1_stg0_fsm_3 == ap_CS_fsm) & ~(ap_sig_bdd_96 & (ap_const_logic_1 == ap_reg_ppiten_pp1_it3)))) begin
ap_reg_ppstg_indvar1_mid2_reg_745_pp1_it1 <= indvar1_mid2_reg_745;
end
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & ~(ap_sig_bdd_73 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it3)))) begin
ap_reg_ppstg_indvar_mid2_reg_681_pp0_it1 <= indvar_mid2_reg_681;
end
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ~(ap_sig_bdd_73 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it3)))) begin
exitcond2_reg_672 <= (indvar_flatten1_phi_fu_139_p4 == ap_const_lv11_400? 1'b1: 1'b0);
end
if (((ap_ST_pp1_stg0_fsm_3 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & ~(ap_sig_bdd_96 & (ap_const_logic_1 == ap_reg_ppiten_pp1_it3)))) begin
exitcond_reg_736 <= (indvar_flatten_phi_fu_183_p4 == ap_const_lv11_400? 1'b1: 1'b0);
end
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ~(ap_sig_bdd_73 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it3)) & (ap_const_lv1_0 == exitcond2_fu_276_p2))) begin
if (exitcond3_fu_288_p2) begin
i_1_mid2_reg_694 <= tmp_13_dup_fu_310_p2;
end else begin
i_1_mid2_reg_694 <= i_1_phi_fu_150_p4;
end
end
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & ~(ap_sig_bdd_73 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it3)) & (exitcond2_reg_672 == ap_const_lv1_0))) begin
i_1_reg_146 <= i_1_mid2_reg_694;
end else if (((ap_ST_st1_fsm_1 == ap_CS_fsm) & ~(ap_const_lv1_0 == or_cond_fu_244_p2) & (ap_const_lv1_0 == tmp_3_fu_250_p2))) begin
i_1_reg_146 <= ap_const_lv7_0;
end
if (((ap_ST_pp1_stg0_fsm_3 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & ~(ap_sig_bdd_96 & (ap_const_logic_1 == ap_reg_ppiten_pp1_it3)) & (ap_const_lv1_0 == exitcond_fu_459_p2))) begin
if (exitcond1_fu_471_p2) begin
i_mid2_reg_758 <= tmp_6_dup_fu_493_p2;
end else begin
i_mid2_reg_758 <= i_phi_fu_194_p4;
end
end
if (((ap_ST_st1_fsm_1 == ap_CS_fsm) & ~(ap_const_lv1_0 == or_cond_fu_244_p2) & ~(ap_const_lv1_0 == tmp_3_fu_250_p2))) begin
i_reg_190 <= ap_const_lv7_0;
end else if (((ap_ST_pp1_stg0_fsm_3 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & ~(ap_sig_bdd_96 & (ap_const_logic_1 == ap_reg_ppiten_pp1_it3)) & (ap_const_lv1_0 == exitcond_reg_736))) begin
i_reg_190 <= i_mid2_reg_758;
end
if (((ap_ST_pp1_stg0_fsm_3 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & ~(ap_sig_bdd_96 & (ap_const_logic_1 == ap_reg_ppiten_pp1_it3)) & (ap_const_lv1_0 == exitcond_fu_459_p2))) begin
if (exitcond1_fu_471_p2) begin
indvar1_mid2_reg_745 <= ap_const_lv5_0;
end else begin
indvar1_mid2_reg_745 <= indvar1_phi_fu_205_p4;
end
end
if (((ap_ST_st1_fsm_1 == ap_CS_fsm) & ~(ap_const_lv1_0 == or_cond_fu_244_p2) & ~(ap_const_lv1_0 == tmp_3_fu_250_p2))) begin
indvar1_reg_201 <= ap_const_lv5_0;
end else if (((ap_ST_pp1_stg0_fsm_3 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & ~(ap_sig_bdd_96 & (ap_const_logic_1 == ap_reg_ppiten_pp1_it3)) & (ap_const_lv1_0 == exitcond_reg_736))) begin
indvar1_reg_201 <= (indvar1_mid2_reg_745 + ap_const_lv5_1);
end
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & ~(ap_sig_bdd_73 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it3)) & (exitcond2_reg_672 == ap_const_lv1_0))) begin
indvar_flatten1_reg_135 <= indvar_flatten_next1_reg_676;
end else if (((ap_ST_st1_fsm_1 == ap_CS_fsm) & ~(ap_const_lv1_0 == or_cond_fu_244_p2) & (ap_const_lv1_0 == tmp_3_fu_250_p2))) begin
indvar_flatten1_reg_135 <= ap_const_lv11_0;
end
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ~(ap_sig_bdd_73 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it3)))) begin
indvar_flatten_next1_reg_676 <= (indvar_flatten1_phi_fu_139_p4 + ap_const_lv11_1);
end
if (((ap_ST_pp1_stg0_fsm_3 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & ~(ap_sig_bdd_96 & (ap_const_logic_1 == ap_reg_ppiten_pp1_it3)))) begin
indvar_flatten_next_reg_740 <= (indvar_flatten_phi_fu_183_p4 + ap_const_lv11_1);
end
if (((ap_ST_st1_fsm_1 == ap_CS_fsm) & ~(ap_const_lv1_0 == or_cond_fu_244_p2) & ~(ap_const_lv1_0 == tmp_3_fu_250_p2))) begin
indvar_flatten_reg_179 <= ap_const_lv11_0;
end else if (((ap_ST_pp1_stg0_fsm_3 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & ~(ap_sig_bdd_96 & (ap_const_logic_1 == ap_reg_ppiten_pp1_it3)) & (ap_const_lv1_0 == exitcond_reg_736))) begin
indvar_flatten_reg_179 <= indvar_flatten_next_reg_740;
end
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ~(ap_sig_bdd_73 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it3)) & (ap_const_lv1_0 == exitcond2_fu_276_p2))) begin
if (exitcond3_fu_288_p2) begin
indvar_mid2_reg_681 <= ap_const_lv5_0;
end else begin
indvar_mid2_reg_681 <= indvar_phi_fu_161_p4;
end
end
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & ~(ap_sig_bdd_73 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it3)) & (exitcond2_reg_672 == ap_const_lv1_0))) begin
indvar_reg_157 <= (indvar_mid2_reg_681 + ap_const_lv5_1);
end else if (((ap_ST_st1_fsm_1 == ap_CS_fsm) & ~(ap_const_lv1_0 == or_cond_fu_244_p2) & (ap_const_lv1_0 == tmp_3_fu_250_p2))) begin
indvar_reg_157 <= ap_const_lv5_0;
end
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ~(ap_sig_bdd_73 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it3)) & (ap_const_lv1_0 == exitcond2_fu_276_p2))) begin
if (exitcond3_fu_288_p2) begin
j_1_mid2_reg_687 <= ap_const_lv7_0;
end else begin
j_1_mid2_reg_687 <= j_1_phi_fu_172_p4;
end
end
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & ~(ap_sig_bdd_73 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it3)) & (exitcond2_reg_672 == ap_const_lv1_0))) begin
j_1_reg_168 <= (j_1_mid2_reg_687 + ap_const_lv7_4);
end else if (((ap_ST_st1_fsm_1 == ap_CS_fsm) & ~(ap_const_lv1_0 == or_cond_fu_244_p2) & (ap_const_lv1_0 == tmp_3_fu_250_p2))) begin
j_1_reg_168 <= ap_const_lv7_0;
end
if (((ap_ST_pp1_stg0_fsm_3 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & ~(ap_sig_bdd_96 & (ap_const_logic_1 == ap_reg_ppiten_pp1_it3)) & (ap_const_lv1_0 == exitcond_fu_459_p2))) begin
if (exitcond1_fu_471_p2) begin
j_mid2_reg_751 <= ap_const_lv7_0;
end else begin
j_mid2_reg_751 <= j_phi_fu_216_p4;
end
end
if (((ap_ST_st1_fsm_1 == ap_CS_fsm) & ~(ap_const_lv1_0 == or_cond_fu_244_p2) & ~(ap_const_lv1_0 == tmp_3_fu_250_p2))) begin
j_reg_212 <= ap_const_lv7_0;
end else if (((ap_ST_pp1_stg0_fsm_3 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & ~(ap_sig_bdd_96 & (ap_const_logic_1 == ap_reg_ppiten_pp1_it3)) & (ap_const_lv1_0 == exitcond_reg_736))) begin
j_reg_212 <= (j_mid2_reg_751 + ap_const_lv7_4);
end
if ((((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it2) & ~(ap_sig_bdd_73 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it3)) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_672_pp0_it1)) | ((ap_ST_pp1_stg0_fsm_3 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it2) & ~(ap_sig_bdd_96 & (ap_const_logic_1 == ap_reg_ppiten_pp1_it3)) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_736_pp1_it1)))) begin
reg_224 <= d_q0;
end
if ((((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it2) & ~(ap_sig_bdd_73 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it3)) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_672_pp0_it1)) | ((ap_ST_pp1_stg0_fsm_3 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it2) & ~(ap_sig_bdd_96 & (ap_const_logic_1 == ap_reg_ppiten_pp1_it3)) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_736_pp1_it1)))) begin
reg_228 <= d_q1;
end
if (((ap_ST_st1_fsm_1 == ap_CS_fsm) & ~(ap_const_lv1_0 == or_cond_fu_244_p2))) begin
tmp1_cast_reg_662[12] <= tmp1_cast_fu_266_p1[12];
tmp1_cast_reg_662[13] <= tmp1_cast_fu_266_p1[13];
tmp1_cast_reg_662[14] <= tmp1_cast_fu_266_p1[14];
tmp1_cast_reg_662[15] <= tmp1_cast_fu_266_p1[15];
tmp1_cast_reg_662[16] <= tmp1_cast_fu_266_p1[16];
tmp1_cast_reg_662[17] <= tmp1_cast_fu_266_p1[17];
tmp1_cast_reg_662[18] <= tmp1_cast_fu_266_p1[18];
end
if (((ap_ST_st1_fsm_1 == ap_CS_fsm) & ~(ap_const_lv1_0 == or_cond_fu_244_p2) & (ap_const_lv1_0 == tmp_3_fu_250_p2))) begin
tmp3_reg_667[12] <= tmp3_fu_270_p2[12];
tmp3_reg_667[13] <= tmp3_fu_270_p2[13];
tmp3_reg_667[14] <= tmp3_fu_270_p2[14];
tmp3_reg_667[15] <= tmp3_fu_270_p2[15];
tmp3_reg_667[16] <= tmp3_fu_270_p2[16];
tmp3_reg_667[17] <= tmp3_fu_270_p2[17];
tmp3_reg_667[18] <= tmp3_fu_270_p2[18];
tmp3_reg_667[19] <= tmp3_fu_270_p2[19];
end
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it2) & ~(ap_sig_bdd_73 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it3)) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_672_pp0_it1))) begin
tmp_16_reg_721 <= {{tmp10_fu_413_p2[ap_const_lv32_13 : ap_const_lv32_2]}};
end
if (((ap_ST_pp1_stg0_fsm_3 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it2) & ~(ap_sig_bdd_96 & (ap_const_logic_1 == ap_reg_ppiten_pp1_it3)) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_736_pp1_it1))) begin
tmp_7_reg_785 <= {{tmp9_fu_609_p2[ap_const_lv32_15 : ap_const_lv32_2]}};
end
end
/// V_bus_address assign process. ///
always @ (ap_CS_fsm or ap_reg_ppstg_exitcond2_reg_672_pp0_it2 or ap_sig_bdd_73 or ap_reg_ppiten_pp0_it3 or ap_reg_ppstg_exitcond_reg_736_pp1_it2 or ap_sig_bdd_96 or ap_reg_ppiten_pp1_it3 or tmp_17_fu_449_p1 or tmp_9_fu_646_p1)
begin
if (((ap_ST_pp1_stg0_fsm_3 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_736_pp1_it2) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it3) & ~(ap_sig_bdd_96 & (ap_const_logic_1 == ap_reg_ppiten_pp1_it3)))) begin
V_bus_address = tmp_9_fu_646_p1;
end else if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_reg_ppstg_exitcond2_reg_672_pp0_it2 == ap_const_lv1_0) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it3) & ~(ap_sig_bdd_73 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it3)))) begin
V_bus_address = tmp_17_fu_449_p1;
end else begin
V_bus_address = tmp_9_fu_646_p1;
end
end
/// V_bus_dataout assign process. ///
always @ (ap_CS_fsm or ap_reg_ppstg_exitcond2_reg_672_pp0_it2 or ap_sig_bdd_73 or ap_reg_ppiten_pp0_it3 or ap_reg_ppstg_exitcond_reg_736_pp1_it2 or ap_sig_bdd_96 or ap_reg_ppiten_pp1_it3 or tmp_15_fu_444_p1 or tmp_s_fu_641_p1)
begin
if (((ap_ST_pp1_stg0_fsm_3 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_736_pp1_it2) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it3) & ~(ap_sig_bdd_96 & (ap_const_logic_1 == ap_reg_ppiten_pp1_it3)))) begin
V_bus_dataout = tmp_s_fu_641_p1;
end else if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_reg_ppstg_exitcond2_reg_672_pp0_it2 == ap_const_lv1_0) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it3) & ~(ap_sig_bdd_73 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it3)))) begin
V_bus_dataout = tmp_15_fu_444_p1;
end else begin
V_bus_dataout = tmp_s_fu_641_p1;
end
end
/// V_bus_req_din assign process. ///
always @ (ap_CS_fsm or ap_reg_ppstg_exitcond2_reg_672_pp0_it2 or ap_sig_bdd_73 or ap_reg_ppiten_pp0_it3 or ap_reg_ppstg_exitcond_reg_736_pp1_it2 or ap_sig_bdd_96 or ap_reg_ppiten_pp1_it3)
begin
if ((((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_reg_ppstg_exitcond2_reg_672_pp0_it2 == ap_const_lv1_0) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it3) & ~(ap_sig_bdd_73 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it3))) | ((ap_ST_pp1_stg0_fsm_3 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_736_pp1_it2) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it3) & ~(ap_sig_bdd_96 & (ap_const_logic_1 == ap_reg_ppiten_pp1_it3))))) begin
V_bus_req_din = ap_const_logic_1;
end else begin
V_bus_req_din = ap_const_logic_0;
end
end
/// V_bus_req_write assign process. ///
always @ (ap_CS_fsm or ap_reg_ppstg_exitcond2_reg_672_pp0_it2 or ap_sig_bdd_73 or ap_reg_ppiten_pp0_it3 or ap_reg_ppstg_exitcond_reg_736_pp1_it2 or ap_sig_bdd_96 or ap_reg_ppiten_pp1_it3)
begin
if ((((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_reg_ppstg_exitcond2_reg_672_pp0_it2 == ap_const_lv1_0) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it3) & ~(ap_sig_bdd_73 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it3))) | ((ap_ST_pp1_stg0_fsm_3 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_736_pp1_it2) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it3) & ~(ap_sig_bdd_96 & (ap_const_logic_1 == ap_reg_ppiten_pp1_it3))))) begin
V_bus_req_write = ap_const_logic_1;
end else begin
V_bus_req_write = ap_const_logic_0;
end
end
/// ap_NS_fsm assign process. ///
always @ (ap_start or ap_CS_fsm or ap_reg_ppiten_pp0_it0 or ap_reg_ppiten_pp0_it1 or ap_sig_bdd_73 or ap_reg_ppiten_pp0_it3 or ap_reg_ppiten_pp0_it4 or ap_reg_ppiten_pp1_it0 or ap_reg_ppiten_pp1_it1 or ap_sig_bdd_96 or ap_reg_ppiten_pp1_it3 or ap_reg_ppiten_pp1_it4 or or_cond_fu_244_p2 or tmp_3_fu_250_p2 or exitcond2_fu_276_p2 or exitcond_fu_459_p2)
begin
if ((~(ap_const_logic_1 == ap_start) & (ap_ST_st12_fsm_4 == ap_CS_fsm))) begin
ap_NS_fsm = ap_ST_st0_fsm_0;
end else if (((ap_ST_st1_fsm_1 == ap_CS_fsm) & ~(ap_const_lv1_0 == or_cond_fu_244_p2) & (ap_const_lv1_0 == tmp_3_fu_250_p2))) begin
ap_NS_fsm = ap_ST_pp0_stg0_fsm_2;
end else if (((ap_ST_st1_fsm_1 == ap_CS_fsm) & ~(ap_const_lv1_0 == or_cond_fu_244_p2) & ~(ap_const_lv1_0 == tmp_3_fu_250_p2))) begin
ap_NS_fsm = ap_ST_pp1_stg0_fsm_3;
end else if ((((ap_ST_st1_fsm_1 == ap_CS_fsm) & (ap_const_lv1_0 == or_cond_fu_244_p2)) | ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it4) & ~(ap_sig_bdd_73 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it3)) & ~(ap_const_logic_1 == ap_reg_ppiten_pp0_it3)) | ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ~(ap_sig_bdd_73 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it3)) & ~(ap_const_lv1_0 == exitcond2_fu_276_p2) & ~(ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | ((ap_ST_pp1_stg0_fsm_3 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it4) & ~(ap_sig_bdd_96 & (ap_const_logic_1 == ap_reg_ppiten_pp1_it3)) & ~(ap_const_logic_1 == ap_reg_ppiten_pp1_it3)) | ((ap_ST_pp1_stg0_fsm_3 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & ~(ap_sig_bdd_96 & (ap_const_logic_1 == ap_reg_ppiten_pp1_it3)) & ~(ap_const_lv1_0 == exitcond_fu_459_p2) & ~(ap_const_logic_1 == ap_reg_ppiten_pp1_it1)))) begin
ap_NS_fsm = ap_ST_st12_fsm_4;
end else if ((((ap_ST_st0_fsm_0 == ap_CS_fsm) & (ap_const_logic_1 == ap_start)) | ((ap_const_logic_1 == ap_start) & (ap_ST_st12_fsm_4 == ap_CS_fsm)))) begin
ap_NS_fsm = ap_ST_st1_fsm_1;
end else begin
ap_NS_fsm = ap_CS_fsm;
end
end
/// ap_done assign process. ///
always @ (ap_CS_fsm)
begin
if (((ap_ST_st0_fsm_0 == ap_CS_fsm) | (ap_ST_st12_fsm_4 == ap_CS_fsm))) begin
ap_done = ap_const_logic_1;
end else begin
ap_done = ap_const_logic_0;
end
end
/// ap_idle assign process. ///
always @ (ap_CS_fsm)
begin
if ((ap_ST_st0_fsm_0 == ap_CS_fsm)) begin
ap_idle = ap_const_logic_1;
end else begin
ap_idle = ap_const_logic_0;
end
end
/// d_address0 assign process. ///
always @ (ap_CS_fsm or ap_reg_ppiten_pp0_it1 or exitcond2_reg_672 or ap_sig_bdd_73 or ap_reg_ppiten_pp0_it3 or ap_reg_ppiten_pp1_it1 or exitcond_reg_736 or ap_sig_bdd_96 or ap_reg_ppiten_pp1_it3 or tmp_12_fu_346_p1 or tmp_5_fu_529_p1)
begin
if (((ap_ST_pp1_stg0_fsm_3 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & ~(ap_sig_bdd_96 & (ap_const_logic_1 == ap_reg_ppiten_pp1_it3)) & (ap_const_lv1_0 == exitcond_reg_736))) begin
d_address0 = tmp_5_fu_529_p1;
end else if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & ~(ap_sig_bdd_73 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it3)) & (exitcond2_reg_672 == ap_const_lv1_0))) begin
d_address0 = tmp_12_fu_346_p1;
end else begin
d_address0 = tmp_5_fu_529_p1;
end
end
/// d_address1 assign process. ///
always @ (ap_CS_fsm or ap_reg_ppiten_pp0_it1 or exitcond2_reg_672 or ap_sig_bdd_73 or ap_reg_ppiten_pp0_it3 or ap_reg_ppiten_pp1_it1 or exitcond_reg_736 or ap_sig_bdd_96 or ap_reg_ppiten_pp1_it3 or tmp_14_fu_366_p1 or tmp_6_fu_549_p1)
begin
if (((ap_ST_pp1_stg0_fsm_3 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & ~(ap_sig_bdd_96 & (ap_const_logic_1 == ap_reg_ppiten_pp1_it3)) & (ap_const_lv1_0 == exitcond_reg_736))) begin
d_address1 = tmp_6_fu_549_p1;
end else if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & ~(ap_sig_bdd_73 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it3)) & (exitcond2_reg_672 == ap_const_lv1_0))) begin
d_address1 = tmp_14_fu_366_p1;
end else begin
d_address1 = tmp_6_fu_549_p1;
end
end
/// d_ce0 assign process. ///
always @ (ap_CS_fsm or ap_reg_ppiten_pp0_it1 or exitcond2_reg_672 or ap_sig_bdd_73 or ap_reg_ppiten_pp0_it3 or ap_reg_ppiten_pp1_it1 or exitcond_reg_736 or ap_sig_bdd_96 or ap_reg_ppiten_pp1_it3)
begin
if ((((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & ~(ap_sig_bdd_73 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it3)) & (exitcond2_reg_672 == ap_const_lv1_0)) | ((ap_ST_pp1_stg0_fsm_3 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & ~(ap_sig_bdd_96 & (ap_const_logic_1 == ap_reg_ppiten_pp1_it3)) & (ap_const_lv1_0 == exitcond_reg_736)))) begin
d_ce0 = ap_const_logic_1;
end else begin
d_ce0 = ap_const_logic_0;
end
end
/// d_ce1 assign process. ///
always @ (ap_CS_fsm or ap_reg_ppiten_pp0_it1 or exitcond2_reg_672 or ap_sig_bdd_73 or ap_reg_ppiten_pp0_it3 or ap_reg_ppiten_pp1_it1 or exitcond_reg_736 or ap_sig_bdd_96 or ap_reg_ppiten_pp1_it3)
begin
if ((((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & ~(ap_sig_bdd_73 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it3)) & (exitcond2_reg_672 == ap_const_lv1_0)) | ((ap_ST_pp1_stg0_fsm_3 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & ~(ap_sig_bdd_96 & (ap_const_logic_1 == ap_reg_ppiten_pp1_it3)) & (ap_const_lv1_0 == exitcond_reg_736)))) begin
d_ce1 = ap_const_logic_1;
end else begin
d_ce1 = ap_const_logic_0;
end
end
/// i_1_phi_fu_150_p4 assign process. ///
always @ (ap_CS_fsm or i_1_reg_146 or ap_reg_ppiten_pp0_it1 or exitcond2_reg_672 or i_1_mid2_reg_694)
begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (exitcond2_reg_672 == ap_const_lv1_0))) begin
i_1_phi_fu_150_p4 = i_1_mid2_reg_694;
end else begin
i_1_phi_fu_150_p4 = i_1_reg_146;
end
end
/// i_phi_fu_194_p4 assign process. ///
always @ (ap_CS_fsm or i_reg_190 or ap_reg_ppiten_pp1_it1 or exitcond_reg_736 or i_mid2_reg_758)
begin
if (((ap_ST_pp1_stg0_fsm_3 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_const_lv1_0 == exitcond_reg_736))) begin
i_phi_fu_194_p4 = i_mid2_reg_758;
end else begin
i_phi_fu_194_p4 = i_reg_190;
end
end
/// indvar1_phi_fu_205_p4 assign process. ///
always @ (ap_CS_fsm or indvar1_reg_201 or ap_reg_ppiten_pp1_it1 or exitcond_reg_736 or indvar_next1_fu_559_p2)
begin
if (((ap_ST_pp1_stg0_fsm_3 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_const_lv1_0 == exitcond_reg_736))) begin
indvar1_phi_fu_205_p4 = indvar_next1_fu_559_p2;
end else begin
indvar1_phi_fu_205_p4 = indvar1_reg_201;
end
end
/// indvar_flatten1_phi_fu_139_p4 assign process. ///
always @ (ap_CS_fsm or indvar_flatten1_reg_135 or ap_reg_ppiten_pp0_it1 or exitcond2_reg_672 or indvar_flatten_next1_reg_676)
begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (exitcond2_reg_672 == ap_const_lv1_0))) begin
indvar_flatten1_phi_fu_139_p4 = indvar_flatten_next1_reg_676;
end else begin
indvar_flatten1_phi_fu_139_p4 = indvar_flatten1_reg_135;
end
end
/// indvar_flatten_phi_fu_183_p4 assign process. ///
always @ (ap_CS_fsm or indvar_flatten_reg_179 or ap_reg_ppiten_pp1_it1 or exitcond_reg_736 or indvar_flatten_next_reg_740)
begin
if (((ap_ST_pp1_stg0_fsm_3 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_const_lv1_0 == exitcond_reg_736))) begin
indvar_flatten_phi_fu_183_p4 = indvar_flatten_next_reg_740;
end else begin
indvar_flatten_phi_fu_183_p4 = indvar_flatten_reg_179;
end
end
/// indvar_phi_fu_161_p4 assign process. ///
always @ (ap_CS_fsm or indvar_reg_157 or ap_reg_ppiten_pp0_it1 or exitcond2_reg_672 or indvar_next_fu_376_p2)
begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (exitcond2_reg_672 == ap_const_lv1_0))) begin
indvar_phi_fu_161_p4 = indvar_next_fu_376_p2;
end else begin
indvar_phi_fu_161_p4 = indvar_reg_157;
end
end
/// j_1_phi_fu_172_p4 assign process. ///
always @ (ap_CS_fsm or j_1_reg_168 or ap_reg_ppiten_pp0_it1 or exitcond2_reg_672 or tmp_18_fu_371_p2)
begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (exitcond2_reg_672 == ap_const_lv1_0))) begin
j_1_phi_fu_172_p4 = tmp_18_fu_371_p2;
end else begin
j_1_phi_fu_172_p4 = j_1_reg_168;
end
end
/// j_phi_fu_216_p4 assign process. ///
always @ (ap_CS_fsm or j_reg_212 or ap_reg_ppiten_pp1_it1 or exitcond_reg_736 or tmp_10_fu_554_p2)
begin
if (((ap_ST_pp1_stg0_fsm_3 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_const_lv1_0 == exitcond_reg_736))) begin
j_phi_fu_216_p4 = tmp_10_fu_554_p2;
end else begin
j_phi_fu_216_p4 = j_reg_212;
end
end
assign V_bus_rsp_read = ap_const_logic_0;
assign V_bus_size = ap_const_lv32_0;
/// ap_sig_bdd_73 assign process. ///
always @ (V_bus_req_full_n or ap_reg_ppstg_exitcond2_reg_672_pp0_it2)
begin
ap_sig_bdd_73 = ((V_bus_req_full_n == ap_const_logic_0) & (ap_reg_ppstg_exitcond2_reg_672_pp0_it2 == ap_const_lv1_0));
end
/// ap_sig_bdd_96 assign process. ///
always @ (V_bus_req_full_n or ap_reg_ppstg_exitcond_reg_736_pp1_it2)
begin
ap_sig_bdd_96 = ((V_bus_req_full_n == ap_const_logic_0) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_736_pp1_it2));
end
assign counter_cast_fu_256_p1 = {{12{1'b0}}, {counter}};
assign d_addr1_fu_360_p2 = (d_addr3_cast_fu_336_p1 + tmp_16_trn_cast_fu_356_p1);
assign d_addr3_cast_fu_336_p1 = {{1{1'b0}}, {d_addr3_fu_330_p2}};
assign d_addr3_fu_330_p2 = tmp_5_trn2_cast_fu_324_p1 << ap_const_lv13_6;
assign d_addr4_fu_340_p2 = (d_addr3_cast_fu_336_p1 + tmp_14_trn_cast_fu_327_p1);
assign d_addr6_fu_543_p2 = (d_addr8_cast_fu_519_p1 + tmp_9_trn_cast_fu_539_p1);
assign d_addr8_cast_fu_519_p1 = {{1{1'b0}}, {d_addr8_fu_513_p2}};
assign d_addr8_fu_513_p2 = tmp_4_trn7_cast_fu_507_p1 << ap_const_lv13_6;
assign d_addr9_fu_523_p2 = (d_addr8_cast_fu_519_p1 + tmp_7_trn_cast_fu_510_p1);
assign exitcond1_fu_471_p2 = (indvar1_phi_fu_205_p4 == ap_const_lv5_10? 1'b1: 1'b0);
assign exitcond2_fu_276_p2 = (indvar_flatten1_phi_fu_139_p4 == ap_const_lv11_400? 1'b1: 1'b0);
assign exitcond3_fu_288_p2 = (indvar_phi_fu_161_p4 == ap_const_lv5_10? 1'b1: 1'b0);
assign exitcond_fu_459_p2 = (indvar_flatten_phi_fu_183_p4 == ap_const_lv11_400? 1'b1: 1'b0);
assign i_1_cast_fu_381_p1 = {{6{1'b0}}, {ap_reg_ppstg_i_1_mid2_reg_694_pp0_it1}};
assign i_cast_fu_564_p1 = {{6{1'b0}}, {ap_reg_ppstg_i_mid2_reg_758_pp1_it1}};
assign indvar1_cast_fu_586_p1 = {{2{1'b0}}, {ap_reg_ppstg_indvar1_mid2_reg_745_pp1_it1}};
assign indvar_cast_fu_390_p1 = {{2{1'b0}}, {ap_reg_ppstg_indvar_mid2_reg_681_pp0_it1}};
assign indvar_next1_fu_559_p2 = (indvar1_mid2_reg_745 + ap_const_lv5_1);
assign indvar_next_fu_376_p2 = (indvar_mid2_reg_681 + ap_const_lv5_1);
assign or_cond_fu_244_p2 = (tmp_1_fu_232_p2 & tmp_2_fu_238_p2);
assign p_0_fu_436_p3 = {{tmp13_fu_432_p1}, {tmp14_fu_428_p1}};
assign p_s_fu_633_p3 = {{tmp11_fu_629_p1}, {tmp12_fu_625_p1}};
assign tmp10_fu_413_p2 = (tmp7_cast_cast_fu_409_p1 + tmp3_reg_667);
assign tmp11_fu_629_p1 = reg_228;
assign tmp12_fu_625_p1 = reg_224;
assign tmp13_fu_432_p1 = reg_228;
assign tmp14_fu_428_p1 = reg_224;
assign tmp1_cast_fu_266_p1 = {{1{1'b0}}, {tmp1_fu_260_p2}};
assign tmp1_fu_260_p2 = counter_cast_fu_256_p1 << ap_const_lv19_C;
assign tmp2_cast_fu_582_p1 = {{2{1'b0}}, {tmp2_fu_577_p2}};
assign tmp2_fu_577_p2 = (tmp1_cast_reg_662 + tmp4_cast_fu_573_p1);
assign tmp3_fu_270_p2 = (ap_const_lv20_42000 - tmp1_cast_fu_266_p1);
assign tmp4_cast_fu_573_p1 = {{7{1'b0}}, {tmp4_fu_567_p2}};
assign tmp4_fu_567_p2 = i_cast_fu_564_p1 << ap_const_lv13_6;
assign tmp5_fu_599_p2 = (tmp8_cast_fu_595_p1 | ap_const_lv15_5000);
assign tmp6_fu_384_p2 = i_1_cast_fu_381_p1 << ap_const_lv13_6;
assign tmp7_cast_cast_fu_409_p1 = {{7{1'b0}}, {tmp7_fu_403_p2}};
assign tmp7_fu_403_p2 = (tmp6_fu_384_p2 + tmp_cast_fu_399_p1);
assign tmp8_cast_fu_595_p1 = {{8{1'b0}}, {tmp8_fu_589_p2}};
assign tmp8_fu_589_p2 = indvar1_cast_fu_586_p1 << ap_const_lv7_2;
assign tmp9_fu_609_p0 = {{7{tmp5_fu_599_p2[14]}}, {tmp5_fu_599_p2}};
assign tmp9_fu_609_p2 = (tmp9_fu_609_p0 + tmp2_cast_fu_582_p1);
assign tmp_10_fu_554_p2 = (j_mid2_reg_751 + ap_const_lv7_4);
assign tmp_12_fu_346_p1 = {{50{1'b0}}, {d_addr4_fu_340_p2}};
assign tmp_13_dup_fu_310_p2 = (i_1_phi_fu_150_p4 + ap_const_lv7_1);
assign tmp_13_fu_351_p2 = (j_1_mid2_reg_687 | ap_const_lv7_2);
assign tmp_14_fu_366_p1 = {{50{1'b0}}, {d_addr1_fu_360_p2}};
assign tmp_14_trn_cast_fu_327_p1 = {{7{1'b0}}, {j_1_mid2_reg_687}};
assign tmp_15_fu_444_p1 = {{64{1'b0}}, {p_0_fu_436_p3}};
assign tmp_16_trn_cast_fu_356_p1 = {{7{1'b0}}, {tmp_13_fu_351_p2}};
assign tmp_17_fu_449_p1 = {{46{tmp_16_reg_721[17]}}, {tmp_16_reg_721}};
assign tmp_18_fu_371_p2 = (j_1_mid2_reg_687 + ap_const_lv7_4);
assign tmp_1_fu_232_p2 = (counter < ap_const_lv7_43? 1'b1: 1'b0);
assign tmp_2_fu_238_p2 = (counter > ap_const_lv7_2? 1'b1: 1'b0);
assign tmp_3_fu_250_p2 = (tag == ap_const_lv2_0? 1'b1: 1'b0);
assign tmp_4_trn7_cast_fu_507_p1 = {{6{1'b0}}, {i_mid2_reg_758}};
assign tmp_5_fu_529_p1 = {{50{1'b0}}, {d_addr9_fu_523_p2}};
assign tmp_5_trn2_cast_fu_324_p1 = {{6{1'b0}}, {i_1_mid2_reg_694}};
assign tmp_6_dup_fu_493_p2 = (i_phi_fu_194_p4 + ap_const_lv7_1);
assign tmp_6_fu_549_p1 = {{50{1'b0}}, {d_addr6_fu_543_p2}};
assign tmp_7_trn_cast_fu_510_p1 = {{7{1'b0}}, {j_mid2_reg_751}};
assign tmp_8_fu_534_p2 = (j_mid2_reg_751 | ap_const_lv7_2);
assign tmp_9_fu_646_p1 = {{44{tmp_7_reg_785[19]}}, {tmp_7_reg_785}};
assign tmp_9_trn_cast_fu_539_p1 = {{7{1'b0}}, {tmp_8_fu_534_p2}};
assign tmp_cast_fu_399_p1 = {{6{1'b0}}, {tmp_fu_393_p2}};
assign tmp_fu_393_p2 = indvar_cast_fu_390_p1 << ap_const_lv7_2;
assign tmp_s_fu_641_p1 = {{64{1'b0}}, {p_s_fu_633_p3}};
always @ (ap_clk)
begin
tmp1_cast_reg_662[0] <= 1'b0;
tmp1_cast_reg_662[1] <= 1'b0;
tmp1_cast_reg_662[2] <= 1'b0;
tmp1_cast_reg_662[3] <= 1'b0;
tmp1_cast_reg_662[4] <= 1'b0;
tmp1_cast_reg_662[5] <= 1'b0;
tmp1_cast_reg_662[6] <= 1'b0;
tmp1_cast_reg_662[7] <= 1'b0;
tmp1_cast_reg_662[8] <= 1'b0;
tmp1_cast_reg_662[9] <= 1'b0;
tmp1_cast_reg_662[10] <= 1'b0;
tmp1_cast_reg_662[11] <= 1'b0;
tmp1_cast_reg_662[19] <= 1'b0;
end
always @ (ap_clk)
begin
tmp3_reg_667[0] <= 1'b0;
tmp3_reg_667[1] <= 1'b0;
tmp3_reg_667[2] <= 1'b0;
tmp3_reg_667[3] <= 1'b0;
tmp3_reg_667[4] <= 1'b0;
tmp3_reg_667[5] <= 1'b0;
tmp3_reg_667[6] <= 1'b0;
tmp3_reg_667[7] <= 1'b0;
tmp3_reg_667[8] <= 1'b0;
tmp3_reg_667[9] <= 1'b0;
tmp3_reg_667[10] <= 1'b0;
tmp3_reg_667[11] <= 1'b0;
end
endmodule //write_r
|
// -*- Mode: Verilog -*-
// Filename : ahb2wb.v
// Description : this module makes up the interface between the AMBA
// AHB slave and the Wishbone slave
// Author : Thomas Ameseder
// Created On : Mon Mar 01 13:55:59 2004
//
// CVS entries:
// $Author: tame $
// $Date: 2004/10/01 14:11:22 $
// $Revision: 1.2 $
// $State: Exp $
// synopsys translate_off
//`include "mc_defines.v"
// synopsys translate_on
// synopsys translate_off
`timescale 1ns/10ps
// synopsys translate_on
// AHB responses
`define HRESP_OK 2'b00
`define HRESP_ERROR 2'b01
`define HRESP_RETRY 2'b10
`define HRESP_SPLIT 2'b11 // unused
`define HRESP_UNDEF 2'bxx
module ahb2wb
// AMBA interface
(hclk, hresetn, hsel, hready_ba, haddr, hwrite, htrans, hsize, hburst,
hwdata, hmaster, hmastlock, hready, hresp, hrdata, hsplit,
// Wishbone interface
wb_inta_i, wbm_adr_o, wbm_dat_o, wbm_sel_o, wbm_we_o,
wbm_stb_o, wbm_cyc_o, wbm_dat_i, wbm_ack_i, wbm_rty_i, wbm_err_i,
// miscellaneous signals
irq_o
);
parameter HAMAX = 8;
parameter HDMAX = 8;
// AHB state machine
parameter [1:0 ] IDLE = 2'b 00,
SELECTED = 2'b 01,
RESP_1 = 2'b 10,
RESP_2 = 2'b 11;
input hclk,
hresetn;
input hsel,
hready_ba,
hwrite,
hmastlock; // unused
input [HAMAX-1:0] haddr;
input [1:0] htrans; // unused
input [2:0] hsize,
hburst; // unused
input [HDMAX-1:0] hwdata;
input [3:0] hmaster; // unused
input wb_inta_i,
wbm_ack_i,
wbm_rty_i,
wbm_err_i;
input [HDMAX-1:0] wbm_dat_i;
output hready;
output [1:0] hresp;
output [HDMAX-1:0] hrdata;
output [15:0] hsplit;
output wbm_we_o,
wbm_stb_o,
wbm_cyc_o;
output [HAMAX-1:0] wbm_adr_o;
output [HDMAX-1:0] wbm_dat_o;
output [3:0] wbm_sel_o;
output irq_o;
reg wbm_stb_o, wbm_we_o, irq_o;
reg [3:0] wbm_sel_o;
reg hready;
reg [1:0] hresp;
reg [HDMAX-1:0] hrdata;
reg [15:0] hsplit;
reg [HAMAX-1:0] wbm_adr_o;
reg wbm_cyc_o;
reg [HDMAX-1:0] wbm_dat_o;
/**** MODULE BODY ****/
// local signals
wire wb_stb_start_next, wb_stb_end_next, wb_cyc_next;
reg hready_s;
reg [1:0] hresp_s;
reg [HDMAX-1:0] hrdata_s;
reg [15:0] hsplit_s;
reg [1:0] state, next_state;
assign wb_stb_start_next = hready_ba & hsel;
assign wb_stb_end_next = wbm_ack_i | wbm_err_i | wbm_rty_i;
assign wb_cyc_next = hready_ba;
/* model wishbone output signals */
always @ (posedge hclk or negedge hresetn) begin
if (!hresetn) begin
wbm_we_o <= #1 1'b 0;
wbm_sel_o <= #1 4'h 0;
wbm_cyc_o <= #1 0;
wbm_stb_o <= #1 0;
wbm_adr_o <= #1 0;
wbm_dat_o <= #1 0;
end else begin
// wishbone cycle must not be shorter than strobe signal
if (wb_cyc_next)
wbm_cyc_o <= #1 1;
else if (!wb_cyc_next & wbm_stb_o & !wb_stb_end_next)
wbm_cyc_o <= #1 1;
else
wbm_cyc_o <= #1 0;
// strobe has to be high until slave
// acknowledges or signals an error
if (wb_stb_end_next) begin
wbm_stb_o <= #1 0;
wbm_we_o <= #1 1'h 0;
end else if (wb_stb_start_next) begin
wbm_dat_o <= #1 hwdata;
wbm_adr_o <= #1 haddr;
wbm_stb_o <= #1 1;
wbm_we_o <= #1 hwrite;
case (hsize)
0: wbm_sel_o <= #1 4'h 1;
1: wbm_sel_o <= #1 4'h 3;
2: wbm_sel_o <= #1 4'h f;
default: wbm_sel_o <= #1 4'h x;
endcase
end else if (!wbm_cyc_o) begin // propagate address, data
wbm_dat_o <= #1 hwdata; // and write signals
wbm_adr_o <= #1 haddr;
wbm_we_o <= #1 hwrite;
end
end
end // always @ (posedge hclk or negedge hresetn)
/* model ahb response signals */
always @ ( /*`HRESP_ERROR or `HRESP_OK or `HRESP_RETRY
or `HRESP_UNDEF or */ hresp or state or wb_cyc_next
or wb_stb_start_next or wbm_ack_i or wbm_dat_i
or wbm_err_i or wbm_rty_i) begin
// defaults to avoid latches
hsplit_s = 16'b 0; // no split transactions
hready_s = 1;
hresp_s = `HRESP_OK;
hrdata_s = {{HDMAX} {1'b x}};
next_state = IDLE;
case (state)
IDLE: begin
if (wb_stb_start_next) begin
next_state = SELECTED;
hready_s = 0;
end
end
SELECTED: begin
hready_s = 0;
next_state = SELECTED;
if (wbm_err_i) begin
hresp_s = `HRESP_ERROR;
hready_s = 0;
next_state = RESP_1;
end else if (wbm_rty_i) begin
hresp_s = `HRESP_RETRY;
hready_s = 0;
next_state = RESP_1;
end else if (wbm_ack_i) begin
hresp_s = `HRESP_OK;
hready_s = 1;
hrdata_s = wbm_dat_i;
next_state = RESP_2;
end
end
RESP_1: begin // for two-cycle error or retry responses
hready_s = 1;
hresp_s = hresp; // keep previous response
if (wb_cyc_next) // only change state when ahb arbiter is ready to sample
next_state = RESP_2;
else begin
next_state = RESP_1;
hready_s = 0;
end
end
RESP_2: begin
hready_s = 1;
if (wb_cyc_next) begin // only change state when ahb arbiter is ready to sample
hresp_s = `HRESP_OK;
hready_s = 1;
next_state = IDLE;
end else begin
next_state = RESP_2;
hresp_s = hresp; // keep previous response
end
end
default: begin // for simulation purposes
next_state = IDLE;
hready_s = 1'b x;
hresp_s = `HRESP_UNDEF;
hrdata_s = {{HDMAX} {1'b x}};
hsplit_s = 16'b 0;
end
endcase // case(state)
end // always @ (...
// change state, propagate interrupt
always @ (posedge hclk or negedge hresetn) begin
if (!hresetn) begin
state <= #1 IDLE;
hresp <= #1 `HRESP_UNDEF;
hrdata <= #1 {{HDMAX} {1'b x}};
hsplit <= #1 16'b 0;
hready <= #1 1'b 1;
irq_o <= #1 1'b 0;
end else begin
state <= #1 next_state;
hresp <= #1 hresp_s;
hrdata <= #1 hrdata_s;
hsplit <= #1 hsplit_s;
hready <= #1 hready_s;
irq_o <= #1 wb_inta_i;
end
end
endmodule // ahb2wb
|
`define INFERRAM
`define CAN_WISHBONE_IF
`define CAN_MBIST_CTRL_WIDTH 3
//////////////////////////////////////////////////////////////////////
//// ////
//// can_top.v ////
//// ////
//// ////
//// This file is part of the CAN Protocol Controller ////
//// http://www.opencores.org/projects/can/ ////
//// ////
//// ////
//// Author(s): ////
//// Igor Mohor ////
//// [email protected] ////
//// ////
//// ////
//// All additional information is available in the README.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2002, 2003, 2004 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//// The CAN protocol is developed by Robert Bosch GmbH and ////
//// protected by patents. Anybody who wants to implement this ////
//// CAN IP core on silicon has to obtain a CAN protocol license ////
//// from Bosch. ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: can_top.v,v $
// Revision 1.48 2004/10/25 11:44:47 igorm
// Interrupt is always cleared for one clock after the irq register is read.
// This fixes problems when CPU is using IRQs that are edge triggered.
//
// Revision 1.47 2004/02/08 14:53:54 mohor
// Header changed. Address latched to posedge. bus_off_on signal added.
//
// Revision 1.46 2003/10/17 05:55:20 markom
// mbist signals updated according to newest convention
//
// Revision 1.45 2003/09/30 00:55:13 mohor
// Error counters fixed to be compatible with Bosch VHDL reference model.
// Small synchronization changes.
//
// Revision 1.44 2003/09/25 18:55:49 mohor
// Synchronization changed, error counters fixed.
//
// Revision 1.43 2003/08/20 09:57:39 mohor
// Tristate signal tx_o is separated to tx_o and tx_oen_o. Both signals need
// to be joined together on higher level.
//
// Revision 1.42 2003/07/16 15:11:28 mohor
// Fixed according to the linter.
//
// Revision 1.41 2003/07/10 15:32:27 mohor
// Unused signal removed.
//
// Revision 1.40 2003/07/10 01:59:04 tadejm
// Synchronization fixed. In some strange cases it didn't work according to
// the VHDL reference model.
//
// Revision 1.39 2003/07/07 11:21:37 mohor
// Little fixes (to fix warnings).
//
// Revision 1.38 2003/07/03 09:32:20 mohor
// Synchronization changed.
//
// Revision 1.37 2003/06/27 20:56:15 simons
// Virtual silicon ram instances added.
//
// Revision 1.36 2003/06/17 14:30:30 mohor
// "chip select" signal cs_can_i is used only when not using WISHBONE
// interface.
//
// Revision 1.35 2003/06/16 13:57:58 mohor
// tx_point generated one clk earlier. rx_i registered. Data corrected when
// using extended mode.
//
// Revision 1.34 2003/06/13 15:02:24 mohor
// Synchronization is also needed when transmitting a message.
//
// Revision 1.33 2003/06/11 14:21:35 mohor
// When switching to tx, sync stage is overjumped.
//
// Revision 1.32 2003/06/09 11:32:36 mohor
// Ports added for the CAN_BIST.
//
// Revision 1.31 2003/03/26 11:19:46 mohor
// CAN interrupt is active low.
//
// Revision 1.30 2003/03/20 17:01:17 mohor
// unix.
//
// Revision 1.28 2003/03/14 19:36:48 mohor
// can_cs signal used for generation of the cs.
//
// Revision 1.27 2003/03/12 05:56:33 mohor
// Bidirectional port_0_i changed to port_0_io.
// input cs_can changed to cs_can_i.
//
// Revision 1.26 2003/03/12 04:39:40 mohor
// rd_i and wr_i are active high signals. If 8051 is connected, these two signals
// need to be negated one level higher.
//
// Revision 1.25 2003/03/12 04:17:36 mohor
// 8051 interface added (besides WISHBONE interface). Selection is made in
// can_defines.v file.
//
// Revision 1.24 2003/03/10 17:24:40 mohor
// wire declaration added.
//
// Revision 1.23 2003/03/05 15:33:13 mohor
// tx_o is now tristated signal. tx_oen and tx_o combined together.
//
// Revision 1.22 2003/03/05 15:01:56 mohor
// Top level signal names changed.
//
// Revision 1.21 2003/03/01 22:53:33 mohor
// Actel APA ram supported.
//
// Revision 1.20 2003/02/19 15:09:02 mohor
// Incomplete sensitivity list fixed.
//
// Revision 1.19 2003/02/19 15:04:14 mohor
// Typo fixed.
//
// Revision 1.18 2003/02/19 14:44:03 mohor
// CAN core finished. Host interface added. Registers finished.
// Synchronization to the wishbone finished.
//
// Revision 1.17 2003/02/18 00:10:15 mohor
// Most of the registers added. Registers "arbitration lost capture", "error code
// capture" + few more still need to be added.
//
// Revision 1.16 2003/02/14 20:17:01 mohor
// Several registers added. Not finished, yet.
//
// Revision 1.15 2003/02/12 14:25:30 mohor
// abort_tx added.
//
// Revision 1.14 2003/02/11 00:56:06 mohor
// Wishbone interface added.
//
// Revision 1.13 2003/02/09 18:40:29 mohor
// Overload fixed. Hard synchronization also enabled at the last bit of
// interframe.
//
// Revision 1.12 2003/02/09 02:24:33 mohor
// Bosch license warning added. Error counters finished. Overload frames
// still need to be fixed.
//
// Revision 1.11 2003/02/04 14:34:52 mohor
// *** empty log message ***
//
// Revision 1.10 2003/01/31 01:13:38 mohor
// backup.
//
// Revision 1.9 2003/01/15 13:16:48 mohor
// When a frame with "remote request" is received, no data is stored to
// fifo, just the frame information (identifier, ...). Data length that
// is stored is the received data length and not the actual data length
// that is stored to fifo.
//
// Revision 1.8 2003/01/14 17:25:09 mohor
// Addresses corrected to decimal values (previously hex).
//
// Revision 1.7 2003/01/10 17:51:34 mohor
// Temporary version (backup).
//
// Revision 1.6 2003/01/09 21:54:45 mohor
// rx fifo added. Not 100 % verified, yet.
//
// Revision 1.5 2003/01/08 02:10:56 mohor
// Acceptance filter added.
//
// Revision 1.4 2002/12/28 04:13:23 mohor
// Backup version.
//
// Revision 1.3 2002/12/27 00:12:52 mohor
// Header changed, testbench improved to send a frame (crc still missing).
//
// Revision 1.2 2002/12/26 16:00:34 mohor
// Testbench define file added. Clock divider register added.
//
// Revision 1.1.1.1 2002/12/20 16:39:21 mohor
// Initial
//
//
//
// synopsys translate_off
//`include "can_defines.v"
`timescale 1ns/10ps
// synopsys translate_on
module can_top
(
`ifdef CAN_WISHBONE_IF
wb_clk_i,
wb_rst_i,
wb_dat_i,
wb_dat_o,
wb_cyc_i,
wb_stb_i,
wb_we_i,
wb_adr_i,
wb_ack_o,
`else
rst_i,
ale_i,
rd_i,
wr_i,
port_0_io,
cs_can_i,
`endif
clk_i,
rx_i,
tx_o,
bus_off_on,
irq_on,
clkout_o,
// Bist
`ifdef CAN_BIST
,
// debug chain signals
mbist_si_i, // bist scan serial in
mbist_so_o, // bist scan serial out
mbist_ctrl_i, // bist chain shift control
`endif
// port connections for Ram
//64x8
q_dp_64x8,
data_64x8,
wren_64x8,
rden_64x8,
wraddress_64x8,
rdaddress_64x8,
//64x4
q_dp_64x4,
data_64x4,
wren_64x4x1,
wraddress_64x4x1,
rdaddress_64x4x1,
//64x1
q_dp_64x1,
data_64x1
);
parameter Tp = 1;
`ifdef CAN_WISHBONE_IF
input wb_clk_i;
input wb_rst_i;
input [7:0] wb_dat_i;
output [7:0] wb_dat_o;
input wb_cyc_i;
input wb_stb_i;
input wb_we_i;
input [7:0] wb_adr_i;
output wb_ack_o;
reg wb_ack_o;
reg cs_sync1;
reg cs_sync2;
reg cs_sync3;
reg cs_ack1;
reg cs_ack2;
reg cs_ack3;
reg cs_sync_rst1;
reg cs_sync_rst2;
wire cs_can_i;
`else
input rst_i;
input ale_i;
input rd_i;
input wr_i;
inout [7:0] port_0_io;
input cs_can_i;
reg [7:0] addr_latched;
reg wr_i_q;
reg rd_i_q;
`endif
input clk_i;
input rx_i;
output tx_o;
output bus_off_on;
output irq_on;
output clkout_o;
// Bist
`ifdef CAN_BIST
input mbist_si_i; // bist scan serial in
output mbist_so_o; // bist scan serial out
input [`CAN_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i; // bist chain shift control
`endif
// port connections for Ram
//64x8
input [7:0] q_dp_64x8;
output[7:0] data_64x8;
output wren_64x8;
output rden_64x8;
output[5:0] wraddress_64x8;
output[5:0] rdaddress_64x8;
//64x4
input [3:0] q_dp_64x4;
output[3:0] data_64x4;
output wren_64x4x1;
output[5:0] wraddress_64x4x1;
output[5:0] rdaddress_64x4x1;
//64x1
input[0:0] q_dp_64x1;
output[0:0] data_64x1;
//-------------------------------
reg data_out_fifo_selected;
wire [7:0] data_out_fifo;
wire [7:0] data_out_regs;
/* Mode register */
wire reset_mode;
wire listen_only_mode;
wire acceptance_filter_mode;
wire self_test_mode;
/* Command register */
wire release_buffer;
wire tx_request;
wire abort_tx;
wire self_rx_request;
wire single_shot_transmission;
wire tx_state;
wire tx_state_q;
wire overload_request;
wire overload_frame;
/* Arbitration Lost Capture Register */
wire read_arbitration_lost_capture_reg;
/* Error Code Capture Register */
wire read_error_code_capture_reg;
wire [7:0] error_capture_code;
/* Bus Timing 0 register */
wire [5:0] baud_r_presc;
wire [1:0] sync_jump_width;
/* Bus Timing 1 register */
wire [3:0] time_segment1;
wire [2:0] time_segment2;
wire triple_sampling;
/* Error Warning Limit register */
wire [7:0] error_warning_limit;
/* Rx Error Counter register */
wire we_rx_err_cnt;
/* Tx Error Counter register */
wire we_tx_err_cnt;
/* Clock Divider register */
wire extended_mode;
/* This section is for BASIC and EXTENDED mode */
/* Acceptance code register */
wire [7:0] acceptance_code_0;
/* Acceptance mask register */
wire [7:0] acceptance_mask_0;
/* End: This section is for BASIC and EXTENDED mode */
/* This section is for EXTENDED mode */
/* Acceptance code register */
wire [7:0] acceptance_code_1;
wire [7:0] acceptance_code_2;
wire [7:0] acceptance_code_3;
/* Acceptance mask register */
wire [7:0] acceptance_mask_1;
wire [7:0] acceptance_mask_2;
wire [7:0] acceptance_mask_3;
/* End: This section is for EXTENDED mode */
/* Tx data registers. Holding identifier (basic mode), tx frame information (extended mode) and data */
wire [7:0] tx_data_0;
wire [7:0] tx_data_1;
wire [7:0] tx_data_2;
wire [7:0] tx_data_3;
wire [7:0] tx_data_4;
wire [7:0] tx_data_5;
wire [7:0] tx_data_6;
wire [7:0] tx_data_7;
wire [7:0] tx_data_8;
wire [7:0] tx_data_9;
wire [7:0] tx_data_10;
wire [7:0] tx_data_11;
wire [7:0] tx_data_12;
/* End: Tx data registers */
wire cs;
/* Output signals from can_btl module */
wire sample_point;
wire sampled_bit;
wire sampled_bit_q;
wire tx_point;
wire hard_sync;
/* output from can_bsp module */
wire rx_idle;
wire transmitting;
wire transmitter;
wire go_rx_inter;
wire not_first_bit_of_inter;
wire set_reset_mode;
wire node_bus_off;
wire error_status;
wire [7:0] rx_err_cnt;
wire [7:0] tx_err_cnt;
wire rx_err_cnt_dummy; // The MSB is not displayed. It is just used for easier calculation (no counter overflow).
wire tx_err_cnt_dummy; // The MSB is not displayed. It is just used for easier calculation (no counter overflow).
wire transmit_status;
wire receive_status;
wire tx_successful;
wire need_to_tx;
wire overrun;
wire info_empty;
wire set_bus_error_irq;
wire set_arbitration_lost_irq;
wire [4:0] arbitration_lost_capture;
wire node_error_passive;
wire node_error_active;
wire [6:0] rx_message_counter;
wire tx_next;
wire go_overload_frame;
wire go_error_frame;
wire go_tx;
wire send_ack;
wire rst;
wire we;
wire [7:0] addr;
wire [7:0] data_in;
reg [7:0] data_out;
reg rx_sync_tmp;
reg rx_sync;
// port connections for Ram
//64x8
wire[7:0] w_q_dp_64x8;
wire[7:0] w_data_64x8;
wire w_wren_64x8;
wire w_rden_64x8;
wire[5:0] w_wraddress_64x8;
wire[5:0] w_rdaddress_64x8;
//64x4
wire[3:0] w_q_dp_64x4;
wire[3:0] w_data_64x4;
wire w_wren_64x4x1;
wire[5:0] w_wraddress_64x4x1;
wire[5:0] w_rdaddress_64x4x1;
//64x1
wire[0:0] w_q_dp_64x1;
wire[0:0] w_data_64x1;
// port connections for Ram
//64x8
assign w_q_dp_64x8 = q_dp_64x8;
assign data_64x8 = w_data_64x8;
assign wren_64x8 = w_wren_64x8;
assign rden_64x8 = w_rden_64x8;
assign wraddress_64x8 = w_wraddress_64x8;
assign rdaddress_64x8 = w_rdaddress_64x8;
//64x4
assign w_q_dp_64x4 = q_dp_64x4;
assign data_64x4 = w_data_64x4;
assign wren_64x4x1 = w_wren_64x4x1;
assign wraddress_64x4x1 = w_wraddress_64x4x1;
assign rdaddress_64x4x1 = w_rdaddress_64x4x1;
//64x1
assign w_q_dp_64x1 = q_dp_64x1;
assign data_64x1 = w_data_64x1;
/* Connecting can_registers module */
can_registers i_can_registers
(
.clk(clk_i),
.rst(rst),
.cs(cs),
.we(we),
.addr(addr),
.data_in(data_in),
.data_out(data_out_regs),
.irq_n(irq_on),
.sample_point(sample_point),
.transmitting(transmitting),
.set_reset_mode(set_reset_mode),
.node_bus_off(node_bus_off),
.error_status(error_status),
.rx_err_cnt(rx_err_cnt),
.tx_err_cnt(tx_err_cnt),
.transmit_status(transmit_status),
.receive_status(receive_status),
.tx_successful(tx_successful),
.need_to_tx(need_to_tx),
.overrun(overrun),
.info_empty(info_empty),
.set_bus_error_irq(set_bus_error_irq),
.set_arbitration_lost_irq(set_arbitration_lost_irq),
.arbitration_lost_capture(arbitration_lost_capture),
.node_error_passive(node_error_passive),
.node_error_active(node_error_active),
.rx_message_counter(rx_message_counter),
/* Mode register */
.reset_mode(reset_mode),
.listen_only_mode(listen_only_mode),
.acceptance_filter_mode(acceptance_filter_mode),
.self_test_mode(self_test_mode),
/* Command register */
.clear_data_overrun(),
.release_buffer(release_buffer),
.abort_tx(abort_tx),
.tx_request(tx_request),
.self_rx_request(self_rx_request),
.single_shot_transmission(single_shot_transmission),
.tx_state(tx_state),
.tx_state_q(tx_state_q),
.overload_request(overload_request),
.overload_frame(overload_frame),
/* Arbitration Lost Capture Register */
.read_arbitration_lost_capture_reg(read_arbitration_lost_capture_reg),
/* Error Code Capture Register */
.read_error_code_capture_reg(read_error_code_capture_reg),
.error_capture_code(error_capture_code),
/* Bus Timing 0 register */
.baud_r_presc(baud_r_presc),
.sync_jump_width(sync_jump_width),
/* Bus Timing 1 register */
.time_segment1(time_segment1),
.time_segment2(time_segment2),
.triple_sampling(triple_sampling),
/* Error Warning Limit register */
.error_warning_limit(error_warning_limit),
/* Rx Error Counter register */
.we_rx_err_cnt(we_rx_err_cnt),
/* Tx Error Counter register */
.we_tx_err_cnt(we_tx_err_cnt),
/* Clock Divider register */
.extended_mode(extended_mode),
.clkout(clkout_o),
/* This section is for BASIC and EXTENDED mode */
/* Acceptance code register */
.acceptance_code_0(acceptance_code_0),
/* Acceptance mask register */
.acceptance_mask_0(acceptance_mask_0),
/* End: This section is for BASIC and EXTENDED mode */
/* This section is for EXTENDED mode */
/* Acceptance code register */
.acceptance_code_1(acceptance_code_1),
.acceptance_code_2(acceptance_code_2),
.acceptance_code_3(acceptance_code_3),
/* Acceptance mask register */
.acceptance_mask_1(acceptance_mask_1),
.acceptance_mask_2(acceptance_mask_2),
.acceptance_mask_3(acceptance_mask_3),
/* End: This section is for EXTENDED mode */
/* Tx data registers. Holding identifier (basic mode), tx frame information (extended mode) and data */
.tx_data_0(tx_data_0),
.tx_data_1(tx_data_1),
.tx_data_2(tx_data_2),
.tx_data_3(tx_data_3),
.tx_data_4(tx_data_4),
.tx_data_5(tx_data_5),
.tx_data_6(tx_data_6),
.tx_data_7(tx_data_7),
.tx_data_8(tx_data_8),
.tx_data_9(tx_data_9),
.tx_data_10(tx_data_10),
.tx_data_11(tx_data_11),
.tx_data_12(tx_data_12)
/* End: Tx data registers */
);
/* Connecting can_btl module */
can_btl i_can_btl
(
.clk(clk_i),
.rst(rst),
.rx(rx_sync),
.tx(tx_o),
/* Bus Timing 0 register */
.baud_r_presc(baud_r_presc),
.sync_jump_width(sync_jump_width),
/* Bus Timing 1 register */
.time_segment1(time_segment1),
.time_segment2(time_segment2),
.triple_sampling(triple_sampling),
/* Output signals from this module */
.sample_point(sample_point),
.sampled_bit(sampled_bit),
.sampled_bit_q(sampled_bit_q),
.tx_point(tx_point),
.hard_sync(hard_sync),
/* output from can_bsp module */
.rx_idle(rx_idle),
.rx_inter(rx_inter),
.transmitting(transmitting),
.transmitter(transmitter),
.go_rx_inter(go_rx_inter),
.tx_next(tx_next),
.go_overload_frame(go_overload_frame),
.go_error_frame(go_error_frame),
.go_tx(go_tx),
.send_ack(send_ack),
.node_error_passive(node_error_passive)
);
can_bsp i_can_bsp
(
.clk(clk_i),
.rst(rst),
/* From btl module */
.sample_point(sample_point),
.sampled_bit(sampled_bit),
.sampled_bit_q(sampled_bit_q),
.tx_point(tx_point),
.hard_sync(hard_sync),
.addr(addr),
.data_in(data_in),
.data_out(data_out_fifo),
.fifo_selected(data_out_fifo_selected),
/* Mode register */
.reset_mode(reset_mode),
.listen_only_mode(listen_only_mode),
.acceptance_filter_mode(acceptance_filter_mode),
.self_test_mode(self_test_mode),
/* Command register */
.release_buffer(release_buffer),
.tx_request(tx_request),
.abort_tx(abort_tx),
.self_rx_request(self_rx_request),
.single_shot_transmission(single_shot_transmission),
.tx_state(tx_state),
.tx_state_q(tx_state_q),
.overload_request(overload_request),
.overload_frame(overload_frame),
/* Arbitration Lost Capture Register */
.read_arbitration_lost_capture_reg(read_arbitration_lost_capture_reg),
/* Error Code Capture Register */
.read_error_code_capture_reg(read_error_code_capture_reg),
.error_capture_code(error_capture_code),
/* Error Warning Limit register */
.error_warning_limit(error_warning_limit),
/* Rx Error Counter register */
.we_rx_err_cnt(we_rx_err_cnt),
/* Tx Error Counter register */
.we_tx_err_cnt(we_tx_err_cnt),
/* Clock Divider register */
.extended_mode(extended_mode),
/* output from can_bsp module */
.rx_idle(rx_idle),
.transmitting(transmitting),
.transmitter(transmitter),
.go_rx_inter(go_rx_inter),
.not_first_bit_of_inter(not_first_bit_of_inter),
.rx_inter(rx_inter),
.set_reset_mode(set_reset_mode),
.node_bus_off(node_bus_off),
.error_status(error_status),
.rx_err_cnt({rx_err_cnt_dummy, rx_err_cnt[7:0]}), // The MSB is not displayed. It is just used for easier calculation (no counter overflow).
.tx_err_cnt({tx_err_cnt_dummy, tx_err_cnt[7:0]}), // The MSB is not displayed. It is just used for easier calculation (no counter overflow).
.transmit_status(transmit_status),
.receive_status(receive_status),
.tx_successful(tx_successful),
.need_to_tx(need_to_tx),
.overrun(overrun),
.info_empty(info_empty),
.set_bus_error_irq(set_bus_error_irq),
.set_arbitration_lost_irq(set_arbitration_lost_irq),
.arbitration_lost_capture(arbitration_lost_capture),
.node_error_passive(node_error_passive),
.node_error_active(node_error_active),
.rx_message_counter(rx_message_counter),
/* This section is for BASIC and EXTENDED mode */
/* Acceptance code register */
.acceptance_code_0(acceptance_code_0),
/* Acceptance mask register */
.acceptance_mask_0(acceptance_mask_0),
/* End: This section is for BASIC and EXTENDED mode */
/* This section is for EXTENDED mode */
/* Acceptance code register */
.acceptance_code_1(acceptance_code_1),
.acceptance_code_2(acceptance_code_2),
.acceptance_code_3(acceptance_code_3),
/* Acceptance mask register */
.acceptance_mask_1(acceptance_mask_1),
.acceptance_mask_2(acceptance_mask_2),
.acceptance_mask_3(acceptance_mask_3),
/* End: This section is for EXTENDED mode */
/* Tx data registers. Holding identifier (basic mode), tx frame information (extended mode) and data */
.tx_data_0(tx_data_0),
.tx_data_1(tx_data_1),
.tx_data_2(tx_data_2),
.tx_data_3(tx_data_3),
.tx_data_4(tx_data_4),
.tx_data_5(tx_data_5),
.tx_data_6(tx_data_6),
.tx_data_7(tx_data_7),
.tx_data_8(tx_data_8),
.tx_data_9(tx_data_9),
.tx_data_10(tx_data_10),
.tx_data_11(tx_data_11),
.tx_data_12(tx_data_12),
/* End: Tx data registers */
/* Tx signal */
.tx(tx_o),
.tx_next(tx_next),
.bus_off_on(bus_off_on),
.go_overload_frame(go_overload_frame),
.go_error_frame(go_error_frame),
.go_tx(go_tx),
.send_ack(send_ack),
`ifdef CAN_BIST
,
/* BIST signals */
.mbist_si_i(mbist_si_i),
.mbist_so_o(mbist_so_o),
.mbist_ctrl_i(mbist_ctrl_i),
`endif
// port connections for Ram
//64x8
.q_dp_64x8(w_q_dp_64x8),
.data_64x8(w_data_64x8),
.wren_64x8(w_wren_64x8),
.rden_64x8(w_rden_64x8),
.wraddress_64x8(w_wraddress_64x8),
.rdaddress_64x8(w_rdaddress_64x8),
//64x4
.q_dp_64x4(w_q_dp_64x4),
.data_64x4(w_data_64x4),
.wren_64x4x1(w_wren_64x4x1),
.wraddress_64x4x1(w_wraddress_64x4x1),
.rdaddress_64x4x1(w_rdaddress_64x4x1),
//64x1
.q_dp_64x1(w_q_dp_64x1),
.data_64x1(w_data_64x1)
);
// Multiplexing wb_dat_o from registers and rx fifo
always @ (extended_mode or addr or reset_mode)
begin
if (extended_mode & (~reset_mode) & ((addr >= 8'd16) && (addr <= 8'd28)) | (~extended_mode) & ((addr >= 8'd20) && (addr <= 8'd29)))
data_out_fifo_selected = 1'b1;
else
data_out_fifo_selected = 1'b0;
end
always @ (posedge clk_i)
begin
if (cs & (~we))
begin
if (data_out_fifo_selected)
data_out <=#Tp data_out_fifo;
else
data_out <=#Tp data_out_regs;
end
end
always @ (posedge clk_i or posedge rst)
begin
if (rst)
begin
rx_sync_tmp <= 1'b1;
rx_sync <= 1'b1;
end
else
begin
rx_sync_tmp <=#Tp rx_i;
rx_sync <=#Tp rx_sync_tmp;
end
end
`ifdef CAN_WISHBONE_IF
assign cs_can_i = 1'b1;
// Combining wb_cyc_i and wb_stb_i signals to cs signal. Than synchronizing to clk_i clock domain.
always @ (posedge clk_i or posedge rst)
begin
if (rst)
begin
cs_sync1 <= 1'b0;
cs_sync2 <= 1'b0;
cs_sync3 <= 1'b0;
cs_sync_rst1 <= 1'b0;
cs_sync_rst2 <= 1'b0;
end
else
begin
cs_sync1 <=#Tp wb_cyc_i & wb_stb_i & (~cs_sync_rst2) & cs_can_i;
cs_sync2 <=#Tp cs_sync1 & (~cs_sync_rst2);
cs_sync3 <=#Tp cs_sync2 & (~cs_sync_rst2);
cs_sync_rst1 <=#Tp cs_ack3;
cs_sync_rst2 <=#Tp cs_sync_rst1;
end
end
assign cs = cs_sync2 & (~cs_sync3);
always @ (posedge wb_clk_i)
begin
cs_ack1 <=#Tp cs_sync3;
cs_ack2 <=#Tp cs_ack1;
cs_ack3 <=#Tp cs_ack2;
end
// Generating acknowledge signal
always @ (posedge wb_clk_i)
begin
wb_ack_o <=#Tp (cs_ack2 & (~cs_ack3));
end
assign rst = wb_rst_i;
assign we = wb_we_i;
assign addr = wb_adr_i;
assign data_in = wb_dat_i;
assign wb_dat_o = data_out;
`else
// Latching address
always @ (posedge clk_i or posedge rst)
begin
if (rst)
addr_latched <= 8'h0;
else if (ale_i)
addr_latched <=#Tp port_0_io;
end
// Generating delayed wr_i and rd_i signals
always @ (posedge clk_i or posedge rst)
begin
if (rst)
begin
wr_i_q <= 1'b0;
rd_i_q <= 1'b0;
end
else
begin
wr_i_q <=#Tp wr_i;
rd_i_q <=#Tp rd_i;
end
end
assign cs = ((wr_i & (~wr_i_q)) | (rd_i & (~rd_i_q))) & cs_can_i;
assign rst = rst_i;
assign we = wr_i;
assign addr = addr_latched;
assign data_in = port_0_io;
assign port_0_io = (cs_can_i & rd_i)? data_out : 8'hz;
`endif
endmodule
//////////////////////////////////////////////////////////////////////
//// ////
//// can_acf.v ////
//// ////
//// ////
//// This file is part of the CAN Protocol Controller ////
//// http://www.opencores.org/projects/can/ ////
//// ////
//// ////
//// Author(s): ////
//// Igor Mohor ////
//// [email protected] ////
//// ////
//// ////
//// All additional information is available in the README.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2002, 2003, 2004 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//// The CAN protocol is developed by Robert Bosch GmbH and ////
//// protected by patents. Anybody who wants to implement this ////
//// CAN IP core on silicon has to obtain a CAN protocol license ////
//// from Bosch. ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: can_acf.v,v $
// Revision 1.9 2004/05/31 14:46:11 igorm
// Bit acceptance_filter_mode was inverted.
//
// Revision 1.8 2004/02/08 14:16:44 mohor
// Header changed.
//
// Revision 1.7 2003/07/16 13:41:34 mohor
// Fixed according to the linter.
//
// Revision 1.6 2003/02/10 16:02:11 mohor
// CAN is working according to the specification. WB interface and more
// registers (status, IRQ, ...) needs to be added.
//
// Revision 1.5 2003/02/09 18:40:29 mohor
// Overload fixed. Hard synchronization also enabled at the last bit of
// interframe.
//
// Revision 1.4 2003/02/09 02:24:33 mohor
// Bosch license warning added. Error counters finished. Overload frames
// still need to be fixed.
//
// Revision 1.3 2003/01/31 01:13:37 mohor
// backup.
//
// Revision 1.2 2003/01/14 12:19:35 mohor
// rx_fifo is now working.
//
// Revision 1.1 2003/01/08 02:13:15 mohor
// Acceptance filter added.
//
//
//
//
// synopsys translate_off
//`include "can_defines.v"
`timescale 1ns/10ps
// synopsys translate_on
module can_acf
(
clk,
rst,
id,
/* Mode register */
reset_mode,
acceptance_filter_mode,
extended_mode,
acceptance_code_0,
acceptance_code_1,
acceptance_code_2,
acceptance_code_3,
acceptance_mask_0,
acceptance_mask_1,
acceptance_mask_2,
acceptance_mask_3,
go_rx_crc_lim,
go_rx_inter,
go_error_frame,
data0,
data1,
rtr1,
rtr2,
ide,
no_byte0,
no_byte1,
id_ok
);
parameter Tp = 1;
input clk;
input rst;
input [28:0] id;
input reset_mode;
input acceptance_filter_mode;
input extended_mode;
input [7:0] acceptance_code_0;
input [7:0] acceptance_code_1;
input [7:0] acceptance_code_2;
input [7:0] acceptance_code_3;
input [7:0] acceptance_mask_0;
input [7:0] acceptance_mask_1;
input [7:0] acceptance_mask_2;
input [7:0] acceptance_mask_3;
input go_rx_crc_lim;
input go_rx_inter;
input go_error_frame;
input [7:0] data0;
input [7:0] data1;
input rtr1;
input rtr2;
input ide;
input no_byte0;
input no_byte1;
output id_ok;
reg id_ok;
wire match;
wire match_sf_std;
wire match_sf_ext;
wire match_df_std;
wire match_df_ext;
// Working in basic mode. ID match for standard format (11-bit ID).
assign match = ( (id[3] == acceptance_code_0[0] | acceptance_mask_0[0] ) &
(id[4] == acceptance_code_0[1] | acceptance_mask_0[1] ) &
(id[5] == acceptance_code_0[2] | acceptance_mask_0[2] ) &
(id[6] == acceptance_code_0[3] | acceptance_mask_0[3] ) &
(id[7] == acceptance_code_0[4] | acceptance_mask_0[4] ) &
(id[8] == acceptance_code_0[5] | acceptance_mask_0[5] ) &
(id[9] == acceptance_code_0[6] | acceptance_mask_0[6] ) &
(id[10] == acceptance_code_0[7] | acceptance_mask_0[7] )
);
// Working in extended mode. ID match for standard format (11-bit ID). Using single filter.
assign match_sf_std = ( (id[3] == acceptance_code_0[0] | acceptance_mask_0[0] ) &
(id[4] == acceptance_code_0[1] | acceptance_mask_0[1] ) &
(id[5] == acceptance_code_0[2] | acceptance_mask_0[2] ) &
(id[6] == acceptance_code_0[3] | acceptance_mask_0[3] ) &
(id[7] == acceptance_code_0[4] | acceptance_mask_0[4] ) &
(id[8] == acceptance_code_0[5] | acceptance_mask_0[5] ) &
(id[9] == acceptance_code_0[6] | acceptance_mask_0[6] ) &
(id[10] == acceptance_code_0[7] | acceptance_mask_0[7] ) &
(rtr1 == acceptance_code_1[4] | acceptance_mask_1[4] ) &
(id[0] == acceptance_code_1[5] | acceptance_mask_1[5] ) &
(id[1] == acceptance_code_1[6] | acceptance_mask_1[6] ) &
(id[2] == acceptance_code_1[7] | acceptance_mask_1[7] ) &
(data0[0] == acceptance_code_2[0] | acceptance_mask_2[0] | no_byte0) &
(data0[1] == acceptance_code_2[1] | acceptance_mask_2[1] | no_byte0) &
(data0[2] == acceptance_code_2[2] | acceptance_mask_2[2] | no_byte0) &
(data0[3] == acceptance_code_2[3] | acceptance_mask_2[3] | no_byte0) &
(data0[4] == acceptance_code_2[4] | acceptance_mask_2[4] | no_byte0) &
(data0[5] == acceptance_code_2[5] | acceptance_mask_2[5] | no_byte0) &
(data0[6] == acceptance_code_2[6] | acceptance_mask_2[6] | no_byte0) &
(data0[7] == acceptance_code_2[7] | acceptance_mask_2[7] | no_byte0) &
(data1[0] == acceptance_code_3[0] | acceptance_mask_3[0] | no_byte1) &
(data1[1] == acceptance_code_3[1] | acceptance_mask_3[1] | no_byte1) &
(data1[2] == acceptance_code_3[2] | acceptance_mask_3[2] | no_byte1) &
(data1[3] == acceptance_code_3[3] | acceptance_mask_3[3] | no_byte1) &
(data1[4] == acceptance_code_3[4] | acceptance_mask_3[4] | no_byte1) &
(data1[5] == acceptance_code_3[5] | acceptance_mask_3[5] | no_byte1) &
(data1[6] == acceptance_code_3[6] | acceptance_mask_3[6] | no_byte1) &
(data1[7] == acceptance_code_3[7] | acceptance_mask_3[7] | no_byte1)
);
// Working in extended mode. ID match for extended format (29-bit ID). Using single filter.
assign match_sf_ext = ( (id[21] == acceptance_code_0[0] | acceptance_mask_0[0] ) &
(id[22] == acceptance_code_0[1] | acceptance_mask_0[1] ) &
(id[23] == acceptance_code_0[2] | acceptance_mask_0[2] ) &
(id[24] == acceptance_code_0[3] | acceptance_mask_0[3] ) &
(id[25] == acceptance_code_0[4] | acceptance_mask_0[4] ) &
(id[26] == acceptance_code_0[5] | acceptance_mask_0[5] ) &
(id[27] == acceptance_code_0[6] | acceptance_mask_0[6] ) &
(id[28] == acceptance_code_0[7] | acceptance_mask_0[7] ) &
(id[13] == acceptance_code_1[0] | acceptance_mask_1[0] ) &
(id[14] == acceptance_code_1[1] | acceptance_mask_1[1] ) &
(id[15] == acceptance_code_1[2] | acceptance_mask_1[2] ) &
(id[16] == acceptance_code_1[3] | acceptance_mask_1[3] ) &
(id[17] == acceptance_code_1[4] | acceptance_mask_1[4] ) &
(id[18] == acceptance_code_1[5] | acceptance_mask_1[5] ) &
(id[19] == acceptance_code_1[6] | acceptance_mask_1[6] ) &
(id[20] == acceptance_code_1[7] | acceptance_mask_1[7] ) &
(id[5] == acceptance_code_2[0] | acceptance_mask_2[0] ) &
(id[6] == acceptance_code_2[1] | acceptance_mask_2[1] ) &
(id[7] == acceptance_code_2[2] | acceptance_mask_2[2] ) &
(id[8] == acceptance_code_2[3] | acceptance_mask_2[3] ) &
(id[9] == acceptance_code_2[4] | acceptance_mask_2[4] ) &
(id[10] == acceptance_code_2[5] | acceptance_mask_2[5] ) &
(id[11] == acceptance_code_2[6] | acceptance_mask_2[6] ) &
(id[12] == acceptance_code_2[7] | acceptance_mask_2[7] ) &
(rtr2 == acceptance_code_3[2] | acceptance_mask_3[2] ) &
(id[0] == acceptance_code_3[3] | acceptance_mask_3[3] ) &
(id[1] == acceptance_code_3[4] | acceptance_mask_3[4] ) &
(id[2] == acceptance_code_3[5] | acceptance_mask_3[5] ) &
(id[3] == acceptance_code_3[6] | acceptance_mask_3[6] ) &
(id[4] == acceptance_code_3[7] | acceptance_mask_3[7] )
);
// Working in extended mode. ID match for standard format (11-bit ID). Using double filter.
assign match_df_std = (((id[3] == acceptance_code_0[0] | acceptance_mask_0[0] ) &
(id[4] == acceptance_code_0[1] | acceptance_mask_0[1] ) &
(id[5] == acceptance_code_0[2] | acceptance_mask_0[2] ) &
(id[6] == acceptance_code_0[3] | acceptance_mask_0[3] ) &
(id[7] == acceptance_code_0[4] | acceptance_mask_0[4] ) &
(id[8] == acceptance_code_0[5] | acceptance_mask_0[5] ) &
(id[9] == acceptance_code_0[6] | acceptance_mask_0[6] ) &
(id[10] == acceptance_code_0[7] | acceptance_mask_0[7] ) &
(rtr1 == acceptance_code_1[4] | acceptance_mask_1[4] ) &
(id[0] == acceptance_code_1[5] | acceptance_mask_1[5] ) &
(id[1] == acceptance_code_1[6] | acceptance_mask_1[6] ) &
(id[2] == acceptance_code_1[7] | acceptance_mask_1[7] ) &
(data0[0] == acceptance_code_3[0] | acceptance_mask_3[0] | no_byte0) &
(data0[1] == acceptance_code_3[1] | acceptance_mask_3[1] | no_byte0) &
(data0[2] == acceptance_code_3[2] | acceptance_mask_3[2] | no_byte0) &
(data0[3] == acceptance_code_3[3] | acceptance_mask_3[3] | no_byte0) &
(data0[4] == acceptance_code_1[4] | acceptance_mask_1[4] | no_byte0) &
(data0[5] == acceptance_code_1[5] | acceptance_mask_1[5] | no_byte0) &
(data0[6] == acceptance_code_1[6] | acceptance_mask_1[6] | no_byte0) &
(data0[7] == acceptance_code_1[7] | acceptance_mask_1[7] | no_byte0) )
|
((id[3] == acceptance_code_2[0] | acceptance_mask_2[0] ) &
(id[4] == acceptance_code_2[1] | acceptance_mask_2[1] ) &
(id[5] == acceptance_code_2[2] | acceptance_mask_2[2] ) &
(id[6] == acceptance_code_2[3] | acceptance_mask_2[3] ) &
(id[7] == acceptance_code_2[4] | acceptance_mask_2[4] ) &
(id[8] == acceptance_code_2[5] | acceptance_mask_2[5] ) &
(id[9] == acceptance_code_2[6] | acceptance_mask_2[6] ) &
(id[10] == acceptance_code_2[7] | acceptance_mask_2[7] ) &
(rtr1 == acceptance_code_3[4] | acceptance_mask_3[4] ) &
(id[0] == acceptance_code_3[5] | acceptance_mask_3[5] ) &
(id[1] == acceptance_code_3[6] | acceptance_mask_3[6] ) &
(id[2] == acceptance_code_3[7] | acceptance_mask_3[7] ) )
);
// Working in extended mode. ID match for extended format (29-bit ID). Using double filter.
assign match_df_ext = (((id[21] == acceptance_code_0[0] | acceptance_mask_0[0] ) &
(id[22] == acceptance_code_0[1] | acceptance_mask_0[1] ) &
(id[23] == acceptance_code_0[2] | acceptance_mask_0[2] ) &
(id[24] == acceptance_code_0[3] | acceptance_mask_0[3] ) &
(id[25] == acceptance_code_0[4] | acceptance_mask_0[4] ) &
(id[26] == acceptance_code_0[5] | acceptance_mask_0[5] ) &
(id[27] == acceptance_code_0[6] | acceptance_mask_0[6] ) &
(id[28] == acceptance_code_0[7] | acceptance_mask_0[7] ) &
(id[13] == acceptance_code_1[0] | acceptance_mask_1[0] ) &
(id[14] == acceptance_code_1[1] | acceptance_mask_1[1] ) &
(id[15] == acceptance_code_1[2] | acceptance_mask_1[2] ) &
(id[16] == acceptance_code_1[3] | acceptance_mask_1[3] ) &
(id[17] == acceptance_code_1[4] | acceptance_mask_1[4] ) &
(id[18] == acceptance_code_1[5] | acceptance_mask_1[5] ) &
(id[19] == acceptance_code_1[6] | acceptance_mask_1[6] ) &
(id[20] == acceptance_code_1[7] | acceptance_mask_1[7] ) )
|
((id[21] == acceptance_code_2[0] | acceptance_mask_2[0] ) &
(id[22] == acceptance_code_2[1] | acceptance_mask_2[1] ) &
(id[23] == acceptance_code_2[2] | acceptance_mask_2[2] ) &
(id[24] == acceptance_code_2[3] | acceptance_mask_2[3] ) &
(id[25] == acceptance_code_2[4] | acceptance_mask_2[4] ) &
(id[26] == acceptance_code_2[5] | acceptance_mask_2[5] ) &
(id[27] == acceptance_code_2[6] | acceptance_mask_2[6] ) &
(id[28] == acceptance_code_2[7] | acceptance_mask_2[7] ) &
(id[13] == acceptance_code_3[0] | acceptance_mask_3[0] ) &
(id[14] == acceptance_code_3[1] | acceptance_mask_3[1] ) &
(id[15] == acceptance_code_3[2] | acceptance_mask_3[2] ) &
(id[16] == acceptance_code_3[3] | acceptance_mask_3[3] ) &
(id[17] == acceptance_code_3[4] | acceptance_mask_3[4] ) &
(id[18] == acceptance_code_3[5] | acceptance_mask_3[5] ) &
(id[19] == acceptance_code_3[6] | acceptance_mask_3[6] ) &
(id[20] == acceptance_code_3[7] | acceptance_mask_3[7] ) )
);
// ID ok signal generation
always @ (posedge clk or posedge rst)
begin
if (rst)
id_ok <= 1'b0;
else if (go_rx_crc_lim) // sample_point is already included in go_rx_crc_lim
begin
if (extended_mode)
begin
if (~acceptance_filter_mode) // dual filter
begin
if (ide) // extended frame message
id_ok <=#Tp match_df_ext;
else // standard frame message
id_ok <=#Tp match_df_std;
end
else // single filter
begin
if (ide) // extended frame message
id_ok <=#Tp match_sf_ext;
else // standard frame message
id_ok <=#Tp match_sf_std;
end
end
else
id_ok <=#Tp match;
end
else if (reset_mode | go_rx_inter | go_error_frame) // sample_point is already included in go_rx_inter
id_ok <=#Tp 1'b0;
end
endmodule
//////////////////////////////////////////////////////////////////////
//// ////
//// can_bsp.v ////
//// ////
//// ////
//// This file is part of the CAN Protocol Controller ////
//// http://www.opencores.org/projects/can/ ////
//// ////
//// ////
//// Author(s): ////
//// Igor Mohor ////
//// [email protected] ////
//// ////
//// ////
//// All additional information is available in the README.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2002, 2003, 2004 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//// The CAN protocol is developed by Robert Bosch GmbH and ////
//// protected by patents. Anybody who wants to implement this ////
//// CAN IP core on silicon has to obtain a CAN protocol license ////
//// from Bosch. ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: can_bsp.v,v $
// Revision 1.52 2004/11/18 12:39:21 igorm
// Fixes for compatibility after the SW reset.
//
// Revision 1.51 2004/11/15 18:23:21 igorm
// When CAN was reset by setting the reset_mode signal in mode register, it
// was possible that CAN was blocked for a short period of time. Problem
// occured very rarly.
//
// Revision 1.50 2004/10/27 18:51:36 igorm
// Fixed synchronization problem in real hardware when 0xf is used for TSEG1.
//
// Revision 1.49 2004/10/25 06:37:51 igorm
// Arbitration bug fixed.
//
// Revision 1.48 2004/05/12 15:58:41 igorm
// Core improved to pass all tests with the Bosch VHDL Reference system.
//
// Revision 1.47 2004/02/08 14:24:10 mohor
// Error counters changed.
//
// Revision 1.46 2003/10/17 05:55:20 markom
// mbist signals updated according to newest convention
//
// Revision 1.45 2003/09/30 21:14:33 mohor
// Error counters changed.
//
// Revision 1.44 2003/09/30 00:55:12 mohor
// Error counters fixed to be compatible with Bosch VHDL reference model.
// Small synchronization changes.
//
// Revision 1.43 2003/09/25 18:55:49 mohor
// Synchronization changed, error counters fixed.
//
// Revision 1.42 2003/08/29 07:01:14 mohor
// When detecting bus-free, signal bus_free_cnt_en was cleared to zero
// although the last sampled bit was zero instead of one.
//
// Revision 1.41 2003/07/18 15:23:31 tadejm
// Tx and rx length are limited to 8 bytes regardless to the DLC value.
//
// Revision 1.40 2003/07/16 15:10:17 mohor
// Fixed according to the linter.
//
// Revision 1.39 2003/07/16 13:12:46 mohor
// Fixed according to the linter.
//
// Revision 1.38 2003/07/10 01:59:04 tadejm
// Synchronization fixed. In some strange cases it didn't work according to
// the VHDL reference model.
//
// Revision 1.37 2003/07/07 11:21:37 mohor
// Little fixes (to fix warnings).
//
// Revision 1.36 2003/07/03 09:32:20 mohor
// Synchronization changed.
//
// Revision 1.35 2003/06/27 20:56:12 simons
// Virtual silicon ram instances added.
//
// Revision 1.34 2003/06/22 09:43:03 mohor
// synthesi full_case parallel_case fixed.
//
// Revision 1.33 2003/06/21 12:16:30 mohor
// paralel_case and full_case compiler directives added to case statements.
//
// Revision 1.32 2003/06/17 14:28:32 mohor
// Form error was detected when stuff bit occured at the end of crc.
//
// Revision 1.31 2003/06/16 14:31:29 tadejm
// Bit stuffing corrected when stuffing comes at the end of the crc.
//
// Revision 1.30 2003/06/16 13:57:58 mohor
// tx_point generated one clk earlier. rx_i registered. Data corrected when
// using extended mode.
//
// Revision 1.29 2003/06/11 14:21:35 mohor
// When switching to tx, sync stage is overjumped.
//
// Revision 1.28 2003/03/01 22:53:33 mohor
// Actel APA ram supported.
//
// Revision 1.27 2003/02/20 00:26:02 mohor
// When a dominant bit was detected at the third bit of the intermission and
// node had a message to transmit, bit_stuff error could occur. Fixed.
//
// Revision 1.26 2003/02/19 23:21:54 mohor
// When bit error occured while active error flag was transmitted, counter was
// not incremented.
//
// Revision 1.25 2003/02/19 14:44:03 mohor
// CAN core finished. Host interface added. Registers finished.
// Synchronization to the wishbone finished.
//
// Revision 1.24 2003/02/18 00:10:15 mohor
// Most of the registers added. Registers "arbitration lost capture", "error code
// capture" + few more still need to be added.
//
// Revision 1.23 2003/02/14 20:17:01 mohor
// Several registers added. Not finished, yet.
//
// Revision 1.22 2003/02/12 14:23:59 mohor
// abort_tx added. Bit destuff fixed.
//
// Revision 1.21 2003/02/11 00:56:06 mohor
// Wishbone interface added.
//
// Revision 1.20 2003/02/10 16:02:11 mohor
// CAN is working according to the specification. WB interface and more
// registers (status, IRQ, ...) needs to be added.
//
// Revision 1.19 2003/02/09 18:40:29 mohor
// Overload fixed. Hard synchronization also enabled at the last bit of
// interframe.
//
// Revision 1.18 2003/02/09 02:24:33 mohor
// Bosch license warning added. Error counters finished. Overload frames
// still need to be fixed.
//
// Revision 1.17 2003/02/04 17:24:41 mohor
// Backup.
//
// Revision 1.16 2003/02/04 14:34:52 mohor
// *** empty log message ***
//
// Revision 1.15 2003/01/31 01:13:37 mohor
// backup.
//
// Revision 1.14 2003/01/16 13:36:19 mohor
// Form error supported. When receiving messages, last bit of the end-of-frame
// does not generate form error. Receiver goes to the idle mode one bit sooner.
// (CAN specification ver 2.0, part B, page 57).
//
// Revision 1.13 2003/01/15 21:59:45 mohor
// Data is stored to fifo at the end of ack stage.
//
// Revision 1.12 2003/01/15 21:05:11 mohor
// CRC checking fixed (when bitstuff occurs at the end of a CRC sequence).
//
// Revision 1.11 2003/01/15 14:40:23 mohor
// RX state machine fixed to receive "remote request" frames correctly.
// No data bytes are written to fifo when such frames are received.
//
// Revision 1.10 2003/01/15 13:16:47 mohor
// When a frame with "remote request" is received, no data is stored to
// fifo, just the frame information (identifier, ...). Data length that
// is stored is the received data length and not the actual data length
// that is stored to fifo.
//
// Revision 1.9 2003/01/14 12:19:35 mohor
// rx_fifo is now working.
//
// Revision 1.8 2003/01/10 17:51:33 mohor
// Temporary version (backup).
//
// Revision 1.7 2003/01/09 21:54:45 mohor
// rx fifo added. Not 100 % verified, yet.
//
// Revision 1.6 2003/01/09 14:46:58 mohor
// Temporary files (backup).
//
// Revision 1.5 2003/01/08 13:30:31 mohor
// Temp version.
//
// Revision 1.4 2003/01/08 02:10:53 mohor
// Acceptance filter added.
//
// Revision 1.3 2002/12/28 04:13:23 mohor
// Backup version.
//
// Revision 1.2 2002/12/27 00:12:52 mohor
// Header changed, testbench improved to send a frame (crc still missing).
//
// Revision 1.1.1.1 2002/12/20 16:39:21 mohor
// Initial
//
//
//
// synopsys translate_off
//`include "can_defines.v"
`timescale 1ns/10ps
// synopsys translate_on
module can_bsp
(
clk,
rst,
sample_point,
sampled_bit,
sampled_bit_q,
tx_point,
hard_sync,
addr,
data_in,
data_out,
fifo_selected,
/* Mode register */
reset_mode,
listen_only_mode,
acceptance_filter_mode,
self_test_mode,
/* Command register */
release_buffer,
tx_request,
abort_tx,
self_rx_request,
single_shot_transmission,
tx_state,
tx_state_q,
overload_request,
overload_frame,
/* Arbitration Lost Capture Register */
read_arbitration_lost_capture_reg,
/* Error Code Capture Register */
read_error_code_capture_reg,
error_capture_code,
/* Error Warning Limit register */
error_warning_limit,
/* Rx Error Counter register */
we_rx_err_cnt,
/* Tx Error Counter register */
we_tx_err_cnt,
/* Clock Divider register */
extended_mode,
rx_idle,
transmitting,
transmitter,
go_rx_inter,
not_first_bit_of_inter,
rx_inter,
set_reset_mode,
node_bus_off,
error_status,
rx_err_cnt,
tx_err_cnt,
transmit_status,
receive_status,
tx_successful,
need_to_tx,
overrun,
info_empty,
set_bus_error_irq,
set_arbitration_lost_irq,
arbitration_lost_capture,
node_error_passive,
node_error_active,
rx_message_counter,
/* This section is for BASIC and EXTENDED mode */
/* Acceptance code register */
acceptance_code_0,
/* Acceptance mask register */
acceptance_mask_0,
/* End: This section is for BASIC and EXTENDED mode */
/* This section is for EXTENDED mode */
/* Acceptance code register */
acceptance_code_1,
acceptance_code_2,
acceptance_code_3,
/* Acceptance mask register */
acceptance_mask_1,
acceptance_mask_2,
acceptance_mask_3,
/* End: This section is for EXTENDED mode */
/* Tx data registers. Holding identifier (basic mode), tx frame information (extended mode) and data */
tx_data_0,
tx_data_1,
tx_data_2,
tx_data_3,
tx_data_4,
tx_data_5,
tx_data_6,
tx_data_7,
tx_data_8,
tx_data_9,
tx_data_10,
tx_data_11,
tx_data_12,
/* End: Tx data registers */
/* Tx signal */
tx,
tx_next,
bus_off_on,
go_overload_frame,
go_error_frame,
go_tx,
send_ack,
/* Bist */
`ifdef CAN_BIST
,
mbist_si_i,
mbist_so_o,
mbist_ctrl_i,
`endif
// port connections for Ram
//64x8
q_dp_64x8,
data_64x8,
wren_64x8,
rden_64x8,
wraddress_64x8,
rdaddress_64x8,
//64x4
q_dp_64x4,
data_64x4,
wren_64x4x1,
wraddress_64x4x1,
rdaddress_64x4x1,
//64x1
q_dp_64x1,
data_64x1
);
parameter Tp = 1;
input clk;
input rst;
input sample_point;
input sampled_bit;
input sampled_bit_q;
input tx_point;
input hard_sync;
input [7:0] addr;
input [7:0] data_in;
output [7:0] data_out;
input fifo_selected;
input reset_mode;
input listen_only_mode;
input acceptance_filter_mode;
input extended_mode;
input self_test_mode;
/* Command register */
input release_buffer;
input tx_request;
input abort_tx;
input self_rx_request;
input single_shot_transmission;
output tx_state;
output tx_state_q;
input overload_request; // When receiver is busy, it needs to send overload frame. Only 2 overload frames are allowed to
output overload_frame; // be send in a row. This is not implemented, yet, because host can not send an overload request.
/* Arbitration Lost Capture Register */
input read_arbitration_lost_capture_reg;
/* Error Code Capture Register */
input read_error_code_capture_reg;
output [7:0] error_capture_code;
/* Error Warning Limit register */
input [7:0] error_warning_limit;
/* Rx Error Counter register */
input we_rx_err_cnt;
/* Tx Error Counter register */
input we_tx_err_cnt;
output rx_idle;
output transmitting;
output transmitter;
output go_rx_inter;
output not_first_bit_of_inter;
output rx_inter;
output set_reset_mode;
output node_bus_off;
output error_status;
output [8:0] rx_err_cnt;
output [8:0] tx_err_cnt;
output transmit_status;
output receive_status;
output tx_successful;
output need_to_tx;
output overrun;
output info_empty;
output set_bus_error_irq;
output set_arbitration_lost_irq;
output [4:0] arbitration_lost_capture;
output node_error_passive;
output node_error_active;
output [6:0] rx_message_counter;
/* This section is for BASIC and EXTENDED mode */
/* Acceptance code register */
input [7:0] acceptance_code_0;
/* Acceptance mask register */
input [7:0] acceptance_mask_0;
/* End: This section is for BASIC and EXTENDED mode */
/* This section is for EXTENDED mode */
/* Acceptance code register */
input [7:0] acceptance_code_1;
input [7:0] acceptance_code_2;
input [7:0] acceptance_code_3;
/* Acceptance mask register */
input [7:0] acceptance_mask_1;
input [7:0] acceptance_mask_2;
input [7:0] acceptance_mask_3;
/* End: This section is for EXTENDED mode */
/* Tx data registers. Holding identifier (basic mode), tx frame information (extended mode) and data */
input [7:0] tx_data_0;
input [7:0] tx_data_1;
input [7:0] tx_data_2;
input [7:0] tx_data_3;
input [7:0] tx_data_4;
input [7:0] tx_data_5;
input [7:0] tx_data_6;
input [7:0] tx_data_7;
input [7:0] tx_data_8;
input [7:0] tx_data_9;
input [7:0] tx_data_10;
input [7:0] tx_data_11;
input [7:0] tx_data_12;
/* End: Tx data registers */
/* Tx signal */
output tx;
output tx_next;
output bus_off_on;
output go_overload_frame;
output go_error_frame;
output go_tx;
output send_ack;
/* Bist */
`ifdef CAN_BIST
input mbist_si_i;
output mbist_so_o;
input [`CAN_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i; // bist chain shift control
`endif
// port connections for Ram
//64x8
input [7:0] q_dp_64x8;
output[7:0] data_64x8;
output wren_64x8;
output rden_64x8;
output[5:0] wraddress_64x8;
output[5:0] rdaddress_64x8;
//64x4
input [3:0] q_dp_64x4;
output[3:0] data_64x4;
output wren_64x4x1;
output[5:0] wraddress_64x4x1;
output[5:0] rdaddress_64x4x1;
//64x1
input[0:0] q_dp_64x1;
output[0:0] data_64x1;
//----------------------------
reg reset_mode_q;
reg [5:0] bit_cnt;
reg [3:0] data_len;
reg [28:0] id;
reg [2:0] bit_stuff_cnt;
reg [2:0] bit_stuff_cnt_tx;
reg tx_point_q;
reg rx_idle;
reg rx_id1;
reg rx_rtr1;
reg rx_ide;
reg rx_id2;
reg rx_rtr2;
reg rx_r1;
reg rx_r0;
reg rx_dlc;
reg rx_data;
reg rx_crc;
reg rx_crc_lim;
reg rx_ack;
reg rx_ack_lim;
reg rx_eof;
reg rx_inter;
reg go_early_tx_latched;
reg rtr1;
reg ide;
reg rtr2;
reg [14:0] crc_in;
reg [7:0] tmp_data;
reg [7:0] tmp_fifo [0:7];
reg write_data_to_tmp_fifo;
reg [2:0] byte_cnt;
reg bit_stuff_cnt_en;
reg crc_enable;
reg [2:0] eof_cnt;
reg [2:0] passive_cnt;
reg transmitting;
reg error_frame;
reg enable_error_cnt2;
reg [2:0] error_cnt1;
reg [2:0] error_cnt2;
reg [2:0] delayed_dominant_cnt;
reg enable_overload_cnt2;
reg overload_frame;
reg overload_frame_blocked;
reg [1:0] overload_request_cnt;
reg [2:0] overload_cnt1;
reg [2:0] overload_cnt2;
reg tx;
reg crc_err;
reg arbitration_lost;
reg arbitration_lost_q;
reg read_arbitration_lost_capture_reg_q;
reg [4:0] arbitration_lost_capture;
reg arbitration_cnt_en;
reg arbitration_blocked;
reg tx_q;
reg need_to_tx; // When the CAN core has something to transmit and a dominant bit is sampled at the third bit
reg [3:0] data_cnt; // Counting the data bytes that are written to FIFO
reg [2:0] header_cnt; // Counting header length
reg wr_fifo; // Write data and header to 64-byte fifo
reg [7:0] data_for_fifo;// Multiplexed data that is stored to 64-byte fifo
reg [5:0] tx_pointer;
reg tx_bit;
reg tx_state;
reg tx_state_q;
reg transmitter;
reg finish_msg;
reg [8:0] rx_err_cnt;
reg [8:0] tx_err_cnt;
reg [3:0] bus_free_cnt;
reg bus_free_cnt_en;
reg bus_free;
reg waiting_for_bus_free;
reg node_error_passive;
reg node_bus_off;
reg node_bus_off_q;
reg ack_err_latched;
reg bit_err_latched;
reg stuff_err_latched;
reg form_err_latched;
reg rule3_exc1_1;
reg rule3_exc1_2;
reg suspend;
reg susp_cnt_en;
reg [2:0] susp_cnt;
reg error_flag_over_latched;
reg [7:0] error_capture_code;
reg [7:6] error_capture_code_type;
reg error_capture_code_blocked;
reg tx_next;
reg first_compare_bit;
wire [4:0] error_capture_code_segment;
wire error_capture_code_direction;
wire bit_de_stuff;
wire bit_de_stuff_tx;
wire rule5;
/* Rx state machine */
wire go_rx_idle;
wire go_rx_id1;
wire go_rx_rtr1;
wire go_rx_ide;
wire go_rx_id2;
wire go_rx_rtr2;
wire go_rx_r1;
wire go_rx_r0;
wire go_rx_dlc;
wire go_rx_data;
wire go_rx_crc;
wire go_rx_crc_lim;
wire go_rx_ack;
wire go_rx_ack_lim;
wire go_rx_eof;
wire go_rx_inter;
wire last_bit_of_inter;
wire go_crc_enable;
wire rst_crc_enable;
wire bit_de_stuff_set;
wire bit_de_stuff_reset;
wire go_early_tx;
wire [14:0] calculated_crc;
wire [15:0] r_calculated_crc;
wire remote_rq;
wire [3:0] limited_data_len;
wire form_err;
wire error_frame_ended;
wire overload_frame_ended;
wire bit_err;
wire ack_err;
wire stuff_err;
wire id_ok; // If received ID matches ID set in registers
wire no_byte0; // There is no byte 0 (RTR bit set to 1 or DLC field equal to 0). Signal used for acceptance filter.
wire no_byte1; // There is no byte 1 (RTR bit set to 1 or DLC field equal to 1). Signal used for acceptance filter.
wire [2:0] header_len;
wire storing_header;
wire [3:0] limited_data_len_minus1;
wire reset_wr_fifo;
wire err;
wire arbitration_field;
wire [18:0] basic_chain;
wire [63:0] basic_chain_data;
wire [18:0] extended_chain_std;
wire [38:0] extended_chain_ext;
wire [63:0] extended_chain_data_std;
wire [63:0] extended_chain_data_ext;
wire rst_tx_pointer;
wire [7:0] r_tx_data_0;
wire [7:0] r_tx_data_1;
wire [7:0] r_tx_data_2;
wire [7:0] r_tx_data_3;
wire [7:0] r_tx_data_4;
wire [7:0] r_tx_data_5;
wire [7:0] r_tx_data_6;
wire [7:0] r_tx_data_7;
wire [7:0] r_tx_data_8;
wire [7:0] r_tx_data_9;
wire [7:0] r_tx_data_10;
wire [7:0] r_tx_data_11;
wire [7:0] r_tx_data_12;
wire send_ack;
wire bit_err_exc1;
wire bit_err_exc2;
wire bit_err_exc3;
wire bit_err_exc4;
wire bit_err_exc5;
wire bit_err_exc6;
wire error_flag_over;
wire overload_flag_over;
wire [5:0] limited_tx_cnt_ext;
wire [5:0] limited_tx_cnt_std;
// port connections for Ram
//64x8
wire[7:0] w_q_dp_64x8;
wire[7:0] w_data_64x8;
wire w_wren_64x8;
wire w_rden_64x8;
wire[5:0] w_wraddress_64x8;
wire[5:0] w_rdaddress_64x8;
//64x4
wire[3:0] w_q_dp_64x4;
wire[3:0] w_data_64x4;
wire w_wren_64x4x1;
wire[5:0] w_wraddress_64x4x1;
wire[5:0] w_rdaddress_64x4x1;
//64x1
wire[0:0] w_q_dp_64x1;
wire[0:0] w_data_64x1;
// port connections for Ram
//64x8
assign w_q_dp_64x8 = q_dp_64x8;
assign data_64x8 = w_data_64x8;
assign wren_64x8 = w_wren_64x8;
assign rden_64x8 = w_rden_64x8;
assign wraddress_64x8 = w_wraddress_64x8;
assign rdaddress_64x8 = w_rdaddress_64x8;
//64x4
assign w_q_dp_64x4 = q_dp_64x4;
assign data_64x4 = w_data_64x4;
assign wren_64x4x1 = w_wren_64x4x1;
assign wraddress_64x4x1 = w_wraddress_64x4x1;
assign rdaddress_64x4x1 = w_rdaddress_64x4x1;
//64x1
assign w_q_dp_64x1 = q_dp_64x1;
assign data_64x1 = w_data_64x1;
// ----------------------
assign go_rx_idle = sample_point & sampled_bit & last_bit_of_inter | bus_free & (~node_bus_off);
assign go_rx_id1 = sample_point & (~sampled_bit) & (rx_idle | last_bit_of_inter);
assign go_rx_rtr1 = (~bit_de_stuff) & sample_point & rx_id1 & (bit_cnt[3:0] == 4'd10);
assign go_rx_ide = (~bit_de_stuff) & sample_point & rx_rtr1;
assign go_rx_id2 = (~bit_de_stuff) & sample_point & rx_ide & sampled_bit;
assign go_rx_rtr2 = (~bit_de_stuff) & sample_point & rx_id2 & (bit_cnt[4:0] == 5'd17);
assign go_rx_r1 = (~bit_de_stuff) & sample_point & rx_rtr2;
assign go_rx_r0 = (~bit_de_stuff) & sample_point & (rx_ide & (~sampled_bit) | rx_r1);
assign go_rx_dlc = (~bit_de_stuff) & sample_point & rx_r0;
assign go_rx_data = (~bit_de_stuff) & sample_point & rx_dlc & (bit_cnt[1:0] == 2'd3) & (sampled_bit | (|data_len[2:0])) & (~remote_rq);
assign go_rx_crc = (~bit_de_stuff) & sample_point & (rx_dlc & (bit_cnt[1:0] == 2'd3) & ((~sampled_bit) & (~(|data_len[2:0])) | remote_rq) |
rx_data & (bit_cnt[5:0] == ((limited_data_len<<3) - 1'b1))); // overflow works ok at max value (8<<3 = 64 = 0). 0-1 = 6'h3f
assign go_rx_crc_lim = (~bit_de_stuff) & sample_point & rx_crc & (bit_cnt[3:0] == 4'd14);
assign go_rx_ack = (~bit_de_stuff) & sample_point & rx_crc_lim;
assign go_rx_ack_lim = sample_point & rx_ack;
assign go_rx_eof = sample_point & rx_ack_lim;
assign go_rx_inter = ((sample_point & rx_eof & (eof_cnt == 3'd6)) | error_frame_ended | overload_frame_ended) & (~overload_request);
assign go_error_frame = (form_err | stuff_err | bit_err | ack_err | (crc_err & go_rx_eof));
assign error_frame_ended = (error_cnt2 == 3'd7) & tx_point;
assign overload_frame_ended = (overload_cnt2 == 3'd7) & tx_point;
assign go_overload_frame = ( sample_point & ((~sampled_bit) | overload_request) & (rx_eof & (~transmitter) & (eof_cnt == 3'd6) | error_frame_ended | overload_frame_ended) |
sample_point & (~sampled_bit) & rx_inter & (bit_cnt[1:0] < 2'd2) |
sample_point & (~sampled_bit) & ((error_cnt2 == 3'd7) | (overload_cnt2 == 3'd7))
)
& (~overload_frame_blocked)
;
assign go_crc_enable = hard_sync | go_tx;
assign rst_crc_enable = go_rx_crc;
assign bit_de_stuff_set = go_rx_id1 & (~go_error_frame);
assign bit_de_stuff_reset = go_rx_ack | reset_mode | go_error_frame | go_overload_frame;
assign remote_rq = ((~ide) & rtr1) | (ide & rtr2);
assign limited_data_len = (data_len < 4'h8)? data_len : 4'h8;
assign ack_err = rx_ack & sample_point & sampled_bit & tx_state & (~self_test_mode);
assign bit_err = (tx_state | error_frame | overload_frame | rx_ack) & sample_point & (tx != sampled_bit) & (~bit_err_exc1) & (~bit_err_exc2) & (~bit_err_exc3) & (~bit_err_exc4) & (~bit_err_exc5) & (~bit_err_exc6);
assign bit_err_exc1 = tx_state & arbitration_field & tx;
assign bit_err_exc2 = rx_ack & tx;
assign bit_err_exc3 = error_frame & node_error_passive & (error_cnt1 < 3'd7);
assign bit_err_exc4 = (error_frame & (error_cnt1 == 3'd7) & (~enable_error_cnt2)) | (overload_frame & (overload_cnt1 == 3'd7) & (~enable_overload_cnt2));
assign bit_err_exc5 = (error_frame & (error_cnt2 == 3'd7)) | (overload_frame & (overload_cnt2 == 3'd7));
assign bit_err_exc6 = (eof_cnt == 3'd6) & rx_eof & (~transmitter);
assign arbitration_field = rx_id1 | rx_rtr1 | rx_ide | rx_id2 | rx_rtr2;
assign last_bit_of_inter = rx_inter & (bit_cnt[1:0] == 2'd2);
assign not_first_bit_of_inter = rx_inter & (bit_cnt[1:0] != 2'd0);
// Rx idle state
always @ (posedge clk or posedge rst)
begin
if (rst)
rx_idle <= 1'b0;
else if (reset_mode | go_rx_id1 | go_error_frame)
rx_idle <=#Tp 1'b0;
else if (go_rx_idle)
rx_idle <=#Tp 1'b1;
end
// Rx id1 state
always @ (posedge clk or posedge rst)
begin
if (rst)
rx_id1 <= 1'b0;
else if (reset_mode | go_rx_rtr1 | go_error_frame)
rx_id1 <=#Tp 1'b0;
else if (go_rx_id1)
rx_id1 <=#Tp 1'b1;
end
// Rx rtr1 state
always @ (posedge clk or posedge rst)
begin
if (rst)
rx_rtr1 <= 1'b0;
else if (reset_mode | go_rx_ide | go_error_frame)
rx_rtr1 <=#Tp 1'b0;
else if (go_rx_rtr1)
rx_rtr1 <=#Tp 1'b1;
end
// Rx ide state
always @ (posedge clk or posedge rst)
begin
if (rst)
rx_ide <= 1'b0;
else if (reset_mode | go_rx_r0 | go_rx_id2 | go_error_frame)
rx_ide <=#Tp 1'b0;
else if (go_rx_ide)
rx_ide <=#Tp 1'b1;
end
// Rx id2 state
always @ (posedge clk or posedge rst)
begin
if (rst)
rx_id2 <= 1'b0;
else if (reset_mode | go_rx_rtr2 | go_error_frame)
rx_id2 <=#Tp 1'b0;
else if (go_rx_id2)
rx_id2 <=#Tp 1'b1;
end
// Rx rtr2 state
always @ (posedge clk or posedge rst)
begin
if (rst)
rx_rtr2 <= 1'b0;
else if (reset_mode | go_rx_r1 | go_error_frame)
rx_rtr2 <=#Tp 1'b0;
else if (go_rx_rtr2)
rx_rtr2 <=#Tp 1'b1;
end
// Rx r0 state
always @ (posedge clk or posedge rst)
begin
if (rst)
rx_r1 <= 1'b0;
else if (reset_mode | go_rx_r0 | go_error_frame)
rx_r1 <=#Tp 1'b0;
else if (go_rx_r1)
rx_r1 <=#Tp 1'b1;
end
// Rx r0 state
always @ (posedge clk or posedge rst)
begin
if (rst)
rx_r0 <= 1'b0;
else if (reset_mode | go_rx_dlc | go_error_frame)
rx_r0 <=#Tp 1'b0;
else if (go_rx_r0)
rx_r0 <=#Tp 1'b1;
end
// Rx dlc state
always @ (posedge clk or posedge rst)
begin
if (rst)
rx_dlc <= 1'b0;
else if (reset_mode | go_rx_data | go_rx_crc | go_error_frame)
rx_dlc <=#Tp 1'b0;
else if (go_rx_dlc)
rx_dlc <=#Tp 1'b1;
end
// Rx data state
always @ (posedge clk or posedge rst)
begin
if (rst)
rx_data <= 1'b0;
else if (reset_mode | go_rx_crc | go_error_frame)
rx_data <=#Tp 1'b0;
else if (go_rx_data)
rx_data <=#Tp 1'b1;
end
// Rx crc state
always @ (posedge clk or posedge rst)
begin
if (rst)
rx_crc <= 1'b0;
else if (reset_mode | go_rx_crc_lim | go_error_frame)
rx_crc <=#Tp 1'b0;
else if (go_rx_crc)
rx_crc <=#Tp 1'b1;
end
// Rx crc delimiter state
always @ (posedge clk or posedge rst)
begin
if (rst)
rx_crc_lim <= 1'b0;
else if (reset_mode | go_rx_ack | go_error_frame)
rx_crc_lim <=#Tp 1'b0;
else if (go_rx_crc_lim)
rx_crc_lim <=#Tp 1'b1;
end
// Rx ack state
always @ (posedge clk or posedge rst)
begin
if (rst)
rx_ack <= 1'b0;
else if (reset_mode | go_rx_ack_lim | go_error_frame)
rx_ack <=#Tp 1'b0;
else if (go_rx_ack)
rx_ack <=#Tp 1'b1;
end
// Rx ack delimiter state
always @ (posedge clk or posedge rst)
begin
if (rst)
rx_ack_lim <= 1'b0;
else if (reset_mode | go_rx_eof | go_error_frame)
rx_ack_lim <=#Tp 1'b0;
else if (go_rx_ack_lim)
rx_ack_lim <=#Tp 1'b1;
end
// Rx eof state
always @ (posedge clk or posedge rst)
begin
if (rst)
rx_eof <= 1'b0;
else if (reset_mode | go_rx_inter | go_error_frame | go_overload_frame)
rx_eof <=#Tp 1'b0;
else if (go_rx_eof)
rx_eof <=#Tp 1'b1;
end
// Interframe space
always @ (posedge clk or posedge rst)
begin
if (rst)
rx_inter <= 1'b0;
else if (reset_mode | go_rx_idle | go_rx_id1 | go_overload_frame | go_error_frame)
rx_inter <=#Tp 1'b0;
else if (go_rx_inter)
rx_inter <=#Tp 1'b1;
end
// ID register
always @ (posedge clk or posedge rst)
begin
if (rst)
id <= 29'h0;
else if (reset_mode)
id <= 29'h0;
else if (sample_point & (rx_id1 | rx_id2) & (~bit_de_stuff))
id <=#Tp {id[27:0], sampled_bit};
end
// rtr1 bit
always @ (posedge clk or posedge rst)
begin
if (rst)
rtr1 <= 1'b0;
else if (reset_mode)
rtr1 <= 1'b0;
else if (sample_point & rx_rtr1 & (~bit_de_stuff))
rtr1 <=#Tp sampled_bit;
end
// rtr2 bit
always @ (posedge clk or posedge rst)
begin
if (rst)
rtr2 <= 1'b0;
else if (reset_mode)
rtr2 <= 1'b0;
else if (sample_point & rx_rtr2 & (~bit_de_stuff))
rtr2 <=#Tp sampled_bit;
end
// ide bit
always @ (posedge clk or posedge rst)
begin
if (rst)
ide <= 1'b0;
else if (reset_mode)
ide <= 1'b0;
else if (sample_point & rx_ide & (~bit_de_stuff))
ide <=#Tp sampled_bit;
end
// Data length
always @ (posedge clk or posedge rst)
begin
if (rst)
data_len <= 4'b0;
else if (reset_mode)
data_len <= 4'b0;
else if (sample_point & rx_dlc & (~bit_de_stuff))
data_len <=#Tp {data_len[2:0], sampled_bit};
end
// Data
always @ (posedge clk or posedge rst)
begin
if (rst)
tmp_data <= 8'h0;
else if (reset_mode)
tmp_data <= 8'h0;
else if (sample_point & rx_data & (~bit_de_stuff))
tmp_data <=#Tp {tmp_data[6:0], sampled_bit};
end
always @ (posedge clk or posedge rst)
begin
if (rst)
write_data_to_tmp_fifo <= 1'b0;
else if (reset_mode)
write_data_to_tmp_fifo <= 1'b0;
else if (sample_point & rx_data & (~bit_de_stuff) & (&bit_cnt[2:0]))
write_data_to_tmp_fifo <=#Tp 1'b1;
else
write_data_to_tmp_fifo <=#Tp 1'b0;
end
always @ (posedge clk or posedge rst)
begin
if (rst)
byte_cnt <= 3'h0;
else if (reset_mode)
byte_cnt <= 3'h0;
else if (write_data_to_tmp_fifo)
byte_cnt <=#Tp byte_cnt + 1'b1;
else if (sample_point & go_rx_crc_lim)
byte_cnt <=#Tp 3'h0;
end
always @ (posedge clk)
begin
if (write_data_to_tmp_fifo)
tmp_fifo[byte_cnt] <=#Tp tmp_data;
end
// CRC
always @ (posedge clk or posedge rst)
begin
if (rst)
crc_in <= 15'h0;
else if (reset_mode)
crc_in <= 15'h0;
else if (sample_point & rx_crc & (~bit_de_stuff))
crc_in <=#Tp {crc_in[13:0], sampled_bit};
end
// bit_cnt
always @ (posedge clk or posedge rst)
begin
if (rst)
bit_cnt <= 6'd0;
else if (reset_mode)
bit_cnt <= 6'd0;
else if (go_rx_id1 | go_rx_id2 | go_rx_dlc | go_rx_data | go_rx_crc |
go_rx_ack | go_rx_eof | go_rx_inter | go_error_frame | go_overload_frame)
bit_cnt <=#Tp 6'd0;
else if (sample_point & (~bit_de_stuff))
bit_cnt <=#Tp bit_cnt + 1'b1;
end
// eof_cnt
always @ (posedge clk or posedge rst)
begin
if (rst)
eof_cnt <= 3'd0;
else if (reset_mode)
eof_cnt <= 3'd0;
else if (sample_point)
begin
if (go_rx_inter | go_error_frame | go_overload_frame)
eof_cnt <=#Tp 3'd0;
else if (rx_eof)
eof_cnt <=#Tp eof_cnt + 1'b1;
end
end
// Enabling bit de-stuffing
always @ (posedge clk or posedge rst)
begin
if (rst)
bit_stuff_cnt_en <= 1'b0;
else if (reset_mode)
bit_stuff_cnt_en <= 1'b0;
else if (bit_de_stuff_set)
bit_stuff_cnt_en <=#Tp 1'b1;
else if (bit_de_stuff_reset)
bit_stuff_cnt_en <=#Tp 1'b0;
end
// bit_stuff_cnt
always @ (posedge clk or posedge rst)
begin
if (rst)
bit_stuff_cnt <= 3'h1;
else if (reset_mode)
bit_stuff_cnt <= 3'h1;
else if (bit_de_stuff_reset)
bit_stuff_cnt <=#Tp 3'h1;
else if (sample_point & bit_stuff_cnt_en)
begin
if (bit_stuff_cnt == 3'h5)
bit_stuff_cnt <=#Tp 3'h1;
else if (sampled_bit == sampled_bit_q)
bit_stuff_cnt <=#Tp bit_stuff_cnt + 1'b1;
else
bit_stuff_cnt <=#Tp 3'h1;
end
end
// bit_stuff_cnt_tx
always @ (posedge clk or posedge rst)
begin
if (rst)
bit_stuff_cnt_tx <= 3'h1;
else if (reset_mode)
bit_stuff_cnt_tx <= 3'h1;
else if (bit_de_stuff_reset)
bit_stuff_cnt_tx <=#Tp 3'h1;
else if (tx_point_q & bit_stuff_cnt_en)
begin
if (bit_stuff_cnt_tx == 3'h5)
bit_stuff_cnt_tx <=#Tp 3'h1;
else if (tx == tx_q)
bit_stuff_cnt_tx <=#Tp bit_stuff_cnt_tx + 1'b1;
else
bit_stuff_cnt_tx <=#Tp 3'h1;
end
end
assign bit_de_stuff = bit_stuff_cnt == 3'h5;
assign bit_de_stuff_tx = bit_stuff_cnt_tx == 3'h5;
// stuff_err
assign stuff_err = sample_point & bit_stuff_cnt_en & bit_de_stuff & (sampled_bit == sampled_bit_q);
// Generating delayed signals
always @ (posedge clk or posedge rst)
begin
if (rst)
begin
reset_mode_q <=#Tp 1'b0;
node_bus_off_q <=#Tp 1'b0;
end
else
begin
reset_mode_q <=#Tp reset_mode;
node_bus_off_q <=#Tp node_bus_off;
end
end
always @ (posedge clk or posedge rst)
begin
if (rst)
crc_enable <= 1'b0;
else if (reset_mode | rst_crc_enable)
crc_enable <=#Tp 1'b0;
else if (go_crc_enable)
crc_enable <=#Tp 1'b1;
end
// CRC error generation
always @ (posedge clk or posedge rst)
begin
if (rst)
crc_err <= 1'b0;
else if (reset_mode | error_frame_ended)
crc_err <=#Tp 1'b0;
else if (go_rx_ack)
crc_err <=#Tp crc_in != calculated_crc;
end
// Conditions for form error
assign form_err = sample_point & ( ((~bit_de_stuff) & rx_crc_lim & (~sampled_bit) ) |
( rx_ack_lim & (~sampled_bit) ) |
((eof_cnt < 3'd6)& rx_eof & (~sampled_bit) & (~transmitter) ) |
( & rx_eof & (~sampled_bit) & transmitter )
);
always @ (posedge clk or posedge rst)
begin
if (rst)
ack_err_latched <= 1'b0;
else if (reset_mode | error_frame_ended | go_overload_frame)
ack_err_latched <=#Tp 1'b0;
else if (ack_err)
ack_err_latched <=#Tp 1'b1;
end
always @ (posedge clk or posedge rst)
begin
if (rst)
bit_err_latched <= 1'b0;
else if (reset_mode | error_frame_ended | go_overload_frame)
bit_err_latched <=#Tp 1'b0;
else if (bit_err)
bit_err_latched <=#Tp 1'b1;
end
// Rule 5 (Fault confinement).
assign rule5 = bit_err & ( (~node_error_passive) & error_frame & (error_cnt1 < 3'd7)
|
overload_frame & (overload_cnt1 < 3'd7)
);
// Rule 3 exception 1 - first part (Fault confinement).
always @ (posedge clk or posedge rst)
begin
if (rst)
rule3_exc1_1 <= 1'b0;
else if (reset_mode | error_flag_over | rule3_exc1_2)
rule3_exc1_1 <=#Tp 1'b0;
else if (transmitter & node_error_passive & ack_err)
rule3_exc1_1 <=#Tp 1'b1;
end
// Rule 3 exception 1 - second part (Fault confinement).
always @ (posedge clk or posedge rst)
begin
if (rst)
rule3_exc1_2 <= 1'b0;
else if (reset_mode | go_error_frame | rule3_exc1_2)
rule3_exc1_2 <=#Tp 1'b0;
else if (rule3_exc1_1 & (error_cnt1 < 3'd7) & sample_point & (~sampled_bit))
rule3_exc1_2 <=#Tp 1'b1;
end
always @ (posedge clk or posedge rst)
begin
if (rst)
stuff_err_latched <= 1'b0;
else if (reset_mode | error_frame_ended | go_overload_frame)
stuff_err_latched <=#Tp 1'b0;
else if (stuff_err)
stuff_err_latched <=#Tp 1'b1;
end
always @ (posedge clk or posedge rst)
begin
if (rst)
form_err_latched <= 1'b0;
else if (reset_mode | error_frame_ended | go_overload_frame)
form_err_latched <=#Tp 1'b0;
else if (form_err)
form_err_latched <=#Tp 1'b1;
end
// Instantiation of the RX CRC module
can_crc i_can_crc_rx
(
.clk(clk),
.data(sampled_bit),
.enable(crc_enable & sample_point & (~bit_de_stuff)),
.initialize(go_crc_enable),
.crc(calculated_crc)
);
assign no_byte0 = rtr1 | (data_len<4'h1);
assign no_byte1 = rtr1 | (data_len<4'h2);
can_acf i_can_acf
(
.clk(clk),
.rst(rst),
.id(id),
/* Mode register */
.reset_mode(reset_mode),
.acceptance_filter_mode(acceptance_filter_mode),
// Clock Divider register
.extended_mode(extended_mode),
/* This section is for BASIC and EXTENDED mode */
/* Acceptance code register */
.acceptance_code_0(acceptance_code_0),
/* Acceptance mask register */
.acceptance_mask_0(acceptance_mask_0),
/* End: This section is for BASIC and EXTENDED mode */
/* This section is for EXTENDED mode */
/* Acceptance code register */
.acceptance_code_1(acceptance_code_1),
.acceptance_code_2(acceptance_code_2),
.acceptance_code_3(acceptance_code_3),
/* Acceptance mask register */
.acceptance_mask_1(acceptance_mask_1),
.acceptance_mask_2(acceptance_mask_2),
.acceptance_mask_3(acceptance_mask_3),
/* End: This section is for EXTENDED mode */
.go_rx_crc_lim(go_rx_crc_lim),
.go_rx_inter(go_rx_inter),
.go_error_frame(go_error_frame),
.data0(tmp_fifo[0]),
.data1(tmp_fifo[1]),
.rtr1(rtr1),
.rtr2(rtr2),
.ide(ide),
.no_byte0(no_byte0),
.no_byte1(no_byte1),
.id_ok(id_ok)
);
assign header_len[2:0] = extended_mode ? (ide? (3'h5) : (3'h3)) : 3'h2;
assign storing_header = header_cnt < header_len;
assign limited_data_len_minus1[3:0] = remote_rq? 4'hf : ((data_len < 4'h8)? (data_len -1'b1) : 4'h7); // - 1 because counter counts from 0
assign reset_wr_fifo = (data_cnt == (limited_data_len_minus1 + {1'b0, header_len})) | reset_mode;
assign err = form_err | stuff_err | bit_err | ack_err | form_err_latched | stuff_err_latched | bit_err_latched | ack_err_latched | crc_err;
// Write enable signal for 64-byte rx fifo
always @ (posedge clk or posedge rst)
begin
if (rst)
wr_fifo <= 1'b0;
else if (reset_wr_fifo)
wr_fifo <=#Tp 1'b0;
else if (go_rx_inter & id_ok & (~error_frame_ended) & ((~tx_state) | self_rx_request))
wr_fifo <=#Tp 1'b1;
end
// Header counter. Header length depends on the mode of operation and frame format.
always @ (posedge clk or posedge rst)
begin
if (rst)
header_cnt <= 3'h0;
else if (reset_wr_fifo)
header_cnt <=#Tp 3'h0;
else if (wr_fifo & storing_header)
header_cnt <=#Tp header_cnt + 1'h1;
end
// Data counter. Length of the data is limited to 8 bytes.
always @ (posedge clk or posedge rst)
begin
if (rst)
data_cnt <= 4'h0;
else if (reset_wr_fifo)
data_cnt <=#Tp 4'h0;
else if (wr_fifo)
data_cnt <=#Tp data_cnt + 4'h1;
end
// Multiplexing data that is stored to 64-byte fifo depends on the mode of operation and frame format
always @ (extended_mode or ide or data_cnt or header_cnt or header_len or
storing_header or id or rtr1 or rtr2 or data_len or
tmp_fifo[0] or tmp_fifo[2] or tmp_fifo[4] or tmp_fifo[6] or
tmp_fifo[1] or tmp_fifo[3] or tmp_fifo[5] or tmp_fifo[7])
begin
casex ({storing_header, extended_mode, ide, header_cnt}) /* synthesis parallel_case */
6'b1_1_1_000 : data_for_fifo = {1'b1, rtr2, 2'h0, data_len}; // extended mode, extended format header
6'b1_1_1_001 : data_for_fifo = id[28:21]; // extended mode, extended format header
6'b1_1_1_010 : data_for_fifo = id[20:13]; // extended mode, extended format header
6'b1_1_1_011 : data_for_fifo = id[12:5]; // extended mode, extended format header
6'b1_1_1_100 : data_for_fifo = {id[4:0], 3'h0}; // extended mode, extended format header
6'b1_1_0_000 : data_for_fifo = {1'b0, rtr1, 2'h0, data_len}; // extended mode, standard format header
6'b1_1_0_001 : data_for_fifo = id[10:3]; // extended mode, standard format header
6'b1_1_0_010 : data_for_fifo = {id[2:0], rtr1, 4'h0}; // extended mode, standard format header
6'b1_0_x_000 : data_for_fifo = id[10:3]; // normal mode header
6'b1_0_x_001 : data_for_fifo = {id[2:0], rtr1, data_len}; // normal mode header
default : data_for_fifo = tmp_fifo[data_cnt - {1'b0, header_len}]; // data
endcase
end
// Instantiation of the RX fifo module
can_fifo i_can_fifo
(
.clk(clk),
.rst(rst),
.wr(wr_fifo),
.data_in(data_for_fifo),
.addr(addr[5:0]),
.data_out(data_out),
.fifo_selected(fifo_selected),
.reset_mode(reset_mode),
.release_buffer(release_buffer),
.extended_mode(extended_mode),
.overrun(overrun),
.info_empty(info_empty),
.info_cnt(rx_message_counter),
`ifdef CAN_BIST
,
.mbist_si_i(mbist_si_i),
.mbist_so_o(mbist_so_o),
.mbist_ctrl_i(mbist_ctrl_i),
`endif
// port connections for Ram
//64x8
.q_dp_64x8(w_q_dp_64x8),
.data_64x8(w_data_64x8),
.wren_64x8(w_wren_64x8),
.rden_64x8(w_rden_64x8),
.wraddress_64x8(w_wraddress_64x8),
.rdaddress_64x8(w_rdaddress_64x8),
//64x4
.q_dp_64x4(w_q_dp_64x4),
.data_64x4(w_data_64x4),
.wren_64x4x1(w_wren_64x4x1),
.wraddress_64x4x1(w_wraddress_64x4x1),
.rdaddress_64x4x1(w_rdaddress_64x4x1),
//64x1
.q_dp_64x1(w_q_dp_64x1),
.data_64x1(w_data_64x1)
);
// Transmitting error frame.
always @ (posedge clk or posedge rst)
begin
if (rst)
error_frame <= 1'b0;
else if (reset_mode | error_frame_ended | go_overload_frame)
error_frame <=#Tp 1'b0;
else if (go_error_frame)
error_frame <=#Tp 1'b1;
end
always @ (posedge clk or posedge rst)
begin
if (rst)
error_cnt1 <= 3'd0;
else if (reset_mode | error_frame_ended | go_error_frame | go_overload_frame)
error_cnt1 <=#Tp 3'd0;
else if (error_frame & tx_point & (error_cnt1 < 3'd7))
error_cnt1 <=#Tp error_cnt1 + 1'b1;
end
assign error_flag_over = ((~node_error_passive) & sample_point & (error_cnt1 == 3'd7) | node_error_passive & sample_point & (passive_cnt == 3'h6)) & (~enable_error_cnt2);
always @ (posedge clk or posedge rst)
begin
if (rst)
error_flag_over_latched <= 1'b0;
else if (reset_mode | error_frame_ended | go_error_frame | go_overload_frame)
error_flag_over_latched <=#Tp 1'b0;
else if (error_flag_over)
error_flag_over_latched <=#Tp 1'b1;
end
always @ (posedge clk or posedge rst)
begin
if (rst)
enable_error_cnt2 <= 1'b0;
else if (reset_mode | error_frame_ended | go_error_frame | go_overload_frame)
enable_error_cnt2 <=#Tp 1'b0;
else if (error_frame & (error_flag_over & sampled_bit))
enable_error_cnt2 <=#Tp 1'b1;
end
always @ (posedge clk or posedge rst)
begin
if (rst)
error_cnt2 <= 3'd0;
else if (reset_mode | error_frame_ended | go_error_frame | go_overload_frame)
error_cnt2 <=#Tp 3'd0;
else if (enable_error_cnt2 & tx_point)
error_cnt2 <=#Tp error_cnt2 + 1'b1;
end
always @ (posedge clk or posedge rst)
begin
if (rst)
delayed_dominant_cnt <= 3'h0;
else if (reset_mode | enable_error_cnt2 | go_error_frame | enable_overload_cnt2 | go_overload_frame)
delayed_dominant_cnt <=#Tp 3'h0;
else if (sample_point & (~sampled_bit) & ((error_cnt1 == 3'd7) | (overload_cnt1 == 3'd7)))
delayed_dominant_cnt <=#Tp delayed_dominant_cnt + 1'b1;
end
// passive_cnt
always @ (posedge clk or posedge rst)
begin
if (rst)
passive_cnt <= 3'h1;
else if (reset_mode | error_frame_ended | go_error_frame | go_overload_frame | first_compare_bit)
passive_cnt <=#Tp 3'h1;
else if (sample_point & (passive_cnt < 3'h6))
begin
if (error_frame & (~enable_error_cnt2) & (sampled_bit == sampled_bit_q))
passive_cnt <=#Tp passive_cnt + 1'b1;
else
passive_cnt <=#Tp 3'h1;
end
end
// When comparing 6 equal bits, first is always equal
always @ (posedge clk or posedge rst)
begin
if (rst)
first_compare_bit <= 1'b0;
else if (go_error_frame)
first_compare_bit <=#Tp 1'b1;
else if (sample_point)
first_compare_bit <= 1'b0;
end
// Transmitting overload frame.
always @ (posedge clk or posedge rst)
begin
if (rst)
overload_frame <= 1'b0;
else if (reset_mode | overload_frame_ended | go_error_frame)
overload_frame <=#Tp 1'b0;
else if (go_overload_frame)
overload_frame <=#Tp 1'b1;
end
always @ (posedge clk or posedge rst)
begin
if (rst)
overload_cnt1 <= 3'd0;
else if (reset_mode | overload_frame_ended | go_error_frame | go_overload_frame)
overload_cnt1 <=#Tp 3'd0;
else if (overload_frame & tx_point & (overload_cnt1 < 3'd7))
overload_cnt1 <=#Tp overload_cnt1 + 1'b1;
end
assign overload_flag_over = sample_point & (overload_cnt1 == 3'd7) & (~enable_overload_cnt2);
always @ (posedge clk or posedge rst)
begin
if (rst)
enable_overload_cnt2 <= 1'b0;
else if (reset_mode | overload_frame_ended | go_error_frame | go_overload_frame)
enable_overload_cnt2 <=#Tp 1'b0;
else if (overload_frame & (overload_flag_over & sampled_bit))
enable_overload_cnt2 <=#Tp 1'b1;
end
always @ (posedge clk or posedge rst)
begin
if (rst)
overload_cnt2 <= 3'd0;
else if (reset_mode | overload_frame_ended | go_error_frame | go_overload_frame)
overload_cnt2 <=#Tp 3'd0;
else if (enable_overload_cnt2 & tx_point)
overload_cnt2 <=#Tp overload_cnt2 + 1'b1;
end
always @ (posedge clk or posedge rst)
begin
if (rst)
overload_request_cnt <= 2'b0;
else if (reset_mode | go_error_frame | go_rx_id1)
overload_request_cnt <=#Tp 2'b0;
else if (overload_request & overload_frame)
overload_request_cnt <=#Tp overload_request_cnt + 1'b1;
end
always @ (posedge clk or posedge rst)
begin
if (rst)
overload_frame_blocked <= 1'b0;
else if (reset_mode | go_error_frame | go_rx_id1)
overload_frame_blocked <=#Tp 1'b0;
else if (overload_request & overload_frame & overload_request_cnt == 2'h2) // This is a second sequential overload_request
overload_frame_blocked <=#Tp 1'b1;
end
assign send_ack = (~tx_state) & rx_ack & (~err) & (~listen_only_mode);
always @ (reset_mode or node_bus_off or tx_state or go_tx or bit_de_stuff_tx or tx_bit or tx_q or
send_ack or go_overload_frame or overload_frame or overload_cnt1 or
go_error_frame or error_frame or error_cnt1 or node_error_passive)
begin
if (reset_mode | node_bus_off) // Reset or node_bus_off
tx_next = 1'b1;
else
begin
if (go_error_frame | error_frame) // Transmitting error frame
begin
if (error_cnt1 < 3'd6)
begin
if (node_error_passive)
tx_next = 1'b1;
else
tx_next = 1'b0;
end
else
tx_next = 1'b1;
end
else if (go_overload_frame | overload_frame) // Transmitting overload frame
begin
if (overload_cnt1 < 3'd6)
tx_next = 1'b0;
else
tx_next = 1'b1;
end
else if (go_tx | tx_state) // Transmitting message
tx_next = ((~bit_de_stuff_tx) & tx_bit) | (bit_de_stuff_tx & (~tx_q));
else if (send_ack) // Acknowledge
tx_next = 1'b0;
else
tx_next = 1'b1;
end
end
always @ (posedge clk or posedge rst)
begin
if (rst)
tx <= 1'b1;
else if (reset_mode)
tx <= 1'b1;
else if (tx_point)
tx <=#Tp tx_next;
end
always @ (posedge clk or posedge rst)
begin
if (rst)
tx_q <=#Tp 1'b0;
else if (reset_mode)
tx_q <=#Tp 1'b0;
else if (tx_point)
tx_q <=#Tp tx & (~go_early_tx_latched);
end
/* Delayed tx point */
always @ (posedge clk or posedge rst)
begin
if (rst)
tx_point_q <=#Tp 1'b0;
else if (reset_mode)
tx_point_q <=#Tp 1'b0;
else
tx_point_q <=#Tp tx_point;
end
/* Changing bit order from [7:0] to [0:7] */
can_ibo i_ibo_tx_data_0 (.di(tx_data_0), .do(r_tx_data_0));
can_ibo i_ibo_tx_data_1 (.di(tx_data_1), .do(r_tx_data_1));
can_ibo i_ibo_tx_data_2 (.di(tx_data_2), .do(r_tx_data_2));
can_ibo i_ibo_tx_data_3 (.di(tx_data_3), .do(r_tx_data_3));
can_ibo i_ibo_tx_data_4 (.di(tx_data_4), .do(r_tx_data_4));
can_ibo i_ibo_tx_data_5 (.di(tx_data_5), .do(r_tx_data_5));
can_ibo i_ibo_tx_data_6 (.di(tx_data_6), .do(r_tx_data_6));
can_ibo i_ibo_tx_data_7 (.di(tx_data_7), .do(r_tx_data_7));
can_ibo i_ibo_tx_data_8 (.di(tx_data_8), .do(r_tx_data_8));
can_ibo i_ibo_tx_data_9 (.di(tx_data_9), .do(r_tx_data_9));
can_ibo i_ibo_tx_data_10 (.di(tx_data_10), .do(r_tx_data_10));
can_ibo i_ibo_tx_data_11 (.di(tx_data_11), .do(r_tx_data_11));
can_ibo i_ibo_tx_data_12 (.di(tx_data_12), .do(r_tx_data_12));
/* Changing bit order from [14:0] to [0:14] */
can_ibo i_calculated_crc0 (.di(calculated_crc[14:7]), .do(r_calculated_crc[7:0]));
can_ibo i_calculated_crc1 (.di({calculated_crc[6:0], 1'b0}), .do(r_calculated_crc[15:8]));
assign basic_chain = {r_tx_data_1[7:4], 2'h0, r_tx_data_1[3:0], r_tx_data_0[7:0], 1'b0};
assign basic_chain_data = {r_tx_data_9, r_tx_data_8, r_tx_data_7, r_tx_data_6, r_tx_data_5, r_tx_data_4, r_tx_data_3, r_tx_data_2};
assign extended_chain_std = {r_tx_data_0[7:4], 2'h0, r_tx_data_0[1], r_tx_data_2[2:0], r_tx_data_1[7:0], 1'b0};
assign extended_chain_ext = {r_tx_data_0[7:4], 2'h0, r_tx_data_0[1], r_tx_data_4[4:0], r_tx_data_3[7:0], r_tx_data_2[7:3], 1'b1, 1'b1, r_tx_data_2[2:0], r_tx_data_1[7:0], 1'b0};
assign extended_chain_data_std = {r_tx_data_10, r_tx_data_9, r_tx_data_8, r_tx_data_7, r_tx_data_6, r_tx_data_5, r_tx_data_4, r_tx_data_3};
assign extended_chain_data_ext = {r_tx_data_12, r_tx_data_11, r_tx_data_10, r_tx_data_9, r_tx_data_8, r_tx_data_7, r_tx_data_6, r_tx_data_5};
always @ (extended_mode or rx_data or tx_pointer or extended_chain_data_std or extended_chain_data_ext or rx_crc or r_calculated_crc or
r_tx_data_0 or extended_chain_ext or extended_chain_std or basic_chain_data or basic_chain or
finish_msg)
begin
if (extended_mode)
begin
if (rx_data) // data stage
if (r_tx_data_0[0]) // Extended frame
tx_bit = extended_chain_data_ext[tx_pointer];
else
tx_bit = extended_chain_data_std[tx_pointer];
else if (rx_crc)
tx_bit = r_calculated_crc[tx_pointer];
else if (finish_msg)
tx_bit = 1'b1;
else
begin
if (r_tx_data_0[0]) // Extended frame
tx_bit = extended_chain_ext[tx_pointer];
else
tx_bit = extended_chain_std[tx_pointer];
end
end
else // Basic mode
begin
if (rx_data) // data stage
tx_bit = basic_chain_data[tx_pointer];
else if (rx_crc)
tx_bit = r_calculated_crc[tx_pointer];
else if (finish_msg)
tx_bit = 1'b1;
else
tx_bit = basic_chain[tx_pointer];
end
end
assign limited_tx_cnt_ext = tx_data_0[3] ? 6'h3f : ((tx_data_0[2:0] <<3) - 1'b1);
assign limited_tx_cnt_std = tx_data_1[3] ? 6'h3f : ((tx_data_1[2:0] <<3) - 1'b1);
assign rst_tx_pointer = ((~bit_de_stuff_tx) & tx_point & (~rx_data) & extended_mode & r_tx_data_0[0] & tx_pointer == 6'd38 ) | // arbitration + control for extended format
((~bit_de_stuff_tx) & tx_point & (~rx_data) & extended_mode & (~r_tx_data_0[0]) & tx_pointer == 6'd18 ) | // arbitration + control for extended format
((~bit_de_stuff_tx) & tx_point & (~rx_data) & (~extended_mode) & tx_pointer == 6'd18 ) | // arbitration + control for standard format
((~bit_de_stuff_tx) & tx_point & rx_data & extended_mode & tx_pointer == limited_tx_cnt_ext) | // data (overflow is OK here)
((~bit_de_stuff_tx) & tx_point & rx_data & (~extended_mode) & tx_pointer == limited_tx_cnt_std) | // data (overflow is OK here)
( tx_point & rx_crc_lim ) | // crc
(go_rx_idle ) | // at the end
(reset_mode ) |
(overload_frame ) |
(error_frame ) ;
always @ (posedge clk or posedge rst)
begin
if (rst)
tx_pointer <= 6'h0;
else if (rst_tx_pointer)
tx_pointer <=#Tp 6'h0;
else if (go_early_tx | (tx_point & (tx_state | go_tx) & (~bit_de_stuff_tx)))
tx_pointer <=#Tp tx_pointer + 1'b1;
end
assign tx_successful = transmitter & go_rx_inter & (~go_error_frame) & (~error_frame_ended) & (~overload_frame_ended) & (~arbitration_lost);
always @ (posedge clk or posedge rst)
begin
if (rst)
need_to_tx <= 1'b0;
else if (tx_successful | reset_mode | (abort_tx & (~transmitting)) | ((~tx_state) & tx_state_q & single_shot_transmission))
need_to_tx <=#Tp 1'h0;
else if (tx_request & sample_point)
need_to_tx <=#Tp 1'b1;
end
assign go_early_tx = (~listen_only_mode) & need_to_tx & (~tx_state) & (~suspend | (susp_cnt == 3'h7)) & sample_point & (~sampled_bit) & (rx_idle | last_bit_of_inter);
assign go_tx = (~listen_only_mode) & need_to_tx & (~tx_state) & (~suspend | (sample_point & (susp_cnt == 3'h7))) & (go_early_tx | rx_idle);
// go_early_tx latched (for proper bit_de_stuff generation)
always @ (posedge clk or posedge rst)
begin
if (rst)
go_early_tx_latched <= 1'b0;
else if (reset_mode || tx_point)
go_early_tx_latched <=#Tp 1'b0;
else if (go_early_tx)
go_early_tx_latched <=#Tp 1'b1;
end
// Tx state
always @ (posedge clk or posedge rst)
begin
if (rst)
tx_state <= 1'b0;
else if (reset_mode | go_rx_inter | error_frame | arbitration_lost)
tx_state <=#Tp 1'b0;
else if (go_tx)
tx_state <=#Tp 1'b1;
end
always @ (posedge clk or posedge rst)
begin
if (rst)
tx_state_q <=#Tp 1'b0;
else if (reset_mode)
tx_state_q <=#Tp 1'b0;
else
tx_state_q <=#Tp tx_state;
end
// Node is a transmitter
always @ (posedge clk or posedge rst)
begin
if (rst)
transmitter <= 1'b0;
else if (go_tx)
transmitter <=#Tp 1'b1;
else if (reset_mode | go_rx_idle | suspend & go_rx_id1)
transmitter <=#Tp 1'b0;
end
// Signal "transmitting" signals that the core is a transmitting (message, error frame or overload frame). No synchronization is done meanwhile.
// Node might be both transmitter or receiver (sending error or overload frame)
always @ (posedge clk or posedge rst)
begin
if (rst)
transmitting <= 1'b0;
else if (go_error_frame | go_overload_frame | go_tx | send_ack)
transmitting <=#Tp 1'b1;
else if (reset_mode | go_rx_idle | (go_rx_id1 & (~tx_state)) | (arbitration_lost & tx_state))
transmitting <=#Tp 1'b0;
end
always @ (posedge clk or posedge rst)
begin
if (rst)
suspend <= 1'b0;
else if (reset_mode | (sample_point & (susp_cnt == 3'h7)))
suspend <=#Tp 1'b0;
else if (not_first_bit_of_inter & transmitter & node_error_passive)
suspend <=#Tp 1'b1;
end
always @ (posedge clk or posedge rst)
begin
if (rst)
susp_cnt_en <= 1'b0;
else if (reset_mode | (sample_point & (susp_cnt == 3'h7)))
susp_cnt_en <=#Tp 1'b0;
else if (suspend & sample_point & last_bit_of_inter)
susp_cnt_en <=#Tp 1'b1;
end
always @ (posedge clk or posedge rst)
begin
if (rst)
susp_cnt <= 3'h0;
else if (reset_mode | (sample_point & (susp_cnt == 3'h7)))
susp_cnt <=#Tp 3'h0;
else if (susp_cnt_en & sample_point)
susp_cnt <=#Tp susp_cnt + 1'b1;
end
always @ (posedge clk or posedge rst)
begin
if (rst)
finish_msg <= 1'b0;
else if (go_rx_idle | go_rx_id1 | error_frame | reset_mode)
finish_msg <=#Tp 1'b0;
else if (go_rx_crc_lim)
finish_msg <=#Tp 1'b1;
end
always @ (posedge clk or posedge rst)
begin
if (rst)
arbitration_lost <= 1'b0;
else if (go_rx_idle | error_frame_ended | reset_mode)
arbitration_lost <=#Tp 1'b0;
else if (transmitter & sample_point & tx & arbitration_field & ~sampled_bit)
arbitration_lost <=#Tp 1'b1;
end
always @ (posedge clk or posedge rst)
begin
if (rst)
begin
arbitration_lost_q <=#Tp 1'b0;
read_arbitration_lost_capture_reg_q <=#Tp 1'b0;
end
else if (reset_mode)
begin
arbitration_lost_q <=#Tp 1'b0;
read_arbitration_lost_capture_reg_q <=#Tp 1'b0;
end
else
begin
arbitration_lost_q <=#Tp arbitration_lost;
read_arbitration_lost_capture_reg_q <=#Tp read_arbitration_lost_capture_reg;
end
end
assign set_arbitration_lost_irq = arbitration_lost & (~arbitration_lost_q) & (~arbitration_blocked);
always @ (posedge clk or posedge rst)
begin
if (rst)
arbitration_cnt_en <= 1'b0;
else if (reset_mode || arbitration_blocked)
arbitration_cnt_en <=#Tp 1'b0;
else if (rx_id1 & sample_point & (~arbitration_blocked))
arbitration_cnt_en <=#Tp 1'b1;
end
always @ (posedge clk or posedge rst)
begin
if (rst)
arbitration_blocked <= 1'b0;
else if (reset_mode || read_arbitration_lost_capture_reg)
arbitration_blocked <=#Tp 1'b0;
else if (set_arbitration_lost_irq)
arbitration_blocked <=#Tp 1'b1;
end
always @ (posedge clk or posedge rst)
begin
if (rst)
arbitration_lost_capture <= 5'h0;
else if (read_arbitration_lost_capture_reg_q)
arbitration_lost_capture <=#Tp 5'h0;
else if (sample_point & (~arbitration_blocked) & arbitration_cnt_en & (~bit_de_stuff))
arbitration_lost_capture <=#Tp arbitration_lost_capture + 1'b1;
end
always @ (posedge clk or posedge rst)
begin
if (rst)
rx_err_cnt <= 9'h0;
else if (we_rx_err_cnt & (~node_bus_off))
rx_err_cnt <=#Tp {1'b0, data_in};
else if (set_reset_mode)
rx_err_cnt <=#Tp 9'h0;
else
begin
if ((~listen_only_mode) & (~transmitter | arbitration_lost))
begin
if (go_rx_ack_lim & (~go_error_frame) & (~crc_err) & (rx_err_cnt > 9'h0))
begin
if (rx_err_cnt > 9'd127)
rx_err_cnt <=#Tp 9'd127;
else
rx_err_cnt <=#Tp rx_err_cnt - 1'b1;
end
else if (rx_err_cnt < 9'd128)
begin
if (go_error_frame & (~rule5)) // 1 (rule 5 is just the opposite then rule 1 exception
rx_err_cnt <=#Tp rx_err_cnt + 1'b1;
else if ( (error_flag_over & (~error_flag_over_latched) & sample_point & (~sampled_bit) & (error_cnt1 == 3'd7) ) | // 2
(go_error_frame & rule5 ) | // 5
(sample_point & (~sampled_bit) & (delayed_dominant_cnt == 3'h7) ) // 6
)
rx_err_cnt <=#Tp rx_err_cnt + 4'h8;
end
end
end
end
always @ (posedge clk or posedge rst)
begin
if (rst)
tx_err_cnt <= 9'h0;
else if (we_tx_err_cnt)
tx_err_cnt <=#Tp {1'b0, data_in};
else
begin
if (set_reset_mode)
tx_err_cnt <=#Tp 9'd128;
else if ((tx_err_cnt > 9'd0) & (tx_successful | bus_free))
tx_err_cnt <=#Tp tx_err_cnt - 1'h1;
else if (transmitter & (~arbitration_lost))
begin
if ( (sample_point & (~sampled_bit) & (delayed_dominant_cnt == 3'h7) ) | // 6
(go_error_frame & rule5 ) | // 4 (rule 5 is the same as rule 4)
(go_error_frame & (~(transmitter & node_error_passive & ack_err)) & (~(transmitter & stuff_err &
arbitration_field & sample_point & tx & (~sampled_bit))) ) | // 3
(error_frame & rule3_exc1_2 ) // 3
)
tx_err_cnt <=#Tp tx_err_cnt + 4'h8;
end
end
end
always @ (posedge clk or posedge rst)
begin
if (rst)
node_error_passive <= 1'b0;
else if ((rx_err_cnt < 128) & (tx_err_cnt < 9'd128))
node_error_passive <=#Tp 1'b0;
else if (((rx_err_cnt >= 128) | (tx_err_cnt >= 9'd128)) & (error_frame_ended | go_error_frame | (~reset_mode) & reset_mode_q) & (~node_bus_off))
node_error_passive <=#Tp 1'b1;
end
assign node_error_active = ~(node_error_passive | node_bus_off);
always @ (posedge clk or posedge rst)
begin
if (rst)
node_bus_off <= 1'b0;
else if ((rx_err_cnt == 9'h0) & (tx_err_cnt == 9'd0) & (~reset_mode) | (we_tx_err_cnt & (data_in < 8'd255)))
node_bus_off <=#Tp 1'b0;
else if ((tx_err_cnt >= 9'd256) | (we_tx_err_cnt & (data_in == 8'd255)))
node_bus_off <=#Tp 1'b1;
end
always @ (posedge clk or posedge rst)
begin
if (rst)
bus_free_cnt <= 4'h0;
else if (reset_mode)
bus_free_cnt <=#Tp 4'h0;
else if (sample_point)
begin
if (sampled_bit & bus_free_cnt_en & (bus_free_cnt < 4'd10))
bus_free_cnt <=#Tp bus_free_cnt + 1'b1;
else
bus_free_cnt <=#Tp 4'h0;
end
end
always @ (posedge clk or posedge rst)
begin
if (rst)
bus_free_cnt_en <= 1'b0;
else if ((~reset_mode) & reset_mode_q | node_bus_off_q & (~reset_mode))
bus_free_cnt_en <=#Tp 1'b1;
else if (sample_point & sampled_bit & (bus_free_cnt==4'd10) & (~node_bus_off))
bus_free_cnt_en <=#Tp 1'b0;
end
always @ (posedge clk or posedge rst)
begin
if (rst)
bus_free <= 1'b0;
else if (reset_mode)
bus_free <= 1'b0;
else if (sample_point & sampled_bit & (bus_free_cnt==4'd10))
bus_free <=#Tp 1'b1;
else
bus_free <=#Tp 1'b0;
end
always @ (posedge clk or posedge rst)
begin
if (rst)
waiting_for_bus_free <= 1'b1;
else if (reset_mode)
waiting_for_bus_free <= 1'b1;
else if (bus_free & (~node_bus_off))
waiting_for_bus_free <=#Tp 1'b0;
else if ((~reset_mode) & reset_mode_q | node_bus_off_q & (~reset_mode))
waiting_for_bus_free <=#Tp 1'b1;
end
assign bus_off_on = ~node_bus_off;
assign set_reset_mode = node_bus_off & (~node_bus_off_q);
assign error_status = extended_mode? ((rx_err_cnt >= error_warning_limit) | (tx_err_cnt >= error_warning_limit)) :
((rx_err_cnt >= 9'd96) | (tx_err_cnt >= 9'd96)) ;
assign transmit_status = transmitting || (extended_mode && waiting_for_bus_free);
assign receive_status = extended_mode ? (waiting_for_bus_free || (!rx_idle) && (!transmitting)) :
((!waiting_for_bus_free) && (!rx_idle) && (!transmitting));
/* Error code capture register */
always @ (posedge clk or posedge rst)
begin
if (rst)
error_capture_code <= 8'h0;
else if (read_error_code_capture_reg)
error_capture_code <=#Tp 8'h0;
else if (set_bus_error_irq)
error_capture_code <=#Tp {error_capture_code_type[7:6], error_capture_code_direction, error_capture_code_segment[4:0]};
end
assign error_capture_code_segment[0] = rx_idle | rx_ide | (rx_id2 & (bit_cnt<6'd13)) | rx_r1 | rx_r0 | rx_dlc | rx_ack | rx_ack_lim | error_frame & node_error_active;
assign error_capture_code_segment[1] = rx_idle | rx_id1 | rx_id2 | rx_dlc | rx_data | rx_ack_lim | rx_eof | rx_inter | error_frame & node_error_passive;
assign error_capture_code_segment[2] = (rx_id1 & (bit_cnt>6'd7)) | rx_rtr1 | rx_ide | rx_id2 | rx_rtr2 | rx_r1 | error_frame & node_error_passive | overload_frame;
assign error_capture_code_segment[3] = (rx_id2 & (bit_cnt>6'd4)) | rx_rtr2 | rx_r1 | rx_r0 | rx_dlc | rx_data | rx_crc | rx_crc_lim | rx_ack | rx_ack_lim | rx_eof | overload_frame;
assign error_capture_code_segment[4] = rx_crc_lim | rx_ack | rx_ack_lim | rx_eof | rx_inter | error_frame | overload_frame;
assign error_capture_code_direction = ~transmitting;
always @ (bit_err or form_err or stuff_err)
begin
if (bit_err)
error_capture_code_type[7:6] = 2'b00;
else if (form_err)
error_capture_code_type[7:6] = 2'b01;
else if (stuff_err)
error_capture_code_type[7:6] = 2'b10;
else
error_capture_code_type[7:6] = 2'b11;
end
assign set_bus_error_irq = go_error_frame & (~error_capture_code_blocked);
always @ (posedge clk or posedge rst)
begin
if (rst)
error_capture_code_blocked <= 1'b0;
else if (read_error_code_capture_reg)
error_capture_code_blocked <=#Tp 1'b0;
else if (set_bus_error_irq)
error_capture_code_blocked <=#Tp 1'b1;
end
endmodule
//////////////////////////////////////////////////////////////////////
//// ////
//// can_btl.v ////
//// ////
//// ////
//// This file is part of the CAN Protocol Controller ////
//// http://www.opencores.org/projects/can/ ////
//// ////
//// ////
//// Author(s): ////
//// Igor Mohor ////
//// [email protected] ////
//// ////
//// ////
//// All additional information is available in the README.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2002, 2003, 2004 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//// The CAN protocol is developed by Robert Bosch GmbH and ////
//// protected by patents. Anybody who wants to implement this ////
//// CAN IP core on silicon has to obtain a CAN protocol license ////
//// from Bosch. ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: can_btl.v,v $
// Revision 1.30 2004/10/27 18:51:37 igorm
// Fixed synchronization problem in real hardware when 0xf is used for TSEG1.
//
// Revision 1.29 2004/05/12 15:58:41 igorm
// Core improved to pass all tests with the Bosch VHDL Reference system.
//
// Revision 1.28 2004/02/08 14:25:26 mohor
// Header changed.
//
// Revision 1.27 2003/09/30 00:55:13 mohor
// Error counters fixed to be compatible with Bosch VHDL reference model.
// Small synchronization changes.
//
// Revision 1.26 2003/09/25 18:55:49 mohor
// Synchronization changed, error counters fixed.
//
// Revision 1.25 2003/07/16 13:40:35 mohor
// Fixed according to the linter.
//
// Revision 1.24 2003/07/10 15:32:28 mohor
// Unused signal removed.
//
// Revision 1.23 2003/07/10 01:59:04 tadejm
// Synchronization fixed. In some strange cases it didn't work according to
// the VHDL reference model.
//
// Revision 1.22 2003/07/07 11:21:37 mohor
// Little fixes (to fix warnings).
//
// Revision 1.21 2003/07/03 09:32:20 mohor
// Synchronization changed.
//
// Revision 1.20 2003/06/20 14:51:11 mohor
// Previous change removed. When resynchronization occurs we go to seg1
// stage. sync stage does not cause another start of seg1 stage.
//
// Revision 1.19 2003/06/20 14:28:20 mohor
// When hard_sync or resync occure we need to go to seg1 segment. Going to
// sync segment is in that case blocked.
//
// Revision 1.18 2003/06/17 15:53:33 mohor
// clk_cnt reduced from [8:0] to [6:0].
//
// Revision 1.17 2003/06/17 14:32:17 mohor
// Removed few signals.
//
// Revision 1.16 2003/06/16 13:57:58 mohor
// tx_point generated one clk earlier. rx_i registered. Data corrected when
// using extended mode.
//
// Revision 1.15 2003/06/13 15:02:24 mohor
// Synchronization is also needed when transmitting a message.
//
// Revision 1.14 2003/06/13 14:55:11 mohor
// Counters width changed.
//
// Revision 1.13 2003/06/11 14:21:35 mohor
// When switching to tx, sync stage is overjumped.
//
// Revision 1.12 2003/02/14 20:17:01 mohor
// Several registers added. Not finished, yet.
//
// Revision 1.11 2003/02/09 18:40:29 mohor
// Overload fixed. Hard synchronization also enabled at the last bit of
// interframe.
//
// Revision 1.10 2003/02/09 02:24:33 mohor
// Bosch license warning added. Error counters finished. Overload frames
// still need to be fixed.
//
// Revision 1.9 2003/01/31 01:13:38 mohor
// backup.
//
// Revision 1.8 2003/01/10 17:51:34 mohor
// Temporary version (backup).
//
// Revision 1.7 2003/01/08 02:10:53 mohor
// Acceptance filter added.
//
// Revision 1.6 2002/12/28 04:13:23 mohor
// Backup version.
//
// Revision 1.5 2002/12/27 00:12:52 mohor
// Header changed, testbench improved to send a frame (crc still missing).
//
// Revision 1.4 2002/12/26 01:33:05 mohor
// Tripple sampling supported.
//
// Revision 1.3 2002/12/25 23:44:16 mohor
// Commented lines removed.
//
// Revision 1.2 2002/12/25 14:17:00 mohor
// Synchronization working.
//
// Revision 1.1.1.1 2002/12/20 16:39:21 mohor
// Initial
//
//
//
// synopsys translate_off
//`include "can_defines.v"
`timescale 1ns/10ps
// synopsys translate_on
module can_btl
(
clk,
rst,
rx,
tx,
/* Bus Timing 0 register */
baud_r_presc,
sync_jump_width,
/* Bus Timing 1 register */
time_segment1,
time_segment2,
triple_sampling,
/* Output signals from this module */
sample_point,
sampled_bit,
sampled_bit_q,
tx_point,
hard_sync,
/* Output from can_bsp module */
rx_idle,
rx_inter,
transmitting,
transmitter,
go_rx_inter,
tx_next,
go_overload_frame,
go_error_frame,
go_tx,
send_ack,
node_error_passive
);
parameter Tp = 1;
input clk;
input rst;
input rx;
input tx;
/* Bus Timing 0 register */
input [5:0] baud_r_presc;
input [1:0] sync_jump_width;
/* Bus Timing 1 register */
input [3:0] time_segment1;
input [2:0] time_segment2;
input triple_sampling;
/* Output from can_bsp module */
input rx_idle;
input rx_inter;
input transmitting;
input transmitter;
input go_rx_inter;
input tx_next;
input go_overload_frame;
input go_error_frame;
input go_tx;
input send_ack;
input node_error_passive;
/* Output signals from this module */
output sample_point;
output sampled_bit;
output sampled_bit_q;
output tx_point;
output hard_sync;
reg [6:0] clk_cnt;
reg clk_en;
reg clk_en_q;
reg sync_blocked;
reg hard_sync_blocked;
reg sampled_bit;
reg sampled_bit_q;
reg [4:0] quant_cnt;
reg [3:0] delay;
reg sync;
reg seg1;
reg seg2;
reg resync_latched;
reg sample_point;
reg [1:0] sample;
reg tx_point;
reg tx_next_sp;
wire go_sync;
wire go_seg1;
wire go_seg2;
wire [7:0] preset_cnt;
wire sync_window;
wire resync;
assign preset_cnt = (baud_r_presc + 1'b1)<<1; // (BRP+1)*2
assign hard_sync = (rx_idle | rx_inter) & (~rx) & sampled_bit & (~hard_sync_blocked); // Hard synchronization
assign resync = (~rx_idle) & (~rx_inter) & (~rx) & sampled_bit & (~sync_blocked); // Re-synchronization
/* Generating general enable signal that defines baud rate. */
always @ (posedge clk or posedge rst)
begin
if (rst)
clk_cnt <= 7'h0;
else if (clk_cnt >= (preset_cnt-1'b1))
clk_cnt <=#Tp 7'h0;
else
clk_cnt <=#Tp clk_cnt + 1'b1;
end
always @ (posedge clk or posedge rst)
begin
if (rst)
clk_en <= 1'b0;
else if ({1'b0, clk_cnt} == (preset_cnt-1'b1))
clk_en <=#Tp 1'b1;
else
clk_en <=#Tp 1'b0;
end
always @ (posedge clk or posedge rst)
begin
if (rst)
clk_en_q <= 1'b0;
else
clk_en_q <=#Tp clk_en;
end
/* Changing states */
assign go_sync = clk_en_q & seg2 & (quant_cnt[2:0] == time_segment2) & (~hard_sync) & (~resync);
assign go_seg1 = clk_en_q & (sync | hard_sync | (resync & seg2 & sync_window) | (resync_latched & sync_window));
assign go_seg2 = clk_en_q & (seg1 & (~hard_sync) & (quant_cnt == (time_segment1 + delay)));
always @ (posedge clk or posedge rst)
begin
if (rst)
tx_point <= 1'b0;
else
tx_point <=#Tp ~tx_point & seg2 & ( clk_en & (quant_cnt[2:0] == time_segment2)
| (clk_en | clk_en_q) & (resync | hard_sync)
); // When transmitter we should transmit as soon as possible.
end
/* When early edge is detected outside of the SJW field, synchronization request is latched and performed when
SJW is reached */
always @ (posedge clk or posedge rst)
begin
if (rst)
resync_latched <= 1'b0;
else if (resync & seg2 & (~sync_window))
resync_latched <=#Tp 1'b1;
else if (go_seg1)
resync_latched <= 1'b0;
end
/* Synchronization stage/segment */
always @ (posedge clk or posedge rst)
begin
if (rst)
sync <= 1'b0;
else if (clk_en_q)
sync <=#Tp go_sync;
end
/* Seg1 stage/segment (together with propagation segment which is 1 quant long) */
always @ (posedge clk or posedge rst)
begin
if (rst)
seg1 <= 1'b1;
else if (go_seg1)
seg1 <=#Tp 1'b1;
else if (go_seg2)
seg1 <=#Tp 1'b0;
end
/* Seg2 stage/segment */
always @ (posedge clk or posedge rst)
begin
if (rst)
seg2 <= 1'b0;
else if (go_seg2)
seg2 <=#Tp 1'b1;
else if (go_sync | go_seg1)
seg2 <=#Tp 1'b0;
end
/* Quant counter */
always @ (posedge clk or posedge rst)
begin
if (rst)
quant_cnt <= 5'h0;
else if (go_sync | go_seg1 | go_seg2)
quant_cnt <=#Tp 5'h0;
else if (clk_en_q)
quant_cnt <=#Tp quant_cnt + 1'b1;
end
/* When late edge is detected (in seg1 stage), stage seg1 is prolonged. */
always @ (posedge clk or posedge rst)
begin
if (rst)
delay <= 4'h0;
else if (resync & seg1 & (~transmitting | transmitting & (tx_next_sp | (tx & (~rx))))) // when transmitting 0 with positive error delay is set to 0
delay <=#Tp (quant_cnt > {3'h0, sync_jump_width})? ({2'h0, sync_jump_width} + 1'b1) : (quant_cnt + 1'b1);
else if (go_sync | go_seg1)
delay <=#Tp 4'h0;
end
// If early edge appears within this window (in seg2 stage), phase error is fully compensated
assign sync_window = ((time_segment2 - quant_cnt[2:0]) < ( sync_jump_width + 1'b1));
// Sampling data (memorizing two samples all the time).
always @ (posedge clk or posedge rst)
begin
if (rst)
sample <= 2'b11;
else if (clk_en_q)
sample <= {sample[0], rx};
end
// When enabled, tripple sampling is done here.
always @ (posedge clk or posedge rst)
begin
if (rst)
begin
sampled_bit <= 1'b1;
sampled_bit_q <= 1'b1;
sample_point <= 1'b0;
end
else if (go_error_frame)
begin
sampled_bit_q <=#Tp sampled_bit;
sample_point <=#Tp 1'b0;
end
else if (clk_en_q & (~hard_sync))
begin
if (seg1 & (quant_cnt == (time_segment1 + delay)))
begin
sample_point <=#Tp 1'b1;
sampled_bit_q <=#Tp sampled_bit;
if (triple_sampling)
sampled_bit <=#Tp (sample[0] & sample[1]) | ( sample[0] & rx) | (sample[1] & rx);
else
sampled_bit <=#Tp rx;
end
end
else
sample_point <=#Tp 1'b0;
end
// tx_next_sp shows next value that will be driven on the TX. When driving 1 and receiving 0 we
// need to synchronize (even when we are a transmitter)
always @ (posedge clk or posedge rst)
begin
if (rst)
tx_next_sp <= 1'b0;
else if (go_overload_frame | (go_error_frame & (~node_error_passive)) | go_tx | send_ack)
tx_next_sp <=#Tp 1'b0;
else if (go_error_frame & node_error_passive)
tx_next_sp <=#Tp 1'b1;
else if (sample_point)
tx_next_sp <=#Tp tx_next;
end
/* Blocking synchronization (can occur only once in a bit time) */
always @ (posedge clk or posedge rst)
begin
if (rst)
sync_blocked <=#Tp 1'b1;
else if (clk_en_q)
begin
if (resync)
sync_blocked <=#Tp 1'b1;
else if (go_seg2)
sync_blocked <=#Tp 1'b0;
end
end
/* Blocking hard synchronization when occurs once or when we are transmitting a msg */
always @ (posedge clk or posedge rst)
begin
if (rst)
hard_sync_blocked <=#Tp 1'b0;
else if (hard_sync & clk_en_q | (transmitting & transmitter | go_tx) & tx_point & (~tx_next))
hard_sync_blocked <=#Tp 1'b1;
else if (go_rx_inter | (rx_idle | rx_inter) & sample_point & sampled_bit) // When a glitch performed synchronization
hard_sync_blocked <=#Tp 1'b0;
end
endmodule
//////////////////////////////////////////////////////////////////////
//// ////
//// can_crc.v ////
//// ////
//// ////
//// This file is part of the CAN Protocol Controller ////
//// http://www.opencores.org/projects/can/ ////
//// ////
//// ////
//// Author(s): ////
//// Igor Mohor ////
//// [email protected] ////
//// ////
//// ////
//// All additional information is available in the README.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2002, 2003, 2004 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//// The CAN protocol is developed by Robert Bosch GmbH and ////
//// protected by patents. Anybody who wants to implement this ////
//// CAN IP core on silicon has to obtain a CAN protocol license ////
//// from Bosch. ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: can_crc.v,v $
// Revision 1.5 2004/02/08 14:25:57 mohor
// Header changed.
//
// Revision 1.4 2003/07/16 13:16:51 mohor
// Fixed according to the linter.
//
// Revision 1.3 2003/02/10 16:02:11 mohor
// CAN is working according to the specification. WB interface and more
// registers (status, IRQ, ...) needs to be added.
//
// Revision 1.2 2003/02/09 02:24:33 mohor
// Bosch license warning added. Error counters finished. Overload frames
// still need to be fixed.
//
// Revision 1.1 2003/01/08 02:10:54 mohor
// Acceptance filter added.
//
//
//
//
// synopsys translate_off
//`include "can_defines.v"
`timescale 1ns/10ps
// synopsys translate_on
module can_crc (clk, data, enable, initialize, crc);
parameter Tp = 1;
input clk;
input data;
input enable;
input initialize;
output [14:0] crc;
reg [14:0] crc;
wire crc_next;
wire [14:0] crc_tmp;
assign crc_next = data ^ crc[14];
assign crc_tmp = {crc[13:0], 1'b0};
always @ (posedge clk)
begin
if(initialize)
crc <= #Tp 15'h0;
else if (enable)
begin
if (crc_next)
crc <= #Tp crc_tmp ^ 15'h4599;
else
crc <= #Tp crc_tmp;
end
end
endmodule
//////////////////////////////////////////////////////////////////////
//// ////
//// can_fifo.v ////
//// ////
//// ////
//// This file is part of the CAN Protocol Controller ////
//// http://www.opencores.org/projects/can/ ////
//// ////
//// ////
//// Author(s): ////
//// Igor Mohor ////
//// [email protected] ////
//// ////
//// ////
//// All additional information is available in the README.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2002, 2003, 2004 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//// The CAN protocol is developed by Robert Bosch GmbH and ////
//// protected by patents. Anybody who wants to implement this ////
//// CAN IP core on silicon has to obtain a CAN protocol license ////
//// from Bosch. ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: can_fifo.v,v $
// Revision 1.27 2004/11/18 12:39:34 igorm
// Fixes for compatibility after the SW reset.
//
// Revision 1.26 2004/02/08 14:30:57 mohor
// Header changed.
//
// Revision 1.25 2003/10/23 16:52:17 mohor
// Active high/low problem when Altera devices are used. Bug fixed by
// Rojhalat Ibrahim.
//
// Revision 1.24 2003/10/17 05:55:20 markom
// mbist signals updated according to newest convention
//
// Revision 1.23 2003/09/05 12:46:41 mohor
// ALTERA_RAM supported.
//
// Revision 1.22 2003/08/20 09:59:16 mohor
// Artisan RAM fixed (when not using BIST).
//
// Revision 1.21 2003/08/14 16:04:52 simons
// Artisan ram instances added.
//
// Revision 1.20 2003/07/16 14:00:45 mohor
// Fixed according to the linter.
//
// Revision 1.19 2003/07/03 09:30:44 mohor
// PCI_BIST replaced with CAN_BIST.
//
// Revision 1.18 2003/06/27 22:14:23 simons
// Overrun fifo implemented with FFs, because it is not possible to create such a memory.
//
// Revision 1.17 2003/06/27 20:56:15 simons
// Virtual silicon ram instances added.
//
// Revision 1.16 2003/06/18 23:03:44 mohor
// Typo fixed.
//
// Revision 1.15 2003/06/11 09:37:05 mohor
// overrun and length_info fifos are initialized at the end of reset.
//
// Revision 1.14 2003/03/05 15:02:30 mohor
// Xilinx RAM added.
//
// Revision 1.13 2003/03/01 22:53:33 mohor
// Actel APA ram supported.
//
// Revision 1.12 2003/02/19 14:44:03 mohor
// CAN core finished. Host interface added. Registers finished.
// Synchronization to the wishbone finished.
//
// Revision 1.11 2003/02/14 20:17:01 mohor
// Several registers added. Not finished, yet.
//
// Revision 1.10 2003/02/11 00:56:06 mohor
// Wishbone interface added.
//
// Revision 1.9 2003/02/09 02:24:33 mohor
// Bosch license warning added. Error counters finished. Overload frames
// still need to be fixed.
//
// Revision 1.8 2003/01/31 01:13:38 mohor
// backup.
//
// Revision 1.7 2003/01/17 17:44:31 mohor
// Fifo corrected to be synthesizable.
//
// Revision 1.6 2003/01/15 13:16:47 mohor
// When a frame with "remote request" is received, no data is stored
// to fifo, just the frame information (identifier, ...). Data length
// that is stored is the received data length and not the actual data
// length that is stored to fifo.
//
// Revision 1.5 2003/01/14 17:25:09 mohor
// Addresses corrected to decimal values (previously hex).
//
// Revision 1.4 2003/01/14 12:19:35 mohor
// rx_fifo is now working.
//
// Revision 1.3 2003/01/09 21:54:45 mohor
// rx fifo added. Not 100 % verified, yet.
//
// Revision 1.2 2003/01/09 14:46:58 mohor
// Temporary files (backup).
//
// Revision 1.1 2003/01/08 02:10:55 mohor
// Acceptance filter added.
//
//
//
//
// synopsys translate_off
//`include "can_defines.v"
`timescale 1ns/10ps
// synopsys translate_on
module can_fifo
(
clk,
rst,
wr,
data_in,
addr,
data_out,
fifo_selected,
reset_mode,
release_buffer,
extended_mode,
overrun,
info_empty,
info_cnt,
`ifdef CAN_BIST
,
mbist_si_i,
mbist_so_o,
mbist_ctrl_i,
`endif
// ---- Signals for ram
// port connections for Ram
//64x8
q_dp_64x8,
data_64x8,
wren_64x8,
rden_64x8,
wraddress_64x8,
rdaddress_64x8,
//64x4
q_dp_64x4,
data_64x4,
wren_64x4x1,
wraddress_64x4x1,
rdaddress_64x4x1,
//64x1
q_dp_64x1,
data_64x1
);
parameter Tp = 1;
input clk;
input rst;
input wr;
input [7:0] data_in;
input [5:0] addr;
input reset_mode;
input release_buffer;
input extended_mode;
input fifo_selected;
output [7:0] data_out;
output overrun;
output info_empty;
output [6:0] info_cnt;
`ifdef CAN_BIST
input mbist_si_i;
output mbist_so_o;
input [`CAN_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i; // bist chain shift control
wire mbist_s_0;
`endif
//------------------------------------------------
// port connections for Ram
//64x8
input [7:0] q_dp_64x8;
output[7:0] data_64x8;
output wren_64x8;
output rden_64x8;
output[5:0] wraddress_64x8;
output[5:0] rdaddress_64x8;
//64x4
input [3:0] q_dp_64x4;
output[3:0] data_64x4;
output wren_64x4x1;
output[5:0] wraddress_64x4x1;
output[5:0] rdaddress_64x4x1;
//64x1
input[0:0] q_dp_64x1;
output[0:0] data_64x1;
//------------------------------------------------
`ifdef ALTERA_RAM
`else
`ifdef ACTEL_APA_RAM
`else
`ifdef XILINX_RAM
`else
`ifdef ARTISAN_RAM
reg overrun_info[0:63];
`else
`ifdef VIRTUALSILICON_RAM
reg overrun_info[0:63];
`else
reg [7:0] fifo [0:63];
reg [3:0] length_fifo[0:63];
reg overrun_info[0:63];
`endif
`endif
`endif
`endif
`endif
reg [5:0] rd_pointer;
reg [5:0] wr_pointer;
reg [5:0] read_address;
reg [5:0] wr_info_pointer;
reg [5:0] rd_info_pointer;
reg wr_q;
reg [3:0] len_cnt;
reg [6:0] fifo_cnt;
reg [6:0] info_cnt;
reg latch_overrun;
reg initialize_memories;
wire [3:0] length_info;
wire write_length_info;
wire fifo_empty;
wire fifo_full;
wire info_full;
assign write_length_info = (~wr) & wr_q;
// Delayed write signal
always @ (posedge clk or posedge rst)
begin
if (rst)
wr_q <=#Tp 1'b0;
else if (reset_mode)
wr_q <=#Tp 1'b0;
else
wr_q <=#Tp wr;
end
// length counter
always @ (posedge clk or posedge rst)
begin
if (rst)
len_cnt <= 4'h0;
else if (reset_mode | write_length_info)
len_cnt <=#Tp 4'h0;
else if (wr & (~fifo_full))
len_cnt <=#Tp len_cnt + 1'b1;
end
// wr_info_pointer
always @ (posedge clk or posedge rst)
begin
if (rst)
wr_info_pointer <= 6'h0;
else if (write_length_info & (~info_full) | initialize_memories)
wr_info_pointer <=#Tp wr_info_pointer + 1'b1;
else if (reset_mode)
wr_info_pointer <=#Tp rd_info_pointer;
end
// rd_info_pointer
always @ (posedge clk or posedge rst)
begin
if (rst)
rd_info_pointer <= 6'h0;
else if (release_buffer & (~fifo_empty))
rd_info_pointer <=#Tp rd_info_pointer + 1'b1;
end
// rd_pointer
always @ (posedge clk or posedge rst)
begin
if (rst)
rd_pointer <= 5'h0;
else if (release_buffer & (~fifo_empty))
rd_pointer <=#Tp rd_pointer + {2'h0, length_info};
end
// wr_pointer
always @ (posedge clk or posedge rst)
begin
if (rst)
wr_pointer <= 5'h0;
else if (reset_mode)
wr_pointer <=#Tp rd_pointer;
else if (wr & (~fifo_full))
wr_pointer <=#Tp wr_pointer + 1'b1;
end
// latch_overrun
always @ (posedge clk or posedge rst)
begin
if (rst)
latch_overrun <= 1'b0;
else if (reset_mode | write_length_info)
latch_overrun <=#Tp 1'b0;
else if (wr & fifo_full)
latch_overrun <=#Tp 1'b1;
end
// Counting data in fifo
always @ (posedge clk or posedge rst)
begin
if (rst)
fifo_cnt <= 7'h0;
else if (reset_mode)
fifo_cnt <=#Tp 7'h0;
else if (wr & (~release_buffer) & (~fifo_full))
fifo_cnt <=#Tp fifo_cnt + 1'b1;
else if ((~wr) & release_buffer & (~fifo_empty))
fifo_cnt <=#Tp fifo_cnt - {3'h0, length_info};
else if (wr & release_buffer & (~fifo_full) & (~fifo_empty))
fifo_cnt <=#Tp fifo_cnt - {3'h0, length_info} + 1'b1;
end
assign fifo_full = fifo_cnt == 7'd64;
assign fifo_empty = fifo_cnt == 7'd0;
// Counting data in length_fifo and overrun_info fifo
always @ (posedge clk or posedge rst)
begin
if (rst)
info_cnt <=#Tp 7'h0;
else if (reset_mode)
info_cnt <=#Tp 7'h0;
else if (write_length_info ^ release_buffer)
begin
if (release_buffer & (~info_empty))
info_cnt <=#Tp info_cnt - 1'b1;
else if (write_length_info & (~info_full))
info_cnt <=#Tp info_cnt + 1'b1;
end
end
assign info_full = info_cnt == 7'd64;
assign info_empty = info_cnt == 7'd0;
// Selecting which address will be used for reading data from rx fifo
always @ (extended_mode or rd_pointer or addr)
begin
if (extended_mode) // extended mode
read_address = rd_pointer + (addr - 6'd16);
else // normal mode
read_address = rd_pointer + (addr - 6'd20);
end
always @ (posedge clk or posedge rst)
begin
if (rst)
initialize_memories <= 1'b1;
else if (&wr_info_pointer)
initialize_memories <=#Tp 1'b0;
end
`ifdef INFERRAM
// port connections for Ram
//64x8
assign data_out = q_dp_64x8;
assign data_64x8 = data_in;
assign wren_64x8 = wr & (~fifo_full);
assign rden_64x8 = fifo_selected;
assign wraddress_64x8 = wr_pointer;
assign rdaddress_64x8 = read_address;
//64x4
assign length_info = q_dp_64x4;
assign data_64x4 = (len_cnt & {4{~initialize_memories}});
assign wren_64x4x1 = (write_length_info & (~info_full) | initialize_memories);
assign wraddress_64x4x1 = wr_info_pointer;
assign rdaddress_64x4x1 = rd_info_pointer;
//64x1
assign overrun = q_dp_64x1;
assign data_64x1 = ((latch_overrun | (wr & fifo_full)) & (~initialize_memories));
// `ifdef ALTERA_RAM
// // altera_ram_64x8_sync fifo
// lpm_ram_dp fifo
// (
// .q (data_out),
// .rdclock (clk),
// .wrclock (clk),
// .data (data_in),
// .wren (wr & (~fifo_full)),
// .rden (fifo_selected),
// .wraddress (wr_pointer),
// .rdaddress (read_address)
// );
// defparam fifo.lpm_width = 8;
// defparam fifo.lpm_widthad = 6;
// defparam fifo.lpm_numwords = 64;
//
//
// // altera_ram_64x4_sync info_fifo
// lpm_ram_dp info_fifo
// (
// .q (length_info),
// .rdclock (clk),
// .wrclock (clk),
// .data (len_cnt & {4{~initialize_memories}}),
// .wren (write_length_info & (~info_full) | initialize_memories),
// .wraddress (wr_info_pointer),
// .rdaddress (rd_info_pointer)
// );
// defparam info_fifo.lpm_width = 4;
// defparam info_fifo.lpm_widthad = 6;
// defparam info_fifo.lpm_numwords = 64;
//
//
// // altera_ram_64x1_sync overrun_fifo
// lpm_ram_dp overrun_fifo
// (
// .q (overrun),
// .rdclock (clk),
// .wrclock (clk),
// .data ((latch_overrun | (wr & fifo_full)) & (~initialize_memories)),
// .wren (write_length_info & (~info_full) | initialize_memories),
// .wraddress (wr_info_pointer),
// .rdaddress (rd_info_pointer)
// );
// defparam overrun_fifo.lpm_width = 1;
// defparam overrun_fifo.lpm_widthad = 6;
// defparam overrun_fifo.lpm_numwords = 64;
`else
`ifdef ACTEL_APA_RAM
actel_ram_64x8_sync fifo
(
.DO (data_out),
.RCLOCK (clk),
.WCLOCK (clk),
.DI (data_in),
.PO (), // parity not used
.WRB (~(wr & (~fifo_full))),
.RDB (~fifo_selected),
.WADDR (wr_pointer),
.RADDR (read_address)
);
actel_ram_64x4_sync info_fifo
(
.DO (length_info),
.RCLOCK (clk),
.WCLOCK (clk),
.DI (len_cnt & {4{~initialize_memories}}),
.PO (), // parity not used
.WRB (~(write_length_info & (~info_full) | initialize_memories)),
.RDB (1'b0), // always enabled
.WADDR (wr_info_pointer),
.RADDR (rd_info_pointer)
);
actel_ram_64x1_sync overrun_fifo
(
.DO (overrun),
.RCLOCK (clk),
.WCLOCK (clk),
.DI ((latch_overrun | (wr & fifo_full)) & (~initialize_memories)),
.PO (), // parity not used
.WRB (~(write_length_info & (~info_full) | initialize_memories)),
.RDB (1'b0), // always enabled
.WADDR (wr_info_pointer),
.RADDR (rd_info_pointer)
);
`else
`ifdef XILINX_RAM
RAMB4_S8_S8 fifo
(
.DOA(),
.DOB(data_out),
.ADDRA({3'h0, wr_pointer}),
.CLKA(clk),
.DIA(data_in),
.ENA(1'b1),
.RSTA(1'b0),
.WEA(wr & (~fifo_full)),
.ADDRB({3'h0, read_address}),
.CLKB(clk),
.DIB(8'h0),
.ENB(1'b1),
.RSTB(1'b0),
.WEB(1'b0)
);
RAMB4_S4_S4 info_fifo
(
.DOA(),
.DOB(length_info),
.ADDRA({4'h0, wr_info_pointer}),
.CLKA(clk),
.DIA(len_cnt & {4{~initialize_memories}}),
.ENA(1'b1),
.RSTA(1'b0),
.WEA(write_length_info & (~info_full) | initialize_memories),
.ADDRB({4'h0, rd_info_pointer}),
.CLKB(clk),
.DIB(4'h0),
.ENB(1'b1),
.RSTB(1'b0),
.WEB(1'b0)
);
RAMB4_S1_S1 overrun_fifo
(
.DOA(),
.DOB(overrun),
.ADDRA({6'h0, wr_info_pointer}),
.CLKA(clk),
.DIA((latch_overrun | (wr & fifo_full)) & (~initialize_memories)),
.ENA(1'b1),
.RSTA(1'b0),
.WEA(write_length_info & (~info_full) | initialize_memories),
.ADDRB({6'h0, rd_info_pointer}),
.CLKB(clk),
.DIB(1'h0),
.ENB(1'b1),
.RSTB(1'b0),
.WEB(1'b0)
);
`else
`ifdef VIRTUALSILICON_RAM
`ifdef CAN_BIST
vs_hdtp_64x8_bist fifo
`else
vs_hdtp_64x8 fifo
`endif
(
.RCK (clk),
.WCK (clk),
.RADR (read_address),
.WADR (wr_pointer),
.DI (data_in),
.DOUT (data_out),
.REN (~fifo_selected),
.WEN (~(wr & (~fifo_full)))
`ifdef CAN_BIST
,
// debug chain signals
.mbist_si_i (mbist_si_i),
.mbist_so_o (mbist_s_0),
.mbist_ctrl_i (mbist_ctrl_i)
`endif
);
`ifdef CAN_BIST
vs_hdtp_64x4_bist info_fifo
`else
vs_hdtp_64x4 info_fifo
`endif
(
.RCK (clk),
.WCK (clk),
.RADR (rd_info_pointer),
.WADR (wr_info_pointer),
.DI (len_cnt & {4{~initialize_memories}}),
.DOUT (length_info),
.REN (1'b0),
.WEN (~(write_length_info & (~info_full) | initialize_memories))
`ifdef CAN_BIST
,
// debug chain signals
.mbist_si_i (mbist_s_0),
.mbist_so_o (mbist_so_o),
.mbist_ctrl_i (mbist_ctrl_i)
`endif
);
// overrun_info
always @ (posedge clk)
begin
if (write_length_info & (~info_full) | initialize_memories)
overrun_info[wr_info_pointer] <=#Tp (latch_overrun | (wr & fifo_full)) & (~initialize_memories);
end
// reading overrun
assign overrun = overrun_info[rd_info_pointer];
`else
`ifdef ARTISAN_RAM
`ifdef CAN_BIST
art_hstp_64x8_bist fifo
(
.CLKR (clk),
.CLKW (clk),
.AR (read_address),
.AW (wr_pointer),
.D (data_in),
.Q (data_out),
.REN (~fifo_selected),
.WEN (~(wr & (~fifo_full))),
.mbist_si_i (mbist_si_i),
.mbist_so_o (mbist_s_0),
.mbist_ctrl_i (mbist_ctrl_i)
);
art_hstp_64x4_bist info_fifo
(
.CLKR (clk),
.CLKW (clk),
.AR (rd_info_pointer),
.AW (wr_info_pointer),
.D (len_cnt & {4{~initialize_memories}}),
.Q (length_info),
.REN (1'b0),
.WEN (~(write_length_info & (~info_full) | initialize_memories)),
.mbist_si_i (mbist_s_0),
.mbist_so_o (mbist_so_o),
.mbist_ctrl_i (mbist_ctrl_i)
);
`else
art_hsdp_64x8 fifo
(
.CENA (1'b0),
.CENB (1'b0),
.CLKA (clk),
.CLKB (clk),
.AA (read_address),
.AB (wr_pointer),
.DA (8'h00),
.DB (data_in),
.QA (data_out),
.QB (),
.OENA (~fifo_selected),
.OENB (1'b1),
.WENA (1'b1),
.WENB (~(wr & (~fifo_full)))
);
art_hsdp_64x4 info_fifo
(
.CENA (1'b0),
.CENB (1'b0),
.CLKA (clk),
.CLKB (clk),
.AA (rd_info_pointer),
.AB (wr_info_pointer),
.DA (4'h0),
.DB (len_cnt & {4{~initialize_memories}}),
.QA (length_info),
.QB (),
.OENA (1'b0),
.OENB (1'b1),
.WENA (1'b1),
.WENB (~(write_length_info & (~info_full) | initialize_memories))
);
`endif
// overrun_info
always @ (posedge clk)
begin
if (write_length_info & (~info_full) | initialize_memories)
overrun_info[wr_info_pointer] <=#Tp (latch_overrun | (wr & fifo_full)) & (~initialize_memories);
end
// reading overrun
assign overrun = overrun_info[rd_info_pointer];
`else
// writing data to fifo
always @ (posedge clk)
begin
if (wr & (~fifo_full))
fifo[wr_pointer] <=#Tp data_in;
end
// reading from fifo
assign data_out = fifo[read_address];
// writing length_fifo
always @ (posedge clk)
begin
if (write_length_info & (~info_full) | initialize_memories)
length_fifo[wr_info_pointer] <=#Tp len_cnt & {4{~initialize_memories}};
end
// reading length_fifo
assign length_info = length_fifo[rd_info_pointer];
// overrun_info
always @ (posedge clk)
begin
if (write_length_info & (~info_full) | initialize_memories)
overrun_info[wr_info_pointer] <=#Tp (latch_overrun | (wr & fifo_full)) & (~initialize_memories);
end
// reading overrun
assign overrun = overrun_info[rd_info_pointer];
`endif
`endif
`endif
`endif
`endif
endmodule
//////////////////////////////////////////////////////////////////////
//// ////
//// can_ibo.v ////
//// ////
//// ////
//// This file is part of the CAN Protocol Controller ////
//// http://www.opencores.org/projects/can/ ////
//// ////
//// ////
//// Author(s): ////
//// Igor Mohor ////
//// [email protected] ////
//// ////
//// ////
//// All additional information is available in the README.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2002, 2003, 2004 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//// The CAN protocol is developed by Robert Bosch GmbH and ////
//// protected by patents. Anybody who wants to implement this ////
//// CAN IP core on silicon has to obtain a CAN protocol license ////
//// from Bosch. ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: can_ibo.v,v $
// Revision 1.3 2004/02/08 14:31:44 mohor
// Header changed.
//
// Revision 1.2 2003/02/09 02:24:33 mohor
// Bosch license warning added. Error counters finished. Overload frames
// still need to be fixed.
//
// Revision 1.1 2003/02/04 14:34:52 mohor
// *** empty log message ***
//
//
//
//
// synopsys translate_off
//`include "can_defines.v"
`timescale 1ns/10ps
// synopsys translate_on
// This module only inverts bit order
module can_ibo
(
di,
do
);
input [7:0] di;
output [7:0] do;
assign do[0] = di[7];
assign do[1] = di[6];
assign do[2] = di[5];
assign do[3] = di[4];
assign do[4] = di[3];
assign do[5] = di[2];
assign do[6] = di[1];
assign do[7] = di[0];
endmodule
//////////////////////////////////////////////////////////////////////
//// ////
//// can_register.v ////
//// ////
//// ////
//// This file is part of the CAN Protocol Controller ////
//// http://www.opencores.org/projects/can/ ////
//// ////
//// ////
//// Author(s): ////
//// Igor Mohor ////
//// [email protected] ////
//// ////
//// ////
//// All additional information is available in the README.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2002, 2003, 2004 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//// The CAN protocol is developed by Robert Bosch GmbH and ////
//// protected by patents. Anybody who wants to implement this ////
//// CAN IP core on silicon has to obtain a CAN protocol license ////
//// from Bosch. ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: can_register.v,v $
// Revision 1.7 2004/02/08 14:32:31 mohor
// Header changed.
//
// Revision 1.6 2003/03/20 16:58:50 mohor
// unix.
//
// Revision 1.4 2003/03/11 16:32:34 mohor
// timescale.v is used for simulation only.
//
// Revision 1.3 2003/02/09 02:24:33 mohor
// Bosch license warning added. Error counters finished. Overload frames
// still need to be fixed.
//
// Revision 1.2 2002/12/27 00:12:52 mohor
// Header changed, testbench improved to send a frame (crc still missing).
//
// Revision 1.1.1.1 2002/12/20 16:39:21 mohor
// Initial
//
//
//
// synopsys translate_off
//`include "can_defines.v"
`timescale 1ns/10ps
// synopsys translate_on
module can_register
( data_in,
data_out,
we,
clk
);
parameter WIDTH = 8; // default parameter of the register width
input [WIDTH-1:0] data_in;
input we;
input clk;
output [WIDTH-1:0] data_out;
reg [WIDTH-1:0] data_out;
always @ (posedge clk)
begin
if (we) // write
data_out<=#1 data_in;
end
endmodule
//////////////////////////////////////////////////////////////////////
//// ////
//// can_register_asyn.v ////
//// ////
//// ////
//// This file is part of the CAN Protocol Controller ////
//// http://www.opencores.org/projects/can/ ////
//// ////
//// ////
//// Author(s): ////
//// Igor Mohor ////
//// [email protected] ////
//// ////
//// ////
//// All additional information is available in the README.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2002, 2003, 2004 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//// The CAN protocol is developed by Robert Bosch GmbH and ////
//// protected by patents. Anybody who wants to implement this ////
//// CAN IP core on silicon has to obtain a CAN protocol license ////
//// from Bosch. ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: can_register_asyn.v,v $
// Revision 1.7 2004/02/08 14:33:19 mohor
// Header changed.
//
// Revision 1.6 2003/03/20 16:58:50 mohor
// unix.
//
// Revision 1.4 2003/03/11 16:32:34 mohor
// timescale.v is used for simulation only.
//
// Revision 1.3 2003/02/09 02:24:33 mohor
// Bosch license warning added. Error counters finished. Overload frames
// still need to be fixed.
//
// Revision 1.2 2002/12/27 00:12:52 mohor
// Header changed, testbench improved to send a frame (crc still missing).
//
// Revision 1.1.1.1 2002/12/20 16:39:21 mohor
// Initial
//
//
//
// synopsys translate_off
//`include "can_defines.v"
`timescale 1ns/10ps
// synopsys translate_on
module can_register_asyn
( data_in,
data_out,
we,
clk,
rst
);
parameter WIDTH = 8; // default parameter of the register width
parameter RESET_VALUE = 0;
input [WIDTH-1:0] data_in;
input we;
input clk;
input rst;
output [WIDTH-1:0] data_out;
reg [WIDTH-1:0] data_out;
always @ (posedge clk or posedge rst)
begin
if (rst) // asynchronous reset
data_out<=#1 RESET_VALUE;
else if (we) // write
data_out<=#1 data_in;
end
endmodule
//////////////////////////////////////////////////////////////////////
//// ////
//// can_register_asyn_syn.v ////
//// ////
//// ////
//// This file is part of the CAN Protocol Controller ////
//// http://www.opencores.org/projects/can/ ////
//// ////
//// ////
//// Author(s): ////
//// Igor Mohor ////
//// [email protected] ////
//// ////
//// ////
//// All additional information is available in the README.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2002, 2003, 2004 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//// The CAN protocol is developed by Robert Bosch GmbH and ////
//// protected by patents. Anybody who wants to implement this ////
//// CAN IP core on silicon has to obtain a CAN protocol license ////
//// from Bosch. ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: can_register_asyn_syn.v,v $
// Revision 1.7 2004/02/08 14:33:59 mohor
// Header changed.
//
// Revision 1.6 2003/03/20 16:52:43 mohor
// unix.
//
// Revision 1.4 2003/03/11 16:32:34 mohor
// timescale.v is used for simulation only.
//
// Revision 1.3 2003/02/09 02:24:33 mohor
// Bosch license warning added. Error counters finished. Overload frames
// still need to be fixed.
//
// Revision 1.2 2002/12/27 00:12:52 mohor
// Header changed, testbench improved to send a frame (crc still missing).
//
// Revision 1.1.1.1 2002/12/20 16:39:21 mohor
// Initial
//
//
//
// synopsys translate_off
//`include "can_defines.v"
`timescale 1ns/10ps
// synopsys translate_on
module can_register_asyn_syn
( data_in,
data_out,
we,
clk,
rst,
rst_sync
);
parameter WIDTH = 8; // default parameter of the register width
parameter RESET_VALUE = 0;
input [WIDTH-1:0] data_in;
input we;
input clk;
input rst;
input rst_sync;
output [WIDTH-1:0] data_out;
reg [WIDTH-1:0] data_out;
always @ (posedge clk or posedge rst)
begin
if(rst)
data_out<=#1 RESET_VALUE;
else if (rst_sync) // synchronous reset
data_out<=#1 RESET_VALUE;
else if (we) // write
data_out<=#1 data_in;
end
endmodule
//////////////////////////////////////////////////////////////////////
//// ////
//// can_register_syn.v ////
//// ////
//// ////
//// This file is part of the CAN Protocol Controller ////
//// http://www.opencores.org/projects/can/ ////
//// ////
//// ////
//// Author(s): ////
//// Igor Mohor ////
//// [email protected] ////
//// ////
//// ////
//// All additional information is available in the README.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2002, 2003, 2004 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//// The CAN protocol is developed by Robert Bosch GmbH and ////
//// protected by patents. Anybody who wants to implement this ////
//// CAN IP core on silicon has to obtain a CAN protocol license ////
//// from Bosch. ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: can_register_syn.v,v $
// Revision 1.5 2004/02/08 14:34:40 mohor
// Header changed.
//
// Revision 1.4 2003/03/11 16:31:58 mohor
// timescale.v is used for simulation only.
//
// Revision 1.3 2003/02/09 02:24:33 mohor
// Bosch license warning added. Error counters finished. Overload frames
// still need to be fixed.
//
// Revision 1.2 2002/12/27 00:12:52 mohor
// Header changed, testbench improved to send a frame (crc still missing).
//
// Revision 1.1.1.1 2002/12/20 16:39:21 mohor
// Initial
//
//
//
// synopsys translate_off
//`include "can_defines.v"
`timescale 1ns/10ps
// synopsys translate_on
module can_register_syn
( data_in,
data_out,
we,
clk,
rst_sync
);
parameter WIDTH = 8; // default parameter of the register width
parameter RESET_VALUE = 0;
input [WIDTH-1:0] data_in;
input we;
input clk;
input rst_sync;
output [WIDTH-1:0] data_out;
reg [WIDTH-1:0] data_out;
always @ (posedge clk)
begin
if (rst_sync) // synchronous reset
data_out<=#1 RESET_VALUE;
else if (we) // write
data_out<=#1 data_in;
end
endmodule
//////////////////////////////////////////////////////////////////////
//// ////
//// can_registers.v ////
//// ////
//// ////
//// This file is part of the CAN Protocol Controller ////
//// http://www.opencores.org/projects/can/ ////
//// ////
//// ////
//// Author(s): ////
//// Igor Mohor ////
//// [email protected] ////
//// ////
//// ////
//// All additional information is available in the README.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2002, 2003 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//// The CAN protocol is developed by Robert Bosch GmbH and ////
//// protected by patents. Anybody who wants to implement this ////
//// CAN IP core on silicon has to obtain a CAN protocol license ////
//// from Bosch. ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: can_registers.v,v $
// Revision 1.34 2004/11/18 12:39:43 igorm
// Fixes for compatibility after the SW reset.
//
// Revision 1.33 2004/10/25 11:44:38 igorm
// Interrupt is always cleared for one clock after the irq register is read.
// This fixes problems when CPU is using IRQs that are edge triggered.
//
// Revision 1.32 2004/05/12 15:58:41 igorm
// Core improved to pass all tests with the Bosch VHDL Reference system.
//
// Revision 1.31 2003/09/25 18:55:49 mohor
// Synchronization changed, error counters fixed.
//
// Revision 1.30 2003/07/16 15:19:34 mohor
// Fixed according to the linter.
// Case statement for data_out joined.
//
// Revision 1.29 2003/07/10 01:59:04 tadejm
// Synchronization fixed. In some strange cases it didn't work according to
// the VHDL reference model.
//
// Revision 1.28 2003/07/07 11:21:37 mohor
// Little fixes (to fix warnings).
//
// Revision 1.27 2003/06/22 09:43:03 mohor
// synthesi full_case parallel_case fixed.
//
// Revision 1.26 2003/06/22 01:33:14 mohor
// clkout is clk/2 after the reset.
//
// Revision 1.25 2003/06/21 12:16:30 mohor
// paralel_case and full_case compiler directives added to case statements.
//
// Revision 1.24 2003/06/09 11:22:54 mohor
// data_out is already registered in the can_top.v file.
//
// Revision 1.23 2003/04/15 15:31:24 mohor
// Some features are supported in extended mode only (listen_only_mode...).
//
// Revision 1.22 2003/03/20 16:58:50 mohor
// unix.
//
// Revision 1.20 2003/03/11 16:31:05 mohor
// Mux used for clkout to avoid "gated clocks warning".
//
// Revision 1.19 2003/03/10 17:34:25 mohor
// Doubled declarations removed.
//
// Revision 1.18 2003/03/01 22:52:11 mohor
// Data is latched on read.
//
// Revision 1.17 2003/02/19 15:09:02 mohor
// Incomplete sensitivity list fixed.
//
// Revision 1.16 2003/02/19 14:44:03 mohor
// CAN core finished. Host interface added. Registers finished.
// Synchronization to the wishbone finished.
//
// Revision 1.15 2003/02/18 00:10:15 mohor
// Most of the registers added. Registers "arbitration lost capture", "error code
// capture" + few more still need to be added.
//
// Revision 1.14 2003/02/14 20:17:01 mohor
// Several registers added. Not finished, yet.
//
// Revision 1.13 2003/02/12 14:25:30 mohor
// abort_tx added.
//
// Revision 1.12 2003/02/11 00:56:06 mohor
// Wishbone interface added.
//
// Revision 1.11 2003/02/09 02:24:33 mohor
// Bosch license warning added. Error counters finished. Overload frames
// still need to be fixed.
//
// Revision 1.10 2003/01/31 01:13:38 mohor
// backup.
//
// Revision 1.9 2003/01/15 13:16:48 mohor
// When a frame with "remote request" is received, no data is stored
// to fifo, just the frame information (identifier, ...). Data length
// that is stored is the received data length and not the actual data
// length that is stored to fifo.
//
// Revision 1.8 2003/01/14 17:25:09 mohor
// Addresses corrected to decimal values (previously hex).
//
// Revision 1.7 2003/01/14 12:19:35 mohor
// rx_fifo is now working.
//
// Revision 1.6 2003/01/10 17:51:34 mohor
// Temporary version (backup).
//
// Revision 1.5 2003/01/09 14:46:58 mohor
// Temporary files (backup).
//
// Revision 1.4 2003/01/08 02:10:55 mohor
// Acceptance filter added.
//
// Revision 1.3 2002/12/27 00:12:52 mohor
// Header changed, testbench improved to send a frame (crc still missing).
//
// Revision 1.2 2002/12/26 16:00:34 mohor
// Testbench define file added. Clock divider register added.
//
// Revision 1.1.1.1 2002/12/20 16:39:21 mohor
// Initial
//
//
//
// synopsys translate_off
//`include "can_defines.v"
`timescale 1ns/10ps
// synopsys translate_on
module can_registers
(
clk,
rst,
cs,
we,
addr,
data_in,
data_out,
irq_n,
sample_point,
transmitting,
set_reset_mode,
node_bus_off,
error_status,
rx_err_cnt,
tx_err_cnt,
transmit_status,
receive_status,
tx_successful,
need_to_tx,
overrun,
info_empty,
set_bus_error_irq,
set_arbitration_lost_irq,
arbitration_lost_capture,
node_error_passive,
node_error_active,
rx_message_counter,
/* Mode register */
reset_mode,
listen_only_mode,
acceptance_filter_mode,
self_test_mode,
/* Command register */
clear_data_overrun,
release_buffer,
abort_tx,
tx_request,
self_rx_request,
single_shot_transmission,
tx_state,
tx_state_q,
overload_request,
overload_frame,
/* Arbitration Lost Capture Register */
read_arbitration_lost_capture_reg,
/* Error Code Capture Register */
read_error_code_capture_reg,
error_capture_code,
/* Bus Timing 0 register */
baud_r_presc,
sync_jump_width,
/* Bus Timing 1 register */
time_segment1,
time_segment2,
triple_sampling,
/* Error Warning Limit register */
error_warning_limit,
/* Rx Error Counter register */
we_rx_err_cnt,
/* Tx Error Counter register */
we_tx_err_cnt,
/* Clock Divider register */
extended_mode,
clkout,
/* This section is for BASIC and EXTENDED mode */
/* Acceptance code register */
acceptance_code_0,
/* Acceptance mask register */
acceptance_mask_0,
/* End: This section is for BASIC and EXTENDED mode */
/* This section is for EXTENDED mode */
/* Acceptance code register */
acceptance_code_1,
acceptance_code_2,
acceptance_code_3,
/* Acceptance mask register */
acceptance_mask_1,
acceptance_mask_2,
acceptance_mask_3,
/* End: This section is for EXTENDED mode */
/* Tx data registers. Holding identifier (basic mode), tx frame information (extended mode) and data */
tx_data_0,
tx_data_1,
tx_data_2,
tx_data_3,
tx_data_4,
tx_data_5,
tx_data_6,
tx_data_7,
tx_data_8,
tx_data_9,
tx_data_10,
tx_data_11,
tx_data_12
/* End: Tx data registers */
);
parameter Tp = 1;
input clk;
input rst;
input cs;
input we;
input [7:0] addr;
input [7:0] data_in;
output [7:0] data_out;
reg [7:0] data_out;
output irq_n;
input sample_point;
input transmitting;
input set_reset_mode;
input node_bus_off;
input error_status;
input [7:0] rx_err_cnt;
input [7:0] tx_err_cnt;
input transmit_status;
input receive_status;
input tx_successful;
input need_to_tx;
input overrun;
input info_empty;
input set_bus_error_irq;
input set_arbitration_lost_irq;
input [4:0] arbitration_lost_capture;
input node_error_passive;
input node_error_active;
input [6:0] rx_message_counter;
/* Mode register */
output reset_mode;
output listen_only_mode;
output acceptance_filter_mode;
output self_test_mode;
/* Command register */
output clear_data_overrun;
output release_buffer;
output abort_tx;
output tx_request;
output self_rx_request;
output single_shot_transmission;
input tx_state;
input tx_state_q;
output overload_request;
input overload_frame;
/* Arbitration Lost Capture Register */
output read_arbitration_lost_capture_reg;
/* Error Code Capture Register */
output read_error_code_capture_reg;
input [7:0] error_capture_code;
/* Bus Timing 0 register */
output [5:0] baud_r_presc;
output [1:0] sync_jump_width;
/* Bus Timing 1 register */
output [3:0] time_segment1;
output [2:0] time_segment2;
output triple_sampling;
/* Error Warning Limit register */
output [7:0] error_warning_limit;
/* Rx Error Counter register */
output we_rx_err_cnt;
/* Tx Error Counter register */
output we_tx_err_cnt;
/* Clock Divider register */
output extended_mode;
output clkout;
/* This section is for BASIC and EXTENDED mode */
/* Acceptance code register */
output [7:0] acceptance_code_0;
/* Acceptance mask register */
output [7:0] acceptance_mask_0;
/* End: This section is for BASIC and EXTENDED mode */
/* This section is for EXTENDED mode */
/* Acceptance code register */
output [7:0] acceptance_code_1;
output [7:0] acceptance_code_2;
output [7:0] acceptance_code_3;
/* Acceptance mask register */
output [7:0] acceptance_mask_1;
output [7:0] acceptance_mask_2;
output [7:0] acceptance_mask_3;
/* End: This section is for EXTENDED mode */
/* Tx data registers. Holding identifier (basic mode), tx frame information (extended mode) and data */
output [7:0] tx_data_0;
output [7:0] tx_data_1;
output [7:0] tx_data_2;
output [7:0] tx_data_3;
output [7:0] tx_data_4;
output [7:0] tx_data_5;
output [7:0] tx_data_6;
output [7:0] tx_data_7;
output [7:0] tx_data_8;
output [7:0] tx_data_9;
output [7:0] tx_data_10;
output [7:0] tx_data_11;
output [7:0] tx_data_12;
/* End: Tx data registers */
reg tx_successful_q;
reg overrun_q;
reg overrun_status;
reg transmission_complete;
reg transmit_buffer_status_q;
reg receive_buffer_status;
reg error_status_q;
reg node_bus_off_q;
reg node_error_passive_q;
reg transmit_buffer_status;
reg single_shot_transmission;
reg self_rx_request;
reg irq_n;
// Some interrupts exist in basic mode and in extended mode. Since they are in different registers they need to be multiplexed.
wire data_overrun_irq_en;
wire error_warning_irq_en;
wire transmit_irq_en;
wire receive_irq_en;
wire [7:0] irq_reg;
wire irq;
wire we_mode = cs & we & (addr == 8'd0);
wire we_command = cs & we & (addr == 8'd1);
wire we_bus_timing_0 = cs & we & (addr == 8'd6) & reset_mode;
wire we_bus_timing_1 = cs & we & (addr == 8'd7) & reset_mode;
wire we_clock_divider_low = cs & we & (addr == 8'd31);
wire we_clock_divider_hi = we_clock_divider_low & reset_mode;
wire read = cs & (~we);
wire read_irq_reg = read & (addr == 8'd3);
assign read_arbitration_lost_capture_reg = read & extended_mode & (addr == 8'd11);
assign read_error_code_capture_reg = read & extended_mode & (addr == 8'd12);
/* This section is for BASIC and EXTENDED mode */
wire we_acceptance_code_0 = cs & we & reset_mode & ((~extended_mode) & (addr == 8'd4) | extended_mode & (addr == 8'd16));
wire we_acceptance_mask_0 = cs & we & reset_mode & ((~extended_mode) & (addr == 8'd5) | extended_mode & (addr == 8'd20));
wire we_tx_data_0 = cs & we & (~reset_mode) & ((~extended_mode) & (addr == 8'd10) | extended_mode & (addr == 8'd16)) & transmit_buffer_status;
wire we_tx_data_1 = cs & we & (~reset_mode) & ((~extended_mode) & (addr == 8'd11) | extended_mode & (addr == 8'd17)) & transmit_buffer_status;
wire we_tx_data_2 = cs & we & (~reset_mode) & ((~extended_mode) & (addr == 8'd12) | extended_mode & (addr == 8'd18)) & transmit_buffer_status;
wire we_tx_data_3 = cs & we & (~reset_mode) & ((~extended_mode) & (addr == 8'd13) | extended_mode & (addr == 8'd19)) & transmit_buffer_status;
wire we_tx_data_4 = cs & we & (~reset_mode) & ((~extended_mode) & (addr == 8'd14) | extended_mode & (addr == 8'd20)) & transmit_buffer_status;
wire we_tx_data_5 = cs & we & (~reset_mode) & ((~extended_mode) & (addr == 8'd15) | extended_mode & (addr == 8'd21)) & transmit_buffer_status;
wire we_tx_data_6 = cs & we & (~reset_mode) & ((~extended_mode) & (addr == 8'd16) | extended_mode & (addr == 8'd22)) & transmit_buffer_status;
wire we_tx_data_7 = cs & we & (~reset_mode) & ((~extended_mode) & (addr == 8'd17) | extended_mode & (addr == 8'd23)) & transmit_buffer_status;
wire we_tx_data_8 = cs & we & (~reset_mode) & ((~extended_mode) & (addr == 8'd18) | extended_mode & (addr == 8'd24)) & transmit_buffer_status;
wire we_tx_data_9 = cs & we & (~reset_mode) & ((~extended_mode) & (addr == 8'd19) | extended_mode & (addr == 8'd25)) & transmit_buffer_status;
wire we_tx_data_10 = cs & we & (~reset_mode) & ( extended_mode & (addr == 8'd26)) & transmit_buffer_status;
wire we_tx_data_11 = cs & we & (~reset_mode) & ( extended_mode & (addr == 8'd27)) & transmit_buffer_status;
wire we_tx_data_12 = cs & we & (~reset_mode) & ( extended_mode & (addr == 8'd28)) & transmit_buffer_status;
/* End: This section is for BASIC and EXTENDED mode */
/* This section is for EXTENDED mode */
wire we_interrupt_enable = cs & we & (addr == 8'd4) & extended_mode;
wire we_error_warning_limit = cs & we & (addr == 8'd13) & reset_mode & extended_mode;
assign we_rx_err_cnt = cs & we & (addr == 8'd14) & reset_mode & extended_mode;
assign we_tx_err_cnt = cs & we & (addr == 8'd15) & reset_mode & extended_mode;
wire we_acceptance_code_1 = cs & we & (addr == 8'd17) & reset_mode & extended_mode;
wire we_acceptance_code_2 = cs & we & (addr == 8'd18) & reset_mode & extended_mode;
wire we_acceptance_code_3 = cs & we & (addr == 8'd19) & reset_mode & extended_mode;
wire we_acceptance_mask_1 = cs & we & (addr == 8'd21) & reset_mode & extended_mode;
wire we_acceptance_mask_2 = cs & we & (addr == 8'd22) & reset_mode & extended_mode;
wire we_acceptance_mask_3 = cs & we & (addr == 8'd23) & reset_mode & extended_mode;
/* End: This section is for EXTENDED mode */
always @ (posedge clk)
begin
tx_successful_q <=#Tp tx_successful;
overrun_q <=#Tp overrun;
transmit_buffer_status_q <=#Tp transmit_buffer_status;
error_status_q <=#Tp error_status;
node_bus_off_q <=#Tp node_bus_off;
node_error_passive_q <=#Tp node_error_passive;
end
/* Mode register */
wire [0:0] mode;
wire [4:1] mode_basic;
wire [3:1] mode_ext;
wire receive_irq_en_basic;
wire transmit_irq_en_basic;
wire error_irq_en_basic;
wire overrun_irq_en_basic;
can_register_asyn_syn #(1, 1'h1) MODE_REG0
( .data_in(data_in[0]),
.data_out(mode[0]),
.we(we_mode),
.clk(clk),
.rst(rst),
.rst_sync(set_reset_mode)
);
can_register_asyn #(4, 0) MODE_REG_BASIC
( .data_in(data_in[4:1]),
.data_out(mode_basic[4:1]),
.we(we_mode),
.clk(clk),
.rst(rst)
);
can_register_asyn #(3, 0) MODE_REG_EXT
( .data_in(data_in[3:1]),
.data_out(mode_ext[3:1]),
.we(we_mode & reset_mode),
.clk(clk),
.rst(rst)
);
assign reset_mode = mode[0];
assign listen_only_mode = extended_mode & mode_ext[1];
assign self_test_mode = extended_mode & mode_ext[2];
assign acceptance_filter_mode = extended_mode & mode_ext[3];
assign receive_irq_en_basic = mode_basic[1];
assign transmit_irq_en_basic = mode_basic[2];
assign error_irq_en_basic = mode_basic[3];
assign overrun_irq_en_basic = mode_basic[4];
/* End Mode register */
/* Command register */
wire [4:0] command;
can_register_asyn_syn #(1, 1'h0) COMMAND_REG0
( .data_in(data_in[0]),
.data_out(command[0]),
.we(we_command),
.clk(clk),
.rst(rst),
.rst_sync(command[0] & sample_point | reset_mode)
);
can_register_asyn_syn #(1, 1'h0) COMMAND_REG1
( .data_in(data_in[1]),
.data_out(command[1]),
.we(we_command),
.clk(clk),
.rst(rst),
.rst_sync(sample_point & (tx_request | (abort_tx & ~transmitting)) | reset_mode)
);
can_register_asyn_syn #(2, 2'h0) COMMAND_REG
( .data_in(data_in[3:2]),
.data_out(command[3:2]),
.we(we_command),
.clk(clk),
.rst(rst),
.rst_sync(|command[3:2] | reset_mode)
);
can_register_asyn_syn #(1, 1'h0) COMMAND_REG4
( .data_in(data_in[4]),
.data_out(command[4]),
.we(we_command),
.clk(clk),
.rst(rst),
.rst_sync(command[4] & sample_point | reset_mode)
);
always @ (posedge clk or posedge rst)
begin
if (rst)
self_rx_request <= 1'b0;
else if (command[4] & (~command[0]))
self_rx_request <=#Tp 1'b1;
else if ((~tx_state) & tx_state_q)
self_rx_request <=#Tp 1'b0;
end
assign clear_data_overrun = command[3];
assign release_buffer = command[2];
assign tx_request = command[0] | command[4];
assign abort_tx = command[1] & (~tx_request);
always @ (posedge clk or posedge rst)
begin
if (rst)
single_shot_transmission <= 1'b0;
else if (tx_request & command[1] & sample_point)
single_shot_transmission <=#Tp 1'b1;
else if ((~tx_state) & tx_state_q)
single_shot_transmission <=#Tp 1'b0;
end
/*
can_register_asyn_syn #(1, 1'h0) COMMAND_REG_OVERLOAD // Uncomment this to enable overload requests !!!
( .data_in(data_in[5]),
.data_out(overload_request),
.we(we_command),
.clk(clk),
.rst(rst),
.rst_sync(overload_frame & ~overload_frame_q)
);
reg overload_frame_q;
always @ (posedge clk or posedge rst)
begin
if (rst)
overload_frame_q <= 1'b0;
else
overload_frame_q <=#Tp overload_frame;
end
*/
assign overload_request = 0; // Overload requests are not supported, yet !!!
/* End Command register */
/* Status register */
wire [7:0] status;
assign status[7] = node_bus_off;
assign status[6] = error_status;
assign status[5] = transmit_status;
assign status[4] = receive_status;
assign status[3] = transmission_complete;
assign status[2] = transmit_buffer_status;
assign status[1] = overrun_status;
assign status[0] = receive_buffer_status;
always @ (posedge clk or posedge rst)
begin
if (rst)
transmission_complete <= 1'b1;
else if (tx_successful & (~tx_successful_q) | abort_tx)
transmission_complete <=#Tp 1'b1;
else if (tx_request)
transmission_complete <=#Tp 1'b0;
end
always @ (posedge clk or posedge rst)
begin
if (rst)
transmit_buffer_status <= 1'b1;
else if (tx_request)
transmit_buffer_status <=#Tp 1'b0;
else if (reset_mode || !need_to_tx)
transmit_buffer_status <=#Tp 1'b1;
end
always @ (posedge clk or posedge rst)
begin
if (rst)
overrun_status <= 1'b0;
else if (overrun & (~overrun_q))
overrun_status <=#Tp 1'b1;
else if (reset_mode || clear_data_overrun)
overrun_status <=#Tp 1'b0;
end
always @ (posedge clk or posedge rst)
begin
if (rst)
receive_buffer_status <= 1'b0;
else if (reset_mode || release_buffer)
receive_buffer_status <=#Tp 1'b0;
else if (~info_empty)
receive_buffer_status <=#Tp 1'b1;
end
/* End Status register */
/* Interrupt Enable register (extended mode) */
wire [7:0] irq_en_ext;
wire bus_error_irq_en;
wire arbitration_lost_irq_en;
wire error_passive_irq_en;
wire data_overrun_irq_en_ext;
wire error_warning_irq_en_ext;
wire transmit_irq_en_ext;
wire receive_irq_en_ext;
can_register #(8) IRQ_EN_REG
( .data_in(data_in),
.data_out(irq_en_ext),
.we(we_interrupt_enable),
.clk(clk)
);
assign bus_error_irq_en = irq_en_ext[7];
assign arbitration_lost_irq_en = irq_en_ext[6];
assign error_passive_irq_en = irq_en_ext[5];
assign data_overrun_irq_en_ext = irq_en_ext[3];
assign error_warning_irq_en_ext = irq_en_ext[2];
assign transmit_irq_en_ext = irq_en_ext[1];
assign receive_irq_en_ext = irq_en_ext[0];
/* End Bus Timing 0 register */
/* Bus Timing 0 register */
wire [7:0] bus_timing_0;
can_register #(8) BUS_TIMING_0_REG
( .data_in(data_in),
.data_out(bus_timing_0),
.we(we_bus_timing_0),
.clk(clk)
);
assign baud_r_presc = bus_timing_0[5:0];
assign sync_jump_width = bus_timing_0[7:6];
/* End Bus Timing 0 register */
/* Bus Timing 1 register */
wire [7:0] bus_timing_1;
can_register #(8) BUS_TIMING_1_REG
( .data_in(data_in),
.data_out(bus_timing_1),
.we(we_bus_timing_1),
.clk(clk)
);
assign time_segment1 = bus_timing_1[3:0];
assign time_segment2 = bus_timing_1[6:4];
assign triple_sampling = bus_timing_1[7];
/* End Bus Timing 1 register */
/* Error Warning Limit register */
can_register_asyn #(8, 96) ERROR_WARNING_REG
( .data_in(data_in),
.data_out(error_warning_limit),
.we(we_error_warning_limit),
.clk(clk),
.rst(rst)
);
/* End Error Warning Limit register */
/* Clock Divider register */
wire [7:0] clock_divider;
wire clock_off;
wire [2:0] cd;
reg [2:0] clkout_div;
reg [2:0] clkout_cnt;
reg clkout_tmp;
can_register_asyn #(1, 0) CLOCK_DIVIDER_REG_7
( .data_in(data_in[7]),
.data_out(clock_divider[7]),
.we(we_clock_divider_hi),
.clk(clk),
.rst(rst)
);
assign clock_divider[6:4] = 3'h0;
can_register_asyn #(1, 0) CLOCK_DIVIDER_REG_3
( .data_in(data_in[3]),
.data_out(clock_divider[3]),
.we(we_clock_divider_hi),
.clk(clk),
.rst(rst)
);
can_register_asyn #(3, 0) CLOCK_DIVIDER_REG_LOW
( .data_in(data_in[2:0]),
.data_out(clock_divider[2:0]),
.we(we_clock_divider_low),
.clk(clk),
.rst(rst)
);
assign extended_mode = clock_divider[7];
assign clock_off = clock_divider[3];
assign cd[2:0] = clock_divider[2:0];
always @ (cd)
begin
case (cd) /* synthesis full_case parallel_case */
3'b000 : clkout_div = 3'd0;
3'b001 : clkout_div = 3'd1;
3'b010 : clkout_div = 3'd2;
3'b011 : clkout_div = 3'd3;
3'b100 : clkout_div = 3'd4;
3'b101 : clkout_div = 3'd5;
3'b110 : clkout_div = 3'd6;
3'b111 : clkout_div = 3'd0;
endcase
end
always @ (posedge clk or posedge rst)
begin
if (rst)
clkout_cnt <= 3'h0;
else if (clkout_cnt == clkout_div)
clkout_cnt <=#Tp 3'h0;
else
clkout_cnt <= clkout_cnt + 1'b1;
end
always @ (posedge clk or posedge rst)
begin
if (rst)
clkout_tmp <= 1'b0;
else if (clkout_cnt == clkout_div)
clkout_tmp <=#Tp ~clkout_tmp;
end
assign clkout = clock_off ? 1'b1 : ((&cd)? clk : clkout_tmp);
/* End Clock Divider register */
/* This section is for BASIC and EXTENDED mode */
/* Acceptance code register */
can_register #(8) ACCEPTANCE_CODE_REG0
( .data_in(data_in),
.data_out(acceptance_code_0),
.we(we_acceptance_code_0),
.clk(clk)
);
/* End: Acceptance code register */
/* Acceptance mask register */
can_register #(8) ACCEPTANCE_MASK_REG0
( .data_in(data_in),
.data_out(acceptance_mask_0),
.we(we_acceptance_mask_0),
.clk(clk)
);
/* End: Acceptance mask register */
/* End: This section is for BASIC and EXTENDED mode */
/* Tx data 0 register. */
can_register #(8) TX_DATA_REG0
( .data_in(data_in),
.data_out(tx_data_0),
.we(we_tx_data_0),
.clk(clk)
);
/* End: Tx data 0 register. */
/* Tx data 1 register. */
can_register #(8) TX_DATA_REG1
( .data_in(data_in),
.data_out(tx_data_1),
.we(we_tx_data_1),
.clk(clk)
);
/* End: Tx data 1 register. */
/* Tx data 2 register. */
can_register #(8) TX_DATA_REG2
( .data_in(data_in),
.data_out(tx_data_2),
.we(we_tx_data_2),
.clk(clk)
);
/* End: Tx data 2 register. */
/* Tx data 3 register. */
can_register #(8) TX_DATA_REG3
( .data_in(data_in),
.data_out(tx_data_3),
.we(we_tx_data_3),
.clk(clk)
);
/* End: Tx data 3 register. */
/* Tx data 4 register. */
can_register #(8) TX_DATA_REG4
( .data_in(data_in),
.data_out(tx_data_4),
.we(we_tx_data_4),
.clk(clk)
);
/* End: Tx data 4 register. */
/* Tx data 5 register. */
can_register #(8) TX_DATA_REG5
( .data_in(data_in),
.data_out(tx_data_5),
.we(we_tx_data_5),
.clk(clk)
);
/* End: Tx data 5 register. */
/* Tx data 6 register. */
can_register #(8) TX_DATA_REG6
( .data_in(data_in),
.data_out(tx_data_6),
.we(we_tx_data_6),
.clk(clk)
);
/* End: Tx data 6 register. */
/* Tx data 7 register. */
can_register #(8) TX_DATA_REG7
( .data_in(data_in),
.data_out(tx_data_7),
.we(we_tx_data_7),
.clk(clk)
);
/* End: Tx data 7 register. */
/* Tx data 8 register. */
can_register #(8) TX_DATA_REG8
( .data_in(data_in),
.data_out(tx_data_8),
.we(we_tx_data_8),
.clk(clk)
);
/* End: Tx data 8 register. */
/* Tx data 9 register. */
can_register #(8) TX_DATA_REG9
( .data_in(data_in),
.data_out(tx_data_9),
.we(we_tx_data_9),
.clk(clk)
);
/* End: Tx data 9 register. */
/* Tx data 10 register. */
can_register #(8) TX_DATA_REG10
( .data_in(data_in),
.data_out(tx_data_10),
.we(we_tx_data_10),
.clk(clk)
);
/* End: Tx data 10 register. */
/* Tx data 11 register. */
can_register #(8) TX_DATA_REG11
( .data_in(data_in),
.data_out(tx_data_11),
.we(we_tx_data_11),
.clk(clk)
);
/* End: Tx data 11 register. */
/* Tx data 12 register. */
can_register #(8) TX_DATA_REG12
( .data_in(data_in),
.data_out(tx_data_12),
.we(we_tx_data_12),
.clk(clk)
);
/* End: Tx data 12 register. */
/* This section is for EXTENDED mode */
/* Acceptance code register 1 */
can_register #(8) ACCEPTANCE_CODE_REG1
( .data_in(data_in),
.data_out(acceptance_code_1),
.we(we_acceptance_code_1),
.clk(clk)
);
/* End: Acceptance code register */
/* Acceptance code register 2 */
can_register #(8) ACCEPTANCE_CODE_REG2
( .data_in(data_in),
.data_out(acceptance_code_2),
.we(we_acceptance_code_2),
.clk(clk)
);
/* End: Acceptance code register */
/* Acceptance code register 3 */
can_register #(8) ACCEPTANCE_CODE_REG3
( .data_in(data_in),
.data_out(acceptance_code_3),
.we(we_acceptance_code_3),
.clk(clk)
);
/* End: Acceptance code register */
/* Acceptance mask register 1 */
can_register #(8) ACCEPTANCE_MASK_REG1
( .data_in(data_in),
.data_out(acceptance_mask_1),
.we(we_acceptance_mask_1),
.clk(clk)
);
/* End: Acceptance code register */
/* Acceptance mask register 2 */
can_register #(8) ACCEPTANCE_MASK_REG2
( .data_in(data_in),
.data_out(acceptance_mask_2),
.we(we_acceptance_mask_2),
.clk(clk)
);
/* End: Acceptance code register */
/* Acceptance mask register 3 */
can_register #(8) ACCEPTANCE_MASK_REG3
( .data_in(data_in),
.data_out(acceptance_mask_3),
.we(we_acceptance_mask_3),
.clk(clk)
);
/* End: Acceptance code register */
/* End: This section is for EXTENDED mode */
// Reading data from registers
always @ ( addr or extended_mode or mode or bus_timing_0 or bus_timing_1 or clock_divider or
acceptance_code_0 or acceptance_code_1 or acceptance_code_2 or acceptance_code_3 or
acceptance_mask_0 or acceptance_mask_1 or acceptance_mask_2 or acceptance_mask_3 or
reset_mode or tx_data_0 or tx_data_1 or tx_data_2 or tx_data_3 or tx_data_4 or
tx_data_5 or tx_data_6 or tx_data_7 or tx_data_8 or tx_data_9 or status or
error_warning_limit or rx_err_cnt or tx_err_cnt or irq_en_ext or irq_reg or mode_ext or
arbitration_lost_capture or rx_message_counter or mode_basic or error_capture_code
)
begin
case({extended_mode, addr[4:0]}) /* synthesis parallel_case */
{1'h1, 5'd00} : data_out = {4'b0000, mode_ext[3:1], mode[0]}; // extended mode
{1'h1, 5'd01} : data_out = 8'h0; // extended mode
{1'h1, 5'd02} : data_out = status; // extended mode
{1'h1, 5'd03} : data_out = irq_reg; // extended mode
{1'h1, 5'd04} : data_out = irq_en_ext; // extended mode
{1'h1, 5'd06} : data_out = bus_timing_0; // extended mode
{1'h1, 5'd07} : data_out = bus_timing_1; // extended mode
{1'h1, 5'd11} : data_out = {3'h0, arbitration_lost_capture[4:0]}; // extended mode
{1'h1, 5'd12} : data_out = error_capture_code; // extended mode
{1'h1, 5'd13} : data_out = error_warning_limit; // extended mode
{1'h1, 5'd14} : data_out = rx_err_cnt; // extended mode
{1'h1, 5'd15} : data_out = tx_err_cnt; // extended mode
{1'h1, 5'd16} : data_out = acceptance_code_0; // extended mode
{1'h1, 5'd17} : data_out = acceptance_code_1; // extended mode
{1'h1, 5'd18} : data_out = acceptance_code_2; // extended mode
{1'h1, 5'd19} : data_out = acceptance_code_3; // extended mode
{1'h1, 5'd20} : data_out = acceptance_mask_0; // extended mode
{1'h1, 5'd21} : data_out = acceptance_mask_1; // extended mode
{1'h1, 5'd22} : data_out = acceptance_mask_2; // extended mode
{1'h1, 5'd23} : data_out = acceptance_mask_3; // extended mode
{1'h1, 5'd24} : data_out = 8'h0; // extended mode
{1'h1, 5'd25} : data_out = 8'h0; // extended mode
{1'h1, 5'd26} : data_out = 8'h0; // extended mode
{1'h1, 5'd27} : data_out = 8'h0; // extended mode
{1'h1, 5'd28} : data_out = 8'h0; // extended mode
{1'h1, 5'd29} : data_out = {1'b0, rx_message_counter}; // extended mode
{1'h1, 5'd31} : data_out = clock_divider; // extended mode
{1'h0, 5'd00} : data_out = {3'b001, mode_basic[4:1], mode[0]}; // basic mode
{1'h0, 5'd01} : data_out = 8'hff; // basic mode
{1'h0, 5'd02} : data_out = status; // basic mode
{1'h0, 5'd03} : data_out = {4'hf, irq_reg[3:0]}; // basic mode
{1'h0, 5'd04} : data_out = reset_mode? acceptance_code_0 : 8'hff; // basic mode
{1'h0, 5'd05} : data_out = reset_mode? acceptance_mask_0 : 8'hff; // basic mode
{1'h0, 5'd06} : data_out = reset_mode? bus_timing_0 : 8'hff; // basic mode
{1'h0, 5'd07} : data_out = reset_mode? bus_timing_1 : 8'hff; // basic mode
{1'h0, 5'd10} : data_out = reset_mode? 8'hff : tx_data_0; // basic mode
{1'h0, 5'd11} : data_out = reset_mode? 8'hff : tx_data_1; // basic mode
{1'h0, 5'd12} : data_out = reset_mode? 8'hff : tx_data_2; // basic mode
{1'h0, 5'd13} : data_out = reset_mode? 8'hff : tx_data_3; // basic mode
{1'h0, 5'd14} : data_out = reset_mode? 8'hff : tx_data_4; // basic mode
{1'h0, 5'd15} : data_out = reset_mode? 8'hff : tx_data_5; // basic mode
{1'h0, 5'd16} : data_out = reset_mode? 8'hff : tx_data_6; // basic mode
{1'h0, 5'd17} : data_out = reset_mode? 8'hff : tx_data_7; // basic mode
{1'h0, 5'd18} : data_out = reset_mode? 8'hff : tx_data_8; // basic mode
{1'h0, 5'd19} : data_out = reset_mode? 8'hff : tx_data_9; // basic mode
{1'h0, 5'd31} : data_out = clock_divider; // basic mode
default : data_out = 8'h0; // the rest is read as 0
endcase
end
// Some interrupts exist in basic mode and in extended mode. Since they are in different registers they need to be multiplexed.
assign data_overrun_irq_en = extended_mode ? data_overrun_irq_en_ext : overrun_irq_en_basic;
assign error_warning_irq_en = extended_mode ? error_warning_irq_en_ext : error_irq_en_basic;
assign transmit_irq_en = extended_mode ? transmit_irq_en_ext : transmit_irq_en_basic;
assign receive_irq_en = extended_mode ? receive_irq_en_ext : receive_irq_en_basic;
reg data_overrun_irq;
always @ (posedge clk or posedge rst)
begin
if (rst)
data_overrun_irq <= 1'b0;
else if (overrun & (~overrun_q) & data_overrun_irq_en)
data_overrun_irq <=#Tp 1'b1;
else if (reset_mode || read_irq_reg)
data_overrun_irq <=#Tp 1'b0;
end
reg transmit_irq;
always @ (posedge clk or posedge rst)
begin
if (rst)
transmit_irq <= 1'b0;
else if (reset_mode || read_irq_reg)
transmit_irq <=#Tp 1'b0;
else if (transmit_buffer_status & (~transmit_buffer_status_q) & transmit_irq_en)
transmit_irq <=#Tp 1'b1;
end
reg receive_irq;
always @ (posedge clk or posedge rst)
begin
if (rst)
receive_irq <= 1'b0;
else if ((~info_empty) & (~receive_irq) & receive_irq_en)
receive_irq <=#Tp 1'b1;
else if (reset_mode || release_buffer)
receive_irq <=#Tp 1'b0;
end
reg error_irq;
always @ (posedge clk or posedge rst)
begin
if (rst)
error_irq <= 1'b0;
else if (((error_status ^ error_status_q) | (node_bus_off ^ node_bus_off_q)) & error_warning_irq_en)
error_irq <=#Tp 1'b1;
else if (read_irq_reg)
error_irq <=#Tp 1'b0;
end
reg bus_error_irq;
always @ (posedge clk or posedge rst)
begin
if (rst)
bus_error_irq <= 1'b0;
else if (set_bus_error_irq & bus_error_irq_en)
bus_error_irq <=#Tp 1'b1;
else if (reset_mode || read_irq_reg)
bus_error_irq <=#Tp 1'b0;
end
reg arbitration_lost_irq;
always @ (posedge clk or posedge rst)
begin
if (rst)
arbitration_lost_irq <= 1'b0;
else if (set_arbitration_lost_irq & arbitration_lost_irq_en)
arbitration_lost_irq <=#Tp 1'b1;
else if (reset_mode || read_irq_reg)
arbitration_lost_irq <=#Tp 1'b0;
end
reg error_passive_irq;
always @ (posedge clk or posedge rst)
begin
if (rst)
error_passive_irq <= 1'b0;
else if ((node_error_passive & (~node_error_passive_q) | (~node_error_passive) & node_error_passive_q & node_error_active) & error_passive_irq_en)
error_passive_irq <=#Tp 1'b1;
else if (reset_mode || read_irq_reg)
error_passive_irq <=#Tp 1'b0;
end
assign irq_reg = {bus_error_irq, arbitration_lost_irq, error_passive_irq, 1'b0, data_overrun_irq, error_irq, transmit_irq, receive_irq};
assign irq = data_overrun_irq | transmit_irq | receive_irq | error_irq | bus_error_irq | arbitration_lost_irq | error_passive_irq;
always @ (posedge clk or posedge rst)
begin
if (rst)
irq_n <= 1'b1;
else if (read_irq_reg)
irq_n <=#Tp 1'b1;
else if (irq)
irq_n <=#Tp 1'b0;
end
endmodule
|
// Settings for TX FIFO
`define ETH_TX_FIFO_CNT_WIDTH 5
`define ETH_TX_FIFO_DEPTH 16
`define ETH_TX_FIFO_DATA_WIDTH 32
// Settings for RX FIFO
`define ETH_RX_FIFO_CNT_WIDTH 5
`define ETH_RX_FIFO_DEPTH 16
`define ETH_RX_FIFO_DATA_WIDTH 32
// Burst length
`define ETH_BURST_LENGTH 8 // Change also ETH_BURST_CNT_WIDTH
`define ETH_BURST_CNT_WIDTH 4 // The counter must be width enough to count to ETH_BURST_LENGTH
// WISHBONE interface is Revision B3 compliant (uncomment when needed)
`define ETH_WISHBONE_B3
//////////////////////////////////////////////////////////////////////
//// ////
//// eth_defines.v ////
//// ////
//// This file is part of the Ethernet IP core project ////
//// http://www.opencores.org/projects/ethmac/ ////
//// ////
//// Author(s): ////
//// - Igor Mohor ([email protected]) ////
//// ////
//// All additional information is available in the Readme.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001, 2002 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: eth_defines.v,v $
// Revision 1.33 2003/11/12 18:24:58 tadejm
// WISHBONE slave changed and tested from only 32-bit accesss to byte access.
//
// Revision 1.32 2003/10/17 07:46:13 markom
// mbist signals updated according to newest convention
//
// Revision 1.31 2003/08/14 16:42:58 simons
// Artisan ram instance added.
//
// Revision 1.30 2003/06/13 11:55:37 mohor
// Define file in eth_cop.v is changed to eth_defines.v. Some defines were
// moved from tb_eth_defines.v to eth_defines.v.
//
// Revision 1.29 2002/11/19 18:13:49 mohor
// r_MiiMRst is not used for resetting the MIIM module. wb_rst used instead.
//
// Revision 1.28 2002/11/15 14:27:15 mohor
// Since r_Rst bit is not used any more, default value is changed to 0xa000.
//
// Revision 1.27 2002/11/01 18:19:34 mohor
// Defines fixed to use generic RAM by default.
//
// Revision 1.26 2002/10/24 18:53:03 mohor
// fpga define added.
//
// Revision 1.3 2002/10/11 16:57:54 igorm
// eth_defines.v tagged with rel_5 used.
//
// Revision 1.25 2002/10/10 16:47:44 mohor
// Defines changed to have ETH_ prolog.
// ETH_WISHBONE_B# define added.
//
// Revision 1.24 2002/10/10 16:33:11 mohor
// Bist added.
//
// Revision 1.23 2002/09/23 18:22:48 mohor
// Virtual Silicon RAM might be used in the ASIC implementation of the ethernet
// core.
//
// Revision 1.22 2002/09/04 18:36:49 mohor
// Defines for control registers added (ETH_TXCTRL and ETH_RXCTRL).
//
// Revision 1.21 2002/08/16 22:09:47 mohor
// Defines for register width added. mii_rst signal in MIIMODER register
// changed.
//
// Revision 1.20 2002/08/14 19:31:48 mohor
// Register TX_BD_NUM is changed so it contains value of the Tx buffer descriptors. No
// need to multiply or devide any more.
//
// Revision 1.19 2002/07/23 15:28:31 mohor
// Ram , used for BDs changed from generic_spram to eth_spram_256x32.
//
// Revision 1.18 2002/05/03 10:15:50 mohor
// Outputs registered. Reset changed for eth_wishbone module.
//
// Revision 1.17 2002/04/24 08:52:19 mohor
// Compiler directives added. Tx and Rx fifo size incremented. A "late collision"
// bug fixed.
//
// Revision 1.16 2002/03/19 12:53:29 mohor
// Some defines that are used in testbench only were moved to tb_eth_defines.v
// file.
//
// Revision 1.15 2002/02/26 16:11:32 mohor
// Number of interrupts changed
//
// Revision 1.14 2002/02/16 14:03:44 mohor
// Registered trimmed. Unused registers removed.
//
// Revision 1.13 2002/02/16 13:06:33 mohor
// EXTERNAL_DMA used instead of WISHBONE_DMA.
//
// Revision 1.12 2002/02/15 10:58:31 mohor
// Changed that were lost with last update put back to the file.
//
// Revision 1.11 2002/02/14 20:19:41 billditt
// Modified for Address Checking,
// addition of eth_addrcheck.v
//
// Revision 1.10 2002/02/12 17:01:19 mohor
// HASH0 and HASH1 registers added.
// Revision 1.9 2002/02/08 16:21:54 mohor
// Rx status is written back to the BD.
//
// Revision 1.8 2002/02/05 16:44:38 mohor
// Both rx and tx part are finished. Tested with wb_clk_i between 10 and 200
// MHz. Statuses, overrun, control frame transmission and reception still need
// to be fixed.
//
// Revision 1.7 2002/01/23 10:28:16 mohor
// Link in the header changed.
//
// Revision 1.6 2001/12/05 15:00:16 mohor
// RX_BD_NUM changed to TX_BD_NUM (holds number of TX descriptors
// instead of the number of RX descriptors).
//
// Revision 1.5 2001/12/05 10:21:37 mohor
// ETH_RX_BD_ADR register deleted. ETH_RX_BD_NUM is used instead.
//
// Revision 1.4 2001/11/13 14:23:56 mohor
// Generic memory model is used. Defines are changed for the same reason.
//
// Revision 1.3 2001/10/18 12:07:11 mohor
// Status signals changed, Adress decoding changed, interrupt controller
// added.
//
// Revision 1.2 2001/09/24 15:02:56 mohor
// Defines changed (All precede with ETH_). Small changes because some
// tools generate warnings when two operands are together. Synchronization
// between two clocks domains in eth_wishbonedma.v is changed (due to ASIC
// demands).
//
// Revision 1.1 2001/08/06 14:44:29 mohor
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
// Include files fixed to contain no path.
// File names and module names changed ta have a eth_ prologue in the name.
// File eth_timescale.v is used to define timescale
// All pin names on the top module are changed to contain _I, _O or _OE at the end.
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
// and Mdo_OE. The bidirectional signal must be created on the top level. This
// is done due to the ASIC tools.
//
// Revision 1.1 2001/07/30 21:23:42 mohor
// Directory structure changed. Files checked and joind together.
//
//
//
//
//
//`define ETH_BIST // Bist for usage with Virtual Silicon RAMS
`define ETH_MBIST_CTRL_WIDTH 3 // width of MBIST control bus
// Ethernet implemented in Xilinx Chips
// `define ETH_FIFO_XILINX // Use Xilinx distributed ram for tx and rx fifo
// `define ETH_XILINX_RAMB4 // Selection of the used memory for Buffer descriptors
// Core is going to be implemented in Virtex FPGA and contains Virtex
// specific elements.
// Ethernet implemented in ASIC with Virtual Silicon RAMs
// `define ETH_VIRTUAL_SILICON_RAM // Virtual Silicon RAMS used storing buffer decriptors (ASIC implementation)
// `define ETH_ARTISAN_RAM // Artisan RAMS used storing buffer decriptors (ASIC implementation)
`define ETH_MODER_ADR 8'h0 // 0x0
`define ETH_INT_SOURCE_ADR 8'h1 // 0x4
`define ETH_INT_MASK_ADR 8'h2 // 0x8
`define ETH_IPGT_ADR 8'h3 // 0xC
`define ETH_IPGR1_ADR 8'h4 // 0x10
`define ETH_IPGR2_ADR 8'h5 // 0x14
`define ETH_PACKETLEN_ADR 8'h6 // 0x18
`define ETH_COLLCONF_ADR 8'h7 // 0x1C
`define ETH_TX_BD_NUM_ADR 8'h8 // 0x20
`define ETH_CTRLMODER_ADR 8'h9 // 0x24
`define ETH_MIIMODER_ADR 8'hA // 0x28
`define ETH_MIICOMMAND_ADR 8'hB // 0x2C
`define ETH_MIIADDRESS_ADR 8'hC // 0x30
`define ETH_MIITX_DATA_ADR 8'hD // 0x34
`define ETH_MIIRX_DATA_ADR 8'hE // 0x38
`define ETH_MIISTATUS_ADR 8'hF // 0x3C
`define ETH_MAC_ADDR0_ADR 8'h10 // 0x40
`define ETH_MAC_ADDR1_ADR 8'h11 // 0x44
`define ETH_HASH0_ADR 8'h12 // 0x48
`define ETH_HASH1_ADR 8'h13 // 0x4C
`define ETH_TX_CTRL_ADR 8'h14 // 0x50
`define ETH_RX_CTRL_ADR 8'h15 // 0x54
`define ETH_MODER_DEF_0 8'h00
`define ETH_MODER_DEF_1 8'hA0
`define ETH_MODER_DEF_2 1'h0
`define ETH_INT_MASK_DEF_0 7'h0
`define ETH_IPGT_DEF_0 7'h12
`define ETH_IPGR1_DEF_0 7'h0C
`define ETH_IPGR2_DEF_0 7'h12
`define ETH_PACKETLEN_DEF_0 8'h00
`define ETH_PACKETLEN_DEF_1 8'h06
`define ETH_PACKETLEN_DEF_2 8'h40
`define ETH_PACKETLEN_DEF_3 8'h00
`define ETH_COLLCONF_DEF_0 6'h3f
`define ETH_COLLCONF_DEF_2 4'hF
`define ETH_TX_BD_NUM_DEF_0 8'h40
`define ETH_CTRLMODER_DEF_0 3'h0
`define ETH_MIIMODER_DEF_0 8'h64
`define ETH_MIIMODER_DEF_1 1'h0
`define ETH_MIIADDRESS_DEF_0 5'h00
`define ETH_MIIADDRESS_DEF_1 5'h00
`define ETH_MIITX_DATA_DEF_0 8'h00
`define ETH_MIITX_DATA_DEF_1 8'h00
`define ETH_MIIRX_DATA_DEF 16'h0000 // not written from WB
`define ETH_MAC_ADDR0_DEF_0 8'h00
`define ETH_MAC_ADDR0_DEF_1 8'h00
`define ETH_MAC_ADDR0_DEF_2 8'h00
`define ETH_MAC_ADDR0_DEF_3 8'h00
`define ETH_MAC_ADDR1_DEF_0 8'h00
`define ETH_MAC_ADDR1_DEF_1 8'h00
`define ETH_HASH0_DEF_0 8'h00
`define ETH_HASH0_DEF_1 8'h00
`define ETH_HASH0_DEF_2 8'h00
`define ETH_HASH0_DEF_3 8'h00
`define ETH_HASH1_DEF_0 8'h00
`define ETH_HASH1_DEF_1 8'h00
`define ETH_HASH1_DEF_2 8'h00
`define ETH_HASH1_DEF_3 8'h00
`define ETH_TX_CTRL_DEF_0 8'h00 //
`define ETH_TX_CTRL_DEF_1 8'h00 //
`define ETH_TX_CTRL_DEF_2 1'h0 //
`define ETH_RX_CTRL_DEF_0 8'h00
`define ETH_RX_CTRL_DEF_1 8'h00
`define ETH_MODER_WIDTH_0 8
`define ETH_MODER_WIDTH_1 8
`define ETH_MODER_WIDTH_2 1
`define ETH_INT_SOURCE_WIDTH_0 7
`define ETH_INT_MASK_WIDTH_0 7
`define ETH_IPGT_WIDTH_0 7
`define ETH_IPGR1_WIDTH_0 7
`define ETH_IPGR2_WIDTH_0 7
`define ETH_PACKETLEN_WIDTH_0 8
`define ETH_PACKETLEN_WIDTH_1 8
`define ETH_PACKETLEN_WIDTH_2 8
`define ETH_PACKETLEN_WIDTH_3 8
`define ETH_COLLCONF_WIDTH_0 6
`define ETH_COLLCONF_WIDTH_2 4
`define ETH_TX_BD_NUM_WIDTH_0 8
`define ETH_CTRLMODER_WIDTH_0 3
`define ETH_MIIMODER_WIDTH_0 8
`define ETH_MIIMODER_WIDTH_1 1
`define ETH_MIICOMMAND_WIDTH_0 3
`define ETH_MIIADDRESS_WIDTH_0 5
`define ETH_MIIADDRESS_WIDTH_1 5
`define ETH_MIITX_DATA_WIDTH_0 8
`define ETH_MIITX_DATA_WIDTH_1 8
`define ETH_MIIRX_DATA_WIDTH 16 // not written from WB
`define ETH_MIISTATUS_WIDTH 3 // not written from WB
`define ETH_MAC_ADDR0_WIDTH_0 8
`define ETH_MAC_ADDR0_WIDTH_1 8
`define ETH_MAC_ADDR0_WIDTH_2 8
`define ETH_MAC_ADDR0_WIDTH_3 8
`define ETH_MAC_ADDR1_WIDTH_0 8
`define ETH_MAC_ADDR1_WIDTH_1 8
`define ETH_HASH0_WIDTH_0 8
`define ETH_HASH0_WIDTH_1 8
`define ETH_HASH0_WIDTH_2 8
`define ETH_HASH0_WIDTH_3 8
`define ETH_HASH1_WIDTH_0 8
`define ETH_HASH1_WIDTH_1 8
`define ETH_HASH1_WIDTH_2 8
`define ETH_HASH1_WIDTH_3 8
`define ETH_TX_CTRL_WIDTH_0 8
`define ETH_TX_CTRL_WIDTH_1 8
`define ETH_TX_CTRL_WIDTH_2 1
`define ETH_RX_CTRL_WIDTH_0 8
`define ETH_RX_CTRL_WIDTH_1 8
// Outputs are registered (uncomment when needed)
`define ETH_REGISTERED_OUTPUTS
// Following defines are needed when eth_cop.v is used. Otherwise they may be deleted.
`define ETH_BASE 32'hd0000000
`define ETH_WIDTH 32'h800
`define MEMORY_BASE 32'h2000
`define MEMORY_WIDTH 32'h10000
`define M1_ADDRESSED_S1 ( (m1_wb_adr_i >= `ETH_BASE) & (m1_wb_adr_i < (`ETH_BASE + `ETH_WIDTH )) )
`define M1_ADDRESSED_S2 ( (m1_wb_adr_i >= `MEMORY_BASE) & (m1_wb_adr_i < (`MEMORY_BASE + `MEMORY_WIDTH)) )
`define M2_ADDRESSED_S1 ( (m2_wb_adr_i >= `ETH_BASE) & (m2_wb_adr_i < (`ETH_BASE + `ETH_WIDTH )) )
`define M2_ADDRESSED_S2 ( (m2_wb_adr_i >= `MEMORY_BASE) & (m2_wb_adr_i < (`MEMORY_BASE + `MEMORY_WIDTH)) )
// Previous defines are only needed for eth_cop.v
//////////////////////////////////////////////////////////////////////
//// ////
//// timescale.v ////
//// ////
//// This file is part of the Ethernet IP core project ////
//// http://www.opencores.org/projects/ethmac/ ////
//// ////
//// Author(s): ////
//// - Igor Mohor ([email protected]) ////
//// ////
//// All additional information is avaliable in the Readme.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: timescale.v,v $
// Revision 1.3 2002/01/23 10:28:16 mohor
// Link in the header changed.
//
// Revision 1.2 2001/10/19 11:36:31 mohor
// Log file added.
//
//
//
`timescale 1ns / 1ns
module xilinx_dist_ram_16x32
(
data_out,
we,
data_in,
read_address,
write_address,
wclk
);
output [31:0] data_out;
input we, wclk;
input [31:0] data_in;
input [3:0] write_address, read_address;
wire [3:0] waddr = write_address ;
wire [3:0] raddr = read_address ;
RAM16X1D ram00 (.DPO(data_out[0]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[0]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we));
RAM16X1D ram01 (.DPO(data_out[1]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[1]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we));
RAM16X1D ram02 (.DPO(data_out[2]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[2]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we));
RAM16X1D ram03 (.DPO(data_out[3]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[3]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we));
RAM16X1D ram04 (.DPO(data_out[4]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[4]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we));
RAM16X1D ram05 (.DPO(data_out[5]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[5]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we));
RAM16X1D ram06 (.DPO(data_out[6]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[6]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we));
RAM16X1D ram07 (.DPO(data_out[7]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[7]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we));
RAM16X1D ram08 (.DPO(data_out[8]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[8]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we));
RAM16X1D ram09 (.DPO(data_out[9]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[9]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we));
RAM16X1D ram10 (.DPO(data_out[10]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[10]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we));
RAM16X1D ram11 (.DPO(data_out[11]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[11]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we));
RAM16X1D ram12 (.DPO(data_out[12]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[12]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we));
RAM16X1D ram13 (.DPO(data_out[13]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[13]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we));
RAM16X1D ram14 (.DPO(data_out[14]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[14]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we));
RAM16X1D ram15 (.DPO(data_out[15]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[15]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we));
RAM16X1D ram16 (.DPO(data_out[16]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[16]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we));
RAM16X1D ram17 (.DPO(data_out[17]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[17]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we));
RAM16X1D ram18 (.DPO(data_out[18]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[18]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we));
RAM16X1D ram19 (.DPO(data_out[19]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[19]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we));
RAM16X1D ram20 (.DPO(data_out[20]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[20]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we));
RAM16X1D ram21 (.DPO(data_out[21]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[21]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we));
RAM16X1D ram22 (.DPO(data_out[22]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[22]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we));
RAM16X1D ram23 (.DPO(data_out[23]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[23]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we));
RAM16X1D ram24 (.DPO(data_out[24]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[24]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we));
RAM16X1D ram25 (.DPO(data_out[25]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[25]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we));
RAM16X1D ram26 (.DPO(data_out[26]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[26]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we));
RAM16X1D ram27 (.DPO(data_out[27]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[27]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we));
RAM16X1D ram28 (.DPO(data_out[28]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[28]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we));
RAM16X1D ram29 (.DPO(data_out[29]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[29]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we));
RAM16X1D ram30 (.DPO(data_out[30]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[30]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we));
RAM16X1D ram31 (.DPO(data_out[31]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[31]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we));
endmodule
//////////////////////////////////////////////////////////////////////
//// ////
//// eth_clockgen.v ////
//// ////
//// This file is part of the Ethernet IP core project ////
//// http://www.opencores.org/projects/ethmac/ ////
//// ////
//// Author(s): ////
//// - Igor Mohor ([email protected]) ////
//// ////
//// All additional information is avaliable in the Readme.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: eth_clockgen.v,v $
// Revision 1.3 2002/01/23 10:28:16 mohor
// Link in the header changed.
//
// Revision 1.2 2001/10/19 08:43:51 mohor
// eth_timescale.v changed to timescale.v This is done because of the
// simulation of the few cores in a one joined project.
//
// Revision 1.1 2001/08/06 14:44:29 mohor
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
// Include files fixed to contain no path.
// File names and module names changed ta have a eth_ prologue in the name.
// File eth_timescale.v is used to define timescale
// All pin names on the top module are changed to contain _I, _O or _OE at the end.
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
// and Mdo_OE. The bidirectional signal must be created on the top level. This
// is done due to the ASIC tools.
//
// Revision 1.1 2001/07/30 21:23:42 mohor
// Directory structure changed. Files checked and joind together.
//
// Revision 1.3 2001/06/01 22:28:55 mohor
// This files (MIIM) are fully working. They were thoroughly tested. The testbench is not updated.
//
//
module eth_clockgen(Clk, Reset, Divider, MdcEn, MdcEn_n, Mdc);
parameter Tp=1;
input Clk; // Input clock (Host clock)
input Reset; // Reset signal
input [7:0] Divider; // Divider (input clock will be divided by the Divider[7:0])
output Mdc; // Output clock
output MdcEn; // Enable signal is asserted for one Clk period before Mdc rises.
output MdcEn_n; // Enable signal is asserted for one Clk period before Mdc falls.
reg Mdc;
reg [7:0] Counter;
wire CountEq0;
wire [7:0] CounterPreset;
wire [7:0] TempDivider;
assign TempDivider[7:0] = (Divider[7:0]<2)? 8'h02 : Divider[7:0]; // If smaller than 2
assign CounterPreset[7:0] = (TempDivider[7:0]>>1) -1; // We are counting half of period
// Counter counts half period
always @ (posedge Clk or posedge Reset)
begin
if(Reset)
Counter[7:0] <= #Tp 8'h1;
else
begin
if(CountEq0)
begin
Counter[7:0] <= #Tp CounterPreset[7:0];
end
else
Counter[7:0] <= #Tp Counter - 8'h1;
end
end
// Mdc is asserted every other half period
always @ (posedge Clk or posedge Reset)
begin
if(Reset)
Mdc <= #Tp 1'b0;
else
begin
if(CountEq0)
Mdc <= #Tp ~Mdc;
end
end
assign CountEq0 = Counter == 8'h0;
assign MdcEn = CountEq0 & ~Mdc;
assign MdcEn_n = CountEq0 & Mdc;
endmodule
//////////////////////////////////////////////////////////////////////
//// ////
//// eth_cop.v ////
//// ////
//// This file is part of the Ethernet IP core project ////
//// http://www.opencores.org/projects/ethmac/ ////
//// ////
//// Author(s): ////
//// - Igor Mohor ([email protected]) ////
//// ////
//// All additional information is avaliable in the Readme.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001, 2002 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: eth_cop.v,v $
// Revision 1.4 2003/06/13 11:55:37 mohor
// Define file in eth_cop.v is changed to eth_defines.v. Some defines were
// moved from tb_eth_defines.v to eth_defines.v.
//
// Revision 1.3 2002/10/10 16:43:59 mohor
// Minor $display change.
//
// Revision 1.2 2002/09/09 12:54:13 mohor
// error acknowledge cycle termination added to display.
//
// Revision 1.1 2002/08/14 17:16:07 mohor
// Traffic cop with 2 wishbone master interfaces and 2 wishbona slave
// interfaces:
// - Host connects to the master interface
// - Ethernet master (DMA) connects to the second master interface
// - Memory interface connects to the slave interface
// - Ethernet slave interface (access to registers and BDs) connects to second
// slave interface
//
//
//
//
//
module eth_cop
(
// WISHBONE common
wb_clk_i, wb_rst_i,
// WISHBONE MASTER 1
m1_wb_adr_i, m1_wb_sel_i, m1_wb_we_i, m1_wb_dat_o,
m1_wb_dat_i, m1_wb_cyc_i, m1_wb_stb_i, m1_wb_ack_o,
m1_wb_err_o,
// WISHBONE MASTER 2
m2_wb_adr_i, m2_wb_sel_i, m2_wb_we_i, m2_wb_dat_o,
m2_wb_dat_i, m2_wb_cyc_i, m2_wb_stb_i, m2_wb_ack_o,
m2_wb_err_o,
// WISHBONE slave 1
s1_wb_adr_o, s1_wb_sel_o, s1_wb_we_o, s1_wb_cyc_o,
s1_wb_stb_o, s1_wb_ack_i, s1_wb_err_i, s1_wb_dat_i,
s1_wb_dat_o,
// WISHBONE slave 2
s2_wb_adr_o, s2_wb_sel_o, s2_wb_we_o, s2_wb_cyc_o,
s2_wb_stb_o, s2_wb_ack_i, s2_wb_err_i, s2_wb_dat_i,
s2_wb_dat_o
);
parameter Tp=1;
// WISHBONE common
input wb_clk_i, wb_rst_i;
// WISHBONE MASTER 1
input [31:0] m1_wb_adr_i, m1_wb_dat_i;
input [3:0] m1_wb_sel_i;
input m1_wb_cyc_i, m1_wb_stb_i, m1_wb_we_i;
output [31:0] m1_wb_dat_o;
output m1_wb_ack_o, m1_wb_err_o;
// WISHBONE MASTER 2
input [31:0] m2_wb_adr_i, m2_wb_dat_i;
input [3:0] m2_wb_sel_i;
input m2_wb_cyc_i, m2_wb_stb_i, m2_wb_we_i;
output [31:0] m2_wb_dat_o;
output m2_wb_ack_o, m2_wb_err_o;
// WISHBONE slave 1
input [31:0] s1_wb_dat_i;
input s1_wb_ack_i, s1_wb_err_i;
output [31:0] s1_wb_adr_o, s1_wb_dat_o;
output [3:0] s1_wb_sel_o;
output s1_wb_we_o, s1_wb_cyc_o, s1_wb_stb_o;
// WISHBONE slave 2
input [31:0] s2_wb_dat_i;
input s2_wb_ack_i, s2_wb_err_i;
output [31:0] s2_wb_adr_o, s2_wb_dat_o;
output [3:0] s2_wb_sel_o;
output s2_wb_we_o, s2_wb_cyc_o, s2_wb_stb_o;
reg m1_in_progress;
reg m2_in_progress;
reg [31:0] s1_wb_adr_o;
reg [3:0] s1_wb_sel_o;
reg s1_wb_we_o;
reg [31:0] s1_wb_dat_o;
reg s1_wb_cyc_o;
reg s1_wb_stb_o;
reg [31:0] s2_wb_adr_o;
reg [3:0] s2_wb_sel_o;
reg s2_wb_we_o;
reg [31:0] s2_wb_dat_o;
reg s2_wb_cyc_o;
reg s2_wb_stb_o;
reg m1_wb_ack_o;
reg [31:0] m1_wb_dat_o;
reg m2_wb_ack_o;
reg [31:0] m2_wb_dat_o;
reg m1_wb_err_o;
reg m2_wb_err_o;
wire m_wb_access_finished;
wire m1_req = m1_wb_cyc_i & m1_wb_stb_i & (`M1_ADDRESSED_S1 | `M1_ADDRESSED_S2);
wire m2_req = m2_wb_cyc_i & m2_wb_stb_i & (`M2_ADDRESSED_S1 | `M2_ADDRESSED_S2);
always @ (posedge wb_clk_i or posedge wb_rst_i)
begin
if(wb_rst_i)
begin
m1_in_progress <=#Tp 0;
m2_in_progress <=#Tp 0;
s1_wb_adr_o <=#Tp 0;
s1_wb_sel_o <=#Tp 0;
s1_wb_we_o <=#Tp 0;
s1_wb_dat_o <=#Tp 0;
s1_wb_cyc_o <=#Tp 0;
s1_wb_stb_o <=#Tp 0;
s2_wb_adr_o <=#Tp 0;
s2_wb_sel_o <=#Tp 0;
s2_wb_we_o <=#Tp 0;
s2_wb_dat_o <=#Tp 0;
s2_wb_cyc_o <=#Tp 0;
s2_wb_stb_o <=#Tp 0;
end
else
begin
case({m1_in_progress, m2_in_progress, m1_req, m2_req, m_wb_access_finished}) // synopsys_full_case synopsys_paralel_case
5'b00_10_0, 5'b00_11_0 :
begin
m1_in_progress <=#Tp 1'b1; // idle: m1 or (m1 & m2) want access: m1 -> m
if(`M1_ADDRESSED_S1)
begin
s1_wb_adr_o <=#Tp m1_wb_adr_i;
s1_wb_sel_o <=#Tp m1_wb_sel_i;
s1_wb_we_o <=#Tp m1_wb_we_i;
s1_wb_dat_o <=#Tp m1_wb_dat_i;
s1_wb_cyc_o <=#Tp 1'b1;
s1_wb_stb_o <=#Tp 1'b1;
end
else if(`M1_ADDRESSED_S2)
begin
s2_wb_adr_o <=#Tp m1_wb_adr_i;
s2_wb_sel_o <=#Tp m1_wb_sel_i;
s2_wb_we_o <=#Tp m1_wb_we_i;
s2_wb_dat_o <=#Tp m1_wb_dat_i;
s2_wb_cyc_o <=#Tp 1'b1;
s2_wb_stb_o <=#Tp 1'b1;
end
else
$display("(%t)(%m)WISHBONE ERROR: Unspecified address space accessed", $time);
end
5'b00_01_0 :
begin
m2_in_progress <=#Tp 1'b1; // idle: m2 wants access: m2 -> m
if(`M2_ADDRESSED_S1)
begin
s1_wb_adr_o <=#Tp m2_wb_adr_i;
s1_wb_sel_o <=#Tp m2_wb_sel_i;
s1_wb_we_o <=#Tp m2_wb_we_i;
s1_wb_dat_o <=#Tp m2_wb_dat_i;
s1_wb_cyc_o <=#Tp 1'b1;
s1_wb_stb_o <=#Tp 1'b1;
end
else if(`M2_ADDRESSED_S2)
begin
s2_wb_adr_o <=#Tp m2_wb_adr_i;
s2_wb_sel_o <=#Tp m2_wb_sel_i;
s2_wb_we_o <=#Tp m2_wb_we_i;
s2_wb_dat_o <=#Tp m2_wb_dat_i;
s2_wb_cyc_o <=#Tp 1'b1;
s2_wb_stb_o <=#Tp 1'b1;
end
else
$display("(%t)(%m)WISHBONE ERROR: Unspecified address space accessed", $time);
end
5'b10_10_1, 5'b10_11_1 :
begin
m1_in_progress <=#Tp 1'b0; // m1 in progress. Cycle is finished. Send ack or err to m1.
if(`M1_ADDRESSED_S1)
begin
s1_wb_cyc_o <=#Tp 1'b0;
s1_wb_stb_o <=#Tp 1'b0;
end
else if(`M1_ADDRESSED_S2)
begin
s2_wb_cyc_o <=#Tp 1'b0;
s2_wb_stb_o <=#Tp 1'b0;
end
end
5'b01_01_1, 5'b01_11_1 :
begin
m2_in_progress <=#Tp 1'b0; // m2 in progress. Cycle is finished. Send ack or err to m2.
if(`M2_ADDRESSED_S1)
begin
s1_wb_cyc_o <=#Tp 1'b0;
s1_wb_stb_o <=#Tp 1'b0;
end
else if(`M2_ADDRESSED_S2)
begin
s2_wb_cyc_o <=#Tp 1'b0;
s2_wb_stb_o <=#Tp 1'b0;
end
end
endcase
end
end
// Generating Ack for master 1
always @ (m1_in_progress or m1_wb_adr_i or s1_wb_ack_i or s2_wb_ack_i or s1_wb_dat_i or s2_wb_dat_i or `M1_ADDRESSED_S1 or `M1_ADDRESSED_S2)
begin
if(m1_in_progress)
begin
if(`M1_ADDRESSED_S1) begin
m1_wb_ack_o <= s1_wb_ack_i;
m1_wb_dat_o <= s1_wb_dat_i;
end
else if(`M1_ADDRESSED_S2) begin
m1_wb_ack_o <= s2_wb_ack_i;
m1_wb_dat_o <= s2_wb_dat_i;
end
end
else
m1_wb_ack_o <= 0;
end
// Generating Ack for master 2
always @ (m2_in_progress or m2_wb_adr_i or s1_wb_ack_i or s2_wb_ack_i or s1_wb_dat_i or s2_wb_dat_i or `M2_ADDRESSED_S1 or `M2_ADDRESSED_S2)
begin
if(m2_in_progress)
begin
if(`M2_ADDRESSED_S1) begin
m2_wb_ack_o <= s1_wb_ack_i;
m2_wb_dat_o <= s1_wb_dat_i;
end
else if(`M2_ADDRESSED_S2) begin
m2_wb_ack_o <= s2_wb_ack_i;
m2_wb_dat_o <= s2_wb_dat_i;
end
end
else
m2_wb_ack_o <= 0;
end
// Generating Err for master 1
always @ (m1_in_progress or m1_wb_adr_i or s1_wb_err_i or s2_wb_err_i or `M2_ADDRESSED_S1 or `M2_ADDRESSED_S2 or
m1_wb_cyc_i or m1_wb_stb_i)
begin
if(m1_in_progress) begin
if(`M1_ADDRESSED_S1)
m1_wb_err_o <= s1_wb_err_i;
else if(`M1_ADDRESSED_S2)
m1_wb_err_o <= s2_wb_err_i;
end
else if(m1_wb_cyc_i & m1_wb_stb_i & ~`M1_ADDRESSED_S1 & ~`M1_ADDRESSED_S2)
m1_wb_err_o <= 1'b1;
else
m1_wb_err_o <= 1'b0;
end
// Generating Err for master 2
always @ (m2_in_progress or m2_wb_adr_i or s1_wb_err_i or s2_wb_err_i or `M2_ADDRESSED_S1 or `M2_ADDRESSED_S2 or
m2_wb_cyc_i or m2_wb_stb_i)
begin
if(m2_in_progress) begin
if(`M2_ADDRESSED_S1)
m2_wb_err_o <= s1_wb_err_i;
else if(`M2_ADDRESSED_S2)
m2_wb_err_o <= s2_wb_err_i;
end
else if(m2_wb_cyc_i & m2_wb_stb_i & ~`M2_ADDRESSED_S1 & ~`M2_ADDRESSED_S2)
m2_wb_err_o <= 1'b1;
else
m2_wb_err_o <= 1'b0;
end
assign m_wb_access_finished = m1_wb_ack_o | m1_wb_err_o | m2_wb_ack_o | m2_wb_err_o;
// Activity monitor
integer cnt;
always @ (posedge wb_clk_i or posedge wb_rst_i)
begin
if(wb_rst_i)
cnt <=#Tp 0;
else
if(s1_wb_ack_i | s1_wb_err_i | s2_wb_ack_i | s2_wb_err_i)
cnt <=#Tp 0;
else
if(s1_wb_cyc_o | s2_wb_cyc_o)
cnt <=#Tp cnt+1;
end
always @ (posedge wb_clk_i)
begin
if(cnt==1000) begin
$display("(%0t)(%m) ERROR: WB activity ??? ", $time);
if(s1_wb_cyc_o) begin
$display("s1_wb_dat_o = 0x%0x", s1_wb_dat_o);
$display("s1_wb_adr_o = 0x%0x", s1_wb_adr_o);
$display("s1_wb_sel_o = 0x%0x", s1_wb_sel_o);
$display("s1_wb_we_o = 0x%0x", s1_wb_we_o);
end
else if(s2_wb_cyc_o) begin
$display("s2_wb_dat_o = 0x%0x", s2_wb_dat_o);
$display("s2_wb_adr_o = 0x%0x", s2_wb_adr_o);
$display("s2_wb_sel_o = 0x%0x", s2_wb_sel_o);
$display("s2_wb_we_o = 0x%0x", s2_wb_we_o);
end
$stop;
end
end
always @ (posedge wb_clk_i)
begin
if(s1_wb_err_i & s1_wb_cyc_o) begin
$display("(%0t) ERROR: WB cycle finished with error acknowledge ", $time);
$display("s1_wb_dat_o = 0x%0x", s1_wb_dat_o);
$display("s1_wb_adr_o = 0x%0x", s1_wb_adr_o);
$display("s1_wb_sel_o = 0x%0x", s1_wb_sel_o);
$display("s1_wb_we_o = 0x%0x", s1_wb_we_o);
$stop;
end
if(s2_wb_err_i & s2_wb_cyc_o) begin
$display("(%0t) ERROR: WB cycle finished with error acknowledge ", $time);
$display("s2_wb_dat_o = 0x%0x", s2_wb_dat_o);
$display("s2_wb_adr_o = 0x%0x", s2_wb_adr_o);
$display("s2_wb_sel_o = 0x%0x", s2_wb_sel_o);
$display("s2_wb_we_o = 0x%0x", s2_wb_we_o);
$stop;
end
end
endmodule
//////////////////////////////////////////////////////////////////////
//// ////
//// eth_crc.v ////
//// ////
//// This file is part of the Ethernet IP core project ////
//// http://www.opencores.org/projects/ethmac/ ////
//// ////
//// Author(s): ////
//// - Igor Mohor ([email protected]) ////
//// - Novan Hartadi ([email protected]) ////
//// - Mahmud Galela ([email protected]) ////
//// ////
//// All additional information is avaliable in the Readme.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: eth_crc.v,v $
// Revision 1.3 2002/01/23 10:28:16 mohor
// Link in the header changed.
//
// Revision 1.2 2001/10/19 08:43:51 mohor
// eth_timescale.v changed to timescale.v This is done because of the
// simulation of the few cores in a one joined project.
//
// Revision 1.1 2001/08/06 14:44:29 mohor
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
// Include files fixed to contain no path.
// File names and module names changed ta have a eth_ prologue in the name.
// File eth_timescale.v is used to define timescale
// All pin names on the top module are changed to contain _I, _O or _OE at the end.
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
// and Mdo_OE. The bidirectional signal must be created on the top level. This
// is done due to the ASIC tools.
//
// Revision 1.1 2001/07/30 21:23:42 mohor
// Directory structure changed. Files checked and joind together.
//
// Revision 1.3 2001/06/19 18:16:40 mohor
// TxClk changed to MTxClk (as discribed in the documentation).
// Crc changed so only one file can be used instead of two.
//
// Revision 1.2 2001/06/19 10:38:07 mohor
// Minor changes in header.
//
// Revision 1.1 2001/06/19 10:27:57 mohor
// TxEthMAC initial release.
//
//
//
module eth_crc (Clk, Reset, Data, Enable, Initialize, Crc, CrcError);
parameter Tp = 1;
input Clk;
input Reset;
input [3:0] Data;
input Enable;
input Initialize;
output [31:0] Crc;
output CrcError;
reg [31:0] Crc;
wire [31:0] CrcNext;
assign CrcNext[0] = Enable & (Data[0] ^ Crc[28]);
assign CrcNext[1] = Enable & (Data[1] ^ Data[0] ^ Crc[28] ^ Crc[29]);
assign CrcNext[2] = Enable & (Data[2] ^ Data[1] ^ Data[0] ^ Crc[28] ^ Crc[29] ^ Crc[30]);
assign CrcNext[3] = Enable & (Data[3] ^ Data[2] ^ Data[1] ^ Crc[29] ^ Crc[30] ^ Crc[31]);
assign CrcNext[4] = (Enable & (Data[3] ^ Data[2] ^ Data[0] ^ Crc[28] ^ Crc[30] ^ Crc[31])) ^ Crc[0];
assign CrcNext[5] = (Enable & (Data[3] ^ Data[1] ^ Data[0] ^ Crc[28] ^ Crc[29] ^ Crc[31])) ^ Crc[1];
assign CrcNext[6] = (Enable & (Data[2] ^ Data[1] ^ Crc[29] ^ Crc[30])) ^ Crc[ 2];
assign CrcNext[7] = (Enable & (Data[3] ^ Data[2] ^ Data[0] ^ Crc[28] ^ Crc[30] ^ Crc[31])) ^ Crc[3];
assign CrcNext[8] = (Enable & (Data[3] ^ Data[1] ^ Data[0] ^ Crc[28] ^ Crc[29] ^ Crc[31])) ^ Crc[4];
assign CrcNext[9] = (Enable & (Data[2] ^ Data[1] ^ Crc[29] ^ Crc[30])) ^ Crc[5];
assign CrcNext[10] = (Enable & (Data[3] ^ Data[2] ^ Data[0] ^ Crc[28] ^ Crc[30] ^ Crc[31])) ^ Crc[6];
assign CrcNext[11] = (Enable & (Data[3] ^ Data[1] ^ Data[0] ^ Crc[28] ^ Crc[29] ^ Crc[31])) ^ Crc[7];
assign CrcNext[12] = (Enable & (Data[2] ^ Data[1] ^ Data[0] ^ Crc[28] ^ Crc[29] ^ Crc[30])) ^ Crc[8];
assign CrcNext[13] = (Enable & (Data[3] ^ Data[2] ^ Data[1] ^ Crc[29] ^ Crc[30] ^ Crc[31])) ^ Crc[9];
assign CrcNext[14] = (Enable & (Data[3] ^ Data[2] ^ Crc[30] ^ Crc[31])) ^ Crc[10];
assign CrcNext[15] = (Enable & (Data[3] ^ Crc[31])) ^ Crc[11];
assign CrcNext[16] = (Enable & (Data[0] ^ Crc[28])) ^ Crc[12];
assign CrcNext[17] = (Enable & (Data[1] ^ Crc[29])) ^ Crc[13];
assign CrcNext[18] = (Enable & (Data[2] ^ Crc[30])) ^ Crc[14];
assign CrcNext[19] = (Enable & (Data[3] ^ Crc[31])) ^ Crc[15];
assign CrcNext[20] = Crc[16];
assign CrcNext[21] = Crc[17];
assign CrcNext[22] = (Enable & (Data[0] ^ Crc[28])) ^ Crc[18];
assign CrcNext[23] = (Enable & (Data[1] ^ Data[0] ^ Crc[29] ^ Crc[28])) ^ Crc[19];
assign CrcNext[24] = (Enable & (Data[2] ^ Data[1] ^ Crc[30] ^ Crc[29])) ^ Crc[20];
assign CrcNext[25] = (Enable & (Data[3] ^ Data[2] ^ Crc[31] ^ Crc[30])) ^ Crc[21];
assign CrcNext[26] = (Enable & (Data[3] ^ Data[0] ^ Crc[31] ^ Crc[28])) ^ Crc[22];
assign CrcNext[27] = (Enable & (Data[1] ^ Crc[29])) ^ Crc[23];
assign CrcNext[28] = (Enable & (Data[2] ^ Crc[30])) ^ Crc[24];
assign CrcNext[29] = (Enable & (Data[3] ^ Crc[31])) ^ Crc[25];
assign CrcNext[30] = Crc[26];
assign CrcNext[31] = Crc[27];
always @ (posedge Clk or posedge Reset)
begin
if (Reset)
Crc <= #1 32'hffffffff;
else
if(Initialize)
Crc <= #Tp 32'hffffffff;
else
Crc <= #Tp CrcNext;
end
assign CrcError = Crc[31:0] != 32'hc704dd7b; // CRC not equal to magic number
endmodule
//////////////////////////////////////////////////////////////////////
//// ////
//// eth_fifo.v ////
//// ////
//// This file is part of the Ethernet IP core project ////
//// http://www.opencores.org/projects/ethmac/ ////
//// ////
//// Author(s): ////
//// - Igor Mohor ([email protected]) ////
//// ////
//// All additional information is avaliable in the Readme.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: eth_fifo.v,v $
// Revision 1.3 2002/04/22 13:45:52 mohor
// Generic ram or Xilinx ram can be used in fifo (selectable by setting
// ETH_FIFO_XILINX in eth_defines.v).
//
// Revision 1.2 2002/03/25 13:33:04 mohor
// When clear and read/write are active at the same time, cnt and pointers are
// set to 1.
//
// Revision 1.1 2002/02/05 16:44:39 mohor
// Both rx and tx part are finished. Tested with wb_clk_i between 10 and 200
// MHz. Statuses, overrun, control frame transmission and reception still need
// to be fixed.
//
//
module eth_fifo (data_in, data_out, clk, reset, write, read, clear, almost_full, full, almost_empty, empty, cnt);
parameter DATA_WIDTH = 32;
parameter DEPTH = 8;
parameter CNT_WIDTH = 4;
parameter Tp = 1;
input clk;
input reset;
input write;
input read;
input clear;
input [DATA_WIDTH-1:0] data_in;
output [DATA_WIDTH-1:0] data_out;
output almost_full;
output full;
output almost_empty;
output empty;
output [CNT_WIDTH-1:0] cnt;
`ifdef ETH_FIFO_XILINX
`else
reg [DATA_WIDTH-1:0] fifo [0:DEPTH-1];
`endif
reg [CNT_WIDTH-1:0] cnt;
reg [CNT_WIDTH-2:0] read_pointer;
reg [CNT_WIDTH-2:0] write_pointer;
always @ (posedge clk or posedge reset)
begin
if(reset)
cnt <=#Tp 0;
else
if(clear)
cnt <=#Tp { {(CNT_WIDTH-1){1'b0}}, read^write};
else
if(read ^ write)
if(read)
cnt <=#Tp cnt - 1'b1;
else
cnt <=#Tp cnt + 1'b1;
end
always @ (posedge clk or posedge reset)
begin
if(reset)
read_pointer <=#Tp 0;
else
if(clear)
read_pointer <=#Tp { {(CNT_WIDTH-2){1'b0}}, read};
else
if(read & ~empty)
read_pointer <=#Tp read_pointer + 1'b1;
end
always @ (posedge clk or posedge reset)
begin
if(reset)
write_pointer <=#Tp 0;
else
if(clear)
write_pointer <=#Tp { {(CNT_WIDTH-2){1'b0}}, write};
else
if(write & ~full)
write_pointer <=#Tp write_pointer + 1'b1;
end
assign empty = ~(|cnt);
assign almost_empty = cnt == 1;
assign full = cnt == DEPTH;
assign almost_full = &cnt[CNT_WIDTH-2:0];
`ifdef ETH_FIFO_XILINX
xilinx_dist_ram_16x32 fifo
( .data_out(data_out),
.we(write & ~full),
.data_in(data_in),
.read_address( clear ? {CNT_WIDTH-1{1'b0}} : read_pointer),
.write_address(clear ? {CNT_WIDTH-1{1'b0}} : write_pointer),
.wclk(clk)
);
`else
always @ (posedge clk)
begin
if(write & clear)
fifo[0] <=#Tp data_in;
else
if(write & ~full)
fifo[write_pointer] <=#Tp data_in;
end
assign data_out = clear ? fifo[0] : fifo[read_pointer];
`endif
endmodule
//////////////////////////////////////////////////////////////////////
//// ////
//// eth_maccontrol.v ////
//// ////
//// This file is part of the Ethernet IP core project ////
//// http://www.opencores.org/projects/ethmac/ ////
//// ////
//// Author(s): ////
//// - Igor Mohor ([email protected]) ////
//// ////
//// All additional information is avaliable in the Readme.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: eth_maccontrol.v,v $
// Revision 1.7 2003/01/22 13:49:26 tadejm
// When control packets were received, they were ignored in some cases.
//
// Revision 1.6 2002/11/22 01:57:06 mohor
// Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort
// synchronized.
//
// Revision 1.5 2002/11/21 00:14:39 mohor
// TxDone and TxAbort changed so they're not propagated to the wishbone
// module when control frame is transmitted.
//
// Revision 1.4 2002/11/19 17:37:32 mohor
// When control frame (PAUSE) was sent, status was written in the
// eth_wishbone module and both TXB and TXC interrupts were set. Fixed.
// Only TXC interrupt is set.
//
// Revision 1.3 2002/01/23 10:28:16 mohor
// Link in the header changed.
//
// Revision 1.2 2001/10/19 08:43:51 mohor
// eth_timescale.v changed to timescale.v This is done because of the
// simulation of the few cores in a one joined project.
//
// Revision 1.1 2001/08/06 14:44:29 mohor
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
// Include files fixed to contain no path.
// File names and module names changed ta have a eth_ prologue in the name.
// File eth_timescale.v is used to define timescale
// All pin names on the top module are changed to contain _I, _O or _OE at the end.
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
// and Mdo_OE. The bidirectional signal must be created on the top level. This
// is done due to the ASIC tools.
//
// Revision 1.1 2001/07/30 21:23:42 mohor
// Directory structure changed. Files checked and joind together.
//
// Revision 1.1 2001/07/03 12:51:54 mohor
// Initial release of the MAC Control module.
//
//
//
//
module eth_maccontrol (MTxClk, MRxClk, TxReset, RxReset, TPauseRq, TxDataIn, TxStartFrmIn, TxUsedDataIn,
TxEndFrmIn, TxDoneIn, TxAbortIn, RxData, RxValid, RxStartFrm, RxEndFrm, ReceiveEnd,
ReceivedPacketGood, ReceivedLengthOK, TxFlow, RxFlow, DlyCrcEn, TxPauseTV,
MAC, PadIn, PadOut, CrcEnIn, CrcEnOut, TxDataOut, TxStartFrmOut, TxEndFrmOut,
TxDoneOut, TxAbortOut, TxUsedDataOut, WillSendControlFrame, TxCtrlEndFrm,
ReceivedPauseFrm, ControlFrmAddressOK, SetPauseTimer, r_PassAll, RxStatusWriteLatched_sync2
);
parameter Tp = 1;
input MTxClk; // Transmit clock (from PHY)
input MRxClk; // Receive clock (from PHY)
input TxReset; // Transmit reset
input RxReset; // Receive reset
input TPauseRq; // Transmit control frame (from host)
input [7:0] TxDataIn; // Transmit packet data byte (from host)
input TxStartFrmIn; // Transmit packet start frame input (from host)
input TxUsedDataIn; // Transmit packet used data (from TxEthMAC)
input TxEndFrmIn; // Transmit packet end frame input (from host)
input TxDoneIn; // Transmit packet done (from TxEthMAC)
input TxAbortIn; // Transmit packet abort (input from TxEthMAC)
input PadIn; // Padding (input from registers)
input CrcEnIn; // Crc append (input from registers)
input [7:0] RxData; // Receive Packet Data (from RxEthMAC)
input RxValid; // Received a valid packet
input RxStartFrm; // Receive packet start frame (input from RxEthMAC)
input RxEndFrm; // Receive packet end frame (input from RxEthMAC)
input ReceiveEnd; // End of receiving of the current packet (input from RxEthMAC)
input ReceivedPacketGood; // Received packet is good
input ReceivedLengthOK; // Length of the received packet is OK
input TxFlow; // Tx flow control (from registers)
input RxFlow; // Rx flow control (from registers)
input DlyCrcEn; // Delayed CRC enabled (from registers)
input [15:0] TxPauseTV; // Transmit Pause Timer Value (from registers)
input [47:0] MAC; // MAC address (from registers)
input RxStatusWriteLatched_sync2;
input r_PassAll;
output [7:0] TxDataOut; // Transmit Packet Data (to TxEthMAC)
output TxStartFrmOut; // Transmit packet start frame (output to TxEthMAC)
output TxEndFrmOut; // Transmit packet end frame (output to TxEthMAC)
output TxDoneOut; // Transmit packet done (to host)
output TxAbortOut; // Transmit packet aborted (to host)
output TxUsedDataOut; // Transmit packet used data (to host)
output PadOut; // Padding (output to TxEthMAC)
output CrcEnOut; // Crc append (output to TxEthMAC)
output WillSendControlFrame;
output TxCtrlEndFrm;
output ReceivedPauseFrm;
output ControlFrmAddressOK;
output SetPauseTimer;
reg TxUsedDataOutDetected;
reg TxAbortInLatched;
reg TxDoneInLatched;
reg MuxedDone;
reg MuxedAbort;
wire Pause;
wire TxCtrlStartFrm;
wire [7:0] ControlData;
wire CtrlMux;
wire SendingCtrlFrm; // Sending Control Frame (enables padding and CRC)
wire BlockTxDone;
// Signal TxUsedDataOut was detected (a transfer is already in progress)
always @ (posedge MTxClk or posedge TxReset)
begin
if(TxReset)
TxUsedDataOutDetected <= #Tp 1'b0;
else
if(TxDoneIn | TxAbortIn)
TxUsedDataOutDetected <= #Tp 1'b0;
else
if(TxUsedDataOut)
TxUsedDataOutDetected <= #Tp 1'b1;
end
// Latching variables
always @ (posedge MTxClk or posedge TxReset)
begin
if(TxReset)
begin
TxAbortInLatched <= #Tp 1'b0;
TxDoneInLatched <= #Tp 1'b0;
end
else
begin
TxAbortInLatched <= #Tp TxAbortIn;
TxDoneInLatched <= #Tp TxDoneIn;
end
end
// Generating muxed abort signal
always @ (posedge MTxClk or posedge TxReset)
begin
if(TxReset)
MuxedAbort <= #Tp 1'b0;
else
if(TxStartFrmIn)
MuxedAbort <= #Tp 1'b0;
else
if(TxAbortIn & ~TxAbortInLatched & TxUsedDataOutDetected)
MuxedAbort <= #Tp 1'b1;
end
// Generating muxed done signal
always @ (posedge MTxClk or posedge TxReset)
begin
if(TxReset)
MuxedDone <= #Tp 1'b0;
else
if(TxStartFrmIn)
MuxedDone <= #Tp 1'b0;
else
if(TxDoneIn & (~TxDoneInLatched) & TxUsedDataOutDetected)
MuxedDone <= #Tp 1'b1;
end
// TxDoneOut
assign TxDoneOut = CtrlMux? ((~TxStartFrmIn) & (~BlockTxDone) & MuxedDone) :
((~TxStartFrmIn) & (~BlockTxDone) & TxDoneIn);
// TxAbortOut
assign TxAbortOut = CtrlMux? ((~TxStartFrmIn) & (~BlockTxDone) & MuxedAbort) :
((~TxStartFrmIn) & (~BlockTxDone) & TxAbortIn);
// TxUsedDataOut
assign TxUsedDataOut = ~CtrlMux & TxUsedDataIn;
// TxStartFrmOut
assign TxStartFrmOut = CtrlMux? TxCtrlStartFrm : (TxStartFrmIn & ~Pause);
// TxEndFrmOut
assign TxEndFrmOut = CtrlMux? TxCtrlEndFrm : TxEndFrmIn;
// TxDataOut[7:0]
assign TxDataOut[7:0] = CtrlMux? ControlData[7:0] : TxDataIn[7:0];
// PadOut
assign PadOut = PadIn | SendingCtrlFrm;
// CrcEnOut
assign CrcEnOut = CrcEnIn | SendingCtrlFrm;
// Connecting receivecontrol module
eth_receivecontrol receivecontrol1
(
.MTxClk(MTxClk), .MRxClk(MRxClk), .TxReset(TxReset), .RxReset(RxReset), .RxData(RxData),
.RxValid(RxValid), .RxStartFrm(RxStartFrm), .RxEndFrm(RxEndFrm), .RxFlow(RxFlow),
.ReceiveEnd(ReceiveEnd), .MAC(MAC), .DlyCrcEn(DlyCrcEn), .TxDoneIn(TxDoneIn),
.TxAbortIn(TxAbortIn), .TxStartFrmOut(TxStartFrmOut), .ReceivedLengthOK(ReceivedLengthOK),
.ReceivedPacketGood(ReceivedPacketGood), .TxUsedDataOutDetected(TxUsedDataOutDetected),
.Pause(Pause), .ReceivedPauseFrm(ReceivedPauseFrm), .AddressOK(ControlFrmAddressOK),
.r_PassAll(r_PassAll), .RxStatusWriteLatched_sync2(RxStatusWriteLatched_sync2), .SetPauseTimer(SetPauseTimer)
);
eth_transmitcontrol transmitcontrol1
(
.MTxClk(MTxClk), .TxReset(TxReset), .TxUsedDataIn(TxUsedDataIn), .TxUsedDataOut(TxUsedDataOut),
.TxDoneIn(TxDoneIn), .TxAbortIn(TxAbortIn), .TxStartFrmIn(TxStartFrmIn), .TPauseRq(TPauseRq),
.TxUsedDataOutDetected(TxUsedDataOutDetected), .TxFlow(TxFlow), .DlyCrcEn(DlyCrcEn), .TxPauseTV(TxPauseTV),
.MAC(MAC), .TxCtrlStartFrm(TxCtrlStartFrm), .TxCtrlEndFrm(TxCtrlEndFrm), .SendingCtrlFrm(SendingCtrlFrm),
.CtrlMux(CtrlMux), .ControlData(ControlData), .WillSendControlFrame(WillSendControlFrame), .BlockTxDone(BlockTxDone)
);
endmodule
//////////////////////////////////////////////////////////////////////
//// ////
//// eth_macstatus.v ////
//// ////
//// This file is part of the Ethernet IP core project ////
//// http://www.opencores.org/projects/ethmac/ ////
//// ////
//// Author(s): ////
//// - Igor Mohor ([email protected]) ////
//// ////
//// All additional information is available in the Readme.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001, 2002 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: eth_macstatus.v,v $
// Revision 1.15 2003/01/30 13:28:19 tadejm
// Defer indication changed.
//
// Revision 1.14 2002/11/22 01:57:06 mohor
// Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort
// synchronized.
//
// Revision 1.13 2002/11/13 22:30:58 tadejm
// Late collision is reported only when not in the full duplex.
// Sample is taken (for status) as soon as MRxDV is not valid (regardless
// of the received byte cnt).
//
// Revision 1.12 2002/09/12 14:50:16 mohor
// CarrierSenseLost bug fixed when operating in full duplex mode.
//
// Revision 1.11 2002/09/04 18:38:03 mohor
// CarrierSenseLost status is not set when working in loopback mode.
//
// Revision 1.10 2002/07/25 18:17:46 mohor
// InvalidSymbol generation changed.
//
// Revision 1.9 2002/04/22 13:51:44 mohor
// Short frame and ReceivedLengthOK were not detected correctly.
//
// Revision 1.8 2002/02/18 10:40:17 mohor
// Small fixes.
//
// Revision 1.7 2002/02/15 17:07:39 mohor
// Status was not written correctly when frames were discarted because of
// address mismatch.
//
// Revision 1.6 2002/02/11 09:18:21 mohor
// Tx status is written back to the BD.
//
// Revision 1.5 2002/02/08 16:21:54 mohor
// Rx status is written back to the BD.
//
// Revision 1.4 2002/01/23 10:28:16 mohor
// Link in the header changed.
//
// Revision 1.3 2001/10/19 08:43:51 mohor
// eth_timescale.v changed to timescale.v This is done because of the
// simulation of the few cores in a one joined project.
//
// Revision 1.2 2001/09/11 14:17:00 mohor
// Few little NCSIM warnings fixed.
//
// Revision 1.1 2001/08/06 14:44:29 mohor
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
// Include files fixed to contain no path.
// File names and module names changed ta have a eth_ prologue in the name.
// File eth_timescale.v is used to define timescale
// All pin names on the top module are changed to contain _I, _O or _OE at the end.
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
// and Mdo_OE. The bidirectional signal must be created on the top level. This
// is done due to the ASIC tools.
//
// Revision 1.1 2001/07/30 21:23:42 mohor
// Directory structure changed. Files checked and joind together.
//
//
//
//
//
module eth_macstatus(
MRxClk, Reset, ReceivedLengthOK, ReceiveEnd, ReceivedPacketGood, RxCrcError,
MRxErr, MRxDV, RxStateSFD, RxStateData, RxStatePreamble, RxStateIdle, Transmitting,
RxByteCnt, RxByteCntEq0, RxByteCntGreat2, RxByteCntMaxFrame,
InvalidSymbol, MRxD, LatchedCrcError, Collision, CollValid, RxLateCollision,
r_RecSmall, r_MinFL, r_MaxFL, ShortFrame, DribbleNibble, ReceivedPacketTooBig, r_HugEn,
LoadRxStatus, StartTxDone, StartTxAbort, RetryCnt, RetryCntLatched, MTxClk, MaxCollisionOccured,
RetryLimit, LateCollision, LateCollLatched, DeferIndication, DeferLatched, TxStartFrm,
StatePreamble, StateData, CarrierSense, CarrierSenseLost, TxUsedData, LatchedMRxErr, Loopback,
r_FullD
);
parameter Tp = 1;
input MRxClk;
input Reset;
input RxCrcError;
input MRxErr;
input MRxDV;
input RxStateSFD;
input [1:0] RxStateData;
input RxStatePreamble;
input RxStateIdle;
input Transmitting;
input [15:0] RxByteCnt;
input RxByteCntEq0;
input RxByteCntGreat2;
input RxByteCntMaxFrame;
input [3:0] MRxD;
input Collision;
input [5:0] CollValid;
input r_RecSmall;
input [15:0] r_MinFL;
input [15:0] r_MaxFL;
input r_HugEn;
input StartTxDone;
input StartTxAbort;
input [3:0] RetryCnt;
input MTxClk;
input MaxCollisionOccured;
input LateCollision;
input DeferIndication;
input TxStartFrm;
input StatePreamble;
input [1:0] StateData;
input CarrierSense;
input TxUsedData;
input Loopback;
input r_FullD;
output ReceivedLengthOK;
output ReceiveEnd;
output ReceivedPacketGood;
output InvalidSymbol;
output LatchedCrcError;
output RxLateCollision;
output ShortFrame;
output DribbleNibble;
output ReceivedPacketTooBig;
output LoadRxStatus;
output [3:0] RetryCntLatched;
output RetryLimit;
output LateCollLatched;
output DeferLatched;
output CarrierSenseLost;
output LatchedMRxErr;
reg ReceiveEnd;
reg LatchedCrcError;
reg LatchedMRxErr;
reg LoadRxStatus;
reg InvalidSymbol;
reg [3:0] RetryCntLatched;
reg RetryLimit;
reg LateCollLatched;
reg DeferLatched;
reg CarrierSenseLost;
wire TakeSample;
wire SetInvalidSymbol; // Invalid symbol was received during reception in 100Mbps
// Crc error
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
LatchedCrcError <=#Tp 1'b0;
else
if(RxStateSFD)
LatchedCrcError <=#Tp 1'b0;
else
if(RxStateData[0])
LatchedCrcError <=#Tp RxCrcError & ~RxByteCntEq0;
end
// LatchedMRxErr
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
LatchedMRxErr <=#Tp 1'b0;
else
if(MRxErr & MRxDV & (RxStatePreamble | RxStateSFD | (|RxStateData) | RxStateIdle & ~Transmitting))
LatchedMRxErr <=#Tp 1'b1;
else
LatchedMRxErr <=#Tp 1'b0;
end
// ReceivedPacketGood
assign ReceivedPacketGood = ~LatchedCrcError;
// ReceivedLengthOK
assign ReceivedLengthOK = RxByteCnt[15:0] >= r_MinFL[15:0] & RxByteCnt[15:0] <= r_MaxFL[15:0];
// Time to take a sample
//assign TakeSample = |RxStateData & ~MRxDV & RxByteCntGreat2 |
assign TakeSample = (|RxStateData) & (~MRxDV) |
RxStateData[0] & MRxDV & RxByteCntMaxFrame;
// LoadRxStatus
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
LoadRxStatus <=#Tp 1'b0;
else
LoadRxStatus <=#Tp TakeSample;
end
// ReceiveEnd
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
ReceiveEnd <=#Tp 1'b0;
else
ReceiveEnd <=#Tp LoadRxStatus;
end
// Invalid Symbol received during 100Mbps mode
assign SetInvalidSymbol = MRxDV & MRxErr & MRxD[3:0] == 4'he;
// InvalidSymbol
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
InvalidSymbol <=#Tp 1'b0;
else
if(LoadRxStatus & ~SetInvalidSymbol)
InvalidSymbol <=#Tp 1'b0;
else
if(SetInvalidSymbol)
InvalidSymbol <=#Tp 1'b1;
end
// Late Collision
reg RxLateCollision;
reg RxColWindow;
// Collision Window
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
RxLateCollision <=#Tp 1'b0;
else
if(LoadRxStatus)
RxLateCollision <=#Tp 1'b0;
else
if(Collision & (~r_FullD) & (~RxColWindow | r_RecSmall))
RxLateCollision <=#Tp 1'b1;
end
// Collision Window
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
RxColWindow <=#Tp 1'b1;
else
if(~Collision & RxByteCnt[5:0] == CollValid[5:0] & RxStateData[1])
RxColWindow <=#Tp 1'b0;
else
if(RxStateIdle)
RxColWindow <=#Tp 1'b1;
end
// ShortFrame
reg ShortFrame;
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
ShortFrame <=#Tp 1'b0;
else
if(LoadRxStatus)
ShortFrame <=#Tp 1'b0;
else
if(TakeSample)
ShortFrame <=#Tp RxByteCnt[15:0] < r_MinFL[15:0];
end
// DribbleNibble
reg DribbleNibble;
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
DribbleNibble <=#Tp 1'b0;
else
if(RxStateSFD)
DribbleNibble <=#Tp 1'b0;
else
if(~MRxDV & RxStateData[1])
DribbleNibble <=#Tp 1'b1;
end
reg ReceivedPacketTooBig;
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
ReceivedPacketTooBig <=#Tp 1'b0;
else
if(LoadRxStatus)
ReceivedPacketTooBig <=#Tp 1'b0;
else
if(TakeSample)
ReceivedPacketTooBig <=#Tp ~r_HugEn & RxByteCnt[15:0] > r_MaxFL[15:0];
end
// Latched Retry counter for tx status
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
RetryCntLatched <=#Tp 4'h0;
else
if(StartTxDone | StartTxAbort)
RetryCntLatched <=#Tp RetryCnt;
end
// Latched Retransmission limit
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
RetryLimit <=#Tp 4'h0;
else
if(StartTxDone | StartTxAbort)
RetryLimit <=#Tp MaxCollisionOccured;
end
// Latched Late Collision
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
LateCollLatched <=#Tp 1'b0;
else
if(StartTxDone | StartTxAbort)
LateCollLatched <=#Tp LateCollision;
end
// Latched Defer state
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
DeferLatched <=#Tp 1'b0;
else
if(DeferIndication & TxUsedData)
DeferLatched <=#Tp 1'b1;
else
if(TxStartFrm)
DeferLatched <=#Tp 1'b0;
end
// CarrierSenseLost
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
CarrierSenseLost <=#Tp 1'b0;
else
if((StatePreamble | (|StateData)) & ~CarrierSense & ~Loopback & ~Collision & ~r_FullD)
CarrierSenseLost <=#Tp 1'b1;
else
if(TxStartFrm)
CarrierSenseLost <=#Tp 1'b0;
end
endmodule
//////////////////////////////////////////////////////////////////////
//// ////
//// eth_miim.v ////
//// ////
//// This file is part of the Ethernet IP core project ////
//// http://www.opencores.org/projects/ethmac/ ////
//// ////
//// Author(s): ////
//// - Igor Mohor ([email protected]) ////
//// ////
//// All additional information is avaliable in the Readme.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: eth_miim.v,v $
// Revision 1.5 2003/05/16 10:08:27 mohor
// Busy was set 2 cycles too late. Reported by Dennis Scott.
//
// Revision 1.4 2002/08/14 18:32:10 mohor
// - Busy signal was not set on time when scan status operation was performed
// and clock was divided with more than 2.
// - Nvalid remains valid two more clocks (was previously cleared too soon).
//
// Revision 1.3 2002/01/23 10:28:16 mohor
// Link in the header changed.
//
// Revision 1.2 2001/10/19 08:43:51 mohor
// eth_timescale.v changed to timescale.v This is done because of the
// simulation of the few cores in a one joined project.
//
// Revision 1.1 2001/08/06 14:44:29 mohor
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
// Include files fixed to contain no path.
// File names and module names changed ta have a eth_ prologue in the name.
// File eth_timescale.v is used to define timescale
// All pin names on the top module are changed to contain _I, _O or _OE at the end.
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
// and Mdo_OE. The bidirectional signal must be created on the top level. This
// is done due to the ASIC tools.
//
// Revision 1.2 2001/08/02 09:25:31 mohor
// Unconnected signals are now connected.
//
// Revision 1.1 2001/07/30 21:23:42 mohor
// Directory structure changed. Files checked and joind together.
//
// Revision 1.3 2001/06/01 22:28:56 mohor
// This files (MIIM) are fully working. They were thoroughly tested. The testbench is not updated.
//
//
module eth_miim
(
Clk,
Reset,
Divider,
NoPre,
CtrlData,
Rgad,
Fiad,
WCtrlData,
RStat,
ScanStat,
Mdi,
Mdo,
MdoEn,
Mdc,
Busy,
Prsd,
LinkFail,
Nvalid,
WCtrlDataStart,
RStatStart,
UpdateMIIRX_DATAReg
);
input Clk; // Host Clock
input Reset; // General Reset
input [7:0] Divider; // Divider for the host clock
input [15:0] CtrlData; // Control Data (to be written to the PHY reg.)
input [4:0] Rgad; // Register Address (within the PHY)
input [4:0] Fiad; // PHY Address
input NoPre; // No Preamble (no 32-bit preamble)
input WCtrlData; // Write Control Data operation
input RStat; // Read Status operation
input ScanStat; // Scan Status operation
input Mdi; // MII Management Data In
output Mdc; // MII Management Data Clock
output Mdo; // MII Management Data Output
output MdoEn; // MII Management Data Output Enable
output Busy; // Busy Signal
output LinkFail; // Link Integrity Signal
output Nvalid; // Invalid Status (qualifier for the valid scan result)
output [15:0] Prsd; // Read Status Data (data read from the PHY)
output WCtrlDataStart; // This signals resets the WCTRLDATA bit in the MIIM Command register
output RStatStart; // This signal resets the RSTAT BIT in the MIIM Command register
output UpdateMIIRX_DATAReg;// Updates MII RX_DATA register with read data
parameter Tp = 1;
reg Nvalid;
reg EndBusy_d; // Pre-end Busy signal
reg EndBusy; // End Busy signal (stops the operation in progress)
reg WCtrlData_q1; // Write Control Data operation delayed 1 Clk cycle
reg WCtrlData_q2; // Write Control Data operation delayed 2 Clk cycles
reg WCtrlData_q3; // Write Control Data operation delayed 3 Clk cycles
reg WCtrlDataStart; // Start Write Control Data Command (positive edge detected)
reg WCtrlDataStart_q;
reg WCtrlDataStart_q1; // Start Write Control Data Command delayed 1 Mdc cycle
reg WCtrlDataStart_q2; // Start Write Control Data Command delayed 2 Mdc cycles
reg RStat_q1; // Read Status operation delayed 1 Clk cycle
reg RStat_q2; // Read Status operation delayed 2 Clk cycles
reg RStat_q3; // Read Status operation delayed 3 Clk cycles
reg RStatStart; // Start Read Status Command (positive edge detected)
reg RStatStart_q1; // Start Read Status Command delayed 1 Mdc cycle
reg RStatStart_q2; // Start Read Status Command delayed 2 Mdc cycles
reg ScanStat_q1; // Scan Status operation delayed 1 cycle
reg ScanStat_q2; // Scan Status operation delayed 2 cycles
reg SyncStatMdcEn; // Scan Status operation delayed at least cycles and synchronized to MdcEn
wire WriteDataOp; // Write Data Operation (positive edge detected)
wire ReadStatusOp; // Read Status Operation (positive edge detected)
wire ScanStatusOp; // Scan Status Operation (positive edge detected)
wire StartOp; // Start Operation (start of any of the preceding operations)
wire EndOp; // End of Operation
reg InProgress; // Operation in progress
reg InProgress_q1; // Operation in progress delayed 1 Mdc cycle
reg InProgress_q2; // Operation in progress delayed 2 Mdc cycles
reg InProgress_q3; // Operation in progress delayed 3 Mdc cycles
reg WriteOp; // Write Operation Latch (When asserted, write operation is in progress)
reg [6:0] BitCounter; // Bit Counter
wire MdcFrame; // Frame window for limiting the Mdc
wire [3:0] ByteSelect; // Byte Select defines which byte (preamble, data, operation, etc.) is loaded and shifted through the shift register.
wire MdcEn; // MII Management Data Clock Enable signal is asserted for one Clk period before Mdc rises.
wire ShiftedBit; // This bit is output of the shift register and is connected to the Mdo signal
wire LatchByte1_d2;
wire LatchByte0_d2;
reg LatchByte1_d;
reg LatchByte0_d;
reg [1:0] LatchByte; // Latch Byte selects which part of Read Status Data is updated from the shift register
reg UpdateMIIRX_DATAReg;// Updates MII RX_DATA register with read data
// Generation of the EndBusy signal. It is used for ending the MII Management operation.
always @ (posedge Clk or posedge Reset)
begin
if(Reset)
begin
EndBusy_d <= #Tp 1'b0;
EndBusy <= #Tp 1'b0;
end
else
begin
EndBusy_d <= #Tp ~InProgress_q2 & InProgress_q3;
EndBusy <= #Tp EndBusy_d;
end
end
// Update MII RX_DATA register
always @ (posedge Clk or posedge Reset)
begin
if(Reset)
UpdateMIIRX_DATAReg <= #Tp 0;
else
if(EndBusy & ~WCtrlDataStart_q)
UpdateMIIRX_DATAReg <= #Tp 1;
else
UpdateMIIRX_DATAReg <= #Tp 0;
end
// Generation of the delayed signals used for positive edge triggering.
always @ (posedge Clk or posedge Reset)
begin
if(Reset)
begin
WCtrlData_q1 <= #Tp 1'b0;
WCtrlData_q2 <= #Tp 1'b0;
WCtrlData_q3 <= #Tp 1'b0;
RStat_q1 <= #Tp 1'b0;
RStat_q2 <= #Tp 1'b0;
RStat_q3 <= #Tp 1'b0;
ScanStat_q1 <= #Tp 1'b0;
ScanStat_q2 <= #Tp 1'b0;
SyncStatMdcEn <= #Tp 1'b0;
end
else
begin
WCtrlData_q1 <= #Tp WCtrlData;
WCtrlData_q2 <= #Tp WCtrlData_q1;
WCtrlData_q3 <= #Tp WCtrlData_q2;
RStat_q1 <= #Tp RStat;
RStat_q2 <= #Tp RStat_q1;
RStat_q3 <= #Tp RStat_q2;
ScanStat_q1 <= #Tp ScanStat;
ScanStat_q2 <= #Tp ScanStat_q1;
if(MdcEn)
SyncStatMdcEn <= #Tp ScanStat_q2;
end
end
// Generation of the Start Commands (Write Control Data or Read Status)
always @ (posedge Clk or posedge Reset)
begin
if(Reset)
begin
WCtrlDataStart <= #Tp 1'b0;
WCtrlDataStart_q <= #Tp 1'b0;
RStatStart <= #Tp 1'b0;
end
else
begin
if(EndBusy)
begin
WCtrlDataStart <= #Tp 1'b0;
RStatStart <= #Tp 1'b0;
end
else
begin
if(WCtrlData_q2 & ~WCtrlData_q3)
WCtrlDataStart <= #Tp 1'b1;
if(RStat_q2 & ~RStat_q3)
RStatStart <= #Tp 1'b1;
WCtrlDataStart_q <= #Tp WCtrlDataStart;
end
end
end
// Generation of the Nvalid signal (indicates when the status is invalid)
always @ (posedge Clk or posedge Reset)
begin
if(Reset)
Nvalid <= #Tp 1'b0;
else
begin
if(~InProgress_q2 & InProgress_q3)
begin
Nvalid <= #Tp 1'b0;
end
else
begin
if(ScanStat_q2 & ~SyncStatMdcEn)
Nvalid <= #Tp 1'b1;
end
end
end
// Signals used for the generation of the Operation signals (positive edge)
always @ (posedge Clk or posedge Reset)
begin
if(Reset)
begin
WCtrlDataStart_q1 <= #Tp 1'b0;
WCtrlDataStart_q2 <= #Tp 1'b0;
RStatStart_q1 <= #Tp 1'b0;
RStatStart_q2 <= #Tp 1'b0;
InProgress_q1 <= #Tp 1'b0;
InProgress_q2 <= #Tp 1'b0;
InProgress_q3 <= #Tp 1'b0;
LatchByte0_d <= #Tp 1'b0;
LatchByte1_d <= #Tp 1'b0;
LatchByte <= #Tp 2'b00;
end
else
begin
if(MdcEn)
begin
WCtrlDataStart_q1 <= #Tp WCtrlDataStart;
WCtrlDataStart_q2 <= #Tp WCtrlDataStart_q1;
RStatStart_q1 <= #Tp RStatStart;
RStatStart_q2 <= #Tp RStatStart_q1;
LatchByte[0] <= #Tp LatchByte0_d;
LatchByte[1] <= #Tp LatchByte1_d;
LatchByte0_d <= #Tp LatchByte0_d2;
LatchByte1_d <= #Tp LatchByte1_d2;
InProgress_q1 <= #Tp InProgress;
InProgress_q2 <= #Tp InProgress_q1;
InProgress_q3 <= #Tp InProgress_q2;
end
end
end
// Generation of the Operation signals
assign WriteDataOp = WCtrlDataStart_q1 & ~WCtrlDataStart_q2;
assign ReadStatusOp = RStatStart_q1 & ~RStatStart_q2;
assign ScanStatusOp = SyncStatMdcEn & ~InProgress & ~InProgress_q1 & ~InProgress_q2;
assign StartOp = WriteDataOp | ReadStatusOp | ScanStatusOp;
// Busy
assign Busy = WCtrlData | WCtrlDataStart | RStat | RStatStart | SyncStatMdcEn | EndBusy | InProgress | InProgress_q3 | Nvalid;
// Generation of the InProgress signal (indicates when an operation is in progress)
// Generation of the WriteOp signal (indicates when a write is in progress)
always @ (posedge Clk or posedge Reset)
begin
if(Reset)
begin
InProgress <= #Tp 1'b0;
WriteOp <= #Tp 1'b0;
end
else
begin
if(MdcEn)
begin
if(StartOp)
begin
if(~InProgress)
WriteOp <= #Tp WriteDataOp;
InProgress <= #Tp 1'b1;
end
else
begin
if(EndOp)
begin
InProgress <= #Tp 1'b0;
WriteOp <= #Tp 1'b0;
end
end
end
end
end
// Bit Counter counts from 0 to 63 (from 32 to 63 when NoPre is asserted)
always @ (posedge Clk or posedge Reset)
begin
if(Reset)
BitCounter[6:0] <= #Tp 7'h0;
else
begin
if(MdcEn)
begin
if(InProgress)
begin
if(NoPre & ( BitCounter == 7'h0 ))
BitCounter[6:0] <= #Tp 7'h21;
else
BitCounter[6:0] <= #Tp BitCounter[6:0] + 1'b1;
end
else
BitCounter[6:0] <= #Tp 7'h0;
end
end
end
// Operation ends when the Bit Counter reaches 63
assign EndOp = BitCounter==63;
assign ByteSelect[0] = InProgress & ((NoPre & (BitCounter == 7'h0)) | (~NoPre & (BitCounter == 7'h20)));
assign ByteSelect[1] = InProgress & (BitCounter == 7'h28);
assign ByteSelect[2] = InProgress & WriteOp & (BitCounter == 7'h30);
assign ByteSelect[3] = InProgress & WriteOp & (BitCounter == 7'h38);
// Latch Byte selects which part of Read Status Data is updated from the shift register
assign LatchByte1_d2 = InProgress & ~WriteOp & BitCounter == 7'h37;
assign LatchByte0_d2 = InProgress & ~WriteOp & BitCounter == 7'h3F;
// Connecting the Clock Generator Module
eth_clockgen clkgen(.Clk(Clk), .Reset(Reset), .Divider(Divider[7:0]), .MdcEn(MdcEn), .MdcEn_n(MdcEn_n), .Mdc(Mdc)
);
// Connecting the Shift Register Module
eth_shiftreg shftrg(.Clk(Clk), .Reset(Reset), .MdcEn_n(MdcEn_n), .Mdi(Mdi), .Fiad(Fiad), .Rgad(Rgad),
.CtrlData(CtrlData), .WriteOp(WriteOp), .ByteSelect(ByteSelect), .LatchByte(LatchByte),
.ShiftedBit(ShiftedBit), .Prsd(Prsd), .LinkFail(LinkFail)
);
// Connecting the Output Control Module
eth_outputcontrol outctrl(.Clk(Clk), .Reset(Reset), .MdcEn_n(MdcEn_n), .InProgress(InProgress),
.ShiftedBit(ShiftedBit), .BitCounter(BitCounter), .WriteOp(WriteOp), .NoPre(NoPre),
.Mdo(Mdo), .MdoEn(MdoEn)
);
endmodule
//////////////////////////////////////////////////////////////////////
//// ////
//// eth_outputcontrol.v ////
//// ////
//// This file is part of the Ethernet IP core project ////
//// http://www.opencores.org/projects/ethmac/ ////
//// ////
//// Author(s): ////
//// - Igor Mohor ([email protected]) ////
//// ////
//// All additional information is avaliable in the Readme.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: eth_outputcontrol.v,v $
// Revision 1.4 2002/07/09 20:11:59 mohor
// Comment removed.
//
// Revision 1.3 2002/01/23 10:28:16 mohor
// Link in the header changed.
//
// Revision 1.2 2001/10/19 08:43:51 mohor
// eth_timescale.v changed to timescale.v This is done because of the
// simulation of the few cores in a one joined project.
//
// Revision 1.1 2001/08/06 14:44:29 mohor
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
// Include files fixed to contain no path.
// File names and module names changed ta have a eth_ prologue in the name.
// File eth_timescale.v is used to define timescale
// All pin names on the top module are changed to contain _I, _O or _OE at the end.
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
// and Mdo_OE. The bidirectional signal must be created on the top level. This
// is done due to the ASIC tools.
//
// Revision 1.1 2001/07/30 21:23:42 mohor
// Directory structure changed. Files checked and joind together.
//
// Revision 1.3 2001/06/01 22:28:56 mohor
// This files (MIIM) are fully working. They were thoroughly tested. The testbench is not updated.
//
//
module eth_outputcontrol(Clk, Reset, InProgress, ShiftedBit, BitCounter, WriteOp, NoPre, MdcEn_n, Mdo, MdoEn);
parameter Tp = 1;
input Clk; // Host Clock
input Reset; // General Reset
input WriteOp; // Write Operation Latch (When asserted, write operation is in progress)
input NoPre; // No Preamble (no 32-bit preamble)
input InProgress; // Operation in progress
input ShiftedBit; // This bit is output of the shift register and is connected to the Mdo signal
input [6:0] BitCounter; // Bit Counter
input MdcEn_n; // MII Management Data Clock Enable signal is asserted for one Clk period before Mdc falls.
output Mdo; // MII Management Data Output
output MdoEn; // MII Management Data Output Enable
wire SerialEn;
reg MdoEn_2d;
reg MdoEn_d;
reg MdoEn;
reg Mdo_2d;
reg Mdo_d;
reg Mdo; // MII Management Data Output
// Generation of the Serial Enable signal (enables the serialization of the data)
assign SerialEn = WriteOp & InProgress & ( BitCounter>31 | ( ( BitCounter == 0 ) & NoPre ) )
| ~WriteOp & InProgress & (( BitCounter>31 & BitCounter<46 ) | ( ( BitCounter == 0 ) & NoPre ));
// Generation of the MdoEn signal
always @ (posedge Clk or posedge Reset)
begin
if(Reset)
begin
MdoEn_2d <= #Tp 1'b0;
MdoEn_d <= #Tp 1'b0;
MdoEn <= #Tp 1'b0;
end
else
begin
if(MdcEn_n)
begin
MdoEn_2d <= #Tp SerialEn | InProgress & BitCounter<32;
MdoEn_d <= #Tp MdoEn_2d;
MdoEn <= #Tp MdoEn_d;
end
end
end
// Generation of the Mdo signal.
always @ (posedge Clk or posedge Reset)
begin
if(Reset)
begin
Mdo_2d <= #Tp 1'b0;
Mdo_d <= #Tp 1'b0;
Mdo <= #Tp 1'b0;
end
else
begin
if(MdcEn_n)
begin
Mdo_2d <= #Tp ~SerialEn & BitCounter<32;
Mdo_d <= #Tp ShiftedBit | Mdo_2d;
Mdo <= #Tp Mdo_d;
end
end
end
endmodule
//////////////////////////////////////////////////////////////////////
//// ////
//// eth_random.v ////
//// ////
//// This file is part of the Ethernet IP core project ////
//// http://www.opencores.org/projects/ethmac/ ////
//// ////
//// Author(s): ////
//// - Igor Mohor ([email protected]) ////
//// - Novan Hartadi ([email protected]) ////
//// - Mahmud Galela ([email protected]) ////
//// ////
//// All additional information is avaliable in the Readme.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: eth_random.v,v $
// Revision 1.4 2003/06/13 11:26:08 mohor
// Binary operator used instead of unary (xnor).
//
// Revision 1.3 2002/01/23 10:28:16 mohor
// Link in the header changed.
//
// Revision 1.2 2001/10/19 08:43:51 mohor
// eth_timescale.v changed to timescale.v This is done because of the
// simulation of the few cores in a one joined project.
//
// Revision 1.1 2001/08/06 14:44:29 mohor
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
// Include files fixed to contain no path.
// File names and module names changed ta have a eth_ prologue in the name.
// File eth_timescale.v is used to define timescale
// All pin names on the top module are changed to contain _I, _O or _OE at the end.
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
// and Mdo_OE. The bidirectional signal must be created on the top level. This
// is done due to the ASIC tools.
//
// Revision 1.1 2001/07/30 21:23:42 mohor
// Directory structure changed. Files checked and joind together.
//
// Revision 1.3 2001/06/19 18:16:40 mohor
// TxClk changed to MTxClk (as discribed in the documentation).
// Crc changed so only one file can be used instead of two.
//
// Revision 1.2 2001/06/19 10:38:07 mohor
// Minor changes in header.
//
// Revision 1.1 2001/06/19 10:27:57 mohor
// TxEthMAC initial release.
//
//
//
//
module eth_random (MTxClk, Reset, StateJam, StateJam_q, RetryCnt, NibCnt, ByteCnt,
RandomEq0, RandomEqByteCnt);
parameter Tp = 1;
input MTxClk;
input Reset;
input StateJam;
input StateJam_q;
input [3:0] RetryCnt;
input [15:0] NibCnt;
input [9:0] ByteCnt;
output RandomEq0;
output RandomEqByteCnt;
wire Feedback;
reg [9:0] x;
wire [9:0] Random;
reg [9:0] RandomLatched;
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
x[9:0] <= #Tp 0;
else
x[9:0] <= #Tp {x[8:0], Feedback};
end
assign Feedback = ~(x[2] ^ x[9]);
assign Random [0] = x[0];
assign Random [1] = (RetryCnt > 1) ? x[1] : 1'b0;
assign Random [2] = (RetryCnt > 2) ? x[2] : 1'b0;
assign Random [3] = (RetryCnt > 3) ? x[3] : 1'b0;
assign Random [4] = (RetryCnt > 4) ? x[4] : 1'b0;
assign Random [5] = (RetryCnt > 5) ? x[5] : 1'b0;
assign Random [6] = (RetryCnt > 6) ? x[6] : 1'b0;
assign Random [7] = (RetryCnt > 7) ? x[7] : 1'b0;
assign Random [8] = (RetryCnt > 8) ? x[8] : 1'b0;
assign Random [9] = (RetryCnt > 9) ? x[9] : 1'b0;
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
RandomLatched <= #Tp 10'h000;
else
begin
if(StateJam & StateJam_q)
RandomLatched <= #Tp Random;
end
end
// Random Number == 0 IEEE 802.3 page 68. If 0 we go to defer and not to backoff.
assign RandomEq0 = RandomLatched == 10'h0;
assign RandomEqByteCnt = ByteCnt[9:0] == RandomLatched & (&NibCnt[6:0]);
endmodule
//////////////////////////////////////////////////////////////////////
//// ////
//// eth_receivecontrol.v ////
//// ////
//// This file is part of the Ethernet IP core project ////
//// http://www.opencores.org/projects/ethmac/ ////
//// ////
//// Author(s): ////
//// - Igor Mohor ([email protected]) ////
//// ////
//// All additional information is avaliable in the Readme.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: eth_receivecontrol.v,v $
// Revision 1.5 2003/01/22 13:49:26 tadejm
// When control packets were received, they were ignored in some cases.
//
// Revision 1.4 2002/11/22 01:57:06 mohor
// Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort
// synchronized.
//
// Revision 1.3 2002/01/23 10:28:16 mohor
// Link in the header changed.
//
// Revision 1.2 2001/10/19 08:43:51 mohor
// eth_timescale.v changed to timescale.v This is done because of the
// simulation of the few cores in a one joined project.
//
// Revision 1.1 2001/08/06 14:44:29 mohor
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
// Include files fixed to contain no path.
// File names and module names changed ta have a eth_ prologue in the name.
// File eth_timescale.v is used to define timescale
// All pin names on the top module are changed to contain _I, _O or _OE at the end.
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
// and Mdo_OE. The bidirectional signal must be created on the top level. This
// is done due to the ASIC tools.
//
// Revision 1.1 2001/07/30 21:23:42 mohor
// Directory structure changed. Files checked and joind together.
//
// Revision 1.1 2001/07/03 12:51:54 mohor
// Initial release of the MAC Control module.
//
//
//
//
//
module eth_receivecontrol (MTxClk, MRxClk, TxReset, RxReset, RxData, RxValid, RxStartFrm,
RxEndFrm, RxFlow, ReceiveEnd, MAC, DlyCrcEn, TxDoneIn,
TxAbortIn, TxStartFrmOut, ReceivedLengthOK, ReceivedPacketGood,
TxUsedDataOutDetected, Pause, ReceivedPauseFrm, AddressOK,
RxStatusWriteLatched_sync2, r_PassAll, SetPauseTimer
);
parameter Tp = 1;
input MTxClk;
input MRxClk;
input TxReset;
input RxReset;
input [7:0] RxData;
input RxValid;
input RxStartFrm;
input RxEndFrm;
input RxFlow;
input ReceiveEnd;
input [47:0]MAC;
input DlyCrcEn;
input TxDoneIn;
input TxAbortIn;
input TxStartFrmOut;
input ReceivedLengthOK;
input ReceivedPacketGood;
input TxUsedDataOutDetected;
input RxStatusWriteLatched_sync2;
input r_PassAll;
output Pause;
output ReceivedPauseFrm;
output AddressOK;
output SetPauseTimer;
reg Pause;
reg AddressOK; // Multicast or unicast address detected
reg TypeLengthOK; // Type/Length field contains 0x8808
reg DetectionWindow; // Detection of the PAUSE frame is possible within this window
reg OpCodeOK; // PAUSE opcode detected (0x0001)
reg [2:0] DlyCrcCnt;
reg [4:0] ByteCnt;
reg [15:0] AssembledTimerValue;
reg [15:0] LatchedTimerValue;
reg ReceivedPauseFrm;
reg ReceivedPauseFrmWAddr;
reg PauseTimerEq0_sync1;
reg PauseTimerEq0_sync2;
reg [15:0] PauseTimer;
reg Divider2;
reg [5:0] SlotTimer;
wire [47:0] ReservedMulticast; // 0x0180C2000001
wire [15:0] TypeLength; // 0x8808
wire ResetByteCnt; //
wire IncrementByteCnt; //
wire ByteCntEq0; // ByteCnt = 0
wire ByteCntEq1; // ByteCnt = 1
wire ByteCntEq2; // ByteCnt = 2
wire ByteCntEq3; // ByteCnt = 3
wire ByteCntEq4; // ByteCnt = 4
wire ByteCntEq5; // ByteCnt = 5
wire ByteCntEq12; // ByteCnt = 12
wire ByteCntEq13; // ByteCnt = 13
wire ByteCntEq14; // ByteCnt = 14
wire ByteCntEq15; // ByteCnt = 15
wire ByteCntEq16; // ByteCnt = 16
wire ByteCntEq17; // ByteCnt = 17
wire ByteCntEq18; // ByteCnt = 18
wire DecrementPauseTimer; //
wire PauseTimerEq0; //
wire ResetSlotTimer; //
wire IncrementSlotTimer; //
wire SlotFinished; //
// Reserved multicast address and Type/Length for PAUSE control
assign ReservedMulticast = 48'h0180C2000001;
assign TypeLength = 16'h8808;
// Address Detection (Multicast or unicast)
always @ (posedge MRxClk or posedge RxReset)
begin
if(RxReset)
AddressOK <= #Tp 1'b0;
else
if(DetectionWindow & ByteCntEq0)
AddressOK <= #Tp RxData[7:0] == ReservedMulticast[47:40] | RxData[7:0] == MAC[47:40];
else
if(DetectionWindow & ByteCntEq1)
AddressOK <= #Tp (RxData[7:0] == ReservedMulticast[39:32] | RxData[7:0] == MAC[39:32]) & AddressOK;
else
if(DetectionWindow & ByteCntEq2)
AddressOK <= #Tp (RxData[7:0] == ReservedMulticast[31:24] | RxData[7:0] == MAC[31:24]) & AddressOK;
else
if(DetectionWindow & ByteCntEq3)
AddressOK <= #Tp (RxData[7:0] == ReservedMulticast[23:16] | RxData[7:0] == MAC[23:16]) & AddressOK;
else
if(DetectionWindow & ByteCntEq4)
AddressOK <= #Tp (RxData[7:0] == ReservedMulticast[15:8] | RxData[7:0] == MAC[15:8]) & AddressOK;
else
if(DetectionWindow & ByteCntEq5)
AddressOK <= #Tp (RxData[7:0] == ReservedMulticast[7:0] | RxData[7:0] == MAC[7:0]) & AddressOK;
else
if(ReceiveEnd)
AddressOK <= #Tp 1'b0;
end
// TypeLengthOK (Type/Length Control frame detected)
always @ (posedge MRxClk or posedge RxReset )
begin
if(RxReset)
TypeLengthOK <= #Tp 1'b0;
else
if(DetectionWindow & ByteCntEq12)
TypeLengthOK <= #Tp ByteCntEq12 & (RxData[7:0] == TypeLength[15:8]);
else
if(DetectionWindow & ByteCntEq13)
TypeLengthOK <= #Tp ByteCntEq13 & (RxData[7:0] == TypeLength[7:0]) & TypeLengthOK;
else
if(ReceiveEnd)
TypeLengthOK <= #Tp 1'b0;
end
// Latch Control Frame Opcode
always @ (posedge MRxClk or posedge RxReset )
begin
if(RxReset)
OpCodeOK <= #Tp 1'b0;
else
if(ByteCntEq16)
OpCodeOK <= #Tp 1'b0;
else
begin
if(DetectionWindow & ByteCntEq14)
OpCodeOK <= #Tp ByteCntEq14 & RxData[7:0] == 8'h00;
if(DetectionWindow & ByteCntEq15)
OpCodeOK <= #Tp ByteCntEq15 & RxData[7:0] == 8'h01 & OpCodeOK;
end
end
// ReceivedPauseFrmWAddr (+Address Check)
always @ (posedge MRxClk or posedge RxReset )
begin
if(RxReset)
ReceivedPauseFrmWAddr <= #Tp 1'b0;
else
if(ReceiveEnd)
ReceivedPauseFrmWAddr <= #Tp 1'b0;
else
if(ByteCntEq16 & TypeLengthOK & OpCodeOK & AddressOK)
ReceivedPauseFrmWAddr <= #Tp 1'b1;
end
// Assembling 16-bit timer value from two 8-bit data
always @ (posedge MRxClk or posedge RxReset )
begin
if(RxReset)
AssembledTimerValue[15:0] <= #Tp 16'h0;
else
if(RxStartFrm)
AssembledTimerValue[15:0] <= #Tp 16'h0;
else
begin
if(DetectionWindow & ByteCntEq16)
AssembledTimerValue[15:8] <= #Tp RxData[7:0];
if(DetectionWindow & ByteCntEq17)
AssembledTimerValue[7:0] <= #Tp RxData[7:0];
end
end
// Detection window (while PAUSE detection is possible)
always @ (posedge MRxClk or posedge RxReset )
begin
if(RxReset)
DetectionWindow <= #Tp 1'b1;
else
if(ByteCntEq18)
DetectionWindow <= #Tp 1'b0;
else
if(ReceiveEnd)
DetectionWindow <= #Tp 1'b1;
end
// Latching Timer Value
always @ (posedge MRxClk or posedge RxReset )
begin
if(RxReset)
LatchedTimerValue[15:0] <= #Tp 16'h0;
else
if(DetectionWindow & ReceivedPauseFrmWAddr & ByteCntEq18)
LatchedTimerValue[15:0] <= #Tp AssembledTimerValue[15:0];
else
if(ReceiveEnd)
LatchedTimerValue[15:0] <= #Tp 16'h0;
end
// Delayed CEC counter
always @ (posedge MRxClk or posedge RxReset)
begin
if(RxReset)
DlyCrcCnt <= #Tp 3'h0;
else
if(RxValid & RxEndFrm)
DlyCrcCnt <= #Tp 3'h0;
else
if(RxValid & ~RxEndFrm & ~DlyCrcCnt[2])
DlyCrcCnt <= #Tp DlyCrcCnt + 1'b1;
end
assign ResetByteCnt = RxEndFrm;
assign IncrementByteCnt = RxValid & DetectionWindow & ~ByteCntEq18 & (~DlyCrcEn | DlyCrcEn & DlyCrcCnt[2]);
// Byte counter
always @ (posedge MRxClk or posedge RxReset)
begin
if(RxReset)
ByteCnt[4:0] <= #Tp 5'h0;
else
if(ResetByteCnt)
ByteCnt[4:0] <= #Tp 5'h0;
else
if(IncrementByteCnt)
ByteCnt[4:0] <= #Tp ByteCnt[4:0] + 1'b1;
end
assign ByteCntEq0 = RxValid & ByteCnt[4:0] == 5'h0;
assign ByteCntEq1 = RxValid & ByteCnt[4:0] == 5'h1;
assign ByteCntEq2 = RxValid & ByteCnt[4:0] == 5'h2;
assign ByteCntEq3 = RxValid & ByteCnt[4:0] == 5'h3;
assign ByteCntEq4 = RxValid & ByteCnt[4:0] == 5'h4;
assign ByteCntEq5 = RxValid & ByteCnt[4:0] == 5'h5;
assign ByteCntEq12 = RxValid & ByteCnt[4:0] == 5'h0C;
assign ByteCntEq13 = RxValid & ByteCnt[4:0] == 5'h0D;
assign ByteCntEq14 = RxValid & ByteCnt[4:0] == 5'h0E;
assign ByteCntEq15 = RxValid & ByteCnt[4:0] == 5'h0F;
assign ByteCntEq16 = RxValid & ByteCnt[4:0] == 5'h10;
assign ByteCntEq17 = RxValid & ByteCnt[4:0] == 5'h11;
assign ByteCntEq18 = RxValid & ByteCnt[4:0] == 5'h12 & DetectionWindow;
assign SetPauseTimer = ReceiveEnd & ReceivedPauseFrmWAddr & ReceivedPacketGood & ReceivedLengthOK & RxFlow;
assign DecrementPauseTimer = SlotFinished & |PauseTimer;
// PauseTimer[15:0]
always @ (posedge MRxClk or posedge RxReset)
begin
if(RxReset)
PauseTimer[15:0] <= #Tp 16'h0;
else
if(SetPauseTimer)
PauseTimer[15:0] <= #Tp LatchedTimerValue[15:0];
else
if(DecrementPauseTimer)
PauseTimer[15:0] <= #Tp PauseTimer[15:0] - 1'b1;
end
assign PauseTimerEq0 = ~(|PauseTimer[15:0]);
// Synchronization of the pause timer
always @ (posedge MTxClk or posedge TxReset)
begin
if(TxReset)
begin
PauseTimerEq0_sync1 <= #Tp 1'b1;
PauseTimerEq0_sync2 <= #Tp 1'b1;
end
else
begin
PauseTimerEq0_sync1 <= #Tp PauseTimerEq0;
PauseTimerEq0_sync2 <= #Tp PauseTimerEq0_sync1;
end
end
// Pause signal generation
always @ (posedge MTxClk or posedge TxReset)
begin
if(TxReset)
Pause <= #Tp 1'b0;
else
if((TxDoneIn | TxAbortIn | ~TxUsedDataOutDetected) & ~TxStartFrmOut)
Pause <= #Tp RxFlow & ~PauseTimerEq0_sync2;
end
// Divider2 is used for incrementing the Slot timer every other clock
always @ (posedge MRxClk or posedge RxReset)
begin
if(RxReset)
Divider2 <= #Tp 1'b0;
else
if(|PauseTimer[15:0] & RxFlow)
Divider2 <= #Tp ~Divider2;
else
Divider2 <= #Tp 1'b0;
end
assign ResetSlotTimer = RxReset;
assign IncrementSlotTimer = Pause & RxFlow & Divider2;
// SlotTimer
always @ (posedge MRxClk or posedge RxReset)
begin
if(RxReset)
SlotTimer[5:0] <= #Tp 6'h0;
else
if(ResetSlotTimer)
SlotTimer[5:0] <= #Tp 6'h0;
else
if(IncrementSlotTimer)
SlotTimer[5:0] <= #Tp SlotTimer[5:0] + 1'b1;
end
assign SlotFinished = &SlotTimer[5:0] & IncrementSlotTimer; // Slot is 512 bits (64 bytes)
// Pause Frame received
always @ (posedge MRxClk or posedge RxReset)
begin
if(RxReset)
ReceivedPauseFrm <=#Tp 1'b0;
else
if(RxStatusWriteLatched_sync2 & r_PassAll | ReceivedPauseFrm & (~r_PassAll))
ReceivedPauseFrm <=#Tp 1'b0;
else
if(ByteCntEq16 & TypeLengthOK & OpCodeOK)
ReceivedPauseFrm <=#Tp 1'b1;
end
endmodule
//////////////////////////////////////////////////////////////////////
//// ////
//// eth_register.v ////
//// ////
//// This file is part of the Ethernet IP core project ////
//// http://www.opencores.org/projects/ethmac/ ////
//// ////
//// Author(s): ////
//// - Igor Mohor ([email protected]) ////
//// ////
//// All additional information is avaliable in the Readme.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001, 2002 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: eth_register.v,v $
// Revision 1.6 2002/08/16 22:10:12 mohor
// Synchronous reset added.
//
// Revision 1.5 2002/08/16 12:33:27 mohor
// Parameter ResetValue changed to capital letters.
//
// Revision 1.4 2002/02/26 16:18:08 mohor
// Reset values are passed to registers through parameters
//
// Revision 1.3 2002/01/23 10:28:16 mohor
// Link in the header changed.
//
// Revision 1.2 2001/10/19 08:43:51 mohor
// eth_timescale.v changed to timescale.v This is done because of the
// simulation of the few cores in a one joined project.
//
// Revision 1.1 2001/08/06 14:44:29 mohor
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
// Include files fixed to contain no path.
// File names and module names changed ta have a eth_ prologue in the name.
// File eth_timescale.v is used to define timescale
// All pin names on the top module are changed to contain _I, _O or _OE at the end.
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
// and Mdo_OE. The bidirectional signal must be created on the top level. This
// is done due to the ASIC tools.
//
//
//
//
//
//
//
module eth_register(DataIn, DataOut, Write, Clk, Reset, SyncReset);
parameter WIDTH = 8; // default parameter of the register width
parameter RESET_VALUE = 0;
input [WIDTH-1:0] DataIn;
input Write;
input Clk;
input Reset;
input SyncReset;
output [WIDTH-1:0] DataOut;
reg [WIDTH-1:0] DataOut;
always @ (posedge Clk or posedge Reset)
begin
if(Reset)
DataOut<=#1 RESET_VALUE;
else
if(SyncReset)
DataOut<=#1 RESET_VALUE;
else
if(Write) // write
DataOut<=#1 DataIn;
end
endmodule // Register
//////////////////////////////////////////////////////////////////////
//// ////
//// eth_registers.v ////
//// ////
//// This file is part of the Ethernet IP core project ////
//// http://www.opencores.org/projects/ethmac/ ////
//// ////
//// Author(s): ////
//// - Igor Mohor ([email protected]) ////
//// ////
//// All additional information is avaliable in the Readme.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001, 2002 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: eth_registers.v,v $
// Revision 1.28 2004/04/26 15:26:23 igorm
// - Bug connected to the TX_BD_NUM_Wr signal fixed (bug came in with the
// previous update of the core.
// - TxBDAddress is set to 0 after the TX is enabled in the MODER register.
// - RxBDAddress is set to r_TxBDNum<<1 after the RX is enabled in the MODER
// register. (thanks to Mathias and Torbjorn)
// - Multicast reception was fixed. Thanks to Ulrich Gries
//
// Revision 1.27 2004/04/26 11:42:17 igorm
// TX_BD_NUM_Wr error fixed. Error was entered with the last check-in.
//
// Revision 1.26 2003/11/12 18:24:59 tadejm
// WISHBONE slave changed and tested from only 32-bit accesss to byte access.
//
// Revision 1.25 2003/04/18 16:26:25 mohor
// RxBDAddress was updated also when value to r_TxBDNum was written with
// greater value than allowed.
//
// Revision 1.24 2002/11/22 01:57:06 mohor
// Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort
// synchronized.
//
// Revision 1.23 2002/11/19 18:13:49 mohor
// r_MiiMRst is not used for resetting the MIIM module. wb_rst used instead.
//
// Revision 1.22 2002/11/14 18:37:20 mohor
// r_Rst signal does not reset any module any more and is removed from the design.
//
// Revision 1.21 2002/09/10 10:35:23 mohor
// Ethernet debug registers removed.
//
// Revision 1.20 2002/09/04 18:40:25 mohor
// ETH_TXCTRL and ETH_RXCTRL registers added. Interrupts related to
// the control frames connected.
//
// Revision 1.19 2002/08/19 16:01:40 mohor
// Only values smaller or equal to 0x80 can be written to TX_BD_NUM register.
// r_TxEn and r_RxEn depend on the limit values of the TX_BD_NUMOut.
//
// Revision 1.18 2002/08/16 22:28:23 mohor
// Syntax error fixed.
//
// Revision 1.17 2002/08/16 22:23:03 mohor
// Syntax error fixed.
//
// Revision 1.16 2002/08/16 22:14:22 mohor
// Synchronous reset added to all registers. Defines used for width. r_MiiMRst
// changed from bit position 10 to 9.
//
// Revision 1.15 2002/08/14 18:26:37 mohor
// LinkFailRegister is reflecting the status of the PHY's link fail status bit.
//
// Revision 1.14 2002/04/22 14:03:44 mohor
// Interrupts are visible in the ETH_INT_SOURCE regardless if they are enabled
// or not.
//
// Revision 1.13 2002/02/26 16:18:09 mohor
// Reset values are passed to registers through parameters
//
// Revision 1.12 2002/02/17 13:23:42 mohor
// Define missmatch fixed.
//
// Revision 1.11 2002/02/16 14:03:44 mohor
// Registered trimmed. Unused registers removed.
//
// Revision 1.10 2002/02/15 11:08:25 mohor
// File format fixed a bit.
//
// Revision 1.9 2002/02/14 20:19:41 billditt
// Modified for Address Checking,
// addition of eth_addrcheck.v
//
// Revision 1.8 2002/02/12 17:01:19 mohor
// HASH0 and HASH1 registers added.
// Revision 1.7 2002/01/23 10:28:16 mohor
// Link in the header changed.
//
// Revision 1.6 2001/12/05 15:00:16 mohor
// RX_BD_NUM changed to TX_BD_NUM (holds number of TX descriptors
// instead of the number of RX descriptors).
//
// Revision 1.5 2001/12/05 10:22:19 mohor
// ETH_RX_BD_ADR register deleted. ETH_RX_BD_NUM is used instead.
//
// Revision 1.4 2001/10/19 08:43:51 mohor
// eth_timescale.v changed to timescale.v This is done because of the
// simulation of the few cores in a one joined project.
//
// Revision 1.3 2001/10/18 12:07:11 mohor
// Status signals changed, Adress decoding changed, interrupt controller
// added.
//
// Revision 1.2 2001/09/24 15:02:56 mohor
// Defines changed (All precede with ETH_). Small changes because some
// tools generate warnings when two operands are together. Synchronization
// between two clocks domains in eth_wishbonedma.v is changed (due to ASIC
// demands).
//
// Revision 1.1 2001/08/06 14:44:29 mohor
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
// Include files fixed to contain no path.
// File names and module names changed ta have a eth_ prologue in the name.
// File eth_timescale.v is used to define timescale
// All pin names on the top module are changed to contain _I, _O or _OE at the end.
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
// and Mdo_OE. The bidirectional signal must be created on the top level. This
// is done due to the ASIC tools.
//
// Revision 1.2 2001/08/02 09:25:31 mohor
// Unconnected signals are now connected.
//
// Revision 1.1 2001/07/30 21:23:42 mohor
// Directory structure changed. Files checked and joind together.
//
//
//
//
//
//
module eth_registers( DataIn, Address, Rw, Cs, Clk, Reset, DataOut,
r_RecSmall, r_Pad, r_HugEn, r_CrcEn, r_DlyCrcEn,
r_FullD, r_ExDfrEn, r_NoBckof, r_LoopBck, r_IFG,
r_Pro, r_Iam, r_Bro, r_NoPre, r_TxEn, r_RxEn,
TxB_IRQ, TxE_IRQ, RxB_IRQ, RxE_IRQ, Busy_IRQ,
r_IPGT, r_IPGR1, r_IPGR2, r_MinFL, r_MaxFL, r_MaxRet,
r_CollValid, r_TxFlow, r_RxFlow, r_PassAll,
r_MiiNoPre, r_ClkDiv, r_WCtrlData, r_RStat, r_ScanStat,
r_RGAD, r_FIAD, r_CtrlData, NValid_stat, Busy_stat,
LinkFail, r_MAC, WCtrlDataStart, RStatStart,
UpdateMIIRX_DATAReg, Prsd, r_TxBDNum, int_o,
r_HASH0, r_HASH1, r_TxPauseTV, r_TxPauseRq, RstTxPauseRq, TxCtrlEndFrm,
StartTxDone, TxClk, RxClk, SetPauseTimer
);
parameter Tp = 1;
input [31:0] DataIn;
input [7:0] Address;
input Rw;
input [3:0] Cs;
input Clk;
input Reset;
input WCtrlDataStart;
input RStatStart;
input UpdateMIIRX_DATAReg;
input [15:0] Prsd;
output [31:0] DataOut;
reg [31:0] DataOut;
output r_RecSmall;
output r_Pad;
output r_HugEn;
output r_CrcEn;
output r_DlyCrcEn;
output r_FullD;
output r_ExDfrEn;
output r_NoBckof;
output r_LoopBck;
output r_IFG;
output r_Pro;
output r_Iam;
output r_Bro;
output r_NoPre;
output r_TxEn;
output r_RxEn;
output [31:0] r_HASH0;
output [31:0] r_HASH1;
input TxB_IRQ;
input TxE_IRQ;
input RxB_IRQ;
input RxE_IRQ;
input Busy_IRQ;
output [6:0] r_IPGT;
output [6:0] r_IPGR1;
output [6:0] r_IPGR2;
output [15:0] r_MinFL;
output [15:0] r_MaxFL;
output [3:0] r_MaxRet;
output [5:0] r_CollValid;
output r_TxFlow;
output r_RxFlow;
output r_PassAll;
output r_MiiNoPre;
output [7:0] r_ClkDiv;
output r_WCtrlData;
output r_RStat;
output r_ScanStat;
output [4:0] r_RGAD;
output [4:0] r_FIAD;
output [15:0]r_CtrlData;
input NValid_stat;
input Busy_stat;
input LinkFail;
output [47:0]r_MAC;
output [7:0] r_TxBDNum;
output int_o;
output [15:0]r_TxPauseTV;
output r_TxPauseRq;
input RstTxPauseRq;
input TxCtrlEndFrm;
input StartTxDone;
input TxClk;
input RxClk;
input SetPauseTimer;
reg irq_txb;
reg irq_txe;
reg irq_rxb;
reg irq_rxe;
reg irq_busy;
reg irq_txc;
reg irq_rxc;
reg SetTxCIrq_txclk;
reg SetTxCIrq_sync1, SetTxCIrq_sync2, SetTxCIrq_sync3;
reg SetTxCIrq;
reg ResetTxCIrq_sync1, ResetTxCIrq_sync2;
reg SetRxCIrq_rxclk;
reg SetRxCIrq_sync1, SetRxCIrq_sync2, SetRxCIrq_sync3;
reg SetRxCIrq;
reg ResetRxCIrq_sync1;
reg ResetRxCIrq_sync2;
reg ResetRxCIrq_sync3;
wire [3:0] Write = Cs & {4{Rw}};
wire Read = (|Cs) & ~Rw;
wire MODER_Sel = (Address == `ETH_MODER_ADR );
wire INT_SOURCE_Sel = (Address == `ETH_INT_SOURCE_ADR );
wire INT_MASK_Sel = (Address == `ETH_INT_MASK_ADR );
wire IPGT_Sel = (Address == `ETH_IPGT_ADR );
wire IPGR1_Sel = (Address == `ETH_IPGR1_ADR );
wire IPGR2_Sel = (Address == `ETH_IPGR2_ADR );
wire PACKETLEN_Sel = (Address == `ETH_PACKETLEN_ADR );
wire COLLCONF_Sel = (Address == `ETH_COLLCONF_ADR );
wire CTRLMODER_Sel = (Address == `ETH_CTRLMODER_ADR );
wire MIIMODER_Sel = (Address == `ETH_MIIMODER_ADR );
wire MIICOMMAND_Sel = (Address == `ETH_MIICOMMAND_ADR );
wire MIIADDRESS_Sel = (Address == `ETH_MIIADDRESS_ADR );
wire MIITX_DATA_Sel = (Address == `ETH_MIITX_DATA_ADR );
wire MAC_ADDR0_Sel = (Address == `ETH_MAC_ADDR0_ADR );
wire MAC_ADDR1_Sel = (Address == `ETH_MAC_ADDR1_ADR );
wire HASH0_Sel = (Address == `ETH_HASH0_ADR );
wire HASH1_Sel = (Address == `ETH_HASH1_ADR );
wire TXCTRL_Sel = (Address == `ETH_TX_CTRL_ADR );
wire RXCTRL_Sel = (Address == `ETH_RX_CTRL_ADR );
wire TX_BD_NUM_Sel = (Address == `ETH_TX_BD_NUM_ADR );
wire [2:0] MODER_Wr;
wire [0:0] INT_SOURCE_Wr;
wire [0:0] INT_MASK_Wr;
wire [0:0] IPGT_Wr;
wire [0:0] IPGR1_Wr;
wire [0:0] IPGR2_Wr;
wire [3:0] PACKETLEN_Wr;
wire [2:0] COLLCONF_Wr;
wire [0:0] CTRLMODER_Wr;
wire [1:0] MIIMODER_Wr;
wire [0:0] MIICOMMAND_Wr;
wire [1:0] MIIADDRESS_Wr;
wire [1:0] MIITX_DATA_Wr;
wire MIIRX_DATA_Wr;
wire [3:0] MAC_ADDR0_Wr;
wire [1:0] MAC_ADDR1_Wr;
wire [3:0] HASH0_Wr;
wire [3:0] HASH1_Wr;
wire [2:0] TXCTRL_Wr;
wire [1:0] RXCTRL_Wr;
wire [0:0] TX_BD_NUM_Wr;
assign MODER_Wr[0] = Write[0] & MODER_Sel;
assign MODER_Wr[1] = Write[1] & MODER_Sel;
assign MODER_Wr[2] = Write[2] & MODER_Sel;
assign INT_SOURCE_Wr[0] = Write[0] & INT_SOURCE_Sel;
assign INT_MASK_Wr[0] = Write[0] & INT_MASK_Sel;
assign IPGT_Wr[0] = Write[0] & IPGT_Sel;
assign IPGR1_Wr[0] = Write[0] & IPGR1_Sel;
assign IPGR2_Wr[0] = Write[0] & IPGR2_Sel;
assign PACKETLEN_Wr[0] = Write[0] & PACKETLEN_Sel;
assign PACKETLEN_Wr[1] = Write[1] & PACKETLEN_Sel;
assign PACKETLEN_Wr[2] = Write[2] & PACKETLEN_Sel;
assign PACKETLEN_Wr[3] = Write[3] & PACKETLEN_Sel;
assign COLLCONF_Wr[0] = Write[0] & COLLCONF_Sel;
assign COLLCONF_Wr[1] = 1'b0; // Not used
assign COLLCONF_Wr[2] = Write[2] & COLLCONF_Sel;
assign CTRLMODER_Wr[0] = Write[0] & CTRLMODER_Sel;
assign MIIMODER_Wr[0] = Write[0] & MIIMODER_Sel;
assign MIIMODER_Wr[1] = Write[1] & MIIMODER_Sel;
assign MIICOMMAND_Wr[0] = Write[0] & MIICOMMAND_Sel;
assign MIIADDRESS_Wr[0] = Write[0] & MIIADDRESS_Sel;
assign MIIADDRESS_Wr[1] = Write[1] & MIIADDRESS_Sel;
assign MIITX_DATA_Wr[0] = Write[0] & MIITX_DATA_Sel;
assign MIITX_DATA_Wr[1] = Write[1] & MIITX_DATA_Sel;
assign MIIRX_DATA_Wr = UpdateMIIRX_DATAReg;
assign MAC_ADDR0_Wr[0] = Write[0] & MAC_ADDR0_Sel;
assign MAC_ADDR0_Wr[1] = Write[1] & MAC_ADDR0_Sel;
assign MAC_ADDR0_Wr[2] = Write[2] & MAC_ADDR0_Sel;
assign MAC_ADDR0_Wr[3] = Write[3] & MAC_ADDR0_Sel;
assign MAC_ADDR1_Wr[0] = Write[0] & MAC_ADDR1_Sel;
assign MAC_ADDR1_Wr[1] = Write[1] & MAC_ADDR1_Sel;
assign HASH0_Wr[0] = Write[0] & HASH0_Sel;
assign HASH0_Wr[1] = Write[1] & HASH0_Sel;
assign HASH0_Wr[2] = Write[2] & HASH0_Sel;
assign HASH0_Wr[3] = Write[3] & HASH0_Sel;
assign HASH1_Wr[0] = Write[0] & HASH1_Sel;
assign HASH1_Wr[1] = Write[1] & HASH1_Sel;
assign HASH1_Wr[2] = Write[2] & HASH1_Sel;
assign HASH1_Wr[3] = Write[3] & HASH1_Sel;
assign TXCTRL_Wr[0] = Write[0] & TXCTRL_Sel;
assign TXCTRL_Wr[1] = Write[1] & TXCTRL_Sel;
assign TXCTRL_Wr[2] = Write[2] & TXCTRL_Sel;
assign RXCTRL_Wr[0] = Write[0] & RXCTRL_Sel;
assign RXCTRL_Wr[1] = Write[1] & RXCTRL_Sel;
assign TX_BD_NUM_Wr[0] = Write[0] & TX_BD_NUM_Sel & (DataIn<='h80);
wire [31:0] MODEROut;
wire [31:0] INT_SOURCEOut;
wire [31:0] INT_MASKOut;
wire [31:0] IPGTOut;
wire [31:0] IPGR1Out;
wire [31:0] IPGR2Out;
wire [31:0] PACKETLENOut;
wire [31:0] COLLCONFOut;
wire [31:0] CTRLMODEROut;
wire [31:0] MIIMODEROut;
wire [31:0] MIICOMMANDOut;
wire [31:0] MIIADDRESSOut;
wire [31:0] MIITX_DATAOut;
wire [31:0] MIIRX_DATAOut;
wire [31:0] MIISTATUSOut;
wire [31:0] MAC_ADDR0Out;
wire [31:0] MAC_ADDR1Out;
wire [31:0] TX_BD_NUMOut;
wire [31:0] HASH0Out;
wire [31:0] HASH1Out;
wire [31:0] TXCTRLOut;
wire [31:0] RXCTRLOut;
// MODER Register
eth_register #(`ETH_MODER_WIDTH_0, `ETH_MODER_DEF_0) MODER_0
(
.DataIn (DataIn[`ETH_MODER_WIDTH_0 - 1:0]),
.DataOut (MODEROut[`ETH_MODER_WIDTH_0 - 1:0]),
.Write (MODER_Wr[0]),
.Clk (Clk),
.Reset (Reset),
.SyncReset (1'b0)
);
eth_register #(`ETH_MODER_WIDTH_1, `ETH_MODER_DEF_1) MODER_1
(
.DataIn (DataIn[`ETH_MODER_WIDTH_1 + 7:8]),
.DataOut (MODEROut[`ETH_MODER_WIDTH_1 + 7:8]),
.Write (MODER_Wr[1]),
.Clk (Clk),
.Reset (Reset),
.SyncReset (1'b0)
);
eth_register #(`ETH_MODER_WIDTH_2, `ETH_MODER_DEF_2) MODER_2
(
.DataIn (DataIn[`ETH_MODER_WIDTH_2 + 15:16]),
.DataOut (MODEROut[`ETH_MODER_WIDTH_2 + 15:16]),
.Write (MODER_Wr[2]),
.Clk (Clk),
.Reset (Reset),
.SyncReset (1'b0)
);
assign MODEROut[31:`ETH_MODER_WIDTH_2 + 16] = 0;
// INT_MASK Register
eth_register #(`ETH_INT_MASK_WIDTH_0, `ETH_INT_MASK_DEF_0) INT_MASK_0
(
.DataIn (DataIn[`ETH_INT_MASK_WIDTH_0 - 1:0]),
.DataOut (INT_MASKOut[`ETH_INT_MASK_WIDTH_0 - 1:0]),
.Write (INT_MASK_Wr[0]),
.Clk (Clk),
.Reset (Reset),
.SyncReset (1'b0)
);
assign INT_MASKOut[31:`ETH_INT_MASK_WIDTH_0] = 0;
// IPGT Register
eth_register #(`ETH_IPGT_WIDTH_0, `ETH_IPGT_DEF_0) IPGT_0
(
.DataIn (DataIn[`ETH_IPGT_WIDTH_0 - 1:0]),
.DataOut (IPGTOut[`ETH_IPGT_WIDTH_0 - 1:0]),
.Write (IPGT_Wr[0]),
.Clk (Clk),
.Reset (Reset),
.SyncReset (1'b0)
);
assign IPGTOut[31:`ETH_IPGT_WIDTH_0] = 0;
// IPGR1 Register
eth_register #(`ETH_IPGR1_WIDTH_0, `ETH_IPGR1_DEF_0) IPGR1_0
(
.DataIn (DataIn[`ETH_IPGR1_WIDTH_0 - 1:0]),
.DataOut (IPGR1Out[`ETH_IPGR1_WIDTH_0 - 1:0]),
.Write (IPGR1_Wr[0]),
.Clk (Clk),
.Reset (Reset),
.SyncReset (1'b0)
);
assign IPGR1Out[31:`ETH_IPGR1_WIDTH_0] = 0;
// IPGR2 Register
eth_register #(`ETH_IPGR2_WIDTH_0, `ETH_IPGR2_DEF_0) IPGR2_0
(
.DataIn (DataIn[`ETH_IPGR2_WIDTH_0 - 1:0]),
.DataOut (IPGR2Out[`ETH_IPGR2_WIDTH_0 - 1:0]),
.Write (IPGR2_Wr[0]),
.Clk (Clk),
.Reset (Reset),
.SyncReset (1'b0)
);
assign IPGR2Out[31:`ETH_IPGR2_WIDTH_0] = 0;
// PACKETLEN Register
eth_register #(`ETH_PACKETLEN_WIDTH_0, `ETH_PACKETLEN_DEF_0) PACKETLEN_0
(
.DataIn (DataIn[`ETH_PACKETLEN_WIDTH_0 - 1:0]),
.DataOut (PACKETLENOut[`ETH_PACKETLEN_WIDTH_0 - 1:0]),
.Write (PACKETLEN_Wr[0]),
.Clk (Clk),
.Reset (Reset),
.SyncReset (1'b0)
);
eth_register #(`ETH_PACKETLEN_WIDTH_1, `ETH_PACKETLEN_DEF_1) PACKETLEN_1
(
.DataIn (DataIn[`ETH_PACKETLEN_WIDTH_1 + 7:8]),
.DataOut (PACKETLENOut[`ETH_PACKETLEN_WIDTH_1 + 7:8]),
.Write (PACKETLEN_Wr[1]),
.Clk (Clk),
.Reset (Reset),
.SyncReset (1'b0)
);
eth_register #(`ETH_PACKETLEN_WIDTH_2, `ETH_PACKETLEN_DEF_2) PACKETLEN_2
(
.DataIn (DataIn[`ETH_PACKETLEN_WIDTH_2 + 15:16]),
.DataOut (PACKETLENOut[`ETH_PACKETLEN_WIDTH_2 + 15:16]),
.Write (PACKETLEN_Wr[2]),
.Clk (Clk),
.Reset (Reset),
.SyncReset (1'b0)
);
eth_register #(`ETH_PACKETLEN_WIDTH_3, `ETH_PACKETLEN_DEF_3) PACKETLEN_3
(
.DataIn (DataIn[`ETH_PACKETLEN_WIDTH_3 + 23:24]),
.DataOut (PACKETLENOut[`ETH_PACKETLEN_WIDTH_3 + 23:24]),
.Write (PACKETLEN_Wr[3]),
.Clk (Clk),
.Reset (Reset),
.SyncReset (1'b0)
);
// COLLCONF Register
eth_register #(`ETH_COLLCONF_WIDTH_0, `ETH_COLLCONF_DEF_0) COLLCONF_0
(
.DataIn (DataIn[`ETH_COLLCONF_WIDTH_0 - 1:0]),
.DataOut (COLLCONFOut[`ETH_COLLCONF_WIDTH_0 - 1:0]),
.Write (COLLCONF_Wr[0]),
.Clk (Clk),
.Reset (Reset),
.SyncReset (1'b0)
);
eth_register #(`ETH_COLLCONF_WIDTH_2, `ETH_COLLCONF_DEF_2) COLLCONF_2
(
.DataIn (DataIn[`ETH_COLLCONF_WIDTH_2 + 15:16]),
.DataOut (COLLCONFOut[`ETH_COLLCONF_WIDTH_2 + 15:16]),
.Write (COLLCONF_Wr[2]),
.Clk (Clk),
.Reset (Reset),
.SyncReset (1'b0)
);
assign COLLCONFOut[15:`ETH_COLLCONF_WIDTH_0] = 0;
assign COLLCONFOut[31:`ETH_COLLCONF_WIDTH_2 + 16] = 0;
// TX_BD_NUM Register
eth_register #(`ETH_TX_BD_NUM_WIDTH_0, `ETH_TX_BD_NUM_DEF_0) TX_BD_NUM_0
(
.DataIn (DataIn[`ETH_TX_BD_NUM_WIDTH_0 - 1:0]),
.DataOut (TX_BD_NUMOut[`ETH_TX_BD_NUM_WIDTH_0 - 1:0]),
.Write (TX_BD_NUM_Wr[0]),
.Clk (Clk),
.Reset (Reset),
.SyncReset (1'b0)
);
assign TX_BD_NUMOut[31:`ETH_TX_BD_NUM_WIDTH_0] = 0;
// CTRLMODER Register
eth_register #(`ETH_CTRLMODER_WIDTH_0, `ETH_CTRLMODER_DEF_0) CTRLMODER_0
(
.DataIn (DataIn[`ETH_CTRLMODER_WIDTH_0 - 1:0]),
.DataOut (CTRLMODEROut[`ETH_CTRLMODER_WIDTH_0 - 1:0]),
.Write (CTRLMODER_Wr[0]),
.Clk (Clk),
.Reset (Reset),
.SyncReset (1'b0)
);
assign CTRLMODEROut[31:`ETH_CTRLMODER_WIDTH_0] = 0;
// MIIMODER Register
eth_register #(`ETH_MIIMODER_WIDTH_0, `ETH_MIIMODER_DEF_0) MIIMODER_0
(
.DataIn (DataIn[`ETH_MIIMODER_WIDTH_0 - 1:0]),
.DataOut (MIIMODEROut[`ETH_MIIMODER_WIDTH_0 - 1:0]),
.Write (MIIMODER_Wr[0]),
.Clk (Clk),
.Reset (Reset),
.SyncReset (1'b0)
);
eth_register #(`ETH_MIIMODER_WIDTH_1, `ETH_MIIMODER_DEF_1) MIIMODER_1
(
.DataIn (DataIn[`ETH_MIIMODER_WIDTH_1 + 7:8]),
.DataOut (MIIMODEROut[`ETH_MIIMODER_WIDTH_1 + 7:8]),
.Write (MIIMODER_Wr[1]),
.Clk (Clk),
.Reset (Reset),
.SyncReset (1'b0)
);
assign MIIMODEROut[31:`ETH_MIIMODER_WIDTH_1 + 8] = 0;
// MIICOMMAND Register
eth_register #(1, 0) MIICOMMAND0
(
.DataIn (DataIn[0]),
.DataOut (MIICOMMANDOut[0]),
.Write (MIICOMMAND_Wr[0]),
.Clk (Clk),
.Reset (Reset),
.SyncReset (1'b0)
);
eth_register #(1, 0) MIICOMMAND1
(
.DataIn (DataIn[1]),
.DataOut (MIICOMMANDOut[1]),
.Write (MIICOMMAND_Wr[0]),
.Clk (Clk),
.Reset (Reset),
.SyncReset (RStatStart)
);
eth_register #(1, 0) MIICOMMAND2
(
.DataIn (DataIn[2]),
.DataOut (MIICOMMANDOut[2]),
.Write (MIICOMMAND_Wr[0]),
.Clk (Clk),
.Reset (Reset),
.SyncReset (WCtrlDataStart)
);
assign MIICOMMANDOut[31:`ETH_MIICOMMAND_WIDTH_0] = 29'h0;
// MIIADDRESSRegister
eth_register #(`ETH_MIIADDRESS_WIDTH_0, `ETH_MIIADDRESS_DEF_0) MIIADDRESS_0
(
.DataIn (DataIn[`ETH_MIIADDRESS_WIDTH_0 - 1:0]),
.DataOut (MIIADDRESSOut[`ETH_MIIADDRESS_WIDTH_0 - 1:0]),
.Write (MIIADDRESS_Wr[0]),
.Clk (Clk),
.Reset (Reset),
.SyncReset (1'b0)
);
eth_register #(`ETH_MIIADDRESS_WIDTH_1, `ETH_MIIADDRESS_DEF_1) MIIADDRESS_1
(
.DataIn (DataIn[`ETH_MIIADDRESS_WIDTH_1 + 7:8]),
.DataOut (MIIADDRESSOut[`ETH_MIIADDRESS_WIDTH_1 + 7:8]),
.Write (MIIADDRESS_Wr[1]),
.Clk (Clk),
.Reset (Reset),
.SyncReset (1'b0)
);
assign MIIADDRESSOut[7:`ETH_MIIADDRESS_WIDTH_0] = 0;
assign MIIADDRESSOut[31:`ETH_MIIADDRESS_WIDTH_1 + 8] = 0;
// MIITX_DATA Register
eth_register #(`ETH_MIITX_DATA_WIDTH_0, `ETH_MIITX_DATA_DEF_0) MIITX_DATA_0
(
.DataIn (DataIn[`ETH_MIITX_DATA_WIDTH_0 - 1:0]),
.DataOut (MIITX_DATAOut[`ETH_MIITX_DATA_WIDTH_0 - 1:0]),
.Write (MIITX_DATA_Wr[0]),
.Clk (Clk),
.Reset (Reset),
.SyncReset (1'b0)
);
eth_register #(`ETH_MIITX_DATA_WIDTH_1, `ETH_MIITX_DATA_DEF_1) MIITX_DATA_1
(
.DataIn (DataIn[`ETH_MIITX_DATA_WIDTH_1 + 7:8]),
.DataOut (MIITX_DATAOut[`ETH_MIITX_DATA_WIDTH_1 + 7:8]),
.Write (MIITX_DATA_Wr[1]),
.Clk (Clk),
.Reset (Reset),
.SyncReset (1'b0)
);
assign MIITX_DATAOut[31:`ETH_MIITX_DATA_WIDTH_1 + 8] = 0;
// MIIRX_DATA Register
eth_register #(`ETH_MIIRX_DATA_WIDTH, `ETH_MIIRX_DATA_DEF) MIIRX_DATA
(
.DataIn (Prsd[`ETH_MIIRX_DATA_WIDTH-1:0]),
.DataOut (MIIRX_DATAOut[`ETH_MIIRX_DATA_WIDTH-1:0]),
.Write (MIIRX_DATA_Wr), // not written from WB
.Clk (Clk),
.Reset (Reset),
.SyncReset (1'b0)
);
assign MIIRX_DATAOut[31:`ETH_MIIRX_DATA_WIDTH] = 0;
// MAC_ADDR0 Register
eth_register #(`ETH_MAC_ADDR0_WIDTH_0, `ETH_MAC_ADDR0_DEF_0) MAC_ADDR0_0
(
.DataIn (DataIn[`ETH_MAC_ADDR0_WIDTH_0 - 1:0]),
.DataOut (MAC_ADDR0Out[`ETH_MAC_ADDR0_WIDTH_0 - 1:0]),
.Write (MAC_ADDR0_Wr[0]),
.Clk (Clk),
.Reset (Reset),
.SyncReset (1'b0)
);
eth_register #(`ETH_MAC_ADDR0_WIDTH_1, `ETH_MAC_ADDR0_DEF_1) MAC_ADDR0_1
(
.DataIn (DataIn[`ETH_MAC_ADDR0_WIDTH_1 + 7:8]),
.DataOut (MAC_ADDR0Out[`ETH_MAC_ADDR0_WIDTH_1 + 7:8]),
.Write (MAC_ADDR0_Wr[1]),
.Clk (Clk),
.Reset (Reset),
.SyncReset (1'b0)
);
eth_register #(`ETH_MAC_ADDR0_WIDTH_2, `ETH_MAC_ADDR0_DEF_2) MAC_ADDR0_2
(
.DataIn (DataIn[`ETH_MAC_ADDR0_WIDTH_2 + 15:16]),
.DataOut (MAC_ADDR0Out[`ETH_MAC_ADDR0_WIDTH_2 + 15:16]),
.Write (MAC_ADDR0_Wr[2]),
.Clk (Clk),
.Reset (Reset),
.SyncReset (1'b0)
);
eth_register #(`ETH_MAC_ADDR0_WIDTH_3, `ETH_MAC_ADDR0_DEF_3) MAC_ADDR0_3
(
.DataIn (DataIn[`ETH_MAC_ADDR0_WIDTH_3 + 23:24]),
.DataOut (MAC_ADDR0Out[`ETH_MAC_ADDR0_WIDTH_3 + 23:24]),
.Write (MAC_ADDR0_Wr[3]),
.Clk (Clk),
.Reset (Reset),
.SyncReset (1'b0)
);
// MAC_ADDR1 Register
eth_register #(`ETH_MAC_ADDR1_WIDTH_0, `ETH_MAC_ADDR1_DEF_0) MAC_ADDR1_0
(
.DataIn (DataIn[`ETH_MAC_ADDR1_WIDTH_0 - 1:0]),
.DataOut (MAC_ADDR1Out[`ETH_MAC_ADDR1_WIDTH_0 - 1:0]),
.Write (MAC_ADDR1_Wr[0]),
.Clk (Clk),
.Reset (Reset),
.SyncReset (1'b0)
);
eth_register #(`ETH_MAC_ADDR1_WIDTH_1, `ETH_MAC_ADDR1_DEF_1) MAC_ADDR1_1
(
.DataIn (DataIn[`ETH_MAC_ADDR1_WIDTH_1 + 7:8]),
.DataOut (MAC_ADDR1Out[`ETH_MAC_ADDR1_WIDTH_1 + 7:8]),
.Write (MAC_ADDR1_Wr[1]),
.Clk (Clk),
.Reset (Reset),
.SyncReset (1'b0)
);
assign MAC_ADDR1Out[31:`ETH_MAC_ADDR1_WIDTH_1 + 8] = 0;
// RXHASH0 Register
eth_register #(`ETH_HASH0_WIDTH_0, `ETH_HASH0_DEF_0) RXHASH0_0
(
.DataIn (DataIn[`ETH_HASH0_WIDTH_0 - 1:0]),
.DataOut (HASH0Out[`ETH_HASH0_WIDTH_0 - 1:0]),
.Write (HASH0_Wr[0]),
.Clk (Clk),
.Reset (Reset),
.SyncReset (1'b0)
);
eth_register #(`ETH_HASH0_WIDTH_1, `ETH_HASH0_DEF_1) RXHASH0_1
(
.DataIn (DataIn[`ETH_HASH0_WIDTH_1 + 7:8]),
.DataOut (HASH0Out[`ETH_HASH0_WIDTH_1 + 7:8]),
.Write (HASH0_Wr[1]),
.Clk (Clk),
.Reset (Reset),
.SyncReset (1'b0)
);
eth_register #(`ETH_HASH0_WIDTH_2, `ETH_HASH0_DEF_2) RXHASH0_2
(
.DataIn (DataIn[`ETH_HASH0_WIDTH_2 + 15:16]),
.DataOut (HASH0Out[`ETH_HASH0_WIDTH_2 + 15:16]),
.Write (HASH0_Wr[2]),
.Clk (Clk),
.Reset (Reset),
.SyncReset (1'b0)
);
eth_register #(`ETH_HASH0_WIDTH_3, `ETH_HASH0_DEF_3) RXHASH0_3
(
.DataIn (DataIn[`ETH_HASH0_WIDTH_3 + 23:24]),
.DataOut (HASH0Out[`ETH_HASH0_WIDTH_3 + 23:24]),
.Write (HASH0_Wr[3]),
.Clk (Clk),
.Reset (Reset),
.SyncReset (1'b0)
);
// RXHASH1 Register
eth_register #(`ETH_HASH1_WIDTH_0, `ETH_HASH1_DEF_0) RXHASH1_0
(
.DataIn (DataIn[`ETH_HASH1_WIDTH_0 - 1:0]),
.DataOut (HASH1Out[`ETH_HASH1_WIDTH_0 - 1:0]),
.Write (HASH1_Wr[0]),
.Clk (Clk),
.Reset (Reset),
.SyncReset (1'b0)
);
eth_register #(`ETH_HASH1_WIDTH_1, `ETH_HASH1_DEF_1) RXHASH1_1
(
.DataIn (DataIn[`ETH_HASH1_WIDTH_1 + 7:8]),
.DataOut (HASH1Out[`ETH_HASH1_WIDTH_1 + 7:8]),
.Write (HASH1_Wr[1]),
.Clk (Clk),
.Reset (Reset),
.SyncReset (1'b0)
);
eth_register #(`ETH_HASH1_WIDTH_2, `ETH_HASH1_DEF_2) RXHASH1_2
(
.DataIn (DataIn[`ETH_HASH1_WIDTH_2 + 15:16]),
.DataOut (HASH1Out[`ETH_HASH1_WIDTH_2 + 15:16]),
.Write (HASH1_Wr[2]),
.Clk (Clk),
.Reset (Reset),
.SyncReset (1'b0)
);
eth_register #(`ETH_HASH1_WIDTH_3, `ETH_HASH1_DEF_3) RXHASH1_3
(
.DataIn (DataIn[`ETH_HASH1_WIDTH_3 + 23:24]),
.DataOut (HASH1Out[`ETH_HASH1_WIDTH_3 + 23:24]),
.Write (HASH1_Wr[3]),
.Clk (Clk),
.Reset (Reset),
.SyncReset (1'b0)
);
// TXCTRL Register
eth_register #(`ETH_TX_CTRL_WIDTH_0, `ETH_TX_CTRL_DEF_0) TXCTRL_0
(
.DataIn (DataIn[`ETH_TX_CTRL_WIDTH_0 - 1:0]),
.DataOut (TXCTRLOut[`ETH_TX_CTRL_WIDTH_0 - 1:0]),
.Write (TXCTRL_Wr[0]),
.Clk (Clk),
.Reset (Reset),
.SyncReset (1'b0)
);
eth_register #(`ETH_TX_CTRL_WIDTH_1, `ETH_TX_CTRL_DEF_1) TXCTRL_1
(
.DataIn (DataIn[`ETH_TX_CTRL_WIDTH_1 + 7:8]),
.DataOut (TXCTRLOut[`ETH_TX_CTRL_WIDTH_1 + 7:8]),
.Write (TXCTRL_Wr[1]),
.Clk (Clk),
.Reset (Reset),
.SyncReset (1'b0)
);
eth_register #(`ETH_TX_CTRL_WIDTH_2, `ETH_TX_CTRL_DEF_2) TXCTRL_2 // Request bit is synchronously reset
(
.DataIn (DataIn[`ETH_TX_CTRL_WIDTH_2 + 15:16]),
.DataOut (TXCTRLOut[`ETH_TX_CTRL_WIDTH_2 + 15:16]),
.Write (TXCTRL_Wr[2]),
.Clk (Clk),
.Reset (Reset),
.SyncReset (RstTxPauseRq)
);
assign TXCTRLOut[31:`ETH_TX_CTRL_WIDTH_2 + 16] = 0;
// RXCTRL Register
eth_register #(`ETH_RX_CTRL_WIDTH_0, `ETH_RX_CTRL_DEF_0) RXCTRL_0
(
.DataIn (DataIn[`ETH_RX_CTRL_WIDTH_0 - 1:0]),
.DataOut (RXCTRLOut[`ETH_RX_CTRL_WIDTH_0 - 1:0]),
.Write (RXCTRL_Wr[0]),
.Clk (Clk),
.Reset (Reset),
.SyncReset (1'b0)
);
eth_register #(`ETH_RX_CTRL_WIDTH_1, `ETH_RX_CTRL_DEF_1) RXCTRL_1
(
.DataIn (DataIn[`ETH_RX_CTRL_WIDTH_1 + 7:8]),
.DataOut (RXCTRLOut[`ETH_RX_CTRL_WIDTH_1 + 7:8]),
.Write (RXCTRL_Wr[1]),
.Clk (Clk),
.Reset (Reset),
.SyncReset (1'b0)
);
assign RXCTRLOut[31:`ETH_RX_CTRL_WIDTH_1 + 8] = 0;
// Reading data from registers
always @ (Address or Read or MODEROut or INT_SOURCEOut or
INT_MASKOut or IPGTOut or IPGR1Out or IPGR2Out or
PACKETLENOut or COLLCONFOut or CTRLMODEROut or MIIMODEROut or
MIICOMMANDOut or MIIADDRESSOut or MIITX_DATAOut or MIIRX_DATAOut or
MIISTATUSOut or MAC_ADDR0Out or MAC_ADDR1Out or TX_BD_NUMOut or
HASH0Out or HASH1Out or TXCTRLOut or RXCTRLOut
)
begin
if(Read) // read
begin
case(Address)
`ETH_MODER_ADR : DataOut<=MODEROut;
`ETH_INT_SOURCE_ADR : DataOut<=INT_SOURCEOut;
`ETH_INT_MASK_ADR : DataOut<=INT_MASKOut;
`ETH_IPGT_ADR : DataOut<=IPGTOut;
`ETH_IPGR1_ADR : DataOut<=IPGR1Out;
`ETH_IPGR2_ADR : DataOut<=IPGR2Out;
`ETH_PACKETLEN_ADR : DataOut<=PACKETLENOut;
`ETH_COLLCONF_ADR : DataOut<=COLLCONFOut;
`ETH_CTRLMODER_ADR : DataOut<=CTRLMODEROut;
`ETH_MIIMODER_ADR : DataOut<=MIIMODEROut;
`ETH_MIICOMMAND_ADR : DataOut<=MIICOMMANDOut;
`ETH_MIIADDRESS_ADR : DataOut<=MIIADDRESSOut;
`ETH_MIITX_DATA_ADR : DataOut<=MIITX_DATAOut;
`ETH_MIIRX_DATA_ADR : DataOut<=MIIRX_DATAOut;
`ETH_MIISTATUS_ADR : DataOut<=MIISTATUSOut;
`ETH_MAC_ADDR0_ADR : DataOut<=MAC_ADDR0Out;
`ETH_MAC_ADDR1_ADR : DataOut<=MAC_ADDR1Out;
`ETH_TX_BD_NUM_ADR : DataOut<=TX_BD_NUMOut;
`ETH_HASH0_ADR : DataOut<=HASH0Out;
`ETH_HASH1_ADR : DataOut<=HASH1Out;
`ETH_TX_CTRL_ADR : DataOut<=TXCTRLOut;
`ETH_RX_CTRL_ADR : DataOut<=RXCTRLOut;
default: DataOut<=32'h0;
endcase
end
else
DataOut<=32'h0;
end
assign r_RecSmall = MODEROut[16];
assign r_Pad = MODEROut[15];
assign r_HugEn = MODEROut[14];
assign r_CrcEn = MODEROut[13];
assign r_DlyCrcEn = MODEROut[12];
// assign r_Rst = MODEROut[11]; This signal is not used any more
assign r_FullD = MODEROut[10];
assign r_ExDfrEn = MODEROut[9];
assign r_NoBckof = MODEROut[8];
assign r_LoopBck = MODEROut[7];
assign r_IFG = MODEROut[6];
assign r_Pro = MODEROut[5];
assign r_Iam = MODEROut[4];
assign r_Bro = MODEROut[3];
assign r_NoPre = MODEROut[2];
assign r_TxEn = MODEROut[1] & (TX_BD_NUMOut>0); // Transmission is enabled when there is at least one TxBD.
assign r_RxEn = MODEROut[0] & (TX_BD_NUMOut<'h80); // Reception is enabled when there is at least one RxBD.
assign r_IPGT[6:0] = IPGTOut[6:0];
assign r_IPGR1[6:0] = IPGR1Out[6:0];
assign r_IPGR2[6:0] = IPGR2Out[6:0];
assign r_MinFL[15:0] = PACKETLENOut[31:16];
assign r_MaxFL[15:0] = PACKETLENOut[15:0];
assign r_MaxRet[3:0] = COLLCONFOut[19:16];
assign r_CollValid[5:0] = COLLCONFOut[5:0];
assign r_TxFlow = CTRLMODEROut[2];
assign r_RxFlow = CTRLMODEROut[1];
assign r_PassAll = CTRLMODEROut[0];
assign r_MiiNoPre = MIIMODEROut[8];
assign r_ClkDiv[7:0] = MIIMODEROut[7:0];
assign r_WCtrlData = MIICOMMANDOut[2];
assign r_RStat = MIICOMMANDOut[1];
assign r_ScanStat = MIICOMMANDOut[0];
assign r_RGAD[4:0] = MIIADDRESSOut[12:8];
assign r_FIAD[4:0] = MIIADDRESSOut[4:0];
assign r_CtrlData[15:0] = MIITX_DATAOut[15:0];
assign MIISTATUSOut[31:`ETH_MIISTATUS_WIDTH] = 0;
assign MIISTATUSOut[2] = NValid_stat ;
assign MIISTATUSOut[1] = Busy_stat ;
assign MIISTATUSOut[0] = LinkFail ;
assign r_MAC[31:0] = MAC_ADDR0Out[31:0];
assign r_MAC[47:32] = MAC_ADDR1Out[15:0];
assign r_HASH1[31:0] = HASH1Out;
assign r_HASH0[31:0] = HASH0Out;
assign r_TxBDNum[7:0] = TX_BD_NUMOut[7:0];
assign r_TxPauseTV[15:0] = TXCTRLOut[15:0];
assign r_TxPauseRq = TXCTRLOut[16];
// Synchronizing TxC Interrupt
always @ (posedge TxClk or posedge Reset)
begin
if(Reset)
SetTxCIrq_txclk <=#Tp 1'b0;
else
if(TxCtrlEndFrm & StartTxDone & r_TxFlow)
SetTxCIrq_txclk <=#Tp 1'b1;
else
if(ResetTxCIrq_sync2)
SetTxCIrq_txclk <=#Tp 1'b0;
end
always @ (posedge Clk or posedge Reset)
begin
if(Reset)
SetTxCIrq_sync1 <=#Tp 1'b0;
else
SetTxCIrq_sync1 <=#Tp SetTxCIrq_txclk;
end
always @ (posedge Clk or posedge Reset)
begin
if(Reset)
SetTxCIrq_sync2 <=#Tp 1'b0;
else
SetTxCIrq_sync2 <=#Tp SetTxCIrq_sync1;
end
always @ (posedge Clk or posedge Reset)
begin
if(Reset)
SetTxCIrq_sync3 <=#Tp 1'b0;
else
SetTxCIrq_sync3 <=#Tp SetTxCIrq_sync2;
end
always @ (posedge Clk or posedge Reset)
begin
if(Reset)
SetTxCIrq <=#Tp 1'b0;
else
SetTxCIrq <=#Tp SetTxCIrq_sync2 & ~SetTxCIrq_sync3;
end
always @ (posedge TxClk or posedge Reset)
begin
if(Reset)
ResetTxCIrq_sync1 <=#Tp 1'b0;
else
ResetTxCIrq_sync1 <=#Tp SetTxCIrq_sync2;
end
always @ (posedge TxClk or posedge Reset)
begin
if(Reset)
ResetTxCIrq_sync2 <=#Tp 1'b0;
else
ResetTxCIrq_sync2 <=#Tp SetTxCIrq_sync1;
end
// Synchronizing RxC Interrupt
always @ (posedge RxClk or posedge Reset)
begin
if(Reset)
SetRxCIrq_rxclk <=#Tp 1'b0;
else
if(SetPauseTimer & r_RxFlow)
SetRxCIrq_rxclk <=#Tp 1'b1;
else
if(ResetRxCIrq_sync2 & (~ResetRxCIrq_sync3))
SetRxCIrq_rxclk <=#Tp 1'b0;
end
always @ (posedge Clk or posedge Reset)
begin
if(Reset)
SetRxCIrq_sync1 <=#Tp 1'b0;
else
SetRxCIrq_sync1 <=#Tp SetRxCIrq_rxclk;
end
always @ (posedge Clk or posedge Reset)
begin
if(Reset)
SetRxCIrq_sync2 <=#Tp 1'b0;
else
SetRxCIrq_sync2 <=#Tp SetRxCIrq_sync1;
end
always @ (posedge Clk or posedge Reset)
begin
if(Reset)
SetRxCIrq_sync3 <=#Tp 1'b0;
else
SetRxCIrq_sync3 <=#Tp SetRxCIrq_sync2;
end
always @ (posedge Clk or posedge Reset)
begin
if(Reset)
SetRxCIrq <=#Tp 1'b0;
else
SetRxCIrq <=#Tp SetRxCIrq_sync2 & ~SetRxCIrq_sync3;
end
always @ (posedge RxClk or posedge Reset)
begin
if(Reset)
ResetRxCIrq_sync1 <=#Tp 1'b0;
else
ResetRxCIrq_sync1 <=#Tp SetRxCIrq_sync2;
end
always @ (posedge RxClk or posedge Reset)
begin
if(Reset)
ResetRxCIrq_sync2 <=#Tp 1'b0;
else
ResetRxCIrq_sync2 <=#Tp ResetRxCIrq_sync1;
end
always @ (posedge RxClk or posedge Reset)
begin
if(Reset)
ResetRxCIrq_sync3 <=#Tp 1'b0;
else
ResetRxCIrq_sync3 <=#Tp ResetRxCIrq_sync2;
end
// Interrupt generation
always @ (posedge Clk or posedge Reset)
begin
if(Reset)
irq_txb <= 1'b0;
else
if(TxB_IRQ)
irq_txb <= #Tp 1'b1;
else
if(INT_SOURCE_Wr[0] & DataIn[0])
irq_txb <= #Tp 1'b0;
end
always @ (posedge Clk or posedge Reset)
begin
if(Reset)
irq_txe <= 1'b0;
else
if(TxE_IRQ)
irq_txe <= #Tp 1'b1;
else
if(INT_SOURCE_Wr[0] & DataIn[1])
irq_txe <= #Tp 1'b0;
end
always @ (posedge Clk or posedge Reset)
begin
if(Reset)
irq_rxb <= 1'b0;
else
if(RxB_IRQ)
irq_rxb <= #Tp 1'b1;
else
if(INT_SOURCE_Wr[0] & DataIn[2])
irq_rxb <= #Tp 1'b0;
end
always @ (posedge Clk or posedge Reset)
begin
if(Reset)
irq_rxe <= 1'b0;
else
if(RxE_IRQ)
irq_rxe <= #Tp 1'b1;
else
if(INT_SOURCE_Wr[0] & DataIn[3])
irq_rxe <= #Tp 1'b0;
end
always @ (posedge Clk or posedge Reset)
begin
if(Reset)
irq_busy <= 1'b0;
else
if(Busy_IRQ)
irq_busy <= #Tp 1'b1;
else
if(INT_SOURCE_Wr[0] & DataIn[4])
irq_busy <= #Tp 1'b0;
end
always @ (posedge Clk or posedge Reset)
begin
if(Reset)
irq_txc <= 1'b0;
else
if(SetTxCIrq)
irq_txc <= #Tp 1'b1;
else
if(INT_SOURCE_Wr[0] & DataIn[5])
irq_txc <= #Tp 1'b0;
end
always @ (posedge Clk or posedge Reset)
begin
if(Reset)
irq_rxc <= 1'b0;
else
if(SetRxCIrq)
irq_rxc <= #Tp 1'b1;
else
if(INT_SOURCE_Wr[0] & DataIn[6])
irq_rxc <= #Tp 1'b0;
end
// Generating interrupt signal
assign int_o = irq_txb & INT_MASKOut[0] |
irq_txe & INT_MASKOut[1] |
irq_rxb & INT_MASKOut[2] |
irq_rxe & INT_MASKOut[3] |
irq_busy & INT_MASKOut[4] |
irq_txc & INT_MASKOut[5] |
irq_rxc & INT_MASKOut[6] ;
// For reading interrupt status
assign INT_SOURCEOut = {{(32-`ETH_INT_SOURCE_WIDTH_0){1'b0}}, irq_rxc, irq_txc, irq_busy, irq_rxe, irq_rxb, irq_txe, irq_txb};
endmodule
//////////////////////////////////////////////////////////////////////
//// ////
//// eth_rxaddrcheck.v ////
//// ////
//// This file is part of the Ethernet IP core project ////
//// http://www.opencores.org/cores/ethmac/ ////
//// ////
//// Author(s): ////
//// - Bill Dittenhofer ([email protected]) ////
//// ////
//// All additional information is avaliable in the Readme.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: eth_rxaddrcheck.v,v $
// Revision 1.9 2002/11/22 01:57:06 mohor
// Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort
// synchronized.
//
// Revision 1.8 2002/11/19 17:34:52 mohor
// AddressMiss status is connecting to the Rx BD. AddressMiss is identifying
// that a frame was received because of the promiscous mode.
//
// Revision 1.7 2002/09/04 18:41:06 mohor
// Bug when last byte of destination address was not checked fixed.
//
// Revision 1.6 2002/03/20 15:14:11 mohor
// When in promiscous mode some frames were not received correctly. Fixed.
//
// Revision 1.5 2002/03/02 21:06:32 mohor
// Log info was missing.
//
//
// Revision 1.1 2002/02/08 12:51:54 ditt
// Initial release of the ethernet addresscheck module.
//
//
//
//
//
module eth_rxaddrcheck(MRxClk, Reset, RxData, Broadcast ,r_Bro ,r_Pro,
ByteCntEq2, ByteCntEq3, ByteCntEq4, ByteCntEq5,
ByteCntEq6, ByteCntEq7, HASH0, HASH1,
CrcHash, CrcHashGood, StateData, RxEndFrm,
Multicast, MAC, RxAbort, AddressMiss, PassAll,
ControlFrmAddressOK
);
parameter Tp = 1;
input MRxClk;
input Reset;
input [7:0] RxData;
input Broadcast;
input r_Bro;
input r_Pro;
input ByteCntEq2;
input ByteCntEq3;
input ByteCntEq4;
input ByteCntEq5;
input ByteCntEq6;
input ByteCntEq7;
input [31:0] HASH0;
input [31:0] HASH1;
input [5:0] CrcHash;
input CrcHashGood;
input Multicast;
input [47:0] MAC;
input [1:0] StateData;
input RxEndFrm;
input PassAll;
input ControlFrmAddressOK;
output RxAbort;
output AddressMiss;
wire BroadcastOK;
wire ByteCntEq2;
wire ByteCntEq3;
wire ByteCntEq4;
wire ByteCntEq5;
wire RxAddressInvalid;
wire RxCheckEn;
wire HashBit;
wire [31:0] IntHash;
reg [7:0] ByteHash;
reg MulticastOK;
reg UnicastOK;
reg RxAbort;
reg AddressMiss;
assign RxAddressInvalid = ~(UnicastOK | BroadcastOK | MulticastOK | r_Pro);
assign BroadcastOK = Broadcast & ~r_Bro;
assign RxCheckEn = | StateData;
// Address Error Reported at end of address cycle
// RxAbort clears after one cycle
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
RxAbort <= #Tp 1'b0;
else if(RxAddressInvalid & ByteCntEq7 & RxCheckEn)
RxAbort <= #Tp 1'b1;
else
RxAbort <= #Tp 1'b0;
end
// This ff holds the "Address Miss" information that is written to the RX BD status.
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
AddressMiss <= #Tp 1'b0;
else if(ByteCntEq7 & RxCheckEn)
AddressMiss <= #Tp (~(UnicastOK | BroadcastOK | MulticastOK | (PassAll & ControlFrmAddressOK)));
end
// Hash Address Check, Multicast
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
MulticastOK <= #Tp 1'b0;
else if(RxEndFrm | RxAbort)
MulticastOK <= #Tp 1'b0;
else if(CrcHashGood & Multicast)
MulticastOK <= #Tp HashBit;
end
// Address Detection (unicast)
// start with ByteCntEq2 due to delay of addres from RxData
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
UnicastOK <= #Tp 1'b0;
else
if(RxCheckEn & ByteCntEq2)
UnicastOK <= #Tp RxData[7:0] == MAC[47:40];
else
if(RxCheckEn & ByteCntEq3)
UnicastOK <= #Tp ( RxData[7:0] == MAC[39:32]) & UnicastOK;
else
if(RxCheckEn & ByteCntEq4)
UnicastOK <= #Tp ( RxData[7:0] == MAC[31:24]) & UnicastOK;
else
if(RxCheckEn & ByteCntEq5)
UnicastOK <= #Tp ( RxData[7:0] == MAC[23:16]) & UnicastOK;
else
if(RxCheckEn & ByteCntEq6)
UnicastOK <= #Tp ( RxData[7:0] == MAC[15:8]) & UnicastOK;
else
if(RxCheckEn & ByteCntEq7)
UnicastOK <= #Tp ( RxData[7:0] == MAC[7:0]) & UnicastOK;
else
if(RxEndFrm | RxAbort)
UnicastOK <= #Tp 1'b0;
end
assign IntHash = (CrcHash[5])? HASH1 : HASH0;
always@(CrcHash or IntHash)
begin
case(CrcHash[4:3])
2'b00: ByteHash = IntHash[7:0];
2'b01: ByteHash = IntHash[15:8];
2'b10: ByteHash = IntHash[23:16];
2'b11: ByteHash = IntHash[31:24];
endcase
end
assign HashBit = ByteHash[CrcHash[2:0]];
endmodule
//////////////////////////////////////////////////////////////////////
//// ////
//// eth_rxcounters.v ////
//// ////
//// This file is part of the Ethernet IP core project ////
//// http://www.opencores.org/projects/ethmac/ ////
//// ////
//// Author(s): ////
//// - Igor Mohor ([email protected]) ////
//// - Novan Hartadi ([email protected]) ////
//// - Mahmud Galela ([email protected]) ////
//// ////
//// All additional information is avaliable in the Readme.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: eth_rxcounters.v,v $
// Revision 1.5 2002/02/15 11:13:29 mohor
// Format of the file changed a bit.
//
// Revision 1.4 2002/02/14 20:19:41 billditt
// Modified for Address Checking,
// addition of eth_addrcheck.v
//
// Revision 1.3 2002/01/23 10:28:16 mohor
// Link in the header changed.
//
// Revision 1.2 2001/10/19 08:43:51 mohor
// eth_timescale.v changed to timescale.v This is done because of the
// simulation of the few cores in a one joined project.
//
// Revision 1.1 2001/08/06 14:44:29 mohor
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
// Include files fixed to contain no path.
// File names and module names changed ta have a eth_ prologue in the name.
// File eth_timescale.v is used to define timescale
// All pin names on the top module are changed to contain _I, _O or _OE at the end.
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
// and Mdo_OE. The bidirectional signal must be created on the top level. This
// is done due to the ASIC tools.
//
// Revision 1.1 2001/07/30 21:23:42 mohor
// Directory structure changed. Files checked and joind together.
//
// Revision 1.1 2001/06/27 21:26:19 mohor
// Initial release of the RxEthMAC module.
//
//
//
//
//
//
module eth_rxcounters (MRxClk, Reset, MRxDV, StateIdle, StateSFD, StateData, StateDrop, StatePreamble,
MRxDEqD, DlyCrcEn, DlyCrcCnt, Transmitting, MaxFL, r_IFG, HugEn, IFGCounterEq24,
ByteCntEq0, ByteCntEq1, ByteCntEq2,ByteCntEq3,ByteCntEq4,ByteCntEq5, ByteCntEq6,
ByteCntEq7, ByteCntGreat2, ByteCntSmall7, ByteCntMaxFrame, ByteCnt
);
parameter Tp = 1;
input MRxClk;
input Reset;
input MRxDV;
input StateSFD;
input [1:0] StateData;
input MRxDEqD;
input StateIdle;
input StateDrop;
input DlyCrcEn;
input StatePreamble;
input Transmitting;
input HugEn;
input [15:0] MaxFL;
input r_IFG;
output IFGCounterEq24; // IFG counter reaches 9600 ns (960 ns)
output [3:0] DlyCrcCnt; // Delayed CRC counter
output ByteCntEq0; // Byte counter = 0
output ByteCntEq1; // Byte counter = 1
output ByteCntEq2; // Byte counter = 2
output ByteCntEq3; // Byte counter = 3
output ByteCntEq4; // Byte counter = 4
output ByteCntEq5; // Byte counter = 5
output ByteCntEq6; // Byte counter = 6
output ByteCntEq7; // Byte counter = 7
output ByteCntGreat2; // Byte counter > 2
output ByteCntSmall7; // Byte counter < 7
output ByteCntMaxFrame; // Byte counter = MaxFL
output [15:0] ByteCnt; // Byte counter
wire ResetByteCounter;
wire IncrementByteCounter;
wire ResetIFGCounter;
wire IncrementIFGCounter;
wire ByteCntMax;
reg [15:0] ByteCnt;
reg [3:0] DlyCrcCnt;
reg [4:0] IFGCounter;
assign ResetByteCounter = MRxDV & (StateSFD & MRxDEqD | StateData[0] & ByteCntMaxFrame);
assign IncrementByteCounter = ~ResetByteCounter & MRxDV &
(StatePreamble | StateSFD | StateIdle & ~Transmitting |
StateData[1] & ~ByteCntMax & ~(DlyCrcEn & |DlyCrcCnt)
);
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
ByteCnt[15:0] <= #Tp 11'h0;
else
begin
if(ResetByteCounter)
ByteCnt[15:0] <= #Tp 11'h0;
else
if(IncrementByteCounter)
ByteCnt[15:0] <= #Tp ByteCnt[15:0] + 1'b1;
end
end
assign ByteCntEq0 = ByteCnt == 16'h0;
assign ByteCntEq1 = ByteCnt == 16'h1;
assign ByteCntEq2 = ByteCnt == 16'h2;
assign ByteCntEq3 = ByteCnt == 16'h3;
assign ByteCntEq4 = ByteCnt == 16'h4;
assign ByteCntEq5 = ByteCnt == 16'h5;
assign ByteCntEq6 = ByteCnt == 16'h6;
assign ByteCntEq7 = ByteCnt == 16'h7;
assign ByteCntGreat2 = ByteCnt > 16'h2;
assign ByteCntSmall7 = ByteCnt < 16'h7;
assign ByteCntMax = ByteCnt == 16'hffff;
assign ByteCntMaxFrame = ByteCnt == MaxFL[15:0] & ~HugEn;
assign ResetIFGCounter = StateSFD & MRxDV & MRxDEqD | StateDrop;
assign IncrementIFGCounter = ~ResetIFGCounter & (StateDrop | StateIdle | StatePreamble | StateSFD) & ~IFGCounterEq24;
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
IFGCounter[4:0] <= #Tp 5'h0;
else
begin
if(ResetIFGCounter)
IFGCounter[4:0] <= #Tp 5'h0;
else
if(IncrementIFGCounter)
IFGCounter[4:0] <= #Tp IFGCounter[4:0] + 1'b1;
end
end
assign IFGCounterEq24 = (IFGCounter[4:0] == 5'h18) | r_IFG; // 24*400 = 9600 ns or r_IFG is set to 1
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
DlyCrcCnt[3:0] <= #Tp 4'h0;
else
begin
if(DlyCrcCnt[3:0] == 4'h9)
DlyCrcCnt[3:0] <= #Tp 4'h0;
else
if(DlyCrcEn & StateSFD)
DlyCrcCnt[3:0] <= #Tp 4'h1;
else
if(DlyCrcEn & (|DlyCrcCnt[3:0]))
DlyCrcCnt[3:0] <= #Tp DlyCrcCnt[3:0] + 1'b1;
end
end
endmodule
//////////////////////////////////////////////////////////////////////
//// ////
//// eth_rxethmac.v ////
//// ////
//// This file is part of the Ethernet IP core project ////
//// http://www.opencores.org/projects/ethmac/ ////
//// ////
//// Author(s): ////
//// - Igor Mohor ([email protected]) ////
//// - Novan Hartadi ([email protected]) ////
//// - Mahmud Galela ([email protected]) ////
//// ////
//// All additional information is avaliable in the Readme.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: eth_rxethmac.v,v $
// Revision 1.12 2004/04/26 15:26:23 igorm
// - Bug connected to the TX_BD_NUM_Wr signal fixed (bug came in with the
// previous update of the core.
// - TxBDAddress is set to 0 after the TX is enabled in the MODER register.
// - RxBDAddress is set to r_TxBDNum<<1 after the RX is enabled in the MODER
// register. (thanks to Mathias and Torbjorn)
// - Multicast reception was fixed. Thanks to Ulrich Gries
//
// Revision 1.11 2004/03/17 09:32:15 igorm
// Multicast detection fixed. Only the LSB of the first byte is checked.
//
// Revision 1.10 2002/11/22 01:57:06 mohor
// Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort
// synchronized.
//
// Revision 1.9 2002/11/19 17:35:35 mohor
// AddressMiss status is connecting to the Rx BD. AddressMiss is identifying
// that a frame was received because of the promiscous mode.
//
// Revision 1.8 2002/02/16 07:15:27 mohor
// Testbench fixed, code simplified, unused signals removed.
//
// Revision 1.7 2002/02/15 13:44:28 mohor
// RxAbort is an output. No need to have is declared as wire.
//
// Revision 1.6 2002/02/15 11:17:48 mohor
// File format changed.
//
// Revision 1.5 2002/02/14 20:48:43 billditt
// Addition of new module eth_addrcheck.v
//
// Revision 1.4 2002/01/23 10:28:16 mohor
// Link in the header changed.
//
// Revision 1.3 2001/10/19 08:43:51 mohor
// eth_timescale.v changed to timescale.v This is done because of the
// simulation of the few cores in a one joined project.
//
// Revision 1.2 2001/09/11 14:17:00 mohor
// Few little NCSIM warnings fixed.
//
// Revision 1.1 2001/08/06 14:44:29 mohor
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
// Include files fixed to contain no path.
// File names and module names changed ta have a eth_ prologue in the name.
// File eth_timescale.v is used to define timescale
// All pin names on the top module are changed to contain _I, _O or _OE at the end.
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
// and Mdo_OE. The bidirectional signal must be created on the top level. This
// is done due to the ASIC tools.
//
// Revision 1.1 2001/07/30 21:23:42 mohor
// Directory structure changed. Files checked and joind together.
//
// Revision 1.1 2001/06/27 21:26:19 mohor
// Initial release of the RxEthMAC module.
//
//
//
//
//
module eth_rxethmac (MRxClk, MRxDV, MRxD, Reset, Transmitting, MaxFL, r_IFG, HugEn, DlyCrcEn,
RxData, RxValid, RxStartFrm, RxEndFrm, ByteCnt, ByteCntEq0, ByteCntGreat2,
ByteCntMaxFrame, CrcError, StateIdle, StatePreamble, StateSFD, StateData,
MAC, r_Pro, r_Bro,r_HASH0, r_HASH1, RxAbort, AddressMiss, PassAll, ControlFrmAddressOK
);
parameter Tp = 1;
input MRxClk;
input MRxDV;
input [3:0] MRxD;
input Transmitting;
input HugEn;
input DlyCrcEn;
input [15:0] MaxFL;
input r_IFG;
input Reset;
input [47:0] MAC; // Station Address
input r_Bro; // broadcast disable
input r_Pro; // promiscuous enable
input [31:0] r_HASH0; // lower 4 bytes Hash Table
input [31:0] r_HASH1; // upper 4 bytes Hash Table
input PassAll;
input ControlFrmAddressOK;
output [7:0] RxData;
output RxValid;
output RxStartFrm;
output RxEndFrm;
output [15:0] ByteCnt;
output ByteCntEq0;
output ByteCntGreat2;
output ByteCntMaxFrame;
output CrcError;
output StateIdle;
output StatePreamble;
output StateSFD;
output [1:0] StateData;
output RxAbort;
output AddressMiss;
reg [7:0] RxData;
reg RxValid;
reg RxStartFrm;
reg RxEndFrm;
reg Broadcast;
reg Multicast;
reg [5:0] CrcHash;
reg CrcHashGood;
reg DelayData;
reg [3:0] LatchedNibble;
reg [7:0] LatchedByte;
reg [7:0] RxData_d;
reg RxValid_d;
reg RxStartFrm_d;
reg RxEndFrm_d;
wire MRxDEqD;
wire MRxDEq5;
wire StateDrop;
wire ByteCntEq1;
wire ByteCntEq2;
wire ByteCntEq3;
wire ByteCntEq4;
wire ByteCntEq5;
wire ByteCntEq6;
wire ByteCntEq7;
wire ByteCntSmall7;
wire [31:0] Crc;
wire Enable_Crc;
wire Initialize_Crc;
wire [3:0] Data_Crc;
wire GenerateRxValid;
wire GenerateRxStartFrm;
wire GenerateRxEndFrm;
wire DribbleRxEndFrm;
wire [3:0] DlyCrcCnt;
assign MRxDEqD = MRxD == 4'hd;
assign MRxDEq5 = MRxD == 4'h5;
// Rx State Machine module
eth_rxstatem rxstatem1 (.MRxClk(MRxClk), .Reset(Reset), .MRxDV(MRxDV), .ByteCntEq0(ByteCntEq0),
.ByteCntGreat2(ByteCntGreat2), .Transmitting(Transmitting), .MRxDEq5(MRxDEq5),
.MRxDEqD(MRxDEqD), .IFGCounterEq24(IFGCounterEq24), .ByteCntMaxFrame(ByteCntMaxFrame),
.StateData(StateData), .StateIdle(StateIdle), .StatePreamble(StatePreamble),
.StateSFD(StateSFD), .StateDrop(StateDrop)
);
// Rx Counters module
eth_rxcounters rxcounters1 (.MRxClk(MRxClk), .Reset(Reset), .MRxDV(MRxDV), .StateIdle(StateIdle),
.StateSFD(StateSFD), .StateData(StateData), .StateDrop(StateDrop),
.StatePreamble(StatePreamble), .MRxDEqD(MRxDEqD), .DlyCrcEn(DlyCrcEn),
.DlyCrcCnt(DlyCrcCnt), .Transmitting(Transmitting), .MaxFL(MaxFL), .r_IFG(r_IFG),
.HugEn(HugEn), .IFGCounterEq24(IFGCounterEq24), .ByteCntEq0(ByteCntEq0),
.ByteCntEq1(ByteCntEq1), .ByteCntEq2(ByteCntEq2), .ByteCntEq3(ByteCntEq3),
.ByteCntEq4(ByteCntEq4), .ByteCntEq5(ByteCntEq5), .ByteCntEq6(ByteCntEq6),
.ByteCntEq7(ByteCntEq7), .ByteCntGreat2(ByteCntGreat2),
.ByteCntSmall7(ByteCntSmall7), .ByteCntMaxFrame(ByteCntMaxFrame),
.ByteCnt(ByteCnt)
);
// Rx Address Check
eth_rxaddrcheck rxaddrcheck1
(.MRxClk(MRxClk), .Reset( Reset), .RxData(RxData),
.Broadcast (Broadcast), .r_Bro (r_Bro), .r_Pro(r_Pro),
.ByteCntEq6(ByteCntEq6), .ByteCntEq7(ByteCntEq7), .ByteCntEq2(ByteCntEq2),
.ByteCntEq3(ByteCntEq3), .ByteCntEq4(ByteCntEq4), .ByteCntEq5(ByteCntEq5),
.HASH0(r_HASH0), .HASH1(r_HASH1),
.CrcHash(CrcHash), .CrcHashGood(CrcHashGood), .StateData(StateData),
.Multicast(Multicast), .MAC(MAC), .RxAbort(RxAbort),
.RxEndFrm(RxEndFrm), .AddressMiss(AddressMiss), .PassAll(PassAll),
.ControlFrmAddressOK(ControlFrmAddressOK)
);
assign Enable_Crc = MRxDV & (|StateData & ~ByteCntMaxFrame);
assign Initialize_Crc = StateSFD | DlyCrcEn & (|DlyCrcCnt[3:0]) & DlyCrcCnt[3:0] < 4'h9;
assign Data_Crc[0] = MRxD[3];
assign Data_Crc[1] = MRxD[2];
assign Data_Crc[2] = MRxD[1];
assign Data_Crc[3] = MRxD[0];
// Connecting module Crc
eth_crc crcrx (.Clk(MRxClk), .Reset(Reset), .Data(Data_Crc), .Enable(Enable_Crc), .Initialize(Initialize_Crc),
.Crc(Crc), .CrcError(CrcError)
);
// Latching CRC for use in the hash table
always @ (posedge MRxClk)
begin
CrcHashGood <= #Tp StateData[0] & ByteCntEq6;
end
always @ (posedge MRxClk)
begin
if(Reset | StateIdle)
CrcHash[5:0] <= #Tp 6'h0;
else
if(StateData[0] & ByteCntEq6)
CrcHash[5:0] <= #Tp Crc[31:26];
end
// Output byte stream
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
begin
RxData_d[7:0] <= #Tp 8'h0;
DelayData <= #Tp 1'b0;
LatchedNibble[3:0] <= #Tp 4'h0;
LatchedByte[7:0] <= #Tp 8'h0;
RxData[7:0] <= #Tp 8'h0;
end
else
begin
LatchedNibble[3:0] <= #Tp MRxD[3:0]; // Latched nibble
LatchedByte[7:0] <= #Tp {MRxD[3:0], LatchedNibble[3:0]}; // Latched byte
DelayData <= #Tp StateData[0];
if(GenerateRxValid)
RxData_d[7:0] <= #Tp LatchedByte[7:0] & {8{|StateData}}; // Data goes through only in data state
else
if(~DelayData)
RxData_d[7:0] <= #Tp 8'h0; // Delaying data to be valid for two cycles. Zero when not active.
RxData[7:0] <= #Tp RxData_d[7:0]; // Output data byte
end
end
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
Broadcast <= #Tp 1'b0;
else
begin
if(StateData[0] & ~(&LatchedByte[7:0]) & ByteCntSmall7)
Broadcast <= #Tp 1'b0;
else
if(StateData[0] & (&LatchedByte[7:0]) & ByteCntEq1)
Broadcast <= #Tp 1'b1;
else
if(RxAbort | RxEndFrm)
Broadcast <= #Tp 1'b0;
end
end
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
Multicast <= #Tp 1'b0;
else
begin
if(StateData[0] & ByteCntEq1 & LatchedByte[0])
Multicast <= #Tp 1'b1;
else if(RxAbort | RxEndFrm)
Multicast <= #Tp 1'b0;
end
end
assign GenerateRxValid = StateData[0] & (~ByteCntEq0 | DlyCrcCnt >= 4'h3);
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
begin
RxValid_d <= #Tp 1'b0;
RxValid <= #Tp 1'b0;
end
else
begin
RxValid_d <= #Tp GenerateRxValid;
RxValid <= #Tp RxValid_d;
end
end
assign GenerateRxStartFrm = StateData[0] & (ByteCntEq1 & ~DlyCrcEn | DlyCrcCnt == 4'h3 & DlyCrcEn);
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
begin
RxStartFrm_d <= #Tp 1'b0;
RxStartFrm <= #Tp 1'b0;
end
else
begin
RxStartFrm_d <= #Tp GenerateRxStartFrm;
RxStartFrm <= #Tp RxStartFrm_d;
end
end
assign GenerateRxEndFrm = StateData[0] & (~MRxDV & ByteCntGreat2 | ByteCntMaxFrame);
assign DribbleRxEndFrm = StateData[1] & ~MRxDV & ByteCntGreat2;
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
begin
RxEndFrm_d <= #Tp 1'b0;
RxEndFrm <= #Tp 1'b0;
end
else
begin
RxEndFrm_d <= #Tp GenerateRxEndFrm;
RxEndFrm <= #Tp RxEndFrm_d | DribbleRxEndFrm;
end
end
endmodule
//////////////////////////////////////////////////////////////////////
//// ////
//// eth_rxstatem.v ////
//// ////
//// This file is part of the Ethernet IP core project ////
//// http://www.opencores.org/projects/ethmac/ ////
//// ////
//// Author(s): ////
//// - Igor Mohor ([email protected]) ////
//// - Novan Hartadi ([email protected]) ////
//// - Mahmud Galela ([email protected]) ////
//// ////
//// All additional information is avaliable in the Readme.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: eth_rxstatem.v,v $
// Revision 1.6 2002/11/13 22:28:26 tadejm
// StartIdle state changed (not important the size of the packet).
// StartData1 activates only while ByteCnt is smaller than the MaxFrame.
//
// Revision 1.5 2002/01/23 10:28:16 mohor
// Link in the header changed.
//
// Revision 1.4 2001/10/19 08:43:51 mohor
// eth_timescale.v changed to timescale.v This is done because of the
// simulation of the few cores in a one joined project.
//
// Revision 1.3 2001/10/18 12:07:11 mohor
// Status signals changed, Adress decoding changed, interrupt controller
// added.
//
// Revision 1.2 2001/09/11 14:17:00 mohor
// Few little NCSIM warnings fixed.
//
// Revision 1.1 2001/08/06 14:44:29 mohor
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
// Include files fixed to contain no path.
// File names and module names changed ta have a eth_ prologue in the name.
// File eth_timescale.v is used to define timescale
// All pin names on the top module are changed to contain _I, _O or _OE at the end.
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
// and Mdo_OE. The bidirectional signal must be created on the top level. This
// is done due to the ASIC tools.
//
// Revision 1.1 2001/07/30 21:23:42 mohor
// Directory structure changed. Files checked and joind together.
//
// Revision 1.2 2001/07/03 12:55:41 mohor
// Minor changes because of the synthesys warnings.
//
//
// Revision 1.1 2001/06/27 21:26:19 mohor
// Initial release of the RxEthMAC module.
//
//
//
//
module eth_rxstatem (MRxClk, Reset, MRxDV, ByteCntEq0, ByteCntGreat2, Transmitting, MRxDEq5, MRxDEqD,
IFGCounterEq24, ByteCntMaxFrame, StateData, StateIdle, StatePreamble, StateSFD,
StateDrop
);
parameter Tp = 1;
input MRxClk;
input Reset;
input MRxDV;
input ByteCntEq0;
input ByteCntGreat2;
input MRxDEq5;
input Transmitting;
input MRxDEqD;
input IFGCounterEq24;
input ByteCntMaxFrame;
output [1:0] StateData;
output StateIdle;
output StateDrop;
output StatePreamble;
output StateSFD;
reg StateData0;
reg StateData1;
reg StateIdle;
reg StateDrop;
reg StatePreamble;
reg StateSFD;
wire StartIdle;
wire StartDrop;
wire StartData0;
wire StartData1;
wire StartPreamble;
wire StartSFD;
// Defining the next state
assign StartIdle = ~MRxDV & (StateDrop | StatePreamble | StateSFD | (|StateData));
assign StartPreamble = MRxDV & ~MRxDEq5 & (StateIdle & ~Transmitting);
assign StartSFD = MRxDV & MRxDEq5 & (StateIdle & ~Transmitting | StatePreamble);
assign StartData0 = MRxDV & (StateSFD & MRxDEqD & IFGCounterEq24 | StateData1);
assign StartData1 = MRxDV & StateData0 & (~ByteCntMaxFrame);
assign StartDrop = MRxDV & (StateIdle & Transmitting | StateSFD & ~IFGCounterEq24 & MRxDEqD
| StateData0 & ByteCntMaxFrame
);
// Rx State Machine
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
begin
StateIdle <= #Tp 1'b0;
StateDrop <= #Tp 1'b1;
StatePreamble <= #Tp 1'b0;
StateSFD <= #Tp 1'b0;
StateData0 <= #Tp 1'b0;
StateData1 <= #Tp 1'b0;
end
else
begin
if(StartPreamble | StartSFD | StartDrop)
StateIdle <= #Tp 1'b0;
else
if(StartIdle)
StateIdle <= #Tp 1'b1;
if(StartIdle)
StateDrop <= #Tp 1'b0;
else
if(StartDrop)
StateDrop <= #Tp 1'b1;
if(StartSFD | StartIdle | StartDrop)
StatePreamble <= #Tp 1'b0;
else
if(StartPreamble)
StatePreamble <= #Tp 1'b1;
if(StartPreamble | StartIdle | StartData0 | StartDrop)
StateSFD <= #Tp 1'b0;
else
if(StartSFD)
StateSFD <= #Tp 1'b1;
if(StartIdle | StartData1 | StartDrop)
StateData0 <= #Tp 1'b0;
else
if(StartData0)
StateData0 <= #Tp 1'b1;
if(StartIdle | StartData0 | StartDrop)
StateData1 <= #Tp 1'b0;
else
if(StartData1)
StateData1 <= #Tp 1'b1;
end
end
assign StateData[1:0] = {StateData1, StateData0};
endmodule
//////////////////////////////////////////////////////////////////////
//// ////
//// eth_shiftreg.v ////
//// ////
//// This file is part of the Ethernet IP core project ////
//// http://www.opencores.org/projects/ethmac/ ////
//// ////
//// Author(s): ////
//// - Igor Mohor ([email protected]) ////
//// ////
//// All additional information is avaliable in the Readme.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: eth_shiftreg.v,v $
// Revision 1.5 2002/08/14 18:16:59 mohor
// LinkFail signal was not latching appropriate bit.
//
// Revision 1.4 2002/03/02 21:06:01 mohor
// LinkFail signal was not latching appropriate bit.
//
// Revision 1.3 2002/01/23 10:28:16 mohor
// Link in the header changed.
//
// Revision 1.2 2001/10/19 08:43:51 mohor
// eth_timescale.v changed to timescale.v This is done because of the
// simulation of the few cores in a one joined project.
//
// Revision 1.1 2001/08/06 14:44:29 mohor
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
// Include files fixed to contain no path.
// File names and module names changed ta have a eth_ prologue in the name.
// File eth_timescale.v is used to define timescale
// All pin names on the top module are changed to contain _I, _O or _OE at the end.
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
// and Mdo_OE. The bidirectional signal must be created on the top level. This
// is done due to the ASIC tools.
//
// Revision 1.1 2001/07/30 21:23:42 mohor
// Directory structure changed. Files checked and joind together.
//
// Revision 1.3 2001/06/01 22:28:56 mohor
// This files (MIIM) are fully working. They were thoroughly tested. The testbench is not updated.
//
//
module eth_shiftreg(Clk, Reset, MdcEn_n, Mdi, Fiad, Rgad, CtrlData, WriteOp, ByteSelect,
LatchByte, ShiftedBit, Prsd, LinkFail);
parameter Tp=1;
input Clk; // Input clock (Host clock)
input Reset; // Reset signal
input MdcEn_n; // Enable signal is asserted for one Clk period before Mdc falls.
input Mdi; // MII input data
input [4:0] Fiad; // PHY address
input [4:0] Rgad; // Register address (within the selected PHY)
input [15:0]CtrlData; // Control data (data to be written to the PHY)
input WriteOp; // The current operation is a PHY register write operation
input [3:0] ByteSelect; // Byte select
input [1:0] LatchByte; // Byte select for latching (read operation)
output ShiftedBit; // Bit shifted out of the shift register
output[15:0]Prsd; // Read Status Data (data read from the PHY)
output LinkFail; // Link Integrity Signal
reg [7:0] ShiftReg; // Shift register for shifting the data in and out
reg [15:0]Prsd;
reg LinkFail;
// ShiftReg[7:0] :: Shift Register Data
always @ (posedge Clk or posedge Reset)
begin
if(Reset)
begin
ShiftReg[7:0] <= #Tp 8'h0;
Prsd[15:0] <= #Tp 16'h0;
LinkFail <= #Tp 1'b0;
end
else
begin
if(MdcEn_n)
begin
if(|ByteSelect)
begin
case (ByteSelect[3:0])
4'h1 : ShiftReg[7:0] <= #Tp {2'b01, ~WriteOp, WriteOp, Fiad[4:1]};
4'h2 : ShiftReg[7:0] <= #Tp {Fiad[0], Rgad[4:0], 2'b10};
4'h4 : ShiftReg[7:0] <= #Tp CtrlData[15:8];
4'h8 : ShiftReg[7:0] <= #Tp CtrlData[7:0];
default : ShiftReg[7:0] <= #Tp 8'h0;
endcase
end
else
begin
ShiftReg[7:0] <= #Tp {ShiftReg[6:0], Mdi};
if(LatchByte[0])
begin
Prsd[7:0] <= #Tp {ShiftReg[6:0], Mdi};
if(Rgad == 5'h01)
LinkFail <= #Tp ~ShiftReg[1]; // this is bit [2], because it is not shifted yet
end
else
begin
if(LatchByte[1])
Prsd[15:8] <= #Tp {ShiftReg[6:0], Mdi};
end
end
end
end
end
assign ShiftedBit = ShiftReg[7];
endmodule
//ETH_SPRAM_256x32 is removed with /* */ comments since it not
//used anymore
//////////////////////////////////////////////////////////////////////
//// ////
//// eth_spram_256x32.v ////
//// ////
//// This file is part of the Ethernet IP core project ////
//// http://www.opencores.org/projects/ethmac/ ////
//// ////
//// Author(s): ////
//// - Igor Mohor ([email protected]) ////
//// ////
//// All additional information is available in the Readme.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001, 2002 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: eth_spram_256x32.v,v $
// Revision 1.9 2003/12/05 12:43:06 tadejm
// Corrected address mismatch for xilinx RAMB4_S8 model which has wider address than RAMB4_S16.
//
// Revision 1.8 2003/12/04 14:59:13 simons
// Lapsus fixed (!we -> ~we).
//
// Revision 1.7 2003/11/12 18:24:59 tadejm
// WISHBONE slave changed and tested from only 32-bit accesss to byte access.
//
// Revision 1.6 2003/10/17 07:46:15 markom
// mbist signals updated according to newest convention
//
// Revision 1.5 2003/08/14 16:42:58 simons
// Artisan ram instance added.
//
// Revision 1.4 2002/10/18 17:04:20 tadejm
// Changed BIST scan signals.
//
// Revision 1.3 2002/10/10 16:29:30 mohor
// BIST added.
//
// Revision 1.2 2002/09/23 18:24:31 mohor
// ETH_VIRTUAL_SILICON_RAM supported (for ASIC implementation).
//
// Revision 1.1 2002/07/23 16:36:09 mohor
// ethernet spram added. So far a generic ram and xilinx RAMB4 are used.
//
//
//
/*module eth_spram_256x32(
// Generic synchronous single-port RAM interface
clk, rst, ce, we, oe, addr, di, do
`ifdef ETH_BIST
,
// debug chain signals
mbist_si_i, // bist scan serial in
mbist_so_o, // bist scan serial out
mbist_ctrl_i // bist chain shift control
`endif
);
//
// Generic synchronous single-port RAM interface
//
input clk; // Clock, rising edge
input rst; // Reset, active high
input ce; // Chip enable input, active high
input [3:0] we; // Write enable input, active high
input oe; // Output enable input, active high
input [7:0] addr; // address bus inputs
input [31:0] di; // input data bus
output [31:0] do; // output data bus
`ifdef ETH_BIST
input mbist_si_i; // bist scan serial in
output mbist_so_o; // bist scan serial out
input [`ETH_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i; // bist chain shift control
`endif
`ifdef ETH_XILINX_RAMB4*/
/*RAMB4_S16 ram0
(
.DO (do[15:0]),
.ADDR (addr),
.DI (di[15:0]),
.EN (ce),
.CLK (clk),
.WE (we),
.RST (rst)
);
RAMB4_S16 ram1
(
.DO (do[31:16]),
.ADDR (addr),
.DI (di[31:16]),
.EN (ce),
.CLK (clk),
.WE (we),
.RST (rst)
);*/
/*RAMB4_S8 ram0
(
.DO (do[7:0]),
.ADDR ({1'b0, addr}),
.DI (di[7:0]),
.EN (ce),
.CLK (clk),
.WE (we[0]),
.RST (rst)
);
RAMB4_S8 ram1
(
.DO (do[15:8]),
.ADDR ({1'b0, addr}),
.DI (di[15:8]),
.EN (ce),
.CLK (clk),
.WE (we[1]),
.RST (rst)
);
RAMB4_S8 ram2
(
.DO (do[23:16]),
.ADDR ({1'b0, addr}),
.DI (di[23:16]),
.EN (ce),
.CLK (clk),
.WE (we[2]),
.RST (rst)
);
RAMB4_S8 ram3
(
.DO (do[31:24]),
.ADDR ({1'b0, addr}),
.DI (di[31:24]),
.EN (ce),
.CLK (clk),
.WE (we[3]),
.RST (rst)
);
`else // !ETH_XILINX_RAMB4
`ifdef ETH_VIRTUAL_SILICON_RAM
`ifdef ETH_BIST
//vs_hdsp_256x32_bist ram0_bist
vs_hdsp_256x32_bw_bist ram0_bist
`else
//vs_hdsp_256x32 ram0
vs_hdsp_256x32_bw ram0
`endif
(
.CK (clk),
.CEN (!ce),
.WEN (~we),
.OEN (!oe),
.ADR (addr),
.DI (di),
.DOUT (do)
`ifdef ETH_BIST
,
// debug chain signals
.mbist_si_i (mbist_si_i),
.mbist_so_o (mbist_so_o),
.mbist_ctrl_i (mbist_ctrl_i)
`endif
);
`else // !ETH_VIRTUAL_SILICON_RAM
`ifdef ETH_ARTISAN_RAM
`ifdef ETH_BIST
//art_hssp_256x32_bist ram0_bist
art_hssp_256x32_bw_bist ram0_bist
`else
//art_hssp_256x32 ram0
art_hssp_256x32_bw ram0
`endif
(
.CLK (clk),
.CEN (!ce),
.WEN (~we),
.OEN (!oe),
.A (addr),
.D (di),
.Q (do)
`ifdef ETH_BIST
,
// debug chain signals
.mbist_si_i (mbist_si_i),
.mbist_so_o (mbist_so_o),
.mbist_ctrl_i (mbist_ctrl_i)
`endif
);
`else // !ETH_ARTISAN_RAM
//
// Generic single-port synchronous RAM model
//
//
// Generic RAM's registers and wires
//
reg [ 7: 0] mem0 [255:0]; // RAM content
reg [15: 8] mem1 [255:0]; // RAM content
reg [23:16] mem2 [255:0]; // RAM content
reg [31:24] mem3 [255:0]; // RAM content
wire [31:0] q; // RAM output
reg [7:0] raddr; // RAM read address
//
// Data output drivers
//
assign do = (oe & ce) ? q : {32{1'bz}};
//
// RAM read and write
//
// read operation
always@(posedge clk)
if (ce) // && !we)
raddr <= #1 addr; // read address needs to be registered to read clock
assign #1 q = rst ? {32{1'b0}} : {mem3[raddr], mem2[raddr], mem1[raddr], mem0[raddr]};
// write operation
always@(posedge clk)
begin
if (ce && we[3])
mem3[addr] <= #1 di[31:24];
if (ce && we[2])
mem2[addr] <= #1 di[23:16];
if (ce && we[1])
mem1[addr] <= #1 di[15: 8];
if (ce && we[0])
mem0[addr] <= #1 di[ 7: 0];
end
// Task prints range of memory
// *** Remember that tasks are non reentrant, don't call this task in parallel for multiple instantiations.
task print_ram;
input [7:0] start;
input [7:0] finish;
integer rnum;
begin
for (rnum=start;rnum<=finish;rnum=rnum+1)
$display("Addr %h = %0h %0h %0h %0h",rnum,mem3[rnum],mem2[rnum],mem1[rnum],mem0[rnum]);
end
endtask
`endif // !ETH_ARTISAN_RAM
`endif // !ETH_VIRTUAL_SILICON_RAM
`endif // !ETH_XILINX_RAMB4
endmodule*/
//////////////////////////////////////////////////////////////////////
//// ////
//// eth_transmitcontrol.v ////
//// ////
//// This file is part of the Ethernet IP core project ////
//// http://www.opencores.org/projects/ethmac/ ////
//// ////
//// Author(s): ////
//// - Igor Mohor ([email protected]) ////
//// ////
//// All additional information is avaliable in the Readme.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: eth_transmitcontrol.v,v $
// Revision 1.6 2002/11/21 00:16:14 mohor
// When TxUsedData and CtrlMux occur at the same time, byte counter needs
// to be incremented by 2. Signal IncrementByteCntBy2 added for that reason.
//
// Revision 1.5 2002/11/19 17:37:32 mohor
// When control frame (PAUSE) was sent, status was written in the
// eth_wishbone module and both TXB and TXC interrupts were set. Fixed.
// Only TXC interrupt is set.
//
// Revision 1.4 2002/01/23 10:28:16 mohor
// Link in the header changed.
//
// Revision 1.3 2001/10/19 08:43:51 mohor
// eth_timescale.v changed to timescale.v This is done because of the
// simulation of the few cores in a one joined project.
//
// Revision 1.2 2001/09/11 14:17:00 mohor
// Few little NCSIM warnings fixed.
//
// Revision 1.1 2001/08/06 14:44:29 mohor
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
// Include files fixed to contain no path.
// File names and module names changed ta have a eth_ prologue in the name.
// File eth_timescale.v is used to define timescale
// All pin names on the top module are changed to contain _I, _O or _OE at the end.
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
// and Mdo_OE. The bidirectional signal must be created on the top level. This
// is done due to the ASIC tools.
//
// Revision 1.1 2001/07/30 21:23:42 mohor
// Directory structure changed. Files checked and joind together.
//
// Revision 1.1 2001/07/03 12:51:54 mohor
// Initial release of the MAC Control module.
//
//
//
//
//
//
module eth_transmitcontrol (MTxClk, TxReset, TxUsedDataIn, TxUsedDataOut, TxDoneIn, TxAbortIn,
TxStartFrmIn, TPauseRq, TxUsedDataOutDetected, TxFlow, DlyCrcEn,
TxPauseTV, MAC, TxCtrlStartFrm, TxCtrlEndFrm, SendingCtrlFrm, CtrlMux,
ControlData, WillSendControlFrame, BlockTxDone
);
parameter Tp = 1;
input MTxClk;
input TxReset;
input TxUsedDataIn;
input TxUsedDataOut;
input TxDoneIn;
input TxAbortIn;
input TxStartFrmIn;
input TPauseRq;
input TxUsedDataOutDetected;
input TxFlow;
input DlyCrcEn;
input [15:0] TxPauseTV;
input [47:0] MAC;
output TxCtrlStartFrm;
output TxCtrlEndFrm;
output SendingCtrlFrm;
output CtrlMux;
output [7:0] ControlData;
output WillSendControlFrame;
output BlockTxDone;
reg SendingCtrlFrm;
reg CtrlMux;
reg WillSendControlFrame;
reg [3:0] DlyCrcCnt;
reg [5:0] ByteCnt;
reg ControlEnd_q;
reg [7:0] MuxedCtrlData;
reg TxCtrlStartFrm;
reg TxCtrlStartFrm_q;
reg TxCtrlEndFrm;
reg [7:0] ControlData;
reg TxUsedDataIn_q;
reg BlockTxDone;
wire IncrementDlyCrcCnt;
wire ResetByteCnt;
wire IncrementByteCnt;
wire ControlEnd;
wire IncrementByteCntBy2;
wire EnableCnt;
// A command for Sending the control frame is active (latched)
always @ (posedge MTxClk or posedge TxReset)
begin
if(TxReset)
WillSendControlFrame <= #Tp 1'b0;
else
if(TxCtrlEndFrm & CtrlMux)
WillSendControlFrame <= #Tp 1'b0;
else
if(TPauseRq & TxFlow)
WillSendControlFrame <= #Tp 1'b1;
end
// Generation of the transmit control packet start frame
always @ (posedge MTxClk or posedge TxReset)
begin
if(TxReset)
TxCtrlStartFrm <= #Tp 1'b0;
else
if(TxUsedDataIn_q & CtrlMux)
TxCtrlStartFrm <= #Tp 1'b0;
else
if(WillSendControlFrame & ~TxUsedDataOut & (TxDoneIn | TxAbortIn | TxStartFrmIn | (~TxUsedDataOutDetected)))
TxCtrlStartFrm <= #Tp 1'b1;
end
// Generation of the transmit control packet end frame
always @ (posedge MTxClk or posedge TxReset)
begin
if(TxReset)
TxCtrlEndFrm <= #Tp 1'b0;
else
if(ControlEnd | ControlEnd_q)
TxCtrlEndFrm <= #Tp 1'b1;
else
TxCtrlEndFrm <= #Tp 1'b0;
end
// Generation of the multiplexer signal (controls muxes for switching between
// normal and control packets)
always @ (posedge MTxClk or posedge TxReset)
begin
if(TxReset)
CtrlMux <= #Tp 1'b0;
else
if(WillSendControlFrame & ~TxUsedDataOut)
CtrlMux <= #Tp 1'b1;
else
if(TxDoneIn)
CtrlMux <= #Tp 1'b0;
end
// Generation of the Sending Control Frame signal (enables padding and CRC)
always @ (posedge MTxClk or posedge TxReset)
begin
if(TxReset)
SendingCtrlFrm <= #Tp 1'b0;
else
if(WillSendControlFrame & TxCtrlStartFrm)
SendingCtrlFrm <= #Tp 1'b1;
else
if(TxDoneIn)
SendingCtrlFrm <= #Tp 1'b0;
end
always @ (posedge MTxClk or posedge TxReset)
begin
if(TxReset)
TxUsedDataIn_q <= #Tp 1'b0;
else
TxUsedDataIn_q <= #Tp TxUsedDataIn;
end
// Generation of the signal that will block sending the Done signal to the eth_wishbone module
// While sending the control frame
always @ (posedge MTxClk or posedge TxReset)
begin
if(TxReset)
BlockTxDone <= #Tp 1'b0;
else
if(TxCtrlStartFrm)
BlockTxDone <= #Tp 1'b1;
else
if(TxStartFrmIn)
BlockTxDone <= #Tp 1'b0;
end
always @ (posedge MTxClk)
begin
ControlEnd_q <= #Tp ControlEnd;
TxCtrlStartFrm_q <= #Tp TxCtrlStartFrm;
end
assign IncrementDlyCrcCnt = CtrlMux & TxUsedDataIn & ~DlyCrcCnt[2];
// Delayed CRC counter
always @ (posedge MTxClk or posedge TxReset)
begin
if(TxReset)
DlyCrcCnt <= #Tp 4'h0;
else
if(ResetByteCnt)
DlyCrcCnt <= #Tp 4'h0;
else
if(IncrementDlyCrcCnt)
DlyCrcCnt <= #Tp DlyCrcCnt + 1'b1;
end
assign ResetByteCnt = TxReset | (~TxCtrlStartFrm & (TxDoneIn | TxAbortIn));
assign IncrementByteCnt = CtrlMux & (TxCtrlStartFrm & ~TxCtrlStartFrm_q & ~TxUsedDataIn | TxUsedDataIn & ~ControlEnd);
assign IncrementByteCntBy2 = CtrlMux & TxCtrlStartFrm & (~TxCtrlStartFrm_q) & TxUsedDataIn; // When TxUsedDataIn and CtrlMux are set at the same time
assign EnableCnt = (~DlyCrcEn | DlyCrcEn & (&DlyCrcCnt[1:0]));
// Byte counter
always @ (posedge MTxClk or posedge TxReset)
begin
if(TxReset)
ByteCnt <= #Tp 6'h0;
else
if(ResetByteCnt)
ByteCnt <= #Tp 6'h0;
else
if(IncrementByteCntBy2 & EnableCnt)
ByteCnt <= #Tp (ByteCnt[5:0] ) + 2'h2;
else
if(IncrementByteCnt & EnableCnt)
ByteCnt <= #Tp (ByteCnt[5:0] ) + 1'b1;
end
assign ControlEnd = ByteCnt[5:0] == 6'h22;
// Control data generation (goes to the TxEthMAC module)
always @ (ByteCnt or DlyCrcEn or MAC or TxPauseTV or DlyCrcCnt)
begin
case(ByteCnt)
6'h0: if(~DlyCrcEn | DlyCrcEn & (&DlyCrcCnt[1:0]))
MuxedCtrlData[7:0] = 8'h01; // Reserved Multicast Address
else
MuxedCtrlData[7:0] = 8'h0;
6'h2: MuxedCtrlData[7:0] = 8'h80;
6'h4: MuxedCtrlData[7:0] = 8'hC2;
6'h6: MuxedCtrlData[7:0] = 8'h00;
6'h8: MuxedCtrlData[7:0] = 8'h00;
6'hA: MuxedCtrlData[7:0] = 8'h01;
6'hC: MuxedCtrlData[7:0] = MAC[47:40];
6'hE: MuxedCtrlData[7:0] = MAC[39:32];
6'h10: MuxedCtrlData[7:0] = MAC[31:24];
6'h12: MuxedCtrlData[7:0] = MAC[23:16];
6'h14: MuxedCtrlData[7:0] = MAC[15:8];
6'h16: MuxedCtrlData[7:0] = MAC[7:0];
6'h18: MuxedCtrlData[7:0] = 8'h88; // Type/Length
6'h1A: MuxedCtrlData[7:0] = 8'h08;
6'h1C: MuxedCtrlData[7:0] = 8'h00; // Opcode
6'h1E: MuxedCtrlData[7:0] = 8'h01;
6'h20: MuxedCtrlData[7:0] = TxPauseTV[15:8]; // Pause timer value
6'h22: MuxedCtrlData[7:0] = TxPauseTV[7:0];
default: MuxedCtrlData[7:0] = 8'h0;
endcase
end
// Latched Control data
always @ (posedge MTxClk or posedge TxReset)
begin
if(TxReset)
ControlData[7:0] <= #Tp 8'h0;
else
if(~ByteCnt[0])
ControlData[7:0] <= #Tp MuxedCtrlData[7:0];
end
endmodule
//////////////////////////////////////////////////////////////////////
//// ////
//// eth_txcounters.v ////
//// ////
//// This file is part of the Ethernet IP core project ////
//// http://www.opencores.org/projects/ethmac/ ////
//// ////
//// Author(s): ////
//// - Igor Mohor ([email protected]) ////
//// - Novan Hartadi ([email protected]) ////
//// - Mahmud Galela ([email protected]) ////
//// ////
//// All additional information is avaliable in the Readme.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: eth_txcounters.v,v $
// Revision 1.5 2002/04/22 14:54:14 mohor
// FCS should not be included in NibbleMinFl.
//
// Revision 1.4 2002/01/23 10:28:16 mohor
// Link in the header changed.
//
// Revision 1.3 2001/10/19 08:43:51 mohor
// eth_timescale.v changed to timescale.v This is done because of the
// simulation of the few cores in a one joined project.
//
// Revision 1.2 2001/09/11 14:17:00 mohor
// Few little NCSIM warnings fixed.
//
// Revision 1.1 2001/08/06 14:44:29 mohor
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
// Include files fixed to contain no path.
// File names and module names changed ta have a eth_ prologue in the name.
// File eth_timescale.v is used to define timescale
// All pin names on the top module are changed to contain _I, _O or _OE at the end.
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
// and Mdo_OE. The bidirectional signal must be created on the top level. This
// is done due to the ASIC tools.
//
// Revision 1.1 2001/07/30 21:23:42 mohor
// Directory structure changed. Files checked and joind together.
//
// Revision 1.4 2001/06/27 21:27:45 mohor
// Few typos fixed.
//
// Revision 1.2 2001/06/19 10:38:07 mohor
// Minor changes in header.
//
// Revision 1.1 2001/06/19 10:27:57 mohor
// TxEthMAC initial release.
//
//
//
module eth_txcounters (StatePreamble, StateIPG, StateData, StatePAD, StateFCS, StateJam,
StateBackOff, StateDefer, StateIdle, StartDefer, StartIPG, StartFCS,
StartJam, StartBackoff, TxStartFrm, MTxClk, Reset, MinFL, MaxFL, HugEn,
ExDfrEn, PacketFinished_q, DlyCrcEn, StateSFD, ByteCnt, NibCnt,
ExcessiveDefer, NibCntEq7, NibCntEq15, MaxFrame, NibbleMinFl, DlyCrcCnt
);
parameter Tp = 1;
input MTxClk; // Tx clock
input Reset; // Reset
input StatePreamble; // Preamble state
input StateIPG; // IPG state
input [1:0] StateData; // Data state
input StatePAD; // PAD state
input StateFCS; // FCS state
input StateJam; // Jam state
input StateBackOff; // Backoff state
input StateDefer; // Defer state
input StateIdle; // Idle state
input StateSFD; // SFD state
input StartDefer; // Defer state will be activated in next clock
input StartIPG; // IPG state will be activated in next clock
input StartFCS; // FCS state will be activated in next clock
input StartJam; // Jam state will be activated in next clock
input StartBackoff; // Backoff state will be activated in next clock
input TxStartFrm; // Tx start frame
input [15:0] MinFL; // Minimum frame length (in bytes)
input [15:0] MaxFL; // Miximum frame length (in bytes)
input HugEn; // Pakets bigger then MaxFL enabled
input ExDfrEn; // Excessive deferral enabled
input PacketFinished_q;
input DlyCrcEn; // Delayed CRC enabled
output [15:0] ByteCnt; // Byte counter
output [15:0] NibCnt; // Nibble counter
output ExcessiveDefer; // Excessive Deferral occuring
output NibCntEq7; // Nibble counter is equal to 7
output NibCntEq15; // Nibble counter is equal to 15
output MaxFrame; // Maximum frame occured
output NibbleMinFl; // Nibble counter is greater than the minimum frame length
output [2:0] DlyCrcCnt; // Delayed CRC Count
wire ExcessiveDeferCnt;
wire ResetNibCnt;
wire IncrementNibCnt;
wire ResetByteCnt;
wire IncrementByteCnt;
wire ByteCntMax;
reg [15:0] NibCnt;
reg [15:0] ByteCnt;
reg [2:0] DlyCrcCnt;
assign IncrementNibCnt = StateIPG | StatePreamble | (|StateData) & ~|DlyCrcCnt[2:0] | StatePAD
| StateFCS | StateJam | StateBackOff | StateDefer & ~ExcessiveDefer & TxStartFrm;
assign ResetNibCnt = StateDefer & ExcessiveDefer & ~TxStartFrm | StatePreamble & NibCntEq15
| StateJam & NibCntEq7 | StateIdle | StartDefer | StartIPG | StartFCS | StartJam;
// Nibble Counter
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
NibCnt <= #Tp 16'h0;
else
begin
if(ResetNibCnt)
NibCnt <= #Tp 16'h0;
else
if(IncrementNibCnt)
NibCnt <= #Tp NibCnt + 1'b1;
end
end
assign NibCntEq7 = &NibCnt[2:0];
assign NibCntEq15 = &NibCnt[3:0];
assign NibbleMinFl = NibCnt >= (((MinFL-3'h4)<<1) -1); // FCS should not be included in NibbleMinFl
assign ExcessiveDeferCnt = NibCnt[13:0] == 16'h17b7;
assign ExcessiveDefer = NibCnt[13:0] == 16'h17b7 & ~ExDfrEn; // 6071 nibbles
assign IncrementByteCnt = StateData[1] & ~ByteCntMax & ~|DlyCrcCnt[2:0]
| StateBackOff & (&NibCnt[6:0])
| (StatePAD | StateFCS) & NibCnt[0] & ~ByteCntMax;
assign ResetByteCnt = StartBackoff | StateIdle & TxStartFrm | PacketFinished_q;
// Transmit Byte Counter
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
ByteCnt[15:0] <= #Tp 16'h0;
else
begin
if(ResetByteCnt)
ByteCnt[15:0] <= #Tp 16'h0;
else
if(IncrementByteCnt)
ByteCnt[15:0] <= #Tp ByteCnt[15:0] + 1'b1;
end
end
assign MaxFrame = ByteCnt[15:0] == MaxFL[15:0] & ~HugEn;
assign ByteCntMax = &ByteCnt[15:0];
// Delayed CRC counter
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
DlyCrcCnt <= #Tp 3'h0;
else
begin
if(StateData[1] & DlyCrcCnt == 3'h4 | StartJam | PacketFinished_q)
DlyCrcCnt <= #Tp 3'h0;
else
if(DlyCrcEn & (StateSFD | StateData[1] & (|DlyCrcCnt[2:0])))
DlyCrcCnt <= #Tp DlyCrcCnt + 1'b1;
end
end
endmodule
//////////////////////////////////////////////////////////////////////
//// ////
//// eth_txethmac.v ////
/// ////
//// This file is part of the Ethernet IP core project ////
//// http://www.opencores.org/projects/ethmac/ ////
//// ////
//// Author(s): ////
//// - Igor Mohor ([email protected]) ////
//// - Novan Hartadi ([email protected]) ////
//// - Mahmud Galela ([email protected]) ////
//// ////
//// All additional information is avaliable in the Readme.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: eth_txethmac.v,v $
// Revision 1.8 2003/01/30 13:33:24 mohor
// When padding was enabled and crc disabled, frame was not ended correctly.
//
// Revision 1.7 2002/02/26 16:24:01 mohor
// RetryCntLatched was unused and removed from design
//
// Revision 1.6 2002/02/22 12:56:35 mohor
// Retry is not activated when a Tx Underrun occured
//
// Revision 1.5 2002/02/11 09:18:22 mohor
// Tx status is written back to the BD.
//
// Revision 1.4 2002/01/23 10:28:16 mohor
// Link in the header changed.
//
// Revision 1.3 2001/10/19 08:43:51 mohor
// eth_timescale.v changed to timescale.v This is done because of the
// simulation of the few cores in a one joined project.
//
// Revision 1.2 2001/09/11 14:17:00 mohor
// Few little NCSIM warnings fixed.
//
// Revision 1.1 2001/08/06 14:44:29 mohor
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
// Include files fixed to contain no path.
// File names and module names changed ta have a eth_ prologue in the name.
// File eth_timescale.v is used to define timescale
// All pin names on the top module are changed to contain _I, _O or _OE at the end.
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
// and Mdo_OE. The bidirectional signal must be created on the top level. This
// is done due to the ASIC tools.
//
// Revision 1.1 2001/07/30 21:23:42 mohor
// Directory structure changed. Files checked and joind together.
//
// Revision 1.3 2001/06/19 18:16:40 mohor
// TxClk changed to MTxClk (as discribed in the documentation).
// Crc changed so only one file can be used instead of two.
//
// Revision 1.2 2001/06/19 10:38:08 mohor
// Minor changes in header.
//
// Revision 1.1 2001/06/19 10:27:58 mohor
// TxEthMAC initial release.
//
//
//
module eth_txethmac (MTxClk, Reset, TxStartFrm, TxEndFrm, TxUnderRun, TxData, CarrierSense,
Collision, Pad, CrcEn, FullD, HugEn, DlyCrcEn, MinFL, MaxFL, IPGT,
IPGR1, IPGR2, CollValid, MaxRet, NoBckof, ExDfrEn,
MTxD, MTxEn, MTxErr, TxDone, TxRetry, TxAbort, TxUsedData, WillTransmit,
ResetCollision, RetryCnt, StartTxDone, StartTxAbort, MaxCollisionOccured,
LateCollision, DeferIndication, StatePreamble, StateData
);
parameter Tp = 1;
input MTxClk; // Transmit clock (from PHY)
input Reset; // Reset
input TxStartFrm; // Transmit packet start frame
input TxEndFrm; // Transmit packet end frame
input TxUnderRun; // Transmit packet under-run
input [7:0] TxData; // Transmit packet data byte
input CarrierSense; // Carrier sense (synchronized)
input Collision; // Collision (synchronized)
input Pad; // Pad enable (from register)
input CrcEn; // Crc enable (from register)
input FullD; // Full duplex (from register)
input HugEn; // Huge packets enable (from register)
input DlyCrcEn; // Delayed Crc enabled (from register)
input [15:0] MinFL; // Minimum frame length (from register)
input [15:0] MaxFL; // Maximum frame length (from register)
input [6:0] IPGT; // Back to back transmit inter packet gap parameter (from register)
input [6:0] IPGR1; // Non back to back transmit inter packet gap parameter IPGR1 (from register)
input [6:0] IPGR2; // Non back to back transmit inter packet gap parameter IPGR2 (from register)
input [5:0] CollValid; // Valid collision window (from register)
input [3:0] MaxRet; // Maximum retry number (from register)
input NoBckof; // No backoff (from register)
input ExDfrEn; // Excessive defferal enable (from register)
output [3:0] MTxD; // Transmit nibble (to PHY)
output MTxEn; // Transmit enable (to PHY)
output MTxErr; // Transmit error (to PHY)
output TxDone; // Transmit packet done (to RISC)
output TxRetry; // Transmit packet retry (to RISC)
output TxAbort; // Transmit packet abort (to RISC)
output TxUsedData; // Transmit packet used data (to RISC)
output WillTransmit; // Will transmit (to RxEthMAC)
output ResetCollision; // Reset Collision (for synchronizing collision)
output [3:0] RetryCnt; // Latched Retry Counter for tx status purposes
output StartTxDone;
output StartTxAbort;
output MaxCollisionOccured;
output LateCollision;
output DeferIndication;
output StatePreamble;
output [1:0] StateData;
reg [3:0] MTxD;
reg MTxEn;
reg MTxErr;
reg TxDone;
reg TxRetry;
reg TxAbort;
reg TxUsedData;
reg WillTransmit;
reg ColWindow;
reg StopExcessiveDeferOccured;
reg [3:0] RetryCnt;
reg [3:0] MTxD_d;
reg StatusLatch;
reg PacketFinished_q;
reg PacketFinished;
wire ExcessiveDeferOccured;
wire StartIPG;
wire StartPreamble;
wire [1:0] StartData;
wire StartFCS;
wire StartJam;
wire StartDefer;
wire StartBackoff;
wire StateDefer;
wire StateIPG;
wire StateIdle;
wire StatePAD;
wire StateFCS;
wire StateJam;
wire StateBackOff;
wire StateSFD;
wire StartTxRetry;
wire UnderRun;
wire TooBig;
wire [31:0] Crc;
wire CrcError;
wire [2:0] DlyCrcCnt;
wire [15:0] NibCnt;
wire NibCntEq7;
wire NibCntEq15;
wire NibbleMinFl;
wire ExcessiveDefer;
wire [15:0] ByteCnt;
wire MaxFrame;
wire RetryMax;
wire RandomEq0;
wire RandomEqByteCnt;
wire PacketFinished_d;
assign ResetCollision = ~(StatePreamble | (|StateData) | StatePAD | StateFCS);
assign ExcessiveDeferOccured = TxStartFrm & StateDefer & ExcessiveDefer & ~StopExcessiveDeferOccured;
assign StartTxDone = ~Collision & (StateFCS & NibCntEq7 | StateData[1] & TxEndFrm & (~Pad | Pad & NibbleMinFl) & ~CrcEn);
assign UnderRun = StateData[0] & TxUnderRun & ~Collision;
assign TooBig = ~Collision & MaxFrame & (StateData[0] & ~TxUnderRun | StateFCS);
// assign StartTxRetry = StartJam & (ColWindow & ~RetryMax);
assign StartTxRetry = StartJam & (ColWindow & ~RetryMax) & ~UnderRun;
assign LateCollision = StartJam & ~ColWindow & ~UnderRun;
assign MaxCollisionOccured = StartJam & ColWindow & RetryMax;
assign StateSFD = StatePreamble & NibCntEq15;
assign StartTxAbort = TooBig | UnderRun | ExcessiveDeferOccured | LateCollision | MaxCollisionOccured;
// StopExcessiveDeferOccured
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
StopExcessiveDeferOccured <= #Tp 1'b0;
else
begin
if(~TxStartFrm)
StopExcessiveDeferOccured <= #Tp 1'b0;
else
if(ExcessiveDeferOccured)
StopExcessiveDeferOccured <= #Tp 1'b1;
end
end
// Collision Window
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
ColWindow <= #Tp 1'b1;
else
begin
if(~Collision & ByteCnt[5:0] == CollValid[5:0] & (StateData[1] | StatePAD & NibCnt[0] | StateFCS & NibCnt[0]))
ColWindow <= #Tp 1'b0;
else
if(StateIdle | StateIPG)
ColWindow <= #Tp 1'b1;
end
end
// Start Window
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
StatusLatch <= #Tp 1'b0;
else
begin
if(~TxStartFrm)
StatusLatch <= #Tp 1'b0;
else
if(ExcessiveDeferOccured | StateIdle)
StatusLatch <= #Tp 1'b1;
end
end
// Transmit packet used data
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
TxUsedData <= #Tp 1'b0;
else
TxUsedData <= #Tp |StartData;
end
// Transmit packet done
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
TxDone <= #Tp 1'b0;
else
begin
if(TxStartFrm & ~StatusLatch)
TxDone <= #Tp 1'b0;
else
if(StartTxDone)
TxDone <= #Tp 1'b1;
end
end
// Transmit packet retry
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
TxRetry <= #Tp 1'b0;
else
begin
if(TxStartFrm & ~StatusLatch)
TxRetry <= #Tp 1'b0;
else
if(StartTxRetry)
TxRetry <= #Tp 1'b1;
end
end
// Transmit packet abort
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
TxAbort <= #Tp 1'b0;
else
begin
if(TxStartFrm & ~StatusLatch & ~ExcessiveDeferOccured)
TxAbort <= #Tp 1'b0;
else
if(StartTxAbort)
TxAbort <= #Tp 1'b1;
end
end
// Retry counter
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
RetryCnt[3:0] <= #Tp 4'h0;
else
begin
if(ExcessiveDeferOccured | UnderRun | TooBig | StartTxDone | TxUnderRun
| StateJam & NibCntEq7 & (~ColWindow | RetryMax))
RetryCnt[3:0] <= #Tp 4'h0;
else
if(StateJam & NibCntEq7 & ColWindow & (RandomEq0 | NoBckof) | StateBackOff & RandomEqByteCnt)
RetryCnt[3:0] <= #Tp RetryCnt[3:0] + 1'b1;
end
end
assign RetryMax = RetryCnt[3:0] == MaxRet[3:0];
// Transmit nibble
always @ (StatePreamble or StateData or StateData or StateFCS or StateJam or StateSFD or TxData or
Crc or NibCnt or NibCntEq15)
begin
if(StateData[0])
MTxD_d[3:0] = TxData[3:0]; // Lower nibble
else
if(StateData[1])
MTxD_d[3:0] = TxData[7:4]; // Higher nibble
else
if(StateFCS)
MTxD_d[3:0] = {~Crc[28], ~Crc[29], ~Crc[30], ~Crc[31]}; // Crc
else
if(StateJam)
MTxD_d[3:0] = 4'h9; // Jam pattern
else
if(StatePreamble)
if(NibCntEq15)
MTxD_d[3:0] = 4'hd; // SFD
else
MTxD_d[3:0] = 4'h5; // Preamble
else
MTxD_d[3:0] = 4'h0;
end
// Transmit Enable
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
MTxEn <= #Tp 1'b0;
else
MTxEn <= #Tp StatePreamble | (|StateData) | StatePAD | StateFCS | StateJam;
end
// Transmit nibble
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
MTxD[3:0] <= #Tp 4'h0;
else
MTxD[3:0] <= #Tp MTxD_d[3:0];
end
// Transmit error
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
MTxErr <= #Tp 1'b0;
else
MTxErr <= #Tp TooBig | UnderRun;
end
// WillTransmit
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
WillTransmit <= #Tp 1'b0;
else
WillTransmit <= #Tp StartPreamble | StatePreamble | (|StateData) | StatePAD | StateFCS | StateJam;
end
assign PacketFinished_d = StartTxDone | TooBig | UnderRun | LateCollision | MaxCollisionOccured | ExcessiveDeferOccured;
// Packet finished
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
begin
PacketFinished <= #Tp 1'b0;
PacketFinished_q <= #Tp 1'b0;
end
else
begin
PacketFinished <= #Tp PacketFinished_d;
PacketFinished_q <= #Tp PacketFinished;
end
end
// Connecting module Counters
eth_txcounters txcounters1 (.StatePreamble(StatePreamble), .StateIPG(StateIPG), .StateData(StateData),
.StatePAD(StatePAD), .StateFCS(StateFCS), .StateJam(StateJam), .StateBackOff(StateBackOff),
.StateDefer(StateDefer), .StateIdle(StateIdle), .StartDefer(StartDefer), .StartIPG(StartIPG),
.StartFCS(StartFCS), .StartJam(StartJam), .TxStartFrm(TxStartFrm), .MTxClk(MTxClk),
.Reset(Reset), .MinFL(MinFL), .MaxFL(MaxFL), .HugEn(HugEn), .ExDfrEn(ExDfrEn),
.PacketFinished_q(PacketFinished_q), .DlyCrcEn(DlyCrcEn), .StartBackoff(StartBackoff),
.StateSFD(StateSFD), .ByteCnt(ByteCnt), .NibCnt(NibCnt), .ExcessiveDefer(ExcessiveDefer),
.NibCntEq7(NibCntEq7), .NibCntEq15(NibCntEq15), .MaxFrame(MaxFrame), .NibbleMinFl(NibbleMinFl),
.DlyCrcCnt(DlyCrcCnt)
);
// Connecting module StateM
eth_txstatem txstatem1 (.MTxClk(MTxClk), .Reset(Reset), .ExcessiveDefer(ExcessiveDefer), .CarrierSense(CarrierSense),
.NibCnt(NibCnt[6:0]), .IPGT(IPGT), .IPGR1(IPGR1), .IPGR2(IPGR2), .FullD(FullD),
.TxStartFrm(TxStartFrm), .TxEndFrm(TxEndFrm), .TxUnderRun(TxUnderRun), .Collision(Collision),
.UnderRun(UnderRun), .StartTxDone(StartTxDone), .TooBig(TooBig), .NibCntEq7(NibCntEq7),
.NibCntEq15(NibCntEq15), .MaxFrame(MaxFrame), .Pad(Pad), .CrcEn(CrcEn),
.NibbleMinFl(NibbleMinFl), .RandomEq0(RandomEq0), .ColWindow(ColWindow), .RetryMax(RetryMax),
.NoBckof(NoBckof), .RandomEqByteCnt(RandomEqByteCnt), .StateIdle(StateIdle),
.StateIPG(StateIPG), .StatePreamble(StatePreamble), .StateData(StateData), .StatePAD(StatePAD),
.StateFCS(StateFCS), .StateJam(StateJam), .StateJam_q(StateJam_q), .StateBackOff(StateBackOff),
.StateDefer(StateDefer), .StartFCS(StartFCS), .StartJam(StartJam), .StartBackoff(StartBackoff),
.StartDefer(StartDefer), .DeferIndication(DeferIndication), .StartPreamble(StartPreamble), .StartData(StartData), .StartIPG(StartIPG)
);
wire Enable_Crc;
wire [3:0] Data_Crc;
wire Initialize_Crc;
assign Enable_Crc = ~StateFCS;
assign Data_Crc[0] = StateData[0]? TxData[3] : StateData[1]? TxData[7] : 1'b0;
assign Data_Crc[1] = StateData[0]? TxData[2] : StateData[1]? TxData[6] : 1'b0;
assign Data_Crc[2] = StateData[0]? TxData[1] : StateData[1]? TxData[5] : 1'b0;
assign Data_Crc[3] = StateData[0]? TxData[0] : StateData[1]? TxData[4] : 1'b0;
assign Initialize_Crc = StateIdle | StatePreamble | (|DlyCrcCnt);
// Connecting module Crc
eth_crc txcrc (.Clk(MTxClk), .Reset(Reset), .Data(Data_Crc), .Enable(Enable_Crc), .Initialize(Initialize_Crc),
.Crc(Crc), .CrcError(CrcError)
);
// Connecting module Random
eth_random random1 (.MTxClk(MTxClk), .Reset(Reset), .StateJam(StateJam), .StateJam_q(StateJam_q), .RetryCnt(RetryCnt),
.NibCnt(NibCnt), .ByteCnt(ByteCnt[9:0]), .RandomEq0(RandomEq0), .RandomEqByteCnt(RandomEqByteCnt));
endmodule
//////////////////////////////////////////////////////////////////////
//// ////
//// eth_txstatem.v ////
//// ////
//// This file is part of the Ethernet IP core project ////
//// http://www.opencores.org/projects/ethmac/ ////
//// ////
//// Author(s): ////
//// - Igor Mohor ([email protected]) ////
//// - Novan Hartadi ([email protected]) ////
//// - Mahmud Galela ([email protected]) ////
//// ////
//// All additional information is avaliable in the Readme.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: eth_txstatem.v,v $
// Revision 1.6 2003/01/30 13:29:08 tadejm
// Defer indication changed.
//
// Revision 1.5 2002/10/30 12:54:50 mohor
// State machine goes from idle to the defer state when CarrierSense is 1. FCS (CRC appending) fixed to check the CrcEn bit also when padding is necessery.
//
// Revision 1.4 2002/01/23 10:28:16 mohor
// Link in the header changed.
//
// Revision 1.3 2001/10/19 08:43:51 mohor
// eth_timescale.v changed to timescale.v This is done because of the
// simulation of the few cores in a one joined project.
//
// Revision 1.2 2001/09/11 14:17:00 mohor
// Few little NCSIM warnings fixed.
//
// Revision 1.1 2001/08/06 14:44:29 mohor
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
// Include files fixed to contain no path.
// File names and module names changed ta have a eth_ prologue in the name.
// File eth_timescale.v is used to define timescale
// All pin names on the top module are changed to contain _I, _O or _OE at the end.
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
// and Mdo_OE. The bidirectional signal must be created on the top level. This
// is done due to the ASIC tools.
//
// Revision 1.1 2001/07/30 21:23:42 mohor
// Directory structure changed. Files checked and joind together.
//
// Revision 1.3 2001/06/19 18:16:40 mohor
// TxClk changed to MTxClk (as discribed in the documentation).
// Crc changed so only one file can be used instead of two.
//
// Revision 1.2 2001/06/19 10:38:07 mohor
// Minor changes in header.
//
// Revision 1.1 2001/06/19 10:27:57 mohor
// TxEthMAC initial release.
//
//
//
//
module eth_txstatem (MTxClk, Reset, ExcessiveDefer, CarrierSense, NibCnt, IPGT, IPGR1,
IPGR2, FullD, TxStartFrm, TxEndFrm, TxUnderRun, Collision, UnderRun,
StartTxDone, TooBig, NibCntEq7, NibCntEq15, MaxFrame, Pad, CrcEn,
NibbleMinFl, RandomEq0, ColWindow, RetryMax, NoBckof, RandomEqByteCnt,
StateIdle, StateIPG, StatePreamble, StateData, StatePAD, StateFCS,
StateJam, StateJam_q, StateBackOff, StateDefer, StartFCS, StartJam,
StartBackoff, StartDefer, DeferIndication, StartPreamble, StartData, StartIPG
);
parameter Tp = 1;
input MTxClk;
input Reset;
input ExcessiveDefer;
input CarrierSense;
input [6:0] NibCnt;
input [6:0] IPGT;
input [6:0] IPGR1;
input [6:0] IPGR2;
input FullD;
input TxStartFrm;
input TxEndFrm;
input TxUnderRun;
input Collision;
input UnderRun;
input StartTxDone;
input TooBig;
input NibCntEq7;
input NibCntEq15;
input MaxFrame;
input Pad;
input CrcEn;
input NibbleMinFl;
input RandomEq0;
input ColWindow;
input RetryMax;
input NoBckof;
input RandomEqByteCnt;
output StateIdle; // Idle state
output StateIPG; // IPG state
output StatePreamble; // Preamble state
output [1:0] StateData; // Data state
output StatePAD; // PAD state
output StateFCS; // FCS state
output StateJam; // Jam state
output StateJam_q; // Delayed Jam state
output StateBackOff; // Backoff state
output StateDefer; // Defer state
output StartFCS; // FCS state will be activated in next clock
output StartJam; // Jam state will be activated in next clock
output StartBackoff; // Backoff state will be activated in next clock
output StartDefer; // Defer state will be activated in next clock
output DeferIndication;
output StartPreamble; // Preamble state will be activated in next clock
output [1:0] StartData; // Data state will be activated in next clock
output StartIPG; // IPG state will be activated in next clock
wire StartIdle; // Idle state will be activated in next clock
wire StartPAD; // PAD state will be activated in next clock
reg StateIdle;
reg StateIPG;
reg StatePreamble;
reg [1:0] StateData;
reg StatePAD;
reg StateFCS;
reg StateJam;
reg StateJam_q;
reg StateBackOff;
reg StateDefer;
reg Rule1;
// Defining the next state
assign StartIPG = StateDefer & ~ExcessiveDefer & ~CarrierSense;
assign StartIdle = StateIPG & (Rule1 & NibCnt[6:0] >= IPGT | ~Rule1 & NibCnt[6:0] >= IPGR2);
assign StartPreamble = StateIdle & TxStartFrm & ~CarrierSense;
assign StartData[0] = ~Collision & (StatePreamble & NibCntEq15 | StateData[1] & ~TxEndFrm);
assign StartData[1] = ~Collision & StateData[0] & ~TxUnderRun & ~MaxFrame;
assign StartPAD = ~Collision & StateData[1] & TxEndFrm & Pad & ~NibbleMinFl;
assign StartFCS = ~Collision & StateData[1] & TxEndFrm & (~Pad | Pad & NibbleMinFl) & CrcEn
| ~Collision & StatePAD & NibbleMinFl & CrcEn;
assign StartJam = (Collision | UnderRun) & ((StatePreamble & NibCntEq15) | (|StateData[1:0]) | StatePAD | StateFCS);
assign StartBackoff = StateJam & ~RandomEq0 & ColWindow & ~RetryMax & NibCntEq7 & ~NoBckof;
assign StartDefer = StateIPG & ~Rule1 & CarrierSense & NibCnt[6:0] <= IPGR1 & NibCnt[6:0] != IPGR2
| StateIdle & CarrierSense
| StateJam & NibCntEq7 & (NoBckof | RandomEq0 | ~ColWindow | RetryMax)
| StateBackOff & (TxUnderRun | RandomEqByteCnt)
| StartTxDone | TooBig;
assign DeferIndication = StateIdle & CarrierSense;
// Tx State Machine
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
begin
StateIPG <= #Tp 1'b0;
StateIdle <= #Tp 1'b0;
StatePreamble <= #Tp 1'b0;
StateData[1:0] <= #Tp 2'b0;
StatePAD <= #Tp 1'b0;
StateFCS <= #Tp 1'b0;
StateJam <= #Tp 1'b0;
StateJam_q <= #Tp 1'b0;
StateBackOff <= #Tp 1'b0;
StateDefer <= #Tp 1'b1;
end
else
begin
StateData[1:0] <= #Tp StartData[1:0];
StateJam_q <= #Tp StateJam;
if(StartDefer | StartIdle)
StateIPG <= #Tp 1'b0;
else
if(StartIPG)
StateIPG <= #Tp 1'b1;
if(StartDefer | StartPreamble)
StateIdle <= #Tp 1'b0;
else
if(StartIdle)
StateIdle <= #Tp 1'b1;
if(StartData[0] | StartJam)
StatePreamble <= #Tp 1'b0;
else
if(StartPreamble)
StatePreamble <= #Tp 1'b1;
if(StartFCS | StartJam)
StatePAD <= #Tp 1'b0;
else
if(StartPAD)
StatePAD <= #Tp 1'b1;
if(StartJam | StartDefer)
StateFCS <= #Tp 1'b0;
else
if(StartFCS)
StateFCS <= #Tp 1'b1;
if(StartBackoff | StartDefer)
StateJam <= #Tp 1'b0;
else
if(StartJam)
StateJam <= #Tp 1'b1;
if(StartDefer)
StateBackOff <= #Tp 1'b0;
else
if(StartBackoff)
StateBackOff <= #Tp 1'b1;
if(StartIPG)
StateDefer <= #Tp 1'b0;
else
if(StartDefer)
StateDefer <= #Tp 1'b1;
end
end
// This sections defines which interpack gap rule to use
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
Rule1 <= #Tp 1'b0;
else
begin
if(StateIdle | StateBackOff)
Rule1 <= #Tp 1'b0;
else
if(StatePreamble | FullD)
Rule1 <= #Tp 1'b1;
end
end
endmodule
//////////////////////////////////////////////////////////////////////
//// ////
//// eth_wishbone.v ////
//// ////
//// This file is part of the Ethernet IP core project ////
//// http://www.opencores.org/projects/ethmac/ ////
//// ////
//// Author(s): ////
//// - Igor Mohor ([email protected]) ////
//// ////
//// All additional information is available in the Readme.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001, 2002 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: eth_wishbone.v,v $
// Revision 1.56 2004/04/30 10:30:00 igorm
// Accidently deleted line put back.
//
// Revision 1.55 2004/04/26 15:26:23 igorm
// - Bug connected to the TX_BD_NUM_Wr signal fixed (bug came in with the
// previous update of the core.
// - TxBDAddress is set to 0 after the TX is enabled in the MODER register.
// - RxBDAddress is set to r_TxBDNum<<1 after the RX is enabled in the MODER
// register. (thanks to Mathias and Torbjorn)
// - Multicast reception was fixed. Thanks to Ulrich Gries
//
// Revision 1.54 2003/11/12 18:24:59 tadejm
// WISHBONE slave changed and tested from only 32-bit accesss to byte access.
//
// Revision 1.53 2003/10/17 07:46:17 markom
// mbist signals updated according to newest convention
//
// Revision 1.52 2003/01/30 14:51:31 mohor
// Reset has priority in some flipflops.
//
// Revision 1.51 2003/01/30 13:36:22 mohor
// A new bug (entered with previous update) fixed. When abort occured sometimes
// data transmission was blocked.
//
// Revision 1.50 2003/01/22 13:49:26 tadejm
// When control packets were received, they were ignored in some cases.
//
// Revision 1.49 2003/01/21 12:09:40 mohor
// When receiving normal data frame and RxFlow control was switched on, RXB
// interrupt was not set.
//
// Revision 1.48 2003/01/20 12:05:26 mohor
// When in full duplex, transmit was sometimes blocked. Fixed.
//
// Revision 1.47 2002/11/22 13:26:21 mohor
// Registers RxStatusWrite_rck and RxStatusWriteLatched were not used
// anywhere. Removed.
//
// Revision 1.46 2002/11/22 01:57:06 mohor
// Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort
// synchronized.
//
// Revision 1.45 2002/11/19 17:33:34 mohor
// AddressMiss status is connecting to the Rx BD. AddressMiss is identifying
// that a frame was received because of the promiscous mode.
//
// Revision 1.44 2002/11/13 22:21:40 tadejm
// RxError is not generated when small frame reception is enabled and small
// frames are received.
//
// Revision 1.43 2002/10/18 20:53:34 mohor
// case changed to casex.
//
// Revision 1.42 2002/10/18 17:04:20 tadejm
// Changed BIST scan signals.
//
// Revision 1.41 2002/10/18 15:42:09 tadejm
// Igor added WB burst support and repaired BUG when handling TX under-run and retry.
//
// Revision 1.40 2002/10/14 16:07:02 mohor
// TxStatus is written after last access to the TX fifo is finished (in case of abort
// or retry). TxDone is fixed.
//
// Revision 1.39 2002/10/11 15:35:20 mohor
// txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v file,
// TxDone and TxRetry are generated after the current WISHBONE access is
// finished.
//
// Revision 1.38 2002/10/10 16:29:30 mohor
// BIST added.
//
// Revision 1.37 2002/09/11 14:18:46 mohor
// Sometimes both RxB_IRQ and RxE_IRQ were activated. Bug fixed.
//
// Revision 1.36 2002/09/10 13:48:46 mohor
// Reception is possible after RxPointer is read and not after BD is read. For
// that reason RxBDReady is changed to RxReady.
// Busy_IRQ interrupt connected. When there is no RxBD ready and frame
// comes, interrupt is generated.
//
// Revision 1.35 2002/09/10 10:35:23 mohor
// Ethernet debug registers removed.
//
// Revision 1.34 2002/09/08 16:31:49 mohor
// Async reset for WB_ACK_O removed (when core was in reset, it was
// impossible to access BDs).
// RxPointers and TxPointers names changed to be more descriptive.
// TxUnderRun synchronized.
//
// Revision 1.33 2002/09/04 18:47:57 mohor
// Debug registers reg1, 2, 3, 4 connected. Synchronization of many signals
// changed (bugs fixed). Access to un-alligned buffers fixed. RxAbort signal
// was not used OK.
//
// Revision 1.32 2002/08/14 19:31:48 mohor
// Register TX_BD_NUM is changed so it contains value of the Tx buffer descriptors. No
// need to multiply or devide any more.
//
// Revision 1.31 2002/07/25 18:29:01 mohor
// WriteRxDataToMemory signal changed so end of frame (when last word is
// written to fifo) is changed.
//
// Revision 1.30 2002/07/23 15:28:31 mohor
// Ram , used for BDs changed from generic_spram to eth_spram_256x32.
//
// Revision 1.29 2002/07/20 00:41:32 mohor
// ShiftEnded synchronization changed.
//
// Revision 1.28 2002/07/18 16:11:46 mohor
// RxBDAddress takes `ETH_TX_BD_NUM_DEF value after reset.
//
// Revision 1.27 2002/07/11 02:53:20 mohor
// RxPointer bug fixed.
//
// Revision 1.26 2002/07/10 13:12:38 mohor
// Previous bug wasn't succesfully removed. Now fixed.
//
// Revision 1.25 2002/07/09 23:53:24 mohor
// Master state machine had a bug when switching from master write to
// master read.
//
// Revision 1.24 2002/07/09 20:44:41 mohor
// m_wb_cyc_o signal released after every single transfer.
//
// Revision 1.23 2002/05/03 10:15:50 mohor
// Outputs registered. Reset changed for eth_wishbone module.
//
// Revision 1.22 2002/04/24 08:52:19 mohor
// Compiler directives added. Tx and Rx fifo size incremented. A "late collision"
// bug fixed.
//
// Revision 1.21 2002/03/29 16:18:11 lampret
// Small typo fixed.
//
// Revision 1.20 2002/03/25 16:19:12 mohor
// Any address can be used for Tx and Rx BD pointers. Address does not need
// to be aligned.
//
// Revision 1.19 2002/03/19 12:51:50 mohor
// Comments in Slovene language removed.
//
// Revision 1.18 2002/03/19 12:46:52 mohor
// casex changed with case, fifo reset changed.
//
// Revision 1.17 2002/03/09 16:08:45 mohor
// rx_fifo was not always cleared ok. Fixed.
//
// Revision 1.16 2002/03/09 13:51:20 mohor
// Status was not latched correctly sometimes. Fixed.
//
// Revision 1.15 2002/03/08 06:56:46 mohor
// Big Endian problem when sending frames fixed.
//
// Revision 1.14 2002/03/02 19:12:40 mohor
// Byte ordering changed (Big Endian used). casex changed with case because
// Xilinx Foundation had problems. Tested in HW. It WORKS.
//
// Revision 1.13 2002/02/26 16:59:55 mohor
// Small fixes for external/internal DMA missmatches.
//
// Revision 1.12 2002/02/26 16:22:07 mohor
// Interrupts changed
//
// Revision 1.11 2002/02/15 17:07:39 mohor
// Status was not written correctly when frames were discarted because of
// address mismatch.
//
// Revision 1.10 2002/02/15 12:17:39 mohor
// RxStartFrm cleared when abort or retry comes.
//
// Revision 1.9 2002/02/15 11:59:10 mohor
// Changes that were lost when updating from 1.5 to 1.8 fixed.
//
// Revision 1.8 2002/02/14 20:54:33 billditt
// Addition of new module eth_addrcheck.v
//
// Revision 1.7 2002/02/12 17:03:47 mohor
// RxOverRun added to statuses.
//
// Revision 1.6 2002/02/11 09:18:22 mohor
// Tx status is written back to the BD.
//
// Revision 1.5 2002/02/08 16:21:54 mohor
// Rx status is written back to the BD.
//
// Revision 1.4 2002/02/06 14:10:21 mohor
// non-DMA host interface added. Select the right configutation in eth_defines.
//
// Revision 1.3 2002/02/05 16:44:39 mohor
// Both rx and tx part are finished. Tested with wb_clk_i between 10 and 200
// MHz. Statuses, overrun, control frame transmission and reception still need
// to be fixed.
//
// Revision 1.2 2002/02/01 12:46:51 mohor
// Tx part finished. TxStatus needs to be fixed. Pause request needs to be
// added.
//
// Revision 1.1 2002/01/23 10:47:59 mohor
// Initial version. Equals to eth_wishbonedma.v at this moment.
//
//
//
module eth_wishbone
(
// WISHBONE common
WB_CLK_I, WB_DAT_I, WB_DAT_O,
// WISHBONE slave
WB_ADR_I, WB_WE_I, WB_ACK_O,
BDCs,
Reset,
// WISHBONE master
m_wb_adr_o, m_wb_sel_o, m_wb_we_o,
m_wb_dat_o, m_wb_dat_i, m_wb_cyc_o,
m_wb_stb_o, m_wb_ack_i, m_wb_err_i,
`ifdef ETH_WISHBONE_B3
m_wb_cti_o, m_wb_bte_o,
`endif
//TX
MTxClk, TxStartFrm, TxEndFrm, TxUsedData, TxData,
TxRetry, TxAbort, TxUnderRun, TxDone, PerPacketCrcEn,
PerPacketPad,
//RX
MRxClk, RxData, RxValid, RxStartFrm, RxEndFrm, RxAbort, RxStatusWriteLatched_sync2,
// Register
r_TxEn, r_RxEn, r_TxBDNum, r_RxFlow, r_PassAll,
// Interrupts
TxB_IRQ, TxE_IRQ, RxB_IRQ, RxE_IRQ, Busy_IRQ,
// Rx Status
InvalidSymbol, LatchedCrcError, RxLateCollision, ShortFrame, DribbleNibble,
ReceivedPacketTooBig, RxLength, LoadRxStatus, ReceivedPacketGood, AddressMiss,
ReceivedPauseFrm,
// Tx Status
RetryCntLatched, RetryLimit, LateCollLatched, DeferLatched, CarrierSenseLost,
// Bist
`ifdef ETH_BIST
// debug chain signals
mbist_si_i, // bist scan serial in
mbist_so_o, // bist scan serial out
mbist_ctrl_i, // bist chain shift control
`endif
//RAM signals to external BD RAM
ram_ce, ram_we, ram_oe, ram_addr, ram_di, ram_do
);
parameter Tp = 1;
// WISHBONE common
input WB_CLK_I; // WISHBONE clock
input [31:0] WB_DAT_I; // WISHBONE data input
output [31:0] WB_DAT_O; // WISHBONE data output
// WISHBONE slave
input [9:2] WB_ADR_I; // WISHBONE address input
input WB_WE_I; // WISHBONE write enable input
input [3:0] BDCs; // Buffer descriptors are selected
output WB_ACK_O; // WISHBONE acknowledge output
// WISHBONE master
output [31:0] m_wb_adr_o; //
output [3:0] m_wb_sel_o; //
output m_wb_we_o; //
output [31:0] m_wb_dat_o; //
output m_wb_cyc_o; //
output m_wb_stb_o; //
input [31:0] m_wb_dat_i; //
input m_wb_ack_i; //
input m_wb_err_i; //
`ifdef ETH_WISHBONE_B3
output [2:0] m_wb_cti_o; // Cycle Type Identifier
output [1:0] m_wb_bte_o; // Burst Type Extension
reg [2:0] m_wb_cti_o; // Cycle Type Identifier
`endif
input Reset; // Reset signal
// Rx Status signals
input InvalidSymbol; // Invalid symbol was received during reception in 100 Mbps mode
input LatchedCrcError; // CRC error
input RxLateCollision; // Late collision occured while receiving frame
input ShortFrame; // Frame shorter then the minimum size (r_MinFL) was received while small packets are enabled (r_RecSmall)
input DribbleNibble; // Extra nibble received
input ReceivedPacketTooBig;// Received packet is bigger than r_MaxFL
input [15:0] RxLength; // Length of the incoming frame
input LoadRxStatus; // Rx status was loaded
input ReceivedPacketGood;// Received packet's length and CRC are good
input AddressMiss; // When a packet is received AddressMiss status is written to the Rx BD
input r_RxFlow;
input r_PassAll;
input ReceivedPauseFrm;
// Tx Status signals
input [3:0] RetryCntLatched; // Latched Retry Counter
input RetryLimit; // Retry limit reached (Retry Max value + 1 attempts were made)
input LateCollLatched; // Late collision occured
input DeferLatched; // Defer indication (Frame was defered before sucessfully sent)
input CarrierSenseLost; // Carrier Sense was lost during the frame transmission
// Tx
input MTxClk; // Transmit clock (from PHY)
input TxUsedData; // Transmit packet used data
input TxRetry; // Transmit packet retry
input TxAbort; // Transmit packet abort
input TxDone; // Transmission ended
output TxStartFrm; // Transmit packet start frame
output TxEndFrm; // Transmit packet end frame
output [7:0] TxData; // Transmit packet data byte
output TxUnderRun; // Transmit packet under-run
output PerPacketCrcEn; // Per packet crc enable
output PerPacketPad; // Per packet pading
// Rx
input MRxClk; // Receive clock (from PHY)
input [7:0] RxData; // Received data byte (from PHY)
input RxValid; //
input RxStartFrm; //
input RxEndFrm; //
input RxAbort; // This signal is set when address doesn't match.
output RxStatusWriteLatched_sync2;
//Register
input r_TxEn; // Transmit enable
input r_RxEn; // Receive enable
input [7:0] r_TxBDNum; // Receive buffer descriptor number
// Interrupts
output TxB_IRQ;
output TxE_IRQ;
output RxB_IRQ;
output RxE_IRQ;
output Busy_IRQ;
// Bist
`ifdef ETH_BIST
input mbist_si_i; // bist scan serial in
output mbist_so_o; // bist scan serial out
input [`ETH_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i; // bist chain shift control
`endif
//RAM
output ram_ce;
output [3:0] ram_we;
output ram_oe;
output [7:0] ram_addr;
output [31:0] ram_di;
input [31:0] ram_do;
reg [7:0] ram_addr;
reg [31:0] ram_di;
reg TxB_IRQ;
reg TxE_IRQ;
reg RxB_IRQ;
reg RxE_IRQ;
reg TxStartFrm;
reg TxEndFrm;
reg [7:0] TxData;
reg TxUnderRun;
reg TxUnderRun_wb;
reg TxBDRead;
wire TxStatusWrite;
reg [1:0] TxValidBytesLatched;
reg [15:0] TxLength;
reg [15:0] LatchedTxLength;
reg [14:11] TxStatus;
reg [14:13] RxStatus;
reg TxStartFrm_wb;
reg TxRetry_wb;
reg TxAbort_wb;
reg TxDone_wb;
reg TxDone_wb_q;
reg TxAbort_wb_q;
reg TxRetry_wb_q;
reg TxRetryPacket;
reg TxRetryPacket_NotCleared;
reg TxDonePacket;
reg TxDonePacket_NotCleared;
reg TxAbortPacket;
reg TxAbortPacket_NotCleared;
reg RxBDReady;
reg RxReady;
reg TxBDReady;
reg RxBDRead;
reg [31:0] TxDataLatched;
reg [1:0] TxByteCnt;
reg LastWord;
reg ReadTxDataFromFifo_tck;
reg BlockingTxStatusWrite;
reg BlockingTxBDRead;
reg Flop;
reg [7:0] TxBDAddress;
reg [7:0] RxBDAddress;
reg TxRetrySync1;
reg TxAbortSync1;
reg TxDoneSync1;
reg TxAbort_q;
reg TxRetry_q;
reg TxUsedData_q;
reg [31:0] RxDataLatched2;
reg [31:8] RxDataLatched1; // Big Endian Byte Ordering
reg [1:0] RxValidBytes;
reg [1:0] RxByteCnt;
reg LastByteIn;
reg ShiftWillEnd;
reg WriteRxDataToFifo;
reg [15:0] LatchedRxLength;
reg RxAbortLatched;
reg ShiftEnded;
reg RxOverrun;
reg [3:0] BDWrite; // BD Write Enable for access from WISHBONE side
reg BDRead; // BD Read access from WISHBONE side
wire [31:0] RxBDDataIn; // Rx BD data in
wire [31:0] TxBDDataIn; // Tx BD data in
reg TxEndFrm_wb;
wire TxRetryPulse;
wire TxDonePulse;
wire TxAbortPulse;
wire StartRxBDRead;
wire StartTxBDRead;
wire TxIRQEn;
wire WrapTxStatusBit;
wire RxIRQEn;
wire WrapRxStatusBit;
wire [1:0] TxValidBytes;
wire [7:0] TempTxBDAddress;
wire [7:0] TempRxBDAddress;
wire RxStatusWrite;
reg WB_ACK_O;
wire [8:0] RxStatusIn;
reg [8:0] RxStatusInLatched;
reg WbEn, WbEn_q;
reg RxEn, RxEn_q;
reg TxEn, TxEn_q;
reg r_TxEn_q;
reg r_RxEn_q;
wire StartTxPointerRead;
reg TxPointerRead;
reg TxEn_needed;
reg RxEn_needed;
wire StartRxPointerRead;
reg RxPointerRead;
`ifdef ETH_WISHBONE_B3
assign m_wb_bte_o = 2'b00; // Linear burst
`endif
always @ (posedge WB_CLK_I)
begin
WB_ACK_O <=#Tp (|BDWrite) & WbEn & WbEn_q | BDRead & WbEn & ~WbEn_q;
end
assign WB_DAT_O = ram_do;
//NOT USED ANYMORE, EXTERNAL RAM INSTEAD.
// Generic synchronous single-port RAM interface
//eth_spram_256x32 bd_ram (
// .clk(WB_CLK_I), .rst(Reset), .ce(ram_ce), .we(ram_we), .oe(ram_oe), .addr(ram_addr), .di(ram_di), .do(ram_do)
//`ifdef ETH_BIST
// ,
// .mbist_si_i (mbist_si_i),
// .mbist_so_o (mbist_so_o),
// .mbist_ctrl_i (mbist_ctrl_i)
//`endif
//);
assign ram_ce = 1'b1;
assign ram_we = (BDWrite & {4{(WbEn & WbEn_q)}}) | {4{(TxStatusWrite | RxStatusWrite)}};
assign ram_oe = BDRead & WbEn & WbEn_q | TxEn & TxEn_q & (TxBDRead | TxPointerRead) | RxEn & RxEn_q & (RxBDRead | RxPointerRead);
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
TxEn_needed <=#Tp 1'b0;
else
if(~TxBDReady & r_TxEn & WbEn & ~WbEn_q)
TxEn_needed <=#Tp 1'b1;
else
if(TxPointerRead & TxEn & TxEn_q)
TxEn_needed <=#Tp 1'b0;
end
// Enabling access to the RAM for three devices.
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
begin
WbEn <=#Tp 1'b1;
RxEn <=#Tp 1'b0;
TxEn <=#Tp 1'b0;
ram_addr <=#Tp 8'h0;
ram_di <=#Tp 32'h0;
BDRead <=#Tp 1'b0;
BDWrite <=#Tp 1'b0;
end
else
begin
// Switching between three stages depends on enable signals
case ({WbEn_q, RxEn_q, TxEn_q, RxEn_needed, TxEn_needed}) // synopsys parallel_case
5'b100_10, 5'b100_11 :
begin
WbEn <=#Tp 1'b0;
RxEn <=#Tp 1'b1; // wb access stage and r_RxEn is enabled
TxEn <=#Tp 1'b0;
ram_addr <=#Tp RxBDAddress + RxPointerRead;
ram_di <=#Tp RxBDDataIn;
end
5'b100_01 :
begin
WbEn <=#Tp 1'b0;
RxEn <=#Tp 1'b0;
TxEn <=#Tp 1'b1; // wb access stage, r_RxEn is disabled but r_TxEn is enabled
ram_addr <=#Tp TxBDAddress + TxPointerRead;
ram_di <=#Tp TxBDDataIn;
end
5'b010_00, 5'b010_10 :
begin
WbEn <=#Tp 1'b1; // RxEn access stage and r_TxEn is disabled
RxEn <=#Tp 1'b0;
TxEn <=#Tp 1'b0;
ram_addr <=#Tp WB_ADR_I[9:2];
ram_di <=#Tp WB_DAT_I;
BDWrite <=#Tp BDCs[3:0] & {4{WB_WE_I}};
BDRead <=#Tp (|BDCs) & ~WB_WE_I;
end
5'b010_01, 5'b010_11 :
begin
WbEn <=#Tp 1'b0;
RxEn <=#Tp 1'b0;
TxEn <=#Tp 1'b1; // RxEn access stage and r_TxEn is enabled
ram_addr <=#Tp TxBDAddress + TxPointerRead;
ram_di <=#Tp TxBDDataIn;
end
5'b001_00, 5'b001_01, 5'b001_10, 5'b001_11 :
begin
WbEn <=#Tp 1'b1; // TxEn access stage (we always go to wb access stage)
RxEn <=#Tp 1'b0;
TxEn <=#Tp 1'b0;
ram_addr <=#Tp WB_ADR_I[9:2];
ram_di <=#Tp WB_DAT_I;
BDWrite <=#Tp BDCs[3:0] & {4{WB_WE_I}};
BDRead <=#Tp (|BDCs) & ~WB_WE_I;
end
5'b100_00 :
begin
WbEn <=#Tp 1'b0; // WbEn access stage and there is no need for other stages. WbEn needs to be switched off for a bit
end
5'b000_00 :
begin
WbEn <=#Tp 1'b1; // Idle state. We go to WbEn access stage.
RxEn <=#Tp 1'b0;
TxEn <=#Tp 1'b0;
ram_addr <=#Tp WB_ADR_I[9:2];
ram_di <=#Tp WB_DAT_I;
BDWrite <=#Tp BDCs[3:0] & {4{WB_WE_I}};
BDRead <=#Tp (|BDCs) & ~WB_WE_I;
end
endcase
end
end
// Delayed stage signals
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
begin
WbEn_q <=#Tp 1'b0;
RxEn_q <=#Tp 1'b0;
TxEn_q <=#Tp 1'b0;
r_TxEn_q <=#Tp 1'b0;
r_RxEn_q <=#Tp 1'b0;
end
else
begin
WbEn_q <=#Tp WbEn;
RxEn_q <=#Tp RxEn;
TxEn_q <=#Tp TxEn;
r_TxEn_q <=#Tp r_TxEn;
r_RxEn_q <=#Tp r_RxEn;
end
end
// Changes for tx occur every second clock. Flop is used for this manner.
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
Flop <=#Tp 1'b0;
else
if(TxDone | TxAbort | TxRetry_q)
Flop <=#Tp 1'b0;
else
if(TxUsedData)
Flop <=#Tp ~Flop;
end
wire ResetTxBDReady;
assign ResetTxBDReady = TxDonePulse | TxAbortPulse | TxRetryPulse;
// Latching READY status of the Tx buffer descriptor
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
TxBDReady <=#Tp 1'b0;
else
if(TxEn & TxEn_q & TxBDRead)
TxBDReady <=#Tp ram_do[15] & (ram_do[31:16] > 4); // TxBDReady is sampled only once at the beginning.
else // Only packets larger then 4 bytes are transmitted.
if(ResetTxBDReady)
TxBDReady <=#Tp 1'b0;
end
// Reading the Tx buffer descriptor
assign StartTxBDRead = (TxRetryPacket_NotCleared | TxStatusWrite) & ~BlockingTxBDRead & ~TxBDReady;
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
TxBDRead <=#Tp 1'b1;
else
if(StartTxBDRead)
TxBDRead <=#Tp 1'b1;
else
if(TxBDReady)
TxBDRead <=#Tp 1'b0;
end
// Reading Tx BD pointer
assign StartTxPointerRead = TxBDRead & TxBDReady;
// Reading Tx BD Pointer
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
TxPointerRead <=#Tp 1'b0;
else
if(StartTxPointerRead)
TxPointerRead <=#Tp 1'b1;
else
if(TxEn_q)
TxPointerRead <=#Tp 1'b0;
end
// Writing status back to the Tx buffer descriptor
assign TxStatusWrite = (TxDonePacket_NotCleared | TxAbortPacket_NotCleared) & TxEn & TxEn_q & ~BlockingTxStatusWrite;
// Status writing must occur only once. Meanwhile it is blocked.
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
BlockingTxStatusWrite <=#Tp 1'b0;
else
if(~TxDone_wb & ~TxAbort_wb)
BlockingTxStatusWrite <=#Tp 1'b0;
else
if(TxStatusWrite)
BlockingTxStatusWrite <=#Tp 1'b1;
end
reg BlockingTxStatusWrite_sync1;
reg BlockingTxStatusWrite_sync2;
// Synchronizing BlockingTxStatusWrite to MTxClk
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
BlockingTxStatusWrite_sync1 <=#Tp 1'b0;
else
BlockingTxStatusWrite_sync1 <=#Tp BlockingTxStatusWrite;
end
// Synchronizing BlockingTxStatusWrite to MTxClk
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
BlockingTxStatusWrite_sync2 <=#Tp 1'b0;
else
BlockingTxStatusWrite_sync2 <=#Tp BlockingTxStatusWrite_sync1;
end
// TxBDRead state is activated only once.
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
BlockingTxBDRead <=#Tp 1'b0;
else
if(StartTxBDRead)
BlockingTxBDRead <=#Tp 1'b1;
else
if(~StartTxBDRead & ~TxBDReady)
BlockingTxBDRead <=#Tp 1'b0;
end
// Latching status from the tx buffer descriptor
// Data is avaliable one cycle after the access is started (at that time signal TxEn is not active)
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
TxStatus <=#Tp 4'h0;
else
if(TxEn & TxEn_q & TxBDRead)
TxStatus <=#Tp ram_do[14:11];
end
reg ReadTxDataFromMemory;
wire WriteRxDataToMemory;
reg MasterWbTX;
reg MasterWbRX;
reg [31:0] m_wb_adr_o;
reg m_wb_cyc_o;
reg m_wb_stb_o;
reg [3:0] m_wb_sel_o;
reg m_wb_we_o;
wire TxLengthEq0;
wire TxLengthLt4;
reg BlockingIncrementTxPointer;
reg [31:2] TxPointerMSB;
reg [1:0] TxPointerLSB;
reg [1:0] TxPointerLSB_rst;
reg [31:2] RxPointerMSB;
reg [1:0] RxPointerLSB_rst;
wire RxBurstAcc;
wire RxWordAcc;
wire RxHalfAcc;
wire RxByteAcc;
//Latching length from the buffer descriptor;
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
TxLength <=#Tp 16'h0;
else
if(TxEn & TxEn_q & TxBDRead)
TxLength <=#Tp ram_do[31:16];
else
if(MasterWbTX & m_wb_ack_i)
begin
if(TxLengthLt4)
TxLength <=#Tp 16'h0;
else
if(TxPointerLSB_rst==2'h0)
TxLength <=#Tp TxLength - 3'h4; // Length is subtracted at the data request
else
if(TxPointerLSB_rst==2'h1)
TxLength <=#Tp TxLength - 3'h3; // Length is subtracted at the data request
else
if(TxPointerLSB_rst==2'h2)
TxLength <=#Tp TxLength - 3'h2; // Length is subtracted at the data request
else
if(TxPointerLSB_rst==2'h3)
TxLength <=#Tp TxLength - 3'h1; // Length is subtracted at the data request
end
end
//Latching length from the buffer descriptor;
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
LatchedTxLength <=#Tp 16'h0;
else
if(TxEn & TxEn_q & TxBDRead)
LatchedTxLength <=#Tp ram_do[31:16];
end
assign TxLengthEq0 = TxLength == 0;
assign TxLengthLt4 = TxLength < 4;
reg cyc_cleared;
reg IncrTxPointer;
// Latching Tx buffer pointer from buffer descriptor. Only 30 MSB bits are latched
// because TxPointerMSB is only used for word-aligned accesses.
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
TxPointerMSB <=#Tp 30'h0;
else
if(TxEn & TxEn_q & TxPointerRead)
TxPointerMSB <=#Tp ram_do[31:2];
else
if(IncrTxPointer & ~BlockingIncrementTxPointer)
TxPointerMSB <=#Tp TxPointerMSB + 1'b1; // TxPointer is word-aligned
end
// Latching 2 MSB bits of the buffer descriptor. Since word accesses are performed,
// valid data does not necesserly start at byte 0 (could be byte 0, 1, 2 or 3). This
// signals are used for proper selection of the start byte (TxData and TxByteCnt) are
// set by this two bits.
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
TxPointerLSB[1:0] <=#Tp 0;
else
if(TxEn & TxEn_q & TxPointerRead)
TxPointerLSB[1:0] <=#Tp ram_do[1:0];
end
// Latching 2 MSB bits of the buffer descriptor.
// After the read access, TxLength needs to be decremented for the number of the valid
// bytes (1 to 4 bytes are valid in the first word). After the first read all bytes are
// valid so this two bits are reset to zero.
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
TxPointerLSB_rst[1:0] <=#Tp 0;
else
if(TxEn & TxEn_q & TxPointerRead)
TxPointerLSB_rst[1:0] <=#Tp ram_do[1:0];
else
if(MasterWbTX & m_wb_ack_i) // After first access pointer is word alligned
TxPointerLSB_rst[1:0] <=#Tp 0;
end
reg [3:0] RxByteSel;
wire MasterAccessFinished;
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
BlockingIncrementTxPointer <=#Tp 0;
else
if(MasterAccessFinished)
BlockingIncrementTxPointer <=#Tp 0;
else
if(IncrTxPointer)
BlockingIncrementTxPointer <=#Tp 1'b1;
end
wire TxBufferAlmostFull;
wire TxBufferFull;
wire TxBufferEmpty;
wire TxBufferAlmostEmpty;
wire SetReadTxDataFromMemory;
reg BlockReadTxDataFromMemory;
assign SetReadTxDataFromMemory = TxEn & TxEn_q & TxPointerRead;
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
ReadTxDataFromMemory <=#Tp 1'b0;
else
if(TxLengthEq0 | TxAbortPulse | TxRetryPulse)
ReadTxDataFromMemory <=#Tp 1'b0;
else
if(SetReadTxDataFromMemory)
ReadTxDataFromMemory <=#Tp 1'b1;
end
reg tx_burst_en;
reg rx_burst_en;
wire ReadTxDataFromMemory_2 = ReadTxDataFromMemory & ~BlockReadTxDataFromMemory;
wire tx_burst = ReadTxDataFromMemory_2 & tx_burst_en;
wire [31:0] TxData_wb;
wire ReadTxDataFromFifo_wb;
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
BlockReadTxDataFromMemory <=#Tp 1'b0;
else
if((TxBufferAlmostFull | TxLength <= 4)& MasterWbTX & (~cyc_cleared) & (!(TxAbortPacket_NotCleared | TxRetryPacket_NotCleared)))
BlockReadTxDataFromMemory <=#Tp 1'b1;
else
if(ReadTxDataFromFifo_wb | TxDonePacket | TxAbortPacket | TxRetryPacket)
BlockReadTxDataFromMemory <=#Tp 1'b0;
end
assign MasterAccessFinished = m_wb_ack_i | m_wb_err_i;
wire [`ETH_TX_FIFO_CNT_WIDTH-1:0] txfifo_cnt;
wire [`ETH_RX_FIFO_CNT_WIDTH-1:0] rxfifo_cnt;
reg [`ETH_BURST_CNT_WIDTH-1:0] tx_burst_cnt;
reg [`ETH_BURST_CNT_WIDTH-1:0] rx_burst_cnt;
wire rx_burst;
wire enough_data_in_rxfifo_for_burst;
wire enough_data_in_rxfifo_for_burst_plus1;
// Enabling master wishbone access to the memory for two devices TX and RX.
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
begin
MasterWbTX <=#Tp 1'b0;
MasterWbRX <=#Tp 1'b0;
m_wb_adr_o <=#Tp 32'h0;
m_wb_cyc_o <=#Tp 1'b0;
m_wb_stb_o <=#Tp 1'b0;
m_wb_we_o <=#Tp 1'b0;
m_wb_sel_o <=#Tp 4'h0;
cyc_cleared<=#Tp 1'b0;
tx_burst_cnt<=#Tp 0;
rx_burst_cnt<=#Tp 0;
IncrTxPointer<=#Tp 1'b0;
tx_burst_en<=#Tp 1'b1;
rx_burst_en<=#Tp 1'b0;
`ifdef ETH_WISHBONE_B3
m_wb_cti_o <=#Tp 3'b0;
`endif
end
else
begin
// Switching between two stages depends on enable signals
casex ({MasterWbTX, MasterWbRX, ReadTxDataFromMemory_2, WriteRxDataToMemory, MasterAccessFinished, cyc_cleared, tx_burst, rx_burst}) // synopsys parallel_case
8'b00_10_00_10, // Idle and MRB needed
8'b10_1x_10_1x, // MRB continues
8'b10_10_01_10, // Clear (previously MR) and MRB needed
8'b01_1x_01_1x : // Clear (previously MW) and MRB needed
begin
MasterWbTX <=#Tp 1'b1; // tx burst
MasterWbRX <=#Tp 1'b0;
m_wb_cyc_o <=#Tp 1'b1;
m_wb_stb_o <=#Tp 1'b1;
m_wb_we_o <=#Tp 1'b0;
m_wb_sel_o <=#Tp 4'hf;
cyc_cleared<=#Tp 1'b0;
IncrTxPointer<=#Tp 1'b1;
tx_burst_cnt <=#Tp tx_burst_cnt+1;
if(tx_burst_cnt==0)
m_wb_adr_o <=#Tp {TxPointerMSB, 2'h0};
else
m_wb_adr_o <=#Tp m_wb_adr_o+3'h4;
if(tx_burst_cnt==(`ETH_BURST_LENGTH-1))
begin
tx_burst_en<=#Tp 1'b0;
`ifdef ETH_WISHBONE_B3
m_wb_cti_o <=#Tp 3'b111;
`endif
end
else
begin
`ifdef ETH_WISHBONE_B3
m_wb_cti_o <=#Tp 3'b010;
`endif
end
end
8'b00_x1_00_x1, // Idle and MWB needed
8'b01_x1_10_x1, // MWB continues
8'b01_01_01_01, // Clear (previously MW) and MWB needed
8'b10_x1_01_x1 : // Clear (previously MR) and MWB needed
begin
MasterWbTX <=#Tp 1'b0; // rx burst
MasterWbRX <=#Tp 1'b1;
m_wb_cyc_o <=#Tp 1'b1;
m_wb_stb_o <=#Tp 1'b1;
m_wb_we_o <=#Tp 1'b1;
m_wb_sel_o <=#Tp RxByteSel;
IncrTxPointer<=#Tp 1'b0;
cyc_cleared<=#Tp 1'b0;
rx_burst_cnt <=#Tp rx_burst_cnt+1;
if(rx_burst_cnt==0)
m_wb_adr_o <=#Tp {RxPointerMSB, 2'h0};
else
m_wb_adr_o <=#Tp m_wb_adr_o+3'h4;
if(rx_burst_cnt==(`ETH_BURST_LENGTH-1))
begin
rx_burst_en<=#Tp 1'b0;
`ifdef ETH_WISHBONE_B3
m_wb_cti_o <=#Tp 3'b111;
`endif
end
else
begin
`ifdef ETH_WISHBONE_B3
m_wb_cti_o <=#Tp 3'b010;
`endif
end
end
8'b00_x1_00_x0 : // idle and MW is needed (data write to rx buffer)
begin
MasterWbTX <=#Tp 1'b0;
MasterWbRX <=#Tp 1'b1;
m_wb_adr_o <=#Tp {RxPointerMSB, 2'h0};
m_wb_cyc_o <=#Tp 1'b1;
m_wb_stb_o <=#Tp 1'b1;
m_wb_we_o <=#Tp 1'b1;
m_wb_sel_o <=#Tp RxByteSel;
IncrTxPointer<=#Tp 1'b0;
end
8'b00_10_00_00 : // idle and MR is needed (data read from tx buffer)
begin
MasterWbTX <=#Tp 1'b1;
MasterWbRX <=#Tp 1'b0;
m_wb_adr_o <=#Tp {TxPointerMSB, 2'h0};
m_wb_cyc_o <=#Tp 1'b1;
m_wb_stb_o <=#Tp 1'b1;
m_wb_we_o <=#Tp 1'b0;
m_wb_sel_o <=#Tp 4'hf;
IncrTxPointer<=#Tp 1'b1;
end
8'b10_10_01_00, // MR and MR is needed (data read from tx buffer)
8'b01_1x_01_0x : // MW and MR is needed (data read from tx buffer)
begin
MasterWbTX <=#Tp 1'b1;
MasterWbRX <=#Tp 1'b0;
m_wb_adr_o <=#Tp {TxPointerMSB, 2'h0};
m_wb_cyc_o <=#Tp 1'b1;
m_wb_stb_o <=#Tp 1'b1;
m_wb_we_o <=#Tp 1'b0;
m_wb_sel_o <=#Tp 4'hf;
cyc_cleared<=#Tp 1'b0;
IncrTxPointer<=#Tp 1'b1;
end
8'b01_01_01_00, // MW and MW needed (data write to rx buffer)
8'b10_x1_01_x0 : // MR and MW is needed (data write to rx buffer)
begin
MasterWbTX <=#Tp 1'b0;
MasterWbRX <=#Tp 1'b1;
m_wb_adr_o <=#Tp {RxPointerMSB, 2'h0};
m_wb_cyc_o <=#Tp 1'b1;
m_wb_stb_o <=#Tp 1'b1;
m_wb_we_o <=#Tp 1'b1;
m_wb_sel_o <=#Tp RxByteSel;
cyc_cleared<=#Tp 1'b0;
IncrTxPointer<=#Tp 1'b0;
end
8'b01_01_10_00, // MW and MW needed (cycle is cleared between previous and next access)
8'b01_1x_10_x0, // MW and MW or MR or MRB needed (cycle is cleared between previous and next access)
8'b10_10_10_00, // MR and MR needed (cycle is cleared between previous and next access)
8'b10_x1_10_0x : // MR and MR or MW or MWB (cycle is cleared between previous and next access)
begin
m_wb_cyc_o <=#Tp 1'b0; // whatever and master read or write is needed. We need to clear m_wb_cyc_o before next access is started
m_wb_stb_o <=#Tp 1'b0;
cyc_cleared<=#Tp 1'b1;
IncrTxPointer<=#Tp 1'b0;
tx_burst_cnt<=#Tp 0;
tx_burst_en<=#Tp txfifo_cnt<(`ETH_TX_FIFO_DEPTH-`ETH_BURST_LENGTH) & (TxLength>(`ETH_BURST_LENGTH*4+4));
rx_burst_cnt<=#Tp 0;
rx_burst_en<=#Tp MasterWbRX ? enough_data_in_rxfifo_for_burst_plus1 : enough_data_in_rxfifo_for_burst; // Counter is not decremented, yet, so plus1 is used.
`ifdef ETH_WISHBONE_B3
m_wb_cti_o <=#Tp 3'b0;
`endif
end
8'bxx_00_10_00, // whatever and no master read or write is needed (ack or err comes finishing previous access)
8'bxx_00_01_00 : // Between cyc_cleared request was cleared
begin
MasterWbTX <=#Tp 1'b0;
MasterWbRX <=#Tp 1'b0;
m_wb_cyc_o <=#Tp 1'b0;
m_wb_stb_o <=#Tp 1'b0;
cyc_cleared<=#Tp 1'b0;
IncrTxPointer<=#Tp 1'b0;
rx_burst_cnt<=#Tp 0;
rx_burst_en<=#Tp MasterWbRX ? enough_data_in_rxfifo_for_burst_plus1 : enough_data_in_rxfifo_for_burst; // Counter is not decremented, yet, so plus1 is used.
`ifdef ETH_WISHBONE_B3
m_wb_cti_o <=#Tp 3'b0;
`endif
end
8'b00_00_00_00: // whatever and no master read or write is needed (ack or err comes finishing previous access)
begin
tx_burst_cnt<=#Tp 0;
tx_burst_en<=#Tp txfifo_cnt<(`ETH_TX_FIFO_DEPTH-`ETH_BURST_LENGTH) & (TxLength>(`ETH_BURST_LENGTH*4+4));
end
default: // Don't touch
begin
MasterWbTX <=#Tp MasterWbTX;
MasterWbRX <=#Tp MasterWbRX;
m_wb_cyc_o <=#Tp m_wb_cyc_o;
m_wb_stb_o <=#Tp m_wb_stb_o;
m_wb_sel_o <=#Tp m_wb_sel_o;
IncrTxPointer<=#Tp IncrTxPointer;
end
endcase
end
end
wire TxFifoClear;
assign TxFifoClear = (TxAbortPacket | TxRetryPacket);
eth_fifo #(`ETH_TX_FIFO_DATA_WIDTH, `ETH_TX_FIFO_DEPTH, `ETH_TX_FIFO_CNT_WIDTH)
tx_fifo ( .data_in(m_wb_dat_i), .data_out(TxData_wb),
.clk(WB_CLK_I), .reset(Reset),
.write(MasterWbTX & m_wb_ack_i), .read(ReadTxDataFromFifo_wb & ~TxBufferEmpty),
.clear(TxFifoClear), .full(TxBufferFull),
.almost_full(TxBufferAlmostFull), .almost_empty(TxBufferAlmostEmpty),
.empty(TxBufferEmpty), .cnt(txfifo_cnt)
);
reg StartOccured;
reg TxStartFrm_sync1;
reg TxStartFrm_sync2;
reg TxStartFrm_syncb1;
reg TxStartFrm_syncb2;
// Start: Generation of the TxStartFrm_wb which is then synchronized to the MTxClk
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
TxStartFrm_wb <=#Tp 1'b0;
else
if(TxBDReady & ~StartOccured & (TxBufferFull | TxLengthEq0))
TxStartFrm_wb <=#Tp 1'b1;
else
if(TxStartFrm_syncb2)
TxStartFrm_wb <=#Tp 1'b0;
end
// StartOccured: TxStartFrm_wb occurs only ones at the beginning. Then it's blocked.
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
StartOccured <=#Tp 1'b0;
else
if(TxStartFrm_wb)
StartOccured <=#Tp 1'b1;
else
if(ResetTxBDReady)
StartOccured <=#Tp 1'b0;
end
// Synchronizing TxStartFrm_wb to MTxClk
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
TxStartFrm_sync1 <=#Tp 1'b0;
else
TxStartFrm_sync1 <=#Tp TxStartFrm_wb;
end
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
TxStartFrm_sync2 <=#Tp 1'b0;
else
TxStartFrm_sync2 <=#Tp TxStartFrm_sync1;
end
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
TxStartFrm_syncb1 <=#Tp 1'b0;
else
TxStartFrm_syncb1 <=#Tp TxStartFrm_sync2;
end
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
TxStartFrm_syncb2 <=#Tp 1'b0;
else
TxStartFrm_syncb2 <=#Tp TxStartFrm_syncb1;
end
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
TxStartFrm <=#Tp 1'b0;
else
if(TxStartFrm_sync2)
TxStartFrm <=#Tp 1'b1;
else
if(TxUsedData_q | ~TxStartFrm_sync2 & (TxRetry & (~TxRetry_q) | TxAbort & (~TxAbort_q)))
TxStartFrm <=#Tp 1'b0;
end
// End: Generation of the TxStartFrm_wb which is then synchronized to the MTxClk
// TxEndFrm_wb: indicator of the end of frame
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
TxEndFrm_wb <=#Tp 1'b0;
else
if(TxLengthEq0 & TxBufferAlmostEmpty & TxUsedData)
TxEndFrm_wb <=#Tp 1'b1;
else
if(TxRetryPulse | TxDonePulse | TxAbortPulse)
TxEndFrm_wb <=#Tp 1'b0;
end
// Marks which bytes are valid within the word.
assign TxValidBytes = TxLengthLt4 ? TxLength[1:0] : 2'b0;
reg LatchValidBytes;
reg LatchValidBytes_q;
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
LatchValidBytes <=#Tp 1'b0;
else
if(TxLengthLt4 & TxBDReady)
LatchValidBytes <=#Tp 1'b1;
else
LatchValidBytes <=#Tp 1'b0;
end
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
LatchValidBytes_q <=#Tp 1'b0;
else
LatchValidBytes_q <=#Tp LatchValidBytes;
end
// Latching valid bytes
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
TxValidBytesLatched <=#Tp 2'h0;
else
if(LatchValidBytes & ~LatchValidBytes_q)
TxValidBytesLatched <=#Tp TxValidBytes;
else
if(TxRetryPulse | TxDonePulse | TxAbortPulse)
TxValidBytesLatched <=#Tp 2'h0;
end
assign TxIRQEn = TxStatus[14];
assign WrapTxStatusBit = TxStatus[13];
assign PerPacketPad = TxStatus[12];
assign PerPacketCrcEn = TxStatus[11];
assign RxIRQEn = RxStatus[14];
assign WrapRxStatusBit = RxStatus[13];
// Temporary Tx and Rx buffer descriptor address
assign TempTxBDAddress[7:0] = {8{ TxStatusWrite & ~WrapTxStatusBit}} & (TxBDAddress + 2'h2) ; // Tx BD increment or wrap (last BD)
assign TempRxBDAddress[7:0] = {8{ WrapRxStatusBit}} & (r_TxBDNum<<1) | // Using first Rx BD
{8{~WrapRxStatusBit}} & (RxBDAddress + 2'h2) ; // Using next Rx BD (incremenrement address)
// Latching Tx buffer descriptor address
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
TxBDAddress <=#Tp 8'h0;
else if (r_TxEn & (~r_TxEn_q))
TxBDAddress <=#Tp 8'h0;
else if (TxStatusWrite)
TxBDAddress <=#Tp TempTxBDAddress;
end
// Latching Rx buffer descriptor address
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
RxBDAddress <=#Tp 8'h0;
else if(r_RxEn & (~r_RxEn_q))
RxBDAddress <=#Tp r_TxBDNum << 1;
else if(RxStatusWrite)
RxBDAddress <=#Tp TempRxBDAddress;
end
wire [8:0] TxStatusInLatched = {TxUnderRun, RetryCntLatched[3:0], RetryLimit, LateCollLatched, DeferLatched, CarrierSenseLost};
assign RxBDDataIn = {LatchedRxLength, 1'b0, RxStatus, 4'h0, RxStatusInLatched};
assign TxBDDataIn = {LatchedTxLength, 1'b0, TxStatus, 2'h0, TxStatusInLatched};
// Signals used for various purposes
assign TxRetryPulse = TxRetry_wb & ~TxRetry_wb_q;
assign TxDonePulse = TxDone_wb & ~TxDone_wb_q;
assign TxAbortPulse = TxAbort_wb & ~TxAbort_wb_q;
// Generating delayed signals
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
begin
TxAbort_q <=#Tp 1'b0;
TxRetry_q <=#Tp 1'b0;
TxUsedData_q <=#Tp 1'b0;
end
else
begin
TxAbort_q <=#Tp TxAbort;
TxRetry_q <=#Tp TxRetry;
TxUsedData_q <=#Tp TxUsedData;
end
end
// Generating delayed signals
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
begin
TxDone_wb_q <=#Tp 1'b0;
TxAbort_wb_q <=#Tp 1'b0;
TxRetry_wb_q <=#Tp 1'b0;
end
else
begin
TxDone_wb_q <=#Tp TxDone_wb;
TxAbort_wb_q <=#Tp TxAbort_wb;
TxRetry_wb_q <=#Tp TxRetry_wb;
end
end
reg TxAbortPacketBlocked;
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
TxAbortPacket <=#Tp 1'b0;
else
if(TxAbort_wb & (~tx_burst_en) & MasterWbTX & MasterAccessFinished & (~TxAbortPacketBlocked) |
TxAbort_wb & (~MasterWbTX) & (~TxAbortPacketBlocked))
TxAbortPacket <=#Tp 1'b1;
else
TxAbortPacket <=#Tp 1'b0;
end
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
TxAbortPacket_NotCleared <=#Tp 1'b0;
else
if(TxEn & TxEn_q & TxAbortPacket_NotCleared)
TxAbortPacket_NotCleared <=#Tp 1'b0;
else
if(TxAbort_wb & (~tx_burst_en) & MasterWbTX & MasterAccessFinished & (~TxAbortPacketBlocked) |
TxAbort_wb & (~MasterWbTX) & (~TxAbortPacketBlocked))
TxAbortPacket_NotCleared <=#Tp 1'b1;
end
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
TxAbortPacketBlocked <=#Tp 1'b0;
else
if(!TxAbort_wb & TxAbort_wb_q)
TxAbortPacketBlocked <=#Tp 1'b0;
else
if(TxAbortPacket)
TxAbortPacketBlocked <=#Tp 1'b1;
end
reg TxRetryPacketBlocked;
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
TxRetryPacket <=#Tp 1'b0;
else
if(TxRetry_wb & !tx_burst_en & MasterWbTX & MasterAccessFinished & !TxRetryPacketBlocked |
TxRetry_wb & !MasterWbTX & !TxRetryPacketBlocked)
TxRetryPacket <=#Tp 1'b1;
else
TxRetryPacket <=#Tp 1'b0;
end
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
TxRetryPacket_NotCleared <=#Tp 1'b0;
else
if(StartTxBDRead)
TxRetryPacket_NotCleared <=#Tp 1'b0;
else
if(TxRetry_wb & !tx_burst_en & MasterWbTX & MasterAccessFinished & !TxRetryPacketBlocked |
TxRetry_wb & !MasterWbTX & !TxRetryPacketBlocked)
TxRetryPacket_NotCleared <=#Tp 1'b1;
end
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
TxRetryPacketBlocked <=#Tp 1'b0;
else
if(!TxRetry_wb & TxRetry_wb_q)
TxRetryPacketBlocked <=#Tp 1'b0;
else
if(TxRetryPacket)
TxRetryPacketBlocked <=#Tp 1'b1;
end
reg TxDonePacketBlocked;
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
TxDonePacket <=#Tp 1'b0;
else
if(TxDone_wb & !tx_burst_en & MasterWbTX & MasterAccessFinished & !TxDonePacketBlocked |
TxDone_wb & !MasterWbTX & !TxDonePacketBlocked)
TxDonePacket <=#Tp 1'b1;
else
TxDonePacket <=#Tp 1'b0;
end
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
TxDonePacket_NotCleared <=#Tp 1'b0;
else
if(TxEn & TxEn_q & TxDonePacket_NotCleared)
TxDonePacket_NotCleared <=#Tp 1'b0;
else
if(TxDone_wb & !tx_burst_en & MasterWbTX & MasterAccessFinished & (~TxDonePacketBlocked) |
TxDone_wb & !MasterWbTX & (~TxDonePacketBlocked))
TxDonePacket_NotCleared <=#Tp 1'b1;
end
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
TxDonePacketBlocked <=#Tp 1'b0;
else
if(!TxDone_wb & TxDone_wb_q)
TxDonePacketBlocked <=#Tp 1'b0;
else
if(TxDonePacket)
TxDonePacketBlocked <=#Tp 1'b1;
end
// Indication of the last word
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
LastWord <=#Tp 1'b0;
else
if((TxEndFrm | TxAbort | TxRetry) & Flop)
LastWord <=#Tp 1'b0;
else
if(TxUsedData & Flop & TxByteCnt == 2'h3)
LastWord <=#Tp TxEndFrm_wb;
end
// Tx end frame generation
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
TxEndFrm <=#Tp 1'b0;
else
if(Flop & TxEndFrm | TxAbort | TxRetry_q)
TxEndFrm <=#Tp 1'b0;
else
if(Flop & LastWord)
begin
case (TxValidBytesLatched) // synopsys parallel_case
1 : TxEndFrm <=#Tp TxByteCnt == 2'h0;
2 : TxEndFrm <=#Tp TxByteCnt == 2'h1;
3 : TxEndFrm <=#Tp TxByteCnt == 2'h2;
0 : TxEndFrm <=#Tp TxByteCnt == 2'h3;
default : TxEndFrm <=#Tp 1'b0;
endcase
end
end
// Tx data selection (latching)
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
TxData <=#Tp 0;
else
if(TxStartFrm_sync2 & ~TxStartFrm)
case(TxPointerLSB) // synopsys parallel_case
2'h0 : TxData <=#Tp TxData_wb[31:24]; // Big Endian Byte Ordering
2'h1 : TxData <=#Tp TxData_wb[23:16]; // Big Endian Byte Ordering
2'h2 : TxData <=#Tp TxData_wb[15:08]; // Big Endian Byte Ordering
2'h3 : TxData <=#Tp TxData_wb[07:00]; // Big Endian Byte Ordering
endcase
else
if(TxStartFrm & TxUsedData & TxPointerLSB==2'h3)
TxData <=#Tp TxData_wb[31:24]; // Big Endian Byte Ordering
else
if(TxUsedData & Flop)
begin
case(TxByteCnt) // synopsys parallel_case
0 : TxData <=#Tp TxDataLatched[31:24]; // Big Endian Byte Ordering
1 : TxData <=#Tp TxDataLatched[23:16];
2 : TxData <=#Tp TxDataLatched[15:8];
3 : TxData <=#Tp TxDataLatched[7:0];
endcase
end
end
// Latching tx data
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
TxDataLatched[31:0] <=#Tp 32'h0;
else
if(TxStartFrm_sync2 & ~TxStartFrm | TxUsedData & Flop & TxByteCnt == 2'h3 | TxStartFrm & TxUsedData & Flop & TxByteCnt == 2'h0)
TxDataLatched[31:0] <=#Tp TxData_wb[31:0];
end
// Tx under run
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
TxUnderRun_wb <=#Tp 1'b0;
else
if(TxAbortPulse)
TxUnderRun_wb <=#Tp 1'b0;
else
if(TxBufferEmpty & ReadTxDataFromFifo_wb)
TxUnderRun_wb <=#Tp 1'b1;
end
reg TxUnderRun_sync1;
// Tx under run
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
TxUnderRun_sync1 <=#Tp 1'b0;
else
if(TxUnderRun_wb)
TxUnderRun_sync1 <=#Tp 1'b1;
else
if(BlockingTxStatusWrite_sync2)
TxUnderRun_sync1 <=#Tp 1'b0;
end
// Tx under run
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
TxUnderRun <=#Tp 1'b0;
else
if(BlockingTxStatusWrite_sync2)
TxUnderRun <=#Tp 1'b0;
else
if(TxUnderRun_sync1)
TxUnderRun <=#Tp 1'b1;
end
// Tx Byte counter
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
TxByteCnt <=#Tp 2'h0;
else
if(TxAbort_q | TxRetry_q)
TxByteCnt <=#Tp 2'h0;
else
if(TxStartFrm & ~TxUsedData)
case(TxPointerLSB) // synopsys parallel_case
2'h0 : TxByteCnt <=#Tp 2'h1;
2'h1 : TxByteCnt <=#Tp 2'h2;
2'h2 : TxByteCnt <=#Tp 2'h3;
2'h3 : TxByteCnt <=#Tp 2'h0;
endcase
else
if(TxUsedData & Flop)
TxByteCnt <=#Tp TxByteCnt + 1'b1;
end
// Start: Generation of the ReadTxDataFromFifo_tck signal and synchronization to the WB_CLK_I
reg ReadTxDataFromFifo_sync1;
reg ReadTxDataFromFifo_sync2;
reg ReadTxDataFromFifo_sync3;
reg ReadTxDataFromFifo_syncb1;
reg ReadTxDataFromFifo_syncb2;
reg ReadTxDataFromFifo_syncb3;
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
ReadTxDataFromFifo_tck <=#Tp 1'b0;
else
if(TxStartFrm_sync2 & ~TxStartFrm | TxUsedData & Flop & TxByteCnt == 2'h3 & ~LastWord | TxStartFrm & TxUsedData & Flop & TxByteCnt == 2'h0)
ReadTxDataFromFifo_tck <=#Tp 1'b1;
else
if(ReadTxDataFromFifo_syncb2 & ~ReadTxDataFromFifo_syncb3)
ReadTxDataFromFifo_tck <=#Tp 1'b0;
end
// Synchronizing TxStartFrm_wb to MTxClk
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
ReadTxDataFromFifo_sync1 <=#Tp 1'b0;
else
ReadTxDataFromFifo_sync1 <=#Tp ReadTxDataFromFifo_tck;
end
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
ReadTxDataFromFifo_sync2 <=#Tp 1'b0;
else
ReadTxDataFromFifo_sync2 <=#Tp ReadTxDataFromFifo_sync1;
end
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
ReadTxDataFromFifo_syncb1 <=#Tp 1'b0;
else
ReadTxDataFromFifo_syncb1 <=#Tp ReadTxDataFromFifo_sync2;
end
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
ReadTxDataFromFifo_syncb2 <=#Tp 1'b0;
else
ReadTxDataFromFifo_syncb2 <=#Tp ReadTxDataFromFifo_syncb1;
end
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
ReadTxDataFromFifo_syncb3 <=#Tp 1'b0;
else
ReadTxDataFromFifo_syncb3 <=#Tp ReadTxDataFromFifo_syncb2;
end
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
ReadTxDataFromFifo_sync3 <=#Tp 1'b0;
else
ReadTxDataFromFifo_sync3 <=#Tp ReadTxDataFromFifo_sync2;
end
assign ReadTxDataFromFifo_wb = ReadTxDataFromFifo_sync2 & ~ReadTxDataFromFifo_sync3;
// End: Generation of the ReadTxDataFromFifo_tck signal and synchronization to the WB_CLK_I
// Synchronizing TxRetry signal (synchronized to WISHBONE clock)
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
TxRetrySync1 <=#Tp 1'b0;
else
TxRetrySync1 <=#Tp TxRetry;
end
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
TxRetry_wb <=#Tp 1'b0;
else
TxRetry_wb <=#Tp TxRetrySync1;
end
// Synchronized TxDone_wb signal (synchronized to WISHBONE clock)
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
TxDoneSync1 <=#Tp 1'b0;
else
TxDoneSync1 <=#Tp TxDone;
end
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
TxDone_wb <=#Tp 1'b0;
else
TxDone_wb <=#Tp TxDoneSync1;
end
// Synchronizing TxAbort signal (synchronized to WISHBONE clock)
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
TxAbortSync1 <=#Tp 1'b0;
else
TxAbortSync1 <=#Tp TxAbort;
end
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
TxAbort_wb <=#Tp 1'b0;
else
TxAbort_wb <=#Tp TxAbortSync1;
end
reg RxAbortSync1;
reg RxAbortSync2;
reg RxAbortSync3;
reg RxAbortSync4;
reg RxAbortSyncb1;
reg RxAbortSyncb2;
assign StartRxBDRead = RxStatusWrite | RxAbortSync3 & ~RxAbortSync4;
// Reading the Rx buffer descriptor
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
RxBDRead <=#Tp 1'b1;
else
if(StartRxBDRead & ~RxReady)
RxBDRead <=#Tp 1'b1;
else
if(RxBDReady)
RxBDRead <=#Tp 1'b0;
end
// Reading of the next receive buffer descriptor starts after reception status is
// written to the previous one.
// Latching READY status of the Rx buffer descriptor
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
RxBDReady <=#Tp 1'b0;
else
if(RxPointerRead)
RxBDReady <=#Tp 1'b0;
else
if(RxEn & RxEn_q & RxBDRead)
RxBDReady <=#Tp ram_do[15]; // RxBDReady is sampled only once at the beginning
end
// Latching Rx buffer descriptor status
// Data is avaliable one cycle after the access is started (at that time signal RxEn is not active)
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
RxStatus <=#Tp 2'h0;
else
if(RxEn & RxEn_q & RxBDRead)
RxStatus <=#Tp ram_do[14:13];
end
// RxReady generation
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
RxReady <=#Tp 1'b0;
else
if(ShiftEnded | RxAbortSync2 & ~RxAbortSync3)
RxReady <=#Tp 1'b0;
else
if(RxEn & RxEn_q & RxPointerRead)
RxReady <=#Tp 1'b1;
end
// Reading Rx BD pointer
assign StartRxPointerRead = RxBDRead & RxBDReady;
// Reading Tx BD Pointer
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
RxPointerRead <=#Tp 1'b0;
else
if(StartRxPointerRead)
RxPointerRead <=#Tp 1'b1;
else
if(RxEn & RxEn_q)
RxPointerRead <=#Tp 1'b0;
end
//Latching Rx buffer pointer from buffer descriptor;
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
RxPointerMSB <=#Tp 30'h0;
else
if(RxEn & RxEn_q & RxPointerRead)
RxPointerMSB <=#Tp ram_do[31:2];
else
if(MasterWbRX & m_wb_ack_i)
RxPointerMSB <=#Tp RxPointerMSB + 1; // Word access (always word access. m_wb_sel_o are used for selecting bytes)
end
//Latching last addresses from buffer descriptor (used as byte-half-word indicator);
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
RxPointerLSB_rst[1:0] <=#Tp 0;
else
if(MasterWbRX & m_wb_ack_i) // After first write all RxByteSel are active
RxPointerLSB_rst[1:0] <=#Tp 0;
else
if(RxEn & RxEn_q & RxPointerRead)
RxPointerLSB_rst[1:0] <=#Tp ram_do[1:0];
end
always @ (RxPointerLSB_rst)
begin
case(RxPointerLSB_rst[1:0]) // synopsys parallel_case
2'h0 : RxByteSel[3:0] = 4'hf;
2'h1 : RxByteSel[3:0] = 4'h7;
2'h2 : RxByteSel[3:0] = 4'h3;
2'h3 : RxByteSel[3:0] = 4'h1;
endcase
end
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
RxEn_needed <=#Tp 1'b0;
else
if(~RxReady & r_RxEn & WbEn & ~WbEn_q)
RxEn_needed <=#Tp 1'b1;
else
if(RxPointerRead & RxEn & RxEn_q)
RxEn_needed <=#Tp 1'b0;
end
// Reception status is written back to the buffer descriptor after the end of frame is detected.
assign RxStatusWrite = ShiftEnded & RxEn & RxEn_q;
reg RxEnableWindow;
// Indicating that last byte is being reveived
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
LastByteIn <=#Tp 1'b0;
else
if(ShiftWillEnd & (&RxByteCnt) | RxAbort)
LastByteIn <=#Tp 1'b0;
else
if(RxValid & RxReady & RxEndFrm & ~(&RxByteCnt) & RxEnableWindow)
LastByteIn <=#Tp 1'b1;
end
reg ShiftEnded_rck;
reg ShiftEndedSync1;
reg ShiftEndedSync2;
reg ShiftEndedSync3;
reg ShiftEndedSync_c1;
reg ShiftEndedSync_c2;
wire StartShiftWillEnd;
assign StartShiftWillEnd = LastByteIn | RxValid & RxEndFrm & (&RxByteCnt) & RxEnableWindow;
// Indicating that data reception will end
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
ShiftWillEnd <=#Tp 1'b0;
else
if(ShiftEnded_rck | RxAbort)
ShiftWillEnd <=#Tp 1'b0;
else
if(StartShiftWillEnd)
ShiftWillEnd <=#Tp 1'b1;
end
// Receive byte counter
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
RxByteCnt <=#Tp 2'h0;
else
if(ShiftEnded_rck | RxAbort)
RxByteCnt <=#Tp 2'h0;
else
if(RxValid & RxStartFrm & RxReady)
case(RxPointerLSB_rst) // synopsys parallel_case
2'h0 : RxByteCnt <=#Tp 2'h1;
2'h1 : RxByteCnt <=#Tp 2'h2;
2'h2 : RxByteCnt <=#Tp 2'h3;
2'h3 : RxByteCnt <=#Tp 2'h0;
endcase
else
if(RxValid & RxEnableWindow & RxReady | LastByteIn)
RxByteCnt <=#Tp RxByteCnt + 1'b1;
end
// Indicates how many bytes are valid within the last word
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
RxValidBytes <=#Tp 2'h1;
else
if(RxValid & RxStartFrm)
case(RxPointerLSB_rst) // synopsys parallel_case
2'h0 : RxValidBytes <=#Tp 2'h1;
2'h1 : RxValidBytes <=#Tp 2'h2;
2'h2 : RxValidBytes <=#Tp 2'h3;
2'h3 : RxValidBytes <=#Tp 2'h0;
endcase
else
if(RxValid & ~LastByteIn & ~RxStartFrm & RxEnableWindow)
RxValidBytes <=#Tp RxValidBytes + 1;
end
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
RxDataLatched1 <=#Tp 24'h0;
else
if(RxValid & RxReady & ~LastByteIn)
if(RxStartFrm)
begin
case(RxPointerLSB_rst) // synopsys parallel_case
2'h0: RxDataLatched1[31:24] <=#Tp RxData; // Big Endian Byte Ordering
2'h1: RxDataLatched1[23:16] <=#Tp RxData;
2'h2: RxDataLatched1[15:8] <=#Tp RxData;
2'h3: RxDataLatched1 <=#Tp RxDataLatched1;
endcase
end
else if (RxEnableWindow)
begin
case(RxByteCnt) // synopsys parallel_case
2'h0: RxDataLatched1[31:24] <=#Tp RxData; // Big Endian Byte Ordering
2'h1: RxDataLatched1[23:16] <=#Tp RxData;
2'h2: RxDataLatched1[15:8] <=#Tp RxData;
2'h3: RxDataLatched1 <=#Tp RxDataLatched1;
endcase
end
end
wire SetWriteRxDataToFifo;
// Assembling data that will be written to the rx_fifo
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
RxDataLatched2 <=#Tp 32'h0;
else
if(SetWriteRxDataToFifo & ~ShiftWillEnd)
RxDataLatched2 <=#Tp {RxDataLatched1[31:8], RxData}; // Big Endian Byte Ordering
else
if(SetWriteRxDataToFifo & ShiftWillEnd)
case(RxValidBytes) // synopsys parallel_case
0 : RxDataLatched2 <=#Tp {RxDataLatched1[31:8], RxData}; // Big Endian Byte Ordering
1 : RxDataLatched2 <=#Tp {RxDataLatched1[31:24], 24'h0};
2 : RxDataLatched2 <=#Tp {RxDataLatched1[31:16], 16'h0};
3 : RxDataLatched2 <=#Tp {RxDataLatched1[31:8], 8'h0};
endcase
end
reg WriteRxDataToFifoSync1;
reg WriteRxDataToFifoSync2;
reg WriteRxDataToFifoSync3;
// Indicating start of the reception process
assign SetWriteRxDataToFifo = (RxValid & RxReady & ~RxStartFrm & RxEnableWindow & (&RxByteCnt)) |
(RxValid & RxReady & RxStartFrm & (&RxPointerLSB_rst)) |
(ShiftWillEnd & LastByteIn & (&RxByteCnt));
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
WriteRxDataToFifo <=#Tp 1'b0;
else
if(SetWriteRxDataToFifo & ~RxAbort)
WriteRxDataToFifo <=#Tp 1'b1;
else
if(WriteRxDataToFifoSync2 | RxAbort)
WriteRxDataToFifo <=#Tp 1'b0;
end
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
WriteRxDataToFifoSync1 <=#Tp 1'b0;
else
if(WriteRxDataToFifo)
WriteRxDataToFifoSync1 <=#Tp 1'b1;
else
WriteRxDataToFifoSync1 <=#Tp 1'b0;
end
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
WriteRxDataToFifoSync2 <=#Tp 1'b0;
else
WriteRxDataToFifoSync2 <=#Tp WriteRxDataToFifoSync1;
end
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
WriteRxDataToFifoSync3 <=#Tp 1'b0;
else
WriteRxDataToFifoSync3 <=#Tp WriteRxDataToFifoSync2;
end
wire WriteRxDataToFifo_wb;
assign WriteRxDataToFifo_wb = WriteRxDataToFifoSync2 & ~WriteRxDataToFifoSync3;
reg LatchedRxStartFrm;
reg SyncRxStartFrm;
reg SyncRxStartFrm_q;
reg SyncRxStartFrm_q2;
wire RxFifoReset;
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
LatchedRxStartFrm <=#Tp 0;
else
if(RxStartFrm & ~SyncRxStartFrm_q)
LatchedRxStartFrm <=#Tp 1;
else
if(SyncRxStartFrm_q)
LatchedRxStartFrm <=#Tp 0;
end
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
SyncRxStartFrm <=#Tp 0;
else
if(LatchedRxStartFrm)
SyncRxStartFrm <=#Tp 1;
else
SyncRxStartFrm <=#Tp 0;
end
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
SyncRxStartFrm_q <=#Tp 0;
else
SyncRxStartFrm_q <=#Tp SyncRxStartFrm;
end
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
SyncRxStartFrm_q2 <=#Tp 0;
else
SyncRxStartFrm_q2 <=#Tp SyncRxStartFrm_q;
end
assign RxFifoReset = SyncRxStartFrm_q & ~SyncRxStartFrm_q2;
eth_fifo #(`ETH_RX_FIFO_DATA_WIDTH, `ETH_RX_FIFO_DEPTH, `ETH_RX_FIFO_CNT_WIDTH)
rx_fifo (.data_in(RxDataLatched2), .data_out(m_wb_dat_o),
.clk(WB_CLK_I), .reset(Reset),
.write(WriteRxDataToFifo_wb & ~RxBufferFull), .read(MasterWbRX & m_wb_ack_i),
.clear(RxFifoReset), .full(RxBufferFull),
.almost_full(), .almost_empty(RxBufferAlmostEmpty),
.empty(RxBufferEmpty), .cnt(rxfifo_cnt)
);
assign enough_data_in_rxfifo_for_burst = rxfifo_cnt>=`ETH_BURST_LENGTH;
assign enough_data_in_rxfifo_for_burst_plus1 = rxfifo_cnt>`ETH_BURST_LENGTH;
assign WriteRxDataToMemory = ~RxBufferEmpty;
assign rx_burst = rx_burst_en & WriteRxDataToMemory;
// Generation of the end-of-frame signal
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
ShiftEnded_rck <=#Tp 1'b0;
else
if(~RxAbort & SetWriteRxDataToFifo & StartShiftWillEnd)
ShiftEnded_rck <=#Tp 1'b1;
else
if(RxAbort | ShiftEndedSync_c1 & ShiftEndedSync_c2)
ShiftEnded_rck <=#Tp 1'b0;
end
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
ShiftEndedSync1 <=#Tp 1'b0;
else
ShiftEndedSync1 <=#Tp ShiftEnded_rck;
end
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
ShiftEndedSync2 <=#Tp 1'b0;
else
ShiftEndedSync2 <=#Tp ShiftEndedSync1;
end
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
ShiftEndedSync3 <=#Tp 1'b0;
else
if(ShiftEndedSync1 & ~ShiftEndedSync2)
ShiftEndedSync3 <=#Tp 1'b1;
else
if(ShiftEnded)
ShiftEndedSync3 <=#Tp 1'b0;
end
// Generation of the end-of-frame signal
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
ShiftEnded <=#Tp 1'b0;
else
if(ShiftEndedSync3 & MasterWbRX & m_wb_ack_i & RxBufferAlmostEmpty & ~ShiftEnded)
ShiftEnded <=#Tp 1'b1;
else
if(RxStatusWrite)
ShiftEnded <=#Tp 1'b0;
end
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
ShiftEndedSync_c1 <=#Tp 1'b0;
else
ShiftEndedSync_c1 <=#Tp ShiftEndedSync2;
end
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
ShiftEndedSync_c2 <=#Tp 1'b0;
else
ShiftEndedSync_c2 <=#Tp ShiftEndedSync_c1;
end
// Generation of the end-of-frame signal
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
RxEnableWindow <=#Tp 1'b0;
else
if(RxStartFrm)
RxEnableWindow <=#Tp 1'b1;
else
if(RxEndFrm | RxAbort)
RxEnableWindow <=#Tp 1'b0;
end
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
RxAbortSync1 <=#Tp 1'b0;
else
RxAbortSync1 <=#Tp RxAbortLatched;
end
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
RxAbortSync2 <=#Tp 1'b0;
else
RxAbortSync2 <=#Tp RxAbortSync1;
end
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
RxAbortSync3 <=#Tp 1'b0;
else
RxAbortSync3 <=#Tp RxAbortSync2;
end
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
RxAbortSync4 <=#Tp 1'b0;
else
RxAbortSync4 <=#Tp RxAbortSync3;
end
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
RxAbortSyncb1 <=#Tp 1'b0;
else
RxAbortSyncb1 <=#Tp RxAbortSync2;
end
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
RxAbortSyncb2 <=#Tp 1'b0;
else
RxAbortSyncb2 <=#Tp RxAbortSyncb1;
end
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
RxAbortLatched <=#Tp 1'b0;
else
if(RxAbortSyncb2)
RxAbortLatched <=#Tp 1'b0;
else
if(RxAbort)
RxAbortLatched <=#Tp 1'b1;
end
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
LatchedRxLength[15:0] <=#Tp 16'h0;
else
if(LoadRxStatus)
LatchedRxLength[15:0] <=#Tp RxLength[15:0];
end
assign RxStatusIn = {ReceivedPauseFrm, AddressMiss, RxOverrun, InvalidSymbol, DribbleNibble, ReceivedPacketTooBig, ShortFrame, LatchedCrcError, RxLateCollision};
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
RxStatusInLatched <=#Tp 'h0;
else
if(LoadRxStatus)
RxStatusInLatched <=#Tp RxStatusIn;
end
// Rx overrun
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
RxOverrun <=#Tp 1'b0;
else
if(RxStatusWrite)
RxOverrun <=#Tp 1'b0;
else
if(RxBufferFull & WriteRxDataToFifo_wb)
RxOverrun <=#Tp 1'b1;
end
wire TxError;
assign TxError = TxUnderRun | RetryLimit | LateCollLatched | CarrierSenseLost;
wire RxError;
// ShortFrame (RxStatusInLatched[2]) can not set an error because short frames
// are aborted when signal r_RecSmall is set to 0 in MODER register.
// AddressMiss is identifying that a frame was received because of the promiscous
// mode and is not an error
assign RxError = (|RxStatusInLatched[6:3]) | (|RxStatusInLatched[1:0]);
reg RxStatusWriteLatched;
reg RxStatusWriteLatched_sync1;
reg RxStatusWriteLatched_sync2;
reg RxStatusWriteLatched_syncb1;
reg RxStatusWriteLatched_syncb2;
// Latching and synchronizing RxStatusWrite signal. This signal is used for clearing the ReceivedPauseFrm signal
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
RxStatusWriteLatched <=#Tp 1'b0;
else
if(RxStatusWriteLatched_syncb2)
RxStatusWriteLatched <=#Tp 1'b0;
else
if(RxStatusWrite)
RxStatusWriteLatched <=#Tp 1'b1;
end
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
begin
RxStatusWriteLatched_sync1 <=#Tp 1'b0;
RxStatusWriteLatched_sync2 <=#Tp 1'b0;
end
else
begin
RxStatusWriteLatched_sync1 <=#Tp RxStatusWriteLatched;
RxStatusWriteLatched_sync2 <=#Tp RxStatusWriteLatched_sync1;
end
end
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
begin
RxStatusWriteLatched_syncb1 <=#Tp 1'b0;
RxStatusWriteLatched_syncb2 <=#Tp 1'b0;
end
else
begin
RxStatusWriteLatched_syncb1 <=#Tp RxStatusWriteLatched_sync2;
RxStatusWriteLatched_syncb2 <=#Tp RxStatusWriteLatched_syncb1;
end
end
// Tx Done Interrupt
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
TxB_IRQ <=#Tp 1'b0;
else
if(TxStatusWrite & TxIRQEn)
TxB_IRQ <=#Tp ~TxError;
else
TxB_IRQ <=#Tp 1'b0;
end
// Tx Error Interrupt
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
TxE_IRQ <=#Tp 1'b0;
else
if(TxStatusWrite & TxIRQEn)
TxE_IRQ <=#Tp TxError;
else
TxE_IRQ <=#Tp 1'b0;
end
// Rx Done Interrupt
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
RxB_IRQ <=#Tp 1'b0;
else
if(RxStatusWrite & RxIRQEn & ReceivedPacketGood & (~ReceivedPauseFrm | ReceivedPauseFrm & r_PassAll & (~r_RxFlow)))
RxB_IRQ <=#Tp (~RxError);
else
RxB_IRQ <=#Tp 1'b0;
end
// Rx Error Interrupt
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
RxE_IRQ <=#Tp 1'b0;
else
if(RxStatusWrite & RxIRQEn & (~ReceivedPauseFrm | ReceivedPauseFrm & r_PassAll & (~r_RxFlow)))
RxE_IRQ <=#Tp RxError;
else
RxE_IRQ <=#Tp 1'b0;
end
// Busy Interrupt
reg Busy_IRQ_rck;
reg Busy_IRQ_sync1;
reg Busy_IRQ_sync2;
reg Busy_IRQ_sync3;
reg Busy_IRQ_syncb1;
reg Busy_IRQ_syncb2;
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
Busy_IRQ_rck <=#Tp 1'b0;
else
if(RxValid & RxStartFrm & ~RxReady)
Busy_IRQ_rck <=#Tp 1'b1;
else
if(Busy_IRQ_syncb2)
Busy_IRQ_rck <=#Tp 1'b0;
end
always @ (posedge WB_CLK_I)
begin
Busy_IRQ_sync1 <=#Tp Busy_IRQ_rck;
Busy_IRQ_sync2 <=#Tp Busy_IRQ_sync1;
Busy_IRQ_sync3 <=#Tp Busy_IRQ_sync2;
end
always @ (posedge MRxClk)
begin
Busy_IRQ_syncb1 <=#Tp Busy_IRQ_sync2;
Busy_IRQ_syncb2 <=#Tp Busy_IRQ_syncb1;
end
assign Busy_IRQ = Busy_IRQ_sync2 & ~Busy_IRQ_sync3;
endmodule
//////////////////////////////////////////////////////////////////////
//// ////
//// eth_top.v ////
//// ////
//// This file is part of the Ethernet IP core project ////
//// http://www.opencores.org/projects/ethmac/ ////
//// ////
//// Author(s): ////
//// - Igor Mohor ([email protected]) ////
//// ////
//// All additional information is available in the Readme.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001, 2002 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: eth_top.v,v $
// Revision 1.50 2004/04/26 15:26:23 igorm
// - Bug connected to the TX_BD_NUM_Wr signal fixed (bug came in with the
// previous update of the core.
// - TxBDAddress is set to 0 after the TX is enabled in the MODER register.
// - RxBDAddress is set to r_TxBDNum<<1 after the RX is enabled in the MODER
// register. (thanks to Mathias and Torbjorn)
// - Multicast reception was fixed. Thanks to Ulrich Gries
//
// Revision 1.49 2003/11/12 18:24:59 tadejm
// WISHBONE slave changed and tested from only 32-bit accesss to byte access.
//
// Revision 1.48 2003/10/17 07:46:16 markom
// mbist signals updated according to newest convention
//
// Revision 1.47 2003/10/06 15:43:45 knguyen
// Update RxEnSync only when mrxdv_pad_i is inactive (LOW).
//
// Revision 1.46 2003/01/30 13:30:22 tadejm
// Defer indication changed.
//
// Revision 1.45 2003/01/22 13:49:26 tadejm
// When control packets were received, they were ignored in some cases.
//
// Revision 1.44 2003/01/21 12:09:40 mohor
// When receiving normal data frame and RxFlow control was switched on, RXB
// interrupt was not set.
//
// Revision 1.43 2002/11/22 01:57:06 mohor
// Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort
// synchronized.
//
// Revision 1.42 2002/11/21 00:09:19 mohor
// TPauseRq synchronized to tx_clk.
//
// Revision 1.41 2002/11/19 18:13:49 mohor
// r_MiiMRst is not used for resetting the MIIM module. wb_rst used instead.
//
// Revision 1.40 2002/11/19 17:34:25 mohor
// AddressMiss status is connecting to the Rx BD. AddressMiss is identifying
// that a frame was received because of the promiscous mode.
//
// Revision 1.39 2002/11/18 17:31:55 mohor
// wb_rst_i is used for MIIM reset.
//
// Revision 1.38 2002/11/14 18:37:20 mohor
// r_Rst signal does not reset any module any more and is removed from the design.
//
// Revision 1.37 2002/11/13 22:25:36 tadejm
// All modules are reset with wb_rst instead of the r_Rst. Exception is MII module.
//
// Revision 1.36 2002/10/18 17:04:20 tadejm
// Changed BIST scan signals.
//
// Revision 1.35 2002/10/11 13:36:58 mohor
// Typo error fixed. (When using Bist)
//
// Revision 1.34 2002/10/10 16:49:50 mohor
// Signals for WISHBONE B3 compliant interface added.
//
// Revision 1.33 2002/10/10 16:29:30 mohor
// BIST added.
//
// Revision 1.32 2002/09/20 17:12:58 mohor
// CsMiss added. When address between 0x800 and 0xfff is accessed within
// Ethernet Core, error acknowledge is generated.
//
// Revision 1.31 2002/09/12 14:50:17 mohor
// CarrierSenseLost bug fixed when operating in full duplex mode.
//
// Revision 1.30 2002/09/10 10:35:23 mohor
// Ethernet debug registers removed.
//
// Revision 1.29 2002/09/09 13:03:13 mohor
// Error acknowledge is generated when accessing BDs and RST bit in the
// MODER register (r_Rst) is set.
//
// Revision 1.28 2002/09/04 18:44:10 mohor
// Signals related to the control frames connected. Debug registers reg1, 2, 3, 4
// connected.
//
// Revision 1.27 2002/07/25 18:15:37 mohor
// RxAbort changed. Packets received with MRxErr (from PHY) are also
// aborted.
//
// Revision 1.26 2002/07/17 18:51:50 mohor
// EXTERNAL_DMA removed. External DMA not supported.
//
// Revision 1.25 2002/05/03 10:15:50 mohor
// Outputs registered. Reset changed for eth_wishbone module.
//
// Revision 1.24 2002/04/22 14:15:42 mohor
// Wishbone signals are registered when ETH_REGISTERED_OUTPUTS is
// selected in eth_defines.v
//
// Revision 1.23 2002/03/25 13:33:53 mohor
// md_padoen_o changed to md_padoe_o. Signal was always active high, just
// name was incorrect.
//
// Revision 1.22 2002/02/26 16:59:54 mohor
// Small fixes for external/internal DMA missmatches.
//
// Revision 1.21 2002/02/26 16:21:00 mohor
// Interrupts changed in the top file
//
// Revision 1.20 2002/02/18 10:40:17 mohor
// Small fixes.
//
// Revision 1.19 2002/02/16 14:03:44 mohor
// Registered trimmed. Unused registers removed.
//
// Revision 1.18 2002/02/16 13:06:33 mohor
// EXTERNAL_DMA used instead of WISHBONE_DMA.
//
// Revision 1.17 2002/02/16 07:15:27 mohor
// Testbench fixed, code simplified, unused signals removed.
//
// Revision 1.16 2002/02/15 13:49:39 mohor
// RxAbort is connected differently.
//
// Revision 1.15 2002/02/15 11:38:26 mohor
// Changes that were lost when updating from 1.11 to 1.14 fixed.
//
// Revision 1.14 2002/02/14 20:19:11 billditt
// Modified for Address Checking,
// addition of eth_addrcheck.v
//
// Revision 1.13 2002/02/12 17:03:03 mohor
// HASH0 and HASH1 registers added. Registers address width was
// changed to 8 bits.
//
// Revision 1.12 2002/02/11 09:18:22 mohor
// Tx status is written back to the BD.
//
// Revision 1.11 2002/02/08 16:21:54 mohor
// Rx status is written back to the BD.
//
// Revision 1.10 2002/02/06 14:10:21 mohor
// non-DMA host interface added. Select the right configutation in eth_defines.
//
// Revision 1.9 2002/01/23 10:28:16 mohor
// Link in the header changed.
//
// Revision 1.8 2001/12/05 15:00:16 mohor
// RX_BD_NUM changed to TX_BD_NUM (holds number of TX descriptors
// instead of the number of RX descriptors).
//
// Revision 1.7 2001/12/05 10:45:59 mohor
// ETH_RX_BD_ADR register deleted. ETH_RX_BD_NUM is used instead.
//
// Revision 1.6 2001/10/19 11:24:29 mohor
// Number of addresses (wb_adr_i) minimized.
//
// Revision 1.5 2001/10/19 08:43:51 mohor
// eth_timescale.v changed to timescale.v This is done because of the
// simulation of the few cores in a one joined project.
//
// Revision 1.4 2001/10/18 12:07:11 mohor
// Status signals changed, Adress decoding changed, interrupt controller
// added.
//
// Revision 1.3 2001/09/24 15:02:56 mohor
// Defines changed (All precede with ETH_). Small changes because some
// tools generate warnings when two operands are together. Synchronization
// between two clocks domains in eth_wishbonedma.v is changed (due to ASIC
// demands).
//
// Revision 1.2 2001/08/15 14:03:59 mohor
// Signal names changed on the top level for easier pad insertion (ASIC).
//
// Revision 1.1 2001/08/06 14:44:29 mohor
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
// Include files fixed to contain no path.
// File names and module names changed ta have a eth_ prologue in the name.
// File eth_timescale.v is used to define timescale
// All pin names on the top module are changed to contain _I, _O or _OE at the end.
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
// and Mdo_OE. The bidirectional signal must be created on the top level. This
// is done due to the ASIC tools.
//
// Revision 1.2 2001/08/02 09:25:31 mohor
// Unconnected signals are now connected.
//
// Revision 1.1 2001/07/30 21:23:42 mohor
// Directory structure changed. Files checked and joind together.
//
//
//
//
module eth_top
(
// WISHBONE common
wb_clk_i, wb_rst_i, wb_dat_i, wb_dat_o,
// WISHBONE slave
wb_adr_i, wb_sel_i, wb_we_i, wb_cyc_i, wb_stb_i, wb_ack_o, wb_err_o,
// WISHBONE master
m_wb_adr_o, m_wb_sel_o, m_wb_we_o,
m_wb_dat_o, m_wb_dat_i, m_wb_cyc_o,
m_wb_stb_o, m_wb_ack_i, m_wb_err_i,
`ifdef ETH_WISHBONE_B3
m_wb_cti_o, m_wb_bte_o,
`endif
//TX
mtx_clk_pad_i, mtxd_pad_o, mtxen_pad_o, mtxerr_pad_o,
//RX
mrx_clk_pad_i, mrxd_pad_i, mrxdv_pad_i, mrxerr_pad_i, mcoll_pad_i, mcrs_pad_i,
// MIIM
mdc_pad_o, md_pad_i, md_pad_o, md_padoe_o,
int_o,
//BDRAM
ram_ce, ram_we, ram_oe, ram_addr, ram_di, ram_do
// Bist
`ifdef ETH_BIST
,
// debug chain signals
mbist_si_i, // bist scan serial in
mbist_so_o, // bist scan serial out
mbist_ctrl_i // bist chain shift control
`endif
);
parameter Tp = 1;
// WISHBONE common
input wb_clk_i; // WISHBONE clock
input wb_rst_i; // WISHBONE reset
input [31:0] wb_dat_i; // WISHBONE data input
output [31:0] wb_dat_o; // WISHBONE data output
output wb_err_o; // WISHBONE error output
// WISHBONE slave
input [11:2] wb_adr_i; // WISHBONE address input
input [3:0] wb_sel_i; // WISHBONE byte select input
input wb_we_i; // WISHBONE write enable input
input wb_cyc_i; // WISHBONE cycle input
input wb_stb_i; // WISHBONE strobe input
output wb_ack_o; // WISHBONE acknowledge output
// WISHBONE master
output [31:0] m_wb_adr_o;
output [3:0] m_wb_sel_o;
output m_wb_we_o;
input [31:0] m_wb_dat_i;
output [31:0] m_wb_dat_o;
output m_wb_cyc_o;
output m_wb_stb_o;
input m_wb_ack_i;
input m_wb_err_i;
`ifdef ETH_WISHBONE_B3
output [2:0] m_wb_cti_o; // Cycle Type Identifier
output [1:0] m_wb_bte_o; // Burst Type Extension
`endif
// Tx
input mtx_clk_pad_i; // Transmit clock (from PHY)
output [3:0] mtxd_pad_o; // Transmit nibble (to PHY)
output mtxen_pad_o; // Transmit enable (to PHY)
output mtxerr_pad_o; // Transmit error (to PHY)
// Rx
input mrx_clk_pad_i; // Receive clock (from PHY)
input [3:0] mrxd_pad_i; // Receive nibble (from PHY)
input mrxdv_pad_i; // Receive data valid (from PHY)
input mrxerr_pad_i; // Receive data error (from PHY)
// Common Tx and Rx
input mcoll_pad_i; // Collision (from PHY)
input mcrs_pad_i; // Carrier sense (from PHY)
// MII Management interface
input md_pad_i; // MII data input (from I/O cell)
output mdc_pad_o; // MII Management data clock (to PHY)
output md_pad_o; // MII data output (to I/O cell)
output md_padoe_o; // MII data output enable (to I/O cell)
output int_o; // Interrupt output
//BDRAM
output ram_ce; // BD RAM Chip Enable
output [3:0] ram_we; // BD RAM Write Enable
output ram_oe; // BD RAM Output Enable
output [7:0] ram_addr; // BD RAM Address
output [31:0] ram_di; // BD RAM Data in
input [31:0] ram_do; // BD RAM Data out
// Bist
`ifdef ETH_BIST
input mbist_si_i; // bist scan serial in
output mbist_so_o; // bist scan serial out
input [`ETH_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i; // bist chain shift control
`endif
wire [7:0] r_ClkDiv;
wire r_MiiNoPre;
wire [15:0] r_CtrlData;
wire [4:0] r_FIAD;
wire [4:0] r_RGAD;
wire r_WCtrlData;
wire r_RStat;
wire r_ScanStat;
wire NValid_stat;
wire Busy_stat;
wire LinkFail;
wire [15:0] Prsd; // Read Status Data (data read from the PHY)
wire WCtrlDataStart;
wire RStatStart;
wire UpdateMIIRX_DATAReg;
wire TxStartFrm;
wire TxEndFrm;
wire TxUsedData;
wire [7:0] TxData;
wire TxRetry;
wire TxAbort;
wire TxUnderRun;
wire TxDone;
wire [5:0] CollValid;
reg WillSendControlFrame_sync1;
reg WillSendControlFrame_sync2;
reg WillSendControlFrame_sync3;
reg RstTxPauseRq;
reg TxPauseRq_sync1;
reg TxPauseRq_sync2;
reg TxPauseRq_sync3;
reg TPauseRq;
// Connecting Miim module
eth_miim miim1
(
.Clk(wb_clk_i), .Reset(wb_rst_i), .Divider(r_ClkDiv),
.NoPre(r_MiiNoPre), .CtrlData(r_CtrlData), .Rgad(r_RGAD),
.Fiad(r_FIAD), .WCtrlData(r_WCtrlData), .RStat(r_RStat),
.ScanStat(r_ScanStat), .Mdi(md_pad_i), .Mdo(md_pad_o),
.MdoEn(md_padoe_o), .Mdc(mdc_pad_o), .Busy(Busy_stat),
.Prsd(Prsd), .LinkFail(LinkFail), .Nvalid(NValid_stat),
.WCtrlDataStart(WCtrlDataStart), .RStatStart(RStatStart), .UpdateMIIRX_DATAReg(UpdateMIIRX_DATAReg)
);
wire [3:0] RegCs; // Connected to registers
wire [31:0] RegDataOut; // Multiplexed to wb_dat_o
wire r_RecSmall; // Receive small frames
wire r_LoopBck; // Loopback
wire r_TxEn; // Tx Enable
wire r_RxEn; // Rx Enable
wire MRxDV_Lb; // Muxed MII receive data valid
wire MRxErr_Lb; // Muxed MII Receive Error
wire [3:0] MRxD_Lb; // Muxed MII Receive Data
wire Transmitting; // Indication that TxEthMAC is transmitting
wire r_HugEn; // Huge packet enable
wire r_DlyCrcEn; // Delayed CRC enabled
wire [15:0] r_MaxFL; // Maximum frame length
wire [15:0] r_MinFL; // Minimum frame length
wire ShortFrame;
wire DribbleNibble; // Extra nibble received
wire ReceivedPacketTooBig; // Received packet is too big
wire [47:0] r_MAC; // MAC address
wire LoadRxStatus; // Rx status was loaded
wire [31:0] r_HASH0; // HASH table, lower 4 bytes
wire [31:0] r_HASH1; // HASH table, upper 4 bytes
wire [7:0] r_TxBDNum; // Receive buffer descriptor number
wire [6:0] r_IPGT; //
wire [6:0] r_IPGR1; //
wire [6:0] r_IPGR2; //
wire [5:0] r_CollValid; //
wire [15:0] r_TxPauseTV; // Transmit PAUSE value
wire r_TxPauseRq; // Transmit PAUSE request
wire [3:0] r_MaxRet; //
wire r_NoBckof; //
wire r_ExDfrEn; //
wire r_TxFlow; // Tx flow control enable
wire r_IFG; // Minimum interframe gap for incoming packets
wire TxB_IRQ; // Interrupt Tx Buffer
wire TxE_IRQ; // Interrupt Tx Error
wire RxB_IRQ; // Interrupt Rx Buffer
wire RxE_IRQ; // Interrupt Rx Error
wire Busy_IRQ; // Interrupt Busy (lack of buffers)
//wire DWord;
wire ByteSelected;
wire [3:0] ByteSel;
wire BDAck;
wire [31:0] BD_WB_DAT_O; // wb_dat_o that comes from the Wishbone module (for buffer descriptors read/write)
wire [3:0] BDCs; // Buffer descriptor CS
wire CsMiss; // When access to the address between 0x800 and 0xfff occurs, acknowledge is set
// but data is not valid.
wire temp_wb_ack_o;
wire [31:0] temp_wb_dat_o;
wire temp_wb_err_o;
`ifdef ETH_REGISTERED_OUTPUTS
reg temp_wb_ack_o_reg;
reg [31:0] temp_wb_dat_o_reg;
reg temp_wb_err_o_reg;
`endif
//assign DWord = &wb_sel_i;
assign ByteSelected = |wb_sel_i;
assign RegCs[3] = wb_stb_i & wb_cyc_i & ByteSelected & ~wb_adr_i[11] & ~wb_adr_i[10] & wb_sel_i[3]; // 0x0 - 0x3FF
assign RegCs[2] = wb_stb_i & wb_cyc_i & ByteSelected & ~wb_adr_i[11] & ~wb_adr_i[10] & wb_sel_i[2]; // 0x0 - 0x3FF
assign RegCs[1] = wb_stb_i & wb_cyc_i & ByteSelected & ~wb_adr_i[11] & ~wb_adr_i[10] & wb_sel_i[1]; // 0x0 - 0x3FF
assign RegCs[0] = wb_stb_i & wb_cyc_i & ByteSelected & ~wb_adr_i[11] & ~wb_adr_i[10] & wb_sel_i[0]; // 0x0 - 0x3FF
assign BDCs[3] = wb_stb_i & wb_cyc_i & ByteSelected & ~wb_adr_i[11] & wb_adr_i[10] & wb_sel_i[3]; // 0x400 - 0x7FF
assign BDCs[2] = wb_stb_i & wb_cyc_i & ByteSelected & ~wb_adr_i[11] & wb_adr_i[10] & wb_sel_i[2]; // 0x400 - 0x7FF
assign BDCs[1] = wb_stb_i & wb_cyc_i & ByteSelected & ~wb_adr_i[11] & wb_adr_i[10] & wb_sel_i[1]; // 0x400 - 0x7FF
assign BDCs[0] = wb_stb_i & wb_cyc_i & ByteSelected & ~wb_adr_i[11] & wb_adr_i[10] & wb_sel_i[0]; // 0x400 - 0x7FF
assign CsMiss = wb_stb_i & wb_cyc_i & ByteSelected & wb_adr_i[11]; // 0x800 - 0xfFF
assign temp_wb_ack_o = (|RegCs) | BDAck;
assign temp_wb_dat_o = ((|RegCs) & ~wb_we_i)? RegDataOut : BD_WB_DAT_O;
assign temp_wb_err_o = wb_stb_i & wb_cyc_i & (~ByteSelected | CsMiss);
`ifdef ETH_REGISTERED_OUTPUTS
assign wb_ack_o = temp_wb_ack_o_reg;
assign wb_dat_o[31:0] = temp_wb_dat_o_reg;
assign wb_err_o = temp_wb_err_o_reg;
`else
assign wb_ack_o = temp_wb_ack_o;
assign wb_dat_o[31:0] = temp_wb_dat_o;
assign wb_err_o = temp_wb_err_o;
`endif
`ifdef ETH_REGISTERED_OUTPUTS
always @ (posedge wb_clk_i or posedge wb_rst_i)
begin
if(wb_rst_i)
begin
temp_wb_ack_o_reg <=#Tp 1'b0;
temp_wb_dat_o_reg <=#Tp 32'h0;
temp_wb_err_o_reg <=#Tp 1'b0;
end
else
begin
temp_wb_ack_o_reg <=#Tp temp_wb_ack_o & ~temp_wb_ack_o_reg;
temp_wb_dat_o_reg <=#Tp temp_wb_dat_o;
temp_wb_err_o_reg <=#Tp temp_wb_err_o & ~temp_wb_err_o_reg;
end
end
`endif
// Connecting Ethernet registers
eth_registers ethreg1
(
.DataIn(wb_dat_i), .Address(wb_adr_i[9:2]), .Rw(wb_we_i),
.Cs(RegCs), .Clk(wb_clk_i), .Reset(wb_rst_i),
.DataOut(RegDataOut), .r_RecSmall(r_RecSmall),
.r_Pad(r_Pad), .r_HugEn(r_HugEn), .r_CrcEn(r_CrcEn),
.r_DlyCrcEn(r_DlyCrcEn), .r_FullD(r_FullD),
.r_ExDfrEn(r_ExDfrEn), .r_NoBckof(r_NoBckof), .r_LoopBck(r_LoopBck),
.r_IFG(r_IFG), .r_Pro(r_Pro), .r_Iam(),
.r_Bro(r_Bro), .r_NoPre(r_NoPre), .r_TxEn(r_TxEn),
.r_RxEn(r_RxEn), .Busy_IRQ(Busy_IRQ), .RxE_IRQ(RxE_IRQ),
.RxB_IRQ(RxB_IRQ), .TxE_IRQ(TxE_IRQ), .TxB_IRQ(TxB_IRQ),
.r_IPGT(r_IPGT),
.r_IPGR1(r_IPGR1), .r_IPGR2(r_IPGR2), .r_MinFL(r_MinFL),
.r_MaxFL(r_MaxFL), .r_MaxRet(r_MaxRet), .r_CollValid(r_CollValid),
.r_TxFlow(r_TxFlow), .r_RxFlow(r_RxFlow), .r_PassAll(r_PassAll),
.r_MiiNoPre(r_MiiNoPre), .r_ClkDiv(r_ClkDiv),
.r_WCtrlData(r_WCtrlData), .r_RStat(r_RStat), .r_ScanStat(r_ScanStat),
.r_RGAD(r_RGAD), .r_FIAD(r_FIAD), .r_CtrlData(r_CtrlData),
.NValid_stat(NValid_stat), .Busy_stat(Busy_stat),
.LinkFail(LinkFail), .r_MAC(r_MAC), .WCtrlDataStart(WCtrlDataStart),
.RStatStart(RStatStart), .UpdateMIIRX_DATAReg(UpdateMIIRX_DATAReg), .Prsd(Prsd),
.r_TxBDNum(r_TxBDNum), .int_o(int_o),
.r_HASH0(r_HASH0), .r_HASH1(r_HASH1), .r_TxPauseRq(r_TxPauseRq),
.r_TxPauseTV(r_TxPauseTV), .RstTxPauseRq(RstTxPauseRq), .TxCtrlEndFrm(TxCtrlEndFrm),
.StartTxDone(StartTxDone), .TxClk(mtx_clk_pad_i), .RxClk(mrx_clk_pad_i),
.SetPauseTimer(SetPauseTimer)
);
wire [7:0] RxData;
wire RxValid;
wire RxStartFrm;
wire RxEndFrm;
wire RxAbort;
wire WillTransmit; // Will transmit (to RxEthMAC)
wire ResetCollision; // Reset Collision (for synchronizing collision)
wire [7:0] TxDataOut; // Transmit Packet Data (to TxEthMAC)
wire WillSendControlFrame;
wire ReceiveEnd;
wire ReceivedPacketGood;
wire ReceivedLengthOK;
wire InvalidSymbol;
wire LatchedCrcError;
wire RxLateCollision;
wire [3:0] RetryCntLatched;
wire [3:0] RetryCnt;
wire StartTxAbort;
wire MaxCollisionOccured;
wire RetryLimit;
wire StatePreamble;
wire [1:0] StateData;
// Connecting MACControl
eth_maccontrol maccontrol1
(
.MTxClk(mtx_clk_pad_i), .TPauseRq(TPauseRq),
.TxPauseTV(r_TxPauseTV), .TxDataIn(TxData),
.TxStartFrmIn(TxStartFrm), .TxEndFrmIn(TxEndFrm),
.TxUsedDataIn(TxUsedDataIn), .TxDoneIn(TxDoneIn),
.TxAbortIn(TxAbortIn), .MRxClk(mrx_clk_pad_i),
.RxData(RxData), .RxValid(RxValid),
.RxStartFrm(RxStartFrm), .RxEndFrm(RxEndFrm),
.ReceiveEnd(ReceiveEnd), .ReceivedPacketGood(ReceivedPacketGood),
.TxFlow(r_TxFlow),
.RxFlow(r_RxFlow), .DlyCrcEn(r_DlyCrcEn),
.MAC(r_MAC), .PadIn(r_Pad | PerPacketPad),
.PadOut(PadOut), .CrcEnIn(r_CrcEn | PerPacketCrcEn),
.CrcEnOut(CrcEnOut), .TxReset(wb_rst_i),
.RxReset(wb_rst_i), .ReceivedLengthOK(ReceivedLengthOK),
.TxDataOut(TxDataOut), .TxStartFrmOut(TxStartFrmOut),
.TxEndFrmOut(TxEndFrmOut), .TxUsedDataOut(TxUsedData),
.TxDoneOut(TxDone), .TxAbortOut(TxAbort),
.WillSendControlFrame(WillSendControlFrame), .TxCtrlEndFrm(TxCtrlEndFrm),
.ReceivedPauseFrm(ReceivedPauseFrm), .ControlFrmAddressOK(ControlFrmAddressOK),
.SetPauseTimer(SetPauseTimer),
.RxStatusWriteLatched_sync2(RxStatusWriteLatched_sync2), .r_PassAll(r_PassAll)
);
wire TxCarrierSense; // Synchronized CarrierSense (to Tx clock)
wire Collision; // Synchronized Collision
reg CarrierSense_Tx1;
reg CarrierSense_Tx2;
reg Collision_Tx1;
reg Collision_Tx2;
reg RxEnSync; // Synchronized Receive Enable
//reg CarrierSense_Rx1;
//reg RxCarrierSense; // Synchronized CarrierSense (to Rx clock)
reg WillTransmit_q;
reg WillTransmit_q2;
// Muxed MII receive data valid
assign MRxDV_Lb = r_LoopBck? mtxen_pad_o : mrxdv_pad_i & RxEnSync;
// Muxed MII Receive Error
assign MRxErr_Lb = r_LoopBck? mtxerr_pad_o : mrxerr_pad_i & RxEnSync;
// Muxed MII Receive Data
assign MRxD_Lb[3:0] = r_LoopBck? mtxd_pad_o[3:0] : mrxd_pad_i[3:0];
// Connecting TxEthMAC
eth_txethmac txethmac1
(
.MTxClk(mtx_clk_pad_i), .Reset(wb_rst_i), .CarrierSense(TxCarrierSense),
.Collision(Collision), .TxData(TxDataOut), .TxStartFrm(TxStartFrmOut),
.TxUnderRun(TxUnderRun), .TxEndFrm(TxEndFrmOut), .Pad(PadOut),
.MinFL(r_MinFL), .CrcEn(CrcEnOut), .FullD(r_FullD),
.HugEn(r_HugEn), .DlyCrcEn(r_DlyCrcEn), .IPGT(r_IPGT),
.IPGR1(r_IPGR1), .IPGR2(r_IPGR2), .CollValid(r_CollValid),
.MaxRet(r_MaxRet), .NoBckof(r_NoBckof), .ExDfrEn(r_ExDfrEn),
.MaxFL(r_MaxFL), .MTxEn(mtxen_pad_o), .MTxD(mtxd_pad_o),
.MTxErr(mtxerr_pad_o), .TxUsedData(TxUsedDataIn), .TxDone(TxDoneIn),
.TxRetry(TxRetry), .TxAbort(TxAbortIn), .WillTransmit(WillTransmit),
.ResetCollision(ResetCollision), .RetryCnt(RetryCnt), .StartTxDone(StartTxDone),
.StartTxAbort(StartTxAbort), .MaxCollisionOccured(MaxCollisionOccured), .LateCollision(LateCollision),
.DeferIndication(DeferIndication), .StatePreamble(StatePreamble), .StateData(StateData)
);
wire [15:0] RxByteCnt;
wire RxByteCntEq0;
wire RxByteCntGreat2;
wire RxByteCntMaxFrame;
wire RxCrcError;
wire RxStateIdle;
wire RxStatePreamble;
wire RxStateSFD;
wire [1:0] RxStateData;
wire AddressMiss;
// Connecting RxEthMAC
eth_rxethmac rxethmac1
(
.MRxClk(mrx_clk_pad_i), .MRxDV(MRxDV_Lb), .MRxD(MRxD_Lb),
.Transmitting(Transmitting), .HugEn(r_HugEn), .DlyCrcEn(r_DlyCrcEn),
.MaxFL(r_MaxFL), .r_IFG(r_IFG), .Reset(wb_rst_i),
.RxData(RxData), .RxValid(RxValid), .RxStartFrm(RxStartFrm),
.RxEndFrm(RxEndFrm), .ByteCnt(RxByteCnt),
.ByteCntEq0(RxByteCntEq0), .ByteCntGreat2(RxByteCntGreat2), .ByteCntMaxFrame(RxByteCntMaxFrame),
.CrcError(RxCrcError), .StateIdle(RxStateIdle), .StatePreamble(RxStatePreamble),
.StateSFD(RxStateSFD), .StateData(RxStateData),
.MAC(r_MAC), .r_Pro(r_Pro), .r_Bro(r_Bro),
.r_HASH0(r_HASH0), .r_HASH1(r_HASH1), .RxAbort(RxAbort),
.AddressMiss(AddressMiss), .PassAll(r_PassAll), .ControlFrmAddressOK(ControlFrmAddressOK)
);
// MII Carrier Sense Synchronization
always @ (posedge mtx_clk_pad_i or posedge wb_rst_i)
begin
if(wb_rst_i)
begin
CarrierSense_Tx1 <= #Tp 1'b0;
CarrierSense_Tx2 <= #Tp 1'b0;
end
else
begin
CarrierSense_Tx1 <= #Tp mcrs_pad_i;
CarrierSense_Tx2 <= #Tp CarrierSense_Tx1;
end
end
assign TxCarrierSense = ~r_FullD & CarrierSense_Tx2;
// MII Collision Synchronization
always @ (posedge mtx_clk_pad_i or posedge wb_rst_i)
begin
if(wb_rst_i)
begin
Collision_Tx1 <= #Tp 1'b0;
Collision_Tx2 <= #Tp 1'b0;
end
else
begin
Collision_Tx1 <= #Tp mcoll_pad_i;
if(ResetCollision)
Collision_Tx2 <= #Tp 1'b0;
else
if(Collision_Tx1)
Collision_Tx2 <= #Tp 1'b1;
end
end
// Synchronized Collision
assign Collision = ~r_FullD & Collision_Tx2;
// Carrier sense is synchronized to receive clock.
//always @ (posedge mrx_clk_pad_i or posedge wb_rst_i)
//begin
// if(wb_rst_i)
// begin
// CarrierSense_Rx1 <= #Tp 1'h0;
// RxCarrierSense <= #Tp 1'h0;
// end
// else
// begin
// CarrierSense_Rx1 <= #Tp mcrs_pad_i;
// RxCarrierSense <= #Tp CarrierSense_Rx1;
// end
//end
// Delayed WillTransmit
always @ (posedge mrx_clk_pad_i)
begin
WillTransmit_q <= #Tp WillTransmit;
WillTransmit_q2 <= #Tp WillTransmit_q;
end
assign Transmitting = ~r_FullD & WillTransmit_q2;
// Synchronized Receive Enable
always @ (posedge mrx_clk_pad_i or posedge wb_rst_i)
begin
if(wb_rst_i)
RxEnSync <= #Tp 1'b0;
else
//if(~RxCarrierSense | RxCarrierSense & Transmitting)
if(~mrxdv_pad_i)
RxEnSync <= #Tp r_RxEn;
end
// Synchronizing WillSendControlFrame to WB_CLK;
always @ (posedge wb_clk_i or posedge wb_rst_i)
begin
if(wb_rst_i)
WillSendControlFrame_sync1 <= 1'b0;
else
WillSendControlFrame_sync1 <=#Tp WillSendControlFrame;
end
always @ (posedge wb_clk_i or posedge wb_rst_i)
begin
if(wb_rst_i)
WillSendControlFrame_sync2 <= 1'b0;
else
WillSendControlFrame_sync2 <=#Tp WillSendControlFrame_sync1;
end
always @ (posedge wb_clk_i or posedge wb_rst_i)
begin
if(wb_rst_i)
WillSendControlFrame_sync3 <= 1'b0;
else
WillSendControlFrame_sync3 <=#Tp WillSendControlFrame_sync2;
end
always @ (posedge wb_clk_i or posedge wb_rst_i)
begin
if(wb_rst_i)
RstTxPauseRq <= 1'b0;
else
RstTxPauseRq <=#Tp WillSendControlFrame_sync2 & ~WillSendControlFrame_sync3;
end
// TX Pause request Synchronization
always @ (posedge mtx_clk_pad_i or posedge wb_rst_i)
begin
if(wb_rst_i)
begin
TxPauseRq_sync1 <= #Tp 1'b0;
TxPauseRq_sync2 <= #Tp 1'b0;
TxPauseRq_sync3 <= #Tp 1'b0;
end
else
begin
TxPauseRq_sync1 <= #Tp (r_TxPauseRq & r_TxFlow);
TxPauseRq_sync2 <= #Tp TxPauseRq_sync1;
TxPauseRq_sync3 <= #Tp TxPauseRq_sync2;
end
end
always @ (posedge mtx_clk_pad_i or posedge wb_rst_i)
begin
if(wb_rst_i)
TPauseRq <= #Tp 1'b0;
else
TPauseRq <= #Tp TxPauseRq_sync2 & (~TxPauseRq_sync3);
end
wire LatchedMRxErr;
reg RxAbort_latch;
reg RxAbort_sync1;
reg RxAbort_sync2;
reg RxAbort_wb;
reg RxAbortRst_sync1;
reg RxAbortRst;
// Synchronizing RxAbort to the WISHBONE clock
always @ (posedge mrx_clk_pad_i or posedge wb_rst_i)
begin
if(wb_rst_i)
RxAbort_latch <= #Tp 1'b0;
else if(RxAbort | (ShortFrame & ~r_RecSmall) | LatchedMRxErr & ~InvalidSymbol | (ReceivedPauseFrm & (~r_PassAll)))
RxAbort_latch <= #Tp 1'b1;
else if(RxAbortRst)
RxAbort_latch <= #Tp 1'b0;
end
always @ (posedge wb_clk_i or posedge wb_rst_i)
begin
if(wb_rst_i)
begin
RxAbort_sync1 <= #Tp 1'b0;
RxAbort_wb <= #Tp 1'b0;
RxAbort_wb <= #Tp 1'b0;
end
else
begin
RxAbort_sync1 <= #Tp RxAbort_latch;
RxAbort_wb <= #Tp RxAbort_sync1;
end
end
always @ (posedge mrx_clk_pad_i or posedge wb_rst_i)
begin
if(wb_rst_i)
begin
RxAbortRst_sync1 <= #Tp 1'b0;
RxAbortRst <= #Tp 1'b0;
end
else
begin
RxAbortRst_sync1 <= #Tp RxAbort_wb;
RxAbortRst <= #Tp RxAbortRst_sync1;
end
end
// Connecting Wishbone module
eth_wishbone wishbone
(
.WB_CLK_I(wb_clk_i), .WB_DAT_I(wb_dat_i),
.WB_DAT_O(BD_WB_DAT_O),
// WISHBONE slave
.WB_ADR_I(wb_adr_i[9:2]), .WB_WE_I(wb_we_i),
.BDCs(BDCs), .WB_ACK_O(BDAck),
.Reset(wb_rst_i),
// WISHBONE master
.m_wb_adr_o(m_wb_adr_o), .m_wb_sel_o(m_wb_sel_o), .m_wb_we_o(m_wb_we_o),
.m_wb_dat_i(m_wb_dat_i), .m_wb_dat_o(m_wb_dat_o), .m_wb_cyc_o(m_wb_cyc_o),
.m_wb_stb_o(m_wb_stb_o), .m_wb_ack_i(m_wb_ack_i), .m_wb_err_i(m_wb_err_i),
`ifdef ETH_WISHBONE_B3
.m_wb_cti_o(m_wb_cti_o), .m_wb_bte_o(m_wb_bte_o),
`endif
//TX
.MTxClk(mtx_clk_pad_i), .TxStartFrm(TxStartFrm), .TxEndFrm(TxEndFrm),
.TxUsedData(TxUsedData), .TxData(TxData),
.TxRetry(TxRetry), .TxAbort(TxAbort), .TxUnderRun(TxUnderRun),
.TxDone(TxDone),
.PerPacketCrcEn(PerPacketCrcEn), .PerPacketPad(PerPacketPad),
// Register
.r_TxEn(r_TxEn), .r_RxEn(r_RxEn), .r_TxBDNum(r_TxBDNum),
.r_RxFlow(r_RxFlow), .r_PassAll(r_PassAll),
//RX
.MRxClk(mrx_clk_pad_i), .RxData(RxData), .RxValid(RxValid),
.RxStartFrm(RxStartFrm), .RxEndFrm(RxEndFrm),
.Busy_IRQ(Busy_IRQ), .RxE_IRQ(RxE_IRQ), .RxB_IRQ(RxB_IRQ),
.TxE_IRQ(TxE_IRQ), .TxB_IRQ(TxB_IRQ),
.RxAbort(RxAbort_wb), .RxStatusWriteLatched_sync2(RxStatusWriteLatched_sync2),
.InvalidSymbol(InvalidSymbol), .LatchedCrcError(LatchedCrcError), .RxLength(RxByteCnt),
.RxLateCollision(RxLateCollision), .ShortFrame(ShortFrame), .DribbleNibble(DribbleNibble),
.ReceivedPacketTooBig(ReceivedPacketTooBig), .LoadRxStatus(LoadRxStatus), .RetryCntLatched(RetryCntLatched),
.RetryLimit(RetryLimit), .LateCollLatched(LateCollLatched), .DeferLatched(DeferLatched),
.CarrierSenseLost(CarrierSenseLost),.ReceivedPacketGood(ReceivedPacketGood), .AddressMiss(AddressMiss),
.ReceivedPauseFrm(ReceivedPauseFrm),
.ram_ce(ram_ce), .ram_we(ram_we), .ram_oe(ram_oe),
.ram_addr(ram_addr), .ram_di(ram_di), .ram_do(ram_do)
`ifdef ETH_BIST
,
.mbist_si_i (mbist_si_i),
.mbist_so_o (mbist_so_o),
.mbist_ctrl_i (mbist_ctrl_i)
`endif
);
// Connecting MacStatus module
eth_macstatus macstatus1
(
.MRxClk(mrx_clk_pad_i), .Reset(wb_rst_i),
.ReceiveEnd(ReceiveEnd), .ReceivedPacketGood(ReceivedPacketGood), .ReceivedLengthOK(ReceivedLengthOK),
.RxCrcError(RxCrcError), .MRxErr(MRxErr_Lb), .MRxDV(MRxDV_Lb),
.RxStateSFD(RxStateSFD), .RxStateData(RxStateData), .RxStatePreamble(RxStatePreamble),
.RxStateIdle(RxStateIdle), .Transmitting(Transmitting), .RxByteCnt(RxByteCnt),
.RxByteCntEq0(RxByteCntEq0), .RxByteCntGreat2(RxByteCntGreat2), .RxByteCntMaxFrame(RxByteCntMaxFrame),
.InvalidSymbol(InvalidSymbol),
.MRxD(MRxD_Lb), .LatchedCrcError(LatchedCrcError), .Collision(mcoll_pad_i),
.CollValid(r_CollValid), .RxLateCollision(RxLateCollision), .r_RecSmall(r_RecSmall),
.r_MinFL(r_MinFL), .r_MaxFL(r_MaxFL), .ShortFrame(ShortFrame),
.DribbleNibble(DribbleNibble), .ReceivedPacketTooBig(ReceivedPacketTooBig), .r_HugEn(r_HugEn),
.LoadRxStatus(LoadRxStatus), .RetryCnt(RetryCnt), .StartTxDone(StartTxDone),
.StartTxAbort(StartTxAbort), .RetryCntLatched(RetryCntLatched), .MTxClk(mtx_clk_pad_i),
.MaxCollisionOccured(MaxCollisionOccured), .RetryLimit(RetryLimit), .LateCollision(LateCollision),
.LateCollLatched(LateCollLatched), .DeferIndication(DeferIndication), .DeferLatched(DeferLatched),
.TxStartFrm(TxStartFrmOut), .StatePreamble(StatePreamble), .StateData(StateData),
.CarrierSense(CarrierSense_Tx2), .CarrierSenseLost(CarrierSenseLost), .TxUsedData(TxUsedDataIn),
.LatchedMRxErr(LatchedMRxErr), .Loopback(r_LoopBck), .r_FullD(r_FullD)
);
endmodule
|
// zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz
// File Name : asyn_fifo.v
// Description : asynchronous fifo for clock domain crossing
// Author : Zefu Dai
// -------------------------------------------------------------------------------
// Version :
// -- 2011-02-15 created by Zefu Dai
// fffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff
`include "timescale.v"
module asyn_fifo
#(
parameter DBITWIDTH = 32, // bit width of data
parameter ABITWIDTH = 4, // bit width of address
// parameter DOUT_REG = 1, // optional output register
parameter AF_THRESHOLD = 4, // almost full threshold
parameter AF_WIDTH = 0 // additional almost full address width
)
(
// global
input wire clk_a,
input wire clk_b,
input wire rst_n,
input wire clr_a,
input wire clr_b,
// FIFO write interface
input wire write,
input wire [DBITWIDTH-1:0] write_data,
// FIFO read interface
input wire read,
output wire [DBITWIDTH-1:0] read_data,
// FIFO status signals
output wire empty,
output wire almost_full,
output wire full
);
reg [ABITWIDTH:0] dcnt_a,dcnt_b;
reg [ABITWIDTH+AF_WIDTH:0] dcnt_a_almost;
reg [ABITWIDTH-1:0] wrPtr, rdPtr;
wire write_sync, read_sync;
assign empty = ~|dcnt_b;
assign full = dcnt_a[ABITWIDTH];
assign almost_full = |dcnt_a_almost[ABITWIDTH+AF_WIDTH:ABITWIDTH];
clk_domain_cross sync_wr(
.sigin(write),
.clkin(clk_a),
.clr_in(clr_a),
.clr_out(clr_b),
.clkout(clk_b),
.sigout(write_sync),
.full()
);
clk_domain_cross sync_rd(
.sigin(read),
.clkin(clk_b),
.clr_in(clr_b),
.clr_out(clr_a),
.clkout(clk_a),
.sigout(read_sync),
.full()
);
// clock domain a
always@(posedge clk_a )begin
if(clr_a)
dcnt_a <= 0;
else if(write & ~read_sync)
dcnt_a <= dcnt_a + 1;
else if(~write & read_sync)
dcnt_a <= dcnt_a - 1;
end
always@(posedge clk_a )begin
if(clr_a)
dcnt_a_almost <= AF_THRESHOLD;
else if(write & ~read_sync)
dcnt_a_almost <= dcnt_a_almost + 1;
else if(~write & read_sync)
dcnt_a_almost <= dcnt_a_almost - 1;
end
always@(posedge clk_a )begin
if(clr_a)
wrPtr <= 0;
else if(write )
wrPtr <= wrPtr + 1;
end
// clock domain b
always@(posedge clk_b )begin
if(clr_b)
dcnt_b <= 0;
else if(write_sync & ~read)
dcnt_b <= dcnt_b + 1;
else if(~write_sync & read)
dcnt_b <= dcnt_b - 1;
end
always@(posedge clk_b )begin
if(clr_b)
rdPtr <= 0;
else if(read)
rdPtr <= rdPtr + 1;
end
// storage
infer_distributed_ram
#(
.ABITWIDTH(ABITWIDTH),
.DBITWIDTH(DBITWIDTH)
)
mem
(
.clk(clk_a),
.write(write),
.wrAddr(wrPtr),
.rdAddr(rdPtr),
.din(write_data),
.dout(read_data)
);
endmodule
module infer_distributed_ram
#(
parameter ABITWIDTH = 3,
parameter DBITWIDTH = 32
)
(
input wire clk,
input wire write,
input wire [ABITWIDTH-1:0] wrAddr,
input wire [ABITWIDTH-1:0] rdAddr,
input wire [DBITWIDTH-1:0] din,
output wire [DBITWIDTH-1:0] dout
);
localparam MEM_SIZE = (2**ABITWIDTH);
//synthesis attribute ram_style of mem is distributed
reg [DBITWIDTH-1:0] mem[2**ABITWIDTH-1:0]; //pragma attribute mem ram_block FALSE
always @ (posedge clk)
begin
if (write) begin
mem[wrAddr] <= din;
end
end
assign dout = mem[rdAddr]; //unregistered read
endmodule
|
// zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz
// File Name : clk_domain_cross.v
// Description : circuit synchronizer for signal goes across
// two different clock domains
// Author : NUDT
// -------------------------------------------------------------------------------
// Version :
// -- 2011-02-15 Modify by Zefu Dai, fix the reset signals to make it consistance
// fffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff
`include "timescale.v"
module clk_domain_cross
(
sigin,
clkin,
clr_in,
clr_out,
clkout,
sigout,
full
);
input sigin;
input clkin;
input clr_in;
input clkout;
input clr_out;
output sigout;
output full;
wire [2:0] wptr,sync_wptr;
wire [2:0] rptr,sync_rptr;
wire full;
write_counter_2 write_counter(
.wptr (wptr ),
.full (full ),
.wq2_rptr (sync_rptr),
.winc (sigin ),
.wclk (clkin ),
.wrst_n (clr_in )
);
sync_reg_2 sync_write_ptr(
.out_ptr (sync_wptr),
.in_ptr (wptr ),
.clk (clkout ),
.rst_n (clr_out )
);
sync_reg_2 sync_read_ptr(
.out_ptr (sync_rptr),
.in_ptr (rptr ),
.clk (clkin ),
.rst_n (clr_in )
);
trans_counter_2 trans_counter(
.sigout (sigout ),
.rptr (rptr ),
.rq2_wptr (sync_wptr),
.rclk (clkout ),
.rrst_n (clr_out )
);
endmodule
module write_counter_2(
wptr,
full,
wq2_rptr,
winc,
wclk,
wrst_n
);
output [2:0] wptr;
output full;
input [2:0] wq2_rptr;
input winc, wclk, wrst_n;
reg [2:0] wbin;
wire [2:0] wgraynext, wbinnext;
wire wdec;
reg [2:0] wptr;
reg winc_reg;
wire [2:0] wbinnext_next;
// GRAYSTYLE2 pointer
always @(posedge wclk)
begin
if (wrst_n)
begin
{wbin, wptr} <= 0;
winc_reg<=0;
end
else
begin
{wbin, wptr} <= {wbinnext, wgraynext};
winc_reg <= winc;
end
end
assign wbinnext = wbin + winc_reg;
assign wdec = (wptr!=wq2_rptr);
assign wgraynext = (wbinnext>>1) ^ wbinnext;
assign wbinnext_next=(wbinnext+1);
assign full = (((wbinnext_next>>1)^wbinnext_next)==wq2_rptr);
endmodule
module trans_counter_2(
sigout,
rptr,
rq2_wptr,
rclk,
rrst_n
);
//output reg rempty,
//output [ADDRSIZE-1:0] raddr,
output sigout;
output [2:0] rptr;
input [2:0] rq2_wptr;
input rclk, rrst_n;
reg [2:0] rbin;
wire [2:0] rgraynext, rbinnext;
reg [2:0] rptr;
always @(posedge rclk)
begin
if (rrst_n) {rbin, rptr} <= 0;
else {rbin, rptr} <= {rbinnext, rgraynext};
end
assign rbinnext = rbin + sigout;//(rinc & ~rempty);
assign rgraynext = (rbin>>1) ^ rbin;//(rbinnext>>1) ^ rbinnext;
assign sigout=(rgraynext != rq2_wptr);
endmodule
module sync_reg_2(
out_ptr,
in_ptr,
clk,
rst_n
);
output [2:0] out_ptr;
input [2:0] in_ptr;
input clk, rst_n;
reg [2:0] out1_ptr;
reg [2:0] out_ptr;
always @(posedge clk)
begin
if (rst_n) {out_ptr,out1_ptr} <= 0;
else {out_ptr,out1_ptr} <= {out1_ptr,in_ptr};
end
endmodule
|
module ClockGenerator
(
input wire EXTERNAL_RESET_L,
output reg CLOCKS_STABLE_H,
input wire CLK_33MHz,
output wire CLK_80MHz,
output wire CLK_320MHz
);
localparam DLL_RESET_COUNTER_LEN = 4;
wire CLK_80MHz_GENERATOR_LOCKED_H, CLK_320MHz_GENERATOR_LOCKED_H;
reg [DLL_RESET_COUNTER_LEN-1:0] DLLResetCounter;
reg CLOCK_GENERATOR_RESET_H;
// This is a registered signal in order to avoid input setup time problems with all the flip flops that use it as a reset
reg CLK_80MHz_GENERATOR_LOCKED_H_REG, CLK_320MHz_GENERATOR_LOCKED_H_REG, EXT_RESET_CLK_80MHz_L;
always @(posedge CLK_80MHz) begin
EXT_RESET_CLK_80MHz_L <= EXTERNAL_RESET_L;
CLK_80MHz_GENERATOR_LOCKED_H_REG <= CLK_80MHz_GENERATOR_LOCKED_H;
// CLK_320MHz_GENERATOR_LOCKED_H_REG <= CLK_320MHz_GENERATOR_LOCKED_H;
CLOCKS_STABLE_H <= EXT_RESET_CLK_80MHz_L & DLLResetCounter[DLL_RESET_COUNTER_LEN-1] & CLK_80MHz_GENERATOR_LOCKED_H_REG;// & CLK_320MHz_GENERATOR_LOCKED_H_REG;
end
// This is a registered signal in order to avoid input setup time problems with all the flip flops that use it as a reset
reg EXT_RESET_CLK_33MHz_L;
// Make sure that the clocks stable signal is low right after FPGA configuration, and set the initial DLLResetCounter to 0
// right after configuration in order to simulate a reset button push.
initial begin
EXT_RESET_CLK_80MHz_L <= 1'b1;
DLLResetCounter <= 0;
CLOCKS_STABLE_H <= 1'b0;
CLOCK_GENERATOR_RESET_H <= 1'b0;
CLK_80MHz_GENERATOR_LOCKED_H_REG <= 1'b0;
// CLK_320MHz_GENERATOR_LOCKED_H_REG <= 1'b0;
end
always @(posedge(CLK_33MHz)) begin
EXT_RESET_CLK_33MHz_L <= EXTERNAL_RESET_L;
if (EXT_RESET_CLK_33MHz_L == 0) begin
DLLResetCounter <= 0;
CLOCK_GENERATOR_RESET_H <= 0;
end
else if (DLLResetCounter[DLL_RESET_COUNTER_LEN-1] == 1'b0) begin
DLLResetCounter <= DLLResetCounter + 1;
CLOCK_GENERATOR_RESET_H <= 1;
end
else
CLOCK_GENERATOR_RESET_H <= 0;
end
// 80MHz clock generation, based on page 91 of the Virtex 5 User Guide, and datasheet
// Fin = 33MHz, Fpfdmin = 19MHz, Fpfdmax = 450MHz, Fvcomin = 400MHz, Fvcomax = 900MHz
// Dmin = Fin/Fpfdmax = 1 (just satisfying the phase detector max frequency)
// Dmax = Fin/Fpfdmin = 1 (if you divide input clock by more than one, 33 MHz will be below 19MHz)
// Mmin = Fvcomin/Fin = 13 (round up to avoid hitting Fvcomin)
// Mmax = Dmin*Fvcomax/Fin = 27 (round down to avoid hitting Fvcomax)
// Mideal = Dmin*Fvcomax/Fin = 27
// In my spreadsheet I found an optimum of Din = 1, M = 17, D0 = 4 gives 140.25MHz
wire CLK_80MHz_FB, CLK_80MHz_Raw, CLK_80MHz_270_Raw;
wire CLK_320MHz_Raw;
defparam CLK_80MHz_Generator.CLKIN1_PERIOD = 25.0;
defparam CLK_80MHz_Generator.DIVCLK_DIVIDE = 1;
// 80 MHz
defparam CLK_80MHz_Generator.CLKFBOUT_MULT_F = 16.0;
defparam CLK_80MHz_Generator.CLKOUT0_DIVIDE_F = 16.0;
// 320 MHz
defparam CLK_80MHz_Generator.CLKOUT1_DIVIDE = 4;
MMCM_BASE CLK_80MHz_Generator (
.CLKFBOUT(CLK_80MHz_FB), // 1-bit MMCM Feedback clock output
.CLKFBOUTB(), // 1-bit Inverted MMCM feedback clock output
.CLKOUT0(CLK_80MHz_Raw), // 1-bit MMCM clock output 0
.CLKOUT0B(), // 1-bit Inverted MMCM clock output 0
.CLKOUT1(CLK_320MHz_Raw), // 1-bit MMCM clock output 1
.CLKOUT1B(), // 1-bit Inverted MMCM clock output 1
.CLKOUT2(), // 1-bit MMCM clock output 2
.CLKOUT2B(), // 1-bit Inverted MMCM clock output 2
.CLKOUT3(), // 1-bit MMCM clock output 3
.CLKOUT3B(), // 1-bit Inverted MMCM clock output 3
.CLKOUT4(), // 1-bit MMCM clock output 4
.CLKOUT5(), // 1-bit MMCM clock output 5, not used if CLKOUT0 is not an integer
.CLKOUT6(), // 1-bit MMCM clock output 6, not used if CLKFBOUT_MULT is not an integer
.LOCKED(CLK_80MHz_GENERATOR_LOCKED_H), // 1-bit MMC locked signal
.CLKFBIN(CLK_80MHz_FB), // 1-bit Feedback clock pin to the MMCM
.CLKIN1(CLK_33MHz), // 1-bit Reference clock pin 1 to the MMCM
.PWRDWN(1'b0), // 1-bit Power down
.RST(CLOCK_GENERATOR_RESET_H) // 1-bit MMCM global reset pin
);
/* PLL_BASE CLK_80MHz_Generator (
.RST(CLOCK_GENERATOR_RESET_H), // Just use the first SRAM clock reset
.CLKIN(CLK_33MHz),
.CLKFBIN(CLK_80MHz_FB),
.CLKOUT0(CLK_80MHz_Raw),
.CLKOUT1(),
.CLKOUT2(),
.CLKOUT3(),
.CLKOUT4(),
.CLKOUT5(),
.CLKFBOUT(CLK_80MHz_FB),
.LOCKED(CLK_80MHz_GENERATOR_LOCKED_H)
);*/
BUFG CLK_80MHz_Buffer ( .I(CLK_80MHz_Raw), .O(CLK_80MHz) );
BUFG CLK_320MHz_Buffer ( .I(CLK_320MHz_Raw), .O(CLK_320MHz) );
// DDR2 200MHz clock, similar to above
// From the spreadsheet Din = 1, M = 25, D0 = 4 gives 206.25MHz
// From the spreadsheet Din = 1, M = 24, D0 = 4 gives 198.0MHz
/* defparam CLK_320MHz_Generator.CLKIN_PERIOD = 25;
defparam CLK_320MHz_Generator.DIVCLK_DIVIDE = 1;
// 333.33 MHz
defparam CLK_320MHz_Generator.CLKFBOUT_MULT = 16;
defparam CLK_320MHz_Generator.CLKOUT0_DIVIDE = 2;
defparam CLK_80MHz_Generator.CLKIN1_PERIOD = 25.0;
defparam CLK_80MHz_Generator.DIVCLK_DIVIDE = 1;
PLL_BASE CLK_320MHz_Generator (
.RST(CLOCK_GENERATOR_RESET_H), // Just use the first SRAM clock reset
.CLKIN(CLK_33MHz),
.CLKFBIN(CLK_320MHz_FB),
.CLKOUT0(CLK_320MHz_Raw),
.CLKOUT1(),
.CLKOUT2(),
.CLKOUT3(),
.CLKOUT4(),
.CLKOUT5(),
.CLKFBOUT(CLK_320MHz_FB),
.LOCKED(CLK_320MHz_GENERATOR_LOCKED_H)
);*/
endmodule
|
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used *
* solely for design, simulation, implementation and creation of *
* design files limited to Xilinx devices or technologies. Use *
* with non-Xilinx devices or technologies is expressly prohibited *
* and immediately terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" *
* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR *
* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION *
* AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION *
* OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS *
* IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, *
* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE *
* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY *
* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS *
* FOR A PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support *
* appliances, devices, or systems. Use in such applications are *
* expressly prohibited. *
* *
* (c) Copyright 1995-2011 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// You must compile the wrapper file fifo_16.v when simulating
// the core, fifo_16. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
`timescale 1ns/1ps
module fifo_16(
clk,
rst,
din,
wr_en,
rd_en,
dout,
full,
empty,
valid
);
input clk;
input rst;
input [8 : 0] din;
input wr_en;
input rd_en;
output [8 : 0] dout;
output full;
output empty;
output valid;
// synthesis translate_off
FIFO_GENERATOR_V8_1 #(
.C_ADD_NGC_CONSTRAINT(0),
.C_APPLICATION_TYPE_AXIS(0),
.C_APPLICATION_TYPE_RACH(0),
.C_APPLICATION_TYPE_RDCH(0),
.C_APPLICATION_TYPE_WACH(0),
.C_APPLICATION_TYPE_WDCH(0),
.C_APPLICATION_TYPE_WRCH(0),
.C_AXI_ADDR_WIDTH(32),
.C_AXI_ARUSER_WIDTH(1),
.C_AXI_AWUSER_WIDTH(1),
.C_AXI_BUSER_WIDTH(1),
.C_AXI_DATA_WIDTH(64),
.C_AXI_ID_WIDTH(4),
.C_AXI_RUSER_WIDTH(1),
.C_AXI_TYPE(0),
.C_AXI_WUSER_WIDTH(1),
.C_AXIS_TDATA_WIDTH(64),
.C_AXIS_TDEST_WIDTH(4),
.C_AXIS_TID_WIDTH(8),
.C_AXIS_TKEEP_WIDTH(4),
.C_AXIS_TSTRB_WIDTH(4),
.C_AXIS_TUSER_WIDTH(4),
.C_AXIS_TYPE(0),
.C_COMMON_CLOCK(1),
.C_COUNT_TYPE(0),
.C_DATA_COUNT_WIDTH(9),
.C_DEFAULT_VALUE("BlankString"),
.C_DIN_WIDTH(9),
.C_DIN_WIDTH_AXIS(1),
.C_DIN_WIDTH_RACH(32),
.C_DIN_WIDTH_RDCH(64),
.C_DIN_WIDTH_WACH(32),
.C_DIN_WIDTH_WDCH(64),
.C_DIN_WIDTH_WRCH(2),
.C_DOUT_RST_VAL("0"),
.C_DOUT_WIDTH(9),
.C_ENABLE_RLOCS(0),
.C_ENABLE_RST_SYNC(1),
.C_ERROR_INJECTION_TYPE(0),
.C_ERROR_INJECTION_TYPE_AXIS(0),
.C_ERROR_INJECTION_TYPE_RACH(0),
.C_ERROR_INJECTION_TYPE_RDCH(0),
.C_ERROR_INJECTION_TYPE_WACH(0),
.C_ERROR_INJECTION_TYPE_WDCH(0),
.C_ERROR_INJECTION_TYPE_WRCH(0),
.C_FAMILY("virtex6"),
.C_FULL_FLAGS_RST_VAL(0),
.C_HAS_ALMOST_EMPTY(0),
.C_HAS_ALMOST_FULL(0),
.C_HAS_AXI_ARUSER(0),
.C_HAS_AXI_AWUSER(0),
.C_HAS_AXI_BUSER(0),
.C_HAS_AXI_RD_CHANNEL(0),
.C_HAS_AXI_RUSER(0),
.C_HAS_AXI_WR_CHANNEL(0),
.C_HAS_AXI_WUSER(0),
.C_HAS_AXIS_TDATA(0),
.C_HAS_AXIS_TDEST(0),
.C_HAS_AXIS_TID(0),
.C_HAS_AXIS_TKEEP(0),
.C_HAS_AXIS_TLAST(0),
.C_HAS_AXIS_TREADY(1),
.C_HAS_AXIS_TSTRB(0),
.C_HAS_AXIS_TUSER(0),
.C_HAS_BACKUP(0),
.C_HAS_DATA_COUNT(0),
.C_HAS_DATA_COUNTS_AXIS(0),
.C_HAS_DATA_COUNTS_RACH(0),
.C_HAS_DATA_COUNTS_RDCH(0),
.C_HAS_DATA_COUNTS_WACH(0),
.C_HAS_DATA_COUNTS_WDCH(0),
.C_HAS_DATA_COUNTS_WRCH(0),
.C_HAS_INT_CLK(0),
.C_HAS_MASTER_CE(0),
.C_HAS_MEMINIT_FILE(0),
.C_HAS_OVERFLOW(0),
.C_HAS_PROG_FLAGS_AXIS(0),
.C_HAS_PROG_FLAGS_RACH(0),
.C_HAS_PROG_FLAGS_RDCH(0),
.C_HAS_PROG_FLAGS_WACH(0),
.C_HAS_PROG_FLAGS_WDCH(0),
.C_HAS_PROG_FLAGS_WRCH(0),
.C_HAS_RD_DATA_COUNT(0),
.C_HAS_RD_RST(0),
.C_HAS_RST(1),
.C_HAS_SLAVE_CE(0),
.C_HAS_SRST(0),
.C_HAS_UNDERFLOW(0),
.C_HAS_VALID(1),
.C_HAS_WR_ACK(0),
.C_HAS_WR_DATA_COUNT(0),
.C_HAS_WR_RST(0),
.C_IMPLEMENTATION_TYPE(5),
.C_IMPLEMENTATION_TYPE_AXIS(1),
.C_IMPLEMENTATION_TYPE_RACH(1),
.C_IMPLEMENTATION_TYPE_RDCH(1),
.C_IMPLEMENTATION_TYPE_WACH(1),
.C_IMPLEMENTATION_TYPE_WDCH(1),
.C_IMPLEMENTATION_TYPE_WRCH(1),
.C_INIT_WR_PNTR_VAL(0),
.C_INTERFACE_TYPE(0),
.C_MEMORY_TYPE(4),
.C_MIF_FILE_NAME("BlankString"),
.C_MSGON_VAL(1),
.C_OPTIMIZATION_MODE(0),
.C_OVERFLOW_LOW(0),
.C_PRELOAD_LATENCY(2),
.C_PRELOAD_REGS(1),
.C_PRIM_FIFO_TYPE("512x36"),
.C_PROG_EMPTY_THRESH_ASSERT_VAL(2),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH(1022),
.C_PROG_EMPTY_THRESH_NEGATE_VAL(3),
.C_PROG_EMPTY_TYPE(0),
.C_PROG_EMPTY_TYPE_AXIS(5),
.C_PROG_EMPTY_TYPE_RACH(5),
.C_PROG_EMPTY_TYPE_RDCH(5),
.C_PROG_EMPTY_TYPE_WACH(5),
.C_PROG_EMPTY_TYPE_WDCH(5),
.C_PROG_EMPTY_TYPE_WRCH(5),
.C_PROG_FULL_THRESH_ASSERT_VAL(511),
.C_PROG_FULL_THRESH_ASSERT_VAL_AXIS(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_RACH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_RDCH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_WACH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_WDCH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_WRCH(1023),
.C_PROG_FULL_THRESH_NEGATE_VAL(510),
.C_PROG_FULL_TYPE(0),
.C_PROG_FULL_TYPE_AXIS(5),
.C_PROG_FULL_TYPE_RACH(5),
.C_PROG_FULL_TYPE_RDCH(5),
.C_PROG_FULL_TYPE_WACH(5),
.C_PROG_FULL_TYPE_WDCH(5),
.C_PROG_FULL_TYPE_WRCH(5),
.C_RACH_TYPE(0),
.C_RD_DATA_COUNT_WIDTH(9),
.C_RD_DEPTH(512),
.C_RD_FREQ(1),
.C_RD_PNTR_WIDTH(9),
.C_RDCH_TYPE(0),
.C_REG_SLICE_MODE_AXIS(0),
.C_REG_SLICE_MODE_RACH(0),
.C_REG_SLICE_MODE_RDCH(0),
.C_REG_SLICE_MODE_WACH(0),
.C_REG_SLICE_MODE_WDCH(0),
.C_REG_SLICE_MODE_WRCH(0),
.C_UNDERFLOW_LOW(0),
.C_USE_COMMON_OVERFLOW(0),
.C_USE_COMMON_UNDERFLOW(0),
.C_USE_DEFAULT_SETTINGS(0),
.C_USE_DOUT_RST(1),
.C_USE_ECC(0),
.C_USE_ECC_AXIS(0),
.C_USE_ECC_RACH(0),
.C_USE_ECC_RDCH(0),
.C_USE_ECC_WACH(0),
.C_USE_ECC_WDCH(0),
.C_USE_ECC_WRCH(0),
.C_USE_EMBEDDED_REG(1),
.C_USE_FIFO16_FLAGS(0),
.C_USE_FWFT_DATA_COUNT(0),
.C_VALID_LOW(0),
.C_WACH_TYPE(0),
.C_WDCH_TYPE(0),
.C_WR_ACK_LOW(0),
.C_WR_DATA_COUNT_WIDTH(9),
.C_WR_DEPTH(512),
.C_WR_DEPTH_AXIS(1024),
.C_WR_DEPTH_RACH(16),
.C_WR_DEPTH_RDCH(1024),
.C_WR_DEPTH_WACH(16),
.C_WR_DEPTH_WDCH(1024),
.C_WR_DEPTH_WRCH(16),
.C_WR_FREQ(1),
.C_WR_PNTR_WIDTH(9),
.C_WR_PNTR_WIDTH_AXIS(10),
.C_WR_PNTR_WIDTH_RACH(4),
.C_WR_PNTR_WIDTH_RDCH(10),
.C_WR_PNTR_WIDTH_WACH(4),
.C_WR_PNTR_WIDTH_WDCH(10),
.C_WR_PNTR_WIDTH_WRCH(4),
.C_WR_RESPONSE_LATENCY(1),
.C_WRCH_TYPE(0)
)
inst (
.CLK(clk),
.RST(rst),
.DIN(din),
.WR_EN(wr_en),
.RD_EN(rd_en),
.DOUT(dout),
.FULL(full),
.EMPTY(empty),
.VALID(valid),
.BACKUP(),
.BACKUP_MARKER(),
.SRST(),
.WR_CLK(),
.WR_RST(),
.RD_CLK(),
.RD_RST(),
.PROG_EMPTY_THRESH(),
.PROG_EMPTY_THRESH_ASSERT(),
.PROG_EMPTY_THRESH_NEGATE(),
.PROG_FULL_THRESH(),
.PROG_FULL_THRESH_ASSERT(),
.PROG_FULL_THRESH_NEGATE(),
.INT_CLK(),
.INJECTDBITERR(),
.INJECTSBITERR(),
.ALMOST_FULL(),
.WR_ACK(),
.OVERFLOW(),
.ALMOST_EMPTY(),
.UNDERFLOW(),
.DATA_COUNT(),
.RD_DATA_COUNT(),
.WR_DATA_COUNT(),
.PROG_FULL(),
.PROG_EMPTY(),
.SBITERR(),
.DBITERR(),
.M_ACLK(),
.S_ACLK(),
.S_ARESETN(),
.M_ACLK_EN(),
.S_ACLK_EN(),
.S_AXI_AWID(),
.S_AXI_AWADDR(),
.S_AXI_AWLEN(),
.S_AXI_AWSIZE(),
.S_AXI_AWBURST(),
.S_AXI_AWLOCK(),
.S_AXI_AWCACHE(),
.S_AXI_AWPROT(),
.S_AXI_AWQOS(),
.S_AXI_AWREGION(),
.S_AXI_AWUSER(),
.S_AXI_AWVALID(),
.S_AXI_AWREADY(),
.S_AXI_WID(),
.S_AXI_WDATA(),
.S_AXI_WSTRB(),
.S_AXI_WLAST(),
.S_AXI_WUSER(),
.S_AXI_WVALID(),
.S_AXI_WREADY(),
.S_AXI_BID(),
.S_AXI_BRESP(),
.S_AXI_BUSER(),
.S_AXI_BVALID(),
.S_AXI_BREADY(),
.M_AXI_AWID(),
.M_AXI_AWADDR(),
.M_AXI_AWLEN(),
.M_AXI_AWSIZE(),
.M_AXI_AWBURST(),
.M_AXI_AWLOCK(),
.M_AXI_AWCACHE(),
.M_AXI_AWPROT(),
.M_AXI_AWQOS(),
.M_AXI_AWREGION(),
.M_AXI_AWUSER(),
.M_AXI_AWVALID(),
.M_AXI_AWREADY(),
.M_AXI_WID(),
.M_AXI_WDATA(),
.M_AXI_WSTRB(),
.M_AXI_WLAST(),
.M_AXI_WUSER(),
.M_AXI_WVALID(),
.M_AXI_WREADY(),
.M_AXI_BID(),
.M_AXI_BRESP(),
.M_AXI_BUSER(),
.M_AXI_BVALID(),
.M_AXI_BREADY(),
.S_AXI_ARID(),
.S_AXI_ARADDR(),
.S_AXI_ARLEN(),
.S_AXI_ARSIZE(),
.S_AXI_ARBURST(),
.S_AXI_ARLOCK(),
.S_AXI_ARCACHE(),
.S_AXI_ARPROT(),
.S_AXI_ARQOS(),
.S_AXI_ARREGION(),
.S_AXI_ARUSER(),
.S_AXI_ARVALID(),
.S_AXI_ARREADY(),
.S_AXI_RID(),
.S_AXI_RDATA(),
.S_AXI_RRESP(),
.S_AXI_RLAST(),
.S_AXI_RUSER(),
.S_AXI_RVALID(),
.S_AXI_RREADY(),
.M_AXI_ARID(),
.M_AXI_ARADDR(),
.M_AXI_ARLEN(),
.M_AXI_ARSIZE(),
.M_AXI_ARBURST(),
.M_AXI_ARLOCK(),
.M_AXI_ARCACHE(),
.M_AXI_ARPROT(),
.M_AXI_ARQOS(),
.M_AXI_ARREGION(),
.M_AXI_ARUSER(),
.M_AXI_ARVALID(),
.M_AXI_ARREADY(),
.M_AXI_RID(),
.M_AXI_RDATA(),
.M_AXI_RRESP(),
.M_AXI_RLAST(),
.M_AXI_RUSER(),
.M_AXI_RVALID(),
.M_AXI_RREADY(),
.S_AXIS_TVALID(),
.S_AXIS_TREADY(),
.S_AXIS_TDATA(),
.S_AXIS_TSTRB(),
.S_AXIS_TKEEP(),
.S_AXIS_TLAST(),
.S_AXIS_TID(),
.S_AXIS_TDEST(),
.S_AXIS_TUSER(),
.M_AXIS_TVALID(),
.M_AXIS_TREADY(),
.M_AXIS_TDATA(),
.M_AXIS_TSTRB(),
.M_AXIS_TKEEP(),
.M_AXIS_TLAST(),
.M_AXIS_TID(),
.M_AXIS_TDEST(),
.M_AXIS_TUSER(),
.AXI_AW_INJECTSBITERR(),
.AXI_AW_INJECTDBITERR(),
.AXI_AW_PROG_FULL_THRESH(),
.AXI_AW_PROG_EMPTY_THRESH(),
.AXI_AW_DATA_COUNT(),
.AXI_AW_WR_DATA_COUNT(),
.AXI_AW_RD_DATA_COUNT(),
.AXI_AW_SBITERR(),
.AXI_AW_DBITERR(),
.AXI_AW_OVERFLOW(),
.AXI_AW_UNDERFLOW(),
.AXI_W_INJECTSBITERR(),
.AXI_W_INJECTDBITERR(),
.AXI_W_PROG_FULL_THRESH(),
.AXI_W_PROG_EMPTY_THRESH(),
.AXI_W_DATA_COUNT(),
.AXI_W_WR_DATA_COUNT(),
.AXI_W_RD_DATA_COUNT(),
.AXI_W_SBITERR(),
.AXI_W_DBITERR(),
.AXI_W_OVERFLOW(),
.AXI_W_UNDERFLOW(),
.AXI_B_INJECTSBITERR(),
.AXI_B_INJECTDBITERR(),
.AXI_B_PROG_FULL_THRESH(),
.AXI_B_PROG_EMPTY_THRESH(),
.AXI_B_DATA_COUNT(),
.AXI_B_WR_DATA_COUNT(),
.AXI_B_RD_DATA_COUNT(),
.AXI_B_SBITERR(),
.AXI_B_DBITERR(),
.AXI_B_OVERFLOW(),
.AXI_B_UNDERFLOW(),
.AXI_AR_INJECTSBITERR(),
.AXI_AR_INJECTDBITERR(),
.AXI_AR_PROG_FULL_THRESH(),
.AXI_AR_PROG_EMPTY_THRESH(),
.AXI_AR_DATA_COUNT(),
.AXI_AR_WR_DATA_COUNT(),
.AXI_AR_RD_DATA_COUNT(),
.AXI_AR_SBITERR(),
.AXI_AR_DBITERR(),
.AXI_AR_OVERFLOW(),
.AXI_AR_UNDERFLOW(),
.AXI_R_INJECTSBITERR(),
.AXI_R_INJECTDBITERR(),
.AXI_R_PROG_FULL_THRESH(),
.AXI_R_PROG_EMPTY_THRESH(),
.AXI_R_DATA_COUNT(),
.AXI_R_WR_DATA_COUNT(),
.AXI_R_RD_DATA_COUNT(),
.AXI_R_SBITERR(),
.AXI_R_DBITERR(),
.AXI_R_OVERFLOW(),
.AXI_R_UNDERFLOW(),
.AXIS_INJECTSBITERR(),
.AXIS_INJECTDBITERR(),
.AXIS_PROG_FULL_THRESH(),
.AXIS_PROG_EMPTY_THRESH(),
.AXIS_DATA_COUNT(),
.AXIS_WR_DATA_COUNT(),
.AXIS_RD_DATA_COUNT(),
.AXIS_SBITERR(),
.AXIS_DBITERR(),
.AXIS_OVERFLOW(),
.AXIS_UNDERFLOW()
);
// synthesis translate_on
endmodule
|
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used *
* solely for design, simulation, implementation and creation of *
* design files limited to Xilinx devices or technologies. Use *
* with non-Xilinx devices or technologies is expressly prohibited *
* and immediately terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" *
* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR *
* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION *
* AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION *
* OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS *
* IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, *
* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE *
* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY *
* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS *
* FOR A PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support *
* appliances, devices, or systems. Use in such applications are *
* expressly prohibited. *
* *
* (c) Copyright 1995-2011 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// You must compile the wrapper file gsm_sram.v when simulating
// the core, gsm_sram. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
`timescale 1ns/1ps
module gsm_sram(
clka,
wea,
addra,
dina,
clkb,
addrb,
doutb
);
input clka;
input [0 : 0] wea;
input [8 : 0] addra;
input [131 : 0] dina;
input clkb;
input [8 : 0] addrb;
output [131 : 0] doutb;
// synthesis translate_off
BLK_MEM_GEN_V6_1 #(
.C_ADDRA_WIDTH(9),
.C_ADDRB_WIDTH(9),
.C_ALGORITHM(0),
.C_AXI_ID_WIDTH(4),
.C_AXI_SLAVE_TYPE(0),
.C_AXI_TYPE(1),
.C_BYTE_SIZE(9),
.C_COMMON_CLK(1),
.C_DEFAULT_DATA("0"),
.C_DISABLE_WARN_BHV_COLL(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_FAMILY("virtex6"),
.C_HAS_AXI_ID(0),
.C_HAS_ENA(0),
.C_HAS_ENB(0),
.C_HAS_INJECTERR(0),
.C_HAS_MEM_OUTPUT_REGS_A(0),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(1),
.C_HAS_REGCEA(0),
.C_HAS_REGCEB(0),
.C_HAS_RSTA(0),
.C_HAS_RSTB(0),
.C_HAS_SOFTECC_INPUT_REGS_A(0),
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
.C_INIT_FILE_NAME("no_coe_file_loaded"),
.C_INITA_VAL("0"),
.C_INITB_VAL("0"),
.C_INTERFACE_TYPE(0),
.C_LOAD_INIT_FILE(0),
.C_MEM_TYPE(1),
.C_MUX_PIPELINE_STAGES(0),
.C_PRIM_TYPE(6),
.C_READ_DEPTH_A(512),
.C_READ_DEPTH_B(512),
.C_READ_WIDTH_A(132),
.C_READ_WIDTH_B(132),
.C_RST_PRIORITY_A("CE"),
.C_RST_PRIORITY_B("CE"),
.C_RST_TYPE("SYNC"),
.C_RSTRAM_A(0),
.C_RSTRAM_B(0),
.C_SIM_COLLISION_CHECK("ALL"),
.C_USE_BYTE_WEA(0),
.C_USE_BYTE_WEB(0),
.C_USE_DEFAULT_DATA(0),
.C_USE_ECC(0),
.C_USE_SOFTECC(0),
.C_WEA_WIDTH(1),
.C_WEB_WIDTH(1),
.C_WRITE_DEPTH_A(512),
.C_WRITE_DEPTH_B(512),
.C_WRITE_MODE_A("READ_FIRST"),
.C_WRITE_MODE_B("READ_FIRST"),
.C_WRITE_WIDTH_A(132),
.C_WRITE_WIDTH_B(132),
.C_XDEVICEFAMILY("virtex6")
)
inst (
.CLKA(clka),
.WEA(wea),
.ADDRA(addra),
.DINA(dina),
.CLKB(clkb),
.ADDRB(addrb),
.DOUTB(doutb),
.RSTA(),
.ENA(),
.REGCEA(),
.DOUTA(),
.RSTB(),
.ENB(),
.REGCEB(),
.WEB(),
.DINB(),
.INJECTSBITERR(),
.INJECTDBITERR(),
.SBITERR(),
.DBITERR(),
.RDADDRECC(),
.S_ACLK(),
.S_ARESETN(),
.S_AXI_AWID(),
.S_AXI_AWADDR(),
.S_AXI_AWLEN(),
.S_AXI_AWSIZE(),
.S_AXI_AWBURST(),
.S_AXI_AWVALID(),
.S_AXI_AWREADY(),
.S_AXI_WDATA(),
.S_AXI_WSTRB(),
.S_AXI_WLAST(),
.S_AXI_WVALID(),
.S_AXI_WREADY(),
.S_AXI_BID(),
.S_AXI_BRESP(),
.S_AXI_BVALID(),
.S_AXI_BREADY(),
.S_AXI_ARID(),
.S_AXI_ARADDR(),
.S_AXI_ARLEN(),
.S_AXI_ARSIZE(),
.S_AXI_ARBURST(),
.S_AXI_ARVALID(),
.S_AXI_ARREADY(),
.S_AXI_RID(),
.S_AXI_RDATA(),
.S_AXI_RRESP(),
.S_AXI_RLAST(),
.S_AXI_RVALID(),
.S_AXI_RREADY(),
.S_AXI_INJECTSBITERR(),
.S_AXI_INJECTDBITERR(),
.S_AXI_SBITERR(),
.S_AXI_DBITERR(),
.S_AXI_RDADDRECC()
);
// synthesis translate_on
endmodule
|
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used *
* solely for design, simulation, implementation and creation of *
* design files limited to Xilinx devices or technologies. Use *
* with non-Xilinx devices or technologies is expressly prohibited *
* and immediately terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" *
* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR *
* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION *
* AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION *
* OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS *
* IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, *
* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE *
* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY *
* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS *
* FOR A PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support *
* appliances, devices, or systems. Use in such applications are *
* expressly prohibited. *
* *
* (c) Copyright 1995-2011 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// You must compile the wrapper file malloc_core.v when simulating
// the core, malloc_core. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
`timescale 1ns/1ps
module malloc_core(
clka,
wea,
addra,
dina,
douta,
clkb,
rstb,
web,
addrb,
dinb,
doutb
);
input clka;
input [0 : 0] wea;
input [9 : 0] addra;
input [3 : 0] dina;
output [3 : 0] douta;
input clkb;
input rstb;
input [0 : 0] web;
input [11 : 0] addrb;
input [0 : 0] dinb;
output [3 : 0] doutb;
// synthesis translate_off
BLK_MEM_GEN_V6_1 #(
.C_ADDRA_WIDTH(10),
.C_ADDRB_WIDTH(12),
.C_ALGORITHM(0),
.C_AXI_ID_WIDTH(4),
.C_AXI_SLAVE_TYPE(0),
.C_AXI_TYPE(1),
.C_BYTE_SIZE(9),
.C_COMMON_CLK(1),
.C_DEFAULT_DATA("0"),
.C_DISABLE_WARN_BHV_COLL(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_FAMILY("virtex6"),
.C_HAS_AXI_ID(0),
.C_HAS_ENA(0),
.C_HAS_ENB(0),
.C_HAS_INJECTERR(0),
.C_HAS_MEM_OUTPUT_REGS_A(0),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(1),
.C_HAS_MUX_OUTPUT_REGS_B(1),
.C_HAS_REGCEA(0),
.C_HAS_REGCEB(0),
.C_HAS_RSTA(0),
.C_HAS_RSTB(1),
.C_HAS_SOFTECC_INPUT_REGS_A(0),
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
.C_INIT_FILE_NAME("no_coe_file_loaded"),
.C_INITA_VAL("0"),
.C_INITB_VAL("0"),
.C_INTERFACE_TYPE(0),
.C_LOAD_INIT_FILE(0),
.C_MEM_TYPE(2),
.C_MUX_PIPELINE_STAGES(0),
.C_PRIM_TYPE(2),
.C_READ_DEPTH_A(1024),
.C_READ_DEPTH_B(1024),
.C_READ_WIDTH_A(4),
.C_READ_WIDTH_B(4),
.C_RST_PRIORITY_A("CE"),
.C_RST_PRIORITY_B("CE"),
.C_RST_TYPE("SYNC"),
.C_RSTRAM_A(0),
.C_RSTRAM_B(0),
.C_SIM_COLLISION_CHECK("ALL"),
.C_USE_BYTE_WEA(0),
.C_USE_BYTE_WEB(0),
.C_USE_DEFAULT_DATA(0),
.C_USE_ECC(0),
.C_USE_SOFTECC(0),
.C_WEA_WIDTH(1),
.C_WEB_WIDTH(1),
.C_WRITE_DEPTH_A(1024),
.C_WRITE_DEPTH_B(4096),
.C_WRITE_MODE_A("WRITE_FIRST"),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_A(4),
.C_WRITE_WIDTH_B(1),
.C_XDEVICEFAMILY("virtex6")
)
inst (
.CLKA(clka),
.WEA(wea),
.ADDRA(addra),
.DINA(dina),
.DOUTA(douta),
.CLKB(clkb),
.RSTB(rstb),
.WEB(web),
.ADDRB(addrb),
.DINB(dinb),
.DOUTB(doutb),
.RSTA(),
.ENA(),
.REGCEA(),
.ENB(),
.REGCEB(),
.INJECTSBITERR(),
.INJECTDBITERR(),
.SBITERR(),
.DBITERR(),
.RDADDRECC(),
.S_ACLK(),
.S_ARESETN(),
.S_AXI_AWID(),
.S_AXI_AWADDR(),
.S_AXI_AWLEN(),
.S_AXI_AWSIZE(),
.S_AXI_AWBURST(),
.S_AXI_AWVALID(),
.S_AXI_AWREADY(),
.S_AXI_WDATA(),
.S_AXI_WSTRB(),
.S_AXI_WLAST(),
.S_AXI_WVALID(),
.S_AXI_WREADY(),
.S_AXI_BID(),
.S_AXI_BRESP(),
.S_AXI_BVALID(),
.S_AXI_BREADY(),
.S_AXI_ARID(),
.S_AXI_ARADDR(),
.S_AXI_ARLEN(),
.S_AXI_ARSIZE(),
.S_AXI_ARBURST(),
.S_AXI_ARVALID(),
.S_AXI_ARREADY(),
.S_AXI_RID(),
.S_AXI_RDATA(),
.S_AXI_RRESP(),
.S_AXI_RLAST(),
.S_AXI_RVALID(),
.S_AXI_RREADY(),
.S_AXI_INJECTSBITERR(),
.S_AXI_INJECTDBITERR(),
.S_AXI_SBITERR(),
.S_AXI_DBITERR(),
.S_AXI_RDADDRECC()
);
// synthesis translate_on
endmodule
|
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