{"size":1142,"ext":"veo","lang":"Verilog","max_stars_count":1.0,"content":"\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\n\/\/ Copyright (c) 2013 Xilinx, Inc.\n\/\/ All Rights Reserved\n\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\n\/\/ ____ ____\n\/\/ \/ \/\\\/ \/\n\/\/ \/___\/ \\ \/ Vendor : Xilinx\n\/\/ \\ \\ \\\/ Version : 14.4\n\/\/ \\ \\ Application: Xilinx CORE Generator\n\/\/ \/ \/ Filename : b200_chipscope_ila.veo\n\/\/ \/___\/ \/\\ Timestamp : Tue Feb 19 16:52:47 PST 2013\n\/\/ \\ \\ \/ \\\n\/\/ \\___\\\/\\___\\\n\/\/\n\/\/ Design Name: ISE Instantiation template\n\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\n\n\/\/ The following must be inserted into your Verilog file for this\n\/\/ core to be instantiated. Change the instance name and port connections\n\/\/ (in parentheses) to your own signal names.\n\n\/\/----------- Begin Cut here for INSTANTIATION Template ---\/\/ INST_TAG\nb200_chipscope_ila YourInstanceName (\n .CONTROL(CONTROL), \/\/ INOUT BUS [35:0]\n .CLK(CLK), \/\/ IN\n .DATA(DATA), \/\/ IN BUS [63:0]\n .TRIG0(TRIG0) \/\/ IN BUS [7:0]\n);\n\n\/\/ INST_TAG_END ------ End INSTANTIATION Template ---------\n\n","avg_line_length":35.6875,"max_line_length":79,"alphanum_fraction":0.4632224168} {"size":7825,"ext":"veo","lang":"Verilog","max_stars_count":null,"content":"\/\/ (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.\n\/\/ \n\/\/ This file contains confidential and proprietary information\n\/\/ of Xilinx, Inc. and is protected under U.S. and\n\/\/ international copyright and other intellectual property\n\/\/ laws.\n\/\/ \n\/\/ DISCLAIMER\n\/\/ This disclaimer is not a license and does not grant any\n\/\/ rights to the materials distributed herewith. Except as\n\/\/ otherwise provided in a valid license issued to you by\n\/\/ Xilinx, and to the maximum extent permitted by applicable\n\/\/ law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n\/\/ WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n\/\/ AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n\/\/ BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n\/\/ INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n\/\/ (2) Xilinx shall not be liable (whether in contract or tort,\n\/\/ including negligence, or under any other theory of\n\/\/ liability) for any loss or damage of any kind or nature\n\/\/ related to, arising under or in connection with these\n\/\/ materials, including for any direct, or any indirect,\n\/\/ special, incidental, or consequential loss or damage\n\/\/ (including loss of data, profits, goodwill, or any type of\n\/\/ loss or damage suffered as a result of any action brought\n\/\/ by a third party) even if such damage or loss was\n\/\/ reasonably foreseeable or Xilinx had been advised of the\n\/\/ possibility of the same.\n\/\/ \n\/\/ CRITICAL APPLICATIONS\n\/\/ Xilinx products are not designed or intended to be fail-\n\/\/ safe, or for use in any application requiring fail-safe\n\/\/ performance, such as life-support or safety devices or\n\/\/ systems, Class III medical devices, nuclear facilities,\n\/\/ applications related to the deployment of airbags, or any\n\/\/ other applications that could lead to death, personal\n\/\/ injury, or severe property or environmental damage\n\/\/ (individually and collectively, \"Critical\n\/\/ Applications\"). Customer assumes the sole risk and\n\/\/ liability of any use of Xilinx products in Critical\n\/\/ Applications, subject only to applicable laws and\n\/\/ regulations governing limitations on product liability.\n\/\/ \n\/\/ THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n\/\/ PART OF THIS FILE AT ALL TIMES.\n\/\/ \n\/\/ DO NOT MODIFY THIS FILE.\n\n\/\/ IP VLNV: xilinx.com:ip:axi_dwidth_converter:2.1\n\/\/ IP Revision: 2\n\n\/\/ The following must be inserted into your Verilog file for this\n\/\/ core to be instantiated. Change the instance name and port connections\n\/\/ (in parentheses) to your own signal names.\n\n\/\/----------- Begin Cut here for INSTANTIATION Template ---\/\/ INST_TAG\ndesign_1_auto_ds_4 your_instance_name (\n .s_axi_aclk(s_axi_aclk), \/\/ input wire s_axi_aclk\n .s_axi_aresetn(s_axi_aresetn), \/\/ input wire s_axi_aresetn\n .s_axi_awaddr(s_axi_awaddr), \/\/ input wire [31 : 0] s_axi_awaddr\n .s_axi_awlen(s_axi_awlen), \/\/ input wire [7 : 0] s_axi_awlen\n .s_axi_awsize(s_axi_awsize), \/\/ input wire [2 : 0] s_axi_awsize\n .s_axi_awburst(s_axi_awburst), \/\/ input wire [1 : 0] s_axi_awburst\n .s_axi_awlock(s_axi_awlock), \/\/ input wire [0 : 0] s_axi_awlock\n .s_axi_awcache(s_axi_awcache), \/\/ input wire [3 : 0] s_axi_awcache\n .s_axi_awprot(s_axi_awprot), \/\/ input wire [2 : 0] s_axi_awprot\n .s_axi_awregion(s_axi_awregion), \/\/ input wire [3 : 0] s_axi_awregion\n .s_axi_awqos(s_axi_awqos), \/\/ input wire [3 : 0] s_axi_awqos\n .s_axi_awvalid(s_axi_awvalid), \/\/ input wire s_axi_awvalid\n .s_axi_awready(s_axi_awready), \/\/ output wire s_axi_awready\n .s_axi_wdata(s_axi_wdata), \/\/ input wire [63 : 0] s_axi_wdata\n .s_axi_wstrb(s_axi_wstrb), \/\/ input wire [7 : 0] s_axi_wstrb\n .s_axi_wlast(s_axi_wlast), \/\/ input wire s_axi_wlast\n .s_axi_wvalid(s_axi_wvalid), \/\/ input wire s_axi_wvalid\n .s_axi_wready(s_axi_wready), \/\/ output wire s_axi_wready\n .s_axi_bresp(s_axi_bresp), \/\/ output wire [1 : 0] s_axi_bresp\n .s_axi_bvalid(s_axi_bvalid), \/\/ output wire s_axi_bvalid\n .s_axi_bready(s_axi_bready), \/\/ input wire s_axi_bready\n .s_axi_araddr(s_axi_araddr), \/\/ input wire [31 : 0] s_axi_araddr\n .s_axi_arlen(s_axi_arlen), \/\/ input wire [7 : 0] s_axi_arlen\n .s_axi_arsize(s_axi_arsize), \/\/ input wire [2 : 0] s_axi_arsize\n .s_axi_arburst(s_axi_arburst), \/\/ input wire [1 : 0] s_axi_arburst\n .s_axi_arlock(s_axi_arlock), \/\/ input wire [0 : 0] s_axi_arlock\n .s_axi_arcache(s_axi_arcache), \/\/ input wire [3 : 0] s_axi_arcache\n .s_axi_arprot(s_axi_arprot), \/\/ input wire [2 : 0] s_axi_arprot\n .s_axi_arregion(s_axi_arregion), \/\/ input wire [3 : 0] s_axi_arregion\n .s_axi_arqos(s_axi_arqos), \/\/ input wire [3 : 0] s_axi_arqos\n .s_axi_arvalid(s_axi_arvalid), \/\/ input wire s_axi_arvalid\n .s_axi_arready(s_axi_arready), \/\/ output wire s_axi_arready\n .s_axi_rdata(s_axi_rdata), \/\/ output wire [63 : 0] s_axi_rdata\n .s_axi_rresp(s_axi_rresp), \/\/ output wire [1 : 0] s_axi_rresp\n .s_axi_rlast(s_axi_rlast), \/\/ output wire s_axi_rlast\n .s_axi_rvalid(s_axi_rvalid), \/\/ output wire s_axi_rvalid\n .s_axi_rready(s_axi_rready), \/\/ input wire s_axi_rready\n .m_axi_awaddr(m_axi_awaddr), \/\/ output wire [31 : 0] m_axi_awaddr\n .m_axi_awlen(m_axi_awlen), \/\/ output wire [7 : 0] m_axi_awlen\n .m_axi_awsize(m_axi_awsize), \/\/ output wire [2 : 0] m_axi_awsize\n .m_axi_awburst(m_axi_awburst), \/\/ output wire [1 : 0] m_axi_awburst\n .m_axi_awlock(m_axi_awlock), \/\/ output wire [0 : 0] m_axi_awlock\n .m_axi_awcache(m_axi_awcache), \/\/ output wire [3 : 0] m_axi_awcache\n .m_axi_awprot(m_axi_awprot), \/\/ output wire [2 : 0] m_axi_awprot\n .m_axi_awregion(m_axi_awregion), \/\/ output wire [3 : 0] m_axi_awregion\n .m_axi_awqos(m_axi_awqos), \/\/ output wire [3 : 0] m_axi_awqos\n .m_axi_awvalid(m_axi_awvalid), \/\/ output wire m_axi_awvalid\n .m_axi_awready(m_axi_awready), \/\/ input wire m_axi_awready\n .m_axi_wdata(m_axi_wdata), \/\/ output wire [31 : 0] m_axi_wdata\n .m_axi_wstrb(m_axi_wstrb), \/\/ output wire [3 : 0] m_axi_wstrb\n .m_axi_wlast(m_axi_wlast), \/\/ output wire m_axi_wlast\n .m_axi_wvalid(m_axi_wvalid), \/\/ output wire m_axi_wvalid\n .m_axi_wready(m_axi_wready), \/\/ input wire m_axi_wready\n .m_axi_bresp(m_axi_bresp), \/\/ input wire [1 : 0] m_axi_bresp\n .m_axi_bvalid(m_axi_bvalid), \/\/ input wire m_axi_bvalid\n .m_axi_bready(m_axi_bready), \/\/ output wire m_axi_bready\n .m_axi_araddr(m_axi_araddr), \/\/ output wire [31 : 0] m_axi_araddr\n .m_axi_arlen(m_axi_arlen), \/\/ output wire [7 : 0] m_axi_arlen\n .m_axi_arsize(m_axi_arsize), \/\/ output wire [2 : 0] m_axi_arsize\n .m_axi_arburst(m_axi_arburst), \/\/ output wire [1 : 0] m_axi_arburst\n .m_axi_arlock(m_axi_arlock), \/\/ output wire [0 : 0] m_axi_arlock\n .m_axi_arcache(m_axi_arcache), \/\/ output wire [3 : 0] m_axi_arcache\n .m_axi_arprot(m_axi_arprot), \/\/ output wire [2 : 0] m_axi_arprot\n .m_axi_arregion(m_axi_arregion), \/\/ output wire [3 : 0] m_axi_arregion\n .m_axi_arqos(m_axi_arqos), \/\/ output wire [3 : 0] m_axi_arqos\n .m_axi_arvalid(m_axi_arvalid), \/\/ output wire m_axi_arvalid\n .m_axi_arready(m_axi_arready), \/\/ input wire m_axi_arready\n .m_axi_rdata(m_axi_rdata), \/\/ input wire [31 : 0] m_axi_rdata\n .m_axi_rresp(m_axi_rresp), \/\/ input wire [1 : 0] m_axi_rresp\n .m_axi_rlast(m_axi_rlast), \/\/ input wire m_axi_rlast\n .m_axi_rvalid(m_axi_rvalid), \/\/ input wire m_axi_rvalid\n .m_axi_rready(m_axi_rready) \/\/ output wire m_axi_rready\n);\n\/\/ INST_TAG_END ------ End INSTANTIATION Template ---------\n\n\/\/ You must compile the wrapper file design_1_auto_ds_4.v when simulating\n\/\/ the core, design_1_auto_ds_4. When compiling the wrapper file, be sure to\n\/\/ reference the Verilog simulation library.\n\n","avg_line_length":57.1167883212,"max_line_length":76,"alphanum_fraction":0.7100319489} {"size":3325,"ext":"veo","lang":"Verilog","max_stars_count":null,"content":"\/\/ (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved.\n\/\/ \n\/\/ This file contains confidential and proprietary information\n\/\/ of Xilinx, Inc. and is protected under U.S. and\n\/\/ international copyright and other intellectual property\n\/\/ laws.\n\/\/ \n\/\/ DISCLAIMER\n\/\/ This disclaimer is not a license and does not grant any\n\/\/ rights to the materials distributed herewith. Except as\n\/\/ otherwise provided in a valid license issued to you by\n\/\/ Xilinx, and to the maximum extent permitted by applicable\n\/\/ law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n\/\/ WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n\/\/ AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n\/\/ BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n\/\/ INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n\/\/ (2) Xilinx shall not be liable (whether in contract or tort,\n\/\/ including negligence, or under any other theory of\n\/\/ liability) for any loss or damage of any kind or nature\n\/\/ related to, arising under or in connection with these\n\/\/ materials, including for any direct, or any indirect,\n\/\/ special, incidental, or consequential loss or damage\n\/\/ (including loss of data, profits, goodwill, or any type of\n\/\/ loss or damage suffered as a result of any action brought\n\/\/ by a third party) even if such damage or loss was\n\/\/ reasonably foreseeable or Xilinx had been advised of the\n\/\/ possibility of the same.\n\/\/ \n\/\/ CRITICAL APPLICATIONS\n\/\/ Xilinx products are not designed or intended to be fail-\n\/\/ safe, or for use in any application requiring fail-safe\n\/\/ performance, such as life-support or safety devices or\n\/\/ systems, Class III medical devices, nuclear facilities,\n\/\/ applications related to the deployment of airbags, or any\n\/\/ other applications that could lead to death, personal\n\/\/ injury, or severe property or environmental damage\n\/\/ (individually and collectively, \"Critical\n\/\/ Applications\"). Customer assumes the sole risk and\n\/\/ liability of any use of Xilinx products in Critical\n\/\/ Applications, subject only to applicable laws and\n\/\/ regulations governing limitations on product liability.\n\/\/ \n\/\/ THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n\/\/ PART OF THIS FILE AT ALL TIMES.\n\/\/ \n\/\/ DO NOT MODIFY THIS FILE.\n\n\/\/ IP VLNV: xilinx.com:ip:fir_compiler:7.2\n\/\/ IP Revision: 13\n\n\/\/ The following must be inserted into your Verilog file for this\n\/\/ core to be instantiated. Change the instance name and port connections\n\/\/ (in parentheses) to your own signal names.\n\n\/\/----------- Begin Cut here for INSTANTIATION Template ---\/\/ INST_TAG\nfir_compiler_0 your_instance_name (\n .aclk(aclk), \/\/ input wire aclk\n .s_axis_data_tvalid(s_axis_data_tvalid), \/\/ input wire s_axis_data_tvalid\n .s_axis_data_tready(s_axis_data_tready), \/\/ output wire s_axis_data_tready\n .s_axis_data_tdata(s_axis_data_tdata), \/\/ input wire [15 : 0] s_axis_data_tdata\n .m_axis_data_tvalid(m_axis_data_tvalid), \/\/ output wire m_axis_data_tvalid\n .m_axis_data_tdata(m_axis_data_tdata) \/\/ output wire [15 : 0] m_axis_data_tdata\n);\n\/\/ INST_TAG_END ------ End INSTANTIATION Template ---------\n\n\/\/ You must compile the wrapper file fir_compiler_0.v when simulating\n\/\/ the core, fir_compiler_0. When compiling the wrapper file, be sure to\n\/\/ reference the Verilog simulation library.\n\n","avg_line_length":46.8309859155,"max_line_length":84,"alphanum_fraction":0.7512781955} {"size":3529,"ext":"veo","lang":"Verilog","max_stars_count":9.0,"content":"\n\/\/ \n\/\/ (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.\n\/\/ \n\/\/ This file contains confidential and proprietary information\n\/\/ of Xilinx, Inc. and is protected under U.S. and\n\/\/ international copyright and other intellectual property\n\/\/ laws.\n\/\/ \n\/\/ DISCLAIMER\n\/\/ This disclaimer is not a license and does not grant any\n\/\/ rights to the materials distributed herewith. Except as\n\/\/ otherwise provided in a valid license issued to you by\n\/\/ Xilinx, and to the maximum extent permitted by applicable\n\/\/ law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n\/\/ WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n\/\/ AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n\/\/ BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n\/\/ INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n\/\/ (2) Xilinx shall not be liable (whether in contract or tort,\n\/\/ including negligence, or under any other theory of\n\/\/ liability) for any loss or damage of any kind or nature\n\/\/ related to, arising under or in connection with these\n\/\/ materials, including for any direct, or any indirect,\n\/\/ special, incidental, or consequential loss or damage\n\/\/ (including loss of data, profits, goodwill, or any type of\n\/\/ loss or damage suffered as a result of any action brought\n\/\/ by a third party) even if such damage or loss was\n\/\/ reasonably foreseeable or Xilinx had been advised of the\n\/\/ possibility of the same.\n\/\/ \n\/\/ CRITICAL APPLICATIONS\n\/\/ Xilinx products are not designed or intended to be fail-\n\/\/ safe, or for use in any application requiring fail-safe\n\/\/ performance, such as life-support or safety devices or\n\/\/ systems, Class III medical devices, nuclear facilities,\n\/\/ applications related to the deployment of airbags, or any\n\/\/ other applications that could lead to death, personal\n\/\/ injury, or severe property or environmental damage\n\/\/ (individually and collectively, \"Critical\n\/\/ Applications\"). Customer assumes the sole risk and\n\/\/ liability of any use of Xilinx products in Critical\n\/\/ Applications, subject only to applicable laws and\n\/\/ regulations governing limitations on product liability.\n\/\/ \n\/\/ THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n\/\/ PART OF THIS FILE AT ALL TIMES.\n\/\/ \n\/\/----------------------------------------------------------------------------\n\/\/ User entered comments\n\/\/----------------------------------------------------------------------------\n\/\/ None\n\/\/\n\/\/----------------------------------------------------------------------------\n\/\/ Output Output Phase Duty Cycle Pk-to-Pk Phase\n\/\/ Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)\n\/\/----------------------------------------------------------------------------\n\/\/ clk_out1____50.000______0.000______50.0______151.636_____98.575\n\/\/\n\/\/----------------------------------------------------------------------------\n\/\/ Input Clock Freq (MHz) Input Jitter (UI)\n\/\/----------------------------------------------------------------------------\n\/\/ __primary_________100.000____________0.010\n\n\/\/ The following must be inserted into your Verilog file for this\n\/\/ core to be instantiated. Change the instance name and port connections\n\/\/ (in parentheses) to your own signal names.\n\n\/\/----------- Begin Cut here for INSTANTIATION Template ---\/\/ INST_TAG\n\n clk_pll instance_name\n (\n \/\/ Clock out ports\n .clk_out1(clk_out1), \/\/ output clk_out1\n \/\/ Clock in ports\n .clk_in1(clk_in1)); \/\/ input clk_in1\n\/\/ INST_TAG_END ------ End INSTANTIATION Template ---------\n","avg_line_length":45.2435897436,"max_line_length":78,"alphanum_fraction":0.6344573534} {"size":3109,"ext":"veo","lang":"Verilog","max_stars_count":null,"content":"\/\/ (c) Copyright 1995-2019 Xilinx, Inc. All rights reserved.\n\/\/ \n\/\/ This file contains confidential and proprietary information\n\/\/ of Xilinx, Inc. and is protected under U.S. and\n\/\/ international copyright and other intellectual property\n\/\/ laws.\n\/\/ \n\/\/ DISCLAIMER\n\/\/ This disclaimer is not a license and does not grant any\n\/\/ rights to the materials distributed herewith. Except as\n\/\/ otherwise provided in a valid license issued to you by\n\/\/ Xilinx, and to the maximum extent permitted by applicable\n\/\/ law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n\/\/ WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n\/\/ AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n\/\/ BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n\/\/ INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n\/\/ (2) Xilinx shall not be liable (whether in contract or tort,\n\/\/ including negligence, or under any other theory of\n\/\/ liability) for any loss or damage of any kind or nature\n\/\/ related to, arising under or in connection with these\n\/\/ materials, including for any direct, or any indirect,\n\/\/ special, incidental, or consequential loss or damage\n\/\/ (including loss of data, profits, goodwill, or any type of\n\/\/ loss or damage suffered as a result of any action brought\n\/\/ by a third party) even if such damage or loss was\n\/\/ reasonably foreseeable or Xilinx had been advised of the\n\/\/ possibility of the same.\n\/\/ \n\/\/ CRITICAL APPLICATIONS\n\/\/ Xilinx products are not designed or intended to be fail-\n\/\/ safe, or for use in any application requiring fail-safe\n\/\/ performance, such as life-support or safety devices or\n\/\/ systems, Class III medical devices, nuclear facilities,\n\/\/ applications related to the deployment of airbags, or any\n\/\/ other applications that could lead to death, personal\n\/\/ injury, or severe property or environmental damage\n\/\/ (individually and collectively, \"Critical\n\/\/ Applications\"). Customer assumes the sole risk and\n\/\/ liability of any use of Xilinx products in Critical\n\/\/ Applications, subject only to applicable laws and\n\/\/ regulations governing limitations on product liability.\n\/\/ \n\/\/ THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n\/\/ PART OF THIS FILE AT ALL TIMES.\n\/\/ \n\/\/ DO NOT MODIFY THIS FILE.\n\n\/\/ IP VLNV: xilinx.com:ip:blk_mem_gen:8.4\n\/\/ IP Revision: 3\n\n\/\/ The following must be inserted into your Verilog file for this\n\/\/ core to be instantiated. Change the instance name and port connections\n\/\/ (in parentheses) to your own signal names.\n\n\/\/----------- Begin Cut here for INSTANTIATION Template ---\/\/ INST_TAG\nblk_mem_gen_0 your_instance_name (\n .clka(clka), \/\/ input wire clka\n .ena(ena), \/\/ input wire ena\n .wea(wea), \/\/ input wire [0 : 0] wea\n .addra(addra), \/\/ input wire [12 : 0] addra\n .dina(dina), \/\/ input wire [7 : 0] dina\n .douta(douta) \/\/ output wire [7 : 0] douta\n);\n\/\/ INST_TAG_END ------ End INSTANTIATION Template ---------\n\n\/\/ You must compile the wrapper file blk_mem_gen_0.v when simulating\n\/\/ the core, blk_mem_gen_0. When compiling the wrapper file, be sure to\n\/\/ reference the Verilog simulation library.\n\n","avg_line_length":43.7887323944,"max_line_length":73,"alphanum_fraction":0.7365712448} {"size":8540,"ext":"veo","lang":"Verilog","max_stars_count":8.0,"content":"\/\/ (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.\n\/\/ \n\/\/ This file contains confidential and proprietary information\n\/\/ of Xilinx, Inc. and is protected under U.S. and\n\/\/ international copyright and other intellectual property\n\/\/ laws.\n\/\/ \n\/\/ DISCLAIMER\n\/\/ This disclaimer is not a license and does not grant any\n\/\/ rights to the materials distributed herewith. Except as\n\/\/ otherwise provided in a valid license issued to you by\n\/\/ Xilinx, and to the maximum extent permitted by applicable\n\/\/ law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n\/\/ WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n\/\/ AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n\/\/ BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n\/\/ INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n\/\/ (2) Xilinx shall not be liable (whether in contract or tort,\n\/\/ including negligence, or under any other theory of\n\/\/ liability) for any loss or damage of any kind or nature\n\/\/ related to, arising under or in connection with these\n\/\/ materials, including for any direct, or any indirect,\n\/\/ special, incidental, or consequential loss or damage\n\/\/ (including loss of data, profits, goodwill, or any type of\n\/\/ loss or damage suffered as a result of any action brought\n\/\/ by a third party) even if such damage or loss was\n\/\/ reasonably foreseeable or Xilinx had been advised of the\n\/\/ possibility of the same.\n\/\/ \n\/\/ CRITICAL APPLICATIONS\n\/\/ Xilinx products are not designed or intended to be fail-\n\/\/ safe, or for use in any application requiring fail-safe\n\/\/ performance, such as life-support or safety devices or\n\/\/ systems, Class III medical devices, nuclear facilities,\n\/\/ applications related to the deployment of airbags, or any\n\/\/ other applications that could lead to death, personal\n\/\/ injury, or severe property or environmental damage\n\/\/ (individually and collectively, \"Critical\n\/\/ Applications\"). Customer assumes the sole risk and\n\/\/ liability of any use of Xilinx products in Critical\n\/\/ Applications, subject only to applicable laws and\n\/\/ regulations governing limitations on product liability.\n\/\/ \n\/\/ THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n\/\/ PART OF THIS FILE AT ALL TIMES.\n\/\/ \n\/\/ DO NOT MODIFY THIS FILE.\n\n\/\/ IP VLNV: xilinx.com:ip:axi_clock_converter:2.1\n\/\/ IP Revision: 11\n\n\/\/ The following must be inserted into your Verilog file for this\n\/\/ core to be instantiated. Change the instance name and port connections\n\/\/ (in parentheses) to your own signal names.\n\n\/\/----------- Begin Cut here for INSTANTIATION Template ---\/\/ INST_TAG\naxi_clock_converter_dramslim your_instance_name (\n .s_axi_aclk(s_axi_aclk), \/\/ input wire s_axi_aclk\n .s_axi_aresetn(s_axi_aresetn), \/\/ input wire s_axi_aresetn\n .s_axi_awid(s_axi_awid), \/\/ input wire [15 : 0] s_axi_awid\n .s_axi_awaddr(s_axi_awaddr), \/\/ input wire [63 : 0] s_axi_awaddr\n .s_axi_awlen(s_axi_awlen), \/\/ input wire [7 : 0] s_axi_awlen\n .s_axi_awsize(s_axi_awsize), \/\/ input wire [2 : 0] s_axi_awsize\n .s_axi_awburst(s_axi_awburst), \/\/ input wire [1 : 0] s_axi_awburst\n .s_axi_awlock(s_axi_awlock), \/\/ input wire [0 : 0] s_axi_awlock\n .s_axi_awcache(s_axi_awcache), \/\/ input wire [3 : 0] s_axi_awcache\n .s_axi_awprot(s_axi_awprot), \/\/ input wire [2 : 0] s_axi_awprot\n .s_axi_awregion(s_axi_awregion), \/\/ input wire [3 : 0] s_axi_awregion\n .s_axi_awqos(s_axi_awqos), \/\/ input wire [3 : 0] s_axi_awqos\n .s_axi_awvalid(s_axi_awvalid), \/\/ input wire s_axi_awvalid\n .s_axi_awready(s_axi_awready), \/\/ output wire s_axi_awready\n .s_axi_wdata(s_axi_wdata), \/\/ input wire [63 : 0] s_axi_wdata\n .s_axi_wstrb(s_axi_wstrb), \/\/ input wire [7 : 0] s_axi_wstrb\n .s_axi_wlast(s_axi_wlast), \/\/ input wire s_axi_wlast\n .s_axi_wvalid(s_axi_wvalid), \/\/ input wire s_axi_wvalid\n .s_axi_wready(s_axi_wready), \/\/ output wire s_axi_wready\n .s_axi_bid(s_axi_bid), \/\/ output wire [15 : 0] s_axi_bid\n .s_axi_bresp(s_axi_bresp), \/\/ output wire [1 : 0] s_axi_bresp\n .s_axi_bvalid(s_axi_bvalid), \/\/ output wire s_axi_bvalid\n .s_axi_bready(s_axi_bready), \/\/ input wire s_axi_bready\n .s_axi_arid(s_axi_arid), \/\/ input wire [15 : 0] s_axi_arid\n .s_axi_araddr(s_axi_araddr), \/\/ input wire [63 : 0] s_axi_araddr\n .s_axi_arlen(s_axi_arlen), \/\/ input wire [7 : 0] s_axi_arlen\n .s_axi_arsize(s_axi_arsize), \/\/ input wire [2 : 0] s_axi_arsize\n .s_axi_arburst(s_axi_arburst), \/\/ input wire [1 : 0] s_axi_arburst\n .s_axi_arlock(s_axi_arlock), \/\/ input wire [0 : 0] s_axi_arlock\n .s_axi_arcache(s_axi_arcache), \/\/ input wire [3 : 0] s_axi_arcache\n .s_axi_arprot(s_axi_arprot), \/\/ input wire [2 : 0] s_axi_arprot\n .s_axi_arregion(s_axi_arregion), \/\/ input wire [3 : 0] s_axi_arregion\n .s_axi_arqos(s_axi_arqos), \/\/ input wire [3 : 0] s_axi_arqos\n .s_axi_arvalid(s_axi_arvalid), \/\/ input wire s_axi_arvalid\n .s_axi_arready(s_axi_arready), \/\/ output wire s_axi_arready\n .s_axi_rid(s_axi_rid), \/\/ output wire [15 : 0] s_axi_rid\n .s_axi_rdata(s_axi_rdata), \/\/ output wire [63 : 0] s_axi_rdata\n .s_axi_rresp(s_axi_rresp), \/\/ output wire [1 : 0] s_axi_rresp\n .s_axi_rlast(s_axi_rlast), \/\/ output wire s_axi_rlast\n .s_axi_rvalid(s_axi_rvalid), \/\/ output wire s_axi_rvalid\n .s_axi_rready(s_axi_rready), \/\/ input wire s_axi_rready\n .m_axi_aclk(m_axi_aclk), \/\/ input wire m_axi_aclk\n .m_axi_aresetn(m_axi_aresetn), \/\/ input wire m_axi_aresetn\n .m_axi_awid(m_axi_awid), \/\/ output wire [15 : 0] m_axi_awid\n .m_axi_awaddr(m_axi_awaddr), \/\/ output wire [63 : 0] m_axi_awaddr\n .m_axi_awlen(m_axi_awlen), \/\/ output wire [7 : 0] m_axi_awlen\n .m_axi_awsize(m_axi_awsize), \/\/ output wire [2 : 0] m_axi_awsize\n .m_axi_awburst(m_axi_awburst), \/\/ output wire [1 : 0] m_axi_awburst\n .m_axi_awlock(m_axi_awlock), \/\/ output wire [0 : 0] m_axi_awlock\n .m_axi_awcache(m_axi_awcache), \/\/ output wire [3 : 0] m_axi_awcache\n .m_axi_awprot(m_axi_awprot), \/\/ output wire [2 : 0] m_axi_awprot\n .m_axi_awregion(m_axi_awregion), \/\/ output wire [3 : 0] m_axi_awregion\n .m_axi_awqos(m_axi_awqos), \/\/ output wire [3 : 0] m_axi_awqos\n .m_axi_awvalid(m_axi_awvalid), \/\/ output wire m_axi_awvalid\n .m_axi_awready(m_axi_awready), \/\/ input wire m_axi_awready\n .m_axi_wdata(m_axi_wdata), \/\/ output wire [63 : 0] m_axi_wdata\n .m_axi_wstrb(m_axi_wstrb), \/\/ output wire [7 : 0] m_axi_wstrb\n .m_axi_wlast(m_axi_wlast), \/\/ output wire m_axi_wlast\n .m_axi_wvalid(m_axi_wvalid), \/\/ output wire m_axi_wvalid\n .m_axi_wready(m_axi_wready), \/\/ input wire m_axi_wready\n .m_axi_bid(m_axi_bid), \/\/ input wire [15 : 0] m_axi_bid\n .m_axi_bresp(m_axi_bresp), \/\/ input wire [1 : 0] m_axi_bresp\n .m_axi_bvalid(m_axi_bvalid), \/\/ input wire m_axi_bvalid\n .m_axi_bready(m_axi_bready), \/\/ output wire m_axi_bready\n .m_axi_arid(m_axi_arid), \/\/ output wire [15 : 0] m_axi_arid\n .m_axi_araddr(m_axi_araddr), \/\/ output wire [63 : 0] m_axi_araddr\n .m_axi_arlen(m_axi_arlen), \/\/ output wire [7 : 0] m_axi_arlen\n .m_axi_arsize(m_axi_arsize), \/\/ output wire [2 : 0] m_axi_arsize\n .m_axi_arburst(m_axi_arburst), \/\/ output wire [1 : 0] m_axi_arburst\n .m_axi_arlock(m_axi_arlock), \/\/ output wire [0 : 0] m_axi_arlock\n .m_axi_arcache(m_axi_arcache), \/\/ output wire [3 : 0] m_axi_arcache\n .m_axi_arprot(m_axi_arprot), \/\/ output wire [2 : 0] m_axi_arprot\n .m_axi_arregion(m_axi_arregion), \/\/ output wire [3 : 0] m_axi_arregion\n .m_axi_arqos(m_axi_arqos), \/\/ output wire [3 : 0] m_axi_arqos\n .m_axi_arvalid(m_axi_arvalid), \/\/ output wire m_axi_arvalid\n .m_axi_arready(m_axi_arready), \/\/ input wire m_axi_arready\n .m_axi_rid(m_axi_rid), \/\/ input wire [15 : 0] m_axi_rid\n .m_axi_rdata(m_axi_rdata), \/\/ input wire [63 : 0] m_axi_rdata\n .m_axi_rresp(m_axi_rresp), \/\/ input wire [1 : 0] m_axi_rresp\n .m_axi_rlast(m_axi_rlast), \/\/ input wire m_axi_rlast\n .m_axi_rvalid(m_axi_rvalid), \/\/ input wire m_axi_rvalid\n .m_axi_rready(m_axi_rready) \/\/ output wire m_axi_rready\n);\n\/\/ INST_TAG_END ------ End INSTANTIATION Template ---------\n\n\/\/ You must compile the wrapper file axi_clock_converter_dramslim.v when simulating\n\/\/ the core, axi_clock_converter_dramslim. When compiling the wrapper file, be sure to\n\/\/ reference the Verilog simulation library.\n\n","avg_line_length":58.0952380952,"max_line_length":86,"alphanum_fraction":0.7026932084} {"size":3338,"ext":"veo","lang":"Verilog","max_stars_count":null,"content":"\/\/ (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.\n\/\/ \n\/\/ This file contains confidential and proprietary information\n\/\/ of Xilinx, Inc. and is protected under U.S. and\n\/\/ international copyright and other intellectual property\n\/\/ laws.\n\/\/ \n\/\/ DISCLAIMER\n\/\/ This disclaimer is not a license and does not grant any\n\/\/ rights to the materials distributed herewith. Except as\n\/\/ otherwise provided in a valid license issued to you by\n\/\/ Xilinx, and to the maximum extent permitted by applicable\n\/\/ law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n\/\/ WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n\/\/ AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n\/\/ BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n\/\/ INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n\/\/ (2) Xilinx shall not be liable (whether in contract or tort,\n\/\/ including negligence, or under any other theory of\n\/\/ liability) for any loss or damage of any kind or nature\n\/\/ related to, arising under or in connection with these\n\/\/ materials, including for any direct, or any indirect,\n\/\/ special, incidental, or consequential loss or damage\n\/\/ (including loss of data, profits, goodwill, or any type of\n\/\/ loss or damage suffered as a result of any action brought\n\/\/ by a third party) even if such damage or loss was\n\/\/ reasonably foreseeable or Xilinx had been advised of the\n\/\/ possibility of the same.\n\/\/ \n\/\/ CRITICAL APPLICATIONS\n\/\/ Xilinx products are not designed or intended to be fail-\n\/\/ safe, or for use in any application requiring fail-safe\n\/\/ performance, such as life-support or safety devices or\n\/\/ systems, Class III medical devices, nuclear facilities,\n\/\/ applications related to the deployment of airbags, or any\n\/\/ other applications that could lead to death, personal\n\/\/ injury, or severe property or environmental damage\n\/\/ (individually and collectively, \"Critical\n\/\/ Applications\"). Customer assumes the sole risk and\n\/\/ liability of any use of Xilinx products in Critical\n\/\/ Applications, subject only to applicable laws and\n\/\/ regulations governing limitations on product liability.\n\/\/ \n\/\/ THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n\/\/ PART OF THIS FILE AT ALL TIMES.\n\/\/ \n\/\/ DO NOT MODIFY THIS FILE.\n\n\/\/ IP VLNV: xilinx.com:ip:blk_mem_gen:8.4\n\/\/ IP Revision: 4\n\n\/\/ The following must be inserted into your Verilog file for this\n\/\/ core to be instantiated. Change the instance name and port connections\n\/\/ (in parentheses) to your own signal names.\n\n\/\/----------- Begin Cut here for INSTANTIATION Template ---\/\/ INST_TAG\nvram your_instance_name (\n .clka(clka), \/\/ input wire clka\n .ena(ena), \/\/ input wire ena\n .wea(wea), \/\/ input wire [0 : 0] wea\n .addra(addra), \/\/ input wire [12 : 0] addra\n .dina(dina), \/\/ input wire [7 : 0] dina\n .douta(douta), \/\/ output wire [7 : 0] douta\n .clkb(clkb), \/\/ input wire clkb\n .enb(enb), \/\/ input wire enb\n .web(web), \/\/ input wire [0 : 0] web\n .addrb(addrb), \/\/ input wire [12 : 0] addrb\n .dinb(dinb), \/\/ input wire [7 : 0] dinb\n .doutb(doutb) \/\/ output wire [7 : 0] doutb\n);\n\/\/ INST_TAG_END ------ End INSTANTIATION Template ---------\n\n\/\/ You must compile the wrapper file vram.v when simulating\n\/\/ the core, vram. When compiling the wrapper file, be sure to\n\/\/ reference the Verilog simulation library.\n\n","avg_line_length":43.3506493506,"max_line_length":73,"alphanum_fraction":0.7186938286} {"size":3197,"ext":"veo","lang":"Verilog","max_stars_count":1.0,"content":"\/\/ (c) Copyright 1995-2019 Xilinx, Inc. All rights reserved.\n\/\/ \n\/\/ This file contains confidential and proprietary information\n\/\/ of Xilinx, Inc. and is protected under U.S. and\n\/\/ international copyright and other intellectual property\n\/\/ laws.\n\/\/ \n\/\/ DISCLAIMER\n\/\/ This disclaimer is not a license and does not grant any\n\/\/ rights to the materials distributed herewith. Except as\n\/\/ otherwise provided in a valid license issued to you by\n\/\/ Xilinx, and to the maximum extent permitted by applicable\n\/\/ law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n\/\/ WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n\/\/ AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n\/\/ BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n\/\/ INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n\/\/ (2) Xilinx shall not be liable (whether in contract or tort,\n\/\/ including negligence, or under any other theory of\n\/\/ liability) for any loss or damage of any kind or nature\n\/\/ related to, arising under or in connection with these\n\/\/ materials, including for any direct, or any indirect,\n\/\/ special, incidental, or consequential loss or damage\n\/\/ (including loss of data, profits, goodwill, or any type of\n\/\/ loss or damage suffered as a result of any action brought\n\/\/ by a third party) even if such damage or loss was\n\/\/ reasonably foreseeable or Xilinx had been advised of the\n\/\/ possibility of the same.\n\/\/ \n\/\/ CRITICAL APPLICATIONS\n\/\/ Xilinx products are not designed or intended to be fail-\n\/\/ safe, or for use in any application requiring fail-safe\n\/\/ performance, such as life-support or safety devices or\n\/\/ systems, Class III medical devices, nuclear facilities,\n\/\/ applications related to the deployment of airbags, or any\n\/\/ other applications that could lead to death, personal\n\/\/ injury, or severe property or environmental damage\n\/\/ (individually and collectively, \"Critical\n\/\/ Applications\"). Customer assumes the sole risk and\n\/\/ liability of any use of Xilinx products in Critical\n\/\/ Applications, subject only to applicable laws and\n\/\/ regulations governing limitations on product liability.\n\/\/ \n\/\/ THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n\/\/ PART OF THIS FILE AT ALL TIMES.\n\/\/ \n\/\/ DO NOT MODIFY THIS FILE.\n\n\/\/ IP VLNV: xilinx.com:ip:fifo_generator:13.2\n\/\/ IP Revision: 2\n\n\/\/ The following must be inserted into your Verilog file for this\n\/\/ core to be instantiated. Change the instance name and port connections\n\/\/ (in parentheses) to your own signal names.\n\n\/\/----------- Begin Cut here for INSTANTIATION Template ---\/\/ INST_TAG\nafifo_wr8x8192 your_instance_name (\n .wr_clk(wr_clk), \/\/ input wire wr_clk\n .rd_clk(rd_clk), \/\/ input wire rd_clk\n .din(din), \/\/ input wire [7 : 0] din\n .wr_en(wr_en), \/\/ input wire wr_en\n .rd_en(rd_en), \/\/ input wire rd_en\n .dout(dout), \/\/ output wire [7 : 0] dout\n .full(full), \/\/ output wire full\n .empty(empty) \/\/ output wire empty\n);\n\/\/ INST_TAG_END ------ End INSTANTIATION Template ---------\n\n\/\/ You must compile the wrapper file afifo_wr8x8192.v when simulating\n\/\/ the core, afifo_wr8x8192. When compiling the wrapper file, be sure to\n\/\/ reference the Verilog simulation library.\n\n","avg_line_length":43.7945205479,"max_line_length":73,"alphanum_fraction":0.7363152956} {"size":3137,"ext":"veo","lang":"Verilog","max_stars_count":null,"content":"\/\/ (c) Copyright 1995-2020 Xilinx, Inc. All rights reserved.\n\/\/ \n\/\/ This file contains confidential and proprietary information\n\/\/ of Xilinx, Inc. and is protected under U.S. and\n\/\/ international copyright and other intellectual property\n\/\/ laws.\n\/\/ \n\/\/ DISCLAIMER\n\/\/ This disclaimer is not a license and does not grant any\n\/\/ rights to the materials distributed herewith. Except as\n\/\/ otherwise provided in a valid license issued to you by\n\/\/ Xilinx, and to the maximum extent permitted by applicable\n\/\/ law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n\/\/ WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n\/\/ AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n\/\/ BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n\/\/ INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n\/\/ (2) Xilinx shall not be liable (whether in contract or tort,\n\/\/ including negligence, or under any other theory of\n\/\/ liability) for any loss or damage of any kind or nature\n\/\/ related to, arising under or in connection with these\n\/\/ materials, including for any direct, or any indirect,\n\/\/ special, incidental, or consequential loss or damage\n\/\/ (including loss of data, profits, goodwill, or any type of\n\/\/ loss or damage suffered as a result of any action brought\n\/\/ by a third party) even if such damage or loss was\n\/\/ reasonably foreseeable or Xilinx had been advised of the\n\/\/ possibility of the same.\n\/\/ \n\/\/ CRITICAL APPLICATIONS\n\/\/ Xilinx products are not designed or intended to be fail-\n\/\/ safe, or for use in any application requiring fail-safe\n\/\/ performance, such as life-support or safety devices or\n\/\/ systems, Class III medical devices, nuclear facilities,\n\/\/ applications related to the deployment of airbags, or any\n\/\/ other applications that could lead to death, personal\n\/\/ injury, or severe property or environmental damage\n\/\/ (individually and collectively, \"Critical\n\/\/ Applications\"). Customer assumes the sole risk and\n\/\/ liability of any use of Xilinx products in Critical\n\/\/ Applications, subject only to applicable laws and\n\/\/ regulations governing limitations on product liability.\n\/\/ \n\/\/ THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n\/\/ PART OF THIS FILE AT ALL TIMES.\n\/\/ \n\/\/ DO NOT MODIFY THIS FILE.\n\n\/\/ IP VLNV: xilinx.com:ip:dist_mem_gen:8.0\n\/\/ IP Revision: 13\n\n\/\/ The following must be inserted into your Verilog file for this\n\/\/ core to be instantiated. Change the instance name and port connections\n\/\/ (in parentheses) to your own signal names.\n\n\/\/----------- Begin Cut here for INSTANTIATION Template ---\/\/ INST_TAG\ndist_mem_gen_1 your_instance_name (\n .a(a), \/\/ input wire [7 : 0] a\n .d(d), \/\/ input wire [31 : 0] d\n .dpra(dpra), \/\/ input wire [7 : 0] dpra\n .clk(clk), \/\/ input wire clk\n .we(we), \/\/ input wire we\n .spo(spo), \/\/ output wire [31 : 0] spo\n .dpo(dpo) \/\/ output wire [31 : 0] dpo\n);\n\/\/ INST_TAG_END ------ End INSTANTIATION Template ---------\n\n\/\/ You must compile the wrapper file dist_mem_gen_1.v when simulating\n\/\/ the core, dist_mem_gen_1. When compiling the wrapper file, be sure to\n\/\/ reference the Verilog simulation library.\n\n","avg_line_length":43.5694444444,"max_line_length":73,"alphanum_fraction":0.7293592604} {"size":4426,"ext":"veo","lang":"Verilog","max_stars_count":8.0,"content":"\/*******************************************************************************\n* This file is owned and controlled by Xilinx and must be used solely *\n* for design, simulation, implementation and creation of design files *\n* limited to Xilinx devices or technologies. Use with non-Xilinx *\n* devices or technologies is expressly prohibited and immediately *\n* terminates your license. *\n* *\n* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION \"AS IS\" SOLELY *\n* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY *\n* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE *\n* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS *\n* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY *\n* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY *\n* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY *\n* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *\n* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *\n* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *\n* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *\n* PARTICULAR PURPOSE. *\n* *\n* Xilinx products are not intended for use in life support appliances, *\n* devices, or systems. Use in such applications are expressly *\n* prohibited. *\n* *\n* (c) Copyright 1995-2019 Xilinx, Inc. *\n* All rights reserved. *\n*******************************************************************************\/\n\n\/*******************************************************************************\n* Generated from core with identifier: xilinx.com:ip:floating_point:5.0 *\n* *\n* The Xilinx Floating-Point Operator is capable of being configured to *\n* provide a range of floating-point operations. The core offers *\n* addition, subtraction, multiplication, division, square-root, compare *\n* and conversion operations. High-speed, with single-cycle throughput *\n* is provided at a wide range of wordlengths that includes both single *\n* and double precision. Embedded multipliers or XtremeDSP slices can be *\n* used with certain operations. *\n*******************************************************************************\/\n\n\/\/ Interfaces:\n\/\/ a_intf\n\/\/ clk_intf\n\/\/ sclr_intf\n\/\/ ce_intf\n\/\/ b_intf\n\/\/ a_negate_intf\n\/\/ b_negate_intf\n\/\/ operation_intf\n\/\/ a_nd_intf\n\/\/ a_rfd_intf\n\/\/ b_nd_intf\n\/\/ b_rfd_intf\n\/\/ operation_nd_intf\n\/\/ operation_rfd_intf\n\/\/ aclr_intf\n\/\/ result_intf\n\/\/ status_intf\n\/\/ exception_intf\n\/\/ underflow_intf\n\/\/ overflow_intf\n\/\/ invalid_op_intf\n\/\/ inexact_intf\n\/\/ divide_by_zero_intf\n\/\/ rdy_intf\n\/\/ cts_intf\n\n\/\/ The following must be inserted into your Verilog file for this\n\/\/ core to be instantiated. Change the instance name and port connections\n\/\/ (in parentheses) to your own signal names.\n\n\/\/----------- Begin Cut here for INSTANTIATION Template ---\/\/ INST_TAG\naccum your_instance_name (\n .a(a), \/\/ input [15 : 0] a\n .b(b), \/\/ input [15 : 0] b\n .operation_nd(operation_nd), \/\/ input operation_nd\n .operation_rfd(operation_rfd), \/\/ output operation_rfd\n .clk(clk), \/\/ input clk\n .result(result), \/\/ output [15 : 0] result\n .rdy(rdy) \/\/ output rdy\n);\n\/\/ INST_TAG_END ------ End INSTANTIATION Template ---------\n\n\/\/ You must compile the wrapper file accum.v when simulating\n\/\/ the core, accum. When compiling the wrapper file, be sure to\n\/\/ reference the XilinxCoreLib Verilog simulation library. For detailed\n\/\/ instructions, please refer to the \"CORE Generator Help\".\n\n","avg_line_length":49.7303370787,"max_line_length":80,"alphanum_fraction":0.5318572074} {"size":3392,"ext":"veo","lang":"Verilog","max_stars_count":312.0,"content":"\/\/ (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.\n\/\/ \n\/\/ This file contains confidential and proprietary information\n\/\/ of Xilinx, Inc. and is protected under U.S. and\n\/\/ international copyright and other intellectual property\n\/\/ laws.\n\/\/ \n\/\/ DISCLAIMER\n\/\/ This disclaimer is not a license and does not grant any\n\/\/ rights to the materials distributed herewith. Except as\n\/\/ otherwise provided in a valid license issued to you by\n\/\/ Xilinx, and to the maximum extent permitted by applicable\n\/\/ law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n\/\/ WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n\/\/ AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n\/\/ BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n\/\/ INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n\/\/ (2) Xilinx shall not be liable (whether in contract or tort,\n\/\/ including negligence, or under any other theory of\n\/\/ liability) for any loss or damage of any kind or nature\n\/\/ related to, arising under or in connection with these\n\/\/ materials, including for any direct, or any indirect,\n\/\/ special, incidental, or consequential loss or damage\n\/\/ (including loss of data, profits, goodwill, or any type of\n\/\/ loss or damage suffered as a result of any action brought\n\/\/ by a third party) even if such damage or loss was\n\/\/ reasonably foreseeable or Xilinx had been advised of the\n\/\/ possibility of the same.\n\/\/ \n\/\/ CRITICAL APPLICATIONS\n\/\/ Xilinx products are not designed or intended to be fail-\n\/\/ safe, or for use in any application requiring fail-safe\n\/\/ performance, such as life-support or safety devices or\n\/\/ systems, Class III medical devices, nuclear facilities,\n\/\/ applications related to the deployment of airbags, or any\n\/\/ other applications that could lead to death, personal\n\/\/ injury, or severe property or environmental damage\n\/\/ (individually and collectively, \"Critical\n\/\/ Applications\"). Customer assumes the sole risk and\n\/\/ liability of any use of Xilinx products in Critical\n\/\/ Applications, subject only to applicable laws and\n\/\/ regulations governing limitations on product liability.\n\/\/ \n\/\/ THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n\/\/ PART OF THIS FILE AT ALL TIMES.\n\/\/ \n\/\/ DO NOT MODIFY THIS FILE.\n\n\/\/ IP VLNV: xilinx.com:ip:fifo_generator:12.0\n\/\/ IP Revision: 3\n\n\/\/ The following must be inserted into your Verilog file for this\n\/\/ core to be instantiated. Change the instance name and port connections\n\/\/ (in parentheses) to your own signal names.\n\n\/\/----------- Begin Cut here for INSTANTIATION Template ---\/\/ INST_TAG\nelink2_top_fifo_103x32_write_0 your_instance_name (\n .rst(rst), \/\/ input wire rst\n .wr_clk(wr_clk), \/\/ input wire wr_clk\n .rd_clk(rd_clk), \/\/ input wire rd_clk\n .din(din), \/\/ input wire [102 : 0] din\n .wr_en(wr_en), \/\/ input wire wr_en\n .rd_en(rd_en), \/\/ input wire rd_en\n .dout(dout), \/\/ output wire [102 : 0] dout\n .full(full), \/\/ output wire full\n .empty(empty), \/\/ output wire empty\n .prog_full(prog_full) \/\/ output wire prog_full\n);\n\/\/ INST_TAG_END ------ End INSTANTIATION Template ---------\n\n\/\/ You must compile the wrapper file elink2_top_fifo_103x32_write_0.v when simulating\n\/\/ the core, elink2_top_fifo_103x32_write_0. When compiling the wrapper file, be sure to\n\/\/ reference the Verilog simulation library.\n\n","avg_line_length":45.2266666667,"max_line_length":88,"alphanum_fraction":0.7255306604} {"size":2966,"ext":"veo","lang":"Verilog","max_stars_count":null,"content":"\/\/ (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.\n\/\/ \n\/\/ This file contains confidential and proprietary information\n\/\/ of Xilinx, Inc. and is protected under U.S. and\n\/\/ international copyright and other intellectual property\n\/\/ laws.\n\/\/ \n\/\/ DISCLAIMER\n\/\/ This disclaimer is not a license and does not grant any\n\/\/ rights to the materials distributed herewith. Except as\n\/\/ otherwise provided in a valid license issued to you by\n\/\/ Xilinx, and to the maximum extent permitted by applicable\n\/\/ law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n\/\/ WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n\/\/ AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n\/\/ BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n\/\/ INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n\/\/ (2) Xilinx shall not be liable (whether in contract or tort,\n\/\/ including negligence, or under any other theory of\n\/\/ liability) for any loss or damage of any kind or nature\n\/\/ related to, arising under or in connection with these\n\/\/ materials, including for any direct, or any indirect,\n\/\/ special, incidental, or consequential loss or damage\n\/\/ (including loss of data, profits, goodwill, or any type of\n\/\/ loss or damage suffered as a result of any action brought\n\/\/ by a third party) even if such damage or loss was\n\/\/ reasonably foreseeable or Xilinx had been advised of the\n\/\/ possibility of the same.\n\/\/ \n\/\/ CRITICAL APPLICATIONS\n\/\/ Xilinx products are not designed or intended to be fail-\n\/\/ safe, or for use in any application requiring fail-safe\n\/\/ performance, such as life-support or safety devices or\n\/\/ systems, Class III medical devices, nuclear facilities,\n\/\/ applications related to the deployment of airbags, or any\n\/\/ other applications that could lead to death, personal\n\/\/ injury, or severe property or environmental damage\n\/\/ (individually and collectively, \"Critical\n\/\/ Applications\"). Customer assumes the sole risk and\n\/\/ liability of any use of Xilinx products in Critical\n\/\/ Applications, subject only to applicable laws and\n\/\/ regulations governing limitations on product liability.\n\/\/ \n\/\/ THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n\/\/ PART OF THIS FILE AT ALL TIMES.\n\/\/ \n\/\/ DO NOT MODIFY THIS FILE.\n\n\/\/ IP VLNV: xilinx.com:ip:c_shift_ram:12.0\n\/\/ IP Revision: 11\n\n\/\/ The following must be inserted into your Verilog file for this\n\/\/ core to be instantiated. Change the instance name and port connections\n\/\/ (in parentheses) to your own signal names.\n\n\/\/----------- Begin Cut here for INSTANTIATION Template ---\/\/ INST_TAG\nc_shift_ram_6 your_instance_name (\n .D(D), \/\/ input wire [23 : 0] D\n .CLK(CLK), \/\/ input wire CLK\n .Q(Q) \/\/ output wire [23 : 0] Q\n);\n\/\/ INST_TAG_END ------ End INSTANTIATION Template ---------\n\n\/\/ You must compile the wrapper file c_shift_ram_6.v when simulating\n\/\/ the core, c_shift_ram_6. When compiling the wrapper file, be sure to\n\/\/ reference the Verilog simulation library.\n\n","avg_line_length":43.6176470588,"max_line_length":73,"alphanum_fraction":0.7434254889} {"size":3392,"ext":"veo","lang":"Verilog","max_stars_count":312.0,"content":"\/\/ (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.\n\/\/ \n\/\/ This file contains confidential and proprietary information\n\/\/ of Xilinx, Inc. and is protected under U.S. and\n\/\/ international copyright and other intellectual property\n\/\/ laws.\n\/\/ \n\/\/ DISCLAIMER\n\/\/ This disclaimer is not a license and does not grant any\n\/\/ rights to the materials distributed herewith. Except as\n\/\/ otherwise provided in a valid license issued to you by\n\/\/ Xilinx, and to the maximum extent permitted by applicable\n\/\/ law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n\/\/ WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n\/\/ AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n\/\/ BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n\/\/ INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n\/\/ (2) Xilinx shall not be liable (whether in contract or tort,\n\/\/ including negligence, or under any other theory of\n\/\/ liability) for any loss or damage of any kind or nature\n\/\/ related to, arising under or in connection with these\n\/\/ materials, including for any direct, or any indirect,\n\/\/ special, incidental, or consequential loss or damage\n\/\/ (including loss of data, profits, goodwill, or any type of\n\/\/ loss or damage suffered as a result of any action brought\n\/\/ by a third party) even if such damage or loss was\n\/\/ reasonably foreseeable or Xilinx had been advised of the\n\/\/ possibility of the same.\n\/\/ \n\/\/ CRITICAL APPLICATIONS\n\/\/ Xilinx products are not designed or intended to be fail-\n\/\/ safe, or for use in any application requiring fail-safe\n\/\/ performance, such as life-support or safety devices or\n\/\/ systems, Class III medical devices, nuclear facilities,\n\/\/ applications related to the deployment of airbags, or any\n\/\/ other applications that could lead to death, personal\n\/\/ injury, or severe property or environmental damage\n\/\/ (individually and collectively, \"Critical\n\/\/ Applications\"). Customer assumes the sole risk and\n\/\/ liability of any use of Xilinx products in Critical\n\/\/ Applications, subject only to applicable laws and\n\/\/ regulations governing limitations on product liability.\n\/\/ \n\/\/ THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n\/\/ PART OF THIS FILE AT ALL TIMES.\n\/\/ \n\/\/ DO NOT MODIFY THIS FILE.\n\n\/\/ IP VLNV: xilinx.com:ip:fifo_generator:12.0\n\/\/ IP Revision: 3\n\n\/\/ The following must be inserted into your Verilog file for this\n\/\/ core to be instantiated. Change the instance name and port connections\n\/\/ (in parentheses) to your own signal names.\n\n\/\/----------- Begin Cut here for INSTANTIATION Template ---\/\/ INST_TAG\nelink2_top_fifo_103x16_rdreq_0 your_instance_name (\n .rst(rst), \/\/ input wire rst\n .wr_clk(wr_clk), \/\/ input wire wr_clk\n .rd_clk(rd_clk), \/\/ input wire rd_clk\n .din(din), \/\/ input wire [102 : 0] din\n .wr_en(wr_en), \/\/ input wire wr_en\n .rd_en(rd_en), \/\/ input wire rd_en\n .dout(dout), \/\/ output wire [102 : 0] dout\n .full(full), \/\/ output wire full\n .empty(empty), \/\/ output wire empty\n .prog_full(prog_full) \/\/ output wire prog_full\n);\n\/\/ INST_TAG_END ------ End INSTANTIATION Template ---------\n\n\/\/ You must compile the wrapper file elink2_top_fifo_103x16_rdreq_0.v when simulating\n\/\/ the core, elink2_top_fifo_103x16_rdreq_0. When compiling the wrapper file, be sure to\n\/\/ reference the Verilog simulation library.\n\n","avg_line_length":45.2266666667,"max_line_length":88,"alphanum_fraction":0.7255306604} {"size":4086,"ext":"veo","lang":"Verilog","max_stars_count":1.0,"content":"\/\/ (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.\n\/\/ \n\/\/ This file contains confidential and proprietary information\n\/\/ of Xilinx, Inc. and is protected under U.S. and\n\/\/ international copyright and other intellectual property\n\/\/ laws.\n\/\/ \n\/\/ DISCLAIMER\n\/\/ This disclaimer is not a license and does not grant any\n\/\/ rights to the materials distributed herewith. Except as\n\/\/ otherwise provided in a valid license issued to you by\n\/\/ Xilinx, and to the maximum extent permitted by applicable\n\/\/ law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n\/\/ WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n\/\/ AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n\/\/ BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n\/\/ INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n\/\/ (2) Xilinx shall not be liable (whether in contract or tort,\n\/\/ including negligence, or under any other theory of\n\/\/ liability) for any loss or damage of any kind or nature\n\/\/ related to, arising under or in connection with these\n\/\/ materials, including for any direct, or any indirect,\n\/\/ special, incidental, or consequential loss or damage\n\/\/ (including loss of data, profits, goodwill, or any type of\n\/\/ loss or damage suffered as a result of any action brought\n\/\/ by a third party) even if such damage or loss was\n\/\/ reasonably foreseeable or Xilinx had been advised of the\n\/\/ possibility of the same.\n\/\/ \n\/\/ CRITICAL APPLICATIONS\n\/\/ Xilinx products are not designed or intended to be fail-\n\/\/ safe, or for use in any application requiring fail-safe\n\/\/ performance, such as life-support or safety devices or\n\/\/ systems, Class III medical devices, nuclear facilities,\n\/\/ applications related to the deployment of airbags, or any\n\/\/ other applications that could lead to death, personal\n\/\/ injury, or severe property or environmental damage\n\/\/ (individually and collectively, \"Critical\n\/\/ Applications\"). Customer assumes the sole risk and\n\/\/ liability of any use of Xilinx products in Critical\n\/\/ Applications, subject only to applicable laws and\n\/\/ regulations governing limitations on product liability.\n\/\/ \n\/\/ THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n\/\/ PART OF THIS FILE AT ALL TIMES.\n\/\/ \n\/\/ DO NOT MODIFY THIS FILE.\n\n\/\/ IP VLNV: www.alinx.com.cn:user:alinx_ov5640:1.4\n\/\/ IP Revision: 3\n\n\/\/ The following must be inserted into your Verilog file for this\n\/\/ core to be instantiated. Change the instance name and port connections\n\/\/ (in parentheses) to your own signal names.\n\n\/\/----------- Begin Cut here for INSTANTIATION Template ---\/\/ INST_TAG\nsystem_alinx_ov5640_0_0 your_instance_name (\n .cmos_xclk(cmos_xclk), \/\/ input wire cmos_xclk\n .cmos_scl(cmos_scl), \/\/ inout wire cmos_scl\n .cmos_sda(cmos_sda), \/\/ inout wire cmos_sda\n .cmos_vsync(cmos_vsync), \/\/ input wire cmos_vsync\n .cmos_href(cmos_href), \/\/ input wire cmos_href\n .cmos_pclk(cmos_pclk), \/\/ input wire cmos_pclk\n .cmos_d(cmos_d), \/\/ input wire [9 : 0] cmos_d\n .cmos_reset(cmos_reset), \/\/ output wire cmos_reset\n .aclk(aclk), \/\/ input wire aclk\n .aclken(aclken), \/\/ input wire aclken\n .aresetn(aresetn), \/\/ input wire aresetn\n .m_axis_video_tdata(m_axis_video_tdata), \/\/ output wire [31 : 0] m_axis_video_tdata\n .m_axis_video_tvalid(m_axis_video_tvalid), \/\/ output wire m_axis_video_tvalid\n .m_axis_video_tready(m_axis_video_tready), \/\/ input wire m_axis_video_tready\n .m_axis_video_tuser(m_axis_video_tuser), \/\/ output wire m_axis_video_tuser\n .m_axis_video_tlast(m_axis_video_tlast), \/\/ output wire m_axis_video_tlast\n .m_axis_video_tkeep(m_axis_video_tkeep), \/\/ output wire [3 : 0] m_axis_video_tkeep\n .fid(fid), \/\/ output wire fid\n .axis_enable(axis_enable) \/\/ input wire axis_enable\n);\n\/\/ INST_TAG_END ------ End INSTANTIATION Template ---------\n\n","avg_line_length":51.075,"max_line_length":88,"alphanum_fraction":0.6948115516} {"size":3148,"ext":"veo","lang":"Verilog","max_stars_count":null,"content":"\/\/ (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.\n\/\/ \n\/\/ This file contains confidential and proprietary information\n\/\/ of Xilinx, Inc. and is protected under U.S. and\n\/\/ international copyright and other intellectual property\n\/\/ laws.\n\/\/ \n\/\/ DISCLAIMER\n\/\/ This disclaimer is not a license and does not grant any\n\/\/ rights to the materials distributed herewith. Except as\n\/\/ otherwise provided in a valid license issued to you by\n\/\/ Xilinx, and to the maximum extent permitted by applicable\n\/\/ law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n\/\/ WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n\/\/ AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n\/\/ BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n\/\/ INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n\/\/ (2) Xilinx shall not be liable (whether in contract or tort,\n\/\/ including negligence, or under any other theory of\n\/\/ liability) for any loss or damage of any kind or nature\n\/\/ related to, arising under or in connection with these\n\/\/ materials, including for any direct, or any indirect,\n\/\/ special, incidental, or consequential loss or damage\n\/\/ (including loss of data, profits, goodwill, or any type of\n\/\/ loss or damage suffered as a result of any action brought\n\/\/ by a third party) even if such damage or loss was\n\/\/ reasonably foreseeable or Xilinx had been advised of the\n\/\/ possibility of the same.\n\/\/ \n\/\/ CRITICAL APPLICATIONS\n\/\/ Xilinx products are not designed or intended to be fail-\n\/\/ safe, or for use in any application requiring fail-safe\n\/\/ performance, such as life-support or safety devices or\n\/\/ systems, Class III medical devices, nuclear facilities,\n\/\/ applications related to the deployment of airbags, or any\n\/\/ other applications that could lead to death, personal\n\/\/ injury, or severe property or environmental damage\n\/\/ (individually and collectively, \"Critical\n\/\/ Applications\"). Customer assumes the sole risk and\n\/\/ liability of any use of Xilinx products in Critical\n\/\/ Applications, subject only to applicable laws and\n\/\/ regulations governing limitations on product liability.\n\/\/ \n\/\/ THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n\/\/ PART OF THIS FILE AT ALL TIMES.\n\/\/ \n\/\/ DO NOT MODIFY THIS FILE.\n\n\/\/ IP VLNV: xilinx.com:ip:blk_mem_gen:8.4\n\/\/ IP Revision: 1\n\n\/\/ The following must be inserted into your Verilog file for this\n\/\/ core to be instantiated. Change the instance name and port connections\n\/\/ (in parentheses) to your own signal names.\n\n\/\/----------- Begin Cut here for INSTANTIATION Template ---\/\/ INST_TAG\nip1_wm_ram your_instance_name (\n .clka(clka), \/\/ input wire clka\n .wea(wea), \/\/ input wire [0 : 0] wea\n .addra(addra), \/\/ input wire [7 : 0] addra\n .dina(dina), \/\/ input wire [15 : 0] dina\n .clkb(clkb), \/\/ input wire clkb\n .addrb(addrb), \/\/ input wire [7 : 0] addrb\n .doutb(doutb) \/\/ output wire [15 : 0] doutb\n);\n\/\/ INST_TAG_END ------ End INSTANTIATION Template ---------\n\n\/\/ You must compile the wrapper file ip1_wm_ram.v when simulating\n\/\/ the core, ip1_wm_ram. When compiling the wrapper file, be sure to\n\/\/ reference the Verilog simulation library.\n\n","avg_line_length":43.7222222222,"max_line_length":73,"alphanum_fraction":0.7341168996} {"size":4165,"ext":"veo","lang":"Verilog","max_stars_count":16.0,"content":"\/\/ (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.\n\/\/ \n\/\/ This file contains confidential and proprietary information\n\/\/ of Xilinx, Inc. and is protected under U.S. and\n\/\/ international copyright and other intellectual property\n\/\/ laws.\n\/\/ \n\/\/ DISCLAIMER\n\/\/ This disclaimer is not a license and does not grant any\n\/\/ rights to the materials distributed herewith. Except as\n\/\/ otherwise provided in a valid license issued to you by\n\/\/ Xilinx, and to the maximum extent permitted by applicable\n\/\/ law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n\/\/ WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n\/\/ AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n\/\/ BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n\/\/ INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n\/\/ (2) Xilinx shall not be liable (whether in contract or tort,\n\/\/ including negligence, or under any other theory of\n\/\/ liability) for any loss or damage of any kind or nature\n\/\/ related to, arising under or in connection with these\n\/\/ materials, including for any direct, or any indirect,\n\/\/ special, incidental, or consequential loss or damage\n\/\/ (including loss of data, profits, goodwill, or any type of\n\/\/ loss or damage suffered as a result of any action brought\n\/\/ by a third party) even if such damage or loss was\n\/\/ reasonably foreseeable or Xilinx had been advised of the\n\/\/ possibility of the same.\n\/\/ \n\/\/ CRITICAL APPLICATIONS\n\/\/ Xilinx products are not designed or intended to be fail-\n\/\/ safe, or for use in any application requiring fail-safe\n\/\/ performance, such as life-support or safety devices or\n\/\/ systems, Class III medical devices, nuclear facilities,\n\/\/ applications related to the deployment of airbags, or any\n\/\/ other applications that could lead to death, personal\n\/\/ injury, or severe property or environmental damage\n\/\/ (individually and collectively, \"Critical\n\/\/ Applications\"). Customer assumes the sole risk and\n\/\/ liability of any use of Xilinx products in Critical\n\/\/ Applications, subject only to applicable laws and\n\/\/ regulations governing limitations on product liability.\n\/\/ \n\/\/ THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n\/\/ PART OF THIS FILE AT ALL TIMES.\n\/\/ \n\/\/ DO NOT MODIFY THIS FILE.\n\n\/\/ IP VLNV: digilentinc.com:ip:pmod_bridge:1.0\n\/\/ IP Revision: 6\n\n\/\/ The following must be inserted into your Verilog file for this\n\/\/ core to be instantiated. Change the instance name and port connections\n\/\/ (in parentheses) to your own signal names.\n\n\/\/----------- Begin Cut here for INSTANTIATION Template ---\/\/ INST_TAG\nPmodAD1_pmod_bridge_0_0 your_instance_name (\n .in0_I(in0_I), \/\/ output wire in0_I\n .in1_I(in1_I), \/\/ output wire in1_I\n .in2_I(in2_I), \/\/ output wire in2_I\n .in3_I(in3_I), \/\/ output wire in3_I\n .in0_O(in0_O), \/\/ input wire in0_O\n .in1_O(in1_O), \/\/ input wire in1_O\n .in2_O(in2_O), \/\/ input wire in2_O\n .in3_O(in3_O), \/\/ input wire in3_O\n .in0_T(in0_T), \/\/ input wire in0_T\n .in1_T(in1_T), \/\/ input wire in1_T\n .in2_T(in2_T), \/\/ input wire in2_T\n .in3_T(in3_T), \/\/ input wire in3_T\n .out0_I(out0_I), \/\/ input wire out0_I\n .out1_I(out1_I), \/\/ input wire out1_I\n .out2_I(out2_I), \/\/ input wire out2_I\n .out3_I(out3_I), \/\/ input wire out3_I\n .out4_I(out4_I), \/\/ input wire out4_I\n .out5_I(out5_I), \/\/ input wire out5_I\n .out6_I(out6_I), \/\/ input wire out6_I\n .out7_I(out7_I), \/\/ input wire out7_I\n .out0_O(out0_O), \/\/ output wire out0_O\n .out1_O(out1_O), \/\/ output wire out1_O\n .out2_O(out2_O), \/\/ output wire out2_O\n .out3_O(out3_O), \/\/ output wire out3_O\n .out4_O(out4_O), \/\/ output wire out4_O\n .out5_O(out5_O), \/\/ output wire out5_O\n .out6_O(out6_O), \/\/ output wire out6_O\n .out7_O(out7_O), \/\/ output wire out7_O\n .out0_T(out0_T), \/\/ output wire out0_T\n .out1_T(out1_T), \/\/ output wire out1_T\n .out2_T(out2_T), \/\/ output wire out2_T\n .out3_T(out3_T), \/\/ output wire out3_T\n .out4_T(out4_T), \/\/ output wire out4_T\n .out5_T(out5_T), \/\/ output wire out5_T\n .out6_T(out6_T), \/\/ output wire out6_T\n .out7_T(out7_T) \/\/ output wire out7_T\n);\n\/\/ INST_TAG_END ------ End INSTANTIATION Template ---------\n\n","avg_line_length":42.9381443299,"max_line_length":73,"alphanum_fraction":0.7150060024} {"size":3292,"ext":"veo","lang":"Verilog","max_stars_count":7.0,"content":"\/\/ (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.\n\/\/ \n\/\/ This file contains confidential and proprietary information\n\/\/ of Xilinx, Inc. and is protected under U.S. and\n\/\/ international copyright and other intellectual property\n\/\/ laws.\n\/\/ \n\/\/ DISCLAIMER\n\/\/ This disclaimer is not a license and does not grant any\n\/\/ rights to the materials distributed herewith. Except as\n\/\/ otherwise provided in a valid license issued to you by\n\/\/ Xilinx, and to the maximum extent permitted by applicable\n\/\/ law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n\/\/ WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n\/\/ AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n\/\/ BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n\/\/ INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n\/\/ (2) Xilinx shall not be liable (whether in contract or tort,\n\/\/ including negligence, or under any other theory of\n\/\/ liability) for any loss or damage of any kind or nature\n\/\/ related to, arising under or in connection with these\n\/\/ materials, including for any direct, or any indirect,\n\/\/ special, incidental, or consequential loss or damage\n\/\/ (including loss of data, profits, goodwill, or any type of\n\/\/ loss or damage suffered as a result of any action brought\n\/\/ by a third party) even if such damage or loss was\n\/\/ reasonably foreseeable or Xilinx had been advised of the\n\/\/ possibility of the same.\n\/\/ \n\/\/ CRITICAL APPLICATIONS\n\/\/ Xilinx products are not designed or intended to be fail-\n\/\/ safe, or for use in any application requiring fail-safe\n\/\/ performance, such as life-support or safety devices or\n\/\/ systems, Class III medical devices, nuclear facilities,\n\/\/ applications related to the deployment of airbags, or any\n\/\/ other applications that could lead to death, personal\n\/\/ injury, or severe property or environmental damage\n\/\/ (individually and collectively, \"Critical\n\/\/ Applications\"). Customer assumes the sole risk and\n\/\/ liability of any use of Xilinx products in Critical\n\/\/ Applications, subject only to applicable laws and\n\/\/ regulations governing limitations on product liability.\n\/\/ \n\/\/ THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n\/\/ PART OF THIS FILE AT ALL TIMES.\n\/\/ \n\/\/ DO NOT MODIFY THIS FILE.\n\n\/\/ IP VLNV: xilinx.com:ip:cordic:6.0\n\/\/ IP Revision: 10\n\n\/\/ The following must be inserted into your Verilog file for this\n\/\/ core to be instantiated. Change the instance name and port connections\n\/\/ (in parentheses) to your own signal names.\n\n\/\/----------- Begin Cut here for INSTANTIATION Template ---\/\/ INST_TAG\ncordic_atan your_instance_name (\n .aclk(aclk), \/\/ input wire aclk\n .s_axis_cartesian_tvalid(s_axis_cartesian_tvalid), \/\/ input wire s_axis_cartesian_tvalid\n .s_axis_cartesian_tdata(s_axis_cartesian_tdata), \/\/ input wire [63 : 0] s_axis_cartesian_tdata\n .m_axis_dout_tvalid(m_axis_dout_tvalid), \/\/ output wire m_axis_dout_tvalid\n .m_axis_dout_tdata(m_axis_dout_tdata) \/\/ output wire [31 : 0] m_axis_dout_tdata\n);\n\/\/ INST_TAG_END ------ End INSTANTIATION Template ---------\n\n\/\/ You must compile the wrapper file cordic_atan.v when simulating\n\/\/ the core, cordic_atan. When compiling the wrapper file, be sure to\n\/\/ reference the Verilog simulation library.\n\n","avg_line_length":47.0285714286,"max_line_length":99,"alphanum_fraction":0.7439246659} {"size":2964,"ext":"veo","lang":"Verilog","max_stars_count":22.0,"content":"\/\/ (c) Copyright 1995-2019 Xilinx, Inc. All rights reserved.\n\/\/ \n\/\/ This file contains confidential and proprietary information\n\/\/ of Xilinx, Inc. and is protected under U.S. and\n\/\/ international copyright and other intellectual property\n\/\/ laws.\n\/\/ \n\/\/ DISCLAIMER\n\/\/ This disclaimer is not a license and does not grant any\n\/\/ rights to the materials distributed herewith. Except as\n\/\/ otherwise provided in a valid license issued to you by\n\/\/ Xilinx, and to the maximum extent permitted by applicable\n\/\/ law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n\/\/ WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n\/\/ AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n\/\/ BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n\/\/ INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n\/\/ (2) Xilinx shall not be liable (whether in contract or tort,\n\/\/ including negligence, or under any other theory of\n\/\/ liability) for any loss or damage of any kind or nature\n\/\/ related to, arising under or in connection with these\n\/\/ materials, including for any direct, or any indirect,\n\/\/ special, incidental, or consequential loss or damage\n\/\/ (including loss of data, profits, goodwill, or any type of\n\/\/ loss or damage suffered as a result of any action brought\n\/\/ by a third party) even if such damage or loss was\n\/\/ reasonably foreseeable or Xilinx had been advised of the\n\/\/ possibility of the same.\n\/\/ \n\/\/ CRITICAL APPLICATIONS\n\/\/ Xilinx products are not designed or intended to be fail-\n\/\/ safe, or for use in any application requiring fail-safe\n\/\/ performance, such as life-support or safety devices or\n\/\/ systems, Class III medical devices, nuclear facilities,\n\/\/ applications related to the deployment of airbags, or any\n\/\/ other applications that could lead to death, personal\n\/\/ injury, or severe property or environmental damage\n\/\/ (individually and collectively, \"Critical\n\/\/ Applications\"). Customer assumes the sole risk and\n\/\/ liability of any use of Xilinx products in Critical\n\/\/ Applications, subject only to applicable laws and\n\/\/ regulations governing limitations on product liability.\n\/\/ \n\/\/ THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n\/\/ PART OF THIS FILE AT ALL TIMES.\n\/\/ \n\/\/ DO NOT MODIFY THIS FILE.\n\n\/\/ IP VLNV: xilinx.com:ip:blk_mem_gen:8.4\n\/\/ IP Revision: 1\n\n\/\/ The following must be inserted into your Verilog file for this\n\/\/ core to be instantiated. Change the instance name and port connections\n\/\/ (in parentheses) to your own signal names.\n\n\/\/----------- Begin Cut here for INSTANTIATION Template ---\/\/ INST_TAG\nprgrom your_instance_name (\n .clka(clka), \/\/ input wire clka\n .addra(addra), \/\/ input wire [13 : 0] addra\n .douta(douta) \/\/ output wire [31 : 0] douta\n);\n\/\/ INST_TAG_END ------ End INSTANTIATION Template ---------\n\n\/\/ You must compile the wrapper file prgrom.v when simulating\n\/\/ the core, prgrom. When compiling the wrapper file, be sure to\n\/\/ reference the Verilog simulation library.\n\n","avg_line_length":43.5882352941,"max_line_length":73,"alphanum_fraction":0.7452766532} {"size":3058,"ext":"veo","lang":"Verilog","max_stars_count":null,"content":"\/\/ (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.\n\/\/ \n\/\/ This file contains confidential and proprietary information\n\/\/ of Xilinx, Inc. and is protected under U.S. and\n\/\/ international copyright and other intellectual property\n\/\/ laws.\n\/\/ \n\/\/ DISCLAIMER\n\/\/ This disclaimer is not a license and does not grant any\n\/\/ rights to the materials distributed herewith. Except as\n\/\/ otherwise provided in a valid license issued to you by\n\/\/ Xilinx, and to the maximum extent permitted by applicable\n\/\/ law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n\/\/ WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n\/\/ AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n\/\/ BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n\/\/ INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n\/\/ (2) Xilinx shall not be liable (whether in contract or tort,\n\/\/ including negligence, or under any other theory of\n\/\/ liability) for any loss or damage of any kind or nature\n\/\/ related to, arising under or in connection with these\n\/\/ materials, including for any direct, or any indirect,\n\/\/ special, incidental, or consequential loss or damage\n\/\/ (including loss of data, profits, goodwill, or any type of\n\/\/ loss or damage suffered as a result of any action brought\n\/\/ by a third party) even if such damage or loss was\n\/\/ reasonably foreseeable or Xilinx had been advised of the\n\/\/ possibility of the same.\n\/\/ \n\/\/ CRITICAL APPLICATIONS\n\/\/ Xilinx products are not designed or intended to be fail-\n\/\/ safe, or for use in any application requiring fail-safe\n\/\/ performance, such as life-support or safety devices or\n\/\/ systems, Class III medical devices, nuclear facilities,\n\/\/ applications related to the deployment of airbags, or any\n\/\/ other applications that could lead to death, personal\n\/\/ injury, or severe property or environmental damage\n\/\/ (individually and collectively, \"Critical\n\/\/ Applications\"). Customer assumes the sole risk and\n\/\/ liability of any use of Xilinx products in Critical\n\/\/ Applications, subject only to applicable laws and\n\/\/ regulations governing limitations on product liability.\n\/\/ \n\/\/ THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n\/\/ PART OF THIS FILE AT ALL TIMES.\n\/\/ \n\/\/ DO NOT MODIFY THIS FILE.\n\n\/\/ IP VLNV: xilinx.com:ip:blk_mem_gen:8.4\n\/\/ IP Revision: 1\n\n\/\/ The following must be inserted into your Verilog file for this\n\/\/ core to be instantiated. Change the instance name and port connections\n\/\/ (in parentheses) to your own signal names.\n\n\/\/----------- Begin Cut here for INSTANTIATION Template ---\/\/ INST_TAG\ndataram2 your_instance_name (\n .clka(clka), \/\/ input wire clka\n .wea(wea), \/\/ input wire [0 : 0] wea\n .addra(addra), \/\/ input wire [13 : 0] addra\n .dina(dina), \/\/ input wire [7 : 0] dina\n .douta(douta) \/\/ output wire [7 : 0] douta\n);\n\/\/ INST_TAG_END ------ End INSTANTIATION Template ---------\n\n\/\/ You must compile the wrapper file dataram2.v when simulating\n\/\/ the core, dataram2. When compiling the wrapper file, be sure to\n\/\/ reference the Verilog simulation library.\n\n","avg_line_length":43.6857142857,"max_line_length":73,"alphanum_fraction":0.7380640942} {"size":10462,"ext":"veo","lang":"Verilog","max_stars_count":5.0,"content":"\/\/*****************************************************************************\n\/\/ (c) Copyright 2009 - 2011 Xilinx, Inc. All rights reserved.\n\/\/\n\/\/ This file contains confidential and proprietary information\n\/\/ of Xilinx, Inc. and is protected under U.S. and\n\/\/ international copyright and other intellectual property\n\/\/ laws.\n\/\/\n\/\/ DISCLAIMER\n\/\/ This disclaimer is not a license and does not grant any\n\/\/ rights to the materials distributed herewith. Except as\n\/\/ otherwise provided in a valid license issued to you by\n\/\/ Xilinx, and to the maximum extent permitted by applicable\n\/\/ law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n\/\/ WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n\/\/ AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n\/\/ BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n\/\/ INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n\/\/ (2) Xilinx shall not be liable (whether in contract or tort,\n\/\/ including negligence, or under any other theory of\n\/\/ liability) for any loss or damage of any kind or nature\n\/\/ related to, arising under or in connection with these\n\/\/ materials, including for any direct, or any indirect,\n\/\/ special, incidental, or consequential loss or damage\n\/\/ (including loss of data, profits, goodwill, or any type of\n\/\/ loss or damage suffered as a result of any action brought\n\/\/ by a third party) even if such damage or loss was\n\/\/ reasonably foreseeable or Xilinx had been advised of the\n\/\/ possibility of the same.\n\/\/\n\/\/ CRITICAL APPLICATIONS\n\/\/ Xilinx products are not designed or intended to be fail-\n\/\/ safe, or for use in any application requiring fail-safe\n\/\/ performance, such as life-support or safety devices or\n\/\/ systems, Class III medical devices, nuclear facilities,\n\/\/ applications related to the deployment of airbags, or any\n\/\/ other applications that could lead to death, personal\n\/\/ injury, or severe property or environmental damage\n\/\/ (individually and collectively, \"Critical\n\/\/ Applications\"). Customer assumes the sole risk and\n\/\/ liability of any use of Xilinx products in Critical\n\/\/ Applications, subject only to applicable laws and\n\/\/ regulations governing limitations on product liability.\n\/\/\n\/\/ THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n\/\/ PART OF THIS FILE AT ALL TIMES.\n\/\/\n\/\/*****************************************************************************\n\/\/ ____ ____\n\/\/ \/ \/\\\/ \/\n\/\/ \/___\/ \\ \/ Vendor : Xilinx\n\/\/ \\ \\ \\\/ Version : 4.0\n\/\/ \\ \\ Application : MIG\n\/\/ \/ \/ Filename : mig_wrap_mig_7series_0_0.veo\n\/\/ \/___\/ \/\\ Date Last Modified : $Date: 2011\/06\/02 08:34:47 $\n\/\/ \\ \\ \/ \\ Date Created : Fri Oct 14 2011\n\/\/ \\___\\\/\\___\\\n\/\/\n\/\/ Device : 7 Series\n\/\/ Design Name : DDR2 SDRAM\n\/\/ Purpose : Template file containing code that can be used as a model\n\/\/ for instantiating a CORE Generator module in a HDL design.\n\/\/ Revision History :\n\/\/*****************************************************************************\n\n\/\/ The following must be inserted into your Verilog file for this\n\/\/ core to be instantiated. Change the instance name and port connections\n\/\/ (in parentheses) to your own signal names.\n\n\/\/----------- Begin Cut here for INSTANTIATION Template ---\/\/ INST_TAG\n\n mig_wrap_mig_7series_0_0 u_mig_wrap_mig_7series_0_0 (\n\n \/\/ Memory interface ports\n .ddr2_addr (ddr2_addr), \/\/ output [12:0] ddr2_addr\n .ddr2_ba (ddr2_ba), \/\/ output [2:0] ddr2_ba\n .ddr2_cas_n (ddr2_cas_n), \/\/ output ddr2_cas_n\n .ddr2_ck_n (ddr2_ck_n), \/\/ output [0:0] ddr2_ck_n\n .ddr2_ck_p (ddr2_ck_p), \/\/ output [0:0] ddr2_ck_p\n .ddr2_cke (ddr2_cke), \/\/ output [0:0] ddr2_cke\n .ddr2_ras_n (ddr2_ras_n), \/\/ output ddr2_ras_n\n .ddr2_we_n (ddr2_we_n), \/\/ output ddr2_we_n\n .ddr2_dq (ddr2_dq), \/\/ inout [15:0] ddr2_dq\n .ddr2_dqs_n (ddr2_dqs_n), \/\/ inout [1:0] ddr2_dqs_n\n .ddr2_dqs_p (ddr2_dqs_p), \/\/ inout [1:0] ddr2_dqs_p\n .init_calib_complete (init_calib_complete), \/\/ output init_calib_complete\n \n\t.ddr2_cs_n (ddr2_cs_n), \/\/ output [0:0] ddr2_cs_n\n .ddr2_dm (ddr2_dm), \/\/ output [1:0] ddr2_dm\n .ddr2_odt (ddr2_odt), \/\/ output [0:0] ddr2_odt\n \/\/ Application interface ports\n .ui_clk (ui_clk), \/\/ output ui_clk\n .ui_clk_sync_rst (ui_clk_sync_rst), \/\/ output ui_clk_sync_rst\n .mmcm_locked (mmcm_locked), \/\/ \n .aresetn (aresetn), \/\/ \n .app_sr_active (app_sr_active), \/\/ output app_sr_active\n .app_ref_ack (app_ref_ack), \/\/ output app_ref_ack\n .app_zq_ack (app_zq_ack), \/\/ output app_zq_ack\n \/\/ Slave Interface Write Address Ports\n .s_axi_awid (s_axi_awid), \/\/ input [3:0] s_axi_awid\n .s_axi_awaddr (s_axi_awaddr), \/\/ input [31:0] s_axi_awaddr\n .s_axi_awlen (s_axi_awlen), \/\/ input [7:0] s_axi_awlen\n .s_axi_awsize (s_axi_awsize), \/\/ input [2:0] s_axi_awsize\n .s_axi_awburst (s_axi_awburst), \/\/ input [1:0] s_axi_awburst\n .s_axi_awlock (s_axi_awlock), \/\/ input [0:0] s_axi_awlock\n .s_axi_awcache (s_axi_awcache), \/\/ input [3:0] s_axi_awcache\n .s_axi_awprot (s_axi_awprot), \/\/ input [2:0] s_axi_awprot\n .s_axi_awqos (s_axi_awqos), \/\/ input [3:0] s_axi_awqos\n .s_axi_awvalid (s_axi_awvalid), \/\/ input s_axi_awvalid\n .s_axi_awready (s_axi_awready), \/\/ output s_axi_awready\n \/\/ Slave Interface Write Data Ports\n .s_axi_wdata (s_axi_wdata), \/\/ input [31:0] s_axi_wdata\n .s_axi_wstrb (s_axi_wstrb), \/\/ input [3:0] s_axi_wstrb\n .s_axi_wlast (s_axi_wlast), \/\/ input s_axi_wlast\n .s_axi_wvalid (s_axi_wvalid), \/\/ input s_axi_wvalid\n .s_axi_wready (s_axi_wready), \/\/ output s_axi_wready\n \/\/ Slave Interface Write Response Ports\n .s_axi_bid (s_axi_bid), \/\/ output [3:0] s_axi_bid\n .s_axi_bresp (s_axi_bresp), \/\/ output [1:0] s_axi_bresp\n .s_axi_bvalid (s_axi_bvalid), \/\/ output s_axi_bvalid\n .s_axi_bready (s_axi_bready), \/\/ input s_axi_bready\n \/\/ Slave Interface Read Address Ports\n .s_axi_arid (s_axi_arid), \/\/ input [3:0] s_axi_arid\n .s_axi_araddr (s_axi_araddr), \/\/ input [31:0] s_axi_araddr\n .s_axi_arlen (s_axi_arlen), \/\/ input [7:0] s_axi_arlen\n .s_axi_arsize (s_axi_arsize), \/\/ input [2:0] s_axi_arsize\n .s_axi_arburst (s_axi_arburst), \/\/ input [1:0] s_axi_arburst\n .s_axi_arlock (s_axi_arlock), \/\/ input [0:0] s_axi_arlock\n .s_axi_arcache (s_axi_arcache), \/\/ input [3:0] s_axi_arcache\n .s_axi_arprot (s_axi_arprot), \/\/ input [2:0] s_axi_arprot\n .s_axi_arqos (s_axi_arqos), \/\/ input [3:0] s_axi_arqos\n .s_axi_arvalid (s_axi_arvalid), \/\/ input s_axi_arvalid\n .s_axi_arready (s_axi_arready), \/\/ output s_axi_arready\n \/\/ Slave Interface Read Data Ports\n .s_axi_rid (s_axi_rid), \/\/ output [3:0] s_axi_rid\n .s_axi_rdata (s_axi_rdata), \/\/ output [31:0] s_axi_rdata\n .s_axi_rresp (s_axi_rresp), \/\/ output [1:0] s_axi_rresp\n .s_axi_rlast (s_axi_rlast), \/\/ output s_axi_rlast\n .s_axi_rvalid (s_axi_rvalid), \/\/ output s_axi_rvalid\n .s_axi_rready (s_axi_rready), \/\/ input s_axi_rready\n \/\/ System Clock Ports\n .sys_clk_i (sys_clk_i),\n \/\/ Reference Clock Ports\n .clk_ref_i (clk_ref_i),\n .sys_rst (sys_rst) \/\/ input sys_rst\n );\n\n\/\/ INST_TAG_END ------ End INSTANTIATION Template ---------\n\n\/\/ You must compile the wrapper file mig_wrap_mig_7series_0_0.v when simulating\n\/\/ the core, mig_wrap_mig_7series_0_0. When compiling the wrapper file, be sure to\n\/\/ reference the XilinxCoreLib Verilog simulation library. For detailed\n\/\/ instructions, please refer to the \"CORE Generator Help\".\n","avg_line_length":67.9350649351,"max_line_length":127,"alphanum_fraction":0.4872873256} {"size":3317,"ext":"veo","lang":"Verilog","max_stars_count":27.0,"content":"\/\/ (c) Copyright 1995-2019 Xilinx, Inc. All rights reserved.\n\/\/ \n\/\/ This file contains confidential and proprietary information\n\/\/ of Xilinx, Inc. and is protected under U.S. and\n\/\/ international copyright and other intellectual property\n\/\/ laws.\n\/\/ \n\/\/ DISCLAIMER\n\/\/ This disclaimer is not a license and does not grant any\n\/\/ rights to the materials distributed herewith. Except as\n\/\/ otherwise provided in a valid license issued to you by\n\/\/ Xilinx, and to the maximum extent permitted by applicable\n\/\/ law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n\/\/ WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n\/\/ AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n\/\/ BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n\/\/ INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n\/\/ (2) Xilinx shall not be liable (whether in contract or tort,\n\/\/ including negligence, or under any other theory of\n\/\/ liability) for any loss or damage of any kind or nature\n\/\/ related to, arising under or in connection with these\n\/\/ materials, including for any direct, or any indirect,\n\/\/ special, incidental, or consequential loss or damage\n\/\/ (including loss of data, profits, goodwill, or any type of\n\/\/ loss or damage suffered as a result of any action brought\n\/\/ by a third party) even if such damage or loss was\n\/\/ reasonably foreseeable or Xilinx had been advised of the\n\/\/ possibility of the same.\n\/\/ \n\/\/ CRITICAL APPLICATIONS\n\/\/ Xilinx products are not designed or intended to be fail-\n\/\/ safe, or for use in any application requiring fail-safe\n\/\/ performance, such as life-support or safety devices or\n\/\/ systems, Class III medical devices, nuclear facilities,\n\/\/ applications related to the deployment of airbags, or any\n\/\/ other applications that could lead to death, personal\n\/\/ injury, or severe property or environmental damage\n\/\/ (individually and collectively, \"Critical\n\/\/ Applications\"). Customer assumes the sole risk and\n\/\/ liability of any use of Xilinx products in Critical\n\/\/ Applications, subject only to applicable laws and\n\/\/ regulations governing limitations on product liability.\n\/\/ \n\/\/ THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n\/\/ PART OF THIS FILE AT ALL TIMES.\n\/\/ \n\/\/ DO NOT MODIFY THIS FILE.\n\n\/\/ IP VLNV: xilinx.com:ip:blk_mem_gen:8.4\n\/\/ IP Revision: 3\n\n\/\/ The following must be inserted into your Verilog file for this\n\/\/ core to be instantiated. Change the instance name and port connections\n\/\/ (in parentheses) to your own signal names.\n\n\/\/----------- Begin Cut here for INSTANTIATION Template ---\/\/ INST_TAG\nblk_mem_gen_level12 your_instance_name (\n .clka(clka), \/\/ input wire clka\n .wea(wea), \/\/ input wire [31 : 0] wea\n .addra(addra), \/\/ input wire [9 : 0] addra\n .dina(dina), \/\/ input wire [255 : 0] dina\n .douta(douta), \/\/ output wire [255 : 0] douta\n .clkb(clkb), \/\/ input wire clkb\n .web(web), \/\/ input wire [7 : 0] web\n .addrb(addrb), \/\/ input wire [11 : 0] addrb\n .dinb(dinb), \/\/ input wire [63 : 0] dinb\n .doutb(doutb) \/\/ output wire [63 : 0] doutb\n);\n\/\/ INST_TAG_END ------ End INSTANTIATION Template ---------\n\n\/\/ You must compile the wrapper file blk_mem_gen_level12.v when simulating\n\/\/ the core, blk_mem_gen_level12. When compiling the wrapper file, be sure to\n\/\/ reference the Verilog simulation library.\n\n","avg_line_length":44.2266666667,"max_line_length":77,"alphanum_fraction":0.7277660537} {"size":3521,"ext":"veo","lang":"Verilog","max_stars_count":null,"content":"\n\/\/ \n\/\/ (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.\n\/\/ \n\/\/ This file contains confidential and proprietary information\n\/\/ of Xilinx, Inc. and is protected under U.S. and\n\/\/ international copyright and other intellectual property\n\/\/ laws.\n\/\/ \n\/\/ DISCLAIMER\n\/\/ This disclaimer is not a license and does not grant any\n\/\/ rights to the materials distributed herewith. Except as\n\/\/ otherwise provided in a valid license issued to you by\n\/\/ Xilinx, and to the maximum extent permitted by applicable\n\/\/ law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n\/\/ WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n\/\/ AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n\/\/ BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n\/\/ INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n\/\/ (2) Xilinx shall not be liable (whether in contract or tort,\n\/\/ including negligence, or under any other theory of\n\/\/ liability) for any loss or damage of any kind or nature\n\/\/ related to, arising under or in connection with these\n\/\/ materials, including for any direct, or any indirect,\n\/\/ special, incidental, or consequential loss or damage\n\/\/ (including loss of data, profits, goodwill, or any type of\n\/\/ loss or damage suffered as a result of any action brought\n\/\/ by a third party) even if such damage or loss was\n\/\/ reasonably foreseeable or Xilinx had been advised of the\n\/\/ possibility of the same.\n\/\/ \n\/\/ CRITICAL APPLICATIONS\n\/\/ Xilinx products are not designed or intended to be fail-\n\/\/ safe, or for use in any application requiring fail-safe\n\/\/ performance, such as life-support or safety devices or\n\/\/ systems, Class III medical devices, nuclear facilities,\n\/\/ applications related to the deployment of airbags, or any\n\/\/ other applications that could lead to death, personal\n\/\/ injury, or severe property or environmental damage\n\/\/ (individually and collectively, \"Critical\n\/\/ Applications\"). Customer assumes the sole risk and\n\/\/ liability of any use of Xilinx products in Critical\n\/\/ Applications, subject only to applicable laws and\n\/\/ regulations governing limitations on product liability.\n\/\/ \n\/\/ THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n\/\/ PART OF THIS FILE AT ALL TIMES.\n\/\/ \n\/\/----------------------------------------------------------------------------\n\/\/ User entered comments\n\/\/----------------------------------------------------------------------------\n\/\/ None\n\/\/\n\/\/----------------------------------------------------------------------------\n\/\/ Output Output Phase Duty Cycle Pk-to-Pk Phase\n\/\/ Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)\n\/\/----------------------------------------------------------------------------\n\/\/ ____oclk__100.00000______0.000______50.0______130.958_____98.575\n\/\/\n\/\/----------------------------------------------------------------------------\n\/\/ Input Clock Freq (MHz) Input Jitter (UI)\n\/\/----------------------------------------------------------------------------\n\/\/ __primary_________100.000____________0.010\n\n\/\/ The following must be inserted into your Verilog file for this\n\/\/ core to be instantiated. Change the instance name and port connections\n\/\/ (in parentheses) to your own signal names.\n\n\/\/----------- Begin Cut here for INSTANTIATION Template ---\/\/ INST_TAG\n\n clk_wiz_0 instance_name\n (\n \/\/ Clock out ports\n .oclk(oclk), \/\/ output oclk\n \/\/ Clock in ports\n .clk_in1(clk_in1)); \/\/ input clk_in1\n\n\/\/ INST_TAG_END ------ End INSTANTIATION Template ---------\n","avg_line_length":44.5696202532,"max_line_length":78,"alphanum_fraction":0.6333428003} {"size":5779,"ext":"veo","lang":"Verilog","max_stars_count":9.0,"content":"\/\/ (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.\n\/\/ \n\/\/ This file contains confidential and proprietary information\n\/\/ of Xilinx, Inc. and is protected under U.S. and\n\/\/ international copyright and other intellectual property\n\/\/ laws.\n\/\/ \n\/\/ DISCLAIMER\n\/\/ This disclaimer is not a license and does not grant any\n\/\/ rights to the materials distributed herewith. Except as\n\/\/ otherwise provided in a valid license issued to you by\n\/\/ Xilinx, and to the maximum extent permitted by applicable\n\/\/ law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n\/\/ WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n\/\/ AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n\/\/ BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n\/\/ INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n\/\/ (2) Xilinx shall not be liable (whether in contract or tort,\n\/\/ including negligence, or under any other theory of\n\/\/ liability) for any loss or damage of any kind or nature\n\/\/ related to, arising under or in connection with these\n\/\/ materials, including for any direct, or any indirect,\n\/\/ special, incidental, or consequential loss or damage\n\/\/ (including loss of data, profits, goodwill, or any type of\n\/\/ loss or damage suffered as a result of any action brought\n\/\/ by a third party) even if such damage or loss was\n\/\/ reasonably foreseeable or Xilinx had been advised of the\n\/\/ possibility of the same.\n\/\/ \n\/\/ CRITICAL APPLICATIONS\n\/\/ Xilinx products are not designed or intended to be fail-\n\/\/ safe, or for use in any application requiring fail-safe\n\/\/ performance, such as life-support or safety devices or\n\/\/ systems, Class III medical devices, nuclear facilities,\n\/\/ applications related to the deployment of airbags, or any\n\/\/ other applications that could lead to death, personal\n\/\/ injury, or severe property or environmental damage\n\/\/ (individually and collectively, \"Critical\n\/\/ Applications\"). Customer assumes the sole risk and\n\/\/ liability of any use of Xilinx products in Critical\n\/\/ Applications, subject only to applicable laws and\n\/\/ regulations governing limitations on product liability.\n\/\/ \n\/\/ THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n\/\/ PART OF THIS FILE AT ALL TIMES.\n\/\/ \n\/\/ DO NOT MODIFY THIS FILE.\n\n\/\/ IP VLNV: xilinx.com:ip:axi_bram_ctrl:3.0\n\/\/ IP Revision: 3\n\n\/\/ The following must be inserted into your Verilog file for this\n\/\/ core to be instantiated. Change the instance name and port connections\n\/\/ (in parentheses) to your own signal names.\n\n\/\/----------- Begin Cut here for INSTANTIATION Template ---\/\/ INST_TAG\nzynq_1_axi_bram_ctrl_0_0 your_instance_name (\n .s_axi_aclk(s_axi_aclk), \/\/ input wire s_axi_aclk\n .s_axi_aresetn(s_axi_aresetn), \/\/ input wire s_axi_aresetn\n .s_axi_awid(s_axi_awid), \/\/ input wire [11 : 0] s_axi_awid\n .s_axi_awaddr(s_axi_awaddr), \/\/ input wire [11 : 0] s_axi_awaddr\n .s_axi_awlen(s_axi_awlen), \/\/ input wire [7 : 0] s_axi_awlen\n .s_axi_awsize(s_axi_awsize), \/\/ input wire [2 : 0] s_axi_awsize\n .s_axi_awburst(s_axi_awburst), \/\/ input wire [1 : 0] s_axi_awburst\n .s_axi_awlock(s_axi_awlock), \/\/ input wire s_axi_awlock\n .s_axi_awcache(s_axi_awcache), \/\/ input wire [3 : 0] s_axi_awcache\n .s_axi_awprot(s_axi_awprot), \/\/ input wire [2 : 0] s_axi_awprot\n .s_axi_awvalid(s_axi_awvalid), \/\/ input wire s_axi_awvalid\n .s_axi_awready(s_axi_awready), \/\/ output wire s_axi_awready\n .s_axi_wdata(s_axi_wdata), \/\/ input wire [31 : 0] s_axi_wdata\n .s_axi_wstrb(s_axi_wstrb), \/\/ input wire [3 : 0] s_axi_wstrb\n .s_axi_wlast(s_axi_wlast), \/\/ input wire s_axi_wlast\n .s_axi_wvalid(s_axi_wvalid), \/\/ input wire s_axi_wvalid\n .s_axi_wready(s_axi_wready), \/\/ output wire s_axi_wready\n .s_axi_bid(s_axi_bid), \/\/ output wire [11 : 0] s_axi_bid\n .s_axi_bresp(s_axi_bresp), \/\/ output wire [1 : 0] s_axi_bresp\n .s_axi_bvalid(s_axi_bvalid), \/\/ output wire s_axi_bvalid\n .s_axi_bready(s_axi_bready), \/\/ input wire s_axi_bready\n .s_axi_arid(s_axi_arid), \/\/ input wire [11 : 0] s_axi_arid\n .s_axi_araddr(s_axi_araddr), \/\/ input wire [11 : 0] s_axi_araddr\n .s_axi_arlen(s_axi_arlen), \/\/ input wire [7 : 0] s_axi_arlen\n .s_axi_arsize(s_axi_arsize), \/\/ input wire [2 : 0] s_axi_arsize\n .s_axi_arburst(s_axi_arburst), \/\/ input wire [1 : 0] s_axi_arburst\n .s_axi_arlock(s_axi_arlock), \/\/ input wire s_axi_arlock\n .s_axi_arcache(s_axi_arcache), \/\/ input wire [3 : 0] s_axi_arcache\n .s_axi_arprot(s_axi_arprot), \/\/ input wire [2 : 0] s_axi_arprot\n .s_axi_arvalid(s_axi_arvalid), \/\/ input wire s_axi_arvalid\n .s_axi_arready(s_axi_arready), \/\/ output wire s_axi_arready\n .s_axi_rid(s_axi_rid), \/\/ output wire [11 : 0] s_axi_rid\n .s_axi_rdata(s_axi_rdata), \/\/ output wire [31 : 0] s_axi_rdata\n .s_axi_rresp(s_axi_rresp), \/\/ output wire [1 : 0] s_axi_rresp\n .s_axi_rlast(s_axi_rlast), \/\/ output wire s_axi_rlast\n .s_axi_rvalid(s_axi_rvalid), \/\/ output wire s_axi_rvalid\n .s_axi_rready(s_axi_rready), \/\/ input wire s_axi_rready\n .bram_rst_a(bram_rst_a), \/\/ output wire bram_rst_a\n .bram_clk_a(bram_clk_a), \/\/ output wire bram_clk_a\n .bram_en_a(bram_en_a), \/\/ output wire bram_en_a\n .bram_we_a(bram_we_a), \/\/ output wire [3 : 0] bram_we_a\n .bram_addr_a(bram_addr_a), \/\/ output wire [11 : 0] bram_addr_a\n .bram_wrdata_a(bram_wrdata_a), \/\/ output wire [31 : 0] bram_wrdata_a\n .bram_rddata_a(bram_rddata_a) \/\/ input wire [31 : 0] bram_rddata_a\n);\n\/\/ INST_TAG_END ------ End INSTANTIATION Template ---------\n\n\/\/ You must compile the wrapper file zynq_1_axi_bram_ctrl_0_0.v when simulating\n\/\/ the core, zynq_1_axi_bram_ctrl_0_0. When compiling the wrapper file, be sure to\n\/\/ reference the Verilog simulation library.\n\n","avg_line_length":53.0183486239,"max_line_length":82,"alphanum_fraction":0.7240006922} {"size":1285,"ext":"veo","lang":"Verilog","max_stars_count":6.0,"content":"\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\n\/\/\/\/\n\/\/\/\/ drm_ip_activator_0x1003000e00010001_wrapper\n\/\/\/\/ verilog component declaration example\n\/\/\/\/ AUTOGENERATED FILE - DO NOT EDIT\n\/\/\/\/ DRM SCRIPT VERSION 2.2.0\n\/\/\/\/ DRM HDK VERSION 6.0.0.0\n\/\/\/\/ DRM VERSION 6.0.0\n\/\/\/\/ COPYRIGHT (C) ALGODONE\n\/\/\/\/\n\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\n\ndrm_ip_activator_0x1003000e00010001_wrapper drm_ip_activator_0x1003000e00010001_wrapper_inst (\n .drm_aclk (drm_aclk),\n .drm_arstn (drm_arstn),\n .drm_bus_slave_i_cs (drm_bus_slave_i_cs),\n .drm_bus_slave_i_cyc (drm_bus_slave_i_cyc),\n .drm_bus_slave_i_we (drm_bus_slave_i_we),\n .drm_bus_slave_i_adr (drm_bus_slave_i_adr),\n .drm_bus_slave_i_dat (drm_bus_slave_i_dat),\n .drm_bus_slave_o_ack (drm_bus_slave_o_ack),\n .drm_bus_slave_o_sta (drm_bus_slave_o_sta),\n .drm_bus_slave_o_intr (drm_bus_slave_o_intr),\n .drm_bus_slave_o_dat (drm_bus_slave_o_dat),\n\n .ip_core_aclk (ip_core_aclk),\n .ip_core_arstn (ip_core_arstn),\n .drm_event (drm_event),\n .drm_arst (drm_arst),\n .activation_code_ready (activation_code_ready),\n .demo_mode (demo_mode),\n .activation_code (activation_code)\n);\n","avg_line_length":37.7941176471,"max_line_length":94,"alphanum_fraction":0.6295719844} {"size":4191,"ext":"veo","lang":"Verilog","max_stars_count":46.0,"content":"\/\/ (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved.\n\/\/ \n\/\/ This file contains confidential and proprietary information\n\/\/ of Xilinx, Inc. and is protected under U.S. and\n\/\/ international copyright and other intellectual property\n\/\/ laws.\n\/\/ \n\/\/ DISCLAIMER\n\/\/ This disclaimer is not a license and does not grant any\n\/\/ rights to the materials distributed herewith. Except as\n\/\/ otherwise provided in a valid license issued to you by\n\/\/ Xilinx, and to the maximum extent permitted by applicable\n\/\/ law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n\/\/ WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n\/\/ AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n\/\/ BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n\/\/ INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n\/\/ (2) Xilinx shall not be liable (whether in contract or tort,\n\/\/ including negligence, or under any other theory of\n\/\/ liability) for any loss or damage of any kind or nature\n\/\/ related to, arising under or in connection with these\n\/\/ materials, including for any direct, or any indirect,\n\/\/ special, incidental, or consequential loss or damage\n\/\/ (including loss of data, profits, goodwill, or any type of\n\/\/ loss or damage suffered as a result of any action brought\n\/\/ by a third party) even if such damage or loss was\n\/\/ reasonably foreseeable or Xilinx had been advised of the\n\/\/ possibility of the same.\n\/\/ \n\/\/ CRITICAL APPLICATIONS\n\/\/ Xilinx products are not designed or intended to be fail-\n\/\/ safe, or for use in any application requiring fail-safe\n\/\/ performance, such as life-support or safety devices or\n\/\/ systems, Class III medical devices, nuclear facilities,\n\/\/ applications related to the deployment of airbags, or any\n\/\/ other applications that could lead to death, personal\n\/\/ injury, or severe property or environmental damage\n\/\/ (individually and collectively, \"Critical\n\/\/ Applications\"). Customer assumes the sole risk and\n\/\/ liability of any use of Xilinx products in Critical\n\/\/ Applications, subject only to applicable laws and\n\/\/ regulations governing limitations on product liability.\n\/\/ \n\/\/ THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n\/\/ PART OF THIS FILE AT ALL TIMES.\n\/\/ \n\/\/ DO NOT MODIFY THIS FILE.\n\n\/\/ IP VLNV: xilinx.com:ip:axi_vip:1.1\n\/\/ IP Revision: 8\n\n\/\/ The following must be inserted into your Verilog file for this\n\/\/ core to be instantiated. Change the instance name and port connections\n\/\/ (in parentheses) to your own signal names.\n\n\/\/----------- Begin Cut here for INSTANTIATION Template ---\/\/ INST_TAG\naxi_mst_0 your_instance_name (\n .aclk(aclk), \/\/ input wire aclk\n .aresetn(aresetn), \/\/ input wire aresetn\n .m_axi_awaddr(m_axi_awaddr), \/\/ output wire [31 : 0] m_axi_awaddr\n .m_axi_awprot(m_axi_awprot), \/\/ output wire [2 : 0] m_axi_awprot\n .m_axi_awvalid(m_axi_awvalid), \/\/ output wire m_axi_awvalid\n .m_axi_awready(m_axi_awready), \/\/ input wire m_axi_awready\n .m_axi_wdata(m_axi_wdata), \/\/ output wire [31 : 0] m_axi_wdata\n .m_axi_wstrb(m_axi_wstrb), \/\/ output wire [3 : 0] m_axi_wstrb\n .m_axi_wvalid(m_axi_wvalid), \/\/ output wire m_axi_wvalid\n .m_axi_wready(m_axi_wready), \/\/ input wire m_axi_wready\n .m_axi_bresp(m_axi_bresp), \/\/ input wire [1 : 0] m_axi_bresp\n .m_axi_bvalid(m_axi_bvalid), \/\/ input wire m_axi_bvalid\n .m_axi_bready(m_axi_bready), \/\/ output wire m_axi_bready\n .m_axi_araddr(m_axi_araddr), \/\/ output wire [31 : 0] m_axi_araddr\n .m_axi_arprot(m_axi_arprot), \/\/ output wire [2 : 0] m_axi_arprot\n .m_axi_arvalid(m_axi_arvalid), \/\/ output wire m_axi_arvalid\n .m_axi_arready(m_axi_arready), \/\/ input wire m_axi_arready\n .m_axi_rdata(m_axi_rdata), \/\/ input wire [31 : 0] m_axi_rdata\n .m_axi_rresp(m_axi_rresp), \/\/ input wire [1 : 0] m_axi_rresp\n .m_axi_rvalid(m_axi_rvalid), \/\/ input wire m_axi_rvalid\n .m_axi_rready(m_axi_rready) \/\/ output wire m_axi_rready\n);\n\/\/ INST_TAG_END ------ End INSTANTIATION Template ---------\n\n\/\/ You must compile the wrapper file axi_mst_0.v when simulating\n\/\/ the core, axi_mst_0. When compiling the wrapper file, be sure to\n\/\/ reference the Verilog simulation library.\n\n","avg_line_length":48.7325581395,"max_line_length":73,"alphanum_fraction":0.7334764973} {"size":3391,"ext":"veo","lang":"Verilog","max_stars_count":null,"content":"\/\/ (c) Copyright 1995-2019 Xilinx, Inc. All rights reserved.\n\/\/ \n\/\/ This file contains confidential and proprietary information\n\/\/ of Xilinx, Inc. and is protected under U.S. and\n\/\/ international copyright and other intellectual property\n\/\/ laws.\n\/\/ \n\/\/ DISCLAIMER\n\/\/ This disclaimer is not a license and does not grant any\n\/\/ rights to the materials distributed herewith. Except as\n\/\/ otherwise provided in a valid license issued to you by\n\/\/ Xilinx, and to the maximum extent permitted by applicable\n\/\/ law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n\/\/ WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n\/\/ AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n\/\/ BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n\/\/ INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n\/\/ (2) Xilinx shall not be liable (whether in contract or tort,\n\/\/ including negligence, or under any other theory of\n\/\/ liability) for any loss or damage of any kind or nature\n\/\/ related to, arising under or in connection with these\n\/\/ materials, including for any direct, or any indirect,\n\/\/ special, incidental, or consequential loss or damage\n\/\/ (including loss of data, profits, goodwill, or any type of\n\/\/ loss or damage suffered as a result of any action brought\n\/\/ by a third party) even if such damage or loss was\n\/\/ reasonably foreseeable or Xilinx had been advised of the\n\/\/ possibility of the same.\n\/\/ \n\/\/ CRITICAL APPLICATIONS\n\/\/ Xilinx products are not designed or intended to be fail-\n\/\/ safe, or for use in any application requiring fail-safe\n\/\/ performance, such as life-support or safety devices or\n\/\/ systems, Class III medical devices, nuclear facilities,\n\/\/ applications related to the deployment of airbags, or any\n\/\/ other applications that could lead to death, personal\n\/\/ injury, or severe property or environmental damage\n\/\/ (individually and collectively, \"Critical\n\/\/ Applications\"). Customer assumes the sole risk and\n\/\/ liability of any use of Xilinx products in Critical\n\/\/ Applications, subject only to applicable laws and\n\/\/ regulations governing limitations on product liability.\n\/\/ \n\/\/ THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n\/\/ PART OF THIS FILE AT ALL TIMES.\n\/\/ \n\/\/ DO NOT MODIFY THIS FILE.\n\n\/\/ IP VLNV: xilinx.com:ip:fir_compiler:7.2\n\/\/ IP Revision: 10\n\n\/\/ The following must be inserted into your Verilog file for this\n\/\/ core to be instantiated. Change the instance name and port connections\n\/\/ (in parentheses) to your own signal names.\n\n\/\/----------- Begin Cut here for INSTANTIATION Template ---\/\/ INST_TAG\nfir_compiler_1 your_instance_name (\n .aresetn(aresetn), \/\/ input wire aresetn\n .aclk(aclk), \/\/ input wire aclk\n .s_axis_data_tvalid(s_axis_data_tvalid), \/\/ input wire s_axis_data_tvalid\n .s_axis_data_tready(s_axis_data_tready), \/\/ output wire s_axis_data_tready\n .s_axis_data_tdata(s_axis_data_tdata), \/\/ input wire [15 : 0] s_axis_data_tdata\n .m_axis_data_tvalid(m_axis_data_tvalid), \/\/ output wire m_axis_data_tvalid\n .m_axis_data_tdata(m_axis_data_tdata) \/\/ output wire [31 : 0] m_axis_data_tdata\n);\n\/\/ INST_TAG_END ------ End INSTANTIATION Template ---------\n\n\/\/ You must compile the wrapper file fir_compiler_1.v when simulating\n\/\/ the core, fir_compiler_1. When compiling the wrapper file, be sure to\n\/\/ reference the Verilog simulation library.\n\n","avg_line_length":47.0972222222,"max_line_length":84,"alphanum_fraction":0.7455028015} {"size":3907,"ext":"veo","lang":"Verilog","max_stars_count":null,"content":"\n\/\/ \n\/\/ (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.\n\/\/ \n\/\/ This file contains confidential and proprietary information\n\/\/ of Xilinx, Inc. and is protected under U.S. and\n\/\/ international copyright and other intellectual property\n\/\/ laws.\n\/\/ \n\/\/ DISCLAIMER\n\/\/ This disclaimer is not a license and does not grant any\n\/\/ rights to the materials distributed herewith. Except as\n\/\/ otherwise provided in a valid license issued to you by\n\/\/ Xilinx, and to the maximum extent permitted by applicable\n\/\/ law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n\/\/ WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n\/\/ AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n\/\/ BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n\/\/ INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n\/\/ (2) Xilinx shall not be liable (whether in contract or tort,\n\/\/ including negligence, or under any other theory of\n\/\/ liability) for any loss or damage of any kind or nature\n\/\/ related to, arising under or in connection with these\n\/\/ materials, including for any direct, or any indirect,\n\/\/ special, incidental, or consequential loss or damage\n\/\/ (including loss of data, profits, goodwill, or any type of\n\/\/ loss or damage suffered as a result of any action brought\n\/\/ by a third party) even if such damage or loss was\n\/\/ reasonably foreseeable or Xilinx had been advised of the\n\/\/ possibility of the same.\n\/\/ \n\/\/ CRITICAL APPLICATIONS\n\/\/ Xilinx products are not designed or intended to be fail-\n\/\/ safe, or for use in any application requiring fail-safe\n\/\/ performance, such as life-support or safety devices or\n\/\/ systems, Class III medical devices, nuclear facilities,\n\/\/ applications related to the deployment of airbags, or any\n\/\/ other applications that could lead to death, personal\n\/\/ injury, or severe property or environmental damage\n\/\/ (individually and collectively, \"Critical\n\/\/ Applications\"). Customer assumes the sole risk and\n\/\/ liability of any use of Xilinx products in Critical\n\/\/ Applications, subject only to applicable laws and\n\/\/ regulations governing limitations on product liability.\n\/\/ \n\/\/ THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n\/\/ PART OF THIS FILE AT ALL TIMES.\n\/\/ \n\/\/----------------------------------------------------------------------------\n\/\/ User entered comments\n\/\/----------------------------------------------------------------------------\n\/\/ None\n\/\/\n\/\/----------------------------------------------------------------------------\n\/\/ Output Output Phase Duty Cycle Pk-to-Pk Phase\n\/\/ Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)\n\/\/----------------------------------------------------------------------------\n\/\/ clk_out1____45.000______0.000______50.0______216.748____161.614\n\/\/ clk_out2____90.000____-45.000______50.0______179.739____161.614\n\/\/ clk_out2_noshift____90.000______0.000______50.0______179.739____161.614\n\/\/\n\/\/----------------------------------------------------------------------------\n\/\/ Input Clock Freq (MHz) Input Jitter (UI)\n\/\/----------------------------------------------------------------------------\n\/\/ __primary______________50____________0.010\n\n\/\/ The following must be inserted into your Verilog file for this\n\/\/ core to be instantiated. Change the instance name and port connections\n\/\/ (in parentheses) to your own signal names.\n\n\/\/----------- Begin Cut here for INSTANTIATION Template ---\/\/ INST_TAG\n\n pll_example instance_name\n (\n \/\/ Clock out ports\n .clk_out1(clk_out1), \/\/ output clk_out1\n .clk_out2(clk_out2), \/\/ output clk_out2\n .clk_out2_noshift(clk_out2_noshift), \/\/ output clk_out2_noshift\n \/\/ Status and control signals\n .reset(reset), \/\/ input reset\n .locked(locked), \/\/ output locked\n \/\/ Clock in ports\n .clk_in1(clk_in1)); \/\/ input clk_in1\n\/\/ INST_TAG_END ------ End INSTANTIATION Template ---------\n","avg_line_length":45.9647058824,"max_line_length":78,"alphanum_fraction":0.644484259} {"size":3030,"ext":"veo","lang":"Verilog","max_stars_count":1.0,"content":"\/\/ (c) Copyright 1995-2020 Xilinx, Inc. All rights reserved.\n\/\/ \n\/\/ This file contains confidential and proprietary information\n\/\/ of Xilinx, Inc. and is protected under U.S. and\n\/\/ international copyright and other intellectual property\n\/\/ laws.\n\/\/ \n\/\/ DISCLAIMER\n\/\/ This disclaimer is not a license and does not grant any\n\/\/ rights to the materials distributed herewith. Except as\n\/\/ otherwise provided in a valid license issued to you by\n\/\/ Xilinx, and to the maximum extent permitted by applicable\n\/\/ law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n\/\/ WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n\/\/ AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n\/\/ BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n\/\/ INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n\/\/ (2) Xilinx shall not be liable (whether in contract or tort,\n\/\/ including negligence, or under any other theory of\n\/\/ liability) for any loss or damage of any kind or nature\n\/\/ related to, arising under or in connection with these\n\/\/ materials, including for any direct, or any indirect,\n\/\/ special, incidental, or consequential loss or damage\n\/\/ (including loss of data, profits, goodwill, or any type of\n\/\/ loss or damage suffered as a result of any action brought\n\/\/ by a third party) even if such damage or loss was\n\/\/ reasonably foreseeable or Xilinx had been advised of the\n\/\/ possibility of the same.\n\/\/ \n\/\/ CRITICAL APPLICATIONS\n\/\/ Xilinx products are not designed or intended to be fail-\n\/\/ safe, or for use in any application requiring fail-safe\n\/\/ performance, such as life-support or safety devices or\n\/\/ systems, Class III medical devices, nuclear facilities,\n\/\/ applications related to the deployment of airbags, or any\n\/\/ other applications that could lead to death, personal\n\/\/ injury, or severe property or environmental damage\n\/\/ (individually and collectively, \"Critical\n\/\/ Applications\"). Customer assumes the sole risk and\n\/\/ liability of any use of Xilinx products in Critical\n\/\/ Applications, subject only to applicable laws and\n\/\/ regulations governing limitations on product liability.\n\/\/ \n\/\/ THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n\/\/ PART OF THIS FILE AT ALL TIMES.\n\/\/ \n\/\/ DO NOT MODIFY THIS FILE.\n\n\/\/ IP VLNV: xilinx.com:ip:blk_mem_gen:8.4\n\/\/ IP Revision: 4\n\n\/\/ The following must be inserted into your Verilog file for this\n\/\/ core to be instantiated. Change the instance name and port connections\n\/\/ (in parentheses) to your own signal names.\n\n\/\/----------- Begin Cut here for INSTANTIATION Template ---\/\/ INST_TAG\nblk_mem_gen_2048 your_instance_name (\n .clka(clka), \/\/ input wire clka\n .ena(ena), \/\/ input wire ena\n .addra(addra), \/\/ input wire [13 : 0] addra\n .douta(douta) \/\/ output wire [11 : 0] douta\n);\n\/\/ INST_TAG_END ------ End INSTANTIATION Template ---------\n\n\/\/ You must compile the wrapper file blk_mem_gen_2048.v when simulating\n\/\/ the core, blk_mem_gen_2048. When compiling the wrapper file, be sure to\n\/\/ reference the Verilog simulation library.\n\n","avg_line_length":43.9130434783,"max_line_length":74,"alphanum_fraction":0.7448844884} {"size":4420,"ext":"veo","lang":"Verilog","max_stars_count":null,"content":"\/\/ (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.\n\/\/ \n\/\/ This file contains confidential and proprietary information\n\/\/ of Xilinx, Inc. and is protected under U.S. and\n\/\/ international copyright and other intellectual property\n\/\/ laws.\n\/\/ \n\/\/ DISCLAIMER\n\/\/ This disclaimer is not a license and does not grant any\n\/\/ rights to the materials distributed herewith. Except as\n\/\/ otherwise provided in a valid license issued to you by\n\/\/ Xilinx, and to the maximum extent permitted by applicable\n\/\/ law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n\/\/ WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n\/\/ AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n\/\/ BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n\/\/ INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n\/\/ (2) Xilinx shall not be liable (whether in contract or tort,\n\/\/ including negligence, or under any other theory of\n\/\/ liability) for any loss or damage of any kind or nature\n\/\/ related to, arising under or in connection with these\n\/\/ materials, including for any direct, or any indirect,\n\/\/ special, incidental, or consequential loss or damage\n\/\/ (including loss of data, profits, goodwill, or any type of\n\/\/ loss or damage suffered as a result of any action brought\n\/\/ by a third party) even if such damage or loss was\n\/\/ reasonably foreseeable or Xilinx had been advised of the\n\/\/ possibility of the same.\n\/\/ \n\/\/ CRITICAL APPLICATIONS\n\/\/ Xilinx products are not designed or intended to be fail-\n\/\/ safe, or for use in any application requiring fail-safe\n\/\/ performance, such as life-support or safety devices or\n\/\/ systems, Class III medical devices, nuclear facilities,\n\/\/ applications related to the deployment of airbags, or any\n\/\/ other applications that could lead to death, personal\n\/\/ injury, or severe property or environmental damage\n\/\/ (individually and collectively, \"Critical\n\/\/ Applications\"). Customer assumes the sole risk and\n\/\/ liability of any use of Xilinx products in Critical\n\/\/ Applications, subject only to applicable laws and\n\/\/ regulations governing limitations on product liability.\n\/\/ \n\/\/ THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n\/\/ PART OF THIS FILE AT ALL TIMES.\n\/\/ \n\/\/ DO NOT MODIFY THIS FILE.\n\n\/\/ IP VLNV: digilentinc.com:ip:axi_dynclk:1.0\n\/\/ IP Revision: 3\n\n\/\/ The following must be inserted into your Verilog file for this\n\/\/ core to be instantiated. Change the instance name and port connections\n\/\/ (in parentheses) to your own signal names.\n\n\/\/----------- Begin Cut here for INSTANTIATION Template ---\/\/ INST_TAG\nhdmi_out_axi_dynclk_0_0 your_instance_name (\n .REF_CLK_I(REF_CLK_I), \/\/ input wire REF_CLK_I\n .PXL_CLK_O(PXL_CLK_O), \/\/ output wire PXL_CLK_O\n .PXL_CLK_5X_O(PXL_CLK_5X_O), \/\/ output wire PXL_CLK_5X_O\n .LOCKED_O(LOCKED_O), \/\/ output wire LOCKED_O\n .s00_axi_aclk(s00_axi_aclk), \/\/ input wire s00_axi_aclk\n .s00_axi_aresetn(s00_axi_aresetn), \/\/ input wire s00_axi_aresetn\n .s00_axi_awaddr(s00_axi_awaddr), \/\/ input wire [4 : 0] s00_axi_awaddr\n .s00_axi_awprot(s00_axi_awprot), \/\/ input wire [2 : 0] s00_axi_awprot\n .s00_axi_awvalid(s00_axi_awvalid), \/\/ input wire s00_axi_awvalid\n .s00_axi_awready(s00_axi_awready), \/\/ output wire s00_axi_awready\n .s00_axi_wdata(s00_axi_wdata), \/\/ input wire [31 : 0] s00_axi_wdata\n .s00_axi_wstrb(s00_axi_wstrb), \/\/ input wire [3 : 0] s00_axi_wstrb\n .s00_axi_wvalid(s00_axi_wvalid), \/\/ input wire s00_axi_wvalid\n .s00_axi_wready(s00_axi_wready), \/\/ output wire s00_axi_wready\n .s00_axi_bresp(s00_axi_bresp), \/\/ output wire [1 : 0] s00_axi_bresp\n .s00_axi_bvalid(s00_axi_bvalid), \/\/ output wire s00_axi_bvalid\n .s00_axi_bready(s00_axi_bready), \/\/ input wire s00_axi_bready\n .s00_axi_araddr(s00_axi_araddr), \/\/ input wire [4 : 0] s00_axi_araddr\n .s00_axi_arprot(s00_axi_arprot), \/\/ input wire [2 : 0] s00_axi_arprot\n .s00_axi_arvalid(s00_axi_arvalid), \/\/ input wire s00_axi_arvalid\n .s00_axi_arready(s00_axi_arready), \/\/ output wire s00_axi_arready\n .s00_axi_rdata(s00_axi_rdata), \/\/ output wire [31 : 0] s00_axi_rdata\n .s00_axi_rresp(s00_axi_rresp), \/\/ output wire [1 : 0] s00_axi_rresp\n .s00_axi_rvalid(s00_axi_rvalid), \/\/ output wire s00_axi_rvalid\n .s00_axi_rready(s00_axi_rready) \/\/ input wire s00_axi_rready\n);\n\/\/ INST_TAG_END ------ End INSTANTIATION Template ---------\n\n","avg_line_length":51.3953488372,"max_line_length":75,"alphanum_fraction":0.7391402715} {"size":3096,"ext":"veo","lang":"Verilog","max_stars_count":9.0,"content":"\/\/ (c) Copyright 1995-2019 Xilinx, Inc. All rights reserved.\n\/\/ \n\/\/ This file contains confidential and proprietary information\n\/\/ of Xilinx, Inc. and is protected under U.S. and\n\/\/ international copyright and other intellectual property\n\/\/ laws.\n\/\/ \n\/\/ DISCLAIMER\n\/\/ This disclaimer is not a license and does not grant any\n\/\/ rights to the materials distributed herewith. Except as\n\/\/ otherwise provided in a valid license issued to you by\n\/\/ Xilinx, and to the maximum extent permitted by applicable\n\/\/ law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n\/\/ WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n\/\/ AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n\/\/ BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n\/\/ INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n\/\/ (2) Xilinx shall not be liable (whether in contract or tort,\n\/\/ including negligence, or under any other theory of\n\/\/ liability) for any loss or damage of any kind or nature\n\/\/ related to, arising under or in connection with these\n\/\/ materials, including for any direct, or any indirect,\n\/\/ special, incidental, or consequential loss or damage\n\/\/ (including loss of data, profits, goodwill, or any type of\n\/\/ loss or damage suffered as a result of any action brought\n\/\/ by a third party) even if such damage or loss was\n\/\/ reasonably foreseeable or Xilinx had been advised of the\n\/\/ possibility of the same.\n\/\/ \n\/\/ CRITICAL APPLICATIONS\n\/\/ Xilinx products are not designed or intended to be fail-\n\/\/ safe, or for use in any application requiring fail-safe\n\/\/ performance, such as life-support or safety devices or\n\/\/ systems, Class III medical devices, nuclear facilities,\n\/\/ applications related to the deployment of airbags, or any\n\/\/ other applications that could lead to death, personal\n\/\/ injury, or severe property or environmental damage\n\/\/ (individually and collectively, \"Critical\n\/\/ Applications\"). Customer assumes the sole risk and\n\/\/ liability of any use of Xilinx products in Critical\n\/\/ Applications, subject only to applicable laws and\n\/\/ regulations governing limitations on product liability.\n\/\/ \n\/\/ THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n\/\/ PART OF THIS FILE AT ALL TIMES.\n\/\/ \n\/\/ DO NOT MODIFY THIS FILE.\n\n\/\/ IP VLNV: xilinx.com:ip:blk_mem_gen:8.4\n\/\/ IP Revision: 3\n\n\/\/ The following must be inserted into your Verilog file for this\n\/\/ core to be instantiated. Change the instance name and port connections\n\/\/ (in parentheses) to your own signal names.\n\n\/\/----------- Begin Cut here for INSTANTIATION Template ---\/\/ INST_TAG\ndata_ram your_instance_name (\n .clka(clka), \/\/ input wire clka\n .ena(ena), \/\/ input wire ena\n .wea(wea), \/\/ input wire [3 : 0] wea\n .addra(addra), \/\/ input wire [15 : 0] addra\n .dina(dina), \/\/ input wire [31 : 0] dina\n .douta(douta) \/\/ output wire [31 : 0] douta\n);\n\/\/ INST_TAG_END ------ End INSTANTIATION Template ---------\n\n\/\/ You must compile the wrapper file data_ram.v when simulating\n\/\/ the core, data_ram. When compiling the wrapper file, be sure to\n\/\/ reference the Verilog simulation library.\n\n","avg_line_length":43.6056338028,"max_line_length":73,"alphanum_fraction":0.7354651163} {"size":3024,"ext":"veo","lang":"Verilog","max_stars_count":null,"content":"\/\/ (c) Copyright 1995-2019 Xilinx, Inc. All rights reserved.\n\/\/ \n\/\/ This file contains confidential and proprietary information\n\/\/ of Xilinx, Inc. and is protected under U.S. and\n\/\/ international copyright and other intellectual property\n\/\/ laws.\n\/\/ \n\/\/ DISCLAIMER\n\/\/ This disclaimer is not a license and does not grant any\n\/\/ rights to the materials distributed herewith. Except as\n\/\/ otherwise provided in a valid license issued to you by\n\/\/ Xilinx, and to the maximum extent permitted by applicable\n\/\/ law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n\/\/ WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n\/\/ AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n\/\/ BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n\/\/ INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n\/\/ (2) Xilinx shall not be liable (whether in contract or tort,\n\/\/ including negligence, or under any other theory of\n\/\/ liability) for any loss or damage of any kind or nature\n\/\/ related to, arising under or in connection with these\n\/\/ materials, including for any direct, or any indirect,\n\/\/ special, incidental, or consequential loss or damage\n\/\/ (including loss of data, profits, goodwill, or any type of\n\/\/ loss or damage suffered as a result of any action brought\n\/\/ by a third party) even if such damage or loss was\n\/\/ reasonably foreseeable or Xilinx had been advised of the\n\/\/ possibility of the same.\n\/\/ \n\/\/ CRITICAL APPLICATIONS\n\/\/ Xilinx products are not designed or intended to be fail-\n\/\/ safe, or for use in any application requiring fail-safe\n\/\/ performance, such as life-support or safety devices or\n\/\/ systems, Class III medical devices, nuclear facilities,\n\/\/ applications related to the deployment of airbags, or any\n\/\/ other applications that could lead to death, personal\n\/\/ injury, or severe property or environmental damage\n\/\/ (individually and collectively, \"Critical\n\/\/ Applications\"). Customer assumes the sole risk and\n\/\/ liability of any use of Xilinx products in Critical\n\/\/ Applications, subject only to applicable laws and\n\/\/ regulations governing limitations on product liability.\n\/\/ \n\/\/ THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n\/\/ PART OF THIS FILE AT ALL TIMES.\n\/\/ \n\/\/ DO NOT MODIFY THIS FILE.\n\n\/\/ IP VLNV: xilinx.com:ip:c_addsub:12.0\n\/\/ IP Revision: 11\n\n\/\/ The following must be inserted into your Verilog file for this\n\/\/ core to be instantiated. Change the instance name and port connections\n\/\/ (in parentheses) to your own signal names.\n\n\/\/----------- Begin Cut here for INSTANTIATION Template ---\/\/ INST_TAG\nc_addsub_0 your_instance_name (\n .A(A), \/\/ input wire [15 : 0] A\n .B(B), \/\/ input wire [15 : 0] B\n .CLK(CLK), \/\/ input wire CLK\n .CE(CE), \/\/ input wire CE\n .S(S) \/\/ output wire [16 : 0] S\n);\n\/\/ INST_TAG_END ------ End INSTANTIATION Template ---------\n\n\/\/ You must compile the wrapper file c_addsub_0.v when simulating\n\/\/ the core, c_addsub_0. When compiling the wrapper file, be sure to\n\/\/ reference the Verilog simulation library.\n\n","avg_line_length":43.2,"max_line_length":73,"alphanum_fraction":0.7351190476} {"size":6958,"ext":"veo","lang":"Verilog","max_stars_count":null,"content":"\/\/ (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.\n\/\/ \n\/\/ This file contains confidential and proprietary information\n\/\/ of Xilinx, Inc. and is protected under U.S. and\n\/\/ international copyright and other intellectual property\n\/\/ laws.\n\/\/ \n\/\/ DISCLAIMER\n\/\/ This disclaimer is not a license and does not grant any\n\/\/ rights to the materials distributed herewith. Except as\n\/\/ otherwise provided in a valid license issued to you by\n\/\/ Xilinx, and to the maximum extent permitted by applicable\n\/\/ law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n\/\/ WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n\/\/ AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n\/\/ BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n\/\/ INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n\/\/ (2) Xilinx shall not be liable (whether in contract or tort,\n\/\/ including negligence, or under any other theory of\n\/\/ liability) for any loss or damage of any kind or nature\n\/\/ related to, arising under or in connection with these\n\/\/ materials, including for any direct, or any indirect,\n\/\/ special, incidental, or consequential loss or damage\n\/\/ (including loss of data, profits, goodwill, or any type of\n\/\/ loss or damage suffered as a result of any action brought\n\/\/ by a third party) even if such damage or loss was\n\/\/ reasonably foreseeable or Xilinx had been advised of the\n\/\/ possibility of the same.\n\/\/ \n\/\/ CRITICAL APPLICATIONS\n\/\/ Xilinx products are not designed or intended to be fail-\n\/\/ safe, or for use in any application requiring fail-safe\n\/\/ performance, such as life-support or safety devices or\n\/\/ systems, Class III medical devices, nuclear facilities,\n\/\/ applications related to the deployment of airbags, or any\n\/\/ other applications that could lead to death, personal\n\/\/ injury, or severe property or environmental damage\n\/\/ (individually and collectively, \"Critical\n\/\/ Applications\"). Customer assumes the sole risk and\n\/\/ liability of any use of Xilinx products in Critical\n\/\/ Applications, subject only to applicable laws and\n\/\/ regulations governing limitations on product liability.\n\/\/ \n\/\/ THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n\/\/ PART OF THIS FILE AT ALL TIMES.\n\/\/ \n\/\/ DO NOT MODIFY THIS FILE.\n\n\/\/ IP VLNV: xilinx.com:ip:axi_protocol_converter:2.1\n\/\/ IP Revision: 5\n\n\/\/ The following must be inserted into your Verilog file for this\n\/\/ core to be instantiated. Change the instance name and port connections\n\/\/ (in parentheses) to your own signal names.\n\n\/\/----------- Begin Cut here for INSTANTIATION Template ---\/\/ INST_TAG\ndesign_1_auto_pc_0 your_instance_name (\n .aclk(aclk), \/\/ input wire aclk\n .aresetn(aresetn), \/\/ input wire aresetn\n .s_axi_awid(s_axi_awid), \/\/ input wire [11 : 0] s_axi_awid\n .s_axi_awaddr(s_axi_awaddr), \/\/ input wire [31 : 0] s_axi_awaddr\n .s_axi_awlen(s_axi_awlen), \/\/ input wire [7 : 0] s_axi_awlen\n .s_axi_awsize(s_axi_awsize), \/\/ input wire [2 : 0] s_axi_awsize\n .s_axi_awburst(s_axi_awburst), \/\/ input wire [1 : 0] s_axi_awburst\n .s_axi_awlock(s_axi_awlock), \/\/ input wire [0 : 0] s_axi_awlock\n .s_axi_awcache(s_axi_awcache), \/\/ input wire [3 : 0] s_axi_awcache\n .s_axi_awprot(s_axi_awprot), \/\/ input wire [2 : 0] s_axi_awprot\n .s_axi_awregion(s_axi_awregion), \/\/ input wire [3 : 0] s_axi_awregion\n .s_axi_awqos(s_axi_awqos), \/\/ input wire [3 : 0] s_axi_awqos\n .s_axi_awvalid(s_axi_awvalid), \/\/ input wire s_axi_awvalid\n .s_axi_awready(s_axi_awready), \/\/ output wire s_axi_awready\n .s_axi_wdata(s_axi_wdata), \/\/ input wire [31 : 0] s_axi_wdata\n .s_axi_wstrb(s_axi_wstrb), \/\/ input wire [3 : 0] s_axi_wstrb\n .s_axi_wlast(s_axi_wlast), \/\/ input wire s_axi_wlast\n .s_axi_wvalid(s_axi_wvalid), \/\/ input wire s_axi_wvalid\n .s_axi_wready(s_axi_wready), \/\/ output wire s_axi_wready\n .s_axi_bid(s_axi_bid), \/\/ output wire [11 : 0] s_axi_bid\n .s_axi_bresp(s_axi_bresp), \/\/ output wire [1 : 0] s_axi_bresp\n .s_axi_bvalid(s_axi_bvalid), \/\/ output wire s_axi_bvalid\n .s_axi_bready(s_axi_bready), \/\/ input wire s_axi_bready\n .s_axi_arid(s_axi_arid), \/\/ input wire [11 : 0] s_axi_arid\n .s_axi_araddr(s_axi_araddr), \/\/ input wire [31 : 0] s_axi_araddr\n .s_axi_arlen(s_axi_arlen), \/\/ input wire [7 : 0] s_axi_arlen\n .s_axi_arsize(s_axi_arsize), \/\/ input wire [2 : 0] s_axi_arsize\n .s_axi_arburst(s_axi_arburst), \/\/ input wire [1 : 0] s_axi_arburst\n .s_axi_arlock(s_axi_arlock), \/\/ input wire [0 : 0] s_axi_arlock\n .s_axi_arcache(s_axi_arcache), \/\/ input wire [3 : 0] s_axi_arcache\n .s_axi_arprot(s_axi_arprot), \/\/ input wire [2 : 0] s_axi_arprot\n .s_axi_arregion(s_axi_arregion), \/\/ input wire [3 : 0] s_axi_arregion\n .s_axi_arqos(s_axi_arqos), \/\/ input wire [3 : 0] s_axi_arqos\n .s_axi_arvalid(s_axi_arvalid), \/\/ input wire s_axi_arvalid\n .s_axi_arready(s_axi_arready), \/\/ output wire s_axi_arready\n .s_axi_rid(s_axi_rid), \/\/ output wire [11 : 0] s_axi_rid\n .s_axi_rdata(s_axi_rdata), \/\/ output wire [31 : 0] s_axi_rdata\n .s_axi_rresp(s_axi_rresp), \/\/ output wire [1 : 0] s_axi_rresp\n .s_axi_rlast(s_axi_rlast), \/\/ output wire s_axi_rlast\n .s_axi_rvalid(s_axi_rvalid), \/\/ output wire s_axi_rvalid\n .s_axi_rready(s_axi_rready), \/\/ input wire s_axi_rready\n .m_axi_awaddr(m_axi_awaddr), \/\/ output wire [31 : 0] m_axi_awaddr\n .m_axi_awprot(m_axi_awprot), \/\/ output wire [2 : 0] m_axi_awprot\n .m_axi_awvalid(m_axi_awvalid), \/\/ output wire m_axi_awvalid\n .m_axi_awready(m_axi_awready), \/\/ input wire m_axi_awready\n .m_axi_wdata(m_axi_wdata), \/\/ output wire [31 : 0] m_axi_wdata\n .m_axi_wstrb(m_axi_wstrb), \/\/ output wire [3 : 0] m_axi_wstrb\n .m_axi_wvalid(m_axi_wvalid), \/\/ output wire m_axi_wvalid\n .m_axi_wready(m_axi_wready), \/\/ input wire m_axi_wready\n .m_axi_bresp(m_axi_bresp), \/\/ input wire [1 : 0] m_axi_bresp\n .m_axi_bvalid(m_axi_bvalid), \/\/ input wire m_axi_bvalid\n .m_axi_bready(m_axi_bready), \/\/ output wire m_axi_bready\n .m_axi_araddr(m_axi_araddr), \/\/ output wire [31 : 0] m_axi_araddr\n .m_axi_arprot(m_axi_arprot), \/\/ output wire [2 : 0] m_axi_arprot\n .m_axi_arvalid(m_axi_arvalid), \/\/ output wire m_axi_arvalid\n .m_axi_arready(m_axi_arready), \/\/ input wire m_axi_arready\n .m_axi_rdata(m_axi_rdata), \/\/ input wire [31 : 0] m_axi_rdata\n .m_axi_rresp(m_axi_rresp), \/\/ input wire [1 : 0] m_axi_rresp\n .m_axi_rvalid(m_axi_rvalid), \/\/ input wire m_axi_rvalid\n .m_axi_rready(m_axi_rready) \/\/ output wire m_axi_rready\n);\n\/\/ INST_TAG_END ------ End INSTANTIATION Template ---------\n\n\/\/ You must compile the wrapper file design_1_auto_pc_0.v when simulating\n\/\/ the core, design_1_auto_pc_0. When compiling the wrapper file, be sure to\n\/\/ reference the Verilog simulation library.\n\n","avg_line_length":55.664,"max_line_length":76,"alphanum_fraction":0.7066685829} {"size":3302,"ext":"veo","lang":"Verilog","max_stars_count":16.0,"content":"\/\/ (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.\n\/\/ \n\/\/ This file contains confidential and proprietary information\n\/\/ of Xilinx, Inc. and is protected under U.S. and\n\/\/ international copyright and other intellectual property\n\/\/ laws.\n\/\/ \n\/\/ DISCLAIMER\n\/\/ This disclaimer is not a license and does not grant any\n\/\/ rights to the materials distributed herewith. Except as\n\/\/ otherwise provided in a valid license issued to you by\n\/\/ Xilinx, and to the maximum extent permitted by applicable\n\/\/ law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n\/\/ WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n\/\/ AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n\/\/ BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n\/\/ INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n\/\/ (2) Xilinx shall not be liable (whether in contract or tort,\n\/\/ including negligence, or under any other theory of\n\/\/ liability) for any loss or damage of any kind or nature\n\/\/ related to, arising under or in connection with these\n\/\/ materials, including for any direct, or any indirect,\n\/\/ special, incidental, or consequential loss or damage\n\/\/ (including loss of data, profits, goodwill, or any type of\n\/\/ loss or damage suffered as a result of any action brought\n\/\/ by a third party) even if such damage or loss was\n\/\/ reasonably foreseeable or Xilinx had been advised of the\n\/\/ possibility of the same.\n\/\/ \n\/\/ CRITICAL APPLICATIONS\n\/\/ Xilinx products are not designed or intended to be fail-\n\/\/ safe, or for use in any application requiring fail-safe\n\/\/ performance, such as life-support or safety devices or\n\/\/ systems, Class III medical devices, nuclear facilities,\n\/\/ applications related to the deployment of airbags, or any\n\/\/ other applications that could lead to death, personal\n\/\/ injury, or severe property or environmental damage\n\/\/ (individually and collectively, \"Critical\n\/\/ Applications\"). Customer assumes the sole risk and\n\/\/ liability of any use of Xilinx products in Critical\n\/\/ Applications, subject only to applicable laws and\n\/\/ regulations governing limitations on product liability.\n\/\/ \n\/\/ THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n\/\/ PART OF THIS FILE AT ALL TIMES.\n\/\/ \n\/\/ DO NOT MODIFY THIS FILE.\n\n\/\/ IP VLNV: xilinx.com:ip:fifo_generator:13.0\n\/\/ IP Revision: 1\n\n\/\/ The following must be inserted into your Verilog file for this\n\/\/ core to be instantiated. Change the instance name and port connections\n\/\/ (in parentheses) to your own signal names.\n\n\/\/----------- Begin Cut here for INSTANTIATION Template ---\/\/ INST_TAG\nfifo_generator_command your_instance_name (\n .rst(rst), \/\/ input wire rst\n .wr_clk(wr_clk), \/\/ input wire wr_clk\n .rd_clk(rd_clk), \/\/ input wire rd_clk\n .din(din), \/\/ input wire [23 : 0] din\n .wr_en(wr_en), \/\/ input wire wr_en\n .rd_en(rd_en), \/\/ input wire rd_en\n .dout(dout), \/\/ output wire [23 : 0] dout\n .full(full), \/\/ output wire full\n .empty(empty), \/\/ output wire empty\n .valid(valid) \/\/ output wire valid\n);\n\/\/ INST_TAG_END ------ End INSTANTIATION Template ---------\n\n\/\/ You must compile the wrapper file fifo_generator_command.v when simulating\n\/\/ the core, fifo_generator_command. When compiling the wrapper file, be sure to\n\/\/ reference the Verilog simulation library.\n\n","avg_line_length":44.0266666667,"max_line_length":80,"alphanum_fraction":0.7337976984} {"size":3502,"ext":"veo","lang":"Verilog","max_stars_count":null,"content":"\/\/ (c) Copyright 1995-2018 Xilinx, Inc. All rights reserved.\n\/\/ \n\/\/ This file contains confidential and proprietary information\n\/\/ of Xilinx, Inc. and is protected under U.S. and\n\/\/ international copyright and other intellectual property\n\/\/ laws.\n\/\/ \n\/\/ DISCLAIMER\n\/\/ This disclaimer is not a license and does not grant any\n\/\/ rights to the materials distributed herewith. Except as\n\/\/ otherwise provided in a valid license issued to you by\n\/\/ Xilinx, and to the maximum extent permitted by applicable\n\/\/ law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n\/\/ WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n\/\/ AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n\/\/ BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n\/\/ INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n\/\/ (2) Xilinx shall not be liable (whether in contract or tort,\n\/\/ including negligence, or under any other theory of\n\/\/ liability) for any loss or damage of any kind or nature\n\/\/ related to, arising under or in connection with these\n\/\/ materials, including for any direct, or any indirect,\n\/\/ special, incidental, or consequential loss or damage\n\/\/ (including loss of data, profits, goodwill, or any type of\n\/\/ loss or damage suffered as a result of any action brought\n\/\/ by a third party) even if such damage or loss was\n\/\/ reasonably foreseeable or Xilinx had been advised of the\n\/\/ possibility of the same.\n\/\/ \n\/\/ CRITICAL APPLICATIONS\n\/\/ Xilinx products are not designed or intended to be fail-\n\/\/ safe, or for use in any application requiring fail-safe\n\/\/ performance, such as life-support or safety devices or\n\/\/ systems, Class III medical devices, nuclear facilities,\n\/\/ applications related to the deployment of airbags, or any\n\/\/ other applications that could lead to death, personal\n\/\/ injury, or severe property or environmental damage\n\/\/ (individually and collectively, \"Critical\n\/\/ Applications\"). Customer assumes the sole risk and\n\/\/ liability of any use of Xilinx products in Critical\n\/\/ Applications, subject only to applicable laws and\n\/\/ regulations governing limitations on product liability.\n\/\/ \n\/\/ THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n\/\/ PART OF THIS FILE AT ALL TIMES.\n\/\/ \n\/\/ DO NOT MODIFY THIS FILE.\n\n\/\/ IP VLNV: xilinx.com:ip:fifo_generator:13.2\n\/\/ IP Revision: 1\n\n\/\/ The following must be inserted into your Verilog file for this\n\/\/ core to be instantiated. Change the instance name and port connections\n\/\/ (in parentheses) to your own signal names.\n\n\/\/----------- Begin Cut here for INSTANTIATION Template ---\/\/ INST_TAG\nprobabilities_fifo your_instance_name (\n .rst(rst), \/\/ input wire rst\n .wr_clk(wr_clk), \/\/ input wire wr_clk\n .rd_clk(rd_clk), \/\/ input wire rd_clk\n .din(din), \/\/ input wire [1023 : 0] din\n .wr_en(wr_en), \/\/ input wire wr_en\n .rd_en(rd_en), \/\/ input wire rd_en\n .dout(dout), \/\/ output wire [255 : 0] dout\n .full(full), \/\/ output wire full\n .wr_ack(wr_ack), \/\/ output wire wr_ack\n .overflow(overflow), \/\/ output wire overflow\n .empty(empty), \/\/ output wire empty\n .valid(valid), \/\/ output wire valid\n .underflow(underflow) \/\/ output wire underflow\n);\n\/\/ INST_TAG_END ------ End INSTANTIATION Template ---------\n\n\/\/ You must compile the wrapper file probabilities_fifo.v when simulating\n\/\/ the core, probabilities_fifo. When compiling the wrapper file, be sure to\n\/\/ reference the Verilog simulation library.\n\n","avg_line_length":44.8974358974,"max_line_length":76,"alphanum_fraction":0.7175899486} {"size":3111,"ext":"veo","lang":"Verilog","max_stars_count":1.0,"content":"\/\/ (c) Copyright 1995-2019 Xilinx, Inc. All rights reserved.\n\/\/ \n\/\/ This file contains confidential and proprietary information\n\/\/ of Xilinx, Inc. and is protected under U.S. and\n\/\/ international copyright and other intellectual property\n\/\/ laws.\n\/\/ \n\/\/ DISCLAIMER\n\/\/ This disclaimer is not a license and does not grant any\n\/\/ rights to the materials distributed herewith. Except as\n\/\/ otherwise provided in a valid license issued to you by\n\/\/ Xilinx, and to the maximum extent permitted by applicable\n\/\/ law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n\/\/ WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n\/\/ AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n\/\/ BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n\/\/ INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n\/\/ (2) Xilinx shall not be liable (whether in contract or tort,\n\/\/ including negligence, or under any other theory of\n\/\/ liability) for any loss or damage of any kind or nature\n\/\/ related to, arising under or in connection with these\n\/\/ materials, including for any direct, or any indirect,\n\/\/ special, incidental, or consequential loss or damage\n\/\/ (including loss of data, profits, goodwill, or any type of\n\/\/ loss or damage suffered as a result of any action brought\n\/\/ by a third party) even if such damage or loss was\n\/\/ reasonably foreseeable or Xilinx had been advised of the\n\/\/ possibility of the same.\n\/\/ \n\/\/ CRITICAL APPLICATIONS\n\/\/ Xilinx products are not designed or intended to be fail-\n\/\/ safe, or for use in any application requiring fail-safe\n\/\/ performance, such as life-support or safety devices or\n\/\/ systems, Class III medical devices, nuclear facilities,\n\/\/ applications related to the deployment of airbags, or any\n\/\/ other applications that could lead to death, personal\n\/\/ injury, or severe property or environmental damage\n\/\/ (individually and collectively, \"Critical\n\/\/ Applications\"). Customer assumes the sole risk and\n\/\/ liability of any use of Xilinx products in Critical\n\/\/ Applications, subject only to applicable laws and\n\/\/ regulations governing limitations on product liability.\n\/\/ \n\/\/ THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n\/\/ PART OF THIS FILE AT ALL TIMES.\n\/\/ \n\/\/ DO NOT MODIFY THIS FILE.\n\n\/\/ IP VLNV: xilinx.com:ip:blk_mem_gen:8.4\n\/\/ IP Revision: 2\n\n\/\/ The following must be inserted into your Verilog file for this\n\/\/ core to be instantiated. Change the instance name and port connections\n\/\/ (in parentheses) to your own signal names.\n\n\/\/----------- Begin Cut here for INSTANTIATION Template ---\/\/ INST_TAG\nblock_cacheblock_data_8KB your_instance_name (\n .clka(clka), \/\/ input wire clka\n .wea(wea), \/\/ input wire [3 : 0] wea\n .addra(addra), \/\/ input wire [10 : 0] addra\n .dina(dina), \/\/ input wire [31 : 0] dina\n .douta(douta) \/\/ output wire [31 : 0] douta\n);\n\/\/ INST_TAG_END ------ End INSTANTIATION Template ---------\n\n\/\/ You must compile the wrapper file block_cacheblock_data_8KB.v when simulating\n\/\/ the core, block_cacheblock_data_8KB. When compiling the wrapper file, be sure to\n\/\/ reference the Verilog simulation library.\n\n","avg_line_length":44.4428571429,"max_line_length":83,"alphanum_fraction":0.7425265188} {"size":8504,"ext":"veo","lang":"Verilog","max_stars_count":1.0,"content":"\/\/ (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.\n\/\/ \n\/\/ This file contains confidential and proprietary information\n\/\/ of Xilinx, Inc. and is protected under U.S. and\n\/\/ international copyright and other intellectual property\n\/\/ laws.\n\/\/ \n\/\/ DISCLAIMER\n\/\/ This disclaimer is not a license and does not grant any\n\/\/ rights to the materials distributed herewith. Except as\n\/\/ otherwise provided in a valid license issued to you by\n\/\/ Xilinx, and to the maximum extent permitted by applicable\n\/\/ law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n\/\/ WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n\/\/ AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n\/\/ BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n\/\/ INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n\/\/ (2) Xilinx shall not be liable (whether in contract or tort,\n\/\/ including negligence, or under any other theory of\n\/\/ liability) for any loss or damage of any kind or nature\n\/\/ related to, arising under or in connection with these\n\/\/ materials, including for any direct, or any indirect,\n\/\/ special, incidental, or consequential loss or damage\n\/\/ (including loss of data, profits, goodwill, or any type of\n\/\/ loss or damage suffered as a result of any action brought\n\/\/ by a third party) even if such damage or loss was\n\/\/ reasonably foreseeable or Xilinx had been advised of the\n\/\/ possibility of the same.\n\/\/ \n\/\/ CRITICAL APPLICATIONS\n\/\/ Xilinx products are not designed or intended to be fail-\n\/\/ safe, or for use in any application requiring fail-safe\n\/\/ performance, such as life-support or safety devices or\n\/\/ systems, Class III medical devices, nuclear facilities,\n\/\/ applications related to the deployment of airbags, or any\n\/\/ other applications that could lead to death, personal\n\/\/ injury, or severe property or environmental damage\n\/\/ (individually and collectively, \"Critical\n\/\/ Applications\"). Customer assumes the sole risk and\n\/\/ liability of any use of Xilinx products in Critical\n\/\/ Applications, subject only to applicable laws and\n\/\/ regulations governing limitations on product liability.\n\/\/ \n\/\/ THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n\/\/ PART OF THIS FILE AT ALL TIMES.\n\/\/ \n\/\/ DO NOT MODIFY THIS FILE.\n\n\/\/ IP VLNV: xilinx.com:ip:axi_dma:7.1\n\/\/ IP Revision: 8\n\n\/\/ The following must be inserted into your Verilog file for this\n\/\/ core to be instantiated. Change the instance name and port connections\n\/\/ (in parentheses) to your own signal names.\n\n\/\/----------- Begin Cut here for INSTANTIATION Template ---\/\/ INST_TAG\ndesign_1_axi_dma_0_0 your_instance_name (\n .s_axi_lite_aclk(s_axi_lite_aclk), \/\/ input wire s_axi_lite_aclk\n .m_axi_mm2s_aclk(m_axi_mm2s_aclk), \/\/ input wire m_axi_mm2s_aclk\n .m_axi_s2mm_aclk(m_axi_s2mm_aclk), \/\/ input wire m_axi_s2mm_aclk\n .axi_resetn(axi_resetn), \/\/ input wire axi_resetn\n .s_axi_lite_awvalid(s_axi_lite_awvalid), \/\/ input wire s_axi_lite_awvalid\n .s_axi_lite_awready(s_axi_lite_awready), \/\/ output wire s_axi_lite_awready\n .s_axi_lite_awaddr(s_axi_lite_awaddr), \/\/ input wire [9 : 0] s_axi_lite_awaddr\n .s_axi_lite_wvalid(s_axi_lite_wvalid), \/\/ input wire s_axi_lite_wvalid\n .s_axi_lite_wready(s_axi_lite_wready), \/\/ output wire s_axi_lite_wready\n .s_axi_lite_wdata(s_axi_lite_wdata), \/\/ input wire [31 : 0] s_axi_lite_wdata\n .s_axi_lite_bresp(s_axi_lite_bresp), \/\/ output wire [1 : 0] s_axi_lite_bresp\n .s_axi_lite_bvalid(s_axi_lite_bvalid), \/\/ output wire s_axi_lite_bvalid\n .s_axi_lite_bready(s_axi_lite_bready), \/\/ input wire s_axi_lite_bready\n .s_axi_lite_arvalid(s_axi_lite_arvalid), \/\/ input wire s_axi_lite_arvalid\n .s_axi_lite_arready(s_axi_lite_arready), \/\/ output wire s_axi_lite_arready\n .s_axi_lite_araddr(s_axi_lite_araddr), \/\/ input wire [9 : 0] s_axi_lite_araddr\n .s_axi_lite_rvalid(s_axi_lite_rvalid), \/\/ output wire s_axi_lite_rvalid\n .s_axi_lite_rready(s_axi_lite_rready), \/\/ input wire s_axi_lite_rready\n .s_axi_lite_rdata(s_axi_lite_rdata), \/\/ output wire [31 : 0] s_axi_lite_rdata\n .s_axi_lite_rresp(s_axi_lite_rresp), \/\/ output wire [1 : 0] s_axi_lite_rresp\n .m_axi_mm2s_araddr(m_axi_mm2s_araddr), \/\/ output wire [31 : 0] m_axi_mm2s_araddr\n .m_axi_mm2s_arlen(m_axi_mm2s_arlen), \/\/ output wire [7 : 0] m_axi_mm2s_arlen\n .m_axi_mm2s_arsize(m_axi_mm2s_arsize), \/\/ output wire [2 : 0] m_axi_mm2s_arsize\n .m_axi_mm2s_arburst(m_axi_mm2s_arburst), \/\/ output wire [1 : 0] m_axi_mm2s_arburst\n .m_axi_mm2s_arprot(m_axi_mm2s_arprot), \/\/ output wire [2 : 0] m_axi_mm2s_arprot\n .m_axi_mm2s_arcache(m_axi_mm2s_arcache), \/\/ output wire [3 : 0] m_axi_mm2s_arcache\n .m_axi_mm2s_arvalid(m_axi_mm2s_arvalid), \/\/ output wire m_axi_mm2s_arvalid\n .m_axi_mm2s_arready(m_axi_mm2s_arready), \/\/ input wire m_axi_mm2s_arready\n .m_axi_mm2s_rdata(m_axi_mm2s_rdata), \/\/ input wire [31 : 0] m_axi_mm2s_rdata\n .m_axi_mm2s_rresp(m_axi_mm2s_rresp), \/\/ input wire [1 : 0] m_axi_mm2s_rresp\n .m_axi_mm2s_rlast(m_axi_mm2s_rlast), \/\/ input wire m_axi_mm2s_rlast\n .m_axi_mm2s_rvalid(m_axi_mm2s_rvalid), \/\/ input wire m_axi_mm2s_rvalid\n .m_axi_mm2s_rready(m_axi_mm2s_rready), \/\/ output wire m_axi_mm2s_rready\n .mm2s_prmry_reset_out_n(mm2s_prmry_reset_out_n), \/\/ output wire mm2s_prmry_reset_out_n\n .m_axis_mm2s_tdata(m_axis_mm2s_tdata), \/\/ output wire [31 : 0] m_axis_mm2s_tdata\n .m_axis_mm2s_tkeep(m_axis_mm2s_tkeep), \/\/ output wire [3 : 0] m_axis_mm2s_tkeep\n .m_axis_mm2s_tvalid(m_axis_mm2s_tvalid), \/\/ output wire m_axis_mm2s_tvalid\n .m_axis_mm2s_tready(m_axis_mm2s_tready), \/\/ input wire m_axis_mm2s_tready\n .m_axis_mm2s_tlast(m_axis_mm2s_tlast), \/\/ output wire m_axis_mm2s_tlast\n .m_axi_s2mm_awaddr(m_axi_s2mm_awaddr), \/\/ output wire [31 : 0] m_axi_s2mm_awaddr\n .m_axi_s2mm_awlen(m_axi_s2mm_awlen), \/\/ output wire [7 : 0] m_axi_s2mm_awlen\n .m_axi_s2mm_awsize(m_axi_s2mm_awsize), \/\/ output wire [2 : 0] m_axi_s2mm_awsize\n .m_axi_s2mm_awburst(m_axi_s2mm_awburst), \/\/ output wire [1 : 0] m_axi_s2mm_awburst\n .m_axi_s2mm_awprot(m_axi_s2mm_awprot), \/\/ output wire [2 : 0] m_axi_s2mm_awprot\n .m_axi_s2mm_awcache(m_axi_s2mm_awcache), \/\/ output wire [3 : 0] m_axi_s2mm_awcache\n .m_axi_s2mm_awvalid(m_axi_s2mm_awvalid), \/\/ output wire m_axi_s2mm_awvalid\n .m_axi_s2mm_awready(m_axi_s2mm_awready), \/\/ input wire m_axi_s2mm_awready\n .m_axi_s2mm_wdata(m_axi_s2mm_wdata), \/\/ output wire [31 : 0] m_axi_s2mm_wdata\n .m_axi_s2mm_wstrb(m_axi_s2mm_wstrb), \/\/ output wire [3 : 0] m_axi_s2mm_wstrb\n .m_axi_s2mm_wlast(m_axi_s2mm_wlast), \/\/ output wire m_axi_s2mm_wlast\n .m_axi_s2mm_wvalid(m_axi_s2mm_wvalid), \/\/ output wire m_axi_s2mm_wvalid\n .m_axi_s2mm_wready(m_axi_s2mm_wready), \/\/ input wire m_axi_s2mm_wready\n .m_axi_s2mm_bresp(m_axi_s2mm_bresp), \/\/ input wire [1 : 0] m_axi_s2mm_bresp\n .m_axi_s2mm_bvalid(m_axi_s2mm_bvalid), \/\/ input wire m_axi_s2mm_bvalid\n .m_axi_s2mm_bready(m_axi_s2mm_bready), \/\/ output wire m_axi_s2mm_bready\n .s2mm_prmry_reset_out_n(s2mm_prmry_reset_out_n), \/\/ output wire s2mm_prmry_reset_out_n\n .s_axis_s2mm_tdata(s_axis_s2mm_tdata), \/\/ input wire [31 : 0] s_axis_s2mm_tdata\n .s_axis_s2mm_tkeep(s_axis_s2mm_tkeep), \/\/ input wire [3 : 0] s_axis_s2mm_tkeep\n .s_axis_s2mm_tvalid(s_axis_s2mm_tvalid), \/\/ input wire s_axis_s2mm_tvalid\n .s_axis_s2mm_tready(s_axis_s2mm_tready), \/\/ output wire s_axis_s2mm_tready\n .s_axis_s2mm_tlast(s_axis_s2mm_tlast), \/\/ input wire s_axis_s2mm_tlast\n .mm2s_introut(mm2s_introut), \/\/ output wire mm2s_introut\n .s2mm_introut(s2mm_introut), \/\/ output wire s2mm_introut\n .axi_dma_tstvec(axi_dma_tstvec) \/\/ output wire [31 : 0] axi_dma_tstvec\n);\n\/\/ INST_TAG_END ------ End INSTANTIATION Template ---------\n\n\/\/ You must compile the wrapper file design_1_axi_dma_0_0.v when simulating\n\/\/ the core, design_1_axi_dma_0_0. When compiling the wrapper file, be sure to\n\/\/ reference the Verilog simulation library.\n\n","avg_line_length":65.9224806202,"max_line_length":93,"alphanum_fraction":0.7143697084} {"size":84,"ext":"veo","lang":"Verilog","max_stars_count":null,"content":" fir sysgen_dut (\n .in1(in1),\n .clk(clk),\n .gateway_out(gateway_out)\n );\n","avg_line_length":14.0,"max_line_length":29,"alphanum_fraction":0.5595238095} {"size":12103,"ext":"veo","lang":"Verilog","max_stars_count":1275.0,"content":"\/\/ (c) Copyright 1995-2018 Xilinx, Inc. All rights reserved.\n\/\/ \n\/\/ This file contains confidential and proprietary information\n\/\/ of Xilinx, Inc. and is protected under U.S. and\n\/\/ international copyright and other intellectual property\n\/\/ laws.\n\/\/ \n\/\/ DISCLAIMER\n\/\/ This disclaimer is not a license and does not grant any\n\/\/ rights to the materials distributed herewith. Except as\n\/\/ otherwise provided in a valid license issued to you by\n\/\/ Xilinx, and to the maximum extent permitted by applicable\n\/\/ law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n\/\/ WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n\/\/ AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n\/\/ BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n\/\/ INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n\/\/ (2) Xilinx shall not be liable (whether in contract or tort,\n\/\/ including negligence, or under any other theory of\n\/\/ liability) for any loss or damage of any kind or nature\n\/\/ related to, arising under or in connection with these\n\/\/ materials, including for any direct, or any indirect,\n\/\/ special, incidental, or consequential loss or damage\n\/\/ (including loss of data, profits, goodwill, or any type of\n\/\/ loss or damage suffered as a result of any action brought\n\/\/ by a third party) even if such damage or loss was\n\/\/ reasonably foreseeable or Xilinx had been advised of the\n\/\/ possibility of the same.\n\/\/ \n\/\/ CRITICAL APPLICATIONS\n\/\/ Xilinx products are not designed or intended to be fail-\n\/\/ safe, or for use in any application requiring fail-safe\n\/\/ performance, such as life-support or safety devices or\n\/\/ systems, Class III medical devices, nuclear facilities,\n\/\/ applications related to the deployment of airbags, or any\n\/\/ other applications that could lead to death, personal\n\/\/ injury, or severe property or environmental damage\n\/\/ (individually and collectively, \"Critical\n\/\/ Applications\"). Customer assumes the sole risk and\n\/\/ liability of any use of Xilinx products in Critical\n\/\/ Applications, subject only to applicable laws and\n\/\/ regulations governing limitations on product liability.\n\/\/ \n\/\/ THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n\/\/ PART OF THIS FILE AT ALL TIMES.\n\/\/ \n\/\/ DO NOT MODIFY THIS FILE.\n\n\/\/ IP VLNV: xilinx.com:ip:ddr4:2.2\n\/\/ IP Revision: 3\n\n\/\/ The following must be inserted into your Verilog file for this\n\/\/ core to be instantiated. Change the instance name and port connections\n\/\/ (in parentheses) to your own signal names.\n\n\/\/----------- Begin Cut here for INSTANTIATION Template ---\/\/ INST_TAG\nddr4_core your_instance_name (\n .c0_init_calib_complete(c0_init_calib_complete), \/\/ output wire c0_init_calib_complete\n .dbg_clk(dbg_clk), \/\/ output wire dbg_clk\n .c0_sys_clk_p(c0_sys_clk_p), \/\/ input wire c0_sys_clk_p\n .c0_sys_clk_n(c0_sys_clk_n), \/\/ input wire c0_sys_clk_n\n .dbg_bus(dbg_bus), \/\/ output wire [511 : 0] dbg_bus\n .c0_ddr4_adr(c0_ddr4_adr), \/\/ output wire [16 : 0] c0_ddr4_adr\n .c0_ddr4_ba(c0_ddr4_ba), \/\/ output wire [1 : 0] c0_ddr4_ba\n .c0_ddr4_cke(c0_ddr4_cke), \/\/ output wire [0 : 0] c0_ddr4_cke\n .c0_ddr4_cs_n(c0_ddr4_cs_n), \/\/ output wire [0 : 0] c0_ddr4_cs_n\n .c0_ddr4_dq(c0_ddr4_dq), \/\/ inout wire [71 : 0] c0_ddr4_dq\n .c0_ddr4_dqs_c(c0_ddr4_dqs_c), \/\/ inout wire [17 : 0] c0_ddr4_dqs_c\n .c0_ddr4_dqs_t(c0_ddr4_dqs_t), \/\/ inout wire [17 : 0] c0_ddr4_dqs_t\n .c0_ddr4_odt(c0_ddr4_odt), \/\/ output wire [0 : 0] c0_ddr4_odt\n .c0_ddr4_parity(c0_ddr4_parity), \/\/ output wire c0_ddr4_parity\n .c0_ddr4_bg(c0_ddr4_bg), \/\/ output wire [1 : 0] c0_ddr4_bg\n .c0_ddr4_reset_n(c0_ddr4_reset_n), \/\/ output wire c0_ddr4_reset_n\n .c0_ddr4_act_n(c0_ddr4_act_n), \/\/ output wire c0_ddr4_act_n\n .c0_ddr4_ck_c(c0_ddr4_ck_c), \/\/ output wire [0 : 0] c0_ddr4_ck_c\n .c0_ddr4_ck_t(c0_ddr4_ck_t), \/\/ output wire [0 : 0] c0_ddr4_ck_t\n .c0_ddr4_ui_clk(c0_ddr4_ui_clk), \/\/ output wire c0_ddr4_ui_clk\n .c0_ddr4_ui_clk_sync_rst(c0_ddr4_ui_clk_sync_rst), \/\/ output wire c0_ddr4_ui_clk_sync_rst\n .c0_ddr4_app_sref_req(c0_ddr4_app_sref_req), \/\/ input wire c0_ddr4_app_sref_req\n .c0_ddr4_app_sref_ack(c0_ddr4_app_sref_ack), \/\/ output wire c0_ddr4_app_sref_ack\n .c0_ddr4_app_restore_en(c0_ddr4_app_restore_en), \/\/ input wire c0_ddr4_app_restore_en\n .c0_ddr4_app_restore_complete(c0_ddr4_app_restore_complete), \/\/ input wire c0_ddr4_app_restore_complete\n .c0_ddr4_app_mem_init_skip(c0_ddr4_app_mem_init_skip), \/\/ input wire c0_ddr4_app_mem_init_skip\n .c0_ddr4_app_xsdb_select(c0_ddr4_app_xsdb_select), \/\/ input wire c0_ddr4_app_xsdb_select\n .c0_ddr4_app_xsdb_rd_en(c0_ddr4_app_xsdb_rd_en), \/\/ input wire c0_ddr4_app_xsdb_rd_en\n .c0_ddr4_app_xsdb_wr_en(c0_ddr4_app_xsdb_wr_en), \/\/ input wire c0_ddr4_app_xsdb_wr_en\n .c0_ddr4_app_xsdb_addr(c0_ddr4_app_xsdb_addr), \/\/ input wire [15 : 0] c0_ddr4_app_xsdb_addr\n .c0_ddr4_app_xsdb_wr_data(c0_ddr4_app_xsdb_wr_data), \/\/ input wire [8 : 0] c0_ddr4_app_xsdb_wr_data\n .c0_ddr4_app_xsdb_rd_data(c0_ddr4_app_xsdb_rd_data), \/\/ output wire [8 : 0] c0_ddr4_app_xsdb_rd_data\n .c0_ddr4_app_xsdb_rdy(c0_ddr4_app_xsdb_rdy), \/\/ output wire c0_ddr4_app_xsdb_rdy\n .c0_ddr4_app_dbg_out(c0_ddr4_app_dbg_out), \/\/ output wire [31 : 0] c0_ddr4_app_dbg_out\n .c0_ddr4_aresetn(c0_ddr4_aresetn), \/\/ input wire c0_ddr4_aresetn\n .c0_ddr4_s_axi_ctrl_awvalid(c0_ddr4_s_axi_ctrl_awvalid), \/\/ input wire c0_ddr4_s_axi_ctrl_awvalid\n .c0_ddr4_s_axi_ctrl_awready(c0_ddr4_s_axi_ctrl_awready), \/\/ output wire c0_ddr4_s_axi_ctrl_awready\n .c0_ddr4_s_axi_ctrl_awaddr(c0_ddr4_s_axi_ctrl_awaddr), \/\/ input wire [31 : 0] c0_ddr4_s_axi_ctrl_awaddr\n .c0_ddr4_s_axi_ctrl_wvalid(c0_ddr4_s_axi_ctrl_wvalid), \/\/ input wire c0_ddr4_s_axi_ctrl_wvalid\n .c0_ddr4_s_axi_ctrl_wready(c0_ddr4_s_axi_ctrl_wready), \/\/ output wire c0_ddr4_s_axi_ctrl_wready\n .c0_ddr4_s_axi_ctrl_wdata(c0_ddr4_s_axi_ctrl_wdata), \/\/ input wire [31 : 0] c0_ddr4_s_axi_ctrl_wdata\n .c0_ddr4_s_axi_ctrl_bvalid(c0_ddr4_s_axi_ctrl_bvalid), \/\/ output wire c0_ddr4_s_axi_ctrl_bvalid\n .c0_ddr4_s_axi_ctrl_bready(c0_ddr4_s_axi_ctrl_bready), \/\/ input wire c0_ddr4_s_axi_ctrl_bready\n .c0_ddr4_s_axi_ctrl_bresp(c0_ddr4_s_axi_ctrl_bresp), \/\/ output wire [1 : 0] c0_ddr4_s_axi_ctrl_bresp\n .c0_ddr4_s_axi_ctrl_arvalid(c0_ddr4_s_axi_ctrl_arvalid), \/\/ input wire c0_ddr4_s_axi_ctrl_arvalid\n .c0_ddr4_s_axi_ctrl_arready(c0_ddr4_s_axi_ctrl_arready), \/\/ output wire c0_ddr4_s_axi_ctrl_arready\n .c0_ddr4_s_axi_ctrl_araddr(c0_ddr4_s_axi_ctrl_araddr), \/\/ input wire [31 : 0] c0_ddr4_s_axi_ctrl_araddr\n .c0_ddr4_s_axi_ctrl_rvalid(c0_ddr4_s_axi_ctrl_rvalid), \/\/ output wire c0_ddr4_s_axi_ctrl_rvalid\n .c0_ddr4_s_axi_ctrl_rready(c0_ddr4_s_axi_ctrl_rready), \/\/ input wire c0_ddr4_s_axi_ctrl_rready\n .c0_ddr4_s_axi_ctrl_rdata(c0_ddr4_s_axi_ctrl_rdata), \/\/ output wire [31 : 0] c0_ddr4_s_axi_ctrl_rdata\n .c0_ddr4_s_axi_ctrl_rresp(c0_ddr4_s_axi_ctrl_rresp), \/\/ output wire [1 : 0] c0_ddr4_s_axi_ctrl_rresp\n .c0_ddr4_interrupt(c0_ddr4_interrupt), \/\/ output wire c0_ddr4_interrupt\n .c0_ddr4_s_axi_awid(c0_ddr4_s_axi_awid), \/\/ input wire [15 : 0] c0_ddr4_s_axi_awid\n .c0_ddr4_s_axi_awaddr(c0_ddr4_s_axi_awaddr), \/\/ input wire [33 : 0] c0_ddr4_s_axi_awaddr\n .c0_ddr4_s_axi_awlen(c0_ddr4_s_axi_awlen), \/\/ input wire [7 : 0] c0_ddr4_s_axi_awlen\n .c0_ddr4_s_axi_awsize(c0_ddr4_s_axi_awsize), \/\/ input wire [2 : 0] c0_ddr4_s_axi_awsize\n .c0_ddr4_s_axi_awburst(c0_ddr4_s_axi_awburst), \/\/ input wire [1 : 0] c0_ddr4_s_axi_awburst\n .c0_ddr4_s_axi_awlock(c0_ddr4_s_axi_awlock), \/\/ input wire [0 : 0] c0_ddr4_s_axi_awlock\n .c0_ddr4_s_axi_awcache(c0_ddr4_s_axi_awcache), \/\/ input wire [3 : 0] c0_ddr4_s_axi_awcache\n .c0_ddr4_s_axi_awprot(c0_ddr4_s_axi_awprot), \/\/ input wire [2 : 0] c0_ddr4_s_axi_awprot\n .c0_ddr4_s_axi_awqos(c0_ddr4_s_axi_awqos), \/\/ input wire [3 : 0] c0_ddr4_s_axi_awqos\n .c0_ddr4_s_axi_awvalid(c0_ddr4_s_axi_awvalid), \/\/ input wire c0_ddr4_s_axi_awvalid\n .c0_ddr4_s_axi_awready(c0_ddr4_s_axi_awready), \/\/ output wire c0_ddr4_s_axi_awready\n .c0_ddr4_s_axi_wdata(c0_ddr4_s_axi_wdata), \/\/ input wire [511 : 0] c0_ddr4_s_axi_wdata\n .c0_ddr4_s_axi_wstrb(c0_ddr4_s_axi_wstrb), \/\/ input wire [63 : 0] c0_ddr4_s_axi_wstrb\n .c0_ddr4_s_axi_wlast(c0_ddr4_s_axi_wlast), \/\/ input wire c0_ddr4_s_axi_wlast\n .c0_ddr4_s_axi_wvalid(c0_ddr4_s_axi_wvalid), \/\/ input wire c0_ddr4_s_axi_wvalid\n .c0_ddr4_s_axi_wready(c0_ddr4_s_axi_wready), \/\/ output wire c0_ddr4_s_axi_wready\n .c0_ddr4_s_axi_bready(c0_ddr4_s_axi_bready), \/\/ input wire c0_ddr4_s_axi_bready\n .c0_ddr4_s_axi_bid(c0_ddr4_s_axi_bid), \/\/ output wire [15 : 0] c0_ddr4_s_axi_bid\n .c0_ddr4_s_axi_bresp(c0_ddr4_s_axi_bresp), \/\/ output wire [1 : 0] c0_ddr4_s_axi_bresp\n .c0_ddr4_s_axi_bvalid(c0_ddr4_s_axi_bvalid), \/\/ output wire c0_ddr4_s_axi_bvalid\n .c0_ddr4_s_axi_arid(c0_ddr4_s_axi_arid), \/\/ input wire [15 : 0] c0_ddr4_s_axi_arid\n .c0_ddr4_s_axi_araddr(c0_ddr4_s_axi_araddr), \/\/ input wire [33 : 0] c0_ddr4_s_axi_araddr\n .c0_ddr4_s_axi_arlen(c0_ddr4_s_axi_arlen), \/\/ input wire [7 : 0] c0_ddr4_s_axi_arlen\n .c0_ddr4_s_axi_arsize(c0_ddr4_s_axi_arsize), \/\/ input wire [2 : 0] c0_ddr4_s_axi_arsize\n .c0_ddr4_s_axi_arburst(c0_ddr4_s_axi_arburst), \/\/ input wire [1 : 0] c0_ddr4_s_axi_arburst\n .c0_ddr4_s_axi_arlock(c0_ddr4_s_axi_arlock), \/\/ input wire [0 : 0] c0_ddr4_s_axi_arlock\n .c0_ddr4_s_axi_arcache(c0_ddr4_s_axi_arcache), \/\/ input wire [3 : 0] c0_ddr4_s_axi_arcache\n .c0_ddr4_s_axi_arprot(c0_ddr4_s_axi_arprot), \/\/ input wire [2 : 0] c0_ddr4_s_axi_arprot\n .c0_ddr4_s_axi_arqos(c0_ddr4_s_axi_arqos), \/\/ input wire [3 : 0] c0_ddr4_s_axi_arqos\n .c0_ddr4_s_axi_arvalid(c0_ddr4_s_axi_arvalid), \/\/ input wire c0_ddr4_s_axi_arvalid\n .c0_ddr4_s_axi_arready(c0_ddr4_s_axi_arready), \/\/ output wire c0_ddr4_s_axi_arready\n .c0_ddr4_s_axi_rready(c0_ddr4_s_axi_rready), \/\/ input wire c0_ddr4_s_axi_rready\n .c0_ddr4_s_axi_rlast(c0_ddr4_s_axi_rlast), \/\/ output wire c0_ddr4_s_axi_rlast\n .c0_ddr4_s_axi_rvalid(c0_ddr4_s_axi_rvalid), \/\/ output wire c0_ddr4_s_axi_rvalid\n .c0_ddr4_s_axi_rresp(c0_ddr4_s_axi_rresp), \/\/ output wire [1 : 0] c0_ddr4_s_axi_rresp\n .c0_ddr4_s_axi_rid(c0_ddr4_s_axi_rid), \/\/ output wire [15 : 0] c0_ddr4_s_axi_rid\n .c0_ddr4_s_axi_rdata(c0_ddr4_s_axi_rdata), \/\/ output wire [511 : 0] c0_ddr4_s_axi_rdata\n .sys_rst(sys_rst) \/\/ input wire sys_rst\n);\n\/\/ INST_TAG_END ------ End INSTANTIATION Template ---------\n\n\/\/ You must compile the wrapper file ddr4_core.v when simulating\n\/\/ the core, ddr4_core. When compiling the wrapper file, be sure to\n\/\/ reference the Verilog simulation library.\n\n","avg_line_length":78.0838709677,"max_line_length":112,"alphanum_fraction":0.6826406676} {"size":3645,"ext":"veo","lang":"Verilog","max_stars_count":38.0,"content":"\n\/\/ \n\/\/ (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.\n\/\/ \n\/\/ This file contains confidential and proprietary information\n\/\/ of Xilinx, Inc. and is protected under U.S. and\n\/\/ international copyright and other intellectual property\n\/\/ laws.\n\/\/ \n\/\/ DISCLAIMER\n\/\/ This disclaimer is not a license and does not grant any\n\/\/ rights to the materials distributed herewith. Except as\n\/\/ otherwise provided in a valid license issued to you by\n\/\/ Xilinx, and to the maximum extent permitted by applicable\n\/\/ law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n\/\/ WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n\/\/ AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n\/\/ BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n\/\/ INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n\/\/ (2) Xilinx shall not be liable (whether in contract or tort,\n\/\/ including negligence, or under any other theory of\n\/\/ liability) for any loss or damage of any kind or nature\n\/\/ related to, arising under or in connection with these\n\/\/ materials, including for any direct, or any indirect,\n\/\/ special, incidental, or consequential loss or damage\n\/\/ (including loss of data, profits, goodwill, or any type of\n\/\/ loss or damage suffered as a result of any action brought\n\/\/ by a third party) even if such damage or loss was\n\/\/ reasonably foreseeable or Xilinx had been advised of the\n\/\/ possibility of the same.\n\/\/ \n\/\/ CRITICAL APPLICATIONS\n\/\/ Xilinx products are not designed or intended to be fail-\n\/\/ safe, or for use in any application requiring fail-safe\n\/\/ performance, such as life-support or safety devices or\n\/\/ systems, Class III medical devices, nuclear facilities,\n\/\/ applications related to the deployment of airbags, or any\n\/\/ other applications that could lead to death, personal\n\/\/ injury, or severe property or environmental damage\n\/\/ (individually and collectively, \"Critical\n\/\/ Applications\"). Customer assumes the sole risk and\n\/\/ liability of any use of Xilinx products in Critical\n\/\/ Applications, subject only to applicable laws and\n\/\/ regulations governing limitations on product liability.\n\/\/ \n\/\/ THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n\/\/ PART OF THIS FILE AT ALL TIMES.\n\/\/ \n\/\/----------------------------------------------------------------------------\n\/\/ User entered comments\n\/\/----------------------------------------------------------------------------\n\/\/ None\n\/\/\n\/\/----------------------------------------------------------------------------\n\/\/ Output Output Phase Duty Cycle Pk-to-Pk Phase\n\/\/ Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)\n\/\/----------------------------------------------------------------------------\n\/\/ clk_out1____24.000______0.000______50.0______175.595_____99.281\n\/\/ clk_out2____25.000______0.000______50.0______174.188_____99.281\n\/\/\n\/\/----------------------------------------------------------------------------\n\/\/ Input Clock Freq (MHz) Input Jitter (UI)\n\/\/----------------------------------------------------------------------------\n\/\/ __primary_________100.000____________0.010\n\n\/\/ The following must be inserted into your Verilog file for this\n\/\/ core to be instantiated. Change the instance name and port connections\n\/\/ (in parentheses) to your own signal names.\n\n\/\/----------- Begin Cut here for INSTANTIATION Template ---\/\/ INST_TAG\n\n clk_wiz_0 instance_name\n (\n \/\/ Clock in ports\n .clk_in1(clk_in1), \/\/ input clk_in1\n \/\/ Clock out ports\n .clk_out1(clk_out1), \/\/ output clk_out1\n .clk_out2(clk_out2)); \/\/ output clk_out2\n\/\/ INST_TAG_END ------ End INSTANTIATION Template ---------\n","avg_line_length":45.5625,"max_line_length":78,"alphanum_fraction":0.638957476} {"size":14129,"ext":"veo","lang":"Verilog","max_stars_count":null,"content":"\/\/ (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.\n\/\/ \n\/\/ This file contains confidential and proprietary information\n\/\/ of Xilinx, Inc. and is protected under U.S. and\n\/\/ international copyright and other intellectual property\n\/\/ laws.\n\/\/ \n\/\/ DISCLAIMER\n\/\/ This disclaimer is not a license and does not grant any\n\/\/ rights to the materials distributed herewith. Except as\n\/\/ otherwise provided in a valid license issued to you by\n\/\/ Xilinx, and to the maximum extent permitted by applicable\n\/\/ law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n\/\/ WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n\/\/ AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n\/\/ BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n\/\/ INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n\/\/ (2) Xilinx shall not be liable (whether in contract or tort,\n\/\/ including negligence, or under any other theory of\n\/\/ liability) for any loss or damage of any kind or nature\n\/\/ related to, arising under or in connection with these\n\/\/ materials, including for any direct, or any indirect,\n\/\/ special, incidental, or consequential loss or damage\n\/\/ (including loss of data, profits, goodwill, or any type of\n\/\/ loss or damage suffered as a result of any action brought\n\/\/ by a third party) even if such damage or loss was\n\/\/ reasonably foreseeable or Xilinx had been advised of the\n\/\/ possibility of the same.\n\/\/ \n\/\/ CRITICAL APPLICATIONS\n\/\/ Xilinx products are not designed or intended to be fail-\n\/\/ safe, or for use in any application requiring fail-safe\n\/\/ performance, such as life-support or safety devices or\n\/\/ systems, Class III medical devices, nuclear facilities,\n\/\/ applications related to the deployment of airbags, or any\n\/\/ other applications that could lead to death, personal\n\/\/ injury, or severe property or environmental damage\n\/\/ (individually and collectively, \"Critical\n\/\/ Applications\"). Customer assumes the sole risk and\n\/\/ liability of any use of Xilinx products in Critical\n\/\/ Applications, subject only to applicable laws and\n\/\/ regulations governing limitations on product liability.\n\/\/ \n\/\/ THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n\/\/ PART OF THIS FILE AT ALL TIMES.\n\/\/ \n\/\/ DO NOT MODIFY THIS FILE.\n\n\/\/ IP VLNV: xilinx.com:ip:processing_system7:5.5\n\/\/ IP Revision: 1\n\n\/\/ The following must be inserted into your Verilog file for this\n\/\/ core to be instantiated. Change the instance name and port connections\n\/\/ (in parentheses) to your own signal names.\n\n\/\/----------- Begin Cut here for INSTANTIATION Template ---\/\/ INST_TAG\ndesign_1_processing_system7_0_0 your_instance_name (\n .ENET0_PTP_DELAY_REQ_RX(ENET0_PTP_DELAY_REQ_RX), \/\/ output wire ENET0_PTP_DELAY_REQ_RX\n .ENET0_PTP_DELAY_REQ_TX(ENET0_PTP_DELAY_REQ_TX), \/\/ output wire ENET0_PTP_DELAY_REQ_TX\n .ENET0_PTP_PDELAY_REQ_RX(ENET0_PTP_PDELAY_REQ_RX), \/\/ output wire ENET0_PTP_PDELAY_REQ_RX\n .ENET0_PTP_PDELAY_REQ_TX(ENET0_PTP_PDELAY_REQ_TX), \/\/ output wire ENET0_PTP_PDELAY_REQ_TX\n .ENET0_PTP_PDELAY_RESP_RX(ENET0_PTP_PDELAY_RESP_RX), \/\/ output wire ENET0_PTP_PDELAY_RESP_RX\n .ENET0_PTP_PDELAY_RESP_TX(ENET0_PTP_PDELAY_RESP_TX), \/\/ output wire ENET0_PTP_PDELAY_RESP_TX\n .ENET0_PTP_SYNC_FRAME_RX(ENET0_PTP_SYNC_FRAME_RX), \/\/ output wire ENET0_PTP_SYNC_FRAME_RX\n .ENET0_PTP_SYNC_FRAME_TX(ENET0_PTP_SYNC_FRAME_TX), \/\/ output wire ENET0_PTP_SYNC_FRAME_TX\n .ENET0_SOF_RX(ENET0_SOF_RX), \/\/ output wire ENET0_SOF_RX\n .ENET0_SOF_TX(ENET0_SOF_TX), \/\/ output wire ENET0_SOF_TX\n .TTC0_WAVE0_OUT(TTC0_WAVE0_OUT), \/\/ output wire TTC0_WAVE0_OUT\n .TTC0_WAVE1_OUT(TTC0_WAVE1_OUT), \/\/ output wire TTC0_WAVE1_OUT\n .TTC0_WAVE2_OUT(TTC0_WAVE2_OUT), \/\/ output wire TTC0_WAVE2_OUT\n .USB0_PORT_INDCTL(USB0_PORT_INDCTL), \/\/ output wire [1 : 0] USB0_PORT_INDCTL\n .USB0_VBUS_PWRSELECT(USB0_VBUS_PWRSELECT), \/\/ output wire USB0_VBUS_PWRSELECT\n .USB0_VBUS_PWRFAULT(USB0_VBUS_PWRFAULT), \/\/ input wire USB0_VBUS_PWRFAULT\n .M_AXI_GP0_ARVALID(M_AXI_GP0_ARVALID), \/\/ output wire M_AXI_GP0_ARVALID\n .M_AXI_GP0_AWVALID(M_AXI_GP0_AWVALID), \/\/ output wire M_AXI_GP0_AWVALID\n .M_AXI_GP0_BREADY(M_AXI_GP0_BREADY), \/\/ output wire M_AXI_GP0_BREADY\n .M_AXI_GP0_RREADY(M_AXI_GP0_RREADY), \/\/ output wire M_AXI_GP0_RREADY\n .M_AXI_GP0_WLAST(M_AXI_GP0_WLAST), \/\/ output wire M_AXI_GP0_WLAST\n .M_AXI_GP0_WVALID(M_AXI_GP0_WVALID), \/\/ output wire M_AXI_GP0_WVALID\n .M_AXI_GP0_ARID(M_AXI_GP0_ARID), \/\/ output wire [11 : 0] M_AXI_GP0_ARID\n .M_AXI_GP0_AWID(M_AXI_GP0_AWID), \/\/ output wire [11 : 0] M_AXI_GP0_AWID\n .M_AXI_GP0_WID(M_AXI_GP0_WID), \/\/ output wire [11 : 0] M_AXI_GP0_WID\n .M_AXI_GP0_ARBURST(M_AXI_GP0_ARBURST), \/\/ output wire [1 : 0] M_AXI_GP0_ARBURST\n .M_AXI_GP0_ARLOCK(M_AXI_GP0_ARLOCK), \/\/ output wire [1 : 0] M_AXI_GP0_ARLOCK\n .M_AXI_GP0_ARSIZE(M_AXI_GP0_ARSIZE), \/\/ output wire [2 : 0] M_AXI_GP0_ARSIZE\n .M_AXI_GP0_AWBURST(M_AXI_GP0_AWBURST), \/\/ output wire [1 : 0] M_AXI_GP0_AWBURST\n .M_AXI_GP0_AWLOCK(M_AXI_GP0_AWLOCK), \/\/ output wire [1 : 0] M_AXI_GP0_AWLOCK\n .M_AXI_GP0_AWSIZE(M_AXI_GP0_AWSIZE), \/\/ output wire [2 : 0] M_AXI_GP0_AWSIZE\n .M_AXI_GP0_ARPROT(M_AXI_GP0_ARPROT), \/\/ output wire [2 : 0] M_AXI_GP0_ARPROT\n .M_AXI_GP0_AWPROT(M_AXI_GP0_AWPROT), \/\/ output wire [2 : 0] M_AXI_GP0_AWPROT\n .M_AXI_GP0_ARADDR(M_AXI_GP0_ARADDR), \/\/ output wire [31 : 0] M_AXI_GP0_ARADDR\n .M_AXI_GP0_AWADDR(M_AXI_GP0_AWADDR), \/\/ output wire [31 : 0] M_AXI_GP0_AWADDR\n .M_AXI_GP0_WDATA(M_AXI_GP0_WDATA), \/\/ output wire [31 : 0] M_AXI_GP0_WDATA\n .M_AXI_GP0_ARCACHE(M_AXI_GP0_ARCACHE), \/\/ output wire [3 : 0] M_AXI_GP0_ARCACHE\n .M_AXI_GP0_ARLEN(M_AXI_GP0_ARLEN), \/\/ output wire [3 : 0] M_AXI_GP0_ARLEN\n .M_AXI_GP0_ARQOS(M_AXI_GP0_ARQOS), \/\/ output wire [3 : 0] M_AXI_GP0_ARQOS\n .M_AXI_GP0_AWCACHE(M_AXI_GP0_AWCACHE), \/\/ output wire [3 : 0] M_AXI_GP0_AWCACHE\n .M_AXI_GP0_AWLEN(M_AXI_GP0_AWLEN), \/\/ output wire [3 : 0] M_AXI_GP0_AWLEN\n .M_AXI_GP0_AWQOS(M_AXI_GP0_AWQOS), \/\/ output wire [3 : 0] M_AXI_GP0_AWQOS\n .M_AXI_GP0_WSTRB(M_AXI_GP0_WSTRB), \/\/ output wire [3 : 0] M_AXI_GP0_WSTRB\n .M_AXI_GP0_ACLK(M_AXI_GP0_ACLK), \/\/ input wire M_AXI_GP0_ACLK\n .M_AXI_GP0_ARREADY(M_AXI_GP0_ARREADY), \/\/ input wire M_AXI_GP0_ARREADY\n .M_AXI_GP0_AWREADY(M_AXI_GP0_AWREADY), \/\/ input wire M_AXI_GP0_AWREADY\n .M_AXI_GP0_BVALID(M_AXI_GP0_BVALID), \/\/ input wire M_AXI_GP0_BVALID\n .M_AXI_GP0_RLAST(M_AXI_GP0_RLAST), \/\/ input wire M_AXI_GP0_RLAST\n .M_AXI_GP0_RVALID(M_AXI_GP0_RVALID), \/\/ input wire M_AXI_GP0_RVALID\n .M_AXI_GP0_WREADY(M_AXI_GP0_WREADY), \/\/ input wire M_AXI_GP0_WREADY\n .M_AXI_GP0_BID(M_AXI_GP0_BID), \/\/ input wire [11 : 0] M_AXI_GP0_BID\n .M_AXI_GP0_RID(M_AXI_GP0_RID), \/\/ input wire [11 : 0] M_AXI_GP0_RID\n .M_AXI_GP0_BRESP(M_AXI_GP0_BRESP), \/\/ input wire [1 : 0] M_AXI_GP0_BRESP\n .M_AXI_GP0_RRESP(M_AXI_GP0_RRESP), \/\/ input wire [1 : 0] M_AXI_GP0_RRESP\n .M_AXI_GP0_RDATA(M_AXI_GP0_RDATA), \/\/ input wire [31 : 0] M_AXI_GP0_RDATA\n .S_AXI_HP0_ARREADY(S_AXI_HP0_ARREADY), \/\/ output wire S_AXI_HP0_ARREADY\n .S_AXI_HP0_AWREADY(S_AXI_HP0_AWREADY), \/\/ output wire S_AXI_HP0_AWREADY\n .S_AXI_HP0_BVALID(S_AXI_HP0_BVALID), \/\/ output wire S_AXI_HP0_BVALID\n .S_AXI_HP0_RLAST(S_AXI_HP0_RLAST), \/\/ output wire S_AXI_HP0_RLAST\n .S_AXI_HP0_RVALID(S_AXI_HP0_RVALID), \/\/ output wire S_AXI_HP0_RVALID\n .S_AXI_HP0_WREADY(S_AXI_HP0_WREADY), \/\/ output wire S_AXI_HP0_WREADY\n .S_AXI_HP0_BRESP(S_AXI_HP0_BRESP), \/\/ output wire [1 : 0] S_AXI_HP0_BRESP\n .S_AXI_HP0_RRESP(S_AXI_HP0_RRESP), \/\/ output wire [1 : 0] S_AXI_HP0_RRESP\n .S_AXI_HP0_BID(S_AXI_HP0_BID), \/\/ output wire [5 : 0] S_AXI_HP0_BID\n .S_AXI_HP0_RID(S_AXI_HP0_RID), \/\/ output wire [5 : 0] S_AXI_HP0_RID\n .S_AXI_HP0_RDATA(S_AXI_HP0_RDATA), \/\/ output wire [63 : 0] S_AXI_HP0_RDATA\n .S_AXI_HP0_RCOUNT(S_AXI_HP0_RCOUNT), \/\/ output wire [7 : 0] S_AXI_HP0_RCOUNT\n .S_AXI_HP0_WCOUNT(S_AXI_HP0_WCOUNT), \/\/ output wire [7 : 0] S_AXI_HP0_WCOUNT\n .S_AXI_HP0_RACOUNT(S_AXI_HP0_RACOUNT), \/\/ output wire [2 : 0] S_AXI_HP0_RACOUNT\n .S_AXI_HP0_WACOUNT(S_AXI_HP0_WACOUNT), \/\/ output wire [5 : 0] S_AXI_HP0_WACOUNT\n .S_AXI_HP0_ACLK(S_AXI_HP0_ACLK), \/\/ input wire S_AXI_HP0_ACLK\n .S_AXI_HP0_ARVALID(S_AXI_HP0_ARVALID), \/\/ input wire S_AXI_HP0_ARVALID\n .S_AXI_HP0_AWVALID(S_AXI_HP0_AWVALID), \/\/ input wire S_AXI_HP0_AWVALID\n .S_AXI_HP0_BREADY(S_AXI_HP0_BREADY), \/\/ input wire S_AXI_HP0_BREADY\n .S_AXI_HP0_RDISSUECAP1_EN(S_AXI_HP0_RDISSUECAP1_EN), \/\/ input wire S_AXI_HP0_RDISSUECAP1_EN\n .S_AXI_HP0_RREADY(S_AXI_HP0_RREADY), \/\/ input wire S_AXI_HP0_RREADY\n .S_AXI_HP0_WLAST(S_AXI_HP0_WLAST), \/\/ input wire S_AXI_HP0_WLAST\n .S_AXI_HP0_WRISSUECAP1_EN(S_AXI_HP0_WRISSUECAP1_EN), \/\/ input wire S_AXI_HP0_WRISSUECAP1_EN\n .S_AXI_HP0_WVALID(S_AXI_HP0_WVALID), \/\/ input wire S_AXI_HP0_WVALID\n .S_AXI_HP0_ARBURST(S_AXI_HP0_ARBURST), \/\/ input wire [1 : 0] S_AXI_HP0_ARBURST\n .S_AXI_HP0_ARLOCK(S_AXI_HP0_ARLOCK), \/\/ input wire [1 : 0] S_AXI_HP0_ARLOCK\n .S_AXI_HP0_ARSIZE(S_AXI_HP0_ARSIZE), \/\/ input wire [2 : 0] S_AXI_HP0_ARSIZE\n .S_AXI_HP0_AWBURST(S_AXI_HP0_AWBURST), \/\/ input wire [1 : 0] S_AXI_HP0_AWBURST\n .S_AXI_HP0_AWLOCK(S_AXI_HP0_AWLOCK), \/\/ input wire [1 : 0] S_AXI_HP0_AWLOCK\n .S_AXI_HP0_AWSIZE(S_AXI_HP0_AWSIZE), \/\/ input wire [2 : 0] S_AXI_HP0_AWSIZE\n .S_AXI_HP0_ARPROT(S_AXI_HP0_ARPROT), \/\/ input wire [2 : 0] S_AXI_HP0_ARPROT\n .S_AXI_HP0_AWPROT(S_AXI_HP0_AWPROT), \/\/ input wire [2 : 0] S_AXI_HP0_AWPROT\n .S_AXI_HP0_ARADDR(S_AXI_HP0_ARADDR), \/\/ input wire [31 : 0] S_AXI_HP0_ARADDR\n .S_AXI_HP0_AWADDR(S_AXI_HP0_AWADDR), \/\/ input wire [31 : 0] S_AXI_HP0_AWADDR\n .S_AXI_HP0_ARCACHE(S_AXI_HP0_ARCACHE), \/\/ input wire [3 : 0] S_AXI_HP0_ARCACHE\n .S_AXI_HP0_ARLEN(S_AXI_HP0_ARLEN), \/\/ input wire [3 : 0] S_AXI_HP0_ARLEN\n .S_AXI_HP0_ARQOS(S_AXI_HP0_ARQOS), \/\/ input wire [3 : 0] S_AXI_HP0_ARQOS\n .S_AXI_HP0_AWCACHE(S_AXI_HP0_AWCACHE), \/\/ input wire [3 : 0] S_AXI_HP0_AWCACHE\n .S_AXI_HP0_AWLEN(S_AXI_HP0_AWLEN), \/\/ input wire [3 : 0] S_AXI_HP0_AWLEN\n .S_AXI_HP0_AWQOS(S_AXI_HP0_AWQOS), \/\/ input wire [3 : 0] S_AXI_HP0_AWQOS\n .S_AXI_HP0_ARID(S_AXI_HP0_ARID), \/\/ input wire [5 : 0] S_AXI_HP0_ARID\n .S_AXI_HP0_AWID(S_AXI_HP0_AWID), \/\/ input wire [5 : 0] S_AXI_HP0_AWID\n .S_AXI_HP0_WID(S_AXI_HP0_WID), \/\/ input wire [5 : 0] S_AXI_HP0_WID\n .S_AXI_HP0_WDATA(S_AXI_HP0_WDATA), \/\/ input wire [63 : 0] S_AXI_HP0_WDATA\n .S_AXI_HP0_WSTRB(S_AXI_HP0_WSTRB), \/\/ input wire [7 : 0] S_AXI_HP0_WSTRB\n .IRQ_F2P(IRQ_F2P), \/\/ input wire [0 : 0] IRQ_F2P\n .FCLK_CLK0(FCLK_CLK0), \/\/ output wire FCLK_CLK0\n .FCLK_RESET0_N(FCLK_RESET0_N), \/\/ output wire FCLK_RESET0_N\n .MIO(MIO), \/\/ inout wire [53 : 0] MIO\n .DDR_CAS_n(DDR_CAS_n), \/\/ inout wire DDR_CAS_n\n .DDR_CKE(DDR_CKE), \/\/ inout wire DDR_CKE\n .DDR_Clk_n(DDR_Clk_n), \/\/ inout wire DDR_Clk_n\n .DDR_Clk(DDR_Clk), \/\/ inout wire DDR_Clk\n .DDR_CS_n(DDR_CS_n), \/\/ inout wire DDR_CS_n\n .DDR_DRSTB(DDR_DRSTB), \/\/ inout wire DDR_DRSTB\n .DDR_ODT(DDR_ODT), \/\/ inout wire DDR_ODT\n .DDR_RAS_n(DDR_RAS_n), \/\/ inout wire DDR_RAS_n\n .DDR_WEB(DDR_WEB), \/\/ inout wire DDR_WEB\n .DDR_BankAddr(DDR_BankAddr), \/\/ inout wire [2 : 0] DDR_BankAddr\n .DDR_Addr(DDR_Addr), \/\/ inout wire [14 : 0] DDR_Addr\n .DDR_VRN(DDR_VRN), \/\/ inout wire DDR_VRN\n .DDR_VRP(DDR_VRP), \/\/ inout wire DDR_VRP\n .DDR_DM(DDR_DM), \/\/ inout wire [3 : 0] DDR_DM\n .DDR_DQ(DDR_DQ), \/\/ inout wire [31 : 0] DDR_DQ\n .DDR_DQS_n(DDR_DQS_n), \/\/ inout wire [3 : 0] DDR_DQS_n\n .DDR_DQS(DDR_DQS), \/\/ inout wire [3 : 0] DDR_DQS\n .PS_SRSTB(PS_SRSTB), \/\/ inout wire PS_SRSTB\n .PS_CLK(PS_CLK), \/\/ inout wire PS_CLK\n .PS_PORB(PS_PORB) \/\/ inout wire PS_PORB\n);\n\/\/ INST_TAG_END ------ End INSTANTIATION Template ---------\n\n\/\/ You must compile the wrapper file design_1_processing_system7_0_0.v when simulating\n\/\/ the core, design_1_processing_system7_0_0. When compiling the wrapper file, be sure to\n\/\/ reference the Verilog simulation library.\n\n","avg_line_length":74.7566137566,"max_line_length":96,"alphanum_fraction":0.635855333} {"size":6763,"ext":"veo","lang":"Verilog","max_stars_count":null,"content":"\/\/ (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.\n\/\/ \n\/\/ This file contains confidential and proprietary information\n\/\/ of Xilinx, Inc. and is protected under U.S. and\n\/\/ international copyright and other intellectual property\n\/\/ laws.\n\/\/ \n\/\/ DISCLAIMER\n\/\/ This disclaimer is not a license and does not grant any\n\/\/ rights to the materials distributed herewith. Except as\n\/\/ otherwise provided in a valid license issued to you by\n\/\/ Xilinx, and to the maximum extent permitted by applicable\n\/\/ law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n\/\/ WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n\/\/ AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n\/\/ BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n\/\/ INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n\/\/ (2) Xilinx shall not be liable (whether in contract or tort,\n\/\/ including negligence, or under any other theory of\n\/\/ liability) for any loss or damage of any kind or nature\n\/\/ related to, arising under or in connection with these\n\/\/ materials, including for any direct, or any indirect,\n\/\/ special, incidental, or consequential loss or damage\n\/\/ (including loss of data, profits, goodwill, or any type of\n\/\/ loss or damage suffered as a result of any action brought\n\/\/ by a third party) even if such damage or loss was\n\/\/ reasonably foreseeable or Xilinx had been advised of the\n\/\/ possibility of the same.\n\/\/ \n\/\/ CRITICAL APPLICATIONS\n\/\/ Xilinx products are not designed or intended to be fail-\n\/\/ safe, or for use in any application requiring fail-safe\n\/\/ performance, such as life-support or safety devices or\n\/\/ systems, Class III medical devices, nuclear facilities,\n\/\/ applications related to the deployment of airbags, or any\n\/\/ other applications that could lead to death, personal\n\/\/ injury, or severe property or environmental damage\n\/\/ (individually and collectively, \"Critical\n\/\/ Applications\"). Customer assumes the sole risk and\n\/\/ liability of any use of Xilinx products in Critical\n\/\/ Applications, subject only to applicable laws and\n\/\/ regulations governing limitations on product liability.\n\/\/ \n\/\/ THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n\/\/ PART OF THIS FILE AT ALL TIMES.\n\/\/ \n\/\/ DO NOT MODIFY THIS FILE.\n\n\/\/ IP VLNV: xilinx.com:ip:axi_protocol_converter:2.1\n\/\/ IP Revision: 7\n\n\/\/ The following must be inserted into your Verilog file for this\n\/\/ core to be instantiated. Change the instance name and port connections\n\/\/ (in parentheses) to your own signal names.\n\n\/\/----------- Begin Cut here for INSTANTIATION Template ---\/\/ INST_TAG\nhdmi_out_auto_pc_0 your_instance_name (\n .aclk(aclk), \/\/ input wire aclk\n .aresetn(aresetn), \/\/ input wire aresetn\n .s_axi_awid(s_axi_awid), \/\/ input wire [11 : 0] s_axi_awid\n .s_axi_awaddr(s_axi_awaddr), \/\/ input wire [31 : 0] s_axi_awaddr\n .s_axi_awlen(s_axi_awlen), \/\/ input wire [3 : 0] s_axi_awlen\n .s_axi_awsize(s_axi_awsize), \/\/ input wire [2 : 0] s_axi_awsize\n .s_axi_awburst(s_axi_awburst), \/\/ input wire [1 : 0] s_axi_awburst\n .s_axi_awlock(s_axi_awlock), \/\/ input wire [1 : 0] s_axi_awlock\n .s_axi_awcache(s_axi_awcache), \/\/ input wire [3 : 0] s_axi_awcache\n .s_axi_awprot(s_axi_awprot), \/\/ input wire [2 : 0] s_axi_awprot\n .s_axi_awqos(s_axi_awqos), \/\/ input wire [3 : 0] s_axi_awqos\n .s_axi_awvalid(s_axi_awvalid), \/\/ input wire s_axi_awvalid\n .s_axi_awready(s_axi_awready), \/\/ output wire s_axi_awready\n .s_axi_wid(s_axi_wid), \/\/ input wire [11 : 0] s_axi_wid\n .s_axi_wdata(s_axi_wdata), \/\/ input wire [31 : 0] s_axi_wdata\n .s_axi_wstrb(s_axi_wstrb), \/\/ input wire [3 : 0] s_axi_wstrb\n .s_axi_wlast(s_axi_wlast), \/\/ input wire s_axi_wlast\n .s_axi_wvalid(s_axi_wvalid), \/\/ input wire s_axi_wvalid\n .s_axi_wready(s_axi_wready), \/\/ output wire s_axi_wready\n .s_axi_bid(s_axi_bid), \/\/ output wire [11 : 0] s_axi_bid\n .s_axi_bresp(s_axi_bresp), \/\/ output wire [1 : 0] s_axi_bresp\n .s_axi_bvalid(s_axi_bvalid), \/\/ output wire s_axi_bvalid\n .s_axi_bready(s_axi_bready), \/\/ input wire s_axi_bready\n .s_axi_arid(s_axi_arid), \/\/ input wire [11 : 0] s_axi_arid\n .s_axi_araddr(s_axi_araddr), \/\/ input wire [31 : 0] s_axi_araddr\n .s_axi_arlen(s_axi_arlen), \/\/ input wire [3 : 0] s_axi_arlen\n .s_axi_arsize(s_axi_arsize), \/\/ input wire [2 : 0] s_axi_arsize\n .s_axi_arburst(s_axi_arburst), \/\/ input wire [1 : 0] s_axi_arburst\n .s_axi_arlock(s_axi_arlock), \/\/ input wire [1 : 0] s_axi_arlock\n .s_axi_arcache(s_axi_arcache), \/\/ input wire [3 : 0] s_axi_arcache\n .s_axi_arprot(s_axi_arprot), \/\/ input wire [2 : 0] s_axi_arprot\n .s_axi_arqos(s_axi_arqos), \/\/ input wire [3 : 0] s_axi_arqos\n .s_axi_arvalid(s_axi_arvalid), \/\/ input wire s_axi_arvalid\n .s_axi_arready(s_axi_arready), \/\/ output wire s_axi_arready\n .s_axi_rid(s_axi_rid), \/\/ output wire [11 : 0] s_axi_rid\n .s_axi_rdata(s_axi_rdata), \/\/ output wire [31 : 0] s_axi_rdata\n .s_axi_rresp(s_axi_rresp), \/\/ output wire [1 : 0] s_axi_rresp\n .s_axi_rlast(s_axi_rlast), \/\/ output wire s_axi_rlast\n .s_axi_rvalid(s_axi_rvalid), \/\/ output wire s_axi_rvalid\n .s_axi_rready(s_axi_rready), \/\/ input wire s_axi_rready\n .m_axi_awaddr(m_axi_awaddr), \/\/ output wire [31 : 0] m_axi_awaddr\n .m_axi_awprot(m_axi_awprot), \/\/ output wire [2 : 0] m_axi_awprot\n .m_axi_awvalid(m_axi_awvalid), \/\/ output wire m_axi_awvalid\n .m_axi_awready(m_axi_awready), \/\/ input wire m_axi_awready\n .m_axi_wdata(m_axi_wdata), \/\/ output wire [31 : 0] m_axi_wdata\n .m_axi_wstrb(m_axi_wstrb), \/\/ output wire [3 : 0] m_axi_wstrb\n .m_axi_wvalid(m_axi_wvalid), \/\/ output wire m_axi_wvalid\n .m_axi_wready(m_axi_wready), \/\/ input wire m_axi_wready\n .m_axi_bresp(m_axi_bresp), \/\/ input wire [1 : 0] m_axi_bresp\n .m_axi_bvalid(m_axi_bvalid), \/\/ input wire m_axi_bvalid\n .m_axi_bready(m_axi_bready), \/\/ output wire m_axi_bready\n .m_axi_araddr(m_axi_araddr), \/\/ output wire [31 : 0] m_axi_araddr\n .m_axi_arprot(m_axi_arprot), \/\/ output wire [2 : 0] m_axi_arprot\n .m_axi_arvalid(m_axi_arvalid), \/\/ output wire m_axi_arvalid\n .m_axi_arready(m_axi_arready), \/\/ input wire m_axi_arready\n .m_axi_rdata(m_axi_rdata), \/\/ input wire [31 : 0] m_axi_rdata\n .m_axi_rresp(m_axi_rresp), \/\/ input wire [1 : 0] m_axi_rresp\n .m_axi_rvalid(m_axi_rvalid), \/\/ input wire m_axi_rvalid\n .m_axi_rready(m_axi_rready) \/\/ output wire m_axi_rready\n);\n\/\/ INST_TAG_END ------ End INSTANTIATION Template ---------\n\n\/\/ You must compile the wrapper file hdmi_out_auto_pc_0.v when simulating\n\/\/ the core, hdmi_out_auto_pc_0. When compiling the wrapper file, be sure to\n\/\/ reference the Verilog simulation library.\n\n","avg_line_length":54.5403225806,"max_line_length":76,"alphanum_fraction":0.7171373651} {"size":3533,"ext":"veo","lang":"Verilog","max_stars_count":1.0,"content":"\n\/\/ \n\/\/ (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.\n\/\/ \n\/\/ This file contains confidential and proprietary information\n\/\/ of Xilinx, Inc. and is protected under U.S. and\n\/\/ international copyright and other intellectual property\n\/\/ laws.\n\/\/ \n\/\/ DISCLAIMER\n\/\/ This disclaimer is not a license and does not grant any\n\/\/ rights to the materials distributed herewith. Except as\n\/\/ otherwise provided in a valid license issued to you by\n\/\/ Xilinx, and to the maximum extent permitted by applicable\n\/\/ law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n\/\/ WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n\/\/ AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n\/\/ BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n\/\/ INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n\/\/ (2) Xilinx shall not be liable (whether in contract or tort,\n\/\/ including negligence, or under any other theory of\n\/\/ liability) for any loss or damage of any kind or nature\n\/\/ related to, arising under or in connection with these\n\/\/ materials, including for any direct, or any indirect,\n\/\/ special, incidental, or consequential loss or damage\n\/\/ (including loss of data, profits, goodwill, or any type of\n\/\/ loss or damage suffered as a result of any action brought\n\/\/ by a third party) even if such damage or loss was\n\/\/ reasonably foreseeable or Xilinx had been advised of the\n\/\/ possibility of the same.\n\/\/ \n\/\/ CRITICAL APPLICATIONS\n\/\/ Xilinx products are not designed or intended to be fail-\n\/\/ safe, or for use in any application requiring fail-safe\n\/\/ performance, such as life-support or safety devices or\n\/\/ systems, Class III medical devices, nuclear facilities,\n\/\/ applications related to the deployment of airbags, or any\n\/\/ other applications that could lead to death, personal\n\/\/ injury, or severe property or environmental damage\n\/\/ (individually and collectively, \"Critical\n\/\/ Applications\"). Customer assumes the sole risk and\n\/\/ liability of any use of Xilinx products in Critical\n\/\/ Applications, subject only to applicable laws and\n\/\/ regulations governing limitations on product liability.\n\/\/ \n\/\/ THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n\/\/ PART OF THIS FILE AT ALL TIMES.\n\/\/ \n\/\/----------------------------------------------------------------------------\n\/\/ User entered comments\n\/\/----------------------------------------------------------------------------\n\/\/ None\n\/\/\n\/\/----------------------------------------------------------------------------\n\/\/ Output Output Phase Duty Cycle Pk-to-Pk Phase\n\/\/ Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)\n\/\/----------------------------------------------------------------------------\n\/\/ clk_out1___125.000______0.000______50.0______154.207____164.985\n\/\/\n\/\/----------------------------------------------------------------------------\n\/\/ Input Clock Freq (MHz) Input Jitter (UI)\n\/\/----------------------------------------------------------------------------\n\/\/ __primary______________50____________0.010\n\n\/\/ The following must be inserted into your Verilog file for this\n\/\/ core to be instantiated. Change the instance name and port connections\n\/\/ (in parentheses) to your own signal names.\n\n\/\/----------- Begin Cut here for INSTANTIATION Template ---\/\/ INST_TAG\n\n pll_clk_125 instance_name\n (\n \/\/ Clock out ports\n .clk_out1(clk_out1), \/\/ output clk_out1\n \/\/ Clock in ports\n .clk_in1(clk_in1)); \/\/ input clk_in1\n\/\/ INST_TAG_END ------ End INSTANTIATION Template ---------\n","avg_line_length":45.2948717949,"max_line_length":78,"alphanum_fraction":0.6351542598} {"size":3002,"ext":"veo","lang":"Verilog","max_stars_count":30.0,"content":"\/\/ (c) Copyright 1995-2020 Xilinx, Inc. All rights reserved.\n\/\/ \n\/\/ This file contains confidential and proprietary information\n\/\/ of Xilinx, Inc. and is protected under U.S. and\n\/\/ international copyright and other intellectual property\n\/\/ laws.\n\/\/ \n\/\/ DISCLAIMER\n\/\/ This disclaimer is not a license and does not grant any\n\/\/ rights to the materials distributed herewith. Except as\n\/\/ otherwise provided in a valid license issued to you by\n\/\/ Xilinx, and to the maximum extent permitted by applicable\n\/\/ law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n\/\/ WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n\/\/ AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n\/\/ BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n\/\/ INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n\/\/ (2) Xilinx shall not be liable (whether in contract or tort,\n\/\/ including negligence, or under any other theory of\n\/\/ liability) for any loss or damage of any kind or nature\n\/\/ related to, arising under or in connection with these\n\/\/ materials, including for any direct, or any indirect,\n\/\/ special, incidental, or consequential loss or damage\n\/\/ (including loss of data, profits, goodwill, or any type of\n\/\/ loss or damage suffered as a result of any action brought\n\/\/ by a third party) even if such damage or loss was\n\/\/ reasonably foreseeable or Xilinx had been advised of the\n\/\/ possibility of the same.\n\/\/ \n\/\/ CRITICAL APPLICATIONS\n\/\/ Xilinx products are not designed or intended to be fail-\n\/\/ safe, or for use in any application requiring fail-safe\n\/\/ performance, such as life-support or safety devices or\n\/\/ systems, Class III medical devices, nuclear facilities,\n\/\/ applications related to the deployment of airbags, or any\n\/\/ other applications that could lead to death, personal\n\/\/ injury, or severe property or environmental damage\n\/\/ (individually and collectively, \"Critical\n\/\/ Applications\"). Customer assumes the sole risk and\n\/\/ liability of any use of Xilinx products in Critical\n\/\/ Applications, subject only to applicable laws and\n\/\/ regulations governing limitations on product liability.\n\/\/ \n\/\/ THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n\/\/ PART OF THIS FILE AT ALL TIMES.\n\/\/ \n\/\/ DO NOT MODIFY THIS FILE.\n\n\/\/ IP VLNV: xilinx.com:ip:c_addsub:12.0\n\/\/ IP Revision: 14\n\n\/\/ The following must be inserted into your Verilog file for this\n\/\/ core to be instantiated. Change the instance name and port connections\n\/\/ (in parentheses) to your own signal names.\n\n\/\/----------- Begin Cut here for INSTANTIATION Template ---\/\/ INST_TAG\nadd_1_16_1_16 your_instance_name (\n .A(A), \/\/ input wire [16 : 0] A\n .B(B), \/\/ input wire [16 : 0] B\n .CLK(CLK), \/\/ input wire CLK\n .S(S) \/\/ output wire [17 : 0] S\n);\n\/\/ INST_TAG_END ------ End INSTANTIATION Template ---------\n\n\/\/ You must compile the wrapper file add_1_16_1_16.v when simulating\n\/\/ the core, add_1_16_1_16. When compiling the wrapper file, be sure to\n\/\/ reference the Verilog simulation library.\n\n","avg_line_length":43.5072463768,"max_line_length":73,"alphanum_fraction":0.7385076616} {"size":4446,"ext":"veo","lang":"Verilog","max_stars_count":3.0,"content":"\/*******************************************************************************\n* This file is owned and controlled by Xilinx and must be used solely *\n* for design, simulation, implementation and creation of design files *\n* limited to Xilinx devices or technologies. Use with non-Xilinx *\n* devices or technologies is expressly prohibited and immediately *\n* terminates your license. *\n* *\n* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION \"AS IS\" SOLELY *\n* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY *\n* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE *\n* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS *\n* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY *\n* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY *\n* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY *\n* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *\n* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *\n* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *\n* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *\n* PARTICULAR PURPOSE. *\n* *\n* Xilinx products are not intended for use in life support appliances, *\n* devices, or systems. Use in such applications are expressly *\n* prohibited. *\n* *\n* (c) Copyright 1995-2017 Xilinx, Inc. *\n* All rights reserved. *\n*******************************************************************************\/\n\n\/*******************************************************************************\n* Generated from core with identifier: xilinx.com:ip:blk_mem_gen:7.3 *\n* *\n* The Xilinx LogiCORE IP Block Memory Generator replaces the Dual Port *\n* Block Memory and Single Port Block Memory LogiCOREs, but is not a *\n* direct drop-in replacement. It should be used in all new Xilinx *\n* designs. The core supports RAM and ROM functions over a wide range of *\n* widths and depths. Use this core to generate block memories with *\n* symmetric or asymmetric read and write port widths, as well as cores *\n* which can perform simultaneous write operations to separate *\n* locations, and simultaneous read operations from the same location. *\n* For more information on differences in interface and feature support *\n* between this core and the Dual Port Block Memory and Single Port *\n* Block Memory LogiCOREs, please consult the data sheet. *\n*******************************************************************************\/\n\n\/\/ The following must be inserted into your Verilog file for this\n\/\/ core to be instantiated. Change the instance name and port connections\n\/\/ (in parentheses) to your own signal names.\n\n\/\/----------- Begin Cut here for INSTANTIATION Template ---\/\/ INST_TAG\ncache_512KB your_instance_name (\n .clka(clka), \/\/ input clka\n .ena(ena), \/\/ input ena\n .wea(wea), \/\/ input [3 : 0] wea\n .addra(addra), \/\/ input [8 : 0] addra\n .dina(dina), \/\/ input [31 : 0] dina\n .douta(douta), \/\/ output [31 : 0] douta\n .clkb(clkb), \/\/ input clkb\n .enb(enb), \/\/ input enb\n .web(web), \/\/ input [3 : 0] web\n .addrb(addrb), \/\/ input [8 : 0] addrb\n .dinb(dinb), \/\/ input [31 : 0] dinb\n .doutb(doutb) \/\/ output [31 : 0] doutb\n);\n\/\/ INST_TAG_END ------ End INSTANTIATION Template ---------\n\n\/\/ You must compile the wrapper file cache_512KB.v when simulating\n\/\/ the core, cache_512KB. When compiling the wrapper file, be sure to\n\/\/ reference the XilinxCoreLib Verilog simulation library. For detailed\n\/\/ instructions, please refer to the \"CORE Generator Help\".\n\n","avg_line_length":62.6197183099,"max_line_length":80,"alphanum_fraction":0.5321637427} {"size":3111,"ext":"veo","lang":"Verilog","max_stars_count":17.0,"content":"\/\/ (c) Copyright 1995-2020 Xilinx, Inc. All rights reserved.\n\/\/ \n\/\/ This file contains confidential and proprietary information\n\/\/ of Xilinx, Inc. and is protected under U.S. and\n\/\/ international copyright and other intellectual property\n\/\/ laws.\n\/\/ \n\/\/ DISCLAIMER\n\/\/ This disclaimer is not a license and does not grant any\n\/\/ rights to the materials distributed herewith. Except as\n\/\/ otherwise provided in a valid license issued to you by\n\/\/ Xilinx, and to the maximum extent permitted by applicable\n\/\/ law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n\/\/ WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n\/\/ AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n\/\/ BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n\/\/ INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n\/\/ (2) Xilinx shall not be liable (whether in contract or tort,\n\/\/ including negligence, or under any other theory of\n\/\/ liability) for any loss or damage of any kind or nature\n\/\/ related to, arising under or in connection with these\n\/\/ materials, including for any direct, or any indirect,\n\/\/ special, incidental, or consequential loss or damage\n\/\/ (including loss of data, profits, goodwill, or any type of\n\/\/ loss or damage suffered as a result of any action brought\n\/\/ by a third party) even if such damage or loss was\n\/\/ reasonably foreseeable or Xilinx had been advised of the\n\/\/ possibility of the same.\n\/\/ \n\/\/ CRITICAL APPLICATIONS\n\/\/ Xilinx products are not designed or intended to be fail-\n\/\/ safe, or for use in any application requiring fail-safe\n\/\/ performance, such as life-support or safety devices or\n\/\/ systems, Class III medical devices, nuclear facilities,\n\/\/ applications related to the deployment of airbags, or any\n\/\/ other applications that could lead to death, personal\n\/\/ injury, or severe property or environmental damage\n\/\/ (individually and collectively, \"Critical\n\/\/ Applications\"). Customer assumes the sole risk and\n\/\/ liability of any use of Xilinx products in Critical\n\/\/ Applications, subject only to applicable laws and\n\/\/ regulations governing limitations on product liability.\n\/\/ \n\/\/ THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n\/\/ PART OF THIS FILE AT ALL TIMES.\n\/\/ \n\/\/ DO NOT MODIFY THIS FILE.\n\n\/\/ IP VLNV: xilinx.com:ip:blk_mem_gen:8.4\n\/\/ IP Revision: 4\n\n\/\/ The following must be inserted into your Verilog file for this\n\/\/ core to be instantiated. Change the instance name and port connections\n\/\/ (in parentheses) to your own signal names.\n\n\/\/----------- Begin Cut here for INSTANTIATION Template ---\/\/ INST_TAG\nblk_mem_gen_0 your_instance_name (\n .clka(clka), \/\/ input wire clka\n .ena(ena), \/\/ input wire ena\n .wea(wea), \/\/ input wire [0 : 0] wea\n .addra(addra), \/\/ input wire [10 : 0] addra\n .dina(dina), \/\/ input wire [15 : 0] dina\n .douta(douta) \/\/ output wire [15 : 0] douta\n);\n\/\/ INST_TAG_END ------ End INSTANTIATION Template ---------\n\n\/\/ You must compile the wrapper file blk_mem_gen_0.v when simulating\n\/\/ the core, blk_mem_gen_0. When compiling the wrapper file, be sure to\n\/\/ reference the Verilog simulation library.\n\n","avg_line_length":43.8169014085,"max_line_length":73,"alphanum_fraction":0.7367405979} {"size":4047,"ext":"veo","lang":"Verilog","max_stars_count":21.0,"content":"\/\/ (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.\n\/\/ \n\/\/ This file contains confidential and proprietary information\n\/\/ of Xilinx, Inc. and is protected under U.S. and\n\/\/ international copyright and other intellectual property\n\/\/ laws.\n\/\/ \n\/\/ DISCLAIMER\n\/\/ This disclaimer is not a license and does not grant any\n\/\/ rights to the materials distributed herewith. Except as\n\/\/ otherwise provided in a valid license issued to you by\n\/\/ Xilinx, and to the maximum extent permitted by applicable\n\/\/ law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n\/\/ WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n\/\/ AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n\/\/ BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n\/\/ INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n\/\/ (2) Xilinx shall not be liable (whether in contract or tort,\n\/\/ including negligence, or under any other theory of\n\/\/ liability) for any loss or damage of any kind or nature\n\/\/ related to, arising under or in connection with these\n\/\/ materials, including for any direct, or any indirect,\n\/\/ special, incidental, or consequential loss or damage\n\/\/ (including loss of data, profits, goodwill, or any type of\n\/\/ loss or damage suffered as a result of any action brought\n\/\/ by a third party) even if such damage or loss was\n\/\/ reasonably foreseeable or Xilinx had been advised of the\n\/\/ possibility of the same.\n\/\/ \n\/\/ CRITICAL APPLICATIONS\n\/\/ Xilinx products are not designed or intended to be fail-\n\/\/ safe, or for use in any application requiring fail-safe\n\/\/ performance, such as life-support or safety devices or\n\/\/ systems, Class III medical devices, nuclear facilities,\n\/\/ applications related to the deployment of airbags, or any\n\/\/ other applications that could lead to death, personal\n\/\/ injury, or severe property or environmental damage\n\/\/ (individually and collectively, \"Critical\n\/\/ Applications\"). Customer assumes the sole risk and\n\/\/ liability of any use of Xilinx products in Critical\n\/\/ Applications, subject only to applicable laws and\n\/\/ regulations governing limitations on product liability.\n\/\/ \n\/\/ THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n\/\/ PART OF THIS FILE AT ALL TIMES.\n\/\/ \n\/\/ DO NOT MODIFY THIS FILE.\n\n\/\/ IP VLNV: xilinx.com:ip:mii_to_rmii:2.0\n\/\/ IP Revision: 8\n\n\/\/ The following must be inserted into your Verilog file for this\n\/\/ core to be instantiated. Change the instance name and port connections\n\/\/ (in parentheses) to your own signal names.\n\n\/\/----------- Begin Cut here for INSTANTIATION Template ---\/\/ INST_TAG\nZynqDesign_mii_to_rmii_0_0 your_instance_name (\n .rst_n(rst_n), \/\/ input wire rst_n\n .ref_clk(ref_clk), \/\/ input wire ref_clk\n .mac2rmii_tx_en(mac2rmii_tx_en), \/\/ input wire mac2rmii_tx_en\n .mac2rmii_txd(mac2rmii_txd), \/\/ input wire [3 : 0] mac2rmii_txd\n .mac2rmii_tx_er(mac2rmii_tx_er), \/\/ input wire mac2rmii_tx_er\n .rmii2mac_tx_clk(rmii2mac_tx_clk), \/\/ output wire rmii2mac_tx_clk\n .rmii2mac_rx_clk(rmii2mac_rx_clk), \/\/ output wire rmii2mac_rx_clk\n .rmii2mac_col(rmii2mac_col), \/\/ output wire rmii2mac_col\n .rmii2mac_crs(rmii2mac_crs), \/\/ output wire rmii2mac_crs\n .rmii2mac_rx_dv(rmii2mac_rx_dv), \/\/ output wire rmii2mac_rx_dv\n .rmii2mac_rx_er(rmii2mac_rx_er), \/\/ output wire rmii2mac_rx_er\n .rmii2mac_rxd(rmii2mac_rxd), \/\/ output wire [3 : 0] rmii2mac_rxd\n .phy2rmii_crs_dv(phy2rmii_crs_dv), \/\/ input wire phy2rmii_crs_dv\n .phy2rmii_rx_er(phy2rmii_rx_er), \/\/ input wire phy2rmii_rx_er\n .phy2rmii_rxd(phy2rmii_rxd), \/\/ input wire [1 : 0] phy2rmii_rxd\n .rmii2phy_txd(rmii2phy_txd), \/\/ output wire [1 : 0] rmii2phy_txd\n .rmii2phy_tx_en(rmii2phy_tx_en) \/\/ output wire rmii2phy_tx_en\n);\n\/\/ INST_TAG_END ------ End INSTANTIATION Template ---------\n\n\/\/ You must compile the wrapper file ZynqDesign_mii_to_rmii_0_0.v when simulating\n\/\/ the core, ZynqDesign_mii_to_rmii_0_0. When compiling the wrapper file, be sure to\n\/\/ reference the Verilog simulation library.\n\n","avg_line_length":49.3536585366,"max_line_length":84,"alphanum_fraction":0.7417840376} {"size":3164,"ext":"veo","lang":"Verilog","max_stars_count":null,"content":"\/\/ (c) Copyright 1995-2018 Xilinx, Inc. All rights reserved.\n\/\/ \n\/\/ This file contains confidential and proprietary information\n\/\/ of Xilinx, Inc. and is protected under U.S. and\n\/\/ international copyright and other intellectual property\n\/\/ laws.\n\/\/ \n\/\/ DISCLAIMER\n\/\/ This disclaimer is not a license and does not grant any\n\/\/ rights to the materials distributed herewith. Except as\n\/\/ otherwise provided in a valid license issued to you by\n\/\/ Xilinx, and to the maximum extent permitted by applicable\n\/\/ law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n\/\/ WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n\/\/ AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n\/\/ BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n\/\/ INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n\/\/ (2) Xilinx shall not be liable (whether in contract or tort,\n\/\/ including negligence, or under any other theory of\n\/\/ liability) for any loss or damage of any kind or nature\n\/\/ related to, arising under or in connection with these\n\/\/ materials, including for any direct, or any indirect,\n\/\/ special, incidental, or consequential loss or damage\n\/\/ (including loss of data, profits, goodwill, or any type of\n\/\/ loss or damage suffered as a result of any action brought\n\/\/ by a third party) even if such damage or loss was\n\/\/ reasonably foreseeable or Xilinx had been advised of the\n\/\/ possibility of the same.\n\/\/ \n\/\/ CRITICAL APPLICATIONS\n\/\/ Xilinx products are not designed or intended to be fail-\n\/\/ safe, or for use in any application requiring fail-safe\n\/\/ performance, such as life-support or safety devices or\n\/\/ systems, Class III medical devices, nuclear facilities,\n\/\/ applications related to the deployment of airbags, or any\n\/\/ other applications that could lead to death, personal\n\/\/ injury, or severe property or environmental damage\n\/\/ (individually and collectively, \"Critical\n\/\/ Applications\"). Customer assumes the sole risk and\n\/\/ liability of any use of Xilinx products in Critical\n\/\/ Applications, subject only to applicable laws and\n\/\/ regulations governing limitations on product liability.\n\/\/ \n\/\/ THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n\/\/ PART OF THIS FILE AT ALL TIMES.\n\/\/ \n\/\/ DO NOT MODIFY THIS FILE.\n\n\/\/ IP VLNV: xilinx.com:ip:fifo_generator:13.1\n\/\/ IP Revision: 4\n\n\/\/ The following must be inserted into your Verilog file for this\n\/\/ core to be instantiated. Change the instance name and port connections\n\/\/ (in parentheses) to your own signal names.\n\n\/\/----------- Begin Cut here for INSTANTIATION Template ---\/\/ INST_TAG\nfifo_write your_instance_name (\n .clk(clk), \/\/ input wire clk\n .srst(srst), \/\/ input wire srst\n .din(din), \/\/ input wire [0 : 0] din\n .wr_en(wr_en), \/\/ input wire wr_en\n .rd_en(rd_en), \/\/ input wire rd_en\n .dout(dout), \/\/ output wire [7 : 0] dout\n .full(full), \/\/ output wire full\n .empty(empty) \/\/ output wire empty\n);\n\/\/ INST_TAG_END ------ End INSTANTIATION Template ---------\n\n\/\/ You must compile the wrapper file fifo_write.v when simulating\n\/\/ the core, fifo_write. When compiling the wrapper file, be sure to\n\/\/ reference the Verilog simulation library.\n\n","avg_line_length":43.3424657534,"max_line_length":73,"alphanum_fraction":0.7354614412} {"size":3563,"ext":"veo","lang":"Verilog","max_stars_count":17.0,"content":"\/\/ (c) Copyright 1995-2020 Xilinx, Inc. All rights reserved.\n\/\/ \n\/\/ This file contains confidential and proprietary information\n\/\/ of Xilinx, Inc. and is protected under U.S. and\n\/\/ international copyright and other intellectual property\n\/\/ laws.\n\/\/ \n\/\/ DISCLAIMER\n\/\/ This disclaimer is not a license and does not grant any\n\/\/ rights to the materials distributed herewith. Except as\n\/\/ otherwise provided in a valid license issued to you by\n\/\/ Xilinx, and to the maximum extent permitted by applicable\n\/\/ law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n\/\/ WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n\/\/ AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n\/\/ BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n\/\/ INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n\/\/ (2) Xilinx shall not be liable (whether in contract or tort,\n\/\/ including negligence, or under any other theory of\n\/\/ liability) for any loss or damage of any kind or nature\n\/\/ related to, arising under or in connection with these\n\/\/ materials, including for any direct, or any indirect,\n\/\/ special, incidental, or consequential loss or damage\n\/\/ (including loss of data, profits, goodwill, or any type of\n\/\/ loss or damage suffered as a result of any action brought\n\/\/ by a third party) even if such damage or loss was\n\/\/ reasonably foreseeable or Xilinx had been advised of the\n\/\/ possibility of the same.\n\/\/ \n\/\/ CRITICAL APPLICATIONS\n\/\/ Xilinx products are not designed or intended to be fail-\n\/\/ safe, or for use in any application requiring fail-safe\n\/\/ performance, such as life-support or safety devices or\n\/\/ systems, Class III medical devices, nuclear facilities,\n\/\/ applications related to the deployment of airbags, or any\n\/\/ other applications that could lead to death, personal\n\/\/ injury, or severe property or environmental damage\n\/\/ (individually and collectively, \"Critical\n\/\/ Applications\"). Customer assumes the sole risk and\n\/\/ liability of any use of Xilinx products in Critical\n\/\/ Applications, subject only to applicable laws and\n\/\/ regulations governing limitations on product liability.\n\/\/ \n\/\/ THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n\/\/ PART OF THIS FILE AT ALL TIMES.\n\/\/ \n\/\/ DO NOT MODIFY THIS FILE.\n\n\/\/ IP VLNV: xilinx.com:ip:fifo_generator:13.2\n\/\/ IP Revision: 5\n\n\/\/ The following must be inserted into your Verilog file for this\n\/\/ core to be instantiated. Change the instance name and port connections\n\/\/ (in parentheses) to your own signal names.\n\n\/\/----------- Begin Cut here for INSTANTIATION Template ---\/\/ INST_TAG\nfifo_generator_0 your_instance_name (\n .rst(rst), \/\/ input wire rst\n .wr_clk(wr_clk), \/\/ input wire wr_clk\n .rd_clk(rd_clk), \/\/ input wire rd_clk\n .din(din), \/\/ input wire [63 : 0] din\n .wr_en(wr_en), \/\/ input wire wr_en\n .rd_en(rd_en), \/\/ input wire rd_en\n .dout(dout), \/\/ output wire [15 : 0] dout\n .full(full), \/\/ output wire full\n .empty(empty), \/\/ output wire empty\n .rd_data_count(rd_data_count), \/\/ output wire [11 : 0] rd_data_count\n .wr_rst_busy(wr_rst_busy), \/\/ output wire wr_rst_busy\n .rd_rst_busy(rd_rst_busy) \/\/ output wire rd_rst_busy\n);\n\/\/ INST_TAG_END ------ End INSTANTIATION Template ---------\n\n\/\/ You must compile the wrapper file fifo_generator_0.v when simulating\n\/\/ the core, fifo_generator_0. When compiling the wrapper file, be sure to\n\/\/ reference the Verilog simulation library.\n\n","avg_line_length":46.2727272727,"max_line_length":74,"alphanum_fraction":0.7067078305} {"size":3023,"ext":"veo","lang":"Verilog","max_stars_count":1.0,"content":"\/\/ (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.\n\/\/ \n\/\/ This file contains confidential and proprietary information\n\/\/ of Xilinx, Inc. and is protected under U.S. and\n\/\/ international copyright and other intellectual property\n\/\/ laws.\n\/\/ \n\/\/ DISCLAIMER\n\/\/ This disclaimer is not a license and does not grant any\n\/\/ rights to the materials distributed herewith. Except as\n\/\/ otherwise provided in a valid license issued to you by\n\/\/ Xilinx, and to the maximum extent permitted by applicable\n\/\/ law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n\/\/ WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n\/\/ AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n\/\/ BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n\/\/ INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n\/\/ (2) Xilinx shall not be liable (whether in contract or tort,\n\/\/ including negligence, or under any other theory of\n\/\/ liability) for any loss or damage of any kind or nature\n\/\/ related to, arising under or in connection with these\n\/\/ materials, including for any direct, or any indirect,\n\/\/ special, incidental, or consequential loss or damage\n\/\/ (including loss of data, profits, goodwill, or any type of\n\/\/ loss or damage suffered as a result of any action brought\n\/\/ by a third party) even if such damage or loss was\n\/\/ reasonably foreseeable or Xilinx had been advised of the\n\/\/ possibility of the same.\n\/\/ \n\/\/ CRITICAL APPLICATIONS\n\/\/ Xilinx products are not designed or intended to be fail-\n\/\/ safe, or for use in any application requiring fail-safe\n\/\/ performance, such as life-support or safety devices or\n\/\/ systems, Class III medical devices, nuclear facilities,\n\/\/ applications related to the deployment of airbags, or any\n\/\/ other applications that could lead to death, personal\n\/\/ injury, or severe property or environmental damage\n\/\/ (individually and collectively, \"Critical\n\/\/ Applications\"). Customer assumes the sole risk and\n\/\/ liability of any use of Xilinx products in Critical\n\/\/ Applications, subject only to applicable laws and\n\/\/ regulations governing limitations on product liability.\n\/\/ \n\/\/ THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n\/\/ PART OF THIS FILE AT ALL TIMES.\n\/\/ \n\/\/ DO NOT MODIFY THIS FILE.\n\n\/\/ IP VLNV: xilinx.com:ip:blk_mem_gen:8.4\n\/\/ IP Revision: 3\n\n\/\/ The following must be inserted into your Verilog file for this\n\/\/ core to be instantiated. Change the instance name and port connections\n\/\/ (in parentheses) to your own signal names.\n\n\/\/----------- Begin Cut here for INSTANTIATION Template ---\/\/ INST_TAG\ncannonball_rom your_instance_name (\n .clka(clka), \/\/ input wire clka\n .ena(ena), \/\/ input wire ena\n .addra(addra), \/\/ input wire [10 : 0] addra\n .douta(douta) \/\/ output wire [3 : 0] douta\n);\n\/\/ INST_TAG_END ------ End INSTANTIATION Template ---------\n\n\/\/ You must compile the wrapper file cannonball_rom.v when simulating\n\/\/ the core, cannonball_rom. When compiling the wrapper file, be sure to\n\/\/ reference the Verilog simulation library.\n\n","avg_line_length":43.8115942029,"max_line_length":73,"alphanum_fraction":0.7442937479} {"size":3155,"ext":"veo","lang":"Verilog","max_stars_count":null,"content":"\/\/ (c) Copyright 1995-2020 Xilinx, Inc. All rights reserved.\n\/\/ \n\/\/ This file contains confidential and proprietary information\n\/\/ of Xilinx, Inc. and is protected under U.S. and\n\/\/ international copyright and other intellectual property\n\/\/ laws.\n\/\/ \n\/\/ DISCLAIMER\n\/\/ This disclaimer is not a license and does not grant any\n\/\/ rights to the materials distributed herewith. Except as\n\/\/ otherwise provided in a valid license issued to you by\n\/\/ Xilinx, and to the maximum extent permitted by applicable\n\/\/ law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n\/\/ WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n\/\/ AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n\/\/ BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n\/\/ INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n\/\/ (2) Xilinx shall not be liable (whether in contract or tort,\n\/\/ including negligence, or under any other theory of\n\/\/ liability) for any loss or damage of any kind or nature\n\/\/ related to, arising under or in connection with these\n\/\/ materials, including for any direct, or any indirect,\n\/\/ special, incidental, or consequential loss or damage\n\/\/ (including loss of data, profits, goodwill, or any type of\n\/\/ loss or damage suffered as a result of any action brought\n\/\/ by a third party) even if such damage or loss was\n\/\/ reasonably foreseeable or Xilinx had been advised of the\n\/\/ possibility of the same.\n\/\/ \n\/\/ CRITICAL APPLICATIONS\n\/\/ Xilinx products are not designed or intended to be fail-\n\/\/ safe, or for use in any application requiring fail-safe\n\/\/ performance, such as life-support or safety devices or\n\/\/ systems, Class III medical devices, nuclear facilities,\n\/\/ applications related to the deployment of airbags, or any\n\/\/ other applications that could lead to death, personal\n\/\/ injury, or severe property or environmental damage\n\/\/ (individually and collectively, \"Critical\n\/\/ Applications\"). Customer assumes the sole risk and\n\/\/ liability of any use of Xilinx products in Critical\n\/\/ Applications, subject only to applicable laws and\n\/\/ regulations governing limitations on product liability.\n\/\/ \n\/\/ THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n\/\/ PART OF THIS FILE AT ALL TIMES.\n\/\/ \n\/\/ DO NOT MODIFY THIS FILE.\n\n\/\/ IP VLNV: xilinx.com:ip:blk_mem_gen:8.4\n\/\/ IP Revision: 2\n\n\/\/ The following must be inserted into your Verilog file for this\n\/\/ core to be instantiated. Change the instance name and port connections\n\/\/ (in parentheses) to your own signal names.\n\n\/\/----------- Begin Cut here for INSTANTIATION Template ---\/\/ INST_TAG\nblk_mem_gen_0 your_instance_name (\n .clka(clka), \/\/ input wire clka\n .wea(wea), \/\/ input wire [0 : 0] wea\n .addra(addra), \/\/ input wire [9 : 0] addra\n .dina(dina), \/\/ input wire [7 : 0] dina\n .clkb(clkb), \/\/ input wire clkb\n .addrb(addrb), \/\/ input wire [9 : 0] addrb\n .doutb(doutb) \/\/ output wire [7 : 0] doutb\n);\n\/\/ INST_TAG_END ------ End INSTANTIATION Template ---------\n\n\/\/ You must compile the wrapper file blk_mem_gen_0.v when simulating\n\/\/ the core, blk_mem_gen_0. When compiling the wrapper file, be sure to\n\/\/ reference the Verilog simulation library.\n\n","avg_line_length":43.8194444444,"max_line_length":73,"alphanum_fraction":0.7347068146} {"size":8338,"ext":"veo","lang":"Verilog","max_stars_count":21.0,"content":"\/\/ (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.\n\/\/ \n\/\/ This file contains confidential and proprietary information\n\/\/ of Xilinx, Inc. and is protected under U.S. and\n\/\/ international copyright and other intellectual property\n\/\/ laws.\n\/\/ \n\/\/ DISCLAIMER\n\/\/ This disclaimer is not a license and does not grant any\n\/\/ rights to the materials distributed herewith. Except as\n\/\/ otherwise provided in a valid license issued to you by\n\/\/ Xilinx, and to the maximum extent permitted by applicable\n\/\/ law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n\/\/ WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n\/\/ AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n\/\/ BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n\/\/ INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n\/\/ (2) Xilinx shall not be liable (whether in contract or tort,\n\/\/ including negligence, or under any other theory of\n\/\/ liability) for any loss or damage of any kind or nature\n\/\/ related to, arising under or in connection with these\n\/\/ materials, including for any direct, or any indirect,\n\/\/ special, incidental, or consequential loss or damage\n\/\/ (including loss of data, profits, goodwill, or any type of\n\/\/ loss or damage suffered as a result of any action brought\n\/\/ by a third party) even if such damage or loss was\n\/\/ reasonably foreseeable or Xilinx had been advised of the\n\/\/ possibility of the same.\n\/\/ \n\/\/ CRITICAL APPLICATIONS\n\/\/ Xilinx products are not designed or intended to be fail-\n\/\/ safe, or for use in any application requiring fail-safe\n\/\/ performance, such as life-support or safety devices or\n\/\/ systems, Class III medical devices, nuclear facilities,\n\/\/ applications related to the deployment of airbags, or any\n\/\/ other applications that could lead to death, personal\n\/\/ injury, or severe property or environmental damage\n\/\/ (individually and collectively, \"Critical\n\/\/ Applications\"). Customer assumes the sole risk and\n\/\/ liability of any use of Xilinx products in Critical\n\/\/ Applications, subject only to applicable laws and\n\/\/ regulations governing limitations on product liability.\n\/\/ \n\/\/ THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n\/\/ PART OF THIS FILE AT ALL TIMES.\n\/\/ \n\/\/ DO NOT MODIFY THIS FILE.\n\n\/\/ IP VLNV: xilinx.com:ip:processing_system7:5.5\n\/\/ IP Revision: 3\n\n\/\/ The following must be inserted into your Verilog file for this\n\/\/ core to be instantiated. Change the instance name and port connections\n\/\/ (in parentheses) to your own signal names.\n\n\/\/----------- Begin Cut here for INSTANTIATION Template ---\/\/ INST_TAG\nZynqDesign_processing_system7_0_0 your_instance_name (\n .TTC0_WAVE0_OUT(TTC0_WAVE0_OUT), \/\/ output wire TTC0_WAVE0_OUT\n .TTC0_WAVE1_OUT(TTC0_WAVE1_OUT), \/\/ output wire TTC0_WAVE1_OUT\n .TTC0_WAVE2_OUT(TTC0_WAVE2_OUT), \/\/ output wire TTC0_WAVE2_OUT\n .USB0_PORT_INDCTL(USB0_PORT_INDCTL), \/\/ output wire [1 : 0] USB0_PORT_INDCTL\n .USB0_VBUS_PWRSELECT(USB0_VBUS_PWRSELECT), \/\/ output wire USB0_VBUS_PWRSELECT\n .USB0_VBUS_PWRFAULT(USB0_VBUS_PWRFAULT), \/\/ input wire USB0_VBUS_PWRFAULT\n .M_AXI_GP0_ARVALID(M_AXI_GP0_ARVALID), \/\/ output wire M_AXI_GP0_ARVALID\n .M_AXI_GP0_AWVALID(M_AXI_GP0_AWVALID), \/\/ output wire M_AXI_GP0_AWVALID\n .M_AXI_GP0_BREADY(M_AXI_GP0_BREADY), \/\/ output wire M_AXI_GP0_BREADY\n .M_AXI_GP0_RREADY(M_AXI_GP0_RREADY), \/\/ output wire M_AXI_GP0_RREADY\n .M_AXI_GP0_WLAST(M_AXI_GP0_WLAST), \/\/ output wire M_AXI_GP0_WLAST\n .M_AXI_GP0_WVALID(M_AXI_GP0_WVALID), \/\/ output wire M_AXI_GP0_WVALID\n .M_AXI_GP0_ARID(M_AXI_GP0_ARID), \/\/ output wire [11 : 0] M_AXI_GP0_ARID\n .M_AXI_GP0_AWID(M_AXI_GP0_AWID), \/\/ output wire [11 : 0] M_AXI_GP0_AWID\n .M_AXI_GP0_WID(M_AXI_GP0_WID), \/\/ output wire [11 : 0] M_AXI_GP0_WID\n .M_AXI_GP0_ARBURST(M_AXI_GP0_ARBURST), \/\/ output wire [1 : 0] M_AXI_GP0_ARBURST\n .M_AXI_GP0_ARLOCK(M_AXI_GP0_ARLOCK), \/\/ output wire [1 : 0] M_AXI_GP0_ARLOCK\n .M_AXI_GP0_ARSIZE(M_AXI_GP0_ARSIZE), \/\/ output wire [2 : 0] M_AXI_GP0_ARSIZE\n .M_AXI_GP0_AWBURST(M_AXI_GP0_AWBURST), \/\/ output wire [1 : 0] M_AXI_GP0_AWBURST\n .M_AXI_GP0_AWLOCK(M_AXI_GP0_AWLOCK), \/\/ output wire [1 : 0] M_AXI_GP0_AWLOCK\n .M_AXI_GP0_AWSIZE(M_AXI_GP0_AWSIZE), \/\/ output wire [2 : 0] M_AXI_GP0_AWSIZE\n .M_AXI_GP0_ARPROT(M_AXI_GP0_ARPROT), \/\/ output wire [2 : 0] M_AXI_GP0_ARPROT\n .M_AXI_GP0_AWPROT(M_AXI_GP0_AWPROT), \/\/ output wire [2 : 0] M_AXI_GP0_AWPROT\n .M_AXI_GP0_ARADDR(M_AXI_GP0_ARADDR), \/\/ output wire [31 : 0] M_AXI_GP0_ARADDR\n .M_AXI_GP0_AWADDR(M_AXI_GP0_AWADDR), \/\/ output wire [31 : 0] M_AXI_GP0_AWADDR\n .M_AXI_GP0_WDATA(M_AXI_GP0_WDATA), \/\/ output wire [31 : 0] M_AXI_GP0_WDATA\n .M_AXI_GP0_ARCACHE(M_AXI_GP0_ARCACHE), \/\/ output wire [3 : 0] M_AXI_GP0_ARCACHE\n .M_AXI_GP0_ARLEN(M_AXI_GP0_ARLEN), \/\/ output wire [3 : 0] M_AXI_GP0_ARLEN\n .M_AXI_GP0_ARQOS(M_AXI_GP0_ARQOS), \/\/ output wire [3 : 0] M_AXI_GP0_ARQOS\n .M_AXI_GP0_AWCACHE(M_AXI_GP0_AWCACHE), \/\/ output wire [3 : 0] M_AXI_GP0_AWCACHE\n .M_AXI_GP0_AWLEN(M_AXI_GP0_AWLEN), \/\/ output wire [3 : 0] M_AXI_GP0_AWLEN\n .M_AXI_GP0_AWQOS(M_AXI_GP0_AWQOS), \/\/ output wire [3 : 0] M_AXI_GP0_AWQOS\n .M_AXI_GP0_WSTRB(M_AXI_GP0_WSTRB), \/\/ output wire [3 : 0] M_AXI_GP0_WSTRB\n .M_AXI_GP0_ACLK(M_AXI_GP0_ACLK), \/\/ input wire M_AXI_GP0_ACLK\n .M_AXI_GP0_ARREADY(M_AXI_GP0_ARREADY), \/\/ input wire M_AXI_GP0_ARREADY\n .M_AXI_GP0_AWREADY(M_AXI_GP0_AWREADY), \/\/ input wire M_AXI_GP0_AWREADY\n .M_AXI_GP0_BVALID(M_AXI_GP0_BVALID), \/\/ input wire M_AXI_GP0_BVALID\n .M_AXI_GP0_RLAST(M_AXI_GP0_RLAST), \/\/ input wire M_AXI_GP0_RLAST\n .M_AXI_GP0_RVALID(M_AXI_GP0_RVALID), \/\/ input wire M_AXI_GP0_RVALID\n .M_AXI_GP0_WREADY(M_AXI_GP0_WREADY), \/\/ input wire M_AXI_GP0_WREADY\n .M_AXI_GP0_BID(M_AXI_GP0_BID), \/\/ input wire [11 : 0] M_AXI_GP0_BID\n .M_AXI_GP0_RID(M_AXI_GP0_RID), \/\/ input wire [11 : 0] M_AXI_GP0_RID\n .M_AXI_GP0_BRESP(M_AXI_GP0_BRESP), \/\/ input wire [1 : 0] M_AXI_GP0_BRESP\n .M_AXI_GP0_RRESP(M_AXI_GP0_RRESP), \/\/ input wire [1 : 0] M_AXI_GP0_RRESP\n .M_AXI_GP0_RDATA(M_AXI_GP0_RDATA), \/\/ input wire [31 : 0] M_AXI_GP0_RDATA\n .FCLK_CLK0(FCLK_CLK0), \/\/ output wire FCLK_CLK0\n .FCLK_CLK1(FCLK_CLK1), \/\/ output wire FCLK_CLK1\n .FCLK_RESET0_N(FCLK_RESET0_N), \/\/ output wire FCLK_RESET0_N\n .MIO(MIO), \/\/ inout wire [53 : 0] MIO\n .DDR_CAS_n(DDR_CAS_n), \/\/ inout wire DDR_CAS_n\n .DDR_CKE(DDR_CKE), \/\/ inout wire DDR_CKE\n .DDR_Clk_n(DDR_Clk_n), \/\/ inout wire DDR_Clk_n\n .DDR_Clk(DDR_Clk), \/\/ inout wire DDR_Clk\n .DDR_CS_n(DDR_CS_n), \/\/ inout wire DDR_CS_n\n .DDR_DRSTB(DDR_DRSTB), \/\/ inout wire DDR_DRSTB\n .DDR_ODT(DDR_ODT), \/\/ inout wire DDR_ODT\n .DDR_RAS_n(DDR_RAS_n), \/\/ inout wire DDR_RAS_n\n .DDR_WEB(DDR_WEB), \/\/ inout wire DDR_WEB\n .DDR_BankAddr(DDR_BankAddr), \/\/ inout wire [2 : 0] DDR_BankAddr\n .DDR_Addr(DDR_Addr), \/\/ inout wire [14 : 0] DDR_Addr\n .DDR_VRN(DDR_VRN), \/\/ inout wire DDR_VRN\n .DDR_VRP(DDR_VRP), \/\/ inout wire DDR_VRP\n .DDR_DM(DDR_DM), \/\/ inout wire [3 : 0] DDR_DM\n .DDR_DQ(DDR_DQ), \/\/ inout wire [31 : 0] DDR_DQ\n .DDR_DQS_n(DDR_DQS_n), \/\/ inout wire [3 : 0] DDR_DQS_n\n .DDR_DQS(DDR_DQS), \/\/ inout wire [3 : 0] DDR_DQS\n .PS_SRSTB(PS_SRSTB), \/\/ inout wire PS_SRSTB\n .PS_CLK(PS_CLK), \/\/ inout wire PS_CLK\n .PS_PORB(PS_PORB) \/\/ inout wire PS_PORB\n);\n\/\/ INST_TAG_END ------ End INSTANTIATION Template ---------\n\n\/\/ You must compile the wrapper file ZynqDesign_processing_system7_0_0.v when simulating\n\/\/ the core, ZynqDesign_processing_system7_0_0. When compiling the wrapper file, be sure to\n\/\/ reference the Verilog simulation library.\n\n","avg_line_length":62.223880597,"max_line_length":91,"alphanum_fraction":0.6748620772} {"size":3074,"ext":"veo","lang":"Verilog","max_stars_count":null,"content":"\/\/ (c) Copyright 1995-2020 Xilinx, Inc. All rights reserved.\n\/\/ \n\/\/ This file contains confidential and proprietary information\n\/\/ of Xilinx, Inc. and is protected under U.S. and\n\/\/ international copyright and other intellectual property\n\/\/ laws.\n\/\/ \n\/\/ DISCLAIMER\n\/\/ This disclaimer is not a license and does not grant any\n\/\/ rights to the materials distributed herewith. Except as\n\/\/ otherwise provided in a valid license issued to you by\n\/\/ Xilinx, and to the maximum extent permitted by applicable\n\/\/ law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n\/\/ WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n\/\/ AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n\/\/ BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n\/\/ INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n\/\/ (2) Xilinx shall not be liable (whether in contract or tort,\n\/\/ including negligence, or under any other theory of\n\/\/ liability) for any loss or damage of any kind or nature\n\/\/ related to, arising under or in connection with these\n\/\/ materials, including for any direct, or any indirect,\n\/\/ special, incidental, or consequential loss or damage\n\/\/ (including loss of data, profits, goodwill, or any type of\n\/\/ loss or damage suffered as a result of any action brought\n\/\/ by a third party) even if such damage or loss was\n\/\/ reasonably foreseeable or Xilinx had been advised of the\n\/\/ possibility of the same.\n\/\/ \n\/\/ CRITICAL APPLICATIONS\n\/\/ Xilinx products are not designed or intended to be fail-\n\/\/ safe, or for use in any application requiring fail-safe\n\/\/ performance, such as life-support or safety devices or\n\/\/ systems, Class III medical devices, nuclear facilities,\n\/\/ applications related to the deployment of airbags, or any\n\/\/ other applications that could lead to death, personal\n\/\/ injury, or severe property or environmental damage\n\/\/ (individually and collectively, \"Critical\n\/\/ Applications\"). Customer assumes the sole risk and\n\/\/ liability of any use of Xilinx products in Critical\n\/\/ Applications, subject only to applicable laws and\n\/\/ regulations governing limitations on product liability.\n\/\/ \n\/\/ THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n\/\/ PART OF THIS FILE AT ALL TIMES.\n\/\/ \n\/\/ DO NOT MODIFY THIS FILE.\n\n\/\/ IP VLNV: xilinx.com:ip:blk_mem_gen:8.4\n\/\/ IP Revision: 4\n\n\/\/ The following must be inserted into your Verilog file for this\n\/\/ core to be instantiated. Change the instance name and port connections\n\/\/ (in parentheses) to your own signal names.\n\n\/\/----------- Begin Cut here for INSTANTIATION Template ---\/\/ INST_TAG\nblk_mem_gen_0 your_instance_name (\n .clka(clka), \/\/ input wire clka\n .wea(wea), \/\/ input wire [0 : 0] wea\n .addra(addra), \/\/ input wire [9 : 0] addra\n .dina(dina), \/\/ input wire [15 : 0] dina\n .douta(douta) \/\/ output wire [15 : 0] douta\n);\n\/\/ INST_TAG_END ------ End INSTANTIATION Template ---------\n\n\/\/ You must compile the wrapper file blk_mem_gen_0.v when simulating\n\/\/ the core, blk_mem_gen_0. When compiling the wrapper file, be sure to\n\/\/ reference the Verilog simulation library.\n\n","avg_line_length":43.9142857143,"max_line_length":73,"alphanum_fraction":0.7394274561} {"size":4998,"ext":"veo","lang":"Verilog","max_stars_count":1.0,"content":"\/\/ (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.\r\n\/\/ \r\n\/\/ This file contains confidential and proprietary information\r\n\/\/ of Xilinx, Inc. and is protected under U.S. and\r\n\/\/ international copyright and other intellectual property\r\n\/\/ laws.\r\n\/\/ \r\n\/\/ DISCLAIMER\r\n\/\/ This disclaimer is not a license and does not grant any\r\n\/\/ rights to the materials distributed herewith. Except as\r\n\/\/ otherwise provided in a valid license issued to you by\r\n\/\/ Xilinx, and to the maximum extent permitted by applicable\r\n\/\/ law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\r\n\/\/ WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\r\n\/\/ AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\r\n\/\/ BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\r\n\/\/ INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\r\n\/\/ (2) Xilinx shall not be liable (whether in contract or tort,\r\n\/\/ including negligence, or under any other theory of\r\n\/\/ liability) for any loss or damage of any kind or nature\r\n\/\/ related to, arising under or in connection with these\r\n\/\/ materials, including for any direct, or any indirect,\r\n\/\/ special, incidental, or consequential loss or damage\r\n\/\/ (including loss of data, profits, goodwill, or any type of\r\n\/\/ loss or damage suffered as a result of any action brought\r\n\/\/ by a third party) even if such damage or loss was\r\n\/\/ reasonably foreseeable or Xilinx had been advised of the\r\n\/\/ possibility of the same.\r\n\/\/ \r\n\/\/ CRITICAL APPLICATIONS\r\n\/\/ Xilinx products are not designed or intended to be fail-\r\n\/\/ safe, or for use in any application requiring fail-safe\r\n\/\/ performance, such as life-support or safety devices or\r\n\/\/ systems, Class III medical devices, nuclear facilities,\r\n\/\/ applications related to the deployment of airbags, or any\r\n\/\/ other applications that could lead to death, personal\r\n\/\/ injury, or severe property or environmental damage\r\n\/\/ (individually and collectively, \"Critical\r\n\/\/ Applications\"). Customer assumes the sole risk and\r\n\/\/ liability of any use of Xilinx products in Critical\r\n\/\/ Applications, subject only to applicable laws and\r\n\/\/ regulations governing limitations on product liability.\r\n\/\/ \r\n\/\/ THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\r\n\/\/ PART OF THIS FILE AT ALL TIMES.\r\n\/\/ \r\n\/\/ DO NOT MODIFY THIS FILE.\r\n\r\n\/\/ IP VLNV: xilinx.com:ip:axi_quad_spi:3.2\r\n\/\/ IP Revision: 6\r\n\r\n\/\/ The following must be inserted into your Verilog file for this\r\n\/\/ core to be instantiated. Change the instance name and port connections\r\n\/\/ (in parentheses) to your own signal names.\r\n\r\n\/\/----------- Begin Cut here for INSTANTIATION Template ---\/\/ INST_TAG\r\nPmodAD1_axi_quad_spi_0_0 your_instance_name (\r\n .ext_spi_clk(ext_spi_clk), \/\/ input wire ext_spi_clk\r\n .s_axi_aclk(s_axi_aclk), \/\/ input wire s_axi_aclk\r\n .s_axi_aresetn(s_axi_aresetn), \/\/ input wire s_axi_aresetn\r\n .s_axi_awaddr(s_axi_awaddr), \/\/ input wire [6 : 0] s_axi_awaddr\r\n .s_axi_awvalid(s_axi_awvalid), \/\/ input wire s_axi_awvalid\r\n .s_axi_awready(s_axi_awready), \/\/ output wire s_axi_awready\r\n .s_axi_wdata(s_axi_wdata), \/\/ input wire [31 : 0] s_axi_wdata\r\n .s_axi_wstrb(s_axi_wstrb), \/\/ input wire [3 : 0] s_axi_wstrb\r\n .s_axi_wvalid(s_axi_wvalid), \/\/ input wire s_axi_wvalid\r\n .s_axi_wready(s_axi_wready), \/\/ output wire s_axi_wready\r\n .s_axi_bresp(s_axi_bresp), \/\/ output wire [1 : 0] s_axi_bresp\r\n .s_axi_bvalid(s_axi_bvalid), \/\/ output wire s_axi_bvalid\r\n .s_axi_bready(s_axi_bready), \/\/ input wire s_axi_bready\r\n .s_axi_araddr(s_axi_araddr), \/\/ input wire [6 : 0] s_axi_araddr\r\n .s_axi_arvalid(s_axi_arvalid), \/\/ input wire s_axi_arvalid\r\n .s_axi_arready(s_axi_arready), \/\/ output wire s_axi_arready\r\n .s_axi_rdata(s_axi_rdata), \/\/ output wire [31 : 0] s_axi_rdata\r\n .s_axi_rresp(s_axi_rresp), \/\/ output wire [1 : 0] s_axi_rresp\r\n .s_axi_rvalid(s_axi_rvalid), \/\/ output wire s_axi_rvalid\r\n .s_axi_rready(s_axi_rready), \/\/ input wire s_axi_rready\r\n .io0_i(io0_i), \/\/ input wire io0_i\r\n .io0_o(io0_o), \/\/ output wire io0_o\r\n .io0_t(io0_t), \/\/ output wire io0_t\r\n .io1_i(io1_i), \/\/ input wire io1_i\r\n .io1_o(io1_o), \/\/ output wire io1_o\r\n .io1_t(io1_t), \/\/ output wire io1_t\r\n .sck_i(sck_i), \/\/ input wire sck_i\r\n .sck_o(sck_o), \/\/ output wire sck_o\r\n .sck_t(sck_t), \/\/ output wire sck_t\r\n .ss_i(ss_i), \/\/ input wire [0 : 0] ss_i\r\n .ss_o(ss_o), \/\/ output wire [0 : 0] ss_o\r\n .ss_t(ss_t), \/\/ output wire ss_t\r\n .ip2intc_irpt(ip2intc_irpt) \/\/ output wire ip2intc_irpt\r\n);\r\n\/\/ INST_TAG_END ------ End INSTANTIATION Template ---------\r\n\r\n\/\/ You must compile the wrapper file PmodAD1_axi_quad_spi_0_0.v when simulating\r\n\/\/ the core, PmodAD1_axi_quad_spi_0_0. When compiling the wrapper file, be sure to\r\n\/\/ reference the Verilog simulation library.\r\n\r\n","avg_line_length":51.0,"max_line_length":83,"alphanum_fraction":0.6882753101} {"size":4209,"ext":"veo","lang":"Verilog","max_stars_count":4.0,"content":"\/*******************************************************************************\r\n* This file is owned and controlled by Xilinx and must be used solely *\r\n* for design, simulation, implementation and creation of design files *\r\n* limited to Xilinx devices or technologies. Use with non-Xilinx *\r\n* devices or technologies is expressly prohibited and immediately *\r\n* terminates your license. *\r\n* *\r\n* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION \"AS IS\" SOLELY *\r\n* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY *\r\n* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE *\r\n* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS *\r\n* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY *\r\n* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY *\r\n* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY *\r\n* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *\r\n* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *\r\n* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *\r\n* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *\r\n* PARTICULAR PURPOSE. *\r\n* *\r\n* Xilinx products are not intended for use in life support appliances, *\r\n* devices, or systems. Use in such applications are expressly *\r\n* prohibited. *\r\n* *\r\n* (c) Copyright 1995-2020 Xilinx, Inc. *\r\n* All rights reserved. *\r\n*******************************************************************************\/\r\n\r\n\/*******************************************************************************\r\n* Generated from core with identifier: xilinx.com:ip:blk_mem_gen:7.3 *\r\n* *\r\n* The Xilinx LogiCORE IP Block Memory Generator replaces the Dual Port *\r\n* Block Memory and Single Port Block Memory LogiCOREs, but is not a *\r\n* direct drop-in replacement. It should be used in all new Xilinx *\r\n* designs. The core supports RAM and ROM functions over a wide range of *\r\n* widths and depths. Use this core to generate block memories with *\r\n* symmetric or asymmetric read and write port widths, as well as cores *\r\n* which can perform simultaneous write operations to separate *\r\n* locations, and simultaneous read operations from the same location. *\r\n* For more information on differences in interface and feature support *\r\n* between this core and the Dual Port Block Memory and Single Port *\r\n* Block Memory LogiCOREs, please consult the data sheet. *\r\n*******************************************************************************\/\r\n\r\n\/\/ The following must be inserted into your Verilog file for this\r\n\/\/ core to be instantiated. Change the instance name and port connections\r\n\/\/ (in parentheses) to your own signal names.\r\n\r\n\/\/----------- Begin Cut here for INSTANTIATION Template ---\/\/ INST_TAG\r\nProgram_Memory your_instance_name (\r\n .clka(clka), \/\/ input clka\r\n .addra(addra), \/\/ input [7 : 0] addra\r\n .douta(douta) \/\/ output [23 : 0] douta\r\n);\r\n\/\/ INST_TAG_END ------ End INSTANTIATION Template ---------\r\n\r\n\/\/ You must compile the wrapper file Program_Memory.v when simulating\r\n\/\/ the core, Program_Memory. When compiling the wrapper file, be sure to\r\n\/\/ reference the XilinxCoreLib Verilog simulation library. For detailed\r\n\/\/ instructions, please refer to the \"CORE Generator Help\".\r\n\r\n","avg_line_length":67.8870967742,"max_line_length":81,"alphanum_fraction":0.5255405084} {"size":3703,"ext":"veo","lang":"Verilog","max_stars_count":72.0,"content":"\/\/ (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.\n\/\/ \n\/\/ This file contains confidential and proprietary information\n\/\/ of Xilinx, Inc. and is protected under U.S. and\n\/\/ international copyright and other intellectual property\n\/\/ laws.\n\/\/ \n\/\/ DISCLAIMER\n\/\/ This disclaimer is not a license and does not grant any\n\/\/ rights to the materials distributed herewith. Except as\n\/\/ otherwise provided in a valid license issued to you by\n\/\/ Xilinx, and to the maximum extent permitted by applicable\n\/\/ law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n\/\/ WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n\/\/ AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n\/\/ BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n\/\/ INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n\/\/ (2) Xilinx shall not be liable (whether in contract or tort,\n\/\/ including negligence, or under any other theory of\n\/\/ liability) for any loss or damage of any kind or nature\n\/\/ related to, arising under or in connection with these\n\/\/ materials, including for any direct, or any indirect,\n\/\/ special, incidental, or consequential loss or damage\n\/\/ (including loss of data, profits, goodwill, or any type of\n\/\/ loss or damage suffered as a result of any action brought\n\/\/ by a third party) even if such damage or loss was\n\/\/ reasonably foreseeable or Xilinx had been advised of the\n\/\/ possibility of the same.\n\/\/ \n\/\/ CRITICAL APPLICATIONS\n\/\/ Xilinx products are not designed or intended to be fail-\n\/\/ safe, or for use in any application requiring fail-safe\n\/\/ performance, such as life-support or safety devices or\n\/\/ systems, Class III medical devices, nuclear facilities,\n\/\/ applications related to the deployment of airbags, or any\n\/\/ other applications that could lead to death, personal\n\/\/ injury, or severe property or environmental damage\n\/\/ (individually and collectively, \"Critical\n\/\/ Applications\"). Customer assumes the sole risk and\n\/\/ liability of any use of Xilinx products in Critical\n\/\/ Applications, subject only to applicable laws and\n\/\/ regulations governing limitations on product liability.\n\/\/ \n\/\/ THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n\/\/ PART OF THIS FILE AT ALL TIMES.\n\/\/ \n\/\/ DO NOT MODIFY THIS FILE.\n\n\/\/ IP VLNV: xilinx.com:ip:proc_sys_reset:5.0\n\/\/ IP Revision: 7\n\n\/\/ The following must be inserted into your Verilog file for this\n\/\/ core to be instantiated. Change the instance name and port connections\n\/\/ (in parentheses) to your own signal names.\n\n\/\/----------- Begin Cut here for INSTANTIATION Template ---\/\/ INST_TAG\nz_turn_proc_sys_reset_3_0 your_instance_name (\n .slowest_sync_clk(slowest_sync_clk), \/\/ input wire slowest_sync_clk\n .ext_reset_in(ext_reset_in), \/\/ input wire ext_reset_in\n .aux_reset_in(aux_reset_in), \/\/ input wire aux_reset_in\n .mb_debug_sys_rst(mb_debug_sys_rst), \/\/ input wire mb_debug_sys_rst\n .dcm_locked(dcm_locked), \/\/ input wire dcm_locked\n .mb_reset(mb_reset), \/\/ output wire mb_reset\n .bus_struct_reset(bus_struct_reset), \/\/ output wire [0 : 0] bus_struct_reset\n .peripheral_reset(peripheral_reset), \/\/ output wire [0 : 0] peripheral_reset\n .interconnect_aresetn(interconnect_aresetn), \/\/ output wire [0 : 0] interconnect_aresetn\n .peripheral_aresetn(peripheral_aresetn) \/\/ output wire [0 : 0] peripheral_aresetn\n);\n\/\/ INST_TAG_END ------ End INSTANTIATION Template ---------\n\n\/\/ You must compile the wrapper file z_turn_proc_sys_reset_3_0.v when simulating\n\/\/ the core, z_turn_proc_sys_reset_3_0. When compiling the wrapper file, be sure to\n\/\/ reference the Verilog simulation library.\n\n","avg_line_length":49.3733333333,"max_line_length":91,"alphanum_fraction":0.736699973} {"size":3238,"ext":"veo","lang":"Verilog","max_stars_count":9.0,"content":"\/\/ (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.\n\/\/ \n\/\/ This file contains confidential and proprietary information\n\/\/ of Xilinx, Inc. and is protected under U.S. and\n\/\/ international copyright and other intellectual property\n\/\/ laws.\n\/\/ \n\/\/ DISCLAIMER\n\/\/ This disclaimer is not a license and does not grant any\n\/\/ rights to the materials distributed herewith. Except as\n\/\/ otherwise provided in a valid license issued to you by\n\/\/ Xilinx, and to the maximum extent permitted by applicable\n\/\/ law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n\/\/ WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n\/\/ AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n\/\/ BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n\/\/ INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n\/\/ (2) Xilinx shall not be liable (whether in contract or tort,\n\/\/ including negligence, or under any other theory of\n\/\/ liability) for any loss or damage of any kind or nature\n\/\/ related to, arising under or in connection with these\n\/\/ materials, including for any direct, or any indirect,\n\/\/ special, incidental, or consequential loss or damage\n\/\/ (including loss of data, profits, goodwill, or any type of\n\/\/ loss or damage suffered as a result of any action brought\n\/\/ by a third party) even if such damage or loss was\n\/\/ reasonably foreseeable or Xilinx had been advised of the\n\/\/ possibility of the same.\n\/\/ \n\/\/ CRITICAL APPLICATIONS\n\/\/ Xilinx products are not designed or intended to be fail-\n\/\/ safe, or for use in any application requiring fail-safe\n\/\/ performance, such as life-support or safety devices or\n\/\/ systems, Class III medical devices, nuclear facilities,\n\/\/ applications related to the deployment of airbags, or any\n\/\/ other applications that could lead to death, personal\n\/\/ injury, or severe property or environmental damage\n\/\/ (individually and collectively, \"Critical\n\/\/ Applications\"). Customer assumes the sole risk and\n\/\/ liability of any use of Xilinx products in Critical\n\/\/ Applications, subject only to applicable laws and\n\/\/ regulations governing limitations on product liability.\n\/\/ \n\/\/ THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n\/\/ PART OF THIS FILE AT ALL TIMES.\n\/\/ \n\/\/ DO NOT MODIFY THIS FILE.\n\n\/\/ IP VLNV: xilinx.com:ip:blk_mem_gen:8.2\n\/\/ IP Revision: 3\n\n\/\/ The following must be inserted into your Verilog file for this\n\/\/ core to be instantiated. Change the instance name and port connections\n\/\/ (in parentheses) to your own signal names.\n\n\/\/----------- Begin Cut here for INSTANTIATION Template ---\/\/ INST_TAG\nipcore_bram_gps_16k_1b_4k_4b your_instance_name (\n .clka(clka), \/\/ input wire clka\n .ena(ena), \/\/ input wire ena\n .wea(wea), \/\/ input wire [0 : 0] wea\n .addra(addra), \/\/ input wire [13 : 0] addra\n .dina(dina), \/\/ input wire [0 : 0] dina\n .clkb(clkb), \/\/ input wire clkb\n .addrb(addrb), \/\/ input wire [11 : 0] addrb\n .doutb(doutb) \/\/ output wire [3 : 0] doutb\n);\n\/\/ INST_TAG_END ------ End INSTANTIATION Template ---------\n\n\/\/ You must compile the wrapper file ipcore_bram_gps_16k_1b_4k_4b.v when simulating\n\/\/ the core, ipcore_bram_gps_16k_1b_4k_4b. When compiling the wrapper file, be sure to\n\/\/ reference the Verilog simulation library.\n\n","avg_line_length":44.3561643836,"max_line_length":86,"alphanum_fraction":0.7359481161} {"size":2985,"ext":"veo","lang":"Verilog","max_stars_count":1.0,"content":"\/\/ (c) Copyright 1995-2012 Xilinx, Inc. All rights reserved.\n\/\/\n\/\/ This file contains confidential and proprietary information\n\/\/ of Xilinx, Inc. and is protected under U.S. and\n\/\/ international copyright and other intellectual property\n\/\/ laws.\n\/\/\n\/\/ DISCLAIMER\n\/\/ This disclaimer is not a license and does not grant any\n\/\/ rights to the materials distributed herewith. Except as\n\/\/ otherwise provided in a valid license issued to you by\n\/\/ Xilinx, and to the maximum extent permitted by applicable\n\/\/ law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n\/\/ WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n\/\/ AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n\/\/ BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n\/\/ INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n\/\/ (2) Xilinx shall not be liable (whether in contract or tort,\n\/\/ including negligence, or under any other theory of\n\/\/ liability) for any loss or damage of any kind or nature\n\/\/ related to, arising under or in connection with these\n\/\/ materials, including for any direct, or any indirect,\n\/\/ special, incidental, or consequential loss or damage\n\/\/ (including loss of data, profits, goodwill, or any type of\n\/\/ loss or damage suffered as a result of any action brought\n\/\/ by a third party) even if such damage or loss was\n\/\/ reasonably foreseeable or Xilinx had been advised of the\n\/\/ possibility of the same.\n\/\/\n\/\/ CRITICAL APPLICATIONS\n\/\/ Xilinx products are not designed or intended to be fail-\n\/\/ safe, or for use in any application requiring fail-safe\n\/\/ performance, such as life-support or safety devices or\n\/\/ systems, Class III medical devices, nuclear facilities,\n\/\/ applications related to the deployment of airbags, or any\n\/\/ other applications that could lead to death, personal\n\/\/ injury, or severe property or environmental damage\n\/\/ (individually and collectively, \"Critical\n\/\/ Applications\"). Customer assumes the sole risk and\n\/\/ liability of any use of Xilinx products in Critical\n\/\/ Applications, subject only to applicable laws and\n\/\/ regulations governing limitations on product liability.\n\/\/\n\/\/ THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n\/\/ PART OF THIS FILE AT ALL TIMES.\n\/\/\n\/\/ DO NOT MODIFY THIS FILE.\n\n\n\/\/ The following must be inserted into your Verilog file for this\n\/\/ core to be instantiated. Change the instance name and port connections\n\/\/ (in parentheses) to your own signal names.\n\n\/\/----------- Begin Cut here for INSTANTIATION Template ---\/\/ INST_TAG\n\nila_0 your_instance_name (\n\t.clk(clk), \/\/ input wire clk\n\n\n\t.probe0(probe0), \/\/ input wire [0:0] probe0 \n\t.probe1(probe1), \/\/ input wire [0:0] probe1 \n\t.probe2(probe2), \/\/ input wire [0:0] probe2 \n\t.probe3(probe3) \/\/ input wire [7:0] probe3\n);\n\n\/\/ INST_TAG_END ------ End INSTANTIATION Template ---------\n\n\/\/ You must compile the wrapper file ila_0 when simulating\n\/\/ the core, ila_0. When compiling the wrapper file, be sure to\n\/\/ reference the Verilog simulation library.\n\n\n","avg_line_length":40.8904109589,"max_line_length":73,"alphanum_fraction":0.7443886097} {"size":3157,"ext":"veo","lang":"Verilog","max_stars_count":null,"content":"\/\/ (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.\n\/\/ \n\/\/ This file contains confidential and proprietary information\n\/\/ of Xilinx, Inc. and is protected under U.S. and\n\/\/ international copyright and other intellectual property\n\/\/ laws.\n\/\/ \n\/\/ DISCLAIMER\n\/\/ This disclaimer is not a license and does not grant any\n\/\/ rights to the materials distributed herewith. Except as\n\/\/ otherwise provided in a valid license issued to you by\n\/\/ Xilinx, and to the maximum extent permitted by applicable\n\/\/ law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n\/\/ WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n\/\/ AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n\/\/ BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n\/\/ INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n\/\/ (2) Xilinx shall not be liable (whether in contract or tort,\n\/\/ including negligence, or under any other theory of\n\/\/ liability) for any loss or damage of any kind or nature\n\/\/ related to, arising under or in connection with these\n\/\/ materials, including for any direct, or any indirect,\n\/\/ special, incidental, or consequential loss or damage\n\/\/ (including loss of data, profits, goodwill, or any type of\n\/\/ loss or damage suffered as a result of any action brought\n\/\/ by a third party) even if such damage or loss was\n\/\/ reasonably foreseeable or Xilinx had been advised of the\n\/\/ possibility of the same.\n\/\/ \n\/\/ CRITICAL APPLICATIONS\n\/\/ Xilinx products are not designed or intended to be fail-\n\/\/ safe, or for use in any application requiring fail-safe\n\/\/ performance, such as life-support or safety devices or\n\/\/ systems, Class III medical devices, nuclear facilities,\n\/\/ applications related to the deployment of airbags, or any\n\/\/ other applications that could lead to death, personal\n\/\/ injury, or severe property or environmental damage\n\/\/ (individually and collectively, \"Critical\n\/\/ Applications\"). Customer assumes the sole risk and\n\/\/ liability of any use of Xilinx products in Critical\n\/\/ Applications, subject only to applicable laws and\n\/\/ regulations governing limitations on product liability.\n\/\/ \n\/\/ THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n\/\/ PART OF THIS FILE AT ALL TIMES.\n\/\/ \n\/\/ DO NOT MODIFY THIS FILE.\n\n\/\/ IP VLNV: xilinx.com:ip:blk_mem_gen:8.4\n\/\/ IP Revision: 0\n\n\/\/ The following must be inserted into your Verilog file for this\n\/\/ core to be instantiated. Change the instance name and port connections\n\/\/ (in parentheses) to your own signal names.\n\n\/\/----------- Begin Cut here for INSTANTIATION Template ---\/\/ INST_TAG\nblk_mem_gen_1 your_instance_name (\n .clka(clka), \/\/ input wire clka\n .wea(wea), \/\/ input wire [0 : 0] wea\n .addra(addra), \/\/ input wire [6 : 0] addra\n .dina(dina), \/\/ input wire [47 : 0] dina\n .clkb(clkb), \/\/ input wire clkb\n .addrb(addrb), \/\/ input wire [6 : 0] addrb\n .doutb(doutb) \/\/ output wire [47 : 0] doutb\n);\n\/\/ INST_TAG_END ------ End INSTANTIATION Template ---------\n\n\/\/ You must compile the wrapper file blk_mem_gen_1.v when simulating\n\/\/ the core, blk_mem_gen_1. When compiling the wrapper file, be sure to\n\/\/ reference the Verilog simulation library.\n\n","avg_line_length":43.8472222222,"max_line_length":73,"alphanum_fraction":0.7348748812} {"size":3043,"ext":"veo","lang":"Verilog","max_stars_count":1.0,"content":"\/\/ (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.\n\/\/ \n\/\/ This file contains confidential and proprietary information\n\/\/ of Xilinx, Inc. and is protected under U.S. and\n\/\/ international copyright and other intellectual property\n\/\/ laws.\n\/\/ \n\/\/ DISCLAIMER\n\/\/ This disclaimer is not a license and does not grant any\n\/\/ rights to the materials distributed herewith. Except as\n\/\/ otherwise provided in a valid license issued to you by\n\/\/ Xilinx, and to the maximum extent permitted by applicable\n\/\/ law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n\/\/ WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n\/\/ AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n\/\/ BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n\/\/ INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n\/\/ (2) Xilinx shall not be liable (whether in contract or tort,\n\/\/ including negligence, or under any other theory of\n\/\/ liability) for any loss or damage of any kind or nature\n\/\/ related to, arising under or in connection with these\n\/\/ materials, including for any direct, or any indirect,\n\/\/ special, incidental, or consequential loss or damage\n\/\/ (including loss of data, profits, goodwill, or any type of\n\/\/ loss or damage suffered as a result of any action brought\n\/\/ by a third party) even if such damage or loss was\n\/\/ reasonably foreseeable or Xilinx had been advised of the\n\/\/ possibility of the same.\n\/\/ \n\/\/ CRITICAL APPLICATIONS\n\/\/ Xilinx products are not designed or intended to be fail-\n\/\/ safe, or for use in any application requiring fail-safe\n\/\/ performance, such as life-support or safety devices or\n\/\/ systems, Class III medical devices, nuclear facilities,\n\/\/ applications related to the deployment of airbags, or any\n\/\/ other applications that could lead to death, personal\n\/\/ injury, or severe property or environmental damage\n\/\/ (individually and collectively, \"Critical\n\/\/ Applications\"). Customer assumes the sole risk and\n\/\/ liability of any use of Xilinx products in Critical\n\/\/ Applications, subject only to applicable laws and\n\/\/ regulations governing limitations on product liability.\n\/\/ \n\/\/ THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n\/\/ PART OF THIS FILE AT ALL TIMES.\n\/\/ \n\/\/ DO NOT MODIFY THIS FILE.\n\n\/\/ IP VLNV: xilinx.com:ip:c_shift_ram:12.0\n\/\/ IP Revision: 13\n\n\/\/ The following must be inserted into your Verilog file for this\n\/\/ core to be instantiated. Change the instance name and port connections\n\/\/ (in parentheses) to your own signal names.\n\n\/\/----------- Begin Cut here for INSTANTIATION Template ---\/\/ INST_TAG\nshift_ram_addr your_instance_name (\n .D(D), \/\/ input wire [18 : 0] D\n .CLK(CLK), \/\/ input wire CLK\n .CE(CE), \/\/ input wire CE\n .SCLR(SCLR), \/\/ input wire SCLR\n .Q(Q) \/\/ output wire [18 : 0] Q\n);\n\/\/ INST_TAG_END ------ End INSTANTIATION Template ---------\n\n\/\/ You must compile the wrapper file shift_ram_addr.v when simulating\n\/\/ the core, shift_ram_addr. When compiling the wrapper file, be sure to\n\/\/ reference the Verilog simulation library.\n\n","avg_line_length":43.4714285714,"max_line_length":73,"alphanum_fraction":0.7374301676} {"size":3271,"ext":"veo","lang":"Verilog","max_stars_count":null,"content":"\/\/ (c) Copyright 1995-2020 Xilinx, Inc. All rights reserved.\n\/\/ \n\/\/ This file contains confidential and proprietary information\n\/\/ of Xilinx, Inc. and is protected under U.S. and\n\/\/ international copyright and other intellectual property\n\/\/ laws.\n\/\/ \n\/\/ DISCLAIMER\n\/\/ This disclaimer is not a license and does not grant any\n\/\/ rights to the materials distributed herewith. Except as\n\/\/ otherwise provided in a valid license issued to you by\n\/\/ Xilinx, and to the maximum extent permitted by applicable\n\/\/ law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n\/\/ WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n\/\/ AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n\/\/ BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n\/\/ INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n\/\/ (2) Xilinx shall not be liable (whether in contract or tort,\n\/\/ including negligence, or under any other theory of\n\/\/ liability) for any loss or damage of any kind or nature\n\/\/ related to, arising under or in connection with these\n\/\/ materials, including for any direct, or any indirect,\n\/\/ special, incidental, or consequential loss or damage\n\/\/ (including loss of data, profits, goodwill, or any type of\n\/\/ loss or damage suffered as a result of any action brought\n\/\/ by a third party) even if such damage or loss was\n\/\/ reasonably foreseeable or Xilinx had been advised of the\n\/\/ possibility of the same.\n\/\/ \n\/\/ CRITICAL APPLICATIONS\n\/\/ Xilinx products are not designed or intended to be fail-\n\/\/ safe, or for use in any application requiring fail-safe\n\/\/ performance, such as life-support or safety devices or\n\/\/ systems, Class III medical devices, nuclear facilities,\n\/\/ applications related to the deployment of airbags, or any\n\/\/ other applications that could lead to death, personal\n\/\/ injury, or severe property or environmental damage\n\/\/ (individually and collectively, \"Critical\n\/\/ Applications\"). Customer assumes the sole risk and\n\/\/ liability of any use of Xilinx products in Critical\n\/\/ Applications, subject only to applicable laws and\n\/\/ regulations governing limitations on product liability.\n\/\/ \n\/\/ THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n\/\/ PART OF THIS FILE AT ALL TIMES.\n\/\/ \n\/\/ DO NOT MODIFY THIS FILE.\n\n\/\/ IP VLNV: xilinx.com:ip:blk_mem_gen:8.4\n\/\/ IP Revision: 2\n\n\/\/ The following must be inserted into your Verilog file for this\n\/\/ core to be instantiated. Change the instance name and port connections\n\/\/ (in parentheses) to your own signal names.\n\n\/\/----------- Begin Cut here for INSTANTIATION Template ---\/\/ INST_TAG\nRAMdp your_instance_name (\n .clka(clka), \/\/ input wire clka\n .wea(wea), \/\/ input wire [3 : 0] wea\n .addra(addra), \/\/ input wire [9 : 0] addra\n .dina(dina), \/\/ input wire [31 : 0] dina\n .douta(douta), \/\/ output wire [31 : 0] douta\n .clkb(clkb), \/\/ input wire clkb\n .web(web), \/\/ input wire [3 : 0] web\n .addrb(addrb), \/\/ input wire [9 : 0] addrb\n .dinb(dinb), \/\/ input wire [31 : 0] dinb\n .doutb(doutb) \/\/ output wire [31 : 0] doutb\n);\n\/\/ INST_TAG_END ------ End INSTANTIATION Template ---------\n\n\/\/ You must compile the wrapper file RAMdp.v when simulating\n\/\/ the core, RAMdp. When compiling the wrapper file, be sure to\n\/\/ reference the Verilog simulation library.\n\n","avg_line_length":43.6133333333,"max_line_length":73,"alphanum_fraction":0.7239376338} {"size":2967,"ext":"veo","lang":"Verilog","max_stars_count":null,"content":"\/\/ (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.\n\/\/ \n\/\/ This file contains confidential and proprietary information\n\/\/ of Xilinx, Inc. and is protected under U.S. and\n\/\/ international copyright and other intellectual property\n\/\/ laws.\n\/\/ \n\/\/ DISCLAIMER\n\/\/ This disclaimer is not a license and does not grant any\n\/\/ rights to the materials distributed herewith. Except as\n\/\/ otherwise provided in a valid license issued to you by\n\/\/ Xilinx, and to the maximum extent permitted by applicable\n\/\/ law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n\/\/ WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n\/\/ AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n\/\/ BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n\/\/ INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n\/\/ (2) Xilinx shall not be liable (whether in contract or tort,\n\/\/ including negligence, or under any other theory of\n\/\/ liability) for any loss or damage of any kind or nature\n\/\/ related to, arising under or in connection with these\n\/\/ materials, including for any direct, or any indirect,\n\/\/ special, incidental, or consequential loss or damage\n\/\/ (including loss of data, profits, goodwill, or any type of\n\/\/ loss or damage suffered as a result of any action brought\n\/\/ by a third party) even if such damage or loss was\n\/\/ reasonably foreseeable or Xilinx had been advised of the\n\/\/ possibility of the same.\n\/\/ \n\/\/ CRITICAL APPLICATIONS\n\/\/ Xilinx products are not designed or intended to be fail-\n\/\/ safe, or for use in any application requiring fail-safe\n\/\/ performance, such as life-support or safety devices or\n\/\/ systems, Class III medical devices, nuclear facilities,\n\/\/ applications related to the deployment of airbags, or any\n\/\/ other applications that could lead to death, personal\n\/\/ injury, or severe property or environmental damage\n\/\/ (individually and collectively, \"Critical\n\/\/ Applications\"). Customer assumes the sole risk and\n\/\/ liability of any use of Xilinx products in Critical\n\/\/ Applications, subject only to applicable laws and\n\/\/ regulations governing limitations on product liability.\n\/\/ \n\/\/ THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n\/\/ PART OF THIS FILE AT ALL TIMES.\n\/\/ \n\/\/ DO NOT MODIFY THIS FILE.\n\n\/\/ IP VLNV: xilinx.com:ip:c_shift_ram:12.0\n\/\/ IP Revision: 11\n\n\/\/ The following must be inserted into your Verilog file for this\n\/\/ core to be instantiated. Change the instance name and port connections\n\/\/ (in parentheses) to your own signal names.\n\n\/\/----------- Begin Cut here for INSTANTIATION Template ---\/\/ INST_TAG\nc_shift_ram_11 your_instance_name (\n .D(D), \/\/ input wire [0 : 0] D\n .CLK(CLK), \/\/ input wire CLK\n .Q(Q) \/\/ output wire [0 : 0] Q\n);\n\/\/ INST_TAG_END ------ End INSTANTIATION Template ---------\n\n\/\/ You must compile the wrapper file c_shift_ram_11.v when simulating\n\/\/ the core, c_shift_ram_11. When compiling the wrapper file, be sure to\n\/\/ reference the Verilog simulation library.\n\n","avg_line_length":43.6323529412,"max_line_length":73,"alphanum_fraction":0.7435119649} {"size":2977,"ext":"veo","lang":"Verilog","max_stars_count":null,"content":"\/\/ (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.\n\/\/ \n\/\/ This file contains confidential and proprietary information\n\/\/ of Xilinx, Inc. and is protected under U.S. and\n\/\/ international copyright and other intellectual property\n\/\/ laws.\n\/\/ \n\/\/ DISCLAIMER\n\/\/ This disclaimer is not a license and does not grant any\n\/\/ rights to the materials distributed herewith. Except as\n\/\/ otherwise provided in a valid license issued to you by\n\/\/ Xilinx, and to the maximum extent permitted by applicable\n\/\/ law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n\/\/ WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n\/\/ AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n\/\/ BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n\/\/ INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n\/\/ (2) Xilinx shall not be liable (whether in contract or tort,\n\/\/ including negligence, or under any other theory of\n\/\/ liability) for any loss or damage of any kind or nature\n\/\/ related to, arising under or in connection with these\n\/\/ materials, including for any direct, or any indirect,\n\/\/ special, incidental, or consequential loss or damage\n\/\/ (including loss of data, profits, goodwill, or any type of\n\/\/ loss or damage suffered as a result of any action brought\n\/\/ by a third party) even if such damage or loss was\n\/\/ reasonably foreseeable or Xilinx had been advised of the\n\/\/ possibility of the same.\n\/\/ \n\/\/ CRITICAL APPLICATIONS\n\/\/ Xilinx products are not designed or intended to be fail-\n\/\/ safe, or for use in any application requiring fail-safe\n\/\/ performance, such as life-support or safety devices or\n\/\/ systems, Class III medical devices, nuclear facilities,\n\/\/ applications related to the deployment of airbags, or any\n\/\/ other applications that could lead to death, personal\n\/\/ injury, or severe property or environmental damage\n\/\/ (individually and collectively, \"Critical\n\/\/ Applications\"). Customer assumes the sole risk and\n\/\/ liability of any use of Xilinx products in Critical\n\/\/ Applications, subject only to applicable laws and\n\/\/ regulations governing limitations on product liability.\n\/\/ \n\/\/ THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n\/\/ PART OF THIS FILE AT ALL TIMES.\n\/\/ \n\/\/ DO NOT MODIFY THIS FILE.\n\n\/\/ IP VLNV: xilinx.com:ip:dist_mem_gen:8.0\n\/\/ IP Revision: 12\n\n\/\/ The following must be inserted into your Verilog file for this\n\/\/ core to be instantiated. Change the instance name and port connections\n\/\/ (in parentheses) to your own signal names.\n\n\/\/----------- Begin Cut here for INSTANTIATION Template ---\/\/ INST_TAG\ndist_mem_gen_6 your_instance_name (\n .a(a), \/\/ input wire [6 : 0] a\n .clk(clk), \/\/ input wire clk\n .qspo(qspo) \/\/ output wire [11 : 0] qspo\n);\n\/\/ INST_TAG_END ------ End INSTANTIATION Template ---------\n\n\/\/ You must compile the wrapper file dist_mem_gen_6.v when simulating\n\/\/ the core, dist_mem_gen_6. When compiling the wrapper file, be sure to\n\/\/ reference the Verilog simulation library.\n\n","avg_line_length":43.7794117647,"max_line_length":73,"alphanum_fraction":0.7443735304} {"size":3309,"ext":"veo","lang":"Verilog","max_stars_count":13.0,"content":"\/\/ (c) Copyright 1995-2019 Xilinx, Inc. All rights reserved.\n\/\/ \n\/\/ This file contains confidential and proprietary information\n\/\/ of Xilinx, Inc. and is protected under U.S. and\n\/\/ international copyright and other intellectual property\n\/\/ laws.\n\/\/ \n\/\/ DISCLAIMER\n\/\/ This disclaimer is not a license and does not grant any\n\/\/ rights to the materials distributed herewith. Except as\n\/\/ otherwise provided in a valid license issued to you by\n\/\/ Xilinx, and to the maximum extent permitted by applicable\n\/\/ law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n\/\/ WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n\/\/ AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n\/\/ BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n\/\/ INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n\/\/ (2) Xilinx shall not be liable (whether in contract or tort,\n\/\/ including negligence, or under any other theory of\n\/\/ liability) for any loss or damage of any kind or nature\n\/\/ related to, arising under or in connection with these\n\/\/ materials, including for any direct, or any indirect,\n\/\/ special, incidental, or consequential loss or damage\n\/\/ (including loss of data, profits, goodwill, or any type of\n\/\/ loss or damage suffered as a result of any action brought\n\/\/ by a third party) even if such damage or loss was\n\/\/ reasonably foreseeable or Xilinx had been advised of the\n\/\/ possibility of the same.\n\/\/ \n\/\/ CRITICAL APPLICATIONS\n\/\/ Xilinx products are not designed or intended to be fail-\n\/\/ safe, or for use in any application requiring fail-safe\n\/\/ performance, such as life-support or safety devices or\n\/\/ systems, Class III medical devices, nuclear facilities,\n\/\/ applications related to the deployment of airbags, or any\n\/\/ other applications that could lead to death, personal\n\/\/ injury, or severe property or environmental damage\n\/\/ (individually and collectively, \"Critical\n\/\/ Applications\"). Customer assumes the sole risk and\n\/\/ liability of any use of Xilinx products in Critical\n\/\/ Applications, subject only to applicable laws and\n\/\/ regulations governing limitations on product liability.\n\/\/ \n\/\/ THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n\/\/ PART OF THIS FILE AT ALL TIMES.\n\/\/ \n\/\/ DO NOT MODIFY THIS FILE.\n\n\/\/ IP VLNV: xilinx.com:ip:blk_mem_gen:8.4\n\/\/ IP Revision: 4\n\n\/\/ The following must be inserted into your Verilog file for this\n\/\/ core to be instantiated. Change the instance name and port connections\n\/\/ (in parentheses) to your own signal names.\n\n\/\/----------- Begin Cut here for INSTANTIATION Template ---\/\/ INST_TAG\ntdp_ram_6144x16x2 your_instance_name (\n .clka(clka), \/\/ input wire clka\n .wea(wea), \/\/ input wire [1 : 0] wea\n .addra(addra), \/\/ input wire [12 : 0] addra\n .dina(dina), \/\/ input wire [15 : 0] dina\n .douta(douta), \/\/ output wire [15 : 0] douta\n .clkb(clkb), \/\/ input wire clkb\n .web(web), \/\/ input wire [1 : 0] web\n .addrb(addrb), \/\/ input wire [12 : 0] addrb\n .dinb(dinb), \/\/ input wire [15 : 0] dinb\n .doutb(doutb) \/\/ output wire [15 : 0] doutb\n);\n\/\/ INST_TAG_END ------ End INSTANTIATION Template ---------\n\n\/\/ You must compile the wrapper file tdp_ram_6144x16x2.v when simulating\n\/\/ the core, tdp_ram_6144x16x2. When compiling the wrapper file, be sure to\n\/\/ reference the Verilog simulation library.\n\n","avg_line_length":44.12,"max_line_length":75,"alphanum_fraction":0.7271078876} {"size":3597,"ext":"veo","lang":"Verilog","max_stars_count":null,"content":"\n\/\/ \n\/\/ (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.\n\/\/ \n\/\/ This file contains confidential and proprietary information\n\/\/ of Xilinx, Inc. and is protected under U.S. and\n\/\/ international copyright and other intellectual property\n\/\/ laws.\n\/\/ \n\/\/ DISCLAIMER\n\/\/ This disclaimer is not a license and does not grant any\n\/\/ rights to the materials distributed herewith. Except as\n\/\/ otherwise provided in a valid license issued to you by\n\/\/ Xilinx, and to the maximum extent permitted by applicable\n\/\/ law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n\/\/ WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n\/\/ AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n\/\/ BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n\/\/ INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n\/\/ (2) Xilinx shall not be liable (whether in contract or tort,\n\/\/ including negligence, or under any other theory of\n\/\/ liability) for any loss or damage of any kind or nature\n\/\/ related to, arising under or in connection with these\n\/\/ materials, including for any direct, or any indirect,\n\/\/ special, incidental, or consequential loss or damage\n\/\/ (including loss of data, profits, goodwill, or any type of\n\/\/ loss or damage suffered as a result of any action brought\n\/\/ by a third party) even if such damage or loss was\n\/\/ reasonably foreseeable or Xilinx had been advised of the\n\/\/ possibility of the same.\n\/\/ \n\/\/ CRITICAL APPLICATIONS\n\/\/ Xilinx products are not designed or intended to be fail-\n\/\/ safe, or for use in any application requiring fail-safe\n\/\/ performance, such as life-support or safety devices or\n\/\/ systems, Class III medical devices, nuclear facilities,\n\/\/ applications related to the deployment of airbags, or any\n\/\/ other applications that could lead to death, personal\n\/\/ injury, or severe property or environmental damage\n\/\/ (individually and collectively, \"Critical\n\/\/ Applications\"). Customer assumes the sole risk and\n\/\/ liability of any use of Xilinx products in Critical\n\/\/ Applications, subject only to applicable laws and\n\/\/ regulations governing limitations on product liability.\n\/\/ \n\/\/ THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n\/\/ PART OF THIS FILE AT ALL TIMES.\n\/\/ \n\/\/----------------------------------------------------------------------------\n\/\/ User entered comments\n\/\/----------------------------------------------------------------------------\n\/\/ None\n\/\/\n\/\/----------------------------------------------------------------------------\n\/\/ Output Output Phase Duty Cycle Pk-to-Pk Phase\n\/\/ Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)\n\/\/----------------------------------------------------------------------------\n\/\/ clk_out1__25.00000______0.000______50.0______181.828____104.359\n\/\/\n\/\/----------------------------------------------------------------------------\n\/\/ Input Clock Freq (MHz) Input Jitter (UI)\n\/\/----------------------------------------------------------------------------\n\/\/ __primary_________100.000____________0.010\n\n\/\/ The following must be inserted into your Verilog file for this\n\/\/ core to be instantiated. Change the instance name and port connections\n\/\/ (in parentheses) to your own signal names.\n\n\/\/----------- Begin Cut here for INSTANTIATION Template ---\/\/ INST_TAG\n\n dcm_25m instance_name\n (\n \/\/ Clock out ports\n .clk_out1(clk_out1), \/\/ output clk_out1\n \/\/ Status and control signals\n .reset(reset), \/\/ input reset\n \/\/ Clock in ports\n .clk_in1(clk_in1)); \/\/ input clk_in1\n\/\/ INST_TAG_END ------ End INSTANTIATION Template ---------\n","avg_line_length":44.9625,"max_line_length":78,"alphanum_fraction":0.6344175702} {"size":3576,"ext":"veo","lang":"Verilog","max_stars_count":null,"content":"\/\/ (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.\n\/\/ \n\/\/ This file contains confidential and proprietary information\n\/\/ of Xilinx, Inc. and is protected under U.S. and\n\/\/ international copyright and other intellectual property\n\/\/ laws.\n\/\/ \n\/\/ DISCLAIMER\n\/\/ This disclaimer is not a license and does not grant any\n\/\/ rights to the materials distributed herewith. Except as\n\/\/ otherwise provided in a valid license issued to you by\n\/\/ Xilinx, and to the maximum extent permitted by applicable\n\/\/ law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n\/\/ WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n\/\/ AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n\/\/ BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n\/\/ INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n\/\/ (2) Xilinx shall not be liable (whether in contract or tort,\n\/\/ including negligence, or under any other theory of\n\/\/ liability) for any loss or damage of any kind or nature\n\/\/ related to, arising under or in connection with these\n\/\/ materials, including for any direct, or any indirect,\n\/\/ special, incidental, or consequential loss or damage\n\/\/ (including loss of data, profits, goodwill, or any type of\n\/\/ loss or damage suffered as a result of any action brought\n\/\/ by a third party) even if such damage or loss was\n\/\/ reasonably foreseeable or Xilinx had been advised of the\n\/\/ possibility of the same.\n\/\/ \n\/\/ CRITICAL APPLICATIONS\n\/\/ Xilinx products are not designed or intended to be fail-\n\/\/ safe, or for use in any application requiring fail-safe\n\/\/ performance, such as life-support or safety devices or\n\/\/ systems, Class III medical devices, nuclear facilities,\n\/\/ applications related to the deployment of airbags, or any\n\/\/ other applications that could lead to death, personal\n\/\/ injury, or severe property or environmental damage\n\/\/ (individually and collectively, \"Critical\n\/\/ Applications\"). Customer assumes the sole risk and\n\/\/ liability of any use of Xilinx products in Critical\n\/\/ Applications, subject only to applicable laws and\n\/\/ regulations governing limitations on product liability.\n\/\/ \n\/\/ THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n\/\/ PART OF THIS FILE AT ALL TIMES.\n\/\/ \n\/\/ DO NOT MODIFY THIS FILE.\n\n\/\/ IP VLNV: xilinx.com:ip:fifo_generator:13.2\n\/\/ IP Revision: 5\n\n\/\/ The following must be inserted into your Verilog file for this\n\/\/ core to be instantiated. Change the instance name and port connections\n\/\/ (in parentheses) to your own signal names.\n\n\/\/----------- Begin Cut here for INSTANTIATION Template ---\/\/ INST_TAG\nfifo_generator_0 your_instance_name (\n .wr_rst_busy(wr_rst_busy), \/\/ output wire wr_rst_busy\n .rd_rst_busy(rd_rst_busy), \/\/ output wire rd_rst_busy\n .s_aclk(s_aclk), \/\/ input wire s_aclk\n .s_aresetn(s_aresetn), \/\/ input wire s_aresetn\n .s_axis_tvalid(s_axis_tvalid), \/\/ input wire s_axis_tvalid\n .s_axis_tready(s_axis_tready), \/\/ output wire s_axis_tready\n .s_axis_tdata(s_axis_tdata), \/\/ input wire [7 : 0] s_axis_tdata\n .m_axis_tvalid(m_axis_tvalid), \/\/ output wire m_axis_tvalid\n .m_axis_tready(m_axis_tready), \/\/ input wire m_axis_tready\n .m_axis_tdata(m_axis_tdata), \/\/ output wire [7 : 0] m_axis_tdata\n .axis_prog_full(axis_prog_full) \/\/ output wire axis_prog_full\n);\n\/\/ INST_TAG_END ------ End INSTANTIATION Template ---------\n\n\/\/ You must compile the wrapper file fifo_generator_0.v when simulating\n\/\/ the core, fifo_generator_0. When compiling the wrapper file, be sure to\n\/\/ reference the Verilog simulation library.\n\n","avg_line_length":47.0526315789,"max_line_length":74,"alphanum_fraction":0.7430089485} {"size":4611,"ext":"veo","lang":"Verilog","max_stars_count":1.0,"content":"\/*******************************************************************************\n* This file is owned and controlled by Xilinx and must be used solely *\n* for design, simulation, implementation and creation of design files *\n* limited to Xilinx devices or technologies. Use with non-Xilinx *\n* devices or technologies is expressly prohibited and immediately *\n* terminates your license. *\n* *\n* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION \"AS IS\" SOLELY *\n* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY *\n* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE *\n* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS *\n* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY *\n* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY *\n* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY *\n* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *\n* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *\n* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *\n* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *\n* PARTICULAR PURPOSE. *\n* *\n* Xilinx products are not intended for use in life support appliances, *\n* devices, or systems. Use in such applications are expressly *\n* prohibited. *\n* *\n* (c) Copyright 1995-2013 Xilinx, Inc. *\n* All rights reserved. *\n*******************************************************************************\/\n\n\/*******************************************************************************\n* Generated from core with identifier: xilinx.com:ip:fifo_generator:9.3 *\n* *\n* Rev 1. The FIFO Generator is a parameterizable first-in\/first-out *\n* memory queue generator. Use it to generate resource and performance *\n* optimized FIFOs with common or independent read\/write clock domains, *\n* and optional fixed or programmable full and empty flags and *\n* handshaking signals. Choose from a selection of memory resource *\n* types for implementation. Optional Hamming code based error *\n* detection and correction as well as error injection capability for *\n* system test help to insure data integrity. FIFO width and depth are *\n* parameterizable, and for native interface FIFOs, asymmetric read and *\n* write port widths are also supported. *\n*******************************************************************************\/\n\n\/\/ Interfaces:\n\/\/ AXI4Stream_MASTER_M_AXIS\n\/\/ AXI4Stream_SLAVE_S_AXIS\n\/\/ AXI4_MASTER_M_AXI\n\/\/ AXI4_SLAVE_S_AXI\n\/\/ AXI4Lite_MASTER_M_AXI\n\/\/ AXI4Lite_SLAVE_S_AXI\n\/\/ master_aclk\n\/\/ slave_aclk\n\/\/ slave_aresetn\n\n\/\/ The following must be inserted into your Verilog file for this\n\/\/ core to be instantiated. Change the instance name and port connections\n\/\/ (in parentheses) to your own signal names.\n\n\/\/----------- Begin Cut here for INSTANTIATION Template ---\/\/ INST_TAG\nfifo_4k_2clk your_instance_name (\n .rst(rst), \/\/ input rst\n .wr_clk(wr_clk), \/\/ input wr_clk\n .rd_clk(rd_clk), \/\/ input rd_clk\n .din(din), \/\/ input [71 : 0] din\n .wr_en(wr_en), \/\/ input wr_en\n .rd_en(rd_en), \/\/ input rd_en\n .dout(dout), \/\/ output [71 : 0] dout\n .full(full), \/\/ output full\n .empty(empty), \/\/ output empty\n .rd_data_count(rd_data_count), \/\/ output [9 : 0] rd_data_count\n .wr_data_count(wr_data_count) \/\/ output [9 : 0] wr_data_count\n);\n\/\/ INST_TAG_END ------ End INSTANTIATION Template ---------\n\n\/\/ You must compile the wrapper file fifo_4k_2clk.v when simulating\n\/\/ the core, fifo_4k_2clk. When compiling the wrapper file, be sure to\n\/\/ reference the XilinxCoreLib Verilog simulation library. For detailed\n\/\/ instructions, please refer to the \"CORE Generator Help\".\n\n","avg_line_length":57.6375,"max_line_length":80,"alphanum_fraction":0.5450010844} {"size":2961,"ext":"veo","lang":"Verilog","max_stars_count":4.0,"content":"\/*******************************************************************************\n* This file is owned and controlled by Xilinx and must be used *\n* solely for design, simulation, implementation and creation of *\n* design files limited to Xilinx devices or technologies. Use *\n* with non-Xilinx devices or technologies is expressly prohibited *\n* and immediately terminates your license. *\n* *\n* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION \"AS IS\" *\n* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR *\n* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION *\n* AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION *\n* OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS *\n* IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, *\n* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE *\n* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY *\n* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *\n* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *\n* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *\n* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS *\n* FOR A PARTICULAR PURPOSE. *\n* *\n* Xilinx products are not intended for use in life support *\n* appliances, devices, or systems. Use in such applications are *\n* expressly prohibited. *\n* *\n* (c) Copyright 1995-2009 Xilinx, Inc. *\n* All rights reserved. *\n*******************************************************************************\/\n\/\/ The following must be inserted into your Verilog file for this\n\/\/ core to be instantiated. Change the instance name and port connections\n\/\/ (in parentheses) to your own signal names.\n\n\/\/----------- Begin Cut here for INSTANTIATION Template ---\/\/ INST_TAG\ntest_core_gen2 YourInstanceName (\n\t.x_in(x_in), \/\/ Bus [7 : 0] \n\t.x_out(x_out)); \/\/ Bus [4 : 0] \n\n\/\/ INST_TAG_END ------ End INSTANTIATION Template ---------\n\n\/\/ You must compile the wrapper file test_core_gen2.v when simulating\n\/\/ the core, test_core_gen2. When compiling the wrapper file, be sure to\n\/\/ reference the XilinxCoreLib Verilog simulation library. For detailed\n\/\/ instructions, please refer to the \"CORE Generator Help\".\n\n","avg_line_length":65.8,"max_line_length":80,"alphanum_fraction":0.515704154} {"size":3006,"ext":"veo","lang":"Verilog","max_stars_count":1.0,"content":"\/\/ (c) Copyright 1995-2020 Xilinx, Inc. All rights reserved.\n\/\/ \n\/\/ This file contains confidential and proprietary information\n\/\/ of Xilinx, Inc. and is protected under U.S. and\n\/\/ international copyright and other intellectual property\n\/\/ laws.\n\/\/ \n\/\/ DISCLAIMER\n\/\/ This disclaimer is not a license and does not grant any\n\/\/ rights to the materials distributed herewith. Except as\n\/\/ otherwise provided in a valid license issued to you by\n\/\/ Xilinx, and to the maximum extent permitted by applicable\n\/\/ law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n\/\/ WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n\/\/ AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n\/\/ BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n\/\/ INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n\/\/ (2) Xilinx shall not be liable (whether in contract or tort,\n\/\/ including negligence, or under any other theory of\n\/\/ liability) for any loss or damage of any kind or nature\n\/\/ related to, arising under or in connection with these\n\/\/ materials, including for any direct, or any indirect,\n\/\/ special, incidental, or consequential loss or damage\n\/\/ (including loss of data, profits, goodwill, or any type of\n\/\/ loss or damage suffered as a result of any action brought\n\/\/ by a third party) even if such damage or loss was\n\/\/ reasonably foreseeable or Xilinx had been advised of the\n\/\/ possibility of the same.\n\/\/ \n\/\/ CRITICAL APPLICATIONS\n\/\/ Xilinx products are not designed or intended to be fail-\n\/\/ safe, or for use in any application requiring fail-safe\n\/\/ performance, such as life-support or safety devices or\n\/\/ systems, Class III medical devices, nuclear facilities,\n\/\/ applications related to the deployment of airbags, or any\n\/\/ other applications that could lead to death, personal\n\/\/ injury, or severe property or environmental damage\n\/\/ (individually and collectively, \"Critical\n\/\/ Applications\"). Customer assumes the sole risk and\n\/\/ liability of any use of Xilinx products in Critical\n\/\/ Applications, subject only to applicable laws and\n\/\/ regulations governing limitations on product liability.\n\/\/ \n\/\/ THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n\/\/ PART OF THIS FILE AT ALL TIMES.\n\/\/ \n\/\/ DO NOT MODIFY THIS FILE.\n\n\/\/ IP VLNV: xilinx.com:ip:blk_mem_gen:8.4\n\/\/ IP Revision: 4\n\n\/\/ The following must be inserted into your Verilog file for this\n\/\/ core to be instantiated. Change the instance name and port connections\n\/\/ (in parentheses) to your own signal names.\n\n\/\/----------- Begin Cut here for INSTANTIATION Template ---\/\/ INST_TAG\nimg_fail your_instance_name (\n .clka(clka), \/\/ input wire clka\n .ena(ena), \/\/ input wire ena\n .addra(addra), \/\/ input wire [15 : 0] addra\n .douta(douta) \/\/ output wire [11 : 0] douta\n);\n\/\/ INST_TAG_END ------ End INSTANTIATION Template ---------\n\n\/\/ You must compile the wrapper file img_fail.v when simulating\n\/\/ the core, img_fail. When compiling the wrapper file, be sure to\n\/\/ reference the Verilog simulation library.\n\n","avg_line_length":43.5652173913,"max_line_length":73,"alphanum_fraction":0.7428476381} {"size":3311,"ext":"veo","lang":"Verilog","max_stars_count":27.0,"content":"\/\/ (c) Copyright 1995-2019 Xilinx, Inc. All rights reserved.\n\/\/ \n\/\/ This file contains confidential and proprietary information\n\/\/ of Xilinx, Inc. and is protected under U.S. and\n\/\/ international copyright and other intellectual property\n\/\/ laws.\n\/\/ \n\/\/ DISCLAIMER\n\/\/ This disclaimer is not a license and does not grant any\n\/\/ rights to the materials distributed herewith. Except as\n\/\/ otherwise provided in a valid license issued to you by\n\/\/ Xilinx, and to the maximum extent permitted by applicable\n\/\/ law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n\/\/ WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n\/\/ AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n\/\/ BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n\/\/ INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n\/\/ (2) Xilinx shall not be liable (whether in contract or tort,\n\/\/ including negligence, or under any other theory of\n\/\/ liability) for any loss or damage of any kind or nature\n\/\/ related to, arising under or in connection with these\n\/\/ materials, including for any direct, or any indirect,\n\/\/ special, incidental, or consequential loss or damage\n\/\/ (including loss of data, profits, goodwill, or any type of\n\/\/ loss or damage suffered as a result of any action brought\n\/\/ by a third party) even if such damage or loss was\n\/\/ reasonably foreseeable or Xilinx had been advised of the\n\/\/ possibility of the same.\n\/\/ \n\/\/ CRITICAL APPLICATIONS\n\/\/ Xilinx products are not designed or intended to be fail-\n\/\/ safe, or for use in any application requiring fail-safe\n\/\/ performance, such as life-support or safety devices or\n\/\/ systems, Class III medical devices, nuclear facilities,\n\/\/ applications related to the deployment of airbags, or any\n\/\/ other applications that could lead to death, personal\n\/\/ injury, or severe property or environmental damage\n\/\/ (individually and collectively, \"Critical\n\/\/ Applications\"). Customer assumes the sole risk and\n\/\/ liability of any use of Xilinx products in Critical\n\/\/ Applications, subject only to applicable laws and\n\/\/ regulations governing limitations on product liability.\n\/\/ \n\/\/ THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n\/\/ PART OF THIS FILE AT ALL TIMES.\n\/\/ \n\/\/ DO NOT MODIFY THIS FILE.\n\n\/\/ IP VLNV: xilinx.com:ip:blk_mem_gen:8.4\n\/\/ IP Revision: 3\n\n\/\/ The following must be inserted into your Verilog file for this\n\/\/ core to be instantiated. Change the instance name and port connections\n\/\/ (in parentheses) to your own signal names.\n\n\/\/----------- Begin Cut here for INSTANTIATION Template ---\/\/ INST_TAG\nblk_mem_gen_level0 your_instance_name (\n .clka(clka), \/\/ input wire clka\n .wea(wea), \/\/ input wire [1 : 0] wea\n .addra(addra), \/\/ input wire [11 : 0] addra\n .dina(dina), \/\/ input wire [15 : 0] dina\n .douta(douta), \/\/ output wire [15 : 0] douta\n .clkb(clkb), \/\/ input wire clkb\n .web(web), \/\/ input wire [7 : 0] web\n .addrb(addrb), \/\/ input wire [9 : 0] addrb\n .dinb(dinb), \/\/ input wire [63 : 0] dinb\n .doutb(doutb) \/\/ output wire [63 : 0] doutb\n);\n\/\/ INST_TAG_END ------ End INSTANTIATION Template ---------\n\n\/\/ You must compile the wrapper file blk_mem_gen_level0.v when simulating\n\/\/ the core, blk_mem_gen_level0. When compiling the wrapper file, be sure to\n\/\/ reference the Verilog simulation library.\n\n","avg_line_length":44.1466666667,"max_line_length":76,"alphanum_fraction":0.7272727273} {"size":3439,"ext":"veo","lang":"Verilog","max_stars_count":1.0,"content":"\/\/ (c) Copyright 1995-2019 Xilinx, Inc. All rights reserved.\n\/\/ \n\/\/ This file contains confidential and proprietary information\n\/\/ of Xilinx, Inc. and is protected under U.S. and\n\/\/ international copyright and other intellectual property\n\/\/ laws.\n\/\/ \n\/\/ DISCLAIMER\n\/\/ This disclaimer is not a license and does not grant any\n\/\/ rights to the materials distributed herewith. Except as\n\/\/ otherwise provided in a valid license issued to you by\n\/\/ Xilinx, and to the maximum extent permitted by applicable\n\/\/ law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n\/\/ WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n\/\/ AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n\/\/ BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n\/\/ INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n\/\/ (2) Xilinx shall not be liable (whether in contract or tort,\n\/\/ including negligence, or under any other theory of\n\/\/ liability) for any loss or damage of any kind or nature\n\/\/ related to, arising under or in connection with these\n\/\/ materials, including for any direct, or any indirect,\n\/\/ special, incidental, or consequential loss or damage\n\/\/ (including loss of data, profits, goodwill, or any type of\n\/\/ loss or damage suffered as a result of any action brought\n\/\/ by a third party) even if such damage or loss was\n\/\/ reasonably foreseeable or Xilinx had been advised of the\n\/\/ possibility of the same.\n\/\/ \n\/\/ CRITICAL APPLICATIONS\n\/\/ Xilinx products are not designed or intended to be fail-\n\/\/ safe, or for use in any application requiring fail-safe\n\/\/ performance, such as life-support or safety devices or\n\/\/ systems, Class III medical devices, nuclear facilities,\n\/\/ applications related to the deployment of airbags, or any\n\/\/ other applications that could lead to death, personal\n\/\/ injury, or severe property or environmental damage\n\/\/ (individually and collectively, \"Critical\n\/\/ Applications\"). Customer assumes the sole risk and\n\/\/ liability of any use of Xilinx products in Critical\n\/\/ Applications, subject only to applicable laws and\n\/\/ regulations governing limitations on product liability.\n\/\/ \n\/\/ THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n\/\/ PART OF THIS FILE AT ALL TIMES.\n\/\/ \n\/\/ DO NOT MODIFY THIS FILE.\n\n\/\/ IP VLNV: xilinx.com:ip:fifo_generator:13.2\n\/\/ IP Revision: 3\n\n\/\/ The following must be inserted into your Verilog file for this\n\/\/ core to be instantiated. Change the instance name and port connections\n\/\/ (in parentheses) to your own signal names.\n\n\/\/----------- Begin Cut here for INSTANTIATION Template ---\/\/ INST_TAG\nweights_fifo your_instance_name (\n .clk(clk), \/\/ input wire clk\n .srst(srst), \/\/ input wire srst\n .din(din), \/\/ input wire [127 : 0] din\n .wr_en(wr_en), \/\/ input wire wr_en\n .rd_en(rd_en), \/\/ input wire rd_en\n .dout(dout), \/\/ output wire [255 : 0] dout\n .full(full), \/\/ output wire full\n .empty(empty), \/\/ output wire empty\n .prog_full(prog_full), \/\/ output wire prog_full\n .wr_rst_busy(wr_rst_busy), \/\/ output wire wr_rst_busy\n .rd_rst_busy(rd_rst_busy) \/\/ output wire rd_rst_busy\n);\n\/\/ INST_TAG_END ------ End INSTANTIATION Template ---------\n\n\/\/ You must compile the wrapper file weights_fifo.v when simulating\n\/\/ the core, weights_fifo. When compiling the wrapper file, be sure to\n\/\/ reference the Verilog simulation library.\n\n","avg_line_length":45.25,"max_line_length":73,"alphanum_fraction":0.7153242222} {"size":3334,"ext":"veo","lang":"Verilog","max_stars_count":4.0,"content":"\/\/ (c) Copyright 1995-2020 Xilinx, Inc. All rights reserved.\n\/\/ \n\/\/ This file contains confidential and proprietary information\n\/\/ of Xilinx, Inc. and is protected under U.S. and\n\/\/ international copyright and other intellectual property\n\/\/ laws.\n\/\/ \n\/\/ DISCLAIMER\n\/\/ This disclaimer is not a license and does not grant any\n\/\/ rights to the materials distributed herewith. Except as\n\/\/ otherwise provided in a valid license issued to you by\n\/\/ Xilinx, and to the maximum extent permitted by applicable\n\/\/ law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n\/\/ WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n\/\/ AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n\/\/ BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n\/\/ INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n\/\/ (2) Xilinx shall not be liable (whether in contract or tort,\n\/\/ including negligence, or under any other theory of\n\/\/ liability) for any loss or damage of any kind or nature\n\/\/ related to, arising under or in connection with these\n\/\/ materials, including for any direct, or any indirect,\n\/\/ special, incidental, or consequential loss or damage\n\/\/ (including loss of data, profits, goodwill, or any type of\n\/\/ loss or damage suffered as a result of any action brought\n\/\/ by a third party) even if such damage or loss was\n\/\/ reasonably foreseeable or Xilinx had been advised of the\n\/\/ possibility of the same.\n\/\/ \n\/\/ CRITICAL APPLICATIONS\n\/\/ Xilinx products are not designed or intended to be fail-\n\/\/ safe, or for use in any application requiring fail-safe\n\/\/ performance, such as life-support or safety devices or\n\/\/ systems, Class III medical devices, nuclear facilities,\n\/\/ applications related to the deployment of airbags, or any\n\/\/ other applications that could lead to death, personal\n\/\/ injury, or severe property or environmental damage\n\/\/ (individually and collectively, \"Critical\n\/\/ Applications\"). Customer assumes the sole risk and\n\/\/ liability of any use of Xilinx products in Critical\n\/\/ Applications, subject only to applicable laws and\n\/\/ regulations governing limitations on product liability.\n\/\/ \n\/\/ THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n\/\/ PART OF THIS FILE AT ALL TIMES.\n\/\/ \n\/\/ DO NOT MODIFY THIS FILE.\n\n\/\/ IP VLNV: xilinx.com:ip:fir_compiler:7.2\n\/\/ IP Revision: 13\n\n\/\/ The following must be inserted into your Verilog file for this\n\/\/ core to be instantiated. Change the instance name and port connections\n\/\/ (in parentheses) to your own signal names.\n\n\/\/----------- Begin Cut here for INSTANTIATION Template ---\/\/ INST_TAG\nhalfband_filter_1 your_instance_name (\n .aclk(aclk), \/\/ input wire aclk\n .s_axis_data_tvalid(s_axis_data_tvalid), \/\/ input wire s_axis_data_tvalid\n .s_axis_data_tready(s_axis_data_tready), \/\/ output wire s_axis_data_tready\n .s_axis_data_tdata(s_axis_data_tdata), \/\/ input wire [31 : 0] s_axis_data_tdata\n .m_axis_data_tvalid(m_axis_data_tvalid), \/\/ output wire m_axis_data_tvalid\n .m_axis_data_tdata(m_axis_data_tdata) \/\/ output wire [47 : 0] m_axis_data_tdata\n);\n\/\/ INST_TAG_END ------ End INSTANTIATION Template ---------\n\n\/\/ You must compile the wrapper file halfband_filter_1.v when simulating\n\/\/ the core, halfband_filter_1. When compiling the wrapper file, be sure to\n\/\/ reference the Verilog simulation library.\n\n","avg_line_length":46.9577464789,"max_line_length":84,"alphanum_fraction":0.7519496101} {"size":4311,"ext":"veo","lang":"Verilog","max_stars_count":1.0,"content":"\/*******************************************************************************\n* This file is owned and controlled by Xilinx and must be used solely *\n* for design, simulation, implementation and creation of design files *\n* limited to Xilinx devices or technologies. Use with non-Xilinx *\n* devices or technologies is expressly prohibited and immediately *\n* terminates your license. *\n* *\n* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION \"AS IS\" SOLELY *\n* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY *\n* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE *\n* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS *\n* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY *\n* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY *\n* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY *\n* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *\n* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *\n* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *\n* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *\n* PARTICULAR PURPOSE. *\n* *\n* Xilinx products are not intended for use in life support appliances, *\n* devices, or systems. Use in such applications are expressly *\n* prohibited. *\n* *\n* (c) Copyright 1995-2013 Xilinx, Inc. *\n* All rights reserved. *\n*******************************************************************************\/\n\n\/*******************************************************************************\n* Generated from core with identifier: xilinx.com:ip:blk_mem_gen:6.2 *\n* *\n* The Xilinx LogiCORE IP Block Memory Generator replaces the Dual Port *\n* Block Memory and Single Port Block Memory LogiCOREs, but is not a *\n* direct drop-in replacement. It should be used in all new Xilinx *\n* designs. The core supports RAM and ROM functions over a wide range of *\n* widths and depths. Use this core to generate block memories with *\n* symmetric or asymmetric read and write port widths, as well as cores *\n* which can perform simultaneous write operations to separate *\n* locations, and simultaneous read operations from the same location. *\n* For more information on differences in interface and feature support *\n* between this core and the Dual Port Block Memory and Single Port *\n* Block Memory LogiCOREs, please consult the data sheet. *\n*******************************************************************************\/\n\n\/\/ Interfaces:\n\/\/ AXI_SLAVE_S_AXI\n\/\/ AXILite_SLAVE_S_AXI\n\n\/\/ The following must be inserted into your Verilog file for this\n\/\/ core to be instantiated. Change the instance name and port connections\n\/\/ (in parentheses) to your own signal names.\n\n\/\/----------- Begin Cut here for INSTANTIATION Template ---\/\/ INST_TAG\nblinky_rom your_instance_name (\n .clka(clka), \/\/ input clka\n .addra(addra), \/\/ input [13 : 0] addra\n .douta(douta), \/\/ output [1 : 0] douta\n .clkb(clkb), \/\/ input clkb\n .addrb(addrb), \/\/ input [13 : 0] addrb\n .doutb(doutb) \/\/ output [1 : 0] doutb\n);\n\/\/ INST_TAG_END ------ End INSTANTIATION Template ---------\n\n\/\/ You must compile the wrapper file blinky_rom.v when simulating\n\/\/ the core, blinky_rom. When compiling the wrapper file, be sure to\n\/\/ reference the XilinxCoreLib Verilog simulation library. For detailed\n\/\/ instructions, please refer to the \"CORE Generator Help\".\n\n","avg_line_length":62.4782608696,"max_line_length":80,"alphanum_fraction":0.5351426583} {"size":3093,"ext":"veo","lang":"Verilog","max_stars_count":null,"content":"\/\/ (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.\n\/\/ \n\/\/ This file contains confidential and proprietary information\n\/\/ of Xilinx, Inc. and is protected under U.S. and\n\/\/ international copyright and other intellectual property\n\/\/ laws.\n\/\/ \n\/\/ DISCLAIMER\n\/\/ This disclaimer is not a license and does not grant any\n\/\/ rights to the materials distributed herewith. Except as\n\/\/ otherwise provided in a valid license issued to you by\n\/\/ Xilinx, and to the maximum extent permitted by applicable\n\/\/ law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n\/\/ WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n\/\/ AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n\/\/ BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n\/\/ INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n\/\/ (2) Xilinx shall not be liable (whether in contract or tort,\n\/\/ including negligence, or under any other theory of\n\/\/ liability) for any loss or damage of any kind or nature\n\/\/ related to, arising under or in connection with these\n\/\/ materials, including for any direct, or any indirect,\n\/\/ special, incidental, or consequential loss or damage\n\/\/ (including loss of data, profits, goodwill, or any type of\n\/\/ loss or damage suffered as a result of any action brought\n\/\/ by a third party) even if such damage or loss was\n\/\/ reasonably foreseeable or Xilinx had been advised of the\n\/\/ possibility of the same.\n\/\/ \n\/\/ CRITICAL APPLICATIONS\n\/\/ Xilinx products are not designed or intended to be fail-\n\/\/ safe, or for use in any application requiring fail-safe\n\/\/ performance, such as life-support or safety devices or\n\/\/ systems, Class III medical devices, nuclear facilities,\n\/\/ applications related to the deployment of airbags, or any\n\/\/ other applications that could lead to death, personal\n\/\/ injury, or severe property or environmental damage\n\/\/ (individually and collectively, \"Critical\n\/\/ Applications\"). Customer assumes the sole risk and\n\/\/ liability of any use of Xilinx products in Critical\n\/\/ Applications, subject only to applicable laws and\n\/\/ regulations governing limitations on product liability.\n\/\/ \n\/\/ THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n\/\/ PART OF THIS FILE AT ALL TIMES.\n\/\/ \n\/\/ DO NOT MODIFY THIS FILE.\n\n\/\/ IP VLNV: xilinx.com:ip:dist_mem_gen:8.0\n\/\/ IP Revision: 12\n\n\/\/ The following must be inserted into your Verilog file for this\n\/\/ core to be instantiated. Change the instance name and port connections\n\/\/ (in parentheses) to your own signal names.\n\n\/\/----------- Begin Cut here for INSTANTIATION Template ---\/\/ INST_TAG\ndist_mem_gen_2 your_instance_name (\n .a(a), \/\/ input wire [7 : 0] a\n .d(d), \/\/ input wire [23 : 0] d\n .dpra(dpra), \/\/ input wire [7 : 0] dpra\n .clk(clk), \/\/ input wire clk\n .we(we), \/\/ input wire we\n .dpo(dpo) \/\/ output wire [23 : 0] dpo\n);\n\/\/ INST_TAG_END ------ End INSTANTIATION Template ---------\n\n\/\/ You must compile the wrapper file dist_mem_gen_2.v when simulating\n\/\/ the core, dist_mem_gen_2. When compiling the wrapper file, be sure to\n\/\/ reference the Verilog simulation library.\n\n","avg_line_length":43.5633802817,"max_line_length":73,"alphanum_fraction":0.7326220498} {"size":2992,"ext":"veo","lang":"Verilog","max_stars_count":1.0,"content":"\/\/ (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.\n\/\/ \n\/\/ This file contains confidential and proprietary information\n\/\/ of Xilinx, Inc. and is protected under U.S. and\n\/\/ international copyright and other intellectual property\n\/\/ laws.\n\/\/ \n\/\/ DISCLAIMER\n\/\/ This disclaimer is not a license and does not grant any\n\/\/ rights to the materials distributed herewith. Except as\n\/\/ otherwise provided in a valid license issued to you by\n\/\/ Xilinx, and to the maximum extent permitted by applicable\n\/\/ law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n\/\/ WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n\/\/ AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n\/\/ BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n\/\/ INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n\/\/ (2) Xilinx shall not be liable (whether in contract or tort,\n\/\/ including negligence, or under any other theory of\n\/\/ liability) for any loss or damage of any kind or nature\n\/\/ related to, arising under or in connection with these\n\/\/ materials, including for any direct, or any indirect,\n\/\/ special, incidental, or consequential loss or damage\n\/\/ (including loss of data, profits, goodwill, or any type of\n\/\/ loss or damage suffered as a result of any action brought\n\/\/ by a third party) even if such damage or loss was\n\/\/ reasonably foreseeable or Xilinx had been advised of the\n\/\/ possibility of the same.\n\/\/ \n\/\/ CRITICAL APPLICATIONS\n\/\/ Xilinx products are not designed or intended to be fail-\n\/\/ safe, or for use in any application requiring fail-safe\n\/\/ performance, such as life-support or safety devices or\n\/\/ systems, Class III medical devices, nuclear facilities,\n\/\/ applications related to the deployment of airbags, or any\n\/\/ other applications that could lead to death, personal\n\/\/ injury, or severe property or environmental damage\n\/\/ (individually and collectively, \"Critical\n\/\/ Applications\"). Customer assumes the sole risk and\n\/\/ liability of any use of Xilinx products in Critical\n\/\/ Applications, subject only to applicable laws and\n\/\/ regulations governing limitations on product liability.\n\/\/ \n\/\/ THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n\/\/ PART OF THIS FILE AT ALL TIMES.\n\/\/ \n\/\/ DO NOT MODIFY THIS FILE.\n\n\/\/ IP VLNV: xilinx.com:ip:mult_gen:12.0\n\/\/ IP Revision: 12\n\n\/\/ The following must be inserted into your Verilog file for this\n\/\/ core to be instantiated. Change the instance name and port connections\n\/\/ (in parentheses) to your own signal names.\n\n\/\/----------- Begin Cut here for INSTANTIATION Template ---\/\/ INST_TAG\nmult_gen_0 your_instance_name (\n .CLK(CLK), \/\/ input wire CLK\n .A(A), \/\/ input wire [16 : 0] A\n .B(B), \/\/ input wire [15 : 0] B\n .P(P) \/\/ output wire [8 : 0] P\n);\n\/\/ INST_TAG_END ------ End INSTANTIATION Template ---------\n\n\/\/ You must compile the wrapper file mult_gen_0.v when simulating\n\/\/ the core, mult_gen_0. When compiling the wrapper file, be sure to\n\/\/ reference the Verilog simulation library.\n\n","avg_line_length":43.3623188406,"max_line_length":73,"alphanum_fraction":0.7376336898} {"size":3645,"ext":"veo","lang":"Verilog","max_stars_count":null,"content":"\n\/\/ \n\/\/ (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.\n\/\/ \n\/\/ This file contains confidential and proprietary information\n\/\/ of Xilinx, Inc. and is protected under U.S. and\n\/\/ international copyright and other intellectual property\n\/\/ laws.\n\/\/ \n\/\/ DISCLAIMER\n\/\/ This disclaimer is not a license and does not grant any\n\/\/ rights to the materials distributed herewith. Except as\n\/\/ otherwise provided in a valid license issued to you by\n\/\/ Xilinx, and to the maximum extent permitted by applicable\n\/\/ law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n\/\/ WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n\/\/ AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n\/\/ BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n\/\/ INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n\/\/ (2) Xilinx shall not be liable (whether in contract or tort,\n\/\/ including negligence, or under any other theory of\n\/\/ liability) for any loss or damage of any kind or nature\n\/\/ related to, arising under or in connection with these\n\/\/ materials, including for any direct, or any indirect,\n\/\/ special, incidental, or consequential loss or damage\n\/\/ (including loss of data, profits, goodwill, or any type of\n\/\/ loss or damage suffered as a result of any action brought\n\/\/ by a third party) even if such damage or loss was\n\/\/ reasonably foreseeable or Xilinx had been advised of the\n\/\/ possibility of the same.\n\/\/ \n\/\/ CRITICAL APPLICATIONS\n\/\/ Xilinx products are not designed or intended to be fail-\n\/\/ safe, or for use in any application requiring fail-safe\n\/\/ performance, such as life-support or safety devices or\n\/\/ systems, Class III medical devices, nuclear facilities,\n\/\/ applications related to the deployment of airbags, or any\n\/\/ other applications that could lead to death, personal\n\/\/ injury, or severe property or environmental damage\n\/\/ (individually and collectively, \"Critical\n\/\/ Applications\"). Customer assumes the sole risk and\n\/\/ liability of any use of Xilinx products in Critical\n\/\/ Applications, subject only to applicable laws and\n\/\/ regulations governing limitations on product liability.\n\/\/ \n\/\/ THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n\/\/ PART OF THIS FILE AT ALL TIMES.\n\/\/ \n\/\/----------------------------------------------------------------------------\n\/\/ User entered comments\n\/\/----------------------------------------------------------------------------\n\/\/ None\n\/\/\n\/\/----------------------------------------------------------------------------\n\/\/ Output Output Phase Duty Cycle Pk-to-Pk Phase\n\/\/ Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)\n\/\/----------------------------------------------------------------------------\n\/\/ clk_out1__160.00000______0.000______50.0______106.311_____87.180\n\/\/\n\/\/----------------------------------------------------------------------------\n\/\/ Input Clock Freq (MHz) Input Jitter (UI)\n\/\/----------------------------------------------------------------------------\n\/\/ __primary_________100.000____________0.010\n\n\/\/ The following must be inserted into your Verilog file for this\n\/\/ core to be instantiated. Change the instance name and port connections\n\/\/ (in parentheses) to your own signal names.\n\n\/\/----------- Begin Cut here for INSTANTIATION Template ---\/\/ INST_TAG\n\n clk_wiz_0 instance_name\n (\n \/\/ Clock out ports\n .clk_out1(clk_out1), \/\/ output clk_out1\n \/\/ Status and control signals\n .reset(reset), \/\/ input reset\n .locked(locked), \/\/ output locked\n \/\/ Clock in ports\n .clk_in1(clk_in1)); \/\/ input clk_in1\n\n\/\/ INST_TAG_END ------ End INSTANTIATION Template ---------\n","avg_line_length":44.4512195122,"max_line_length":78,"alphanum_fraction":0.6334705075} {"size":8345,"ext":"veo","lang":"Verilog","max_stars_count":312.0,"content":"\/\/ (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.\n\/\/ \n\/\/ This file contains confidential and proprietary information\n\/\/ of Xilinx, Inc. and is protected under U.S. and\n\/\/ international copyright and other intellectual property\n\/\/ laws.\n\/\/ \n\/\/ DISCLAIMER\n\/\/ This disclaimer is not a license and does not grant any\n\/\/ rights to the materials distributed herewith. Except as\n\/\/ otherwise provided in a valid license issued to you by\n\/\/ Xilinx, and to the maximum extent permitted by applicable\n\/\/ law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n\/\/ WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n\/\/ AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n\/\/ BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n\/\/ INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n\/\/ (2) Xilinx shall not be liable (whether in contract or tort,\n\/\/ including negligence, or under any other theory of\n\/\/ liability) for any loss or damage of any kind or nature\n\/\/ related to, arising under or in connection with these\n\/\/ materials, including for any direct, or any indirect,\n\/\/ special, incidental, or consequential loss or damage\n\/\/ (including loss of data, profits, goodwill, or any type of\n\/\/ loss or damage suffered as a result of any action brought\n\/\/ by a third party) even if such damage or loss was\n\/\/ reasonably foreseeable or Xilinx had been advised of the\n\/\/ possibility of the same.\n\/\/ \n\/\/ CRITICAL APPLICATIONS\n\/\/ Xilinx products are not designed or intended to be fail-\n\/\/ safe, or for use in any application requiring fail-safe\n\/\/ performance, such as life-support or safety devices or\n\/\/ systems, Class III medical devices, nuclear facilities,\n\/\/ applications related to the deployment of airbags, or any\n\/\/ other applications that could lead to death, personal\n\/\/ injury, or severe property or environmental damage\n\/\/ (individually and collectively, \"Critical\n\/\/ Applications\"). Customer assumes the sole risk and\n\/\/ liability of any use of Xilinx products in Critical\n\/\/ Applications, subject only to applicable laws and\n\/\/ regulations governing limitations on product liability.\n\/\/ \n\/\/ THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n\/\/ PART OF THIS FILE AT ALL TIMES.\n\/\/ \n\/\/ DO NOT MODIFY THIS FILE.\n\n\/\/ IP VLNV: xilinx.com:ip:axi_protocol_converter:2.1\n\/\/ IP Revision: 4\n\n\/\/ The following must be inserted into your Verilog file for this\n\/\/ core to be instantiated. Change the instance name and port connections\n\/\/ (in parentheses) to your own signal names.\n\n\/\/----------- Begin Cut here for INSTANTIATION Template ---\/\/ INST_TAG\nelink2_top_axi_protocol_converter_0_0 your_instance_name (\n .aclk(aclk), \/\/ input wire aclk\n .aresetn(aresetn), \/\/ input wire aresetn\n .s_axi_awid(s_axi_awid), \/\/ input wire [0 : 0] s_axi_awid\n .s_axi_awaddr(s_axi_awaddr), \/\/ input wire [31 : 0] s_axi_awaddr\n .s_axi_awlen(s_axi_awlen), \/\/ input wire [7 : 0] s_axi_awlen\n .s_axi_awsize(s_axi_awsize), \/\/ input wire [2 : 0] s_axi_awsize\n .s_axi_awburst(s_axi_awburst), \/\/ input wire [1 : 0] s_axi_awburst\n .s_axi_awlock(s_axi_awlock), \/\/ input wire [0 : 0] s_axi_awlock\n .s_axi_awcache(s_axi_awcache), \/\/ input wire [3 : 0] s_axi_awcache\n .s_axi_awprot(s_axi_awprot), \/\/ input wire [2 : 0] s_axi_awprot\n .s_axi_awregion(s_axi_awregion), \/\/ input wire [3 : 0] s_axi_awregion\n .s_axi_awqos(s_axi_awqos), \/\/ input wire [3 : 0] s_axi_awqos\n .s_axi_awvalid(s_axi_awvalid), \/\/ input wire s_axi_awvalid\n .s_axi_awready(s_axi_awready), \/\/ output wire s_axi_awready\n .s_axi_wdata(s_axi_wdata), \/\/ input wire [63 : 0] s_axi_wdata\n .s_axi_wstrb(s_axi_wstrb), \/\/ input wire [7 : 0] s_axi_wstrb\n .s_axi_wlast(s_axi_wlast), \/\/ input wire s_axi_wlast\n .s_axi_wvalid(s_axi_wvalid), \/\/ input wire s_axi_wvalid\n .s_axi_wready(s_axi_wready), \/\/ output wire s_axi_wready\n .s_axi_bid(s_axi_bid), \/\/ output wire [0 : 0] s_axi_bid\n .s_axi_bresp(s_axi_bresp), \/\/ output wire [1 : 0] s_axi_bresp\n .s_axi_bvalid(s_axi_bvalid), \/\/ output wire s_axi_bvalid\n .s_axi_bready(s_axi_bready), \/\/ input wire s_axi_bready\n .s_axi_arid(s_axi_arid), \/\/ input wire [0 : 0] s_axi_arid\n .s_axi_araddr(s_axi_araddr), \/\/ input wire [31 : 0] s_axi_araddr\n .s_axi_arlen(s_axi_arlen), \/\/ input wire [7 : 0] s_axi_arlen\n .s_axi_arsize(s_axi_arsize), \/\/ input wire [2 : 0] s_axi_arsize\n .s_axi_arburst(s_axi_arburst), \/\/ input wire [1 : 0] s_axi_arburst\n .s_axi_arlock(s_axi_arlock), \/\/ input wire [0 : 0] s_axi_arlock\n .s_axi_arcache(s_axi_arcache), \/\/ input wire [3 : 0] s_axi_arcache\n .s_axi_arprot(s_axi_arprot), \/\/ input wire [2 : 0] s_axi_arprot\n .s_axi_arregion(s_axi_arregion), \/\/ input wire [3 : 0] s_axi_arregion\n .s_axi_arqos(s_axi_arqos), \/\/ input wire [3 : 0] s_axi_arqos\n .s_axi_arvalid(s_axi_arvalid), \/\/ input wire s_axi_arvalid\n .s_axi_arready(s_axi_arready), \/\/ output wire s_axi_arready\n .s_axi_rid(s_axi_rid), \/\/ output wire [0 : 0] s_axi_rid\n .s_axi_rdata(s_axi_rdata), \/\/ output wire [63 : 0] s_axi_rdata\n .s_axi_rresp(s_axi_rresp), \/\/ output wire [1 : 0] s_axi_rresp\n .s_axi_rlast(s_axi_rlast), \/\/ output wire s_axi_rlast\n .s_axi_rvalid(s_axi_rvalid), \/\/ output wire s_axi_rvalid\n .s_axi_rready(s_axi_rready), \/\/ input wire s_axi_rready\n .m_axi_awid(m_axi_awid), \/\/ output wire [0 : 0] m_axi_awid\n .m_axi_awaddr(m_axi_awaddr), \/\/ output wire [31 : 0] m_axi_awaddr\n .m_axi_awlen(m_axi_awlen), \/\/ output wire [3 : 0] m_axi_awlen\n .m_axi_awsize(m_axi_awsize), \/\/ output wire [2 : 0] m_axi_awsize\n .m_axi_awburst(m_axi_awburst), \/\/ output wire [1 : 0] m_axi_awburst\n .m_axi_awlock(m_axi_awlock), \/\/ output wire [1 : 0] m_axi_awlock\n .m_axi_awcache(m_axi_awcache), \/\/ output wire [3 : 0] m_axi_awcache\n .m_axi_awprot(m_axi_awprot), \/\/ output wire [2 : 0] m_axi_awprot\n .m_axi_awqos(m_axi_awqos), \/\/ output wire [3 : 0] m_axi_awqos\n .m_axi_awvalid(m_axi_awvalid), \/\/ output wire m_axi_awvalid\n .m_axi_awready(m_axi_awready), \/\/ input wire m_axi_awready\n .m_axi_wid(m_axi_wid), \/\/ output wire [0 : 0] m_axi_wid\n .m_axi_wdata(m_axi_wdata), \/\/ output wire [63 : 0] m_axi_wdata\n .m_axi_wstrb(m_axi_wstrb), \/\/ output wire [7 : 0] m_axi_wstrb\n .m_axi_wlast(m_axi_wlast), \/\/ output wire m_axi_wlast\n .m_axi_wvalid(m_axi_wvalid), \/\/ output wire m_axi_wvalid\n .m_axi_wready(m_axi_wready), \/\/ input wire m_axi_wready\n .m_axi_bid(m_axi_bid), \/\/ input wire [0 : 0] m_axi_bid\n .m_axi_bresp(m_axi_bresp), \/\/ input wire [1 : 0] m_axi_bresp\n .m_axi_bvalid(m_axi_bvalid), \/\/ input wire m_axi_bvalid\n .m_axi_bready(m_axi_bready), \/\/ output wire m_axi_bready\n .m_axi_arid(m_axi_arid), \/\/ output wire [0 : 0] m_axi_arid\n .m_axi_araddr(m_axi_araddr), \/\/ output wire [31 : 0] m_axi_araddr\n .m_axi_arlen(m_axi_arlen), \/\/ output wire [3 : 0] m_axi_arlen\n .m_axi_arsize(m_axi_arsize), \/\/ output wire [2 : 0] m_axi_arsize\n .m_axi_arburst(m_axi_arburst), \/\/ output wire [1 : 0] m_axi_arburst\n .m_axi_arlock(m_axi_arlock), \/\/ output wire [1 : 0] m_axi_arlock\n .m_axi_arcache(m_axi_arcache), \/\/ output wire [3 : 0] m_axi_arcache\n .m_axi_arprot(m_axi_arprot), \/\/ output wire [2 : 0] m_axi_arprot\n .m_axi_arqos(m_axi_arqos), \/\/ output wire [3 : 0] m_axi_arqos\n .m_axi_arvalid(m_axi_arvalid), \/\/ output wire m_axi_arvalid\n .m_axi_arready(m_axi_arready), \/\/ input wire m_axi_arready\n .m_axi_rid(m_axi_rid), \/\/ input wire [0 : 0] m_axi_rid\n .m_axi_rdata(m_axi_rdata), \/\/ input wire [63 : 0] m_axi_rdata\n .m_axi_rresp(m_axi_rresp), \/\/ input wire [1 : 0] m_axi_rresp\n .m_axi_rlast(m_axi_rlast), \/\/ input wire m_axi_rlast\n .m_axi_rvalid(m_axi_rvalid), \/\/ input wire m_axi_rvalid\n .m_axi_rready(m_axi_rready) \/\/ output wire m_axi_rready\n);\n\/\/ INST_TAG_END ------ End INSTANTIATION Template ---------\n\n\/\/ You must compile the wrapper file elink2_top_axi_protocol_converter_0_0.v when simulating\n\/\/ the core, elink2_top_axi_protocol_converter_0_0. When compiling the wrapper file, be sure to\n\/\/ reference the Verilog simulation library.\n\n","avg_line_length":57.9513888889,"max_line_length":95,"alphanum_fraction":0.6986219293} {"size":4291,"ext":"veo","lang":"Verilog","max_stars_count":null,"content":"\/*******************************************************************************\r\n* This file is owned and controlled by Xilinx and must be used solely *\r\n* for design, simulation, implementation and creation of design files *\r\n* limited to Xilinx devices or technologies. Use with non-Xilinx *\r\n* devices or technologies is expressly prohibited and immediately *\r\n* terminates your license. *\r\n* *\r\n* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION \"AS IS\" SOLELY *\r\n* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY *\r\n* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE *\r\n* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS *\r\n* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY *\r\n* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY *\r\n* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY *\r\n* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *\r\n* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *\r\n* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *\r\n* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *\r\n* PARTICULAR PURPOSE. *\r\n* *\r\n* Xilinx products are not intended for use in life support appliances, *\r\n* devices, or systems. Use in such applications are expressly *\r\n* prohibited. *\r\n* *\r\n* (c) Copyright 1995-2019 Xilinx, Inc. *\r\n* All rights reserved. *\r\n*******************************************************************************\/\r\n\r\n\/*******************************************************************************\r\n* Generated from core with identifier: xilinx.com:ip:blk_mem_gen:7.3 *\r\n* *\r\n* The Xilinx LogiCORE IP Block Memory Generator replaces the Dual Port *\r\n* Block Memory and Single Port Block Memory LogiCOREs, but is not a *\r\n* direct drop-in replacement. It should be used in all new Xilinx *\r\n* designs. The core supports RAM and ROM functions over a wide range of *\r\n* widths and depths. Use this core to generate block memories with *\r\n* symmetric or asymmetric read and write port widths, as well as cores *\r\n* which can perform simultaneous write operations to separate *\r\n* locations, and simultaneous read operations from the same location. *\r\n* For more information on differences in interface and feature support *\r\n* between this core and the Dual Port Block Memory and Single Port *\r\n* Block Memory LogiCOREs, please consult the data sheet. *\r\n*******************************************************************************\/\r\n\r\n\/\/ The following must be inserted into your Verilog file for this\r\n\/\/ core to be instantiated. Change the instance name and port connections\r\n\/\/ (in parentheses) to your own signal names.\r\n\r\n\/\/----------- Begin Cut here for INSTANTIATION Template ---\/\/ INST_TAG\r\nim_m_ram your_instance_name (\r\n .clka(clka), \/\/ input clka\r\n .ena(ena), \/\/ input ena\r\n .wea(wea), \/\/ input [0 : 0] wea\r\n .addra(addra), \/\/ input [13 : 0] addra\r\n .dina(dina), \/\/ input [7 : 0] dina\r\n .douta(douta) \/\/ output [7 : 0] douta\r\n);\r\n\/\/ INST_TAG_END ------ End INSTANTIATION Template ---------\r\n\r\n\/\/ You must compile the wrapper file im_m_ram.v when simulating\r\n\/\/ the core, im_m_ram. When compiling the wrapper file, be sure to\r\n\/\/ reference the XilinxCoreLib Verilog simulation library. For detailed\r\n\/\/ instructions, please refer to the \"CORE Generator Help\".\r\n\r\n","avg_line_length":66.0153846154,"max_line_length":81,"alphanum_fraction":0.5227219762} {"size":4674,"ext":"veo","lang":"Verilog","max_stars_count":8.0,"content":"\/*******************************************************************************\n* This file is owned and controlled by Xilinx and must be used solely *\n* for design, simulation, implementation and creation of design files *\n* limited to Xilinx devices or technologies. Use with non-Xilinx *\n* devices or technologies is expressly prohibited and immediately *\n* terminates your license. *\n* *\n* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION \"AS IS\" SOLELY *\n* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY *\n* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE *\n* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS *\n* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY *\n* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY *\n* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY *\n* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *\n* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *\n* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *\n* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *\n* PARTICULAR PURPOSE. *\n* *\n* Xilinx products are not intended for use in life support appliances, *\n* devices, or systems. Use in such applications are expressly *\n* prohibited. *\n* *\n* (c) Copyright 1995-2019 Xilinx, Inc. *\n* All rights reserved. *\n*******************************************************************************\/\n\n\/*******************************************************************************\n* Generated from core with identifier: xilinx.com:ip:fifo_generator:9.3 *\n* *\n* Rev 1. The FIFO Generator is a parameterizable first-in\/first-out *\n* memory queue generator. Use it to generate resource and performance *\n* optimized FIFOs with common or independent read\/write clock domains, *\n* and optional fixed or programmable full and empty flags and *\n* handshaking signals. Choose from a selection of memory resource *\n* types for implementation. Optional Hamming code based error *\n* detection and correction as well as error injection capability for *\n* system test help to insure data integrity. FIFO width and depth are *\n* parameterizable, and for native interface FIFOs, asymmetric read and *\n* write port widths are also supported. *\n*******************************************************************************\/\n\n\/\/ Interfaces:\n\/\/ AXI4Stream_MASTER_M_AXIS\n\/\/ AXI4Stream_SLAVE_S_AXIS\n\/\/ AXI4_MASTER_M_AXI\n\/\/ AXI4_SLAVE_S_AXI\n\/\/ AXI4Lite_MASTER_M_AXI\n\/\/ AXI4Lite_SLAVE_S_AXI\n\/\/ master_aclk\n\/\/ slave_aclk\n\/\/ slave_aresetn\n\n\/\/ The following must be inserted into your Verilog file for this\n\/\/ core to be instantiated. Change the instance name and port connections\n\/\/ (in parentheses) to your own signal names.\n\n\/\/----------- Begin Cut here for INSTANTIATION Template ---\/\/ INST_TAG\nfifo_w32_1024_r32_1024 your_instance_name (\n .rst(rst), \/\/ input rst\n .wr_clk(wr_clk), \/\/ input wr_clk\n .rd_clk(rd_clk), \/\/ input rd_clk\n .din(din), \/\/ input [31 : 0] din\n .wr_en(wr_en), \/\/ input wr_en\n .rd_en(rd_en), \/\/ input rd_en\n .dout(dout), \/\/ output [31 : 0] dout\n .full(full), \/\/ output full\n .empty(empty), \/\/ output empty\n .valid(valid), \/\/ output valid\n .rd_data_count(rd_data_count), \/\/ output [9 : 0] rd_data_count\n .wr_data_count(wr_data_count) \/\/ output [9 : 0] wr_data_count\n);\n\/\/ INST_TAG_END ------ End INSTANTIATION Template ---------\n\n\/\/ You must compile the wrapper file fifo_w32_1024_r32_1024.v when simulating\n\/\/ the core, fifo_w32_1024_r32_1024. When compiling the wrapper file, be sure to\n\/\/ reference the XilinxCoreLib Verilog simulation library. For detailed\n\/\/ instructions, please refer to the \"CORE Generator Help\".\n\n","avg_line_length":57.7037037037,"max_line_length":80,"alphanum_fraction":0.5485665383} {"size":4275,"ext":"veo","lang":"Verilog","max_stars_count":null,"content":"\/\/ (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.\n\/\/ \n\/\/ This file contains confidential and proprietary information\n\/\/ of Xilinx, Inc. and is protected under U.S. and\n\/\/ international copyright and other intellectual property\n\/\/ laws.\n\/\/ \n\/\/ DISCLAIMER\n\/\/ This disclaimer is not a license and does not grant any\n\/\/ rights to the materials distributed herewith. Except as\n\/\/ otherwise provided in a valid license issued to you by\n\/\/ Xilinx, and to the maximum extent permitted by applicable\n\/\/ law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n\/\/ WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n\/\/ AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n\/\/ BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n\/\/ INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n\/\/ (2) Xilinx shall not be liable (whether in contract or tort,\n\/\/ including negligence, or under any other theory of\n\/\/ liability) for any loss or damage of any kind or nature\n\/\/ related to, arising under or in connection with these\n\/\/ materials, including for any direct, or any indirect,\n\/\/ special, incidental, or consequential loss or damage\n\/\/ (including loss of data, profits, goodwill, or any type of\n\/\/ loss or damage suffered as a result of any action brought\n\/\/ by a third party) even if such damage or loss was\n\/\/ reasonably foreseeable or Xilinx had been advised of the\n\/\/ possibility of the same.\n\/\/ \n\/\/ CRITICAL APPLICATIONS\n\/\/ Xilinx products are not designed or intended to be fail-\n\/\/ safe, or for use in any application requiring fail-safe\n\/\/ performance, such as life-support or safety devices or\n\/\/ systems, Class III medical devices, nuclear facilities,\n\/\/ applications related to the deployment of airbags, or any\n\/\/ other applications that could lead to death, personal\n\/\/ injury, or severe property or environmental damage\n\/\/ (individually and collectively, \"Critical\n\/\/ Applications\"). Customer assumes the sole risk and\n\/\/ liability of any use of Xilinx products in Critical\n\/\/ Applications, subject only to applicable laws and\n\/\/ regulations governing limitations on product liability.\n\/\/ \n\/\/ THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n\/\/ PART OF THIS FILE AT ALL TIMES.\n\/\/ \n\/\/ DO NOT MODIFY THIS FILE.\n\n\/\/ IP VLNV: xilinx.com:ip:axi_uartlite:2.0\n\/\/ IP Revision: 4\n\n\/\/ The following must be inserted into your Verilog file for this\n\/\/ core to be instantiated. Change the instance name and port connections\n\/\/ (in parentheses) to your own signal names.\n\n\/\/----------- Begin Cut here for INSTANTIATION Template ---\/\/ INST_TAG\ndesign_1_axi_uartlite_0_0 your_instance_name (\n .s_axi_aclk(s_axi_aclk), \/\/ input wire s_axi_aclk\n .s_axi_aresetn(s_axi_aresetn), \/\/ input wire s_axi_aresetn\n .interrupt(interrupt), \/\/ output wire interrupt\n .s_axi_awaddr(s_axi_awaddr), \/\/ input wire [3 : 0] s_axi_awaddr\n .s_axi_awvalid(s_axi_awvalid), \/\/ input wire s_axi_awvalid\n .s_axi_awready(s_axi_awready), \/\/ output wire s_axi_awready\n .s_axi_wdata(s_axi_wdata), \/\/ input wire [31 : 0] s_axi_wdata\n .s_axi_wstrb(s_axi_wstrb), \/\/ input wire [3 : 0] s_axi_wstrb\n .s_axi_wvalid(s_axi_wvalid), \/\/ input wire s_axi_wvalid\n .s_axi_wready(s_axi_wready), \/\/ output wire s_axi_wready\n .s_axi_bresp(s_axi_bresp), \/\/ output wire [1 : 0] s_axi_bresp\n .s_axi_bvalid(s_axi_bvalid), \/\/ output wire s_axi_bvalid\n .s_axi_bready(s_axi_bready), \/\/ input wire s_axi_bready\n .s_axi_araddr(s_axi_araddr), \/\/ input wire [3 : 0] s_axi_araddr\n .s_axi_arvalid(s_axi_arvalid), \/\/ input wire s_axi_arvalid\n .s_axi_arready(s_axi_arready), \/\/ output wire s_axi_arready\n .s_axi_rdata(s_axi_rdata), \/\/ output wire [31 : 0] s_axi_rdata\n .s_axi_rresp(s_axi_rresp), \/\/ output wire [1 : 0] s_axi_rresp\n .s_axi_rvalid(s_axi_rvalid), \/\/ output wire s_axi_rvalid\n .s_axi_rready(s_axi_rready), \/\/ input wire s_axi_rready\n .rx(rx), \/\/ input wire rx\n .tx(tx) \/\/ output wire tx\n);\n\/\/ INST_TAG_END ------ End INSTANTIATION Template ---------\n\n\/\/ You must compile the wrapper file design_1_axi_uartlite_0_0.v when simulating\n\/\/ the core, design_1_axi_uartlite_0_0. When compiling the wrapper file, be sure to\n\/\/ reference the Verilog simulation library.\n\n","avg_line_length":49.1379310345,"max_line_length":83,"alphanum_fraction":0.7326315789} {"size":3012,"ext":"veo","lang":"Verilog","max_stars_count":1.0,"content":"\/\/ (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.\n\/\/ \n\/\/ This file contains confidential and proprietary information\n\/\/ of Xilinx, Inc. and is protected under U.S. and\n\/\/ international copyright and other intellectual property\n\/\/ laws.\n\/\/ \n\/\/ DISCLAIMER\n\/\/ This disclaimer is not a license and does not grant any\n\/\/ rights to the materials distributed herewith. Except as\n\/\/ otherwise provided in a valid license issued to you by\n\/\/ Xilinx, and to the maximum extent permitted by applicable\n\/\/ law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n\/\/ WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n\/\/ AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n\/\/ BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n\/\/ INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n\/\/ (2) Xilinx shall not be liable (whether in contract or tort,\n\/\/ including negligence, or under any other theory of\n\/\/ liability) for any loss or damage of any kind or nature\n\/\/ related to, arising under or in connection with these\n\/\/ materials, including for any direct, or any indirect,\n\/\/ special, incidental, or consequential loss or damage\n\/\/ (including loss of data, profits, goodwill, or any type of\n\/\/ loss or damage suffered as a result of any action brought\n\/\/ by a third party) even if such damage or loss was\n\/\/ reasonably foreseeable or Xilinx had been advised of the\n\/\/ possibility of the same.\n\/\/ \n\/\/ CRITICAL APPLICATIONS\n\/\/ Xilinx products are not designed or intended to be fail-\n\/\/ safe, or for use in any application requiring fail-safe\n\/\/ performance, such as life-support or safety devices or\n\/\/ systems, Class III medical devices, nuclear facilities,\n\/\/ applications related to the deployment of airbags, or any\n\/\/ other applications that could lead to death, personal\n\/\/ injury, or severe property or environmental damage\n\/\/ (individually and collectively, \"Critical\n\/\/ Applications\"). Customer assumes the sole risk and\n\/\/ liability of any use of Xilinx products in Critical\n\/\/ Applications, subject only to applicable laws and\n\/\/ regulations governing limitations on product liability.\n\/\/ \n\/\/ THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n\/\/ PART OF THIS FILE AT ALL TIMES.\n\/\/ \n\/\/ DO NOT MODIFY THIS FILE.\n\n\/\/ IP VLNV: xilinx.com:ip:mult_gen:12.0\n\/\/ IP Revision: 12\n\n\/\/ The following must be inserted into your Verilog file for this\n\/\/ core to be instantiated. Change the instance name and port connections\n\/\/ (in parentheses) to your own signal names.\n\n\/\/----------- Begin Cut here for INSTANTIATION Template ---\/\/ INST_TAG\nmultiply_u8xu8_l3 your_instance_name (\n .CLK(CLK), \/\/ input wire CLK\n .A(A), \/\/ input wire [7 : 0] A\n .B(B), \/\/ input wire [7 : 0] B\n .P(P) \/\/ output wire [15 : 0] P\n);\n\/\/ INST_TAG_END ------ End INSTANTIATION Template ---------\n\n\/\/ You must compile the wrapper file multiply_u8xu8_l3.v when simulating\n\/\/ the core, multiply_u8xu8_l3. When compiling the wrapper file, be sure to\n\/\/ reference the Verilog simulation library.\n\n","avg_line_length":43.652173913,"max_line_length":75,"alphanum_fraction":0.73937583} {"size":2975,"ext":"veo","lang":"Verilog","max_stars_count":1.0,"content":"\/\/ (c) Copyright 1995-2020 Xilinx, Inc. All rights reserved.\n\/\/ \n\/\/ This file contains confidential and proprietary information\n\/\/ of Xilinx, Inc. and is protected under U.S. and\n\/\/ international copyright and other intellectual property\n\/\/ laws.\n\/\/ \n\/\/ DISCLAIMER\n\/\/ This disclaimer is not a license and does not grant any\n\/\/ rights to the materials distributed herewith. Except as\n\/\/ otherwise provided in a valid license issued to you by\n\/\/ Xilinx, and to the maximum extent permitted by applicable\n\/\/ law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n\/\/ WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n\/\/ AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n\/\/ BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n\/\/ INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n\/\/ (2) Xilinx shall not be liable (whether in contract or tort,\n\/\/ including negligence, or under any other theory of\n\/\/ liability) for any loss or damage of any kind or nature\n\/\/ related to, arising under or in connection with these\n\/\/ materials, including for any direct, or any indirect,\n\/\/ special, incidental, or consequential loss or damage\n\/\/ (including loss of data, profits, goodwill, or any type of\n\/\/ loss or damage suffered as a result of any action brought\n\/\/ by a third party) even if such damage or loss was\n\/\/ reasonably foreseeable or Xilinx had been advised of the\n\/\/ possibility of the same.\n\/\/ \n\/\/ CRITICAL APPLICATIONS\n\/\/ Xilinx products are not designed or intended to be fail-\n\/\/ safe, or for use in any application requiring fail-safe\n\/\/ performance, such as life-support or safety devices or\n\/\/ systems, Class III medical devices, nuclear facilities,\n\/\/ applications related to the deployment of airbags, or any\n\/\/ other applications that could lead to death, personal\n\/\/ injury, or severe property or environmental damage\n\/\/ (individually and collectively, \"Critical\n\/\/ Applications\"). Customer assumes the sole risk and\n\/\/ liability of any use of Xilinx products in Critical\n\/\/ Applications, subject only to applicable laws and\n\/\/ regulations governing limitations on product liability.\n\/\/ \n\/\/ THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n\/\/ PART OF THIS FILE AT ALL TIMES.\n\/\/ \n\/\/ DO NOT MODIFY THIS FILE.\n\n\/\/ IP VLNV: xilinx.com:ip:c_counter_binary:12.0\n\/\/ IP Revision: 13\n\n\/\/ The following must be inserted into your Verilog file for this\n\/\/ core to be instantiated. Change the instance name and port connections\n\/\/ (in parentheses) to your own signal names.\n\n\/\/----------- Begin Cut here for INSTANTIATION Template ---\/\/ INST_TAG\nsddrtt_timer your_instance_name (\n .CLK(CLK), \/\/ input wire CLK\n .SINIT(SINIT), \/\/ input wire SINIT\n .Q(Q) \/\/ output wire [31 : 0] Q\n);\n\/\/ INST_TAG_END ------ End INSTANTIATION Template ---------\n\n\/\/ You must compile the wrapper file sddrtt_timer.v when simulating\n\/\/ the core, sddrtt_timer. When compiling the wrapper file, be sure to\n\/\/ reference the Verilog simulation library.\n\n","avg_line_length":43.75,"max_line_length":73,"alphanum_fraction":0.7448739496} {"size":3044,"ext":"veo","lang":"Verilog","max_stars_count":38.0,"content":"\/*******************************************************************************\n* This file is owned and controlled by Xilinx and must be used *\n* solely for design, simulation, implementation and creation of *\n* design files limited to Xilinx devices or technologies. Use *\n* with non-Xilinx devices or technologies is expressly prohibited *\n* and immediately terminates your license. *\n* *\n* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION \"AS IS\" *\n* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR *\n* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION *\n* AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION *\n* OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS *\n* IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, *\n* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE *\n* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY *\n* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *\n* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *\n* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *\n* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS *\n* FOR A PARTICULAR PURPOSE. *\n* *\n* Xilinx products are not intended for use in life support *\n* appliances, devices, or systems. Use in such applications are *\n* expressly prohibited. *\n* *\n* (c) Copyright 1995-2009 Xilinx, Inc. *\n* All rights reserved. *\n*******************************************************************************\/\n\/\/ The following must be inserted into your Verilog file for this\n\/\/ core to be instantiated. Change the instance name and port connections\n\/\/ (in parentheses) to your own signal names.\n\n\/\/----------- Begin Cut here for INSTANTIATION Template ---\/\/ INST_TAG\nvirtex5_pmem YourInstanceName (\n\t.clka(clka),\n\t.ena(ena),\n\t.wea(wea), \/\/ Bus [1 : 0] \n\t.addra(addra), \/\/ Bus [11 : 0] \n\t.dina(dina), \/\/ Bus [15 : 0] \n\t.douta(douta)); \/\/ Bus [15 : 0] \n\n\/\/ INST_TAG_END ------ End INSTANTIATION Template ---------\n\n\/\/ You must compile the wrapper file virtex5_pmem.v when simulating\n\/\/ the core, virtex5_pmem. When compiling the wrapper file, be sure to\n\/\/ reference the XilinxCoreLib Verilog simulation library. For detailed\n\/\/ instructions, please refer to the \"CORE Generator Help\".\n\n","avg_line_length":62.1224489796,"max_line_length":80,"alphanum_fraction":0.5137976347} {"size":3376,"ext":"veo","lang":"Verilog","max_stars_count":1.0,"content":"\/\/ (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.\r\n\/\/ \r\n\/\/ This file contains confidential and proprietary information\r\n\/\/ of Xilinx, Inc. and is protected under U.S. and\r\n\/\/ international copyright and other intellectual property\r\n\/\/ laws.\r\n\/\/ \r\n\/\/ DISCLAIMER\r\n\/\/ This disclaimer is not a license and does not grant any\r\n\/\/ rights to the materials distributed herewith. Except as\r\n\/\/ otherwise provided in a valid license issued to you by\r\n\/\/ Xilinx, and to the maximum extent permitted by applicable\r\n\/\/ law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\r\n\/\/ WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\r\n\/\/ AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\r\n\/\/ BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\r\n\/\/ INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\r\n\/\/ (2) Xilinx shall not be liable (whether in contract or tort,\r\n\/\/ including negligence, or under any other theory of\r\n\/\/ liability) for any loss or damage of any kind or nature\r\n\/\/ related to, arising under or in connection with these\r\n\/\/ materials, including for any direct, or any indirect,\r\n\/\/ special, incidental, or consequential loss or damage\r\n\/\/ (including loss of data, profits, goodwill, or any type of\r\n\/\/ loss or damage suffered as a result of any action brought\r\n\/\/ by a third party) even if such damage or loss was\r\n\/\/ reasonably foreseeable or Xilinx had been advised of the\r\n\/\/ possibility of the same.\r\n\/\/ \r\n\/\/ CRITICAL APPLICATIONS\r\n\/\/ Xilinx products are not designed or intended to be fail-\r\n\/\/ safe, or for use in any application requiring fail-safe\r\n\/\/ performance, such as life-support or safety devices or\r\n\/\/ systems, Class III medical devices, nuclear facilities,\r\n\/\/ applications related to the deployment of airbags, or any\r\n\/\/ other applications that could lead to death, personal\r\n\/\/ injury, or severe property or environmental damage\r\n\/\/ (individually and collectively, \"Critical\r\n\/\/ Applications\"). Customer assumes the sole risk and\r\n\/\/ liability of any use of Xilinx products in Critical\r\n\/\/ Applications, subject only to applicable laws and\r\n\/\/ regulations governing limitations on product liability.\r\n\/\/ \r\n\/\/ THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\r\n\/\/ PART OF THIS FILE AT ALL TIMES.\r\n\/\/ \r\n\/\/ DO NOT MODIFY THIS FILE.\r\n\r\n\/\/ IP VLNV: xilinx.com:ip:fifo_generator:13.0\r\n\/\/ IP Revision: 1\r\n\r\n\/\/ The following must be inserted into your Verilog file for this\r\n\/\/ core to be instantiated. Change the instance name and port connections\r\n\/\/ (in parentheses) to your own signal names.\r\n\r\n\/\/----------- Begin Cut here for INSTANTIATION Template ---\/\/ INST_TAG\r\nfifo_generator_command your_instance_name (\r\n .rst(rst), \/\/ input wire rst\r\n .wr_clk(wr_clk), \/\/ input wire wr_clk\r\n .rd_clk(rd_clk), \/\/ input wire rd_clk\r\n .din(din), \/\/ input wire [23 : 0] din\r\n .wr_en(wr_en), \/\/ input wire wr_en\r\n .rd_en(rd_en), \/\/ input wire rd_en\r\n .dout(dout), \/\/ output wire [23 : 0] dout\r\n .full(full), \/\/ output wire full\r\n .empty(empty), \/\/ output wire empty\r\n .valid(valid) \/\/ output wire valid\r\n);\r\n\/\/ INST_TAG_END ------ End INSTANTIATION Template ---------\r\n\r\n\/\/ You must compile the wrapper file fifo_generator_command.v when simulating\r\n\/\/ the core, fifo_generator_command. When compiling the wrapper file, be sure to\r\n\/\/ reference the Verilog simulation library.\r\n\r\n","avg_line_length":45.0133333333,"max_line_length":81,"alphanum_fraction":0.7177132701} {"size":4475,"ext":"veo","lang":"Verilog","max_stars_count":56.0,"content":"\/*******************************************************************************\n* This file is owned and controlled by Xilinx and must be used solely *\n* for design, simulation, implementation and creation of design files *\n* limited to Xilinx devices or technologies. Use with non-Xilinx *\n* devices or technologies is expressly prohibited and immediately *\n* terminates your license. *\n* *\n* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION \"AS IS\" SOLELY *\n* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY *\n* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE *\n* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS *\n* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY *\n* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY *\n* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY *\n* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *\n* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *\n* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *\n* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *\n* PARTICULAR PURPOSE. *\n* *\n* Xilinx products are not intended for use in life support appliances, *\n* devices, or systems. Use in such applications are expressly *\n* prohibited. *\n* *\n* (c) Copyright 1995-2015 Xilinx, Inc. *\n* All rights reserved. *\n*******************************************************************************\/\n\n\/*******************************************************************************\n* Generated from core with identifier: xilinx.com:ip:fifo_generator:9.3 *\n* *\n* Rev 1. The FIFO Generator is a parameterizable first-in\/first-out *\n* memory queue generator. Use it to generate resource and performance *\n* optimized FIFOs with common or independent read\/write clock domains, *\n* and optional fixed or programmable full and empty flags and *\n* handshaking signals. Choose from a selection of memory resource *\n* types for implementation. Optional Hamming code based error *\n* detection and correction as well as error injection capability for *\n* system test help to insure data integrity. FIFO width and depth are *\n* parameterizable, and for native interface FIFOs, asymmetric read and *\n* write port widths are also supported. *\n*******************************************************************************\/\n\n\/\/ Interfaces:\n\/\/ AXI4Stream_MASTER_M_AXIS\n\/\/ AXI4Stream_SLAVE_S_AXIS\n\/\/ AXI4_MASTER_M_AXI\n\/\/ AXI4_SLAVE_S_AXI\n\/\/ AXI4Lite_MASTER_M_AXI\n\/\/ AXI4Lite_SLAVE_S_AXI\n\/\/ master_aclk\n\/\/ slave_aclk\n\/\/ slave_aresetn\n\n\/\/ The following must be inserted into your Verilog file for this\n\/\/ core to be instantiated. Change the instance name and port connections\n\/\/ (in parentheses) to your own signal names.\n\n\/\/----------- Begin Cut here for INSTANTIATION Template ---\/\/ INST_TAG\ncfifo32x16 your_instance_name (\n .rst(rst), \/\/ input rst\n .wr_clk(wr_clk), \/\/ input wr_clk\n .rd_clk(rd_clk), \/\/ input rd_clk\n .din(din), \/\/ input [31 : 0] din\n .wr_en(wr_en), \/\/ input wr_en\n .rd_en(rd_en), \/\/ input rd_en\n .dout(dout), \/\/ output [31 : 0] dout\n .full(full), \/\/ output full\n .empty(empty) \/\/ output empty\n);\n\/\/ INST_TAG_END ------ End INSTANTIATION Template ---------\n\n\/\/ You must compile the wrapper file cfifo32x16.v when simulating\n\/\/ the core, cfifo32x16. When compiling the wrapper file, be sure to\n\/\/ reference the XilinxCoreLib Verilog simulation library. For detailed\n\/\/ instructions, please refer to the \"CORE Generator Help\".\n\n","avg_line_length":57.3717948718,"max_line_length":80,"alphanum_fraction":0.5392178771} {"size":3685,"ext":"veo","lang":"Verilog","max_stars_count":null,"content":"\/\/ (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.\n\/\/ \n\/\/ This file contains confidential and proprietary information\n\/\/ of Xilinx, Inc. and is protected under U.S. and\n\/\/ international copyright and other intellectual property\n\/\/ laws.\n\/\/ \n\/\/ DISCLAIMER\n\/\/ This disclaimer is not a license and does not grant any\n\/\/ rights to the materials distributed herewith. Except as\n\/\/ otherwise provided in a valid license issued to you by\n\/\/ Xilinx, and to the maximum extent permitted by applicable\n\/\/ law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n\/\/ WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n\/\/ AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n\/\/ BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n\/\/ INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n\/\/ (2) Xilinx shall not be liable (whether in contract or tort,\n\/\/ including negligence, or under any other theory of\n\/\/ liability) for any loss or damage of any kind or nature\n\/\/ related to, arising under or in connection with these\n\/\/ materials, including for any direct, or any indirect,\n\/\/ special, incidental, or consequential loss or damage\n\/\/ (including loss of data, profits, goodwill, or any type of\n\/\/ loss or damage suffered as a result of any action brought\n\/\/ by a third party) even if such damage or loss was\n\/\/ reasonably foreseeable or Xilinx had been advised of the\n\/\/ possibility of the same.\n\/\/ \n\/\/ CRITICAL APPLICATIONS\n\/\/ Xilinx products are not designed or intended to be fail-\n\/\/ safe, or for use in any application requiring fail-safe\n\/\/ performance, such as life-support or safety devices or\n\/\/ systems, Class III medical devices, nuclear facilities,\n\/\/ applications related to the deployment of airbags, or any\n\/\/ other applications that could lead to death, personal\n\/\/ injury, or severe property or environmental damage\n\/\/ (individually and collectively, \"Critical\n\/\/ Applications\"). Customer assumes the sole risk and\n\/\/ liability of any use of Xilinx products in Critical\n\/\/ Applications, subject only to applicable laws and\n\/\/ regulations governing limitations on product liability.\n\/\/ \n\/\/ THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n\/\/ PART OF THIS FILE AT ALL TIMES.\n\/\/ \n\/\/ DO NOT MODIFY THIS FILE.\n\n\/\/ IP VLNV: xilinx.com:ip:proc_sys_reset:5.0\n\/\/ IP Revision: 7\n\n\/\/ The following must be inserted into your Verilog file for this\n\/\/ core to be instantiated. Change the instance name and port connections\n\/\/ (in parentheses) to your own signal names.\n\n\/\/----------- Begin Cut here for INSTANTIATION Template ---\/\/ INST_TAG\nsystem_sys_rstgen_0 your_instance_name (\n .slowest_sync_clk(slowest_sync_clk), \/\/ input wire slowest_sync_clk\n .ext_reset_in(ext_reset_in), \/\/ input wire ext_reset_in\n .aux_reset_in(aux_reset_in), \/\/ input wire aux_reset_in\n .mb_debug_sys_rst(mb_debug_sys_rst), \/\/ input wire mb_debug_sys_rst\n .dcm_locked(dcm_locked), \/\/ input wire dcm_locked\n .mb_reset(mb_reset), \/\/ output wire mb_reset\n .bus_struct_reset(bus_struct_reset), \/\/ output wire [0 : 0] bus_struct_reset\n .peripheral_reset(peripheral_reset), \/\/ output wire [0 : 0] peripheral_reset\n .interconnect_aresetn(interconnect_aresetn), \/\/ output wire [0 : 0] interconnect_aresetn\n .peripheral_aresetn(peripheral_aresetn) \/\/ output wire [0 : 0] peripheral_aresetn\n);\n\/\/ INST_TAG_END ------ End INSTANTIATION Template ---------\n\n\/\/ You must compile the wrapper file system_sys_rstgen_0.v when simulating\n\/\/ the core, system_sys_rstgen_0. When compiling the wrapper file, be sure to\n\/\/ reference the Verilog simulation library.\n\n","avg_line_length":49.1333333333,"max_line_length":91,"alphanum_fraction":0.7354138399} {"size":4523,"ext":"veo","lang":"Verilog","max_stars_count":null,"content":"\/\/ (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.\n\/\/ \n\/\/ This file contains confidential and proprietary information\n\/\/ of Xilinx, Inc. and is protected under U.S. and\n\/\/ international copyright and other intellectual property\n\/\/ laws.\n\/\/ \n\/\/ DISCLAIMER\n\/\/ This disclaimer is not a license and does not grant any\n\/\/ rights to the materials distributed herewith. Except as\n\/\/ otherwise provided in a valid license issued to you by\n\/\/ Xilinx, and to the maximum extent permitted by applicable\n\/\/ law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n\/\/ WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n\/\/ AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n\/\/ BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n\/\/ INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n\/\/ (2) Xilinx shall not be liable (whether in contract or tort,\n\/\/ including negligence, or under any other theory of\n\/\/ liability) for any loss or damage of any kind or nature\n\/\/ related to, arising under or in connection with these\n\/\/ materials, including for any direct, or any indirect,\n\/\/ special, incidental, or consequential loss or damage\n\/\/ (including loss of data, profits, goodwill, or any type of\n\/\/ loss or damage suffered as a result of any action brought\n\/\/ by a third party) even if such damage or loss was\n\/\/ reasonably foreseeable or Xilinx had been advised of the\n\/\/ possibility of the same.\n\/\/ \n\/\/ CRITICAL APPLICATIONS\n\/\/ Xilinx products are not designed or intended to be fail-\n\/\/ safe, or for use in any application requiring fail-safe\n\/\/ performance, such as life-support or safety devices or\n\/\/ systems, Class III medical devices, nuclear facilities,\n\/\/ applications related to the deployment of airbags, or any\n\/\/ other applications that could lead to death, personal\n\/\/ injury, or severe property or environmental damage\n\/\/ (individually and collectively, \"Critical\n\/\/ Applications\"). Customer assumes the sole risk and\n\/\/ liability of any use of Xilinx products in Critical\n\/\/ Applications, subject only to applicable laws and\n\/\/ regulations governing limitations on product liability.\n\/\/ \n\/\/ THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n\/\/ PART OF THIS FILE AT ALL TIMES.\n\/\/ \n\/\/ DO NOT MODIFY THIS FILE.\n\n\/\/ IP VLNV: xilinx.com:ip:lmb_v10:3.0\n\/\/ IP Revision: 3\n\n\/\/ The following must be inserted into your Verilog file for this\n\/\/ core to be instantiated. Change the instance name and port connections\n\/\/ (in parentheses) to your own signal names.\n\n\/\/----------- Begin Cut here for INSTANTIATION Template ---\/\/ INST_TAG\ndesign_1_ilmb_v10_0 your_instance_name (\n .LMB_Clk(LMB_Clk), \/\/ input wire LMB_Clk\n .SYS_Rst(SYS_Rst), \/\/ input wire SYS_Rst\n .LMB_Rst(LMB_Rst), \/\/ output wire LMB_Rst\n .M_ABus(M_ABus), \/\/ input wire [0 : 31] M_ABus\n .M_ReadStrobe(M_ReadStrobe), \/\/ input wire M_ReadStrobe\n .M_WriteStrobe(M_WriteStrobe), \/\/ input wire M_WriteStrobe\n .M_AddrStrobe(M_AddrStrobe), \/\/ input wire M_AddrStrobe\n .M_DBus(M_DBus), \/\/ input wire [0 : 31] M_DBus\n .M_BE(M_BE), \/\/ input wire [0 : 3] M_BE\n .Sl_DBus(Sl_DBus), \/\/ input wire [0 : 31] Sl_DBus\n .Sl_Ready(Sl_Ready), \/\/ input wire [0 : 0] Sl_Ready\n .Sl_Wait(Sl_Wait), \/\/ input wire [0 : 0] Sl_Wait\n .Sl_UE(Sl_UE), \/\/ input wire [0 : 0] Sl_UE\n .Sl_CE(Sl_CE), \/\/ input wire [0 : 0] Sl_CE\n .LMB_ABus(LMB_ABus), \/\/ output wire [0 : 31] LMB_ABus\n .LMB_ReadStrobe(LMB_ReadStrobe), \/\/ output wire LMB_ReadStrobe\n .LMB_WriteStrobe(LMB_WriteStrobe), \/\/ output wire LMB_WriteStrobe\n .LMB_AddrStrobe(LMB_AddrStrobe), \/\/ output wire LMB_AddrStrobe\n .LMB_ReadDBus(LMB_ReadDBus), \/\/ output wire [0 : 31] LMB_ReadDBus\n .LMB_WriteDBus(LMB_WriteDBus), \/\/ output wire [0 : 31] LMB_WriteDBus\n .LMB_Ready(LMB_Ready), \/\/ output wire LMB_Ready\n .LMB_Wait(LMB_Wait), \/\/ output wire LMB_Wait\n .LMB_UE(LMB_UE), \/\/ output wire LMB_UE\n .LMB_CE(LMB_CE), \/\/ output wire LMB_CE\n .LMB_BE(LMB_BE) \/\/ output wire [0 : 3] LMB_BE\n);\n\/\/ INST_TAG_END ------ End INSTANTIATION Template ---------\n\n\/\/ You must compile the wrapper file design_1_ilmb_v10_0.v when simulating\n\/\/ the core, design_1_ilmb_v10_0. When compiling the wrapper file, be sure to\n\/\/ reference the Verilog simulation library.\n\n","avg_line_length":50.2555555556,"max_line_length":77,"alphanum_fraction":0.6822905151} {"size":3177,"ext":"veo","lang":"Verilog","max_stars_count":9.0,"content":"\/\/ (c) Copyright 1995-2018 Xilinx, Inc. All rights reserved.\n\/\/ \n\/\/ This file contains confidential and proprietary information\n\/\/ of Xilinx, Inc. and is protected under U.S. and\n\/\/ international copyright and other intellectual property\n\/\/ laws.\n\/\/ \n\/\/ DISCLAIMER\n\/\/ This disclaimer is not a license and does not grant any\n\/\/ rights to the materials distributed herewith. Except as\n\/\/ otherwise provided in a valid license issued to you by\n\/\/ Xilinx, and to the maximum extent permitted by applicable\n\/\/ law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n\/\/ WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n\/\/ AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n\/\/ BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n\/\/ INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n\/\/ (2) Xilinx shall not be liable (whether in contract or tort,\n\/\/ including negligence, or under any other theory of\n\/\/ liability) for any loss or damage of any kind or nature\n\/\/ related to, arising under or in connection with these\n\/\/ materials, including for any direct, or any indirect,\n\/\/ special, incidental, or consequential loss or damage\n\/\/ (including loss of data, profits, goodwill, or any type of\n\/\/ loss or damage suffered as a result of any action brought\n\/\/ by a third party) even if such damage or loss was\n\/\/ reasonably foreseeable or Xilinx had been advised of the\n\/\/ possibility of the same.\n\/\/ \n\/\/ CRITICAL APPLICATIONS\n\/\/ Xilinx products are not designed or intended to be fail-\n\/\/ safe, or for use in any application requiring fail-safe\n\/\/ performance, such as life-support or safety devices or\n\/\/ systems, Class III medical devices, nuclear facilities,\n\/\/ applications related to the deployment of airbags, or any\n\/\/ other applications that could lead to death, personal\n\/\/ injury, or severe property or environmental damage\n\/\/ (individually and collectively, \"Critical\n\/\/ Applications\"). Customer assumes the sole risk and\n\/\/ liability of any use of Xilinx products in Critical\n\/\/ Applications, subject only to applicable laws and\n\/\/ regulations governing limitations on product liability.\n\/\/ \n\/\/ THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n\/\/ PART OF THIS FILE AT ALL TIMES.\n\/\/ \n\/\/ DO NOT MODIFY THIS FILE.\n\n\/\/ IP VLNV: xilinx.com:ip:blk_mem_gen:8.4\n\/\/ IP Revision: 1\n\n\/\/ The following must be inserted into your Verilog file for this\n\/\/ core to be instantiated. Change the instance name and port connections\n\/\/ (in parentheses) to your own signal names.\n\n\/\/----------- Begin Cut here for INSTANTIATION Template ---\/\/ INST_TAG\nipcore_bram_16k_16b your_instance_name (\n .clka(clka), \/\/ input wire clka\n .wea(wea), \/\/ input wire [0 : 0] wea\n .addra(addra), \/\/ input wire [13 : 0] addra\n .dina(dina), \/\/ input wire [15 : 0] dina\n .clkb(clkb), \/\/ input wire clkb\n .addrb(addrb), \/\/ input wire [13 : 0] addrb\n .doutb(doutb) \/\/ output wire [15 : 0] doutb\n);\n\/\/ INST_TAG_END ------ End INSTANTIATION Template ---------\n\n\/\/ You must compile the wrapper file ipcore_bram_16k_16b.v when simulating\n\/\/ the core, ipcore_bram_16k_16b. When compiling the wrapper file, be sure to\n\/\/ reference the Verilog simulation library.\n\n","avg_line_length":44.125,"max_line_length":77,"alphanum_fraction":0.7365439093} {"size":3675,"ext":"veo","lang":"Verilog","max_stars_count":null,"content":"\/\/ (c) Copyright 1995-2020 Xilinx, Inc. All rights reserved.\n\/\/ \n\/\/ This file contains confidential and proprietary information\n\/\/ of Xilinx, Inc. and is protected under U.S. and\n\/\/ international copyright and other intellectual property\n\/\/ laws.\n\/\/ \n\/\/ DISCLAIMER\n\/\/ This disclaimer is not a license and does not grant any\n\/\/ rights to the materials distributed herewith. Except as\n\/\/ otherwise provided in a valid license issued to you by\n\/\/ Xilinx, and to the maximum extent permitted by applicable\n\/\/ law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n\/\/ WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n\/\/ AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n\/\/ BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n\/\/ INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n\/\/ (2) Xilinx shall not be liable (whether in contract or tort,\n\/\/ including negligence, or under any other theory of\n\/\/ liability) for any loss or damage of any kind or nature\n\/\/ related to, arising under or in connection with these\n\/\/ materials, including for any direct, or any indirect,\n\/\/ special, incidental, or consequential loss or damage\n\/\/ (including loss of data, profits, goodwill, or any type of\n\/\/ loss or damage suffered as a result of any action brought\n\/\/ by a third party) even if such damage or loss was\n\/\/ reasonably foreseeable or Xilinx had been advised of the\n\/\/ possibility of the same.\n\/\/ \n\/\/ CRITICAL APPLICATIONS\n\/\/ Xilinx products are not designed or intended to be fail-\n\/\/ safe, or for use in any application requiring fail-safe\n\/\/ performance, such as life-support or safety devices or\n\/\/ systems, Class III medical devices, nuclear facilities,\n\/\/ applications related to the deployment of airbags, or any\n\/\/ other applications that could lead to death, personal\n\/\/ injury, or severe property or environmental damage\n\/\/ (individually and collectively, \"Critical\n\/\/ Applications\"). Customer assumes the sole risk and\n\/\/ liability of any use of Xilinx products in Critical\n\/\/ Applications, subject only to applicable laws and\n\/\/ regulations governing limitations on product liability.\n\/\/ \n\/\/ THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n\/\/ PART OF THIS FILE AT ALL TIMES.\n\/\/ \n\/\/ DO NOT MODIFY THIS FILE.\n\n\/\/ IP VLNV: xilinx.com:user:Driver_IIC:1.0\n\/\/ IP Revision: 2\n\n\/\/ The following must be inserted into your Verilog file for this\n\/\/ core to be instantiated. Change the instance name and port connections\n\/\/ (in parentheses) to your own signal names.\n\n\/\/----------- Begin Cut here for INSTANTIATION Template ---\/\/ INST_TAG\nDriver_IIC_0 your_instance_name (\n .clk(clk), \/\/ input wire clk\n .Rst(Rst), \/\/ input wire Rst\n .Addr(Addr), \/\/ input wire [7 : 0] Addr\n .Reg_Addr(Reg_Addr), \/\/ input wire [15 : 0] Reg_Addr\n .Data(Data), \/\/ input wire [7 : 0] Data\n .IIC_Write(IIC_Write), \/\/ input wire IIC_Write\n .IIC_Read(IIC_Read), \/\/ input wire IIC_Read\n .IIC_Read_Data(IIC_Read_Data), \/\/ output wire [7 : 0] IIC_Read_Data\n .IIC_Busy(IIC_Busy), \/\/ output wire IIC_Busy\n .Reg_2Addr(Reg_2Addr), \/\/ input wire Reg_2Addr\n .IIC_SCL(IIC_SCL), \/\/ output wire IIC_SCL\n .IIC_SDA_In(IIC_SDA_In), \/\/ input wire IIC_SDA_In\n .SDA_Dir(SDA_Dir), \/\/ output wire SDA_Dir\n .SDA_Out(SDA_Out) \/\/ output wire SDA_Out\n);\n\/\/ INST_TAG_END ------ End INSTANTIATION Template ---------\n\n\/\/ You must compile the wrapper file Driver_IIC_0.v when simulating\n\/\/ the core, Driver_IIC_0. When compiling the wrapper file, be sure to\n\/\/ reference the Verilog simulation library.\n\n","avg_line_length":46.5189873418,"max_line_length":73,"alphanum_fraction":0.7053061224} {"size":4164,"ext":"veo","lang":"Verilog","max_stars_count":16.0,"content":"\/\/ (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.\n\/\/ \n\/\/ This file contains confidential and proprietary information\n\/\/ of Xilinx, Inc. and is protected under U.S. and\n\/\/ international copyright and other intellectual property\n\/\/ laws.\n\/\/ \n\/\/ DISCLAIMER\n\/\/ This disclaimer is not a license and does not grant any\n\/\/ rights to the materials distributed herewith. Except as\n\/\/ otherwise provided in a valid license issued to you by\n\/\/ Xilinx, and to the maximum extent permitted by applicable\n\/\/ law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n\/\/ WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n\/\/ AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n\/\/ BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n\/\/ INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n\/\/ (2) Xilinx shall not be liable (whether in contract or tort,\n\/\/ including negligence, or under any other theory of\n\/\/ liability) for any loss or damage of any kind or nature\n\/\/ related to, arising under or in connection with these\n\/\/ materials, including for any direct, or any indirect,\n\/\/ special, incidental, or consequential loss or damage\n\/\/ (including loss of data, profits, goodwill, or any type of\n\/\/ loss or damage suffered as a result of any action brought\n\/\/ by a third party) even if such damage or loss was\n\/\/ reasonably foreseeable or Xilinx had been advised of the\n\/\/ possibility of the same.\n\/\/ \n\/\/ CRITICAL APPLICATIONS\n\/\/ Xilinx products are not designed or intended to be fail-\n\/\/ safe, or for use in any application requiring fail-safe\n\/\/ performance, such as life-support or safety devices or\n\/\/ systems, Class III medical devices, nuclear facilities,\n\/\/ applications related to the deployment of airbags, or any\n\/\/ other applications that could lead to death, personal\n\/\/ injury, or severe property or environmental damage\n\/\/ (individually and collectively, \"Critical\n\/\/ Applications\"). Customer assumes the sole risk and\n\/\/ liability of any use of Xilinx products in Critical\n\/\/ Applications, subject only to applicable laws and\n\/\/ regulations governing limitations on product liability.\n\/\/ \n\/\/ THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n\/\/ PART OF THIS FILE AT ALL TIMES.\n\/\/ \n\/\/ DO NOT MODIFY THIS FILE.\n\n\/\/ IP VLNV: xilinx.com:ip:axi_gpio:2.0\n\/\/ IP Revision: 9\n\n\/\/ The following must be inserted into your Verilog file for this\n\/\/ core to be instantiated. Change the instance name and port connections\n\/\/ (in parentheses) to your own signal names.\n\n\/\/----------- Begin Cut here for INSTANTIATION Template ---\/\/ INST_TAG\nPmodAMP2_axi_gpio_0_0 your_instance_name (\n .s_axi_aclk(s_axi_aclk), \/\/ input wire s_axi_aclk\n .s_axi_aresetn(s_axi_aresetn), \/\/ input wire s_axi_aresetn\n .s_axi_awaddr(s_axi_awaddr), \/\/ input wire [8 : 0] s_axi_awaddr\n .s_axi_awvalid(s_axi_awvalid), \/\/ input wire s_axi_awvalid\n .s_axi_awready(s_axi_awready), \/\/ output wire s_axi_awready\n .s_axi_wdata(s_axi_wdata), \/\/ input wire [31 : 0] s_axi_wdata\n .s_axi_wstrb(s_axi_wstrb), \/\/ input wire [3 : 0] s_axi_wstrb\n .s_axi_wvalid(s_axi_wvalid), \/\/ input wire s_axi_wvalid\n .s_axi_wready(s_axi_wready), \/\/ output wire s_axi_wready\n .s_axi_bresp(s_axi_bresp), \/\/ output wire [1 : 0] s_axi_bresp\n .s_axi_bvalid(s_axi_bvalid), \/\/ output wire s_axi_bvalid\n .s_axi_bready(s_axi_bready), \/\/ input wire s_axi_bready\n .s_axi_araddr(s_axi_araddr), \/\/ input wire [8 : 0] s_axi_araddr\n .s_axi_arvalid(s_axi_arvalid), \/\/ input wire s_axi_arvalid\n .s_axi_arready(s_axi_arready), \/\/ output wire s_axi_arready\n .s_axi_rdata(s_axi_rdata), \/\/ output wire [31 : 0] s_axi_rdata\n .s_axi_rresp(s_axi_rresp), \/\/ output wire [1 : 0] s_axi_rresp\n .s_axi_rvalid(s_axi_rvalid), \/\/ output wire s_axi_rvalid\n .s_axi_rready(s_axi_rready), \/\/ input wire s_axi_rready\n .gpio_io_o(gpio_io_o) \/\/ output wire [2 : 0] gpio_io_o\n);\n\/\/ INST_TAG_END ------ End INSTANTIATION Template ---------\n\n\/\/ You must compile the wrapper file PmodAMP2_axi_gpio_0_0.v when simulating\n\/\/ the core, PmodAMP2_axi_gpio_0_0. When compiling the wrapper file, be sure to\n\/\/ reference the Verilog simulation library.\n\n","avg_line_length":48.9882352941,"max_line_length":79,"alphanum_fraction":0.7413544669} {"size":4397,"ext":"veo","lang":"Verilog","max_stars_count":1.0,"content":"\/*******************************************************************************\n* This file is owned and controlled by Xilinx and must be used solely *\n* for design, simulation, implementation and creation of design files *\n* limited to Xilinx devices or technologies. Use with non-Xilinx *\n* devices or technologies is expressly prohibited and immediately *\n* terminates your license. *\n* *\n* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION \"AS IS\" SOLELY *\n* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY *\n* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE *\n* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS *\n* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY *\n* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY *\n* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY *\n* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *\n* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *\n* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *\n* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *\n* PARTICULAR PURPOSE. *\n* *\n* Xilinx products are not intended for use in life support appliances, *\n* devices, or systems. Use in such applications are expressly *\n* prohibited. *\n* *\n* (c) Copyright 1995-2012 Xilinx, Inc. *\n* All rights reserved. *\n*******************************************************************************\/\n\n\/*******************************************************************************\n* Generated from core with identifier: xilinx.com:ip:fifo_generator:8.4 *\n* *\n* The FIFO Generator is a parameterizable first-in\/first-out memory *\n* queue generator. Use it to generate resource and performance *\n* optimized FIFOs with common or independent read\/write clock domains, *\n* and optional fixed or programmable full and empty flags and *\n* handshaking signals. Choose from a selection of memory resource *\n* types for implementation. Optional Hamming code based error *\n* detection and correction as well as error injection capability for *\n* system test help to insure data integrity. FIFO width and depth are *\n* parameterizable, and for native interface FIFOs, asymmetric read and *\n* write port widths are also supported. *\n*******************************************************************************\/\n\n\/\/ Interfaces:\n\/\/ AXI4Stream_MASTER_M_AXIS\n\/\/ AXI4Stream_SLAVE_S_AXIS\n\/\/ AXI4_MASTER_M_AXI\n\/\/ AXI4_SLAVE_S_AXI\n\/\/ AXI4Lite_MASTER_M_AXI\n\/\/ AXI4Lite_SLAVE_S_AXI\n\n\/\/ The following must be inserted into your Verilog file for this\n\/\/ core to be instantiated. Change the instance name and port connections\n\/\/ (in parentheses) to your own signal names.\n\n\/\/----------- Begin Cut here for INSTANTIATION Template ---\/\/ INST_TAG\nfifo_fwft_96x512 your_instance_name (\n .clk(clk), \/\/ input clk\n .srst(srst), \/\/ input srst\n .din(din), \/\/ input [95 : 0] din\n .wr_en(wr_en), \/\/ input wr_en\n .rd_en(rd_en), \/\/ input rd_en\n .dout(dout), \/\/ output [95 : 0] dout\n .full(full), \/\/ output full\n .empty(empty) \/\/ output empty\n);\n\/\/ INST_TAG_END ------ End INSTANTIATION Template ---------\n\n\/\/ You must compile the wrapper file fifo_fwft_96x512.v when simulating\n\/\/ the core, fifo_fwft_96x512. When compiling the wrapper file, be sure to\n\/\/ reference the XilinxCoreLib Verilog simulation library. For detailed\n\/\/ instructions, please refer to the \"CORE Generator Help\".\n\n","avg_line_length":59.4189189189,"max_line_length":80,"alphanum_fraction":0.5376392995} {"size":4683,"ext":"veo","lang":"Verilog","max_stars_count":2.0,"content":"\/\/ (c) Copyright 1995-2018 Xilinx, Inc. All rights reserved.\n\/\/ \n\/\/ This file contains confidential and proprietary information\n\/\/ of Xilinx, Inc. and is protected under U.S. and\n\/\/ international copyright and other intellectual property\n\/\/ laws.\n\/\/ \n\/\/ DISCLAIMER\n\/\/ This disclaimer is not a license and does not grant any\n\/\/ rights to the materials distributed herewith. Except as\n\/\/ otherwise provided in a valid license issued to you by\n\/\/ Xilinx, and to the maximum extent permitted by applicable\n\/\/ law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n\/\/ WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n\/\/ AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n\/\/ BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n\/\/ INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n\/\/ (2) Xilinx shall not be liable (whether in contract or tort,\n\/\/ including negligence, or under any other theory of\n\/\/ liability) for any loss or damage of any kind or nature\n\/\/ related to, arising under or in connection with these\n\/\/ materials, including for any direct, or any indirect,\n\/\/ special, incidental, or consequential loss or damage\n\/\/ (including loss of data, profits, goodwill, or any type of\n\/\/ loss or damage suffered as a result of any action brought\n\/\/ by a third party) even if such damage or loss was\n\/\/ reasonably foreseeable or Xilinx had been advised of the\n\/\/ possibility of the same.\n\/\/ \n\/\/ CRITICAL APPLICATIONS\n\/\/ Xilinx products are not designed or intended to be fail-\n\/\/ safe, or for use in any application requiring fail-safe\n\/\/ performance, such as life-support or safety devices or\n\/\/ systems, Class III medical devices, nuclear facilities,\n\/\/ applications related to the deployment of airbags, or any\n\/\/ other applications that could lead to death, personal\n\/\/ injury, or severe property or environmental damage\n\/\/ (individually and collectively, \"Critical\n\/\/ Applications\"). Customer assumes the sole risk and\n\/\/ liability of any use of Xilinx products in Critical\n\/\/ Applications, subject only to applicable laws and\n\/\/ regulations governing limitations on product liability.\n\/\/ \n\/\/ THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n\/\/ PART OF THIS FILE AT ALL TIMES.\n\/\/ \n\/\/ DO NOT MODIFY THIS FILE.\n\n\/\/ IP VLNV: xilinx.com:ip:mdm:3.2\n\/\/ IP Revision: 4\n\n\/\/ The following must be inserted into your Verilog file for this\n\/\/ core to be instantiated. Change the instance name and port connections\n\/\/ (in parentheses) to your own signal names.\n\n\/\/----------- Begin Cut here for INSTANTIATION Template ---\/\/ INST_TAG\nPWSBD_mdm_1_0 your_instance_name (\n .S_AXI_ACLK(S_AXI_ACLK), \/\/ input wire S_AXI_ACLK\n .S_AXI_ARESETN(S_AXI_ARESETN), \/\/ input wire S_AXI_ARESETN\n .Interrupt(Interrupt), \/\/ output wire Interrupt\n .Debug_SYS_Rst(Debug_SYS_Rst), \/\/ output wire Debug_SYS_Rst\n .S_AXI_AWADDR(S_AXI_AWADDR), \/\/ input wire [31 : 0] S_AXI_AWADDR\n .S_AXI_AWVALID(S_AXI_AWVALID), \/\/ input wire S_AXI_AWVALID\n .S_AXI_AWREADY(S_AXI_AWREADY), \/\/ output wire S_AXI_AWREADY\n .S_AXI_WDATA(S_AXI_WDATA), \/\/ input wire [31 : 0] S_AXI_WDATA\n .S_AXI_WSTRB(S_AXI_WSTRB), \/\/ input wire [3 : 0] S_AXI_WSTRB\n .S_AXI_WVALID(S_AXI_WVALID), \/\/ input wire S_AXI_WVALID\n .S_AXI_WREADY(S_AXI_WREADY), \/\/ output wire S_AXI_WREADY\n .S_AXI_BRESP(S_AXI_BRESP), \/\/ output wire [1 : 0] S_AXI_BRESP\n .S_AXI_BVALID(S_AXI_BVALID), \/\/ output wire S_AXI_BVALID\n .S_AXI_BREADY(S_AXI_BREADY), \/\/ input wire S_AXI_BREADY\n .S_AXI_ARADDR(S_AXI_ARADDR), \/\/ input wire [31 : 0] S_AXI_ARADDR\n .S_AXI_ARVALID(S_AXI_ARVALID), \/\/ input wire S_AXI_ARVALID\n .S_AXI_ARREADY(S_AXI_ARREADY), \/\/ output wire S_AXI_ARREADY\n .S_AXI_RDATA(S_AXI_RDATA), \/\/ output wire [31 : 0] S_AXI_RDATA\n .S_AXI_RRESP(S_AXI_RRESP), \/\/ output wire [1 : 0] S_AXI_RRESP\n .S_AXI_RVALID(S_AXI_RVALID), \/\/ output wire S_AXI_RVALID\n .S_AXI_RREADY(S_AXI_RREADY), \/\/ input wire S_AXI_RREADY\n .Dbg_Clk_0(Dbg_Clk_0), \/\/ output wire Dbg_Clk_0\n .Dbg_TDI_0(Dbg_TDI_0), \/\/ output wire Dbg_TDI_0\n .Dbg_TDO_0(Dbg_TDO_0), \/\/ input wire Dbg_TDO_0\n .Dbg_Reg_En_0(Dbg_Reg_En_0), \/\/ output wire [0 : 7] Dbg_Reg_En_0\n .Dbg_Capture_0(Dbg_Capture_0), \/\/ output wire Dbg_Capture_0\n .Dbg_Shift_0(Dbg_Shift_0), \/\/ output wire Dbg_Shift_0\n .Dbg_Update_0(Dbg_Update_0), \/\/ output wire Dbg_Update_0\n .Dbg_Rst_0(Dbg_Rst_0) \/\/ output wire Dbg_Rst_0\n);\n\/\/ INST_TAG_END ------ End INSTANTIATION Template ---------\n\n\/\/ You must compile the wrapper file PWSBD_mdm_1_0.v when simulating\n\/\/ the core, PWSBD_mdm_1_0. When compiling the wrapper file, be sure to\n\/\/ reference the Verilog simulation library.\n\n","avg_line_length":49.8191489362,"max_line_length":73,"alphanum_fraction":0.7345718556} {"size":5596,"ext":"veo","lang":"Verilog","max_stars_count":1.0,"content":"\/\/ (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.\n\/\/ \n\/\/ This file contains confidential and proprietary information\n\/\/ of Xilinx, Inc. and is protected under U.S. and\n\/\/ international copyright and other intellectual property\n\/\/ laws.\n\/\/ \n\/\/ DISCLAIMER\n\/\/ This disclaimer is not a license and does not grant any\n\/\/ rights to the materials distributed herewith. Except as\n\/\/ otherwise provided in a valid license issued to you by\n\/\/ Xilinx, and to the maximum extent permitted by applicable\n\/\/ law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n\/\/ WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n\/\/ AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n\/\/ BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n\/\/ INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n\/\/ (2) Xilinx shall not be liable (whether in contract or tort,\n\/\/ including negligence, or under any other theory of\n\/\/ liability) for any loss or damage of any kind or nature\n\/\/ related to, arising under or in connection with these\n\/\/ materials, including for any direct, or any indirect,\n\/\/ special, incidental, or consequential loss or damage\n\/\/ (including loss of data, profits, goodwill, or any type of\n\/\/ loss or damage suffered as a result of any action brought\n\/\/ by a third party) even if such damage or loss was\n\/\/ reasonably foreseeable or Xilinx had been advised of the\n\/\/ possibility of the same.\n\/\/ \n\/\/ CRITICAL APPLICATIONS\n\/\/ Xilinx products are not designed or intended to be fail-\n\/\/ safe, or for use in any application requiring fail-safe\n\/\/ performance, such as life-support or safety devices or\n\/\/ systems, Class III medical devices, nuclear facilities,\n\/\/ applications related to the deployment of airbags, or any\n\/\/ other applications that could lead to death, personal\n\/\/ injury, or severe property or environmental damage\n\/\/ (individually and collectively, \"Critical\n\/\/ Applications\"). Customer assumes the sole risk and\n\/\/ liability of any use of Xilinx products in Critical\n\/\/ Applications, subject only to applicable laws and\n\/\/ regulations governing limitations on product liability.\n\/\/ \n\/\/ THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n\/\/ PART OF THIS FILE AT ALL TIMES.\n\/\/ \n\/\/ DO NOT MODIFY THIS FILE.\n\n\/\/ IP VLNV: xilinx.com:ip:axi_dwidth_converter:2.1\n\/\/ IP Revision: 7\n\n\/\/ The following must be inserted into your Verilog file for this\n\/\/ core to be instantiated. Change the instance name and port connections\n\/\/ (in parentheses) to your own signal names.\n\n\/\/----------- Begin Cut here for INSTANTIATION Template ---\/\/ INST_TAG\ntop_auto_us_1 your_instance_name (\n .s_axi_aclk(s_axi_aclk), \/\/ input wire s_axi_aclk\n .s_axi_aresetn(s_axi_aresetn), \/\/ input wire s_axi_aresetn\n .s_axi_awaddr(s_axi_awaddr), \/\/ input wire [31 : 0] s_axi_awaddr\n .s_axi_awlen(s_axi_awlen), \/\/ input wire [7 : 0] s_axi_awlen\n .s_axi_awsize(s_axi_awsize), \/\/ input wire [2 : 0] s_axi_awsize\n .s_axi_awburst(s_axi_awburst), \/\/ input wire [1 : 0] s_axi_awburst\n .s_axi_awlock(s_axi_awlock), \/\/ input wire [0 : 0] s_axi_awlock\n .s_axi_awcache(s_axi_awcache), \/\/ input wire [3 : 0] s_axi_awcache\n .s_axi_awprot(s_axi_awprot), \/\/ input wire [2 : 0] s_axi_awprot\n .s_axi_awregion(s_axi_awregion), \/\/ input wire [3 : 0] s_axi_awregion\n .s_axi_awqos(s_axi_awqos), \/\/ input wire [3 : 0] s_axi_awqos\n .s_axi_awvalid(s_axi_awvalid), \/\/ input wire s_axi_awvalid\n .s_axi_awready(s_axi_awready), \/\/ output wire s_axi_awready\n .s_axi_wdata(s_axi_wdata), \/\/ input wire [31 : 0] s_axi_wdata\n .s_axi_wstrb(s_axi_wstrb), \/\/ input wire [3 : 0] s_axi_wstrb\n .s_axi_wlast(s_axi_wlast), \/\/ input wire s_axi_wlast\n .s_axi_wvalid(s_axi_wvalid), \/\/ input wire s_axi_wvalid\n .s_axi_wready(s_axi_wready), \/\/ output wire s_axi_wready\n .s_axi_bresp(s_axi_bresp), \/\/ output wire [1 : 0] s_axi_bresp\n .s_axi_bvalid(s_axi_bvalid), \/\/ output wire s_axi_bvalid\n .s_axi_bready(s_axi_bready), \/\/ input wire s_axi_bready\n .m_axi_awaddr(m_axi_awaddr), \/\/ output wire [31 : 0] m_axi_awaddr\n .m_axi_awlen(m_axi_awlen), \/\/ output wire [7 : 0] m_axi_awlen\n .m_axi_awsize(m_axi_awsize), \/\/ output wire [2 : 0] m_axi_awsize\n .m_axi_awburst(m_axi_awburst), \/\/ output wire [1 : 0] m_axi_awburst\n .m_axi_awlock(m_axi_awlock), \/\/ output wire [0 : 0] m_axi_awlock\n .m_axi_awcache(m_axi_awcache), \/\/ output wire [3 : 0] m_axi_awcache\n .m_axi_awprot(m_axi_awprot), \/\/ output wire [2 : 0] m_axi_awprot\n .m_axi_awregion(m_axi_awregion), \/\/ output wire [3 : 0] m_axi_awregion\n .m_axi_awqos(m_axi_awqos), \/\/ output wire [3 : 0] m_axi_awqos\n .m_axi_awvalid(m_axi_awvalid), \/\/ output wire m_axi_awvalid\n .m_axi_awready(m_axi_awready), \/\/ input wire m_axi_awready\n .m_axi_wdata(m_axi_wdata), \/\/ output wire [63 : 0] m_axi_wdata\n .m_axi_wstrb(m_axi_wstrb), \/\/ output wire [7 : 0] m_axi_wstrb\n .m_axi_wlast(m_axi_wlast), \/\/ output wire m_axi_wlast\n .m_axi_wvalid(m_axi_wvalid), \/\/ output wire m_axi_wvalid\n .m_axi_wready(m_axi_wready), \/\/ input wire m_axi_wready\n .m_axi_bresp(m_axi_bresp), \/\/ input wire [1 : 0] m_axi_bresp\n .m_axi_bvalid(m_axi_bvalid), \/\/ input wire m_axi_bvalid\n .m_axi_bready(m_axi_bready) \/\/ output wire m_axi_bready\n);\n\/\/ INST_TAG_END ------ End INSTANTIATION Template ---------\n\n\/\/ You must compile the wrapper file top_auto_us_1.v when simulating\n\/\/ the core, top_auto_us_1. When compiling the wrapper file, be sure to\n\/\/ reference the Verilog simulation library.\n\n","avg_line_length":53.2952380952,"max_line_length":73,"alphanum_fraction":0.7203359543} {"size":3294,"ext":"veo","lang":"Verilog","max_stars_count":9.0,"content":"\/\/ (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.\n\/\/ \n\/\/ This file contains confidential and proprietary information\n\/\/ of Xilinx, Inc. and is protected under U.S. and\n\/\/ international copyright and other intellectual property\n\/\/ laws.\n\/\/ \n\/\/ DISCLAIMER\n\/\/ This disclaimer is not a license and does not grant any\n\/\/ rights to the materials distributed herewith. Except as\n\/\/ otherwise provided in a valid license issued to you by\n\/\/ Xilinx, and to the maximum extent permitted by applicable\n\/\/ law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n\/\/ WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n\/\/ AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n\/\/ BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n\/\/ INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n\/\/ (2) Xilinx shall not be liable (whether in contract or tort,\n\/\/ including negligence, or under any other theory of\n\/\/ liability) for any loss or damage of any kind or nature\n\/\/ related to, arising under or in connection with these\n\/\/ materials, including for any direct, or any indirect,\n\/\/ special, incidental, or consequential loss or damage\n\/\/ (including loss of data, profits, goodwill, or any type of\n\/\/ loss or damage suffered as a result of any action brought\n\/\/ by a third party) even if such damage or loss was\n\/\/ reasonably foreseeable or Xilinx had been advised of the\n\/\/ possibility of the same.\n\/\/ \n\/\/ CRITICAL APPLICATIONS\n\/\/ Xilinx products are not designed or intended to be fail-\n\/\/ safe, or for use in any application requiring fail-safe\n\/\/ performance, such as life-support or safety devices or\n\/\/ systems, Class III medical devices, nuclear facilities,\n\/\/ applications related to the deployment of airbags, or any\n\/\/ other applications that could lead to death, personal\n\/\/ injury, or severe property or environmental damage\n\/\/ (individually and collectively, \"Critical\n\/\/ Applications\"). Customer assumes the sole risk and\n\/\/ liability of any use of Xilinx products in Critical\n\/\/ Applications, subject only to applicable laws and\n\/\/ regulations governing limitations on product liability.\n\/\/ \n\/\/ THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n\/\/ PART OF THIS FILE AT ALL TIMES.\n\/\/ \n\/\/ DO NOT MODIFY THIS FILE.\n\n\/\/ IP VLNV: xilinx.com:ip:dds_compiler:6.0\n\/\/ IP Revision: 7\n\n\/\/ The following must be inserted into your Verilog file for this\n\/\/ core to be instantiated. Change the instance name and port connections\n\/\/ (in parentheses) to your own signal names.\n\n\/\/----------- Begin Cut here for INSTANTIATION Template ---\/\/ INST_TAG\nipcore_dds_sin_cos_13b_15b your_instance_name (\n .aclk(aclk), \/\/ input wire aclk\n .s_axis_phase_tvalid(s_axis_phase_tvalid), \/\/ input wire s_axis_phase_tvalid\n .s_axis_phase_tdata(s_axis_phase_tdata), \/\/ input wire [31 : 0] s_axis_phase_tdata\n .m_axis_data_tvalid(m_axis_data_tvalid), \/\/ output wire m_axis_data_tvalid\n .m_axis_data_tdata(m_axis_data_tdata) \/\/ output wire [31 : 0] m_axis_data_tdata\n);\n\/\/ INST_TAG_END ------ End INSTANTIATION Template ---------\n\n\/\/ You must compile the wrapper file ipcore_dds_sin_cos_13b_15b.v when simulating\n\/\/ the core, ipcore_dds_sin_cos_13b_15b. When compiling the wrapper file, be sure to\n\/\/ reference the Verilog simulation library.\n\n","avg_line_length":47.0571428571,"max_line_length":87,"alphanum_fraction":0.7513661202} {"size":3499,"ext":"veo","lang":"Verilog","max_stars_count":170.0,"content":"\/\/ (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.\n\/\/ \n\/\/ This file contains confidential and proprietary information\n\/\/ of Xilinx, Inc. and is protected under U.S. and\n\/\/ international copyright and other intellectual property\n\/\/ laws.\n\/\/ \n\/\/ DISCLAIMER\n\/\/ This disclaimer is not a license and does not grant any\n\/\/ rights to the materials distributed herewith. Except as\n\/\/ otherwise provided in a valid license issued to you by\n\/\/ Xilinx, and to the maximum extent permitted by applicable\n\/\/ law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n\/\/ WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n\/\/ AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n\/\/ BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n\/\/ INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n\/\/ (2) Xilinx shall not be liable (whether in contract or tort,\n\/\/ including negligence, or under any other theory of\n\/\/ liability) for any loss or damage of any kind or nature\n\/\/ related to, arising under or in connection with these\n\/\/ materials, including for any direct, or any indirect,\n\/\/ special, incidental, or consequential loss or damage\n\/\/ (including loss of data, profits, goodwill, or any type of\n\/\/ loss or damage suffered as a result of any action brought\n\/\/ by a third party) even if such damage or loss was\n\/\/ reasonably foreseeable or Xilinx had been advised of the\n\/\/ possibility of the same.\n\/\/ \n\/\/ CRITICAL APPLICATIONS\n\/\/ Xilinx products are not designed or intended to be fail-\n\/\/ safe, or for use in any application requiring fail-safe\n\/\/ performance, such as life-support or safety devices or\n\/\/ systems, Class III medical devices, nuclear facilities,\n\/\/ applications related to the deployment of airbags, or any\n\/\/ other applications that could lead to death, personal\n\/\/ injury, or severe property or environmental damage\n\/\/ (individually and collectively, \"Critical\n\/\/ Applications\"). Customer assumes the sole risk and\n\/\/ liability of any use of Xilinx products in Critical\n\/\/ Applications, subject only to applicable laws and\n\/\/ regulations governing limitations on product liability.\n\/\/ \n\/\/ THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n\/\/ PART OF THIS FILE AT ALL TIMES.\n\/\/ \n\/\/ DO NOT MODIFY THIS FILE.\n\n\/\/ IP VLNV: xilinx.com:ip:fifo_generator:13.2\n\/\/ IP Revision: 5\n\n\/\/ The following must be inserted into your Verilog file for this\n\/\/ core to be instantiated. Change the instance name and port connections\n\/\/ (in parentheses) to your own signal names.\n\n\/\/----------- Begin Cut here for INSTANTIATION Template ---\/\/ INST_TAG\nfifo_generator_0 your_instance_name (\n .rst(rst), \/\/ input wire rst\n .wr_clk(wr_clk), \/\/ input wire wr_clk\n .rd_clk(rd_clk), \/\/ input wire rd_clk\n .din(din), \/\/ input wire [63 : 0] din\n .wr_en(wr_en), \/\/ input wire wr_en\n .rd_en(rd_en), \/\/ input wire rd_en\n .dout(dout), \/\/ output wire [127 : 0] dout\n .full(full), \/\/ output wire full\n .empty(empty), \/\/ output wire empty\n .valid(valid), \/\/ output wire valid\n .wr_rst_busy(wr_rst_busy), \/\/ output wire wr_rst_busy\n .rd_rst_busy(rd_rst_busy) \/\/ output wire rd_rst_busy\n);\n\/\/ INST_TAG_END ------ End INSTANTIATION Template ---------\n\n\/\/ You must compile the wrapper file fifo_generator_0.v when simulating\n\/\/ the core, fifo_generator_0. When compiling the wrapper file, be sure to\n\/\/ reference the Verilog simulation library.\n\n","avg_line_length":45.4415584416,"max_line_length":74,"alphanum_fraction":0.7122034867} {"size":3282,"ext":"veo","lang":"Verilog","max_stars_count":null,"content":"\/\/ (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.\n\/\/ \n\/\/ This file contains confidential and proprietary information\n\/\/ of Xilinx, Inc. and is protected under U.S. and\n\/\/ international copyright and other intellectual property\n\/\/ laws.\n\/\/ \n\/\/ DISCLAIMER\n\/\/ This disclaimer is not a license and does not grant any\n\/\/ rights to the materials distributed herewith. Except as\n\/\/ otherwise provided in a valid license issued to you by\n\/\/ Xilinx, and to the maximum extent permitted by applicable\n\/\/ law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n\/\/ WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n\/\/ AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n\/\/ BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n\/\/ INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n\/\/ (2) Xilinx shall not be liable (whether in contract or tort,\n\/\/ including negligence, or under any other theory of\n\/\/ liability) for any loss or damage of any kind or nature\n\/\/ related to, arising under or in connection with these\n\/\/ materials, including for any direct, or any indirect,\n\/\/ special, incidental, or consequential loss or damage\n\/\/ (including loss of data, profits, goodwill, or any type of\n\/\/ loss or damage suffered as a result of any action brought\n\/\/ by a third party) even if such damage or loss was\n\/\/ reasonably foreseeable or Xilinx had been advised of the\n\/\/ possibility of the same.\n\/\/ \n\/\/ CRITICAL APPLICATIONS\n\/\/ Xilinx products are not designed or intended to be fail-\n\/\/ safe, or for use in any application requiring fail-safe\n\/\/ performance, such as life-support or safety devices or\n\/\/ systems, Class III medical devices, nuclear facilities,\n\/\/ applications related to the deployment of airbags, or any\n\/\/ other applications that could lead to death, personal\n\/\/ injury, or severe property or environmental damage\n\/\/ (individually and collectively, \"Critical\n\/\/ Applications\"). Customer assumes the sole risk and\n\/\/ liability of any use of Xilinx products in Critical\n\/\/ Applications, subject only to applicable laws and\n\/\/ regulations governing limitations on product liability.\n\/\/ \n\/\/ THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n\/\/ PART OF THIS FILE AT ALL TIMES.\n\/\/ \n\/\/ DO NOT MODIFY THIS FILE.\n\n\/\/ IP VLNV: xilinx.com:ip:xbip_multadd:3.0\n\/\/ IP Revision: 13\n\n\/\/ The following must be inserted into your Verilog file for this\n\/\/ core to be instantiated. Change the instance name and port connections\n\/\/ (in parentheses) to your own signal names.\n\n\/\/----------- Begin Cut here for INSTANTIATION Template ---\/\/ INST_TAG\nxbip_multadd_0 your_instance_name (\n .CLK(CLK), \/\/ input wire CLK\n .CE(CE), \/\/ input wire CE\n .SCLR(SCLR), \/\/ input wire SCLR\n .A(A), \/\/ input wire [31 : 0] A\n .B(B), \/\/ input wire [31 : 0] B\n .C(C), \/\/ input wire [31 : 0] C\n .SUBTRACT(SUBTRACT), \/\/ input wire SUBTRACT\n .P(P), \/\/ output wire [63 : 0] P\n .PCOUT(PCOUT) \/\/ output wire [47 : 0] PCOUT\n);\n\/\/ INST_TAG_END ------ End INSTANTIATION Template ---------\n\n\/\/ You must compile the wrapper file xbip_multadd_0.v when simulating\n\/\/ the core, xbip_multadd_0. When compiling the wrapper file, be sure to\n\/\/ reference the Verilog simulation library.\n\n","avg_line_length":44.3513513514,"max_line_length":73,"alphanum_fraction":0.711456429} {"size":3642,"ext":"veo","lang":"Verilog","max_stars_count":6.0,"content":"\n\/\/ \n\/\/ (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.\n\/\/ \n\/\/ This file contains confidential and proprietary information\n\/\/ of Xilinx, Inc. and is protected under U.S. and\n\/\/ international copyright and other intellectual property\n\/\/ laws.\n\/\/ \n\/\/ DISCLAIMER\n\/\/ This disclaimer is not a license and does not grant any\n\/\/ rights to the materials distributed herewith. Except as\n\/\/ otherwise provided in a valid license issued to you by\n\/\/ Xilinx, and to the maximum extent permitted by applicable\n\/\/ law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n\/\/ WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n\/\/ AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n\/\/ BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n\/\/ INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n\/\/ (2) Xilinx shall not be liable (whether in contract or tort,\n\/\/ including negligence, or under any other theory of\n\/\/ liability) for any loss or damage of any kind or nature\n\/\/ related to, arising under or in connection with these\n\/\/ materials, including for any direct, or any indirect,\n\/\/ special, incidental, or consequential loss or damage\n\/\/ (including loss of data, profits, goodwill, or any type of\n\/\/ loss or damage suffered as a result of any action brought\n\/\/ by a third party) even if such damage or loss was\n\/\/ reasonably foreseeable or Xilinx had been advised of the\n\/\/ possibility of the same.\n\/\/ \n\/\/ CRITICAL APPLICATIONS\n\/\/ Xilinx products are not designed or intended to be fail-\n\/\/ safe, or for use in any application requiring fail-safe\n\/\/ performance, such as life-support or safety devices or\n\/\/ systems, Class III medical devices, nuclear facilities,\n\/\/ applications related to the deployment of airbags, or any\n\/\/ other applications that could lead to death, personal\n\/\/ injury, or severe property or environmental damage\n\/\/ (individually and collectively, \"Critical\n\/\/ Applications\"). Customer assumes the sole risk and\n\/\/ liability of any use of Xilinx products in Critical\n\/\/ Applications, subject only to applicable laws and\n\/\/ regulations governing limitations on product liability.\n\/\/ \n\/\/ THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n\/\/ PART OF THIS FILE AT ALL TIMES.\n\/\/ \n\/\/----------------------------------------------------------------------------\n\/\/ User entered comments\n\/\/----------------------------------------------------------------------------\n\/\/ None\n\/\/\n\/\/----------------------------------------------------------------------------\n\/\/ Output Output Phase Duty Cycle Pk-to-Pk Phase\n\/\/ Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)\n\/\/----------------------------------------------------------------------------\n\/\/ _cpu_clk__85.00000______0.000______50.0_______87.746_____82.376\n\/\/ _sys_clk__100.00000______0.000______50.0_______85.291_____82.376\n\/\/\n\/\/----------------------------------------------------------------------------\n\/\/ Input Clock Freq (MHz) Input Jitter (UI)\n\/\/----------------------------------------------------------------------------\n\/\/ __primary_________100.000____________0.010\n\n\/\/ The following must be inserted into your Verilog file for this\n\/\/ core to be instantiated. Change the instance name and port connections\n\/\/ (in parentheses) to your own signal names.\n\n\/\/----------- Begin Cut here for INSTANTIATION Template ---\/\/ INST_TAG\n\n clk_pll_85 instance_name\n (\n \/\/ Clock out ports\n .cpu_clk(cpu_clk), \/\/ output cpu_clk\n .sys_clk(sys_clk), \/\/ output sys_clk\n \/\/ Clock in ports\n .clk_in1(clk_in1)); \/\/ input clk_in1\n\/\/ INST_TAG_END ------ End INSTANTIATION Template ---------\n","avg_line_length":45.525,"max_line_length":78,"alphanum_fraction":0.6383855025} {"size":3148,"ext":"veo","lang":"Verilog","max_stars_count":null,"content":"\/\/ (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.\n\/\/ \n\/\/ This file contains confidential and proprietary information\n\/\/ of Xilinx, Inc. and is protected under U.S. and\n\/\/ international copyright and other intellectual property\n\/\/ laws.\n\/\/ \n\/\/ DISCLAIMER\n\/\/ This disclaimer is not a license and does not grant any\n\/\/ rights to the materials distributed herewith. Except as\n\/\/ otherwise provided in a valid license issued to you by\n\/\/ Xilinx, and to the maximum extent permitted by applicable\n\/\/ law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n\/\/ WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n\/\/ AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n\/\/ BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n\/\/ INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n\/\/ (2) Xilinx shall not be liable (whether in contract or tort,\n\/\/ including negligence, or under any other theory of\n\/\/ liability) for any loss or damage of any kind or nature\n\/\/ related to, arising under or in connection with these\n\/\/ materials, including for any direct, or any indirect,\n\/\/ special, incidental, or consequential loss or damage\n\/\/ (including loss of data, profits, goodwill, or any type of\n\/\/ loss or damage suffered as a result of any action brought\n\/\/ by a third party) even if such damage or loss was\n\/\/ reasonably foreseeable or Xilinx had been advised of the\n\/\/ possibility of the same.\n\/\/ \n\/\/ CRITICAL APPLICATIONS\n\/\/ Xilinx products are not designed or intended to be fail-\n\/\/ safe, or for use in any application requiring fail-safe\n\/\/ performance, such as life-support or safety devices or\n\/\/ systems, Class III medical devices, nuclear facilities,\n\/\/ applications related to the deployment of airbags, or any\n\/\/ other applications that could lead to death, personal\n\/\/ injury, or severe property or environmental damage\n\/\/ (individually and collectively, \"Critical\n\/\/ Applications\"). Customer assumes the sole risk and\n\/\/ liability of any use of Xilinx products in Critical\n\/\/ Applications, subject only to applicable laws and\n\/\/ regulations governing limitations on product liability.\n\/\/ \n\/\/ THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n\/\/ PART OF THIS FILE AT ALL TIMES.\n\/\/ \n\/\/ DO NOT MODIFY THIS FILE.\n\n\/\/ IP VLNV: xilinx.com:ip:blk_mem_gen:8.4\n\/\/ IP Revision: 1\n\n\/\/ The following must be inserted into your Verilog file for this\n\/\/ core to be instantiated. Change the instance name and port connections\n\/\/ (in parentheses) to your own signal names.\n\n\/\/----------- Begin Cut here for INSTANTIATION Template ---\/\/ INST_TAG\nip1_rm_ram your_instance_name (\n .clka(clka), \/\/ input wire clka\n .wea(wea), \/\/ input wire [0 : 0] wea\n .addra(addra), \/\/ input wire [7 : 0] addra\n .dina(dina), \/\/ input wire [15 : 0] dina\n .clkb(clkb), \/\/ input wire clkb\n .addrb(addrb), \/\/ input wire [7 : 0] addrb\n .doutb(doutb) \/\/ output wire [15 : 0] doutb\n);\n\/\/ INST_TAG_END ------ End INSTANTIATION Template ---------\n\n\/\/ You must compile the wrapper file ip1_rm_ram.v when simulating\n\/\/ the core, ip1_rm_ram. When compiling the wrapper file, be sure to\n\/\/ reference the Verilog simulation library.\n\n","avg_line_length":43.7222222222,"max_line_length":73,"alphanum_fraction":0.7341168996} {"size":3283,"ext":"veo","lang":"Verilog","max_stars_count":null,"content":"\/\/ (c) Copyright 1995-2019 Xilinx, Inc. All rights reserved.\n\/\/ \n\/\/ This file contains confidential and proprietary information\n\/\/ of Xilinx, Inc. and is protected under U.S. and\n\/\/ international copyright and other intellectual property\n\/\/ laws.\n\/\/ \n\/\/ DISCLAIMER\n\/\/ This disclaimer is not a license and does not grant any\n\/\/ rights to the materials distributed herewith. Except as\n\/\/ otherwise provided in a valid license issued to you by\n\/\/ Xilinx, and to the maximum extent permitted by applicable\n\/\/ law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n\/\/ WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n\/\/ AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n\/\/ BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n\/\/ INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n\/\/ (2) Xilinx shall not be liable (whether in contract or tort,\n\/\/ including negligence, or under any other theory of\n\/\/ liability) for any loss or damage of any kind or nature\n\/\/ related to, arising under or in connection with these\n\/\/ materials, including for any direct, or any indirect,\n\/\/ special, incidental, or consequential loss or damage\n\/\/ (including loss of data, profits, goodwill, or any type of\n\/\/ loss or damage suffered as a result of any action brought\n\/\/ by a third party) even if such damage or loss was\n\/\/ reasonably foreseeable or Xilinx had been advised of the\n\/\/ possibility of the same.\n\/\/ \n\/\/ CRITICAL APPLICATIONS\n\/\/ Xilinx products are not designed or intended to be fail-\n\/\/ safe, or for use in any application requiring fail-safe\n\/\/ performance, such as life-support or safety devices or\n\/\/ systems, Class III medical devices, nuclear facilities,\n\/\/ applications related to the deployment of airbags, or any\n\/\/ other applications that could lead to death, personal\n\/\/ injury, or severe property or environmental damage\n\/\/ (individually and collectively, \"Critical\n\/\/ Applications\"). Customer assumes the sole risk and\n\/\/ liability of any use of Xilinx products in Critical\n\/\/ Applications, subject only to applicable laws and\n\/\/ regulations governing limitations on product liability.\n\/\/ \n\/\/ THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n\/\/ PART OF THIS FILE AT ALL TIMES.\n\/\/ \n\/\/ DO NOT MODIFY THIS FILE.\n\n\/\/ IP VLNV: xilinx.com:ip:cordic:6.0\n\/\/ IP Revision: 14\n\n\/\/ The following must be inserted into your Verilog file for this\n\/\/ core to be instantiated. Change the instance name and port connections\n\/\/ (in parentheses) to your own signal names.\n\n\/\/----------- Begin Cut here for INSTANTIATION Template ---\/\/ INST_TAG\ncordic_0 your_instance_name (\n .aclk(aclk), \/\/ input wire aclk\n .s_axis_cartesian_tvalid(s_axis_cartesian_tvalid), \/\/ input wire s_axis_cartesian_tvalid\n .s_axis_cartesian_tdata(s_axis_cartesian_tdata), \/\/ input wire [23 : 0] s_axis_cartesian_tdata\n .m_axis_dout_tvalid(m_axis_dout_tvalid), \/\/ output wire m_axis_dout_tvalid\n .m_axis_dout_tdata(m_axis_dout_tdata) \/\/ output wire [15 : 0] m_axis_dout_tdata\n);\n\/\/ INST_TAG_END ------ End INSTANTIATION Template ---------\n\n\/\/ You must compile the wrapper file cordic_0.v when simulating\n\/\/ the core, cordic_0. When compiling the wrapper file, be sure to\n\/\/ reference the Verilog simulation library.\n\n","avg_line_length":46.9,"max_line_length":99,"alphanum_fraction":0.7432226622} {"size":3325,"ext":"veo","lang":"Verilog","max_stars_count":null,"content":"\/\/ (c) Copyright 1995-2019 Xilinx, Inc. All rights reserved.\n\/\/ \n\/\/ This file contains confidential and proprietary information\n\/\/ of Xilinx, Inc. and is protected under U.S. and\n\/\/ international copyright and other intellectual property\n\/\/ laws.\n\/\/ \n\/\/ DISCLAIMER\n\/\/ This disclaimer is not a license and does not grant any\n\/\/ rights to the materials distributed herewith. Except as\n\/\/ otherwise provided in a valid license issued to you by\n\/\/ Xilinx, and to the maximum extent permitted by applicable\n\/\/ law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n\/\/ WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n\/\/ AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n\/\/ BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n\/\/ INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n\/\/ (2) Xilinx shall not be liable (whether in contract or tort,\n\/\/ including negligence, or under any other theory of\n\/\/ liability) for any loss or damage of any kind or nature\n\/\/ related to, arising under or in connection with these\n\/\/ materials, including for any direct, or any indirect,\n\/\/ special, incidental, or consequential loss or damage\n\/\/ (including loss of data, profits, goodwill, or any type of\n\/\/ loss or damage suffered as a result of any action brought\n\/\/ by a third party) even if such damage or loss was\n\/\/ reasonably foreseeable or Xilinx had been advised of the\n\/\/ possibility of the same.\n\/\/ \n\/\/ CRITICAL APPLICATIONS\n\/\/ Xilinx products are not designed or intended to be fail-\n\/\/ safe, or for use in any application requiring fail-safe\n\/\/ performance, such as life-support or safety devices or\n\/\/ systems, Class III medical devices, nuclear facilities,\n\/\/ applications related to the deployment of airbags, or any\n\/\/ other applications that could lead to death, personal\n\/\/ injury, or severe property or environmental damage\n\/\/ (individually and collectively, \"Critical\n\/\/ Applications\"). Customer assumes the sole risk and\n\/\/ liability of any use of Xilinx products in Critical\n\/\/ Applications, subject only to applicable laws and\n\/\/ regulations governing limitations on product liability.\n\/\/ \n\/\/ THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n\/\/ PART OF THIS FILE AT ALL TIMES.\n\/\/ \n\/\/ DO NOT MODIFY THIS FILE.\n\n\/\/ IP VLNV: xilinx.com:ip:fifo_generator:13.2\n\/\/ IP Revision: 5\n\n\/\/ The following must be inserted into your Verilog file for this\n\/\/ core to be instantiated. Change the instance name and port connections\n\/\/ (in parentheses) to your own signal names.\n\n\/\/----------- Begin Cut here for INSTANTIATION Template ---\/\/ INST_TAG\nTriangleFifo your_instance_name (\n .clk(clk), \/\/ input wire clk\n .srst(srst), \/\/ input wire srst\n .din(din), \/\/ input wire [58 : 0] din\n .wr_en(wr_en), \/\/ input wire wr_en\n .rd_en(rd_en), \/\/ input wire rd_en\n .dout(dout), \/\/ output wire [58 : 0] dout\n .full(full), \/\/ output wire full\n .almost_full(almost_full), \/\/ output wire almost_full\n .empty(empty) \/\/ output wire empty\n);\n\/\/ INST_TAG_END ------ End INSTANTIATION Template ---------\n\n\/\/ You must compile the wrapper file TriangleFifo.v when simulating\n\/\/ the core, TriangleFifo. When compiling the wrapper file, be sure to\n\/\/ reference the Verilog simulation library.\n\n","avg_line_length":44.9324324324,"max_line_length":73,"alphanum_fraction":0.7151879699} {"size":4229,"ext":"veo","lang":"Verilog","max_stars_count":4.0,"content":"\/*******************************************************************************\n* This file is owned and controlled by Xilinx and must be used solely *\n* for design, simulation, implementation and creation of design files *\n* limited to Xilinx devices or technologies. Use with non-Xilinx *\n* devices or technologies is expressly prohibited and immediately *\n* terminates your license. *\n* *\n* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION \"AS IS\" SOLELY *\n* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY *\n* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE *\n* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS *\n* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY *\n* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY *\n* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY *\n* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *\n* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *\n* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *\n* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *\n* PARTICULAR PURPOSE. *\n* *\n* Xilinx products are not intended for use in life support appliances, *\n* devices, or systems. Use in such applications are expressly *\n* prohibited. *\n* *\n* (c) Copyright 1995-2018 Xilinx, Inc. *\n* All rights reserved. *\n*******************************************************************************\/\n\n\/*******************************************************************************\n* Generated from core with identifier: xilinx.com:ip:blk_mem_gen:7.3 *\n* *\n* The Xilinx LogiCORE IP Block Memory Generator replaces the Dual Port *\n* Block Memory and Single Port Block Memory LogiCOREs, but is not a *\n* direct drop-in replacement. It should be used in all new Xilinx *\n* designs. The core supports RAM and ROM functions over a wide range of *\n* widths and depths. Use this core to generate block memories with *\n* symmetric or asymmetric read and write port widths, as well as cores *\n* which can perform simultaneous write operations to separate *\n* locations, and simultaneous read operations from the same location. *\n* For more information on differences in interface and feature support *\n* between this core and the Dual Port Block Memory and Single Port *\n* Block Memory LogiCOREs, please consult the data sheet. *\n*******************************************************************************\/\n\n\/\/ The following must be inserted into your Verilog file for this\n\/\/ core to be instantiated. Change the instance name and port connections\n\/\/ (in parentheses) to your own signal names.\n\n\/\/----------- Begin Cut here for INSTANTIATION Template ---\/\/ INST_TAG\nise_IRAM your_instance_name (\n .clka(clka), \/\/ input clka\n .ena(ena), \/\/ input ena\n .wea(wea), \/\/ input [0 : 0] wea\n .addra(addra), \/\/ input [13 : 0] addra\n .dina(dina), \/\/ input [48 : 0] dina\n .douta(douta) \/\/ output [48 : 0] douta\n);\n\/\/ INST_TAG_END ------ End INSTANTIATION Template ---------\n\n\/\/ You must compile the wrapper file ise_IRAM.v when simulating\n\/\/ the core, ise_IRAM. When compiling the wrapper file, be sure to\n\/\/ reference the XilinxCoreLib Verilog simulation library. For detailed\n\/\/ instructions, please refer to the \"CORE Generator Help\".\n\n","avg_line_length":65.0615384615,"max_line_length":80,"alphanum_fraction":0.530858359}