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/*
Legal Notice: (C)2007 Altera Corporation. All rights reserved. Your
use of Altera Corporation's design tools, logic functions and other
software and tools, and its AMPP partner logic functions, and any
output files any of the foregoing (including device programming or
simulation files), and any associated documentation or information are
expressly subject to the terms and conditions of the Altera Program
License Subscription Agreement or other applicable license agreement,
including, without limitation, that your use is for the sole purpose
of programming logic devices manufactured by Altera and sold by Altera
or its authorized distributors. Please refer to the applicable
agreement for further details.
*/
/*
Author: JCJB
Date: 11/04/2007
This bursting read master is passed a word aligned address, length in bytes,
and a 'go' bit. The master will continue to post full length bursts until
the length register reaches a value less than a full burst. A single final
burst is then posted and when all the reads return the done bit will be asserted.
To use this master you must simply drive the control signals into this block,
and also read the data from the exposed read FIFO. To read from the exposed FIFO
use the 'user_read_buffer' signal to pop data from the FIFO 'user_buffer_data'.
The signal 'user_data_available' is asserted whenever data is available from the
exposed FIFO.
Update by FabienM <[email protected]>
- adding scfifo verilog model description
*/
`timescale 1 ps / 1 ps
// altera message_off 10230
`define FIFODEPTH_LOG2_DEF 5
/* altera scfifo model rewritten */
module scfifo (
input aclr,
input clock,
input [31:0] data,
output empty,
output [31:0] q,
input rdreq,
output [`FIFODEPTH_LOG2_DEF-1:0] usedw,
input wrreq);
localparam lpm_width = 32;
localparam lpm_numwords = 32; // FIFODEPTH
localparam lpm_showahead = "ON";
localparam use_eab = "ON";
localparam add_ram_output_register = "OFF";
localparam underflow_checking = "OFF";
localparam overflow_checking = "OFF";
assign q = buf_out;
assign empty = buf_empty;
assign usedw = fifo_counter;
reg[lpm_width-1:0] buf_out;
reg buf_empty, buf_full;
reg[lpm_numwords :0] fifo_counter;
// pointer to read and write addresses
reg[`FIFODEPTH_LOG2_DEF-1:0] rd_ptr, wr_ptr;
reg[lpm_width:0] buf_mem[lpm_numwords-1 : 0];
always @(fifo_counter)
begin
buf_empty = (fifo_counter==0);
buf_full = (fifo_counter==lpm_numwords);
end
always @(posedge clock or posedge aclr)
begin
if(aclr)
fifo_counter <= 0;
else if( (!buf_full && wrreq) && ( !buf_empty && rdreq ) )
fifo_counter <= fifo_counter;
else if( !buf_full && wrreq )
fifo_counter <= fifo_counter + 1;
else if( !buf_empty && rdreq )
fifo_counter <= fifo_counter - 1;
else
fifo_counter <= fifo_counter;
end
always @( posedge clock or posedge aclr)
begin
if( aclr )
buf_out <= 0;
else
begin
if( rdreq && !buf_empty )
buf_out <= buf_mem[rd_ptr];
else
buf_out <= buf_out;
end
end
always @(posedge clock)
begin
if( wrreq && !buf_full )
buf_mem[ wr_ptr ] <= data;
else
buf_mem[ wr_ptr ] <= buf_mem[ wr_ptr ];
end
always@(posedge clock or posedge aclr)
begin
if( aclr )
begin
wr_ptr <= 0;
rd_ptr <= 0;
end
else
begin
if( !buf_full && wrreq ) wr_ptr <= wr_ptr + 1;
else wr_ptr <= wr_ptr;
if( !buf_empty && rdreq ) rd_ptr <= rd_ptr + 1;
else rd_ptr <= rd_ptr;
end
end
endmodule
module burst_read_master (
clk,
reset,
// control inputs and outputs
control_fixed_location, // When set the master address will not increment
control_read_base, // Word aligned byte address
control_read_length, // Number of bytes to transfer
control_go,
control_done,
control_early_done,
// user logic inputs and outputs
user_read_buffer,
user_buffer_data,
user_data_available,
// master inputs and outputs
master_address,
master_read,
master_byteenable,
master_readdata,
master_readdatavalid,
master_burstcount,
master_waitrequest);
parameter MAXBURSTCOUNT = 16; // in word
parameter BURSTCOUNTWIDTH = 5;
parameter DATAWIDTH = 32;
parameter BYTEENABLEWIDTH = 4;
parameter ADDRESSWIDTH = 32;
parameter FIFODEPTH = 32;
parameter FIFODEPTH_LOG2 = `FIFODEPTH_LOG2_DEF;
parameter FIFOUSEMEMORY = 1; // set to 0 to use LEs instead
input clk;
input reset;
// control inputs and outputs
input control_fixed_location;
input [ADDRESSWIDTH-1:0] control_read_base;
input [ADDRESSWIDTH-1:0] control_read_length;
input control_go;
output wire control_done;
// don't use this unless you know what you are doing,
// it's going to fire when the last read is posted,
// not when the last data returns!
output wire control_early_done;
// user logic inputs and outputs
input user_read_buffer;
output wire [DATAWIDTH-1:0] user_buffer_data;
output wire user_data_available;
// master inputs and outputs
input master_waitrequest;
input master_readdatavalid;
input [DATAWIDTH-1:0] master_readdata;
output wire [ADDRESSWIDTH-1:0] master_address;
output wire master_read;
output wire [BYTEENABLEWIDTH-1:0] master_byteenable;
output wire [BURSTCOUNTWIDTH-1:0] master_burstcount;
// internal control signals
reg control_fixed_location_d1;
wire fifo_empty;
reg [ADDRESSWIDTH-1:0] address;
reg [ADDRESSWIDTH-1:0] length;
reg [FIFODEPTH_LOG2-1:0] reads_pending;
wire increment_address;
wire [BURSTCOUNTWIDTH-1:0] burst_count;
wire [BURSTCOUNTWIDTH-1:0] first_short_burst_count;
wire first_short_burst_enable;
wire [BURSTCOUNTWIDTH-1:0] final_short_burst_count;
wire final_short_burst_enable;
wire [BURSTCOUNTWIDTH-1:0] burst_boundary_word_address;
reg burst_begin;
wire too_many_reads_pending;
wire [FIFODEPTH_LOG2-1:0] fifo_used;
// registering the control_fixed_location bit
always @ (posedge clk or posedge reset)
begin
if (reset == 1)
begin
control_fixed_location_d1 <= 0;
end
else
begin
if (control_go == 1)
begin
control_fixed_location_d1 <= control_fixed_location;
end
end
end
// master address logic
always @ (posedge clk or posedge reset)
begin
if (reset == 1)
begin
address <= 0;
end
else
begin
if(control_go == 1)
begin
address <= control_read_base;
end
else if((increment_address == 1) & (control_fixed_location_d1 == 0))
begin
// always performing word size accesses,
// increment by the burst count presented
address <= address + (burst_count * BYTEENABLEWIDTH);
end
end
end
// master length logic
always @ (posedge clk or posedge reset)
begin
if (reset == 1)
begin
length <= 0;
end
else
begin
if(control_go == 1)
begin
length <= control_read_length;
end
else if(increment_address == 1)
begin
// always performing word size accesses,
// decrement by the burst count presented
length <= length - (burst_count * BYTEENABLEWIDTH);
end
end
end
// controlled signals going to the master/control ports
assign master_address = address;
// all ones, always performing word size accesses
assign master_byteenable = -1;
assign master_burstcount = burst_count;
// need to make sure that the reads have returned before firing the done bit
assign control_done = (length == 0) & (reads_pending == 0);
// advanced feature, you should use 'control_done' if you need all
// the reads to return first
assign control_early_done = (length == 0);
assign master_read = (too_many_reads_pending == 0) & (length != 0);
assign burst_boundary_word_address = ((address / BYTEENABLEWIDTH) & (MAXBURSTCOUNT - 1));
assign first_short_burst_enable = (burst_boundary_word_address != 0);
assign final_short_burst_enable = (length < (MAXBURSTCOUNT * BYTEENABLEWIDTH));
// if the burst boundary isn't a multiple of 2 then must post a burst of
// 1 to get to a multiple of 2 for the next burst
assign first_short_burst_count = ((burst_boundary_word_address & 1'b1) == 1'b1)? 1 :
(((MAXBURSTCOUNT - burst_boundary_word_address) < (length / BYTEENABLEWIDTH))?
(MAXBURSTCOUNT - burst_boundary_word_address) : (length / BYTEENABLEWIDTH));
assign final_short_burst_count = (length / BYTEENABLEWIDTH);
// this will get the transfer back on a burst boundary,
assign burst_count = (first_short_burst_enable == 1)? first_short_burst_count :
(final_short_burst_enable == 1)? final_short_burst_count : MAXBURSTCOUNT;
assign increment_address =
(too_many_reads_pending == 0) & (master_waitrequest == 0) & (length != 0);
// make sure there are fewer reads posted than room in the FIFO
assign too_many_reads_pending = (reads_pending + fifo_used) >= (FIFODEPTH - MAXBURSTCOUNT - 4);
// tracking FIFO
always @ (posedge clk or posedge reset)
begin
if (reset == 1)
begin
reads_pending <= 0;
end
else
begin
if(increment_address == 1)
begin
if(master_readdatavalid == 0)
begin
reads_pending <= reads_pending + burst_count;
end
else
begin
// a burst read was posted, but a word returned
reads_pending <= reads_pending + burst_count - 1;
end
end
else
begin
if(master_readdatavalid == 0)
begin
// burst read was not posted and no read returned
reads_pending <= reads_pending;
end
else
begin
// burst read was not posted but a word returned
reads_pending <= reads_pending - 1;
end
end
end
end
// read data feeding user logic
assign user_data_available = !fifo_empty;
scfifo the_master_to_user_fifo (
.aclr (reset),
.clock (clk),
.data (master_readdata),
.empty (fifo_empty),
.q (user_buffer_data),
.rdreq (user_read_buffer),
.usedw (fifo_used),
.wrreq (master_readdatavalid)
);
defparam the_master_to_user_fifo.lpm_width = DATAWIDTH;
defparam the_master_to_user_fifo.lpm_numwords = FIFODEPTH;
defparam the_master_to_user_fifo.lpm_showahead = "ON";
defparam the_master_to_user_fifo.use_eab = (FIFOUSEMEMORY == 1)? "ON" : "OFF";
defparam the_master_to_user_fifo.add_ram_output_register = "OFF";
defparam the_master_to_user_fifo.underflow_checking = "OFF";
defparam the_master_to_user_fifo.overflow_checking = "OFF";
initial begin
$dumpfile("waveform.vcd");
$dumpvars(0, burst_read_master);
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 15:50:04 07/21/2014
// Design Name:
// Module Name: divider
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module divider(
input [7:0] div, // dividend switch [15:8]
input [7:0] dvr, // divisor switch [7:0]
input clk,
output [7:0] quotient, // quotient
output [7:0] remainder // remainder
);
integer i;
//reg [7:0] r_d_diff;
reg [7:0] diff; // remainder - divisor diff result
//reg [8:0] c0;
reg [7:0] qu;// quotient
reg [7:0] rem;// remainder
always @(posedge clk) begin
//c0[0] = 1'b1;
rem [7:0] = 8'b0; // assign reminader to all zeros initially
qu [7:0] = div[7:0]; // place dividend in Quotient
for (i=0;i<=7;i=i+1) begin
//repeat (8)
rem = rem<<1;// first iteration shift
rem[0] = qu[7];// first iteration shift
qu = qu<<1;// first iteration shift
qu[0] = 1'b0;// first iteration shift
if ( rem >= dvr) begin
rem = rem-dvr;
qu[0] = 1'b1;
end
end
end
assign remainder [7:0] = rem[7:0];
assign quotient [7:0] = qu[7:0];
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
reg _ranit;
reg [2:0] xor3;
reg [1:0] xor2;
reg [0:0] xor1;
reg [2:0] ma, mb;
reg [9:0] mc;
reg [4:0] mr1;
reg [30:0] mr2;
reg [67:0] sh1;
reg [67:0] shq;
wire foo, bar; assign {foo,bar} = 2'b1_0;
// surefire lint_off STMINI
initial _ranit = 0;
wire [4:0] cond_check = (( xor2 == 2'b11) ? 5'h1
: (xor2 == 2'b00) ? 5'h2
: (xor2 == 2'b01) ? 5'h3
: 5'h4);
wire ctrue = 1'b1 ? cond_check[1] : cond_check[0];
wire cfalse = 1'b0 ? cond_check[1] : cond_check[0];
wire cif = cond_check[2] ? cond_check[1] : cond_check[0];
wire cifn = (!cond_check[2]) ? cond_check[1] : cond_check[0];
wire [4:0] doubleconc = {1'b0, 1'b1, 1'b0, cond_check[0], 1'b1};
wire zero = 1'b0;
wire one = 1'b1;
wire [5:0] rep6 = {6{one}};
// verilator lint_off WIDTH
localparam [3:0] bug764_p11 = 1'bx;
// verilator lint_on WIDTH
always @ (posedge clk) begin
if (!_ranit) begin
_ranit <= 1;
if (rep6 != 6'b111111) $stop;
if (!one) $stop;
if (~one) $stop;
if (( 1'b0 ? 3'h3 : 1'b0 ? 3'h2 : 1'b1 ? 3'h1 : 3'h0) !== 3'h1) $stop;
// verilator lint_off WIDTH
if (( 8'h10 + 1'b0 ? 8'he : 8'hf) !== 8'he) $stop; // + is higher than ?
// verilator lint_on WIDTH
// surefire lint_off SEQASS
xor1 = 1'b1;
xor2 = 2'b11;
xor3 = 3'b111;
// verilator lint_off WIDTH
if (1'b1 & | (!xor3)) $stop;
// verilator lint_on WIDTH
if ({1{xor1}} != 1'b1) $stop;
if ({4{xor1}} != 4'b1111) $stop;
if (!(~xor1) !== ~(!xor1)) $stop;
if ((^xor1) !== 1'b1) $stop;
if ((^xor2) !== 1'b0) $stop;
if ((^xor3) !== 1'b1) $stop;
if (~(^xor2) !== 1'b1) $stop;
if (~(^xor3) !== 1'b0) $stop;
if ((^~xor1) !== 1'b0) $stop;
if ((^~xor2) !== 1'b1) $stop;
if ((^~xor3) !== 1'b0) $stop;
if ((~^xor1) !== 1'b0) $stop;
if ((~^xor2) !== 1'b1) $stop;
if ((~^xor3) !== 1'b0) $stop;
xor1 = 1'b0;
xor2 = 2'b10;
xor3 = 3'b101;
if ((^xor1) !== 1'b0) $stop;
if ((^xor2) !== 1'b1) $stop;
if ((^xor3) !== 1'b0) $stop;
if (~(^xor2) !== 1'b0) $stop;
if (~(^xor3) !== 1'b1) $stop;
if ((^~xor1) !== 1'b1) $stop;
if ((^~xor2) !== 1'b0) $stop;
if ((^~xor3) !== 1'b1) $stop;
if ((~^xor1) !== 1'b1) $stop;
if ((~^xor2) !== 1'b0) $stop;
if ((~^xor3) !== 1'b1) $stop;
ma = 3'h3;
mb = 3'h4;
mc = 10'h5;
mr1 = ma * mb; // Lint ASWESB: Assignment width mismatch
mr2 = 30'h5 * mc; // Lint ASWESB: Assignment width mismatch
if (mr1 !== 5'd12) $stop;
if (mr2 !== 31'd25) $stop; // Lint CWECBB: Comparison width mismatch
sh1 = 68'hf_def1_9abc_5678_1234;
shq = sh1 >> 16;
if (shq !== 68'hf_def1_9abc_5678) $stop;
shq = sh1 << 16; // Lint ASWESB: Assignment width mismatch
if (shq !== 68'h1_9abc_5678_1234_0000) $stop;
// surefire lint_on SEQASS
// Test display extraction widthing
$display("[%0t] %x %x %x(%d)", $time, shq[2:0], shq[2:0]<<2, xor3[2:0], xor3[2:0]);
// bug736
//verilator lint_off WIDTH
if ((~| 4'b0000) != 4'b0001) $stop;
if ((~| 4'b0010) != 4'b0000) $stop;
if ((~& 4'b1111) != 4'b0000) $stop;
if ((~& 4'b1101) != 4'b0001) $stop;
//verilator lint_on WIDTH
// bug764
//verilator lint_off WIDTH
// X does not sign extend
if (bug764_p11 !== 4'b000x) $stop;
if (~& bug764_p11 !== 1'b1) $stop;
//verilator lint_on WIDTH
// However IEEE says for constants in 2012 5.7.1 that smaller-sizes do extend
if (4'bx !== 4'bxxxx) $stop;
if (4'bz !== 4'bzzzz) $stop;
if (4'b1 !== 4'b0001) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
reg [63:0] m_data_pipe2_r;
reg [31:0] m_corr_data_w0, m_corr_data_w1;
reg [7:0] m_corr_data_b8;
initial begin
m_data_pipe2_r = 64'h1234_5678_9abc_def0;
{m_corr_data_b8, m_corr_data_w1, m_corr_data_w0} = { m_data_pipe2_r[63:57], 1'b0, //m_corr_data_b8 [7:0]
m_data_pipe2_r[56:26], 1'b0, //m_corr_data_w1 [31:0]
m_data_pipe2_r[25:11], 1'b0, //m_corr_data_w0 [31:16]
m_data_pipe2_r[10:04], 1'b0, //m_corr_data_w0 [15:8]
m_data_pipe2_r[03:01], 1'b0, //m_corr_data_w0 [7:4]
m_data_pipe2_r[0], 3'b000 //m_corr_data_w0 [3:0]
};
if (m_corr_data_w0 != 32'haf36de00) $stop;
if (m_corr_data_w1 != 32'h1a2b3c4c) $stop;
if (m_corr_data_b8 != 8'h12) $stop;
end
endmodule
|
/**********************************************************
-- (c) Copyright 2011 - 2014 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). A Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
//
// THIS NOTICE MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES.
//
//
// Owner: Gary Martin
// Revision: $Id: //depot/icm/proj/common/head/rtl/v32_cmt/rtl/phy/phy_4lanes.v#6 $
// $Author: gary $
// $DateTime: 2010/05/11 18:05:17 $
// $Change: 490882 $
// Description:
// This verilog file is the parameterizable 4-byte lane phy primitive top
// This module may be ganged to create an N-lane phy.
//
// History:
// Date Engineer Description
// 04/01/2010 G. Martin Initial Checkin.
//
///////////////////////////////////////////////////////////
**********************************************************/
`timescale 1ps/1ps
`define PC_DATA_OFFSET_RANGE 22:17
module mig_7series_v2_3_ddr_phy_4lanes #(
parameter GENERATE_IDELAYCTRL = "TRUE",
parameter IODELAY_GRP = "IODELAY_MIG",
parameter FPGA_SPEED_GRADE = 1,
parameter BANK_TYPE = "HP_IO", // # = "HP_IO", "HPL_IO", "HR_IO", "HRL_IO"
parameter BYTELANES_DDR_CK = 24'b0010_0010_0010_0010_0010_0010,
parameter NUM_DDR_CK = 1,
// next three parameter fields correspond to byte lanes for lane order DCBA
parameter BYTE_LANES = 4'b1111, // lane existence, one per lane
parameter DATA_CTL_N = 4'b1111, // data or control, per lane
parameter BITLANES = 48'hffff_ffff_ffff,
parameter BITLANES_OUTONLY = 48'h0000_0000_0000,
parameter LANE_REMAP = 16'h3210,// 4-bit index
// used to rewire to one of four
// input/output buss lanes
// example: 0321 remaps lanes as:
// D->A
// C->D
// B->C
// A->B
parameter LAST_BANK = "FALSE",
parameter USE_PRE_POST_FIFO = "FALSE",
parameter RCLK_SELECT_LANE = "B",
parameter real TCK = 0.00,
parameter SYNTHESIS = "FALSE",
parameter PO_CTL_COARSE_BYPASS = "FALSE",
parameter PO_FINE_DELAY = 0,
parameter PI_SEL_CLK_OFFSET = 0,
// phy_control paramter used in other paramsters
parameter PC_CLK_RATIO = 4,
//phaser_in parameters
parameter A_PI_FREQ_REF_DIV = "NONE",
parameter A_PI_CLKOUT_DIV = 2,
parameter A_PI_BURST_MODE = "TRUE",
parameter A_PI_OUTPUT_CLK_SRC = "DELAYED_REF" , //"DELAYED_REF",
parameter A_PI_FINE_DELAY = 60,
parameter A_PI_SYNC_IN_DIV_RST = "TRUE",
parameter B_PI_FREQ_REF_DIV = A_PI_FREQ_REF_DIV,
parameter B_PI_CLKOUT_DIV = A_PI_CLKOUT_DIV,
parameter B_PI_BURST_MODE = A_PI_BURST_MODE,
parameter B_PI_OUTPUT_CLK_SRC = A_PI_OUTPUT_CLK_SRC,
parameter B_PI_FINE_DELAY = A_PI_FINE_DELAY,
parameter B_PI_SYNC_IN_DIV_RST = A_PI_SYNC_IN_DIV_RST,
parameter C_PI_FREQ_REF_DIV = A_PI_FREQ_REF_DIV,
parameter C_PI_CLKOUT_DIV = A_PI_CLKOUT_DIV,
parameter C_PI_BURST_MODE = A_PI_BURST_MODE,
parameter C_PI_OUTPUT_CLK_SRC = A_PI_OUTPUT_CLK_SRC,
parameter C_PI_FINE_DELAY = 0,
parameter C_PI_SYNC_IN_DIV_RST = A_PI_SYNC_IN_DIV_RST,
parameter D_PI_FREQ_REF_DIV = A_PI_FREQ_REF_DIV,
parameter D_PI_CLKOUT_DIV = A_PI_CLKOUT_DIV,
parameter D_PI_BURST_MODE = A_PI_BURST_MODE,
parameter D_PI_OUTPUT_CLK_SRC = A_PI_OUTPUT_CLK_SRC,
parameter D_PI_FINE_DELAY = 0,
parameter D_PI_SYNC_IN_DIV_RST = A_PI_SYNC_IN_DIV_RST,
//phaser_out parameters
parameter A_PO_CLKOUT_DIV = (DATA_CTL_N[0] == 0) ? PC_CLK_RATIO : 2,
parameter A_PO_FINE_DELAY = PO_FINE_DELAY,
parameter A_PO_COARSE_DELAY = 0,
parameter A_PO_OCLK_DELAY = 0,
parameter A_PO_OCLKDELAY_INV = "FALSE",
parameter A_PO_OUTPUT_CLK_SRC = "DELAYED_REF",
parameter A_PO_SYNC_IN_DIV_RST = "TRUE",
//parameter A_PO_SYNC_IN_DIV_RST = "FALSE",
parameter B_PO_CLKOUT_DIV = (DATA_CTL_N[1] == 0) ? PC_CLK_RATIO : 2,
parameter B_PO_FINE_DELAY = PO_FINE_DELAY,
parameter B_PO_COARSE_DELAY = A_PO_COARSE_DELAY,
parameter B_PO_OCLK_DELAY = A_PO_OCLK_DELAY,
parameter B_PO_OCLKDELAY_INV = A_PO_OCLKDELAY_INV,
parameter B_PO_OUTPUT_CLK_SRC = A_PO_OUTPUT_CLK_SRC,
parameter B_PO_SYNC_IN_DIV_RST = A_PO_SYNC_IN_DIV_RST,
parameter C_PO_CLKOUT_DIV = (DATA_CTL_N[2] == 0) ? PC_CLK_RATIO : 2,
parameter C_PO_FINE_DELAY = PO_FINE_DELAY,
parameter C_PO_COARSE_DELAY = A_PO_COARSE_DELAY,
parameter C_PO_OCLK_DELAY = A_PO_OCLK_DELAY,
parameter C_PO_OCLKDELAY_INV = A_PO_OCLKDELAY_INV,
parameter C_PO_OUTPUT_CLK_SRC = A_PO_OUTPUT_CLK_SRC,
parameter C_PO_SYNC_IN_DIV_RST = A_PO_SYNC_IN_DIV_RST,
parameter D_PO_CLKOUT_DIV = (DATA_CTL_N[3] == 0) ? PC_CLK_RATIO : 2,
parameter D_PO_FINE_DELAY = PO_FINE_DELAY,
parameter D_PO_COARSE_DELAY = A_PO_COARSE_DELAY,
parameter D_PO_OCLK_DELAY = A_PO_OCLK_DELAY,
parameter D_PO_OCLKDELAY_INV = A_PO_OCLKDELAY_INV,
parameter D_PO_OUTPUT_CLK_SRC = A_PO_OUTPUT_CLK_SRC,
parameter D_PO_SYNC_IN_DIV_RST = A_PO_SYNC_IN_DIV_RST,
parameter A_IDELAYE2_IDELAY_TYPE = "VARIABLE",
parameter A_IDELAYE2_IDELAY_VALUE = 00,
parameter B_IDELAYE2_IDELAY_TYPE = A_IDELAYE2_IDELAY_TYPE,
parameter B_IDELAYE2_IDELAY_VALUE = A_IDELAYE2_IDELAY_VALUE,
parameter C_IDELAYE2_IDELAY_TYPE = A_IDELAYE2_IDELAY_TYPE,
parameter C_IDELAYE2_IDELAY_VALUE = A_IDELAYE2_IDELAY_VALUE,
parameter D_IDELAYE2_IDELAY_TYPE = A_IDELAYE2_IDELAY_TYPE,
parameter D_IDELAYE2_IDELAY_VALUE = A_IDELAYE2_IDELAY_VALUE,
// phy_control parameters
parameter PC_BURST_MODE = "TRUE",
parameter PC_DATA_CTL_N = DATA_CTL_N,
parameter PC_CMD_OFFSET = 0,
parameter PC_RD_CMD_OFFSET_0 = 0,
parameter PC_RD_CMD_OFFSET_1 = 0,
parameter PC_RD_CMD_OFFSET_2 = 0,
parameter PC_RD_CMD_OFFSET_3 = 0,
parameter PC_CO_DURATION = 1,
parameter PC_DI_DURATION = 1,
parameter PC_DO_DURATION = 1,
parameter PC_RD_DURATION_0 = 0,
parameter PC_RD_DURATION_1 = 0,
parameter PC_RD_DURATION_2 = 0,
parameter PC_RD_DURATION_3 = 0,
parameter PC_WR_CMD_OFFSET_0 = 5,
parameter PC_WR_CMD_OFFSET_1 = 5,
parameter PC_WR_CMD_OFFSET_2 = 5,
parameter PC_WR_CMD_OFFSET_3 = 5,
parameter PC_WR_DURATION_0 = 6,
parameter PC_WR_DURATION_1 = 6,
parameter PC_WR_DURATION_2 = 6,
parameter PC_WR_DURATION_3 = 6,
parameter PC_AO_WRLVL_EN = 0,
parameter PC_AO_TOGGLE = 4'b0101, // odd bits are toggle (CKE)
parameter PC_FOUR_WINDOW_CLOCKS = 63,
parameter PC_EVENTS_DELAY = 18,
parameter PC_PHY_COUNT_EN = "TRUE",
parameter PC_SYNC_MODE = "TRUE",
parameter PC_DISABLE_SEQ_MATCH = "TRUE",
parameter PC_MULTI_REGION = "FALSE",
// io fifo parameters
parameter A_OF_ARRAY_MODE = (DATA_CTL_N[0] == 1) ? "ARRAY_MODE_8_X_4" : "ARRAY_MODE_4_X_4",
parameter B_OF_ARRAY_MODE = (DATA_CTL_N[1] == 1) ? "ARRAY_MODE_8_X_4" : "ARRAY_MODE_4_X_4",
parameter C_OF_ARRAY_MODE = (DATA_CTL_N[2] == 1) ? "ARRAY_MODE_8_X_4" : "ARRAY_MODE_4_X_4",
parameter D_OF_ARRAY_MODE = (DATA_CTL_N[3] == 1) ? "ARRAY_MODE_8_X_4" : "ARRAY_MODE_4_X_4",
parameter OF_ALMOST_EMPTY_VALUE = 1,
parameter OF_ALMOST_FULL_VALUE = 1,
parameter OF_OUTPUT_DISABLE = "TRUE",
parameter OF_SYNCHRONOUS_MODE = PC_SYNC_MODE,
parameter A_OS_DATA_RATE = "DDR",
parameter A_OS_DATA_WIDTH = 4,
parameter B_OS_DATA_RATE = A_OS_DATA_RATE,
parameter B_OS_DATA_WIDTH = A_OS_DATA_WIDTH,
parameter C_OS_DATA_RATE = A_OS_DATA_RATE,
parameter C_OS_DATA_WIDTH = A_OS_DATA_WIDTH,
parameter D_OS_DATA_RATE = A_OS_DATA_RATE,
parameter D_OS_DATA_WIDTH = A_OS_DATA_WIDTH,
parameter A_IF_ARRAY_MODE = "ARRAY_MODE_4_X_8",
parameter B_IF_ARRAY_MODE = A_IF_ARRAY_MODE,
parameter C_IF_ARRAY_MODE = A_IF_ARRAY_MODE,
parameter D_IF_ARRAY_MODE = A_IF_ARRAY_MODE,
parameter IF_ALMOST_EMPTY_VALUE = 1,
parameter IF_ALMOST_FULL_VALUE = 1,
parameter IF_SYNCHRONOUS_MODE = PC_SYNC_MODE,
// this is used locally, not for external pushdown
// NOTE: the 0+ is needed in each to coerce to integer for addition.
// otherwise 4x 1'b values are added producing a 1'b value.
parameter HIGHEST_LANE = LAST_BANK == "FALSE" ? 4 : (BYTE_LANES[3] ? 4 : BYTE_LANES[2] ? 3 : BYTE_LANES[1] ? 2 : 1),
parameter N_CTL_LANES = ((0+(!DATA_CTL_N[0]) & BYTE_LANES[0]) + (0+(!DATA_CTL_N[1]) & BYTE_LANES[1]) + (0+(!DATA_CTL_N[2]) & BYTE_LANES[2]) + (0+(!DATA_CTL_N[3]) & BYTE_LANES[3])),
parameter N_BYTE_LANES = (0+BYTE_LANES[0]) + (0+BYTE_LANES[1]) + (0+BYTE_LANES[2]) + (0+BYTE_LANES[3]),
parameter N_DATA_LANES = N_BYTE_LANES - N_CTL_LANES,
// assume odt per rank + any declared cke's
parameter AUXOUT_WIDTH = 4,
parameter LP_DDR_CK_WIDTH = 2
,parameter CKE_ODT_AUX = "FALSE"
)
(
//`include "phy.vh"
input rst,
input phy_clk,
input phy_ctl_clk,
input freq_refclk,
input mem_refclk,
input mem_refclk_div4,
input pll_lock,
input sync_pulse,
input idelayctrl_refclk,
input [HIGHEST_LANE*80-1:0] phy_dout,
input phy_cmd_wr_en,
input phy_data_wr_en,
input phy_rd_en,
input phy_ctl_mstr_empty,
input [31:0] phy_ctl_wd,
input [`PC_DATA_OFFSET_RANGE] data_offset,
input phy_ctl_wr,
input if_empty_def,
input phyGo,
input input_sink,
output [(LP_DDR_CK_WIDTH*24)-1:0] ddr_clk, // to memory
output rclk,
output if_a_empty,
output if_empty,
output byte_rd_en,
output if_empty_or,
output if_empty_and,
output of_ctl_a_full,
output of_data_a_full,
output of_ctl_full,
output of_data_full,
output pre_data_a_full,
output [HIGHEST_LANE*80-1:0]phy_din, // assume input bus same size as output bus
output phy_ctl_empty,
output phy_ctl_a_full,
output phy_ctl_full,
output [HIGHEST_LANE*12-1:0]mem_dq_out,
output [HIGHEST_LANE*12-1:0]mem_dq_ts,
input [HIGHEST_LANE*10-1:0]mem_dq_in,
output [HIGHEST_LANE-1:0] mem_dqs_out,
output [HIGHEST_LANE-1:0] mem_dqs_ts,
input [HIGHEST_LANE-1:0] mem_dqs_in,
input [1:0] byte_rd_en_oth_banks,
output [AUXOUT_WIDTH-1:0] aux_out,
output reg rst_out = 0,
output reg mcGo=0,
output phy_ctl_ready,
output ref_dll_lock,
input if_rst,
input phy_read_calib,
input phy_write_calib,
input idelay_inc,
input idelay_ce,
input idelay_ld,
input [2:0] calib_sel,
input calib_zero_ctrl,
input [HIGHEST_LANE-1:0] calib_zero_lanes,
input calib_in_common,
input po_fine_enable,
input po_coarse_enable,
input po_fine_inc,
input po_coarse_inc,
input po_counter_load_en,
input po_counter_read_en,
input [8:0] po_counter_load_val,
input po_sel_fine_oclk_delay,
output reg po_coarse_overflow,
output reg po_fine_overflow,
output reg [8:0] po_counter_read_val,
input pi_rst_dqs_find,
input pi_fine_enable,
input pi_fine_inc,
input pi_counter_load_en,
input pi_counter_read_en,
input [5:0] pi_counter_load_val,
output reg pi_fine_overflow,
output reg [5:0] pi_counter_read_val,
output reg pi_dqs_found,
output pi_dqs_found_all,
output pi_dqs_found_any,
output [HIGHEST_LANE-1:0] pi_phase_locked_lanes,
output [HIGHEST_LANE-1:0] pi_dqs_found_lanes,
output reg pi_dqs_out_of_range,
output reg pi_phase_locked,
output pi_phase_locked_all,
input [29:0] fine_delay,
input fine_delay_sel
);
localparam DATA_CTL_A = (~DATA_CTL_N[0]);
localparam DATA_CTL_B = (~DATA_CTL_N[1]);
localparam DATA_CTL_C = (~DATA_CTL_N[2]);
localparam DATA_CTL_D = (~DATA_CTL_N[3]);
localparam PRESENT_CTL_A = BYTE_LANES[0] && ! DATA_CTL_N[0];
localparam PRESENT_CTL_B = BYTE_LANES[1] && ! DATA_CTL_N[1];
localparam PRESENT_CTL_C = BYTE_LANES[2] && ! DATA_CTL_N[2];
localparam PRESENT_CTL_D = BYTE_LANES[3] && ! DATA_CTL_N[3];
localparam PRESENT_DATA_A = BYTE_LANES[0] && DATA_CTL_N[0];
localparam PRESENT_DATA_B = BYTE_LANES[1] && DATA_CTL_N[1];
localparam PRESENT_DATA_C = BYTE_LANES[2] && DATA_CTL_N[2];
localparam PRESENT_DATA_D = BYTE_LANES[3] && DATA_CTL_N[3];
localparam PC_DATA_CTL_A = (DATA_CTL_A) ? "FALSE" : "TRUE";
localparam PC_DATA_CTL_B = (DATA_CTL_B) ? "FALSE" : "TRUE";
localparam PC_DATA_CTL_C = (DATA_CTL_C) ? "FALSE" : "TRUE";
localparam PC_DATA_CTL_D = (DATA_CTL_D) ? "FALSE" : "TRUE";
localparam A_PO_COARSE_BYPASS = (DATA_CTL_A) ? PO_CTL_COARSE_BYPASS : "FALSE";
localparam B_PO_COARSE_BYPASS = (DATA_CTL_B) ? PO_CTL_COARSE_BYPASS : "FALSE";
localparam C_PO_COARSE_BYPASS = (DATA_CTL_C) ? PO_CTL_COARSE_BYPASS : "FALSE";
localparam D_PO_COARSE_BYPASS = (DATA_CTL_D) ? PO_CTL_COARSE_BYPASS : "FALSE";
localparam IO_A_START = 41;
localparam IO_A_END = 40;
localparam IO_B_START = 43;
localparam IO_B_END = 42;
localparam IO_C_START = 45;
localparam IO_C_END = 44;
localparam IO_D_START = 47;
localparam IO_D_END = 46;
localparam IO_A_X_START = (HIGHEST_LANE * 10) + 1;
localparam IO_A_X_END = (IO_A_X_START-1);
localparam IO_B_X_START = (IO_A_X_START + 2);
localparam IO_B_X_END = (IO_B_X_START -1);
localparam IO_C_X_START = (IO_B_X_START + 2);
localparam IO_C_X_END = (IO_C_X_START -1);
localparam IO_D_X_START = (IO_C_X_START + 2);
localparam IO_D_X_END = (IO_D_X_START -1);
localparam MSB_BURST_PEND_PO = 3;
localparam MSB_BURST_PEND_PI = 7;
localparam MSB_RANK_SEL_I = MSB_BURST_PEND_PI + 8;
localparam PHASER_CTL_BUS_WIDTH = MSB_RANK_SEL_I + 1;
wire [1:0] oserdes_dqs;
wire [1:0] oserdes_dqs_ts;
wire [1:0] oserdes_dq_ts;
wire [PHASER_CTL_BUS_WIDTH-1:0] phaser_ctl_bus;
wire [7:0] in_rank;
wire [11:0] IO_A;
wire [11:0] IO_B;
wire [11:0] IO_C;
wire [11:0] IO_D;
wire [319:0] phy_din_remap;
reg A_po_counter_read_en;
wire [8:0] A_po_counter_read_val;
reg A_pi_counter_read_en;
wire [5:0] A_pi_counter_read_val;
wire A_pi_fine_overflow;
wire A_po_coarse_overflow;
wire A_po_fine_overflow;
wire A_pi_dqs_found;
wire A_pi_dqs_out_of_range;
wire A_pi_phase_locked;
wire A_pi_iserdes_rst;
reg A_pi_fine_enable;
reg A_pi_fine_inc;
reg A_pi_counter_load_en;
reg [5:0] A_pi_counter_load_val;
reg A_pi_rst_dqs_find;
reg A_po_fine_enable;
reg A_po_coarse_enable;
reg A_po_fine_inc /* synthesis syn_maxfan = 3 */;
reg A_po_sel_fine_oclk_delay;
reg A_po_coarse_inc;
reg A_po_counter_load_en;
reg [8:0] A_po_counter_load_val;
wire A_rclk;
reg A_idelay_ce;
reg A_idelay_ld;
reg [29:0] A_fine_delay;
reg A_fine_delay_sel;
reg B_po_counter_read_en;
wire [8:0] B_po_counter_read_val;
reg B_pi_counter_read_en;
wire [5:0] B_pi_counter_read_val;
wire B_pi_fine_overflow;
wire B_po_coarse_overflow;
wire B_po_fine_overflow;
wire B_pi_phase_locked;
wire B_pi_iserdes_rst;
wire B_pi_dqs_found;
wire B_pi_dqs_out_of_range;
reg B_pi_fine_enable;
reg B_pi_fine_inc;
reg B_pi_counter_load_en;
reg [5:0] B_pi_counter_load_val;
reg B_pi_rst_dqs_find;
reg B_po_fine_enable;
reg B_po_coarse_enable;
reg B_po_fine_inc /* synthesis syn_maxfan = 3 */;
reg B_po_coarse_inc;
reg B_po_sel_fine_oclk_delay;
reg B_po_counter_load_en;
reg [8:0] B_po_counter_load_val;
wire B_rclk;
reg B_idelay_ce;
reg B_idelay_ld;
reg [29:0] B_fine_delay;
reg B_fine_delay_sel;
reg C_pi_fine_inc;
reg D_pi_fine_inc;
reg C_pi_fine_enable;
reg D_pi_fine_enable;
reg C_po_counter_load_en;
reg D_po_counter_load_en;
reg C_po_coarse_inc;
reg D_po_coarse_inc;
reg C_po_fine_inc /* synthesis syn_maxfan = 3 */;
reg D_po_fine_inc /* synthesis syn_maxfan = 3 */;
reg C_po_sel_fine_oclk_delay;
reg D_po_sel_fine_oclk_delay;
reg [5:0] C_pi_counter_load_val;
reg [5:0] D_pi_counter_load_val;
reg [8:0] C_po_counter_load_val;
reg [8:0] D_po_counter_load_val;
reg C_po_coarse_enable;
reg D_po_coarse_enable;
reg C_po_fine_enable;
reg D_po_fine_enable;
wire C_po_coarse_overflow;
wire D_po_coarse_overflow;
wire C_po_fine_overflow;
wire D_po_fine_overflow;
wire [8:0] C_po_counter_read_val;
wire [8:0] D_po_counter_read_val;
reg C_po_counter_read_en;
reg D_po_counter_read_en;
wire C_pi_dqs_found;
wire D_pi_dqs_found;
wire C_pi_fine_overflow;
wire D_pi_fine_overflow;
reg C_pi_counter_read_en;
reg D_pi_counter_read_en;
reg C_pi_counter_load_en;
reg D_pi_counter_load_en;
wire C_pi_phase_locked;
wire C_pi_iserdes_rst;
wire D_pi_phase_locked;
wire D_pi_iserdes_rst;
wire C_pi_dqs_out_of_range;
wire D_pi_dqs_out_of_range;
wire [5:0] C_pi_counter_read_val;
wire [5:0] D_pi_counter_read_val;
wire C_rclk;
wire D_rclk;
reg C_idelay_ce;
reg D_idelay_ce;
reg C_idelay_ld;
reg D_idelay_ld;
reg C_pi_rst_dqs_find;
reg D_pi_rst_dqs_find;
reg [29:0] C_fine_delay;
reg [29:0] D_fine_delay;
reg C_fine_delay_sel;
reg D_fine_delay_sel;
wire pi_iserdes_rst;
wire A_if_empty;
wire B_if_empty;
wire C_if_empty;
wire D_if_empty;
wire A_byte_rd_en;
wire B_byte_rd_en;
wire C_byte_rd_en;
wire D_byte_rd_en;
wire A_if_a_empty;
wire B_if_a_empty;
wire C_if_a_empty;
wire D_if_a_empty;
//wire A_if_full;
//wire B_if_full;
//wire C_if_full;
//wire D_if_full;
//wire A_of_empty;
//wire B_of_empty;
//wire C_of_empty;
//wire D_of_empty;
wire A_of_full;
wire B_of_full;
wire C_of_full;
wire D_of_full;
wire A_of_ctl_full;
wire B_of_ctl_full;
wire C_of_ctl_full;
wire D_of_ctl_full;
wire A_of_data_full;
wire B_of_data_full;
wire C_of_data_full;
wire D_of_data_full;
wire A_of_a_full;
wire B_of_a_full;
wire C_of_a_full;
wire D_of_a_full;
wire A_pre_fifo_a_full;
wire B_pre_fifo_a_full;
wire C_pre_fifo_a_full;
wire D_pre_fifo_a_full;
wire A_of_ctl_a_full;
wire B_of_ctl_a_full;
wire C_of_ctl_a_full;
wire D_of_ctl_a_full;
wire A_of_data_a_full;
wire B_of_data_a_full;
wire C_of_data_a_full;
wire D_of_data_a_full;
wire A_pre_data_a_full;
wire B_pre_data_a_full;
wire C_pre_data_a_full;
wire D_pre_data_a_full;
wire [LP_DDR_CK_WIDTH*6-1:0] A_ddr_clk; // for generation
wire [LP_DDR_CK_WIDTH*6-1:0] B_ddr_clk; //
wire [LP_DDR_CK_WIDTH*6-1:0] C_ddr_clk; //
wire [LP_DDR_CK_WIDTH*6-1:0] D_ddr_clk; //
wire [3:0] dummy_data;
wire [31:0] _phy_ctl_wd;
wire [1:0] phy_encalib;
assign pi_dqs_found_all =
(! PRESENT_DATA_A | A_pi_dqs_found) &
(! PRESENT_DATA_B | B_pi_dqs_found) &
(! PRESENT_DATA_C | C_pi_dqs_found) &
(! PRESENT_DATA_D | D_pi_dqs_found) ;
assign pi_dqs_found_any =
( PRESENT_DATA_A & A_pi_dqs_found) |
( PRESENT_DATA_B & B_pi_dqs_found) |
( PRESENT_DATA_C & C_pi_dqs_found) |
( PRESENT_DATA_D & D_pi_dqs_found) ;
assign pi_phase_locked_all =
(! PRESENT_DATA_A | A_pi_phase_locked) &
(! PRESENT_DATA_B | B_pi_phase_locked) &
(! PRESENT_DATA_C | C_pi_phase_locked) &
(! PRESENT_DATA_D | D_pi_phase_locked);
wire dangling_inputs = (& dummy_data) & input_sink & 1'b0; // this reduces all constant 0 values to 1 signal
// which is combined into another signals such that
// the other signal isn't changed. The purpose
// is to fake the tools into ignoring dangling inputs.
// Because it is anded with 1'b0, the contributing signals
// are folded as constants or trimmed.
assign if_empty = !if_empty_def ? (A_if_empty | B_if_empty | C_if_empty | D_if_empty) : (A_if_empty & B_if_empty & C_if_empty & D_if_empty);
assign byte_rd_en = !if_empty_def ? (A_byte_rd_en & B_byte_rd_en & C_byte_rd_en & D_byte_rd_en) :
(A_byte_rd_en | B_byte_rd_en | C_byte_rd_en | D_byte_rd_en);
assign if_empty_or = (A_if_empty | B_if_empty | C_if_empty | D_if_empty);
assign if_empty_and = (A_if_empty & B_if_empty & C_if_empty & D_if_empty);
assign if_a_empty = A_if_a_empty | B_if_a_empty | C_if_a_empty | D_if_a_empty;
//assign if_full = A_if_full | B_if_full | C_if_full | D_if_full ;
//assign of_empty = A_of_empty & B_of_empty & C_of_empty & D_of_empty;
assign of_ctl_full = A_of_ctl_full | B_of_ctl_full | C_of_ctl_full | D_of_ctl_full ;
assign of_data_full = A_of_data_full | B_of_data_full | C_of_data_full | D_of_data_full ;
assign of_ctl_a_full = A_of_ctl_a_full | B_of_ctl_a_full | C_of_ctl_a_full | D_of_ctl_a_full ;
assign of_data_a_full = A_of_data_a_full | B_of_data_a_full | C_of_data_a_full | D_of_data_a_full | dangling_inputs ;
assign pre_data_a_full = A_pre_data_a_full | B_pre_data_a_full | C_pre_data_a_full | D_pre_data_a_full;
function [79:0] part_select_80;
input [319:0] vector;
input [1:0] select;
begin
case (select)
2'b00 : part_select_80[79:0] = vector[1*80-1:0*80];
2'b01 : part_select_80[79:0] = vector[2*80-1:1*80];
2'b10 : part_select_80[79:0] = vector[3*80-1:2*80];
2'b11 : part_select_80[79:0] = vector[4*80-1:3*80];
endcase
end
endfunction
wire [319:0] phy_dout_remap;
reg rst_out_trig = 1'b0;
reg [31:0] rclk_delay;
reg rst_edge1 = 1'b0;
reg rst_edge2 = 1'b0;
reg rst_edge3 = 1'b0;
reg rst_edge_detect = 1'b0;
wire rclk_;
reg rst_out_start = 1'b0 ;
reg rst_primitives=0;
reg A_rst_primitives=0;
reg B_rst_primitives=0;
reg C_rst_primitives=0;
reg D_rst_primitives=0;
`ifdef USE_PHY_CONTROL_TEST
wire [15:0] test_output;
wire [15:0] test_input;
wire [2:0] test_select=0;
wire scan_enable = 0;
`endif
generate
genvar i;
if (RCLK_SELECT_LANE == "A") begin
assign rclk_ = A_rclk;
assign pi_iserdes_rst = A_pi_iserdes_rst;
end
else if (RCLK_SELECT_LANE == "B") begin
assign rclk_ = B_rclk;
assign pi_iserdes_rst = B_pi_iserdes_rst;
end
else if (RCLK_SELECT_LANE == "C") begin
assign rclk_ = C_rclk;
assign pi_iserdes_rst = C_pi_iserdes_rst;
end
else if (RCLK_SELECT_LANE == "D") begin
assign rclk_ = D_rclk;
assign pi_iserdes_rst = D_pi_iserdes_rst;
end
else begin
assign rclk_ = B_rclk; // default
end
endgenerate
assign ddr_clk[LP_DDR_CK_WIDTH*6-1:0] = A_ddr_clk;
assign ddr_clk[LP_DDR_CK_WIDTH*12-1:LP_DDR_CK_WIDTH*6] = B_ddr_clk;
assign ddr_clk[LP_DDR_CK_WIDTH*18-1:LP_DDR_CK_WIDTH*12] = C_ddr_clk;
assign ddr_clk[LP_DDR_CK_WIDTH*24-1:LP_DDR_CK_WIDTH*18] = D_ddr_clk;
assign pi_phase_locked_lanes =
{(! PRESENT_DATA_A[0] | A_pi_phase_locked),
(! PRESENT_DATA_B[0] | B_pi_phase_locked) ,
(! PRESENT_DATA_C[0] | C_pi_phase_locked) ,
(! PRESENT_DATA_D[0] | D_pi_phase_locked)};
assign pi_dqs_found_lanes = {D_pi_dqs_found, C_pi_dqs_found, B_pi_dqs_found, A_pi_dqs_found};
// this block scrubs X from rclk_delay[11]
reg rclk_delay_11;
always @(rclk_delay[11]) begin : rclk_delay_11_blk
if ( rclk_delay[11])
rclk_delay_11 = 1;
else
rclk_delay_11 = 0;
end
always @(posedge phy_clk or posedge rst ) begin
// scrub 4-state values from rclk_delay[11]
if ( rst) begin
rst_out <= #1 0;
end
else begin
if ( rclk_delay_11)
rst_out <= #1 1;
end
end
always @(posedge phy_clk ) begin
// phy_ctl_ready drives reset of the system
rst_primitives <= !phy_ctl_ready ;
A_rst_primitives <= rst_primitives ;
B_rst_primitives <= rst_primitives ;
C_rst_primitives <= rst_primitives ;
D_rst_primitives <= rst_primitives ;
rclk_delay <= #1 (rclk_delay << 1) | (!rst_primitives && phyGo);
mcGo <= #1 rst_out ;
end
generate
if (BYTE_LANES[0]) begin
assign dummy_data[0] = 0;
end
else begin
assign dummy_data[0] = &phy_dout_remap[1*80-1:0*80];
end
if (BYTE_LANES[1]) begin
assign dummy_data[1] = 0;
end
else begin
assign dummy_data[1] = &phy_dout_remap[2*80-1:1*80];
end
if (BYTE_LANES[2]) begin
assign dummy_data[2] = 0;
end
else begin
assign dummy_data[2] = &phy_dout_remap[3*80-1:2*80];
end
if (BYTE_LANES[3]) begin
assign dummy_data[3] = 0;
end
else begin
assign dummy_data[3] = &phy_dout_remap[4*80-1:3*80];
end
if (PRESENT_DATA_A) begin
assign A_of_data_full = A_of_full;
assign A_of_ctl_full = 0;
assign A_of_data_a_full = A_of_a_full;
assign A_of_ctl_a_full = 0;
assign A_pre_data_a_full = A_pre_fifo_a_full;
end
else begin
assign A_of_ctl_full = A_of_full;
assign A_of_data_full = 0;
assign A_of_ctl_a_full = A_of_a_full;
assign A_of_data_a_full = 0;
assign A_pre_data_a_full = 0;
end
if (PRESENT_DATA_B) begin
assign B_of_data_full = B_of_full;
assign B_of_ctl_full = 0;
assign B_of_data_a_full = B_of_a_full;
assign B_of_ctl_a_full = 0;
assign B_pre_data_a_full = B_pre_fifo_a_full;
end
else begin
assign B_of_ctl_full = B_of_full;
assign B_of_data_full = 0;
assign B_of_ctl_a_full = B_of_a_full;
assign B_of_data_a_full = 0;
assign B_pre_data_a_full = 0;
end
if (PRESENT_DATA_C) begin
assign C_of_data_full = C_of_full;
assign C_of_ctl_full = 0;
assign C_of_data_a_full = C_of_a_full;
assign C_of_ctl_a_full = 0;
assign C_pre_data_a_full = C_pre_fifo_a_full;
end
else begin
assign C_of_ctl_full = C_of_full;
assign C_of_data_full = 0;
assign C_of_ctl_a_full = C_of_a_full;
assign C_of_data_a_full = 0;
assign C_pre_data_a_full = 0;
end
if (PRESENT_DATA_D) begin
assign D_of_data_full = D_of_full;
assign D_of_ctl_full = 0;
assign D_of_data_a_full = D_of_a_full;
assign D_of_ctl_a_full = 0;
assign D_pre_data_a_full = D_pre_fifo_a_full;
end
else begin
assign D_of_ctl_full = D_of_full;
assign D_of_data_full = 0;
assign D_of_ctl_a_full = D_of_a_full;
assign D_of_data_a_full = 0;
assign D_pre_data_a_full = 0;
end
// byte lane must exist and be data lane.
if (PRESENT_DATA_A )
case ( LANE_REMAP[1:0] )
2'b00 : assign phy_din[1*80-1:0] = phy_din_remap[79:0];
2'b01 : assign phy_din[2*80-1:80] = phy_din_remap[79:0];
2'b10 : assign phy_din[3*80-1:160] = phy_din_remap[79:0];
2'b11 : assign phy_din[4*80-1:240] = phy_din_remap[79:0];
endcase
else
case ( LANE_REMAP[1:0] )
2'b00 : assign phy_din[1*80-1:0] = 80'h0;
2'b01 : assign phy_din[2*80-1:80] = 80'h0;
2'b10 : assign phy_din[3*80-1:160] = 80'h0;
2'b11 : assign phy_din[4*80-1:240] = 80'h0;
endcase
if (PRESENT_DATA_B )
case ( LANE_REMAP[5:4] )
2'b00 : assign phy_din[1*80-1:0] = phy_din_remap[159:80];
2'b01 : assign phy_din[2*80-1:80] = phy_din_remap[159:80];
2'b10 : assign phy_din[3*80-1:160] = phy_din_remap[159:80];
2'b11 : assign phy_din[4*80-1:240] = phy_din_remap[159:80];
endcase
else
if (HIGHEST_LANE > 1)
case ( LANE_REMAP[5:4] )
2'b00 : assign phy_din[1*80-1:0] = 80'h0;
2'b01 : assign phy_din[2*80-1:80] = 80'h0;
2'b10 : assign phy_din[3*80-1:160] = 80'h0;
2'b11 : assign phy_din[4*80-1:240] = 80'h0;
endcase
if (PRESENT_DATA_C)
case ( LANE_REMAP[9:8] )
2'b00 : assign phy_din[1*80-1:0] = phy_din_remap[239:160];
2'b01 : assign phy_din[2*80-1:80] = phy_din_remap[239:160];
2'b10 : assign phy_din[3*80-1:160] = phy_din_remap[239:160];
2'b11 : assign phy_din[4*80-1:240] = phy_din_remap[239:160];
endcase
else
if (HIGHEST_LANE > 2)
case ( LANE_REMAP[9:8] )
2'b00 : assign phy_din[1*80-1:0] = 80'h0;
2'b01 : assign phy_din[2*80-1:80] = 80'h0;
2'b10 : assign phy_din[3*80-1:160] = 80'h0;
2'b11 : assign phy_din[4*80-1:240] = 80'h0;
endcase
if (PRESENT_DATA_D )
case ( LANE_REMAP[13:12] )
2'b00 : assign phy_din[1*80-1:0] = phy_din_remap[319:240];
2'b01 : assign phy_din[2*80-1:80] = phy_din_remap[319:240];
2'b10 : assign phy_din[3*80-1:160] = phy_din_remap[319:240];
2'b11 : assign phy_din[4*80-1:240] = phy_din_remap[319:240];
endcase
else
if (HIGHEST_LANE > 3)
case ( LANE_REMAP[13:12] )
2'b00 : assign phy_din[1*80-1:0] = 80'h0;
2'b01 : assign phy_din[2*80-1:80] = 80'h0;
2'b10 : assign phy_din[3*80-1:160] = 80'h0;
2'b11 : assign phy_din[4*80-1:240] = 80'h0;
endcase
if (HIGHEST_LANE > 1)
assign _phy_ctl_wd = {phy_ctl_wd[31:23], data_offset, phy_ctl_wd[16:0]};
if (HIGHEST_LANE == 1)
assign _phy_ctl_wd = phy_ctl_wd;
//BUFR #(.BUFR_DIVIDE ("1")) rclk_buf(.I(rclk_), .O(rclk), .CE (1'b1), .CLR (pi_iserdes_rst));
BUFIO rclk_buf(.I(rclk_), .O(rclk) );
if ( BYTE_LANES[0] ) begin : ddr_byte_lane_A
assign phy_dout_remap[79:0] = part_select_80(phy_dout, (LANE_REMAP[1:0]));
mig_7series_v2_3_ddr_byte_lane #
(
.ABCD ("A"),
.PO_DATA_CTL (PC_DATA_CTL_N[0] ? "TRUE" : "FALSE"),
.BITLANES (BITLANES[11:0]),
.BITLANES_OUTONLY (BITLANES_OUTONLY[11:0]),
.OF_ALMOST_EMPTY_VALUE (OF_ALMOST_EMPTY_VALUE),
.OF_ALMOST_FULL_VALUE (OF_ALMOST_FULL_VALUE),
.OF_SYNCHRONOUS_MODE (OF_SYNCHRONOUS_MODE),
//.OF_OUTPUT_DISABLE (OF_OUTPUT_DISABLE),
//.OF_ARRAY_MODE (A_OF_ARRAY_MODE),
//.IF_ARRAY_MODE (IF_ARRAY_MODE),
.IF_ALMOST_EMPTY_VALUE (IF_ALMOST_EMPTY_VALUE),
.IF_ALMOST_FULL_VALUE (IF_ALMOST_FULL_VALUE),
.IF_SYNCHRONOUS_MODE (IF_SYNCHRONOUS_MODE),
.IODELAY_GRP (IODELAY_GRP),
.FPGA_SPEED_GRADE (FPGA_SPEED_GRADE),
.BANK_TYPE (BANK_TYPE),
.BYTELANES_DDR_CK (BYTELANES_DDR_CK),
.RCLK_SELECT_LANE (RCLK_SELECT_LANE),
.USE_PRE_POST_FIFO (USE_PRE_POST_FIFO),
.SYNTHESIS (SYNTHESIS),
.TCK (TCK),
.PC_CLK_RATIO (PC_CLK_RATIO),
.PI_BURST_MODE (A_PI_BURST_MODE),
.PI_CLKOUT_DIV (A_PI_CLKOUT_DIV),
.PI_FREQ_REF_DIV (A_PI_FREQ_REF_DIV),
.PI_FINE_DELAY (A_PI_FINE_DELAY),
.PI_OUTPUT_CLK_SRC (A_PI_OUTPUT_CLK_SRC),
.PI_SYNC_IN_DIV_RST (A_PI_SYNC_IN_DIV_RST),
.PI_SEL_CLK_OFFSET (PI_SEL_CLK_OFFSET),
.PO_CLKOUT_DIV (A_PO_CLKOUT_DIV),
.PO_FINE_DELAY (A_PO_FINE_DELAY),
.PO_COARSE_BYPASS (A_PO_COARSE_BYPASS),
.PO_COARSE_DELAY (A_PO_COARSE_DELAY),
.PO_OCLK_DELAY (A_PO_OCLK_DELAY),
.PO_OCLKDELAY_INV (A_PO_OCLKDELAY_INV),
.PO_OUTPUT_CLK_SRC (A_PO_OUTPUT_CLK_SRC),
.PO_SYNC_IN_DIV_RST (A_PO_SYNC_IN_DIV_RST),
.OSERDES_DATA_RATE (A_OS_DATA_RATE),
.OSERDES_DATA_WIDTH (A_OS_DATA_WIDTH),
.IDELAYE2_IDELAY_TYPE (A_IDELAYE2_IDELAY_TYPE),
.IDELAYE2_IDELAY_VALUE (A_IDELAYE2_IDELAY_VALUE)
,.CKE_ODT_AUX (CKE_ODT_AUX)
)
ddr_byte_lane_A(
.mem_dq_out (mem_dq_out[11:0]),
.mem_dq_ts (mem_dq_ts[11:0]),
.mem_dq_in (mem_dq_in[9:0]),
.mem_dqs_out (mem_dqs_out[0]),
.mem_dqs_ts (mem_dqs_ts[0]),
.mem_dqs_in (mem_dqs_in[0]),
.rst (A_rst_primitives),
.phy_clk (phy_clk),
.freq_refclk (freq_refclk),
.mem_refclk (mem_refclk),
.idelayctrl_refclk (idelayctrl_refclk),
.sync_pulse (sync_pulse),
.ddr_ck_out (A_ddr_clk),
.rclk (A_rclk),
.pi_dqs_found (A_pi_dqs_found),
.dqs_out_of_range (A_pi_dqs_out_of_range),
.if_empty_def (if_empty_def),
.if_a_empty (A_if_a_empty),
.if_empty (A_if_empty),
.if_a_full (/*if_a_full*/),
.if_full (/*A_if_full*/),
.of_a_empty (/*of_a_empty*/),
.of_empty (/*A_of_empty*/),
.of_a_full (A_of_a_full),
.of_full (A_of_full),
.pre_fifo_a_full (A_pre_fifo_a_full),
.phy_din (phy_din_remap[79:0]),
.phy_dout (phy_dout_remap[79:0]),
.phy_cmd_wr_en (phy_cmd_wr_en),
.phy_data_wr_en (phy_data_wr_en),
.phy_rd_en (phy_rd_en),
.phaser_ctl_bus (phaser_ctl_bus),
.if_rst (if_rst),
.byte_rd_en_oth_lanes ({B_byte_rd_en,C_byte_rd_en,D_byte_rd_en}),
.byte_rd_en_oth_banks (byte_rd_en_oth_banks),
.byte_rd_en (A_byte_rd_en),
// calibration signals
.idelay_inc (idelay_inc),
.idelay_ce (A_idelay_ce),
.idelay_ld (A_idelay_ld),
.pi_rst_dqs_find (A_pi_rst_dqs_find),
.po_en_calib (phy_encalib),
.po_fine_enable (A_po_fine_enable),
.po_coarse_enable (A_po_coarse_enable),
.po_fine_inc (A_po_fine_inc),
.po_coarse_inc (A_po_coarse_inc),
.po_counter_load_en (A_po_counter_load_en),
.po_counter_read_en (A_po_counter_read_en),
.po_counter_load_val (A_po_counter_load_val),
.po_coarse_overflow (A_po_coarse_overflow),
.po_fine_overflow (A_po_fine_overflow),
.po_counter_read_val (A_po_counter_read_val),
.po_sel_fine_oclk_delay(A_po_sel_fine_oclk_delay),
.pi_en_calib (phy_encalib),
.pi_fine_enable (A_pi_fine_enable),
.pi_fine_inc (A_pi_fine_inc),
.pi_counter_load_en (A_pi_counter_load_en),
.pi_counter_read_en (A_pi_counter_read_en),
.pi_counter_load_val (A_pi_counter_load_val),
.pi_fine_overflow (A_pi_fine_overflow),
.pi_counter_read_val (A_pi_counter_read_val),
.pi_iserdes_rst (A_pi_iserdes_rst),
.pi_phase_locked (A_pi_phase_locked),
.fine_delay (A_fine_delay),
.fine_delay_sel (A_fine_delay_sel)
);
end
else begin : no_ddr_byte_lane_A
assign A_of_a_full = 1'b0;
assign A_of_full = 1'b0;
assign A_pre_fifo_a_full = 1'b0;
assign A_if_empty = 1'b0;
assign A_byte_rd_en = 1'b1;
assign A_if_a_empty = 1'b0;
assign A_pi_phase_locked = 1;
assign A_pi_dqs_found = 1;
assign A_rclk = 0;
assign A_ddr_clk = {LP_DDR_CK_WIDTH*6{1'b0}};
assign A_pi_counter_read_val = 0;
assign A_po_counter_read_val = 0;
assign A_pi_fine_overflow = 0;
assign A_po_coarse_overflow = 0;
assign A_po_fine_overflow = 0;
end
if ( BYTE_LANES[1] ) begin : ddr_byte_lane_B
assign phy_dout_remap[159:80] = part_select_80(phy_dout, (LANE_REMAP[5:4]));
mig_7series_v2_3_ddr_byte_lane #
(
.ABCD ("B"),
.PO_DATA_CTL (PC_DATA_CTL_N[1] ? "TRUE" : "FALSE"),
.BITLANES (BITLANES[23:12]),
.BITLANES_OUTONLY (BITLANES_OUTONLY[23:12]),
.OF_ALMOST_EMPTY_VALUE (OF_ALMOST_EMPTY_VALUE),
.OF_ALMOST_FULL_VALUE (OF_ALMOST_FULL_VALUE),
.OF_SYNCHRONOUS_MODE (OF_SYNCHRONOUS_MODE),
//.OF_OUTPUT_DISABLE (OF_OUTPUT_DISABLE),
//.OF_ARRAY_MODE (B_OF_ARRAY_MODE),
//.IF_ARRAY_MODE (IF_ARRAY_MODE),
.IF_ALMOST_EMPTY_VALUE (IF_ALMOST_EMPTY_VALUE),
.IF_ALMOST_FULL_VALUE (IF_ALMOST_FULL_VALUE),
.IF_SYNCHRONOUS_MODE (IF_SYNCHRONOUS_MODE),
.IODELAY_GRP (IODELAY_GRP),
.FPGA_SPEED_GRADE (FPGA_SPEED_GRADE),
.BANK_TYPE (BANK_TYPE),
.BYTELANES_DDR_CK (BYTELANES_DDR_CK),
.RCLK_SELECT_LANE (RCLK_SELECT_LANE),
.USE_PRE_POST_FIFO (USE_PRE_POST_FIFO),
.SYNTHESIS (SYNTHESIS),
.TCK (TCK),
.PC_CLK_RATIO (PC_CLK_RATIO),
.PI_BURST_MODE (B_PI_BURST_MODE),
.PI_CLKOUT_DIV (B_PI_CLKOUT_DIV),
.PI_FREQ_REF_DIV (B_PI_FREQ_REF_DIV),
.PI_FINE_DELAY (B_PI_FINE_DELAY),
.PI_OUTPUT_CLK_SRC (B_PI_OUTPUT_CLK_SRC),
.PI_SYNC_IN_DIV_RST (B_PI_SYNC_IN_DIV_RST),
.PI_SEL_CLK_OFFSET (PI_SEL_CLK_OFFSET),
.PO_CLKOUT_DIV (B_PO_CLKOUT_DIV),
.PO_FINE_DELAY (B_PO_FINE_DELAY),
.PO_COARSE_BYPASS (B_PO_COARSE_BYPASS),
.PO_COARSE_DELAY (B_PO_COARSE_DELAY),
.PO_OCLK_DELAY (B_PO_OCLK_DELAY),
.PO_OCLKDELAY_INV (B_PO_OCLKDELAY_INV),
.PO_OUTPUT_CLK_SRC (B_PO_OUTPUT_CLK_SRC),
.PO_SYNC_IN_DIV_RST (B_PO_SYNC_IN_DIV_RST),
.OSERDES_DATA_RATE (B_OS_DATA_RATE),
.OSERDES_DATA_WIDTH (B_OS_DATA_WIDTH),
.IDELAYE2_IDELAY_TYPE (B_IDELAYE2_IDELAY_TYPE),
.IDELAYE2_IDELAY_VALUE (B_IDELAYE2_IDELAY_VALUE)
,.CKE_ODT_AUX (CKE_ODT_AUX)
)
ddr_byte_lane_B(
.mem_dq_out (mem_dq_out[23:12]),
.mem_dq_ts (mem_dq_ts[23:12]),
.mem_dq_in (mem_dq_in[19:10]),
.mem_dqs_out (mem_dqs_out[1]),
.mem_dqs_ts (mem_dqs_ts[1]),
.mem_dqs_in (mem_dqs_in[1]),
.rst (B_rst_primitives),
.phy_clk (phy_clk),
.freq_refclk (freq_refclk),
.mem_refclk (mem_refclk),
.idelayctrl_refclk (idelayctrl_refclk),
.sync_pulse (sync_pulse),
.ddr_ck_out (B_ddr_clk),
.rclk (B_rclk),
.pi_dqs_found (B_pi_dqs_found),
.dqs_out_of_range (B_pi_dqs_out_of_range),
.if_empty_def (if_empty_def),
.if_a_empty (B_if_a_empty),
.if_empty (B_if_empty),
.if_a_full (/*if_a_full*/),
.if_full (/*B_if_full*/),
.of_a_empty (/*of_a_empty*/),
.of_empty (/*B_of_empty*/),
.of_a_full (B_of_a_full),
.of_full (B_of_full),
.pre_fifo_a_full (B_pre_fifo_a_full),
.phy_din (phy_din_remap[159:80]),
.phy_dout (phy_dout_remap[159:80]),
.phy_cmd_wr_en (phy_cmd_wr_en),
.phy_data_wr_en (phy_data_wr_en),
.phy_rd_en (phy_rd_en),
.phaser_ctl_bus (phaser_ctl_bus),
.if_rst (if_rst),
.byte_rd_en_oth_lanes ({A_byte_rd_en,C_byte_rd_en,D_byte_rd_en}),
.byte_rd_en_oth_banks (byte_rd_en_oth_banks),
.byte_rd_en (B_byte_rd_en),
// calibration signals
.idelay_inc (idelay_inc),
.idelay_ce (B_idelay_ce),
.idelay_ld (B_idelay_ld),
.pi_rst_dqs_find (B_pi_rst_dqs_find),
.po_en_calib (phy_encalib),
.po_fine_enable (B_po_fine_enable),
.po_coarse_enable (B_po_coarse_enable),
.po_fine_inc (B_po_fine_inc),
.po_coarse_inc (B_po_coarse_inc),
.po_counter_load_en (B_po_counter_load_en),
.po_counter_read_en (B_po_counter_read_en),
.po_counter_load_val (B_po_counter_load_val),
.po_coarse_overflow (B_po_coarse_overflow),
.po_fine_overflow (B_po_fine_overflow),
.po_counter_read_val (B_po_counter_read_val),
.po_sel_fine_oclk_delay(B_po_sel_fine_oclk_delay),
.pi_en_calib (phy_encalib),
.pi_fine_enable (B_pi_fine_enable),
.pi_fine_inc (B_pi_fine_inc),
.pi_counter_load_en (B_pi_counter_load_en),
.pi_counter_read_en (B_pi_counter_read_en),
.pi_counter_load_val (B_pi_counter_load_val),
.pi_fine_overflow (B_pi_fine_overflow),
.pi_counter_read_val (B_pi_counter_read_val),
.pi_iserdes_rst (B_pi_iserdes_rst),
.pi_phase_locked (B_pi_phase_locked),
.fine_delay (B_fine_delay),
.fine_delay_sel (B_fine_delay_sel)
);
end
else begin : no_ddr_byte_lane_B
assign B_of_a_full = 1'b0;
assign B_of_full = 1'b0;
assign B_pre_fifo_a_full = 1'b0;
assign B_if_empty = 1'b0;
assign B_if_a_empty = 1'b0;
assign B_byte_rd_en = 1'b1;
assign B_pi_phase_locked = 1;
assign B_pi_dqs_found = 1;
assign B_rclk = 0;
assign B_ddr_clk = {LP_DDR_CK_WIDTH*6{1'b0}};
assign B_pi_counter_read_val = 0;
assign B_po_counter_read_val = 0;
assign B_pi_fine_overflow = 0;
assign B_po_coarse_overflow = 0;
assign B_po_fine_overflow = 0;
end
if ( BYTE_LANES[2] ) begin : ddr_byte_lane_C
assign phy_dout_remap[239:160] = part_select_80(phy_dout, (LANE_REMAP[9:8]));
mig_7series_v2_3_ddr_byte_lane #
(
.ABCD ("C"),
.PO_DATA_CTL (PC_DATA_CTL_N[2] ? "TRUE" : "FALSE"),
.BITLANES (BITLANES[35:24]),
.BITLANES_OUTONLY (BITLANES_OUTONLY[35:24]),
.OF_ALMOST_EMPTY_VALUE (OF_ALMOST_EMPTY_VALUE),
.OF_ALMOST_FULL_VALUE (OF_ALMOST_FULL_VALUE),
.OF_SYNCHRONOUS_MODE (OF_SYNCHRONOUS_MODE),
//.OF_OUTPUT_DISABLE (OF_OUTPUT_DISABLE),
//.OF_ARRAY_MODE (C_OF_ARRAY_MODE),
//.IF_ARRAY_MODE (IF_ARRAY_MODE),
.IF_ALMOST_EMPTY_VALUE (IF_ALMOST_EMPTY_VALUE),
.IF_ALMOST_FULL_VALUE (IF_ALMOST_FULL_VALUE),
.IF_SYNCHRONOUS_MODE (IF_SYNCHRONOUS_MODE),
.IODELAY_GRP (IODELAY_GRP),
.FPGA_SPEED_GRADE (FPGA_SPEED_GRADE),
.BANK_TYPE (BANK_TYPE),
.BYTELANES_DDR_CK (BYTELANES_DDR_CK),
.RCLK_SELECT_LANE (RCLK_SELECT_LANE),
.USE_PRE_POST_FIFO (USE_PRE_POST_FIFO),
.SYNTHESIS (SYNTHESIS),
.TCK (TCK),
.PC_CLK_RATIO (PC_CLK_RATIO),
.PI_BURST_MODE (C_PI_BURST_MODE),
.PI_CLKOUT_DIV (C_PI_CLKOUT_DIV),
.PI_FREQ_REF_DIV (C_PI_FREQ_REF_DIV),
.PI_FINE_DELAY (C_PI_FINE_DELAY),
.PI_OUTPUT_CLK_SRC (C_PI_OUTPUT_CLK_SRC),
.PI_SYNC_IN_DIV_RST (C_PI_SYNC_IN_DIV_RST),
.PI_SEL_CLK_OFFSET (PI_SEL_CLK_OFFSET),
.PO_CLKOUT_DIV (C_PO_CLKOUT_DIV),
.PO_FINE_DELAY (C_PO_FINE_DELAY),
.PO_COARSE_BYPASS (C_PO_COARSE_BYPASS),
.PO_COARSE_DELAY (C_PO_COARSE_DELAY),
.PO_OCLK_DELAY (C_PO_OCLK_DELAY),
.PO_OCLKDELAY_INV (C_PO_OCLKDELAY_INV),
.PO_OUTPUT_CLK_SRC (C_PO_OUTPUT_CLK_SRC),
.PO_SYNC_IN_DIV_RST (C_PO_SYNC_IN_DIV_RST),
.OSERDES_DATA_RATE (C_OS_DATA_RATE),
.OSERDES_DATA_WIDTH (C_OS_DATA_WIDTH),
.IDELAYE2_IDELAY_TYPE (C_IDELAYE2_IDELAY_TYPE),
.IDELAYE2_IDELAY_VALUE (C_IDELAYE2_IDELAY_VALUE)
,.CKE_ODT_AUX (CKE_ODT_AUX)
)
ddr_byte_lane_C(
.mem_dq_out (mem_dq_out[35:24]),
.mem_dq_ts (mem_dq_ts[35:24]),
.mem_dq_in (mem_dq_in[29:20]),
.mem_dqs_out (mem_dqs_out[2]),
.mem_dqs_ts (mem_dqs_ts[2]),
.mem_dqs_in (mem_dqs_in[2]),
.rst (C_rst_primitives),
.phy_clk (phy_clk),
.freq_refclk (freq_refclk),
.mem_refclk (mem_refclk),
.idelayctrl_refclk (idelayctrl_refclk),
.sync_pulse (sync_pulse),
.ddr_ck_out (C_ddr_clk),
.rclk (C_rclk),
.pi_dqs_found (C_pi_dqs_found),
.dqs_out_of_range (C_pi_dqs_out_of_range),
.if_empty_def (if_empty_def),
.if_a_empty (C_if_a_empty),
.if_empty (C_if_empty),
.if_a_full (/*if_a_full*/),
.if_full (/*C_if_full*/),
.of_a_empty (/*of_a_empty*/),
.of_empty (/*C_of_empty*/),
.of_a_full (C_of_a_full),
.of_full (C_of_full),
.pre_fifo_a_full (C_pre_fifo_a_full),
.phy_din (phy_din_remap[239:160]),
.phy_dout (phy_dout_remap[239:160]),
.phy_cmd_wr_en (phy_cmd_wr_en),
.phy_data_wr_en (phy_data_wr_en),
.phy_rd_en (phy_rd_en),
.phaser_ctl_bus (phaser_ctl_bus),
.if_rst (if_rst),
.byte_rd_en_oth_lanes ({A_byte_rd_en,B_byte_rd_en,D_byte_rd_en}),
.byte_rd_en_oth_banks (byte_rd_en_oth_banks),
.byte_rd_en (C_byte_rd_en),
// calibration signals
.idelay_inc (idelay_inc),
.idelay_ce (C_idelay_ce),
.idelay_ld (C_idelay_ld),
.pi_rst_dqs_find (C_pi_rst_dqs_find),
.po_en_calib (phy_encalib),
.po_fine_enable (C_po_fine_enable),
.po_coarse_enable (C_po_coarse_enable),
.po_fine_inc (C_po_fine_inc),
.po_coarse_inc (C_po_coarse_inc),
.po_counter_load_en (C_po_counter_load_en),
.po_counter_read_en (C_po_counter_read_en),
.po_counter_load_val (C_po_counter_load_val),
.po_coarse_overflow (C_po_coarse_overflow),
.po_fine_overflow (C_po_fine_overflow),
.po_counter_read_val (C_po_counter_read_val),
.po_sel_fine_oclk_delay(C_po_sel_fine_oclk_delay),
.pi_en_calib (phy_encalib),
.pi_fine_enable (C_pi_fine_enable),
.pi_fine_inc (C_pi_fine_inc),
.pi_counter_load_en (C_pi_counter_load_en),
.pi_counter_read_en (C_pi_counter_read_en),
.pi_counter_load_val (C_pi_counter_load_val),
.pi_fine_overflow (C_pi_fine_overflow),
.pi_counter_read_val (C_pi_counter_read_val),
.pi_iserdes_rst (C_pi_iserdes_rst),
.pi_phase_locked (C_pi_phase_locked),
.fine_delay (C_fine_delay),
.fine_delay_sel (C_fine_delay_sel)
);
end
else begin : no_ddr_byte_lane_C
assign C_of_a_full = 1'b0;
assign C_of_full = 1'b0;
assign C_pre_fifo_a_full = 1'b0;
assign C_if_empty = 1'b0;
assign C_byte_rd_en = 1'b1;
assign C_if_a_empty = 1'b0;
assign C_pi_phase_locked = 1;
assign C_pi_dqs_found = 1;
assign C_rclk = 0;
assign C_ddr_clk = {LP_DDR_CK_WIDTH*6{1'b0}};
assign C_pi_counter_read_val = 0;
assign C_po_counter_read_val = 0;
assign C_pi_fine_overflow = 0;
assign C_po_coarse_overflow = 0;
assign C_po_fine_overflow = 0;
end
if ( BYTE_LANES[3] ) begin : ddr_byte_lane_D
assign phy_dout_remap[319:240] = part_select_80(phy_dout, (LANE_REMAP[13:12]));
mig_7series_v2_3_ddr_byte_lane #
(
.ABCD ("D"),
.PO_DATA_CTL (PC_DATA_CTL_N[3] ? "TRUE" : "FALSE"),
.BITLANES (BITLANES[47:36]),
.BITLANES_OUTONLY (BITLANES_OUTONLY[47:36]),
.OF_ALMOST_EMPTY_VALUE (OF_ALMOST_EMPTY_VALUE),
.OF_ALMOST_FULL_VALUE (OF_ALMOST_FULL_VALUE),
.OF_SYNCHRONOUS_MODE (OF_SYNCHRONOUS_MODE),
//.OF_OUTPUT_DISABLE (OF_OUTPUT_DISABLE),
//.OF_ARRAY_MODE (D_OF_ARRAY_MODE),
//.IF_ARRAY_MODE (IF_ARRAY_MODE),
.IF_ALMOST_EMPTY_VALUE (IF_ALMOST_EMPTY_VALUE),
.IF_ALMOST_FULL_VALUE (IF_ALMOST_FULL_VALUE),
.IF_SYNCHRONOUS_MODE (IF_SYNCHRONOUS_MODE),
.IODELAY_GRP (IODELAY_GRP),
.FPGA_SPEED_GRADE (FPGA_SPEED_GRADE),
.BANK_TYPE (BANK_TYPE),
.BYTELANES_DDR_CK (BYTELANES_DDR_CK),
.RCLK_SELECT_LANE (RCLK_SELECT_LANE),
.USE_PRE_POST_FIFO (USE_PRE_POST_FIFO),
.SYNTHESIS (SYNTHESIS),
.TCK (TCK),
.PC_CLK_RATIO (PC_CLK_RATIO),
.PI_BURST_MODE (D_PI_BURST_MODE),
.PI_CLKOUT_DIV (D_PI_CLKOUT_DIV),
.PI_FREQ_REF_DIV (D_PI_FREQ_REF_DIV),
.PI_FINE_DELAY (D_PI_FINE_DELAY),
.PI_OUTPUT_CLK_SRC (D_PI_OUTPUT_CLK_SRC),
.PI_SYNC_IN_DIV_RST (D_PI_SYNC_IN_DIV_RST),
.PI_SEL_CLK_OFFSET (PI_SEL_CLK_OFFSET),
.PO_CLKOUT_DIV (D_PO_CLKOUT_DIV),
.PO_FINE_DELAY (D_PO_FINE_DELAY),
.PO_COARSE_BYPASS (D_PO_COARSE_BYPASS),
.PO_COARSE_DELAY (D_PO_COARSE_DELAY),
.PO_OCLK_DELAY (D_PO_OCLK_DELAY),
.PO_OCLKDELAY_INV (D_PO_OCLKDELAY_INV),
.PO_OUTPUT_CLK_SRC (D_PO_OUTPUT_CLK_SRC),
.PO_SYNC_IN_DIV_RST (D_PO_SYNC_IN_DIV_RST),
.OSERDES_DATA_RATE (D_OS_DATA_RATE),
.OSERDES_DATA_WIDTH (D_OS_DATA_WIDTH),
.IDELAYE2_IDELAY_TYPE (D_IDELAYE2_IDELAY_TYPE),
.IDELAYE2_IDELAY_VALUE (D_IDELAYE2_IDELAY_VALUE)
,.CKE_ODT_AUX (CKE_ODT_AUX)
)
ddr_byte_lane_D(
.mem_dq_out (mem_dq_out[47:36]),
.mem_dq_ts (mem_dq_ts[47:36]),
.mem_dq_in (mem_dq_in[39:30]),
.mem_dqs_out (mem_dqs_out[3]),
.mem_dqs_ts (mem_dqs_ts[3]),
.mem_dqs_in (mem_dqs_in[3]),
.rst (D_rst_primitives),
.phy_clk (phy_clk),
.freq_refclk (freq_refclk),
.mem_refclk (mem_refclk),
.idelayctrl_refclk (idelayctrl_refclk),
.sync_pulse (sync_pulse),
.ddr_ck_out (D_ddr_clk),
.rclk (D_rclk),
.pi_dqs_found (D_pi_dqs_found),
.dqs_out_of_range (D_pi_dqs_out_of_range),
.if_empty_def (if_empty_def),
.if_a_empty (D_if_a_empty),
.if_empty (D_if_empty),
.if_a_full (/*if_a_full*/),
.if_full (/*D_if_full*/),
.of_a_empty (/*of_a_empty*/),
.of_empty (/*D_of_empty*/),
.of_a_full (D_of_a_full),
.of_full (D_of_full),
.pre_fifo_a_full (D_pre_fifo_a_full),
.phy_din (phy_din_remap[319:240]),
.phy_dout (phy_dout_remap[319:240]),
.phy_cmd_wr_en (phy_cmd_wr_en),
.phy_data_wr_en (phy_data_wr_en),
.phy_rd_en (phy_rd_en),
.phaser_ctl_bus (phaser_ctl_bus),
.idelay_inc (idelay_inc),
.idelay_ce (D_idelay_ce),
.idelay_ld (D_idelay_ld),
.if_rst (if_rst),
.byte_rd_en_oth_lanes ({A_byte_rd_en,B_byte_rd_en,C_byte_rd_en}),
.byte_rd_en_oth_banks (byte_rd_en_oth_banks),
.byte_rd_en (D_byte_rd_en),
// calibration signals
.pi_rst_dqs_find (D_pi_rst_dqs_find),
.po_en_calib (phy_encalib),
.po_fine_enable (D_po_fine_enable),
.po_coarse_enable (D_po_coarse_enable),
.po_fine_inc (D_po_fine_inc),
.po_coarse_inc (D_po_coarse_inc),
.po_counter_load_en (D_po_counter_load_en),
.po_counter_read_en (D_po_counter_read_en),
.po_counter_load_val (D_po_counter_load_val),
.po_coarse_overflow (D_po_coarse_overflow),
.po_fine_overflow (D_po_fine_overflow),
.po_counter_read_val (D_po_counter_read_val),
.po_sel_fine_oclk_delay(D_po_sel_fine_oclk_delay),
.pi_en_calib (phy_encalib),
.pi_fine_enable (D_pi_fine_enable),
.pi_fine_inc (D_pi_fine_inc),
.pi_counter_load_en (D_pi_counter_load_en),
.pi_counter_read_en (D_pi_counter_read_en),
.pi_counter_load_val (D_pi_counter_load_val),
.pi_fine_overflow (D_pi_fine_overflow),
.pi_counter_read_val (D_pi_counter_read_val),
.pi_iserdes_rst (D_pi_iserdes_rst),
.pi_phase_locked (D_pi_phase_locked),
.fine_delay (D_fine_delay),
.fine_delay_sel (D_fine_delay_sel)
);
end
else begin : no_ddr_byte_lane_D
assign D_of_a_full = 1'b0;
assign D_of_full = 1'b0;
assign D_pre_fifo_a_full = 1'b0;
assign D_if_empty = 1'b0;
assign D_byte_rd_en = 1'b1;
assign D_if_a_empty = 1'b0;
assign D_rclk = 0;
assign D_ddr_clk = {LP_DDR_CK_WIDTH*6{1'b0}};
assign D_pi_dqs_found = 1;
assign D_pi_phase_locked = 1;
assign D_pi_counter_read_val = 0;
assign D_po_counter_read_val = 0;
assign D_pi_fine_overflow = 0;
assign D_po_coarse_overflow = 0;
assign D_po_fine_overflow = 0;
end
endgenerate
assign phaser_ctl_bus[MSB_RANK_SEL_I : MSB_RANK_SEL_I - 7] = in_rank;
PHY_CONTROL #(
.AO_WRLVL_EN ( PC_AO_WRLVL_EN),
.AO_TOGGLE ( PC_AO_TOGGLE),
.BURST_MODE ( PC_BURST_MODE),
.CO_DURATION ( PC_CO_DURATION ),
.CLK_RATIO ( PC_CLK_RATIO),
.DATA_CTL_A_N ( PC_DATA_CTL_A),
.DATA_CTL_B_N ( PC_DATA_CTL_B),
.DATA_CTL_C_N ( PC_DATA_CTL_C),
.DATA_CTL_D_N ( PC_DATA_CTL_D),
.DI_DURATION ( PC_DI_DURATION ),
.DO_DURATION ( PC_DO_DURATION ),
.EVENTS_DELAY ( PC_EVENTS_DELAY),
.FOUR_WINDOW_CLOCKS ( PC_FOUR_WINDOW_CLOCKS),
.MULTI_REGION ( PC_MULTI_REGION ),
.PHY_COUNT_ENABLE ( PC_PHY_COUNT_EN),
.DISABLE_SEQ_MATCH ( PC_DISABLE_SEQ_MATCH),
.SYNC_MODE ( PC_SYNC_MODE),
.CMD_OFFSET ( PC_CMD_OFFSET),
.RD_CMD_OFFSET_0 ( PC_RD_CMD_OFFSET_0),
.RD_CMD_OFFSET_1 ( PC_RD_CMD_OFFSET_1),
.RD_CMD_OFFSET_2 ( PC_RD_CMD_OFFSET_2),
.RD_CMD_OFFSET_3 ( PC_RD_CMD_OFFSET_3),
.RD_DURATION_0 ( PC_RD_DURATION_0),
.RD_DURATION_1 ( PC_RD_DURATION_1),
.RD_DURATION_2 ( PC_RD_DURATION_2),
.RD_DURATION_3 ( PC_RD_DURATION_3),
.WR_CMD_OFFSET_0 ( PC_WR_CMD_OFFSET_0),
.WR_CMD_OFFSET_1 ( PC_WR_CMD_OFFSET_1),
.WR_CMD_OFFSET_2 ( PC_WR_CMD_OFFSET_2),
.WR_CMD_OFFSET_3 ( PC_WR_CMD_OFFSET_3),
.WR_DURATION_0 ( PC_WR_DURATION_0),
.WR_DURATION_1 ( PC_WR_DURATION_1),
.WR_DURATION_2 ( PC_WR_DURATION_2),
.WR_DURATION_3 ( PC_WR_DURATION_3)
) phy_control_i (
.AUXOUTPUT (aux_out),
.INBURSTPENDING (phaser_ctl_bus[MSB_BURST_PEND_PI:MSB_BURST_PEND_PI-3]),
.INRANKA (in_rank[1:0]),
.INRANKB (in_rank[3:2]),
.INRANKC (in_rank[5:4]),
.INRANKD (in_rank[7:6]),
.OUTBURSTPENDING (phaser_ctl_bus[MSB_BURST_PEND_PO:MSB_BURST_PEND_PO-3]),
.PCENABLECALIB (phy_encalib),
.PHYCTLALMOSTFULL (phy_ctl_a_full),
.PHYCTLEMPTY (phy_ctl_empty),
.PHYCTLFULL (phy_ctl_full),
.PHYCTLREADY (phy_ctl_ready),
.MEMREFCLK (mem_refclk),
.PHYCLK (phy_ctl_clk),
.PHYCTLMSTREMPTY (phy_ctl_mstr_empty),
.PHYCTLWD (_phy_ctl_wd),
.PHYCTLWRENABLE (phy_ctl_wr),
.PLLLOCK (pll_lock),
.REFDLLLOCK (ref_dll_lock), // is reset while !locked
.RESET (rst),
.SYNCIN (sync_pulse),
.READCALIBENABLE (phy_read_calib),
.WRITECALIBENABLE (phy_write_calib)
`ifdef USE_PHY_CONTROL_TEST
, .TESTINPUT (16'b0),
.TESTOUTPUT (test_output),
.TESTSELECT (test_select),
.SCANENABLEN (scan_enable)
`endif
);
// register outputs to give extra slack in timing
always @(posedge phy_clk ) begin
case (calib_sel[1:0])
2'h0: begin
po_coarse_overflow <= #1 A_po_coarse_overflow;
po_fine_overflow <= #1 A_po_fine_overflow;
po_counter_read_val <= #1 A_po_counter_read_val;
pi_fine_overflow <= #1 A_pi_fine_overflow;
pi_counter_read_val<= #1 A_pi_counter_read_val;
pi_phase_locked <= #1 A_pi_phase_locked;
if ( calib_in_common)
pi_dqs_found <= #1 pi_dqs_found_any;
else
pi_dqs_found <= #1 A_pi_dqs_found;
pi_dqs_out_of_range <= #1 A_pi_dqs_out_of_range;
end
2'h1: begin
po_coarse_overflow <= #1 B_po_coarse_overflow;
po_fine_overflow <= #1 B_po_fine_overflow;
po_counter_read_val <= #1 B_po_counter_read_val;
pi_fine_overflow <= #1 B_pi_fine_overflow;
pi_counter_read_val <= #1 B_pi_counter_read_val;
pi_phase_locked <= #1 B_pi_phase_locked;
if ( calib_in_common)
pi_dqs_found <= #1 pi_dqs_found_any;
else
pi_dqs_found <= #1 B_pi_dqs_found;
pi_dqs_out_of_range <= #1 B_pi_dqs_out_of_range;
end
2'h2: begin
po_coarse_overflow <= #1 C_po_coarse_overflow;
po_fine_overflow <= #1 C_po_fine_overflow;
po_counter_read_val <= #1 C_po_counter_read_val;
pi_fine_overflow <= #1 C_pi_fine_overflow;
pi_counter_read_val <= #1 C_pi_counter_read_val;
pi_phase_locked <= #1 C_pi_phase_locked;
if ( calib_in_common)
pi_dqs_found <= #1 pi_dqs_found_any;
else
pi_dqs_found <= #1 C_pi_dqs_found;
pi_dqs_out_of_range <= #1 C_pi_dqs_out_of_range;
end
2'h3: begin
po_coarse_overflow <= #1 D_po_coarse_overflow;
po_fine_overflow <= #1 D_po_fine_overflow;
po_counter_read_val <= #1 D_po_counter_read_val;
pi_fine_overflow <= #1 D_pi_fine_overflow;
pi_counter_read_val <= #1 D_pi_counter_read_val;
pi_phase_locked <= #1 D_pi_phase_locked;
if ( calib_in_common)
pi_dqs_found <= #1 pi_dqs_found_any;
else
pi_dqs_found <= #1 D_pi_dqs_found;
pi_dqs_out_of_range <= #1 D_pi_dqs_out_of_range;
end
default: begin
po_coarse_overflow <= po_coarse_overflow;
end
endcase
end
wire B_mux_ctrl;
wire C_mux_ctrl;
wire D_mux_ctrl;
generate
if (HIGHEST_LANE > 1)
assign B_mux_ctrl = ( !calib_zero_lanes[1] && ( ! calib_zero_ctrl || DATA_CTL_N[1]));
else
assign B_mux_ctrl = 0;
if (HIGHEST_LANE > 2)
assign C_mux_ctrl = ( !calib_zero_lanes[2] && (! calib_zero_ctrl || DATA_CTL_N[2]));
else
assign C_mux_ctrl = 0;
if (HIGHEST_LANE > 3)
assign D_mux_ctrl = ( !calib_zero_lanes[3] && ( ! calib_zero_ctrl || DATA_CTL_N[3]));
else
assign D_mux_ctrl = 0;
endgenerate
always @(*) begin
A_pi_fine_enable = 0;
A_pi_fine_inc = 0;
A_pi_counter_load_en = 0;
A_pi_counter_read_en = 0;
A_pi_counter_load_val = 0;
A_pi_rst_dqs_find = 0;
A_po_fine_enable = 0;
A_po_coarse_enable = 0;
A_po_fine_inc = 0;
A_po_coarse_inc = 0;
A_po_counter_load_en = 0;
A_po_counter_read_en = 0;
A_po_counter_load_val = 0;
A_po_sel_fine_oclk_delay = 0;
A_idelay_ce = 0;
A_idelay_ld = 0;
A_fine_delay = 0;
A_fine_delay_sel = 0;
B_pi_fine_enable = 0;
B_pi_fine_inc = 0;
B_pi_counter_load_en = 0;
B_pi_counter_read_en = 0;
B_pi_counter_load_val = 0;
B_pi_rst_dqs_find = 0;
B_po_fine_enable = 0;
B_po_coarse_enable = 0;
B_po_fine_inc = 0;
B_po_coarse_inc = 0;
B_po_counter_load_en = 0;
B_po_counter_read_en = 0;
B_po_counter_load_val = 0;
B_po_sel_fine_oclk_delay = 0;
B_idelay_ce = 0;
B_idelay_ld = 0;
B_fine_delay = 0;
B_fine_delay_sel = 0;
C_pi_fine_enable = 0;
C_pi_fine_inc = 0;
C_pi_counter_load_en = 0;
C_pi_counter_read_en = 0;
C_pi_counter_load_val = 0;
C_pi_rst_dqs_find = 0;
C_po_fine_enable = 0;
C_po_coarse_enable = 0;
C_po_fine_inc = 0;
C_po_coarse_inc = 0;
C_po_counter_load_en = 0;
C_po_counter_read_en = 0;
C_po_counter_load_val = 0;
C_po_sel_fine_oclk_delay = 0;
C_idelay_ce = 0;
C_idelay_ld = 0;
C_fine_delay = 0;
C_fine_delay_sel = 0;
D_pi_fine_enable = 0;
D_pi_fine_inc = 0;
D_pi_counter_load_en = 0;
D_pi_counter_read_en = 0;
D_pi_counter_load_val = 0;
D_pi_rst_dqs_find = 0;
D_po_fine_enable = 0;
D_po_coarse_enable = 0;
D_po_fine_inc = 0;
D_po_coarse_inc = 0;
D_po_counter_load_en = 0;
D_po_counter_read_en = 0;
D_po_counter_load_val = 0;
D_po_sel_fine_oclk_delay = 0;
D_idelay_ce = 0;
D_idelay_ld = 0;
D_fine_delay = 0;
D_fine_delay_sel = 0;
if ( calib_sel[2]) begin
// if this is asserted, all calib signals are deasserted
A_pi_fine_enable = 0;
A_pi_fine_inc = 0;
A_pi_counter_load_en = 0;
A_pi_counter_read_en = 0;
A_pi_counter_load_val = 0;
A_pi_rst_dqs_find = 0;
A_po_fine_enable = 0;
A_po_coarse_enable = 0;
A_po_fine_inc = 0;
A_po_coarse_inc = 0;
A_po_counter_load_en = 0;
A_po_counter_read_en = 0;
A_po_counter_load_val = 0;
A_po_sel_fine_oclk_delay = 0;
A_idelay_ce = 0;
A_idelay_ld = 0;
A_fine_delay = 0;
A_fine_delay_sel = 0;
B_pi_fine_enable = 0;
B_pi_fine_inc = 0;
B_pi_counter_load_en = 0;
B_pi_counter_read_en = 0;
B_pi_counter_load_val = 0;
B_pi_rst_dqs_find = 0;
B_po_fine_enable = 0;
B_po_coarse_enable = 0;
B_po_fine_inc = 0;
B_po_coarse_inc = 0;
B_po_counter_load_en = 0;
B_po_counter_read_en = 0;
B_po_counter_load_val = 0;
B_po_sel_fine_oclk_delay = 0;
B_idelay_ce = 0;
B_idelay_ld = 0;
B_fine_delay = 0;
B_fine_delay_sel = 0;
C_pi_fine_enable = 0;
C_pi_fine_inc = 0;
C_pi_counter_load_en = 0;
C_pi_counter_read_en = 0;
C_pi_counter_load_val = 0;
C_pi_rst_dqs_find = 0;
C_po_fine_enable = 0;
C_po_coarse_enable = 0;
C_po_fine_inc = 0;
C_po_coarse_inc = 0;
C_po_counter_load_en = 0;
C_po_counter_read_en = 0;
C_po_counter_load_val = 0;
C_po_sel_fine_oclk_delay = 0;
C_idelay_ce = 0;
C_idelay_ld = 0;
C_fine_delay = 0;
C_fine_delay_sel = 0;
D_pi_fine_enable = 0;
D_pi_fine_inc = 0;
D_pi_counter_load_en = 0;
D_pi_counter_read_en = 0;
D_pi_counter_load_val = 0;
D_pi_rst_dqs_find = 0;
D_po_fine_enable = 0;
D_po_coarse_enable = 0;
D_po_fine_inc = 0;
D_po_coarse_inc = 0;
D_po_counter_load_en = 0;
D_po_counter_read_en = 0;
D_po_counter_load_val = 0;
D_po_sel_fine_oclk_delay = 0;
D_idelay_ce = 0;
D_idelay_ld = 0;
D_fine_delay = 0;
D_fine_delay_sel = 0;
end else
if (calib_in_common) begin
// if this is asserted, each signal is broadcast to all phasers
// in common
if ( !calib_zero_lanes[0] && (! calib_zero_ctrl || DATA_CTL_N[0])) begin
A_pi_fine_enable = pi_fine_enable;
A_pi_fine_inc = pi_fine_inc;
A_pi_counter_load_en = pi_counter_load_en;
A_pi_counter_read_en = pi_counter_read_en;
A_pi_counter_load_val = pi_counter_load_val;
A_pi_rst_dqs_find = pi_rst_dqs_find;
A_po_fine_enable = po_fine_enable;
A_po_coarse_enable = po_coarse_enable;
A_po_fine_inc = po_fine_inc;
A_po_coarse_inc = po_coarse_inc;
A_po_counter_load_en = po_counter_load_en;
A_po_counter_read_en = po_counter_read_en;
A_po_counter_load_val = po_counter_load_val;
A_po_sel_fine_oclk_delay = po_sel_fine_oclk_delay;
A_idelay_ce = idelay_ce;
A_idelay_ld = idelay_ld;
A_fine_delay = fine_delay ;
A_fine_delay_sel = fine_delay_sel;
end
if ( B_mux_ctrl) begin
B_pi_fine_enable = pi_fine_enable;
B_pi_fine_inc = pi_fine_inc;
B_pi_counter_load_en = pi_counter_load_en;
B_pi_counter_read_en = pi_counter_read_en;
B_pi_counter_load_val = pi_counter_load_val;
B_pi_rst_dqs_find = pi_rst_dqs_find;
B_po_fine_enable = po_fine_enable;
B_po_coarse_enable = po_coarse_enable;
B_po_fine_inc = po_fine_inc;
B_po_coarse_inc = po_coarse_inc;
B_po_counter_load_en = po_counter_load_en;
B_po_counter_read_en = po_counter_read_en;
B_po_counter_load_val = po_counter_load_val;
B_po_sel_fine_oclk_delay = po_sel_fine_oclk_delay;
B_idelay_ce = idelay_ce;
B_idelay_ld = idelay_ld;
B_fine_delay = fine_delay ;
B_fine_delay_sel = fine_delay_sel;
end
if ( C_mux_ctrl) begin
C_pi_fine_enable = pi_fine_enable;
C_pi_fine_inc = pi_fine_inc;
C_pi_counter_load_en = pi_counter_load_en;
C_pi_counter_read_en = pi_counter_read_en;
C_pi_counter_load_val = pi_counter_load_val;
C_pi_rst_dqs_find = pi_rst_dqs_find;
C_po_fine_enable = po_fine_enable;
C_po_coarse_enable = po_coarse_enable;
C_po_fine_inc = po_fine_inc;
C_po_coarse_inc = po_coarse_inc;
C_po_counter_load_en = po_counter_load_en;
C_po_counter_read_en = po_counter_read_en;
C_po_counter_load_val = po_counter_load_val;
C_po_sel_fine_oclk_delay = po_sel_fine_oclk_delay;
C_idelay_ce = idelay_ce;
C_idelay_ld = idelay_ld;
C_fine_delay = fine_delay ;
C_fine_delay_sel = fine_delay_sel;
end
if ( D_mux_ctrl) begin
D_pi_fine_enable = pi_fine_enable;
D_pi_fine_inc = pi_fine_inc;
D_pi_counter_load_en = pi_counter_load_en;
D_pi_counter_read_en = pi_counter_read_en;
D_pi_counter_load_val = pi_counter_load_val;
D_pi_rst_dqs_find = pi_rst_dqs_find;
D_po_fine_enable = po_fine_enable;
D_po_coarse_enable = po_coarse_enable;
D_po_fine_inc = po_fine_inc;
D_po_coarse_inc = po_coarse_inc;
D_po_counter_load_en = po_counter_load_en;
D_po_counter_read_en = po_counter_read_en;
D_po_counter_load_val = po_counter_load_val;
D_po_sel_fine_oclk_delay = po_sel_fine_oclk_delay;
D_idelay_ce = idelay_ce;
D_idelay_ld = idelay_ld;
D_fine_delay = fine_delay ;
D_fine_delay_sel = fine_delay_sel;
end
end
else begin
// otherwise, only a single phaser is selected
case (calib_sel[1:0])
0: begin
A_pi_fine_enable = pi_fine_enable;
A_pi_fine_inc = pi_fine_inc;
A_pi_counter_load_en = pi_counter_load_en;
A_pi_counter_read_en = pi_counter_read_en;
A_pi_counter_load_val = pi_counter_load_val;
A_pi_rst_dqs_find = pi_rst_dqs_find;
A_po_fine_enable = po_fine_enable;
A_po_coarse_enable = po_coarse_enable;
A_po_fine_inc = po_fine_inc;
A_po_coarse_inc = po_coarse_inc;
A_po_counter_load_en = po_counter_load_en;
A_po_counter_read_en = po_counter_read_en;
A_po_counter_load_val = po_counter_load_val;
A_po_sel_fine_oclk_delay = po_sel_fine_oclk_delay;
A_idelay_ce = idelay_ce;
A_idelay_ld = idelay_ld;
A_fine_delay = fine_delay ;
A_fine_delay_sel = fine_delay_sel;
end
1: begin
B_pi_fine_enable = pi_fine_enable;
B_pi_fine_inc = pi_fine_inc;
B_pi_counter_load_en = pi_counter_load_en;
B_pi_counter_read_en = pi_counter_read_en;
B_pi_counter_load_val = pi_counter_load_val;
B_pi_rst_dqs_find = pi_rst_dqs_find;
B_po_fine_enable = po_fine_enable;
B_po_coarse_enable = po_coarse_enable;
B_po_fine_inc = po_fine_inc;
B_po_coarse_inc = po_coarse_inc;
B_po_counter_load_en = po_counter_load_en;
B_po_counter_read_en = po_counter_read_en;
B_po_counter_load_val = po_counter_load_val;
B_po_sel_fine_oclk_delay = po_sel_fine_oclk_delay;
B_idelay_ce = idelay_ce;
B_idelay_ld = idelay_ld;
B_fine_delay = fine_delay ;
B_fine_delay_sel = fine_delay_sel;
end
2: begin
C_pi_fine_enable = pi_fine_enable;
C_pi_fine_inc = pi_fine_inc;
C_pi_counter_load_en = pi_counter_load_en;
C_pi_counter_read_en = pi_counter_read_en;
C_pi_counter_load_val = pi_counter_load_val;
C_pi_rst_dqs_find = pi_rst_dqs_find;
C_po_fine_enable = po_fine_enable;
C_po_coarse_enable = po_coarse_enable;
C_po_fine_inc = po_fine_inc;
C_po_coarse_inc = po_coarse_inc;
C_po_counter_load_en = po_counter_load_en;
C_po_counter_read_en = po_counter_read_en;
C_po_counter_load_val = po_counter_load_val;
C_po_sel_fine_oclk_delay = po_sel_fine_oclk_delay;
C_idelay_ce = idelay_ce;
C_idelay_ld = idelay_ld;
C_fine_delay = fine_delay ;
C_fine_delay_sel = fine_delay_sel;
end
3: begin
D_pi_fine_enable = pi_fine_enable;
D_pi_fine_inc = pi_fine_inc;
D_pi_counter_load_en = pi_counter_load_en;
D_pi_counter_read_en = pi_counter_read_en;
D_pi_counter_load_val = pi_counter_load_val;
D_pi_rst_dqs_find = pi_rst_dqs_find;
D_po_fine_enable = po_fine_enable;
D_po_coarse_enable = po_coarse_enable;
D_po_fine_inc = po_fine_inc;
D_po_coarse_inc = po_coarse_inc;
D_po_counter_load_en = po_counter_load_en;
D_po_counter_load_val = po_counter_load_val;
D_po_counter_read_en = po_counter_read_en;
D_po_sel_fine_oclk_delay = po_sel_fine_oclk_delay;
D_idelay_ce = idelay_ce;
D_idelay_ld = idelay_ld;
D_fine_delay = fine_delay ;
D_fine_delay_sel = fine_delay_sel;
end
endcase
end
end
//obligatory phaser-ref
PHASER_REF phaser_ref_i(
.LOCKED (ref_dll_lock),
.CLKIN (freq_refclk),
.PWRDWN (1'b0),
.RST ( ! pll_lock)
);
// optional idelay_ctrl
generate
if ( GENERATE_IDELAYCTRL == "TRUE")
IDELAYCTRL idelayctrl (
.RDY (/*idelayctrl_rdy*/),
.REFCLK (idelayctrl_refclk),
.RST (rst)
);
endgenerate
endmodule
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : pcie_7x_v1_11_0_gt_top.v
// Version : 1.11
//-- Description: GTX module for 7-series Integrated PCIe Block
//--
//--
//--
//--------------------------------------------------------------------------------
`timescale 1ns/1ns
module pcie_7x_v1_11_0_gt_top #
(
parameter LINK_CAP_MAX_LINK_WIDTH = 8, // 1 - x1 , 2 - x2 , 4 - x4 , 8 - x8
parameter REF_CLK_FREQ = 0, // 0 - 100 MHz , 1 - 125 MHz , 2 - 250 MHz
parameter USER_CLK2_DIV2 = "FALSE", // "FALSE" => user_clk2 = user_clk
// "TRUE" => user_clk2 = user_clk/2, where user_clk = 500 or 250 MHz.
parameter integer USER_CLK_FREQ = 3, // 0 - 31.25 MHz , 1 - 62.5 MHz , 2 - 125 MHz , 3 - 250 MHz , 4 - 500Mhz
parameter PL_FAST_TRAIN = "FALSE", // Simulation Speedup
parameter PCIE_EXT_CLK = "FALSE", // Use External Clocking
parameter PCIE_USE_MODE = "1.0", // 1.0 = K325T IES, 1.1 = VX485T IES, 3.0 = K325T GES
parameter PCIE_GT_DEVICE = "GTX", // Select the GT to use (GTP for Artix-7, GTX for K7/V7)
parameter PCIE_PLL_SEL = "CPLL", // Select the PLL (CPLL or QPLL)
parameter PCIE_ASYNC_EN = "FALSE", // Asynchronous Clocking Enable
parameter PCIE_TXBUF_EN = "FALSE", // Use the Tansmit Buffer
parameter PCIE_CHAN_BOND = 0
)
(
//-----------------------------------------------------------------------------------------------------------------//
// pl ltssm
input wire [5:0] pl_ltssm_state ,
// Pipe Per-Link Signals
input wire pipe_tx_rcvr_det ,
input wire pipe_tx_reset ,
input wire pipe_tx_rate ,
input wire pipe_tx_deemph ,
input wire [2:0] pipe_tx_margin ,
input wire pipe_tx_swing ,
//-----------------------------------------------------------------------------------------------------------------//
// Clock Inputs //
//-----------------------------------------------------------------------------------------------------------------//
input PIPE_PCLK_IN,
input PIPE_RXUSRCLK_IN,
input [(LINK_CAP_MAX_LINK_WIDTH - 1) : 0] PIPE_RXOUTCLK_IN,
input PIPE_DCLK_IN,
input PIPE_USERCLK1_IN,
input PIPE_USERCLK2_IN,
input PIPE_OOBCLK_IN,
input PIPE_MMCM_LOCK_IN,
output PIPE_TXOUTCLK_OUT,
output [(LINK_CAP_MAX_LINK_WIDTH - 1) : 0] PIPE_RXOUTCLK_OUT,
output [(LINK_CAP_MAX_LINK_WIDTH - 1) : 0] PIPE_PCLK_SEL_OUT,
output PIPE_GEN3_OUT,
// Pipe Per-Lane Signals - Lane 0
output wire [ 1:0] pipe_rx0_char_is_k ,
output wire [15:0] pipe_rx0_data ,
output wire pipe_rx0_valid ,
output wire pipe_rx0_chanisaligned ,
output wire [ 2:0] pipe_rx0_status ,
output wire pipe_rx0_phy_status ,
output wire pipe_rx0_elec_idle ,
input wire pipe_rx0_polarity ,
input wire pipe_tx0_compliance ,
input wire [ 1:0] pipe_tx0_char_is_k ,
input wire [15:0] pipe_tx0_data ,
input wire pipe_tx0_elec_idle ,
input wire [ 1:0] pipe_tx0_powerdown ,
// Pipe Per-Lane Signals - Lane 1
output wire [ 1:0] pipe_rx1_char_is_k ,
output wire [15:0] pipe_rx1_data ,
output wire pipe_rx1_valid ,
output wire pipe_rx1_chanisaligned ,
output wire [ 2:0] pipe_rx1_status ,
output wire pipe_rx1_phy_status ,
output wire pipe_rx1_elec_idle ,
input wire pipe_rx1_polarity ,
input wire pipe_tx1_compliance ,
input wire [ 1:0] pipe_tx1_char_is_k ,
input wire [15:0] pipe_tx1_data ,
input wire pipe_tx1_elec_idle ,
input wire [ 1:0] pipe_tx1_powerdown ,
// Pipe Per-Lane Signals - Lane 2
output wire [ 1:0] pipe_rx2_char_is_k ,
output wire [15:0] pipe_rx2_data ,
output wire pipe_rx2_valid ,
output wire pipe_rx2_chanisaligned ,
output wire [ 2:0] pipe_rx2_status ,
output wire pipe_rx2_phy_status ,
output wire pipe_rx2_elec_idle ,
input wire pipe_rx2_polarity ,
input wire pipe_tx2_compliance ,
input wire [ 1:0] pipe_tx2_char_is_k ,
input wire [15:0] pipe_tx2_data ,
input wire pipe_tx2_elec_idle ,
input wire [ 1:0] pipe_tx2_powerdown ,
// Pipe Per-Lane Signals - Lane 3
output wire [ 1:0] pipe_rx3_char_is_k ,
output wire [15:0] pipe_rx3_data ,
output wire pipe_rx3_valid ,
output wire pipe_rx3_chanisaligned ,
output wire [ 2:0] pipe_rx3_status ,
output wire pipe_rx3_phy_status ,
output wire pipe_rx3_elec_idle ,
input wire pipe_rx3_polarity ,
input wire pipe_tx3_compliance ,
input wire [ 1:0] pipe_tx3_char_is_k ,
input wire [15:0] pipe_tx3_data ,
input wire pipe_tx3_elec_idle ,
input wire [ 1:0] pipe_tx3_powerdown ,
// Pipe Per-Lane Signals - Lane 4
output wire [ 1:0] pipe_rx4_char_is_k ,
output wire [15:0] pipe_rx4_data ,
output wire pipe_rx4_valid ,
output wire pipe_rx4_chanisaligned ,
output wire [ 2:0] pipe_rx4_status ,
output wire pipe_rx4_phy_status ,
output wire pipe_rx4_elec_idle ,
input wire pipe_rx4_polarity ,
input wire pipe_tx4_compliance ,
input wire [ 1:0] pipe_tx4_char_is_k ,
input wire [15:0] pipe_tx4_data ,
input wire pipe_tx4_elec_idle ,
input wire [ 1:0] pipe_tx4_powerdown ,
// Pipe Per-Lane Signals - Lane 5
output wire [ 1:0] pipe_rx5_char_is_k ,
output wire [15:0] pipe_rx5_data ,
output wire pipe_rx5_valid ,
output wire pipe_rx5_chanisaligned ,
output wire [ 2:0] pipe_rx5_status ,
output wire pipe_rx5_phy_status ,
output wire pipe_rx5_elec_idle ,
input wire pipe_rx5_polarity ,
input wire pipe_tx5_compliance ,
input wire [ 1:0] pipe_tx5_char_is_k ,
input wire [15:0] pipe_tx5_data ,
input wire pipe_tx5_elec_idle ,
input wire [ 1:0] pipe_tx5_powerdown ,
// Pipe Per-Lane Signals - Lane 6
output wire [ 1:0] pipe_rx6_char_is_k ,
output wire [15:0] pipe_rx6_data ,
output wire pipe_rx6_valid ,
output wire pipe_rx6_chanisaligned ,
output wire [ 2:0] pipe_rx6_status ,
output wire pipe_rx6_phy_status ,
output wire pipe_rx6_elec_idle ,
input wire pipe_rx6_polarity ,
input wire pipe_tx6_compliance ,
input wire [ 1:0] pipe_tx6_char_is_k ,
input wire [15:0] pipe_tx6_data ,
input wire pipe_tx6_elec_idle ,
input wire [ 1:0] pipe_tx6_powerdown ,
// Pipe Per-Lane Signals - Lane 7
output wire [ 1:0] pipe_rx7_char_is_k ,
output wire [15:0] pipe_rx7_data ,
output wire pipe_rx7_valid ,
output wire pipe_rx7_chanisaligned ,
output wire [ 2:0] pipe_rx7_status ,
output wire pipe_rx7_phy_status ,
output wire pipe_rx7_elec_idle ,
input wire pipe_rx7_polarity ,
input wire pipe_tx7_compliance ,
input wire [ 1:0] pipe_tx7_char_is_k ,
input wire [15:0] pipe_tx7_data ,
input wire pipe_tx7_elec_idle ,
input wire [ 1:0] pipe_tx7_powerdown ,
// PCI Express signals
output wire [ (LINK_CAP_MAX_LINK_WIDTH-1):0] pci_exp_txn ,
output wire [ (LINK_CAP_MAX_LINK_WIDTH-1):0] pci_exp_txp ,
input wire [ (LINK_CAP_MAX_LINK_WIDTH-1):0] pci_exp_rxn ,
input wire [ (LINK_CAP_MAX_LINK_WIDTH-1):0] pci_exp_rxp ,
// Non PIPE signals
input wire sys_clk ,
input wire sys_rst_n ,
input wire PIPE_MMCM_RST_N ,
input [3:0] i_tx_diff_ctr ,
output wire pipe_clk ,
output wire user_clk ,
output wire user_clk2 ,
output [15:0] o_rx_data,
output [1:0] o_rx_data_k,
output [1:0] o_rx_byte_is_comma,
output o_rx_byte_is_aligned,
output wire phy_rdy_n
);
parameter TCQ = 1; // clock to out delay model
localparam USERCLK2_FREQ = (USER_CLK2_DIV2 == "FALSE") ? USER_CLK_FREQ :
(USER_CLK_FREQ == 4) ? 3 :
(USER_CLK_FREQ == 3) ? 2 :
USER_CLK_FREQ;
localparam PCIE_LPM_DFE = (PL_FAST_TRAIN == "TRUE") ? "DFE" : "LPM";
//localparam PCIE_LPM_DFE = "DFE";
localparam PCIE_LINK_SPEED = (PL_FAST_TRAIN == "TRUE") ? 2 : 3;
// The parameter PCIE_OOBCLK_MODE_ENABLE value should be "0" for simulation and for synthesis it should be 1
//localparam PCIE_OOBCLK_MODE_ENABLE = (PL_FAST_TRAIN == "TRUE") ? 0 : 1;
localparam PCIE_OOBCLK_MODE_ENABLE = 1;
localparam PCIE_TX_EIDLE_ASSERT_DELAY = (PL_FAST_TRAIN == "TRUE") ? 3'b100 : 3'b010;
wire [ 7:0] gt_rx_phy_status_wire ;
wire [ 7:0] gt_rxchanisaligned_wire ;
wire [ 31:0] gt_rx_data_k_wire ;
wire [255:0] gt_rx_data_wire ;
wire [ 7:0] gt_rx_elec_idle_wire ;
wire [ 23:0] gt_rx_status_wire ;
wire [ 7:0] gt_rx_valid_wire ;
wire [ 7:0] gt_rx_polarity ;
wire [ 15:0] gt_power_down ;
wire [ 7:0] gt_tx_char_disp_mode ;
wire [ 31:0] gt_tx_data_k ;
wire [255:0] gt_tx_data ;
wire gt_tx_detect_rx_loopback ;
wire [ 7:0] gt_tx_elec_idle ;
wire [ 7:0] gt_rx_elec_idle_reset ;
wire [LINK_CAP_MAX_LINK_WIDTH-1:0] plllkdet ;
wire [LINK_CAP_MAX_LINK_WIDTH-1:0] phystatus_rst ;
wire clock_locked ;
wire [ 7:0] gt_rx_phy_status_wire_filter ;
wire [ 31:0] gt_rx_data_k_wire_filter ;
wire [255:0] gt_rx_data_wire_filter ;
wire [ 7:0] gt_rx_elec_idle_wire_filter ;
wire [ 23:0] gt_rx_status_wire_filter ;
wire [ 7:0] gt_rx_valid_wire_filter ;
wire pipe_clk_int;
reg phy_rdy_n_int;
reg reg_clock_locked;
wire all_phystatus_rst;
reg [5:0] pl_ltssm_state_q;
always @(posedge pipe_clk_int or negedge clock_locked) begin
if (!clock_locked)
pl_ltssm_state_q <= #TCQ 6'b0;
else
pl_ltssm_state_q <= #TCQ pl_ltssm_state;
end
assign pipe_clk = pipe_clk_int ;
wire plm_in_l0 = (pl_ltssm_state_q == 6'h16);
wire plm_in_rl = (pl_ltssm_state_q == 6'h1c);
wire plm_in_dt = (pl_ltssm_state_q == 6'h2d);
wire plm_in_rs = (pl_ltssm_state_q == 6'h1f);
//-------------RX FILTER Instantiation----------------------------------------------------------//
genvar i;
generate for (i=0; i<LINK_CAP_MAX_LINK_WIDTH; i=i+1)
begin : gt_rx_valid_filter
pcie_7x_v1_11_0_gt_rx_valid_filter_7x # (
.CLK_COR_MIN_LAT(28)
)
GT_RX_VALID_FILTER_7x_inst (
.USER_RXCHARISK ( gt_rx_data_k_wire [(2*i)+1 + (2*i):(2*i)+ (2*i)] ), //O
.USER_RXDATA ( gt_rx_data_wire [(16*i)+15+(16*i) :(16*i)+0 + (16*i)] ), //O
.USER_RXVALID ( gt_rx_valid_wire [i] ), //O
.USER_RXELECIDLE ( gt_rx_elec_idle_wire [i] ), //O
.USER_RX_STATUS ( gt_rx_status_wire [(3*i)+2:(3*i)] ), //O
.USER_RX_PHY_STATUS ( gt_rx_phy_status_wire [i] ), //O
.GT_RXCHARISK ( gt_rx_data_k_wire_filter [(2*i)+1+ (2*i):2*i+ (2*i)] ), //I
.GT_RXDATA ( gt_rx_data_wire_filter [(16*i)+15+(16*i) :(16*i)+0+(16*i)] ), //I
.GT_RXVALID ( gt_rx_valid_wire_filter [i] ), //I
.GT_RXELECIDLE ( gt_rx_elec_idle_wire_filter [i] ), //I
.GT_RX_STATUS ( gt_rx_status_wire_filter [(3*i)+2:(3*i)] ), //I
.GT_RX_PHY_STATUS ( gt_rx_phy_status_wire_filter [i] ),
.PLM_IN_L0 ( plm_in_l0 ), //I
.PLM_IN_RS ( plm_in_rs ), //I
.USER_CLK ( pipe_clk_int ), //I
.RESET ( phy_rdy_n_int ) //I
);
end
endgenerate
//---------- GT Instantiation ---------------------------------------------------------------
pcie_7x_v1_11_0_pipe_wrapper #
(
.PCIE_SIM_MODE ( PL_FAST_TRAIN ),
// synthesis translate_off
.PCIE_SIM_SPEEDUP ( "TRUE" ),
// synthesis translate_on
.PCIE_EXT_CLK ( PCIE_EXT_CLK ),
.PCIE_TXBUF_EN ( PCIE_TXBUF_EN ),
.PCIE_ASYNC_EN ( PCIE_ASYNC_EN ),
.PCIE_CHAN_BOND ( PCIE_CHAN_BOND ),
.PCIE_PLL_SEL ( PCIE_PLL_SEL ),
.PCIE_GT_DEVICE ( PCIE_GT_DEVICE ),
.PCIE_USE_MODE ( PCIE_USE_MODE ),
.PCIE_LANE ( LINK_CAP_MAX_LINK_WIDTH ),
.PCIE_LPM_DFE ( PCIE_LPM_DFE ),
.PCIE_LINK_SPEED ( PCIE_LINK_SPEED ),
.PCIE_TX_EIDLE_ASSERT_DELAY ( PCIE_TX_EIDLE_ASSERT_DELAY ),
.PCIE_OOBCLK_MODE ( PCIE_OOBCLK_MODE_ENABLE ),
.PCIE_REFCLK_FREQ ( REF_CLK_FREQ ),
.PCIE_USERCLK1_FREQ ( USER_CLK_FREQ +1 ),
.PCIE_USERCLK2_FREQ ( USERCLK2_FREQ +1 )
) pipe_wrapper_i (
//---------- PIPE Clock & Reset Ports ------------------
.PIPE_CLK ( sys_clk ),
.PIPE_RESET_N ( sys_rst_n ),
.PIPE_PCLK ( pipe_clk_int ),
//---------- PIPE TX Data Ports ------------------
.PIPE_TXDATA ( gt_tx_data[((32*LINK_CAP_MAX_LINK_WIDTH)-1):0] ),
.PIPE_TXDATAK ( gt_tx_data_k[((4*LINK_CAP_MAX_LINK_WIDTH)-1):0] ),
.PIPE_TXP ( pci_exp_txp[((LINK_CAP_MAX_LINK_WIDTH)-1):0] ),
.PIPE_TXN ( pci_exp_txn[((LINK_CAP_MAX_LINK_WIDTH)-1):0] ),
//---------- PIPE RX Data Ports ------------------
.PIPE_RXP ( pci_exp_rxp[((LINK_CAP_MAX_LINK_WIDTH)-1):0] ),
.PIPE_RXN ( pci_exp_rxn[((LINK_CAP_MAX_LINK_WIDTH)-1):0] ),
.PIPE_RXDATA ( gt_rx_data_wire_filter[((32*LINK_CAP_MAX_LINK_WIDTH)-1):0] ),
.PIPE_RXDATAK ( gt_rx_data_k_wire_filter[((4*LINK_CAP_MAX_LINK_WIDTH)-1):0] ),
//---------- PIPE Command Ports ------------------
.PIPE_TXDETECTRX ( gt_tx_detect_rx_loopback ),
.PIPE_TXELECIDLE ( gt_tx_elec_idle[((LINK_CAP_MAX_LINK_WIDTH)-1):0] ),
.PIPE_TXCOMPLIANCE ( gt_tx_char_disp_mode[((LINK_CAP_MAX_LINK_WIDTH)-1):0] ),
.PIPE_RXPOLARITY ( gt_rx_polarity[((LINK_CAP_MAX_LINK_WIDTH)-1):0] ),
.PIPE_POWERDOWN ( gt_power_down[((2*LINK_CAP_MAX_LINK_WIDTH)-1):0] ),
.PIPE_RATE ( {1'b0,pipe_tx_rate} ),
//---------- PIPE Electrical Command Ports ------------------
.PIPE_TXMARGIN ( pipe_tx_margin[2:0] ),
.PIPE_TXSWING ( pipe_tx_swing ),
.PIPE_TXDEEMPH ( {(LINK_CAP_MAX_LINK_WIDTH){pipe_tx_deemph}} ),
.PIPE_TXEQ_CONTROL ( {2*LINK_CAP_MAX_LINK_WIDTH{1'b0}} ),
.PIPE_TXEQ_PRESET ( {4*LINK_CAP_MAX_LINK_WIDTH{1'b0}} ),
.PIPE_TXEQ_PRESET_DEFAULT ( {4*LINK_CAP_MAX_LINK_WIDTH{1'b0}} ),
.PIPE_RXEQ_CONTROL ( {2*LINK_CAP_MAX_LINK_WIDTH{1'b0}} ),
.PIPE_RXEQ_PRESET ( {3*LINK_CAP_MAX_LINK_WIDTH{1'b0}} ),
.PIPE_RXEQ_LFFS ( {6*LINK_CAP_MAX_LINK_WIDTH{1'b0}} ),
.PIPE_RXEQ_TXPRESET ( {4*LINK_CAP_MAX_LINK_WIDTH{1'b0}} ),
.PIPE_RXEQ_USER_EN ( {1*LINK_CAP_MAX_LINK_WIDTH{1'b0}} ),
.PIPE_RXEQ_USER_TXCOEFF ( {18*LINK_CAP_MAX_LINK_WIDTH{1'b0}} ),
.PIPE_RXEQ_USER_MODE ( {1*LINK_CAP_MAX_LINK_WIDTH{1'b0}} ),
.PIPE_TXEQ_COEFF ( ),
.PIPE_TXEQ_DEEMPH ( {6*LINK_CAP_MAX_LINK_WIDTH{1'b0}} ),
.PIPE_TXEQ_FS ( ),
.PIPE_TXEQ_LF ( ),
.PIPE_TXEQ_DONE ( ),
.PIPE_RXEQ_NEW_TXCOEFF ( ),
.PIPE_RXEQ_LFFS_SEL ( ),
.PIPE_RXEQ_ADAPT_DONE ( ),
.PIPE_RXEQ_DONE ( ),
//---------- PIPE Status Ports -------------------
.PIPE_RXVALID ( gt_rx_valid_wire_filter[((LINK_CAP_MAX_LINK_WIDTH)-1):0] ),
.PIPE_PHYSTATUS ( gt_rx_phy_status_wire_filter[((LINK_CAP_MAX_LINK_WIDTH)-1):0] ),
.PIPE_PHYSTATUS_RST ( phystatus_rst ),
.PIPE_RXELECIDLE ( gt_rx_elec_idle_wire_filter[((LINK_CAP_MAX_LINK_WIDTH)-1):0] ),
.PIPE_RXSTATUS ( gt_rx_status_wire_filter[((3*LINK_CAP_MAX_LINK_WIDTH)-1):0] ),
.PIPE_RXBUFSTATUS ( ),
//---------- PIPE User Ports ---------------------------
.PIPE_MMCM_RST_N ( PIPE_MMCM_RST_N ), // Async | Async
.PIPE_RXSLIDE ( {1*LINK_CAP_MAX_LINK_WIDTH{1'b0}} ),
.PIPE_CPLL_LOCK ( plllkdet ),
.PIPE_QPLL_LOCK ( ),
.PIPE_PCLK_LOCK ( clock_locked ),
.PIPE_RXCDRLOCK ( ),
.PIPE_USERCLK1 ( user_clk ),
.PIPE_USERCLK2 ( user_clk2 ),
.PIPE_RXUSRCLK ( ),
.PIPE_RXOUTCLK ( ),
.PIPE_TXSYNC_DONE ( ),
.PIPE_RXSYNC_DONE ( ),
.PIPE_GEN3_RDY ( ),
.PIPE_RXCHANISALIGNED ( gt_rxchanisaligned_wire[LINK_CAP_MAX_LINK_WIDTH-1:0] ),
.PIPE_ACTIVE_LANE ( ),
.i_tx_diff_ctr (i_tx_diff_ctr),
.o_rx_byte_is_comma (o_rx_byte_is_comma),
.o_rx_byte_is_aligned (o_rx_byte_is_aligned),
//---------- External Clock Ports ---------------------------
.PIPE_PCLK_IN ( PIPE_PCLK_IN ),
.PIPE_RXUSRCLK_IN ( PIPE_RXUSRCLK_IN ),
.PIPE_RXOUTCLK_IN ( PIPE_RXOUTCLK_IN ),
.PIPE_DCLK_IN ( PIPE_DCLK_IN ),
.PIPE_USERCLK1_IN ( PIPE_USERCLK1_IN ),
.PIPE_USERCLK2_IN ( PIPE_USERCLK2_IN ),
.PIPE_OOBCLK_IN ( PIPE_OOBCLK_IN ),
.PIPE_JTAG_EN ( 1'b0 ),
.PIPE_JTAG_RDY ( ),
.PIPE_MMCM_LOCK_IN ( PIPE_MMCM_LOCK_IN ),
.PIPE_TXOUTCLK_OUT ( PIPE_TXOUTCLK_OUT ),
.PIPE_RXOUTCLK_OUT ( PIPE_RXOUTCLK_OUT ),
.PIPE_PCLK_SEL_OUT ( PIPE_PCLK_SEL_OUT ),
.PIPE_GEN3_OUT ( PIPE_GEN3_OUT ),
//---------- PRBS/Loopback Ports ---------------------------
.PIPE_TXPRBSSEL ( 3'b0 ),
.PIPE_RXPRBSSEL ( 3'b0 ),
.PIPE_TXPRBSFORCEERR ( 1'b0 ),
.PIPE_RXPRBSCNTRESET ( 1'b0 ),
.PIPE_LOOPBACK ( 3'b0 ),
.PIPE_RXPRBSERR ( ),
//---------- FSM Ports ---------------------------
.PIPE_RST_FSM ( ),
.PIPE_QRST_FSM ( ),
.PIPE_RATE_FSM ( ),
.PIPE_SYNC_FSM_TX ( ),
.PIPE_SYNC_FSM_RX ( ),
.PIPE_DRP_FSM ( ),
.PIPE_TXEQ_FSM ( ),
.PIPE_RXEQ_FSM ( ),
.PIPE_QDRP_FSM ( ),
.PIPE_RST_IDLE ( ),
.PIPE_QRST_IDLE ( ),
.PIPE_RATE_IDLE ( ),
//---------- DEBUG Ports ---------------------------
.PIPE_DEBUG_0 ( ),
.PIPE_DEBUG_1 ( ),
.PIPE_DEBUG_2 ( ),
.PIPE_DEBUG_3 ( ),
.PIPE_DEBUG_4 ( ),
.PIPE_DEBUG_5 ( ),
.PIPE_DEBUG_6 ( ),
.PIPE_DEBUG_7 ( ),
.PIPE_DEBUG_8 ( ),
.PIPE_DEBUG_9 ( ),
.PIPE_DEBUG ( ),
.PIPE_DMONITOROUT ( )
);
assign pipe_rx0_phy_status = gt_rx_phy_status_wire[0] ;
assign pipe_rx1_phy_status = (LINK_CAP_MAX_LINK_WIDTH >= 2 ) ? gt_rx_phy_status_wire[1] : 1'b0;
assign pipe_rx2_phy_status = (LINK_CAP_MAX_LINK_WIDTH >= 4 ) ? gt_rx_phy_status_wire[2] : 1'b0;
assign pipe_rx3_phy_status = (LINK_CAP_MAX_LINK_WIDTH >= 4 ) ? gt_rx_phy_status_wire[3] : 1'b0;
assign pipe_rx4_phy_status = (LINK_CAP_MAX_LINK_WIDTH >= 8 ) ? gt_rx_phy_status_wire[4] : 1'b0;
assign pipe_rx5_phy_status = (LINK_CAP_MAX_LINK_WIDTH >= 8 ) ? gt_rx_phy_status_wire[5] : 1'b0;
assign pipe_rx6_phy_status = (LINK_CAP_MAX_LINK_WIDTH >= 8 ) ? gt_rx_phy_status_wire[6] : 1'b0;
assign pipe_rx7_phy_status = (LINK_CAP_MAX_LINK_WIDTH >= 8 ) ? gt_rx_phy_status_wire[7] : 1'b0;
assign pipe_rx0_chanisaligned = gt_rxchanisaligned_wire[0];
assign pipe_rx1_chanisaligned = (LINK_CAP_MAX_LINK_WIDTH >= 2 ) ? gt_rxchanisaligned_wire[1] : 1'b0 ;
assign pipe_rx2_chanisaligned = (LINK_CAP_MAX_LINK_WIDTH >= 4 ) ? gt_rxchanisaligned_wire[2] : 1'b0 ;
assign pipe_rx3_chanisaligned = (LINK_CAP_MAX_LINK_WIDTH >= 4 ) ? gt_rxchanisaligned_wire[3] : 1'b0 ;
assign pipe_rx4_chanisaligned = (LINK_CAP_MAX_LINK_WIDTH >= 8 ) ? gt_rxchanisaligned_wire[4] : 1'b0 ;
assign pipe_rx5_chanisaligned = (LINK_CAP_MAX_LINK_WIDTH >= 8 ) ? gt_rxchanisaligned_wire[5] : 1'b0 ;
assign pipe_rx6_chanisaligned = (LINK_CAP_MAX_LINK_WIDTH >= 8 ) ? gt_rxchanisaligned_wire[6] : 1'b0 ;
assign pipe_rx7_chanisaligned = (LINK_CAP_MAX_LINK_WIDTH >= 8 ) ? gt_rxchanisaligned_wire[7] : 1'b0 ;
//<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
//<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
assign pipe_rx0_char_is_k = {gt_rx_data_k_wire[1], gt_rx_data_k_wire[0]};
assign pipe_rx1_char_is_k = (LINK_CAP_MAX_LINK_WIDTH >= 2 ) ? {gt_rx_data_k_wire[5], gt_rx_data_k_wire[4]} : 2'b0 ;
assign pipe_rx2_char_is_k = (LINK_CAP_MAX_LINK_WIDTH >= 4 ) ? {gt_rx_data_k_wire[9], gt_rx_data_k_wire[8]} : 2'b0 ;
assign pipe_rx3_char_is_k = (LINK_CAP_MAX_LINK_WIDTH >= 4 ) ? {gt_rx_data_k_wire[13], gt_rx_data_k_wire[12]} : 2'b0 ;
assign pipe_rx4_char_is_k = (LINK_CAP_MAX_LINK_WIDTH >= 8 ) ? {gt_rx_data_k_wire[17], gt_rx_data_k_wire[16]} : 2'b0 ;
assign pipe_rx5_char_is_k = (LINK_CAP_MAX_LINK_WIDTH >= 8 ) ? {gt_rx_data_k_wire[21], gt_rx_data_k_wire[20]} : 2'b0 ;
assign pipe_rx6_char_is_k = (LINK_CAP_MAX_LINK_WIDTH >= 8 ) ? {gt_rx_data_k_wire[25], gt_rx_data_k_wire[24]} : 2'b0 ;
assign pipe_rx7_char_is_k = (LINK_CAP_MAX_LINK_WIDTH >= 8 ) ? {gt_rx_data_k_wire[29], gt_rx_data_k_wire[28]} : 2'b0 ;
assign pipe_rx0_data = {gt_rx_data_wire[ 15: 8], gt_rx_data_wire[ 7: 0]};
assign pipe_rx1_data = (LINK_CAP_MAX_LINK_WIDTH >= 2 ) ? {gt_rx_data_wire[47:40], gt_rx_data_wire[39:32]} : 16'h0 ;
assign pipe_rx2_data = (LINK_CAP_MAX_LINK_WIDTH >= 4 ) ? {gt_rx_data_wire[79:72], gt_rx_data_wire[71:64]} : 16'h0 ;
assign pipe_rx3_data = (LINK_CAP_MAX_LINK_WIDTH >= 4 ) ? {gt_rx_data_wire[111:104], gt_rx_data_wire[103:96]} : 16'h0 ;
assign pipe_rx4_data = (LINK_CAP_MAX_LINK_WIDTH >= 8 ) ? {gt_rx_data_wire[143:136], gt_rx_data_wire[135:128]} : 16'h0 ;
assign pipe_rx5_data = (LINK_CAP_MAX_LINK_WIDTH >= 8 ) ? {gt_rx_data_wire[175:168], gt_rx_data_wire[167:160]} : 16'h0 ;
assign pipe_rx6_data = (LINK_CAP_MAX_LINK_WIDTH >= 8 ) ? {gt_rx_data_wire[207:200], gt_rx_data_wire[199:192]} : 16'h0 ;
assign pipe_rx7_data = (LINK_CAP_MAX_LINK_WIDTH >= 8 ) ? {gt_rx_data_wire[239:232], gt_rx_data_wire[231:224]} : 16'h0 ;
assign pipe_rx0_status = gt_rx_status_wire[ 2: 0];
assign pipe_rx1_status = (LINK_CAP_MAX_LINK_WIDTH >= 2 ) ? gt_rx_status_wire[ 5: 3] : 3'b0 ;
assign pipe_rx2_status = (LINK_CAP_MAX_LINK_WIDTH >= 4 ) ? gt_rx_status_wire[ 8: 6] : 3'b0 ;
assign pipe_rx3_status = (LINK_CAP_MAX_LINK_WIDTH >= 4 ) ? gt_rx_status_wire[11: 9] : 3'b0 ;
assign pipe_rx4_status = (LINK_CAP_MAX_LINK_WIDTH >= 8 ) ? gt_rx_status_wire[14:12] : 3'b0 ;
assign pipe_rx5_status = (LINK_CAP_MAX_LINK_WIDTH >= 8 ) ? gt_rx_status_wire[17:15] : 3'b0 ;
assign pipe_rx6_status = (LINK_CAP_MAX_LINK_WIDTH >= 8 ) ? gt_rx_status_wire[20:18] : 3'b0 ;
assign pipe_rx7_status = (LINK_CAP_MAX_LINK_WIDTH >= 8 ) ? gt_rx_status_wire[23:21] : 3'b0 ;
//<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
//<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
assign pipe_rx0_elec_idle = gt_rx_elec_idle_wire[0];
assign pipe_rx1_elec_idle = (LINK_CAP_MAX_LINK_WIDTH >= 2 ) ? gt_rx_elec_idle_wire[1] : 1'b1 ;
assign pipe_rx2_elec_idle = (LINK_CAP_MAX_LINK_WIDTH >= 4 ) ? gt_rx_elec_idle_wire[2] : 1'b1 ;
assign pipe_rx3_elec_idle = (LINK_CAP_MAX_LINK_WIDTH >= 4 ) ? gt_rx_elec_idle_wire[3] : 1'b1 ;
assign pipe_rx4_elec_idle = (LINK_CAP_MAX_LINK_WIDTH >= 8 ) ? gt_rx_elec_idle_wire[4] : 1'b1 ;
assign pipe_rx5_elec_idle = (LINK_CAP_MAX_LINK_WIDTH >= 8 ) ? gt_rx_elec_idle_wire[5] : 1'b1 ;
assign pipe_rx6_elec_idle = (LINK_CAP_MAX_LINK_WIDTH >= 8 ) ? gt_rx_elec_idle_wire[6] : 1'b1 ;
assign pipe_rx7_elec_idle = (LINK_CAP_MAX_LINK_WIDTH >= 8 ) ? gt_rx_elec_idle_wire[7] : 1'b1 ;
assign pipe_rx0_valid = gt_rx_valid_wire[0];
assign pipe_rx1_valid = (LINK_CAP_MAX_LINK_WIDTH >= 2 ) ? gt_rx_valid_wire[1] : 1'b0 ;
assign pipe_rx2_valid = (LINK_CAP_MAX_LINK_WIDTH >= 4 ) ? gt_rx_valid_wire[2] : 1'b0 ;
assign pipe_rx3_valid = (LINK_CAP_MAX_LINK_WIDTH >= 4 ) ? gt_rx_valid_wire[3] : 1'b0 ;
assign pipe_rx4_valid = (LINK_CAP_MAX_LINK_WIDTH >= 8 ) ? gt_rx_valid_wire[4] : 1'b0 ;
assign pipe_rx5_valid = (LINK_CAP_MAX_LINK_WIDTH >= 8 ) ? gt_rx_valid_wire[5] : 1'b0 ;
assign pipe_rx6_valid = (LINK_CAP_MAX_LINK_WIDTH >= 8 ) ? gt_rx_valid_wire[6] : 1'b0 ;
assign pipe_rx7_valid = (LINK_CAP_MAX_LINK_WIDTH >= 8 ) ? gt_rx_valid_wire[7] : 1'b0 ;
assign gt_rx_polarity[0] = pipe_rx0_polarity;
assign gt_rx_polarity[1] = pipe_rx1_polarity;
assign gt_rx_polarity[2] = pipe_rx2_polarity;
assign gt_rx_polarity[3] = pipe_rx3_polarity;
assign gt_rx_polarity[4] = pipe_rx4_polarity;
assign gt_rx_polarity[5] = pipe_rx5_polarity;
assign gt_rx_polarity[6] = pipe_rx6_polarity;
assign gt_rx_polarity[7] = pipe_rx7_polarity;
assign gt_power_down[ 1: 0] = pipe_tx0_powerdown;
assign gt_power_down[ 3: 2] = pipe_tx1_powerdown;
assign gt_power_down[ 5: 4] = pipe_tx2_powerdown;
assign gt_power_down[ 7: 6] = pipe_tx3_powerdown;
assign gt_power_down[ 9: 8] = pipe_tx4_powerdown;
assign gt_power_down[11:10] = pipe_tx5_powerdown;
assign gt_power_down[13:12] = pipe_tx6_powerdown;
assign gt_power_down[15:14] = pipe_tx7_powerdown;
assign gt_tx_char_disp_mode = {pipe_tx7_compliance,
pipe_tx6_compliance,
pipe_tx5_compliance,
pipe_tx4_compliance,
pipe_tx3_compliance,
pipe_tx2_compliance,
pipe_tx1_compliance,
pipe_tx0_compliance};
assign gt_tx_data_k = {2'd0,
pipe_tx7_char_is_k,
2'd0,
pipe_tx6_char_is_k,
2'd0,
pipe_tx5_char_is_k,
2'd0,
pipe_tx4_char_is_k,
2'd0,
pipe_tx3_char_is_k,
2'd0,
pipe_tx2_char_is_k,
2'd0,
pipe_tx1_char_is_k,
2'd0,
pipe_tx0_char_is_k};
assign gt_tx_data = {16'd0,
pipe_tx7_data,
16'd0,
pipe_tx6_data,
16'd0,
pipe_tx5_data,
16'd0,
pipe_tx4_data,
16'd0,
pipe_tx3_data,
16'd0,
pipe_tx2_data,
16'd0,
pipe_tx1_data,
16'd0,
pipe_tx0_data};
assign gt_tx_detect_rx_loopback = pipe_tx_rcvr_det;
assign gt_tx_elec_idle = {pipe_tx7_elec_idle,
pipe_tx6_elec_idle,
pipe_tx5_elec_idle,
pipe_tx4_elec_idle,
pipe_tx3_elec_idle,
pipe_tx2_elec_idle,
pipe_tx1_elec_idle,
pipe_tx0_elec_idle};
always @(posedge pipe_clk_int or negedge clock_locked) begin
if (!clock_locked)
reg_clock_locked <= #TCQ 1'b0;
else
reg_clock_locked <= #TCQ 1'b1;
end
always @(posedge pipe_clk_int) begin
if (!reg_clock_locked)
phy_rdy_n_int <= #TCQ 1'b0;
else
phy_rdy_n_int <= #TCQ all_phystatus_rst;
end
assign all_phystatus_rst = (&phystatus_rst[LINK_CAP_MAX_LINK_WIDTH-1:0]);
assign phy_rdy_n = phy_rdy_n_int;
assign o_rx_data = gt_rx_data_wire_filter[15:0];
assign o_rx_data_k = gt_rx_data_k_wire_filter[1:0];
endmodule
|
(* FASM_PARAMS="INV.TA1=TAS1;INV.TA2=TAS2;INV.TB1=TBS1;INV.TB2=TBS2;INV.BA1=BAS1;INV.BA2=BAS2;INV.BB1=BBS1;INV.BB2=BBS2" *)
(* whitebox *)
module C_FRAG (TBS, TAB, TSL, TA1, TA2, TB1, TB2, BAB, BSL, BA1, BA2, BB1, BB2, TZ, CZ);
// Routing ports
input wire TBS;
input wire TAB;
input wire TSL;
input wire TA1;
input wire TA2;
input wire TB1;
input wire TB2;
input wire BAB;
input wire BSL;
input wire BA1;
input wire BA2;
input wire BB1;
input wire BB2;
(* DELAY_CONST_TAB="{iopath_TAB_TZ}" *)
(* DELAY_CONST_TSL="{iopath_TSL_TZ}" *)
(* DELAY_CONST_TA1="{iopath_TA1_TZ}" *)
(* DELAY_CONST_TA2="{iopath_TA2_TZ}" *)
(* DELAY_CONST_TB1="{iopath_TB1_TZ}" *)
(* DELAY_CONST_TB2="{iopath_TB2_TZ}" *)
output wire TZ;
(* DELAY_CONST_TBS="{iopath_TBS_CZ}" *)
(* DELAY_CONST_TAB="{iopath_TAB_CZ}" *)
(* DELAY_CONST_TSL="{iopath_TSL_CZ}" *)
(* DELAY_CONST_TA1="{iopath_TA1_CZ}" *)
(* DELAY_CONST_TA2="{iopath_TA2_CZ}" *)
(* DELAY_CONST_TB1="{iopath_TB1_CZ}" *)
(* DELAY_CONST_TB2="{iopath_TB2_CZ}" *)
(* DELAY_CONST_BAB="{iopath_BAB_CZ}" *)
(* DELAY_CONST_BSL="{iopath_BSL_CZ}" *)
(* DELAY_CONST_BA1="{iopath_BA1_CZ}" *)
(* DELAY_CONST_BA2="{iopath_BA2_CZ}" *)
(* DELAY_CONST_BB1="{iopath_BB1_CZ}" *)
(* DELAY_CONST_BB2="{iopath_BB2_CZ}" *)
output wire CZ;
// Control parameters
parameter [0:0] TAS1 = 1'b0;
parameter [0:0] TAS2 = 1'b0;
parameter [0:0] TBS1 = 1'b0;
parameter [0:0] TBS2 = 1'b0;
parameter [0:0] BAS1 = 1'b0;
parameter [0:0] BAS2 = 1'b0;
parameter [0:0] BBS1 = 1'b0;
parameter [0:0] BBS2 = 1'b0;
// Input routing inverters
wire TAP1 = (TAS1) ? ~TA1 : TA1;
wire TAP2 = (TAS2) ? ~TA2 : TA2;
wire TBP1 = (TBS1) ? ~TB1 : TB1;
wire TBP2 = (TBS2) ? ~TB2 : TB2;
wire BAP1 = (BAS1) ? ~BA1 : BA1;
wire BAP2 = (BAS2) ? ~BA2 : BA2;
wire BBP1 = (BBS1) ? ~BB1 : BB1;
wire BBP2 = (BBS2) ? ~BB2 : BB2;
// 1st mux stage
wire TAI = TSL ? TAP2 : TAP1;
wire TBI = TSL ? TBP2 : TBP1;
wire BAI = BSL ? BAP2 : BAP1;
wire BBI = BSL ? BBP2 : BBP1;
// 2nd mux stage
wire TZI = TAB ? TBI : TAI;
wire BZI = BAB ? BBI : BAI;
// 3rd mux stage
wire CZI = TBS ? BZI : TZI;
// Output
assign TZ = TZI;
assign CZ = CZI;
specify
(TBS => CZ) = (0,0);
(TAB => CZ) = (0,0);
(TSL => CZ) = (0,0);
(TA1 => CZ) = (0,0);
(TA2 => CZ) = (0,0);
(TB1 => CZ) = (0,0);
(TB2 => CZ) = (0,0);
(BAB => CZ) = (0,0);
(BSL => CZ) = (0,0);
(BA1 => CZ) = (0,0);
(BA2 => CZ) = (0,0);
(BB1 => CZ) = (0,0);
(BB2 => CZ) = (0,0);
(TAB => TZ) = (0,0);
(TSL => TZ) = (0,0);
(TA1 => TZ) = (0,0);
(TA2 => TZ) = (0,0);
(TB1 => TZ) = (0,0);
(TB2 => TZ) = (0,0);
endspecify
endmodule
|
(** * Hoare: Hoare Logic, Part I *)
Require Export Imp.
(** In the past couple of chapters, we've begun applying the
mathematical tools developed in the first part of the course to
studying the theory of a small programming language, Imp.
- We defined a type of _abstract syntax trees_ for Imp, together
with an _evaluation relation_ (a partial function on states)
that specifies the _operational semantics_ of programs.
The language we defined, though small, captures some of the key
features of full-blown languages like C, C++, and Java,
including the fundamental notion of mutable state and some
common control structures.
- We proved a number of _metatheoretic properties_ -- "meta" in
the sense that they are properties of the language as a whole,
rather than properties of particular programs in the language.
These included:
- determinism of evaluation
- equivalence of some different ways of writing down the
definitions (e.g. functional and relational definitions of
arithmetic expression evaluation)
- guaranteed termination of certain classes of programs
- correctness (in the sense of preserving meaning) of a number
of useful program transformations
- behavioral equivalence of programs (in the [Equiv] chapter).
If we stopped here, we would already have something useful: a set
of tools for defining and discussing programming languages and
language features that are mathematically precise, flexible, and
easy to work with, applied to a set of key properties. All of
these properties are things that language designers, compiler
writers, and users might care about knowing. Indeed, many of them
are so fundamental to our understanding of the programming
languages we deal with that we might not consciously recognize
them as "theorems." But properties that seem intuitively obvious
can sometimes be quite subtle (in some cases, even subtly wrong!).
We'll return to the theme of metatheoretic properties of whole
languages later in the course when we discuss _types_ and _type
soundness_. In this chapter, though, we'll turn to a different
set of issues.
Our goal is to see how to carry out some simple examples of
_program verification_ -- i.e., using the precise definition of
Imp to prove formally that particular programs satisfy particular
specifications of their behavior. We'll develop a reasoning system
called _Floyd-Hoare Logic_ -- often shortened to just _Hoare
Logic_ -- in which each of the syntactic constructs of Imp is
equipped with a single, generic "proof rule" that can be used to
reason compositionally about the correctness of programs involving
this construct.
Hoare Logic originates in the 1960s, and it continues to be the
subject of intensive research right up to the present day. It
lies at the core of a multitude of tools that are being used in
academia and industry to specify and verify real software
systems. *)
(* ####################################################### *)
(** * Hoare Logic *)
(** Hoare Logic combines two beautiful ideas: a natural way of
writing down _specifications_ of programs, and a _compositional
proof technique_ for proving that programs are correct with
respect to such specifications -- where by "compositional" we mean
that the structure of proofs directly mirrors the structure of the
programs that they are about. *)
(* ####################################################### *)
(** ** Assertions *)
(** To talk about specifications of programs, the first thing we
need is a way of making _assertions_ about properties that hold at
particular points during a program's execution -- i.e., claims
about the current state of the memory when program execution
reaches that point. Formally, an assertion is just a family of
propositions indexed by a [state]. *)
Definition Assertion := state -> Prop.
(** **** Exercise: 1 star, optional (assertions) *)
Module ExAssertions.
(** Paraphrase the following assertions in English. *)
Definition as1 : Assertion := fun st => st X = 3.
Definition as2 : Assertion := fun st => st X <= st Y.
Definition as3 : Assertion :=
fun st => st X = 3 \/ st X <= st Y.
Definition as4 : Assertion :=
fun st => st Z * st Z <= st X /\
~ (((S (st Z)) * (S (st Z))) <= st X).
Definition as5 : Assertion := fun st => True.
Definition as6 : Assertion := fun st => False.
(*
as1 : X equal to three in any state
as2 : X less than Y in any state
as3 : X equal to 3 and X not more than Y in any state
as4 : the square of Z not more than X, and the square of (Z+1) is more than X in any state
as5 : forall state there is Ture
as6 : forall state there is False
FILL IN HERE *)
End ExAssertions.
(** [] *)
(** This way of writing assertions can be a little bit heavy,
for two reasons: (1) every single assertion that we ever write is
going to begin with [fun st => ]; and (2) this state [st] is the
only one that we ever use to look up variables (we will never need
to talk about two different memory states at the same time). For
discussing examples informally, we'll adopt some simplifying
conventions: we'll drop the initial [fun st =>], and we'll write
just [X] to mean [st X]. Thus, instead of writing *)
(**
fun st => (st Z) * (st Z) <= m /\
~ ((S (st Z)) * (S (st Z)) <= m)
we'll write just
Z * Z <= m /\ ~((S Z) * (S Z) <= m).
*)
(** Given two assertions [P] and [Q], we say that [P] _implies_ [Q],
written [P ->> Q] (in ASCII, [P -][>][> Q]), if, whenever [P]
holds in some state [st], [Q] also holds. *)
Definition assert_implies (P Q : Assertion) : Prop :=
forall st, P st -> Q st.
Notation "P ->> Q" :=
(assert_implies P Q) (at level 80) : hoare_spec_scope.
Open Scope hoare_spec_scope.
(** We'll also have occasion to use the "iff" variant of implication
between assertions: *)
Notation "P <<->> Q" :=
(P ->> Q /\ Q ->> P) (at level 80) : hoare_spec_scope.
(* ####################################################### *)
(** ** Hoare Triples *)
(** Next, we need a way of making formal claims about the
behavior of commands. *)
(** Since the behavior of a command is to transform one state to
another, it is natural to express claims about commands in terms
of assertions that are true before and after the command executes:
- "If command [c] is started in a state satisfying assertion
[P], and if [c] eventually terminates in some final state,
then this final state will satisfy the assertion [Q]."
Such a claim is called a _Hoare Triple_. The property [P] is
called the _precondition_ of [c], while [Q] is the
_postcondition_. Formally: *)
Definition hoare_triple
(P:Assertion) (c:com) (Q:Assertion) : Prop :=
forall st st',
c / st || st' ->
P st ->
Q st'.
(** Since we'll be working a lot with Hoare triples, it's useful to
have a compact notation:
{{P}} c {{Q}}.
*)
(** (The traditional notation is [{P} c {Q}], but single braces
are already used for other things in Coq.) *)
Notation "{{ P }} c {{ Q }}" :=
(hoare_triple P c Q) (at level 90, c at next level)
: hoare_spec_scope.
(** (The [hoare_spec_scope] annotation here tells Coq that this
notation is not global but is intended to be used in particular
contexts. The [Open Scope] tells Coq that this file is one such
context.) *)
(** **** Exercise: 1 star, optional (triples) *)
(** Paraphrase the following Hoare triples in English.
1) {{True}} c {{X = 5}}
2) {{X = m}} c {{X = m + 5)}}
3) {{X <= Y}} c {{Y <= X}}
4) {{True}} c {{False}}
5) {{X = m}}
c
{{Y = real_fact m}}.
6) {{True}}
c
{{(Z * Z) <= m /\ ~ (((S Z) * (S Z)) <= m)}}
*)
(**
1)after the command c executes, X is equal to 5
2)if X is equal to m before c executes,
then X will equal to (m+5) after c executes.
3)if X is not more than Y before c executes,
then Y will not more than X after c executes.
4)after c executes any asssrtions will not be satisfied.
5)if X is equal to m before c executes,
then Y will equal to (real_fact m)
6)after c executes the square of z is not more than m,
and the square of (z+1) is more than m.
*)
(** **** Exercise: 1 star, optional (valid_triples) *)
(** Which of the following Hoare triples are _valid_ -- i.e., the
claimed relation between [P], [c], and [Q] is true?
1) {{True}} X ::= 5 {{X = 5}}
2) {{X = 2}} X ::= X + 1 {{X = 3}}
3) {{True}} X ::= 5; Y ::= 0 {{X = 5}}
4) {{X = 2 /\ X = 3}} X ::= 5 {{X = 0}}
5) {{True}} SKIP {{False}}
6) {{False}} SKIP {{True}}
7) {{True}} WHILE True DO SKIP END {{False}}
8) {{X = 0}}
WHILE X == 0 DO X ::= X + 1 END
{{X = 1}}
9) {{X = 1}}
WHILE X <> 0 DO X ::= X + 1 END
{{X = 100}}
*)
(* FILL IN HERE *)
(**
valid:
1,2,3,4,6,8
*)
(** (Note that we're using informal mathematical notations for
expressions inside of commands, for readability, rather than their
formal [aexp] and [bexp] encodings. We'll continue doing so
throughout the chapter.) *)
(** To get us warmed up for what's coming, here are two simple
facts about Hoare triples. *)
Theorem hoare_post_true : forall (P Q : Assertion) c,
(forall st, Q st) ->
{{P}} c {{Q}}.
Proof.
intros P Q c H. unfold hoare_triple.
intros st st' Heval HP.
apply H. Qed.
Theorem hoare_pre_false : forall (P Q : Assertion) c,
(forall st, ~(P st)) ->
{{P}} c {{Q}}.
Proof.
intros P Q c H. unfold hoare_triple.
intros st st' Heval HP.
unfold not in H. apply H in HP.
inversion HP. Qed.
(* ####################################################### *)
(** ** Proof Rules *)
(** The goal of Hoare logic is to provide a _compositional_
method for proving the validity of Hoare triples. That is, the
structure of a program's correctness proof should mirror the
structure of the program itself. To this end, in the sections
below, we'll introduce one rule for reasoning about each of the
different syntactic forms of commands in Imp -- one for
assignment, one for sequencing, one for conditionals, etc. -- plus
a couple of "structural" rules that are useful for gluing things
together. We will prove programs correct using these proof rules,
without ever unfolding the definition of [hoare_triple]. *)
(* ####################################################### *)
(** *** Assignment *)
(** The rule for assignment is the most fundamental of the Hoare logic
proof rules. Here's how it works.
Consider this (valid) Hoare triple:
{{ Y = 1 }} X ::= Y {{ X = 1 }}
In English: if we start out in a state where the value of [Y]
is [1] and we assign [Y] to [X], then we'll finish in a
state where [X] is [1]. That is, the property of being equal
to [1] gets transferred from [Y] to [X].
Similarly, in
{{ Y + Z = 1 }} X ::= Y + Z {{ X = 1 }}
the same property (being equal to one) gets transferred to
[X] from the expression [Y + Z] on the right-hand side of
the assignment.
More generally, if [a] is _any_ arithmetic expression, then
{{ a = 1 }} X ::= a {{ X = 1 }}
is a valid Hoare triple.
This can be made even more general. To conclude that an
_arbitrary_ property [Q] holds after [X ::= a], we need to assume
that [Q] holds before [X ::= a], but _with all occurrences of_ [X]
replaced by [a] in [Q]. This leads to the Hoare rule for
assignment
{{ Q [X |-> a] }} X ::= a {{ Q }}
where "[Q [X |-> a]]" is pronounced "[Q] where [a] is substituted
for [X]".
For example, these are valid applications of the assignment
rule:
{{ (X <= 5) [X |-> X + 1]
i.e., X + 1 <= 5 }}
X ::= X + 1
{{ X <= 5 }}
{{ (X = 3) [X |-> 3]
i.e., 3 = 3}}
X ::= 3
{{ X = 3 }}
{{ (0 <= X /\ X <= 5) [X |-> 3]
i.e., (0 <= 3 /\ 3 <= 5)}}
X ::= 3
{{ 0 <= X /\ X <= 5 }}
*)
(** To formalize the rule, we must first formalize the idea of
"substituting an expression for an Imp variable in an assertion."
That is, given a proposition [P], a variable [X], and an
arithmetic expression [a], we want to derive another proposition
[P'] that is just the same as [P] except that, wherever [P]
mentions [X], [P'] should instead mention [a].
Since [P] is an arbitrary Coq proposition, we can't directly
"edit" its text. Instead, we can achieve the effect we want by
evaluating [P] in an updated state: *)
Definition assn_sub X a P : Assertion :=
fun (st : state) =>
P (update st X (aeval st a)).
Notation "P [ X |-> a ]" := (assn_sub X a P) (at level 10).
(** That is, [P [X |-> a]] is an assertion [P'] that is just like [P]
except that, wherever [P] looks up the variable [X] in the current
state, [P'] instead uses the value of the expression [a].
To see how this works, let's calculate what happens with a couple
of examples. First, suppose [P'] is [(X <= 5) [X |-> 3]] -- that
is, more formally, [P'] is the Coq expression
fun st =>
(fun st' => st' X <= 5)
(update st X (aeval st (ANum 3))),
which simplifies to
fun st =>
(fun st' => st' X <= 5)
(update st X 3)
and further simplifies to
fun st =>
((update st X 3) X) <= 5)
and by further simplification to
fun st =>
(3 <= 5).
That is, [P'] is the assertion that [3] is less than or equal to
[5] (as expected).
For a more interesting example, suppose [P'] is [(X <= 5) [X |->
X+1]]. Formally, [P'] is the Coq expression
fun st =>
(fun st' => st' X <= 5)
(update st X (aeval st (APlus (AId X) (ANum 1)))),
which simplifies to
fun st =>
(((update st X (aeval st (APlus (AId X) (ANum 1))))) X) <= 5
and further simplifies to
fun st =>
(aeval st (APlus (AId X) (ANum 1))) <= 5.
That is, [P'] is the assertion that [X+1] is at most [5].
*)
(** Now we can give the precise proof rule for assignment:
------------------------------ (hoare_asgn)
{{Q [X |-> a]}} X ::= a {{Q}}
*)
(** We can prove formally that this rule is indeed valid. *)
Theorem hoare_asgn : forall Q X a,
{{Q [X |-> a]}} (X ::= a) {{Q}}.
Proof.
unfold hoare_triple.
intros Q X a st st' HE HQ.
inversion HE. subst.
unfold assn_sub in HQ. assumption. Qed.
(** Here's a first formal proof using this rule. *)
Example assn_sub_example :
{{(fun st => st X = 3) [X |-> ANum 3]}}
(X ::= (ANum 3))
{{fun st => st X = 3}}.
Proof.
apply hoare_asgn. Qed.
(** **** Exercise: 2 stars (hoare_asgn_examples) *)
(** Translate these informal Hoare triples...
1) {{ (X <= 5) [X |-> X + 1] }}
X ::= X + 1
{{ X <= 5 }}
2) {{ (0 <= X /\ X <= 5) [X |-> 3] }}
X ::= 3
{{ 0 <= X /\ X <= 5 }}
...into formal statements and use [hoare_asgn] to prove them. *)
Example assn_sub_example_1:
{{ (fun st => st X <= 5 ) [X |-> APlus (AId X) (ANum 1)] }}
(X ::= APlus (AId X) (ANum 1))
{{fun st => st X <= 5 }}.
Proof.
apply hoare_asgn.
Qed.
Example assn_sub_example_2:
{{(fun st=>(0 <= st X) /\ (st X <= 5)) [X |->ANum 3] }}
X ::=(ANum 3)
{{fun st=> 0 <= st X /\ st X <= 5 }}.
Proof.
apply hoare_asgn.
Qed.
(* FILL IN HERE *)
(** [] *)
(** **** Exercise: 2 stars (hoare_asgn_wrong) *)
(** The assignment rule looks backward to almost everyone the first
time they see it. If it still seems backward to you, it may help
to think a little about alternative "forward" rules. Here is a
seemingly natural one:
------------------------------ (hoare_asgn_wrong)
{{ True }} X ::= a {{ X = a }}
Give a counterexample showing that this rule is incorrect
(informally). Hint: The rule universally quantifies over the
arithmetic expression [a], and your counterexample needs to
exhibit an [a] for which the rule doesn't work. *)
(* FILL IN HERE *)
(** {{ True }} X ::= X+1 {{ X = X+1 }}*)
(** **** Exercise: 3 stars, advanced (hoare_asgn_fwd) *)
(** However, using an auxiliary variable [m] to remember the original
value of [X] we can define a Hoare rule for assignment that does,
intuitively, "work forwards" rather than backwards.
------------------------------------------ (hoare_asgn_fwd)
{{fun st => Q st /\ st X = m}}
X ::= a
{{fun st => Q st' /\ st X = aeval st' a }}
(where st' = update st X m)
Note that we use the original value of [X] to reconstruct the
state [st'] before the assignment took place. Prove that this rule
is correct (the first hypothesis is the functional extensionality
axiom, which you will need at some point). Also note that this
rule is more complicated than [hoare_asgn].
*)
Theorem hoare_asgn_fwd :
(forall {X Y: Type} {f g : X -> Y}, (forall (x: X), f x = g x) -> f = g) ->
forall m a Q,
{{fun st => Q st /\ st X = m}}
X ::= a
{{fun st => Q (update st X m) /\ st X = aeval (update st X m) a }}.
Proof.
intros functional_extensionality v a Q. unfold hoare_triple.
intros. inversion H0. split.
Case "Q (update st' X v)". inversion H.
assert (update (update st X n) X v = st) as IH.
apply functional_extensionality . intros. rewrite update_shadow.
apply update_same. apply H2. rewrite IH. apply H1.
Case "right". inversion H.
assert (update (update st X n) X v = st) as IH.
apply functional_extensionality . intros. rewrite update_shadow.
apply update_same. apply H2. rewrite IH. SearchAbout update.
rewrite update_eq. rewrite H7. reflexivity.
Qed.
(* FILL IN HERE *)
(** [] *)
(* ####################################################### *)
(** *** Consequence *)
(** Sometimes the preconditions and postconditions we get from the
Hoare rules won't quite be the ones we want in the particular
situation at hand -- they may be logically equivalent but have a
different syntactic form that fails to unify with the goal we are
trying to prove, or they actually may be logically weaker (for
preconditions) or stronger (for postconditions) than what we need.
For instance, while
{{(X = 3) [X |-> 3]}} X ::= 3 {{X = 3}},
follows directly from the assignment rule,
{{True}} X ::= 3 {{X = 3}}.
does not. This triple is valid, but it is not an instance of
[hoare_asgn] because [True] and [(X = 3) [X |-> 3]] are not
syntactically equal assertions. However, they are logically
equivalent, so if one triple is valid, then the other must
certainly be as well. We might capture this observation with the
following rule:
{{P'}} c {{Q}}
P <<->> P'
----------------------------- (hoare_consequence_pre_equiv)
{{P}} c {{Q}}
Taking this line of thought a bit further, we can see that
strengthening the precondition or weakening the postcondition of a
valid triple always produces another valid triple. This
observation is captured by two _Rules of Consequence_.
{{P'}} c {{Q}}
P ->> P'
----------------------------- (hoare_consequence_pre)
{{P}} c {{Q}}
{{P}} c {{Q'}}
Q' ->> Q
----------------------------- (hoare_consequence_post)
{{P}} c {{Q}}
*)
(** Here are the formal versions: *)
Theorem hoare_consequence_pre : forall (P P' Q : Assertion) c,
{{P'}} c {{Q}} ->
P ->> P' ->
{{P}} c {{Q}}.
Proof.
intros P P' Q c Hhoare Himp.
intros st st' Hc HP. apply (Hhoare st st').
assumption. apply Himp. assumption. Qed.
Theorem hoare_consequence_post : forall (P Q Q' : Assertion) c,
{{P}} c {{Q'}} ->
Q' ->> Q ->
{{P}} c {{Q}}.
Proof.
intros P Q Q' c Hhoare Himp.
intros st st' Hc HP.
apply Himp.
apply (Hhoare st st').
assumption. assumption. Qed.
(** For example, we might use the first consequence rule like this:
{{ True }} ->>
{{ 1 = 1 }}
X ::= 1
{{ X = 1 }}
Or, formally...
*)
Example hoare_asgn_example1 :
{{fun st => True}} (X ::= (ANum 1)) {{fun st => st X = 1}}.
Proof.
apply hoare_consequence_pre
with (P' := (fun st => st X = 1) [X |-> ANum 1]).
apply hoare_asgn.
intros st H. unfold assn_sub, update. simpl. reflexivity.
Qed.
(** Finally, for convenience in some proofs, we can state a "combined"
rule of consequence that allows us to vary both the precondition
and the postcondition.
{{P'}} c {{Q'}}
P ->> P'
Q' ->> Q
----------------------------- (hoare_consequence)
{{P}} c {{Q}}
*)
Theorem hoare_consequence : forall (P P' Q Q' : Assertion) c,
{{P'}} c {{Q'}} ->
P ->> P' ->
Q' ->> Q ->
{{P}} c {{Q}}.
Proof.
intros P P' Q Q' c Hht HPP' HQ'Q.
apply hoare_consequence_pre with (P' := P').
apply hoare_consequence_post with (Q' := Q').
assumption. assumption. assumption. Qed.
(* ####################################################### *)
(** *** Digression: The [eapply] Tactic *)
(** This is a good moment to introduce another convenient feature of
Coq. We had to write "[with (P' := ...)]" explicitly in the proof
of [hoare_asgn_example1] and [hoare_consequence] above, to make
sure that all of the metavariables in the premises to the
[hoare_consequence_pre] rule would be set to specific
values. (Since [P'] doesn't appear in the conclusion of
[hoare_consequence_pre], the process of unifying the conclusion
with the current goal doesn't constrain [P'] to a specific
assertion.)
This is a little annoying, both because the assertion is a bit
long and also because for [hoare_asgn_example1] the very next
thing we are going to do -- applying the [hoare_asgn] rule -- will
tell us exactly what it should be! We can use [eapply] instead of
[apply] to tell Coq, essentially, "Be patient: The missing part is
going to be filled in soon." *)
Example hoare_asgn_example1' :
{{fun st => True}}
(X ::= (ANum 1))
{{fun st => st X = 1}}.
Proof.
eapply hoare_consequence_pre.
apply hoare_asgn.
intros st H. reflexivity. Qed.
(** In general, [eapply H] tactic works just like [apply H] except
that, instead of failing if unifying the goal with the conclusion
of [H] does not determine how to instantiate all of the variables
appearing in the premises of [H], [eapply H] will replace these
variables with so-called _existential variables_ (written [?nnn])
as placeholders for expressions that will be determined (by
further unification) later in the proof. *)
(** In order for [Qed] to succeed, all existential variables need to
be determined by the end of the proof. Otherwise Coq
will (rightly) refuse to accept the proof. Remember that the Coq
tactics build proof objects, and proof objects containing
existential variables are not complete. *)
Lemma silly1 : forall (P : nat -> nat -> Prop) (Q : nat -> Prop),
(forall x y : nat, P x y) ->
(forall x y : nat, P x y -> Q x) ->
Q 42.
Proof.
intros P Q HP HQ. eapply HQ . apply HP.
(** Coq gives a warning after [apply HP]:
No more subgoals but non-instantiated existential variables:
Existential 1 =
?171 : [P : nat -> nat -> Prop
Q : nat -> Prop
HP : forall x y : nat, P x y
HQ : forall x y : nat, P x y -> Q x |- nat]
(dependent evars: ?171 open,)
You can use Grab Existential Variables.
Trying to finish the proof with [Qed] gives an error:
<<
Error: Attempt to save a proof with existential variables still
non-instantiated
>> *)
Abort.
(** An additional constraint is that existential variables cannot be
instantiated with terms containing (ordinary) variables that did
not exist at the time the existential variable was created. *)
Lemma silly2 :
forall (P : nat -> nat -> Prop) (Q : nat -> Prop),
(exists y, P 42 y) ->
(forall x y : nat, P x y -> Q x) ->
Q 42.
Proof.
intros P Q HP HQ. eapply HQ. destruct HP as [y HP'].
(** Doing [apply HP'] above fails with the following error:
Error: Impossible to unify "?175" with "y".
In this case there is an easy fix:
doing [destruct HP] _before_ doing [eapply HQ].
*)
Abort.
Lemma silly2_fixed :
forall (P : nat -> nat -> Prop) (Q : nat -> Prop),
(exists y, P 42 y) ->
(forall x y : nat, P x y -> Q x) ->
Q 42.
Proof.
intros P Q HP HQ. destruct HP as [y HP'].
eapply HQ. apply HP'.
Qed.
(** In the last step we did [apply HP'] which unifies the existential
variable in the goal with the variable [y]. The [assumption]
tactic doesn't work in this case, since it cannot handle
existential variables. However, Coq also provides an [eassumption]
tactic that solves the goal if one of the premises matches the
goal up to instantiations of existential variables. We can use
it instead of [apply HP']. *)
Lemma silly2_eassumption : forall (P : nat -> nat -> Prop) (Q : nat -> Prop),
(exists y, P 42 y) ->
(forall x y : nat, P x y -> Q x) ->
Q 42.
Proof.
intros P Q HP HQ. destruct HP as [y HP']. eapply HQ. eassumption.
Qed.
(** **** Exercise: 2 stars (hoare_asgn_examples_2) *)
(** Translate these informal Hoare triples...
{{ X + 1 <= 5 }} X ::= X + 1 {{ X <= 5 }}
{{ 0 <= 3 /\ 3 <= 5 }} X ::= 3 {{ 0 <= X /\ X <= 5 }}
...into formal statements and use [hoare_asgn] and
[hoare_consequence_pre] to prove them. *)
Example hoare_asgn_examples_2 :
{{fun st => st X + 1<=5 }}
(X ::= APlus (AId X)(ANum 1))
{{fun st => st X <=5}}.
Proof.
unfold hoare_triple. intros.
eapply hoare_asgn. apply H.
unfold assn_sub. inversion H. subst.
simpl. apply H0.
Qed.
Example hoare_asgn_example2' :
{{fun _ => 0 <= 3 /\ 3 <= 5 }}
(X ::= (ANum 3))
{{fun st => 0 <= st X /\ st X <= 5}}.
Proof.
unfold hoare_triple. intros. inversion H.
subst. simpl. apply H0.
Qed.
(* FILL IN HERE *)
(** [] *)
(* ####################################################### *)
(** *** Skip *)
(** Since [SKIP] doesn't change the state, it preserves any
property P:
-------------------- (hoare_skip)
{{ P }} SKIP {{ P }}
*)
Theorem hoare_skip : forall P,
{{P}} SKIP {{P}}.
Proof.
intros P st st' H HP. inversion H. subst.
assumption. Qed.
(* ####################################################### *)
(** *** Sequencing *)
(** More interestingly, if the command [c1] takes any state where
[P] holds to a state where [Q] holds, and if [c2] takes any
state where [Q] holds to one where [R] holds, then doing [c1]
followed by [c2] will take any state where [P] holds to one
where [R] holds:
{{ P }} c1 {{ Q }}
{{ Q }} c2 {{ R }}
--------------------- (hoare_seq)
{{ P }} c1;;c2 {{ R }}
*)
Theorem hoare_seq : forall P Q R c1 c2,
{{Q}} c2 {{R}} ->
{{P}} c1 {{Q}} ->
{{P}} c1;;c2 {{R}}.
Proof.
intros P Q R c1 c2 H1 H2 st st' H12 Pre.
inversion H12; subst.
apply (H1 st'0 st'); try assumption.
apply (H2 st st'0); assumption. Qed.
(** Note that, in the formal rule [hoare_seq], the premises are
given in "backwards" order ([c2] before [c1]). This matches the
natural flow of information in many of the situations where we'll
use the rule: the natural way to construct a Hoare-logic proof is
to begin at the end of the program (with the final postcondition)
and push postconditions backwards through commands until we reach
the beginning. *)
(** Informally, a nice way of recording a proof using the sequencing
rule is as a "decorated program" where the intermediate assertion
[Q] is written between [c1] and [c2]:
{{ a = n }}
X ::= a;;
{{ X = n }} <---- decoration for Q
SKIP
{{ X = n }}
*)
Example hoare_asgn_example3 : forall a n,
{{fun st => aeval st a = n}}
(X ::= a;; SKIP)
{{fun st => st X = n}}.
Proof.
intros a n. eapply hoare_seq.
Case "right part of seq".
apply hoare_skip.
Case "left part of seq".
eapply hoare_consequence_pre. apply hoare_asgn.
intros st H. subst. reflexivity. Qed.
(** You will most often use [hoare_seq] and
[hoare_consequence_pre] in conjunction with the [eapply] tactic,
as done above. *)
(** **** Exercise: 2 stars (hoare_asgn_example4) *)
(** Translate this "decorated program" into a formal proof:
{{ True }} ->>
{{ 1 = 1 }}
X ::= 1;;
{{ X = 1 }} ->>
{{ X = 1 /\ 2 = 2 }}
Y ::= 2
{{ X = 1 /\ Y = 2 }}
*)
Example hoare_asgn_example4 :
{{fun st => True}} (X ::= (ANum 1);; Y ::= (ANum 2))
{{fun st => st X = 1 /\ st Y = 2}}.
Proof.
eapply hoare_seq. apply hoare_asgn.
eapply hoare_consequence_pre. apply hoare_asgn.
unfold assert_implies. intros. split. simpl. reflexivity.
simpl. reflexivity.
Qed.
(* FILL IN HERE *)
(** [] *)
(** **** Exercise: 3 stars (swap_exercise) *)
(** Write an Imp program [c] that swaps the values of [X] and [Y]
and show (in Coq) that it satisfies the following
specification:
{{X <= Y}} c {{Y <= X}}
*)
Definition swap_program : com :=
Z::=AId Y;;Y::=AId X;;X::=AId Z.
(* FILL IN HERE *)
Theorem swap_exercise :
{{fun st => st X <= st Y}}
swap_program
{{fun st => st Y <= st X}}.
Proof.
unfold swap_program. eapply hoare_seq. eapply hoare_seq.
apply hoare_asgn. apply hoare_asgn. eapply hoare_consequence_pre.
apply hoare_asgn. unfold assert_implies. intros. apply H.
Qed.
(* FILL IN HERE *)
(** [] *)
(** **** Exercise: 3 stars (hoarestate1) *)
(** Explain why the following proposition can't be proven:
forall (a : aexp) (n : nat),
{{fun st => aeval st a = n}}
(X ::= (ANum 3);; Y ::= a)
{{fun st => st Y = n}}.
*)
(* FILL IN HERE *)
(* [表达式a 中可能含有 X,给X赋值后,表达式a的不一定还是n] *)
(* ####################################################### *)
(** *** Conditionals *)
(** What sort of rule do we want for reasoning about conditional
commands? Certainly, if the same assertion [Q] holds after
executing either branch, then it holds after the whole
conditional. So we might be tempted to write:
{{P}} c1 {{Q}}
{{P}} c2 {{Q}}
--------------------------------
{{P}} IFB b THEN c1 ELSE c2 {{Q}}
However, this is rather weak. For example, using this rule,
we cannot show that:
{{ True }}
IFB X == 0
THEN Y ::= 2
ELSE Y ::= X + 1
FI
{{ X <= Y }}
since the rule tells us nothing about the state in which the
assignments take place in the "then" and "else" branches. *)
(** But we can actually say something more precise. In the
"then" branch, we know that the boolean expression [b] evaluates to
[true], and in the "else" branch, we know it evaluates to [false].
Making this information available in the premises of the rule gives
us more information to work with when reasoning about the behavior
of [c1] and [c2] (i.e., the reasons why they establish the
postcondition [Q]). *)
(**
{{P /\ b}} c1 {{Q}}
{{P /\ ~b}} c2 {{Q}}
------------------------------------ (hoare_if)
{{P}} IFB b THEN c1 ELSE c2 FI {{Q}}
*)
(** To interpret this rule formally, we need to do a little work.
Strictly speaking, the assertion we've written, [P /\ b], is the
conjunction of an assertion and a boolean expression -- i.e., it
doesn't typecheck. To fix this, we need a way of formally
"lifting" any bexp [b] to an assertion. We'll write [bassn b] for
the assertion "the boolean expression [b] evaluates to [true] (in
the given state)." *)
Definition bassn b : Assertion :=
fun st => (beval st b = true).
(** A couple of useful facts about [bassn]: *)
Lemma bexp_eval_true : forall b st,
beval st b = true -> (bassn b) st.
Proof.
intros b st Hbe.
unfold bassn. assumption. Qed.
Lemma bexp_eval_false : forall b st,
beval st b = false -> ~ ((bassn b) st).
Proof.
intros b st Hbe contra.
unfold bassn in contra.
rewrite -> contra in Hbe. inversion Hbe. Qed.
(** Now we can formalize the Hoare proof rule for conditionals
and prove it correct. *)
Theorem hoare_if : forall P Q b c1 c2,
{{fun st => P st /\ bassn b st}} c1 {{Q}} ->
{{fun st => P st /\ ~(bassn b st)}} c2 {{Q}} ->
{{P}} (IFB b THEN c1 ELSE c2 FI) {{Q}}.
Proof.
intros P Q b c1 c2 HTrue HFalse st st' HE HP.
inversion HE; subst.
Case "b is true".
apply (HTrue st st').
assumption.
split. assumption.
apply bexp_eval_true. assumption.
Case "b is false".
apply (HFalse st st').
assumption.
split. assumption.
apply bexp_eval_false. assumption. Qed.
(** Here is a formal proof that the program we used to motivate the
rule satisfies the specification we gave. *)
Example if_example :
{{fun st => True}}
IFB (BEq (AId X) (ANum 0))
THEN (Y ::= (ANum 2))
ELSE (Y ::= APlus (AId X) (ANum 1))
FI
{{fun st => st X <= st Y}}.
Proof.
(* WORKED IN CLASS *)
apply hoare_if.
Case "Then".
eapply hoare_consequence_pre. apply hoare_asgn.
unfold bassn, assn_sub, update, assert_implies.
simpl. intros st [_ H].
apply beq_nat_true in H.
rewrite H. omega. (* apply ble_nat_true. simpl.*)
Case "Else".
eapply hoare_consequence_pre. apply hoare_asgn.
unfold assn_sub, update, assert_implies.
simpl; intros st _. omega.
Qed.
(** **** Exercise: 2 stars (if_minus_plus) *)
(** Prove the following hoare triple using [hoare_if]: *)
Theorem if_minus_plus :
{{fun st => True}}
IFB (BLe (AId X) (AId Y))
THEN (Z ::= AMinus (AId Y) (AId X))
ELSE (Y ::= APlus (AId X) (AId Z))
FI
{{fun st => st Y = st X + st Z}}.
Proof.
apply hoare_if.
Case "Then".
eapply hoare_consequence_pre. apply hoare_asgn.
unfold bassn, assn_sub,assert_implies,update.
simpl. intros. symmetry. apply le_plus_minus_r.
inversion H. apply ble_nat_true in H1. apply H1.
Case "Else".
eapply hoare_consequence_pre. apply hoare_asgn.
unfold bassn, assn_sub,assert_implies, update.
simpl. intros. reflexivity.
Qed.
(* FILL IN HERE *)
(* ####################################################### *)
(** *** Exercise: One-sided conditionals *)
(** **** Exercise: 4 stars (if1_hoare) *)
(** In this exercise we consider extending Imp with "one-sided
conditionals" of the form [IF1 b THEN c FI]. Here [b] is a
boolean expression, and [c] is a command. If [b] evaluates to
[true], then command [c] is evaluated. If [b] evaluates to
[false], then [IF1 b THEN c FI] does nothing.
We recommend that you do this exercise before the ones that
follow, as it should help solidify your understanding of the
material. *)
(** The first step is to extend the syntax of commands and introduce
the usual notations. (We've done this for you. We use a separate
module to prevent polluting the global name space.) *)
Module If1.
Inductive com : Type :=
| CSkip : com
| CAss : id -> aexp -> com
| CSeq : com -> com -> com
| CIf : bexp -> com -> com -> com
| CWhile : bexp -> com -> com
| CIf1 : bexp -> com -> com.
Tactic Notation "com_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "SKIP" | Case_aux c "::=" | Case_aux c ";"
| Case_aux c "IFB" | Case_aux c "WHILE" | Case_aux c "CIF1" ].
Notation "'SKIP'" :=
CSkip.
Notation "c1 ;; c2" :=
(CSeq c1 c2) (at level 80, right associativity).
Notation "X '::=' a" :=
(CAss X a) (at level 60).
Notation "'WHILE' b 'DO' c 'END'" :=
(CWhile b c) (at level 80, right associativity).
Notation "'IFB' e1 'THEN' e2 'ELSE' e3 'FI'" :=
(CIf e1 e2 e3) (at level 80, right associativity).
Notation "'IF1' b 'THEN' c 'FI'" :=
(CIf1 b c) (at level 80, right associativity).
(** Next we need to extend the evaluation relation to accommodate
[IF1] branches. This is for you to do... What rule(s) need to be
added to [ceval] to evaluate one-sided conditionals? *)
Reserved Notation "c1 '/' st '||' st'" (at level 40, st at level 39).
Inductive ceval : com -> state -> state -> Prop :=
| E_Skip : forall st : state, SKIP / st || st
| E_Ass : forall (st : state) (a1 : aexp) (n : nat) (X : id),
aeval st a1 = n -> (X ::= a1) / st || update st X n
| E_Seq : forall (c1 c2 : com) (st st' st'' : state),
c1 / st || st' -> c2 / st' || st'' -> (c1 ;; c2) / st || st''
| E_IfTrue : forall (st st' : state) (b1 : bexp) (c1 c2 : com),
beval st b1 = true ->
c1 / st || st' -> (IFB b1 THEN c1 ELSE c2 FI) / st || st'
| E_IfFalse : forall (st st' : state) (b1 : bexp) (c1 c2 : com),
beval st b1 = false ->
c2 / st || st' -> (IFB b1 THEN c1 ELSE c2 FI) / st || st'
| E_WhileEnd : forall (b1 : bexp) (st : state) (c1 : com),
beval st b1 = false -> (WHILE b1 DO c1 END) / st || st
| E_WhileLoop : forall (st st' st'' : state) (b1 : bexp) (c1 : com),
beval st b1 = true ->
c1 / st || st' ->
(WHILE b1 DO c1 END) / st' || st'' ->
(WHILE b1 DO c1 END) / st || st''
(* FILL IN HERE *)
| E_If1True : forall (b : bexp)(st st' : state)(c : com),
beval st b =true ->
c / st || st'->
(IF1 b THEN c FI) / st || st'
| E_If1False : forall (b : bexp)(st : state)(c : com),
beval st b = false ->
(IF1 b THEN c FI) / st || st
where "c1 '/' st '||' st'" := (ceval c1 st st').
Tactic Notation "ceval_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "E_Skip" | Case_aux c "E_Ass" | Case_aux c "E_Seq"
| Case_aux c "E_IfTrue" | Case_aux c "E_IfFalse"
| Case_aux c "E_WhileEnd" | Case_aux c "E_WhileLoop"
| Case_aux c "E_If1True" | Case_aux c "E_If1False"
(* FILL IN HERE *)
].
(** Now we repeat (verbatim) the definition and notation of Hoare triples. *)
Definition hoare_triple (P:Assertion) (c:com) (Q:Assertion) : Prop :=
forall st st',
c / st || st' ->
P st ->
Q st'.
Notation "{{ P }} c {{ Q }}" := (hoare_triple P c Q)
(at level 90, c at next level)
: hoare_spec_scope.
(** Finally, we (i.e., you) need to state and prove a theorem,
[hoare_if1], that expresses an appropriate Hoare logic proof rule
for one-sided conditionals. Try to come up with a rule that is
both sound and as precise as possible. *)
Theorem hoare_if1 : forall P Q b c,
{{fun st => P st /\ bassn b st}} c {{Q}} ->
{{fun st => P st /\ ~(bassn b st)}} SKIP {{Q}} ->
{{P}} (IF1 b THEN c FI) {{Q}}.
Proof.
unfold hoare_triple. intros.
inversion H1;subst.
Case "b is true".
eapply H. apply H8. split.
apply H2. apply bexp_eval_true. apply H5.
Case "b is false".
eapply H0. apply E_Skip.
split. apply H2. unfold bassn. unfold not.
intros. rewrite H3 in H7. inversion H7.
Qed.
(* FILL IN HERE *)
(** For full credit, prove formally that your rule is precise enough
to show the following valid Hoare triple:
{{ X + Y = Z }}
IF1 Y <> 0 THEN
X ::= X + Y
FI
{{ X = Z }}
*)
(** Hint: Your proof of this triple may need to use the other proof
rules also. Because we're working in a separate module, you'll
need to copy here the rules you find necessary. *)
Theorem hoare_consequence_pre : forall (P P' Q : Assertion) c,
{{P'}} c {{Q}} ->
P ->> P' ->
{{P}} c {{Q}}.
Proof.
intros P P' Q c Hhoare Himp.
intros st st' Hc HP. apply (Hhoare st st').
assumption. apply Himp. assumption. Qed.
Theorem hoare_asgn : forall Q X a,
{{Q [X |-> a]}} (X ::= a) {{Q}}.
Proof.
unfold hoare_triple.
intros Q X a st st' HE HQ.
inversion HE. subst.
unfold assn_sub in HQ. assumption. Qed.
Theorem hoare_skip : forall P,
{{P}} SKIP {{P}}.
Proof.
intros P st st' H HP. inversion H. subst.
assumption. Qed.
Lemma hoare_if1_good :
{{ fun st => st X + st Y = st Z }}
IF1 BNot (BEq (AId Y) (ANum 0)) THEN
X ::= APlus (AId X) (AId Y)
FI
{{ fun st => st X = st Z }}.
Proof.
apply hoare_if1.
Case "Then".
eapply hoare_consequence_pre. apply hoare_asgn.
unfold bassn, assn_sub, update, assert_implies.
simpl. intros. inversion H. apply H0.
Case "SKip".
eapply hoare_consequence_pre. apply hoare_skip.
unfold bassn, assn_sub, update, assert_implies.
simpl. intros. inversion H. unfold not in H1.
destruct (beq_nat (st Y) 0) eqn:HE.
SCase "true". apply beq_nat_true in HE. omega.
SCase "false". simpl in H1. apply False_ind.
apply H1. reflexivity.
Qed.
(* FILL IN HERE *)
End If1.
(** [] *)
(* ####################################################### *)
(** *** Loops *)
(** Finally, we need a rule for reasoning about while loops. *)
(** Suppose we have a loop
WHILE b DO c END
and we want to find a pre-condition [P] and a post-condition
[Q] such that
{{P}} WHILE b DO c END {{Q}}
is a valid triple. *)
(** First of all, let's think about the case where [b] is false at the
beginning -- i.e., let's assume that the loop body never executes
at all. In this case, the loop behaves like [SKIP], so we might
be tempted to write
{{P}} WHILE b DO c END {{P}}.
But, as we remarked above for the conditional, we know a
little more at the end -- not just [P], but also the fact
that [b] is false in the current state. So we can enrich the
postcondition a little:
{{P}} WHILE b DO c END {{P /\ ~b}}
What about the case where the loop body _does_ get executed?
In order to ensure that [P] holds when the loop finally
exits, we certainly need to make sure that the command [c]
guarantees that [P] holds whenever [c] is finished.
Moreover, since [P] holds at the beginning of the first
execution of [c], and since each execution of [c]
re-establishes [P] when it finishes, we can always assume
that [P] holds at the beginning of [c]. This leads us to the
following rule:
{{P}} c {{P}}
-----------------------------------
{{P}} WHILE b DO c END {{P /\ ~b}}
This is almost the rule we want, but again it can be improved a
little: at the beginning of the loop body, we know not only that
[P] holds, but also that the guard [b] is true in the current
state. This gives us a little more information to use in
reasoning about [c] (showing that it establishes the invariant by
the time it finishes). This gives us the final version of the rule:
{{P /\ b}} c {{P}}
----------------------------------- (hoare_while)
{{P}} WHILE b DO c END {{P /\ ~b}}
The proposition [P] is called an _invariant_ of the loop.
One subtlety in the terminology is that calling some assertion [P]
a "loop invariant" doesn't just mean that it is preserved by the
body of the loop in question (i.e., [{{P}} c {{P}}], where [c] is
the loop body), but rather that [P] _together with the fact that
the loop's guard is true_ is a sufficient precondition for [c] to
ensure [P] as a postcondition.
This is a slightly (but significantly) weaker requirement. For
example, if [P] is the assertion [X = 0], then [P] _is_ an
invariant of the loop
WHILE X = 2 DO X := 1 END
although it is clearly _not_ preserved by the body of the
loop.
*)
Lemma hoare_while : forall P b c,
{{fun st => P st /\ bassn b st}} c {{P}} ->
{{P}} WHILE b DO c END {{fun st => P st /\ ~ (bassn b st)}}.
Proof.
intros P b c Hhoare st st' He HP.
(* Like we've seen before, we need to reason by induction
on He, because, in the "keep looping" case, its hypotheses
talk about the whole loop instead of just c *)
remember (WHILE b DO c END) as wcom eqn:Heqwcom.
ceval_cases (induction He) Case;
try (inversion Heqwcom); subst; clear Heqwcom.
Case "E_WhileEnd".
split. assumption. apply bexp_eval_false. assumption.
Case "E_WhileLoop".
apply IHHe2. reflexivity.
apply (Hhoare st st'). assumption.
split. assumption. apply bexp_eval_true. assumption.
Qed.
Example while_example :
{{fun st => st X <= 3}}
WHILE (BLe (AId X) (ANum 2))
DO X ::= APlus (AId X) (ANum 1) END
{{fun st => st X = 3}}.
Proof.
eapply hoare_consequence_post.
apply hoare_while.
eapply hoare_consequence_pre.
apply hoare_asgn.
unfold bassn, assn_sub, assert_implies, update. simpl.
intros st [H1 H2]. apply ble_nat_true in H2. omega.
unfold bassn, assert_implies. intros st [Hle Hb].
simpl in Hb. destruct (ble_nat (st X) 2) eqn : Heqle.
apply ex_falso_quodlibet. apply Hb; reflexivity.
apply ble_nat_false in Heqle. omega.
Qed.
(** We can use the while rule to prove the following Hoare triple,
which may seem surprising at first... *)
Theorem always_loop_hoare : forall P Q,
{{P}} WHILE BTrue DO SKIP END {{Q}}.
Proof.
(* WORKED IN CLASS *)
intros P Q.
apply hoare_consequence_pre with (P' := fun st : state => True).
eapply hoare_consequence_post.
apply hoare_while.
Case "Loop body preserves invariant".
apply hoare_post_true. intros st. apply I.
Case "Loop invariant and negated guard imply postcondition".
simpl. intros st [Hinv Hguard].
apply ex_falso_quodlibet. apply Hguard. reflexivity.
Case "Precondition implies invariant".
intros st H. (*apply I.*) constructor. Qed.
(** Of course, this result is not surprising if we remember that
the definition of [hoare_triple] asserts that the postcondition
must hold _only_ when the command terminates. If the command
doesn't terminate, we can prove anything we like about the
post-condition. *)
(** Hoare rules that only talk about terminating commands are
often said to describe a logic of "partial" correctness. It is
also possible to give Hoare rules for "total" correctness, which
build in the fact that the commands terminate. However, in this
course we will only talk about partial correctness. *)
(* ####################################################### *)
(** *** Exercise: [REPEAT] *)
Module RepeatExercise.
(** **** Exercise: 4 stars, advanced (hoare_repeat) *)
(** In this exercise, we'll add a new command to our language of
commands: [REPEAT] c [UNTIL] a [END]. You will write the
evaluation rule for [repeat] and add a new Hoare rule to
the language for programs involving it. *)
Inductive com : Type :=
| CSkip : com
| CAsgn : id -> aexp -> com
| CSeq : com -> com -> com
| CIf : bexp -> com -> com -> com
| CWhile : bexp -> com -> com
| CRepeat : com -> bexp -> com.
(** [REPEAT] behaves like [WHILE], except that the loop guard is
checked _after_ each execution of the body, with the loop
repeating as long as the guard stays _false_. Because of this,
the body will always execute at least once. *)
Tactic Notation "com_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "SKIP" | Case_aux c "::=" | Case_aux c ";"
| Case_aux c "IFB" | Case_aux c "WHILE"
| Case_aux c "CRepeat" ].
Notation "'SKIP'" :=
CSkip.
Notation "c1 ;; c2" :=
(CSeq c1 c2) (at level 80, right associativity).
Notation "X '::=' a" :=
(CAsgn X a) (at level 60).
Notation "'WHILE' b 'DO' c 'END'" :=
(CWhile b c) (at level 80, right associativity).
Notation "'IFB' e1 'THEN' e2 'ELSE' e3 'FI'" :=
(CIf e1 e2 e3) (at level 80, right associativity).
Notation "'REPEAT' e1 'UNTIL' b2 'END'" :=
(CRepeat e1 b2) (at level 80, right associativity).
(** Add new rules for [REPEAT] to [ceval] below. You can use the rules
for [WHILE] as a guide, but remember that the body of a [REPEAT]
should always execute at least once, and that the loop ends when
the guard becomes true. Then update the [ceval_cases] tactic to
handle these added cases. *)
Inductive ceval : state -> com -> state -> Prop :=
| E_Skip : forall st,
ceval st SKIP st
| E_Ass : forall st a1 n X,
aeval st a1 = n ->
ceval st (X ::= a1) (update st X n)
| E_Seq : forall c1 c2 st st' st'',
ceval st c1 st' ->
ceval st' c2 st'' ->
ceval st (c1 ;; c2) st''
| E_IfTrue : forall st st' b1 c1 c2,
beval st b1 = true ->
ceval st c1 st' ->
ceval st (IFB b1 THEN c1 ELSE c2 FI) st'
| E_IfFalse : forall st st' b1 c1 c2,
beval st b1 = false ->
ceval st c2 st' ->
ceval st (IFB b1 THEN c1 ELSE c2 FI) st'
| E_WhileEnd : forall b1 st c1,
beval st b1 = false ->
ceval st (WHILE b1 DO c1 END) st
| E_WhileLoop : forall st st' st'' b1 c1,
beval st b1 = true ->
ceval st c1 st' ->
ceval st' (WHILE b1 DO c1 END) st'' ->
ceval st (WHILE b1 DO c1 END) st''
(* FILL IN HERE *)
| E_Repeat : forall st st' st'' b c,
ceval st c st' ->
ceval st' (WHILE BNot b DO c END) st'' ->
ceval st (REPEAT c UNTIL b END) st''
(* | E_RepeatEnd : forall b c st st',
ceval st c st' ->
beval st' b = true ->
ceval st (REPEAT c UNTIL b END) st'
| E_RepeatLoop : forall st st' st'' b c,
ceval st c st' ->
beval st' b = false ->
ceval st' (REPEAT c UNTIL b END) st''->
ceval st (REPEAT c UNTIL b END) st''*)
.
Tactic Notation "ceval_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "E_Skip" | Case_aux c "E_Ass"
| Case_aux c "E_Seq"
| Case_aux c "E_IfTrue" | Case_aux c "E_IfFalse"
| Case_aux c "E_WhileEnd" | Case_aux c "E_WhileLoop"
| Case_aux c "E_Repeat"
(* FILL IN HERE *)
].
(** A couple of definitions from above, copied here so they use the
new [ceval]. *)
Notation "c1 '/' st '||' st'" := (ceval st c1 st')
(at level 40, st at level 39).
Definition hoare_triple (P:Assertion) (c:com) (Q:Assertion)
: Prop :=
forall st st', (c / st || st') -> P st -> Q st'.
Notation "{{ P }} c {{ Q }}" :=
(hoare_triple P c Q) (at level 90, c at next level).
(** To make sure you've got the evaluation rules for [REPEAT] right,
prove that [ex1_repeat evaluates correctly. *)
Definition ex1_repeat :=
REPEAT
X ::= ANum 1;;
Y ::= APlus (AId Y) (ANum 1)
UNTIL (BEq (AId X) (ANum 1)) END.
Theorem ex1_repeat_works :
ex1_repeat / empty_state ||
update (update empty_state X 1) Y 1.
Proof.
unfold ex1_repeat. eapply E_Repeat. eapply E_Seq. eapply E_Ass. simpl.
reflexivity. eapply E_Ass. simpl. reflexivity. apply E_WhileEnd. simpl.
reflexivity.
Qed.
(*unfold ex1_repeat. apply E_RepeatEnd.
apply E_Seq with (st':=(update empty_state X 1)).
apply E_Ass. simpl. reflexivity. apply E_Ass. simpl. reflexivity.
simpl. reflexivity.
Qed.*)
(* FILL IN HERE *)
(** Now state and prove a theorem, [hoare_repeat], that expresses an
appropriate proof rule for [repeat] commands. Use [hoare_while]
as a model, and try to make your rule as precise as possible. *)
(**
{{P}} c {{Q}} {{Q}} WHILE BNot b DO c END {{Q/\b}}
-------------------------------------------------- (hoare_repeat)
{{P}} REPEAT c UNTIL b END {{Q/\b}}
*)
Theorem hoare_repeat : forall P Q b c,
{{P}}c{{Q}}->
{{Q}}WHILE BNot b DO c END {{fun st => Q st /\(bassn b st) }}->
{{P}}REPEAT c UNTIL b END{{fun st => Q st /\(bassn b st)}}
.
Proof.
unfold hoare_triple. intros.
remember (REPEAT c UNTIL b END) as rcom eqn :Heqrcom.
ceval_cases (induction H1) Case;
inversion Heqrcom; subst. eapply H0. apply H1_0. eapply H. apply H1_. apply H2.
Qed.
(* FILL IN HERE *)
(** For full credit, make sure (informally) that your rule can be used
to prove the following valid Hoare triple:
{{ X > 0 }}
REPEAT
Y ::= X;;
X ::= X - 1
UNTIL X = 0 END
{{ X = 0 /\ Y > 0 }}
{{X>0}}
Y::X;;
X::X - 1
{{(Y= X+ 1 /\ X >=0)}}
WHILE (x<>0) DO
Y ::= X;;
X ::= X - 1
END
{{(Y= X+ 1 /\ X >=0)/\(X=0)}}
{{X = 0 /\ Y > 0}}
*)
Theorem hoare_consequence_pre : forall (P P' Q : Assertion) c,
{{P'}} c {{Q}} ->
P ->> P' ->
{{P}} c {{Q}}.
Proof.
intros P P' Q c Hhoare Himp.
intros st st' Hc HP. apply (Hhoare st st').
assumption. apply Himp. assumption. Qed.
Theorem hoare_consequence_post : forall (P Q Q' : Assertion) c,
{{P}} c {{Q'}} ->
Q' ->> Q ->
{{P}} c {{Q}}.
Proof.
intros P Q Q' c Hhoare Himp.
intros st st' Hc HP.
apply Himp.
apply (Hhoare st st').
assumption. assumption. Qed.
Theorem hoare_consequence : forall (P P' Q Q' : Assertion) c,
{{P'}} c {{Q'}} ->
P ->> P' ->
Q' ->> Q ->
{{P}} c {{Q}}.
Proof.
intros P P' Q Q' c Hht HPP' HQ'Q.
apply hoare_consequence_pre with (P' := P').
apply hoare_consequence_post with (Q' := Q').
assumption. assumption. assumption. Qed.
Lemma hoare_while : forall P b c,
{{fun st => P st /\ bassn b st}} c {{P}} ->
{{P}} WHILE b DO c END {{fun st => P st /\ ~ (bassn b st)}}.
Proof.
intros P b c Hhoare st st' He HP.
(* Like we've seen before, we need to reason by induction
on He, because, in the "keep looping" case, its hypotheses
talk about the whole loop instead of just c *)
remember (WHILE b DO c END) as wcom eqn:Heqwcom.
ceval_cases (induction He) Case;
try (inversion Heqwcom); subst; clear Heqwcom.
Case "E_WhileEnd".
split. assumption. apply bexp_eval_false. assumption.
Case "E_WhileLoop".
apply IHHe2. reflexivity.
apply (Hhoare st st'). assumption.
split. assumption. apply bexp_eval_true. assumption.
Qed.
Theorem hoare_asgn : forall Q X a,
{{Q [X |-> a]}} (X ::= a) {{Q}}.
Proof.
unfold hoare_triple.
intros Q X a st st' HE HQ.
inversion HE. subst.
unfold assn_sub in HQ. assumption. Qed.
Theorem hoare_seq : forall P Q R c1 c2,
{{Q}} c2 {{R}} ->
{{P}} c1 {{Q}} ->
{{P}} c1;;c2 {{R}}.
Proof.
intros P Q R c1 c2 H1 H2 st st' H12 Pre.
inversion H12; subst.
apply (H1 st'0 st'); try assumption.
apply (H2 st st'0); assumption. Qed.
Example repeat_example :
{{fun st => st X > 0 }}
REPEAT
Y ::= AId X;;
X ::= AMinus (AId X)(ANum 1)
UNTIL (BEq (AId X)(ANum 0)) END
{{fun st => st X = 0 /\ st Y > 0 }}
.
Proof with unfold bassn, assn_sub, assert_implies, update; simpl; try intros.
eapply hoare_consequence_post.
eapply hoare_repeat with (Q:=(fun st: state => st Y= (st X) + 1 /\ st X >=0)).
eapply hoare_seq. apply hoare_asgn. eapply hoare_consequence_pre. eapply hoare_asgn.
auto...
omega.
eapply hoare_consequence_post.
eapply hoare_while.
eapply hoare_consequence_pre.
eapply hoare_seq. apply hoare_asgn. apply hoare_asgn.
unfold bassn, assn_sub, assert_implies, update. simpl.
intros. split. inversion H.
inversion H. assert (beq_nat (st X) 0=false) as Hw. apply negb_true_iff. apply H1.
apply beq_nat_false in Hw. inversion H2. omega. omega.
unfold bassn, assn_sub, assert_implies, update. simpl.
intros. split. apply H.
inversion H. apply not_true_iff_false in H1. apply negb_false_iff. apply H1.
simpl...
inversion H. split. apply beq_nat_true in H1. apply H1. omega.
Qed.
End RepeatExercise.
(** [] *)
(* ####################################################### *)
(** ** Exercise: [HAVOC] *)
(** **** Exercise: 3 stars (himp_hoare) *)
(** In this exercise, we will derive proof rules for the [HAVOC] command
which we studied in the last chapter. First, we enclose this work
in a separate module, and recall the syntax and big-step semantics
of Himp commands. *)
Module Himp.
Inductive com : Type :=
| CSkip : com
| CAsgn : id -> aexp -> com
| CSeq : com -> com -> com
| CIf : bexp -> com -> com -> com
| CWhile : bexp -> com -> com
| CHavoc : id -> com.
Tactic Notation "com_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "SKIP" | Case_aux c "::=" | Case_aux c ";"
| Case_aux c "IFB" | Case_aux c "WHILE" | Case_aux c "HAVOC" ].
Notation "'SKIP'" :=
CSkip.
Notation "X '::=' a" :=
(CAsgn X a) (at level 60).
Notation "c1 ;; c2" :=
(CSeq c1 c2) (at level 80, right associativity).
Notation "'WHILE' b 'DO' c 'END'" :=
(CWhile b c) (at level 80, right associativity).
Notation "'IFB' e1 'THEN' e2 'ELSE' e3 'FI'" :=
(CIf e1 e2 e3) (at level 80, right associativity).
Notation "'HAVOC' X" := (CHavoc X) (at level 60).
Reserved Notation "c1 '/' st '||' st'" (at level 40, st at level 39).
Inductive ceval : com -> state -> state -> Prop :=
| E_Skip : forall st : state, SKIP / st || st
| E_Ass : forall (st : state) (a1 : aexp) (n : nat) (X : id),
aeval st a1 = n -> (X ::= a1) / st || update st X n
| E_Seq : forall (c1 c2 : com) (st st' st'' : state),
c1 / st || st' -> c2 / st' || st'' -> (c1 ;; c2) / st || st''
| E_IfTrue : forall (st st' : state) (b1 : bexp) (c1 c2 : com),
beval st b1 = true ->
c1 / st || st' -> (IFB b1 THEN c1 ELSE c2 FI) / st || st'
| E_IfFalse : forall (st st' : state) (b1 : bexp) (c1 c2 : com),
beval st b1 = false ->
c2 / st || st' -> (IFB b1 THEN c1 ELSE c2 FI) / st || st'
| E_WhileEnd : forall (b1 : bexp) (st : state) (c1 : com),
beval st b1 = false -> (WHILE b1 DO c1 END) / st || st
| E_WhileLoop : forall (st st' st'' : state) (b1 : bexp) (c1 : com),
beval st b1 = true ->
c1 / st || st' ->
(WHILE b1 DO c1 END) / st' || st'' ->
(WHILE b1 DO c1 END) / st || st''
| E_Havoc : forall (st : state) (X : id) (n : nat),
(HAVOC X) / st || update st X n
where "c1 '/' st '||' st'" := (ceval c1 st st').
Tactic Notation "ceval_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "E_Skip" | Case_aux c "E_Ass" | Case_aux c "E_Seq"
| Case_aux c "E_IfTrue" | Case_aux c "E_IfFalse"
| Case_aux c "E_WhileEnd" | Case_aux c "E_WhileLoop"
| Case_aux c "E_Havoc" ].
(** The definition of Hoare triples is exactly as before. Unlike our
notion of program equivalence, which had subtle consequences with
occassionally nonterminating commands (exercise [havoc_diverge]),
this definition is still fully satisfactory. Convince yourself of
this before proceeding. *)
Definition hoare_triple (P:Assertion) (c:com) (Q:Assertion) : Prop :=
forall st st', c / st || st' -> P st -> Q st'.
Notation "{{ P }} c {{ Q }}" := (hoare_triple P c Q)
(at level 90, c at next level)
: hoare_spec_scope.
(** Complete the Hoare rule for [HAVOC] commands below by defining
[havoc_pre] and prove that the resulting rule is correct. *)
Definition havoc_pre (X : id) (Q : Assertion) : Assertion :=
fun st => forall (n:nat), Q (update st X n).
(* FILL IN HERE *)
Theorem hoare_havoc : forall (Q : Assertion) (X : id),
{{ havoc_pre X Q }} HAVOC X {{ Q }}.
Proof.
intros.
unfold hoare_triple,havoc_pre. intros. inversion H. subst. apply H0.
Qed.
(* FILL IN HERE *)
End Himp.
(** [] *)
(* ####################################################### *)
(** ** Review *)
(** Above, we've introduced Hoare Logic as a tool to reasoning
about Imp programs. In the reminder of this chapter we will
explore a systematic way to use Hoare Logic to prove properties
about programs. The rules of Hoare Logic are the following: *)
(**
------------------------------ (hoare_asgn)
{{Q [X |-> a]}} X::=a {{Q}}
-------------------- (hoare_skip)
{{ P }} SKIP {{ P }}
{{ P }} c1 {{ Q }}
{{ Q }} c2 {{ R }}
--------------------- (hoare_seq)
{{ P }} c1;;c2 {{ R }}
{{P /\ b}} c1 {{Q}}
{{P /\ ~b}} c2 {{Q}}
------------------------------------ (hoare_if)
{{P}} IFB b THEN c1 ELSE c2 FI {{Q}}
{{P /\ b}} c {{P}}
----------------------------------- (hoare_while)
{{P}} WHILE b DO c END {{P /\ ~b}}
{{P'}} c {{Q'}}
P ->> P'
Q' ->> Q
----------------------------- (hoare_consequence)
{{P}} c {{Q}}
In the next chapter, we'll see how these rules are used to prove
that programs satisfy specifications of their behavior.
*)
(* $Date: 2013-07-18 09:59:22 -0400 (Thu, 18 Jul 2013) $ *)
|
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
//`include "../../firmware/include/fpga_regs_common.v"
//`include "../../firmware/include/fpga_regs_standard.v"
module rx_buffer_inband
( input usbclk,
input bus_reset,
input reset, // DSP side reset (used here), do not reset registers
input reset_regs, //Only reset registers
output [15:0] usbdata,
input RD,
output wire have_pkt_rdy,
output reg rx_overrun,
input wire [3:0] channels,
input wire [15:0] ch_0,
input wire [15:0] ch_1,
input wire [15:0] ch_2,
input wire [15:0] ch_3,
input wire [15:0] ch_4,
input wire [15:0] ch_5,
input wire [15:0] ch_6,
input wire [15:0] ch_7,
input rxclk,
input rxstrobe,
input clear_status,
input [6:0] serial_addr,
input [31:0] serial_data,
input serial_strobe,
output wire [15:0] debugbus,
//Connection with tx_inband
input rx_WR,
input [15:0] rx_databus,
input rx_WR_done,
output reg rx_WR_enabled,
//signal strength
input wire [31:0] rssi_0, input wire [31:0] rssi_1,
input wire [31:0] rssi_2, input wire [31:0] rssi_3,
input wire [1:0] tx_underrun
);
parameter NUM_CHAN =1;
genvar i ;
// FX2 Bug Fix
reg [8:0] read_count;
always @(negedge usbclk)
if(bus_reset)
read_count <= #1 9'd0;
else if(RD & ~read_count[8])
read_count <= #1 read_count + 9'd1;
else
read_count <= #1 RD ? read_count : 9'b0;
// Time counter
reg [31:0] adctime;
always @(posedge rxclk)
if (reset)
adctime <= 0;
else if (rxstrobe)
adctime <= adctime + 1;
// USB side fifo
wire [11:0] rdusedw;
wire [11:0] wrusedw;
wire [15:0] fifodata;
wire [15:0] fifodata_il;
reg [15:0] fifodata_16;
wire WR;
wire have_space;
assign fifodata_il = fifodata_16;
fifo_4kx16_dc rx_usb_fifo (
.aclr ( reset ),
.data ( fifodata ),
.rdclk ( ~usbclk ),
.rdreq ( RD & ~read_count[8] ),
.wrclk ( rxclk ),
.wrreq ( WR ),
.q ( usbdata ),
.rdempty ( ),
.rdusedw ( rdusedw ),
.wrfull ( ),
.wrusedw ( wrusedw ) );
assign have_pkt_rdy = (rdusedw >= 12'd256);
assign have_space = (wrusedw < 12'd760);
// Rx side fifos
wire chan_rdreq;
wire [15:0] chan_fifodata;
wire [9:0] chan_usedw;
wire [NUM_CHAN:0] chan_empty;
wire [3:0] rd_select;
wire [NUM_CHAN:0] rx_full;
wire [7:0] debug;
packet_builder #(NUM_CHAN) rx_pkt_builer (
.rxclk ( rxclk ),
.reset ( reset ),
.adctime ( adctime ),
.channels ( 4'd1 ), //need to be tested and changed to channels
.chan_rdreq ( chan_rdreq ),
.chan_fifodata ( chan_fifodata ),
.chan_empty ( chan_empty ),
.rd_select ( rd_select ),
.chan_usedw ( chan_usedw ),
.WR ( WR ),
.fifodata ( fifodata ),
.have_space ( have_space ),
.rssi_0(rssi_0), .rssi_1(rssi_1),
.rssi_2(rssi_2),.rssi_3(rssi_3), .debugbus(debug),
.underrun(tx_underrun));
// Detect overrun
always @(posedge rxclk)
if(reset)
rx_overrun <= 1'b0;
else if(rx_full[0])
rx_overrun <= 1'b1;
else if(clear_status)
rx_overrun <= 1'b0;
// TODO write this genericly
//wire [15:0]ch[NUM_CHAN:0];
//assign ch[0] = ch_0;
wire cmd_empty;
always @(posedge rxclk)
if(reset)
rx_WR_enabled <= 1;
else if(cmd_empty)
rx_WR_enabled <= 1;
else if(rx_WR_done)
rx_WR_enabled <= 0;
// Switching of channels
reg [3:0] store_next;
always @(posedge rxclk)
if(reset)
store_next <= #1 4'd0;
else if(rxstrobe & (store_next == 0))
store_next <= #1 4'd1;
else if(~rx_full & (store_next == 4'd2))
store_next <= #1 4'd0;
else if(~rx_full & (store_next != 0))
store_next <= #1 store_next + 4'd1;
always @*
case(store_next)
4'd1 : fifodata_16 = ch_0;
4'd2 : fifodata_16 = ch_1;
default: fifodata_16 = 16'hFFFF;
endcase
wire [15:0] dataout [0:NUM_CHAN];
wire [9:0] usedw [0:NUM_CHAN];
wire empty[0:NUM_CHAN];
generate for (i = 0 ; i < NUM_CHAN; i = i + 1)
begin : generate_channel_fifos
wire rdreq;
assign rdreq = (rd_select == i) & chan_rdreq;
fifo_1kx16 rx_chan_fifo (
.aclr ( reset ),
.clock ( rxclk ),
.data ( fifodata_il ),
.rdreq ( rdreq ),
.wrreq ( ~rx_full[i] & (store_next != 0)),
.empty (empty[i]),
.full (rx_full[i]),
.q ( dataout[i]),
.usedw ( usedw[i]),
.almost_empty(chan_empty[i])
);
end
endgenerate
fifo_1kx16 rx_cmd_fifo (
.aclr ( reset ),
.clock ( rxclk ),
.data ( rx_databus ),
.rdreq ( (rd_select == NUM_CHAN) & chan_rdreq ),
.wrreq ( rx_WR & rx_WR_enabled),
.empty ( cmd_empty),
.full ( rx_full[NUM_CHAN] ),
.q ( dataout[NUM_CHAN]),
.usedw ( usedw[NUM_CHAN] )
);
assign chan_empty[NUM_CHAN] = cmd_empty | rx_WR_enabled;
assign chan_fifodata = dataout[rd_select];
assign chan_usedw = usedw[rd_select];
assign debugbus = {4'd0, rxclk, rxstrobe, store_next[3], store_next[1], store_next[0]};
endmodule
|
module auto_module
( input my_clk,
input my_rst_n,
output manually_listed,
/*AUTOINOUTMODPORT("automodport_if" "pure_mp")*/
//ex: input in_pure;
//ex: output out_pure;
/*AUTOINOUTMODPORT("automodport_if" "req_mon_mp")*/
//ex: input req_credit, // To auto_i of auto_intf.sv
//ex: input [63:0] req_data, // To auto_i of auto_intf.sv
//ex: input req_val, // To auto_i of auto_intf.sv
/*AUTOINOUTMODPORT("automodport_if" "rsp_drv_mp")*/
//ex: output [1:0] rsp_cmd, // From auto_i of auto_intf.sv
//ex: input rsp_credit, // To auto_i of auto_intf.sv
//ex: output [63:0] rsp_data // From auto_i of auto_intf.sv
);
auto_intf auto_i
(// Inputs
.clk (my_clk),
.rst_n (my_rst_n));
/*AUTOASSIGNMODPORT("automodport_if" "req_mon_mp" "auto_i" )*/
//ex: assign auto_i.req_credit = req_credit;
//ex: assign auto_i.req_data = req_data;
//ex: assign auto_i.req_val = req_val;
/*AUTOASSIGNMODPORT("automodport_if" "rsp_drv_mp" "auto_i" )*/
//ex: assign rsp_cmd = auto_i.rsp_cmd;
//ex: assign rsp_data = auto_i.rsp_data;
//ex: assign auto_i.rsp_credit = rsp_credit;
/*AUTOASSIGNMODPORT("automodport_if" "r.*" "auto_i" )*/
initial begin
`cn_set_intf(virtual auto_intf.req_mon_mp, "auto_pkg::auto_intf", "req_mon_vi", auto_i.req_mon_mp );
`cn_set_intf(virtual auto_intf.rsp_drv_mp, "auto_pkg::auto_intf", "rsp_drv_vi", auto_i.rsp_drv_mp );
end
endmodule
|
(** * Auto: More Automation *)
Set Warnings "-notation-overridden,-parsing".
From Coq Require Import omega.Omega.
From LF Require Import Maps.
From LF Require Import Imp.
(** Up to now, we've used the more manual part of Coq's tactic
facilities. In this chapter, we'll learn more about some of Coq's
powerful automation features: proof search via the [auto] tactic,
automated forward reasoning via the [Ltac] hypothesis matching
machinery, and deferred instantiation of existential variables
using [eapply] and [eauto]. Using these features together with
Ltac's scripting facilities will enable us to make our proofs
startlingly short! Used properly, they can also make proofs more
maintainable and robust to changes in underlying definitions. A
deeper treatment of [auto] and [eauto] can be found in the
[UseAuto] chapter in _Programming Language Foundations_.
There's another major category of automation we haven't discussed
much yet, namely built-in decision procedures for specific kinds
of problems: [omega] is one example, but there are others. This
topic will be deferred for a while longer.
Our motivating example will be this proof, repeated with just a
few small changes from the [Imp] chapter. We will simplify
this proof in several stages. *)
(** First, define a little Ltac macro to compress a common
pattern into a single command. *)
Ltac inv H := inversion H; subst; clear H.
Theorem ceval_deterministic: forall c st st1 st2,
st =[ c ]=> st1 ->
st =[ c ]=> st2 ->
st1 = st2.
Proof.
intros c st st1 st2 E1 E2;
generalize dependent st2;
induction E1; intros st2 E2; inv E2.
- (* E_Skip *) reflexivity.
- (* E_Ass *) reflexivity.
- (* E_Seq *)
assert (st' = st'0) as EQ1.
{ (* Proof of assertion *) apply IHE1_1; apply H1. }
subst st'0.
apply IHE1_2. assumption.
(* E_IfTrue *)
- (* b evaluates to true *)
apply IHE1. assumption.
- (* b evaluates to false (contradiction) *)
rewrite H in H5. inversion H5.
(* E_IfFalse *)
- (* b evaluates to true (contradiction) *)
rewrite H in H5. inversion H5.
- (* b evaluates to false *)
apply IHE1. assumption.
(* E_WhileFalse *)
- (* b evaluates to false *)
reflexivity.
- (* b evaluates to true (contradiction) *)
rewrite H in H2. inversion H2.
(* E_WhileTrue *)
- (* b evaluates to false (contradiction) *)
rewrite H in H4. inversion H4.
- (* b evaluates to true *)
assert (st' = st'0) as EQ1.
{ (* Proof of assertion *) apply IHE1_1; assumption. }
subst st'0.
apply IHE1_2. assumption. Qed.
(* ################################################################# *)
(** * The [auto] Tactic *)
(** Thus far, our proof scripts mostly apply relevant hypotheses or
lemmas by name, and one at a time. *)
Example auto_example_1 : forall (P Q R: Prop),
(P -> Q) -> (Q -> R) -> P -> R.
Proof.
intros P Q R H1 H2 H3.
apply H2. apply H1. assumption.
Qed.
(** The [auto] tactic frees us from this drudgery by _searching_ for a
sequence of applications that will prove the goal: *)
Example auto_example_1' : forall (P Q R: Prop),
(P -> Q) -> (Q -> R) -> P -> R.
Proof.
auto.
Qed.
(** The [auto] tactic solves goals that are solvable by any combination of
- [intros] and
- [apply] (of hypotheses from the local context, by default). *)
(** Using [auto] is always "safe" in the sense that it will never fail
and will never change the proof state: either it completely solves
the current goal, or it does nothing. *)
(** Here is a more interesting example showing [auto]'s power: *)
Example auto_example_2 : forall P Q R S T U : Prop,
(P -> Q) ->
(P -> R) ->
(T -> R) ->
(S -> T -> U) ->
((P->Q) -> (P->S)) ->
T ->
P ->
U.
Proof. auto. Qed.
(** Proof search could, in principle, take an arbitrarily long time,
so there are limits to how far [auto] will search by default. *)
Example auto_example_3 : forall (P Q R S T U: Prop),
(P -> Q) ->
(Q -> R) ->
(R -> S) ->
(S -> T) ->
(T -> U) ->
P ->
U.
Proof.
(* When it cannot solve the goal, [auto] does nothing *)
auto.
(* Optional argument says how deep to search (default is 5) *)
auto 6.
Qed.
(** When searching for potential proofs of the current goal,
[auto] considers the hypotheses in the current context together
with a _hint database_ of other lemmas and constructors. Some
common lemmas about equality and logical operators are installed
in this hint database by default. *)
Example auto_example_4 : forall P Q R : Prop,
Q ->
(Q -> R) ->
P \/ (Q /\ R).
Proof. auto. Qed.
(** We can extend the hint database just for the purposes of one
application of [auto] by writing "[auto using ...]". *)
Lemma le_antisym : forall n m: nat, (n <= m /\ m <= n) -> n = m.
Proof. intros. omega. Qed.
Example auto_example_6 : forall n m p : nat,
(n <= p -> (n <= m /\ m <= n)) ->
n <= p ->
n = m.
Proof.
intros.
auto using le_antisym.
Qed.
(** Of course, in any given development there will probably be
some specific constructors and lemmas that are used very often in
proofs. We can add these to the global hint database by writing
Hint Resolve T.
at the top level, where [T] is a top-level theorem or a
constructor of an inductively defined proposition (i.e., anything
whose type is an implication). As a shorthand, we can write
Hint Constructors c.
to tell Coq to do a [Hint Resolve] for _all_ of the constructors
from the inductive definition of [c].
It is also sometimes necessary to add
Hint Unfold d.
where [d] is a defined symbol, so that [auto] knows to expand uses
of [d], thus enabling further possibilities for applying lemmas that
it knows about. *)
(** It is also possible to define specialized hint databases that can
be activated only when needed. See the Coq reference manual for
more. *)
Hint Resolve le_antisym.
Example auto_example_6' : forall n m p : nat,
(n<= p -> (n <= m /\ m <= n)) ->
n <= p ->
n = m.
Proof.
intros.
auto. (* picks up hint from database *)
Qed.
Definition is_fortytwo x := (x = 42).
Example auto_example_7: forall x,
(x <= 42 /\ 42 <= x) -> is_fortytwo x.
Proof.
auto. (* does nothing *)
Abort.
Hint Unfold is_fortytwo.
Example auto_example_7' : forall x,
(x <= 42 /\ 42 <= x) -> is_fortytwo x.
Proof. auto. Qed.
(** Let's take a first pass over [ceval_deterministic] to simplify the
proof script. *)
Theorem ceval_deterministic': forall c st st1 st2,
st =[ c ]=> st1 ->
st =[ c ]=> st2 ->
st1 = st2.
Proof.
intros c st st1 st2 E1 E2.
generalize dependent st2;
induction E1; intros st2 E2; inv E2; auto.
- (* E_Seq *)
assert (st' = st'0) as EQ1 by auto.
subst st'0.
auto.
- (* E_IfTrue *)
+ (* b evaluates to false (contradiction) *)
rewrite H in H5. inversion H5.
- (* E_IfFalse *)
+ (* b evaluates to true (contradiction) *)
rewrite H in H5. inversion H5.
- (* E_WhileFalse *)
+ (* b evaluates to true (contradiction) *)
rewrite H in H2. inversion H2.
(* E_WhileTrue *)
- (* b evaluates to false (contradiction) *)
rewrite H in H4. inversion H4.
- (* b evaluates to true *)
assert (st' = st'0) as EQ1 by auto.
subst st'0.
auto.
Qed.
(** When we are using a particular tactic many times in a proof, we
can use a variant of the [Proof] command to make that tactic into
a default within the proof. Saying [Proof with t] (where [t] is
an arbitrary tactic) allows us to use [t1...] as a shorthand for
[t1;t] within the proof. As an illustration, here is an alternate
version of the previous proof, using [Proof with auto]. *)
Theorem ceval_deterministic'_alt: forall c st st1 st2,
st =[ c ]=> st1 ->
st =[ c ]=> st2 ->
st1 = st2.
Proof with auto.
intros c st st1 st2 E1 E2;
generalize dependent st2;
induction E1;
intros st2 E2; inv E2...
- (* E_Seq *)
assert (st' = st'0) as EQ1...
subst st'0...
- (* E_IfTrue *)
+ (* b evaluates to false (contradiction) *)
rewrite H in H5. inversion H5.
- (* E_IfFalse *)
+ (* b evaluates to true (contradiction) *)
rewrite H in H5. inversion H5.
- (* E_WhileFalse *)
+ (* b evaluates to true (contradiction) *)
rewrite H in H2. inversion H2.
(* E_WhileTrue *)
- (* b evaluates to false (contradiction) *)
rewrite H in H4. inversion H4.
- (* b evaluates to true *)
assert (st' = st'0) as EQ1...
subst st'0...
Qed.
(* ################################################################# *)
(** * Searching For Hypotheses *)
(** The proof has become simpler, but there is still an annoying
amount of repetition. Let's start by tackling the contradiction
cases. Each of them occurs in a situation where we have both
H1: beval st b = false
and
H2: beval st b = true
as hypotheses. The contradiction is evident, but demonstrating it
is a little complicated: we have to locate the two hypotheses [H1]
and [H2] and do a [rewrite] following by an [inversion]. We'd
like to automate this process.
(In fact, Coq has a built-in tactic [congruence] that will do the
job in this case. But we'll ignore the existence of this tactic
for now, in order to demonstrate how to build forward search
tactics by hand.)
As a first step, we can abstract out the piece of script in
question by writing a little function in Ltac. *)
Ltac rwinv H1 H2 := rewrite H1 in H2; inv H2.
Theorem ceval_deterministic'': forall c st st1 st2,
st =[ c ]=> st1 ->
st =[ c ]=> st2 ->
st1 = st2.
Proof.
intros c st st1 st2 E1 E2.
generalize dependent st2;
induction E1; intros st2 E2; inv E2; auto.
- (* E_Seq *)
assert (st' = st'0) as EQ1 by auto.
subst st'0.
auto.
- (* E_IfTrue *)
+ (* b evaluates to false (contradiction) *)
rwinv H H5.
- (* E_IfFalse *)
+ (* b evaluates to true (contradiction) *)
rwinv H H5.
- (* E_WhileFalse *)
+ (* b evaluates to true (contradiction) *)
rwinv H H2.
(* E_WhileTrue *)
- (* b evaluates to false (contradiction) *)
rwinv H H4.
- (* b evaluates to true *)
assert (st' = st'0) as EQ1 by auto.
subst st'0.
auto. Qed.
(** That was a bit better, but we really want Coq to discover the
relevant hypotheses for us. We can do this by using the [match
goal] facility of Ltac. *)
Ltac find_rwinv :=
match goal with
H1: ?E = true,
H2: ?E = false
|- _ => rwinv H1 H2
end.
(** This [match goal] looks for two distinct hypotheses that
have the form of equalities, with the same arbitrary expression
[E] on the left and with conflicting boolean values on the right.
If such hypotheses are found, it binds [H1] and [H2] to their
names and applies the [rwinv] tactic to [H1] and [H2].
Adding this tactic to the ones that we invoke in each case of the
induction handles all of the contradictory cases. *)
Theorem ceval_deterministic''': forall c st st1 st2,
st =[ c ]=> st1 ->
st =[ c ]=> st2 ->
st1 = st2.
Proof.
intros c st st1 st2 E1 E2.
generalize dependent st2;
induction E1; intros st2 E2; inv E2; try find_rwinv; auto.
- (* E_Seq *)
assert (st' = st'0) as EQ1 by auto.
subst st'0.
auto.
- (* E_WhileTrue *)
+ (* b evaluates to true *)
assert (st' = st'0) as EQ1 by auto.
subst st'0.
auto. Qed.
(** Let's see about the remaining cases. Each of them involves
applying a conditional hypothesis to extract an equality.
Currently we have phrased these as assertions, so that we have to
predict what the resulting equality will be (although we can then
use [auto] to prove it). An alternative is to pick the relevant
hypotheses to use and then [rewrite] with them, as follows: *)
Theorem ceval_deterministic'''': forall c st st1 st2,
st =[ c ]=> st1 ->
st =[ c ]=> st2 ->
st1 = st2.
Proof.
intros c st st1 st2 E1 E2.
generalize dependent st2;
induction E1; intros st2 E2; inv E2; try find_rwinv; auto.
- (* E_Seq *)
rewrite (IHE1_1 st'0 H1) in *. auto.
- (* E_WhileTrue *)
+ (* b evaluates to true *)
rewrite (IHE1_1 st'0 H3) in *. auto. Qed.
(** Now we can automate the task of finding the relevant hypotheses to
rewrite with. *)
Ltac find_eqn :=
match goal with
H1: forall x, ?P x -> ?L = ?R,
H2: ?P ?X
|- _ => rewrite (H1 X H2) in *
end.
(** The pattern [forall x, ?P x -> ?L = ?R] matches any hypothesis of
the form "for all [x], _some property of [x]_ implies _some
equality_." The property of [x] is bound to the pattern variable
[P], and the left- and right-hand sides of the equality are bound
to [L] and [R]. The name of this hypothesis is bound to [H1].
Then the pattern [?P ?X] matches any hypothesis that provides
evidence that [P] holds for some concrete [X]. If both patterns
succeed, we apply the [rewrite] tactic (instantiating the
quantified [x] with [X] and providing [H2] as the required
evidence for [P X]) in all hypotheses and the goal.
One problem remains: in general, there may be several pairs of
hypotheses that have the right general form, and it seems tricky
to pick out the ones we actually need. A key trick is to realize
that we can _try them all_! Here's how this works:
- each execution of [match goal] will keep trying to find a valid
pair of hypotheses until the tactic on the RHS of the match
succeeds; if there are no such pairs, it fails;
- [rewrite] will fail given a trivial equation of the form [X = X];
- we can wrap the whole thing in a [repeat], which will keep doing
useful rewrites until only trivial ones are left. *)
Theorem ceval_deterministic''''': forall c st st1 st2,
st =[ c ]=> st1 ->
st =[ c ]=> st2 ->
st1 = st2.
Proof.
intros c st st1 st2 E1 E2.
generalize dependent st2;
induction E1; intros st2 E2; inv E2; try find_rwinv;
repeat find_eqn; auto.
Qed.
(** The big payoff in this approach is that our proof script should be
more robust in the face of modest changes to our language. To
test this, let's try adding a [REPEAT] command to the language. *)
Module Repeat.
Inductive com : Type :=
| CSkip
| CAsgn (x : string) (a : aexp)
| CSeq (c1 c2 : com)
| CIf (b : bexp) (c1 c2 : com)
| CWhile (b : bexp) (c : com)
| CRepeat (c : com) (b : bexp).
(** [REPEAT] behaves like [WHILE], except that the loop guard is
checked _after_ each execution of the body, with the loop
repeating as long as the guard stays _false_. Because of this,
the body will always execute at least once. *)
Notation "'SKIP'" :=
CSkip.
Notation "c1 ; c2" :=
(CSeq c1 c2) (at level 80, right associativity).
Notation "X '::=' a" :=
(CAsgn X a) (at level 60).
Notation "'WHILE' b 'DO' c 'END'" :=
(CWhile b c) (at level 80, right associativity).
Notation "'TEST' e1 'THEN' e2 'ELSE' e3 'FI'" :=
(CIf e1 e2 e3) (at level 80, right associativity).
Notation "'REPEAT' e1 'UNTIL' b2 'END'" :=
(CRepeat e1 b2) (at level 80, right associativity).
Inductive ceval : state -> com -> state -> Prop :=
| E_Skip : forall st,
ceval st SKIP st
| E_Ass : forall st a1 n X,
aeval st a1 = n ->
ceval st (X ::= a1) (t_update st X n)
| E_Seq : forall c1 c2 st st' st'',
ceval st c1 st' ->
ceval st' c2 st'' ->
ceval st (c1 ; c2) st''
| E_IfTrue : forall st st' b1 c1 c2,
beval st b1 = true ->
ceval st c1 st' ->
ceval st (TEST b1 THEN c1 ELSE c2 FI) st'
| E_IfFalse : forall st st' b1 c1 c2,
beval st b1 = false ->
ceval st c2 st' ->
ceval st (TEST b1 THEN c1 ELSE c2 FI) st'
| E_WhileFalse : forall b1 st c1,
beval st b1 = false ->
ceval st (WHILE b1 DO c1 END) st
| E_WhileTrue : forall st st' st'' b1 c1,
beval st b1 = true ->
ceval st c1 st' ->
ceval st' (WHILE b1 DO c1 END) st'' ->
ceval st (WHILE b1 DO c1 END) st''
| E_RepeatEnd : forall st st' b1 c1,
ceval st c1 st' ->
beval st' b1 = true ->
ceval st (CRepeat c1 b1) st'
| E_RepeatLoop : forall st st' st'' b1 c1,
ceval st c1 st' ->
beval st' b1 = false ->
ceval st' (CRepeat c1 b1) st'' ->
ceval st (CRepeat c1 b1) st''.
Notation "st '=[' c ']=>' st'" := (ceval st c st')
(at level 40).
(** Our first attempt at the determinacy proof does not quite succeed:
the [E_RepeatEnd] and [E_RepeatLoop] cases are not handled by our
previous automation. *)
Theorem ceval_deterministic: forall c st st1 st2,
st =[ c ]=> st1 ->
st =[ c ]=> st2 ->
st1 = st2.
Proof.
intros c st st1 st2 E1 E2.
generalize dependent st2;
induction E1;
intros st2 E2; inv E2; try find_rwinv; repeat find_eqn; auto.
- (* E_RepeatEnd *)
+ (* b evaluates to false (contradiction) *)
find_rwinv.
(* oops: why didn't [find_rwinv] solve this for us already?
answer: we did things in the wrong order. *)
- (* E_RepeatLoop *)
+ (* b evaluates to true (contradiction) *)
find_rwinv.
Qed.
(** Fortunately, to fix this, we just have to swap the invocations of
[find_eqn] and [find_rwinv]. *)
Theorem ceval_deterministic': forall c st st1 st2,
st =[ c ]=> st1 ->
st =[ c ]=> st2 ->
st1 = st2.
Proof.
intros c st st1 st2 E1 E2.
generalize dependent st2;
induction E1;
intros st2 E2; inv E2; repeat find_eqn; try find_rwinv; auto.
Qed.
End Repeat.
(** These examples just give a flavor of what "hyper-automation"
can achieve in Coq. The details of [match goal] are a bit
tricky (and debugging scripts using it is, frankly, not very
pleasant). But it is well worth adding at least simple uses to
your proofs, both to avoid tedium and to "future proof" them. *)
(* ================================================================= *)
(** ** The [eapply] and [eauto] variants *)
(** To close the chapter, we'll introduce one more convenient feature
of Coq: its ability to delay instantiation of quantifiers. To
motivate this feature, recall this example from the [Imp]
chapter: *)
Example ceval_example1:
empty_st =[
X ::= 2;;
TEST X <= 1
THEN Y ::= 3
ELSE Z ::= 4
FI
]=> (Z !-> 4 ; X !-> 2).
Proof.
(* We supply the intermediate state [st']... *)
apply E_Seq with (X !-> 2).
- apply E_Ass. reflexivity.
- apply E_IfFalse. reflexivity. apply E_Ass. reflexivity.
Qed.
(** In the first step of the proof, we had to explicitly provide a
longish expression to help Coq instantiate a "hidden" argument to
the [E_Seq] constructor. This was needed because the definition
of [E_Seq]...
E_Seq : forall c1 c2 st st' st'',
st =[ c1 ]=> st' ->
st' =[ c2 ]=> st'' ->
st =[ c1 ;; c2 ]=> st''
is quantified over a variable, [st'], that does not appear in its
conclusion, so unifying its conclusion with the goal state doesn't
help Coq find a suitable value for this variable. If we leave
out the [with], this step fails ("Error: Unable to find an
instance for the variable [st']").
What's silly about this error is that the appropriate value for [st']
will actually become obvious in the very next step, where we apply
[E_Ass]. If Coq could just wait until we get to this step, there
would be no need to give the value explicitly. This is exactly what
the [eapply] tactic gives us: *)
Example ceval'_example1:
empty_st =[
X ::= 2;;
TEST X <= 1
THEN Y ::= 3
ELSE Z ::= 4
FI
]=> (Z !-> 4 ; X !-> 2).
Proof.
eapply E_Seq. (* 1 *)
- apply E_Ass. (* 2 *)
reflexivity. (* 3 *)
- (* 4 *) apply E_IfFalse. reflexivity. apply E_Ass. reflexivity.
Qed.
(** The [eapply H] tactic behaves just like [apply H] except
that, after it finishes unifying the goal state with the
conclusion of [H], it does not bother to check whether all the
variables that were introduced in the process have been given
concrete values during unification.
If you step through the proof above, you'll see that the goal
state at position [1] mentions the _existential variable_ [?st']
in both of the generated subgoals. The next step (which gets us
to position [2]) replaces [?st'] with a concrete value. This new
value contains a new existential variable [?n], which is
instantiated in its turn by the following [reflexivity] step,
position [3]. When we start working on the second
subgoal (position [4]), we observe that the occurrence of [?st']
in this subgoal has been replaced by the value that it was given
during the first subgoal. *)
(** Several of the tactics that we've seen so far, including [exists],
[constructor], and [auto], have similar variants. For example,
here's a proof using [eauto]: *)
Hint Constructors ceval.
Hint Transparent state.
Hint Transparent total_map.
Definition st12 := (Y !-> 2 ; X !-> 1).
Definition st21 := (Y !-> 1 ; X !-> 2).
Example eauto_example : exists s',
st21 =[
TEST X <= Y
THEN Z ::= Y - X
ELSE Y ::= X + Z
FI
]=> s'.
Proof. eauto. Qed.
(** The [eauto] tactic works just like [auto], except that it uses
[eapply] instead of [apply].
Pro tip: One might think that, since [eapply] and [eauto] are more
powerful than [apply] and [auto], it would be a good idea to use
them all the time. Unfortunately, they are also significantly
slower -- especially [eauto]. Coq experts tend to use [apply] and
[auto] most of the time, only switching to the [e] variants when
the ordinary variants don't do the job. *)
(* Wed Jan 9 12:02:47 EST 2019 *)
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: ff_jbi_sc2_2.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
module ff_jbi_sc2_2(/*AUTOARG*/
// Outputs
jbi_sctag_req_d1, scbuf_jbi_data_d1, jbi_scbuf_ecc_d1,
jbi_sctag_req_vld_d1, scbuf_jbi_ctag_vld_d1, scbuf_jbi_ue_err_d1,
sctag_jbi_iq_dequeue_d1, sctag_jbi_wib_dequeue_d1,
sctag_jbi_por_req_d1, so,
// Inputs
jbi_sctag_req, scbuf_jbi_data, jbi_scbuf_ecc, jbi_sctag_req_vld,
scbuf_jbi_ctag_vld, scbuf_jbi_ue_err, sctag_jbi_iq_dequeue,
sctag_jbi_wib_dequeue, sctag_jbi_por_req, rclk, si, se
);
output [31:0] jbi_sctag_req_d1;
output [31:0] scbuf_jbi_data_d1;
output [6:0] jbi_scbuf_ecc_d1;
output jbi_sctag_req_vld_d1;
output scbuf_jbi_ctag_vld_d1;
output scbuf_jbi_ue_err_d1;
output sctag_jbi_iq_dequeue_d1;
output sctag_jbi_wib_dequeue_d1;
output sctag_jbi_por_req_d1;
input [31:0] jbi_sctag_req;
input [31:0] scbuf_jbi_data;
input [6:0] jbi_scbuf_ecc;
input jbi_sctag_req_vld;
input scbuf_jbi_ctag_vld;
input scbuf_jbi_ue_err;
input sctag_jbi_iq_dequeue;
input sctag_jbi_wib_dequeue;
input sctag_jbi_por_req;
input rclk;
input si, se;
output so;
wire int_scanout;
// connect scanout of the last flop to int_scanout.
// The output of the lockup latch is
// the scanout of this dbb (so)
bw_u1_scanlg_2x so_lockup(.so(so), .sd(int_scanout), .ck(rclk), .se(se));
dff_s #(32) ff_flop_row0 (.q(jbi_sctag_req_d1[31:0]),
.din(jbi_sctag_req[31:0]),
.clk(rclk), .se(1'b0), .si(), .so() );
dff_s #(32) ff_flop_row1 (.q(scbuf_jbi_data_d1[31:0]),
.din(scbuf_jbi_data[31:0]),
.clk(rclk), .se(1'b0), .si(), .so() );
dff_s #(13) ff_flop_row2 (.q({ jbi_scbuf_ecc_d1[6:0],
jbi_sctag_req_vld_d1,
scbuf_jbi_ctag_vld_d1,
scbuf_jbi_ue_err_d1,
sctag_jbi_iq_dequeue_d1,
sctag_jbi_wib_dequeue_d1,
sctag_jbi_por_req_d1}),
.din({ jbi_scbuf_ecc[6:0],
jbi_sctag_req_vld,
scbuf_jbi_ctag_vld,
scbuf_jbi_ue_err,
sctag_jbi_iq_dequeue,
sctag_jbi_wib_dequeue,
sctag_jbi_por_req}),
.clk(rclk), .se(1'b0), .si(), .so() );
endmodule
|
// (C) 1992-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// Reduced Normalization module
//
// This module performs realignment of data such that the most significant bit is 1 for any number with exponent >= 1,
// and zero otherwise. This version of the module is specifically designed for the multiplier with no support for denormalized
// numbers. As such it is far smaller.
//
module acl_fp_custom_reduced_normalize_mult_double(
clock, resetn,
mantissa, exponent, sign,
// Used in HIGH_CAPACITY = 1 mode
stall_in, valid_in, stall_out, valid_out,
// Used in HIGH_CAPACITY = 0 mode
enable,
mantissa_out, exponent_out, sign_out);
parameter HIGH_CAPACITY = 1;
parameter FINITE_MATH_ONLY = 1;
parameter REMOVE_STICKY = 1;
input clock, resetn;
input stall_in, valid_in;
output stall_out, valid_out;
input enable;
// Data in
input [56:0] mantissa;
input [11:0] exponent; // Exponent with MSB set to 1 is an exception.
input sign;
// Data output
output [55:0] mantissa_out; // When mantissa_out[54] = 1 and exponent_out[11] == 1 then the number is NaN.
output [11:0] exponent_out; // Exponent with MSB set to 1 is an exception.
output sign_out;
// Stall/valid and enable signals on per-stage basis.
reg c1_valid;
wire c1_stall;
wire c1_enable;
// Cycle 1 - There is not much to do for a multiplier that does not support denormalized numbers.
// At the most, shift right by 1.
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg [55:0] c1_mantissa;
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg [11:0] c1_exponent;
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg c1_sign;
assign c1_enable = (HIGH_CAPACITY == 1) ? (~c1_valid | ~c1_stall) : enable;
assign stall_out = c1_valid & c1_stall;
always@(posedge clock or negedge resetn)
begin
if (~resetn)
begin
c1_mantissa <= 56'dx;
c1_exponent <= 12'dx;
c1_sign <= 1'bx;
c1_valid <= 1'b0;
end
else if (c1_enable)
begin
c1_valid <= valid_in;
c1_sign <= sign;
// Handle mantissa
if (mantissa[56])
begin
if ((exponent == 12'h7fe) && (FINITE_MATH_ONLY == 0))
begin
c1_mantissa <= 56'h40000000000000;
end
else
begin
if (REMOVE_STICKY == 1)
begin
c1_mantissa <= mantissa[56:1];
end
else
begin
c1_mantissa <= {mantissa[56:2], |mantissa[1:0]};
end
end
end
else
begin
c1_mantissa <= mantissa[55:0];
end
// handle exponent
if (FINITE_MATH_ONLY == 0)
begin
if (mantissa[56])
begin
if (exponent == 12'h7fe)
begin
c1_exponent <= 12'hfff;
end
else
begin
c1_exponent <= exponent + 1'b1;
end
end
else
begin
if (~mantissa[55] & ~exponent[11])
c1_exponent <= 12'd0;
else
c1_exponent <= exponent;
end
end
else
begin
c1_exponent <= (exponent & {12{mantissa[56] | mantissa[55]}}) + {1'b0, mantissa[56]};
end
end
end
assign mantissa_out = c1_mantissa;
assign exponent_out = c1_exponent;
assign sign_out = c1_sign;
assign valid_out = c1_valid;
assign c1_stall = stall_in;
endmodule
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2009-2010 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : V5-Block Plus for PCI Express
// File : pcie_blk_cf_arb.v
//--------------------------------------------------------------------------------
//--------------------------------------------------------------------------------
//--
//-- Description: CFG Arbiter. This module will send messages as triggered
//-- by the err manager, power interface, or bar hit/miss logic. It sends
//-- the messages to the Tx arbiter.
//--
//--------------------------------------------------------------------------------
`timescale 1ns/1ns
`ifndef Tcq
`define Tcq 1
`endif
module pcie_blk_cf_arb
(
// PCIe Block clock and reset
input wire clk,
input wire rst_n,
// Device,Bus,Func#
input [7:0] cfg_bus_number,
input [4:0] cfg_device_number,
input [2:0] cfg_function_number,
input [15:0] msi_data,
input [31:0] msi_laddr,
input [31:0] msi_haddr,
// Interface to Error Manager
input send_cor,
input send_nfl,
input send_ftl,
input send_cplt,
input send_cplu,
input [49:0] cmt_rd_hdr,
input [49:0] cfg_rd_hdr,
output reg [49:0] request_data = 0,
output reg grant = 0,
output reg cs_is_cplu = 0,
output reg cs_is_cplt = 0,
output reg cs_is_cor = 0,
output reg cs_is_nfl = 0,
output reg cs_is_ftl = 0,
output reg cs_is_pm = 0,
// Interface from Power Manager
input send_pmeack,
output reg cs_is_intr = 0,
input [7:0] intr_vector,
input [1:0] intr_req_type,
input intr_req_valid,
// Output to Tx Block (via arbiter) to generate message/UR Completions
output reg [63:0] cfg_arb_td = 0,
output reg [7:0] cfg_arb_trem_n = 1,
output reg cfg_arb_tsof_n = 1,
output reg cfg_arb_teof_n = 1,
output reg cfg_arb_tsrc_rdy_n = 1,
input cfg_arb_tdst_rdy_n
);
reg [3:0] cs_fsm; // current state
reg [1:0] state;
parameter [3:0] st_reset = 0,
st_clear_count = 9, // Added these three
st_clear_send = 10, // states 'cos counter takes 2 cycles to clear!
st_cleared_all = 11, // and "send_***" signals are flopped; so 1 more-cycle is needed
st_cplu_req = 1,
st_cplt_req = 2,
st_ftl_req = 3,
st_nfl_req = 4,
st_cor_req = 5,
st_send_pm = 6,
st_send_msi_32 = 7,
st_send_msi_64 = 8,
st_code_send_asrt = 12,
st_code_send_d_asrt = 13;
parameter type_msg_intr = 5'b10100;
parameter UR = 1'b0;
parameter CA = 1'b1;
parameter LOCK = 1'b0;
parameter rsvd_BYTE0 = 1'b0;
parameter fmt_mwr_3dwhdr_data = 2'b10;
parameter fmt_mwr_4dwhdr_data = 2'b11;
parameter fmt_msg = 2'b01; // Table 2-3
parameter fmt_cpl = 2'b00; // Table 2-3
parameter type_mwr = 5'b0_0000;
parameter type_msg = 5'b1_0000; // all msgs routed to root-complex (Table 2-11)
parameter type_cpl = 5'b0_1010; // all msgs routed to root-complex (Table 2-11)
parameter type_cpllock = 5'b0_1011;
parameter rsvd_msb_BYTE1 = 1'b0;
parameter tc_param = 3'b000;
parameter rsvd_BYTE1 = 4'b0000;
parameter td = 1'b0;
parameter ep = 1'b0;
parameter attr_param = 2'b00;
parameter rsvd_BYTE2 = 2'b00;
parameter len_98 = 2'b00;
parameter len_70_BYTE3 = 8'b0000_0000;
parameter len_70_mwrd_BYTE3 = 8'b0000_0001;
wire [7:0] completer_id_BYTE4 = cfg_bus_number[7:0];
wire [7:0] completer_id_BYTE5 = {cfg_device_number[4:0],cfg_function_number[2:0]};
parameter compl_status_sc = 3'b000;
parameter compl_status_ur = 3'b001;
parameter compl_status_ca = 3'b100;
parameter bcm = 1'b0;
parameter msg_code_err_cor_BYTE7 = 8'b0011_0000;
parameter msg_code_err_nfl_BYTE7 = 8'b0011_0001;
parameter msg_code_err_ftl_BYTE7 = 8'b0011_0011;
parameter rsvd_BYTE11 = 1'b0;
parameter msg_code_pm_pme_BYTE7 = 8'b0001_1000;
parameter msg_code_pme_to_ack_BYTE7 = 8'b0001_1011;
parameter type_msg_pme_to_ack = 5'b1_0101;
parameter last_dw_byte_enable_BYTE7 = 4'b0000;
parameter first_dw_byte_enable_BYTE7 = 4'b1111;
parameter msg_code_asrt_inta_BYTE7 = 8'b0010_0000;
parameter msg_code_asrt_intb_BYTE7 = 8'b0010_0001;
parameter msg_code_asrt_intc_BYTE7 = 8'b0010_0010;
parameter msg_code_asrt_intd_BYTE7 = 8'b0010_0011;
parameter msg_code_d_asrt_inta_BYTE7 = 8'b0010_0100;
parameter msg_code_d_asrt_intb_BYTE7 = 8'b0010_0101;
parameter msg_code_d_asrt_intc_BYTE7 = 8'b0010_0110;
parameter msg_code_d_asrt_intd_BYTE7 = 8'b0010_0111;
wire [31:0] swizzle_msi_data = { intr_vector[7:0] // Byte0
,msi_data[15:8] // Byte1
,8'h0 // Byte2
,8'h0 // Byte3
};
reg [7:0] byte_00, byte_01, byte_02, byte_03,
byte_04, byte_05, byte_06, byte_07,
byte_08, byte_09, byte_10, byte_11;
reg [31:0] bytes_12_to_15 = 0;
reg reg_req_pkt_tx = 0;
reg [1:0] wait_cntr = 0;
always @(posedge clk) begin
if (~rst_n) begin
cs_fsm <= #`Tcq 4'b0000;
request_data <= #`Tcq 0;
cs_is_cplu <= #`Tcq 1'b0;
cs_is_cplt <= #`Tcq 1'b0;
cs_is_cor <= #`Tcq 1'b0;
cs_is_nfl <= #`Tcq 1'b0;
cs_is_ftl <= #`Tcq 1'b0;
cs_is_pm <= #`Tcq 1'b0;
cs_is_intr <= #`Tcq 1'b0;
byte_00 <= #`Tcq 0;
byte_01 <= #`Tcq 0;
byte_02 <= #`Tcq 0;
byte_03 <= #`Tcq 0;
byte_04 <= #`Tcq 0;
byte_05 <= #`Tcq 0;
byte_06 <= #`Tcq 0;
byte_07 <= #`Tcq 0;
byte_08 <= #`Tcq 0;
byte_09 <= #`Tcq 0;
byte_10 <= #`Tcq 0;
byte_11 <= #`Tcq 0;
bytes_12_to_15 <= #`Tcq 0;
reg_req_pkt_tx <= #`Tcq 1'b0;
end
else begin
case (cs_fsm) // synthesis full_case parallel_case
st_reset: begin
if (send_cplu)
cs_fsm <= #`Tcq st_cplu_req;
else if (send_cplt)
cs_fsm <= #`Tcq st_cplt_req;
else if (send_ftl)
cs_fsm <= #`Tcq st_ftl_req;
else if (send_nfl)
cs_fsm <= #`Tcq st_nfl_req;
else if (send_cor)
cs_fsm <= #`Tcq st_cor_req;
else if (send_pmeack)
cs_fsm <= #`Tcq st_send_pm;
else if (intr_req_valid)
begin
if (intr_req_type == 2'b00)
cs_fsm <= #`Tcq st_code_send_asrt;
else if (intr_req_type == 2'b01)
cs_fsm <= #`Tcq st_code_send_d_asrt;
else if (intr_req_type == 2'b10)
cs_fsm <= #`Tcq st_send_msi_32;
else if (intr_req_type == 2'b11)
cs_fsm <= #`Tcq st_send_msi_64;
end
else
cs_fsm <= #`Tcq st_reset;
request_data <= #`Tcq 0;
cs_is_cplu <= #`Tcq 1'b0;
cs_is_cplt <= #`Tcq 1'b0;
cs_is_cor <= #`Tcq 1'b0;
cs_is_nfl <= #`Tcq 1'b0;
cs_is_ftl <= #`Tcq 1'b0;
cs_is_pm <= #`Tcq 1'b0;
cs_is_intr <= #`Tcq 1'b0;
reg_req_pkt_tx <= #`Tcq 1'b0;
end
st_cplu_req: begin
if (grant)
cs_fsm <= #`Tcq st_clear_count;
else
cs_fsm <= #`Tcq st_cplu_req;
request_data <= #`Tcq cfg_rd_hdr;
cs_is_cplu <= #`Tcq 1'b1;
cs_is_cplt <= #`Tcq 1'b0;
cs_is_cor <= #`Tcq 1'b0;
cs_is_nfl <= #`Tcq 1'b0;
cs_is_ftl <= #`Tcq 1'b0;
cs_is_pm <= #`Tcq 1'b0;
cs_is_intr <= #`Tcq 1'b0;
////
if (cfg_rd_hdr[49] == LOCK) begin
byte_00 <= #`Tcq {rsvd_BYTE0,fmt_cpl,type_cpllock};
end else begin
byte_00 <= #`Tcq {rsvd_BYTE0,fmt_cpl,type_cpl};
end
byte_03 <= #`Tcq {len_70_BYTE3};
byte_04 <= #`Tcq {completer_id_BYTE4};
byte_05 <= #`Tcq {completer_id_BYTE5};
//byte_07 <= #`Tcq {byte_count_cpln_BYTE7};
byte_07 <= #`Tcq {cfg_rd_hdr[36:29]};
//byte_08 <= #`Tcq {msg_requester_id_BYTE4};
byte_08 <= #`Tcq {cfg_rd_hdr[23:16]};
//byte_09 <= #`Tcq {msg_requester_id_BYTE5};
byte_09 <= #`Tcq {cfg_rd_hdr[15:8]};
byte_10 <= #`Tcq cfg_rd_hdr[7:0];
//byte_11 <= #`Tcq {rsvd_BYTE11,lower_address_cpln};
byte_11 <= #`Tcq {rsvd_BYTE11,cfg_rd_hdr[47:41]};
bytes_12_to_15 <= #`Tcq 0;
reg_req_pkt_tx <= #`Tcq 1'b1;
if (cfg_rd_hdr[48] == UR) begin
//byte_01 <= #`Tcq {rsvd_msb_BYTE1,tc_ur,rsvd_BYTE1};
byte_01 <= #`Tcq {rsvd_msb_BYTE1,cfg_rd_hdr[28:26],rsvd_BYTE1};
//byte_02 <= #`Tcq {td,ep,attr_ur,rsvd_BYTE2,len_98};
byte_02 <= #`Tcq {td,ep,cfg_rd_hdr[25:24],rsvd_BYTE2,len_98};
//byte_06 <= #`Tcq {compl_status_ur,bcm,byte_count_cpln_BYTE6};
byte_06 <= #`Tcq {compl_status_ur,bcm,cfg_rd_hdr[40:37]};
end else begin // CA
//byte_01 <= #`Tcq {rsvd_msb_BYTE1,tc_ur,rsvd_BYTE1};
byte_01 <= #`Tcq {rsvd_msb_BYTE1,cfg_rd_hdr[28:26],rsvd_BYTE1};
//byte_02 <= #`Tcq {td,ep,attr_ur,rsvd_BYTE2,len_98};
byte_02 <= #`Tcq {td,ep,cfg_rd_hdr[25:24],rsvd_BYTE2,len_98};
//byte_06 <= #`Tcq {compl_status_ca,bcm,byte_count_cpln_BYTE6};
byte_06 <= #`Tcq {compl_status_ca,bcm,cfg_rd_hdr[40:37]};
end
end
st_cplt_req: begin
if (grant)
cs_fsm <= #`Tcq st_clear_count;
else
cs_fsm <= #`Tcq st_cplt_req;
request_data <= #`Tcq cmt_rd_hdr;
cs_is_cplt <= #`Tcq 1'b1;
cs_is_cplu <= #`Tcq 1'b0;
cs_is_cor <= #`Tcq 1'b0;
cs_is_nfl <= #`Tcq 1'b0;
cs_is_ftl <= #`Tcq 1'b0;
cs_is_pm <= #`Tcq 1'b0;
cs_is_intr <= #`Tcq 1'b0;
////
if (cmt_rd_hdr[49] == LOCK) begin
byte_00 <= #`Tcq {rsvd_BYTE0,fmt_cpl,type_cpllock};
end else begin
byte_00 <= #`Tcq {rsvd_BYTE0,fmt_cpl,type_cpl};
end
byte_03 <= #`Tcq {len_70_BYTE3};
byte_04 <= #`Tcq {completer_id_BYTE4};
byte_05 <= #`Tcq {completer_id_BYTE5};
byte_07 <= #`Tcq {cmt_rd_hdr[36:29]};
byte_08 <= #`Tcq {cmt_rd_hdr[23:16]};
byte_09 <= #`Tcq {cmt_rd_hdr[15:8]};
byte_10 <= #`Tcq cmt_rd_hdr[7:0];
byte_11 <= #`Tcq {rsvd_BYTE11,cmt_rd_hdr[47:41]};
bytes_12_to_15 <= #`Tcq 0;
reg_req_pkt_tx <= #`Tcq 1'b1;
if (cmt_rd_hdr[48] == UR) begin
byte_01 <= #`Tcq {rsvd_msb_BYTE1,cmt_rd_hdr[28:26],rsvd_BYTE1};
byte_02 <= #`Tcq {td,ep,cmt_rd_hdr[25:24],rsvd_BYTE2,len_98};
byte_06 <= #`Tcq {compl_status_ur,bcm,cmt_rd_hdr[40:37]};
end else begin // CA
byte_01 <= #`Tcq {rsvd_msb_BYTE1,cmt_rd_hdr[28:26],rsvd_BYTE1};
byte_02 <= #`Tcq {td,ep,cmt_rd_hdr[25:24],rsvd_BYTE2,len_98};
byte_06 <= #`Tcq {compl_status_ca,bcm,cmt_rd_hdr[40:37]};
end
end
st_ftl_req: begin
if (grant)
cs_fsm <= #`Tcq st_clear_count;
else
cs_fsm <= #`Tcq st_ftl_req;
request_data <= #`Tcq 0;
cs_is_ftl <= #`Tcq 1'b1;
cs_is_cplu <= #`Tcq 1'b0;
cs_is_cplt <= #`Tcq 1'b0;
cs_is_cor <= #`Tcq 1'b0;
cs_is_nfl <= #`Tcq 1'b0;
cs_is_pm <= #`Tcq 1'b0;
cs_is_intr <= #`Tcq 1'b0;
////
byte_00 <= #`Tcq {rsvd_BYTE0,fmt_msg,type_msg};
byte_01 <= #`Tcq {rsvd_msb_BYTE1,tc_param,rsvd_BYTE1};
byte_02 <= #`Tcq {td,ep,attr_param,rsvd_BYTE2,len_98};
byte_03 <= #`Tcq {len_70_BYTE3};
byte_04 <= #`Tcq {completer_id_BYTE4};
byte_05 <= #`Tcq {completer_id_BYTE5};
byte_06 <= #`Tcq 8'h0;
byte_07 <= #`Tcq {msg_code_err_ftl_BYTE7};
byte_08 <= #`Tcq 0;
byte_09 <= #`Tcq 0;
byte_10 <= #`Tcq 0;
byte_11 <= #`Tcq 0;
bytes_12_to_15 <= #`Tcq 0;
reg_req_pkt_tx <= #`Tcq 1'b1;
end
st_nfl_req: begin
if (grant)
cs_fsm <= #`Tcq st_clear_count;
else
cs_fsm <= #`Tcq st_nfl_req;
request_data <= #`Tcq 0;
cs_is_nfl <= #`Tcq 1'b1;
cs_is_cplu <= #`Tcq 1'b0;
cs_is_cplt <= #`Tcq 1'b0;
cs_is_cor <= #`Tcq 1'b0;
cs_is_ftl <= #`Tcq 1'b0;
cs_is_pm <= #`Tcq 1'b0;
cs_is_intr <= #`Tcq 1'b0;
////
byte_00 <= #`Tcq {rsvd_BYTE0,fmt_msg,type_msg};
byte_01 <= #`Tcq {rsvd_msb_BYTE1,tc_param,rsvd_BYTE1};
byte_02 <= #`Tcq {td,ep,attr_param,rsvd_BYTE2,len_98};
byte_03 <= #`Tcq {len_70_BYTE3};
byte_04 <= #`Tcq {completer_id_BYTE4};
byte_05 <= #`Tcq {completer_id_BYTE5};
byte_06 <= #`Tcq 8'h0;
byte_07 <= #`Tcq {msg_code_err_nfl_BYTE7};
byte_08 <= #`Tcq 0;
byte_09 <= #`Tcq 0;
byte_10 <= #`Tcq 0;
byte_11 <= #`Tcq 0;
bytes_12_to_15 <= #`Tcq 0;
reg_req_pkt_tx <= #`Tcq 1'b1;
end
st_cor_req: begin
if (grant)
cs_fsm <= #`Tcq st_clear_count;
else
cs_fsm <= #`Tcq st_cor_req;
request_data <= #`Tcq 0;
cs_is_cor <= #`Tcq 1'b1;
cs_is_cplu <= #`Tcq 1'b0;
cs_is_cplt <= #`Tcq 1'b0;
cs_is_nfl <= #`Tcq 1'b0;
cs_is_ftl <= #`Tcq 1'b0;
cs_is_pm <= #`Tcq 1'b0;
cs_is_intr <= #`Tcq 1'b0;
////
byte_00 <= #`Tcq {rsvd_BYTE0,fmt_msg,type_msg};
byte_01 <= #`Tcq {rsvd_msb_BYTE1,tc_param,rsvd_BYTE1};
byte_02 <= #`Tcq {td,ep,attr_param,rsvd_BYTE2,len_98};
byte_03 <= #`Tcq {len_70_BYTE3};
byte_04 <= #`Tcq {completer_id_BYTE4};
byte_05 <= #`Tcq {completer_id_BYTE5};
byte_06 <= #`Tcq 8'h0;
byte_07 <= #`Tcq {msg_code_err_cor_BYTE7};
byte_08 <= #`Tcq 0;
byte_09 <= #`Tcq 0;
byte_10 <= #`Tcq 0;
byte_11 <= #`Tcq 0;
bytes_12_to_15 <= #`Tcq 0;
reg_req_pkt_tx <= #`Tcq 1'b1;
end
st_send_pm: begin
if (grant)
cs_fsm <= #`Tcq st_clear_count;
else
cs_fsm <= #`Tcq st_send_pm;
request_data <= #`Tcq 0;
cs_is_cor <= #`Tcq 1'b0;
cs_is_cplu <= #`Tcq 1'b0;
cs_is_cplt <= #`Tcq 1'b0;
cs_is_nfl <= #`Tcq 1'b0;
cs_is_ftl <= #`Tcq 1'b0;
cs_is_pm <= #`Tcq 1'b1;
cs_is_intr <= #`Tcq 1'b0;
////
byte_01 <= #`Tcq {rsvd_msb_BYTE1,tc_param,rsvd_BYTE1};
byte_02 <= #`Tcq {td,ep,attr_param,rsvd_BYTE2,len_98};
byte_03 <= #`Tcq {len_70_BYTE3};
byte_04 <= #`Tcq {completer_id_BYTE4};
byte_05 <= #`Tcq {completer_id_BYTE5};
byte_06 <= #`Tcq 8'h0;
byte_08 <= #`Tcq 0;
byte_09 <= #`Tcq 0;
byte_10 <= #`Tcq 0;
byte_11 <= #`Tcq 0;
bytes_12_to_15 <= #`Tcq 0;
//if (pme_ack_bar) begin
// byte_07 <= #`Tcq {msg_code_pm_pme_BYTE7};
// byte_00 <= #`Tcq {rsvd_BYTE0,fmt_msg,type_msg};
//end
//else begin
byte_07 <= #`Tcq {msg_code_pme_to_ack_BYTE7};
byte_00 <= #`Tcq {rsvd_BYTE0,fmt_msg,type_msg_pme_to_ack};
//end
reg_req_pkt_tx <= #`Tcq 1'b1;
end
st_code_send_asrt: begin
if (grant)
cs_fsm <= #`Tcq st_clear_count;
else
cs_fsm <= #`Tcq st_code_send_asrt;
request_data <= #`Tcq 0;
cs_is_cor <= #`Tcq 1'b0;
cs_is_cplu <= #`Tcq 1'b0;
cs_is_cplt <= #`Tcq 1'b0;
cs_is_nfl <= #`Tcq 1'b0;
cs_is_ftl <= #`Tcq 1'b0;
cs_is_pm <= #`Tcq 1'b0;
cs_is_intr <= #`Tcq 1'b1;
////
byte_00 <= #`Tcq {rsvd_BYTE0,fmt_msg,type_msg_intr};
byte_01 <= #`Tcq {rsvd_msb_BYTE1,tc_param,rsvd_BYTE1};
byte_02 <= #`Tcq {td,ep,attr_param,rsvd_BYTE2,len_98};
byte_03 <= #`Tcq {len_70_BYTE3};
byte_04 <= #`Tcq {completer_id_BYTE4};
byte_05 <= #`Tcq {completer_id_BYTE5};
byte_06 <= #`Tcq 8'h0;
byte_08 <= #`Tcq 0;
byte_09 <= #`Tcq 0;
byte_10 <= #`Tcq 0;
byte_11 <= #`Tcq 0;
bytes_12_to_15 <= #`Tcq 0;
reg_req_pkt_tx <= #`Tcq 1'b1;
case (intr_vector[1:0]) // synthesis full_case parallel_case
2'b00: byte_07 <= #`Tcq {msg_code_asrt_inta_BYTE7};
2'b01: byte_07 <= #`Tcq {msg_code_asrt_intb_BYTE7};
2'b10: byte_07 <= #`Tcq {msg_code_asrt_intc_BYTE7};
2'b11: byte_07 <= #`Tcq {msg_code_asrt_intd_BYTE7};
endcase
end
st_code_send_d_asrt: begin
if (grant)
cs_fsm <= #`Tcq st_clear_count;
else
cs_fsm <= #`Tcq st_code_send_d_asrt;
request_data <= #`Tcq 0;
cs_is_cor <= #`Tcq 1'b0;
cs_is_cplu <= #`Tcq 1'b0;
cs_is_cplt <= #`Tcq 1'b0;
cs_is_nfl <= #`Tcq 1'b0;
cs_is_ftl <= #`Tcq 1'b0;
cs_is_pm <= #`Tcq 1'b0;
cs_is_intr <= #`Tcq 1'b1;
////
byte_00 <= #`Tcq {rsvd_BYTE0,fmt_msg,type_msg_intr};
byte_01 <= #`Tcq {rsvd_msb_BYTE1,tc_param,rsvd_BYTE1};
byte_02 <= #`Tcq {td,ep,attr_param,rsvd_BYTE2,len_98};
byte_03 <= #`Tcq {len_70_BYTE3};
byte_04 <= #`Tcq {completer_id_BYTE4};
byte_05 <= #`Tcq {completer_id_BYTE5};
byte_06 <= #`Tcq 8'h0;
byte_08 <= #`Tcq 0;
byte_09 <= #`Tcq 0;
byte_10 <= #`Tcq 0;
byte_11 <= #`Tcq 0;
bytes_12_to_15 <= #`Tcq 0;
reg_req_pkt_tx <= #`Tcq 1'b1;
case (intr_vector[1:0]) // synthesis full_case parallel_case
2'b00: byte_07 <= #`Tcq {msg_code_d_asrt_inta_BYTE7};
2'b01: byte_07 <= #`Tcq {msg_code_d_asrt_intb_BYTE7};
2'b10: byte_07 <= #`Tcq {msg_code_d_asrt_intc_BYTE7};
2'b11: byte_07 <= #`Tcq {msg_code_d_asrt_intd_BYTE7};
endcase
end
st_send_msi_32: begin
if (grant)
cs_fsm <= #`Tcq st_clear_count;
else
cs_fsm <= #`Tcq st_send_msi_32;
request_data <= #`Tcq 0;
cs_is_cor <= #`Tcq 1'b0;
cs_is_cplu <= #`Tcq 1'b0;
cs_is_cplt <= #`Tcq 1'b0;
cs_is_nfl <= #`Tcq 1'b0;
cs_is_ftl <= #`Tcq 1'b0;
cs_is_pm <= #`Tcq 1'b0;
cs_is_intr <= #`Tcq 1'b1;
////
byte_00 <= #`Tcq {rsvd_BYTE0,fmt_mwr_3dwhdr_data,type_mwr};
byte_01 <= #`Tcq {rsvd_msb_BYTE1,tc_param,rsvd_BYTE1};
byte_02 <= #`Tcq {td,ep,attr_param,rsvd_BYTE2,len_98};
byte_03 <= #`Tcq {len_70_mwrd_BYTE3};
byte_04 <= #`Tcq {completer_id_BYTE4};
byte_05 <= #`Tcq {completer_id_BYTE5};
byte_06 <= #`Tcq 8'h0;
byte_07 <= #`Tcq {last_dw_byte_enable_BYTE7,first_dw_byte_enable_BYTE7};
byte_08 <= #`Tcq msi_laddr[31:24];
byte_09 <= #`Tcq msi_laddr[23:16];
byte_10 <= #`Tcq msi_laddr[15:08];
byte_11 <= #`Tcq {msi_laddr[07:02],2'b00};
bytes_12_to_15 <= #`Tcq swizzle_msi_data;
reg_req_pkt_tx <= #`Tcq 1'b1;
end
st_send_msi_64: begin
if (grant)
cs_fsm <= #`Tcq st_clear_count;
else
cs_fsm <= #`Tcq st_send_msi_64;
request_data <= #`Tcq 0;
cs_is_cor <= #`Tcq 1'b0;
cs_is_cplu <= #`Tcq 1'b0;
cs_is_cplt <= #`Tcq 1'b0;
cs_is_nfl <= #`Tcq 1'b0;
cs_is_ftl <= #`Tcq 1'b0;
cs_is_pm <= #`Tcq 1'b0;
cs_is_intr <= #`Tcq 1'b1;
////
byte_00 <= #`Tcq {rsvd_BYTE0,fmt_mwr_4dwhdr_data,type_mwr};
byte_01 <= #`Tcq {rsvd_msb_BYTE1,tc_param,rsvd_BYTE1};
byte_02 <= #`Tcq {td,ep,attr_param,rsvd_BYTE2,len_98};
byte_03 <= #`Tcq {len_70_mwrd_BYTE3};
byte_04 <= #`Tcq {completer_id_BYTE4};
byte_05 <= #`Tcq {completer_id_BYTE5};
byte_06 <= #`Tcq 8'h0;
byte_07 <= #`Tcq {last_dw_byte_enable_BYTE7,first_dw_byte_enable_BYTE7};
byte_08 <= #`Tcq msi_haddr[31:24];
byte_09 <= #`Tcq msi_haddr[23:16];
byte_10 <= #`Tcq msi_haddr[15:08];
byte_11 <= #`Tcq msi_haddr[07:00];
bytes_12_to_15 <= #`Tcq {msi_laddr[31:2],2'b00};
reg_req_pkt_tx <= #`Tcq 1'b1;
end
st_clear_count: begin
cs_fsm <= #`Tcq st_clear_send;
request_data <= #`Tcq 0;
cs_is_cplu <= #`Tcq 1'b0;
cs_is_cplt <= #`Tcq 1'b0;
cs_is_cor <= #`Tcq 1'b0;
cs_is_nfl <= #`Tcq 1'b0;
cs_is_ftl <= #`Tcq 1'b0;
cs_is_pm <= #`Tcq 1'b0;
cs_is_intr <= #`Tcq 1'b0;
reg_req_pkt_tx <= #`Tcq 1'b0;
end
st_clear_send: begin
cs_fsm <= #`Tcq st_cleared_all;
request_data <= #`Tcq 0;
cs_is_cplu <= #`Tcq 1'b0;
cs_is_cplt <= #`Tcq 1'b0;
cs_is_cor <= #`Tcq 1'b0;
cs_is_nfl <= #`Tcq 1'b0;
cs_is_ftl <= #`Tcq 1'b0;
cs_is_pm <= #`Tcq 1'b0;
cs_is_intr <= #`Tcq 1'b0;
reg_req_pkt_tx <= #`Tcq 1'b0;
end
st_cleared_all: begin
cs_fsm <= #`Tcq st_reset;
request_data <= #`Tcq 0;
cs_is_cplu <= #`Tcq 1'b0;
cs_is_cplt <= #`Tcq 1'b0;
cs_is_cor <= #`Tcq 1'b0;
cs_is_nfl <= #`Tcq 1'b0;
cs_is_ftl <= #`Tcq 1'b0;
cs_is_pm <= #`Tcq 1'b0;
cs_is_intr <= #`Tcq 1'b0;
reg_req_pkt_tx <= #`Tcq 1'b0;
end
default: begin
cs_fsm <= #`Tcq st_reset;
request_data <= #`Tcq 0;
cs_is_cplu <= #`Tcq 1'b0;
cs_is_cplt <= #`Tcq 1'b0;
cs_is_cor <= #`Tcq 1'b0;
cs_is_nfl <= #`Tcq 1'b0;
cs_is_ftl <= #`Tcq 1'b0;
cs_is_pm <= #`Tcq 1'b0;
cs_is_intr <= #`Tcq 1'b0;
reg_req_pkt_tx <= #`Tcq 1'b0;
end
endcase
end
end
wire [159:0] tlp_data= {swizzle_msi_data,
bytes_12_to_15,
byte_08,byte_09,byte_10,byte_11,
byte_04,byte_05,byte_06,byte_07,
byte_00,byte_01,byte_02,byte_03};
wire pkt_3dw = (tlp_data[30:29]==2'b00); // fmt type is pkt_3dw tlp
wire pkt_5dw = (tlp_data[30:29]==2'b11); // fmt type is pkt_5dw tlp
parameter TX_IDLE = 2'b00;
parameter TX_DW1 = 2'b01;
parameter TX_DW3 = 2'b10;
parameter SEND_GRANT = 2'b11;
always @(posedge clk)
begin
if (~rst_n) begin
cfg_arb_tsof_n <= #`Tcq 1;
cfg_arb_teof_n <= #`Tcq 1;
cfg_arb_td <= #`Tcq 64'h0000_0000;
cfg_arb_trem_n <= #`Tcq 8'hff;
cfg_arb_tsrc_rdy_n <= #`Tcq 1;
grant <= #`Tcq 0;
state <= #`Tcq TX_IDLE;
end
else
case (state) //synthesis full_case parallel_case
TX_IDLE : begin
grant <= #`Tcq 0;
cfg_arb_td[31:0] <= #`Tcq tlp_data[63:32];
cfg_arb_td[63:32] <= #`Tcq tlp_data[31:0];
cfg_arb_teof_n <= #`Tcq 1;
cfg_arb_trem_n <= #`Tcq 8'h00;
if (reg_req_pkt_tx && (~|wait_cntr)) begin
cfg_arb_tsrc_rdy_n <= #`Tcq 0;
cfg_arb_tsof_n <= #`Tcq 0;
end
else begin
cfg_arb_tsrc_rdy_n <= #`Tcq 1;
cfg_arb_tsof_n <= #`Tcq 1;
end
if (reg_req_pkt_tx && (~|wait_cntr)) begin
state <= #`Tcq TX_DW1;
end
end
TX_DW1 : begin
cfg_arb_tsrc_rdy_n <= #`Tcq 0;
cfg_arb_trem_n <= #`Tcq pkt_3dw ? 8'h0f : 8'h00 ;
if (!cfg_arb_tdst_rdy_n) begin
cfg_arb_td[31:0] <= #`Tcq tlp_data[127:96];
cfg_arb_td[63:32] <= #`Tcq tlp_data[95:64];
cfg_arb_tsof_n <= #`Tcq 1;
cfg_arb_teof_n <= #`Tcq pkt_5dw;
state <= #`Tcq pkt_5dw ? TX_DW3 : SEND_GRANT;
grant <= #`Tcq 0;
end
else begin
cfg_arb_td[31:0] <= #`Tcq tlp_data[63:32];
cfg_arb_td[63:32] <= #`Tcq tlp_data[31:0];
cfg_arb_tsof_n <= #`Tcq 0;
cfg_arb_teof_n <= #`Tcq 1;
state <= #`Tcq TX_DW1;
grant <= #`Tcq 0;
end
end
TX_DW3 : begin
cfg_arb_tsrc_rdy_n <= #`Tcq 0;
cfg_arb_trem_n <= #`Tcq 8'h0f;
if (!cfg_arb_tdst_rdy_n) begin
cfg_arb_td[31:0] <= #`Tcq 32'h0;
cfg_arb_td[63:32] <= #`Tcq tlp_data[159:128];
cfg_arb_tsof_n <= #`Tcq 1;
cfg_arb_teof_n <= #`Tcq 0;
state <= #`Tcq SEND_GRANT;
grant <= #`Tcq 0;
end
else begin
cfg_arb_td[31:0] <= #`Tcq tlp_data[127:96];
cfg_arb_td[63:32] <= #`Tcq tlp_data[95:64];
cfg_arb_tsof_n <= #`Tcq 1;
cfg_arb_teof_n <= #`Tcq 1;
state <= #`Tcq TX_DW3;
grant <= #`Tcq 0;
end
end
SEND_GRANT : begin
if (!cfg_arb_tdst_rdy_n) begin
cfg_arb_tsrc_rdy_n<= #`Tcq 1;
cfg_arb_tsof_n <= #`Tcq 1;
cfg_arb_teof_n <= #`Tcq 1;
state <= #`Tcq TX_IDLE;
grant <= #`Tcq 1;
end
else begin
cfg_arb_tsrc_rdy_n<= #`Tcq 0;
cfg_arb_tsof_n <= #`Tcq 1;
cfg_arb_teof_n <= #`Tcq 0;
state <= #`Tcq SEND_GRANT;
grant <= #`Tcq 0;
end
end
endcase
end
always @(posedge clk)
begin
if (~rst_n) begin
wait_cntr <= #`Tcq 0;
end else if (state == SEND_GRANT) begin
wait_cntr <= #`Tcq 2'b10;
end else if (|wait_cntr) begin
wait_cntr <= #`Tcq wait_cntr - 1;
end
end
endmodule // pcie_blk_cf_arb
|
// Name: WcaWriteDwordReg.v
//
// Copyright(c) 2013 Loctronix Corporation
// http://www.loctronix.com
//
// This program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public License
// as published by the Free Software Foundation; either version 2
// of the License, or (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
module WcaWriteDwordReg
(
input wire reset,
output wire [31:0] out, //Output data.
//Internal Interface.
input wire [11:0] rbusCtrl, // Address and control lines(12 total) { addr[7:0], readEnable, writeEnable, dataStrobe, clkbus}
inout wire [7:0] rbusData // Tri-state I/O data.
);
parameter my_addr = 0;
wire addrValid = (my_addr == rbusCtrl[11:4]);
wire write = addrValid & rbusCtrl[2];
//Sequence Registers for 4 pulse write.
reg [1:0] select;
always @(posedge rbusCtrl[0])
begin
if( reset | ~addrValid)
select <= 2'h0;
else if(rbusCtrl[1] & addrValid)
select <= select + 2'h1;
end
//Write to the selected register.
WcaRegCore8 sr3( .Data(rbusData), .Enable( write & select == 2'h3), .Aclr(reset), .Clock(rbusCtrl[0]), .Q(out[31:24]));
WcaRegCore8 sr2( .Data(rbusData), .Enable( write & select == 2'h2), .Aclr(reset), .Clock(rbusCtrl[0]), .Q(out[23:16]));
WcaRegCore8 sr1( .Data(rbusData), .Enable( write & select == 2'h1), .Aclr(reset), .Clock(rbusCtrl[0]), .Q(out[15:8]));
WcaRegCore8 sr0( .Data(rbusData), .Enable( write & select == 2'h0), .Aclr(reset), .Clock(rbusCtrl[0]), .Q(out[7:0]));
endmodule //WcaWriteDwordReg |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__AND2_PP_BLACKBOX_V
`define SKY130_FD_SC_LP__AND2_PP_BLACKBOX_V
/**
* and2: 2-input AND.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__and2 (
X ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__AND2_PP_BLACKBOX_V
|
/* verilator lint_off WIDTH */
module FIFO
#(
parameter data_width=32,
parameter size=32,
parameter device_id=1
)
(
input [data_width-1:0] data_in /*verilator public*/,
output [data_width-1:0] data_out /*verilator public*/,
input clk /*verilator public*/,
input next /*verilator public*/,
input insert /*verilator public*/,
input clear /*verilator public*/,
output full /*verilator public*/,
output empty /*verilator public*/
);
reg [data_width-1:0] mem[size];
reg [9:0] words_inside=0;
assign data_out=mem[0];
assign full=words_inside==size;
assign empty=words_inside==0;
always @(posedge clk) begin
if (!(insert&&next)) begin
if (clear)
words_inside<=0;
else if (insert && ~full)
words_inside<=words_inside+1;
else if (next && ~empty)
words_inside<=words_inside-1;
end
end
generate
genvar pos;
for (pos=0; pos<size; pos=pos+1) begin: registers
always @(posedge clk) begin
mem[pos]<=
insert^next?
insert && words_inside==pos?
data_in
:
next?
pos+1!=size?
mem[pos+1]
:
0
:
mem[pos]
:
insert&&next?
// -1 : location of
// the last word
pos<words_inside-1?
mem[pos+1]
:
data_in
:
mem[pos];
// I'm so sorry... This evil language
// made me do it.
end
end
endgenerate
endmodule
|
/*
File: axi_slave_rd.v
This file is part of the Parallella FPGA Reference Design.
Copyright (C) 2013 Adapteva, Inc.
Contributed by Roman Trogan <[email protected]>
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program (see the file COPYING). If not, see
<http://www.gnu.org/licenses/>.
*/
//# Limitations:
//# 1. Read burst cannot cross single core boundaries
module axi_slave_rd (/*AUTOARG*/
// Outputs
arready, rid, rdata, rresp, rlast, rvalid, emesh_access_inb,
emesh_write_inb, emesh_datamode_inb, emesh_ctrlmode_inb,
emesh_dstaddr_inb, emesh_srcaddr_inb, emesh_data_inb,
emesh_wr_wait_inb,
// Inputs
aclk, eclk, reset, arid, araddr, arlen, arsize, arburst, arlock,
arcache, arprot, arvalid, rready, emesh_access_outb,
emesh_write_outb, emesh_datamode_outb, emesh_ctrlmode_outb,
emesh_dstaddr_outb, emesh_srcaddr_outb, emesh_data_outb,
emesh_rd_wait_outb
);
parameter SIDW = 12; //ID Width
parameter SAW = 32; //Address Bus Width
parameter SDW = 32; //Data Bus Width
parameter ACH = SAW+SIDW+5; //Width of all used Read Address Signals
parameter DFW = 4; //Data channel Fifo address width
parameter DCH = SDW+SIDW+1; //Width of all used Read Data Signals
//#########
//# Inputs
//#########
// global signals
input aclk; // clock source of the axi bus
input eclk; // clock source of emesh interface
input reset; // reset
//########################
//# Read address channel
//########################
input [SIDW-1:0] arid; //read address ID
input [SAW-1:0] araddr; //read address
input [3:0] arlen; //burst lenght (the number of data transfers)
input [2:0] arsize; //burst size (the size of each transfer)
input [1:0] arburst; //burst type
input [1:0] arlock; //lock type (atomic characteristics)
input [3:0] arcache; //memory type
input [2:0] arprot; //protection type
input arvalid; //write address valid
//########################
//# Read data channel
//########################
input rready; //read ready
//##############################
//# From the emesh interface
//##############################
input emesh_access_outb;
input emesh_write_outb;
input [1:0] emesh_datamode_outb;
input [3:0] emesh_ctrlmode_outb;
input [31:0] emesh_dstaddr_outb;
input [31:0] emesh_srcaddr_outb;
input [31:0] emesh_data_outb;
input emesh_rd_wait_outb;
//##########
//# Outputs
//##########
//########################
//# Read address channel
//########################
output arready;//read address ready
//########################
//# Read data channel
//########################
output [SIDW-1:0] rid; //read ID tag (must match arid of the transaction)
output [SDW-1:0] rdata;//read data
output [1:0] rresp; //read response
output rlast; //read last, indicates the last transfer in burst
output rvalid;//read valid
//##############################
//# To the emesh interface
//##############################
output emesh_access_inb;
output emesh_write_inb;
output [1:0] emesh_datamode_inb;
output [3:0] emesh_ctrlmode_inb;
output [31:0] emesh_dstaddr_inb;
output [31:0] emesh_srcaddr_inb;
output [31:0] emesh_data_inb;
output emesh_wr_wait_inb;
/*AUTOINPUT*/
/*AUTOWIRE*/
//#########
//# Regs
//#########
reg [3:0] tran_len;
reg tran_go_reg;
reg [SIDW+5:0] tran_info_reg;
reg tran_last_reg;
reg [31:0] dstaddr_reg;
reg [31:0] data_reg;
reg emesh_wr_access_reg;
reg [31:0] realgn_byte;
reg dch_fifo_empty_reg;
reg [DCH-1:0] dch_fifo_reg;
//#########
//# Wires
//#########
wire arready;
wire tran_go;
wire tran_stall;
wire tran_last_int;
wire tran_last;//Indicates last data of burst (out of fifo_dch)
wire [SAW-1:0] tran_addr;
wire [1:0] tran_mode;
wire [SIDW-1:0] arid_ec;
wire [3:0] arlen_ec;
wire [3:0] arlen_new;
wire arlen_dec;
wire [3:0] arlen_upd;
wire rd_last;
wire [2:0] dalgn_ctrl;
wire byte_tran;
wire hword_tran;
wire word_tran;
wire [SIDW+5:0] tran_info;
wire emesh_wr_access;
wire dch_fifo_full;
wire [2:0] realgn_ctrl;
wire [31:0] realgn_hword;
wire byte_realgn;
wire hword_realgn;
wire word_realgn;
wire [31:0] data_realgn;
wire [SIDW-1:0] tran_id;
wire last_tran;
wire [DCH-1:0] dch_fifo_in;
wire dch_fifo_wr;
wire dch_fifo_rd;
wire dch_fifo_empty;
wire [DCH-1:0] dch_fifo_out;
wire rvalid_rready;
wire dch_advance;
wire new_burst;
//#######################################
//# Address channel synchronization FIFO
//#######################################
/*axi_slave_addrch AUTO_TEMPLATE(.aclk (aclk),
.addr (araddr[]),
.ach_fifo_empty (),
.a\(.*\) (ar\1[]),
.new_addr_sel (new_burst),
);
*/
axi_slave_addrch axi_slave_addrch(/*AUTOINST*/
// Outputs
.aready (arready), // Templated
.ach_fifo_empty (), // Templated
.tran_addr (tran_addr[SAW-1:0]),
.tran_mode (tran_mode[1:0]),
.dalgn_ctrl (dalgn_ctrl[2:0]),
.byte_tran (byte_tran),
.hword_tran (hword_tran),
.word_tran (word_tran),
.aid_ec (arid_ec[SIDW-1:0]), // Templated
.alen_ec (arlen_ec[3:0]), // Templated
.new_addr_sel (new_burst), // Templated
// Inputs
.aclk (aclk), // Templated
.eclk (eclk),
.reset (reset),
.avalid (arvalid), // Templated
.addr (araddr[SAW-1:0]), // Templated
.aid (arid[SIDW-1:0]), // Templated
.alen (arlen[3:0]), // Templated
.asize (arsize[2:0]), // Templated
.aburst (arburst[1:0]), // Templated
.tran_last (tran_last),
.tran_stall (tran_stall),
.tran_go (tran_go));
//########################
//# AXI-EMESH conversion
//########################
assign tran_go = |(arlen_new[3:0]);
assign tran_last_int = dch_fifo_wr & last_tran;
assign tran_last = tran_last_reg & ~tran_stall;
always @ (posedge eclk or posedge reset)
if(reset)
tran_last_reg <= 1'b0;
else if(tran_last_int | ~tran_stall)
tran_last_reg <= tran_last_int;
always @ (posedge eclk or posedge reset)
if(reset)
tran_len[3:0] <= 4'b0000;
else if(tran_go & ~tran_stall)
tran_len[3:0] <= arlen_new[3:0];
always @ (posedge eclk or posedge reset)
if(reset)
tran_go_reg <= 1'b0;
else if(~tran_stall)
tran_go_reg <= tran_go;
assign arlen_dec = |(tran_len[3:0]);
assign arlen_upd[3:0] = {(4){arlen_dec}} & (tran_len[3:0] - 4'b0001);
assign arlen_new[3:0] = new_burst ? arlen_ec[3:0] : arlen_upd[3:0];
assign rd_last = (tran_len[3:0] == 4'b0001);
assign tran_info[SIDW+5:0] = {arid_ec[SIDW-1:0],dalgn_ctrl[2:0],byte_tran,
hword_tran,word_tran};
always @ (posedge eclk)
if(tran_go & ~tran_stall)
tran_info_reg[SIDW+5:0] <= tran_info[SIDW+5:0];
//#############################
//# Emesh transaction creation
//#############################
assign emesh_dstaddr_inb[31:0] = tran_addr[SAW-1:0];
assign emesh_srcaddr_inb[31:0] = {`AXI_COORD,{(13-SIDW){1'b0}},
tran_info_reg[SIDW+5:0], rd_last};
assign emesh_data_inb[31:0] = 32'h00000000;
assign emesh_datamode_inb[1:0] = tran_mode[1:0];
assign emesh_ctrlmode_inb[3:0] = 4'b0000;
assign emesh_write_inb = 1'b0;
assign emesh_access_inb = tran_go_reg & ~tran_stall;
//#######################################
//# Data channel synchronization FIFO
//#######################################
assign emesh_wr_wait_inb = dch_fifo_full;
//# Incoming transaction should be sampled to prevent timing issues
assign emesh_wr_access = emesh_access_outb & emesh_write_outb &
~emesh_wr_wait_inb;
always @ (posedge eclk)
if (emesh_wr_access)
dstaddr_reg[31:0] <= emesh_dstaddr_outb[31:0];
always @ (posedge eclk)
if (emesh_wr_access)
data_reg[31:0] <= emesh_data_outb[31:0];
always @ (posedge eclk or posedge reset)
if(reset)
emesh_wr_access_reg <= 1'b0;
else if(~emesh_wr_wait_inb)
emesh_wr_access_reg <= emesh_wr_access;
//# RID
assign tran_id[SIDW-1:0] = dstaddr_reg[SIDW+6:7];
//# Data Re-alignment from the EMESH protocol
assign realgn_ctrl[2:0] = dstaddr_reg[6:4];
assign byte_realgn = dstaddr_reg[3];
assign hword_realgn = dstaddr_reg[2];
assign word_realgn = dstaddr_reg[1];
//# Last transfer
assign last_tran = dstaddr_reg[0];
always @ (realgn_ctrl[1:0] or data_reg[7:0])
begin
casez (realgn_ctrl[1:0])
2'b00 : realgn_byte[31:0] = {{(24){1'b0}},data_reg[7:0] };
2'b01 : realgn_byte[31:0] = {{(16){1'b0}},data_reg[7:0],{( 8){1'b0}}};
2'b10 : realgn_byte[31:0] = {{(8){1'b0}},data_reg[7:0],{(16){1'b0}}};
2'b11 : realgn_byte[31:0] = {data_reg[7:0],{(24){1'b0}}};
default: realgn_byte[31:0] = {{(24){1'b0}},data_reg[7:0]};
endcase // casez (realgn_ctrl[1:0])
end
assign realgn_hword[31:0] = realgn_ctrl[1] ? {data_reg[15:0],{(16){1'b0}}} :
{{(16){1'b0}},data_reg[15:0]};
assign data_realgn[31:0] = byte_realgn ? realgn_byte[31:0] :
hword_realgn ? realgn_hword[31:0]:
data_reg[31:0];
assign dch_fifo_in[DCH-1:0] = {data_realgn[31:0],tran_id[SIDW-1:0],last_tran};
assign dch_fifo_wr = emesh_wr_access_reg & ~dch_fifo_full;
assign dch_fifo_rd = ~dch_fifo_empty & (~rvalid | rvalid_rready);
assign dch_advance = rvalid_rready | ~rvalid;
/*fifo AUTO_TEMPLATE(.rd_clk (aclk),
.wr_clk (eclk),
.wr_data (dch_fifo_in[DCH-1:0]),
.rd_data (dch_fifo_out[DCH-1:0]),
.rd_fifo_empty (dch_fifo_empty),
.wr_fifo_full (dch_fifo_full),
.wr_write (dch_fifo_wr),
.rd_read (dch_fifo_rd),
);
*/
fifo #(.DW(DCH), .AW(DFW)) fifo_dch(/*AUTOINST*/
// Outputs
.rd_data (dch_fifo_out[DCH-1:0]), // Templated
.rd_fifo_empty (dch_fifo_empty), // Templated
.wr_fifo_full (dch_fifo_full), // Templated
// Inputs
.reset (reset),
.wr_clk (eclk), // Templated
.rd_clk (aclk), // Templated
.wr_write (dch_fifo_wr), // Templated
.wr_data (dch_fifo_in[DCH-1:0]), // Templated
.rd_read (dch_fifo_rd)); // Templated
//# The data is sampled after exiting FIFO to prevent timing issues
always @ (posedge aclk or posedge reset)
if(reset)
dch_fifo_empty_reg <= 1'b1;
else if(dch_advance)
dch_fifo_empty_reg <= dch_fifo_empty;
always @ (posedge aclk)
if (dch_advance)
dch_fifo_reg[DCH-1:0] <= dch_fifo_out[DCH-1:0];
assign rid[SIDW-1:0] = dch_fifo_reg[SIDW:1];
assign rresp[1:0] = 2'b00;
assign rvalid = ~dch_fifo_empty_reg;
assign rvalid_rready = rvalid & rready;
assign rdata[SDW-1:0] = dch_fifo_reg[DCH-1:SIDW+1];
assign rlast = dch_fifo_reg[0];
//# Transaction Stall
assign tran_stall = emesh_rd_wait_outb;
endmodule // axi_slave_rd
|
`timescale 1ns / 1ps
module stackMachine
#(
parameter N=8, //bits
parameter S=8 //stack size
)
(
clk,
rst,
g_input,
e_input,
o
);
input clk;
input rst;
input signed [N-1:0] g_input;
input [2:0] e_input;
output reg signed [N-1:0] o;
reg signed [N-1:0] alu;
reg signed [N-1:0] stack[S-1:0];
reg push;
reg op1;
reg op2;
integer j;
always@(*)
begin
push <= 0;
op1 <= 0;
op2 <= 0;
alu <= stack[0];
case(e_input)
3'd0://nop
begin
alu <= stack[0];
end
3'd1://add
begin
alu <= stack[0] + stack[1];
op2 <= 1'b1;
end
3'd2://sub
begin
alu <= stack[0] - stack[1];
op2 <= 1'b1;
end
3'd3://mult
begin
alu <= stack[0] * stack[1];
op2 <= 1'b1;
end
3'd4://push
begin
push <= 1;
end
3'd5://neg
begin
alu <= -1 * stack[0];
op1 <= 1'b1;
end
3'd6://and
begin
alu <= stack[0] & stack[1];
op2 <= 1'b1;
end
3'd7://or
begin
alu <= stack[0] | stack[1];
op2 <= 1'b1;
end
3'd8://xor
begin
alu <= stack[0] ^ stack[1];
op2 <= 1'b1;
end
endcase
end
always @(*)
begin
if(push)
begin
o <= g_input;
end
else
begin
o <= alu;
end
end
always@(posedge clk or posedge rst)
begin
if(rst)
begin
for(j=0;j<S;j=j+1)
begin
stack[j] <= 0;
end
end
else
begin
if(push)
begin
stack[0] <= g_input;
for(j=1;j<S;j=j+1)
begin
stack[j] <= stack[j-1];
end
end
else if(op1)
begin
stack[0] <= alu;
end
else if(op2)
begin
stack[0] <= alu;
for(j=1;j<S-1;j=j+1)
begin
stack[j] <= stack[j+1];
end
end
end
end
endmodule
|
/*------------------------------------------------------------------------------
* This code was generated by Spiral Multiplier Block Generator, www.spiral.net
* Copyright (c) 2006, Carnegie Mellon University
* All rights reserved.
* The code is distributed under a BSD style license
* (see http://www.opensource.org/licenses/bsd-license.php)
*------------------------------------------------------------------------------ */
/* ./multBlockGen.pl 10060 -fractionalBits 0*/
module multiplier_block (
i_data0,
o_data0
);
// Port mode declarations:
input [31:0] i_data0;
output [31:0]
o_data0;
//Multipliers:
wire [31:0]
w1,
w4,
w5,
w40,
w45,
w2560,
w2515,
w10060;
assign w1 = i_data0;
assign w10060 = w2515 << 2;
assign w2515 = w2560 - w45;
assign w2560 = w5 << 9;
assign w4 = w1 << 2;
assign w40 = w5 << 3;
assign w45 = w5 + w40;
assign w5 = w1 + w4;
assign o_data0 = w10060;
//multiplier_block area estimate = 5119.32965016029;
endmodule //multiplier_block
module surround_with_regs(
i_data0,
o_data0,
clk
);
// Port mode declarations:
input [31:0] i_data0;
output [31:0] o_data0;
reg [31:0] o_data0;
input clk;
reg [31:0] i_data0_reg;
wire [30:0] o_data0_from_mult;
always @(posedge clk) begin
i_data0_reg <= i_data0;
o_data0 <= o_data0_from_mult;
end
multiplier_block mult_blk(
.i_data0(i_data0_reg),
.o_data0(o_data0_from_mult)
);
endmodule
|
/*
* VGA top level file
* Copyright (C) 2010 Zeus Gomez Marmolejo <[email protected]>
*
* This file is part of the Zet processor. This processor is free
* hardware; you can redistribute it and/or modify it under the terms of
* the GNU General Public License as published by the Free Software
* Foundation; either version 3, or (at your option) any later version.
*
* Zet is distrubuted in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
* License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Zet; see the file COPYING. If not, see
* <http://www.gnu.org/licenses/>.
*/
module vga (
// Wishbone signals
input wb_clk_i, // 25 Mhz VDU clock
input wb_rst_i,
input [15:0] wb_dat_i,
output [15:0] wb_dat_o,
input [16:1] wb_adr_i,
input wb_we_i,
input wb_tga_i,
input [ 1:0] wb_sel_i,
input wb_stb_i,
input wb_cyc_i,
output wb_ack_o,
// VGA pad signals
output [ 3:0] vga_red_o,
output [ 3:0] vga_green_o,
output [ 3:0] vga_blue_o,
output horiz_sync,
output vert_sync,
// CSR SRAM master interface
output [17:1] csrm_adr_o,
output [ 1:0] csrm_sel_o,
output csrm_we_o,
output [15:0] csrm_dat_o,
input [15:0] csrm_dat_i
);
// Registers and nets
//
// csr address
reg [17:1] csr_adr_i;
reg csr_stb_i;
// Config wires
wire [15:0] conf_wb_dat_o;
wire conf_wb_ack_o;
// Mem wires
wire [15:0] mem_wb_dat_o;
wire mem_wb_ack_o;
// LCD wires
wire [17:1] csr_adr_o;
wire [15:0] csr_dat_i;
wire csr_stb_o;
wire v_retrace;
wire vh_retrace;
wire w_vert_sync;
// VGA configuration registers
wire shift_reg1;
wire graphics_alpha;
wire memory_mapping1;
wire [ 1:0] write_mode;
wire [ 1:0] raster_op;
wire read_mode;
wire [ 7:0] bitmask;
wire [ 3:0] set_reset;
wire [ 3:0] enable_set_reset;
wire [ 3:0] map_mask;
wire x_dotclockdiv2;
wire chain_four;
wire [ 1:0] read_map_select;
wire [ 3:0] color_compare;
wire [ 3:0] color_dont_care;
// Wishbone master to SRAM
wire [17:1] wbm_adr_o;
wire [ 1:0] wbm_sel_o;
wire wbm_we_o;
wire [15:0] wbm_dat_o;
wire [15:0] wbm_dat_i;
wire wbm_stb_o;
wire wbm_ack_i;
wire stb;
// CRT wires
wire [ 5:0] cur_start;
wire [ 5:0] cur_end;
wire [15:0] start_addr;
wire [ 4:0] vcursor;
wire [ 6:0] hcursor;
wire [ 6:0] horiz_total;
wire [ 6:0] end_horiz;
wire [ 6:0] st_hor_retr;
wire [ 4:0] end_hor_retr;
wire [ 9:0] vert_total;
wire [ 9:0] end_vert;
wire [ 9:0] st_ver_retr;
wire [ 3:0] end_ver_retr;
// attribute_ctrl wires
wire [3:0] pal_addr;
wire pal_we;
wire [7:0] pal_read;
wire [7:0] pal_write;
// dac_regs wires
wire dac_we;
wire [1:0] dac_read_data_cycle;
wire [7:0] dac_read_data_register;
wire [3:0] dac_read_data;
wire [1:0] dac_write_data_cycle;
wire [7:0] dac_write_data_register;
wire [3:0] dac_write_data;
// Module instances
//
vga_config_iface config_iface (
.wb_clk_i (wb_clk_i),
.wb_rst_i (wb_rst_i),
.wb_dat_i (wb_dat_i),
.wb_dat_o (conf_wb_dat_o),
.wb_adr_i (wb_adr_i[4:1]),
.wb_we_i (wb_we_i),
.wb_sel_i (wb_sel_i),
.wb_stb_i (stb & wb_tga_i),
.wb_ack_o (conf_wb_ack_o),
.shift_reg1 (shift_reg1),
.graphics_alpha (graphics_alpha),
.memory_mapping1 (memory_mapping1),
.write_mode (write_mode),
.raster_op (raster_op),
.read_mode (read_mode),
.bitmask (bitmask),
.set_reset (set_reset),
.enable_set_reset (enable_set_reset),
.map_mask (map_mask),
.x_dotclockdiv2 (x_dotclockdiv2),
.chain_four (chain_four),
.read_map_select (read_map_select),
.color_compare (color_compare),
.color_dont_care (color_dont_care),
.pal_addr (pal_addr),
.pal_we (pal_we),
.pal_read (pal_read),
.pal_write (pal_write),
.dac_we (dac_we),
.dac_read_data_cycle (dac_read_data_cycle),
.dac_read_data_register (dac_read_data_register),
.dac_read_data (dac_read_data),
.dac_write_data_cycle (dac_write_data_cycle),
.dac_write_data_register (dac_write_data_register),
.dac_write_data (dac_write_data),
.cur_start (cur_start),
.cur_end (cur_end),
.start_addr (start_addr),
.vcursor (vcursor),
.hcursor (hcursor),
.horiz_total (horiz_total),
.end_horiz (end_horiz),
.st_hor_retr (st_hor_retr),
.end_hor_retr (end_hor_retr),
.vert_total (vert_total),
.end_vert (end_vert),
.st_ver_retr (st_ver_retr),
.end_ver_retr (end_ver_retr),
.v_retrace (v_retrace),
.vh_retrace (vh_retrace)
);
vga_lcd lcd (
.clk (wb_clk_i),
.rst (wb_rst_i),
.shift_reg1 (shift_reg1),
.graphics_alpha (graphics_alpha),
.pal_addr (pal_addr),
.pal_we (pal_we),
.pal_read (pal_read),
.pal_write (pal_write),
.dac_we (dac_we),
.dac_read_data_cycle (dac_read_data_cycle),
.dac_read_data_register (dac_read_data_register),
.dac_read_data (dac_read_data),
.dac_write_data_cycle (dac_write_data_cycle),
.dac_write_data_register (dac_write_data_register),
.dac_write_data (dac_write_data),
.csr_adr_o (csr_adr_o),
.csr_dat_i (csr_dat_i),
.csr_stb_o (csr_stb_o),
.vga_red_o (vga_red_o),
.vga_green_o (vga_green_o),
.vga_blue_o (vga_blue_o),
.horiz_sync (horiz_sync),
.vert_sync (w_vert_sync),
.cur_start (cur_start),
.cur_end (cur_end),
.vcursor (vcursor),
.hcursor (hcursor),
.horiz_total (horiz_total),
.end_horiz (end_horiz),
.st_hor_retr (st_hor_retr),
.end_hor_retr (end_hor_retr),
.vert_total (vert_total),
.end_vert (end_vert),
.st_ver_retr (st_ver_retr),
.end_ver_retr (end_ver_retr),
.x_dotclockdiv2 (x_dotclockdiv2),
.v_retrace (v_retrace),
.vh_retrace (vh_retrace)
);
vga_cpu_mem_iface cpu_mem_iface (
.wb_clk_i (wb_clk_i),
.wb_rst_i (wb_rst_i),
.wbs_adr_i (wb_adr_i),
.wbs_sel_i (wb_sel_i),
.wbs_we_i (wb_we_i),
.wbs_dat_i (wb_dat_i),
.wbs_dat_o (mem_wb_dat_o),
.wbs_stb_i (stb & !wb_tga_i),
.wbs_ack_o (mem_wb_ack_o),
.wbm_adr_o (wbm_adr_o),
.wbm_sel_o (wbm_sel_o),
.wbm_we_o (wbm_we_o),
.wbm_dat_o (wbm_dat_o),
.wbm_dat_i (wbm_dat_i),
.wbm_stb_o (wbm_stb_o),
.wbm_ack_i (wbm_ack_i),
.chain_four (chain_four),
.memory_mapping1 (memory_mapping1),
.write_mode (write_mode),
.raster_op (raster_op),
.read_mode (read_mode),
.bitmask (bitmask),
.set_reset (set_reset),
.enable_set_reset (enable_set_reset),
.map_mask (map_mask),
.read_map_select (read_map_select),
.color_compare (color_compare),
.color_dont_care (color_dont_care)
);
vga_mem_arbitrer mem_arbitrer (
.clk_i (wb_clk_i),
.rst_i (wb_rst_i),
.wb_adr_i (wbm_adr_o),
.wb_sel_i (wbm_sel_o),
.wb_we_i (wbm_we_o),
.wb_dat_i (wbm_dat_o),
.wb_dat_o (wbm_dat_i),
.wb_stb_i (wbm_stb_o),
.wb_ack_o (wbm_ack_i),
.csr_adr_i (csr_adr_i),
.csr_dat_o (csr_dat_i),
.csr_stb_i (csr_stb_i),
.csrm_adr_o (csrm_adr_o),
.csrm_sel_o (csrm_sel_o),
.csrm_we_o (csrm_we_o),
.csrm_dat_o (csrm_dat_o),
.csrm_dat_i (csrm_dat_i)
);
// Continous assignments
assign wb_dat_o = wb_tga_i ? conf_wb_dat_o : mem_wb_dat_o;
assign wb_ack_o = wb_tga_i ? conf_wb_ack_o : mem_wb_ack_o;
assign stb = wb_stb_i & wb_cyc_i;
assign vert_sync = ~graphics_alpha ^ w_vert_sync;
// Behaviour
// csr_adr_i
always @(posedge wb_clk_i)
csr_adr_i <= wb_rst_i ? 17'h0 : csr_adr_o + start_addr[15:1];
// csr_stb_i
always @(posedge wb_clk_i)
csr_stb_i <= wb_rst_i ? 1'b0 : csr_stb_o;
endmodule
|
//Legal Notice: (C)2013 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
module debounce (
clk,
reset_n,
data_in,
data_out
);
parameter WIDTH = 32; // set to be the width of the bus being debounced
parameter POLARITY = "HIGH"; // set to be "HIGH" for active high debounce or "LOW" for active low debounce
parameter TIMEOUT = 50000; // number of input clock cycles the input signal needs to be in the active state
parameter TIMEOUT_WIDTH = 16; // set to be ceil(log2(TIMEOUT))
input wire clk;
input wire reset_n;
input wire [WIDTH-1:0] data_in;
output wire [WIDTH-1:0] data_out;
reg [TIMEOUT_WIDTH-1:0] counter [0:WIDTH-1];
wire counter_reset [0:WIDTH-1];
wire counter_enable [0:WIDTH-1];
// need one counter per input to debounce
genvar i;
generate for (i = 0; i < WIDTH; i = i+1)
begin: debounce_counter_loop
always @ (posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
counter[i] <= 0;
end
else
begin
if (counter_reset[i] == 1) // resetting the counter needs to win
begin
counter[i] <= 0;
end
else if (counter_enable[i] == 1)
begin
counter[i] <= counter[i] + 1'b1;
end
end
end
if (POLARITY == "HIGH")
begin
assign counter_reset[i] = (data_in[i] == 0);
assign counter_enable[i] = (data_in[i] == 1) & (counter[i] < TIMEOUT);
assign data_out[i] = (counter[i] == TIMEOUT) ? 1'b1 : 1'b0;
end
else
begin
assign counter_reset[i] = (data_in[i] == 1);
assign counter_enable[i] = (data_in[i] == 0) & (counter[i] < TIMEOUT);
assign data_out[i] = (counter[i] == TIMEOUT) ? 1'b0 : 1'b1;
end
end
endgenerate
endmodule
|
/*
Legal Notice: (C)2009 Altera Corporation. All rights reserved. Your
use of Altera Corporation's design tools, logic functions and other
software and tools, and its AMPP partner logic functions, and any
output files any of the foregoing (including device programming or
simulation files), and any associated documentation or information are
expressly subject to the terms and conditions of the Altera Program
License Subscription Agreement or other applicable license agreement,
including, without limitation, that your use is for the sole purpose
of programming logic devices manufactured by Altera and sold by Altera
or its authorized distributors. Please refer to the applicable
agreement for further details.
*/
/*
Author: JCJB
Date: 07/01/2009
This optional block is used for two purposes:
1) Relay response information back to the host typically in ST->MM mode.
This information is 'actual bytes transferred', 'error', and 'early termination'.
2) Relay response and interrupt information back to a prefetching master block
that will write the contents back to memory. Interrupt information is also passed
since the interrupt needs to occur when the prefetching master block overwrites
the descriptor in main memory and not when the event occurs. The host needs to read
the interrupt condition out of memory so it could potentially get out of sync if
the interrupt information wasn't buffered and delayed.
This block has three response port options: MM slave, ST source, and disabled.
When you don't need access to response information (MM->MM or MM->ST) or interrupts in
the case of a prefetching descriptor master then you can safely disable the port.
By disabling the port you will not consume any logic resources or on-chip memory blocks.
When the source port is enabled bit 52 of the data stream represents the "descriptor full"
condition. The descriptor prefetching master can use this signal to perform pipelined reads
without having to worry about flow control (since there is room for an entire descriptor to be
written). This is benefical as apposed to performing descriptor reads, buffering the data, then
writting it out to the descriptor buffer block.
Version 1.0
1.0 - If you attempt to use the wrong response port type you will be issued a warning
but allowed to generate. This is because in some cases you may not need the typical
behavior. For example if you perform MM->MM transfers with some streaming IP between
the read and write masters you still might need access to error bits. Likewise
if you don't enable the streaming sink port while using a descriptor pre-fetching block
you may not care if you get interrupted early and want to use the CSR block for interrupts
instead.
*/
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module response_block (
clk,
reset,
mm_response_readdata,
mm_response_read,
mm_response_address,
mm_response_byteenable,
mm_response_waitrequest,
src_response_data,
src_response_valid,
src_response_ready,
sw_reset,
response_watermark,
response_fifo_full,
response_fifo_empty,
done_strobe,
actual_bytes_transferred,
error,
early_termination,
transfer_complete_IRQ_mask,
error_IRQ_mask,
early_termination_IRQ_mask,
descriptor_buffer_full
);
parameter RESPONSE_PORT = 0; // when disabled all the outputs will be disconnected by the component wrapper
parameter FIFO_DEPTH = 256; // needs to be double the descriptor FIFO depth
parameter FIFO_DEPTH_LOG2 = 8;
localparam FIFO_WIDTH = (RESPONSE_PORT == 0)? 41 : 51; // when 'RESPONSE_PORT' is 1 then the response port is set to streaming and must pass the interrupt masks as well
input clk;
input reset;
output wire [31:0] mm_response_readdata;
input mm_response_read;
input mm_response_address; // only have 2 addresses
input [3:0] mm_response_byteenable;
output wire mm_response_waitrequest;
output wire [255:0] src_response_data; // not going to use all these bits, the remainder will be grounded
output wire src_response_valid;
input src_response_ready;
input sw_reset;
output wire [15:0] response_watermark;
output wire response_fifo_full;
output wire response_fifo_empty;
input done_strobe;
input [31:0] actual_bytes_transferred;
input [7:0] error;
input early_termination;
// all of these signals are only used the ST source response port since the pre-fetching master component will handle the interrupt generation as apposed to the CSR block
input transfer_complete_IRQ_mask;
input [7:0] error_IRQ_mask;
input early_termination_IRQ_mask;
input descriptor_buffer_full; // handy signal for the prefetching master to use so that it known when to blast a new descriptor into the dispatcher
/* internal signals and registers */
wire [FIFO_DEPTH_LOG2-1:0] fifo_used;
wire fifo_full;
wire fifo_empty;
wire fifo_read;
wire [FIFO_WIDTH-1:0] fifo_input;
wire [FIFO_WIDTH-1:0] fifo_output;
generate
if (RESPONSE_PORT == 0) // slave port used for response data
begin
assign fifo_input = {early_termination, error, actual_bytes_transferred};
assign fifo_read = (mm_response_read == 1) & (fifo_empty == 0) & (mm_response_address == 1) & (mm_response_byteenable[3] == 1); // reading from the upper byte (byte offset 7) pops the fifo
scfifo the_response_FIFO (
.clock (clk),
.aclr (reset),
.sclr (sw_reset),
.data (fifo_input),
.wrreq (done_strobe),
.rdreq (fifo_read),
.q (fifo_output),
.full (fifo_full),
.empty (fifo_empty),
.usedw (fifo_used)
);
defparam the_response_FIFO.lpm_width = FIFO_WIDTH;
defparam the_response_FIFO.lpm_numwords = FIFO_DEPTH;
defparam the_response_FIFO.lpm_widthu = FIFO_DEPTH_LOG2;
defparam the_response_FIFO.lpm_showahead = "ON";
defparam the_response_FIFO.use_eab = "ON";
defparam the_response_FIFO.overflow_checking = "OFF";
defparam the_response_FIFO.underflow_checking = "OFF";
defparam the_response_FIFO.add_ram_output_register = "ON";
defparam the_response_FIFO.lpm_type = "scfifo";
// either actual bytes transfered when address == 0 or {zero padding, early_termination, error[7:0]} when address = 1
assign mm_response_readdata = (mm_response_address == 0)? fifo_output[31:0] : {{23{1'b0}}, fifo_output[40:32]};
assign mm_response_waitrequest = fifo_empty;
assign response_watermark = {{(16-(FIFO_DEPTH_LOG2+1)){1'b0}}, fifo_full, fifo_used}; // zero padding plus the 'true used' FIFO amount
assign response_fifo_full = fifo_full;
assign response_fifo_empty = fifo_empty;
// no streaming port so ground all of its outputs
assign src_response_data = 0;
assign src_response_valid = 0;
end
else if (RESPONSE_PORT == 1) // streaming source port used for response data (prefetcher will catch this data)
begin
assign fifo_input = {early_termination_IRQ_mask, error_IRQ_mask, transfer_complete_IRQ_mask, early_termination, error, actual_bytes_transferred};
assign fifo_read = (fifo_empty == 0) & (src_response_ready == 1);
scfifo the_response_FIFO (
.clock (clk),
.aclr (reset | sw_reset),
.data (fifo_input),
.wrreq (done_strobe),
.rdreq (fifo_read),
.q (fifo_output),
.full (fifo_full),
.empty (fifo_empty),
.usedw (fifo_used)
);
defparam the_response_FIFO.lpm_width = FIFO_WIDTH;
defparam the_response_FIFO.lpm_numwords = FIFO_DEPTH;
defparam the_response_FIFO.lpm_widthu = FIFO_DEPTH_LOG2;
defparam the_response_FIFO.lpm_showahead = "ON";
defparam the_response_FIFO.use_eab = "ON";
defparam the_response_FIFO.overflow_checking = "OFF";
defparam the_response_FIFO.underflow_checking = "OFF";
defparam the_response_FIFO.add_ram_output_register = "ON";
defparam the_response_FIFO.lpm_type = "scfifo";
assign src_response_data = {{204{1'b0}}, descriptor_buffer_full, fifo_output}; // zero padding the upper bits, also sending out the descriptor buffer full signal to simplify the throttling in the prefetching master (bit 52)
assign src_response_valid = (fifo_empty == 0);
assign response_watermark = {{(16-(FIFO_DEPTH_LOG2+1)){1'b0}}, fifo_full, fifo_used}; // zero padding plus the 'true used' FIFO amount;
assign response_fifo_full = fifo_full;
assign response_fifo_empty = fifo_empty;
// no slave port so ground all of its outputs
assign mm_response_readdata = 0;
assign mm_response_waitrequest = 0;
end
else // no response port so grounding all outputs
begin
assign fifo_input = 0;
assign fifo_output = 0;
assign mm_response_readdata = 0;
assign mm_response_waitrequest = 0;
assign src_response_data = 0;
assign src_response_valid = 0;
assign response_watermark = 0;
assign response_fifo_full = 0;
assign response_fifo_empty = 0;
end
endgenerate
endmodule
|
// (C) 2001-2012 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
`timescale 1ps/1ps
module altera_pll_reconfig_core
#(
parameter reconf_width = 64,
parameter device_family = "Stratix V",
// MIF Streaming parameters
parameter RECONFIG_ADDR_WIDTH = 6,
parameter RECONFIG_DATA_WIDTH = 32,
parameter ROM_ADDR_WIDTH = 9,
parameter ROM_DATA_WIDTH = 32,
parameter ROM_NUM_WORDS = 512
) (
//input
input wire mgmt_clk,
input wire mgmt_reset,
//conduits
output wire [reconf_width-1:0] reconfig_to_pll,
input wire [reconf_width-1:0] reconfig_from_pll,
// user data (avalon-MM slave interface)
output wire [31:0] mgmt_readdata,
output wire mgmt_waitrequest,
input wire [5:0] mgmt_address,
input wire mgmt_read,
input wire mgmt_write,
input wire [31:0] mgmt_writedata,
//other
output wire mif_start_out,
output reg [ROM_ADDR_WIDTH-1:0] mif_base_addr
);
localparam mode_WR = 1'b0;
localparam mode_POLL = 1'b1;
localparam MODE_REG = 6'b000000;
localparam STATUS_REG = 6'b000001;
localparam START_REG = 6'b000010;
localparam N_REG = 6'b000011;
localparam M_REG = 6'b000100;
localparam C_COUNTERS_REG = 6'b000101;
localparam DPS_REG = 6'b000110;
localparam DSM_REG = 6'b000111;
localparam BWCTRL_REG = 6'b001000;
localparam CP_CURRENT_REG = 6'b001001;
localparam ANY_DPRIO = 6'b100000;
localparam CNT_BASE = 5'b001010;
localparam MIF_REG = 6'b011111;
//C Counters
localparam number_of_counters = 5'd18;
localparam CNT_0 = 1'd0, CNT_1 = 5'd1, CNT_2 = 5'd2,
CNT_3 = 5'd3, CNT_4 = 5'd4, CNT_5 = 5'd5,
CNT_6 = 5'd6, CNT_7 = 5'd7, CNT_8 = 5'd8,
CNT_9 = 5'd9, CNT_10 = 5'd10, CNT_11 = 5'd11,
CNT_12 = 5'd12, CNT_13 = 5'd13, CNT_14 = 5'd14,
CNT_15 = 5'd15, CNT_16 = 5'd16, CNT_17 = 5'd17;
//C counter addresses
localparam C_CNT_0_DIV_ADDR = 5'h00;
localparam C_CNT_0_DIV_ADDR_DPRIO_1 = 5'h11;
localparam C_CNT_0_3_BYPASS_EN_ADDR = 5'h15;
localparam C_CNT_0_3_ODD_DIV_EN_ADDR = 5'h17;
localparam C_CNT_4_17_BYPASS_EN_ADDR = 5'h14;
localparam C_CNT_4_17_ODD_DIV_EN_ADDR = 5'h16;
//N counter addresses
localparam N_CNT_DIV_ADDR = 5'h13;
localparam N_CNT_BYPASS_EN_ADDR = 5'h15;
localparam N_CNT_ODD_DIV_EN_ADDR = 5'h17;
//M counter addresses
localparam M_CNT_DIV_ADDR = 5'h12;
localparam M_CNT_BYPASS_EN_ADDR = 5'h15;
localparam M_CNT_ODD_DIV_EN_ADDR = 5'h17;
//DSM address
localparam DSM_K_FRACTIONAL_DIVISION_ADDR_0 = 5'h18;
localparam DSM_K_FRACTIONAL_DIVISION_ADDR_1 = 5'h19;
localparam DSM_K_READY_ADDR = 5'h17;
localparam DSM_K_DITHER_ADDR = 5'h17;
localparam DSM_OUT_SEL_ADDR = 6'h30;
//Other DSM params
localparam DSM_K_READY_BIT_INDEX = 4'd11;
//BWCTRL address
//Bit 0-3 of addr
localparam BWCTRL_ADDR = 6'h30;
//CP_CURRENT address
//Bit 0-2 of addr
localparam CP_CURRENT_ADDR = 6'h31;
localparam DPRIO_IDLE = 3'd0, ONE = 3'd1, TWO = 3'd2, THREE = 3'd3, FOUR = 3'd4,
FIVE = 3'd5, SIX = 3'd6, SEVEN = 3'd7, EIGHT = 4'd8, NINE = 4'd9, TEN = 4'd10,
ELEVEN = 4'd11, TWELVE = 4'd12, THIRTEEN = 4'd13, FOURTEEN = 4'd14, DPRIO_DONE = 4'd15;
localparam IDLE = 2'b00, WAIT_ON_LOCK = 2'b01, LOCKED = 2'b10;
wire clk;
wire reset;
wire gnd;
wire [5: 0] slave_address;
wire slave_read;
wire slave_write;
wire [31: 0] slave_writedata;
reg [31: 0] slave_readdata_d;
reg [31: 0] slave_readdata_q;
wire slave_waitrequest;
assign clk = mgmt_clk;
assign slave_address = mgmt_address;
assign slave_read = mgmt_read;
assign slave_write = mgmt_write;
assign slave_writedata = mgmt_writedata;
// Outputs
assign mgmt_readdata = slave_readdata_q;
assign mgmt_waitrequest = slave_waitrequest;
//internal signals
wire locked;
wire pll_start;
wire pll_start_valid;
reg status_read;
wire read_slave_mode_asserted;
wire pll_start_asserted;
reg [1:0] current_state;
reg [1:0] next_state;
reg slave_mode;
reg status;//0=busy, 1=ready
//user_mode_init user_mode_init_inst (clk, reset, dprio_mdio_dis, ser_shift_load);
//declaring the init wires. These will have 0 on them for 64 clk cycles
wire [ 5:0] init_dprio_address;
wire init_dprio_read;
wire [ 1:0] init_dprio_byteen;
wire init_dprio_write;
wire [15:0] init_dprio_writedata;
wire init_atpgmode;
wire init_mdio_dis;
wire init_scanen;
wire init_ser_shift_load;
wire dprio_init_done;
//DPRIO output signals after initialization is done
wire dprio_clk;
reg avmm_dprio_write;
reg avmm_dprio_read;
reg [5:0] avmm_dprio_address;
reg [15:0] avmm_dprio_writedata;
reg [1:0] avmm_dprio_byteen;
wire avmm_atpgmode;
wire avmm_mdio_dis;
wire avmm_scanen;
//Final output wires that are muxed between the init and avmm wires.
wire dprio_init_reset;
wire [5:0] dprio_address /*synthesis keep*/;
wire dprio_read/*synthesis keep*/;
wire [1:0] dprio_byteen/*synthesis keep*/;
wire dprio_write/*synthesis keep*/;
wire [15:0] dprio_writedata/*synthesis keep*/;
wire dprio_mdio_dis/*synthesis keep*/;
wire dprio_ser_shift_load/*synthesis keep*/;
wire dprio_atpgmode/*synthesis keep*/;
wire dprio_scanen/*synthesis keep*/;
//other PLL signals for dyn ph shift
wire phase_done/*synthesis keep*/;
wire phase_en/*synthesis keep*/;
wire up_dn/*synthesis keep*/;
wire [4:0] cnt_sel;
//DPRIO input signals
wire [15:0] dprio_readdata;
//internal logic signals
//storage registers for user sent data
reg dprio_temp_read_1;
reg dprio_temp_read_2;
reg dprio_start;
reg mif_start_assert;
reg dps_start_assert;
wire usr_valid_changes;
reg [3:0] dprio_cur_state;
reg [3:0] dprio_next_state;
reg [15:0] dprio_temp_m_n_c_readdata_1_d;
reg [15:0] dprio_temp_m_n_c_readdata_2_d;
reg [15:0] dprio_temp_m_n_c_readdata_1_q;
reg [15:0] dprio_temp_m_n_c_readdata_2_q;
reg dprio_write_done;
//C counters signals
reg [7:0] usr_c_cnt_lo;
reg [7:0] usr_c_cnt_hi;
reg usr_c_cnt_bypass_en;
reg usr_c_cnt_odd_duty_div_en;
reg [7:0] temp_c_cnt_lo [0:17];
reg [7:0] temp_c_cnt_hi [0:17];
reg temp_c_cnt_bypass_en [0:17];
reg temp_c_cnt_odd_duty_div_en [0:17];
reg any_c_cnt_changed;
reg all_c_cnt_done_q;
reg all_c_cnt_done_d;
reg [17:0] c_cnt_changed;
reg [17:0] c_cnt_done_d;
reg [17:0] c_cnt_done_q;
//N counter signals
reg [7:0] usr_n_cnt_lo;
reg [7:0] usr_n_cnt_hi;
reg usr_n_cnt_bypass_en;
reg usr_n_cnt_odd_duty_div_en;
reg n_cnt_changed;
reg n_cnt_done_d;
reg n_cnt_done_q;
//M counter signals
reg [7:0] usr_m_cnt_lo;
reg [7:0] usr_m_cnt_hi;
reg usr_m_cnt_bypass_en;
reg usr_m_cnt_odd_duty_div_en;
reg m_cnt_changed;
reg m_cnt_done_d;
reg m_cnt_done_q;
//dyn phase regs
reg [15:0] usr_num_shifts;
reg [4:0] usr_cnt_sel /*synthesis preserve*/;
reg usr_up_dn;
reg dps_changed;
wire dps_changed_valid;
wire dps_done;
//DSM Signals
reg [31:0] usr_k_value;
reg dsm_k_changed;
reg dsm_k_done_d;
reg dsm_k_done_q;
reg dsm_k_ready_false_done_d;
//BW signals
reg [3:0] usr_bwctrl_value;
reg bwctrl_changed;
reg bwctrl_done_d;
reg bwctrl_done_q;
//CP signals
reg [2:0] usr_cp_current_value;
reg cp_current_changed;
reg cp_current_done_d;
reg cp_current_done_q;
//Manual DPRIO signals
reg manual_dprio_done_q;
reg manual_dprio_done_d;
reg manual_dprio_changed;
reg [5:0] usr_dprio_address;
reg [15:0] usr_dprio_writedata_0;
reg usr_r_w;
//keeping track of which operation happened last
reg [5:0] operation_address;
// Address wires for all C_counter DPRIO registers
// These are outputs of LUTS, changing depending
// on whether PLL_0 or PLL_1 being used
//Fitter will tell if FPLL1 is being used
wire fpll_1;
// other
reg mif_reg_asserted;
// MAIN FSM
always @(posedge clk)
begin
if (reset)
begin
dprio_cur_state <= DPRIO_IDLE;
current_state <= IDLE;
end
else
begin
current_state <= next_state;
dprio_cur_state <= dprio_next_state;
end
end
always @(*)
begin
case(current_state)
IDLE:
begin
if (pll_start & !slave_waitrequest & usr_valid_changes)
next_state = WAIT_ON_LOCK;
else
next_state = IDLE;
end
WAIT_ON_LOCK:
begin
if (locked & dps_done & dprio_write_done) // received locked high from PLL
begin
if (slave_mode==mode_WR) //if the mode is waitrequest, then
// goto IDLE state directly
next_state = IDLE;
else
next_state = LOCKED; //otherwise go the locked state
end
else
next_state = WAIT_ON_LOCK;
end
LOCKED:
begin
if (status_read) // stay in LOCKED until user reads status
next_state = IDLE;
else
next_state = LOCKED;
end
default: next_state = 2'bxx;
endcase
end
// ask the pll to start reconfig
assign pll_start = (pll_start_asserted & (current_state==IDLE)) ;
assign pll_start_valid = (pll_start & (next_state==WAIT_ON_LOCK)) ;
// WRITE OPERATIONS
assign pll_start_asserted = slave_write & (slave_address == START_REG);
assign mif_start_out = pll_start & mif_reg_asserted;
//reading the mode register to determine what mode the slave will operate
//in.
always @(posedge clk)
begin
if (reset)
slave_mode <= mode_WR;
else if (slave_write & (slave_address == MODE_REG) & !slave_waitrequest)
slave_mode <= slave_writedata[0];
end
//record which values user wants to change.
//reading in the actual values that need to be reconfigged and sending
//them to the PLL
always @(posedge clk)
begin
if (reset)
begin
//reset all regs here
//BW signals reset
usr_bwctrl_value <= 0;
bwctrl_changed <= 0;
bwctrl_done_q <= 0;
//CP signals reset
usr_cp_current_value <= 0;
cp_current_changed <= 0;
cp_current_done_q <= 0;
//DSM signals reset
usr_k_value <= 0;
dsm_k_changed <= 0;
dsm_k_done_q <= 0;
//N counter signals reset
usr_n_cnt_lo <= 0;
usr_n_cnt_hi <= 0;
usr_n_cnt_bypass_en <= 0;
usr_n_cnt_odd_duty_div_en <= 0;
n_cnt_changed <= 0;
n_cnt_done_q <= 0;
//M counter signals reset
usr_m_cnt_lo <= 0;
usr_m_cnt_hi <= 0;
usr_m_cnt_bypass_en <= 0;
usr_m_cnt_odd_duty_div_en <= 0;
m_cnt_changed <= 0;
m_cnt_done_q <= 0;
//C counter signals reset
usr_c_cnt_lo <= 0;
usr_c_cnt_hi <= 0;
usr_c_cnt_bypass_en <= 0;
usr_c_cnt_odd_duty_div_en <= 0;
any_c_cnt_changed <= 0;
all_c_cnt_done_q <= 0;
c_cnt_done_q <= 0;
//generic signals
dprio_start <= 0;
mif_start_assert <= 0;
dps_start_assert <= 0;
dprio_temp_m_n_c_readdata_1_q <= 0;
dprio_temp_m_n_c_readdata_2_q <= 0;
c_cnt_done_q <= 0;
//DPS signals
usr_up_dn <= 0;
usr_cnt_sel <= 0;
usr_num_shifts <= 0;
dps_changed <= 0;
//manual DPRIO signals
manual_dprio_changed <= 0;
usr_dprio_address <= 0;
usr_dprio_writedata_0 <= 0;
usr_r_w <= 0;
operation_address <= 0;
mif_reg_asserted <= 0;
mif_base_addr <= 0;
end
else
begin
if (dprio_temp_read_1)
begin
dprio_temp_m_n_c_readdata_1_q <= dprio_temp_m_n_c_readdata_1_d;
end
if (dprio_temp_read_2)
begin
dprio_temp_m_n_c_readdata_2_q <= dprio_temp_m_n_c_readdata_2_d;
end
if ((dps_done)) dps_changed <= 0;
if (dsm_k_done_d) dsm_k_done_q <= dsm_k_done_d;
if (n_cnt_done_d) n_cnt_done_q <= n_cnt_done_d;
if (m_cnt_done_d) m_cnt_done_q <= m_cnt_done_d;
if (all_c_cnt_done_d) all_c_cnt_done_q <= all_c_cnt_done_d;
if (c_cnt_done_d != 0) c_cnt_done_q <= c_cnt_done_q | c_cnt_done_d;
if (bwctrl_done_d) bwctrl_done_q <= bwctrl_done_d;
if (cp_current_done_d) cp_current_done_q <= cp_current_done_d;
if (manual_dprio_done_d) manual_dprio_done_q <= manual_dprio_done_d;
if (mif_start_out == 1'b1)
mif_start_assert <= 0; // Signaled MIF block to start, so deassert on next cycle
if (dps_done != 1'b1)
dps_start_assert <= 0; // DPS has started, so dessert its start signal on next cycle
if (dprio_next_state == ONE)
dprio_start <= 0;
if (dprio_write_done)
begin
bwctrl_done_q <= 0;
cp_current_done_q <= 0;
dsm_k_done_q <= 0;
dsm_k_done_q <= 0;
n_cnt_done_q <= 0;
m_cnt_done_q <= 0;
all_c_cnt_done_q <= 0;
c_cnt_done_q <= 0;
dsm_k_changed <= 0;
n_cnt_changed <= 0;
m_cnt_changed <= 0;
any_c_cnt_changed <= 0;
bwctrl_changed <= 0;
cp_current_changed <= 0;
manual_dprio_changed <= 0;
manual_dprio_done_q <= 0;
if (dps_changed | dps_changed_valid | !dps_done )
begin
usr_cnt_sel <= usr_cnt_sel;
end
else
begin
usr_cnt_sel <= 0;
end
mif_reg_asserted <= 0;
end
else
begin
dsm_k_changed <= dsm_k_changed;
n_cnt_changed <= n_cnt_changed;
m_cnt_changed <= m_cnt_changed;
any_c_cnt_changed <= any_c_cnt_changed;
manual_dprio_changed <= manual_dprio_changed;
mif_reg_asserted <= mif_reg_asserted;
usr_cnt_sel <= usr_cnt_sel;
end
if(slave_write & !slave_waitrequest)
begin
case(slave_address)
//read in the values here from the user and act on them
DSM_REG:
begin
operation_address <= DSM_REG;
usr_k_value <= slave_writedata[31:0];
dsm_k_changed <= 1'b1;
dsm_k_done_q <= 0;
dprio_start <= 1'b1;
end
N_REG:
begin
operation_address <= N_REG;
usr_n_cnt_lo <= slave_writedata[7:0];
usr_n_cnt_hi <= slave_writedata[15:8];
usr_n_cnt_bypass_en <= slave_writedata[16];
usr_n_cnt_odd_duty_div_en <= slave_writedata[17];
n_cnt_changed <= 1'b1;
n_cnt_done_q <= 0;
dprio_start <= 1'b1;
end
M_REG:
begin
operation_address <= M_REG;
usr_m_cnt_lo <= slave_writedata[7:0];
usr_m_cnt_hi <= slave_writedata[15:8];
usr_m_cnt_bypass_en <= slave_writedata[16];
usr_m_cnt_odd_duty_div_en <= slave_writedata[17];
m_cnt_changed <= 1'b1;
m_cnt_done_q <= 0;
dprio_start <= 1'b1;
end
DPS_REG:
begin
operation_address <= DPS_REG;
usr_num_shifts <= slave_writedata[15:0];
usr_cnt_sel <= slave_writedata[20:16];
usr_up_dn <= slave_writedata[21];
dps_changed <= 1;
dps_start_assert <= 1;
end
C_COUNTERS_REG:
begin
operation_address <= C_COUNTERS_REG;
usr_c_cnt_lo <= slave_writedata[7:0];
usr_c_cnt_hi <= slave_writedata[15:8];
usr_c_cnt_bypass_en <= slave_writedata[16];
usr_c_cnt_odd_duty_div_en <= slave_writedata[17];
usr_cnt_sel <= slave_writedata[22:18];
any_c_cnt_changed <= 1'b1;
all_c_cnt_done_q <= 0;
dprio_start <= 1'b1;
end
BWCTRL_REG:
begin
usr_bwctrl_value <= slave_writedata[3:0];
bwctrl_changed <= 1'b1;
bwctrl_done_q <= 0;
dprio_start <= 1'b1;
operation_address <= BWCTRL_REG;
end
CP_CURRENT_REG:
begin
usr_cp_current_value <= slave_writedata[2:0];
cp_current_changed <= 1'b1;
cp_current_done_q <= 0;
dprio_start <= 1'b1;
operation_address <= CP_CURRENT_REG;
end
ANY_DPRIO:
begin
operation_address <= ANY_DPRIO;
manual_dprio_changed <= 1'b1;
usr_dprio_address <= slave_writedata[5:0];
usr_dprio_writedata_0 <= slave_writedata[21:6];
usr_r_w <= slave_writedata[22];
manual_dprio_done_q <= 0;
dprio_start <= 1'b1;
end
MIF_REG:
begin
mif_reg_asserted <= 1'b1;
mif_base_addr <= slave_writedata[ROM_ADDR_WIDTH-1:0];
mif_start_assert <= 1'b1;
end
endcase
end
end
end
//C Counter assigning values to the 2-d array of values for each C counter
reg [4:0] j;
always @(posedge clk)
begin
if (reset)
begin
c_cnt_changed[17:0] <= 0;
for (j = 0; j < number_of_counters; j = j + 1'b1)
begin : c_cnt_reset
temp_c_cnt_bypass_en[j] <= 0;
temp_c_cnt_odd_duty_div_en[j] <= 0;
temp_c_cnt_lo[j][7:0] <= 0;
temp_c_cnt_hi[j][7:0] <= 0;
end
end
else
begin
if (dprio_write_done)
begin
c_cnt_changed <= 0;
end
if (any_c_cnt_changed && (operation_address == C_COUNTERS_REG))
begin
case (cnt_sel)
CNT_0:
begin
temp_c_cnt_lo [0] <= usr_c_cnt_lo;
temp_c_cnt_hi [0] <= usr_c_cnt_hi;
temp_c_cnt_bypass_en [0] <= usr_c_cnt_bypass_en;
temp_c_cnt_odd_duty_div_en [0] <= usr_c_cnt_odd_duty_div_en;
c_cnt_changed [0] <= 1'b1;
end
CNT_1:
begin
temp_c_cnt_lo [1] <= usr_c_cnt_lo;
temp_c_cnt_hi [1] <= usr_c_cnt_hi;
temp_c_cnt_bypass_en [1] <= usr_c_cnt_bypass_en;
temp_c_cnt_odd_duty_div_en [1] <= usr_c_cnt_odd_duty_div_en;
c_cnt_changed [1] <= 1'b1;
end
CNT_2:
begin
temp_c_cnt_lo [2] <= usr_c_cnt_lo;
temp_c_cnt_hi [2] <= usr_c_cnt_hi;
temp_c_cnt_bypass_en [2] <= usr_c_cnt_bypass_en;
temp_c_cnt_odd_duty_div_en [2] <= usr_c_cnt_odd_duty_div_en;
c_cnt_changed [2] <= 1'b1;
end
CNT_3:
begin
temp_c_cnt_lo [3] <= usr_c_cnt_lo;
temp_c_cnt_hi [3] <= usr_c_cnt_hi;
temp_c_cnt_bypass_en [3] <= usr_c_cnt_bypass_en;
temp_c_cnt_odd_duty_div_en [3] <= usr_c_cnt_odd_duty_div_en;
c_cnt_changed [3] <= 1'b1;
end
CNT_4:
begin
temp_c_cnt_lo [4] <= usr_c_cnt_lo;
temp_c_cnt_hi [4] <= usr_c_cnt_hi;
temp_c_cnt_bypass_en [4] <= usr_c_cnt_bypass_en;
temp_c_cnt_odd_duty_div_en [4] <= usr_c_cnt_odd_duty_div_en;
c_cnt_changed [4] <= 1'b1;
end
CNT_5:
begin
temp_c_cnt_lo [5] <= usr_c_cnt_lo;
temp_c_cnt_hi [5] <= usr_c_cnt_hi;
temp_c_cnt_bypass_en [5] <= usr_c_cnt_bypass_en;
temp_c_cnt_odd_duty_div_en [5] <= usr_c_cnt_odd_duty_div_en;
c_cnt_changed [5] <= 1'b1;
end
CNT_6:
begin
temp_c_cnt_lo [6] <= usr_c_cnt_lo;
temp_c_cnt_hi [6] <= usr_c_cnt_hi;
temp_c_cnt_bypass_en [6] <= usr_c_cnt_bypass_en;
temp_c_cnt_odd_duty_div_en [6] <= usr_c_cnt_odd_duty_div_en;
c_cnt_changed [6] <= 1'b1;
end
CNT_7:
begin
temp_c_cnt_lo [7] <= usr_c_cnt_lo;
temp_c_cnt_hi [7] <= usr_c_cnt_hi;
temp_c_cnt_bypass_en [7] <= usr_c_cnt_bypass_en;
temp_c_cnt_odd_duty_div_en [7] <= usr_c_cnt_odd_duty_div_en;
c_cnt_changed [7] <= 1'b1;
end
CNT_8:
begin
temp_c_cnt_lo [8] <= usr_c_cnt_lo;
temp_c_cnt_hi [8] <= usr_c_cnt_hi;
temp_c_cnt_bypass_en [8] <= usr_c_cnt_bypass_en;
temp_c_cnt_odd_duty_div_en [8] <= usr_c_cnt_odd_duty_div_en;
c_cnt_changed [8] <= 1'b1;
end
CNT_9:
begin
temp_c_cnt_lo [9] <= usr_c_cnt_lo;
temp_c_cnt_hi [9] <= usr_c_cnt_hi;
temp_c_cnt_bypass_en [9] <= usr_c_cnt_bypass_en;
temp_c_cnt_odd_duty_div_en [9] <= usr_c_cnt_odd_duty_div_en;
c_cnt_changed [9] <= 1'b1;
end
CNT_10:
begin
temp_c_cnt_lo [10] <= usr_c_cnt_lo;
temp_c_cnt_hi [10] <= usr_c_cnt_hi;
temp_c_cnt_bypass_en [10] <= usr_c_cnt_bypass_en;
temp_c_cnt_odd_duty_div_en [10] <= usr_c_cnt_odd_duty_div_en;
c_cnt_changed [10] <= 1'b1;
end
CNT_11:
begin
temp_c_cnt_lo [11] <= usr_c_cnt_lo;
temp_c_cnt_hi [11] <= usr_c_cnt_hi;
temp_c_cnt_bypass_en [11] <= usr_c_cnt_bypass_en;
temp_c_cnt_odd_duty_div_en [11] <= usr_c_cnt_odd_duty_div_en;
c_cnt_changed [11] <= 1'b1;
end
CNT_12:
begin
temp_c_cnt_lo [12] <= usr_c_cnt_lo;
temp_c_cnt_hi [12] <= usr_c_cnt_hi;
temp_c_cnt_bypass_en [12] <= usr_c_cnt_bypass_en;
temp_c_cnt_odd_duty_div_en [12] <= usr_c_cnt_odd_duty_div_en;
c_cnt_changed [12] <= 1'b1;
end
CNT_13:
begin
temp_c_cnt_lo [13] <= usr_c_cnt_lo;
temp_c_cnt_hi [13] <= usr_c_cnt_hi;
temp_c_cnt_bypass_en [13] <= usr_c_cnt_bypass_en;
temp_c_cnt_odd_duty_div_en [13] <= usr_c_cnt_odd_duty_div_en;
c_cnt_changed [13] <= 1'b1;
end
CNT_14:
begin
temp_c_cnt_lo [14] <= usr_c_cnt_lo;
temp_c_cnt_hi [14] <= usr_c_cnt_hi;
temp_c_cnt_bypass_en [14] <= usr_c_cnt_bypass_en;
temp_c_cnt_odd_duty_div_en [14] <= usr_c_cnt_odd_duty_div_en;
c_cnt_changed [14] <= 1'b1;
end
CNT_15:
begin
temp_c_cnt_lo [15] <= usr_c_cnt_lo;
temp_c_cnt_hi [15] <= usr_c_cnt_hi;
temp_c_cnt_bypass_en [15] <= usr_c_cnt_bypass_en;
temp_c_cnt_odd_duty_div_en [15] <= usr_c_cnt_odd_duty_div_en;
c_cnt_changed [15] <= 1'b1;
end
CNT_16:
begin
temp_c_cnt_lo [16] <= usr_c_cnt_lo;
temp_c_cnt_hi [16] <= usr_c_cnt_hi;
temp_c_cnt_bypass_en [16] <= usr_c_cnt_bypass_en;
temp_c_cnt_odd_duty_div_en [16] <= usr_c_cnt_odd_duty_div_en;
c_cnt_changed [16] <= 1'b1;
end
CNT_17:
begin
temp_c_cnt_lo [17] <= usr_c_cnt_lo;
temp_c_cnt_hi [17] <= usr_c_cnt_hi;
temp_c_cnt_bypass_en [17] <= usr_c_cnt_bypass_en;
temp_c_cnt_odd_duty_div_en [17] <= usr_c_cnt_odd_duty_div_en;
c_cnt_changed [17] <= 1'b1;
end
endcase
end
end
end
//logic to handle which writes the user indicated and wants to start.
assign usr_valid_changes =dsm_k_changed| any_c_cnt_changed |n_cnt_changed | m_cnt_changed | dps_changed_valid |manual_dprio_changed |cp_current_changed|bwctrl_changed;
//start the reconfig operations by writing to the DPRIO
reg break_loop;
reg [4:0] i;
always @(*)
begin
dprio_temp_read_1 = 0;
dprio_temp_read_2 = 0;
dprio_temp_m_n_c_readdata_1_d = 0;
dprio_temp_m_n_c_readdata_2_d = 0;
break_loop = 0;
dprio_next_state = DPRIO_IDLE;
avmm_dprio_write = 0;
avmm_dprio_read = 0;
avmm_dprio_address = 0;
avmm_dprio_writedata = 0;
avmm_dprio_byteen = 0;
dprio_write_done = 1;
manual_dprio_done_d = 0;
n_cnt_done_d = 0;
dsm_k_done_d = 0;
dsm_k_ready_false_done_d = 0;
m_cnt_done_d = 0;
c_cnt_done_d[17:0] = 0;
all_c_cnt_done_d = 0;
bwctrl_done_d = 0;
cp_current_done_d = 0;
i = 0;
// Deassert dprio_write_done so it doesn't reset mif_reg_asserted (toggled writes)
if (dprio_start | mif_start_assert)
dprio_write_done = 0;
if (current_state == WAIT_ON_LOCK)
begin
case (dprio_cur_state)
ONE:
begin
if (n_cnt_changed & !n_cnt_done_q)
begin
dprio_write_done = 0;
avmm_dprio_write = 1'b1;
avmm_dprio_byteen = 2'b11;
dprio_next_state = TWO;
avmm_dprio_address = N_CNT_DIV_ADDR;
avmm_dprio_writedata[7:0] = usr_n_cnt_lo;
avmm_dprio_writedata[15:8] = usr_n_cnt_hi;
end
else if (m_cnt_changed & !m_cnt_done_q)
begin
dprio_write_done = 0;
avmm_dprio_write = 1'b1;
avmm_dprio_byteen = 2'b11;
dprio_next_state = TWO;
avmm_dprio_address = M_CNT_DIV_ADDR;
avmm_dprio_writedata[7:0] = usr_m_cnt_lo;
avmm_dprio_writedata[15:8] = usr_m_cnt_hi;
end
else if (any_c_cnt_changed & !all_c_cnt_done_q)
begin
for (i = 0; (i < number_of_counters) & !break_loop; i = i + 1'b1)
begin : c_cnt_write_hilo
if (c_cnt_changed[i] & !c_cnt_done_q[i])
begin
dprio_write_done = 0;
avmm_dprio_write = 1'b1;
avmm_dprio_byteen = 2'b11;
dprio_next_state = TWO;
if (fpll_1) avmm_dprio_address = C_CNT_0_DIV_ADDR + C_CNT_0_DIV_ADDR_DPRIO_1 - i;
else avmm_dprio_address = C_CNT_0_DIV_ADDR + i;
avmm_dprio_writedata[7:0] = temp_c_cnt_lo[i];
avmm_dprio_writedata[15:8] = temp_c_cnt_hi[i];
//To break from the loop, since only one counter
//is addressed at a time
break_loop = 1'b1;
end
end
end
else if (dsm_k_changed & !dsm_k_done_q)
begin
dprio_write_done = 0;
avmm_dprio_write = 0;
dprio_next_state = TWO;
end
else if (bwctrl_changed & !bwctrl_done_q)
begin
dprio_write_done = 0;
avmm_dprio_write = 0;
dprio_next_state = TWO;
end
else if (cp_current_changed & !cp_current_done_q)
begin
dprio_write_done = 0;
avmm_dprio_write = 0;
dprio_next_state = TWO;
end
else if (manual_dprio_changed & !manual_dprio_done_q)
begin
dprio_write_done = 0;
avmm_dprio_byteen = 2'b11;
dprio_next_state = TWO;
avmm_dprio_write = usr_r_w;
avmm_dprio_address = usr_dprio_address;
avmm_dprio_writedata[15:0] = usr_dprio_writedata_0;
end
else dprio_next_state = DPRIO_IDLE;
end
TWO:
begin
//handle reading the two setting bits on n_cnt, then
//writing them back while preserving other bits.
//Issue two consecutive reads then wait; readLatency=3
dprio_write_done = 0;
dprio_next_state = THREE;
avmm_dprio_byteen = 2'b11;
avmm_dprio_read = 1'b1;
if (n_cnt_changed & !n_cnt_done_q)
begin
avmm_dprio_address = N_CNT_BYPASS_EN_ADDR;
end
else if (m_cnt_changed & !m_cnt_done_q)
begin
avmm_dprio_address = M_CNT_BYPASS_EN_ADDR;
end
else if (any_c_cnt_changed & !all_c_cnt_done_q)
begin
for (i = 0; (i < number_of_counters) & !break_loop; i = i + 1'b1)
begin : c_cnt_read_bypass
if (fpll_1)
begin
if (i > 13)
begin
if (c_cnt_changed[i] & !c_cnt_done_q[i])
begin
avmm_dprio_address = C_CNT_0_3_BYPASS_EN_ADDR;
break_loop = 1'b1;
end
end
else
begin
if (c_cnt_changed[i] & !c_cnt_done_q[i])
begin
avmm_dprio_address = C_CNT_4_17_BYPASS_EN_ADDR;
break_loop = 1'b1;
end
end
end
else
begin
if (i < 4)
begin
if (c_cnt_changed[i] & !c_cnt_done_q[i])
begin
avmm_dprio_address = C_CNT_0_3_BYPASS_EN_ADDR;
break_loop = 1'b1;
end
end
else
begin
if (c_cnt_changed[i] & !c_cnt_done_q[i])
begin
avmm_dprio_address = C_CNT_4_17_BYPASS_EN_ADDR;
break_loop = 1'b1;
end
end
end
end
end
//reading the K ready 16 bit word. Need to write 0 to it
//afterwards to indicate that K has not been done writing
else if (dsm_k_changed & !dsm_k_done_q)
begin
avmm_dprio_address = DSM_K_READY_ADDR;
dprio_next_state = FOUR;
end
else if (bwctrl_changed & !bwctrl_done_q)
begin
avmm_dprio_address = BWCTRL_ADDR;
dprio_next_state = FOUR;
end
else if (cp_current_changed & !cp_current_done_q)
begin
avmm_dprio_address = CP_CURRENT_ADDR;
dprio_next_state = FOUR;
end
else if (manual_dprio_changed & !manual_dprio_done_q)
begin
avmm_dprio_read = ~usr_r_w;
avmm_dprio_address = usr_dprio_address;
dprio_next_state = DPRIO_DONE;
end
else dprio_next_state = DPRIO_IDLE;
end
THREE:
begin
dprio_write_done = 0;
avmm_dprio_byteen = 2'b11;
avmm_dprio_read = 1'b1;
dprio_next_state = FOUR;
if (n_cnt_changed & !n_cnt_done_q)
begin
avmm_dprio_address = N_CNT_ODD_DIV_EN_ADDR;
end
else if (m_cnt_changed & !m_cnt_done_q)
begin
avmm_dprio_address = M_CNT_ODD_DIV_EN_ADDR;
end
else if (any_c_cnt_changed & !all_c_cnt_done_q)
begin
for (i = 0; (i < number_of_counters) & !break_loop; i = i + 1'b1)
begin : c_cnt_read_odd_div
if (fpll_1)
begin
if (i > 13)
begin
if (c_cnt_changed[i] & !c_cnt_done_q[i])
begin
avmm_dprio_address = C_CNT_0_3_ODD_DIV_EN_ADDR;
break_loop = 1'b1;
end
end
else
begin
if (c_cnt_changed[i] & !c_cnt_done_q[i])
begin
avmm_dprio_address = C_CNT_4_17_ODD_DIV_EN_ADDR;
break_loop = 1'b1;
end
end
end
else
begin
if (i < 4)
begin
if (c_cnt_changed[i] & !c_cnt_done_q[i])
begin
avmm_dprio_address = C_CNT_0_3_ODD_DIV_EN_ADDR;
break_loop = 1'b1;
end
end
else
begin
if (c_cnt_changed[i] & !c_cnt_done_q[i])
begin
avmm_dprio_address = C_CNT_4_17_ODD_DIV_EN_ADDR;
break_loop = 1'b1;
end
end
end
end
end
else dprio_next_state = DPRIO_IDLE;
end
FOUR:
begin
dprio_temp_read_1 = 1'b1;
dprio_write_done = 0;
if (cp_current_changed|bwctrl_changed|dsm_k_changed|n_cnt_changed|m_cnt_changed|any_c_cnt_changed)
begin
dprio_temp_m_n_c_readdata_1_d = dprio_readdata;
dprio_next_state = FIVE;
end
else dprio_next_state = DPRIO_IDLE;
end
FIVE:
begin
dprio_write_done = 0;
dprio_temp_read_2 = 1'b1;
if (cp_current_changed|bwctrl_changed|dsm_k_changed|n_cnt_changed|m_cnt_changed|any_c_cnt_changed)
begin
//this is where DSM ready value comes.
//Need to store in a register to be used later
dprio_temp_m_n_c_readdata_2_d = dprio_readdata;
dprio_next_state = SIX;
end
else dprio_next_state = DPRIO_IDLE;
end
SIX:
begin
dprio_write_done = 0;
avmm_dprio_write = 1'b1;
avmm_dprio_byteen = 2'b11;
dprio_next_state = SEVEN;
avmm_dprio_writedata = dprio_temp_m_n_c_readdata_1_q;
if (n_cnt_changed & !n_cnt_done_q)
begin
avmm_dprio_address = N_CNT_BYPASS_EN_ADDR;
avmm_dprio_writedata[5] = usr_n_cnt_bypass_en;
end
else if (m_cnt_changed & !m_cnt_done_q)
begin
avmm_dprio_address = M_CNT_BYPASS_EN_ADDR;
avmm_dprio_writedata[4] = usr_m_cnt_bypass_en;
end
else if (any_c_cnt_changed & !all_c_cnt_done_q)
begin
for (i = 0; (i < number_of_counters) & !break_loop; i = i + 1'b1)
begin : c_cnt_write_bypass
if (fpll_1)
begin
if (i > 13)
begin
if (c_cnt_changed[i] & !c_cnt_done_q[i])
begin
avmm_dprio_address = C_CNT_0_3_BYPASS_EN_ADDR;
avmm_dprio_writedata[i-14] = temp_c_cnt_bypass_en[i];
break_loop = 1'b1;
end
end
else
begin
if (c_cnt_changed[i] & !c_cnt_done_q[i])
begin
avmm_dprio_address = C_CNT_4_17_BYPASS_EN_ADDR;
avmm_dprio_writedata[i] = temp_c_cnt_bypass_en[i];
break_loop = 1'b1;
end
end
end
else
begin
if (i < 4)
begin
if (c_cnt_changed[i] & !c_cnt_done_q[i])
begin
avmm_dprio_address = C_CNT_0_3_BYPASS_EN_ADDR;
avmm_dprio_writedata[3-i] = temp_c_cnt_bypass_en[i];
break_loop = 1'b1;
end
end
else
begin
if (c_cnt_changed[i] & !c_cnt_done_q[i])
begin
avmm_dprio_address = C_CNT_4_17_BYPASS_EN_ADDR;
avmm_dprio_writedata[17-i] = temp_c_cnt_bypass_en[i];
break_loop = 1'b1;
end
end
end
end
end
else if (dsm_k_changed & !dsm_k_done_q)
begin
avmm_dprio_write = 0;
end
else if (bwctrl_changed & !bwctrl_done_q)
begin
avmm_dprio_write = 0;
end
else if (cp_current_changed & !cp_current_done_q)
begin
avmm_dprio_write = 0;
end
else dprio_next_state = DPRIO_IDLE;
end
SEVEN:
begin
dprio_write_done = 0;
dprio_next_state = EIGHT;
avmm_dprio_write = 1'b1;
avmm_dprio_byteen = 2'b11;
avmm_dprio_writedata = dprio_temp_m_n_c_readdata_2_q;
if (n_cnt_changed & !n_cnt_done_q)
begin
avmm_dprio_address = N_CNT_ODD_DIV_EN_ADDR;
avmm_dprio_writedata[5] = usr_n_cnt_odd_duty_div_en;
n_cnt_done_d = 1'b1;
end
else if (m_cnt_changed & !m_cnt_done_q)
begin
avmm_dprio_address = M_CNT_ODD_DIV_EN_ADDR;
avmm_dprio_writedata[4] = usr_m_cnt_odd_duty_div_en;
m_cnt_done_d = 1'b1;
end
else if (any_c_cnt_changed & !all_c_cnt_done_q)
begin
for (i = 0; (i < number_of_counters) & !break_loop; i = i + 1'b1)
begin : c_cnt_write_odd_div
if (fpll_1)
begin
if (i > 13)
begin
if (c_cnt_changed[i] & !c_cnt_done_q[i])
begin
avmm_dprio_address = C_CNT_0_3_ODD_DIV_EN_ADDR;
avmm_dprio_writedata[i-14] = temp_c_cnt_odd_duty_div_en[i];
c_cnt_done_d[i] = 1'b1;
//have to OR the signals to prevent
//overwriting of previous dones
c_cnt_done_d = c_cnt_done_d | c_cnt_done_q;
break_loop = 1'b1;
end
end
else
begin
if (c_cnt_changed[i] & !c_cnt_done_q[i])
begin
avmm_dprio_address = C_CNT_4_17_ODD_DIV_EN_ADDR;
avmm_dprio_writedata[i] = temp_c_cnt_odd_duty_div_en[i];
c_cnt_done_d[i] = 1'b1;
c_cnt_done_d = c_cnt_done_d | c_cnt_done_q;
break_loop = 1'b1;
end
end
end
else
begin
if (i < 4)
begin
if (c_cnt_changed[i] & !c_cnt_done_q[i])
begin
avmm_dprio_address = C_CNT_0_3_ODD_DIV_EN_ADDR;
avmm_dprio_writedata[3-i] = temp_c_cnt_odd_duty_div_en[i];
c_cnt_done_d[i] = 1'b1;
//have to OR the signals to prevent
//overwriting of previous dones
c_cnt_done_d = c_cnt_done_d | c_cnt_done_q;
break_loop = 1'b1;
end
end
else
begin
if (c_cnt_changed[i] & !c_cnt_done_q[i])
begin
avmm_dprio_address = C_CNT_4_17_ODD_DIV_EN_ADDR;
avmm_dprio_writedata[17-i] = temp_c_cnt_odd_duty_div_en[i];
c_cnt_done_d[i] = 1'b1;
c_cnt_done_d = c_cnt_done_d | c_cnt_done_q;
break_loop = 1'b1;
end
end
end
end
end
else if (dsm_k_changed & !dsm_k_done_q)
begin
avmm_dprio_address = DSM_K_READY_ADDR;
avmm_dprio_writedata[DSM_K_READY_BIT_INDEX] = 1'b0;
dsm_k_ready_false_done_d = 1'b1;
end
else if (bwctrl_changed & !bwctrl_done_q)
begin
avmm_dprio_address = BWCTRL_ADDR;
avmm_dprio_writedata[3:0] = usr_bwctrl_value;
bwctrl_done_d = 1'b1;
end
else if (cp_current_changed & !cp_current_done_q)
begin
avmm_dprio_address = CP_CURRENT_ADDR;
avmm_dprio_writedata[2:0] = usr_cp_current_value;
cp_current_done_d = 1'b1;
end
//if all C_cnt that were changed are done, then assert all_c_cnt_done
if (c_cnt_done_d == c_cnt_changed)
all_c_cnt_done_d = 1'b1;
if (n_cnt_changed & n_cnt_done_d)
dprio_next_state = DPRIO_DONE;
if (any_c_cnt_changed & !all_c_cnt_done_d & !all_c_cnt_done_q)
dprio_next_state = ONE;
else if (m_cnt_changed & !m_cnt_done_d & !m_cnt_done_q)
dprio_next_state = ONE;
else if (dsm_k_changed & !dsm_k_ready_false_done_d)
dprio_next_state = TWO;
else if (dsm_k_changed & !dsm_k_done_q)
dprio_next_state = EIGHT;
else if (bwctrl_changed & !bwctrl_done_d)
dprio_next_state = TWO;
else if (cp_current_changed & !cp_current_done_d)
dprio_next_state = TWO;
else
begin
dprio_next_state = DPRIO_DONE;
dprio_write_done = 1'b1;
end
end
//finish the rest of the DSM reads/writes
//writing k value, writing k_ready to 1.
EIGHT:
begin
dprio_write_done = 0;
dprio_next_state = NINE;
avmm_dprio_write = 1'b1;
avmm_dprio_byteen = 2'b11;
if (dsm_k_changed & !dsm_k_done_q)
begin
avmm_dprio_address = DSM_K_FRACTIONAL_DIVISION_ADDR_0;
avmm_dprio_writedata[15:0] = usr_k_value[15:0];
end
end
NINE:
begin
dprio_write_done = 0;
dprio_next_state = TEN;
avmm_dprio_write = 1'b1;
avmm_dprio_byteen = 2'b11;
if (dsm_k_changed & !dsm_k_done_q)
begin
avmm_dprio_address = DSM_K_FRACTIONAL_DIVISION_ADDR_1;
avmm_dprio_writedata[15:0] = usr_k_value[31:16];
end
end
TEN:
begin
dprio_write_done = 0;
dprio_next_state = ONE;
avmm_dprio_write = 1'b1;
avmm_dprio_byteen = 2'b11;
if (dsm_k_changed & !dsm_k_done_q)
begin
avmm_dprio_address = DSM_K_READY_ADDR;
//already have the readdata for DSM_K_READY_ADDR since we read it
//earlier. Just reuse here
avmm_dprio_writedata = dprio_temp_m_n_c_readdata_2_q;
avmm_dprio_writedata[DSM_K_READY_BIT_INDEX] = 1'b1;
dsm_k_done_d = 1'b1;
end
end
DPRIO_DONE:
begin
dprio_write_done = 1'b1;
if (dprio_start) dprio_next_state = DPRIO_IDLE;
else dprio_next_state = DPRIO_DONE;
end
DPRIO_IDLE:
begin
if (dprio_start) dprio_next_state = ONE;
else dprio_next_state = DPRIO_IDLE;
end
default: dprio_next_state = 4'bxxxx;
endcase
end
end
//assert the waitreq signal according to the state of the slave
assign slave_waitrequest = (slave_mode==mode_WR) ? ((locked === 1'b1) ? (((current_state==WAIT_ON_LOCK) & !dprio_write_done) | !dps_done |reset|!dprio_init_done) : 1'b1) : 1'b0;
// Read operations
always @(*)
begin
status = 0;
if (slave_mode == mode_POLL)
//asserting status to 1 if the slave is done.
status = (current_state == LOCKED);
end
//************************************************************//
//************************************************************//
//******************** READ STATE MACHINE ********************//
//************************************************************//
//************************************************************//
reg [1:0] current_read_state;
reg [1:0] next_read_state;
reg [5:0] slave_address_int_d;
reg [5:0] slave_address_int_q;
reg dprio_read_1;
reg [5:0] dprio_address_1;
reg [1:0] dprio_byteen_1;
reg [4:0] usr_cnt_sel_1;
localparam READ = 2'b00, READ_WAIT = 2'b01, READ_IDLE = 2'b10;
always @(posedge clk)
begin
if (reset)
begin
current_read_state <= READ_IDLE;
slave_address_int_q <= 0;
slave_readdata_q <= 0;
end
else
begin
current_read_state <= next_read_state;
slave_address_int_q <= slave_address_int_d;
slave_readdata_q <= slave_readdata_d;
end
end
always @(*)
begin
dprio_read_1 = 0;
dprio_address_1 = 0;
dprio_byteen_1 = 0;
slave_address_int_d = 0;
slave_readdata_d = 0;
status_read = 0;
usr_cnt_sel_1 = 0;
case(current_read_state)
READ_IDLE:
begin
slave_address_int_d = 0;
next_read_state = READ_IDLE;
if ((current_state != WAIT_ON_LOCK) && slave_read)
begin
slave_address_int_d = slave_address;
if ((slave_address >= CNT_BASE) && (slave_address < CNT_BASE+18))
begin
next_read_state = READ_WAIT;
dprio_byteen_1 = 2'b11;
dprio_read_1 = 1'b1;
usr_cnt_sel_1 = (slave_address[4:0] - CNT_BASE);
if (fpll_1) dprio_address_1 = C_CNT_0_DIV_ADDR + C_CNT_0_DIV_ADDR_DPRIO_1 - cnt_sel;
else dprio_address_1 = C_CNT_0_DIV_ADDR + cnt_sel;
end
else
begin
case (slave_address)
MODE_REG:
begin
next_read_state = READ_WAIT;
slave_readdata_d = slave_mode;
end
STATUS_REG:
begin
next_read_state = READ_WAIT;
status_read = 1'b1;
slave_readdata_d = status;
end
N_REG:
begin
dprio_byteen_1 = 2'b11;
dprio_read_1 = 1'b1;
dprio_address_1 = N_CNT_DIV_ADDR;
next_read_state = READ_WAIT;
end
M_REG:
begin
dprio_byteen_1 = 2'b11;
dprio_read_1 = 1'b1;
dprio_address_1 = M_CNT_DIV_ADDR;
next_read_state = READ_WAIT;
end
BWCTRL_REG:
begin
dprio_byteen_1 = 2'b11;
dprio_read_1 = 1'b1;
dprio_address_1 = BWCTRL_ADDR;
next_read_state = READ_WAIT;
end
CP_CURRENT_REG:
begin
dprio_byteen_1 = 2'b11;
dprio_read_1 = 1'b1;
dprio_address_1 = CP_CURRENT_ADDR;
next_read_state = READ_WAIT;
end
default : next_read_state = READ_IDLE;
endcase
end
end
else
next_read_state = READ_IDLE;
end
READ_WAIT:
begin
next_read_state = READ;
slave_address_int_d = slave_address_int_q;
case (slave_address_int_q)
MODE_REG:
begin
slave_readdata_d = slave_readdata_q;
end
STATUS_REG:
begin
slave_readdata_d = slave_readdata_q;
end
endcase
end
READ:
begin
next_read_state = READ_IDLE;
slave_address_int_d = slave_address_int_q;
slave_readdata_d = dprio_readdata;
case (slave_address_int_q)
MODE_REG:
begin
slave_readdata_d = slave_readdata_q;
end
STATUS_REG:
begin
slave_readdata_d = slave_readdata_q;
end
BWCTRL_REG:
begin
slave_readdata_d = dprio_readdata[3:0];
end
CP_CURRENT_REG:
begin
slave_readdata_d = dprio_readdata[2:0];
end
endcase
end
default: next_read_state = 2'bxx;
endcase
end
dyn_phase_shift dyn_phase_shift_inst (
.clk(clk),
.reset(reset),
.phase_done(phase_done),
.pll_start_valid(pll_start_valid),
.dps_changed(dps_changed),
.dps_changed_valid(dps_changed_valid),
.dprio_write_done(dprio_write_done),
.usr_num_shifts(usr_num_shifts),
.usr_cnt_sel(usr_cnt_sel|usr_cnt_sel_1),
.usr_up_dn(usr_up_dn),
.locked(locked),
.dps_done(dps_done),
.phase_en(phase_en),
.up_dn(up_dn),
.cnt_sel(cnt_sel));
defparam dyn_phase_shift_inst.device_family = device_family;
assign dprio_clk = clk;
self_reset self_reset_inst (mgmt_reset, clk, reset, dprio_init_reset);
dprio_mux dprio_mux_inst (
.init_dprio_address(init_dprio_address),
.init_dprio_read(init_dprio_read),
.init_dprio_byteen(init_dprio_byteen),
.init_dprio_write(init_dprio_write),
.init_dprio_writedata(init_dprio_writedata),
.init_atpgmode(init_atpgmode),
.init_mdio_dis(init_mdio_dis),
.init_scanen(init_scanen),
.init_ser_shift_load(init_ser_shift_load),
.dprio_init_done(dprio_init_done),
// Inputs from avmm master
.avmm_dprio_address(avmm_dprio_address | dprio_address_1),
.avmm_dprio_read(avmm_dprio_read | dprio_read_1),
.avmm_dprio_byteen(avmm_dprio_byteen | dprio_byteen_1),
.avmm_dprio_write(avmm_dprio_write),
.avmm_dprio_writedata(avmm_dprio_writedata),
.avmm_atpgmode(avmm_atpgmode),
.avmm_mdio_dis(avmm_mdio_dis),
.avmm_scanen(avmm_scanen),
// Outputs to fpll
.dprio_address(dprio_address),
.dprio_read(dprio_read),
.dprio_byteen(dprio_byteen),
.dprio_write(dprio_write),
.dprio_writedata(dprio_writedata),
.atpgmode(dprio_atpgmode),
.mdio_dis(dprio_mdio_dis),
.scanen(dprio_scanen),
.ser_shift_load(dprio_ser_shift_load)
);
fpll_dprio_init fpll_dprio_init_inst (
.clk(clk),
.reset_n(~reset),
.locked(locked),
//outputs
.dprio_address(init_dprio_address),
.dprio_read(init_dprio_read),
.dprio_byteen(init_dprio_byteen),
.dprio_write(init_dprio_write),
.dprio_writedata(init_dprio_writedata),
.atpgmode(init_atpgmode),
.mdio_dis(init_mdio_dis),
.scanen(init_scanen),
.ser_shift_load(init_ser_shift_load),
.dprio_init_done(dprio_init_done));
//address luts, to be reconfigged by the Fitter
//FPLL_1 or 0 address lut
generic_lcell_comb lcell_fpll_0_1 (
.dataa(1'b0),
.combout (fpll_1));
defparam lcell_fpll_0_1.lut_mask = 64'hAAAAAAAAAAAAAAAA;
defparam lcell_fpll_0_1.dont_touch = "on";
defparam lcell_fpll_0_1.family = device_family;
wire dprio_read_combout;
generic_lcell_comb lcell_dprio_read (
.dataa(fpll_1),
.datab(dprio_read),
.datac(1'b0),
.datad(1'b0),
.datae(1'b0),
.dataf(1'b0),
.combout (dprio_read_combout));
defparam lcell_dprio_read.lut_mask = 64'hCCCCCCCCCCCCCCCC;
defparam lcell_dprio_read.dont_touch = "on";
defparam lcell_dprio_read.family = device_family;
//assign reconfig_to_pll signals
assign reconfig_to_pll[0] = dprio_clk;
assign reconfig_to_pll[1] = ~dprio_init_reset;
assign reconfig_to_pll[2] = dprio_write;
assign reconfig_to_pll[3] = dprio_read_combout;
assign reconfig_to_pll[9:4] = dprio_address;
assign reconfig_to_pll[25:10] = dprio_writedata;
assign reconfig_to_pll[27:26] = dprio_byteen;
assign reconfig_to_pll[28] = dprio_ser_shift_load;
assign reconfig_to_pll[29] = dprio_mdio_dis;
assign reconfig_to_pll[30] = phase_en;
assign reconfig_to_pll[31] = up_dn;
assign reconfig_to_pll[36:32] = cnt_sel;
assign reconfig_to_pll[37] = dprio_scanen;
assign reconfig_to_pll[38] = dprio_atpgmode;
//assign reconfig_to_pll[40:37] = clken;
assign reconfig_to_pll[63:39] = 0;
//assign reconfig_from_pll signals
assign dprio_readdata = reconfig_from_pll [15:0];
assign locked = reconfig_from_pll [16];
assign phase_done = reconfig_from_pll [17];
endmodule
module self_reset (input wire mgmt_reset, input wire clk, output wire reset, output wire init_reset);
localparam RESET_COUNTER_VALUE = 3'd2;
localparam INITIAL_WAIT_VALUE = 9'd340;
reg [9:0]counter;
reg local_reset;
reg usr_mode_init_wait;
initial
begin
local_reset = 1'b1;
counter = 0;
usr_mode_init_wait = 0;
end
always @(posedge clk)
begin
if (mgmt_reset)
begin
counter <= 0;
end
else
begin
if (!usr_mode_init_wait)
begin
if (counter == INITIAL_WAIT_VALUE)
begin
local_reset <= 0;
usr_mode_init_wait <= 1'b1;
counter <= 0;
end
else
begin
counter <= counter + 1'b1;
end
end
else
begin
if (counter == RESET_COUNTER_VALUE)
local_reset <= 0;
else
counter <= counter + 1'b1;
end
end
end
assign reset = mgmt_reset | local_reset;
assign init_reset = local_reset;
endmodule
module dprio_mux (
// Inputs from init block
input [ 5:0] init_dprio_address,
input init_dprio_read,
input [ 1:0] init_dprio_byteen,
input init_dprio_write,
input [15:0] init_dprio_writedata,
input init_atpgmode,
input init_mdio_dis,
input init_scanen,
input init_ser_shift_load,
input dprio_init_done,
// Inputs from avmm master
input [ 5:0] avmm_dprio_address,
input avmm_dprio_read,
input [ 1:0] avmm_dprio_byteen,
input avmm_dprio_write,
input [15:0] avmm_dprio_writedata,
input avmm_atpgmode,
input avmm_mdio_dis,
input avmm_scanen,
input avmm_ser_shift_load,
// Outputs to fpll
output [ 5:0] dprio_address,
output dprio_read,
output [ 1:0] dprio_byteen,
output dprio_write,
output [15:0] dprio_writedata,
output atpgmode,
output mdio_dis,
output scanen,
output ser_shift_load
);
assign dprio_address = dprio_init_done ? avmm_dprio_address : init_dprio_address;
assign dprio_read = dprio_init_done ? avmm_dprio_read : init_dprio_read;
assign dprio_byteen = dprio_init_done ? avmm_dprio_byteen : init_dprio_byteen;
assign dprio_write = dprio_init_done ? avmm_dprio_write : init_dprio_write;
assign dprio_writedata = dprio_init_done ? avmm_dprio_writedata : init_dprio_writedata;
assign atpgmode = init_atpgmode;
assign scanen = init_scanen;
assign mdio_dis = init_mdio_dis;
assign ser_shift_load = init_ser_shift_load ;
endmodule
module fpll_dprio_init (
input clk,
input reset_n,
input locked,
output [ 5:0] dprio_address,
output dprio_read,
output [ 1:0] dprio_byteen,
output dprio_write,
output [15:0] dprio_writedata,
output reg atpgmode,
output reg mdio_dis,
output reg scanen,
output reg ser_shift_load,
output reg dprio_init_done
);
reg [1:0] rst_n = 2'b00;
reg [6:0] count = 7'd0;
reg init_done_forever;
// Internal versions of control signals
wire int_mdio_dis;
wire int_ser_shift_load;
wire int_dprio_init_done;
wire int_atpgmode/*synthesis keep*/;
wire int_scanen/*synthesis keep*/;
assign dprio_address = count[6] ? 5'b0 : count[5:0] ;
assign dprio_byteen = 2'b11; // always enabled
assign dprio_write = ~count[6] & reset_n ; // write for first 64 cycles
assign dprio_read = 1'b0;
assign dprio_writedata = 16'd0;
assign int_ser_shift_load = count[6] ? |count[2:1] : 1'b1;
assign int_mdio_dis = count[6] ? ~count[2] : 1'b1;
assign int_dprio_init_done = ~init_done_forever ? (count[6] ? &count[2:0] : 1'b0)
: 1'b1;
assign int_atpgmode = 0;
assign int_scanen = 0;
initial begin
count = 7'd0;
init_done_forever = 0;
mdio_dis = 1'b1;
ser_shift_load = 1'b1;
dprio_init_done = 1'b0;
scanen = 1'b0;
atpgmode = 1'b0;
end
// reset synch.
always @(posedge clk or negedge reset_n)
if(!reset_n) rst_n <= 2'b00;
else rst_n <= {rst_n[0],1'b1};
// counter
always @(posedge clk)
begin
if (!rst_n[1])
init_done_forever <= 1'b0;
else
begin
if (count[6] && &count[1:0])
init_done_forever <= 1'b1;
end
end
always @(posedge clk or negedge rst_n[1])
begin
if(!rst_n[1])
begin
count <= 7'd0;
end
else if(~int_dprio_init_done)
begin
count <= count + 7'd1;
end
else
begin
count <= count;
end
end
// outputs
always @(posedge clk) begin
mdio_dis <= int_mdio_dis;
ser_shift_load <= int_ser_shift_load;
dprio_init_done <= int_dprio_init_done;
atpgmode <= int_atpgmode;
scanen <= int_scanen;
end
endmodule
module dyn_phase_shift
#(
parameter device_family = "Stratix V"
) (
input wire clk,
input wire reset,
input wire phase_done,
input wire pll_start_valid,
input wire dps_changed,
input wire dprio_write_done,
input wire [15:0] usr_num_shifts,
input wire [4:0] usr_cnt_sel,
input wire usr_up_dn,
input wire locked,
//output
output wire dps_done,
output reg phase_en,
output wire up_dn,
output wire dps_changed_valid,
output wire [4:0] cnt_sel);
reg first_phase_shift_d;
reg first_phase_shift_q;
reg [15:0] phase_en_counter;
reg [3:0] dps_current_state;
reg [3:0] dps_next_state;
localparam DPS_START = 4'd0, DPS_WAIT_PHASE_DONE = 4'd1, DPS_DONE = 4'd2, DPS_WAIT_PHASE_EN = 4'd3, DPS_WAIT_DPRIO_WRITING = 4'd4, DPS_CHANGED = 4'd5;
localparam PHASE_EN_WAIT_COUNTER = 5'd1;
reg [15:0] shifts_done_counter;
reg phase_done_final;
wire gnd /*synthesis keep*/;
//fsm
//always block controlling the state regs
always @(posedge clk)
begin
if (reset)
begin
dps_current_state <= DPS_DONE;
end
else
begin
dps_current_state <= dps_next_state;
end
end
//the combinational part. assigning the next state
//this turns on the phase_done_final signal when phase_done does this:
//_____ ______
// |______|
always @(*)
begin
phase_done_final = 0;
first_phase_shift_d = 0;
phase_en = 0;
dps_next_state = DPS_DONE;
case (dps_current_state)
DPS_START:
begin
phase_en = 1'b1;
dps_next_state = DPS_WAIT_PHASE_EN;
end
DPS_WAIT_PHASE_EN:
begin
phase_en = 1'b1;
if (first_phase_shift_q)
begin
first_phase_shift_d = 1'b1;
dps_next_state = DPS_WAIT_PHASE_EN;
end
else
begin
if (phase_en_counter == PHASE_EN_WAIT_COUNTER)
dps_next_state = DPS_WAIT_PHASE_DONE;
else dps_next_state = DPS_WAIT_PHASE_EN;
end
end
DPS_WAIT_PHASE_DONE:
begin
if (!phase_done | !locked)
begin
dps_next_state = DPS_WAIT_PHASE_DONE;
end
else
begin
if ((usr_num_shifts != shifts_done_counter) & (usr_num_shifts != 0))
begin
dps_next_state = DPS_START;
phase_done_final = 1'b1;
end
else
begin
dps_next_state = DPS_DONE;
end
end
end
DPS_DONE:
begin
phase_done_final = 0;
if (dps_changed)
dps_next_state = DPS_CHANGED;
else dps_next_state = DPS_DONE;
end
DPS_CHANGED:
begin
if (pll_start_valid)
dps_next_state = DPS_WAIT_DPRIO_WRITING;
else
dps_next_state = DPS_CHANGED;
end
DPS_WAIT_DPRIO_WRITING:
begin
if (dprio_write_done)
dps_next_state = DPS_START;
else
dps_next_state = DPS_WAIT_DPRIO_WRITING;
end
default: dps_next_state = 4'bxxxx;
endcase
end
always @(posedge clk)
begin
if (dps_current_state == DPS_WAIT_PHASE_DONE)
phase_en_counter <= 0;
else if (dps_current_state == DPS_WAIT_PHASE_EN)
phase_en_counter <= phase_en_counter + 1'b1;
if (reset)
begin
phase_en_counter <= 0;
shifts_done_counter <= 1'b1;
first_phase_shift_q <= 1;
end
else
begin
if (first_phase_shift_d)
first_phase_shift_q <= 0;
if (dps_done)
begin
shifts_done_counter <= 1'b1;
end
else
begin
if (phase_done_final & (dps_next_state!= DPS_DONE))
shifts_done_counter <= shifts_done_counter + 1'b1;
else
shifts_done_counter <= shifts_done_counter;
end
end
end
assign dps_changed_valid = (dps_current_state == DPS_CHANGED);
assign dps_done =(dps_current_state == DPS_DONE) | (dps_current_state == DPS_CHANGED);
assign up_dn = usr_up_dn;
assign gnd = 1'b0;
//cnt select luts (5)
generic_lcell_comb lcell_cnt_sel_0 (
.dataa(usr_cnt_sel[0]),
.datab(usr_cnt_sel[1]),
.datac(usr_cnt_sel[2]),
.datad(usr_cnt_sel[3]),
.datae(usr_cnt_sel[4]),
.dataf(gnd),
.combout (cnt_sel[0]));
defparam lcell_cnt_sel_0.lut_mask = 64'hAAAAAAAAAAAAAAAA;
defparam lcell_cnt_sel_0.dont_touch = "on";
defparam lcell_cnt_sel_0.family = device_family;
generic_lcell_comb lcell_cnt_sel_1 (
.dataa(usr_cnt_sel[0]),
.datab(usr_cnt_sel[1]),
.datac(usr_cnt_sel[2]),
.datad(usr_cnt_sel[3]),
.datae(usr_cnt_sel[4]),
.dataf(gnd),
.combout (cnt_sel[1]));
defparam lcell_cnt_sel_1.lut_mask = 64'hCCCCCCCCCCCCCCCC;
defparam lcell_cnt_sel_1.dont_touch = "on";
defparam lcell_cnt_sel_1.family = device_family;
generic_lcell_comb lcell_cnt_sel_2 (
.dataa(usr_cnt_sel[0]),
.datab(usr_cnt_sel[1]),
.datac(usr_cnt_sel[2]),
.datad(usr_cnt_sel[3]),
.datae(usr_cnt_sel[4]),
.dataf(gnd),
.combout (cnt_sel[2]));
defparam lcell_cnt_sel_2.lut_mask = 64'hF0F0F0F0F0F0F0F0;
defparam lcell_cnt_sel_2.dont_touch = "on";
defparam lcell_cnt_sel_2.family = device_family;
generic_lcell_comb lcell_cnt_sel_3 (
.dataa(usr_cnt_sel[0]),
.datab(usr_cnt_sel[1]),
.datac(usr_cnt_sel[2]),
.datad(usr_cnt_sel[3]),
.datae(usr_cnt_sel[4]),
.dataf(gnd),
.combout (cnt_sel[3]));
defparam lcell_cnt_sel_3.lut_mask = 64'hFF00FF00FF00FF00;
defparam lcell_cnt_sel_3.dont_touch = "on";
defparam lcell_cnt_sel_3.family = device_family;
generic_lcell_comb lcell_cnt_sel_4 (
.dataa(usr_cnt_sel[0]),
.datab(usr_cnt_sel[1]),
.datac(usr_cnt_sel[2]),
.datad(usr_cnt_sel[3]),
.datae(usr_cnt_sel[4]),
.dataf(gnd),
.combout (cnt_sel[4]));
defparam lcell_cnt_sel_4.lut_mask = 64'hFFFF0000FFFF0000;
defparam lcell_cnt_sel_4.dont_touch = "on";
defparam lcell_cnt_sel_4.family = device_family;
endmodule
module generic_lcell_comb
#(
//parameter
parameter family = "Stratix V",
parameter lut_mask = 64'hAAAAAAAAAAAAAAAA,
parameter dont_touch = "on"
) (
input dataa,
input datab,
input datac,
input datad,
input datae,
input dataf,
output combout
);
generate
if (family == "Stratix V")
begin
stratixv_lcell_comb lcell_inst (
.dataa(dataa),
.datab(datab),
.datac(datac),
.datad(datad),
.datae(datae),
.dataf(dataf),
.combout (combout));
defparam lcell_inst.lut_mask = lut_mask;
defparam lcell_inst.dont_touch = dont_touch;
end
else if (family == "Arria V")
begin
arriav_lcell_comb lcell_inst (
.dataa(dataa),
.datab(datab),
.datac(datac),
.datad(datad),
.datae(datae),
.dataf(dataf),
.combout (combout));
defparam lcell_inst.lut_mask = lut_mask;
defparam lcell_inst.dont_touch = dont_touch;
end
else if (family == "Arria V GZ")
begin
arriavgz_lcell_comb lcell_inst (
.dataa(dataa),
.datab(datab),
.datac(datac),
.datad(datad),
.datae(datae),
.dataf(dataf),
.combout (combout));
defparam lcell_inst.lut_mask = lut_mask;
defparam lcell_inst.dont_touch = dont_touch;
end
else if (family == "Cyclone V")
begin
cyclonev_lcell_comb lcell_inst (
.dataa(dataa),
.datab(datab),
.datac(datac),
.datad(datad),
.datae(datae),
.dataf(dataf),
.combout (combout));
defparam lcell_inst.lut_mask = lut_mask;
defparam lcell_inst.dont_touch = dont_touch;
end
endgenerate
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A221OI_TB_V
`define SKY130_FD_SC_MS__A221OI_TB_V
/**
* a221oi: 2-input AND into first two inputs of 3-input NOR.
*
* Y = !((A1 & A2) | (B1 & B2) | C1)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__a221oi.v"
module top();
// Inputs are registered
reg A1;
reg A2;
reg B1;
reg B2;
reg C1;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A1 = 1'bX;
A2 = 1'bX;
B1 = 1'bX;
B2 = 1'bX;
C1 = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A1 = 1'b0;
#40 A2 = 1'b0;
#60 B1 = 1'b0;
#80 B2 = 1'b0;
#100 C1 = 1'b0;
#120 VGND = 1'b0;
#140 VNB = 1'b0;
#160 VPB = 1'b0;
#180 VPWR = 1'b0;
#200 A1 = 1'b1;
#220 A2 = 1'b1;
#240 B1 = 1'b1;
#260 B2 = 1'b1;
#280 C1 = 1'b1;
#300 VGND = 1'b1;
#320 VNB = 1'b1;
#340 VPB = 1'b1;
#360 VPWR = 1'b1;
#380 A1 = 1'b0;
#400 A2 = 1'b0;
#420 B1 = 1'b0;
#440 B2 = 1'b0;
#460 C1 = 1'b0;
#480 VGND = 1'b0;
#500 VNB = 1'b0;
#520 VPB = 1'b0;
#540 VPWR = 1'b0;
#560 VPWR = 1'b1;
#580 VPB = 1'b1;
#600 VNB = 1'b1;
#620 VGND = 1'b1;
#640 C1 = 1'b1;
#660 B2 = 1'b1;
#680 B1 = 1'b1;
#700 A2 = 1'b1;
#720 A1 = 1'b1;
#740 VPWR = 1'bx;
#760 VPB = 1'bx;
#780 VNB = 1'bx;
#800 VGND = 1'bx;
#820 C1 = 1'bx;
#840 B2 = 1'bx;
#860 B1 = 1'bx;
#880 A2 = 1'bx;
#900 A1 = 1'bx;
end
sky130_fd_sc_ms__a221oi dut (.A1(A1), .A2(A2), .B1(B1), .B2(B2), .C1(C1), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__A221OI_TB_V
|
//*****************************************************************************
// (c) Copyright 2008-2009 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: %version
// \ \ Application: MIG
// / / Filename: afifo.v
// /___/ /\ Date Last Modified: $Date: 2011/06/02 07:16:32 $
// \ \ / \ Date Created: Oct 21 2008
// \___\/\___\
//
//Device: Spartan6
//Design Name: DDR/DDR2/DDR3/LPDDR
//Purpose: A generic synchronous fifo.
//Reference:
//Revision History:
//*****************************************************************************
`timescale 1ps/1ps
module afifo #
(
parameter TCQ = 100,
parameter DSIZE = 32,
parameter FIFO_DEPTH = 16,
parameter ASIZE = 4,
parameter SYNC = 1 // only has always '1' logic.
)
(
input wr_clk,
input rst,
input wr_en,
input [DSIZE-1:0] wr_data,
input rd_en,
input rd_clk,
output [DSIZE-1:0] rd_data,
output reg full,
output reg empty,
output reg almost_full
);
// memory array
reg [DSIZE-1:0] mem [0:FIFO_DEPTH-1];
//Read Capture Logic
// if Sync = 1, then no need to remove metastability logic because wrclk = rdclk
reg [ASIZE:0] rd_gray_nxt;
reg [ASIZE:0] rd_gray;
reg [ASIZE:0] rd_capture_ptr;
reg [ASIZE:0] pre_rd_capture_gray_ptr;
reg [ASIZE:0] rd_capture_gray_ptr;
reg [ASIZE:0] wr_gray;
reg [ASIZE:0] wr_gray_nxt;
reg [ASIZE:0] wr_capture_ptr;
reg [ASIZE:0] pre_wr_capture_gray_ptr;
reg [ASIZE:0] wr_capture_gray_ptr;
wire [ASIZE:0] buf_avail;
wire [ASIZE:0] buf_filled;
wire [ASIZE-1:0] wr_addr, rd_addr;
reg [ASIZE:0] wr_ptr, rd_ptr;
integer i,j,k;
// for design that use the same clock for both read and write
generate
if (SYNC == 1) begin: RDSYNC
always @ (rd_ptr)
rd_capture_ptr = rd_ptr;
end
endgenerate
//capture the wr_gray_pointers to rd_clk domains and convert the gray pointers to binary pointers
// before do comparison.
// if Sync = 1, then no need to remove metastability logic because wrclk = rdclk
generate
if (SYNC == 1) begin: WRSYNC
always @ (wr_ptr)
wr_capture_ptr = wr_ptr;
end
endgenerate
// dualport ram
// Memory (RAM) that holds the contents of the FIFO
assign wr_addr = wr_ptr;
assign rd_data = mem[rd_addr];
always @(posedge wr_clk)
begin
if (wr_en && !full)
mem[wr_addr] <= #TCQ wr_data;
end
// Read Side Logic
assign rd_addr = rd_ptr[ASIZE-1:0];
assign rd_strobe = rd_en && !empty;
integer n;
reg [ASIZE:0] rd_ptr_tmp;
// change the binary pointer to gray pointer
always @ (rd_ptr)
begin
// rd_gray_nxt[ASIZE] = rd_ptr_tmp[ASIZE];
// for (n=0; n < ASIZE; n=n+1)
// rd_gray_nxt[n] = rd_ptr_tmp[n] ^ rd_ptr_tmp[n+1];
rd_gray_nxt[ASIZE] = rd_ptr[ASIZE];
for (n=0; n < ASIZE; n=n+1)
rd_gray_nxt[n] = rd_ptr[n] ^ rd_ptr[n+1];
end
always @(posedge rd_clk)
begin
if (rst)
begin
rd_ptr <= #TCQ 'b0;
rd_gray <= #TCQ 'b0;
end
else begin
if (rd_strobe)
rd_ptr <= #TCQ rd_ptr + 1;
rd_ptr_tmp <= #TCQ rd_ptr;
// change the binary pointer to gray pointer
rd_gray <= #TCQ rd_gray_nxt;
end
end
//generate empty signal
assign buf_filled = wr_capture_ptr - rd_ptr;
always @ (posedge rd_clk )
begin
if (rst)
empty <= #TCQ 1'b1;
else if ((buf_filled == 0) || (buf_filled == 1 && rd_strobe))
empty <= #TCQ 1'b1;
else
empty <= #TCQ 1'b0;
end
// write side logic;
reg [ASIZE:0] wbin;
wire [ASIZE:0] wgraynext, wbinnext;
always @(posedge rd_clk)
begin
if (rst)
begin
wr_ptr <= #TCQ 'b0;
wr_gray <= #TCQ 'b0;
end
else begin
if (wr_en)
wr_ptr <= #TCQ wr_ptr + 1;
// change the binary pointer to gray pointer
wr_gray <= #TCQ wr_gray_nxt;
end
end
// change the write pointer to gray pointer
always @ (wr_ptr)
begin
wr_gray_nxt[ASIZE] = wr_ptr[ASIZE];
for (n=0; n < ASIZE; n=n+1)
wr_gray_nxt[n] = wr_ptr[n] ^ wr_ptr[n+1];
end
// calculate how many buf still available
assign buf_avail = (rd_capture_ptr + FIFO_DEPTH) - wr_ptr;
always @ (posedge wr_clk )
begin
if (rst)
full <= #TCQ 1'b0;
else if ((buf_avail == 0) || (buf_avail == 1 && wr_en))
full <= #TCQ 1'b1;
else
full <= #TCQ 1'b0;
end
always @ (posedge wr_clk )
begin
if (rst)
almost_full <= #TCQ 1'b0;
else if ((buf_avail == FIFO_DEPTH - 2 ) || ((buf_avail == FIFO_DEPTH -3) && wr_en))
almost_full <= #TCQ 1'b1;
else
almost_full <= #TCQ 1'b0;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__NOR3_1_V
`define SKY130_FD_SC_LS__NOR3_1_V
/**
* nor3: 3-input NOR.
*
* Y = !(A | B | C | !D)
*
* Verilog wrapper for nor3 with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__nor3.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__nor3_1 (
Y ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__nor3 base (
.Y(Y),
.A(A),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__nor3_1 (
Y,
A,
B,
C
);
output Y;
input A;
input B;
input C;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__nor3 base (
.Y(Y),
.A(A),
.B(B),
.C(C)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__NOR3_1_V
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 05/12/2015 06:11:28 PM
// Design Name:
// Module Name: system_controller
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module system_controller(
input CLK_IN,
input RESET_IN,
output CLK_OUT,
output RESET_OUT
);
reg [4:0] reset_count = 4'h00;
//
// Input buffer to make sure the XCLK signal is routed
// onto the low skew clock lines
//
wire xclk_buf;
IBUFG xclk_ibufg(.I(CLK_IN), .O(xclk_buf));
//
// Using our input clk buffer, we sample the input reset
// signal. if it is high, we hold the count to 1 (NOT 0!)
// Once the input reset is released, we will count until
// we wrap around to 0. While this counter is not 0,
// assert the reset signal to all other blocks. This is done
// to ensure we get a good clean synchronous reset of all flops
// in the device
//
// This is the ONLY place we use xclk_buf or XRESET!
//
wire LOCKED;
assign RESET_OUT = RESET_IN;
// assign dcm_reset = |reset_count;
/* -----\/----- EXCLUDED -----\/-----
assign RESET_OUT = !LOCKED || (|reset_count);
always @(posedge xclk_buf)
if (RESET_IN)
reset_count <= 'h01;
else
if ( (|reset_count) & LOCKED)
reset_count <= reset_count +1;
-----/\----- EXCLUDED -----/\----- */
//
// DCM Reset Logic. This is also off the xclk_buf since
// we want this to be synchronous and held for a few clocks
// in order for the DCM to get a good reset.
//
// This is the ONLY place we use xclk_buf or XRESET!
//
/* -----\/----- EXCLUDED -----\/-----
reg [3:0] dcm_reset_count = 4'h00;
assign dcm_reset = |dcm_reset_count;
always @(posedge xclk_buf)
if (RESET_IN)
dcm_reset_count <= 'h01;
else
if (dcm_reset_count)
dcm_reset_count <= dcm_reset_count + 1;
-----/\----- EXCLUDED -----/\----- */
//
// Clock buffer that ensures the clock going out to the hardware is on a low skew line
//
BUFG clk_bug (
.O(CLK_OUT), // 1-bit output Clock buffer output
.I(CLKFBOUT) // 1-bit input Clock buffer input (S=0)
);
// MMCME2_BASE: Base Mixed Mode Clock Manager
//
// Xilinx HDL Libraries Guide, version 14.2
MMCME2_BASE #(
.BANDWIDTH("OPTIMIZED"),
// Jitter programming (OPTIMIZED, HIGH, LOW)
.CLKFBOUT_MULT_F(6.0),
// Multiply value for all CLKOUT (2.000-64.000).
.CLKFBOUT_PHASE(0.0),
// Phase offset in degrees of CLKFB (-360.000-360.000).
.CLKIN1_PERIOD(10.0),
// Input clock period in ns to ps resolution (i.e. 33.333 is 30 MHz).
// CLKOUT0_DIVIDE - CLKOUT6_DIVIDE: Divide amount for each CLKOUT (1-128)
.CLKOUT1_DIVIDE(1),
.CLKOUT2_DIVIDE(1),
.CLKOUT3_DIVIDE(1),
.CLKOUT4_DIVIDE(1),
.CLKOUT5_DIVIDE(1),
.CLKOUT6_DIVIDE(1),
.CLKOUT0_DIVIDE_F(1.0),
// Divide amount for CLKOUT0 (1.000-128.000).
// CLKOUT0_DUTY_CYCLE - CLKOUT6_DUTY_CYCLE: Duty cycle for each CLKOUT (0.01-0.99).
.CLKOUT0_DUTY_CYCLE(0.5),
.CLKOUT1_DUTY_CYCLE(0.5),
.CLKOUT2_DUTY_CYCLE(0.5),
.CLKOUT3_DUTY_CYCLE(0.5),
.CLKOUT4_DUTY_CYCLE(0.5),
.CLKOUT5_DUTY_CYCLE(0.5),
.CLKOUT6_DUTY_CYCLE(0.5),
// CLKOUT0_PHASE - CLKOUT6_PHASE: Phase offset for each CLKOUT (-360.000-360.000).
.CLKOUT0_PHASE(0.0),
.CLKOUT1_PHASE(0.0),
.CLKOUT2_PHASE(0.0),
.CLKOUT3_PHASE(0.0),
.CLKOUT4_PHASE(0.0),
.CLKOUT5_PHASE(0.0),
.CLKOUT6_PHASE(0.0),
.CLKOUT4_CASCADE("FALSE"), // Cascade CLKOUT4 counter with CLKOUT6 (FALSE, TRUE)
.DIVCLK_DIVIDE(1),
// Master division value (1-106)
.REF_JITTER1(0.0),
// Reference input jitter in UI (0.000-0.999).
.STARTUP_WAIT("FALSE")
// Delays DONE until MMCM is locked (FALSE, TRUE)
)
MMCME2_BASE_inst (
// Clock Outputs: 1-bit (each) output: User configurable clock outputs
.CLKOUT0(),
// 1-bit output: CLKOUT0
.CLKOUT0B(),
// 1-bit output: Inverted CLKOUT0
.CLKOUT1(),
// 1-bit output: CLKOUT1
.CLKOUT1B(),
// 1-bit output: Inverted CLKOUT1
.CLKOUT2(),
// 1-bit output: CLKOUT2
.CLKOUT2B(),
// 1-bit output: Inverted CLKOUT2
.CLKOUT3(),
// 1-bit output: CLKOUT3
.CLKOUT3B(),
// 1-bit output: Inverted CLKOUT3
.CLKOUT4(),
// 1-bit output: CLKOUT4
.CLKOUT5(),
// 1-bit output: CLKOUT5
.CLKOUT6(),
// 1-bit output: CLKOUT6
// Feedback Clocks: 1-bit (each) output: Clock feedback ports
.CLKFBOUT(CLKFBOUT),
// 1-bit output: Feedback clock
.CLKFBOUTB(), // 1-bit output: Inverted CLKFBOUT
// Status Ports: 1-bit (each) output: MMCM status ports
.LOCKED(LOCKED),
// 1-bit output: LOCK
// Clock Inputs: 1-bit (each) input: Clock input
.CLKIN1(xclk_buf),
// 1-bit input: Clock
// Control Ports: 1-bit (each) input: MMCM control ports
.PWRDWN(1'b0),
// 1-bit input: Power-down
// .RST(dcm_reset),
.RST(RESET_IN),
// 1-bit input: Reset
// Feedback Clocks: 1-bit (each) input: Clock feedback ports
.CLKFBIN(CLK_OUT)
// 1-bit input: Feedback clock
);
// End of MMCME2_BASE_inst instantiation
endmodule // system_control
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DLRTN_SYMBOL_V
`define SKY130_FD_SC_HS__DLRTN_SYMBOL_V
/**
* dlrtn: Delay latch, inverted reset, inverted enable, single output.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__dlrtn (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{control|Control Signals}}
input RESET_B,
//# {{clocks|Clocking}}
input GATE_N
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__DLRTN_SYMBOL_V
|
// This is a component of pluto_servo, a PWM servo driver and quadrature
// counter for emc2
// Copyright 2006 Jeff Epler <[email protected]>
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
module wdt(clk, ena, cnt, out);
input clk, ena, cnt;
output out;
reg [6:0] timer;
wire timer_top = (timer == 7'd127);
reg internal_enable;
wire out = internal_enable && timer_top;
always @(posedge clk) begin
if(ena) begin
internal_enable <= 1;
timer <= 0;
end else if(cnt && !timer_top) timer <= timer + 7'd1;
end
endmodule
|
`define IDX(x) (((x)+1)*(32)-1):((x)*(32))
`define E0(x) ( {{x}[1:0],{x}[31:2]} ^ {{x}[12:0],{x}[31:13]} ^ {{x}[21:0],{x}[31:22]} )
`define E1(x) ( {{x}[5:0],{x}[31:6]} ^ {{x}[10:0],{x}[31:11]} ^ {{x}[24:0],{x}[31:25]} )
`define CH(x,y,z) ( (z) ^ ((x) & ((y) ^ (z))) )
`define MAJ(x,y,z) ( ((x) & (y)) | ((z) & ((x) | (y))) )
`define S0(x) ( { {x}[6:4] ^ {x}[17:15], {{x}[3:0], {x}[31:7]} ^ {{x}[14:0],{x}[31:18]} ^ {x}[31:3] } )
`define S1(x) ( { {x}[16:7] ^ {x}[18:9], {{x}[6:0], {x}[31:17]} ^ {{x}[8:0],{x}[31:19]} ^ {x}[31:10] } )
module dummy_pipe2_base ( clk, i_state, i_data, out );
parameter STAGES = 64;
input clk;
input [255:0] i_state;
input [511:0] i_data;
output [255:0] out;
localparam Ks = {
32'h428a2f98, 32'h71374491, 32'hb5c0fbcf, 32'he9b5dba5,
32'h3956c25b, 32'h59f111f1, 32'h923f82a4, 32'hab1c5ed5,
32'hd807aa98, 32'h12835b01, 32'h243185be, 32'h550c7dc3,
32'h72be5d74, 32'h80deb1fe, 32'h9bdc06a7, 32'hc19bf174,
32'he49b69c1, 32'hefbe4786, 32'h0fc19dc6, 32'h240ca1cc,
32'h2de92c6f, 32'h4a7484aa, 32'h5cb0a9dc, 32'h76f988da,
32'h983e5152, 32'ha831c66d, 32'hb00327c8, 32'hbf597fc7,
32'hc6e00bf3, 32'hd5a79147, 32'h06ca6351, 32'h14292967,
32'h27b70a85, 32'h2e1b2138, 32'h4d2c6dfc, 32'h53380d13,
32'h650a7354, 32'h766a0abb, 32'h81c2c92e, 32'h92722c85,
32'ha2bfe8a1, 32'ha81a664b, 32'hc24b8b70, 32'hc76c51a3,
32'hd192e819, 32'hd6990624, 32'hf40e3585, 32'h106aa070,
32'h19a4c116, 32'h1e376c08, 32'h2748774c, 32'h34b0bcb5,
32'h391c0cb3, 32'h4ed8aa4a, 32'h5b9cca4f, 32'h682e6ff3,
32'h748f82ee, 32'h78a5636f, 32'h84c87814, 32'h8cc70208,
32'h90befffa, 32'ha4506ceb, 32'hbef9a3f7, 32'hc67178f2
};
genvar i;
generate
for (i = 0; i <= STAGES; i = i + 1) begin : S
reg [511:0] data;
reg [223:0] state;
reg [31:0] t1_p1;
if(i == 0)
begin
always @ (posedge clk)
begin
data <= i_data;
state <= i_state[223:0];
t1_p1 <= i_state[`IDX(7)] + i_data[`IDX(0)] + Ks[`IDX(63)];
end
end else
begin
reg [511:0] data_buf;
reg [223:0] state_buf;
reg [31:0] data15_p1, data15_p2, data15_p3, t1, t1_helper, t1_helper2;
wire [31:0] state4 = state_buf[`IDX(3)] + t1;
always @ (posedge clk)
begin
data_buf <= S[i-1].data;
data[479:0] <= data_buf[511:32];
data15_p1 <= `S1( S[i-1].data[`IDX(15)] ); // 3
data15_p2 <= data15_p1; // 1
data15_p3 <= ( ( i == 1 ) ? `S1( S[i-1].data[`IDX(14)] ) : S[i-1].data15_p2 ) + S[i-1].data[`IDX(9)] + S[i-1].data[`IDX(0)]; // 3
data[`IDX(15)] <= `S0( data_buf[`IDX(1)] ) + data15_p3; // 4
state_buf <= S[i-1].state; // 2
t1 <= S[i-1].t1_helper + S[i-1].t1_helper2 + S[i-1].t1_p1; // 6
state[`IDX(0)] <= `MAJ( state_buf[`IDX(0)], state_buf[`IDX(1)], state_buf[`IDX(2)] ) + `E0( state_buf[`IDX(0)] ) + t1; // 7
state[`IDX(1)] <= state_buf[`IDX(0)]; // 1
state[`IDX(2)] <= state_buf[`IDX(1)]; // 1
state[`IDX(3)] <= state_buf[`IDX(2)]; // 1
state[`IDX(4)] <= state4; // 2
state[`IDX(5)] <= state_buf[`IDX(4)]; // 1
state[`IDX(6)] <= state_buf[`IDX(5)]; // 1
t1_p1 <= state_buf[`IDX(6)] + data_buf[`IDX(1)] + Ks[`IDX((127-i) & 63)]; // 2
t1_helper <= `CH( state4, state_buf[`IDX(4)], state_buf[`IDX(5)] );
t1_helper2 <= `E1( state4 );
end
end
end
endgenerate
reg [31:0] state7, state7_buf;
always @ (posedge clk)
begin
state7_buf <= S[STAGES-1].state[`IDX(6)];
state7 <= state7_buf;
end
assign out[223:0] = S[STAGES].state;
assign out[255:224] = state7;
endmodule
module dummy_pipe130 ( clk, state, state2, data, hash );
input clk;
input [255:0] state, state2;
input [511:0] data;
output reg [31:0] hash;
wire [255:0] out;
dummy_pipe2_base #( .STAGES(32) ) P (
.clk(clk),
.i_state(state),
.i_data(data),
.out(out)
);
always @ (posedge clk)
begin
hash <= out[`IDX(0)] ^ out[`IDX(1)] ^ out[`IDX(2)] ^ out[`IDX(3)] ^ out[`IDX(4)] ^ out[`IDX(5)] ^ out[`IDX(6)] ^ out[`IDX(7)];
end
endmodule
|
//-----------------------------------------------------
// Design Name : cam
// File Name : cam.v
// Function : CAM
// Coder : Deepak Kumar Tala
//-----------------------------------------------------
module cam (
clk , // Cam clock
cam_enable , // Cam enable
cam_data_in , // Cam data to match
cam_hit_out , // Cam match has happened
cam_addr_out // Cam output address
);
parameter ADDR_WIDTH = 8;
parameter DEPTH = 1 << ADDR_WIDTH;
//------------Input Ports--------------
input clk;
input cam_enable;
input [DEPTH-1:0] cam_data_in;
//----------Output Ports--------------
output cam_hit_out;
output [ADDR_WIDTH-1:0] cam_addr_out;
//------------Internal Variables--------
reg [ADDR_WIDTH-1:0] cam_addr_out;
reg cam_hit_out;
reg [ADDR_WIDTH-1:0] cam_addr_combo;
reg cam_hit_combo;
reg found_match;
integer i;
//-------------Code Starts Here-------
always @(cam_data_in) begin
cam_addr_combo = {ADDR_WIDTH{1'b0}};
found_match = 1'b0;
cam_hit_combo = 1'b0;
for (i=0; i<DEPTH; i=i+1) begin
if (cam_data_in[i] && !found_match) begin
found_match = 1'b1;
cam_hit_combo = 1'b1;
cam_addr_combo = i;
end else begin
found_match = found_match;
cam_hit_combo = cam_hit_combo;
cam_addr_combo = cam_addr_combo;
end
end
end
// Register the outputs
always @(posedge clk) begin
if (cam_enable) begin
cam_hit_out <= cam_hit_combo;
cam_addr_out <= cam_addr_combo;
end else begin
cam_hit_out <= 1'b0;
cam_addr_out <= {ADDR_WIDTH{1'b0}};
end
end
endmodule
|
// Generate a debug screen, displaying the hex value of three 32-bit registers.
module LCD_debug(
input wire [6:0] column,
input wire [5:0] row,
input wire [31:0] value0,
input wire [31:0] value1,
input wire [31:0] value2,
output reg [6:0] character
);
// Which value to display.
reg [31:0] display;
// Binary-to-hex converter.
reg [3:0] binary;
wire [6:0] hex;
Binary_to_hex binary_to_hex(
.value(binary),
.hex(hex)
);
// Lay out screen.
reg show_hex;
always @(*) begin
// Configure value by row.
case (row)
6'd2: display = value0;
6'd3: display = value1;
default: display = value2;
endcase
end
always @(*) begin
// Configure nybble for value output.
case (column)
7'd0: { show_hex, binary } = { 1'b1, display[31:28] };
7'd1: { show_hex, binary } = { 1'b1, display[27:24] };
7'd2: { show_hex, binary } = { 1'b1, display[23:20] };
7'd3: { show_hex, binary } = { 1'b1, display[19:16] };
7'd5: { show_hex, binary } = { 1'b1, display[15:12] };
7'd6: { show_hex, binary } = { 1'b1, display[11:8] };
7'd7: { show_hex, binary } = { 1'b1, display[7:4] };
7'd8: { show_hex, binary } = { 1'b1, display[3:0] };
default: { show_hex, binary } = { 1'b0, 4'h0 };
endcase
end
always @(*) begin
// Select output.
if (row == 6'd0) begin
case (column)
7'd0: character = 7'h41;
7'd1: character = 7'h6C;
7'd2: character = 7'h69;
7'd3: character = 7'h63;
7'd4: character = 7'h65;
7'd6: character = 7'h34;
7'd8: character = 7'h03;
default: character = 7'h20;
endcase
end else if (row >= 6'd2 && row <= 6'd4) begin
character = show_hex ? hex : 7'h20;
end else begin
character = 7'h20;
end
end
endmodule
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2018.2
// Copyright (C) 1986-2018 Xilinx, Inc. All Rights Reserved.
//
// ==============================================================
`timescale 1ns/1ps
module hls_macc_HLS_MACC_PERIPH_BUS_s_axi
#(parameter
C_S_AXI_ADDR_WIDTH = 6,
C_S_AXI_DATA_WIDTH = 32
)(
// axi4 lite slave signals
input wire ACLK,
input wire ARESET,
input wire ACLK_EN,
input wire [C_S_AXI_ADDR_WIDTH-1:0] AWADDR,
input wire AWVALID,
output wire AWREADY,
input wire [C_S_AXI_DATA_WIDTH-1:0] WDATA,
input wire [C_S_AXI_DATA_WIDTH/8-1:0] WSTRB,
input wire WVALID,
output wire WREADY,
output wire [1:0] BRESP,
output wire BVALID,
input wire BREADY,
input wire [C_S_AXI_ADDR_WIDTH-1:0] ARADDR,
input wire ARVALID,
output wire ARREADY,
output wire [C_S_AXI_DATA_WIDTH-1:0] RDATA,
output wire [1:0] RRESP,
output wire RVALID,
input wire RREADY,
output wire interrupt,
// user signals
output wire ap_start,
input wire ap_done,
input wire ap_ready,
input wire ap_idle,
output wire [31:0] a,
output wire [31:0] b,
input wire [31:0] accum,
input wire accum_ap_vld,
output wire [0:0] accum_clr
);
//------------------------Address Info-------------------
// 0x00 : Control signals
// bit 0 - ap_start (Read/Write/COH)
// bit 1 - ap_done (Read/COR)
// bit 2 - ap_idle (Read)
// bit 3 - ap_ready (Read)
// bit 7 - auto_restart (Read/Write)
// others - reserved
// 0x04 : Global Interrupt Enable Register
// bit 0 - Global Interrupt Enable (Read/Write)
// others - reserved
// 0x08 : IP Interrupt Enable Register (Read/Write)
// bit 0 - Channel 0 (ap_done)
// bit 1 - Channel 1 (ap_ready)
// others - reserved
// 0x0c : IP Interrupt Status Register (Read/TOW)
// bit 0 - Channel 0 (ap_done)
// bit 1 - Channel 1 (ap_ready)
// others - reserved
// 0x10 : Data signal of a
// bit 31~0 - a[31:0] (Read/Write)
// 0x14 : reserved
// 0x18 : Data signal of b
// bit 31~0 - b[31:0] (Read/Write)
// 0x1c : reserved
// 0x20 : Data signal of accum
// bit 31~0 - accum[31:0] (Read)
// 0x24 : Control signal of accum
// bit 0 - accum_ap_vld (Read/COR)
// others - reserved
// 0x28 : Data signal of accum_clr
// bit 0 - accum_clr[0] (Read/Write)
// others - reserved
// 0x2c : reserved
// (SC = Self Clear, COR = Clear on Read, TOW = Toggle on Write, COH = Clear on Handshake)
//------------------------Parameter----------------------
localparam
ADDR_AP_CTRL = 6'h00,
ADDR_GIE = 6'h04,
ADDR_IER = 6'h08,
ADDR_ISR = 6'h0c,
ADDR_A_DATA_0 = 6'h10,
ADDR_A_CTRL = 6'h14,
ADDR_B_DATA_0 = 6'h18,
ADDR_B_CTRL = 6'h1c,
ADDR_ACCUM_DATA_0 = 6'h20,
ADDR_ACCUM_CTRL = 6'h24,
ADDR_ACCUM_CLR_DATA_0 = 6'h28,
ADDR_ACCUM_CLR_CTRL = 6'h2c,
WRIDLE = 2'd0,
WRDATA = 2'd1,
WRRESP = 2'd2,
WRRESET = 2'd3,
RDIDLE = 2'd0,
RDDATA = 2'd1,
RDRESET = 2'd2,
ADDR_BITS = 6;
//------------------------Local signal-------------------
reg [1:0] wstate = WRRESET;
reg [1:0] wnext;
reg [ADDR_BITS-1:0] waddr;
wire [31:0] wmask;
wire aw_hs;
wire w_hs;
reg [1:0] rstate = RDRESET;
reg [1:0] rnext;
reg [31:0] rdata;
wire ar_hs;
wire [ADDR_BITS-1:0] raddr;
// internal registers
reg int_ap_idle;
reg int_ap_ready;
reg int_ap_done = 1'b0;
reg int_ap_start = 1'b0;
reg int_auto_restart = 1'b0;
reg int_gie = 1'b0;
reg [1:0] int_ier = 2'b0;
reg [1:0] int_isr = 2'b0;
reg [31:0] int_a = 'b0;
reg [31:0] int_b = 'b0;
reg [31:0] int_accum = 'b0;
reg int_accum_ap_vld;
reg [0:0] int_accum_clr = 'b0;
//------------------------Instantiation------------------
//------------------------AXI write fsm------------------
assign AWREADY = (wstate == WRIDLE);
assign WREADY = (wstate == WRDATA);
assign BRESP = 2'b00; // OKAY
assign BVALID = (wstate == WRRESP);
assign wmask = { {8{WSTRB[3]}}, {8{WSTRB[2]}}, {8{WSTRB[1]}}, {8{WSTRB[0]}} };
assign aw_hs = AWVALID & AWREADY;
assign w_hs = WVALID & WREADY;
// wstate
always @(posedge ACLK) begin
if (ARESET)
wstate <= WRRESET;
else if (ACLK_EN)
wstate <= wnext;
end
// wnext
always @(*) begin
case (wstate)
WRIDLE:
if (AWVALID)
wnext = WRDATA;
else
wnext = WRIDLE;
WRDATA:
if (WVALID)
wnext = WRRESP;
else
wnext = WRDATA;
WRRESP:
if (BREADY)
wnext = WRIDLE;
else
wnext = WRRESP;
default:
wnext = WRIDLE;
endcase
end
// waddr
always @(posedge ACLK) begin
if (ACLK_EN) begin
if (aw_hs)
waddr <= AWADDR[ADDR_BITS-1:0];
end
end
//------------------------AXI read fsm-------------------
assign ARREADY = (rstate == RDIDLE);
assign RDATA = rdata;
assign RRESP = 2'b00; // OKAY
assign RVALID = (rstate == RDDATA);
assign ar_hs = ARVALID & ARREADY;
assign raddr = ARADDR[ADDR_BITS-1:0];
// rstate
always @(posedge ACLK) begin
if (ARESET)
rstate <= RDRESET;
else if (ACLK_EN)
rstate <= rnext;
end
// rnext
always @(*) begin
case (rstate)
RDIDLE:
if (ARVALID)
rnext = RDDATA;
else
rnext = RDIDLE;
RDDATA:
if (RREADY & RVALID)
rnext = RDIDLE;
else
rnext = RDDATA;
default:
rnext = RDIDLE;
endcase
end
// rdata
always @(posedge ACLK) begin
if (ACLK_EN) begin
if (ar_hs) begin
rdata <= 1'b0;
case (raddr)
ADDR_AP_CTRL: begin
rdata[0] <= int_ap_start;
rdata[1] <= int_ap_done;
rdata[2] <= int_ap_idle;
rdata[3] <= int_ap_ready;
rdata[7] <= int_auto_restart;
end
ADDR_GIE: begin
rdata <= int_gie;
end
ADDR_IER: begin
rdata <= int_ier;
end
ADDR_ISR: begin
rdata <= int_isr;
end
ADDR_A_DATA_0: begin
rdata <= int_a[31:0];
end
ADDR_B_DATA_0: begin
rdata <= int_b[31:0];
end
ADDR_ACCUM_DATA_0: begin
rdata <= int_accum[31:0];
end
ADDR_ACCUM_CTRL: begin
rdata[0] <= int_accum_ap_vld;
end
ADDR_ACCUM_CLR_DATA_0: begin
rdata <= int_accum_clr[0:0];
end
endcase
end
end
end
//------------------------Register logic-----------------
assign interrupt = int_gie & (|int_isr);
assign ap_start = int_ap_start;
assign a = int_a;
assign b = int_b;
assign accum_clr = int_accum_clr;
// int_ap_start
always @(posedge ACLK) begin
if (ARESET)
int_ap_start <= 1'b0;
else if (ACLK_EN) begin
if (w_hs && waddr == ADDR_AP_CTRL && WSTRB[0] && WDATA[0])
int_ap_start <= 1'b1;
else if (ap_ready)
int_ap_start <= int_auto_restart; // clear on handshake/auto restart
end
end
// int_ap_done
always @(posedge ACLK) begin
if (ARESET)
int_ap_done <= 1'b0;
else if (ACLK_EN) begin
if (ap_done)
int_ap_done <= 1'b1;
else if (ar_hs && raddr == ADDR_AP_CTRL)
int_ap_done <= 1'b0; // clear on read
end
end
// int_ap_idle
always @(posedge ACLK) begin
if (ARESET)
int_ap_idle <= 1'b0;
else if (ACLK_EN) begin
int_ap_idle <= ap_idle;
end
end
// int_ap_ready
always @(posedge ACLK) begin
if (ARESET)
int_ap_ready <= 1'b0;
else if (ACLK_EN) begin
int_ap_ready <= ap_ready;
end
end
// int_auto_restart
always @(posedge ACLK) begin
if (ARESET)
int_auto_restart <= 1'b0;
else if (ACLK_EN) begin
if (w_hs && waddr == ADDR_AP_CTRL && WSTRB[0])
int_auto_restart <= WDATA[7];
end
end
// int_gie
always @(posedge ACLK) begin
if (ARESET)
int_gie <= 1'b0;
else if (ACLK_EN) begin
if (w_hs && waddr == ADDR_GIE && WSTRB[0])
int_gie <= WDATA[0];
end
end
// int_ier
always @(posedge ACLK) begin
if (ARESET)
int_ier <= 1'b0;
else if (ACLK_EN) begin
if (w_hs && waddr == ADDR_IER && WSTRB[0])
int_ier <= WDATA[1:0];
end
end
// int_isr[0]
always @(posedge ACLK) begin
if (ARESET)
int_isr[0] <= 1'b0;
else if (ACLK_EN) begin
if (int_ier[0] & ap_done)
int_isr[0] <= 1'b1;
else if (w_hs && waddr == ADDR_ISR && WSTRB[0])
int_isr[0] <= int_isr[0] ^ WDATA[0]; // toggle on write
end
end
// int_isr[1]
always @(posedge ACLK) begin
if (ARESET)
int_isr[1] <= 1'b0;
else if (ACLK_EN) begin
if (int_ier[1] & ap_ready)
int_isr[1] <= 1'b1;
else if (w_hs && waddr == ADDR_ISR && WSTRB[0])
int_isr[1] <= int_isr[1] ^ WDATA[1]; // toggle on write
end
end
// int_a[31:0]
always @(posedge ACLK) begin
if (ARESET)
int_a[31:0] <= 0;
else if (ACLK_EN) begin
if (w_hs && waddr == ADDR_A_DATA_0)
int_a[31:0] <= (WDATA[31:0] & wmask) | (int_a[31:0] & ~wmask);
end
end
// int_b[31:0]
always @(posedge ACLK) begin
if (ARESET)
int_b[31:0] <= 0;
else if (ACLK_EN) begin
if (w_hs && waddr == ADDR_B_DATA_0)
int_b[31:0] <= (WDATA[31:0] & wmask) | (int_b[31:0] & ~wmask);
end
end
// int_accum
always @(posedge ACLK) begin
if (ARESET)
int_accum <= 0;
else if (ACLK_EN) begin
if (accum_ap_vld)
int_accum <= accum;
end
end
// int_accum_ap_vld
always @(posedge ACLK) begin
if (ARESET)
int_accum_ap_vld <= 1'b0;
else if (ACLK_EN) begin
if (accum_ap_vld)
int_accum_ap_vld <= 1'b1;
else if (ar_hs && raddr == ADDR_ACCUM_CTRL)
int_accum_ap_vld <= 1'b0; // clear on read
end
end
// int_accum_clr[0:0]
always @(posedge ACLK) begin
if (ARESET)
int_accum_clr[0:0] <= 0;
else if (ACLK_EN) begin
if (w_hs && waddr == ADDR_ACCUM_CLR_DATA_0)
int_accum_clr[0:0] <= (WDATA[31:0] & wmask) | (int_accum_clr[0:0] & ~wmask);
end
end
//------------------------Memory logic-------------------
endmodule
|
/*
* Milkymist VJ SoC
* Copyright (C) 2007, 2008, 2009 Sebastien Bourdeauducq
* adjusted to FML 8x16 by Zeus Gomez Marmolejo <[email protected]>
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module hpdmc_mgmt #(
parameter sdram_depth = 26,
parameter sdram_columndepth = 9,
parameter sdram_addrdepth = sdram_depth-1-1-(sdram_columndepth+2)+1
) (
input sys_clk,
input sdram_rst,
input [2:0] tim_rp,
input [2:0] tim_rcd,
input [10:0] tim_refi,
input [3:0] tim_rfc,
input stb,
input we,
input [sdram_depth-1-1:0] address, /* in 16-bit words */
output reg ack,
output reg read,
output reg write,
output [3:0] concerned_bank,
input read_safe,
input write_safe,
input [3:0] precharge_safe,
output sdram_cs_n,
output sdram_we_n,
output sdram_cas_n,
output sdram_ras_n,
output [sdram_addrdepth-1:0] sdram_adr,
output [1:0] sdram_ba
);
/*
* Address Mapping :
* | ROW ADDRESS | BANK NUMBER | COL ADDRESS | for 16-bit words
* |depth-1 coldepth+2|coldepth+1 coldepth|coldepth-1 0|
* (depth for 16-bit words, which is sdram_depth-1)
*/
localparam rowdepth = sdram_depth-1-1-(sdram_columndepth+2)+1;
localparam sdram_addrdepth_o1024 = sdram_addrdepth-11;
wire [sdram_depth-1-1:0] address16 = address;
wire [sdram_columndepth-1:0] col_address = address16[sdram_columndepth-1:0];
wire [1:0] bank_address = address16[sdram_columndepth+1:sdram_columndepth];
wire [rowdepth-1:0] row_address = address16[sdram_depth-1-1:sdram_columndepth+2];
reg [3:0] bank_address_onehot;
always @(*) begin
case(bank_address)
2'b00: bank_address_onehot <= 4'b0001;
2'b01: bank_address_onehot <= 4'b0010;
2'b10: bank_address_onehot <= 4'b0100;
2'b11: bank_address_onehot <= 4'b1000;
endcase
end
/* Track open rows */
reg [3:0] has_openrow;
reg [rowdepth-1:0] openrows[0:3];
reg [3:0] track_close;
reg [3:0] track_open;
always @(posedge sys_clk) begin
if(sdram_rst) begin
has_openrow <= 4'h0;
end else begin
has_openrow <= (has_openrow | track_open) & ~track_close;
if(track_open[0]) openrows[0] <= row_address;
if(track_open[1]) openrows[1] <= row_address;
if(track_open[2]) openrows[2] <= row_address;
if(track_open[3]) openrows[3] <= row_address;
end
end
/* Bank precharge safety */
assign concerned_bank = bank_address_onehot;
wire current_precharge_safe =
(precharge_safe[0] | ~bank_address_onehot[0])
&(precharge_safe[1] | ~bank_address_onehot[1])
&(precharge_safe[2] | ~bank_address_onehot[2])
&(precharge_safe[3] | ~bank_address_onehot[3]);
/* Check for page hits */
wire bank_open = has_openrow[bank_address];
wire page_hit = bank_open & (openrows[bank_address] == row_address);
/* Address drivers */
reg sdram_adr_loadrow;
reg sdram_adr_loadcol;
reg sdram_adr_loadA10;
assign sdram_adr =
({sdram_addrdepth{sdram_adr_loadrow}} & row_address)
|({sdram_addrdepth{sdram_adr_loadcol}} & col_address)
|({sdram_addrdepth{sdram_adr_loadA10}}
& { {sdram_addrdepth_o1024{1'b0}} , 11'd1024});
assign sdram_ba = bank_address;
/* Command drivers */
reg sdram_cs;
reg sdram_we;
reg sdram_cas;
reg sdram_ras;
assign sdram_cs_n = ~sdram_cs;
assign sdram_we_n = ~sdram_we;
assign sdram_cas_n = ~sdram_cas;
assign sdram_ras_n = ~sdram_ras;
/* Timing counters */
/* The number of clocks we must wait following a PRECHARGE command (usually tRP). */
reg [2:0] precharge_counter;
reg reload_precharge_counter;
wire precharge_done = (precharge_counter == 3'd0);
always @(posedge sys_clk) begin
if(reload_precharge_counter)
precharge_counter <= tim_rp;
else if(~precharge_done)
precharge_counter <= precharge_counter - 3'd1;
end
/* The number of clocks we must wait following an ACTIVATE command (usually tRCD). */
reg [2:0] activate_counter;
reg reload_activate_counter;
wire activate_done = (activate_counter == 3'd0);
always @(posedge sys_clk) begin
if(reload_activate_counter)
activate_counter <= tim_rcd;
else if(~activate_done)
activate_counter <= activate_counter - 3'd1;
end
/* The number of clocks we have left before we must refresh one row in the SDRAM array (usually tREFI). */
reg [10:0] refresh_counter;
reg reload_refresh_counter;
wire must_refresh = refresh_counter == 11'd0;
always @(posedge sys_clk) begin
if(sdram_rst)
refresh_counter <= 11'd0;
else begin
if(reload_refresh_counter)
refresh_counter <= tim_refi;
else if(~must_refresh)
refresh_counter <= refresh_counter - 11'd1;
end
end
/* The number of clocks we must wait following an AUTO REFRESH command (usually tRFC). */
reg [3:0] autorefresh_counter;
reg reload_autorefresh_counter;
wire autorefresh_done = (autorefresh_counter == 4'd0);
always @(posedge sys_clk) begin
if(reload_autorefresh_counter)
autorefresh_counter <= tim_rfc;
else if(~autorefresh_done)
autorefresh_counter <= autorefresh_counter - 4'd1;
end
/* FSM that pushes commands into the SDRAM */
reg [3:0] state;
reg [3:0] next_state;
localparam [3:0]
IDLE = 4'd0,
ACTIVATE = 4'd1,
READ = 4'd2,
WRITE = 4'd3,
PRECHARGEALL = 4'd4,
AUTOREFRESH = 4'd5,
AUTOREFRESH_WAIT = 4'd6;
always @(posedge sys_clk) begin
if(sdram_rst)
state <= IDLE;
else begin
//$display("state: %d -> %d", state, next_state);
state <= next_state;
end
end
always @(*) begin
next_state = state;
reload_precharge_counter = 1'b0;
reload_activate_counter = 1'b0;
reload_refresh_counter = 1'b0;
reload_autorefresh_counter = 1'b0;
sdram_cs = 1'b0;
sdram_we = 1'b0;
sdram_cas = 1'b0;
sdram_ras = 1'b0;
sdram_adr_loadrow = 1'b0;
sdram_adr_loadcol = 1'b0;
sdram_adr_loadA10 = 1'b0;
track_close = 4'b0000;
track_open = 4'b0000;
read = 1'b0;
write = 1'b0;
ack = 1'b0;
case(state)
IDLE: begin
if(must_refresh)
next_state = PRECHARGEALL;
else begin
if(stb) begin
if(page_hit) begin
if(we) begin
if(write_safe) begin
/* Write */
sdram_cs = 1'b1;
sdram_ras = 1'b0;
sdram_cas = 1'b1;
sdram_we = 1'b1;
sdram_adr_loadcol = 1'b1;
write = 1'b1;
ack = 1'b1;
end
end else begin
if(read_safe) begin
/* Read */
sdram_cs = 1'b1;
sdram_ras = 1'b0;
sdram_cas = 1'b1;
sdram_we = 1'b0;
sdram_adr_loadcol = 1'b1;
read = 1'b1;
ack = 1'b1;
end
end
end else begin
if(bank_open) begin
if(current_precharge_safe) begin
/* Precharge Bank */
sdram_cs = 1'b1;
sdram_ras = 1'b1;
sdram_cas = 1'b0;
sdram_we = 1'b1;
track_close = bank_address_onehot;
reload_precharge_counter = 1'b1;
next_state = ACTIVATE;
end
end else begin
/* Activate */
sdram_cs = 1'b1;
sdram_ras = 1'b1;
sdram_cas = 1'b0;
sdram_we = 1'b0;
sdram_adr_loadrow = 1'b1;
track_open = bank_address_onehot;
reload_activate_counter = 1'b1;
if(we)
next_state = WRITE;
else
next_state = READ;
end
end
end
end
end
ACTIVATE: begin
if(precharge_done) begin
sdram_cs = 1'b1;
sdram_ras = 1'b1;
sdram_cas = 1'b0;
sdram_we = 1'b0;
sdram_adr_loadrow = 1'b1;
track_open = bank_address_onehot;
reload_activate_counter = 1'b1;
if(we)
next_state = WRITE;
else
next_state = READ;
end
end
READ: begin
if(activate_done) begin
if(read_safe) begin
sdram_cs = 1'b1;
sdram_ras = 1'b0;
sdram_cas = 1'b1;
sdram_we = 1'b0;
sdram_adr_loadcol = 1'b1;
read = 1'b1;
ack = 1'b1;
next_state = IDLE;
end
end
end
WRITE: begin
if(activate_done) begin
if(write_safe) begin
sdram_cs = 1'b1;
sdram_ras = 1'b0;
sdram_cas = 1'b1;
sdram_we = 1'b1;
sdram_adr_loadcol = 1'b1;
write = 1'b1;
ack = 1'b1;
next_state = IDLE;
end
end
end
PRECHARGEALL: begin
if(precharge_safe == 4'b1111) begin
sdram_cs = 1'b1;
sdram_ras = 1'b1;
sdram_cas = 1'b0;
sdram_we = 1'b1;
sdram_adr_loadA10 = 1'b1;
reload_precharge_counter = 1'b1;
track_close = 4'b1111;
next_state = AUTOREFRESH;
end
end
AUTOREFRESH: begin
if(precharge_done) begin
sdram_cs = 1'b1;
sdram_ras = 1'b1;
sdram_cas = 1'b1;
sdram_we = 1'b0;
reload_refresh_counter = 1'b1;
reload_autorefresh_counter = 1'b1;
next_state = AUTOREFRESH_WAIT;
end
end
AUTOREFRESH_WAIT: begin
if(autorefresh_done)
next_state = IDLE;
end
endcase
end
endmodule
|
(* -*- coding: utf-8 -*- *)
(************************************************************************)
(* v * The Coq Proof Assistant / The Coq Development Team *)
(* <O___,, * INRIA - CNRS - LIX - LRI - PPS - Copyright 1999-2010 *)
(* \VV/ **************************************************************)
(* // * This file is distributed under the terms of the *)
(* * GNU Lesser General Public License Version 2.1 *)
(************************************************************************)
(** * Typeclass-based morphism definition and standard, minimal instances
Author: Matthieu Sozeau
Institution: LRI, CNRS UMR 8623 - University Paris Sud
*)
Require Import Coq.Program.Basics.
Require Import Coq.Program.Tactics.
Require Import Coq.Relations.Relation_Definitions.
Require Export Coq.Classes.RelationClasses.
Generalizable All Variables.
Local Obligation Tactic := simpl_relation.
Local Notation "'λ' x .. y , t" := (fun x => .. (fun y => t) ..)
(at level 200, x binder, y binder, right associativity).
Local Notation "'Π' x .. y , P" := (forall x, .. (forall y, P) ..)
(at level 200, x binder, y binder, right associativity) : type_scope.
(** * Morphisms.
We now turn to the definition of [Proper] and declare standard instances.
These will be used by the [setoid_rewrite] tactic later. *)
(** A morphism for a relation [R] is a proper element of the relation.
The relation [R] will be instantiated by [respectful] and [A] by an arrow
type for usual morphisms. *)
Class Proper {A} (R : relation A) (m : A) : Prop :=
proper_prf : R m m.
(** Respectful morphisms. *)
(** The fully dependent version, not used yet. *)
Definition respectful_hetero
(A B : Type)
(C : A -> Type) (D : B -> Type)
(R : A -> B -> Prop)
(R' : forall (x : A) (y : B), C x -> D y -> Prop) :
(forall x : A, C x) -> (forall x : B, D x) -> Prop :=
fun f g => forall x y, R x y -> R' x y (f x) (g y).
(** The non-dependent version is an instance where we forget dependencies. *)
Definition respectful {A B : Type}
(R : relation A) (R' : relation B) : relation (A -> B) :=
Eval compute in @respectful_hetero A A (fun _ => B) (fun _ => B) R (fun _ _ => R').
(** Notations reminiscent of the old syntax for declaring morphisms. *)
Delimit Scope signature_scope with signature.
Arguments Scope Proper [type_scope signature_scope].
Arguments Scope respectful [type_scope type_scope signature_scope signature_scope].
Module ProperNotations.
Notation " R ++> R' " := (@respectful _ _ (R%signature) (R'%signature))
(right associativity, at level 55) : signature_scope.
Notation " R ==> R' " := (@respectful _ _ (R%signature) (R'%signature))
(right associativity, at level 55) : signature_scope.
Notation " R --> R' " := (@respectful _ _ (inverse (R%signature)) (R'%signature))
(right associativity, at level 55) : signature_scope.
End ProperNotations.
Export ProperNotations.
Open Local Scope signature_scope.
(** [solve_proper] try to solve the goal [Proper (?==> ... ==>?) f]
by repeated introductions and setoid rewrites. It should work
fine when [f] is a combination of already known morphisms and
quantifiers. *)
Ltac solve_respectful t :=
match goal with
| |- respectful _ _ _ _ =>
let H := fresh "H" in
intros ? ? H; solve_respectful ltac:(setoid_rewrite H; t)
| _ => t; reflexivity
end.
Ltac solve_proper := unfold Proper; solve_respectful ltac:(idtac).
(** [f_equiv] is a clone of [f_equal] that handles setoid equivalences.
For example, if we know that [f] is a morphism for [E1==>E2==>E],
then the goal [E (f x y) (f x' y')] will be transformed by [f_equiv]
into the subgoals [E1 x x'] and [E2 y y'].
*)
Ltac f_equiv :=
match goal with
| |- ?R (?f ?x) (?f' _) =>
let T := type of x in
let Rx := fresh "R" in
evar (Rx : relation T);
let H := fresh in
assert (H : (Rx==>R)%signature f f');
unfold Rx in *; clear Rx; [ f_equiv | apply H; clear H; try reflexivity ]
| |- ?R ?f ?f' =>
try reflexivity;
change (Proper R f); eauto with typeclass_instances; fail
| _ => idtac
end.
(** [forall_def] reifies the dependent product as a definition. *)
Definition forall_def {A : Type} (B : A -> Type) : Type := forall x : A, B x.
(** Dependent pointwise lifting of a relation on the range. *)
Definition forall_relation {A : Type} {B : A -> Type} (sig : Π a : A, relation (B a)) : relation (Π x : A, B x) :=
λ f g, Π a : A, sig a (f a) (g a).
Arguments Scope forall_relation [type_scope type_scope signature_scope].
(** Non-dependent pointwise lifting *)
Definition pointwise_relation (A : Type) {B : Type} (R : relation B) : relation (A -> B) :=
Eval compute in forall_relation (B:=λ _, B) (λ _, R).
Lemma pointwise_pointwise A B (R : relation B) :
relation_equivalence (pointwise_relation A R) (@eq A ==> R).
Proof. intros. split. simpl_relation. firstorder. Qed.
(** We can build a PER on the Coq function space if we have PERs on the domain and
codomain. *)
Hint Unfold Reflexive : core.
Hint Unfold Symmetric : core.
Hint Unfold Transitive : core.
Typeclasses Opaque respectful pointwise_relation forall_relation.
Program Instance respectful_per `(PER A R, PER B R') : PER (R ==> R').
Next Obligation.
Proof with auto.
assert(R x0 x0).
transitivity y0... symmetry...
transitivity (y x0)...
Qed.
(** Subrelations induce a morphism on the identity. *)
Instance subrelation_id_proper `(subrelation A R₁ R₂) : Proper (R₁ ==> R₂) id.
Proof. firstorder. Qed.
(** The subrelation property goes through products as usual. *)
Lemma subrelation_respectful `(subl : subrelation A R₂ R₁, subr : subrelation B S₁ S₂) :
subrelation (R₁ ==> S₁) (R₂ ==> S₂).
Proof. simpl_relation. apply subr. apply H. apply subl. apply H0. Qed.
(** And of course it is reflexive. *)
Lemma subrelation_refl A R : @subrelation A R R.
Proof. simpl_relation. Qed.
Ltac subrelation_tac T U :=
(is_ground T ; is_ground U ; class_apply @subrelation_refl) ||
class_apply @subrelation_respectful || class_apply @subrelation_refl.
Hint Extern 3 (@subrelation _ ?T ?U) => subrelation_tac T U : typeclass_instances.
(** [Proper] is itself a covariant morphism for [subrelation]. *)
Lemma subrelation_proper `(mor : Proper A R₁ m, unc : Unconvertible (relation A) R₁ R₂,
sub : subrelation A R₁ R₂) : Proper R₂ m.
Proof.
intros. apply sub. apply mor.
Qed.
CoInductive apply_subrelation : Prop := do_subrelation.
Ltac proper_subrelation :=
match goal with
[ H : apply_subrelation |- _ ] => clear H ; class_apply @subrelation_proper
end.
Hint Extern 5 (@Proper _ ?H _) => proper_subrelation : typeclass_instances.
Instance proper_subrelation_proper :
Proper (subrelation ++> eq ==> impl) (@Proper A).
Proof. reduce. subst. firstorder. Qed.
(** Essential subrelation instances for [iff], [impl] and [pointwise_relation]. *)
Instance iff_impl_subrelation : subrelation iff impl | 2.
Proof. firstorder. Qed.
Instance iff_inverse_impl_subrelation : subrelation iff (inverse impl) | 2.
Proof. firstorder. Qed.
Instance pointwise_subrelation {A} `(sub : subrelation B R R') :
subrelation (pointwise_relation A R) (pointwise_relation A R') | 4.
Proof. reduce. unfold pointwise_relation in *. apply sub. apply H. Qed.
(** For dependent function types. *)
Lemma forall_subrelation A (B : A -> Type) (R S : forall x : A, relation (B x)) :
(forall a, subrelation (R a) (S a)) -> subrelation (forall_relation R) (forall_relation S).
Proof. reduce. apply H. apply H0. Qed.
(** We use an extern hint to help unification. *)
Hint Extern 4 (subrelation (@forall_relation ?A ?B ?R) (@forall_relation _ _ ?S)) =>
apply (@forall_subrelation A B R S) ; intro : typeclass_instances.
(** Any symmetric relation is equal to its inverse. *)
Lemma subrelation_symmetric A R `(Symmetric A R) : subrelation (inverse R) R.
Proof. reduce. red in H0. symmetry. assumption. Qed.
Hint Extern 4 (subrelation (inverse _) _) =>
class_apply @subrelation_symmetric : typeclass_instances.
(** The complement of a relation conserves its proper elements. *)
Program Definition complement_proper
`(mR : Proper (A -> A -> Prop) (RA ==> RA ==> iff) R) :
Proper (RA ==> RA ==> iff) (complement R) := _.
Next Obligation.
Proof.
unfold complement.
pose (mR x y H x0 y0 H0).
intuition.
Qed.
Hint Extern 1 (Proper (_ ==> _ ==> iff) (complement _)) =>
apply @complement_proper : typeclass_instances.
(** The [inverse] too, actually the [flip] instance is a bit more general. *)
Program Definition flip_proper
`(mor : Proper (A -> B -> C) (RA ==> RB ==> RC) f) :
Proper (RB ==> RA ==> RC) (flip f) := _.
Next Obligation.
Proof.
apply mor ; auto.
Qed.
Hint Extern 1 (Proper (_ ==> _ ==> _) (flip _)) =>
apply @flip_proper : typeclass_instances.
(** Every Transitive relation gives rise to a binary morphism on [impl],
contravariant in the first argument, covariant in the second. *)
Program Instance trans_contra_co_morphism
`(Transitive A R) : Proper (R --> R ++> impl) R.
Next Obligation.
Proof with auto.
transitivity x...
transitivity x0...
Qed.
(** Proper declarations for partial applications. *)
Program Instance trans_contra_inv_impl_morphism
`(Transitive A R) : Proper (R --> inverse impl) (R x) | 3.
Next Obligation.
Proof with auto.
transitivity y...
Qed.
Program Instance trans_co_impl_morphism
`(Transitive A R) : Proper (R ++> impl) (R x) | 3.
Next Obligation.
Proof with auto.
transitivity x0...
Qed.
Program Instance trans_sym_co_inv_impl_morphism
`(PER A R) : Proper (R ++> inverse impl) (R x) | 3.
Next Obligation.
Proof with auto.
transitivity y... symmetry...
Qed.
Program Instance trans_sym_contra_impl_morphism
`(PER A R) : Proper (R --> impl) (R x) | 3.
Next Obligation.
Proof with auto.
transitivity x0... symmetry...
Qed.
Program Instance per_partial_app_morphism
`(PER A R) : Proper (R ==> iff) (R x) | 2.
Next Obligation.
Proof with auto.
split. intros ; transitivity x0...
intros.
transitivity y...
symmetry...
Qed.
(** Every Transitive relation induces a morphism by "pushing" an [R x y] on the left of an [R x z] proof
to get an [R y z] goal. *)
Program Instance trans_co_eq_inv_impl_morphism
`(Transitive A R) : Proper (R ==> (@eq A) ==> inverse impl) R | 2.
Next Obligation.
Proof with auto.
transitivity y...
Qed.
(** Every Symmetric and Transitive relation gives rise to an equivariant morphism. *)
Program Instance PER_morphism `(PER A R) : Proper (R ==> R ==> iff) R | 1.
Next Obligation.
Proof with auto.
split ; intros.
transitivity x0... transitivity x... symmetry...
transitivity y... transitivity y0... symmetry...
Qed.
Lemma symmetric_equiv_inverse `(Symmetric A R) : relation_equivalence R (flip R).
Proof. firstorder. Qed.
Program Instance compose_proper A B C R₀ R₁ R₂ :
Proper ((R₁ ==> R₂) ==> (R₀ ==> R₁) ==> (R₀ ==> R₂)) (@compose A B C).
Next Obligation.
Proof.
simpl_relation.
unfold compose. apply H. apply H0. apply H1.
Qed.
(** Coq functions are morphisms for Leibniz equality,
applied only if really needed. *)
Instance reflexive_eq_dom_reflexive (A : Type) `(Reflexive B R') :
Reflexive (@Logic.eq A ==> R').
Proof. simpl_relation. Qed.
(** [respectful] is a morphism for relation equivalence. *)
Instance respectful_morphism :
Proper (relation_equivalence ++> relation_equivalence ++> relation_equivalence) (@respectful A B).
Proof.
reduce.
unfold respectful, relation_equivalence, predicate_equivalence in * ; simpl in *.
split ; intros.
rewrite <- H0.
apply H1.
rewrite H.
assumption.
rewrite H0.
apply H1.
rewrite <- H.
assumption.
Qed.
(** Every element in the carrier of a reflexive relation is a morphism for this relation.
We use a proxy class for this case which is used internally to discharge reflexivity constraints.
The [Reflexive] instance will almost always be used, but it won't apply in general to any kind of
[Proper (A -> B) _ _] goal, making proof-search much slower. A cleaner solution would be to be able
to set different priorities in different hint bases and select a particular hint database for
resolution of a type class constraint.*)
Class ProperProxy {A} (R : relation A) (m : A) : Prop :=
proper_proxy : R m m.
Lemma eq_proper_proxy A (x : A) : ProperProxy (@eq A) x.
Proof. firstorder. Qed.
Lemma reflexive_proper_proxy `(Reflexive A R) (x : A) : ProperProxy R x.
Proof. firstorder. Qed.
Lemma proper_proper_proxy `(Proper A R x) : ProperProxy R x.
Proof. firstorder. Qed.
Hint Extern 1 (ProperProxy _ _) =>
class_apply @eq_proper_proxy || class_apply @reflexive_proper_proxy : typeclass_instances.
Hint Extern 2 (ProperProxy ?R _) => not_evar R; class_apply @proper_proper_proxy : typeclass_instances.
(** [R] is Reflexive, hence we can build the needed proof. *)
Lemma Reflexive_partial_app_morphism `(Proper (A -> B) (R ==> R') m, ProperProxy A R x) :
Proper R' (m x).
Proof. simpl_relation. Qed.
Class Params {A : Type} (of : A) (arity : nat).
Class PartialApplication.
CoInductive normalization_done : Prop := did_normalization.
Ltac partial_application_tactic :=
let rec do_partial_apps H m :=
match m with
| ?m' ?x => class_apply @Reflexive_partial_app_morphism ; [do_partial_apps H m'|clear H]
| _ => idtac
end
in
let rec do_partial H ar m :=
match ar with
| 0 => do_partial_apps H m
| S ?n' =>
match m with
?m' ?x => do_partial H n' m'
end
end
in
let on_morphism m :=
let m' := fresh in head_of_constr m' m ;
let n := fresh in evar (n:nat) ;
let v := eval compute in n in clear n ;
let H := fresh in
assert(H:Params m' v) by typeclasses eauto ;
let v' := eval compute in v in subst m';
do_partial H v' m
in
match goal with
| [ _ : normalization_done |- _ ] => fail 1
| [ _ : @Params _ _ _ |- _ ] => fail 1
| [ |- @Proper ?T _ (?m ?x) ] =>
match goal with
| [ _ : PartialApplication |- _ ] =>
class_apply @Reflexive_partial_app_morphism
| _ =>
on_morphism (m x) ||
(class_apply @Reflexive_partial_app_morphism ;
[ pose Build_PartialApplication | idtac ])
end
end.
Hint Extern 4 (@Proper _ _ _) => partial_application_tactic : typeclass_instances.
Lemma inverse_respectful : forall (A : Type) (R : relation A) (B : Type) (R' : relation B),
relation_equivalence (inverse (R ==> R')) (inverse R ==> inverse R').
Proof.
intros.
unfold flip, respectful.
split ; intros ; intuition.
Qed.
(** Special-purpose class to do normalization of signatures w.r.t. inverse. *)
Class Normalizes (A : Type) (m : relation A) (m' : relation A) : Prop :=
normalizes : relation_equivalence m m'.
(** Current strategy: add [inverse] everywhere and reduce using [subrelation]
afterwards. *)
Lemma inverse_atom A R : Normalizes A R (inverse (inverse R)).
Proof.
firstorder.
Qed.
Lemma inverse_arrow `(NA : Normalizes A R (inverse R'''), NB : Normalizes B R' (inverse R'')) :
Normalizes (A -> B) (R ==> R') (inverse (R''' ==> R'')%signature).
Proof. unfold Normalizes in *. intros.
rewrite NA, NB. firstorder.
Qed.
Ltac inverse :=
match goal with
| [ |- Normalizes _ (respectful _ _) _ ] => class_apply @inverse_arrow
| _ => class_apply @inverse_atom
end.
Hint Extern 1 (Normalizes _ _ _) => inverse : typeclass_instances.
(** Treating inverse: can't make them direct instances as we
need at least a [flip] present in the goal. *)
Lemma inverse1 `(subrelation A R' R) : subrelation (inverse (inverse R')) R.
Proof. firstorder. Qed.
Lemma inverse2 `(subrelation A R R') : subrelation R (inverse (inverse R')).
Proof. firstorder. Qed.
Hint Extern 1 (subrelation (flip _) _) => class_apply @inverse1 : typeclass_instances.
Hint Extern 1 (subrelation _ (flip _)) => class_apply @inverse2 : typeclass_instances.
(** That's if and only if *)
Lemma eq_subrelation `(Reflexive A R) : subrelation (@eq A) R.
Proof. simpl_relation. Qed.
(* Hint Extern 3 (subrelation eq ?R) => not_evar R ; class_apply eq_subrelation : typeclass_instances. *)
(** Once we have normalized, we will apply this instance to simplify the problem. *)
Definition proper_inverse_proper `(mor : Proper A R m) : Proper (inverse R) m := mor.
Hint Extern 2 (@Proper _ (flip _) _) => class_apply @proper_inverse_proper : typeclass_instances.
(** Bootstrap !!! *)
Instance proper_proper : Proper (relation_equivalence ==> eq ==> iff) (@Proper A).
Proof.
simpl_relation.
reduce in H.
split ; red ; intros.
setoid_rewrite <- H.
apply H0.
setoid_rewrite H.
apply H0.
Qed.
Lemma proper_normalizes_proper `(Normalizes A R0 R1, Proper A R1 m) : Proper R0 m.
Proof.
red in H, H0.
setoid_rewrite H.
assumption.
Qed.
Ltac proper_normalization :=
match goal with
| [ _ : normalization_done |- _ ] => fail 1
| [ _ : apply_subrelation |- @Proper _ ?R _ ] => let H := fresh "H" in
set(H:=did_normalization) ; class_apply @proper_normalizes_proper
end.
Hint Extern 6 (@Proper _ _ _) => proper_normalization : typeclass_instances.
(** Every reflexive relation gives rise to a morphism, only for immediately solving goals without variables. *)
Lemma reflexive_proper `{Reflexive A R} (x : A)
: Proper R x.
Proof. firstorder. Qed.
Lemma proper_eq A (x : A) : Proper (@eq A) x.
Proof. intros. apply reflexive_proper. Qed.
Ltac proper_reflexive :=
match goal with
| [ _ : normalization_done |- _ ] => fail 1
| _ => class_apply proper_eq || class_apply @reflexive_proper
end.
Hint Extern 7 (@Proper _ _ _) => proper_reflexive : typeclass_instances.
(** When the relation on the domain is symmetric, we can
inverse the relation on the codomain. Same for binary functions. *)
Lemma proper_sym_flip :
forall `(Symmetric A R1)`(Proper (A->B) (R1==>R2) f),
Proper (R1==>inverse R2) f.
Proof.
intros A R1 Sym B R2 f Hf.
intros x x' Hxx'. apply Hf, Sym, Hxx'.
Qed.
Lemma proper_sym_flip_2 :
forall `(Symmetric A R1)`(Symmetric B R2)`(Proper (A->B->C) (R1==>R2==>R3) f),
Proper (R1==>R2==>inverse R3) f.
Proof.
intros A R1 Sym1 B R2 Sym2 C R3 f Hf.
intros x x' Hxx' y y' Hyy'. apply Hf; auto.
Qed.
(** When the relation on the domain is symmetric, a predicate is
compatible with [iff] as soon as it is compatible with [impl].
Same with a binary relation. *)
Lemma proper_sym_impl_iff : forall `(Symmetric A R)`(Proper _ (R==>impl) f),
Proper (R==>iff) f.
Proof.
intros A R Sym f Hf x x' Hxx'. repeat red in Hf. split; eauto.
Qed.
Lemma proper_sym_impl_iff_2 :
forall `(Symmetric A R)`(Symmetric B R')`(Proper _ (R==>R'==>impl) f),
Proper (R==>R'==>iff) f.
Proof.
intros A R Sym B R' Sym' f Hf x x' Hxx' y y' Hyy'.
repeat red in Hf. split; eauto.
Qed.
(** A [PartialOrder] is compatible with its underlying equivalence. *)
Instance PartialOrder_proper `(PartialOrder A eqA R) :
Proper (eqA==>eqA==>iff) R.
Proof.
intros.
apply proper_sym_impl_iff_2; auto with *.
intros x x' Hx y y' Hy Hr.
transitivity x.
generalize (partial_order_equivalence x x'); compute; intuition.
transitivity y; auto.
generalize (partial_order_equivalence y y'); compute; intuition.
Qed.
(** From a [PartialOrder] to the corresponding [StrictOrder]:
[lt = le /\ ~eq].
If the order is total, we could also say [gt = ~le]. *)
Lemma PartialOrder_StrictOrder `(PartialOrder A eqA R) :
StrictOrder (relation_conjunction R (complement eqA)).
Proof.
split; compute.
intros x (_,Hx). apply Hx, Equivalence_Reflexive.
intros x y z (Hxy,Hxy') (Hyz,Hyz'). split.
apply PreOrder_Transitive with y; assumption.
intro Hxz.
apply Hxy'.
apply partial_order_antisym; auto.
rewrite Hxz; auto.
Qed.
Hint Extern 4 (StrictOrder (relation_conjunction _ _)) =>
class_apply PartialOrder_StrictOrder : typeclass_instances.
(** From a [StrictOrder] to the corresponding [PartialOrder]:
[le = lt \/ eq].
If the order is total, we could also say [ge = ~lt]. *)
Lemma StrictOrder_PreOrder
`(Equivalence A eqA, StrictOrder A R, Proper _ (eqA==>eqA==>iff) R) :
PreOrder (relation_disjunction R eqA).
Proof.
split.
intros x. right. reflexivity.
intros x y z [Hxy|Hxy] [Hyz|Hyz].
left. transitivity y; auto.
left. rewrite <- Hyz; auto.
left. rewrite Hxy; auto.
right. transitivity y; auto.
Qed.
Hint Extern 4 (PreOrder (relation_disjunction _ _)) =>
class_apply StrictOrder_PreOrder : typeclass_instances.
Lemma StrictOrder_PartialOrder
`(Equivalence A eqA, StrictOrder A R, Proper _ (eqA==>eqA==>iff) R) :
PartialOrder eqA (relation_disjunction R eqA).
Proof.
intros. intros x y. compute. intuition.
elim (StrictOrder_Irreflexive x).
transitivity y; auto.
Qed.
Hint Extern 4 (PartialOrder _ (relation_disjunction _ _)) =>
class_apply StrictOrder_PartialOrder : typeclass_instances.
|
//
// Generated by Bluespec Compiler, version 2012.09.beta1 (build 29570, 2012-09.11)
//
// On Mon Nov 5 13:20:08 EST 2012
//
//
// Ports:
// Name I/O size props
// RDY_server_request_put O 1 reg
// server_response_get O 40
// RDY_server_response_get O 1 reg
// client_request_get O 40
// RDY_client_request_get O 1 reg
// RDY_client_response_put O 1 reg
// RDY_macAddr O 1 const
// RDY_dstAddr O 1 const
// RDY_dstType O 1 const
// edpRx O 1 reg
// RDY_edpRx O 1 const
// edpTx O 1 reg
// RDY_edpTx O 1 const
// edpTxEOP O 1 reg
// RDY_edpTxEOP O 1 const
// CLK I 1 clock
// RST_N I 1 reset
// server_request_put I 40
// client_response_put I 40
// macAddr_u I 48 reg
// dstAddr_d I 48 reg
// dstType_t I 16 reg
// EN_server_request_put I 1
// EN_client_response_put I 1
// EN_macAddr I 1
// EN_dstAddr I 1
// EN_dstType I 1
// EN_server_response_get I 1
// EN_client_request_get I 1
//
// No combinational paths from inputs to outputs
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
module mkEDDPAdapter(CLK,
RST_N,
server_request_put,
EN_server_request_put,
RDY_server_request_put,
EN_server_response_get,
server_response_get,
RDY_server_response_get,
EN_client_request_get,
client_request_get,
RDY_client_request_get,
client_response_put,
EN_client_response_put,
RDY_client_response_put,
macAddr_u,
EN_macAddr,
RDY_macAddr,
dstAddr_d,
EN_dstAddr,
RDY_dstAddr,
dstType_t,
EN_dstType,
RDY_dstType,
edpRx,
RDY_edpRx,
edpTx,
RDY_edpTx,
edpTxEOP,
RDY_edpTxEOP);
input CLK;
input RST_N;
// action method server_request_put
input [39 : 0] server_request_put;
input EN_server_request_put;
output RDY_server_request_put;
// actionvalue method server_response_get
input EN_server_response_get;
output [39 : 0] server_response_get;
output RDY_server_response_get;
// actionvalue method client_request_get
input EN_client_request_get;
output [39 : 0] client_request_get;
output RDY_client_request_get;
// action method client_response_put
input [39 : 0] client_response_put;
input EN_client_response_put;
output RDY_client_response_put;
// action method macAddr
input [47 : 0] macAddr_u;
input EN_macAddr;
output RDY_macAddr;
// action method dstAddr
input [47 : 0] dstAddr_d;
input EN_dstAddr;
output RDY_dstAddr;
// action method dstType
input [15 : 0] dstType_t;
input EN_dstType;
output RDY_dstType;
// value method edpRx
output edpRx;
output RDY_edpRx;
// value method edpTx
output edpTx;
output RDY_edpTx;
// value method edpTxEOP
output edpTxEOP;
output RDY_edpTxEOP;
// signals for module outputs
wire [39 : 0] client_request_get, server_response_get;
wire RDY_client_request_get,
RDY_client_response_put,
RDY_dstAddr,
RDY_dstType,
RDY_edpRx,
RDY_edpTx,
RDY_edpTxEOP,
RDY_macAddr,
RDY_server_request_put,
RDY_server_response_get,
edpRx,
edpTx,
edpTxEOP;
// inlined wires
wire edpEgressEOP_1$wget,
edpEgressEOP_1$whas,
edpEgress_1$wget,
edpEgress_1$whas,
edpFsm_abort$wget,
edpFsm_abort$whas,
edpFsm_start_reg_1_1$wget,
edpFsm_start_reg_1_1$whas,
edpFsm_start_wire$wget,
edpFsm_start_wire$whas,
edpFsm_state_fired_1$wget,
edpFsm_state_fired_1$whas,
edpFsm_state_overlap_pw$whas,
edpFsm_state_set_pw$whas,
edpIngress_1$wget,
edpIngress_1$whas;
// register dEType
reg [15 : 0] dEType;
wire [15 : 0] dEType$D_IN;
wire dEType$EN;
// register dMAddr
reg [47 : 0] dMAddr;
wire [47 : 0] dMAddr$D_IN;
wire dMAddr$EN;
// register dbge0
reg [9 : 0] dbge0;
wire [9 : 0] dbge0$D_IN;
wire dbge0$EN;
// register dbge1
reg [9 : 0] dbge1;
wire [9 : 0] dbge1$D_IN;
wire dbge1$EN;
// register dbge2
reg [9 : 0] dbge2;
wire [9 : 0] dbge2$D_IN;
wire dbge2$EN;
// register dbge3
reg [9 : 0] dbge3;
wire [9 : 0] dbge3$D_IN;
wire dbge3$EN;
// register edpEgress
reg edpEgress;
wire edpEgress$D_IN, edpEgress$EN;
// register edpEgressEOP
reg edpEgressEOP;
wire edpEgressEOP$D_IN, edpEgressEOP$EN;
// register edpFsm_start_reg
reg edpFsm_start_reg;
wire edpFsm_start_reg$D_IN, edpFsm_start_reg$EN;
// register edpFsm_start_reg_1
reg edpFsm_start_reg_1;
wire edpFsm_start_reg_1$D_IN, edpFsm_start_reg_1$EN;
// register edpFsm_state_can_overlap
reg edpFsm_state_can_overlap;
wire edpFsm_state_can_overlap$D_IN, edpFsm_state_can_overlap$EN;
// register edpFsm_state_fired
reg edpFsm_state_fired;
wire edpFsm_state_fired$D_IN, edpFsm_state_fired$EN;
// register edpFsm_state_mkFSMstate
reg [2 : 0] edpFsm_state_mkFSMstate;
reg [2 : 0] edpFsm_state_mkFSMstate$D_IN;
wire edpFsm_state_mkFSMstate$EN;
// register edpIngress
reg edpIngress;
wire edpIngress$D_IN, edpIngress$EN;
// register eeDID
reg [15 : 0] eeDID;
wire [15 : 0] eeDID$D_IN;
wire eeDID$EN;
// register igPtr
reg [3 : 0] igPtr;
wire [3 : 0] igPtr$D_IN;
wire igPtr$EN;
// register txPayload
reg txPayload;
wire txPayload$D_IN, txPayload$EN;
// register uMAddr
reg [47 : 0] uMAddr;
wire [47 : 0] uMAddr$D_IN;
wire uMAddr$EN;
// ports of submodule dpReqF
wire [39 : 0] dpReqF$D_IN, dpReqF$D_OUT;
wire dpReqF$CLR, dpReqF$DEQ, dpReqF$EMPTY_N, dpReqF$ENQ, dpReqF$FULL_N;
// ports of submodule dpRespF
wire [39 : 0] dpRespF$D_IN, dpRespF$D_OUT;
wire dpRespF$CLR, dpRespF$DEQ, dpRespF$EMPTY_N, dpRespF$ENQ, dpRespF$FULL_N;
// ports of submodule edpReqF
wire [39 : 0] edpReqF$D_IN, edpReqF$D_OUT;
wire edpReqF$CLR, edpReqF$DEQ, edpReqF$EMPTY_N, edpReqF$ENQ, edpReqF$FULL_N;
// ports of submodule edpRespF
reg [39 : 0] edpRespF$D_IN;
wire [39 : 0] edpRespF$D_OUT;
wire edpRespF$CLR,
edpRespF$DEQ,
edpRespF$EMPTY_N,
edpRespF$ENQ,
edpRespF$FULL_N;
// rule scheduling signals
wire WILL_FIRE_RL_edpFsm_action_l90c14,
WILL_FIRE_RL_edpFsm_action_l91c14,
WILL_FIRE_RL_edpFsm_action_l92c14,
WILL_FIRE_RL_edpFsm_action_l93c14,
WILL_FIRE_RL_edpFsm_fsm_start,
WILL_FIRE_RL_edpFsm_idle_l89c3,
WILL_FIRE_RL_egress_body;
// inputs to muxes for submodule ports
wire [39 : 0] MUX_edpRespF$enq_1__VAL_1,
MUX_edpRespF$enq_1__VAL_2,
MUX_edpRespF$enq_1__VAL_3,
MUX_edpRespF$enq_1__VAL_4,
MUX_edpRespF$enq_1__VAL_5;
wire MUX_edpFsm_start_reg$write_1__SEL_2, MUX_txPayload$write_1__VAL_2;
// remaining internal signals
reg [1 : 0] CASE_client_response_put_BITS_19_TO_18_3_0_cli_ETC__q19,
CASE_client_response_put_BITS_29_TO_28_3_0_cli_ETC__q18,
CASE_client_response_put_BITS_39_TO_38_3_0_cli_ETC__q17,
CASE_client_response_put_BITS_9_TO_8_3_0_clien_ETC__q20,
CASE_dpReqFD_OUT_BITS_19_TO_18_3_0_dpReqFD_O_ETC__q7,
CASE_dpReqFD_OUT_BITS_29_TO_28_3_0_dpReqFD_O_ETC__q6,
CASE_dpReqFD_OUT_BITS_39_TO_38_3_0_dpReqFD_O_ETC__q5,
CASE_dpReqFD_OUT_BITS_9_TO_8_3_0_dpReqFD_OUT_ETC__q8,
CASE_dpRespFD_OUT_BITS_19_TO_18_3_0_dpRespFD_ETC__q11,
CASE_dpRespFD_OUT_BITS_29_TO_28_3_0_dpRespFD_ETC__q10,
CASE_dpRespFD_OUT_BITS_39_TO_38_3_0_dpRespFD_ETC__q9,
CASE_dpRespFD_OUT_BITS_9_TO_8_3_0_dpRespFD_O_ETC__q12,
CASE_edpReqFD_OUT_BITS_19_TO_18_3_0_edpReqFD_ETC__q15,
CASE_edpReqFD_OUT_BITS_29_TO_28_3_0_edpReqFD_ETC__q14,
CASE_edpReqFD_OUT_BITS_39_TO_38_3_0_edpReqFD_ETC__q13,
CASE_edpReqFD_OUT_BITS_9_TO_8_3_0_edpReqFD_O_ETC__q16,
CASE_edpRespFD_OUT_BITS_19_TO_18_3_0_edpRespF_ETC__q3,
CASE_edpRespFD_OUT_BITS_29_TO_28_3_0_edpRespF_ETC__q2,
CASE_edpRespFD_OUT_BITS_39_TO_38_3_0_edpRespF_ETC__q1,
CASE_edpRespFD_OUT_BITS_9_TO_8_3_0_edpRespFD_ETC__q4,
CASE_server_request_put_BITS_19_TO_18_3_0_serv_ETC__q23,
CASE_server_request_put_BITS_29_TO_28_3_0_serv_ETC__q22,
CASE_server_request_put_BITS_39_TO_38_3_0_serv_ETC__q21,
CASE_server_request_put_BITS_9_TO_8_3_0_server_ETC__q24;
wire [3 : 0] x__h1670;
wire edpFsm_abort_whas__5_AND_edpFsm_abort_wget__6__ETC___d157,
igPtr_1_ULE_3___d12;
// action method server_request_put
assign RDY_server_request_put = edpReqF$FULL_N ;
// actionvalue method server_response_get
assign server_response_get =
{ CASE_edpRespFD_OUT_BITS_39_TO_38_3_0_edpRespF_ETC__q1,
edpRespF$D_OUT[37:30],
CASE_edpRespFD_OUT_BITS_29_TO_28_3_0_edpRespF_ETC__q2,
edpRespF$D_OUT[27:20],
CASE_edpRespFD_OUT_BITS_19_TO_18_3_0_edpRespF_ETC__q3,
edpRespF$D_OUT[17:10],
CASE_edpRespFD_OUT_BITS_9_TO_8_3_0_edpRespFD_ETC__q4,
edpRespF$D_OUT[7:0] } ;
assign RDY_server_response_get = edpRespF$EMPTY_N ;
// actionvalue method client_request_get
assign client_request_get =
{ CASE_dpReqFD_OUT_BITS_39_TO_38_3_0_dpReqFD_O_ETC__q5,
dpReqF$D_OUT[37:30],
CASE_dpReqFD_OUT_BITS_29_TO_28_3_0_dpReqFD_O_ETC__q6,
dpReqF$D_OUT[27:20],
CASE_dpReqFD_OUT_BITS_19_TO_18_3_0_dpReqFD_O_ETC__q7,
dpReqF$D_OUT[17:10],
CASE_dpReqFD_OUT_BITS_9_TO_8_3_0_dpReqFD_OUT_ETC__q8,
dpReqF$D_OUT[7:0] } ;
assign RDY_client_request_get = dpReqF$EMPTY_N ;
// action method client_response_put
assign RDY_client_response_put = dpRespF$FULL_N ;
// action method macAddr
assign RDY_macAddr = 1'd1 ;
// action method dstAddr
assign RDY_dstAddr = 1'd1 ;
// action method dstType
assign RDY_dstType = 1'd1 ;
// value method edpRx
assign edpRx = edpIngress ;
assign RDY_edpRx = 1'd1 ;
// value method edpTx
assign edpTx = edpEgress ;
assign RDY_edpTx = 1'd1 ;
// value method edpTxEOP
assign edpTxEOP = edpEgressEOP ;
assign RDY_edpTxEOP = 1'd1 ;
// submodule dpReqF
FIFO2 #(.width(32'd40), .guarded(32'd1)) dpReqF(.RST(RST_N),
.CLK(CLK),
.D_IN(dpReqF$D_IN),
.ENQ(dpReqF$ENQ),
.DEQ(dpReqF$DEQ),
.CLR(dpReqF$CLR),
.D_OUT(dpReqF$D_OUT),
.FULL_N(dpReqF$FULL_N),
.EMPTY_N(dpReqF$EMPTY_N));
// submodule dpRespF
FIFO2 #(.width(32'd40), .guarded(32'd1)) dpRespF(.RST(RST_N),
.CLK(CLK),
.D_IN(dpRespF$D_IN),
.ENQ(dpRespF$ENQ),
.DEQ(dpRespF$DEQ),
.CLR(dpRespF$CLR),
.D_OUT(dpRespF$D_OUT),
.FULL_N(dpRespF$FULL_N),
.EMPTY_N(dpRespF$EMPTY_N));
// submodule edpReqF
FIFO2 #(.width(32'd40), .guarded(32'd1)) edpReqF(.RST(RST_N),
.CLK(CLK),
.D_IN(edpReqF$D_IN),
.ENQ(edpReqF$ENQ),
.DEQ(edpReqF$DEQ),
.CLR(edpReqF$CLR),
.D_OUT(edpReqF$D_OUT),
.FULL_N(edpReqF$FULL_N),
.EMPTY_N(edpReqF$EMPTY_N));
// submodule edpRespF
FIFO2 #(.width(32'd40), .guarded(32'd1)) edpRespF(.RST(RST_N),
.CLK(CLK),
.D_IN(edpRespF$D_IN),
.ENQ(edpRespF$ENQ),
.DEQ(edpRespF$DEQ),
.CLR(edpRespF$CLR),
.D_OUT(edpRespF$D_OUT),
.FULL_N(edpRespF$FULL_N),
.EMPTY_N(edpRespF$EMPTY_N));
// rule RL_egress_body
assign WILL_FIRE_RL_egress_body =
edpRespF$FULL_N && dpRespF$EMPTY_N && txPayload ;
// rule RL_edpFsm_action_l91c14
assign WILL_FIRE_RL_edpFsm_action_l91c14 =
edpRespF$FULL_N && edpFsm_state_mkFSMstate == 3'd1 &&
!WILL_FIRE_RL_egress_body ;
// rule RL_edpFsm_action_l92c14
assign WILL_FIRE_RL_edpFsm_action_l92c14 =
edpRespF$FULL_N && edpFsm_state_mkFSMstate == 3'd2 &&
!WILL_FIRE_RL_egress_body ;
// rule RL_edpFsm_action_l93c14
assign WILL_FIRE_RL_edpFsm_action_l93c14 =
edpRespF$FULL_N && edpFsm_state_mkFSMstate == 3'd3 &&
!WILL_FIRE_RL_egress_body ;
// rule RL_edpFsm_fsm_start
assign WILL_FIRE_RL_edpFsm_fsm_start =
edpFsm_abort_whas__5_AND_edpFsm_abort_wget__6__ETC___d157 &&
edpFsm_start_reg ;
// rule RL_edpFsm_action_l90c14
assign WILL_FIRE_RL_edpFsm_action_l90c14 =
edpRespF$FULL_N && edpFsm_start_reg_1_1$whas &&
(edpFsm_state_mkFSMstate == 3'd0 ||
edpFsm_state_mkFSMstate == 3'd5) &&
!WILL_FIRE_RL_egress_body ;
// rule RL_edpFsm_idle_l89c3
assign WILL_FIRE_RL_edpFsm_idle_l89c3 =
!edpFsm_start_reg_1_1$whas && edpFsm_state_mkFSMstate == 3'd5 ;
// inputs to muxes for submodule ports
assign MUX_edpFsm_start_reg$write_1__SEL_2 =
edpFsm_abort_whas__5_AND_edpFsm_abort_wget__6__ETC___d157 &&
!edpFsm_start_reg &&
dpRespF$EMPTY_N &&
!txPayload ;
assign MUX_edpRespF$enq_1__VAL_1 =
{ 2'd0,
dMAddr[23:16],
2'd0,
dMAddr[31:24],
2'd0,
dMAddr[39:32],
2'd0,
dMAddr[47:40] } ;
assign MUX_edpRespF$enq_1__VAL_2 =
{ 2'd0,
uMAddr[39:32],
2'd0,
uMAddr[47:40],
2'd0,
dMAddr[7:0],
2'd0,
dMAddr[15:8] } ;
assign MUX_edpRespF$enq_1__VAL_3 =
{ 2'd0,
uMAddr[7:0],
2'd0,
uMAddr[15:8],
2'd0,
uMAddr[23:16],
2'd0,
uMAddr[31:24] } ;
assign MUX_edpRespF$enq_1__VAL_4 =
{ 2'd0,
eeDID[7:0],
2'd0,
eeDID[15:8],
2'd0,
dEType[7:0],
2'd0,
dEType[15:8] } ;
assign MUX_edpRespF$enq_1__VAL_5 =
{ CASE_dpRespFD_OUT_BITS_39_TO_38_3_0_dpRespFD_ETC__q9,
dpRespF$D_OUT[37:30],
CASE_dpRespFD_OUT_BITS_29_TO_28_3_0_dpRespFD_ETC__q10,
dpRespF$D_OUT[27:20],
CASE_dpRespFD_OUT_BITS_19_TO_18_3_0_dpRespFD_ETC__q11,
dpRespF$D_OUT[17:10],
CASE_dpRespFD_OUT_BITS_9_TO_8_3_0_dpRespFD_O_ETC__q12,
dpRespF$D_OUT[7:0] } ;
assign MUX_txPayload$write_1__VAL_2 =
dpRespF$D_OUT[9:8] == 2'd0 && dpRespF$D_OUT[19:18] == 2'd0 &&
dpRespF$D_OUT[29:28] == 2'd0 &&
dpRespF$D_OUT[39:38] == 2'd0 ;
// inlined wires
assign edpIngress_1$wget = 1'd1 ;
assign edpIngress_1$whas =
edpReqF$EMPTY_N && (igPtr_1_ULE_3___d12 || dpReqF$FULL_N) ;
assign edpEgress_1$wget = 1'd1 ;
assign edpEgress_1$whas = WILL_FIRE_RL_egress_body ;
assign edpEgressEOP_1$wget =
dpRespF$D_OUT[9:8] != 2'd0 || dpRespF$D_OUT[19:18] != 2'd0 ||
dpRespF$D_OUT[29:28] != 2'd0 ||
dpRespF$D_OUT[39:38] != 2'd0 ;
assign edpEgressEOP_1$whas = WILL_FIRE_RL_egress_body ;
assign edpFsm_start_wire$wget = 1'd1 ;
assign edpFsm_start_wire$whas = edpFsm_start_reg_1_1$whas ;
assign edpFsm_start_reg_1_1$wget = 1'd1 ;
assign edpFsm_start_reg_1_1$whas =
WILL_FIRE_RL_edpFsm_fsm_start ||
edpFsm_start_reg_1 && !edpFsm_state_fired ;
assign edpFsm_abort$wget = 1'b0 ;
assign edpFsm_abort$whas = 1'b0 ;
assign edpFsm_state_fired_1$wget = 1'd1 ;
assign edpFsm_state_fired_1$whas = edpFsm_state_set_pw$whas ;
assign edpFsm_state_set_pw$whas =
WILL_FIRE_RL_edpFsm_idle_l89c3 ||
edpFsm_state_mkFSMstate == 3'd4 ||
WILL_FIRE_RL_edpFsm_action_l93c14 ||
WILL_FIRE_RL_edpFsm_action_l92c14 ||
WILL_FIRE_RL_edpFsm_action_l91c14 ||
WILL_FIRE_RL_edpFsm_action_l90c14 ;
assign edpFsm_state_overlap_pw$whas = 1'b0 ;
// register dEType
assign dEType$D_IN = dstType_t ;
assign dEType$EN = EN_dstType ;
// register dMAddr
assign dMAddr$D_IN = dstAddr_d ;
assign dMAddr$EN = EN_dstAddr ;
// register dbge0
assign dbge0$D_IN =
{ CASE_dpRespFD_OUT_BITS_9_TO_8_3_0_dpRespFD_O_ETC__q12,
dpRespF$D_OUT[7:0] } ;
assign dbge0$EN = WILL_FIRE_RL_egress_body ;
// register dbge1
assign dbge1$D_IN =
{ CASE_dpRespFD_OUT_BITS_19_TO_18_3_0_dpRespFD_ETC__q11,
dpRespF$D_OUT[17:10] } ;
assign dbge1$EN = WILL_FIRE_RL_egress_body ;
// register dbge2
assign dbge2$D_IN =
{ CASE_dpRespFD_OUT_BITS_29_TO_28_3_0_dpRespFD_ETC__q10,
dpRespF$D_OUT[27:20] } ;
assign dbge2$EN = WILL_FIRE_RL_egress_body ;
// register dbge3
assign dbge3$D_IN =
{ CASE_dpRespFD_OUT_BITS_39_TO_38_3_0_dpRespFD_ETC__q9,
dpRespF$D_OUT[37:30] } ;
assign dbge3$EN = WILL_FIRE_RL_egress_body ;
// register edpEgress
assign edpEgress$D_IN = WILL_FIRE_RL_egress_body ;
assign edpEgress$EN = 1'd1 ;
// register edpEgressEOP
assign edpEgressEOP$D_IN = WILL_FIRE_RL_egress_body && edpEgressEOP_1$wget ;
assign edpEgressEOP$EN = 1'd1 ;
// register edpFsm_start_reg
assign edpFsm_start_reg$D_IN = !WILL_FIRE_RL_edpFsm_fsm_start ;
assign edpFsm_start_reg$EN =
WILL_FIRE_RL_edpFsm_fsm_start ||
MUX_edpFsm_start_reg$write_1__SEL_2 ;
// register edpFsm_start_reg_1
assign edpFsm_start_reg_1$D_IN = edpFsm_start_reg_1_1$whas ;
assign edpFsm_start_reg_1$EN = 1'd1 ;
// register edpFsm_state_can_overlap
assign edpFsm_state_can_overlap$D_IN =
edpFsm_state_set_pw$whas || edpFsm_state_can_overlap ;
assign edpFsm_state_can_overlap$EN = 1'd1 ;
// register edpFsm_state_fired
assign edpFsm_state_fired$D_IN = edpFsm_state_set_pw$whas ;
assign edpFsm_state_fired$EN = 1'd1 ;
// register edpFsm_state_mkFSMstate
always@(WILL_FIRE_RL_edpFsm_idle_l89c3 or
WILL_FIRE_RL_edpFsm_action_l90c14 or
WILL_FIRE_RL_edpFsm_action_l91c14 or
WILL_FIRE_RL_edpFsm_action_l92c14 or
WILL_FIRE_RL_edpFsm_action_l93c14 or edpFsm_state_mkFSMstate)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_edpFsm_idle_l89c3: edpFsm_state_mkFSMstate$D_IN = 3'd0;
WILL_FIRE_RL_edpFsm_action_l90c14: edpFsm_state_mkFSMstate$D_IN = 3'd1;
WILL_FIRE_RL_edpFsm_action_l91c14: edpFsm_state_mkFSMstate$D_IN = 3'd2;
WILL_FIRE_RL_edpFsm_action_l92c14: edpFsm_state_mkFSMstate$D_IN = 3'd3;
WILL_FIRE_RL_edpFsm_action_l93c14: edpFsm_state_mkFSMstate$D_IN = 3'd4;
edpFsm_state_mkFSMstate == 3'd4: edpFsm_state_mkFSMstate$D_IN = 3'd5;
default: edpFsm_state_mkFSMstate$D_IN = 3'b010 /* unspecified value */ ;
endcase
end
assign edpFsm_state_mkFSMstate$EN =
WILL_FIRE_RL_edpFsm_idle_l89c3 ||
WILL_FIRE_RL_edpFsm_action_l90c14 ||
WILL_FIRE_RL_edpFsm_action_l91c14 ||
WILL_FIRE_RL_edpFsm_action_l92c14 ||
WILL_FIRE_RL_edpFsm_action_l93c14 ||
edpFsm_state_mkFSMstate == 3'd4 ;
// register edpIngress
assign edpIngress$D_IN = edpIngress_1$whas ;
assign edpIngress$EN = 1'd1 ;
// register eeDID
assign eeDID$D_IN = { dpRespF$D_OUT[27:20], dpRespF$D_OUT[37:30] } ;
assign eeDID$EN = MUX_edpFsm_start_reg$write_1__SEL_2 ;
// register igPtr
assign igPtr$D_IN =
(x__h1670 == 4'd0) ?
((igPtr == 4'd15) ? igPtr : igPtr + 4'd1) :
4'd0 ;
assign igPtr$EN = edpIngress_1$whas ;
// register txPayload
assign txPayload$D_IN =
edpFsm_state_mkFSMstate == 3'd4 || MUX_txPayload$write_1__VAL_2 ;
assign txPayload$EN =
WILL_FIRE_RL_egress_body || edpFsm_state_mkFSMstate == 3'd4 ;
// register uMAddr
assign uMAddr$D_IN = macAddr_u ;
assign uMAddr$EN = EN_macAddr ;
// submodule dpReqF
assign dpReqF$D_IN =
{ CASE_edpReqFD_OUT_BITS_39_TO_38_3_0_edpReqFD_ETC__q13,
edpReqF$D_OUT[37:30],
CASE_edpReqFD_OUT_BITS_29_TO_28_3_0_edpReqFD_ETC__q14,
edpReqF$D_OUT[27:20],
CASE_edpReqFD_OUT_BITS_19_TO_18_3_0_edpReqFD_ETC__q15,
edpReqF$D_OUT[17:10],
CASE_edpReqFD_OUT_BITS_9_TO_8_3_0_edpReqFD_O_ETC__q16,
edpReqF$D_OUT[7:0] } ;
assign dpReqF$ENQ =
edpReqF$EMPTY_N && (igPtr_1_ULE_3___d12 || dpReqF$FULL_N) &&
!igPtr_1_ULE_3___d12 ;
assign dpReqF$DEQ = EN_client_request_get ;
assign dpReqF$CLR = 1'b0 ;
// submodule dpRespF
assign dpRespF$D_IN =
{ CASE_client_response_put_BITS_39_TO_38_3_0_cli_ETC__q17,
client_response_put[37:30],
CASE_client_response_put_BITS_29_TO_28_3_0_cli_ETC__q18,
client_response_put[27:20],
CASE_client_response_put_BITS_19_TO_18_3_0_cli_ETC__q19,
client_response_put[17:10],
CASE_client_response_put_BITS_9_TO_8_3_0_clien_ETC__q20,
client_response_put[7:0] } ;
assign dpRespF$ENQ = EN_client_response_put ;
assign dpRespF$DEQ =
WILL_FIRE_RL_egress_body || MUX_edpFsm_start_reg$write_1__SEL_2 ;
assign dpRespF$CLR = 1'b0 ;
// submodule edpReqF
assign edpReqF$D_IN =
{ CASE_server_request_put_BITS_39_TO_38_3_0_serv_ETC__q21,
server_request_put[37:30],
CASE_server_request_put_BITS_29_TO_28_3_0_serv_ETC__q22,
server_request_put[27:20],
CASE_server_request_put_BITS_19_TO_18_3_0_serv_ETC__q23,
server_request_put[17:10],
CASE_server_request_put_BITS_9_TO_8_3_0_server_ETC__q24,
server_request_put[7:0] } ;
assign edpReqF$ENQ = EN_server_request_put ;
assign edpReqF$DEQ = edpIngress_1$whas ;
assign edpReqF$CLR = 1'b0 ;
// submodule edpRespF
always@(WILL_FIRE_RL_edpFsm_action_l90c14 or
MUX_edpRespF$enq_1__VAL_1 or
WILL_FIRE_RL_edpFsm_action_l91c14 or
MUX_edpRespF$enq_1__VAL_2 or
WILL_FIRE_RL_edpFsm_action_l92c14 or
MUX_edpRespF$enq_1__VAL_3 or
WILL_FIRE_RL_edpFsm_action_l93c14 or
MUX_edpRespF$enq_1__VAL_4 or
WILL_FIRE_RL_egress_body or MUX_edpRespF$enq_1__VAL_5)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_edpFsm_action_l90c14:
edpRespF$D_IN = MUX_edpRespF$enq_1__VAL_1;
WILL_FIRE_RL_edpFsm_action_l91c14:
edpRespF$D_IN = MUX_edpRespF$enq_1__VAL_2;
WILL_FIRE_RL_edpFsm_action_l92c14:
edpRespF$D_IN = MUX_edpRespF$enq_1__VAL_3;
WILL_FIRE_RL_edpFsm_action_l93c14:
edpRespF$D_IN = MUX_edpRespF$enq_1__VAL_4;
WILL_FIRE_RL_egress_body: edpRespF$D_IN = MUX_edpRespF$enq_1__VAL_5;
default: edpRespF$D_IN = 40'hAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign edpRespF$ENQ =
WILL_FIRE_RL_edpFsm_action_l90c14 ||
WILL_FIRE_RL_edpFsm_action_l91c14 ||
WILL_FIRE_RL_edpFsm_action_l92c14 ||
WILL_FIRE_RL_edpFsm_action_l93c14 ||
WILL_FIRE_RL_egress_body ;
assign edpRespF$DEQ = EN_server_response_get ;
assign edpRespF$CLR = 1'b0 ;
// remaining internal signals
assign edpFsm_abort_whas__5_AND_edpFsm_abort_wget__6__ETC___d157 =
(edpFsm_state_mkFSMstate == 3'd0 ||
edpFsm_state_mkFSMstate == 3'd5) &&
(!edpFsm_start_reg_1 || edpFsm_state_fired) ;
assign igPtr_1_ULE_3___d12 = igPtr <= 4'd3 ;
assign x__h1670 =
{ edpReqF$D_OUT[39:38] != 2'd0,
edpReqF$D_OUT[29:28] != 2'd0,
edpReqF$D_OUT[19:18] != 2'd0,
edpReqF$D_OUT[9:8] != 2'd0 } ;
always@(edpRespF$D_OUT)
begin
case (edpRespF$D_OUT[39:38])
2'd0, 2'd1, 2'd2:
CASE_edpRespFD_OUT_BITS_39_TO_38_3_0_edpRespF_ETC__q1 =
edpRespF$D_OUT[39:38];
2'd3: CASE_edpRespFD_OUT_BITS_39_TO_38_3_0_edpRespF_ETC__q1 = 2'd3;
endcase
end
always@(edpRespF$D_OUT)
begin
case (edpRespF$D_OUT[29:28])
2'd0, 2'd1, 2'd2:
CASE_edpRespFD_OUT_BITS_29_TO_28_3_0_edpRespF_ETC__q2 =
edpRespF$D_OUT[29:28];
2'd3: CASE_edpRespFD_OUT_BITS_29_TO_28_3_0_edpRespF_ETC__q2 = 2'd3;
endcase
end
always@(edpRespF$D_OUT)
begin
case (edpRespF$D_OUT[19:18])
2'd0, 2'd1, 2'd2:
CASE_edpRespFD_OUT_BITS_19_TO_18_3_0_edpRespF_ETC__q3 =
edpRespF$D_OUT[19:18];
2'd3: CASE_edpRespFD_OUT_BITS_19_TO_18_3_0_edpRespF_ETC__q3 = 2'd3;
endcase
end
always@(edpRespF$D_OUT)
begin
case (edpRespF$D_OUT[9:8])
2'd0, 2'd1, 2'd2:
CASE_edpRespFD_OUT_BITS_9_TO_8_3_0_edpRespFD_ETC__q4 =
edpRespF$D_OUT[9:8];
2'd3: CASE_edpRespFD_OUT_BITS_9_TO_8_3_0_edpRespFD_ETC__q4 = 2'd3;
endcase
end
always@(dpReqF$D_OUT)
begin
case (dpReqF$D_OUT[39:38])
2'd0, 2'd1, 2'd2:
CASE_dpReqFD_OUT_BITS_39_TO_38_3_0_dpReqFD_O_ETC__q5 =
dpReqF$D_OUT[39:38];
2'd3: CASE_dpReqFD_OUT_BITS_39_TO_38_3_0_dpReqFD_O_ETC__q5 = 2'd3;
endcase
end
always@(dpReqF$D_OUT)
begin
case (dpReqF$D_OUT[29:28])
2'd0, 2'd1, 2'd2:
CASE_dpReqFD_OUT_BITS_29_TO_28_3_0_dpReqFD_O_ETC__q6 =
dpReqF$D_OUT[29:28];
2'd3: CASE_dpReqFD_OUT_BITS_29_TO_28_3_0_dpReqFD_O_ETC__q6 = 2'd3;
endcase
end
always@(dpReqF$D_OUT)
begin
case (dpReqF$D_OUT[19:18])
2'd0, 2'd1, 2'd2:
CASE_dpReqFD_OUT_BITS_19_TO_18_3_0_dpReqFD_O_ETC__q7 =
dpReqF$D_OUT[19:18];
2'd3: CASE_dpReqFD_OUT_BITS_19_TO_18_3_0_dpReqFD_O_ETC__q7 = 2'd3;
endcase
end
always@(dpReqF$D_OUT)
begin
case (dpReqF$D_OUT[9:8])
2'd0, 2'd1, 2'd2:
CASE_dpReqFD_OUT_BITS_9_TO_8_3_0_dpReqFD_OUT_ETC__q8 =
dpReqF$D_OUT[9:8];
2'd3: CASE_dpReqFD_OUT_BITS_9_TO_8_3_0_dpReqFD_OUT_ETC__q8 = 2'd3;
endcase
end
always@(dpRespF$D_OUT)
begin
case (dpRespF$D_OUT[39:38])
2'd0, 2'd1, 2'd2:
CASE_dpRespFD_OUT_BITS_39_TO_38_3_0_dpRespFD_ETC__q9 =
dpRespF$D_OUT[39:38];
2'd3: CASE_dpRespFD_OUT_BITS_39_TO_38_3_0_dpRespFD_ETC__q9 = 2'd3;
endcase
end
always@(dpRespF$D_OUT)
begin
case (dpRespF$D_OUT[29:28])
2'd0, 2'd1, 2'd2:
CASE_dpRespFD_OUT_BITS_29_TO_28_3_0_dpRespFD_ETC__q10 =
dpRespF$D_OUT[29:28];
2'd3: CASE_dpRespFD_OUT_BITS_29_TO_28_3_0_dpRespFD_ETC__q10 = 2'd3;
endcase
end
always@(dpRespF$D_OUT)
begin
case (dpRespF$D_OUT[19:18])
2'd0, 2'd1, 2'd2:
CASE_dpRespFD_OUT_BITS_19_TO_18_3_0_dpRespFD_ETC__q11 =
dpRespF$D_OUT[19:18];
2'd3: CASE_dpRespFD_OUT_BITS_19_TO_18_3_0_dpRespFD_ETC__q11 = 2'd3;
endcase
end
always@(dpRespF$D_OUT)
begin
case (dpRespF$D_OUT[9:8])
2'd0, 2'd1, 2'd2:
CASE_dpRespFD_OUT_BITS_9_TO_8_3_0_dpRespFD_O_ETC__q12 =
dpRespF$D_OUT[9:8];
2'd3: CASE_dpRespFD_OUT_BITS_9_TO_8_3_0_dpRespFD_O_ETC__q12 = 2'd3;
endcase
end
always@(edpReqF$D_OUT)
begin
case (edpReqF$D_OUT[39:38])
2'd0, 2'd1, 2'd2:
CASE_edpReqFD_OUT_BITS_39_TO_38_3_0_edpReqFD_ETC__q13 =
edpReqF$D_OUT[39:38];
2'd3: CASE_edpReqFD_OUT_BITS_39_TO_38_3_0_edpReqFD_ETC__q13 = 2'd3;
endcase
end
always@(edpReqF$D_OUT)
begin
case (edpReqF$D_OUT[29:28])
2'd0, 2'd1, 2'd2:
CASE_edpReqFD_OUT_BITS_29_TO_28_3_0_edpReqFD_ETC__q14 =
edpReqF$D_OUT[29:28];
2'd3: CASE_edpReqFD_OUT_BITS_29_TO_28_3_0_edpReqFD_ETC__q14 = 2'd3;
endcase
end
always@(edpReqF$D_OUT)
begin
case (edpReqF$D_OUT[19:18])
2'd0, 2'd1, 2'd2:
CASE_edpReqFD_OUT_BITS_19_TO_18_3_0_edpReqFD_ETC__q15 =
edpReqF$D_OUT[19:18];
2'd3: CASE_edpReqFD_OUT_BITS_19_TO_18_3_0_edpReqFD_ETC__q15 = 2'd3;
endcase
end
always@(edpReqF$D_OUT)
begin
case (edpReqF$D_OUT[9:8])
2'd0, 2'd1, 2'd2:
CASE_edpReqFD_OUT_BITS_9_TO_8_3_0_edpReqFD_O_ETC__q16 =
edpReqF$D_OUT[9:8];
2'd3: CASE_edpReqFD_OUT_BITS_9_TO_8_3_0_edpReqFD_O_ETC__q16 = 2'd3;
endcase
end
always@(client_response_put)
begin
case (client_response_put[39:38])
2'd0, 2'd1, 2'd2:
CASE_client_response_put_BITS_39_TO_38_3_0_cli_ETC__q17 =
client_response_put[39:38];
2'd3: CASE_client_response_put_BITS_39_TO_38_3_0_cli_ETC__q17 = 2'd3;
endcase
end
always@(client_response_put)
begin
case (client_response_put[29:28])
2'd0, 2'd1, 2'd2:
CASE_client_response_put_BITS_29_TO_28_3_0_cli_ETC__q18 =
client_response_put[29:28];
2'd3: CASE_client_response_put_BITS_29_TO_28_3_0_cli_ETC__q18 = 2'd3;
endcase
end
always@(client_response_put)
begin
case (client_response_put[19:18])
2'd0, 2'd1, 2'd2:
CASE_client_response_put_BITS_19_TO_18_3_0_cli_ETC__q19 =
client_response_put[19:18];
2'd3: CASE_client_response_put_BITS_19_TO_18_3_0_cli_ETC__q19 = 2'd3;
endcase
end
always@(client_response_put)
begin
case (client_response_put[9:8])
2'd0, 2'd1, 2'd2:
CASE_client_response_put_BITS_9_TO_8_3_0_clien_ETC__q20 =
client_response_put[9:8];
2'd3: CASE_client_response_put_BITS_9_TO_8_3_0_clien_ETC__q20 = 2'd3;
endcase
end
always@(server_request_put)
begin
case (server_request_put[39:38])
2'd0, 2'd1, 2'd2:
CASE_server_request_put_BITS_39_TO_38_3_0_serv_ETC__q21 =
server_request_put[39:38];
2'd3: CASE_server_request_put_BITS_39_TO_38_3_0_serv_ETC__q21 = 2'd3;
endcase
end
always@(server_request_put)
begin
case (server_request_put[29:28])
2'd0, 2'd1, 2'd2:
CASE_server_request_put_BITS_29_TO_28_3_0_serv_ETC__q22 =
server_request_put[29:28];
2'd3: CASE_server_request_put_BITS_29_TO_28_3_0_serv_ETC__q22 = 2'd3;
endcase
end
always@(server_request_put)
begin
case (server_request_put[19:18])
2'd0, 2'd1, 2'd2:
CASE_server_request_put_BITS_19_TO_18_3_0_serv_ETC__q23 =
server_request_put[19:18];
2'd3: CASE_server_request_put_BITS_19_TO_18_3_0_serv_ETC__q23 = 2'd3;
endcase
end
always@(server_request_put)
begin
case (server_request_put[9:8])
2'd0, 2'd1, 2'd2:
CASE_server_request_put_BITS_9_TO_8_3_0_server_ETC__q24 =
server_request_put[9:8];
2'd3: CASE_server_request_put_BITS_9_TO_8_3_0_server_ETC__q24 = 2'd3;
endcase
end
// handling of inlined registers
always@(posedge CLK)
begin
if (RST_N == `BSV_RESET_VALUE)
begin
edpEgress <= `BSV_ASSIGNMENT_DELAY 1'd0;
edpEgressEOP <= `BSV_ASSIGNMENT_DELAY 1'd0;
edpFsm_start_reg <= `BSV_ASSIGNMENT_DELAY 1'd0;
edpFsm_start_reg_1 <= `BSV_ASSIGNMENT_DELAY 1'd0;
edpFsm_state_can_overlap <= `BSV_ASSIGNMENT_DELAY 1'd1;
edpFsm_state_fired <= `BSV_ASSIGNMENT_DELAY 1'd0;
edpFsm_state_mkFSMstate <= `BSV_ASSIGNMENT_DELAY 3'd0;
edpIngress <= `BSV_ASSIGNMENT_DELAY 1'd0;
igPtr <= `BSV_ASSIGNMENT_DELAY 4'd0;
txPayload <= `BSV_ASSIGNMENT_DELAY 1'd0;
end
else
begin
if (edpEgress$EN) edpEgress <= `BSV_ASSIGNMENT_DELAY edpEgress$D_IN;
if (edpEgressEOP$EN)
edpEgressEOP <= `BSV_ASSIGNMENT_DELAY edpEgressEOP$D_IN;
if (edpFsm_start_reg$EN)
edpFsm_start_reg <= `BSV_ASSIGNMENT_DELAY edpFsm_start_reg$D_IN;
if (edpFsm_start_reg_1$EN)
edpFsm_start_reg_1 <= `BSV_ASSIGNMENT_DELAY edpFsm_start_reg_1$D_IN;
if (edpFsm_state_can_overlap$EN)
edpFsm_state_can_overlap <= `BSV_ASSIGNMENT_DELAY
edpFsm_state_can_overlap$D_IN;
if (edpFsm_state_fired$EN)
edpFsm_state_fired <= `BSV_ASSIGNMENT_DELAY edpFsm_state_fired$D_IN;
if (edpFsm_state_mkFSMstate$EN)
edpFsm_state_mkFSMstate <= `BSV_ASSIGNMENT_DELAY
edpFsm_state_mkFSMstate$D_IN;
if (edpIngress$EN)
edpIngress <= `BSV_ASSIGNMENT_DELAY edpIngress$D_IN;
if (igPtr$EN) igPtr <= `BSV_ASSIGNMENT_DELAY igPtr$D_IN;
if (txPayload$EN) txPayload <= `BSV_ASSIGNMENT_DELAY txPayload$D_IN;
end
if (dEType$EN) dEType <= `BSV_ASSIGNMENT_DELAY dEType$D_IN;
if (dMAddr$EN) dMAddr <= `BSV_ASSIGNMENT_DELAY dMAddr$D_IN;
if (dbge0$EN) dbge0 <= `BSV_ASSIGNMENT_DELAY dbge0$D_IN;
if (dbge1$EN) dbge1 <= `BSV_ASSIGNMENT_DELAY dbge1$D_IN;
if (dbge2$EN) dbge2 <= `BSV_ASSIGNMENT_DELAY dbge2$D_IN;
if (dbge3$EN) dbge3 <= `BSV_ASSIGNMENT_DELAY dbge3$D_IN;
if (eeDID$EN) eeDID <= `BSV_ASSIGNMENT_DELAY eeDID$D_IN;
if (uMAddr$EN) uMAddr <= `BSV_ASSIGNMENT_DELAY uMAddr$D_IN;
end
// synopsys translate_off
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
initial
begin
dEType = 16'hAAAA;
dMAddr = 48'hAAAAAAAAAAAA;
dbge0 = 10'h2AA;
dbge1 = 10'h2AA;
dbge2 = 10'h2AA;
dbge3 = 10'h2AA;
edpEgress = 1'h0;
edpEgressEOP = 1'h0;
edpFsm_start_reg = 1'h0;
edpFsm_start_reg_1 = 1'h0;
edpFsm_state_can_overlap = 1'h0;
edpFsm_state_fired = 1'h0;
edpFsm_state_mkFSMstate = 3'h2;
edpIngress = 1'h0;
eeDID = 16'hAAAA;
igPtr = 4'hA;
txPayload = 1'h0;
uMAddr = 48'hAAAAAAAAAAAA;
end
`endif // BSV_NO_INITIAL_BLOCKS
// synopsys translate_on
// handling of system tasks
// synopsys translate_off
always@(negedge CLK)
begin
#0;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_edpFsm_action_l91c14 &&
(WILL_FIRE_RL_edpFsm_action_l92c14 ||
WILL_FIRE_RL_edpFsm_action_l93c14 ||
edpFsm_state_mkFSMstate == 3'd4))
$display("Error: \"bsv/eth/EDDP.bsv\", line 91, column 14: (R0001)\n Mutually exclusive rules (from the ME sets [RL_edpFsm_action_l91c14] and\n [RL_edpFsm_action_l92c14, RL_edpFsm_action_l93c14, RL_edpFsm_action_l94c16]\n ) fired in the same clock cycle.\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_edpFsm_action_l92c14 &&
(WILL_FIRE_RL_edpFsm_action_l93c14 ||
edpFsm_state_mkFSMstate == 3'd4))
$display("Error: \"bsv/eth/EDDP.bsv\", line 92, column 14: (R0001)\n Mutually exclusive rules (from the ME sets [RL_edpFsm_action_l92c14] and\n [RL_edpFsm_action_l93c14, RL_edpFsm_action_l94c16] ) fired in the same clock\n cycle.\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_edpFsm_action_l93c14 &&
edpFsm_state_mkFSMstate == 3'd4)
$display("Error: \"bsv/eth/EDDP.bsv\", line 93, column 14: (R0001)\n Mutually exclusive rules (from the ME sets [RL_edpFsm_action_l93c14] and\n [RL_edpFsm_action_l94c16] ) fired in the same clock cycle.\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_edpFsm_action_l90c14 &&
(WILL_FIRE_RL_edpFsm_action_l91c14 ||
WILL_FIRE_RL_edpFsm_action_l92c14 ||
WILL_FIRE_RL_edpFsm_action_l93c14 ||
edpFsm_state_mkFSMstate == 3'd4))
$display("Error: \"bsv/eth/EDDP.bsv\", line 90, column 14: (R0001)\n Mutually exclusive rules (from the ME sets [RL_edpFsm_action_l90c14] and\n [RL_edpFsm_action_l91c14, RL_edpFsm_action_l92c14, RL_edpFsm_action_l93c14,\n RL_edpFsm_action_l94c16] ) fired in the same clock cycle.\n");
end
// synopsys translate_on
endmodule // mkEDDPAdapter
|
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description: AxiLite Slave Conversion
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
// axilite_conv
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_protocol_converter_v2_1_axilite_conv #
(
parameter C_FAMILY = "virtex6",
parameter integer C_AXI_ID_WIDTH = 1,
parameter integer C_AXI_ADDR_WIDTH = 32,
parameter integer C_AXI_DATA_WIDTH = 32,
parameter integer C_AXI_SUPPORTS_WRITE = 1,
parameter integer C_AXI_SUPPORTS_READ = 1,
parameter integer C_AXI_RUSER_WIDTH = 1,
parameter integer C_AXI_BUSER_WIDTH = 1
)
(
// System Signals
input wire ACLK,
input wire ARESETN,
// Slave Interface Write Address Ports
input wire [C_AXI_ID_WIDTH-1:0] S_AXI_AWID,
input wire [C_AXI_ADDR_WIDTH-1:0] S_AXI_AWADDR,
input wire [3-1:0] S_AXI_AWPROT,
input wire S_AXI_AWVALID,
output wire S_AXI_AWREADY,
// Slave Interface Write Data Ports
input wire [C_AXI_DATA_WIDTH-1:0] S_AXI_WDATA,
input wire [C_AXI_DATA_WIDTH/8-1:0] S_AXI_WSTRB,
input wire S_AXI_WVALID,
output wire S_AXI_WREADY,
// Slave Interface Write Response Ports
output wire [C_AXI_ID_WIDTH-1:0] S_AXI_BID,
output wire [2-1:0] S_AXI_BRESP,
output wire [C_AXI_BUSER_WIDTH-1:0] S_AXI_BUSER, // Constant =0
output wire S_AXI_BVALID,
input wire S_AXI_BREADY,
// Slave Interface Read Address Ports
input wire [C_AXI_ID_WIDTH-1:0] S_AXI_ARID,
input wire [C_AXI_ADDR_WIDTH-1:0] S_AXI_ARADDR,
input wire [3-1:0] S_AXI_ARPROT,
input wire S_AXI_ARVALID,
output wire S_AXI_ARREADY,
// Slave Interface Read Data Ports
output wire [C_AXI_ID_WIDTH-1:0] S_AXI_RID,
output wire [C_AXI_DATA_WIDTH-1:0] S_AXI_RDATA,
output wire [2-1:0] S_AXI_RRESP,
output wire S_AXI_RLAST, // Constant =1
output wire [C_AXI_RUSER_WIDTH-1:0] S_AXI_RUSER, // Constant =0
output wire S_AXI_RVALID,
input wire S_AXI_RREADY,
// Master Interface Write Address Port
output wire [C_AXI_ADDR_WIDTH-1:0] M_AXI_AWADDR,
output wire [3-1:0] M_AXI_AWPROT,
output wire M_AXI_AWVALID,
input wire M_AXI_AWREADY,
// Master Interface Write Data Ports
output wire [C_AXI_DATA_WIDTH-1:0] M_AXI_WDATA,
output wire [C_AXI_DATA_WIDTH/8-1:0] M_AXI_WSTRB,
output wire M_AXI_WVALID,
input wire M_AXI_WREADY,
// Master Interface Write Response Ports
input wire [2-1:0] M_AXI_BRESP,
input wire M_AXI_BVALID,
output wire M_AXI_BREADY,
// Master Interface Read Address Port
output wire [C_AXI_ADDR_WIDTH-1:0] M_AXI_ARADDR,
output wire [3-1:0] M_AXI_ARPROT,
output wire M_AXI_ARVALID,
input wire M_AXI_ARREADY,
// Master Interface Read Data Ports
input wire [C_AXI_DATA_WIDTH-1:0] M_AXI_RDATA,
input wire [2-1:0] M_AXI_RRESP,
input wire M_AXI_RVALID,
output wire M_AXI_RREADY
);
wire s_awvalid_i;
wire s_arvalid_i;
wire [C_AXI_ADDR_WIDTH-1:0] m_axaddr;
// Arbiter
reg read_active;
reg write_active;
reg busy;
wire read_req;
wire write_req;
wire read_complete;
wire write_complete;
reg [1:0] areset_d; // Reset delay register
always @(posedge ACLK) begin
areset_d <= {areset_d[0], ~ARESETN};
end
assign s_awvalid_i = S_AXI_AWVALID & (C_AXI_SUPPORTS_WRITE != 0);
assign s_arvalid_i = S_AXI_ARVALID & (C_AXI_SUPPORTS_READ != 0);
assign read_req = s_arvalid_i & ~busy & ~|areset_d & ~write_active;
assign write_req = s_awvalid_i & ~busy & ~|areset_d & ((~read_active & ~s_arvalid_i) | write_active);
assign read_complete = M_AXI_RVALID & S_AXI_RREADY;
assign write_complete = M_AXI_BVALID & S_AXI_BREADY;
always @(posedge ACLK) begin : arbiter_read_ff
if (|areset_d)
read_active <= 1'b0;
else if (read_complete)
read_active <= 1'b0;
else if (read_req)
read_active <= 1'b1;
end
always @(posedge ACLK) begin : arbiter_write_ff
if (|areset_d)
write_active <= 1'b0;
else if (write_complete)
write_active <= 1'b0;
else if (write_req)
write_active <= 1'b1;
end
always @(posedge ACLK) begin : arbiter_busy_ff
if (|areset_d)
busy <= 1'b0;
else if (read_complete | write_complete)
busy <= 1'b0;
else if ((write_req & M_AXI_AWREADY) | (read_req & M_AXI_ARREADY))
busy <= 1'b1;
end
assign M_AXI_ARVALID = read_req;
assign S_AXI_ARREADY = M_AXI_ARREADY & read_req;
assign M_AXI_AWVALID = write_req;
assign S_AXI_AWREADY = M_AXI_AWREADY & write_req;
assign M_AXI_RREADY = S_AXI_RREADY & read_active;
assign S_AXI_RVALID = M_AXI_RVALID & read_active;
assign M_AXI_BREADY = S_AXI_BREADY & write_active;
assign S_AXI_BVALID = M_AXI_BVALID & write_active;
// Address multiplexer
assign m_axaddr = (read_req | (C_AXI_SUPPORTS_WRITE == 0)) ? S_AXI_ARADDR : S_AXI_AWADDR;
// Id multiplexer and flip-flop
reg [C_AXI_ID_WIDTH-1:0] s_axid;
always @(posedge ACLK) begin : axid
if (read_req) s_axid <= S_AXI_ARID;
else if (write_req) s_axid <= S_AXI_AWID;
end
assign S_AXI_BID = s_axid;
assign S_AXI_RID = s_axid;
assign M_AXI_AWADDR = m_axaddr;
assign M_AXI_ARADDR = m_axaddr;
// Feed-through signals
assign S_AXI_WREADY = M_AXI_WREADY & ~|areset_d;
assign S_AXI_BRESP = M_AXI_BRESP;
assign S_AXI_RDATA = M_AXI_RDATA;
assign S_AXI_RRESP = M_AXI_RRESP;
assign S_AXI_RLAST = 1'b1;
assign S_AXI_BUSER = {C_AXI_BUSER_WIDTH{1'b0}};
assign S_AXI_RUSER = {C_AXI_RUSER_WIDTH{1'b0}};
assign M_AXI_AWPROT = S_AXI_AWPROT;
assign M_AXI_WVALID = S_AXI_WVALID & ~|areset_d;
assign M_AXI_WDATA = S_AXI_WDATA;
assign M_AXI_WSTRB = S_AXI_WSTRB;
assign M_AXI_ARPROT = S_AXI_ARPROT;
endmodule
|
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description: Write Data Response Down-Sizer
// Collect MI-side responses and set the SI-side response to the most critical
// level (in descending order):
// DECERR, SLVERROR and OKAY.
// EXOKAY cannot occur for split transactions.
//
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
// wr_upsizer
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_protocol_converter_v2_1_b_downsizer #
(
parameter C_FAMILY = "none",
// FPGA Family. Current version: virtex6 or spartan6.
parameter integer C_AXI_ID_WIDTH = 4,
// Width of all ID signals on SI and MI side of converter.
// Range: >= 1.
parameter integer C_AXI_SUPPORTS_USER_SIGNALS = 0,
// 1 = Propagate all USER signals, 0 = Don�t propagate.
parameter integer C_AXI_BUSER_WIDTH = 1
// Width of BUSER signals.
// Range: >= 1.
)
(
// Global Signals
input wire ARESET,
input wire ACLK,
// Command Interface
input wire cmd_valid,
input wire cmd_split,
input wire [4-1:0] cmd_repeat,
output wire cmd_ready,
// Slave Interface Write Response Ports
output wire [C_AXI_ID_WIDTH-1:0] S_AXI_BID,
output wire [2-1:0] S_AXI_BRESP,
output wire [C_AXI_BUSER_WIDTH-1:0] S_AXI_BUSER,
output wire S_AXI_BVALID,
input wire S_AXI_BREADY,
// Master Interface Write Response Ports
input wire [C_AXI_ID_WIDTH-1:0] M_AXI_BID,
input wire [2-1:0] M_AXI_BRESP,
input wire [C_AXI_BUSER_WIDTH-1:0] M_AXI_BUSER,
input wire M_AXI_BVALID,
output wire M_AXI_BREADY
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
// Constants for packing levels.
localparam [2-1:0] C_RESP_OKAY = 2'b00;
localparam [2-1:0] C_RESP_EXOKAY = 2'b01;
localparam [2-1:0] C_RESP_SLVERROR = 2'b10;
localparam [2-1:0] C_RESP_DECERR = 2'b11;
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
// Throttling help signals.
wire cmd_ready_i;
wire pop_mi_data;
wire mi_stalling;
// Repeat handling related.
reg [4-1:0] repeat_cnt_pre;
reg [4-1:0] repeat_cnt;
wire [4-1:0] next_repeat_cnt;
reg first_mi_word;
wire last_word;
// Ongoing split transaction.
wire load_bresp;
wire need_to_update_bresp;
reg [2-1:0] S_AXI_BRESP_ACC;
// Internal signals for MI-side.
wire M_AXI_BREADY_I;
// Internal signals for SI-side.
wire [C_AXI_ID_WIDTH-1:0] S_AXI_BID_I;
reg [2-1:0] S_AXI_BRESP_I;
wire [C_AXI_BUSER_WIDTH-1:0] S_AXI_BUSER_I;
wire S_AXI_BVALID_I;
wire S_AXI_BREADY_I;
/////////////////////////////////////////////////////////////////////////////
// Handle interface handshaking:
//
// The MI-side BRESP is popped when at once for split transactions, except
// for the last cycle that behaves like a "normal" transaction.
// A "normal" BRESP is popped once the SI-side is able to use it,
//
//
/////////////////////////////////////////////////////////////////////////////
// Pop word from MI-side.
assign M_AXI_BREADY_I = M_AXI_BVALID & ~mi_stalling;
assign M_AXI_BREADY = M_AXI_BREADY_I;
// Indicate when there is a BRESP available @ SI-side.
assign S_AXI_BVALID_I = M_AXI_BVALID & last_word;
// Get MI-side data.
assign pop_mi_data = M_AXI_BVALID & M_AXI_BREADY_I;
// Signal that the command is done (so that it can be poped from command queue).
assign cmd_ready_i = cmd_valid & pop_mi_data & last_word;
assign cmd_ready = cmd_ready_i;
// Detect when MI-side is stalling.
assign mi_stalling = (~S_AXI_BREADY_I & last_word);
/////////////////////////////////////////////////////////////////////////////
// Handle the accumulation of BRESP.
//
// Forward the accumulated or MI-side BRESP value depending on state:
// * MI-side BRESP is forwarded untouched when it is a non split cycle.
// (MI-side BRESP value is also used when updating the accumulated for
// the last access during a split access).
// * The accumulated BRESP is for a split transaction.
//
// The accumulated BRESP register is updated for each MI-side response that
// is used.
//
/////////////////////////////////////////////////////////////////////////////
// Force load accumulated BRESPs to first value
assign load_bresp = (cmd_split & first_mi_word);
// Update if more critical.
assign need_to_update_bresp = ( M_AXI_BRESP > S_AXI_BRESP_ACC );
// Select accumultated or direct depending on setting.
always @ *
begin
if ( cmd_split ) begin
if ( load_bresp || need_to_update_bresp ) begin
S_AXI_BRESP_I = M_AXI_BRESP;
end else begin
S_AXI_BRESP_I = S_AXI_BRESP_ACC;
end
end else begin
S_AXI_BRESP_I = M_AXI_BRESP;
end
end
// Accumulate MI-side BRESP.
always @ (posedge ACLK) begin
if (ARESET) begin
S_AXI_BRESP_ACC <= C_RESP_OKAY;
end else begin
if ( pop_mi_data ) begin
S_AXI_BRESP_ACC <= S_AXI_BRESP_I;
end
end
end
/////////////////////////////////////////////////////////////////////////////
// Keep track of BRESP repeat counter.
//
// Last BRESP word is either:
// * The first and only word when not merging.
// * The last value when merging.
//
// The internal counter is taken from the external command interface during
// the first response when merging. The counter is updated each time a
// BRESP is popped from the MI-side interface.
//
/////////////////////////////////////////////////////////////////////////////
// Determine last BRESP cycle.
assign last_word = ( ( repeat_cnt == 4'b0 ) & ~first_mi_word ) |
~cmd_split;
// Select command reapeat or counted repeat value.
always @ *
begin
if ( first_mi_word ) begin
repeat_cnt_pre = cmd_repeat;
end else begin
repeat_cnt_pre = repeat_cnt;
end
end
// Calculate next repeat counter value.
assign next_repeat_cnt = repeat_cnt_pre - 1'b1;
// Keep track of the repeat count.
always @ (posedge ACLK) begin
if (ARESET) begin
repeat_cnt <= 4'b0;
first_mi_word <= 1'b1;
end else begin
if ( pop_mi_data ) begin
repeat_cnt <= next_repeat_cnt;
first_mi_word <= last_word;
end
end
end
/////////////////////////////////////////////////////////////////////////////
// BID Handling
/////////////////////////////////////////////////////////////////////////////
assign S_AXI_BID_I = M_AXI_BID;
/////////////////////////////////////////////////////////////////////////////
// USER Data bits
//
// The last USER bits are simply taken from the last BRESP that is merged.
// Ground USER bits when unused.
/////////////////////////////////////////////////////////////////////////////
// Select USER bits.
assign S_AXI_BUSER_I = {C_AXI_BUSER_WIDTH{1'b0}};
/////////////////////////////////////////////////////////////////////////////
// SI-side output handling
/////////////////////////////////////////////////////////////////////////////
// TODO: registered?
assign S_AXI_BID = S_AXI_BID_I;
assign S_AXI_BRESP = S_AXI_BRESP_I;
assign S_AXI_BUSER = S_AXI_BUSER_I;
assign S_AXI_BVALID = S_AXI_BVALID_I;
assign S_AXI_BREADY_I = S_AXI_BREADY;
endmodule
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: dram_sstl_pad.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
module dram_sstl_pad(/*AUTOARG*/
// Outputs
to_core, bso,
// Inouts
pad,
// Inputs
vrefcode, vdd_h, update_dr, shift_dr, oe, odt_enable_mask,
mode_ctrl, hiz_n, data_in, clock_dr, cbu, cbd, bsi
);
inout pad;
/*AUTOOUTPUT*/
// Beginning of automatic outputs (from unused autoinst outputs)
output bso; // From dram_pad_scan_jtag of dram_pad_scan_jtag.v
output to_core; // From dram_pad_scan_jtag of dram_pad_scan_jtag.v
// End of automatics
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
input bsi; // To dram_pad_scan_jtag of dram_pad_scan_jtag.v
input [8:1] cbd; // To bw_io_ddr_pad_txrx of bw_io_ddr_pad_txrx.v
input [8:1] cbu; // To bw_io_ddr_pad_txrx of bw_io_ddr_pad_txrx.v
input clock_dr; // To dram_pad_scan_jtag of dram_pad_scan_jtag.v
input data_in; // To dram_pad_scan_jtag of dram_pad_scan_jtag.v
input hiz_n; // To dram_pad_scan_jtag of dram_pad_scan_jtag.v
input mode_ctrl; // To dram_pad_scan_jtag of dram_pad_scan_jtag.v
input odt_enable_mask; // To dram_pad_scan_jtag of dram_pad_scan_jtag.v
input oe; // To dram_pad_scan_jtag of dram_pad_scan_jtag.v
input shift_dr; // To dram_pad_scan_jtag of dram_pad_scan_jtag.v
input update_dr; // To dram_pad_scan_jtag of dram_pad_scan_jtag.v
input vdd_h; // To bw_io_ddr_pad_txrx of bw_io_ddr_pad_txrx.v
input [7:0] vrefcode; // To bw_io_ddr_pad_txrx of bw_io_ddr_pad_txrx.v
// End of automatics
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire bscan_oe; // From dram_pad_scan_jtag of dram_pad_scan_jtag.v
wire data_out; // From dram_pad_scan_jtag of dram_pad_scan_jtag.v
wire odt_enable; // From dram_pad_scan_jtag of dram_pad_scan_jtag.v
wire rx_out; // From bw_io_ddr_pad_txrx of bw_io_ddr_pad_txrx.v
// End of automatics
/////////////////////
// TRANSCEIVER module
/////////////////////
/* bw_io_ddr_pad_txrx AUTO_TEMPLATE(
// Outputs
.out (rx_out),
// Inputs
.data (data_out),
.oe (bscan_oe));
*/
bw_io_ddr_pad_txrx bw_io_ddr_pad_txrx(/*AUTOINST*/
// Outputs
.out(rx_out), // Templated
// Inouts
.pad(pad),
// Inputs
.vrefcode(vrefcode[7:0]),
.odt_enable(odt_enable),
.vdd_h(vdd_h),
.cbu(cbu[8:1]),
.cbd(cbd[8:1]),
.data(data_out), // Templated
.oe(bscan_oe)); // Templated
/////////////////////
// SCAN & JTAG module
/////////////////////
/*bw_io_sstl_bscan AUTO_TEMPLATE(
// Outputs
.oe(bscan_oe),
// Inputs
.rcv_in(rx_out),
.drv_oe(oe));
*/
bw_io_sstl_bscan bw_io_sstl_bscan(/*AUTOINST*/
// Outputs
.to_core(to_core),
.data_out(data_out),
.oe(bscan_oe), // Templated
.bso(bso),
.odt_enable(odt_enable),
// Inputs
.bsi(bsi),
.mode_ctrl(mode_ctrl),
.clock_dr(clock_dr),
.shift_dr(shift_dr),
.update_dr(update_dr),
.hiz_l(hiz_n),
.rcv_in(rx_out), // Templated
.data_in(data_in),
.drv_oe(oe), // Templated
.odt_enable_mask(odt_enable_mask));
endmodule
// Local Variables:
// verilog-library-directories:(".")
|
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2008-2008 by Wilson Snyder.
module autoinst_moddefine (/*AUTOARG*/);
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire q; // From `SUBNAME_B of `SUBMOD_A.v, ...
// End of automatics
`define SUBMOD_A submod_mod
`define SUBNAME_B subname_b
`SUBMOD_A `SUBNAME_B
(/*AUTOINST*/
// Outputs
.q (q),
// Inputs
.a (a));
`SUBMOD_UNDEFED subundefed
(/*AUTOINST*/
// Outputs
.q (q));
submod_decl_from_def subundefed
(/*AUTOINST*/
// Outputs
.q (q));
endmodule
module submod_mod (/*AUTOARG*/
// Outputs
q,
// Inputs
a
);
input a;
output q;
endmodule
module SUBMOD_UNDEFED (/*AUTOARG*/
// Outputs
q
);
output q;
endmodule
`define SUBMOD_DECL submod_decl_from_def
module `SUBMOD_DECL (/*AUTOARG*/
// Outputs
q
);
output q;
endmodule
// Local Variables:
// verilog-auto-read-includes:t
// End:
|
/*
----------------------------------------------------------------------------------
Copyright (c) 2013-2014
Embedded and Network Computing Lab.
Open SSD Project
Hanyang University
All rights reserved.
----------------------------------------------------------------------------------
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. All advertising materials mentioning features or use of this source code
must display the following acknowledgement:
This product includes source code developed
by the Embedded and Network Computing Lab. and the Open SSD Project.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
----------------------------------------------------------------------------------
http://enclab.hanyang.ac.kr/
http://www.openssd-project.org/
http://www.hanyang.ac.kr/
----------------------------------------------------------------------------------
*/
`timescale 1ns / 1ps
module pcie_hcmd_slot_mgt
(
input pcie_user_clk,
input pcie_user_rst_n,
output hcmd_slot_rdy,
output [6:0] hcmd_slot_tag,
input hcmd_slot_alloc_en,
input hcmd_slot_free_en,
input [6:0] hcmd_slot_invalid_tag
);
localparam S_RESET_SEARCH_SLOT = 5'b00001;
localparam S_SEARCH_L1_SLOT = 5'b00010;
localparam S_SEARCH_L2_SLOT = 5'b00100;
localparam S_GNT_VAILD_SLOT = 5'b01000;
localparam S_VAILD_SLOT = 5'b10000;
reg [4:0] cur_state;
reg [4:0] next_state;
reg [127:0] r_slot_valid;
reg [127:0] r_slot_search_mask;
reg [127:0] r_slot_valid_mask;
reg [6:0] r_slot_tag;
reg r_slot_rdy;
reg [15:0] r_slot_l1_valid;
wire [7:0] w_slot_l1_mask;
wire r_slot_l1_ok;
//wire [7:0] w_slot_l2_valid;
wire [127:0] w_slot_l2_mask;
wire w_slot_l2_ok;
reg r_slot_free_en;
reg [6:0] r_slot_invalid_tag;
reg [127:0] r_slot_invalid_mask;
wire [127:0] w_slot_invalid_mask;
assign hcmd_slot_rdy = r_slot_rdy;
assign hcmd_slot_tag = r_slot_tag;
assign w_slot_l1_mask = { r_slot_search_mask[95],
r_slot_search_mask[79],
r_slot_search_mask[63],
r_slot_search_mask[47],
r_slot_search_mask[31],
r_slot_search_mask[15],
r_slot_search_mask[127],
r_slot_search_mask[111]};
always @ (*)
begin
case(w_slot_l1_mask) // synthesis parallel_case full_case
8'b00000001: r_slot_l1_valid <= r_slot_valid[15:0];
8'b00000010: r_slot_l1_valid <= r_slot_valid[31:16];
8'b00000100: r_slot_l1_valid <= r_slot_valid[47:32];
8'b00001000: r_slot_l1_valid <= r_slot_valid[63:48];
8'b00010000: r_slot_l1_valid <= r_slot_valid[79:64];
8'b00100000: r_slot_l1_valid <= r_slot_valid[95:80];
8'b01000000: r_slot_l1_valid <= r_slot_valid[111:96];
8'b10000000: r_slot_l1_valid <= r_slot_valid[127:112];
endcase
end
assign r_slot_l1_ok = (r_slot_l1_valid != 16'hFFFF);
assign w_slot_l2_mask = {r_slot_search_mask[126:0], r_slot_search_mask[127]};
assign w_slot_l2_ok = ((r_slot_valid & w_slot_l2_mask) == 0);
always @ (posedge pcie_user_clk or negedge pcie_user_rst_n)
begin
if(pcie_user_rst_n == 0)
cur_state <= S_RESET_SEARCH_SLOT;
else
cur_state <= next_state;
end
always @ (*)
begin
case(cur_state)
S_RESET_SEARCH_SLOT: begin
next_state <= S_SEARCH_L1_SLOT;
end
S_SEARCH_L1_SLOT: begin
if(r_slot_l1_ok == 1)
next_state <= S_SEARCH_L2_SLOT;
else
next_state <= S_SEARCH_L1_SLOT;
end
S_SEARCH_L2_SLOT: begin
if(w_slot_l2_ok == 1)
next_state <= S_GNT_VAILD_SLOT;
else
next_state <= S_SEARCH_L2_SLOT;
end
S_GNT_VAILD_SLOT: begin
if(hcmd_slot_alloc_en == 1)
next_state <= S_VAILD_SLOT;
else
next_state <= S_GNT_VAILD_SLOT;
end
S_VAILD_SLOT: begin
next_state <= S_RESET_SEARCH_SLOT;
end
default: begin
next_state <= S_RESET_SEARCH_SLOT;
end
endcase
end
always @ (posedge pcie_user_clk)
begin
case(cur_state)
S_RESET_SEARCH_SLOT: begin
r_slot_search_mask[127:112] <= 0;
r_slot_search_mask[111] <= 1'b1;
r_slot_search_mask[110:0] <= 0;
r_slot_tag <= 7'h6F;
end
S_SEARCH_L1_SLOT: begin
r_slot_search_mask[111] <= w_slot_l1_mask[7];
r_slot_search_mask[95] <= w_slot_l1_mask[6];
r_slot_search_mask[79] <= w_slot_l1_mask[5];
r_slot_search_mask[63] <= w_slot_l1_mask[4];
r_slot_search_mask[47] <= w_slot_l1_mask[3];
r_slot_search_mask[31] <= w_slot_l1_mask[2];
r_slot_search_mask[15] <= w_slot_l1_mask[1];
r_slot_search_mask[127] <= w_slot_l1_mask[0];
r_slot_tag <= r_slot_tag + 16;
end
S_SEARCH_L2_SLOT: begin
r_slot_search_mask <= w_slot_l2_mask;
r_slot_tag <= r_slot_tag + 1;
end
S_GNT_VAILD_SLOT: begin
end
S_VAILD_SLOT: begin
end
default: begin
end
endcase
end
always @ (posedge pcie_user_clk or negedge pcie_user_rst_n)
begin
if(pcie_user_rst_n == 0) begin
r_slot_valid <= 0;
end
else begin
r_slot_valid <= (r_slot_valid | r_slot_valid_mask) & r_slot_invalid_mask;
//r_slot_valid <= (r_slot_valid | r_slot_valid_mask);
end
end
always @ (*)
begin
case(cur_state)
S_RESET_SEARCH_SLOT: begin
r_slot_rdy <= 0;
r_slot_valid_mask <= 0;
end
S_SEARCH_L1_SLOT: begin
r_slot_rdy <= 0;
r_slot_valid_mask <= 0;
end
S_SEARCH_L2_SLOT: begin
r_slot_rdy <= 0;
r_slot_valid_mask <= 0;
end
S_GNT_VAILD_SLOT: begin
r_slot_rdy <= 1;
r_slot_valid_mask <= 0;
end
S_VAILD_SLOT: begin
r_slot_rdy <= 0;
r_slot_valid_mask <= r_slot_search_mask;
end
default: begin
r_slot_rdy <= 0;
r_slot_valid_mask <= 0;
end
endcase
end
always @ (posedge pcie_user_clk)
begin
r_slot_free_en <= hcmd_slot_free_en;
r_slot_invalid_tag <= hcmd_slot_invalid_tag;
if(r_slot_free_en == 1)
r_slot_invalid_mask <= w_slot_invalid_mask;
else
r_slot_invalid_mask <= {128{1'b1}};
end
genvar i;
generate
for(i = 0; i < 128; i = i + 1)
begin : INVALID_TAG
assign w_slot_invalid_mask[i] = (r_slot_invalid_tag != i);
end
endgenerate
endmodule |
// This tests SystemVerilog casting support
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2012 by Iztok Jeras.
// Extended by Maciej Suminski
// Copied and modified by Martin Whitaker
// Copied and modified again by Lars-Peter Clausen
module test();
typedef logic [7:0] pa08;
typedef pa08 [1:0] pa16;
typedef pa16 [1:0] pa32;
typedef pa32 [1:0] pa64;
// variables used in casting
pa08 var_08;
pa16 var_16;
pa32 var_32;
pa64 var_64;
real var_real;
// error counter
bit err = 0;
initial begin
var_08 = pa08'(4'h5); if (var_08 !== 8'h05) begin $display("FAILED -- var_08 = 'h%0h != 8'h05", var_08); err=1; end
var_16 = pa16'(var_08); if (var_16 !== 16'h05) begin $display("FAILED -- var_16 = 'h%0h != 16'h05", var_16); err=1; end
var_32 = pa32'(var_16); if (var_32 !== 32'h05) begin $display("FAILED -- var_32 = 'h%0h != 32'h05", var_32); err=1; end
var_64 = pa64'(var_32); if (var_64 !== 64'h05) begin $display("FAILED -- var_64 = 'h%0h != 64'h05", var_64); err=1; end
var_real = 13.4; var_08 = pa08'(var_real); if (var_08 !== 13) begin $display("FAILED -- var_08 = %d != 13", var_08); err=1; end
var_real = 14.5; var_16 = pa16'(var_real); if (var_16 !== 15) begin $display("FAILED -- var_16 = %d != 15", var_16); err=1; end
var_real = 15.6; var_32 = pa32'(var_real); if (var_32 !== 16) begin $display("FAILED -- var_32 = %d != 16", var_32); err=1; end
var_real = -15.6; var_64 = pa64'(var_real); if (var_64 !== -16) begin $display("FAILED -- var_64 = %d != -16", var_64); err=1; end
var_08 = pa08'(4'hf); if (var_08 !== 8'h0f) begin $display("FAILED -- var_08 = 'h%0h != 8'h0f", var_08); err=1; end
var_16 = pa08'(16'h0f0f); if (var_16 !== 16'h0f) begin $display("FAILED -- var_16 = 'h%0h != 16'h0f", var_16); err=1; end
if (!err) $display("PASSED");
end
endmodule // test
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 16:35:40 05/31/2016
// Design Name:
// Module Name: Contador_AD_Dia
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Contador_AD_Dia(
input rst,
input [7:0]estado,
input [1:0] en,
input [7:0] Cambio,
input got_data,
input clk,
output reg [(N-1):0] Cuenta
);
parameter N = 7;
parameter X = 99;
always @(posedge clk)
if (rst)
Cuenta <= 1;
else if (en == 2'd2 && estado == 8'h7D)
begin
if (Cambio == 8'h73 && got_data)
begin
if (Cuenta == X)
Cuenta <= 1;
else
Cuenta <= Cuenta + 1'd1;
end
else if (Cambio == 8'h72 && got_data)
begin
if (Cuenta == 1)
Cuenta <= X;
else
Cuenta <= Cuenta - 1'd1;
end
else
Cuenta <= Cuenta;
end
else
Cuenta <= Cuenta;
endmodule
|
//*****************************************************************************
// (c) Copyright 2008-2009 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 3.91
// \ \ Application : MIG
// / / Filename : rank_cntrl.v
// /___/ /\ Date Last Modified : $date$
// \ \ / \ Date Created : Tue Jun 30 2009
// \___\/\___\
//
//Device : Virtex-6
//Design Name : DDR3 SDRAM
//Purpose :
//Reference :
//Revision History :
//*****************************************************************************
// This block is responsible for managing various rank level timing
// parameters. For now, only Four Activate Window (FAW) and Write
// To Read delay are implemented here.
//
// Each rank machine generates its own inhbt_act_faw_r and inhbt_rd_r.
// These per rank machines are driven into the bank machines. Each
// bank machines selects the correct inhibits based on the rank
// of its current request.
`timescale 1 ps / 1 ps
module rank_cntrl #
(
parameter TCQ = 100,
parameter BURST_MODE = "8",
parameter ID = 0,
parameter nBANK_MACHS = 4,
parameter nCK_PER_CLK = 2,
parameter CL = 5,
parameter nFAW = 30,
parameter nREFRESH_BANK = 8,
parameter nRRD = 4,
parameter nWTR = 4,
parameter PERIODIC_RD_TIMER_DIV = 20,
parameter RANK_BM_BV_WIDTH = 16,
parameter RANK_WIDTH = 2,
parameter RANKS = 4,
parameter PHASE_DETECT = "OFF",
parameter REFRESH_TIMER_DIV = 39
)
(/*AUTOARG*/
// Outputs
inhbt_act_faw_r, inhbt_rd_r, wtr_inhbt_config_r, refresh_request,
periodic_rd_request,
// Inputs
clk, rst, sending_row, act_this_rank_r, sending_col, wr_this_rank_r,
app_ref_req, dfi_init_complete, rank_busy_r, refresh_tick,
insert_maint_r1, maint_zq_r, maint_rank_r, app_periodic_rd_req,
maint_prescaler_tick_r, clear_periodic_rd_request, rd_this_rank_r
);
input clk;
input rst;
function integer clogb2 (input integer size); // ceiling logb2
begin
size = size - 1;
for (clogb2=1; size>1; clogb2=clogb2+1)
size = size >> 1;
end
endfunction // clogb2
// Determine if this rank has been activated. act_this_rank_r is a
// registered bit vector from individual bank machines indicating the
// corresponding bank machine is sending
// an activate. Timing is improved with this method.
input [nBANK_MACHS-1:0] sending_row;
input [RANK_BM_BV_WIDTH-1:0] act_this_rank_r;
reg act_this_rank;
integer i;
always @(/*AS*/act_this_rank_r or sending_row) begin
act_this_rank = 1'b0;
for (i=0; i<nBANK_MACHS; i=i+1)
act_this_rank =
act_this_rank || (sending_row[i] && act_this_rank_r[(i*RANKS)+ID]);
end
// RRD. The bank machines have a mechanism to prevent RAS to RAS
// on adjacent fabric CLK states to the same rank. When
// nCK_PER_CLK == 1, this translates to a minimum of 2 for nRRD, and
// 4 for nRRD when nCK_PER_CLK == 2. Some of the higher clock
// rate DDR3 DRAMs have nRRD > 4. The additional RRD inhibit is worked into
// the inhbt_faw signal.
localparam nADD_RRD = nRRD - ((nCK_PER_CLK == 1) ? 2 : 4);
localparam nRRD_CLKS = (nCK_PER_CLK == 1)
? nADD_RRD
: ((nADD_RRD/2) + (nADD_RRD%2));
localparam ADD_RRD_CNTR_WIDTH = clogb2(nRRD_CLKS + /*idle state*/ 1);
reg add_rrd_inhbt = 1'b0;
generate
if (nADD_RRD > 0) begin :add_rdd
reg[ADD_RRD_CNTR_WIDTH-1:0] add_rrd_ns;
reg[ADD_RRD_CNTR_WIDTH-1:0] add_rrd_r;
always @(/*AS*/act_this_rank or add_rrd_r or rst) begin
add_rrd_ns = add_rrd_r;
if (rst) add_rrd_ns = {ADD_RRD_CNTR_WIDTH{1'b0}};
else
if (act_this_rank)
add_rrd_ns = nRRD_CLKS[0+:ADD_RRD_CNTR_WIDTH];
else if (|add_rrd_r) add_rrd_ns =
add_rrd_r - {{ADD_RRD_CNTR_WIDTH-1{1'b0}}, 1'b1};
end
always @(posedge clk) add_rrd_r <= #TCQ add_rrd_ns;
always @(/*AS*/add_rrd_ns) add_rrd_inhbt = |add_rrd_ns;
end
endgenerate
// Compute inhbt_act_faw_r. Only allow a limited number of activates
// in a window. Both the number of activates and the window are
// configurable. This depends on the RRD mechanism to prevent
// two consecutive activates to the same rank.
//
// Subtract three from the specified nFAW. Subtract three because:
// -Zero for the delay into the SRL is really one state.
// -Sending_row is used to trigger the delay. Sending_row is one
// state delayed from the arb.
// -inhbt_act_faw_r is registered to make timing work, hence the
// generation needs to be one state early.
localparam nFAW_CLKS = (nCK_PER_CLK == 1)
? nFAW
: ((nFAW/2) + (nFAW%2));
output reg inhbt_act_faw_r;
generate
begin : inhbt_act_faw
wire act_delayed;
wire [4:0] shift_depth = nFAW_CLKS[4:0] - 5'd3;
SRLC32E #(.INIT(32'h00000000) ) SRLC32E0
(.Q(act_delayed), // SRL data output
.Q31(), // SRL cascade output pin
.A(shift_depth), // 5-bit shift depth select input
.CE(1'b1), // Clock enable input
.CLK(clk), // Clock input
.D(act_this_rank) // SRL data input
);
reg [2:0] faw_cnt_ns;
reg [2:0] faw_cnt_r;
reg inhbt_act_faw_ns;
always @(/*AS*/act_delayed or act_this_rank or add_rrd_inhbt
or faw_cnt_r or rst) begin
if (rst) faw_cnt_ns = 3'b0;
else begin
faw_cnt_ns = faw_cnt_r;
if (act_this_rank) faw_cnt_ns = faw_cnt_r + 3'b1;
if (act_delayed) faw_cnt_ns = faw_cnt_ns - 3'b1;
end
inhbt_act_faw_ns = (faw_cnt_ns == 3'h4) || add_rrd_inhbt;
end
always @(posedge clk) faw_cnt_r <= #TCQ faw_cnt_ns;
always @(posedge clk) inhbt_act_faw_r <= #TCQ inhbt_act_faw_ns;
end // block: inhbt_act_faw
endgenerate
// In the DRAM spec, tWTR starts from CK following the end of the data
// burst. Since we don't directly have that spec, the wtr timer is
// based on when the CAS write command is sent to the DRAM.
//
// To compute the wtr timer value, first compute the time from
// first data of the write to the first data of the read. This
// is data_time + nWTR + CL.
//
// Now note that dfi_rddata_en and dfi_wrdata_en have a equal
// delays to data on the DQ bus. If we compute the minimum dfi_wrdata_en
// to dfi_rddata_en value we can compare it to the required data
// to data delay computed above and determine if we need to
// implement the wtr timer. (currently not implemented)
//
// Two is subtracted from the required wtr time since the timer
// starts two states after the arbitration cycle.
localparam ONE = 1;
localparam CASWR2CASRD = ((BURST_MODE == "4") ? 2 : 4) + nWTR + CL;
localparam CASWR2CASRD_CLKS = (nCK_PER_CLK == 1)
? CASWR2CASRD
: ((CASWR2CASRD / 2) + (CASWR2CASRD %2));
localparam WTR_CNT_WIDTH = clogb2(CASWR2CASRD_CLKS - /*-2 max cnt*/ 1);
localparam TWO = 2;
input [nBANK_MACHS-1:0] sending_col;
input [RANK_BM_BV_WIDTH-1:0] wr_this_rank_r;
output reg inhbt_rd_r;
output reg wtr_inhbt_config_r;
generate
begin : wtr_timer
reg write_this_rank;
always @(/*AS*/sending_col or wr_this_rank_r) begin
write_this_rank = 1'b0;
for (i = 0; i < nBANK_MACHS; i = i + 1)
write_this_rank =
write_this_rank || (sending_col[i] && wr_this_rank_r[(i*RANKS)+ID]);
end
reg [WTR_CNT_WIDTH-1:0] wtr_cnt_r;
reg [WTR_CNT_WIDTH-1:0] wtr_cnt_ns;
always @(/*AS*/rst or write_this_rank or wtr_cnt_r)
if (rst) wtr_cnt_ns = {WTR_CNT_WIDTH{1'b0}};
else begin
wtr_cnt_ns = wtr_cnt_r;
if (write_this_rank) wtr_cnt_ns =
CASWR2CASRD_CLKS[WTR_CNT_WIDTH-1:0] - TWO[WTR_CNT_WIDTH-1:0];
else if (|wtr_cnt_r) wtr_cnt_ns = wtr_cnt_r - ONE[WTR_CNT_WIDTH-1:0];
end
wire inhbt_rd_ns = |wtr_cnt_ns;
wire wtr_inhbt_config_ns = wtr_cnt_ns >= TWO[WTR_CNT_WIDTH-1:0];
always @(posedge clk) wtr_cnt_r <= #TCQ wtr_cnt_ns;
always @(posedge clk) inhbt_rd_r <= #TCQ inhbt_rd_ns;
always @(posedge clk) wtr_inhbt_config_r <= #TCQ wtr_inhbt_config_ns;
end
endgenerate
// Refresh request generation. Implement a "refresh bank". Referred
// to as pullin-in refresh in the JEDEC spec.
// The refresh_rank_r counter increments when a refresh to this
// rank has been decoded. In the up direction, the count saturates
// at nREFRESH_BANK. As specified in the JEDEC spec, nREFRESH_BANK
// is normally eight. The counter decrements with each refresh_tick,
// saturating at zero. A refresh will be requests when the rank is
// not busy and refresh_rank_r != nREFRESH_BANK, or refresh_rank_r
// equals zero.
localparam REFRESH_BANK_WIDTH = clogb2(nREFRESH_BANK + 1);
input app_ref_req;
input dfi_init_complete;
input [(RANKS*nBANK_MACHS)-1:0] rank_busy_r;
input refresh_tick;
input insert_maint_r1;
input maint_zq_r;
input [RANK_WIDTH-1:0] maint_rank_r;
output wire refresh_request;
generate begin : refresh_generation
reg my_rank_busy;
always @(/*AS*/rank_busy_r) begin
my_rank_busy = 1'b0;
for (i=0; i < nBANK_MACHS; i=i+1)
my_rank_busy = my_rank_busy || rank_busy_r[(i*RANKS)+ID];
end
wire my_refresh =
insert_maint_r1 && ~maint_zq_r && (maint_rank_r == ID[RANK_WIDTH-1:0]);
reg [REFRESH_BANK_WIDTH-1:0] refresh_bank_r;
reg [REFRESH_BANK_WIDTH-1:0] refresh_bank_ns;
always @(/*AS*/app_ref_req or dfi_init_complete or my_refresh
or refresh_bank_r or refresh_tick)
if (~dfi_init_complete)
if (REFRESH_TIMER_DIV == 0)
refresh_bank_ns = nREFRESH_BANK[0+:REFRESH_BANK_WIDTH];
else refresh_bank_ns = {REFRESH_BANK_WIDTH{1'b0}};
else
case ({my_refresh, refresh_tick, app_ref_req})
3'b000, 3'b110, 3'b101, 3'b111 : refresh_bank_ns = refresh_bank_r;
3'b010, 3'b001, 3'b011 : refresh_bank_ns =
(|refresh_bank_r)?
refresh_bank_r - ONE[0+:REFRESH_BANK_WIDTH]:
refresh_bank_r;
3'b100 : refresh_bank_ns =
refresh_bank_r + ONE[0+:REFRESH_BANK_WIDTH];
endcase // case ({my_refresh, refresh_tick})
always @(posedge clk) refresh_bank_r <= #TCQ refresh_bank_ns;
`ifdef MC_SVA
refresh_bank_overflow: assert property (@(posedge clk)
(rst || (refresh_bank_r <= nREFRESH_BANK)));
refresh_bank_underflow: assert property (@(posedge clk)
(rst || ~(~|refresh_bank_r && ~my_refresh && refresh_tick)));
refresh_hi_priority: cover property (@(posedge clk)
(rst && ~|refresh_bank_ns && (refresh_bank_r ==
ONE[0+:REFRESH_BANK_WIDTH])));
refresh_bank_full: cover property (@(posedge clk)
(rst && (refresh_bank_r ==
nREFRESH_BANK[0+:REFRESH_BANK_WIDTH])));
`endif
assign refresh_request = dfi_init_complete &&
(~|refresh_bank_r ||
((refresh_bank_r != nREFRESH_BANK[0+:REFRESH_BANK_WIDTH]) && ~my_rank_busy));
end
endgenerate
// Periodic read request generation.
localparam PERIODIC_RD_TIMER_WIDTH = clogb2(PERIODIC_RD_TIMER_DIV + /*idle state*/ 1);
input app_periodic_rd_req;
input maint_prescaler_tick_r;
output periodic_rd_request;
input clear_periodic_rd_request;
input [RANK_BM_BV_WIDTH-1:0] rd_this_rank_r;
generate begin : periodic_rd_generation
if ( PHASE_DETECT != "OFF" ) begin //to enable periodic reads
reg read_this_rank;
always @(/*AS*/rd_this_rank_r or sending_col) begin
read_this_rank = 1'b0;
for (i = 0; i < nBANK_MACHS; i = i + 1)
read_this_rank =
read_this_rank || (sending_col[i] && rd_this_rank_r[(i*RANKS)+ID]);
end
reg [PERIODIC_RD_TIMER_WIDTH-1:0] periodic_rd_timer_r;
reg [PERIODIC_RD_TIMER_WIDTH-1:0] periodic_rd_timer_ns;
always @(/*AS*/dfi_init_complete or maint_prescaler_tick_r
or periodic_rd_timer_r or read_this_rank) begin
periodic_rd_timer_ns = periodic_rd_timer_r;
if (~dfi_init_complete)
periodic_rd_timer_ns = {PERIODIC_RD_TIMER_WIDTH{1'b0}};
else if (read_this_rank)
periodic_rd_timer_ns =
PERIODIC_RD_TIMER_DIV[0+:PERIODIC_RD_TIMER_WIDTH];
else if (|periodic_rd_timer_r && maint_prescaler_tick_r)
periodic_rd_timer_ns =
periodic_rd_timer_r - ONE[0+:PERIODIC_RD_TIMER_WIDTH];
end
always @(posedge clk) periodic_rd_timer_r <= #TCQ periodic_rd_timer_ns;
wire periodic_rd_timer_one = maint_prescaler_tick_r &&
(periodic_rd_timer_r == ONE[0+:PERIODIC_RD_TIMER_WIDTH]);
reg periodic_rd_request_r;
wire periodic_rd_request_ns = ~rst &&
((app_periodic_rd_req && dfi_init_complete) ||
((PERIODIC_RD_TIMER_DIV != 0) && ~dfi_init_complete) ||
(~(read_this_rank || clear_periodic_rd_request) &&
(periodic_rd_request_r || periodic_rd_timer_one)));
always @(posedge clk) periodic_rd_request_r <=
#TCQ periodic_rd_request_ns;
`ifdef MC_SVA
read_clears_periodic_rd_request: cover property (@(posedge clk)
(rst && (periodic_rd_request_r && read_this_rank)));
`endif
assign periodic_rd_request = dfi_init_complete && periodic_rd_request_r;
end else
assign periodic_rd_request = 1'b0; //to disable periodic reads
end
endgenerate
endmodule
|
/******************************************************************************
-- (c) Copyright 2006 - 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
*****************************************************************************
*
* Filename: blk_mem_gen_v8_3_3.v
*
* Description:
* This file is the Verilog behvarial model for the
* Block Memory Generator Core.
*
*****************************************************************************
* Author: Xilinx
*
* History: Jan 11, 2006 Initial revision
* Jun 11, 2007 Added independent register stages for
* Port A and Port B (IP1_Jm/v2.5)
* Aug 28, 2007 Added mux pipeline stages feature (IP2_Jm/v2.6)
* Mar 13, 2008 Behavioral model optimizations
* April 07, 2009 : Added support for Spartan-6 and Virtex-6
* features, including the following:
* (i) error injection, detection and/or correction
* (ii) reset priority
* (iii) special reset behavior
*
*****************************************************************************/
`timescale 1ps/1ps
module STATE_LOGIC_v8_3 (O, I0, I1, I2, I3, I4, I5);
parameter INIT = 64'h0000000000000000;
input I0, I1, I2, I3, I4, I5;
output O;
reg O;
reg tmp;
always @( I5 or I4 or I3 or I2 or I1 or I0 ) begin
tmp = I0 ^ I1 ^ I2 ^ I3 ^ I4 ^ I5;
if ( tmp == 0 || tmp == 1)
O = INIT[{I5, I4, I3, I2, I1, I0}];
end
endmodule
module beh_vlog_muxf7_v8_3 (O, I0, I1, S);
output O;
reg O;
input I0, I1, S;
always @(I0 or I1 or S)
if (S)
O = I1;
else
O = I0;
endmodule
module beh_vlog_ff_clr_v8_3 (Q, C, CLR, D);
parameter INIT = 0;
localparam FLOP_DELAY = 100;
output Q;
input C, CLR, D;
reg Q;
initial Q= 1'b0;
always @(posedge C )
if (CLR)
Q<= 1'b0;
else
Q<= #FLOP_DELAY D;
endmodule
module beh_vlog_ff_pre_v8_3 (Q, C, D, PRE);
parameter INIT = 0;
localparam FLOP_DELAY = 100;
output Q;
input C, D, PRE;
reg Q;
initial Q= 1'b0;
always @(posedge C )
if (PRE)
Q <= 1'b1;
else
Q <= #FLOP_DELAY D;
endmodule
module beh_vlog_ff_ce_clr_v8_3 (Q, C, CE, CLR, D);
parameter INIT = 0;
localparam FLOP_DELAY = 100;
output Q;
input C, CE, CLR, D;
reg Q;
initial Q= 1'b0;
always @(posedge C )
if (CLR)
Q <= 1'b0;
else if (CE)
Q <= #FLOP_DELAY D;
endmodule
module write_netlist_v8_3
#(
parameter C_AXI_TYPE = 0
)
(
S_ACLK, S_ARESETN, S_AXI_AWVALID, S_AXI_WVALID, S_AXI_BREADY,
w_last_c, bready_timeout_c, aw_ready_r, S_AXI_WREADY, S_AXI_BVALID,
S_AXI_WR_EN, addr_en_c, incr_addr_c, bvalid_c
);
input S_ACLK;
input S_ARESETN;
input S_AXI_AWVALID;
input S_AXI_WVALID;
input S_AXI_BREADY;
input w_last_c;
input bready_timeout_c;
output aw_ready_r;
output S_AXI_WREADY;
output S_AXI_BVALID;
output S_AXI_WR_EN;
output addr_en_c;
output incr_addr_c;
output bvalid_c;
//-------------------------------------------------------------------------
//AXI LITE
//-------------------------------------------------------------------------
generate if (C_AXI_TYPE == 0 ) begin : gbeh_axi_lite_sm
wire w_ready_r_7;
wire w_ready_c;
wire aw_ready_c;
wire NlwRenamedSignal_bvalid_c;
wire NlwRenamedSignal_incr_addr_c;
wire present_state_FSM_FFd3_13;
wire present_state_FSM_FFd2_14;
wire present_state_FSM_FFd1_15;
wire present_state_FSM_FFd4_16;
wire present_state_FSM_FFd4_In;
wire present_state_FSM_FFd3_In;
wire present_state_FSM_FFd2_In;
wire present_state_FSM_FFd1_In;
wire present_state_FSM_FFd4_In1_21;
wire [0:0] Mmux_aw_ready_c ;
begin
assign
S_AXI_WREADY = w_ready_r_7,
S_AXI_BVALID = NlwRenamedSignal_incr_addr_c,
S_AXI_WR_EN = NlwRenamedSignal_bvalid_c,
incr_addr_c = NlwRenamedSignal_incr_addr_c,
bvalid_c = NlwRenamedSignal_bvalid_c;
assign NlwRenamedSignal_incr_addr_c = 1'b0;
beh_vlog_ff_clr_v8_3 #(
.INIT (1'b0))
aw_ready_r_2 (
.C ( S_ACLK),
.CLR ( S_ARESETN),
.D ( aw_ready_c),
.Q ( aw_ready_r)
);
beh_vlog_ff_clr_v8_3 #(
.INIT (1'b0))
w_ready_r (
.C ( S_ACLK),
.CLR ( S_ARESETN),
.D ( w_ready_c),
.Q ( w_ready_r_7)
);
beh_vlog_ff_pre_v8_3 #(
.INIT (1'b1))
present_state_FSM_FFd4 (
.C ( S_ACLK),
.D ( present_state_FSM_FFd4_In),
.PRE ( S_ARESETN),
.Q ( present_state_FSM_FFd4_16)
);
beh_vlog_ff_clr_v8_3 #(
.INIT (1'b0))
present_state_FSM_FFd3 (
.C ( S_ACLK),
.CLR ( S_ARESETN),
.D ( present_state_FSM_FFd3_In),
.Q ( present_state_FSM_FFd3_13)
);
beh_vlog_ff_clr_v8_3 #(
.INIT (1'b0))
present_state_FSM_FFd2 (
.C ( S_ACLK),
.CLR ( S_ARESETN),
.D ( present_state_FSM_FFd2_In),
.Q ( present_state_FSM_FFd2_14)
);
beh_vlog_ff_clr_v8_3 #(
.INIT (1'b0))
present_state_FSM_FFd1 (
.C ( S_ACLK),
.CLR ( S_ARESETN),
.D ( present_state_FSM_FFd1_In),
.Q ( present_state_FSM_FFd1_15)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h0000000055554440))
present_state_FSM_FFd3_In1 (
.I0 ( S_AXI_WVALID),
.I1 ( S_AXI_AWVALID),
.I2 ( present_state_FSM_FFd2_14),
.I3 ( present_state_FSM_FFd4_16),
.I4 ( present_state_FSM_FFd3_13),
.I5 (1'b0),
.O ( present_state_FSM_FFd3_In)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h0000000088880800))
present_state_FSM_FFd2_In1 (
.I0 ( S_AXI_AWVALID),
.I1 ( S_AXI_WVALID),
.I2 ( bready_timeout_c),
.I3 ( present_state_FSM_FFd2_14),
.I4 ( present_state_FSM_FFd4_16),
.I5 (1'b0),
.O ( present_state_FSM_FFd2_In)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h00000000AAAA2000))
Mmux_addr_en_c_0_1 (
.I0 ( S_AXI_AWVALID),
.I1 ( bready_timeout_c),
.I2 ( present_state_FSM_FFd2_14),
.I3 ( S_AXI_WVALID),
.I4 ( present_state_FSM_FFd4_16),
.I5 (1'b0),
.O ( addr_en_c)
);
STATE_LOGIC_v8_3 #(
.INIT (64'hF5F07570F5F05500))
Mmux_w_ready_c_0_1 (
.I0 ( S_AXI_WVALID),
.I1 ( bready_timeout_c),
.I2 ( S_AXI_AWVALID),
.I3 ( present_state_FSM_FFd3_13),
.I4 ( present_state_FSM_FFd4_16),
.I5 ( present_state_FSM_FFd2_14),
.O ( w_ready_c)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h88808880FFFF8880))
present_state_FSM_FFd1_In1 (
.I0 ( S_AXI_WVALID),
.I1 ( bready_timeout_c),
.I2 ( present_state_FSM_FFd3_13),
.I3 ( present_state_FSM_FFd2_14),
.I4 ( present_state_FSM_FFd1_15),
.I5 ( S_AXI_BREADY),
.O ( present_state_FSM_FFd1_In)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h00000000000000A8))
Mmux_S_AXI_WR_EN_0_1 (
.I0 ( S_AXI_WVALID),
.I1 ( present_state_FSM_FFd2_14),
.I2 ( present_state_FSM_FFd3_13),
.I3 (1'b0),
.I4 (1'b0),
.I5 (1'b0),
.O ( NlwRenamedSignal_bvalid_c)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h2F0F27072F0F2200))
present_state_FSM_FFd4_In1 (
.I0 ( S_AXI_WVALID),
.I1 ( bready_timeout_c),
.I2 ( S_AXI_AWVALID),
.I3 ( present_state_FSM_FFd3_13),
.I4 ( present_state_FSM_FFd4_16),
.I5 ( present_state_FSM_FFd2_14),
.O ( present_state_FSM_FFd4_In1_21)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h00000000000000F8))
present_state_FSM_FFd4_In2 (
.I0 ( present_state_FSM_FFd1_15),
.I1 ( S_AXI_BREADY),
.I2 ( present_state_FSM_FFd4_In1_21),
.I3 (1'b0),
.I4 (1'b0),
.I5 (1'b0),
.O ( present_state_FSM_FFd4_In)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h7535753575305500))
Mmux_aw_ready_c_0_1 (
.I0 ( S_AXI_AWVALID),
.I1 ( bready_timeout_c),
.I2 ( S_AXI_WVALID),
.I3 ( present_state_FSM_FFd4_16),
.I4 ( present_state_FSM_FFd3_13),
.I5 ( present_state_FSM_FFd2_14),
.O ( Mmux_aw_ready_c[0])
);
STATE_LOGIC_v8_3 #(
.INIT (64'h00000000000000F8))
Mmux_aw_ready_c_0_2 (
.I0 ( present_state_FSM_FFd1_15),
.I1 ( S_AXI_BREADY),
.I2 ( Mmux_aw_ready_c[0]),
.I3 (1'b0),
.I4 (1'b0),
.I5 (1'b0),
.O ( aw_ready_c)
);
end
end
endgenerate
//---------------------------------------------------------------------
// AXI FULL
//---------------------------------------------------------------------
generate if (C_AXI_TYPE == 1 ) begin : gbeh_axi_full_sm
wire w_ready_r_8;
wire w_ready_c;
wire aw_ready_c;
wire NlwRenamedSig_OI_bvalid_c;
wire present_state_FSM_FFd1_16;
wire present_state_FSM_FFd4_17;
wire present_state_FSM_FFd3_18;
wire present_state_FSM_FFd2_19;
wire present_state_FSM_FFd4_In;
wire present_state_FSM_FFd3_In;
wire present_state_FSM_FFd2_In;
wire present_state_FSM_FFd1_In;
wire present_state_FSM_FFd2_In1_24;
wire present_state_FSM_FFd4_In1_25;
wire N2;
wire N4;
begin
assign
S_AXI_WREADY = w_ready_r_8,
bvalid_c = NlwRenamedSig_OI_bvalid_c,
S_AXI_BVALID = 1'b0;
beh_vlog_ff_clr_v8_3 #(
.INIT (1'b0))
aw_ready_r_2
(
.C ( S_ACLK),
.CLR ( S_ARESETN),
.D ( aw_ready_c),
.Q ( aw_ready_r)
);
beh_vlog_ff_clr_v8_3 #(
.INIT (1'b0))
w_ready_r
(
.C ( S_ACLK),
.CLR ( S_ARESETN),
.D ( w_ready_c),
.Q ( w_ready_r_8)
);
beh_vlog_ff_pre_v8_3 #(
.INIT (1'b1))
present_state_FSM_FFd4
(
.C ( S_ACLK),
.D ( present_state_FSM_FFd4_In),
.PRE ( S_ARESETN),
.Q ( present_state_FSM_FFd4_17)
);
beh_vlog_ff_clr_v8_3 #(
.INIT (1'b0))
present_state_FSM_FFd3
(
.C ( S_ACLK),
.CLR ( S_ARESETN),
.D ( present_state_FSM_FFd3_In),
.Q ( present_state_FSM_FFd3_18)
);
beh_vlog_ff_clr_v8_3 #(
.INIT (1'b0))
present_state_FSM_FFd2
(
.C ( S_ACLK),
.CLR ( S_ARESETN),
.D ( present_state_FSM_FFd2_In),
.Q ( present_state_FSM_FFd2_19)
);
beh_vlog_ff_clr_v8_3 #(
.INIT (1'b0))
present_state_FSM_FFd1
(
.C ( S_ACLK),
.CLR ( S_ARESETN),
.D ( present_state_FSM_FFd1_In),
.Q ( present_state_FSM_FFd1_16)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h0000000000005540))
present_state_FSM_FFd3_In1
(
.I0 ( S_AXI_WVALID),
.I1 ( present_state_FSM_FFd4_17),
.I2 ( S_AXI_AWVALID),
.I3 ( present_state_FSM_FFd3_18),
.I4 (1'b0),
.I5 (1'b0),
.O ( present_state_FSM_FFd3_In)
);
STATE_LOGIC_v8_3 #(
.INIT (64'hBF3FBB33AF0FAA00))
Mmux_aw_ready_c_0_2
(
.I0 ( S_AXI_BREADY),
.I1 ( bready_timeout_c),
.I2 ( S_AXI_AWVALID),
.I3 ( present_state_FSM_FFd1_16),
.I4 ( present_state_FSM_FFd4_17),
.I5 ( NlwRenamedSig_OI_bvalid_c),
.O ( aw_ready_c)
);
STATE_LOGIC_v8_3 #(
.INIT (64'hAAAAAAAA20000000))
Mmux_addr_en_c_0_1
(
.I0 ( S_AXI_AWVALID),
.I1 ( bready_timeout_c),
.I2 ( present_state_FSM_FFd2_19),
.I3 ( S_AXI_WVALID),
.I4 ( w_last_c),
.I5 ( present_state_FSM_FFd4_17),
.O ( addr_en_c)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h00000000000000A8))
Mmux_S_AXI_WR_EN_0_1
(
.I0 ( S_AXI_WVALID),
.I1 ( present_state_FSM_FFd2_19),
.I2 ( present_state_FSM_FFd3_18),
.I3 (1'b0),
.I4 (1'b0),
.I5 (1'b0),
.O ( S_AXI_WR_EN)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h0000000000002220))
Mmux_incr_addr_c_0_1
(
.I0 ( S_AXI_WVALID),
.I1 ( w_last_c),
.I2 ( present_state_FSM_FFd2_19),
.I3 ( present_state_FSM_FFd3_18),
.I4 (1'b0),
.I5 (1'b0),
.O ( incr_addr_c)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h0000000000008880))
Mmux_aw_ready_c_0_11
(
.I0 ( S_AXI_WVALID),
.I1 ( w_last_c),
.I2 ( present_state_FSM_FFd2_19),
.I3 ( present_state_FSM_FFd3_18),
.I4 (1'b0),
.I5 (1'b0),
.O ( NlwRenamedSig_OI_bvalid_c)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h000000000000D5C0))
present_state_FSM_FFd2_In1
(
.I0 ( w_last_c),
.I1 ( S_AXI_AWVALID),
.I2 ( present_state_FSM_FFd4_17),
.I3 ( present_state_FSM_FFd3_18),
.I4 (1'b0),
.I5 (1'b0),
.O ( present_state_FSM_FFd2_In1_24)
);
STATE_LOGIC_v8_3 #(
.INIT (64'hFFFFAAAA08AAAAAA))
present_state_FSM_FFd2_In2
(
.I0 ( present_state_FSM_FFd2_19),
.I1 ( S_AXI_AWVALID),
.I2 ( bready_timeout_c),
.I3 ( w_last_c),
.I4 ( S_AXI_WVALID),
.I5 ( present_state_FSM_FFd2_In1_24),
.O ( present_state_FSM_FFd2_In)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h00C0004000C00000))
present_state_FSM_FFd4_In1
(
.I0 ( S_AXI_AWVALID),
.I1 ( w_last_c),
.I2 ( S_AXI_WVALID),
.I3 ( bready_timeout_c),
.I4 ( present_state_FSM_FFd3_18),
.I5 ( present_state_FSM_FFd2_19),
.O ( present_state_FSM_FFd4_In1_25)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h00000000FFFF88F8))
present_state_FSM_FFd4_In2
(
.I0 ( present_state_FSM_FFd1_16),
.I1 ( S_AXI_BREADY),
.I2 ( present_state_FSM_FFd4_17),
.I3 ( S_AXI_AWVALID),
.I4 ( present_state_FSM_FFd4_In1_25),
.I5 (1'b0),
.O ( present_state_FSM_FFd4_In)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h0000000000000007))
Mmux_w_ready_c_0_SW0
(
.I0 ( w_last_c),
.I1 ( S_AXI_WVALID),
.I2 (1'b0),
.I3 (1'b0),
.I4 (1'b0),
.I5 (1'b0),
.O ( N2)
);
STATE_LOGIC_v8_3 #(
.INIT (64'hFABAFABAFAAAF000))
Mmux_w_ready_c_0_Q
(
.I0 ( N2),
.I1 ( bready_timeout_c),
.I2 ( S_AXI_AWVALID),
.I3 ( present_state_FSM_FFd4_17),
.I4 ( present_state_FSM_FFd3_18),
.I5 ( present_state_FSM_FFd2_19),
.O ( w_ready_c)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h0000000000000008))
Mmux_aw_ready_c_0_11_SW0
(
.I0 ( bready_timeout_c),
.I1 ( S_AXI_WVALID),
.I2 (1'b0),
.I3 (1'b0),
.I4 (1'b0),
.I5 (1'b0),
.O ( N4)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h88808880FFFF8880))
present_state_FSM_FFd1_In1
(
.I0 ( w_last_c),
.I1 ( N4),
.I2 ( present_state_FSM_FFd2_19),
.I3 ( present_state_FSM_FFd3_18),
.I4 ( present_state_FSM_FFd1_16),
.I5 ( S_AXI_BREADY),
.O ( present_state_FSM_FFd1_In)
);
end
end
endgenerate
endmodule
module read_netlist_v8_3 #(
parameter C_AXI_TYPE = 1,
parameter C_ADDRB_WIDTH = 12
) ( S_AXI_R_LAST_INT, S_ACLK, S_ARESETN, S_AXI_ARVALID,
S_AXI_RREADY,S_AXI_INCR_ADDR,S_AXI_ADDR_EN,
S_AXI_SINGLE_TRANS,S_AXI_MUX_SEL, S_AXI_R_LAST, S_AXI_ARREADY,
S_AXI_RLAST, S_AXI_RVALID, S_AXI_RD_EN, S_AXI_ARLEN);
input S_AXI_R_LAST_INT;
input S_ACLK;
input S_ARESETN;
input S_AXI_ARVALID;
input S_AXI_RREADY;
output S_AXI_INCR_ADDR;
output S_AXI_ADDR_EN;
output S_AXI_SINGLE_TRANS;
output S_AXI_MUX_SEL;
output S_AXI_R_LAST;
output S_AXI_ARREADY;
output S_AXI_RLAST;
output S_AXI_RVALID;
output S_AXI_RD_EN;
input [7:0] S_AXI_ARLEN;
wire present_state_FSM_FFd1_13 ;
wire present_state_FSM_FFd2_14 ;
wire gaxi_full_sm_outstanding_read_r_15 ;
wire gaxi_full_sm_ar_ready_r_16 ;
wire gaxi_full_sm_r_last_r_17 ;
wire NlwRenamedSig_OI_gaxi_full_sm_r_valid_r ;
wire gaxi_full_sm_r_valid_c ;
wire S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o ;
wire gaxi_full_sm_ar_ready_c ;
wire gaxi_full_sm_outstanding_read_c ;
wire NlwRenamedSig_OI_S_AXI_R_LAST ;
wire S_AXI_ARLEN_7_GND_8_o_equal_1_o ;
wire present_state_FSM_FFd2_In ;
wire present_state_FSM_FFd1_In ;
wire Mmux_S_AXI_R_LAST13 ;
wire N01 ;
wire N2 ;
wire Mmux_gaxi_full_sm_ar_ready_c11 ;
wire N4 ;
wire N8 ;
wire N9 ;
wire N10 ;
wire N11 ;
wire N12 ;
wire N13 ;
assign
S_AXI_R_LAST = NlwRenamedSig_OI_S_AXI_R_LAST,
S_AXI_ARREADY = gaxi_full_sm_ar_ready_r_16,
S_AXI_RLAST = gaxi_full_sm_r_last_r_17,
S_AXI_RVALID = NlwRenamedSig_OI_gaxi_full_sm_r_valid_r;
beh_vlog_ff_clr_v8_3 #(
.INIT (1'b0))
gaxi_full_sm_outstanding_read_r (
.C (S_ACLK),
.CLR(S_ARESETN),
.D(gaxi_full_sm_outstanding_read_c),
.Q(gaxi_full_sm_outstanding_read_r_15)
);
beh_vlog_ff_ce_clr_v8_3 #(
.INIT (1'b0))
gaxi_full_sm_r_valid_r (
.C (S_ACLK),
.CE (S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o),
.CLR (S_ARESETN),
.D (gaxi_full_sm_r_valid_c),
.Q (NlwRenamedSig_OI_gaxi_full_sm_r_valid_r)
);
beh_vlog_ff_clr_v8_3 #(
.INIT (1'b0))
gaxi_full_sm_ar_ready_r (
.C (S_ACLK),
.CLR (S_ARESETN),
.D (gaxi_full_sm_ar_ready_c),
.Q (gaxi_full_sm_ar_ready_r_16)
);
beh_vlog_ff_ce_clr_v8_3 #(
.INIT(1'b0))
gaxi_full_sm_r_last_r (
.C (S_ACLK),
.CE (S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o),
.CLR (S_ARESETN),
.D (NlwRenamedSig_OI_S_AXI_R_LAST),
.Q (gaxi_full_sm_r_last_r_17)
);
beh_vlog_ff_clr_v8_3 #(
.INIT (1'b0))
present_state_FSM_FFd2 (
.C ( S_ACLK),
.CLR ( S_ARESETN),
.D ( present_state_FSM_FFd2_In),
.Q ( present_state_FSM_FFd2_14)
);
beh_vlog_ff_clr_v8_3 #(
.INIT (1'b0))
present_state_FSM_FFd1 (
.C (S_ACLK),
.CLR (S_ARESETN),
.D (present_state_FSM_FFd1_In),
.Q (present_state_FSM_FFd1_13)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h000000000000000B))
S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o1 (
.I0 ( S_AXI_RREADY),
.I1 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I2 (1'b0),
.I3 (1'b0),
.I4 (1'b0),
.I5 (1'b0),
.O (S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h0000000000000008))
Mmux_S_AXI_SINGLE_TRANS11 (
.I0 (S_AXI_ARVALID),
.I1 (S_AXI_ARLEN_7_GND_8_o_equal_1_o),
.I2 (1'b0),
.I3 (1'b0),
.I4 (1'b0),
.I5 (1'b0),
.O (S_AXI_SINGLE_TRANS)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h0000000000000004))
Mmux_S_AXI_ADDR_EN11 (
.I0 (present_state_FSM_FFd1_13),
.I1 (S_AXI_ARVALID),
.I2 (1'b0),
.I3 (1'b0),
.I4 (1'b0),
.I5 (1'b0),
.O (S_AXI_ADDR_EN)
);
STATE_LOGIC_v8_3 #(
.INIT (64'hECEE2022EEEE2022))
present_state_FSM_FFd2_In1 (
.I0 ( S_AXI_ARVALID),
.I1 ( present_state_FSM_FFd1_13),
.I2 ( S_AXI_RREADY),
.I3 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),
.I4 ( present_state_FSM_FFd2_14),
.I5 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.O ( present_state_FSM_FFd2_In)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h0000000044440444))
Mmux_S_AXI_R_LAST131 (
.I0 ( present_state_FSM_FFd1_13),
.I1 ( S_AXI_ARVALID),
.I2 ( present_state_FSM_FFd2_14),
.I3 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I4 ( S_AXI_RREADY),
.I5 (1'b0),
.O ( Mmux_S_AXI_R_LAST13)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h4000FFFF40004000))
Mmux_S_AXI_INCR_ADDR11 (
.I0 ( S_AXI_R_LAST_INT),
.I1 ( S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o),
.I2 ( present_state_FSM_FFd2_14),
.I3 ( present_state_FSM_FFd1_13),
.I4 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),
.I5 ( Mmux_S_AXI_R_LAST13),
.O ( S_AXI_INCR_ADDR)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h00000000000000FE))
S_AXI_ARLEN_7_GND_8_o_equal_1_o_7_SW0 (
.I0 ( S_AXI_ARLEN[2]),
.I1 ( S_AXI_ARLEN[1]),
.I2 ( S_AXI_ARLEN[0]),
.I3 ( 1'b0),
.I4 ( 1'b0),
.I5 ( 1'b0),
.O ( N01)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h0000000000000001))
S_AXI_ARLEN_7_GND_8_o_equal_1_o_7_Q (
.I0 ( S_AXI_ARLEN[7]),
.I1 ( S_AXI_ARLEN[6]),
.I2 ( S_AXI_ARLEN[5]),
.I3 ( S_AXI_ARLEN[4]),
.I4 ( S_AXI_ARLEN[3]),
.I5 ( N01),
.O ( S_AXI_ARLEN_7_GND_8_o_equal_1_o)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h0000000000000007))
Mmux_gaxi_full_sm_outstanding_read_c1_SW0 (
.I0 ( S_AXI_ARVALID),
.I1 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),
.I2 ( 1'b0),
.I3 ( 1'b0),
.I4 ( 1'b0),
.I5 ( 1'b0),
.O ( N2)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h0020000002200200))
Mmux_gaxi_full_sm_outstanding_read_c1 (
.I0 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I1 ( S_AXI_RREADY),
.I2 ( present_state_FSM_FFd1_13),
.I3 ( present_state_FSM_FFd2_14),
.I4 ( gaxi_full_sm_outstanding_read_r_15),
.I5 ( N2),
.O ( gaxi_full_sm_outstanding_read_c)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h0000000000004555))
Mmux_gaxi_full_sm_ar_ready_c12 (
.I0 ( S_AXI_ARVALID),
.I1 ( S_AXI_RREADY),
.I2 ( present_state_FSM_FFd2_14),
.I3 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I4 ( 1'b0),
.I5 ( 1'b0),
.O ( Mmux_gaxi_full_sm_ar_ready_c11)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h00000000000000EF))
Mmux_S_AXI_R_LAST11_SW0 (
.I0 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),
.I1 ( S_AXI_RREADY),
.I2 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I3 ( 1'b0),
.I4 ( 1'b0),
.I5 ( 1'b0),
.O ( N4)
);
STATE_LOGIC_v8_3 #(
.INIT (64'hFCAAFC0A00AA000A))
Mmux_S_AXI_R_LAST11 (
.I0 ( S_AXI_ARVALID),
.I1 ( gaxi_full_sm_outstanding_read_r_15),
.I2 ( present_state_FSM_FFd2_14),
.I3 ( present_state_FSM_FFd1_13),
.I4 ( N4),
.I5 ( S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o),
.O ( gaxi_full_sm_r_valid_c)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h00000000AAAAAA08))
S_AXI_MUX_SEL1 (
.I0 (present_state_FSM_FFd1_13),
.I1 (NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I2 (S_AXI_RREADY),
.I3 (present_state_FSM_FFd2_14),
.I4 (gaxi_full_sm_outstanding_read_r_15),
.I5 (1'b0),
.O (S_AXI_MUX_SEL)
);
STATE_LOGIC_v8_3 #(
.INIT (64'hF3F3F755A2A2A200))
Mmux_S_AXI_RD_EN11 (
.I0 ( present_state_FSM_FFd1_13),
.I1 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I2 ( S_AXI_RREADY),
.I3 ( gaxi_full_sm_outstanding_read_r_15),
.I4 ( present_state_FSM_FFd2_14),
.I5 ( S_AXI_ARVALID),
.O ( S_AXI_RD_EN)
);
beh_vlog_muxf7_v8_3 present_state_FSM_FFd1_In3 (
.I0 ( N8),
.I1 ( N9),
.S ( present_state_FSM_FFd1_13),
.O ( present_state_FSM_FFd1_In)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h000000005410F4F0))
present_state_FSM_FFd1_In3_F (
.I0 ( S_AXI_RREADY),
.I1 ( present_state_FSM_FFd2_14),
.I2 ( S_AXI_ARVALID),
.I3 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I4 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),
.I5 ( 1'b0),
.O ( N8)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h0000000072FF7272))
present_state_FSM_FFd1_In3_G (
.I0 ( present_state_FSM_FFd2_14),
.I1 ( S_AXI_R_LAST_INT),
.I2 ( gaxi_full_sm_outstanding_read_r_15),
.I3 ( S_AXI_RREADY),
.I4 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I5 ( 1'b0),
.O ( N9)
);
beh_vlog_muxf7_v8_3 Mmux_gaxi_full_sm_ar_ready_c14 (
.I0 ( N10),
.I1 ( N11),
.S ( present_state_FSM_FFd1_13),
.O ( gaxi_full_sm_ar_ready_c)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h00000000FFFF88A8))
Mmux_gaxi_full_sm_ar_ready_c14_F (
.I0 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),
.I1 ( S_AXI_RREADY),
.I2 ( present_state_FSM_FFd2_14),
.I3 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I4 ( Mmux_gaxi_full_sm_ar_ready_c11),
.I5 ( 1'b0),
.O ( N10)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h000000008D008D8D))
Mmux_gaxi_full_sm_ar_ready_c14_G (
.I0 ( present_state_FSM_FFd2_14),
.I1 ( S_AXI_R_LAST_INT),
.I2 ( gaxi_full_sm_outstanding_read_r_15),
.I3 ( S_AXI_RREADY),
.I4 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I5 ( 1'b0),
.O ( N11)
);
beh_vlog_muxf7_v8_3 Mmux_S_AXI_R_LAST1 (
.I0 ( N12),
.I1 ( N13),
.S ( present_state_FSM_FFd1_13),
.O ( NlwRenamedSig_OI_S_AXI_R_LAST)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h0000000088088888))
Mmux_S_AXI_R_LAST1_F (
.I0 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),
.I1 ( S_AXI_ARVALID),
.I2 ( present_state_FSM_FFd2_14),
.I3 ( S_AXI_RREADY),
.I4 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I5 ( 1'b0),
.O ( N12)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h00000000E400E4E4))
Mmux_S_AXI_R_LAST1_G (
.I0 ( present_state_FSM_FFd2_14),
.I1 ( gaxi_full_sm_outstanding_read_r_15),
.I2 ( S_AXI_R_LAST_INT),
.I3 ( S_AXI_RREADY),
.I4 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I5 ( 1'b0),
.O ( N13)
);
endmodule
module blk_mem_axi_write_wrapper_beh_v8_3
# (
// AXI Interface related parameters start here
parameter C_INTERFACE_TYPE = 0, // 0: Native Interface; 1: AXI Interface
parameter C_AXI_TYPE = 0, // 0: AXI Lite; 1: AXI Full;
parameter C_AXI_SLAVE_TYPE = 0, // 0: MEMORY SLAVE; 1: PERIPHERAL SLAVE;
parameter C_MEMORY_TYPE = 0, // 0: SP-RAM, 1: SDP-RAM; 2: TDP-RAM; 3: DP-ROM;
parameter C_WRITE_DEPTH_A = 0,
parameter C_AXI_AWADDR_WIDTH = 32,
parameter C_ADDRA_WIDTH = 12,
parameter C_AXI_WDATA_WIDTH = 32,
parameter C_HAS_AXI_ID = 0,
parameter C_AXI_ID_WIDTH = 4,
// AXI OUTSTANDING WRITES
parameter C_AXI_OS_WR = 2
)
(
// AXI Global Signals
input S_ACLK,
input S_ARESETN,
// AXI Full/Lite Slave Write Channel (write side)
input [C_AXI_ID_WIDTH-1:0] S_AXI_AWID,
input [C_AXI_AWADDR_WIDTH-1:0] S_AXI_AWADDR,
input [8-1:0] S_AXI_AWLEN,
input [2:0] S_AXI_AWSIZE,
input [1:0] S_AXI_AWBURST,
input S_AXI_AWVALID,
output S_AXI_AWREADY,
input S_AXI_WVALID,
output S_AXI_WREADY,
output reg [C_AXI_ID_WIDTH-1:0] S_AXI_BID = 0,
output S_AXI_BVALID,
input S_AXI_BREADY,
// Signals for BMG interface
output [C_ADDRA_WIDTH-1:0] S_AXI_AWADDR_OUT,
output S_AXI_WR_EN
);
localparam FLOP_DELAY = 100; // 100 ps
localparam C_RANGE = ((C_AXI_WDATA_WIDTH == 8)?0:
((C_AXI_WDATA_WIDTH==16)?1:
((C_AXI_WDATA_WIDTH==32)?2:
((C_AXI_WDATA_WIDTH==64)?3:
((C_AXI_WDATA_WIDTH==128)?4:
((C_AXI_WDATA_WIDTH==256)?5:0))))));
wire bvalid_c ;
reg bready_timeout_c = 0;
wire [1:0] bvalid_rd_cnt_c;
reg bvalid_r = 0;
reg [2:0] bvalid_count_r = 0;
reg [((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?
C_AXI_AWADDR_WIDTH:C_ADDRA_WIDTH)-1:0] awaddr_reg = 0;
reg [1:0] bvalid_wr_cnt_r = 0;
reg [1:0] bvalid_rd_cnt_r = 0;
wire w_last_c ;
wire addr_en_c ;
wire incr_addr_c ;
wire aw_ready_r ;
wire dec_alen_c ;
reg bvalid_d1_c = 0;
reg [7:0] awlen_cntr_r = 0;
reg [7:0] awlen_int = 0;
reg [1:0] awburst_int = 0;
integer total_bytes = 0;
integer wrap_boundary = 0;
integer wrap_base_addr = 0;
integer num_of_bytes_c = 0;
integer num_of_bytes_r = 0;
// Array to store BIDs
reg [C_AXI_ID_WIDTH-1:0] axi_bid_array[3:0] ;
wire S_AXI_BVALID_axi_wr_fsm;
//-------------------------------------
//AXI WRITE FSM COMPONENT INSTANTIATION
//-------------------------------------
write_netlist_v8_3 #(.C_AXI_TYPE(C_AXI_TYPE)) axi_wr_fsm
(
.S_ACLK(S_ACLK),
.S_ARESETN(S_ARESETN),
.S_AXI_AWVALID(S_AXI_AWVALID),
.aw_ready_r(aw_ready_r),
.S_AXI_WVALID(S_AXI_WVALID),
.S_AXI_WREADY(S_AXI_WREADY),
.S_AXI_BREADY(S_AXI_BREADY),
.S_AXI_WR_EN(S_AXI_WR_EN),
.w_last_c(w_last_c),
.bready_timeout_c(bready_timeout_c),
.addr_en_c(addr_en_c),
.incr_addr_c(incr_addr_c),
.bvalid_c(bvalid_c),
.S_AXI_BVALID (S_AXI_BVALID_axi_wr_fsm)
);
//Wrap Address boundary calculation
always@(*) begin
num_of_bytes_c = 2**((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_AWSIZE:0);
total_bytes = (num_of_bytes_r)*(awlen_int+1);
wrap_base_addr = ((awaddr_reg)/((total_bytes==0)?1:total_bytes))*(total_bytes);
wrap_boundary = wrap_base_addr+total_bytes;
end
//-------------------------------------------------------------------------
// BMG address generation
//-------------------------------------------------------------------------
always @(posedge S_ACLK or S_ARESETN) begin
if (S_ARESETN == 1'b1) begin
awaddr_reg <= 0;
num_of_bytes_r <= 0;
awburst_int <= 0;
end else begin
if (addr_en_c == 1'b1) begin
awaddr_reg <= #FLOP_DELAY S_AXI_AWADDR ;
num_of_bytes_r <= num_of_bytes_c;
awburst_int <= ((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_AWBURST:2'b01);
end else if (incr_addr_c == 1'b1) begin
if (awburst_int == 2'b10) begin
if(awaddr_reg == (wrap_boundary-num_of_bytes_r)) begin
awaddr_reg <= wrap_base_addr;
end else begin
awaddr_reg <= awaddr_reg + num_of_bytes_r;
end
end else if (awburst_int == 2'b01 || awburst_int == 2'b11) begin
awaddr_reg <= awaddr_reg + num_of_bytes_r;
end
end
end
end
assign S_AXI_AWADDR_OUT = ((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?
awaddr_reg[C_AXI_AWADDR_WIDTH-1:C_RANGE]:awaddr_reg);
//-------------------------------------------------------------------------
// AXI wlast generation
//-------------------------------------------------------------------------
always @(posedge S_ACLK or S_ARESETN) begin
if (S_ARESETN == 1'b1) begin
awlen_cntr_r <= 0;
awlen_int <= 0;
end else begin
if (addr_en_c == 1'b1) begin
awlen_int <= #FLOP_DELAY (C_AXI_TYPE == 0?0:S_AXI_AWLEN) ;
awlen_cntr_r <= #FLOP_DELAY (C_AXI_TYPE == 0?0:S_AXI_AWLEN) ;
end else if (dec_alen_c == 1'b1) begin
awlen_cntr_r <= #FLOP_DELAY awlen_cntr_r - 1 ;
end
end
end
assign w_last_c = (awlen_cntr_r == 0 && S_AXI_WVALID == 1'b1)?1'b1:1'b0;
assign dec_alen_c = (incr_addr_c | w_last_c);
//-------------------------------------------------------------------------
// Generation of bvalid counter for outstanding transactions
//-------------------------------------------------------------------------
always @(posedge S_ACLK or S_ARESETN) begin
if (S_ARESETN == 1'b1) begin
bvalid_count_r <= 0;
end else begin
// bvalid_count_r generation
if (bvalid_c == 1'b1 && bvalid_r == 1'b1 && S_AXI_BREADY == 1'b1) begin
bvalid_count_r <= #FLOP_DELAY bvalid_count_r ;
end else if (bvalid_c == 1'b1) begin
bvalid_count_r <= #FLOP_DELAY bvalid_count_r + 1 ;
end else if (bvalid_r == 1'b1 && S_AXI_BREADY == 1'b1 && bvalid_count_r != 0) begin
bvalid_count_r <= #FLOP_DELAY bvalid_count_r - 1 ;
end
end
end
//-------------------------------------------------------------------------
// Generation of bvalid when BID is used
//-------------------------------------------------------------------------
generate if (C_HAS_AXI_ID == 1) begin:gaxi_bvalid_id_r
always @(posedge S_ACLK or S_ARESETN) begin
if (S_ARESETN == 1'b1) begin
bvalid_r <= 0;
bvalid_d1_c <= 0;
end else begin
// Delay the generation o bvalid_r for generation for BID
bvalid_d1_c <= bvalid_c;
//external bvalid signal generation
if (bvalid_d1_c == 1'b1) begin
bvalid_r <= #FLOP_DELAY 1'b1 ;
end else if (bvalid_count_r <= 1 && S_AXI_BREADY == 1'b1) begin
bvalid_r <= #FLOP_DELAY 0 ;
end
end
end
end
endgenerate
//-------------------------------------------------------------------------
// Generation of bvalid when BID is not used
//-------------------------------------------------------------------------
generate if(C_HAS_AXI_ID == 0) begin:gaxi_bvalid_noid_r
always @(posedge S_ACLK or S_ARESETN) begin
if (S_ARESETN == 1'b1) begin
bvalid_r <= 0;
end else begin
//external bvalid signal generation
if (bvalid_c == 1'b1) begin
bvalid_r <= #FLOP_DELAY 1'b1 ;
end else if (bvalid_count_r <= 1 && S_AXI_BREADY == 1'b1) begin
bvalid_r <= #FLOP_DELAY 0 ;
end
end
end
end
endgenerate
//-------------------------------------------------------------------------
// Generation of Bready timeout
//-------------------------------------------------------------------------
always @(bvalid_count_r) begin
// bready_timeout_c generation
if(bvalid_count_r == C_AXI_OS_WR-1) begin
bready_timeout_c <= 1'b1;
end else begin
bready_timeout_c <= 1'b0;
end
end
//-------------------------------------------------------------------------
// Generation of BID
//-------------------------------------------------------------------------
generate if(C_HAS_AXI_ID == 1) begin:gaxi_bid_gen
always @(posedge S_ACLK or S_ARESETN) begin
if (S_ARESETN == 1'b1) begin
bvalid_wr_cnt_r <= 0;
bvalid_rd_cnt_r <= 0;
end else begin
// STORE AWID IN AN ARRAY
if(bvalid_c == 1'b1) begin
bvalid_wr_cnt_r <= bvalid_wr_cnt_r + 1;
end
// generate BID FROM AWID ARRAY
bvalid_rd_cnt_r <= #FLOP_DELAY bvalid_rd_cnt_c ;
S_AXI_BID <= axi_bid_array[bvalid_rd_cnt_c];
end
end
assign bvalid_rd_cnt_c = (bvalid_r == 1'b1 && S_AXI_BREADY == 1'b1)?bvalid_rd_cnt_r+1:bvalid_rd_cnt_r;
//-------------------------------------------------------------------------
// Storing AWID for generation of BID
//-------------------------------------------------------------------------
always @(posedge S_ACLK or S_ARESETN) begin
if(S_ARESETN == 1'b1) begin
axi_bid_array[0] = 0;
axi_bid_array[1] = 0;
axi_bid_array[2] = 0;
axi_bid_array[3] = 0;
end else if(aw_ready_r == 1'b1 && S_AXI_AWVALID == 1'b1) begin
axi_bid_array[bvalid_wr_cnt_r] <= S_AXI_AWID;
end
end
end
endgenerate
assign S_AXI_BVALID = bvalid_r;
assign S_AXI_AWREADY = aw_ready_r;
endmodule
module blk_mem_axi_read_wrapper_beh_v8_3
# (
//// AXI Interface related parameters start here
parameter C_INTERFACE_TYPE = 0,
parameter C_AXI_TYPE = 0,
parameter C_AXI_SLAVE_TYPE = 0,
parameter C_MEMORY_TYPE = 0,
parameter C_WRITE_WIDTH_A = 4,
parameter C_WRITE_DEPTH_A = 32,
parameter C_ADDRA_WIDTH = 12,
parameter C_AXI_PIPELINE_STAGES = 0,
parameter C_AXI_ARADDR_WIDTH = 12,
parameter C_HAS_AXI_ID = 0,
parameter C_AXI_ID_WIDTH = 4,
parameter C_ADDRB_WIDTH = 12
)
(
//// AXI Global Signals
input S_ACLK,
input S_ARESETN,
//// AXI Full/Lite Slave Read (Read side)
input [C_AXI_ARADDR_WIDTH-1:0] S_AXI_ARADDR,
input [7:0] S_AXI_ARLEN,
input [2:0] S_AXI_ARSIZE,
input [1:0] S_AXI_ARBURST,
input S_AXI_ARVALID,
output S_AXI_ARREADY,
output S_AXI_RLAST,
output S_AXI_RVALID,
input S_AXI_RREADY,
input [C_AXI_ID_WIDTH-1:0] S_AXI_ARID,
output reg [C_AXI_ID_WIDTH-1:0] S_AXI_RID = 0,
//// AXI Full/Lite Read Address Signals to BRAM
output [C_ADDRB_WIDTH-1:0] S_AXI_ARADDR_OUT,
output S_AXI_RD_EN
);
localparam FLOP_DELAY = 100; // 100 ps
localparam C_RANGE = ((C_WRITE_WIDTH_A == 8)?0:
((C_WRITE_WIDTH_A==16)?1:
((C_WRITE_WIDTH_A==32)?2:
((C_WRITE_WIDTH_A==64)?3:
((C_WRITE_WIDTH_A==128)?4:
((C_WRITE_WIDTH_A==256)?5:0))))));
reg [C_AXI_ID_WIDTH-1:0] ar_id_r=0;
wire addr_en_c;
wire rd_en_c;
wire incr_addr_c;
wire single_trans_c;
wire dec_alen_c;
wire mux_sel_c;
wire r_last_c;
wire r_last_int_c;
wire [C_ADDRB_WIDTH-1 : 0] araddr_out;
reg [7:0] arlen_int_r=0;
reg [7:0] arlen_cntr=8'h01;
reg [1:0] arburst_int_c=0;
reg [1:0] arburst_int_r=0;
reg [((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?
C_AXI_ARADDR_WIDTH:C_ADDRA_WIDTH)-1:0] araddr_reg =0;
integer num_of_bytes_c = 0;
integer total_bytes = 0;
integer num_of_bytes_r = 0;
integer wrap_base_addr_r = 0;
integer wrap_boundary_r = 0;
reg [7:0] arlen_int_c=0;
integer total_bytes_c = 0;
integer wrap_base_addr_c = 0;
integer wrap_boundary_c = 0;
assign dec_alen_c = incr_addr_c | r_last_int_c;
read_netlist_v8_3
#(.C_AXI_TYPE (1),
.C_ADDRB_WIDTH (C_ADDRB_WIDTH))
axi_read_fsm (
.S_AXI_INCR_ADDR(incr_addr_c),
.S_AXI_ADDR_EN(addr_en_c),
.S_AXI_SINGLE_TRANS(single_trans_c),
.S_AXI_MUX_SEL(mux_sel_c),
.S_AXI_R_LAST(r_last_c),
.S_AXI_R_LAST_INT(r_last_int_c),
//// AXI Global Signals
.S_ACLK(S_ACLK),
.S_ARESETN(S_ARESETN),
//// AXI Full/Lite Slave Read (Read side)
.S_AXI_ARLEN(S_AXI_ARLEN),
.S_AXI_ARVALID(S_AXI_ARVALID),
.S_AXI_ARREADY(S_AXI_ARREADY),
.S_AXI_RLAST(S_AXI_RLAST),
.S_AXI_RVALID(S_AXI_RVALID),
.S_AXI_RREADY(S_AXI_RREADY),
//// AXI Full/Lite Read Address Signals to BRAM
.S_AXI_RD_EN(rd_en_c)
);
always@(*) begin
num_of_bytes_c = 2**((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_ARSIZE:0);
total_bytes = (num_of_bytes_r)*(arlen_int_r+1);
wrap_base_addr_r = ((araddr_reg)/(total_bytes==0?1:total_bytes))*(total_bytes);
wrap_boundary_r = wrap_base_addr_r+total_bytes;
//////// combinatorial from interface
arlen_int_c = (C_AXI_TYPE == 0?0:S_AXI_ARLEN);
total_bytes_c = (num_of_bytes_c)*(arlen_int_c+1);
wrap_base_addr_c = ((S_AXI_ARADDR)/(total_bytes_c==0?1:total_bytes_c))*(total_bytes_c);
wrap_boundary_c = wrap_base_addr_c+total_bytes_c;
arburst_int_c = ((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_ARBURST:1);
end
////-------------------------------------------------------------------------
//// BMG address generation
////-------------------------------------------------------------------------
always @(posedge S_ACLK or S_ARESETN) begin
if (S_ARESETN == 1'b1) begin
araddr_reg <= 0;
arburst_int_r <= 0;
num_of_bytes_r <= 0;
end else begin
if (incr_addr_c == 1'b1 && addr_en_c == 1'b1 && single_trans_c == 1'b0) begin
arburst_int_r <= arburst_int_c;
num_of_bytes_r <= num_of_bytes_c;
if (arburst_int_c == 2'b10) begin
if(S_AXI_ARADDR == (wrap_boundary_c-num_of_bytes_c)) begin
araddr_reg <= wrap_base_addr_c;
end else begin
araddr_reg <= S_AXI_ARADDR + num_of_bytes_c;
end
end else if (arburst_int_c == 2'b01 || arburst_int_c == 2'b11) begin
araddr_reg <= S_AXI_ARADDR + num_of_bytes_c;
end
end else if (addr_en_c == 1'b1) begin
araddr_reg <= S_AXI_ARADDR;
num_of_bytes_r <= num_of_bytes_c;
arburst_int_r <= arburst_int_c;
end else if (incr_addr_c == 1'b1) begin
if (arburst_int_r == 2'b10) begin
if(araddr_reg == (wrap_boundary_r-num_of_bytes_r)) begin
araddr_reg <= wrap_base_addr_r;
end else begin
araddr_reg <= araddr_reg + num_of_bytes_r;
end
end else if (arburst_int_r == 2'b01 || arburst_int_r == 2'b11) begin
araddr_reg <= araddr_reg + num_of_bytes_r;
end
end
end
end
assign araddr_out = ((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?araddr_reg[C_AXI_ARADDR_WIDTH-1:C_RANGE]:araddr_reg);
////-----------------------------------------------------------------------
//// Counter to generate r_last_int_c from registered ARLEN - AXI FULL FSM
////-----------------------------------------------------------------------
always @(posedge S_ACLK or S_ARESETN) begin
if (S_ARESETN == 1'b1) begin
arlen_cntr <= 8'h01;
arlen_int_r <= 0;
end else begin
if (addr_en_c == 1'b1 && dec_alen_c == 1'b1 && single_trans_c == 1'b0) begin
arlen_int_r <= (C_AXI_TYPE == 0?0:S_AXI_ARLEN) ;
arlen_cntr <= S_AXI_ARLEN - 1'b1;
end else if (addr_en_c == 1'b1) begin
arlen_int_r <= (C_AXI_TYPE == 0?0:S_AXI_ARLEN) ;
arlen_cntr <= (C_AXI_TYPE == 0?0:S_AXI_ARLEN) ;
end else if (dec_alen_c == 1'b1) begin
arlen_cntr <= arlen_cntr - 1'b1 ;
end
else begin
arlen_cntr <= arlen_cntr;
end
end
end
assign r_last_int_c = (arlen_cntr == 0 && S_AXI_RREADY == 1'b1)?1'b1:1'b0;
////------------------------------------------------------------------------
//// AXI FULL FSM
//// Mux Selection of ARADDR
//// ARADDR is driven out from the read fsm based on the mux_sel_c
//// Based on mux_sel either ARADDR is given out or the latched ARADDR is
//// given out to BRAM
////------------------------------------------------------------------------
assign S_AXI_ARADDR_OUT = (mux_sel_c == 1'b0)?((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_ARADDR[C_AXI_ARADDR_WIDTH-1:C_RANGE]:S_AXI_ARADDR):araddr_out;
////------------------------------------------------------------------------
//// Assign output signals - AXI FULL FSM
////------------------------------------------------------------------------
assign S_AXI_RD_EN = rd_en_c;
generate if (C_HAS_AXI_ID == 1) begin:gaxi_bvalid_id_r
always @(posedge S_ACLK or S_ARESETN) begin
if (S_ARESETN == 1'b1) begin
S_AXI_RID <= 0;
ar_id_r <= 0;
end else begin
if (addr_en_c == 1'b1 && rd_en_c == 1'b1) begin
S_AXI_RID <= S_AXI_ARID;
ar_id_r <= S_AXI_ARID;
end else if (addr_en_c == 1'b1 && rd_en_c == 1'b0) begin
ar_id_r <= S_AXI_ARID;
end else if (rd_en_c == 1'b1) begin
S_AXI_RID <= ar_id_r;
end
end
end
end
endgenerate
endmodule
module blk_mem_axi_regs_fwd_v8_3
#(parameter C_DATA_WIDTH = 8
)(
input ACLK,
input ARESET,
input S_VALID,
output S_READY,
input [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA,
output M_VALID,
input M_READY,
output reg [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA
);
reg [C_DATA_WIDTH-1:0] STORAGE_DATA;
wire S_READY_I;
reg M_VALID_I;
reg [1:0] ARESET_D;
//assign local signal to its output signal
assign S_READY = S_READY_I;
assign M_VALID = M_VALID_I;
always @(posedge ACLK) begin
ARESET_D <= {ARESET_D[0], ARESET};
end
//Save payload data whenever we have a transaction on the slave side
always @(posedge ACLK or ARESET) begin
if (ARESET == 1'b1) begin
STORAGE_DATA <= 0;
end else begin
if(S_VALID == 1'b1 && S_READY_I == 1'b1 ) begin
STORAGE_DATA <= S_PAYLOAD_DATA;
end
end
end
always @(posedge ACLK) begin
M_PAYLOAD_DATA = STORAGE_DATA;
end
//M_Valid set to high when we have a completed transfer on slave side
//Is removed on a M_READY except if we have a new transfer on the slave side
always @(posedge ACLK or ARESET_D) begin
if (ARESET_D != 2'b00) begin
M_VALID_I <= 1'b0;
end else begin
if (S_VALID == 1'b1) begin
//Always set M_VALID_I when slave side is valid
M_VALID_I <= 1'b1;
end else if (M_READY == 1'b1 ) begin
//Clear (or keep) when no slave side is valid but master side is ready
M_VALID_I <= 1'b0;
end
end
end
//Slave Ready is either when Master side drives M_READY or we have space in our storage data
assign S_READY_I = (M_READY || (!M_VALID_I)) && !(|(ARESET_D));
endmodule
//*****************************************************************************
// Output Register Stage module
//
// This module builds the output register stages of the memory. This module is
// instantiated in the main memory module (blk_mem_gen_v8_3_3) which is
// declared/implemented further down in this file.
//*****************************************************************************
module blk_mem_gen_v8_3_3_output_stage
#(parameter C_FAMILY = "virtex7",
parameter C_XDEVICEFAMILY = "virtex7",
parameter C_RST_TYPE = "SYNC",
parameter C_HAS_RST = 0,
parameter C_RSTRAM = 0,
parameter C_RST_PRIORITY = "CE",
parameter C_INIT_VAL = "0",
parameter C_HAS_EN = 0,
parameter C_HAS_REGCE = 0,
parameter C_DATA_WIDTH = 32,
parameter C_ADDRB_WIDTH = 10,
parameter C_HAS_MEM_OUTPUT_REGS = 0,
parameter C_USE_SOFTECC = 0,
parameter C_USE_ECC = 0,
parameter NUM_STAGES = 1,
parameter C_EN_ECC_PIPE = 0,
parameter FLOP_DELAY = 100
)
(
input CLK,
input RST,
input EN,
input REGCE,
input [C_DATA_WIDTH-1:0] DIN_I,
output reg [C_DATA_WIDTH-1:0] DOUT,
input SBITERR_IN_I,
input DBITERR_IN_I,
output reg SBITERR,
output reg DBITERR,
input [C_ADDRB_WIDTH-1:0] RDADDRECC_IN_I,
input ECCPIPECE,
output reg [C_ADDRB_WIDTH-1:0] RDADDRECC
);
//******************************
// Port and Generic Definitions
//******************************
//////////////////////////////////////////////////////////////////////////
// Generic Definitions
//////////////////////////////////////////////////////////////////////////
// C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following
// options are available - "spartan3", "spartan6",
// "virtex4", "virtex5", "virtex6" and "virtex6l".
// C_RST_TYPE : Type of reset - Synchronous or Asynchronous
// C_HAS_RST : Determines the presence of the RST port
// C_RSTRAM : Determines if special reset behavior is used
// C_RST_PRIORITY : Determines the priority between CE and SR
// C_INIT_VAL : Initialization value
// C_HAS_EN : Determines the presence of the EN port
// C_HAS_REGCE : Determines the presence of the REGCE port
// C_DATA_WIDTH : Memory write/read width
// C_ADDRB_WIDTH : Width of the ADDRB input port
// C_HAS_MEM_OUTPUT_REGS : Designates the use of a register at the output
// of the RAM primitive
// C_USE_SOFTECC : Determines if the Soft ECC feature is used or
// not. Only applicable Spartan-6
// C_USE_ECC : Determines if the ECC feature is used or
// not. Only applicable for V5 and V6
// NUM_STAGES : Determines the number of output stages
// FLOP_DELAY : Constant delay for register assignments
//////////////////////////////////////////////////////////////////////////
// Port Definitions
//////////////////////////////////////////////////////////////////////////
// CLK : Clock to synchronize all read and write operations
// RST : Reset input to reset memory outputs to a user-defined
// reset state
// EN : Enable all read and write operations
// REGCE : Register Clock Enable to control each pipeline output
// register stages
// DIN : Data input to the Output stage.
// DOUT : Final Data output
// SBITERR_IN : SBITERR input signal to the Output stage.
// SBITERR : Final SBITERR Output signal.
// DBITERR_IN : DBITERR input signal to the Output stage.
// DBITERR : Final DBITERR Output signal.
// RDADDRECC_IN : RDADDRECC input signal to the Output stage.
// RDADDRECC : Final RDADDRECC Output signal.
//////////////////////////////////////////////////////////////////////////
// Fix for CR-509792
localparam REG_STAGES = (NUM_STAGES < 2) ? 1 : NUM_STAGES-1;
// Declare the pipeline registers
// (includes mem output reg, mux pipeline stages, and mux output reg)
reg [C_DATA_WIDTH*REG_STAGES-1:0] out_regs;
reg [C_ADDRB_WIDTH*REG_STAGES-1:0] rdaddrecc_regs;
reg [REG_STAGES-1:0] sbiterr_regs;
reg [REG_STAGES-1:0] dbiterr_regs;
reg [C_DATA_WIDTH*8-1:0] init_str = C_INIT_VAL;
reg [C_DATA_WIDTH-1:0] init_val ;
//*********************************************
// Wire off optional inputs based on parameters
//*********************************************
wire en_i;
wire regce_i;
wire rst_i;
// Internal signals
reg [C_DATA_WIDTH-1:0] DIN;
reg [C_ADDRB_WIDTH-1:0] RDADDRECC_IN;
reg SBITERR_IN;
reg DBITERR_IN;
// Internal enable for output registers is tied to user EN or '1' depending
// on parameters
assign en_i = (C_HAS_EN==0 || EN);
// Internal register enable for output registers is tied to user REGCE, EN or
// '1' depending on parameters
// For V4 ECC, REGCE is always 1
// Virtex-4 ECC Not Yet Supported
assign regce_i = ((C_HAS_REGCE==1) && REGCE) ||
((C_HAS_REGCE==0) && (C_HAS_EN==0 || EN));
//Internal SRR is tied to user RST or '0' depending on parameters
assign rst_i = (C_HAS_RST==1) && RST;
//****************************************************
// Power on: load up the output registers and latches
//****************************************************
initial begin
if (!($sscanf(init_str, "%h", init_val))) begin
init_val = 0;
end
DOUT = init_val;
RDADDRECC = 0;
SBITERR = 1'b0;
DBITERR = 1'b0;
DIN = {(C_DATA_WIDTH){1'b0}};
RDADDRECC_IN = 0;
SBITERR_IN = 0;
DBITERR_IN = 0;
// This will be one wider than need, but 0 is an error
out_regs = {(REG_STAGES+1){init_val}};
rdaddrecc_regs = 0;
sbiterr_regs = {(REG_STAGES+1){1'b0}};
dbiterr_regs = {(REG_STAGES+1){1'b0}};
end
//***********************************************
// NUM_STAGES = 0 (No output registers. RAM only)
//***********************************************
generate if (NUM_STAGES == 0) begin : zero_stages
always @* begin
DOUT = DIN;
RDADDRECC = RDADDRECC_IN;
SBITERR = SBITERR_IN;
DBITERR = DBITERR_IN;
end
end
endgenerate
generate if (C_EN_ECC_PIPE == 0) begin : no_ecc_pipe_reg
always @* begin
DIN = DIN_I;
SBITERR_IN = SBITERR_IN_I;
DBITERR_IN = DBITERR_IN_I;
RDADDRECC_IN = RDADDRECC_IN_I;
end
end
endgenerate
generate if (C_EN_ECC_PIPE == 1) begin : with_ecc_pipe_reg
always @(posedge CLK) begin
if(ECCPIPECE == 1) begin
DIN <= #FLOP_DELAY DIN_I;
SBITERR_IN <= #FLOP_DELAY SBITERR_IN_I;
DBITERR_IN <= #FLOP_DELAY DBITERR_IN_I;
RDADDRECC_IN <= #FLOP_DELAY RDADDRECC_IN_I;
end
end
end
endgenerate
//***********************************************
// NUM_STAGES = 1
// (Mem Output Reg only or Mux Output Reg only)
//***********************************************
// Possible valid combinations:
// Note: C_HAS_MUX_OUTPUT_REGS_*=0 when (C_RSTRAM_*=1)
// +-----------------------------------------+
// | C_RSTRAM_* | Reset Behavior |
// +----------------+------------------------+
// | 0 | Normal Behavior |
// +----------------+------------------------+
// | 1 | Special Behavior |
// +----------------+------------------------+
//
// Normal = REGCE gates reset, as in the case of all families except S3ADSP.
// Special = EN gates reset, as in the case of S3ADSP.
generate if (NUM_STAGES == 1 &&
(C_RSTRAM == 0 || (C_RSTRAM == 1 && (C_XDEVICEFAMILY != "spartan3adsp" && C_XDEVICEFAMILY != "aspartan3adsp" )) ||
C_HAS_MEM_OUTPUT_REGS == 0 || C_HAS_RST == 0))
begin : one_stages_norm
always @(posedge CLK) begin
if (C_RST_PRIORITY == "CE") begin //REGCE has priority
if (regce_i && rst_i) begin
DOUT <= #FLOP_DELAY init_val;
RDADDRECC <= #FLOP_DELAY 0;
SBITERR <= #FLOP_DELAY 1'b0;
DBITERR <= #FLOP_DELAY 1'b0;
end else if (regce_i) begin
DOUT <= #FLOP_DELAY DIN;
RDADDRECC <= #FLOP_DELAY RDADDRECC_IN;
SBITERR <= #FLOP_DELAY SBITERR_IN;
DBITERR <= #FLOP_DELAY DBITERR_IN;
end //Output signal assignments
end else begin //RST has priority
if (rst_i) begin
DOUT <= #FLOP_DELAY init_val;
RDADDRECC <= #FLOP_DELAY RDADDRECC_IN;
SBITERR <= #FLOP_DELAY 1'b0;
DBITERR <= #FLOP_DELAY 1'b0;
end else if (regce_i) begin
DOUT <= #FLOP_DELAY DIN;
RDADDRECC <= #FLOP_DELAY RDADDRECC_IN;
SBITERR <= #FLOP_DELAY SBITERR_IN;
DBITERR <= #FLOP_DELAY DBITERR_IN;
end //Output signal assignments
end //end Priority conditions
end //end RST Type conditions
end //end one_stages_norm generate statement
endgenerate
// Special Reset Behavior for S3ADSP
generate if (NUM_STAGES == 1 && C_RSTRAM == 1 && (C_XDEVICEFAMILY =="spartan3adsp" || C_XDEVICEFAMILY =="aspartan3adsp"))
begin : one_stage_splbhv
always @(posedge CLK) begin
if (en_i && rst_i) begin
DOUT <= #FLOP_DELAY init_val;
end else if (regce_i && !rst_i) begin
DOUT <= #FLOP_DELAY DIN;
end //Output signal assignments
end //end CLK
end //end one_stage_splbhv generate statement
endgenerate
//************************************************************
// NUM_STAGES > 1
// Mem Output Reg + Mux Output Reg
// or
// Mem Output Reg + Mux Pipeline Stages (>0) + Mux Output Reg
// or
// Mux Pipeline Stages (>0) + Mux Output Reg
//*************************************************************
generate if (NUM_STAGES > 1) begin : multi_stage
//Asynchronous Reset
always @(posedge CLK) begin
if (C_RST_PRIORITY == "CE") begin //REGCE has priority
if (regce_i && rst_i) begin
DOUT <= #FLOP_DELAY init_val;
RDADDRECC <= #FLOP_DELAY 0;
SBITERR <= #FLOP_DELAY 1'b0;
DBITERR <= #FLOP_DELAY 1'b0;
end else if (regce_i) begin
DOUT <= #FLOP_DELAY
out_regs[C_DATA_WIDTH*(NUM_STAGES-2)+:C_DATA_WIDTH];
RDADDRECC <= #FLOP_DELAY rdaddrecc_regs[C_ADDRB_WIDTH*(NUM_STAGES-2)+:C_ADDRB_WIDTH];
SBITERR <= #FLOP_DELAY sbiterr_regs[NUM_STAGES-2];
DBITERR <= #FLOP_DELAY dbiterr_regs[NUM_STAGES-2];
end //Output signal assignments
end else begin //RST has priority
if (rst_i) begin
DOUT <= #FLOP_DELAY init_val;
RDADDRECC <= #FLOP_DELAY 0;
SBITERR <= #FLOP_DELAY 1'b0;
DBITERR <= #FLOP_DELAY 1'b0;
end else if (regce_i) begin
DOUT <= #FLOP_DELAY
out_regs[C_DATA_WIDTH*(NUM_STAGES-2)+:C_DATA_WIDTH];
RDADDRECC <= #FLOP_DELAY rdaddrecc_regs[C_ADDRB_WIDTH*(NUM_STAGES-2)+:C_ADDRB_WIDTH];
SBITERR <= #FLOP_DELAY sbiterr_regs[NUM_STAGES-2];
DBITERR <= #FLOP_DELAY dbiterr_regs[NUM_STAGES-2];
end //Output signal assignments
end //end Priority conditions
// Shift the data through the output stages
if (en_i) begin
out_regs <= #FLOP_DELAY (out_regs << C_DATA_WIDTH) | DIN;
rdaddrecc_regs <= #FLOP_DELAY (rdaddrecc_regs << C_ADDRB_WIDTH) | RDADDRECC_IN;
sbiterr_regs <= #FLOP_DELAY (sbiterr_regs << 1) | SBITERR_IN;
dbiterr_regs <= #FLOP_DELAY (dbiterr_regs << 1) | DBITERR_IN;
end
end //end CLK
end //end multi_stage generate statement
endgenerate
endmodule
module blk_mem_gen_v8_3_3_softecc_output_reg_stage
#(parameter C_DATA_WIDTH = 32,
parameter C_ADDRB_WIDTH = 10,
parameter C_HAS_SOFTECC_OUTPUT_REGS_B= 0,
parameter C_USE_SOFTECC = 0,
parameter FLOP_DELAY = 100
)
(
input CLK,
input [C_DATA_WIDTH-1:0] DIN,
output reg [C_DATA_WIDTH-1:0] DOUT,
input SBITERR_IN,
input DBITERR_IN,
output reg SBITERR,
output reg DBITERR,
input [C_ADDRB_WIDTH-1:0] RDADDRECC_IN,
output reg [C_ADDRB_WIDTH-1:0] RDADDRECC
);
//******************************
// Port and Generic Definitions
//******************************
//////////////////////////////////////////////////////////////////////////
// Generic Definitions
//////////////////////////////////////////////////////////////////////////
// C_DATA_WIDTH : Memory write/read width
// C_ADDRB_WIDTH : Width of the ADDRB input port
// C_HAS_SOFTECC_OUTPUT_REGS_B : Designates the use of a register at the output
// of the RAM primitive
// C_USE_SOFTECC : Determines if the Soft ECC feature is used or
// not. Only applicable Spartan-6
// FLOP_DELAY : Constant delay for register assignments
//////////////////////////////////////////////////////////////////////////
// Port Definitions
//////////////////////////////////////////////////////////////////////////
// CLK : Clock to synchronize all read and write operations
// DIN : Data input to the Output stage.
// DOUT : Final Data output
// SBITERR_IN : SBITERR input signal to the Output stage.
// SBITERR : Final SBITERR Output signal.
// DBITERR_IN : DBITERR input signal to the Output stage.
// DBITERR : Final DBITERR Output signal.
// RDADDRECC_IN : RDADDRECC input signal to the Output stage.
// RDADDRECC : Final RDADDRECC Output signal.
//////////////////////////////////////////////////////////////////////////
reg [C_DATA_WIDTH-1:0] dout_i = 0;
reg sbiterr_i = 0;
reg dbiterr_i = 0;
reg [C_ADDRB_WIDTH-1:0] rdaddrecc_i = 0;
//***********************************************
// NO OUTPUT REGISTERS.
//***********************************************
generate if (C_HAS_SOFTECC_OUTPUT_REGS_B==0) begin : no_output_stage
always @* begin
DOUT = DIN;
RDADDRECC = RDADDRECC_IN;
SBITERR = SBITERR_IN;
DBITERR = DBITERR_IN;
end
end
endgenerate
//***********************************************
// WITH OUTPUT REGISTERS.
//***********************************************
generate if (C_HAS_SOFTECC_OUTPUT_REGS_B==1) begin : has_output_stage
always @(posedge CLK) begin
dout_i <= #FLOP_DELAY DIN;
rdaddrecc_i <= #FLOP_DELAY RDADDRECC_IN;
sbiterr_i <= #FLOP_DELAY SBITERR_IN;
dbiterr_i <= #FLOP_DELAY DBITERR_IN;
end
always @* begin
DOUT = dout_i;
RDADDRECC = rdaddrecc_i;
SBITERR = sbiterr_i;
DBITERR = dbiterr_i;
end //end always
end //end in_or_out_stage generate statement
endgenerate
endmodule
//*****************************************************************************
// Main Memory module
//
// This module is the top-level behavioral model and this implements the RAM
//*****************************************************************************
module blk_mem_gen_v8_3_3_mem_module
#(parameter C_CORENAME = "blk_mem_gen_v8_3_3",
parameter C_FAMILY = "virtex7",
parameter C_XDEVICEFAMILY = "virtex7",
parameter C_MEM_TYPE = 2,
parameter C_BYTE_SIZE = 9,
parameter C_USE_BRAM_BLOCK = 0,
parameter C_ALGORITHM = 1,
parameter C_PRIM_TYPE = 3,
parameter C_LOAD_INIT_FILE = 0,
parameter C_INIT_FILE_NAME = "",
parameter C_INIT_FILE = "",
parameter C_USE_DEFAULT_DATA = 0,
parameter C_DEFAULT_DATA = "0",
parameter C_RST_TYPE = "SYNC",
parameter C_HAS_RSTA = 0,
parameter C_RST_PRIORITY_A = "CE",
parameter C_RSTRAM_A = 0,
parameter C_INITA_VAL = "0",
parameter C_HAS_ENA = 1,
parameter C_HAS_REGCEA = 0,
parameter C_USE_BYTE_WEA = 0,
parameter C_WEA_WIDTH = 1,
parameter C_WRITE_MODE_A = "WRITE_FIRST",
parameter C_WRITE_WIDTH_A = 32,
parameter C_READ_WIDTH_A = 32,
parameter C_WRITE_DEPTH_A = 64,
parameter C_READ_DEPTH_A = 64,
parameter C_ADDRA_WIDTH = 5,
parameter C_HAS_RSTB = 0,
parameter C_RST_PRIORITY_B = "CE",
parameter C_RSTRAM_B = 0,
parameter C_INITB_VAL = "",
parameter C_HAS_ENB = 1,
parameter C_HAS_REGCEB = 0,
parameter C_USE_BYTE_WEB = 0,
parameter C_WEB_WIDTH = 1,
parameter C_WRITE_MODE_B = "WRITE_FIRST",
parameter C_WRITE_WIDTH_B = 32,
parameter C_READ_WIDTH_B = 32,
parameter C_WRITE_DEPTH_B = 64,
parameter C_READ_DEPTH_B = 64,
parameter C_ADDRB_WIDTH = 5,
parameter C_HAS_MEM_OUTPUT_REGS_A = 0,
parameter C_HAS_MEM_OUTPUT_REGS_B = 0,
parameter C_HAS_MUX_OUTPUT_REGS_A = 0,
parameter C_HAS_MUX_OUTPUT_REGS_B = 0,
parameter C_HAS_SOFTECC_INPUT_REGS_A = 0,
parameter C_HAS_SOFTECC_OUTPUT_REGS_B= 0,
parameter C_MUX_PIPELINE_STAGES = 0,
parameter C_USE_SOFTECC = 0,
parameter C_USE_ECC = 0,
parameter C_HAS_INJECTERR = 0,
parameter C_SIM_COLLISION_CHECK = "NONE",
parameter C_COMMON_CLK = 1,
parameter FLOP_DELAY = 100,
parameter C_DISABLE_WARN_BHV_COLL = 0,
parameter C_EN_ECC_PIPE = 0,
parameter C_DISABLE_WARN_BHV_RANGE = 0
)
(input CLKA,
input RSTA,
input ENA,
input REGCEA,
input [C_WEA_WIDTH-1:0] WEA,
input [C_ADDRA_WIDTH-1:0] ADDRA,
input [C_WRITE_WIDTH_A-1:0] DINA,
output [C_READ_WIDTH_A-1:0] DOUTA,
input CLKB,
input RSTB,
input ENB,
input REGCEB,
input [C_WEB_WIDTH-1:0] WEB,
input [C_ADDRB_WIDTH-1:0] ADDRB,
input [C_WRITE_WIDTH_B-1:0] DINB,
output [C_READ_WIDTH_B-1:0] DOUTB,
input INJECTSBITERR,
input INJECTDBITERR,
input ECCPIPECE,
input SLEEP,
output SBITERR,
output DBITERR,
output [C_ADDRB_WIDTH-1:0] RDADDRECC
);
//******************************
// Port and Generic Definitions
//******************************
//////////////////////////////////////////////////////////////////////////
// Generic Definitions
//////////////////////////////////////////////////////////////////////////
// C_CORENAME : Instance name of the Block Memory Generator core
// C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following
// options are available - "spartan3", "spartan6",
// "virtex4", "virtex5", "virtex6" and "virtex6l".
// C_MEM_TYPE : Designates memory type.
// It can be
// 0 - Single Port Memory
// 1 - Simple Dual Port Memory
// 2 - True Dual Port Memory
// 3 - Single Port Read Only Memory
// 4 - Dual Port Read Only Memory
// C_BYTE_SIZE : Size of a byte (8 or 9 bits)
// C_ALGORITHM : Designates the algorithm method used
// for constructing the memory.
// It can be Fixed_Primitives, Minimum_Area or
// Low_Power
// C_PRIM_TYPE : Designates the user selected primitive used to
// construct the memory.
//
// C_LOAD_INIT_FILE : Designates the use of an initialization file to
// initialize memory contents.
// C_INIT_FILE_NAME : Memory initialization file name.
// C_USE_DEFAULT_DATA : Designates whether to fill remaining
// initialization space with default data
// C_DEFAULT_DATA : Default value of all memory locations
// not initialized by the memory
// initialization file.
// C_RST_TYPE : Type of reset - Synchronous or Asynchronous
// C_HAS_RSTA : Determines the presence of the RSTA port
// C_RST_PRIORITY_A : Determines the priority between CE and SR for
// Port A.
// C_RSTRAM_A : Determines if special reset behavior is used for
// Port A
// C_INITA_VAL : The initialization value for Port A
// C_HAS_ENA : Determines the presence of the ENA port
// C_HAS_REGCEA : Determines the presence of the REGCEA port
// C_USE_BYTE_WEA : Determines if the Byte Write is used or not.
// C_WEA_WIDTH : The width of the WEA port
// C_WRITE_MODE_A : Configurable write mode for Port A. It can be
// WRITE_FIRST, READ_FIRST or NO_CHANGE.
// C_WRITE_WIDTH_A : Memory write width for Port A.
// C_READ_WIDTH_A : Memory read width for Port A.
// C_WRITE_DEPTH_A : Memory write depth for Port A.
// C_READ_DEPTH_A : Memory read depth for Port A.
// C_ADDRA_WIDTH : Width of the ADDRA input port
// C_HAS_RSTB : Determines the presence of the RSTB port
// C_RST_PRIORITY_B : Determines the priority between CE and SR for
// Port B.
// C_RSTRAM_B : Determines if special reset behavior is used for
// Port B
// C_INITB_VAL : The initialization value for Port B
// C_HAS_ENB : Determines the presence of the ENB port
// C_HAS_REGCEB : Determines the presence of the REGCEB port
// C_USE_BYTE_WEB : Determines if the Byte Write is used or not.
// C_WEB_WIDTH : The width of the WEB port
// C_WRITE_MODE_B : Configurable write mode for Port B. It can be
// WRITE_FIRST, READ_FIRST or NO_CHANGE.
// C_WRITE_WIDTH_B : Memory write width for Port B.
// C_READ_WIDTH_B : Memory read width for Port B.
// C_WRITE_DEPTH_B : Memory write depth for Port B.
// C_READ_DEPTH_B : Memory read depth for Port B.
// C_ADDRB_WIDTH : Width of the ADDRB input port
// C_HAS_MEM_OUTPUT_REGS_A : Designates the use of a register at the output
// of the RAM primitive for Port A.
// C_HAS_MEM_OUTPUT_REGS_B : Designates the use of a register at the output
// of the RAM primitive for Port B.
// C_HAS_MUX_OUTPUT_REGS_A : Designates the use of a register at the output
// of the MUX for Port A.
// C_HAS_MUX_OUTPUT_REGS_B : Designates the use of a register at the output
// of the MUX for Port B.
// C_MUX_PIPELINE_STAGES : Designates the number of pipeline stages in
// between the muxes.
// C_USE_SOFTECC : Determines if the Soft ECC feature is used or
// not. Only applicable Spartan-6
// C_USE_ECC : Determines if the ECC feature is used or
// not. Only applicable for V5 and V6
// C_HAS_INJECTERR : Determines if the error injection pins
// are present or not. If the ECC feature
// is not used, this value is defaulted to
// 0, else the following are the allowed
// values:
// 0 : No INJECTSBITERR or INJECTDBITERR pins
// 1 : Only INJECTSBITERR pin exists
// 2 : Only INJECTDBITERR pin exists
// 3 : Both INJECTSBITERR and INJECTDBITERR pins exist
// C_SIM_COLLISION_CHECK : Controls the disabling of Unisim model collision
// warnings. It can be "ALL", "NONE",
// "Warnings_Only" or "Generate_X_Only".
// C_COMMON_CLK : Determins if the core has a single CLK input.
// C_DISABLE_WARN_BHV_COLL : Controls the Behavioral Model Collision warnings
// C_DISABLE_WARN_BHV_RANGE: Controls the Behavioral Model Out of Range
// warnings
//////////////////////////////////////////////////////////////////////////
// Port Definitions
//////////////////////////////////////////////////////////////////////////
// CLKA : Clock to synchronize all read and write operations of Port A.
// RSTA : Reset input to reset memory outputs to a user-defined
// reset state for Port A.
// ENA : Enable all read and write operations of Port A.
// REGCEA : Register Clock Enable to control each pipeline output
// register stages for Port A.
// WEA : Write Enable to enable all write operations of Port A.
// ADDRA : Address of Port A.
// DINA : Data input of Port A.
// DOUTA : Data output of Port A.
// CLKB : Clock to synchronize all read and write operations of Port B.
// RSTB : Reset input to reset memory outputs to a user-defined
// reset state for Port B.
// ENB : Enable all read and write operations of Port B.
// REGCEB : Register Clock Enable to control each pipeline output
// register stages for Port B.
// WEB : Write Enable to enable all write operations of Port B.
// ADDRB : Address of Port B.
// DINB : Data input of Port B.
// DOUTB : Data output of Port B.
// INJECTSBITERR : Single Bit ECC Error Injection Pin.
// INJECTDBITERR : Double Bit ECC Error Injection Pin.
// SBITERR : Output signal indicating that a Single Bit ECC Error has been
// detected and corrected.
// DBITERR : Output signal indicating that a Double Bit ECC Error has been
// detected.
// RDADDRECC : Read Address Output signal indicating address at which an
// ECC error has occurred.
//////////////////////////////////////////////////////////////////////////
// Note: C_CORENAME parameter is hard-coded to "blk_mem_gen_v8_3_3" and it is
// only used by this module to print warning messages. It is neither passed
// down from blk_mem_gen_v8_3_3_xst.v nor present in the instantiation template
// coregen generates
//***************************************************************************
// constants for the core behavior
//***************************************************************************
// file handles for logging
//--------------------------------------------------
localparam ADDRFILE = 32'h8000_0001; //stdout for addr out of range
localparam COLLFILE = 32'h8000_0001; //stdout for coll detection
localparam ERRFILE = 32'h8000_0001; //stdout for file I/O errors
// other constants
//--------------------------------------------------
localparam COLL_DELAY = 100; // 100 ps
// locally derived parameters to determine memory shape
//-----------------------------------------------------
localparam CHKBIT_WIDTH = (C_WRITE_WIDTH_A>57 ? 8 : (C_WRITE_WIDTH_A>26 ? 7 : (C_WRITE_WIDTH_A>11 ? 6 : (C_WRITE_WIDTH_A>4 ? 5 : (C_WRITE_WIDTH_A<5 ? 4 :0)))));
localparam MIN_WIDTH_A = (C_WRITE_WIDTH_A < C_READ_WIDTH_A) ?
C_WRITE_WIDTH_A : C_READ_WIDTH_A;
localparam MIN_WIDTH_B = (C_WRITE_WIDTH_B < C_READ_WIDTH_B) ?
C_WRITE_WIDTH_B : C_READ_WIDTH_B;
localparam MIN_WIDTH = (MIN_WIDTH_A < MIN_WIDTH_B) ?
MIN_WIDTH_A : MIN_WIDTH_B;
localparam MAX_DEPTH_A = (C_WRITE_DEPTH_A > C_READ_DEPTH_A) ?
C_WRITE_DEPTH_A : C_READ_DEPTH_A;
localparam MAX_DEPTH_B = (C_WRITE_DEPTH_B > C_READ_DEPTH_B) ?
C_WRITE_DEPTH_B : C_READ_DEPTH_B;
localparam MAX_DEPTH = (MAX_DEPTH_A > MAX_DEPTH_B) ?
MAX_DEPTH_A : MAX_DEPTH_B;
// locally derived parameters to assist memory access
//----------------------------------------------------
// Calculate the width ratios of each port with respect to the narrowest
// port
localparam WRITE_WIDTH_RATIO_A = C_WRITE_WIDTH_A/MIN_WIDTH;
localparam READ_WIDTH_RATIO_A = C_READ_WIDTH_A/MIN_WIDTH;
localparam WRITE_WIDTH_RATIO_B = C_WRITE_WIDTH_B/MIN_WIDTH;
localparam READ_WIDTH_RATIO_B = C_READ_WIDTH_B/MIN_WIDTH;
// To modify the LSBs of the 'wider' data to the actual
// address value
//----------------------------------------------------
localparam WRITE_ADDR_A_DIV = C_WRITE_WIDTH_A/MIN_WIDTH_A;
localparam READ_ADDR_A_DIV = C_READ_WIDTH_A/MIN_WIDTH_A;
localparam WRITE_ADDR_B_DIV = C_WRITE_WIDTH_B/MIN_WIDTH_B;
localparam READ_ADDR_B_DIV = C_READ_WIDTH_B/MIN_WIDTH_B;
// If byte writes aren't being used, make sure BYTE_SIZE is not
// wider than the memory elements to avoid compilation warnings
localparam BYTE_SIZE = (C_BYTE_SIZE < MIN_WIDTH) ? C_BYTE_SIZE : MIN_WIDTH;
// The memory
reg [MIN_WIDTH-1:0] memory [0:MAX_DEPTH-1];
reg [MIN_WIDTH-1:0] temp_mem_array [0:MAX_DEPTH-1];
reg [C_WRITE_WIDTH_A+CHKBIT_WIDTH-1:0] doublebit_error = 3;
// ECC error arrays
reg sbiterr_arr [0:MAX_DEPTH-1];
reg dbiterr_arr [0:MAX_DEPTH-1];
reg softecc_sbiterr_arr [0:MAX_DEPTH-1];
reg softecc_dbiterr_arr [0:MAX_DEPTH-1];
// Memory output 'latches'
reg [C_READ_WIDTH_A-1:0] memory_out_a;
reg [C_READ_WIDTH_B-1:0] memory_out_b;
// ECC error inputs and outputs from output_stage module:
reg sbiterr_in;
wire sbiterr_sdp;
reg dbiterr_in;
wire dbiterr_sdp;
wire [C_READ_WIDTH_B-1:0] dout_i;
wire dbiterr_i;
wire sbiterr_i;
wire [C_ADDRB_WIDTH-1:0] rdaddrecc_i;
reg [C_ADDRB_WIDTH-1:0] rdaddrecc_in;
wire [C_ADDRB_WIDTH-1:0] rdaddrecc_sdp;
// Reset values
reg [C_READ_WIDTH_A-1:0] inita_val;
reg [C_READ_WIDTH_B-1:0] initb_val;
// Collision detect
reg is_collision;
reg is_collision_a, is_collision_delay_a;
reg is_collision_b, is_collision_delay_b;
// Temporary variables for initialization
//---------------------------------------
integer status;
integer initfile;
integer meminitfile;
// data input buffer
reg [C_WRITE_WIDTH_A-1:0] mif_data;
reg [C_WRITE_WIDTH_A-1:0] mem_data;
// string values in hex
reg [C_READ_WIDTH_A*8-1:0] inita_str = C_INITA_VAL;
reg [C_READ_WIDTH_B*8-1:0] initb_str = C_INITB_VAL;
reg [C_WRITE_WIDTH_A*8-1:0] default_data_str = C_DEFAULT_DATA;
// initialization filename
reg [1023*8-1:0] init_file_str = C_INIT_FILE_NAME;
reg [1023*8-1:0] mem_init_file_str = C_INIT_FILE;
//Constants used to calculate the effective address widths for each of the
//four ports.
integer cnt = 1;
integer write_addr_a_width, read_addr_a_width;
integer write_addr_b_width, read_addr_b_width;
localparam C_FAMILY_LOCALPARAM = (C_FAMILY=="zynquplus"?"virtex7":(C_FAMILY=="kintexuplus"?"virtex7":(C_FAMILY=="virtexuplus"?"virtex7":(C_FAMILY=="virtexu"?"virtex7":(C_FAMILY=="kintexu" ? "virtex7":(C_FAMILY=="virtex7" ? "virtex7" : (C_FAMILY=="virtex7l" ? "virtex7" : (C_FAMILY=="qvirtex7" ? "virtex7" : (C_FAMILY=="qvirtex7l" ? "virtex7" : (C_FAMILY=="kintex7" ? "virtex7" : (C_FAMILY=="kintex7l" ? "virtex7" : (C_FAMILY=="qkintex7" ? "virtex7" : (C_FAMILY=="qkintex7l" ? "virtex7" : (C_FAMILY=="artix7" ? "virtex7" : (C_FAMILY=="artix7l" ? "virtex7" : (C_FAMILY=="qartix7" ? "virtex7" : (C_FAMILY=="qartix7l" ? "virtex7" : (C_FAMILY=="aartix7" ? "virtex7" : (C_FAMILY=="zynq" ? "virtex7" : (C_FAMILY=="azynq" ? "virtex7" : (C_FAMILY=="qzynq" ? "virtex7" : C_FAMILY)))))))))))))))))))));
// Internal configuration parameters
//---------------------------------------------
localparam SINGLE_PORT = (C_MEM_TYPE==0 || C_MEM_TYPE==3);
localparam IS_ROM = (C_MEM_TYPE==3 || C_MEM_TYPE==4);
localparam HAS_A_WRITE = (!IS_ROM);
localparam HAS_B_WRITE = (C_MEM_TYPE==2);
localparam HAS_A_READ = (C_MEM_TYPE!=1);
localparam HAS_B_READ = (!SINGLE_PORT);
localparam HAS_B_PORT = (HAS_B_READ || HAS_B_WRITE);
// Calculate the mux pipeline register stages for Port A and Port B
//------------------------------------------------------------------
localparam MUX_PIPELINE_STAGES_A = (C_HAS_MUX_OUTPUT_REGS_A) ?
C_MUX_PIPELINE_STAGES : 0;
localparam MUX_PIPELINE_STAGES_B = (C_HAS_MUX_OUTPUT_REGS_B) ?
C_MUX_PIPELINE_STAGES : 0;
// Calculate total number of register stages in the core
// -----------------------------------------------------
localparam NUM_OUTPUT_STAGES_A = (C_HAS_MEM_OUTPUT_REGS_A+MUX_PIPELINE_STAGES_A+C_HAS_MUX_OUTPUT_REGS_A);
localparam NUM_OUTPUT_STAGES_B = (C_HAS_MEM_OUTPUT_REGS_B+MUX_PIPELINE_STAGES_B+C_HAS_MUX_OUTPUT_REGS_B);
wire ena_i;
wire enb_i;
wire reseta_i;
wire resetb_i;
wire [C_WEA_WIDTH-1:0] wea_i;
wire [C_WEB_WIDTH-1:0] web_i;
wire rea_i;
wire reb_i;
wire rsta_outp_stage;
wire rstb_outp_stage;
// ECC SBITERR/DBITERR Outputs
// The ECC Behavior is modeled by the behavioral models only for Virtex-6.
// For Virtex-5, these outputs will be tied to 0.
assign SBITERR = ((C_MEM_TYPE == 1 && C_USE_ECC == 1) || C_USE_SOFTECC == 1)?sbiterr_sdp:0;
assign DBITERR = ((C_MEM_TYPE == 1 && C_USE_ECC == 1) || C_USE_SOFTECC == 1)?dbiterr_sdp:0;
assign RDADDRECC = (((C_FAMILY_LOCALPARAM == "virtex7") && C_MEM_TYPE == 1 && C_USE_ECC == 1) || C_USE_SOFTECC == 1)?rdaddrecc_sdp:0;
// This effectively wires off optional inputs
assign ena_i = (C_HAS_ENA==0) || ENA;
assign enb_i = ((C_HAS_ENB==0) || ENB) && HAS_B_PORT;
//assign wea_i = (HAS_A_WRITE && ena_i) ? WEA : 'b0;
// To Fix CR855535
assign wea_i = (HAS_A_WRITE == 1 && C_MEM_TYPE == 1 &&C_USE_ECC == 1 && C_HAS_ENA == 1 && ENA == 1) ? 'b1 :(HAS_A_WRITE == 1 && C_MEM_TYPE == 1 &&C_USE_ECC == 1 && C_HAS_ENA == 0) ? WEA : (HAS_A_WRITE && ena_i && C_USE_ECC == 0) ? WEA : 'b0;
assign web_i = (HAS_B_WRITE && enb_i) ? WEB : 'b0;
assign rea_i = (HAS_A_READ) ? ena_i : 'b0;
assign reb_i = (HAS_B_READ) ? enb_i : 'b0;
// These signals reset the memory latches
assign reseta_i =
((C_HAS_RSTA==1 && RSTA && NUM_OUTPUT_STAGES_A==0) ||
(C_HAS_RSTA==1 && RSTA && C_RSTRAM_A==1));
assign resetb_i =
((C_HAS_RSTB==1 && RSTB && NUM_OUTPUT_STAGES_B==0) ||
(C_HAS_RSTB==1 && RSTB && C_RSTRAM_B==1));
// Tasks to access the memory
//---------------------------
//**************
// write_a
//**************
task write_a
(input reg [C_ADDRA_WIDTH-1:0] addr,
input reg [C_WEA_WIDTH-1:0] byte_en,
input reg [C_WRITE_WIDTH_A-1:0] data,
input inj_sbiterr,
input inj_dbiterr);
reg [C_WRITE_WIDTH_A-1:0] current_contents;
reg [C_ADDRA_WIDTH-1:0] address;
integer i;
begin
// Shift the address by the ratio
address = (addr/WRITE_ADDR_A_DIV);
if (address >= C_WRITE_DEPTH_A) begin
if (!C_DISABLE_WARN_BHV_RANGE) begin
$fdisplay(ADDRFILE,
"%0s WARNING: Address %0h is outside range for A Write",
C_CORENAME, addr);
end
// valid address
end else begin
// Combine w/ byte writes
if (C_USE_BYTE_WEA) begin
// Get the current memory contents
if (WRITE_WIDTH_RATIO_A == 1) begin
// Workaround for IUS 5.5 part-select issue
current_contents = memory[address];
end else begin
for (i = 0; i < WRITE_WIDTH_RATIO_A; i = i + 1) begin
current_contents[MIN_WIDTH*i+:MIN_WIDTH]
= memory[address*WRITE_WIDTH_RATIO_A + i];
end
end
// Apply incoming bytes
if (C_WEA_WIDTH == 1) begin
// Workaround for IUS 5.5 part-select issue
if (byte_en[0]) begin
current_contents = data;
end
end else begin
for (i = 0; i < C_WEA_WIDTH; i = i + 1) begin
if (byte_en[i]) begin
current_contents[BYTE_SIZE*i+:BYTE_SIZE]
= data[BYTE_SIZE*i+:BYTE_SIZE];
end
end
end
// No byte-writes, overwrite the whole word
end else begin
current_contents = data;
end
// Insert double bit errors:
if (C_USE_ECC == 1) begin
if ((C_HAS_INJECTERR == 2 || C_HAS_INJECTERR == 3) && inj_dbiterr == 1'b1) begin
// Modified for Implementing CR_859399
current_contents[0] = !(current_contents[30]);
current_contents[1] = !(current_contents[62]);
/*current_contents[0] = !(current_contents[0]);
current_contents[1] = !(current_contents[1]);*/
end
end
// Insert softecc double bit errors:
if (C_USE_SOFTECC == 1) begin
if ((C_HAS_INJECTERR == 2 || C_HAS_INJECTERR == 3) && inj_dbiterr == 1'b1) begin
doublebit_error[C_WRITE_WIDTH_A+CHKBIT_WIDTH-1:2] = doublebit_error[C_WRITE_WIDTH_A+CHKBIT_WIDTH-3:0];
doublebit_error[0] = doublebit_error[C_WRITE_WIDTH_A+CHKBIT_WIDTH-1];
doublebit_error[1] = doublebit_error[C_WRITE_WIDTH_A+CHKBIT_WIDTH-2];
current_contents = current_contents ^ doublebit_error[C_WRITE_WIDTH_A-1:0];
end
end
// Write data to memory
if (WRITE_WIDTH_RATIO_A == 1) begin
// Workaround for IUS 5.5 part-select issue
memory[address*WRITE_WIDTH_RATIO_A] = current_contents;
end else begin
for (i = 0; i < WRITE_WIDTH_RATIO_A; i = i + 1) begin
memory[address*WRITE_WIDTH_RATIO_A + i]
= current_contents[MIN_WIDTH*i+:MIN_WIDTH];
end
end
// Store the address at which error is injected:
if ((C_FAMILY_LOCALPARAM == "virtex7") && C_USE_ECC == 1) begin
if ((C_HAS_INJECTERR == 1 && inj_sbiterr == 1'b1) ||
(C_HAS_INJECTERR == 3 && inj_sbiterr == 1'b1 && inj_dbiterr != 1'b1))
begin
sbiterr_arr[addr] = 1;
end else begin
sbiterr_arr[addr] = 0;
end
if ((C_HAS_INJECTERR == 2 || C_HAS_INJECTERR == 3) && inj_dbiterr == 1'b1) begin
dbiterr_arr[addr] = 1;
end else begin
dbiterr_arr[addr] = 0;
end
end
// Store the address at which softecc error is injected:
if (C_USE_SOFTECC == 1) begin
if ((C_HAS_INJECTERR == 1 && inj_sbiterr == 1'b1) ||
(C_HAS_INJECTERR == 3 && inj_sbiterr == 1'b1 && inj_dbiterr != 1'b1))
begin
softecc_sbiterr_arr[addr] = 1;
end else begin
softecc_sbiterr_arr[addr] = 0;
end
if ((C_HAS_INJECTERR == 2 || C_HAS_INJECTERR == 3) && inj_dbiterr == 1'b1) begin
softecc_dbiterr_arr[addr] = 1;
end else begin
softecc_dbiterr_arr[addr] = 0;
end
end
end
end
endtask
//**************
// write_b
//**************
task write_b
(input reg [C_ADDRB_WIDTH-1:0] addr,
input reg [C_WEB_WIDTH-1:0] byte_en,
input reg [C_WRITE_WIDTH_B-1:0] data);
reg [C_WRITE_WIDTH_B-1:0] current_contents;
reg [C_ADDRB_WIDTH-1:0] address;
integer i;
begin
// Shift the address by the ratio
address = (addr/WRITE_ADDR_B_DIV);
if (address >= C_WRITE_DEPTH_B) begin
if (!C_DISABLE_WARN_BHV_RANGE) begin
$fdisplay(ADDRFILE,
"%0s WARNING: Address %0h is outside range for B Write",
C_CORENAME, addr);
end
// valid address
end else begin
// Combine w/ byte writes
if (C_USE_BYTE_WEB) begin
// Get the current memory contents
if (WRITE_WIDTH_RATIO_B == 1) begin
// Workaround for IUS 5.5 part-select issue
current_contents = memory[address];
end else begin
for (i = 0; i < WRITE_WIDTH_RATIO_B; i = i + 1) begin
current_contents[MIN_WIDTH*i+:MIN_WIDTH]
= memory[address*WRITE_WIDTH_RATIO_B + i];
end
end
// Apply incoming bytes
if (C_WEB_WIDTH == 1) begin
// Workaround for IUS 5.5 part-select issue
if (byte_en[0]) begin
current_contents = data;
end
end else begin
for (i = 0; i < C_WEB_WIDTH; i = i + 1) begin
if (byte_en[i]) begin
current_contents[BYTE_SIZE*i+:BYTE_SIZE]
= data[BYTE_SIZE*i+:BYTE_SIZE];
end
end
end
// No byte-writes, overwrite the whole word
end else begin
current_contents = data;
end
// Write data to memory
if (WRITE_WIDTH_RATIO_B == 1) begin
// Workaround for IUS 5.5 part-select issue
memory[address*WRITE_WIDTH_RATIO_B] = current_contents;
end else begin
for (i = 0; i < WRITE_WIDTH_RATIO_B; i = i + 1) begin
memory[address*WRITE_WIDTH_RATIO_B + i]
= current_contents[MIN_WIDTH*i+:MIN_WIDTH];
end
end
end
end
endtask
//**************
// read_a
//**************
task read_a
(input reg [C_ADDRA_WIDTH-1:0] addr,
input reg reset);
reg [C_ADDRA_WIDTH-1:0] address;
integer i;
begin
if (reset) begin
memory_out_a <= #FLOP_DELAY inita_val;
end else begin
// Shift the address by the ratio
address = (addr/READ_ADDR_A_DIV);
if (address >= C_READ_DEPTH_A) begin
if (!C_DISABLE_WARN_BHV_RANGE) begin
$fdisplay(ADDRFILE,
"%0s WARNING: Address %0h is outside range for A Read",
C_CORENAME, addr);
end
memory_out_a <= #FLOP_DELAY 'bX;
// valid address
end else begin
if (READ_WIDTH_RATIO_A==1) begin
memory_out_a <= #FLOP_DELAY memory[address*READ_WIDTH_RATIO_A];
end else begin
// Increment through the 'partial' words in the memory
for (i = 0; i < READ_WIDTH_RATIO_A; i = i + 1) begin
memory_out_a[MIN_WIDTH*i+:MIN_WIDTH]
<= #FLOP_DELAY memory[address*READ_WIDTH_RATIO_A + i];
end
end //end READ_WIDTH_RATIO_A==1 loop
end //end valid address loop
end //end reset-data assignment loops
end
endtask
//**************
// read_b
//**************
task read_b
(input reg [C_ADDRB_WIDTH-1:0] addr,
input reg reset);
reg [C_ADDRB_WIDTH-1:0] address;
integer i;
begin
if (reset) begin
memory_out_b <= #FLOP_DELAY initb_val;
sbiterr_in <= #FLOP_DELAY 1'b0;
dbiterr_in <= #FLOP_DELAY 1'b0;
rdaddrecc_in <= #FLOP_DELAY 0;
end else begin
// Shift the address
address = (addr/READ_ADDR_B_DIV);
if (address >= C_READ_DEPTH_B) begin
if (!C_DISABLE_WARN_BHV_RANGE) begin
$fdisplay(ADDRFILE,
"%0s WARNING: Address %0h is outside range for B Read",
C_CORENAME, addr);
end
memory_out_b <= #FLOP_DELAY 'bX;
sbiterr_in <= #FLOP_DELAY 1'bX;
dbiterr_in <= #FLOP_DELAY 1'bX;
rdaddrecc_in <= #FLOP_DELAY 'bX;
// valid address
end else begin
if (READ_WIDTH_RATIO_B==1) begin
memory_out_b <= #FLOP_DELAY memory[address*READ_WIDTH_RATIO_B];
end else begin
// Increment through the 'partial' words in the memory
for (i = 0; i < READ_WIDTH_RATIO_B; i = i + 1) begin
memory_out_b[MIN_WIDTH*i+:MIN_WIDTH]
<= #FLOP_DELAY memory[address*READ_WIDTH_RATIO_B + i];
end
end
if ((C_FAMILY_LOCALPARAM == "virtex7") && C_USE_ECC == 1) begin
rdaddrecc_in <= #FLOP_DELAY addr;
if (sbiterr_arr[addr] == 1) begin
sbiterr_in <= #FLOP_DELAY 1'b1;
end else begin
sbiterr_in <= #FLOP_DELAY 1'b0;
end
if (dbiterr_arr[addr] == 1) begin
dbiterr_in <= #FLOP_DELAY 1'b1;
end else begin
dbiterr_in <= #FLOP_DELAY 1'b0;
end
end else if (C_USE_SOFTECC == 1) begin
rdaddrecc_in <= #FLOP_DELAY addr;
if (softecc_sbiterr_arr[addr] == 1) begin
sbiterr_in <= #FLOP_DELAY 1'b1;
end else begin
sbiterr_in <= #FLOP_DELAY 1'b0;
end
if (softecc_dbiterr_arr[addr] == 1) begin
dbiterr_in <= #FLOP_DELAY 1'b1;
end else begin
dbiterr_in <= #FLOP_DELAY 1'b0;
end
end else begin
rdaddrecc_in <= #FLOP_DELAY 0;
dbiterr_in <= #FLOP_DELAY 1'b0;
sbiterr_in <= #FLOP_DELAY 1'b0;
end //end SOFTECC Loop
end //end Valid address loop
end //end reset-data assignment loops
end
endtask
//**************
// reset_a
//**************
task reset_a (input reg reset);
begin
if (reset) memory_out_a <= #FLOP_DELAY inita_val;
end
endtask
//**************
// reset_b
//**************
task reset_b (input reg reset);
begin
if (reset) memory_out_b <= #FLOP_DELAY initb_val;
end
endtask
//**************
// init_memory
//**************
task init_memory;
integer i, j, addr_step;
integer status;
reg [C_WRITE_WIDTH_A-1:0] default_data;
begin
default_data = 0;
//Display output message indicating that the behavioral model is being
//initialized
if (C_USE_DEFAULT_DATA || C_LOAD_INIT_FILE) $display(" Block Memory Generator module loading initial data...");
// Convert the default to hex
if (C_USE_DEFAULT_DATA) begin
if (default_data_str == "") begin
$fdisplay(ERRFILE, "%0s ERROR: C_DEFAULT_DATA is empty!", C_CORENAME);
$finish;
end else begin
status = $sscanf(default_data_str, "%h", default_data);
if (status == 0) begin
$fdisplay(ERRFILE, {"%0s ERROR: Unsuccessful hexadecimal read",
"from C_DEFAULT_DATA: %0s"},
C_CORENAME, C_DEFAULT_DATA);
$finish;
end
end
end
// Step by WRITE_ADDR_A_DIV through the memory via the
// Port A write interface to hit every location once
addr_step = WRITE_ADDR_A_DIV;
// 'write' to every location with default (or 0)
for (i = 0; i < C_WRITE_DEPTH_A*addr_step; i = i + addr_step) begin
write_a(i, {C_WEA_WIDTH{1'b1}}, default_data, 1'b0, 1'b0);
end
// Get specialized data from the MIF file
if (C_LOAD_INIT_FILE) begin
if (init_file_str == "") begin
$fdisplay(ERRFILE, "%0s ERROR: C_INIT_FILE_NAME is empty!",
C_CORENAME);
$finish;
end else begin
initfile = $fopen(init_file_str, "r");
if (initfile == 0) begin
$fdisplay(ERRFILE, {"%0s, ERROR: Problem opening",
"C_INIT_FILE_NAME: %0s!"},
C_CORENAME, init_file_str);
$finish;
end else begin
// loop through the mif file, loading in the data
for (i = 0; i < C_WRITE_DEPTH_A*addr_step; i = i + addr_step) begin
status = $fscanf(initfile, "%b", mif_data);
if (status > 0) begin
write_a(i, {C_WEA_WIDTH{1'b1}}, mif_data, 1'b0, 1'b0);
end
end
$fclose(initfile);
end //initfile
end //init_file_str
end //C_LOAD_INIT_FILE
if (C_USE_BRAM_BLOCK) begin
// Get specialized data from the MIF file
if (C_INIT_FILE != "NONE") begin
if (mem_init_file_str == "") begin
$fdisplay(ERRFILE, "%0s ERROR: C_INIT_FILE is empty!",
C_CORENAME);
$finish;
end else begin
meminitfile = $fopen(mem_init_file_str, "r");
if (meminitfile == 0) begin
$fdisplay(ERRFILE, {"%0s, ERROR: Problem opening",
"C_INIT_FILE: %0s!"},
C_CORENAME, mem_init_file_str);
$finish;
end else begin
// loop through the mif file, loading in the data
$readmemh(mem_init_file_str, memory );
for (j = 0; j < MAX_DEPTH-1 ; j = j + 1) begin
end
$fclose(meminitfile);
end //meminitfile
end //mem_init_file_str
end //C_INIT_FILE
end //C_USE_BRAM_BLOCK
//Display output message indicating that the behavioral model is done
//initializing
if (C_USE_DEFAULT_DATA || C_LOAD_INIT_FILE)
$display(" Block Memory Generator data initialization complete.");
end
endtask
//**************
// log2roundup
//**************
function integer log2roundup (input integer data_value);
integer width;
integer cnt;
begin
width = 0;
if (data_value > 1) begin
for(cnt=1 ; cnt < data_value ; cnt = cnt * 2) begin
width = width + 1;
end //loop
end //if
log2roundup = width;
end //log2roundup
endfunction
//*******************
// collision_check
//*******************
function integer collision_check (input reg [C_ADDRA_WIDTH-1:0] addr_a,
input integer iswrite_a,
input reg [C_ADDRB_WIDTH-1:0] addr_b,
input integer iswrite_b);
reg c_aw_bw, c_aw_br, c_ar_bw;
integer scaled_addra_to_waddrb_width;
integer scaled_addrb_to_waddrb_width;
integer scaled_addra_to_waddra_width;
integer scaled_addrb_to_waddra_width;
integer scaled_addra_to_raddrb_width;
integer scaled_addrb_to_raddrb_width;
integer scaled_addra_to_raddra_width;
integer scaled_addrb_to_raddra_width;
begin
c_aw_bw = 0;
c_aw_br = 0;
c_ar_bw = 0;
//If write_addr_b_width is smaller, scale both addresses to that width for
//comparing write_addr_a and write_addr_b; addr_a starts as C_ADDRA_WIDTH,
//scale it down to write_addr_b_width. addr_b starts as C_ADDRB_WIDTH,
//scale it down to write_addr_b_width. Once both are scaled to
//write_addr_b_width, compare.
scaled_addra_to_waddrb_width = ((addr_a)/
2**(C_ADDRA_WIDTH-write_addr_b_width));
scaled_addrb_to_waddrb_width = ((addr_b)/
2**(C_ADDRB_WIDTH-write_addr_b_width));
//If write_addr_a_width is smaller, scale both addresses to that width for
//comparing write_addr_a and write_addr_b; addr_a starts as C_ADDRA_WIDTH,
//scale it down to write_addr_a_width. addr_b starts as C_ADDRB_WIDTH,
//scale it down to write_addr_a_width. Once both are scaled to
//write_addr_a_width, compare.
scaled_addra_to_waddra_width = ((addr_a)/
2**(C_ADDRA_WIDTH-write_addr_a_width));
scaled_addrb_to_waddra_width = ((addr_b)/
2**(C_ADDRB_WIDTH-write_addr_a_width));
//If read_addr_b_width is smaller, scale both addresses to that width for
//comparing write_addr_a and read_addr_b; addr_a starts as C_ADDRA_WIDTH,
//scale it down to read_addr_b_width. addr_b starts as C_ADDRB_WIDTH,
//scale it down to read_addr_b_width. Once both are scaled to
//read_addr_b_width, compare.
scaled_addra_to_raddrb_width = ((addr_a)/
2**(C_ADDRA_WIDTH-read_addr_b_width));
scaled_addrb_to_raddrb_width = ((addr_b)/
2**(C_ADDRB_WIDTH-read_addr_b_width));
//If read_addr_a_width is smaller, scale both addresses to that width for
//comparing read_addr_a and write_addr_b; addr_a starts as C_ADDRA_WIDTH,
//scale it down to read_addr_a_width. addr_b starts as C_ADDRB_WIDTH,
//scale it down to read_addr_a_width. Once both are scaled to
//read_addr_a_width, compare.
scaled_addra_to_raddra_width = ((addr_a)/
2**(C_ADDRA_WIDTH-read_addr_a_width));
scaled_addrb_to_raddra_width = ((addr_b)/
2**(C_ADDRB_WIDTH-read_addr_a_width));
//Look for a write-write collision. In order for a write-write
//collision to exist, both ports must have a write transaction.
if (iswrite_a && iswrite_b) begin
if (write_addr_a_width > write_addr_b_width) begin
if (scaled_addra_to_waddrb_width == scaled_addrb_to_waddrb_width) begin
c_aw_bw = 1;
end else begin
c_aw_bw = 0;
end
end else begin
if (scaled_addrb_to_waddra_width == scaled_addra_to_waddra_width) begin
c_aw_bw = 1;
end else begin
c_aw_bw = 0;
end
end //width
end //iswrite_a and iswrite_b
//If the B port is reading (which means it is enabled - so could be
//a TX_WRITE or TX_READ), then check for a write-read collision).
//This could happen whether or not a write-write collision exists due
//to asymmetric write/read ports.
if (iswrite_a) begin
if (write_addr_a_width > read_addr_b_width) begin
if (scaled_addra_to_raddrb_width == scaled_addrb_to_raddrb_width) begin
c_aw_br = 1;
end else begin
c_aw_br = 0;
end
end else begin
if (scaled_addrb_to_waddra_width == scaled_addra_to_waddra_width) begin
c_aw_br = 1;
end else begin
c_aw_br = 0;
end
end //width
end //iswrite_a
//If the A port is reading (which means it is enabled - so could be
// a TX_WRITE or TX_READ), then check for a write-read collision).
//This could happen whether or not a write-write collision exists due
// to asymmetric write/read ports.
if (iswrite_b) begin
if (read_addr_a_width > write_addr_b_width) begin
if (scaled_addra_to_waddrb_width == scaled_addrb_to_waddrb_width) begin
c_ar_bw = 1;
end else begin
c_ar_bw = 0;
end
end else begin
if (scaled_addrb_to_raddra_width == scaled_addra_to_raddra_width) begin
c_ar_bw = 1;
end else begin
c_ar_bw = 0;
end
end //width
end //iswrite_b
collision_check = c_aw_bw | c_aw_br | c_ar_bw;
end
endfunction
//*******************************
// power on values
//*******************************
initial begin
// Load up the memory
init_memory;
// Load up the output registers and latches
if ($sscanf(inita_str, "%h", inita_val)) begin
memory_out_a = inita_val;
end else begin
memory_out_a = 0;
end
if ($sscanf(initb_str, "%h", initb_val)) begin
memory_out_b = initb_val;
end else begin
memory_out_b = 0;
end
sbiterr_in = 1'b0;
dbiterr_in = 1'b0;
rdaddrecc_in = 0;
// Determine the effective address widths for each of the 4 ports
write_addr_a_width = C_ADDRA_WIDTH - log2roundup(WRITE_ADDR_A_DIV);
read_addr_a_width = C_ADDRA_WIDTH - log2roundup(READ_ADDR_A_DIV);
write_addr_b_width = C_ADDRB_WIDTH - log2roundup(WRITE_ADDR_B_DIV);
read_addr_b_width = C_ADDRB_WIDTH - log2roundup(READ_ADDR_B_DIV);
$display("Block Memory Generator module %m is using a behavioral model for simulation which will not precisely model memory collision behavior.");
end
//***************************************************************************
// These are the main blocks which schedule read and write operations
// Note that the reset priority feature at the latch stage is only supported
// for Spartan-6. For other families, the default priority at the latch stage
// is "CE"
//***************************************************************************
// Synchronous clocks: schedule port operations with respect to
// both write operating modes
generate
if(C_COMMON_CLK && (C_WRITE_MODE_A == "WRITE_FIRST") && (C_WRITE_MODE_B ==
"WRITE_FIRST")) begin : com_clk_sched_wf_wf
always @(posedge CLKA) begin
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
if (rea_i) read_a(ADDRA, reseta_i);
//Read B
if (reb_i) read_b(ADDRB, resetb_i);
end
end
else
if(C_COMMON_CLK && (C_WRITE_MODE_A == "READ_FIRST") && (C_WRITE_MODE_B ==
"WRITE_FIRST")) begin : com_clk_sched_rf_wf
always @(posedge CLKA) begin
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
//Read B
if (reb_i) read_b(ADDRB, resetb_i);
//Read A
if (rea_i) read_a(ADDRA, reseta_i);
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
end
end
else
if(C_COMMON_CLK && (C_WRITE_MODE_A == "WRITE_FIRST") && (C_WRITE_MODE_B ==
"READ_FIRST")) begin : com_clk_sched_wf_rf
always @(posedge CLKA) begin
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
//Read A
if (rea_i) read_a(ADDRA, reseta_i);
//Read B
if (reb_i) read_b(ADDRB, resetb_i);
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
end
end
else
if(C_COMMON_CLK && (C_WRITE_MODE_A == "READ_FIRST") && (C_WRITE_MODE_B ==
"READ_FIRST")) begin : com_clk_sched_rf_rf
always @(posedge CLKA) begin
//Read A
if (rea_i) read_a(ADDRA, reseta_i);
//Read B
if (reb_i) read_b(ADDRB, resetb_i);
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
end
end
else if(C_COMMON_CLK && (C_WRITE_MODE_A =="WRITE_FIRST") && (C_WRITE_MODE_B ==
"NO_CHANGE")) begin : com_clk_sched_wf_nc
always @(posedge CLKA) begin
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
//Read A
if (rea_i) read_a(ADDRA, reseta_i);
//Read B
if (reb_i && (!web_i || resetb_i)) read_b(ADDRB, resetb_i);
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
end
end
else if(C_COMMON_CLK && (C_WRITE_MODE_A =="READ_FIRST") && (C_WRITE_MODE_B ==
"NO_CHANGE")) begin : com_clk_sched_rf_nc
always @(posedge CLKA) begin
//Read A
if (rea_i) read_a(ADDRA, reseta_i);
//Read B
if (reb_i && (!web_i || resetb_i)) read_b(ADDRB, resetb_i);
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
end
end
else if(C_COMMON_CLK && (C_WRITE_MODE_A =="NO_CHANGE") && (C_WRITE_MODE_B ==
"WRITE_FIRST")) begin : com_clk_sched_nc_wf
always @(posedge CLKA) begin
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
//Read A
if (rea_i && (!wea_i || reseta_i)) read_a(ADDRA, reseta_i);
//Read B
if (reb_i) read_b(ADDRB, resetb_i);
end
end
else if(C_COMMON_CLK && (C_WRITE_MODE_A =="NO_CHANGE") && (C_WRITE_MODE_B ==
"READ_FIRST")) begin : com_clk_sched_nc_rf
always @(posedge CLKA) begin
//Read B
if (reb_i) read_b(ADDRB, resetb_i);
//Read A
if (rea_i && (!wea_i || reseta_i)) read_a(ADDRA, reseta_i);
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
end
end
else if(C_COMMON_CLK && (C_WRITE_MODE_A =="NO_CHANGE") && (C_WRITE_MODE_B ==
"NO_CHANGE")) begin : com_clk_sched_nc_nc
always @(posedge CLKA) begin
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
//Read A
if (rea_i && (!wea_i || reseta_i)) read_a(ADDRA, reseta_i);
//Read B
if (reb_i && (!web_i || resetb_i)) read_b(ADDRB, resetb_i);
end
end
else if(C_COMMON_CLK) begin: com_clk_sched_default
always @(posedge CLKA) begin
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
//Read A
if (rea_i) read_a(ADDRA, reseta_i);
//Read B
if (reb_i) read_b(ADDRB, resetb_i);
end
end
endgenerate
// Asynchronous clocks: port operation is independent
generate
if((!C_COMMON_CLK) && (C_WRITE_MODE_A == "WRITE_FIRST")) begin : async_clk_sched_clka_wf
always @(posedge CLKA) begin
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
//Read A
if (rea_i) read_a(ADDRA, reseta_i);
end
end
else if((!C_COMMON_CLK) && (C_WRITE_MODE_A == "READ_FIRST")) begin : async_clk_sched_clka_rf
always @(posedge CLKA) begin
//Read A
if (rea_i) read_a(ADDRA, reseta_i);
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
end
end
else if((!C_COMMON_CLK) && (C_WRITE_MODE_A == "NO_CHANGE")) begin : async_clk_sched_clka_nc
always @(posedge CLKA) begin
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
//Read A
if (rea_i && (!wea_i || reseta_i)) read_a(ADDRA, reseta_i);
end
end
endgenerate
generate
if ((!C_COMMON_CLK) && (C_WRITE_MODE_B == "WRITE_FIRST")) begin: async_clk_sched_clkb_wf
always @(posedge CLKB) begin
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
//Read B
if (reb_i) read_b(ADDRB, resetb_i);
end
end
else if ((!C_COMMON_CLK) && (C_WRITE_MODE_B == "READ_FIRST")) begin: async_clk_sched_clkb_rf
always @(posedge CLKB) begin
//Read B
if (reb_i) read_b(ADDRB, resetb_i);
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
end
end
else if ((!C_COMMON_CLK) && (C_WRITE_MODE_B == "NO_CHANGE")) begin: async_clk_sched_clkb_nc
always @(posedge CLKB) begin
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
//Read B
if (reb_i && (!web_i || resetb_i)) read_b(ADDRB, resetb_i);
end
end
endgenerate
//***************************************************************
// Instantiate the variable depth output register stage module
//***************************************************************
// Port A
assign rsta_outp_stage = RSTA & (~SLEEP);
blk_mem_gen_v8_3_3_output_stage
#(.C_FAMILY (C_FAMILY),
.C_XDEVICEFAMILY (C_XDEVICEFAMILY),
.C_RST_TYPE ("SYNC"),
.C_HAS_RST (C_HAS_RSTA),
.C_RSTRAM (C_RSTRAM_A),
.C_RST_PRIORITY (C_RST_PRIORITY_A),
.C_INIT_VAL (C_INITA_VAL),
.C_HAS_EN (C_HAS_ENA),
.C_HAS_REGCE (C_HAS_REGCEA),
.C_DATA_WIDTH (C_READ_WIDTH_A),
.C_ADDRB_WIDTH (C_ADDRB_WIDTH),
.C_HAS_MEM_OUTPUT_REGS (C_HAS_MEM_OUTPUT_REGS_A),
.C_USE_SOFTECC (C_USE_SOFTECC),
.C_USE_ECC (C_USE_ECC),
.NUM_STAGES (NUM_OUTPUT_STAGES_A),
.C_EN_ECC_PIPE (0),
.FLOP_DELAY (FLOP_DELAY))
reg_a
(.CLK (CLKA),
.RST (rsta_outp_stage),//(RSTA),
.EN (ENA),
.REGCE (REGCEA),
.DIN_I (memory_out_a),
.DOUT (DOUTA),
.SBITERR_IN_I (1'b0),
.DBITERR_IN_I (1'b0),
.SBITERR (),
.DBITERR (),
.RDADDRECC_IN_I ({C_ADDRB_WIDTH{1'b0}}),
.ECCPIPECE (1'b0),
.RDADDRECC ()
);
assign rstb_outp_stage = RSTB & (~SLEEP);
// Port B
blk_mem_gen_v8_3_3_output_stage
#(.C_FAMILY (C_FAMILY),
.C_XDEVICEFAMILY (C_XDEVICEFAMILY),
.C_RST_TYPE ("SYNC"),
.C_HAS_RST (C_HAS_RSTB),
.C_RSTRAM (C_RSTRAM_B),
.C_RST_PRIORITY (C_RST_PRIORITY_B),
.C_INIT_VAL (C_INITB_VAL),
.C_HAS_EN (C_HAS_ENB),
.C_HAS_REGCE (C_HAS_REGCEB),
.C_DATA_WIDTH (C_READ_WIDTH_B),
.C_ADDRB_WIDTH (C_ADDRB_WIDTH),
.C_HAS_MEM_OUTPUT_REGS (C_HAS_MEM_OUTPUT_REGS_B),
.C_USE_SOFTECC (C_USE_SOFTECC),
.C_USE_ECC (C_USE_ECC),
.NUM_STAGES (NUM_OUTPUT_STAGES_B),
.C_EN_ECC_PIPE (C_EN_ECC_PIPE),
.FLOP_DELAY (FLOP_DELAY))
reg_b
(.CLK (CLKB),
.RST (rstb_outp_stage),//(RSTB),
.EN (ENB),
.REGCE (REGCEB),
.DIN_I (memory_out_b),
.DOUT (dout_i),
.SBITERR_IN_I (sbiterr_in),
.DBITERR_IN_I (dbiterr_in),
.SBITERR (sbiterr_i),
.DBITERR (dbiterr_i),
.RDADDRECC_IN_I (rdaddrecc_in),
.ECCPIPECE (ECCPIPECE),
.RDADDRECC (rdaddrecc_i)
);
//***************************************************************
// Instantiate the Input and Output register stages
//***************************************************************
blk_mem_gen_v8_3_3_softecc_output_reg_stage
#(.C_DATA_WIDTH (C_READ_WIDTH_B),
.C_ADDRB_WIDTH (C_ADDRB_WIDTH),
.C_HAS_SOFTECC_OUTPUT_REGS_B (C_HAS_SOFTECC_OUTPUT_REGS_B),
.C_USE_SOFTECC (C_USE_SOFTECC),
.FLOP_DELAY (FLOP_DELAY))
has_softecc_output_reg_stage
(.CLK (CLKB),
.DIN (dout_i),
.DOUT (DOUTB),
.SBITERR_IN (sbiterr_i),
.DBITERR_IN (dbiterr_i),
.SBITERR (sbiterr_sdp),
.DBITERR (dbiterr_sdp),
.RDADDRECC_IN (rdaddrecc_i),
.RDADDRECC (rdaddrecc_sdp)
);
//****************************************************
// Synchronous collision checks
//****************************************************
// CR 780544 : To make verilog model's collison warnings in consistant with
// vhdl model, the non-blocking assignments are replaced with blocking
// assignments.
generate if (!C_DISABLE_WARN_BHV_COLL && C_COMMON_CLK) begin : sync_coll
always @(posedge CLKA) begin
// Possible collision if both are enabled and the addresses match
if (ena_i && enb_i) begin
if (wea_i || web_i) begin
is_collision = collision_check(ADDRA, wea_i, ADDRB, web_i);
end else begin
is_collision = 0;
end
end else begin
is_collision = 0;
end
// If the write port is in READ_FIRST mode, there is no collision
if (C_WRITE_MODE_A=="READ_FIRST" && wea_i && !web_i) begin
is_collision = 0;
end
if (C_WRITE_MODE_B=="READ_FIRST" && web_i && !wea_i) begin
is_collision = 0;
end
// Only flag if one of the accesses is a write
if (is_collision && (wea_i || web_i)) begin
$fwrite(COLLFILE, "%0s collision detected at time: %0d, ",
C_CORENAME, $time);
$fwrite(COLLFILE, "A %0s address: %0h, B %0s address: %0h\n",
wea_i ? "write" : "read", ADDRA,
web_i ? "write" : "read", ADDRB);
end
end
//****************************************************
// Asynchronous collision checks
//****************************************************
end else if (!C_DISABLE_WARN_BHV_COLL && !C_COMMON_CLK) begin : async_coll
// Delay A and B addresses in order to mimic setup/hold times
wire [C_ADDRA_WIDTH-1:0] #COLL_DELAY addra_delay = ADDRA;
wire [0:0] #COLL_DELAY wea_delay = wea_i;
wire #COLL_DELAY ena_delay = ena_i;
wire [C_ADDRB_WIDTH-1:0] #COLL_DELAY addrb_delay = ADDRB;
wire [0:0] #COLL_DELAY web_delay = web_i;
wire #COLL_DELAY enb_delay = enb_i;
// Do the checks w/rt A
always @(posedge CLKA) begin
// Possible collision if both are enabled and the addresses match
if (ena_i && enb_i) begin
if (wea_i || web_i) begin
is_collision_a = collision_check(ADDRA, wea_i, ADDRB, web_i);
end else begin
is_collision_a = 0;
end
end else begin
is_collision_a = 0;
end
if (ena_i && enb_delay) begin
if(wea_i || web_delay) begin
is_collision_delay_a = collision_check(ADDRA, wea_i, addrb_delay,
web_delay);
end else begin
is_collision_delay_a = 0;
end
end else begin
is_collision_delay_a = 0;
end
// Only flag if B access is a write
if (is_collision_a && web_i) begin
$fwrite(COLLFILE, "%0s collision detected at time: %0d, ",
C_CORENAME, $time);
$fwrite(COLLFILE, "A %0s address: %0h, B write address: %0h\n",
wea_i ? "write" : "read", ADDRA, ADDRB);
end else if (is_collision_delay_a && web_delay) begin
$fwrite(COLLFILE, "%0s collision detected at time: %0d, ",
C_CORENAME, $time);
$fwrite(COLLFILE, "A %0s address: %0h, B write address: %0h\n",
wea_i ? "write" : "read", ADDRA, addrb_delay);
end
end
// Do the checks w/rt B
always @(posedge CLKB) begin
// Possible collision if both are enabled and the addresses match
if (ena_i && enb_i) begin
if (wea_i || web_i) begin
is_collision_b = collision_check(ADDRA, wea_i, ADDRB, web_i);
end else begin
is_collision_b = 0;
end
end else begin
is_collision_b = 0;
end
if (ena_delay && enb_i) begin
if (wea_delay || web_i) begin
is_collision_delay_b = collision_check(addra_delay, wea_delay, ADDRB,
web_i);
end else begin
is_collision_delay_b = 0;
end
end else begin
is_collision_delay_b = 0;
end
// Only flag if A access is a write
if (is_collision_b && wea_i) begin
$fwrite(COLLFILE, "%0s collision detected at time: %0d, ",
C_CORENAME, $time);
$fwrite(COLLFILE, "A write address: %0h, B %s address: %0h\n",
ADDRA, web_i ? "write" : "read", ADDRB);
end else if (is_collision_delay_b && wea_delay) begin
$fwrite(COLLFILE, "%0s collision detected at time: %0d, ",
C_CORENAME, $time);
$fwrite(COLLFILE, "A write address: %0h, B %s address: %0h\n",
addra_delay, web_i ? "write" : "read", ADDRB);
end
end
end
endgenerate
endmodule
//*****************************************************************************
// Top module wraps Input register and Memory module
//
// This module is the top-level behavioral model and this implements the memory
// module and the input registers
//*****************************************************************************
module blk_mem_gen_v8_3_3
#(parameter C_CORENAME = "blk_mem_gen_v8_3_3",
parameter C_FAMILY = "virtex7",
parameter C_XDEVICEFAMILY = "virtex7",
parameter C_ELABORATION_DIR = "",
parameter C_INTERFACE_TYPE = 0,
parameter C_USE_BRAM_BLOCK = 0,
parameter C_CTRL_ECC_ALGO = "NONE",
parameter C_ENABLE_32BIT_ADDRESS = 0,
parameter C_AXI_TYPE = 0,
parameter C_AXI_SLAVE_TYPE = 0,
parameter C_HAS_AXI_ID = 0,
parameter C_AXI_ID_WIDTH = 4,
parameter C_MEM_TYPE = 2,
parameter C_BYTE_SIZE = 9,
parameter C_ALGORITHM = 1,
parameter C_PRIM_TYPE = 3,
parameter C_LOAD_INIT_FILE = 0,
parameter C_INIT_FILE_NAME = "",
parameter C_INIT_FILE = "",
parameter C_USE_DEFAULT_DATA = 0,
parameter C_DEFAULT_DATA = "0",
//parameter C_RST_TYPE = "SYNC",
parameter C_HAS_RSTA = 0,
parameter C_RST_PRIORITY_A = "CE",
parameter C_RSTRAM_A = 0,
parameter C_INITA_VAL = "0",
parameter C_HAS_ENA = 1,
parameter C_HAS_REGCEA = 0,
parameter C_USE_BYTE_WEA = 0,
parameter C_WEA_WIDTH = 1,
parameter C_WRITE_MODE_A = "WRITE_FIRST",
parameter C_WRITE_WIDTH_A = 32,
parameter C_READ_WIDTH_A = 32,
parameter C_WRITE_DEPTH_A = 64,
parameter C_READ_DEPTH_A = 64,
parameter C_ADDRA_WIDTH = 5,
parameter C_HAS_RSTB = 0,
parameter C_RST_PRIORITY_B = "CE",
parameter C_RSTRAM_B = 0,
parameter C_INITB_VAL = "",
parameter C_HAS_ENB = 1,
parameter C_HAS_REGCEB = 0,
parameter C_USE_BYTE_WEB = 0,
parameter C_WEB_WIDTH = 1,
parameter C_WRITE_MODE_B = "WRITE_FIRST",
parameter C_WRITE_WIDTH_B = 32,
parameter C_READ_WIDTH_B = 32,
parameter C_WRITE_DEPTH_B = 64,
parameter C_READ_DEPTH_B = 64,
parameter C_ADDRB_WIDTH = 5,
parameter C_HAS_MEM_OUTPUT_REGS_A = 0,
parameter C_HAS_MEM_OUTPUT_REGS_B = 0,
parameter C_HAS_MUX_OUTPUT_REGS_A = 0,
parameter C_HAS_MUX_OUTPUT_REGS_B = 0,
parameter C_HAS_SOFTECC_INPUT_REGS_A = 0,
parameter C_HAS_SOFTECC_OUTPUT_REGS_B= 0,
parameter C_MUX_PIPELINE_STAGES = 0,
parameter C_USE_SOFTECC = 0,
parameter C_USE_ECC = 0,
parameter C_EN_ECC_PIPE = 0,
parameter C_HAS_INJECTERR = 0,
parameter C_SIM_COLLISION_CHECK = "NONE",
parameter C_COMMON_CLK = 1,
parameter C_DISABLE_WARN_BHV_COLL = 0,
parameter C_EN_SLEEP_PIN = 0,
parameter C_USE_URAM = 0,
parameter C_EN_RDADDRA_CHG = 0,
parameter C_EN_RDADDRB_CHG = 0,
parameter C_EN_DEEPSLEEP_PIN = 0,
parameter C_EN_SHUTDOWN_PIN = 0,
parameter C_EN_SAFETY_CKT = 0,
parameter C_COUNT_36K_BRAM = "",
parameter C_COUNT_18K_BRAM = "",
parameter C_EST_POWER_SUMMARY = "",
parameter C_DISABLE_WARN_BHV_RANGE = 0
)
(input clka,
input rsta,
input ena,
input regcea,
input [C_WEA_WIDTH-1:0] wea,
input [C_ADDRA_WIDTH-1:0] addra,
input [C_WRITE_WIDTH_A-1:0] dina,
output [C_READ_WIDTH_A-1:0] douta,
input clkb,
input rstb,
input enb,
input regceb,
input [C_WEB_WIDTH-1:0] web,
input [C_ADDRB_WIDTH-1:0] addrb,
input [C_WRITE_WIDTH_B-1:0] dinb,
output [C_READ_WIDTH_B-1:0] doutb,
input injectsbiterr,
input injectdbiterr,
output sbiterr,
output dbiterr,
output [C_ADDRB_WIDTH-1:0] rdaddrecc,
input eccpipece,
input sleep,
input deepsleep,
input shutdown,
output rsta_busy,
output rstb_busy,
//AXI BMG Input and Output Port Declarations
//AXI Global Signals
input s_aclk,
input s_aresetn,
//AXI Full/lite slave write (write side)
input [C_AXI_ID_WIDTH-1:0] s_axi_awid,
input [31:0] s_axi_awaddr,
input [7:0] s_axi_awlen,
input [2:0] s_axi_awsize,
input [1:0] s_axi_awburst,
input s_axi_awvalid,
output s_axi_awready,
input [C_WRITE_WIDTH_A-1:0] s_axi_wdata,
input [C_WEA_WIDTH-1:0] s_axi_wstrb,
input s_axi_wlast,
input s_axi_wvalid,
output s_axi_wready,
output [C_AXI_ID_WIDTH-1:0] s_axi_bid,
output [1:0] s_axi_bresp,
output s_axi_bvalid,
input s_axi_bready,
//AXI Full/lite slave read (write side)
input [C_AXI_ID_WIDTH-1:0] s_axi_arid,
input [31:0] s_axi_araddr,
input [7:0] s_axi_arlen,
input [2:0] s_axi_arsize,
input [1:0] s_axi_arburst,
input s_axi_arvalid,
output s_axi_arready,
output [C_AXI_ID_WIDTH-1:0] s_axi_rid,
output [C_WRITE_WIDTH_B-1:0] s_axi_rdata,
output [1:0] s_axi_rresp,
output s_axi_rlast,
output s_axi_rvalid,
input s_axi_rready,
//AXI Full/lite sideband signals
input s_axi_injectsbiterr,
input s_axi_injectdbiterr,
output s_axi_sbiterr,
output s_axi_dbiterr,
output [C_ADDRB_WIDTH-1:0] s_axi_rdaddrecc
);
//******************************
// Port and Generic Definitions
//******************************
//////////////////////////////////////////////////////////////////////////
// Generic Definitions
//////////////////////////////////////////////////////////////////////////
// C_CORENAME : Instance name of the Block Memory Generator core
// C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following
// options are available - "spartan3", "spartan6",
// "virtex4", "virtex5", "virtex6" and "virtex6l".
// C_MEM_TYPE : Designates memory type.
// It can be
// 0 - Single Port Memory
// 1 - Simple Dual Port Memory
// 2 - True Dual Port Memory
// 3 - Single Port Read Only Memory
// 4 - Dual Port Read Only Memory
// C_BYTE_SIZE : Size of a byte (8 or 9 bits)
// C_ALGORITHM : Designates the algorithm method used
// for constructing the memory.
// It can be Fixed_Primitives, Minimum_Area or
// Low_Power
// C_PRIM_TYPE : Designates the user selected primitive used to
// construct the memory.
//
// C_LOAD_INIT_FILE : Designates the use of an initialization file to
// initialize memory contents.
// C_INIT_FILE_NAME : Memory initialization file name.
// C_USE_DEFAULT_DATA : Designates whether to fill remaining
// initialization space with default data
// C_DEFAULT_DATA : Default value of all memory locations
// not initialized by the memory
// initialization file.
// C_RST_TYPE : Type of reset - Synchronous or Asynchronous
// C_HAS_RSTA : Determines the presence of the RSTA port
// C_RST_PRIORITY_A : Determines the priority between CE and SR for
// Port A.
// C_RSTRAM_A : Determines if special reset behavior is used for
// Port A
// C_INITA_VAL : The initialization value for Port A
// C_HAS_ENA : Determines the presence of the ENA port
// C_HAS_REGCEA : Determines the presence of the REGCEA port
// C_USE_BYTE_WEA : Determines if the Byte Write is used or not.
// C_WEA_WIDTH : The width of the WEA port
// C_WRITE_MODE_A : Configurable write mode for Port A. It can be
// WRITE_FIRST, READ_FIRST or NO_CHANGE.
// C_WRITE_WIDTH_A : Memory write width for Port A.
// C_READ_WIDTH_A : Memory read width for Port A.
// C_WRITE_DEPTH_A : Memory write depth for Port A.
// C_READ_DEPTH_A : Memory read depth for Port A.
// C_ADDRA_WIDTH : Width of the ADDRA input port
// C_HAS_RSTB : Determines the presence of the RSTB port
// C_RST_PRIORITY_B : Determines the priority between CE and SR for
// Port B.
// C_RSTRAM_B : Determines if special reset behavior is used for
// Port B
// C_INITB_VAL : The initialization value for Port B
// C_HAS_ENB : Determines the presence of the ENB port
// C_HAS_REGCEB : Determines the presence of the REGCEB port
// C_USE_BYTE_WEB : Determines if the Byte Write is used or not.
// C_WEB_WIDTH : The width of the WEB port
// C_WRITE_MODE_B : Configurable write mode for Port B. It can be
// WRITE_FIRST, READ_FIRST or NO_CHANGE.
// C_WRITE_WIDTH_B : Memory write width for Port B.
// C_READ_WIDTH_B : Memory read width for Port B.
// C_WRITE_DEPTH_B : Memory write depth for Port B.
// C_READ_DEPTH_B : Memory read depth for Port B.
// C_ADDRB_WIDTH : Width of the ADDRB input port
// C_HAS_MEM_OUTPUT_REGS_A : Designates the use of a register at the output
// of the RAM primitive for Port A.
// C_HAS_MEM_OUTPUT_REGS_B : Designates the use of a register at the output
// of the RAM primitive for Port B.
// C_HAS_MUX_OUTPUT_REGS_A : Designates the use of a register at the output
// of the MUX for Port A.
// C_HAS_MUX_OUTPUT_REGS_B : Designates the use of a register at the output
// of the MUX for Port B.
// C_HAS_SOFTECC_INPUT_REGS_A :
// C_HAS_SOFTECC_OUTPUT_REGS_B :
// C_MUX_PIPELINE_STAGES : Designates the number of pipeline stages in
// between the muxes.
// C_USE_SOFTECC : Determines if the Soft ECC feature is used or
// not. Only applicable Spartan-6
// C_USE_ECC : Determines if the ECC feature is used or
// not. Only applicable for V5 and V6
// C_HAS_INJECTERR : Determines if the error injection pins
// are present or not. If the ECC feature
// is not used, this value is defaulted to
// 0, else the following are the allowed
// values:
// 0 : No INJECTSBITERR or INJECTDBITERR pins
// 1 : Only INJECTSBITERR pin exists
// 2 : Only INJECTDBITERR pin exists
// 3 : Both INJECTSBITERR and INJECTDBITERR pins exist
// C_SIM_COLLISION_CHECK : Controls the disabling of Unisim model collision
// warnings. It can be "ALL", "NONE",
// "Warnings_Only" or "Generate_X_Only".
// C_COMMON_CLK : Determins if the core has a single CLK input.
// C_DISABLE_WARN_BHV_COLL : Controls the Behavioral Model Collision warnings
// C_DISABLE_WARN_BHV_RANGE: Controls the Behavioral Model Out of Range
// warnings
//////////////////////////////////////////////////////////////////////////
// Port Definitions
//////////////////////////////////////////////////////////////////////////
// CLKA : Clock to synchronize all read and write operations of Port A.
// RSTA : Reset input to reset memory outputs to a user-defined
// reset state for Port A.
// ENA : Enable all read and write operations of Port A.
// REGCEA : Register Clock Enable to control each pipeline output
// register stages for Port A.
// WEA : Write Enable to enable all write operations of Port A.
// ADDRA : Address of Port A.
// DINA : Data input of Port A.
// DOUTA : Data output of Port A.
// CLKB : Clock to synchronize all read and write operations of Port B.
// RSTB : Reset input to reset memory outputs to a user-defined
// reset state for Port B.
// ENB : Enable all read and write operations of Port B.
// REGCEB : Register Clock Enable to control each pipeline output
// register stages for Port B.
// WEB : Write Enable to enable all write operations of Port B.
// ADDRB : Address of Port B.
// DINB : Data input of Port B.
// DOUTB : Data output of Port B.
// INJECTSBITERR : Single Bit ECC Error Injection Pin.
// INJECTDBITERR : Double Bit ECC Error Injection Pin.
// SBITERR : Output signal indicating that a Single Bit ECC Error has been
// detected and corrected.
// DBITERR : Output signal indicating that a Double Bit ECC Error has been
// detected.
// RDADDRECC : Read Address Output signal indicating address at which an
// ECC error has occurred.
//////////////////////////////////////////////////////////////////////////
wire SBITERR;
wire DBITERR;
wire S_AXI_AWREADY;
wire S_AXI_WREADY;
wire S_AXI_BVALID;
wire S_AXI_ARREADY;
wire S_AXI_RLAST;
wire S_AXI_RVALID;
wire S_AXI_SBITERR;
wire S_AXI_DBITERR;
wire [C_WEA_WIDTH-1:0] WEA = wea;
wire [C_ADDRA_WIDTH-1:0] ADDRA = addra;
wire [C_WRITE_WIDTH_A-1:0] DINA = dina;
wire [C_READ_WIDTH_A-1:0] DOUTA;
wire [C_WEB_WIDTH-1:0] WEB = web;
wire [C_ADDRB_WIDTH-1:0] ADDRB = addrb;
wire [C_WRITE_WIDTH_B-1:0] DINB = dinb;
wire [C_READ_WIDTH_B-1:0] DOUTB;
wire [C_ADDRB_WIDTH-1:0] RDADDRECC;
wire [C_AXI_ID_WIDTH-1:0] S_AXI_AWID = s_axi_awid;
wire [31:0] S_AXI_AWADDR = s_axi_awaddr;
wire [7:0] S_AXI_AWLEN = s_axi_awlen;
wire [2:0] S_AXI_AWSIZE = s_axi_awsize;
wire [1:0] S_AXI_AWBURST = s_axi_awburst;
wire [C_WRITE_WIDTH_A-1:0] S_AXI_WDATA = s_axi_wdata;
wire [C_WEA_WIDTH-1:0] S_AXI_WSTRB = s_axi_wstrb;
wire [C_AXI_ID_WIDTH-1:0] S_AXI_BID;
wire [1:0] S_AXI_BRESP;
wire [C_AXI_ID_WIDTH-1:0] S_AXI_ARID = s_axi_arid;
wire [31:0] S_AXI_ARADDR = s_axi_araddr;
wire [7:0] S_AXI_ARLEN = s_axi_arlen;
wire [2:0] S_AXI_ARSIZE = s_axi_arsize;
wire [1:0] S_AXI_ARBURST = s_axi_arburst;
wire [C_AXI_ID_WIDTH-1:0] S_AXI_RID;
wire [C_WRITE_WIDTH_B-1:0] S_AXI_RDATA;
wire [1:0] S_AXI_RRESP;
wire [C_ADDRB_WIDTH-1:0] S_AXI_RDADDRECC;
// Added to fix the simulation warning #CR731605
wire [C_WEB_WIDTH-1:0] WEB_parameterized = 0;
wire ECCPIPECE;
wire SLEEP;
reg RSTA_BUSY = 0;
reg RSTB_BUSY = 0;
// Declaration of internal signals to avoid warnings #927399
wire CLKA;
wire RSTA;
wire ENA;
wire REGCEA;
wire CLKB;
wire RSTB;
wire ENB;
wire REGCEB;
wire INJECTSBITERR;
wire INJECTDBITERR;
wire S_ACLK;
wire S_ARESETN;
wire S_AXI_AWVALID;
wire S_AXI_WLAST;
wire S_AXI_WVALID;
wire S_AXI_BREADY;
wire S_AXI_ARVALID;
wire S_AXI_RREADY;
wire S_AXI_INJECTSBITERR;
wire S_AXI_INJECTDBITERR;
assign CLKA = clka;
assign RSTA = rsta;
assign ENA = ena;
assign REGCEA = regcea;
assign CLKB = clkb;
assign RSTB = rstb;
assign ENB = enb;
assign REGCEB = regceb;
assign INJECTSBITERR = injectsbiterr;
assign INJECTDBITERR = injectdbiterr;
assign ECCPIPECE = eccpipece;
assign SLEEP = sleep;
assign sbiterr = SBITERR;
assign dbiterr = DBITERR;
assign S_ACLK = s_aclk;
assign S_ARESETN = s_aresetn;
assign S_AXI_AWVALID = s_axi_awvalid;
assign s_axi_awready = S_AXI_AWREADY;
assign S_AXI_WLAST = s_axi_wlast;
assign S_AXI_WVALID = s_axi_wvalid;
assign s_axi_wready = S_AXI_WREADY;
assign s_axi_bvalid = S_AXI_BVALID;
assign S_AXI_BREADY = s_axi_bready;
assign S_AXI_ARVALID = s_axi_arvalid;
assign s_axi_arready = S_AXI_ARREADY;
assign s_axi_rlast = S_AXI_RLAST;
assign s_axi_rvalid = S_AXI_RVALID;
assign S_AXI_RREADY = s_axi_rready;
assign S_AXI_INJECTSBITERR = s_axi_injectsbiterr;
assign S_AXI_INJECTDBITERR = s_axi_injectdbiterr;
assign s_axi_sbiterr = S_AXI_SBITERR;
assign s_axi_dbiterr = S_AXI_DBITERR;
assign rsta_busy = RSTA_BUSY;
assign rstb_busy = RSTB_BUSY;
assign doutb = DOUTB;
assign douta = DOUTA;
assign rdaddrecc = RDADDRECC;
assign s_axi_bid = S_AXI_BID;
assign s_axi_bresp = S_AXI_BRESP;
assign s_axi_rid = S_AXI_RID;
assign s_axi_rdata = S_AXI_RDATA;
assign s_axi_rresp = S_AXI_RRESP;
assign s_axi_rdaddrecc = S_AXI_RDADDRECC;
localparam FLOP_DELAY = 100; // 100 ps
reg injectsbiterr_in;
reg injectdbiterr_in;
reg rsta_in;
reg ena_in;
reg regcea_in;
reg [C_WEA_WIDTH-1:0] wea_in;
reg [C_ADDRA_WIDTH-1:0] addra_in;
reg [C_WRITE_WIDTH_A-1:0] dina_in;
wire [C_ADDRA_WIDTH-1:0] s_axi_awaddr_out_c;
wire [C_ADDRB_WIDTH-1:0] s_axi_araddr_out_c;
wire s_axi_wr_en_c;
wire s_axi_rd_en_c;
wire s_aresetn_a_c;
wire [7:0] s_axi_arlen_c ;
wire [C_AXI_ID_WIDTH-1 : 0] s_axi_rid_c;
wire [C_WRITE_WIDTH_B-1 : 0] s_axi_rdata_c;
wire [1:0] s_axi_rresp_c;
wire s_axi_rlast_c;
wire s_axi_rvalid_c;
wire s_axi_rready_c;
wire regceb_c;
localparam C_AXI_PAYLOAD = (C_HAS_MUX_OUTPUT_REGS_B == 1)?C_WRITE_WIDTH_B+C_AXI_ID_WIDTH+3:C_AXI_ID_WIDTH+3;
wire [C_AXI_PAYLOAD-1 : 0] s_axi_payload_c;
wire [C_AXI_PAYLOAD-1 : 0] m_axi_payload_c;
// Safety logic related signals
reg [4:0] RSTA_SHFT_REG = 0;
reg POR_A = 0;
reg [4:0] RSTB_SHFT_REG = 0;
reg POR_B = 0;
reg ENA_dly = 0;
reg ENA_dly_D = 0;
reg ENB_dly = 0;
reg ENB_dly_D = 0;
wire RSTA_I_SAFE;
wire RSTB_I_SAFE;
wire ENA_I_SAFE;
wire ENB_I_SAFE;
reg ram_rstram_a_busy = 0;
reg ram_rstreg_a_busy = 0;
reg ram_rstram_b_busy = 0;
reg ram_rstreg_b_busy = 0;
reg ENA_dly_reg = 0;
reg ENB_dly_reg = 0;
reg ENA_dly_reg_D = 0;
reg ENB_dly_reg_D = 0;
//**************
// log2roundup
//**************
function integer log2roundup (input integer data_value);
integer width;
integer cnt;
begin
width = 0;
if (data_value > 1) begin
for(cnt=1 ; cnt < data_value ; cnt = cnt * 2) begin
width = width + 1;
end //loop
end //if
log2roundup = width;
end //log2roundup
endfunction
//**************
// log2int
//**************
function integer log2int (input integer data_value);
integer width;
integer cnt;
begin
width = 0;
cnt= data_value;
for(cnt=data_value ; cnt >1 ; cnt = cnt / 2) begin
width = width + 1;
end //loop
log2int = width;
end //log2int
endfunction
//**************************************************************************
// FUNCTION : divroundup
// Returns the ceiling value of the division
// Data_value - the quantity to be divided, dividend
// Divisor - the value to divide the data_value by
//**************************************************************************
function integer divroundup (input integer data_value,input integer divisor);
integer div;
begin
div = data_value/divisor;
if ((data_value % divisor) != 0) begin
div = div+1;
end //if
divroundup = div;
end //if
endfunction
localparam AXI_FULL_MEMORY_SLAVE = ((C_AXI_SLAVE_TYPE == 0 && C_AXI_TYPE == 1)?1:0);
localparam C_AXI_ADDR_WIDTH_MSB = C_ADDRA_WIDTH+log2roundup(C_WRITE_WIDTH_A/8);
localparam C_AXI_ADDR_WIDTH = C_AXI_ADDR_WIDTH_MSB;
//Data Width Number of LSB address bits to be discarded
//1 to 16 1
//17 to 32 2
//33 to 64 3
//65 to 128 4
//129 to 256 5
//257 to 512 6
//513 to 1024 7
// The following two constants determine this.
localparam LOWER_BOUND_VAL = (log2roundup(divroundup(C_WRITE_WIDTH_A,8) == 0))?0:(log2roundup(divroundup(C_WRITE_WIDTH_A,8)));
localparam C_AXI_ADDR_WIDTH_LSB = ((AXI_FULL_MEMORY_SLAVE == 1)?0:LOWER_BOUND_VAL);
localparam C_AXI_OS_WR = 2;
//***********************************************
// INPUT REGISTERS.
//***********************************************
generate if (C_HAS_SOFTECC_INPUT_REGS_A==0) begin : no_softecc_input_reg_stage
always @* begin
injectsbiterr_in = INJECTSBITERR;
injectdbiterr_in = INJECTDBITERR;
rsta_in = RSTA;
ena_in = ENA;
regcea_in = REGCEA;
wea_in = WEA;
addra_in = ADDRA;
dina_in = DINA;
end //end always
end //end no_softecc_input_reg_stage
endgenerate
generate if (C_HAS_SOFTECC_INPUT_REGS_A==1) begin : has_softecc_input_reg_stage
always @(posedge CLKA) begin
injectsbiterr_in <= #FLOP_DELAY INJECTSBITERR;
injectdbiterr_in <= #FLOP_DELAY INJECTDBITERR;
rsta_in <= #FLOP_DELAY RSTA;
ena_in <= #FLOP_DELAY ENA;
regcea_in <= #FLOP_DELAY REGCEA;
wea_in <= #FLOP_DELAY WEA;
addra_in <= #FLOP_DELAY ADDRA;
dina_in <= #FLOP_DELAY DINA;
end //end always
end //end input_reg_stages generate statement
endgenerate
//**************************************************************************
// NO SAFETY LOGIC
//**************************************************************************
generate
if (C_EN_SAFETY_CKT == 0) begin : NO_SAFETY_CKT_GEN
assign ENA_I_SAFE = ena_in;
assign ENB_I_SAFE = ENB;
assign RSTA_I_SAFE = rsta_in;
assign RSTB_I_SAFE = RSTB;
end
endgenerate
//***************************************************************************
// SAFETY LOGIC
// Power-ON Reset Generation
//***************************************************************************
generate
if (C_EN_SAFETY_CKT == 1) begin
always @(posedge clka) RSTA_SHFT_REG <= #FLOP_DELAY {RSTA_SHFT_REG[3:0],1'b1} ;
always @(posedge clka) POR_A <= #FLOP_DELAY RSTA_SHFT_REG[4] ^ RSTA_SHFT_REG[0];
always @(posedge clkb) RSTB_SHFT_REG <= #FLOP_DELAY {RSTB_SHFT_REG[3:0],1'b1} ;
always @(posedge clkb) POR_B <= #FLOP_DELAY RSTB_SHFT_REG[4] ^ RSTB_SHFT_REG[0];
assign RSTA_I_SAFE = rsta_in | POR_A;
assign RSTB_I_SAFE = (C_MEM_TYPE == 0 || C_MEM_TYPE == 3) ? 1'b0 : (RSTB | POR_B);
end
endgenerate
//-----------------------------------------------------------------------------
// -- RSTA/B_BUSY Generation
//-----------------------------------------------------------------------------
generate
if ((C_HAS_MEM_OUTPUT_REGS_A==0 || (C_HAS_MEM_OUTPUT_REGS_A==1 && C_RSTRAM_A==1)) && (C_EN_SAFETY_CKT == 1)) begin : RSTA_BUSY_NO_REG
always @(*) ram_rstram_a_busy = RSTA_I_SAFE | ENA_dly | ENA_dly_D;
always @(posedge clka) RSTA_BUSY <= #FLOP_DELAY ram_rstram_a_busy;
end
endgenerate
generate
if (C_HAS_MEM_OUTPUT_REGS_A==1 && C_RSTRAM_A==0 && C_EN_SAFETY_CKT == 1) begin : RSTA_BUSY_WITH_REG
always @(*) ram_rstreg_a_busy = RSTA_I_SAFE | ENA_dly_reg | ENA_dly_reg_D;
always @(posedge clka) RSTA_BUSY <= #FLOP_DELAY ram_rstreg_a_busy;
end
endgenerate
generate
if ( (C_MEM_TYPE == 0 || C_MEM_TYPE == 3) && C_EN_SAFETY_CKT == 1) begin : SPRAM_RST_BUSY
always @(*) RSTB_BUSY = 1'b0;
end
endgenerate
generate
if ( (C_HAS_MEM_OUTPUT_REGS_B==0 || (C_HAS_MEM_OUTPUT_REGS_B==1 && C_RSTRAM_B==1)) && (C_MEM_TYPE != 0 && C_MEM_TYPE != 3) && C_EN_SAFETY_CKT == 1) begin : RSTB_BUSY_NO_REG
always @(*) ram_rstram_b_busy = RSTB_I_SAFE | ENB_dly | ENB_dly_D;
always @(posedge clkb) RSTB_BUSY <= #FLOP_DELAY ram_rstram_b_busy;
end
endgenerate
generate
if (C_HAS_MEM_OUTPUT_REGS_B==1 && C_RSTRAM_B==0 && C_MEM_TYPE != 0 && C_MEM_TYPE != 3 && C_EN_SAFETY_CKT == 1) begin : RSTB_BUSY_WITH_REG
always @(*) ram_rstreg_b_busy = RSTB_I_SAFE | ENB_dly_reg | ENB_dly_reg_D;
always @(posedge clkb) RSTB_BUSY <= #FLOP_DELAY ram_rstreg_b_busy;
end
endgenerate
//-----------------------------------------------------------------------------
// -- ENA/ENB Generation
//-----------------------------------------------------------------------------
generate
if ((C_HAS_MEM_OUTPUT_REGS_A==0 || (C_HAS_MEM_OUTPUT_REGS_A==1 && C_RSTRAM_A==1)) && C_EN_SAFETY_CKT == 1) begin : ENA_NO_REG
always @(posedge clka) begin
ENA_dly <= #FLOP_DELAY RSTA_I_SAFE;
ENA_dly_D <= #FLOP_DELAY ENA_dly;
end
assign ENA_I_SAFE = (C_HAS_ENA == 0)? 1'b1 : (ENA_dly_D | ena_in);
end
endgenerate
generate
if ( (C_HAS_MEM_OUTPUT_REGS_A==1 && C_RSTRAM_A==0) && C_EN_SAFETY_CKT == 1) begin : ENA_WITH_REG
always @(posedge clka) begin
ENA_dly_reg <= #FLOP_DELAY RSTA_I_SAFE;
ENA_dly_reg_D <= #FLOP_DELAY ENA_dly_reg;
end
assign ENA_I_SAFE = (C_HAS_ENA == 0)? 1'b1 : (ENA_dly_reg_D | ena_in);
end
endgenerate
generate
if (C_MEM_TYPE == 0 || C_MEM_TYPE == 3) begin : SPRAM_ENB
assign ENB_I_SAFE = 1'b0;
end
endgenerate
generate
if ((C_HAS_MEM_OUTPUT_REGS_B==0 || (C_HAS_MEM_OUTPUT_REGS_B==1 && C_RSTRAM_B==1)) && C_MEM_TYPE != 0 && C_MEM_TYPE != 3 && C_EN_SAFETY_CKT == 1) begin : ENB_NO_REG
always @(posedge clkb) begin : PROC_ENB_GEN
ENB_dly <= #FLOP_DELAY RSTB_I_SAFE;
ENB_dly_D <= #FLOP_DELAY ENB_dly;
end
assign ENB_I_SAFE = (C_HAS_ENB == 0)? 1'b1 : (ENB_dly_D | ENB);
end
endgenerate
generate
if (C_HAS_MEM_OUTPUT_REGS_B==1 && C_RSTRAM_B==0 && C_MEM_TYPE != 0 && C_MEM_TYPE != 3 && C_EN_SAFETY_CKT == 1)begin : ENB_WITH_REG
always @(posedge clkb) begin : PROC_ENB_GEN
ENB_dly_reg <= #FLOP_DELAY RSTB_I_SAFE;
ENB_dly_reg_D <= #FLOP_DELAY ENB_dly_reg;
end
assign ENB_I_SAFE = (C_HAS_ENB == 0)? 1'b1 : (ENB_dly_reg_D | ENB);
end
endgenerate
generate if ((C_INTERFACE_TYPE == 0) && (C_ENABLE_32BIT_ADDRESS == 0)) begin : native_mem_module
blk_mem_gen_v8_3_3_mem_module
#(.C_CORENAME (C_CORENAME),
.C_FAMILY (C_FAMILY),
.C_XDEVICEFAMILY (C_XDEVICEFAMILY),
.C_MEM_TYPE (C_MEM_TYPE),
.C_BYTE_SIZE (C_BYTE_SIZE),
.C_ALGORITHM (C_ALGORITHM),
.C_USE_BRAM_BLOCK (C_USE_BRAM_BLOCK),
.C_PRIM_TYPE (C_PRIM_TYPE),
.C_LOAD_INIT_FILE (C_LOAD_INIT_FILE),
.C_INIT_FILE_NAME (C_INIT_FILE_NAME),
.C_INIT_FILE (C_INIT_FILE),
.C_USE_DEFAULT_DATA (C_USE_DEFAULT_DATA),
.C_DEFAULT_DATA (C_DEFAULT_DATA),
.C_RST_TYPE ("SYNC"),
.C_HAS_RSTA (C_HAS_RSTA),
.C_RST_PRIORITY_A (C_RST_PRIORITY_A),
.C_RSTRAM_A (C_RSTRAM_A),
.C_INITA_VAL (C_INITA_VAL),
.C_HAS_ENA (C_HAS_ENA),
.C_HAS_REGCEA (C_HAS_REGCEA),
.C_USE_BYTE_WEA (C_USE_BYTE_WEA),
.C_WEA_WIDTH (C_WEA_WIDTH),
.C_WRITE_MODE_A (C_WRITE_MODE_A),
.C_WRITE_WIDTH_A (C_WRITE_WIDTH_A),
.C_READ_WIDTH_A (C_READ_WIDTH_A),
.C_WRITE_DEPTH_A (C_WRITE_DEPTH_A),
.C_READ_DEPTH_A (C_READ_DEPTH_A),
.C_ADDRA_WIDTH (C_ADDRA_WIDTH),
.C_HAS_RSTB (C_HAS_RSTB),
.C_RST_PRIORITY_B (C_RST_PRIORITY_B),
.C_RSTRAM_B (C_RSTRAM_B),
.C_INITB_VAL (C_INITB_VAL),
.C_HAS_ENB (C_HAS_ENB),
.C_HAS_REGCEB (C_HAS_REGCEB),
.C_USE_BYTE_WEB (C_USE_BYTE_WEB),
.C_WEB_WIDTH (C_WEB_WIDTH),
.C_WRITE_MODE_B (C_WRITE_MODE_B),
.C_WRITE_WIDTH_B (C_WRITE_WIDTH_B),
.C_READ_WIDTH_B (C_READ_WIDTH_B),
.C_WRITE_DEPTH_B (C_WRITE_DEPTH_B),
.C_READ_DEPTH_B (C_READ_DEPTH_B),
.C_ADDRB_WIDTH (C_ADDRB_WIDTH),
.C_HAS_MEM_OUTPUT_REGS_A (C_HAS_MEM_OUTPUT_REGS_A),
.C_HAS_MEM_OUTPUT_REGS_B (C_HAS_MEM_OUTPUT_REGS_B),
.C_HAS_MUX_OUTPUT_REGS_A (C_HAS_MUX_OUTPUT_REGS_A),
.C_HAS_MUX_OUTPUT_REGS_B (C_HAS_MUX_OUTPUT_REGS_B),
.C_HAS_SOFTECC_INPUT_REGS_A (C_HAS_SOFTECC_INPUT_REGS_A),
.C_HAS_SOFTECC_OUTPUT_REGS_B (C_HAS_SOFTECC_OUTPUT_REGS_B),
.C_MUX_PIPELINE_STAGES (C_MUX_PIPELINE_STAGES),
.C_USE_SOFTECC (C_USE_SOFTECC),
.C_USE_ECC (C_USE_ECC),
.C_HAS_INJECTERR (C_HAS_INJECTERR),
.C_SIM_COLLISION_CHECK (C_SIM_COLLISION_CHECK),
.C_COMMON_CLK (C_COMMON_CLK),
.FLOP_DELAY (FLOP_DELAY),
.C_DISABLE_WARN_BHV_COLL (C_DISABLE_WARN_BHV_COLL),
.C_EN_ECC_PIPE (C_EN_ECC_PIPE),
.C_DISABLE_WARN_BHV_RANGE (C_DISABLE_WARN_BHV_RANGE))
blk_mem_gen_v8_3_3_inst
(.CLKA (CLKA),
.RSTA (RSTA_I_SAFE),//(rsta_in),
.ENA (ENA_I_SAFE),//(ena_in),
.REGCEA (regcea_in),
.WEA (wea_in),
.ADDRA (addra_in),
.DINA (dina_in),
.DOUTA (DOUTA),
.CLKB (CLKB),
.RSTB (RSTB_I_SAFE),//(RSTB),
.ENB (ENB_I_SAFE),//(ENB),
.REGCEB (REGCEB),
.WEB (WEB),
.ADDRB (ADDRB),
.DINB (DINB),
.DOUTB (DOUTB),
.INJECTSBITERR (injectsbiterr_in),
.INJECTDBITERR (injectdbiterr_in),
.ECCPIPECE (ECCPIPECE),
.SLEEP (SLEEP),
.SBITERR (SBITERR),
.DBITERR (DBITERR),
.RDADDRECC (RDADDRECC)
);
end
endgenerate
generate if((C_INTERFACE_TYPE == 0) && (C_ENABLE_32BIT_ADDRESS == 1)) begin : native_mem_mapped_module
localparam C_ADDRA_WIDTH_ACTUAL = log2roundup(C_WRITE_DEPTH_A);
localparam C_ADDRB_WIDTH_ACTUAL = log2roundup(C_WRITE_DEPTH_B);
localparam C_ADDRA_WIDTH_MSB = C_ADDRA_WIDTH_ACTUAL+log2int(C_WRITE_WIDTH_A/8);
localparam C_ADDRB_WIDTH_MSB = C_ADDRB_WIDTH_ACTUAL+log2int(C_WRITE_WIDTH_B/8);
// localparam C_ADDRA_WIDTH_MSB = C_ADDRA_WIDTH_ACTUAL+log2roundup(C_WRITE_WIDTH_A/8);
// localparam C_ADDRB_WIDTH_MSB = C_ADDRB_WIDTH_ACTUAL+log2roundup(C_WRITE_WIDTH_B/8);
localparam C_MEM_MAP_ADDRA_WIDTH_MSB = C_ADDRA_WIDTH_MSB;
localparam C_MEM_MAP_ADDRB_WIDTH_MSB = C_ADDRB_WIDTH_MSB;
// Data Width Number of LSB address bits to be discarded
// 1 to 16 1
// 17 to 32 2
// 33 to 64 3
// 65 to 128 4
// 129 to 256 5
// 257 to 512 6
// 513 to 1024 7
// The following two constants determine this.
localparam MEM_MAP_LOWER_BOUND_VAL_A = (log2int(divroundup(C_WRITE_WIDTH_A,8)==0)) ? 0:(log2int(divroundup(C_WRITE_WIDTH_A,8)));
localparam MEM_MAP_LOWER_BOUND_VAL_B = (log2int(divroundup(C_WRITE_WIDTH_A,8)==0)) ? 0:(log2int(divroundup(C_WRITE_WIDTH_A,8)));
localparam C_MEM_MAP_ADDRA_WIDTH_LSB = MEM_MAP_LOWER_BOUND_VAL_A;
localparam C_MEM_MAP_ADDRB_WIDTH_LSB = MEM_MAP_LOWER_BOUND_VAL_B;
wire [C_ADDRB_WIDTH_ACTUAL-1 :0] rdaddrecc_i;
wire [C_ADDRB_WIDTH-1:C_MEM_MAP_ADDRB_WIDTH_MSB] msb_zero_i;
wire [C_MEM_MAP_ADDRB_WIDTH_LSB-1:0] lsb_zero_i;
assign msb_zero_i = 0;
assign lsb_zero_i = 0;
assign RDADDRECC = {msb_zero_i,rdaddrecc_i,lsb_zero_i};
blk_mem_gen_v8_3_3_mem_module
#(.C_CORENAME (C_CORENAME),
.C_FAMILY (C_FAMILY),
.C_XDEVICEFAMILY (C_XDEVICEFAMILY),
.C_MEM_TYPE (C_MEM_TYPE),
.C_BYTE_SIZE (C_BYTE_SIZE),
.C_USE_BRAM_BLOCK (C_USE_BRAM_BLOCK),
.C_ALGORITHM (C_ALGORITHM),
.C_PRIM_TYPE (C_PRIM_TYPE),
.C_LOAD_INIT_FILE (C_LOAD_INIT_FILE),
.C_INIT_FILE_NAME (C_INIT_FILE_NAME),
.C_INIT_FILE (C_INIT_FILE),
.C_USE_DEFAULT_DATA (C_USE_DEFAULT_DATA),
.C_DEFAULT_DATA (C_DEFAULT_DATA),
.C_RST_TYPE ("SYNC"),
.C_HAS_RSTA (C_HAS_RSTA),
.C_RST_PRIORITY_A (C_RST_PRIORITY_A),
.C_RSTRAM_A (C_RSTRAM_A),
.C_INITA_VAL (C_INITA_VAL),
.C_HAS_ENA (C_HAS_ENA),
.C_HAS_REGCEA (C_HAS_REGCEA),
.C_USE_BYTE_WEA (C_USE_BYTE_WEA),
.C_WEA_WIDTH (C_WEA_WIDTH),
.C_WRITE_MODE_A (C_WRITE_MODE_A),
.C_WRITE_WIDTH_A (C_WRITE_WIDTH_A),
.C_READ_WIDTH_A (C_READ_WIDTH_A),
.C_WRITE_DEPTH_A (C_WRITE_DEPTH_A),
.C_READ_DEPTH_A (C_READ_DEPTH_A),
.C_ADDRA_WIDTH (C_ADDRA_WIDTH_ACTUAL),
.C_HAS_RSTB (C_HAS_RSTB),
.C_RST_PRIORITY_B (C_RST_PRIORITY_B),
.C_RSTRAM_B (C_RSTRAM_B),
.C_INITB_VAL (C_INITB_VAL),
.C_HAS_ENB (C_HAS_ENB),
.C_HAS_REGCEB (C_HAS_REGCEB),
.C_USE_BYTE_WEB (C_USE_BYTE_WEB),
.C_WEB_WIDTH (C_WEB_WIDTH),
.C_WRITE_MODE_B (C_WRITE_MODE_B),
.C_WRITE_WIDTH_B (C_WRITE_WIDTH_B),
.C_READ_WIDTH_B (C_READ_WIDTH_B),
.C_WRITE_DEPTH_B (C_WRITE_DEPTH_B),
.C_READ_DEPTH_B (C_READ_DEPTH_B),
.C_ADDRB_WIDTH (C_ADDRB_WIDTH_ACTUAL),
.C_HAS_MEM_OUTPUT_REGS_A (C_HAS_MEM_OUTPUT_REGS_A),
.C_HAS_MEM_OUTPUT_REGS_B (C_HAS_MEM_OUTPUT_REGS_B),
.C_HAS_MUX_OUTPUT_REGS_A (C_HAS_MUX_OUTPUT_REGS_A),
.C_HAS_MUX_OUTPUT_REGS_B (C_HAS_MUX_OUTPUT_REGS_B),
.C_HAS_SOFTECC_INPUT_REGS_A (C_HAS_SOFTECC_INPUT_REGS_A),
.C_HAS_SOFTECC_OUTPUT_REGS_B (C_HAS_SOFTECC_OUTPUT_REGS_B),
.C_MUX_PIPELINE_STAGES (C_MUX_PIPELINE_STAGES),
.C_USE_SOFTECC (C_USE_SOFTECC),
.C_USE_ECC (C_USE_ECC),
.C_HAS_INJECTERR (C_HAS_INJECTERR),
.C_SIM_COLLISION_CHECK (C_SIM_COLLISION_CHECK),
.C_COMMON_CLK (C_COMMON_CLK),
.FLOP_DELAY (FLOP_DELAY),
.C_DISABLE_WARN_BHV_COLL (C_DISABLE_WARN_BHV_COLL),
.C_EN_ECC_PIPE (C_EN_ECC_PIPE),
.C_DISABLE_WARN_BHV_RANGE (C_DISABLE_WARN_BHV_RANGE))
blk_mem_gen_v8_3_3_inst
(.CLKA (CLKA),
.RSTA (RSTA_I_SAFE),//(rsta_in),
.ENA (ENA_I_SAFE),//(ena_in),
.REGCEA (regcea_in),
.WEA (wea_in),
.ADDRA (addra_in[C_MEM_MAP_ADDRA_WIDTH_MSB-1:C_MEM_MAP_ADDRA_WIDTH_LSB]),
.DINA (dina_in),
.DOUTA (DOUTA),
.CLKB (CLKB),
.RSTB (RSTB_I_SAFE),//(RSTB),
.ENB (ENB_I_SAFE),//(ENB),
.REGCEB (REGCEB),
.WEB (WEB),
.ADDRB (ADDRB[C_MEM_MAP_ADDRB_WIDTH_MSB-1:C_MEM_MAP_ADDRB_WIDTH_LSB]),
.DINB (DINB),
.DOUTB (DOUTB),
.INJECTSBITERR (injectsbiterr_in),
.INJECTDBITERR (injectdbiterr_in),
.ECCPIPECE (ECCPIPECE),
.SLEEP (SLEEP),
.SBITERR (SBITERR),
.DBITERR (DBITERR),
.RDADDRECC (rdaddrecc_i)
);
end
endgenerate
generate if (C_HAS_MEM_OUTPUT_REGS_B == 0 && C_HAS_MUX_OUTPUT_REGS_B == 0 ) begin : no_regs
assign S_AXI_RDATA = s_axi_rdata_c;
assign S_AXI_RLAST = s_axi_rlast_c;
assign S_AXI_RVALID = s_axi_rvalid_c;
assign S_AXI_RID = s_axi_rid_c;
assign S_AXI_RRESP = s_axi_rresp_c;
assign s_axi_rready_c = S_AXI_RREADY;
end
endgenerate
generate if (C_HAS_MEM_OUTPUT_REGS_B == 1) begin : has_regceb
assign regceb_c = s_axi_rvalid_c && s_axi_rready_c;
end
endgenerate
generate if (C_HAS_MEM_OUTPUT_REGS_B == 0) begin : no_regceb
assign regceb_c = REGCEB;
end
endgenerate
generate if (C_HAS_MUX_OUTPUT_REGS_B == 1) begin : only_core_op_regs
assign s_axi_payload_c = {s_axi_rid_c,s_axi_rdata_c,s_axi_rresp_c,s_axi_rlast_c};
assign S_AXI_RID = m_axi_payload_c[C_AXI_PAYLOAD-1 : C_AXI_PAYLOAD-C_AXI_ID_WIDTH];
assign S_AXI_RDATA = m_axi_payload_c[C_AXI_PAYLOAD-C_AXI_ID_WIDTH-1 : C_AXI_PAYLOAD-C_AXI_ID_WIDTH-C_WRITE_WIDTH_B];
assign S_AXI_RRESP = m_axi_payload_c[2:1];
assign S_AXI_RLAST = m_axi_payload_c[0];
end
endgenerate
generate if (C_HAS_MEM_OUTPUT_REGS_B == 1) begin : only_emb_op_regs
assign s_axi_payload_c = {s_axi_rid_c,s_axi_rresp_c,s_axi_rlast_c};
assign S_AXI_RDATA = s_axi_rdata_c;
assign S_AXI_RID = m_axi_payload_c[C_AXI_PAYLOAD-1 : C_AXI_PAYLOAD-C_AXI_ID_WIDTH];
assign S_AXI_RRESP = m_axi_payload_c[2:1];
assign S_AXI_RLAST = m_axi_payload_c[0];
end
endgenerate
generate if (C_HAS_MUX_OUTPUT_REGS_B == 1 || C_HAS_MEM_OUTPUT_REGS_B == 1) begin : has_regs_fwd
blk_mem_axi_regs_fwd_v8_3
#(.C_DATA_WIDTH (C_AXI_PAYLOAD))
axi_regs_inst (
.ACLK (S_ACLK),
.ARESET (s_aresetn_a_c),
.S_VALID (s_axi_rvalid_c),
.S_READY (s_axi_rready_c),
.S_PAYLOAD_DATA (s_axi_payload_c),
.M_VALID (S_AXI_RVALID),
.M_READY (S_AXI_RREADY),
.M_PAYLOAD_DATA (m_axi_payload_c)
);
end
endgenerate
generate if (C_INTERFACE_TYPE == 1) begin : axi_mem_module
assign s_aresetn_a_c = !S_ARESETN;
assign S_AXI_BRESP = 2'b00;
assign s_axi_rresp_c = 2'b00;
assign s_axi_arlen_c = (C_AXI_TYPE == 1)?S_AXI_ARLEN:8'h0;
blk_mem_axi_write_wrapper_beh_v8_3
#(.C_INTERFACE_TYPE (C_INTERFACE_TYPE),
.C_AXI_TYPE (C_AXI_TYPE),
.C_AXI_SLAVE_TYPE (C_AXI_SLAVE_TYPE),
.C_MEMORY_TYPE (C_MEM_TYPE),
.C_WRITE_DEPTH_A (C_WRITE_DEPTH_A),
.C_AXI_AWADDR_WIDTH ((AXI_FULL_MEMORY_SLAVE == 1)?C_AXI_ADDR_WIDTH:C_AXI_ADDR_WIDTH-C_AXI_ADDR_WIDTH_LSB),
.C_HAS_AXI_ID (C_HAS_AXI_ID),
.C_AXI_ID_WIDTH (C_AXI_ID_WIDTH),
.C_ADDRA_WIDTH (C_ADDRA_WIDTH),
.C_AXI_WDATA_WIDTH (C_WRITE_WIDTH_A),
.C_AXI_OS_WR (C_AXI_OS_WR))
axi_wr_fsm (
// AXI Global Signals
.S_ACLK (S_ACLK),
.S_ARESETN (s_aresetn_a_c),
// AXI Full/Lite Slave Write interface
.S_AXI_AWADDR (S_AXI_AWADDR[C_AXI_ADDR_WIDTH_MSB-1:C_AXI_ADDR_WIDTH_LSB]),
.S_AXI_AWLEN (S_AXI_AWLEN),
.S_AXI_AWID (S_AXI_AWID),
.S_AXI_AWSIZE (S_AXI_AWSIZE),
.S_AXI_AWBURST (S_AXI_AWBURST),
.S_AXI_AWVALID (S_AXI_AWVALID),
.S_AXI_AWREADY (S_AXI_AWREADY),
.S_AXI_WVALID (S_AXI_WVALID),
.S_AXI_WREADY (S_AXI_WREADY),
.S_AXI_BVALID (S_AXI_BVALID),
.S_AXI_BREADY (S_AXI_BREADY),
.S_AXI_BID (S_AXI_BID),
// Signals for BRAM interfac(
.S_AXI_AWADDR_OUT (s_axi_awaddr_out_c),
.S_AXI_WR_EN (s_axi_wr_en_c)
);
blk_mem_axi_read_wrapper_beh_v8_3
#(.C_INTERFACE_TYPE (C_INTERFACE_TYPE),
.C_AXI_TYPE (C_AXI_TYPE),
.C_AXI_SLAVE_TYPE (C_AXI_SLAVE_TYPE),
.C_MEMORY_TYPE (C_MEM_TYPE),
.C_WRITE_WIDTH_A (C_WRITE_WIDTH_A),
.C_ADDRA_WIDTH (C_ADDRA_WIDTH),
.C_AXI_PIPELINE_STAGES (1),
.C_AXI_ARADDR_WIDTH ((AXI_FULL_MEMORY_SLAVE == 1)?C_AXI_ADDR_WIDTH:C_AXI_ADDR_WIDTH-C_AXI_ADDR_WIDTH_LSB),
.C_HAS_AXI_ID (C_HAS_AXI_ID),
.C_AXI_ID_WIDTH (C_AXI_ID_WIDTH),
.C_ADDRB_WIDTH (C_ADDRB_WIDTH))
axi_rd_sm(
//AXI Global Signals
.S_ACLK (S_ACLK),
.S_ARESETN (s_aresetn_a_c),
//AXI Full/Lite Read Side
.S_AXI_ARADDR (S_AXI_ARADDR[C_AXI_ADDR_WIDTH_MSB-1:C_AXI_ADDR_WIDTH_LSB]),
.S_AXI_ARLEN (s_axi_arlen_c),
.S_AXI_ARSIZE (S_AXI_ARSIZE),
.S_AXI_ARBURST (S_AXI_ARBURST),
.S_AXI_ARVALID (S_AXI_ARVALID),
.S_AXI_ARREADY (S_AXI_ARREADY),
.S_AXI_RLAST (s_axi_rlast_c),
.S_AXI_RVALID (s_axi_rvalid_c),
.S_AXI_RREADY (s_axi_rready_c),
.S_AXI_ARID (S_AXI_ARID),
.S_AXI_RID (s_axi_rid_c),
//AXI Full/Lite Read FSM Outputs
.S_AXI_ARADDR_OUT (s_axi_araddr_out_c),
.S_AXI_RD_EN (s_axi_rd_en_c)
);
blk_mem_gen_v8_3_3_mem_module
#(.C_CORENAME (C_CORENAME),
.C_FAMILY (C_FAMILY),
.C_XDEVICEFAMILY (C_XDEVICEFAMILY),
.C_MEM_TYPE (C_MEM_TYPE),
.C_BYTE_SIZE (C_BYTE_SIZE),
.C_USE_BRAM_BLOCK (C_USE_BRAM_BLOCK),
.C_ALGORITHM (C_ALGORITHM),
.C_PRIM_TYPE (C_PRIM_TYPE),
.C_LOAD_INIT_FILE (C_LOAD_INIT_FILE),
.C_INIT_FILE_NAME (C_INIT_FILE_NAME),
.C_INIT_FILE (C_INIT_FILE),
.C_USE_DEFAULT_DATA (C_USE_DEFAULT_DATA),
.C_DEFAULT_DATA (C_DEFAULT_DATA),
.C_RST_TYPE ("SYNC"),
.C_HAS_RSTA (C_HAS_RSTA),
.C_RST_PRIORITY_A (C_RST_PRIORITY_A),
.C_RSTRAM_A (C_RSTRAM_A),
.C_INITA_VAL (C_INITA_VAL),
.C_HAS_ENA (1),
.C_HAS_REGCEA (C_HAS_REGCEA),
.C_USE_BYTE_WEA (1),
.C_WEA_WIDTH (C_WEA_WIDTH),
.C_WRITE_MODE_A (C_WRITE_MODE_A),
.C_WRITE_WIDTH_A (C_WRITE_WIDTH_A),
.C_READ_WIDTH_A (C_READ_WIDTH_A),
.C_WRITE_DEPTH_A (C_WRITE_DEPTH_A),
.C_READ_DEPTH_A (C_READ_DEPTH_A),
.C_ADDRA_WIDTH (C_ADDRA_WIDTH),
.C_HAS_RSTB (C_HAS_RSTB),
.C_RST_PRIORITY_B (C_RST_PRIORITY_B),
.C_RSTRAM_B (C_RSTRAM_B),
.C_INITB_VAL (C_INITB_VAL),
.C_HAS_ENB (1),
.C_HAS_REGCEB (C_HAS_MEM_OUTPUT_REGS_B),
.C_USE_BYTE_WEB (1),
.C_WEB_WIDTH (C_WEB_WIDTH),
.C_WRITE_MODE_B (C_WRITE_MODE_B),
.C_WRITE_WIDTH_B (C_WRITE_WIDTH_B),
.C_READ_WIDTH_B (C_READ_WIDTH_B),
.C_WRITE_DEPTH_B (C_WRITE_DEPTH_B),
.C_READ_DEPTH_B (C_READ_DEPTH_B),
.C_ADDRB_WIDTH (C_ADDRB_WIDTH),
.C_HAS_MEM_OUTPUT_REGS_A (0),
.C_HAS_MEM_OUTPUT_REGS_B (C_HAS_MEM_OUTPUT_REGS_B),
.C_HAS_MUX_OUTPUT_REGS_A (0),
.C_HAS_MUX_OUTPUT_REGS_B (0),
.C_HAS_SOFTECC_INPUT_REGS_A (C_HAS_SOFTECC_INPUT_REGS_A),
.C_HAS_SOFTECC_OUTPUT_REGS_B (C_HAS_SOFTECC_OUTPUT_REGS_B),
.C_MUX_PIPELINE_STAGES (C_MUX_PIPELINE_STAGES),
.C_USE_SOFTECC (C_USE_SOFTECC),
.C_USE_ECC (C_USE_ECC),
.C_HAS_INJECTERR (C_HAS_INJECTERR),
.C_SIM_COLLISION_CHECK (C_SIM_COLLISION_CHECK),
.C_COMMON_CLK (C_COMMON_CLK),
.FLOP_DELAY (FLOP_DELAY),
.C_DISABLE_WARN_BHV_COLL (C_DISABLE_WARN_BHV_COLL),
.C_EN_ECC_PIPE (0),
.C_DISABLE_WARN_BHV_RANGE (C_DISABLE_WARN_BHV_RANGE))
blk_mem_gen_v8_3_3_inst
(.CLKA (S_ACLK),
.RSTA (s_aresetn_a_c),
.ENA (s_axi_wr_en_c),
.REGCEA (regcea_in),
.WEA (S_AXI_WSTRB),
.ADDRA (s_axi_awaddr_out_c),
.DINA (S_AXI_WDATA),
.DOUTA (DOUTA),
.CLKB (S_ACLK),
.RSTB (s_aresetn_a_c),
.ENB (s_axi_rd_en_c),
.REGCEB (regceb_c),
.WEB (WEB_parameterized),
.ADDRB (s_axi_araddr_out_c),
.DINB (DINB),
.DOUTB (s_axi_rdata_c),
.INJECTSBITERR (injectsbiterr_in),
.INJECTDBITERR (injectdbiterr_in),
.SBITERR (SBITERR),
.DBITERR (DBITERR),
.ECCPIPECE (1'b0),
.SLEEP (1'b0),
.RDADDRECC (RDADDRECC)
);
end
endgenerate
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// A test of the +verilog1995ext+ and +verilog2001ext+ flags.
//
// This source code contains constructs that are valid in Verilog 2001 and
// SystemVerilog 2005/2009, but not in Verilog 1995. So it should fail if we
// set the language to be 1995, but not 2001.
//
// Compile only test, so no need for "All Finished" output.
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2012 by Jeremy Bennett.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
reg [1:0] res;
// Instantiate the test
test test_i (/*AUTOINST*/
// Outputs
.res (res),
// Inputs
.clk (clk),
.in (1'b1));
endmodule
module test (// Outputs
res,
// Inputs
clk,
in
);
output [1:0] res;
input clk;
input in;
// This is a Verilog 2001 test
generate
genvar i;
for (i=0; i<2; i=i+1) begin
always @(posedge clk) begin
res[i:i] <= in;
end
end
endgenerate
endmodule
|
// (C) 1992-2012 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
module acl_fp_custom_align_double( clock, resetn,
input_a_mantissa, input_a_exponent, input_a_sign,
input_b_mantissa, input_b_exponent, input_b_sign,
left_mantissa, left_exponent, left_sign,
right_mantissa, right_exponent, right_sign,
valid_in, valid_out, stall_in, stall_out,
enable);
parameter HIGH_CAPACITY = 1;
parameter FLUSH_DENORMS = 0;
parameter HIGH_LATENCY = 1;
parameter ROUNDING_MODE = 0;
parameter REMOVE_STICKY = 1;
parameter FINITE_MATH_ONLY = 1;
input clock, resetn;
input [55:0] input_a_mantissa;
input [11:0] input_a_exponent;
input input_a_sign;
input [55:0] input_b_mantissa;
input [11:0] input_b_exponent;
input input_b_sign;
output [55:0] left_mantissa;
output [11:0] left_exponent;
output left_sign;
output [55:0] right_mantissa;
output [11:0] right_exponent;
output right_sign;
input enable, valid_in, stall_in;
output valid_out, stall_out;
// This module aligns two floating point input values such that their exponents are equal,
// permitting a proper addition of the two numbers.
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg c1_valid;
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg c2_valid;
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg c3_valid;
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg c4_valid;
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg c5_valid;
wire c1_enable;
wire c2_enable;
wire c3_enable;
wire c4_enable;
wire c5_enable;
wire c1_stall;
wire c2_stall;
wire c3_stall;
wire c4_stall;
wire c5_stall;
// Cycle 1 - Determine the magnitude of both numbers.
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg [55:0] c1_l_mantissa;
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg [55:0] c1_r_mantissa;
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg [11:0] c1_l_exponent;
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg [11:0] c1_r_exponent;
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg [13:0] c1_l_mantissa_nonzero;
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg [13:0] c1_r_mantissa_nonzero;
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg c1_l_sign, c1_r_sign;
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg [11:0] c1_exp_diff;
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg [1:0]c1_matissa_r_greater, c1_matissas_equal;
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg c1_exp_equal;
assign c1_enable = (HIGH_CAPACITY ? (~c1_stall | ~c1_valid) : enable);
assign stall_out = c1_stall & c1_valid;
always @(posedge clock or negedge resetn)
begin
if (~resetn)
begin
c1_l_mantissa <= 56'dx;
c1_r_mantissa <= 56'dx;
c1_l_exponent <= 12'dx;
c1_r_exponent <= 12'dx;
c1_l_mantissa_nonzero <= 14'dx;
c1_r_mantissa_nonzero <= 14'dx;
c1_l_sign <= 1'bx;
c1_r_sign <= 1'bx;
c1_matissa_r_greater <= 2'bxx;
c1_exp_diff <= 12'dx;
c1_exp_equal <= 1'bx;
c1_matissas_equal <= 2'bxx;
c1_valid <= 1'b0;
end
else if (c1_enable)
begin
c1_valid <= valid_in;
if ((FINITE_MATH_ONLY == 0) && (input_a_exponent[11] || input_b_exponent[11]))
begin
c1_exp_diff <= 12'd0;
c1_exp_equal <= 1'b1;
end
else
begin
c1_exp_diff <= {1'b0, input_a_exponent[10:0]} - {1'b0, input_b_exponent[10:0]};
c1_exp_equal <= (input_a_exponent[10:0] == input_b_exponent[10:0]);
end
c1_l_mantissa <= input_a_mantissa;
c1_r_mantissa <= input_b_mantissa;
c1_l_exponent <= input_a_exponent;
c1_r_exponent <= input_b_exponent;
c1_l_mantissa_nonzero <= {input_a_exponent[11] ? (|input_a_mantissa[54:52]) : (|input_a_mantissa[55:52]), |input_a_mantissa[51:48], |input_a_mantissa[47:44], |input_a_mantissa[43:40], |input_a_mantissa[39:36], |input_a_mantissa[35:32], |input_a_mantissa[31:28], |input_a_mantissa[27:24], |input_a_mantissa[23:20], |input_a_mantissa[19:16], |input_a_mantissa[15:12], |input_a_mantissa[11:8], |input_a_mantissa[7:3], |input_a_mantissa[2:0]};
c1_r_mantissa_nonzero <= {input_b_exponent[11] ? (|input_b_mantissa[54:52]) : (|input_b_mantissa[55:52]), |input_b_mantissa[51:48], |input_b_mantissa[47:44], |input_b_mantissa[43:40], |input_b_mantissa[39:36], |input_b_mantissa[35:32], |input_b_mantissa[31:28], |input_b_mantissa[27:24], |input_b_mantissa[23:20], |input_b_mantissa[19:16], |input_b_mantissa[15:12], |input_b_mantissa[11:8], |input_b_mantissa[7:3], |input_b_mantissa[2:0]};
c1_l_sign <= input_a_sign;
c1_r_sign <= input_b_sign;
c1_matissa_r_greater <= {{1'b0, input_b_mantissa[55:28]} > {1'b0, input_a_mantissa[55:28]}, {1'b0, input_b_mantissa[27:0]} > {1'b0, input_a_mantissa[27:0]} };
c1_matissas_equal <= {(input_b_mantissa[55:28] == input_a_mantissa[55:28]),(input_b_mantissa[27:0] == input_a_mantissa[27:0])};
end
end
// Cycle 2 - Swap numbers such that the larger one is the left and the smaller one is the right.
// If the numbers are equal in magnitude, then pick the positive one to be the left one.
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg [55:0] c2_l_mantissa;
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg [55:0] c2_r_mantissa;
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg [11:0] c2_l_exponent;
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg c2_l_sign, c2_r_sign;
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg [11:0] c2_exp_diff;
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg [3:0] c2_r_mantissa_nonzero;
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg [3:0] c2_lr_mantissa_info;
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg c2_diff_signs;
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg [1:0] c2_exponents;
assign c2_enable = (HIGH_CAPACITY ? (~c2_stall | ~c2_valid) : enable);
assign c1_stall = c2_stall & c2_valid;
generate
if (HIGH_LATENCY == 1)
begin
always @(posedge clock or negedge resetn)
begin
if (~resetn)
begin
c2_l_mantissa <= 56'dx;
c2_r_mantissa <= 56'dx;
c2_l_exponent <= 12'dx;
c2_l_sign <= 1'bx;
c2_r_sign <= 1'bx;
c2_r_mantissa_nonzero <= 4'dx;
c2_lr_mantissa_info <= 4'dx;
c2_diff_signs <= 1'bx;
c2_exponents <= 2'bxx;
c2_valid <= 1'b0;
end
else if (c2_enable)
begin
c2_valid <= c1_valid;
c2_diff_signs <= c1_l_sign ^ c1_r_sign;
c2_exponents <= {c1_l_exponent[11], c1_r_exponent[11]};
// Here we account for denorms
if (c1_exp_diff[11])
begin
c2_exp_diff <= {12{c1_r_mantissa[55] ^ c1_l_mantissa[55]}} - c1_exp_diff;
end
else
begin
if (FINITE_MATH_ONLY == 0)
c2_exp_diff <= (c1_l_exponent[11] || c1_r_exponent[11]) ? c1_exp_diff : c1_exp_diff - {1'b0, c1_r_mantissa[55] ^ c1_l_mantissa[55]};
else
c2_exp_diff <= c1_exp_diff - {1'b0, c1_r_mantissa[55] ^ c1_l_mantissa[55]};
end
if ((c1_l_exponent[11] || c1_r_exponent[11]) && (FINITE_MATH_ONLY == 0))
begin
// Here we handle the cases of NaN and Inf values.
// I need to split this into two stages, otherwise the logic is really complicated.
// When testing for non-zero mantissa we need to check that the exponent is maxed out.
// We use c3_lr_mantissa_info to convey this information to the next cycle.
c2_lr_mantissa_info <= {|c1_l_mantissa_nonzero[13:7], |c1_l_mantissa_nonzero[6:0], |c1_r_mantissa_nonzero[13:7], |c1_r_mantissa_nonzero[6:0]};
c2_l_mantissa[55] <= 1'b1; // Inf
c2_l_mantissa[54:0] <= 55'd0; // Inf
c2_r_mantissa <= 56'd0;
c2_l_exponent <= 12'hfff;
c2_l_sign <= c1_l_exponent[11] ? c1_l_sign : c1_r_sign;
c2_r_sign <= c1_l_exponent[11] ? c1_l_sign : c1_r_sign;
c2_r_mantissa_nonzero <= {|c1_r_mantissa_nonzero[13:12], |c1_r_mantissa_nonzero[11:8], |c1_r_mantissa_nonzero[7:4], |c1_r_mantissa_nonzero[3:0]};
end
else
if ((&c1_matissas_equal) & c1_exp_equal & ~c1_r_sign |
(c1_exp_equal & (c1_matissa_r_greater[1] | c1_matissas_equal[1] & c1_matissa_r_greater[0])) | (c1_exp_diff[11]))
begin
// Swap left and right inputs
c2_lr_mantissa_info <= 4'd0;
c2_l_mantissa <= c1_r_mantissa;
c2_r_mantissa <= c1_l_mantissa;
c2_l_exponent <= c1_r_exponent;
c2_l_sign <= c1_r_sign;
c2_r_sign <= c1_l_sign;
c2_r_mantissa_nonzero <= {|c1_l_mantissa_nonzero[13:12], |c1_l_mantissa_nonzero[11:8], |c1_l_mantissa_nonzero[7:4], |c1_l_mantissa_nonzero[3:0]};
end
else
begin
c2_lr_mantissa_info <= 4'd0;
c2_l_mantissa <= c1_l_mantissa;
c2_r_mantissa <= c1_r_mantissa;
c2_l_exponent <= c1_l_exponent;
c2_l_sign <= c1_l_sign;
c2_r_sign <= c1_r_sign;
c2_r_mantissa_nonzero <= {|c1_r_mantissa_nonzero[13:12], |c1_r_mantissa_nonzero[11:8], |c1_r_mantissa_nonzero[7:4], |c1_r_mantissa_nonzero[3:0]};
end
end
end
end
else
begin
// Do not register this stage in low-latency mode.
always @(*)
begin
c2_valid <= c1_valid;
c2_diff_signs <= c1_l_sign ^ c1_r_sign;
c2_exponents <= {c1_l_exponent[11], c1_r_exponent[11]};
// Here we account for denorms
if (c1_exp_diff[11])
begin
c2_exp_diff <= {12{c1_r_mantissa[55] ^ c1_l_mantissa[55]}} - c1_exp_diff;
end
else
begin
if (FINITE_MATH_ONLY == 0)
c2_exp_diff <= (c1_l_exponent[11] || c1_r_exponent[11]) ? c1_exp_diff : c1_exp_diff - {1'b0, c1_r_mantissa[55] ^ c1_l_mantissa[55]};
else
c2_exp_diff <= c1_exp_diff - {1'b0, c1_r_mantissa[55] ^ c1_l_mantissa[55]};
end
if ((c1_l_exponent[11] || c1_r_exponent[11]) && (FINITE_MATH_ONLY == 0))
begin
// Here we handle the cases of NaN and Inf values.
// I need to split this into two stages, otherwise the logic is really complicated.
// When testing for non-zero mantissa we need to check that the exponent is maxed out.
// We use c3_lr_mantissa_info to convey this information to the next cycle.
c2_lr_mantissa_info <= {|c1_l_mantissa_nonzero[13:7], |c1_l_mantissa_nonzero[6:0], |c1_r_mantissa_nonzero[13:7], |c1_r_mantissa_nonzero[6:0]};
c2_l_mantissa[55] <= 1'b1; // Inf
c2_l_mantissa[54:0] <= 55'd0; // Inf
c2_r_mantissa <= 56'd0;
c2_l_exponent <= 12'hfff;
c2_l_sign <= c1_l_exponent[11] ? c1_l_sign : c1_r_sign;
c2_r_sign <= c1_l_exponent[11] ? c1_l_sign : c1_r_sign;
c2_r_mantissa_nonzero <= {|c1_r_mantissa_nonzero[13:12], |c1_r_mantissa_nonzero[11:8], |c1_r_mantissa_nonzero[7:4], |c1_r_mantissa_nonzero[3:0]};
end
else
if ((&c1_matissas_equal) & c1_exp_equal & ~c1_r_sign |
(c1_exp_equal & (c1_matissa_r_greater[1] | c1_matissas_equal[1] & c1_matissa_r_greater[0])) | (c1_exp_diff[11]))
begin
// Swap left and right inputs
c2_lr_mantissa_info <= 4'd0;
c2_l_mantissa <= c1_r_mantissa;
c2_r_mantissa <= c1_l_mantissa;
c2_l_exponent <= c1_r_exponent;
c2_l_sign <= c1_r_sign;
c2_r_sign <= c1_l_sign;
c2_r_mantissa_nonzero <= {|c1_l_mantissa_nonzero[13:12], |c1_l_mantissa_nonzero[11:8], |c1_l_mantissa_nonzero[7:4], |c1_l_mantissa_nonzero[3:0]};
end
else
begin
c2_lr_mantissa_info <= 4'd0;
c2_l_mantissa <= c1_l_mantissa;
c2_r_mantissa <= c1_r_mantissa;
c2_l_exponent <= c1_l_exponent;
c2_l_sign <= c1_l_sign;
c2_r_sign <= c1_r_sign;
c2_r_mantissa_nonzero <= {|c1_r_mantissa_nonzero[13:12], |c1_r_mantissa_nonzero[11:8], |c1_r_mantissa_nonzero[7:4], |c1_r_mantissa_nonzero[3:0]};
end
end
end
endgenerate
// Cycle 3 - shift data in the right input as much as needed to match exponents
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg [55:0] c3_l_mantissa;
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg [55:0] c3_r_mantissa;
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg [11:0] c3_l_exponent;
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg c3_l_sign, c3_r_sign;
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg [11:0] c3_exp_diff;
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg c3_clear_right;
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg c3_sticky_right;
assign c3_enable = (HIGH_CAPACITY ? (~c3_stall | ~c3_valid) : enable);
assign c2_stall = c3_stall & c3_valid;
reg [1:0] c3_select;
always@(*)
begin
if (c2_exp_diff >= 9'd48)
c3_select = 2'b11;
else if (c2_exp_diff >= 9'd32)
c3_select = 2'b10;
else if (c2_exp_diff >= 9'd16)
c3_select = 2'b01;
else
c3_select = 2'b00;
end
always @(posedge clock or negedge resetn)
begin
if (~resetn)
begin
c3_l_mantissa <= 27'dx;
c3_r_mantissa <= 27'dx;
c3_l_exponent <= 9'dx;
c3_l_sign <= 1'bx;
c3_r_sign <= 1'bx;
c3_clear_right <= 1'bx;
c3_sticky_right <= 1'bx;
c3_valid <= 1'b0;
end
else if (c3_enable)
begin
c3_valid <= c2_valid;
// A number becomes a NaN when
// 1. it is a sum of positive and negative infinities
// 2. one of the numbers is a NaN
if ((FINITE_MATH_ONLY == 0) && ((c2_exponents[1] & c2_exponents[0] & ~(|c2_lr_mantissa_info) & c2_diff_signs) ||
(c2_exponents[1] & (|c2_lr_mantissa_info[3:2]) | c2_exponents[0] & (|c2_lr_mantissa_info[1:0]))))
c3_l_mantissa[54] <= 1'b1; // Make a number into a NaN if it was infinity before.
else
c3_l_mantissa[54] <= c2_l_mantissa[54];
c3_l_mantissa[55] <= c2_l_mantissa[55];
c3_l_mantissa[53:0] <= c2_l_mantissa[53:0];
c3_l_exponent <= c2_l_exponent;
c3_l_sign <= c2_l_sign;
c3_r_sign <= c2_r_sign;
c3_clear_right <= (c2_exp_diff >= 12'd56);
if (REMOVE_STICKY == 1)
c3_sticky_right <= 1'b0;
else
c3_sticky_right <= |c2_r_mantissa_nonzero;
c3_exp_diff <= c2_exp_diff - {1'b0, c3_select, 4'd0};
case(c3_select)
2'b11:
begin
if (REMOVE_STICKY == 1)
c3_r_mantissa <= {48'd0, c2_r_mantissa[55:49], c2_r_mantissa[48]};
else
c3_r_mantissa <= {48'd0, c2_r_mantissa[55:49], c2_r_mantissa[48] | (|c2_r_mantissa_nonzero[2:0])};
end
2'b10:
begin
if (REMOVE_STICKY == 1)
c3_r_mantissa <= {32'd0, c2_r_mantissa[55:33], c2_r_mantissa[32]};
else
c3_r_mantissa <= {32'd0, c2_r_mantissa[55:33], c2_r_mantissa[32] | (|c2_r_mantissa_nonzero[1:0])};
end
2'b01:
begin
if (REMOVE_STICKY == 1)
c3_r_mantissa <= {16'd0, c2_r_mantissa[55:17], c2_r_mantissa[16]};
else
c3_r_mantissa <= {16'd0, c2_r_mantissa[55:17], c2_r_mantissa[16] | (c2_r_mantissa_nonzero[0])};
end
2'b00:
begin
c3_r_mantissa <= c2_r_mantissa;
end
endcase
end
end
// Cycle 4 - Shift by 12, 8 or 4.
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg [55:0] c4_l_mantissa;
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg [55:0] c4_r_mantissa;
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg [11:0] c4_l_exponent;
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg [1:0] c4_exp_diff;
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg c4_l_sign, c4_r_sign;
assign c4_enable = (HIGH_CAPACITY ? (~c4_stall | ~c4_valid) : enable);
assign c3_stall = c4_stall & c4_valid;
reg c4_sticky_bit;
always@(*)
begin
if (REMOVE_STICKY == 1)
c4_sticky_bit = 1'b0;
else
begin
case(c3_exp_diff[3:2])
2'h3: c4_sticky_bit = |c3_r_mantissa[11:0];
2'h2: c4_sticky_bit = |c3_r_mantissa[7:0];
2'h1: c4_sticky_bit = |c3_r_mantissa[3:0];
2'h0: c4_sticky_bit = 1'b0;
endcase
end
end
generate
if (HIGH_LATENCY == 1)
begin
always @(posedge clock or negedge resetn)
begin
if (~resetn)
begin
c4_l_mantissa <= 56'dx;
c4_r_mantissa <= 56'dx;
c4_l_exponent <= 12'dx;
c4_l_sign <= 1'bx;
c4_r_sign <= 1'bx;
c4_exp_diff <= 2'bxx;
c4_valid <= 1'b0;
end
else if (c4_enable)
begin
c4_valid <= c3_valid;
c4_l_mantissa <= c3_l_mantissa;
c4_l_exponent <= c3_l_exponent;
c4_l_sign <= c3_l_sign;
c4_r_sign <= c3_r_sign;
c4_exp_diff <= c3_exp_diff[1:0];
if (c3_clear_right)
begin
c4_r_mantissa <= c3_sticky_right ? 56'd1 : 56'd0;
end
else
begin
case(c3_exp_diff[3:2])
2'h3: c4_r_mantissa <= {12'd0, c3_r_mantissa[55:13], c3_r_mantissa[12] | c4_sticky_bit};
2'h2: c4_r_mantissa <= {8'd0, c3_r_mantissa[55:9], c3_r_mantissa[8] | c4_sticky_bit};
2'h1: c4_r_mantissa <= {4'd0, c3_r_mantissa[55:5], c3_r_mantissa[4] | c4_sticky_bit};
2'h0: c4_r_mantissa <= c3_r_mantissa;
endcase
end
end
end
end
else
begin
// in low latency mode do not register this stage.
always @(*)
begin
c4_valid <= c3_valid;
c4_l_mantissa <= c3_l_mantissa;
c4_l_exponent <= c3_l_exponent;
c4_l_sign <= c3_l_sign;
c4_r_sign <= c3_r_sign;
c4_exp_diff <= c3_exp_diff[1:0];
if (c3_clear_right)
begin
c4_r_mantissa <= c3_sticky_right ? 56'd1 : 56'd0;
end
else
begin
case(c3_exp_diff[3:2])
2'h3: c4_r_mantissa <= {12'd0, c3_r_mantissa[55:13], c3_r_mantissa[12] | c4_sticky_bit};
2'h2: c4_r_mantissa <= {8'd0, c3_r_mantissa[55:9], c3_r_mantissa[8] | c4_sticky_bit};
2'h1: c4_r_mantissa <= {4'd0, c3_r_mantissa[55:5], c3_r_mantissa[4] | c4_sticky_bit};
2'h0: c4_r_mantissa <= c3_r_mantissa;
endcase
end
end
end
endgenerate
// Cycle 5 - Complete the shifting of data and produce a final result
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg [55:0] c5_l_mantissa;
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg [55:0] c5_r_mantissa;
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg [11:0] c5_l_exponent;
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg c5_l_sign, c5_r_sign;
assign c5_enable = (HIGH_CAPACITY ? (~c5_stall | ~c5_valid) : enable);
assign c4_stall = c5_stall & c5_valid;
reg c5_sticky_bit;
always@(*)
begin
case(c4_exp_diff)
2'h3: c5_sticky_bit = |c4_r_mantissa[2:0];
2'h2: c5_sticky_bit = |c4_r_mantissa[1:0];
2'h1: c5_sticky_bit = c4_r_mantissa[0];
2'h0: c5_sticky_bit = 1'b0;
endcase
end
always @(posedge clock or negedge resetn)
begin
if (~resetn)
begin
c5_l_mantissa <= 27'dx;
c5_r_mantissa <= 27'dx;
c5_l_exponent <= 9'dx;
c5_l_sign <= 1'bx;
c5_r_sign <= 1'bx;
c5_valid <= 1'b0;
end
else if (c5_enable)
begin
c5_valid <= c4_valid;
c5_l_mantissa <= c4_l_mantissa;
c5_l_exponent <= c4_l_exponent;
c5_l_sign <= c4_l_sign;
c5_r_sign <= c4_r_sign;
c5_r_mantissa <= (c4_r_mantissa >> c4_exp_diff) | c5_sticky_bit;
end
end
assign c5_stall = stall_in;
assign valid_out = c5_valid;
assign left_mantissa = c5_l_mantissa;
assign left_exponent = c5_l_exponent;
assign left_sign = c5_l_sign;
assign right_mantissa = c5_r_mantissa;
assign right_exponent = c5_l_exponent;
assign right_sign = c5_r_sign;
endmodule
|
//
// Copyright (c) 1999 Steven Wilson ([email protected])
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW - Validate unary or |(value)
//
module main;
reg [3:0] vect;
reg error;
wire result;
assign result = |(vect);
initial
begin
error = 0;
for(vect=4'b0001;vect<4'b1111;vect = vect + 1)
begin
#1;
if(result !== 1'b1)
begin
$display("FAILED - Unary or |(%b)=%b",vect,result);
error = 1'b1;
end
end
#1;
vect = 4'b0000;
#1;
if(result !== 1'b0)
begin
$display("FAILED - Unary or |(%b)=%b",vect,result);
error = 1'b1;
end
if(error === 0 )
$display("PASSED");
end
endmodule // main
|
/*
----------------------------------------------------------------------------------
Copyright (c) 2013-2014
Embedded and Network Computing Lab.
Open SSD Project
Hanyang University
All rights reserved.
----------------------------------------------------------------------------------
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. All advertising materials mentioning features or use of this source code
must display the following acknowledgement:
This product includes source code developed
by the Embedded and Network Computing Lab. and the Open SSD Project.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
----------------------------------------------------------------------------------
http://enclab.hanyang.ac.kr/
http://www.openssd-project.org/
http://www.hanyang.ac.kr/
----------------------------------------------------------------------------------
*/
`timescale 1ns / 1ps
module reg_cpu_pcie_sync # (
parameter C_PCIE_ADDR_WIDTH = 36
)
(
input cpu_bus_clk,
input [1:0] nvme_csts_shst,
input nvme_csts_rdy,
input [8:0] sq_valid,
input [7:0] io_sq1_size,
input [7:0] io_sq2_size,
input [7:0] io_sq3_size,
input [7:0] io_sq4_size,
input [7:0] io_sq5_size,
input [7:0] io_sq6_size,
input [7:0] io_sq7_size,
input [7:0] io_sq8_size,
input [C_PCIE_ADDR_WIDTH-1:2] io_sq1_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_sq2_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_sq3_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_sq4_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_sq5_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_sq6_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_sq7_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_sq8_bs_addr,
input [3:0] io_sq1_cq_vec,
input [3:0] io_sq2_cq_vec,
input [3:0] io_sq3_cq_vec,
input [3:0] io_sq4_cq_vec,
input [3:0] io_sq5_cq_vec,
input [3:0] io_sq6_cq_vec,
input [3:0] io_sq7_cq_vec,
input [3:0] io_sq8_cq_vec,
input [8:0] cq_valid,
input [7:0] io_cq1_size,
input [7:0] io_cq2_size,
input [7:0] io_cq3_size,
input [7:0] io_cq4_size,
input [7:0] io_cq5_size,
input [7:0] io_cq6_size,
input [7:0] io_cq7_size,
input [7:0] io_cq8_size,
input [C_PCIE_ADDR_WIDTH-1:2] io_cq1_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_cq2_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_cq3_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_cq4_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_cq5_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_cq6_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_cq7_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_cq8_bs_addr,
input [8:0] io_cq_irq_en,
input [2:0] io_cq1_iv,
input [2:0] io_cq2_iv,
input [2:0] io_cq3_iv,
input [2:0] io_cq4_iv,
input [2:0] io_cq5_iv,
input [2:0] io_cq6_iv,
input [2:0] io_cq7_iv,
input [2:0] io_cq8_iv,
output pcie_link_up_sync,
output [5:0] pl_ltssm_state_sync,
output [15:0] cfg_command_sync,
output [2:0] cfg_interrupt_mmenable_sync,
output cfg_interrupt_msienable_sync,
output cfg_interrupt_msixenable_sync,
output pcie_mreq_err_sync,
output pcie_cpld_err_sync,
output pcie_cpld_len_err_sync,
output nvme_cc_en_sync,
output [1:0] nvme_cc_shn_sync,
input pcie_user_clk,
input pcie_link_up,
input [5:0] pl_ltssm_state,
input [15:0] cfg_command,
input [2:0] cfg_interrupt_mmenable,
input cfg_interrupt_msienable,
input cfg_interrupt_msixenable,
input pcie_mreq_err,
input pcie_cpld_err,
input pcie_cpld_len_err,
input nvme_cc_en,
input [1:0] nvme_cc_shn,
output [1:0] nvme_csts_shst_sync,
output nvme_csts_rdy_sync,
output [8:0] sq_rst_n_sync,
output [8:0] sq_valid_sync,
output [7:0] io_sq1_size_sync,
output [7:0] io_sq2_size_sync,
output [7:0] io_sq3_size_sync,
output [7:0] io_sq4_size_sync,
output [7:0] io_sq5_size_sync,
output [7:0] io_sq6_size_sync,
output [7:0] io_sq7_size_sync,
output [7:0] io_sq8_size_sync,
output [C_PCIE_ADDR_WIDTH-1:2] io_sq1_bs_addr_sync,
output [C_PCIE_ADDR_WIDTH-1:2] io_sq2_bs_addr_sync,
output [C_PCIE_ADDR_WIDTH-1:2] io_sq3_bs_addr_sync,
output [C_PCIE_ADDR_WIDTH-1:2] io_sq4_bs_addr_sync,
output [C_PCIE_ADDR_WIDTH-1:2] io_sq5_bs_addr_sync,
output [C_PCIE_ADDR_WIDTH-1:2] io_sq6_bs_addr_sync,
output [C_PCIE_ADDR_WIDTH-1:2] io_sq7_bs_addr_sync,
output [C_PCIE_ADDR_WIDTH-1:2] io_sq8_bs_addr_sync,
output [3:0] io_sq1_cq_vec_sync,
output [3:0] io_sq2_cq_vec_sync,
output [3:0] io_sq3_cq_vec_sync,
output [3:0] io_sq4_cq_vec_sync,
output [3:0] io_sq5_cq_vec_sync,
output [3:0] io_sq6_cq_vec_sync,
output [3:0] io_sq7_cq_vec_sync,
output [3:0] io_sq8_cq_vec_sync,
output [8:0] cq_rst_n_sync,
output [8:0] cq_valid_sync,
output [7:0] io_cq1_size_sync,
output [7:0] io_cq2_size_sync,
output [7:0] io_cq3_size_sync,
output [7:0] io_cq4_size_sync,
output [7:0] io_cq5_size_sync,
output [7:0] io_cq6_size_sync,
output [7:0] io_cq7_size_sync,
output [7:0] io_cq8_size_sync,
output [C_PCIE_ADDR_WIDTH-1:2] io_cq1_bs_addr_sync,
output [C_PCIE_ADDR_WIDTH-1:2] io_cq2_bs_addr_sync,
output [C_PCIE_ADDR_WIDTH-1:2] io_cq3_bs_addr_sync,
output [C_PCIE_ADDR_WIDTH-1:2] io_cq4_bs_addr_sync,
output [C_PCIE_ADDR_WIDTH-1:2] io_cq5_bs_addr_sync,
output [C_PCIE_ADDR_WIDTH-1:2] io_cq6_bs_addr_sync,
output [C_PCIE_ADDR_WIDTH-1:2] io_cq7_bs_addr_sync,
output [C_PCIE_ADDR_WIDTH-1:2] io_cq8_bs_addr_sync,
output [8:0] io_cq_irq_en_sync,
output [2:0] io_cq1_iv_sync,
output [2:0] io_cq2_iv_sync,
output [2:0] io_cq3_iv_sync,
output [2:0] io_cq4_iv_sync,
output [2:0] io_cq5_iv_sync,
output [2:0] io_cq6_iv_sync,
output [2:0] io_cq7_iv_sync,
output [2:0] io_cq8_iv_sync
);
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_pcie_link_up;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_pcie_link_up_d1;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [5:0] r_pl_ltssm_state;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [5:0] r_pl_ltssm_state_d1;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [15:0] r_cfg_command;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [15:0] r_cfg_command_d1;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [2:0] r_cfg_interrupt_mmenable;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [2:0] r_cfg_interrupt_mmenable_d1;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_cfg_interrupt_msienable;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_cfg_interrupt_msienable_d1;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_cfg_interrupt_msixenable;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_cfg_interrupt_msixenable_d1;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_pcie_mreq_err;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_pcie_mreq_err_d1;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_pcie_cpld_err;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_pcie_cpld_err_d1;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_pcie_cpld_len_err;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_pcie_cpld_len_err_d1;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_nvme_cc_en;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_nvme_cc_en_d1;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [1:0] r_nvme_cc_shn;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [1:0] r_nvme_cc_shn_d1;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [1:0] r_nvme_csts_shst;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [1:0] r_nvme_csts_shst_d1;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_nvme_csts_rdy;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_nvme_csts_rdy_d1;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [8:0] r_sq_valid;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [8:0] r_sq_valid_d1;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [8:0] r_sq_valid_d2;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [8:0] r_sq_valid_d3;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [7:0] r_io_sq1_size;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [7:0] r_io_sq2_size;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [7:0] r_io_sq3_size;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [7:0] r_io_sq4_size;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [7:0] r_io_sq5_size;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [7:0] r_io_sq6_size;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [7:0] r_io_sq7_size;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [7:0] r_io_sq8_size;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [C_PCIE_ADDR_WIDTH-1:2] r_io_sq1_bs_addr;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [C_PCIE_ADDR_WIDTH-1:2] r_io_sq2_bs_addr;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [C_PCIE_ADDR_WIDTH-1:2] r_io_sq3_bs_addr;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [C_PCIE_ADDR_WIDTH-1:2] r_io_sq4_bs_addr;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [C_PCIE_ADDR_WIDTH-1:2] r_io_sq5_bs_addr;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [C_PCIE_ADDR_WIDTH-1:2] r_io_sq6_bs_addr;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [C_PCIE_ADDR_WIDTH-1:2] r_io_sq7_bs_addr;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [C_PCIE_ADDR_WIDTH-1:2] r_io_sq8_bs_addr;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [3:0] r_io_sq1_cq_vec;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [3:0] r_io_sq2_cq_vec;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [3:0] r_io_sq3_cq_vec;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [3:0] r_io_sq4_cq_vec;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [3:0] r_io_sq5_cq_vec;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [3:0] r_io_sq6_cq_vec;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [3:0] r_io_sq7_cq_vec;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [3:0] r_io_sq8_cq_vec;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [8:0] r_cq_valid;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [8:0] r_cq_valid_d1;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [8:0] r_cq_valid_d2;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [8:0] r_cq_valid_d3;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [7:0] r_io_cq1_size;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [7:0] r_io_cq2_size;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [7:0] r_io_cq3_size;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [7:0] r_io_cq4_size;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [7:0] r_io_cq5_size;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [7:0] r_io_cq6_size;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [7:0] r_io_cq7_size;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [7:0] r_io_cq8_size;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [C_PCIE_ADDR_WIDTH-1:2] r_io_cq1_bs_addr;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [C_PCIE_ADDR_WIDTH-1:2] r_io_cq2_bs_addr;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [C_PCIE_ADDR_WIDTH-1:2] r_io_cq3_bs_addr;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [C_PCIE_ADDR_WIDTH-1:2] r_io_cq4_bs_addr;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [C_PCIE_ADDR_WIDTH-1:2] r_io_cq5_bs_addr;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [C_PCIE_ADDR_WIDTH-1:2] r_io_cq6_bs_addr;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [C_PCIE_ADDR_WIDTH-1:2] r_io_cq7_bs_addr;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [C_PCIE_ADDR_WIDTH-1:2] r_io_cq8_bs_addr;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [8:0] r_io_cq_irq_en;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [8:0] r_io_cq_irq_en_d1;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [2:0] r_io_cq1_iv;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [2:0] r_io_cq2_iv;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [2:0] r_io_cq3_iv;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [2:0] r_io_cq4_iv;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [2:0] r_io_cq5_iv;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [2:0] r_io_cq6_iv;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [2:0] r_io_cq7_iv;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [2:0] r_io_cq8_iv;
assign pcie_link_up_sync = r_pcie_link_up_d1;
assign pl_ltssm_state_sync = r_pl_ltssm_state_d1;
assign cfg_command_sync = r_cfg_command_d1;
assign cfg_interrupt_mmenable_sync = r_cfg_interrupt_mmenable_d1;
assign cfg_interrupt_msienable_sync = r_cfg_interrupt_msienable_d1;
assign cfg_interrupt_msixenable_sync = r_cfg_interrupt_msixenable_d1;
assign pcie_mreq_err_sync = r_pcie_mreq_err_d1;
assign pcie_cpld_err_sync = r_pcie_cpld_err_d1;
assign pcie_cpld_len_err_sync = r_pcie_cpld_len_err_d1;
assign nvme_cc_en_sync = r_nvme_cc_en_d1;
assign nvme_cc_shn_sync = r_nvme_cc_shn_d1;
assign nvme_csts_shst_sync = r_nvme_csts_shst_d1;
assign nvme_csts_rdy_sync = r_nvme_csts_rdy_d1;
assign sq_rst_n_sync = r_sq_valid_d3;
assign sq_valid_sync = r_sq_valid_d1;
assign io_sq1_size_sync = r_io_sq1_size;
assign io_sq2_size_sync = r_io_sq2_size;
assign io_sq3_size_sync = r_io_sq3_size;
assign io_sq4_size_sync = r_io_sq4_size;
assign io_sq5_size_sync = r_io_sq5_size;
assign io_sq6_size_sync = r_io_sq6_size;
assign io_sq7_size_sync = r_io_sq7_size;
assign io_sq8_size_sync = r_io_sq8_size;
assign io_sq1_bs_addr_sync = r_io_sq1_bs_addr;
assign io_sq2_bs_addr_sync = r_io_sq2_bs_addr;
assign io_sq3_bs_addr_sync = r_io_sq3_bs_addr;
assign io_sq4_bs_addr_sync = r_io_sq4_bs_addr;
assign io_sq5_bs_addr_sync = r_io_sq5_bs_addr;
assign io_sq6_bs_addr_sync = r_io_sq6_bs_addr;
assign io_sq7_bs_addr_sync = r_io_sq7_bs_addr;
assign io_sq8_bs_addr_sync = r_io_sq8_bs_addr;
assign io_sq1_cq_vec_sync = r_io_sq1_cq_vec;
assign io_sq2_cq_vec_sync = r_io_sq2_cq_vec;
assign io_sq3_cq_vec_sync = r_io_sq3_cq_vec;
assign io_sq4_cq_vec_sync = r_io_sq4_cq_vec;
assign io_sq5_cq_vec_sync = r_io_sq5_cq_vec;
assign io_sq6_cq_vec_sync = r_io_sq6_cq_vec;
assign io_sq7_cq_vec_sync = r_io_sq7_cq_vec;
assign io_sq8_cq_vec_sync = r_io_sq8_cq_vec;
assign cq_rst_n_sync = r_cq_valid_d3;
assign cq_valid_sync = r_cq_valid_d1;
assign io_cq1_size_sync = r_io_cq1_size;
assign io_cq2_size_sync = r_io_cq2_size;
assign io_cq3_size_sync = r_io_cq3_size;
assign io_cq4_size_sync = r_io_cq4_size;
assign io_cq5_size_sync = r_io_cq5_size;
assign io_cq6_size_sync = r_io_cq6_size;
assign io_cq7_size_sync = r_io_cq7_size;
assign io_cq8_size_sync = r_io_cq8_size;
assign io_cq1_bs_addr_sync = r_io_cq1_bs_addr;
assign io_cq2_bs_addr_sync = r_io_cq2_bs_addr;
assign io_cq3_bs_addr_sync = r_io_cq3_bs_addr;
assign io_cq4_bs_addr_sync = r_io_cq4_bs_addr;
assign io_cq5_bs_addr_sync = r_io_cq5_bs_addr;
assign io_cq6_bs_addr_sync = r_io_cq6_bs_addr;
assign io_cq7_bs_addr_sync = r_io_cq7_bs_addr;
assign io_cq8_bs_addr_sync = r_io_cq8_bs_addr;
assign io_cq_irq_en_sync = r_io_cq_irq_en_d1;
assign io_cq1_iv_sync = r_io_cq1_iv;
assign io_cq2_iv_sync = r_io_cq2_iv;
assign io_cq3_iv_sync = r_io_cq3_iv;
assign io_cq4_iv_sync = r_io_cq4_iv;
assign io_cq5_iv_sync = r_io_cq5_iv;
assign io_cq6_iv_sync = r_io_cq6_iv;
assign io_cq7_iv_sync = r_io_cq7_iv;
assign io_cq8_iv_sync = r_io_cq8_iv;
always @ (posedge cpu_bus_clk)
begin
r_pcie_link_up <= pcie_link_up;
r_pcie_link_up_d1 <= r_pcie_link_up;
r_pl_ltssm_state <= pl_ltssm_state;
r_pl_ltssm_state_d1 <= r_pl_ltssm_state;
r_cfg_command <= cfg_command;
r_cfg_command_d1 <= r_cfg_command;
r_cfg_interrupt_mmenable <= cfg_interrupt_mmenable;
r_cfg_interrupt_mmenable_d1 <= r_cfg_interrupt_mmenable;
r_cfg_interrupt_msienable <= cfg_interrupt_msienable;
r_cfg_interrupt_msienable_d1 <= r_cfg_interrupt_msienable;
r_cfg_interrupt_msixenable <= cfg_interrupt_msixenable;
r_cfg_interrupt_msixenable_d1 <= r_cfg_interrupt_msixenable;
r_pcie_mreq_err <= pcie_mreq_err;
r_pcie_mreq_err_d1 <= r_pcie_mreq_err;
r_pcie_cpld_err <= pcie_cpld_err;
r_pcie_cpld_err_d1 <= r_pcie_cpld_err;
r_pcie_cpld_len_err <= pcie_cpld_len_err;
r_pcie_cpld_len_err_d1 <= r_pcie_cpld_len_err;
r_nvme_cc_en <= nvme_cc_en;
r_nvme_cc_en_d1 <= r_nvme_cc_en;
r_nvme_cc_shn <= nvme_cc_shn;
r_nvme_cc_shn_d1 <= r_nvme_cc_shn;
end
always @ (posedge pcie_user_clk)
begin
r_nvme_csts_shst <= nvme_csts_shst;
r_nvme_csts_shst_d1 <= r_nvme_csts_shst;
r_nvme_csts_rdy <= nvme_csts_rdy;
r_nvme_csts_rdy_d1 <= r_nvme_csts_rdy;
r_sq_valid <= sq_valid;
r_sq_valid_d1 <= r_sq_valid;
r_sq_valid_d2 <= r_sq_valid_d1;
r_sq_valid_d3 <= r_sq_valid_d2;
r_io_sq1_size <= io_sq1_size;
r_io_sq2_size <= io_sq2_size;
r_io_sq3_size <= io_sq3_size;
r_io_sq4_size <= io_sq4_size;
r_io_sq5_size <= io_sq5_size;
r_io_sq6_size <= io_sq6_size;
r_io_sq7_size <= io_sq7_size;
r_io_sq8_size <= io_sq8_size;
r_io_sq1_bs_addr <= io_sq1_bs_addr;
r_io_sq2_bs_addr <= io_sq2_bs_addr;
r_io_sq3_bs_addr <= io_sq3_bs_addr;
r_io_sq4_bs_addr <= io_sq4_bs_addr;
r_io_sq5_bs_addr <= io_sq5_bs_addr;
r_io_sq6_bs_addr <= io_sq6_bs_addr;
r_io_sq7_bs_addr <= io_sq7_bs_addr;
r_io_sq8_bs_addr <= io_sq8_bs_addr;
r_io_sq1_cq_vec <= io_sq1_cq_vec;
r_io_sq2_cq_vec <= io_sq2_cq_vec;
r_io_sq3_cq_vec <= io_sq3_cq_vec;
r_io_sq4_cq_vec <= io_sq4_cq_vec;
r_io_sq5_cq_vec <= io_sq5_cq_vec;
r_io_sq6_cq_vec <= io_sq6_cq_vec;
r_io_sq7_cq_vec <= io_sq7_cq_vec;
r_io_sq8_cq_vec <= io_sq8_cq_vec;
r_cq_valid <= cq_valid;
r_cq_valid_d1 <= r_cq_valid;
r_cq_valid_d2 <= r_cq_valid_d1;
r_cq_valid_d3 <= r_cq_valid_d2;
r_io_cq1_size <= io_cq1_size;
r_io_cq2_size <= io_cq2_size;
r_io_cq3_size <= io_cq3_size;
r_io_cq4_size <= io_cq4_size;
r_io_cq5_size <= io_cq5_size;
r_io_cq6_size <= io_cq6_size;
r_io_cq7_size <= io_cq7_size;
r_io_cq8_size <= io_cq8_size;
r_io_cq1_bs_addr <= io_cq1_bs_addr;
r_io_cq2_bs_addr <= io_cq2_bs_addr;
r_io_cq3_bs_addr <= io_cq3_bs_addr;
r_io_cq4_bs_addr <= io_cq4_bs_addr;
r_io_cq5_bs_addr <= io_cq5_bs_addr;
r_io_cq6_bs_addr <= io_cq6_bs_addr;
r_io_cq7_bs_addr <= io_cq7_bs_addr;
r_io_cq8_bs_addr <= io_cq8_bs_addr;
r_io_cq_irq_en <= io_cq_irq_en;
r_io_cq_irq_en_d1 <= r_io_cq_irq_en;
r_io_cq1_iv <= io_cq1_iv;
r_io_cq2_iv <= io_cq2_iv;
r_io_cq3_iv <= io_cq3_iv;
r_io_cq4_iv <= io_cq4_iv;
r_io_cq5_iv <= io_cq5_iv;
r_io_cq6_iv <= io_cq6_iv;
r_io_cq7_iv <= io_cq7_iv;
r_io_cq8_iv <= io_cq8_iv;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__DFSTP_PP_BLACKBOX_V
`define SKY130_FD_SC_HDLL__DFSTP_PP_BLACKBOX_V
/**
* dfstp: Delay flop, inverted set, single output.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__dfstp (
Q ,
CLK ,
D ,
SET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
input CLK ;
input D ;
input SET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__DFSTP_PP_BLACKBOX_V
|
////////////////////////////////////////////////////////////////////////////////
// Original Author: Schuyler Eldridge
// Contact Point: Schuyler Eldridge ([email protected])
// button_debounce.v
// Created: 10/10/2009
// Modified: 3/20/2012
//
// Counter based debounce circuit originally written for EC551 (back
// in the day) and then modified (i.e. chagned entirely) into 3 always
// block format. This debouncer generates a signal that goes high for
// 1 clock cycle after the clock sees an asserted value on the button
// line. This action is then disabled until the counter hits a
// specified count value that is determined by the clock frequency and
// desired debounce frequency. An alternative implementation would not
// use a counter, but would use the shift register approach, looking
// for repeated matches (say 5) on the button line.
//
// Copyright (C) 2012 Schuyler Eldridge, Boston University
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
module button_debounce
(
input clk, // clock
input reset_n, // asynchronous reset
input button, // bouncy button
output reg debounce // debounced 1-cycle signal
);
parameter
CLK_FREQUENCY = 66000000,
DEBOUNCE_HZ = 2;
// These parameters are specified such that you can choose any power
// of 2 frequency for a debouncer between 1 Hz and
// CLK_FREQUENCY. Note, that this will throw errors if you choose a
// non power of 2 frequency (i.e. count_value evaluates to some
// number / 3 which isn't interpreted as a logical right shift). I'm
// assuming this will not work for DEBOUNCE_HZ values less than 1,
// however, I'm uncertain of the value of a debouncer for fractional
// hertz button presses.
localparam
COUNT_VALUE = CLK_FREQUENCY / DEBOUNCE_HZ,
WAIT = 0,
FIRE = 1,
COUNT = 2;
reg [1:0] state, next_state;
reg [25:0] count;
always @ (posedge clk or negedge reset_n)
state <= (!reset_n) ? WAIT : next_state;
always @ (posedge clk or negedge reset_n) begin
if (!reset_n) begin
debounce <= 0;
count <= 0;
end
else begin
debounce <= 0;
count <= 0;
case (state)
WAIT: begin
end
FIRE: begin
debounce <= 1;
end
COUNT: begin
count <= count + 1;
end
endcase
end
end
always @ * begin
case (state)
WAIT: next_state = (button) ? FIRE : state;
FIRE: next_state = COUNT;
COUNT: next_state = (count > COUNT_VALUE - 1) ? WAIT : state;
default: next_state = WAIT;
endcase
end
endmodule
|
/*
* I expect the following statistics results:
* 0 x 0 x x x
* 1 x 1 x 0 0
* 2 1 2 x 1 0
* 3 1 3 x 2 1
* 2 1 3 3 2 2
* 2 1 3 3 3 2
* 3 1 3 3 4 2
* 1 1 3 3 1 3
* 0 1 3 2 x 3
* 1 2 3 2 0 2
* 0 2 3 1 x 3
* 1 3 3 1 0 2
* 2 2 3 1 1 2
* 3 2 3 1 2 2
*
* x implies there is no defined value for that statistic.
*/
module top;
reg pass;
integer res, status, value, value2;
integer id, job, item;
initial begin
pass = 1'b1;
id = 1;
// Use id = 1, type = 1 (FIFO) and a size of 5.
$display("----- INIT -----");
$q_initialize(id, 1, 5, status);
if (status !== 0) begin
$display("Failed to initialize queue, got %d", status);
pass = 1'b0;
end
print_stats(id);
// Add an element to the queue.
job = 1;
item = 10;
$display("----- ADD -----");
$q_add(id, job, item, status);
if (status !== 0) begin
$display("Failed to add element to the queue, got %d", status);
pass = 1'b0;
end
print_stats(id);
#1;
// Add a second element to the queue.
job = 1;
item = 20;
$display("----- ADD -----");
$q_add(id, job, item, status);
if (status !== 0) begin
$display("Failed to add element to the queue, got %d", status);
pass = 1'b0;
end
print_stats(id);
#1;
// Add a third element to the queue.
job = 1;
item = 30;
$display("----- ADD -----");
$q_add(id, job, item, status);
if (status !== 0) begin
$display("Failed to add element to the queue, got %d", status);
pass = 1'b0;
end
print_stats(id);
#1;
// Remove an element from the queue.
$display("----- REMOVE -----");
$q_remove(id, value, value2, status);
if (status !== 0) begin
$display("Failed to remove element from the queue, got %d", status);
pass = 1'b0;
end
print_stats(id);
#1
print_stats(id);
#1;
// Add a fourth element to the queue.
job = 1;
item = 30;
$display("----- ADD -----");
$q_add(id, job, item, status);
if (status !== 0) begin
$display("Failed to add element to the queue, got %d", status);
pass = 1'b0;
end
print_stats(id);
#1;
// Remove two elements from the queue.
$display("----- REMOVE TWO -----");
$q_remove(id, value, value2, status);
if (status !== 0) begin
$display("Failed to remove element (1) from the queue, got %d", status);
pass = 1'b0;
end
$q_remove(id, value, value2, status);
if (status !== 0) begin
$display("Failed to remove element (2) from the queue, got %d", status);
pass = 1'b0;
end
print_stats(id);
#1;
// Remove an element from the queue.
$display("----- REMOVE -----");
$q_remove(id, value, value2, status);
if (status !== 0) begin
$display("Failed to remove element from the queue, got %d", status);
pass = 1'b0;
end
print_stats(id);
#1;
// Add a fifth element to the queue.
job = 1;
item = 50;
$display("----- ADD -----");
$q_add(id, job, item, status);
if (status !== 0) begin
$display("Failed to add element to the queue, got %d", status);
pass = 1'b0;
end
print_stats(id);
#1;
// Remove an element from the queue.
$display("----- REMOVE -----");
$q_remove(id, value, value2, status);
if (status !== 0) begin
$display("Failed to remove element from the queue, got %d", status);
pass = 1'b0;
end
print_stats(id);
#7;
// Add a sixth element to the queue.
job = 1;
item = 60;
$display("----- ADD -----");
$q_add(id, job, item, status);
if (status !== 0) begin
$display("Failed to add element to the queue, got %d", status);
pass = 1'b0;
end
print_stats(id);
#1;
// Add a seventh element to the queue.
job = 1;
item = 70;
$display("----- ADD -----");
$q_add(id, job, item, status);
if (status !== 0) begin
$display("Failed to add element to the queue, got %d", status);
pass = 1'b0;
end
print_stats(id);
#1;
// Add a eight element to the queue.
job = 1;
item = 80;
$display("----- ADD -----");
$q_add(id, job, item, status);
if (status !== 0) begin
$display("Failed to add element to the queue, got %d", status);
pass = 1'b0;
end
print_stats(id);
if (pass) $display("PASSED");
end
task print_stats;
input id;
integer id;
integer len, inter, max, short, long, avg, status;
// Icarus uses a status code of 10 to indicate no statistics available.
begin
len = 32'bx;
inter = 32'bx;
max = 32'bx;
short = 32'bx;
long = 32'bx;
avg = 32'bx;
$display("Queue statistics at time %0d", $time);
// Get the queue length.
$q_exam(id, 1, len, status);
if ((status !== 0) && (status !== 10)) begin
$display(" Failed to get the length, status %0d", status);
pass = 1'b0;
end
// Get the mean inter-arrival time.
$q_exam(id, 2, inter, status);
if ((status !== 0) && (status !== 10)) begin
$display(" Failed to get the inter-arrival, status %0d", status);
pass = 1'b0;
end
// Get the maximum length.
$q_exam(id, 3, max, status);
if ((status !== 0) && (status !== 10)) begin
$display(" Failed to get the maximum length, status %0d", status);
pass = 1'b0;
end
// Get the shortest wait time.
$q_exam(id, 4, short, status);
if ((status !== 0) && (status !== 10)) begin
$display(" Failed to get the shortest wait time, status %0d", status);
pass = 1'b0;
end
// Get the longest wait time.
$q_exam(id, 5, long, status);
if ((status !== 0) && (status !== 10)) begin
$display(" Failed to get the longest wait time, status %0d", status);
pass = 1'b0;
end
// Get the average wait time.
$q_exam(id, 6, avg, status);
if ((status !== 0) && (status !== 10)) begin
$display(" Failed to get the average wait time, status %0d", status);
pass = 1'b0;
end
$display(" %0d, %0d, %0d, %0d, %0d, %0d",
len, inter, max, short, long, avg);
end
endtask
endmodule
|
// megafunction wizard: %FIFO%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: scfifo
// ============================================================
// File Name: fifo_1kx16.v
// Megafunction Name(s):
// scfifo
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 5.1 Build 213 01/19/2006 SP 1 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2006 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module fifo_1kx16 (
aclr,
clock,
data,
rdreq,
wrreq,
almost_empty,
empty,
full,
q,
usedw);
input aclr;
input clock;
input [15:0] data;
input rdreq;
input wrreq;
output almost_empty;
output empty;
output full;
output [15:0] q;
output [9:0] usedw;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "1"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "504"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "0"
// Retrieval info: PRIVATE: Depth NUMERIC "1024"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: Optimize NUMERIC "2"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "2"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: Width NUMERIC "16"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "1"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF"
// Retrieval info: CONSTANT: ALMOST_EMPTY_VALUE NUMERIC "504"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
// Retrieval info: CONSTANT: LPM_HINT STRING "RAM_BLOCK_TYPE=M4K"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "1024"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
// Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "10"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr
// Retrieval info: USED_PORT: almost_empty 0 0 0 0 OUTPUT NODEFVAL almost_empty
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL data[15..0]
// Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL empty
// Retrieval info: USED_PORT: full 0 0 0 0 OUTPUT NODEFVAL full
// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL q[15..0]
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq
// Retrieval info: USED_PORT: usedw 0 0 10 0 OUTPUT NODEFVAL usedw[9..0]
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq
// Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0
// Retrieval info: CONNECT: q 0 0 16 0 @q 0 0 16 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: full 0 0 0 0 @full 0 0 0 0
// Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0
// Retrieval info: CONNECT: usedw 0 0 10 0 @usedw 0 0 10 0
// Retrieval info: CONNECT: almost_empty 0 0 0 0 @almost_empty 0 0 0 0
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16.inc TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16.cmp TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16.bsf TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16_bb.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16_waveforms.html FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16_wave*.jpg FALSE
|
//=============================================================================
// Verilog module generated by IPExpress 08/21/2007 16:22:41
// Filename: USERNAME_bb.v
// Copyright(c) 2005 Lattice Semiconductor Corporation. All rights reserved.
//=============================================================================
/* WARNING - Changes to this file should be performed by re-running IPexpress
or modifying the .LPC file and regenerating the core. Other changes may lead
to inconsistent simulation and/or implemenation results */
//---------------------------------------------------------------
// USERNAME synthesis black box definition
//---------------------------------------------------------------
module pcie (
input wire sys_clk_250, // 250 Mhz Clock
input wire sys_clk_125, // 125 Mhz Clock
input wire rst_n, // asynchronous system reset.
input wire inta_n,
input wire [7:0] msi,
input wire [15:0] vendor_id ,
input wire [15:0] device_id ,
input wire [7:0] rev_id ,
input wire [23:0] class_code ,
input wire [15:0] subsys_ven_id ,
input wire [15:0] subsys_id ,
input wire load_id ,
input wire force_lsm_active, // Force LSM Status Active
input wire force_rec_ei, // Force Received Electrical Idle
input wire force_phy_status, // Force PHY Connection Status
input wire force_disable_scr,// Force Disable Scrambler to PCS
input wire hl_snd_beacon, // HL req. to Send Beacon
input wire hl_disable_scr, // HL req. to Disable Scrambling bit in TS1/TS2
input wire hl_gto_dis, // HL req a jump to Disable
input wire hl_gto_det, // HL req a jump to detect
input wire hl_gto_hrst, // HL req a jump to Hot reset
input wire hl_gto_l0stx, // HL req a jump to TX L0s
input wire hl_gto_l1, // HL req a jump to L1
input wire hl_gto_l2, // HL req a jump to L2
input wire hl_gto_l0stxfts, // HL req a jump to L0s TX FTS
input wire hl_gto_lbk, // HL req a jump to Loopback
input wire hl_gto_rcvry, // HL req a jump to recovery
input wire hl_gto_cfg, // HL req a jump to CFG
input wire no_pcie_train, // Disable the training process
// Power Management Interface
input wire [1:0] tx_dllp_val, // Req for Sending PM/Vendor type DLLP
input wire [2:0] tx_pmtype, // Power Management Type
input wire [23:0] tx_vsd_data, // Vendor Type DLLP contents
// For VC Inputs
input wire tx_req_vc0, // VC0 Request from User
input wire [15:0] tx_data_vc0, // VC0 Input data from user logic
input wire tx_st_vc0, // VC0 start of pkt from user logic.
input wire tx_end_vc0, // VC0 End of pkt from user logic.
input wire tx_nlfy_vc0, // VC0 End of nullified pkt from user logic.
input wire ph_buf_status_vc0, // VC0 Indicate the Full/alm.Full status of the PH buffers
input wire pd_buf_status_vc0, // VC0 Indicate PD Buffer has got space less than Max Pkt size
input wire nph_buf_status_vc0, // VC0 For NPH
input wire npd_buf_status_vc0, // VC0 For NPD
input wire ph_processed_vc0, // VC0 TL has processed one TLP Header - PH Type
input wire pd_processed_vc0, // VC0 TL has processed one TLP Data - PD TYPE
input wire nph_processed_vc0, // VC0 For NPH
input wire npd_processed_vc0, // VC0 For NPD
input wire [7:0] pd_num_vc0, // VC0 For PD -- No. of Data processed
input wire [7:0] npd_num_vc0, // VC0 For PD
input wire [7:0] rxp_data, // CH0:PCI Express data from External Phy
input wire rxp_data_k, // CH0:PCI Express Control from External Phy
input wire rxp_valid, // CH0:Indicates a symbol lock and valid data on rx_data /rx_data_k
input wire rxp_elec_idle, // CH0:Inidicates receiver detection of an electrical signal
input wire [2:0] rxp_status, // CH0:Indicates receiver Staus/Error codes
input wire phy_status, // Indicates PHY status info
// From User logic
// From User logic
input wire cmpln_tout , // Completion time out.
input wire cmpltr_abort_np , // Completor abort.
input wire cmpltr_abort_p , // Completor abort.
input wire unexp_cmpln , // Unexpexted completion.
input wire ur_np_ext , // UR for NP type.
input wire ur_p_ext , // UR for P type.
input wire np_req_pend , // Non posted request is pending.
input wire pme_status , // PME status to reg 044h.
// User Loop back data
input wire [15:0] tx_lbk_data, // TX User Master Loopback data
input wire [1:0] tx_lbk_kcntl, // TX User Master Loopback control
output wire tx_lbk_rdy, // TX loop back is ready to accept data
output wire [15:0] rx_lbk_data, // RX User Master Loopback data
output wire [1:0] rx_lbk_kcntl, // RX User Master Loopback control
// Power Management/ Vendor specific DLLP
output wire tx_dllp_sent, // Requested PM DLLP is sent
output wire [2:0] rxdp_pmd_type, // PM DLLP type bits.
output wire [23:0] rxdp_vsd_data , // Vendor specific DLLP data.
output wire [1:0] rxdp_dllp_val, // PM/Vendor specific DLLP valid.
output wire [7:0] txp_data, // CH0:PCI Express data to External Phy
output wire txp_data_k, // CH0:PCI Express control to External Phy
output wire txp_elec_idle, // CH0:Tells PHY to output Electrical Idle
output wire txp_compliance, // CH0:Sets the PHY running disparity to -ve
output wire rxp_polarity, // CH0:Tells PHY to do polarity inversion on the received data
output wire txp_detect_rx_lb, // Tells PHY to begin receiver detection or begin Loopback
output wire reset_n, // Async reset to the PHY
output wire [1:0] power_down, // Tell sthe PHY to power Up or Down
output wire phy_pol_compliance, // Polling compliance
output wire [3:0] phy_ltssm_state, // Indicates the states of the ltssm
output wire [2:0] phy_ltssm_substate, // sub-states of the ltssm_state
output wire tx_rdy_vc0, // VC0 TX ready indicating signal
output wire [8:0] tx_ca_ph_vc0, // VC0 Available credit for Posted Type Headers
output wire [12:0] tx_ca_pd_vc0, // VC0 For Posted - Data
output wire [8:0] tx_ca_nph_vc0, // VC0 For Non-posted - Header
output wire [12:0] tx_ca_npd_vc0, // VC0 For Non-posted - Data
output wire [8:0] tx_ca_cplh_vc0, // VC0 For Completion - Header
output wire [12:0] tx_ca_cpld_vc0, // VC0 For Completion - Data
output wire tx_ca_p_recheck_vc0, //
output wire tx_ca_cpl_recheck_vc0, //
output wire [15:0] rx_data_vc0, // VC0 Receive data
output wire rx_st_vc0, // VC0 Receive data start
output wire rx_end_vc0, // VC0 Receive data end
output wire rx_us_req_vc0 , // VC0 unsupported req received
output wire rx_malf_tlp_vc0 ,// VC0 malformed TLP in received data
output wire [6:0] rx_bar_hit , // Bar hit
output wire [2:0] mm_enable , // Multiple message enable bits of Register
output wire msi_enable , // MSI enable bit of Register
// From Config Registers
output wire [7:0] bus_num , // Bus number
output wire [4:0] dev_num , // Device number
output wire [2:0] func_num , // Function number
output wire [1:0] pm_power_state , // Power state bits of Register at 044h
output wire pme_en , // PME_En at 044h
output wire [5:0] cmd_reg_out , // Bits 10,8,6,2,1,0 From register 004h
output wire [14:0] dev_cntl_out , // Divice control register at 060h
output wire [7:0] lnk_cntl_out , // Link control register at 068h
// To ASPM implementation outside the IP
output wire tx_rbuf_empty, // Transmit retry buffer is empty
output wire tx_dllp_pend, // DLPP is pending to be transmitted
output wire rx_tlp_rcvd, // Received a TLP
// Datal Link Control SM Status
output wire dl_inactive, // Data Link Control SM is in INACTIVE state
output wire dl_init, // INIT state
output wire dl_active, // ACTIVE state
output wire dl_up // Data Link Layer is UP
);
endmodule
|
// DESCRIPTION: Test that slice assignment overflows are handled correctly,
// i.e. that if you assign to a slice such that some of the bits you assign to
// do not actually exist, that those bits get correctly discarded.
// Issue #2803 existed in a number number of different codepaths in
// verilated.h and V3Expand.cpp. This test should cover all of these cases
// when run both with and without the -Ox flag to verilator.
// - Select offset constant, insert IData into CData
// - Select offset constant, insert IData into SData
// - Select offset constant, insert IData into IData
// - Select offset constant, insert QData into QData
// - Select offset constant, insert IData into WData within a word
// - Select offset constant, insert IData into WData crossing a word boundary
// - Select offset constant, insert IData into WData whole word insertion
// - Select offset constant, insert QData into WData
// - Select offset constant, insert WData into WData, several whole words
// - Select offset constant, insert WData into WData, starting at word-offset
// - Select offset constant, insert WData into WData, all other cases
// - Select offset is non-constant, destination is wide, bit-select width == 1
// - Select offset is non-constant, destination is wide, bit-select width != 1
// - Select offset is non-constant, destination is narrow
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2021 by David Turner.
// SPDX-License-Identifier: CC0-1.0
module t(/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc = 0;
// Non-constant offsets
reg varoffset1;
reg [6:0] varoffset2;
reg [6:0] varoffset3;
// Destinations for variable-offset assignments
reg [69:0] dstwide1;
reg [69:0] dstwide2;
reg [1:0] dstnarrow;
// Constant offsets
reg [6:0] constoffset;
// Destinations for constant-offset assignments
reg [2:0] dst_cdata;
reg [11:0] dst_sdata;
reg [29:0] dst_idata;
reg [59:0] dst_qdata;
reg [69:0] dst_wdata1; // assign idata within word
reg [69:0] dst_wdata2; // assign idata crossing word boundary
reg [69:0] dst_wdata3; // assign idata corresponding to whole word
reg [69:0] dst_wdata4; // assign qdata
reg [69:0] dst_wdata5; // assign wdata corresponding to several whole words
reg [69:0] dst_wdata6; // assign wdata starting at word-offset
reg [69:0] dst_wdata7; // assign wdata unaligned
always @(*) begin
// Non-constant select offset, destination narrow
dstnarrow = 2'd0;
dstnarrow[varoffset1 +: 2'd2] = 2'd2;
// Non-constant select offset, destination wide, width == 1
dstwide1 = 70'd0;
dstwide1[varoffset2 +: 1'd1] = 1'd1;
// Non-constant select offset, destination wide, width != 1
dstwide2 = 70'd0;
dstwide2[varoffset3 +: 2'd2] = 2'd2;
// Constant offset, IData into CData
constoffset = 7'd2;
dst_cdata = 3'd0;
dst_cdata[constoffset[0 +: 2] +: 3'd3] = 3'd6;
// Constant offset, IData into SData
constoffset = 7'd11;
dst_sdata = 12'd0;
dst_sdata[constoffset[0 +: 4] +: 2'd2] = 2'd2;
// Constant offset, IData into IData
constoffset = 7'd29;
dst_idata = 30'd0;
dst_idata[constoffset[0 +: 5] +: 2'd2] = 2'd2;
// Constant offset, QData into QData
constoffset = 7'd59;
dst_qdata = 60'd0;
dst_qdata[constoffset[0 +: 6] +: 2'd2] = 2'd2;
// Constant offset, IData into WData within word
constoffset = 7'd69;
dst_wdata1 = 70'd0;
dst_wdata1[constoffset +: 2'd2] = 2'd2;
// Constant offset, IData into WData crossing word boundary
constoffset = 7'd61;
dst_wdata2 = 70'd0;
dst_wdata2[constoffset +: 4'd10] = 10'd1 << 4'd9;
// Constant offset, IData into WData replacing a whole word
constoffset = 7'd64;
dst_wdata3 = 70'd0;
dst_wdata3[constoffset +: 6'd32] = 32'd1 << 3'd6;
// Constant offset, QData into WData
constoffset = 7'd31;
dst_wdata4 = 70'd0;
dst_wdata4[constoffset +: 7'd40] = 40'd1 << 7'd39;
// Constant offset, WData into WData replacing whole words
constoffset = 7'd32;
dst_wdata5 = 70'd0;
dst_wdata5[constoffset +: 7'd64] = 64'd1 << 7'd38;
// Constant offset, WData into WData offset word aligned
constoffset = 7'd32;
dst_wdata6 = 70'd0;
dst_wdata6[constoffset +: 7'd40] = 40'd1 << 7'd38;
// Constant offset, WData into WData unaligned
constoffset = 7'd1;
dst_wdata7 = 70'd0;
dst_wdata7[constoffset +: 7'd70] = 70'd1 << 7'd69;
end
// Test loop
always @ (posedge clk) begin
// State machine to avoid verilator constant-folding offset
if (cyc == 0) begin
// Initialisation
varoffset1 <= 1'd0;
varoffset2 <= 7'd0;
varoffset3 <= 7'd0;
end else if (cyc == 1) begin
// Variable offsets set here to avoid verilator constant folding
varoffset1 <= 1'd1;
varoffset2 <= 7'd70;
varoffset3 <= 7'd69;
end else if (cyc == 2) begin
// Check all destinations are 0
$write("dstwide1 = %23d, downshifted = %23d\n", dstwide1, dstwide1 >> 1);
$write("dstwide2 = %23d, downshifted = %23d\n", dstwide2, dstwide2 >> 1);
$write("dstnarrow = %23d, downshifted = %23d\n", dstnarrow, dstnarrow >> 1);
$write("dst_cdata = %23d, downshifted = %23d\n", dst_cdata, dst_cdata >> 1);
$write("dst_sdata = %23d, downshifted = %23d\n", dst_sdata, dst_sdata >> 1);
$write("dst_idata = %23d, downshifted = %23d\n", dst_idata, dst_idata >> 1);
$write("dst_qdata = %23d, downshifted = %23d\n", dst_qdata, dst_qdata >> 1);
$write("dst_wdata1 = %23d, downshifted = %23d\n", dst_wdata1, dst_wdata1 >> 1);
$write("dst_wdata2 = %23d, downshifted = %23d\n", dst_wdata2, dst_wdata2 >> 1);
$write("dst_wdata3 = %23d, downshifted = %23d\n", dst_wdata3, dst_wdata3 >> 1);
$write("dst_wdata4 = %23d, downshifted = %23d\n", dst_wdata4, dst_wdata4 >> 1);
$write("dst_wdata5 = %23d, downshifted = %23d\n", dst_wdata5, dst_wdata5 >> 1);
$write("dst_wdata6 = %23d, downshifted = %23d\n", dst_wdata6, dst_wdata6 >> 1);
$write("dst_wdata7 = %23d, downshifted = %23d\n", dst_wdata7, dst_wdata7 >> 1);
if (dstwide1 !== 70'd0 || (dstwide1 >> 1) !== 70'd0) $stop;
if (dstwide2 !== 70'd0 || (dstwide2 >> 1) !== 70'd0) $stop;
if (dstnarrow !== 2'd0 || (dstnarrow >> 1) !== 2'd0) $stop;
if (dst_cdata !== 3'd0 || (dst_cdata >> 1) !== 3'd0) $stop;
if (dst_sdata !== 12'd0 || (dst_sdata >> 1) !== 12'd0) $stop;
if (dst_idata !== 30'd0 || (dst_idata >> 1) !== 30'd0) $stop;
if (dst_qdata !== 60'd0 || (dst_qdata >> 1) !== 60'd0) $stop;
if (dst_wdata1 !== 70'd0 || (dst_wdata1 >> 1) !== 70'd0) $stop;
if (dst_wdata2 !== 70'd0 || (dst_wdata2 >> 1) !== 70'd0) $stop;
if (dst_wdata3 !== 70'd0 || (dst_wdata3 >> 1) !== 70'd0) $stop;
if (dst_wdata4 !== 70'd0 || (dst_wdata4 >> 1) !== 70'd0) $stop;
if (dst_wdata5 !== 70'd0 || (dst_wdata5 >> 1) !== 70'd0) $stop;
if (dst_wdata6 !== 70'd0 || (dst_wdata6 >> 1) !== 70'd0) $stop;
if (dst_wdata7 !== 70'd0 || (dst_wdata7 >> 1) !== 70'd0) $stop;
end else begin
$write("*-* All Finished *-*\n");
$finish;
end
cyc <= cyc + 1;
end
endmodule
|
//
`default_nettype none
`ifdef ALT_MEM_PHY_DEFINES
`else
`include "alt_mem_phy_defines.v"
`endif
//
(* altera_attribute = "-name MESSAGE_DISABLE 14130", altera_attribute = "-name SYNCHRONIZER_IDENTIFICATION OFF" *) module ddr2_phy_alt_mem_phy (
//Clock and reset inputs:
pll_ref_clk,
global_reset_n,
soft_reset_n,
// Used to indicate PLL loss of lock for system reset management:
reset_request_n,
// Clock and reset for the controller interface:
ctl_clk,
ctl_reset_n,
// Write data interface:
ctl_dqs_burst,
ctl_wdata_valid,
ctl_wdata,
ctl_dm,
ctl_wlat,
// Address and command interface:
ctl_addr,
ctl_ba,
ctl_cas_n,
ctl_cke,
ctl_cs_n,
ctl_odt,
ctl_ras_n,
ctl_we_n,
ctl_rst_n,
ctl_mem_clk_disable,
// Read data interface:
ctl_doing_rd,
ctl_rdata,
ctl_rdata_valid,
ctl_rlat,
//re-calibration request & configuration:
ctl_cal_req,
ctl_cal_byte_lane_sel_n,
//Calibration status interface:
ctl_cal_success,
ctl_cal_fail,
ctl_cal_warning,
//ports to memory device(s):
mem_addr,
mem_ba,
mem_cas_n,
mem_cke,
mem_cs_n,
mem_dm,
mem_odt,
mem_ras_n,
mem_we_n,
mem_clk,
mem_clk_n,
mem_reset_n,
// Bidirectional Memory interface signals:
mem_dq,
mem_dqs,
mem_dqs_n,
// Auxiliary clocks. Some systems may need these for debugging
// purposes, or for full-rate to half-rate bridge interfaces
aux_half_rate_clk,
aux_full_rate_clk,
// On Chip Termination: - dynamically updated values.
oct_ctl_rs_value,
oct_ctl_rt_value,
// DLL import/export ports
dqs_offset_delay_ctrl,
dqs_delay_ctrl_import,
dqs_delay_ctrl_export,
dll_reference_clk,
// Debug interface:- ALTERA USE ONLY
dbg_clk,
dbg_reset_n,
dbg_addr,
dbg_wr,
dbg_rd,
dbg_cs,
dbg_wr_data,
dbg_rd_data,
dbg_waitrequest
);
// Default parameter values :
parameter FAMILY = "CYCLONEIII";
parameter MEM_IF_MEMTYPE = "DDR2";
parameter SPEED_GRADE = "C6";
parameter DLL_DELAY_BUFFER_MODE = "HIGH";
parameter DLL_DELAY_CHAIN_LENGTH = 8;
parameter DQS_DELAY_CTL_WIDTH = 6;
parameter DQS_OUT_MODE = "DELAY_CHAIN2";
parameter DQS_PHASE = 9000;
parameter DQS_PHASE_SETTING = 2;
parameter DWIDTH_RATIO = 4;
parameter MEM_IF_DWIDTH = 64;
parameter MEM_IF_ADDR_WIDTH = 13;
parameter MEM_IF_BANKADDR_WIDTH = 3;
parameter MEM_IF_CS_WIDTH = 2;
parameter MEM_IF_DM_WIDTH = 8;
parameter MEM_IF_DM_PINS_EN = 1;
parameter MEM_IF_DQ_PER_DQS = 8;
parameter MEM_IF_DQS_WIDTH = 8;
parameter MEM_IF_OCT_EN = 0;
parameter MEM_IF_CLK_PAIR_COUNT = 3;
parameter MEM_IF_CLK_PS = 4000;
parameter MEM_IF_CLK_PS_STR = "4000 ps";
parameter MEM_IF_MR_0 = 0;
parameter MEM_IF_MR_1 = 0;
parameter MEM_IF_MR_2 = 0;
parameter MEM_IF_MR_3 = 0;
parameter MEM_IF_PRESET_RLAT = 0;
parameter PLL_STEPS_PER_CYCLE = 24;
parameter SCAN_CLK_DIVIDE_BY = 4;
parameter REDUCE_SIM_TIME = 0;
parameter CAPABILITIES = 0;
parameter TINIT_TCK = 40000;
parameter TINIT_RST = 100000;
parameter DBG_A_WIDTH = 13;
parameter SEQ_STRING_ID = "seq_name";
parameter MEM_IF_CS_PER_RANK = 1; // duplicates CS, CKE, ODT, sequencer still controls 1 rank, but it is subdivided from controller perspective.
parameter MEM_IF_RANKS_PER_SLOT = 1; // how ranks are arranged into slot - needed for odt setting in the sequencer
parameter MEM_IF_RDV_PER_CHIP = 0; // multiple chips, and which gives valid data
parameter GENERATE_ADDITIONAL_DBG_RTL = 0; // DDR2 sequencer specific
parameter CAPTURE_PHASE_OFFSET = 0;
parameter MEM_IF_ADDR_CMD_PHASE = 0;
parameter DLL_EXPORT_IMPORT = "NONE";
parameter MEM_IF_DQSN_EN = 1;
parameter RANK_HAS_ADDR_SWAP = 0;
parameter INVERT_POSTAMBLE_CLK = "false";
//
localparam phy_report_prefix = "ddr2_phy_alt_mem_phy (top level) : ";
localparam POSTAMBLE_AWIDTH = 6;
localparam POSTAMBLE_HALFT_EN = 0;
localparam POSTAMBLE_INITIAL_LAT = 16;
localparam POSTAMBLE_RESYNC_LAT_CTL_EN = 0;
// function to set the USE_MEM_CLK_FOR_ADDR_CMD_CLK localparam based on MEM_IF_ADDR_CMD_PHASE
function integer set_mem_clk_for_ac_clk (input reg [23:0] addr_cmd_phase);
integer return_value;
begin
return_value = 0;
case (addr_cmd_phase)
0, 180 : return_value = 1;
90, 270 : return_value = 0;
default : begin
//synthesis translate_off
$display(phy_report_prefix, "Illegal value set on MEM_IF_ADDR_CMD_PHASE parameter: ", addr_cmd_phase);
$stop;
//synthesis translate_on
end
endcase
set_mem_clk_for_ac_clk = return_value;
end
endfunction
// function to set the ADDR_CMD_NEGEDGE_EN localparam based on MEM_IF_ADDR_CMD_PHASE
function integer set_ac_negedge_en(input reg [23:0] addr_cmd_phase);
integer return_value;
begin
return_value = 0;
case (addr_cmd_phase)
90, 180 : return_value = 1;
0, 270 : return_value = 0;
default : begin
//synthesis translate_off
$display(phy_report_prefix, "Illegal value set on MEM_IF_ADDR_CMD_PHASE parameter: ", addr_cmd_phase);
$stop;
//synthesis translate_on
end
endcase
set_ac_negedge_en = return_value;
end
endfunction
localparam USE_MEM_CLK_FOR_ADDR_CMD_CLK = set_mem_clk_for_ac_clk(MEM_IF_ADDR_CMD_PHASE);
localparam ADDR_CMD_NEGEDGE_EN = set_ac_negedge_en(MEM_IF_ADDR_CMD_PHASE);
localparam LOCAL_IF_DWIDTH = MEM_IF_DWIDTH*DWIDTH_RATIO;
localparam MEM_IF_POSTAMBLE_EN_WIDTH = MEM_IF_DWIDTH/MEM_IF_DQ_PER_DQS;
localparam LOCAL_IF_CLK_PS = MEM_IF_CLK_PS/(DWIDTH_RATIO/2);
localparam PLL_REF_CLK_PS = LOCAL_IF_CLK_PS;
localparam MEM_IF_DQS_CAPTURE_EN = 1;
localparam ADDR_COUNT_WIDTH = 4;
localparam RDP_RESYNC_LAT_CTL_EN = 0;
localparam DEDICATED_MEMORY_CLK_EN = 0;
localparam ADV_LAT_WIDTH = 5;
localparam CAPTURE_MIMIC_PATH = 0;
localparam DDR_MIMIC_PATH_EN = 1;
localparam MIMIC_DEBUG_EN = 0;
localparam NUM_MIMIC_SAMPLE_CYCLES = 6;
localparam NUM_DEBUG_SAMPLES_TO_STORE = 4096;
localparam ASYNCHRONOUS_AVALON_CLOCK = 1;
localparam RDV_INITIAL_LAT = 23;
localparam RDP_INITIAL_LAT = 6;
localparam RESYNC_PIPELINE_DEPTH = 0;
localparam CLOCK_INDEX_WIDTH = 3;
localparam OCT_LAT_WIDTH = ADV_LAT_WIDTH;
// I/O Signal definitions :
// Clock and reset I/O :
input wire pll_ref_clk;
input wire global_reset_n;
input wire soft_reset_n;
// This is the PLL locked signal :
output wire reset_request_n;
// The controller must use this phy_clk to interface to the PHY. It is
// optional as to whether the remainder of the system uses it :
output wire ctl_clk;
output wire ctl_reset_n;
// new AFI I/Os - write data i/f:
input wire [MEM_IF_DQS_WIDTH * DWIDTH_RATIO/2 -1 : 0] ctl_dqs_burst;
input wire [MEM_IF_DQS_WIDTH * DWIDTH_RATIO/2 -1 : 0] ctl_wdata_valid;
input wire [MEM_IF_DWIDTH * DWIDTH_RATIO -1 : 0] ctl_wdata;
input wire [MEM_IF_DM_WIDTH * DWIDTH_RATIO -1 : 0] ctl_dm;
output wire [4 : 0] ctl_wlat;
// new AFI I/Os - addr/cmd i/f:
input wire [MEM_IF_ADDR_WIDTH * DWIDTH_RATIO/2 -1 : 0] ctl_addr;
input wire [MEM_IF_BANKADDR_WIDTH * DWIDTH_RATIO/2 -1 : 0] ctl_ba;
input wire [1 * DWIDTH_RATIO/2 -1 : 0] ctl_cas_n;
input wire [MEM_IF_CS_WIDTH * DWIDTH_RATIO/2 - 1:0] ctl_cke;
input wire [MEM_IF_CS_WIDTH * DWIDTH_RATIO/2 - 1:0] ctl_cs_n;
input wire [MEM_IF_CS_WIDTH * DWIDTH_RATIO/2 - 1:0] ctl_odt;
input wire [1 * DWIDTH_RATIO/2 -1 : 0] ctl_ras_n;
input wire [1 * DWIDTH_RATIO/2 -1 : 0] ctl_we_n;
input wire [DWIDTH_RATIO/2 - 1 : 0] ctl_rst_n;
input wire [MEM_IF_CLK_PAIR_COUNT - 1 : 0] ctl_mem_clk_disable;
// new AFI I/Os - read data i/f:
input wire [MEM_IF_DQS_WIDTH * DWIDTH_RATIO / 2 -1 : 0] ctl_doing_rd;
output wire [MEM_IF_DWIDTH * DWIDTH_RATIO -1 : 0] ctl_rdata;
output wire [DWIDTH_RATIO / 2 -1 : 0] ctl_rdata_valid;
output wire [4 : 0] ctl_rlat;
// re-calibration request and configuration:
input wire ctl_cal_req;
input wire [MEM_IF_DQS_WIDTH * MEM_IF_CS_WIDTH - 1 : 0] ctl_cal_byte_lane_sel_n;
// new AFI I/Os - status interface:
output wire ctl_cal_success;
output wire ctl_cal_fail;
output wire ctl_cal_warning;
//Outputs to DIMM :
output wire [MEM_IF_ADDR_WIDTH - 1 : 0] mem_addr;
output wire [MEM_IF_BANKADDR_WIDTH - 1 : 0] mem_ba;
output wire mem_cas_n;
output wire [MEM_IF_CS_WIDTH - 1 : 0] mem_cke;
output wire [MEM_IF_CS_WIDTH - 1 : 0] mem_cs_n;
wire [MEM_IF_DWIDTH - 1 : 0] mem_d;
output wire [MEM_IF_DM_WIDTH - 1 : 0] mem_dm;
output wire [MEM_IF_CS_WIDTH - 1 : 0] mem_odt;
output wire mem_ras_n;
output wire mem_we_n;
output wire mem_reset_n;
//The mem_clks are outputs, but one is sometimes used for the mimic_path, so
//is looped back in. Therefore defining as an inout ensures no errors in Quartus :
inout wire [MEM_IF_CLK_PAIR_COUNT - 1 : 0] mem_clk;
inout wire [MEM_IF_CLK_PAIR_COUNT - 1 : 0] mem_clk_n;
//Bidirectional:
inout tri [MEM_IF_DWIDTH - 1 : 0] mem_dq;
inout tri [MEM_IF_DWIDTH / MEM_IF_DQ_PER_DQS - 1 : 0] mem_dqs;
inout tri [MEM_IF_DWIDTH / MEM_IF_DQ_PER_DQS - 1 : 0] mem_dqs_n;
input wire [`OCT_SERIES_TERM_CONTROL_WIDTH -1 : 0] oct_ctl_rs_value;
input wire [`OCT_PARALLEL_TERM_CONTROL_WIDTH -1 : 0] oct_ctl_rt_value;
// DQS offsetting is possible with the ArriaII hardware, however this is unsupported by the IP
// in this release :
input wire [DQS_DELAY_CTL_WIDTH - 1 : 0 ] dqs_offset_delay_ctrl;
input wire [DQS_DELAY_CTL_WIDTH - 1 : 0 ] dqs_delay_ctrl_import;
output wire [DQS_DELAY_CTL_WIDTH - 1 : 0 ] dqs_delay_ctrl_export;
output wire dll_reference_clk;
// AVALON MM Slave -- debug IF
input wire dbg_clk;
input wire dbg_reset_n;
input wire [DBG_A_WIDTH -1 : 0] dbg_addr;
input wire dbg_wr;
input wire dbg_rd;
input wire dbg_cs;
input wire [31 : 0] dbg_wr_data;
output wire [31 : 0] dbg_rd_data;
output wire dbg_waitrequest;
// Auxillary clocks. These do not have to be connected if the system
// doesn't require them :
output wire aux_half_rate_clk;
output wire aux_full_rate_clk;
// Internal signal declarations :
// Clocks :
// full-rate memory clock
wire mem_clk_2x;
// write_clk_2x is a full-rate write clock. It is -90 degress aligned to the
// system clock :
wire write_clk_2x;
wire phy_clk_1x_src;
wire phy_clk_1x;
wire ac_clk_1x;
wire ac_clk_2x;
wire cs_n_clk_1x;
wire cs_n_clk_2x;
wire postamble_clk_2x;
wire resync_clk_2x;
wire measure_clk_1x;
wire measure_clk_2x;
wire half_rate_clk;
wire [DQS_DELAY_CTL_WIDTH - 1 : 0 ] dedicated_dll_delay_ctrl;
// resets, async assert, de-assert is sync'd to each clock domain
wire reset_mem_clk_2x_n;
wire reset_rdp_phy_clk_1x_n;
wire reset_phy_clk_1x_n;
wire reset_ac_clk_1x_n;
wire reset_ac_clk_2x_n;
wire reset_cs_n_clk_1x_n;
wire reset_cs_n_clk_2x_n;
wire reset_mimic_2x_n;
wire [MEM_IF_DQS_WIDTH - 1 : 0] reset_resync_clk_1x_n;
wire reset_resync_clk_2x_n;
wire reset_seq_n;
wire reset_measure_clk_1x_n;
wire reset_measure_clk_2x_n;
wire reset_poa_clk_2x_n;
wire reset_write_clk_2x_n;
// Misc signals :
wire phs_shft_busy;
wire pll_seq_reconfig_busy;
// Postamble signals :
wire [MEM_IF_DQS_WIDTH * DWIDTH_RATIO /2 - 1 : 0] poa_postamble_en_preset;
wire [MEM_IF_POSTAMBLE_EN_WIDTH - 1 : 0] poa_postamble_en_preset_2x;
// Sequencer signals
wire seq_mmc_start;
wire seq_pll_inc_dec_n;
wire seq_pll_start_reconfig;
wire [CLOCK_INDEX_WIDTH - 1 : 0] seq_pll_select;
wire [MEM_IF_DQS_WIDTH -1 : 0] seq_rdp_dec_read_lat_1x;
wire [MEM_IF_DQS_WIDTH -1 : 0] seq_rdp_inc_read_lat_1x;
wire [MEM_IF_DQS_WIDTH -1 : 0] seq_poa_lat_dec_1x;
wire [MEM_IF_DQS_WIDTH -1 : 0] seq_poa_lat_inc_1x;
wire seq_poa_protection_override_1x;
wire seq_rdp_reset_req_n;
wire seq_ac_sel;
wire [MEM_IF_ADDR_WIDTH * DWIDTH_RATIO/2 - 1 : 0] seq_ac_addr;
wire [MEM_IF_BANKADDR_WIDTH * DWIDTH_RATIO/2 - 1 : 0] seq_ac_ba;
wire [DWIDTH_RATIO/2 -1 : 0] seq_ac_cas_n;
wire [DWIDTH_RATIO/2 -1 : 0] seq_ac_ras_n;
wire [DWIDTH_RATIO/2 -1 : 0] seq_ac_we_n;
wire [MEM_IF_CS_WIDTH * DWIDTH_RATIO/2 - 1 : 0] seq_ac_cke;
wire [MEM_IF_CS_WIDTH * DWIDTH_RATIO/2 - 1 : 0] seq_ac_cs_n;
wire [MEM_IF_CS_WIDTH * DWIDTH_RATIO/2 - 1 : 0] seq_ac_odt;
wire [DWIDTH_RATIO * MEM_IF_DM_WIDTH - 1 : 0 ] seq_wdp_dm;
wire [MEM_IF_DQS_WIDTH * (DWIDTH_RATIO/2) - 1 : 0] seq_wdp_dqs_burst;
wire [MEM_IF_DWIDTH * DWIDTH_RATIO - 1 : 0 ] seq_wdp_wdata;
wire [MEM_IF_DQS_WIDTH * (DWIDTH_RATIO/2) - 1 : 0] seq_wdp_wdata_valid;
wire [DWIDTH_RATIO - 1 :0] seq_wdp_dqs;
wire seq_wdp_ovride;
wire [MEM_IF_DQS_WIDTH * (DWIDTH_RATIO/2) - 1 : 0] oct_rsst_sel;
wire [MEM_IF_DQS_WIDTH * DWIDTH_RATIO/2 - 1 : 0] seq_doing_rd;
wire seq_rdata_valid_lat_inc;
wire seq_rdata_valid_lat_dec;
wire [DWIDTH_RATIO/2 - 1 : 0] seq_rdata_valid;
reg [DQS_DELAY_CTL_WIDTH - 1 : 0 ] dedicated_dll_delay_ctrl_r;
wire [DQS_DELAY_CTL_WIDTH - 1 : 0 ] dqs_delay_ctrl_internal;
wire [DQS_DELAY_CTL_WIDTH - 1 : 0 ] dqs_delay_ctrl; // Output from clk_reset block
// set pll clock index of resync and mimic clocks
wire [CLOCK_INDEX_WIDTH - 1 : 0] pll_resync_clk_index;
wire [CLOCK_INDEX_WIDTH - 1 : 0] pll_measure_clk_index;
// The clk_reset block provides the sc_clk to the sequencer and DP blocks.
wire sc_clk;
wire [MEM_IF_DQS_WIDTH - 1 : 0] sc_clk_dp;
// Mimic signals :
wire mmc_seq_done;
wire mmc_seq_value;
wire mimic_data;
wire mux_seq_controller_ready;
wire mux_seq_wdata_req;
// Read datapath signals :
// Connections from the IOE to the read datapath :
wire [MEM_IF_DWIDTH - 1 : 0] dio_rdata_h_2x;
wire [MEM_IF_DWIDTH - 1 : 0] dio_rdata_l_2x;
// Write datapath signals :
// wires from the wdp to the dpio :
wire [MEM_IF_DWIDTH - 1 : 0] wdp_wdata3_1x;
wire [MEM_IF_DWIDTH - 1 : 0] wdp_wdata2_1x;
wire [MEM_IF_DWIDTH - 1 : 0] wdp_wdata1_1x;
wire [MEM_IF_DWIDTH - 1 : 0] wdp_wdata0_1x;
wire [MEM_IF_DWIDTH - 1 : 0] wdp_wdata_h_2x;
wire [MEM_IF_DWIDTH - 1 : 0] wdp_wdata_l_2x;
wire [MEM_IF_DWIDTH - 1 : 0] wdp_wdata_oe_2x;
wire [(LOCAL_IF_DWIDTH/8) - 1 : 0] ctl_mem_be;
wire [MEM_IF_DQS_WIDTH - 1 : 0] wdp_wdata_oe_h_1x;
wire [MEM_IF_DQS_WIDTH - 1 : 0] wdp_wdata_oe_l_1x;
wire [MEM_IF_DQS_WIDTH - 1 : 0] wdp_dqs3_1x;
wire [MEM_IF_DQS_WIDTH - 1 : 0] wdp_dqs2_1x;
wire [MEM_IF_DQS_WIDTH - 1 : 0] wdp_dqs1_1x;
wire [MEM_IF_DQS_WIDTH - 1 : 0] wdp_dqs0_1x;
wire [(MEM_IF_DQS_WIDTH) - 1 : 0] wdp_wdqs_2x;
wire [MEM_IF_DQS_WIDTH - 1 : 0] wdp_dqs_oe_h_1x;
wire [MEM_IF_DQS_WIDTH - 1 : 0] wdp_dqs_oe_l_1x;
wire [(MEM_IF_DQS_WIDTH) - 1 : 0] wdp_wdqs_oe_2x;
wire [MEM_IF_DM_WIDTH -1 : 0] wdp_dm3_1x;
wire [MEM_IF_DM_WIDTH -1 : 0] wdp_dm2_1x;
wire [MEM_IF_DM_WIDTH -1 : 0] wdp_dm1_1x;
wire [MEM_IF_DM_WIDTH -1 : 0] wdp_dm0_1x;
wire [MEM_IF_DM_WIDTH -1 : 0] wdp_dm_h_2x;
wire [MEM_IF_DM_WIDTH -1 : 0] wdp_dm_l_2x;
wire [MEM_IF_DQS_WIDTH -1 : 0] wdp_oct_h_1x;
wire [MEM_IF_DQS_WIDTH -1 : 0] wdp_oct_l_1x;
wire [MEM_IF_DQS_WIDTH -1 : 0] seq_dqs_add_2t_delay;
wire ctl_add_1t_ac_lat_internal;
wire ctl_add_1t_odt_lat_internal;
wire ctl_add_intermediate_regs_internal;
wire ctl_negedge_en_internal;
wire ctl_mem_dqs_burst;
wire [MEM_IF_DWIDTH*DWIDTH_RATIO - 1 : 0] ctl_mem_wdata;
wire ctl_mem_wdata_valid;
// These ports are tied off for DDR,DDR2,DDR3. Registers are used to reduce Quartus warnings :
(* preserve *) reg [3 : 0] ctl_mem_dqs = 4'b1100;
wire [MEM_IF_CS_WIDTH - 1 : 0] int_rank_has_addr_swap;
//SIII declarations :
//Outputs from the dp_io block to the read_dp block :
wire [MEM_IF_DWIDTH - 1 : 0] dio_rdata3_1x;
wire [MEM_IF_DWIDTH - 1 : 0] dio_rdata2_1x;
wire [MEM_IF_DWIDTH - 1 : 0] dio_rdata1_1x;
wire [MEM_IF_DWIDTH - 1 : 0] dio_rdata0_1x;
wire [MEM_IF_DQS_WIDTH * DWIDTH_RATIO/2 - 1 : 0] merged_doing_rd;
wire [OCT_LAT_WIDTH - 1 : 0] seq_oct_oct_delay; // oct_lat
wire [OCT_LAT_WIDTH - 1 : 0] seq_oct_oct_extend; //oct_extend_duration
wire seq_oct_val;
wire seq_mem_clk_disable;
wire [DWIDTH_RATIO/2 - 1 : 0] seq_ac_rst_n;
wire dqs_delay_update_en;
wire [DQS_DELAY_CTL_WIDTH - 1 : 0 ] dlloffset_offsetctrl_out;
// Use either the imported DQS delay or the clock/reset output :
generate
if (DLL_EXPORT_IMPORT == "IMPORT")
assign dqs_delay_ctrl_internal = dqs_delay_ctrl_import;
else
assign dqs_delay_ctrl_internal = dqs_delay_ctrl;
endgenerate
// Generate auxillary clocks:
generate
// Half-rate mode :
if (DWIDTH_RATIO == 4)
begin
assign aux_half_rate_clk = phy_clk_1x;
assign aux_full_rate_clk = mem_clk_2x;
end
// Full-rate mode :
else
begin
assign aux_half_rate_clk = half_rate_clk;
assign aux_full_rate_clk = phy_clk_1x;
end
endgenerate
// The top level I/O should not have the "Nx" clock domain suffices, so this is
// assigned here. Also note that to avoid delta delay issues both the external and
// internal phy_clks are assigned to a common 'src' clock :
assign ctl_clk = phy_clk_1x_src;
assign phy_clk_1x = phy_clk_1x_src;
assign ctl_reset_n = reset_phy_clk_1x_n;
// Export the internally generated DQS delay :
assign dqs_delay_ctrl_export = dqs_delay_ctrl;
assign dll_reference_clk = mem_clk_2x;
// Instance I/O modules :
//
ddr2_phy_alt_mem_phy_dp_io #(
.MEM_IF_DWIDTH (MEM_IF_DWIDTH),
.MEM_IF_DM_PINS_EN (MEM_IF_DM_PINS_EN),
.MEM_IF_DM_WIDTH (MEM_IF_DM_WIDTH),
.MEM_IF_DQ_PER_DQS (MEM_IF_DQ_PER_DQS),
.MEM_IF_DQS_WIDTH (MEM_IF_DQS_WIDTH),
.MEM_IF_MEMTYPE (MEM_IF_MEMTYPE),
.MEM_IF_DQSN_EN (MEM_IF_DQSN_EN),
.MEM_IF_POSTAMBLE_EN_WIDTH (MEM_IF_POSTAMBLE_EN_WIDTH),
.DQS_DELAY_CTL_WIDTH (DQS_DELAY_CTL_WIDTH)
) dpio (
.reset_write_clk_2x_n (reset_write_clk_2x_n),
.resync_clk_2x (resync_clk_2x),
.postamble_clk_2x (postamble_clk_2x),
.mem_clk_2x (mem_clk_2x),
.write_clk_2x (write_clk_2x),
.dqs_delay_ctrl (dqs_delay_ctrl_internal),
.mem_dm (mem_dm),
.mem_dq (mem_dq),
.mem_dqs (mem_dqs),
.mem_dqsn (mem_dqs_n),
.dio_rdata_h_2x (dio_rdata_h_2x),
.dio_rdata_l_2x (dio_rdata_l_2x),
.poa_postamble_en_preset_2x (poa_postamble_en_preset_2x),
.wdp_dm_h_2x (wdp_dm_h_2x),
.wdp_dm_l_2x (wdp_dm_l_2x),
.wdp_wdata_h_2x (wdp_wdata_h_2x),
.wdp_wdata_l_2x (wdp_wdata_l_2x),
.wdp_wdata_oe_2x (wdp_wdata_oe_2x),
.wdp_wdqs_2x (wdp_wdqs_2x),
.wdp_wdqs_oe_2x (wdp_wdqs_oe_2x)
);
// Instance the read datapath :
//
ddr2_phy_alt_mem_phy_read_dp #(
.ADDR_COUNT_WIDTH (ADDR_COUNT_WIDTH),
.BIDIR_DPINS (1),
.DWIDTH_RATIO (DWIDTH_RATIO),
.MEM_IF_CLK_PS (MEM_IF_CLK_PS),
.FAMILY (FAMILY),
.LOCAL_IF_DWIDTH (LOCAL_IF_DWIDTH),
.MEM_IF_DQ_PER_DQS (MEM_IF_DQ_PER_DQS),
.MEM_IF_DQS_WIDTH (MEM_IF_DQS_WIDTH),
.MEM_IF_DWIDTH (MEM_IF_DWIDTH),
.RDP_INITIAL_LAT (RDP_INITIAL_LAT),
.RDP_RESYNC_LAT_CTL_EN (RDP_RESYNC_LAT_CTL_EN),
.RESYNC_PIPELINE_DEPTH (RESYNC_PIPELINE_DEPTH)
) rdp (
.phy_clk_1x (phy_clk_1x),
.resync_clk_2x (resync_clk_2x),
.reset_phy_clk_1x_n (reset_rdp_phy_clk_1x_n),
.reset_resync_clk_2x_n (reset_resync_clk_2x_n),
.seq_rdp_dec_read_lat_1x (seq_rdp_dec_read_lat_1x[0]),
.seq_rdp_dmx_swap (1'b0),
.seq_rdp_inc_read_lat_1x (seq_rdp_inc_read_lat_1x[0]),
.dio_rdata_h_2x (dio_rdata_h_2x),
.dio_rdata_l_2x (dio_rdata_l_2x),
.ctl_mem_rdata (ctl_rdata)
);
// enhancements a different delay per dqs group may be implemented using the
// full vector
// Instance the write datapath :
generate
// Half-rate Write datapath :
if (DWIDTH_RATIO == 4)
begin : half_rate_wdp_gen
//
ddr2_phy_alt_mem_phy_write_dp #(
.MEM_IF_MEMTYPE (MEM_IF_MEMTYPE),
.BIDIR_DPINS (1),
.LOCAL_IF_DRATE ("HALF"),
.LOCAL_IF_DWIDTH (LOCAL_IF_DWIDTH),
.MEM_IF_DM_WIDTH (MEM_IF_DM_WIDTH),
.MEM_IF_DQ_PER_DQS (MEM_IF_DQ_PER_DQS),
.MEM_IF_DQS_WIDTH (MEM_IF_DQS_WIDTH),
.GENERATE_WRITE_DQS (1),
.MEM_IF_DWIDTH (MEM_IF_DWIDTH),
.DWIDTH_RATIO (DWIDTH_RATIO)
) wdp (
.phy_clk_1x (phy_clk_1x),
.mem_clk_2x (mem_clk_2x),
.write_clk_2x (write_clk_2x),
.reset_phy_clk_1x_n (reset_phy_clk_1x_n),
.reset_mem_clk_2x_n (reset_mem_clk_2x_n),
.reset_write_clk_2x_n (reset_write_clk_2x_n),
.ctl_mem_be (ctl_dm),
.ctl_mem_dqs_burst (ctl_dqs_burst),
.ctl_mem_wdata (ctl_wdata),
.ctl_mem_wdata_valid (ctl_wdata_valid),
.seq_be (seq_wdp_dm),
.seq_dqs_burst (seq_wdp_dqs_burst),
.seq_wdata (seq_wdp_wdata),
.seq_wdata_valid (seq_wdp_wdata_valid),
.seq_ctl_sel (seq_wdp_ovride),
.wdp_wdata_h_2x (wdp_wdata_h_2x),
.wdp_wdata_l_2x (wdp_wdata_l_2x),
.wdp_wdata_oe_2x (wdp_wdata_oe_2x),
.wdp_wdqs_2x (wdp_wdqs_2x),
.wdp_wdqs_oe_2x (wdp_wdqs_oe_2x),
.wdp_dm_h_2x (wdp_dm_h_2x),
.wdp_dm_l_2x (wdp_dm_l_2x)
);
end
// Full-rate :
else
begin : full_rate_wdp_gen
//
ddr2_phy_alt_mem_phy_write_dp_fr #(
.BIDIR_DPINS (1),
.LOCAL_IF_DRATE ("FULL"),
.LOCAL_IF_DWIDTH (LOCAL_IF_DWIDTH),
.MEM_IF_DM_WIDTH (MEM_IF_DM_WIDTH),
.MEM_IF_DQ_PER_DQS (MEM_IF_DQ_PER_DQS),
.MEM_IF_DQS_WIDTH (MEM_IF_DQS_WIDTH),
.GENERATE_WRITE_DQS (1),
.MEM_IF_DWIDTH (MEM_IF_DWIDTH),
.DWIDTH_RATIO (DWIDTH_RATIO)
) wdp (
.phy_clk_1x (phy_clk_1x),
.mem_clk_2x (mem_clk_2x),
.write_clk_2x (write_clk_2x),
.reset_phy_clk_1x_n (reset_phy_clk_1x_n),
.reset_mem_clk_2x_n (reset_mem_clk_2x_n),
.reset_write_clk_2x_n (reset_write_clk_2x_n),
.ctl_mem_be (ctl_dm),
.ctl_mem_dqs_burst (ctl_dqs_burst),
.ctl_mem_wdata (ctl_wdata),
.ctl_mem_wdata_valid (ctl_wdata_valid),
.seq_be (seq_wdp_dm),
.seq_dqs_burst (seq_wdp_dqs_burst),
.seq_wdata (seq_wdp_wdata),
.seq_wdata_valid (seq_wdp_wdata_valid),
.seq_ctl_sel (seq_wdp_ovride),
.wdp_wdata_h_2x (wdp_wdata_h_2x),
.wdp_wdata_l_2x (wdp_wdata_l_2x),
.wdp_wdata_oe_2x (wdp_wdata_oe_2x),
.wdp_wdqs_2x (wdp_wdqs_2x),
.wdp_wdqs_oe_2x (wdp_wdqs_oe_2x),
.wdp_dm_h_2x (wdp_dm_h_2x),
.wdp_dm_l_2x (wdp_dm_l_2x)
);
end
endgenerate
// Instance the address and command :
// A CIII ADC block is used, as the ADC clock may be set to one of four quadrant positions,
// not an arbitrary PLL phase :
generate
// Half-rate address and command :
if (DWIDTH_RATIO == 4)
begin : half_rate_adc_gen
//
ddr2_phy_alt_mem_phy_addr_cmd #(
.DWIDTH_RATIO (DWIDTH_RATIO),
.MEM_ADDR_CMD_BUS_COUNT (1),
.MEM_IF_BANKADDR_WIDTH (MEM_IF_BANKADDR_WIDTH),
.MEM_IF_CS_WIDTH (MEM_IF_CS_WIDTH),
.MEM_IF_MEMTYPE (MEM_IF_MEMTYPE),
.MEM_IF_ROWADDR_WIDTH (MEM_IF_ADDR_WIDTH)
) adc (
.ac_clk_1x (ac_clk_1x),
.ac_clk_2x (ac_clk_2x),
.cs_n_clk_1x (cs_n_clk_1x),
.cs_n_clk_2x (cs_n_clk_2x),
.phy_clk_1x (phy_clk_1x),
.reset_ac_clk_1x_n (reset_ac_clk_1x_n),
.reset_ac_clk_2x_n (reset_ac_clk_2x_n),
.reset_cs_n_clk_1x_n (reset_cs_n_clk_1x_n),
.reset_cs_n_clk_2x_n (reset_cs_n_clk_2x_n),
.ctl_add_1t_ac_lat (ctl_add_1t_ac_lat_internal),
.ctl_add_1t_odt_lat (ctl_add_1t_odt_lat_internal),
.ctl_add_intermediate_regs (ctl_add_intermediate_regs_internal),
// .ctl_negedge_en (ctl_negedge_en_internal),
.ctl_negedge_en (ADDR_CMD_NEGEDGE_EN[0 : 0]),
.ctl_mem_addr_h (ctl_addr[MEM_IF_ADDR_WIDTH -1 : 0]),
.ctl_mem_addr_l (ctl_addr[(MEM_IF_ADDR_WIDTH * DWIDTH_RATIO/2) -1 : MEM_IF_ADDR_WIDTH]),
.ctl_mem_ba_h (ctl_ba[MEM_IF_BANKADDR_WIDTH -1 : 0]),
.ctl_mem_ba_l (ctl_ba[MEM_IF_BANKADDR_WIDTH * DWIDTH_RATIO/2 -1 : MEM_IF_BANKADDR_WIDTH]),
.ctl_mem_cas_n_h (ctl_cas_n[0]),
.ctl_mem_cas_n_l (ctl_cas_n[1]),
.ctl_mem_cke_h (ctl_cke[MEM_IF_CS_WIDTH - 1 : 0]),
.ctl_mem_cke_l (ctl_cke[MEM_IF_CS_WIDTH * DWIDTH_RATIO/2 - 1 : MEM_IF_CS_WIDTH]),
.ctl_mem_cs_n_h (ctl_cs_n[MEM_IF_CS_WIDTH - 1 : 0]),
.ctl_mem_cs_n_l (ctl_cs_n[MEM_IF_CS_WIDTH * DWIDTH_RATIO/2 - 1 : MEM_IF_CS_WIDTH]),
.ctl_mem_odt_h (ctl_odt[MEM_IF_CS_WIDTH - 1 : 0]),
.ctl_mem_odt_l (ctl_odt[MEM_IF_CS_WIDTH * DWIDTH_RATIO/2 - 1 : MEM_IF_CS_WIDTH]),
.ctl_mem_ras_n_h (ctl_ras_n[0]),
.ctl_mem_ras_n_l (ctl_ras_n[1]),
.ctl_mem_we_n_h (ctl_we_n[0]),
.ctl_mem_we_n_l (ctl_we_n[1]),
.ctl_mem_rst_n_h (ctl_rst_n[0]),
.ctl_mem_rst_n_l (ctl_rst_n[1]),
.seq_addr_h (seq_ac_addr[MEM_IF_ADDR_WIDTH -1 : 0]),
.seq_addr_l (seq_ac_addr[MEM_IF_ADDR_WIDTH * DWIDTH_RATIO/2 -1 : MEM_IF_ADDR_WIDTH]),
.seq_ba_h (seq_ac_ba[MEM_IF_BANKADDR_WIDTH -1 : 0]),
.seq_ba_l (seq_ac_ba[MEM_IF_BANKADDR_WIDTH * DWIDTH_RATIO/2 -1 : MEM_IF_BANKADDR_WIDTH]),
.seq_cas_n_h (seq_ac_cas_n[0]),
.seq_cas_n_l (seq_ac_cas_n[1]),
.seq_cke_h (seq_ac_cke[MEM_IF_CS_WIDTH - 1 : 0]),
.seq_cke_l (seq_ac_cke[MEM_IF_CS_WIDTH * DWIDTH_RATIO/2 - 1 : MEM_IF_CS_WIDTH]),
.seq_cs_n_h (seq_ac_cs_n[MEM_IF_CS_WIDTH - 1 : 0]),
.seq_cs_n_l (seq_ac_cs_n[MEM_IF_CS_WIDTH * DWIDTH_RATIO/2 - 1 : MEM_IF_CS_WIDTH]),
.seq_odt_h (seq_ac_odt[MEM_IF_CS_WIDTH - 1 : 0]),
.seq_odt_l (seq_ac_odt[MEM_IF_CS_WIDTH * DWIDTH_RATIO/2 - 1 : MEM_IF_CS_WIDTH]),
.seq_ras_n_h (seq_ac_ras_n[0]),
.seq_ras_n_l (seq_ac_ras_n[1]),
.seq_we_n_h (seq_ac_we_n[0]),
.seq_we_n_l (seq_ac_we_n[1]),
.seq_mem_rst_n_h (seq_ac_rst_n[0]),
.seq_mem_rst_n_l (seq_ac_rst_n[1]),
.seq_ac_sel (seq_ac_sel),
.mem_addr (mem_addr),
.mem_ba (mem_ba),
.mem_cas_n (mem_cas_n),
.mem_cke (mem_cke),
.mem_cs_n (mem_cs_n),
.mem_odt (mem_odt),
.mem_ras_n (mem_ras_n),
.mem_we_n (mem_we_n),
.mem_rst_n (mem_reset_n)
);
end
// Full-rate :
else
begin : full_rate_adc_gen
//
ddr2_phy_alt_mem_phy_addr_cmd #(
.DWIDTH_RATIO (DWIDTH_RATIO),
.MEM_ADDR_CMD_BUS_COUNT (1),
.MEM_IF_BANKADDR_WIDTH (MEM_IF_BANKADDR_WIDTH),
.MEM_IF_CS_WIDTH (MEM_IF_CS_WIDTH),
.MEM_IF_MEMTYPE (MEM_IF_MEMTYPE),
.MEM_IF_ROWADDR_WIDTH (MEM_IF_ADDR_WIDTH)
) adc (
.ac_clk_1x (ac_clk_1x),
.ac_clk_2x (ac_clk_2x),
.cs_n_clk_1x (cs_n_clk_1x),
.cs_n_clk_2x (cs_n_clk_2x),
.phy_clk_1x (phy_clk_1x),
.reset_ac_clk_1x_n (reset_ac_clk_1x_n),
.reset_ac_clk_2x_n (reset_ac_clk_2x_n),
.reset_cs_n_clk_1x_n (reset_cs_n_clk_1x_n),
.reset_cs_n_clk_2x_n (reset_cs_n_clk_2x_n),
.ctl_add_1t_ac_lat (ctl_add_1t_ac_lat_internal),
.ctl_add_1t_odt_lat (ctl_add_1t_odt_lat_internal),
.ctl_add_intermediate_regs (ctl_add_intermediate_regs_internal),
// .ctl_negedge_en (ctl_negedge_en_internal),
.ctl_negedge_en (ADDR_CMD_NEGEDGE_EN[0 : 0]),
.ctl_mem_addr_h (),
.ctl_mem_addr_l (ctl_addr[MEM_IF_ADDR_WIDTH -1 : 0]),
.ctl_mem_ba_h (),
.ctl_mem_ba_l (ctl_ba[MEM_IF_BANKADDR_WIDTH -1 : 0]),
.ctl_mem_cas_n_h (),
.ctl_mem_cas_n_l (ctl_cas_n[0]),
.ctl_mem_cke_h (),
.ctl_mem_cke_l (ctl_cke[MEM_IF_CS_WIDTH - 1 : 0]),
.ctl_mem_cs_n_h (),
.ctl_mem_cs_n_l (ctl_cs_n[MEM_IF_CS_WIDTH - 1 : 0]),
.ctl_mem_odt_h (),
.ctl_mem_odt_l (ctl_odt[MEM_IF_CS_WIDTH - 1 : 0]),
.ctl_mem_ras_n_h (),
.ctl_mem_ras_n_l (ctl_ras_n[0]),
.ctl_mem_we_n_h (),
.ctl_mem_we_n_l (ctl_we_n[0]),
.ctl_mem_rst_n_h (),
.ctl_mem_rst_n_l (ctl_rst_n[0]),
.seq_addr_h (),
.seq_addr_l (seq_ac_addr[MEM_IF_ADDR_WIDTH -1 : 0]),
.seq_ba_h (),
.seq_ba_l (seq_ac_ba[MEM_IF_BANKADDR_WIDTH -1 : 0]),
.seq_cas_n_h (),
.seq_cas_n_l (seq_ac_cas_n[0]),
.seq_cke_h (),
.seq_cke_l (seq_ac_cke[MEM_IF_CS_WIDTH - 1 : 0]),
.seq_cs_n_h (),
.seq_cs_n_l (seq_ac_cs_n[MEM_IF_CS_WIDTH - 1 : 0]),
.seq_odt_h (),
.seq_odt_l (seq_ac_odt[MEM_IF_CS_WIDTH - 1 : 0]),
.seq_ras_n_h (),
.seq_ras_n_l (seq_ac_ras_n[0]),
.seq_we_n_h (),
.seq_we_n_l (seq_ac_we_n[0]),
.seq_mem_rst_n_h (),
.seq_mem_rst_n_l (seq_ac_rst_n[0]),
.seq_ac_sel (seq_ac_sel),
.mem_addr (mem_addr),
.mem_ba (mem_ba),
.mem_cas_n (mem_cas_n),
.mem_cke (mem_cke),
.mem_cs_n (mem_cs_n),
.mem_odt (mem_odt),
.mem_ras_n (mem_ras_n),
.mem_we_n (mem_we_n),
.mem_rst_n (mem_reset_n)
);
end
endgenerate
//
ddr2_phy_alt_mem_phy_postamble #(
.FAMILY (FAMILY),
.DWIDTH_RATIO (DWIDTH_RATIO),
.MEM_IF_POSTAMBLE_EN_WIDTH (MEM_IF_POSTAMBLE_EN_WIDTH),
.POSTAMBLE_AWIDTH (POSTAMBLE_AWIDTH),
.POSTAMBLE_HALFT_EN (POSTAMBLE_HALFT_EN),
.POSTAMBLE_INITIAL_LAT (POSTAMBLE_INITIAL_LAT),
.POSTAMBLE_RESYNC_LAT_CTL_EN (POSTAMBLE_RESYNC_LAT_CTL_EN)
) poa (
.phy_clk_1x (phy_clk_1x),
.poa_postamble_en_preset_2x (poa_postamble_en_preset_2x),
.postamble_clk_2x (postamble_clk_2x),
.reset_phy_clk_1x_n (reset_rdp_phy_clk_1x_n),
.reset_poa_clk_2x_n (reset_poa_clk_2x_n),
.ctl_doing_rd_beat1_1x (merged_doing_rd[0]),
.ctl_doing_rd_beat2_1x (DWIDTH_RATIO == 4 ? merged_doing_rd[MEM_IF_DQS_WIDTH] : merged_doing_rd[0]),
.seq_poa_lat_dec_1x (seq_poa_lat_dec_1x[0]),
.seq_poa_lat_inc_1x (seq_poa_lat_inc_1x[0]),
.seq_poa_protection_override_1x (seq_poa_protection_override_1x)
);
// Generate the data postamble paths (merged_doing_rd)
assign merged_doing_rd = seq_doing_rd | (ctl_doing_rd & {((DWIDTH_RATIO/2) * MEM_IF_DQS_WIDTH) {ctl_cal_success}});
assign int_rank_has_addr_swap = RANK_HAS_ADDR_SWAP[MEM_IF_CS_WIDTH - 1 : 0];
assign pll_resync_clk_index = 5;
assign pll_measure_clk_index = 7;
//
ddr2_phy_alt_mem_phy_seq_wrapper
//
seq_wrapper (
.phy_clk_1x (phy_clk_1x),
.reset_phy_clk_1x_n (reset_phy_clk_1x_n),
.ctl_cal_success (ctl_cal_success),
.ctl_cal_fail (ctl_cal_fail),
.ctl_cal_warning (ctl_cal_warning),
.ctl_cal_req (ctl_cal_req),
.int_RANK_HAS_ADDR_SWAP (int_rank_has_addr_swap),
.ctl_cal_byte_lane_sel_n (ctl_cal_byte_lane_sel_n),
.seq_pll_inc_dec_n (seq_pll_inc_dec_n),
.seq_pll_start_reconfig (seq_pll_start_reconfig),
.seq_pll_select (seq_pll_select),
.phs_shft_busy (phs_shft_busy),
.pll_resync_clk_index (pll_resync_clk_index),
.pll_measure_clk_index (pll_measure_clk_index),
.sc_clk_dp (),
.scan_enable_dqs_config (),
.scan_update (),
.scan_din (),
.scan_enable_ck (),
.scan_enable_dqs (),
.scan_enable_dqsn (),
.scan_enable_dq (),
.scan_enable_dm (),
.hr_rsc_clk (1'b0), // Halfrate resync clock not required for non-SIII style families.
.seq_ac_addr (seq_ac_addr),
.seq_ac_ba (seq_ac_ba),
.seq_ac_cas_n (seq_ac_cas_n),
.seq_ac_ras_n (seq_ac_ras_n),
.seq_ac_we_n (seq_ac_we_n),
.seq_ac_cke (seq_ac_cke),
.seq_ac_cs_n (seq_ac_cs_n),
.seq_ac_odt (seq_ac_odt),
.seq_ac_rst_n (seq_ac_rst_n),
.seq_ac_sel (seq_ac_sel),
.seq_mem_clk_disable (seq_mem_clk_disable),
.ctl_add_1t_ac_lat_internal (ctl_add_1t_ac_lat_internal),
.ctl_add_1t_odt_lat_internal (ctl_add_1t_odt_lat_internal),
.ctl_add_intermediate_regs_internal (ctl_add_intermediate_regs_internal),
.seq_rdv_doing_rd (seq_doing_rd),
.seq_rdp_reset_req_n (seq_rdp_reset_req_n),
.seq_rdp_inc_read_lat_1x (seq_rdp_inc_read_lat_1x),
.seq_rdp_dec_read_lat_1x (seq_rdp_dec_read_lat_1x),
.ctl_rdata (ctl_rdata),
.int_rdata_valid_1t (seq_rdata_valid),
.seq_rdata_valid_lat_inc (seq_rdata_valid_lat_inc),
.seq_rdata_valid_lat_dec (seq_rdata_valid_lat_dec),
.ctl_rlat (ctl_rlat),
.seq_poa_lat_dec_1x (seq_poa_lat_dec_1x),
.seq_poa_lat_inc_1x (seq_poa_lat_inc_1x),
.seq_poa_protection_override_1x (seq_poa_protection_override_1x),
.seq_oct_oct_delay (seq_oct_oct_delay),
.seq_oct_oct_extend (seq_oct_oct_extend),
.seq_oct_val (seq_oct_val),
.seq_wdp_dqs_burst (seq_wdp_dqs_burst),
.seq_wdp_wdata_valid (seq_wdp_wdata_valid),
.seq_wdp_wdata (seq_wdp_wdata),
.seq_wdp_dm (seq_wdp_dm),
.seq_wdp_dqs (seq_wdp_dqs),
.seq_wdp_ovride (seq_wdp_ovride),
.seq_dqs_add_2t_delay (seq_dqs_add_2t_delay),
.ctl_wlat (ctl_wlat),
.seq_mmc_start (seq_mmc_start),
.mmc_seq_done (mmc_seq_done),
.mmc_seq_value (mmc_seq_value),
.mem_err_out_n (1'b1),
.parity_error_n (),
.dbg_clk (dbg_clk),
.dbg_reset_n (dbg_reset_n),
.dbg_addr (dbg_addr),
.dbg_wr (dbg_wr),
.dbg_rd (dbg_rd),
.dbg_cs (dbg_cs),
.dbg_wr_data (dbg_wr_data),
.dbg_rd_data (dbg_rd_data),
.dbg_waitrequest (dbg_waitrequest)
);
// Generate rdata_valid for sequencer and control blocks
//
ddr2_phy_alt_mem_phy_rdata_valid #(
.FAMILY (FAMILY),
.MEM_IF_DQS_WIDTH (MEM_IF_DQS_WIDTH),
.RDATA_VALID_AWIDTH (5),
.RDATA_VALID_INITIAL_LAT (RDV_INITIAL_LAT),
.DWIDTH_RATIO (DWIDTH_RATIO)
) rdv_pipe (
.phy_clk_1x (phy_clk_1x),
.reset_phy_clk_1x_n (reset_rdp_phy_clk_1x_n),
.seq_rdata_valid_lat_dec (seq_rdata_valid_lat_dec),
.seq_rdata_valid_lat_inc (seq_rdata_valid_lat_inc),
.seq_doing_rd (seq_doing_rd),
.ctl_doing_rd (ctl_doing_rd),
.ctl_cal_success (ctl_cal_success),
.ctl_rdata_valid (ctl_rdata_valid),
.seq_rdata_valid (seq_rdata_valid)
);
// Instance the AII clock and reset :
//
ddr2_phy_alt_mem_phy_clk_reset #(
.CLOCK_INDEX_WIDTH (CLOCK_INDEX_WIDTH),
.DLL_EXPORT_IMPORT (DLL_EXPORT_IMPORT),
.DWIDTH_RATIO (DWIDTH_RATIO),
.LOCAL_IF_CLK_PS (LOCAL_IF_CLK_PS),
.MEM_IF_CLK_PAIR_COUNT (MEM_IF_CLK_PAIR_COUNT),
.MEM_IF_CLK_PS (MEM_IF_CLK_PS),
.MEM_IF_CLK_PS_STR (MEM_IF_CLK_PS_STR),
.MEM_IF_DWIDTH (MEM_IF_DWIDTH),
.MEM_IF_MEMTYPE (MEM_IF_MEMTYPE),
.MEM_IF_DQSN_EN (MEM_IF_DQSN_EN),
.DLL_DELAY_BUFFER_MODE (DLL_DELAY_BUFFER_MODE),
.DLL_DELAY_CHAIN_LENGTH (DLL_DELAY_CHAIN_LENGTH),
.SCAN_CLK_DIVIDE_BY (SCAN_CLK_DIVIDE_BY),
.USE_MEM_CLK_FOR_ADDR_CMD_CLK (USE_MEM_CLK_FOR_ADDR_CMD_CLK),
.DQS_DELAY_CTL_WIDTH (DQS_DELAY_CTL_WIDTH),
.INVERT_POSTAMBLE_CLK (INVERT_POSTAMBLE_CLK)
) clk (
.pll_ref_clk (pll_ref_clk),
.global_reset_n (global_reset_n),
.soft_reset_n (soft_reset_n),
.seq_rdp_reset_req_n (seq_rdp_reset_req_n),
.ac_clk_2x (ac_clk_2x),
.measure_clk_2x (measure_clk_2x),
.mem_clk_2x (mem_clk_2x),
.mem_clk (mem_clk),
.mem_clk_n (mem_clk_n),
.phy_clk_1x (phy_clk_1x_src),
.postamble_clk_2x (postamble_clk_2x),
.resync_clk_2x (resync_clk_2x),
.cs_n_clk_2x (cs_n_clk_2x),
.write_clk_2x (write_clk_2x),
.half_rate_clk (half_rate_clk),
.reset_ac_clk_2x_n (reset_ac_clk_2x_n),
.reset_measure_clk_2x_n (reset_measure_clk_2x_n),
.reset_mem_clk_2x_n (reset_mem_clk_2x_n),
.reset_phy_clk_1x_n (reset_phy_clk_1x_n),
.reset_poa_clk_2x_n (reset_poa_clk_2x_n),
.reset_resync_clk_2x_n (reset_resync_clk_2x_n),
.reset_write_clk_2x_n (reset_write_clk_2x_n),
.reset_cs_n_clk_2x_n (reset_cs_n_clk_2x_n),
.reset_rdp_phy_clk_1x_n (reset_rdp_phy_clk_1x_n),
.mem_reset_n (),
.reset_request_n (reset_request_n),
.dqs_delay_ctrl (dqs_delay_ctrl),
.phs_shft_busy (phs_shft_busy),
.seq_pll_inc_dec_n (seq_pll_inc_dec_n),
.seq_pll_select (seq_pll_select),
.seq_pll_start_reconfig (seq_pll_start_reconfig),
.mimic_data_2x (mimic_data),
.seq_clk_disable (seq_mem_clk_disable),
.ctrl_clk_disable (ctl_mem_clk_disable)
);
// Instance the mimic block :
//
ddr2_phy_alt_mem_phy_mimic #(
.NUM_MIMIC_SAMPLE_CYCLES (NUM_MIMIC_SAMPLE_CYCLES)
) mmc (
.measure_clk (measure_clk_2x),
.reset_measure_clk_n (reset_measure_clk_2x_n),
.mimic_data_in (mimic_data),
.seq_mmc_start (seq_mmc_start),
.mmc_seq_done (mmc_seq_done),
.mmc_seq_value (mmc_seq_value)
);
// If required, instance the Mimic debug block. If the debug block is used, a top level input
// for mimic_recapture_debug_data should be created.
generate
if (MIMIC_DEBUG_EN == 1)
begin : create_mimic_debug_ram
//
ddr2_phy_alt_mem_phy_mimic_debug #(
.NUM_DEBUG_SAMPLES_TO_STORE (NUM_DEBUG_SAMPLES_TO_STORE),
.PLL_STEPS_PER_CYCLE (PLL_STEPS_PER_CYCLE)
) mmc_debug (
.measure_clk (measure_clk_1x),
.reset_measure_clk_n (reset_measure_clk_1x_n),
.mmc_seq_done (mmc_seq_done),
.mmc_seq_value (mmc_seq_value),
.mimic_recapture_debug_data (1'b0)
);
end
endgenerate
endmodule
`default_nettype wire
//
`default_nettype none
`ifdef ALT_MEM_PHY_DEFINES
`else
`include "alt_mem_phy_defines.v"
`endif
//
module ddr2_phy_alt_mem_phy_ac (
clk_2x,
reset_2x_n,
phy_clk_1x,
ctl_add_1t_ac_lat,
ctl_negedge_en,
ctl_add_intermediate_regs,
period_sel,
seq_ac_sel,
ctl_ac_h,
ctl_ac_l,
seq_ac_h,
seq_ac_l,
mem_ac );
parameter POWER_UP_HIGH = 1;
parameter DWIDTH_RATIO = 4;
// NB. clk_2x could be either ac_clk_2x or cs_n_clk_2x :
input wire clk_2x;
input wire reset_2x_n;
input wire phy_clk_1x;
input wire ctl_add_1t_ac_lat;
input wire ctl_negedge_en;
input wire ctl_add_intermediate_regs;
input wire period_sel;
input wire seq_ac_sel;
input wire ctl_ac_h;
input wire ctl_ac_l;
input wire seq_ac_h;
input wire seq_ac_l;
output wire mem_ac;
(* preserve *) reg ac_h_r = POWER_UP_HIGH[0];
(* preserve *) reg ac_l_r = POWER_UP_HIGH[0];
(* preserve *) reg ac_h_2r = POWER_UP_HIGH[0];
(* preserve *) reg ac_l_2r = POWER_UP_HIGH[0];
(* preserve *) reg ac_1t = POWER_UP_HIGH[0];
(* preserve *) reg ac_2x = POWER_UP_HIGH[0];
(* preserve *) reg ac_2x_r = POWER_UP_HIGH[0];
(* preserve *) reg ac_2x_2r = POWER_UP_HIGH[0];
(* preserve *) reg ac_2x_mux = POWER_UP_HIGH[0];
reg ac_2x_retime = POWER_UP_HIGH[0];
reg ac_2x_retime_r = POWER_UP_HIGH[0];
reg ac_2x_deg_choice = POWER_UP_HIGH[0];
reg ac_h;
reg ac_l;
wire reset_2x ;
assign reset_2x = ~reset_2x_n;
generate
if (DWIDTH_RATIO == 4) //HR
begin : hr_mux_gen
// Half Rate DDR memory types require an extra cycle of latency :
always @(posedge phy_clk_1x)
begin
casez(seq_ac_sel)
1'b0 :
begin
ac_l <= ctl_ac_l;
ac_h <= ctl_ac_h;
end
1'b1 :
begin
ac_l <= seq_ac_l;
ac_h <= seq_ac_h;
end
endcase
end //always
end
else // FR
begin : fr_passthru_gen
// Note that "_h" is unused in full-rate and no latency
// is required :
always @*
begin
casez(seq_ac_sel)
1'b0 :
begin
ac_l <= ctl_ac_l;
end
1'b1 :
begin
ac_l <= seq_ac_l;
end
endcase
end
end
endgenerate
generate
if (DWIDTH_RATIO == 4)
begin : half_rate
// Initial registering of inputs :
always @(posedge phy_clk_1x)
begin
ac_h_r <= ac_h;
ac_l_r <= ac_l;
end
// Select high and low phases periodically to create the _2x signal :
always @*
begin
casez(period_sel)
1'b0 : ac_2x = ac_l_2r;
1'b1 : ac_2x = ac_h_2r;
default : ac_2x = 1'bx; // X propagaton
endcase
end
always @(posedge clk_2x)
begin
// Second stage of registering - on clk_2x
ac_h_2r <= ac_h_r;
ac_l_2r <= ac_l_r;
// 1t registering - used if ctl_add_1t_ac_lat is true
ac_1t <= ac_2x;
// AC_PHASE==270 requires an extra cycle of delay :
ac_2x_deg_choice <= ac_1t;
// If not at AC_PHASE==270, ctl_add_intermediate_regs shall be zero :
if (ctl_add_intermediate_regs == 1'b0)
begin
if (ctl_add_1t_ac_lat == 1'b1)
begin
ac_2x_r <= ac_1t;
end
else
begin
ac_2x_r <= ac_2x;
end
end
// If at AC_PHASE==270, ctl_add_intermediate_regs shall be one
// and an extra cycle delay is required :
else
begin
if (ctl_add_1t_ac_lat == 1'b1)
begin
ac_2x_r <= ac_2x_deg_choice;
end
else
begin
ac_2x_r <= ac_1t;
end
end
// Register the above output for use when ctl_negedge_en is set :
ac_2x_2r <= ac_2x_r;
end
// Determine whether to select the "_r" or "_2r" variant :
always @*
begin
casez(ctl_negedge_en)
1'b0 : ac_2x_mux = ac_2x_r;
1'b1 : ac_2x_mux = ac_2x_2r;
default : ac_2x_mux = 1'bx; // X propagaton
endcase
end
if (POWER_UP_HIGH == 1)
begin
altddio_out #(
.extend_oe_disable ("UNUSED"),
.intended_device_family ("Cyclone III"),
.lpm_hint ("UNUSED"),
.lpm_type ("altddio_out"),
.oe_reg ("UNUSED"),
.power_up_high ("ON"),
.width (1)
) addr_pin (
.aset (reset_2x),
.datain_h (ac_2x_mux),
.datain_l (ac_2x_r),
.dataout (mem_ac),
.oe (1'b1),
.outclock (clk_2x),
.outclocken (1'b1),
.aclr (),
.sset (),
.sclr (),
.oe_out ()
);
end
else
begin
altddio_out #(
.extend_oe_disable ("UNUSED"),
.intended_device_family ("Cyclone III"),
.lpm_hint ("UNUSED"),
.lpm_type ("altddio_out"),
.oe_reg ("UNUSED"),
.power_up_high ("OFF"),
.width (1)
) addr_pin (
.aclr (reset_2x),
.aset (),
.datain_h (ac_2x_mux),
.datain_l (ac_2x_r),
.dataout (mem_ac),
.oe (1'b1),
.outclock (clk_2x),
.outclocken (1'b1),
.sset (),
.sclr (),
.oe_out ()
);
end
end // Half-rate
// full-rate
else
begin : full_rate
always @(posedge phy_clk_1x)
begin
// 1t registering - only used if ctl_add_1t_ac_lat is true
ac_1t <= ac_l;
// add 1 addr_clock delay if "Add 1T" is set:
if (ctl_add_1t_ac_lat == 1'b1)
ac_2x <= ac_1t;
else
ac_2x <= ac_l;
end
always @(posedge clk_2x)
begin
ac_2x_deg_choice <= ac_2x;
end
// Note this is for 270 degree operation to align it to the correct clock phase.
always @*
begin
casez(ctl_add_intermediate_regs)
1'b0 : ac_2x_r = ac_2x;
1'b1 : ac_2x_r = ac_2x_deg_choice;
default : ac_2x_r = 1'bx; // X propagaton
endcase
end
always @(posedge clk_2x)
begin
ac_2x_2r <= ac_2x_r;
end
// Determine whether to select the "_r" or "_2r" variant :
always @*
begin
casez(ctl_negedge_en)
1'b0 : ac_2x_mux = ac_2x_r;
1'b1 : ac_2x_mux = ac_2x_2r;
default : ac_2x_mux = 1'bx; // X propagaton
endcase
end
if (POWER_UP_HIGH == 1)
begin
altddio_out #(
.extend_oe_disable ("UNUSED"),
.intended_device_family ("Cyclone III"),
.lpm_hint ("UNUSED"),
.lpm_type ("altddio_out"),
.oe_reg ("UNUSED"),
.power_up_high ("ON"),
.width (1)
) addr_pin (
.aset (reset_2x),
.datain_h (ac_2x_mux),
.datain_l (ac_2x_r),
.dataout (mem_ac),
.oe (1'b1),
.outclock (clk_2x),
.outclocken (1'b1),
.aclr (),
.sclr (),
.sset (),
.oe_out ()
);
end
else
begin
altddio_out #(
.extend_oe_disable ("UNUSED"),
.intended_device_family ("Cyclone III"),
.lpm_hint ("UNUSED"),
.lpm_type ("altddio_out"),
.oe_reg ("UNUSED"),
.power_up_high ("OFF"),
.width (1)
) addr_pin (
.aclr (reset_2x),
.datain_h (ac_2x_mux),
.datain_l (ac_2x_r),
.dataout (mem_ac),
.oe (1'b1),
.outclock (clk_2x),
.outclocken (1'b1),
.aset (),
.sclr (),
.sset (),
.oe_out ()
);
end // else: !if(POWER_UP_HIGH == 1)
end // block: full_rate
endgenerate
endmodule
`default_nettype wire
//
`default_nettype none
`ifdef ALT_MEM_PHY_DEFINES
`else
`include "alt_mem_phy_defines.v"
`endif
//
module ddr2_phy_alt_mem_phy_addr_cmd ( ac_clk_1x,
ac_clk_2x,
cs_n_clk_1x,
cs_n_clk_2x,
phy_clk_1x,
reset_ac_clk_1x_n,
reset_ac_clk_2x_n,
reset_cs_n_clk_1x_n,
reset_cs_n_clk_2x_n,
// Addr/cmd interface from controller
ctl_add_1t_ac_lat,
ctl_add_1t_odt_lat,
ctl_add_intermediate_regs,
ctl_negedge_en,
ctl_mem_addr_h,
ctl_mem_addr_l,
ctl_mem_ba_h,
ctl_mem_ba_l,
ctl_mem_cas_n_h,
ctl_mem_cas_n_l,
ctl_mem_cke_h,
ctl_mem_cke_l,
ctl_mem_cs_n_h,
ctl_mem_cs_n_l,
ctl_mem_odt_h,
ctl_mem_odt_l,
ctl_mem_ras_n_h,
ctl_mem_ras_n_l,
ctl_mem_we_n_h,
ctl_mem_we_n_l,
// DDR3 Signals
ctl_mem_rst_n_h,
ctl_mem_rst_n_l,
// Interface from Sequencer, used for calibration
// as the MRS registers need to be controlled :
seq_addr_h,
seq_addr_l,
seq_ba_h,
seq_ba_l,
seq_cas_n_h,
seq_cas_n_l,
seq_cke_h,
seq_cke_l,
seq_cs_n_h,
seq_cs_n_l,
seq_odt_h,
seq_odt_l,
seq_ras_n_h,
seq_ras_n_l,
seq_we_n_h,
seq_we_n_l,
// DDR3 Signals
seq_mem_rst_n_h,
seq_mem_rst_n_l,
seq_ac_sel,
mem_addr,
mem_ba,
mem_cas_n,
mem_cke,
mem_cs_n,
mem_odt,
mem_ras_n,
mem_we_n,
mem_rst_n
);
parameter DWIDTH_RATIO = 4;
parameter MEM_ADDR_CMD_BUS_COUNT = 1;
parameter MEM_IF_BANKADDR_WIDTH = 3;
parameter MEM_IF_CS_WIDTH = 2;
parameter MEM_IF_MEMTYPE = "DDR";
parameter MEM_IF_ROWADDR_WIDTH = 13;
input wire cs_n_clk_1x;
input wire cs_n_clk_2x;
input wire ac_clk_1x;
input wire ac_clk_2x;
input wire phy_clk_1x;
input wire reset_ac_clk_1x_n;
input wire reset_ac_clk_2x_n;
input wire reset_cs_n_clk_1x_n;
input wire reset_cs_n_clk_2x_n;
input wire [MEM_IF_ROWADDR_WIDTH -1:0] ctl_mem_addr_h;
input wire [MEM_IF_ROWADDR_WIDTH -1:0] ctl_mem_addr_l;
input wire ctl_add_1t_ac_lat;
input wire ctl_add_1t_odt_lat;
input wire ctl_negedge_en;
input wire ctl_add_intermediate_regs;
input wire [MEM_IF_BANKADDR_WIDTH - 1:0] ctl_mem_ba_h;
input wire [MEM_IF_BANKADDR_WIDTH - 1:0] ctl_mem_ba_l;
input wire ctl_mem_cas_n_h;
input wire ctl_mem_cas_n_l;
input wire [MEM_IF_CS_WIDTH - 1:0] ctl_mem_cke_h;
input wire [MEM_IF_CS_WIDTH - 1:0] ctl_mem_cke_l;
input wire [MEM_IF_CS_WIDTH - 1:0] ctl_mem_cs_n_h;
input wire [MEM_IF_CS_WIDTH - 1:0] ctl_mem_cs_n_l;
input wire [MEM_IF_CS_WIDTH - 1:0] ctl_mem_odt_h;
input wire [MEM_IF_CS_WIDTH - 1:0] ctl_mem_odt_l;
input wire ctl_mem_ras_n_h;
input wire ctl_mem_ras_n_l;
input wire ctl_mem_we_n_h;
input wire ctl_mem_we_n_l;
input wire ctl_mem_rst_n_h;
input wire ctl_mem_rst_n_l;
input wire [MEM_IF_ROWADDR_WIDTH -1:0] seq_addr_h;
input wire [MEM_IF_ROWADDR_WIDTH -1:0] seq_addr_l;
input wire [MEM_IF_BANKADDR_WIDTH - 1:0] seq_ba_h;
input wire [MEM_IF_BANKADDR_WIDTH - 1:0] seq_ba_l;
input wire seq_cas_n_h;
input wire seq_cas_n_l;
input wire [MEM_IF_CS_WIDTH - 1:0] seq_cke_h;
input wire [MEM_IF_CS_WIDTH - 1:0] seq_cke_l;
input wire [MEM_IF_CS_WIDTH - 1:0] seq_cs_n_h;
input wire [MEM_IF_CS_WIDTH - 1:0] seq_cs_n_l;
input wire [MEM_IF_CS_WIDTH - 1:0] seq_odt_h;
input wire [MEM_IF_CS_WIDTH - 1:0] seq_odt_l;
input wire seq_ras_n_h;
input wire seq_ras_n_l;
input wire seq_we_n_h;
input wire seq_we_n_l;
input wire seq_mem_rst_n_h;
input wire seq_mem_rst_n_l;
input wire seq_ac_sel;
output wire [MEM_IF_ROWADDR_WIDTH - 1 : 0] mem_addr;
output wire [MEM_IF_BANKADDR_WIDTH - 1 : 0] mem_ba;
output wire mem_cas_n;
output wire [MEM_IF_CS_WIDTH - 1 : 0] mem_cke;
output wire [MEM_IF_CS_WIDTH - 1 : 0] mem_cs_n;
output wire [MEM_IF_CS_WIDTH - 1 : 0] mem_odt;
output wire mem_ras_n;
output wire mem_we_n;
output wire mem_rst_n;
// Periodical select registers - per group of pins
reg [`ADC_NUM_PIN_GROUPS-1:0] count_addr = `ADC_NUM_PIN_GROUPS'b0;
reg [`ADC_NUM_PIN_GROUPS-1:0] count_addr_2x = `ADC_NUM_PIN_GROUPS'b0;
reg [`ADC_NUM_PIN_GROUPS-1:0] count_addr_2x_r = `ADC_NUM_PIN_GROUPS'b0;
reg [`ADC_NUM_PIN_GROUPS-1:0] period_sel_addr = `ADC_NUM_PIN_GROUPS'b0;
// Create new period select for new reset output :
reg period_sel_rst_n = 1'b0;
reg count_addr_rst_n = 1'b0;
reg count_addr_rst_n_2x = 1'b0;
reg count_addr_rst_n_2x_r = 1'b0;
generate
genvar ia;
for (ia=0; ia<`ADC_NUM_PIN_GROUPS - 1; ia=ia+1)
begin : SELECTS
always @(posedge phy_clk_1x)
begin
count_addr[ia] <= ~count_addr[ia];
end
always @(posedge ac_clk_2x)
begin
count_addr_2x[ia] <= count_addr[ia];
count_addr_2x_r[ia] <= count_addr_2x[ia];
period_sel_addr[ia] <= ~(count_addr_2x_r[ia] ^ count_addr_2x[ia]);
end
end
endgenerate
// Reset period select :
always @(posedge phy_clk_1x)
begin
count_addr_rst_n <= ~count_addr_rst_n;
end
always @(posedge ac_clk_2x)
begin
count_addr_rst_n_2x <= count_addr_rst_n ;
count_addr_rst_n_2x_r <= count_addr_rst_n_2x;
period_sel_rst_n <= ~(count_addr_rst_n_2x_r ^ count_addr_rst_n_2x );
end
//now generate cs_n period sel, off the dedicated cs_n clock :
always @(posedge phy_clk_1x)
begin
count_addr[`ADC_CS_N_PERIOD_SEL] <= ~count_addr[`ADC_CS_N_PERIOD_SEL];
end
always @(posedge cs_n_clk_2x)
begin
count_addr_2x [`ADC_CS_N_PERIOD_SEL] <= count_addr [`ADC_CS_N_PERIOD_SEL];
count_addr_2x_r[`ADC_CS_N_PERIOD_SEL] <= count_addr_2x[`ADC_CS_N_PERIOD_SEL];
period_sel_addr[`ADC_CS_N_PERIOD_SEL] <= ~(count_addr_2x_r[`ADC_CS_N_PERIOD_SEL] ^ count_addr_2x[`ADC_CS_N_PERIOD_SEL]);
end
// Create the ADDR I/O structure :
generate
genvar ib;
for (ib=0; ib<MEM_IF_ROWADDR_WIDTH; ib=ib+1)
begin : addr
//
ddr2_phy_alt_mem_phy_ac # (
.POWER_UP_HIGH (1),
.DWIDTH_RATIO (DWIDTH_RATIO)
) addr_struct (
.clk_2x (ac_clk_2x),
.reset_2x_n (1'b1),
.phy_clk_1x (phy_clk_1x),
.ctl_add_1t_ac_lat (ctl_add_1t_ac_lat),
.ctl_negedge_en (ctl_negedge_en),
.ctl_add_intermediate_regs (ctl_add_intermediate_regs),
.period_sel (period_sel_addr[`ADC_ADDR_PERIOD_SEL]),
.seq_ac_sel (seq_ac_sel),
.ctl_ac_h (ctl_mem_addr_h[ib]),
.ctl_ac_l (ctl_mem_addr_l[ib]),
.seq_ac_h (seq_addr_h[ib]),
.seq_ac_l (seq_addr_l[ib]),
.mem_ac (mem_addr[ib])
);
end
endgenerate
// Create the BANK_ADDR I/O structure :
generate
genvar ic;
for (ic=0; ic<MEM_IF_BANKADDR_WIDTH; ic=ic+1)
begin : ba
//
ddr2_phy_alt_mem_phy_ac #(
.POWER_UP_HIGH (0),
.DWIDTH_RATIO (DWIDTH_RATIO)
) ba_struct (
.clk_2x (ac_clk_2x),
.reset_2x_n (1'b1),
.phy_clk_1x (phy_clk_1x),
.ctl_add_1t_ac_lat (ctl_add_1t_ac_lat),
.ctl_negedge_en (ctl_negedge_en),
.ctl_add_intermediate_regs (ctl_add_intermediate_regs),
.period_sel (period_sel_addr[`ADC_BA_PERIOD_SEL]),
.seq_ac_sel (seq_ac_sel),
.ctl_ac_h (ctl_mem_ba_h[ic]),
.ctl_ac_l (ctl_mem_ba_l[ic]),
.seq_ac_h (seq_ba_h[ic]),
.seq_ac_l (seq_ba_l[ic]),
.mem_ac (mem_ba[ic])
);
end
endgenerate
// Create the CAS_N I/O structure :
//
ddr2_phy_alt_mem_phy_ac #(
.POWER_UP_HIGH (1),
.DWIDTH_RATIO (DWIDTH_RATIO)
) cas_n_struct (
.clk_2x (ac_clk_2x),
.reset_2x_n (1'b1),
.phy_clk_1x (phy_clk_1x),
.ctl_add_1t_ac_lat (ctl_add_1t_ac_lat),
.ctl_negedge_en (ctl_negedge_en),
.ctl_add_intermediate_regs (ctl_add_intermediate_regs),
.period_sel (period_sel_addr[`ADC_CAS_N_PERIOD_SEL]),
.seq_ac_sel (seq_ac_sel),
.ctl_ac_h (ctl_mem_cas_n_h),
.ctl_ac_l (ctl_mem_cas_n_l),
.seq_ac_h (seq_cas_n_h),
.seq_ac_l (seq_cas_n_l),
.mem_ac (mem_cas_n)
);
// Create the CKE I/O structure :
generate
genvar id;
for (id=0; id<MEM_IF_CS_WIDTH; id=id+1)
begin : cke
//
ddr2_phy_alt_mem_phy_ac # (
.POWER_UP_HIGH (0),
.DWIDTH_RATIO (DWIDTH_RATIO)
) cke_struct (
.clk_2x (ac_clk_2x),
.reset_2x_n (reset_ac_clk_2x_n),
.phy_clk_1x (phy_clk_1x),
.ctl_add_1t_ac_lat (ctl_add_1t_ac_lat),
.ctl_negedge_en (ctl_negedge_en),
.ctl_add_intermediate_regs (ctl_add_intermediate_regs),
.period_sel (period_sel_addr[`ADC_CKE_PERIOD_SEL]),
.seq_ac_sel (seq_ac_sel),
.ctl_ac_h (ctl_mem_cke_h[id]),
.ctl_ac_l (ctl_mem_cke_l[id]),
.seq_ac_h (seq_cke_h[id]),
.seq_ac_l (seq_cke_l[id]),
.mem_ac (mem_cke[id])
);
end
endgenerate
// Create the CS_N I/O structure. Note that the 2x clock is different.
generate
genvar ie;
for (ie=0; ie<MEM_IF_CS_WIDTH; ie=ie+1)
begin : cs_n
//
ddr2_phy_alt_mem_phy_ac # (
.POWER_UP_HIGH (1),
.DWIDTH_RATIO (DWIDTH_RATIO)
) cs_n_struct (
.clk_2x (cs_n_clk_2x),
.reset_2x_n (reset_ac_clk_2x_n),
.phy_clk_1x (phy_clk_1x),
.ctl_add_1t_ac_lat (ctl_add_1t_ac_lat),
.ctl_negedge_en (ctl_negedge_en),
.ctl_add_intermediate_regs (ctl_add_intermediate_regs),
.period_sel (period_sel_addr[`ADC_CS_N_PERIOD_SEL]),
.seq_ac_sel (seq_ac_sel),
.ctl_ac_h (ctl_mem_cs_n_h[ie]),
.ctl_ac_l (ctl_mem_cs_n_l[ie]),
.seq_ac_h (seq_cs_n_h[ie]),
.seq_ac_l (seq_cs_n_l[ie]),
.mem_ac (mem_cs_n[ie])
);
end
endgenerate
// Create the ODT I/O structure :
generate
genvar ig;
if (MEM_IF_MEMTYPE != "DDR")
begin : gen_odt
for (ig=0; ig<MEM_IF_CS_WIDTH; ig=ig+1)
begin : odt
//
ddr2_phy_alt_mem_phy_ac #(
.POWER_UP_HIGH (0),
.DWIDTH_RATIO (DWIDTH_RATIO)
) odt_struct (
.clk_2x (ac_clk_2x),
.reset_2x_n (1'b1),
.phy_clk_1x (phy_clk_1x),
.ctl_add_1t_ac_lat (ctl_add_1t_odt_lat),
.ctl_negedge_en (ctl_negedge_en),
.ctl_add_intermediate_regs (ctl_add_intermediate_regs),
.period_sel (period_sel_addr[`ADC_ODT_PERIOD_SEL]),
.seq_ac_sel (seq_ac_sel),
.ctl_ac_h (ctl_mem_odt_h[ig]),
.ctl_ac_l (ctl_mem_odt_l[ig]),
.seq_ac_h (seq_odt_h[ig]),
.seq_ac_l (seq_odt_l[ig]),
.mem_ac (mem_odt[ig])
);
end
end
endgenerate
// Create the RAS_N I/O structure :
//
ddr2_phy_alt_mem_phy_ac # (
.POWER_UP_HIGH (1),
.DWIDTH_RATIO (DWIDTH_RATIO)
) ras_n_struct (
.clk_2x (ac_clk_2x),
.reset_2x_n (1'b1),
.phy_clk_1x (phy_clk_1x),
.ctl_add_1t_ac_lat (ctl_add_1t_ac_lat),
.ctl_negedge_en (ctl_negedge_en),
.ctl_add_intermediate_regs (ctl_add_intermediate_regs),
.period_sel (period_sel_addr[`ADC_RAS_N_PERIOD_SEL]),
.seq_ac_sel (seq_ac_sel),
.ctl_ac_h (ctl_mem_ras_n_h),
.ctl_ac_l (ctl_mem_ras_n_l),
.seq_ac_h (seq_ras_n_h),
.seq_ac_l (seq_ras_n_l),
.mem_ac (mem_ras_n)
);
// Create the WE_N I/O structure :
//
ddr2_phy_alt_mem_phy_ac # (
.POWER_UP_HIGH (1),
.DWIDTH_RATIO (DWIDTH_RATIO)
) we_n_struct (
.clk_2x (ac_clk_2x),
.reset_2x_n (1'b1),
.phy_clk_1x (phy_clk_1x),
.ctl_add_1t_ac_lat (ctl_add_1t_ac_lat),
.ctl_negedge_en (ctl_negedge_en),
.ctl_add_intermediate_regs (ctl_add_intermediate_regs),
.period_sel (period_sel_addr[`ADC_WE_N_PERIOD_SEL]),
.seq_ac_sel (seq_ac_sel),
.ctl_ac_h (ctl_mem_we_n_h),
.ctl_ac_l (ctl_mem_we_n_l),
.seq_ac_h (seq_we_n_h),
.seq_ac_l (seq_we_n_l),
.mem_ac (mem_we_n)
);
generate
if (MEM_IF_MEMTYPE == "DDR3")
begin : ddr3_rst
// generate rst_n for DDR3
//
ddr2_phy_alt_mem_phy_ac # (
.POWER_UP_HIGH (0),
.DWIDTH_RATIO (DWIDTH_RATIO)
)ddr3_rst_struct (
.clk_2x (ac_clk_2x),
.reset_2x_n (reset_ac_clk_2x_n),
.phy_clk_1x (phy_clk_1x),
.ctl_add_1t_ac_lat (ctl_add_1t_ac_lat),
.ctl_negedge_en (ctl_negedge_en),
.ctl_add_intermediate_regs (ctl_add_intermediate_regs),
.period_sel (period_sel_rst_n),
.seq_ac_sel (seq_ac_sel),
.ctl_ac_h (ctl_mem_rst_n_h),
.ctl_ac_l (ctl_mem_rst_n_l),
.seq_ac_h (seq_mem_rst_n_h),
.seq_ac_l (seq_mem_rst_n_l),
.mem_ac (mem_rst_n)
);
end
else
begin : no_ddr3_rst
assign mem_rst_n = 1'b1;
end
endgenerate
endmodule
`default_nettype wire
/* Legal Notice: (C)2006 Altera Corporation. All rights reserved. Your
use of Altera Corporation's design tools, logic functions and other
software and tools, and its AMPP partner logic functions, and any
output files any of the foregoing (including device programming or
simulation files), and any associated documentation or information are
expressly subject to the terms and conditions of the Altera Program
License Subscription Agreement or other applicable license agreement,
including, without limitation, that your use is for the sole purpose
of programming logic devices manufactured by Altera and sold by Altera
or its authorized distributors. Please refer to the applicable
agreement for further details. */
/*////////////////////////////////////////////////////////////////////////////-
Title : Datapath IO elements
File: $RCSfile : alt_mem_phy_dp_io.v,v $
Last Modified : $Date: 2010/04/12 $
Revision : $Revision: #1 $
Abstract : NewPhy Datapath IO atoms. This block shall connect to both
the read and write datapath blocks, abstracting the I/O
elements from the remainder of the circuit. This file
uses the ALTDQ_DQS WYSIWYG which is configurable to be either
of type DQ, DQS or DQSN and just requires connecting to the
relevant IO buffers (ALTIOBUF) to create the full IO required
for DDR.
////////////////////////////////////////////////////////////////////////////-*/
`include "alt_mem_phy_defines.v"
//
module ddr2_phy_alt_mem_phy_dp_io (
reset_write_clk_2x_n,
resync_clk_2x,
postamble_clk_2x,
mem_clk_2x,
write_clk_2x,
dqs_delay_ctrl,
mem_dm,
mem_dq,
mem_dqs,
mem_dqsn,
dio_rdata_h_2x,
dio_rdata_l_2x,
poa_postamble_en_preset_2x,
wdp_dm_h_2x,
wdp_dm_l_2x,
wdp_wdata_h_2x,
wdp_wdata_l_2x,
wdp_wdata_oe_2x,
wdp_wdqs_2x,
wdp_wdqs_oe_2x
);
parameter MEM_IF_DWIDTH = 64;
parameter MEM_IF_DM_PINS_EN = 1;
parameter MEM_IF_DM_WIDTH = 8;
parameter MEM_IF_DQ_PER_DQS = 8;
parameter MEM_IF_DQS_WIDTH = 8;
parameter MEM_IF_MEMTYPE = "DDR";
parameter MEM_IF_DQSN_EN = 1;
parameter MEM_IF_POSTAMBLE_EN_WIDTH = 8;
parameter DQS_DELAY_CTL_WIDTH = 6;
input wire reset_write_clk_2x_n;
input wire resync_clk_2x;
input wire postamble_clk_2x;
input wire mem_clk_2x;
input wire write_clk_2x;
input wire [DQS_DELAY_CTL_WIDTH - 1 : 0 ] dqs_delay_ctrl;
output wire [MEM_IF_DM_WIDTH - 1 : 0] mem_dm;
inout wire [MEM_IF_DWIDTH - 1 : 0] mem_dq;
inout wire [MEM_IF_DQS_WIDTH - 1 : 0] mem_dqs;
inout wire [MEM_IF_DQS_WIDTH - 1 : 0] mem_dqsn;
output reg [MEM_IF_DWIDTH - 1 : 0] dio_rdata_h_2x;
output reg [MEM_IF_DWIDTH - 1 : 0] dio_rdata_l_2x;
input wire [MEM_IF_POSTAMBLE_EN_WIDTH - 1 : 0] poa_postamble_en_preset_2x;
input wire [MEM_IF_DM_WIDTH -1 : 0] wdp_dm_h_2x;
input wire [MEM_IF_DM_WIDTH -1 : 0] wdp_dm_l_2x;
input wire [MEM_IF_DWIDTH - 1 : 0] wdp_wdata_h_2x;
input wire [MEM_IF_DWIDTH - 1 : 0] wdp_wdata_l_2x;
input wire [MEM_IF_DWIDTH - 1 : 0] wdp_wdata_oe_2x;
input wire [MEM_IF_DQS_WIDTH - 1 : 0] wdp_wdqs_2x;
input wire [MEM_IF_DQS_WIDTH - 1 : 0] wdp_wdqs_oe_2x;
wire [MEM_IF_DWIDTH - 1 : 0] wdp_wdata_oe_2x_r;
wire [MEM_IF_DWIDTH - 1 : 0] rdata_n_captured;
wire [MEM_IF_DWIDTH - 1 : 0] rdata_p_captured;
wire [(MEM_IF_DQS_WIDTH) - 1 : 0] wdp_wdqs_oe_2x_r;
wire [(MEM_IF_DQS_WIDTH) - 1 : 0] wdp_wdqsn_oe_2x_r;
// The power-on high values are required to match those within ALTDQ_DQS, not for any functional reason :
(* preserve *) reg [MEM_IF_DWIDTH - 1 : 0] rdata_n_ams = {MEM_IF_DWIDTH{1'b1}};
(* preserve *) reg [MEM_IF_DWIDTH - 1 : 0] rdata_p_ams = {MEM_IF_DWIDTH{1'b1}};
wire reset_write_clk_2x;
wire [MEM_IF_DWIDTH - 1 : 0] dq_ddio_dataout;
wire [MEM_IF_DWIDTH - 1 : 0] dq_datain;
wire [MEM_IF_DWIDTH - 1 : 0] dm_ddio_dataout;
wire [MEM_IF_DQS_WIDTH - 1 : 0] dqs_ddio_dataout;
wire [MEM_IF_DM_WIDTH - 1 : 0] dm_ddio_oe;
wire [MEM_IF_DQS_WIDTH - 1 : 0] dqs_buffered;
wire [(MEM_IF_DQS_WIDTH) - 1 : 0] dqs_pseudo_diff_out;
wire [(MEM_IF_DQS_WIDTH) - 1 : 0] dqsn_pseudo_diff_out;
// Create non-inverted reset for pads :
assign reset_write_clk_2x = ~reset_write_clk_2x_n;
// Read datapath functionality :
// synchronise to the resync_clk_2x_domain
always @(posedge resync_clk_2x)
begin : capture_regs
// Resynchronise :
// The comparison to 'X' is performed to prevent X's being captured in non-DQS mode
// and propagating into the sequencer's control logic. This can only occur when a Verilog SIMGEN
// model of the sequencer is being used :
if (|rdata_p_captured === 1'bX)
rdata_p_ams <= {MEM_IF_DWIDTH{1'b0}};
else
rdata_p_ams <= rdata_p_captured; // 'captured' is from the IOEs
if (|rdata_n_captured === 1'bX)
rdata_n_ams <= {MEM_IF_DWIDTH{1'b0}};
else
rdata_n_ams <= rdata_n_captured; // 'captured' is from the IOEs
// Output registers :
dio_rdata_h_2x <= rdata_p_ams;
dio_rdata_l_2x <= rdata_n_ams;
end
// DQ pins and their logic
generate
genvar i,j;
// First generate each DQS group :
for (i=0; i<MEM_IF_DQS_WIDTH ; i=i+1)
begin : dqs_group
// ALTDQ_DQS instances all WYSIWYGs for the DQ, DM and DQS/DQSN pins for a group :
//
ddr2_phy_alt_mem_phy_dq_dqs dq_dqs (
// DQ pin connections :
.bidir_dq_areset({MEM_IF_DQ_PER_DQS{reset_write_clk_2x}}),
.bidir_dq_input_data_in(dq_datain[ (i+1)*MEM_IF_DQ_PER_DQS - 1 : i*MEM_IF_DQ_PER_DQS] ), // From ibuf
.bidir_dq_input_data_out_high(rdata_n_captured[ (i+1)*MEM_IF_DQ_PER_DQS - 1 : i*MEM_IF_DQ_PER_DQS]),
.bidir_dq_input_data_out_low(rdata_p_captured[ (i+1)*MEM_IF_DQ_PER_DQS - 1 : i*MEM_IF_DQ_PER_DQS]),
.bidir_dq_oe_in(wdp_wdata_oe_2x[ (i+1)*MEM_IF_DQ_PER_DQS - 1 : i*MEM_IF_DQ_PER_DQS]),
.bidir_dq_oe_out(wdp_wdata_oe_2x_r[ (i+1)*MEM_IF_DQ_PER_DQS - 1 : i*MEM_IF_DQ_PER_DQS]),
.bidir_dq_output_data_in_high(wdp_wdata_h_2x[ (i+1)*MEM_IF_DQ_PER_DQS - 1 : i*MEM_IF_DQ_PER_DQS]),
.bidir_dq_output_data_in_low(wdp_wdata_l_2x[ (i+1)*MEM_IF_DQ_PER_DQS - 1 : i*MEM_IF_DQ_PER_DQS]),
.bidir_dq_output_data_out(dq_ddio_dataout[ (i+1)*MEM_IF_DQ_PER_DQS - 1 : i*MEM_IF_DQ_PER_DQS]), // To obuf
// Misc connections :
.dll_delayctrlin(dqs_delay_ctrl), // From DLL
.dq_input_reg_clk(dqs_buffered[i]),
.dq_output_reg_clk(write_clk_2x),
// DQS/DQSN connections :
.dqs_enable_ctrl_in(poa_postamble_en_preset_2x[i]),
.dqs_enable_ctrl_clk(postamble_clk_2x),
//NB. Inverted via dq_input_reg_clk_source=INVERTED_DQS_BUS param in ALTDQ_DQS clearbox config file :
.dqs_input_data_in(dqs_buffered[i]),
.dqs_oe_in(wdp_wdqs_oe_2x[i]),
.dqs_oe_out(wdp_wdqs_oe_2x_r[i]),
.dqs_output_data_in_high(wdp_wdqs_2x[i]), // DQS Output. From the write datapath
.dqs_output_data_in_low(1'b0),
.dqs_output_data_out(dqs_ddio_dataout[i]),
.dqs_output_reg_clk(mem_clk_2x),
.dqsn_oe_in(wdp_wdqs_oe_2x[i]), // Just use DQS OE to drive DQSN OE also
.dqsn_oe_out(wdp_wdqsn_oe_2x_r[i]),
//DM pins are implemented using unidirection DQ pins :
.output_dq_oe_in(1'b1),
.output_dq_oe_out(dm_ddio_oe[i]),
.output_dq_output_data_in_high(wdp_dm_h_2x[i]),
.output_dq_output_data_in_low(wdp_dm_l_2x[i]),
.output_dq_output_data_out(dm_ddio_dataout[i]) // To obuf
);
// For DDR, or DDR2 where DQSN is disabled, it is important to leave the DQSN
// pad unconnected, as otherwise this path remains in the netlist even
// though there is no intent to use DQSN, and it is unused as an output :
if (MEM_IF_MEMTYPE == "DDR" || (MEM_IF_MEMTYPE == "DDR2" && (MEM_IF_DQSN_EN == 0)) )
begin : ddr_no_dqsn_ibuf_gen
// Input buf
arriaii_io_ibuf dqs_inpt_ibuf(
.i (mem_dqs[i]),
.ibar (),
.o (dqs_buffered[i])
);
// The DQS Output buffer itself :
// OE input is active HIGH
arriaii_io_obuf dqs_obuf (
.i(dqs_ddio_dataout[i]),
.oe(wdp_wdqs_oe_2x_r[i]),
.seriesterminationcontrol(),
.devoe(),
.o(mem_dqs[i]),
.obar()
);
assign mem_dqsn[i] = 1'b0;
end
// DDR2 (with DQSN enabled) has true differential DQS inputs :
else
begin : ddr2_with_dqsn_buf_gen
// Input buffer now has DQSN input connection too :
arriaii_io_ibuf dqs_inpt_ibuf(
.i (mem_dqs[i]),
.ibar (mem_dqsn[i]),
.o (dqs_buffered[i])
);
// Need to create the DQSN output buffer, which requires the use of the
// Pseudo-diff atom :
arriaii_pseudo_diff_out dqs_pdiff_out (
.i (dqs_ddio_dataout[i]),
.o (dqs_pseudo_diff_out[i]),
.obar (dqsn_pseudo_diff_out[i])
);
// The DQS Output buffer itself, driven from 'O' output of pseudo-diff atom :
// OE input is active HIGH
arriaii_io_obuf dqs_obuf (
.i(dqs_pseudo_diff_out[i]),
.oe(wdp_wdqs_oe_2x_r[i]),
.seriesterminationcontrol(),
.devoe(),
.o(mem_dqs[i]),
.obar()
);
// The DQSN Output buffer itself, driven from 'OBAR' output of pseudo-diff atom :
// OE input is active HIGH
arriaii_io_obuf dqsn_obuf (
.i(dqsn_pseudo_diff_out[i]),
.oe(wdp_wdqsn_oe_2x_r[i]),
.seriesterminationcontrol(),
.devoe(),
.o(mem_dqsn[i]),
.obar()
);
end
// Then generate DQ pins for each group :
for (j=0; j<MEM_IF_DQ_PER_DQS ; j=j+1)
begin : dq
// The DQ buffer (output side) :
arriaii_io_obuf dq_obuf (
.i(dq_ddio_dataout[j+(i*MEM_IF_DQ_PER_DQS)]),
.oe(wdp_wdata_oe_2x_r[j+(i*MEM_IF_DQ_PER_DQS)]),
.seriesterminationcontrol(),
.devoe(),
.o(mem_dq[j+(i*MEM_IF_DQ_PER_DQS)]), //pad
.obar()
);
// The DQ buffer (input side) :
arriaii_io_ibuf # (
.simulate_z_as("gnd")
) dq_ibuf (
.i(mem_dq[j+(i*MEM_IF_DQ_PER_DQS)]),//pad
.ibar(),
.o(dq_datain[j+(i*MEM_IF_DQ_PER_DQS)])
);
end
// The DM buffer (output only) :
// DM Pin - if required :
if (MEM_IF_DM_PINS_EN)
begin : gen_dm
arriaii_io_obuf dm_obuf (
.i(dm_ddio_dataout[i]),
.oe(dm_ddio_oe[i]),
.seriesterminationcontrol(),
.devoe(),
.o(mem_dm[i]), //pad
.obar()
);
end
end
endgenerate
endmodule
//
`ifdef ALT_MEM_PHY_DEFINES
`else
`include "alt_mem_phy_defines.v"
`endif
// ArriaII Clock/Reset block
//
module ddr2_phy_alt_mem_phy_clk_reset (
pll_ref_clk,
global_reset_n,
soft_reset_n,
seq_rdp_reset_req_n,
ac_clk_2x,
measure_clk_2x,
mem_clk_2x,
mem_clk,
mem_clk_n,
phy_clk_1x,
postamble_clk_2x,
resync_clk_2x,
cs_n_clk_2x,
write_clk_2x,
half_rate_clk,
reset_ac_clk_2x_n,
reset_measure_clk_2x_n,
reset_mem_clk_2x_n,
reset_phy_clk_1x_n,
reset_poa_clk_2x_n,
reset_resync_clk_2x_n,
reset_write_clk_2x_n,
reset_cs_n_clk_2x_n,
reset_rdp_phy_clk_1x_n,
mem_reset_n,
reset_request_n, // new output
dqs_delay_ctrl,
phs_shft_busy,
seq_pll_inc_dec_n,
seq_pll_select,
seq_pll_start_reconfig,
mimic_data_2x,
seq_clk_disable,
ctrl_clk_disable
) /* synthesis altera_attribute="disable_da_rule=\"R101,C104,C106\"" */;
parameter CLOCK_INDEX_WIDTH = 3;
parameter DLL_EXPORT_IMPORT = "NONE";
parameter DWIDTH_RATIO = 4;
parameter LOCAL_IF_CLK_PS = 4000;
parameter MEM_IF_CLK_PAIR_COUNT = 3;
parameter MEM_IF_CLK_PS = 4000;
parameter MEM_IF_CLK_PS_STR = "4000 ps";
parameter MEM_IF_DWIDTH = 64;
parameter MEM_IF_MEMTYPE = "DDR";
parameter MEM_IF_DQSN_EN = 1;
parameter DLL_DELAY_BUFFER_MODE = "HIGH";
parameter DLL_DELAY_CHAIN_LENGTH = 8;
parameter SCAN_CLK_DIVIDE_BY = 2;
parameter USE_MEM_CLK_FOR_ADDR_CMD_CLK = 1;
parameter DQS_DELAY_CTL_WIDTH = 6;
parameter INVERT_POSTAMBLE_CLK = "false";
// Clock/reset inputs :
input global_reset_n;
input wire soft_reset_n;
input wire pll_ref_clk;
input wire seq_rdp_reset_req_n;
// Clock/reset outputs :
output ac_clk_2x;
output measure_clk_2x;
output mem_clk_2x;
inout [MEM_IF_CLK_PAIR_COUNT - 1 : 0] mem_clk;
inout [MEM_IF_CLK_PAIR_COUNT - 1 : 0] mem_clk_n;
output phy_clk_1x;
output postamble_clk_2x;
output resync_clk_2x;
output cs_n_clk_2x;
output write_clk_2x;
output wire half_rate_clk;
output wire reset_ac_clk_2x_n;
output wire reset_measure_clk_2x_n;
output wire reset_mem_clk_2x_n;
(*preserve*) (* altera_attribute = "-name global_signal off" *) output reg reset_phy_clk_1x_n;
output wire reset_poa_clk_2x_n;
output wire reset_resync_clk_2x_n;
output wire reset_write_clk_2x_n;
output wire reset_cs_n_clk_2x_n;
output wire reset_rdp_phy_clk_1x_n;
output wire mem_reset_n;
// This is the PLL locked signal :
output wire reset_request_n;
// Misc I/O :
output wire [DQS_DELAY_CTL_WIDTH - 1 : 0 ] dqs_delay_ctrl;
output wire phs_shft_busy;
input wire seq_pll_inc_dec_n;
input wire [CLOCK_INDEX_WIDTH - 1 : 0 ] seq_pll_select;
input wire seq_pll_start_reconfig;
output wire mimic_data_2x;
input wire seq_clk_disable;
input wire [MEM_IF_CLK_PAIR_COUNT - 1 : 0] ctrl_clk_disable;
// No attributes are applied to the clk/reset wires, as the fitter should be able to
// allocate GCLK/QCLK routing resources appropriately. For specific GCLk/QCLK requirements
// this HDL may be edited using the following syntax :
// (* keep, altera_attribute = "-name global_signal dual_regional_clock" *) wire resync_clk_2x;
wire global_reset_n;
reg scan_clk = 1'b0;
wire mem_clk_2x;
wire phy_clk_1x;
wire postamble_clk_2x;
wire resync_clk_2x;
wire write_clk_2x;
wire cs_n_clk_2x;
wire ac_clk_2x;
wire measure_clk_2x;
wire phy_internal_reset_n;
wire [MEM_IF_CLK_PAIR_COUNT - 1 : 0] mem_clk;
wire [MEM_IF_CLK_PAIR_COUNT - 1 : 0] mem_clk_n;
reg [2:0] divider = 3'h0;
(*preserve*) reg seq_pll_start_reconfig_ams;
(*preserve*) reg seq_pll_start_reconfig_r;
(*preserve*) reg seq_pll_start_reconfig_2r;
(*preserve*) reg seq_pll_start_reconfig_3r;
reg pll_new_dir;
reg [CLOCK_INDEX_WIDTH - 1 : 0 ] pll_new_phase;
wire pll_phase_auto_calibrate_pulse;
(*preserve*) reg pll_reprogram_request;
wire pll_locked_src;
reg pll_locked;
(*preserve*) reg pll_reprogram_request_pulse; // 1 scan clk cycle long
(*preserve*) reg pll_reprogram_request_pulse_r;
(*preserve*) reg pll_reprogram_request_pulse_2r;
wire pll_reprogram_request_long_pulse; // 3 scan clk cycles long
(*preserve*) reg reset_master_ams;
wire [MEM_IF_CLK_PAIR_COUNT - 1 : 0] mem_clk_pdiff_in;
wire [MEM_IF_CLK_PAIR_COUNT - 1 : 0] mem_clk_buf_in;
wire [MEM_IF_CLK_PAIR_COUNT - 1 : 0] mem_clk_n_buf_in;
wire pll_phase_done;
reg phs_shft_busy_siii;
(*preserve*) reg [2:0] seq_pll_start_reconfig_ccd_pipe;
(*preserve*) reg seq_pll_inc_dec_ccd;
(*preserve*) reg [CLOCK_INDEX_WIDTH - 1 : 0] seq_pll_select_ccd ;
(*preserve*) reg global_pre_clear;
wire global_or_soft_reset_n;
(*preserve*) reg clk_div_reset_ams_n = 1'b0;
(*preserve*) reg clk_div_reset_ams_n_r = 1'b0;
(*preserve*) reg pll_reconfig_reset_ams_n = 1'b0;
(*preserve*) reg pll_reconfig_reset_ams_n_r = 1'b0;
wire clk_divider_reset_n;
wire [MEM_IF_CLK_PAIR_COUNT - 1 : 0] mimic_data_2x_internal;
wire pll_reset;
wire fb_clk;
wire pll_reconfig_reset_n;
genvar dqs_group;
// Output the PLL locked signal to be used as a reset_request_n - IE. reset when the PLL loses
// lock :
assign reset_request_n = pll_locked;
// Reset the scanclk clock divider if we either have a global_reset or the PLL loses lock
assign pll_reconfig_reset_n = global_reset_n && pll_locked;
// Clock divider circuit reset generation.
always @(posedge phy_clk_1x or negedge pll_reconfig_reset_n)
begin
if (pll_reconfig_reset_n == 1'b0)
begin
clk_div_reset_ams_n <= 1'b0;
clk_div_reset_ams_n_r <= 1'b0;
end
else
begin
clk_div_reset_ams_n <= 1'b1;
clk_div_reset_ams_n_r <= clk_div_reset_ams_n;
end
end
// PLL reconfig and synchronisation circuit reset generation.
always @(posedge scan_clk or negedge pll_reconfig_reset_n)
begin
if (pll_reconfig_reset_n == 1'b0)
begin
pll_reconfig_reset_ams_n <= 1'b0;
pll_reconfig_reset_ams_n_r <= 1'b0;
end
else
begin
pll_reconfig_reset_ams_n <= 1'b1;
pll_reconfig_reset_ams_n_r <= pll_reconfig_reset_ams_n;
end
end
// Create the scan clock. Used for PLL reconfiguring in this block.
// Clock divider reset is the direct output of the AMS flops :
assign clk_divider_reset_n = clk_div_reset_ams_n_r;
generate
if (SCAN_CLK_DIVIDE_BY == 1)
begin : no_scan_clk_divider
always @(phy_clk_1x)
begin
scan_clk = phy_clk_1x;
end
end
else
begin : gen_scan_clk
always @(posedge phy_clk_1x or negedge clk_divider_reset_n)
begin
if (clk_divider_reset_n == 1'b0)
begin
scan_clk <= 1'b0;
divider <= 3'h0;
end
else
begin
// This method of clock division does not require "divider" to be used
// as an intermediate clock:
if (divider == (SCAN_CLK_DIVIDE_BY / 2 - 1))
begin
scan_clk <= ~scan_clk; // Toggle
divider <= 3'h0;
end
else
begin
scan_clk <= scan_clk; // Do not toggle
divider <= divider + 3'h1;
end
end
end
end
endgenerate
function [3:0] lookup_aii;
input [CLOCK_INDEX_WIDTH-1:0] seq_num;
begin
casez (seq_num)
4'b0000 : lookup_aii = 4'b0010; // Legal code
4'b0001 : lookup_aii = 4'b0011; // Legal code
4'b0010 : lookup_aii = 4'b1111; // illegal - return code 4'b1111
4'b0011 : lookup_aii = 4'b0101; // Legal code
4'b0100 : lookup_aii = 4'b1111; // illegal - return code 4'b1111
4'b0101 : lookup_aii = 4'b0110; // Legal code
4'b0110 : lookup_aii = 4'b1000; // Legal code
4'b0111 : lookup_aii = 4'b0111; // Legal code
4'b1000 : lookup_aii = 4'b0100; // Legal code
4'b1001 : lookup_aii = 4'b1111; // illegal - return code 4'b1111
4'b1010 : lookup_aii = 4'b1111; // illegal - return code 4'b1111
4'b1011 : lookup_aii = 4'b1111; // illegal - return code 4'b1111
4'b1100 : lookup_aii = 4'b1111; // illegal - return code 4'b1111
4'b1101 : lookup_aii = 4'b1111; // illegal - return code 4'b1111
4'b1110 : lookup_aii = 4'b1111; // illegal - return code 4'b1111
4'b1111 : lookup_aii = 4'b1111; // illegal - return code 4'b1111
default : lookup_aii = 4'bxxxx; // X propagation
endcase
end
endfunction
always @(posedge phy_clk_1x or negedge reset_phy_clk_1x_n)
begin
if (reset_phy_clk_1x_n == 1'b0)
begin
seq_pll_inc_dec_ccd <= 1'b0;
seq_pll_select_ccd <= {CLOCK_INDEX_WIDTH{1'b0}};
seq_pll_start_reconfig_ccd_pipe <= 3'b000;
end
// Generate 'ccd' Cross Clock Domain signals :
else
begin
seq_pll_start_reconfig_ccd_pipe <= {seq_pll_start_reconfig_ccd_pipe[1:0], seq_pll_start_reconfig};
if (seq_pll_start_reconfig == 1'b1 && seq_pll_start_reconfig_ccd_pipe[0] == 1'b0)
begin
seq_pll_inc_dec_ccd <= seq_pll_inc_dec_n;
seq_pll_select_ccd <= seq_pll_select;
end
end
end
always @(posedge scan_clk or negedge pll_reconfig_reset_ams_n_r)
begin
if (pll_reconfig_reset_ams_n_r == 1'b0)
begin
seq_pll_start_reconfig_ams <= 1'b0;
seq_pll_start_reconfig_r <= 1'b0;
seq_pll_start_reconfig_2r <= 1'b0;
seq_pll_start_reconfig_3r <= 1'b0;
pll_reprogram_request_pulse <= 1'b0;
pll_reprogram_request_pulse_r <= 1'b0;
pll_reprogram_request_pulse_2r <= 1'b0;
pll_reprogram_request <= 1'b0;
end
else
begin
seq_pll_start_reconfig_ams <= seq_pll_start_reconfig_ccd_pipe[2];
seq_pll_start_reconfig_r <= seq_pll_start_reconfig_ams;
seq_pll_start_reconfig_2r <= seq_pll_start_reconfig_r;
seq_pll_start_reconfig_3r <= seq_pll_start_reconfig_2r;
pll_reprogram_request_pulse <= pll_phase_auto_calibrate_pulse;
pll_reprogram_request_pulse_r <= pll_reprogram_request_pulse;
pll_reprogram_request_pulse_2r <= pll_reprogram_request_pulse_r;
pll_reprogram_request <= pll_reprogram_request_long_pulse;
end
end
// Rising-edge detect to generate a single phase shift step
assign pll_phase_auto_calibrate_pulse = ~seq_pll_start_reconfig_3r && seq_pll_start_reconfig_2r;
// extend the phase shift request pulse to be 3 scan clk cycles long.
assign pll_reprogram_request_long_pulse = pll_reprogram_request_pulse || pll_reprogram_request_pulse_r || pll_reprogram_request_pulse_2r;
// Register the Phase step settings
always @(posedge scan_clk or negedge pll_reconfig_reset_ams_n_r)
begin
if (pll_reconfig_reset_ams_n_r == 1'b0)
begin
pll_new_dir <= 1'b0;
pll_new_phase <= 'h0;
end
else
begin
if (pll_phase_auto_calibrate_pulse)
begin
pll_new_dir <= seq_pll_inc_dec_ccd;
pll_new_phase <= seq_pll_select_ccd;
end
end
end
// generate the busy signal - just the inverse of the done o/p from the pll, and stretched ,
//as the initial pulse might not be long enough to be catched by the sequencer
//the same circuitry in the ciii clock and reset block
always @(posedge scan_clk or negedge pll_reconfig_reset_ams_n_r)
begin
if (pll_reconfig_reset_ams_n_r == 1'b0)
phs_shft_busy_siii <= 1'b0;
else
phs_shft_busy_siii <= pll_reprogram_request || ~pll_phase_done;
end
assign phs_shft_busy = phs_shft_busy_siii;
// Gate the soft reset input (from SOPC builder for example) with the PLL
// locked signal :
assign global_or_soft_reset_n = soft_reset_n && global_reset_n;
// Create the PHY internal reset signal :
assign phy_internal_reset_n = pll_locked && global_or_soft_reset_n;
// The PLL resets only on a global reset :
assign pll_reset = !global_reset_n;
generate
// Half-rate mode :
if (DWIDTH_RATIO == 4)
begin : half_rate
//
ddr2_phy_alt_mem_phy_pll pll (
.inclk0 (pll_ref_clk),
.areset (pll_reset),
.c0 (phy_clk_1x),
.c1 (mem_clk_2x),
.c2 (), //unused
.c3 (write_clk_2x),
.c4 (resync_clk_2x),
.c5 (measure_clk_2x),
.phasecounterselect (lookup_aii(pll_new_phase)),
.phasestep (pll_reprogram_request),
.phaseupdown (pll_new_dir),
.scanclk (scan_clk),
.locked (pll_locked_src),
.phasedone (pll_phase_done)
);
assign half_rate_clk = phy_clk_1x;
end
// Full-rate mode :
else
begin : full_rate
//
ddr2_phy_alt_mem_phy_pll pll (
.inclk0 (pll_ref_clk),
.areset (pll_reset),
.c0 (half_rate_clk),
.c1 (mem_clk_2x),
.c2 (), //unused
.c3 (write_clk_2x),
.c4 (resync_clk_2x),
.c5 (measure_clk_2x),
.phasecounterselect (lookup_aii(pll_new_phase)),
.phasestep (pll_reprogram_request),
.phaseupdown (pll_new_dir),
.scanclk (scan_clk),
.locked (pll_locked_src),
.phasedone (pll_phase_done)
);
// NB. phy_clk_1x is now full-rate, despite the "1x" naming convention :
assign phy_clk_1x = mem_clk_2x;
end
endgenerate
//synopsys translate_off
reg [19:0] pll_locked_chain = 20'h0;
always @(posedge pll_ref_clk)
begin
pll_locked_chain <= {pll_locked_chain[18:0],pll_locked_src};
end
//synopsys translate_on
always @*
begin
pll_locked = pll_locked_src;
//synopsys translate_off
pll_locked = pll_locked_chain[19];
//synopsys translate_on
end
// The postamble clock can be the inverse of the resync clock
assign postamble_clk_2x = (INVERT_POSTAMBLE_CLK == "true") ? ~resync_clk_2x : resync_clk_2x;
generate
if (USE_MEM_CLK_FOR_ADDR_CMD_CLK == 1)
begin
assign ac_clk_2x = mem_clk_2x;
assign cs_n_clk_2x = mem_clk_2x;
end
else
begin
assign ac_clk_2x = write_clk_2x;
assign cs_n_clk_2x = write_clk_2x;
end
endgenerate
generate
genvar clk_pair;
for (clk_pair = 0 ; clk_pair < MEM_IF_CLK_PAIR_COUNT; clk_pair = clk_pair + 1)
begin : DDR_CLK_OUT
arriaii_ddio_out # (
.half_rate_mode("false"),
.sync_mode("clear"), // for mem clk disable
.use_new_clocking_model("true")
) mem_clk_ddio (
.datainlo (1'b0),
.datainhi (1'b1),
.clkhi (mem_clk_2x),
.clklo (mem_clk_2x),
//synthesis translate_off
.clk (),
//synthesis translate_on
.muxsel (mem_clk_2x),
.ena (1'b1),
.areset (1'b0),
.sreset (1'b0),/////seq_clk_disable || ctrl_clk_disable[clk_pair]
.dataout (mem_clk_pdiff_in[clk_pair]),
.dfflo (),
.dffhi (),
.devpor (),
.devclrn ()
);
// Pseudo-diff used to ensure fanout of 1 from OPA/DDIO_OUT atoms :
arriaii_pseudo_diff_out mem_clk_pdiff (
.i (mem_clk_pdiff_in[clk_pair]),
.o ( mem_clk_buf_in[clk_pair]),
.obar (mem_clk_n_buf_in[clk_pair])
);
// The same output buf is for both DDR2 and 3 :
arriaii_io_obuf # (
.bus_hold("false"),
.open_drain_output("false")
) mem_clk_obuf (
.i (mem_clk_buf_in[clk_pair]),
.oe (1'b1),
// synopsys translate_off
.seriesterminationcontrol(),
.obar(),
// synopsys translate_on
.o(mem_clk[clk_pair]),
.devoe()
);
// The same output buf is used
arriaii_io_obuf # (
.bus_hold("false"),
.open_drain_output("false")
) mem_clk_n_obuf (
.i (mem_clk_n_buf_in[clk_pair]),
.oe (1'b1),
// synopsys translate_off
.seriesterminationcontrol(),
.obar(),
// synopsys translate_on
.o(mem_clk_n[clk_pair]),
.devoe()
);
end //for
endgenerate
// Mimic path uses single-ended buffer, as this is the SII scheme :
arriaii_io_ibuf fb_clk_ibuf(
.i (mem_clk[0]),
// synopsys translate_off
.ibar(),
// synopsys translate_on
.o (fb_clk)
);
// DDR2 Mimic Path Generation - in effect this is just a register :
arriaii_ddio_in ddio_mimic(
.datain (fb_clk),
.clk (measure_clk_2x),
.clkn (),
// synopsys translate_off
.devclrn(),
.devpor(),
// synopsys translate_on
.ena (1'b1),
.areset (1'b0),
.sreset (1'b0),
.regoutlo (),
.regouthi (mimic_data_2x),
.dfflo ()
);
generate
if (DLL_EXPORT_IMPORT != "IMPORT")
begin
arriaii_dll # (
.input_frequency (MEM_IF_CLK_PS_STR),
.delay_buffer_mode (DLL_DELAY_BUFFER_MODE),
.delay_chain_length (DLL_DELAY_CHAIN_LENGTH),
.delayctrlout_mode ("normal"),
.jitter_reduction ("true"),
.sim_valid_lock (1280),
.sim_low_buffer_intrinsic_delay (350),
.sim_high_buffer_intrinsic_delay (175),
.sim_buffer_delay_increment (10),
.static_delay_ctrl (0),
.lpm_type ("arriaii_dll")
) dll(
.clk (mem_clk_2x),
.aload (~pll_locked),
.delayctrlout (dqs_delay_ctrl),
.upndnout (),
.dqsupdate (),
.offsetdelayctrlclkout (),
.offsetdelayctrlout (),
.devpor (),
.devclrn (),
.upndninclkena (),
.upndnin ()
);
end
else
begin
assign dqs_delay_ctrl = {DQS_DELAY_CTL_WIDTH{1'b0}};
end
endgenerate
// Master reset generation :
always @(posedge phy_clk_1x or negedge phy_internal_reset_n)
begin
if (phy_internal_reset_n == 1'b0)
begin
reset_master_ams <= 1'b0;
global_pre_clear <= 1'b0;
end
else
begin
reset_master_ams <= 1'b1;
global_pre_clear <= reset_master_ams;
end
end
// phy_clk reset generation :
always @(posedge phy_clk_1x or negedge global_pre_clear)
begin
if (global_pre_clear == 1'b0)
begin
reset_phy_clk_1x_n <= 1'b0;
end
else
begin
reset_phy_clk_1x_n <= global_pre_clear;
end
end
// phy_clk reset generation for read datapaths :
//
ddr2_phy_alt_mem_phy_reset_pipe # (.PIPE_DEPTH (2) ) reset_rdp_phy_clk_pipe(
.clock (phy_clk_1x),
.pre_clear (seq_rdp_reset_req_n && global_pre_clear),
.reset_out (reset_rdp_phy_clk_1x_n)
);
// NB. phy_clk reset is generated above.
// Instantiate the reset pipes. The 4 reset signals below are family invariant
// whilst the other resets are generated on a per-family basis :
// mem_clk reset generation :
//
ddr2_phy_alt_mem_phy_reset_pipe # (.PIPE_DEPTH (2) ) mem_pipe(
.clock (mem_clk_2x),
.pre_clear (global_pre_clear),
.reset_out (mem_reset_n)
);
// mem_clk_2x reset generation - required for SIII DDR/DDR2 support :
//
ddr2_phy_alt_mem_phy_reset_pipe # (.PIPE_DEPTH (4) ) mem_clk_pipe(
.clock (mem_clk_2x),
.pre_clear (global_pre_clear),
.reset_out (reset_mem_clk_2x_n)
);
// poa_clk_2x reset generation (also reset on sequencer re-cal request) :
//
ddr2_phy_alt_mem_phy_reset_pipe # (.PIPE_DEPTH (2) ) poa_clk_pipe(
.clock (postamble_clk_2x),
.pre_clear (seq_rdp_reset_req_n && global_pre_clear),
.reset_out (reset_poa_clk_2x_n)
);
// write_clk_2x reset generation :
//
ddr2_phy_alt_mem_phy_reset_pipe # (.PIPE_DEPTH (4) ) write_clk_pipe(
.clock (write_clk_2x),
.pre_clear (global_pre_clear),
.reset_out (reset_write_clk_2x_n)
);
// ac_clk_2x reset generation :
//
ddr2_phy_alt_mem_phy_reset_pipe # (.PIPE_DEPTH (2) ) ac_clk_pipe_2x(
.clock (ac_clk_2x),
.pre_clear (global_pre_clear),
.reset_out (reset_ac_clk_2x_n)
);
// cs_clk_2x reset generation :
//
ddr2_phy_alt_mem_phy_reset_pipe # (.PIPE_DEPTH (4) ) cs_n_clk_pipe_2x(
.clock (cs_n_clk_2x),
.pre_clear (global_pre_clear),
.reset_out (reset_cs_n_clk_2x_n)
);
// measure_clk_2x reset generation :
//
ddr2_phy_alt_mem_phy_reset_pipe # (.PIPE_DEPTH (2) ) measure_clk_pipe(
.clock (measure_clk_2x),
.pre_clear (global_pre_clear),
.reset_out (reset_measure_clk_2x_n)
);
// resync_clk_2x reset generation (also reset on sequencer re-cal request):
//
ddr2_phy_alt_mem_phy_reset_pipe # (.PIPE_DEPTH (2) ) resync_clk_2x_pipe(
.clock (resync_clk_2x),
.pre_clear (seq_rdp_reset_req_n && global_pre_clear),
.reset_out (reset_resync_clk_2x_n)
);
endmodule
//
`ifdef ALT_MEM_PHY_DEFINES
`else
`include "alt_mem_phy_defines.v"
`endif
//
module ddr2_phy_alt_mem_phy_postamble ( // inputs
phy_clk_1x,
postamble_clk_2x,
reset_phy_clk_1x_n,
reset_poa_clk_2x_n,
seq_poa_lat_inc_1x,
seq_poa_lat_dec_1x,
seq_poa_protection_override_1x,
// for 2T / 2N addr/CMD drive both of these with the same value.
ctl_doing_rd_beat1_1x,
ctl_doing_rd_beat2_1x ,
// outputs
poa_postamble_en_preset_2x
) /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL = \"R105\"" */ ;
parameter FAMILY = "Stratix II";
parameter POSTAMBLE_INITIAL_LAT = 16;
parameter POSTAMBLE_RESYNC_LAT_CTL_EN = 0; // 0 means false, 1 means true
parameter POSTAMBLE_AWIDTH = 6;
parameter POSTAMBLE_HALFT_EN = 0; // 0 means false, 1 means true
parameter MEM_IF_POSTAMBLE_EN_WIDTH = 8;
parameter DWIDTH_RATIO = 4;
// clocks
input wire phy_clk_1x;
input wire postamble_clk_2x;
// resets
input wire reset_phy_clk_1x_n;
input wire reset_poa_clk_2x_n;
// control signals from sequencer
input wire seq_poa_lat_inc_1x;
input wire seq_poa_lat_dec_1x;
input wire seq_poa_protection_override_1x;
input wire ctl_doing_rd_beat1_1x;
input wire ctl_doing_rd_beat2_1x ;
// output to IOE
output wire [MEM_IF_POSTAMBLE_EN_WIDTH - 1 : 0] poa_postamble_en_preset_2x;
// internal wires/regs
reg [POSTAMBLE_AWIDTH - 1 : 0] rd_addr_2x;
reg [POSTAMBLE_AWIDTH - 1 : 0] wr_addr_1x;
reg [POSTAMBLE_AWIDTH - 1 : 0] next_wr_addr_1x;
reg [1:0] wr_data_1x;
wire wr_en_1x;
reg sync_seq_poa_lat_inc_1x;
reg sync_seq_poa_lat_dec_1x;
reg seq_poa_lat_inc_1x_1t;
reg seq_poa_lat_dec_1x_1t;
reg ctl_doing_rd_beat2_1x_r1;
wire postamble_en_2x;
reg [MEM_IF_POSTAMBLE_EN_WIDTH-1 : 0] postamble_en_pos_2x;
reg [MEM_IF_POSTAMBLE_EN_WIDTH-1 : 0] delayed_postamble_en_pos_2x;
reg [MEM_IF_POSTAMBLE_EN_WIDTH-1 : 0] postamble_en_pos_2x_vdc;
(*preserve*) reg [MEM_IF_POSTAMBLE_EN_WIDTH-1 : 0] postamble_en_2x_r;
reg bit_order_1x;
reg ams_inc;
reg ams_dec;
// loop variables
genvar i;
////////////////////////////////////////////////////////////////////////////////
// Generate Statements to synchronise controls if necessary
////////////////////////////////////////////////////////////////////////////////
generate
if (POSTAMBLE_RESYNC_LAT_CTL_EN == 0)
begin : sync_lat_controls
always @* // combinational logic sensitivity
begin
sync_seq_poa_lat_inc_1x = seq_poa_lat_inc_1x;
sync_seq_poa_lat_dec_1x = seq_poa_lat_dec_1x;
end
end
endgenerate
generate
if (POSTAMBLE_RESYNC_LAT_CTL_EN == 1)
begin : resynch_lat_controls
always @(posedge phy_clk_1x or negedge reset_phy_clk_1x_n)
begin
if (reset_phy_clk_1x_n == 1'b0)
begin
sync_seq_poa_lat_inc_1x <= 1'b0;
sync_seq_poa_lat_dec_1x <= 1'b0;
ams_inc <= 1'b0;
ams_dec <= 1'b0;
end
else
begin
sync_seq_poa_lat_inc_1x <= ams_inc;
sync_seq_poa_lat_dec_1x <= ams_dec;
ams_inc <= seq_poa_lat_inc_1x;
ams_dec <= seq_poa_lat_dec_1x;
end
end
end
endgenerate
////////////////////////////////////////////////////////////////////////////////
// write address controller
////////////////////////////////////////////////////////////////////////////////
// seq_poa_protection_override_1x is used to overide the write data
// Otherwise use bit_order_1x to choose how word is written into RAM.
always @*
begin
if (seq_poa_protection_override_1x == 1'b1)
begin
wr_data_1x = `POA_OVERRIDE_VAL;
end
else if (bit_order_1x == 1'b0)
begin
wr_data_1x = {ctl_doing_rd_beat2_1x, ctl_doing_rd_beat1_1x};
end
else
begin
wr_data_1x = {ctl_doing_rd_beat1_1x, ctl_doing_rd_beat2_1x_r1};
end
end
always @*
begin
next_wr_addr_1x = wr_addr_1x + 1'b1;
if (sync_seq_poa_lat_dec_1x == 1'b1 && seq_poa_lat_dec_1x_1t == 1'b0)
begin
if ((bit_order_1x == 1'b0) || (DWIDTH_RATIO == 2))
begin
next_wr_addr_1x = wr_addr_1x;
end
end
else if (sync_seq_poa_lat_inc_1x == 1'b1 && seq_poa_lat_inc_1x_1t == 1'b0)
begin
if ((bit_order_1x == 1'b1) || (DWIDTH_RATIO ==2))
begin
next_wr_addr_1x = wr_addr_1x + 2'b10;
end
end
end
always @(posedge phy_clk_1x or negedge reset_phy_clk_1x_n)
begin
if (reset_phy_clk_1x_n == 1'b0)
begin
wr_addr_1x <= POSTAMBLE_INITIAL_LAT[POSTAMBLE_AWIDTH - 1 : 0];
end
else
begin
wr_addr_1x <= next_wr_addr_1x;
end
end
always @(posedge phy_clk_1x or negedge reset_phy_clk_1x_n)
begin
if (reset_phy_clk_1x_n == 1'b0)
begin
ctl_doing_rd_beat2_1x_r1 <= 1'b0;
seq_poa_lat_inc_1x_1t <= 1'b0;
seq_poa_lat_dec_1x_1t <= 1'b0;
bit_order_1x <= 1'b0;
end
else
begin
ctl_doing_rd_beat2_1x_r1 <= ctl_doing_rd_beat2_1x;
seq_poa_lat_inc_1x_1t <= sync_seq_poa_lat_inc_1x;
seq_poa_lat_dec_1x_1t <= sync_seq_poa_lat_dec_1x;
if (DWIDTH_RATIO == 2)
bit_order_1x <= 1'b0;
else if (sync_seq_poa_lat_dec_1x == 1'b1 && seq_poa_lat_dec_1x_1t == 1'b0)
begin
bit_order_1x <= ~bit_order_1x;
end
else if (sync_seq_poa_lat_inc_1x == 1'b1 && seq_poa_lat_inc_1x_1t == 1'b0)
begin
bit_order_1x <= ~bit_order_1x;
end
end
end
///////////////////////////////////////////////////////////////////////////////////
// Instantiate the postamble dpram
///////////////////////////////////////////////////////////////////////////////////
assign wr_en_1x = 1'b1;
generate
// Half-rate mode :
if (DWIDTH_RATIO == 4)
begin : half_rate_ram_gen
altsyncram #(
.address_reg_b ("CLOCK1"),
.clock_enable_input_a ("BYPASS"),
.clock_enable_input_b ("BYPASS"),
.clock_enable_output_b ("BYPASS"),
.intended_device_family (FAMILY),
.lpm_type ("altsyncram"),
.numwords_a ((2**POSTAMBLE_AWIDTH )/2),
.numwords_b ((2**POSTAMBLE_AWIDTH )),
.operation_mode ("DUAL_PORT"),
.outdata_aclr_b ("NONE"),
.outdata_reg_b ("CLOCK1"),
.power_up_uninitialized ("FALSE"),
.widthad_a (POSTAMBLE_AWIDTH - 1),
.widthad_b (POSTAMBLE_AWIDTH),
.width_a (2),
.width_b (1),
.width_byteena_a (1)
) altsyncram_inst (
.wren_a (wr_en_1x),
.clock0 (phy_clk_1x),
.clock1 (postamble_clk_2x),
.address_a (wr_addr_1x[POSTAMBLE_AWIDTH - 2 : 0]),
.address_b (rd_addr_2x),
.data_a (wr_data_1x),
.q_b (postamble_en_2x),
.aclr0 (1'b0),
.aclr1 (1'b0),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (),
.clocken3 (),
.data_b (1'b1),
.q_a (),
.rden_a (),
.rden_b (1'b1),
.wren_b (1'b0),
.eccstatus ()
);
end
// Full-rate mode :
else
begin : full_rate_ram_gen
altsyncram #(
.address_reg_b ("CLOCK1"),
.clock_enable_input_a ("BYPASS"),
.clock_enable_input_b ("BYPASS"),
.clock_enable_output_b ("BYPASS"),
.intended_device_family (FAMILY),
.lpm_type ("altsyncram"),
.numwords_a (2**POSTAMBLE_AWIDTH ),
.numwords_b (2**POSTAMBLE_AWIDTH ),
.operation_mode ("DUAL_PORT"),
.outdata_aclr_b ("NONE"),
.outdata_reg_b ("UNREGISTERED"),
.power_up_uninitialized ("FALSE"),
.widthad_a (POSTAMBLE_AWIDTH),
.widthad_b (POSTAMBLE_AWIDTH),
.width_a (1),
.width_b (1),
.width_byteena_a (1)
) altsyncram_inst (
.wren_a (wr_en_1x),
.clock0 (phy_clk_1x),
.clock1 (postamble_clk_2x),
.address_a (wr_addr_1x),
.address_b (rd_addr_2x),
.data_a (wr_data_1x[0]),
.q_b (postamble_en_2x),
.aclr0 (1'b0),
.aclr1 (1'b0),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (),
.clocken3 (),
.data_b (1'b1),
.q_a (),
.rden_b (1'b1),
.rden_a (),
.wren_b (1'b0),
.eccstatus ()
);
end
endgenerate
///////////////////////////////////////////////////////////////////////////////////
// read address generator : just a free running counter.
///////////////////////////////////////////////////////////////////////////////////
always @(posedge postamble_clk_2x or negedge reset_poa_clk_2x_n)
begin
if (reset_poa_clk_2x_n == 1'b0)
begin
rd_addr_2x <= {POSTAMBLE_AWIDTH{1'b0}};
end
else
begin
rd_addr_2x <= rd_addr_2x + 1'b1; //inc address, can wrap
end
end
///////////////////////////////////////////////////////////////////////////////////
// generate the poa_postamble_en_preset_2x signal, 2 generate statements dependent
// on generics - both contained within another generate to produce output of
// appropriate width
///////////////////////////////////////////////////////////////////////////////////
generate
for (i=0; i<MEM_IF_POSTAMBLE_EN_WIDTH; i=i+1)
begin : postamble_output_gen
always @(posedge postamble_clk_2x or negedge reset_poa_clk_2x_n)
begin :pipeline_ram_op
if (reset_poa_clk_2x_n == 1'b0)
begin
postamble_en_2x_r[i] <= 1'b0;
end
else
begin
postamble_en_2x_r[i] <= postamble_en_2x;
end
end
always @(posedge postamble_clk_2x or negedge reset_poa_clk_2x_n)
begin
if (reset_poa_clk_2x_n == 1'b0)
begin
postamble_en_pos_2x[i] <= 1'b0;
end
else
begin
postamble_en_pos_2x[i] <= postamble_en_2x_r[i];
end
end
`ifdef QUARTUS__SIMGEN
`else
//synopsys translate_off
`endif
// Introduce 180degrees to model postamble insertion delay :
always @(negedge postamble_clk_2x or negedge reset_poa_clk_2x_n)
begin
if (reset_poa_clk_2x_n == 1'b0)
begin
postamble_en_pos_2x_vdc[i] <= 1'b0;
end
else
begin
postamble_en_pos_2x_vdc[i] <= postamble_en_pos_2x[i];
end
end
`ifdef QUARTUS__SIMGEN
`else
//synopsys translate_on
`endif
always @*
begin
delayed_postamble_en_pos_2x[i] = postamble_en_pos_2x[i];
`ifdef QUARTUS__SIMGEN
`else
//synopsys translate_off
`endif
delayed_postamble_en_pos_2x[i] = postamble_en_pos_2x_vdc[i];
`ifdef QUARTUS__SIMGEN
`else
//synopsys translate_on
`endif
end
case (POSTAMBLE_HALFT_EN)
1: begin : half_t_output
(* preserve *) reg [MEM_IF_POSTAMBLE_EN_WIDTH - 1 : 0] postamble_en_neg_2x;
always @(negedge postamble_clk_2x or negedge reset_poa_clk_2x_n)
begin
if (reset_poa_clk_2x_n == 1'b0)
begin
postamble_en_neg_2x[i] <= 1'b0;
end
else
begin
postamble_en_neg_2x[i] <= postamble_en_pos_2x[i];
end
end
assign poa_postamble_en_preset_2x[i] = postamble_en_pos_2x[i] && postamble_en_neg_2x[i];
end
0: begin : one_t_output
assign poa_postamble_en_preset_2x[i] = delayed_postamble_en_pos_2x[i];
end
endcase
end
endgenerate
endmodule
//
`ifdef ALT_MEM_PHY_DEFINES
`else
`include "alt_mem_phy_defines.v"
`endif
//
module ddr2_phy_alt_mem_phy_read_dp ( phy_clk_1x,
resync_clk_2x,
reset_phy_clk_1x_n,
reset_resync_clk_2x_n,
seq_rdp_dec_read_lat_1x,
seq_rdp_dmx_swap,
seq_rdp_inc_read_lat_1x,
dio_rdata_h_2x,
dio_rdata_l_2x,
ctl_mem_rdata
);
parameter ADDR_COUNT_WIDTH = 4;
parameter BIDIR_DPINS = 1; // 0 for QDR only.
parameter DWIDTH_RATIO = 4;
parameter MEM_IF_CLK_PS = 4000;
parameter FAMILY = "Stratix II";
parameter LOCAL_IF_DWIDTH = 256;
parameter MEM_IF_DQ_PER_DQS = 8;
parameter MEM_IF_DQS_WIDTH = 8;
parameter MEM_IF_DWIDTH = 64;
parameter MEM_IF_PHY_NAME = "STRATIXII_DQS";
parameter RDP_INITIAL_LAT = 6;
parameter RDP_RESYNC_LAT_CTL_EN = 0;
parameter RESYNC_PIPELINE_DEPTH = 1;
localparam NUM_DQS_PINS = MEM_IF_DQS_WIDTH;
input wire phy_clk_1x;
input wire resync_clk_2x;
input wire reset_phy_clk_1x_n;
input wire reset_resync_clk_2x_n;
input wire seq_rdp_dec_read_lat_1x;
input wire seq_rdp_dmx_swap;
input wire seq_rdp_inc_read_lat_1x;
input wire [MEM_IF_DWIDTH-1 : 0] dio_rdata_h_2x;
input wire [MEM_IF_DWIDTH-1 : 0] dio_rdata_l_2x;
output wire [LOCAL_IF_DWIDTH-1 : 0] ctl_mem_rdata;
// concatonated read data :
wire [(2*MEM_IF_DWIDTH)-1 : 0] dio_rdata_2x;
reg [ADDR_COUNT_WIDTH - DWIDTH_RATIO/2 : 0] rd_ram_rd_addr;
reg [ADDR_COUNT_WIDTH - 1 : 0] rd_ram_wr_addr;
wire [(2*MEM_IF_DWIDTH)-1 : 0] rd_data_piped_2x;
reg inc_read_lat_sync_r;
reg dec_read_lat_sync_r;
// Optional AMS registers :
reg inc_read_lat_ams;
reg inc_read_lat_sync;
reg dec_read_lat_ams;
reg dec_read_lat_sync;
reg state;
reg dmx_swap_ams;
reg dmx_swap_sync;
reg dmx_swap_sync_r;
wire wr_addr_toggle_detect;
wire wr_addr_stall;
wire wr_addr_double_inc;
wire rd_addr_stall;
wire rd_addr_double_inc;
// Read data from ram, prior to mapping/re-ordering :
wire [LOCAL_IF_DWIDTH-1 : 0] ram_rdata_1x;
////////////////////////////////////////////////////////////////////////////////
// Write Address block
////////////////////////////////////////////////////////////////////////////////
// 'toggle detect' logic :
assign wr_addr_toggle_detect = !dmx_swap_sync_r && dmx_swap_sync;
// 'stall' logic :
assign wr_addr_stall = !(~state && wr_addr_toggle_detect);
// 'double_inc' logic :
assign wr_addr_double_inc = state && wr_addr_toggle_detect;
// Write address generation
// When no demux toggle - increment every clock cycle
// When demux toggle is detected,invert addr_stall
// if addr_stall is 1 then do nothing to address, else double increment this cycle.
always@ (posedge resync_clk_2x or negedge reset_resync_clk_2x_n)
begin
if (reset_resync_clk_2x_n == 0)
begin
rd_ram_wr_addr <= RDP_INITIAL_LAT[3:0];
state <= 1'b0;
dmx_swap_ams <= 1'b0;
dmx_swap_sync <= 1'b0;
dmx_swap_sync_r <= 1'b0;
end
else
begin
// Synchronise dmx_swap :
dmx_swap_ams <= seq_rdp_dmx_swap;
dmx_swap_sync <= dmx_swap_ams;
dmx_swap_sync_r <= dmx_swap_sync;
// RAM write address :
if (wr_addr_stall == 1'b1)
begin
rd_ram_wr_addr <= rd_ram_wr_addr + 1'b1 + wr_addr_double_inc;
end
// Maintain single bit state :
if (wr_addr_toggle_detect == 1'b1)
begin
state <= ~state;
end
end
end
////////////////////////////////////////////////////////////////////////////////
// Pipeline registers
////////////////////////////////////////////////////////////////////////////////
// Concatenate the input read data taking note of ram input datawidths
// This is concatenating rdata_p and rdata_n from a DQS group together so that the rest
// of the pipeline can use a single vector:
generate
genvar dqs_group_num;
for (dqs_group_num = 0; dqs_group_num < NUM_DQS_PINS ; dqs_group_num = dqs_group_num + 1)
begin : ddio_remap
assign dio_rdata_2x[2*MEM_IF_DQ_PER_DQS*dqs_group_num + 2*MEM_IF_DQ_PER_DQS-1: 2*MEM_IF_DQ_PER_DQS*dqs_group_num]
= { dio_rdata_l_2x[MEM_IF_DQ_PER_DQS*dqs_group_num + MEM_IF_DQ_PER_DQS-1: MEM_IF_DQ_PER_DQS*dqs_group_num],
dio_rdata_h_2x[MEM_IF_DQ_PER_DQS*dqs_group_num + MEM_IF_DQ_PER_DQS-1: MEM_IF_DQ_PER_DQS*dqs_group_num]
};
end
endgenerate
// Generate appropriate pipeline depth
generate
genvar i;
if (RESYNC_PIPELINE_DEPTH > 0)
begin : resync_pipeline_gen
// Declare pipeline registers
reg [(2*MEM_IF_DWIDTH)-1 : 0 ] pipeline_delay [0 : RESYNC_PIPELINE_DEPTH - 1] ;
for (i=0; i< RESYNC_PIPELINE_DEPTH; i = i + 1)
begin : PIPELINE
always @(posedge resync_clk_2x)
begin
if (i==0)
pipeline_delay[i] <= dio_rdata_2x;
else
pipeline_delay[i] <= pipeline_delay[i-1];
end //always
end //for
assign rd_data_piped_2x = pipeline_delay[RESYNC_PIPELINE_DEPTH-1];
end
// If pipeline registers are not configured, pass-thru :
else
begin : no_resync_pipe_gen
assign rd_data_piped_2x = dio_rdata_2x;
end
endgenerate
////////////////////////////////////////////////////////////////////////////////
// Instantiate the read_dp dpram
////////////////////////////////////////////////////////////////////////////////
generate
if (DWIDTH_RATIO == 4)
begin : half_rate_ram_gen
altsyncram #(
.address_reg_b ("CLOCK1"),
.clock_enable_input_a ("BYPASS"),
.clock_enable_input_b ("BYPASS"),
.clock_enable_output_b ("BYPASS"),
.intended_device_family (FAMILY),
.lpm_type ("altsyncram"),
.numwords_a ((2**ADDR_COUNT_WIDTH )),
.numwords_b ((2**ADDR_COUNT_WIDTH )/2),
.operation_mode ("DUAL_PORT"),
.outdata_aclr_b ("NONE"),
.outdata_reg_b ("CLOCK1"),
.power_up_uninitialized ("FALSE"),
.widthad_a (ADDR_COUNT_WIDTH),
.widthad_b (ADDR_COUNT_WIDTH - 1),
.width_a (MEM_IF_DWIDTH*2),
.width_b (MEM_IF_DWIDTH*4),
.width_byteena_a (1)
) altsyncram_component (
.wren_a (1'b1),
.clock0 (resync_clk_2x),
.clock1 (phy_clk_1x),
.address_a (rd_ram_wr_addr),
.address_b (rd_ram_rd_addr),
.data_a (rd_data_piped_2x),
.q_b (ram_rdata_1x),
.aclr0 (1'b0),
.aclr1 (1'b0),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (),
.clocken3 (),
.data_b ({(MEM_IF_DWIDTH*4){1'b1}}),
.q_a (),
.rden_b (1'b1),
.rden_a (),
.wren_b (1'b0),
.eccstatus ()
);
// Read data mapping :
genvar dqs_group_num_b;
for (dqs_group_num_b = 0; dqs_group_num_b < NUM_DQS_PINS ; dqs_group_num_b = dqs_group_num_b + 1)
begin : remap_logic
assign ctl_mem_rdata [MEM_IF_DWIDTH * 0 + dqs_group_num_b * MEM_IF_DQ_PER_DQS + MEM_IF_DQ_PER_DQS -1 : MEM_IF_DWIDTH * 0 + dqs_group_num_b * MEM_IF_DQ_PER_DQS ] = ram_rdata_1x [ dqs_group_num_b * 2 * MEM_IF_DQ_PER_DQS + MEM_IF_DQ_PER_DQS - 1 : dqs_group_num_b * 2 * MEM_IF_DQ_PER_DQS ];
assign ctl_mem_rdata [MEM_IF_DWIDTH * 1 + dqs_group_num_b * MEM_IF_DQ_PER_DQS + MEM_IF_DQ_PER_DQS -1 : MEM_IF_DWIDTH * 1 + dqs_group_num_b * MEM_IF_DQ_PER_DQS ] = ram_rdata_1x [ dqs_group_num_b * 2 * MEM_IF_DQ_PER_DQS + 2 * MEM_IF_DQ_PER_DQS - 1 : dqs_group_num_b * 2 * MEM_IF_DQ_PER_DQS + MEM_IF_DQ_PER_DQS ];
assign ctl_mem_rdata [MEM_IF_DWIDTH * 2 + dqs_group_num_b * MEM_IF_DQ_PER_DQS + MEM_IF_DQ_PER_DQS -1 : MEM_IF_DWIDTH * 2 + dqs_group_num_b * MEM_IF_DQ_PER_DQS ] = ram_rdata_1x [ MEM_IF_DWIDTH * 2 + dqs_group_num_b * 2 * MEM_IF_DQ_PER_DQS + MEM_IF_DQ_PER_DQS - 1 : MEM_IF_DWIDTH * 2 + dqs_group_num_b * 2 * MEM_IF_DQ_PER_DQS ];
assign ctl_mem_rdata [MEM_IF_DWIDTH * 3 + dqs_group_num_b * MEM_IF_DQ_PER_DQS + MEM_IF_DQ_PER_DQS -1 : MEM_IF_DWIDTH * 3 + dqs_group_num_b * MEM_IF_DQ_PER_DQS ] = ram_rdata_1x [ MEM_IF_DWIDTH * 2 + dqs_group_num_b * 2 * MEM_IF_DQ_PER_DQS + 2 * MEM_IF_DQ_PER_DQS - 1 : MEM_IF_DWIDTH * 2 + dqs_group_num_b * 2 * MEM_IF_DQ_PER_DQS + MEM_IF_DQ_PER_DQS ];
end
end // block: half_rate_dp
endgenerate
// full-rate
generate
if (DWIDTH_RATIO == 2)
begin : full_rate_ram_gen
altsyncram #(
.address_reg_b ("CLOCK1"),
.clock_enable_input_a ("BYPASS"),
.clock_enable_input_b ("BYPASS"),
.clock_enable_output_b ("BYPASS"),
.intended_device_family (FAMILY),
.lpm_type ("altsyncram"),
.numwords_a ((2**ADDR_COUNT_WIDTH )),
.numwords_b ((2**ADDR_COUNT_WIDTH )),
.operation_mode ("DUAL_PORT"),
.outdata_aclr_b ("NONE"),
.outdata_reg_b ("CLOCK1"),
.power_up_uninitialized ("FALSE"),
.widthad_a (ADDR_COUNT_WIDTH),
.widthad_b (ADDR_COUNT_WIDTH),
.width_a (MEM_IF_DWIDTH*2),
.width_b (MEM_IF_DWIDTH*2),
.width_byteena_a (1)
) altsyncram_component(
.wren_a (1'b1),
.clock0 (resync_clk_2x),
.clock1 (phy_clk_1x),
.address_a (rd_ram_wr_addr),
.address_b (rd_ram_rd_addr),
.data_a (rd_data_piped_2x),
.q_b (ram_rdata_1x),
.aclr0 (1'b0),
.aclr1 (1'b0),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (),
.clocken3 (),
.data_b ({(MEM_IF_DWIDTH*2){1'b1}}),
.q_a (),
.rden_b (1'b1),
.rden_a (),
.wren_b (1'b0),
.eccstatus ()
);
// Read data mapping :
genvar dqs_group_num_b;
for (dqs_group_num_b = 0; dqs_group_num_b < NUM_DQS_PINS ; dqs_group_num_b = dqs_group_num_b + 1)
begin : remap_logic
assign ctl_mem_rdata [MEM_IF_DWIDTH * 0 + dqs_group_num_b * MEM_IF_DQ_PER_DQS + MEM_IF_DQ_PER_DQS -1 : MEM_IF_DWIDTH * 0 + dqs_group_num_b * MEM_IF_DQ_PER_DQS ] = ram_rdata_1x [ dqs_group_num_b * 2 * MEM_IF_DQ_PER_DQS + MEM_IF_DQ_PER_DQS - 1 : dqs_group_num_b * 2 * MEM_IF_DQ_PER_DQS ];
assign ctl_mem_rdata [MEM_IF_DWIDTH * 1 + dqs_group_num_b * MEM_IF_DQ_PER_DQS + MEM_IF_DQ_PER_DQS -1 : MEM_IF_DWIDTH * 1 + dqs_group_num_b * MEM_IF_DQ_PER_DQS ] = ram_rdata_1x [ dqs_group_num_b * 2 * MEM_IF_DQ_PER_DQS + 2 * MEM_IF_DQ_PER_DQS - 1 : dqs_group_num_b * 2 * MEM_IF_DQ_PER_DQS + MEM_IF_DQ_PER_DQS ];
end
end // block: half_rate_dp
endgenerate
////////////////////////////////////////////////////////////////////////////////
// Read Address block
////////////////////////////////////////////////////////////////////////////////
// Optional Anti-metastability flops :
generate
if (RDP_RESYNC_LAT_CTL_EN == 1)
always@ (posedge phy_clk_1x or negedge reset_phy_clk_1x_n)
begin : rd_addr_ams
if (reset_phy_clk_1x_n == 1'b0)
begin
inc_read_lat_ams <= 1'b0;
inc_read_lat_sync <= 1'b0;
inc_read_lat_sync_r <= 1'b0;
// Synchronise rd_lat_inc_1x :
dec_read_lat_ams <= 1'b0;
dec_read_lat_sync <= 1'b0;
dec_read_lat_sync_r <= 1'b0;
end
else
begin
// Synchronise rd_lat_inc_1x :
inc_read_lat_ams <= seq_rdp_inc_read_lat_1x;
inc_read_lat_sync <= inc_read_lat_ams;
inc_read_lat_sync_r <= inc_read_lat_sync;
// Synchronise rd_lat_inc_1x :
dec_read_lat_ams <= seq_rdp_dec_read_lat_1x;
dec_read_lat_sync <= dec_read_lat_ams;
dec_read_lat_sync_r <= dec_read_lat_sync;
end
end // always
// No anti-metastability protection required :
else
always@ (posedge phy_clk_1x or negedge reset_phy_clk_1x_n)
begin
if (reset_phy_clk_1x_n == 1'b0)
begin
inc_read_lat_sync_r <= 1'b0;
dec_read_lat_sync_r <= 1'b0;
end
else
begin
// No need to re-synchronise, just register for edge detect :
inc_read_lat_sync_r <= seq_rdp_inc_read_lat_1x;
dec_read_lat_sync_r <= seq_rdp_dec_read_lat_1x;
end
end
endgenerate
generate
if (RDP_RESYNC_LAT_CTL_EN == 1)
begin : lat_ctl_en_gen
// 'toggle detect' logic :
//assign rd_addr_double_inc = !inc_read_lat_sync_r && inc_read_lat_sync;
assign rd_addr_double_inc = ( !dec_read_lat_sync_r && dec_read_lat_sync );
// 'stall' logic :
// assign rd_addr_stall = !( !dec_read_lat_sync_r && dec_read_lat_sync );
assign rd_addr_stall = !inc_read_lat_sync_r && inc_read_lat_sync;
end
else
begin : no_lat_ctl_en_gen
// 'toggle detect' logic :
//assign rd_addr_double_inc = !inc_read_lat_sync_r && seq_rdp_inc_read_lat_1x;
assign rd_addr_double_inc = ( !dec_read_lat_sync_r && seq_rdp_dec_read_lat_1x );
// 'stall' logic :
//assign rd_addr_stall = !( !dec_read_lat_sync_r && seq_rdp_dec_read_lat_1x );
assign rd_addr_stall = !inc_read_lat_sync_r && seq_rdp_inc_read_lat_1x;
end
endgenerate
always@ (posedge phy_clk_1x or negedge reset_phy_clk_1x_n)
begin
if (reset_phy_clk_1x_n == 0)
begin
rd_ram_rd_addr <= { ADDR_COUNT_WIDTH - DWIDTH_RATIO/2 {1'b0} };
end
else
begin
// RAM read address :
if (rd_addr_stall == 1'b0)
begin
rd_ram_rd_addr <= rd_ram_rd_addr + 1'b1 + rd_addr_double_inc;
end
end
end
endmodule
//
// Note, this write datapath logic matches both the spec, and what was done in
// the beta project.
`ifdef ALT_MEM_PHY_DEFINES
`else
`include "alt_mem_phy_defines.v"
`endif
//
module ddr2_phy_alt_mem_phy_write_dp_fr(
// clocks
phy_clk_1x, // full-rate clock
mem_clk_2x, // full-rate clock
write_clk_2x, // full-rate clock
// active-low resets, sync'd to clock domain
reset_phy_clk_1x_n,
reset_mem_clk_2x_n,
reset_write_clk_2x_n,
// control i/f inputs
ctl_mem_be,
ctl_mem_dqs_burst,
ctl_mem_wdata,
ctl_mem_wdata_valid,
// seq i/f inputs :
seq_be,
seq_dqs_burst,
seq_wdata,
seq_wdata_valid,
seq_ctl_sel,
// outputs to IOEs
wdp_wdata_h_2x,
wdp_wdata_l_2x,
wdp_wdata_oe_2x,
wdp_wdqs_2x,
wdp_wdqs_oe_2x,
wdp_dm_h_2x,
wdp_dm_l_2x
);
// parameter declarations
parameter BIDIR_DPINS = 1;
parameter LOCAL_IF_DRATE = "FULL";
parameter LOCAL_IF_DWIDTH = 256;
parameter MEM_IF_DM_WIDTH = 8;
parameter MEM_IF_DQ_PER_DQS = 8;
parameter MEM_IF_DQS_WIDTH = 8;
parameter GENERATE_WRITE_DQS = 1;
parameter MEM_IF_DWIDTH = 64;
parameter DWIDTH_RATIO = 2;
parameter MEM_IF_DM_PINS_EN = 1;
// "internal" parameter, not to get propagated from higher levels...
parameter NUM_DUPLICATE_REGS = 4; // 1 per nibble to save registers
// clocks
input wire phy_clk_1x; // half-rate system clock
input wire mem_clk_2x; // full-rate memory clock
input wire write_clk_2x; // full-rate write clock
// resets, async assert, de-assert is sync'd to each clock domain
input wire reset_phy_clk_1x_n;
input wire reset_mem_clk_2x_n;
input wire reset_write_clk_2x_n;
// control i/f inputs
input wire [MEM_IF_DM_WIDTH * DWIDTH_RATIO - 1 : 0] ctl_mem_be; // byte enable == ~data mask
input wire [MEM_IF_DQS_WIDTH * DWIDTH_RATIO/2 - 1 : 0] ctl_mem_dqs_burst; // dqs burst indication
input wire [MEM_IF_DWIDTH*DWIDTH_RATIO - 1 : 0] ctl_mem_wdata; // write data
input wire [MEM_IF_DQS_WIDTH * DWIDTH_RATIO/2 - 1 : 0] ctl_mem_wdata_valid; // write data valid indication
// seq i/f inputs
input wire [MEM_IF_DM_WIDTH * DWIDTH_RATIO - 1 : 0] seq_be;
input wire [MEM_IF_DWIDTH * DWIDTH_RATIO - 1 : 0] seq_wdata;
input wire [MEM_IF_DQS_WIDTH * DWIDTH_RATIO/2 - 1 : 0] seq_dqs_burst;
input wire [MEM_IF_DQS_WIDTH * DWIDTH_RATIO/2 - 1 : 0] seq_wdata_valid;
input wire seq_ctl_sel;
(*preserve*) output reg [MEM_IF_DWIDTH - 1 : 0] wdp_wdata_h_2x; // wdata_h to IOE
(*preserve*) output reg [MEM_IF_DWIDTH - 1 : 0] wdp_wdata_l_2x; // wdata_l to IOE
output wire [MEM_IF_DWIDTH - 1 : 0] wdp_wdata_oe_2x; // OE to DQ pin
output reg [(MEM_IF_DQS_WIDTH) - 1 : 0] wdp_wdqs_2x; // DQS to IOE
output reg [(MEM_IF_DQS_WIDTH) - 1 : 0] wdp_wdqs_oe_2x; // OE to DQS pin
(*preserve*) output reg [MEM_IF_DM_WIDTH -1 : 0] wdp_dm_h_2x; // dm_h to IOE
(*preserve*) output reg [MEM_IF_DM_WIDTH -1 : 0] wdp_dm_l_2x; // dm_l to IOE
// internal reg declarations
// registers (on a per- DQS group basis) which sync the dqs_burst_1x to phy_clk or mem_clk_2x.
// They are used to generate the DQS signal and its OE.
(*preserve*) reg [MEM_IF_DQS_WIDTH -1 : 0] dqs_burst_1x_r;
(*preserve*) reg [MEM_IF_DQS_WIDTH -1 : 0] dqs_burst_2x_r1;
(*preserve*) reg [MEM_IF_DQS_WIDTH -1 : 0] dqs_burst_2x_r2;
(*preserve*) reg [MEM_IF_DQS_WIDTH -1 : 0] dqs_burst_2x_r3;
// registers to generate the dq_oe, on a per nibble basis, to save registers.
(*preserve*) reg [MEM_IF_DWIDTH/NUM_DUPLICATE_REGS -1 : 0 ] wdata_valid_1x_r1; // wdata_valid_1x, retimed in phy_clk_1x
(*preserve*) reg [MEM_IF_DWIDTH/NUM_DUPLICATE_REGS -1 : 0 ] wdata_valid_1x_r2; // wdata_valid_1x_r1, retimed in phy_clk_1x
(* preserve, altera_attribute = "-name ADV_NETLIST_OPT_ALLOWED \"NEVER ALLOW\"" *) reg [MEM_IF_DWIDTH/NUM_DUPLICATE_REGS -1 : 0 ] dq_oe_2x; // 1 per nibble, to save registers
reg [MEM_IF_DWIDTH - 1 : 0] wdp_wdata_oe_2x_int; // intermediate output, gets assigned to o/p signal
reg [LOCAL_IF_DWIDTH -1 : 0] mem_wdata_r1; // mem_wdata, retimed in phy_clk_1x
reg [LOCAL_IF_DWIDTH -1 : 0] mem_wdata_r2; // mem_wdata_r1, retimed in phy_clk_1x
// registers used to generate the mux select signal for wdata.
(*preserve*) reg [MEM_IF_DWIDTH/NUM_DUPLICATE_REGS -1 : 0 ] wdata_valid_1x_r; // 1 per nibble, to save registers
(*preserve*) reg [MEM_IF_DWIDTH/NUM_DUPLICATE_REGS -1 : 0 ] wdata_valid_2x_r1; // 1 per nibble, to save registers
(*preserve*) reg [MEM_IF_DWIDTH/NUM_DUPLICATE_REGS -1 : 0 ] wdata_valid_2x_r2; // 1 per nibble, to save registers
(*preserve*) reg [MEM_IF_DWIDTH/NUM_DUPLICATE_REGS -1 : 0 ] wdata_sel; // 1 per nibble, to save registers
// registers used to generate the dm mux select and dm signals
reg [MEM_IF_DM_WIDTH*DWIDTH_RATIO - 1 : 0] mem_dm_r1;
reg [MEM_IF_DM_WIDTH*DWIDTH_RATIO - 1 : 0] mem_dm_r2;
(*preserve*) reg wdata_dm_1x_r; // preserved, to stop merge with wdata_valid_1x_r
(*preserve*) reg wdata_dm_2x_r1; // preserved, to stop merge with wdata_valid_2x_r1
(*preserve*) reg wdata_dm_2x_r2; // preserved, to stop merge with wdata_valid_2x_r2
(*preserve*) reg dm_sel; // preserved, to stop merge with wdata_sel
// MUX outputs....
reg [MEM_IF_DQS_WIDTH * DWIDTH_RATIO/2 - 1 : 0] mem_dqs_burst ;
reg [MEM_IF_DQS_WIDTH * DWIDTH_RATIO/2 - 1 : 0] mem_wdata_valid;
reg [MEM_IF_DM_WIDTH * DWIDTH_RATIO - 1 : 0] mem_be ;
reg [MEM_IF_DWIDTH * DWIDTH_RATIO - 1 : 0] mem_wdata ;
wire [MEM_IF_DQS_WIDTH - 1 : 0] wdp_wdqs_oe_2x_int;
always @*
begin
// Select controller or sequencer according to the select signal :
if (seq_ctl_sel)
begin
mem_be = seq_be;
mem_wdata = seq_wdata;
mem_wdata_valid = seq_wdata_valid;
mem_dqs_burst = seq_dqs_burst;
end
else
begin
mem_be = ctl_mem_be;
mem_wdata = ctl_mem_wdata;
mem_wdata_valid = ctl_mem_wdata_valid;
mem_dqs_burst = ctl_mem_dqs_burst;
end
end
genvar a, b, c, d; // variable for generate statement
integer j; // variable for loop counters
/////////////////////////////////////////////////////////////////////////
// generate the following write DQS logic on a per DQS group basis.
// wdp_wdqs_2x and wdp_wdqs_oe_2x get output to the IOEs.
////////////////////////////////////////////////////////////////////////
generate
if (GENERATE_WRITE_DQS == 1)
begin
for (a=0; a<MEM_IF_DQS_WIDTH; a = a+1)
begin : gen_loop_dqs
always @(posedge phy_clk_1x or negedge reset_phy_clk_1x_n)
begin
if (reset_phy_clk_1x_n == 1'b0)
begin
wdp_wdqs_2x[a] <= 0;
wdp_wdqs_oe_2x[a] <= 0;
end
else
begin
wdp_wdqs_2x[a] <= wdp_wdqs_oe_2x[a];
wdp_wdqs_oe_2x[a] <= mem_dqs_burst;
end
end
end
end
endgenerate
///////////////////////////////////////////////////////////////////
// Generate the write DQ logic.
// These are internal registers which will be used to assign to:
// wdp_wdata_h_2x, wdp_wdata_l_2x, wdp_wdata_oe_2x
// (these get output to the IOEs).
//////////////////////////////////////////////////////////////////
// number of times to replicate mem_wdata_valid bits
parameter DQ_OE_REPS = MEM_IF_DQ_PER_DQS/NUM_DUPLICATE_REGS;
generate
for (a=0; a<MEM_IF_DWIDTH/MEM_IF_DQ_PER_DQS; a=a+1)
begin : gen_dq_oe_2x
always @(posedge phy_clk_1x or negedge reset_phy_clk_1x_n)
begin
if (reset_phy_clk_1x_n == 1'b0)
begin
dq_oe_2x[DQ_OE_REPS*(a+1)-1:DQ_OE_REPS*a] <= {(DQ_OE_REPS){1'b0}};
end
else
begin
dq_oe_2x[DQ_OE_REPS*(a+1)-1:DQ_OE_REPS*a] <= {(DQ_OE_REPS){mem_wdata_valid[a]}};
end
end
end
endgenerate
////////////////////////////////////////////////////////////////////////////////
// fanout the dq_oe_2x, which has one register per NUM_DUPLICATE_REGS
// (to save registers), to each bit of wdp_wdata_oe_2x_int and then
// assign to the output wire wdp_wdata_oe_2x( ie one oe for each DQ "pin").
////////////////////////////////////////////////////////////////////////////////
always @(dq_oe_2x)
begin
for (j=0; j<MEM_IF_DWIDTH; j=j+1)
begin
wdp_wdata_oe_2x_int[j] = dq_oe_2x[(j/NUM_DUPLICATE_REGS)];
end
end
assign wdp_wdata_oe_2x = wdp_wdata_oe_2x_int;
//////////////////////////////////////////////////////////////////////
// Write DQ mapping from mem_wdata to wdata_l_2x, wdata_h_2x
//////////////////////////////////////////////////////////////////////
generate
for (c=0; c<MEM_IF_DWIDTH; c=c+1)
begin : gen_wdata
always @(posedge phy_clk_1x)
begin
wdp_wdata_l_2x[c] <= mem_wdata[c + MEM_IF_DWIDTH];
wdp_wdata_h_2x[c] <= mem_wdata[c ];
end
end
endgenerate
///////////////////////////////////////////////////////
// Conditional generation of DM logic, based on generic
///////////////////////////////////////////////////////
generate
if (MEM_IF_DM_PINS_EN == 1'b1)
begin : dm_logic_enabled
///////////////////////////////////////////////////////////////////
// Write DM logic: assignment to wdp_dm_h_2x, wdp_dm_l_2x
///////////////////////////////////////////////////////////////////
// for loop inside a generate statement, but outside a procedural block
// is treated as a nested generate
for (d=0; d<MEM_IF_DM_WIDTH; d=d+1)
begin : gen_dm
always @(posedge phy_clk_1x)
begin
if (mem_wdata_valid[d] == 1'b1) // nb might need to duplicate to meet timing
begin
wdp_dm_l_2x[d] <= mem_be[d+MEM_IF_DM_WIDTH];
wdp_dm_h_2x[d] <= mem_be[d];
end
// To support writes of less than the burst length, mask data when invalid :
else
begin
wdp_dm_l_2x[d] <= 1'b1;
wdp_dm_h_2x[d] <= 1'b1;
end
end
end // block: gen_dm
end // block: dm_logic_enabled
endgenerate
endmodule
//
`ifdef ALT_MEM_PHY_DEFINES
`else
`include "alt_mem_phy_defines.v"
`endif
`default_nettype none
//
module ddr2_phy_alt_mem_phy_rdata_valid ( // inputs
phy_clk_1x,
reset_phy_clk_1x_n,
seq_rdata_valid_lat_dec,
seq_rdata_valid_lat_inc,
seq_doing_rd,
ctl_doing_rd,
ctl_cal_success,
// outputs
ctl_rdata_valid,
seq_rdata_valid
);
parameter FAMILY = "CYCLONEIII";
parameter MEM_IF_DQS_WIDTH = 8;
parameter RDATA_VALID_AWIDTH = 5;
parameter RDATA_VALID_INITIAL_LAT = 16;
parameter DWIDTH_RATIO = 2;
localparam MAX_RDATA_VALID_DELAY = 2 ** RDATA_VALID_AWIDTH;
localparam RDV_DELAY_SHR_LEN = MAX_RDATA_VALID_DELAY*(DWIDTH_RATIO/2);
// clocks
input wire phy_clk_1x;
// resets
input wire reset_phy_clk_1x_n;
// control signals from sequencer
input wire seq_rdata_valid_lat_dec;
input wire seq_rdata_valid_lat_inc;
input wire [MEM_IF_DQS_WIDTH * DWIDTH_RATIO / 2 -1 : 0] seq_doing_rd;
input wire [MEM_IF_DQS_WIDTH * DWIDTH_RATIO / 2 -1 : 0] ctl_doing_rd;
input wire ctl_cal_success;
// output to IOE
output reg [DWIDTH_RATIO / 2 -1 : 0] ctl_rdata_valid;
output reg [DWIDTH_RATIO / 2 -1 : 0] seq_rdata_valid;
// Internal Signals / Variables
reg [RDATA_VALID_AWIDTH - 1 : 0] rd_addr;
reg [RDATA_VALID_AWIDTH - 1 : 0] wr_addr;
reg [RDATA_VALID_AWIDTH - 1 : 0] next_wr_addr;
reg [DWIDTH_RATIO/2 - 1 : 0] wr_data;
wire [DWIDTH_RATIO / 2 -1 : 0] int_rdata_valid;
reg [DWIDTH_RATIO/2 - 1 : 0] rdv_pipe_ip;
reg rdv_pipe_ip_beat2_r;
reg [MEM_IF_DQS_WIDTH * DWIDTH_RATIO/2 - 1 : 0] merged_doing_rd;
reg seq_rdata_valid_lat_dec_1t;
reg seq_rdata_valid_lat_inc_1t;
reg bit_order_1x;
// Generate the input to the RDV delay.
// Also determine the data for the OCT control & postamble paths (merged_doing_rd)
generate
if (DWIDTH_RATIO == 4)
begin : merging_doing_rd_halfrate
always @*
begin
merged_doing_rd = seq_doing_rd | (ctl_doing_rd & {(2 * MEM_IF_DQS_WIDTH) {ctl_cal_success}});
rdv_pipe_ip[0] = | merged_doing_rd[ MEM_IF_DQS_WIDTH - 1 : 0];
rdv_pipe_ip[1] = | merged_doing_rd[2 * MEM_IF_DQS_WIDTH - 1 : MEM_IF_DQS_WIDTH];
end
end
else // DWIDTH_RATIO == 2
begin : merging_doing_rd_fullrate
always @*
begin
merged_doing_rd = seq_doing_rd | (ctl_doing_rd & { MEM_IF_DQS_WIDTH {ctl_cal_success}});
rdv_pipe_ip[0] = | merged_doing_rd[MEM_IF_DQS_WIDTH - 1 : 0];
end
end // else: !if(DWIDTH_RATIO == 4)
endgenerate
// Register inc/dec rdata_valid signals and generate bit_order_1x
always @(posedge phy_clk_1x or negedge reset_phy_clk_1x_n)
begin
if (reset_phy_clk_1x_n == 1'b0)
begin
seq_rdata_valid_lat_dec_1t <= 1'b0;
seq_rdata_valid_lat_inc_1t <= 1'b0;
bit_order_1x <= 1'b1;
end
else
begin
rdv_pipe_ip_beat2_r <= rdv_pipe_ip[DWIDTH_RATIO/2 - 1];
seq_rdata_valid_lat_dec_1t <= seq_rdata_valid_lat_dec;
seq_rdata_valid_lat_inc_1t <= seq_rdata_valid_lat_inc;
if (DWIDTH_RATIO == 2)
bit_order_1x <= 1'b0;
else if (seq_rdata_valid_lat_dec == 1'b1 && seq_rdata_valid_lat_dec_1t == 1'b0)
begin
bit_order_1x <= ~bit_order_1x;
end
else if (seq_rdata_valid_lat_inc == 1'b1 && seq_rdata_valid_lat_inc_1t == 1'b0)
begin
bit_order_1x <= ~bit_order_1x;
end
end
end
// write data
generate // based on DWIDTH RATIO
if (DWIDTH_RATIO == 4) // Half Rate
begin : halfrate_wdata_gen
always @* // combinational logic sensitivity
begin
if (bit_order_1x == 1'b0)
begin
wr_data = {rdv_pipe_ip[1], rdv_pipe_ip[0]};
end
else
begin
wr_data = {rdv_pipe_ip[0], rdv_pipe_ip_beat2_r};
end
end
end
else // Full-rate
begin : fullrate_wdata_gen
always @* // combinational logic sensitivity
begin
wr_data = rdv_pipe_ip;
end
end
endgenerate
// write address
always @*
begin
next_wr_addr = wr_addr + 1'b1;
if (seq_rdata_valid_lat_dec == 1'b1 && seq_rdata_valid_lat_dec_1t == 1'b0)
begin
if ((bit_order_1x == 1'b0) || (DWIDTH_RATIO == 2))
begin
next_wr_addr = wr_addr;
end
end
else if (seq_rdata_valid_lat_inc == 1'b1 && seq_rdata_valid_lat_inc_1t == 1'b0)
begin
if ((bit_order_1x == 1'b1) || (DWIDTH_RATIO ==2))
begin
next_wr_addr = wr_addr + 2'h2;
end
end
end
always @(posedge phy_clk_1x or negedge reset_phy_clk_1x_n)
begin
if (reset_phy_clk_1x_n == 1'b0)
begin
wr_addr <= RDATA_VALID_INITIAL_LAT[RDATA_VALID_AWIDTH - 1 : 0];
end
else
begin
wr_addr <= next_wr_addr;
end
end
// read address generator : just a free running counter.
always @(posedge phy_clk_1x or negedge reset_phy_clk_1x_n)
begin
if (reset_phy_clk_1x_n == 1'b0)
begin
rd_addr <= {RDATA_VALID_AWIDTH{1'b0}};
end
else
begin
rd_addr <= rd_addr + 1'b1; //inc address, can wrap
end
end
// altsyncram instance
altsyncram #(.
address_aclr_b ("NONE"),
.address_reg_b ("CLOCK0"),
.clock_enable_input_a ("BYPASS"),
.clock_enable_input_b ("BYPASS"),
.clock_enable_output_b ("BYPASS"),
.intended_device_family (FAMILY),
.lpm_type ("altsyncram"),
.numwords_a (2**RDATA_VALID_AWIDTH),
.numwords_b (2**RDATA_VALID_AWIDTH),
.operation_mode ("DUAL_PORT"),
.outdata_aclr_b ("NONE"),
.outdata_reg_b ("CLOCK0"),
.power_up_uninitialized ("FALSE"),
.widthad_a (RDATA_VALID_AWIDTH),
.widthad_b (RDATA_VALID_AWIDTH),
.width_a (DWIDTH_RATIO/2),
.width_b (DWIDTH_RATIO/2),
.width_byteena_a (1)
) altsyncram_component (
.wren_a (1'b1),
.clock0 (phy_clk_1x),
.address_a (wr_addr),
.address_b (rd_addr),
.data_a (wr_data),
.q_b (int_rdata_valid),
.aclr0 (1'b0),
.aclr1 (1'b0),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_b ({(DWIDTH_RATIO/2){1'b1}}),
.eccstatus (),
.q_a (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_b (1'b0)
);
// Generate read data valid enable signals for controller and seqencer
always @(posedge phy_clk_1x or negedge reset_phy_clk_1x_n)
begin
if (reset_phy_clk_1x_n == 1'b0)
begin
ctl_rdata_valid <= {(DWIDTH_RATIO/2){1'b0}};
seq_rdata_valid <= {(DWIDTH_RATIO/2){1'b0}};
end
else
begin
// shift the shift register by DWIDTH_RATIO locations
// rdv_delay_index plus (DWIDTH_RATIO/2)-1 bits counting down
ctl_rdata_valid <= int_rdata_valid & {(DWIDTH_RATIO/2){ctl_cal_success}};
seq_rdata_valid <= int_rdata_valid;
end
end
endmodule
`default_nettype wire
//
`ifdef ALT_MEM_PHY_DEFINES
`else
`include "alt_mem_phy_defines.v"
`endif
//
module ddr2_phy_alt_mem_phy_mux (
phy_clk_1x,
reset_phy_clk_1x_n,
// MUX Outputs to controller :
ctl_address,
ctl_read_req,
ctl_wdata,
ctl_write_req,
ctl_size,
ctl_be,
ctl_refresh_req,
ctl_burstbegin,
// Controller inputs to the MUX :
ctl_ready,
ctl_wdata_req,
ctl_rdata,
ctl_rdata_valid,
ctl_refresh_ack,
ctl_init_done,
// MUX Select line :
ctl_usr_mode_rdy,
// MUX inputs from local interface :
local_address,
local_read_req,
local_wdata,
local_write_req,
local_size,
local_be,
local_refresh_req,
local_burstbegin,
// MUX outputs to sequencer :
mux_seq_controller_ready,
mux_seq_wdata_req,
// MUX inputs from sequencer :
seq_mux_address,
seq_mux_read_req,
seq_mux_wdata,
seq_mux_write_req,
seq_mux_size,
seq_mux_be,
seq_mux_refresh_req,
seq_mux_burstbegin,
// Changes made to accomodate new ports for self refresh/power-down & Auto precharge in HP Controller (User to PHY)
local_autopch_req,
local_powerdn_req,
local_self_rfsh_req,
local_powerdn_ack,
local_self_rfsh_ack,
// Changes made to accomodate new ports for self refresh/power-down & Auto precharge in HP Controller (PHY to Controller)
ctl_autopch_req,
ctl_powerdn_req,
ctl_self_rfsh_req,
ctl_powerdn_ack,
ctl_self_rfsh_ack,
// Also MUX some signals from the controller to the local interface :
local_ready,
local_wdata_req,
local_init_done,
local_rdata,
local_rdata_valid,
local_refresh_ack
);
parameter LOCAL_IF_AWIDTH = 26;
parameter LOCAL_IF_DWIDTH = 256;
parameter LOCAL_BURST_LEN_BITS = 1;
parameter MEM_IF_DQ_PER_DQS = 8;
parameter MEM_IF_DWIDTH = 64;
input wire phy_clk_1x;
input wire reset_phy_clk_1x_n;
// MUX Select line :
input wire ctl_usr_mode_rdy;
// MUX inputs from local interface :
input wire [LOCAL_IF_AWIDTH - 1 : 0] local_address;
input wire local_read_req;
input wire [LOCAL_IF_DWIDTH - 1 : 0] local_wdata;
input wire local_write_req;
input wire [LOCAL_BURST_LEN_BITS - 1 : 0] local_size;
input wire [(LOCAL_IF_DWIDTH/8) - 1 : 0] local_be;
input wire local_refresh_req;
input wire local_burstbegin;
// MUX inputs from sequencer :
input wire [LOCAL_IF_AWIDTH - 1 : 0] seq_mux_address;
input wire seq_mux_read_req;
input wire [LOCAL_IF_DWIDTH - 1 : 0] seq_mux_wdata;
input wire seq_mux_write_req;
input wire [LOCAL_BURST_LEN_BITS - 1 : 0] seq_mux_size;
input wire [(LOCAL_IF_DWIDTH/8) - 1:0] seq_mux_be;
input wire seq_mux_refresh_req;
input wire seq_mux_burstbegin;
// MUX Outputs to controller :
output reg [LOCAL_IF_AWIDTH - 1 : 0] ctl_address;
output reg ctl_read_req;
output reg [LOCAL_IF_DWIDTH - 1 : 0] ctl_wdata;
output reg ctl_write_req;
output reg [LOCAL_BURST_LEN_BITS - 1 : 0] ctl_size;
output reg [(LOCAL_IF_DWIDTH/8) - 1:0] ctl_be;
output reg ctl_refresh_req;
output reg ctl_burstbegin;
// The "ready" input from the controller shall be passed to either the
// local interface if in user mode, or the sequencer :
input wire ctl_ready;
output reg local_ready;
output reg mux_seq_controller_ready;
// The controller's "wdata req" output is similarly passed to either
// the local interface if in user mode, or the sequencer :
input wire ctl_wdata_req;
output reg local_wdata_req;
output reg mux_seq_wdata_req;
input wire ctl_init_done;
output reg local_init_done;
input wire [LOCAL_IF_DWIDTH - 1 : 0] ctl_rdata;
output reg [LOCAL_IF_DWIDTH - 1 : 0] local_rdata;
input wire ctl_rdata_valid;
output reg local_rdata_valid;
input wire ctl_refresh_ack;
output reg local_refresh_ack;
//-> Changes made to accomodate new ports for self refresh/power-down & Auto precharge in HP Controller (User to PHY)
input wire local_autopch_req;
input wire local_powerdn_req;
input wire local_self_rfsh_req;
output reg local_powerdn_ack;
output reg local_self_rfsh_ack;
// --> Changes made to accomodate new ports for self refresh/power-down & Auto precharge in HP Controller (PHY to Controller)
output reg ctl_autopch_req;
output reg ctl_powerdn_req;
output reg ctl_self_rfsh_req;
input wire ctl_powerdn_ack;
input wire ctl_self_rfsh_ack;
wire local_burstbegin_held;
reg burstbegin_hold;
always @(posedge phy_clk_1x or negedge reset_phy_clk_1x_n)
begin
if (reset_phy_clk_1x_n == 1'b0)
burstbegin_hold <= 1'b0;
else
begin
if (local_ready == 1'b0 && (local_write_req == 1'b1 || local_read_req == 1'b1) && local_burstbegin == 1'b1)
burstbegin_hold <= 1'b1;
else if (local_ready == 1'b1 && (local_write_req == 1'b1 || local_read_req == 1'b1))
burstbegin_hold <= 1'b0;
end
end
// Gate the local burstbegin signal with the held version :
assign local_burstbegin_held = burstbegin_hold || local_burstbegin;
always @*
begin
if (ctl_usr_mode_rdy == 1'b1)
begin
// Pass local interface signals to the controller if ready :
ctl_address = local_address;
ctl_read_req = local_read_req;
ctl_wdata = local_wdata;
ctl_write_req = local_write_req;
ctl_size = local_size;
ctl_be = local_be;
ctl_refresh_req = local_refresh_req;
ctl_burstbegin = local_burstbegin_held;
// If in user mode, pass on the controller's ready
// and wdata request signals to the local interface :
local_ready = ctl_ready;
local_wdata_req = ctl_wdata_req;
local_init_done = ctl_init_done;
local_rdata = ctl_rdata;
local_rdata_valid = ctl_rdata_valid;
local_refresh_ack = ctl_refresh_ack;
// Whilst indicate to the sequencer that the controller is busy :
mux_seq_controller_ready = 1'b0;
mux_seq_wdata_req = 1'b0;
// Autopch_req & Local_power_req changes
ctl_autopch_req = local_autopch_req;
ctl_powerdn_req = local_powerdn_req;
ctl_self_rfsh_req = local_self_rfsh_req;
local_powerdn_ack = ctl_powerdn_ack;
local_self_rfsh_ack = ctl_self_rfsh_ack;
end
else
begin
// Pass local interface signals to the sequencer if not in user mode :
// NB. The controller will have more address bits than the sequencer, so
// these are zero padded :
ctl_address = seq_mux_address;
ctl_read_req = seq_mux_read_req;
ctl_wdata = seq_mux_wdata;
ctl_write_req = seq_mux_write_req;
ctl_size = seq_mux_size; // NB. Should be tied-off when the mux is instanced
ctl_be = seq_mux_be; // NB. Should be tied-off when the mux is instanced
ctl_refresh_req = local_refresh_req; // NB. Should be tied-off when the mux is instanced
ctl_burstbegin = seq_mux_burstbegin; // NB. Should be tied-off when the mux is instanced
// Indicate to the local IF that the controller is busy :
local_ready = 1'b0;
local_wdata_req = 1'b0;
local_init_done = 1'b0;
local_rdata = {LOCAL_IF_DWIDTH{1'b0}};
local_rdata_valid = 1'b0;
local_refresh_ack = ctl_refresh_ack;
// If not in user mode, pass on the controller's ready
// and wdata request signals to the sequencer :
mux_seq_controller_ready = ctl_ready;
mux_seq_wdata_req = ctl_wdata_req;
// Autopch_req & Local_power_req changes
ctl_autopch_req = 1'b0;
ctl_powerdn_req = 1'b0;
ctl_self_rfsh_req = local_self_rfsh_req;
local_powerdn_ack = 1'b0;
local_self_rfsh_ack = ctl_self_rfsh_ack;
end
end
endmodule
//
`default_nettype none
`ifdef ALT_MEM_PHY_DEFINES
`else
`include "alt_mem_phy_defines.v"
`endif
/* -----------------------------------------------------------------------------
// module description
---------------------------------------------------------------------------- */
//
module ddr2_phy_alt_mem_phy_mimic(
//Inputs
//Clocks
measure_clk, // full rate clock from PLL
mimic_data_in, // Input against which the VT variations
// are tracked (e.g. memory clock)
// Active low reset
reset_measure_clk_n,
//Indicates that the mimic calibration sequence can start
seq_mmc_start, // from sequencer
//Outputs
mmc_seq_done, // mimic calibration finished for the current PLL phase
mmc_seq_value // result value of the mimic calibration
);
input wire measure_clk;
input wire mimic_data_in;
input wire reset_measure_clk_n;
input wire seq_mmc_start;
output wire mmc_seq_done;
output wire mmc_seq_value;
function integer clogb2;
input [31:0] value;
for (clogb2=0; value>0; clogb2=clogb2+1)
value = value >> 1;
endfunction // clogb2
// Parameters
parameter NUM_MIMIC_SAMPLE_CYCLES = 6;
parameter SHIFT_REG_COUNTER_WIDTH = clogb2(NUM_MIMIC_SAMPLE_CYCLES);
reg [`MIMIC_FSM_WIDTH-1:0] mimic_state;
reg [2:0] seq_mmc_start_metastable;
wire start_edge_detected;
(* altera_attribute=" -name fast_input_register OFF"*) reg [1:0] mimic_data_in_metastable;
wire mimic_data_in_sample;
wire shift_reg_data_out_all_ones;
reg mimic_done_out;
reg mimic_value_captured;
reg [SHIFT_REG_COUNTER_WIDTH : 0] shift_reg_counter;
reg shift_reg_enable;
wire shift_reg_data_in;
reg shift_reg_s_clr;
wire shift_reg_a_clr;
reg [NUM_MIMIC_SAMPLE_CYCLES -1 : 0] shift_reg_data_out;
// shift register which contains the sampled data
always @(posedge measure_clk or posedge shift_reg_a_clr)
begin
if (shift_reg_a_clr == 1'b1)
begin
shift_reg_data_out <= {NUM_MIMIC_SAMPLE_CYCLES{1'b0}};
end
else
begin
if (shift_reg_s_clr == 1'b1)
begin
shift_reg_data_out <= {NUM_MIMIC_SAMPLE_CYCLES{1'b0}};
end
else if (shift_reg_enable == 1'b1)
begin
shift_reg_data_out <= {(shift_reg_data_out[NUM_MIMIC_SAMPLE_CYCLES -2 : 0]), shift_reg_data_in};
end
end
end
// Metastable-harden mimic_start :
always @(posedge measure_clk or negedge reset_measure_clk_n)
begin
if (reset_measure_clk_n == 1'b0)
begin
seq_mmc_start_metastable <= 0;
end
else
begin
seq_mmc_start_metastable[0] <= seq_mmc_start;
seq_mmc_start_metastable[1] <= seq_mmc_start_metastable[0];
seq_mmc_start_metastable[2] <= seq_mmc_start_metastable[1];
end
end
assign start_edge_detected = seq_mmc_start_metastable[1]
&& !seq_mmc_start_metastable[2];
// Metastable-harden mimic_data_in :
always @(posedge measure_clk or negedge reset_measure_clk_n)
begin
if (reset_measure_clk_n == 1'b0)
begin
mimic_data_in_metastable <= 0;
end
//some mimic paths configurations have another flop inside the wysiwyg ioe
else
begin
mimic_data_in_metastable[0] <= mimic_data_in;
mimic_data_in_metastable[1] <= mimic_data_in_metastable[0];
end
end
assign mimic_data_in_sample = mimic_data_in_metastable[1];
// Main FSM :
always @(posedge measure_clk or negedge reset_measure_clk_n )
begin
if (reset_measure_clk_n == 1'b0)
begin
mimic_state <= `MIMIC_IDLE;
mimic_done_out <= 1'b0;
mimic_value_captured <= 1'b0;
shift_reg_counter <= 0;
shift_reg_enable <= 1'b0;
shift_reg_s_clr <= 1'b0;
end
else
begin
case (mimic_state)
`MIMIC_IDLE : begin
shift_reg_counter <= 0;
mimic_done_out <= 1'b0;
shift_reg_s_clr <= 1'b1;
shift_reg_enable <= 1'b1;
if (start_edge_detected == 1'b1)
begin
mimic_state <= `MIMIC_SAMPLE;
shift_reg_counter <= shift_reg_counter + 1'b1;
shift_reg_s_clr <= 1'b0;
end
else
begin
mimic_state <= `MIMIC_IDLE;
end
end // case: MIMIC_IDLE
`MIMIC_SAMPLE : begin
shift_reg_counter <= shift_reg_counter + 1'b1;
if (shift_reg_counter == NUM_MIMIC_SAMPLE_CYCLES + 1)
begin
mimic_done_out <= 1'b1;
mimic_value_captured <= shift_reg_data_out_all_ones; //captured only here
shift_reg_enable <= 1'b0;
shift_reg_counter <= shift_reg_counter;
mimic_state <= `MIMIC_SEND;
end
end // case: MIMIC_SAMPLE
`MIMIC_SEND : begin
mimic_done_out <= 1'b1; //redundant statement, here just for readibility
mimic_state <= `MIMIC_SEND1;
/* mimic_value_captured will not change during MIMIC_SEND
it will change next time mimic_done_out is asserted
mimic_done_out will be reset during MIMIC_IDLE
the purpose of the current state is to add one clock cycle
mimic_done_out will be active for 2 measure_clk clock cycles, i.e
the pulses duration will be just one sequencer clock cycle
(which is half rate) */
end // case: MIMIC_SEND
// MIMIC_SEND1 and MIMIC_SEND2 extend the mimic_done_out signal by another 2 measure_clk_2x cycles
// so it is a total of 4 measure clocks long (ie 2 half-rate clock cycles long in total)
`MIMIC_SEND1 : begin
mimic_done_out <= 1'b1; //redundant statement, here just for readibility
mimic_state <= `MIMIC_SEND2;
end
`MIMIC_SEND2 : begin
mimic_done_out <= 1'b1; //redundant statement, here just for readibility
mimic_state <= `MIMIC_IDLE;
end
default : begin
mimic_state <= `MIMIC_IDLE;
end
endcase
end
end
assign shift_reg_data_out_all_ones = (( & shift_reg_data_out) == 1'b1) ? 1'b1
: 1'b0;
// Shift Register assignments
assign shift_reg_data_in = mimic_data_in_sample;
assign shift_reg_a_clr = !reset_measure_clk_n;
// Output assignments
assign mmc_seq_done = mimic_done_out;
assign mmc_seq_value = mimic_value_captured;
endmodule
`default_nettype wire
//
/* -----------------------------------------------------------------------------
// module description
----------------------------------------------------------------------------- */
//
module ddr2_phy_alt_mem_phy_mimic_debug(
// Inputs
// Clocks
measure_clk, // full rate clock from PLL
// Active low reset
reset_measure_clk_n,
mimic_recapture_debug_data, // from user board button
mmc_seq_done, // mimic calibration finished for the current PLL phase
mmc_seq_value // result value of the mimic calibration
);
// Parameters
parameter NUM_DEBUG_SAMPLES_TO_STORE = 4096; // can range from 4096 to 524288
parameter PLL_STEPS_PER_CYCLE = 24; // can range from 16 to 48
input wire measure_clk;
input wire reset_measure_clk_n;
input wire mimic_recapture_debug_data;
input wire mmc_seq_done;
input wire mmc_seq_value;
function integer clogb2;
input [31:0] value;
for (clogb2=0; value>0; clogb2=clogb2+1)
value = value >> 1;
endfunction // clogb2
parameter RAM_WR_ADDRESS_WIDTH = clogb2(NUM_DEBUG_SAMPLES_TO_STORE - 1); // can range from 12 to 19
reg s_clr_ram_wr_address_count;
reg [(clogb2(PLL_STEPS_PER_CYCLE)-1) : 0] mimic_sample_count;
reg [RAM_WR_ADDRESS_WIDTH-1 : 0 ] ram_write_address;
wire ram_wr_enable;
wire [0:0] debug_ram_data;
reg clear_ram_wr_enable;
reg [1:0] mimic_recapture_debug_data_metastable;
wire mimic_done_in_dbg; // for internal use, just 1 measure_clk cycles long
reg mmc_seq_done_r;
// generate mimic_done_in_debug : a single clock wide pulse based on the rising edge of mmc_seq_done:
always @ (posedge measure_clk or negedge reset_measure_clk_n)
begin
if (reset_measure_clk_n == 1'b0) // asynchronous reset (active low)
begin
mmc_seq_done_r <= 1'b0;
end
else
begin
mmc_seq_done_r <= mmc_seq_done;
end
end
assign mimic_done_in_dbg = mmc_seq_done && !mmc_seq_done_r;
assign ram_wr_enable = mimic_done_in_dbg && !clear_ram_wr_enable;
assign debug_ram_data[0] = mmc_seq_value;
altsyncram #(
.clock_enable_input_a ( "BYPASS"),
.clock_enable_output_a ( "BYPASS"),
.intended_device_family ( "Stratix II"),
.lpm_hint ( "ENABLE_RUNTIME_MOD=YES, INSTANCE_NAME=MRAM"),
.lpm_type ( "altsyncram"),
.maximum_depth ( 4096),
.numwords_a ( 4096),
.operation_mode ( "SINGLE_PORT"),
.outdata_aclr_a ( "NONE"),
.outdata_reg_a ( "UNREGISTERED"),
.power_up_uninitialized ( "FALSE"),
.widthad_a ( 12),
.width_a ( 1),
.width_byteena_a ( 1)
)
altsyncram_component (
.wren_a ( ram_wr_enable),
.clock0 ( measure_clk),
.address_a ( ram_write_address),
.data_a ( debug_ram_data),
.q_a ( )
);
// Metastability_mimic_recapture_debug_data :
always @(posedge measure_clk or negedge reset_measure_clk_n)
begin
if (reset_measure_clk_n == 1'b0)
begin
mimic_recapture_debug_data_metastable <= 2'b0;
end
else
begin
mimic_recapture_debug_data_metastable[0] <= mimic_recapture_debug_data;
mimic_recapture_debug_data_metastable[1] <= mimic_recapture_debug_data_metastable[0];
end
end
//mimic_sample_counter :
always @(posedge measure_clk or negedge reset_measure_clk_n)
begin
if (reset_measure_clk_n == 1'b0)
begin
mimic_sample_count <= 0; // (others => '0');
end
else
begin
if (mimic_done_in_dbg == 1'b1)
begin
mimic_sample_count <= mimic_sample_count + 1'b1;
if (mimic_sample_count == PLL_STEPS_PER_CYCLE-1)
begin
mimic_sample_count <= 0; //(others => '0');
end
end
end
end
//RAMWrAddressCounter :
always @(posedge measure_clk or negedge reset_measure_clk_n)
begin
if (reset_measure_clk_n == 1'b0)
begin
ram_write_address <= 0; //(others => '0');
clear_ram_wr_enable <= 1'b0;
end
else
begin
if (s_clr_ram_wr_address_count == 1'b1) // then --Active high synchronous reset
begin
ram_write_address <= 0; //(others => '0');
clear_ram_wr_enable <= 1'b1;
end
else
begin
clear_ram_wr_enable <= 1'b0;
if (mimic_done_in_dbg == 1'b1)
begin
if (ram_write_address != NUM_DEBUG_SAMPLES_TO_STORE-1)
begin
ram_write_address <= ram_write_address + 1'b1;
end
else
begin
clear_ram_wr_enable <= 1'b1;
end
end
end
end
end
//ClearRAMWrAddressCounter :
always @(posedge measure_clk or negedge reset_measure_clk_n)
begin
if (reset_measure_clk_n == 1'b0)
begin
s_clr_ram_wr_address_count <= 1'b0;
end
else
begin
if (mimic_recapture_debug_data_metastable[1] == 1'b1)
begin
s_clr_ram_wr_address_count <= 1'b1;
end
else if (mimic_sample_count == 0)
begin
s_clr_ram_wr_address_count <= 1'b0;
end
end
end
endmodule
//
`ifdef ALT_MEM_PHY_DEFINES
`else
`include "alt_mem_phy_defines.v"
`endif
//
module ddr2_phy_alt_mem_phy_reset_pipe (
input wire clock,
input wire pre_clear,
output wire reset_out
);
parameter PIPE_DEPTH = 4;
// Declare pipeline registers.
reg [PIPE_DEPTH - 1 : 0] ams_pipe;
integer i;
// begin : RESET_PIPE
always @(posedge clock or negedge pre_clear)
begin
if (pre_clear == 1'b0)
begin
ams_pipe <= 0;
end
else
begin
for (i=0; i< PIPE_DEPTH; i = i + 1)
begin
if (i==0)
ams_pipe[i] <= 1'b1;
else
ams_pipe[i] <= ams_pipe[i-1];
end
end // if-else
end // always
// end
assign reset_out = ams_pipe[PIPE_DEPTH-1];
endmodule
|
//////////////////////////////////////////////////////////////////////
//// ////
//// ROM ////
//// ////
//// Author(s): ////
//// - Michael Unneback ([email protected]) ////
//// - Julius Baxter ([email protected]) ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2009 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
module rom
#(parameter addr_width = 5,
parameter b3_burst = 0)
(
input wb_clk,
input wb_rst,
input [(addr_width+2)-1:2] wb_adr_i,
input wb_stb_i,
input wb_cyc_i,
input [2:0] wb_cti_i,
input [1:0] wb_bte_i,
output reg [31:0] wb_dat_o,
output reg wb_ack_o);
reg [addr_width-1:0] adr;
always @ (posedge wb_clk or posedge wb_rst)
if (wb_rst)
wb_dat_o <= 32'h15000000;
else
case (adr)
// Zero r0 and endless loop
0 : wb_dat_o <= 32'h18000000;
1 : wb_dat_o <= 32'hA8200000;
2 : wb_dat_o <= 32'hA8C00100;
3 : wb_dat_o <= 32'h00000000;
4 : wb_dat_o <= 32'h15000000;
/*
// Zero r0 and jump to 0x00000100
0 : wb_dat_o <= 32'h18000000;
1 : wb_dat_o <= 32'hA8200000;
2 : wb_dat_o <= 32'hA8C00100;
3 : wb_dat_o <= 32'h44003000;
4 : wb_dat_o <= 32'h15000000;
*/
default:
wb_dat_o <= 32'h00000000;
endcase // case (wb_adr_i)
generate
if(b3_burst) begin : gen_b3_burst
reg wb_stb_i_r;
reg new_access_r;
reg burst_r;
wire burst = wb_cyc_i & (!(wb_cti_i == 3'b000)) & (!(wb_cti_i == 3'b111));
wire new_access = (wb_stb_i & !wb_stb_i_r);
wire new_burst = (burst & !burst_r);
always @(posedge wb_clk) begin
new_access_r <= new_access;
burst_r <= burst;
wb_stb_i_r <= wb_stb_i;
end
always @(posedge wb_clk)
if (wb_rst)
adr <= 0;
else if (new_access)
// New access, register address, ack a cycle later
adr <= wb_adr_i[(addr_width+2)-1:2];
else if (burst) begin
if (wb_cti_i == 3'b010)
case (wb_bte_i)
2'b00: adr <= adr + 1;
2'b01: adr[1:0] <= adr[1:0] + 1;
2'b10: adr[2:0] <= adr[2:0] + 1;
2'b11: adr[3:0] <= adr[3:0] + 1;
endcase // case (wb_bte_i)
else
adr <= wb_adr_i[(addr_width+2)-1:2];
end // if (burst)
always @(posedge wb_clk)
if (wb_rst)
wb_ack_o <= 0;
else if (wb_ack_o & (!burst | (wb_cti_i == 3'b111)))
wb_ack_o <= 0;
else if (wb_stb_i & ((!burst & !new_access & new_access_r) | (burst & burst_r)))
wb_ack_o <= 1;
else
wb_ack_o <= 0;
end else begin
always @(wb_adr_i)
adr <= wb_adr_i;
always @ (posedge wb_clk or posedge wb_rst)
if (wb_rst)
wb_ack_o <= 1'b0;
else
wb_ack_o <= wb_stb_i & wb_cyc_i & !wb_ack_o;
end
endgenerate
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__UDP_MUX_4TO2_TB_V
`define SKY130_FD_SC_HS__UDP_MUX_4TO2_TB_V
/**
* udp_mux_4to2: Four to one multiplexer with 2 select controls
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__udp_mux_4to2.v"
module top();
// Inputs are registered
reg A0;
reg A1;
reg A2;
reg A3;
reg S0;
reg S1;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A0 = 1'bX;
A1 = 1'bX;
A2 = 1'bX;
A3 = 1'bX;
S0 = 1'bX;
S1 = 1'bX;
#20 A0 = 1'b0;
#40 A1 = 1'b0;
#60 A2 = 1'b0;
#80 A3 = 1'b0;
#100 S0 = 1'b0;
#120 S1 = 1'b0;
#140 A0 = 1'b1;
#160 A1 = 1'b1;
#180 A2 = 1'b1;
#200 A3 = 1'b1;
#220 S0 = 1'b1;
#240 S1 = 1'b1;
#260 A0 = 1'b0;
#280 A1 = 1'b0;
#300 A2 = 1'b0;
#320 A3 = 1'b0;
#340 S0 = 1'b0;
#360 S1 = 1'b0;
#380 S1 = 1'b1;
#400 S0 = 1'b1;
#420 A3 = 1'b1;
#440 A2 = 1'b1;
#460 A1 = 1'b1;
#480 A0 = 1'b1;
#500 S1 = 1'bx;
#520 S0 = 1'bx;
#540 A3 = 1'bx;
#560 A2 = 1'bx;
#580 A1 = 1'bx;
#600 A0 = 1'bx;
end
sky130_fd_sc_hs__udp_mux_4to2 dut (.A0(A0), .A1(A1), .A2(A2), .A3(A3), .S0(S0), .S1(S1), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__UDP_MUX_4TO2_TB_V
|
//-----------------------------------------------------------------
// RISC-V Top
// V0.6
// Ultra-Embedded.com
// Copyright 2014-2019
//
// [email protected]
//
// License: BSD
//-----------------------------------------------------------------
//
// Copyright (c) 2014, Ultra-Embedded.com
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer
// in the documentation and/or other materials provided with the
// distribution.
// - Neither the name of the author nor the names of its contributors
// may be used to endorse or promote products derived from this
// software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
// SUCH DAMAGE.
//-----------------------------------------------------------------
//-----------------------------------------------------------------
// Generated File
//-----------------------------------------------------------------
module dport_mux
//-----------------------------------------------------------------
// Params
//-----------------------------------------------------------------
#(
parameter TCM_MEM_BASE = 0
)
//-----------------------------------------------------------------
// Ports
//-----------------------------------------------------------------
(
// Inputs
input clk_i
,input rst_i
,input [ 31:0] mem_addr_i
,input [ 31:0] mem_data_wr_i
,input mem_rd_i
,input [ 3:0] mem_wr_i
,input mem_cacheable_i
,input [ 10:0] mem_req_tag_i
,input mem_invalidate_i
,input mem_writeback_i
,input mem_flush_i
,input [ 31:0] mem_tcm_data_rd_i
,input mem_tcm_accept_i
,input mem_tcm_ack_i
,input mem_tcm_error_i
,input [ 10:0] mem_tcm_resp_tag_i
,input [ 31:0] mem_ext_data_rd_i
,input mem_ext_accept_i
,input mem_ext_ack_i
,input mem_ext_error_i
,input [ 10:0] mem_ext_resp_tag_i
// Outputs
,output [ 31:0] mem_data_rd_o
,output mem_accept_o
,output mem_ack_o
,output mem_error_o
,output [ 10:0] mem_resp_tag_o
,output [ 31:0] mem_tcm_addr_o
,output [ 31:0] mem_tcm_data_wr_o
,output mem_tcm_rd_o
,output [ 3:0] mem_tcm_wr_o
,output mem_tcm_cacheable_o
,output [ 10:0] mem_tcm_req_tag_o
,output mem_tcm_invalidate_o
,output mem_tcm_writeback_o
,output mem_tcm_flush_o
,output [ 31:0] mem_ext_addr_o
,output [ 31:0] mem_ext_data_wr_o
,output mem_ext_rd_o
,output [ 3:0] mem_ext_wr_o
,output mem_ext_cacheable_o
,output [ 10:0] mem_ext_req_tag_o
,output mem_ext_invalidate_o
,output mem_ext_writeback_o
,output mem_ext_flush_o
);
//-----------------------------------------------------------------
// Dcache_if mux
//-----------------------------------------------------------------
wire hold_w;
/* verilator lint_off UNSIGNED */
wire tcm_access_w = (mem_addr_i >= TCM_MEM_BASE && mem_addr_i < (TCM_MEM_BASE + 32'd65536));
/* verilator lint_on UNSIGNED */
reg tcm_access_q;
reg [4:0] pending_q;
assign mem_tcm_addr_o = mem_addr_i;
assign mem_tcm_data_wr_o = mem_data_wr_i;
assign mem_tcm_rd_o = (tcm_access_w & ~hold_w) ? mem_rd_i : 1'b0;
assign mem_tcm_wr_o = (tcm_access_w & ~hold_w) ? mem_wr_i : 4'b0;
assign mem_tcm_cacheable_o = mem_cacheable_i;
assign mem_tcm_req_tag_o = mem_req_tag_i;
assign mem_tcm_invalidate_o = (tcm_access_w & ~hold_w) ? mem_invalidate_i : 1'b0;
assign mem_tcm_writeback_o = (tcm_access_w & ~hold_w) ? mem_writeback_i : 1'b0;
assign mem_tcm_flush_o = (tcm_access_w & ~hold_w) ? mem_flush_i : 1'b0;
assign mem_ext_addr_o = mem_addr_i;
assign mem_ext_data_wr_o = mem_data_wr_i;
assign mem_ext_rd_o = (~tcm_access_w & ~hold_w) ? mem_rd_i : 1'b0;
assign mem_ext_wr_o = (~tcm_access_w & ~hold_w) ? mem_wr_i : 4'b0;
assign mem_ext_cacheable_o = mem_cacheable_i;
assign mem_ext_req_tag_o = mem_req_tag_i;
assign mem_ext_invalidate_o = (~tcm_access_w & ~hold_w) ? mem_invalidate_i : 1'b0;
assign mem_ext_writeback_o = (~tcm_access_w & ~hold_w) ? mem_writeback_i : 1'b0;
assign mem_ext_flush_o = (~tcm_access_w & ~hold_w) ? mem_flush_i : 1'b0;
assign mem_accept_o =(tcm_access_w ? mem_tcm_accept_i : mem_ext_accept_i) & !hold_w;
assign mem_data_rd_o = tcm_access_q ? mem_tcm_data_rd_i : mem_ext_data_rd_i;
assign mem_ack_o = tcm_access_q ? mem_tcm_ack_i : mem_ext_ack_i;
assign mem_error_o = tcm_access_q ? mem_tcm_error_i : mem_ext_error_i;
assign mem_resp_tag_o = tcm_access_q ? mem_tcm_resp_tag_i : mem_ext_resp_tag_i;
wire request_w = mem_rd_i || mem_wr_i != 4'b0 || mem_flush_i || mem_invalidate_i || mem_writeback_i;
reg [4:0] pending_r;
always @ *
begin
pending_r = pending_q;
if ((request_w && mem_accept_o) && !mem_ack_o)
pending_r = pending_r + 5'd1;
else if (!(request_w && mem_accept_o) && mem_ack_o)
pending_r = pending_r - 5'd1;
end
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
pending_q <= 5'b0;
else
pending_q <= pending_r;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
tcm_access_q <= 1'b0;
else if (request_w && mem_accept_o)
tcm_access_q <= tcm_access_w;
assign hold_w = (|pending_q) && (tcm_access_q != tcm_access_w);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A2111O_TB_V
`define SKY130_FD_SC_HD__A2111O_TB_V
/**
* a2111o: 2-input AND into first input of 4-input OR.
*
* X = ((A1 & A2) | B1 | C1 | D1)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__a2111o.v"
module top();
// Inputs are registered
reg A1;
reg A2;
reg B1;
reg C1;
reg D1;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A1 = 1'bX;
A2 = 1'bX;
B1 = 1'bX;
C1 = 1'bX;
D1 = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A1 = 1'b0;
#40 A2 = 1'b0;
#60 B1 = 1'b0;
#80 C1 = 1'b0;
#100 D1 = 1'b0;
#120 VGND = 1'b0;
#140 VNB = 1'b0;
#160 VPB = 1'b0;
#180 VPWR = 1'b0;
#200 A1 = 1'b1;
#220 A2 = 1'b1;
#240 B1 = 1'b1;
#260 C1 = 1'b1;
#280 D1 = 1'b1;
#300 VGND = 1'b1;
#320 VNB = 1'b1;
#340 VPB = 1'b1;
#360 VPWR = 1'b1;
#380 A1 = 1'b0;
#400 A2 = 1'b0;
#420 B1 = 1'b0;
#440 C1 = 1'b0;
#460 D1 = 1'b0;
#480 VGND = 1'b0;
#500 VNB = 1'b0;
#520 VPB = 1'b0;
#540 VPWR = 1'b0;
#560 VPWR = 1'b1;
#580 VPB = 1'b1;
#600 VNB = 1'b1;
#620 VGND = 1'b1;
#640 D1 = 1'b1;
#660 C1 = 1'b1;
#680 B1 = 1'b1;
#700 A2 = 1'b1;
#720 A1 = 1'b1;
#740 VPWR = 1'bx;
#760 VPB = 1'bx;
#780 VNB = 1'bx;
#800 VGND = 1'bx;
#820 D1 = 1'bx;
#840 C1 = 1'bx;
#860 B1 = 1'bx;
#880 A2 = 1'bx;
#900 A1 = 1'bx;
end
sky130_fd_sc_hd__a2111o dut (.A1(A1), .A2(A2), .B1(B1), .C1(C1), .D1(D1), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__A2111O_TB_V
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 21:14:53 10/20/2015
// Design Name: GateLevel_PE
// Module Name: E:/IIIT-Delhi/Semester III/Courses/ELD/Assignments/PriorityEncoder/PE_test.v
// Project Name: PriorityEncoder
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: GateLevel_PE
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module PE_test;
// Inputs
reg in2;
reg in1;
reg in0;
// Outputs
wire out1;
wire out0;
// Instantiate the Unit Under Test (UUT)
Behavioral_PE uut (
.out1(out1),
.out0(out0),
.in2(in2),
.in1(in1),
.in0(in0)
);
initial begin
// Initialize Inputs
in2 = 0;
in1 = 0;
in0 = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
in2 = 0; in1 = 0; in0 = 0;
#20;
in2 = 0; in1 = 0; in0 = 1;
#20;
in2 = 0; in1 = 1; in0 = 0;
#20;
in2 = 0; in1 = 1; in0 = 1;
#20;
in2 = 1; in1 = 0; in0 = 0;
#20;
in2 = 1; in1 = 0; in0 = 1;
#20;
in2 = 1; in1 = 1; in0 = 0;
#20;
in2 = 1; in1 = 1; in0 = 1;
#20;
end
endmodule
|
// Synchronous FIFO. 1024 x 32 bit words.
//
module fifo (
clk,
rstp,
din,
writep,
readp,
dout,
emptyp,
fullp);
input clk;
input rstp;
input [31:0] din;
input readp;
input writep;
output [31:0] dout;
output emptyp;
output fullp;
// Defines sizes in terms of bits.
//
parameter DEPTH = 1024; // 2 bits, e.g. 4 words in the FIFO.
parameter MAX_COUNT = 10'b1111111111; // topmost address in FIFO.
reg emptyp;
reg fullp;
// Registered output.
reg [31:0] dout;
// Define the FIFO pointers. A FIFO is essentially a circular queue.
//
reg [(DEPTH-1):0] tail;
reg [(DEPTH-1):0] head;
// Define the FIFO counter. Counts the number of entries in the FIFO which
// is how we figure out things like Empty and Full.
//
reg [(DEPTH-1):0] count;
// Define our regsiter bank. This is actually synthesizable!
//
reg [31:0] fifomem[0:MAX_COUNT];
// Dout is registered and gets the value that tail points to RIGHT NOW.
//
always @(posedge clk) begin
if (rstp == 1) begin
dout <= 16'h0000;
end
else begin
dout <= fifomem[tail];
end
end
// Update FIFO memory.
always @(posedge clk) begin
if (rstp == 1'b0 && writep == 1'b1 && fullp == 1'b0) begin
fifomem[head] <= din;
end
end
// Update the head register.
//
always @(posedge clk) begin
if (rstp == 1'b1) begin
head <= 2'b00;
end
else begin
if (writep == 1'b1 && fullp == 1'b0) begin
// WRITE
head <= head + 1;
end
end
end
// Update the tail register.
//
always @(posedge clk) begin
if (rstp == 1'b1) begin
tail <= 2'b00;
end
else begin
if (readp == 1'b1 && emptyp == 1'b0) begin
// READ
tail <= tail + 1;
end
end
end
// Update the count regsiter.
//
always @(posedge clk) begin
if (rstp == 1'b1) begin
count <= 2'b00;
end
else begin
case ({readp, writep})
2'b00: count <= count;
2'b01:
// WRITE
if (count != MAX_COUNT)
count <= count + 1;
2'b10:
// READ
if (count != 2'b00)
count <= count - 1;
2'b11:
// Concurrent read and write.. no change in count
count <= count;
endcase
end
end
// *** Update the flags
//
// First, update the empty flag.
//
always @(count) begin
if (count == 2'b00)
emptyp <= 1'b1;
else
emptyp <= 1'b0;
end
// Update the full flag
//
always @(count) begin
if (count == MAX_COUNT)
fullp <= 1'b1;
else
fullp <= 1'b0;
end
endmodule |
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2004 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc; initial cyc=1;
reg [41:0] aaa;
wire [41:0] bbb;
// verilator public_module
wire [41:0] z_0;
wire [41:0] z_1;
wide w_0(
.xxx( { {40{1'b0}},2'b11 } ),
.yyy( aaa[1:0] ),
.zzz( z_0 )
);
wide w_1(
.xxx( aaa ),
.yyy( 2'b10 ),
.zzz( z_1 )
);
assign bbb= z_0 + z_1;
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
if (cyc==1) begin
aaa <= 42'b01;
end
if (cyc==2) begin
aaa <= 42'b10;
if (z_0 != 42'h4) $stop;
if (z_1 != 42'h3) $stop;
end
if (cyc==3) begin
if (z_0 != 42'h5) $stop;
if (z_1 != 42'h4) $stop;
end
if (cyc==4) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
module wide (
input [41:0] xxx,
input [1:0] yyy,
output [41:0] zzz
);
// verilator public_module
assign zzz = xxx+ { {40{1'b0}},yyy };
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2011 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc = 0;
reg [63:0] crc;
reg [63:0] sum;
wire [3:0] drv_a = crc[3:0];
wire [3:0] drv_b = crc[7:4];
wire [3:0] drv_e = crc[19:16];
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [8:0] match1; // From test1 of Test1.v
wire [8:0] match2; // From test2 of Test2.v
// End of automatics
Test1 test1 (/*AUTOINST*/
// Outputs
.match1 (match1[8:0]),
// Inputs
.drv_a (drv_a[3:0]),
.drv_e (drv_e[3:0]));
Test2 test2 (/*AUTOINST*/
// Outputs
.match2 (match2[8:0]),
// Inputs
.drv_a (drv_a[3:0]),
.drv_e (drv_e[3:0]));
// Aggregate outputs into a single result vector
wire [63:0] result = {39'h0, match2, 7'h0, match1};
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x m1=%x m2=%x (%b??%b:%b)\n", $time, cyc, crc, match1, match2, drv_e,drv_a,drv_b);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
sum <= 64'h0;
end
else if (cyc<10) begin
sum <= 64'h0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'hc0c4a2b9aea7c4b4
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module Test1
(
input wire [3:0] drv_a,
input wire [3:0] drv_e,
output wire [8:0] match1
);
wire [2:1] drv_all;
bufif1 bufa [2:1] (drv_all, drv_a[2:1], drv_e[2:1]);
`ifdef VERILATOR
// At present Verilator only allows comparisons with Zs
assign match1[0] = (drv_a[2:1]== 2'b00 && drv_e[2:1]==2'b11);
assign match1[1] = (drv_a[2:1]== 2'b01 && drv_e[2:1]==2'b11);
assign match1[2] = (drv_a[2:1]== 2'b10 && drv_e[2:1]==2'b11);
assign match1[3] = (drv_a[2:1]== 2'b11 && drv_e[2:1]==2'b11);
`else
assign match1[0] = drv_all === 2'b00;
assign match1[1] = drv_all === 2'b01;
assign match1[2] = drv_all === 2'b10;
assign match1[3] = drv_all === 2'b11;
`endif
assign match1[4] = drv_all === 2'bz0;
assign match1[5] = drv_all === 2'bz1;
assign match1[6] = drv_all === 2'bzz;
assign match1[7] = drv_all === 2'b0z;
assign match1[8] = drv_all === 2'b1z;
endmodule
module Test2
(
input wire [3:0] drv_a,
input wire [3:0] drv_e,
output wire [8:0] match2
);
wire [2:1] drv_all;
bufif1 bufa [2:1] (drv_all, drv_a[2:1], drv_e[2:1]);
`ifdef VERILATOR
assign match2[0] = (drv_all !== 2'b00 || drv_e[2:1]!=2'b11);
assign match2[1] = (drv_all !== 2'b01 || drv_e[2:1]!=2'b11);
assign match2[2] = (drv_all !== 2'b10 || drv_e[2:1]!=2'b11);
assign match2[3] = (drv_all !== 2'b11 || drv_e[2:1]!=2'b11);
`else
assign match2[0] = drv_all !== 2'b00;
assign match2[1] = drv_all !== 2'b01;
assign match2[2] = drv_all !== 2'b10;
assign match2[3] = drv_all !== 2'b11;
`endif
assign match2[4] = drv_all !== 2'bz0;
assign match2[5] = drv_all !== 2'bz1;
assign match2[6] = drv_all !== 2'bzz;
assign match2[7] = drv_all !== 2'b0z;
assign match2[8] = drv_all !== 2'b1z;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__NAND3_BEHAVIORAL_V
`define SKY130_FD_SC_HS__NAND3_BEHAVIORAL_V
/**
* nand3: 3-input NAND.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__nand3 (
Y ,
A ,
B ,
C ,
VPWR,
VGND
);
// Module ports
output Y ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
// Local signals
wire nand0_out_Y ;
wire u_vpwr_vgnd0_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out_Y , B, A, C );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_Y, nand0_out_Y, VPWR, VGND);
buf buf0 (Y , u_vpwr_vgnd0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__NAND3_BEHAVIORAL_V |
// i2c_hs_interface.v
// This file was auto-generated as a prototype implementation of a module
// created in component editor. It ties off all outputs to ground and
// ignores all inputs. It needs to be edited to make it do something
// useful.
//
// This file will not be automatically regenerated. You should check it in
// to your version control system if you want to keep it.
`timescale 1 ps / 1 ps
module i2c_hs_interface (
input wire clk, // clock.clk
input wire [2:0] slave_address, // slave.address
output wire [31:0] slave_readdata, // .readdata
input wire slave_read, // .read
input wire slave_write, // .write
input wire [31:0] slave_writedata, // .writedata
input wire reset, // reset.reset
output wire i2c_hs_read, // i2c_hs.export
output wire i2c_hs_write, // .export
output wire [2:0] i2c_hs_addr, // .export
input wire [31:0] i2c_hs_readdata, // .export
output wire [31:0] i2c_hs_writedata // .export
);
assign slave_readdata = i2c_hs_readdata;
assign i2c_hs_writedata = slave_writedata;
assign i2c_hs_write = slave_write;
assign i2c_hs_read = slave_read;
assign i2c_hs_addr = slave_address;
endmodule
|
`timescale 1ns / 1ps
/*
-- Module Name: Selector
-- Description: Seleccion de peticion activa para este ciclo de reloj.
El uso de algoritmos adaptativos o semi adaptativos
produce una o mas salidas validas para un paquete. Sin
embargo la solicitud de dos o mas puertos de salida a la
vez puede ocacionar dupliacion o liberacion de paquetes
corruptos a la red.
Este modulo recibe una o mas solicitudes para los
"planificadores de salida", pero solo permite la salida
de una peticion a la vez.
La seleccion de peticion activa depende de un esquema de
prioridad y de la disponibilidad de puertos.
-- Dependencies: -- system.vh
-- Parameters: -- PORT_DIR: Direccion del puerto de entrada
conectado a este modulo {x+, y+
x-, y-}.
-- Original Author: Héctor Cabrera
-- Current Author:
-- Notas:
(05/06/2015) El esquema de prioridad utilizado es fijo, y otorga
preferencia de salida en el siguiente orden {pe, x+, y+, x-, y-}
-- History:
-- Creacion 05 de Junio 2015
*/
module des_control
(
input wire clk,
input wire reset,
// -- input ---------------------------------------------------------- >>>>>
input wire start_strobe_din,
// -- output --------------------------------------------------------- >>>>>
output wire enable_dout,
output wire source_dout,
output wire active_dout,
output reg round_shift_dout,
output wire done_strobe_dout
);
// -- Parametros Locales ------------------------------------------------- >>>>>
localparam IDLE = 1'b0;
localparam ACTIVE = 1'b1;
// -- Declaracion temprana de Señales ------------------------------------ >>>>>
reg [3:0] round_counter;
// -- FSM::DES ----------------------------------------------------------- >>>>>
reg state_reg;
reg state_next;
// -- Elementos de memoria FSM --------------------------------------- >>>>>
always @(posedge clk)
if(reset)
state_reg <= IDLE;
else
state_reg <= state_next;
// -- Logica de estado siguiente ------------------------------------- >>>>>
always @(*)
begin
state_next = state_reg;
case (state_reg)
IDLE: if (start_strobe_din)
state_next = ACTIVE;
ACTIVE: if (round_counter == 4'b1111)
state_next = IDLE;
endcase // state_reg
end
// -- Contador de rondas --------------------------------------------- >>>>>
always @(posedge clk)
if (state_reg)
round_counter <= round_counter + 1'b1;
else
round_counter <= {4{1'b0}};
// -- Logica de salidas de control ----------------------------------- >>>>>
// -- enable ----------------------------------------------------- >>>>>
assign enable_dout = (state_next | state_reg) ? 1'b1 : 1'b0;
// -- round shift ------------------------------------------------ >>>>>
always @(*)
case (round_counter)
4'd0 : round_shift_dout = 1'b0;
4'd1 : round_shift_dout = 1'b0;
4'd8 : round_shift_dout = 1'b0;
4'd15: round_shift_dout = 1'b0;
default : round_shift_dout = 1'b1;
endcase // round_counter
// -- source select ---------------------------------------------- >>>>>
assign source_dout = (state_reg) ? 1'b1 : 1'b0;
// -- done strobe ------------------------------------------------ >>>>>
assign done_strobe_dout = (&round_counter) ? 1'b1 : 1'b0;
// -- active ----------------------------------------------------- >>>>>
assign active_dout = (state_reg) ? 1'b1 : 1'b0;
// -- Simbolos de Depuracion ----------------------------------------- >>>>>
wire [6*8:0] estado_presente;
wire [6*8:0] estado_siguiente;
assign estado_presente = (state_reg) ? "ACTIVE" : "IDLE";
assign estado_siguiente = (state_next) ? "ACTIVE" : "IDLE";
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 22:40:46 12/20/2010
// Design Name:
// Module Name: clk_test
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module clk_test(
input clk,
input sysclk,
output [31:0] snes_sysclk_freq
);
reg [31:0] snes_sysclk_freq_r;
assign snes_sysclk_freq = snes_sysclk_freq_r;
reg [31:0] sysclk_counter;
reg [31:0] sysclk_value;
initial snes_sysclk_freq_r = 32'hFFFFFFFF;
initial sysclk_counter = 0;
initial sysclk_value = 0;
reg [1:0] sysclk_sreg;
always @(posedge clk) sysclk_sreg <= {sysclk_sreg[0], sysclk};
wire sysclk_rising = (sysclk_sreg == 2'b01);
always @(posedge clk) begin
if(sysclk_counter < 96000000) begin
sysclk_counter <= sysclk_counter + 1;
if(sysclk_rising) sysclk_value <= sysclk_value + 1;
end else begin
snes_sysclk_freq_r <= sysclk_value;
sysclk_counter <= 0;
sysclk_value <= 0;
end
end
endmodule
|
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description: Write Response Channel for ATC
//
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
// b_atc
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
module processing_system7_v5_5_b_atc #
(
parameter C_FAMILY = "rtl",
// FPGA Family. Current version: virtex6, spartan6 or later.
parameter integer C_AXI_ID_WIDTH = 4,
// Width of all ID signals on SI and MI side of checker.
// Range: >= 1.
parameter integer C_AXI_BUSER_WIDTH = 1,
// Width of AWUSER signals.
// Range: >= 1.
parameter integer C_FIFO_DEPTH_LOG = 4
)
(
// Global Signals
input wire ARESET,
input wire ACLK,
// Command Interface
input wire cmd_b_push,
input wire cmd_b_error,
input wire [C_AXI_ID_WIDTH-1:0] cmd_b_id,
output wire cmd_b_ready,
output wire [C_FIFO_DEPTH_LOG-1:0] cmd_b_addr,
output reg cmd_b_full,
// Slave Interface Write Response Ports
output wire [C_AXI_ID_WIDTH-1:0] S_AXI_BID,
output reg [2-1:0] S_AXI_BRESP,
output wire [C_AXI_BUSER_WIDTH-1:0] S_AXI_BUSER,
output wire S_AXI_BVALID,
input wire S_AXI_BREADY,
// Master Interface Write Response Ports
input wire [C_AXI_ID_WIDTH-1:0] M_AXI_BID,
input wire [2-1:0] M_AXI_BRESP,
input wire [C_AXI_BUSER_WIDTH-1:0] M_AXI_BUSER,
input wire M_AXI_BVALID,
output wire M_AXI_BREADY,
// Trigger detection
output reg ERROR_TRIGGER,
output reg [C_AXI_ID_WIDTH-1:0] ERROR_TRANSACTION_ID
);
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
// Constants for packing levels.
localparam [2-1:0] C_RESP_OKAY = 2'b00;
localparam [2-1:0] C_RESP_EXOKAY = 2'b01;
localparam [2-1:0] C_RESP_SLVERROR = 2'b10;
localparam [2-1:0] C_RESP_DECERR = 2'b11;
// Command FIFO settings
localparam C_FIFO_WIDTH = C_AXI_ID_WIDTH + 1;
localparam C_FIFO_DEPTH = 2 ** C_FIFO_DEPTH_LOG;
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
integer index;
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
// Command Queue.
reg [C_FIFO_DEPTH_LOG-1:0] addr_ptr;
reg [C_FIFO_WIDTH-1:0] data_srl[C_FIFO_DEPTH-1:0];
reg cmd_b_valid;
wire cmd_b_ready_i;
wire inject_error;
wire [C_AXI_ID_WIDTH-1:0] current_id;
// Search command.
wire found_match;
wire use_match;
wire matching_id;
// Manage valid command.
wire write_valid_cmd;
reg [C_FIFO_DEPTH-2:0] valid_cmd;
reg [C_FIFO_DEPTH-2:0] updated_valid_cmd;
reg [C_FIFO_DEPTH-2:0] next_valid_cmd;
reg [C_FIFO_DEPTH_LOG-1:0] search_addr_ptr;
reg [C_FIFO_DEPTH_LOG-1:0] collapsed_addr_ptr;
// Pipelined data
reg [C_AXI_ID_WIDTH-1:0] M_AXI_BID_I;
reg [2-1:0] M_AXI_BRESP_I;
reg [C_AXI_BUSER_WIDTH-1:0] M_AXI_BUSER_I;
reg M_AXI_BVALID_I;
wire M_AXI_BREADY_I;
/////////////////////////////////////////////////////////////////////////////
// Command Queue:
//
// Keep track of depth of Queue to generate full flag.
//
// Also generate valid to mark pressence of commands in Queue.
//
// Maintain Queue and extract data from currently searched entry.
//
/////////////////////////////////////////////////////////////////////////////
// SRL FIFO Pointer.
always @ (posedge ACLK) begin
if (ARESET) begin
addr_ptr <= {C_FIFO_DEPTH_LOG{1'b1}};
end else begin
if ( cmd_b_push & ~cmd_b_ready_i ) begin
// Pushing data increase length/addr.
addr_ptr <= addr_ptr + 1;
end else if ( cmd_b_ready_i ) begin
// Collapse addr when data is popped.
addr_ptr <= collapsed_addr_ptr;
end
end
end
// FIFO Flags.
always @ (posedge ACLK) begin
if (ARESET) begin
cmd_b_full <= 1'b0;
cmd_b_valid <= 1'b0;
end else begin
if ( cmd_b_push & ~cmd_b_ready_i ) begin
cmd_b_full <= ( addr_ptr == C_FIFO_DEPTH-3 );
cmd_b_valid <= 1'b1;
end else if ( ~cmd_b_push & cmd_b_ready_i ) begin
cmd_b_full <= 1'b0;
cmd_b_valid <= ( collapsed_addr_ptr != C_FIFO_DEPTH-1 );
end
end
end
// Infere SRL for storage.
always @ (posedge ACLK) begin
if ( cmd_b_push ) begin
for (index = 0; index < C_FIFO_DEPTH-1 ; index = index + 1) begin
data_srl[index+1] <= data_srl[index];
end
data_srl[0] <= {cmd_b_error, cmd_b_id};
end
end
// Get current transaction info.
assign {inject_error, current_id} = data_srl[search_addr_ptr];
// Assign outputs.
assign cmd_b_addr = collapsed_addr_ptr;
/////////////////////////////////////////////////////////////////////////////
// Search Command Queue:
//
// Search for matching valid command in queue.
//
// A command is found when an valid entry with correct ID is found. The queue
// is search from the oldest entry, i.e. from a high value.
// When new commands are pushed the search address has to be updated to always
// start the search from the oldest available.
//
/////////////////////////////////////////////////////////////////////////////
// Handle search addr.
always @ (posedge ACLK) begin
if (ARESET) begin
search_addr_ptr <= {C_FIFO_DEPTH_LOG{1'b1}};
end else begin
if ( cmd_b_ready_i ) begin
// Collapse addr when data is popped.
search_addr_ptr <= collapsed_addr_ptr;
end else if ( M_AXI_BVALID_I & cmd_b_valid & ~found_match & ~cmd_b_push ) begin
// Skip non valid command.
search_addr_ptr <= search_addr_ptr - 1;
end else if ( cmd_b_push ) begin
search_addr_ptr <= search_addr_ptr + 1;
end
end
end
// Check if searched command is valid and match ID (for existing response on MI side).
assign matching_id = ( M_AXI_BID_I == current_id );
assign found_match = valid_cmd[search_addr_ptr] & matching_id & M_AXI_BVALID_I;
assign use_match = found_match & S_AXI_BREADY;
/////////////////////////////////////////////////////////////////////////////
// Track Used Commands:
//
// Actions that affect Valid Command:
// * When a new command is pushed
// => Shift valid vector one step
// * When a command is used
// => Clear corresponding valid bit
//
/////////////////////////////////////////////////////////////////////////////
// Valid command status is updated when a command is used or a new one is pushed.
assign write_valid_cmd = cmd_b_push | cmd_b_ready_i;
// Update the used command valid bit.
always @ *
begin
updated_valid_cmd = valid_cmd;
updated_valid_cmd[search_addr_ptr] = ~use_match;
end
// Shift valid vector when command is pushed.
always @ *
begin
if ( cmd_b_push ) begin
next_valid_cmd = {updated_valid_cmd[C_FIFO_DEPTH-3:0], 1'b1};
end else begin
next_valid_cmd = updated_valid_cmd;
end
end
// Valid signals for next cycle.
always @ (posedge ACLK) begin
if (ARESET) begin
valid_cmd <= {C_FIFO_WIDTH{1'b0}};
end else if ( write_valid_cmd ) begin
valid_cmd <= next_valid_cmd;
end
end
// Detect oldest available command in Queue.
always @ *
begin
// Default to empty.
collapsed_addr_ptr = {C_FIFO_DEPTH_LOG{1'b1}};
for (index = 0; index < C_FIFO_DEPTH-2 ; index = index + 1) begin
if ( next_valid_cmd[index] ) begin
collapsed_addr_ptr = index;
end
end
end
/////////////////////////////////////////////////////////////////////////////
// Pipe incoming data:
//
// The B channel is piped to improve timing and avoid impact in search
// mechanism due to late arriving signals.
//
/////////////////////////////////////////////////////////////////////////////
// Clock data.
always @ (posedge ACLK) begin
if (ARESET) begin
M_AXI_BID_I <= {C_AXI_ID_WIDTH{1'b0}};
M_AXI_BRESP_I <= 2'b00;
M_AXI_BUSER_I <= {C_AXI_BUSER_WIDTH{1'b0}};
M_AXI_BVALID_I <= 1'b0;
end else begin
if ( M_AXI_BREADY_I | ~M_AXI_BVALID_I ) begin
M_AXI_BVALID_I <= 1'b0;
end
if (M_AXI_BVALID & ( M_AXI_BREADY_I | ~M_AXI_BVALID_I) ) begin
M_AXI_BID_I <= M_AXI_BID;
M_AXI_BRESP_I <= M_AXI_BRESP;
M_AXI_BUSER_I <= M_AXI_BUSER;
M_AXI_BVALID_I <= 1'b1;
end
end
end
// Generate ready to get new transaction.
assign M_AXI_BREADY = M_AXI_BREADY_I | ~M_AXI_BVALID_I;
/////////////////////////////////////////////////////////////////////////////
// Inject Error:
//
// BRESP is modified according to command information.
//
/////////////////////////////////////////////////////////////////////////////
// Inject error in response.
always @ *
begin
if ( inject_error ) begin
S_AXI_BRESP = C_RESP_SLVERROR;
end else begin
S_AXI_BRESP = M_AXI_BRESP_I;
end
end
// Handle interrupt generation.
always @ (posedge ACLK) begin
if (ARESET) begin
ERROR_TRIGGER <= 1'b0;
ERROR_TRANSACTION_ID <= {C_AXI_ID_WIDTH{1'b0}};
end else begin
if ( inject_error & cmd_b_ready_i ) begin
ERROR_TRIGGER <= 1'b1;
ERROR_TRANSACTION_ID <= M_AXI_BID_I;
end else begin
ERROR_TRIGGER <= 1'b0;
end
end
end
/////////////////////////////////////////////////////////////////////////////
// Transaction Throttling:
//
// Response is passed forward when a matching entry has been found in queue.
// Both ready and valid are set when the command is completed.
//
/////////////////////////////////////////////////////////////////////////////
// Propagate masked valid.
assign S_AXI_BVALID = M_AXI_BVALID_I & cmd_b_valid & found_match;
// Return ready with push back.
assign M_AXI_BREADY_I = cmd_b_valid & use_match;
// Command has been handled.
assign cmd_b_ready_i = M_AXI_BVALID_I & cmd_b_valid & use_match;
assign cmd_b_ready = cmd_b_ready_i;
/////////////////////////////////////////////////////////////////////////////
// Write Response Propagation:
//
// All information is simply forwarded on from MI- to SI-Side untouched.
//
/////////////////////////////////////////////////////////////////////////////
// 1:1 mapping.
assign S_AXI_BID = M_AXI_BID_I;
assign S_AXI_BUSER = M_AXI_BUSER_I;
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 04/26/2016 09:14:57 AM
// Design Name:
// Module Name: FSM_test
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module FSM_test
(
input wire clk,
input wire rst,
input wire ready_op,
input wire max_tick_address,
input wire max_tick_ch,
input wire TX_DONE,
output reg beg_op,
output reg ack_op,
output reg load_address,
output reg enab_address,
output reg enab_ch,
output reg load_ch,
output reg TX_START
);
//symbolic state declaration
localparam [3:0] est0 = 4'b0000,
est1 = 4'b0001,
est2 = 4'b0010,
est3 = 4'b0011,
est4 = 4'b0100,
est5 = 4'b0101,
est6 = 4'b0110,
est7 = 4'b0111,
est8 = 4'b1000,
est9 = 4'b1001,
est10 = 4'b1010,
est11 = 4'b1011;
//signal declaration
reg [3:0] state_reg, state_next; // Guardan el estado actual y el estado futuro, respectivamente.
//state register
always @( posedge clk, posedge rst)
begin
if(rst) // Si hay reset, el estado actual es el estado inicial.
state_reg <= est0;
else //Si no hay reset el estado actual es igual al estado siguiente.
state_reg <= state_next;
end
//next-state logic and output logic
always @*
begin
state_next = state_reg; // default state : the same
//declaration of default outputs.
beg_op = 1'b0;
ack_op = 1'b0;
load_address = 1'b0;
enab_address = 1'b0;
enab_ch = 1'b0;
load_ch = 1'b0;
TX_START = 1'b0;
case(state_reg)
est0:
begin
state_next = est1;
end
est1:
begin
load_address = 1'b1;
enab_address = 1'b1;
state_next = est2;
end
est2:
begin
beg_op = 1'b1;
state_next=est3;
end
est3:
begin
beg_op = 1'b1;
enab_ch = 1'b1;
load_ch = 1'b1;
state_next=est4;
end
est4:
begin
if(ready_op)
state_next=est5;
else
state_next=est4;
end
est5:
begin
state_next=est6;
end
est6:
begin
TX_START = 1'b1;
state_next=est7;
end
est7:
begin
if(TX_DONE)
if(max_tick_ch)
state_next=est9;
else
begin
state_next=est8;
end
else
state_next=est7;
end
est8:
begin
enab_ch = 1'b1;
state_next=est5;
end
est9:
begin
if(max_tick_address)
state_next=est11;
else
begin
state_next=est10;
end
end
est10:
begin
enab_address = 1'b1;
ack_op = 1'b1;
state_next=est2;
end
est11:
begin
state_next=est11;
end
default:
state_next=est0;
endcase
end
endmodule
|
//altera message_off 10230
`timescale 1 ps / 1 ps
module alt_mem_ddrx_list
# (
// module parameter port list
parameter
CTL_LIST_WIDTH = 3, // number of dram commands that can be tracked at a time
CTL_LIST_DEPTH = 8,
CTL_LIST_INIT_VALUE_TYPE = "INCR", // INCR, ZERO
CTL_LIST_INIT_VALID = "VALID" // VALID, INVALID
)
(
// port list
ctl_clk,
ctl_reset_n,
// pop free list
list_get_entry_valid,
list_get_entry_ready,
list_get_entry_id,
list_get_entry_id_vector,
// push free list
list_put_entry_valid,
list_put_entry_ready,
list_put_entry_id
);
// -----------------------------
// port declaration
// -----------------------------
input ctl_clk;
input ctl_reset_n;
// pop free list
input list_get_entry_ready;
output list_get_entry_valid;
output [CTL_LIST_WIDTH-1:0] list_get_entry_id;
output [CTL_LIST_DEPTH-1:0] list_get_entry_id_vector;
// push free list
output list_put_entry_ready;
input list_put_entry_valid;
input [CTL_LIST_WIDTH-1:0] list_put_entry_id;
// -----------------------------
// port type declaration
// -----------------------------
reg list_get_entry_valid;
wire list_get_entry_ready;
reg [CTL_LIST_WIDTH-1:0] list_get_entry_id;
reg [CTL_LIST_DEPTH-1:0] list_get_entry_id_vector;
wire list_put_entry_valid;
reg list_put_entry_ready;
wire [CTL_LIST_WIDTH-1:0] list_put_entry_id;
// -----------------------------
// signal declaration
// -----------------------------
reg [CTL_LIST_WIDTH-1:0] list [CTL_LIST_DEPTH-1:0];
reg list_v [CTL_LIST_DEPTH-1:0];
reg [CTL_LIST_DEPTH-1:0] list_vector;
wire list_get = list_get_entry_valid & list_get_entry_ready;
wire list_put = list_put_entry_valid & list_put_entry_ready;
// -----------------------------
// module definition
// -----------------------------
// generate interface signals
always @ (*)
begin
// connect interface signals to list head & tail
list_get_entry_valid = list_v[0];
list_get_entry_id = list[0];
list_get_entry_id_vector = list_vector;
list_put_entry_ready = ~list_v[CTL_LIST_DEPTH-1];
end
// list put & get management
integer i;
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (~ctl_reset_n)
begin
for (i = 0; i < CTL_LIST_DEPTH; i = i + 1'b1)
begin
// initialize every entry
if (CTL_LIST_INIT_VALUE_TYPE == "INCR")
begin
list [i] <= i;
end
else
begin
list [i] <= {CTL_LIST_WIDTH{1'b0}};
end
if (CTL_LIST_INIT_VALID == "VALID")
begin
list_v [i] <= 1'b1;
end
else
begin
list_v [i] <= 1'b0;
end
end
list_vector <= {CTL_LIST_DEPTH{1'b0}};
end
else
begin
// get request code must be above put request code
if (list_get)
begin
// on a get request, list is shifted to move next entry to head
for (i = 1; i < CTL_LIST_DEPTH; i = i + 1'b1)
begin
list_v [i-1] <= list_v [i];
list [i-1] <= list [i];
end
list_v [CTL_LIST_DEPTH-1] <= 0;
for (i = 0; i < CTL_LIST_DEPTH;i = i + 1'b1)
begin
if (i == list [1])
begin
list_vector [i] <= 1'b1;
end
else
begin
list_vector [i] <= 1'b0;
end
end
end
if (list_put)
begin
// on a put request, next empty list entry is written
if (~list_get)
begin
// put request only
for (i = 1; i < CTL_LIST_DEPTH; i = i + 1'b1)
begin
if ( list_v[i-1] & ~list_v[i])
begin
list_v [i] <= 1'b1;
list [i] <= list_put_entry_id;
end
end
if (~list_v[0])
begin
list_v [0] <= 1'b1;
list [0] <= list_put_entry_id;
for (i = 0; i < CTL_LIST_DEPTH;i = i + 1'b1)
begin
if (i == list_put_entry_id)
begin
list_vector [i] <= 1'b1;
end
else
begin
list_vector [i] <= 1'b0;
end
end
end
end
else
begin
// put & get request on same cycle
for (i = 1; i < CTL_LIST_DEPTH; i = i + 1'b1)
begin
if (list_v[i-1] & ~list_v[i])
begin
list_v [i-1] <= 1'b1;
list [i-1] <= list_put_entry_id;
end
end
// if (~list_v[0])
// begin
// $display("error - list underflow");
// end
for (i = 0; i < CTL_LIST_DEPTH;i = i + 1'b1)
begin
if (list_v[0] & ~list_v[1])
begin
if (i == list_put_entry_id)
begin
list_vector [i] <= 1'b1;
end
else
begin
list_vector [i] <= 1'b0;
end
end
else
begin
if (i == list [1])
begin
list_vector [i] <= 1'b1;
end
else
begin
list_vector [i] <= 1'b0;
end
end
end
end
end
end
end
endmodule
|
// -- (c) Copyright 2009 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// File name: si_transactor.v
//
// Description:
// This module manages multi-threaded transactions for one SI-slot.
// The module interface consists of a 1-slave to 1-master address channel, plus a
// (M+1)-master (from M MI-slots plus error handler) to 1-slave response channel.
// The module maintains transaction thread control registers that count the
// number of outstanding transations for each thread and the target MI-slot.
// On the address channel, the module decodes addresses to select among MI-slots
// accessible to the SI-slot where it is instantiated.
// It then qualifies whether each received transaction
// should be propagated as a request to the address channel arbiter.
// Transactions are blocked while there is any outstanding transaction to a
// different slave (MI-slot) for the requested ID thread (for deadlock avoidance).
// On the response channel, the module mulitplexes transfers from each of the
// MI-slots whenever a transfer targets the ID of an active thread,
// arbitrating between MI-slots if multiple threads respond concurrently.
//
//--------------------------------------------------------------------------
//
// Structure:
// si_transactor
// addr_decoder
// comparator_static
// mux_enc
// axic_srl_fifo
// arbiter_resp
//
//-----------------------------------------------------------------------------
`timescale 1ps/1ps
`default_nettype none
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_crossbar_v2_1_si_transactor #
(
parameter C_FAMILY = "none",
parameter integer C_SI = 0, // SI-slot number of current instance.
parameter integer C_DIR = 0, // Direction: 0 = Write; 1 = Read.
parameter integer C_NUM_ADDR_RANGES = 1,
parameter integer C_NUM_M = 2,
parameter integer C_NUM_M_LOG = 1,
parameter integer C_ACCEPTANCE = 1, // Acceptance limit of this SI-slot.
parameter integer C_ACCEPTANCE_LOG = 0, // Width of acceptance counter for this SI-slot.
parameter integer C_ID_WIDTH = 1,
parameter integer C_THREAD_ID_WIDTH = 0,
parameter integer C_ADDR_WIDTH = 32,
parameter integer C_AMESG_WIDTH = 1, // Used for AW or AR channel payload, depending on instantiation.
parameter integer C_RMESG_WIDTH = 1, // Used for B or R channel payload, depending on instantiation.
parameter [C_ID_WIDTH-1:0] C_BASE_ID = {C_ID_WIDTH{1'b0}},
parameter [C_ID_WIDTH-1:0] C_HIGH_ID = {C_ID_WIDTH{1'b0}},
parameter [C_NUM_M*C_NUM_ADDR_RANGES*64-1:0] C_BASE_ADDR = {C_NUM_M*C_NUM_ADDR_RANGES*64{1'b1}},
parameter [C_NUM_M*C_NUM_ADDR_RANGES*64-1:0] C_HIGH_ADDR = {C_NUM_M*C_NUM_ADDR_RANGES*64{1'b0}},
parameter integer C_SINGLE_THREAD = 0,
parameter [C_NUM_M-1:0] C_TARGET_QUAL = {C_NUM_M{1'b1}},
parameter [C_NUM_M*32-1:0] C_M_AXI_SECURE = {C_NUM_M{32'h00000000}},
parameter integer C_RANGE_CHECK = 0,
parameter integer C_ADDR_DECODE =0,
parameter [C_NUM_M*32-1:0] C_ERR_MODE = {C_NUM_M{32'h00000000}},
parameter integer C_DEBUG = 1
)
(
// Global Signals
input wire ACLK,
input wire ARESET,
// Slave Address Channel Interface Ports
input wire [C_ID_WIDTH-1:0] S_AID,
input wire [C_ADDR_WIDTH-1:0] S_AADDR,
input wire [8-1:0] S_ALEN,
input wire [3-1:0] S_ASIZE,
input wire [2-1:0] S_ABURST,
input wire [2-1:0] S_ALOCK,
input wire [3-1:0] S_APROT,
// input wire [4-1:0] S_AREGION,
input wire [C_AMESG_WIDTH-1:0] S_AMESG,
input wire S_AVALID,
output wire S_AREADY,
// Master Address Channel Interface Ports
output wire [C_ID_WIDTH-1:0] M_AID,
output wire [C_ADDR_WIDTH-1:0] M_AADDR,
output wire [8-1:0] M_ALEN,
output wire [3-1:0] M_ASIZE,
output wire [2-1:0] M_ALOCK,
output wire [3-1:0] M_APROT,
output wire [4-1:0] M_AREGION,
output wire [C_AMESG_WIDTH-1:0] M_AMESG,
output wire [(C_NUM_M+1)-1:0] M_ATARGET_HOT,
output wire [(C_NUM_M_LOG+1)-1:0] M_ATARGET_ENC,
output wire [7:0] M_AERROR,
output wire M_AVALID_QUAL,
output wire M_AVALID,
input wire M_AREADY,
// Slave Response Channel Interface Ports
output wire [C_ID_WIDTH-1:0] S_RID,
output wire [C_RMESG_WIDTH-1:0] S_RMESG,
output wire S_RLAST,
output wire S_RVALID,
input wire S_RREADY,
// Master Response Channel Interface Ports
input wire [(C_NUM_M+1)*C_ID_WIDTH-1:0] M_RID,
input wire [(C_NUM_M+1)*C_RMESG_WIDTH-1:0] M_RMESG,
input wire [(C_NUM_M+1)-1:0] M_RLAST,
input wire [(C_NUM_M+1)-1:0] M_RVALID,
output wire [(C_NUM_M+1)-1:0] M_RREADY,
input wire [(C_NUM_M+1)-1:0] M_RTARGET, // Does response ID from each MI-slot target this SI slot?
input wire [8-1:0] DEBUG_A_TRANS_SEQ
);
localparam integer P_WRITE = 0;
localparam integer P_READ = 1;
localparam integer P_RMUX_MESG_WIDTH = C_ID_WIDTH + C_RMESG_WIDTH + 1;
localparam [31:0] P_AXILITE_ERRMODE = 32'h00000001;
localparam integer P_NONSECURE_BIT = 1;
localparam integer P_NUM_M_LOG_M1 = C_NUM_M_LOG ? C_NUM_M_LOG : 1;
localparam [C_NUM_M-1:0] P_M_AXILITE = f_m_axilite(0); // Mask of AxiLite MI-slots
localparam [1:0] P_FIXED = 2'b00;
localparam integer P_NUM_M_DE_LOG = f_ceil_log2(C_NUM_M+1);
localparam integer P_THREAD_ID_WIDTH_M1 = (C_THREAD_ID_WIDTH > 0) ? C_THREAD_ID_WIDTH : 1;
localparam integer P_NUM_ID_VAL = 2**C_THREAD_ID_WIDTH;
localparam integer P_NUM_THREADS = (P_NUM_ID_VAL < C_ACCEPTANCE) ? P_NUM_ID_VAL : C_ACCEPTANCE;
localparam [C_NUM_M-1:0] P_M_SECURE_MASK = f_bit32to1_mi(C_M_AXI_SECURE); // Mask of secure MI-slots
// Ceiling of log2(x)
function integer f_ceil_log2
(
input integer x
);
integer acc;
begin
acc=0;
while ((2**acc) < x)
acc = acc + 1;
f_ceil_log2 = acc;
end
endfunction
// AxiLite protocol flag vector
function [C_NUM_M-1:0] f_m_axilite
(
input integer null_arg
);
integer mi;
begin
for (mi=0; mi<C_NUM_M; mi=mi+1) begin
f_m_axilite[mi] = (C_ERR_MODE[mi*32+:32] == P_AXILITE_ERRMODE);
end
end
endfunction
// Convert Bit32 vector of range [0,1] to Bit1 vector on MI
function [C_NUM_M-1:0] f_bit32to1_mi
(input [C_NUM_M*32-1:0] vec32);
integer mi;
begin
for (mi=0; mi<C_NUM_M; mi=mi+1) begin
f_bit32to1_mi[mi] = vec32[mi*32];
end
end
endfunction
wire [C_NUM_M-1:0] target_mi_hot;
wire [P_NUM_M_LOG_M1-1:0] target_mi_enc;
wire [(C_NUM_M+1)-1:0] m_atarget_hot_i;
wire [(P_NUM_M_DE_LOG)-1:0] m_atarget_enc_i;
wire match;
wire [3:0] target_region;
wire [3:0] m_aregion_i;
wire m_avalid_i;
wire s_aready_i;
wire any_error;
wire s_rvalid_i;
wire [C_ID_WIDTH-1:0] s_rid_i;
wire s_rlast_i;
wire [P_RMUX_MESG_WIDTH-1:0] si_rmux_mesg;
wire [(C_NUM_M+1)*P_RMUX_MESG_WIDTH-1:0] mi_rmux_mesg;
wire [(C_NUM_M+1)-1:0] m_rvalid_qual;
wire [(C_NUM_M+1)-1:0] m_rready_arb;
wire [(C_NUM_M+1)-1:0] m_rready_i;
wire target_secure;
wire target_axilite;
wire m_avalid_qual_i;
wire [7:0] m_aerror_i;
genvar gen_mi;
genvar gen_thread;
generate
if (C_ADDR_DECODE) begin : gen_addr_decoder
axi_crossbar_v2_1_addr_decoder #
(
.C_FAMILY (C_FAMILY),
.C_NUM_TARGETS (C_NUM_M),
.C_NUM_TARGETS_LOG (P_NUM_M_LOG_M1),
.C_NUM_RANGES (C_NUM_ADDR_RANGES),
.C_ADDR_WIDTH (C_ADDR_WIDTH),
.C_TARGET_ENC (1),
.C_TARGET_HOT (1),
.C_REGION_ENC (1),
.C_BASE_ADDR (C_BASE_ADDR),
.C_HIGH_ADDR (C_HIGH_ADDR),
.C_TARGET_QUAL (C_TARGET_QUAL),
.C_RESOLUTION (2)
)
addr_decoder_inst
(
.ADDR (S_AADDR),
.TARGET_HOT (target_mi_hot),
.TARGET_ENC (target_mi_enc),
.MATCH (match),
.REGION (target_region)
);
end else begin : gen_no_addr_decoder
assign target_mi_hot = 1;
assign target_mi_enc = 0;
assign match = 1'b1;
assign target_region = 4'b0000;
end
endgenerate
assign target_secure = |(target_mi_hot & P_M_SECURE_MASK);
assign target_axilite = |(target_mi_hot & P_M_AXILITE);
assign any_error = C_RANGE_CHECK && (m_aerror_i != 0); // DECERR if error-detection enabled and any error condition.
assign m_aerror_i[0] = ~match; // Invalid target address
assign m_aerror_i[1] = target_secure && S_APROT[P_NONSECURE_BIT]; // TrustZone violation
assign m_aerror_i[2] = target_axilite && ((S_ALEN != 0) ||
(S_ASIZE[1:0] == 2'b11) || (S_ASIZE[2] == 1'b1)); // AxiLite access violation
assign m_aerror_i[7:3] = 5'b00000; // Reserved
assign M_ATARGET_HOT = m_atarget_hot_i;
assign m_atarget_hot_i = (any_error ? {1'b1, {C_NUM_M{1'b0}}} : {1'b0, target_mi_hot});
assign m_atarget_enc_i = (any_error ? C_NUM_M : target_mi_enc);
assign M_AVALID = m_avalid_i;
assign m_avalid_i = S_AVALID;
assign M_AVALID_QUAL = m_avalid_qual_i;
assign S_AREADY = s_aready_i;
assign s_aready_i = M_AREADY;
assign M_AERROR = m_aerror_i;
assign M_ATARGET_ENC = m_atarget_enc_i;
assign m_aregion_i = any_error ? 4'b0000 : (C_ADDR_DECODE != 0) ? target_region : 4'b0000;
// assign m_aregion_i = any_error ? 4'b0000 : (C_ADDR_DECODE != 0) ? target_region : S_AREGION;
assign M_AREGION = m_aregion_i;
assign M_AID = S_AID;
assign M_AADDR = S_AADDR;
assign M_ALEN = S_ALEN;
assign M_ASIZE = S_ASIZE;
assign M_ALOCK = S_ALOCK;
assign M_APROT = S_APROT;
assign M_AMESG = S_AMESG;
assign S_RVALID = s_rvalid_i;
assign M_RREADY = m_rready_i;
assign s_rid_i = si_rmux_mesg[0+:C_ID_WIDTH];
assign S_RMESG = si_rmux_mesg[C_ID_WIDTH+:C_RMESG_WIDTH];
assign s_rlast_i = si_rmux_mesg[C_ID_WIDTH+C_RMESG_WIDTH+:1];
assign S_RID = s_rid_i;
assign S_RLAST = s_rlast_i;
assign m_rvalid_qual = M_RVALID & M_RTARGET;
assign m_rready_i = m_rready_arb & M_RTARGET;
generate
for (gen_mi=0; gen_mi<(C_NUM_M+1); gen_mi=gen_mi+1) begin : gen_rmesg_mi
// Note: Concatenation of mesg signals is from MSB to LSB; assignments that chop mesg signals appear in opposite order.
assign mi_rmux_mesg[gen_mi*P_RMUX_MESG_WIDTH+:P_RMUX_MESG_WIDTH] = {
M_RLAST[gen_mi],
M_RMESG[gen_mi*C_RMESG_WIDTH+:C_RMESG_WIDTH],
M_RID[gen_mi*C_ID_WIDTH+:C_ID_WIDTH]
};
end // gen_rmesg_mi
if (C_ACCEPTANCE == 1) begin : gen_single_issue
wire cmd_push;
wire cmd_pop;
reg [(C_NUM_M+1)-1:0] active_target_hot;
reg [P_NUM_M_DE_LOG-1:0] active_target_enc;
reg accept_cnt;
reg [8-1:0] debug_r_beat_cnt_i;
wire [8-1:0] debug_r_trans_seq_i;
assign cmd_push = M_AREADY;
assign cmd_pop = s_rvalid_i && S_RREADY && s_rlast_i; // Pop command queue if end of read burst
assign m_avalid_qual_i = ~accept_cnt | cmd_pop; // Ready for arbitration if no outstanding transaction or transaction being completed
always @(posedge ACLK) begin
if (ARESET) begin
accept_cnt <= 1'b0;
active_target_enc <= 0;
active_target_hot <= 0;
end else begin
if (cmd_push) begin
active_target_enc <= m_atarget_enc_i;
active_target_hot <= m_atarget_hot_i;
accept_cnt <= 1'b1;
end else if (cmd_pop) begin
accept_cnt <= 1'b0;
end
end
end // Clocked process
assign m_rready_arb = active_target_hot & {(C_NUM_M+1){S_RREADY}};
assign s_rvalid_i = |(active_target_hot & m_rvalid_qual);
generic_baseblocks_v2_1_mux_enc #
(
.C_FAMILY (C_FAMILY),
.C_RATIO (C_NUM_M+1),
.C_SEL_WIDTH (P_NUM_M_DE_LOG),
.C_DATA_WIDTH (P_RMUX_MESG_WIDTH)
) mux_resp_single_issue
(
.S (active_target_enc),
.A (mi_rmux_mesg),
.O (si_rmux_mesg),
.OE (1'b1)
);
if (C_DEBUG) begin : gen_debug_r_single_issue
// DEBUG READ BEAT COUNTER (only meaningful for R-channel)
always @(posedge ACLK) begin
if (ARESET) begin
debug_r_beat_cnt_i <= 0;
end else if (C_DIR == P_READ) begin
if (s_rvalid_i && S_RREADY) begin
if (s_rlast_i) begin
debug_r_beat_cnt_i <= 0;
end else begin
debug_r_beat_cnt_i <= debug_r_beat_cnt_i + 1;
end
end
end else begin
debug_r_beat_cnt_i <= 0;
end
end // Clocked process
// DEBUG R-CHANNEL TRANSACTION SEQUENCE FIFO
axi_data_fifo_v2_1_axic_srl_fifo #
(
.C_FAMILY (C_FAMILY),
.C_FIFO_WIDTH (8),
.C_FIFO_DEPTH_LOG (C_ACCEPTANCE_LOG+1),
.C_USE_FULL (0)
)
debug_r_seq_fifo_single_issue
(
.ACLK (ACLK),
.ARESET (ARESET),
.S_MESG (DEBUG_A_TRANS_SEQ),
.S_VALID (cmd_push),
.S_READY (),
.M_MESG (debug_r_trans_seq_i),
.M_VALID (),
.M_READY (cmd_pop)
);
end // gen_debug_r
end else if (C_SINGLE_THREAD || (P_NUM_ID_VAL==1)) begin : gen_single_thread
wire s_avalid_en;
wire cmd_push;
wire cmd_pop;
reg [C_ID_WIDTH-1:0] active_id;
reg [(C_NUM_M+1)-1:0] active_target_hot;
reg [P_NUM_M_DE_LOG-1:0] active_target_enc;
reg [4-1:0] active_region;
reg [(C_ACCEPTANCE_LOG+1)-1:0] accept_cnt;
reg [8-1:0] debug_r_beat_cnt_i;
wire [8-1:0] debug_r_trans_seq_i;
wire accept_limit ;
// Implement single-region-per-ID cyclic dependency avoidance method.
assign s_avalid_en = // This transaction is qualified to request arbitration if ...
(accept_cnt == 0) || // Either there are no outstanding transactions, or ...
(((P_NUM_ID_VAL==1) || (S_AID[P_THREAD_ID_WIDTH_M1-1:0] == active_id[P_THREAD_ID_WIDTH_M1-1:0])) && // the current transaction ID matches the previous, and ...
(active_target_enc == m_atarget_enc_i) && // all outstanding transactions are to the same target MI ...
(active_region == m_aregion_i)); // and to the same REGION.
assign cmd_push = M_AREADY;
assign cmd_pop = s_rvalid_i && S_RREADY && s_rlast_i; // Pop command queue if end of read burst
assign accept_limit = (accept_cnt == C_ACCEPTANCE) & ~cmd_pop; // Allow next push if a transaction is currently being completed
assign m_avalid_qual_i = s_avalid_en & ~accept_limit;
always @(posedge ACLK) begin
if (ARESET) begin
accept_cnt <= 0;
active_id <= 0;
active_target_enc <= 0;
active_target_hot <= 0;
active_region <= 0;
end else begin
if (cmd_push) begin
active_id <= S_AID[P_THREAD_ID_WIDTH_M1-1:0];
active_target_enc <= m_atarget_enc_i;
active_target_hot <= m_atarget_hot_i;
active_region <= m_aregion_i;
if (~cmd_pop) begin
accept_cnt <= accept_cnt + 1;
end
end else begin
if (cmd_pop & (accept_cnt != 0)) begin
accept_cnt <= accept_cnt - 1;
end
end
end
end // Clocked process
assign m_rready_arb = active_target_hot & {(C_NUM_M+1){S_RREADY}};
assign s_rvalid_i = |(active_target_hot & m_rvalid_qual);
generic_baseblocks_v2_1_mux_enc #
(
.C_FAMILY (C_FAMILY),
.C_RATIO (C_NUM_M+1),
.C_SEL_WIDTH (P_NUM_M_DE_LOG),
.C_DATA_WIDTH (P_RMUX_MESG_WIDTH)
) mux_resp_single_thread
(
.S (active_target_enc),
.A (mi_rmux_mesg),
.O (si_rmux_mesg),
.OE (1'b1)
);
if (C_DEBUG) begin : gen_debug_r_single_thread
// DEBUG READ BEAT COUNTER (only meaningful for R-channel)
always @(posedge ACLK) begin
if (ARESET) begin
debug_r_beat_cnt_i <= 0;
end else if (C_DIR == P_READ) begin
if (s_rvalid_i && S_RREADY) begin
if (s_rlast_i) begin
debug_r_beat_cnt_i <= 0;
end else begin
debug_r_beat_cnt_i <= debug_r_beat_cnt_i + 1;
end
end
end else begin
debug_r_beat_cnt_i <= 0;
end
end // Clocked process
// DEBUG R-CHANNEL TRANSACTION SEQUENCE FIFO
axi_data_fifo_v2_1_axic_srl_fifo #
(
.C_FAMILY (C_FAMILY),
.C_FIFO_WIDTH (8),
.C_FIFO_DEPTH_LOG (C_ACCEPTANCE_LOG+1),
.C_USE_FULL (0)
)
debug_r_seq_fifo_single_thread
(
.ACLK (ACLK),
.ARESET (ARESET),
.S_MESG (DEBUG_A_TRANS_SEQ),
.S_VALID (cmd_push),
.S_READY (),
.M_MESG (debug_r_trans_seq_i),
.M_VALID (),
.M_READY (cmd_pop)
);
end // gen_debug_r
end else begin : gen_multi_thread
wire [(P_NUM_M_DE_LOG)-1:0] resp_select;
reg [(C_ACCEPTANCE_LOG+1)-1:0] accept_cnt;
wire [P_NUM_THREADS-1:0] s_avalid_en;
wire [P_NUM_THREADS-1:0] thread_valid;
wire [P_NUM_THREADS-1:0] aid_match;
wire [P_NUM_THREADS-1:0] rid_match;
wire [P_NUM_THREADS-1:0] cmd_push;
wire [P_NUM_THREADS-1:0] cmd_pop;
wire [P_NUM_THREADS:0] accum_push;
reg [P_NUM_THREADS*C_ID_WIDTH-1:0] active_id;
reg [P_NUM_THREADS*8-1:0] active_target;
reg [P_NUM_THREADS*8-1:0] active_region;
reg [P_NUM_THREADS*8-1:0] active_cnt;
reg [P_NUM_THREADS*8-1:0] debug_r_beat_cnt_i;
wire [P_NUM_THREADS*8-1:0] debug_r_trans_seq_i;
wire any_aid_match;
wire any_rid_match;
wire accept_limit;
wire any_push;
wire any_pop;
axi_crossbar_v2_1_arbiter_resp # // Multi-thread response arbiter
(
.C_FAMILY (C_FAMILY),
.C_NUM_S (C_NUM_M+1),
.C_NUM_S_LOG (P_NUM_M_DE_LOG),
.C_GRANT_ENC (1),
.C_GRANT_HOT (0)
)
arbiter_resp_inst
(
.ACLK (ACLK),
.ARESET (ARESET),
.S_VALID (m_rvalid_qual),
.S_READY (m_rready_arb),
.M_GRANT_HOT (),
.M_GRANT_ENC (resp_select),
.M_VALID (s_rvalid_i),
.M_READY (S_RREADY)
);
generic_baseblocks_v2_1_mux_enc #
(
.C_FAMILY (C_FAMILY),
.C_RATIO (C_NUM_M+1),
.C_SEL_WIDTH (P_NUM_M_DE_LOG),
.C_DATA_WIDTH (P_RMUX_MESG_WIDTH)
) mux_resp_multi_thread
(
.S (resp_select),
.A (mi_rmux_mesg),
.O (si_rmux_mesg),
.OE (1'b1)
);
assign any_push = M_AREADY;
assign any_pop = s_rvalid_i & S_RREADY & s_rlast_i;
assign accept_limit = (accept_cnt == C_ACCEPTANCE) & ~any_pop; // Allow next push if a transaction is currently being completed
assign m_avalid_qual_i = (&s_avalid_en) & ~accept_limit; // The current request is qualified for arbitration when it is qualified against all outstanding transaction threads.
assign any_aid_match = |aid_match;
assign any_rid_match = |rid_match;
assign accum_push[0] = 1'b0;
always @(posedge ACLK) begin
if (ARESET) begin
accept_cnt <= 0;
end else begin
if (any_push & ~any_pop) begin
accept_cnt <= accept_cnt + 1;
end else if (any_pop & ~any_push & (accept_cnt != 0)) begin
accept_cnt <= accept_cnt - 1;
end
end
end // Clocked process
for (gen_thread=0; gen_thread<P_NUM_THREADS; gen_thread=gen_thread+1) begin : gen_thread_loop
assign thread_valid[gen_thread] = (active_cnt[gen_thread*8 +: C_ACCEPTANCE_LOG+1] != 0);
assign aid_match[gen_thread] = // The currect thread is active for the requested transaction if
thread_valid[gen_thread] && // this thread slot is not vacant, and
((S_AID[P_THREAD_ID_WIDTH_M1-1:0]) == active_id[gen_thread*C_ID_WIDTH+:P_THREAD_ID_WIDTH_M1]); // the requested ID matches the active ID for this thread.
assign s_avalid_en[gen_thread] = // The current request is qualified against this thread slot if
(~aid_match[gen_thread]) || // This thread slot is not active for the requested ID, or
((m_atarget_enc_i == active_target[gen_thread*8+:P_NUM_M_DE_LOG]) && // this outstanding transaction was to the same target and
(m_aregion_i == active_region[gen_thread*8+:4])); // to the same region.
// cmd_push points to the position of either the active thread for the requested ID or the lowest vacant thread slot.
assign accum_push[gen_thread+1] = accum_push[gen_thread] | ~thread_valid[gen_thread];
assign cmd_push[gen_thread] = any_push & (aid_match[gen_thread] | ((~any_aid_match) & ~thread_valid[gen_thread] & ~accum_push[gen_thread]));
// cmd_pop points to the position of the active thread that matches the current RID.
assign rid_match[gen_thread] = thread_valid[gen_thread] & ((s_rid_i[P_THREAD_ID_WIDTH_M1-1:0]) == active_id[gen_thread*C_ID_WIDTH+:P_THREAD_ID_WIDTH_M1]);
assign cmd_pop[gen_thread] = any_pop & rid_match[gen_thread];
always @(posedge ACLK) begin
if (ARESET) begin
active_id[gen_thread*C_ID_WIDTH+:C_ID_WIDTH] <= 0;
active_target[gen_thread*8+:8] <= 0;
active_region[gen_thread*8+:8] <= 0;
active_cnt[gen_thread*8+:8] <= 0;
end else begin
if (cmd_push[gen_thread]) begin
active_id[gen_thread*C_ID_WIDTH+:P_THREAD_ID_WIDTH_M1] <= S_AID[P_THREAD_ID_WIDTH_M1-1:0];
active_target[gen_thread*8+:P_NUM_M_DE_LOG] <= m_atarget_enc_i;
active_region[gen_thread*8+:4] <= m_aregion_i;
if (~cmd_pop[gen_thread]) begin
active_cnt[gen_thread*8+:C_ACCEPTANCE_LOG+1] <= active_cnt[gen_thread*8+:C_ACCEPTANCE_LOG+1] + 1;
end
end else if (cmd_pop[gen_thread]) begin
active_cnt[gen_thread*8+:C_ACCEPTANCE_LOG+1] <= active_cnt[gen_thread*8+:C_ACCEPTANCE_LOG+1] - 1;
end
end
end // Clocked process
if (C_DEBUG) begin : gen_debug_r_multi_thread
// DEBUG READ BEAT COUNTER (only meaningful for R-channel)
always @(posedge ACLK) begin
if (ARESET) begin
debug_r_beat_cnt_i[gen_thread*8+:8] <= 0;
end else if (C_DIR == P_READ) begin
if (s_rvalid_i & S_RREADY & rid_match[gen_thread]) begin
if (s_rlast_i) begin
debug_r_beat_cnt_i[gen_thread*8+:8] <= 0;
end else begin
debug_r_beat_cnt_i[gen_thread*8+:8] <= debug_r_beat_cnt_i[gen_thread*8+:8] + 1;
end
end
end else begin
debug_r_beat_cnt_i[gen_thread*8+:8] <= 0;
end
end // Clocked process
// DEBUG R-CHANNEL TRANSACTION SEQUENCE FIFO
axi_data_fifo_v2_1_axic_srl_fifo #
(
.C_FAMILY (C_FAMILY),
.C_FIFO_WIDTH (8),
.C_FIFO_DEPTH_LOG (C_ACCEPTANCE_LOG+1),
.C_USE_FULL (0)
)
debug_r_seq_fifo_multi_thread
(
.ACLK (ACLK),
.ARESET (ARESET),
.S_MESG (DEBUG_A_TRANS_SEQ),
.S_VALID (cmd_push[gen_thread]),
.S_READY (),
.M_MESG (debug_r_trans_seq_i[gen_thread*8+:8]),
.M_VALID (),
.M_READY (cmd_pop[gen_thread])
);
end // gen_debug_r_multi_thread
end // Next gen_thread_loop
end // thread control
endgenerate
endmodule
`default_nettype wire
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2006 by Wilson Snyder.
`include "verilated.v"
module t_case_write1_tasks ();
// verilator lint_off WIDTH
// verilator lint_off CASEINCOMPLETE
parameter STRLEN = 78;
task ozonerab;
input [6:0] rab;
inout [STRLEN*8:1] foobar;
// verilator no_inline_task
begin
case (rab[6:0])
7'h00 : foobar = {foobar, " 0"};
7'h01 : foobar = {foobar, " 1"};
7'h02 : foobar = {foobar, " 2"};
7'h03 : foobar = {foobar, " 3"};
7'h04 : foobar = {foobar, " 4"};
7'h05 : foobar = {foobar, " 5"};
7'h06 : foobar = {foobar, " 6"};
7'h07 : foobar = {foobar, " 7"};
7'h08 : foobar = {foobar, " 8"};
7'h09 : foobar = {foobar, " 9"};
7'h0a : foobar = {foobar, " 10"};
7'h0b : foobar = {foobar, " 11"};
7'h0c : foobar = {foobar, " 12"};
7'h0d : foobar = {foobar, " 13"};
7'h0e : foobar = {foobar, " 14"};
7'h0f : foobar = {foobar, " 15"};
7'h10 : foobar = {foobar, " 16"};
7'h11 : foobar = {foobar, " 17"};
7'h12 : foobar = {foobar, " 18"};
7'h13 : foobar = {foobar, " 19"};
7'h14 : foobar = {foobar, " 20"};
7'h15 : foobar = {foobar, " 21"};
7'h16 : foobar = {foobar, " 22"};
7'h17 : foobar = {foobar, " 23"};
7'h18 : foobar = {foobar, " 24"};
7'h19 : foobar = {foobar, " 25"};
7'h1a : foobar = {foobar, " 26"};
7'h1b : foobar = {foobar, " 27"};
7'h1c : foobar = {foobar, " 28"};
7'h1d : foobar = {foobar, " 29"};
7'h1e : foobar = {foobar, " 30"};
7'h1f : foobar = {foobar, " 31"};
7'h20 : foobar = {foobar, " 32"};
7'h21 : foobar = {foobar, " 33"};
7'h22 : foobar = {foobar, " 34"};
7'h23 : foobar = {foobar, " 35"};
7'h24 : foobar = {foobar, " 36"};
7'h25 : foobar = {foobar, " 37"};
7'h26 : foobar = {foobar, " 38"};
7'h27 : foobar = {foobar, " 39"};
7'h28 : foobar = {foobar, " 40"};
7'h29 : foobar = {foobar, " 41"};
7'h2a : foobar = {foobar, " 42"};
7'h2b : foobar = {foobar, " 43"};
7'h2c : foobar = {foobar, " 44"};
7'h2d : foobar = {foobar, " 45"};
7'h2e : foobar = {foobar, " 46"};
7'h2f : foobar = {foobar, " 47"};
7'h30 : foobar = {foobar, " 48"};
7'h31 : foobar = {foobar, " 49"};
7'h32 : foobar = {foobar, " 50"};
7'h33 : foobar = {foobar, " 51"};
7'h34 : foobar = {foobar, " 52"};
7'h35 : foobar = {foobar, " 53"};
7'h36 : foobar = {foobar, " 54"};
7'h37 : foobar = {foobar, " 55"};
7'h38 : foobar = {foobar, " 56"};
7'h39 : foobar = {foobar, " 57"};
7'h3a : foobar = {foobar, " 58"};
7'h3b : foobar = {foobar, " 59"};
7'h3c : foobar = {foobar, " 60"};
7'h3d : foobar = {foobar, " 61"};
7'h3e : foobar = {foobar, " 62"};
7'h3f : foobar = {foobar, " 63"};
7'h40 : foobar = {foobar, " 64"};
7'h41 : foobar = {foobar, " 65"};
7'h42 : foobar = {foobar, " 66"};
7'h43 : foobar = {foobar, " 67"};
7'h44 : foobar = {foobar, " 68"};
7'h45 : foobar = {foobar, " 69"};
7'h46 : foobar = {foobar, " 70"};
7'h47 : foobar = {foobar, " 71"};
7'h48 : foobar = {foobar, " 72"};
7'h49 : foobar = {foobar, " 73"};
7'h4a : foobar = {foobar, " 74"};
7'h4b : foobar = {foobar, " 75"};
7'h4c : foobar = {foobar, " 76"};
7'h4d : foobar = {foobar, " 77"};
7'h4e : foobar = {foobar, " 78"};
7'h4f : foobar = {foobar, " 79"};
7'h50 : foobar = {foobar, " 80"};
7'h51 : foobar = {foobar, " 81"};
7'h52 : foobar = {foobar, " 82"};
7'h53 : foobar = {foobar, " 83"};
7'h54 : foobar = {foobar, " 84"};
7'h55 : foobar = {foobar, " 85"};
7'h56 : foobar = {foobar, " 86"};
7'h57 : foobar = {foobar, " 87"};
7'h58 : foobar = {foobar, " 88"};
7'h59 : foobar = {foobar, " 89"};
7'h5a : foobar = {foobar, " 90"};
7'h5b : foobar = {foobar, " 91"};
7'h5c : foobar = {foobar, " 92"};
7'h5d : foobar = {foobar, " 93"};
7'h5e : foobar = {foobar, " 94"};
7'h5f : foobar = {foobar, " 95"};
7'h60 : foobar = {foobar, " 96"};
7'h61 : foobar = {foobar, " 97"};
7'h62 : foobar = {foobar, " 98"};
7'h63 : foobar = {foobar, " 99"};
7'h64 : foobar = {foobar, " 100"};
7'h65 : foobar = {foobar, " 101"};
7'h66 : foobar = {foobar, " 102"};
7'h67 : foobar = {foobar, " 103"};
7'h68 : foobar = {foobar, " 104"};
7'h69 : foobar = {foobar, " 105"};
7'h6a : foobar = {foobar, " 106"};
7'h6b : foobar = {foobar, " 107"};
7'h6c : foobar = {foobar, " 108"};
7'h6d : foobar = {foobar, " 109"};
7'h6e : foobar = {foobar, " 110"};
7'h6f : foobar = {foobar, " 111"};
7'h70 : foobar = {foobar, " 112"};
7'h71 : foobar = {foobar, " 113"};
7'h72 : foobar = {foobar, " 114"};
7'h73 : foobar = {foobar, " 115"};
7'h74 : foobar = {foobar, " 116"};
7'h75 : foobar = {foobar, " 117"};
7'h76 : foobar = {foobar, " 118"};
7'h77 : foobar = {foobar, " 119"};
7'h78 : foobar = {foobar, " 120"};
7'h79 : foobar = {foobar, " 121"};
7'h7a : foobar = {foobar, " 122"};
7'h7b : foobar = {foobar, " 123"};
7'h7c : foobar = {foobar, " 124"};
7'h7d : foobar = {foobar, " 125"};
7'h7e : foobar = {foobar, " 126"};
7'h7f : foobar = {foobar, " 127"};
default:foobar = {foobar, " 128"};
endcase
end
endtask
task ozonerb;
input [5:0] rb;
inout [STRLEN*8: 1] foobar;
// verilator no_inline_task
begin
case (rb[5:0])
6'h10,
6'h17,
6'h1e,
6'h1f: foobar = {foobar, " 129"};
default: ozonerab({1'b1, rb}, foobar);
endcase
end
endtask
task ozonef3f4_iext;
input [1:0] foo;
input [15:0] im16;
inout [STRLEN*8: 1] foobar;
// verilator no_inline_task
begin
case (foo)
2'h0 :
begin
skyway({4{im16[15]}}, foobar);
skyway({4{im16[15]}}, foobar);
skyway(im16[15:12], foobar);
skyway(im16[11: 8], foobar);
skyway(im16[ 7: 4], foobar);
skyway(im16[ 3:0], foobar);
foobar = {foobar, " 130"};
end
2'h1 :
begin
foobar = {foobar, " 131"};
skyway(im16[15:12], foobar);
skyway(im16[11: 8], foobar);
skyway(im16[ 7: 4], foobar);
skyway(im16[ 3:0], foobar);
end
2'h2 :
begin
skyway({4{im16[15]}}, foobar);
skyway({4{im16[15]}}, foobar);
skyway(im16[15:12], foobar);
skyway(im16[11: 8], foobar);
skyway(im16[ 7: 4], foobar);
skyway(im16[ 3:0], foobar);
foobar = {foobar, " 132"};
end
2'h3 :
begin
foobar = {foobar, " 133"};
skyway(im16[15:12], foobar);
skyway(im16[11: 8], foobar);
skyway(im16[ 7: 4], foobar);
skyway(im16[ 3:0], foobar);
end
endcase
end
endtask
task skyway;
input [ 3:0] hex;
inout [STRLEN*8: 1] foobar;
// verilator no_inline_task
begin
case (hex)
4'h0 : foobar = {foobar, " 134"};
4'h1 : foobar = {foobar, " 135"};
4'h2 : foobar = {foobar, " 136"};
4'h3 : foobar = {foobar, " 137"};
4'h4 : foobar = {foobar, " 138"};
4'h5 : foobar = {foobar, " 139"};
4'h6 : foobar = {foobar, " 140"};
4'h7 : foobar = {foobar, " 141"};
4'h8 : foobar = {foobar, " 142"};
4'h9 : foobar = {foobar, " 143"};
4'ha : foobar = {foobar, " 144"};
4'hb : foobar = {foobar, " 145"};
4'hc : foobar = {foobar, " 146"};
4'hd : foobar = {foobar, " 147"};
4'he : foobar = {foobar, " 148"};
4'hf : foobar = {foobar, " 149"};
endcase
end
endtask
task ozonesr;
input [ 15:0] foo;
inout [STRLEN*8: 1] foobar;
// verilator no_inline_task
begin
case (foo[11: 9])
3'h0 : foobar = {foobar, " 158"};
3'h1 : foobar = {foobar, " 159"};
3'h2 : foobar = {foobar, " 160"};
3'h3 : foobar = {foobar, " 161"};
3'h4 : foobar = {foobar, " 162"};
3'h5 : foobar = {foobar, " 163"};
3'h6 : foobar = {foobar, " 164"};
3'h7 : foobar = {foobar, " 165"};
endcase
end
endtask
task ozonejk;
input k;
inout [STRLEN*8: 1] foobar;
// verilator no_inline_task
begin
if (k)
foobar = {foobar, " 166"};
else
foobar = {foobar, " 167"};
end
endtask
task ozoneae;
input [ 2:0] ae;
inout [STRLEN*8: 1] foobar;
// verilator no_inline_task
begin
case (ae)
3'b000 : foobar = {foobar, " 168"};
3'b001 : foobar = {foobar, " 169"};
3'b010 : foobar = {foobar, " 170"};
3'b011 : foobar = {foobar, " 171"};
3'b100 : foobar = {foobar, " 172"};
3'b101 : foobar = {foobar, " 173"};
3'b110 : foobar = {foobar, " 174"};
3'b111 : foobar = {foobar, " 175"};
endcase
end
endtask
task ozoneaee;
input [ 2:0] aee;
inout [STRLEN*8: 1] foobar;
// verilator no_inline_task
begin
case (aee)
3'b001,
3'b011,
3'b101,
3'b111 : foobar = {foobar, " 176"};
3'b000 : foobar = {foobar, " 177"};
3'b010 : foobar = {foobar, " 178"};
3'b100 : foobar = {foobar, " 179"};
3'b110 : foobar = {foobar, " 180"};
endcase
end
endtask
task ozoneape;
input [ 2:0] ape;
inout [STRLEN*8: 1] foobar;
// verilator no_inline_task
begin
case (ape)
3'b001,
3'b011,
3'b101,
3'b111 : foobar = {foobar, " 181"};
3'b000 : foobar = {foobar, " 182"};
3'b010 : foobar = {foobar, " 183"};
3'b100 : foobar = {foobar, " 184"};
3'b110 : foobar = {foobar, " 185"};
endcase
end
endtask
task ozonef1;
input [ 31:0] foo;
inout [STRLEN*8: 1] foobar;
// verilator no_inline_task
begin
case (foo[24:21])
4'h0 :
if (foo[26])
foobar = {foobar, " 186"};
else
foobar = {foobar, " 187"};
4'h1 :
case (foo[26:25])
2'b00 : foobar = {foobar, " 188"};
2'b01 : foobar = {foobar, " 189"};
2'b10 : foobar = {foobar, " 190"};
2'b11 : foobar = {foobar, " 191"};
endcase
4'h2 : foobar = {foobar, " 192"};
4'h3 :
case (foo[26:25])
2'b00 : foobar = {foobar, " 193"};
2'b01 : foobar = {foobar, " 194"};
2'b10 : foobar = {foobar, " 195"};
2'b11 : foobar = {foobar, " 196"};
endcase
4'h4 :
if (foo[26])
foobar = {foobar, " 197"};
else
foobar = {foobar, " 198"};
4'h5 :
case (foo[26:25])
2'b00 : foobar = {foobar, " 199"};
2'b01 : foobar = {foobar, " 200"};
2'b10 : foobar = {foobar, " 201"};
2'b11 : foobar = {foobar, " 202"};
endcase
4'h6 : foobar = {foobar, " 203"};
4'h7 :
case (foo[26:25])
2'b00 : foobar = {foobar, " 204"};
2'b01 : foobar = {foobar, " 205"};
2'b10 : foobar = {foobar, " 206"};
2'b11 : foobar = {foobar, " 207"};
endcase
4'h8 :
case (foo[26:25])
2'b00 : foobar = {foobar, " 208"};
2'b01 : foobar = {foobar, " 209"};
2'b10 : foobar = {foobar, " 210"};
2'b11 : foobar = {foobar, " 211"};
endcase
4'h9 :
case (foo[26:25])
2'b00 : foobar = {foobar, " 212"};
2'b01 : foobar = {foobar, " 213"};
2'b10 : foobar = {foobar, " 214"};
2'b11 : foobar = {foobar, " 215"};
endcase
4'ha :
if (foo[25])
foobar = {foobar, " 216"};
else
foobar = {foobar, " 217"};
4'hb :
if (foo[25])
foobar = {foobar, " 218"};
else
foobar = {foobar, " 219"};
4'hc :
if (foo[26])
foobar = {foobar, " 220"};
else
foobar = {foobar, " 221"};
4'hd :
case (foo[26:25])
2'b00 : foobar = {foobar, " 222"};
2'b01 : foobar = {foobar, " 223"};
2'b10 : foobar = {foobar, " 224"};
2'b11 : foobar = {foobar, " 225"};
endcase
4'he :
case (foo[26:25])
2'b00 : foobar = {foobar, " 226"};
2'b01 : foobar = {foobar, " 227"};
2'b10 : foobar = {foobar, " 228"};
2'b11 : foobar = {foobar, " 229"};
endcase
4'hf :
case (foo[26:25])
2'b00 : foobar = {foobar, " 230"};
2'b01 : foobar = {foobar, " 231"};
2'b10 : foobar = {foobar, " 232"};
2'b11 : foobar = {foobar, " 233"};
endcase
endcase
end
endtask
task ozonef1e;
input [ 31:0] foo;
inout [STRLEN*8: 1] foobar;
// verilator no_inline_task
begin
case (foo[27:21])
7'h00:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 234"};
foobar = {foobar, " 235"};
end
7'h01:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 236"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 237"};
foobar = {foobar, " 238"};
end
7'h02:
foobar = {foobar, " 239"};
7'h03:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 240"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 241"};
foobar = {foobar, " 242"};
end
7'h04:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 243"};
foobar = {foobar," 244"};
end
7'h05:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 245"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 246"};
end
7'h06:
foobar = {foobar, " 247"};
7'h07:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 248"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 249"};
end
7'h08:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 250"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 251"};
end
7'h09:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 252"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 253"};
end
7'h0a:
begin
ozoneae(foo[17:15], foobar);
foobar = {foobar," 254"};
end
7'h0b:
begin
ozoneae(foo[17:15], foobar);
foobar = {foobar," 255"};
end
7'h0c:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 256"};
end
7'h0d:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 257"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 258"};
end
7'h0e:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 259"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 260"};
end
7'h0f:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 261"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 262"};
end
7'h10:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 263"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 264"};
foobar = {foobar, " 265"};
foobar = {foobar, " 266"};
end
7'h11:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 267"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 268"};
foobar = {foobar, " 269"};
foobar = {foobar, " 270"};
end
7'h12:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 271"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 272"};
foobar = {foobar, " 273"};
foobar = {foobar, " 274"};
end
7'h13:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 275"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 276"};
foobar = {foobar, " 277"};
foobar = {foobar, " 278"};
end
7'h14:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 279"};
ozoneaee(foo[17:15], foobar);
foobar = {foobar," 280"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 281"};
ozoneape(foo[17:15], foobar);
foobar = {foobar," 282"};
foobar = {foobar, " 283"};
foobar = {foobar, " 284"};
end
7'h15:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 285"};
ozoneaee(foo[17:15], foobar);
foobar = {foobar," 286"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 287"};
ozoneape(foo[17:15], foobar);
foobar = {foobar," 288"};
foobar = {foobar, " 289"};
foobar = {foobar, " 290"};
end
7'h16:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 291"};
ozoneaee(foo[17:15], foobar);
foobar = {foobar," 292"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 293"};
ozoneape(foo[17:15], foobar);
foobar = {foobar," 294"};
foobar = {foobar, " 295"};
foobar = {foobar, " 296"};
end
7'h17:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 297"};
ozoneaee(foo[17:15], foobar);
foobar = {foobar," 298"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 299"};
ozoneape(foo[17:15], foobar);
foobar = {foobar," 300"};
foobar = {foobar, " 301"};
foobar = {foobar, " 302"};
end
7'h18:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 303"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 304"};
foobar = {foobar, " 305"};
foobar = {foobar, " 306"};
end
7'h19:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 307"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 308"};
foobar = {foobar, " 309"};
foobar = {foobar, " 310"};
end
7'h1a:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 311"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 312"};
foobar = {foobar, " 313"};
foobar = {foobar, " 314"};
end
7'h1b:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 315"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 316"};
foobar = {foobar, " 317"};
foobar = {foobar, " 318"};
end
7'h1c:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 319"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 320"};
foobar = {foobar, " 321"};
foobar = {foobar, " 322"};
end
7'h1d:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 323"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 324"};
foobar = {foobar, " 325"};
foobar = {foobar, " 326"};
end
7'h1e:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 327"};
ozoneaee(foo[17:15], foobar);
foobar = {foobar," 328"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 329"};
ozoneape(foo[17:15], foobar);
foobar = {foobar," 330"};
foobar = {foobar, " 331"};
foobar = {foobar, " 332"};
end
7'h1f:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 333"};
ozoneaee(foo[17:15], foobar);
foobar = {foobar," 334"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 335"};
ozoneape(foo[17:15], foobar);
foobar = {foobar," 336"};
foobar = {foobar, " 337"};
foobar = {foobar, " 338"};
end
7'h20:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 339"};
ozoneaee(foo[17:15], foobar);
foobar = {foobar," 340"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 341"};
ozoneape(foo[17:15], foobar);
foobar = {foobar," 342"};
foobar = {foobar, " 343"};
foobar = {foobar, " 344"};
end
7'h21:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 345"};
ozoneaee(foo[17:15], foobar);
foobar = {foobar," 346"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 347"};
ozoneape(foo[17:15], foobar);
foobar = {foobar," 348"};
foobar = {foobar, " 349"};
foobar = {foobar, " 350"};
end
7'h22:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 351"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 352"};
foobar = {foobar, " 353"};
foobar = {foobar, " 354"};
end
7'h23:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 355"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 356"};
foobar = {foobar, " 357"};
foobar = {foobar, " 358"};
end
7'h24:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 359"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 360"};
foobar = {foobar, " 361"};
foobar = {foobar, " 362"};
end
7'h25:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 363"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 364"};
foobar = {foobar, " 365"};
foobar = {foobar, " 366"};
end
7'h26:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 367"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 368"};
foobar = {foobar, " 369"};
foobar = {foobar, " 370"};
end
7'h27:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 371"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 372"};
foobar = {foobar, " 373"};
foobar = {foobar, " 374"};
end
7'h28:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 375"};
ozoneaee(foo[17:15], foobar);
foobar = {foobar," 376"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 377"};
ozoneape(foo[17:15], foobar);
foobar = {foobar," 378"};
foobar = {foobar, " 379"};
foobar = {foobar, " 380"};
end
7'h29:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 381"};
ozoneaee(foo[17:15], foobar);
foobar = {foobar," 382"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 383"};
ozoneape(foo[17:15], foobar);
foobar = {foobar," 384"};
foobar = {foobar, " 385"};
foobar = {foobar, " 386"};
end
7'h2a:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 387"};
ozoneaee(foo[17:15], foobar);
foobar = {foobar," 388"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 389"};
ozoneape(foo[17:15], foobar);
foobar = {foobar," 390"};
foobar = {foobar, " 391"};
foobar = {foobar, " 392"};
end
7'h2b:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 393"};
ozoneaee(foo[17:15], foobar);
foobar = {foobar," 394"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 395"};
ozoneape(foo[17:15], foobar);
foobar = {foobar," 396"};
foobar = {foobar, " 397"};
foobar = {foobar, " 398"};
end
7'h2c:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 399"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 400"};
foobar = {foobar, " 401"};
foobar = {foobar, " 402"};
end
7'h2d:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 403"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 404"};
foobar = {foobar, " 405"};
foobar = {foobar, " 406"};
end
7'h2e:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 407"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 408"};
foobar = {foobar, " 409"};
foobar = {foobar, " 410"};
end
7'h2f:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 411"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 412"};
foobar = {foobar, " 413"};
foobar = {foobar, " 414"};
end
7'h30:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 415"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 416"};
foobar = {foobar, " 417"};
foobar = {foobar, " 418"};
end
7'h31:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 419"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 420"};
foobar = {foobar, " 421"};
foobar = {foobar, " 422"};
end
7'h32:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 423"};
ozoneaee(foo[17:15], foobar);
foobar = {foobar," 424"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 425"};
ozoneape(foo[17:15], foobar);
foobar = {foobar," 426"};
foobar = {foobar, " 427"};
foobar = {foobar, " 428"};
end
7'h33:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 429"};
ozoneaee(foo[17:15], foobar);
foobar = {foobar," 430"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 431"};
ozoneape(foo[17:15], foobar);
foobar = {foobar," 432"};
foobar = {foobar, " 433"};
foobar = {foobar, " 434"};
end
7'h34:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 435"};
ozoneaee(foo[17:15], foobar);
foobar = {foobar," 436"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 437"};
ozoneape(foo[17:15], foobar);
foobar = {foobar," 438"};
foobar = {foobar, " 439"};
foobar = {foobar, " 440"};
end
7'h35:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 441"};
ozoneaee(foo[17:15], foobar);
foobar = {foobar," 442"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 443"};
ozoneape(foo[17:15], foobar);
foobar = {foobar," 444"};
foobar = {foobar, " 445"};
foobar = {foobar, " 446"};
end
7'h36:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 447"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 448"};
foobar = {foobar, " 449"};
foobar = {foobar, " 450"};
end
7'h37:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 451"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 452"};
foobar = {foobar, " 453"};
foobar = {foobar, " 454"};
end
7'h38:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 455"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 456"};
foobar = {foobar, " 457"};
end
7'h39:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 458"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 459"};
foobar = {foobar, " 460"};
end
7'h3a:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 461"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 462"};
foobar = {foobar, " 463"};
end
7'h3b:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 464"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 465"};
foobar = {foobar, " 466"};
end
7'h3c:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 467"};
ozoneaee(foo[17:15], foobar);
foobar = {foobar," 468"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 469"};
ozoneape(foo[17:15], foobar);
foobar = {foobar," 470"};
foobar = {foobar, " 471"};
end
7'h3d:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 472"};
ozoneaee(foo[17:15], foobar);
foobar = {foobar," 473"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 474"};
ozoneape(foo[17:15], foobar);
foobar = {foobar," 475"};
foobar = {foobar, " 476"};
end
7'h3e:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 477"};
ozoneaee(foo[17:15], foobar);
foobar = {foobar," 478"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 479"};
ozoneape(foo[17:15], foobar);
foobar = {foobar," 480"};
foobar = {foobar, " 481"};
end
7'h3f:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 482"};
ozoneaee(foo[17:15], foobar);
foobar = {foobar," 483"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 484"};
ozoneape(foo[17:15], foobar);
foobar = {foobar," 485"};
foobar = {foobar, " 486"};
end
7'h40:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 487"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 488"};
foobar = {foobar, " 489"};
foobar = {foobar, " 490"};
end
7'h41:
begin
foobar = {foobar, " 491"};
foobar = {foobar, " 492"};
end
7'h42:
begin
foobar = {foobar, " 493"};
foobar = {foobar, " 494"};
end
7'h43:
begin
foobar = {foobar, " 495"};
foobar = {foobar, " 496"};
end
7'h44:
begin
foobar = {foobar, " 497"};
foobar = {foobar, " 498"};
end
7'h45:
foobar = {foobar, " 499"};
7'h46:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 500"};
foobar = {foobar, " 501"};
foobar = {foobar, " 502"};
end
7'h47:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 503"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 504"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 505"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 506"};
foobar = {foobar, " 507"};
foobar = {foobar, " 508"};
end
7'h48:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 509"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 510"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 511"};
ozoneaee(foo[17:15], foobar);
foobar = {foobar," 512"};
ozoneape(foo[17:15], foobar);
foobar = {foobar," 513"};
end
7'h49:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 514"};
ozoneaee(foo[17:15], foobar);
foobar = {foobar," 515"};
ozoneape(foo[17:15], foobar);
foobar = {foobar," 516"};
end
7'h4a:
foobar = {foobar," 517"};
7'h4b:
foobar = {foobar, " 518"};
7'h4c:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 519"};
foobar = {foobar, " 520"};
foobar = {foobar, " 521"};
end
7'h4d:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 522"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 523"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 524"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 525"};
foobar = {foobar, " 526"};
foobar = {foobar, " 527"};
end
7'h4e:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 528"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 529"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 530"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 531"};
end
7'h4f:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 532"};
end
7'h50:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 533"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 534"};
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 535"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 536"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 537"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 538"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 539"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 540"};
end
7'h51:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 541"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 542"};
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 543"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 544"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 545"};
end
7'h52:
foobar = {foobar, " 546"};
7'h53:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar, " 547"};
end
7'h54:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 548"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 549"};
end
7'h55:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 550"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 551"};
end
7'h56:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 552"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 553"};
foobar = {foobar, " 554"};
end
7'h57:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 555"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 556"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 557"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 558"};
end
7'h58:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar, " 559"};
end
7'h59:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 560"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 561"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 562"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 563"};
end
7'h5a:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 564"};
ozoneae(foo[17:15], foobar);
foobar = {foobar, " 565"};
end
7'h5b:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 566"};
ozoneae(foo[17:15], foobar);
foobar = {foobar, " 567"};
end
7'h5c:
begin
foobar = {foobar," 568"};
ozoneape(foo[17:15], foobar);
foobar = {foobar," 569"};
foobar = {foobar," 570"};
ozoneape(foo[17:15], foobar);
foobar = {foobar," 571"};
ozoneae(foo[20:18], foobar);
foobar = {foobar," 572"};
ozoneaee(foo[17:15], foobar);
foobar = {foobar, " 573"};
end
7'h5d:
begin
foobar = {foobar," 574"};
ozoneape(foo[17:15], foobar);
foobar = {foobar," 575"};
foobar = {foobar," 576"};
ozoneape(foo[17:15], foobar);
foobar = {foobar," 577"};
ozoneae(foo[20:18], foobar);
foobar = {foobar," 578"};
ozoneaee(foo[17:15], foobar);
foobar = {foobar, " 579"};
end
7'h5e:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 580"};
ozoneae(foo[17:15], foobar);
foobar = {foobar, " 581"};
end
7'h5f:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 582"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 583"};
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 584"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 585"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 586"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 587"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 588"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 589"};
end
7'h60:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 590"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 591"};
end
7'h61:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 592"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 593"};
end
7'h62:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 594"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 595"};
end
7'h63:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 596"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 597"};
end
7'h64:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 598"};
ozoneaee(foo[17:15], foobar);
foobar = {foobar," 599"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 600"};
ozoneape(foo[17:15], foobar);
foobar = {foobar," 601"};
end
7'h65:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 602"};
ozoneaee(foo[17:15], foobar);
foobar = {foobar," 603"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 604"};
ozoneape(foo[17:15], foobar);
foobar = {foobar," 605"};
end
7'h66:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 606"};
ozoneaee(foo[17:15], foobar);
foobar = {foobar," 607"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 608"};
ozoneape(foo[17:15], foobar);
foobar = {foobar," 609"};
end
7'h67:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 610"};
ozoneaee(foo[17:15], foobar);
foobar = {foobar," 611"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 612"};
ozoneape(foo[17:15], foobar);
foobar = {foobar," 613"};
end
7'h68:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 614"};
ozoneaee(foo[17:15], foobar);
foobar = {foobar," 615"};
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 616"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 617"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 618"};
ozoneape(foo[17:15], foobar);
end
7'h69:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 619"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 620"};
ozoneae(foo[20:18], foobar);
foobar = {foobar," 621"};
end
7'h6a:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 622"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 623"};
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 624"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 625"};
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 626"};
ozoneae(foo[17:15], foobar);
end
7'h6b:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 627"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 628"};
ozoneae(foo[20:18], foobar);
foobar = {foobar," 629"};
end
7'h6c:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 630"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 631"};
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 632"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 633"};
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 634"};
ozoneae(foo[17:15], foobar);
end
7'h6d:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 635"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 636"};
ozoneae(foo[20:18], foobar);
foobar = {foobar," 637"};
end
7'h6e:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 638"};
ozoneaee(foo[17:15], foobar);
foobar = {foobar," 639"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 640"};
ozoneape(foo[17:15], foobar);
foobar = {foobar," 641"};
end
7'h6f:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 642"};
ozoneaee(foo[17:15], foobar);
foobar = {foobar," 643"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 644"};
ozoneape(foo[17:15], foobar);
foobar = {foobar," 645"};
end
7'h70:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 646"};
ozoneae(foo[20:18], foobar);
foobar = {foobar," 647"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 648"};
ozoneae(foo[17:15], foobar);
foobar = {foobar, " 649"};
end
7'h71:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 650"};
ozoneae(foo[17:15], foobar);
foobar = {foobar, " 651"};
end
7'h72:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 652"};
ozoneae(foo[17:15], foobar);
foobar = {foobar, " 653"};
end
7'h73:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 654"};
ozoneae(foo[20:18], foobar);
foobar = {foobar," 655"};
ozoneae(foo[17:15], foobar);
end
7'h74:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 656"};
ozoneae(foo[20:18], foobar);
foobar = {foobar," 657"};
ozoneae(foo[17:15], foobar);
end
7'h75:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 658"};
ozoneaee(foo[17:15], foobar);
foobar = {foobar," 659"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 660"};
ozoneape(foo[17:15], foobar);
foobar = {foobar," 661"};
foobar = {foobar, " 662"};
foobar = {foobar, " 663"};
end
7'h76:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 664"};
ozoneaee(foo[17:15], foobar);
foobar = {foobar," 665"};
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 666"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 667"};
ozoneape(foo[17:15], foobar);
foobar = {foobar," 668"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 669"};
end
7'h77:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 670"};
ozoneaee(foo[17:15], foobar);
foobar = {foobar," 671"};
ozoneaee(foo[17:15], foobar);
foobar = {foobar," 672"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 673"};
ozoneape(foo[17:15], foobar);
foobar = {foobar," 674"};
ozoneape(foo[17:15], foobar);
foobar = {foobar," 675"};
end
7'h78,
7'h79,
7'h7a,
7'h7b,
7'h7c,
7'h7d,
7'h7e,
7'h7f:
foobar = {foobar," 676"};
endcase
end
endtask
task ozonef2;
input [ 31:0] foo;
inout [STRLEN*8: 1] foobar;
// verilator no_inline_task
begin
case (foo[24:21])
4'h0 :
case (foo[26:25])
2'b00 : foobar = {foobar," 677"};
2'b01 : foobar = {foobar," 678"};
2'b10 : foobar = {foobar," 679"};
2'b11 : foobar = {foobar," 680"};
endcase
4'h1 :
case (foo[26:25])
2'b00 : foobar = {foobar," 681"};
2'b01 : foobar = {foobar," 682"};
2'b10 : foobar = {foobar," 683"};
2'b11 : foobar = {foobar," 684"};
endcase
4'h2 :
case (foo[26:25])
2'b00 : foobar = {foobar," 685"};
2'b01 : foobar = {foobar," 686"};
2'b10 : foobar = {foobar," 687"};
2'b11 : foobar = {foobar," 688"};
endcase
4'h3 :
case (foo[26:25])
2'b00 : foobar = {foobar," 689"};
2'b01 : foobar = {foobar," 690"};
2'b10 : foobar = {foobar," 691"};
2'b11 : foobar = {foobar," 692"};
endcase
4'h4 :
case (foo[26:25])
2'b00 : foobar = {foobar," 693"};
2'b01 : foobar = {foobar," 694"};
2'b10 : foobar = {foobar," 695"};
2'b11 : foobar = {foobar," 696"};
endcase
4'h5 :
case (foo[26:25])
2'b00 : foobar = {foobar," 697"};
2'b01 : foobar = {foobar," 698"};
2'b10 : foobar = {foobar," 699"};
2'b11 : foobar = {foobar," 700"};
endcase
4'h6 :
case (foo[26:25])
2'b00 : foobar = {foobar," 701"};
2'b01 : foobar = {foobar," 702"};
2'b10 : foobar = {foobar," 703"};
2'b11 : foobar = {foobar," 704"};
endcase
4'h7 :
case (foo[26:25])
2'b00 : foobar = {foobar," 705"};
2'b01 : foobar = {foobar," 706"};
2'b10 : foobar = {foobar," 707"};
2'b11 : foobar = {foobar," 708"};
endcase
4'h8 :
if (foo[26])
foobar = {foobar," 709"};
else
foobar = {foobar," 710"};
4'h9 :
case (foo[26:25])
2'b00 : foobar = {foobar," 711"};
2'b01 : foobar = {foobar," 712"};
2'b10 : foobar = {foobar," 713"};
2'b11 : foobar = {foobar," 714"};
endcase
4'ha :
case (foo[26:25])
2'b00 : foobar = {foobar," 715"};
2'b01 : foobar = {foobar," 716"};
2'b10 : foobar = {foobar," 717"};
2'b11 : foobar = {foobar," 718"};
endcase
4'hb :
case (foo[26:25])
2'b00 : foobar = {foobar," 719"};
2'b01 : foobar = {foobar," 720"};
2'b10 : foobar = {foobar," 721"};
2'b11 : foobar = {foobar," 722"};
endcase
4'hc :
if (foo[26])
foobar = {foobar," 723"};
else
foobar = {foobar," 724"};
4'hd :
case (foo[26:25])
2'b00 : foobar = {foobar," 725"};
2'b01 : foobar = {foobar," 726"};
2'b10 : foobar = {foobar," 727"};
2'b11 : foobar = {foobar," 728"};
endcase
4'he :
case (foo[26:25])
2'b00 : foobar = {foobar," 729"};
2'b01 : foobar = {foobar," 730"};
2'b10 : foobar = {foobar," 731"};
2'b11 : foobar = {foobar," 732"};
endcase
4'hf :
case (foo[26:25])
2'b00 : foobar = {foobar," 733"};
2'b01 : foobar = {foobar," 734"};
2'b10 : foobar = {foobar," 735"};
2'b11 : foobar = {foobar," 736"};
endcase
endcase
end
endtask
task ozonef2e;
input [ 31:0] foo;
inout [STRLEN*8: 1] foobar;
// verilator no_inline_task
begin
casez (foo[25:21])
5'h00 :
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 737"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 738"};
end
5'h01 :
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 739"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 740"};
end
5'h02 :
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 741"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 742"};
end
5'h03 :
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 743"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 744"};
end
5'h04 :
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 745"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 746"};
end
5'h05 :
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 747"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 748"};
end
5'h06 :
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 749"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 750"};
end
5'h07 :
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 751"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 752"};
end
5'h08 :
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 753"};
if (foo[ 6])
foobar = {foobar," 754"};
else
foobar = {foobar," 755"};
end
5'h09 :
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 756"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 757"};
end
5'h0a :
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 758"};
ozoneae(foo[17:15], foobar);
end
5'h0b :
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 759"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 760"};
end
5'h0c :
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 761"};
end
5'h0d :
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 762"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 763"};
end
5'h0e :
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 764"};
ozoneae(foo[17:15], foobar);
end
5'h0f :
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 765"};
ozoneae(foo[17:15], foobar);
end
5'h10 :
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 766"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 767"};
end
5'h11 :
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 768"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 769"};
end
5'h18 :
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 770"};
if (foo[ 6])
foobar = {foobar," 771"};
else
foobar = {foobar," 772"};
end
5'h1a :
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 773"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 774"};
end
5'h1b :
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 775"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 776"};
if (foo[ 6])
foobar = {foobar," 777"};
else
foobar = {foobar," 778"};
foobar = {foobar," 779"};
end
5'h1c :
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 780"};
end
5'h1d :
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 781"};
if (foo[ 6])
foobar = {foobar," 782"};
else
foobar = {foobar," 783"};
foobar = {foobar," 784"};
end
5'h1e :
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 785"};
if (foo[ 6])
foobar = {foobar," 786"};
else
foobar = {foobar," 787"};
foobar = {foobar," 788"};
end
5'h1f :
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 789"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 790"};
if (foo[ 6])
foobar = {foobar," 791"};
else
foobar = {foobar," 792"};
foobar = {foobar," 793"};
end
default :
foobar = {foobar," 794"};
endcase
end
endtask
task ozonef3e;
input [ 31:0] foo;
inout [STRLEN*8: 1] foobar;
// verilator no_inline_task
begin
case (foo[25:21])
5'h00,
5'h01,
5'h02:
begin
ozoneae(foo[20:18], foobar);
case (foo[22:21])
2'h0: foobar = {foobar," 795"};
2'h1: foobar = {foobar," 796"};
2'h2: foobar = {foobar," 797"};
endcase
ozoneae(foo[17:15], foobar);
foobar = {foobar," 798"};
if (foo[ 9])
ozoneae(foo[ 8: 6], foobar);
else
ozonef3e_te(foo[ 8: 6], foobar);
foobar = {foobar," 799"};
end
5'h08,
5'h09,
5'h0d,
5'h0e,
5'h0f:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 800"};
ozoneae(foo[17:15], foobar);
case (foo[23:21])
3'h0: foobar = {foobar," 801"};
3'h1: foobar = {foobar," 802"};
3'h5: foobar = {foobar," 803"};
3'h6: foobar = {foobar," 804"};
3'h7: foobar = {foobar," 805"};
endcase
if (foo[ 9])
ozoneae(foo[ 8: 6], foobar);
else
ozonef3e_te(foo[ 8: 6], foobar);
end
5'h0a,
5'h0b:
begin
ozoneae(foo[17:15], foobar);
if (foo[21])
foobar = {foobar," 806"};
else
foobar = {foobar," 807"};
if (foo[ 9])
ozoneae(foo[ 8: 6], foobar);
else
ozonef3e_te(foo[ 8: 6], foobar);
end
5'h0c:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 808"};
if (foo[ 9])
ozoneae(foo[ 8: 6], foobar);
else
ozonef3e_te(foo[ 8: 6], foobar);
foobar = {foobar," 809"};
ozoneae(foo[17:15], foobar);
end
5'h10,
5'h11,
5'h12,
5'h13:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 810"};
ozoneae(foo[17:15], foobar);
case (foo[22:21])
2'h0,
2'h2:
foobar = {foobar," 811"};
2'h1,
2'h3:
foobar = {foobar," 812"};
endcase
ozoneae(foo[ 8: 6], foobar);
foobar = {foobar," 813"};
ozoneae((foo[20:18]+1), foobar);
foobar = {foobar," 814"};
ozoneae((foo[17:15]+1), foobar);
case (foo[22:21])
2'h0,
2'h3:
foobar = {foobar," 815"};
2'h1,
2'h2:
foobar = {foobar," 816"};
endcase
ozoneae((foo[ 8: 6]+1), foobar);
end
5'h18:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 817"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 818"};
ozoneae(foo[ 8: 6], foobar);
foobar = {foobar," 819"};
ozoneae(foo[20:18], foobar);
foobar = {foobar," 820"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 821"};
ozoneae(foo[ 8: 6], foobar);
end
default :
foobar = {foobar," 822"};
endcase
end
endtask
task ozonef3e_te;
input [ 2:0] te;
inout [STRLEN*8: 1] foobar;
// verilator no_inline_task
begin
case (te)
3'b100 : foobar = {foobar, " 823"};
3'b101 : foobar = {foobar, " 824"};
3'b110 : foobar = {foobar, " 825"};
default: foobar = {foobar, " 826"};
endcase
end
endtask
task ozonearm;
input [ 2:0] ate;
inout [STRLEN*8: 1] foobar;
// verilator no_inline_task
begin
case (ate)
3'b000 : foobar = {foobar, " 827"};
3'b001 : foobar = {foobar, " 828"};
3'b010 : foobar = {foobar, " 829"};
3'b011 : foobar = {foobar, " 830"};
3'b100 : foobar = {foobar, " 831"};
3'b101 : foobar = {foobar, " 832"};
3'b110 : foobar = {foobar, " 833"};
3'b111 : foobar = {foobar, " 834"};
endcase
end
endtask
task ozonebmuop;
input [ 4:0] f4;
inout [STRLEN*8: 1] foobar;
// verilator no_inline_task
begin
case (f4[ 4:0])
5'h00,
5'h04 :
foobar = {foobar, " 835"};
5'h01,
5'h05 :
foobar = {foobar, " 836"};
5'h02,
5'h06 :
foobar = {foobar, " 837"};
5'h03,
5'h07 :
foobar = {foobar, " 838"};
5'h08,
5'h18 :
foobar = {foobar, " 839"};
5'h09,
5'h19 :
foobar = {foobar, " 840"};
5'h0a,
5'h1a :
foobar = {foobar, " 841"};
5'h0b :
foobar = {foobar, " 842"};
5'h1b :
foobar = {foobar, " 843"};
5'h0c,
5'h1c :
foobar = {foobar, " 844"};
5'h0d,
5'h1d :
foobar = {foobar, " 845"};
5'h1e :
foobar = {foobar, " 846"};
endcase
end
endtask
task ozonef3;
input [ 31:0] foo;
inout [STRLEN*8: 1] foobar;
reg nacho;
// verilator no_inline_task
begin : f3_body
nacho = 1'b0;
case (foo[24:21])
4'h0:
case (foo[26:25])
2'b00 : foobar = {foobar, " 847"};
2'b01 : foobar = {foobar, " 848"};
2'b10 : foobar = {foobar, " 849"};
2'b11 : foobar = {foobar, " 850"};
endcase
4'h1:
case (foo[26:25])
2'b00 : foobar = {foobar, " 851"};
2'b01 : foobar = {foobar, " 852"};
2'b10 : foobar = {foobar, " 853"};
2'b11 : foobar = {foobar, " 854"};
endcase
4'h2:
case (foo[26:25])
2'b00 : foobar = {foobar, " 855"};
2'b01 : foobar = {foobar, " 856"};
2'b10 : foobar = {foobar, " 857"};
2'b11 : foobar = {foobar, " 858"};
endcase
4'h8,
4'h9,
4'hd,
4'he,
4'hf :
case (foo[26:25])
2'b00 : foobar = {foobar, " 859"};
2'b01 : foobar = {foobar, " 860"};
2'b10 : foobar = {foobar, " 861"};
2'b11 : foobar = {foobar, " 862"};
endcase
4'ha,
4'hb :
if (foo[25])
foobar = {foobar, " 863"};
else
foobar = {foobar, " 864"};
4'hc :
if (foo[26])
foobar = {foobar, " 865"};
else
foobar = {foobar, " 866"};
default :
begin
foobar = {foobar, " 867"};
nacho = 1'b1;
end
endcase
if (~nacho)
begin
case (foo[24:21])
4'h8 :
foobar = {foobar, " 868"};
4'h9 :
foobar = {foobar, " 869"};
4'ha,
4'he :
foobar = {foobar, " 870"};
4'hb,
4'hf :
foobar = {foobar, " 871"};
4'hd :
foobar = {foobar, " 872"};
endcase
if (foo[20])
case (foo[18:16])
3'b000 : foobar = {foobar, " 873"};
3'b100 : foobar = {foobar, " 874"};
default: foobar = {foobar, " 875"};
endcase
else
ozoneae(foo[18:16], foobar);
if (foo[24:21] === 4'hc)
if (foo[25])
foobar = {foobar, " 876"};
else
foobar = {foobar, " 877"};
case (foo[24:21])
4'h0,
4'h1,
4'h2:
foobar = {foobar, " 878"};
endcase
end
end
endtask
task ozonerx;
input [ 31:0] foo;
inout [STRLEN*8: 1] foobar;
// verilator no_inline_task
begin
case (foo[19:18])
2'h0 : foobar = {foobar, " 879"};
2'h1 : foobar = {foobar, " 880"};
2'h2 : foobar = {foobar, " 881"};
2'h3 : foobar = {foobar, " 882"};
endcase
case (foo[17:16])
2'h1 : foobar = {foobar, " 883"};
2'h2 : foobar = {foobar, " 884"};
2'h3 : foobar = {foobar, " 885"};
endcase
end
endtask
task ozonerme;
input [ 2:0] rme;
inout [STRLEN*8: 1] foobar;
// verilator no_inline_task
begin
case (rme)
3'h0 : foobar = {foobar, " 886"};
3'h1 : foobar = {foobar, " 887"};
3'h2 : foobar = {foobar, " 888"};
3'h3 : foobar = {foobar, " 889"};
3'h4 : foobar = {foobar, " 890"};
3'h5 : foobar = {foobar, " 891"};
3'h6 : foobar = {foobar, " 892"};
3'h7 : foobar = {foobar, " 893"};
endcase
end
endtask
task ozoneye;
input [5:0] ye;
input l;
inout [STRLEN*8: 1] foobar;
// verilator no_inline_task
begin
foobar = {foobar, " 894"};
ozonerme(ye[5:3],foobar);
case ({ye[ 2:0], l})
4'h2,
4'ha: foobar = {foobar, " 895"};
4'h4,
4'hb: foobar = {foobar, " 896"};
4'h6,
4'he: foobar = {foobar, " 897"};
4'h8,
4'hc: foobar = {foobar, " 898"};
endcase
end
endtask
task ozonef1e_ye;
input [5:0] ye;
input l;
inout [STRLEN*8: 1] foobar;
// verilator no_inline_task
begin
foobar = {foobar, " 899"};
ozonerme(ye[5:3],foobar);
ozonef1e_inc_dec(ye[5:0], l ,foobar);
end
endtask
task ozonef1e_h;
input [ 2:0] e;
inout [STRLEN*8: 1] foobar;
// verilator no_inline_task
begin
if (e[ 2:0] <= 3'h4)
foobar = {foobar, " 900"};
end
endtask
task ozonef1e_inc_dec;
input [5:0] ye;
input l;
inout [STRLEN*8: 1] foobar;
// verilator no_inline_task
begin
case ({ye[ 2:0], l})
4'h2,
4'h3,
4'ha: foobar = {foobar, " 901"};
4'h4,
4'h5,
4'hb: foobar = {foobar, " 902"};
4'h6,
4'h7,
4'he: foobar = {foobar, " 903"};
4'h8,
4'h9,
4'hc: foobar = {foobar, " 904"};
4'hf: foobar = {foobar, " 905"};
endcase
end
endtask
task ozonef1e_hl;
input [ 2:0] e;
input l;
inout [STRLEN*8: 1] foobar;
// verilator no_inline_task
begin
case ({e[ 2:0], l})
4'h0,
4'h2,
4'h4,
4'h6,
4'h8: foobar = {foobar, " 906"};
4'h1,
4'h3,
4'h5,
4'h7,
4'h9: foobar = {foobar, " 907"};
endcase
end
endtask
task ozonexe;
input [ 3:0] xe;
inout [STRLEN*8: 1] foobar;
// verilator no_inline_task
begin
case (xe[3])
1'b0 : foobar = {foobar, " 908"};
1'b1 : foobar = {foobar, " 909"};
endcase
case (xe[ 2:0])
3'h1,
3'h5: foobar = {foobar, " 910"};
3'h2,
3'h6: foobar = {foobar, " 911"};
3'h3,
3'h7: foobar = {foobar, " 912"};
3'h4: foobar = {foobar, " 913"};
endcase
end
endtask
task ozonerp;
input [ 2:0] rp;
inout [STRLEN*8: 1] foobar;
// verilator no_inline_task
begin
case (rp)
3'h0 : foobar = {foobar, " 914"};
3'h1 : foobar = {foobar, " 915"};
3'h2 : foobar = {foobar, " 916"};
3'h3 : foobar = {foobar, " 917"};
3'h4 : foobar = {foobar, " 918"};
3'h5 : foobar = {foobar, " 919"};
3'h6 : foobar = {foobar, " 920"};
3'h7 : foobar = {foobar, " 921"};
endcase
end
endtask
task ozonery;
input [ 3:0] ry;
inout [STRLEN*8: 1] foobar;
// verilator no_inline_task
begin
case (ry)
4'h0 : foobar = {foobar, " 922"};
4'h1 : foobar = {foobar, " 923"};
4'h2 : foobar = {foobar, " 924"};
4'h3 : foobar = {foobar, " 925"};
4'h4 : foobar = {foobar, " 926"};
4'h5 : foobar = {foobar, " 927"};
4'h6 : foobar = {foobar, " 928"};
4'h7 : foobar = {foobar, " 929"};
4'h8 : foobar = {foobar, " 930"};
4'h9 : foobar = {foobar, " 931"};
4'ha : foobar = {foobar, " 932"};
4'hb : foobar = {foobar, " 933"};
4'hc : foobar = {foobar, " 934"};
4'hd : foobar = {foobar, " 935"};
4'he : foobar = {foobar, " 936"};
4'hf : foobar = {foobar, " 937"};
endcase
end
endtask
task ozonearx;
input [ 15:0] foo;
inout [STRLEN*8: 1] foobar;
// verilator no_inline_task
begin
case (foo[1:0])
2'h0 : foobar = {foobar, " 938"};
2'h1 : foobar = {foobar, " 939"};
2'h2 : foobar = {foobar, " 940"};
2'h3 : foobar = {foobar, " 941"};
endcase
end
endtask
task ozonef3f4imop;
input [ 4:0] f3f4iml;
inout [STRLEN*8: 1] foobar;
// verilator no_inline_task
begin
casez (f3f4iml)
5'b000??: foobar = {foobar, " 942"};
5'b001??: foobar = {foobar, " 943"};
5'b?10??: foobar = {foobar, " 944"};
5'b0110?: foobar = {foobar, " 945"};
5'b01110: foobar = {foobar, " 946"};
5'b01111: foobar = {foobar, " 947"};
5'b10???: foobar = {foobar, " 948"};
5'b11100: foobar = {foobar, " 949"};
5'b11101: foobar = {foobar, " 950"};
5'b11110: foobar = {foobar, " 951"};
5'b11111: foobar = {foobar, " 952"};
endcase
end
endtask
task ozonecon;
input [ 4:0] con;
inout [STRLEN*8: 1] foobar;
// verilator no_inline_task
begin
case (con)
5'h00 : foobar = {foobar, " 953"};
5'h01 : foobar = {foobar, " 954"};
5'h02 : foobar = {foobar, " 955"};
5'h03 : foobar = {foobar, " 956"};
5'h04 : foobar = {foobar, " 957"};
5'h05 : foobar = {foobar, " 958"};
5'h06 : foobar = {foobar, " 959"};
5'h07 : foobar = {foobar, " 960"};
5'h08 : foobar = {foobar, " 961"};
5'h09 : foobar = {foobar, " 962"};
5'h0a : foobar = {foobar, " 963"};
5'h0b : foobar = {foobar, " 964"};
5'h0c : foobar = {foobar, " 965"};
5'h0d : foobar = {foobar, " 966"};
5'h0e : foobar = {foobar, " 967"};
5'h0f : foobar = {foobar, " 968"};
5'h10 : foobar = {foobar, " 969"};
5'h11 : foobar = {foobar, " 970"};
5'h12 : foobar = {foobar, " 971"};
5'h13 : foobar = {foobar, " 972"};
5'h14 : foobar = {foobar, " 973"};
5'h15 : foobar = {foobar, " 974"};
5'h16 : foobar = {foobar, " 975"};
5'h17 : foobar = {foobar, " 976"};
5'h18 : foobar = {foobar, " 977"};
5'h19 : foobar = {foobar, " 978"};
5'h1a : foobar = {foobar, " 979"};
5'h1b : foobar = {foobar, " 980"};
5'h1c : foobar = {foobar, " 981"};
5'h1d : foobar = {foobar, " 982"};
5'h1e : foobar = {foobar, " 983"};
5'h1f : foobar = {foobar, " 984"};
endcase
end
endtask
task ozonedr;
input [ 15:0] foo;
inout [STRLEN*8: 1] foobar;
// verilator no_inline_task
begin
case (foo[ 9: 6])
4'h0 : foobar = {foobar, " 985"};
4'h1 : foobar = {foobar, " 986"};
4'h2 : foobar = {foobar, " 987"};
4'h3 : foobar = {foobar, " 988"};
4'h4 : foobar = {foobar, " 989"};
4'h5 : foobar = {foobar, " 990"};
4'h6 : foobar = {foobar, " 991"};
4'h7 : foobar = {foobar, " 992"};
4'h8 : foobar = {foobar, " 993"};
4'h9 : foobar = {foobar, " 994"};
4'ha : foobar = {foobar, " 995"};
4'hb : foobar = {foobar, " 996"};
4'hc : foobar = {foobar, " 997"};
4'hd : foobar = {foobar, " 998"};
4'he : foobar = {foobar, " 999"};
4'hf : foobar = {foobar, " 1000"};
endcase
end
endtask
task ozoneshift;
input [ 15:0] foo;
inout [STRLEN*8: 1] foobar;
// verilator no_inline_task
begin
case (foo[ 4: 3])
2'h0 : foobar = {foobar, " 1001"};
2'h1 : foobar = {foobar, " 1002"};
2'h2 : foobar = {foobar, " 1003"};
2'h3 : foobar = {foobar, " 1004"};
endcase
end
endtask
task ozoneacc;
input foo;
inout [STRLEN*8: 1] foobar;
// verilator no_inline_task
begin
case (foo)
2'h0 : foobar = {foobar, " 1005"};
2'h1 : foobar = {foobar, " 1006"};
endcase
end
endtask
task ozonehl;
input foo;
inout [STRLEN*8: 1] foobar;
// verilator no_inline_task
begin
case (foo)
2'h0 : foobar = {foobar, " 1007"};
2'h1 : foobar = {foobar, " 1008"};
endcase
end
endtask
task dude;
inout [STRLEN*8: 1] foobar;
reg [ 7:0] temp;
integer i;
reg nacho;
// verilator no_inline_task
begin : justify_block
nacho = 1'b0;
for (i=STRLEN-1; i>1; i=i-1)
begin
temp = foobar>>((STRLEN-1)*8);
if (temp || nacho)
nacho = 1'b1;
else
begin
foobar = foobar<<8;
foobar[8:1] = 32;
end
end
end
endtask
task big_case;
input [ 31:0] fd;
input [ 31:0] foo;
reg [STRLEN*8: 1] foobar;
// verilator no_inline_task
begin
foobar = " 1009";
if (&foo === 1'bx)
$fwrite(fd, " 1010");
else
casez ( {foo[31:26], foo[19:15], foo[5:0]} )
17'b00_111?_?_????_??_???? :
begin
ozonef1(foo, foobar);
foobar = {foobar, " 1011"};
ozoneacc(~foo[26], foobar);
ozonehl(foo[20], foobar);
foobar = {foobar, " 1012"};
ozonerx(foo, foobar);
dude(foobar);
$fwrite (fd, " 1013:%s", foobar);
end
17'b01_001?_?_????_??_???? :
begin
ozonef1(foo, foobar);
foobar = {foobar, " 1014"};
ozonerx(foo, foobar);
foobar = {foobar, " 1015"};
foobar = {foobar, " 1016"};
ozonehl(foo[20], foobar);
dude(foobar);
$fwrite (fd, " 1017:%s", foobar);
end
17'b10_100?_?_????_??_???? :
begin
ozonef1(foo, foobar);
foobar = {foobar, " 1018"};
ozonerx(foo, foobar);
foobar = {foobar, " 1019"};
foobar = {foobar, " 1020"};
ozonehl(foo[20], foobar);
dude(foobar);
$fwrite (fd, " 1021:%s", foobar);
end
17'b10_101?_?_????_??_???? :
begin
ozonef1(foo, foobar);
foobar = {foobar, " 1022"};
if (foo[20])
begin
foobar = {foobar, " 1023"};
ozoneacc(foo[18], foobar);
foobar = {foobar, " 1024"};
foobar = {foobar, " 1025"};
if (foo[19])
foobar = {foobar, " 1026"};
else
foobar = {foobar, " 1027"};
end
else
ozonerx(foo, foobar);
dude(foobar);
$fwrite (fd, " 1028:%s", foobar);
end
17'b10_110?_?_????_??_???? :
begin
ozonef1(foo, foobar);
foobar = {foobar, " 1029"};
foobar = {foobar, " 1030"};
ozonehl(foo[20], foobar);
foobar = {foobar, " 1031"};
ozonerx(foo, foobar);
dude(foobar);
$fwrite (fd, " 1032:%s", foobar);
end
17'b10_111?_?_????_??_???? :
begin
ozonef1(foo, foobar);
foobar = {foobar, " 1033"};
foobar = {foobar, " 1034"};
ozonehl(foo[20], foobar);
foobar = {foobar, " 1035"};
ozonerx(foo, foobar);
dude(foobar);
$fwrite (fd, " 1036:%s", foobar);
end
17'b11_001?_?_????_??_???? :
begin
ozonef1(foo, foobar);
foobar = {foobar, " 1037"};
ozonerx(foo, foobar);
foobar = {foobar, " 1038"};
foobar = {foobar, " 1039"};
ozonehl(foo[20], foobar);
dude(foobar);
$fwrite (fd, " 1040:%s", foobar);
end
17'b11_111?_?_????_??_???? :
begin
ozonef1(foo, foobar);
foobar = {foobar, " 1041"};
foobar = {foobar, " 1042"};
ozonerx(foo, foobar);
foobar = {foobar, " 1043"};
if (foo[20])
foobar = {foobar, " 1044"};
else
foobar = {foobar, " 1045"};
dude(foobar);
$fwrite (fd, " 1046:%s", foobar);
end
17'b00_10??_?_????_?1_1111 :
casez (foo[11: 5])
7'b??_0_010_0:
begin
foobar = " 1047";
ozonecon(foo[14:10], foobar);
foobar = {foobar, " 1048"};
ozonef1e(foo, foobar);
dude(foobar);
$fwrite (fd, " 1049:%s", foobar);
end
7'b00_?_110_?:
begin
ozonef1e(foo, foobar);
foobar = {foobar, " 1050"};
case ({foo[ 9],foo[ 5]})
2'b00:
begin
foobar = {foobar, " 1051"};
ozoneae(foo[14:12], foobar);
ozonehl(foo[ 5], foobar);
end
2'b01:
begin
foobar = {foobar, " 1052"};
ozoneae(foo[14:12], foobar);
ozonehl(foo[ 5], foobar);
end
2'b10:
begin
foobar = {foobar, " 1053"};
ozoneae(foo[14:12], foobar);
end
2'b11: foobar = {foobar, " 1054"};
endcase
dude(foobar);
$fwrite (fd, " 1055:%s", foobar);
end
7'b01_?_110_?:
begin
ozonef1e(foo, foobar);
foobar = {foobar, " 1056"};
case ({foo[ 9],foo[ 5]})
2'b00:
begin
ozoneae(foo[14:12], foobar);
ozonehl(foo[ 5], foobar);
foobar = {foobar, " 1057"};
end
2'b01:
begin
ozoneae(foo[14:12], foobar);
ozonehl(foo[ 5], foobar);
foobar = {foobar, " 1058"};
end
2'b10:
begin
ozoneae(foo[14:12], foobar);
foobar = {foobar, " 1059"};
end
2'b11: foobar = {foobar, " 1060"};
endcase
dude(foobar);
$fwrite (fd, " 1061:%s", foobar);
end
7'b10_0_110_0:
begin
ozonef1e(foo, foobar);
foobar = {foobar, " 1062"};
foobar = {foobar, " 1063"};
if (foo[12])
foobar = {foobar, " 1064"};
else
ozonerab({4'b1001, foo[14:12]}, foobar);
dude(foobar);
$fwrite (fd, " 1065:%s", foobar);
end
7'b10_0_110_1:
begin
ozonef1e(foo, foobar);
foobar = {foobar, " 1066"};
if (foo[12])
foobar = {foobar, " 1067"};
else
ozonerab({4'b1001, foo[14:12]}, foobar);
foobar = {foobar, " 1068"};
dude(foobar);
$fwrite (fd, " 1069:%s", foobar);
end
7'b??_?_000_?:
begin
ozonef1e(foo, foobar);
foobar = {foobar, " 1070"};
foobar = {foobar, " 1071"};
ozonef1e_hl(foo[11:9],foo[ 5],foobar);
foobar = {foobar, " 1072"};
ozonef1e_ye(foo[14:9],foo[ 5],foobar);
dude(foobar);
$fwrite (fd, " 1073:%s", foobar);
end
7'b??_?_100_?:
begin
ozonef1e(foo, foobar);
foobar = {foobar, " 1074"};
foobar = {foobar, " 1075"};
ozonef1e_hl(foo[11:9],foo[ 5],foobar);
foobar = {foobar, " 1076"};
ozonef1e_ye(foo[14:9],foo[ 5],foobar);
dude(foobar);
$fwrite (fd, " 1077:%s", foobar);
end
7'b??_?_001_?:
begin
ozonef1e(foo, foobar);
foobar = {foobar, " 1078"};
ozonef1e_ye(foo[14:9],foo[ 5],foobar);
foobar = {foobar, " 1079"};
foobar = {foobar, " 1080"};
ozonef1e_hl(foo[11:9],foo[ 5],foobar);
dude(foobar);
$fwrite (fd, " 1081:%s", foobar);
end
7'b??_?_011_?:
begin
ozonef1e(foo, foobar);
foobar = {foobar, " 1082"};
ozonef1e_ye(foo[14:9],foo[ 5],foobar);
foobar = {foobar, " 1083"};
foobar = {foobar, " 1084"};
ozonef1e_hl(foo[11:9],foo[ 5],foobar);
dude(foobar);
$fwrite (fd, " 1085:%s", foobar);
end
7'b??_?_101_?:
begin
ozonef1e(foo, foobar);
foobar = {foobar, " 1086"};
ozonef1e_ye(foo[14:9],foo[ 5],foobar);
dude(foobar);
$fwrite (fd, " 1087:%s", foobar);
end
endcase
17'b00_10??_?_????_?0_0110 :
begin
ozonef1e(foo, foobar);
foobar = {foobar, " 1088"};
ozoneae(foo[ 8: 6], foobar);
ozonef1e_hl(foo[11:9],foo[ 5],foobar);
foobar = {foobar, " 1089"};
ozonef1e_ye(foo[14:9],foo[ 5],foobar);
dude(foobar);
$fwrite (fd, " 1090:%s", foobar);
end
17'b00_10??_?_????_00_0111 :
begin
ozonef1e(foo, foobar);
foobar = {foobar, " 1091"};
if (foo[ 6])
foobar = {foobar, " 1092"};
else
ozonerab({4'b1001, foo[ 8: 6]}, foobar);
foobar = {foobar, " 1093"};
foobar = {foobar, " 1094"};
ozonerme(foo[14:12],foobar);
case (foo[11: 9])
3'h2,
3'h5,
3'h6,
3'h7:
ozonef1e_inc_dec(foo[14:9],1'b0,foobar);
3'h1,
3'h3,
3'h4:
foobar = {foobar, " 1095"};
endcase
dude(foobar);
$fwrite (fd, " 1096:%s", foobar);
end
17'b00_10??_?_????_?0_0100 :
begin
ozonef1e(foo, foobar);
foobar = {foobar, " 1097"};
ozonef1e_ye(foo[14:9],foo[ 5],foobar);
foobar = {foobar, " 1098"};
ozoneae(foo[ 8: 6], foobar);
ozonef1e_hl(foo[11:9],foo[ 5],foobar);
dude(foobar);
$fwrite (fd, " 1099:%s", foobar);
end
17'b00_10??_?_????_10_0111 :
begin
ozonef1e(foo, foobar);
foobar = {foobar, " 1100"};
foobar = {foobar, " 1101"};
ozonerme(foo[14:12],foobar);
case (foo[11: 9])
3'h2,
3'h5,
3'h6,
3'h7:
ozonef1e_inc_dec(foo[14:9],1'b0,foobar);
3'h1,
3'h3,
3'h4:
foobar = {foobar, " 1102"};
endcase
foobar = {foobar, " 1103"};
if (foo[ 6])
foobar = {foobar, " 1104"};
else
ozonerab({4'b1001, foo[ 8: 6]}, foobar);
dude(foobar);
$fwrite (fd, " 1105:%s", foobar);
end
17'b00_10??_?_????_?0_1110 :
begin
ozonef1e(foo, foobar);
foobar = {foobar, " 1106"};
case (foo[11:9])
3'h2:
begin
foobar = {foobar, " 1107"};
if (foo[14:12] == 3'h0)
foobar = {foobar, " 1108"};
else
ozonerme(foo[14:12],foobar);
foobar = {foobar, " 1109"};
end
3'h6:
begin
foobar = {foobar, " 1110"};
if (foo[14:12] == 3'h0)
foobar = {foobar, " 1111"};
else
ozonerme(foo[14:12],foobar);
foobar = {foobar, " 1112"};
end
3'h0:
begin
foobar = {foobar, " 1113"};
if (foo[14:12] == 3'h0)
foobar = {foobar, " 1114"};
else
ozonerme(foo[14:12],foobar);
foobar = {foobar, " 1115"};
if (foo[ 7: 5] >= 3'h5)
foobar = {foobar, " 1116"};
else
ozonexe(foo[ 8: 5], foobar);
end
3'h1:
begin
foobar = {foobar, " 1117"};
if (foo[14:12] == 3'h0)
foobar = {foobar, " 1118"};
else
ozonerme(foo[14:12],foobar);
foobar = {foobar, " 1119"};
if (foo[ 7: 5] >= 3'h5)
foobar = {foobar, " 1120"};
else
ozonexe(foo[ 8: 5], foobar);
end
3'h4:
begin
foobar = {foobar, " 1121"};
if (foo[14:12] == 3'h0)
foobar = {foobar, " 1122"};
else
ozonerme(foo[14:12],foobar);
foobar = {foobar, " 1123"};
if (foo[ 7: 5] >= 3'h5)
foobar = {foobar, " 1124"};
else
ozonexe(foo[ 8: 5], foobar);
end
3'h5:
begin
foobar = {foobar, " 1125"};
if (foo[14:12] == 3'h0)
foobar = {foobar, " 1126"};
else
ozonerme(foo[14:12],foobar);
foobar = {foobar, " 1127"};
if (foo[ 7: 5] >= 3'h5)
foobar = {foobar, " 1128"};
else
ozonexe(foo[ 8: 5], foobar);
end
endcase
dude(foobar);
$fwrite (fd, " 1129:%s", foobar);
end
17'b00_10??_?_????_?0_1111 :
casez (foo[14: 9])
6'b001_10_?:
begin
ozonef1e(foo, foobar);
foobar = {foobar, " 1130"};
foobar = {foobar, " 1131"};
ozonef1e_hl(foo[ 7: 5],foo[ 9],foobar);
foobar = {foobar, " 1132"};
ozonexe(foo[ 8: 5], foobar);
dude(foobar);
$fwrite (fd, " 1133:%s", foobar);
end
6'b???_11_?:
begin
ozonef1e(foo, foobar);
foobar = {foobar, " 1134"};
ozoneae(foo[14:12], foobar);
ozonef1e_hl(foo[ 7: 5],foo[ 9],foobar);
foobar = {foobar, " 1135"};
ozonexe(foo[ 8: 5], foobar);
dude(foobar);
$fwrite (fd, " 1136:%s", foobar);
end
6'b000_10_1,
6'b010_10_1,
6'b100_10_1,
6'b110_10_1:
begin
ozonef1e(foo, foobar);
foobar = {foobar, " 1137"};
ozonerab({4'b1001, foo[14:12]}, foobar);
foobar = {foobar, " 1138"};
if ((foo[ 7: 5] >= 3'h1) & (foo[ 7: 5] <= 3'h3))
foobar = {foobar, " 1139"};
else
ozonexe(foo[ 8: 5], foobar);
dude(foobar);
$fwrite (fd, " 1140:%s", foobar);
end
6'b000_10_0,
6'b010_10_0,
6'b100_10_0,
6'b110_10_0:
begin
ozonef1e(foo, foobar);
foobar = {foobar, " 1141"};
foobar = {foobar, " 1142"};
ozonerab({4'b1001, foo[14:12]}, foobar);
foobar = {foobar, " 1143"};
foobar = {foobar, " 1144"};
ozonef1e_h(foo[ 7: 5],foobar);
foobar = {foobar, " 1145"};
ozonexe(foo[ 8: 5], foobar);
dude(foobar);
$fwrite (fd, " 1146:%s", foobar);
end
6'b???_00_?:
begin
ozonef1e(foo, foobar);
foobar = {foobar, " 1147"};
if (foo[ 9])
begin
foobar = {foobar, " 1148"};
ozoneae(foo[14:12], foobar);
end
else
begin
foobar = {foobar, " 1149"};
ozoneae(foo[14:12], foobar);
foobar = {foobar, " 1150"};
end
foobar = {foobar, " 1151"};
foobar = {foobar, " 1152"};
ozonef1e_h(foo[ 7: 5],foobar);
foobar = {foobar, " 1153"};
ozonexe(foo[ 8: 5], foobar);
dude(foobar);
$fwrite (fd, " 1154:%s", foobar);
end
6'b???_01_?:
begin
ozonef1e(foo, foobar);
foobar = {foobar, " 1155"};
ozoneae(foo[14:12], foobar);
if (foo[ 9])
foobar = {foobar, " 1156"};
else
foobar = {foobar, " 1157"};
foobar = {foobar, " 1158"};
foobar = {foobar, " 1159"};
ozonef1e_h(foo[ 7: 5],foobar);
foobar = {foobar, " 1160"};
ozonexe(foo[ 8: 5], foobar);
dude(foobar);
$fwrite (fd, " 1161:%s", foobar);
end
6'b011_10_0:
begin
ozonef1e(foo, foobar);
foobar = {foobar, " 1162"};
case (foo[ 8: 5])
4'h0: foobar = {foobar, " 1163"};
4'h1: foobar = {foobar, " 1164"};
4'h2: foobar = {foobar, " 1165"};
4'h3: foobar = {foobar, " 1166"};
4'h4: foobar = {foobar, " 1167"};
4'h5: foobar = {foobar, " 1168"};
4'h8: foobar = {foobar, " 1169"};
4'h9: foobar = {foobar, " 1170"};
4'ha: foobar = {foobar, " 1171"};
4'hb: foobar = {foobar, " 1172"};
4'hc: foobar = {foobar, " 1173"};
4'hd: foobar = {foobar, " 1174"};
default: foobar = {foobar, " 1175"};
endcase
dude(foobar);
$fwrite (fd, " 1176:%s", foobar);
end
default: foobar = {foobar, " 1177"};
endcase
17'b00_10??_?_????_?0_110? :
begin
ozonef1e(foo, foobar);
foobar = {foobar, " 1178"};
foobar = {foobar, " 1179"};
ozonef1e_hl(foo[11:9], foo[0], foobar);
foobar = {foobar, " 1180"};
ozonef1e_ye(foo[14:9],1'b0,foobar);
foobar = {foobar, " 1181"};
ozonef1e_h(foo[ 7: 5],foobar);
foobar = {foobar, " 1182"};
ozonexe(foo[ 8: 5], foobar);
dude(foobar);
$fwrite (fd, " 1183:%s", foobar);
end
17'b00_10??_?_????_?1_110? :
begin
ozonef1e(foo, foobar);
foobar = {foobar, " 1184"};
foobar = {foobar, " 1185"};
ozonef1e_hl(foo[11:9],foo[0],foobar);
foobar = {foobar, " 1186"};
ozonef1e_ye(foo[14:9],foo[ 0],foobar);
foobar = {foobar, " 1187"};
foobar = {foobar, " 1188"};
ozonef1e_h(foo[ 7: 5],foobar);
foobar = {foobar, " 1189"};
ozonexe(foo[ 8: 5], foobar);
dude(foobar);
$fwrite (fd, " 1190:%s", foobar);
end
17'b00_10??_?_????_?0_101? :
begin
ozonef1e(foo, foobar);
foobar = {foobar, " 1191"};
ozonef1e_ye(foo[14:9],foo[ 0],foobar);
foobar = {foobar, " 1192"};
foobar = {foobar, " 1193"};
ozonef1e_hl(foo[11:9],foo[0],foobar);
foobar = {foobar, " 1194"};
foobar = {foobar, " 1195"};
ozonef1e_h(foo[ 7: 5],foobar);
foobar = {foobar, " 1196"};
ozonexe(foo[ 8: 5], foobar);
dude(foobar);
$fwrite (fd, " 1197:%s", foobar);
end
17'b00_10??_?_????_?0_1001 :
begin
ozonef1e(foo, foobar);
foobar = {foobar, " 1198"};
foobar = {foobar, " 1199"};
ozonef1e_h(foo[11:9],foobar);
foobar = {foobar, " 1200"};
ozonef1e_ye(foo[14:9],1'b0,foobar);
foobar = {foobar, " 1201"};
case (foo[ 7: 5])
3'h1,
3'h2,
3'h3:
foobar = {foobar, " 1202"};
default:
begin
foobar = {foobar, " 1203"};
foobar = {foobar, " 1204"};
ozonexe(foo[ 8: 5], foobar);
end
endcase
dude(foobar);
$fwrite (fd, " 1205:%s", foobar);
end
17'b00_10??_?_????_?0_0101 :
begin
ozonef1e(foo, foobar);
foobar = {foobar, " 1206"};
case (foo[11: 9])
3'h1,
3'h3,
3'h4:
foobar = {foobar, " 1207"};
default:
begin
ozonef1e_ye(foo[14:9],1'b0,foobar);
foobar = {foobar, " 1208"};
foobar = {foobar, " 1209"};
end
endcase
foobar = {foobar, " 1210"};
foobar = {foobar, " 1211"};
ozonef1e_h(foo[ 7: 5],foobar);
foobar = {foobar, " 1212"};
ozonexe(foo[ 8: 5], foobar);
dude(foobar);
$fwrite (fd, " 1213:%s", foobar);
end
17'b00_10??_?_????_?1_1110 :
begin
ozonef1e(foo, foobar);
foobar = {foobar, " 1214"};
ozonef1e_ye(foo[14:9],1'b0,foobar);
foobar = {foobar, " 1215"};
foobar = {foobar, " 1216"};
ozonef1e_h(foo[11: 9],foobar);
foobar = {foobar, " 1217"};
foobar = {foobar, " 1218"};
ozonef1e_h(foo[ 7: 5],foobar);
foobar = {foobar, " 1219"};
ozonexe(foo[ 8: 5], foobar);
dude(foobar);
$fwrite (fd, " 1220:%s", foobar);
end
17'b00_10??_?_????_?0_1000 :
begin
ozonef1e(foo, foobar);
foobar = {foobar, " 1221"};
ozonef1e_ye(foo[14:9],1'b0,foobar);
foobar = {foobar, " 1222"};
foobar = {foobar, " 1223"};
ozonef1e_h(foo[11: 9],foobar);
foobar = {foobar, " 1224"};
foobar = {foobar, " 1225"};
ozonef1e_h(foo[ 7: 5],foobar);
foobar = {foobar, " 1226"};
ozonexe(foo[ 8: 5], foobar);
dude(foobar);
$fwrite (fd, " 1227:%s", foobar);
end
17'b10_01??_?_????_??_???? :
begin
if (foo[27])
foobar = " 1228";
else
foobar = " 1229";
ozonecon(foo[20:16], foobar);
foobar = {foobar, " 1230"};
ozonef2(foo[31:0], foobar);
dude(foobar);
$fwrite (fd, " 1231:%s", foobar);
end
17'b00_1000_?_????_01_0011 :
if (~|foo[ 9: 8])
begin
if (foo[ 7])
foobar = " 1232";
else
foobar = " 1233";
ozonecon(foo[14:10], foobar);
foobar = {foobar, " 1234"};
ozonef2e(foo[31:0], foobar);
dude(foobar);
$fwrite (fd, " 1235:%s", foobar);
end
else
begin
foobar = " 1236";
ozonecon(foo[14:10], foobar);
foobar = {foobar, " 1237"};
ozonef3e(foo[31:0], foobar);
dude(foobar);
$fwrite (fd, " 1238:%s", foobar);
end
17'b11_110?_1_????_??_???? :
begin
ozonef3(foo[31:0], foobar);
dude(foobar);
$fwrite(fd, " 1239:%s", foobar);
end
17'b11_110?_0_????_??_???? :
begin : f4_body
casez (foo[24:20])
5'b0_1110,
5'b1_0???,
5'b1_1111:
begin
$fwrite (fd, " 1240");
end
5'b0_00??:
begin
ozoneacc(foo[26], foobar);
foobar = {foobar, " 1241"};
ozoneacc(foo[25], foobar);
ozonebmuop(foo[24:20], foobar);
ozoneae(foo[18:16], foobar);
foobar = {foobar, " 1242"};
dude(foobar);
$fwrite(fd, " 1243:%s", foobar);
end
5'b0_01??:
begin
ozoneacc(foo[26], foobar);
foobar = {foobar, " 1244"};
ozoneacc(foo[25], foobar);
ozonebmuop(foo[24:20], foobar);
ozonearm(foo[18:16], foobar);
dude(foobar);
$fwrite(fd, " 1245:%s", foobar);
end
5'b0_1011:
begin
ozoneacc(foo[26], foobar);
foobar = {foobar, " 1246"};
ozonebmuop(foo[24:20], foobar);
foobar = {foobar, " 1247"};
ozoneae(foo[18:16], foobar);
foobar = {foobar, " 1248"};
dude(foobar);
$fwrite(fd, " 1249:%s", foobar);
end
5'b0_100?,
5'b0_1010,
5'b0_110? :
begin
ozoneacc(foo[26], foobar);
foobar = {foobar, " 1250"};
ozonebmuop(foo[24:20], foobar);
foobar = {foobar, " 1251"};
ozoneacc(foo[25], foobar);
foobar = {foobar, " 1252"};
ozoneae(foo[18:16], foobar);
foobar = {foobar, " 1253"};
dude(foobar);
$fwrite(fd, " 1254:%s", foobar);
end
5'b0_1111 :
begin
ozoneacc(foo[26], foobar);
foobar = {foobar, " 1255"};
ozoneacc(foo[25], foobar);
foobar = {foobar, " 1256"};
ozoneae(foo[18:16], foobar);
dude(foobar);
$fwrite(fd, " 1257:%s", foobar);
end
5'b1_10??,
5'b1_110?,
5'b1_1110 :
begin
ozoneacc(foo[26], foobar);
foobar = {foobar, " 1258"};
ozonebmuop(foo[24:20], foobar);
foobar = {foobar, " 1259"};
ozoneacc(foo[25], foobar);
foobar = {foobar, " 1260"};
ozonearm(foo[18:16], foobar);
foobar = {foobar, " 1261"};
dude(foobar);
$fwrite(fd, " 1262:%s", foobar);
end
endcase
end
17'b11_100?_?_????_??_???? :
casez (foo[23:19])
5'b111??,
5'b0111?:
begin
ozoneae(foo[26:24], foobar);
foobar = {foobar, " 1263"};
ozonef3f4imop(foo[23:19], foobar);
foobar = {foobar, " 1264"};
ozoneae(foo[18:16], foobar);
foobar = {foobar, " 1265"};
skyway(foo[15:12], foobar);
skyway(foo[11: 8], foobar);
skyway(foo[ 7: 4], foobar);
skyway(foo[ 3:0], foobar);
foobar = {foobar, " 1266"};
dude(foobar);
$fwrite(fd, " 1267:%s", foobar);
end
5'b?0???,
5'b110??:
begin
ozoneae(foo[26:24], foobar);
foobar = {foobar, " 1268"};
if (foo[23:21] == 3'b100)
foobar = {foobar, " 1269"};
ozoneae(foo[18:16], foobar);
if (foo[19])
foobar = {foobar, " 1270"};
else
foobar = {foobar, " 1271"};
ozonef3f4imop(foo[23:19], foobar);
foobar = {foobar, " 1272"};
ozonef3f4_iext(foo[20:19], foo[15:0], foobar);
dude(foobar);
$fwrite(fd, " 1273:%s", foobar);
end
5'b010??,
5'b0110?:
begin
ozoneae(foo[18:16], foobar);
if (foo[19])
foobar = {foobar, " 1274"};
else
foobar = {foobar, " 1275"};
ozonef3f4imop(foo[23:19], foobar);
foobar = {foobar, " 1276"};
ozonef3f4_iext(foo[20:19], foo[15:0], foobar);
dude(foobar);
$fwrite(fd, " 1277:%s", foobar);
end
endcase
17'b00_1000_?_????_11_0011 :
begin
foobar = " 1278";
ozonecon(foo[14:10], foobar);
foobar = {foobar, " 1279"};
casez (foo[25:21])
5'b0_1110,
5'b1_0???,
5'b1_1111:
begin
$fwrite(fd, " 1280");
end
5'b0_00??:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar, " 1281"};
ozoneae(foo[17:15], foobar);
ozonebmuop(foo[25:21], foobar);
ozoneae(foo[ 8: 6], foobar);
foobar = {foobar, " 1282"};
dude(foobar);
$fwrite(fd, " 1283:%s", foobar);
end
5'b0_01??:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar, " 1284"};
ozoneae(foo[17:15], foobar);
ozonebmuop(foo[25:21], foobar);
ozonearm(foo[ 8: 6], foobar);
dude(foobar);
$fwrite(fd, " 1285:%s", foobar);
end
5'b0_1011:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar, " 1286"};
ozonebmuop(foo[25:21], foobar);
foobar = {foobar, " 1287"};
ozoneae(foo[ 8: 6], foobar);
foobar = {foobar, " 1288"};
dude(foobar);
$fwrite(fd, " 1289:%s", foobar);
end
5'b0_100?,
5'b0_1010,
5'b0_110? :
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar, " 1290"};
ozonebmuop(foo[25:21], foobar);
foobar = {foobar, " 1291"};
ozoneae(foo[17:15], foobar);
foobar = {foobar, " 1292"};
ozoneae(foo[ 8: 6], foobar);
foobar = {foobar, " 1293"};
dude(foobar);
$fwrite(fd, " 1294:%s", foobar);
end
5'b0_1111 :
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar, " 1295"};
ozoneae(foo[17:15], foobar);
foobar = {foobar, " 1296"};
ozoneae(foo[ 8: 6], foobar);
dude(foobar);
$fwrite(fd, " 1297:%s", foobar);
end
5'b1_10??,
5'b1_110?,
5'b1_1110 :
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar, " 1298"};
ozonebmuop(foo[25:21], foobar);
foobar = {foobar, " 1299"};
ozoneae(foo[17:15], foobar);
foobar = {foobar, " 1300"};
ozonearm(foo[ 8: 6], foobar);
foobar = {foobar, " 1301"};
dude(foobar);
$fwrite(fd, " 1302:%s", foobar);
end
endcase
end
17'b00_0010_?_????_??_???? :
begin
$fwrite(fd, " 1304a:%x;%x", foobar, foo[25:20]);
ozonerab({1'b0, foo[25:20]}, foobar);
$fwrite(fd, " 1304b:%x", foobar);
foobar = {foobar, " 1303"};
$fwrite(fd, " 1304c:%x;%x", foobar, foo[19:16]);
skyway(foo[19:16], foobar);
$fwrite(fd, " 1304d:%x", foobar);
dude(foobar);
$fwrite(fd, " 1304e:%x", foobar);
$fwrite(fd, " 1304:%s", foobar);
end
17'b00_01??_?_????_??_???? :
begin
if (foo[27])
begin
foobar = {foobar, " 1305"};
if (foo[26])
foobar = {foobar, " 1306"};
else
foobar = {foobar, " 1307"};
skyway(foo[19:16], foobar);
foobar = {foobar, " 1308"};
ozonerab({1'b0, foo[25:20]}, foobar);
end
else
begin
ozonerab({1'b0, foo[25:20]}, foobar);
foobar = {foobar, " 1309"};
if (foo[26])
foobar = {foobar, " 1310"};
else
foobar = {foobar, " 1311"};
skyway(foo[19:16], foobar);
foobar = {foobar, " 1312"};
end
dude(foobar);
$fwrite(fd, " 1313:%s", foobar);
end
17'b01_000?_?_????_??_???? :
begin
if (foo[26])
begin
ozonerb(foo[25:20], foobar);
foobar = {foobar, " 1314"};
ozoneae(foo[18:16], foobar);
ozonehl(foo[19], foobar);
end
else
begin
ozoneae(foo[18:16], foobar);
ozonehl(foo[19], foobar);
foobar = {foobar, " 1315"};
ozonerb(foo[25:20], foobar);
end
dude(foobar);
$fwrite(fd, " 1316:%s", foobar);
end
17'b01_10??_?_????_??_???? :
begin
if (foo[27])
begin
ozonerab({1'b0, foo[25:20]}, foobar);
foobar = {foobar, " 1317"};
ozonerx(foo, foobar);
end
else
begin
ozonerx(foo, foobar);
foobar = {foobar, " 1318"};
ozonerab({1'b0, foo[25:20]}, foobar);
end
dude(foobar);
$fwrite(fd, " 1319:%s", foobar);
end
17'b11_101?_?_????_??_???? :
begin
ozonerab (foo[26:20], foobar);
foobar = {foobar, " 1320"};
skyway(foo[19:16], foobar);
skyway(foo[15:12], foobar);
skyway(foo[11: 8], foobar);
skyway(foo[ 7: 4], foobar);
skyway(foo[ 3: 0], foobar);
dude(foobar);
$fwrite(fd, " 1321:%s", foobar);
end
17'b11_0000_?_????_??_???? :
begin
casez (foo[25:23])
3'b00?:
begin
ozonerab(foo[22:16], foobar);
foobar = {foobar, " 1322"};
end
3'b01?:
begin
foobar = {foobar, " 1323"};
if (foo[22:16]>=7'h60)
foobar = {foobar, " 1324"};
else
ozonerab(foo[22:16], foobar);
end
3'b110:
foobar = {foobar, " 1325"};
3'b10?:
begin
foobar = {foobar, " 1326"};
if (foo[22:16]>=7'h60)
foobar = {foobar, " 1327"};
else
ozonerab(foo[22:16], foobar);
end
3'b111:
begin
foobar = {foobar, " 1328"};
ozonerab(foo[22:16], foobar);
foobar = {foobar, " 1329"};
end
endcase
dude(foobar);
$fwrite(fd, " 1330:%s", foobar);
end
17'b00_10??_?_????_?1_0000 :
begin
if (foo[27])
begin
foobar = {foobar, " 1331"};
ozonerp(foo[14:12], foobar);
foobar = {foobar, " 1332"};
skyway(foo[19:16], foobar);
skyway({foo[15],foo[11: 9]}, foobar);
skyway(foo[ 8: 5], foobar);
foobar = {foobar, " 1333"};
if (foo[26:20]>=7'h60)
foobar = {foobar, " 1334"};
else
ozonerab(foo[26:20], foobar);
end
else
begin
ozonerab(foo[26:20], foobar);
foobar = {foobar, " 1335"};
foobar = {foobar, " 1336"};
ozonerp(foo[14:12], foobar);
foobar = {foobar, " 1337"};
skyway(foo[19:16], foobar);
skyway({foo[15],foo[11: 9]}, foobar);
skyway(foo[ 8: 5], foobar);
foobar = {foobar, " 1338"};
end
dude(foobar);
$fwrite(fd, " 1339:%s", foobar);
end
17'b00_101?_1_0000_?1_0010 :
if (~|foo[11: 7])
begin
if (foo[ 6])
begin
foobar = {foobar, " 1340"};
ozonerp(foo[14:12], foobar);
foobar = {foobar, " 1341"};
ozonejk(foo[ 5], foobar);
foobar = {foobar, " 1342"};
if (foo[26:20]>=7'h60)
foobar = {foobar, " 1343"};
else
ozonerab(foo[26:20], foobar);
end
else
begin
ozonerab(foo[26:20], foobar);
foobar = {foobar, " 1344"};
foobar = {foobar, " 1345"};
ozonerp(foo[14:12], foobar);
foobar = {foobar, " 1346"};
ozonejk(foo[ 5], foobar);
foobar = {foobar, " 1347"};
end
dude(foobar);
$fwrite(fd, " 1348:%s", foobar);
end
else
$fwrite(fd, " 1349");
17'b00_100?_0_0011_?1_0101 :
if (~|foo[ 8: 7])
begin
if (foo[6])
begin
ozonerab(foo[26:20], foobar);
foobar = {foobar, " 1350"};
ozoneye(foo[14: 9],foo[ 5], foobar);
end
else
begin
ozoneye(foo[14: 9],foo[ 5], foobar);
foobar = {foobar, " 1351"};
if (foo[26:20]>=7'h60)
foobar = {foobar, " 1352"};
else
ozonerab(foo[26:20], foobar);
end
dude(foobar);
$fwrite(fd, " 1353:%s", foobar);
end
else
$fwrite(fd, " 1354");
17'b00_1001_0_0000_?1_0010 :
if (~|foo[25:20])
begin
ozoneye(foo[14: 9],1'b0, foobar);
foobar = {foobar, " 1355"};
ozonef1e_h(foo[11: 9],foobar);
foobar = {foobar, " 1356"};
ozonef1e_h(foo[ 7: 5],foobar);
foobar = {foobar, " 1357"};
ozonexe(foo[ 8: 5], foobar);
dude(foobar);
$fwrite(fd, " 1358:%s", foobar);
end
else
$fwrite(fd, " 1359");
17'b00_101?_0_????_?1_0010 :
if (~foo[13])
begin
if (foo[12])
begin
foobar = {foobar, " 1360"};
if (foo[26:20]>=7'h60)
foobar = {foobar, " 1361"};
else
ozonerab(foo[26:20], foobar);
foobar = {foobar, " 1362"};
foobar = {foobar, " 1363"};
skyway({1'b0,foo[18:16]}, foobar);
skyway({foo[15],foo[11: 9]}, foobar);
skyway(foo[ 8: 5], foobar);
dude(foobar);
$fwrite(fd, " 1364:%s", foobar);
end
else
begin
ozonerab(foo[26:20], foobar);
foobar = {foobar, " 1365"};
foobar = {foobar, " 1366"};
skyway({1'b0,foo[18:16]}, foobar);
skyway({foo[15],foo[11: 9]}, foobar);
skyway(foo[ 8: 5], foobar);
dude(foobar);
$fwrite(fd, " 1367:%s", foobar);
end
end
else
$fwrite(fd, " 1368");
17'b01_01??_?_????_??_???? :
begin
ozonerab({1'b0,foo[27:26],foo[19:16]}, foobar);
foobar = {foobar, " 1369"};
ozonerab({1'b0,foo[25:20]}, foobar);
dude(foobar);
$fwrite(fd, " 1370:%s", foobar);
end
17'b00_100?_?_???0_11_0101 :
if (~foo[6])
begin
foobar = " 1371";
ozonecon(foo[14:10], foobar);
foobar = {foobar, " 1372"};
ozonerab({foo[ 9: 7],foo[19:16]}, foobar);
foobar = {foobar, " 1373"};
ozonerab({foo[26:20]}, foobar);
dude(foobar);
$fwrite(fd, " 1374:%s", foobar);
end
else
$fwrite(fd, " 1375");
17'b00_1000_?_????_?1_0010 :
if (~|foo[25:24])
begin
ozonery(foo[23:20], foobar);
foobar = {foobar, " 1376"};
ozonerp(foo[14:12], foobar);
foobar = {foobar, " 1377"};
skyway(foo[19:16], foobar);
skyway({foo[15],foo[11: 9]}, foobar);
skyway(foo[ 8: 5], foobar);
dude(foobar);
$fwrite(fd, " 1378:%s", foobar);
end
else if ((foo[25:24] == 2'b10) & ~|foo[19:15] & ~|foo[11: 6])
begin
ozonery(foo[23:20], foobar);
foobar = {foobar, " 1379"};
ozonerp(foo[14:12], foobar);
foobar = {foobar, " 1380"};
ozonejk(foo[ 5], foobar);
dude(foobar);
$fwrite(fd, " 1381:%s", foobar);
end
else
$fwrite(fd, " 1382");
17'b11_01??_?_????_??_????,
17'b10_00??_?_????_??_???? :
if (foo[30])
$fwrite(fd, " 1383:%s", foo[27:16]);
else
$fwrite(fd, " 1384:%s", foo[27:16]);
17'b00_10??_?_????_01_1000 :
if (~foo[6])
begin
if (foo[7])
$fwrite(fd, " 1385:%s", foo[27: 8]);
else
$fwrite(fd, " 1386:%s", foo[27: 8]);
end
else
$fwrite(fd, " 1387");
17'b00_10??_?_????_11_1000 :
begin
foobar = " 1388";
ozonecon(foo[14:10], foobar);
foobar = {foobar, " 1389"};
if (foo[15])
foobar = {foobar, " 1390"};
else
foobar = {foobar, " 1391"};
skyway(foo[27:24], foobar);
skyway(foo[23:20], foobar);
skyway(foo[19:16], foobar);
skyway(foo[ 9: 6], foobar);
dude(foobar);
$fwrite(fd, " 1392:%s", foobar);
end
17'b11_0001_?_????_??_???? :
casez (foo[25:22])
4'b01?? :
begin
foobar = " 1393";
ozonecon(foo[20:16], foobar);
case (foo[23:21])
3'h0 : foobar = {foobar, " 1394"};
3'h1 : foobar = {foobar, " 1395"};
3'h2 : foobar = {foobar, " 1396"};
3'h3 : foobar = {foobar, " 1397"};
3'h4 : foobar = {foobar, " 1398"};
3'h5 : foobar = {foobar, " 1399"};
3'h6 : foobar = {foobar, " 1400"};
3'h7 : foobar = {foobar, " 1401"};
endcase
dude(foobar);
$fwrite(fd, " 1402:%s", foobar);
end
4'b0000 :
$fwrite(fd, " 1403:%s", foo[21:16]);
4'b0010 :
if (~|foo[21:16])
$fwrite(fd, " 1404");
4'b1010 :
if (~|foo[21:17])
begin
if (foo[16])
$fwrite(fd, " 1405");
else
$fwrite(fd, " 1406");
end
default :
$fwrite(fd, " 1407");
endcase
17'b01_11??_?_????_??_???? :
if (foo[27:23] === 5'h00)
$fwrite(fd, " 1408:%s", foo[22:16]);
else
$fwrite(fd, " 1409:%s", foo[22:16]);
default: $fwrite(fd, " 1410");
endcase
end
endtask
//(query-replace-regexp "\\([a-z0-9_]+\\) *( *\\([][a-z0-9_~': ]+\\) *, *\\([][a-z0-9'~: ]+\\) *, *\\([][a-z0-9'~: ]+\\) *);" "$c(\"\\1(\",\\2,\",\",\\3,\",\",\\4,\");\");" nil nil nil)
//(query-replace-regexp "\\([a-z0-9_]+\\) *( *\\([][a-z0-9_~': ]+\\) *, *\\([][a-z0-9'~: ]+\\) *);" "$c(\"\\1(\",\\2,\",\",\\3,\");\");" nil nil nil)
endmodule
|
/*****************************************************************************
* File : processing_system7_bfm_v2_0_axi_master.v
*
* Date : 2012-11
*
* Description : Model that acts as PS AXI Master port interface.
* It uses AXI3 Master BFM
*****************************************************************************/
`timescale 1ns/1ps
module processing_system7_bfm_v2_0_axi_master (
M_RESETN,
M_ARVALID,
M_AWVALID,
M_BREADY,
M_RREADY,
M_WLAST,
M_WVALID,
M_ARID,
M_AWID,
M_WID,
M_ARBURST,
M_ARLOCK,
M_ARSIZE,
M_AWBURST,
M_AWLOCK,
M_AWSIZE,
M_ARPROT,
M_AWPROT,
M_ARADDR,
M_AWADDR,
M_WDATA,
M_ARCACHE,
M_ARLEN,
M_AWCACHE,
M_AWLEN,
M_ARQOS, // not connected to AXI BFM
M_AWQOS, // not connected to AXI BFM
M_WSTRB,
M_ACLK,
M_ARREADY,
M_AWREADY,
M_BVALID,
M_RLAST,
M_RVALID,
M_WREADY,
M_BID,
M_RID,
M_BRESP,
M_RRESP,
M_RDATA
);
parameter enable_this_port = 0;
parameter master_name = "Master";
parameter data_bus_width = 32;
parameter address_bus_width = 32;
parameter id_bus_width = 6;
parameter max_outstanding_transactions = 8;
parameter exclusive_access_supported = 0;
parameter EXCL_ID = 12'hC00;
`include "processing_system7_bfm_v2_0_local_params.v"
/* IDs for Masters
// l2m1 (CPU000)
12'b11_000_000_00_00
12'b11_010_000_00_00
12'b11_011_000_00_00
12'b11_100_000_00_00
12'b11_101_000_00_00
12'b11_110_000_00_00
12'b11_111_000_00_00
// l2m1 (CPU001)
12'b11_000_001_00_00
12'b11_010_001_00_00
12'b11_011_001_00_00
12'b11_100_001_00_00
12'b11_101_001_00_00
12'b11_110_001_00_00
12'b11_111_001_00_00
*/
input M_RESETN;
output M_ARVALID;
output M_AWVALID;
output M_BREADY;
output M_RREADY;
output M_WLAST;
output M_WVALID;
output [id_bus_width-1:0] M_ARID;
output [id_bus_width-1:0] M_AWID;
output [id_bus_width-1:0] M_WID;
output [axi_brst_type_width-1:0] M_ARBURST;
output [axi_lock_width-1:0] M_ARLOCK;
output [axi_size_width-1:0] M_ARSIZE;
output [axi_brst_type_width-1:0] M_AWBURST;
output [axi_lock_width-1:0] M_AWLOCK;
output [axi_size_width-1:0] M_AWSIZE;
output [axi_prot_width-1:0] M_ARPROT;
output [axi_prot_width-1:0] M_AWPROT;
output [address_bus_width-1:0] M_ARADDR;
output [address_bus_width-1:0] M_AWADDR;
output [data_bus_width-1:0] M_WDATA;
output [axi_cache_width-1:0] M_ARCACHE;
output [axi_len_width-1:0] M_ARLEN;
output [axi_qos_width-1:0] M_ARQOS; // not connected to AXI BFM
output [axi_cache_width-1:0] M_AWCACHE;
output [axi_len_width-1:0] M_AWLEN;
output [axi_qos_width-1:0] M_AWQOS; // not connected to AXI BFM
output [(data_bus_width/8)-1:0] M_WSTRB;
input M_ACLK;
input M_ARREADY;
input M_AWREADY;
input M_BVALID;
input M_RLAST;
input M_RVALID;
input M_WREADY;
input [id_bus_width-1:0] M_BID;
input [id_bus_width-1:0] M_RID;
input [axi_rsp_width-1:0] M_BRESP;
input [axi_rsp_width-1:0] M_RRESP;
input [data_bus_width-1:0] M_RDATA;
wire net_RESETN;
wire net_RVALID;
wire net_BVALID;
reg DEBUG_INFO = 1'b1;
reg STOP_ON_ERROR = 1'b1;
integer use_id_no = 0;
assign M_ARQOS = 'b0;
assign M_AWQOS = 'b0;
assign net_RESETN = M_RESETN; //ENABLE_THIS_PORT ? M_RESETN : 1'b0;
assign net_RVALID = enable_this_port ? M_RVALID : 1'b0;
assign net_BVALID = enable_this_port ? M_BVALID : 1'b0;
initial begin
if(DEBUG_INFO) begin
if(enable_this_port)
$display("[%0d] : %0s : %0s : Port is ENABLED.",$time, DISP_INFO, master_name);
else
$display("[%0d] : %0s : %0s : Port is DISABLED.",$time, DISP_INFO, master_name);
end
end
initial master.set_disable_reset_value_checks(1);
initial begin
repeat(2) @(posedge M_ACLK);
if(!enable_this_port) begin
master.set_channel_level_info(0);
master.set_function_level_info(0);
end
master.RESPONSE_TIMEOUT = 0;
end
cdn_axi3_master_bfm #(master_name,
data_bus_width,
address_bus_width,
id_bus_width,
max_outstanding_transactions,
exclusive_access_supported)
master (.ACLK (M_ACLK),
.ARESETn (net_RESETN), /// confirm this
// Write Address Channel
.AWID (M_AWID),
.AWADDR (M_AWADDR),
.AWLEN (M_AWLEN),
.AWSIZE (M_AWSIZE),
.AWBURST (M_AWBURST),
.AWLOCK (M_AWLOCK),
.AWCACHE (M_AWCACHE),
.AWPROT (M_AWPROT),
.AWVALID (M_AWVALID),
.AWREADY (M_AWREADY),
// Write Data Channel Signals.
.WID (M_WID),
.WDATA (M_WDATA),
.WSTRB (M_WSTRB),
.WLAST (M_WLAST),
.WVALID (M_WVALID),
.WREADY (M_WREADY),
// Write Response Channel Signals.
.BID (M_BID),
.BRESP (M_BRESP),
.BVALID (net_BVALID),
.BREADY (M_BREADY),
// Read Address Channel Signals.
.ARID (M_ARID),
.ARADDR (M_ARADDR),
.ARLEN (M_ARLEN),
.ARSIZE (M_ARSIZE),
.ARBURST (M_ARBURST),
.ARLOCK (M_ARLOCK),
.ARCACHE (M_ARCACHE),
.ARPROT (M_ARPROT),
.ARVALID (M_ARVALID),
.ARREADY (M_ARREADY),
// Read Data Channel Signals.
.RID (M_RID),
.RDATA (M_RDATA),
.RRESP (M_RRESP),
.RLAST (M_RLAST),
.RVALID (net_RVALID),
.RREADY (M_RREADY));
/* Call to BFM APIs */
task automatic read_burst(input [address_bus_width-1:0] addr,input [axi_len_width-1:0] len,input [axi_size_width-1:0] siz,input [axi_brst_type_width-1:0] burst,input [axi_lock_width-1:0] lck,input [axi_cache_width-1:0] cache,input [axi_prot_width-1:0] prot,output [(axi_mgp_data_width*axi_burst_len)-1:0] data, output [(axi_rsp_width*axi_burst_len)-1:0] response);
if(enable_this_port)begin
if(lck !== AXI_NRML)
master.READ_BURST(EXCL_ID,addr,len,siz,burst,lck,cache,prot,data,response);
else
master.READ_BURST(get_id(1),addr,len,siz,burst,lck,cache,prot,data,response);
end else begin
$display("[%0d] : %0s : %0s : Port is disabled. 'read_burst' will not be executed...",$time, DISP_ERR, master_name);
if(STOP_ON_ERROR) $stop;
end
endtask
task automatic write_burst(input [address_bus_width-1:0] addr,input [axi_len_width-1:0] len,input [axi_size_width-1:0] siz,input [axi_brst_type_width-1:0] burst,input [axi_lock_width-1:0] lck,input [axi_cache_width-1:0] cache,input [axi_prot_width-1:0] prot,input [(axi_mgp_data_width*axi_burst_len)-1:0] data,input integer datasize, output [axi_rsp_width-1:0] response);
if(enable_this_port)begin
if(lck !== AXI_NRML)
master.WRITE_BURST(EXCL_ID,addr,len,siz,burst,lck,cache,prot,data,datasize,response);
else
master.WRITE_BURST(get_id(1),addr,len,siz,burst,lck,cache,prot,data,datasize,response);
end else begin
$display("[%0d] : %0s : %0s : Port is disabled. 'write_burst' will not be executed...",$time, DISP_ERR, master_name);
if(STOP_ON_ERROR) $stop;
end
endtask
task automatic write_burst_concurrent(input [address_bus_width-1:0] addr,input [axi_len_width-1:0] len,input [axi_size_width-1:0] siz,input [axi_brst_type_width-1:0] burst,input [axi_lock_width-1:0] lck,input [axi_cache_width-1:0] cache,input [axi_prot_width-1:0] prot,input [(axi_mgp_data_width*axi_burst_len)-1:0] data,input integer datasize, output [axi_rsp_width-1:0] response);
if(enable_this_port)begin
if(lck !== AXI_NRML)
master.WRITE_BURST_CONCURRENT(EXCL_ID,addr,len,siz,burst,lck,cache,prot,data,datasize,response);
else
master.WRITE_BURST_CONCURRENT(get_id(1),addr,len,siz,burst,lck,cache,prot,data,datasize,response);
end else begin
$display("[%0d] : %0s : %0s : Port is disabled. 'write_burst_concurrent' will not be executed...",$time, DISP_ERR, master_name);
if(STOP_ON_ERROR) $stop;
end
endtask
/* local */
function automatic[id_bus_width-1:0] get_id;
input dummy;
begin
case(use_id_no)
// l2m1 (CPU000)
0 : get_id = 12'b11_000_000_00_00;
1 : get_id = 12'b11_010_000_00_00;
2 : get_id = 12'b11_011_000_00_00;
3 : get_id = 12'b11_100_000_00_00;
4 : get_id = 12'b11_101_000_00_00;
5 : get_id = 12'b11_110_000_00_00;
6 : get_id = 12'b11_111_000_00_00;
// l2m1 (CPU001)
7 : get_id = 12'b11_000_001_00_00;
8 : get_id = 12'b11_010_001_00_00;
9 : get_id = 12'b11_011_001_00_00;
10 : get_id = 12'b11_100_001_00_00;
11 : get_id = 12'b11_101_001_00_00;
12 : get_id = 12'b11_110_001_00_00;
13 : get_id = 12'b11_111_001_00_00;
endcase
if(use_id_no == 13)
use_id_no = 0;
else
use_id_no = use_id_no+1;
end
endfunction
/* Write data from file */
task automatic write_from_file;
input [(max_chars*8)-1:0] file_name;
input [addr_width-1:0] start_addr;
input [int_width-1:0] wr_size;
output [axi_rsp_width-1:0] response;
reg [axi_rsp_width-1:0] wresp,rwrsp;
reg [addr_width-1:0] addr;
reg [(axi_burst_len*data_bus_width)-1 : 0] wr_data;
integer bytes;
integer trnsfr_bytes;
integer wr_fd;
integer succ;
integer trnsfr_lngth;
reg concurrent;
reg [id_bus_width-1:0] wr_id;
reg [axi_size_width-1:0] siz;
reg [axi_brst_type_width-1:0] burst;
reg [axi_lock_width-1:0] lck;
reg [axi_cache_width-1:0] cache;
reg [axi_prot_width-1:0] prot;
begin
if(!enable_this_port) begin
$display("[%0d] : %0s : %0s : Port is disabled. 'write_from_file' will not be executed...",$time, DISP_ERR, master_name);
if(STOP_ON_ERROR) $stop;
end else begin
siz = 2;
burst = 1;
lck = 0;
cache = 0;
prot = 0;
addr = start_addr;
bytes = wr_size;
wresp = 0;
concurrent = $random;
if(bytes > (axi_burst_len * data_bus_width/8))
trnsfr_bytes = (axi_burst_len * data_bus_width/8);
else
trnsfr_bytes = bytes;
if(bytes > (axi_burst_len * data_bus_width/8))
trnsfr_lngth = axi_burst_len-1;
else if(bytes%(data_bus_width/8) == 0)
trnsfr_lngth = bytes/(data_bus_width/8) - 1;
else
trnsfr_lngth = bytes/(data_bus_width/8);
wr_id = get_id(1);
wr_fd = $fopen(file_name,"r");
while (bytes > 0) begin
repeat(axi_burst_len) begin /// get the data for 1 AXI burst transaction
wr_data = wr_data >> data_bus_width;
succ = $fscanf(wr_fd,"%h",wr_data[(axi_burst_len*data_bus_width)-1 :(axi_burst_len*data_bus_width)-data_bus_width ]); /// write as 4 bytes (data_bus_width) ..
end
if(concurrent)
master.WRITE_BURST_CONCURRENT(wr_id, addr, trnsfr_lngth, siz, burst, lck, cache, prot, wr_data, trnsfr_bytes, rwrsp);
else
master.WRITE_BURST(wr_id, addr, trnsfr_lngth, siz, burst, lck, cache, prot, wr_data, trnsfr_bytes, rwrsp);
bytes = bytes - trnsfr_bytes;
addr = addr + trnsfr_bytes;
if(bytes >= (axi_burst_len * data_bus_width/8) )
trnsfr_bytes = (axi_burst_len * data_bus_width/8); //
else
trnsfr_bytes = bytes;
if(bytes > (axi_burst_len * data_bus_width/8))
trnsfr_lngth = axi_burst_len-1;
else if(bytes%(data_bus_width/8) == 0)
trnsfr_lngth = bytes/(data_bus_width/8) - 1;
else
trnsfr_lngth = bytes/(data_bus_width/8);
wresp = wresp | rwrsp;
end /// while
response = wresp;
end
end
endtask
/* Read data to file */
task automatic read_to_file;
input [(max_chars*8)-1:0] file_name;
input [addr_width-1:0] start_addr;
input [int_width-1:0] rd_size;
output [axi_rsp_width-1:0] response;
reg [axi_rsp_width-1:0] rresp, rrrsp;
reg [addr_width-1:0] addr;
integer bytes;
integer trnsfr_lngth;
reg [(axi_burst_len*data_bus_width)-1 :0] rd_data;
integer rd_fd;
reg [id_bus_width-1:0] rd_id;
reg [axi_size_width-1:0] siz;
reg [axi_brst_type_width-1:0] burst;
reg [axi_lock_width-1:0] lck;
reg [axi_cache_width-1:0] cache;
reg [axi_prot_width-1:0] prot;
begin
if(!enable_this_port) begin
$display("[%0d] : %0s : %0s : Port is disabled. 'read_to_file' will not be executed...",$time, DISP_ERR, master_name);
if(STOP_ON_ERROR) $stop;
end else begin
siz = 2;
burst = 1;
lck = 0;
cache = 0;
prot = 0;
addr = start_addr;
rresp = 0;
bytes = rd_size;
rd_id = get_id(1'b1);
if(bytes > (axi_burst_len * data_bus_width/8))
trnsfr_lngth = axi_burst_len-1;
else if(bytes%(data_bus_width/8) == 0)
trnsfr_lngth = bytes/(data_bus_width/8) - 1;
else
trnsfr_lngth = bytes/(data_bus_width/8);
rd_fd = $fopen(file_name,"w");
while (bytes > 0) begin
master.READ_BURST(rd_id, addr, trnsfr_lngth, siz, burst, lck, cache, prot, rd_data, rrrsp);
repeat(trnsfr_lngth+1) begin
$fdisplayh(rd_fd,rd_data[data_bus_width-1:0]);
rd_data = rd_data >> data_bus_width;
end
addr = addr + (trnsfr_lngth+1)*4;
if(bytes >= (axi_burst_len * data_bus_width/8) )
bytes = bytes - (axi_burst_len * data_bus_width/8); //
else
bytes = 0;
if(bytes > (axi_burst_len * data_bus_width/8))
trnsfr_lngth = axi_burst_len-1;
else if(bytes%(data_bus_width/8) == 0)
trnsfr_lngth = bytes/(data_bus_width/8) - 1;
else
trnsfr_lngth = bytes/(data_bus_width/8);
rresp = rresp | rrrsp;
end /// while
response = rresp;
end
end
endtask
/* Write data (used for transfer size <= 128 Bytes */
task automatic write_data;
input [addr_width-1:0] start_addr;
input [max_transfer_bytes_width:0] wr_size;
input [(max_transfer_bytes*8)-1:0] w_data;
output [axi_rsp_width-1:0] response;
reg [axi_rsp_width-1:0] wresp,rwrsp;
reg [addr_width-1:0] addr;
reg [7:0] bytes,tmp_bytes;
integer trnsfr_bytes;
reg [(max_transfer_bytes*8)-1:0] wr_data;
integer trnsfr_lngth;
reg concurrent;
reg [id_bus_width-1:0] wr_id;
reg [axi_size_width-1:0] siz;
reg [axi_brst_type_width-1:0] burst;
reg [axi_lock_width-1:0] lck;
reg [axi_cache_width-1:0] cache;
reg [axi_prot_width-1:0] prot;
integer pad_bytes;
begin
if(!enable_this_port) begin
$display("[%0d] : %0s : %0s : Port is disabled. 'write_data' will not be executed...",$time, DISP_ERR, master_name);
if(STOP_ON_ERROR) $stop;
end else begin
addr = start_addr;
bytes = wr_size;
wresp = 0;
wr_data = w_data;
concurrent = $random;
siz = 2;
burst = 1;
lck = 0;
cache = 0;
prot = 0;
pad_bytes = start_addr[clogb2(data_bus_width/8)-1:0];
wr_id = get_id(1);
if(bytes+pad_bytes > (data_bus_width/8*axi_burst_len)) begin /// for unaligned address
trnsfr_bytes = (data_bus_width*axi_burst_len)/8 - pad_bytes;//start_addr[1:0];
trnsfr_lngth = axi_burst_len-1;
end else begin
trnsfr_bytes = bytes;
tmp_bytes = bytes + pad_bytes;//start_addr[1:0];
if(tmp_bytes%(data_bus_width/8) == 0)
trnsfr_lngth = tmp_bytes/(data_bus_width/8) - 1;
else
trnsfr_lngth = tmp_bytes/(data_bus_width/8);
end
while (bytes > 0) begin
if(concurrent)
master.WRITE_BURST_CONCURRENT(wr_id, addr, trnsfr_lngth, siz, burst, lck, cache, prot, wr_data[(axi_burst_len*data_bus_width)-1:0], trnsfr_bytes, rwrsp);
else
master.WRITE_BURST(wr_id, addr, trnsfr_lngth, siz, burst, lck, cache, prot, wr_data[(axi_burst_len*data_bus_width)-1:0], trnsfr_bytes, rwrsp);
wr_data = wr_data >> (trnsfr_bytes*8);
bytes = bytes - trnsfr_bytes;
addr = addr + trnsfr_bytes;
if(bytes > (axi_burst_len * data_bus_width/8)) begin
trnsfr_bytes = (axi_burst_len * data_bus_width/8) - pad_bytes;//start_addr[1:0];
trnsfr_lngth = axi_burst_len-1;
end else begin
trnsfr_bytes = bytes;
tmp_bytes = bytes + pad_bytes;//start_addr[1:0];
if(tmp_bytes%(data_bus_width/8) == 0)
trnsfr_lngth = tmp_bytes/(data_bus_width/8) - 1;
else
trnsfr_lngth = tmp_bytes/(data_bus_width/8);
end
wresp = wresp | rwrsp;
end /// while
response = wresp;
end
end
endtask
/* Read data (used for transfer size <= 128 Bytes */
task automatic read_data;
input [addr_width-1:0] start_addr;
input [max_transfer_bytes_width:0] rd_size;
output [(max_transfer_bytes*8)-1:0] r_data;
output [axi_rsp_width-1:0] response;
reg [axi_rsp_width-1:0] rresp,rdrsp;
reg [addr_width-1:0] addr;
reg [max_transfer_bytes_width:0] bytes,tmp_bytes;
integer trnsfr_bytes;
reg [(max_transfer_bytes*8)-1 : 0] rd_data;
reg [(axi_burst_len*data_bus_width)-1:0] rcv_rd_data;
integer total_rcvd_bytes;
integer trnsfr_lngth;
integer i;
reg [id_bus_width-1:0] rd_id;
reg [axi_size_width-1:0] siz;
reg [axi_brst_type_width-1:0] burst;
reg [axi_lock_width-1:0] lck;
reg [axi_cache_width-1:0] cache;
reg [axi_prot_width-1:0] prot;
integer pad_bytes;
begin
if(!enable_this_port) begin
$display("[%0d] : %0s : %0s : Port is disabled. 'read_data' will not be executed...",$time, DISP_ERR, master_name);
if(STOP_ON_ERROR) $stop;
end else begin
addr = start_addr;
bytes = rd_size;
rresp = 0;
total_rcvd_bytes = 0;
rd_data = 0;
rd_id = get_id(1'b1);
siz = 2;
burst = 1;
lck = 0;
cache = 0;
prot = 0;
pad_bytes = start_addr[clogb2(data_bus_width/8)-1:0];
if(bytes+ pad_bytes > (axi_burst_len * data_bus_width/8)) begin /// for unaligned address
trnsfr_bytes = (axi_burst_len * data_bus_width/8) - pad_bytes;//start_addr[1:0];
trnsfr_lngth = axi_burst_len-1;
end else begin
trnsfr_bytes = bytes;
tmp_bytes = bytes + pad_bytes;//start_addr[1:0];
if(tmp_bytes%(data_bus_width/8) == 0)
trnsfr_lngth = tmp_bytes/(data_bus_width/8) - 1;
else
trnsfr_lngth = tmp_bytes/(data_bus_width/8);
end
while (bytes > 0) begin
master.READ_BURST(rd_id,addr, trnsfr_lngth, siz, burst, lck, cache, prot, rcv_rd_data, rdrsp);
for(i = 0; i < trnsfr_bytes; i = i+1) begin
rd_data = rd_data >> 8;
rd_data[(max_transfer_bytes*8)-1 : (max_transfer_bytes*8)-8] = rcv_rd_data[7:0];
rcv_rd_data = rcv_rd_data >> 8;
total_rcvd_bytes = total_rcvd_bytes+1;
end
bytes = bytes - trnsfr_bytes;
addr = addr + trnsfr_bytes;
if(bytes > (axi_burst_len * data_bus_width/8)) begin
trnsfr_bytes = (axi_burst_len * data_bus_width/8) - pad_bytes;//start_addr[1:0];
trnsfr_lngth = 15;
end else begin
trnsfr_bytes = bytes;
tmp_bytes = bytes + pad_bytes;//start_addr[1:0];
if(tmp_bytes%(data_bus_width/8) == 0)
trnsfr_lngth = tmp_bytes/(data_bus_width/8) - 1;
else
trnsfr_lngth = tmp_bytes/(data_bus_width/8);
end
rresp = rresp | rdrsp;
end /// while
rd_data = rd_data >> (max_transfer_bytes - total_rcvd_bytes)*8;
r_data = rd_data;
response = rresp;
end
end
endtask
/* Wait Register Update in PL */
/* Issue a series of 1 burst length reads until the expected data pattern is received */
task automatic wait_reg_update;
input [addr_width-1:0] addri;
input [data_width-1:0] datai;
input [data_width-1:0] maski;
input [int_width-1:0] time_interval;
input [int_width-1:0] time_out;
output [data_width-1:0] data_o;
output upd_done;
reg [addr_width-1:0] addr;
reg [data_width-1:0] data_i;
reg [data_width-1:0] mask_i;
integer time_int;
integer timeout;
reg [axi_rsp_width-1:0] rdrsp;
reg [id_bus_width-1:0] rd_id;
reg [axi_size_width-1:0] siz;
reg [axi_brst_type_width-1:0] burst;
reg [axi_lock_width-1:0] lck;
reg [axi_cache_width-1:0] cache;
reg [axi_prot_width-1:0] prot;
reg [data_width-1:0] rcv_data;
integer trnsfr_lngth;
reg rd_loop;
reg timed_out;
integer i;
integer cycle_cnt;
begin
addr = addri;
data_i = datai;
mask_i = maski;
time_int = time_interval;
timeout = time_out;
timed_out = 0;
cycle_cnt = 0;
if(!enable_this_port) begin
$display("[%0d] : %0s : %0s : Port is disabled. 'wait_reg_update' will not be executed...",$time, DISP_ERR, master_name);
upd_done = 0;
if(STOP_ON_ERROR) $stop;
end else begin
rd_id = get_id(1'b1);
siz = 2;
burst = 1;
lck = 0;
cache = 0;
prot = 0;
trnsfr_lngth = 0;
rd_loop = 1;
fork
begin
while(!timed_out & rd_loop) begin
cycle_cnt = cycle_cnt + 1;
if(cycle_cnt >= timeout) timed_out = 1;
@(posedge M_ACLK);
end
end
begin
while (rd_loop) begin
if(DEBUG_INFO)
$display("[%0d] : %0s : %0s : Reading Register mapped at Address(0x%0h) ",$time, master_name, DISP_INFO, addr);
master.READ_BURST(rd_id,addr, trnsfr_lngth, siz, burst, lck, cache, prot, rcv_data, rdrsp);
if(DEBUG_INFO)
$display("[%0d] : %0s : %0s : Reading Register returned (0x%0h) ",$time, master_name, DISP_INFO, rcv_data);
if(((rcv_data & ~mask_i) === (data_i & ~mask_i)) | timed_out)
rd_loop = 0;
else
repeat(time_int) @(posedge M_ACLK);
end /// while
end
join
data_o = rcv_data & ~mask_i;
if(timed_out) begin
$display("[%0d] : %0s : %0s : 'wait_reg_update' timed out ... Register is not updated ",$time, DISP_ERR, master_name);
if(STOP_ON_ERROR) $stop;
end else
upd_done = 1;
end
end
endtask
endmodule
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//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module soc_design_dma_read_data_mux (
// inputs:
byte_access,
clk,
clk_en,
dma_ctl_address,
dma_ctl_chipselect,
dma_ctl_write_n,
dma_ctl_writedata,
hw,
read_readdata,
read_readdatavalid,
readaddress,
readaddress_inc,
reset_n,
// outputs:
fifo_wr_data
)
;
output [ 15: 0] fifo_wr_data;
input byte_access;
input clk;
input clk_en;
input [ 2: 0] dma_ctl_address;
input dma_ctl_chipselect;
input dma_ctl_write_n;
input [ 25: 0] dma_ctl_writedata;
input hw;
input [ 15: 0] read_readdata;
input read_readdatavalid;
input [ 25: 0] readaddress;
input [ 4: 0] readaddress_inc;
input reset_n;
wire control_write;
wire [ 15: 0] fifo_wr_data;
wire length_write;
wire read_data_mux_input;
reg readdata_mux_select;
assign control_write = dma_ctl_chipselect & ~dma_ctl_write_n & ((dma_ctl_address == 6) || (dma_ctl_address == 7));
assign length_write = dma_ctl_chipselect & ~dma_ctl_write_n & (dma_ctl_address == 3);
assign read_data_mux_input = ((control_write && dma_ctl_writedata[3] || length_write))? readaddress[1 : 0] :
(read_readdatavalid)? (readdata_mux_select + readaddress_inc) :
readdata_mux_select;
// Reset value: the transaction size bits of the read address reset value.
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
readdata_mux_select <= 0;
else if (clk_en)
readdata_mux_select <= read_data_mux_input;
end
assign fifo_wr_data[15 : 8] = read_readdata[15 : 8];
assign fifo_wr_data[7 : 0] = ({8 {(byte_access & (readdata_mux_select == 0))}} & read_readdata[7 : 0]) |
({8 {(byte_access & (readdata_mux_select == 1))}} & read_readdata[15 : 8]) |
({8 {hw}} & read_readdata[7 : 0]);
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module soc_design_dma_byteenables (
// inputs:
byte_access,
hw,
write_address,
// outputs:
write_byteenable
)
;
output [ 1: 0] write_byteenable;
input byte_access;
input hw;
input [ 25: 0] write_address;
wire wa_0_is_0;
wire wa_0_is_1;
wire [ 1: 0] write_byteenable;
assign wa_0_is_1 = write_address[0] == 1'h1;
assign wa_0_is_0 = write_address[0] == 1'h0;
assign write_byteenable = ({2 {byte_access}} & {wa_0_is_1, wa_0_is_0}) |
({2 {hw}} & 2'b11);
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module soc_design_dma_fifo_module_fifo_ram_module (
// inputs:
clk,
data,
rdaddress,
rdclken,
reset_n,
wraddress,
wrclock,
wren,
// outputs:
q
)
;
output [ 15: 0] q;
input clk;
input [ 15: 0] data;
input [ 4: 0] rdaddress;
input rdclken;
input reset_n;
input [ 4: 0] wraddress;
input wrclock;
input wren;
reg [ 15: 0] mem_array [ 31: 0];
wire [ 15: 0] q;
reg [ 4: 0] read_address;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
read_address <= 0;
else if (rdclken)
read_address <= rdaddress;
end
// Data read is synchronized through latent_rdaddress.
assign q = mem_array[read_address];
always @(posedge wrclock)
begin
// Write data
if (wren)
mem_array[wraddress] <= data;
end
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// always @(rdaddress)
// begin
// read_address = rdaddress;
// end
//
//
// lpm_ram_dp lpm_ram_dp_component
// (
// .data (data),
// .q (q),
// .rdaddress (read_address),
// .rdclken (rdclken),
// .rdclock (clk),
// .wraddress (wraddress),
// .wrclock (wrclock),
// .wren (wren)
// );
//
// defparam lpm_ram_dp_component.lpm_file = "UNUSED",
// lpm_ram_dp_component.lpm_hint = "USE_EAB=ON",
// lpm_ram_dp_component.lpm_indata = "REGISTERED",
// lpm_ram_dp_component.lpm_outdata = "UNREGISTERED",
// lpm_ram_dp_component.lpm_rdaddress_control = "REGISTERED",
// lpm_ram_dp_component.lpm_width = 16,
// lpm_ram_dp_component.lpm_widthad = 5,
// lpm_ram_dp_component.lpm_wraddress_control = "REGISTERED",
// lpm_ram_dp_component.suppress_memory_conversion_warnings = "ON";
//
//synthesis read_comments_as_HDL off
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module soc_design_dma_fifo_module (
// inputs:
clk,
clk_en,
fifo_read,
fifo_wr_data,
fifo_write,
flush_fifo,
inc_pending_data,
reset_n,
// outputs:
fifo_datavalid,
fifo_empty,
fifo_rd_data,
p1_fifo_full
)
;
output fifo_datavalid;
output fifo_empty;
output [ 15: 0] fifo_rd_data;
output p1_fifo_full;
input clk;
input clk_en;
input fifo_read;
input [ 15: 0] fifo_wr_data;
input fifo_write;
input flush_fifo;
input inc_pending_data;
input reset_n;
wire [ 4: 0] estimated_rdaddress;
reg [ 4: 0] estimated_wraddress;
wire fifo_datavalid;
wire fifo_dec;
reg fifo_empty;
reg fifo_full;
wire fifo_inc;
wire [ 15: 0] fifo_ram_q;
wire [ 15: 0] fifo_rd_data;
reg last_write_collision;
reg [ 15: 0] last_write_data;
wire [ 4: 0] p1_estimated_wraddress;
wire p1_fifo_empty;
wire p1_fifo_full;
wire [ 4: 0] p1_wraddress;
wire [ 4: 0] rdaddress;
reg [ 4: 0] rdaddress_reg;
reg [ 4: 0] wraddress;
wire write_collision;
assign p1_wraddress = (fifo_write)? wraddress - 1 :
wraddress;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
wraddress <= 0;
else if (clk_en)
if (flush_fifo)
wraddress <= 0;
else
wraddress <= p1_wraddress;
end
assign rdaddress = flush_fifo ? 0 : fifo_read ? (rdaddress_reg - 1) : rdaddress_reg;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
rdaddress_reg <= 0;
else
rdaddress_reg <= rdaddress;
end
assign fifo_datavalid = ~fifo_empty;
assign fifo_inc = fifo_write & ~fifo_read;
assign fifo_dec = fifo_read & ~fifo_write;
assign estimated_rdaddress = rdaddress_reg - 1;
assign p1_estimated_wraddress = (inc_pending_data)? estimated_wraddress - 1 :
estimated_wraddress;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
estimated_wraddress <= {5 {1'b1}};
else if (clk_en)
if (flush_fifo)
estimated_wraddress <= {5 {1'b1}};
else
estimated_wraddress <= p1_estimated_wraddress;
end
assign p1_fifo_empty = flush_fifo | ((~fifo_inc & fifo_empty) | (fifo_dec & (wraddress == estimated_rdaddress)));
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_empty <= 1;
else if (clk_en)
fifo_empty <= p1_fifo_empty;
end
assign p1_fifo_full = ~flush_fifo & ((~fifo_dec & fifo_full) | (inc_pending_data & (estimated_wraddress == rdaddress)));
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_full <= 0;
else if (clk_en)
fifo_full <= p1_fifo_full;
end
assign write_collision = fifo_write && (wraddress == rdaddress);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
last_write_data <= 0;
else if (write_collision)
last_write_data <= fifo_wr_data;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
last_write_collision <= 0;
else if (write_collision)
last_write_collision <= -1;
else if (fifo_read)
last_write_collision <= 0;
end
assign fifo_rd_data = last_write_collision ? last_write_data : fifo_ram_q;
//soc_design_dma_fifo_module_fifo_ram, which is an e_ram
soc_design_dma_fifo_module_fifo_ram_module soc_design_dma_fifo_module_fifo_ram
(
.clk (clk),
.data (fifo_wr_data),
.q (fifo_ram_q),
.rdaddress (rdaddress),
.rdclken (1'b1),
.reset_n (reset_n),
.wraddress (wraddress),
.wrclock (clk),
.wren (fifo_write)
);
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module soc_design_dma_mem_read (
// inputs:
clk,
clk_en,
go,
p1_done_read,
p1_fifo_full,
read_waitrequest,
reset_n,
// outputs:
inc_read,
mem_read_n
)
;
output inc_read;
output mem_read_n;
input clk;
input clk_en;
input go;
input p1_done_read;
input p1_fifo_full;
input read_waitrequest;
input reset_n;
wire inc_read;
wire mem_read_n;
wire p1_read_select;
reg read_select;
reg soc_design_dma_mem_read_access;
reg soc_design_dma_mem_read_idle;
assign mem_read_n = ~read_select;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
read_select <= 0;
else if (clk_en)
read_select <= p1_read_select;
end
assign inc_read = read_select & ~read_waitrequest;
// Transitions into state 'idle'.
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
soc_design_dma_mem_read_idle <= 1;
else if (clk_en)
soc_design_dma_mem_read_idle <= ((soc_design_dma_mem_read_idle == 1) & (go == 0)) |
((soc_design_dma_mem_read_idle == 1) & (p1_done_read == 1)) |
((soc_design_dma_mem_read_idle == 1) & (p1_fifo_full == 1)) |
((soc_design_dma_mem_read_access == 1) & (p1_fifo_full == 1) & (read_waitrequest == 0)) |
((soc_design_dma_mem_read_access == 1) & (p1_done_read == 1) & (read_waitrequest == 0));
end
// Transitions into state 'access'.
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
soc_design_dma_mem_read_access <= 0;
else if (clk_en)
soc_design_dma_mem_read_access <= ((soc_design_dma_mem_read_idle == 1) & (p1_fifo_full == 0) & (p1_done_read == 0) & (go == 1)) |
((soc_design_dma_mem_read_access == 1) & (read_waitrequest == 1)) |
((soc_design_dma_mem_read_access == 1) & (p1_fifo_full == 0) & (p1_done_read == 0) & (read_waitrequest == 0));
end
assign p1_read_select = ({1 {((soc_design_dma_mem_read_access && (read_waitrequest == 1)))}} & 1) |
({1 {((soc_design_dma_mem_read_access && (p1_done_read == 0) && (p1_fifo_full == 0) && (read_waitrequest == 0)))}} & 1) |
({1 {((soc_design_dma_mem_read_idle && (go == 1) && (p1_done_read == 0) && (p1_fifo_full == 0)))}} & 1);
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module soc_design_dma_mem_write (
// inputs:
d1_enabled_write_endofpacket,
fifo_datavalid,
write_waitrequest,
// outputs:
fifo_read,
inc_write,
mem_write_n,
write_select
)
;
output fifo_read;
output inc_write;
output mem_write_n;
output write_select;
input d1_enabled_write_endofpacket;
input fifo_datavalid;
input write_waitrequest;
wire fifo_read;
wire inc_write;
wire mem_write_n;
wire write_select;
assign write_select = fifo_datavalid & ~d1_enabled_write_endofpacket;
assign mem_write_n = ~write_select;
assign fifo_read = write_select & ~write_waitrequest;
assign inc_write = fifo_read;
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
//DMA peripheral soc_design_dma
//Read slaves:
//SDRAM.s1;
//Write slaves:
//SDRAM.s1;
module soc_design_dma (
// inputs:
clk,
dma_ctl_address,
dma_ctl_chipselect,
dma_ctl_write_n,
dma_ctl_writedata,
read_readdata,
read_readdatavalid,
read_waitrequest,
system_reset_n,
write_waitrequest,
// outputs:
dma_ctl_irq,
dma_ctl_readdata,
read_address,
read_chipselect,
read_read_n,
write_address,
write_byteenable,
write_chipselect,
write_write_n,
write_writedata
)
/* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"R101\"" */ ;
output dma_ctl_irq;
output [ 25: 0] dma_ctl_readdata;
output [ 25: 0] read_address;
output read_chipselect;
output read_read_n;
output [ 25: 0] write_address;
output [ 1: 0] write_byteenable;
output write_chipselect;
output write_write_n;
output [ 15: 0] write_writedata;
input clk;
input [ 2: 0] dma_ctl_address;
input dma_ctl_chipselect;
input dma_ctl_write_n;
input [ 25: 0] dma_ctl_writedata;
input [ 15: 0] read_readdata;
input read_readdatavalid;
input read_waitrequest;
input system_reset_n;
input write_waitrequest;
wire busy;
wire byte_access;
wire clk_en;
reg [ 12: 0] control;
reg d1_done_transaction;
reg d1_enabled_write_endofpacket;
reg d1_read_got_endofpacket;
reg d1_softwarereset;
wire dma_ctl_irq;
reg [ 25: 0] dma_ctl_readdata;
reg done;
wire done_transaction;
reg done_write;
wire doubleword;
wire enabled_write_endofpacket;
wire fifo_datavalid;
wire fifo_empty;
wire [ 15: 0] fifo_rd_data;
wire [ 15: 0] fifo_rd_data_as_byte_access;
wire [ 15: 0] fifo_rd_data_as_hw;
wire fifo_read;
wire [ 15: 0] fifo_wr_data;
wire fifo_write;
wire fifo_write_data_valid;
wire flush_fifo;
wire go;
wire hw;
wire i_en;
wire inc_read;
wire inc_write;
wire leen;
reg len;
reg [ 25: 0] length;
reg length_eq_0;
wire mem_read_n;
wire mem_write_n;
wire [ 12: 0] p1_control;
wire [ 25: 0] p1_dma_ctl_readdata;
wire p1_done_read;
wire p1_done_write;
wire p1_fifo_full;
wire [ 25: 0] p1_length;
wire p1_length_eq_0;
wire p1_read_got_endofpacket;
wire [ 25: 0] p1_readaddress;
wire p1_write_got_endofpacket;
wire [ 25: 0] p1_writeaddress;
wire [ 25: 0] p1_writelength;
wire p1_writelength_eq_0;
wire quadword;
wire rcon;
wire [ 25: 0] read_address;
wire read_chipselect;
wire read_endofpacket;
reg read_got_endofpacket;
wire read_read_n;
reg [ 25: 0] readaddress;
wire [ 4: 0] readaddress_inc;
wire reen;
reg reop;
reg reset_n;
wire set_software_reset_bit;
reg software_reset_request;
wire softwarereset;
wire [ 4: 0] status;
wire status_register_write;
wire wcon;
wire ween;
reg weop;
wire word;
wire [ 25: 0] write_address;
wire [ 1: 0] write_byteenable;
wire write_chipselect;
wire write_endofpacket;
reg write_got_endofpacket;
wire write_select;
wire write_write_n;
wire [ 15: 0] write_writedata;
reg [ 25: 0] writeaddress;
wire [ 4: 0] writeaddress_inc;
reg [ 25: 0] writelength;
reg writelength_eq_0;
assign clk_en = 1;
//control_port_slave, which is an e_avalon_slave
//read_master, which is an e_avalon_master
soc_design_dma_read_data_mux the_soc_design_dma_read_data_mux
(
.byte_access (byte_access),
.clk (clk),
.clk_en (clk_en),
.dma_ctl_address (dma_ctl_address),
.dma_ctl_chipselect (dma_ctl_chipselect),
.dma_ctl_write_n (dma_ctl_write_n),
.dma_ctl_writedata (dma_ctl_writedata),
.fifo_wr_data (fifo_wr_data),
.hw (hw),
.read_readdata (read_readdata),
.read_readdatavalid (read_readdatavalid),
.readaddress (readaddress),
.readaddress_inc (readaddress_inc),
.reset_n (reset_n)
);
//write_master, which is an e_avalon_master
soc_design_dma_byteenables the_soc_design_dma_byteenables
(
.byte_access (byte_access),
.hw (hw),
.write_address (write_address),
.write_byteenable (write_byteenable)
);
assign read_read_n = mem_read_n;
assign status_register_write = dma_ctl_chipselect & ~dma_ctl_write_n & (dma_ctl_address == 0);
// read address
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
readaddress <= 26'h0;
else if (clk_en)
readaddress <= p1_readaddress;
end
assign p1_readaddress = ((dma_ctl_chipselect & ~dma_ctl_write_n & (dma_ctl_address == 1)))? dma_ctl_writedata :
(inc_read)? (readaddress + readaddress_inc) :
readaddress;
// write address
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
writeaddress <= 26'h0;
else if (clk_en)
writeaddress <= p1_writeaddress;
end
assign p1_writeaddress = ((dma_ctl_chipselect & ~dma_ctl_write_n & (dma_ctl_address == 2)))? dma_ctl_writedata :
(inc_write)? (writeaddress + writeaddress_inc) :
writeaddress;
// length in bytes
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
length <= 26'h0;
else if (clk_en)
length <= p1_length;
end
assign p1_length = ((dma_ctl_chipselect & ~dma_ctl_write_n & (dma_ctl_address == 3)))? dma_ctl_writedata :
((inc_read && (!length_eq_0)))? length - {1'b0,
1'b0,
1'b0,
hw,
byte_access} :
length;
// control register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
control <= 13'h84;
else if (clk_en)
control <= p1_control;
end
assign p1_control = ((dma_ctl_chipselect & ~dma_ctl_write_n & ((dma_ctl_address == 6) || (dma_ctl_address == 7))))? dma_ctl_writedata :
control;
// write master length
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
writelength <= 26'h0;
else if (clk_en)
writelength <= p1_writelength;
end
assign p1_writelength = ((dma_ctl_chipselect & ~dma_ctl_write_n & (dma_ctl_address == 3)))? dma_ctl_writedata :
((inc_write && (!writelength_eq_0)))? writelength - {1'b0,
1'b0,
1'b0,
hw,
byte_access} :
writelength;
assign p1_writelength_eq_0 = inc_write && (!writelength_eq_0) && ((writelength - {1'b0,
1'b0,
1'b0,
hw,
byte_access}) == 0);
assign p1_length_eq_0 = inc_read && (!length_eq_0) && ((length - {1'b0,
1'b0,
1'b0,
hw,
byte_access}) == 0);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
length_eq_0 <= 1;
else if (clk_en)
if (dma_ctl_chipselect & ~dma_ctl_write_n & (dma_ctl_address == 3))
length_eq_0 <= 0;
else if (p1_length_eq_0)
length_eq_0 <= -1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
writelength_eq_0 <= 1;
else if (clk_en)
if (dma_ctl_chipselect & ~dma_ctl_write_n & (dma_ctl_address == 3))
writelength_eq_0 <= 0;
else if (p1_writelength_eq_0)
writelength_eq_0 <= -1;
end
assign writeaddress_inc = (wcon)? 0 :
{1'b0,
1'b0,
1'b0,
hw,
byte_access};
assign readaddress_inc = (rcon)? 0 :
{1'b0,
1'b0,
1'b0,
hw,
byte_access};
assign p1_dma_ctl_readdata = ({26 {(dma_ctl_address == 0)}} & status) |
({26 {(dma_ctl_address == 1)}} & readaddress) |
({26 {(dma_ctl_address == 2)}} & writeaddress) |
({26 {(dma_ctl_address == 3)}} & writelength) |
({26 {(dma_ctl_address == 6)}} & control);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
dma_ctl_readdata <= 0;
else if (clk_en)
dma_ctl_readdata <= p1_dma_ctl_readdata;
end
assign done_transaction = go & done_write;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
done <= 0;
else if (clk_en)
if (status_register_write)
done <= 0;
else if (done_transaction & ~d1_done_transaction)
done <= -1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
d1_done_transaction <= 0;
else if (clk_en)
d1_done_transaction <= done_transaction;
end
assign busy = go & ~done_write;
assign status[0] = done;
assign status[1] = busy;
assign status[2] = reop;
assign status[3] = weop;
assign status[4] = len;
assign byte_access = control[0];
assign hw = control[1];
assign word = control[2];
assign go = control[3];
assign i_en = control[4];
assign reen = control[5];
assign ween = control[6];
assign leen = control[7];
assign rcon = control[8];
assign wcon = control[9];
assign doubleword = control[10];
assign quadword = control[11];
assign softwarereset = control[12];
assign dma_ctl_irq = i_en & done;
assign p1_read_got_endofpacket = ~status_register_write && (read_got_endofpacket || (read_endofpacket & reen));
assign p1_write_got_endofpacket = ~status_register_write && (write_got_endofpacket || (inc_write & write_endofpacket & ween));
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
read_got_endofpacket <= 0;
else if (clk_en)
read_got_endofpacket <= p1_read_got_endofpacket;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
write_got_endofpacket <= 0;
else if (clk_en)
write_got_endofpacket <= p1_write_got_endofpacket;
end
assign flush_fifo = ~d1_done_transaction & done_transaction;
soc_design_dma_fifo_module the_soc_design_dma_fifo_module
(
.clk (clk),
.clk_en (clk_en),
.fifo_datavalid (fifo_datavalid),
.fifo_empty (fifo_empty),
.fifo_rd_data (fifo_rd_data),
.fifo_read (fifo_read),
.fifo_wr_data (fifo_wr_data),
.fifo_write (fifo_write),
.flush_fifo (flush_fifo),
.inc_pending_data (inc_read),
.p1_fifo_full (p1_fifo_full),
.reset_n (reset_n)
);
//the_soc_design_dma_mem_read, which is an e_instance
soc_design_dma_mem_read the_soc_design_dma_mem_read
(
.clk (clk),
.clk_en (clk_en),
.go (go),
.inc_read (inc_read),
.mem_read_n (mem_read_n),
.p1_done_read (p1_done_read),
.p1_fifo_full (p1_fifo_full),
.read_waitrequest (read_waitrequest),
.reset_n (reset_n)
);
assign fifo_write = fifo_write_data_valid;
assign enabled_write_endofpacket = write_endofpacket & ween;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
d1_enabled_write_endofpacket <= 0;
else if (clk_en)
d1_enabled_write_endofpacket <= enabled_write_endofpacket;
end
soc_design_dma_mem_write the_soc_design_dma_mem_write
(
.d1_enabled_write_endofpacket (d1_enabled_write_endofpacket),
.fifo_datavalid (fifo_datavalid),
.fifo_read (fifo_read),
.inc_write (inc_write),
.mem_write_n (mem_write_n),
.write_select (write_select),
.write_waitrequest (write_waitrequest)
);
assign p1_done_read = (leen && (p1_length_eq_0 || (length_eq_0))) | p1_read_got_endofpacket | p1_done_write;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
len <= 0;
else if (clk_en)
if (status_register_write)
len <= 0;
else if (~d1_done_transaction & done_transaction && (writelength_eq_0))
len <= -1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
reop <= 0;
else if (clk_en)
if (status_register_write)
reop <= 0;
else if (fifo_empty & read_got_endofpacket & d1_read_got_endofpacket)
reop <= -1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
weop <= 0;
else if (clk_en)
if (status_register_write)
weop <= 0;
else if (write_got_endofpacket)
weop <= -1;
end
assign p1_done_write = (leen && (p1_writelength_eq_0 || writelength_eq_0)) | p1_write_got_endofpacket | fifo_empty & d1_read_got_endofpacket;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
d1_read_got_endofpacket <= 0;
else if (clk_en)
d1_read_got_endofpacket <= read_got_endofpacket;
end
// Write has completed when the length goes to 0, or
//the write source said end-of-packet, or
//the read source said end-of-packet and the fifo has emptied.
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
done_write <= 0;
else if (clk_en)
done_write <= p1_done_write;
end
assign read_address = readaddress;
assign write_address = writeaddress;
assign write_chipselect = write_select;
assign read_chipselect = ~read_read_n;
assign write_write_n = mem_write_n;
assign fifo_rd_data_as_byte_access = {fifo_rd_data[7 : 0],
fifo_rd_data[7 : 0]};
assign fifo_rd_data_as_hw = fifo_rd_data[15 : 0];
assign write_writedata = ({16 {byte_access}} & fifo_rd_data_as_byte_access) |
({16 {hw}} & fifo_rd_data_as_hw);
assign fifo_write_data_valid = read_readdatavalid;
assign set_software_reset_bit = ((dma_ctl_chipselect & ~dma_ctl_write_n & ((dma_ctl_address == 6) || (dma_ctl_address == 7)))) & (dma_ctl_address != 7) & dma_ctl_writedata[12];
always @(posedge clk or negedge system_reset_n)
begin
if (system_reset_n == 0)
d1_softwarereset <= 0;
else if (set_software_reset_bit | software_reset_request)
d1_softwarereset <= softwarereset & ~software_reset_request;
end
always @(posedge clk or negedge system_reset_n)
begin
if (system_reset_n == 0)
software_reset_request <= 0;
else if (set_software_reset_bit | software_reset_request)
software_reset_request <= d1_softwarereset & ~software_reset_request;
end
always @(posedge clk or negedge system_reset_n)
begin
if (system_reset_n == 0)
reset_n <= 0;
else
reset_n <= ~(~system_reset_n | software_reset_request);
end
assign read_endofpacket = 0;
assign write_endofpacket = 0;
endmodule
|
module allocator
(/*AUTOARG*/
// Outputs
allocator_cu_valid, allocator_cu_rejected, allocator_wg_id_out,
allocator_cu_id_out, allocator_wf_count, allocator_vgpr_size_out,
allocator_sgpr_size_out, allocator_lds_size_out,
allocator_gds_size_out, allocator_vgpr_start_out,
allocator_sgpr_start_out, allocator_lds_start_out,
allocator_gds_start_out,
// Inputs
clk, rst, inflight_wg_buffer_alloc_wg_id,
inflight_wg_buffer_alloc_num_wf,
inflight_wg_buffer_alloc_vgpr_size,
inflight_wg_buffer_alloc_sgpr_size,
inflight_wg_buffer_alloc_lds_size,
inflight_wg_buffer_alloc_gds_size, dis_controller_cu_busy,
dis_controller_alloc_ack, dis_controller_start_alloc,
grt_cam_up_valid, grt_cam_up_cu_id, grt_cam_up_vgpr_strt,
grt_cam_up_vgpr_size, grt_cam_up_sgpr_strt, grt_cam_up_sgpr_size,
grt_cam_up_lds_strt, grt_cam_up_lds_size, grt_cam_up_gds_strt,
grt_cam_up_gds_size, grt_cam_up_wg_count
);
parameter WG_ID_WIDTH = 6;
parameter CU_ID_WIDTH = 6;
parameter NUMBER_CU = 64;
parameter VGPR_ID_WIDTH = 10;
parameter NUMBER_VGPR_SLOTS = 1024;
parameter SGPR_ID_WIDTH = 10;
parameter NUMBER_SGPR_SLOTS = 1024;
parameter LDS_ID_WIDTH = 10;
parameter NUMBER_LDS_SLOTS = 1024;
parameter WG_SLOT_ID_WIDTH = 10;
parameter NUMBER_WF_SLOTS = 40;
parameter GDS_ID_WIDTH = 10;
parameter GDS_SIZE = 1024;
parameter WF_COUNT_WIDTH = 4;
// Allocation input port
input clk,rst;
input [WG_ID_WIDTH-1:0] inflight_wg_buffer_alloc_wg_id;
input [WF_COUNT_WIDTH-1:0] inflight_wg_buffer_alloc_num_wf;
input [VGPR_ID_WIDTH :0] inflight_wg_buffer_alloc_vgpr_size;
input [SGPR_ID_WIDTH :0] inflight_wg_buffer_alloc_sgpr_size;
input [LDS_ID_WIDTH :0] inflight_wg_buffer_alloc_lds_size;
input [GDS_ID_WIDTH :0] inflight_wg_buffer_alloc_gds_size;
input [NUMBER_CU-1:0] dis_controller_cu_busy;
input dis_controller_alloc_ack;
input dis_controller_start_alloc;
// Allocation output port
output allocator_cu_valid;
output allocator_cu_rejected;
output [WG_ID_WIDTH-1:0] allocator_wg_id_out;
output [CU_ID_WIDTH-1 :0] allocator_cu_id_out;
output [WF_COUNT_WIDTH-1:0] allocator_wf_count;
output [VGPR_ID_WIDTH :0] allocator_vgpr_size_out;
output [SGPR_ID_WIDTH :0] allocator_sgpr_size_out;
output [LDS_ID_WIDTH :0] allocator_lds_size_out;
output [GDS_ID_WIDTH :0] allocator_gds_size_out;
output [VGPR_ID_WIDTH-1 :0] allocator_vgpr_start_out;
output [SGPR_ID_WIDTH-1 :0] allocator_sgpr_start_out;
output [LDS_ID_WIDTH-1 :0] allocator_lds_start_out;
output [GDS_ID_WIDTH-1 :0] allocator_gds_start_out;
// CAM update port
input grt_cam_up_valid;
input [CU_ID_WIDTH-1 :0] grt_cam_up_cu_id;
input [VGPR_ID_WIDTH-1 :0] grt_cam_up_vgpr_strt;
input [VGPR_ID_WIDTH :0] grt_cam_up_vgpr_size;
input [SGPR_ID_WIDTH-1 :0] grt_cam_up_sgpr_strt;
input [SGPR_ID_WIDTH :0] grt_cam_up_sgpr_size;
input [LDS_ID_WIDTH-1 :0] grt_cam_up_lds_strt;
input [LDS_ID_WIDTH :0] grt_cam_up_lds_size;
input [GDS_ID_WIDTH-1 :0] grt_cam_up_gds_strt;
input [GDS_ID_WIDTH :0] grt_cam_up_gds_size;
input [WG_SLOT_ID_WIDTH:0] grt_cam_up_wg_count;
// Flop inputs
reg alloc_valid_i;
reg [WG_ID_WIDTH-1:0] alloc_wg_id_i;
reg [WF_COUNT_WIDTH-1:0] alloc_num_wf_i;
reg [VGPR_ID_WIDTH :0] alloc_vgpr_size_i;
reg [SGPR_ID_WIDTH :0] alloc_sgpr_size_i;
reg [LDS_ID_WIDTH :0] alloc_lds_size_i;
reg [GDS_ID_WIDTH :0] alloc_gds_size_i;
reg [NUMBER_CU-1:0] dis_controller_cu_busy_i;
reg cam_up_valid_i;
reg [CU_ID_WIDTH-1 :0] cam_up_cu_id_i;
reg [VGPR_ID_WIDTH-1 :0] cam_up_vgpr_strt_i;
reg [VGPR_ID_WIDTH :0] cam_up_vgpr_size_i;
reg [SGPR_ID_WIDTH-1 :0] cam_up_sgpr_strt_i;
reg [SGPR_ID_WIDTH :0] cam_up_sgpr_size_i;
reg [LDS_ID_WIDTH-1 :0] cam_up_lds_strt_i;
reg [LDS_ID_WIDTH :0] cam_up_lds_size_i;
reg [GDS_ID_WIDTH-1 :0] cam_up_gds_strt_i;
reg [GDS_ID_WIDTH :0] cam_up_gds_size_i;
reg [WG_SLOT_ID_WIDTH:0] cam_up_wg_count_i;
// cam outputs
reg cam_out_valid;
wire [NUMBER_CU-1 :0] vgpr_search_out, sgpr_search_out, lds_search_out,
wg_search_out;
reg gds_valid;
// Signals that bypass the cam
reg cam_wait_valid;
reg [WG_ID_WIDTH-1 : 0] cam_wait_wg_id;
reg [WF_COUNT_WIDTH-1: 0] cam_wait_wf_count;
reg [VGPR_ID_WIDTH:0] cam_wait_vgpr_size;
reg [SGPR_ID_WIDTH:0] cam_wait_sgpr_size;
reg [LDS_ID_WIDTH:0] cam_wait_lds_size;
reg [GDS_ID_WIDTH:0] cam_wait_gds_size;
reg [GDS_ID_WIDTH-1:0] cam_wait_gds_strt;
reg [NUMBER_CU-1:0] cam_wait_dis_controller_cu_busy;
// And cam outputs to check if there is anything we can use, choose the right cu
reg anded_cam_out_valid;
reg [NUMBER_CU-1: 0] anded_cam_out;
reg [WG_ID_WIDTH-1 :0] anded_cam_wg_id;
reg [WF_COUNT_WIDTH-1: 0] anded_cam_wf_count;
reg [VGPR_ID_WIDTH :0] anded_cam_vgpr_size;
reg [SGPR_ID_WIDTH :0] anded_cam_sgpr_size;
reg [LDS_ID_WIDTH :0] anded_cam_lds_size;
reg [GDS_ID_WIDTH :0] anded_cam_gds_size;
reg [GDS_ID_WIDTH-1 :0] anded_cam_gds_strt;
// Output encoder and find if we can use any cu, also addr the res start ram
reg encoded_cu_out_valid,
encoded_cu_found_valid, encoded_cu_found_valid_comb;
reg [CU_ID_WIDTH-1:0] encoded_cu_id, encoded_cu_id_comb;
reg [WG_ID_WIDTH-1 :0] encoded_cu_wg_id;
reg [WF_COUNT_WIDTH-1: 0] encoded_wf_count;
reg [VGPR_ID_WIDTH :0] encoded_vgpr_size;
reg [SGPR_ID_WIDTH :0] encoded_sgpr_size;
reg [LDS_ID_WIDTH :0] encoded_lds_size;
reg [GDS_ID_WIDTH :0] encoded_gds_size;
reg [GDS_ID_WIDTH-1 :0] encoded_gds_strt;
// res size ram lookup
reg size_ram_valid, size_ram_cu_id_found;
reg [CU_ID_WIDTH-1:0] cu_id_out;
reg [VGPR_ID_WIDTH-1:0] vgpr_start_out;
reg [SGPR_ID_WIDTH-1:0] sgpr_start_out;
reg [LDS_ID_WIDTH-1:0] lds_start_out;
reg [GDS_ID_WIDTH-1:0] gds_start_out;
reg [WG_ID_WIDTH-1 :0] wg_id_out;
reg [VGPR_ID_WIDTH :0] vgpr_size_out;
reg [SGPR_ID_WIDTH :0] sgpr_size_out;
reg [LDS_ID_WIDTH :0] lds_size_out;
reg [GDS_ID_WIDTH :0] gds_size_out;
reg [WF_COUNT_WIDTH-1: 0] wf_count_out;
localparam RAM_SIZE_WIDTH
= VGPR_ID_WIDTH + SGPR_ID_WIDTH + LDS_ID_WIDTH +GDS_ID_WIDTH;
localparam RES_SIZE_VGPR_START = 0;
localparam RES_SIZE_VGPR_END = RES_SIZE_VGPR_START+ VGPR_ID_WIDTH-1;
localparam RES_SIZE_SGPR_START = RES_SIZE_VGPR_END + 1;
localparam RES_SIZE_SGPR_END = RES_SIZE_SGPR_START+ SGPR_ID_WIDTH-1;
localparam RES_SIZE_LDS_START = RES_SIZE_SGPR_END + 1;
localparam RES_SIZE_LDS_END = RES_SIZE_LDS_START+ LDS_ID_WIDTH-1;
localparam RES_SIZE_GDS_START = RES_SIZE_LDS_END + 1;
localparam RES_SIZE_GDS_END = RES_SIZE_GDS_START+ GDS_ID_WIDTH-1;
wire [RAM_SIZE_WIDTH-1 :0] res_size_rd_wire, res_size_wr_wire;
reg [GDS_ID_WIDTH:0] gds_free;
reg [GDS_ID_WIDTH-1:0] gds_strt;
reg [NUMBER_CU-1:0] cu_initialized;
reg pipeline_waiting;
// Instantiate cams
cam_allocator
#(.CU_ID_WIDTH(CU_ID_WIDTH),
.NUMBER_CU(NUMBER_CU),
.RES_ID_WIDTH(VGPR_ID_WIDTH),
.NUMBER_RES_SLOTS(NUMBER_VGPR_SLOTS))
vgpr_cam
(.clk(clk),
.rst(rst),
// Search port in
.res_search_en(alloc_valid_i),
.res_search_size(alloc_vgpr_size_i),
// Search port out
.res_search_out(vgpr_search_out),
// Update port
.cam_wr_en(cam_up_valid_i),
.cam_wr_addr(cam_up_cu_id_i),
.cam_wr_data(cam_up_vgpr_size_i));
cam_allocator
#(.CU_ID_WIDTH(CU_ID_WIDTH),
.NUMBER_CU(NUMBER_CU),
.RES_ID_WIDTH(SGPR_ID_WIDTH),
.NUMBER_RES_SLOTS(NUMBER_SGPR_SLOTS))
sgpr_cam
(.clk(clk),
.rst(rst),
// Search port in
.res_search_en(alloc_valid_i),
.res_search_size(alloc_sgpr_size_i),
// Search port out
.res_search_out(sgpr_search_out),
// Update port
.cam_wr_en(cam_up_valid_i),
.cam_wr_addr(cam_up_cu_id_i),
.cam_wr_data(cam_up_sgpr_size_i));
cam_allocator
#(.CU_ID_WIDTH(CU_ID_WIDTH),
.NUMBER_CU(NUMBER_CU),
.RES_ID_WIDTH(LDS_ID_WIDTH),
.NUMBER_RES_SLOTS(NUMBER_LDS_SLOTS))
lds_cam
(.clk(clk),
.rst(rst),
// Search port in
.res_search_en(alloc_valid_i),
.res_search_size(alloc_lds_size_i),
// Search port out
.res_search_out(lds_search_out),
// Update port
.cam_wr_en(cam_up_valid_i),
.cam_wr_addr(cam_up_cu_id_i),
.cam_wr_data(cam_up_lds_size_i));
cam_allocator
#(.CU_ID_WIDTH(CU_ID_WIDTH),
.NUMBER_CU(NUMBER_CU),
.RES_ID_WIDTH(WG_SLOT_ID_WIDTH),
.NUMBER_RES_SLOTS(NUMBER_WF_SLOTS))
wf_cam
(.clk(clk),
.rst(rst),
// Search port in
.res_search_en(alloc_valid_i),
.res_search_size({{(WG_SLOT_ID_WIDTH+1-(WF_COUNT_WIDTH)){1'b0}},
alloc_num_wf_i}),
// Search port out
.res_search_out(wg_search_out),
// Update port
.cam_wr_en(cam_up_valid_i),
.cam_wr_addr(cam_up_cu_id_i),
.cam_wr_data(cam_up_wg_count_i));
ram_2_port
#(.WORD_SIZE(RAM_SIZE_WIDTH),
.ADDR_SIZE(CU_ID_WIDTH),
.NUM_WORDS(NUMBER_CU))
res_start_cam
(// Outputs
.rd_word (res_size_rd_wire),
// Inputs
.rst (rst),
.clk (clk),
.wr_en (cam_up_valid_i),
.wr_addr (cam_up_cu_id_i),
.wr_word (res_size_wr_wire),
.rd_en (encoded_cu_out_valid &&
encoded_cu_found_valid),
.rd_addr (encoded_cu_id));
assign res_size_wr_wire = { cam_up_lds_strt_i,
cam_up_sgpr_strt_i, cam_up_vgpr_strt_i };
always @(posedge clk or rst) begin
if(rst) begin
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
alloc_gds_size_i <= {(1+(GDS_ID_WIDTH)){1'b0}};
alloc_lds_size_i <= {(1+(LDS_ID_WIDTH)){1'b0}};
alloc_num_wf_i <= {WF_COUNT_WIDTH{1'b0}};
alloc_sgpr_size_i <= {(1+(SGPR_ID_WIDTH)){1'b0}};
alloc_valid_i <= 1'h0;
alloc_vgpr_size_i <= {(1+(VGPR_ID_WIDTH)){1'b0}};
alloc_wg_id_i <= {WG_ID_WIDTH{1'b0}};
anded_cam_gds_size <= {(1+(GDS_ID_WIDTH)){1'b0}};
anded_cam_gds_strt <= {GDS_ID_WIDTH{1'b0}};
anded_cam_lds_size <= {(1+(LDS_ID_WIDTH)){1'b0}};
anded_cam_out <= {NUMBER_CU{1'b0}};
anded_cam_out_valid <= 1'h0;
anded_cam_sgpr_size <= {(1+(SGPR_ID_WIDTH)){1'b0}};
anded_cam_vgpr_size <= {(1+(VGPR_ID_WIDTH)){1'b0}};
anded_cam_wf_count <= {WF_COUNT_WIDTH{1'b0}};
anded_cam_wg_id <= {WG_ID_WIDTH{1'b0}};
cam_up_cu_id_i <= {CU_ID_WIDTH{1'b0}};
cam_up_gds_size_i <= {(1+(GDS_ID_WIDTH)){1'b0}};
cam_up_gds_strt_i <= {GDS_ID_WIDTH{1'b0}};
cam_up_lds_size_i <= {(1+(LDS_ID_WIDTH)){1'b0}};
cam_up_lds_strt_i <= {LDS_ID_WIDTH{1'b0}};
cam_up_sgpr_size_i <= {(1+(SGPR_ID_WIDTH)){1'b0}};
cam_up_sgpr_strt_i <= {SGPR_ID_WIDTH{1'b0}};
cam_up_valid_i <= 1'h0;
cam_up_vgpr_size_i <= {(1+(VGPR_ID_WIDTH)){1'b0}};
cam_up_vgpr_strt_i <= {VGPR_ID_WIDTH{1'b0}};
cam_up_wg_count_i <= {(1+(WG_SLOT_ID_WIDTH)){1'b0}};
cam_wait_dis_controller_cu_busy <= {NUMBER_CU{1'b0}};
cam_wait_gds_size <= {(1+(GDS_ID_WIDTH)){1'b0}};
cam_wait_gds_strt <= {GDS_ID_WIDTH{1'b0}};
cam_wait_lds_size <= {(1+(LDS_ID_WIDTH)){1'b0}};
cam_wait_sgpr_size <= {(1+(SGPR_ID_WIDTH)){1'b0}};
cam_wait_valid <= 1'h0;
cam_wait_vgpr_size <= {(1+(VGPR_ID_WIDTH)){1'b0}};
cam_wait_wf_count <= {WF_COUNT_WIDTH{1'b0}};
cam_wait_wg_id <= {WG_ID_WIDTH{1'b0}};
cu_id_out <= {CU_ID_WIDTH{1'b0}};
cu_initialized <= {NUMBER_CU{1'b0}};
dis_controller_cu_busy_i <= {NUMBER_CU{1'b0}};
encoded_cu_found_valid <= 1'h0;
encoded_cu_id <= {CU_ID_WIDTH{1'b0}};
encoded_cu_out_valid <= 1'h0;
encoded_cu_wg_id <= {WG_ID_WIDTH{1'b0}};
encoded_gds_size <= {(1+(GDS_ID_WIDTH)){1'b0}};
encoded_gds_strt <= {GDS_ID_WIDTH{1'b0}};
encoded_lds_size <= {(1+(LDS_ID_WIDTH)){1'b0}};
encoded_sgpr_size <= {(1+(SGPR_ID_WIDTH)){1'b0}};
encoded_vgpr_size <= {(1+(VGPR_ID_WIDTH)){1'b0}};
encoded_wf_count <= {WF_COUNT_WIDTH{1'b0}};
gds_free <= {(1+(GDS_ID_WIDTH)){1'b0}};
gds_size_out <= {(1+(GDS_ID_WIDTH)){1'b0}};
gds_start_out <= {GDS_ID_WIDTH{1'b0}};
gds_strt <= {GDS_ID_WIDTH{1'b0}};
gds_valid <= 1'h0;
lds_size_out <= {(1+(LDS_ID_WIDTH)){1'b0}};
pipeline_waiting <= 1'h0;
sgpr_size_out <= {(1+(SGPR_ID_WIDTH)){1'b0}};
size_ram_cu_id_found <= 1'h0;
size_ram_valid <= 1'h0;
vgpr_size_out <= {(1+(VGPR_ID_WIDTH)){1'b0}};
wf_count_out <= {WF_COUNT_WIDTH{1'b0}};
wg_id_out <= {WG_ID_WIDTH{1'b0}};
// End of automatics
gds_free <= GDS_SIZE;
end
else begin // if (rst)
// Locks the pipeline until an ack arrive from the controller
if(encoded_cu_out_valid && !pipeline_waiting) begin
pipeline_waiting <= 1'b1;
end
if(dis_controller_alloc_ack) begin
pipeline_waiting <= 1'b0;
end
if(!pipeline_waiting) begin
//////////////////////////////////
// Cam search pipeline
//////////////////////////////////
alloc_valid_i <= dis_controller_start_alloc;
alloc_wg_id_i <= inflight_wg_buffer_alloc_wg_id;
alloc_num_wf_i <= inflight_wg_buffer_alloc_num_wf;
alloc_vgpr_size_i <= inflight_wg_buffer_alloc_vgpr_size;
alloc_sgpr_size_i <= inflight_wg_buffer_alloc_sgpr_size;
alloc_lds_size_i <= inflight_wg_buffer_alloc_lds_size;
alloc_gds_size_i <= inflight_wg_buffer_alloc_gds_size;
dis_controller_cu_busy_i <= dis_controller_cu_busy;
// Wait for cam search
cam_wait_valid <= alloc_valid_i;
cam_wait_wg_id <= alloc_wg_id_i;
cam_wait_wf_count <= alloc_num_wf_i;
cam_wait_vgpr_size <= alloc_vgpr_size_i;
cam_wait_sgpr_size <= alloc_sgpr_size_i;
cam_wait_lds_size <= alloc_lds_size_i;
cam_wait_gds_size <= alloc_gds_size_i;
cam_wait_gds_strt <= gds_strt;
cam_wait_dis_controller_cu_busy <= dis_controller_cu_busy_i;
if(gds_free >= alloc_gds_size_i)
gds_valid <= 1'b1;
else
gds_valid <= 1'b0;
// AND all cam outs
anded_cam_out_valid <= cam_wait_valid;
anded_cam_out <= vgpr_search_out & sgpr_search_out & lds_search_out &
wg_search_out & {NUMBER_CU{gds_valid}} &
(~cam_wait_dis_controller_cu_busy);
anded_cam_wg_id <= cam_wait_wg_id;
anded_cam_wf_count <= cam_wait_wf_count;
anded_cam_vgpr_size <= cam_wait_vgpr_size;
anded_cam_sgpr_size <= cam_wait_sgpr_size;
anded_cam_lds_size <= cam_wait_lds_size;
anded_cam_gds_size <= cam_wait_gds_size;
anded_cam_gds_strt <= cam_wait_gds_strt;
// Use the encoded output to find the start of the resources
encoded_cu_out_valid <= anded_cam_out_valid;
encoded_cu_found_valid <= encoded_cu_found_valid_comb;
encoded_cu_id <= encoded_cu_id_comb;
encoded_wf_count <= anded_cam_wf_count;
encoded_cu_wg_id <= anded_cam_wg_id;
encoded_vgpr_size <= anded_cam_vgpr_size;
encoded_sgpr_size <= anded_cam_sgpr_size;
encoded_lds_size <= anded_cam_lds_size;
encoded_gds_size <= anded_cam_gds_size;
encoded_gds_strt <= anded_cam_gds_strt;
// Output the starts and the cu id
size_ram_valid <= encoded_cu_out_valid;
size_ram_cu_id_found <= encoded_cu_found_valid;
cu_id_out <= encoded_cu_id;
wg_id_out <= encoded_cu_wg_id;
wf_count_out <= encoded_wf_count;
vgpr_size_out <= encoded_vgpr_size;
sgpr_size_out <= encoded_sgpr_size;
lds_size_out <= encoded_lds_size;
gds_size_out <= encoded_gds_size;
gds_start_out <= encoded_gds_strt;
end // if (pipeline_waiting)
//////////////////////////////////
// Cam write
//////////////////////////////////
cam_up_valid_i <= grt_cam_up_valid;
cam_up_cu_id_i <= grt_cam_up_cu_id;
cam_up_vgpr_strt_i <= grt_cam_up_vgpr_strt;
cam_up_sgpr_strt_i <= grt_cam_up_sgpr_strt;
cam_up_lds_strt_i <= grt_cam_up_lds_strt;
cam_up_gds_strt_i <= grt_cam_up_gds_strt;
cam_up_wg_count_i <= grt_cam_up_wg_count;
if(cam_up_valid_i) begin
cu_initialized[cam_up_cu_id_i] <= 1'b1;
end
//////////////////////////////////
// Size ram write
//////////////////////////////////
cam_up_vgpr_size_i <= grt_cam_up_vgpr_size;
cam_up_sgpr_size_i <= grt_cam_up_sgpr_size;
cam_up_lds_size_i <= grt_cam_up_lds_size;
cam_up_gds_size_i <= grt_cam_up_gds_size;
if(cam_up_valid_i) begin
gds_free <= cam_up_gds_size_i;
gds_strt <= cam_up_gds_strt_i;
end
else if(alloc_valid_i && (gds_free >= alloc_gds_size_i) && !pipeline_waiting) begin
gds_free <= gds_free - alloc_gds_size_i;
gds_strt <= gds_strt + alloc_gds_size_i;
end
end // else: !if(rst)
end // always @ (posedge clk or rst)
assign allocator_cu_valid = size_ram_valid;
assign allocator_cu_rejected = ~size_ram_cu_id_found;
assign allocator_wg_id_out = wg_id_out;
assign allocator_cu_id_out = cu_id_out;
assign allocator_vgpr_size_out = vgpr_size_out;
assign allocator_sgpr_size_out = sgpr_size_out;
assign allocator_lds_size_out = lds_size_out;
assign allocator_gds_size_out = gds_size_out;
assign allocator_vgpr_start_out = (!cu_initialized[cu_id_out])? 0 :
res_size_rd_wire[RES_SIZE_VGPR_END:RES_SIZE_VGPR_START];
assign allocator_sgpr_start_out = (!cu_initialized[cu_id_out])? 0 :
res_size_rd_wire[RES_SIZE_SGPR_END:RES_SIZE_SGPR_START];
assign allocator_lds_start_out = (!cu_initialized[cu_id_out])? 0 :
res_size_rd_wire[RES_SIZE_LDS_END:RES_SIZE_LDS_START];
assign allocator_gds_start_out = (!cu_initialized[cu_id_out])? 0 :
gds_start_out;
assign allocator_wf_count = wf_count_out;
always @ ( /*AUTOSENSE*/anded_cam_out) begin : PRI_ENCODER_CAM_OUT
integer i;
reg found_valid;
found_valid = 1'b0;
encoded_cu_id_comb = 0;
for (i=0; i<NUMBER_CU; i = i+1) begin
if(~found_valid && anded_cam_out[i]) begin
found_valid = 1'b1;
encoded_cu_id_comb = i;
end
end
encoded_cu_found_valid_comb = found_valid;
end
endmodule // allocator
|
//Copyright (C) 1991-2003 Altera Corporation
//Any megafunction design, and related netlist (encrypted or decrypted),
//support information, device programming or simulation file, and any other
//associated documentation or information provided by Altera or a partner
//under Altera's Megafunction Partnership Program may be used only
//to program PLD devices (but not masked PLD devices) from Altera. Any
//other use of such megafunction design, netlist, support information,
//device programming or simulation file, or any other related documentation
//or information is prohibited for any other purpose, including, but not
//limited to modification, reverse engineering, de-compiling, or use with
//any other silicon devices, unless such use is explicitly licensed under
//a separate agreement with Altera or a megafunction partner. Title to the
//intellectual property, including patents, copyrights, trademarks, trade
//secrets, or maskworks, embodied in any such megafunction design, netlist,
//support information, device programming or simulation file, or any other
//related documentation or information provided by Altera or a megafunction
//partner, remains with Altera, the megafunction partner, or their respective
//licensors. No other licenses, including any licenses needed under any third
//party's intellectual property, are provided herein.
module add32 (
dataa,
datab,
result)/* synthesis synthesis_clearbox = 1 */;
input [7:0] dataa;
input [7:0] datab;
output [7:0] result;
endmodule
|
// =============================================================================
// COPYRIGHT NOTICE
// Copyright 2006 (c) Lattice Semiconductor Corporation
// ALL RIGHTS RESERVED
// This confidential and proprietary software may be used only as authorised by
// a licensing agreement from Lattice Semiconductor Corporation.
// The entire notice above must be reproduced on all authorized copies and
// copies may only be made to the extent permitted by a licensing agreement from
// Lattice Semiconductor Corporation.
//
// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada)
// 5555 NE Moore Court 408-826-6000 (other locations)
// Hillsboro, OR 97124 web : http://www.latticesemi.com/
// U.S.A email: [email protected]
// =============================================================================/
// FILE DETAILS
// Project : LatticeMico32
// File : lm32_jtag.v
// Title : JTAG interface
// Dependencies : lm32_include.v
// Version : 6.1.17
// : Initial Release
// Version : 7.0SP2, 3.0
// : No Change
// Version : 3.1
// : No Change
// =============================================================================
`include "lm32_include.v"
`ifdef CFG_JTAG_ENABLED
`define LM32_DP 3'b000
`define LM32_TX 3'b001
`define LM32_RX 3'b010
// LM32 Debug Protocol commands IDs
`define LM32_DP_RNG 3:0
`define LM32_DP_READ_MEMORY 4'b0001
`define LM32_DP_WRITE_MEMORY 4'b0010
`define LM32_DP_READ_SEQUENTIAL 4'b0011
`define LM32_DP_WRITE_SEQUENTIAL 4'b0100
`define LM32_DP_WRITE_CSR 4'b0101
`define LM32_DP_BREAK 4'b0110
`define LM32_DP_RESET 4'b0111
// States for FSM
`define LM32_JTAG_STATE_RNG 3:0
`define LM32_JTAG_STATE_READ_COMMAND 4'h0
`define LM32_JTAG_STATE_READ_BYTE_0 4'h1
`define LM32_JTAG_STATE_READ_BYTE_1 4'h2
`define LM32_JTAG_STATE_READ_BYTE_2 4'h3
`define LM32_JTAG_STATE_READ_BYTE_3 4'h4
`define LM32_JTAG_STATE_READ_BYTE_4 4'h5
`define LM32_JTAG_STATE_PROCESS_COMMAND 4'h6
`define LM32_JTAG_STATE_WAIT_FOR_MEMORY 4'h7
`define LM32_JTAG_STATE_WAIT_FOR_CSR 4'h8
/////////////////////////////////////////////////////
// Module interface
/////////////////////////////////////////////////////
module lm32_jtag (
// ----- Inputs -------
clk_i,
rst_i,
jtag_clk,
jtag_update,
jtag_reg_q,
jtag_reg_addr_q,
`ifdef CFG_JTAG_UART_ENABLED
csr,
csr_write_enable,
csr_write_data,
stall_x,
`endif
`ifdef CFG_HW_DEBUG_ENABLED
jtag_read_data,
jtag_access_complete,
`endif
`ifdef CFG_DEBUG_ENABLED
exception_q_w,
`endif
// ----- Outputs -------
`ifdef CFG_JTAG_UART_ENABLED
jtx_csr_read_data,
jrx_csr_read_data,
`endif
`ifdef CFG_HW_DEBUG_ENABLED
jtag_csr_write_enable,
jtag_csr_write_data,
jtag_csr,
jtag_read_enable,
jtag_write_enable,
jtag_write_data,
jtag_address,
`endif
`ifdef CFG_DEBUG_ENABLED
jtag_break,
jtag_reset,
`endif
jtag_reg_d,
jtag_reg_addr_d
);
parameter lat_family = `LATTICE_FAMILY;
/////////////////////////////////////////////////////
// Inputs
/////////////////////////////////////////////////////
input clk_i; // Clock
input rst_i; // Reset
input jtag_clk; // JTAG clock
input jtag_update; // JTAG data register has been updated
input [`LM32_BYTE_RNG] jtag_reg_q; // JTAG data register
input [2:0] jtag_reg_addr_q; // JTAG data register
`ifdef CFG_JTAG_UART_ENABLED
input [`LM32_CSR_RNG] csr; // CSR to write
input csr_write_enable; // CSR write enable
input [`LM32_WORD_RNG] csr_write_data; // Data to write to specified CSR
input stall_x; // Stall instruction in X stage
`endif
`ifdef CFG_HW_DEBUG_ENABLED
input [`LM32_BYTE_RNG] jtag_read_data; // Data read from requested address
input jtag_access_complete; // Memory access if complete
`endif
`ifdef CFG_DEBUG_ENABLED
input exception_q_w; // Indicates an exception has occured in W stage
`endif
/////////////////////////////////////////////////////
// Outputs
/////////////////////////////////////////////////////
`ifdef CFG_JTAG_UART_ENABLED
output [`LM32_WORD_RNG] jtx_csr_read_data; // Value of JTX CSR for rcsr instructions
wire [`LM32_WORD_RNG] jtx_csr_read_data;
output [`LM32_WORD_RNG] jrx_csr_read_data; // Value of JRX CSR for rcsr instructions
wire [`LM32_WORD_RNG] jrx_csr_read_data;
`endif
`ifdef CFG_HW_DEBUG_ENABLED
output jtag_csr_write_enable; // CSR write enable
reg jtag_csr_write_enable;
output [`LM32_WORD_RNG] jtag_csr_write_data; // Data to write to specified CSR
wire [`LM32_WORD_RNG] jtag_csr_write_data;
output [`LM32_CSR_RNG] jtag_csr; // CSR to write
wire [`LM32_CSR_RNG] jtag_csr;
output jtag_read_enable; // Memory read enable
reg jtag_read_enable;
output jtag_write_enable; // Memory write enable
reg jtag_write_enable;
output [`LM32_BYTE_RNG] jtag_write_data; // Data to write to specified address
wire [`LM32_BYTE_RNG] jtag_write_data;
output [`LM32_WORD_RNG] jtag_address; // Memory read/write address
wire [`LM32_WORD_RNG] jtag_address;
`endif
`ifdef CFG_DEBUG_ENABLED
output jtag_break; // Request to raise a breakpoint exception
reg jtag_break;
output jtag_reset; // Request to raise a reset exception
reg jtag_reset;
`endif
output [`LM32_BYTE_RNG] jtag_reg_d;
reg [`LM32_BYTE_RNG] jtag_reg_d;
output [2:0] jtag_reg_addr_d;
wire [2:0] jtag_reg_addr_d;
/////////////////////////////////////////////////////
// Internal nets and registers
/////////////////////////////////////////////////////
reg rx_toggle; // Clock-domain crossing registers
reg rx_toggle_r; // Registered version of rx_toggle
reg rx_toggle_r_r; // Registered version of rx_toggle_r
reg rx_toggle_r_r_r; // Registered version of rx_toggle_r_r
reg [`LM32_BYTE_RNG] rx_byte;
reg [2:0] rx_addr;
`ifdef CFG_JTAG_UART_ENABLED
reg [`LM32_BYTE_RNG] uart_tx_byte; // UART TX data
reg uart_tx_valid; // TX data is valid
reg [`LM32_BYTE_RNG] uart_rx_byte; // UART RX data
reg uart_rx_valid; // RX data is valid
`endif
reg [`LM32_DP_RNG] command; // The last received command
`ifdef CFG_HW_DEBUG_ENABLED
reg [`LM32_BYTE_RNG] jtag_byte_0; // Registers to hold command paramaters
reg [`LM32_BYTE_RNG] jtag_byte_1;
reg [`LM32_BYTE_RNG] jtag_byte_2;
reg [`LM32_BYTE_RNG] jtag_byte_3;
reg [`LM32_BYTE_RNG] jtag_byte_4;
reg processing; // Indicates if we're still processing a memory read/write
`endif
reg [`LM32_JTAG_STATE_RNG] state; // Current state of FSM
/////////////////////////////////////////////////////
// Combinational Logic
/////////////////////////////////////////////////////
`ifdef CFG_HW_DEBUG_ENABLED
assign jtag_csr_write_data = {jtag_byte_0, jtag_byte_1, jtag_byte_2, jtag_byte_3};
assign jtag_csr = jtag_byte_4[`LM32_CSR_RNG];
assign jtag_address = {jtag_byte_0, jtag_byte_1, jtag_byte_2, jtag_byte_3};
assign jtag_write_data = jtag_byte_4;
`endif
// Generate status flags for reading via the JTAG interface
`ifdef CFG_JTAG_UART_ENABLED
assign jtag_reg_addr_d[1:0] = {uart_rx_valid, uart_tx_valid};
`else
assign jtag_reg_addr_d[1:0] = 2'b00;
`endif
`ifdef CFG_HW_DEBUG_ENABLED
assign jtag_reg_addr_d[2] = processing;
`else
assign jtag_reg_addr_d[2] = 1'b0;
`endif
`ifdef CFG_JTAG_UART_ENABLED
assign jtx_csr_read_data = {{`LM32_WORD_WIDTH-9{1'b0}}, uart_tx_valid, 8'h00};
assign jrx_csr_read_data = {{`LM32_WORD_WIDTH-9{1'b0}}, uart_rx_valid, uart_rx_byte};
`endif
/////////////////////////////////////////////////////
// Sequential Logic
/////////////////////////////////////////////////////
// Toggle a flag when a JTAG write occurs
always @(negedge jtag_update `CFG_RESET_SENSITIVITY)
begin
if (rst_i == `TRUE)
rx_toggle <= 1'b0;
else
rx_toggle <= ~rx_toggle;
end
always @(*)
begin
rx_byte = jtag_reg_q;
rx_addr = jtag_reg_addr_q;
end
// Clock domain crossing from JTAG clock domain to CPU clock domain
always @(posedge clk_i `CFG_RESET_SENSITIVITY)
begin
if (rst_i == `TRUE)
begin
rx_toggle_r <= 1'b0;
rx_toggle_r_r <= 1'b0;
rx_toggle_r_r_r <= 1'b0;
end
else
begin
rx_toggle_r <= rx_toggle;
rx_toggle_r_r <= rx_toggle_r;
rx_toggle_r_r_r <= rx_toggle_r_r;
end
end
// LM32 debug protocol state machine
always @(posedge clk_i `CFG_RESET_SENSITIVITY)
begin
if (rst_i == `TRUE)
begin
state <= `LM32_JTAG_STATE_READ_COMMAND;
command <= 4'b0000;
jtag_reg_d <= 8'h00;
`ifdef CFG_HW_DEBUG_ENABLED
processing <= `FALSE;
jtag_csr_write_enable <= `FALSE;
jtag_read_enable <= `FALSE;
jtag_write_enable <= `FALSE;
`endif
`ifdef CFG_DEBUG_ENABLED
jtag_break <= `FALSE;
jtag_reset <= `FALSE;
`endif
`ifdef CFG_JTAG_UART_ENABLED
uart_tx_byte <= 8'h00;
uart_tx_valid <= `FALSE;
uart_rx_byte <= 8'h00;
uart_rx_valid <= `FALSE;
`endif
end
else
begin
`ifdef CFG_JTAG_UART_ENABLED
if ((csr_write_enable == `TRUE) && (stall_x == `FALSE))
begin
case (csr)
`LM32_CSR_JTX:
begin
// Set flag indicating data is available
uart_tx_byte <= csr_write_data[`LM32_BYTE_0_RNG];
uart_tx_valid <= `TRUE;
end
`LM32_CSR_JRX:
begin
// Clear flag indidicating data has been received
uart_rx_valid <= `FALSE;
end
endcase
end
`endif
`ifdef CFG_DEBUG_ENABLED
// When an exception has occured, clear the requests
if (exception_q_w == `TRUE)
begin
jtag_break <= `FALSE;
jtag_reset <= `FALSE;
end
`endif
case (state)
`LM32_JTAG_STATE_READ_COMMAND:
begin
// Wait for rx register to toggle which indicates new data is available
if (rx_toggle_r_r != rx_toggle_r_r_r)
begin
command <= rx_byte[7:4];
case (rx_addr)
`ifdef CFG_DEBUG_ENABLED
`LM32_DP:
begin
case (rx_byte[7:4])
`ifdef CFG_HW_DEBUG_ENABLED
`LM32_DP_READ_MEMORY:
state <= `LM32_JTAG_STATE_READ_BYTE_0;
`LM32_DP_READ_SEQUENTIAL:
begin
{jtag_byte_2, jtag_byte_3} <= {jtag_byte_2, jtag_byte_3} + 1'b1;
state <= `LM32_JTAG_STATE_PROCESS_COMMAND;
end
`LM32_DP_WRITE_MEMORY:
state <= `LM32_JTAG_STATE_READ_BYTE_0;
`LM32_DP_WRITE_SEQUENTIAL:
begin
{jtag_byte_2, jtag_byte_3} <= {jtag_byte_2, jtag_byte_3} + 1'b1;
state <= 5;
end
`LM32_DP_WRITE_CSR:
state <= `LM32_JTAG_STATE_READ_BYTE_0;
`endif
`LM32_DP_BREAK:
begin
`ifdef CFG_JTAG_UART_ENABLED
uart_rx_valid <= `FALSE;
uart_tx_valid <= `FALSE;
`endif
jtag_break <= `TRUE;
end
`LM32_DP_RESET:
begin
`ifdef CFG_JTAG_UART_ENABLED
uart_rx_valid <= `FALSE;
uart_tx_valid <= `FALSE;
`endif
jtag_reset <= `TRUE;
end
endcase
end
`endif
`ifdef CFG_JTAG_UART_ENABLED
`LM32_TX:
begin
uart_rx_byte <= rx_byte;
uart_rx_valid <= `TRUE;
end
`LM32_RX:
begin
jtag_reg_d <= uart_tx_byte;
uart_tx_valid <= `FALSE;
end
`endif
default:
;
endcase
end
end
`ifdef CFG_HW_DEBUG_ENABLED
`LM32_JTAG_STATE_READ_BYTE_0:
begin
if (rx_toggle_r_r != rx_toggle_r_r_r)
begin
jtag_byte_0 <= rx_byte;
state <= `LM32_JTAG_STATE_READ_BYTE_1;
end
end
`LM32_JTAG_STATE_READ_BYTE_1:
begin
if (rx_toggle_r_r != rx_toggle_r_r_r)
begin
jtag_byte_1 <= rx_byte;
state <= `LM32_JTAG_STATE_READ_BYTE_2;
end
end
`LM32_JTAG_STATE_READ_BYTE_2:
begin
if (rx_toggle_r_r != rx_toggle_r_r_r)
begin
jtag_byte_2 <= rx_byte;
state <= `LM32_JTAG_STATE_READ_BYTE_3;
end
end
`LM32_JTAG_STATE_READ_BYTE_3:
begin
if (rx_toggle_r_r != rx_toggle_r_r_r)
begin
jtag_byte_3 <= rx_byte;
if (command == `LM32_DP_READ_MEMORY)
state <= `LM32_JTAG_STATE_PROCESS_COMMAND;
else
state <= `LM32_JTAG_STATE_READ_BYTE_4;
end
end
`LM32_JTAG_STATE_READ_BYTE_4:
begin
if (rx_toggle_r_r != rx_toggle_r_r_r)
begin
jtag_byte_4 <= rx_byte;
state <= `LM32_JTAG_STATE_PROCESS_COMMAND;
end
end
`LM32_JTAG_STATE_PROCESS_COMMAND:
begin
case (command)
`LM32_DP_READ_MEMORY,
`LM32_DP_READ_SEQUENTIAL:
begin
jtag_read_enable <= `TRUE;
processing <= `TRUE;
state <= `LM32_JTAG_STATE_WAIT_FOR_MEMORY;
end
`LM32_DP_WRITE_MEMORY,
`LM32_DP_WRITE_SEQUENTIAL:
begin
jtag_write_enable <= `TRUE;
processing <= `TRUE;
state <= `LM32_JTAG_STATE_WAIT_FOR_MEMORY;
end
`LM32_DP_WRITE_CSR:
begin
jtag_csr_write_enable <= `TRUE;
processing <= `TRUE;
state <= `LM32_JTAG_STATE_WAIT_FOR_CSR;
end
endcase
end
`LM32_JTAG_STATE_WAIT_FOR_MEMORY:
begin
if (jtag_access_complete == `TRUE)
begin
jtag_read_enable <= `FALSE;
jtag_reg_d <= jtag_read_data;
jtag_write_enable <= `FALSE;
processing <= `FALSE;
state <= `LM32_JTAG_STATE_READ_COMMAND;
end
end
`LM32_JTAG_STATE_WAIT_FOR_CSR:
begin
jtag_csr_write_enable <= `FALSE;
processing <= `FALSE;
state <= `LM32_JTAG_STATE_READ_COMMAND;
end
`endif
endcase
end
end
endmodule
`endif
|
module memory_tb();
reg clk;
reg rst;
reg[3:0] rd_en, wr_en;
reg[6:0] input_tag;
reg[63:0] wr_mask;
reg[2047:0] addresses;
reg[8191:0] wr_data;
wire ack;
wire[6:0] output_tag;
wire[2047:0] tracemon_addr;
wire[8191:0] rd_data, tracemon_store_data;
memory mem(
rd_en,
wr_en,
addresses,
wr_data,
input_tag,
wr_mask,
rd_data,
output_tag,
ack,
tracemon_addr,
tracemon_store_data,
clk,
rst
);
initial begin
clk = 0;
while (1) begin
#2;
clk = ~clk;
end
end
initial begin
rst = 1;
rd_en = 4'b0000;
wr_en = 4'b0000;
#11;
rst = 0;
#20
input_tag = 1;
addresses = 2048'h00000034_00000024_00000014_00000004;
wr_data = 8192'h00000001_00000002_00000003_00000004_00000005_00000006_00000007_00000008;
wr_en = 4'b0101;
wr_mask = 7;
#4
wr_en = 4'b0000;
#20;
input_tag = 2;
addresses = 2048'h00000034_00000024_00000014_00000004;
rd_en = 4'b0101;
wr_mask = 1;
#4
rd_en = 0;
#10
$finish;
end
always @ (posedge clk) begin
if (!rst) begin
$display ("Time= %g : Ack= %b : Output_tag= %b", $time, ack, output_tag);
if(ack) begin
$display ("Addr: %h Read Data: %h", addresses[31:0], rd_data[127:0]);
$display ("Addr: %h Read Data: %h", addresses[63:32], rd_data[255:128]);
$display ("Addr: %h Read Data: %h", addresses[95:64], rd_data[383:256]);
$display ("Addr: %h Read Data: %h", addresses[127:96], rd_data[511:384]);
end
end
end
endmodule
|
//
// Copyright (c) 1999 Steven Wilson ([email protected])
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW - Validate fork template 2
module main ;
reg [3:0] value1,value2 ;
reg [3:0] ret1,ret2 ;
reg error;
always @(value1 or value2)
begin
fork
#10 ret1 = value1;
@(ret1) #12 ret2 = value2;
join
end
initial
begin
error = 0;
#1;
value1 = 1;
value2 = 2;
ret1 = 0;
ret2 = 0;
#12;
if(ret1 !== 1)
begin
$display("FAILED - force3.19B first statement didn't execute(1)");
error = 1;
end
if(ret2 !== 0)
begin
$display("FAILED - force3.19B second stmt executed? is %d sb %d",
1'b0,ret2);
error = 1;
end
#10;
if(ret1 !== 1)
begin
$display("FAILED -fork3.19B First statement problem sb 1, is %d",ret1);
error = 1;
end
if(ret2 !== 2)
begin
$display("FAILED -fork3.19B First statement problem sb 2, is %d",ret1);
error = 1;
end
if(error == 0)
$display("PASSED");
end
endmodule
|
//////////////////////////////////////////////////////////////////////
//// ////
//// spi_top.v ////
//// ////
//// This file is part of the SPI IP core project ////
//// http://www.opencores.org/projects/spi/ ////
//// ////
//// Author(s): ////
//// - Simon Srot ([email protected]) ////
//// ////
//// All additional information is avaliable in the Readme.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2002 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
// Copyright (C) 2005 Rice University - Rice Open License Fill
`include "spi_defines.v"
module spi_top
(
// OPB signals
opb_clk_i, opb_rst_i,
// SPI registers
reg_ctrl, reg_ss, reg_divider, reg_tx, ctrlwrite, busval, go,
// SPI signals
ss_pad_o, sclk_pad_o, mosi_pad_o
);
parameter Tp = 1;
// OPB signals
input opb_clk_i; // master clock input
input opb_rst_i; // synchronous active high reset
// SPI registers
input [13:0] reg_ctrl;
input [7:0] reg_ss;
input reg_divider;
input [17:0] reg_tx;
input ctrlwrite;
input busval;
output go;
// SPI signals
output [`SPI_SS_NB-1:0] ss_pad_o; // slave select
output sclk_pad_o; // serial clock
output mosi_pad_o; // master out slave in
// Internal signals
wire [`SPI_MAX_CHAR-1:0] rx; // Rx register
wire rx_negedge; // miso is sampled on negative edge
wire tx_negedge; // mosi is driven on negative edge
wire [`SPI_CHAR_LEN_BITS-1:0] char_len; // char len
//wire go; // go
wire lsb; // lsb first on line
wire ie; // interrupt enable
wire ass; // automatic slave select
wire spi_divider_sel; // divider register select
wire spi_ctrl_sel; // ctrl register select
wire [3:0] spi_tx_sel; // tx_l register select
wire spi_ss_sel; // ss register select
wire tip; // transfer in progress
wire pos_edge; // recognize posedge of sclk
wire neg_edge; // recognize negedge of sclk
wire last_bit; // marks last character bit
reg ctrlbitgo;
assign rx_negedge = reg_ctrl[`SPI_CTRL_RX_NEGEDGE];
assign tx_negedge = reg_ctrl[`SPI_CTRL_TX_NEGEDGE];
assign go = ctrlbitgo;
assign char_len = reg_ctrl[`SPI_CTRL_CHAR_LEN];
assign lsb = reg_ctrl[`SPI_CTRL_LSB];
assign ie = reg_ctrl[`SPI_CTRL_IE];
assign ass = reg_ctrl[`SPI_CTRL_ASS];
always @(posedge opb_clk_i or posedge opb_rst_i)
begin
if (opb_rst_i)
ctrlbitgo <= #Tp 1'b0;
else if(ctrlwrite && !tip)
ctrlbitgo <= #Tp busval;
else if(tip && last_bit && pos_edge)
ctrlbitgo <= #Tp 1'b0;
end
assign ss_pad_o = ~((reg_ss & {`SPI_SS_NB{tip & ass}}) | (reg_ss & {`SPI_SS_NB{!ass}}));
spi_clgen clgen (.clk_in(opb_clk_i), .rst(opb_rst_i), .go(go), .enable(tip), .last_clk(last_bit),
.divider(reg_divider), .clk_out(sclk_pad_o), .pos_edge(pos_edge),
.neg_edge(neg_edge));
spi_shift shift (.clk(opb_clk_i), .rst(opb_rst_i), .len(char_len[`SPI_CHAR_LEN_BITS-1:0]),
.lsb(lsb), .go(go), .pos_edge(pos_edge), .neg_edge(neg_edge),
.rx_negedge(rx_negedge), .tx_negedge(tx_negedge),
.tip(tip), .last(last_bit),
.p_in(reg_tx), .p_out(rx),
.s_clk(sclk_pad_o), .s_out(mosi_pad_o));
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2010 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
rst_sync_l, rst_both_l, rst_async_l, d, clk
);
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
input clk; // To sub1 of sub1.v, ...
input d; // To sub1 of sub1.v, ...
input rst_async_l; // To sub2 of sub2.v
input rst_both_l; // To sub1 of sub1.v, ...
input rst_sync_l; // To sub1 of sub1.v
// End of automatics
sub1 sub1 (/*AUTOINST*/
// Inputs
.clk (clk),
.rst_both_l (rst_both_l),
.rst_sync_l (rst_sync_l),
.d (d));
sub2 sub2 (/*AUTOINST*/
// Inputs
.clk (clk),
.rst_both_l (rst_both_l),
.rst_async_l (rst_async_l),
.d (d));
endmodule
module sub1 (/*AUTOARG*/
// Inputs
clk, rst_both_l, rst_sync_l, d
);
input clk;
input rst_both_l;
input rst_sync_l;
//input rst_async_l;
input d;
reg q1;
reg q2;
always @(posedge clk) begin
if (~rst_sync_l) begin
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
q1 <= 1'h0;
// End of automatics
end else begin
q1 <= d;
end
end
always @(posedge clk) begin
q2 <= (~rst_both_l) ? 1'b0 : d;
if (0 && q1 && q2) ;
end
endmodule
module sub2 (/*AUTOARG*/
// Inputs
clk, rst_both_l, rst_async_l, d
);
input clk;
input rst_both_l;
//input rst_sync_l;
input rst_async_l;
input d;
reg q1;
reg q2;
reg q3;
always @(posedge clk or negedge rst_async_l) begin
if (~rst_async_l) begin
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
q1 <= 1'h0;
// End of automatics
end else begin
q1 <= d;
end
end
always @(posedge clk or negedge rst_both_l) begin
q2 <= (~rst_both_l) ? 1'b0 : d;
end
// Make there be more async uses than sync uses
always @(posedge clk or negedge rst_both_l) begin
q3 <= (~rst_both_l) ? 1'b0 : d;
if (0 && q1 && q2 && q3) ;
end
endmodule
|
`timescale 1ns / 1ps
module ScanCodeModule(Clk,Reset, ClkKB, DataKB,NewScanCode, ScanCode);
input Clk,Reset,ClkKB, DataKB;
wire NewDataKB;
output NewScanCode;
output [7:0] ScanCode;
wire Load, New,Borrar,EndTras,ParityCoherente;
reg ClkKB_syn, DataKB_syn ;
always @(negedge Clk) begin
ClkKB_syn <= ClkKB;
DataKB_syn <= DataKB;
end
//module module Muestrear(ClkKB, NewDataKB, Clk , Reset);
Muestrear Muestrear (.Clk(Clk), .Reset(Reset),.ClkKB(ClkKB_syn), .NewDataKB(NewDataKB) );
//module ScanCodeControl(NewDataKB,Load, New , Borrar, EndTras, ParityCoherente, Clk , Reset);
ScanCodeControl Control (.Clk(Clk), .Reset(Reset),.NewDataKB(NewDataKB), .Load(Load) , .New(New), .Borrar(Borrar), .EndTras(EndTras), .ParityCoherente(ParityCoherente));
//module ModuloDato(Clk, Reset, DataKB,Load, New,Borrar,EndTras,ParityCoherente ,NewScanCode, ScanCode)
ModuloDato Dato (.Clk(Clk), .Reset(Reset), .DataKB(DataKB_syn), .NewScanCode(NewScanCode), .ScanCode(ScanCode), .Load(Load), .Borrar(Borrar), .EndTras(EndTras), .ParityCoherente(ParityCoherente),.New(New));
endmodule
|
Require Import List.
Require Import Ascii.
Require Import Omega.
Require Import Stream.
Require Import Charset.
Import INSTREAM.
Set Implicit Arguments.
Section CHARSET.
Variable charset : Charset.
Definition char := char charset.
(* We describe the syntax of grammars using Adam's approach from ltamer *)
Section VARS.
Variable var : Set -> Type.
Inductive term: Set -> Type :=
| GVar : forall t:Set, var t -> term t
| GEpsilon : forall t:Set, t -> term t
| GSatisfy : (char -> bool) -> term char
| GCat : forall (t1 t2:Set), term t1 -> term t2 -> term (t1 * t2)
| GAlt : forall t, term t -> term t -> term t
| GTry : forall t, term t -> term t
| GRec : forall t:Set, (var t -> term t) -> term t
| GMap : forall (t1 t2:Set), (t1 -> t2) -> term t1 -> term t2.
(* A relational definition of substitution for terms -- used in the definition
* of the semantics below, in particular for the rec case *)
Inductive Subst :
forall (t1 t2:Set), (var t1->term t2)->(term t1)->(term t2)->Type :=
| SEpsilon : forall (t1 t2:Set) (v:t2) (e:term t1),
Subst (fun _ => GEpsilon v) e (GEpsilon v)
| SSatisfy : forall t1 (f:char->bool) (e:term t1),
Subst (fun _ => GSatisfy f) e (GSatisfy f)
| SCat :
forall t1 t2 t3 (f1:var t1 -> term t2) (f2:var t1 -> term t3) (e:term t1)
(e1:term t2)(e2:term t3),
Subst f1 e e1 -> Subst f2 e e2 ->
Subst (fun v => GCat (f1 v) (f2 v)) e (GCat e1 e2)
| SAlt :
forall t1 t2 (f1 f2:var t1 -> term t2) (e:term t1)(e1 e2:term t2),
Subst f1 e e1 -> Subst f2 e e2 ->
Subst (fun v => GAlt (f1 v) (f2 v)) e (GAlt e1 e2)
| SMap :
forall (t1 t2 t3:Set)
(f:var t1 -> term t2) (e:term t1) (g:t2->t3) (e1:term t2),
Subst f e e1 ->
Subst (fun v => GMap g (f v)) e (GMap g e1)
| STry :
forall t1 t2 (f1:var t1 -> term t2) (e : term t1) (e1:term t2),
Subst f1 e e1 -> Subst (fun v => GTry (f1 v)) e (GTry e1)
| SVarEq :
forall t (e:term t), Subst (@GVar t) e e
| SVarNeq :
forall t1 t2 (v:var t2) (e:term t1), Subst (fun _ => GVar v) e (GVar v)
| SRec :
forall t1 t2 (f1:var t1->var t2->term t2) (f2:var t2->term t2)(e:term t1),
(forall v', Subst (fun v => f1 v v') e (f2 v')) ->
Subst (fun v => GRec (f1 v)) e (GRec f2).
End VARS.
Definition Term t := forall V, term V t.
Implicit Arguments GVar [var t].
Implicit Arguments GEpsilon [var t].
Implicit Arguments GSatisfy [var].
Implicit Arguments GCat [var t1 t2].
Implicit Arguments GAlt [var t].
Implicit Arguments GTry [var t].
Implicit Arguments GRec [var t].
Implicit Arguments GMap [var t1 t2].
Fixpoint flatten(V:Set->Type)(t:Set)(e: term (term V) t) {struct e} : term V t :=
match e in (term _ t) return (term V t) with
| GVar _ v => v
| GEpsilon t v => GEpsilon v
| GSatisfy f => GSatisfy f
| GCat t1 t2 e1 e2 => GCat (flatten e1) (flatten e2)
| GAlt t e1 e2 => GAlt (flatten e1) (flatten e2)
| GMap t1 t2 f e => GMap f (flatten e)
| GTry t e => GTry (flatten e)
| GRec t f => GRec (fun (v:V t) => flatten (f (GVar v)))
end.
Definition unroll(t:Set)(f:forall V, V t -> term V t) : Term t :=
fun V => flatten (f (term V) (GRec (f V))).
Definition empvar := (fun _:Set => Empty_set).
(* It would be nice if we could prove the following axiom so that the definition
* of Gfix was simpler:
Axiom Unroll : forall (t:Set)(f:forall var, var t -> term var t),
Subst (f empvar) (GRec (f empvar)) (unroll f empvar).
*)
Inductive consumed_t : Set := Consumed | NotConsumed.
Inductive reply_t(a:Set) : Set :=
| Okay : consumed_t -> a -> list char -> reply_t a
| Error : consumed_t -> reply_t a.
Implicit Arguments Error [a].
Definition join_cons (nc1 nc2 : consumed_t) : consumed_t :=
match (nc1, nc2) with
| (Consumed, _) => Consumed
| (_, Consumed) => Consumed
| (_, _) => NotConsumed
end.
(* We give meaning to grammars here, following the style of Parsec combinators.
* In particular, note that we only try the second grammar of an alternation when
* the first one does not consume input. The presentation here is slightly di fferent
* from Parsec in that (a) we don't worry about space leaks since this is intended
* for specification only, and (b) instead of representing concatenation with a
* bind-like construct, we simply return a pair of the results. We have a separate
* operation GMap that allows us to transform a t1 grammar to a t2 grammar. The
* intention here is that grammars should use a minimum of meta-level stuff in
* revealing their structure, so that we can potentially analyze and transform them.
*)
(* What I'm doing here is defining a denotational semantics that maps grammar terms
* down to a simpler language with a monadic structure. Then we give an operational
* semantics to the monadic structure. Note that I've instantiated the var in the
* phoas so that it always yields an empty set. This ensures that the term does not
* have a free variable. *)
Inductive M: Set -> Type :=
| MReturn : forall t, reply_t t -> M t
| MBind : forall t1 t2, M t1 -> (reply_t t1 -> M t2) -> M t2
| MFix : forall t (f:empvar t -> term empvar t), list char -> M t.
Notation "'Return' x" := (MReturn x) (at level 75) : gdenote_scope.
Notation "x <- c1 ; c2" := (MBind c1 (fun x => c2))
(right associativity, at level 84, c1 at next level) : gdenote_scope.
Definition wfCoerce (t:Set)(v:empvar t) : M t := match v with end.
Open Local Scope gdenote_scope.
(* here we map a term e to a computation over lists of characters -- this is
* essentially the same as with Parsec-style combinators, though I've chosen
* slightly different combinators that are closer to arrows than the monadic
* interpretation. *)
Fixpoint denote(t:Set)(e:term empvar t)(s:list char) {struct e} : M t :=
match e in term _ t return M t with
| GVar _ v => wfCoerce v
| GEpsilon _ x => Return Okay NotConsumed x s
| GSatisfy test =>
Return match s with
| c :: cs => if (test c) then Okay Consumed c cs else
Error NotConsumed
| nil => Error NotConsumed
end
| GMap t1 t2 f e =>
r <- denote e s ;
Return match r with
| Okay nc v s2 => Okay nc (f v) s2
| Error nc => Error nc
end
| GTry t e =>
r <- denote e s ;
Return match r with
| Error Consumed => Error NotConsumed
| Okay Consumed v s2 => Okay NotConsumed v s2
| _ => r
end
| GCat t1 t2 e1 e2 =>
r1 <- denote e1 s ;
match r1 with
| Error nc => Return Error nc
| Okay nc1 v1 s1 =>
r2 <- denote e2 s1 ;
Return match r2 with
| Error nc2 => Error (join_cons nc1 nc2)
| Okay nc2 v2 s2 => Okay (join_cons nc1 nc2) (v1,v2) s2
end
end
| GAlt t e1 e2 =>
r1 <- denote e1 s ;
match r1 with
| Error Consumed => Return Error Consumed
| Error NotConsumed => denote e2 s
| Okay NotConsumed v s2 =>
r2 <- denote e2 s ;
Return match r2 with
| Error NotConsumed => Okay NotConsumed v s2
| Okay NotConsumed _ _ => Okay NotConsumed v s2
| r2 => r2
end
| Okay Consumed v s2 => Return Okay Consumed v s2
end
| GRec t f => MFix f s
end.
(* We now give an operational semantics to the monadic terms generated by the
* denotation function. Note that in essence, we just delay unrolling the
* fix operator. *)
Inductive evals : forall t, M t -> reply_t t -> Prop :=
| eMReturn : forall t (r:reply_t t), evals (MReturn r) r
| eMBind : forall t1 t2 (c:M t1) (r1:reply_t t1) (f:reply_t t1 -> M t2) r2,
evals c r1 -> evals (f r1) r2 -> evals (MBind c f) r2
| eMFix :
forall t (f:empvar t -> term empvar t) (s:list char) (e:term empvar t) (r:reply_t t),
Subst f (GRec f) e -> evals (denote e s) r -> evals (MFix f s) r.
(* Then we say that a term t parses string s yielding result r if the following
* if evaluating the denotation of e, when applied to s yields r. *)
Definition parses(t:Set)(e:Term t)(s:list char)(r:reply_t t) :=
evals (denote (e empvar) s) r.
Inductive parse_reply_t(t:Set) : Set :=
| OKAY : consumed_t -> nat -> t -> parse_reply_t t
| ERROR : consumed_t -> list ascii -> parse_reply_t t.
Fixpoint nthtail(A:Type)(cs:list A)(n:nat) {struct n} : list A :=
match (n,cs) with
| (0,cs) => cs
| (S n, c::cs) => nthtail cs n
| (S n, nil) => nil
end.
Require Import Ynot.
Definition okay(t:Set)(n: [nat])(i:instream_t char)(e:Term t)(c:consumed_t)(m:nat)(v:t) :=
(n ~~ let elts := stream_elts i in
elts ~~ [parses e (nthtail elts n) (Okay c v (nthtail elts (m+n)))])%hprop.
Definition okaystr(t:Set)(n:[nat])(i:instream_t char)(e:Term t)(c:consumed_t)(m:nat)(v:t) :=
(okay n i e c m v * (n ~~ rep i (m+n)))%hprop.
Definition error(t:Set)(n:[nat])(i:instream_t char)(e:Term t)(c:consumed_t) :=
(n ~~ let elts := stream_elts i in
elts ~~ [parses e (nthtail elts n) (Error c)])%hprop.
Definition errorstr(t:Set)(n:[nat])(i:instream_t char)(e:Term t)(c:consumed_t) :=
(error n i e c * (Exists m :@ nat, rep i m))%hprop.
Definition ans_correct(t:Set)(n:[nat])(i:instream_t char)(e:Term t)(ans:parse_reply_t t) :=
match ans with
| OKAY c m v => okay n i e c m v
| ERROR c _ => error n i e c
end.
Definition ans_str_correct(t:Set)(n:[nat])(i:instream_t char)(e:Term t)(ans:parse_reply_t t) :=
match ans with
| OKAY c m v => okaystr n i e c m v
| ERROR c _ => errorstr n i e c
end.
Definition parser_t(t:Set)(e:Term t) :=
forall (ins:instream_t char)(n:[nat]), STsep (n ~~ rep ins n) (ans_str_correct n ins e).
Implicit Arguments parser_t [t].
Open Local Scope stsep_scope.
Lemma EmpImpInj(P:Prop) :
P -> __ ==> [P].
Proof.
intros. sep fail auto.
Qed.
Lemma NthErrorNoneNthTail(A:Type)(i:nat) : forall (vs:list A),
nth_error vs i = None -> nthtail vs i = nil.
Proof.
induction i ; destruct vs ; auto ; simpl ; intros. unfold value in H. congruence.
apply IHi. auto.
Qed.
Lemma NthErrorSomeNthTail(A:Type)(i:nat) : forall (vs:list A)(v:A),
nth_error vs i = Some v ->
exists vs1, exists vs2, vs = vs1 ++ v::vs2 /\ nthtail vs i = v::vs2.
Proof.
induction i ; destruct vs ; auto ; simpl ; intros. unfold Specif.error in H. congruence.
unfold value in H. inversion H. subst. exists (nil(A:=A)). simpl. eauto.
unfold Specif.error in H. congruence. pose (IHi _ _ H). destruct e as [vs1 [vs2 [H1 H2]]].
exists (a::vs1). exists vs2. split. rewrite H1. simpl. auto. auto.
Qed.
Lemma NthTailSucc(A:Type)(i:nat) : forall (vs vs2:list A)(v:A),
nthtail vs i = v::vs2 -> nthtail vs (S i) = vs2.
Proof.
induction i ; simpl ; intros. rewrite H. auto. destruct vs. congruence.
pose (IHi _ _ _ H). apply e.
Qed.
Lemma PlusAssoc(n m p:nat) : n + (m + p) = n + m + p. intros ; omega.
Qed.
Ltac mysep :=
match goal with
| [ |- (__ ==> [ _ ])%hprop ] => apply EmpImpInj
| [ |- evals (MReturn ?r) ?r ] => constructor
| [ |- evals (MBind _ _) _] => econstructor
| [ |- context[?n + (?m + ?p)]] => rewrite (PlusAssoc n m p)
| [ |- context[if (?f ?c) then _ else _] ] =>
let H := fresh "H" in
assert (H: f c = true \/ f c = false) ; [ destruct (f c) ; tauto |
destruct H ; [ rewrite H ; simpl | rewrite H ; simpl ]]
| _ => auto
end.
Definition lower (P : char -> Prop) (v : forall c : char, {P c} + {~P c}) : char -> bool := fun c => if v c then true else false.
Definition gsatisfy(f:char -> bool) vars := GSatisfy (var:=vars) f.
Definition gclass(cl:CharClass charset) vars := GSatisfy (var:=vars) (@lower (DenoteClass cl) (In_CharClass_dec cl)).
Definition gepsilon(t:Set)(v:t) vars := GEpsilon (var:=vars) v.
Definition galt(t:Set)(e1 e2:Term t) vars := GAlt (e1 vars) (e2 vars).
Definition gmap(t1 t2:Set)(f:t1 -> t2)(e:Term t1) vars := GMap f (e vars).
Definition gcat(t1 t2:Set)(e1:Term t1)(e2:Term t2) vars := GCat (e1 vars) (e2 vars).
Definition gtry(t:Set)(e:Term t) vars := GTry (e vars).
Definition grec(t:Set)(f:forall (var:Set->Type), var t -> term var t)(var:Set -> Type) := GRec (f var).
Ltac myunfold := unfold ans_str_correct, ans_correct, okaystr, okay, errorstr, error,
parses, gsatisfy, gepsilon, galt, gmap, gcat, gtry, grec.
Ltac psimp := (myunfold ; sep fail auto ; mysep ; simpl ; eauto).
Ltac rsimp := psimp ;
match goal with
| [ |- context[match ?a with | OKAY c m v => _ | ERROR c _ => _ end] ] => destruct a
| [ |- context[match ?c with | Consumed => _ | NotConsumed => _ end] ] => destruct c
| _ => idtac
end.
Lemma NthError(x:list char)(n:nat) :
(nth_error x n = None \/ exists c, nth_error x n = Some c).
Proof. intros. destruct (nth_error x n). right. eauto. left. eauto.
Qed.
Lemma EvalsMReturn(t:Set)(r1 r2:reply_t t) : r1 = r2 -> evals (MReturn r1) r2.
Proof. intros. rewrite <- H. constructor. Qed.
Open Scope char_scope.
Definition bad_character := "b"::"a"::"d"::" "::"c"::"h"::"a"::"r"::"a"::"c"::"t"::"e"::"r"::nil.
(* the parser for a single character *)
Definition satisfy(f:char -> bool) : parser_t (gsatisfy f).
intros instream n.
refine (copt <- next instream n ;
Return (match copt with
| None => ERROR char NotConsumed bad_character
| Some c => if f c then OKAY Consumed 1 c
else ERROR char NotConsumed bad_character
end) <@>
match copt with
| None => errorstr n instream (gsatisfy f) NotConsumed
| Some c => if f c then okaystr n instream (gsatisfy f) Consumed 1 c
else errorstr n instream (gsatisfy f) NotConsumed
end @> _);
psimp ; solve [ sep fail auto |
match goal with
[ |- _ ==> match nth_error ?x ?n with | Some c => _ | None => _ end] =>
let H := fresh in pose (H := NthError x n) ; destruct H ; [ rewrite H ; psimp ;
rewrite (NthErrorNoneNthTail _ _ H) ; psimp | destruct H ; rewrite H ; psimp ; psimp ;
let H1 := fresh in let v1 := fresh in let v2 := fresh in
let H2 := fresh in let H3 := fresh in
pose (H1 := NthErrorSomeNthTail _ _ H) ; destruct H1 as [v1 [v2 [H1 H2]]] ;
rewrite H2 ; psimp ; pose (H3 := (NthTailSucc _ _ H2)) ;
simpl in H3 ; eapply EvalsMReturn ; congruence]
| [ |- match ?copt with | Some c => _ | None => _ end ==> _] => destruct copt ;
repeat psimp
end ].
Qed.
Definition class(cl:CharClass charset) : parser_t (gsatisfy (@lower (DenoteClass cl) (In_CharClass_dec cl))) := satisfy (@lower (DenoteClass cl) (In_CharClass_dec cl)).
(* the parser for the empty string *)
Definition epsilon(t:Set)(v:t) : parser_t (gepsilon v).
intros instream n.
refine ({{Return (OKAY NotConsumed 0 v) <@> (n ~~ rep instream n)}}) ;
repeat psimp.
Qed.
(* left-biased alternation -- need to fix error message propagation here *)
Definition alt(t:Set)(e1 e2:Term t)(p1:parser_t e1)(p2:parser_t e2) : parser_t (galt e1 e2).
intros instream n. unfold galt.
refine (n0 <- position instream n @> (fun n0 => n ~~ rep instream n * [n0=n])%hprop ;
ans1 <- p1 instream n <@> (n ~~ [n0=n])%hprop @>
(fun ans1 => ans_str_correct n instream e1 ans1 * (n ~~ [n0=n]))%hprop ;
let frame := fun ans => ((n ~~ [n0=n]) * ans_correct n instream e1 ans)%hprop in
match ans1 as ans1'
return STsep (ans_str_correct n instream e1 ans1' * (n ~~ [n0=n]))%hprop
(ans_str_correct n instream (galt e1 e2))
with
| ERROR NotConsumed msg1 =>
seek instream n0 <@> frame (ERROR t NotConsumed msg1) ;;
p2 instream n <@> frame (ERROR t NotConsumed msg1) @> _
| OKAY NotConsumed m1 v1 =>
seek instream n0 <@> frame (OKAY NotConsumed m1 v1) ;;
ans2 <- p2 instream n <@> frame (OKAY NotConsumed m1 v1) ;
match ans2 as ans2'
return STsep (frame (OKAY NotConsumed m1 v1) *
ans_str_correct n instream e2 ans2')
(ans_str_correct n instream (galt e1 e2))
with
| ERROR NotConsumed msg2 =>
(* interestingly, I forgot to do the seek here and in the next
case and then got stuck doing the proof! *)
seek instream (m1 + n0) <@>
frame (OKAY NotConsumed m1 v1) *
ans_correct n instream e2 (ERROR t NotConsumed msg2) ;;
Return OKAY NotConsumed m1 v1 <@>
frame (OKAY NotConsumed m1 v1) *
rep instream (m1 + n0) *
ans_correct n instream e2 (ERROR t NotConsumed msg2) @> _
| OKAY NotConsumed m2 v2 =>
seek instream (m1 + n0) <@>
frame (OKAY NotConsumed m1 v1) *
ans_correct n instream e2 (OKAY NotConsumed m2 v2) ;;
Return OKAY NotConsumed m1 v1 <@>
frame (OKAY NotConsumed m1 v1) *
rep instream (m1 + n0) *
ans_correct n instream e2 (OKAY NotConsumed m2 v2) @> _
| ans =>
{{Return ans <@>
frame (OKAY NotConsumed m1 v1) * ans_str_correct n instream e2 ans}}
end
| ans =>
{{Return ans <@>
((n ~~ [n0=n]) * ans_str_correct n instream e1 ans)%hprop}}
end) ;
(try unfold frame) ; repeat rsimp.
Qed.
(* the parser for (gmap f e) given f and a parser p for e *)
Definition map(t1 t2:Set)(f:t1->t2)(e:Term t1)(p:parser_t e) : parser_t (gmap f e).
intros instream n.
refine (ans <- p instream n;
Return (match ans with
| OKAY c m v => OKAY c m (f v)
| ERROR c msg => ERROR t2 c msg
end) <@> ans_str_correct n instream e ans @> _) ; psimp.
destruct ans ; repeat psimp.
Qed.
(* parser for concatenation *)
Definition cat(t1 t2:Set)(e1:Term t1)(e2:Term t2)(p1:parser_t e1)(p2:parser_t e2) :
parser_t (gcat e1 e2).
intros instream n.
refine (n0 <- position instream n ;
ans1 <- p1 instream n <@> (n ~~ [n0 = n])%hprop ;
match ans1 as ans1' return
STsep (ans_str_correct n instream e1 ans1' * (n ~~ [n0 = n])%hprop)
(ans_str_correct n instream (gcat e1 e2))
with
| OKAY c1 m1 v1 =>
ans2 <- p2 instream (inhabits (m1+n0))<@>
(ans_correct n instream e1 (OKAY c1 m1 v1) * (n ~~ [n0=n]))%hprop;
Return match ans2 with
| OKAY c2 m2 v2 => OKAY (join_cons c1 c2) (m2 + m1) (v1,v2)
| ERROR c2 msg => ERROR (t1*t2)%type (join_cons c1 c2) msg
end <@>
(ans_correct n instream e1 (OKAY c1 m1 v1) * (n ~~ [n0=n]) *
ans_str_correct (inhabits (m1+n0)) instream e2 ans2)%hprop @> _
| ERROR c1 msg =>
{{Return ERROR (t1*t2) c1 msg <@>
(ans_str_correct n instream e1 (ERROR t1 c1 msg) * (n ~~ [n0 = n]))%hprop}}
end) ; repeat rsimp.
Qed.
(* try combinator *)
Definition try(t:Set)(e:Term t)(p:parser_t e) : parser_t (gtry e).
intros instream n.
refine (ans <- p instream n ;
Return match ans with
| ERROR Consumed msg => ERROR t NotConsumed msg
| OKAY Consumed m v => OKAY NotConsumed m v
| ans => ans
end <@> ans_str_correct n instream e ans @> _) ; psimp.
destruct ans ; destruct c ; repeat psimp.
Qed.
(* used in construction of fixed-point *)
Definition coerce_parse_fn(t:Set)(f:forall var, var t -> term var t)(e:Term t)
(H1:Subst (f empvar) (GRec (f empvar)) (e empvar))
(F:parser_t (grec f) -> parser_t e) :
parser_t (grec f) -> parser_t (grec f).
intros p instream n.
refine ((F p instream n) @> _). sep fail auto. sep fail auto. destruct v ; psimp ; econstructor ; eauto.
Qed.
Definition parser_t'(t:Set)(e:Term t)(p:(instream_t char * [nat])) :=
let ins := fst p in
let n := snd p in
STsep (n ~~ rep ins n) (ans_str_correct n ins e).
Open Local Scope stsepi_scope.
(* Alas, note that we need H here -- can't easily prove this once and for all *)
Definition Gfix(t:Set)(f:forall V, V t -> term V t)
(F:parser_t (grec f) -> parser_t (unroll f))
(H: Subst (f empvar) (GRec (f empvar)) (unroll f empvar)) :
parser_t (grec f) :=
(* coerce F so that its result is re-rolled *)
let Fc : parser_t (grec f) -> parser_t (grec f) := coerce_parse_fn H F in
Fix2 _ _ Fc.
Implicit Arguments Gfix [t f].
End CHARSET.
Module ParsecNotation.
Delimit Scope grammar_scope with grammar.
Notation "!!!! v" := (@GVar _ _ _ v) (at level 1) : grammar_scope.
Notation "# c" := (@GSatisfy AsciiCharset _
(fun c2 => if ascii_dec (c)%char c2 then true else false)) (at level 1) : grammar_scope.
Notation "e1 ^ e2" := (GCat e1 e2)
(right associativity, at level 30) : grammar_scope.
Notation "e @ f" := (GMap f e)
(left associativity, at level 78) : grammar_scope.
Notation "e1 '|||' e2" := (GAlt e1 e2)
(right associativity, at level 79) : grammar_scope.
Notation "% v" := (@GEpsilon _ _ _ v) (at level 1) : grammar_scope.
Delimit Scope parser_scope with parser.
Notation "e1 ^ e2" := (cat e1 e2)
(right associativity, at level 30) : parser_scope.
Notation "e @ f" := (map f e)
(left associativity, at level 78) : parser_scope.
Notation "e1 '|||' e2" := (alt e1 e2)
(right associativity, at level 79) : parser_scope.
Notation "# c" := (satisfy AsciiCharset (fun c2 => if ascii_dec (c%char) c2 then true else false))
(at level 1) : parser_scope.
Notation "% v" := (epsilon _ v) : parser_scope.
Notation "'gfix' e" := (Gfix e _) (at level 70).
Ltac gtac := unfold unroll, gclass, grec ; simpl ; repeat (progress constructor).
End ParsecNotation.
|
module resource_table
(/*AUTOARG*/
// Outputs
res_table_done, cam_biggest_space_size, cam_biggest_space_addr,
// Inputs
clk, rst, alloc_res_en, dealloc_res_en, alloc_cu_id, dealloc_cu_id,
alloc_wg_slot_id, dealloc_wg_slot_id, alloc_res_size,
alloc_res_start
);
parameter CU_ID_WIDTH = 1;
parameter NUMBER_CU = 2;
parameter WG_SLOT_ID_WIDTH = 6;
parameter NUMBER_WF_SLOTS_PER_CU = 40;
parameter RES_ID_WIDTH = 10;
parameter NUMBER_RES_SLOTS = 1024;
localparam TABLE_ADDR_WIDTH = WG_SLOT_ID_WIDTH + CU_ID_WIDTH;
localparam TABLE_ENTRY_WIDTH = 2*WG_SLOT_ID_WIDTH + 2*RES_ID_WIDTH+1;
input clk, rst;
input alloc_res_en, dealloc_res_en;
input [CU_ID_WIDTH-1:0] alloc_cu_id, dealloc_cu_id;
input [WG_SLOT_ID_WIDTH-1:0] alloc_wg_slot_id, dealloc_wg_slot_id;
input [RES_ID_WIDTH :0] alloc_res_size;
input [RES_ID_WIDTH-1 :0] alloc_res_start;
output reg res_table_done;
output [RES_ID_WIDTH :0] cam_biggest_space_size;
output [RES_ID_WIDTH-1 :0] cam_biggest_space_addr;
reg alloc_res_en_i, dealloc_res_en_i;
reg [CU_ID_WIDTH-1:0] alloc_cu_id_i, dealloc_cu_id_i;
reg [WG_SLOT_ID_WIDTH-1:0] alloc_wg_slot_id_i, dealloc_wg_slot_id_i;
reg [RES_ID_WIDTH :0] alloc_res_start_i;
reg [RES_ID_WIDTH-1 :0] alloc_res_size_i;
function[TABLE_ENTRY_WIDTH-1 : 0] get_new_entry;
input [RES_ID_WIDTH-1 :0] res_start;
input [RES_ID_WIDTH :0] res_size;
input [WG_SLOT_ID_WIDTH-1:0] prev_entry, next_entry;
get_new_entry = {next_entry, prev_entry, res_size, res_start};
endfunction // if
// Put here localparams for items location
localparam RES_STRT_L = 0;
localparam RES_STRT_H = RES_ID_WIDTH-1;
localparam RES_SIZE_L = RES_STRT_H+1;
localparam RES_SIZE_H = RES_SIZE_L+RES_ID_WIDTH;
localparam PREV_ENTRY_L = RES_SIZE_H+1;
localparam PREV_ENTRY_H = PREV_ENTRY_L + WG_SLOT_ID_WIDTH-1;
localparam NEXT_ENTRY_L = PREV_ENTRY_H + 1;
localparam NEXT_ENTRY_H = NEXT_ENTRY_L + WG_SLOT_ID_WIDTH-1;
function[TABLE_ADDR_WIDTH-1 : 0] calc_table_addr;
input [CU_ID_WIDTH-1:0] cu_id;
input [WG_SLOT_ID_WIDTH-1:0] wg_slot_id;
calc_table_addr = NUMBER_WF_SLOTS_PER_CU*cu_id + wg_slot_id;
endfunction // calc_table_addr
function[WG_SLOT_ID_WIDTH-1 : 0] get_prev_item_wg_slot;
input [TABLE_ENTRY_WIDTH-1 : 0] table_entry;
get_prev_item_wg_slot = table_entry[PREV_ENTRY_H:PREV_ENTRY_L];
endfunction // if
function[WG_SLOT_ID_WIDTH-1 : 0] get_next_item_wg_slot;
input [TABLE_ENTRY_WIDTH-1 : 0] table_entry;
get_next_item_wg_slot = table_entry[NEXT_ENTRY_H:NEXT_ENTRY_L];
endfunction // if
function[RES_ID_WIDTH-1 : 0] get_res_start;
input [TABLE_ENTRY_WIDTH-1 : 0] table_entry;
get_res_start = table_entry[RES_STRT_H:RES_STRT_L];
endfunction // if
function[RES_ID_WIDTH : 0] get_res_size;
input [TABLE_ENTRY_WIDTH-1 : 0] table_entry;
get_res_size = table_entry[RES_SIZE_H:RES_SIZE_L];
endfunction // if
function[TABLE_ENTRY_WIDTH-1 : 0] set_prev_item_wg_slot;
input [WG_SLOT_ID_WIDTH-1:0] prev_item_wg_slot;
input [TABLE_ENTRY_WIDTH-1 : 0] table_entry;
set_prev_item_wg_slot
= {table_entry[NEXT_ENTRY_H:NEXT_ENTRY_L],
prev_item_wg_slot,
table_entry[RES_SIZE_H:RES_SIZE_L],
table_entry[RES_STRT_H:RES_STRT_L]};
endfunction // if
function[TABLE_ENTRY_WIDTH-1 : 0] set_next_item_wg_slot;
input [WG_SLOT_ID_WIDTH-1:0] next_item_wg_slot;
input [TABLE_ENTRY_WIDTH-1 : 0] table_entry;
set_next_item_wg_slot
= {next_item_wg_slot,
table_entry[PREV_ENTRY_H:PREV_ENTRY_L],
table_entry[RES_SIZE_H:RES_SIZE_L],
table_entry[RES_STRT_H:RES_STRT_L]};
endfunction // if
function[RES_ID_WIDTH-1 : 0] get_free_res_start;
input [TABLE_ENTRY_WIDTH-1 : 0] table_entry;
get_free_res_start = get_res_start(table_entry) + get_res_size(table_entry);
endfunction // if
function[RES_ID_WIDTH:0] get_free_res_size;
input [TABLE_ENTRY_WIDTH-1 : 0] last_table_entry, table_entry;
get_free_res_size
= (table_entry[RES_STRT_H:RES_STRT_L]) -
(last_table_entry[RES_STRT_H:RES_STRT_L]+
last_table_entry[RES_SIZE_H:RES_SIZE_L]);
endfunction // if
function[RES_ID_WIDTH:0] get_free_res_size_last;
input [TABLE_ENTRY_WIDTH-1 : 0] table_entry;
get_free_res_size_last
= NUMBER_RES_SLOTS -
(table_entry[RES_STRT_H:RES_STRT_L]+table_entry[RES_SIZE_H:RES_SIZE_L]);
endfunction // if
// Ram to implement the table
localparam NUM_ENTRIES = NUMBER_CU*(NUMBER_WF_SLOTS_PER_CU+1);
localparam[WG_SLOT_ID_WIDTH-1:0] RES_TABLE_END_TABLE = 2**WG_SLOT_ID_WIDTH-1;
localparam[WG_SLOT_ID_WIDTH-1:0] RES_TABLE_HEAD_POINTER = 2**WG_SLOT_ID_WIDTH-2;
reg [TABLE_ENTRY_WIDTH-1 : 0] resource_table_ram[NUM_ENTRIES-1:0];
reg [WG_SLOT_ID_WIDTH-1 : 0] table_head_pointer[NUMBER_CU-1:0];
reg [WG_SLOT_ID_WIDTH-1 : 0] table_head_pointer_i;
wire [RES_ID_WIDTH-1 : 0] rtwr_res_strt, rtrr_res_strt,
rtne_res_strt, rtlrr_res_strt;
wire [RES_ID_WIDTH : 0] rtwr_res_size, rtrr_res_size,
rtne_res_size, rtlrr_res_size;
wire [TABLE_ENTRY_WIDTH-1 : 0] rtwr_prev_item, rtrr_prev_item,
rtne_prev_item, rtlrr_prev_item;
wire [RES_ID_WIDTH-1 : 0] rtwr_next_item, rtrr_next_item,
rtne_next_item, rtlrr_next_item;
// State machines
// Main state machine
localparam ST_M_IDLE = 1;
localparam ST_M_ALLOC = 2;
localparam ST_M_DEALLOC = 4;
localparam ST_M_FIND_MAX = 8;
reg [3:0] m_state;
// Alloc state machine
localparam ST_A_IDLE = 1;
localparam ST_A_FIND_POSITION = 2;
localparam ST_A_UPDATE_PREV_ENTRY = 4;
localparam ST_A_WRITE_NEW_ENTRY = 8;
reg [3:0] a_state;
// Dealloc state machine
localparam ST_D_IDLE = 1;
localparam ST_D_READ_PREV_ENTRY = 2;
localparam ST_D_READ_NEXT_ENTRY = 4;
localparam ST_D_UPDATE_PREV_ENTRY = 8;
localparam ST_D_UPDATE_NEXT_ENTRY = 16;
reg [4:0] d_state;
// Find max state machine
localparam ST_F_IDLE = 1;
localparam ST_F_FIRST_ITEM = 2;
localparam ST_F_SEARCHING = 4;
localparam ST_F_LAST_ITEM = 8;
reg [3:0] f_state;
// Datapath regs
reg [TABLE_ENTRY_WIDTH-1 : 0] res_table_wr_reg, res_table_rd_reg;
reg [TABLE_ENTRY_WIDTH-1 : 0] res_table_last_rd_reg;
reg [CU_ID_WIDTH-1:0] res_addr_cu_id;
reg [WG_SLOT_ID_WIDTH-1 : 0] res_addr_wg_slot;
reg res_table_rd_en, res_table_wr_en;
reg res_table_rd_valid;
reg [RES_ID_WIDTH : 0] res_table_max_size;
reg [RES_ID_WIDTH-1 : 0] res_table_max_start;
// Control signals
reg alloc_start, dealloc_start, find_max_start;
reg alloc_done, dealloc_done, find_max_done;
reg new_entry_is_last, new_entry_is_first;
reg rem_entry_is_last, rem_entry_is_first;
reg [NUMBER_CU-1:0] cu_initialized;
reg cu_initialized_i;
assign rtwr_res_strt = get_res_start(res_table_wr_reg);
assign rtrr_res_strt = get_res_start(res_table_rd_reg);
assign rtlrr_res_strt = get_res_start(res_table_last_rd_reg);
assign rtwr_res_size = get_res_size(res_table_wr_reg);
assign rtrr_res_size = get_res_size(res_table_rd_reg);
assign rtlrr_res_size = get_res_size(res_table_last_rd_reg);
assign rtwr_prev_item = get_prev_item_wg_slot(res_table_wr_reg);
assign rtrr_prev_item = get_prev_item_wg_slot(res_table_rd_reg);
assign rtlrr_prev_item = get_prev_item_wg_slot(res_table_last_rd_reg);
assign rtwr_next_item = get_next_item_wg_slot(res_table_wr_reg);
assign rtrr_next_item = get_next_item_wg_slot(res_table_rd_reg);
assign rtlrr_next_item = get_next_item_wg_slot(res_table_last_rd_reg);
// Implements the resouce table
always @(posedge clk or rst) begin
if(rst) begin
m_state = ST_M_IDLE;
a_state = ST_A_IDLE;
d_state = ST_D_IDLE;
f_state = ST_F_IDLE;
alloc_res_en_i <= 0;
alloc_cu_id_i <= 0;
alloc_res_start_i <= 0;
alloc_res_size_i <= 0;
alloc_start <= 0;
alloc_done <= 0;
new_entry_is_first <= 0;
new_entry_is_last <= 0;
dealloc_res_en_i <= 0;
dealloc_cu_id_i <= 0;
dealloc_wg_slot_id_i <= 0;
dealloc_start <= 0;
dealloc_done <= 0;
find_max_start <= 0;
find_max_done <=0;
rem_entry_is_first <= 0;
rem_entry_is_last <= 0;
find_max_done <= 0;
find_max_start <= 0;
res_table_max_size <= 0;
res_table_max_start <= 0;
res_addr_cu_id <= 0;
res_addr_wg_slot <= 0;
table_head_pointer_i <= 0;
res_table_rd_reg <= 0;
res_table_last_rd_reg <= 0;
res_table_rd_en <= 0;
res_table_rd_valid <=0;
res_table_wr_en <= 0;
res_table_wr_reg <= 0;
cu_initialized <= 0;
cu_initialized_i <= 0;
end else begin
// Flop input signals
alloc_res_en_i <= alloc_res_en;
if(alloc_res_en) begin
alloc_cu_id_i <= alloc_cu_id;
alloc_wg_slot_id_i <= alloc_wg_slot_id;
alloc_res_start_i <= alloc_res_start;
alloc_res_size_i <= alloc_res_size;
res_addr_cu_id <= alloc_cu_id;
end
dealloc_res_en_i <= dealloc_res_en;
if(dealloc_res_en) begin
dealloc_cu_id_i <= dealloc_cu_id;
dealloc_wg_slot_id_i <= dealloc_wg_slot_id;
res_addr_cu_id <= dealloc_cu_id;
end
// Main state machine of the resource table
alloc_start <= 1'b0;
dealloc_start <= 1'b0;
find_max_start <= 1'b0;
res_table_done <= 1'b0;
case(m_state)
ST_M_IDLE : begin
if(1'b1 == alloc_res_en_i) begin
alloc_start <= 1'b1;
m_state <= ST_M_ALLOC;
end else if(1'b1 == dealloc_res_en_i) begin
dealloc_start <= 1'b1;
m_state <= ST_M_DEALLOC;
end
end
/////////////////////////////////////////////////
ST_M_ALLOC : begin
if(1'b1 == alloc_done) begin
find_max_start <= 1'b1;
m_state <= ST_M_FIND_MAX;
end
end
/////////////////////////////////////////////////
ST_M_DEALLOC : begin
if(1'b1 == dealloc_done) begin
find_max_start <= 1'b1;
m_state <= ST_M_FIND_MAX;
end
end
/////////////////////////////////////////////////
ST_M_FIND_MAX : begin
if(1'b1 == find_max_done) begin
res_table_done <= 1'b1;
m_state <= ST_M_IDLE;
end
end
/////////////////////////////////////////////////
endcase // case (m_state)
// All state machines share the same resource (the table) so,
// there can be onle one machine out of IDLE state at a given time.
res_table_rd_en <= 1'b0;
res_table_wr_en <= 1'b0;
alloc_done <= 1'b0;
// Alloc state machine
case(a_state)
ST_A_IDLE : begin
// Start looking for the new entry positon on
// head_position
if( alloc_start ) begin
// Table is clear or cu was not initialized
if( (table_head_pointer_i == RES_TABLE_END_TABLE) ||
!cu_initialized_i) begin
new_entry_is_first <= 1'b1;
new_entry_is_last <= 1'b1;
a_state <= ST_A_WRITE_NEW_ENTRY;
// Otherwise we have to find a position
end else begin
new_entry_is_last <= 1'b0;
new_entry_is_first <= 1'b0;
res_table_rd_en <= 1'b1;
res_addr_wg_slot <= table_head_pointer_i;
a_state <= ST_A_FIND_POSITION;
end
end // if ( alloc_start )
end // case: ST_A_IDLE
ST_A_FIND_POSITION : begin
// Look for the entry postion
if( res_table_rd_valid ) begin
// Found the entry that will be after the new one
if( get_res_start(res_table_rd_reg) > alloc_res_start_i ) begin
// if new entry will be the first entry
if( get_prev_item_wg_slot(res_table_rd_reg) ==
RES_TABLE_HEAD_POINTER) begin
new_entry_is_first <= 1'b1;
res_table_wr_en <= 1'b1;
res_table_wr_reg
<= set_prev_item_wg_slot(alloc_wg_slot_id_i,
res_table_rd_reg);
a_state <= ST_A_WRITE_NEW_ENTRY;
end
// Normal case
else begin
// Update this entry
res_table_wr_en <= 1'b1;
res_table_wr_reg
<= set_prev_item_wg_slot(alloc_wg_slot_id_i,
res_table_rd_reg);
a_state <= ST_A_UPDATE_PREV_ENTRY;
end // else: !if( get_prev_item_wg_slot(res_table_rd_reg) ==...
end // if ( get_res_start(res_table_rd_reg) > alloc_res_start_i )
// The new entry will be the last entry
else if( get_next_item_wg_slot(res_table_rd_reg) ==
RES_TABLE_END_TABLE ) begin
res_table_wr_en <= 1'b1;
res_table_wr_reg
<= set_next_item_wg_slot(alloc_wg_slot_id_i,res_table_rd_reg);
new_entry_is_last <= 1'b1;
a_state <= ST_A_WRITE_NEW_ENTRY;
end
// Keep looking for the entry postion
else begin
res_table_rd_en <= 1'b1;
res_addr_wg_slot <= get_next_item_wg_slot(res_table_rd_reg);
end // else: !if( get_next_item_wg_slot(res_table_rd_reg) ==...
end // if ( res_table_rd_valid )
end // case: ST_A_FIND_POSITION
ST_A_UPDATE_PREV_ENTRY : begin
// Update the entry that will be before the new one
res_table_wr_en <= 1'b1;
res_table_wr_reg
<= set_next_item_wg_slot(alloc_wg_slot_id_i,
res_table_last_rd_reg);
res_addr_wg_slot <= get_prev_item_wg_slot(res_table_rd_reg);
a_state <= ST_A_WRITE_NEW_ENTRY;
end
ST_A_WRITE_NEW_ENTRY : begin
if( new_entry_is_first ) begin
table_head_pointer_i <= alloc_wg_slot_id_i;
end
// Write the new entry
res_table_wr_en <= 1'b1;
res_addr_wg_slot <= alloc_wg_slot_id_i;
if( new_entry_is_first && new_entry_is_last ) begin
res_table_wr_reg
<= get_new_entry(alloc_res_start_i, alloc_res_size_i,
RES_TABLE_HEAD_POINTER,
RES_TABLE_END_TABLE);
end
else if( new_entry_is_last ) begin
res_table_wr_reg
<= get_new_entry(alloc_res_start_i, alloc_res_size_i,
res_addr_wg_slot,
RES_TABLE_END_TABLE);
end
else if(new_entry_is_first) begin
res_table_wr_reg
<= get_new_entry(alloc_res_start_i, alloc_res_size_i,
RES_TABLE_HEAD_POINTER,
res_addr_wg_slot);
end
else begin
res_table_wr_reg
<= get_new_entry(alloc_res_start_i, alloc_res_size_i,
res_addr_wg_slot,
get_next_item_wg_slot(res_table_last_rd_reg));
end // else: !if( new_entry_is_last )
alloc_done <= 1'b1;
a_state <= ST_A_IDLE;
end
endcase // case (a_state)
// Dealloc state machine
dealloc_done <= 1'b0;
case(d_state)
ST_D_IDLE: begin
if( dealloc_start ) begin
rem_entry_is_last <= 1'b0;
rem_entry_is_first <= 1'b0;
res_table_rd_en <= 1'b1;
res_addr_wg_slot <= dealloc_wg_slot_id_i;
d_state <= ST_D_READ_PREV_ENTRY;
end
end
ST_D_READ_PREV_ENTRY : begin
if (res_table_rd_valid ) begin
// We are removing the last remaining entry on the table
if( (get_prev_item_wg_slot(res_table_rd_reg)
== RES_TABLE_HEAD_POINTER) &&
(get_next_item_wg_slot(res_table_rd_reg)
== RES_TABLE_END_TABLE)) begin
table_head_pointer_i <= RES_TABLE_END_TABLE;
dealloc_done <= 1'b1;
d_state <= ST_D_IDLE;
// We are removing the first entry on the table
end else if(get_prev_item_wg_slot(res_table_rd_reg)
== RES_TABLE_HEAD_POINTER) begin
rem_entry_is_first <= 1'b1;
d_state <= ST_D_READ_NEXT_ENTRY;
// We are removing the last entry on the table
end else if (get_next_item_wg_slot(res_table_rd_reg)
== RES_TABLE_END_TABLE) begin
rem_entry_is_last <= 1'b1;
res_table_rd_en <= 1'b1;
res_addr_wg_slot <= get_prev_item_wg_slot(res_table_rd_reg);
d_state <= ST_D_UPDATE_PREV_ENTRY;
// We are a normal entry
end else begin
res_table_rd_en <= 1'b1;
res_addr_wg_slot <= get_prev_item_wg_slot(res_table_rd_reg);
d_state <= ST_D_READ_NEXT_ENTRY;
end
end // if (res_table_rd_valid )
end // case: ST_D_READ_PREV_ENTRY
ST_D_READ_NEXT_ENTRY : begin
res_table_rd_en <= 1'b1;
res_addr_wg_slot <= get_next_item_wg_slot(res_table_rd_reg);
d_state <= ST_D_UPDATE_PREV_ENTRY;
end
ST_D_UPDATE_PREV_ENTRY : begin
// In this cycle it is reading the next entry, so we can use the
// the addr_reg to get our the next entry addr
// Single cycle delay to complete reading if the entry if the entry
// is the first or the last
if(rem_entry_is_first) begin
d_state <= ST_D_UPDATE_NEXT_ENTRY;
end else if(rem_entry_is_last) begin
d_state <= ST_D_UPDATE_NEXT_ENTRY;
end else begin
res_table_wr_en <= 1'b1;
res_addr_wg_slot <= get_prev_item_wg_slot(res_table_last_rd_reg);
res_table_wr_reg
<= set_next_item_wg_slot(res_addr_wg_slot,
res_table_rd_reg);
d_state <= ST_D_UPDATE_NEXT_ENTRY;
end // else: !if(rem_entry_is_last)
end // case: ST_D_UPDATE_PREV_ENTRY
ST_D_UPDATE_NEXT_ENTRY : begin
// In this cycle it is writing the previous entry, so we can use the
// the addr_reg to get our the next entry addr
res_table_wr_en <= 1'b1;
if( rem_entry_is_first ) begin
table_head_pointer_i <= res_addr_wg_slot;
res_table_wr_reg
<= set_prev_item_wg_slot(RES_TABLE_HEAD_POINTER,
res_table_rd_reg);
end else if ( rem_entry_is_last ) begin
res_table_wr_en <= 1'b1;
// No need to update addr, we are writing the
// entry we just read
res_table_wr_reg
<= set_next_item_wg_slot(RES_TABLE_END_TABLE,
res_table_rd_reg);
end else begin
res_addr_wg_slot <= get_next_item_wg_slot(res_table_wr_reg);
res_table_wr_reg
<= set_prev_item_wg_slot(res_addr_wg_slot,
res_table_rd_reg);
end
dealloc_done <= 1'b1;
d_state <= ST_D_IDLE;
end // case: ST_D_UPDATE_NEXT_ENTRY
endcase
// Find max state machine
find_max_done <= 1'b0;
case(f_state)
ST_F_IDLE : begin
if( find_max_start ) begin
// Zero the max res size reg
res_table_max_size <= 0;
// In case table is clear, return 0 and finish
if(table_head_pointer_i == RES_TABLE_END_TABLE) begin
res_table_max_size
<= NUMBER_RES_SLOTS;
res_table_max_start
<= 0;
find_max_done <= 1'b1;
// otherwise start searching
end else begin
res_table_rd_en <= 1'b1;
res_addr_wg_slot <= table_head_pointer_i;
f_state <= ST_F_FIRST_ITEM;
end
end // if ( find_max_start )
end // case: ST_F_IDLE
ST_F_FIRST_ITEM: begin
// only read first item. If it is alst the last, skip
// the searching state
if( res_table_rd_valid ) begin
res_table_max_size
<= get_res_start(res_table_rd_reg);
res_table_max_start
<= 0;
// check if it is in the end o of the table
if( get_next_item_wg_slot(res_table_rd_reg) !=
RES_TABLE_END_TABLE) begin
res_table_rd_en <= 1'b1;
res_addr_wg_slot <= get_next_item_wg_slot(res_table_rd_reg);
f_state <= ST_F_SEARCHING;
end else begin
f_state <= ST_F_LAST_ITEM;
end
end // if ( res_table_rd_valid )
end // case: ST_F_FIRST_ITEM
ST_F_SEARCHING : begin
if( res_table_rd_valid ) begin
// check if it is in the end o of the table
if( get_next_item_wg_slot(res_table_rd_reg) !=
RES_TABLE_END_TABLE) begin
res_table_rd_en <= 1'b1;
res_addr_wg_slot <= get_next_item_wg_slot(res_table_rd_reg);
end else begin
f_state <= ST_F_LAST_ITEM;
end
// check if this is the max res size
if( get_free_res_size(res_table_last_rd_reg, res_table_rd_reg) >
res_table_max_size) begin
res_table_max_size
<= get_free_res_size(res_table_last_rd_reg, res_table_rd_reg);
res_table_max_start
<= get_free_res_start(res_table_last_rd_reg);
end
end // if ( res_table_rd_valid )
end // case: ST_F_SEARCHING
ST_F_LAST_ITEM : begin
// calculate the free space for the last item
if( get_free_res_size_last(res_table_rd_reg) >
res_table_max_size) begin
res_table_max_size
<= get_free_res_size_last(res_table_rd_reg);
res_table_max_start
<= get_free_res_start(res_table_rd_reg);
end
find_max_done <= 1'b1;
f_state <= ST_F_IDLE;
end // case: ST_F_LAST_ITEM
endcase
// Data path of the resource table
if( alloc_res_en_i || dealloc_res_en_i ) begin
// Read the head pointer at the start
cu_initialized_i <= cu_initialized[res_addr_cu_id];
table_head_pointer_i <= table_head_pointer[res_addr_cu_id];
end else if (alloc_done || dealloc_done) begin
// Write at the end
table_head_pointer[res_addr_cu_id] <= table_head_pointer_i;
cu_initialized[res_addr_cu_id] <= 1'b1;
end
res_table_rd_valid <= res_table_rd_en;
if( res_table_rd_en ) begin
res_table_rd_reg
<= resource_table_ram[calc_table_addr(res_addr_cu_id,
res_addr_wg_slot)];
res_table_last_rd_reg <= res_table_rd_reg;
end else if (res_table_wr_en) begin
resource_table_ram[calc_table_addr(res_addr_cu_id, res_addr_wg_slot)]
<= res_table_wr_reg;
end
end // else: !if(rst)
end // always @ (posedge clk or rst)
assign cam_biggest_space_size = res_table_max_size;
assign cam_biggest_space_addr = res_table_max_start;
endmodule
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 18:39:12 09/13/2014
// Design Name: timer32
// Module Name: C:/ece4743/projects/lab6_solution/tb_timer32.v
// Project Name: lab6_solution
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: timer32
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_timer32;
// Inputs
reg clk;
reg reset;
reg [31:0] din;
reg wren;
reg rden;
reg [1:0] addr;
// Outputs
wire [31:0] dout;
`define PERIOD_INITIAL 32'h0000000F
`define TMR_REG 2'b00
`define PER_REG 2'b01
`define CON_REG 2'b10
// Instantiate the Unit Under Test (UUT)
timer32 #(.PERIOD(`PERIOD_INITIAL),.ENBIT(0)) uut (
.clk(clk),
.reset(reset),
.din(din),
.dout(dout),
.wren(wren),
.rden(rden),
.addr(addr)
);
initial begin
clk = 0;
#100 //reset delay
forever #20 clk = ~clk;
end
integer errors;
initial begin
// Initialize Inputs
#1
clk = 0;
reset = 1;
din = 0;
wren = 0;
rden = 0;
addr = 0;
errors = 0;
// Wait 100 ns for global reset to finish
#100;
reset = 0;
@(negedge clk);
rden = 1;
addr = `TMR_REG;
@(negedge clk);
//read Timer register
if (dout != 0) begin
$display("(%t)FAIL: Timer not reset to zero\n",$time());
errors = errors + 1;
end
addr = `PER_REG;
@(negedge clk);
//read Period register
if (dout != `PERIOD_INITIAL) begin
$display("(%t)FAIL: Period register not reset to initial parameter value\n",$time());
errors = errors + 1;
end
addr = `CON_REG;
@(negedge clk);
//read Control register
if (dout != 0) begin
$display("(%t)FAIL: Control register not reset to zero\n",$time());
errors = errors + 1;
end
addr = `PER_REG;
din = 32'h00000007;
wren = 1;
@(negedge clk); //write
//write Period register, read result
if (dout != 32'h00000007) begin
$display("(%t)FAIL: Period register write failed\n",$time());
errors = errors + 1;
end
//enable the timer, write a '1' to the EN bit
wren = 1;
addr = `CON_REG;
din = 1;
@(negedge clk);
wren = 0;
addr = `TMR_REG;
@(negedge clk);
//timer should have incremented
if (dout != 1) begin
$display("(%t)FAIL: Timer failed to increment\n",$time());
errors = errors + 1;
end
@(negedge clk);
//timer should have incremented
if (dout != 2) begin
$display("(%t)FAIL: Timer failed to increment\n",$time());
errors = errors + 1;
end
@(negedge clk); //timer=3
@(negedge clk); //timer=4
@(negedge clk); //timer=5
@(negedge clk); //timer=6
@(negedge clk); //timer=7
//period register should cause the timer to reset
@(negedge clk); //timer=0
if (dout != 0) begin
$display("(%t)FAIL: Timer (%d) failed to be reset by period register\n",$time(),din);
errors = errors + 1;
end
@(posedge clk); //timer =1
//read the control register, all three bits should be set!
//change addres after posedge so can read register output on negedge
addr = `CON_REG;
@(negedge clk); //timer=1
if (dout != 7) begin
$display("(%t)FAIL: Expected Control register value of 7, got (%d)\n",$time(),din);
errors = errors + 1;
end
@(negedge clk); //timer=2
//read again, the timer flag bit should be cleared because of previous reead
if (dout != 5) begin
$display("(%t)FAIL: Expected Control register value of 5, got (%d)\n",$time(),din);
errors = errors + 1;
end
@(negedge clk); //timer=3
addr = `CON_REG;
wren = 1;
din = 4; //disable the timer, keep the toggle bit as '1' ('b100)
//We are clearing the TMR enable bit to freeze the timer value
@(negedge clk); //timer=4, but should no longer increment
addr = `TMR_REG;
wren = 0;
//cannot check DOUT here as we have just changed the address bus
@(negedge clk); //timer=4
//Timer should be frozen at 4
if (dout != 4) begin
$display("(%t)FAIL: Expected Timer register value of 4, got (%d)\n",$time(),din);
errors = errors + 1;
end
//lets renable the timer
@(negedge clk); //timer=4
//Timer should be frozen at 4
addr = `CON_REG;
wren = 1;
din = 5; //enable the timer, keep the toggle bit as '1' ('b100)
@(negedge clk); //timer=4
addr = `TMR_REG;
wren = 0;
//Timer is 4, but should start counting again
@(negedge clk); //timer=5
if (dout != 5) begin
$display("(%t)FAIL: Expected Timer register value of 5, got (%d)\n",$time(),din);
errors = errors + 1;
end
@(negedge clk); //timer=6
if (dout != 6) begin
$display("(%t)FAIL: Expected Timer register value of 6, got (%d)\n",$time(),din);
errors = errors + 1;
end
@(negedge clk); //timer=7
if (dout != 7) begin
$display("(%t)FAIL: Expected Timer register value of 7, got (%d)\n",$time(),din);
errors = errors + 1;
end
@(negedge clk); //timer=0
if (dout != 0) begin
$display("(%t)FAIL: Expected Timer register value of 0, got (%d)\n",$time(),din);
errors = errors + 1;
end
@(negedge clk); //timer=1
@(posedge clk); //timer = 2
//change address right after pos edge so have time read at neg edge
addr = `CON_REG; //read the control register
@(negedge clk); //timer=2
//the toggle bit should cleared, the TMR Flag, enable bits should be set
if (dout != 3) begin
$display("(%t)FAIL: Expected Control register value of 3, got (%d)\n",$time(),din);
errors = errors + 1;
end
@(negedge clk); //timer=3
//the toggle bit, TMR flag bits should cleared,the enable bits should be set
if (dout != 1) begin
$display("(%t)FAIL: Expected Control register value of 1, got (%d)\n",$time(),din);
errors = errors + 1;
end
if (errors == 0) begin
$display("(%t)PASSED: All vectors passed\n",$time());
end else begin
$display("(%t)FAILED: %d vectors failed\n",$time(),errors);
end
end
endmodule
|
//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module nios_system_sram_data (
// inputs:
address,
chipselect,
clk,
reset_n,
write_n,
writedata,
// outputs:
bidir_port,
readdata
)
;
inout [ 15: 0] bidir_port;
output [ 31: 0] readdata;
input [ 1: 0] address;
input chipselect;
input clk;
input reset_n;
input write_n;
input [ 31: 0] writedata;
wire [ 15: 0] bidir_port;
wire clk_en;
reg [ 15: 0] data_dir;
wire [ 15: 0] data_in;
reg [ 15: 0] data_out;
wire [ 15: 0] read_mux_out;
reg [ 31: 0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = ({16 {(address == 0)}} & data_in) |
({16 {(address == 1)}} & data_dir);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
readdata <= 0;
else if (clk_en)
readdata <= {32'b0 | read_mux_out};
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
data_out <= 0;
else if (chipselect && ~write_n && (address == 0))
data_out <= writedata[15 : 0];
end
assign bidir_port[0] = data_dir[0] ? data_out[0] : 1'bZ;
assign bidir_port[1] = data_dir[1] ? data_out[1] : 1'bZ;
assign bidir_port[2] = data_dir[2] ? data_out[2] : 1'bZ;
assign bidir_port[3] = data_dir[3] ? data_out[3] : 1'bZ;
assign bidir_port[4] = data_dir[4] ? data_out[4] : 1'bZ;
assign bidir_port[5] = data_dir[5] ? data_out[5] : 1'bZ;
assign bidir_port[6] = data_dir[6] ? data_out[6] : 1'bZ;
assign bidir_port[7] = data_dir[7] ? data_out[7] : 1'bZ;
assign bidir_port[8] = data_dir[8] ? data_out[8] : 1'bZ;
assign bidir_port[9] = data_dir[9] ? data_out[9] : 1'bZ;
assign bidir_port[10] = data_dir[10] ? data_out[10] : 1'bZ;
assign bidir_port[11] = data_dir[11] ? data_out[11] : 1'bZ;
assign bidir_port[12] = data_dir[12] ? data_out[12] : 1'bZ;
assign bidir_port[13] = data_dir[13] ? data_out[13] : 1'bZ;
assign bidir_port[14] = data_dir[14] ? data_out[14] : 1'bZ;
assign bidir_port[15] = data_dir[15] ? data_out[15] : 1'bZ;
assign data_in = bidir_port;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
data_dir <= 0;
else if (chipselect && ~write_n && (address == 1))
data_dir <= writedata[15 : 0];
end
endmodule
|
// DESCRIPTION: Verilator: Interface parameter getter
//
// A test of the import parameter used with modport
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2015 by Todd Strader
interface test_if #(parameter integer FOO = 1);
// Interface variable
logic data;
// Modport
modport mp(
import getFoo,
output data
);
function integer getFoo ();
return FOO;
endfunction
endinterface // test_if
function integer identity (input integer x);
return x;
endfunction
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
test_if #( .FOO (identity(5)) ) the_interface ();
testmod testmod_i (.clk (clk),
.intf (the_interface),
.intf_no_mp (the_interface)
);
localparam THE_TOP_FOO = the_interface.FOO;
initial begin
if (THE_TOP_FOO != 5) begin
$display("%%Error: THE_TOP_FOO = %0d", THE_TOP_FOO);
$stop;
end
end
endmodule
module testmod
(
input clk,
test_if.mp intf,
test_if intf_no_mp
);
localparam THE_FOO = intf.FOO;
localparam THE_OTHER_FOO = intf_no_mp.FOO;
always @(posedge clk) begin
if (THE_FOO != 5) begin
$display("%%Error: THE_FOO = %0d", THE_FOO);
$stop;
end
if (THE_OTHER_FOO != 5) begin
$display("%%Error: THE_OTHER_FOO = %0d", THE_OTHER_FOO);
$stop;
end
if (intf.FOO != 5) begin
$display("%%Error: intf.FOO = %0d", intf.FOO);
$stop;
end
if (intf_no_mp.FOO != 5) begin
$display("%%Error: intf_no_mp.FOO = %0d", intf_no_mp.FOO);
$stop;
end
// if (i.getFoo() != 5) begin
// $display("%%Error: i.getFoo() = %0d", i.getFoo());
// $stop;
// end
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
|
///////////////////////////////////////////////////////////////////////////////
//
// File name: axi_protocol_converter_v2_1_7_b2s_rd_cmd_fsm.v
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1ps/1ps
`default_nettype none
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_protocol_converter_v2_1_7_b2s_rd_cmd_fsm (
///////////////////////////////////////////////////////////////////////////////
// Port Declarations
///////////////////////////////////////////////////////////////////////////////
input wire clk ,
input wire reset ,
output wire s_arready ,
input wire s_arvalid ,
input wire [7:0] s_arlen ,
output wire m_arvalid ,
input wire m_arready ,
// signal to increment to the next mc transaction
output wire next ,
// signal to the fsm there is another transaction required
input wire next_pending ,
// Write Data portion has completed or Read FIFO has a slot available (not
// full)
input wire data_ready ,
// status signal for w_channel when command is written.
output wire a_push ,
output wire r_push
);
////////////////////////////////////////////////////////////////////////////////
// Local parameters
////////////////////////////////////////////////////////////////////////////////
// States
localparam SM_IDLE = 2'b00;
localparam SM_CMD_EN = 2'b01;
localparam SM_CMD_ACCEPTED = 2'b10;
localparam SM_DONE = 2'b11;
////////////////////////////////////////////////////////////////////////////////
// Wires/Reg declarations
////////////////////////////////////////////////////////////////////////////////
reg [1:0] state;
// synthesis attribute MAX_FANOUT of state is 20;
reg [1:0] state_r1;
reg [1:0] next_state;
reg [7:0] s_arlen_r;
////////////////////////////////////////////////////////////////////////////////
// BEGIN RTL
///////////////////////////////////////////////////////////////////////////////
// register for timing
always @(posedge clk) begin
if (reset) begin
state <= SM_IDLE;
state_r1 <= SM_IDLE;
s_arlen_r <= 0;
end else begin
state <= next_state;
state_r1 <= state;
s_arlen_r <= s_arlen;
end
end
// Next state transitions.
always @( * ) begin
next_state = state;
case (state)
SM_IDLE:
if (s_arvalid & data_ready) begin
next_state = SM_CMD_EN;
end else begin
next_state = state;
end
SM_CMD_EN:
///////////////////////////////////////////////////////////////////
// Drive m_arvalid downstream in this state
///////////////////////////////////////////////////////////////////
//If there is no fifo space
if (~data_ready & m_arready & next_pending) begin
///////////////////////////////////////////////////////////////////
//There is more to do, wait until data space is available drop valid
next_state = SM_CMD_ACCEPTED;
end else if (m_arready & ~next_pending)begin
next_state = SM_DONE;
end else if (m_arready & next_pending) begin
next_state = SM_CMD_EN;
end else begin
next_state = state;
end
SM_CMD_ACCEPTED:
if (data_ready) begin
next_state = SM_CMD_EN;
end else begin
next_state = state;
end
SM_DONE:
next_state = SM_IDLE;
default:
next_state = SM_IDLE;
endcase
end
// Assign outputs based on current state.
assign m_arvalid = (state == SM_CMD_EN);
assign next = m_arready && (state == SM_CMD_EN);
assign r_push = next;
assign a_push = (state == SM_IDLE);
assign s_arready = ((state == SM_CMD_EN) || (state == SM_DONE)) && (next_state == SM_IDLE);
endmodule
`default_nettype wire
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O31A_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LP__O31A_FUNCTIONAL_PP_V
/**
* o31a: 3-input OR into 2-input AND.
*
* X = ((A1 | A2 | A3) & B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__o31a (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire or0_out ;
wire and0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
or or0 (or0_out , A2, A1, A3 );
and and0 (and0_out_X , or0_out, B1 );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__O31A_FUNCTIONAL_PP_V |
/*
----------------------------------------------------------------------------------
Copyright (c) 2013-2014
Embedded and Network Computing Lab.
Open SSD Project
Hanyang University
All rights reserved.
----------------------------------------------------------------------------------
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. All advertising materials mentioning features or use of this source code
must display the following acknowledgement:
This product includes source code developed
by the Embedded and Network Computing Lab. and the Open SSD Project.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
----------------------------------------------------------------------------------
http://enclab.hanyang.ac.kr/
http://www.openssd-project.org/
http://www.hanyang.ac.kr/
----------------------------------------------------------------------------------
*/
`timescale 1ns / 1ps
module pcie_rx # (
parameter C_PCIE_DATA_WIDTH = 128
)
(
input pcie_user_clk,
input pcie_user_rst_n,
//pcie rx signal
input [C_PCIE_DATA_WIDTH-1:0] s_axis_rx_tdata,
input [(C_PCIE_DATA_WIDTH/8)-1:0] s_axis_rx_tkeep,
input s_axis_rx_tlast,
input s_axis_rx_tvalid,
output s_axis_rx_tready,
input [21:0] s_axis_rx_tuser,
output pcie_mreq_err,
output pcie_cpld_err,
output pcie_cpld_len_err,
output mreq_fifo_wr_en,
output [C_PCIE_DATA_WIDTH-1:0] mreq_fifo_wr_data,
output [7:0] cpld0_fifo_tag,
output cpld0_fifo_tag_last,
output cpld0_fifo_wr_en,
output [C_PCIE_DATA_WIDTH-1:0] cpld0_fifo_wr_data,
output [7:0] cpld1_fifo_tag,
output cpld1_fifo_tag_last,
output cpld1_fifo_wr_en,
output [C_PCIE_DATA_WIDTH-1:0] cpld1_fifo_wr_data,
output [7:0] cpld2_fifo_tag,
output cpld2_fifo_tag_last,
output cpld2_fifo_wr_en,
output [C_PCIE_DATA_WIDTH-1:0] cpld2_fifo_wr_data
);
wire [7:0] w_cpld_fifo_tag;
wire w_cpld_fifo_tag_last;
wire w_cpld_fifo_wr_en;
wire [C_PCIE_DATA_WIDTH-1:0] w_cpld_fifo_wr_data;
pcie_rx_recv # (
.C_PCIE_DATA_WIDTH (C_PCIE_DATA_WIDTH)
)
pcie_rx_recv_inst0(
.pcie_user_clk (pcie_user_clk),
.pcie_user_rst_n (pcie_user_rst_n),
//pcie rx signal
.s_axis_rx_tdata (s_axis_rx_tdata),
.s_axis_rx_tkeep (s_axis_rx_tkeep),
.s_axis_rx_tlast (s_axis_rx_tlast),
.s_axis_rx_tvalid (s_axis_rx_tvalid),
.s_axis_rx_tready (s_axis_rx_tready),
.s_axis_rx_tuser (s_axis_rx_tuser),
.pcie_mreq_err (pcie_mreq_err),
.pcie_cpld_err (pcie_cpld_err),
.pcie_cpld_len_err (pcie_cpld_len_err),
.mreq_fifo_wr_en (mreq_fifo_wr_en),
.mreq_fifo_wr_data (mreq_fifo_wr_data),
.cpld_fifo_tag (w_cpld_fifo_tag),
.cpld_fifo_tag_last (w_cpld_fifo_tag_last),
.cpld_fifo_wr_en (w_cpld_fifo_wr_en),
.cpld_fifo_wr_data (w_cpld_fifo_wr_data)
);
pcie_rx_cpld_sel
pcie_rx_cpld_sel_inst0(
.pcie_user_clk (pcie_user_clk),
.cpld_fifo_tag (w_cpld_fifo_tag),
.cpld_fifo_tag_last (w_cpld_fifo_tag_last),
.cpld_fifo_wr_en (w_cpld_fifo_wr_en),
.cpld_fifo_wr_data (w_cpld_fifo_wr_data),
.cpld0_fifo_tag (cpld0_fifo_tag),
.cpld0_fifo_tag_last (cpld0_fifo_tag_last),
.cpld0_fifo_wr_en (cpld0_fifo_wr_en),
.cpld0_fifo_wr_data (cpld0_fifo_wr_data),
.cpld1_fifo_tag (cpld1_fifo_tag),
.cpld1_fifo_tag_last (cpld1_fifo_tag_last),
.cpld1_fifo_wr_en (cpld1_fifo_wr_en),
.cpld1_fifo_wr_data (cpld1_fifo_wr_data),
.cpld2_fifo_tag (cpld2_fifo_tag),
.cpld2_fifo_tag_last (cpld2_fifo_tag_last),
.cpld2_fifo_wr_en (cpld2_fifo_wr_en),
.cpld2_fifo_wr_data (cpld2_fifo_wr_data)
);
endmodule |
/*
* Copyright (c) 2003 Stephen Williams ([email protected])
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
/*
* This sample demonstrates the post 20030904 Icarus Verilog feature
* where combinational blocks with time-0 races against the rest of
* the design can be resolved.
*
* The always @(foo) threads should be detected by the compiler as
* combinational, and should be pushed to the front of the time-0
* scheduling queue. This causes the threads to enter the wait early
* so that it can detect the change from x to 1 for its value.
*
* The program HAS a time-0 race according to the IEEE1364 standard,
* but Icarus Verilog as an extension resolves this race intentionally
* as described.
*/
module main;
reg foo, bar;
reg foo_ok = 0, bar_ok = 0;
initial foo = 1;
always @(foo) begin
if (foo !== 1'b1) begin
$display("FAILED --(foo = %b)", foo);
$finish;
end
foo_ok = 1;
end
always @(bar) begin
if (bar !== 1'b1) begin
$display("FAILED --(bar = %b)", bar);
$finish;
end
bar_ok = 1;
end
initial bar = 1;
initial begin
#1 if (foo_ok !== 1) begin
$display("FAILED -- foo lost the race");
$finish;
end
if (bar_ok !== 1) begin
$display("FAILED -- bar lost the race");
$finish;
end
$display("PASSED");
end // initial begin
endmodule // main
|
//-----------------------------------------------------------------------------
// module: serial.vhd
// This file contains modules for serial I/O.
//
// OVERVIEW of contents: The clock generators are
// configured to provide clocks at 16x the desired transmit
// BAUD rates for RS232 serial I/O. This is done so that
// the rs232rx module can easily share the clock generation
// circuitry of the rs232tx block.
// The clock_gen_select module has a BAUD rate selection
// input field of three bits. This field allows the appropriate
// "clock_factor" clock rate to be produced once and used on many
// transmitters and receivers.
// Alternatively, there is a "clock_gen" block which uses parameters
// to specify the desired values for the DDS and prescaler divide factor.
//
// Author: John Clayton
// Date : Nov. 7, 2000
// Update: Nov. 7, 2000 Created this file, with RS232tx block only
// The rs232tx block has no double buffering.
// Update: Nov. 9, 2000 Separated clock generator circuitry into "clock_gen"
// Update: Nov. 29, 2000 Added rs232rx block
// Update: Nov. 30, 2000 Moved contents of "async_tx" and "async_rx" from
// blocks.vhd to this file.
// Update: May 7, 2001 Translated this file from VHDL to verilog, using
// "xhdl"
// Update: May 8, 2001 Since the output of xhdl was rather "spotty", I have
// fixed errors and filled in the "holes" in the code.
// In addition, I have tried to wean this file from
// its previous use and dependency upon "blocks.v"
// (also translated from VHDL, but consisting of rather
// trivial modules.)
// Update: May 8, 2001 Converted to synchronous resets on all flip-flops.
// Update: May 16, 2001 Re-worked the state machines for rs232rx and rs232tx.
// Update: July 25, 2001 Changed the polarity of q[] in rs232_tx, so that its
// output will be the desired (high) level upon initial
// FPGA configuration, even before or without a reset!
// Update: Jan. 30, 2002 Corrected the formula in STEP 1: Find the ratio.
// (Thanks to Shehryar Shaheen at the University of
// Limerick for pointing out the error.)
// Update: June 28, 2002 Fixed "clock_gen" so that it uses the dds_clk.
//
//----------------------------------------
//
// FORMULATING BAUD RATE SETTINGS
//
//
// This ROM contains BAUD rate selection parameters for
// use with the clock_gen_select block.
// The BAUD clocks which are generated are positive pulses,
// (used as clock enables,) and may be used as general clock enables
// if desired.
// Configuring the clock_gen begins with a "Fclk" MHz basic clock.
// To this is applied a prescaler (with value of dds_prescale_value,)
// followed by a Direct Digital Synthesizer (DDS) frequency
// generator. The DDS has an accumulator that is "dds_bits" bits wide.
// The user should know that there is some "jitter" introduced by the
// DDS, and that the amount of jitter varies depending upon the desired
// output frequency. By increasing "dds_bits" the jitter can be made
// very small. Also, the jitter tends to be smaller for small values of
// "dds_phase_increment"
//
// The following settings apply for these table values:
// rate_select BAUD rate (16x this is generated)
//----------------------------------------
// 000 9600
// 001 19200
// 010 38400
// 011 57600
// 100 115200
// (other values are available)
//
//
//
// In order to generate the parameters for a new clock
// frequency, first find the basic Fclk for your board.
// (Fclk=49.152 MHz in this example.)
// Next, choose the lowest desired BAUD rate.
// (lowest_rate=9600 in this example.)
//
// STEP 1 : Find the ratio
//-------------------------
// First, pick a "clock_factor" for the operation of the rs232 units.
// (16 is traditional, although this hardware supports odd values as
// well. For instance, you could pick a clock_factor of 7, if this
// allows you to generate BAUD rates more exactly from your particular
// Fclk. Try to pick the highest clock_factor that you practically can
// since higher numbers allow the receiver to sample in the middle of
// the received bit more exactly... Also, don't go over 16 unless you
// widen out the counters in the design!)
// So, for this example, let clock_factor=16.
//
// Now, find Fclk/(clock_factor*lowest_rate) = 320 (in this example).
// If this ratio is NOT an integer, then be aware that the
// BAUD rates which you will be able to produce will not be
// exact. For asynchronous communications, the clock frequency need not
// be exact. (As mentioned in "Brute Force DDS method" below.)
// If you cannot make clocks close enough to the BAUD rates you desire,
// then you can try a different "clock_factor" setting.
// Or, alternately, you could just use the "Brute Force DDS method."
// (See below)
//
// Or, if all else fails: get a different clock oscillator!
// If the ratio is an integer, or close to it, then proceed to step 2.
//
// Brute Force DDS method (Still step 1):
//-----------------------
// Simply increase the size of the DDS (increase "dds_bits",)
// and set the prescaler to Ndiv=1 (to pass the clock directly
// to the DDS). Then choose your DDS phase increment values (STEP 3)
// so that you can produce rates which are as close as possible
// to "clock_factor" times the desired BAUD rates. It might not be exact,
// but it is as close as possible. If "dds_bits" is sufficiently large,
// then the resulting BAUD rate clocks can be _extremely_ close to the
// correct frequencies. The Baud rate clocks actually do not need
// to be perfect, they can vary by perhaps 3 or 4 percent from their
// exact frequencies, with an increased risk of bit-errors which result,
// of course.
//
// The formula is: dds_freq_int = (2^dds_bits)*(desired_frequency)/Fclk.
//
// STEP 2 : Find the prescaler value
//----------------------------------
// If the ratio mentioned in STEP 1 is an integer, then divide that integer
// into its prime factors. The product of all of the prime factors which
// are not equal to 2 is a good place to start for the prescaler_value.
// If this yields too low of a clock frequency going into the DDS, then
// revert to the "Brute force DDS approach" mentioned above, or else get
// a more suitable clock oscillator!
//
// For this example: 320 = 2*2*2*2*2*2*5. So the prescaler Ndiv = 5.
//
// If you are lucky and the prime factors are all equal to 2, then you have
// chosen an Fclk which is very agreeable to producing the BAUD clocks. You
// can probably set Ndiv=1, which disables the prescaler from operating.
//
//
// STEP 3 : Calculate DDS phase increment values
//----------------------------------------------
// Use the following formula:
// dds_freq_int = (2^dds_bits)*(desired_frequency)/Fclk_dds.
// The resulting values should be used with the DDS, and the values will be
// be "dds_bits-1" wide unsigned quantities.
// Remember that you can change the prescaler Ndiv value to get different
// Fclk_dds values.
//
//=========================================================================
//-----------------------------------------
// This component is a generic clock generator. Simply connect the appropriate
// inputs, and the desired frequency will be the result. Output consists of a
// stream of narrow pulses which are one clock wide. The sizes of DDS and
// prescaler counters are adjustable by parameters.
module clock_gen (
clk,
reset,
frequency,
clk_out
);
parameter DDS_PRESCALE_NDIV_PP = 5; // Prescale divide factor
parameter DDS_PRESCALE_BITS_PP = 3;
parameter DDS_BITS_PP = 6;
input clk;
input reset;
input[DDS_BITS_PP-2:0] frequency;
output clk_out;
// Local signals
wire pulse;
wire dds_clk;
// Simple renaming for readability
wire [DDS_BITS_PP-2:0] dds_phase_increment = frequency;
reg delayed_pulse;
reg [DDS_PRESCALE_BITS_PP-1:0] dds_prescale_count;
reg [DDS_BITS_PP-1:0] dds_phase;
// This is the DDS prescaler part. It has a variable divide value.
// The divide factor is "dds_prescale_ndiv".
always @(posedge clk)
begin
if (reset) dds_prescale_count <= 0;
else if (dds_prescale_count == (DDS_PRESCALE_NDIV_PP-1))
dds_prescale_count <= 0;
else dds_prescale_count <= dds_prescale_count + 1;
end
assign dds_clk = (dds_prescale_count == (DDS_PRESCALE_NDIV_PP-1));
// "dds_prescale_count" above could be compared to zero instead, to save
// on logic?...
// This is the DDS phase accumulator part
always @(posedge clk)
begin
if (reset) dds_phase <= 0;
else if (dds_clk) dds_phase <= dds_phase + dds_phase_increment;
end
assign pulse = dds_phase[DDS_BITS_PP-1]; // Simple renaming for readability
// This is "rising edge detector" part
always @(posedge clk)
begin
delayed_pulse <= pulse;
end
assign clk_out = (pulse && ~delayed_pulse); // Choose the rising edge
endmodule
//-----------------------------------------
// This component is a clock generator with parameters selected by an
// index into a lookup table. There are eight possible settings.
// Recalculate the settings for your own needs as described in
// "FORMULATING BAUD RATE SETTINGS" above. You will need to change
// the bit width of the DDS registers, according to the `defines.
`define DDS_BITS 6
`define DDS_PRESCALE_BITS 3
module clock_gen_select (
clk,
reset,
rate_select,
clk_out
);
input clk;
input reset;
input [2:0] rate_select;
output clk_out;
// Local signals
wire pulse;
wire dds_clk;
reg delayed_pulse;
reg [`DDS_PRESCALE_BITS-1:0] dds_prescale_count;
reg [`DDS_PRESCALE_BITS-1:0] dds_prescale_ndiv;
reg [`DDS_BITS-1:0] dds_phase;
reg [`DDS_BITS-2:0] dds_phase_increment;
// This part sets up the "dds_phase_increment" and "dds_prescale_ndiv" values
always @(rate_select)
begin
case (rate_select)
3'b000 : begin
dds_phase_increment <= 1; // 9600
dds_prescale_ndiv <= 5;
end
3'b001 : begin
dds_phase_increment <= 2; // 19200
dds_prescale_ndiv <= 5;
end
3'b010 : begin
dds_phase_increment <= 4; // 38400
dds_prescale_ndiv <= 5;
end
3'b011 : begin
dds_phase_increment <= 6; // 57600
dds_prescale_ndiv <= 5;
end
3'b100 : begin
dds_phase_increment <= 12; // 115200
dds_prescale_ndiv <= 5;
end
3'b101 : begin
dds_phase_increment <= 12; // 115200
dds_prescale_ndiv <= 5;
end
3'b110 : begin
dds_phase_increment <= 12; // 115200
dds_prescale_ndiv <= 5;
end
3'b111 : begin
dds_phase_increment <= 12; // 115200
dds_prescale_ndiv <= 5;
end
default : begin
dds_phase_increment <= 12; // 115200
dds_prescale_ndiv <= 5;
end
endcase
end
// This is the DDS prescaler part. It has a variable divide value.
// The divide factor is "dds_prescale_ndiv" + 1.
always @(posedge clk)
begin
if (reset) dds_prescale_count <= 0;
else if (dds_prescale_count == (dds_prescale_ndiv-1))
dds_prescale_count <= 0;
else dds_prescale_count <= dds_prescale_count + 1;
end
assign dds_clk = (dds_prescale_count == (dds_prescale_ndiv-1));
// "dds_prescale_count" above could be compared to zero?...
// This is the DDS phase accumulator part
always @(posedge clk)
begin
if (reset) dds_phase <= 0;
else if (dds_clk) dds_phase <= dds_phase + dds_phase_increment;
end
assign pulse = dds_phase[`DDS_BITS-1]; // Simple renaming for readability
// This is "rising edge detector" part
always @(posedge clk)
begin
delayed_pulse <= pulse;
end
assign clk_out = (pulse && ~delayed_pulse); // Choose the rising edge
endmodule
//`undef DDS_BITS
//`undef DDS_PRESCALE_BITS
//-----------------------------------------
// This block takes care of receiving an RS232 input word,
// from the "rxd" line in a serial fashion.
// The user is responsible for providing appropriate CLK
// and clock enable (CE) to achieve the desired Baudot interval
// (NOTE: the state machine operates at "CLOCK_FACTOR_PP" times the
// desired BAUD rate. Set it to anything between 2 and 16,
// inclusive. Values higher than 16 will not "buy" much for you,
// and the state machine might not work well for values less than
// four either, because of the difficulty in sampling rxd at the
// "middle" of the bit time. However, it may be useful to adjust
// the clock_factor around in order to generate good BAUD clocks
// from odd Fclk frequencies on your board.)
// Each time the "word_ready" line drives high the unit has put
// a newly received data word into its output buffer, and is possibly
// already in the process of receiving the next one.
// Note that support is not provided for 1.5 stop bits, only integral
// numbers of stop bits are allowed. However, a selection >2 for
// number of stop bits will still work (it will simply receive
// and count additional stop bits before reporting "word_ready"
module rs232rx (
clk,
rx_clk,
reset,
rxd,
read,
data,
data_ready,
error_over_run,
error_under_run,
error_all_low
);
// Parameter declarations
parameter START_BITS_PP = 1;
parameter DATA_BITS_PP = 8;
parameter STOP_BITS_PP = 1;
parameter CLOCK_FACTOR_PP = 16;
// State encodings, provided as parameters
// for flexibility to the one instantiating the module
parameter m1_idle = 0;
parameter m1_start = 1;
parameter m1_shift = 3;
parameter m1_over_run = 2;
parameter m1_under_run = 4;
parameter m1_all_low = 5;
parameter m1_extra_1 = 6;
parameter m1_extra_2 = 7;
parameter m2_data_ready_flag = 1;
parameter m2_data_ready_ack = 0;
// I/O declarations
input clk;
input rx_clk;
input reset;
input rxd;
input read;
output [DATA_BITS_PP-1:0] data;
output data_ready;
output error_over_run;
output error_under_run;
output error_all_low;
reg [DATA_BITS_PP-1:0] data;
reg data_ready;
reg error_over_run;
reg error_under_run;
reg error_all_low;
// Local signal declarations
`define TOTAL_BITS START_BITS_PP + DATA_BITS_PP + STOP_BITS_PP
wire word_xfer_l;
wire mid_bit_l;
wire start_bit_l;
wire stop_bit_l;
wire all_low_l;
reg [3:0] intrabit_count_l;
reg [`TOTAL_BITS-1:0] q;
reg shifter_preset;
reg [2:0] m1_state;
reg [2:0] m1_next_state;
reg m2_state;
reg m2_next_state;
// State register
always @(posedge clk)
begin : m1_state_register
if (reset) m1_state <= m1_idle;
else m1_state <= m1_next_state;
end
always @(m1_state
or reset
or rxd
or mid_bit_l
or all_low_l
or start_bit_l
or stop_bit_l
)
begin : m1_state_logic
// Output signals are low unless set high in a state condition.
shifter_preset <= 0;
error_over_run <= 0;
error_under_run <= 0;
error_all_low <= 0;
case (m1_state)
m1_idle :
begin
shifter_preset <= 1'b1;
if (~rxd) m1_next_state <= m1_start;
else m1_next_state <= m1_idle;
end
m1_start :
begin
if (~rxd && mid_bit_l) m1_next_state <= m1_shift;
else if (rxd && mid_bit_l) m1_next_state <= m1_under_run;
else m1_next_state <= m1_start;
end
m1_shift :
begin
if (all_low_l) m1_next_state <= m1_all_low;
else if (~start_bit_l && ~stop_bit_l) m1_next_state <= m1_over_run;
else if (~start_bit_l && stop_bit_l) m1_next_state <= m1_idle;
else m1_next_state <= m1_shift;
end
m1_over_run :
begin
error_over_run <= 1;
shifter_preset <= 1'b1;
if (reset) m1_next_state <= m1_idle;
else m1_next_state <= m1_over_run;
end
m1_under_run :
begin
error_under_run <= 1;
shifter_preset <= 1'b1;
if (reset) m1_next_state <= m1_idle;
else m1_next_state <= m1_under_run;
end
m1_all_low :
begin
error_all_low <= 1;
shifter_preset <= 1'b1;
if (reset) m1_next_state <= m1_idle;
else m1_next_state <= m1_all_low;
end
default : m1_next_state <= m1_idle;
endcase
end
assign word_xfer_l = ((m1_state == m1_shift) && ~start_bit_l && stop_bit_l);
// State register
always @(posedge clk)
begin : m2_state_register
if (reset) m2_state <= m2_data_ready_ack;
else m2_state <= m2_next_state;
end
// State transition logic
always @(m2_state or word_xfer_l or read)
begin : m2_state_logic
case (m2_state)
m2_data_ready_ack:
begin
data_ready <= 1'b0;
if (word_xfer_l) m2_next_state <= m2_data_ready_flag;
else m2_next_state <= m2_data_ready_ack;
end
m2_data_ready_flag:
begin
data_ready <= 1'b1;
if (read) m2_next_state <= m2_data_ready_ack;
else m2_next_state <= m2_data_ready_flag;
end
default : m2_next_state <= m2_data_ready_ack;
endcase
end
// This counts within a bit-time.
always @(posedge clk)
begin
if (shifter_preset) intrabit_count_l <= 0;
else if (rx_clk)
begin
if (intrabit_count_l == (CLOCK_FACTOR_PP-1)) intrabit_count_l <= 0;
else intrabit_count_l <= intrabit_count_l + 1;
end
end
// This signal gets one "rx_clk" at the middle of the bit time.
assign mid_bit_l = ((intrabit_count_l==(CLOCK_FACTOR_PP / 2)) && rx_clk);
// This is the shift register
always @(posedge clk)
begin : rxd_shifter
if (shifter_preset) q <= -1; // Set to all ones.
else if (mid_bit_l) q <= {rxd,q[`TOTAL_BITS-1:1]};
end
// Note: The definitions of "start_bit_l" and "stop_bit_l" could
// well be updated to include _all_ of the start and stop bits.
assign start_bit_l = q[0];
assign stop_bit_l = q[`TOTAL_BITS-1];
assign all_low_l = ~(| q); // Bit-wise or of the entire shift register
// This is the output buffer
always @(posedge clk)
begin : rxd_output
if (reset) data <= 0;
else if (word_xfer_l)
data <= q[START_BITS_PP+DATA_BITS_PP-1:START_BITS_PP];
end
endmodule
//`undef TOTAL_BITS
//-----------------------------------------
// This block takes care of framing up an RS232 output word,
// and sending it out the "txd" line in a serial fashion.
// The user is responsible for providing appropriate clk
// and clock enable (tx_clk) to achieve the desired Baudot interval
// (a new bit is transmitted each (tx_clk/clock_factor) pulses)
// (NOTE: the state machine operates at "clock_factor" times the
// desired BAUD rate. Set it to anything between 2 and 16,
// inclusive. It may be useful to adjust the clock_factor in order to
// generate good BAUD clocks from odd Fclk frequencies on your board.)
// A load operation is requested by bringing the "load" line high. However,
// the load will only be accepted when load_request is also high (which
// just happens to coincide with tx_clk_1x inside of the state machine...)
// Therefore, the "load_request" line may be used as a bus acknowledgement.
// (load_request = "ack_o" in Wishbone terminology -- but it only lasts for
// one single clk cycle, so be careful how you use it!)
//
// If the "load_request" line is tied to "load," the unit will send
// data characters continuously, with no gaps in between transmissions.
//
// Note that support is not provided for 1.5 stop bits, only integral
// numbers of stop bits are allowed. A selection of more than 2 for
// number of stop bits will still work fine, it will simply introduce
// a delay between characters being transmitted, although the length
// of the transmitter shift register will also grow to include one
// stage for each stop bit requested...
module rs232tx (
clk,
tx_clk,
reset,
load,
data,
load_request,
txd
);
parameter START_BITS_PP = 1;
parameter DATA_BITS_PP = 8;
parameter STOP_BITS_PP = 1;
parameter CLOCK_FACTOR_PP = 16;
parameter TX_BIT_COUNT_BITS_PP = 4; // = ceil(log(total_bits)/log(2)));
// State encodings, provided as parameters
// for flexibility to the one instantiating the module
parameter m1_idle = 0;
parameter m1_waiting = 1;
parameter m1_sending = 3;
parameter m1_sending_last_bit = 2;
// I/O declarations
input clk;
input tx_clk;
input reset;
input load;
input[DATA_BITS_PP-1:0] data;
output load_request;
output txd;
reg load_request;
// local signals
`define TOTAL_BITS START_BITS_PP + DATA_BITS_PP + STOP_BITS_PP
reg [`TOTAL_BITS-1:0] q; // Actual tx shifter
reg [TX_BIT_COUNT_BITS_PP-1:0] tx_bit_count_l;
reg [3:0] prescaler_count_l;
reg [1:0] m1_state;
reg [1:0] m1_next_state;
wire [`TOTAL_BITS-1:0] tx_word = {{STOP_BITS_PP{1'b1}},
data,
{START_BITS_PP{1'b0}}};
wire begin_last_bit;
wire start_sending;
wire tx_clk_1x;
// This is a prescaler to produce the actual transmit clock.
always @(posedge clk)
begin
if (reset) prescaler_count_l <= 0;
else if (tx_clk)
begin
if (prescaler_count_l == (CLOCK_FACTOR_PP-1)) prescaler_count_l <= 0;
else prescaler_count_l <= prescaler_count_l + 1;
end
end
assign tx_clk_1x = ((prescaler_count_l == (CLOCK_FACTOR_PP-1) ) && tx_clk);
// This is the transmitted bit counter
always @(posedge clk)
begin
if (start_sending) tx_bit_count_l <= 0;
else if (tx_clk_1x)
begin
if (tx_bit_count_l == (`TOTAL_BITS-2)) tx_bit_count_l <= 0;
else tx_bit_count_l <= tx_bit_count_l + 1;
end
end
assign begin_last_bit = ((tx_bit_count_l == (`TOTAL_BITS-2) ) && tx_clk_1x);
assign start_sending = (tx_clk_1x && load);
// This state machine handles sending out the transmit data
// State register.
always @(posedge clk)
begin : state_register
if (reset) m1_state <= m1_idle;
else m1_state <= m1_next_state;
end
// State transition logic
always @(m1_state or tx_clk_1x or load or begin_last_bit)
begin : state_logic
// Signal is low unless changed in a state condition.
load_request <= 0;
case (m1_state)
m1_idle :
begin
load_request <= tx_clk_1x;
if (tx_clk_1x && load) m1_next_state <= m1_sending;
else m1_next_state <= m1_idle;
end
m1_sending :
begin
if (begin_last_bit) m1_next_state <= m1_sending_last_bit;
else m1_next_state <= m1_sending;
end
m1_sending_last_bit :
begin
load_request <= tx_clk_1x;
if (load & tx_clk_1x) m1_next_state <= m1_sending;
else if (tx_clk_1x) m1_next_state <= m1_idle;
else m1_next_state <= m1_sending_last_bit;
end
default :
begin
m1_next_state <= m1_idle;
end
endcase
end
// This is the transmit shifter
always @(posedge clk)
begin : txd_shifter
if (reset) q <= 0; // set output to all ones
else if (start_sending) q <= ~tx_word;
else if (tx_clk_1x) q <= {1'b0,q[`TOTAL_BITS-1:1]};
end
assign txd = ~q[0];
endmodule
|
(************************************************************************)
(* v * The Coq Proof Assistant / The Coq Development Team *)
(* <O___,, * INRIA - CNRS - LIX - LRI - PPS - Copyright 1999-2015 *)
(* \VV/ **************************************************************)
(* // * This file is distributed under the terms of the *)
(* * GNU Lesser General Public License Version 2.1 *)
(************************************************************************)
(** Extraction to Ocaml : use of basic Ocaml types *)
Extract Inductive bool => bool [ true false ].
Extract Inductive option => option [ Some None ].
Extract Inductive unit => unit [ "()" ].
Extract Inductive list => list [ "[]" "( :: )" ].
Extract Inductive prod => "( * )" [ "" ].
(** NB: The "" above is a hack, but produce nicer code than "(,)" *)
(** Mapping sumbool to bool and sumor to option is not always nicer,
but it helps when realizing stuff like [lt_eq_lt_dec] *)
Extract Inductive sumbool => bool [ true false ].
Extract Inductive sumor => option [ Some None ].
(** Restore lazyness of andb, orb.
NB: without these Extract Constant, andb/orb would be inlined
by extraction in order to have lazyness, producing inelegant
(if ... then ... else false) and (if ... then true else ...).
*)
Extract Inlined Constant andb => "(&&)".
Extract Inlined Constant orb => "(||)".
|
// (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:axi_dwidth_converter:2.1
// IP Revision: 11
(* X_CORE_INFO = "axi_dwidth_converter_v2_1_11_top,Vivado 2016.4" *)
(* CHECK_LICENSE_TYPE = "system_auto_us_2,axi_dwidth_converter_v2_1_11_top,{}" *)
(* CORE_GENERATION_INFO = "system_auto_us_2,axi_dwidth_converter_v2_1_11_top,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_dwidth_converter,x_ipVersion=2.1,x_ipCoreRevision=11,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_AXI_PROTOCOL=0,C_S_AXI_ID_WIDTH=1,C_SUPPORTS_ID=0,C_AXI_ADDR_WIDTH=32,C_S_AXI_DATA_WIDTH=32,C_M_AXI_DATA_WIDTH=64,C_AXI_SUPPORTS_WRITE=1,C_AXI_SUPPORTS_READ=0,C_FIFO_MODE=0,C_S_AXI_ACLK_RATIO=1,C_M_AXI_ACLK_RATIO=2,C_AXI_IS_ACLK_ASYNC=0,C_MAX_SPLIT_BEATS=16,C_PACK\
ING_LEVEL=1,C_SYNCHRONIZER_STAGE=3}" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module system_auto_us_2 (
s_axi_aclk,
s_axi_aresetn,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awlock,
s_axi_awcache,
s_axi_awprot,
s_axi_awregion,
s_axi_awqos,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wvalid,
s_axi_wready,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
m_axi_awaddr,
m_axi_awlen,
m_axi_awsize,
m_axi_awburst,
m_axi_awlock,
m_axi_awcache,
m_axi_awprot,
m_axi_awregion,
m_axi_awqos,
m_axi_awvalid,
m_axi_awready,
m_axi_wdata,
m_axi_wstrb,
m_axi_wlast,
m_axi_wvalid,
m_axi_wready,
m_axi_bresp,
m_axi_bvalid,
m_axi_bready
);
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 SI_CLK CLK" *)
input wire s_axi_aclk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 SI_RST RST" *)
input wire s_axi_aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *)
input wire [31 : 0] s_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLEN" *)
input wire [7 : 0] s_axi_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE" *)
input wire [2 : 0] s_axi_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWBURST" *)
input wire [1 : 0] s_axi_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK" *)
input wire [0 : 0] s_axi_awlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE" *)
input wire [3 : 0] s_axi_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWPROT" *)
input wire [2 : 0] s_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREGION" *)
input wire [3 : 0] s_axi_awregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWQOS" *)
input wire [3 : 0] s_axi_awqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *)
input wire s_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *)
output wire s_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *)
input wire [31 : 0] s_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *)
input wire [3 : 0] s_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WLAST" *)
input wire s_axi_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *)
input wire s_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *)
output wire s_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *)
output wire [1 : 0] s_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *)
output wire s_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *)
input wire s_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *)
output wire [31 : 0] m_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLEN" *)
output wire [7 : 0] m_axi_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWSIZE" *)
output wire [2 : 0] m_axi_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWBURST" *)
output wire [1 : 0] m_axi_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLOCK" *)
output wire [0 : 0] m_axi_awlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWCACHE" *)
output wire [3 : 0] m_axi_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWPROT" *)
output wire [2 : 0] m_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREGION" *)
output wire [3 : 0] m_axi_awregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWQOS" *)
output wire [3 : 0] m_axi_awqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *)
output wire m_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *)
input wire m_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *)
output wire [63 : 0] m_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WSTRB" *)
output wire [7 : 0] m_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WLAST" *)
output wire m_axi_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *)
output wire m_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *)
input wire m_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *)
input wire [1 : 0] m_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *)
input wire m_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *)
output wire m_axi_bready;
axi_dwidth_converter_v2_1_11_top #(
.C_FAMILY("zynq"),
.C_AXI_PROTOCOL(0),
.C_S_AXI_ID_WIDTH(1),
.C_SUPPORTS_ID(0),
.C_AXI_ADDR_WIDTH(32),
.C_S_AXI_DATA_WIDTH(32),
.C_M_AXI_DATA_WIDTH(64),
.C_AXI_SUPPORTS_WRITE(1),
.C_AXI_SUPPORTS_READ(0),
.C_FIFO_MODE(0),
.C_S_AXI_ACLK_RATIO(1),
.C_M_AXI_ACLK_RATIO(2),
.C_AXI_IS_ACLK_ASYNC(0),
.C_MAX_SPLIT_BEATS(16),
.C_PACKING_LEVEL(1),
.C_SYNCHRONIZER_STAGE(3)
) inst (
.s_axi_aclk(s_axi_aclk),
.s_axi_aresetn(s_axi_aresetn),
.s_axi_awid(1'H0),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awlen(s_axi_awlen),
.s_axi_awsize(s_axi_awsize),
.s_axi_awburst(s_axi_awburst),
.s_axi_awlock(s_axi_awlock),
.s_axi_awcache(s_axi_awcache),
.s_axi_awprot(s_axi_awprot),
.s_axi_awregion(s_axi_awregion),
.s_axi_awqos(s_axi_awqos),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_awready(s_axi_awready),
.s_axi_wdata(s_axi_wdata),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wlast(s_axi_wlast),
.s_axi_wvalid(s_axi_wvalid),
.s_axi_wready(s_axi_wready),
.s_axi_bid(),
.s_axi_bresp(s_axi_bresp),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_bready(s_axi_bready),
.s_axi_arid(1'H0),
.s_axi_araddr(32'H00000000),
.s_axi_arlen(8'H00),
.s_axi_arsize(3'H0),
.s_axi_arburst(2'H1),
.s_axi_arlock(1'H0),
.s_axi_arcache(4'H0),
.s_axi_arprot(3'H0),
.s_axi_arregion(4'H0),
.s_axi_arqos(4'H0),
.s_axi_arvalid(1'H0),
.s_axi_arready(),
.s_axi_rid(),
.s_axi_rdata(),
.s_axi_rresp(),
.s_axi_rlast(),
.s_axi_rvalid(),
.s_axi_rready(1'H0),
.m_axi_aclk(1'H0),
.m_axi_aresetn(1'H0),
.m_axi_awaddr(m_axi_awaddr),
.m_axi_awlen(m_axi_awlen),
.m_axi_awsize(m_axi_awsize),
.m_axi_awburst(m_axi_awburst),
.m_axi_awlock(m_axi_awlock),
.m_axi_awcache(m_axi_awcache),
.m_axi_awprot(m_axi_awprot),
.m_axi_awregion(m_axi_awregion),
.m_axi_awqos(m_axi_awqos),
.m_axi_awvalid(m_axi_awvalid),
.m_axi_awready(m_axi_awready),
.m_axi_wdata(m_axi_wdata),
.m_axi_wstrb(m_axi_wstrb),
.m_axi_wlast(m_axi_wlast),
.m_axi_wvalid(m_axi_wvalid),
.m_axi_wready(m_axi_wready),
.m_axi_bresp(m_axi_bresp),
.m_axi_bvalid(m_axi_bvalid),
.m_axi_bready(m_axi_bready),
.m_axi_araddr(),
.m_axi_arlen(),
.m_axi_arsize(),
.m_axi_arburst(),
.m_axi_arlock(),
.m_axi_arcache(),
.m_axi_arprot(),
.m_axi_arregion(),
.m_axi_arqos(),
.m_axi_arvalid(),
.m_axi_arready(1'H0),
.m_axi_rdata(64'H0000000000000000),
.m_axi_rresp(2'H0),
.m_axi_rlast(1'H1),
.m_axi_rvalid(1'H0),
.m_axi_rready()
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__DLXTN_BLACKBOX_V
`define SKY130_FD_SC_HDLL__DLXTN_BLACKBOX_V
/**
* dlxtn: Delay latch, inverted enable, single output.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__dlxtn (
Q ,
D ,
GATE_N
);
output Q ;
input D ;
input GATE_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__DLXTN_BLACKBOX_V
|
module top;
reg pass = 1'b1;
reg in;
wire bf1, bf2, nt1, nt2, pd1, pd2, pu1, pu2;
initial begin
// $monitor(bf1, bf2,, nt1, nt2,, pd1, pd2,, pu1, pu2,, in);
if (bf1 !== 1'bx && bf2 !== 1'bx) begin
$display("Buffer failed, expected 2'bxx, got %b%b", bf1, bf2);
pass = 1'b0;
end
if (nt1 !== 1'bx && nt2 !== 1'bx) begin
$display("Inverter (not) failed, expected 2'bxx, got %b%b", nt1, nt2);
pass = 1'b0;
end
if (pd1 !== 1'b0 && pd2 !== 1'b0) begin
$display("Pull down failed, expected 2'b00, got %b%b", pd1, pd2);
pass = 1'b0;
end
if (pu1 !== 1'b1 && pu2 !== 1'b1) begin
$display("Pull up failed, expected 2'b11, got %b%b", pu1, pu2);
pass = 1'b0;
end
in = 1'b0;
#1;
if (bf1 !== 1'b0 && bf2 !== 1'b0) begin
$display("Buffer failed, expected 2'b00, got %b%b", bf1, bf2);
pass = 1'b0;
end
if (nt1 !== 1'b1 && nt2 !== 1'b1) begin
$display("Inverter (not) failed, expected 2'b11, got %b%b", nt1, nt2);
pass = 1'b0;
end
if (pd1 !== 1'b0 && pd2 !== 1'b0) begin
$display("Pull down failed, expected 2'b00, got %b%b", pd1, pd2);
pass = 1'b0;
end
if (pu1 !== 1'b1 && pu2 !== 1'b1) begin
$display("Pull up failed, expected 2'b11, got %b%b", pu1, pu2);
pass = 1'b0;
end
in = 1'b1;
#1;
if (bf1 !== 1'b1 && bf2 !== 1'b1) begin
$display("Buffer failed, expected 2'b11, got %b%b", bf1, bf2);
pass = 1'b0;
end
if (nt1 !== 1'b0 && nt2 !== 1'b0) begin
$display("Inverter (not) failed, expected 2'b00, got %b%b", nt1, nt2);
pass = 1'b0;
end
if (pd1 !== 1'b0 && pd2 !== 1'b0) begin
$display("Pull down failed, expected 2'b00, got %b%b", pd1, pd2);
pass = 1'b0;
end
if (pu1 !== 1'b1 && pu2 !== 1'b1) begin
$display("Pull up failed, expected 2'b11, got %b%b", pu1, pu2);
pass = 1'b0;
end
if (pass) $display("PASSED");
end
buf (bf1, bf2, in);
not (nt1, nt2, in);
pulldown (pd1, pd2);
pullup (pu1, pu2);
endmodule
|
//////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2013, Andrew "bunnie" Huang
//
// See the NOTICE file distributed with this work for additional
// information regarding copyright ownership. The copyright holder
// licenses this file to you under the Apache License, Version 2.0
// (the "License"); you may not use this file except in compliance
// with the License. You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing,
// code distributed under the License is distributed on an
// "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
// KIND, either express or implied. See the License for the
// specific language governing permissions and limitations
// under the License.
//////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
module nand_log(
input wire bclk, // 133 Mhz clock
input wire clk100, // 100 Mhz clock
input wire nand_re,
input wire nand_we,
input wire nand_ale,
input wire nand_cle,
input wire nand_cs,
input wire nand_rb,
input wire [7:0] nand_din,
input wire [9:0] nand_uk,
input wire log_reset,
input wire log_run,
output reg log_cmd_error, // stuck high if cmd fifo overflowed during logging
output reg log_data_error, // stuck high if data fifo overflowed during logging
output reg [26:0] log_entries, // number of entries currently in the log
output wire [3:0] ddr3_wr_mask,
output wire [31:0] ddr3_wr_data,
output wire ddr3_wr_en,
input wire ddr3_wr_full,
input wire ddr3_wr_empty,
input wire [6:0] ddr3_wr_count,
output wire ddr3_cmd_clk,
output wire [2:0] ddr3_cmd_instr,
output wire ddr3_cmd_en,
output wire [5:0] ddr3_cmd_burstlen,
output wire [29:0] ddr3_cmd_addr,
input wire ddr3_cmd_full,
input wire ddr3_cmd_empty,
output wire [63:0] time_t_clk100, // note synched to clk100
input wire reset
);
wire bclk_reset, clk100_reset;
sync_reset log_bclk_res_sync( .glbl_reset(reset), .clk(bclk), .reset(bclk_reset) );
sync_reset log_clk100_res_sync( .glbl_reset(reset), .clk(clk100), .reset(clk100_reset) );
reg [7:0] cap_wr_din;
reg [9:0] cap_wr_uk;
reg cap_wr_ale;
reg cap_wr_cle;
reg cap_wr_cs;
reg cap_wr_rb;
reg [7:0] cap_rd_din;
reg [9:0] cap_rd_uk;
reg cap_rd_ale;
reg cap_rd_cle;
reg cap_rd_cs;
reg cap_rd_rb;
reg [7:0] log_din;
reg [9:0] log_uk;
reg log_ale;
reg log_cle;
reg log_cs;
reg log_rb;
reg log_we;
reg log_re;
reg log_capture_pulse; // whenever this goes high, grab the log_* data
wire cap_we;
wire cap_re;
reg cap_wed2, cap_wed1, cap_wedA;
reg cap_red2, cap_red1, cap_redA;
wire time_we;
wire time_re;
////////////
// Sync the asynchronous NAND data into the bclk domain
//
// 1. capture data with the rising edges of the NAND we, re signals
// 2. sync NAND we, re into bclk domain
// 3. detect rising edges of we, re
// 4. use rising edges to latch captured data
// why this works:
// the data capture stabilizes the data busses for long periods of time
// as long as the pulse detection on the we, re signals is shorter than the
// min cycle length of the NAND, we will always be guaranteed to grab "good"
// data from the capture registers.
// bclk runs at 133 MHz -> 7.5ns cycle length
// pulse occurs max two cycles later, which is 15ns: shortest we, re cycle time is 25 ns.
// so we should be 100% solid on the data captures.
////////////
always @(posedge nand_we) begin
cap_wr_din[7:0] <= nand_din[7:0];
cap_wr_uk[9:0] <= nand_uk[9:0];
cap_wr_ale <= nand_ale;
cap_wr_cle <= nand_cle;
cap_wr_cs <= nand_cs;
cap_wr_rb <= nand_rb;
end
always @(posedge nand_re) begin
cap_rd_din[7:0] <= nand_din[7:0];
cap_rd_uk[9:0] <= nand_uk[9:0];
cap_rd_ale <= nand_ale;
cap_rd_cle <= nand_cle;
cap_rd_cs <= nand_cs;
cap_rd_rb <= nand_rb;
end
always @(posedge bclk) begin
// cap_wedA <= nand_we; // extra stage for synching into local clock domain
// cap_redA <= nand_re;
// cap_wed1 <= cap_wedA;
// cap_red1 <= cap_redA;
cap_wed1 <= nand_we;
cap_red1 <= nand_re;
cap_wed2 <= cap_wed1;
cap_red2 <= cap_red1;
end
assign cap_we = !cap_wed2 & cap_wed1; // rising edge pulse gen
assign cap_re = !cap_red2 & cap_red1;
/////////
// capture a single entry of log information on rising edges of we, re, synchronized to bclk
/////////
always @(posedge bclk) begin
log_capture_pulse <= cap_we || cap_re;
if( cap_we ) begin
log_din <= cap_wr_din;
log_uk <= cap_wr_uk;
log_ale <= cap_wr_ale;
log_cle <= cap_wr_cle;
log_cs <= cap_wr_cs;
log_rb <= cap_wr_rb;
log_we <= 1'b0; // we is active low
log_re <= 1'b1;
end else if( cap_re ) begin
log_din <= cap_rd_din;
log_uk <= cap_rd_uk;
log_ale <= cap_rd_ale;
log_cle <= cap_rd_cle;
log_cs <= cap_rd_cs;
log_rb <= cap_rd_rb;
log_we <= 1'b1;
log_re <= 1'b0; // re is active low
end else begin
log_din <= log_din;
log_uk <= log_uk;
log_ale <= log_ale;
log_cle <= log_cle;
log_cs <= log_cs;
log_rb <= log_rb;
log_we <= log_we;
log_re <= log_re;
end // else: !if( cap_re )
end // always @ (posedge bclk)
/*
* PACKET_NAND_CYCLE format (FPGA):
* Offset | Size | Description
* --------+------+-------------
* 0 | 11 | Header
* 11 | 1 | Data/Command pins
* 12 | 1 | Bits [0..4] are ALE, CLE, WE, RE, and CS (in order)
* 13 | 2 | Bits [0..9] are the unknown pins
*/
wire [22:0] ddr3_log_data;
reg [40:0] ddr3_log_time; // this gives us up to 8.5 minutes of monotonic logging with ns-resolution
wire [63:0] ddr3_log_entry;
reg [63:0] time_t_clk100_cap;
////// grabbing time_t in a synchronized fashion to bclk:
// time_t_clk100 is frozen on the *falling* edge of we_re, yet
// ddr3_log_time is captured on the *rising* edge of we, re; thereby avoiding
// a synchronization problem trying to grab a fast-moving counter value
always @(posedge bclk) begin
if( cap_we || cap_re ) begin
ddr3_log_time[40:0] <= time_t_clk100_cap[40:0];
end else begin
ddr3_log_time <= ddr3_log_time;
end
end
assign ddr3_log_data[7:0] = log_din[7:0];
assign ddr3_log_data[8] = log_ale;
assign ddr3_log_data[9] = log_cle;
assign ddr3_log_data[10] = log_we;
assign ddr3_log_data[11] = log_re;
assign ddr3_log_data[12] = log_cs;
// note 3 bits are filled in here...cut them out at the final register output stage
assign ddr3_log_data[22:13] = log_uk[9:0];
assign ddr3_log_entry[63:0] = {ddr3_log_time, ddr3_log_data};
/////////
// now mux log time, data into the DDR3 memory
/////////
parameter LOG_DATA = 4'b1 << 0;
parameter LOG_TIME = 4'b1 << 1;
parameter LOG_nSTATES = 4;
reg [(LOG_nSTATES - 1):0] cstate;
reg [(LOG_nSTATES - 1):0] nstate;
always @(posedge bclk or posedge bclk_reset) begin
if( bclk_reset ) begin
cstate <= LOG_DATA; // async reset
end else if( log_reset ) begin
cstate <= LOG_DATA; // sync reset
end else begin
cstate <= nstate;
end
end
always @(*) begin
case (cstate)
LOG_DATA: begin
if( log_capture_pulse ) begin
nstate <= LOG_TIME;
end else begin
nstate <= LOG_DATA;
end
end
LOG_TIME: begin
nstate <= LOG_DATA;
end
endcase // case (cstate)
end
/// this is a no-op right now, fortunately the synthesis tool doesn't care
always @(posedge bclk) begin
if( log_reset ) begin
// set things to zero
end else begin
case (cstate)
LOG_DATA: begin
if( log_capture_pulse ) begin
// hmmm...
end
// do stuff based upon the current state
end
endcase // case (cstate)
end
end
reg [29:0] log_address;
reg cmd_delay;
reg cmd_flush; // used to advance the command queue to flush the DDR3 fifos
assign ddr3_cmd_clk = bclk;
assign ddr3_wr_data = (cstate == LOG_DATA) ? ddr3_log_entry[31:0] : ddr3_log_entry[63:32];
assign ddr3_wr_mask = 4'b0; // never mask
assign ddr3_wr_en = (((cstate == LOG_DATA) && log_capture_pulse) || (cstate == LOG_TIME)) &
log_run;
assign ddr3_cmd_instr = 3'b000; // hard-wired to a write command
assign ddr3_cmd_burstlen = 6'h1; // write two words in a burst
assign ddr3_cmd_en = cmd_delay & log_run | cmd_flush;
assign ddr3_cmd_addr = log_address;
reg still_resetting;
always @(posedge bclk) begin
cmd_delay <= (cstate == LOG_TIME); // issue command enable one cycle after writes are done
if( log_reset ) begin
log_address <= 30'h0F00_0000; // start log at high memory, 16 megs from top
log_entries <= 27'h0;
end else if( cmd_delay ) begin
if( log_address < 30'h0FFF_FFF8 ) begin
log_address <= log_address + 30'h8; // 64 bits written = 8 bytes
end else begin
log_address <= log_address; // just keep owerwriting the last spot in case of overflow
end
log_entries <= log_entries + 27'h1; // if entries > 16 MB then we've overflowed
end else begin
log_address <= log_address;
log_entries <= log_entries;
end
// catch if the command fifo ever overflows
if( log_reset ) begin
log_cmd_error <= 1'b0;
end else if( ddr3_cmd_full ) begin
log_cmd_error <= 1'b1;
end else begin
log_cmd_error <= log_cmd_error;
end
// catch if the data fifo ever overflows
// work around condition where fifo shows full during and slightly after reset
if( log_reset ) begin
log_data_error <= 1'b0;
still_resetting <= 1'b1;
end else if( still_resetting & ddr3_wr_full ) begin
still_resetting <= 1'b1;
log_data_error <= 1'b0;
end else if( !still_resetting & ddr3_wr_full ) begin
log_data_error <= 1'b1;
still_resetting <= 1'b0;
end else begin
log_data_error <= log_data_error;
still_resetting <= 1'b0;
end
end // always @ (posedge bclk)
/////////
// time_t generator: synchcronized to clk100
// also includes capture of time on falling-edge of we, re to aid synchronization to logs
// value is passed up to the register interface to the CPU, but the synchronization
// problem has to be solved there, too!
/////////
reg [31:0] time_ns;
reg [31:0] time_s;
reg log_reset_clk100;
reg log_run_clk100;
wire time_we_clk100;
wire time_re_clk100;
reg clk100_wed1, clk100_wed2;
reg clk100_red1, clk100_red2;
assign time_we_clk100 = clk100_wed2 & !clk100_wed1; // falling edge pulse gen
assign time_re_clk100 = clk100_red2 & !clk100_red1;
always @(posedge clk100) begin
// local clock sync
log_reset_clk100 <= log_reset;
log_run_clk100 <= log_run;
clk100_wed1 <= nand_we;
clk100_red1 <= nand_re;
clk100_wed2 <= clk100_wed1;
clk100_red2 <= clk100_red1;
// time_t_clk100_cap is updated only on the *falling* edge of we, re
if( time_we_clk100 || time_re_clk100 ) begin
time_t_clk100_cap <= {time_s, time_ns};
end else begin
time_t_clk100_cap <= time_t_clk100_cap;
end
if( log_reset_clk100 ) begin
time_ns <= 32'b0;
time_s <= 32'b0;
end else begin
if( log_run_clk100 ) begin
if( time_ns < 32'd999_999_999 ) begin // count up to only a billion
time_ns <= time_ns + 32'd10; // increment by 10ns (100 MHz clock rate)
time_s <= time_s;
end else begin
time_ns <= 32'd0;
time_s <= time_s + 32'd1;
end
end else begin
time_ns <= time_ns;
time_s <= time_s;
end // else: !if( log_run_clk100 )
end // else: !if( log_reset_clk100 )
end // always @ (posedge clk100)
assign time_t_clk100 = {time_s, time_ns};
endmodule // nand_log
|
////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2004 Xilinx, Inc.
// All Rights Reserved
////////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: 1.01
// \ \ Filename: uart_rx.v
// / / Date Last Modified: 08/04/2004
// /___/ /\ Date Created: 10/16/2002
// \ \ / \
// \___\/\___\
//
//Device: Xilinx
//Purpose:
// UART Receiver with integral 16 byte FIFO buffer
// 8 bit, no parity, 1 stop bit
//Reference:
// None
//Revision History:
// Rev 1.00 - kc - Start of design entry in VHDL, 10/16/2002.
// Rev 1.01 - sus - Converted to verilog, 08/04/2004.
////////////////////////////////////////////////////////////////////////////////
// Contact: e-mail [email protected]
//////////////////////////////////////////////////////////////////////////////////
//
// Disclaimer:
// LIMITED WARRANTY AND DISCLAIMER. These designs are
// provided to you "as is". Xilinx and its licensors make and you
// receive no warranties or conditions, express, implied,
// statutory or otherwise, and Xilinx specifically disclaims any
// implied warranties of merchantability, non-infringement, or
// fitness for a particular purpose. Xilinx does not warrant that
// the functions contained in these designs will meet your
// requirements, or that the operation of these designs will be
// uninterrupted or error free, or that defects in the Designs
// will be corrected. Furthermore, Xilinx does not warrant or
// make any representations regarding use or the results of the
// use of the designs in terms of correctness, accuracy,
// reliability, or otherwise.
//
// LIMITATION OF LIABILITY. In no event will Xilinx or its
// licensors be liable for any loss of data, lost profits, cost
// or procurement of substitute goods or services, or for any
// special, incidental, consequential, or indirect damages
// arising from the use or operation of the designs or
// accompanying documentation, however caused and on any theory
// of liability. This limitation will apply even if Xilinx
// has been advised of the possibility of such damage. This
// limitation shall apply not-withstanding the failure of the
// essential purpose of any limited remedies herein.
//////////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1ps
module uart_rx
( serial_in,
data_out,
read_buffer,
reset_buffer,
en_16_x_baud,
buffer_data_present,
buffer_full,
buffer_half_full,
clk);
input serial_in;
output[7:0] data_out;
input read_buffer;
input reset_buffer;
input en_16_x_baud;
output buffer_data_present;
output buffer_full;
output buffer_half_full;
input clk;
wire serial_in;
wire [7:0] data_out;
wire read_buffer;
wire reset_buffer;
wire en_16_x_baud;
wire buffer_data_present;
wire buffer_full;
wire buffer_half_full;
wire clk;
//----------------------------------------------------------------------------------
//
// Start of Main UART_RX
//
//
//----------------------------------------------------------------------------------
//
// Signals used in UART_RX
//
//----------------------------------------------------------------------------------
//
wire [7:0] uart_data_out;
wire fifo_write;
//
//----------------------------------------------------------------------------------
//
// Start of UART_RX circuit description
//
//----------------------------------------------------------------------------------
//
// 8 to 1 multiplexer to convert parallel data to serial
kcuart_rx kcuart
( .serial_in(serial_in),
.data_out(uart_data_out),
.data_strobe(fifo_write),
.en_16_x_baud(en_16_x_baud),
.clk(clk));
bbfifo_16x8 buf_0
( .data_in(uart_data_out),
.data_out(data_out),
.reset(reset_buffer),
.write(fifo_write),
.read(read_buffer),
.full(buffer_full),
.half_full(buffer_half_full),
.data_present(buffer_data_present),
.clk(clk));
endmodule
//----------------------------------------------------------------------------------
//
// END OF FILE uart_rx.v
//
//----------------------------------------------------------------------------------
|
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